From 814c8657cb5cc207ec0f04fc2af133ec90e6e5f6 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 14 Feb 2020 13:18:06 +0800 Subject: [PATCH 0001/1463] vboot: fix up some includes These header files need to make use of vb2_shared_data. Remove the last vestiges of vboot1 data structures in coreboot. BUG=b:124141368, chromium:1038260 TEST=Build locally with CL:2054269 TEST=make clean && make test-abuild BRANCH=none Change-Id: I61b27e33751c11aac9f8af261a75d83b003b5f92 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/38884 Reviewed-by: Hung-Te Lin Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/security/vboot/ec_sync.c | 1 + src/security/vboot/misc.h | 4 +--- src/security/vboot/vboot_common.h | 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index ecceff50f9..f4f9c23976 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -23,6 +23,7 @@ #include #include #include +#include #define _EC_FILENAME(select, suffix) \ (select == VB_SELECT_FIRMWARE_READONLY ? "ecro" suffix : "ecrw" suffix) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 2d5b0845d1..324af5ca11 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -18,9 +18,7 @@ #include #include - -struct vb2_context; -struct vb2_shared_data; +#include /* * Source: security/vboot/common.c diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 976c26a70b..57f3475adb 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -17,8 +17,7 @@ #include #include -#include -#include +#include /* * Function to check if there is a request to enter recovery mode. Returns From b1f1ee38d57094a0cd90e1683fe479d94d184b30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 10 Feb 2020 20:58:50 +0100 Subject: [PATCH 0002/1463] mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Thus drop the remaining settings. Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38817 Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../variants/x11ssh-tf/overridetree.cb | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 3d46fe02a7..f481c77bda 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -114,14 +114,8 @@ chip soc/intel/skylake end device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO - device pnp 2e.b off # SUART3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.c off # SUART4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 device pnp 2e.d on end # iLPC2AHB device pnp 2e.e on # Mailbox io 0x60 = 0xa40 From 68241737044a9aade46346538729e9e3813551f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 10 Feb 2020 19:21:22 +0100 Subject: [PATCH 0003/1463] mainboard/supermicro: x11ssm-f: disable SUART3/4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Further they break the console for an unknown reason. Thus disable them. Change-Id: I30bb8184d03ee1037d9ec33eb1d93ee540563fc5 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38818 Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../variants/x11ssm-f/overridetree.cb | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index ea90e0b0ba..0c7c17fffe 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -10,8 +10,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - register "gen3_dec" = "0x000c03e1" # UART3 - register "gen4_dec" = "0x000c02e1" # UART4 # PCIe configuration register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 @@ -103,14 +101,8 @@ chip soc/intel/skylake end device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO - device pnp 2e.b on # SUART3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.c on # SUART4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 device pnp 2e.d on end # iLPC2AHB device pnp 2e.e on # Mailbox io 0x60 = 0xa40 From 611ec48c1db12bad4cbe5bbfde2eb116887971d0 Mon Sep 17 00:00:00 2001 From: Usha P Date: Mon, 3 Feb 2020 18:39:57 +0530 Subject: [PATCH 0004/1463] soc/intel/tigerlake: Update Kconfig related to JSL Update Kconfig: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE 2. Update the right value of MAX_ROOT_PORTS and MAX_PCIE_CLOCKS for SOC_INTEL_JASPERLAKE Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/38678 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0e33..1b90d4b365 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,7 @@ config SOC_INTEL_TIGERLAKE config SOC_INTEL_JASPERLAKE bool select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM help Intel Jasperlake support @@ -113,13 +113,13 @@ config HEAP_SIZE config MAX_ROOT_PORTS int - default 16 if SOC_INTEL_JASPERLAKE + default 8 if SOC_INTEL_JASPERLAKE default 12 if SOC_INTEL_TIGERLAKE config MAX_PCIE_CLOCKS int default 7 if SOC_INTEL_TIGERLAKE - default 16 if SOC_INTEL_JASPERLAKE + default 6 if SOC_INTEL_JASPERLAKE config SMM_TSEG_SIZE hex From 77eaecf06b238157decfe19fea02eadfa71a9436 Mon Sep 17 00:00:00 2001 From: Usha P Date: Tue, 4 Feb 2020 11:24:25 +0530 Subject: [PATCH 0005/1463] soc/intel/tigerlake: Update PMC Register Base and platform check for JSP Change: 1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP 2. Platform check in espi.c BUG=None TEST= 1. Test for JSL RVP Boot 2. Verify PMC register values are valid for GEN_PMCON and GBLRST_CAUSE from the coreboot console logs. Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1 Signed-off-by: Usha P Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704 Reviewed-by: Rizwan Qureshi Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/bootblock/pch.c | 2 +- src/soc/intel/tigerlake/espi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 1654809a6b..cd264d682c 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -41,7 +41,7 @@ #include #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100 -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index d07a582a32..7efd210cad 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -83,7 +83,7 @@ uint8_t get_pch_series(void) if (lpc_did_hi_byte == 0xA0) return PCH_TGP; - else if (lpc_did_hi_byte == 0x38) + else if (lpc_did_hi_byte == 0x4d) return PCH_JSP; else return PCH_UNKNOWN_SERIES; From 0e61a53b06bf0f1f0eba7a85e0a19fec97375717 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 13 Feb 2020 22:07:00 +0530 Subject: [PATCH 0006/1463] soc/tigerlake: Update xhci ACPI files for JSP ACPI files for xhci in JSL is different from TGL. Hence, renaming xhci.asl to xhci_tgl.asl and adding a new file xhci_jsl.asl for JSL. Also, allowing xhci.asl to choose the correct file based on the SoC selected. BUG=None BRANCH=None TEST=Compilation for JasperLake board is working Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/38880 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/acpi/xhci.asl | 55 +++----------------- src/soc/intel/tigerlake/acpi/xhci_jsl.asl | 63 +++++++++++++++++++++++ src/soc/intel/tigerlake/acpi/xhci_tgl.asl | 63 +++++++++++++++++++++++ 3 files changed, 132 insertions(+), 49 deletions(-) create mode 100644 src/soc/intel/tigerlake/acpi/xhci_jsl.asl create mode 100644 src/soc/intel/tigerlake/acpi/xhci_tgl.asl diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl index 312cc5a88e..9618cf3003 100644 --- a/src/soc/intel/tigerlake/acpi/xhci.asl +++ b/src/soc/intel/tigerlake/acpi/xhci.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,51 +13,8 @@ * GNU General Public License for more details. */ -#include - -/* XHCI Controller 0:14.0 */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - - Name (_PRW, Package () { GPE0_PME_B0, 3 }) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Method (_PS0, 0, Serialized) - { - - } - - Method (_PS3, 0, Serialized) - { - - } - - /* Root Hub for Tigerlake-LP PCH */ - Device (RHUB) - { - Name (_ADR, Zero) - - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - Device (HS09) { Name (_ADR, 9) } - Device (HS10) { Name (_ADR, 10) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 13) } - Device (SS02) { Name (_ADR, 14) } - Device (SS03) { Name (_ADR, 15) } - Device (SS04) { Name (_ADR, 16) } - } -} +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "xhci_tgl.asl" +#else + #include "xhci_jsl.asl" +#endif diff --git a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl new file mode 100644 index 0000000000..fe17b0d1bf --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Jasperlake PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 9) } + Device (SS02) { Name (_ADR, 10) } + Device (SS03) { Name (_ADR, 11) } + Device (SS04) { Name (_ADR, 12) } + Device (SS05) { Name (_ADR, 13) } + Device (SS06) { Name (_ADR, 14) } + } +} diff --git a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl new file mode 100644 index 0000000000..312cc5a88e --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Tigerlake-LP PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + } +} From e921911f1008169d236c4d2bd3e169a176cdf45c Mon Sep 17 00:00:00 2001 From: Usha P Date: Mon, 3 Feb 2020 18:54:19 +0530 Subject: [PATCH 0007/1463] mb/intel/jasperlake_rvp: Enable only required PCIE root ports Jasper Lake SOC has 8 PCIe root ports. Cleaning up the root ports as per Jasper Lake. This patch updates the devicetree to enable WLAN and NVME for jasperlake_rvp and removes the other root port configurations which are not required. Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367 Signed-off-by: Usha P Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/38679 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- .../variants/jslrvp/devicetree.cb | 87 +++++-------------- 1 file changed, 22 insertions(+), 65 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 854df4656b..fb636251da 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -48,56 +48,23 @@ chip soc/intel/tigerlake register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "0" - register "PcieRpEnable[2]" = "0" - register "PcieRpEnable[3]" = "0" + # PCIe port 1 for M.2 E-key WLAN + register "PcieRpEnable[1]" = "1" + + # RP 1 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "0x01" + + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "0x01" + + # Enable Root Port 4(x4) for NVMe register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieClkSrcUsage[0]" = "2" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "0xE" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" + # RP 4 uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "0x04" - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" + # ClkReq-to-ClkSrc mapping for CLK SRC 0 + register "PcieClkSrcClkReq[0]" = "0x00" register "SataEnable" = "1" register "SataSalpSupport" = "1" @@ -294,24 +261,14 @@ chip soc/intel/tigerlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 From 81726663bcfe07234eb286ec5eddbff5e55be813 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Sat, 8 Feb 2020 12:23:23 +0800 Subject: [PATCH 0008/1463] vboot: push clear recovery mode switch until BS_WRITE_TABLES Serves two purposes: (1) On some platforms, FSP initialization may cause a reboot. Push clearing the recovery mode switch until after FSP code runs, so that a manual recovery request (three-finger salute) will function correctly under this condition. (2) The recovery mode switch value is needed at BS_WRITE_TABLES for adding an event to elog. (Previously this was done by stashing the value in CBMEM_ID_EC_HOSTEVENT.) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/commonlib/include/commonlib/cbmem_id.h | 2 +- src/ec/google/chromeec/ec.c | 35 ---------------------- src/ec/google/chromeec/switches.c | 30 +++++++++++-------- src/include/bootmode.h | 1 - src/mainboard/intel/galileo/vboot.c | 10 ------- src/mainboard/intel/kblrvp/chromeos.c | 10 ------- src/security/vboot/bootmode.c | 19 ++++++++++-- src/security/vboot/vboot_logic.c | 25 ---------------- 8 files changed, 34 insertions(+), 98 deletions(-) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index b063cd1937..93d1464f1b 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -72,7 +72,7 @@ #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 #define CBMEM_ID_VPD 0x56504420 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 -#define CBMEM_ID_EC_HOSTEVENT 0x63ccbbc3 +#define CBMEM_ID_EC_HOSTEVENT 0x63ccbbc3 /* deprecated */ #define CBMEM_ID_EXT_VBT 0x69866684 #define CBMEM_ID_ROM0 0x524f4d30 #define CBMEM_ID_ROM1 0x524f4d31 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 4bf41ac119..1d351c5875 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -81,41 +81,6 @@ static const struct { }, }; -void log_recovery_mode_switch(void) -{ - uint64_t *events; - - if (cbmem_find(CBMEM_ID_EC_HOSTEVENT)) - return; - - events = cbmem_add(CBMEM_ID_EC_HOSTEVENT, sizeof(*events)); - if (!events) - return; - - *events = google_chromeec_get_events_b(); -} - -static void google_chromeec_elog_add_recovery_event(void *unused) -{ - uint64_t *events = cbmem_find(CBMEM_ID_EC_HOSTEVENT); - uint8_t event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY; - - if (!events) - return; - - if (!(*events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY))) - return; - - if (*events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)) - event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT; - - elog_add_event_byte(ELOG_TYPE_EC_EVENT, event_byte); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - google_chromeec_elog_add_recovery_event, NULL); - uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) { int csum; diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 3fd38084f6..1eb2f2f6ef 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -14,8 +14,8 @@ */ #include -#include #include +#include #if CONFIG(EC_GOOGLE_CHROMEEC_LPC) int get_lid_switch(void) @@ -41,29 +41,33 @@ int get_recovery_mode_switch(void) int get_recovery_mode_retrain_switch(void) { - uint64_t events; - const uint64_t mask = - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT); - /* * Check if the EC has posted the keyboard recovery event with memory * retrain. */ - events = google_chromeec_get_events_b(); + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); +} - if (cbmem_possibly_online()) { - const uint64_t *events_save; +static void elog_add_recovery_mode_switch_event(void) +{ + uint64_t events = google_chromeec_get_events_b(); + uint8_t event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY; - events_save = cbmem_find(CBMEM_ID_EC_HOSTEVENT); - if (events_save != NULL) - events |= *events_save; - } + if (!(events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY))) + return; - return !!(events & mask); + if (events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)) + event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT; + + elog_add_event_byte(ELOG_TYPE_EC_EVENT, event_byte); } int clear_recovery_mode_switch(void) { + /* Log elog event before clearing */ + elog_add_recovery_mode_switch_event(); + /* Clear all host event bits requesting recovery mode. */ return google_chromeec_clear_events_b( EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 33148dcd56..3ae87461a9 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -22,7 +22,6 @@ int get_write_protect_state(void); int get_recovery_mode_switch(void); int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); -void log_recovery_mode_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 8b6706c15c..3ec5bb3b44 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -24,12 +24,6 @@ #include "gen1.h" #include "gen2.h" -int clear_recovery_mode_switch(void) -{ - /* Nothing to do */ - return 0; -} - int get_recovery_mode_switch(void) { return 0; @@ -41,10 +35,6 @@ int get_write_protect_state(void) return 0; } -void log_recovery_mode_switch(void) -{ -} - void verstage_mainboard_init(void) { const struct reg_script *script; diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 9db46744bc..647a4302b2 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -62,16 +62,6 @@ int get_recovery_mode_switch(void) return 0; } -int clear_recovery_mode_switch(void) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - /* Clear keyboard recovery event. */ - return google_chromeec_clear_events_b( - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); - - return 0; -} - int get_write_protect_state(void) { /* No write protect */ diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 83baa815c7..2a911cbf10 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -101,14 +101,27 @@ int vboot_recovery_mode_enabled(void) int __weak clear_recovery_mode_switch(void) { - // Weak implementation. Nothing to do. return 0; } -void __weak log_recovery_mode_switch(void) +static void do_clear_recovery_mode_switch(void *unused) { - // Weak implementation. Nothing to do. + if (vboot_get_context()->flags & VB2_CONTEXT_FORCE_RECOVERY_MODE) + clear_recovery_mode_switch(); } +/* + * The recovery mode switch (typically backed by EC) is not cleared until + * BS_WRITE_TABLES for two reasons: + * + * (1) On some platforms, FSP initialization may cause a reboot. Push clearing + * the recovery mode switch until after FSP code runs, so that a manual recovery + * request (three-finger salute) will function correctly under this condition. + * + * (2) To give the implementation of clear_recovery_mode_switch a chance to + * add an event to elog. See the function in chromeec/switches.c. + */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + do_clear_recovery_mode_switch, NULL); int __weak get_recovery_mode_retrain_switch(void) { diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 182128c547..18c96d77ff 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -248,26 +248,6 @@ static uint32_t extend_pcrs(struct vb2_context *ctx) vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); } -static void vboot_log_and_clear_recovery_mode_switch(int unused) -{ - /* Log the recovery mode switches if required, before clearing them. */ - log_recovery_mode_switch(); - - /* - * The recovery mode switch is cleared (typically backed by EC) here - * to allow multiple queries to get_recovery_mode_switch() and have - * them return consistent results during the verified boot path as well - * as dram initialization. x86 systems ignore the saved dram settings - * in the recovery path in order to start from a clean slate. Therefore - * clear the state here since this function is called when memory - * is known to be up. - */ - clear_recovery_mode_switch(); -} -#if !CONFIG(VBOOT_STARTS_IN_ROMSTAGE) -ROMSTAGE_CBMEM_INIT_HOOK(vboot_log_and_clear_recovery_mode_switch) -#endif - /** * Verify and select the firmware in the RW image * @@ -428,11 +408,6 @@ void verstage_main(void) vboot_is_firmware_slot_a(ctx) ? 'A' : 'B'); verstage_main_exit: - /* If CBMEM is not up yet, let the ROMSTAGE_CBMEM_INIT_HOOK take care - of running this function. */ - if (ENV_ROMSTAGE && CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) - vboot_log_and_clear_recovery_mode_switch(0); - /* Save recovery reason in case of unexpected reboots on x86. */ vboot_save_recovery_reason_vbnv(); From 56e2f130a64c9da6319631c19d452e0db978e70b Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Sat, 8 Feb 2020 11:17:57 +0800 Subject: [PATCH 0009/1463] vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT option With CL:1940398, this option is no longer needed. Recovery requests are not cleared until kernel verification stage is reached. If the FSP triggers any reboots, recovery requests will be preserved. In particular: - Manual requests will be preserved via recovery switch state, whose behaviour is modified in CB:38779. - Other recovery requests will remain in nvdata across reboot. These functions now only work after verstage has run: int vboot_check_recovery_request(void) int vboot_recovery_mode_enabled(void) int vboot_developer_mode_enabled(void) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780 Reviewed-by: Julius Werner Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/security/vboot/Kconfig | 8 ---- src/security/vboot/bootmode.c | 80 ++++---------------------------- src/security/vboot/misc.h | 5 -- src/security/vboot/vbnv.c | 20 -------- src/security/vboot/vbnv.h | 2 - src/security/vboot/vboot_logic.c | 3 -- src/soc/amd/stoneyridge/Kconfig | 1 - src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/icelake/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - src/soc/intel/tigerlake/Kconfig | 1 - 12 files changed, 10 insertions(+), 114 deletions(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ea70e65256..54e88dd594 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -156,14 +156,6 @@ config VBOOT_RETURN_FROM_VERSTAGE reused by the succeeding stage. This is useful if a RAM space is too small to fit both the verstage and the succeeding stage. -config VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT - bool - default n - help - This option ensures that the recovery request is not lost because of - reboots caused after vboot verification is run. e.g. reboots caused by - FSP components on Intel platforms. - config VBOOT_MUST_REQUEST_DISPLAY bool default y if VGA_ROM_RUN diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 2a911cbf10..50b3cc3b6c 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -24,79 +24,25 @@ #include #include -static int vboot_get_recovery_reason_shared_data(void) -{ - struct vb2_shared_data *sd = vb2_get_sd(vboot_get_context()); - assert(sd); - return sd->recovery_reason; -} - -void vboot_save_recovery_reason_vbnv(void) -{ - if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) - return; - - int reason = vboot_get_recovery_reason_shared_data(); - if (!reason) - return; - - set_recovery_mode_into_vbnv(reason); -} - -static void vboot_clear_recovery_reason_vbnv(void *unused) -{ - if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) - return; - - set_recovery_mode_into_vbnv(0); -} - /* - * Recovery reason stored in VBNV needs to be cleared before the state of VBNV - * is backed-up anywhere or jumping to the payload (whichever occurs - * first). Currently, vbnv_cmos.c backs up VBNV on POST_DEVICE. Thus, we need to - * make sure that the stored recovery reason is cleared off before that - * happens. - * IMPORTANT: Any reboot occurring after BS_DEV_INIT state will cause loss of - * recovery reason on reboot. Until now, we have seen reboots occurring on x86 - * only in FSP stages which run before BS_DEV_INIT. + * Functions which check vboot information should only be called after verstage + * has run. Otherwise, they will hit the assertion in vboot_get_context(). */ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, - vboot_clear_recovery_reason_vbnv, NULL); -/* - * vb2_check_recovery_request looks up different components to identify if there - * is a recovery request and returns appropriate reason code: - * 1. Checks if recovery mode is initiated by EC. If yes, returns - * VB2_RECOVERY_RO_MANUAL. - * 2. Checks if recovery request is present in VBNV and returns the code read - * from it. - * 3. Checks if vboot verification is done. If yes, return the reason code from - * shared data. - * 4. If nothing applies, return 0 indicating no recovery request. - */ int vboot_check_recovery_request(void) { - int reason = 0; - - /* EC-initiated recovery. */ - if (get_recovery_mode_switch()) - return VB2_RECOVERY_RO_MANUAL; - - /* Recovery request in VBNV. */ - if ((reason = get_recovery_mode_from_vbnv()) != 0) - return reason; - - /* Identify if vboot verification is already complete. */ - if (vboot_logic_executed()) - return vboot_get_recovery_reason_shared_data(); - - return 0; + /* TODO: Expose vb2api_recovery_reason() and vb2api_need_train_and_reboot(). */ + return vb2_get_sd(vboot_get_context())->recovery_reason; } int vboot_recovery_mode_enabled(void) { - return !!vboot_check_recovery_request(); + return vboot_get_context()->flags & VB2_CONTEXT_RECOVERY_MODE; +} + +int vboot_developer_mode_enabled(void) +{ + return vboot_get_context()->flags & VB2_CONTEXT_DEVELOPER_MODE; } int __weak clear_recovery_mode_switch(void) @@ -133,12 +79,6 @@ int vboot_recovery_mode_memory_retrain(void) return get_recovery_mode_retrain_switch(); } -int vboot_developer_mode_enabled(void) -{ - return vboot_logic_executed() && - vboot_get_context()->flags & VB2_CONTEXT_DEVELOPER_MODE; -} - #if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** * TODO: Create flash protection interface which implements get_write_protect_state. diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 324af5ca11..97944d92a6 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -49,11 +49,6 @@ static inline bool vboot_is_gbb_flag_set(enum vb2_gbb_flag flag) */ int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw); -/* - * Source: security/vboot/bootmode.c - */ -void vboot_save_recovery_reason_vbnv(void); - /* * The stage loading code is compiled and entered from multiple stages. The * helper functions below attempt to provide more clarity on when certain diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index be598acb18..a5a780664c 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -101,26 +101,6 @@ void save_vbnv(const uint8_t *vbnv_copy) vbnv_initialized = 0; } -/* Save a recovery reason into VBNV. */ -void set_recovery_mode_into_vbnv(int recovery_reason) -{ - uint8_t vbnv_copy[VBOOT_VBNV_BLOCK_SIZE]; - - read_vbnv(vbnv_copy); - - vbnv_copy[RECOVERY_OFFSET] = recovery_reason; - vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); - - save_vbnv(vbnv_copy); -} - -/* Read the recovery reason from VBNV. */ -int get_recovery_mode_from_vbnv(void) -{ - vbnv_setup(); - return vbnv[RECOVERY_OFFSET]; -} - /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index a2f0b4c978..7d288d5773 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -23,8 +23,6 @@ void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); void regen_vbnv_crc(uint8_t *vbnv_copy); -int get_recovery_mode_from_vbnv(void); -void set_recovery_mode_into_vbnv(int recovery_reason); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 18c96d77ff..df2f00243b 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -408,8 +408,5 @@ void verstage_main(void) vboot_is_firmware_slot_a(ctx) ? 'A' : 'B'); verstage_main_exit: - /* Save recovery reason in case of unexpected reboots on x86. */ - vboot_save_recovery_reason_vbnv(); - timestamp_add_now(TS_END_VBOOT); } diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index c3fcad9a50..7d69a92158 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -93,7 +93,6 @@ config AMD_SOC_PACKAGE config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0d69da23ca..6c90294d8c 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -113,7 +113,6 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d098785bad..b68e93d9c1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -260,7 +260,6 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 42e86c73b2..15a5a3120d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -165,7 +165,6 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ae60a63056..0340282c90 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -94,7 +94,6 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 1b90d4b365..79d74b4083 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -189,7 +189,6 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH From bd75e0c5cbe9f80519e7cf05e9077f3920414a55 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 14 Feb 2020 20:22:49 +0100 Subject: [PATCH 0010/1463] nb/intel/nehalem: Remove unused MRC_CACHE_SIZE Change-Id: I5d00fb238be6399ea6e9f394d8f899b03b1d44cf Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38906 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel --- src/northbridge/intel/nehalem/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index a119b817ae..cfd7fe248d 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -58,10 +58,6 @@ config DCACHE_BSP_STACK_SIZE The amount of anticipated stack usage in CAR by bootblock and other stages. -config MRC_CACHE_SIZE - hex - default 0x10000 - config MMCONF_BASE_ADDRESS hex default 0xe0000000 From c9a717ddb01dd7f8ba0a7fb3eb622885cd3716ad Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 16 Feb 2020 09:52:09 +0100 Subject: [PATCH 0011/1463] nb/intel/gm45: Fix typo in console message Change-Id: Ia0d7d5ecf376af97ee54ff3ca536160202e43f79 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38927 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: Paul Menzel --- src/northbridge/intel/gm45/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 5b8d1d811e..90dfa92a60 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1293,7 +1293,7 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; break; case CHANNEL_MODE_DUAL_ASYNC: - printk(BIOS_DEBUG, "Memory configured in dual-channel assymetric mode.\n"); + printk(BIOS_DEBUG, "Memory configured in dual-channel asymmetric mode.\n"); MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; break; case CHANNEL_MODE_DUAL_INTERLEAVED: From 84400180fa098edc47c044b8bc457d85da38858a Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 3 Feb 2020 15:20:46 +0100 Subject: [PATCH 0012/1463] soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is set DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI offset 0x80. This is specified in PCH BWG par 2.5.1.5. Add the support to make sure this PCR is always set correctly. BUG=N/A TEST=tested on facebook monolith. Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38746 Reviewed-by: Paul Menzel Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/bootblock/pch.c | 5 +++++ src/soc/intel/icelake/bootblock/pch.c | 5 +++++ src/soc/intel/skylake/bootblock/pch.c | 6 ++++++ src/soc/intel/tigerlake/bootblock/pch.c | 5 +++++ 4 files changed, 21 insertions(+) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a6e9f9db52..e7b79a0a68 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -172,6 +172,11 @@ void pch_early_iorange_init(void) * value program in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index fd2ffd2c88..b1309a45b0 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -144,6 +144,11 @@ void pch_early_iorange_init(void) * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ddf1139aa0..7763cf0033 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -140,6 +140,12 @@ void pch_early_iorange_init(void) * value program in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * As per PCH BWG 2.5.1.5. + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index cd264d682c..33637e9e01 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -169,6 +169,11 @@ void pch_early_iorange_init(void) * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ From ee38b991eb93de5f7a707f177693a1d9839c0409 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 3 Feb 2020 15:25:49 +0100 Subject: [PATCH 0013/1463] soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all. BUG=N/A TEST=build Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/cannonlake/bootblock/pch.c | 4 ++-- src/soc/intel/icelake/bootblock/pch.c | 4 ++-- src/soc/intel/skylake/bootblock/pch.c | 6 +++--- src/soc/intel/tigerlake/bootblock/pch.c | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index e7b79a0a68..eca28b33dd 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -168,8 +168,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index b1309a45b0..f51ecab4af 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -140,8 +140,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 7763cf0033..d5d3aedc3d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -135,9 +135,9 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * As per PCH BWG 2.5.16. - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * As per PCH BWG 2.5.1.6. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 33637e9e01..090f88f910 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -165,8 +165,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* From 4aab4abfa2c4d262743c5654643b95101e235191 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Tue, 28 May 2019 17:44:43 +0300 Subject: [PATCH 0014/1463] mb/apple/macbookair4_2: Add CMOS support Added CMOS support for MacBook Air 4,2. In future, I hope there will be more useful options available, because I'm working on macbooks support. Also, it may be necessary for hyper_threading support (#29669) once it will be ready. Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/33045 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Peter Lemenkov --- src/mainboard/apple/macbookair4_2/Kconfig | 2 + .../apple/macbookair4_2/cmos.default | 2 + src/mainboard/apple/macbookair4_2/cmos.layout | 85 +++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 src/mainboard/apple/macbookair4_2/cmos.default create mode 100644 src/mainboard/apple/macbookair4_2/cmos.layout diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 771f327aa0..627b421649 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select GFX_GMA_INTERNAL_IS_EDP select MAINBOARD_HAS_LIBGFXINIT + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbookair4_2/cmos.default b/src/mainboard/apple/macbookair4_2/cmos.default new file mode 100644 index 0000000000..06b04332a2 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.default @@ -0,0 +1,2 @@ +boot_option=Fallback +debug_level=Debug diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout new file mode 100644 index 0000000000..4f5df93c06 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -0,0 +1,85 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: cpu +#424 8 r 0 unused +# coreboot config options: northbridge +#432 5 e 11 gfx_uma_size +#437 3 r 0 unused +#440 8 h 0 volume +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk +# coreboot config options: check sums +984 16 h 0 check_sum +# ----------------------------------------------------------------- +enumerations +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums +checksum 392 447 984 From ca15430bf7d43c2ba0c0684f745f206ab5f70670 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 11 Feb 2020 19:25:17 +0000 Subject: [PATCH 0015/1463] Revert "mb/google/hatch: Override CPU flex ratio" This reverts commit a017e5fb3dda5ea6bbc94ee15b2e981eeaa2d918. Reason for revert: The extra reset in the FSP after the flex ratio is changed causes recovery reasons to be lost. There are some vboot changes that recently landed that could help with this issue, but for now, we are working on a new AU image for Kohaku and this is causing our automated testing to fail. Change-Id: Ic38b390842e2a533033587b3247b7c8d982b1dff Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/38324 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f7cf3cd466..9894e56324 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -197,9 +197,6 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - # CPU Ratio Override - register "cpu_ratio_override" = "15" - # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: From 2ae9d698882dd0ce899a0008d5d0526373af407a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 11 Feb 2020 12:38:29 -0600 Subject: [PATCH 0016/1463] ec/purism/librem: Add ACPI temp reporting Add EC ACPI reporting of current temp and platform critical temp. Adapted from ACPI dump of ODM AMI firmware. TEST: check reporting of current/critical temps via lm-sensors from ACPI on Librem 13v1 and 13v4 boards. Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/38835 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/ec/purism/librem/acpi/ec.asl | 24 ++++++++++++++++++++- src/mainboard/purism/librem_bdw/acpi/ec.asl | 1 + src/mainboard/purism/librem_skl/acpi/ec.asl | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index ff325aa9a3..6f6ced1b5c 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -52,7 +52,9 @@ Device (EC) OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x15), + Offset (0x13), + RTMP, 8, + , 8, BSTS, 2, /* Battery Status */ , 3, BTEX, 1, /* Battery Present */ @@ -231,3 +233,23 @@ Device (EC) #include "ac.asl" #include "battery.asl" } + +Scope (\_TZ) +{ + ThermalZone (TZ0) + { + /* _TMP: Temperature */ + Method (_TMP, 0, Serialized) + { + Local0 = (0x0AAC + (\_SB.PCI0.LPCB.EC.RTMP * 0x0A)) + Return (Local0) + } + + /* _CRT: Critical Temperature */ + Method (_CRT, 0, Serialized) + { + /* defined in board ec.asl */ + Return (CRIT_TEMP) + } + } +} diff --git a/src/mainboard/purism/librem_bdw/acpi/ec.asl b/src/mainboard/purism/librem_bdw/acpi/ec.asl index b2fa5b9924..a660a526f4 100644 --- a/src/mainboard/purism/librem_bdw/acpi/ec.asl +++ b/src/mainboard/purism/librem_bdw/acpi/ec.asl @@ -16,5 +16,6 @@ #define EC_SCI_GPI 10 #define PPCM_TURBO Zero #define PPCM_NOTURBO One +#define CRIT_TEMP 105 #include diff --git a/src/mainboard/purism/librem_skl/acpi/ec.asl b/src/mainboard/purism/librem_skl/acpi/ec.asl index c667b6c41b..c440ff87e4 100644 --- a/src/mainboard/purism/librem_skl/acpi/ec.asl +++ b/src/mainboard/purism/librem_skl/acpi/ec.asl @@ -16,5 +16,6 @@ #define EC_SCI_GPI 0x50 #define PPCM_TURBO One #define PPCM_NOTURBO 0x02 +#define CRIT_TEMP 100 #include From 970ed2ad293c6928a0ebaa41c6229112c7531983 Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Mon, 10 Feb 2020 15:02:27 -0500 Subject: [PATCH 0017/1463] cpu/x86: Adjust STM smm_save_state_size Initial testing of STM support revealed a sizing issue for greater than 4 threads. This patch reduces the STM smm_save_state_size, which should allow for 24 threads. Signed-off-by: Eugene D. Myers Change-Id: I025694185469577e072a92ea75cbbb53c24b2c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38819 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c747207f7c..5169861676 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1046,19 +1046,7 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) */ if (CONFIG(STM)) { state->smm_save_state_size += - sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); - - /* Currently, the CPU SMM save state size is based on a simplistic - * algorithm. (align on 4K) - * note: In the future, this will need to handle newer x86 processors - * that require alignment of the save state on 32K boundaries. - * The alignment is done here because coreboot has a hard coded - * value of 0x400 for this value. - * Also, this alignment only works on CPUs less than 5 threads - */ - if (CONFIG(STM)) - state->smm_save_state_size = - ALIGN_UP(state->smm_save_state_size, 0x1000); + ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100); } /* From 53e92360f5b08866856eb50a3d9adae070d4df7b Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Mon, 10 Feb 2020 15:44:38 -0500 Subject: [PATCH 0018/1463] cpu/x86: Remove unnecessary guard The is_smm_enabled is not necessary because it is done previously in this code path. Signed-off-by: Eugene D. Myers Change-Id: I20d50acbea891cb56ad49edc128df25d21c5f1ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/38820 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5169861676..6082df99d4 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -747,20 +747,15 @@ static void asmlinkage smm_do_relocation(void *arg) mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); if (CONFIG(STM)) { - if (is_smm_enabled()) { - uintptr_t mseg; + uintptr_t mseg; - mseg = mp_state.perm_smbase + - (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + mseg = mp_state.perm_smbase + + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); - stm_setup(mseg, p->cpu, runtime->num_cpus, - perm_smbase, - mp_state.perm_smbase, - runtime->start32_offset); - } else { - printk(BIOS_DEBUG, - "STM not loaded because SMM is not enabled!\n"); - } + stm_setup(mseg, p->cpu, runtime->num_cpus, + perm_smbase, + mp_state.perm_smbase, + runtime->start32_offset); } } From 47607bdc83558f63b917b4de2e35741fe5366469 Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Mon, 10 Feb 2020 17:46:49 -0500 Subject: [PATCH 0019/1463] cpu/x86/smm: Remove blank line in code Remove blank line to maintain the relation between the previous comment and the remainder of the block. Signed-off-by: Eugene D. Myers Change-Id: Ib9754c6723ecd5e4895898490fc7228e1c3839d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38821 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/x86/smm/smm_module_loader.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 81020a460a..66a40c4233 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -396,7 +396,6 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - // account for the bios resource list if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; From 2a3cef29d81ab9200b8226be41a09f975c9ed485 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 6 Feb 2020 17:58:07 -0700 Subject: [PATCH 0020/1463] mb/google/dedede: Enable AP <-> H1 Communication Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I37972635454cd0d35608623e7be4110012ace658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772 Reviewed-by: Justin TerAvest Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/Kconfig | 10 +++++++ .../dedede/variants/baseboard/devicetree.cb | 29 +++++++++++++++++-- .../google/dedede/variants/baseboard/gpio.c | 22 +++++++++++++- 3 files changed, 57 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 5254d16b7c..9b5bd4af5e 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,11 +1,14 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -25,6 +28,9 @@ config DEVICETREE string default "variants/baseboard/devicetree.cb" +config DRIVER_TPM_SPI_BUS + default 0x1 + config MAINBOARD_DIR string default "google/dedede" @@ -41,6 +47,10 @@ config MAX_CPUS int default 4 +config TPM_TIS_ACPI_INTERRUPT + int + default 4 # GPE0_DW0_4 (GPP_B4) + config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2a0b760728..e98b686608 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -29,13 +29,13 @@ chip soc/intel/tigerlake }" register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI0] = 1, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, }" @@ -52,6 +52,22 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -87,7 +103,14 @@ chip soc/intel/tigerlake device pci 1c.7 off end # PCI Express Root Port 8 device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 device pci 1e.3 off end # GSPI 1 device pci 1f.0 on chip ec/google/chromeec diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 090841260f..b9d77bf585 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,11 +21,31 @@ static const struct pad_config gpio_table[] = { /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) From 95ea799019fdb7c0baee70bd07196910dbc0cd95 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 7 Feb 2020 17:37:17 -0700 Subject: [PATCH 0021/1463] mb/google/dedede: Add console UART configuration Enable UART Port 2 as console UART and configure the concerned GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776 Reviewed-by: Justin TerAvest Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/Kconfig | 1 + .../google/dedede/variants/baseboard/devicetree.cb | 4 ++-- src/mainboard/google/dedede/variants/baseboard/gpio.c | 9 +++++++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 9b5bd4af5e..c2f66a43eb 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e98b686608..4b2a3c5b13 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ chip soc/intel/tigerlake register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoDisabled, [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" # Intel Common SoC Config @@ -91,7 +91,7 @@ chip soc/intel/tigerlake device pci 17.0 off end # SATA device pci 19.0 off end # I2C 4 device pci 19.1 off end # I2C 5 - device pci 19.2 off end # UART 2 + device pci 19.2 on end # UART 2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index b9d77bf585..c334f1107a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -32,6 +32,15 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C20 : UART_DBG_TX_AP_RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART_AP_TX_DBG_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS_N */ + PAD_NC(GPP_C22, DN_20K), + /* C23 : UART2_CTS_N */ + PAD_NC(GPP_C23, DN_20K), }; /* Early pad configuration in bootblock */ From 55c8702324c4ea99fe5f5a741b0c95c361f83672 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 11 Feb 2020 11:53:47 -0700 Subject: [PATCH 0022/1463] mb/google/dedede: Configure I2C ports Enable I2C ports that are used. Add GPIO configuration for the I2C ports. Enable config items that are required for I2C HID & Generic devices. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38847 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest --- src/mainboard/google/dedede/Kconfig | 2 + .../dedede/variants/baseboard/devicetree.cb | 40 ++++++++++++++----- .../google/dedede/variants/baseboard/gpio.c | 21 ++++++++++ 3 files changed, 53 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index c2f66a43eb..a3d189d639 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,5 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 4b2a3c5b13..2d57a14f25 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -20,11 +20,11 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw2" = "GPP_H" register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" @@ -60,12 +60,32 @@ chip soc/intel/tigerlake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, }" device domain 0 on @@ -80,16 +100,16 @@ chip soc/intel/tigerlake device pci 14.2 off end # PMC SRAM device pci 14.3 off end # CNVi wifi device pci 14.5 off end # SDCard - device pci 15.0 off end # I2C 0 - device pci 15.1 off end # I2C 1 - device pci 15.2 off end # I2C 2 - device pci 15.3 off end # I2C 3 + device pci 15.0 on end # I2C 0 + device pci 15.1 on end # I2C 1 + device pci 15.2 on end # I2C 2 + device pci 15.3 on end # I2C 3 device pci 16.0 off end # HECI 1 device pci 16.1 off end # HECI 2 device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4 device pci 17.0 off end # SATA - device pci 19.0 off end # I2C 4 + device pci 19.0 on end # I2C 4 device pci 19.1 off end # I2C 5 device pci 19.2 on end # UART 2 device pci 1a.0 off end # eMMC diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index c334f1107a..8e4200ab9f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -33,6 +33,14 @@ static const struct pad_config gpio_table[] = { /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : AP_I2C_EMR_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : AP_I2C_EMR_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART_DBG_TX_AP_RX */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART_AP_TX_DBG_RX */ @@ -41,6 +49,19 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C22, DN_20K), /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + + /* H4 : AP_I2C_TS_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : AP_I2C_TS_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : AP_I2C_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : AP_I2C_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : AP_I2C_AUDIO_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : AP_I2C_AUDIO_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ From 0ae3a14307274b345846d10d948a1f56ef44dcb3 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Wed, 12 Feb 2020 19:35:34 +0800 Subject: [PATCH 0023/1463] mb/google/octopus: Add custom SAR values for Bipship Bipship is a sustaining project of Blooguard. SAR value follow Blooguard. BUG=b:149414960 BRANCH=octopus TEST=build and verify load correct SAR value by sku-id Change-Id: Ic45ed10fc147401d4278f1811a86cd2b2e4c63ac Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/38859 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/octopus/variants/bloog/variant.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 699385ef09..6c85e50948 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -55,6 +55,8 @@ const char *get_wifi_sar_cbfs_filename(void) case SKU_50_BLOOGUARD: case SKU_51_BLOOGUARD: case SKU_52_BLOOGUARD: + case SKU_53_BIPSHIP: + case SKU_54_BIPSHIP: filename = "wifi_sar-blooguard.hex"; break; } From 1d812e893a2c2e0e6ee1eb9dafb9e681139624e7 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 7 Feb 2020 15:51:09 -0800 Subject: [PATCH 0024/1463] soc/tigerlake: Add Device id for Tiger Lake Dual Core Add device id for Tiger Lake Dual core part. BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38774 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro --- src/include/device/pci_ids.h | 1 + src/soc/intel/common/block/systemagent/systemagent.c | 1 + src/soc/intel/tigerlake/bootblock/report_platform.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e117ac2237..c6602c44e3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3445,6 +3445,7 @@ #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 4c7d8c8137..e660dbf162 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -398,6 +398,7 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, + PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, PCI_DEVICE_ID_INTEL_TGL_ID_Y, PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, PCI_DEVICE_ID_INTEL_JSL_EHL, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 127994d540..f38e9cf7be 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -46,6 +46,7 @@ static struct { } mch_table[] = { { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, From fa36d0b79fb9fdc9747bb653398c1893eb7221c8 Mon Sep 17 00:00:00 2001 From: Casper Chang Date: Tue, 11 Feb 2020 11:34:26 +0800 Subject: [PATCH 0025/1463] mb/google/kukui: Add panel for Kakadu Declare the following panel for Kakadu: - BOE_TV105WUM_NW0 BUG=b:148997748 TEST=build Kakadu image passed BRANCH=kukui Signed-off-by: Casper Chang Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38822 Reviewed-by: Peichao Li Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/kukui/Makefile.inc | 1 + src/mainboard/google/kukui/panel_kakadu.c | 28 ++ .../google/kukui/panel_params/Makefile.inc | 1 + .../panel_params/panel-BOE_TV105WUM_NW0.c | 333 ++++++++++++++++++ 4 files changed, 363 insertions(+) create mode 100644 src/mainboard/google/kukui/panel_kakadu.c create mode 100644 src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 7839422f93..a2a147c399 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -26,6 +26,7 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c +ramstage-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel_kakadu.c ramstage-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel_kodama.c ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c diff --git a/src/mainboard/google/kukui/panel_kakadu.c b/src/mainboard/google/kukui/panel_kakadu.c new file mode 100644 index 0000000000..3cb18ba918 --- /dev/null +++ b/src/mainboard/google/kukui/panel_kakadu.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Bitland Tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "panel.h" + +static struct panel_description kakadu_panels[] = { + [1] = { .name = "BOE_TV105WUM_NW0", }, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + if (panel_id < 0 || panel_id >= ARRAY_SIZE(kakadu_panels)) + return NULL; + + return get_panel_from_cbfs(&kakadu_panels[panel_id]); +} diff --git a/src/mainboard/google/kukui/panel_params/Makefile.inc b/src/mainboard/google/kukui/panel_params/Makefile.inc index 016dad05ef..3bd605d9b2 100644 --- a/src/mainboard/google/kukui/panel_params/Makefile.inc +++ b/src/mainboard/google/kukui/panel_params/Makefile.inc @@ -3,6 +3,7 @@ panel-params-$(CONFIG_BOARD_GOOGLE_KRANE) += panel-AUO_KD101N80_45NA panel-params-$(CONFIG_BOARD_GOOGLE_KRANE) += panel-BOE_TV101WUM_NL6 panel-params-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel-AUO_B101UAN08_3 panel-params-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel-BOE_TV101WUM_N53 +panel-params-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel-BOE_TV105WUM_NW0 panel-params-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel-CMN_P097PFG_SSD2858 panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-AUO_NT51021D8P panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-BOE_TV080WUM_NG0 diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c new file mode 100644 index 0000000000..45068839ff --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Bitland Tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data BOE_TV105WUM_NW0 = { + .edid = { + .ascii_string = "TV105WUM-NW0", + .manufacturer_name = "BOE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 156298, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 140, .hso = 60, .hspw = 24, + .va = 1920, .vbl = 24, .vso = 14, .vspw = 2, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 236, + }, + }, + .init = { + INIT_DCS_CMD(0x10), + INIT_DELAY_CMD(34), + INIT_DCS_CMD(0xB0, 0x05), + INIT_DCS_CMD(0xB1, 0xE5), + INIT_DCS_CMD(0xB3, 0x52), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x88), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB6, 0x03), + INIT_DCS_CMD(0xBA, 0x87), + INIT_DCS_CMD(0xBF, 0x1F), + INIT_DCS_CMD(0xC0, 0x0F), + INIT_DCS_CMD(0xC2, 0x0E), + INIT_DCS_CMD(0xC3, 0x02), + INIT_DCS_CMD(0xC4, 0x0E), + INIT_DCS_CMD(0xC5, 0x02), + INIT_DCS_CMD(0xB0, 0x01), + INIT_DCS_CMD(0xE0, 0x26), + INIT_DCS_CMD(0xE1, 0x26), + INIT_DCS_CMD(0xDC, 0x00), + INIT_DCS_CMD(0xDD, 0x00), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x26), + INIT_DCS_CMD(0xC8, 0x00), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xD2, 0x03), + INIT_DCS_CMD(0xD3, 0x03), + INIT_DCS_CMD(0xE6, 0x04), + INIT_DCS_CMD(0xE7, 0x04), + INIT_DCS_CMD(0xC4, 0x09), + INIT_DCS_CMD(0xC5, 0x09), + INIT_DCS_CMD(0xD8, 0x0A), + INIT_DCS_CMD(0xD9, 0x0A), + INIT_DCS_CMD(0xC2, 0x0B), + INIT_DCS_CMD(0xC3, 0x0B), + INIT_DCS_CMD(0xD6, 0x0C), + INIT_DCS_CMD(0xD7, 0x0C), + INIT_DCS_CMD(0xC0, 0x05), + INIT_DCS_CMD(0xC1, 0x05), + INIT_DCS_CMD(0xD4, 0x06), + INIT_DCS_CMD(0xD5, 0x06), + INIT_DCS_CMD(0xCA, 0x07), + INIT_DCS_CMD(0xCB, 0x07), + INIT_DCS_CMD(0xDE, 0x08), + INIT_DCS_CMD(0xDF, 0x08), + INIT_DCS_CMD(0xB0, 0x02), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xC1, 0x11), + INIT_DCS_CMD(0xC2, 0x1D), + INIT_DCS_CMD(0xC3, 0x2E), + INIT_DCS_CMD(0xC4, 0x3F), + INIT_DCS_CMD(0xC5, 0x3F), + INIT_DCS_CMD(0xC6, 0x3F), + INIT_DCS_CMD(0xC7, 0x3F), + INIT_DCS_CMD(0xC8, 0x3F), + INIT_DCS_CMD(0xC9, 0x3F), + INIT_DCS_CMD(0xCA, 0x3F), + INIT_DCS_CMD(0xCB, 0x3F), + INIT_DCS_CMD(0xCC, 0x3F), + INIT_DCS_CMD(0xCD, 0x33), + INIT_DCS_CMD(0xCE, 0x32), + INIT_DCS_CMD(0xCF, 0x31), + INIT_DCS_CMD(0xD0, 0x07), + INIT_DCS_CMD(0xD2, 0x00), + INIT_DCS_CMD(0xD3, 0x11), + INIT_DCS_CMD(0xD4, 0x1D), + INIT_DCS_CMD(0xD5, 0x2E), + INIT_DCS_CMD(0xD6, 0x3F), + INIT_DCS_CMD(0xD7, 0x3F), + INIT_DCS_CMD(0xD8, 0x3F), + INIT_DCS_CMD(0xD9, 0x3F), + INIT_DCS_CMD(0xDA, 0x3F), + INIT_DCS_CMD(0xDB, 0x3F), + INIT_DCS_CMD(0xDC, 0x3F), + INIT_DCS_CMD(0xDD, 0x3F), + INIT_DCS_CMD(0xDE, 0x3F), + INIT_DCS_CMD(0xDF, 0x33), + INIT_DCS_CMD(0xE0, 0x32), + INIT_DCS_CMD(0xE1, 0x31), + INIT_DCS_CMD(0xE2, 0x07), + INIT_DCS_CMD(0xB0, 0x03), + INIT_DCS_CMD(0xC8, 0x0B), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xC3, 0x00), + INIT_DCS_CMD(0xE7, 0x00), + INIT_DCS_CMD(0xC5, 0x2A), + INIT_DCS_CMD(0xDE, 0x2A), + INIT_DCS_CMD(0xCA, 0x43), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xE4, 0xC0), + INIT_DCS_CMD(0xE5, 0x0D), + INIT_DCS_CMD(0xCB, 0x00), + INIT_DCS_CMD(0xB0, 0x06), + INIT_DCS_CMD(0xB8, 0xA5), + INIT_DCS_CMD(0xC0, 0xA5), + INIT_DCS_CMD(0xC7, 0x0F), + INIT_DCS_CMD(0xD5, 0x32), + INIT_DCS_CMD(0xBC, 0x33), + INIT_DCS_CMD(0xB0, 0x07), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB9), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6D), + INIT_DCS_CMD(0xBC, 0xE5), + INIT_DCS_CMD(0xBD, 0xE9), + INIT_DCS_CMD(0xBE, 0x5E), + INIT_DCS_CMD(0xBF, 0xD6), + INIT_DCS_CMD(0xC0, 0x15), + INIT_DCS_CMD(0xC1, 0x51), + INIT_DCS_CMD(0xC2, 0x71), + INIT_DCS_CMD(0xC3, 0x90), + INIT_DCS_CMD(0xC4, 0x9C), + INIT_DCS_CMD(0xC5, 0xA8), + INIT_DCS_CMD(0xC6, 0xB5), + INIT_DCS_CMD(0xC7, 0xBC), + INIT_DCS_CMD(0xC8, 0xC0), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x08), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB8), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6C), + INIT_DCS_CMD(0xBC, 0xE3), + INIT_DCS_CMD(0xBD, 0xE7), + INIT_DCS_CMD(0xBE, 0x5C), + INIT_DCS_CMD(0xBF, 0xD3), + INIT_DCS_CMD(0xC0, 0x10), + INIT_DCS_CMD(0xC1, 0x4C), + INIT_DCS_CMD(0xC2, 0x6A), + INIT_DCS_CMD(0xC3, 0x8A), + INIT_DCS_CMD(0xC4, 0x96), + INIT_DCS_CMD(0xC5, 0xA2), + INIT_DCS_CMD(0xC6, 0xAE), + INIT_DCS_CMD(0xC7, 0xB4), + INIT_DCS_CMD(0xC8, 0xB8), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x09), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0C), + INIT_DCS_CMD(0xB4, 0x1C), + INIT_DCS_CMD(0xB5, 0x2D), + INIT_DCS_CMD(0xB6, 0x3C), + INIT_DCS_CMD(0xB7, 0x5F), + INIT_DCS_CMD(0xB8, 0x80), + INIT_DCS_CMD(0xB9, 0xC8), + INIT_DCS_CMD(0xBA, 0x0D), + INIT_DCS_CMD(0xBB, 0x8A), + INIT_DCS_CMD(0xBC, 0x10), + INIT_DCS_CMD(0xBD, 0x14), + INIT_DCS_CMD(0xBE, 0x91), + INIT_DCS_CMD(0xBF, 0x13), + INIT_DCS_CMD(0xC0, 0x53), + INIT_DCS_CMD(0xC1, 0x93), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xC6), + INIT_DCS_CMD(0xC4, 0xD6), + INIT_DCS_CMD(0xC5, 0xE4), + INIT_DCS_CMD(0xC6, 0xF3), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0A), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB9), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6D), + INIT_DCS_CMD(0xBC, 0xE5), + INIT_DCS_CMD(0xBD, 0xE9), + INIT_DCS_CMD(0xBE, 0x5E), + INIT_DCS_CMD(0xBF, 0xD6), + INIT_DCS_CMD(0xC0, 0x15), + INIT_DCS_CMD(0xC1, 0x51), + INIT_DCS_CMD(0xC2, 0x71), + INIT_DCS_CMD(0xC3, 0x90), + INIT_DCS_CMD(0xC4, 0x9C), + INIT_DCS_CMD(0xC5, 0xA8), + INIT_DCS_CMD(0xC6, 0xB5), + INIT_DCS_CMD(0xC7, 0xBC), + INIT_DCS_CMD(0xC8, 0xC0), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0B), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB8), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6C), + INIT_DCS_CMD(0xBC, 0xE3), + INIT_DCS_CMD(0xBD, 0xE7), + INIT_DCS_CMD(0xBE, 0x5C), + INIT_DCS_CMD(0xBF, 0xD3), + INIT_DCS_CMD(0xC0, 0x10), + INIT_DCS_CMD(0xC1, 0x4C), + INIT_DCS_CMD(0xC2, 0x6A), + INIT_DCS_CMD(0xC3, 0x8A), + INIT_DCS_CMD(0xC4, 0x96), + INIT_DCS_CMD(0xC5, 0xA2), + INIT_DCS_CMD(0xC6, 0xAE), + INIT_DCS_CMD(0xC7, 0xB4), + INIT_DCS_CMD(0xC8, 0xB8), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0C), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0C), + INIT_DCS_CMD(0xB4, 0x1C), + INIT_DCS_CMD(0xB5, 0x2D), + INIT_DCS_CMD(0xB6, 0x3C), + INIT_DCS_CMD(0xB7, 0x5F), + INIT_DCS_CMD(0xB8, 0x80), + INIT_DCS_CMD(0xB9, 0xC8), + INIT_DCS_CMD(0xBA, 0x0D), + INIT_DCS_CMD(0xBB, 0x8A), + INIT_DCS_CMD(0xBC, 0x10), + INIT_DCS_CMD(0xBD, 0x14), + INIT_DCS_CMD(0xBE, 0x91), + INIT_DCS_CMD(0xBF, 0x13), + INIT_DCS_CMD(0xC0, 0x53), + INIT_DCS_CMD(0xC1, 0x93), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xC6), + INIT_DCS_CMD(0xC4, 0xD6), + INIT_DCS_CMD(0xC5, 0xE4), + INIT_DCS_CMD(0xC6, 0xF3), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DELAY_CMD(100), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x08), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x68), + INIT_DELAY_CMD(10), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(100), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(50), + INIT_END_CMD, + }, +}; From 443fbd70495404a99a17be990518c237f3654227 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Tue, 11 Feb 2020 18:33:57 +0800 Subject: [PATCH 0026/1463] soc/mediatek: dsi: Increase pcw precision When configuring MIPI DSI Tx, the value of pcw was calculated from data rate in MHz, leading to loss of precision. This patch changes to use data rate in Hz for the calculation so that the resulting value should be consistent with the one in kernel (CL:1786327). In addition, change the type of data rate to u32, and calculation of data rate from pixel clock is changed to use DIV_ROUND_UP for consistency with kernel (CL:1761843). Also remove unused variable txdiv. BRANCH=kukui BUG=b:149051882 TEST=emerge-jacuzzi coreboot TEST=No scrolling issue on Juniper AUO and InnoLux panels Change-Id: I23220d446833b956431006027bbc8cb20fc696a5 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/38827 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/dsi.c | 36 ++++++++++--------- .../mediatek/common/include/soc/dsi_common.h | 3 +- src/soc/mediatek/mt8173/dsi.c | 14 ++++---- src/soc/mediatek/mt8183/dsi.c | 24 ++++++------- 4 files changed, 39 insertions(+), 38 deletions(-) diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 238b1eb47f..9222cb0c4b 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -39,29 +39,32 @@ static unsigned int mtk_dsi_get_bits_per_pixel(u32 format) return 24; } -static int mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes, +static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes, const struct edid *edid) { /* data_rate = pixel_clock * bits_per_pixel * mipi_ratio / lanes - * Note pixel_clock comes in kHz and returned data_rate is in Mbps. + * Note pixel_clock comes in kHz and returned data_rate is in bps. * mipi_ratio is the clk coefficient to balance the pixel clk in MIPI * for older platforms which do not have complete implementation in HFP. * Newer platforms should just set that to 1.0 (100 / 100). */ - int data_rate = (u64)edid->mode.pixel_clock * bits_per_pixel * - MTK_DSI_MIPI_RATIO_NUMERATOR / - (1000 * lanes * MTK_DSI_MIPI_RATIO_DENOMINATOR); - printk(BIOS_INFO, "DSI data_rate: %d Mbps\n", data_rate); + u32 data_rate = DIV_ROUND_UP((u64)edid->mode.pixel_clock * + bits_per_pixel * 1000 * + MTK_DSI_MIPI_RATIO_NUMERATOR, + (u64)lanes * + MTK_DSI_MIPI_RATIO_DENOMINATOR); + printk(BIOS_INFO, "DSI data_rate: %u bps\n", data_rate); - if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ) { - printk(BIOS_ERR, "data rate (%dMbps) must be >=%dMbps. " - "Please check the pixel clock (%u), bits per pixel(%u), " + if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ * MHz) { + printk(BIOS_ERR, "data rate (%ubps) must be >= %ubps. " + "Please check the pixel clock (%u), " + "bits per pixel (%u), " "mipi_ratio (%d%%) and number of lanes (%d)\n", - data_rate, MTK_DSI_DATA_RATE_MIN_MHZ, + data_rate, MTK_DSI_DATA_RATE_MIN_MHZ * MHz, edid->mode.pixel_clock, bits_per_pixel, (100 * MTK_DSI_MIPI_RATIO_NUMERATOR / MTK_DSI_MIPI_RATIO_DENOMINATOR), lanes); - return -1; + return 0; } return data_rate; } @@ -71,12 +74,13 @@ __weak void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) /* Do nothing. */ } -static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) +static void mtk_dsi_phy_timing(u32 data_rate, struct mtk_phy_timing *phy_timing) { u32 cycle_time, ui; + u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz); - ui = 1000 / data_rate + 0x01; - cycle_time = 8000 / data_rate + 0x01; + ui = 1000 / data_rate_mhz + 0x01; + cycle_time = 8000 / data_rate_mhz + 0x01; memset(phy_timing, 0, sizeof(*phy_timing)); @@ -401,11 +405,11 @@ static void mtk_dsi_reset_dphy(void) int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, const u8 *init_commands) { - int data_rate; + u32 data_rate; u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format); data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid); - if (data_rate < 0) + if (!data_rate) return -1; mtk_dsi_configure_mipi_tx(data_rate, lanes); diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 3052689c90..25727b8398 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -16,6 +16,7 @@ #ifndef SOC_MEDIATEK_DSI_COMMON_H #define SOC_MEDIATEK_DSI_COMMON_H +#include #include #include #include @@ -358,7 +359,7 @@ struct lcm_init_command { /* Functions that each SOC should provide. */ void mtk_dsi_reset(void); -void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes); +void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes); /* Functions as weak no-ops that can be overridden. */ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing); diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index dae23f5a0c..48bfbef1a5 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -20,7 +20,7 @@ #include #include -void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) +void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) { u32 txdiv0, txdiv1; u64 pcw; @@ -51,21 +51,21 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); - if (data_rate > 500) { + if (data_rate > 500 * MHz) { txdiv0 = 0; txdiv1 = 0; - } else if (data_rate >= 250) { + } else if (data_rate >= 250 * MHz) { txdiv0 = 1; txdiv1 = 0; - } else if (data_rate >= 125) { + } else if (data_rate >= 125 * MHz) { txdiv0 = 2; txdiv1 = 0; - } else if (data_rate >= 62) { + } else if (data_rate >= 62 * MHz) { txdiv0 = 2; txdiv1 = 1; } else { /* MIN = 50 */ - assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ); + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz); txdiv0 = 2; txdiv1 = 2; } @@ -83,7 +83,7 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) * Ref_clk is 26MHz */ pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24; - pcw /= 13; + pcw /= 13 * MHz; write32(&mipi_tx0->dsi_pll_con2, pcw); setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 7f5ac0a747..3710fc652c 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -19,32 +19,28 @@ #include #include -void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) +void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) { - unsigned int txdiv, txdiv0, txdiv1; + unsigned int txdiv0, txdiv1; u64 pcw; - if (data_rate >= 2000) { - txdiv = 1; + if (data_rate >= 2000 * MHz) { txdiv0 = 0; txdiv1 = 0; - } else if (data_rate >= 1000) { - txdiv = 2; + } else if (data_rate >= 1000 * MHz) { txdiv0 = 1; txdiv1 = 0; - } else if (data_rate >= 500) { - txdiv = 4; + } else if (data_rate >= 500 * MHz) { txdiv0 = 2; txdiv1 = 0; - } else if (data_rate > 250) { - /* Be aware that 250 is a special case that must use txdiv=4. */ - txdiv = 8; + } else if (data_rate > 250 * MHz) { + /* (data_rate == 250MHz) is a special case that should go to the + else-block below (txdiv0 = 4) */ txdiv0 = 3; txdiv1 = 0; } else { /* MIN = 125 */ - assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ); - txdiv = 16; + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz); txdiv0 = 4; txdiv1 = 0; } @@ -56,7 +52,7 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); pcw <<= 24; - pcw /= CLK26M_HZ / MHz; + pcw /= CLK26M_HZ; write32(&mipi_tx->pll_con0, pcw); clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); From f68cc8151310bf4477bf48ebd95b5473dab8ebde Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Tue, 14 Jan 2020 21:23:44 +0800 Subject: [PATCH 0027/1463] soc/mediatek: dsi: reduce the hbp and hfp for phy timing The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen. To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442. Also rename 'phy_timing' to 'timing' to sync with kernel upstream. Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed. BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=Boots and sees firmware screen on krane and juniper TEST=No scrolling issue on juniper AUO and InnoLux panels Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/38400 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/drivers/analogix/anx7625/anx7625.c | 2 +- src/soc/mediatek/common/dsi.c | 92 ++++++++++++++------------ 2 files changed, 49 insertions(+), 45 deletions(-) diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 293cc1c20e..9387a83bd9 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -273,7 +273,7 @@ static int anx7625_calculate_m_n(u32 pixelclock, return 1; } - *m = (unsigned long long)pixelclock * 599 / 600; + *m = pixelclock; *n = XTAL_FRQ / post_divider; *pd = post_divider; diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 9222cb0c4b..be99fe8992 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -74,47 +74,43 @@ __weak void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) /* Do nothing. */ } -static void mtk_dsi_phy_timing(u32 data_rate, struct mtk_phy_timing *phy_timing) +static void mtk_dsi_phy_timing(u32 data_rate, struct mtk_phy_timing *timing) { - u32 cycle_time, ui; + u32 timcon0, timcon1, timcon2, timcon3; u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz); - ui = 1000 / data_rate_mhz + 0x01; - cycle_time = 8000 / data_rate_mhz + 0x01; + memset(timing, 0, sizeof(*timing)); - memset(phy_timing, 0, sizeof(*phy_timing)); + timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; + timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; + timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - + timing->da_hs_prepare; + timing->da_hs_trail = timing->da_hs_prepare + 1; - phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); + timing->ta_go = 4 * timing->lpx - 2; + timing->ta_sure = timing->lpx + 2; + timing->ta_get = 4 * timing->lpx; + timing->da_hs_exit = 2 * timing->lpx + 1; - phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; + timing->da_hs_sync = 1; - phy_timing->da_hs_sync = 1; - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; - - phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); + timing->clk_hs_post = timing->clk_hs_prepare + 8; + timing->clk_hs_trail = timing->clk_hs_prepare; + timing->clk_hs_zero = timing->clk_hs_trail * 4; + timing->clk_hs_exit = 2 * timing->clk_hs_trail; /* Allow board-specific tuning. */ - mtk_dsi_override_phy_timing(phy_timing); + mtk_dsi_override_phy_timing(timing); - u32 timcon0, timcon1, timcon2, timcon3; - - timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | - phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; - timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | - phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; - timcon2 = phy_timing->da_hs_sync << 8 | phy_timing->clk_hs_zero << 16 | - phy_timing->clk_hs_trail << 24; - timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | - phy_timing->clk_hs_exit << 16; + timcon0 = timing->lpx | timing->da_hs_prepare << 8 | + timing->da_hs_zero << 16 | timing->da_hs_trail << 24; + timcon1 = timing->ta_go | timing->ta_sure << 8 | + timing->ta_get << 16 | timing->da_hs_exit << 24; + timcon2 = timing->da_hs_sync << 8 | timing->clk_hs_zero << 16 | + timing->clk_hs_trail << 24; + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 | + timing->clk_hs_exit << 16; write32(&dsi0->dsi_phy_timecon0, timcon0); write32(&dsi0->dsi_phy_timecon1, timcon1); @@ -180,6 +176,8 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, const struct mtk_phy_timing *phy_timing) { u32 hsync_active_byte; + u32 hbp; + u32 hfp; u32 hbp_byte; u32 hfp_byte; u32 vbp_byte; @@ -199,17 +197,20 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, write32(&dsi0->dsi_vfp_nl, vfp_byte); write32(&dsi0->dsi_vact_nl, edid->mode.va); - unsigned int hspw = 0; - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hspw = edid->mode.hspw; - - hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) - * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; - hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel; + + hbp = edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder; + hfp = edid->mode.hso - edid->mode.hborder; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = hbp * bytes_per_pixel - 10; + else + hbp_byte = (hbp + edid->mode.hspw) * bytes_per_pixel - 10; + hfp_byte = hfp * bytes_per_pixel; data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3; u32 delta = 12; if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) @@ -218,11 +219,14 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, u32 d_phy = phy_timing->d_phy; if (d_phy == 0) d_phy = data_phy_cycles * lanes + delta; - if (hfp_byte > d_phy) - hfp_byte -= d_phy; - else - printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz " - "and the panel may not work properly.\n"); + + if ((hfp + hbp) * bytes_per_pixel > d_phy) { + hfp_byte -= d_phy * hfp / (hfp + hbp); + hbp_byte -= d_phy * hbp / (hfp + hbp); + } else { + printk(BIOS_ERR, "HFP plus HBP is not greater than d_phy, " + "the panel may not work properly.\n"); + } write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte); From a151311b5958e811cafc436ca25119fbe98b991a Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Tue, 14 Jan 2020 21:29:35 +0800 Subject: [PATCH 0028/1463] mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. The parameters are based on BOE NV101WUM-N53 preliminary product spec. BRANCH=kukui BUG=b:147378025 TEST=bootup pass Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162 Signed-off-by: Jitao Shi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38401 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- .../google/kukui/panel_params/panel-BOE_TV101WUM_N53.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c index dc5a2ac911..10753d960f 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c @@ -22,11 +22,11 @@ struct panel_serializable_data BOE_TV101WUM_N53 = { .panel_bits_per_color = 8, .panel_bits_per_pixel = 24, .mode = { - .pixel_clock = 159834, + .pixel_clock = 159916, .lvds_dual_channel = 0, .refresh = 60, - .ha = 1200, .hbl = 164, .hso = 114, .hspw = 10, - .va = 1920, .vbl = 33, .vso = 19, .vspw = 4, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, + .va = 1920, .vbl = 34, .vso = 20, .vspw = 4, .phsync = '-', .pvsync = '-', .x_mm = 135, .y_mm = 216, }, From b4a2938f0936985bca4b3715eddb1392ef422297 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 12 Feb 2020 11:51:49 +0800 Subject: [PATCH 0029/1463] soc/mediatek: dsi: Correct bits_per_pixel for MIPI_DSI_FMT_RGB666 The number of bits per pixel for MIPI_DSI_FMT_RGB666 should be 24 instead of 18. BRANCH=none BUG=none TEST=none Change-Id: I9574502b2dec4b5a042df3886922ddd8c755da1a Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/38845 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Jitao Shi Reviewed-by: Hung-Te Lin --- src/soc/mediatek/common/dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index be99fe8992..03e177e569 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -28,9 +28,9 @@ static unsigned int mtk_dsi_get_bits_per_pixel(u32 format) switch (format) { case MIPI_DSI_FMT_RGB565: return 16; - case MIPI_DSI_FMT_RGB666: case MIPI_DSI_FMT_RGB666_PACKED: return 18; + case MIPI_DSI_FMT_RGB666: case MIPI_DSI_FMT_RGB888: return 24; } From 4e3cb9588bf15b416698484faad8454482ceae41 Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Wed, 12 Feb 2020 15:49:58 +0800 Subject: [PATCH 0030/1463] mb/google/puff: Enable SPD_READ_BY_WORD to short the boottime Puff uses the smbus to access the SPD of memory DIMMs. It will short the SPD reading time if enabling SPD_READ_BY_WORD. BUG=b:149360051 BRANCH=None TEST=build puff and boot up OS ran cbmem -t | grep FspMemoryInit Without this patch: 950:calling FspMemoryInit 643,199 (257,588) With this patch: 950:calling FspMemoryInit 477,714 (154,612) Signed-off-by: Jamie Chen Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38848 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e216135419..2427b12bf4 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -48,6 +48,7 @@ config BOARD_GOOGLE_PUFF select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 select ROMSTAGE_SPD_SMBUS + select SPD_READ_BY_WORD config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" From 4714100c49663cee47cd37dbfe31e6ae11c4b6b4 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 14 Feb 2020 15:50:05 +0800 Subject: [PATCH 0031/1463] mb/google/drallion: Correct USB3 OC pin configuration USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly. BUG=b:147869924 TEST=USB function works well and OC function is corresponds to the right port. Signed-off-by: Eric Lai Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885 Reviewed-by: John Su Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../google/drallion/variants/drallion/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 06d3e5dd26..92f3fb9772 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -154,9 +154,9 @@ chip soc/intel/cannonlake register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" From 3404247115c1a853a64a01dfa5468aaef289bcf1 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 14 Feb 2020 09:51:54 +0100 Subject: [PATCH 0032/1463] util/docker: Use more stable URL The pgeorgi namespace is my own and things could change without notice there. To overcome this issue, encapsulate is now maintained on review.coreboot.org/encapsulate.git and mirrored over to github, so let's use that. Change-Id: I12e43f61f693a6b0392b84dd56ede665a1a2129a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38899 Reviewed-by: Martin Roth Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/docker/coreboot-jenkins-node/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index cfe5abb92d..73f7f1829d 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -45,7 +45,7 @@ RUN mkdir /cb-build && \ echo "tmpfs /home/coreboot/.ccache tmpfs rw,mode=1777 0 0" >> /etc/fstab # Build encapsulate tool -ADD https://raw.githubusercontent.com/pgeorgi/encapsulate/master/encapsulate.c /tmp/encapsulate.c +ADD https://raw.githubusercontent.com/coreboot/encapsulate/master/encapsulate.c /tmp/encapsulate.c RUN gcc -o /usr/sbin/encapsulate /tmp/encapsulate.c && \ chown root /usr/sbin/encapsulate && \ chmod +s /usr/sbin/encapsulate From 6cf33858b64449ad6e22cd27ec5734a972b8f39e Mon Sep 17 00:00:00 2001 From: Kenneth Chan Date: Thu, 6 Feb 2020 17:14:34 +0800 Subject: [PATCH 0033/1463] mb/google/octopus/variants/dood: add two new SKU IDs add SKU ID 3 and 4 for dood DVT 1: Dood WiFi + LTE (evt) 2: Dood WiFi (evt) 3: Dood WiFi + LTE + dual camera (dvt) 4: Dood WiFi + dual camera (dvt) BUG=b:148988979 TEST=build firmware and verify on the DUT of sku 3 and 4 check LTE module is enabled or not Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892 Signed-off-by: Kenneth Chan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38730 Reviewed-by: Marco Chen Reviewed-by: Ren Kuo Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/dood/gpio.c | 3 +++ src/mainboard/google/octopus/variants/dood/variant.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 5b567b3691..96b8ac02c7 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -22,6 +22,8 @@ enum { SKU_1_LTE = 1, /* Wifi + LTE */ SKU_2_WIFI = 2, /* Wifi */ + SKU_3_LTE_2CAM = 3, /* Wifi + LTE + dual camera */ + SKU_4_WIFI_2CAM = 4, /* Wifi + dual camera */ }; static const struct pad_config default_override_table[] = { @@ -62,6 +64,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) switch (sku_id) { case SKU_1_LTE: + case SKU_3_LTE_2CAM: *num = ARRAY_SIZE(lte_override_table); return lte_override_table; default: diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 7116061019..694e190892 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -23,6 +23,8 @@ enum { SKU_1_LTE = 1, /* Wifi + LTE */ SKU_2_WIFI = 2, /* Wifi */ + SKU_3_LTE_2CAM = 3, /* Wifi + LTE + dual camera */ + SKU_4_WIFI_2CAM = 4, /* Wifi + dual camera */ }; struct gpio_with_delay { @@ -63,6 +65,7 @@ void variant_smi_sleep(u8 slp_typ) switch (get_board_sku()) { case SKU_1_LTE: + case SKU_3_LTE_2CAM: power_off_lte_module(slp_typ); return; default: From bf33b03acf27d79df9bf1bd8d5075b70196b1844 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 14 Feb 2020 12:42:01 -0800 Subject: [PATCH 0034/1463] libpayload: arm64: Keep instruction cache enabled at all times This patch makes libpayload enable the instruction cache as the very first thing, which is similar to how we treat it in coreboot. It also prevents the icache from being disabled again during mmu_disable() as part of the two-stage page table setup in post_sysinfo_scan_mmu_setup(). It replaces the existing mmu_disable() implementation with the assembly version from coreboot which handles certain edge cases better (see CB:27238 for details). The SCTLR flag definitions in libpayload seem to have still been copy&pasted from arm32, so replace with the actual arm64 defintions from coreboot. Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38908 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- payloads/libpayload/arch/arm64/cpu.S | 15 +++++++++ payloads/libpayload/arch/arm64/head.S | 4 +++ payloads/libpayload/arch/arm64/mmu.c | 24 -------------- .../libpayload/include/arm64/arch/cache.h | 32 ------------------- .../include/arm64/arch/lib_helpers.h | 20 ++++++++++++ 5 files changed, 39 insertions(+), 56 deletions(-) diff --git a/payloads/libpayload/arch/arm64/cpu.S b/payloads/libpayload/arch/arm64/cpu.S index d80f73c112..70a1044b02 100644 --- a/payloads/libpayload/arch/arm64/cpu.S +++ b/payloads/libpayload/arch/arm64/cpu.S @@ -29,6 +29,7 @@ */ #include +#include .macro dcache_apply_all crm dsb sy @@ -96,3 +97,17 @@ ENDPROC(dcache_clean_all) ENTRY(dcache_clean_invalidate_all) dcache_apply_all crm=cisw ENDPROC(dcache_clean_invalidate_all) + +/* This must be implemented in assembly to ensure there are no accesses to + memory (e.g. the stack) in between disabling and flushing the cache. */ +ENTRY(mmu_disable) + str x30, [sp, #-0x8] + mrs x0, sctlr_el2 + mov x1, #~(SCTLR_C | SCTLR_M) + and x0, x0, x1 + msr sctlr_el2, x0 + isb + bl dcache_clean_invalidate_all + ldr x30, [sp, #-0x8] + ret +ENDPROC(mmu_disable) diff --git a/payloads/libpayload/arch/arm64/head.S b/payloads/libpayload/arch/arm64/head.S index 8bac70fee5..c44169b82a 100644 --- a/payloads/libpayload/arch/arm64/head.S +++ b/payloads/libpayload/arch/arm64/head.S @@ -28,11 +28,15 @@ */ #include +#include /* * Our entry point */ ENTRY(_entry) + /* Initialize SCTLR to intended state (icache and stack-alignment on) */ + ldr w1, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA) + msr sctlr_el2, x1 /* Save off the location of the coreboot tables */ ldr x1, 1f diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index d1dd5b0147..3a5e04db6c 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -303,30 +303,6 @@ static uint32_t is_mmu_enabled(void) return (sctlr & SCTLR_M); } -/* - * Func: mmu_disable - * Desc: Invalidate caches and disable mmu - */ -void mmu_disable(void) -{ - uint32_t sctlr; - - sctlr = raw_read_sctlr_el2(); - sctlr &= ~(SCTLR_C | SCTLR_M | SCTLR_I); - - tlbiall_el2(); - dcache_clean_invalidate_all(); - - dsb(); - isb(); - - raw_write_sctlr_el2(sctlr); - - dcache_clean_invalidate_all(); - dsb(); - isb(); -} - /* * Func: mmu_enable * Desc: Initialize MAIR, TCR, TTBR and enable MMU by setting appropriate bits diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index de68cee3f1..ace0e0ecd6 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -35,38 +35,6 @@ #include #include -/* SCTLR bits */ -#define SCTLR_M (1 << 0) /* MMU enable */ -#define SCTLR_A (1 << 1) /* Alignment check enable */ -#define SCTLR_C (1 << 2) /* Data/unified cache enable */ -/* Bits 4:3 are reserved */ -#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */ -/* Bit 6 is reserved */ -#define SCTLR_B (1 << 7) /* Endianness */ -/* Bits 9:8 */ -#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */ -#define SCTLR_Z (1 << 11) /* Branch prediction enable */ -#define SCTLR_I (1 << 12) /* Instruction cache enable */ -#define SCTLR_V (1 << 13) /* Low/high exception vectors */ -#define SCTLR_RR (1 << 14) /* Round Robin select */ -/* Bits 16:15 are reserved */ -#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */ -/* Bit 18 is reserved */ -/* Bits 20:19 reserved virtualization not supported */ -#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ -#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission - implies PL1 XN */ -#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ -#define SCTLR_U (1 << 22) /* Unaligned access behavior */ -#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */ -#define SCTLR_EE (1 << 25) /* Exception endianness */ -/* Bit 26 is reserved */ -#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */ -#define SCTLR_TRE (1 << 28) /* TEX remap enable */ -#define SCTLR_AFE (1 << 29) /* Access flag enable */ -#define SCTLR_TE (1 << 30) /* Thumb exception enable */ -/* Bit 31 is reserved */ - /* * Cache maintenance API */ diff --git a/payloads/libpayload/include/arm64/arch/lib_helpers.h b/payloads/libpayload/include/arm64/arch/lib_helpers.h index 7617f97426..b2e3a069e0 100644 --- a/payloads/libpayload/include/arm64/arch/lib_helpers.h +++ b/payloads/libpayload/include/arm64/arch/lib_helpers.h @@ -30,11 +30,29 @@ #ifndef __ARCH_LIB_HELPERS_H__ #define __ARCH_LIB_HELPERS_H__ +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +#define SCTLR_SA (1 << 3) /* Stack alignment check enable */ +#define SCTLR_NAA (1 << 6) /* non-aligned access STA/LDR */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_ENDB (1 << 13) /* Pointer auth (data B) */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_IESB (1 << 21) /* Implicit error sync event */ +#define SCTLR_EE (1 << 25) /* Exception endianness (BE) */ +#define SCTLR_ENDA (1 << 27) /* Pointer auth (data A) */ +#define SCTLR_ENIB (1 << 30) /* Pointer auth (insn B) */ +#define SCTLR_ENIA (1 << 31) /* Pointer auth (insn A) */ +#define SCTLR_RES1 ((0x3 << 4) | (0x1 << 11) | (0x1 << 16) | \ + (0x1 << 18) | (0x3 << 22) | (0x3 << 28)) + #define DAIF_DBG_BIT (1 << 3) #define DAIF_ABT_BIT (1 << 2) #define DAIF_IRQ_BIT (1 << 1) #define DAIF_FIQ_BIT (1 << 0) +#ifndef __ASSEMBLER__ + #include #define MAKE_REGISTER_ACCESSORS(reg) \ @@ -273,4 +291,6 @@ static inline void tlbivaa_el1(uint64_t va) #define dsb() dsb_opt(sy) #define isb() isb_opt() +#endif /* __ASSEMBLER__ */ + #endif /* __ARCH_LIB_HELPERS_H__ */ From 433bf770fc62fe8646b5a0ea795d381e28ec19f6 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Tue, 29 Nov 2016 21:02:04 +0100 Subject: [PATCH 0035/1463] lib/edid.c: Remove trailing space from detailed mode output When the bit for interlaced mode is not set, a trailing space is added to the end. As the space is already accounted for in `" interlaced"`, remove that space. TEST=Boot on Lenovo X60t, and verify the trailing space in the detailed mode is gone. Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/17644 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/lib/edid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 4a2f07ae3e..238fed56a0 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -573,7 +573,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, "Detailed mode (IN HEX): Clock %d KHz, %x mm x %x mm\n" " %04x %04x %04x %04x hborder %x\n" " %04x %04x %04x %04x vborder %x\n" - " %chsync %cvsync%s%s %s\n", + " %chsync %cvsync%s%s%s\n", out->mode.pixel_clock, extra_info.x_mm, extra_info.y_mm, From 1ced4e64b0b130708dbce6c406c7125f82c8e705 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 15 Feb 2020 13:12:04 +0100 Subject: [PATCH 0036/1463] lib/edid: Zero struct only when used Change-Id: I1c14e7458153fb992b17f30d7015321fae533bb2 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38913 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/lib/edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 238fed56a0..048cc6ad5a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1138,8 +1138,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) .conformant = EDID_CONFORMANT, }; - memset(out, 0, sizeof(*out)); - if (!edid) { printk(BIOS_ERR, "No EDID found\n"); return EDID_ABSENT; @@ -1152,6 +1150,8 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) return EDID_ABSENT; } + memset(out, 0, sizeof(*out)); + if (manufacturer_name(edid + 0x08, out->manufacturer_name)) c.manufacturer_name_well_formed = 1; From 6f6be5afbd16bde6e41ec9dce915aa4e8e04808f Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 15 Feb 2020 13:56:01 +0100 Subject: [PATCH 0037/1463] drivers/intel/gma: Remove space between `printf ()` Fix the warning below. WARNING: space prohibited between function name and open parenthesis '(' Change-Id: I28d9ba64c790c659040cd34eda37125e191dab39 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38914 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/drivers/intel/gma/edid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 4d4aec3a6e..cf6ea51045 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -103,7 +103,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) printk (BIOS_SPEW, "EDID:\n"); for (i = 0; i < 128; i++) { - printk (BIOS_SPEW, "%02x ", edid[i]); + printk(BIOS_SPEW, "%02x ", edid[i]); if ((i & 0xf) == 0xf) printk (BIOS_SPEW, "\n"); } From 75c5eadaf6238bb05e54e6d0dacd4d4966a70219 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 15 Feb 2020 13:57:41 +0100 Subject: [PATCH 0038/1463] drivers/intel/gma: Print EDID with leading instead of trailing space This way, the block is a little indented below `EDID:` making it a little more structured for the eye. Change-Id: I12066efefb23c5ffa8ba6b8c486cd54e142d4dc1 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38915 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/drivers/intel/gma/edid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index cf6ea51045..ca3ab322b6 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -103,7 +103,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) printk (BIOS_SPEW, "EDID:\n"); for (i = 0; i < 128; i++) { - printk(BIOS_SPEW, "%02x ", edid[i]); + printk(BIOS_SPEW, " %02x", edid[i]); if ((i & 0xf) == 0xf) printk (BIOS_SPEW, "\n"); } From 141020a80aa22181da038da5bf749d4ec79e4f95 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 17 Jan 2020 15:58:48 +0100 Subject: [PATCH 0039/1463] autoport: Remove space in example code The coreboot coding style does not insert a space between the function and argument list. Change-Id: I740f6c7f513e4f2715c793f61c9d9835c55c9dce Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38912 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- util/autoport/readme.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/autoport/readme.md b/util/autoport/readme.md index b73b44121d..a964e06d87 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -155,10 +155,10 @@ the SPD array must be `0x50`. After testing all the slots, your `mainboard_get_s should look similar to this: void mainboard_get_spd(spd_raw_data *spd) { - read_spd (&spd[0], 0x50); - read_spd (&spd[1], 0x51); - read_spd (&spd[2], 0x52); - read_spd (&spd[3], 0x53); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } Note that there should be one line per memory slot on the mainboard. From 96f18a01da872079bbec51c3c3c10cd7d4d4bc83 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 17 Oct 2019 02:01:47 +0200 Subject: [PATCH 0040/1463] util/k8resdump: Remove util AMD K8 support was dropped. Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36085 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/k8resdump/Makefile | 61 ------------------ util/k8resdump/description.md | 2 - util/k8resdump/k8resdump.c | 114 ---------------------------------- 3 files changed, 177 deletions(-) delete mode 100644 util/k8resdump/Makefile delete mode 100644 util/k8resdump/description.md delete mode 100644 util/k8resdump/k8resdump.c diff --git a/util/k8resdump/Makefile b/util/k8resdump/Makefile deleted file mode 100644 index a1d4dfa682..0000000000 --- a/util/k8resdump/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -## -## Makefile for k8resdump utility -## -## (C) 2005 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -PROGRAM = k8resdump - -CC = gcc -INSTALL = /usr/bin/env install -PREFIX = /usr/local -#CFLAGS = -O2 -g -Wall -Werror -CFLAGS = -Os -Wall -Werror -OS_ARCH = $(shell uname) -ifeq ($(OS_ARCH), SunOS) -LDFLAGS = -lpci -else -LDFLAGS = -lpci -lz -static -endif - -OBJS = k8resdump.o - -all: pciutils dep $(PROGRAM) - -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) - -clean: - rm -f *.o *~ - -distclean: clean - rm -f $(PROGRAM) .dependencies - -dep: - @$(CC) -MM *.c > .dependencies - -pciutils: - @echo; echo -n "Checking for pciutils and zlib... " - @$(shell ( echo "#include "; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install pciutils-devel and zlib-devel."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test; exit 1) - @rm -f .test.c .test - -.PHONY: all clean distclean dep pciutils - --include .dependencies diff --git a/util/k8resdump/description.md b/util/k8resdump/description.md deleted file mode 100644 index dd1f1449af..0000000000 --- a/util/k8resdump/description.md +++ /dev/null @@ -1,2 +0,0 @@ -This program will dump the IO/memory/PCI resources from the K8 memory -controller `C` diff --git a/util/k8resdump/k8resdump.c b/util/k8resdump/k8resdump.c deleted file mode 100644 index 66d7060960..0000000000 --- a/util/k8resdump/k8resdump.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License v2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This program will dump the IO/memory/PCI resources from the K8 - * memory controller - */ - -#include -#include -#include -#include -#include -#include - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -static uint8_t dram_bases[] = - { 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78 }; -static uint8_t dram_limits[] = - { 0x44, 0x4C, 0x54, 0x5C, 0x64, 0x6C, 0x74, 0x7C }; -static uint8_t iomem_bases[] = - { 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0, 0xB8 }; -static uint8_t iomem_limits[] = - { 0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC }; - -static uint8_t pciio_bases[] = { 0xC0, 0xC8, 0xD0, 0xD8 }; -static uint8_t pciio_limits[] = { 0xC4, 0xCC, 0xD4, 0xDC }; - -void print_info(struct pci_dev *dev) -{ - int i; - uint32_t regb, regl; - - for (i = 0; i < ARRAY_SIZE(dram_bases); i++) { - regb = pci_read_long(dev, dram_bases[i]); - regl = pci_read_long(dev, dram_limits[i]); - - printf - ("DRAM map: #%d 0x%04x000000 - 0x%04xffffff Access: %s/%s" - " IntlvEN:0x%x IntlvSEL:0x%x Dstnode:%d\n", - i, regb >> 16, regl >> 16, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", (regb & 0x700) >> 8, - (regl & 0x700) >> 8, (regl & 0x7)); - } - - - for (i = 0; i < ARRAY_SIZE(iomem_bases); i++) { - regb = pci_read_long(dev, iomem_bases[i]); - regl = pci_read_long(dev, iomem_limits[i]); - - printf - ("MMIO map: #%d 0x%06x0000 - 0x%06xffff Access: %s/%s %s %s" - " %s Dstnode:%d DstLink %d\n", - i, regb >> 8, regl >> 8, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 4 ? "CPU Dis" : "", - regb & 8 ? "Locked" : "", - regl & 0x80 ? "NonPosted" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - for (i = 0; i < ARRAY_SIZE(pciio_bases); i++) { - regb = pci_read_long(dev, pciio_bases[i]); - regl = pci_read_long(dev, pciio_limits[i]); - - printf - (" IO map: #%d 0x%03x000 - 0x%03xfff Access: %s/%s %s %s" - " Dstnode:%d DstLink %d\n", - i, (regb & ~0xff000000) >> 12, - (regl & ~0xff000000) >> 12, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 0x20 ? "ISA" : "", - regb & 0x10 ? "VGA" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - -} - -int main(void) -{ - struct pci_access *pacc; - struct pci_dev *dev; - - if (getuid()) { - fprintf(stderr, "Please run me root, need access to all" - " PCI regs!\n"); - exit(1); - } - - pacc = pci_alloc(); - pci_init(pacc); - pci_scan_bus(pacc); - for (dev = pacc->devices; dev; dev = dev->next) { - pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | - PCI_FILL_CLASS); - if ((dev->vendor_id == 0x1022) /* AMD */ - && (dev->device_id == 0x1101)) { /* Address MAP */ - print_info(dev); - } - } - pci_cleanup(pacc); - return 0; -} From 16043d6742aedb2740d23628fead775748aa0ce0 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 23 Jan 2020 12:48:03 +0100 Subject: [PATCH 0041/1463] libpayload/corebootfb: Fix character buffer relocation The `chars` pointer references the heap which is part of the payload and relocated along with it. So calling phys_to_virt() on it was always wrong; and the virt_to_phys() at its initialization was a no-op anyway, when the console was brought up before relocation. While we are at it, add a null-pointer check. Change-Id: Ic03150f0bcd14a6ec6bf514dffe2b9153d5a6d2a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38536 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Julius Werner --- payloads/libpayload/drivers/video/corebootfb.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index b5ad1a511d..11397ba905 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -64,11 +64,11 @@ static const u32 vga_colors[] = { /* Addresses for the various components */ static unsigned long fbinfo; static unsigned long fbaddr; -static unsigned long chars; +static unsigned short *chars; #define FI ((struct cb_framebuffer *) phys_to_virt(fbinfo)) #define FB ((unsigned char *) phys_to_virt(fbaddr)) -#define CHARS ((unsigned short *) phys_to_virt(chars)) +#define CHARS (chars) static void corebootfb_scroll_up(void) { @@ -243,9 +243,10 @@ static int corebootfb_init(void) coreboot_video_console.columns = FI->x_resolution / font_width; coreboot_video_console.rows = FI->y_resolution / font_height; - /* See setting of fbinfo above. */ - chars = virt_to_phys(malloc(coreboot_video_console.rows * - coreboot_video_console.columns * 2)); + chars = malloc(coreboot_video_console.rows * + coreboot_video_console.columns * 2); + if (!chars) + return -1; // clear boot splash screen if there is one. corebootfb_clear(); From 99e54fece3d6e03b21366f6415dea6972a7eda8d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 30 Jan 2020 15:08:03 +0100 Subject: [PATCH 0042/1463] util: Fix typos Change-Id: Ia405384211aa53ac089a99ecd31acc25effdb71e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38653 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/amdfwtool/amdfwtool.c | 2 +- util/ifdtool/ifdtool.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d5c63dec34..522d332bbd 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1439,7 +1439,7 @@ int main(int argc, char **argv) integrate_firmwares(&ctx, amd_romsig, amd_fw_table); - ctx.current = ALIGN(ctx.current, 0x10000U); /* todo: is necessary? */ + ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is necessary? */ if (multi) { /* Do 2nd PSP directory followed by 1st */ diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 2bf2f4d266..d89e77d2c2 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -631,11 +631,11 @@ static void dump_fmsba(const fmsba_t *fmsba) static void dump_jid(uint32_t jid) { - printf(" SPI Componend Vendor ID: 0x%02x\n", + printf(" SPI Component Vendor ID: 0x%02x\n", jid & 0xff); - printf(" SPI Componend Device ID 0: 0x%02x\n", + printf(" SPI Component Device ID 0: 0x%02x\n", (jid >> 8) & 0xff); - printf(" SPI Componend Device ID 1: 0x%02x\n", + printf(" SPI Component Device ID 1: 0x%02x\n", (jid >> 16) & 0xff); } From cdabc407cde7a7ccea46390b8ed0cfb7b95c826b Mon Sep 17 00:00:00 2001 From: John Su Date: Mon, 10 Feb 2020 13:59:27 +0800 Subject: [PATCH 0043/1463] mb/google/drallion: Set cpu_pl2_4_cfg to baseline for Drallion Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg. BUG=b:148912093 BRANCH=None TEST=build coreboot and checked IA_TDC from TAT tool. Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Mathew King --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 92f3fb9772..cdb6288173 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -65,6 +65,9 @@ chip soc/intel/cannonlake register "PchHdaIDispCodecDisconnect" = "1" register "PchHdaAudioLinkHda" = "1" + # Select CPU PL2/PL4 config + register "cpu_pl2_4_cfg" = "baseline" + # VR Settings Configuration for 2/4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | From b143e677ee8df130fec1456a47e30f3088139974 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Fri, 7 Feb 2020 22:27:58 +0530 Subject: [PATCH 0044/1463] src/soc/tigerlake: Accomodate JSP specific changes in iomap.h Updating MCH, GSPI And I2C base addresses for JSP in iomap header. BUG=None BRANCH=None TEST=Compilation for Jasper lake board is working Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb Signed-off-by: Meera Ravindranath Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/38754 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/include/soc/iomap.h | 29 ++++++++++++++++----- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 2e61477dd4..f403873f10 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -42,12 +42,6 @@ UART_BASE_SIZE * (x))) #define UART_BASE(x) UART_BASE_0_ADDR(x) -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -#define MCH_BASE_ADDRESS 0xfedc0000 -#define MCH_BASE_SIZE 0x20000 - #define DMI_BASE_ADDRESS 0xfeda0000 #define DMI_BASE_SIZE 0x1000 @@ -66,7 +60,6 @@ #define PCH_PWRM_BASE_SIZE 0x10000 #define SPI_BASE_ADDRESS 0xfe010000 -#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 #define GPIO_BASE_SIZE 0x10000 @@ -78,6 +71,28 @@ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) +#if CONFIG(SOC_INTEL_TIGERLAKE) + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#else /* CONFIG_SOC_INTEL_JASPERLAKE */ + +#define MCH_BASE_ADDRESS 0xfea80000 +#define MCH_BASE_SIZE 0x8000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + +#endif + /* * I/O port address space */ From 75909184fefac9ade704f9cfe4bc220803ed39f3 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sat, 8 Feb 2020 06:55:48 +0530 Subject: [PATCH 0045/1463] soc/intel/skl: Rename me_hfs union into me_hfsts Rename below union tags for consistency: me_hfs2 -> me_hfsts2 me_hfs3 -> me_hfsts3 me_hfs6 -> me_hfsts6 TEST=Verified on Soraka Change-Id: Ibb53e6a5f2b95021f86b3e42e100b711b7d6e64e Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/38797 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/include/soc/me.h | 6 +++--- src/soc/intel/skylake/me.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index e8de30dde9..332340f860 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -147,7 +147,7 @@ union me_hfsts1 { } __packed fields; }; -union me_hfs2 { +union me_hfsts2 { u32 data; struct { u32 reserved1: 3; @@ -168,7 +168,7 @@ union me_hfs2 { } __packed fields; }; -union me_hfs3 { +union me_hfsts3 { u32 data; struct { u32 reserved1: 4; @@ -184,7 +184,7 @@ union me_hfs3 { #define ME_HFS6_FPF_NOT_COMMITTED 0x0 #define ME_HFS6_FPF_ERROR 0x2 -union me_hfs6 { +union me_hfsts6 { u32 data; struct { u32 reserved1: 30; diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 17a66bc618..b45234ec65 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -273,9 +273,9 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); void intel_me_status(void) { union me_hfsts1 hfs1; - union me_hfs2 hfs2; - union me_hfs3 hfs3; - union me_hfs6 hfs6; + union me_hfsts2 hfs2; + union me_hfsts3 hfs3; + union me_hfsts6 hfs6; if (!is_cse_enabled()) return; From 3e89b65c2cf634c1ba81da65d42aa64b53c5b244 Mon Sep 17 00:00:00 2001 From: John Su Date: Fri, 31 Jan 2020 14:02:40 +0800 Subject: [PATCH 0046/1463] mb/google/drallion/variants/drallion: Update thermal configuration for DPTF Follow thermal table for fine tuning. 1. Update PSV values for sensors. 2. Change PL1 min value from 4W to 5W. 3. Change PL1 max value from 15W to 12W. 4. Change PL2 min value from 15W to 12W. BUG=b:148627484 TEST=Built and tested on drallion Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40 Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Sumeet R Pawnikar --- .../variants/drallion/include/variant/acpi/dptf.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl index 4ecdf1a67e..6f114b7c8b 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -19,19 +19,19 @@ /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 64 +#define DPTF_TSR0_PASSIVE 67 #define DPTF_TSR0_CRITICAL 127 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 54 +#define DPTF_TSR1_PASSIVE 60 #define DPTF_TSR1_CRITICAL 127 /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 40 +#define DPTF_TSR2_PASSIVE 90 #define DPTF_TSR2_CRITICAL 127 #undef DPTF_ENABLE_FAN_CONTROL @@ -56,15 +56,15 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 4000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 5000, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ 100000, /* TimeWindowMinimum */ 100000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ + 12000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ 280000, /* TimeWindowMinimum */ 280000, /* TimeWindowMaximum */ From 3465d2730ba130f5aed18cb356d09e7104af2280 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 6 Feb 2020 15:31:04 +0530 Subject: [PATCH 0047/1463] src/intel: Define HFSTS3 register Changes: 1. Define HFSTS3 register across SoCs(apl/cnl/icl/tgl). 2. Define cse_is_hfs3_fw_sku_custom() which checks ME's Firmware SKU is Custom or not. TEST=Verified on hatch, soraka, bobba and iclrvp. Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/38798 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/soc/intel/apollolake/include/soc/me.h | 14 ++++++++++++++ src/soc/intel/cannonlake/include/soc/me.h | 14 ++++++++++++++ src/soc/intel/common/block/cse/cse.c | 7 +++++++ .../intel/common/block/include/intelblocks/cse.h | 6 ++++++ src/soc/intel/icelake/include/soc/me.h | 14 ++++++++++++++ src/soc/intel/tigerlake/include/soc/me.h | 13 +++++++++++++ 6 files changed, 68 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/me.h b/src/soc/intel/apollolake/include/soc/me.h index 7ac4deecfa..e1916f622e 100644 --- a/src/soc/intel/apollolake/include/soc/me.h +++ b/src/soc/intel/apollolake/include/soc/me.h @@ -40,4 +40,18 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + #endif /* _APOLLOLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 041769b19a..ba4a11a64c 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -44,6 +44,20 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + void dump_me_status(void *unused); #endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c82f3bdc7a..39c30e9cb3 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -270,6 +270,13 @@ bool cse_is_hfs1_com_soft_temp_disable(void) return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); } +bool cse_is_hfs3_fw_sku_custom(void) +{ + union me_hfsts3 hfs3; + hfs3.data = me_read_config32(PCI_ME_HFSTS3); + return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_CUSTOM; +} + /* Makes the host ready to communicate with CSE */ void cse_set_host_ready(void) { diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 6f8f4ff34c..af8d85272d 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -186,4 +186,10 @@ bool cse_is_hfs1_com_secover_mei_msg(void); */ bool cse_is_hfs1_com_soft_temp_disable(void); +/* + * Checks CSE's Firmware SKU is Custom or not. + * Returns true if CSE's Firmware SKU is Custom, otherwise false + */ +bool cse_is_hfs3_fw_sku_custom(void); + #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h index b1646a2716..1146fdf848 100644 --- a/src/soc/intel/icelake/include/soc/me.h +++ b/src/soc/intel/icelake/include/soc/me.h @@ -40,4 +40,18 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + #endif /* _ICELAKE_ME_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index 3baa0045bd..9bb41ca57b 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -40,4 +40,17 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; #endif /* _TIGERLAKE_ME_H_ */ From 9c26605353873165805ce611d93e259a8545853e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 15 Feb 2020 23:19:19 +0100 Subject: [PATCH 0048/1463] util/autoport: Fix typo Also reflow the paragraph in which the typo was hiding a bit. Change-Id: I2fea01fe23af21c2540fa90154ce29af3e74776b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38925 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Peter Lemenkov --- util/autoport/readme.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/autoport/readme.md b/util/autoport/readme.md index a964e06d87..9af08f40bc 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -355,9 +355,9 @@ Types are: ## `c*_acpower` and `c*_battery` -Which mwait states to match to which ACPI levels. Normall, there is no -need to modify anything unless your device has very special power -saving requirements. +Which mwait states to match to which ACPI levels. Normally, there is no +need to modify anything unless your device has very special power saving +requirements. ## `install_intel_vga_int15_handler` From 824b4b8a2038e91d008ac60919fbc742c3facc61 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 15 Feb 2020 09:27:11 +0100 Subject: [PATCH 0049/1463] payloads: Fix typos Change-Id: Ib7f1ba1766e5c972542ce7571a8aa3583c513823 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38911 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- payloads/coreinfo/cpuinfo_module.c | 2 +- payloads/libpayload/drivers/i8042/keyboard.c | 2 +- payloads/libpayload/drivers/serial/ipq40xx.c | 4 ++-- payloads/libpayload/drivers/serial/ipq806x.c | 4 ++-- payloads/libpayload/drivers/serial/qcs405.c | 4 ++-- payloads/libpayload/drivers/udc/dwc2.c | 4 ++-- payloads/libpayload/drivers/usb/dwc2.c | 2 +- payloads/libpayload/drivers/usb/ehci.c | 6 +++--- payloads/libpayload/drivers/usb/ohci.c | 4 ++-- payloads/libpayload/drivers/usb/usb.c | 4 ++-- payloads/libpayload/drivers/usb/usbhub.c | 2 +- payloads/libpayload/drivers/usb/usbmsc.c | 4 ++-- payloads/libpayload/drivers/video/graphics.c | 2 +- payloads/libpayload/libc/args.c | 4 ++-- payloads/libpayload/libc/malloc.c | 2 +- payloads/libpayload/libc/readline.c | 2 +- payloads/libpayload/libc/string.c | 6 +++--- 17 files changed, 29 insertions(+), 29 deletions(-) diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index 94379f3077..2b833a9447 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -233,7 +233,7 @@ static int cpuinfo_module_redraw(WINDOW *win) } if (cpu_khz != 0) - mvwprintw(win, row++, 1, "CPU Speed: %d Mhz", cpu_khz / 1000); + mvwprintw(win, row++, 1, "CPU Speed: %d MHz", cpu_khz / 1000); else mvwprintw(win, row++, 1, "CPU Speed: Error"); diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 79455cfe7b..f96f28a3c8 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -349,7 +349,7 @@ static int set_scancode_set(void) /* * Set default parameters. - * Fix for broken QEMU ps/2 make scancodes. + * Fix for broken QEMU PS/2 make scancodes. */ ret = keyboard_cmd(I8042_KBCMD_SET_DEFAULT); if (!ret) { diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 7656ad73e0..5a9079b46b 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -442,7 +442,7 @@ static unsigned int msm_boot_uart_dm_reset(void *base) } /* - * msm_boot_uart_dm_init - initilaizes UART controller + * msm_boot_uart_dm_init - Initializes UART controller * @uart_dm_base: UART controller base address */ unsigned int msm_boot_uart_dm_init(void *uart_dm_base) @@ -550,7 +550,7 @@ int serial_getchar(void) static struct console_input_driver consin = {}; static struct console_output_driver consout = {}; -/* For simplicity sake let's rely on coreboot initalizing the UART. */ +/* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { struct cb_serial *sc_ptr = lib_sysinfo.serial; diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c index 183ada6563..ef4ce80849 100644 --- a/payloads/libpayload/drivers/serial/ipq806x.c +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -235,7 +235,7 @@ static unsigned int msm_boot_uart_dm_reset(void *base) } /* - * msm_boot_uart_dm_init - initilaizes UART controller + * msm_boot_uart_dm_init - Initializes UART controller * @uart_dm_base: UART controller base address */ static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) @@ -340,7 +340,7 @@ int serial_getchar(void) return byte; } -/* For simplicity sake let's rely on coreboot initalizing the UART. */ +/* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { struct cb_serial *sc_ptr = lib_sysinfo.serial; diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c index 06ec5b9e1d..1a7b9e901b 100644 --- a/payloads/libpayload/drivers/serial/qcs405.c +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -434,7 +434,7 @@ static unsigned int msm_boot_uart_dm_reset(void *base) } /* - * msm_boot_uart_dm_init - initilaizes UART controller + * msm_boot_uart_dm_init - Initializes UART controller * @uart_dm_base: UART controller base address */ unsigned int msm_boot_uart_dm_init(void *uart_dm_base) @@ -538,7 +538,7 @@ int serial_getchar(void) return byte; } -/* For simplicity sake let's rely on coreboot initalizing the UART. */ +/* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { struct cb_serial *sc_ptr = lib_sysinfo.serial; diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index e95eb7938d..025c0710fe 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -253,7 +253,7 @@ static void dwc2_halt_ep(struct usbdev_ctrl *this, int ep, int in_dir) usb_debug("dwc2_halt_ep ep %d-%d\n", ep, in_dir); depctl.d32 = readl(&ep_reg->depctl); - /*Alread disabled*/ + /* Already disabled */ if (!depctl.epena) return; /* First step: disable EP */ @@ -558,7 +558,7 @@ static void dwc2_outep_intr(struct usbdev_ctrl *this, dwc2_ep_t *ep) writel(DXEPINT_AHBERR, &ep->ep_regs->depint); } - /* Handle Setup Phase Done (Contorl Ep) */ + /* Handle Setup Phase Done (Control Ep) */ if (depint.setup) { usb_debug("DEPINT_SETUP\n"); writel(DXEPINT_SETUP, &ep->ep_regs->depint); diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 963ae84762..eef486bcc9 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -233,7 +233,7 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, packet_size = ep->maxpacketsize; packet_cnt = ALIGN_UP(size, packet_size) / packet_size; inpkt_length = packet_cnt * packet_size; - /* At least 1 packet should be programed */ + /* At least 1 packet should be programmed */ packet_cnt = (packet_cnt == 0) ? 1 : packet_cnt; /* diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 68763402af..1cfa8bb6d6 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -78,7 +78,7 @@ static void dump_qh(ehci_qh_t *cur) usb_debug("+===================================================+\n"); usb_debug("| ############# EHCI QH at [0x%08lx] ########### |\n", virt_to_phys(cur)); usb_debug("+---------------------------------------------------+\n"); - usb_debug("| Horizonal Link Pointer [0x%08lx] |\n", cur->horiz_link_ptr); + usb_debug("| Horizontal Link Pointer [0x%08lx] |\n", cur->horiz_link_ptr); usb_debug("+------------------[ 0x%08lx ]-------------------+\n", cur->epchar); usb_debug("| | Maximum Packet Length | [%04ld] |\n", ((cur->epchar & (0x7ffUL << 16)) >> 16)); usb_debug("| | Device Address | [%ld] |\n", cur->epchar & 0x7F); @@ -133,7 +133,7 @@ static void ehci_reset (hci_t *controller) { short count = 0; ehci_stop(controller); - /* wait 10 ms just to be shure */ + /* wait 10 ms just to be sure */ mdelay(10); if (EHCI_INST(controller)->operation->usbsts & HC_OP_HC_HALTED) { EHCI_INST(controller)->operation->usbcmd = HC_OP_HC_RESET; @@ -215,7 +215,7 @@ static int fill_td(qtd_t *td, void* data, int datalen) total_len += page_len; while (page_no < 5) { - /* we have a continguous mapping between virtual and physical memory */ + /* we have a contiguous mapping between virtual and physical memory */ page += 4096; td->bufptrs[page_no++] = page; diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index f1dc081656..2571273378 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -66,7 +66,7 @@ dump_td (td_t *cur) usb_debug("|:| C | Condition Code | [%02ld] |:|\n", (cur->config & (0xFUL << 28)) >> 28); usb_debug("|:| O | Direction/PID | [%ld] |:|\n", (cur->config & (3UL << 19)) >> 19); usb_debug("|:| N | Buffer Rounding | [%ld] |:|\n", (cur->config & (1UL << 18)) >> 18); - usb_debug("|:| F | Delay Intterrupt | [%ld] |:|\n", (cur->config & (7UL << 21)) >> 21); + usb_debug("|:| F | Delay Interrupt | [%ld] |:|\n", (cur->config & (7UL << 21)) >> 21); usb_debug("|:| I | Data Toggle | [%ld] |:|\n", (cur->config & (3UL << 24)) >> 24); usb_debug("|:| G | Error Count | [%ld] |:|\n", (cur->config & (3UL << 26)) >> 26); usb_debug("|:+-----------------------------------------------+:|\n"); @@ -879,7 +879,7 @@ ohci_process_done_queue(ohci_t *const ohci, const int spew_debug) intrq_td_t *const td = INTRQ_TD_FROM_TD(done_td); intr_queue_t *const intrq = td->intrq; /* Check if the corresponding interrupt - queue is still beeing processed. */ + queue is still being processed. */ if (intrq->destroy) { /* Free this TD, and */ free(td); diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 4004def9d9..d98fd9e2bc 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -499,7 +499,7 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) break; } - /* Gather up all endpoints belonging to this inteface */ + /* Gather up all endpoints belonging to this interface */ dev->num_endp = 1; for (; ptr + 2 <= end && ptr[0] && ptr + ptr[0] <= end; ptr += ptr[0]) { if (ptr[1] == DT_INTF || ptr[1] == DT_CFG || @@ -654,7 +654,7 @@ usb_detach_device(hci_t *controller, int devno) controller->devices[devno]->configuration = NULL; /* Tear down the device itself *after* destroy_device() - * has had a chance to interoogate it. */ + * has had a chance to interrogate it. */ free(controller->devices[devno]); controller->devices[devno] = NULL; } diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index 87c58169c5..5c39eac3d9 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -285,7 +285,7 @@ usb_hub_init(usbdev_t *const dev) return; } - /* Get number of ports from hub decriptor */ + /* Get number of ports from hub descriptor */ int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; /* won't fit the whole thing, we don't care */ if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index d8b7bcea6e..50fd24b1f8 100755 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -538,7 +538,7 @@ usb_msc_test_unit_ready (usbdev_t *dev) time_t start_time_secs; struct timeval tv; /* SCSI/ATA specs say we have to wait up to 30s, but most devices - * are ready much sooner. Use a 5 sec timeout to better accomodate + * are ready much sooner. Use a 5 sec timeout to better accommodate * devices which fail to respond. */ const int timeout_secs = 5; @@ -569,7 +569,7 @@ usb_msc_test_unit_ready (usbdev_t *dev) MSC_INST (dev)->ready = USB_MSC_NOT_READY; } - /* Don't bother spinning up the stroage device if the device is not + /* Don't bother spinning up the storage device if the device is not * ready. This can happen when empty card readers are present. * Polling will pick it back up if readiness changes. */ if (!MSC_INST (dev)->ready) diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index d346e4b733..8cb984b872 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -509,7 +509,7 @@ static int draw_bitmap_v3(const struct vector *top_left, * When d hits the right bottom corner, s0 also hits the right bottom * corner of the pixel array because that's how scale->x and scale->y * have been set. Since the pixel array size is already validated in - * parse_bitmap_header_v3, s0 is guranteed not to exceed pixel array + * parse_bitmap_header_v3, s0 is guaranteed not to exceed pixel array * boundary. */ struct vector s0, s1, d; diff --git a/payloads/libpayload/libc/args.c b/payloads/libpayload/libc/args.c index 663d767dc5..3839c629af 100644 --- a/payloads/libpayload/libc/args.c +++ b/payloads/libpayload/libc/args.c @@ -52,7 +52,7 @@ int string_argc; * * @param caller to be used as argv[0] (may be NULL to ignore) * @param string to process - * @return 0 if no error occured. + * @return 0 if no error occurred. */ int string_to_args(char *caller, char *string) { @@ -66,7 +66,7 @@ int string_to_args(char *caller, char *string) /* Terminate if the string ends */ while (string && *string) { - /* whitespace occured? */ + /* whitespace occurred? */ if ((*string == ' ') || (*string == '\t')) { /* skip all whitespace (and null it) */ while (*string == ' ' || *string == '\t') diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 510758970e..1fdb59e9b1 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -318,7 +318,7 @@ void *realloc(void *ptr, size_t size) struct align_region_t { - /* If alignment is 0 then the region reqpresents a large region which + /* If alignment is 0 then the region represents a large region which * has no metadata for tracking subelements. */ int alignment; /* start in memory, and size in bytes */ diff --git a/payloads/libpayload/libc/readline.c b/payloads/libpayload/libc/readline.c index 9387e09149..7324e04666 100644 --- a/payloads/libpayload/libc/readline.c +++ b/payloads/libpayload/libc/readline.c @@ -129,7 +129,7 @@ char *readline(const char *prompt) if (ch < 0x20) break; - /* ignore unprintables */ + /* ignore unprintable characters */ if (ch >= 0x7f) break; diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index 0e34a036b0..9309223da1 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -268,7 +268,7 @@ size_t strlcat(char *d, const char *s, size_t n) * * @param s The string. * @param c The character. - * @return A pointer to the first occurence of the character in the + * @return A pointer to the first occurrence of the character in the * string, or NULL if the character was not encountered within the string. */ char *strchr(const char *s, int c) @@ -288,7 +288,7 @@ char *strchr(const char *s, int c) * * @param s The string. * @param c The character. - * @return A pointer to the last occurence of the character in the + * @return A pointer to the last occurrence of the character in the * string, or NULL if the character was not encountered within the string. */ @@ -327,7 +327,7 @@ char *strdup(const char *s) * * @param h The haystack string. * @param n The needle string (substring). - * @return A pointer to the first occurence of the substring in + * @return A pointer to the first occurrence of the substring in * the string, or NULL if the substring was not encountered within the string. */ char *strstr(const char *h, const char *n) From 984d0c6afe09360ca4894c12204d21e77a564ef6 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Wed, 4 Dec 2019 15:33:57 +0800 Subject: [PATCH 0050/1463] vboot: rename GBB flag FAFT_KEY_OVERIDE to FLAG_RUNNING_FAFT This was renamed in vboot_reference CL:1977902. BUG=b:124141368, chromium:965914 TEST=make clean && make test-abuild BRANCH=none Change-Id: I79af304e9608a30c6839cd616378c7330c3de00a Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/37462 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/security/vboot/Kconfig | 4 ++-- src/security/vboot/Makefile.inc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 54e88dd594..28639529bb 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -307,8 +307,8 @@ config GBB_FLAG_FORCE_DEV_BOOT_LEGACY bool "Allow booting to legacy in dev mode even if dev_boot_legacy=0" default n -config GBB_FLAG_FAFT_KEY_OVERIDE - bool "Allow booting using alternative keys for FAFT servo testing" +config GBB_FLAG_RUNNING_FAFT + bool "Running FAFT tests; used as a hint to disable other debug features" default n config GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 2fe2d92900..138273fe4b 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -226,7 +226,7 @@ GBB_FLAGS := $(call int-add, \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FW_ROLLBACK_CHECK),0x20) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_ENTER_TRIGGERS_TONORM),0x40) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_DEV_BOOT_LEGACY),0x80) \ - $(call bool-to-mask,$(CONFIG_GBB_FLAG_FAFT_KEY_OVERIDE),0x100) \ + $(call bool-to-mask,$(CONFIG_GBB_FLAG_RUNNING_FAFT),0x100) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC),0x200) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY),0x400) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC),0x800) \ From 6ca5b475bf286ee8827edee64df5d14b09d936cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 10 Sep 2019 15:10:22 +0200 Subject: [PATCH 0051/1463] nb/amd/pi/00730F01: enable ACS and AER for PCIe ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable Access Control Services and Advanced Error Reporting for PCI Express bridges in order to have PCIe devices in separate IOMMU groups for correct passthrough. TEST=run dmesg on Debian Buster on PC Engines apu2 and check whether PCIe devices have separate groups Signed-off-by: Michał Żygowski Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35313 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/northbridge/amd/pi/00730F01/northbridge.c | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e5a75e8b80..cf4d78b4a6 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -37,6 +37,8 @@ #include #define MAX_NODE_NUMS MAX_NODES +#define PCIE_CAP_AER BIT(5) +#define PCIE_CAP_ACS BIT(6) typedef struct dram_base_mask { u32 base; //[47:27] at [28:8] @@ -777,6 +779,35 @@ static void fam16_finalize(void *chip_info) pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + /* + * Currently it is impossible to enable ACS with AGESA by setting the + * correct bit for AmdInitMid phase. AGESA code path does not call the + * right function that enables these functionalities. Disabled ACS + * result in multiple PCIe devices to be assigned to the same IOMMU + * group. Without IOMMU group separation the devices cannot be passed + * through independently. + */ + + /* Select GPP link core IO Link Strap Control register 0xB0 */ + pci_write_config32(dev, 0xE0, 0x014000B0); + value = pci_read_config32(dev, 0xE4); + + /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ + value |= PCIE_CAP_AER | PCIE_CAP_ACS; + pci_write_config32(dev, 0xE4, value); + + /* Select GPP link core Wrapper register 0x00 (undocumented) */ + pci_write_config32(dev, 0xE0, 0x01300000); + value = pci_read_config32(dev, 0xE4); + + /* + * Enable ACS capabilities straps including sub-items. From lspci it + * looks like these bits enable: Source Validation and Translation + * Blocking + */ + value |= (BIT(24) | BIT(25) | BIT(26)); + pci_write_config32(dev, 0xE4, value); + /* disable No Snoop */ dev = pcidev_on_root(1, 1); if (dev != NULL) { From 2f2c7ebfb4059220179cd16e2c7d0f422fbe5841 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 2 Jan 2020 16:11:27 -0800 Subject: [PATCH 0052/1463] soc/intel/tigerlake: Enable Audio on TGL Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Wonkyu Kim --- .../variants/jslrvp/devicetree.cb | 2 +- src/soc/intel/tigerlake/chip.h | 24 +++++++++---------- .../intel/tigerlake/romstage/fsp_params_tgl.c | 13 ++++++++++ 3 files changed, 25 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fb636251da..843de142b3 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -46,7 +46,7 @@ chip soc/intel/tigerlake register "gen3_dec" = "0x00fc0901" register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkHdaEnable" = "1" # PCIe port 1 for M.2 E-key WLAN register "PcieRpEnable[1]" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 4f57b0e07a..75a399fc27 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -30,6 +30,10 @@ #include #include +#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 + struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ @@ -99,20 +103,14 @@ struct soc_intel_tigerlake_config { uint8_t SataPortsDevSlp[8]; /* Audio related */ - uint8_t PchHdaEnable; uint8_t PchHdaDspEnable; - - /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ - uint8_t PchHdaAudioLinkHda; - uint8_t PchHdaAudioLinkDmic0; - uint8_t PchHdaAudioLinkDmic1; - uint8_t PchHdaAudioLinkSsp0; - uint8_t PchHdaAudioLinkSsp1; - uint8_t PchHdaAudioLinkSsp2; - uint8_t PchHdaAudioLinkSndw1; - uint8_t PchHdaAudioLinkSndw2; - uint8_t PchHdaAudioLinkSndw3; - uint8_t PchHdaAudioLinkSndw4; + uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; + uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; + uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispLinkTmode; + uint8_t PchHdaIDispLinkFrequency; + uint8_t PchHdaIDispCodecDisconnect; /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index fc3155f8ad..8b32bc056b 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -119,6 +119,19 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; + + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) From 8407d4f12e6d32771af4ff5aaee752682a0c8f43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicol=C3=B2=20Veronese?= Date: Mon, 23 Dec 2019 20:44:43 +0100 Subject: [PATCH 0053/1463] mb/google/slippy: Fix IRQ of the ambient light sensor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change based on google/auron that is similar to peppy. This will be helpful for the next follow-up commit that will add ACPI for the ambient light sensor. Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3 Signed-off-by: Nicolò Veronese Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/google/slippy/onboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 9e1dc8bf69..7c40e23183 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -17,7 +17,7 @@ #define ONBOARD_H #define BOARD_LIGHTSENSOR_NAME "lightsensor" -#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */ +#define BOARD_LIGHTSENSOR_IRQ 35 /* PIRQT */ #define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */ #define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 From fab9ae8167cc1f830452bb3da0157736fb7d4245 Mon Sep 17 00:00:00 2001 From: Nicola Corna Date: Mon, 18 Feb 2019 17:44:18 +0100 Subject: [PATCH 0054/1463] ec/lenovo/h8/acpi: Add alternative Fn-F2 and Fn-F3 layout thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and the lock hotkey (KEY_COFFEE) on scancode 0x02. On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2 and Fn-F3 are different from the default one so a new layout has to be defined. Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/ec/lenovo/h8/acpi/ec.asl | 21 ++++++++++++++++++++ src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 1 + 2 files changed, 22 insertions(+) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cfe1f..5a116818df 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -195,6 +195,26 @@ Device(EC) ^HKEY.RHK (0x01) } + /* + * Alternative layout (like in the Thinkpad X1 Carbon 1st generation): + * * Fn-F2 (_Q11) -> not mapped + * * Fn-F3 (_Q12) -> scancode 0x01 (KEY_COFFEE) + * + * Default layout (like in the Thinkpad X220): + * * Fn-F2 (_Q11) -> scancode 0x01 (KEY_COFFEE) + * * Fn-F3 (_Q12) -> scancode 0x02 (KEY_BATTERY) + */ +#ifdef EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT + Method (_Q11, 0, NotSerialized) + { + // Not mapped + } + + Method (_Q12, 0, NotSerialized) + { + ^HKEY.RHK (0x02) + } +#else Method (_Q11, 0, NotSerialized) { ^HKEY.RHK (0x02) @@ -204,6 +224,7 @@ Device(EC) { ^HKEY.RHK (0x03) } +#endif Method (_Q64, 0, NotSerialized) { diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index de6866d1ad..29235d77a1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -20,6 +20,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 +#define EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT 1 #include DefinitionBlock( From b39bc2510e2ef21d652f3bc3812669ab47b7a185 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 22 Jan 2020 18:48:39 +0100 Subject: [PATCH 0055/1463] Documentation/superio: add formatting to generic PNP documentation Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38519 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/superio/common/pnp.md | 46 ++++++++++++++--------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/Documentation/superio/common/pnp.md b/Documentation/superio/common/pnp.md index 314cac27ed..3c17259e58 100644 --- a/Documentation/superio/common/pnp.md +++ b/Documentation/superio/common/pnp.md @@ -15,13 +15,13 @@ specification is still the main reference though. Super I/O chips connected via LPC to the southbridge usually have their I/O-mapped configuration interface with a size of two bytes at the base -address 0x2e or 0x4e. Other PNP devices have their configuration +address `0x2e` or `0x4e`. Other PNP devices have their configuration interface at other addresses. The two byte registers allow access to an indirect 256 bytes big -register space that contains the configuration. By writing the index -to the lower byte (e.g. 0x2e), you can access the register contents at -that index by reading/writing the higher byte (e.g. 0x2f). +register space that contains the configuration. By writing the index to +the lower byte (e.g. `0x2e`), you can access the register contents at +that index by reading/writing the higher byte (e.g. `0x2f`). To prevent accidental changes of the Super I/O (SIO) configuration, the SIOs need a configuration mode unlock sequence. After changing the @@ -31,18 +31,18 @@ the configuration mode lock sequence. ## Logical device numbers (LDN) Each PNP device can contain multiple logical devices. The bytes from -0x00 to 0x2f in the indirect configuration register space are common -for all LDNs, but some SIO chips require a certain LDN to be selected -in order to write certain registers in there. An LDN gets selected by -writing the LDN number to the LDN select register 0x07. Registers 0x30 -to 0xFF are specific to each LDN number. +`0x00` to `0x2f` in the indirect configuration register space are common +for all LDNs, but some SIO chips require a certain LDN to be selected in +order to write certain registers in there. An LDN gets selected by +writing the LDN number to the LDN select register `0x07`. Registers +`0x30` to `0xff` are specific to each LDN number. coreboot encodes the physical LDN number in the lower byte of the LDN number. ### Virtual logical device numbers -Register 0x30 is the LDN enable register and since it is an 8 bit +Register `0x30` is the LDN enable register and since it is an 8 bit register, it can contain up to 8 enable bits for different parts of the functionality of that logical device. To set a certain enable bit in one physical LDN, the concept of virtual LDNs was introduced. @@ -54,7 +54,7 @@ part in the lower 3 bits of the higher byte of the LDN number. ## I/O resources -Starting at register address 0x60, each LDN has 2 byte wide I/O base +Starting at register address `0x60`, each LDN has 2 byte wide I/O base address registers. The size of an I/O resource is always a power of two. @@ -67,29 +67,29 @@ number of LSBs being zero, which can also be zero if the LSB is a one, the resource has N address bits and a size of 2\*\*N bytes. The mask address is also the highest possible address to map the I/O region. -A typical example for an I/O resource mask is 0x07f8 which is -0b0000011111111000 in binary notation. The three LSBs are zeros here, +A typical example for an I/O resource mask is `0x07f8` which is +`0b0000011111111000` in binary notation. The three LSBs are zeros here, so it's an eight byte I/O resource with three address offset bits inside the resource. The highest base address it can be mapped to is -0x07f8, so the region will end at 0x07ff. +`0x07f8`, so the region will end at `0x07ff`. The Super I/O datasheets typically contain the information about the I/O resource masks. On most Super I/O chips the mask can also be found -out by writing 0xffff to the corresponding I/O base address register +out by writing `0xffff` to the corresponding I/O base address register and reading back the value; since the lowest and highest bits are hard-wired to zero according to the I/O resource size and maximal possible I/O address, this gives the mask. ## IRQ resources -Each physical LDN has up to two configurable interrupt request -register pairs 0x70, 0x71 and 0x72, 0x73. Each pair can be configured -to use a certain IRQ number. Writing 1 to 15 into the first register +Each physical LDN has up to two configurable interrupt request register +pairs `0x70`, `0x71` and `0x72`, `0x73`. Each pair can be configured to +use a certain IRQ number. Writing 1 to 15 into the first register selects the IRQ number generated by the corresponding IRQ source and -enables IRQ generation; writing 0 to it disables the generation of -IRQs for the source. The second register selects the IRQ type (level -or edge) and IRQ level (high or low). For LPC SIOs the IRQ type is -hard-wired to edge. +enables IRQ generation; writing 0 to it disables the generation of IRQs +for the source. The second register selects the IRQ type (level or edge) +and IRQ level (high or low). For LPC SIOs the IRQ type is hard-wired to +edge. On the LPC bus a shared SERIRQ line is used to signal IRQs to the host; the IRQ number gets encoded by the number of LPC clock cycles @@ -106,7 +106,7 @@ number. The quiet mode is often broken. ## DRQ resources Each physical LDN has two legacy ISA-style DMA request channel -registers at 0x74 and 0x75. Those are only used for legacy devices +registers at `0x74` and `0x75`. Those are only used for legacy devices like parallel printer ports or floppy disk controllers. Each device using LPC legacy DMA needs its own LDMA line to the host. From c7a3152273ef3179e3ad5f66f53c4a9d2aa39c8e Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Sun, 16 Feb 2020 20:28:22 +0300 Subject: [PATCH 0056/1463] Documentation: ifdtool/layout: use real table for FD regions Current doc transpiles to something completely unreadable. Change-Id: I197deb52974c88e067bc1615986a42c889214888 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38933 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Patrick Georgi --- Documentation/ifdtool/layout.md | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 950db6f7ff..2513929db9 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -14,14 +14,26 @@ The names of the IFD regions in the FMAP should follow the convention of starting with the prefix `SI_` which stands for `silicon initialization` as a way to categorize anything required by the SoC but not provided by coreboot. -|IFD Region index|IFD Region name|FMAP Name|Notes| -|---|---|---|---| -|0|Flash Descriptor|SI_DESC|Always the top 4KB of flash| -|1|BIOS|SI_BIOS|This is the region that contains coreboot| -|2|Intel ME|SI_ME|| -|3|Gigabit Ethernet|SI_GBE|| -|4|Platform Data|SI_PDR|| -|8|EC Firmware|SI_EC|Most Chrome OS devices do not use this region; EC firmware is stored BIOS region of flash| +```eval_rst ++------------+------------------+-----------+-------------------------------------------+ +| IFD Region | IFD Region name | FMAP Name | Notes | +| index | | | | ++============+==================+===========+===========================================+ +| 0 | Flash Descriptor | SI_DESC | Always the top 4KB of flash | ++------------+------------------+-----------+-------------------------------------------+ +| 1 | BIOS | SI_BIOS | This is the region that contains coreboot | ++------------+------------------+-----------+-------------------------------------------+ +| 2 | Intel ME | SI_ME | | ++------------+------------------+-----------+-------------------------------------------+ +| 3 | Gigabit Ethernet | SI_GBE | | ++------------+------------------+-----------+-------------------------------------------+ +| 4 | Platform Data | SI_PDR | | ++------------+------------------+-----------+-------------------------------------------+ +| 8 | EC Firmware | SI_EC | Most Chrome OS devices do not use this | +| | | | region; EC firmware is stored in BIOS | +| | | | region of flash | ++------------+------------------+-----------+-------------------------------------------+ +``` ## Validation From 6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 16 Feb 2020 16:22:52 +0100 Subject: [PATCH 0057/1463] treewide: capitalize 'BIOS' Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/releases/coreboot-4.8.1-relnotes.md | 2 +- Documentation/soc/intel/fit.md | 2 +- Documentation/tutorial/part1.md | 2 +- payloads/external/SeaBIOS/Kconfig | 2 +- src/cpu/x86/smm/smm_module_loader.c | 2 +- src/device/Kconfig | 2 +- src/device/oprom/include/x86emu/x86emu.h | 2 +- src/drivers/intel/gma/int15.c | 2 +- src/mainboard/asus/p8z77-m_pro/cmos.layout | 2 +- src/mainboard/asus/p8z77-m_pro/early_init.c | 2 +- src/mainboard/google/cyan/Kconfig | 4 ++-- src/mainboard/google/link/mainboard.c | 6 +++--- src/mainboard/google/rambi/mainboard.c | 2 +- src/mainboard/intel/strago/Kconfig | 4 ++-- src/mainboard/kontron/ktqm77/mainboard.c | 6 +++--- src/mainboard/lenovo/t420/early_init.c | 2 +- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/common/block/fast_spi/fast_spi.c | 2 +- src/soc/intel/common/pch/lockdown/lockdown.c | 6 +++--- src/soc/intel/skylake/lockdown.c | 2 +- util/inteltool/inteltool.8 | 2 +- util/inteltool/spi.c | 2 +- 22 files changed, 30 insertions(+), 30 deletions(-) diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md index 8a6ab964e8..e2462365ac 100644 --- a/Documentation/releases/coreboot-4.8.1-relnotes.md +++ b/Documentation/releases/coreboot-4.8.1-relnotes.md @@ -40,7 +40,7 @@ possible Lenovo mainboards ----------------- -* Started integration of VBT (Video Bios Table) binary files to +* Started integration of VBT (Video BIOS Table) binary files to support native graphics initialisation Internal changes diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index 8b638f0433..553fef3c16 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -57,4 +57,4 @@ execution of the IA32 reset vector happens. ## References * [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf) -* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf) +* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf) diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 0c7ef67cbb..7e3da01572 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -173,7 +173,7 @@ Here's the command line instruction broken down: This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge. * `-bios build/coreboot.rom` -Use the bios rom image that we just built. If this flag is left out, the +Use the coreboot rom image that we just built. If this flag is left out, the standard SeaBIOS image that comes with QEMU is used. * `-serial stdio` Send the serial output to the console. This allows you to view the coreboot diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 8ec7361813..e816775f28 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -125,7 +125,7 @@ config SEABIOS_DEBUG_LEVEL level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts - level 4 - bios tables, more optionrom + level 4 - BIOS tables, more optionrom level 5 - Extra bootsplash, more XHCI level 6 - ATA commands, extra optionrom level 7 - extra ps2 commands, more OHCI & EHCI diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 66a40c4233..ca6f611959 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -396,7 +396,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - // account for the bios resource list + // account for the BIOS resource list if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; diff --git a/src/device/Kconfig b/src/device/Kconfig index a25bb911c9..603c7eb8d1 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -721,7 +721,7 @@ config INTEL_GMA_HAVE_VBT config INTEL_GMA_ADD_VBT depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON - bool "Add a Video Bios Table (VBT) binary to CBFS" + bool "Add a Video BIOS Table (VBT) binary to CBFS" default y if INTEL_GMA_HAVE_VBT help Add a VBT data file to CBFS. The VBT describes the integrated diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index 4ae82d96ff..e7f48e4ade 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -170,7 +170,7 @@ void X86EMU_halt_sys(void); #define DEBUG_SVC_F 0x000020 #define DEBUG_FS_F 0x000080 #define DEBUG_PROC_F 0x000100 -#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 #define DEBUG_MEM_TRACE_F 0x001000 diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 7e0ece3382..11efe8c57d 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -33,7 +33,7 @@ int intel_vga_int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = pfit; diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index da29d1c10e..4ac7b5d2eb 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -77,7 +77,7 @@ entries 421 2 e 8 usb3_mode # usb3_drv -# Load (or not) pre-OS xHCI USB3 bios driver +# Load (or not) pre-OS xHCI USB3 BIOS driver # 423 1 e 1 usb3_drv diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 800d975d0f..6c76a7ac29 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -115,7 +115,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ + .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ .dimm_channel0_disabled = 0, /* Both DIMM enabled */ .dimm_channel1_disabled = 0, /* Both DIMM enabled */ diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6331419cd3..94ffbc0bad 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -78,7 +78,7 @@ config VGA_BIOS_FILE depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run. @@ -87,7 +87,7 @@ config VGA_BIOS_ID depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 config CBFS_SIZE diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 8be4012263..32e5487278 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -47,10 +47,10 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; - X86_CL = 0x00; /* Use video bios default */ + X86_CL = 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -66,7 +66,7 @@ static int int15_handler(void) * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0000; /* Use video bios default */ + X86_CX = 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d4e38d0532..7e9b343880 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -48,7 +48,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = 0x0001; diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 5e710a52bf..640f5d4e91 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -35,7 +35,7 @@ config VGA_BIOS_FILE depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run. @@ -44,7 +44,7 @@ config VGA_BIOS_ID depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 config EC_GOOGLE_CHROMEEC_BOARDNAME diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 2af5eb239f..5cd3fc4234 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -41,12 +41,12 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffffff00; - X86_ECX |= 0x00; /* Use video bios default */ + X86_ECX |= 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -64,7 +64,7 @@ static int int15_handler(void) X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; /* Use video bios default */ + X86_ECX |= 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 2e39885b6b..c675512d6f 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -48,7 +48,7 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d9c42f9c20..b9c5a4fa27 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -733,7 +733,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; - /* Bios config lockdown Audio clk and power gate */ + /* BIOS config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; if (CONFIG(SOC_INTEL_GLK)) glk_fsp_silicon_init_params_cb(cfg, silconfig); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 019976ad8c..49284e9489 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -237,7 +237,7 @@ void fast_spi_cache_bios_region(void) /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will * cause memory type conflict when setting memory type to write - * protection, so limit the cached bios region to be no more than 16MB. + * protection, so limit the cached BIOS region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); if (bios_size <= 0) diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 4a3209e03e..3fa6e77042 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -69,12 +69,12 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown) /* Lock FAST_SPIBAR */ fast_spi_lock_bar(); - /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* Bios Interface Lock */ + /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down(); - /* Bios Lock */ + /* BIOS Lock */ fast_spi_set_lock_enable(); } } diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 66dae8c73c..6911744bcb 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -22,7 +22,7 @@ static void lpc_lockdown_config(int chipset_lockdown) { - /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 86a76bdc9a..01e3cfd7f2 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -32,7 +32,7 @@ Show only GPIO register differences from hardware defaults. Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "\-s, \-\-spi" -Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. +Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control. .TP .B "\-f, \-\-gfx" .RB "Dump graphics registers. " \ diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 22ba3d42f2..e8289acaf3 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -22,7 +22,7 @@ static const io_register_t pch_bios_cntl_registers[] = { { 0x1, 1, "BLE - lock enable" }, { 0x2, 2, "SPI Read configuration" }, { 0x4, 1, "TopSwapStatus" }, - { 0x5, 1, "SMM Bios Write Protect Disable" }, + { 0x5, 1, "SMM BIOS Write Protect Disable" }, { 0x6, 2, "reserved" }, }; From f9e10f26ba0c35c99a2781fc9c6bddaca385bf3d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 16 Feb 2020 11:28:11 +0100 Subject: [PATCH 0058/1463] Documentation: Remove confusing xyz0 naming convention for Lenovo devices Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge. Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s. Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: Patrick Georgi --- Documentation/mainboard/index.md | 4 ++-- .../mainboard/lenovo/{xx30_series.md => Ivy_Bridge_series.md} | 4 +++- .../lenovo/{xx20_series.md => Sandy_Bridge_series.md} | 2 +- .../{flashlayout_xx30.svg => flashlayout_Ivy_Bridge.svg} | 0 .../{flashlayout_xx20.svg => flashlayout_Sandy_Bridge.svg} | 0 Documentation/mainboard/lenovo/t420.md | 2 +- Documentation/mainboard/lenovo/t430.md | 2 +- Documentation/mainboard/lenovo/t431s.md | 2 +- Documentation/mainboard/lenovo/w530.md | 2 +- Documentation/mainboard/lenovo/x1.md | 2 +- 10 files changed, 11 insertions(+), 9 deletions(-) rename Documentation/mainboard/lenovo/{xx30_series.md => Ivy_Bridge_series.md} (96%) rename Documentation/mainboard/lenovo/{xx20_series.md => Sandy_Bridge_series.md} (97%) rename Documentation/mainboard/lenovo/{flashlayout_xx30.svg => flashlayout_Ivy_Bridge.svg} (100%) rename Documentation/mainboard/lenovo/{flashlayout_xx20.svg => flashlayout_Sandy_Bridge.svg} (100%) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index ce30ee2f1c..3e69119edc 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -82,7 +82,7 @@ The boards in this section are not real mainboards, but emulators. ### Sandy Bridge series - [T420](lenovo/t420.md) -- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md) +- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) - [x1](lenovo/x1.md) ### Ivy Bridge series @@ -90,7 +90,7 @@ The boards in this section are not real mainboards, but emulators. - [T430](lenovo/t430.md) - [T530](lenovo/w530.md) - [W530](lenovo/w530.md) -- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) +- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md) - [T431s](lenovo/t431s.md) - [Internal flashing](lenovo/ivb_internal_flashing.md) diff --git a/Documentation/mainboard/lenovo/xx30_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md similarity index 96% rename from Documentation/mainboard/lenovo/xx30_series.md rename to Documentation/mainboard/lenovo/Ivy_Bridge_series.md index ad856057f0..2f83ffa8a8 100644 --- a/Documentation/mainboard/lenovo/xx30_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -1,5 +1,7 @@ # Lenovo Ivy Bridge series +This information is valid for all supported models, except T430s and T431s. + ## Flashing coreboot ```eval_rst +---------------------+--------------------------------+ @@ -72,5 +74,5 @@ region. The update is then written into the EC once. ![][fl] -[fl]: flashlayout_xx30.svg +[fl]: flashlayout_Ivy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/xx20_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md similarity index 97% rename from Documentation/mainboard/lenovo/xx20_series.md rename to Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 8603853b94..0b833f5cc8 100644 --- a/Documentation/mainboard/lenovo/xx20_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -44,5 +44,5 @@ region. The update is then written into the EC once. ![][fl] -[fl]: flashlayout_xx20.svg +[fl]: flashlayout_Sandy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/flashlayout_xx30.svg b/Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg similarity index 100% rename from Documentation/mainboard/lenovo/flashlayout_xx30.svg rename to Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/flashlayout_xx20.svg b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg similarity index 100% rename from Documentation/mainboard/lenovo/flashlayout_xx20.svg rename to Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 831cb58765..40665b4db9 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -22,4 +22,4 @@ For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md index 787246f4d4..1ef4460f5c 100644 --- a/Documentation/mainboard/lenovo/t430.md +++ b/Documentation/mainboard/lenovo/t430.md @@ -12,4 +12,4 @@ For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md index 146e1c12a3..48315a2459 100644 --- a/Documentation/mainboard/lenovo/t431s.md +++ b/Documentation/mainboard/lenovo/t431s.md @@ -39,4 +39,4 @@ inteltool, and replace the content of the SPD hex with what is dumped. I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md index f91d9cee6a..3b54303a73 100644 --- a/Documentation/mainboard/lenovo/w530.md +++ b/Documentation/mainboard/lenovo/w530.md @@ -24,4 +24,4 @@ For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and [w530-2]: w530-2.jpg -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/x1.md b/Documentation/mainboard/lenovo/x1.md index cb9248a4e4..9758197a02 100644 --- a/Documentation/mainboard/lenovo/x1.md +++ b/Documentation/mainboard/lenovo/x1.md @@ -21,4 +21,4 @@ For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and Steps to access the flash IC are described here [X2xx series]. [X2xx series]: x2xx_series.md -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md From f6be41a988e0143d5cb3629e445c14f6b9b127ac Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 16 Feb 2020 11:35:05 +0100 Subject: [PATCH 0059/1463] Documentation/lenovo: Replace RST code with markdown Latest Sphinx supports up path traversal in markdown. Replace old RST code that's no longer needed to prevent it being copy and pasted. Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38930 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- Documentation/mainboard/lenovo/t420.md | 6 ++---- Documentation/mainboard/lenovo/t430.md | 5 ++--- Documentation/mainboard/lenovo/t431s.md | 4 +--- Documentation/mainboard/lenovo/w530.md | 5 ++--- Documentation/mainboard/lenovo/x1.md | 6 ++---- Documentation/mainboard/lenovo/x301.md | 9 ++++++--- 6 files changed, 15 insertions(+), 20 deletions(-) diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 40665b4db9..00ce45f69a 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -14,12 +14,10 @@ W25Q64CVSIG. Do not rely on dots painted in the corner of the chip (such as the blue dot pictured) to orient the pins! For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and - -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md index 1ef4460f5c..c2cddca053 100644 --- a/Documentation/mainboard/lenovo/t430.md +++ b/Documentation/mainboard/lenovo/t430.md @@ -5,11 +5,10 @@ You have to disassemble the whole device, as the flash ICs are on the bottom of the mainboard. For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. Steps to access the flash IC are described here [T4xx series]. +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T4xx series]: t4xx_series.md [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md index 48315a2459..f177e0f452 100644 --- a/Documentation/mainboard/lenovo/t431s.md +++ b/Documentation/mainboard/lenovo/t431s.md @@ -26,9 +26,7 @@ the programmer. ![t431s_programming](t431s_programming.jpg) -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +The general [flashing tutorial] has more details. Currently, detecting the model of soldered RAM at runtime and loading the corresponding SPD datum from CBFS is not implemented yet. You may diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md index 3b54303a73..e3fe6b8d4f 100644 --- a/Documentation/mainboard/lenovo/w530.md +++ b/Documentation/mainboard/lenovo/w530.md @@ -10,9 +10,7 @@ As all lines except /CS are shared between the flash ICs you can access both with an external programmer. For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. ### After removing the keyboard and palm rest ![][w530-1] @@ -24,4 +22,5 @@ For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and [w530-2]: w530-2.jpg +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/x1.md b/Documentation/mainboard/lenovo/x1.md index 9758197a02..9f915bc07f 100644 --- a/Documentation/mainboard/lenovo/x1.md +++ b/Documentation/mainboard/lenovo/x1.md @@ -13,12 +13,10 @@ The flash IC can be a SOIC-8 one or a WSON-8 one, and may be covered with a piece of insulation tape. For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and - -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. Steps to access the flash IC are described here [X2xx series]. [X2xx series]: x2xx_series.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/x301.md b/Documentation/mainboard/lenovo/x301.md index 28b512d24d..89b422f978 100644 --- a/Documentation/mainboard/lenovo/x301.md +++ b/Documentation/mainboard/lenovo/x301.md @@ -26,9 +26,8 @@ The vendor IFD VSCC list contains: -WINBOND_NEX_W25X64 (0xef, 0x3017) -ATMEL_AT25DF641 (0x1f, 0x4800) -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +The general [flashing tutorial] has more details. + Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung @@ -42,3 +41,7 @@ Tested: - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. + + +[flashing tutorial]: ../../flash_tutorial/ext_power.md + From b3a247cccac77f761bc2cf64089e465d7a53dad8 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Sun, 16 Feb 2020 22:19:57 +0300 Subject: [PATCH 0060/1463] Documentation: mb/lenovo: Make X1 uppercase x1 -> X1. Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38935 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/mainboard/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3e69119edc..126a8fb875 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -83,7 +83,7 @@ The boards in this section are not real mainboards, but emulators. - [T420](lenovo/t420.md) - [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) -- [x1](lenovo/x1.md) +- [X1](lenovo/x1.md) ### Ivy Bridge series From 1e7da75b77c4bad048a7638f57b0ed5d75a59e9b Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Fri, 14 Feb 2020 08:51:10 -0700 Subject: [PATCH 0061/1463] volteer: allow empty SPD_SOURCES Some Volteer variants might not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Signed-off-by: Paul Fagerburg Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/spd/Makefile.inc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc index c4b9e99afc..9f0106ba83 100644 --- a/src/mainboard/google/volteer/spd/Makefile.inc +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -6,13 +6,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## +ifneq ($(SPD_SOURCES),) SPD_BIN = $(obj)/spd.bin -ifeq ($(SPD_SOURCES),) - SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) -endif +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) # Include spd ROM data $(SPD_BIN): $(SPD_DEPS) @@ -25,3 +22,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +endif From bda161b4b5744f98a8b5dfe71c584197f642e1ff Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Thu, 13 Feb 2020 13:04:48 -0600 Subject: [PATCH 0062/1463] nb/intel/sandybridge: use list of northbridge device IDs Change-Id: Ida311a7b0c1f33b1724a07c7cd64ea9834cfc179 Signed-off-by: Jonathan A. Kollasch Reviewed-on: https://review.coreboot.org/c/coreboot/+/38882 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../intel/sandybridge/northbridge.c | 28 ++++--------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a9b1c251d0..68f8411366 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -460,34 +460,16 @@ static struct device_operations mc_ops = { .acpi_fill_ssdt_generator = generate_cpu_entries, }; -static const struct pci_driver mc_driver_0100 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0100, +static const unsigned short pci_device_ids[] = { + 0x0100, 0x0104, /* Sandy Bridge */ + 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ + 0 }; static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0104, /* Sandy bridge */ -}; - -static const struct pci_driver mc_driver_150 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0150, /* Ivy bridge */ -}; - -static const struct pci_driver mc_driver_1 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0154, /* Ivy bridge */ -}; - -static const struct pci_driver mc_driver_158 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0158, /* Ivy bridge */ + .devices = pci_device_ids, }; static struct device_operations cpu_bus_ops = { From d346a19dedf28aecc4a2bce7ab9ee08323b63a1c Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Tue, 11 Feb 2020 09:03:48 -0600 Subject: [PATCH 0063/1463] nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Signed-off-by: Jonathan A. Kollasch Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 68f8411366..cc8a62ced1 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -461,7 +461,7 @@ static struct device_operations mc_ops = { }; static const unsigned short pci_device_ids[] = { - 0x0100, 0x0104, /* Sandy Bridge */ + 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ 0 }; From 214fb9b511faaa59716a1b65a43438781f6237ef Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Fri, 14 Feb 2020 17:16:53 +0800 Subject: [PATCH 0064/1463] security/vboot: Correct help text of VBOOT_STARTS_IN_ROMSTAGE Since CB:37231 [1], the vboot working data has been replaced with vboot work buffer, so corrrect the help text of option VBOOT_STARTS_IN_ROMSTAGE accordingly. [1] security/vboot: Remove struct vboot_working_data BRANCH=none BUG=chromium:1021452 TEST=none Change-Id: I80783274179ae7582bbb4c8f9d392895623badce Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/38900 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- src/security/vboot/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 28639529bb..e366cc4c09 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -114,8 +114,8 @@ config VBOOT_STARTS_IN_ROMSTAGE depends on !VBOOT_STARTS_IN_BOOTBLOCK help Firmware verification happens during the end of romstage (after - memory initialization). This implies that vboot working data is - allocated in CBMEM. + memory initialization). This implies that the vboot work buffer is + in CBMEM from the start and doesn't need to be reserved in memlayout. config VBOOT_MOCK_SECDATA bool "Mock secdata for firmware verification" From eb3cd856106dae68da4aae39f9954fb90770e8a2 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 22 Jan 2020 16:52:13 -0700 Subject: [PATCH 0065/1463] ec/google/chromeec: Add SSDT generator for ChromeOS EC Upcoming patches for the Linux kernel (5.6 ?) would like to consume information about the USB PD ports that are attached to the device. This information is obtained from the CrOS EC and exposed in the SSDT ACPI table. Also, the device enable for this PCI device is moved from ec_lpc.c to a new file, ec_chip.c, where EC-related ACPI methods can live. It still allows other code to call functions on device enable (so that PnP enable for the LPC device still gets called). BUG=b:146506369 BRANCH=none TEST=Verify the SSDT contains the expected information Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/Makefile.inc | 1 + src/ec/google/chromeec/ec.c | 27 +++- src/ec/google/chromeec/ec.h | 23 +++ src/ec/google/chromeec/ec_chip.c | 228 ++++++++++++++++++++++++++++ src/ec/google/chromeec/ec_lpc.c | 7 +- 5 files changed, 278 insertions(+), 8 deletions(-) create mode 100644 src/ec/google/chromeec/ec_chip.c diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index f2e0034bc2..4994480baa 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -24,6 +24,7 @@ verstage-y += ec.c crosec_proto.c vstore.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c ramstage-$(CONFIG_VBOOT) += vboot_storage.c smm-$(CONFIG_VBOOT) += vboot_storage.c diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 1d351c5875..81e68d0f96 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -29,9 +29,7 @@ #include #include -#include "chip.h" #include "ec.h" -#include "ec_commands.h" #define INVALID_HCMD 0xFF @@ -1527,3 +1525,28 @@ int google_chromeec_wait_for_displayport(long timeout) return 1; } + +#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY +static struct device_operations ec_chromeec_ops = { + .acpi_name = google_chromeec_acpi_name, + .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, +}; +#endif + +/* ec_lpc, ec_spi, or ec_i2c can override this */ +__weak void google_ec_enable_extra(struct device *dev) +{ +} + +static void google_chromeec_enable(struct device *dev) +{ +#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY + dev->ops = &ec_chromeec_ops; +#endif + google_ec_enable_extra(dev); +} + +struct chip_operations ec_google_chromeec_ops = { + CHIP_NAME("Google Chrome EC") + .enable_dev = google_chromeec_enable +}; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 5ce375e00b..7341636819 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -18,6 +18,7 @@ #ifndef _EC_GOOGLE_CHROMEEC_EC_H #define _EC_GOOGLE_CHROMEEC_EC_H #include +#include #include "ec_commands.h" /* Fill in base and size of the IO port resources used. */ @@ -329,4 +330,26 @@ struct usb_pd_port_caps { int google_chromeec_get_pd_port_caps(int port, struct usb_pd_port_caps *port_caps); +#if CONFIG(HAVE_ACPI_TABLES) +/** + * Writes USB Type-C PD related information to the SSDT + * + * @param dev EC device + */ +void google_chromeec_fill_ssdt_generator(struct device *dev); + +/** + * Returns the ACPI name for the EC device. + * + * @param dev EC device + */ +const char *google_chromeec_acpi_name(const struct device *dev); + +#endif /* HAVE_ACPI_TABLES */ + +/* + * Allows bus-specific EC code to perform actions when the device is enabled. + */ +void google_ec_enable_extra(struct device *dev); + #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ diff --git a/src/ec/google/chromeec/ec_chip.c b/src/ec/google/chromeec/ec_chip.c new file mode 100644 index 0000000000..db78bdb853 --- /dev/null +++ b/src/ec/google/chromeec/ec_chip.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "ec.h" +#include "ec_commands.h" + +#define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" +#define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" + +const char *google_chromeec_acpi_name(const struct device *dev) +{ + return "EC0"; +} + +static const char *power_role_to_str(enum ec_pd_power_role_caps power_role) +{ + switch (power_role) { + case EC_PD_POWER_ROLE_SOURCE: + return "source"; + case EC_PD_POWER_ROLE_SINK: + return "sink"; + case EC_PD_POWER_ROLE_DUAL: + return "dual"; + default: + return "unknown"; + } +} + +static const char *try_power_role_to_str(enum ec_pd_try_power_role_caps try_power_role) +{ + switch (try_power_role) { + case EC_PD_TRY_POWER_ROLE_NONE: + /* + * This should never get returned; if there is no try-power role for a device, + * then the try-power-role field is not added to the DSD. Thus, this is just + * for completeness. + */ + return "none"; + case EC_PD_TRY_POWER_ROLE_SINK: + return "sink"; + case EC_PD_TRY_POWER_ROLE_SOURCE: + return "source"; + default: + return "unknown"; + } +} + +static const char *data_role_to_str(enum ec_pd_data_role_caps data_role) +{ + switch (data_role) { + case EC_PD_DATA_ROLE_DFP: + return "host"; + case EC_PD_DATA_ROLE_UFP: + return "device"; + case EC_PD_DATA_ROLE_DUAL: + return "dual"; + default: + return "unknown"; + } +} + +/* + * Apparently these are supposed to be uppercase, in contrast to the other + * lowercase fields. + */ +static const char *port_location_to_str(enum ec_pd_port_location port_location) +{ + switch (port_location) { + case EC_PD_PORT_LOCATION_LEFT: + return "LEFT"; + case EC_PD_PORT_LOCATION_RIGHT: + return "RIGHT"; + case EC_PD_PORT_LOCATION_BACK: + return "BACK"; + case EC_PD_PORT_LOCATION_FRONT: + return "FRONT"; + case EC_PD_PORT_LOCATION_LEFT_FRONT: + return "LEFT_FRONT"; + case EC_PD_PORT_LOCATION_LEFT_BACK: + return "LEFT_BACK"; + case EC_PD_PORT_LOCATION_RIGHT_FRONT: + return "RIGHT_FRONT"; + case EC_PD_PORT_LOCATION_RIGHT_BACK: + return "RIGHT_BACK"; + case EC_PD_PORT_LOCATION_BACK_LEFT: + return "BACK_LEFT"; + case EC_PD_PORT_LOCATION_BACK_RIGHT: + return "BACK_RIGHT"; + case EC_PD_PORT_LOCATION_UNKNOWN: /* intentional fallthrough */ + default: + return "UNKNOWN"; + } +} + +/* Add port capabilities as DP properties */ +static void add_port_caps(struct acpi_dp *dsd, const struct usb_pd_port_caps *port_caps) +{ + acpi_dp_add_string(dsd, "power-role", power_role_to_str(port_caps->power_role_cap)); + + if (port_caps->try_power_role_cap != EC_PD_TRY_POWER_ROLE_NONE) + acpi_dp_add_string(dsd, "try-power-role", + try_power_role_to_str(port_caps->try_power_role_cap)); + + acpi_dp_add_string(dsd, "data-role", data_role_to_str(port_caps->data_role_cap)); + acpi_dp_add_string(dsd, "port-location", port_location_to_str( + port_caps->port_location)); +} + +/* + * Helper for fill_ssdt_generator. This adds references to the USB + * port objects so that the consumer of this information can know + * whether the port supports USB2 and/or USB3. + */ +static void add_usb_port_references(struct acpi_dp *dsd, int port_number) +{ + static const char usb2_port[] = "usb2-port"; + static const char usb3_port[] = "usb3-port"; + struct device *port = NULL; + const char *path; + const char *usb_port_type; + struct drivers_usb_acpi_config *config; + + /* + * Unfortunately, the acpi_dp_* API doesn't write out the data immediately, thus we need + * different storage areas for all of the strings, so strdup() is used for that. It is + * safe to use strdup() here, because the strings are generated at build-time and are + * guaranteed to be NUL-terminated (they come from the devicetree). + */ + while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) { + if (!port->enabled || port->path.type != DEVICE_PATH_USB) + continue; + + /* Looking for USB 2 & 3 port devices only */ + if (port->path.usb.port_type == 2) + usb_port_type = usb2_port; + else if (port->path.usb.port_type == 3) + usb_port_type = usb3_port; + else + continue; + + config = port->chip_info; + + /* + * Look at only USB Type-C ports, making sure they match the + * port number we're looking for (the 'token' field in 'group'). + * Also note that 'port_number' is 0-based, whereas the 'token' + * field is 1-based. + */ + if ((config->type != UPC_TYPE_C_USB2_ONLY) && + (config->type != UPC_TYPE_C_USB2_SS_SWITCH) && + (config->type != UPC_TYPE_C_USB2_SS)) + continue; + + if (config->group.token != (port_number + 1)) + continue; + + path = acpi_device_path(port); + if (path) { + path = strdup(path); + if (!path) + continue; + + acpi_dp_add_reference(dsd, usb_port_type, path); + } + } +} + +static void fill_ssdt_typec_device(struct device *dev) +{ + struct usb_pd_port_caps port_caps; + char con_name[] = "CONx"; + struct acpi_dp *dsd; + int num_ports; + int rv; + int i; + + rv = google_chromeec_get_num_pd_ports(&num_ports); + if (rv) + return; + + acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); + acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); + acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " + "USB Type-C Control"); + + for (i = 0; i < num_ports; ++i) { + rv = google_chromeec_get_pd_port_caps(i, &port_caps); + if (rv) + continue; + + con_name[3] = (char)i + '0'; + acpigen_write_device(con_name); + acpigen_write_name_integer("_ADR", i); + + /* _DSD, Device-Specific Data */ + dsd = acpi_dp_new_table("_DSD"); + + acpi_dp_add_integer(dsd, "port-number", i); + add_port_caps(dsd, &port_caps); + add_usb_port_references(dsd, i); + + acpi_dp_write(dsd); + acpigen_pop_len(); /* Device CONx */ + } + + acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ +} + +void google_chromeec_fill_ssdt_generator(struct device *dev) +{ + /* Reference the existing device's scope */ + acpigen_write_scope(acpi_device_path(dev)); + fill_ssdt_typec_device(dev); + acpigen_pop_len(); /* Scope */ +} diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 6bc4fbd310..9afb1fd653 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -458,16 +458,11 @@ static struct pnp_info pnp_dev_info[] = { { NULL, 0, 0, 0, } }; -static void enable_dev(struct device *dev) +void google_ec_enable_extra(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") - .enable_dev = enable_dev, -}; - static int google_chromeec_data_ready(u16 port) { return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, From 5bf7ffbe0814528436cfef5bdca00c1ef7f584d1 Mon Sep 17 00:00:00 2001 From: Usha P Date: Mon, 17 Feb 2020 15:07:53 +0530 Subject: [PATCH 0066/1463] cpu/x86/name: Make name.c file available in romstage In this patch, name.c file that includes the function definition for fill_processor_name which is used by the report_cpu_info function is been made available in romstage. This is done to facilitate the report_platform_info to be called from romstage, as the intention is to move the report_platform_info to romstage for all SOC's due to the bootblock size constraint. BUG=None TEST=Build and boot APL, GLK and CNL platforms. Change-Id: Ifd6d4b80c2e07d02adaed676a56efeb6fb704552 Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/38940 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/cpu/x86/name/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 944c18f87f..02b5863192 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -12,4 +12,5 @@ ## bootblock-y += name.c +romstage-y += name.c ramstage-y += name.c From 206905c309a6a7643a61633d0563ad1245fe7f93 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 6 Feb 2020 18:48:22 +0530 Subject: [PATCH 0067/1463] soc/intel/common: Check prerequisites for HMRFPO_GET_STATUS command Send HMRFPO_GET_STATUS command when CSE's current working state is Normal. TEST=Verified on hatch. Change-Id: I4380e5096c6346d88aae6826d19a2f4ed1e97036 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/38799 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/soc/intel/common/block/cse/cse.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 39c30e9cb3..afce985fa8 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -713,6 +713,11 @@ int cse_hmrfpo_get_status(void) printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); + if (!cse_is_hfs1_cws_normal()) { + printk(BIOS_ERR, "HECI: CSE's current working state is not Normal\n"); + return -1; + } + if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), &resp, &resp_size)) { printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); From 09ea37172eb62d2b675b3d7a1db36c697c49a6da Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Tue, 12 Nov 2019 23:35:50 +0530 Subject: [PATCH 0068/1463] soc/intel/common: Add function to wait for CSE to enter Soft Temp Disable mode Below helper function is added: cse_wait_com_soft_temp_disable() - It polls for CSE's operation mode 'Soft Temporary Disable'. CSE enters this mode when it boots from RO(BP1) partition. The function must be called after resetting CSE to wait for CSE to enter 'Soft Temporary Disable' Mode. BUG=b:145809764 Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/36786 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/soc/intel/common/block/cse/cse.c | 23 +++++++++++++++++++ .../common/block/include/intelblocks/cse.h | 5 ++++ 2 files changed, 28 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index afce985fa8..5877d537f8 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -68,6 +68,9 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) +/* Wait up to 5 seconds for CSE to boot from RO(BP1) */ +#define CSE_DELAY_BOOT_TO_RO (5 * 1000) + static struct cse_device { uintptr_t sec_bar; } cse; @@ -304,6 +307,26 @@ uint8_t cse_wait_sec_override_mode(void) return 1; } +/* + * Polls for CSE's current operation mode 'Soft Temporary Disable'. + * The CSE enters the current operation mode when it boots from RO(BP1). + */ +uint8_t cse_wait_com_soft_temp_disable(void) +{ + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO); + while (!cse_is_hfs1_com_soft_temp_disable()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: Timed out waiting for CSE to boot from RO!\n"); + return 0; + } + } + printk(BIOS_SPEW, "HECI: CSE took %lu ms to boot from RO\n", + stopwatch_duration_msecs(&sw)); + return 1; +} + static int wait_heci_ready(void) { struct stopwatch sw; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index af8d85272d..c597a3f46f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -192,4 +192,9 @@ bool cse_is_hfs1_com_soft_temp_disable(void); */ bool cse_is_hfs3_fw_sku_custom(void); +/* + * Polls for CSE's current operation mode 'Soft Temp Disable'. + * Returns 0 on failure and 1 on success. + */ +uint8_t cse_wait_com_soft_temp_disable(void); #endif // SOC_INTEL_COMMON_CSE_H From 2e7c2cef15c88f000380668e8948e71b7d8d7f75 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 5 Feb 2020 12:20:21 +0100 Subject: [PATCH 0069/1463] mb/facebook/monolith: Enable use of VPD Enable use of VPD for monolith. This will be used to store the UUID and Serial number. BUG=N/A TEST=build Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/monolith/Kconfig | 1 + src/mainboard/facebook/monolith/vboot-ro.fmd | 5 +++-- src/mainboard/facebook/monolith/vboot-rw.fmd | 5 +++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 203f8a5d25..b6c9f1939c 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_IFD_GBE_REGION select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE + select VPD config CBFS_SIZE hex "CBFS_SIZE" diff --git a/src/mainboard/facebook/monolith/vboot-ro.fmd b/src/mainboard/facebook/monolith/vboot-ro.fmd index 4abd883f22..569971aade 100644 --- a/src/mainboard/facebook/monolith/vboot-ro.fmd +++ b/src/mainboard/facebook/monolith/vboot-ro.fmd @@ -13,12 +13,13 @@ FLASH 16M { RW_NVRAM(PRESERVE)@0x012000 0x6000 } WP_RO@0x20000 0x8E0000 { - RO_SECTION@0x0000 0x8E0000 { + RO_VPD(PRESERVE)@0x00000 0x1000 + RO_SECTION@0x1000 0x8DF000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x4000 - COREBOOT(CBFS)@0x5000 0x8DB000 + COREBOOT(CBFS)@0x5000 0x8DA000 } } } diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd index df2674b93d..dc2dadfa9c 100644 --- a/src/mainboard/facebook/monolith/vboot-rw.fmd +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -18,12 +18,13 @@ FLASH 16M { FW_MAIN_A(CBFS)@0x10040 0x84FFC0 } WP_RO@0x880000 0x080000 { - RO_SECTION@0x0000 0x80000 { + RO_VPD(PRESERVE)@0x00000 0x1000 + RO_SECTION@0x1000 0x7F000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x4000 - COREBOOT(CBFS)@0x5000 0x07B000 + COREBOOT(CBFS)@0x5000 0x07A000 } } } From 5bf7b1ac69e796ff508325eab2b8c27cc782372d Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 4 Feb 2020 13:21:41 +0100 Subject: [PATCH 0070/1463] mb/facebook/monolith: Use serial number and UUID from VPD The serial number and UUID returned by DMI are retrieved from VPD. The solution supports a 16 character "serial_number" and a 36 character "UUID" string. BUG=N/A TEST=tested on monolith Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/monolith/ramstage.c | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c index bed104956f..05cbf31adc 100644 --- a/src/mainboard/facebook/monolith/ramstage.c +++ b/src/mainboard/facebook/monolith/ramstage.c @@ -14,7 +14,14 @@ * GNU General Public License for more details. */ +#include +#include +#include +#include +#include #include +#include + #include "gpio.h" void mainboard_silicon_init_params(FSP_SIL_UPD *params) @@ -24,3 +31,30 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; } + +#define VPD_KEY_SERIAL "serial_number" +#define VPD_KEY_UUID "UUID" +#define VPD_SERIAL_LEN 17 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + + if (vpd_gets(VPD_KEY_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + + printk(BIOS_ERR, "serial_number could not be read or invalid.\n"); + return ""; +} + +void smbios_system_set_uuid(u8 *uuid) +{ + static char vpd_uuid_string[UUID_STRLEN+1]; + + if (vpd_gets(VPD_KEY_UUID, vpd_uuid_string, UUID_STRLEN+1, VPD_RO)) + if (!parse_uuid(uuid, vpd_uuid_string)) + return; + + memset(uuid, 0, UUID_LEN); + printk(BIOS_ERR, "UUID could not be read or invalid.\n"); +} From 900a254475f5a057ce41e3dbcec33ff6999d8df6 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 17 Feb 2020 16:52:40 +0100 Subject: [PATCH 0071/1463] util/amdfwtool: Improve comment's grammar Change-Id: I2daa57c1982346e48dbd91a94864baf2f11c2129 Signed-off-by: Patrick Georgi Reported-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38944 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/amdfwtool/amdfwtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 522d332bbd..379caaab5a 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1439,7 +1439,7 @@ int main(int argc, char **argv) integrate_firmwares(&ctx, amd_romsig, amd_fw_table); - ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is necessary? */ + ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ if (multi) { /* Do 2nd PSP directory followed by 1st */ From 286b07ca33dfc827463d1b701dc3cb2457f13bf4 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Tue, 18 Feb 2020 03:41:25 +0300 Subject: [PATCH 0072/1463] Documentation: Fix style issues on Lenovo X301 page - Fix lists markup - Some minor fixes in the text (e.g. lowercases) Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38948 Reviewed-by: Patrick Georgi Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- Documentation/mainboard/lenovo/x301.md | 30 +++++++++++++------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/Documentation/mainboard/lenovo/x301.md b/Documentation/mainboard/lenovo/x301.md index 89b422f978..b273fc5a33 100644 --- a/Documentation/mainboard/lenovo/x301.md +++ b/Documentation/mainboard/lenovo/x301.md @@ -22,25 +22,25 @@ SOIC-8 one (you might need to add the chip to the IFD VSCC list), as what is done in the photo. The vendor IFD VSCC list contains: - -MACRONIX_MX25L6405 (0xc2, 0x2017) - -WINBOND_NEX_W25X64 (0xef, 0x3017) - -ATMEL_AT25DF641 (0x1f, 0x4800) +- MACRONIX_MX25L6405 (0xc2, 0x2017) +- WINBOND_NEX_W25X64 (0xef, 0x3017) +- ATMEL_AT25DF641 (0x1f, 0x4800) The general [flashing tutorial] has more details. Tested: - - CPU Core 2 Duo U9400 - - Slotted DIMM 4GiB*2 from samsung - - Camera - - pci-e slots - - sata and usb2 - - libgfxinit-based graphic init - - NVRAM options for North and South bridges - - Sound - - Thinkpad EC - - S3 - - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from - Linux payload (Heads) and Seabios. +- Core 2 Duo U9400 CPU +- Slotted DIMM 4GiB*2 from Samsung +- Camera +- PCI-e slots +- SATA and USB2 +- libgfxinit-based graphics init +- NVRAM options for North and South bridges +- Sound +- ThinkPad EC +- S3 +- Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from + Linux payload (Heads) and SeaBIOS. [flashing tutorial]: ../../flash_tutorial/ext_power.md From d1f7c6f2867ad7ede4af36ed42860a206538c550 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Tue, 28 Jan 2020 10:51:36 -0800 Subject: [PATCH 0073/1463] cpu: Allow to configure microcode at pre-defined address FSP-T takes microcode pointer and location parameters, and FSP-T is invoked before CAR is set-up and before memory is trained. So it is not possible to modify supplied microcode pointer in runtime. Because of that we have to hardcode the pointer in bootblock. Also, current FSP-T on Xeons require microcode (it is not optional). Reasons for that are currently unclear and are being investigated. However for the present time we need to be able to add microcode at a certain offset so FSP-T can be used. TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/cpu/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 4b5d67b908..0289be0297 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -60,3 +60,7 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode cpu_microcode_blob.bin-align := 16 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +endif From 52c89d302b9e85dd048e4d8f1a09c7fd50bcf7d7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 31 Jan 2020 22:42:23 +0100 Subject: [PATCH 0074/1463] mb/intel/glkrvp/chromeos.fmd: Correct indentation Tested with BUILD_TIMELESS, no changes. Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/intel/glkrvp/chromeos.fmd | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 5d4ba46b58..8f3c63a417 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -13,11 +13,11 @@ FLASH 16M { } } MISC_RW@0x400000 0x4a000 { - UNIFIED_MRC_CACHE@0x0 0x31000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - RW_VAR_MRC_CACHE@0x30000 0x1000 - } + UNIFIED_MRC_CACHE@0x0 0x31000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + RW_VAR_MRC_CACHE@0x30000 0x1000 + } RW_ELOG(PRESERVE)@0x31000 0x4000 RW_SHARED@0x35000 0x4000 { SHARED_DATA@0x0 0x2000 From 24d994afd227446087a24ae26bfe3df0df34767b Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Tue, 18 Feb 2020 06:30:16 +0000 Subject: [PATCH 0075/1463] Update vboot submodule to upstream master Updating from commit id 0e97e25e: 2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was meant to be) to commit id 8b9732f5: 2020-02-18 05:55:01 +0000 - (vboot: do not call vb2_commit_data at end of VBSLK) This brings in 36 new commits. Change-Id: Icb0ab2c82c3264185171a32357944949afd2edce Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/38953 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 0e97e25e85..8b9732f5fc 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 0e97e25e85f0499e23b09a31a2c7116759f191d5 +Subproject commit 8b9732f5fcccc1c568e821f144b7ccd94708b45d From 338e9dcd6bea50fce0c317ee497eb4acb620ce88 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 14 Feb 2020 15:41:11 +0800 Subject: [PATCH 0076/1463] vboot: use vb2api_get_recovery_reason function Use vb2api_get_recovery_reason() API function rather than accessing vb2_shared_data internals. Of all the vanilla verified boot code in coreboot, this is the last remaining use of vboot's internal data structures in coreboot. There remains only one sole instance in Eltan's code. BUG=b:124141368, chromium:957880 TEST=make clean && make test-abuild BRANCH=none Change-Id: I845c9b14ffa830bc7de28e9a38188f7066871803 Signed-off-by: Joel Kitching Cq-Depend: chromium:2055662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38886 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/security/vboot/bootmode.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 50b3cc3b6c..2363bf9588 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#define NEED_VB20_INTERNALS /* Peeking into vb2_shared_data */ - #include #include #include @@ -31,8 +29,7 @@ int vboot_check_recovery_request(void) { - /* TODO: Expose vb2api_recovery_reason() and vb2api_need_train_and_reboot(). */ - return vb2_get_sd(vboot_get_context())->recovery_reason; + return vb2api_get_recovery_reason(vboot_get_context()); } int vboot_recovery_mode_enabled(void) From 172ef5fe6182ade5fefed0e4f9e76c59fc89667d Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 14 Feb 2020 16:08:45 +0800 Subject: [PATCH 0077/1463] vboot: remove use of NEED_VB20_INTERNALS switch The NEED_VB20_INTERNALS switch is being deprecated. Use the header file vb2_internals_please_do_not_use.h instead. BUG=b:124141368, chromium:957880 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie35644876178b806fab4f0ce8089a556227312db Signed-off-by: Joel Kitching Cq-Depend: chromium:2055600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38887 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/vendorcode/eltan/security/verified_boot/vboot_check.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 2edd8f9a74..9d99e02e71 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -14,13 +14,12 @@ * GNU General Public License for more details. */ -#define NEED_VB20_INTERNALS - #include #include #include #include #include +#include #define RSA_PUBLICKEY_FILE_NAME "vboot_public_key.bin" From e549503967aab3aabe68f686f75ca316b6bd8bf6 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 17 Feb 2020 18:26:51 +0100 Subject: [PATCH 0078/1463] soc/intel/p2sb: Drop unnecessary P2SB_GET_DEV PCH_DEV_P2SB already covers both __SIMPLE_DEVICE__ cases. The values are only used for PCI-config access functions, which also check for NULL when necessary. The PCI_DEV_INVALID case can't occur by definition, and if we wanted to check, we could do so at compile time using _Static_assert(). Change-Id: I400fc20133809aaa0fd0519531a62ec9b8812ef1 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38946 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Subrata Banik --- src/soc/intel/common/block/p2sb/p2sb.c | 50 +++++++------------------- 1 file changed, 12 insertions(+), 38 deletions(-) diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 34b6e06cb5..c968409e0a 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -29,40 +29,14 @@ #define HIDE_BIT (1 << 0) -#if defined(__SIMPLE_DEVICE__) -static pci_devfn_t p2sb_get_device(void) -{ - int devfn = PCH_DEVFN_P2SB; - pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - if (dev == PCI_DEV_INVALID) - die_with_post_code(POST_HW_INIT_FAILURE, - "PCH_DEV_P2SB not found!\n"); - - return dev; -} -#else -static struct device *p2sb_get_device(void) -{ - struct device *dev = PCH_DEV_P2SB; - if (!dev) - die_with_post_code(POST_HW_INIT_FAILURE, - "PCH_DEV_P2SB not found!\n"); - - return dev; -} -#endif - -#define P2SB_GET_DEV p2sb_get_device() - void p2sb_enable_bar(void) { /* Enable PCR Base address in PCH */ - pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_0, P2SB_BAR); - pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_1, 0); + pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); + pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config8(P2SB_GET_DEV, PCI_COMMAND, + pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } @@ -79,7 +53,7 @@ void p2sb_configure_hpet(void) * the High Performance Timer memory address range * selected by bits 1:0 */ - pci_write_config8(P2SB_GET_DEV, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); + pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); } static void p2sb_set_hide_bit(int hide) @@ -88,18 +62,18 @@ static void p2sb_set_hide_bit(int hide) const uint8_t mask = HIDE_BIT; uint8_t val; - val = pci_read_config8(P2SB_GET_DEV, reg); + val = pci_read_config8(PCH_DEV_P2SB, reg); val &= ~mask; if (hide) val |= mask; - pci_write_config8(P2SB_GET_DEV, reg, val); + pci_write_config8(PCH_DEV_P2SB, reg, val); } void p2sb_unhide(void) { p2sb_set_hide_bit(0); - if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to unhide PCH_DEV_P2SB device !\n"); @@ -109,7 +83,7 @@ void p2sb_hide(void) { p2sb_set_hide_bit(1); - if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != 0xFFFF) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to hide PCH_DEV_P2SB device !\n"); @@ -119,8 +93,8 @@ static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) { uint32_t reg32; - reg32 = pci_read_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id), + reg32 = pci_read_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id)); + pci_write_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); } @@ -129,8 +103,8 @@ static void p2sb_lock_endpoints(void) uint8_t reg8; /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2); - pci_write_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2, + reg8 = pci_read_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2); + pci_write_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2, reg8 | P2SB_E0_MASKLOCK); } From abe96737745f84a0a33512e1eb62386d101a92d8 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Tue, 18 Feb 2020 15:03:05 +0300 Subject: [PATCH 0079/1463] Documentation: Use inline code block for kernel parameter Change-Id: I41649d4d0ee0abf9335f6cb3d7b19888c0c62382 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38955 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Peter Lemenkov --- Documentation/flash_tutorial/int_flashrom.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/flash_tutorial/int_flashrom.md b/Documentation/flash_tutorial/int_flashrom.md index 28b534b003..982aca287d 100644 --- a/Documentation/flash_tutorial/int_flashrom.md +++ b/Documentation/flash_tutorial/int_flashrom.md @@ -5,7 +5,7 @@ ## Using flashrom This method does only work on Linux, if it isn't locked down. -You may also need to boot with 'iomem=relaxed' in the kernel command +You may also need to boot with `iomem=relaxed` in the kernel command line if CONFIG_IO_STRICT_DEVMEM is set. From 5efe122b2776f168c5aa02cd91f56052608b1220 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Tue, 18 Feb 2020 14:59:08 +0300 Subject: [PATCH 0080/1463] Documentation: soc/amd/psp: Use real table markup Currently, tables on this page are formatted as code blocks with ASCII tables. Make it real beautiful tables. Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Peter Lemenkov --- Documentation/soc/amd/psp_integration.md | 265 ++++++++++++----------- 1 file changed, 136 insertions(+), 129 deletions(-) diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md index 5f53a39f05..9c7b1be404 100755 --- a/Documentation/soc/amd/psp_integration.md +++ b/Documentation/soc/amd/psp_integration.md @@ -37,38 +37,40 @@ any of the eligible locations. Below are typical definitions within the structure (for all families combined). Individual features supported vary by family and model. - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | Signature | 0x00 | 4 | 0x55aa55aa | - |--------------|---------------|------------------|----------------------------| - | IMC FW | 0x04 | 4 | Integrated Micro | - | | | | Controller: unsupported | - | | | | but functional in some | - | | | | systems | - |--------------|---------------|------------------|----------------------------| - | GbE FW | 0x08 | 4 | Gigabit Ethernet | - |--------------|---------------|------------------|----------------------------| - | xHCI FW | 0x0c | 4 | xHCI firmware | - |--------------|---------------|------------------|----------------------------| - | PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory | - | | | | Table (early devices) | - |--------------|---------------|------------------|----------------------------| - | PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory | - | | | | Table (later devices and | - | | | | is combo capable) | - |--------------|---------------|------------------|----------------------------| - | BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory | - | | | | Table for models n* | - |--------------|---------------|------------------|----------------------------| - | BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory | - | | | | Table for models nn | - |--------------|---------------|------------------|----------------------------| - | BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory | - | | | | Table for models nnn | - |--------------|---------------|------------------|----------------------------| - | … | | | ... | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | ++==============+===============+==================+============================+ +| Signature | 0x00 | 4 | 0x55aa55aa | ++--------------+---------------+------------------+----------------------------+ +| IMC FW | 0x04 | 4 | Integrated Micro | +| | | | Controller: unsupported | +| | | | but functional in some | +| | | | systems | ++--------------+---------------+------------------+----------------------------+ +| GbE FW | 0x08 | 4 | Gigabit Ethernet | ++--------------+---------------+------------------+----------------------------+ +| xHCI FW | 0x0c | 4 | xHCI firmware | ++--------------+---------------+------------------+----------------------------+ +| PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory | +| | | | Table (early devices) | ++--------------+---------------+------------------+----------------------------+ +| PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory | +| | | | Table (later devices and | +| | | | is combo capable) | ++--------------+---------------+------------------+----------------------------+ +| BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory | +| | | | Table for models n* | ++--------------+---------------+------------------+----------------------------+ +| BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory | +| | | | Table for models nn | ++--------------+---------------+------------------+----------------------------+ +| BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory | +| | | | Table for models nnn | ++--------------+---------------+------------------+----------------------------+ +| … | | | ... | ++--------------+---------------+------------------+----------------------------+ +``` * The Embedded Firmware Structure may support pointers to multiple generations of devices, e.g. Family 17h Models 00h-0Fh, Family 17h Models 10h-1Fh, etc. @@ -83,46 +85,47 @@ allowing secondary tables to be referenced by device ID. No coreboot implementations currently use combo tables. ### PSP Directory Table Header - - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to | - | | | | recognize the header. | - | | | | Cookie “$PL2” for level 2 | - |--------------|---------------|------------------|----------------------------| - | Checksum | 0x04 | 4 | 32-bit CRC value of header | - | | | | below this field and | - | | | | including all entries | - |--------------|---------------|------------------|----------------------------| - | Total Entries| 0x08 | 4 | Number of PSP Directory | - | | | | entries in the table | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x0C | 4 | Reserved - Set to zero | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | ++==============+===============+==================+============================+ +| PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to | +| | | | recognize the header. | +| | | | Cookie “$PL2” for level 2 | ++--------------+---------------+------------------+----------------------------+ +| Checksum | 0x04 | 4 | 32-bit CRC value of header | +| | | | below this field and | +| | | | including all entries | ++--------------+---------------+------------------+----------------------------+ +| Total Entries| 0x08 | 4 | Number of PSP Directory | +| | | | entries in the table | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x0C | 4 | Reserved - Set to zero | ++--------------+---------------+------------------+----------------------------+ +``` ### PSP Directory Table Entries - - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | Type | 0x00 | 8 | Entry type (see below) | - |--------------|---------------|------------------|----------------------------| - | Sub Program | 0x01 | 8 | Specifies sub program | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x02 | 16 | Reserved - set to 0 | - |--------------|---------------|------------------|----------------------------| - | Size | 0x04 | 32 | Size of PSP entry in bytes | - |--------------|---------------|------------------|----------------------------| - | Location / | 0x08 | 64 | Location: Physical Address | - | Value | | | of SPIROM location where | - | | | | corresponding PSP entry | - | | | | located. | - | | | | | - | | | | Value: 64-bit value for the| - | | | | PSP Entry | - +--------------+---------------+------------------+----------------------------+ - +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | ++==============+===============+==================+============================+ +| Type | 0x00 | 8 | Entry type (see below) | ++--------------+---------------+------------------+----------------------------+ +| Sub Program | 0x01 | 8 | Specifies sub program | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x02 | 16 | Reserved - set to 0 | ++--------------+---------------+------------------+----------------------------+ +| Size | 0x04 | 32 | Size of PSP entry in bytes | ++--------------+---------------+------------------+----------------------------+ +| Location / | 0x08 | 64 | Location: Physical Address | +| Value | | | of SPIROM location where | +| | | | corresponding PSP entry | +| | | | located. | +| | | | | +| | | | Value: 64-bit value for the| +| | | | PSP Entry | ++--------------+---------------+------------------+----------------------------+ +``` ### PSP Directory Table Types **0x00**: AMD public key @@ -248,68 +251,72 @@ The BIOS Directory table structure is slightly different from the PSP Directory: ### BIOS Directory Table Header - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to | - | | | | recognize the header. | - | | | | Cookie “$BL2” for level 2 | - |--------------|---------------|------------------|----------------------------| - | Checksum | 0x04 | 4 | 32 bit CRC value of header | - | | | | below this field and | - | | | | including all entries | - |--------------|---------------|------------------|----------------------------| - | Total Entries| 0x08 | 4 | Number of BIOS Directory | - | | | | entries in the table | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x0C | 4 | Reserved - Set to zero | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | ++==============+===============+==================+============================+ +| BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to | +| | | | recognize the header. | +| | | | Cookie “$BL2” for level 2 | ++--------------+---------------+------------------+----------------------------+ +| Checksum | 0x04 | 4 | 32 bit CRC value of header | +| | | | below this field and | +| | | | including all entries | ++--------------+---------------+------------------+----------------------------+ +| Total Entries| 0x08 | 4 | Number of BIOS Directory | +| | | | entries in the table | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x0C | 4 | Reserved - Set to zero | ++--------------+---------------+------------------+----------------------------+ +``` ### BIOS Directory Table Entries - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | Type | 0x00 | 8 | Entry type (see below) | - |--------------|---------------|------------------|----------------------------| - | Region Type | 0x01 | 8 | Setup the memory region's | - | | | | security attribute for the | - | | | | BIOS entry | - |--------------|---------------|------------------|----------------------------| - | Reset Image | 0x02[0] | 1 | Boolean value to define the| - | | | | BIOS entry is a reset | - | | | | binary image | - |--------------|---------------|------------------|----------------------------| - | Copy Image | 0x02[1] | 1 | Define the binary image of | - | | | | the BIOS entry is for | - | | | | copying over to the memory | - | | | | region | - |--------------|---------------|------------------|----------------------------| - | Read Only | 0x02[2] | 1 | Setup the memory region for| - | | | | the BIOS entry to read only| - |--------------|---------------|------------------|----------------------------| - | Compressed | 0x02[3] | 1 | Compressed using zlib | - | | | | | - |--------------|---------------|------------------|----------------------------| - | Instance | 0x02[7:4] | 4 | Specify the Instance of an | - | | | | entry | - |--------------|---------------|------------------|----------------------------| - | SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | - |--------------|---------------|------------------|----------------------------| - | Size | 0x04 | 32 | Memory Region Size | - |--------------|---------------|------------------|----------------------------| - | Source | 0x08 | 64 | Physical Address of SPIROM | - | Address | | | location where the data for| - | | | | the corresponding entry is | - | | | | located | - |--------------|---------------|------------------|----------------------------| - | Destination | 0x10 | 64 | Destination Address of | - | Address | | | memory location where the | - | | | | data for the corresponding | - | | | | BIOS Entry is copied | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | ++==============+===============+==================+============================+ +| Type | 0x00 | 8 | Entry type (see below) | ++--------------+---------------+------------------+----------------------------+ +| Region Type | 0x01 | 8 | Setup the memory region's | +| | | | security attribute for the | +| | | | BIOS entry | ++--------------+---------------+------------------+----------------------------+ +| Reset Image | 0x02[0] | 1 | Boolean value to define the| +| | | | BIOS entry is a reset | +| | | | binary image | ++--------------+---------------+------------------+----------------------------+ +| Copy Image | 0x02[1] | 1 | Define the binary image of | +| | | | the BIOS entry is for | +| | | | copying over to the memory | +| | | | region | ++--------------+---------------+------------------+----------------------------+ +| Read Only | 0x02[2] | 1 | Setup the memory region for| +| | | | the BIOS entry to read only| ++--------------+---------------+------------------+----------------------------+ +| Compressed | 0x02[3] | 1 | Compressed using zlib | +| | | | | ++--------------+---------------+------------------+----------------------------+ +| Instance | 0x02[7:4] | 4 | Specify the Instance of an | +| | | | entry | ++--------------+---------------+------------------+----------------------------+ +| SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | ++--------------+---------------+------------------+----------------------------+ +| Size | 0x04 | 32 | Memory Region Size | ++--------------+---------------+------------------+----------------------------+ +| Source | 0x08 | 64 | Physical Address of SPIROM | +| Address | | | location where the data for| +| | | | the corresponding entry is | +| | | | located | ++--------------+---------------+------------------+----------------------------+ +| Destination | 0x10 | 64 | Destination Address of | +| Address | | | memory location where the | +| | | | data for the corresponding | +| | | | BIOS Entry is copied | ++--------------+---------------+------------------+----------------------------+ +``` ### BIOS Directory Table Entry Types From f71c6ae216bb493275a4b6a20577c883f7575ca0 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 13 Feb 2020 13:55:42 +0530 Subject: [PATCH 0081/1463] soc/tigerlake: Add IRQ header and ACPI support for JSP Tigerlake irq.h and pci_irqs.asl have differences compared to Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as pci_irqs_tgl.asl Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake SoC and allowing irq.h and pci_irqs.asl to choose the correct file based on SoC selected. BUG=None BRANCH=None TEST=Compilation for Jasperlake board is working Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/acpi/pci_irqs.asl | 157 +--------------- src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl | 142 +++++++++++++++ src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl | 168 ++++++++++++++++++ src/soc/intel/tigerlake/include/soc/irq.h | 69 +------ src/soc/intel/tigerlake/include/soc/irq_jsl.h | 87 +++++++++ src/soc/intel/tigerlake/include/soc/irq_tgl.h | 84 +++++++++ 6 files changed, 491 insertions(+), 216 deletions(-) create mode 100644 src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl create mode 100644 src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl create mode 100644 src/soc/intel/tigerlake/include/soc/irq_jsl.h create mode 100644 src/soc/intel/tigerlake/include/soc/irq_tgl.h diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 8aadf8db6a..d3230b4aa9 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -14,155 +14,8 @@ * GNU General Public License for more details. */ -#include - -Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ - Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, - Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, ISH_IRQ }, - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, - Package(){0x0010FFFF, 6, 0, THC0_IRQ }, - Package(){0x0010FFFF, 7, 0, THC1_IRQ }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, - Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, PEG_IRQ }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, -}) - -Name (PICN, Package () { - /* D31:HSA, SMBUS, TraceHUB*/ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package () { 0x001EFFFF, 0, 0, 11 }, - Package () { 0x001EFFFF, 1, 0, 10 }, - Package () { 0x001EFFFF, 2, 0, 11 }, - Package () { 0x001EFFFF, 3, 0, 11 }, - /* D29: RP9 ~ RP12 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: RP1 ~ RP8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, 11 }, - Package(){0x0019FFFF, 1, 0, 10 }, - Package(){0x0019FFFF, 2, 0, 11 }, - /* D23: SATA */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, 11 }, - Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 4, 0, 11 }, - Package(){0x0016FFFF, 5, 0, 11 }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, 11 }, - Package(){0x0015FFFF, 1, 0, 10 }, - Package(){0x0015FFFF, 2, 0, 11 }, - Package(){0x0015FFFF, 3, 0, 11 }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, 11 }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 6, 0, 11 },, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, 11 }, - Package(){0x0010FFFF, 6, 0, 11 }, - Package(){0x0010FFFF, 7, 0, 10 }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, 11 }, - Package(){0x000DFFFF, 1, 0, 10 }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, 11 }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, 11 }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, 11 }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "pci_irqs_tgl.asl" +#else + #include "pci_irqs_jsl.asl" +#endif diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl new file mode 100644 index 0000000000..006a5de4a8 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Name (PICP, Package () { + /* cAVS, SMBus, GbE, Northpeak */ + Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, + Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ }, + /* SerialIo */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* eMMC */ + Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, + /* SerialIo */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* SATA controller */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 2, 0, IDER_IRQ }, + Package(){0x0016FFFF, 3, 0, KT_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* SerialIo */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ + Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, + Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, + Package(){0x0014FFFF, 5, 0, SD_IRQ }, + /* SerialIo */ + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Northpeak */ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 10 }, + Package () { 0x001FFFFF, 6, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D30: SerialIo */ + Package () {0x001EFFFF, 0, 0, 11 }, + Package () {0x001EFFFF, 1, 0, 10 }, + Package () {0x001EFFFF, 2, 0, 11 }, + Package () {0x001EFFFF, 3, 0, 11 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D26: eMMC */ + Package(){0x001AFFFF, 0, 0, 11 }, + /* D25: SerialIo */ + Package () {0x0019FFFF, 0, 0, 11 }, + Package () {0x0019FFFF, 1, 0, 10 }, + Package () {0x0019FFFF, 2, 0, 11 }, + /* D23: SATA controller */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, 0, 11 }, + Package () { 0x0016FFFF, 1, 0, 10 }, + Package () { 0x0016FFFF, 2, 0, 11 }, + Package () { 0x0016FFFF, 3, 0, 11 }, + Package () { 0x0016FFFF, 4, 0, 11 }, + Package () { 0x0016FFFF, 5, 0, 11 }, + /* D21: SerialIo */ + Package () {0x0015FFFF, 0, 0, 11 }, + Package () {0x0015FFFF, 1, 0, 10 }, + Package () {0x0015FFFF, 2, 0, 11 }, + Package () {0x0015FFFF, 3, 0, 11 }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ + Package () { 0x0014FFFF, 0, 0, 11 }, + Package () { 0x0014FFFF, 1, 0, 10 }, + Package () { 0x0014FFFF, 2, 0, 11 }, + Package () { 0x0014FFFF, 3, 0, 11 }, + Package () { 0x0014FFFF, 5, 0, 11 }, + /* D18: SerialIo */ + Package () {0x0012FFFF, 6, 0, 11 }, + /* SA IGFX Device */ + Package () {0x0002FFFF, 0, 0, 11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, 11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, 11 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl new file mode 100644 index 0000000000..8aadf8db6a --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Name (PICP, Package () { + /* D31:HSA, SMBUS, TraceHUB */ + Package(){0x001FFFFF, 3, 0, HDA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* D29: RP9 ~ RP12 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* D28: RP1 ~ RP8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* D23: SATA */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ + Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, + Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, ISH_IRQ }, + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, + Package(){0x0010FFFF, 6, 0, THC0_IRQ }, + Package(){0x0010FFFF, 7, 0, THC1_IRQ }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, + Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, PEG_IRQ }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, +}) + +Name (PICN, Package () { + /* D31:HSA, SMBUS, TraceHUB*/ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package () { 0x001EFFFF, 0, 0, 11 }, + Package () { 0x001EFFFF, 1, 0, 10 }, + Package () { 0x001EFFFF, 2, 0, 11 }, + Package () { 0x001EFFFF, 3, 0, 11 }, + /* D29: RP9 ~ RP12 */ + Package () { 0x001DFFFF, 0, 0, 11 }, + Package () { 0x001DFFFF, 1, 0, 10 }, + Package () { 0x001DFFFF, 2, 0, 11 }, + Package () { 0x001DFFFF, 3, 0, 11 }, + /* D28: RP1 ~ RP8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, 11 }, + Package(){0x0019FFFF, 1, 0, 10 }, + Package(){0x0019FFFF, 2, 0, 11 }, + /* D23: SATA */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, 11 }, + Package(){0x0016FFFF, 1, 0, 10 }, + Package(){0x0016FFFF, 4, 0, 11 }, + Package(){0x0016FFFF, 5, 0, 11 }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, 11 }, + Package(){0x0015FFFF, 1, 0, 10 }, + Package(){0x0015FFFF, 2, 0, 11 }, + Package(){0x0015FFFF, 3, 0, 11 }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, 11 }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, 11 }, + Package(){0x0012FFFF, 6, 0, 11 },, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, 11 }, + Package(){0x0010FFFF, 6, 0, 11 }, + Package(){0x0010FFFF, 7, 0, 10 }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, 11 }, + Package(){0x000DFFFF, 1, 0, 10 }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, 11 }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, 11 }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, 11 }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, 11 }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 4d6318f9c5..dec8376033 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -16,69 +16,10 @@ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "irq_tgl.h" +#else + #include "irq_jsl.h" +#endif /* CONFIG_SOC_INTEL_TIGERLAKE */ -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 28 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 18 -#define LPSS_SPI3_IRQ 23 -#define LPSS_UART0_IRQ 34 -#define LPSS_UART1_IRQ 35 -#define LPSS_UART2_IRQ 33 - -#define HDA_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 - -#define THC0_IRQ 16 -#define THC1_IRQ 17 - -#define ISH_IRQ 16 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_jsl.h b/src/soc/intel/tigerlake/include/soc/irq_jsl.h new file mode 100644 index 0000000000..2a2d20f671 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/irq_jsl.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JSL_IRQ_H_ +#define _SOC_JSL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +/* LPSS Devices */ +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 + +/* PCI D:31 F:x */ +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +/* PCI D:28 F:x */ +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 + +/* PCI D:26 F:x */ +#define eMMC_IRQ 16 + +/* PCI D:23 F:x */ +#define SATA_IRQ 16 + +/* PCI D:22 F:x */ +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 +#define IDER_IRQ 18 +#define KT_IRQ 19 + +/* PCI D:20 F:x */ +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define CNViWIFI_IRQ 16 +#define SD_IRQ 19 +#define PMC_SRAM_IRQ 18 + +/* PCI D:18 F:x */ +#define UFS_IRQ 16 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 + +#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h new file mode 100644 index 0000000000..0ea6053c2d --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TGL_IRQ_H_ +#define _SOC_TGL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 18 +#define LPSS_SPI3_IRQ 23 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 + +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 + +#define CNVI_BT_IRQ 18 + +#define THC0_IRQ 16 +#define THC1_IRQ 17 + +#define ISH_IRQ 16 + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 + +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif /* _TGL_IRQ_H_ */ From 0d866f8cd830f0ec6e84d7b284f15d2a2b485888 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 18 Feb 2020 11:20:30 +0530 Subject: [PATCH 0082/1463] soc/intel/common/block/lpc: Drop unnecessary helper function This patch removes unnecessary helper function pch_lpc_interrupt_init() and directly uses soc_pch_pirq_init() function to avoid redundant device NULL check. TEST=Able to build and boot CML platform. Change-Id: I3d11afb7e98f9b7f84beb2fdf308bbffeb3bbff7 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38952 Reviewed-by: Werner Zeh Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/lpc/lpc_lib.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 3ad2176c11..5b30a8121b 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -270,17 +270,6 @@ static void lpc_set_gen_decode_range( gen_io_dec[i]); } -static void pch_lpc_interrupt_init(void) -{ - const struct device *dev; - - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev) - return; - - soc_pch_pirq_init(dev); -} - void pch_enable_lpc(void) { /* Lookup device tree in romstage */ @@ -295,7 +284,7 @@ void pch_enable_lpc(void) lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) - pch_lpc_interrupt_init(); + soc_pch_pirq_init(dev); } void lpc_enable_pci_clk_cntl(void) From cbc5b99ac9e5856631109b1e7f20e80799beb1e4 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 23 Nov 2018 15:55:56 +0100 Subject: [PATCH 0083/1463] util/lint: Allow non-option carrying named choices named choices can be overridden with a default later-on: choice FOO config A config B config C endchoice ... if BOARD_FOO choice FOO default A endchoice endif Reflect that. Change-Id: I6662e19685f6ab0b84c78b30aedc266c0e176039 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/29813 Reviewed-by: Nico Huber Reviewed-by: Martin Roth Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- util/lint/kconfig_lint | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 1545c8299b..16188bacc5 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -530,6 +530,7 @@ sub build_and_parse_kconfig_tree { my $inside_config = ""; # set to symbol name of the config section my @inside_menu = (); # stack of menu names my $inside_choice = ""; + my $choice_symbol = ""; my $configs_inside_choice; my %fileinfo; @@ -617,6 +618,7 @@ sub build_and_parse_kconfig_tree { my $symbol = $1; add_symbol( $symbol, \@inside_menu, $filename, $line_no, \@inside_if ); handle_type( "bool", $symbol, $filename, $line_no ); + $choice_symbol = $symbol; } $inside_config = ""; $inside_choice = "$filename $line_no"; @@ -633,10 +635,12 @@ sub build_and_parse_kconfig_tree { } $inside_choice = ""; - if ( $configs_inside_choice == 0 ) { - show_error("choice block has no symbols at $filename:$line_no."); + if (( $configs_inside_choice == 0 ) && + ( $choice_symbol eq "" )) { + show_error("unnamed choice block has no symbols at $filename:$line_no."); } $configs_inside_choice = 0; + $choice_symbol=""; } # [optional] From dc83cd2ac1a79622295c52516a7d9c49a82a1792 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 19 Feb 2020 09:02:52 -0700 Subject: [PATCH 0084/1463] soc/amd/stoneyridge: Remove TODO for file extensions The comment is no longer relevant. Perhaps the intention had been to modify the names of the files delivered from AMD in order to simplify Makefile.inc. AMD firmware is distributed via the new amd_blobs repo and the filenames match the blobs as they are released. Multiple Family 15h devices are supported by this directory and their SMU Firmwares do not all follow identical naming convention. Keep the existing functionality and reword the comment. BUG=b:120118850 Signed-off-by: Marshall Dawson Change-Id: Ifbf8e2286f34bc37a6178c37f8c412ec51ee02c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39012 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/amd/stoneyridge/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index eb8af2d7b2..0cc49c8568 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -155,8 +155,8 @@ PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYP ###4 PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -###8 - Check for SMU firmware named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. +###8 - Check for SMU firmware named either *.sbin or *.csbin. Both "signed" and +### "compressed signed" are used by generations supported by this file. SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFWM_FILE))","") From 2b6d249632980ddf2162cc6f4530045214f5ba81 Mon Sep 17 00:00:00 2001 From: James Ye Date: Thu, 20 Feb 2020 16:13:04 +1100 Subject: [PATCH 0085/1463] nb/intel/snb: Add PCI routing table for PEG root ports Previously the PRTs were defined in southbridge code (8014714 southbridge/intel/bd82x6x/acpi: Fix IRQ warnings), but this was lost when southbridge PRTs became autogenerated. Add the proper PRTs for the PCI express for graphics root ports. This (again) fixes warnings issued by Linux for interrupts on secondary functions of devices on the PEG ports, such as the HDMI audio controller on graphics cards. pcieport 0000:00:01.0: can't derive routing for PCI INT B snd_hda_intel 0000:01:00.1: PCI INT B: no GSI Tested with GIGABYTE P67A-UD3R (CB:31363) with Radeon HD 5670. Change-Id: Ic429ec2fdeadb9dab1c03916974e173004d6cd16 Signed-off-by: James Ye Reviewed-on: https://review.coreboot.org/c/coreboot/+/39021 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../intel/sandybridge/acpi/peg.asl | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index fcec00ec67..afc24dfe85 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -27,6 +27,11 @@ Device (PEGP) { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + Return (\_SB.PCI0.IRQM (1)) + } } Device (PEG1) @@ -42,6 +47,11 @@ Device (PEG1) { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + Return (\_SB.PCI0.IRQM (2)) + } } Device (PEG2) @@ -57,6 +67,11 @@ Device (PEG2) { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + Return (\_SB.PCI0.IRQM (3)) + } } Device (PEG6) @@ -72,4 +87,9 @@ Device (PEG6) { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + Return (\_SB.PCI0.IRQM (4)) + } } From 5544f62746aeb8e5e1a7916d9b509f4d9339f387 Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Wed, 12 Feb 2020 13:31:30 -0500 Subject: [PATCH 0086/1463] security/intel/stm: Check for processor STM support Check to ensure that dual monitor mode is supported on the current processor. Dual monitor mode is normally supported on any Intel x86 processor that has VTx support. The STM is a hypervisor that executes in SMM dual monitor mode. This check should fail only in the rare case were dual monitor mode is disabled. If the check fails, then the STM will not be initialized by coreboot. Signed-off-by: Eugene D. Myers Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38836 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/include/cpu/x86/msr.h | 1 + src/security/intel/stm/StmPlatformSmm.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 49abd41c00..c761bc04b6 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -74,6 +74,7 @@ #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) #define IA32_VMX_BASIC_MSR 0x480 +#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define IA32_VMX_MISC_MSR 0x485 #define MC0_ADDR 0x402 #define MC0_MISC 0x403 diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index d7064b07f5..45db0e069f 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -159,9 +159,20 @@ void stm_setup(uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, { msr_t InitMseg; msr_t MsegChk; + msr_t vmx_basic; + uintptr_t addr_calc; // used to calculate the stm resource heap area printk(BIOS_DEBUG, "STM: set up for cpu %d/%d\n", cpu, num_cpus); + + vmx_basic = rdmsr(IA32_VMX_BASIC_MSR); + + // Does this processor support an STM? + if ((vmx_basic.hi & VMX_BASIC_HI_DUAL_MONITOR) != VMX_BASIC_HI_DUAL_MONITOR) { + printk(BIOS_WARNING, "STM: not supported on CPU %d\n", cpu); + return; + } + if (cpu == 0) { // need to create the BIOS resource list once From 9d4f94af248418ff6b88ee2c0f9013b372ef3344 Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Wed, 12 Feb 2020 12:47:57 -0500 Subject: [PATCH 0087/1463] security/intel/stm: Use depends on ENABLE_VMX The STM is a part of the core VTx and using ENABLE_VMX will make the STM option available for any configuration that has an Intel processor that supports VTx. Signed-off-by: Eugene D. Myers Change-Id: I57ff82754e6c692c8722d41f812e35940346888a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38852 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/security/intel/stm/Kconfig | 8 ++------ src/soc/intel/skylake/Kconfig | 1 - 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index 144deeda9e..618217f686 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -1,12 +1,8 @@ - -config PLATFORM_SUPPORTS_STM - bool - depends on SMM_TSEG - config STM bool "Enable STM" default n - depends on PLATFORM_SUPPORTS_STM + depends on ENABLE_VMX + depends on SMM_TSEG select USE_BLOBS help diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0340282c90..7382df0134 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -44,7 +44,6 @@ config CPU_SPECIFIC_OPTIONS select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK - select PLATFORM_SUPPORTS_STM select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR From 17f0f0118853f3f35897cf5aa14661eb9ec08ac5 Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Wed, 12 Feb 2020 17:08:29 -0500 Subject: [PATCH 0088/1463] cpu/x86/smm: Convert C++ style comment Originally, this patch made 'BIOS' uppercase in the referenced comment and converted the C++ style to be consistent with the remainder of the function. Somewhere, the 'BIOS' became uppercase creating a merge conflict. Now this CL converts the C++ style to be consistent with the remainder of the comments. Signed-off-by: Eugene D. Myers Change-Id: I85d78b5e08a7643c3d87e3daf353d6b3ba8d306b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38854 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/x86/smm/smm_module_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index ca6f611959..856ca7876b 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -396,7 +396,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - // account for the BIOS resource list + /* Account for the BIOS resource list */ if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; From 291a014e158d856b5583ff192d9300115d4cec1c Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Tue, 18 Feb 2020 08:48:22 -0700 Subject: [PATCH 0089/1463] util/mainboard/google: deduplicate create_coreboot_variant.sh create_coreboot_variant.sh and kconfig.py have moved to the chromium repo, in src/platform/dev/contrib/variant (see crrev.com/c/2052338), so remove them from the coreboot repo. BUG=b:149410618 BRANCH=None TEST=N/A Cq-Depend: chromium:2052338 Signed-off-by: Paul Fagerburg Change-Id: Ie27f68bfd978be5e2b1a2f0789d574749825f6fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/38979 Tested-by: build bot (Jenkins) Reviewed-by: Jack Rosenthal Reviewed-by: Justin TerAvest --- .../google/create_coreboot_variant.sh | 94 ------------ util/mainboard/google/kconfig.py | 140 ------------------ 2 files changed, 234 deletions(-) delete mode 100755 util/mainboard/google/create_coreboot_variant.sh delete mode 100755 util/mainboard/google/kconfig.py diff --git a/util/mainboard/google/create_coreboot_variant.sh b/util/mainboard/google/create_coreboot_variant.sh deleted file mode 100755 index dcbacb99cd..0000000000 --- a/util/mainboard/google/create_coreboot_variant.sh +++ /dev/null @@ -1,94 +0,0 @@ -#!/bin/bash -# -# This file is part of the coreboot project. -# -# Copyright 2019 Google LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -VERSION="2.0.0" -SCRIPT=$(basename -- "${0}") - -export LC_ALL=C - -if [[ "$#" -lt 3 ]]; then - echo "Usage: ${SCRIPT} base_name reference_name variant_name [bug_number]" - echo "e.g. ${SCRIPT} hatch hatch kohaku b:140261109" - echo "e.g. ${SCRIPT} zork trembyle dalboz" - echo "* Adds a new variant of the baseboard to Kconfig and Kconfig.name" - echo "* Copies the template files for the baseboard to the new variant" - exit 1 -fi - -# This is the name of the base board -# ${var,,} converts to all lowercase. -BASE="${1,,}" -# This is the name of the reference board that we're using to make the variant. -REFERENCE="${2,,}" -# This is the name of the variant that is being cloned. -# ${var,,} converts to all lowercase; ${var^^} is all uppercase. -VARIANT="${3,,}" -VARIANT_UPPER="${VARIANT^^}" - -# Assign BUG= text, or "None" if that parameter wasn't specified. -BUG=${4:-None} - -# This script lives in util/mainboard/google -# The template files are in util/mainboard/google/${BASE}/templates -# We need to create files in src/mainboard/google/${BASE}/variants/${VARIANT} -pushd "${BASH_SOURCE%/*}" || exit 1 -SRC=$(pwd) -popd || exit 1 -pushd "${SRC}/../../../src/mainboard/google/${BASE}" || { - echo "The baseboard directory for ${BASE} does not exist."; - exit 1; } - -# Make sure the variant doesn't already exist. -if [[ -e variants/${VARIANT} ]]; then - echo "variants/${VARIANT} already exists." - echo "Have you already created this variant?" - exit 1 -fi - -# Start a branch. Use YMD timestamp to avoid collisions. -DATE=$(date +%Y%m%d) -git checkout -b "coreboot_${VARIANT}_${DATE}" || exit 1 - -# Copy the template tree to the target. -mkdir -p "variants/${VARIANT}/" -cp -pr "${SRC}/${BASE}/template/." "variants/${VARIANT}/" -if [[ -e "variants/${VARIANT}/Kconfig" ]]; then - sed -i -e "s/BOARD_GOOGLE_TEMPLATE/BOARD_GOOGLE_${VARIANT_UPPER}/" \ - "variants/${VARIANT}/Kconfig" -fi -git add "variants/${VARIANT}/" - -# Now add the new variant to Kconfig and Kconfig.name -# These files are in the current directory, e.g. src/mainboard/google/hatch -"${SRC}/kconfig.py" --board "${BASE}" --variant "${VARIANT}" || exit 1 - -mv Kconfig.new Kconfig -mv Kconfig.name.new Kconfig.name - -git add Kconfig Kconfig.name - -# Now commit the files. -git commit -sm "${BASE}: Create ${VARIANT} variant - -Create the ${VARIANT} variant of the ${REFERENCE} reference -board by copying the template files to a new directory named -for the variant. - -(Auto-Generated by ${SCRIPT} version ${VERSION}). - -BUG=${BUG} -BRANCH=None -TEST=util/abuild/abuild -p none -t google/${BASE} -x -a -make sure the build includes GOOGLE_${VARIANT_UPPER}" diff --git a/util/mainboard/google/kconfig.py b/util/mainboard/google/kconfig.py deleted file mode 100755 index 1293f4aafe..0000000000 --- a/util/mainboard/google/kconfig.py +++ /dev/null @@ -1,140 +0,0 @@ -#!/usr/bin/env python3 -# -*- coding: utf-8 -*- -"""Add a new variant to the Kconfig and Kconfig.name - -To start a new variant of an existing reference board, we need to -add the variant into the Kconfig and Kconfig.name files for the -reference board. In Kconfig, we have two sections that need additional -entries, MAINBOARD_PART_NUMBER and VARIANT_DIR. - -The MAINBOARD_PART_NUMBER and VARIANT_DIR just use various -capitalizations of the variant name to create the strings. - -Kconfig.name adds an entire section for the new variant, and all -of these use various capitalizations of the variant name. The strings -in this section are SOC-specific, so we'll need versions for each -SOC that we support. - -Copyright 2019 Google LLC. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; version 2 of the License. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. -""" - -from __future__ import print_function -import argparse -import sys - - -def main(): - parser = argparse.ArgumentParser( - description='Add strings to coreboot Kconfig for a new board variant') - parser.add_argument('--board', type=str, required=True, - help='Name of the reference board') - parser.add_argument('--variant', type=str, required=True, - help='Name of the board variant') - args = parser.parse_args() - - if args.board not in ['hatch', 'volteer', 'trembyle']: - print('Unsupported reference board "' + args.board + '"') - sys.exit(1) - - add_to_Kconfig(args.variant) - add_to_Kconfig_name(args.board, args.variant) - - -def add_to_Kconfig(variant_name): - """Add options for the variant to the Kconfig - - Open the Kconfig file and read it line-by-line. When we detect that we're - in one of the sections of interest, wait until we get a blank line - (signalling the end of that section), and then add our new line before - the blank line. The updated lines are written out to Kconfig.new in the - same directory as Kconfig. - - variant_name The name of the board variant, e.g. 'kohaku' - """ - # These are the part of the strings that we'll add to the sections - BOARD = 'BOARD_GOOGLE_' + variant_name.upper() - lowercase = variant_name.lower() - capitalized = lowercase.capitalize() - - # These flags track whether we're in a section where we need to add an option - in_mainboard_part_number = False - in_variant_dir = False - - inputname = 'Kconfig' - outputname = 'Kconfig.new' - with open(outputname, 'w') as outfile: - with open(inputname, 'r') as infile: - for rawline in infile: - line = rawline.rstrip('\r\n') - - # Are we in one of the sections of interest? - if line == 'config MAINBOARD_PART_NUMBER': - in_mainboard_part_number = True - if line == 'config VARIANT_DIR': - in_variant_dir = True - - # Are we at the end of a section, and if so, is it one of the - # sections of interest? - if line == '': - if in_mainboard_part_number: - print('\tdefault "' + capitalized + '" if ' + BOARD, file=outfile) - in_mainboard_part_number = False - if in_variant_dir: - print('\tdefault "' + lowercase + '" if ' + BOARD, file=outfile) - in_variant_dir = False - - print(line, file=outfile) - - -def add_to_Kconfig_name(refboard_name, variant_name): - """Add a config section for the variant to the Kconfig.name - - Kconfig.name is easier to modify than Kconfig; it only has a block at - the end with the new variant's details. - - refboard_name The name of the reference board, e.g. 'hatch' - We expect the caller to have checked that it is one we support - variant_name The name of the board variant, e.g. 'kohaku' - """ - # Board name for the config section - uppercase = variant_name.upper() - capitalized = variant_name.lower().capitalize() - - inputname = 'Kconfig.name' - outputname = 'Kconfig.name.new' - with open(outputname, 'w') as outfile: - with open(inputname, 'r') as infile: - # Copy all input lines to output - for rawline in infile: - line = rawline.rstrip('\r\n') - print(line, file=outfile) - - # Now add the new section - if refboard_name == 'hatch': - print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) - print('\tbool "-> ' + capitalized + '"', file=outfile) - print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) - print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) - - if refboard_name == 'volteer': - print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) - print('\tbool "-> ' + capitalized + '"', file=outfile) - print('\tselect BOARD_GOOGLE_BASEBOARD_VOLTEER', file=outfile) - - if refboard_name == 'trembyle': - print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) - print('\tbool "-> ' + capitalized + '"', file=outfile) - print('\tselect BOARD_GOOGLE_BASEBOARD_TREMBYLE', file=outfile) - - -if __name__ == '__main__': - main() From f5529d9edc82666e1ac410c0042099228f6e6734 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 21 Feb 2020 22:14:01 +0000 Subject: [PATCH 0090/1463] cbfs: allow uncompressed payloads Change-Id: I8261bc28e5bc9aa32db1dccef7035486995c9873 Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/c/coreboot/+/39051 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- payloads/Kconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/payloads/Kconfig b/payloads/Kconfig index 4e86c21ec7..f85dce9175 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -57,10 +57,16 @@ config PAYLOAD_FILE choice prompt "Payload compression algorithm" default COMPRESSED_PAYLOAD_LZMA + default COMPRESSED_PAYLOAD_NONE if PAYLOAD_LINUX || PAYLOAD_LINUXBOOT || PAYLOAD_FIT depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT help Choose the compression algorithm for the chosen payloads. - You can choose between LZMA and LZ4. + You can choose between None, LZMA, or LZ4. + +config COMPRESSED_PAYLOAD_NONE + bool "Use no compression for payloads" + help + Do not compress the payload. config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" From 4ab7ef93ee6fef0f12a9237486fa1cacf9a9c84a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 20 Feb 2020 11:53:04 +0530 Subject: [PATCH 0091/1463] soc/intel/apollolake: Make SMI_STS offset macro definition consistent This patch makes all bit field macro definition for SMI_STS register (offset 0x44) be consistent i.e. ending with "_STS_BIT". Also modified relevant files where those macros are getting used. Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39022 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/include/soc/pm.h | 43 +++++++++++----------- src/soc/intel/apollolake/pmutil.c | 44 +++++++++++------------ src/soc/intel/apollolake/smihandler.c | 16 ++++----- 3 files changed, 52 insertions(+), 51 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 22e414c803..0cf06b2a60 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -105,29 +105,30 @@ (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN) #define SMI_STS 0x44 +#define SMI_STS_BITS 32 /* Bits for SMI status */ #define ESPI_SMI_STS_BIT 28 -#define PMC_OCP_SMI_STS 27 -#define SPI_SMI_STS 26 -#define SPI_SSMI_STS 25 -#define SCC2_SMI_STS 21 -#define PCIE_SMI_STS 20 -#define SCS_SMI_STS 19 -#define HSMBUS_SMI_STS 18 -#define XHCI_SMI_STS 17 -#define SMBUS_SMI_STS 16 -#define SERIRQ_SMI_STS 15 -#define PERIODIC_SMI_STS 14 -#define TCO_SMI_STS 13 -#define MC_SMI_STS 12 -#define GPIO_UNLOCK_SMI_STS 11 -#define GPIO_SMI_STS 10 -#define FAKE_PM1_SMI_STS 8 -#define SWSMI_TMR_SMI_STS 6 -#define APM_SMI_STS 5 -#define SLP_SMI_STS 4 -#define LEGACY_USB_SMI_STS 3 -#define BIOS_SMI_STS 2 +#define PMC_OCP_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SPI_SSMI_STS_BIT 25 +#define SCC2_SMI_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SCS_SMI_STS_BIT 19 +#define HSMBUS_SMI_STS_BIT 18 +#define XHCI_SMI_STS_BIT 17 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define MC_SMI_STS_BIT 12 +#define GPIO_UNLOCK_SMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 8151afc08d..4a08827c1c 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -57,27 +57,27 @@ uint32_t *soc_pmc_etr_addr(void) const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { - [BIOS_SMI_STS] = "BIOS", - [LEGACY_USB_SMI_STS] = "LEGACY USB", - [SLP_SMI_STS] = "SLP_SMI", - [APM_SMI_STS] = "APM", - [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", - [FAKE_PM1_SMI_STS] = "PM1", - [GPIO_SMI_STS] = "GPIO_SMI", - [GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI", - [MC_SMI_STS] = "MCSMI", - [TCO_SMI_STS] = "TCO", - [PERIODIC_SMI_STS] = "PERIODIC", - [SERIRQ_SMI_STS] = "SERIRQ", - [SMBUS_SMI_STS] = "SMBUS_SMI", - [XHCI_SMI_STS] = "XHCI", - [HSMBUS_SMI_STS] = "HOST_SMBUS", - [SCS_SMI_STS] = "SCS", - [PCIE_SMI_STS] = "PCI_EXP_SMI", - [SCC2_SMI_STS] = "SCC2", - [SPI_SSMI_STS] = "SPI_SSMI", - [SPI_SMI_STS] = "SPI", - [PMC_OCP_SMI_STS] = "OCP_CSE", + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPIO_STS_BIT] = "GPIO_SMI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI", + [MC_SMI_STS_BIT] = "MCSMI", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [XHCI_SMI_STS_BIT] = "XHCI", + [SCS_SMI_STS_BIT] = "HOST_SMBUS", + [SCS_SMI_STS_BIT] = "SCS", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [SCC2_SMI_STS_BIT] = "SCC2", + [SPI_SSMI_STS_BIT] = "SPI_SSMI", + [SPI_SMI_STS_BIT] = "SPI", + [PMC_OCP_SMI_STS_BIT] = "OCP_CSE", }; *a = ARRAY_SIZE(smi_sts_bits); @@ -98,7 +98,7 @@ uint32_t soc_get_smi_status(uint32_t generic_sts) /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) - generic_sts |= (1 << FAKE_PM1_SMI_STS); + generic_sts |= (1 << PM1_STS_BIT); } return generic_sts; diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e858..424d66f0d7 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -38,19 +38,19 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) uint32_t smihandler_soc_get_sci_mask(void) { uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_SMI_STS) | - SMI_HANDLER_SCI_EN(SLP_SMI_STS); + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); return sci_mask; } const smi_handler_t southbridge_smi[32] = { - [SLP_SMI_STS] = smihandler_southbridge_sleep, - [APM_SMI_STS] = smihandler_southbridge_apmc, - [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1, - [GPIO_SMI_STS] = smihandler_southbridge_gpi, - [TCO_SMI_STS] = smihandler_southbridge_tco, - [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [TCO_STS_BIT] = smihandler_southbridge_tco, + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, #endif From 182a0aee3ddeaa762d4dd89b16cb9df856315e26 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 19 Feb 2020 14:57:04 +0530 Subject: [PATCH 0092/1463] soc/intel/cnl: Rename hfsts into me_hfsts Remove me_hfs3 union from cnl/me.c since it's already defined in soc/me.h. Rename below union tags for consistency: hfsts2 -> me_hfsts2 hfsts3 -> me_hfsts3 hfsts4 -> me_hfsts4 hfsts5 -> me_hfsts5 hfsts6 -> me_hfsts6 TEST=Verified on hatch Change-Id: If81edbad0322425ee3e96c55a9c84a5087604308 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/39009 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik --- src/soc/intel/cannonlake/me.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 0414470ef7..3d3fcb8ded 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -32,7 +32,7 @@ enum { }; /* Host Firmware Status Register 2 */ -union hfsts2 { +union me_hfsts2 { uint32_t raw; struct { uint32_t nftp_load_failure : 1; @@ -55,13 +55,8 @@ union hfsts2 { } __packed fields; }; -/* Host Firmware Status Register 3 */ -union hfsts3 { - uint32_t raw; -}; - /* Host Firmware Status Register 4 */ -union hfsts4 { +union me_hfsts4 { uint32_t raw; struct { uint32_t rsvd0 : 9; @@ -77,7 +72,7 @@ union hfsts4 { }; /* Host Firmware Status Register 5 */ -union hfsts5 { +union me_hfsts5 { uint32_t raw; struct { uint32_t acm_active : 1; @@ -96,7 +91,7 @@ union hfsts5 { }; /* Host Firmware Status Register 6 */ -union hfsts6 { +union me_hfsts6 { uint32_t raw; struct { uint32_t force_boot_guard_acm : 1; @@ -193,18 +188,18 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); void dump_me_status(void *unused) { union me_hfsts1 hfsts1; - union hfsts2 hfsts2; - union hfsts3 hfsts3; - union hfsts4 hfsts4; - union hfsts5 hfsts5; - union hfsts6 hfsts6; + union me_hfsts2 hfsts2; + union me_hfsts3 hfsts3; + union me_hfsts4 hfsts4; + union me_hfsts5 hfsts5; + union me_hfsts6 hfsts6; if (!is_cse_enabled()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); - hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); + hfsts3.data = me_read_config32(PCI_ME_HFSTS3); hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); @@ -214,7 +209,7 @@ void dump_me_status(void *unused) printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.raw); printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", - hfsts3.raw); + hfsts3.data); printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.raw); printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", From 5cfe449814af7ab5cb874d5771c3b74a65ee72eb Mon Sep 17 00:00:00 2001 From: Dtrain Hsu Date: Thu, 20 Feb 2020 10:54:10 +0800 Subject: [PATCH 0093/1463] mb/google/drallion: Remove MAC address pass through Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:147994020 TEST=tested on drallion and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Mathew King --- src/mainboard/google/drallion/dsdt.asl | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index ee63d6ee8a..33ede7a2b1 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -48,8 +48,6 @@ DefinitionBlock( #include /* VPD support */ #include - /* MAC address passthru */ - #include #endif #include From 7225ed60351c48eee93f1e163e4d42480bc72185 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 12 Feb 2020 11:41:23 -0700 Subject: [PATCH 0094/1463] mb/google/dedede: Add USB configuration Add USB port configuration in devicetree. Configure USB Over-Current (OC) GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Justin TerAvest Reviewed-by: Aamir Bohra --- .../dedede/variants/baseboard/devicetree.cb | 19 ++++++++++++++++++- .../google/dedede/variants/baseboard/gpio.c | 8 ++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2d57a14f25..9dfd6b7536 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,23 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H" + # USB Port Configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not Used + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Not Used + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Not Used + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -95,7 +112,7 @@ chip soc/intel/tigerlake device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub device pci 12.6 off end # GSPI 2 - device pci 14.0 off end # USB xHCI + device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM device pci 14.3 off end # CNVi wifi diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 8e4200ab9f..71ddadbf95 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,6 +21,14 @@ static const struct pad_config gpio_table[] = { /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + /* A12 : USB_OC1_N */ + PAD_NC(GPP_A12, NONE), + /* A13 : USB_OC2_N */ + PAD_NC(GPP_A13, NONE), + /* A14 : USB_OC3_N */ + PAD_NC(GPP_A14, NONE), + /* A18 : USB_OC0_N */ + PAD_NC(GPP_A18, NONE), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), From be6583ae5c98ccae7f58bda9389fbf7458787612 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 12 Feb 2020 12:07:51 -0700 Subject: [PATCH 0095/1463] mb/google/dedede: Add EMMC configuration Turn on EMMC device and enable the HS400 mode. Configure the GPIOs associated with EMMC. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra --- .../dedede/variants/baseboard/devicetree.cb | 5 +++- .../google/dedede/variants/baseboard/gpio.c | 25 +++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 9dfd6b7536..c17620b3e7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -69,6 +69,9 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" + # Enable EMMC HS400 mode + register "ScsEmmcHs400Enabled" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -129,7 +132,7 @@ chip soc/intel/tigerlake device pci 19.0 on end # I2C 4 device pci 19.1 off end # I2C 5 device pci 19.2 on end # UART 2 - device pci 1a.0 off end # eMMC + device pci 1a.0 on end # eMMC device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 off end # PCI Express Root Port 3 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 71ddadbf95..fa975e796b 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -58,6 +58,31 @@ static const struct pad_config gpio_table[] = { /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + /* F7 : EMMC_CMD */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* F8 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* F9 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* F10 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + /* F11 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_CLK */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_RESET_N */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* H4 : AP_I2C_TS_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : AP_I2C_TS_SCL */ From 96eceba31424a97c183a8111a039fba342565dba Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 12 Feb 2020 16:28:08 -0700 Subject: [PATCH 0096/1463] mb/google/dedede: Add waddledoo variant Add initial support for waddledoo board. BUG=None TEST=Build the mainboard and variant board. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/Kconfig | 8 +++++++- src/mainboard/google/dedede/Kconfig.name | 6 ++++++ .../dedede/variants/waddledoo/include/variant/ec.h | 14 ++++++++++++++ .../variants/waddledoo/include/variant/gpio.h | 14 ++++++++++++++ .../dedede/variants/waddledoo/overridetree.cb | 3 +++ 5 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h create mode 100644 src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h create mode 100644 src/mainboard/google/dedede/variants/waddledoo/overridetree.cb diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index a3d189d639..3eddabc985 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -44,12 +44,17 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string - default "dedede" if BOARD_GOOGLE_DEDEDE + default "Dedede" if BOARD_GOOGLE_DEDEDE + default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO config MAX_CPUS int default 4 +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_DEDEDE + config TPM_TIS_ACPI_INTERRUPT int default 4 # GPE0_DW0_4 (GPP_B4) @@ -61,5 +66,6 @@ config UART_FOR_CONSOLE config VARIANT_DIR string default "dedede" if BOARD_GOOGLE_DEDEDE + default "waddledoo" if BOARD_GOOGLE_WADDLEDOO endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 4bf440d3cd..ae5df66df5 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -3,3 +3,9 @@ config BOARD_GOOGLE_DEDEDE select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + +config BOARD_GOOGLE_WADDLEDOO + bool "Waddledoo" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h new file mode 100644 index 0000000000..cc897dcdcf --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h new file mode 100644 index 0000000000..bf23f6e457 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb new file mode 100644 index 0000000000..ac9d576d01 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -0,0 +1,3 @@ +chip soc/intel/tigerlake + device domain 0 on end +end From 0868f964398e401c7c100627e6c2d713699772a0 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 18 Feb 2020 16:06:04 -0600 Subject: [PATCH 0097/1463] mb/google/{auron,slippy}/ec: clear pending events on S3 wakeup Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source] partially broke resume from suspend on Auron and Slippy variants when multiple events exist in the EC event queue. In the case of the device suspending manually and then subsequently having the lid closed, the device will be stuck in a resume/suspend/resume loop until the device is forcibly powered down. Mitigate this by clearing any pending EC events on S3 wakeup. Test: build/boot several Auron/Slippy variants, test suspend/resume functional with both single and multiple events in EC event queue. Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/mainboard/google/auron/ec.c | 9 ++++++++- src/mainboard/google/slippy/ec.c | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index 3fc5373096..0589864d7f 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -29,10 +29,17 @@ void mainboard_ec_init(void) .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; + int s3_wakeup = acpi_is_wakeup_s3(); + printk(BIOS_DEBUG, "mainboard_ec_init\n"); post_code(0xf0); - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + google_chromeec_events_init(&info, s3_wakeup); + if (s3_wakeup) { + /* Clear pending events. */ + while (google_chromeec_get_event() != 0) + ; + } post_code(0xf1); } diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index f8ab6b81d5..e296575a92 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -28,10 +28,17 @@ void mainboard_ec_init(void) .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; + int s3_wakeup = acpi_is_wakeup_s3(); + printk(BIOS_DEBUG, "mainboard_ec_init\n"); post_code(0xf0); - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + google_chromeec_events_init(&info, s3_wakeup); + if (s3_wakeup) { + /* Clear pending events. */ + while (google_chromeec_get_event() != 0) + ; + } post_code(0xf1); } From 94022a0abf044ef48bf1ca99851111c1dc08ded0 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Wed, 19 Feb 2020 17:52:29 +0800 Subject: [PATCH 0098/1463] mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin. This can save 1mW power comsumption. BUG=b:149289256 TEST=NA Signed-off-by: Eric Lai Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999 Tested-by: build bot (Jenkins) Reviewed-by: Ivy Jian Reviewed-by: Mathew King --- src/mainboard/google/drallion/variants/drallion/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 85de17346a..d26abdb2be 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -184,9 +184,9 @@ static const struct pad_config gpio_table[] = { /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_CLK */ PAD_NC(GPP_G6, NONE), /* AUD_PWR_EN */ /* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), From 8c4c3700309727f2da0c96bd1e0716343fb3abb8 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Sun, 16 Feb 2020 20:34:26 +0300 Subject: [PATCH 0099/1463] util/ifdtool: Mention MeDisable in help text The -M option of ifdtool sets not only AltMeDisable bit, but also MeDisable bit in ICH0 and MCH0 straps. Make it obvious and mention in the help message. Change-Id: I9dba2fa6509a9c833f72414367944bc606671e7b Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38934 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Peter Lemenkov --- util/ifdtool/ifdtool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index d89e77d2c2..84a8ead9f1 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1438,8 +1438,8 @@ static void print_usage(const char *name) " Dual Output Fast Read Support\n" " -l | --lock Lock firmware descriptor and ME region\n" " -u | --unlock Unlock firmware descriptor and ME region\n" - " -M | --altmedisable <0|1> Set the AltMeDisable (or HAP for skylake or newer platform)\n" - " bit to disable ME\n" + " -M | --altmedisable <0|1> Set the MeDisable and AltMeDisable (or HAP for skylake or newer platform)\n" + " bits to disable ME\n" " -p | --platform Add platform-specific quirks\n" " aplk - Apollo Lake\n" " cnl - Cannon Lake\n" From 0d4dd167f5228e6fccdde40f1877ac55905fc826 Mon Sep 17 00:00:00 2001 From: Dtrain Hsu Date: Fri, 21 Feb 2020 14:49:55 +0800 Subject: [PATCH 0100/1463] mb/google/sarien: Remove MAC address pass through Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:149813043 TEST=tested on sarien and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/sarien/dsdt.asl | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index c32470eb1b..8acd0b59d7 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -48,8 +48,6 @@ DefinitionBlock( #include /* VPD support */ #include - /* MAC address passthru */ - #include #endif #include From a6531a335c9fed0776f033ee69f7eb4fc325c944 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Thu, 20 Feb 2020 17:50:25 +0800 Subject: [PATCH 0101/1463] vboot: remove rogue vboot_struct.h include As part of vboot1 deprecation, remove an unused vboot_struct.h include. coreboot is now free of vboot1 data structure use. One vboot_api.h include remains as part of security/vboot/ec_sync.c. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I042d692aa252f8f859d4005455eb6a2eabc24a87 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/39024 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Julius Werner --- src/security/vboot/ec_sync.c | 2 +- src/vendorcode/google/chromeos/gnvs.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index f4f9c23976..e7b64b2398 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include /* for VbExDisplayScreen() and VbScreenData */ #define _EC_FILENAME(select, suffix) \ (select == VB_SELECT_FIRMWARE_READONLY ? "ecro" suffix : "ecrw" suffix) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 81154550ec..04680c0974 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -22,7 +22,6 @@ #include #include #include -#include #include "chromeos.h" #include "gnvs.h" From 4684dc0c638ea0debe9ec1aa736d119d58626424 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 21 Feb 2020 18:37:51 +0100 Subject: [PATCH 0102/1463] util/inteltool: Add missing entry for WPT-LP Premium Tested on a laptop with an i7-5500U processor, the device is now found. Change-Id: I49ddec862520d0d5492d78fec89efd841c141790 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39046 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/inteltool/inteltool.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index de66811419..c20aafe601 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -226,8 +226,10 @@ static const struct { "Lynx Point Low Power Premium SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM, + "Wildcat Point Low Power Premium SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, - "Wildcat Point Low Power SKU" }, + "Wildcat Point Low Power Base SKU" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, From a0b0d42d691f163b0a5a8268da1087c9c5f28eaa Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 21 Feb 2020 09:57:54 -0800 Subject: [PATCH 0103/1463] gfx: Move drivers/generic/gfx to drivers/gfx/generic This change creates gfx directory under drivers/ so that all drivers handling gfx devices can be located in the same place. In follow-up CLs, we will be adding another driver that handles gfx devices. This change also updates the names used within the driver from *generic_gfx* to *gfx_generic*. In addition to that, mainboard drallion using this driver is updated to match the correct path and Kconfig name. TEST=Verified that drallion still builds. Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/39047 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Mathew King --- src/drivers/generic/gfx/Makefile.inc | 1 - .../{generic/gfx => gfx/generic}/Kconfig | 2 +- src/drivers/gfx/generic/Makefile.inc | 1 + .../{generic/gfx => gfx/generic}/chip.h | 16 ++++++++-------- .../gfx/gfx.c => gfx/generic/generic.c} | 18 +++++++++--------- src/mainboard/google/drallion/Kconfig | 2 +- .../drallion/variants/drallion/devicetree.cb | 2 +- 7 files changed, 21 insertions(+), 21 deletions(-) delete mode 100644 src/drivers/generic/gfx/Makefile.inc rename src/drivers/{generic/gfx => gfx/generic}/Kconfig (80%) create mode 100644 src/drivers/gfx/generic/Makefile.inc rename src/drivers/{generic/gfx => gfx/generic}/chip.h (81%) rename src/drivers/{generic/gfx/gfx.c => gfx/generic/generic.c} (84%) diff --git a/src/drivers/generic/gfx/Makefile.inc b/src/drivers/generic/gfx/Makefile.inc deleted file mode 100644 index c31986be46..0000000000 --- a/src/drivers/generic/gfx/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_GENERIC_GFX) += gfx.c diff --git a/src/drivers/generic/gfx/Kconfig b/src/drivers/gfx/generic/Kconfig similarity index 80% rename from src/drivers/generic/gfx/Kconfig rename to src/drivers/gfx/generic/Kconfig index 1152f5bb7d..dcd1a8bc01 100644 --- a/src/drivers/generic/gfx/Kconfig +++ b/src/drivers/gfx/generic/Kconfig @@ -1,4 +1,4 @@ -config DRIVERS_GENERIC_GFX +config DRIVERS_GFX_GENERIC bool default n depends on HAVE_ACPI_TABLES diff --git a/src/drivers/gfx/generic/Makefile.inc b/src/drivers/gfx/generic/Makefile.inc new file mode 100644 index 0000000000..4ffe8dcc80 --- /dev/null +++ b/src/drivers/gfx/generic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GFX_GENERIC) += generic.c diff --git a/src/drivers/generic/gfx/chip.h b/src/drivers/gfx/generic/chip.h similarity index 81% rename from src/drivers/generic/gfx/chip.h rename to src/drivers/gfx/generic/chip.h index ee5bd1ff88..5e855e3853 100644 --- a/src/drivers/generic/gfx/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -13,11 +13,11 @@ * GNU General Public License for more details. */ -#ifndef __DRIVERS_GENERIC_GFX_CHIP_H__ -#define __DRIVERS_GENERIC_GFX_CHIP_H__ +#ifndef __DRIVERS_GFX_GENERIC_CHIP_H__ +#define __DRIVERS_GFX_GENERIC_CHIP_H__ /* Config for electronic privacy screen */ -struct drivers_generic_gfx_privacy_screen_config { +struct drivers_gfx_generic_privacy_screen_config { /* Is privacy screen available on this graphics device */ int enabled; /* ACPI namespace path to privacy screen detection function */ @@ -31,17 +31,17 @@ struct drivers_generic_gfx_privacy_screen_config { }; /* Config for an output device as defined in section A.5 of the ACPI spec */ -struct drivers_generic_gfx_device_config { +struct drivers_gfx_generic_device_config { /* ACPI device name of the output device */ const char *name; /* The address of the output device. See section A.3.2 */ unsigned int addr; /* Electronic privacy screen specific config */ - struct drivers_generic_gfx_privacy_screen_config privacy; + struct drivers_gfx_generic_privacy_screen_config privacy; }; /* Config for an ACPI video device defined in Appendix A of the ACPI spec */ -struct drivers_generic_gfx_config { +struct drivers_gfx_generic_config { /* * ACPI device name of the graphics card, "GFX0" will be used if name is * not set @@ -50,7 +50,7 @@ struct drivers_generic_gfx_config { /* The number of output devices defined */ int device_count; /* Config for output devices */ - struct drivers_generic_gfx_device_config device[5]; + struct drivers_gfx_generic_device_config device[5]; }; -#endif /* __DRIVERS_GENERIC_GFX_CHIP_H__ */ +#endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */ diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/gfx/generic/generic.c similarity index 84% rename from src/drivers/generic/gfx/gfx.c rename to src/drivers/gfx/generic/generic.c index 0386e9b2ef..8488040d30 100644 --- a/src/drivers/generic/gfx/gfx.c +++ b/src/drivers/gfx/generic/generic.c @@ -26,7 +26,7 @@ static void privacy_screen_detect_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_write_store(); acpigen_emit_namestring(config->detect_function); @@ -37,20 +37,20 @@ static void privacy_screen_detect_cb(void *arg) } static void privacy_screen_get_status_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring(config->status_function); } static void privacy_screen_enable_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_emit_namestring(config->enable_function); } static void privacy_screen_disable_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_emit_namestring(config->disable_function); } @@ -65,7 +65,7 @@ static void (*privacy_screen_callbacks[])(void *) = { static void gfx_fill_ssdt_generator(struct device *dev) { size_t i; - struct drivers_generic_gfx_config *config = dev->chip_info; + struct drivers_gfx_generic_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); @@ -103,7 +103,7 @@ static void gfx_fill_ssdt_generator(struct device *dev) static const char *gfx_acpi_name(const struct device *dev) { - struct drivers_generic_gfx_config *config = dev->chip_info; + struct drivers_gfx_generic_config *config = dev->chip_info; return config->name ? : "GFX0"; } @@ -115,7 +115,7 @@ static struct device_operations gfx_ops = { static void gfx_enable(struct device *dev) { - struct drivers_generic_gfx_config *config = dev->chip_info; + struct drivers_gfx_generic_config *config = dev->chip_info; if (!config) return; @@ -123,7 +123,7 @@ static void gfx_enable(struct device *dev) dev->ops = &gfx_ops; } -struct chip_operations drivers_generic_gfx_ops = { - CHIP_NAME("Graphics Device") +struct chip_operations drivers_gfx_generic_ops = { + CHIP_NAME("Generic Graphics Device") .enable_dev = gfx_enable }; diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index a0068580c7..61bae2b03d 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -2,7 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 - select DRIVERS_GENERIC_GFX + select DRIVERS_GFX_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index cdb6288173..d0006d64d7 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -226,7 +226,7 @@ chip soc/intel/cannonlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on - chip drivers/generic/gfx + chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" # Address is set following the ACPI spec section A.3.2 From 183ad06f522b279328acb70dfba52d31f9ff9c91 Mon Sep 17 00:00:00 2001 From: Alex Rebert Date: Thu, 20 Feb 2020 22:55:45 -0500 Subject: [PATCH 0104/1463] libpayload: Fix out-of-bounds read Fix an out-of-bounds read in the LZMA decoder which happens when the src buffer is too small to contain the 13-byte LZMA header. Change-Id: Ie442f82cd1abcf7fa18295e782cccf26a7d30079 Signed-off-by: Alex Rebert Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39033 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Menzel --- payloads/libpayload/liblzma/lzma.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/payloads/libpayload/liblzma/lzma.c b/payloads/libpayload/liblzma/lzma.c index 57a8b3a5c7..1845afc883 100644 --- a/payloads/libpayload/liblzma/lzma.c +++ b/payloads/libpayload/liblzma/lzma.c @@ -28,6 +28,11 @@ unsigned long ulzman(const unsigned char *src, unsigned long srcn, SizeT mallocneeds; unsigned char *scratchpad; + if (srcn < data_offset) { + printf("lzma: Input too small.\n"); + return 0; + } + memcpy(properties, src, LZMA_PROPERTIES_SIZE); memcpy(&outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize)); if (outSize > dstn) From ef90609cbb4229ccc242f67c48a8e14273bf0aac Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 20 Feb 2020 19:41:17 +0100 Subject: [PATCH 0105/1463] src: capitalize 'RAM' Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/commonlib/include/commonlib/timestamp_serialized.h | 4 ++-- src/cpu/intel/microcode/Kconfig | 2 +- src/drivers/intel/fsp1_1/exit_car.S | 2 +- src/drivers/intel/fsp2_0/Kconfig | 2 +- src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex | 2 +- src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex | 2 +- src/mainboard/hp/snb_ivb_laptops/Makefile.inc | 2 +- src/northbridge/intel/gm45/memmap.c | 4 ++-- src/northbridge/intel/i945/memmap.c | 4 ++-- src/northbridge/intel/pineview/memmap.c | 4 ++-- src/northbridge/intel/sandybridge/memmap.c | 4 ++-- src/northbridge/intel/x4x/memmap.c | 4 ++-- src/northbridge/intel/x4x/raminit_ddr23.c | 2 +- src/soc/intel/apollolake/glk_page_map.txt | 2 +- src/soc/intel/denverton_ns/Kconfig | 2 +- 15 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d7d636e6a4..ca72734df4 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -156,8 +156,8 @@ static const struct timestamp_id_to_name { /* Marker to report base_time. */ { 0, "1st timestamp" }, { TS_START_ROMSTAGE, "start of romstage" }, - { TS_BEFORE_INITRAM, "before ram initialization" }, - { TS_AFTER_INITRAM, "after ram initialization" }, + { TS_BEFORE_INITRAM, "before RAM initialization" }, + { TS_AFTER_INITRAM, "after RAM initialization" }, { TS_END_ROMSTAGE, "end of romstage" }, { TS_START_VBOOT, "start of verified boot" }, { TS_END_VBOOT, "end of verified boot" }, diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 238aad745d..c7bbecbace 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -4,4 +4,4 @@ config MICROCODE_UPDATE_PRE_RAM default y help Select this option if you want to update the microcode - during the cache as ram setup. + during the cache as RAM setup. diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S index 4b2822a887..a8db68afd8 100644 --- a/src/drivers/intel/fsp1_1/exit_car.S +++ b/src/drivers/intel/fsp1_1/exit_car.S @@ -17,7 +17,7 @@ chipset_teardown_car: pop %ebx - /* Move the stack pointer to real ram */ + /* Move the stack pointer to real RAM */ movl post_car_stack_top, %esp /* Align the stack 16 bytes */ andl $0xfffffff0, %esp diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index a8b3ac43a5..2d45343083 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -61,7 +61,7 @@ config FSP_USE_REPO and FSP_FD_PATH correctly so FSP splitting works. config FSP_T_FILE - string "Intel FSP-T (temp ram init) binary path and filename" + string "Intel FSP-T (temp RAM init) binary path and filename" depends on FSP_CAR default "$(obj)/Fsp_T.fd" if FSP_USE_REPO help diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex index 111310a24a..f3e3e75ded 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details. # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-1066 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex index ba3d5ac4bf..6e90bfa92d 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details. # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-800 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index d949ad8c05..50cea25914 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -20,5 +20,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -# FIXME: Other variants with same size onboard ram may exist. +# FIXME: Other variants with same size onboard RAM may exist. SPD_SOURCES = hynix_4g diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index d34820eb3d..33abc510a1 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -133,8 +133,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 54141205ec..83157d88ac 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -99,8 +99,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 0aa70cdb34..9fde9f7fdb 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -149,8 +149,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 6ebd7e0bb6..0784c11313 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -58,12 +58,12 @@ void fill_postcar_frame(struct postcar_frame *pcf) top_of_ram = (uintptr_t)cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to + * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems + /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 1924ddf678..334e6c7a37 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -144,8 +144,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index dd48d8ab63..1e871c7600 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1636,7 +1636,7 @@ static void set_dradrb(struct sysinfo *s) dual_channel_size = MIN(size_ch0, size_ch1) * 2; } else { if (size_ch0 == 0) { - /* ME needs ram on CH0 */ + /* ME needs RAM on CH0 */ size_me = 0; /* TOTEST: bailout? */ } else { diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt index e96a2db0ea..1a5f11fc0a 100644 --- a/src/soc/intel/apollolake/glk_page_map.txt +++ b/src/soc/intel/apollolake/glk_page_map.txt @@ -1,7 +1,7 @@ 0x00000000, 0x100000000, WB, # RAM # Above entry is needed because below 4G allocated memory range is # only known after FSP memory init completes. However, FSP migrates to memory -# from cache as ram before it exits FSP Memory Init. Hence we need to add +# from cache as RAM before it exits FSP Memory Init. Hence we need to add # page table entries for this entire range before FSP Memory Init. The # overlapped MMIO ranges will be overridden by below entries. 0xd0000000, 0x100000000, UC, NX # All of MMIO diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index aed2beb3fd..9a611271ab 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -59,7 +59,7 @@ config MMCONF_BASE_ADDRESS default 0xe0000000 config FSP_T_ADDR - hex "Intel FSP-T (temp ram init) binary location" + hex "Intel FSP-T (temp RAM init) binary location" depends on ADD_FSP_BINARIES && FSP_CAR default 0xfff30000 help From 3ae1765df67ff39cfe50222a1c6d05092d538057 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ivan=20Lab=C3=A1th?= Date: Sat, 22 Feb 2020 17:38:32 +0100 Subject: [PATCH 0106/1463] Documentation: getting_started/gpio.md: fix markup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2c61770d60a4f290fd8d516850f16bc3808ad48d Signed-off-by: Ivan Labáth Reviewed-on: https://review.coreboot.org/c/coreboot/+/39082 Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/getting_started/gpio.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 26939ce7cf..81a06eb410 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -25,7 +25,7 @@ how to appropriately set these registers. In addition, some mainboards are based on a baseboard/variant model, where several variant mainboards may share a lot of their circuitry and ICs and the commonality between the boards is collected into a virtual ``baseboard.`` In that case, the GPIOs which are shared -between multiple boards are placed in the baseboard's ``gpio.c` file, while the +between multiple boards are placed in the baseboard's ``gpio.c`` file, while the ones that are board-specific go into each variant's ``gpio.c`` file. ## Intel SoCs From e1ebabe3cd46d6f12c42c4b0b2518f085ba37731 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Fri, 14 Feb 2020 16:12:45 +0000 Subject: [PATCH 0107/1463] mainboard: Add missing include Add missing include for the boards that are being switched away from ROMCC_BOOTBLOCK. Signed-off-by: Mike Banon Change-Id: I83ff712f99388c4e6ea00a942eb57bcabb53a3fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38903 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/irq_tables.c | 1 + src/mainboard/amd/olivehill/irq_tables.c | 1 + src/mainboard/amd/parmer/irq_tables.c | 1 + src/mainboard/amd/persimmon/irq_tables.c | 1 + src/mainboard/amd/south_station/irq_tables.c | 1 + src/mainboard/amd/thatcher/irq_tables.c | 1 + src/mainboard/amd/union_station/irq_tables.c | 1 + src/mainboard/bap/ode_e20XX/irq_tables.c | 1 + src/mainboard/elmex/pcm205400/irq_tables.c | 1 + src/mainboard/gizmosphere/gizmo2/irq_tables.c | 1 + src/mainboard/hp/abm/irq_tables.c | 1 + src/mainboard/lippert/frontrunner-af/irq_tables.c | 1 + src/mainboard/lippert/toucan-af/irq_tables.c | 1 + 13 files changed, 13 insertions(+) diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index a066864abd..1d1e81f05e 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 530c132a05..181908a8ad 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 530c132a05..181908a8ad 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index a066864abd..1d1e81f05e 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index a066864abd..1d1e81f05e 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 530c132a05..181908a8ad 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index a066864abd..1d1e81f05e 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c index 530c132a05..181908a8ad 100644 --- a/src/mainboard/bap/ode_e20XX/irq_tables.c +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 804f52dcc5..d1149968aa 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -15,6 +15,7 @@ #include +#include #include #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/irq_tables.c b/src/mainboard/gizmosphere/gizmo2/irq_tables.c index 530c132a05..181908a8ad 100644 --- a/src/mainboard/gizmosphere/gizmo2/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index 530c132a05..181908a8ad 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index a066864abd..1d1e81f05e 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index a066864abd..1d1e81f05e 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include From d254fc4ac27a3de8c5e9840ae35cba557c7aa8ab Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 11:38:05 +0100 Subject: [PATCH 0108/1463] mb/amd: Fix typos Change-Id: I9abc0837b72b13e7614ecffa5b21c3d4bf41d0f8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39080 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/mainboard/amd/gardenia/irq_tables.c | 2 +- src/mainboard/amd/padmelon/gpio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c index 66dafb7f28..2aefaea7ba 100644 --- a/src/mainboard/amd/gardenia/irq_tables.c +++ b/src/mainboard/amd/gardenia/irq_tables.c @@ -76,7 +76,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - /* pci bridge */ + /* PCI bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index df53c4a516..09e580e89d 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -24,7 +24,7 @@ * ramstage. */ static const struct soc_amd_gpio gpio_set_stage_reset[] = { - /* GFX presense detect */ + /* GFX presence detect */ PAD_GPI(GPIO_9, PULL_DOWN), /* VDDP_VCTRL */ PAD_GPO(GPIO_40, HIGH), From 22f8ee0f0ee8383238cd92cec0b6e42ed0651ee8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 14:13:59 +0100 Subject: [PATCH 0109/1463] mb/google: Fix typos Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39081 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- .../auron/variants/auron_paine/include/variant/hda_verb.h | 2 +- .../auron/variants/auron_yuna/include/variant/hda_verb.h | 2 +- .../google/auron/variants/buddy/include/variant/hda_verb.h | 2 +- src/mainboard/google/auron/variants/buddy/pei_data.c | 4 ++-- src/mainboard/google/auron/variants/buddy/variant.c | 2 +- .../google/auron/variants/gandof/include/variant/hda_verb.h | 2 +- .../google/auron/variants/lulu/include/variant/hda_verb.h | 2 +- src/mainboard/google/beltino/variants/mccloud/hda_verb.c | 2 +- src/mainboard/google/beltino/variants/monroe/hda_verb.c | 2 +- src/mainboard/google/beltino/variants/panther/hda_verb.c | 2 +- src/mainboard/google/beltino/variants/tricky/hda_verb.c | 2 +- src/mainboard/google/beltino/variants/zako/hda_verb.c | 2 +- src/mainboard/google/jecht/hda_verb.c | 2 +- src/mainboard/google/parrot/hda_verb.c | 2 +- src/mainboard/google/slippy/variants/falco/hda_verb.c | 2 +- src/mainboard/google/slippy/variants/leon/hda_verb.c | 2 +- src/mainboard/google/slippy/variants/peppy/hda_verb.c | 2 +- src/mainboard/google/slippy/variants/wolf/hda_verb.c | 2 +- 18 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h index 520879bd57..d560ccf968 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h @@ -72,7 +72,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h index 31b97a045a..70913215c9 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h @@ -68,7 +68,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h index 7fd9853d8e..7d0af93481 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h @@ -85,7 +85,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable 0x01d71d81, // mute spkr on hpout - 0x01d71e15, // pcbeep en able, checksum + 0x01d71e15, // pcbeep enable, checksum 0x01d71f40, // no physical, Internal, Location N/A /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index f3463727eb..a0436ecc89 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -32,7 +32,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* P2: Rear USB3.0 port, USB3R2 */ pei_data_usb2_port(pei_data, 2, 0x0080, 1, 1, USB_PORT_INTERNAL); - /* P3: Card Rearder, CRS1 */ + /* P3: Card Reader, CRS1 */ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); /* P4: Rear USB2.0 port, USB2R1 */ @@ -54,6 +54,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data_usb3_port(pei_data, 1, 1, 0, 0); /* P3: Rear USB3.0 port, USB3R2 */ pei_data_usb3_port(pei_data, 2, 1, 1, 0); - /* P4: Card Rearder, CRS1 */ + /* P4: Card Reader, CRS1 */ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 58fee1ef18..4e05711970 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -179,7 +179,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN PCI config space 0x81h=01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h index 48419741ce..23e9146751 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h @@ -72,7 +72,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h index e00d5b0cda..cfc279ac0b 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h @@ -72,7 +72,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 14f1410747..57e5fa2dca 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 964687c770..0e71960ee1 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -55,7 +55,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 14f1410747..57e5fa2dca 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 14f1410747..57e5fa2dca 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 14f1410747..57e5fa2dca 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 535e7e8600..0b0127e2b5 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index c91cd29682..e22f6edde3 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -78,7 +78,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/falco/hda_verb.c b/src/mainboard/google/slippy/variants/falco/hda_verb.c index 02d39072ae..745a3a7d4c 100644 --- a/src/mainboard/google/slippy/variants/falco/hda_verb.c +++ b/src/mainboard/google/slippy/variants/falco/hda_verb.c @@ -63,7 +63,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/leon/hda_verb.c b/src/mainboard/google/slippy/variants/leon/hda_verb.c index 6e01ca58aa..13fbb4d53a 100644 --- a/src/mainboard/google/slippy/variants/leon/hda_verb.c +++ b/src/mainboard/google/slippy/variants/leon/hda_verb.c @@ -63,7 +63,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/peppy/hda_verb.c b/src/mainboard/google/slippy/variants/peppy/hda_verb.c index 4d6ef3430a..0b1b69c370 100644 --- a/src/mainboard/google/slippy/variants/peppy/hda_verb.c +++ b/src/mainboard/google/slippy/variants/peppy/hda_verb.c @@ -67,7 +67,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c index 11ff65b1c0..e1eb5eda50 100644 --- a/src/mainboard/google/slippy/variants/wolf/hda_verb.c +++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c @@ -68,7 +68,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), From e9f86c1016bc71eb0d9f7bb4b5f3ce36c56f100b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 18 Feb 2020 19:00:32 +0100 Subject: [PATCH 0110/1463] soc/amd/common/block/include/amdblocks: Fix typos Change-Id: I8363816a51c342935668545a8b39acce96ce4b2c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38980 Reviewed-by: Jacob Garber Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/include/amdblocks/gpio_banks.h | 2 +- src/soc/amd/common/block/include/amdblocks/lpc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 2206e35ff2..8600e64fcc 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -303,7 +303,7 @@ uintptr_t gpio_get_address(gpio_t gpio_num); void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); /* Return the interrupt status and clear if set. */ int gpio_interrupt_status(gpio_t gpio); -/* Implemented by soc, provides table of avaialable GPIO mapping to Gevents */ +/* Implemented by soc, provides table of available GPIO mapping to Gevents */ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items); /* May be implemented by soc to handle special cases */ void soc_gpio_hook(uint8_t gpio, uint8_t mux); diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 2874c18879..2f8cd971f1 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -103,7 +103,7 @@ #define LPC_MEM_PORT0 0x60 /* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. - For ease of access, each sub-register is declared separetely. */ + For ease of access, each sub-register is declared separately. */ #define LPC_WIDEIO_GENERIC_PORT 0x64 #define LPC_WIDEIO1_GENERIC_PORT 0x66 #define ROM_ADDRESS_RANGE1_START 0x68 From 1b296ee3b832bc9dbff57c680a3de509db3c95fd Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 19 Feb 2020 20:48:29 +0100 Subject: [PATCH 0111/1463] soc/{samsung,sifive}: Fix typos Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39016 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- src/soc/samsung/exynos5420/spi.c | 2 +- src/soc/sifive/fu540/clock.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index a98f51d72c..ec9002399b 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -101,7 +101,7 @@ static void exynos_spi_init(struct exynos_spi *regs) // CPOL: Active high. clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); - // Clear rx and tx channel if set priveously. + // Clear rx and tx channel if set previously. clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); setbits32(®s->swap_cfg, diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index a15e639839..ad5e06b65e 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -104,7 +104,7 @@ static void configure_pll(u32 *reg, const struct pll_settings *s) * Set coreclk according to the SiFive FU540-C000 Manual * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/ * - * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 Ghz is possible) + * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible) * * Section 7.4.2 provides the necessary values: * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1), From 23e3f9d6ed4f841f0c5222a2aa2cb586f2210d95 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 3 Feb 2020 21:07:19 +0100 Subject: [PATCH 0112/1463] src/commonlib: Fix typos Change-Id: Ida1770c5e4b18c536e4943eb9cf862d69196c589 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38689 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/commonlib/cbfs.c | 2 +- src/commonlib/include/commonlib/storage.h | 2 +- src/commonlib/storage/sd.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 5c9aacba20..be0de9f6aa 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -44,7 +44,7 @@ static size_t cbfs_next_offset(const struct region_device *cbfs, if (f == NULL) return 0; - /* The region_device objects store absolute offets over the whole + /* The region_device objects store absolute offsets over the whole * region. Therefore a relative offset needs to be calculated. */ offset = rdev_relative_offset(cbfs, &f->data); offset += region_device_sz(&f->data); diff --git a/src/commonlib/include/commonlib/storage.h b/src/commonlib/include/commonlib/storage.h index 47a2bb6543..faba2fe5a9 100644 --- a/src/commonlib/include/commonlib/storage.h +++ b/src/commonlib/include/commonlib/storage.h @@ -57,7 +57,7 @@ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ #define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */ -#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ +#define EXT_CSD_TIMING_BC 0 /* Backwards compatibility */ #define EXT_CSD_TIMING_HS 1 /* High speed */ #define EXT_CSD_TIMING_HS200 2 /* HS200 */ #define EXT_CSD_TIMING_HS400 3 /* HS400 */ diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index bdb0baa2e4..30af81088d 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -220,7 +220,7 @@ int sd_change_freq(struct storage_media *media) if (!((ctrlr->caps & DRVR_CAP_HS52) && (ctrlr->caps & DRVR_CAP_HS))) goto out; - /* Give the card time to recover afer the switch operation. Wait for + /* Give the card time to recover after the switch operation. Wait for * 9 (>= 8) clock cycles receiving the switch status. */ delay = (9000000 + ctrlr->bus_hz - 1) / ctrlr->bus_hz; From 8d1b0f1dbd2736391d4011106527a1e5b286307d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 20 Feb 2020 18:20:57 +0100 Subject: [PATCH 0113/1463] soc/rockchip: Fix typos Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39028 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/rockchip/common/edp.c | 2 +- src/soc/rockchip/rk3288/hdmi.c | 2 +- src/soc/rockchip/rk3288/tsadc.c | 2 +- src/soc/rockchip/rk3399/clock.c | 4 ++-- src/soc/rockchip/rk3399/mipi.c | 2 +- src/soc/rockchip/rk3399/tsadc.c | 4 ++-- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 18afc3a50a..060099c230 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -135,7 +135,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) static void rk_edp_init_aux(struct rk_edp *edp) { - /* Clear inerrupts related to AUX channel */ + /* Clear interrupts related to AUX channel */ write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index cd9890bc9b..36a08a9000 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -733,7 +733,7 @@ static int hdmi_read_edid(int block, u8 *buff) u32 trytime = 5; u32 n, j, val; - /* set ddc i2c clk which devided from ddc_clk to 100khz */ + /* set ddc i2c clk which derived from ddc_clk to 100kHz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index de3d0580ff..7a1e34d4a3 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -100,7 +100,7 @@ void tsadc_init(void) /* tsadc iomux must be set after the tshut polarity setting, - since the tshut polarity defalut low active, + since the tshut polarity default low active, so if you enable tsadc iomux,it will output high */ setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 4cd2839547..d2f5b7c6d1 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -304,7 +304,7 @@ static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " - "postdiv2=%d, vco=%u khz, output=%u khz\n", + "postdiv2=%d, vco=%u kHz, output=%u kHz\n", pll_con, div->fbdiv, div->refdiv, div->postdiv1, div->postdiv2, vco_khz, output_khz); assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && @@ -485,7 +485,7 @@ void rkclk_init(void) /* some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. - * Please consider these threee lines as a fix of bootrom bug. + * Please consider these three lines as a fix of bootrom bug. */ write32(&cru_ptr->clksel_con[12], 0xffff4101); write32(&cru_ptr->clksel_con[19], 0xffff033f); diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 751c8a5e63..5df5fdf1e6 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -319,7 +319,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi, min_prediv = DIV_ROUND_UP(fref, 40 * MHz); max_prediv = fref / (5 * MHz); - /* constraint: 80MHz <= Fvco <= 1500Mhz */ + /* constraint: 80MHz <= Fvco <= 1500MHz */ fvco_min = 80 * MHz; fvco_max = 1500 * MHz; min_delta = 1500 * MHz; diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 1cdb355237..9f699150fc 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -112,7 +112,7 @@ void tsadc_init(uint32_t polarity) /* setup the automatic mode: * AUTO_PERIOD: interleave between every two accessing of TSADC - * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temprature + * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temperature * is higher than COMP_INT for "debounce" times * AUTO_PERIOD_HT: the interleave between every two accessing after the * temperature is higher than COMP_SHUT or COMP_INT @@ -123,7 +123,7 @@ void tsadc_init(uint32_t polarity) write32(&rk3399_tsadc->hight_int_debounce, AUTO_DEBOUNCE); write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); - /* Enable the src0, negative temprature coefficient */ + /* Enable the src0, negative temperature coefficient */ setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); setbits32(&rk3399_tsadc->auto_con, AUTO_EN); From 255aeaa9a27bf9c2eab6db57a20153aa16947559 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 19 Feb 2020 11:55:34 +0800 Subject: [PATCH 0114/1463] libpayload: cbgfx: Fix potential overflowing expression BRANCH=none BUG=none TEST=none Change-Id: Icd37a6abc01d9fcbcf54525d47b15c9930a9b9fb Signed-off-by: Yu-Ping Wu Found-by: Coverity Scan #1419491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38987 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- payloads/libpayload/drivers/video/graphics.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 8cb984b872..9494de31f5 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -349,8 +349,8 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, /* Use 64 bits to avoid overflow */ int32_t x, y; uint64_t yy; - const uint64_t rrx = r.x * r.x, rry = r.y * r.y; - const uint64_t ssx = s.x * s.x, ssy = s.y * s.y; + const uint64_t rrx = (uint64_t)r.x * r.x, rry = (uint64_t)r.y * r.y; + const uint64_t ssx = (uint64_t)s.x * s.x, ssy = (uint64_t)s.y * s.y; x_begin = 0; x_end = 0; for (y = r.y - 1; y >= 0; y--) { @@ -358,7 +358,7 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, * The inequality is valid in the beginning of each iteration: * y^2 + x_end^2 < r^2 */ - yy = y * y; + yy = (uint64_t)y * y; /* Check yy/ssy + xx/ssx < 1 */ while (yy * ssx + x_begin * x_begin * ssy < ssx * ssy) x_begin++; From 672a4feee628ef9e6117f4b1e9ad3b1324369545 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 21 Feb 2020 14:11:29 -0600 Subject: [PATCH 0115/1463] device/Kconfig: select linear framebuffer for Tianocore Automatically select the linear framebuffer mode option if available when Tianocore selected as payload, since VGA text mode will not work properly with the default Tianocore payload. Change-Id: Ic36fd035526f3efd00ffa12ad613fbac304b18cf Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39048 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/device/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index 603c7eb8d1..25123ea3e0 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -413,6 +413,8 @@ choice prompt "Framebuffer mode" default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && CHROMEOS default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && CHROMEOS + default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && PAYLOAD_TIANOCORE + default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && PAYLOAD_TIANOCORE default VGA_TEXT_FRAMEBUFFER config VGA_TEXT_FRAMEBUFFER From f07d3b45856fb3cb62d684e526c4fd2af76ee33f Mon Sep 17 00:00:00 2001 From: Usha P Date: Wed, 19 Feb 2020 14:06:09 +0530 Subject: [PATCH 0116/1463] mb/intel/jasperlake_rvp: Disable SATA controller This patch disables the SATA config from devicetree for JSL RVP, since we are not planning to use the SATA storage in chrome config. Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2 Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: V Sowmya --- .../variants/jslrvp/devicetree.cb | 22 ++----------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 843de142b3..9c40f66210 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -66,25 +66,7 @@ chip soc/intel/tigerlake # ClkReq-to-ClkSrc mapping for CLK SRC 0 register "PcieClkSrcClkReq[0]" = "0x00" - register "SataEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "SataPortsDevSlp[3]" = "1" - register "SataPortsDevSlp[4]" = "1" - register "SataPortsDevSlp[5]" = "1" - register "SataPortsDevSlp[6]" = "1" - register "SataPortsDevSlp[7]" = "1" + register "SataEnable" = "0" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -256,7 +238,7 @@ chip soc/intel/tigerlake device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 off end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 From 9d667906f3c0029dbea41580a0d0961cf1ab2fc9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 19 Feb 2020 19:09:06 +0530 Subject: [PATCH 0117/1463] soc/intel/icelake: Skip FSP-S IGD related UPD override Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence related FSP-S UPD override can be avoided from coreboot. As per FSP-S UPD Header (FspsUpd.h) /** Offset 0x020E - GT Frequency Limit 0xFF: Auto(Default) **/ UINT8 GtFreqMax; /** Offset 0x0209 - CdClock Frequency selection 0: (Default) Auto **/ UINT8 CdClock; TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform. Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya --- src/soc/intel/icelake/fsp_params.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 448b82c7d8..7514be107d 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -96,10 +96,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0; - if (dev && dev->enabled) { - params->GtFreqMax = 2; - params->CdClock = 3; - } /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; From d6cb3bc9424f67173a08a704369103ac691764dc Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 15:26:20 +0000 Subject: [PATCH 0118/1463] src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon Change-Id: Ifb50fd22f5ef4db204a3427e03430177cad211cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38866 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/hp/abm/Kconfig | 4 --- src/mainboard/hp/abm/Kconfig.name | 4 +-- src/mainboard/hp/abm/Makefile.inc | 2 ++ src/mainboard/hp/abm/bootblock.c | 39 +++++++++++++++++++++ src/mainboard/hp/abm/romstage.c | 58 ------------------------------- 5 files changed, 43 insertions(+), 64 deletions(-) create mode 100644 src/mainboard/hp/abm/bootblock.c delete mode 100644 src/mainboard/hp/abm/romstage.c diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 907c02546c..f4883b0331 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_HP_ABM - def_bool n - if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig.name b/src/mainboard/hp/abm/Kconfig.name index 27eda0c7d9..4ace57323d 100644 --- a/src/mainboard/hp/abm/Kconfig.name +++ b/src/mainboard/hp/abm/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_HP_ABM -# bool"ABM" +config BOARD_HP_ABM + bool "ABM" diff --git a/src/mainboard/hp/abm/Makefile.inc b/src/mainboard/hp/abm/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/hp/abm/Makefile.inc +++ b/src/mainboard/hp/abm/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/hp/abm/bootblock.c b/src/mainboard/hp/abm/bootblock.c new file mode 100644 index 0000000000..a48ba772e1 --- /dev/null +++ b/src/mainboard/hp/abm/bootblock.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) + +void bootblock_mainboard_early_init(void) +{ + u32 reg32; + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ + reg32 = misc_read32(0x28); + reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] + reg32 |= 0x00010000; // Set bit 16 for 25MHz + misc_write32(0x28, reg32); + + /* Enable Auxiliary OSCOUT1/OSCOUT2 */ + reg32 = misc_read32(0x40); + reg32 &= 0xffffff7b; // clear 2, 7 + misc_write32(0x40, reg32); + + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c deleted file mode 100644 index 5092e1772f..0000000000 --- a/src/mainboard/hp/abm/romstage.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u32 t32; - - /* For serial port option, plug-in card on LPC. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - pm_io_write8(0xd2, 0); - - /* Enable the AcpiMmio space */ - pm_io_write8(0x24, 1); - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ - /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ - t32 = misc_read32(0x28); - t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] - t32 |= 0x00010000; // Set bit 16 for 25MHz - misc_write(0x28, t32); - - /* Enable Auxiliary OSCOUT1/OSCOUT2 */ - t32 = misc_write32(0x40, misc_read32(0x40) & 0xffffff7b); - - nct5104d_enable_uartd(SERIAL_DEV); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} From 938ae2655f1ef076278c7327f343ae786e9a491c Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:13:18 +0000 Subject: [PATCH 0119/1463] mb/amd/persimmon: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I51d42f137fa539225bca5631bec38144ffd4f1d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38873 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/persimmon/Kconfig | 4 ---- src/mainboard/amd/persimmon/Kconfig.name | 4 ++-- src/mainboard/amd/persimmon/Makefile.inc | 2 ++ src/mainboard/amd/persimmon/{romstage.c => bootblock.c} | 6 ++---- 4 files changed, 6 insertions(+), 10 deletions(-) rename src/mainboard/amd/persimmon/{romstage.c => bootblock.c} (85%) diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index f243f0f9c7..41bf3c9c2e 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_PERSIMMON - def_bool n - if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name index d50ebbe8cd..ba24b13aa4 100644 --- a/src/mainboard/amd/persimmon/Kconfig.name +++ b/src/mainboard/amd/persimmon/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_PERSIMMON -# bool"Persimmon" +config BOARD_AMD_PERSIMMON + bool "Persimmon" diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index ba56286636..bf86007cec 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/bootblock.c similarity index 85% rename from src/mainboard/amd/persimmon/romstage.c rename to src/mainboard/amd/persimmon/bootblock.c index 7ccf1674d7..6cd9e2a59a 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From 44db2f60121d90c1829b66523357c26b9a9bf358 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:31:32 +0000 Subject: [PATCH 0120/1463] mb/amd/parmer: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: Ic3fda4e598af8df9c9ddc97f7eb7fdcdaff6580b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38879 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/parmer/Kconfig | 4 ---- src/mainboard/amd/parmer/Kconfig.name | 4 ++-- src/mainboard/amd/parmer/Makefile.inc | 2 ++ src/mainboard/amd/parmer/{romstage.c => bootblock.c} | 9 ++------- 4 files changed, 6 insertions(+), 13 deletions(-) rename src/mainboard/amd/parmer/{romstage.c => bootblock.c} (68%) diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index ae024dd91f..820d43ebf6 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_PARMER - def_bool n - if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/parmer/Kconfig.name b/src/mainboard/amd/parmer/Kconfig.name index 07714686dd..3aedc956ae 100644 --- a/src/mainboard/amd/parmer/Kconfig.name +++ b/src/mainboard/amd/parmer/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_PARMER -# bool"Parmer" +config BOARD_AMD_PARMER + bool "Parmer" diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/bootblock.c similarity index 68% rename from src/mainboard/amd/parmer/romstage.c rename to src/mainboard/amd/parmer/bootblock.c index 6366c4e348..fea4d7b632 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/bootblock.c @@ -13,14 +13,9 @@ * GNU General Public License for more details. */ +#include #include -#include -#include -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - - /* For serial port option, plug-in card on LPC. */ - pci_write_config32(dev, 0x44, 0xff03ffd5); } From e3229a5192a84c04a4d1f0307d8cfb5e864b7ff3 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 15:34:24 +0000 Subject: [PATCH 0121/1463] mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/olivehill/Kconfig | 4 --- src/mainboard/amd/olivehill/Kconfig.name | 4 +-- src/mainboard/amd/olivehill/Makefile.inc | 2 ++ .../amd/olivehill/{romstage.c => bootblock.c} | 25 +++---------------- 4 files changed, 8 insertions(+), 27 deletions(-) rename src/mainboard/amd/olivehill/{romstage.c => bootblock.c} (52%) diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 78f768f132..bd3dd9384c 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_OLIVEHILL - def_bool n - if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name index d065472731..fd1a713aac 100644 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ b/src/mainboard/amd/olivehill/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_OLIVEHILL -# bool"Olive Hill" +config BOARD_AMD_OLIVEHILL + bool "Olive Hill" diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/bootblock.c similarity index 52% rename from src/mainboard/amd/olivehill/romstage.c rename to src/mainboard/amd/olivehill/bootblock.c index dfe7c49f9f..d1f8d606e4 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,32 +11,17 @@ * GNU General Public License for more details. */ -#include #include -#include -#include -#include -#include -#include +#include +#include -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { int i; u32 val; - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - pm_io_write8(0xd2, 0); - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - pm_io_write8(0xea, 1); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); + pm_write8(0xea, 0x1); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ for (i = 0; i < 200000; i++) From c896df7f158cf759906f4f164330fb552bbe0fec Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:16:01 +0000 Subject: [PATCH 0122/1463] mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 4 ---- src/mainboard/jetway/nf81-t56n-lf/Kconfig.name | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 2 ++ .../jetway/nf81-t56n-lf/{romstage.c => bootblock.c} | 6 ++---- 4 files changed, 6 insertions(+), 10 deletions(-) rename src/mainboard/jetway/nf81-t56n-lf/{romstage.c => bootblock.c} (87%) diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index dfa01b93a6..d2dda6725f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_JETWAY_NF81_T56N_LF - def_bool n - if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name index 0b676274ae..2e660f937c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_JETWAY_NF81_T56N_LF -# bool"NF81_T56N_LF" +config BOARD_JETWAY_NF81_T56N_LF + bool "NF81_T56N_LF" diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index ba56286636..bf86007cec 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c similarity index 87% rename from src/mainboard/jetway/nf81-t56n-lf/romstage.c rename to src/mainboard/jetway/nf81-t56n-lf/bootblock.c index 5e61bddfcc..5ecfaf74f8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c @@ -14,16 +14,14 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From 6ed9df448b4d025a4caa01b594fca90724eef691 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:29:11 +0000 Subject: [PATCH 0123/1463] mb/lippert/toucan-af: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I22774a6d6a32c2fb8340f5ac678befe0d5f8ad75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38878 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/lippert/toucan-af/Kconfig | 4 ---- src/mainboard/lippert/toucan-af/Kconfig.name | 4 ++-- src/mainboard/lippert/toucan-af/Makefile.inc | 2 ++ src/mainboard/lippert/toucan-af/{romstage.c => bootblock.c} | 6 ++---- src/mainboard/lippert/toucan-af/dsdt.asl | 1 - 5 files changed, 6 insertions(+), 11 deletions(-) rename src/mainboard/lippert/toucan-af/{romstage.c => bootblock.c} (85%) diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index b62da2e333..74b335a9fa 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_LIPPERT_TOUCAN_AF - def_bool n - if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig.name b/src/mainboard/lippert/toucan-af/Kconfig.name index 6eceb51f0c..3481f92fba 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig.name +++ b/src/mainboard/lippert/toucan-af/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_LIPPERT_TOUCAN_AF -# bool"Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" +config BOARD_LIPPERT_TOUCAN_AF + bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index 1080c64ded..7e4f2804bb 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/bootblock.c similarity index 85% rename from src/mainboard/lippert/toucan-af/romstage.c rename to src/mainboard/lippert/toucan-af/bootblock.c index ebbe4fc0df..39b108e6dc 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 347f1a1a02..4e36c2b152 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1123,7 +1123,6 @@ DefinitionBlock ( External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Operating System Capabilities Method */ Method (_OSC, 4) From bb45f38eb9d0ecc6f4a1d0ca37c8c52212360c56 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 15:45:05 +0000 Subject: [PATCH 0124/1463] mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38869 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/bap/ode_e20XX/Kconfig | 4 ---- src/mainboard/bap/ode_e20XX/Kconfig.name | 4 ++-- src/mainboard/bap/ode_e20XX/Makefile.inc | 2 ++ .../bap/ode_e20XX/{romstage.c => bootblock.c} | 19 +++---------------- 4 files changed, 7 insertions(+), 22 deletions(-) rename src/mainboard/bap/ode_e20XX/{romstage.c => bootblock.c} (61%) diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 2a72debf58..4df74c0c24 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_ODE_E20XX - def_bool n - if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index 54ddcac682..a482846808 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ODE_E20XX -# bool"ODE_e20xx" +config BOARD_ODE_E20XX + bool "ODE_e20xx" diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 4d8eb8dba0..8747d2fecb 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/bootblock.c similarity index 61% rename from src/mainboard/bap/ode_e20XX/romstage.c rename to src/mainboard/bap/ode_e20XX/bootblock.c index c1b96f1273..8744547bfc 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/bootblock.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,26 +11,17 @@ * GNU General Public License for more details. */ -#include #include -#include -#include - -#include +#include #include #include - #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - pm_io_write(0xea, 1); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); + pm_write8(0xea, 0x1); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } From 0dcbcd31918cd0dd7e4f1086649dfe4a04397633 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:05:35 +0000 Subject: [PATCH 0125/1463] mb/amd/south_station: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: Iba1d020b9e565e3c6c89a97114084d72a00b2a55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38871 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/south_station/Kconfig | 4 ---- src/mainboard/amd/south_station/Kconfig.name | 4 ++-- src/mainboard/amd/south_station/Makefile.inc | 2 ++ src/mainboard/amd/south_station/{romstage.c => bootblock.c} | 6 ++---- 4 files changed, 6 insertions(+), 10 deletions(-) rename src/mainboard/amd/south_station/{romstage.c => bootblock.c} (85%) diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 42841cbb93..a059403c7b 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_SOUTHSTATION - def_bool n - if BOARD_AMD_SOUTHSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/south_station/Kconfig.name b/src/mainboard/amd/south_station/Kconfig.name index f8f1404af2..0cc745e3bc 100644 --- a/src/mainboard/amd/south_station/Kconfig.name +++ b/src/mainboard/amd/south_station/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_SOUTHSTATION -# bool"Southstation" +config BOARD_AMD_SOUTHSTATION + bool "Southstation" diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index 440744c479..ffea060d80 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/bootblock.c similarity index 85% rename from src/mainboard/amd/south_station/romstage.c rename to src/mainboard/amd/south_station/bootblock.c index 7ccf1674d7..6cd9e2a59a 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From 0bed4c84cc73870bb9757fc5229d33032ff71b5b Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:25:10 +0000 Subject: [PATCH 0126/1463] mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/38877 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/thatcher/Kconfig | 4 -- src/mainboard/amd/thatcher/Kconfig.name | 4 +- src/mainboard/amd/thatcher/Makefile.inc | 2 + .../amd/thatcher/{romstage.c => bootblock.c} | 38 +++++-------------- 4 files changed, 13 insertions(+), 35 deletions(-) rename src/mainboard/amd/thatcher/{romstage.c => bootblock.c} (55%) diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e55659225f..e1c5aee487 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_THATCHER - def_bool n - if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name index b57bdb9a7f..aff5246cc7 100644 --- a/src/mainboard/amd/thatcher/Kconfig.name +++ b/src/mainboard/amd/thatcher/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_THATCHER -# bool"Thatcher" +config BOARD_AMD_THATCHER + bool "Thatcher" diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/bootblock.c similarity index 55% rename from src/mainboard/amd/thatcher/romstage.c rename to src/mainboard/amd/thatcher/bootblock.c index dff516ca3a..d25102541c 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,42 +11,24 @@ * GNU General Public License for more details. */ +#include +#include #include -#include -#include -#include -#include #include -#include -#include -#include +#include #include #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - u8 byte; - pci_devfn_t dev; - - /* Set LPC decode enables. */ - dev = PCI_DEV(0, 0x14, 3); - - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - post_code(0x30); - /* For serial port. */ - pci_write_config32(dev, 0x44, 0xff03ffd5); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - post_code(0x31); - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - pm_io_write8(0x24, 1); - pm_io_write8(0xea, 1); gpio_100_write8(0x1, 0x98); + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From a185665de442be7ce6d498c9ae2359f938d173cf Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:07:54 +0000 Subject: [PATCH 0127/1463] mb/lippert/frontrunner-af: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I63dd15ade28acb06da8d320edc8ae1fd433aa0e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/lippert/frontrunner-af/Kconfig | 4 ---- src/mainboard/lippert/frontrunner-af/Kconfig.name | 4 ++-- src/mainboard/lippert/frontrunner-af/Makefile.inc | 2 ++ .../lippert/frontrunner-af/{romstage.c => bootblock.c} | 5 ++--- src/mainboard/lippert/frontrunner-af/dsdt.asl | 1 - 5 files changed, 6 insertions(+), 10 deletions(-) rename src/mainboard/lippert/frontrunner-af/{romstage.c => bootblock.c} (90%) diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 4a007bf394..92d77434f5 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_LIPPERT_FRONTRUNNER_AF - def_bool n - if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name index 1939264bc4..2a8cba52ab 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig.name +++ b/src/mainboard/lippert/frontrunner-af/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_LIPPERT_FRONTRUNNER_AF -# bool"FrontRunner-AF aka ADLINK CoreModule2-GF" +config BOARD_LIPPERT_FRONTRUNNER_AF + bool "FrontRunner-AF aka ADLINK CoreModule2-GF" diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 3ea57cd1e3..46a44d20ef 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/bootblock.c similarity index 90% rename from src/mainboard/lippert/frontrunner-af/romstage.c rename to src/mainboard/lippert/frontrunner-af/bootblock.c index f8e6091af0..e0dddc20cc 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/bootblock.c @@ -13,14 +13,13 @@ * GNU General Public License for more details. */ +#include #include #include -#include #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 07b50713c7..9fcc7aef03 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1124,7 +1124,6 @@ DefinitionBlock ( External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Operating System Capabilities Method */ Method (_OSC, 4) From dddd5cca75520fda927f32acf3a3a8cb29ab3a41 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:18:27 +0000 Subject: [PATCH 0128/1463] mb/amd/union_station: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I0edfc7bb6d01eb1a12299fddd3d3ac45b43edfdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38875 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/union_station/Kconfig | 4 ---- src/mainboard/amd/union_station/Kconfig.name | 4 ++-- src/mainboard/amd/union_station/Makefile.inc | 2 ++ src/mainboard/amd/union_station/{romstage.c => bootblock.c} | 6 ++---- 4 files changed, 6 insertions(+), 10 deletions(-) rename src/mainboard/amd/union_station/{romstage.c => bootblock.c} (81%) diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 1532d34062..72881b8d4c 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_UNIONSTATION - def_bool n - if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name index b4dc53656d..9af3c8270b 100644 --- a/src/mainboard/amd/union_station/Kconfig.name +++ b/src/mainboard/amd/union_station/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_UNIONSTATION -# bool"Unionstation" +config BOARD_AMD_UNIONSTATION + bool "Unionstation" diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index 440744c479..ffea060d80 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/bootblock.c similarity index 81% rename from src/mainboard/amd/union_station/romstage.c rename to src/mainboard/amd/union_station/bootblock.c index af64ad8b50..f0361d6cf0 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/bootblock.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#include -#include +#include -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); } From 541498be0a1921ee62b96bd07bc38af584c1e06e Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:02:50 +0000 Subject: [PATCH 0129/1463] mb/elmex/pcm20540*: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I53b80fe97370c99968f073dfad61b5e5709e4ab6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38870 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/elmex/pcm205400/Kconfig | 4 ---- src/mainboard/elmex/pcm205400/Kconfig.name | 4 ++-- src/mainboard/elmex/pcm205400/Makefile.inc | 2 ++ src/mainboard/elmex/pcm205400/{romstage.c => bootblock.c} | 6 ++---- src/mainboard/elmex/pcm205401/Kconfig | 3 --- src/mainboard/elmex/pcm205401/Kconfig.name | 4 ++-- 6 files changed, 8 insertions(+), 15 deletions(-) rename src/mainboard/elmex/pcm205400/{romstage.c => bootblock.c} (85%) diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index e94a6d89bb..7dc67d17ea 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -13,9 +13,6 @@ # GNU General Public License for more details. # -config BOARD_ELMEX_PCM205400 - def_bool n - if BOARD_ELMEX_PCM205400 config MAINBOARD_PART_NUMBER @@ -32,7 +29,6 @@ if BOARD_ELMEX_PCM205400 || BOARD_ELMEX_PCM205401 config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name index 6488992de2..445b58868a 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig.name +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ELMEX_PCM205400 -# bool"pcm205400" +config BOARD_ELMEX_PCM205400 + bool "pcm205400" diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc index ba56286636..bf86007cec 100644 --- a/src/mainboard/elmex/pcm205400/Makefile.inc +++ b/src/mainboard/elmex/pcm205400/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/bootblock.c similarity index 85% rename from src/mainboard/elmex/pcm205400/romstage.c rename to src/mainboard/elmex/pcm205400/bootblock.c index 7ccf1674d7..6cd9e2a59a 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index 15c741abf2..a9bbe6e471 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -13,9 +13,6 @@ # GNU General Public License for more details. # -config BOARD_ELMEX_PCM205401 - def_bool n - if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index 050b94c4b4..f70b215abc 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ELMEX_PCM205401 -# bool "pcm205401" +config BOARD_ELMEX_PCM205401 + bool "pcm205401" From 24c1f94258d52402494f17f6e34cd489009c01f9 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 15:39:42 +0000 Subject: [PATCH 0130/1463] gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Mike Banon Change-Id: Iad86755952204bb1a56ef341e626b0627a958467 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38868 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/gizmosphere/gizmo2/Kconfig | 4 --- src/mainboard/gizmosphere/gizmo2/Kconfig.name | 4 +-- src/mainboard/gizmosphere/gizmo2/Makefile.inc | 2 ++ src/mainboard/gizmosphere/gizmo2/bootblock.c | 31 +++++++++++++++++ src/mainboard/gizmosphere/gizmo2/romstage.c | 34 ------------------- 5 files changed, 35 insertions(+), 40 deletions(-) create mode 100644 src/mainboard/gizmosphere/gizmo2/bootblock.c delete mode 100644 src/mainboard/gizmosphere/gizmo2/romstage.c diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 685e27190a..47a39b694b 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_GIZMOSPHERE_GIZMO2 - def_bool n - if BOARD_GIZMOSPHERE_GIZMO2 config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig.name b/src/mainboard/gizmosphere/gizmo2/Kconfig.name index 29688e2a34..a3bae57b28 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig.name +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_GIZMOSPHERE_GIZMO2 -# bool"Gizmo2" +config BOARD_GIZMOSPHERE_GIZMO2 + bool "Gizmo2" diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc index 8a24bea452..2a7d26bd6b 100644 --- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/gizmosphere/gizmo2/bootblock.c b/src/mainboard/gizmosphere/gizmo2/bootblock.c new file mode 100644 index 0000000000..312b5cc0a6 --- /dev/null +++ b/src/mainboard/gizmosphere/gizmo2/bootblock.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ +#if 0 + volatile u32 i, val; + + /* LPC clock? Should happen before enable_serial. */ + + /* + * On Larne, after LpcClkDrvSth is set, it needs some time to be stable, + * because of the buffer ICS551M + */ + for (i = 0; i < 200000; i++) + val = inb(0xcd6); +#endif +} diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c deleted file mode 100644 index 6312270712..0000000000 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -void board_BeforeAgesa(struct sysinfo *cb) -{ - /* For serial port option, plug-in card on LPC. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - pm_io_write8(0xd2, 0); -} From ebdf298ec2dd84810a37a4aac154200b2102b394 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:20:08 +0000 Subject: [PATCH 0131/1463] mb/amd/inagua: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I55bf3004c728bb42ee51dfa917c58d97c56502cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38876 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/Kconfig | 4 ---- src/mainboard/amd/inagua/Kconfig.name | 4 ++-- src/mainboard/amd/inagua/Makefile.inc | 2 ++ src/mainboard/amd/inagua/{romstage.c => bootblock.c} | 6 ++---- 4 files changed, 6 insertions(+), 10 deletions(-) rename src/mainboard/amd/inagua/{romstage.c => bootblock.c} (84%) diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index a5ba07e637..e24af4044a 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_INAGUA - def_bool n - if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/inagua/Kconfig.name b/src/mainboard/amd/inagua/Kconfig.name index 1784fe6fd8..668b22a7d7 100644 --- a/src/mainboard/amd/inagua/Kconfig.name +++ b/src/mainboard/amd/inagua/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_INAGUA -# bool"Inagua" +config BOARD_AMD_INAGUA + bool "Inagua" diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc index ba56286636..bf86007cec 100644 --- a/src/mainboard/amd/inagua/Makefile.inc +++ b/src/mainboard/amd/inagua/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/bootblock.c similarity index 84% rename from src/mainboard/amd/inagua/romstage.c rename to src/mainboard/amd/inagua/bootblock.c index 43d9da9b5d..78d8fca8f3 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include +#include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); kbc1100_early_init(0x2e); kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From 2119d0ba4345a19b9db7dc13e36f3fa57f75d234 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 16 Feb 2020 10:01:33 +0100 Subject: [PATCH 0132/1463] treewide: Capitalize 'CMOS' Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi Reviewed-by: Peter Lemenkov Tested-by: build bot (Jenkins) --- Documentation/mainboard/msi/ms7707/ms7707.md | 2 +- Documentation/releases/coreboot-4.6-relnotes.md | 2 +- Makefile.inc | 2 +- payloads/libpayload/drivers/options.c | 8 ++++---- src/Kconfig | 2 +- src/commonlib/include/commonlib/coreboot_tables.h | 12 ++++++------ src/drivers/pc80/rtc/mc146818rtc.c | 4 ++-- src/drivers/pc80/rtc/option.c | 2 +- src/lib/coreboot_table.c | 2 +- src/northbridge/intel/gm45/igd.c | 4 ++-- src/northbridge/intel/i945/early_init.c | 2 +- src/northbridge/intel/pineview/early_init.c | 2 +- src/northbridge/intel/x4x/early_init.c | 4 ++-- src/security/vboot/vbnv.h | 4 ++-- src/security/vboot/vbnv_cmos.c | 6 +++--- src/soc/intel/baytrail/acpi/globalnvs.asl | 4 ++-- src/soc/intel/braswell/acpi/globalnvs.asl | 4 ++-- src/soc/intel/broadwell/acpi/globalnvs.asl | 4 ++-- src/soc/intel/skylake/acpi/globalnvs.asl | 4 ++-- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 4 ++-- src/southbridge/intel/i82371eb/fadt.c | 2 +- src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 4 ++-- src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 4 ++-- src/southbridge/intel/i82801jx/acpi/globalnvs.asl | 4 ++-- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 4 ++-- util/nvramtool/cli/nvramtool.c | 2 +- util/nvramtool/layout.c | 2 +- 27 files changed, 50 insertions(+), 50 deletions(-) diff --git a/Documentation/mainboard/msi/ms7707/ms7707.md b/Documentation/mainboard/msi/ms7707/ms7707.md index 789431872c..c27ff60142 100644 --- a/Documentation/mainboard/msi/ms7707/ms7707.md +++ b/Documentation/mainboard/msi/ms7707/ms7707.md @@ -75,7 +75,7 @@ Put all back in place and restart the board. It might need 1-2 AC power cycles to reinitialize (running at full fan speed - don't panic). * External flashing has been tested with RPi2 without main power connected. 3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html). -* In case of going back to proprietary BIOS create/save cmos settings as early +* In case of going back to proprietary BIOS create/save CMOS settings as early as possible (do not leave BIOS on first start without saving settings). The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state that needs an external flasher to revive. If stuck, reset the Fintek (see diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md index faa3303b4c..4d19ba7fcf 100644 --- a/Documentation/releases/coreboot-4.6-relnotes.md +++ b/Documentation/releases/coreboot-4.6-relnotes.md @@ -164,7 +164,7 @@ Drivers (29 commits) * i2c/hid: Add generic I2C HID driver * i2c/max98927: add i2c driver for Maxim 98927 codec * i2c/wacom_ts: Add support for WCOM touchscreen device driver -* pc80/rtc: Check cmos checksum BEFORE reading cmos value +* pc80/rtc: Check CMOS checksum BEFORE reading CMOS value * regulator: Add driver for handling GPIO-based fixed regulator * storage: Add SD/MMC/eMMC driver based upon depthcharge diff --git a/Makefile.inc b/Makefile.inc index 1f18726e5d..f172005c7f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -293,7 +293,7 @@ $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h endef ####################################################################### -# Parse plaintext cmos defaults into binary format +# Parse plaintext CMOS defaults into binary format # arg1: source file # arg2: binary file name cbfs-files-processor-nvramtool= \ diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 2b0a42e1b7..0bdb8bcff9 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -157,7 +157,7 @@ static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *op struct cb_cmos_entries *cmos_entry; int len = name ? strnlen(name, CB_CMOS_MAX_NAME_LENGTH) : 0; - /* cmos entries are located right after the option table */ + /* CMOS entries are located right after the option table */ cmos_entry = first_cmos_entry(option_table); while (cmos_entry) { if (memcmp((const char*)cmos_entry->name, name, len) == 0) @@ -186,12 +186,12 @@ struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cmos_entry) struct cb_cmos_enums *first_cmos_enum(struct cb_cmos_option_table *option_table) { struct cb_cmos_entries *cmos_entry; - /* cmos entries are located right after the option table. Skip them */ + /* CMOS entries are located right after the option table. Skip them */ cmos_entry = (struct cb_cmos_entries *)((unsigned char *)option_table + option_table->header_length); while (cmos_entry->tag == CB_TAG_OPTION) cmos_entry = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size); - /* cmos enums are located after cmos entries. */ + /* CMOS enums are located after CMOS entries. */ return (struct cb_cmos_enums *)cmos_entry; } @@ -237,7 +237,7 @@ static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table * { int len = strnlen(text, CB_CMOS_MAX_TEXT_LENGTH); - /* cmos enums are located after cmos entries. */ + /* CMOS enums are located after CMOS entries. */ struct cb_cmos_enums *cmos_enum; for ( cmos_enum = first_cmos_enum_of_id(option_table, config_id); cmos_enum; diff --git a/src/Kconfig b/src/Kconfig index f75f94279e..16bc4ab524 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -205,7 +205,7 @@ config INCLUDE_CONFIG_FILE Alignment: 64 bytes Name Offset Type Size - cmos_layout.bin 0x0 cmos layout 1159 + cmos_layout.bin 0x0 CMOS layout 1159 fallback/romstage 0x4c0 stage 339756 fallback/ramstage 0x53440 stage 186664 fallback/payload 0x80dc0 payload 51526 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 68166701b0..213d8210f8 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -431,15 +431,15 @@ struct lb_macs { #define MAX_SERIALNO_LENGTH 32 -/* The following structures are for the cmos definitions table */ -/* cmos header record */ +/* The following structures are for the CMOS definitions table */ +/* CMOS header record */ struct cmos_option_table { uint32_t tag; /* CMOS definitions table type */ uint32_t size; /* size of the entire table */ uint32_t header_length; /* length of header */ }; -/* cmos entry record +/* CMOS entry record * This record is variable length. The name field may be * shorter than CMOS_MAX_NAME_LENGTH. The entry may start * anywhere in the byte, but can not span bytes unless it @@ -459,7 +459,7 @@ struct cmos_entries { }; -/* cmos enumerations record +/* CMOS enumerations record * This record is variable length. The text field may be * shorter than CMOS_MAX_TEXT_LENGTH. */ @@ -473,8 +473,8 @@ struct cmos_enums { variable length int aligned */ }; -/* cmos defaults record - * This record contains default settings for the cmos ram. +/* CMOS defaults record + * This record contains default settings for the CMOS ram. */ struct cmos_defaults { uint32_t tag; /* default type */ diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 23f2db3556..c197d375fb 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -160,7 +160,7 @@ static void cmos_init_vbnv(bool invalid) occurred with !CONFIG_USE_OPTION_TABLE. However, __cmos_init() may clear vbnv data for other internal reasons. For that, always back up the vbnv contents and conditionally save them when __cmos_init() - indicates cmos was cleared. */ + indicates CMOS was cleared. */ read_vbnv_cmos(vbnv); if (__cmos_init(invalid)) @@ -204,7 +204,7 @@ void cmos_check_update_date(void) year = cmos_read(RTC_CLK_YEAR); /* - * TODO: If century is 0xFF, 100% that the cmos is cleared. + * TODO: If century is 0xFF, 100% that the CMOS is cleared. * Other than that, so far rtc_year is the only entry to check * if the date is valid. */ diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index ad77669a8d..bb697dfba1 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -26,7 +26,7 @@ /* * This routine returns the value of the requested bits. - * input bit = bit count from the beginning of the cmos image + * input bit = bit count from the beginning of the CMOS image * length = number of bits to include in the value * ret = a character pointer to where the value is to be returned * returns CB_SUCCESS = successful, cb_err code if an error occurred diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e42cb3bdd2..bd09697618 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -505,7 +505,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) * lb_record... */ memcpy(rec_dest, option_table, option_table->size); - /* Create cmos checksum entry in coreboot table */ + /* Create CMOS checksum entry in coreboot table */ lb_cmos_checksum(head); } else { printk(BIOS_ERR, diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index cfd067e044..28e93b858e 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -153,13 +153,13 @@ void igd_compute_ggc(sysinfo_t *const sysinfo) if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) sysinfo->ggc = 0x0002; else { - /* 4 for 32MB, default if not set in cmos */ + /* 4 for 32MB, default if not set in CMOS */ u8 gfxsize = 4; /* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ get_option(&gfxsize, "gfx_uma_size"); - /* Handle invalid cmos settings */ + /* Handle invalid CMOS settings */ /* Only allow settings between 32MB and 352MB */ gfxsize = MIN(MAX(gfxsize, 4), 12); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1deca3eeba..44d25846c2 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -161,7 +161,7 @@ static void i945_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); - /* vram size from cmos option */ + /* vram size from CMOS option */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) gfxsize = 2; /* 2 for 8MB */ /* make sure no invalid setting is used */ diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index c3cd380dc5..8f925f71d7 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -43,7 +43,7 @@ static void early_graphics_setup(void) pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); - /* vram size from cmos option */ + /* vram size from CMOS option */ if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) reg8 = 0; /* 0 for 8MB */ /* make sure no invalid setting is used */ diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 3520b88deb..fbcfadbd9c 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -56,8 +56,8 @@ void x4x_early_init(void) /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */ + /* Set preallocated IGD size from CMOS */ + u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */ get_option(&gfxsize, "gfx_uma_size"); if (gfxsize > 12) gfxsize = 6; diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index 7d288d5773..12b939986b 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -33,10 +33,10 @@ void vbnv_init(uint8_t *vbnv_copy); void vbnv_reset(uint8_t *vbnv_copy); /* CMOS backend */ -/* Initialize the vbnv cmos backing store. The vbnv_copy pointer is used for +/* Initialize the vbnv CMOS backing store. The vbnv_copy pointer is used for optional temporary storage in the init function. */ void vbnv_init_cmos(uint8_t *vbnv_copy); -/* Return non-zero if cmos power was lost. */ +/* Return non-zero if CMOS power was lost. */ int vbnv_cmos_failed(void); void read_vbnv_cmos(uint8_t *vbnv_copy); void save_vbnv_cmos(const uint8_t *vbnv_copy); diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index 7758ef6198..fe5d6ce922 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -81,13 +81,13 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy) void vbnv_init_cmos(uint8_t *vbnv_copy) { - /* If no cmos failure just defer to the normal read path for checking + /* If no CMOS failure just defer to the normal read path for checking vbnv contents' integrity. */ if (!vbnv_cmos_failed()) return; - /* In the case of cmos failure force the backup. If backup wasn't used - force the vbnv cmos to be reset. */ + /* In the case of CMOS failure force the backup. If backup wasn't used + force the vbnv CMOS to be reset. */ if (!restore_from_backup(vbnv_copy)) { vbnv_reset(vbnv_copy); /* This parallels the vboot_reference implementation. */ diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index f33fcf6ae1..703e20fa8a 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -71,8 +71,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 9bd9afc924..a67117da5f 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -73,8 +73,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 9ceeca59dd..22a22e3ed1 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -63,8 +63,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index b2467f9918..e17b2604cf 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -78,8 +78,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index f7652ee5a5..4b54d61b66 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -138,8 +138,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index cbfb0af2ee..15ab0eec0d 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -80,7 +80,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->flush_stride = 0; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */ + fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ fadt->mon_alrm = 0x0; /* not supported */ fadt->century = 0x0; /* not supported */ /* diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 650b07c2a2..23ba6afdfc 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -132,8 +132,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index c1be85246d..1fc5b74591 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -137,8 +137,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 44aa8e4511..c7354a028b 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -137,8 +137,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ba9f850208..fddfa701af 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -133,8 +133,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option + IPAT, 8, // 0xb9 - IGD panel type CMOS option + ITVF, 8, // 0xba - IGD TV format CMOS option ITVM, 8, // 0xbb - IGD TV minor format option IPSC, 8, // 0xbc - IGD panel scaling IBLC, 8, // 0xbd - IGD BLC config diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 9181800e30..7f3f468984 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -126,7 +126,7 @@ int main(int argc, char *argv[]) if (!nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].found) { cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, NULL); if (cmos_default == NULL) { - fprintf(stderr, "Need a cmos.default in the CBFS image or separate cmos file (-D).\n"); + fprintf(stderr, "Need a cmos.default in the CBFS image or separate CMOS file (-D).\n"); exit(1); } } diff --git a/util/nvramtool/layout.c b/util/nvramtool/layout.c index a340671caa..884a828934 100644 --- a/util/nvramtool/layout.c +++ b/util/nvramtool/layout.c @@ -93,7 +93,7 @@ static cmos_layout_get_fn_t cmos_layout_get_fn = default_cmos_layout_get_fn; /**************************************************************************** * entries_overlap * - * Return 1 if cmos entries 'p' and 'q' overlap. Else return 0. + * Return 1 if CMOS entries 'p' and 'q' overlap. Else return 0. ****************************************************************************/ static inline int entries_overlap(const cmos_entry_t * p, const cmos_entry_t * q) From c44d1e2c7c5a609e7ea3893ddd6baf25ef3f5293 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 2 Oct 2019 13:37:45 -0600 Subject: [PATCH 0133/1463] xcompile: Use GCC wrappers for ar, nm When compiling with GCC, use the special wrappers around ar and nm that provide the path to the plugin they need to understand LTO object files. These wrappers forward all other functionality to the underlying programs, so they should otherwise be equivalent. Change-Id: Ibdae4faabf67bf6a4bb8c38970f6189646ee74b3 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38290 Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/xcompile/xcompile | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index a116407b8b..3203d71899 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -293,12 +293,17 @@ EOF fi # if [ "${TARCH}" = "arm64" ]... cat < Date: Sun, 23 Feb 2020 09:51:07 +0100 Subject: [PATCH 0134/1463] Documentation/project_ideas: Update after 2019 The coverity project is done, for the most part, so drop it. Expand a bit on the scope of the toolchain binary project, and point out that the Ghidra project already has code from GSoC 2019 but could be developed further. Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39086 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber Reviewed-by: Patrick Rudolph --- Documentation/contributing/project_ideas.md | 29 ++++++--------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 90164a2bfa..8271ea91f0 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -27,7 +27,9 @@ which is a bad experience when trying to build coreboot the first time. Provide packages/installers of our compiler toolchain for Linux distros, Windows, Mac OS. For Windows, this should also include the environment -(shell, make, ...). +(shell, make, ...). A student doesn't have to cover _all_ platforms, but +pick a set of systems that match their interest and knowledge and lay +out a plan on how to do this. The scripts to generate these packages should be usable on a Linux host, as that's what we're using for our automated build testing system @@ -131,26 +133,6 @@ their bug reports. ### Mentors * Patrick Georgi -## Make coreboot coverity clean -coreboot and several other of our projects are automatically tested -using Synopsys' free "Coverity Scan" service. While some fare pretty -good, like [em100](https://scan.coverity.com/projects/em100) at 0 known -defects, there are still many open issues in other projects, most notably -[coreboot](https://scan.coverity.com/projects/coreboot) itself (which -is also the largest codebase). - -Not all of the reports are actual issues, but the project benefits a -lot if the list of unhandled reports is down to 0 because that provides -a baseline when future changes reintroduce new issues: it's easier to -triage and handle a list of 5 issues rather than more than 350. - -This project would be going through all reports and handling them -appropriately: Figure out if reports are valid or not and mark them -as such. For valid reports, provide patches to fix the underlying issue. - -### Mentors -* Patrick Georgi - ## Extend Ghidra to support analysis of firmware images [Ghidra](https://ghidra-sre.org) is a recently released cross-platform disassembler and decompiler that is extensible through plugins. Make it @@ -158,6 +140,11 @@ useful for firmware related work: Automatically parse formats (eg. by integrating UEFITool, cbfstool, decompressors), automatically identify 16/32/64bit code on x86/amd64, etc. +This has been done in 2019 with [some neat +features](https://github.com/al3xtjames/ghidra-firmware-utils) being +developed, but it may be possible to expand support for all kinds of firmware +analyses. + ## Learn hardware behavior from I/O and memory access logs [SerialICE](https://www.serialice.com) is a tool to trace the behavior of executable code like firmware images. One result of that is a long log file From 8297fa1e206c7d0a5628661f4ed57f768a676ebe Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 10:37:49 +0100 Subject: [PATCH 0135/1463] util: Remove old reference to ROMCC Change-Id: Ia1a37db8341281102ae8ae9c03f1ce76d8d126eb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39075 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/README.md | 2 -- util/lint/check_lint_tests | 2 +- util/lint/lint-000-license-headers | 2 -- util/lint/lint-014-qualified-types | 2 +- util/lint/lint-extended-015-final-newlines | 2 +- 5 files changed, 3 insertions(+), 7 deletions(-) diff --git a/util/README.md b/util/README.md index 55bcaab637..66438a9ce9 100644 --- a/util/README.md +++ b/util/README.md @@ -86,8 +86,6 @@ can be passed to SPIKE, the RISC-V reference emulator.`Bash` * _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for SiFive's bootrom. `Python3` * __rockchip__ - Generate Rockchip idblock bootloader. `Python2` -* __romcc__ - Compile a C source file generating a binary that does not -implicitly use RAM. `C` * __sconfig__ - coreboot device tree compiler `Lex` `Yacc` * __scripts__ * _config_ - Manipulate options in a .config file from the diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests index 6b1860fdae..6f6942d549 100755 --- a/util/lint/check_lint_tests +++ b/util/lint/check_lint_tests @@ -36,7 +36,7 @@ sed -i "s/for more details./for more details.\n \* You${SPACE}should${SPACE}have git add ${TESTFILE009} #lint-stable-010-asm-syntax -TESTFILE010=src/arch/x86/bootblock_romcc.S +TESTFILE010=src/arch/x86/bootblock_crt0.S sed -i "1s/^/.att${UNDERSCORE}syntax noprefix\n/" ${TESTFILE010} git add ${TESTFILE010} diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 88e15ecca0..48f7b400ca 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -24,8 +24,6 @@ HEADER_EXCLUDED="\ ^util/amdtools/example_input/|\ ^util/cbfstool/lzma/|\ ^util/kconfig/|\ -^util/romcc/tests|\ -^util/romcc/results|\ Kconfig|\ \|\ \|\ diff --git a/util/lint/lint-014-qualified-types b/util/lint/lint-014-qualified-types index 98679ea55e..d447c4bd6d 100755 --- a/util/lint/lint-014-qualified-types +++ b/util/lint/lint-014-qualified-types @@ -17,7 +17,7 @@ LC_ALL=C export LC_ALL INCLUDED_DIRS='^src/\|^util/\|payloads/libpayload\|payloads/coreinfo' -EXCLUDED_DIRS='^src/vendorcode\|^util/romcc\|cbfstool/lzma\|cbfstool/lz4' +EXCLUDED_DIRS='^src/vendorcode\|cbfstool/lzma\|cbfstool/lz4' INCLUDED_FILES='\.[ch]:' # Use git grep if the code is in a git repo, otherwise use grep. diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines index b5a503f3cf..ee573f516f 100755 --- a/util/lint/lint-extended-015-final-newlines +++ b/util/lint/lint-extended-015-final-newlines @@ -18,7 +18,7 @@ LC_ALL=C export LC_ALL PIDS="" INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc' -EXCLUDED_DIRS='src/vendorcode/\|util/romcc/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/' +EXCLUDED_DIRS='src/vendorcode/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/' EXCLUDED_FILES='\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$' # Use git ls-files if the code is in a git repo, otherwise use find. From 32fecd689beb4b50e0b0dca0328b422cfb3a7931 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 10:15:33 +0100 Subject: [PATCH 0136/1463] cpu/Kconfig: Remove old reference to ROMCC Change-Id: I06425d8290a89e72a2420aeb6a9bc4b4acbaf498 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39070 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/Kconfig | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 1ad7ef1b1b..c1b84f9d44 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -27,15 +27,13 @@ config MMX bool help Select MMX in your socket or model Kconfig if your CPU has MMX - streaming SIMD instructions. ROMCC can build more efficient - code if it can spill to MMX registers. + streaming SIMD instructions. config SSE bool help Select SSE in your socket or model Kconfig if your CPU has SSE - streaming SIMD instructions. ROMCC can build more efficient - code if it can spill to SSE (aka XMM) registers. + streaming SIMD instructions. config SSE2 bool From 5f6cfef424d968f9adc20232a33d3599f4dda812 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 10:20:50 +0100 Subject: [PATCH 0137/1463] include/arch/cpu.h: Remove old reference to ROMCC Change-Id: I17d13c53baf16f58e6e2ba45f439c36f7ba28690 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39071 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index c8cf8c76c3..59eb9ad32d 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -261,7 +261,6 @@ static inline struct cpu_info *cpu_info(void) return ci; } -/* romcc is segfaulting in some cases. */ struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ @@ -281,7 +280,6 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) } -/* romcc does not understand regparm. */ #define asmlinkage __attribute__((regparm(0))) /* From 75cd6d2a97a3d5630e74ca099ddb702be143415e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 10:44:08 +0100 Subject: [PATCH 0138/1463] mb/amd/samba: Drop board leftover lippert/hurricane-lx doesn't exist anymore (see Change-Id: I87e3963). Change-Id: I6d1c3a846c5bbb5fdc74178d0cf8a3cdaae1a010 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39076 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/samba/board_info.txt | 8 -------- 1 file changed, 8 deletions(-) delete mode 100644 src/mainboard/amd/samba/board_info.txt diff --git a/src/mainboard/amd/samba/board_info.txt b/src/mainboard/amd/samba/board_info.txt deleted file mode 100644 index d608aba495..0000000000 --- a/src/mainboard/amd/samba/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Category: half -Board name: Samba -Board URL: http://www.amd.com/Documents/40631a_epic_rdk_pb.pdf -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: lippert/hurricane-lx From 9318d6d6251dcc5ae243a377d15d407a066ec46f Mon Sep 17 00:00:00 2001 From: Marx Wang Date: Fri, 7 Feb 2020 16:44:14 +0800 Subject: [PATCH 0139/1463] soc/intel/cannonlake: Add TDC config for CML Add Thermal Design Current (TDC) defaults for CML: 1. TdcEnable 2. TdcPowerLimit BUG=b:148912093 BRANCH=None TEST=build coreboot and Intel FSP with fw_debug enabled, flash image to the device, capture the log from the serial port during boot-up and check TdcEnable and TdcPowerLimit for each domain in captured log Signed-off-by: Marx Wang Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38741 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: John Su Reviewed-by: Angel Pons --- .../intel/cannonlake/include/soc/vr_config.h | 16 +++ src/soc/intel/cannonlake/vr_config.c | 97 +++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 1390b174e1..456db5b48f 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -53,10 +53,18 @@ struct vr_config { /* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */ uint16_t ac_loadline; uint16_t dc_loadline; + + /* Thermal Design Current (TDC) Power Limit will take effect when + this is set to 0 */ + uint8_t tdc_disable; + + /* Thermal Design Current (TDC) Power Limit in 1/8 A units */ + uint16_t tdc_powerlimit; }; #define VR_CFG_AMP(i) (uint16_t)((i) * 4) #define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) +#define VR_CFG_TDC_AMP(i) (uint16_t)((i) * 8) /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, @@ -85,6 +93,14 @@ enum vr_domain { [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ } +#define VR_CFG_ALL_DOMAINS_TDC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_TDC_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_TDC_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_TDC_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_TDC_AMP(gt_sl), \ + } + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 5fadcf4023..bd73d15dd7 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -419,6 +419,96 @@ static uint16_t get_sku_voltagelimit(int domain) return 1520; } +static uint16_t get_sku_tdc_powerlimit(int domain) +{ + const uint16_t tdp = cpu_get_power_max(); + const config_t *cfg = config_of_soc(); + + static uint16_t mch_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_CML_ULT: + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(48); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + const uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22); + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(60); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(80); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25); + + if (tdp >= 65) /* 65W */ + tdc[VR_IA_CORE] = (cfg->cpu_pl2_4_cfg == baseline) ? + VR_CFG_TDC_AMP(117) : + VR_CFG_TDC_AMP(146); + else /* 45W */ + tdc[VR_IA_CORE] = (cfg->cpu_pl2_4_cfg == baseline) ? + VR_CFG_TDC_AMP(86) : + VR_CFG_TDC_AMP(125); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28); + + if (tdp >= 125) /* 125W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(132); + else if (tdp >= 65) /* 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(104); + else /* 35W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(74); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28); + + if (tdp > 35) /* 125W or 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(175); + + return tdc[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + } + + return 0; +} + void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { @@ -463,4 +553,11 @@ void fill_vr_domain_config(void *params, vr_params->DcLoadline[domain] = cfg->dc_loadline; else vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); + + vr_params->TdcEnable[domain] = !cfg->tdc_disable; + + if (cfg->tdc_powerlimit) + vr_params->TdcPowerLimit[domain] = cfg->tdc_powerlimit; + else + vr_params->TdcPowerLimit[domain] = get_sku_tdc_powerlimit(domain); } From e5c1aa69c7208fc1c9a0827e971b4b58340da307 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 23 Feb 2020 23:04:10 +0100 Subject: [PATCH 0140/1463] superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The datasheet uses "SWC" as shortcut for "System Wake-up Controller", thus rename it in the code. Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39095 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Frans Hendriks --- src/superio/aspeed/ast2400/ast2400.h | 2 +- src/superio/aspeed/ast2400/superio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/aspeed/ast2400/ast2400.h b/src/superio/aspeed/ast2400/ast2400.h index d9e4ea1b02..d361c8b9fd 100644 --- a/src/superio/aspeed/ast2400/ast2400.h +++ b/src/superio/aspeed/ast2400/ast2400.h @@ -6,7 +6,7 @@ #define AST2400_SUART1 0x2 /* Com1 */ #define AST2400_SUART2 0x3 /* Com2 */ -#define AST2400_SWAK 0x4 /* System Wake-Up control */ +#define AST2400_SWC 0x4 /* System Wake-Up Control */ #define AST2400_KBC 0x5 /* Keyboard controller */ #define AST2400_GPIO 0x7 /* GPIO */ #define AST2400_SUART3 0xB /* Com3 */ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 0941663e2b..a3d92c22ce 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -75,7 +75,7 @@ static struct device_operations ops = { static struct pnp_info pnp_dev_info[] = { { NULL, AST2400_SUART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, { NULL, AST2400_SUART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, - { NULL, AST2400_SWAK, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 + { NULL, AST2400_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, }, { NULL, AST2400_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, 0xffff, 0xffff, }, From 00b7533629b4b227b182d0edca5ee7275054a03b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 20 Feb 2020 12:09:45 +0530 Subject: [PATCH 0141/1463] soc/intel/common/block: Move smihandler common functions into common code This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/smihandler.c | 12 +----- src/soc/intel/cannonlake/smihandler.c | 43 ++----------------- .../block/include/intelblocks/smihandler.h | 9 ---- src/soc/intel/common/block/smm/smihandler.c | 42 ++++++++++++++---- src/soc/intel/icelake/smihandler.c | 42 ++---------------- src/soc/intel/skylake/smihandler.c | 39 +---------------- src/soc/intel/tigerlake/smihandler.c | 42 ++---------------- 7 files changed, 44 insertions(+), 185 deletions(-) diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 424d66f0d7..e37de92d2a 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,16 +34,6 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) return &em64t100_smm_ops; } -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[32] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4d0b241517..550c92dc6f 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,26 +17,19 @@ #include #include -#include +#include #include #include #include -#include +#include #include #include #include -#include "chip.h" - #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { @@ -85,36 +78,6 @@ void smihandler_soc_at_finalize(void) pch_disable_heci(); } -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index d8520f12c6..06b9e212ad 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -156,15 +156,6 @@ void smihandler_soc_at_finalize(void); */ int smihandler_soc_disable_busmaster(pci_devfn_t dev); -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void); - -/* - * SoC needs to implement the mechanism to know if an illegal attempt - * has been made to write to the BIOS area. - */ -void smihandler_soc_check_illegal_access(uint32_t tco_sts); - /* Mainboard overrides. */ /* Mainboard handler for GPI SMIs */ diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 4677d27943..54f4e41e50 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2017 Intel Corp. + * Copyright (C) 2015-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,6 +44,11 @@ static struct global_nvs_t *gnvs; /* SoC overrides. */ +__weak const struct smm_save_state_ops *get_smm_save_state_ops(void) +{ + return &em64t101_smm_ops; +} + /* Specific SOC SMI handler during ramstage finalize phase */ __weak void smihandler_soc_at_finalize(void) { @@ -55,20 +60,29 @@ __weak int smihandler_soc_disable_busmaster(pci_devfn_t dev) return 1; } -/* SMI handlers that should be serviced in SCI mode too. */ -__weak uint32_t smihandler_soc_get_sci_mask(void) -{ - return 0; /* No valid SCI mask for SMI handler */ -} - /* * Needs to implement the mechanism to know if an illegal attempt * has been made to write to the BIOS area. */ -__weak void smihandler_soc_check_illegal_access( +static void smihandler_soc_check_illegal_access( uint32_t tco_sts) { - return; + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) + && fast_spi_wpd_status())) + return; + + /* + * BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + * + * This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk(BIOS_DEBUG, "Switching back to RO\n"); + fast_spi_enable_wp(); } /* Mainboard overrides. */ @@ -472,6 +486,16 @@ void smihandler_southbridge_espi( mainboard_smi_espi_handler(); } +/* SMI handlers that should be serviced in SCI mode too. */ +static uint32_t smihandler_soc_get_sci_mask(void) +{ + uint32_t sci_mask = + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); + + return sci_mask; +} + void southbridge_smi_handler(void) { int i; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index b7c37d4aa7..5228f5d4a0 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,25 +15,19 @@ #include #include -#include +#include #include #include #include -#include +#include #include #include #include -#include #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { @@ -82,36 +76,6 @@ void smihandler_soc_at_finalize(void) pch_disable_heci(); } -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075f7b..4818c0202e 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,46 +15,9 @@ * GNU General Public License for more details. */ -#include -#include #include #include -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index bf07beadb6..68954eb999 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,25 +15,19 @@ #include #include -#include +#include #include #include #include -#include +#include #include #include #include -#include #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { @@ -82,36 +76,6 @@ void smihandler_soc_at_finalize(void) pch_disable_heci(); } -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, From 7e8998466f6b0cfa410af94da41b18859d6379f2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 17 May 2018 18:28:26 +0530 Subject: [PATCH 0142/1463] soc/intel/common/block: Move cse common functions into block/cse This patch cleans soc/intel/{cnl, icl, tgl} by moving common soc code into common/block/cse. Supported SoC can select existing HECI_DISABLE_USING_SMM option to select common cse code block to make heci function disable using sideband interface during SMM mode at preboot envionment. BUG=b:78109109 TEST=Able to make HECI disable in SMM mode successfully without any hang or errors in CNL, ICL and TGL platform. Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Signed-off-by: Subrata Banik Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133 Reviewed-by: V Sowmya Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/smihandler.c | 40 +----------- src/soc/intel/common/block/cse/Kconfig | 8 +++ src/soc/intel/common/block/cse/Makefile.inc | 1 + src/soc/intel/common/block/cse/disable_heci.c | 62 +++++++++++++++++++ .../common/block/include/intelblocks/cse.h | 2 + src/soc/intel/icelake/smihandler.c | 40 +----------- src/soc/intel/tigerlake/smihandler.c | 40 +----------- 7 files changed, 76 insertions(+), 117 deletions(-) create mode 100644 src/soc/intel/common/block/cse/disable_heci.c diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 550c92dc6f..4be7897f78 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -18,49 +18,11 @@ #include #include #include -#include -#include #include #include #include -#include #include -#define CSME0_FBE 0xf -#define CSME0_BAR 0x0 -#define CSME0_FID 0xb0 - -static void pch_disable_heci(void) -{ - struct pcr_sbi_msg msg = { - .pid = PID_CSME0, - .offset = 0, - .opcode = PCR_WRITE, - .is_posted = false, - .fast_byte_enable = CSME0_FBE, - .bar = CSME0_BAR, - .fid = CSME0_FID - }; - /* Bit 0: Set to make HECI#1 Function disable */ - uint32_t data32 = 1; - uint8_t response; - int status; - - /* unhide p2sb device */ - p2sb_unhide(); - - /* Send SBI command to make HECI#1 function disable */ - status = pcr_execute_sideband_msg(&msg, &data32, &response); - if (status && response) - printk(BIOS_ERR, "Fail to make CSME function disable\n"); - - /* Ensure to Lock SBI interface after this command */ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - /* * Specific SOC SMI handler during ramstage finalize phase * @@ -75,7 +37,7 @@ void smihandler_soc_at_finalize(void) config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) - pch_disable_heci(); + heci_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 321d34ce61..15de0b0536 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -4,3 +4,11 @@ config SOC_INTEL_COMMON_BLOCK_CSE help Driver for communication with Converged Security Engine (CSE) over Host Embedded Controller Interface (HECI) + +config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM + bool + default y if HECI_DISABLE_USING_SMM + select SOC_INTEL_COMMON_BLOCK_P2SB + help + Use this config to include common CSE block to make HECI function + disable in SMM mode diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 376f00f715..90f76d59b0 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c new file mode 100644 index 0000000000..f560a37e9d --- /dev/null +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CSME0_FBE 0xf +#define CSME0_BAR 0x0 +#define CSME0_FID 0xb0 + +/* Disable HECI using Sideband interface communication */ +void heci_disable(void) +{ + struct pcr_sbi_msg msg = { + .pid = PID_CSME0, + .offset = 0, + .opcode = PCR_WRITE, + .is_posted = false, + .fast_byte_enable = CSME0_FBE, + .bar = CSME0_BAR, + .fid = CSME0_FID + }; + /* Bit 0: Set to make HECI#1 Function disable */ + uint32_t data32 = 1; + uint8_t response; + int status; + + /* unhide p2sb device */ + p2sb_unhide(); + + /* Send SBI command to make HECI#1 function disable */ + status = pcr_execute_sideband_msg(&msg, &data32, &response); + if (status || response) + printk(BIOS_ERR, "Fail to make CSME function disable\n"); + + /* Ensure to Lock SBI interface after this command */ + p2sb_disable_sideband_access(); + + /* hide p2sb device */ + p2sb_hide(); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c597a3f46f..59ddc5b5d5 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -97,6 +97,8 @@ int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t * Returns 0 on failure and 1 on success. */ int heci_reset(void); +/* Disable HECI using Sideband interface communication */ +void heci_disable(void); /* Reads config value from a specified offset in the CSE PCI Config space. */ uint32_t me_read_config32(int offset); diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5228f5d4a0..6be7b70338 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -16,49 +16,11 @@ #include #include #include -#include -#include #include #include #include -#include #include -#define CSME0_FBE 0xf -#define CSME0_BAR 0x0 -#define CSME0_FID 0xb0 - -static void pch_disable_heci(void) -{ - struct pcr_sbi_msg msg = { - .pid = PID_CSME0, - .offset = 0, - .opcode = PCR_WRITE, - .is_posted = false, - .fast_byte_enable = CSME0_FBE, - .bar = CSME0_BAR, - .fid = CSME0_FID - }; - /* Bit 0: Set to make HECI#1 Function disable */ - uint32_t data32 = 1; - uint8_t response; - int status; - - /* unhide p2sb device */ - p2sb_unhide(); - - /* Send SBI command to make HECI#1 function disable */ - status = pcr_execute_sideband_msg(&msg, &data32, &response); - if (status && response) - printk(BIOS_ERR, "Fail to make CSME function disable\n"); - - /* Ensure to Lock SBI interface after this command */ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - /* * Specific SOC SMI handler during ramstage finalize phase * @@ -73,7 +35,7 @@ void smihandler_soc_at_finalize(void) config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) - pch_disable_heci(); + heci_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 68954eb999..0e8d345bac 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -16,49 +16,11 @@ #include #include #include -#include -#include #include #include #include -#include #include -#define CSME0_FBE 0xf -#define CSME0_BAR 0x0 -#define CSME0_FID 0xb0 - -static void pch_disable_heci(void) -{ - struct pcr_sbi_msg msg = { - .pid = PID_CSME0, - .offset = 0, - .opcode = PCR_WRITE, - .is_posted = false, - .fast_byte_enable = CSME0_FBE, - .bar = CSME0_BAR, - .fid = CSME0_FID - }; - /* Bit 0: Set to make HECI#1 Function disable */ - uint32_t data32 = 1; - uint8_t response; - int status; - - /* unhide p2sb device */ - p2sb_unhide(); - - /* Send SBI command to make HECI#1 function disable */ - status = pcr_execute_sideband_msg(&msg, &data32, &response); - if (status && response) - printk(BIOS_ERR, "Fail to make CSME function disable\n"); - - /* Ensure to Lock SBI interface after this command */ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - /* * Specific SOC SMI handler during ramstage finalize phase * @@ -73,7 +35,7 @@ void smihandler_soc_at_finalize(void) config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) - pch_disable_heci(); + heci_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { From 3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 12 Feb 2020 16:01:22 +0530 Subject: [PATCH 0143/1463] soc/intel/common: Update Jasper Lake Device IDs Update Jasper Lake CPU, SA and PCH IDs. BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath Signed-off-by: Varshit Pandya Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Wonkyu Kim --- src/include/device/pci_ids.h | 77 +++++++++++-------- src/soc/intel/common/block/cpu/mp_init.c | 1 + src/soc/intel/common/block/cse/cse.c | 5 +- src/soc/intel/common/block/dsp/dsp.c | 2 +- .../intel/common/block/graphics/graphics.c | 3 +- src/soc/intel/common/block/i2c/i2c.c | 12 +-- .../block/include/intelblocks/mp_init.h | 1 + src/soc/intel/common/block/lpc/lpc.c | 3 +- src/soc/intel/common/block/p2sb/p2sb.c | 2 +- src/soc/intel/common/block/pcie/pcie.c | 16 ++-- src/soc/intel/common/block/pmc/pmc.c | 2 +- src/soc/intel/common/block/sata/sata.c | 3 +- src/soc/intel/common/block/scs/mmc.c | 1 + src/soc/intel/common/block/scs/sd.c | 2 +- src/soc/intel/common/block/smbus/smbus.c | 2 +- src/soc/intel/common/block/spi/spi.c | 8 +- src/soc/intel/common/block/sram/sram.c | 2 +- .../common/block/systemagent/systemagent.c | 2 +- src/soc/intel/common/block/uart/uart.c | 6 +- src/soc/intel/common/block/xdci/xdci.c | 1 + src/soc/intel/common/block/xhci/xhci.c | 2 +- .../tigerlake/bootblock/report_platform.c | 9 ++- 22 files changed, 90 insertions(+), 72 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c6602c44e3..47b182577d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2809,8 +2809,6 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_0 0x4b00 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_1 0x4b04 #define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI 0x4b03 @@ -2819,6 +2817,7 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 +#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3014,6 +3013,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 + #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba @@ -3038,14 +3038,15 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4 0x38bb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5 0x38bc -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6 0x38bd -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf + +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1 0x4db8 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2 0x4db9 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3 0x4dba +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4 0x4dbb +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5 0x4dbc +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6 0x4dbd +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7 0x4dbe +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8 0x4dbf #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1 0x4b38 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2 0x4b39 @@ -3089,8 +3090,9 @@ #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3 #define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60 +#define PCI_DEVICE_ID_INTEL_JSP_SATA_1 0x4dd2 +#define PCI_DEVICE_ID_INTEL_JSP_SATA_2 0x4dd3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3106,8 +3108,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 #define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 +#define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3178,12 +3180,13 @@ #define PCI_DEVICE_ID_INTEL_MCC_I2C5 0x4b4c #define PCI_DEVICE_ID_INTEL_MCC_I2C6 0x4b44 #define PCI_DEVICE_ID_INTEL_MCC_I2C7 0x4b45 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3 0x38eb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4 0x38c5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5 0x38c6 + +#define PCI_DEVICE_ID_INTEL_JSP_I2C0 0x4de8 +#define PCI_DEVICE_ID_INTEL_JSP_I2C1 0x4de9 +#define PCI_DEVICE_ID_INTEL_JSP_I2C2 0x4dea +#define PCI_DEVICE_ID_INTEL_JSP_I2C3 0x4deb +#define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5 +#define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -3224,9 +3227,9 @@ #define PCI_DEVICE_ID_INTEL_MCC_UART0 0x4b28 #define PCI_DEVICE_ID_INTEL_MCC_UART1 0x4b29 #define PCI_DEVICE_ID_INTEL_MCC_UART2 0x4b4d -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7 +#define PCI_DEVICE_ID_INTEL_JSP_UART0 0x4da8 +#define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9 +#define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -3273,10 +3276,10 @@ #define PCI_DEVICE_ID_INTEL_MCC_GSPI0 0x4b2a #define PCI_DEVICE_ID_INTEL_MCC_GSPI1 0x4b2b #define PCI_DEVICE_ID_INTEL_MCC_GSPI2 0x4b37 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI 0x38a4 +#define PCI_DEVICE_ID_INTEL_JSP_SPI0 0x4daa +#define PCI_DEVICE_ID_INTEL_JSP_SPI1 0x4dab +#define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb +#define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4 /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3387,7 +3390,8 @@ #define PCI_DEVICE_ID_INTEL_EHL_GT2_2 0x4550 #define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4571 #define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569 +#define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51 +#define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3447,9 +3451,9 @@ #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 +#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3462,8 +3466,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 +#define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3479,8 +3483,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d +#define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3496,8 +3500,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 #define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 +#define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3508,8 +3512,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f +#define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3526,8 +3530,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 +#define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3545,11 +3549,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 #define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 #define PCI_DEVICE_ID_INTEL_MCC_CSE0 0x4b70 #define PCI_DEVICE_ID_INTEL_MCC_CSE1 0x4b71 #define PCI_DEVICE_ID_INTEL_MCC_CSE2 0x4b74 #define PCI_DEVICE_ID_INTEL_MCC_CSE3 0x4b75 +#define PCI_DEVICE_ID_INTEL_JSP_CSE0 0x4de0 +#define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1 +#define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4 +#define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3562,6 +3569,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e +#define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3572,12 +3580,13 @@ #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 #define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 #define PCI_DEVICE_ID_INTEL_MCC_SD 0x4b48 +#define PCI_DEVICE_ID_INTEL_JSP_SD 0x4df8 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 +#define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4 /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 66a358f09a..87cebc0a8f 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -87,6 +87,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0}, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 5877d537f8..48c26f3897 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -791,11 +791,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_CSE0, PCI_DEVICE_ID_INTEL_CMP_H_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE1, PCI_DEVICE_ID_INTEL_MCC_CSE2, PCI_DEVICE_ID_INTEL_MCC_CSE3, + PCI_DEVICE_ID_INTEL_JSP_CSE0, + PCI_DEVICE_ID_INTEL_JSP_CSE1, + PCI_DEVICE_ID_INTEL_JSP_CSE2, + PCI_DEVICE_ID_INTEL_JSP_CSE3, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 78f43a036e..dc21b8e116 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -36,8 +36,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, + PCI_DEVICE_ID_INTEL_JSP_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 6c1436a281..29d6c53e42 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -219,13 +219,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, PCI_DEVICE_ID_INTEL_EHL_GT1_1, PCI_DEVICE_ID_INTEL_EHL_GT2_1, PCI_DEVICE_ID_INTEL_EHL_GT1_2, PCI_DEVICE_ID_INTEL_EHL_GT2_2, PCI_DEVICE_ID_INTEL_EHL_GT1_3, PCI_DEVICE_ID_INTEL_EHL_GT2_3, + PCI_DEVICE_ID_INTEL_JSL_GT1, + PCI_DEVICE_ID_INTEL_JSL_GT2, 0, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index ca854a9720..57dad62b8b 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -249,12 +249,6 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_I2C5, PCI_DEVICE_ID_INTEL_TGP_I2C6, PCI_DEVICE_ID_INTEL_TGP_I2C7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C0, PCI_DEVICE_ID_INTEL_MCC_I2C1, PCI_DEVICE_ID_INTEL_MCC_I2C2, @@ -263,6 +257,12 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_MCC_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C6, PCI_DEVICE_ID_INTEL_MCC_I2C7, + PCI_DEVICE_ID_INTEL_JSP_I2C0, + PCI_DEVICE_ID_INTEL_JSP_I2C1, + PCI_DEVICE_ID_INTEL_JSP_I2C2, + PCI_DEVICE_ID_INTEL_JSP_I2C3, + PCI_DEVICE_ID_INTEL_JSP_I2C4, + PCI_DEVICE_ID_INTEL_JSP_I2C5, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index c0c58afc8d..4c528e0f78 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE_A0 0x906c0 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 #define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index af90df6e6c..3524a8f9e6 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -231,8 +231,6 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, PCI_DEVICE_ID_INTEL_TGP_ESPI_25, PCI_DEVICE_ID_INTEL_TGP_ESPI_26, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_0, PCI_DEVICE_ID_INTEL_MCC_ESPI_1, PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, @@ -241,6 +239,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_MCC_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_3, PCI_DEVICE_ID_INTEL_MCC_ESPI_4, + PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index c968409e0a..5b72e72fe7 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -155,8 +155,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_CMP_H_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, PCI_DEVICE_ID_INTEL_EHL_P2SB, + PCI_DEVICE_ID_INTEL_JSP_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index eab6667b7f..cc20a48d22 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -290,14 +290,6 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3, @@ -305,6 +297,14 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 3a9431baed..ba64063425 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -135,8 +135,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_PMC, PCI_DEVICE_ID_INTEL_CMP_H_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, PCI_DEVICE_ID_INTEL_MCC_PMC, + PCI_DEVICE_ID_INTEL_JSP_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index cb12ad3e2c..5439767c32 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -103,8 +103,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA, PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, + PCI_DEVICE_ID_INTEL_JSP_SATA_1, + PCI_DEVICE_ID_INTEL_JSP_SATA_2, 0 }; diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index 4ff3ac5e7e..bbdde39ed5 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -85,6 +85,7 @@ static struct device_operations dev_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_EMMC, + PCI_DEVICE_ID_INTEL_JSP_EMMC, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 6b360d5cd1..3f036e9847 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -74,8 +74,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, PCI_DEVICE_ID_INTEL_CMP_H_SD, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, PCI_DEVICE_ID_INTEL_MCC_SD, + PCI_DEVICE_ID_INTEL_JSP_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 44b216562b..d647cf839b 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -97,8 +97,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_H_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, PCI_DEVICE_ID_INTEL_MCC_SMBUS, + PCI_DEVICE_ID_INTEL_JSP_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 95981be7eb..51ac697eae 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -93,14 +93,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_GSPI4, PCI_DEVICE_ID_INTEL_TGP_GSPI5, PCI_DEVICE_ID_INTEL_TGP_GSPI6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_MCC_SPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI1, PCI_DEVICE_ID_INTEL_MCC_GSPI2, + PCI_DEVICE_ID_INTEL_JSP_SPI0, + PCI_DEVICE_ID_INTEL_JSP_SPI1, + PCI_DEVICE_ID_INTEL_JSP_SPI2, + PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 6498d4010e..bfbacea740 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -53,8 +53,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_SRAM, PCI_DEVICE_ID_INTEL_CMP_H_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, PCI_DEVICE_ID_INTEL_MCC_SRAM, + PCI_DEVICE_ID_INTEL_JSP_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e660dbf162..02a67884dd 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -400,9 +400,9 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, PCI_DEVICE_ID_INTEL_TGL_ID_Y, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, PCI_DEVICE_ID_INTEL_JSL_EHL, PCI_DEVICE_ID_INTEL_EHL_ID_1, + PCI_DEVICE_ID_INTEL_JSL_ID_1, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 08c0090b21..6f027e7af1 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -281,12 +281,12 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2, PCI_DEVICE_ID_INTEL_MCC_UART0, PCI_DEVICE_ID_INTEL_MCC_UART1, PCI_DEVICE_ID_INTEL_MCC_UART2, + PCI_DEVICE_ID_INTEL_JSP_UART0, + PCI_DEVICE_ID_INTEL_JSP_UART1, + PCI_DEVICE_ID_INTEL_JSP_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 5b70f9d9b8..ff4320197b 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -46,6 +46,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_H_XDCI, PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, PCI_DEVICE_ID_INTEL_MCC_XDCI, + PCI_DEVICE_ID_INTEL_JSP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 4b8a5cc1ec..e4f98eb39b 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -133,8 +133,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_H_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, PCI_DEVICE_ID_INTEL_MCC_XHCI, + PCI_DEVICE_ID_INTEL_JSP_XHCI, 0 }; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index f38e9cf7be..c6a62c3deb 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -38,6 +38,7 @@ static struct { const char *name; } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, + { CPUID_JASPERLAKE_A0, "Jasperlake A0" }, }; static struct { @@ -48,7 +49,7 @@ static struct { { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; @@ -89,8 +90,7 @@ static struct { { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, @@ -106,7 +106,8 @@ static struct { { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" }, + { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, + { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, From 41de2a08ec85df00ff85d87dbee2cb37185e5323 Mon Sep 17 00:00:00 2001 From: Alex Rebert Date: Sat, 22 Feb 2020 18:13:39 -0500 Subject: [PATCH 0144/1463] lib/lzma: Fix out-of-bounds read Fix an out-of-bounds read in the LZMA decoder which happens when the src buffer is too small to contain the 13-byte LZMA header. Change-Id: Id5893e60fc9a48deb83560b7917f5558cd30ef4e Signed-off-by: Alex Rebert Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39085 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/lib/lzma.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/lib/lzma.c b/src/lib/lzma.c index 71c016ebcd..16b6e228fb 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -29,6 +29,11 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn) MAYBE_STATIC_BSS unsigned char scratchpad[15980]; const unsigned char *cp; + if (srcn < data_offset) { + printk(BIOS_WARNING, "lzma: Input too small.\n"); + return 0; + } + memcpy(properties, src, LZMA_PROPERTIES_SIZE); /* The outSize in LZMA stream is a 64bit integer stored in little-endian * (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by From 1f220a9da7cf14b6c776b4323d5bff7b2bca12c5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 20 Feb 2020 14:17:55 +0100 Subject: [PATCH 0145/1463] soc/mediatek: Fix typos in comments Also add missing whitespace. Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39027 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- src/soc/mediatek/common/include/soc/pmic_wrap_common.h | 4 ++-- src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 2 +- src/soc/mediatek/mt8173/dramc_pi_calibration_api.c | 4 ++-- src/soc/mediatek/mt8173/emi.c | 4 ++-- src/soc/mediatek/mt8173/include/soc/pmic_wrap.h | 2 +- src/soc/mediatek/mt8173/mt6391.c | 4 ++-- src/soc/mediatek/mt8183/spm.c | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 0b9f2d3860..bf64164948 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -69,7 +69,7 @@ static inline s32 pwrap_write_nochk(u16 addr, u16 wdata) return pwrap_wacs2(1, addr, wdata, 0, 0); } -/* dewrapper defaule value */ +/* dewrapper default value */ enum { DEFAULT_VALUE_READ_TEST = 0x5aa5, WRITE_TEST_VALUE = 0xa55a @@ -81,7 +81,7 @@ enum { TIMEOUT_WAIT_IDLE_US = 255 }; -/* manual commnd */ +/* manual command */ enum { OP_WR = 0x1, OP_CSH = 0x0, diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 58dce72e94..4fafb049d2 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -450,7 +450,7 @@ static void dramc_set_mrs_value(int channel, int rank, mrs_write(channel, rank, sdram_params->mrs_set.mrs_63, 10); /* MR10 -> ZQ Init, tZQINIT>=1us */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_10, 1); - /* MR3 driving stregth set to max */ + /* MR3 driving strength set to max */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_3, 1); /* MR1 */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_1, 1); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 492238a80c..f6c866bfdb 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -971,9 +971,9 @@ void perbit_window_cal(u32 channel, u8 type) dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2; } - /* 1. delay DQ,find the pass widnow (left boundary) + /* 1. delay DQ,find the pass window (left boundary) * 2. delay DQS find the pass window (right boundary) - * 3. find the best DQ / DQS to satify the middle value + * 3. find the best DQ / DQS to satisfy the middle value * of the overall pass window per bit * 4. set DQS delay to the max per byte, delay DQ to de-skew */ diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index f3ea7614e4..12f08379ea 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -148,7 +148,7 @@ size_t sdram_size(void) 9; /* check if row address */ - /*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ + /* 00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + 13; @@ -159,7 +159,7 @@ size_t sdram_size(void) /* add bank address bit, LPDDR3 is 8 banks =2^3 */ bit_counter += 3; - /*transfor bits to bytes */ + /* transform bits to bytes */ return ((size_t)1 << (bit_counter - 3)); } diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index 3687a2992d..d6c58a5ca0 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -125,7 +125,7 @@ struct mt8173_pwrap_regs { check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148); -/* dewrapper regsister */ +/* dewrapper register */ enum { DEW_EVENT_OUT_EN = DEW_BASE + 0x0, DEW_DIO_EN = DEW_BASE + 0x2, diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 2656d7252d..3f77c8accc 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -201,7 +201,7 @@ static void mt6391_init_setting(void) pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); - /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */ + /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); @@ -359,7 +359,7 @@ static void mt6391_init_setting(void) pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0); - /* 26M clock amplitute adjust */ + /* 26M clock amplitude adjust */ pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11); diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 024fe1c9fc..020da934ab 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -274,7 +274,7 @@ static int spm_load_firmware(enum dyna_load_pcm_index index, offset += copy_size; /* version */ - /* The termintating character should be contained in the spm binary */ + /* The terminating character should be contained in the spm binary */ assert(spm_bin[file_size - 1] == '\0'); assert(offset < file_size); printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset); From 71b1ed8f77649e153af57b9f033e06e49688e123 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 23 Feb 2020 14:58:14 +0100 Subject: [PATCH 0146/1463] mb/supermicro/x11-lga1151-series: fix GPIO reset mapping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset value of 0x0 is only defined for GPD pads. For any other GPIOs this maps to 0x3. On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical to Chipset mapping not found". Set the right value (0x3<<30) for the affected GPIOs. Signed-off-by: Michael Niewöhner Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../variants/x11ssh-tf/include/variant/gpio.h | 4 ++-- .../variants/x11ssm-f/include/variant/gpio.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index 83fb22db7d..3eeef29257 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -114,7 +114,7 @@ static const struct pad_config gpio_table[] = { /* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0xc4000102, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), /* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), @@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = { /* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 6a25128c5a..d27e234ff2 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -125,7 +125,7 @@ static const struct pad_config gpio_table[] = { _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x04000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0xc4000100, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ /* GPIO Group GPP_E */ @@ -167,7 +167,7 @@ static const struct pad_config gpio_table[] = { _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000010), /* GPIO */ /* GPIO Group GPP_G */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ From 4311d9f8528360f0c161d511a016b643b68562f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 23 Feb 2020 22:55:03 +0100 Subject: [PATCH 0147/1463] superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB bridge's index/value interface. They are no one-time config registers so we can't specify a sane value in the devicetree. Thus, drop them to stop coreboot from complaining about the missing entries. Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Felix Held --- src/superio/aspeed/ast2400/superio.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index a3d92c22ce..4867f6ed88 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -82,10 +82,7 @@ static struct pnp_info pnp_dev_info[] = { { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, - { NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 - | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 - | PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC - | PNP_MSCD | PNP_MSCE, }, + { NULL, AST2400_ILPC2AHB, PNP_IRQ0 }, { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, }, }; From 1c8e464e36f380046588476e50a382539aba4e23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 23 Feb 2020 22:51:05 +0100 Subject: [PATCH 0148/1463] mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix PNP warning about missing devicetree entry for SUART1/2 by setting register 0xF0 to a sane (default) value. Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- .../x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 2 ++ .../x11-lga1151-series/variants/x11ssm-f/overridetree.cb | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index f481c77bda..074e61bfbc 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -100,10 +100,12 @@ chip soc/intel/skylake device pnp 2e.2 on # SUART1 io 0x60 = 0x3f8 irq 0x70 = 4 + drq 0xf0 = 0x00 end device pnp 2e.3 on # SUART2 io 0x60 = 0x2f8 irq 0x70 = 3 + drq 0xf0 = 0x00 end device pnp 2e.4 on # SWC io 0x60 = 0xa00 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 0c7c17fffe..76e684ce4d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -87,10 +87,12 @@ chip soc/intel/skylake device pnp 2e.2 on # SUART1 / COM1 (ext) io 0x60 = 0x3f8 irq 0x70 = 4 + drq 0xf0 = 0x00 end device pnp 2e.3 on # SUART2 / COM2 (int) io 0x60 = 0x2f8 irq 0x70 = 3 + drq 0xf0 = 0x00 end device pnp 2e.4 on # SWC io 0x60 = 0xa00 From d2bba86bf7200362d8801fa475bc2c1ff935c8d7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 10:24:23 +0100 Subject: [PATCH 0149/1463] include/stdint.h: Remove old reference to ROMCC Change-Id: I00fdcee177c5d4b5e95bc3d0330fd8934eee2f0a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39072 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- src/include/stdint.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/include/stdint.h b/src/include/stdint.h index b534addfe2..b3e4cb31ec 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -14,10 +14,6 @@ #ifndef STDINT_H #define STDINT_H -/* romcc does not support long long, _Static_assert, or _Bool, so we must ifdef that code out. - Also, GCC can provide its own implementation of stdint.h, so in theory we could use that - instead of this custom file once romcc is no more. */ - /* Fixed width integer types */ typedef signed char int8_t; typedef unsigned char uint8_t; From 68bb307418a691359bddb801a7b7a2c48c5c1297 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 20 Jan 2020 11:42:42 +0800 Subject: [PATCH 0150/1463] soc/mediatek/mt8183: Fix programming error of DRAMC setting 1. The ac timing of 2400Mbps should use diff params with 1600Mbps. 2. Fix the typo error of save shuffle function for DVFS. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I5edac32938def50836f386426e7deb652b80d42d Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38474 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Angel Pons Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/emi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index cf104f8485..07d1cc8ee5 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -325,7 +325,7 @@ static void dramc_ac_timing_optimize(u8 freq_group) { struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91}, [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119}, [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138}, }; @@ -456,9 +456,9 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle) value = read32(src_addr) & 0x7f; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8); + clrsetbits32(dst_addr, 0x7f << 8, value << 8); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16); + clrsetbits32(dst_addr, 0x7f << 16, value << 16); /* DRAMC-exception-2 */ src_addr = (u8 *)&ch[chn].ao.dvfsdll; From e53f8c902535bf979f9549e09d5ecf4b8d922019 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 22 Feb 2020 10:24:09 +0100 Subject: [PATCH 0151/1463] mb/hp: Set CBFS_SIZE Overwrite the default of 1 MiB with the actual bios region size set in the stock IFD. Allows to use payloads like TianoCore without manually touching the CBFS_SIZE. Change-Id: Ic1753a38212cc4961671fea11afe88265e73333b Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39073 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/hp/compaq_8200_elite_sff/Kconfig | 3 +++ src/mainboard/hp/z220_sff_workstation/Kconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index e3b2ebd1f9..6734d5bf2a 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION +config CBFS_SIZE + default 0x2F0000 + config MAINBOARD_DIR string default "hp/compaq_8200_elite_sff" diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index dc288d6940..8f28baf82d 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -30,6 +30,9 @@ config VBOOT_VBNV_OFFSET hex default 0x2a +config CBFS_SIZE + default 0x570000 + config MAINBOARD_DIR string default "hp/z220_sff_workstation" From 646109a4ea12b28ec5c5cd89c4066bb37835605f Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 25 Feb 2020 10:29:15 +0530 Subject: [PATCH 0152/1463] soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to avoid discrepancy between S0 and S3 resume flow. TEST=Able to boot to TianoCore without any hangs and errors, also verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD. Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110 Reviewed-by: Duncan Laurie Reviewed-by: Wonkyu Kim Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/fsp_params.c | 2 +- src/soc/intel/icelake/fsp_params.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a841e..f1b8446f48 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -261,7 +261,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = 1; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 7514be107d..334fac8766 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -140,7 +140,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = 1; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; From 4f81bba18b92a04f147611d5b9ec9453b467f65b Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Tue, 25 Feb 2020 14:36:15 +0530 Subject: [PATCH 0153/1463] vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake Update FSP header file for Tiger Lake platform version 2457. Add SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39117 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Srinidhi N Kaushik Reviewed-by: Nick Vaccaro Reviewed-by: Furquan Shaikh --- .../intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 95 ++++++++++++------- 1 file changed, 62 insertions(+), 33 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 6cf3668fce..24cbd6e9ef 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -187,7 +187,16 @@ typedef struct { /** Offset 0x00CA - Reserved **/ - UINT8 Reserved4[74]; + UINT8 Reserved4[65]; + +/** Offset 0x010B - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x0112 - Reserved +**/ + UINT8 Reserved5[2]; /** Offset 0x0114 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* @@ -223,7 +232,7 @@ typedef struct { /** Offset 0x0185 - Reserved **/ - UINT8 Reserved5[7]; + UINT8 Reserved6[7]; /** Offset 0x018C - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available @@ -245,7 +254,7 @@ typedef struct { /** Offset 0x01D4 - Reserved **/ - UINT8 Reserved6[192]; + UINT8 Reserved7[192]; /** Offset 0x0294 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, @@ -297,7 +306,7 @@ typedef struct { /** Offset 0x02FC - Reserved **/ - UINT8 Reserved7[80]; + UINT8 Reserved8[80]; /** Offset 0x034C - Enable LAN Enable/disable LAN controller. @@ -307,7 +316,7 @@ typedef struct { /** Offset 0x034D - Reserved **/ - UINT8 Reserved8[11]; + UINT8 Reserved9[11]; /** Offset 0x0358 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. @@ -316,7 +325,7 @@ typedef struct { /** Offset 0x0370 - Reserved **/ - UINT8 Reserved9[73]; + UINT8 Reserved10[73]; /** Offset 0x03B9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX @@ -332,7 +341,7 @@ typedef struct { /** Offset 0x03BB - Reserved **/ - UINT8 Reserved10; + UINT8 Reserved11; /** Offset 0x03BC - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. @@ -341,7 +350,7 @@ typedef struct { /** Offset 0x03BE - Reserved **/ - UINT8 Reserved11[38]; + UINT8 Reserved12[38]; /** Offset 0x03E4 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] @@ -364,7 +373,7 @@ typedef struct { /** Offset 0x03E7 - Reserved **/ - UINT8 Reserved12; + UINT8 Reserved13; /** Offset 0x03E8 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) @@ -381,18 +390,18 @@ typedef struct { /** Offset 0x03F0 - Reserved **/ - UINT8 Reserved13[14]; + UINT8 Reserved14[14]; /** Offset 0x03FE - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - DEPRECATED 0: disable, 1: enable + 0: disable, 1: enable $EN_DIS **/ UINT8 Heci3Enabled; /** Offset 0x03FF - Reserved **/ - UINT8 Reserved14[141]; + UINT8 Reserved15[141]; /** Offset 0x048C - CdClock Frequency selection 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: @@ -410,7 +419,7 @@ typedef struct { /** Offset 0x048E - Reserved **/ - UINT8 Reserved15[2]; + UINT8 Reserved16[2]; /** Offset 0x0490 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined @@ -421,7 +430,7 @@ typedef struct { /** Offset 0x04B0 - Reserved **/ - UINT8 Reserved16[30]; + UINT8 Reserved17[30]; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -435,7 +444,7 @@ typedef struct { /** Offset 0x04D2 - Reserved **/ - UINT8 Reserved17[2]; + UINT8 Reserved18[2]; /** Offset 0x04D4 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable @@ -445,7 +454,7 @@ typedef struct { /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved18[11]; + UINT8 Reserved19[11]; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -455,7 +464,7 @@ typedef struct { /** Offset 0x04E7 - Reserved **/ - UINT8 Reserved19[194]; + UINT8 Reserved20[194]; /** Offset 0x05A9 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -466,7 +475,7 @@ typedef struct { /** Offset 0x05AA - Reserved **/ - UINT8 Reserved20[60]; + UINT8 Reserved21[60]; /** Offset 0x05E6 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -476,7 +485,7 @@ typedef struct { /** Offset 0x05E7 - Reserved **/ - UINT8 Reserved21[36]; + UINT8 Reserved22[36]; /** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -485,7 +494,7 @@ typedef struct { /** Offset 0x060C - Reserved **/ - UINT8 Reserved22[2]; + UINT8 Reserved23[2]; /** Offset 0x060E - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -509,7 +518,7 @@ typedef struct { /** Offset 0x061C - Reserved **/ - UINT8 Reserved23[2]; + UINT8 Reserved24[2]; /** Offset 0x061E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -520,7 +529,7 @@ typedef struct { /** Offset 0x061F - Reserved **/ - UINT8 Reserved24[75]; + UINT8 Reserved25[75]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -534,7 +543,7 @@ typedef struct { /** Offset 0x069A - Reserved **/ - UINT8 Reserved25[168]; + UINT8 Reserved26[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. @@ -543,7 +552,7 @@ typedef struct { /** Offset 0x075A - Reserved **/ - UINT8 Reserved26[86]; + UINT8 Reserved27[86]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -564,7 +573,7 @@ typedef struct { /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved27[98]; + UINT8 Reserved28[98]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -574,7 +583,7 @@ typedef struct { /** Offset 0x085B - Reserved **/ - UINT8 Reserved28[50]; + UINT8 Reserved29[50]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -583,7 +592,7 @@ typedef struct { /** Offset 0x0895 - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved30; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -592,7 +601,7 @@ typedef struct { /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved30[72]; + UINT8 Reserved31[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -606,7 +615,27 @@ typedef struct { /** Offset 0x0908 - Reserved **/ - UINT8 Reserved31[456]; + UINT8 Reserved32[16]; + +/** Offset 0x0918 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x0919 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x091A - Reserved +**/ + UINT8 Reserved33[438]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -614,7 +643,7 @@ typedef struct { /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved32[101]; + UINT8 Reserved34[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -632,7 +661,7 @@ typedef struct { /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved33[264]; + UINT8 Reserved35[264]; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -646,7 +675,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved34[269]; + UINT8 Reserved36[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -654,7 +683,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved35[80]; + UINT8 Reserved37[80]; } FSP_S_CONFIG; /** Fsp S UPD Configuration From 71090c6063fd73b7390149b7234d4070cc904855 Mon Sep 17 00:00:00 2001 From: Jeff Chase Date: Mon, 24 Feb 2020 18:43:23 -0500 Subject: [PATCH 0154/1463] mb/google/fizz: allow 8 bit sku ids Change-Id: I663678a4c572fe80298f7388870d5cd403122b98 Signed-off-by: Jeff Chase Reviewed-on: https://review.coreboot.org/c/coreboot/+/39109 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/mainboard/google/fizz/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 939778630c..89795f5eb3 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -184,7 +184,7 @@ static uint8_t board_oem_id(void) const char *smbios_system_sku(void) { - static char sku_str[5]; /* sku{0..7} */ + static char sku_str[7]; /* sku{0..255} */ snprintf(sku_str, sizeof(sku_str), "sku%d", board_oem_id()); From 741dec4681482bb64646fbbcc47afd8dd48ed611 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 26 Feb 2020 01:30:03 +0530 Subject: [PATCH 0155/1463] mb/google/dedede: Enable host bridge device Change-Id: Ie47265527b2b81748f4f3ad744d35cb81af17b80 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39122 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Karthik Ramasubramanian Reviewed-by: V Sowmya Reviewed-by: Subrata Banik --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c17620b3e7..346a3096b6 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -109,7 +109,7 @@ chip soc/intel/tigerlake }" device domain 0 on - device pci 00.0 off end # Host Bridge + device pci 00.0 on end # Host Bridge device pci 02.0 off end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device device pci 05.0 off end # IPU From dfd3f211740be4cf0d234bf4621ac384758a24ce Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 3 May 2019 23:01:13 +0200 Subject: [PATCH 0156/1463] crossgcc: Upgrade GCC to 9.2.0 nds32 and GNAT bad constant patches are integrated in upstream so we don't need them anymore. Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32564 Reviewed-by: Paul Menzel Reviewed-by: Jett Rink Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/crossgcc/buildgcc | 2 +- .../patches/gcc-8.3.0_gnat-bad_constant.patch | 150 - .../patches/gcc-8.3.0_nds32_ite.patch | 21019 ---------------- ...ch => gcc-9.2.0_ada-musl_workaround.patch} | 0 ...-8.3.0_gnat.patch => gcc-9.2.0_gnat.patch} | 0 ....0_libgcc.patch => gcc-9.2.0_libgcc.patch} | 0 util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum | 1 - util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum | 1 + util/xcompile/xcompile | 4 +- 9 files changed, 3 insertions(+), 21174 deletions(-) delete mode 100644 util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch delete mode 100644 util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch rename util/crossgcc/patches/{gcc-8.3.0_ada-musl_workaround.patch => gcc-9.2.0_ada-musl_workaround.patch} (100%) rename util/crossgcc/patches/{gcc-8.3.0_gnat.patch => gcc-9.2.0_gnat.patch} (100%) rename util/crossgcc/patches/{gcc-8.3.0_libgcc.patch => gcc-9.2.0_libgcc.patch} (100%) delete mode 100644 util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum create mode 100644 util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 150e616652..9920799796 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -50,7 +50,7 @@ THREADS=1 GMP_VERSION=6.1.2 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 -GCC_VERSION=8.3.0 +GCC_VERSION=9.2.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 diff --git a/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch b/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch deleted file mode 100644 index e98f933a13..0000000000 --- a/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch +++ /dev/null @@ -1,150 +0,0 @@ -commit b6f742f96c62bab0582021455328ae3be58e16d3 -Author: pmderodat -Date: Fri May 25 09:05:10 2018 +0000 - - [Ada] Remove "constant" attribute on Osint.Unknown_Attributes - - 2018-05-25 Arnaud Charlet - - gcc/ada/ - - * exp_aggr.adb (Convert_To_Positional): Bump default for - Max_Others_Replicate to 32. Update comments. - * osint.ads (Unknown_Attributes): No longer pretend this is a constant. - (No_File_Info_Cache): Initialize separately. - * osint.adb (No_File_Info_Cache): Update initializer. - - git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260739 138bc75d-0d04-0410-961f-82ee72b054a4 - -diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog -index e4127e472aa..d56240b7b82 100644 ---- a/gcc/ada/ChangeLog -+++ b/gcc/ada/ChangeLog -@@ -188,6 +188,14 @@ - an allocator if the type is an unconstrained record type with default - discriminant. - -+2018-05-25 Arnaud Charlet -+ -+ * exp_aggr.adb (Convert_To_Positional): Bump default for -+ Max_Others_Replicate to 32. Update comments. -+ * osint.ads (Unknown_Attributes): No longer pretend this is a constant. -+ (No_File_Info_Cache): Initialize separately. -+ * osint.adb (No_File_Info_Cache): Update initializer. -+ - 2018-05-04 John Marino - - PR ada/85635 -diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb -index f723c1b4d99..ff5210eb4e4 100644 ---- a/gcc/ada/exp_aggr.adb -+++ b/gcc/ada/exp_aggr.adb -@@ -284,14 +284,14 @@ package body Exp_Aggr is - - procedure Convert_To_Positional - (N : Node_Id; -- Max_Others_Replicate : Nat := 5; -+ Max_Others_Replicate : Nat := 32; - Handle_Bit_Packed : Boolean := False); - -- If possible, convert named notation to positional notation. This - -- conversion is possible only in some static cases. If the conversion is - -- possible, then N is rewritten with the analyzed converted aggregate. - -- The parameter Max_Others_Replicate controls the maximum number of - -- values corresponding to an others choice that will be converted to -- -- positional notation (the default of 5 is the normal limit, and reflects -+ -- positional notation (the default of 32 is the normal limit, and reflects - -- the fact that normally the loop is better than a lot of separate - -- assignments). Note that this limit gets overridden in any case if - -- either of the restrictions No_Elaboration_Code or No_Implicit_Loops is -@@ -301,11 +301,6 @@ package body Exp_Aggr is - -- Packed_Array_Aggregate_Handled, we set this parameter to True, since - -- these are cases we handle in there. - -- -- It would seem useful to have a higher default for Max_Others_Replicate, -- -- but aggregates in the compiler make this impossible: the compiler -- -- bootstrap fails if Max_Others_Replicate is greater than 25. This -- -- is unexpected ??? -- - procedure Expand_Array_Aggregate (N : Node_Id); - -- This is the top-level routine to perform array aggregate expansion. - -- N is the N_Aggregate node to be expanded. -@@ -4292,7 +4287,7 @@ package body Exp_Aggr is - - procedure Convert_To_Positional - (N : Node_Id; -- Max_Others_Replicate : Nat := 5; -+ Max_Others_Replicate : Nat := 32; - Handle_Bit_Packed : Boolean := False) - is - Typ : constant Entity_Id := Etype (N); -diff --git a/gcc/ada/osint.adb b/gcc/ada/osint.adb -index 0c23761b6dc..896fbc7ee37 100644 ---- a/gcc/ada/osint.adb -+++ b/gcc/ada/osint.adb -@@ -250,8 +250,7 @@ package body Osint is - Attr : aliased File_Attributes; - end record; - -- No_File_Info_Cache : constant File_Info_Cache := -- (No_File, Unknown_Attributes); -+ No_File_Info_Cache : constant File_Info_Cache := (No_File, (others => 0)); - - package File_Name_Hash_Table is new GNAT.HTable.Simple_HTable ( - Header_Num => File_Hash_Num, -diff --git a/gcc/ada/osint.ads b/gcc/ada/osint.ads -index 65a87fe4ce3..6c75b521456 100644 ---- a/gcc/ada/osint.ads -+++ b/gcc/ada/osint.ads -@@ -255,10 +255,26 @@ package Osint is - -- from the disk and then cached in the File_Attributes parameter (possibly - -- along with other values). - -- type File_Attributes is private; -- Unknown_Attributes : constant File_Attributes; -+ File_Attributes_Size : constant Natural := 32; -+ -- This should be big enough to fit a "struct file_attributes" on any -+ -- system. It doesn't cause any malfunction if it is too big (which avoids -+ -- the need for either mapping the struct exactly or importing the sizeof -+ -- from C, which would result in dynamic code). However, it does waste -+ -- space (e.g. when a component of this type appears in a record, if it is -+ -- unnecessarily large). Note: for runtime units, use System.OS_Constants. -+ -- SIZEOF_struct_file_attributes instead, which has the exact value. -+ -+ type File_Attributes is -+ array (1 .. File_Attributes_Size) -+ of System.Storage_Elements.Storage_Element; -+ for File_Attributes'Alignment use Standard'Maximum_Alignment; -+ -+ Unknown_Attributes : File_Attributes; - -- A cache for various attributes for a file (length, accessibility,...) -- -- This must be initialized to Unknown_Attributes prior to the first call. -+ -- Will be initialized properly at elaboration (for efficiency later on, -+ -- avoid function calls every time we want to reset the attributes) prior -+ -- to the first usage. We cannot make it constant since the compiler may -+ -- put it in a read-only section. - - function Is_Directory - (Name : C_File_Name; -@@ -754,22 +770,4 @@ private - -- detected, the file being written is deleted, and a fatal error is - -- signalled. - -- File_Attributes_Size : constant Natural := 32; -- -- This should be big enough to fit a "struct file_attributes" on any -- -- system. It doesn't cause any malfunction if it is too big (which avoids -- -- the need for either mapping the struct exactly or importing the sizeof -- -- from C, which would result in dynamic code). However, it does waste -- -- space (e.g. when a component of this type appears in a record, if it is -- -- unnecessarily large). Note: for runtime units, use System.OS_Constants. -- -- SIZEOF_struct_file_attributes instead, which has the exact value. -- -- type File_Attributes is -- array (1 .. File_Attributes_Size) -- of System.Storage_Elements.Storage_Element; -- for File_Attributes'Alignment use Standard'Maximum_Alignment; -- -- Unknown_Attributes : constant File_Attributes := (others => 0); -- -- Will be initialized properly at elaboration (for efficiency later on, -- -- avoid function calls every time we want to reset the attributes). -- - end Osint; diff --git a/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch b/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch deleted file mode 100644 index 2f0780be7f..0000000000 --- a/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch +++ /dev/null @@ -1,21019 +0,0 @@ -diff -urN gcc-8.2.0.orig/gcc/common/config/nds32/nds32-common.c gcc-8.2.0/gcc/common/config/nds32/nds32-common.c ---- gcc-8.2.0.orig/gcc/common/config/nds32/nds32-common.c 2018-04-06 07:51:33.000000000 +0200 -+++ gcc-8.2.0/gcc/common/config/nds32/nds32-common.c 2019-01-25 15:38:32.817242625 +0100 -@@ -53,6 +53,16 @@ - - return true; - -+ case OPT_misr_secure_: -+ /* Check the valid security level: 0 1 2 3. */ -+ if (value < 0 || value > 3) -+ { -+ error_at (loc, "for the option -misr-secure=X, the valid X " -+ "must be: 0, 1, 2, or 3"); -+ return false; -+ } -+ return true; -+ - case OPT_mcache_block_size_: - /* Check valid value: 4 8 16 32 64 128 256 512. */ - if (exact_log2 (value) < 2 || exact_log2 (value) > 9) -@@ -74,12 +84,19 @@ - /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ - static const struct default_options nds32_option_optimization_table[] = - { -+#if TARGET_LINUX_ABI == 0 -+ /* Disable -fdelete-null-pointer-checks by default in ELF toolchain. */ -+ { OPT_LEVELS_ALL, OPT_fdelete_null_pointer_checks, -+ NULL, 0 }, -+#endif - /* Enable -fsched-pressure by default at -O1 and above. */ - { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 }, - /* Enable -fomit-frame-pointer by default at all optimization levels. */ - { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 1 }, - /* Enable -mrelax-hint by default at all optimization levels. */ - { OPT_LEVELS_ALL, OPT_mrelax_hint, NULL, 1 }, -+ /* Enalbe -malways-align by default at -O1 and above, but not -Os or -Og. */ -+ { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_malways_align, NULL, 1 }, - /* Enable -mv3push by default at -Os, but it is useless under V2 ISA. */ - { OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 }, - -@@ -87,6 +104,19 @@ - }; - - /* ------------------------------------------------------------------------ */ -+ -+/* Implement TARGET_EXCEPT_UNWIND_INFO. */ -+static enum unwind_info_type -+nds32_except_unwind_info (struct gcc_options *opts ATTRIBUTE_UNUSED) -+{ -+ if (TARGET_LINUX_ABI) -+ return UI_DWARF2; -+ -+ return UI_SJLJ; -+} -+ -+/* ------------------------------------------------------------------------ */ -+ - - /* Run-time Target Specification. */ - -@@ -103,6 +133,7 @@ - TARGET_EXT_PERF : Generate performance extention instrcution. - TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution. - TARGET_EXT_STRING : Generate string extention instrcution. -+ TARGET_HW_ABS : Generate hardware abs instruction. - TARGET_CMOV : Generate conditional move instruction. */ - #undef TARGET_DEFAULT_TARGET_FLAGS - #define TARGET_DEFAULT_TARGET_FLAGS \ -@@ -113,6 +144,7 @@ - | MASK_EXT_PERF \ - | MASK_EXT_PERF2 \ - | MASK_EXT_STRING \ -+ | MASK_HW_ABS \ - | MASK_CMOV) - - #undef TARGET_HANDLE_OPTION -@@ -125,7 +157,7 @@ - /* Defining the Output Assembler Language. */ - - #undef TARGET_EXCEPT_UNWIND_INFO --#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info -+#define TARGET_EXCEPT_UNWIND_INFO nds32_except_unwind_info - - /* ------------------------------------------------------------------------ */ - -diff -urN gcc-8.2.0.orig/gcc/config/nds32/constants.md gcc-8.2.0/gcc/config/nds32/constants.md ---- gcc-8.2.0.orig/gcc/config/nds32/constants.md 2018-04-22 09:46:39.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/constants.md 2019-01-25 15:38:32.821242637 +0100 -@@ -23,6 +23,7 @@ - (define_constants - [(R8_REGNUM 8) - (TA_REGNUM 15) -+ (TP_REGNUM 25) - (FP_REGNUM 28) - (GP_REGNUM 29) - (LP_REGNUM 30) -@@ -49,6 +50,16 @@ - UNSPEC_FFB - UNSPEC_FFMISM - UNSPEC_FLMISM -+ UNSPEC_KDMBB -+ UNSPEC_KDMBT -+ UNSPEC_KDMTB -+ UNSPEC_KDMTT -+ UNSPEC_KHMBB -+ UNSPEC_KHMBT -+ UNSPEC_KHMTB -+ UNSPEC_KHMTT -+ UNSPEC_KSLRAW -+ UNSPEC_KSLRAWU - UNSPEC_SVA - UNSPEC_SVS - UNSPEC_WSBH -@@ -62,6 +73,29 @@ - UNSPEC_UASTORE_HW - UNSPEC_UASTORE_W - UNSPEC_UASTORE_DW -+ UNSPEC_GOTINIT -+ UNSPEC_GOT -+ UNSPEC_GOTOFF -+ UNSPEC_PLT -+ UNSPEC_TLSGD -+ UNSPEC_TLSLD -+ UNSPEC_TLSIE -+ UNSPEC_TLSLE -+ UNSPEC_ROUND -+ UNSPEC_VEC_COMPARE -+ UNSPEC_KHM -+ UNSPEC_KHMX -+ UNSPEC_CLIP_OV -+ UNSPEC_CLIPS_OV -+ UNSPEC_BITREV -+ UNSPEC_KABS -+ UNSPEC_LOOP_END -+ UNSPEC_TLS_DESC -+ UNSPEC_TLS_IE -+ UNSPEC_ADD32 -+ UNSPEC_ICT -+ UNSPEC_KADDH -+ UNSPEC_KSUBH - ]) - - ;; The unspec_volatile operation index. -@@ -135,10 +169,14 @@ - UNSPEC_VOLATILE_SET_TRIG_EDGE - UNSPEC_VOLATILE_GET_TRIG_TYPE - UNSPEC_VOLATILE_RELAX_GROUP -+ UNSPEC_VOLATILE_OMIT_FP_BEGIN -+ UNSPEC_VOLATILE_OMIT_FP_END - UNSPEC_VOLATILE_POP25_RETURN - UNSPEC_VOLATILE_UNALIGNED_FEATURE - UNSPEC_VOLATILE_ENABLE_UNALIGNED - UNSPEC_VOLATILE_DISABLE_UNALIGNED -+ UNSPEC_VOLATILE_RDOV -+ UNSPEC_VOLATILE_CLROV - ]) - - ;; ------------------------------------------------------------------------ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/constraints.md gcc-8.2.0/gcc/config/nds32/constraints.md ---- gcc-8.2.0.orig/gcc/config/nds32/constraints.md 2018-04-06 07:51:33.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/constraints.md 2019-01-25 15:38:32.821242637 +0100 -@@ -127,6 +127,11 @@ - (and (match_code "const_int") - (match_test "IN_RANGE (ival, -31, 0)"))) - -+(define_constraint "Iu06" -+ "Unsigned immediate 6-bit value" -+ (and (match_code "const_int") -+ (match_test "ival < (1 << 6) && ival >= 0"))) -+ - ;; Ip05 is special and dedicated for v3 movpi45 instruction. - ;; movpi45 has imm5u field but the range is 16 ~ 47. - (define_constraint "Ip05" -@@ -136,10 +141,10 @@ - && ival >= (0 + 16) - && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) - --(define_constraint "Iu06" -+(define_constraint "IU06" - "Unsigned immediate 6-bit value constraint for addri36.sp instruction" - (and (match_code "const_int") -- (match_test "ival < (1 << 6) -+ (match_test "ival < (1 << 8) - && ival >= 0 - && (ival % 4 == 0) - && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) -@@ -302,6 +307,25 @@ - (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M) - && (IN_RANGE (exact_log2 (ival + 1), 1, 8))"))) - -+(define_constraint "CVp5" -+ "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47" -+ (and (match_code "const_vector") -+ (match_test "nds32_valid_CVp5_p (op)"))) -+ -+(define_constraint "CVs5" -+ "Signed immediate 5-bit value" -+ (and (match_code "const_vector") -+ (match_test "nds32_valid_CVs5_p (op)"))) -+ -+(define_constraint "CVs2" -+ "Signed immediate 20-bit value" -+ (and (match_code "const_vector") -+ (match_test "nds32_valid_CVs2_p (op)"))) -+ -+(define_constraint "CVhi" -+ "The immediate value that can be simply set high 20-bit" -+ (and (match_code "const_vector") -+ (match_test "nds32_valid_CVhi_p (op)"))) - - (define_memory_constraint "U33" - "Memory constraint for 333 format" -@@ -349,4 +373,9 @@ - (match_test "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) - && nds32_float_mem_operand_p (op)"))) - -+(define_constraint "S" -+ "@internal -+ A constant call address." -+ (match_operand 0 "nds32_symbolic_operand")) -+ - ;; ------------------------------------------------------------------------ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/elf.h gcc-8.2.0/gcc/config/nds32/elf.h ---- gcc-8.2.0.orig/gcc/config/nds32/elf.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/elf.h 2019-01-25 15:38:32.821242637 +0100 -@@ -0,0 +1,81 @@ -+/* Definitions of target machine of Andes NDS32 cpu for GNU compiler -+ Copyright (C) 2012-2014 Free Software Foundation, Inc. -+ Contributed by Andes Technology Corporation. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+/* ------------------------------------------------------------------------ */ -+ -+#define TARGET_LINUX_ABI 0 -+ -+/* In the configure stage we may use options --enable-default-relax, -+ --enable-Os-default-ifc and --enable-Os-default-ex9. They effect -+ the default spec of passing --relax, --mifc, and --mex9 to linker. -+ We use NDS32_RELAX_SPEC, NDS32_IFC_SPEC, and NDS32_EX9_SPEC -+ so that we can customize them conveniently. */ -+#define LINK_SPEC \ -+ " %{G*}" \ -+ " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ -+ " %{shared:-shared}" \ -+ NDS32_RELAX_SPEC -+ -+#define LIB_SPEC \ -+ " -lc -lgloss" -+ -+#define LIBGCC_SPEC \ -+ " -lgcc" -+ -+/* The option -mno-ctor-dtor can disable constructor/destructor feature -+ by applying different crt stuff. In the convention, crt0.o is the -+ startup file without constructor/destructor; -+ crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the -+ startup files with constructor/destructor. -+ Note that crt0.o, crt1.o, crti.o, and crtn.o are provided -+ by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are -+ currently provided by GCC for nds32 target. -+ -+ For nds32 target so far: -+ If -mno-ctor-dtor, we are going to link -+ "crt0.o [user objects]". -+ If -mctor-dtor, we are going to link -+ "crt1.o crtbegin1.o [user objects] crtend1.o". -+ -+ Note that the TARGET_DEFAULT_CTOR_DTOR would effect the -+ default behavior. Check gcc/config.gcc for more information. */ -+#ifdef TARGET_DEFAULT_CTOR_DTOR -+ #define STARTFILE_SPEC \ -+ " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ -+ " %{!mno-ctor-dtor:crtbegin1.o%s}" \ -+ " %{mcrt-arg:crtarg.o%s}" -+ #define ENDFILE_SPEC \ -+ " %{!mno-ctor-dtor:crtend1.o%s}" -+#else -+ #define STARTFILE_SPEC \ -+ " %{mctor-dtor|coverage:crt1.o%s;:crt0.o%s}" \ -+ " %{mctor-dtor|coverage:crtbegin1.o%s}" \ -+ " %{mcrt-arg:crtarg.o%s}" -+ #define ENDFILE_SPEC \ -+ " %{mctor-dtor|coverage:crtend1.o%s}" -+#endif -+ -+#define STARTFILE_CXX_SPEC \ -+ " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ -+ " %{!mno-ctor-dtor:crtbegin1.o%s}" \ -+ " %{mcrt-arg:crtarg.o%s}" -+#define ENDFILE_CXX_SPEC \ -+ " %{!mno-ctor-dtor:crtend1.o%s}" -diff -urN gcc-8.2.0.orig/gcc/config/nds32/iterators.md gcc-8.2.0/gcc/config/nds32/iterators.md ---- gcc-8.2.0.orig/gcc/config/nds32/iterators.md 2018-04-06 07:51:33.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/iterators.md 2019-01-25 15:38:32.821242637 +0100 -@@ -68,6 +68,28 @@ - ;; shifts - (define_code_iterator shift_rotate [ashift ashiftrt lshiftrt rotatert]) - -+(define_code_iterator shifts [ashift ashiftrt lshiftrt]) -+ -+(define_code_iterator shiftrt [ashiftrt lshiftrt]) -+ -+(define_code_iterator sat_plus [ss_plus us_plus]) -+ -+(define_code_iterator all_plus [plus ss_plus us_plus]) -+ -+(define_code_iterator sat_minus [ss_minus us_minus]) -+ -+(define_code_iterator all_minus [minus ss_minus us_minus]) -+ -+(define_code_iterator plus_minus [plus minus]) -+ -+(define_code_iterator extend [sign_extend zero_extend]) -+ -+(define_code_iterator sumax [smax umax]) -+ -+(define_code_iterator sumin [smin umin]) -+ -+(define_code_iterator sumin_max [smax umax smin umin]) -+ - ;;---------------------------------------------------------------------------- - ;; Code attributes. - ;;---------------------------------------------------------------------------- -@@ -76,5 +98,23 @@ - (define_code_attr shift - [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr") (rotatert "rotr")]) - -+(define_code_attr su -+ [(ashiftrt "") (lshiftrt "u") (sign_extend "s") (zero_extend "u")]) -+ -+(define_code_attr zs -+ [(sign_extend "s") (zero_extend "z")]) -+ -+(define_code_attr uk -+ [(plus "") (ss_plus "k") (us_plus "uk") -+ (minus "") (ss_minus "k") (us_minus "uk")]) -+ -+(define_code_attr opcode -+ [(plus "add") (minus "sub") (smax "smax") (umax "umax") (smin "smin") (umin "umin")]) -+ -+(define_code_attr add_rsub -+ [(plus "a") (minus "rs")]) -+ -+(define_code_attr add_sub -+ [(plus "a") (minus "s")]) - - ;;---------------------------------------------------------------------------- -diff -urN gcc-8.2.0.orig/gcc/config/nds32/linux.h gcc-8.2.0/gcc/config/nds32/linux.h ---- gcc-8.2.0.orig/gcc/config/nds32/linux.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/linux.h 2019-01-25 15:38:32.821242637 +0100 -@@ -0,0 +1,86 @@ -+/* Definitions of target machine of Andes NDS32 cpu for GNU compiler -+ Copyright (C) 2012-2014 Free Software Foundation, Inc. -+ Contributed by Andes Technology Corporation. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+/* ------------------------------------------------------------------------ */ -+ -+#define TARGET_LINUX_ABI 1 -+ -+#undef SIZE_TYPE -+#define SIZE_TYPE "unsigned int" -+ -+#undef PTRDIFF_TYPE -+#define PTRDIFF_TYPE "int" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do \ -+ { \ -+ GNU_USER_TARGET_OS_CPP_BUILTINS(); \ -+ } \ -+ while (0) -+ -+#ifdef TARGET_BIG_ENDIAN_DEFAULT -+#define LD_SO_ENDIAN_SPEC "%{mlittle-endian:le}%{!mlittle-endian:be}" -+#else -+#define LD_SO_ENDIAN_SPEC "%{mbig-endian:be}%{!mbig-endian:le}" -+#endif -+ -+/* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI, -+ 1 means hard ABI and using full floating-point instruction, -+ 2 means hard ABI and only using single-precision floating-point -+ instruction */ -+#if TARGET_ARCH_DEFAULT -+#define LD_SO_ABI_SPEC "%{!mabi=2:f}" -+#else -+#define LD_SO_ABI_SPEC "%{mabi=2fp+:f}" -+#endif -+ -+#define GLIBC_DYNAMIC_LINKER \ -+ "/lib/ld-linux-nds32" LD_SO_ENDIAN_SPEC LD_SO_ABI_SPEC ".so.1" -+ -+/* In the configure stage we may use options --enable-default-relax, -+ --enable-Os-default-ifc and --enable-Os-default-ex9. They effect -+ the default spec of passing --relax, --mifc, and --mex9 to linker. -+ We use NDS32_RELAX_SPEC, NDS32_IFC_SPEC, and NDS32_EX9_SPEC -+ so that we can customize them conveniently. */ -+#define LINK_SPEC \ -+ " %{G*}" \ -+ " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ -+ " %{shared:-shared} \ -+ %{!shared: \ -+ %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \ -+ %{static:-static}}" \ -+ NDS32_RELAX_SPEC -+ -+#define LINK_PIE_SPEC "%{pie:%{!fno-pie:%{!fno-PIE:%{!static:-pie}}}} " -+ -+#define CPP_SPEC "%{pthread:-D_REENTRANT}" -+ -+/* The SYNC operations are implemented as library functions, not -+ INSN patterns. As a result, the HAVE defines for the patterns are -+ not defined. We need to define them to generate the corresponding -+ __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* and __GCC_ATOMIC_*_LOCK_FREE -+ defines. -+ Ref: https://sourceware.org/ml/libc-alpha/2014-09/msg00322.html */ -+#define HAVE_sync_compare_and_swapqi 1 -+#define HAVE_sync_compare_and_swaphi 1 -+#define HAVE_sync_compare_and_swapsi 1 -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.c gcc-8.2.0/gcc/config/nds32/nds32.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32.c 2018-05-07 03:38:02.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32.c 2019-01-25 15:38:32.833242671 +0100 -@@ -305,6 +305,7 @@ - { "nested", 0, 0, false, false, false, false, NULL, NULL }, - { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, - { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, -+ { "critical", 0, 0, false, false, false, false, NULL, NULL }, - - /* The attributes describing isr register save scheme. */ - { "save_all", 0, 0, false, false, false, false, NULL, NULL }, -@@ -314,9 +315,19 @@ - { "nmi", 1, 1, false, false, false, false, NULL, NULL }, - { "warm", 1, 1, false, false, false, false, NULL, NULL }, - -+ /* The attributes describing isr security level. */ -+ { "secure", 1, 1, false, false, false, false, NULL, NULL }, -+ - /* The attribute telling no prologue/epilogue. */ - { "naked", 0, 0, false, false, false, false, NULL, NULL }, - -+ /* The attribute is used to tell this function to be ROM patch. */ -+ { "indirect_call",0, 0, false, false, false, false, NULL, NULL }, -+ -+ /* FOR BACKWARD COMPATIBILITY, -+ this attribute also tells no prologue/epilogue. */ -+ { "no_prologue", 0, 0, false, false, false, false, NULL, NULL }, -+ - /* The last attribute spec is set to be NULL. */ - { NULL, 0, 0, false, false, false, false, NULL, NULL } - }; -@@ -345,6 +356,10 @@ - /* Initially this function is not under strictly aligned situation. */ - machine->strict_aligned_p = 0; - -+ /* Initially this function has no naked and no_prologue attributes. */ -+ machine->attr_naked_p = 0; -+ machine->attr_no_prologue_p = 0; -+ - return machine; - } - -@@ -362,6 +377,15 @@ - needs prologue/epilogue. */ - cfun->machine->naked_p = 0; - -+ /* We need to mark whether this function has naked and no_prologue -+ attribute so that we can distinguish the difference if users applies -+ -mret-in-naked-func option. */ -+ cfun->machine->attr_naked_p -+ = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) -+ ? 1 : 0; -+ cfun->machine->attr_no_prologue_p -+ = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) -+ ? 1 : 0; - - /* If __builtin_eh_return is used, we better have frame pointer needed - so that we can easily locate the stack slot of return address. */ -@@ -432,7 +456,8 @@ - - /* If $gp value is required to be saved on stack, it needs 4 bytes space. - Check whether we are using PIC code genration. */ -- cfun->machine->gp_size = (flag_pic) ? 4 : 0; -+ cfun->machine->gp_size = -+ (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; - - /* If $lp value is required to be saved on stack, it needs 4 bytes space. - Check whether $lp is ever live. */ -@@ -497,7 +522,7 @@ - } - - /* Check if this function can omit prologue/epilogue code fragment. -- If there is 'naked' attribute in this function, -+ If there is 'no_prologue'/'naked'/'secure' attribute in this function, - we can set 'naked_p' flag to indicate that - we do not have to generate prologue/epilogue. - Or, if all the following conditions succeed, -@@ -510,14 +535,17 @@ - is no outgoing size. - condition 3: There is no local_size, which means - we do not need to adjust $sp. */ -- if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) -+ if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) -+ || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) -+ || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl)) - || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM - && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM - && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM - && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM - && !df_regs_ever_live_p (FP_REGNUM) - && !df_regs_ever_live_p (LP_REGNUM) -- && cfun->machine->local_size == 0)) -+ && cfun->machine->local_size == 0 -+ && !flag_pic)) - { - /* Set this function 'naked_p' and other functions can check this flag. - Note that in nds32 port, the 'naked_p = 1' JUST means there is no -@@ -1259,6 +1287,32 @@ - REG_NOTES (parallel_insn) = dwarf; - } - -+static void -+nds32_emit_load_gp (void) -+{ -+ rtx got_symbol, pat; -+ -+ /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ -+ emit_insn (gen_blockage ()); -+ -+ got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); -+ /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */ -+ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); -+ pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8))); -+ emit_insn (gen_sethi (pic_offset_table_rtx,pat)); -+ -+ /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */ -+ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); -+ pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4))); -+ emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat)); -+ -+ /* add5.pc $gp */ -+ emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx)); -+ -+ /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ -+ emit_insn (gen_blockage ()); -+} -+ - /* Function that may creates more instructions - for large value on adjusting stack pointer. - -@@ -1342,17 +1396,25 @@ - } - - /* Return true if FUNC is a naked function. */ --static bool -+bool - nds32_naked_function_p (tree func) - { -- tree t; -+ /* FOR BACKWARD COMPATIBILITY, -+ we need to support 'no_prologue' attribute as well. */ -+ tree t_naked; -+ tree t_no_prologue; - - if (TREE_CODE (func) != FUNCTION_DECL) - abort (); - -- t = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); -+ /* We have to use lookup_attribute() to check attributes. -+ Because attr_naked_p and attr_no_prologue_p are set in -+ nds32_compute_stack_frame() and the function has not been -+ invoked yet. */ -+ t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); -+ t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func)); - -- return (t != NULL_TREE); -+ return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE)); - } - - /* Function that determine whether a load postincrement is a good thing to use -@@ -1570,6 +1632,11 @@ - nds32_register_passes (void) - { - nds32_register_pass ( -+ make_pass_nds32_fp_as_gp, -+ PASS_POS_INSERT_BEFORE, -+ "ira"); -+ -+ nds32_register_pass ( - make_pass_nds32_relax_opt, - PASS_POS_INSERT_AFTER, - "mach"); -@@ -1636,6 +1703,9 @@ - { - int regno; - -+ if (TARGET_LINUX_ABI) -+ fixed_regs[TP_REGNUM] = 1; -+ - if (TARGET_HARD_FLOAT) - { - for (regno = NDS32_FIRST_FPR_REGNUM; -@@ -1987,6 +2057,16 @@ - : PARM_BOUNDARY); - } - -+bool -+nds32_vector_mode_supported_p (machine_mode mode) -+{ -+ if (mode == V4QImode -+ || mode == V2HImode) -+ return NDS32_EXT_DSP_P (); -+ -+ return false; -+} -+ - /* -- How Scalar Function Values Are Returned. */ - - static rtx -@@ -2124,56 +2204,12 @@ - nds32_asm_function_end_prologue (FILE *file) - { - fprintf (file, "\t! END PROLOGUE\n"); -- -- /* If frame pointer is NOT needed and -mfp-as-gp is issued, -- we can generate special directive: ".omit_fp_begin" -- to guide linker doing fp-as-gp optimization. -- However, for a naked function, which means -- it should not have prologue/epilogue, -- using fp-as-gp still requires saving $fp by push/pop behavior and -- there is no benefit to use fp-as-gp on such small function. -- So we need to make sure this function is NOT naked as well. */ -- if (!frame_pointer_needed -- && !cfun->machine->naked_p -- && cfun->machine->fp_as_gp_p) -- { -- fprintf (file, "\t! ----------------------------------------\n"); -- fprintf (file, "\t! Guide linker to do " -- "link time optimization: fp-as-gp\n"); -- fprintf (file, "\t! We add one more instruction to " -- "initialize $fp near to $gp location.\n"); -- fprintf (file, "\t! If linker fails to use fp-as-gp transformation,\n"); -- fprintf (file, "\t! this extra instruction should be " -- "eliminated at link stage.\n"); -- fprintf (file, "\t.omit_fp_begin\n"); -- fprintf (file, "\tla\t$fp,_FP_BASE_\n"); -- fprintf (file, "\t! ----------------------------------------\n"); -- } - } - - /* Before rtl epilogue has been expanded, this function is used. */ - static void - nds32_asm_function_begin_epilogue (FILE *file) - { -- /* If frame pointer is NOT needed and -mfp-as-gp is issued, -- we can generate special directive: ".omit_fp_end" -- to claim fp-as-gp optimization range. -- However, for a naked function, -- which means it should not have prologue/epilogue, -- using fp-as-gp still requires saving $fp by push/pop behavior and -- there is no benefit to use fp-as-gp on such small function. -- So we need to make sure this function is NOT naked as well. */ -- if (!frame_pointer_needed -- && !cfun->machine->naked_p -- && cfun->machine->fp_as_gp_p) -- { -- fprintf (file, "\t! ----------------------------------------\n"); -- fprintf (file, "\t! Claim the range of fp-as-gp " -- "link time optimization\n"); -- fprintf (file, "\t.omit_fp_end\n"); -- fprintf (file, "\t! ----------------------------------------\n"); -- } -- - fprintf (file, "\t! BEGIN EPILOGUE\n"); - } - -@@ -2200,6 +2236,26 @@ - ? 1 - : 0); - -+ if (flag_pic) -+ { -+ fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n"); -+ fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n", -+ reg_names [PIC_OFFSET_TABLE_REGNUM]); -+ fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n", -+ reg_names [PIC_OFFSET_TABLE_REGNUM], -+ reg_names [PIC_OFFSET_TABLE_REGNUM]); -+ -+ if (TARGET_ISA_V3) -+ fprintf (file, "\tadd5.pc\t$gp\n"); -+ else -+ { -+ fprintf (file, "\tmfusr\t$ta, $pc\n"); -+ fprintf (file, "\tadd\t%s, $ta, %s\n", -+ reg_names [PIC_OFFSET_TABLE_REGNUM], -+ reg_names [PIC_OFFSET_TABLE_REGNUM]); -+ } -+ } -+ - if (delta != 0) - { - if (satisfies_constraint_Is15 (GEN_INT (delta))) -@@ -2224,9 +2280,23 @@ - } - } - -- fprintf (file, "\tb\t"); -- assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); -- fprintf (file, "\n"); -+ if (flag_pic) -+ { -+ fprintf (file, "\tla\t$ta, "); -+ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); -+ fprintf (file, "@PLT\n"); -+ fprintf (file, "\t! epilogue\n"); -+ fprintf (file, "\tlwi.bi\t%s, [%s], 4\n", -+ reg_names[PIC_OFFSET_TABLE_REGNUM], -+ reg_names[STACK_POINTER_REGNUM]); -+ fprintf (file, "\tbr\t$ta\n"); -+ } -+ else -+ { -+ fprintf (file, "\tb\t"); -+ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); -+ fprintf (file, "\n"); -+ } - - final_end_function (); - } -@@ -2242,15 +2312,20 @@ - - /* 1. Do not apply sibling call if -mv3push is enabled, - because pop25 instruction also represents return behavior. -- 2. If this function is a variadic function, do not apply sibling call -+ 2. If this function is a isr function, do not apply sibling call -+ because it may perform the behavior that user does not expect. -+ 3. If this function is a variadic function, do not apply sibling call - because the stack layout may be a mess. -- 3. We don't want to apply sibling call optimization for indirect -+ 4. We don't want to apply sibling call optimization for indirect - sibcall because the pop behavior in epilogue may pollute the - content of caller-saved regsiter when the register is used for -- indirect sibcall. */ -+ indirect sibcall. -+ 5. In pic mode, it may use some registers for PLT call. */ - return (!TARGET_V3PUSH -+ && !nds32_isr_function_p (current_function_decl) - && (cfun->machine->va_args_size == 0) -- && decl); -+ && decl -+ && !flag_pic); - } - - /* Determine whether we need to enable warning for function return check. */ -@@ -2566,6 +2641,13 @@ - - case SYMBOL_REF: - /* (mem (symbol_ref A)) => [symbol_ref] */ -+ -+ if (flag_pic || SYMBOL_REF_TLS_MODEL (x)) -+ return false; -+ -+ if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) -+ return false; -+ - /* If -mcmodel=large, the 'symbol_ref' is not a valid address - during or after LRA/reload phase. */ - if (TARGET_CMODEL_LARGE -@@ -2577,7 +2659,8 @@ - the 'symbol_ref' is not a valid address during or after - LRA/reload phase. */ - if (TARGET_CMODEL_MEDIUM -- && NDS32_SYMBOL_REF_RODATA_P (x) -+ && (NDS32_SYMBOL_REF_RODATA_P (x) -+ || CONSTANT_POOL_ADDRESS_P (x)) - && (reload_completed - || reload_in_progress - || lra_in_progress)) -@@ -2599,6 +2682,10 @@ - { - /* Now we see the [ + const_addr ] pattern, but we need - some further checking. */ -+ -+ if (flag_pic || SYMBOL_REF_TLS_MODEL (op0)) -+ return false; -+ - /* If -mcmodel=large, the 'const_addr' is not a valid address - during or after LRA/reload phase. */ - if (TARGET_CMODEL_LARGE -@@ -2675,17 +2762,202 @@ - - case LO_SUM: - /* (mem (lo_sum (reg) (symbol_ref))) */ -- /* (mem (lo_sum (reg) (const))) */ -- gcc_assert (REG_P (XEXP (x, 0))); -- if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -- || GET_CODE (XEXP (x, 1)) == CONST) -- return nds32_legitimate_address_p (mode, XEXP (x, 1), strict); -- else -+ /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */ -+ /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */ -+ /* The LO_SUM is a valid address if and only if we would like to -+ generate 32-bit full address memory access with any of following -+ circumstance: -+ 1. -mcmodel=large. -+ 2. -mcmodel=medium and the symbol_ref references to rodata. */ -+ { -+ rtx sym = NULL_RTX; -+ -+ if (flag_pic) -+ return false; -+ -+ if (!REG_P (XEXP (x, 0))) -+ return false; -+ -+ if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF) -+ sym = XEXP (x, 1); -+ else if (GET_CODE (XEXP (x, 1)) == CONST) -+ { -+ rtx plus = XEXP(XEXP (x, 1), 0); -+ if (GET_CODE (plus) == PLUS) -+ sym = XEXP (plus, 0); -+ else if (GET_CODE (plus) == UNSPEC) -+ sym = XVECEXP (plus, 0, 0); -+ } -+ else -+ return false; -+ -+ gcc_assert (GET_CODE (sym) == SYMBOL_REF); -+ -+ if (TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (sym)) -+ return true; -+ -+ if (TARGET_CMODEL_LARGE) -+ return true; -+ else if (TARGET_CMODEL_MEDIUM -+ && NDS32_SYMBOL_REF_RODATA_P (sym)) -+ return true; -+ else -+ return false; -+ } -+ -+ default: -+ return false; -+ } -+} -+ -+static rtx -+nds32_legitimize_address (rtx x, -+ rtx oldx ATTRIBUTE_UNUSED, -+ machine_mode mode ATTRIBUTE_UNUSED) -+{ -+ if (nds32_tls_referenced_p (x)) -+ x = nds32_legitimize_tls_address (x); -+ else if (flag_pic && SYMBOLIC_CONST_P (x)) -+ x = nds32_legitimize_pic_address (x); -+ else if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) -+ x = nds32_legitimize_ict_address (x); -+ -+ return x; -+} -+ -+static bool -+nds32_legitimate_constant_p (machine_mode mode, rtx x) -+{ -+ switch (GET_CODE (x)) -+ { -+ case CONST_DOUBLE: -+ if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) -+ && (mode == DFmode || mode == SFmode)) - return false; -+ break; -+ case CONST: -+ x = XEXP (x, 0); -+ -+ if (GET_CODE (x) == PLUS) -+ { -+ if (!CONST_INT_P (XEXP (x, 1))) -+ return false; -+ x = XEXP (x, 0); -+ } -+ -+ if (GET_CODE (x) == UNSPEC) -+ { -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_GOT: -+ case UNSPEC_GOTOFF: -+ case UNSPEC_PLT: -+ case UNSPEC_TLSGD: -+ case UNSPEC_TLSLD: -+ case UNSPEC_TLSIE: -+ case UNSPEC_TLSLE: -+ case UNSPEC_ICT: -+ return false; -+ default: -+ return true; -+ } -+ } -+ break; -+ case SYMBOL_REF: -+ /* TLS symbols need a call to resolve in -+ precompute_register_parameters. */ -+ if (SYMBOL_REF_TLS_MODEL (x)) -+ return false; -+ break; -+ default: -+ return true; -+ } -+ -+ return true; -+} -+ -+/* Reorgnize the UNSPEC CONST and return its direct symbol. */ -+static rtx -+nds32_delegitimize_address (rtx x) -+{ -+ x = delegitimize_mem_from_attrs (x); -+ -+ if (GET_CODE(x) == CONST) -+ { -+ rtx inner = XEXP (x, 0); -+ -+ /* Handle for GOTOFF. */ -+ if (GET_CODE (inner) == PLUS) -+ inner = XEXP (inner, 0); -+ -+ if (GET_CODE (inner) == UNSPEC) -+ { -+ switch (XINT (inner, 1)) -+ { -+ case UNSPEC_GOTINIT: -+ case UNSPEC_GOT: -+ case UNSPEC_GOTOFF: -+ case UNSPEC_PLT: -+ case UNSPEC_TLSGD: -+ case UNSPEC_TLSLD: -+ case UNSPEC_TLSIE: -+ case UNSPEC_TLSLE: -+ case UNSPEC_ICT: -+ x = XVECEXP (inner, 0, 0); -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ return x; -+} - -+static machine_mode -+nds32_vectorize_preferred_simd_mode (scalar_mode mode) -+{ -+ if (!NDS32_EXT_DSP_P ()) -+ return word_mode; -+ -+ switch (mode) -+ { -+ case E_QImode: -+ return V4QImode; -+ case E_HImode: -+ return V2HImode; -+ default: -+ return word_mode; -+ } -+} -+ -+static bool -+nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) -+{ -+ switch (GET_CODE (x)) -+ { -+ case CONST: -+ return !nds32_legitimate_constant_p (mode, x); -+ case SYMBOL_REF: -+ /* All symbols have to be accessed through gp-relative in PIC mode. */ -+ /* We don't want to force symbol as constant pool in .text section, -+ because we use the gp-relatived instruction to load in small -+ or medium model. */ -+ if (flag_pic -+ || SYMBOL_REF_TLS_MODEL (x) -+ || TARGET_CMODEL_SMALL -+ || TARGET_CMODEL_MEDIUM) -+ return true; -+ break; -+ case CONST_INT: -+ case CONST_DOUBLE: -+ if (flag_pic && (lra_in_progress || reload_completed)) -+ return true; -+ break; - default: - return false; - } -+ return false; - } - - -@@ -2731,13 +3003,33 @@ - /* Describing Relative Costs of Operations. */ - - static int --nds32_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, -+nds32_register_move_cost (machine_mode mode, - reg_class_t from, - reg_class_t to) - { -+ /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ -+ if (TARGET_PIPELINE_GRAYWOLF) -+ { -+ if (GET_MODE_SIZE (mode) == 8) -+ { -+ /* DPR to GPR. */ -+ if (from == FP_REGS && to != FP_REGS) -+ return 3; -+ /* GPR to DPR. */ -+ if (from != FP_REGS && to == FP_REGS) -+ return 2; -+ } -+ else -+ { -+ if ((from == FP_REGS && to != FP_REGS) -+ || (from != FP_REGS && to == FP_REGS)) -+ return 2; -+ } -+ } -+ - if ((from == FP_REGS && to != FP_REGS) - || (from != FP_REGS && to == FP_REGS)) -- return 9; -+ return 3; - else if (from == HIGH_REGS || to == HIGH_REGS) - return optimize_size ? 6 : 2; - else -@@ -2825,6 +3117,9 @@ - { - default_file_start (); - -+ if (flag_pic) -+ fprintf (asm_out_file, "\t.pic\n"); -+ - /* Tell assembler which ABI we are using. */ - fprintf (asm_out_file, "\t! ABI version\n"); - if (TARGET_HARD_FLOAT) -@@ -2835,10 +3130,36 @@ - /* Tell assembler that this asm code is generated by compiler. */ - fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); - fprintf (asm_out_file, "\t.flag\tverbatim\n"); -- /* Give assembler the size of each vector for interrupt handler. */ -- fprintf (asm_out_file, "\t! This vector size directive is required " -- "for checking inconsistency on interrupt handler\n"); -- fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); -+ -+ /* Insert directive for linker to distinguish object's ict flag. */ -+ if (!TARGET_LINUX_ABI) -+ { -+ if (TARGET_ICT_MODEL_LARGE) -+ fprintf (asm_out_file, "\t.ict_model\tlarge\n"); -+ else -+ fprintf (asm_out_file, "\t.ict_model\tsmall\n"); -+ } -+ -+ /* We need to provide the size of each vector for interrupt handler -+ under elf toolchain. */ -+ if (!TARGET_LINUX_ABI) -+ { -+ fprintf (asm_out_file, "\t! This vector size directive is required " -+ "for checking inconsistency on interrupt handler\n"); -+ fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); -+ } -+ -+ /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os, -+ the compiler may produce 'la $fp,_FP_BASE_' instruction -+ at prologue for fp-as-gp optimization. -+ We should emit weak reference of _FP_BASE_ to avoid undefined reference -+ in case user does not pass '--relax' option to linker. */ -+ if (!TARGET_LINUX_ABI && (TARGET_FORCE_FP_AS_GP || optimize_size)) -+ { -+ fprintf (asm_out_file, "\t! This weak reference is required to do " -+ "fp-as-gp link time optimization\n"); -+ fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n"); -+ } - - fprintf (asm_out_file, "\t! ------------------------------------\n"); - -@@ -2849,6 +3170,49 @@ - if (TARGET_ISA_V3M) - fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); - -+ switch (nds32_cpu_option) -+ { -+ case CPU_N6: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N6"); -+ break; -+ -+ case CPU_N7: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N7"); -+ break; -+ -+ case CPU_N8: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8"); -+ break; -+ -+ case CPU_E8: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "E8"); -+ break; -+ -+ case CPU_N9: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N9"); -+ break; -+ -+ case CPU_N10: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10"); -+ break; -+ -+ case CPU_GRAYWOLF: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "Graywolf"); -+ break; -+ -+ case CPU_N12: -+ case CPU_N13: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N13"); -+ break; -+ -+ case CPU_SIMPLE: -+ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE"); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ - if (TARGET_CMODEL_SMALL) - fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); - if (TARGET_CMODEL_MEDIUM) -@@ -2926,9 +3290,65 @@ - { - nds32_asm_file_end_for_isr (); - -+ /* The NDS32 Linux stack is mapped non-executable by default, so add a -+ .note.GNU-stack section. */ -+ if (TARGET_LINUX_ABI) -+ file_end_indicate_exec_stack (); -+ - fprintf (asm_out_file, "\t! ------------------------------------\n"); - } - -+static bool -+nds32_asm_output_addr_const_extra (FILE *file, rtx x) -+{ -+ if (GET_CODE (x) == UNSPEC) -+ { -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_GOTINIT: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ break; -+ case UNSPEC_GOTOFF: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@GOTOFF", file); -+ break; -+ case UNSPEC_GOT: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@GOT", file); -+ break; -+ case UNSPEC_PLT: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@PLT", file); -+ break; -+ case UNSPEC_TLSGD: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@TLSDESC", file); -+ break; -+ case UNSPEC_TLSLD: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@TLSDESC", file); -+ break; -+ case UNSPEC_TLSIE: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@GOTTPOFF", file); -+ break; -+ case UNSPEC_TLSLE: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@TPOFF", file); -+ break; -+ case UNSPEC_ICT: -+ output_addr_const (file, XVECEXP (x, 0, 0)); -+ fputs ("@ICT", file); -+ break; -+ default: -+ return false; -+ } -+ return true; -+ } -+ else -+ return false; -+} -+ - /* -- Output and Generation of Labels. */ - - static void -@@ -2978,6 +3398,18 @@ - - /* No need to handle following process, so return immediately. */ - return; -+ -+ case 'v': -+ gcc_assert (CONST_INT_P (x) -+ && (INTVAL (x) == 0 -+ || INTVAL (x) == 8 -+ || INTVAL (x) == 16 -+ || INTVAL (x) == 24)); -+ fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8); -+ -+ /* No need to handle following process, so return immediately. */ -+ return; -+ - case 'B': - /* Use exact_log2() to search the 1-bit position. */ - gcc_assert (CONST_INT_P (x)); -@@ -3084,8 +3516,15 @@ - switch (GET_CODE (x)) - { - case LABEL_REF: -+ output_addr_const (stream, x); -+ break; -+ - case SYMBOL_REF: - output_addr_const (stream, x); -+ -+ if (!TARGET_LINUX_ABI && nds32_indirect_call_referenced_p (x)) -+ fprintf (stream, "@ICT"); -+ - break; - - case REG: -@@ -3168,6 +3607,17 @@ - output_addr_const (stream, x); - break; - -+ case CONST_VECTOR: -+ fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x)); -+ break; -+ -+ case LO_SUM: -+ /* This is a special case for inline assembly using memory address 'p'. -+ The inline assembly code is expected to use pesudo instruction -+ for the operand. EX: la */ -+ output_addr_const (stream, XEXP(x, 1)); -+ break; -+ - default: - /* Generally, output_addr_const () is able to handle most cases. - We want to see what CODE could appear, -@@ -3179,7 +3629,9 @@ - } - - static void --nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) -+nds32_print_operand_address (FILE *stream, -+ machine_mode mode ATTRIBUTE_UNUSED, -+ rtx x) - { - rtx op0, op1; - -@@ -3194,6 +3646,16 @@ - fputs ("]", stream); - break; - -+ case LO_SUM: -+ /* This is a special case for inline assembly using memory operand 'm'. -+ The inline assembly code is expected to use pesudo instruction -+ for the operand. EX: [ls].[bhw] */ -+ fputs ("[ + ", stream); -+ op1 = XEXP (x, 1); -+ output_addr_const (stream, op1); -+ fputs ("]", stream); -+ break; -+ - case REG: - /* Forbid using static chain register ($r16) - on reduced-set registers configuration. */ -@@ -3260,6 +3722,20 @@ - reg_names[REGNO (XEXP (op0, 0))], - sv); - } -+ else if (GET_CODE (op0) == ASHIFT && REG_P (op1)) -+ { -+ /* [Ra + Rb << sv] -+ In normal, ASHIFT can be converted to MULT like above case. -+ But when the address rtx does not go through canonicalize_address -+ defined in fwprop, we'll need this case. */ -+ int sv = INTVAL (XEXP (op0, 1)); -+ gcc_assert (sv <= 3 && sv >=0); -+ -+ fprintf (stream, "[%s + %s << %d]", -+ reg_names[REGNO (op1)], -+ reg_names[REGNO (XEXP (op0, 0))], -+ sv); -+ } - else - { - /* The control flow is not supposed to be here. */ -@@ -3454,6 +3930,27 @@ - static void - nds32_insert_attributes (tree decl, tree *attributes) - { -+ /* A "indirect_call" function attribute implies "noinline" and "noclone" -+ for elf toolchain to support ROM patch mechanism. */ -+ if (TREE_CODE (decl) == FUNCTION_DECL -+ && lookup_attribute ("indirect_call", *attributes) != NULL) -+ { -+ tree new_attrs = *attributes; -+ -+ if (TARGET_LINUX_ABI) -+ error("cannot use indirect_call attribute under linux toolchain"); -+ -+ if (lookup_attribute ("noinline", new_attrs) == NULL) -+ new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs); -+ if (lookup_attribute ("noclone", new_attrs) == NULL) -+ new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs); -+ -+ if (!TREE_PUBLIC (decl)) -+ error("indirect_call attribute can't apply for static function"); -+ -+ *attributes = new_attrs; -+ } -+ - /* For function declaration, we need to check isr-specific attributes: - 1. Call nds32_check_isr_attrs_conflict() to check any conflict. - 2. Check valid integer value for interrupt/exception. -@@ -3479,6 +3976,38 @@ - excp = lookup_attribute ("exception", func_attrs); - reset = lookup_attribute ("reset", func_attrs); - -+ /* The following code may use attribute arguments. If there is no -+ argument from source code, it will cause segmentation fault. -+ Therefore, return dircetly and report error message later. */ -+ if ((intr && TREE_VALUE (intr) == NULL) -+ || (excp && TREE_VALUE (excp) == NULL) -+ || (reset && TREE_VALUE (reset) == NULL)) -+ return; -+ -+ /* ------------------------------------------------------------- */ -+ /* FIXME: -+ FOR BACKWARD COMPATIBILITY, we need to support following patterns: -+ -+ __attribute__((interrupt("XXX;YYY;id=ZZZ"))) -+ __attribute__((exception("XXX;YYY;id=ZZZ"))) -+ __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) -+ -+ If interrupt/exception/reset appears and its argument is a -+ STRING_CST, we will use other functions to parse string in the -+ nds32_construct_isr_vectors_information() and then set necessary -+ isr information in the nds32_isr_vectors[] array. Here we can -+ just return immediately to avoid new-syntax checking. */ -+ if (intr != NULL_TREE -+ && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) -+ return; -+ if (excp != NULL_TREE -+ && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) -+ return; -+ if (reset != NULL_TREE -+ && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) -+ return; -+ /* ------------------------------------------------------------- */ -+ - if (intr || excp) - { - /* Deal with interrupt/exception. */ -@@ -3598,7 +4127,9 @@ - } - if (TARGET_ISA_V3) - { -- /* Under V3 ISA, currently nothing should be strictly set. */ -+ /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */ -+ if (nds32_arch_option == ARCH_V3J) -+ target_flags |= MASK_REDUCED_REGS; - } - if (TARGET_ISA_V3M) - { -@@ -3610,6 +4141,9 @@ - target_flags &= ~MASK_EXT_PERF2; - /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ - target_flags &= ~MASK_EXT_STRING; -+ -+ if (flag_pic) -+ error ("not support -fpic option for v3m toolchain"); - } - - /* See if we are using reduced-set registers: -@@ -3627,6 +4161,12 @@ - fixed_regs[r] = call_used_regs[r] = 1; - } - -+ /* See if user explicitly would like to use fp-as-gp optimization. -+ If so, we must prevent $fp from being allocated -+ during register allocation. */ -+ if (TARGET_FORCE_FP_AS_GP) -+ fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1; -+ - if (!TARGET_16_BIT) - { - /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ -@@ -3643,9 +4183,7 @@ - "must be enable '-mext-fpu-sp' or '-mext-fpu-dp'"); - } - -- /* Currently, we don't support PIC code generation yet. */ -- if (flag_pic) -- sorry ("position-independent code not supported"); -+ nds32_init_rtx_costs (); - - nds32_register_passes (); - } -@@ -3659,8 +4197,11 @@ - vec &constraints ATTRIBUTE_UNUSED, - vec &clobbers, HARD_REG_SET &clobbered_regs) - { -- clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); -- SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); -+ if (!flag_inline_asm_r15) -+ { -+ clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); -+ SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); -+ } - return NULL; - } - -@@ -3687,6 +4228,13 @@ - return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); - } - -+/* Implement TARGET_INIT_LIBFUNCS. */ -+static void -+nds32_init_libfuncs (void) -+{ -+ if (TARGET_LINUX_ABI) -+ init_sync_libfuncs (UNITS_PER_WORD); -+} - - /* ------------------------------------------------------------------------ */ - -@@ -3703,6 +4251,16 @@ - builtin_define ("__nds32__"); - builtin_define ("__NDS32__"); - -+ /* We need to provide builtin macro to describe the size of -+ each vector for interrupt handler under elf toolchain. */ -+ if (!TARGET_LINUX_ABI) -+ { -+ if (TARGET_ISR_VECTOR_SIZE_4_BYTE) -+ builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__"); -+ else -+ builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__"); -+ } -+ - if (TARGET_HARD_FLOAT) - builtin_define ("__NDS32_ABI_2FP_PLUS__"); - else -@@ -3770,6 +4328,8 @@ - builtin_define ("__NDS32_GP_DIRECT__"); - if (TARGET_VH) - builtin_define ("__NDS32_VH__"); -+ if (NDS32_EXT_DSP_P ()) -+ builtin_define ("__NDS32_EXT_DSP__"); - - if (TARGET_BIG_ENDIAN) - builtin_define ("__big_endian__"); -@@ -4042,6 +4602,10 @@ - The result will be in cfun->machine. */ - nds32_compute_stack_frame (); - -+ /* Check frame_pointer_needed again to prevent fp is need after reload. */ -+ if (frame_pointer_needed) -+ cfun->machine->fp_as_gp_p = false; -+ - /* If this is a variadic function, first we need to push argument - registers that hold the unnamed argument value. */ - if (cfun->machine->va_args_size != 0) -@@ -4066,7 +4630,7 @@ - - /* If the function is 'naked', - we do not have to generate prologue code fragment. */ -- if (cfun->machine->naked_p) -+ if (cfun->machine->naked_p && !flag_pic) - return; - - /* Get callee_first_regno and callee_last_regno. */ -@@ -4195,9 +4759,15 @@ - -1 * sp_adjust); - } - -- /* Prevent the instruction scheduler from -- moving instructions across the boundary. */ -- emit_insn (gen_blockage ()); -+ /* Emit gp setup instructions for -fpic. */ -+ if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) -+ nds32_emit_load_gp (); -+ -+ /* If user applies -mno-sched-prolog-epilog option, -+ we need to prevent instructions of function body from being -+ scheduled with stack adjustment in prologue. */ -+ if (!flag_sched_prolog_epilog) -+ emit_insn (gen_blockage ()); - } - - /* Function for normal multiple pop epilogue. */ -@@ -4211,9 +4781,11 @@ - The result will be in cfun->machine. */ - nds32_compute_stack_frame (); - -- /* Prevent the instruction scheduler from -- moving instructions across the boundary. */ -- emit_insn (gen_blockage ()); -+ /* If user applies -mno-sched-prolog-epilog option, -+ we need to prevent instructions of function body from being -+ scheduled with stack adjustment in epilogue. */ -+ if (!flag_sched_prolog_epilog) -+ emit_insn (gen_blockage ()); - - /* If the function is 'naked', we do not have to generate - epilogue code fragment BUT 'ret' instruction. -@@ -4239,7 +4811,16 @@ - /* Generate return instruction by using 'return_internal' pattern. - Make sure this instruction is after gen_blockage(). */ - if (!sibcall_p) -- emit_jump_insn (gen_return_internal ()); -+ { -+ /* We need to further check attributes to determine whether -+ there should be return instruction at epilogue. -+ If the attribute naked exists but -mno-ret-in-naked-func -+ is issued, there is NO need to generate return instruction. */ -+ if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) -+ return; -+ -+ emit_jump_insn (gen_return_internal ()); -+ } - return; - } - -@@ -4436,9 +5017,13 @@ - if (cfun->machine->callee_saved_gpr_regs_size > 0) - df_set_regs_ever_live (FP_REGNUM, 1); - -+ /* Check frame_pointer_needed again to prevent fp is need after reload. */ -+ if (frame_pointer_needed) -+ cfun->machine->fp_as_gp_p = false; -+ - /* If the function is 'naked', - we do not have to generate prologue code fragment. */ -- if (cfun->machine->naked_p) -+ if (cfun->machine->naked_p && !flag_pic) - return; - - /* Get callee_first_regno and callee_last_regno. */ -@@ -4566,6 +5151,10 @@ - -1 * sp_adjust); - } - -+ /* Emit gp setup instructions for -fpic. */ -+ if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) -+ nds32_emit_load_gp (); -+ - /* Prevent the instruction scheduler from - moving instructions across the boundary. */ - emit_insn (gen_blockage ()); -@@ -4591,9 +5180,19 @@ - if (cfun->machine->naked_p) - { - /* Generate return instruction by using 'return_internal' pattern. -- Make sure this instruction is after gen_blockage(). */ -+ Make sure this instruction is after gen_blockage(). -+ First we need to check this is a function without sibling call. */ - if (!sibcall_p) -- emit_jump_insn (gen_return_internal ()); -+ { -+ /* We need to further check attributes to determine whether -+ there should be return instruction at epilogue. -+ If the attribute naked exists but -mno-ret-in-naked-func -+ is issued, there is NO need to generate return instruction. */ -+ if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) -+ return; -+ -+ emit_jump_insn (gen_return_internal ()); -+ } - return; - } - -@@ -4757,6 +5356,11 @@ - if (!reload_completed) - return 0; - -+ /* If attribute 'naked' appears but -mno-ret-in-naked-func is used, -+ we cannot use return instruction. */ -+ if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) -+ return 0; -+ - sp_adjust = cfun->machine->local_size - + cfun->machine->out_args_size - + cfun->machine->callee_saved_area_gpr_padding_bytes -@@ -5010,6 +5614,9 @@ - #undef TARGET_FUNCTION_ARG_BOUNDARY - #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary - -+#undef TARGET_VECTOR_MODE_SUPPORTED_P -+#define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p -+ - /* -- How Scalar Function Values Are Returned. */ - - #undef TARGET_FUNCTION_VALUE -@@ -5087,6 +5694,21 @@ - #undef TARGET_LEGITIMATE_ADDRESS_P - #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p - -+#undef TARGET_LEGITIMIZE_ADDRESS -+#define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address -+ -+#undef TARGET_LEGITIMATE_CONSTANT_P -+#define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p -+ -+#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE -+#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem -+ -+#undef TARGET_DELEGITIMIZE_ADDRESS -+#define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address -+ - - /* Anchored Addresses. */ - -@@ -5147,6 +5769,9 @@ - #undef TARGET_ASM_ALIGNED_SI_OP - #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" - -+#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA -+#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra -+ - /* -- Output of Uninitialized Variables. */ - - /* -- Output and Generation of Labels. */ -@@ -5216,6 +5841,9 @@ - - /* Emulating TLS. */ - -+#undef TARGET_HAVE_TLS -+#define TARGET_HAVE_TLS TARGET_LINUX_ABI -+ - - /* Defining coprocessor specifics for MIPS targets. */ - -@@ -5243,6 +5871,8 @@ - #undef TARGET_EXPAND_BUILTIN - #define TARGET_EXPAND_BUILTIN nds32_expand_builtin - -+#undef TARGET_INIT_LIBFUNCS -+#define TARGET_INIT_LIBFUNCS nds32_init_libfuncs - - #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P - #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-cost.c gcc-8.2.0/gcc/config/nds32/nds32-cost.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-cost.c 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-cost.c 2019-01-25 15:38:32.821242637 +0100 -@@ -34,66 +34,379 @@ - #include "optabs.h" /* For GEN_FCN. */ - #include "recog.h" - #include "tm-constrs.h" -+#include "tree-pass.h" - - /* ------------------------------------------------------------------------ */ - --bool --nds32_rtx_costs_impl (rtx x, -- machine_mode mode ATTRIBUTE_UNUSED, -- int outer_code, -- int opno ATTRIBUTE_UNUSED, -- int *total, -- bool speed) --{ -- int code = GET_CODE (x); -+typedef bool (*rtx_cost_func) (rtx, int, int, int, int*); - -- /* According to 'speed', goto suitable cost model section. */ -- if (speed) -- goto performance_cost; -- else -- goto size_cost; -- -- --performance_cost: -- /* This is section for performance cost model. */ -+struct rtx_cost_model_t { -+ rtx_cost_func speed_prefer; -+ rtx_cost_func size_prefer; -+}; -+ -+static rtx_cost_model_t rtx_cost_model; -+ -+static int insn_size_16bit; /* Initial at nds32_init_rtx_costs. */ -+static const int insn_size_32bit = 4; -+ -+static bool -+nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED, -+ int code, -+ int outer_code ATTRIBUTE_UNUSED, -+ int opno ATTRIBUTE_UNUSED, -+ int *total) -+{ -+ rtx op0; -+ rtx op1; -+ machine_mode mode = GET_MODE (x); -+ /* Scale cost by mode size. */ -+ int cost = COSTS_N_INSNS (GET_MODE_SIZE (mode) / GET_MODE_SIZE (SImode)); - -- /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4. -- We treat it as 4-cycle cost for each instruction -- under performance consideration. */ - switch (code) - { -- case SET: -- /* For 'SET' rtx, we need to return false -- so that it can recursively calculate costs. */ -- return false; -- - case USE: - /* Used in combine.c as a marker. */ - *total = 0; -- break; -+ return true; -+ -+ case CONST_INT: -+ /* When not optimizing for size, we care more about the cost -+ of hot code, and hot code is often in a loop. If a constant -+ operand needs to be forced into a register, we will often be -+ able to hoist the constant load out of the loop, so the load -+ should not contribute to the cost. */ -+ if (outer_code == SET || outer_code == PLUS) -+ *total = satisfies_constraint_Is20 (x) ? 0 : 4; -+ else if (outer_code == AND || outer_code == IOR || outer_code == XOR -+ || outer_code == MINUS) -+ *total = satisfies_constraint_Iu15 (x) ? 0 : 4; -+ else if (outer_code == ASHIFT || outer_code == ASHIFTRT -+ || outer_code == LSHIFTRT) -+ *total = satisfies_constraint_Iu05 (x) ? 0 : 4; -+ else if (GET_RTX_CLASS (outer_code) == RTX_COMPARE -+ || GET_RTX_CLASS (outer_code) == RTX_COMM_COMPARE) -+ *total = satisfies_constraint_Is16 (x) ? 0 : 4; -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case CONST: -+ case LO_SUM: -+ case HIGH: -+ case SYMBOL_REF: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case MEM: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case SET: -+ op0 = SET_DEST (x); -+ op1 = SET_SRC (x); -+ mode = GET_MODE (op0); -+ /* Scale cost by mode size. */ -+ cost = COSTS_N_INSNS (GET_MODE_SIZE (mode) / GET_MODE_SIZE (SImode)); -+ -+ switch (GET_CODE (op1)) -+ { -+ case REG: -+ case SUBREG: -+ /* Register move and Store instructions. */ -+ if ((REG_P (op0) || MEM_P (op0)) -+ && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode)) -+ *total = COSTS_N_INSNS (1); -+ else -+ *total = cost; -+ return true; -+ -+ case MEM: -+ /* Load instructions. */ -+ if (REG_P (op0) && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode)) -+ *total = COSTS_N_INSNS (1); -+ else -+ *total = cost; -+ return true; -+ -+ case CONST_INT: -+ /* movi instruction. */ -+ if (REG_P (op0) && GET_MODE_SIZE (mode) < GET_MODE_SIZE (DImode)) -+ { -+ if (satisfies_constraint_Is20 (op1)) -+ *total = COSTS_N_INSNS (1) - 1; -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ else -+ *total = cost; -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case LABEL_REF: -+ /* la instruction. */ -+ if (REG_P (op0) && GET_MODE_SIZE (mode) < GET_MODE_SIZE (DImode)) -+ *total = COSTS_N_INSNS (1) - 1; -+ else -+ *total = cost; -+ return true; -+ case VEC_SELECT: -+ *total = cost; -+ return true; -+ -+ default: -+ *total = cost; -+ return true; -+ } -+ -+ case PLUS: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) -+ *total = cost; -+ else if (GET_CODE (op0) == MULT || GET_CODE (op0) == LSHIFTRT -+ || GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT) -+ /* ALU_SHIFT */ -+ *total = COSTS_N_INSNS (2); -+ -+ else if ((GET_CODE (op1) == CONST_INT -+ && satisfies_constraint_Is15 (op1)) -+ || REG_P (op1)) -+ /* ADD instructions */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* ADD instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ return true; -+ -+ case MINUS: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) -+ *total = cost; -+ else if (GET_CODE (op0) == MULT || GET_CODE (op0) == LSHIFTRT -+ || GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT) -+ /* ALU_SHIFT */ -+ *total = COSTS_N_INSNS (2); -+ else if ((GET_CODE (op0) == CONST_INT -+ && satisfies_constraint_Is15 (op0)) -+ || REG_P (op0)) -+ /* SUB instructions */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* SUB instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ return true; -+ -+ case TRUNCATE: -+ /* TRUNCATE and AND behavior is same. */ -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case AND: -+ case IOR: -+ case XOR: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ if (NDS32_EXT_DSP_P ()) -+ { -+ /* We prefer (and (ior) (ior)) than (ior (and) (and)) for -+ synthetize pk** and insb instruction. */ -+ if (code == AND && GET_CODE (op0) == IOR && GET_CODE (op1) == IOR) -+ return COSTS_N_INSNS (1); -+ -+ if (code == IOR && GET_CODE (op0) == AND && GET_CODE (op1) == AND) -+ return COSTS_N_INSNS (10); -+ } -+ -+ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) -+ *total = cost; -+ else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFTRT) -+ *total = COSTS_N_INSNS (2); -+ else if ((GET_CODE (op1) == CONST_INT -+ && satisfies_constraint_Iu15 (op1)) -+ || REG_P (op1)) -+ /* AND, OR, XOR instructions */ -+ *total = COSTS_N_INSNS (1); -+ else if (code == AND || GET_CODE (op0) == NOT) -+ /* BITC instruction */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* AND, OR, XOR instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ return true; - - case MULT: -+ if (GET_MODE (x) == DImode -+ || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND -+ || GET_CODE (XEXP (x, 1)) == ZERO_EXTEND) -+ /* MUL instructions */ -+ *total = COSTS_N_INSNS (1); -+ else if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) -+ *total = cost; -+ else if (outer_code == PLUS || outer_code == MINUS) -+ *total = COSTS_N_INSNS (2); -+ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT -+ && satisfies_constraint_Iu05 (XEXP (x, 1))) -+ || REG_P (XEXP (x, 1))) -+ /* MUL instructions */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* MUL instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ -+ if (TARGET_MUL_SLOW) -+ *total += COSTS_N_INSNS (4); -+ -+ return true; -+ -+ case LSHIFTRT: -+ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) -+ *total = cost; -+ else if (outer_code == PLUS || outer_code == MINUS -+ || outer_code == AND || outer_code == IOR -+ || outer_code == XOR) -+ *total = COSTS_N_INSNS (2); -+ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT -+ && satisfies_constraint_Iu05 (XEXP (x, 1))) -+ || REG_P (XEXP (x, 1))) -+ /* SRL instructions */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* SRL instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ return true; -+ -+ case ASHIFT: -+ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) -+ *total = cost; -+ else if (outer_code == AND || outer_code == IOR -+ || outer_code == XOR) -+ *total = COSTS_N_INSNS (2); -+ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT -+ && satisfies_constraint_Iu05 (XEXP (x, 1))) -+ || REG_P (XEXP (x, 1))) -+ /* SLL instructions */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* SLL instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ return true; -+ -+ case ASHIFTRT: -+ case ROTATERT: -+ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) -+ *total = cost; -+ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT -+ && satisfies_constraint_Iu05 (XEXP (x, 1))) -+ || REG_P (XEXP (x, 1))) -+ /* ROTR, SLL instructions */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* ROTR, SLL instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ return true; -+ -+ case LT: -+ case LTU: -+ if (outer_code == SET) -+ { -+ if ((GET_CODE (XEXP (x, 1)) == CONST_INT -+ && satisfies_constraint_Iu15 (XEXP (x, 1))) -+ || REG_P (XEXP (x, 1))) -+ /* SLT, SLTI instructions */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* SLT, SLT instructions: IMM out of range. */ -+ *total = COSTS_N_INSNS (2); -+ } -+ else -+ /* branch */ -+ *total = COSTS_N_INSNS (2); -+ return true; -+ -+ case EQ: -+ case NE: -+ case GE: -+ case LE: -+ case GT: -+ /* branch */ -+ *total = COSTS_N_INSNS (2); -+ return true; -+ -+ case IF_THEN_ELSE: -+ if (GET_CODE (XEXP (x, 1)) == LABEL_REF) -+ /* branch */ -+ *total = COSTS_N_INSNS (2); -+ else -+ /* cmovz, cmovn instructions */ -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ if (outer_code == IF_THEN_ELSE) -+ /* branch */ -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case ZERO_EXTEND: -+ case SIGN_EXTEND: -+ if (MEM_P (XEXP (x, 0))) -+ /* Using memory access. */ -+ *total = COSTS_N_INSNS (1); -+ else -+ /* Zero extend and sign extend instructions. */ -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case NEG: -+ case NOT: - *total = COSTS_N_INSNS (1); -- break; -+ return true; - - case DIV: - case UDIV: - case MOD: - case UMOD: -- *total = COSTS_N_INSNS (7); -- break; -- -- default: -- *total = COSTS_N_INSNS (1); -- break; -- } -+ *total = COSTS_N_INSNS (20); -+ return true; - -- return true; -+ case CALL: -+ *total = COSTS_N_INSNS (2); -+ return true; - -+ case CLZ: -+ case SMIN: -+ case SMAX: -+ case ZERO_EXTRACT: -+ if (TARGET_EXT_PERF) -+ *total = COSTS_N_INSNS (1); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ case VEC_SELECT: -+ *total = COSTS_N_INSNS (1); -+ return true; - --size_cost: -- /* This is section for size cost model. */ -+ default: -+ *total = COSTS_N_INSNS (3); -+ return true; -+ } -+} - -+static bool -+nds32_rtx_costs_size_prefer (rtx x, -+ int code, -+ int outer_code, -+ int opno ATTRIBUTE_UNUSED, -+ int *total) -+{ - /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4. - We treat it as 4-byte cost for each instruction - under code size consideration. */ -@@ -118,85 +431,162 @@ - (set X imm20s), use movi, 4-byte cost. - (set X BIG_INT), use sethi/ori, 8-byte cost. */ - if (satisfies_constraint_Is05 (x)) -- *total = COSTS_N_INSNS (1) - 2; -+ *total = insn_size_16bit; - else if (satisfies_constraint_Is20 (x)) -- *total = COSTS_N_INSNS (1); -+ *total = insn_size_32bit; - else -- *total = COSTS_N_INSNS (2); -+ *total = insn_size_32bit * 2; - } - else if (outer_code == PLUS || outer_code == MINUS) - { - /* Possible addi333/subi333 or subi45/addi45, 2-byte cost. - General case, cost 1 instruction with 4-byte. */ - if (satisfies_constraint_Iu05 (x)) -- *total = COSTS_N_INSNS (1) - 2; -+ *total = insn_size_16bit; - else -- *total = COSTS_N_INSNS (1); -+ *total = insn_size_32bit; - } - else if (outer_code == ASHIFT) - { - /* Possible slli333, 2-byte cost. - General case, cost 1 instruction with 4-byte. */ - if (satisfies_constraint_Iu03 (x)) -- *total = COSTS_N_INSNS (1) - 2; -+ *total = insn_size_16bit; - else -- *total = COSTS_N_INSNS (1); -+ *total = insn_size_32bit; - } - else if (outer_code == ASHIFTRT || outer_code == LSHIFTRT) - { - /* Possible srai45 or srli45, 2-byte cost. - General case, cost 1 instruction with 4-byte. */ - if (satisfies_constraint_Iu05 (x)) -- *total = COSTS_N_INSNS (1) - 2; -+ *total = insn_size_16bit; - else -- *total = COSTS_N_INSNS (1); -+ *total = insn_size_32bit; - } - else - { - /* For other cases, simply set it 4-byte cost. */ -- *total = COSTS_N_INSNS (1); -+ *total = insn_size_32bit; - } - break; - - case CONST_DOUBLE: - /* It requires high part and low part processing, set it 8-byte cost. */ -- *total = COSTS_N_INSNS (2); -+ *total = insn_size_32bit * 2; -+ break; -+ -+ case CONST: -+ case SYMBOL_REF: -+ *total = insn_size_32bit * 2; - break; - - default: - /* For other cases, generally we set it 4-byte cost -- and stop resurively traversing. */ -- *total = COSTS_N_INSNS (1); -+ and stop resurively traversing. */ -+ *total = insn_size_32bit; - break; - } - - return true; - } - --int --nds32_address_cost_impl (rtx address, -- machine_mode mode ATTRIBUTE_UNUSED, -- addr_space_t as ATTRIBUTE_UNUSED, -- bool speed) -+void -+nds32_init_rtx_costs (void) -+{ -+ rtx_cost_model.speed_prefer = nds32_rtx_costs_speed_prefer; -+ rtx_cost_model.size_prefer = nds32_rtx_costs_size_prefer; -+ -+ if (TARGET_16_BIT) -+ insn_size_16bit = 2; -+ else -+ insn_size_16bit = 4; -+} -+ -+/* This target hook describes the relative costs of RTL expressions. -+ Return 'true' when all subexpressions of x have been processed. -+ Return 'false' to sum the costs of sub-rtx, plus cost of this operation. -+ Refer to gcc/rtlanal.c for more information. */ -+bool -+nds32_rtx_costs_impl (rtx x, -+ machine_mode mode ATTRIBUTE_UNUSED, -+ int outer_code, -+ int opno, -+ int *total, -+ bool speed) -+{ -+ int code = GET_CODE (x); -+ -+ /* According to 'speed', use suitable cost model section. */ -+ if (speed) -+ return rtx_cost_model.speed_prefer(x, code, outer_code, opno, total); -+ else -+ return rtx_cost_model.size_prefer(x, code, outer_code, opno, total); -+} -+ -+ -+int nds32_address_cost_speed_prefer (rtx address) - { - rtx plus0, plus1; - enum rtx_code code; - - code = GET_CODE (address); - -- /* According to 'speed', goto suitable cost model section. */ -- if (speed) -- goto performance_cost; -- else -- goto size_cost; -+ switch (code) -+ { -+ case POST_MODIFY: -+ case POST_INC: -+ case POST_DEC: -+ /* We encourage that rtx contains -+ POST_MODIFY/POST_INC/POST_DEC behavior. */ -+ return COSTS_N_INSNS (1) - 2; -+ -+ case SYMBOL_REF: -+ /* We can have gp-relative load/store for symbol_ref. -+ Have it 4-byte cost. */ -+ return COSTS_N_INSNS (2); -+ -+ case CONST: -+ /* It is supposed to be the pattern (const (plus symbol_ref const_int)). -+ Have it 4-byte cost. */ -+ return COSTS_N_INSNS (2); -+ -+ case REG: -+ /* Simply return 4-byte costs. */ -+ return COSTS_N_INSNS (1) - 2; -+ -+ case PLUS: -+ /* We do not need to check if the address is a legitimate address, -+ because this hook is never called with an invalid address. -+ But we better check the range of -+ const_int value for cost, if it exists. */ -+ plus0 = XEXP (address, 0); -+ plus1 = XEXP (address, 1); - --performance_cost: -- /* This is section for performance cost model. */ -+ if (REG_P (plus0) && CONST_INT_P (plus1)) -+ return COSTS_N_INSNS (1) - 2; -+ else if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1)) -+ return COSTS_N_INSNS (1) - 1; -+ else if (REG_P (plus0) && REG_P (plus1)) -+ return COSTS_N_INSNS (1); - -- /* FALLTHRU, currently we use same cost model as size_cost. */ -+ /* For other 'plus' situation, make it cost 4-byte. */ -+ return COSTS_N_INSNS (1); - --size_cost: -- /* This is section for size cost model. */ -+ default: -+ break; -+ } -+ -+ return COSTS_N_INSNS (4); -+ -+} -+ -+int nds32_address_cost_speed_fwprop (rtx address) -+{ -+ rtx plus0, plus1; -+ enum rtx_code code; -+ -+ code = GET_CODE (address); - - switch (code) - { -@@ -210,12 +600,12 @@ - case SYMBOL_REF: - /* We can have gp-relative load/store for symbol_ref. - Have it 4-byte cost. */ -- return COSTS_N_INSNS (1); -+ return COSTS_N_INSNS (2); - - case CONST: - /* It is supposed to be the pattern (const (plus symbol_ref const_int)). - Have it 4-byte cost. */ -- return COSTS_N_INSNS (1); -+ return COSTS_N_INSNS (2); - - case REG: - /* Simply return 4-byte costs. */ -@@ -233,11 +623,78 @@ - { - /* If it is possible to be lwi333/swi333 form, - make it 2-byte cost. */ -- if (satisfies_constraint_Iu05 (plus1)) -+ if (satisfies_constraint_Iu03 (plus1)) - return (COSTS_N_INSNS (1) - 2); - else - return COSTS_N_INSNS (1); - } -+ if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1)) -+ return COSTS_N_INSNS (1) - 2; -+ else if (REG_P (plus0) && REG_P (plus1)) -+ return COSTS_N_INSNS (1); -+ -+ /* For other 'plus' situation, make it cost 4-byte. */ -+ return COSTS_N_INSNS (1); -+ -+ default: -+ break; -+ } -+ -+ return COSTS_N_INSNS (4); -+} -+ -+ -+int nds32_address_cost_size_prefer (rtx address) -+{ -+ rtx plus0, plus1; -+ enum rtx_code code; -+ -+ code = GET_CODE (address); -+ -+ switch (code) -+ { -+ case POST_MODIFY: -+ case POST_INC: -+ case POST_DEC: -+ /* We encourage that rtx contains -+ POST_MODIFY/POST_INC/POST_DEC behavior. */ -+ return 0; -+ -+ case SYMBOL_REF: -+ /* We can have gp-relative load/store for symbol_ref. -+ Have it 4-byte cost. */ -+ return COSTS_N_INSNS (2); -+ -+ case CONST: -+ /* It is supposed to be the pattern (const (plus symbol_ref const_int)). -+ Have it 4-byte cost. */ -+ return COSTS_N_INSNS (2); -+ -+ case REG: -+ /* Simply return 4-byte costs. */ -+ return COSTS_N_INSNS (1) - 1; -+ -+ case PLUS: -+ /* We do not need to check if the address is a legitimate address, -+ because this hook is never called with an invalid address. -+ But we better check the range of -+ const_int value for cost, if it exists. */ -+ plus0 = XEXP (address, 0); -+ plus1 = XEXP (address, 1); -+ -+ if (REG_P (plus0) && CONST_INT_P (plus1)) -+ { -+ /* If it is possible to be lwi333/swi333 form, -+ make it 2-byte cost. */ -+ if (satisfies_constraint_Iu03 (plus1)) -+ return (COSTS_N_INSNS (1) - 2); -+ else -+ return COSTS_N_INSNS (1) - 1; -+ } -+ -+ /* (plus (reg) (mult (reg) (const))) */ -+ if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1)) -+ return (COSTS_N_INSNS (1) - 1); - - /* For other 'plus' situation, make it cost 4-byte. */ - return COSTS_N_INSNS (1); -@@ -247,6 +704,23 @@ - } - - return COSTS_N_INSNS (4); -+ -+} -+ -+int nds32_address_cost_impl (rtx address, -+ machine_mode mode ATTRIBUTE_UNUSED, -+ addr_space_t as ATTRIBUTE_UNUSED, -+ bool speed_p) -+{ -+ if (speed_p) -+ { -+ if (current_pass->tv_id == TV_FWPROP) -+ return nds32_address_cost_speed_fwprop (address); -+ else -+ return nds32_address_cost_speed_prefer (address); -+ } -+ else -+ return nds32_address_cost_size_prefer (address); - } - - /* ------------------------------------------------------------------------ */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-doubleword.md gcc-8.2.0/gcc/config/nds32/nds32-doubleword.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-doubleword.md 2018-05-07 04:09:58.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-doubleword.md 2019-01-25 15:38:32.821242637 +0100 -@@ -136,10 +136,28 @@ - } - ) - -+;; Split move_di pattern when the hard register is odd. -+(define_split -+ [(set (match_operand:DIDF 0 "register_operand" "") -+ (match_operand:DIDF 1 "register_operand" ""))] -+ "(NDS32_IS_GPR_REGNUM (REGNO (operands[0])) -+ && ((REGNO (operands[0]) & 0x1) == 1)) -+ || (NDS32_IS_GPR_REGNUM (REGNO (operands[1])) -+ && ((REGNO (operands[1]) & 0x1) == 1))" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ } -+) -+ - (define_split - [(set (match_operand:DIDF 0 "register_operand" "") - (match_operand:DIDF 1 "const_double_operand" ""))] -- "reload_completed" -+ "flag_pic || reload_completed" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] - { -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-dspext.md gcc-8.2.0/gcc/config/nds32/nds32-dspext.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-dspext.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-dspext.md 2019-01-25 15:38:32.825242648 +0100 -@@ -0,0 +1,5278 @@ -+;; Machine description of Andes NDS32 cpu for GNU compiler -+;; Copyright (C) 2012-2018 Free Software Foundation, Inc. -+;; Contributed by Andes Technology Corporation. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published -+;; by the Free Software Foundation; either version 3, or (at your -+;; option) any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but WITHOUT -+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+;; License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_expand "mov" -+ [(set (match_operand:VQIHI 0 "general_operand" "") -+ (match_operand:VQIHI 1 "general_operand" ""))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ /* Need to force register if mem <- !reg. */ -+ if (MEM_P (operands[0]) && !REG_P (operands[1])) -+ operands[1] = force_reg (mode, operands[1]); -+ -+ /* If operands[1] is a large constant and cannot be performed -+ by a single instruction, we need to split it. */ -+ if (GET_CODE (operands[1]) == CONST_VECTOR -+ && !satisfies_constraint_CVs2 (operands[1]) -+ && !satisfies_constraint_CVhi (operands[1])) -+ { -+ HOST_WIDE_INT ival = const_vector_to_hwint (operands[1]); -+ rtx tmp_rtx; -+ -+ tmp_rtx = can_create_pseudo_p () -+ ? gen_reg_rtx (SImode) -+ : simplify_gen_subreg (SImode, operands[0], mode, 0); -+ -+ emit_move_insn (tmp_rtx, gen_int_mode (ival, SImode)); -+ convert_move (operands[0], tmp_rtx, false); -+ DONE; -+ } -+ -+ if (REG_P (operands[0]) && SYMBOLIC_CONST_P (operands[1])) -+ { -+ if (nds32_tls_referenced_p (operands [1])) -+ { -+ nds32_expand_tls_move (operands); -+ DONE; -+ } -+ else if (flag_pic) -+ { -+ nds32_expand_pic_move (operands); -+ DONE; -+ } -+ } -+}) -+ -+(define_insn "*mov" -+ [(set (match_operand:VQIHI 0 "nonimmediate_operand" "=r, r,$U45,$U33,$U37,$U45, m,$ l,$ l,$ l,$ d, d, r,$ d, r, r, r, *f, *f, r, *f, Q") -+ (match_operand:VQIHI 1 "nds32_vmove_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45,Ufe, m, CVp5, CVs5, CVs2, CVhi, *f, r, *f, Q, *f"))] -+ "NDS32_EXT_DSP_P () -+ && (register_operand(operands[0], mode) -+ || register_operand(operands[1], mode))" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "mov55\t%0, %1"; -+ case 1: -+ return "ori\t%0, %1, 0"; -+ case 2: -+ case 3: -+ case 4: -+ case 5: -+ return nds32_output_16bit_store (operands, ); -+ case 6: -+ return nds32_output_32bit_store (operands, ); -+ case 7: -+ case 8: -+ case 9: -+ case 10: -+ case 11: -+ return nds32_output_16bit_load (operands, ); -+ case 12: -+ return nds32_output_32bit_load (operands, ); -+ case 13: -+ return "movpi45\t%0, %1"; -+ case 14: -+ return "movi55\t%0, %1"; -+ case 15: -+ return "movi\t%0, %1"; -+ case 16: -+ return "sethi\t%0, hi20(%1)"; -+ case 17: -+ if (TARGET_FPU_SINGLE) -+ return "fcpyss\t%0, %1, %1"; -+ else -+ return "#"; -+ case 18: -+ return "fmtsr\t%1, %0"; -+ case 19: -+ return "fmfsr\t%0, %1"; -+ case 20: -+ return nds32_output_float_load (operands); -+ case 21: -+ return nds32_output_float_store (operands); -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,load,alu,alu,alu,alu,fcpy,fmtsr,fmfsr,fload,fstore") -+ (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 4, 2, 2, 4, 4, 4, 4, 4, 4, 4") -+ (set_attr "feature" " v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v3m, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")]) -+ -+(define_expand "movv2si" -+ [(set (match_operand:V2SI 0 "general_operand" "") -+ (match_operand:V2SI 1 "general_operand" ""))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ /* Need to force register if mem <- !reg. */ -+ if (MEM_P (operands[0]) && !REG_P (operands[1])) -+ operands[1] = force_reg (V2SImode, operands[1]); -+}) -+ -+(define_insn "*movv2si" -+ [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r, r, r, r, Da, m, f, Q, f, r, f") -+ (match_operand:V2SI 1 "general_operand" " r, i, Da, m, r, r, Q, f, f, f, r"))] -+ "NDS32_EXT_DSP_P () -+ && (register_operand(operands[0], V2SImode) -+ || register_operand(operands[1], V2SImode))" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "movd44\t%0, %1"; -+ case 1: -+ /* reg <- const_int, we ask gcc to split instruction. */ -+ return "#"; -+ case 2: -+ /* The memory format is (mem (reg)), -+ we can generate 'lmw.bi' instruction. */ -+ return nds32_output_double (operands, true); -+ case 3: -+ /* We haven't 64-bit load instruction, -+ we split this pattern to two SImode pattern. */ -+ return "#"; -+ case 4: -+ /* The memory format is (mem (reg)), -+ we can generate 'smw.bi' instruction. */ -+ return nds32_output_double (operands, false); -+ case 5: -+ /* We haven't 64-bit store instruction, -+ we split this pattern to two SImode pattern. */ -+ return "#"; -+ case 6: -+ return nds32_output_float_load (operands); -+ case 7: -+ return nds32_output_float_store (operands); -+ case 8: -+ return "fcpysd\t%0, %1, %1"; -+ case 9: -+ return "fmfdr\t%0, %1"; -+ case 10: -+ return "fmtdr\t%1, %0"; -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu,alu,load,load,store,store,unknown,unknown,unknown,unknown,unknown") -+ (set_attr_alternative "length" -+ [ -+ ;; Alternative 0 -+ (if_then_else (match_test "!TARGET_16_BIT") -+ (const_int 4) -+ (const_int 2)) -+ ;; Alternative 1 -+ (const_int 16) -+ ;; Alternative 2 -+ (const_int 4) -+ ;; Alternative 3 -+ (const_int 8) -+ ;; Alternative 4 -+ (const_int 4) -+ ;; Alternative 5 -+ (const_int 8) -+ ;; Alternative 6 -+ (const_int 4) -+ ;; Alternative 7 -+ (const_int 4) -+ ;; Alternative 8 -+ (const_int 4) -+ ;; Alternative 9 -+ (const_int 4) -+ ;; Alternative 10 -+ (const_int 4) -+ ]) -+ (set_attr "feature" " v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")]) -+ -+(define_expand "movmisalign" -+ [(set (match_operand:VQIHI 0 "general_operand" "") -+ (match_operand:VQIHI 1 "general_operand" ""))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ rtx addr; -+ if (MEM_P (operands[0]) && !REG_P (operands[1])) -+ operands[1] = force_reg (mode, operands[1]); -+ -+ if (MEM_P (operands[0])) -+ { -+ addr = force_reg (Pmode, XEXP (operands[0], 0)); -+ emit_insn (gen_unaligned_store (addr, operands[1])); -+ } -+ else -+ { -+ addr = force_reg (Pmode, XEXP (operands[1], 0)); -+ emit_insn (gen_unaligned_load (operands[0], addr)); -+ } -+ DONE; -+}) -+ -+(define_expand "unaligned_load" -+ [(set (match_operand:VQIHI 0 "register_operand" "=r") -+ (unspec:VQIHI [(mem:VQIHI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_ISA_V3M) -+ nds32_expand_unaligned_load (operands, mode); -+ else -+ emit_insn (gen_unaligned_load_w (operands[0], gen_rtx_MEM (mode, operands[1]))); -+ DONE; -+}) -+ -+(define_insn "unaligned_load_w" -+ [(set (match_operand:VQIHI 0 "register_operand" "= r") -+ (unspec:VQIHI [(match_operand:VQIHI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ return nds32_output_lmw_single_word (operands); -+} -+ [(set_attr "type" "load") -+ (set_attr "length" "4")] -+) -+ -+(define_expand "unaligned_store" -+ [(set (mem:VQIHI (match_operand:SI 0 "register_operand" "r")) -+ (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" "r")] UNSPEC_UASTORE_W))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_ISA_V3M) -+ nds32_expand_unaligned_store (operands, mode); -+ else -+ emit_insn (gen_unaligned_store_w (gen_rtx_MEM (mode, operands[0]), operands[1])); -+ DONE; -+}) -+ -+(define_insn "unaligned_store_w" -+ [(set (match_operand:VQIHI 0 "nds32_lmw_smw_base_operand" "=Umw") -+ (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" " r")] UNSPEC_UASTORE_W))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ return nds32_output_smw_single_word (operands); -+} -+ [(set_attr "type" "store") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "add3" -+ [(set (match_operand:VQIHI 0 "register_operand" "=r") -+ (all_plus:VQIHI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "add %0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "adddi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (all_plus:DI (match_operand:DI 1 "register_operand" " r") -+ (match_operand:DI 2 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "add64 %0, %1, %2" -+ [(set_attr "type" "dalu64") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "raddv4qi3" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (truncate:V4QI -+ (ashiftrt:V4HI -+ (plus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) -+ (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "radd8\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+ -+(define_insn "uraddv4qi3" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (truncate:V4QI -+ (lshiftrt:V4HI -+ (plus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) -+ (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "uradd8\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "raddv2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (truncate:V2HI -+ (ashiftrt:V2SI -+ (plus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) -+ (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "radd16\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "uraddv2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (truncate:V2HI -+ (lshiftrt:V2SI -+ (plus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) -+ (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "uradd16\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "radddi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (ashiftrt:TI -+ (plus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r")) -+ (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "radd64\t%0, %1, %2" -+ [(set_attr "type" "dalu64") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+ -+(define_insn "uradddi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (lshiftrt:TI -+ (plus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r")) -+ (zero_extend:TI (match_operand:DI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "uradd64\t%0, %1, %2" -+ [(set_attr "type" "dalu64") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "sub3" -+ [(set (match_operand:VQIHI 0 "register_operand" "=r") -+ (all_minus:VQIHI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "sub %0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (all_minus:DI (match_operand:DI 1 "register_operand" " r") -+ (match_operand:DI 2 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "sub64 %0, %1, %2" -+ [(set_attr "type" "dalu64") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+(define_insn "rsubv4qi3" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (truncate:V4QI -+ (ashiftrt:V4HI -+ (minus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) -+ (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "rsub8\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "ursubv4qi3" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (truncate:V4QI -+ (lshiftrt:V4HI -+ (minus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) -+ (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "ursub8\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rsubv2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (truncate:V2HI -+ (ashiftrt:V2SI -+ (minus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) -+ (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "rsub16\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "ursubv2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (truncate:V2HI -+ (lshiftrt:V2SI -+ (minus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) -+ (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "ursub16\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rsubdi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (ashiftrt:TI -+ (minus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r")) -+ (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "rsub64\t%0, %1, %2" -+ [(set_attr "type" "dalu64") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "ursubdi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (lshiftrt:TI -+ (minus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r")) -+ (zero_extend:TI (match_operand:DI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "ursub64\t%0, %1, %2" -+ [(set_attr "type" "dalu64") -+ (set_attr "length" "4")]) -+ -+(define_expand "cras16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_cras16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_cras16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "cras16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (plus:HI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "cras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "cras16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (plus:HI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "cras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "kcras16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kcras16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_kcras16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "kcras16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (ss_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (ss_plus:HI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "kcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "kcras16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (ss_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (ss_plus:HI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "kcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "ukcras16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_ukcras16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_ukcras16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "ukcras16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (us_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (us_plus:HI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "ukcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "ukcras16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (us_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (us_plus:HI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "ukcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "crsa16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_crsa16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_crsa16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "crsa16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (plus:HI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "crsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "crsa16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (plus:HI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "crsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "kcrsa16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kcrsa16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_kcrsa16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "kcrsa16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (ss_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (ss_plus:HI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "kcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "kcrsa16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (ss_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (ss_plus:HI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "kcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "ukcrsa16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_ukcrsa16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_ukcrsa16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "ukcrsa16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (us_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (us_plus:HI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "ukcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "ukcrsa16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (us_minus:HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (us_plus:HI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "ukcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "rcras16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_rcras16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_rcras16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "rcras16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (minus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (plus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "rcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "rcras16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (minus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (plus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "rcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "urcras16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_urcras16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_urcras16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "urcras16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (minus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (plus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "urcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "urcras16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (minus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (plus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "urcras16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "rcrsa16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_rcrsa16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_rcrsa16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "rcrsa16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (minus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (plus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "rcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "rcrsa16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (minus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (ashiftrt:SI -+ (plus:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "rcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "urcrsa16_1" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_urcrsa16_1_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_urcrsa16_1_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_insn "urcrsa16_1_le" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (minus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (plus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "urcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_insn "urcrsa16_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (minus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (const_int 1)))) -+ (vec_duplicate:V2HI -+ (truncate:HI -+ (lshiftrt:SI -+ (plus:SI -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)]))) -+ (zero_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])))) -+ (const_int 1)))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "urcrsa16\t%0, %1, %2" -+ [(set_attr "type" "dalu")] -+) -+ -+(define_expand "v2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "") -+ (shifts:V2HI (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:SI 2 "nds32_rimm4u_operand" "")))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (operands[2] == const0_rtx) -+ { -+ emit_move_insn (operands[0], operands[1]); -+ DONE; -+ } -+}) -+ -+(define_insn "*ashlv2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ slli16\t%0, %1, %2 -+ sll16\t%0, %1, %2" -+ [(set_attr "type" "dalu,dalu") -+ (set_attr "length" " 4, 4")]) -+ -+(define_insn "kslli16" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (ss_ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ kslli16\t%0, %1, %2 -+ ksll16\t%0, %1, %2" -+ [(set_attr "type" "dalu,dalu") -+ (set_attr "length" " 4, 4")]) -+ -+(define_insn "*ashrv2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ srai16\t%0, %1, %2 -+ sra16\t%0, %1, %2" -+ [(set_attr "type" "dalu,dalu") -+ (set_attr "length" " 4, 4")]) -+ -+(define_insn "sra16_round" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))] -+ UNSPEC_ROUND))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ srai16.u\t%0, %1, %2 -+ sra16.u\t%0, %1, %2" -+ [(set_attr "type" "daluround,daluround") -+ (set_attr "length" " 4, 4")]) -+ -+(define_insn "*lshrv2hi3" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ srli16\t%0, %1, %2 -+ srl16\t%0, %1, %2" -+ [(set_attr "type" "dalu,dalu") -+ (set_attr "length" " 4, 4")]) -+ -+(define_insn "srl16_round" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (unspec:V2HI [(lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))] -+ UNSPEC_ROUND))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ srli16.u\t%0, %1, %2 -+ srl16.u\t%0, %1, %2" -+ [(set_attr "type" "daluround,daluround") -+ (set_attr "length" " 4, 4")]) -+ -+(define_insn "kslra16" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (if_then_else:V2HI -+ (lt:SI (match_operand:SI 2 "register_operand" " r") -+ (const_int 0)) -+ (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r") -+ (neg:SI (match_dup 2))) -+ (ashift:V2HI (match_dup 1) -+ (match_dup 2))))] -+ "NDS32_EXT_DSP_P ()" -+ "kslra16\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "kslra16_round" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (if_then_else:V2HI -+ (lt:SI (match_operand:SI 2 "register_operand" " r") -+ (const_int 0)) -+ (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r") -+ (neg:SI (match_dup 2)))] -+ UNSPEC_ROUND) -+ (ashift:V2HI (match_dup 1) -+ (match_dup 2))))] -+ "NDS32_EXT_DSP_P ()" -+ "kslra16.u\t%0, %1, %2" -+ [(set_attr "type" "daluround") -+ (set_attr "length" "4")]) -+ -+(define_insn "cmpeq" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(eq:SI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r"))] -+ UNSPEC_VEC_COMPARE))] -+ "NDS32_EXT_DSP_P ()" -+ "cmpeq\t%0, %1, %2" -+ [(set_attr "type" "dcmp") -+ (set_attr "length" "4")]) -+ -+(define_insn "scmplt" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(lt:SI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r"))] -+ UNSPEC_VEC_COMPARE))] -+ "NDS32_EXT_DSP_P ()" -+ "scmplt\t%0, %1, %2" -+ [(set_attr "type" "dcmp") -+ (set_attr "length" "4")]) -+ -+(define_insn "scmple" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(le:SI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r"))] -+ UNSPEC_VEC_COMPARE))] -+ "NDS32_EXT_DSP_P ()" -+ "scmple\t%0, %1, %2" -+ [(set_attr "type" "dcmp") -+ (set_attr "length" "4")]) -+ -+(define_insn "ucmplt" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(ltu:SI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r"))] -+ UNSPEC_VEC_COMPARE))] -+ "NDS32_EXT_DSP_P ()" -+ "ucmplt\t%0, %1, %2" -+ [(set_attr "type" "dcmp") -+ (set_attr "length" "4")]) -+ -+(define_insn "ucmple" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(leu:SI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r"))] -+ UNSPEC_VEC_COMPARE))] -+ "NDS32_EXT_DSP_P ()" -+ "ucmple\t%0, %1, %2" -+ [(set_attr "type" "dcmp") -+ (set_attr "length" "4")]) -+ -+(define_insn "sclip16" -+ [(set (match_operand:V2HI 0 "register_operand" "= r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") -+ (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")] -+ UNSPEC_CLIPS))] -+ "NDS32_EXT_DSP_P ()" -+ "sclip16\t%0, %1, %2" -+ [(set_attr "type" "dclip") -+ (set_attr "length" "4")]) -+ -+(define_insn "uclip16" -+ [(set (match_operand:V2HI 0 "register_operand" "= r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") -+ (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")] -+ UNSPEC_CLIP))] -+ "NDS32_EXT_DSP_P ()" -+ "uclip16\t%0, %1, %2" -+ [(set_attr "type" "dclip") -+ (set_attr "length" "4")]) -+ -+(define_insn "khm16" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") -+ (match_operand:V2HI 2 "register_operand" " r")] -+ UNSPEC_KHM))] -+ "NDS32_EXT_DSP_P ()" -+ "khm16\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_insn "khmx16" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") -+ (match_operand:V2HI 2 "register_operand" " r")] -+ UNSPEC_KHMX))] -+ "NDS32_EXT_DSP_P ()" -+ "khmx16\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_expand "vec_setv4qi" -+ [(match_operand:V4QI 0 "register_operand" "") -+ (match_operand:QI 1 "register_operand" "") -+ (match_operand:SI 2 "immediate_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ HOST_WIDE_INT pos = INTVAL (operands[2]); -+ if (pos > 4) -+ gcc_unreachable (); -+ HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos; -+ emit_insn (gen_vec_setv4qi_internal (operands[0], operands[1], -+ operands[0], GEN_INT (elem))); -+ DONE; -+}) -+ -+(define_expand "insb" -+ [(match_operand:V4QI 0 "register_operand" "") -+ (match_operand:V4QI 1 "register_operand" "") -+ (match_operand:SI 2 "register_operand" "") -+ (match_operand:SI 3 "const_int_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (INTVAL (operands[3]) > 3 || INTVAL (operands[3]) < 0) -+ gcc_unreachable (); -+ -+ rtx src = gen_reg_rtx (QImode); -+ -+ convert_move (src, operands[2], false); -+ -+ HOST_WIDE_INT selector_index; -+ /* Big endian need reverse index. */ -+ if (TARGET_BIG_ENDIAN) -+ selector_index = 4 - INTVAL (operands[3]) - 1; -+ else -+ selector_index = INTVAL (operands[3]); -+ rtx selector = gen_int_mode (1 << selector_index, SImode); -+ emit_insn (gen_vec_setv4qi_internal (operands[0], src, -+ operands[1], selector)); -+ DONE; -+}) -+ -+(define_expand "insvsi" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "") -+ (match_operand:SI 2 "nds32_insv_operand" "")) -+ (match_operand:SI 3 "register_operand" ""))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (INTVAL (operands[1]) != 8) -+ FAIL; -+} -+ [(set_attr "type" "dinsb") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "insvsi_internal" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (const_int 8) -+ (match_operand:SI 1 "nds32_insv_operand" "i")) -+ (match_operand:SI 2 "register_operand" "r"))] -+ "NDS32_EXT_DSP_P ()" -+ "insb\t%0, %2, %v1" -+ [(set_attr "type" "dinsb") -+ (set_attr "length" "4")]) -+ -+(define_insn "insvsiqi_internal" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (const_int 8) -+ (match_operand:SI 1 "nds32_insv_operand" "i")) -+ (zero_extend:SI (match_operand:QI 2 "register_operand" "r")))] -+ "NDS32_EXT_DSP_P ()" -+ "insb\t%0, %2, %v1" -+ [(set_attr "type" "dinsb") -+ (set_attr "length" "4")]) -+ -+;; Intermedium pattern for synthetize insvsiqi_internal -+;; v0 = ((v1 & 0xff) << 8) -+(define_insn_and_split "and0xff_s8" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") -+ (const_int 8)) -+ (const_int 65280)))] -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (SImode); -+ emit_insn (gen_ashlsi3 (tmp, operands[1], gen_int_mode (8, SImode))); -+ emit_insn (gen_andsi3 (operands[0], tmp, gen_int_mode (0xffff, SImode))); -+ DONE; -+}) -+ -+;; v0 = (v1 & 0xff00ffff) | ((v2 << 16) | 0xff0000) -+(define_insn_and_split "insbsi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") -+ (const_int -16711681)) -+ (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") -+ (const_int 16)) -+ (const_int 16711680))))] -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (SImode); -+ emit_move_insn (tmp, operands[1]); -+ emit_insn (gen_insvsi_internal (tmp, gen_int_mode(16, SImode), operands[2])); -+ emit_move_insn (operands[0], tmp); -+ DONE; -+}) -+ -+;; v0 = (v1 & 0xff00ffff) | v2 -+(define_insn_and_split "ior_and0xff00ffff_reg" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") -+ (const_int -16711681)) -+ (match_operand:SI 2 "register_operand" "r")))] -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (SImode); -+ emit_insn (gen_andsi3 (tmp, operands[1], gen_int_mode (0xff00ffff, SImode))); -+ emit_insn (gen_iorsi3 (operands[0], tmp, operands[2])); -+ DONE; -+}) -+ -+(define_insn "vec_setv4qi_internal" -+ [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r") -+ (vec_merge:V4QI -+ (vec_duplicate:V4QI -+ (match_operand:QI 1 "register_operand" " r, r, r, r")) -+ (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0") -+ (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "insb\t%0, %1, 3", -+ "insb\t%0, %1, 2", -+ "insb\t%0, %1, 1", -+ "insb\t%0, %1, 0" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "insb\t%0, %1, 0", -+ "insb\t%0, %1, 1", -+ "insb\t%0, %1, 2", -+ "insb\t%0, %1, 3" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dinsb") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_setv4qi_internal_vec" -+ [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r") -+ (vec_merge:V4QI -+ (vec_duplicate:V4QI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r, r, r, r") -+ (parallel [(const_int 0)]))) -+ (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0") -+ (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ insb\t%0, %1, 0 -+ insb\t%0, %1, 1 -+ insb\t%0, %1, 2 -+ insb\t%0, %1, 3" -+ [(set_attr "type" "dinsb") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_mergev4qi_and_cv0_1" -+ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") -+ (vec_merge:V4QI -+ (vec_duplicate:V4QI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " l,r") -+ (parallel [(const_int 0)]))) -+ (const_vector:V4QI [ -+ (const_int 0) -+ (const_int 0) -+ (const_int 0) -+ (const_int 0)]) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeb33\t%0, %1 -+ zeb\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_mergev4qi_and_cv0_2" -+ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") -+ (vec_merge:V4QI -+ (const_vector:V4QI [ -+ (const_int 0) -+ (const_int 0) -+ (const_int 0) -+ (const_int 0)]) -+ (vec_duplicate:V4QI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " l,r") -+ (parallel [(const_int 0)]))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeb33\t%0, %1 -+ zeb\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_mergeqi_and_cv0_1" -+ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") -+ (vec_merge:V4QI -+ (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r")) -+ (const_vector:V4QI [ -+ (const_int 0) -+ (const_int 0) -+ (const_int 0) -+ (const_int 0)]) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeb33\t%0, %1 -+ zeb\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_mergeqi_and_cv0_2" -+ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") -+ (vec_merge:V4QI -+ (const_vector:V4QI [ -+ (const_int 0) -+ (const_int 0) -+ (const_int 0) -+ (const_int 0)]) -+ (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r")) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeb33\t%0, %1 -+ zeb\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_expand "vec_setv2hi" -+ [(match_operand:V2HI 0 "register_operand" "") -+ (match_operand:HI 1 "register_operand" "") -+ (match_operand:SI 2 "immediate_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ HOST_WIDE_INT pos = INTVAL (operands[2]); -+ if (pos > 2) -+ gcc_unreachable (); -+ HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos; -+ emit_insn (gen_vec_setv2hi_internal (operands[0], operands[1], -+ operands[0], GEN_INT (elem))); -+ DONE; -+}) -+ -+(define_insn "vec_setv2hi_internal" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (match_operand:HI 1 "register_operand" " r, r")) -+ (match_operand:V2HI 2 "register_operand" " r, r") -+ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "pkbb16\t%0, %1, %2", -+ "pktb16\t%0, %2, %1" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "pktb16\t%0, %2, %1", -+ "pkbb16\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_mergev2hi_and_cv0_1" -+ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " l,r") -+ (parallel [(const_int 0)]))) -+ (const_vector:V2HI [ -+ (const_int 0) -+ (const_int 0)]) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeh33\t%0, %1 -+ zeh\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_mergev2hi_and_cv0_2" -+ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") -+ (vec_merge:V2HI -+ (const_vector:V2HI [ -+ (const_int 0) -+ (const_int 0)]) -+ (vec_duplicate:V2HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " l,r") -+ (parallel [(const_int 0)]))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeh33\t%0, %1 -+ zeh\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_mergehi_and_cv0_1" -+ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r")) -+ (const_vector:V2HI [ -+ (const_int 0) -+ (const_int 0)]) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeh33\t%0, %1 -+ zeh\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_mergehi_and_cv0_2" -+ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") -+ (vec_merge:V2HI -+ (const_vector:V2HI [ -+ (const_int 0) -+ (const_int 0)]) -+ (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r")) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ zeh33\t%0, %1 -+ zeh\t%0, %1" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_expand "pkbb" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V2HI 1 "register_operand") -+ (match_operand:V2HI 2 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (1), GEN_INT (1), GEN_INT (1))); -+ } -+ else -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (2), GEN_INT (0), GEN_INT (0))); -+ } -+ DONE; -+}) -+ -+(define_insn "pkbbsi_1" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") -+ (const_int 65535)) -+ (ashift:SI (match_operand:SI 2 "register_operand" "r") -+ (const_int 16))))] -+ "NDS32_EXT_DSP_P ()" -+ "pkbb16\t%0, %2, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "pkbbsi_2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") -+ (const_int 16)) -+ (and:SI (match_operand:SI 1 "register_operand" "r") -+ (const_int 65535))))] -+ "NDS32_EXT_DSP_P ()" -+ "pkbb16\t%0, %2, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "pkbbsi_3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) -+ (ashift:SI (match_operand:SI 2 "register_operand" "r") -+ (const_int 16))))] -+ "NDS32_EXT_DSP_P ()" -+ "pkbb16\t%0, %2, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "pkbbsi_4" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") -+ (const_int 16)) -+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))))] -+ "NDS32_EXT_DSP_P ()" -+ "pkbb16\t%0, %2, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+;; v0 = (v1 & 0xffff0000) | (v2 & 0xffff) -+(define_insn "pktbsi_1" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") -+ (const_int -65536)) -+ (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] -+ "NDS32_EXT_DSP_P ()" -+ "pktb16\t%0, %1, %2" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "pktbsi_2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") -+ (const_int -65536)) -+ (and:SI (match_operand:SI 2 "register_operand" "r") -+ (const_int 65535))))] -+ "NDS32_EXT_DSP_P ()" -+ "pktb16\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "pktbsi_3" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (const_int 16 ) -+ (const_int 0)) -+ (match_operand:SI 1 "register_operand" " r"))] -+ "NDS32_EXT_DSP_P ()" -+ "pktb16\t%0, %0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "pktbsi_4" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (const_int 16 ) -+ (const_int 0)) -+ (zero_extend:SI (match_operand:HI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "pktb16\t%0, %0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "pkttsi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI (and:SI (match_operand:SI 1 "register_operand" " r") -+ (const_int -65536)) -+ (lshiftrt:SI (match_operand:SI 2 "register_operand" " r") -+ (const_int 16))))] -+ "NDS32_EXT_DSP_P ()" -+ "pktt16\t%0, %1, %2" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_expand "pkbt" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V2HI 1 "register_operand") -+ (match_operand:V2HI 2 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (1), GEN_INT (1), GEN_INT (0))); -+ } -+ else -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (2), GEN_INT (0), GEN_INT (1))); -+ } -+ DONE; -+}) -+ -+(define_expand "pktt" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V2HI 1 "register_operand") -+ (match_operand:V2HI 2 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (1), GEN_INT (0), GEN_INT (0))); -+ } -+ else -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (2), GEN_INT (1), GEN_INT (1))); -+ } -+ DONE; -+}) -+ -+(define_expand "pktb" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V2HI 1 "register_operand") -+ (match_operand:V2HI 2 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (1), GEN_INT (0), GEN_INT (1))); -+ } -+ else -+ { -+ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], -+ GEN_INT (2), GEN_INT (1), GEN_INT (0))); -+ } -+ DONE; -+}) -+ -+(define_insn "vec_mergerr" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (match_operand:HI 1 "register_operand" " r, r")) -+ (vec_duplicate:V2HI -+ (match_operand:HI 2 "register_operand" " r, r")) -+ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ pkbb16\t%0, %2, %1 -+ pkbb16\t%0, %1, %2" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "vec_merge" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r") -+ (vec_merge:V2HI -+ (match_operand:V2HI 1 "register_operand" " r, r") -+ (match_operand:V2HI 2 "register_operand" " r, r") -+ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "pktb16\t%0, %1, %2", -+ "pktb16\t%0, %2, %1" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "pktb16\t%0, %2, %1", -+ "pktb16\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_mergerv" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (match_operand:HI 1 "register_operand" " r, r, r, r")) -+ (vec_duplicate:V2HI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")]))) -+ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ pkbb16\t%0, %2, %1 -+ pktb16\t%0, %2, %1 -+ pkbb16\t%0, %1, %2 -+ pkbt16\t%0, %1, %2" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_mergevr" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")]))) -+ (vec_duplicate:V2HI -+ (match_operand:HI 2 "register_operand" " r, r, r, r")) -+ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ pkbb16\t%0, %2, %1 -+ pkbt16\t%0, %2, %1 -+ pkbb16\t%0, %1, %2 -+ pktb16\t%0, %1, %2" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_mergevv" -+ [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r, r, r, r, r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r, r, r, r, r, r, r, r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01")]))) -+ (vec_duplicate:V2HI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r, r, r, r, r, r, r") -+ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01, Iv00")]))) -+ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv01, Iv01, Iv02, Iv02, Iv02, Iv02")))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "pktt16\t%0, %1, %2", -+ "pktb16\t%0, %1, %2", -+ "pkbb16\t%0, %1, %2", -+ "pkbt16\t%0, %1, %2", -+ "pktt16\t%0, %2, %1", -+ "pkbt16\t%0, %2, %1", -+ "pkbb16\t%0, %2, %1", -+ "pktb16\t%0, %2, %1" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "pkbb16\t%0, %2, %1", -+ "pktb16\t%0, %2, %1", -+ "pktt16\t%0, %2, %1", -+ "pkbt16\t%0, %2, %1", -+ "pkbb16\t%0, %1, %2", -+ "pkbt16\t%0, %1, %2", -+ "pktt16\t%0, %1, %2", -+ "pktb16\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_expand "vec_extractv4qi" -+ [(set (match_operand:QI 0 "register_operand" "") -+ (vec_select:QI -+ (match_operand:V4QI 1 "nonimmediate_operand" "") -+ (parallel [(match_operand:SI 2 "const_int_operand" "")])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ if (INTVAL (operands[2]) != 0 -+ && INTVAL (operands[2]) != 1 -+ && INTVAL (operands[2]) != 2 -+ && INTVAL (operands[2]) != 3) -+ gcc_unreachable (); -+ -+ if (INTVAL (operands[2]) != 0 && MEM_P (operands[0])) -+ FAIL; -+}) -+ -+(define_insn "vec_extractv4qi0" -+ [(set (match_operand:QI 0 "register_operand" "=l,r,r") -+ (vec_select:QI -+ (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") -+ (parallel [(const_int 0)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "zeb33\t%0, %1"; -+ case 1: -+ return "zeb\t%0, %1"; -+ case 2: -+ return nds32_output_32bit_load (operands, 1); -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_extractv4qi0_ze" -+ [(set (match_operand:SI 0 "register_operand" "=l,r,r") -+ (zero_extend:SI -+ (vec_select:QI -+ (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") -+ (parallel [(const_int 0)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "zeb33\t%0, %1"; -+ case 1: -+ return "zeb\t%0, %1"; -+ case 2: -+ return nds32_output_32bit_load (operands, 1); -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_extractv4qi0_se" -+ [(set (match_operand:SI 0 "register_operand" "=l,r,r") -+ (sign_extend:SI -+ (vec_select:QI -+ (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") -+ (parallel [(const_int 0)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "seb33\t%0, %1"; -+ case 1: -+ return "seb\t%0, %1"; -+ case 2: -+ return nds32_output_32bit_load_s (operands, 1); -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "vec_extractv4qi1" -+ [(set (match_operand:QI 0 "register_operand" "=r") -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 1)])))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (V4QImode); -+ emit_insn (gen_rotrv4qi_1 (tmp, operands[1])); -+ emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "vec_extractv4qi2" -+ [(set (match_operand:QI 0 "register_operand" "=r") -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2)])))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (V4QImode); -+ emit_insn (gen_rotrv4qi_2 (tmp, operands[1])); -+ emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "vec_extractv4qi3" -+ [(set (match_operand:QI 0 "register_operand" "=r") -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)])))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (V4QImode); -+ emit_insn (gen_rotrv4qi_3 (tmp, operands[1])); -+ emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "vec_extractv4qi3_se" -+ [(set (match_operand:SI 0 "register_operand" "=$d,r") -+ (sign_extend:SI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " 0,r") -+ (parallel [(const_int 3)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ srai45\t%0, 24 -+ srai\t%0, %1, 24" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_extractv4qi3_ze" -+ [(set (match_operand:SI 0 "register_operand" "=$d,r") -+ (zero_extend:SI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " 0,r") -+ (parallel [(const_int 3)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ srli45\t%0, 24 -+ srli\t%0, %1, 24" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn_and_split "vec_extractv4qihi0" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (QImode); -+ emit_insn (gen_vec_extractv4qi0 (tmp, operands[1])); -+ emit_insn (gen_extendqihi2 (operands[0], tmp)); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "vec_extractv4qihi1" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (QImode); -+ emit_insn (gen_vec_extractv4qi1 (tmp, operands[1])); -+ emit_insn (gen_extendqihi2 (operands[0], tmp)); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "vec_extractv4qihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2)]))))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (QImode); -+ emit_insn (gen_vec_extractv4qi2 (tmp, operands[1])); -+ emit_insn (gen_extendqihi2 (operands[0], tmp)); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "vec_extractv4qihi3" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)]))))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx tmp = gen_reg_rtx (QImode); -+ emit_insn (gen_vec_extractv4qi3 (tmp, operands[1])); -+ emit_insn (gen_extendqihi2 (operands[0], tmp)); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_expand "vec_extractv2hi" -+ [(set (match_operand:HI 0 "register_operand" "") -+ (vec_select:HI -+ (match_operand:V2HI 1 "nonimmediate_operand" "") -+ (parallel [(match_operand:SI 2 "const_int_operand" "")])))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (INTVAL (operands[2]) != 0 -+ && INTVAL (operands[2]) != 1) -+ gcc_unreachable (); -+ -+ if (INTVAL (operands[2]) != 0 && MEM_P (operands[0])) -+ FAIL; -+}) -+ -+(define_insn "vec_extractv2hi0" -+ [(set (match_operand:HI 0 "register_operand" "=$l,r,r") -+ (vec_select:HI -+ (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") -+ (parallel [(const_int 0)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "seh33\t%0, %1"; -+ case 1: -+ return "seh\t%0, %1"; -+ case 2: -+ return nds32_output_32bit_load_s (operands, 2); -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu,alu,load") -+ (set_attr "length" " 2, 4, 4")]) -+ -+(define_insn "vec_extractv2hi0_ze" -+ [(set (match_operand:SI 0 "register_operand" "=$l, r,$ l, *r") -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "nonimmediate_operand" " l, r, U33, m") -+ (parallel [(const_int 0)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "zeh33\t%0, %1"; -+ case 1: -+ return "zeh\t%0, %1"; -+ case 2: -+ return nds32_output_16bit_load (operands, 2); -+ case 3: -+ return nds32_output_32bit_load (operands, 2); -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu,alu,load,load") -+ (set_attr "length" " 2, 4, 2, 4")]) -+ -+(define_insn "vec_extractv2hi0_se" -+ [(set (match_operand:SI 0 "register_operand" "=$l, r, r") -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") -+ (parallel [(const_int 0)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "seh33\t%0, %1"; -+ case 1: -+ return "seh\t%0, %1"; -+ case 2: -+ return nds32_output_32bit_load_s (operands, 2); -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu,alu,load") -+ (set_attr "length" " 2, 4, 4")]) -+ -+(define_insn "vec_extractv2hi0_be" -+ [(set (match_operand:HI 0 "register_operand" "=$d,r") -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " 0,r") -+ (parallel [(const_int 0)])))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "@ -+ srai45\t%0, 16 -+ srai\t%0, %1, 16" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_extractv2hi1" -+ [(set (match_operand:HI 0 "register_operand" "=$d,r") -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " 0,r") -+ (parallel [(const_int 1)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ srai45\t%0, 16 -+ srai\t%0, %1, 16" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_extractv2hi1_se" -+ [(set (match_operand:SI 0 "register_operand" "=$d,r") -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " 0,r") -+ (parallel [(const_int 1)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ srai45\t%0, 16 -+ srai\t%0, %1, 16" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_extractv2hi1_ze" -+ [(set (match_operand:SI 0 "register_operand" "=$d,r") -+ (zero_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " 0,r") -+ (parallel [(const_int 1)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "@ -+ srli45\t%0, 16 -+ srli\t%0, %1, 16" -+ [(set_attr "type" "alu,alu") -+ (set_attr "length" " 2, 4")]) -+ -+(define_insn "vec_extractv2hi1_be" -+ [(set (match_operand:HI 0 "register_operand" "=$l,r,r") -+ (vec_select:HI -+ (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") -+ (parallel [(const_int 1)])))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+{ -+ switch (which_alternative) -+ { -+ case 0: -+ return "seh33\t%0, %1"; -+ case 1: -+ return "seh\t%0, %1"; -+ case 2: -+ return nds32_output_32bit_load_s (operands, 2); -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ [(set_attr "type" "alu,alu,load") -+ (set_attr "length" " 2, 4, 4")]) -+ -+(define_insn "mul16" -+ [(set (match_operand:V2SI 0 "register_operand" "=r") -+ (mult:V2SI (extend:V2SI (match_operand:V2HI 1 "register_operand" "%r")) -+ (extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))))] -+ "NDS32_EXT_DSP_P ()" -+ "mul16\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_insn "mulx16" -+ [(set (match_operand:V2SI 0 "register_operand" "=r") -+ (vec_merge:V2SI -+ (vec_duplicate:V2SI -+ (mult:SI -+ (extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))))) -+ (vec_duplicate:V2SI -+ (mult:SI -+ (extend:SI -+ (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)]))) -+ (extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P ()" -+ "mulx16\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv2hi_1" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_select:V2HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1) (const_int 0)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 16" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv2hi_1_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_select:V2HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0) (const_int 1)])))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 16" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv4qi_1" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 0)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 8" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv4qi_1_be" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2) (const_int 1) (const_int 0) (const_int 3)])))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 8" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv4qi_2" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 16" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv4qi_2_be" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 16" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv4qi_3" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3) (const_int 0) (const_int 1) (const_int 2)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 24" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "rotrv4qi_3_be" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0) (const_int 3) (const_int 2) (const_int 1)])))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "rotri\t%0, %1, 24" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "v4qi_dup_10" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0) (const_int 1) (const_int 0) (const_int 1)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "pkbb\t%0, %1, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "v4qi_dup_32" -+ [(set (match_operand:V4QI 0 "register_operand" "=r") -+ (vec_select:V4QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)])))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "pktt\t%0, %1, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_expand "vec_unpacks_lo_v4qi" -+ [(match_operand:V2HI 0 "register_operand" "=r") -+ (match_operand:V4QI 1 "register_operand" " r")] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+{ -+ emit_insn (gen_sunpkd810 (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_expand "sunpkd810" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_sunpkd810_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_sunpkd810_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_insn "unpkd810_imp" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd810\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd810_imp_inv" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd810\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd810_imp_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 3)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd810\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd810_imp_inv_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 2)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd810\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_expand "sunpkd820" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_sunpkd820_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_sunpkd820_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_insn "unpkd820_imp" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd820\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd820_imp_inv" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 2)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd820\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd820_imp_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 3)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd820\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd820_imp_inv_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd820\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_expand "sunpkd830" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_sunpkd830_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_sunpkd830_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_insn "unpkd830_imp" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd830\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd830_imp_inv" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 3)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd830\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd830_imp_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 3)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd830\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd830_imp_inv_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd830\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_expand "sunpkd831" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_sunpkd831_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_sunpkd831_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_insn "unpkd831_imp" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 1)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd831\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd831_imp_inv" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 3)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "unpkd831\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd831_imp_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 2)])))) -+ (const_int 1)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd831\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "unpkd831_imp_inv_be" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2)])))) -+ (vec_duplicate:V2HI -+ (extend:HI -+ (vec_select:QI -+ (match_dup 1) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "unpkd831\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_expand "zunpkd810" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_zunpkd810_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_zunpkd810_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_expand "zunpkd820" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_zunpkd820_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_zunpkd820_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_expand "zunpkd830" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_zunpkd830_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_zunpkd830_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_expand "zunpkd831" -+ [(match_operand:V2HI 0 "register_operand") -+ (match_operand:V4QI 1 "register_operand")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_zunpkd831_imp_be (operands[0], operands[1])); -+ else -+ emit_insn (gen_zunpkd831_imp (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_expand "smbb" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], -+ GEN_INT (1), GEN_INT (1))); -+ else -+ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], -+ GEN_INT (0), GEN_INT (0))); -+ DONE; -+}) -+ -+(define_expand "smbt" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], -+ GEN_INT (1), GEN_INT (0))); -+ else -+ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], -+ GEN_INT (0), GEN_INT (1))); -+ DONE; -+}) -+ -+(define_expand "smtt" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], -+ GEN_INT (0), GEN_INT (0))); -+ else -+ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], -+ GEN_INT (1), GEN_INT (1))); -+ DONE; -+}) -+ -+(define_insn "mulhisi3v" -+ [(set (match_operand:SI 0 "register_operand" "= r, r, r, r") -+ (mult:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "smtt\t%0, %1, %2", -+ "smbt\t%0, %2, %1", -+ "smbb\t%0, %1, %2", -+ "smbt\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "smbb\t%0, %1, %2", -+ "smbt\t%0, %1, %2", -+ "smtt\t%0, %1, %2", -+ "smbt\t%0, %2, %1" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_expand "kmabb" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], -+ GEN_INT (1), GEN_INT (1), -+ operands[1])); -+ else -+ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], -+ GEN_INT (0), GEN_INT (0), -+ operands[1])); -+ DONE; -+}) -+ -+(define_expand "kmabt" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], -+ GEN_INT (1), GEN_INT (0), -+ operands[1])); -+ else -+ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], -+ GEN_INT (0), GEN_INT (1), -+ operands[1])); -+ DONE; -+}) -+ -+(define_expand "kmatt" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], -+ GEN_INT (0), GEN_INT (0), -+ operands[1])); -+ else -+ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], -+ GEN_INT (1), GEN_INT (1), -+ operands[1])); -+ DONE; -+}) -+ -+(define_insn "kma_internal" -+ [(set (match_operand:SI 0 "register_operand" "= r, r, r, r") -+ (ss_plus:SI -+ (mult:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))) -+ (match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "kmatt\t%0, %1, %2", -+ "kmabt\t%0, %2, %1", -+ "kmabb\t%0, %1, %2", -+ "kmabt\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "kmabb\t%0, %1, %2", -+ "kmabt\t%0, %1, %2", -+ "kmatt\t%0, %1, %2", -+ "kmabt\t%0, %2, %1" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_expand "smds" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smds_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_smds_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_expand "smds_le" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+}) -+ -+(define_expand "smds_be" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+}) -+ -+(define_expand "smdrs" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smdrs_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_smdrs_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_expand "smdrs_le" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+}) -+ -+(define_expand "smdrs_be" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+}) -+ -+(define_expand "smxdsv" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:V2HI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smxdsv_be (operands[0], operands[1], operands[2])); -+ else -+ emit_insn (gen_smxdsv_le (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+ -+(define_expand "smxdsv_le" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+}) -+ -+(define_expand "smxdsv_be" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+}) -+ -+(define_insn "smal1" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI (match_operand:DI 1 "register_operand" " r") -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smal2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI (match_operand:DI 1 "register_operand" " r") -+ (mult:DI -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))))))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smal3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI (match_operand:DI 1 "register_operand" " r") -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smal4" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI (match_operand:DI 1 "register_operand" " r") -+ (mult:DI -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))))))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smal5" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))))) -+ (match_operand:DI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smal6" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (mult:DI -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)])))) -+ (match_operand:DI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smal7" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))))) -+ (match_operand:DI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smal8" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (mult:DI -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)])))) -+ (match_operand:DI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "smal\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+;; We need this dummy pattern for smal -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (sign_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))] -+ "NDS32_EXT_DSP_P ()" -+ "#" -+ "NDS32_EXT_DSP_P ()" -+ [(const_int 0)] -+{ -+ rtx high_part_dst, low_part_dst; -+ -+ low_part_dst = nds32_di_low_part_subreg (operands[0]); -+ high_part_dst = nds32_di_high_part_subreg (operands[0]); -+ -+ emit_move_insn (low_part_dst, operands[1]); -+ emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31))); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+;; We need this dummy pattern for usmar64/usmsr64 -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (zero_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))] -+ "NDS32_EXT_DSP_P ()" -+ "#" -+ "NDS32_EXT_DSP_P ()" -+ [(const_int 0)] -+{ -+ rtx high_part_dst, low_part_dst; -+ -+ low_part_dst = nds32_di_low_part_subreg (operands[0]); -+ high_part_dst = nds32_di_high_part_subreg (operands[0]); -+ -+ emit_move_insn (low_part_dst, operands[1]); -+ emit_move_insn (high_part_dst, const0_rtx); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] -+ "NDS32_EXT_DSP_P ()" -+ "#" -+ "NDS32_EXT_DSP_P ()" -+ [(const_int 0)] -+{ -+ rtx high_part_dst, low_part_dst; -+ -+ low_part_dst = nds32_di_low_part_subreg (operands[0]); -+ high_part_dst = nds32_di_high_part_subreg (operands[0]); -+ -+ -+ emit_insn (gen_extendhisi2 (low_part_dst, operands[1])); -+ emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31))); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "sunpkd820\t%0, %1" -+ [(set_attr "type" "dpack") -+ (set_attr "length" "4")]) -+ -+(define_insn "smulsi3_highpart" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) -+ (const_int 32))))] -+ "NDS32_EXT_DSP_P ()" -+ "smmul\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_insn "smmul_round" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (lshiftrt:DI -+ (unspec:DI [(mult:DI -+ (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))] -+ UNSPEC_ROUND) -+ (const_int 32))))] -+ "NDS32_EXT_DSP_P ()" -+ "smmul.u\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmmac" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI (match_operand:SI 1 "register_operand" " 0") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) -+ (sign_extend:DI (match_operand:SI 3 "register_operand" " r"))) -+ (const_int 32)))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmmac\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmmac_round" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI (match_operand:SI 1 "register_operand" " 0") -+ (truncate:SI -+ (lshiftrt:DI -+ (unspec:DI [(mult:DI -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) -+ (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))] -+ UNSPEC_ROUND) -+ (const_int 32)))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmmac.u\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmmsb" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_minus:SI (match_operand:SI 1 "register_operand" " 0") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) -+ (sign_extend:DI (match_operand:SI 3 "register_operand" " r"))) -+ (const_int 32)))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmmsb\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmmsb_round" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_minus:SI (match_operand:SI 1 "register_operand" " 0") -+ (truncate:SI -+ (lshiftrt:DI -+ (unspec:DI [(mult:DI -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) -+ (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))] -+ UNSPEC_ROUND) -+ (const_int 32)))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmmsb.u\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kwmmul" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (lshiftrt:DI -+ (ss_mult:DI -+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2)) -+ (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2))) -+ (const_int 32))))] -+ "NDS32_EXT_DSP_P ()" -+ "kwmmul\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_insn "kwmmul_round" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (lshiftrt:DI -+ (unspec:DI [ -+ (ss_mult:DI -+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2)) -+ (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))] -+ UNSPEC_ROUND) -+ (const_int 32))))] -+ "NDS32_EXT_DSP_P ()" -+ "kwmmul.u\t%0, %1, %2" -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_expand "smmwb" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1))); -+ else -+ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0))); -+ DONE; -+}) -+ -+(define_expand "smmwt" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0))); -+ else -+ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1))); -+ DONE; -+}) -+ -+(define_insn "smulhisi3_highpart_1" -+ [(set (match_operand:SI 0 "register_operand" "= r, r") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))) -+ (const_int 16))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "smmwt\t%0, %1, %2", -+ "smmwb\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "smmwb\t%0, %1, %2", -+ "smmwt\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_insn "smulhisi3_highpart_2" -+ [(set (match_operand:SI 0 "register_operand" "= r, r") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r, r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))) -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r, r"))) -+ (const_int 16))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "smmwt\t%0, %1, %2", -+ "smmwb\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "smmwb\t%0, %1, %2", -+ "smmwt\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_expand "smmwb_round" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1))); -+ else -+ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0))); -+ DONE; -+}) -+ -+(define_expand "smmwt_round" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0))); -+ else -+ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1))); -+ DONE; -+}) -+ -+(define_insn "smmw_round_internal" -+ [(set (match_operand:SI 0 "register_operand" "= r, r") -+ (truncate:SI -+ (lshiftrt:DI -+ (unspec:DI -+ [(mult:DI -+ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))] -+ UNSPEC_ROUND) -+ (const_int 16))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "smmwt.u\t%0, %1, %2", -+ "smmwb.u\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "smmwb.u\t%0, %1, %2", -+ "smmwt.u\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmul") -+ (set_attr "length" "4")]) -+ -+(define_expand "kmmawb" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:SI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); -+ else -+ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); -+ DONE; -+}) -+ -+(define_expand "kmmawt" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:SI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); -+ else -+ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); -+ DONE; -+}) -+ -+(define_insn "kmmaw_internal" -+ [(set (match_operand:SI 0 "register_operand" "= r, r") -+ (ss_plus:SI -+ (match_operand:SI 4 "register_operand" " 0, 0") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))) -+ (const_int 16)))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "kmmawt\t%0, %1, %2", -+ "kmmawb\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "kmmawb\t%0, %1, %2", -+ "kmmawt\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_expand "kmmawb_round" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:SI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); -+ else -+ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); -+ DONE; -+} -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ -+(define_expand "kmmawt_round" -+ [(match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "") -+ (match_operand:SI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); -+ else -+ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); -+ DONE; -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "kmmaw_round_internal" -+ [(set (match_operand:SI 0 "register_operand" "= r, r") -+ (ss_plus:SI -+ (match_operand:SI 4 "register_operand" " 0, 0") -+ (truncate:SI -+ (lshiftrt:DI -+ (unspec:DI -+ [(mult:DI -+ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))] -+ UNSPEC_ROUND) -+ (const_int 16)))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "kmmawt.u\t%0, %1, %2", -+ "kmmawb.u\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "kmmawb.u\t%0, %1, %2", -+ "kmmawt.u\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_expand "smalbb" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smaddhidi (operands[0], operands[2], -+ operands[3], operands[1], -+ GEN_INT (1), GEN_INT (1))); -+ else -+ emit_insn (gen_smaddhidi (operands[0], operands[2], -+ operands[3], operands[1], -+ GEN_INT (0), GEN_INT (0))); -+ DONE; -+}) -+ -+(define_expand "smalbt" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smaddhidi (operands[0], operands[2], -+ operands[3], operands[1], -+ GEN_INT (1), GEN_INT (0))); -+ else -+ emit_insn (gen_smaddhidi (operands[0], operands[2], -+ operands[3], operands[1], -+ GEN_INT (0), GEN_INT (1))); -+ DONE; -+}) -+ -+(define_expand "smaltt" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" "") -+ (match_operand:V2HI 3 "register_operand" "")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smaddhidi (operands[0], operands[2], -+ operands[3], operands[1], -+ GEN_INT (0), GEN_INT (0))); -+ else -+ emit_insn (gen_smaddhidi (operands[0], operands[2], -+ operands[3], operands[1], -+ GEN_INT (1), GEN_INT (1))); -+ DONE; -+}) -+ -+(define_insn "smaddhidi" -+ [(set (match_operand:DI 0 "register_operand" "= r, r, r, r") -+ (plus:DI -+ (match_operand:DI 3 "register_operand" " 0, 0, 0, 0") -+ (mult:DI -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "smaltt\t%0, %1, %2", -+ "smalbt\t%0, %2, %1", -+ "smalbb\t%0, %1, %2", -+ "smalbt\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "smalbb\t%0, %1, %2", -+ "smalbt\t%0, %1, %2", -+ "smaltt\t%0, %1, %2", -+ "smalbt\t%0, %2, %1" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smaddhidi2" -+ [(set (match_operand:DI 0 "register_operand" "= r, r, r, r") -+ (plus:DI -+ (mult:DI -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) -+ (sign_extend:DI -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r, r, r, r") -+ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))) -+ (match_operand:DI 3 "register_operand" " 0, 0, 0, 0")))] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ { -+ const char *pats[] = { "smaltt\t%0, %1, %2", -+ "smalbt\t%0, %2, %1", -+ "smalbb\t%0, %1, %2", -+ "smalbt\t%0, %1, %2" }; -+ return pats[which_alternative]; -+ } -+ else -+ { -+ const char *pats[] = { "smalbb\t%0, %1, %2", -+ "smalbt\t%0, %1, %2", -+ "smaltt\t%0, %1, %2", -+ "smalbt\t%0, %2, %1" }; -+ return pats[which_alternative]; -+ } -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_expand "smalda1" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" " r") -+ (match_operand:V2HI 3 "register_operand" " r")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smalda1_be (operands[0], operands[1], operands[2], operands[3])); -+ else -+ emit_insn (gen_smalda1_le (operands[0], operands[1], operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_expand "smalds1" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" " r") -+ (match_operand:V2HI 3 "register_operand" " r")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smalds1_be (operands[0], operands[1], operands[2], operands[3])); -+ else -+ emit_insn (gen_smalds1_le (operands[0], operands[1], operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_insn "smalda1_le" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)]))))))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "smalda\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smalds1_le" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)]))))))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "smalds\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smalda1_be" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)]))))))))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "smalda\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smalds1_be" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)]))))))))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "smalds\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_expand "smaldrs3" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" " r") -+ (match_operand:V2HI 3 "register_operand" " r")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smaldrs3_be (operands[0], operands[1], operands[2], operands[3])); -+ else -+ emit_insn (gen_smaldrs3_le (operands[0], operands[1], operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_insn "smaldrs3_le" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)]))))))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "smaldrs\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smaldrs3_be" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)]))))))))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "smaldrs\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_expand "smalxda1" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" " r") -+ (match_operand:V2HI 3 "register_operand" " r")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smalxda1_be (operands[0], operands[1], operands[2], operands[3])); -+ else -+ emit_insn (gen_smalxda1_le (operands[0], operands[1], operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_expand "smalxds1" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "register_operand" "") -+ (match_operand:V2HI 2 "register_operand" " r") -+ (match_operand:V2HI 3 "register_operand" " r")] -+ "NDS32_EXT_DSP_P ()" -+{ -+ if (TARGET_BIG_ENDIAN) -+ emit_insn (gen_smalxds1_be (operands[0], operands[1], operands[2], operands[3])); -+ else -+ emit_insn (gen_smalxds1_le (operands[0], operands[1], operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_insn "smalxd1_le" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (plus_minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)]))))))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "smalxd\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "smalxd1_be" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (plus_minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)]))))))))] -+ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" -+ "smalxd\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smslda1" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (minus:DI -+ (minus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))))) -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "smslda\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "smslxda1" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (minus:DI -+ (minus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))))) -+ (sign_extend:DI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "smslxda\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+;; mada for synthetize smalda -+(define_insn_and_split "mada1" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" "r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" "r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx result0 = gen_reg_rtx (SImode); -+ rtx result1 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3v (result0, operands[1], operands[2], -+ operands[3], operands[4])); -+ emit_insn (gen_mulhisi3v (result1, operands[1], operands[2], -+ operands[5], operands[6])); -+ emit_insn (gen_addsi3 (operands[0], result0, result1)); -+ DONE; -+}) -+ -+(define_insn_and_split "mada2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" "r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" "r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 1)] -+{ -+ rtx result0 = gen_reg_rtx (SImode); -+ rtx result1 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3v (result0, operands[1], operands[2], -+ operands[3], operands[4])); -+ emit_insn (gen_mulhisi3v (result1, operands[1], operands[2], -+ operands[6], operands[5])); -+ emit_insn (gen_addsi3 (operands[0], result0, result1)); -+ DONE; -+}) -+ -+;; sms for synthetize smalds -+(define_insn_and_split "sms1" -+ [(set (match_operand:SI 0 "register_operand" "= r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] -+ "NDS32_EXT_DSP_P () -+ && (!reload_completed -+ || !nds32_need_split_sms_p (operands[3], operands[4], -+ operands[5], operands[6]))" -+ -+{ -+ return nds32_output_sms (operands[3], operands[4], -+ operands[5], operands[6]); -+} -+ "NDS32_EXT_DSP_P () -+ && !reload_completed -+ && nds32_need_split_sms_p (operands[3], operands[4], -+ operands[5], operands[6])" -+ [(const_int 1)] -+{ -+ nds32_split_sms (operands[0], operands[1], operands[2], -+ operands[3], operands[4], -+ operands[5], operands[6]); -+ DONE; -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "sms2" -+ [(set (match_operand:SI 0 "register_operand" "= r") -+ (minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] -+ "NDS32_EXT_DSP_P () -+ && (!reload_completed -+ || !nds32_need_split_sms_p (operands[3], operands[4], -+ operands[6], operands[5]))" -+{ -+ return nds32_output_sms (operands[3], operands[4], -+ operands[6], operands[5]); -+} -+ "NDS32_EXT_DSP_P () -+ && !reload_completed -+ && nds32_need_split_sms_p (operands[3], operands[4], -+ operands[6], operands[5])" -+ [(const_int 1)] -+{ -+ nds32_split_sms (operands[0], operands[1], operands[2], -+ operands[3], operands[4], -+ operands[6], operands[5]); -+ DONE; -+} -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmda" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" "r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" "r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmda\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmxda" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" "r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" "r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 1) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmxda\t%0, %1, %2" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmada" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmada\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmada2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmada\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmaxda" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_plus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmaxda\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmads" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmads\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmadrs" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmadrs\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmaxds" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmaxds\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmsda" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_minus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 0)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmsda\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmsxda" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_minus:SI -+ (match_operand:SI 1 "register_operand" " 0") -+ (ss_minus:SI -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_operand:V2HI 3 "register_operand" " r") -+ (parallel [(const_int 0)])))) -+ (mult:SI -+ (sign_extend:SI (vec_select:HI -+ (match_dup 2) -+ (parallel [(const_int 0)]))) -+ (sign_extend:SI (vec_select:HI -+ (match_dup 3) -+ (parallel [(const_int 1)])))))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmsxda\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+;; smax[8|16] and umax[8|16] -+(define_insn "3" -+ [(set (match_operand:VQIHI 0 "register_operand" "=r") -+ (sumax:VQIHI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+;; smin[8|16] and umin[8|16] -+(define_insn "3" -+ [(set (match_operand:VQIHI 0 "register_operand" "=r") -+ (sumin:VQIHI (match_operand:VQIHI 1 "register_operand" " r") -+ (match_operand:VQIHI 2 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "3_bb" -+ [(set (match_operand: 0 "register_operand" "=r") -+ (sumin_max: (vec_select: -+ (match_operand:VQIHI 1 "register_operand" " r") -+ (parallel [(const_int 0)])) -+ (vec_select: -+ (match_operand:VQIHI 2 "register_operand" " r") -+ (parallel [(const_int 0)]))))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "3_tt" -+ [(set (match_operand: 0 "register_operand" "=r") -+ (sumin_max: (vec_select: -+ (match_operand:VQIHI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select: -+ (match_operand:VQIHI 2 "register_operand" " r") -+ (parallel [(const_int 1)]))))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 0)] -+{ -+ rtx tmp = gen_reg_rtx (mode); -+ emit_insn (gen_3 (tmp, operands[1], operands[2])); -+ emit_insn (gen_rotr_1 (tmp, tmp)); -+ emit_move_insn (operands[0], simplify_gen_subreg (mode, tmp, mode, 0)); -+ DONE; -+} -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "v4qi3_22" -+ [(set (match_operand:QI 0 "register_operand" "=r") -+ (sumin_max:QI (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 2)])) -+ (vec_select:QI -+ (match_operand:V4QI 2 "register_operand" " r") -+ (parallel [(const_int 2)]))))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 0)] -+{ -+ rtx tmp = gen_reg_rtx (V4QImode); -+ emit_insn (gen_v4qi3 (tmp, operands[1], operands[2])); -+ emit_insn (gen_rotrv4qi_2 (tmp, tmp)); -+ emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0)); -+ DONE; -+} -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "v4qi3_33" -+ [(set (match_operand:QI 0 "register_operand" "=r") -+ (sumin_max:QI (vec_select:QI -+ (match_operand:V4QI 1 "register_operand" " r") -+ (parallel [(const_int 3)])) -+ (vec_select:QI -+ (match_operand:V4QI 2 "register_operand" " r") -+ (parallel [(const_int 3)]))))] -+ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 0)] -+{ -+ rtx tmp = gen_reg_rtx (V4QImode); -+ emit_insn (gen_v4qi3 (tmp, operands[1], operands[2])); -+ emit_insn (gen_rotrv4qi_3 (tmp, tmp)); -+ emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0)); -+ DONE; -+} -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "v2hi3_bbtt" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (vec_merge:V2HI -+ (vec_duplicate:V2HI -+ (sumin_max:HI (vec_select:HI -+ (match_operand:V2HI 1 "register_operand" " r") -+ (parallel [(const_int 1)])) -+ (vec_select:HI -+ (match_operand:V2HI 2 "register_operand" " r") -+ (parallel [(const_int 1)])))) -+ (vec_duplicate:V2HI -+ (sumin_max:HI (vec_select:HI -+ (match_dup:V2HI 1) -+ (parallel [(const_int 0)])) -+ (vec_select:HI -+ (match_dup:V2HI 2) -+ (parallel [(const_int 0)])))) -+ (const_int 2)))] -+ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" -+ "#" -+ "NDS32_EXT_DSP_P ()" -+ [(const_int 0)] -+{ -+ emit_insn (gen_v2hi3 (operands[0], operands[1], operands[2])); -+ DONE; -+} -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_expand "abs2" -+ [(set (match_operand:VQIHI 0 "register_operand" "=r") -+ (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P () && TARGET_HW_ABS && !flag_wrapv" -+{ -+}) -+ -+(define_insn "kabs2" -+ [(set (match_operand:VQIHI 0 "register_operand" "=r") -+ (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))] -+ "NDS32_EXT_DSP_P ()" -+ "kabs\t%0, %1" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "mar64_1" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (mult:DI -+ (extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (extend:DI -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "mar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "mar64_2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (mult:DI -+ (extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (extend:DI -+ (match_operand:SI 3 "register_operand" " r"))) -+ (match_operand:DI 1 "register_operand" " 0")))] -+ "NDS32_EXT_DSP_P ()" -+ "mar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "mar64_3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (extend:DI -+ (mult:SI -+ (match_operand:SI 2 "register_operand" " r") -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "mar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "mar64_4" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI -+ (extend:DI -+ (mult:SI -+ (match_operand:SI 2 "register_operand" " r") -+ (match_operand:SI 3 "register_operand" " r"))) -+ (match_operand:DI 1 "register_operand" " 0")))] -+ "NDS32_EXT_DSP_P ()" -+ "mar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "msr64" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (minus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (mult:DI -+ (extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (extend:DI -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "msr64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "msr64_2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (minus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (extend:DI -+ (mult:SI -+ (match_operand:SI 2 "register_operand" " r") -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "msr64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+;; kmar64, kmsr64, ukmar64 and ukmsr64 -+(define_insn "kmar64_1" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (ss_plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (mult:DI -+ (sign_extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (sign_extend:DI -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmar64_2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (ss_plus:DI -+ (mult:DI -+ (sign_extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (sign_extend:DI -+ (match_operand:SI 3 "register_operand" " r"))) -+ (match_operand:DI 1 "register_operand" " 0")))] -+ "NDS32_EXT_DSP_P ()" -+ "kmar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "kmsr64" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (ss_minus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (mult:DI -+ (sign_extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (sign_extend:DI -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "kmsr64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "ukmar64_1" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (us_plus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (mult:DI -+ (zero_extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (zero_extend:DI -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "ukmar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "ukmar64_2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (us_plus:DI -+ (mult:DI -+ (zero_extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (zero_extend:DI -+ (match_operand:SI 3 "register_operand" " r"))) -+ (match_operand:DI 1 "register_operand" " 0")))] -+ "NDS32_EXT_DSP_P ()" -+ "ukmar64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "ukmsr64" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (us_minus:DI -+ (match_operand:DI 1 "register_operand" " 0") -+ (mult:DI -+ (zero_extend:DI -+ (match_operand:SI 2 "register_operand" " r")) -+ (zero_extend:DI -+ (match_operand:SI 3 "register_operand" " r")))))] -+ "NDS32_EXT_DSP_P ()" -+ "ukmsr64\t%0, %2, %3" -+ [(set_attr "type" "dmac") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick1" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (match_operand:SI 1 "register_operand" " r") -+ (match_operand:SI 3 "register_operand" " r")) -+ (and:SI -+ (match_operand:SI 2 "register_operand" " r") -+ (not:SI (match_dup 3)))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %1, %2, %3" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (match_operand:SI 1 "register_operand" " r") -+ (match_operand:SI 2 "register_operand" " r")) -+ (and:SI -+ (not:SI (match_dup 2)) -+ (match_operand:SI 3 "register_operand" " r"))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %1, %3, %2" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (match_operand:SI 1 "register_operand" " r") -+ (match_operand:SI 2 "register_operand" " r")) -+ (and:SI -+ (match_operand:SI 3 "register_operand" " r") -+ (not:SI (match_dup 1)))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %2, %3, %1" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick4" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (match_operand:SI 1 "register_operand" " r") -+ (match_operand:SI 2 "register_operand" " r")) -+ (and:SI -+ (not:SI (match_dup 1)) -+ (match_operand:SI 3 "register_operand" " r"))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %2, %3, %1" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick5" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (match_operand:SI 1 "register_operand" " r") -+ (not:SI (match_operand:SI 2 "register_operand" " r"))) -+ (and:SI -+ (match_operand:SI 3 "register_operand" " r") -+ (match_dup 2))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %3, %1, %2" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick6" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (not:SI (match_operand:SI 1 "register_operand" " r")) -+ (match_operand:SI 2 "register_operand" " r")) -+ (and:SI -+ (match_operand:SI 3 "register_operand" " r") -+ (match_dup 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %3, %2, %1" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick7" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (match_operand:SI 1 "register_operand" " r") -+ (not:SI (match_operand:SI 2 "register_operand" " r"))) -+ (and:SI -+ (match_dup 2) -+ (match_operand:SI 3 "register_operand" " r"))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %3, %1, %2" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "bpick8" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ior:SI -+ (and:SI -+ (not:SI (match_operand:SI 1 "register_operand" " r")) -+ (match_operand:SI 2 "register_operand" " r")) -+ (and:SI -+ (match_dup 1) -+ (match_operand:SI 3 "register_operand" " r"))))] -+ "NDS32_EXT_DSP_P ()" -+ "bpick\t%0, %3, %2, %1" -+ [(set_attr "type" "dbpick") -+ (set_attr "length" "4")]) -+ -+(define_insn "sraiu" -+ [(set (match_operand:SI 0 "register_operand" "= r, r") -+ (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r"))] -+ UNSPEC_ROUND))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ srai.u\t%0, %1, %2 -+ sra.u\t%0, %1, %2" -+ [(set_attr "type" "daluround") -+ (set_attr "length" "4")]) -+ -+(define_insn "kssl" -+ [(set (match_operand:SI 0 "register_operand" "= r, r") -+ (ss_ashift:SI (match_operand:SI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ kslli\t%0, %1, %2 -+ ksll\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+(define_insn "kslraw_round" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (if_then_else:SI -+ (lt:SI (match_operand:SI 2 "register_operand" " r") -+ (const_int 0)) -+ (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r") -+ (neg:SI (match_dup 2)))] -+ UNSPEC_ROUND) -+ (ss_ashift:SI (match_dup 1) -+ (match_dup 2))))] -+ "NDS32_EXT_DSP_P ()" -+ "kslraw.u\t%0, %1, %2" -+ [(set_attr "type" "daluround") -+ (set_attr "length" "4")]) -+ -+(define_insn_and_split "di3" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (shift_rotate:DI (match_operand:DI 1 "register_operand" "") -+ (match_operand:SI 2 "nds32_rimm6u_operand" "")))] -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ "#" -+ "NDS32_EXT_DSP_P () && !reload_completed" -+ [(const_int 0)] -+{ -+ if (REGNO (operands[0]) == REGNO (operands[1])) -+ { -+ rtx tmp = gen_reg_rtx (DImode); -+ nds32_split_di3 (tmp, operands[1], operands[2]); -+ emit_move_insn (operands[0], tmp); -+ } -+ else -+ nds32_split_di3 (operands[0], operands[1], operands[2]); -+ DONE; -+}) -+ -+(define_insn "sclip32" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIPS_OV))] -+ "NDS32_EXT_DSP_P ()" -+ "sclip32\t%0, %1, %2" -+ [(set_attr "type" "dclip") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "uclip32" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIP_OV))] -+ "NDS32_EXT_DSP_P ()" -+ "uclip32\t%0, %1, %2" -+ [(set_attr "type" "dclip") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "bitrev" -+ [(set (match_operand:SI 0 "register_operand" "=r, r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm5u_operand" " r, Iu05")] -+ UNSPEC_BITREV))] -+ "" -+ "@ -+ bitrev\t%0, %1, %2 -+ bitrevi\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")] -+) -+ -+;; wext, wexti -+(define_insn "wext" -+ [(set (match_operand:SI 0 "register_operand" "=r, r") -+ (truncate:SI -+ (shiftrt:DI -+ (match_operand:DI 1 "register_operand" " r, r") -+ (match_operand:SI 2 "nds32_rimm5u_operand" " r,Iu05"))))] -+ "NDS32_EXT_DSP_P ()" -+ "@ -+ wext\t%0, %1, %2 -+ wexti\t%0, %1, %2" -+ [(set_attr "type" "dwext") -+ (set_attr "length" "4")]) -+ -+;; 32-bit add/sub instruction: raddw and rsubw. -+(define_insn "rsi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (ashiftrt:DI -+ (plus_minus:DI -+ (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) -+ (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "rw\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -+ -+;; 32-bit add/sub instruction: uraddw and ursubw. -+(define_insn "ursi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (lshiftrt:DI -+ (plus_minus:DI -+ (zero_extend:DI (match_operand:SI 1 "register_operand" " r")) -+ (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))) -+ (const_int 1))))] -+ "NDS32_EXT_DSP_P ()" -+ "urw\t%0, %1, %2" -+ [(set_attr "type" "dalu") -+ (set_attr "length" "4")]) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-elf.opt gcc-8.2.0/gcc/config/nds32/nds32-elf.opt ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-elf.opt 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-elf.opt 2019-01-25 15:38:32.825242648 +0100 -@@ -0,0 +1,16 @@ -+mcmodel= -+Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_MEDIUM) -+Specify the address generation strategy for code model. -+ -+Enum -+Name(nds32_cmodel_type) Type(enum nds32_cmodel_type) -+Known cmodel types (for use with the -mcmodel= option): -+ -+EnumValue -+Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL) -+ -+EnumValue -+Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM) -+ -+EnumValue -+Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-fp-as-gp.c gcc-8.2.0/gcc/config/nds32/nds32-fp-as-gp.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-fp-as-gp.c 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-fp-as-gp.c 2019-01-25 15:38:32.825242648 +0100 -@@ -26,19 +26,256 @@ - #include "system.h" - #include "coretypes.h" - #include "backend.h" -+#include "hard-reg-set.h" -+#include "tm_p.h" -+#include "rtl.h" -+#include "memmodel.h" -+#include "emit-rtl.h" -+#include "insn-config.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "ira.h" -+#include "ira-int.h" -+#include "df.h" -+#include "tree-core.h" -+#include "tree-pass.h" -+#include "nds32-protos.h" - - /* ------------------------------------------------------------------------ */ - -+/* A helper function to check if this function should contain prologue. */ -+static bool -+nds32_have_prologue_p (void) -+{ -+ int i; -+ -+ for (i = 0; i < 28; i++) -+ if (NDS32_REQUIRED_CALLEE_SAVED_P (i)) -+ return true; -+ -+ return (flag_pic -+ || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM) -+ || NDS32_REQUIRED_CALLEE_SAVED_P (LP_REGNUM)); -+} -+ -+static int -+nds32_get_symbol_count (void) -+{ -+ int symbol_count = 0; -+ rtx_insn *insn; -+ basic_block bb; -+ -+ FOR_EACH_BB_FN (bb, cfun) -+ { -+ FOR_BB_INSNS (bb, insn) -+ { -+ /* Counting the insn number which the addressing mode is symbol. */ -+ if (single_set (insn) && nds32_symbol_load_store_p (insn)) -+ { -+ rtx pattern = PATTERN (insn); -+ rtx mem; -+ gcc_assert (GET_CODE (pattern) == SET); -+ if (GET_CODE (SET_SRC (pattern)) == REG ) -+ mem = SET_DEST (pattern); -+ else -+ mem = SET_SRC (pattern); -+ -+ /* We have only lwi37 and swi37 for fp-as-gp optimization, -+ so don't count any other than SImode. -+ MEM for QImode and HImode will wrap by ZERO_EXTEND -+ or SIGN_EXTEND */ -+ if (GET_CODE (mem) == MEM) -+ symbol_count++; -+ } -+ } -+ } -+ -+ return symbol_count; -+} -+ - /* Function to determine whether it is worth to do fp_as_gp optimization. -- Return 0: It is NOT worth to do fp_as_gp optimization. -- Return 1: It is APPROXIMATELY worth to do fp_as_gp optimization. -+ Return false: It is NOT worth to do fp_as_gp optimization. -+ Return true: It is APPROXIMATELY worth to do fp_as_gp optimization. - Note that if it is worth to do fp_as_gp optimization, - we MUST set FP_REGNUM ever live in this function. */ --int -+static bool - nds32_fp_as_gp_check_available (void) - { -- /* By default we return 0. */ -- return 0; -+ basic_block bb; -+ basic_block exit_bb; -+ edge_iterator ei; -+ edge e; -+ bool first_exit_blocks_p; -+ -+ /* If there exists ANY of following conditions, -+ we DO NOT perform fp_as_gp optimization: -+ 1. TARGET_FORBID_FP_AS_GP is set -+ regardless of the TARGET_FORCE_FP_AS_GP. -+ 2. User explicitly uses 'naked'/'no_prologue' attribute. -+ We use nds32_naked_function_p() to help such checking. -+ 3. Not optimize for size. -+ 4. Need frame pointer. -+ 5. If $fp is already required to be saved, -+ it means $fp is already choosen by register allocator. -+ Thus we better not to use it for fp_as_gp optimization. -+ 6. This function is a vararg function. -+ DO NOT apply fp_as_gp optimization on this function -+ because it may change and break stack frame. -+ 7. The epilogue is empty. -+ This happens when the function uses exit() -+ or its attribute is no_return. -+ In that case, compiler will not expand epilogue -+ so that we have no chance to output .omit_fp_end directive. */ -+ if (TARGET_FORBID_FP_AS_GP -+ || nds32_naked_function_p (current_function_decl) -+ || !optimize_size -+ || frame_pointer_needed -+ || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM) -+ || (cfun->stdarg == 1) -+ || (find_fallthru_edge (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == NULL)) -+ return false; -+ -+ /* Disable fp_as_gp if there is any infinite loop since the fp may -+ reuse in infinite loops by register rename. -+ For check infinite loops we should make sure exit_bb is post dominate -+ all other basic blocks if there is no infinite loops. */ -+ first_exit_blocks_p = true; -+ exit_bb = NULL; -+ -+ FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) -+ { -+ /* More than one exit block also do not perform fp_as_gp optimization. */ -+ if (!first_exit_blocks_p) -+ return false; -+ -+ exit_bb = e->src; -+ first_exit_blocks_p = false; -+ } -+ -+ /* Not found exit_bb? just abort fp_as_gp! */ -+ if (!exit_bb) -+ return false; -+ -+ /* Each bb should post dominate by exit_bb if there is no infinite loop! */ -+ FOR_EACH_BB_FN (bb, cfun) -+ { -+ if (!dominated_by_p (CDI_POST_DOMINATORS, -+ bb, -+ exit_bb)) -+ return false; -+ } -+ -+ /* Now we can check the possibility of using fp_as_gp optimization. */ -+ if (TARGET_FORCE_FP_AS_GP) -+ { -+ /* User explicitly issues -mforce-fp-as-gp option. */ -+ return true; -+ } -+ else -+ { -+ /* In the following we are going to evaluate whether -+ it is worth to do fp_as_gp optimization. */ -+ bool good_gain = false; -+ int symbol_count; -+ -+ int threshold; -+ -+ /* We check if there already requires prologue. -+ Note that $gp will be saved in prologue for PIC code generation. -+ After that, we can set threshold by the existence of prologue. -+ Each fp-implied instruction will gain 2-byte code size -+ from gp-aware instruction, so we have following heuristics. */ -+ if (flag_pic -+ || nds32_have_prologue_p ()) -+ { -+ /* Have-prologue: -+ Compiler already intends to generate prologue content, -+ so the fp_as_gp optimization will only insert -+ 'la $fp,_FP_BASE_' instruction, which will be -+ converted into 4-byte instruction at link time. -+ The threshold is "3" symbol accesses, 2 + 2 + 2 > 4. */ -+ threshold = 3; -+ } -+ else -+ { -+ /* None-prologue: -+ Compiler originally does not generate prologue content, -+ so the fp_as_gp optimization will NOT ONLY insert -+ 'la $fp,_FP_BASE' instruction, but also causes -+ push/pop instructions. -+ If we are using v3push (push25/pop25), -+ the threshold is "5" symbol accesses, 5*2 > 4 + 2 + 2; -+ If we are using normal push (smw/lmw), -+ the threshold is "5+2" symbol accesses 7*2 > 4 + 4 + 4. */ -+ threshold = 5 + (TARGET_V3PUSH ? 0 : 2); -+ } -+ -+ symbol_count = nds32_get_symbol_count (); -+ -+ if (symbol_count >= threshold) -+ good_gain = true; -+ -+ /* Enable fp_as_gp optimization when potential gain is good enough. */ -+ return good_gain; -+ } -+} -+ -+static unsigned int -+nds32_fp_as_gp (void) -+{ -+ bool fp_as_gp_p; -+ calculate_dominance_info (CDI_POST_DOMINATORS); -+ fp_as_gp_p = nds32_fp_as_gp_check_available (); -+ -+ /* Here is a hack to IRA for enable/disable a hard register per function. -+ We *MUST* review this way after migrate gcc 4.9! */ -+ if (fp_as_gp_p) { -+ SET_HARD_REG_BIT(this_target_ira_int->x_no_unit_alloc_regs, FP_REGNUM); -+ df_set_regs_ever_live (FP_REGNUM, 1); -+ } else { -+ CLEAR_HARD_REG_BIT(this_target_ira_int->x_no_unit_alloc_regs, FP_REGNUM); -+ } -+ -+ cfun->machine->fp_as_gp_p = fp_as_gp_p; -+ -+ free_dominance_info (CDI_POST_DOMINATORS); -+ return 1; -+} -+ -+const pass_data pass_data_nds32_fp_as_gp = -+{ -+ RTL_PASS, /* type */ -+ "fp_as_gp", /* name */ -+ OPTGROUP_NONE, /* optinfo_flags */ -+ TV_MACH_DEP, /* tv_id */ -+ 0, /* properties_required */ -+ 0, /* properties_provided */ -+ 0, /* properties_destroyed */ -+ 0, /* todo_flags_start */ -+ 0 /* todo_flags_finish */ -+}; -+ -+class pass_nds32_fp_as_gp : public rtl_opt_pass -+{ -+public: -+ pass_nds32_fp_as_gp (gcc::context *ctxt) -+ : rtl_opt_pass (pass_data_nds32_fp_as_gp, ctxt) -+ {} -+ -+ /* opt_pass methods: */ -+ bool gate (function *) -+ { -+ return !TARGET_LINUX_ABI -+ && TARGET_16_BIT -+ && optimize_size; -+ } -+ unsigned int execute (function *) { return nds32_fp_as_gp (); } -+}; -+ -+rtl_opt_pass * -+make_pass_nds32_fp_as_gp (gcc::context *ctxt) -+{ -+ return new pass_nds32_fp_as_gp (ctxt); - } - - /* ------------------------------------------------------------------------ */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-fpu.md gcc-8.2.0/gcc/config/nds32/nds32-fpu.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-fpu.md 2018-04-06 07:51:33.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-fpu.md 2019-01-25 15:38:32.825242648 +0100 -@@ -1,5 +1,5 @@ - ;; Machine description of Andes NDS32 cpu for GNU compiler --;; Copyright (C) 2012-2015 Free Software Foundation, Inc. -+;; Copyright (C) 2012-2018 Free Software Foundation, Inc. - ;; Contributed by Andes Technology Corporation. - ;; - ;; This file is part of GCC. -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-graywolf.md gcc-8.2.0/gcc/config/nds32/nds32-graywolf.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-graywolf.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-graywolf.md 2019-01-25 15:38:32.825242648 +0100 -@@ -0,0 +1,471 @@ -+;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -+;; Copyright (C) 2012-2013 Free Software Foundation, Inc. -+;; Contributed by Andes Technology Corporation. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published -+;; by the Free Software Foundation; either version 3, or (at your -+;; option) any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but WITHOUT -+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+;; License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+;; ------------------------------------------------------------------------ -+;; Define Graywolf pipeline settings. -+;; ------------------------------------------------------------------------ -+ -+(define_automaton "nds32_graywolf_machine") -+ -+(define_cpu_unit "gw_ii_0" "nds32_graywolf_machine") -+(define_cpu_unit "gw_ii_1" "nds32_graywolf_machine") -+(define_cpu_unit "gw_ex_p0" "nds32_graywolf_machine") -+(define_cpu_unit "gw_mm_p0" "nds32_graywolf_machine") -+(define_cpu_unit "gw_wb_p0" "nds32_graywolf_machine") -+(define_cpu_unit "gw_ex_p1" "nds32_graywolf_machine") -+(define_cpu_unit "gw_mm_p1" "nds32_graywolf_machine") -+(define_cpu_unit "gw_wb_p1" "nds32_graywolf_machine") -+(define_cpu_unit "gw_iq_p2" "nds32_graywolf_machine") -+(define_cpu_unit "gw_rf_p2" "nds32_graywolf_machine") -+(define_cpu_unit "gw_e1_p2" "nds32_graywolf_machine") -+(define_cpu_unit "gw_e2_p2" "nds32_graywolf_machine") -+(define_cpu_unit "gw_e3_p2" "nds32_graywolf_machine") -+(define_cpu_unit "gw_e4_p2" "nds32_graywolf_machine") -+ -+(define_reservation "gw_ii" "gw_ii_0 | gw_ii_1") -+(define_reservation "gw_ex" "gw_ex_p0 | gw_ex_p1") -+(define_reservation "gw_mm" "gw_mm_p0 | gw_mm_p1") -+(define_reservation "gw_wb" "gw_wb_p0 | gw_wb_p1") -+ -+(define_reservation "gw_ii_all" "gw_ii_0 + gw_ii_1") -+ -+(define_insn_reservation "nds_gw_unknown" 1 -+ (and (eq_attr "type" "unknown") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_misc" 1 -+ (and (eq_attr "type" "misc") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_mmu" 1 -+ (and (eq_attr "type" "mmu") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_alu" 1 -+ (and (and (eq_attr "type" "alu") -+ (match_test "!nds32::movd44_insn_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_movd44" 1 -+ (and (and (eq_attr "type" "alu") -+ (match_test "nds32::movd44_insn_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_alu_shift" 1 -+ (and (eq_attr "type" "alu_shift") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex*2, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_pbsad" 1 -+ (and (eq_attr "type" "pbsad") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex*3, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_pbsada" 1 -+ (and (eq_attr "type" "pbsada") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex*3, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_load" 1 -+ (and (and (eq_attr "type" "load") -+ (match_test "!nds32::post_update_insn_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_2w" 1 -+ (and (and (eq_attr "type" "load") -+ (match_test "nds32::post_update_insn_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store" 1 -+ (and (and (eq_attr "type" "store") -+ (match_test "!nds32::store_offset_reg_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_3r" 1 -+ (and (and (eq_attr "type" "store") -+ (match_test "nds32::store_offset_reg_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_1" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "1")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_2" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "2")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_3" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "3")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_4" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "4")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_5" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "5")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_6" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "6")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_7" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "7")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_8" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "8")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_load_multiple_12" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "12")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_1" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "1")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_2" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "2")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_3" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "3")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_4" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "4")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_5" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "5")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_6" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "6")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_7" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "7")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_8" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "8")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_store_multiple_12" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "12")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") -+ -+(define_insn_reservation "nds_gw_mul_fast1" 1 -+ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") -+ (and (eq_attr "type" "mul") -+ (eq_attr "pipeline_model" "graywolf"))) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_mul_fast2" 1 -+ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") -+ (and (eq_attr "type" "mul") -+ (eq_attr "pipeline_model" "graywolf"))) -+ "gw_ii_0, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_mul_slow" 1 -+ (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") -+ (and (eq_attr "type" "mul") -+ (eq_attr "pipeline_model" "graywolf"))) -+ "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_mac_fast1" 1 -+ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") -+ (and (eq_attr "type" "mac") -+ (eq_attr "pipeline_model" "graywolf"))) -+ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_mac_fast2" 1 -+ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") -+ (and (eq_attr "type" "mac") -+ (eq_attr "pipeline_model" "graywolf"))) -+ "gw_ii_all, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_mac_slow" 1 -+ (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") -+ (and (eq_attr "type" "mac") -+ (eq_attr "pipeline_model" "graywolf"))) -+ "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_div" 1 -+ (and (and (eq_attr "type" "div") -+ (match_test "!nds32::divmod_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_div_2w" 1 -+ (and (and (eq_attr "type" "div") -+ (match_test "nds32::divmod_p (insn)")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_branch" 1 -+ (and (eq_attr "type" "branch") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_alu" 1 -+ (and (eq_attr "type" "dalu") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ex, gw_mm, gw_wb") -+ -+(define_insn_reservation "nds_gw_dsp_alu64" 1 -+ (and (eq_attr "type" "dalu64") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_alu_round" 1 -+ (and (eq_attr "type" "daluround") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_cmp" 1 -+ (and (eq_attr "type" "dcmp") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_clip" 1 -+ (and (eq_attr "type" "dclip") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_mul" 1 -+ (and (eq_attr "type" "dmul") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_mac" 1 -+ (and (eq_attr "type" "dmac") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_insb" 1 -+ (and (eq_attr "type" "dinsb") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_pack" 1 -+ (and (eq_attr "type" "dpack") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_bpick" 1 -+ (and (eq_attr "type" "dbpick") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_dsp_wext" 1 -+ (and (eq_attr "type" "dwext") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") -+ -+(define_insn_reservation "nds_gw_fpu_alu" 4 -+ (and (eq_attr "type" "falu") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_muls" 4 -+ (and (eq_attr "type" "fmuls") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_muld" 4 -+ (and (eq_attr "type" "fmuld") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*2, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_macs" 4 -+ (and (eq_attr "type" "fmacs") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*3, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_macd" 4 -+ (and (eq_attr "type" "fmacd") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*4, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_divs" 4 -+ (and (ior (eq_attr "type" "fdivs") -+ (eq_attr "type" "fsqrts")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*14, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_divd" 4 -+ (and (ior (eq_attr "type" "fdivd") -+ (eq_attr "type" "fsqrtd")) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*28, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_fast_alu" 2 -+ (and (ior (eq_attr "type" "fcmp") -+ (ior (eq_attr "type" "fabs") -+ (ior (eq_attr "type" "fcpy") -+ (eq_attr "type" "fcmov")))) -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_fmtsr" 1 -+ (and (eq_attr "type" "fmtsr") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_fmtdr" 1 -+ (and (eq_attr "type" "fmtdr") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_fmfsr" 1 -+ (and (eq_attr "type" "fmfsr") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_fmfdr" 1 -+ (and (eq_attr "type" "fmfdr") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_load" 3 -+ (and (eq_attr "type" "fload") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") -+ -+(define_insn_reservation "nds_gw_fpu_store" 1 -+ (and (eq_attr "type" "fstore") -+ (eq_attr "pipeline_model" "graywolf")) -+ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") -+ -+;; FPU_ADDR_OUT -> FPU_ADDR_IN -+;; Main pipeline rules don't need this because those default latency is 1. -+(define_bypass 1 -+ "nds_gw_fpu_load, nds_gw_fpu_store" -+ "nds_gw_fpu_load, nds_gw_fpu_store" -+ "nds32_gw_ex_to_ex_p" -+) -+ -+;; LD, MUL, MAC, DIV, DALU64, DMUL, DMAC, DALUROUND, DBPICK, DWEXT -+;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU, -+;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb -+(define_bypass 2 -+ "nds_gw_load, nds_gw_load_2w,\ -+ nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ -+ nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ -+ nds_gw_div, nds_gw_div_2w,\ -+ nds_gw_dsp_alu64, nds_gw_dsp_mul, nds_gw_dsp_mac,\ -+ nds_gw_dsp_alu_round, nds_gw_dsp_bpick, nds_gw_dsp_wext" -+ "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ -+ nds_gw_pbsad, nds_gw_pbsada,\ -+ nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ -+ nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ -+ nds_gw_branch,\ -+ nds_gw_div, nds_gw_div_2w,\ -+ nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ -+ nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ -+ nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ -+ nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ -+ nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ -+ nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ -+ nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ -+ nds_gw_mmu,\ -+ nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ -+ nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ -+ nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ -+ nds_gw_dsp_wext, nds_gw_dsp_bpick" -+ "nds32_gw_mm_to_ex_p" -+) -+ -+;; LMW(N, N) -+;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU -+;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb -+(define_bypass 2 -+ "nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ -+ nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ -+ nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12" -+ "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ -+ nds_gw_pbsad, nds_gw_pbsada,\ -+ nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ -+ nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ -+ nds_gw_branch,\ -+ nds_gw_div, nds_gw_div_2w,\ -+ nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ -+ nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ -+ nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ -+ nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ -+ nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ -+ nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ -+ nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ -+ nds_gw_mmu,\ -+ nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ -+ nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ -+ nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ -+ nds_gw_dsp_wext, nds_gw_dsp_bpick" -+ "nds32_gw_last_load_to_ex_p" -+) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.h gcc-8.2.0/gcc/config/nds32/nds32.h ---- gcc-8.2.0.orig/gcc/config/nds32/nds32.h 2018-05-07 03:27:52.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32.h 2019-01-25 15:44:03.534160189 +0100 -@@ -36,6 +36,16 @@ - #define NDS32_SYMBOL_REF_RODATA_P(x) \ - ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0) - -+enum nds32_relax_insn_type -+{ -+ RELAX_ORI, -+ RELAX_PLT_ADD, -+ RELAX_TLS_ADD_or_LW, -+ RELAX_TLS_ADD_LW, -+ RELAX_TLS_LW_JRAL, -+ RELAX_DONE -+}; -+ - /* Classifies expand result for expand helper function. */ - enum nds32_expand_result_type - { -@@ -140,6 +150,9 @@ - Check gcc/common/config/nds32/nds32-common.c for the optimizations that - apply -malways-align. */ - #define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN) -+ -+#define NDS32_EXT_DSP_P() (TARGET_EXT_DSP && !TARGET_FORCE_NO_EXT_DSP) -+ - /* Get alignment according to mode or type information. - When 'type' is nonnull, there is no need to look at 'mode'. */ - #define NDS32_MODE_TYPE_ALIGN(mode, type) \ -@@ -305,6 +318,10 @@ - 2. The rtl lowering and optimization are close to target code. - For this case we need address to be strictly aligned. */ - int strict_aligned_p; -+ -+ /* Record two similar attributes status. */ -+ int attr_naked_p; -+ int attr_no_prologue_p; - }; - - /* A C structure that contains the arguments information. */ -@@ -350,7 +367,8 @@ - { - NDS32_NESTED, - NDS32_NOT_NESTED, -- NDS32_NESTED_READY -+ NDS32_NESTED_READY, -+ NDS32_CRITICAL - }; - - /* Define structure to record isr information. -@@ -378,6 +396,13 @@ - unless user specifies attribute to change it. */ - enum nds32_isr_nested_type nested_type; - -+ /* Secure isr level. -+ Currently we have 0-3 security level. -+ It should be set to 0 by default. -+ For security processors, this is determined by secure -+ attribute or compiler options. */ -+ unsigned int security_level; -+ - /* Total vectors. - The total vectors = interrupt + exception numbers + reset. - It should be set to 0 by default. -@@ -439,7 +464,30 @@ - NDS32_BUILTIN_FFB, - NDS32_BUILTIN_FFMISM, - NDS32_BUILTIN_FLMISM, -- -+ NDS32_BUILTIN_KADDW, -+ NDS32_BUILTIN_KSUBW, -+ NDS32_BUILTIN_KADDH, -+ NDS32_BUILTIN_KSUBH, -+ NDS32_BUILTIN_KDMBB, -+ NDS32_BUILTIN_V_KDMBB, -+ NDS32_BUILTIN_KDMBT, -+ NDS32_BUILTIN_V_KDMBT, -+ NDS32_BUILTIN_KDMTB, -+ NDS32_BUILTIN_V_KDMTB, -+ NDS32_BUILTIN_KDMTT, -+ NDS32_BUILTIN_V_KDMTT, -+ NDS32_BUILTIN_KHMBB, -+ NDS32_BUILTIN_V_KHMBB, -+ NDS32_BUILTIN_KHMBT, -+ NDS32_BUILTIN_V_KHMBT, -+ NDS32_BUILTIN_KHMTB, -+ NDS32_BUILTIN_V_KHMTB, -+ NDS32_BUILTIN_KHMTT, -+ NDS32_BUILTIN_V_KHMTT, -+ NDS32_BUILTIN_KSLRAW, -+ NDS32_BUILTIN_KSLRAW_U, -+ NDS32_BUILTIN_RDOV, -+ NDS32_BUILTIN_CLROV, - NDS32_BUILTIN_ROTR, - NDS32_BUILTIN_SVA, - NDS32_BUILTIN_SVS, -@@ -512,7 +560,295 @@ - NDS32_BUILTIN_SET_TRIG_LEVEL, - NDS32_BUILTIN_SET_TRIG_EDGE, - NDS32_BUILTIN_GET_TRIG_TYPE, -- -+ NDS32_BUILTIN_DSP_BEGIN, -+ NDS32_BUILTIN_ADD16, -+ NDS32_BUILTIN_V_UADD16, -+ NDS32_BUILTIN_V_SADD16, -+ NDS32_BUILTIN_RADD16, -+ NDS32_BUILTIN_V_RADD16, -+ NDS32_BUILTIN_URADD16, -+ NDS32_BUILTIN_V_URADD16, -+ NDS32_BUILTIN_KADD16, -+ NDS32_BUILTIN_V_KADD16, -+ NDS32_BUILTIN_UKADD16, -+ NDS32_BUILTIN_V_UKADD16, -+ NDS32_BUILTIN_SUB16, -+ NDS32_BUILTIN_V_USUB16, -+ NDS32_BUILTIN_V_SSUB16, -+ NDS32_BUILTIN_RSUB16, -+ NDS32_BUILTIN_V_RSUB16, -+ NDS32_BUILTIN_URSUB16, -+ NDS32_BUILTIN_V_URSUB16, -+ NDS32_BUILTIN_KSUB16, -+ NDS32_BUILTIN_V_KSUB16, -+ NDS32_BUILTIN_UKSUB16, -+ NDS32_BUILTIN_V_UKSUB16, -+ NDS32_BUILTIN_CRAS16, -+ NDS32_BUILTIN_V_UCRAS16, -+ NDS32_BUILTIN_V_SCRAS16, -+ NDS32_BUILTIN_RCRAS16, -+ NDS32_BUILTIN_V_RCRAS16, -+ NDS32_BUILTIN_URCRAS16, -+ NDS32_BUILTIN_V_URCRAS16, -+ NDS32_BUILTIN_KCRAS16, -+ NDS32_BUILTIN_V_KCRAS16, -+ NDS32_BUILTIN_UKCRAS16, -+ NDS32_BUILTIN_V_UKCRAS16, -+ NDS32_BUILTIN_CRSA16, -+ NDS32_BUILTIN_V_UCRSA16, -+ NDS32_BUILTIN_V_SCRSA16, -+ NDS32_BUILTIN_RCRSA16, -+ NDS32_BUILTIN_V_RCRSA16, -+ NDS32_BUILTIN_URCRSA16, -+ NDS32_BUILTIN_V_URCRSA16, -+ NDS32_BUILTIN_KCRSA16, -+ NDS32_BUILTIN_V_KCRSA16, -+ NDS32_BUILTIN_UKCRSA16, -+ NDS32_BUILTIN_V_UKCRSA16, -+ NDS32_BUILTIN_ADD8, -+ NDS32_BUILTIN_V_UADD8, -+ NDS32_BUILTIN_V_SADD8, -+ NDS32_BUILTIN_RADD8, -+ NDS32_BUILTIN_V_RADD8, -+ NDS32_BUILTIN_URADD8, -+ NDS32_BUILTIN_V_URADD8, -+ NDS32_BUILTIN_KADD8, -+ NDS32_BUILTIN_V_KADD8, -+ NDS32_BUILTIN_UKADD8, -+ NDS32_BUILTIN_V_UKADD8, -+ NDS32_BUILTIN_SUB8, -+ NDS32_BUILTIN_V_USUB8, -+ NDS32_BUILTIN_V_SSUB8, -+ NDS32_BUILTIN_RSUB8, -+ NDS32_BUILTIN_V_RSUB8, -+ NDS32_BUILTIN_URSUB8, -+ NDS32_BUILTIN_V_URSUB8, -+ NDS32_BUILTIN_KSUB8, -+ NDS32_BUILTIN_V_KSUB8, -+ NDS32_BUILTIN_UKSUB8, -+ NDS32_BUILTIN_V_UKSUB8, -+ NDS32_BUILTIN_SRA16, -+ NDS32_BUILTIN_V_SRA16, -+ NDS32_BUILTIN_SRA16_U, -+ NDS32_BUILTIN_V_SRA16_U, -+ NDS32_BUILTIN_SRL16, -+ NDS32_BUILTIN_V_SRL16, -+ NDS32_BUILTIN_SRL16_U, -+ NDS32_BUILTIN_V_SRL16_U, -+ NDS32_BUILTIN_SLL16, -+ NDS32_BUILTIN_V_SLL16, -+ NDS32_BUILTIN_KSLL16, -+ NDS32_BUILTIN_V_KSLL16, -+ NDS32_BUILTIN_KSLRA16, -+ NDS32_BUILTIN_V_KSLRA16, -+ NDS32_BUILTIN_KSLRA16_U, -+ NDS32_BUILTIN_V_KSLRA16_U, -+ NDS32_BUILTIN_CMPEQ16, -+ NDS32_BUILTIN_V_SCMPEQ16, -+ NDS32_BUILTIN_V_UCMPEQ16, -+ NDS32_BUILTIN_SCMPLT16, -+ NDS32_BUILTIN_V_SCMPLT16, -+ NDS32_BUILTIN_SCMPLE16, -+ NDS32_BUILTIN_V_SCMPLE16, -+ NDS32_BUILTIN_UCMPLT16, -+ NDS32_BUILTIN_V_UCMPLT16, -+ NDS32_BUILTIN_UCMPLE16, -+ NDS32_BUILTIN_V_UCMPLE16, -+ NDS32_BUILTIN_CMPEQ8, -+ NDS32_BUILTIN_V_SCMPEQ8, -+ NDS32_BUILTIN_V_UCMPEQ8, -+ NDS32_BUILTIN_SCMPLT8, -+ NDS32_BUILTIN_V_SCMPLT8, -+ NDS32_BUILTIN_SCMPLE8, -+ NDS32_BUILTIN_V_SCMPLE8, -+ NDS32_BUILTIN_UCMPLT8, -+ NDS32_BUILTIN_V_UCMPLT8, -+ NDS32_BUILTIN_UCMPLE8, -+ NDS32_BUILTIN_V_UCMPLE8, -+ NDS32_BUILTIN_SMIN16, -+ NDS32_BUILTIN_V_SMIN16, -+ NDS32_BUILTIN_UMIN16, -+ NDS32_BUILTIN_V_UMIN16, -+ NDS32_BUILTIN_SMAX16, -+ NDS32_BUILTIN_V_SMAX16, -+ NDS32_BUILTIN_UMAX16, -+ NDS32_BUILTIN_V_UMAX16, -+ NDS32_BUILTIN_SCLIP16, -+ NDS32_BUILTIN_V_SCLIP16, -+ NDS32_BUILTIN_UCLIP16, -+ NDS32_BUILTIN_V_UCLIP16, -+ NDS32_BUILTIN_KHM16, -+ NDS32_BUILTIN_V_KHM16, -+ NDS32_BUILTIN_KHMX16, -+ NDS32_BUILTIN_V_KHMX16, -+ NDS32_BUILTIN_KABS16, -+ NDS32_BUILTIN_V_KABS16, -+ NDS32_BUILTIN_SMIN8, -+ NDS32_BUILTIN_V_SMIN8, -+ NDS32_BUILTIN_UMIN8, -+ NDS32_BUILTIN_V_UMIN8, -+ NDS32_BUILTIN_SMAX8, -+ NDS32_BUILTIN_V_SMAX8, -+ NDS32_BUILTIN_UMAX8, -+ NDS32_BUILTIN_V_UMAX8, -+ NDS32_BUILTIN_KABS8, -+ NDS32_BUILTIN_V_KABS8, -+ NDS32_BUILTIN_SUNPKD810, -+ NDS32_BUILTIN_V_SUNPKD810, -+ NDS32_BUILTIN_SUNPKD820, -+ NDS32_BUILTIN_V_SUNPKD820, -+ NDS32_BUILTIN_SUNPKD830, -+ NDS32_BUILTIN_V_SUNPKD830, -+ NDS32_BUILTIN_SUNPKD831, -+ NDS32_BUILTIN_V_SUNPKD831, -+ NDS32_BUILTIN_ZUNPKD810, -+ NDS32_BUILTIN_V_ZUNPKD810, -+ NDS32_BUILTIN_ZUNPKD820, -+ NDS32_BUILTIN_V_ZUNPKD820, -+ NDS32_BUILTIN_ZUNPKD830, -+ NDS32_BUILTIN_V_ZUNPKD830, -+ NDS32_BUILTIN_ZUNPKD831, -+ NDS32_BUILTIN_V_ZUNPKD831, -+ NDS32_BUILTIN_RADDW, -+ NDS32_BUILTIN_URADDW, -+ NDS32_BUILTIN_RSUBW, -+ NDS32_BUILTIN_URSUBW, -+ NDS32_BUILTIN_SRA_U, -+ NDS32_BUILTIN_KSLL, -+ NDS32_BUILTIN_PKBB16, -+ NDS32_BUILTIN_V_PKBB16, -+ NDS32_BUILTIN_PKBT16, -+ NDS32_BUILTIN_V_PKBT16, -+ NDS32_BUILTIN_PKTB16, -+ NDS32_BUILTIN_V_PKTB16, -+ NDS32_BUILTIN_PKTT16, -+ NDS32_BUILTIN_V_PKTT16, -+ NDS32_BUILTIN_SMMUL, -+ NDS32_BUILTIN_SMMUL_U, -+ NDS32_BUILTIN_KMMAC, -+ NDS32_BUILTIN_KMMAC_U, -+ NDS32_BUILTIN_KMMSB, -+ NDS32_BUILTIN_KMMSB_U, -+ NDS32_BUILTIN_KWMMUL, -+ NDS32_BUILTIN_KWMMUL_U, -+ NDS32_BUILTIN_SMMWB, -+ NDS32_BUILTIN_V_SMMWB, -+ NDS32_BUILTIN_SMMWB_U, -+ NDS32_BUILTIN_V_SMMWB_U, -+ NDS32_BUILTIN_SMMWT, -+ NDS32_BUILTIN_V_SMMWT, -+ NDS32_BUILTIN_SMMWT_U, -+ NDS32_BUILTIN_V_SMMWT_U, -+ NDS32_BUILTIN_KMMAWB, -+ NDS32_BUILTIN_V_KMMAWB, -+ NDS32_BUILTIN_KMMAWB_U, -+ NDS32_BUILTIN_V_KMMAWB_U, -+ NDS32_BUILTIN_KMMAWT, -+ NDS32_BUILTIN_V_KMMAWT, -+ NDS32_BUILTIN_KMMAWT_U, -+ NDS32_BUILTIN_V_KMMAWT_U, -+ NDS32_BUILTIN_SMBB, -+ NDS32_BUILTIN_V_SMBB, -+ NDS32_BUILTIN_SMBT, -+ NDS32_BUILTIN_V_SMBT, -+ NDS32_BUILTIN_SMTT, -+ NDS32_BUILTIN_V_SMTT, -+ NDS32_BUILTIN_KMDA, -+ NDS32_BUILTIN_V_KMDA, -+ NDS32_BUILTIN_KMXDA, -+ NDS32_BUILTIN_V_KMXDA, -+ NDS32_BUILTIN_SMDS, -+ NDS32_BUILTIN_V_SMDS, -+ NDS32_BUILTIN_SMDRS, -+ NDS32_BUILTIN_V_SMDRS, -+ NDS32_BUILTIN_SMXDS, -+ NDS32_BUILTIN_V_SMXDS, -+ NDS32_BUILTIN_KMABB, -+ NDS32_BUILTIN_V_KMABB, -+ NDS32_BUILTIN_KMABT, -+ NDS32_BUILTIN_V_KMABT, -+ NDS32_BUILTIN_KMATT, -+ NDS32_BUILTIN_V_KMATT, -+ NDS32_BUILTIN_KMADA, -+ NDS32_BUILTIN_V_KMADA, -+ NDS32_BUILTIN_KMAXDA, -+ NDS32_BUILTIN_V_KMAXDA, -+ NDS32_BUILTIN_KMADS, -+ NDS32_BUILTIN_V_KMADS, -+ NDS32_BUILTIN_KMADRS, -+ NDS32_BUILTIN_V_KMADRS, -+ NDS32_BUILTIN_KMAXDS, -+ NDS32_BUILTIN_V_KMAXDS, -+ NDS32_BUILTIN_KMSDA, -+ NDS32_BUILTIN_V_KMSDA, -+ NDS32_BUILTIN_KMSXDA, -+ NDS32_BUILTIN_V_KMSXDA, -+ NDS32_BUILTIN_SMAL, -+ NDS32_BUILTIN_V_SMAL, -+ NDS32_BUILTIN_BITREV, -+ NDS32_BUILTIN_WEXT, -+ NDS32_BUILTIN_BPICK, -+ NDS32_BUILTIN_INSB, -+ NDS32_BUILTIN_SADD64, -+ NDS32_BUILTIN_UADD64, -+ NDS32_BUILTIN_RADD64, -+ NDS32_BUILTIN_URADD64, -+ NDS32_BUILTIN_KADD64, -+ NDS32_BUILTIN_UKADD64, -+ NDS32_BUILTIN_SSUB64, -+ NDS32_BUILTIN_USUB64, -+ NDS32_BUILTIN_RSUB64, -+ NDS32_BUILTIN_URSUB64, -+ NDS32_BUILTIN_KSUB64, -+ NDS32_BUILTIN_UKSUB64, -+ NDS32_BUILTIN_SMAR64, -+ NDS32_BUILTIN_SMSR64, -+ NDS32_BUILTIN_UMAR64, -+ NDS32_BUILTIN_UMSR64, -+ NDS32_BUILTIN_KMAR64, -+ NDS32_BUILTIN_KMSR64, -+ NDS32_BUILTIN_UKMAR64, -+ NDS32_BUILTIN_UKMSR64, -+ NDS32_BUILTIN_SMALBB, -+ NDS32_BUILTIN_V_SMALBB, -+ NDS32_BUILTIN_SMALBT, -+ NDS32_BUILTIN_V_SMALBT, -+ NDS32_BUILTIN_SMALTT, -+ NDS32_BUILTIN_V_SMALTT, -+ NDS32_BUILTIN_SMALDA, -+ NDS32_BUILTIN_V_SMALDA, -+ NDS32_BUILTIN_SMALXDA, -+ NDS32_BUILTIN_V_SMALXDA, -+ NDS32_BUILTIN_SMALDS, -+ NDS32_BUILTIN_V_SMALDS, -+ NDS32_BUILTIN_SMALDRS, -+ NDS32_BUILTIN_V_SMALDRS, -+ NDS32_BUILTIN_SMALXDS, -+ NDS32_BUILTIN_V_SMALXDS, -+ NDS32_BUILTIN_SMUL16, -+ NDS32_BUILTIN_V_SMUL16, -+ NDS32_BUILTIN_SMULX16, -+ NDS32_BUILTIN_V_SMULX16, -+ NDS32_BUILTIN_UMUL16, -+ NDS32_BUILTIN_V_UMUL16, -+ NDS32_BUILTIN_UMULX16, -+ NDS32_BUILTIN_V_UMULX16, -+ NDS32_BUILTIN_SMSLDA, -+ NDS32_BUILTIN_V_SMSLDA, -+ NDS32_BUILTIN_SMSLXDA, -+ NDS32_BUILTIN_V_SMSLXDA, -+ NDS32_BUILTIN_UCLIP32, -+ NDS32_BUILTIN_SCLIP32, -+ NDS32_BUILTIN_KABS, -+ NDS32_BUILTIN_UALOAD_U16, -+ NDS32_BUILTIN_UALOAD_S16, -+ NDS32_BUILTIN_UALOAD_U8, -+ NDS32_BUILTIN_UALOAD_S8, -+ NDS32_BUILTIN_UASTORE_U16, -+ NDS32_BUILTIN_UASTORE_S16, -+ NDS32_BUILTIN_UASTORE_U8, -+ NDS32_BUILTIN_UASTORE_S8, -+ NDS32_BUILTIN_DSP_END, - NDS32_BUILTIN_UNALIGNED_FEATURE, - NDS32_BUILTIN_ENABLE_UNALIGNED, - NDS32_BUILTIN_DISABLE_UNALIGNED, -@@ -521,16 +857,30 @@ - - /* ------------------------------------------------------------------------ */ - --#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) -+#define TARGET_ISR_VECTOR_SIZE_4_BYTE \ -+ (nds32_isr_vector_size == 4) - -+#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) - #define TARGET_ISA_V3 \ - (nds32_arch_option == ARCH_V3 \ -+ || nds32_arch_option == ARCH_V3J \ - || nds32_arch_option == ARCH_V3F \ - || nds32_arch_option == ARCH_V3S) - #define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M) - -+#define TARGET_PIPELINE_N7 \ -+ (nds32_cpu_option == CPU_N7) -+#define TARGET_PIPELINE_N8 \ -+ (nds32_cpu_option == CPU_N6 \ -+ || nds32_cpu_option == CPU_N8) - #define TARGET_PIPELINE_N9 \ - (nds32_cpu_option == CPU_N9) -+#define TARGET_PIPELINE_N10 \ -+ (nds32_cpu_option == CPU_N10) -+#define TARGET_PIPELINE_N13 \ -+ (nds32_cpu_option == CPU_N12 || nds32_cpu_option == CPU_N13) -+#define TARGET_PIPELINE_GRAYWOLF \ -+ (nds32_cpu_option == CPU_GRAYWOLF) - #define TARGET_PIPELINE_SIMPLE \ - (nds32_cpu_option == CPU_SIMPLE) - -@@ -541,6 +891,12 @@ - #define TARGET_CMODEL_LARGE \ - (nds32_cmodel_option == CMODEL_LARGE) - -+#define TARGET_ICT_MODEL_SMALL \ -+ (nds32_ict_model == ICT_MODEL_SMALL) -+ -+#define TARGET_ICT_MODEL_LARGE \ -+ (nds32_ict_model == ICT_MODEL_LARGE) -+ - /* When -mcmodel=small or -mcmodel=medium, - compiler may generate gp-base instruction directly. */ - #define TARGET_GP_DIRECT \ -@@ -576,6 +932,21 @@ - #endif - - #define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2 -+ -+/* ------------------------------------------------------------------------ */ -+ -+#ifdef TARGET_DEFAULT_RELAX -+# define NDS32_RELAX_SPEC " %{!mno-relax:--relax}" -+#else -+# define NDS32_RELAX_SPEC " %{mrelax:--relax}" -+#endif -+ -+#ifdef TARGET_DEFAULT_EXT_DSP -+# define NDS32_EXT_DSP_SPEC " %{!mno-ext-dsp:-mext-dsp}" -+#else -+# define NDS32_EXT_DSP_SPEC "" -+#endif -+ - /* ------------------------------------------------------------------------ */ - - /* Controlling the Compilation Driver. */ -@@ -591,11 +962,15 @@ - {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" } - - #define CC1_SPEC \ -- "" -+ NDS32_EXT_DSP_SPEC - - #define ASM_SPEC \ - " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ - " %{march=*:-march=%*}" \ -+ " %{mno-16-bit|mno-16bit:-mno-16bit-ext}" \ -+ " %{march=v3m:%{!mfull-regs:%{!mreduced-regs:-mreduced-regs}}}" \ -+ " %{mfull-regs:-mno-reduced-regs}" \ -+ " %{mreduced-regs:-mreduced-regs}" \ - " %{mabi=*:-mabi=v%*}" \ - " %{mconfig-fpu=*:-mfpu-freg=%*}" \ - " %{mext-fpu-mac:-mmac}" \ -@@ -603,35 +978,9 @@ - " %{mext-fpu-sp:-mfpu-sp-ext}" \ - " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \ - " %{mext-fpu-dp:-mfpu-dp-ext}" \ -- " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" -- --/* If user issues -mrelax, we need to pass '--relax' to linker. */ --#define LINK_SPEC \ -- " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ -- " %{mrelax:--relax}" -- --#define LIB_SPEC \ -- " -lc -lgloss" -- --/* The option -mno-ctor-dtor can disable constructor/destructor feature -- by applying different crt stuff. In the convention, crt0.o is the -- startup file without constructor/destructor; -- crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the -- startup files with constructor/destructor. -- Note that crt0.o, crt1.o, crti.o, and crtn.o are provided -- by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are -- currently provided by GCC for nds32 target. -- -- For nds32 target so far: -- If -mno-ctor-dtor, we are going to link -- "crt0.o [user objects]". -- If general cases, we are going to link -- "crt1.o crtbegin1.o [user objects] crtend1.o". */ --#define STARTFILE_SPEC \ -- " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ -- " %{!mno-ctor-dtor:crtbegin1.o%s}" --#define ENDFILE_SPEC \ -- " %{!mno-ctor-dtor:crtend1.o%s}" -+ " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" \ -+ " %{mext-dsp:-mdsp-ext}" \ -+ " %{O|O1|O2|O3|Ofast:-O1;:-Os}" - - /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we - configure gcc with --target=nds32be-* setting. -@@ -642,9 +991,11 @@ - # define NDS32_ENDIAN_DEFAULT "mlittle-endian" - #endif - --/* Currently we only have elf toolchain, -- where -mcmodel=medium is always the default. */ --#define NDS32_CMODEL_DEFAULT "mcmodel=medium" -+#if TARGET_ELF -+# define NDS32_CMODEL_DEFAULT "mcmodel=medium" -+#else -+# define NDS32_CMODEL_DEFAULT "mcmodel=large" -+#endif - - #define MULTILIB_DEFAULTS \ - { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT } -@@ -1139,6 +1490,11 @@ - - #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM - -+#define SYMBOLIC_CONST_P(X) \ -+(GET_CODE (X) == SYMBOL_REF \ -+ || GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) -+ - - /* Defining the Output Assembler Language. */ - -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32_init.inc gcc-8.2.0/gcc/config/nds32/nds32_init.inc ---- gcc-8.2.0.orig/gcc/config/nds32/nds32_init.inc 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32_init.inc 2019-01-25 15:38:32.833242671 +0100 -@@ -0,0 +1,43 @@ -+/* -+ * nds32_init.inc -+ * -+ * NDS32 architecture startup assembler header file -+ * -+ */ -+ -+.macro nds32_init -+ -+ ! Initialize GP for data access -+ la $gp, _SDA_BASE_ -+ -+#if defined(__NDS32_EXT_EX9__) -+ ! Check HW for EX9 -+ mfsr $r0, $MSC_CFG -+ li $r1, (1 << 24) -+ and $r2, $r0, $r1 -+ beqz $r2, 1f -+ -+ ! Initialize the table base of EX9 instruction -+ la $r0, _ITB_BASE_ -+ mtusr $r0, $ITB -+1: -+#endif -+ -+#if defined(__NDS32_EXT_FPU_DP__) || defined(__NDS32_EXT_FPU_SP__) -+ ! Enable FPU -+ mfsr $r0, $FUCOP_CTL -+ ori $r0, $r0, #0x1 -+ mtsr $r0, $FUCOP_CTL -+ dsb -+ -+ ! Enable denormalized flush-to-Zero mode -+ fmfcsr $r0 -+ ori $r0,$r0,#0x1000 -+ fmtcsr $r0 -+ dsb -+#endif -+ -+ ! Initialize default stack pointer -+ la $sp, _stack -+ -+.endm -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.c gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.c 2018-04-22 09:46:39.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.c 2019-01-25 15:38:32.825242648 +0100 -@@ -519,6 +519,7 @@ - { - NDS32_BUILTIN(unspec_fmfcfg, "fmfcfg", FMFCFG) - NDS32_BUILTIN(unspec_fmfcsr, "fmfcsr", FMFCSR) -+ NDS32_BUILTIN(unspec_volatile_rdov, "rdov", RDOV) - NDS32_BUILTIN(unspec_get_current_sp, "get_current_sp", GET_CURRENT_SP) - NDS32_BUILTIN(unspec_return_address, "return_address", RETURN_ADDRESS) - NDS32_BUILTIN(unspec_get_all_pending_int, "get_all_pending_int", -@@ -558,6 +559,31 @@ - NDS32_NO_TARGET_BUILTIN(unspec_ret_itoff, "ret_itoff", RET_ITOFF) - NDS32_NO_TARGET_BUILTIN(unspec_set_current_sp, - "set_current_sp", SET_CURRENT_SP) -+ NDS32_BUILTIN(kabsv2hi2, "kabs16", KABS16) -+ NDS32_BUILTIN(kabsv2hi2, "v_kabs16", V_KABS16) -+ NDS32_BUILTIN(kabsv4qi2, "kabs8", KABS8) -+ NDS32_BUILTIN(kabsv4qi2, "v_kabs8", V_KABS8) -+ NDS32_BUILTIN(sunpkd810, "sunpkd810", SUNPKD810) -+ NDS32_BUILTIN(sunpkd810, "v_sunpkd810", V_SUNPKD810) -+ NDS32_BUILTIN(sunpkd820, "sunpkd820", SUNPKD820) -+ NDS32_BUILTIN(sunpkd820, "v_sunpkd820", V_SUNPKD820) -+ NDS32_BUILTIN(sunpkd830, "sunpkd830", SUNPKD830) -+ NDS32_BUILTIN(sunpkd830, "v_sunpkd830", V_SUNPKD830) -+ NDS32_BUILTIN(sunpkd831, "sunpkd831", SUNPKD831) -+ NDS32_BUILTIN(sunpkd831, "v_sunpkd831", V_SUNPKD831) -+ NDS32_BUILTIN(zunpkd810, "zunpkd810", ZUNPKD810) -+ NDS32_BUILTIN(zunpkd810, "v_zunpkd810", V_ZUNPKD810) -+ NDS32_BUILTIN(zunpkd820, "zunpkd820", ZUNPKD820) -+ NDS32_BUILTIN(zunpkd820, "v_zunpkd820", V_ZUNPKD820) -+ NDS32_BUILTIN(zunpkd830, "zunpkd830", ZUNPKD830) -+ NDS32_BUILTIN(zunpkd830, "v_zunpkd830", V_ZUNPKD830) -+ NDS32_BUILTIN(zunpkd831, "zunpkd831", ZUNPKD831) -+ NDS32_BUILTIN(zunpkd831, "v_zunpkd831", V_ZUNPKD831) -+ NDS32_BUILTIN(unspec_kabs, "kabs", KABS) -+ NDS32_BUILTIN(unaligned_loadv2hi, "get_unaligned_u16x2", UALOAD_U16) -+ NDS32_BUILTIN(unaligned_loadv2hi, "get_unaligned_s16x2", UALOAD_S16) -+ NDS32_BUILTIN(unaligned_loadv4qi, "get_unaligned_u8x4", UALOAD_U8) -+ NDS32_BUILTIN(unaligned_loadv4qi, "get_unaligned_s8x4", UALOAD_S8) - }; - - /* Intrinsics that take just one argument. and the argument is immediate. */ -@@ -593,6 +619,28 @@ - NDS32_BUILTIN(unspec_ffb, "ffb", FFB) - NDS32_BUILTIN(unspec_ffmism, "ffmsim", FFMISM) - NDS32_BUILTIN(unspec_flmism, "flmism", FLMISM) -+ NDS32_BUILTIN(unspec_kaddw, "kaddw", KADDW) -+ NDS32_BUILTIN(unspec_kaddh, "kaddh", KADDH) -+ NDS32_BUILTIN(unspec_ksubw, "ksubw", KSUBW) -+ NDS32_BUILTIN(unspec_ksubh, "ksubh", KSUBH) -+ NDS32_BUILTIN(unspec_kdmbb, "kdmbb", KDMBB) -+ NDS32_BUILTIN(unspec_kdmbb, "v_kdmbb", V_KDMBB) -+ NDS32_BUILTIN(unspec_kdmbt, "kdmbt", KDMBT) -+ NDS32_BUILTIN(unspec_kdmbt, "v_kdmbt", V_KDMBT) -+ NDS32_BUILTIN(unspec_kdmtb, "kdmtb", KDMTB) -+ NDS32_BUILTIN(unspec_kdmtb, "v_kdmtb", V_KDMTB) -+ NDS32_BUILTIN(unspec_kdmtt, "kdmtt", KDMTT) -+ NDS32_BUILTIN(unspec_kdmtt, "v_kdmtt", V_KDMTT) -+ NDS32_BUILTIN(unspec_khmbb, "khmbb", KHMBB) -+ NDS32_BUILTIN(unspec_khmbb, "v_khmbb", V_KHMBB) -+ NDS32_BUILTIN(unspec_khmbt, "khmbt", KHMBT) -+ NDS32_BUILTIN(unspec_khmbt, "v_khmbt", V_KHMBT) -+ NDS32_BUILTIN(unspec_khmtb, "khmtb", KHMTB) -+ NDS32_BUILTIN(unspec_khmtb, "v_khmtb", V_KHMTB) -+ NDS32_BUILTIN(unspec_khmtt, "khmtt", KHMTT) -+ NDS32_BUILTIN(unspec_khmtt, "v_khmtt", V_KHMTT) -+ NDS32_BUILTIN(unspec_kslraw, "kslraw", KSLRAW) -+ NDS32_BUILTIN(unspec_kslrawu, "kslraw_u", KSLRAW_U) - NDS32_BUILTIN(rotrsi3, "rotr", ROTR) - NDS32_BUILTIN(unspec_sva, "sva", SVA) - NDS32_BUILTIN(unspec_svs, "svs", SVS) -@@ -603,7 +651,202 @@ - NDS32_NO_TARGET_BUILTIN(unaligned_store_hw, "unaligned_store_hw", UASTORE_HW) - NDS32_NO_TARGET_BUILTIN(unaligned_storesi, "unaligned_store_hw", UASTORE_W) - NDS32_NO_TARGET_BUILTIN(unaligned_storedi, "unaligned_store_hw", UASTORE_DW) -- -+ NDS32_BUILTIN(addv2hi3, "add16", ADD16) -+ NDS32_BUILTIN(addv2hi3, "v_uadd16", V_UADD16) -+ NDS32_BUILTIN(addv2hi3, "v_sadd16", V_SADD16) -+ NDS32_BUILTIN(raddv2hi3, "radd16", RADD16) -+ NDS32_BUILTIN(raddv2hi3, "v_radd16", V_RADD16) -+ NDS32_BUILTIN(uraddv2hi3, "uradd16", URADD16) -+ NDS32_BUILTIN(uraddv2hi3, "v_uradd16", V_URADD16) -+ NDS32_BUILTIN(kaddv2hi3, "kadd16", KADD16) -+ NDS32_BUILTIN(kaddv2hi3, "v_kadd16", V_KADD16) -+ NDS32_BUILTIN(ukaddv2hi3, "ukadd16", UKADD16) -+ NDS32_BUILTIN(ukaddv2hi3, "v_ukadd16", V_UKADD16) -+ NDS32_BUILTIN(subv2hi3, "sub16", SUB16) -+ NDS32_BUILTIN(subv2hi3, "v_usub16", V_USUB16) -+ NDS32_BUILTIN(subv2hi3, "v_ssub16", V_SSUB16) -+ NDS32_BUILTIN(rsubv2hi3, "rsub16", RSUB16) -+ NDS32_BUILTIN(rsubv2hi3, "v_rsub16", V_RSUB16) -+ NDS32_BUILTIN(ursubv2hi3, "ursub16", URSUB16) -+ NDS32_BUILTIN(ursubv2hi3, "v_ursub16", V_URSUB16) -+ NDS32_BUILTIN(ksubv2hi3, "ksub16", KSUB16) -+ NDS32_BUILTIN(ksubv2hi3, "v_ksub16", V_KSUB16) -+ NDS32_BUILTIN(uksubv2hi3, "uksub16", UKSUB16) -+ NDS32_BUILTIN(uksubv2hi3, "v_uksub16", V_UKSUB16) -+ NDS32_BUILTIN(cras16_1, "cras16", CRAS16) -+ NDS32_BUILTIN(cras16_1, "v_ucras16", V_UCRAS16) -+ NDS32_BUILTIN(cras16_1, "v_scras16", V_SCRAS16) -+ NDS32_BUILTIN(rcras16_1, "rcras16", RCRAS16) -+ NDS32_BUILTIN(rcras16_1, "v_rcras16", V_RCRAS16) -+ NDS32_BUILTIN(urcras16_1, "urcras16", URCRAS16) -+ NDS32_BUILTIN(urcras16_1, "v_urcras16", V_URCRAS16) -+ NDS32_BUILTIN(kcras16_1, "kcras16", KCRAS16) -+ NDS32_BUILTIN(kcras16_1, "v_kcras16", V_KCRAS16) -+ NDS32_BUILTIN(ukcras16_1, "ukcras16", UKCRAS16) -+ NDS32_BUILTIN(ukcras16_1, "v_ukcras16", V_UKCRAS16) -+ NDS32_BUILTIN(crsa16_1, "crsa16", CRSA16) -+ NDS32_BUILTIN(crsa16_1, "v_ucrsa16", V_UCRSA16) -+ NDS32_BUILTIN(crsa16_1, "v_scrsa16", V_SCRSA16) -+ NDS32_BUILTIN(rcrsa16_1, "rcrsa16", RCRSA16) -+ NDS32_BUILTIN(rcrsa16_1, "v_rcrsa16", V_RCRSA16) -+ NDS32_BUILTIN(urcrsa16_1, "urcrsa16", URCRSA16) -+ NDS32_BUILTIN(urcrsa16_1, "v_urcrsa16", V_URCRSA16) -+ NDS32_BUILTIN(kcrsa16_1, "kcrsa16", KCRSA16) -+ NDS32_BUILTIN(kcrsa16_1, "v_kcrsa16", V_KCRSA16) -+ NDS32_BUILTIN(ukcrsa16_1, "ukcrsa16", UKCRSA16) -+ NDS32_BUILTIN(ukcrsa16_1, "v_ukcrsa16", V_UKCRSA16) -+ NDS32_BUILTIN(addv4qi3, "add8", ADD8) -+ NDS32_BUILTIN(addv4qi3, "v_uadd8", V_UADD8) -+ NDS32_BUILTIN(addv4qi3, "v_sadd8", V_SADD8) -+ NDS32_BUILTIN(raddv4qi3, "radd8", RADD8) -+ NDS32_BUILTIN(raddv4qi3, "v_radd8", V_RADD8) -+ NDS32_BUILTIN(uraddv4qi3, "uradd8", URADD8) -+ NDS32_BUILTIN(uraddv4qi3, "v_uradd8", V_URADD8) -+ NDS32_BUILTIN(kaddv4qi3, "kadd8", KADD8) -+ NDS32_BUILTIN(kaddv4qi3, "v_kadd8", V_KADD8) -+ NDS32_BUILTIN(ukaddv4qi3, "ukadd8", UKADD8) -+ NDS32_BUILTIN(ukaddv4qi3, "v_ukadd8", V_UKADD8) -+ NDS32_BUILTIN(subv4qi3, "sub8", SUB8) -+ NDS32_BUILTIN(subv4qi3, "v_usub8", V_USUB8) -+ NDS32_BUILTIN(subv4qi3, "v_ssub8", V_SSUB8) -+ NDS32_BUILTIN(rsubv4qi3, "rsub8", RSUB8) -+ NDS32_BUILTIN(rsubv4qi3, "v_rsub8", V_RSUB8) -+ NDS32_BUILTIN(ursubv4qi3, "ursub8", URSUB8) -+ NDS32_BUILTIN(ursubv4qi3, "v_ursub8", V_URSUB8) -+ NDS32_BUILTIN(ksubv4qi3, "ksub8", KSUB8) -+ NDS32_BUILTIN(ksubv4qi3, "v_ksub8", V_KSUB8) -+ NDS32_BUILTIN(uksubv4qi3, "uksub8", UKSUB8) -+ NDS32_BUILTIN(uksubv4qi3, "v_uksub8", V_UKSUB8) -+ NDS32_BUILTIN(ashrv2hi3, "sra16", SRA16) -+ NDS32_BUILTIN(ashrv2hi3, "v_sra16", V_SRA16) -+ NDS32_BUILTIN(sra16_round, "sra16_u", SRA16_U) -+ NDS32_BUILTIN(sra16_round, "v_sra16_u", V_SRA16_U) -+ NDS32_BUILTIN(lshrv2hi3, "srl16", SRL16) -+ NDS32_BUILTIN(lshrv2hi3, "v_srl16", V_SRL16) -+ NDS32_BUILTIN(srl16_round, "srl16_u", SRL16_U) -+ NDS32_BUILTIN(srl16_round, "v_srl16_u", V_SRL16_U) -+ NDS32_BUILTIN(ashlv2hi3, "sll16", SLL16) -+ NDS32_BUILTIN(ashlv2hi3, "v_sll16", V_SLL16) -+ NDS32_BUILTIN(kslli16, "ksll16", KSLL16) -+ NDS32_BUILTIN(kslli16, "v_ksll16", V_KSLL16) -+ NDS32_BUILTIN(kslra16, "kslra16", KSLRA16) -+ NDS32_BUILTIN(kslra16, "v_kslra16", V_KSLRA16) -+ NDS32_BUILTIN(kslra16_round, "kslra16_u", KSLRA16_U) -+ NDS32_BUILTIN(kslra16_round, "v_kslra16_u", V_KSLRA16_U) -+ NDS32_BUILTIN(cmpeq16, "cmpeq16", CMPEQ16) -+ NDS32_BUILTIN(cmpeq16, "v_scmpeq16", V_SCMPEQ16) -+ NDS32_BUILTIN(cmpeq16, "v_ucmpeq16", V_UCMPEQ16) -+ NDS32_BUILTIN(scmplt16, "scmplt16", SCMPLT16) -+ NDS32_BUILTIN(scmplt16, "v_scmplt16", V_SCMPLT16) -+ NDS32_BUILTIN(scmple16, "scmple16", SCMPLE16) -+ NDS32_BUILTIN(scmple16, "v_scmple16", V_SCMPLE16) -+ NDS32_BUILTIN(ucmplt16, "ucmplt16", UCMPLT16) -+ NDS32_BUILTIN(ucmplt16, "v_ucmplt16", V_UCMPLT16) -+ NDS32_BUILTIN(ucmplt16, "ucmple16", UCMPLE16) -+ NDS32_BUILTIN(ucmplt16, "v_ucmple16", V_UCMPLE16) -+ NDS32_BUILTIN(cmpeq8, "cmpeq8", CMPEQ8) -+ NDS32_BUILTIN(cmpeq8, "v_scmpeq8", V_SCMPEQ8) -+ NDS32_BUILTIN(cmpeq8, "v_ucmpeq8", V_UCMPEQ8) -+ NDS32_BUILTIN(scmplt8, "scmplt8", SCMPLT8) -+ NDS32_BUILTIN(scmplt8, "v_scmplt8", V_SCMPLT8) -+ NDS32_BUILTIN(scmple8, "scmple8", SCMPLE8) -+ NDS32_BUILTIN(scmple8, "v_scmple8", V_SCMPLE8) -+ NDS32_BUILTIN(ucmplt8, "ucmplt8", UCMPLT8) -+ NDS32_BUILTIN(ucmplt8, "v_ucmplt8", V_UCMPLT8) -+ NDS32_BUILTIN(ucmplt8, "ucmple8", UCMPLE8) -+ NDS32_BUILTIN(ucmplt8, "v_ucmple8", V_UCMPLE8) -+ NDS32_BUILTIN(sminv2hi3, "smin16", SMIN16) -+ NDS32_BUILTIN(sminv2hi3, "v_smin16", V_SMIN16) -+ NDS32_BUILTIN(uminv2hi3, "umin16", UMIN16) -+ NDS32_BUILTIN(uminv2hi3, "v_umin16", V_UMIN16) -+ NDS32_BUILTIN(smaxv2hi3, "smax16", SMAX16) -+ NDS32_BUILTIN(smaxv2hi3, "v_smax16", V_SMAX16) -+ NDS32_BUILTIN(umaxv2hi3, "umax16", UMAX16) -+ NDS32_BUILTIN(umaxv2hi3, "v_umax16", V_UMAX16) -+ NDS32_BUILTIN(khm16, "khm16", KHM16) -+ NDS32_BUILTIN(khm16, "v_khm16", V_KHM16) -+ NDS32_BUILTIN(khmx16, "khmx16", KHMX16) -+ NDS32_BUILTIN(khmx16, "v_khmx16", V_KHMX16) -+ NDS32_BUILTIN(sminv4qi3, "smin8", SMIN8) -+ NDS32_BUILTIN(sminv4qi3, "v_smin8", V_SMIN8) -+ NDS32_BUILTIN(uminv4qi3, "umin8", UMIN8) -+ NDS32_BUILTIN(uminv4qi3, "v_umin8", V_UMIN8) -+ NDS32_BUILTIN(smaxv4qi3, "smax8", SMAX8) -+ NDS32_BUILTIN(smaxv4qi3, "v_smax8", V_SMAX8) -+ NDS32_BUILTIN(umaxv4qi3, "umax8", UMAX8) -+ NDS32_BUILTIN(umaxv4qi3, "v_umax8", V_UMAX8) -+ NDS32_BUILTIN(raddsi3, "raddw", RADDW) -+ NDS32_BUILTIN(uraddsi3, "uraddw", URADDW) -+ NDS32_BUILTIN(rsubsi3, "rsubw", RSUBW) -+ NDS32_BUILTIN(ursubsi3, "ursubw", URSUBW) -+ NDS32_BUILTIN(sraiu, "sra_u", SRA_U) -+ NDS32_BUILTIN(kssl, "ksll", KSLL) -+ NDS32_BUILTIN(pkbb, "pkbb16", PKBB16) -+ NDS32_BUILTIN(pkbb, "v_pkbb16", V_PKBB16) -+ NDS32_BUILTIN(pkbt, "pkbt16", PKBT16) -+ NDS32_BUILTIN(pkbt, "v_pkbt16", V_PKBT16) -+ NDS32_BUILTIN(pktb, "pktb16", PKTB16) -+ NDS32_BUILTIN(pktb, "v_pktb16", V_PKTB16) -+ NDS32_BUILTIN(pktt, "pktt16", PKTT16) -+ NDS32_BUILTIN(pktt, "v_pktt16", V_PKTT16) -+ NDS32_BUILTIN(smulsi3_highpart, "smmul", SMMUL) -+ NDS32_BUILTIN(smmul_round, "smmul_u", SMMUL_U) -+ NDS32_BUILTIN(smmwb, "smmwb", SMMWB) -+ NDS32_BUILTIN(smmwb, "v_smmwb", V_SMMWB) -+ NDS32_BUILTIN(smmwb_round, "smmwb_u", SMMWB_U) -+ NDS32_BUILTIN(smmwb_round, "v_smmwb_u", V_SMMWB_U) -+ NDS32_BUILTIN(smmwt, "smmwt", SMMWT) -+ NDS32_BUILTIN(smmwt, "v_smmwt", V_SMMWT) -+ NDS32_BUILTIN(smmwt_round, "smmwt_u", SMMWT_U) -+ NDS32_BUILTIN(smmwt_round, "v_smmwt_u", V_SMMWT_U) -+ NDS32_BUILTIN(smbb, "smbb", SMBB) -+ NDS32_BUILTIN(smbb, "v_smbb", V_SMBB) -+ NDS32_BUILTIN(smbt, "smbt", SMBT) -+ NDS32_BUILTIN(smbt, "v_smbt", V_SMBT) -+ NDS32_BUILTIN(smtt, "smtt", SMTT) -+ NDS32_BUILTIN(smtt, "v_smtt", V_SMTT) -+ NDS32_BUILTIN(kmda, "kmda", KMDA) -+ NDS32_BUILTIN(kmda, "v_kmda", V_KMDA) -+ NDS32_BUILTIN(kmxda, "kmxda", KMXDA) -+ NDS32_BUILTIN(kmxda, "v_kmxda", V_KMXDA) -+ NDS32_BUILTIN(smds, "smds", SMDS) -+ NDS32_BUILTIN(smds, "v_smds", V_SMDS) -+ NDS32_BUILTIN(smdrs, "smdrs", SMDRS) -+ NDS32_BUILTIN(smdrs, "v_smdrs", V_SMDRS) -+ NDS32_BUILTIN(smxdsv, "smxds", SMXDS) -+ NDS32_BUILTIN(smxdsv, "v_smxds", V_SMXDS) -+ NDS32_BUILTIN(smal1, "smal", SMAL) -+ NDS32_BUILTIN(smal1, "v_smal", V_SMAL) -+ NDS32_BUILTIN(bitrev, "bitrev", BITREV) -+ NDS32_BUILTIN(wext, "wext", WEXT) -+ NDS32_BUILTIN(adddi3, "sadd64", SADD64) -+ NDS32_BUILTIN(adddi3, "uadd64", UADD64) -+ NDS32_BUILTIN(radddi3, "radd64", RADD64) -+ NDS32_BUILTIN(uradddi3, "uradd64", URADD64) -+ NDS32_BUILTIN(kadddi3, "kadd64", KADD64) -+ NDS32_BUILTIN(ukadddi3, "ukadd64", UKADD64) -+ NDS32_BUILTIN(subdi3, "ssub64", SSUB64) -+ NDS32_BUILTIN(subdi3, "usub64", USUB64) -+ NDS32_BUILTIN(rsubdi3, "rsub64", RSUB64) -+ NDS32_BUILTIN(ursubdi3, "ursub64", URSUB64) -+ NDS32_BUILTIN(ksubdi3, "ksub64", KSUB64) -+ NDS32_BUILTIN(uksubdi3, "uksub64", UKSUB64) -+ NDS32_BUILTIN(smul16, "smul16", SMUL16) -+ NDS32_BUILTIN(smul16, "v_smul16", V_SMUL16) -+ NDS32_BUILTIN(smulx16, "smulx16", SMULX16) -+ NDS32_BUILTIN(smulx16, "v_smulx16", V_SMULX16) -+ NDS32_BUILTIN(umul16, "umul16", UMUL16) -+ NDS32_BUILTIN(umul16, "v_umul16", V_UMUL16) -+ NDS32_BUILTIN(umulx16, "umulx16", UMULX16) -+ NDS32_BUILTIN(umulx16, "v_umulx16", V_UMULX16) -+ NDS32_BUILTIN(kwmmul, "kwmmul", KWMMUL) -+ NDS32_BUILTIN(kwmmul_round, "kwmmul_u", KWMMUL_U) -+ NDS32_NO_TARGET_BUILTIN(unaligned_storev2hi, -+ "put_unaligned_u16x2", UASTORE_U16) -+ NDS32_NO_TARGET_BUILTIN(unaligned_storev2hi, -+ "put_unaligned_s16x2", UASTORE_S16) -+ NDS32_NO_TARGET_BUILTIN(unaligned_storev4qi, "put_unaligned_u8x4", UASTORE_U8) -+ NDS32_NO_TARGET_BUILTIN(unaligned_storev4qi, "put_unaligned_s8x4", UASTORE_S8) - }; - - /* Two-argument intrinsics with an immediate second argument. */ -@@ -617,6 +860,22 @@ - NDS32_BUILTIN(unspec_clips, "clips", CLIPS) - NDS32_NO_TARGET_BUILTIN(unspec_teqz, "teqz", TEQZ) - NDS32_NO_TARGET_BUILTIN(unspec_tnez, "tnez", TNEZ) -+ NDS32_BUILTIN(ashrv2hi3, "srl16", SRL16) -+ NDS32_BUILTIN(ashrv2hi3, "v_srl16", V_SRL16) -+ NDS32_BUILTIN(srl16_round, "srl16_u", SRL16_U) -+ NDS32_BUILTIN(srl16_round, "v_srl16_u", V_SRL16_U) -+ NDS32_BUILTIN(kslli16, "ksll16", KSLL16) -+ NDS32_BUILTIN(kslli16, "v_ksll16", V_KSLL16) -+ NDS32_BUILTIN(sclip16, "sclip16", SCLIP16) -+ NDS32_BUILTIN(sclip16, "v_sclip16", V_SCLIP16) -+ NDS32_BUILTIN(uclip16, "uclip16", UCLIP16) -+ NDS32_BUILTIN(uclip16, "v_uclip16", V_UCLIP16) -+ NDS32_BUILTIN(sraiu, "sra_u", SRA_U) -+ NDS32_BUILTIN(kssl, "ksll", KSLL) -+ NDS32_BUILTIN(bitrev, "bitrev", BITREV) -+ NDS32_BUILTIN(wext, "wext", WEXT) -+ NDS32_BUILTIN(uclip32, "uclip32", UCLIP32) -+ NDS32_BUILTIN(sclip32, "sclip32", SCLIP32) - }; - - /* Intrinsics that take three arguments. */ -@@ -625,6 +884,67 @@ - NDS32_BUILTIN(unspec_pbsada, "pbsada", PBSADA) - NDS32_NO_TARGET_BUILTIN(bse, "bse", BSE) - NDS32_NO_TARGET_BUILTIN(bsp, "bsp", BSP) -+ NDS32_BUILTIN(kmabb, "kmabb", KMABB) -+ NDS32_BUILTIN(kmabb, "v_kmabb", V_KMABB) -+ NDS32_BUILTIN(kmabt, "kmabt", KMABT) -+ NDS32_BUILTIN(kmabt, "v_kmabt", V_KMABT) -+ NDS32_BUILTIN(kmatt, "kmatt", KMATT) -+ NDS32_BUILTIN(kmatt, "v_kmatt", V_KMATT) -+ NDS32_BUILTIN(kmada, "kmada", KMADA) -+ NDS32_BUILTIN(kmada, "v_kmada", V_KMADA) -+ NDS32_BUILTIN(kmaxda, "kmaxda", KMAXDA) -+ NDS32_BUILTIN(kmaxda, "v_kmaxda", V_KMAXDA) -+ NDS32_BUILTIN(kmads, "kmads", KMADS) -+ NDS32_BUILTIN(kmads, "v_kmads", V_KMADS) -+ NDS32_BUILTIN(kmadrs, "kmadrs", KMADRS) -+ NDS32_BUILTIN(kmadrs, "v_kmadrs", V_KMADRS) -+ NDS32_BUILTIN(kmaxds, "kmaxds", KMAXDS) -+ NDS32_BUILTIN(kmaxds, "v_kmaxds", V_KMAXDS) -+ NDS32_BUILTIN(kmsda, "kmsda", KMSDA) -+ NDS32_BUILTIN(kmsda, "v_kmsda", V_KMSDA) -+ NDS32_BUILTIN(kmsxda, "kmsxda", KMSXDA) -+ NDS32_BUILTIN(kmsxda, "v_kmsxda", V_KMSXDA) -+ NDS32_BUILTIN(bpick1, "bpick", BPICK) -+ NDS32_BUILTIN(smar64_1, "smar64", SMAR64) -+ NDS32_BUILTIN(smsr64, "smsr64", SMSR64) -+ NDS32_BUILTIN(umar64_1, "umar64", UMAR64) -+ NDS32_BUILTIN(umsr64, "umsr64", UMSR64) -+ NDS32_BUILTIN(kmar64_1, "kmar64", KMAR64) -+ NDS32_BUILTIN(kmsr64, "kmsr64", KMSR64) -+ NDS32_BUILTIN(ukmar64_1, "ukmar64", UKMAR64) -+ NDS32_BUILTIN(ukmsr64, "ukmsr64", UKMSR64) -+ NDS32_BUILTIN(smalbb, "smalbb", SMALBB) -+ NDS32_BUILTIN(smalbb, "v_smalbb", V_SMALBB) -+ NDS32_BUILTIN(smalbt, "smalbt", SMALBT) -+ NDS32_BUILTIN(smalbt, "v_smalbt", V_SMALBT) -+ NDS32_BUILTIN(smaltt, "smaltt", SMALTT) -+ NDS32_BUILTIN(smaltt, "v_smaltt", V_SMALTT) -+ NDS32_BUILTIN(smalda1, "smalda", SMALDA) -+ NDS32_BUILTIN(smalda1, "v_smalda", V_SMALDA) -+ NDS32_BUILTIN(smalxda1, "smalxda", SMALXDA) -+ NDS32_BUILTIN(smalxda1, "v_smalxda", V_SMALXDA) -+ NDS32_BUILTIN(smalds1, "smalds", SMALDS) -+ NDS32_BUILTIN(smalds1, "v_smalds", V_SMALDS) -+ NDS32_BUILTIN(smaldrs3, "smaldrs", SMALDRS) -+ NDS32_BUILTIN(smaldrs3, "v_smaldrs", V_SMALDRS) -+ NDS32_BUILTIN(smalxds1, "smalxds", SMALXDS) -+ NDS32_BUILTIN(smalxds1, "v_smalxds", V_SMALXDS) -+ NDS32_BUILTIN(smslda1, "smslda", SMSLDA) -+ NDS32_BUILTIN(smslda1, "v_smslda", V_SMSLDA) -+ NDS32_BUILTIN(smslxda1, "smslxda", SMSLXDA) -+ NDS32_BUILTIN(smslxda1, "v_smslxda", V_SMSLXDA) -+ NDS32_BUILTIN(kmmawb, "kmmawb", KMMAWB) -+ NDS32_BUILTIN(kmmawb, "v_kmmawb", V_KMMAWB) -+ NDS32_BUILTIN(kmmawb_round, "kmmawb_u", KMMAWB_U) -+ NDS32_BUILTIN(kmmawb_round, "v_kmmawb_u", V_KMMAWB_U) -+ NDS32_BUILTIN(kmmawt, "kmmawt", KMMAWT) -+ NDS32_BUILTIN(kmmawt, "v_kmmawt", V_KMMAWT) -+ NDS32_BUILTIN(kmmawt_round, "kmmawt_u", KMMAWT_U) -+ NDS32_BUILTIN(kmmawt_round, "v_kmmawt_u", V_KMMAWT_U) -+ NDS32_BUILTIN(kmmac, "kmmac", KMMAC) -+ NDS32_BUILTIN(kmmac_round, "kmmac_u", KMMAC_U) -+ NDS32_BUILTIN(kmmsb, "kmmsb", KMMSB) -+ NDS32_BUILTIN(kmmsb_round, "kmmsb_u", KMMSB_U) - }; - - /* Three-argument intrinsics with an immediate third argument. */ -@@ -634,6 +954,7 @@ - NDS32_NO_TARGET_BUILTIN(prefetch_hw, "prefetch_hw", DPREF_HW) - NDS32_NO_TARGET_BUILTIN(prefetch_w, "prefetch_w", DPREF_W) - NDS32_NO_TARGET_BUILTIN(prefetch_dw, "prefetch_dw", DPREF_DW) -+ NDS32_BUILTIN(insb, "insb", INSB) - }; - - /* Intrinsics that load a value. */ -@@ -676,6 +997,11 @@ - unsigned i; - struct builtin_description *d; - -+ if (!NDS32_EXT_DSP_P () -+ && fcode > NDS32_BUILTIN_DSP_BEGIN -+ && fcode < NDS32_BUILTIN_DSP_END) -+ error ("don't support DSP extension instructions"); -+ - switch (fcode) - { - /* FPU Register Transfer. */ -@@ -812,6 +1138,9 @@ - case NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL: - emit_insn (gen_cctl_l1d_wball_one_lvl()); - return target; -+ case NDS32_BUILTIN_CLROV: -+ emit_insn (gen_unspec_volatile_clrov ()); -+ return target; - case NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT: - emit_insn (gen_unspec_standby_no_wake_grant ()); - return target; -@@ -947,10 +1276,18 @@ - NDS32_BUILTIN_ ## CODE, BUILT_IN_MD, NULL, NULL_TREE) - - /* Looking for return type and argument can be found in tree.h file. */ -+ tree ptr_char_type_node = build_pointer_type (char_type_node); - tree ptr_uchar_type_node = build_pointer_type (unsigned_char_type_node); - tree ptr_ushort_type_node = build_pointer_type (short_unsigned_type_node); -+ tree ptr_short_type_node = build_pointer_type (short_integer_type_node); - tree ptr_uint_type_node = build_pointer_type (unsigned_type_node); - tree ptr_ulong_type_node = build_pointer_type (long_long_unsigned_type_node); -+ tree v4qi_type_node = build_vector_type (intQI_type_node, 4); -+ tree u_v4qi_type_node = build_vector_type (unsigned_intQI_type_node, 4); -+ tree v2hi_type_node = build_vector_type (intHI_type_node, 2); -+ tree u_v2hi_type_node = build_vector_type (unsigned_intHI_type_node, 2); -+ tree v2si_type_node = build_vector_type (intSI_type_node, 2); -+ tree u_v2si_type_node = build_vector_type (unsigned_intSI_type_node, 2); - - /* Cache. */ - ADD_NDS32_BUILTIN1 ("isync", void, ptr_uint, ISYNC); -@@ -1050,6 +1387,31 @@ - ADD_NDS32_BUILTIN2 ("se_ffmism", integer, unsigned, unsigned, FFMISM); - ADD_NDS32_BUILTIN2 ("se_flmism", integer, unsigned, unsigned, FLMISM); - -+ /* SATURATION */ -+ ADD_NDS32_BUILTIN2 ("kaddw", integer, integer, integer, KADDW); -+ ADD_NDS32_BUILTIN2 ("ksubw", integer, integer, integer, KSUBW); -+ ADD_NDS32_BUILTIN2 ("kaddh", integer, integer, integer, KADDH); -+ ADD_NDS32_BUILTIN2 ("ksubh", integer, integer, integer, KSUBH); -+ ADD_NDS32_BUILTIN2 ("kdmbb", integer, unsigned, unsigned, KDMBB); -+ ADD_NDS32_BUILTIN2 ("v_kdmbb", integer, v2hi, v2hi, V_KDMBB); -+ ADD_NDS32_BUILTIN2 ("kdmbt", integer, unsigned, unsigned, KDMBT); -+ ADD_NDS32_BUILTIN2 ("v_kdmbt", integer, v2hi, v2hi, V_KDMBT); -+ ADD_NDS32_BUILTIN2 ("kdmtb", integer, unsigned, unsigned, KDMTB); -+ ADD_NDS32_BUILTIN2 ("v_kdmtb", integer, v2hi, v2hi, V_KDMTB); -+ ADD_NDS32_BUILTIN2 ("kdmtt", integer, unsigned, unsigned, KDMTT); -+ ADD_NDS32_BUILTIN2 ("v_kdmtt", integer, v2hi, v2hi, V_KDMTT); -+ ADD_NDS32_BUILTIN2 ("khmbb", integer, unsigned, unsigned, KHMBB); -+ ADD_NDS32_BUILTIN2 ("v_khmbb", integer, v2hi, v2hi, V_KHMBB); -+ ADD_NDS32_BUILTIN2 ("khmbt", integer, unsigned, unsigned, KHMBT); -+ ADD_NDS32_BUILTIN2 ("v_khmbt", integer, v2hi, v2hi, V_KHMBT); -+ ADD_NDS32_BUILTIN2 ("khmtb", integer, unsigned, unsigned, KHMTB); -+ ADD_NDS32_BUILTIN2 ("v_khmtb", integer, v2hi, v2hi, V_KHMTB); -+ ADD_NDS32_BUILTIN2 ("khmtt", integer, unsigned, unsigned, KHMTT); -+ ADD_NDS32_BUILTIN2 ("v_khmtt", integer, v2hi, v2hi, V_KHMTT); -+ ADD_NDS32_BUILTIN2 ("kslraw", integer, integer, integer, KSLRAW); -+ ADD_NDS32_BUILTIN2 ("kslraw_u", integer, integer, integer, KSLRAW_U); -+ ADD_NDS32_BUILTIN0 ("rdov", unsigned, RDOV); -+ ADD_NDS32_BUILTIN0 ("clrov", void, CLROV); - - /* ROTR */ - ADD_NDS32_BUILTIN2 ("rotr", unsigned, unsigned, unsigned, ROTR); -@@ -1109,4 +1471,384 @@ - ADD_NDS32_BUILTIN0 ("enable_unaligned", void, ENABLE_UNALIGNED); - ADD_NDS32_BUILTIN0 ("disable_unaligned", void, DISABLE_UNALIGNED); - -+ /* DSP Extension: SIMD 16bit Add and Subtract. */ -+ ADD_NDS32_BUILTIN2 ("add16", unsigned, unsigned, unsigned, ADD16); -+ ADD_NDS32_BUILTIN2 ("v_uadd16", u_v2hi, u_v2hi, u_v2hi, V_UADD16); -+ ADD_NDS32_BUILTIN2 ("v_sadd16", v2hi, v2hi, v2hi, V_SADD16); -+ ADD_NDS32_BUILTIN2 ("radd16", unsigned, unsigned, unsigned, RADD16); -+ ADD_NDS32_BUILTIN2 ("v_radd16", v2hi, v2hi, v2hi, V_RADD16); -+ ADD_NDS32_BUILTIN2 ("uradd16", unsigned, unsigned, unsigned, URADD16); -+ ADD_NDS32_BUILTIN2 ("v_uradd16", u_v2hi, u_v2hi, u_v2hi, V_URADD16); -+ ADD_NDS32_BUILTIN2 ("kadd16", unsigned, unsigned, unsigned, KADD16); -+ ADD_NDS32_BUILTIN2 ("v_kadd16", v2hi, v2hi, v2hi, V_KADD16); -+ ADD_NDS32_BUILTIN2 ("ukadd16", unsigned, unsigned, unsigned, UKADD16); -+ ADD_NDS32_BUILTIN2 ("v_ukadd16", u_v2hi, u_v2hi, u_v2hi, V_UKADD16); -+ ADD_NDS32_BUILTIN2 ("sub16", unsigned, unsigned, unsigned, SUB16); -+ ADD_NDS32_BUILTIN2 ("v_usub16", u_v2hi, u_v2hi, u_v2hi, V_USUB16); -+ ADD_NDS32_BUILTIN2 ("v_ssub16", v2hi, v2hi, v2hi, V_SSUB16); -+ ADD_NDS32_BUILTIN2 ("rsub16", unsigned, unsigned, unsigned, RSUB16); -+ ADD_NDS32_BUILTIN2 ("v_rsub16", v2hi, v2hi, v2hi, V_RSUB16); -+ ADD_NDS32_BUILTIN2 ("ursub16", unsigned, unsigned, unsigned, URSUB16); -+ ADD_NDS32_BUILTIN2 ("v_ursub16", u_v2hi, u_v2hi, u_v2hi, V_URSUB16); -+ ADD_NDS32_BUILTIN2 ("ksub16", unsigned, unsigned, unsigned, KSUB16); -+ ADD_NDS32_BUILTIN2 ("v_ksub16", v2hi, v2hi, v2hi, V_KSUB16); -+ ADD_NDS32_BUILTIN2 ("uksub16", unsigned, unsigned, unsigned, UKSUB16); -+ ADD_NDS32_BUILTIN2 ("v_uksub16", u_v2hi, u_v2hi, u_v2hi, V_UKSUB16); -+ ADD_NDS32_BUILTIN2 ("cras16", unsigned, unsigned, unsigned, CRAS16); -+ ADD_NDS32_BUILTIN2 ("v_ucras16", u_v2hi, u_v2hi, u_v2hi, V_UCRAS16); -+ ADD_NDS32_BUILTIN2 ("v_scras16", v2hi, v2hi, v2hi, V_SCRAS16); -+ ADD_NDS32_BUILTIN2 ("rcras16", unsigned, unsigned, unsigned, RCRAS16); -+ ADD_NDS32_BUILTIN2 ("v_rcras16", v2hi, v2hi, v2hi, V_RCRAS16); -+ ADD_NDS32_BUILTIN2 ("urcras16", unsigned, unsigned, unsigned, URCRAS16); -+ ADD_NDS32_BUILTIN2 ("v_urcras16", u_v2hi, u_v2hi, u_v2hi, V_URCRAS16); -+ ADD_NDS32_BUILTIN2 ("kcras16", unsigned, unsigned, unsigned, KCRAS16); -+ ADD_NDS32_BUILTIN2 ("v_kcras16", v2hi, v2hi, v2hi, V_KCRAS16); -+ ADD_NDS32_BUILTIN2 ("ukcras16", unsigned, unsigned, unsigned, UKCRAS16); -+ ADD_NDS32_BUILTIN2 ("v_ukcras16", u_v2hi, u_v2hi, u_v2hi, V_UKCRAS16); -+ ADD_NDS32_BUILTIN2 ("crsa16", unsigned, unsigned, unsigned, CRSA16); -+ ADD_NDS32_BUILTIN2 ("v_ucrsa16", u_v2hi, u_v2hi, u_v2hi, V_UCRSA16); -+ ADD_NDS32_BUILTIN2 ("v_scrsa16", v2hi, v2hi, v2hi, V_SCRSA16); -+ ADD_NDS32_BUILTIN2 ("rcrsa16", unsigned, unsigned, unsigned, RCRSA16); -+ ADD_NDS32_BUILTIN2 ("v_rcrsa16", v2hi, v2hi, v2hi, V_RCRSA16); -+ ADD_NDS32_BUILTIN2 ("urcrsa16", unsigned, unsigned, unsigned, URCRSA16); -+ ADD_NDS32_BUILTIN2 ("v_urcrsa16", u_v2hi, u_v2hi, u_v2hi, V_URCRSA16); -+ ADD_NDS32_BUILTIN2 ("kcrsa16", unsigned, unsigned, unsigned, KCRSA16); -+ ADD_NDS32_BUILTIN2 ("v_kcrsa16", v2hi, v2hi, v2hi, V_KCRSA16); -+ ADD_NDS32_BUILTIN2 ("ukcrsa16", unsigned, unsigned, unsigned, UKCRSA16); -+ ADD_NDS32_BUILTIN2 ("v_ukcrsa16", u_v2hi, u_v2hi, u_v2hi, V_UKCRSA16); -+ -+ /* DSP Extension: SIMD 8bit Add and Subtract. */ -+ ADD_NDS32_BUILTIN2 ("add8", integer, integer, integer, ADD8); -+ ADD_NDS32_BUILTIN2 ("v_uadd8", u_v4qi, u_v4qi, u_v4qi, V_UADD8); -+ ADD_NDS32_BUILTIN2 ("v_sadd8", v4qi, v4qi, v4qi, V_SADD8); -+ ADD_NDS32_BUILTIN2 ("radd8", unsigned, unsigned, unsigned, RADD8); -+ ADD_NDS32_BUILTIN2 ("v_radd8", v4qi, v4qi, v4qi, V_RADD8); -+ ADD_NDS32_BUILTIN2 ("uradd8", unsigned, unsigned, unsigned, URADD8); -+ ADD_NDS32_BUILTIN2 ("v_uradd8", u_v4qi, u_v4qi, u_v4qi, V_URADD8); -+ ADD_NDS32_BUILTIN2 ("kadd8", unsigned, unsigned, unsigned, KADD8); -+ ADD_NDS32_BUILTIN2 ("v_kadd8", v4qi, v4qi, v4qi, V_KADD8); -+ ADD_NDS32_BUILTIN2 ("ukadd8", unsigned, unsigned, unsigned, UKADD8); -+ ADD_NDS32_BUILTIN2 ("v_ukadd8", u_v4qi, u_v4qi, u_v4qi, V_UKADD8); -+ ADD_NDS32_BUILTIN2 ("sub8", integer, integer, integer, SUB8); -+ ADD_NDS32_BUILTIN2 ("v_usub8", u_v4qi, u_v4qi, u_v4qi, V_USUB8); -+ ADD_NDS32_BUILTIN2 ("v_ssub8", v4qi, v4qi, v4qi, V_SSUB8); -+ ADD_NDS32_BUILTIN2 ("rsub8", unsigned, unsigned, unsigned, RSUB8); -+ ADD_NDS32_BUILTIN2 ("v_rsub8", v4qi, v4qi, v4qi, V_RSUB8); -+ ADD_NDS32_BUILTIN2 ("ursub8", unsigned, unsigned, unsigned, URSUB8); -+ ADD_NDS32_BUILTIN2 ("v_ursub8", u_v4qi, u_v4qi, u_v4qi, V_URSUB8); -+ ADD_NDS32_BUILTIN2 ("ksub8", unsigned, unsigned, unsigned, KSUB8); -+ ADD_NDS32_BUILTIN2 ("v_ksub8", v4qi, v4qi, v4qi, V_KSUB8); -+ ADD_NDS32_BUILTIN2 ("uksub8", unsigned, unsigned, unsigned, UKSUB8); -+ ADD_NDS32_BUILTIN2 ("v_uksub8", u_v4qi, u_v4qi, u_v4qi, V_UKSUB8); -+ -+ /* DSP Extension: SIMD 16bit Shift. */ -+ ADD_NDS32_BUILTIN2 ("sra16", unsigned, unsigned, unsigned, SRA16); -+ ADD_NDS32_BUILTIN2 ("v_sra16", v2hi, v2hi, unsigned, V_SRA16); -+ ADD_NDS32_BUILTIN2 ("sra16_u", unsigned, unsigned, unsigned, SRA16_U); -+ ADD_NDS32_BUILTIN2 ("v_sra16_u", v2hi, v2hi, unsigned, V_SRA16_U); -+ ADD_NDS32_BUILTIN2 ("srl16", unsigned, unsigned, unsigned, SRL16); -+ ADD_NDS32_BUILTIN2 ("v_srl16", u_v2hi, u_v2hi, unsigned, V_SRL16); -+ ADD_NDS32_BUILTIN2 ("srl16_u", unsigned, unsigned, unsigned, SRL16_U); -+ ADD_NDS32_BUILTIN2 ("v_srl16_u", u_v2hi, u_v2hi, unsigned, V_SRL16_U); -+ ADD_NDS32_BUILTIN2 ("sll16", unsigned, unsigned, unsigned, SLL16); -+ ADD_NDS32_BUILTIN2 ("v_sll16", u_v2hi, u_v2hi, unsigned, V_SLL16); -+ ADD_NDS32_BUILTIN2 ("ksll16", unsigned, unsigned, unsigned, KSLL16); -+ ADD_NDS32_BUILTIN2 ("v_ksll16", v2hi, v2hi, unsigned, V_KSLL16); -+ ADD_NDS32_BUILTIN2 ("kslra16", unsigned, unsigned, unsigned, KSLRA16); -+ ADD_NDS32_BUILTIN2 ("v_kslra16", v2hi, v2hi, unsigned, V_KSLRA16); -+ ADD_NDS32_BUILTIN2 ("kslra16_u", unsigned, unsigned, unsigned, KSLRA16_U); -+ ADD_NDS32_BUILTIN2 ("v_kslra16_u", v2hi, v2hi, unsigned, V_KSLRA16_U); -+ -+ /* DSP Extension: 16bit Compare. */ -+ ADD_NDS32_BUILTIN2 ("cmpeq16", unsigned, unsigned, unsigned, CMPEQ16); -+ ADD_NDS32_BUILTIN2 ("v_scmpeq16", u_v2hi, v2hi, v2hi, V_SCMPEQ16); -+ ADD_NDS32_BUILTIN2 ("v_ucmpeq16", u_v2hi, u_v2hi, u_v2hi, V_UCMPEQ16); -+ ADD_NDS32_BUILTIN2 ("scmplt16", unsigned, unsigned, unsigned, SCMPLT16); -+ ADD_NDS32_BUILTIN2 ("v_scmplt16", u_v2hi, v2hi, v2hi, V_SCMPLT16); -+ ADD_NDS32_BUILTIN2 ("scmple16", unsigned, unsigned, unsigned, SCMPLE16); -+ ADD_NDS32_BUILTIN2 ("v_scmple16", u_v2hi, v2hi, v2hi, V_SCMPLE16); -+ ADD_NDS32_BUILTIN2 ("ucmplt16", unsigned, unsigned, unsigned, UCMPLT16); -+ ADD_NDS32_BUILTIN2 ("v_ucmplt16", u_v2hi, u_v2hi, u_v2hi, V_UCMPLT16); -+ ADD_NDS32_BUILTIN2 ("ucmple16", unsigned, unsigned, unsigned, UCMPLE16); -+ ADD_NDS32_BUILTIN2 ("v_ucmple16", u_v2hi, u_v2hi, u_v2hi, V_UCMPLE16); -+ -+ /* DSP Extension: 8bit Compare. */ -+ ADD_NDS32_BUILTIN2 ("cmpeq8", unsigned, unsigned, unsigned, CMPEQ8); -+ ADD_NDS32_BUILTIN2 ("v_scmpeq8", u_v4qi, v4qi, v4qi, V_SCMPEQ8); -+ ADD_NDS32_BUILTIN2 ("v_ucmpeq8", u_v4qi, u_v4qi, u_v4qi, V_UCMPEQ8); -+ ADD_NDS32_BUILTIN2 ("scmplt8", unsigned, unsigned, unsigned, SCMPLT8); -+ ADD_NDS32_BUILTIN2 ("v_scmplt8", u_v4qi, v4qi, v4qi, V_SCMPLT8); -+ ADD_NDS32_BUILTIN2 ("scmple8", unsigned, unsigned, unsigned, SCMPLE8); -+ ADD_NDS32_BUILTIN2 ("v_scmple8", u_v4qi, v4qi, v4qi, V_SCMPLE8); -+ ADD_NDS32_BUILTIN2 ("ucmplt8", unsigned, unsigned, unsigned, UCMPLT8); -+ ADD_NDS32_BUILTIN2 ("v_ucmplt8", u_v4qi, u_v4qi, u_v4qi, V_UCMPLT8); -+ ADD_NDS32_BUILTIN2 ("ucmple8", unsigned, unsigned, unsigned, UCMPLE8); -+ ADD_NDS32_BUILTIN2 ("v_ucmple8", u_v4qi, u_v4qi, u_v4qi, V_UCMPLE8); -+ -+ /* DSP Extension: SIMD 16bit MISC. */ -+ ADD_NDS32_BUILTIN2 ("smin16", unsigned, unsigned, unsigned, SMIN16); -+ ADD_NDS32_BUILTIN2 ("v_smin16", v2hi, v2hi, v2hi, V_SMIN16); -+ ADD_NDS32_BUILTIN2 ("umin16", unsigned, unsigned, unsigned, UMIN16); -+ ADD_NDS32_BUILTIN2 ("v_umin16", u_v2hi, u_v2hi, u_v2hi, V_UMIN16); -+ ADD_NDS32_BUILTIN2 ("smax16", unsigned, unsigned, unsigned, SMAX16); -+ ADD_NDS32_BUILTIN2 ("v_smax16", v2hi, v2hi, v2hi, V_SMAX16); -+ ADD_NDS32_BUILTIN2 ("umax16", unsigned, unsigned, unsigned, UMAX16); -+ ADD_NDS32_BUILTIN2 ("v_umax16", u_v2hi, u_v2hi, u_v2hi, V_UMAX16); -+ ADD_NDS32_BUILTIN2 ("sclip16", unsigned, unsigned, unsigned, SCLIP16); -+ ADD_NDS32_BUILTIN2 ("v_sclip16", v2hi, v2hi, unsigned, V_SCLIP16); -+ ADD_NDS32_BUILTIN2 ("uclip16", unsigned, unsigned, unsigned, UCLIP16); -+ ADD_NDS32_BUILTIN2 ("v_uclip16", v2hi, v2hi, unsigned, V_UCLIP16); -+ ADD_NDS32_BUILTIN2 ("khm16", unsigned, unsigned, unsigned, KHM16); -+ ADD_NDS32_BUILTIN2 ("v_khm16", v2hi, v2hi, v2hi, V_KHM16); -+ ADD_NDS32_BUILTIN2 ("khmx16", unsigned, unsigned, unsigned, KHMX16); -+ ADD_NDS32_BUILTIN2 ("v_khmx16", v2hi, v2hi, v2hi, V_KHMX16); -+ ADD_NDS32_BUILTIN1 ("kabs16", unsigned, unsigned, KABS16); -+ ADD_NDS32_BUILTIN1 ("v_kabs16", v2hi, v2hi, V_KABS16); -+ ADD_NDS32_BUILTIN2 ("smul16", long_long_unsigned, unsigned, unsigned, SMUL16); -+ ADD_NDS32_BUILTIN2 ("v_smul16", v2si, v2hi, v2hi, V_SMUL16); -+ ADD_NDS32_BUILTIN2 ("smulx16", -+ long_long_unsigned, unsigned, unsigned, SMULX16); -+ ADD_NDS32_BUILTIN2 ("v_smulx16", v2si, v2hi, v2hi, V_SMULX16); -+ ADD_NDS32_BUILTIN2 ("umul16", long_long_unsigned, unsigned, unsigned, UMUL16); -+ ADD_NDS32_BUILTIN2 ("v_umul16", u_v2si, u_v2hi, u_v2hi, V_UMUL16); -+ ADD_NDS32_BUILTIN2 ("umulx16", -+ long_long_unsigned, unsigned, unsigned, UMULX16); -+ ADD_NDS32_BUILTIN2 ("v_umulx16", u_v2si, u_v2hi, u_v2hi, V_UMULX16); -+ -+ /* DSP Extension: SIMD 8bit MISC. */ -+ ADD_NDS32_BUILTIN2 ("smin8", unsigned, unsigned, unsigned, SMIN8); -+ ADD_NDS32_BUILTIN2 ("v_smin8", v4qi, v4qi, v4qi, V_SMIN8); -+ ADD_NDS32_BUILTIN2 ("umin8", unsigned, unsigned, unsigned, UMIN8); -+ ADD_NDS32_BUILTIN2 ("v_umin8", u_v4qi, u_v4qi, u_v4qi, V_UMIN8); -+ ADD_NDS32_BUILTIN2 ("smax8", unsigned, unsigned, unsigned, SMAX8); -+ ADD_NDS32_BUILTIN2 ("v_smax8", v4qi, v4qi, v4qi, V_SMAX8); -+ ADD_NDS32_BUILTIN2 ("umax8", unsigned, unsigned, unsigned, UMAX8); -+ ADD_NDS32_BUILTIN2 ("v_umax8", u_v4qi, u_v4qi, u_v4qi, V_UMAX8); -+ ADD_NDS32_BUILTIN1 ("kabs8", unsigned, unsigned, KABS8); -+ ADD_NDS32_BUILTIN1 ("v_kabs8", v4qi, v4qi, V_KABS8); -+ -+ /* DSP Extension: 8bit Unpacking. */ -+ ADD_NDS32_BUILTIN1 ("sunpkd810", unsigned, unsigned, SUNPKD810); -+ ADD_NDS32_BUILTIN1 ("v_sunpkd810", v2hi, v4qi, V_SUNPKD810); -+ ADD_NDS32_BUILTIN1 ("sunpkd820", unsigned, unsigned, SUNPKD820); -+ ADD_NDS32_BUILTIN1 ("v_sunpkd820", v2hi, v4qi, V_SUNPKD820); -+ ADD_NDS32_BUILTIN1 ("sunpkd830", unsigned, unsigned, SUNPKD830); -+ ADD_NDS32_BUILTIN1 ("v_sunpkd830", v2hi, v4qi, V_SUNPKD830); -+ ADD_NDS32_BUILTIN1 ("sunpkd831", unsigned, unsigned, SUNPKD831); -+ ADD_NDS32_BUILTIN1 ("v_sunpkd831", v2hi, v4qi, V_SUNPKD831); -+ ADD_NDS32_BUILTIN1 ("zunpkd810", unsigned, unsigned, ZUNPKD810); -+ ADD_NDS32_BUILTIN1 ("v_zunpkd810", u_v2hi, u_v4qi, V_ZUNPKD810); -+ ADD_NDS32_BUILTIN1 ("zunpkd820", unsigned, unsigned, ZUNPKD820); -+ ADD_NDS32_BUILTIN1 ("v_zunpkd820", u_v2hi, u_v4qi, V_ZUNPKD820); -+ ADD_NDS32_BUILTIN1 ("zunpkd830", unsigned, unsigned, ZUNPKD830); -+ ADD_NDS32_BUILTIN1 ("v_zunpkd830", u_v2hi, u_v4qi, V_ZUNPKD830); -+ ADD_NDS32_BUILTIN1 ("zunpkd831", unsigned, unsigned, ZUNPKD831); -+ ADD_NDS32_BUILTIN1 ("v_zunpkd831", u_v2hi, u_v4qi, V_ZUNPKD831); -+ -+ /* DSP Extension: 32bit Add and Subtract. */ -+ ADD_NDS32_BUILTIN2 ("raddw", integer, integer, integer, RADDW); -+ ADD_NDS32_BUILTIN2 ("uraddw", unsigned, unsigned, unsigned, URADDW); -+ ADD_NDS32_BUILTIN2 ("rsubw", integer, integer, integer, RSUBW); -+ ADD_NDS32_BUILTIN2 ("ursubw", unsigned, unsigned, unsigned, URSUBW); -+ -+ /* DSP Extension: 32bit Shift. */ -+ ADD_NDS32_BUILTIN2 ("sra_u", integer, integer, unsigned, SRA_U); -+ ADD_NDS32_BUILTIN2 ("ksll", integer, integer, unsigned, KSLL); -+ -+ /* DSP Extension: 16bit Packing. */ -+ ADD_NDS32_BUILTIN2 ("pkbb16", unsigned, unsigned, unsigned, PKBB16); -+ ADD_NDS32_BUILTIN2 ("v_pkbb16", u_v2hi, u_v2hi, u_v2hi, V_PKBB16); -+ ADD_NDS32_BUILTIN2 ("pkbt16", unsigned, unsigned, unsigned, PKBT16); -+ ADD_NDS32_BUILTIN2 ("v_pkbt16", u_v2hi, u_v2hi, u_v2hi, V_PKBT16); -+ ADD_NDS32_BUILTIN2 ("pktb16", unsigned, unsigned, unsigned, PKTB16); -+ ADD_NDS32_BUILTIN2 ("v_pktb16", u_v2hi, u_v2hi, u_v2hi, V_PKTB16); -+ ADD_NDS32_BUILTIN2 ("pktt16", unsigned, unsigned, unsigned, PKTT16); -+ ADD_NDS32_BUILTIN2 ("v_pktt16", u_v2hi, u_v2hi, u_v2hi, V_PKTT16); -+ -+ /* DSP Extension: Signed MSW 32x32 Multiply and ADD. */ -+ ADD_NDS32_BUILTIN2 ("smmul", integer, integer, integer, SMMUL); -+ ADD_NDS32_BUILTIN2 ("smmul_u", integer, integer, integer, SMMUL_U); -+ ADD_NDS32_BUILTIN3 ("kmmac", integer, integer, integer, integer, KMMAC); -+ ADD_NDS32_BUILTIN3 ("kmmac_u", integer, integer, integer, integer, KMMAC_U); -+ ADD_NDS32_BUILTIN3 ("kmmsb", integer, integer, integer, integer, KMMSB); -+ ADD_NDS32_BUILTIN3 ("kmmsb_u", integer, integer, integer, integer, KMMSB_U); -+ ADD_NDS32_BUILTIN2 ("kwmmul", integer, integer, integer, KWMMUL); -+ ADD_NDS32_BUILTIN2 ("kwmmul_u", integer, integer, integer, KWMMUL_U); -+ -+ /* DSP Extension: Most Significant Word 32x16 Multiply and ADD. */ -+ ADD_NDS32_BUILTIN2 ("smmwb", integer, integer, unsigned, SMMWB); -+ ADD_NDS32_BUILTIN2 ("v_smmwb", integer, integer, v2hi, V_SMMWB); -+ ADD_NDS32_BUILTIN2 ("smmwb_u", integer, integer, unsigned, SMMWB_U); -+ ADD_NDS32_BUILTIN2 ("v_smmwb_u", integer, integer, v2hi, V_SMMWB_U); -+ ADD_NDS32_BUILTIN2 ("smmwt", integer, integer, unsigned, SMMWT); -+ ADD_NDS32_BUILTIN2 ("v_smmwt", integer, integer, v2hi, V_SMMWT); -+ ADD_NDS32_BUILTIN2 ("smmwt_u", integer, integer, unsigned, SMMWT_U); -+ ADD_NDS32_BUILTIN2 ("v_smmwt_u", integer, integer, v2hi, V_SMMWT_U); -+ ADD_NDS32_BUILTIN3 ("kmmawb", integer, integer, integer, unsigned, KMMAWB); -+ ADD_NDS32_BUILTIN3 ("v_kmmawb", integer, integer, integer, v2hi, V_KMMAWB); -+ ADD_NDS32_BUILTIN3 ("kmmawb_u", -+ integer, integer, integer, unsigned, KMMAWB_U); -+ ADD_NDS32_BUILTIN3 ("v_kmmawb_u", -+ integer, integer, integer, v2hi, V_KMMAWB_U); -+ ADD_NDS32_BUILTIN3 ("kmmawt", integer, integer, integer, unsigned, KMMAWT); -+ ADD_NDS32_BUILTIN3 ("v_kmmawt", integer, integer, integer, v2hi, V_KMMAWT); -+ ADD_NDS32_BUILTIN3 ("kmmawt_u", -+ integer, integer, integer, unsigned, KMMAWT_U); -+ ADD_NDS32_BUILTIN3 ("v_kmmawt_u", -+ integer, integer, integer, v2hi, V_KMMAWT_U); -+ -+ /* DSP Extension: Signed 16bit Multiply with ADD/Subtract. */ -+ ADD_NDS32_BUILTIN2 ("smbb", integer, unsigned, unsigned, SMBB); -+ ADD_NDS32_BUILTIN2 ("v_smbb", integer, v2hi, v2hi, V_SMBB); -+ ADD_NDS32_BUILTIN2 ("smbt", integer, unsigned, unsigned, SMBT); -+ ADD_NDS32_BUILTIN2 ("v_smbt", integer, v2hi, v2hi, V_SMBT); -+ ADD_NDS32_BUILTIN2 ("smtt", integer, unsigned, unsigned, SMTT); -+ ADD_NDS32_BUILTIN2 ("v_smtt", integer, v2hi, v2hi, V_SMTT); -+ ADD_NDS32_BUILTIN2 ("kmda", integer, unsigned, unsigned, KMDA); -+ ADD_NDS32_BUILTIN2 ("v_kmda", integer, v2hi, v2hi, V_KMDA); -+ ADD_NDS32_BUILTIN2 ("kmxda", integer, unsigned, unsigned, KMXDA); -+ ADD_NDS32_BUILTIN2 ("v_kmxda", integer, v2hi, v2hi, V_KMXDA); -+ ADD_NDS32_BUILTIN2 ("smds", integer, unsigned, unsigned, SMDS); -+ ADD_NDS32_BUILTIN2 ("v_smds", integer, v2hi, v2hi, V_SMDS); -+ ADD_NDS32_BUILTIN2 ("smdrs", integer, unsigned, unsigned, SMDRS); -+ ADD_NDS32_BUILTIN2 ("v_smdrs", integer, v2hi, v2hi, V_SMDRS); -+ ADD_NDS32_BUILTIN2 ("smxds", integer, unsigned, unsigned, SMXDS); -+ ADD_NDS32_BUILTIN2 ("v_smxds", integer, v2hi, v2hi, V_SMXDS); -+ ADD_NDS32_BUILTIN3 ("kmabb", integer, integer, unsigned, unsigned, KMABB); -+ ADD_NDS32_BUILTIN3 ("v_kmabb", integer, integer, v2hi, v2hi, V_KMABB); -+ ADD_NDS32_BUILTIN3 ("kmabt", integer, integer, unsigned, unsigned, KMABT); -+ ADD_NDS32_BUILTIN3 ("v_kmabt", integer, integer, v2hi, v2hi, V_KMABT); -+ ADD_NDS32_BUILTIN3 ("kmatt", integer, integer, unsigned, unsigned, KMATT); -+ ADD_NDS32_BUILTIN3 ("v_kmatt", integer, integer, v2hi, v2hi, V_KMATT); -+ ADD_NDS32_BUILTIN3 ("kmada", integer, integer, unsigned, unsigned, KMADA); -+ ADD_NDS32_BUILTIN3 ("v_kmada", integer, integer, v2hi, v2hi, V_KMADA); -+ ADD_NDS32_BUILTIN3 ("kmaxda", integer, integer, unsigned, unsigned, KMAXDA); -+ ADD_NDS32_BUILTIN3 ("v_kmaxda", integer, integer, v2hi, v2hi, V_KMAXDA); -+ ADD_NDS32_BUILTIN3 ("kmads", integer, integer, unsigned, unsigned, KMADS); -+ ADD_NDS32_BUILTIN3 ("v_kmads", integer, integer, v2hi, v2hi, V_KMADS); -+ ADD_NDS32_BUILTIN3 ("kmadrs", integer, integer, unsigned, unsigned, KMADRS); -+ ADD_NDS32_BUILTIN3 ("v_kmadrs", integer, integer, v2hi, v2hi, V_KMADRS); -+ ADD_NDS32_BUILTIN3 ("kmaxds", integer, integer, unsigned, unsigned, KMAXDS); -+ ADD_NDS32_BUILTIN3 ("v_kmaxds", integer, integer, v2hi, v2hi, V_KMAXDS); -+ ADD_NDS32_BUILTIN3 ("kmsda", integer, integer, unsigned, unsigned, KMSDA); -+ ADD_NDS32_BUILTIN3 ("v_kmsda", integer, integer, v2hi, v2hi, V_KMSDA); -+ ADD_NDS32_BUILTIN3 ("kmsxda", integer, integer, unsigned, unsigned, KMSXDA); -+ ADD_NDS32_BUILTIN3 ("v_kmsxda", integer, integer, v2hi, v2hi, V_KMSXDA); -+ -+ /* DSP Extension: Signed 16bit Multiply with 64bit ADD/Subtract. */ -+ ADD_NDS32_BUILTIN2 ("smal", long_long_integer, -+ long_long_integer, unsigned, SMAL); -+ ADD_NDS32_BUILTIN2 ("v_smal", long_long_integer, -+ long_long_integer, v2hi, V_SMAL); -+ -+ /* DSP Extension: 32bit MISC. */ -+ ADD_NDS32_BUILTIN2 ("bitrev", unsigned, unsigned, unsigned, BITREV); -+ ADD_NDS32_BUILTIN2 ("wext", unsigned, long_long_integer, unsigned, WEXT); -+ ADD_NDS32_BUILTIN3 ("bpick", unsigned, unsigned, unsigned, unsigned, BPICK); -+ ADD_NDS32_BUILTIN3 ("insb", unsigned, unsigned, unsigned, unsigned, INSB); -+ -+ /* DSP Extension: 64bit Add and Subtract. */ -+ ADD_NDS32_BUILTIN2 ("sadd64", long_long_integer, -+ long_long_integer, long_long_integer, SADD64); -+ ADD_NDS32_BUILTIN2 ("uadd64", long_long_unsigned, -+ long_long_unsigned, long_long_unsigned, UADD64); -+ ADD_NDS32_BUILTIN2 ("radd64", long_long_integer, -+ long_long_integer, long_long_integer, RADD64); -+ ADD_NDS32_BUILTIN2 ("uradd64", long_long_unsigned, -+ long_long_unsigned, long_long_unsigned, URADD64); -+ ADD_NDS32_BUILTIN2 ("kadd64", long_long_integer, -+ long_long_integer, long_long_integer, KADD64); -+ ADD_NDS32_BUILTIN2 ("ukadd64", long_long_unsigned, -+ long_long_unsigned, long_long_unsigned, UKADD64); -+ ADD_NDS32_BUILTIN2 ("ssub64", long_long_integer, -+ long_long_integer, long_long_integer, SSUB64); -+ ADD_NDS32_BUILTIN2 ("usub64", long_long_unsigned, -+ long_long_unsigned, long_long_unsigned, USUB64); -+ ADD_NDS32_BUILTIN2 ("rsub64", long_long_integer, -+ long_long_integer, long_long_integer, RSUB64); -+ ADD_NDS32_BUILTIN2 ("ursub64", long_long_unsigned, -+ long_long_unsigned, long_long_unsigned, URSUB64); -+ ADD_NDS32_BUILTIN2 ("ksub64", long_long_integer, -+ long_long_integer, long_long_integer, KSUB64); -+ ADD_NDS32_BUILTIN2 ("uksub64", long_long_unsigned, -+ long_long_unsigned, long_long_unsigned, UKSUB64); -+ -+ /* DSP Extension: 32bit Multiply with 64bit Add/Subtract. */ -+ ADD_NDS32_BUILTIN3 ("smar64", long_long_integer, -+ long_long_integer, integer, integer, SMAR64); -+ ADD_NDS32_BUILTIN3 ("smsr64", long_long_integer, -+ long_long_integer, integer, integer, SMSR64); -+ ADD_NDS32_BUILTIN3 ("umar64", long_long_unsigned, -+ long_long_unsigned, unsigned, unsigned, UMAR64); -+ ADD_NDS32_BUILTIN3 ("umsr64", long_long_unsigned, -+ long_long_unsigned, unsigned, unsigned, UMSR64); -+ ADD_NDS32_BUILTIN3 ("kmar64", long_long_integer, -+ long_long_integer, integer, integer, KMAR64); -+ ADD_NDS32_BUILTIN3 ("kmsr64", long_long_integer, -+ long_long_integer, integer, integer, KMSR64); -+ ADD_NDS32_BUILTIN3 ("ukmar64", long_long_unsigned, -+ long_long_unsigned, unsigned, unsigned, UKMAR64); -+ ADD_NDS32_BUILTIN3 ("ukmsr64", long_long_unsigned, -+ long_long_unsigned, unsigned, unsigned, UKMSR64); -+ -+ /* DSP Extension: Signed 16bit Multiply with 64bit Add/Subtract. */ -+ ADD_NDS32_BUILTIN3 ("smalbb", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALBB); -+ ADD_NDS32_BUILTIN3 ("v_smalbb", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALBB); -+ ADD_NDS32_BUILTIN3 ("smalbt", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALBT); -+ ADD_NDS32_BUILTIN3 ("v_smalbt", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALBT); -+ ADD_NDS32_BUILTIN3 ("smaltt", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALTT); -+ ADD_NDS32_BUILTIN3 ("v_smaltt", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALTT); -+ ADD_NDS32_BUILTIN3 ("smalda", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALDA); -+ ADD_NDS32_BUILTIN3 ("v_smalda", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALDA); -+ ADD_NDS32_BUILTIN3 ("smalxda", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALXDA); -+ ADD_NDS32_BUILTIN3 ("v_smalxda", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALXDA); -+ ADD_NDS32_BUILTIN3 ("smalds", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALDS); -+ ADD_NDS32_BUILTIN3 ("v_smalds", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALDS); -+ ADD_NDS32_BUILTIN3 ("smaldrs", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALDRS); -+ ADD_NDS32_BUILTIN3 ("v_smaldrs", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALDRS); -+ ADD_NDS32_BUILTIN3 ("smalxds", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMALXDS); -+ ADD_NDS32_BUILTIN3 ("v_smalxds", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMALXDS); -+ ADD_NDS32_BUILTIN3 ("smslda", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMSLDA); -+ ADD_NDS32_BUILTIN3 ("v_smslda", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMSLDA); -+ ADD_NDS32_BUILTIN3 ("smslxda", long_long_integer, -+ long_long_integer, unsigned, unsigned, SMSLXDA); -+ ADD_NDS32_BUILTIN3 ("v_smslxda", long_long_integer, -+ long_long_integer, v2hi, v2hi, V_SMSLXDA); -+ -+ /* DSP Extension: augmented baseline. */ -+ ADD_NDS32_BUILTIN2 ("uclip32", unsigned, integer, unsigned, UCLIP32); -+ ADD_NDS32_BUILTIN2 ("sclip32", integer, integer, unsigned, SCLIP32); -+ ADD_NDS32_BUILTIN1 ("kabs", integer, integer, KABS); -+ -+ /* DSP Extension: vector type unaligned Load/Store */ -+ ADD_NDS32_BUILTIN1 ("get_unaligned_u16x2", u_v2hi, ptr_ushort, UALOAD_U16); -+ ADD_NDS32_BUILTIN1 ("get_unaligned_s16x2", v2hi, ptr_short, UALOAD_S16); -+ ADD_NDS32_BUILTIN1 ("get_unaligned_u8x4", u_v4qi, ptr_uchar, UALOAD_U8); -+ ADD_NDS32_BUILTIN1 ("get_unaligned_s8x4", v4qi, ptr_char, UALOAD_S8); -+ ADD_NDS32_BUILTIN2 ("put_unaligned_u16x2", void, ptr_ushort, -+ u_v2hi, UASTORE_U16); -+ ADD_NDS32_BUILTIN2 ("put_unaligned_s16x2", void, ptr_short, -+ v2hi, UASTORE_S16); -+ ADD_NDS32_BUILTIN2 ("put_unaligned_u8x4", void, ptr_uchar, -+ u_v4qi, UASTORE_U8); -+ ADD_NDS32_BUILTIN2 ("put_unaligned_s8x4", void, ptr_char, -+ v4qi, UASTORE_S8); - } -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32_intrinsic.h gcc-8.2.0/gcc/config/nds32/nds32_intrinsic.h ---- gcc-8.2.0.orig/gcc/config/nds32/nds32_intrinsic.h 2018-04-22 09:46:39.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32_intrinsic.h 2019-01-25 15:38:32.833242671 +0100 -@@ -26,6 +26,13 @@ - #ifndef _NDS32_INTRINSIC_H - #define _NDS32_INTRINSIC_H - -+typedef signed char int8x4_t __attribute ((vector_size(4))); -+typedef short int16x2_t __attribute ((vector_size(4))); -+typedef int int32x2_t __attribute__((vector_size(8))); -+typedef unsigned char uint8x4_t __attribute__ ((vector_size (4))); -+typedef unsigned short uint16x2_t __attribute__ ((vector_size (4))); -+typedef unsigned int uint32x2_t __attribute__((vector_size(8))); -+ - /* General instrinsic register names. */ - enum nds32_intrinsic_registers - { -@@ -691,6 +698,55 @@ - #define __nds32__tlbop_flua() \ - (__builtin_nds32_tlbop_flua()) - -+#define __nds32__kaddw(a, b) \ -+ (__builtin_nds32_kaddw ((a), (b))) -+#define __nds32__kaddh(a, b) \ -+ (__builtin_nds32_kaddh ((a), (b))) -+#define __nds32__ksubw(a, b) \ -+ (__builtin_nds32_ksubw ((a), (b))) -+#define __nds32__ksubh(a, b) \ -+ (__builtin_nds32_ksubh ((a), (b))) -+#define __nds32__kdmbb(a, b) \ -+ (__builtin_nds32_kdmbb ((a), (b))) -+#define __nds32__v_kdmbb(a, b) \ -+ (__builtin_nds32_v_kdmbb ((a), (b))) -+#define __nds32__kdmbt(a, b) \ -+ (__builtin_nds32_kdmbt ((a), (b))) -+#define __nds32__v_kdmbt(a, b) \ -+ (__builtin_nds32_v_kdmbt ((a), (b))) -+#define __nds32__kdmtb(a, b) \ -+ (__builtin_nds32_kdmtb ((a), (b))) -+#define __nds32__v_kdmtb(a, b) \ -+ (__builtin_nds32_v_kdmtb ((a), (b))) -+#define __nds32__kdmtt(a, b) \ -+ (__builtin_nds32_kdmtt ((a), (b))) -+#define __nds32__v_kdmtt(a, b) \ -+ (__builtin_nds32_v_kdmtt ((a), (b))) -+#define __nds32__khmbb(a, b) \ -+ (__builtin_nds32_khmbb ((a), (b))) -+#define __nds32__v_khmbb(a, b) \ -+ (__builtin_nds32_v_khmbb ((a), (b))) -+#define __nds32__khmbt(a, b) \ -+ (__builtin_nds32_khmbt ((a), (b))) -+#define __nds32__v_khmbt(a, b) \ -+ (__builtin_nds32_v_khmbt ((a), (b))) -+#define __nds32__khmtb(a, b) \ -+ (__builtin_nds32_khmtb ((a), (b))) -+#define __nds32__v_khmtb(a, b) \ -+ (__builtin_nds32_v_khmtb ((a), (b))) -+#define __nds32__khmtt(a, b) \ -+ (__builtin_nds32_khmtt ((a), (b))) -+#define __nds32__v_khmtt(a, b) \ -+ (__builtin_nds32_v_khmtt ((a), (b))) -+#define __nds32__kslraw(a, b) \ -+ (__builtin_nds32_kslraw ((a), (b))) -+#define __nds32__kslraw_u(a, b) \ -+ (__builtin_nds32_kslraw_u ((a), (b))) -+ -+#define __nds32__rdov() \ -+ (__builtin_nds32_rdov()) -+#define __nds32__clrov() \ -+ (__builtin_nds32_clrov()) - #define __nds32__gie_dis() \ - (__builtin_nds32_gie_dis()) - #define __nds32__gie_en() \ -@@ -720,10 +776,622 @@ - #define __nds32__get_trig_type(a) \ - (__builtin_nds32_get_trig_type ((a))) - -+#define __nds32__get_unaligned_hw(a) \ -+ (__builtin_nds32_unaligned_load_hw ((a))) -+#define __nds32__get_unaligned_w(a) \ -+ (__builtin_nds32_unaligned_load_w ((a))) -+#define __nds32__get_unaligned_dw(a) \ -+ (__builtin_nds32_unaligned_load_dw ((a))) -+#define __nds32__put_unaligned_hw(a, data) \ -+ (__builtin_nds32_unaligned_store_hw ((a), (data))) -+#define __nds32__put_unaligned_w(a, data) \ -+ (__builtin_nds32_unaligned_store_w ((a), (data))) -+#define __nds32__put_unaligned_dw(a, data) \ -+ (__builtin_nds32_unaligned_store_dw ((a), (data))) -+ -+#define __nds32__add16(a, b) \ -+ (__builtin_nds32_add16 ((a), (b))) -+#define __nds32__v_uadd16(a, b) \ -+ (__builtin_nds32_v_uadd16 ((a), (b))) -+#define __nds32__v_sadd16(a, b) \ -+ (__builtin_nds32_v_sadd16 ((a), (b))) -+#define __nds32__radd16(a, b) \ -+ (__builtin_nds32_radd16 ((a), (b))) -+#define __nds32__v_radd16(a, b) \ -+ (__builtin_nds32_v_radd16 ((a), (b))) -+#define __nds32__uradd16(a, b) \ -+ (__builtin_nds32_uradd16 ((a), (b))) -+#define __nds32__v_uradd16(a, b) \ -+ (__builtin_nds32_v_uradd16 ((a), (b))) -+#define __nds32__kadd16(a, b) \ -+ (__builtin_nds32_kadd16 ((a), (b))) -+#define __nds32__v_kadd16(a, b) \ -+ (__builtin_nds32_v_kadd16 ((a), (b))) -+#define __nds32__ukadd16(a, b) \ -+ (__builtin_nds32_ukadd16 ((a), (b))) -+#define __nds32__v_ukadd16(a, b) \ -+ (__builtin_nds32_v_ukadd16 ((a), (b))) -+#define __nds32__sub16(a, b) \ -+ (__builtin_nds32_sub16 ((a), (b))) -+#define __nds32__v_usub16(a, b) \ -+ (__builtin_nds32_v_usub16 ((a), (b))) -+#define __nds32__v_ssub16(a, b) \ -+ (__builtin_nds32_v_ssub16 ((a), (b))) -+#define __nds32__rsub16(a, b) \ -+ (__builtin_nds32_rsub16 ((a), (b))) -+#define __nds32__v_rsub16(a, b) \ -+ (__builtin_nds32_v_rsub16 ((a), (b))) -+#define __nds32__ursub16(a, b) \ -+ (__builtin_nds32_ursub16 ((a), (b))) -+#define __nds32__v_ursub16(a, b) \ -+ (__builtin_nds32_v_ursub16 ((a), (b))) -+#define __nds32__ksub16(a, b) \ -+ (__builtin_nds32_ksub16 ((a), (b))) -+#define __nds32__v_ksub16(a, b) \ -+ (__builtin_nds32_v_ksub16 ((a), (b))) -+#define __nds32__uksub16(a, b) \ -+ (__builtin_nds32_uksub16 ((a), (b))) -+#define __nds32__v_uksub16(a, b) \ -+ (__builtin_nds32_v_uksub16 ((a), (b))) -+#define __nds32__cras16(a, b) \ -+ (__builtin_nds32_cras16 ((a), (b))) -+#define __nds32__v_ucras16(a, b) \ -+ (__builtin_nds32_v_ucras16 ((a), (b))) -+#define __nds32__v_scras16(a, b) \ -+ (__builtin_nds32_v_scras16 ((a), (b))) -+#define __nds32__rcras16(a, b) \ -+ (__builtin_nds32_rcras16 ((a), (b))) -+#define __nds32__v_rcras16(a, b) \ -+ (__builtin_nds32_v_rcras16 ((a), (b))) -+#define __nds32__urcras16(a, b) \ -+ (__builtin_nds32_urcras16 ((a), (b))) -+#define __nds32__v_urcras16(a, b) \ -+ (__builtin_nds32_v_urcras16 ((a), (b))) -+#define __nds32__kcras16(a, b) \ -+ (__builtin_nds32_kcras16 ((a), (b))) -+#define __nds32__v_kcras16(a, b) \ -+ (__builtin_nds32_v_kcras16 ((a), (b))) -+#define __nds32__ukcras16(a, b) \ -+ (__builtin_nds32_ukcras16 ((a), (b))) -+#define __nds32__v_ukcras16(a, b) \ -+ (__builtin_nds32_v_ukcras16 ((a), (b))) -+#define __nds32__crsa16(a, b) \ -+ (__builtin_nds32_crsa16 ((a), (b))) -+#define __nds32__v_ucrsa16(a, b) \ -+ (__builtin_nds32_v_ucrsa16 ((a), (b))) -+#define __nds32__v_scrsa16(a, b) \ -+ (__builtin_nds32_v_scrsa16 ((a), (b))) -+#define __nds32__rcrsa16(a, b) \ -+ (__builtin_nds32_rcrsa16 ((a), (b))) -+#define __nds32__v_rcrsa16(a, b) \ -+ (__builtin_nds32_v_rcrsa16 ((a), (b))) -+#define __nds32__urcrsa16(a, b) \ -+ (__builtin_nds32_urcrsa16 ((a), (b))) -+#define __nds32__v_urcrsa16(a, b) \ -+ (__builtin_nds32_v_urcrsa16 ((a), (b))) -+#define __nds32__kcrsa16(a, b) \ -+ (__builtin_nds32_kcrsa16 ((a), (b))) -+#define __nds32__v_kcrsa16(a, b) \ -+ (__builtin_nds32_v_kcrsa16 ((a), (b))) -+#define __nds32__ukcrsa16(a, b) \ -+ (__builtin_nds32_ukcrsa16 ((a), (b))) -+#define __nds32__v_ukcrsa16(a, b) \ -+ (__builtin_nds32_v_ukcrsa16 ((a), (b))) -+ -+#define __nds32__add8(a, b) \ -+ (__builtin_nds32_add8 ((a), (b))) -+#define __nds32__v_uadd8(a, b) \ -+ (__builtin_nds32_v_uadd8 ((a), (b))) -+#define __nds32__v_sadd8(a, b) \ -+ (__builtin_nds32_v_sadd8 ((a), (b))) -+#define __nds32__radd8(a, b) \ -+ (__builtin_nds32_radd8 ((a), (b))) -+#define __nds32__v_radd8(a, b) \ -+ (__builtin_nds32_v_radd8 ((a), (b))) -+#define __nds32__uradd8(a, b) \ -+ (__builtin_nds32_uradd8 ((a), (b))) -+#define __nds32__v_uradd8(a, b) \ -+ (__builtin_nds32_v_uradd8 ((a), (b))) -+#define __nds32__kadd8(a, b) \ -+ (__builtin_nds32_kadd8 ((a), (b))) -+#define __nds32__v_kadd8(a, b) \ -+ (__builtin_nds32_v_kadd8 ((a), (b))) -+#define __nds32__ukadd8(a, b) \ -+ (__builtin_nds32_ukadd8 ((a), (b))) -+#define __nds32__v_ukadd8(a, b) \ -+ (__builtin_nds32_v_ukadd8 ((a), (b))) -+#define __nds32__sub8(a, b) \ -+ (__builtin_nds32_sub8 ((a), (b))) -+#define __nds32__v_usub8(a, b) \ -+ (__builtin_nds32_v_usub8 ((a), (b))) -+#define __nds32__v_ssub8(a, b) \ -+ (__builtin_nds32_v_ssub8 ((a), (b))) -+#define __nds32__rsub8(a, b) \ -+ (__builtin_nds32_rsub8 ((a), (b))) -+#define __nds32__v_rsub8(a, b) \ -+ (__builtin_nds32_v_rsub8 ((a), (b))) -+#define __nds32__ursub8(a, b) \ -+ (__builtin_nds32_ursub8 ((a), (b))) -+#define __nds32__v_ursub8(a, b) \ -+ (__builtin_nds32_v_ursub8 ((a), (b))) -+#define __nds32__ksub8(a, b) \ -+ (__builtin_nds32_ksub8 ((a), (b))) -+#define __nds32__v_ksub8(a, b) \ -+ (__builtin_nds32_v_ksub8 ((a), (b))) -+#define __nds32__uksub8(a, b) \ -+ (__builtin_nds32_uksub8 ((a), (b))) -+#define __nds32__v_uksub8(a, b) \ -+ (__builtin_nds32_v_uksub8 ((a), (b))) -+ -+#define __nds32__sra16(a, b) \ -+ (__builtin_nds32_sra16 ((a), (b))) -+#define __nds32__v_sra16(a, b) \ -+ (__builtin_nds32_v_sra16 ((a), (b))) -+#define __nds32__sra16_u(a, b) \ -+ (__builtin_nds32_sra16_u ((a), (b))) -+#define __nds32__v_sra16_u(a, b) \ -+ (__builtin_nds32_v_sra16_u ((a), (b))) -+#define __nds32__srl16(a, b) \ -+ (__builtin_nds32_srl16 ((a), (b))) -+#define __nds32__v_srl16(a, b) \ -+ (__builtin_nds32_v_srl16 ((a), (b))) -+#define __nds32__srl16_u(a, b) \ -+ (__builtin_nds32_srl16_u ((a), (b))) -+#define __nds32__v_srl16_u(a, b) \ -+ (__builtin_nds32_v_srl16_u ((a), (b))) -+#define __nds32__sll16(a, b) \ -+ (__builtin_nds32_sll16 ((a), (b))) -+#define __nds32__v_sll16(a, b) \ -+ (__builtin_nds32_v_sll16 ((a), (b))) -+#define __nds32__ksll16(a, b) \ -+ (__builtin_nds32_ksll16 ((a), (b))) -+#define __nds32__v_ksll16(a, b) \ -+ (__builtin_nds32_v_ksll16 ((a), (b))) -+#define __nds32__kslra16(a, b) \ -+ (__builtin_nds32_kslra16 ((a), (b))) -+#define __nds32__v_kslra16(a, b) \ -+ (__builtin_nds32_v_kslra16 ((a), (b))) -+#define __nds32__kslra16_u(a, b) \ -+ (__builtin_nds32_kslra16_u ((a), (b))) -+#define __nds32__v_kslra16_u(a, b) \ -+ (__builtin_nds32_v_kslra16_u ((a), (b))) -+ -+#define __nds32__cmpeq16(a, b) \ -+ (__builtin_nds32_cmpeq16 ((a), (b))) -+#define __nds32__v_scmpeq16(a, b) \ -+ (__builtin_nds32_v_scmpeq16 ((a), (b))) -+#define __nds32__v_ucmpeq16(a, b) \ -+ (__builtin_nds32_v_ucmpeq16 ((a), (b))) -+#define __nds32__scmplt16(a, b) \ -+ (__builtin_nds32_scmplt16 ((a), (b))) -+#define __nds32__v_scmplt16(a, b) \ -+ (__builtin_nds32_v_scmplt16 ((a), (b))) -+#define __nds32__scmple16(a, b) \ -+ (__builtin_nds32_scmple16 ((a), (b))) -+#define __nds32__v_scmple16(a, b) \ -+ (__builtin_nds32_v_scmple16 ((a), (b))) -+#define __nds32__ucmplt16(a, b) \ -+ (__builtin_nds32_ucmplt16 ((a), (b))) -+#define __nds32__v_ucmplt16(a, b) \ -+ (__builtin_nds32_v_ucmplt16 ((a), (b))) -+#define __nds32__ucmple16(a, b) \ -+ (__builtin_nds32_ucmple16 ((a), (b))) -+#define __nds32__v_ucmple16(a, b) \ -+ (__builtin_nds32_v_ucmple16 ((a), (b))) -+ -+#define __nds32__cmpeq8(a, b) \ -+ (__builtin_nds32_cmpeq8 ((a), (b))) -+#define __nds32__v_scmpeq8(a, b) \ -+ (__builtin_nds32_v_scmpeq8 ((a), (b))) -+#define __nds32__v_ucmpeq8(a, b) \ -+ (__builtin_nds32_v_ucmpeq8 ((a), (b))) -+#define __nds32__scmplt8(a, b) \ -+ (__builtin_nds32_scmplt8 ((a), (b))) -+#define __nds32__v_scmplt8(a, b) \ -+ (__builtin_nds32_v_scmplt8 ((a), (b))) -+#define __nds32__scmple8(a, b) \ -+ (__builtin_nds32_scmple8 ((a), (b))) -+#define __nds32__v_scmple8(a, b) \ -+ (__builtin_nds32_v_scmple8 ((a), (b))) -+#define __nds32__ucmplt8(a, b) \ -+ (__builtin_nds32_ucmplt8 ((a), (b))) -+#define __nds32__v_ucmplt8(a, b) \ -+ (__builtin_nds32_v_ucmplt8 ((a), (b))) -+#define __nds32__ucmple8(a, b) \ -+ (__builtin_nds32_ucmple8 ((a), (b))) -+#define __nds32__v_ucmple8(a, b) \ -+ (__builtin_nds32_v_ucmple8 ((a), (b))) -+ -+#define __nds32__smin16(a, b) \ -+ (__builtin_nds32_smin16 ((a), (b))) -+#define __nds32__v_smin16(a, b) \ -+ (__builtin_nds32_v_smin16 ((a), (b))) -+#define __nds32__umin16(a, b) \ -+ (__builtin_nds32_umin16 ((a), (b))) -+#define __nds32__v_umin16(a, b) \ -+ (__builtin_nds32_v_umin16 ((a), (b))) -+#define __nds32__smax16(a, b) \ -+ (__builtin_nds32_smax16 ((a), (b))) -+#define __nds32__v_smax16(a, b) \ -+ (__builtin_nds32_v_smax16 ((a), (b))) -+#define __nds32__umax16(a, b) \ -+ (__builtin_nds32_umax16 ((a), (b))) -+#define __nds32__v_umax16(a, b) \ -+ (__builtin_nds32_v_umax16 ((a), (b))) -+#define __nds32__sclip16(a, b) \ -+ (__builtin_nds32_sclip16 ((a), (b))) -+#define __nds32__v_sclip16(a, b) \ -+ (__builtin_nds32_v_sclip16 ((a), (b))) -+#define __nds32__uclip16(a, b) \ -+ (__builtin_nds32_uclip16 ((a), (b))) -+#define __nds32__v_uclip16(a, b) \ -+ (__builtin_nds32_v_uclip16 ((a), (b))) -+#define __nds32__khm16(a, b) \ -+ (__builtin_nds32_khm16 ((a), (b))) -+#define __nds32__v_khm16(a, b) \ -+ (__builtin_nds32_v_khm16 ((a), (b))) -+#define __nds32__khmx16(a, b) \ -+ (__builtin_nds32_khmx16 ((a), (b))) -+#define __nds32__v_khmx16(a, b) \ -+ (__builtin_nds32_v_khmx16 ((a), (b))) -+#define __nds32__kabs16(a) \ -+ (__builtin_nds32_kabs16 ((a))) -+#define __nds32__v_kabs16(a) \ -+ (__builtin_nds32_v_kabs16 ((a))) -+ -+#define __nds32__smin8(a, b) \ -+ (__builtin_nds32_smin8 ((a), (b))) -+#define __nds32__v_smin8(a, b) \ -+ (__builtin_nds32_v_smin8 ((a), (b))) -+#define __nds32__umin8(a, b) \ -+ (__builtin_nds32_umin8 ((a), (b))) -+#define __nds32__v_umin8(a, b) \ -+ (__builtin_nds32_v_umin8 ((a), (b))) -+#define __nds32__smax8(a, b) \ -+ (__builtin_nds32_smax8 ((a), (b))) -+#define __nds32__v_smax8(a, b) \ -+ (__builtin_nds32_v_smax8 ((a), (b))) -+#define __nds32__umax8(a, b) \ -+ (__builtin_nds32_umax8 ((a), (b))) -+#define __nds32__v_umax8(a, b) \ -+ (__builtin_nds32_v_umax8 ((a), (b))) -+#define __nds32__kabs8(a) \ -+ (__builtin_nds32_kabs8 ((a))) -+#define __nds32__v_kabs8(a) \ -+ (__builtin_nds32_v_kabs8 ((a))) -+ -+#define __nds32__sunpkd810(a) \ -+ (__builtin_nds32_sunpkd810 ((a))) -+#define __nds32__v_sunpkd810(a) \ -+ (__builtin_nds32_v_sunpkd810 ((a))) -+#define __nds32__sunpkd820(a) \ -+ (__builtin_nds32_sunpkd820 ((a))) -+#define __nds32__v_sunpkd820(a) \ -+ (__builtin_nds32_v_sunpkd820 ((a))) -+#define __nds32__sunpkd830(a) \ -+ (__builtin_nds32_sunpkd830 ((a))) -+#define __nds32__v_sunpkd830(a) \ -+ (__builtin_nds32_v_sunpkd830 ((a))) -+#define __nds32__sunpkd831(a) \ -+ (__builtin_nds32_sunpkd831 ((a))) -+#define __nds32__v_sunpkd831(a) \ -+ (__builtin_nds32_v_sunpkd831 ((a))) -+#define __nds32__zunpkd810(a) \ -+ (__builtin_nds32_zunpkd810 ((a))) -+#define __nds32__v_zunpkd810(a) \ -+ (__builtin_nds32_v_zunpkd810 ((a))) -+#define __nds32__zunpkd820(a) \ -+ (__builtin_nds32_zunpkd820 ((a))) -+#define __nds32__v_zunpkd820(a) \ -+ (__builtin_nds32_v_zunpkd820 ((a))) -+#define __nds32__zunpkd830(a) \ -+ (__builtin_nds32_zunpkd830 ((a))) -+#define __nds32__v_zunpkd830(a) \ -+ (__builtin_nds32_v_zunpkd830 ((a))) -+#define __nds32__zunpkd831(a) \ -+ (__builtin_nds32_zunpkd831 ((a))) -+#define __nds32__v_zunpkd831(a) \ -+ (__builtin_nds32_v_zunpkd831 ((a))) -+ -+#define __nds32__raddw(a, b) \ -+ (__builtin_nds32_raddw ((a), (b))) -+#define __nds32__uraddw(a, b) \ -+ (__builtin_nds32_uraddw ((a), (b))) -+#define __nds32__rsubw(a, b) \ -+ (__builtin_nds32_rsubw ((a), (b))) -+#define __nds32__ursubw(a, b) \ -+ (__builtin_nds32_ursubw ((a), (b))) -+ -+#define __nds32__sra_u(a, b) \ -+ (__builtin_nds32_sra_u ((a), (b))) -+#define __nds32__ksll(a, b) \ -+ (__builtin_nds32_ksll ((a), (b))) -+#define __nds32__pkbb16(a, b) \ -+ (__builtin_nds32_pkbb16 ((a), (b))) -+#define __nds32__v_pkbb16(a, b) \ -+ (__builtin_nds32_v_pkbb16 ((a), (b))) -+#define __nds32__pkbt16(a, b) \ -+ (__builtin_nds32_pkbt16 ((a), (b))) -+#define __nds32__v_pkbt16(a, b) \ -+ (__builtin_nds32_v_pkbt16 ((a), (b))) -+#define __nds32__pktb16(a, b) \ -+ (__builtin_nds32_pktb16 ((a), (b))) -+#define __nds32__v_pktb16(a, b) \ -+ (__builtin_nds32_v_pktb16 ((a), (b))) -+#define __nds32__pktt16(a, b) \ -+ (__builtin_nds32_pktt16 ((a), (b))) -+#define __nds32__v_pktt16(a, b) \ -+ (__builtin_nds32_v_pktt16 ((a), (b))) -+ -+#define __nds32__smmul(a, b) \ -+ (__builtin_nds32_smmul ((a), (b))) -+#define __nds32__smmul_u(a, b) \ -+ (__builtin_nds32_smmul_u ((a), (b))) -+#define __nds32__kmmac(r, a, b) \ -+ (__builtin_nds32_kmmac ((r), (a), (b))) -+#define __nds32__kmmac_u(r, a, b) \ -+ (__builtin_nds32_kmmac_u ((r), (a), (b))) -+#define __nds32__kmmsb(r, a, b) \ -+ (__builtin_nds32_kmmsb ((r), (a), (b))) -+#define __nds32__kmmsb_u(r, a, b) \ -+ (__builtin_nds32_kmmsb_u ((r), (a), (b))) -+#define __nds32__kwmmul(a, b) \ -+ (__builtin_nds32_kwmmul ((a), (b))) -+#define __nds32__kwmmul_u(a, b) \ -+ (__builtin_nds32_kwmmul_u ((a), (b))) -+ -+#define __nds32__smmwb(a, b) \ -+ (__builtin_nds32_smmwb ((a), (b))) -+#define __nds32__v_smmwb(a, b) \ -+ (__builtin_nds32_v_smmwb ((a), (b))) -+#define __nds32__smmwb_u(a, b) \ -+ (__builtin_nds32_smmwb_u ((a), (b))) -+#define __nds32__v_smmwb_u(a, b) \ -+ (__builtin_nds32_v_smmwb_u ((a), (b))) -+#define __nds32__smmwt(a, b) \ -+ (__builtin_nds32_smmwt ((a), (b))) -+#define __nds32__v_smmwt(a, b) \ -+ (__builtin_nds32_v_smmwt ((a), (b))) -+#define __nds32__smmwt_u(a, b) \ -+ (__builtin_nds32_smmwt_u ((a), (b))) -+#define __nds32__v_smmwt_u(a, b) \ -+ (__builtin_nds32_v_smmwt_u ((a), (b))) -+#define __nds32__kmmawb(r, a, b) \ -+ (__builtin_nds32_kmmawb ((r), (a), (b))) -+#define __nds32__v_kmmawb(r, a, b) \ -+ (__builtin_nds32_v_kmmawb ((r), (a), (b))) -+#define __nds32__kmmawb_u(r, a, b) \ -+ (__builtin_nds32_kmmawb_u ((r), (a), (b))) -+#define __nds32__v_kmmawb_u(r, a, b) \ -+ (__builtin_nds32_v_kmmawb_u ((r), (a), (b))) -+#define __nds32__kmmawt(r, a, b) \ -+ (__builtin_nds32_kmmawt ((r), (a), (b))) -+#define __nds32__v_kmmawt(r, a, b) \ -+ (__builtin_nds32_v_kmmawt ((r), (a), (b))) -+#define __nds32__kmmawt_u(r, a, b) \ -+ (__builtin_nds32_kmmawt_u ((r), (a), (b))) -+#define __nds32__v_kmmawt_u(r, a, b) \ -+ (__builtin_nds32_v_kmmawt_u ((r), (a), (b))) -+ -+#define __nds32__smbb(a, b) \ -+ (__builtin_nds32_smbb ((a), (b))) -+#define __nds32__v_smbb(a, b) \ -+ (__builtin_nds32_v_smbb ((a), (b))) -+#define __nds32__smbt(a, b) \ -+ (__builtin_nds32_smbt ((a), (b))) -+#define __nds32__v_smbt(a, b) \ -+ (__builtin_nds32_v_smbt ((a), (b))) -+#define __nds32__smtt(a, b) \ -+ (__builtin_nds32_smtt ((a), (b))) -+#define __nds32__v_smtt(a, b) \ -+ (__builtin_nds32_v_smtt ((a), (b))) -+#define __nds32__kmda(a, b) \ -+ (__builtin_nds32_kmda ((a), (b))) -+#define __nds32__v_kmda(a, b) \ -+ (__builtin_nds32_v_kmda ((a), (b))) -+#define __nds32__kmxda(a, b) \ -+ (__builtin_nds32_kmxda ((a), (b))) -+#define __nds32__v_kmxda(a, b) \ -+ (__builtin_nds32_v_kmxda ((a), (b))) -+#define __nds32__smds(a, b) \ -+ (__builtin_nds32_smds ((a), (b))) -+#define __nds32__v_smds(a, b) \ -+ (__builtin_nds32_v_smds ((a), (b))) -+#define __nds32__smdrs(a, b) \ -+ (__builtin_nds32_smdrs ((a), (b))) -+#define __nds32__v_smdrs(a, b) \ -+ (__builtin_nds32_v_smdrs ((a), (b))) -+#define __nds32__smxds(a, b) \ -+ (__builtin_nds32_smxds ((a), (b))) -+#define __nds32__v_smxds(a, b) \ -+ (__builtin_nds32_v_smxds ((a), (b))) -+#define __nds32__kmabb(r, a, b) \ -+ (__builtin_nds32_kmabb ((r), (a), (b))) -+#define __nds32__v_kmabb(r, a, b) \ -+ (__builtin_nds32_v_kmabb ((r), (a), (b))) -+#define __nds32__kmabt(r, a, b) \ -+ (__builtin_nds32_kmabt ((r), (a), (b))) -+#define __nds32__v_kmabt(r, a, b) \ -+ (__builtin_nds32_v_kmabt ((r), (a), (b))) -+#define __nds32__kmatt(r, a, b) \ -+ (__builtin_nds32_kmatt ((r), (a), (b))) -+#define __nds32__v_kmatt(r, a, b) \ -+ (__builtin_nds32_v_kmatt ((r), (a), (b))) -+#define __nds32__kmada(r, a, b) \ -+ (__builtin_nds32_kmada ((r), (a), (b))) -+#define __nds32__v_kmada(r, a, b) \ -+ (__builtin_nds32_v_kmada ((r), (a), (b))) -+#define __nds32__kmaxda(r, a, b) \ -+ (__builtin_nds32_kmaxda ((r), (a), (b))) -+#define __nds32__v_kmaxda(r, a, b) \ -+ (__builtin_nds32_v_kmaxda ((r), (a), (b))) -+#define __nds32__kmads(r, a, b) \ -+ (__builtin_nds32_kmads ((r), (a), (b))) -+#define __nds32__v_kmads(r, a, b) \ -+ (__builtin_nds32_v_kmads ((r), (a), (b))) -+#define __nds32__kmadrs(r, a, b) \ -+ (__builtin_nds32_kmadrs ((r), (a), (b))) -+#define __nds32__v_kmadrs(r, a, b) \ -+ (__builtin_nds32_v_kmadrs ((r), (a), (b))) -+#define __nds32__kmaxds(r, a, b) \ -+ (__builtin_nds32_kmaxds ((r), (a), (b))) -+#define __nds32__v_kmaxds(r, a, b) \ -+ (__builtin_nds32_v_kmaxds ((r), (a), (b))) -+#define __nds32__kmsda(r, a, b) \ -+ (__builtin_nds32_kmsda ((r), (a), (b))) -+#define __nds32__v_kmsda(r, a, b) \ -+ (__builtin_nds32_v_kmsda ((r), (a), (b))) -+#define __nds32__kmsxda(r, a, b) \ -+ (__builtin_nds32_kmsxda ((r), (a), (b))) -+#define __nds32__v_kmsxda(r, a, b) \ -+ (__builtin_nds32_v_kmsxda ((r), (a), (b))) -+ -+#define __nds32__smal(a, b) \ -+ (__builtin_nds32_smal ((a), (b))) -+#define __nds32__v_smal(a, b) \ -+ (__builtin_nds32_v_smal ((a), (b))) -+ -+#define __nds32__bitrev(a, b) \ -+ (__builtin_nds32_bitrev ((a), (b))) -+#define __nds32__wext(a, b) \ -+ (__builtin_nds32_wext ((a), (b))) -+#define __nds32__bpick(r, a, b) \ -+ (__builtin_nds32_bpick ((r), (a), (b))) -+#define __nds32__insb(r, a, b) \ -+ (__builtin_nds32_insb ((r), (a), (b))) -+ -+#define __nds32__sadd64(a, b) \ -+ (__builtin_nds32_sadd64 ((a), (b))) -+#define __nds32__uadd64(a, b) \ -+ (__builtin_nds32_uadd64 ((a), (b))) -+#define __nds32__radd64(a, b) \ -+ (__builtin_nds32_radd64 ((a), (b))) -+#define __nds32__uradd64(a, b) \ -+ (__builtin_nds32_uradd64 ((a), (b))) -+#define __nds32__kadd64(a, b) \ -+ (__builtin_nds32_kadd64 ((a), (b))) -+#define __nds32__ukadd64(a, b) \ -+ (__builtin_nds32_ukadd64 ((a), (b))) -+#define __nds32__ssub64(a, b) \ -+ (__builtin_nds32_ssub64 ((a), (b))) -+#define __nds32__usub64(a, b) \ -+ (__builtin_nds32_usub64 ((a), (b))) -+#define __nds32__rsub64(a, b) \ -+ (__builtin_nds32_rsub64 ((a), (b))) -+#define __nds32__ursub64(a, b) \ -+ (__builtin_nds32_ursub64 ((a), (b))) -+#define __nds32__ksub64(a, b) \ -+ (__builtin_nds32_ksub64 ((a), (b))) -+#define __nds32__uksub64(a, b) \ -+ (__builtin_nds32_uksub64 ((a), (b))) -+ -+#define __nds32__smar64(r, a, b) \ -+ (__builtin_nds32_smar64 ((r), (a), (b))) -+#define __nds32__smsr64(r, a, b) \ -+ (__builtin_nds32_smsr64 ((r), (a), (b))) -+#define __nds32__umar64(r, a, b) \ -+ (__builtin_nds32_umar64 ((r), (a), (b))) -+#define __nds32__umsr64(r, a, b) \ -+ (__builtin_nds32_umsr64 ((r), (a), (b))) -+#define __nds32__kmar64(r, a, b) \ -+ (__builtin_nds32_kmar64 ((r), (a), (b))) -+#define __nds32__kmsr64(r, a, b) \ -+ (__builtin_nds32_kmsr64 ((r), (a), (b))) -+#define __nds32__ukmar64(r, a, b) \ -+ (__builtin_nds32_ukmar64 ((r), (a), (b))) -+#define __nds32__ukmsr64(r, a, b) \ -+ (__builtin_nds32_ukmsr64 ((r), (a), (b))) -+ -+#define __nds32__smalbb(r, a, b) \ -+ (__builtin_nds32_smalbb ((r), (a), (b))) -+#define __nds32__v_smalbb(r, a, b) \ -+ (__builtin_nds32_v_smalbb ((r), (a), (b))) -+#define __nds32__smalbt(r, a, b) \ -+ (__builtin_nds32_smalbt ((r), (a), (b))) -+#define __nds32__v_smalbt(r, a, b) \ -+ (__builtin_nds32_v_smalbt ((r), (a), (b))) -+#define __nds32__smaltt(r, a, b) \ -+ (__builtin_nds32_smaltt ((r), (a), (b))) -+#define __nds32__v_smaltt(r, a, b) \ -+ (__builtin_nds32_v_smaltt ((r), (a), (b))) -+#define __nds32__smalda(r, a, b) \ -+ (__builtin_nds32_smalda ((r), (a), (b))) -+#define __nds32__v_smalda(r, a, b) \ -+ (__builtin_nds32_v_smalda ((r), (a), (b))) -+#define __nds32__smalxda(r, a, b) \ -+ (__builtin_nds32_smalxda ((r), (a), (b))) -+#define __nds32__v_smalxda(r, a, b) \ -+ (__builtin_nds32_v_smalxda ((r), (a), (b))) -+#define __nds32__smalds(r, a, b) \ -+ (__builtin_nds32_smalds ((r), (a), (b))) -+#define __nds32__v_smalds(r, a, b) \ -+ (__builtin_nds32_v_smalds ((r), (a), (b))) -+#define __nds32__smaldrs(r, a, b) \ -+ (__builtin_nds32_smaldrs ((r), (a), (b))) -+#define __nds32__v_smaldrs(r, a, b) \ -+ (__builtin_nds32_v_smaldrs ((r), (a), (b))) -+#define __nds32__smalxds(r, a, b) \ -+ (__builtin_nds32_smalxds ((r), (a), (b))) -+#define __nds32__v_smalxds(r, a, b) \ -+ (__builtin_nds32_v_smalxds ((r), (a), (b))) -+#define __nds32__smslda(r, a, b) \ -+ (__builtin_nds32_smslda ((r), (a), (b))) -+#define __nds32__v_smslda(r, a, b) \ -+ (__builtin_nds32_v_smslda ((r), (a), (b))) -+#define __nds32__smslxda(r, a, b) \ -+ (__builtin_nds32_smslxda ((r), (a), (b))) -+#define __nds32__v_smslxda(r, a, b) \ -+ (__builtin_nds32_v_smslxda ((r), (a), (b))) -+ -+#define __nds32__smul16(a, b) \ -+ (__builtin_nds32_smul16 ((a), (b))) -+#define __nds32__v_smul16(a, b) \ -+ (__builtin_nds32_v_smul16 ((a), (b))) -+#define __nds32__smulx16(a, b) \ -+ (__builtin_nds32_smulx16 ((a), (b))) -+#define __nds32__v_smulx16(a, b) \ -+ (__builtin_nds32_v_smulx16 ((a), (b))) -+#define __nds32__umul16(a, b) \ -+ (__builtin_nds32_umul16 ((a), (b))) -+#define __nds32__v_umul16(a, b) \ -+ (__builtin_nds32_v_umul16 ((a), (b))) -+#define __nds32__umulx16(a, b) \ -+ (__builtin_nds32_umulx16 ((a), (b))) -+#define __nds32__v_umulx16(a, b) \ -+ (__builtin_nds32_v_umulx16 ((a), (b))) -+ -+#define __nds32__uclip32(a, imm) \ -+ (__builtin_nds32_uclip32 ((a), (imm))) -+#define __nds32__sclip32(a, imm) \ -+ (__builtin_nds32_sclip32 ((a), (imm))) -+#define __nds32__kabs(a) \ -+ (__builtin_nds32_kabs ((a))) -+ - #define __nds32__unaligned_feature() \ - (__builtin_nds32_unaligned_feature()) - #define __nds32__enable_unaligned() \ - (__builtin_nds32_enable_unaligned()) - #define __nds32__disable_unaligned() \ - (__builtin_nds32_disable_unaligned()) -+ -+#define __nds32__get_unaligned_u16x2(a) \ -+ (__builtin_nds32_get_unaligned_u16x2 ((a))) -+#define __nds32__get_unaligned_s16x2(a) \ -+ (__builtin_nds32_get_unaligned_s16x2 ((a))) -+#define __nds32__get_unaligned_u8x4(a) \ -+ (__builtin_nds32_get_unaligned_u8x4 ((a))) -+#define __nds32__get_unaligned_s8x4(a) \ -+ (__builtin_nds32_get_unaligned_s8x4 ((a))) -+ -+#define __nds32__put_unaligned_u16x2(a, data) \ -+ (__builtin_nds32_put_unaligned_u16x2 ((a), (data))) -+#define __nds32__put_unaligned_s16x2(a, data) \ -+ (__builtin_nds32_put_unaligned_s16x2 ((a), (data))) -+#define __nds32__put_unaligned_u8x4(a, data) \ -+ (__builtin_nds32_put_unaligned_u8x4 ((a), (data))) -+#define __nds32__put_unaligned_s8x4(a, data) \ -+ (__builtin_nds32_put_unaligned_s8x4 ((a), (data))) -+ -+#define NDS32ATTR_SIGNATURE __attribute__((signature)) -+ - #endif /* nds32_intrinsic.h */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.md gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.md 2018-04-22 09:46:39.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.md 2019-01-25 15:38:32.825242648 +0100 -@@ -1037,6 +1037,187 @@ - (set_attr "length" "4")] - ) - -+;; SATURATION -+ -+(define_insn "unspec_kaddw" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_plus:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")))] -+ "" -+ "kaddw\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_ksubw" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ss_minus:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")))] -+ "" -+ "ksubw\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kaddh" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KADDH))] -+ "" -+ "kaddh\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_ksubh" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSUBH))] -+ "" -+ "ksubh\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kaddh_dsp" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")) -+ (const_int 15)] UNSPEC_CLIPS))] -+ "NDS32_EXT_DSP_P ()" -+ "kaddh\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_ksubh_dsp" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(minus:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")) -+ (const_int 15)] UNSPEC_CLIPS))] -+ "NDS32_EXT_DSP_P ()" -+ "ksubh\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kdmbb" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMBB))] -+ "" -+ "kdmbb\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kdmbt" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMBT))] -+ "" -+ "kdmbt\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kdmtb" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMTB))] -+ "" -+ "kdmtb\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kdmtt" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMTT))] -+ "" -+ "kdmtt\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_khmbb" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMBB))] -+ "" -+ "khmbb\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_khmbt" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMBT))] -+ "" -+ "khmbt\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_khmtb" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMTB))] -+ "" -+ "khmtb\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_khmtt" -+ [(set (match_operand:V2HI 0 "register_operand" "=r") -+ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") -+ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMTT))] -+ "" -+ "khmtt\t%0, %1, %2" -+ [(set_attr "type" "mul") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kslraw" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAW))] -+ "" -+ "kslraw\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_kslrawu" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAWU))] -+ "" -+ "kslraw.u\t%0, %1, %2" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_volatile_rdov" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_RDOV))] -+ "" -+ "rdov\t%0" -+ [(set_attr "type" "misc") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "unspec_volatile_clrov" -+ [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CLROV)] -+ "" -+ "clrov" -+ [(set_attr "type" "misc") -+ (set_attr "length" "4")] -+) -+ - ;; System - - (define_insn "unspec_sva" -@@ -1415,22 +1596,17 @@ - if (TARGET_ISA_V3M) - nds32_expand_unaligned_store (operands, DImode); - else -- emit_insn (gen_unaligned_store_dw (operands[0], operands[1])); -+ emit_insn (gen_unaligned_store_dw (gen_rtx_MEM (DImode, operands[0]), -+ operands[1])); - DONE; - }) - - (define_insn "unaligned_store_dw" -- [(set (mem:DI (match_operand:SI 0 "register_operand" "r")) -- (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))] -+ [(set (match_operand:DI 0 "nds32_lmw_smw_base_operand" "=Umw") -+ (unspec:DI [(match_operand:DI 1 "register_operand" " r")] UNSPEC_UASTORE_DW))] - "" - { -- rtx otherops[3]; -- otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1])); -- otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); -- otherops[2] = operands[0]; -- -- output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops); -- return ""; -+ return nds32_output_smw_double_word (operands); - } - [(set_attr "type" "store") - (set_attr "length" "4")] -@@ -1495,4 +1671,15 @@ - DONE; - }) - -+;; abs alias kabs -+ -+(define_insn "unspec_kabs" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_KABS))] -+ "" -+ "kabs\t%0, %1" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ - ;; ------------------------------------------------------------------------ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-isr.c gcc-8.2.0/gcc/config/nds32/nds32-isr.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-isr.c 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-isr.c 2019-01-25 15:38:32.829242659 +0100 -@@ -43,7 +43,260 @@ - We use an array to record essential information for each vector. */ - static struct nds32_isr_info nds32_isr_vectors[NDS32_N_ISR_VECTORS]; - --/* ------------------------------------------------------------------------ */ -+/* ------------------------------------------------------------- */ -+/* FIXME: -+ FOR BACKWARD COMPATIBILITY, we need to support following patterns: -+ -+ __attribute__((interrupt("XXX;YYY;id=ZZZ"))) -+ __attribute__((exception("XXX;YYY;id=ZZZ"))) -+ __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) -+ -+ We provide several functions to parse the strings. */ -+ -+static void -+nds32_interrupt_attribute_parse_string (const char *original_str, -+ const char *func_name, -+ unsigned int s_level) -+{ -+ char target_str[100]; -+ enum nds32_isr_save_reg save_reg; -+ enum nds32_isr_nested_type nested_type; -+ -+ char *save_all_regs_str, *save_caller_regs_str; -+ char *nested_str, *not_nested_str, *ready_nested_str, *critical_str; -+ char *id_str, *value_str; -+ -+ /* Copy original string into a character array so that -+ the string APIs can handle it. */ -+ strcpy (target_str, original_str); -+ -+ /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL -+ 'save_caller_regs' : NDS32_PARTIAL_SAVE */ -+ save_all_regs_str = strstr (target_str, "save_all_regs"); -+ save_caller_regs_str = strstr (target_str, "save_caller_regs"); -+ -+ /* Note that if no argument is found, -+ use NDS32_PARTIAL_SAVE by default. */ -+ if (save_all_regs_str) -+ save_reg = NDS32_SAVE_ALL; -+ else if (save_caller_regs_str) -+ save_reg = NDS32_PARTIAL_SAVE; -+ else -+ save_reg = NDS32_PARTIAL_SAVE; -+ -+ /* 2. Detect 'nested' : NDS32_NESTED -+ 'not_nested' : NDS32_NOT_NESTED -+ 'ready_nested' : NDS32_NESTED_READY -+ 'critical' : NDS32_CRITICAL */ -+ nested_str = strstr (target_str, "nested"); -+ not_nested_str = strstr (target_str, "not_nested"); -+ ready_nested_str = strstr (target_str, "ready_nested"); -+ critical_str = strstr (target_str, "critical"); -+ -+ /* Note that if no argument is found, -+ use NDS32_NOT_NESTED by default. -+ Also, since 'not_nested' and 'ready_nested' both contains -+ 'nested' string, we check 'nested' with lowest priority. */ -+ if (not_nested_str) -+ nested_type = NDS32_NOT_NESTED; -+ else if (ready_nested_str) -+ nested_type = NDS32_NESTED_READY; -+ else if (nested_str) -+ nested_type = NDS32_NESTED; -+ else if (critical_str) -+ nested_type = NDS32_CRITICAL; -+ else -+ nested_type = NDS32_NOT_NESTED; -+ -+ /* 3. Traverse each id value and set corresponding information. */ -+ id_str = strstr (target_str, "id="); -+ -+ /* If user forgets to assign 'id', issue an error message. */ -+ if (id_str == NULL) -+ error ("require id argument in the string"); -+ /* Extract the value_str first. */ -+ id_str = strtok (id_str, "="); -+ value_str = strtok (NULL, ";"); -+ -+ /* Pick up the first id value token. */ -+ value_str = strtok (value_str, ","); -+ while (value_str != NULL) -+ { -+ int i; -+ i = atoi (value_str); -+ -+ /* For interrupt(0..63), the actual vector number is (9..72). */ -+ i = i + 9; -+ if (i < 9 || i > 72) -+ error ("invalid id value for interrupt attribute"); -+ -+ /* Setup nds32_isr_vectors[] array. */ -+ nds32_isr_vectors[i].category = NDS32_ISR_INTERRUPT; -+ strcpy (nds32_isr_vectors[i].func_name, func_name); -+ nds32_isr_vectors[i].save_reg = save_reg; -+ nds32_isr_vectors[i].nested_type = nested_type; -+ nds32_isr_vectors[i].security_level = s_level; -+ -+ /* Fetch next token. */ -+ value_str = strtok (NULL, ","); -+ } -+ -+ return; -+} -+ -+static void -+nds32_exception_attribute_parse_string (const char *original_str, -+ const char *func_name, -+ unsigned int s_level) -+{ -+ char target_str[100]; -+ enum nds32_isr_save_reg save_reg; -+ enum nds32_isr_nested_type nested_type; -+ -+ char *save_all_regs_str, *save_caller_regs_str; -+ char *nested_str, *not_nested_str, *ready_nested_str, *critical_str; -+ char *id_str, *value_str; -+ -+ /* Copy original string into a character array so that -+ the string APIs can handle it. */ -+ strcpy (target_str, original_str); -+ -+ /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL -+ 'save_caller_regs' : NDS32_PARTIAL_SAVE */ -+ save_all_regs_str = strstr (target_str, "save_all_regs"); -+ save_caller_regs_str = strstr (target_str, "save_caller_regs"); -+ -+ /* Note that if no argument is found, -+ use NDS32_PARTIAL_SAVE by default. */ -+ if (save_all_regs_str) -+ save_reg = NDS32_SAVE_ALL; -+ else if (save_caller_regs_str) -+ save_reg = NDS32_PARTIAL_SAVE; -+ else -+ save_reg = NDS32_PARTIAL_SAVE; -+ -+ /* 2. Detect 'nested' : NDS32_NESTED -+ 'not_nested' : NDS32_NOT_NESTED -+ 'ready_nested' : NDS32_NESTED_READY -+ 'critical' : NDS32_CRITICAL */ -+ nested_str = strstr (target_str, "nested"); -+ not_nested_str = strstr (target_str, "not_nested"); -+ ready_nested_str = strstr (target_str, "ready_nested"); -+ critical_str = strstr (target_str, "critical"); -+ -+ /* Note that if no argument is found, -+ use NDS32_NOT_NESTED by default. -+ Also, since 'not_nested' and 'ready_nested' both contains -+ 'nested' string, we check 'nested' with lowest priority. */ -+ if (not_nested_str) -+ nested_type = NDS32_NOT_NESTED; -+ else if (ready_nested_str) -+ nested_type = NDS32_NESTED_READY; -+ else if (nested_str) -+ nested_type = NDS32_NESTED; -+ else if (critical_str) -+ nested_type = NDS32_CRITICAL; -+ else -+ nested_type = NDS32_NOT_NESTED; -+ -+ /* 3. Traverse each id value and set corresponding information. */ -+ id_str = strstr (target_str, "id="); -+ -+ /* If user forgets to assign 'id', issue an error message. */ -+ if (id_str == NULL) -+ error ("require id argument in the string"); -+ /* Extract the value_str first. */ -+ id_str = strtok (id_str, "="); -+ value_str = strtok (NULL, ";"); -+ -+ /* Pick up the first id value token. */ -+ value_str = strtok (value_str, ","); -+ while (value_str != NULL) -+ { -+ int i; -+ i = atoi (value_str); -+ -+ /* For exception(1..8), the actual vector number is (1..8). */ -+ if (i < 1 || i > 8) -+ error ("invalid id value for exception attribute"); -+ -+ /* Setup nds32_isr_vectors[] array. */ -+ nds32_isr_vectors[i].category = NDS32_ISR_EXCEPTION; -+ strcpy (nds32_isr_vectors[i].func_name, func_name); -+ nds32_isr_vectors[i].save_reg = save_reg; -+ nds32_isr_vectors[i].nested_type = nested_type; -+ nds32_isr_vectors[i].security_level = s_level; -+ -+ /* Fetch next token. */ -+ value_str = strtok (NULL, ","); -+ } -+ -+ return; -+} -+ -+static void -+nds32_reset_attribute_parse_string (const char *original_str, -+ const char *func_name) -+{ -+ char target_str[100]; -+ char *vectors_str, *nmi_str, *warm_str, *value_str; -+ -+ /* Deal with reset attribute. Its vector number is always 0. */ -+ nds32_isr_vectors[0].category = NDS32_ISR_RESET; -+ -+ -+ /* 1. Parse 'vectors=XXXX'. */ -+ -+ /* Copy original string into a character array so that -+ the string APIs can handle it. */ -+ strcpy (target_str, original_str); -+ vectors_str = strstr (target_str, "vectors="); -+ /* The total vectors = interrupt + exception numbers + reset. -+ There are 8 exception and 1 reset in nds32 architecture. -+ If user forgets to assign 'vectors', user default 16 interrupts. */ -+ if (vectors_str != NULL) -+ { -+ /* Extract the value_str. */ -+ vectors_str = strtok (vectors_str, "="); -+ value_str = strtok (NULL, ";"); -+ nds32_isr_vectors[0].total_n_vectors = atoi (value_str) + 8 + 1; -+ } -+ else -+ nds32_isr_vectors[0].total_n_vectors = 16 + 8 + 1; -+ strcpy (nds32_isr_vectors[0].func_name, func_name); -+ -+ -+ /* 2. Parse 'nmi_func=YYYY'. */ -+ -+ /* Copy original string into a character array so that -+ the string APIs can handle it. */ -+ strcpy (target_str, original_str); -+ nmi_str = strstr (target_str, "nmi_func="); -+ if (nmi_str != NULL) -+ { -+ /* Extract the value_str. */ -+ nmi_str = strtok (nmi_str, "="); -+ value_str = strtok (NULL, ";"); -+ strcpy (nds32_isr_vectors[0].nmi_name, value_str); -+ } -+ -+ /* 3. Parse 'warm_func=ZZZZ'. */ -+ -+ /* Copy original string into a character array so that -+ the string APIs can handle it. */ -+ strcpy (target_str, original_str); -+ warm_str = strstr (target_str, "warm_func="); -+ if (warm_str != NULL) -+ { -+ /* Extract the value_str. */ -+ warm_str = strtok (warm_str, "="); -+ value_str = strtok (NULL, ";"); -+ strcpy (nds32_isr_vectors[0].warm_name, value_str); -+ } -+ -+ return; -+} -+/* ------------------------------------------------------------- */ - - /* A helper function to emit section head template. */ - static void -@@ -79,6 +332,15 @@ - char section_name[100]; - char symbol_name[100]; - -+ /* A critical isr does not need jump table section because -+ its behavior is not performed by two-level handler. */ -+ if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL) -+ { -+ fprintf (asm_out_file, "\t! The vector %02d is a critical isr !\n", -+ vector_id); -+ return; -+ } -+ - /* Prepare jmptbl section and symbol name. */ - snprintf (section_name, sizeof (section_name), - ".nds32_jmptbl.%02d", vector_id); -@@ -99,7 +361,6 @@ - const char *c_str = "CATEGORY"; - const char *sr_str = "SR"; - const char *nt_str = "NT"; -- const char *vs_str = "VS"; - char first_level_handler_name[100]; - char section_name[100]; - char symbol_name[100]; -@@ -147,30 +408,47 @@ - case NDS32_NESTED_READY: - nt_str = "nr"; - break; -+ case NDS32_CRITICAL: -+ /* The critical isr is not performed by two-level handler. */ -+ nt_str = ""; -+ break; - } - -- /* Currently we have 4-byte or 16-byte size for each vector. -- If it is 4-byte, the first level handler name has suffix string "_4b". */ -- vs_str = (nds32_isr_vector_size == 4) ? "_4b" : ""; -- - /* Now we can create first level handler name. */ -- snprintf (first_level_handler_name, sizeof (first_level_handler_name), -- "_nds32_%s_%s_%s%s", c_str, sr_str, nt_str, vs_str); -+ if (nds32_isr_vectors[vector_id].security_level == 0) -+ { -+ /* For security level 0, use normal first level handler name. */ -+ snprintf (first_level_handler_name, sizeof (first_level_handler_name), -+ "_nds32_%s_%s_%s", c_str, sr_str, nt_str); -+ } -+ else -+ { -+ /* For security level 1-3, use corresponding spl_1, spl_2, or spl_3. */ -+ snprintf (first_level_handler_name, sizeof (first_level_handler_name), -+ "_nds32_spl_%d", nds32_isr_vectors[vector_id].security_level); -+ } - - /* Prepare vector section and symbol name. */ - snprintf (section_name, sizeof (section_name), - ".nds32_vector.%02d", vector_id); - snprintf (symbol_name, sizeof (symbol_name), -- "_nds32_vector_%02d%s", vector_id, vs_str); -+ "_nds32_vector_%02d", vector_id); - - - /* Everything is ready. We can start emit vector section content. */ - nds32_emit_section_head_template (section_name, symbol_name, - floor_log2 (nds32_isr_vector_size), false); - -- /* According to the vector size, the instructions in the -- vector section may be different. */ -- if (nds32_isr_vector_size == 4) -+ /* First we check if it is a critical isr. -+ If so, jump to user handler directly; otherwise, the instructions -+ in the vector section may be different according to the vector size. */ -+ if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL) -+ { -+ /* This block is for critical isr. Jump to user handler directly. */ -+ fprintf (asm_out_file, "\tj\t%s ! jump to user handler directly\n", -+ nds32_isr_vectors[vector_id].func_name); -+ } -+ else if (nds32_isr_vector_size == 4) - { - /* This block is for 4-byte vector size. - Hardware $VID support is necessary and only one instruction -@@ -239,13 +517,11 @@ - { - unsigned int i; - unsigned int total_n_vectors; -- const char *vs_str; - char reset_handler_name[100]; - char section_name[100]; - char symbol_name[100]; - - total_n_vectors = nds32_isr_vectors[0].total_n_vectors; -- vs_str = (nds32_isr_vector_size == 4) ? "_4b" : ""; - - fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - BEGIN !\n"); - -@@ -261,7 +537,7 @@ - /* Emit vector references. */ - fprintf (asm_out_file, "\t ! references to vector section entries\n"); - for (i = 0; i < total_n_vectors; i++) -- fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d%s\n", i, vs_str); -+ fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d\n", i); - - /* Emit jmptbl_00 section. */ - snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.00"); -@@ -275,9 +551,9 @@ - - /* Emit vector_00 section. */ - snprintf (section_name, sizeof (section_name), ".nds32_vector.00"); -- snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00%s", vs_str); -+ snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00"); - snprintf (reset_handler_name, sizeof (reset_handler_name), -- "_nds32_reset%s", vs_str); -+ "_nds32_reset"); - - fprintf (asm_out_file, "\t! ....................................\n"); - nds32_emit_section_head_template (section_name, symbol_name, -@@ -323,12 +599,12 @@ - nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs) - { - int save_all_p, partial_save_p; -- int nested_p, not_nested_p, nested_ready_p; -+ int nested_p, not_nested_p, nested_ready_p, critical_p; - int intr_p, excp_p, reset_p; - - /* Initialize variables. */ - save_all_p = partial_save_p = 0; -- nested_p = not_nested_p = nested_ready_p = 0; -+ nested_p = not_nested_p = nested_ready_p = critical_p = 0; - intr_p = excp_p = reset_p = 0; - - /* We must check at MOST one attribute to set save-reg. */ -@@ -347,8 +623,10 @@ - not_nested_p = 1; - if (lookup_attribute ("nested_ready", func_attrs)) - nested_ready_p = 1; -+ if (lookup_attribute ("critical", func_attrs)) -+ critical_p = 1; - -- if ((nested_p + not_nested_p + nested_ready_p) > 1) -+ if ((nested_p + not_nested_p + nested_ready_p + critical_p) > 1) - error ("multiple nested types attributes to function %qD", func_decl); - - /* We must check at MOST one attribute to -@@ -362,6 +640,17 @@ - - if ((intr_p + excp_p + reset_p) > 1) - error ("multiple interrupt attributes to function %qD", func_decl); -+ -+ /* Do not allow isr attributes under linux toolchain. */ -+ if (TARGET_LINUX_ABI && intr_p) -+ error ("cannot use interrupt attributes to function %qD " -+ "under linux toolchain", func_decl); -+ if (TARGET_LINUX_ABI && excp_p) -+ error ("cannot use exception attributes to function %qD " -+ "under linux toolchain", func_decl); -+ if (TARGET_LINUX_ABI && reset_p) -+ error ("cannot use reset attributes to function %qD " -+ "under linux toolchain", func_decl); - } - - /* Function to construct isr vectors information array. -@@ -373,15 +662,21 @@ - const char *func_name) - { - tree save_all, partial_save; -- tree nested, not_nested, nested_ready; -+ tree nested, not_nested, nested_ready, critical; - tree intr, excp, reset; - -+ tree secure; -+ tree security_level_list; -+ tree security_level; -+ unsigned int s_level; -+ - save_all = lookup_attribute ("save_all", func_attrs); - partial_save = lookup_attribute ("partial_save", func_attrs); - - nested = lookup_attribute ("nested", func_attrs); - not_nested = lookup_attribute ("not_nested", func_attrs); - nested_ready = lookup_attribute ("nested_ready", func_attrs); -+ critical = lookup_attribute ("critical", func_attrs); - - intr = lookup_attribute ("interrupt", func_attrs); - excp = lookup_attribute ("exception", func_attrs); -@@ -391,6 +686,63 @@ - if (!intr && !excp && !reset) - return; - -+ /* At first, we need to retrieve security level. */ -+ secure = lookup_attribute ("secure", func_attrs); -+ if (secure != NULL) -+ { -+ security_level_list = TREE_VALUE (secure); -+ security_level = TREE_VALUE (security_level_list); -+ s_level = TREE_INT_CST_LOW (security_level); -+ } -+ else -+ { -+ /* If there is no secure attribute, the security level is set by -+ nds32_isr_secure_level, which is controlled by -misr-secure=X option. -+ By default nds32_isr_secure_level should be 0. */ -+ s_level = nds32_isr_secure_level; -+ } -+ -+ /* ------------------------------------------------------------- */ -+ /* FIXME: -+ FOR BACKWARD COMPATIBILITY, we need to support following patterns: -+ -+ __attribute__((interrupt("XXX;YYY;id=ZZZ"))) -+ __attribute__((exception("XXX;YYY;id=ZZZ"))) -+ __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) -+ -+ If interrupt/exception/reset appears and its argument is a -+ STRING_CST, we will parse string with some auxiliary functions -+ which set necessary isr information in the nds32_isr_vectors[] array. -+ After that, we can return immediately to avoid new-syntax isr -+ information construction. */ -+ if (intr != NULL_TREE -+ && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) -+ { -+ tree string_arg = TREE_VALUE (TREE_VALUE (intr)); -+ nds32_interrupt_attribute_parse_string (TREE_STRING_POINTER (string_arg), -+ func_name, -+ s_level); -+ return; -+ } -+ if (excp != NULL_TREE -+ && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) -+ { -+ tree string_arg = TREE_VALUE (TREE_VALUE (excp)); -+ nds32_exception_attribute_parse_string (TREE_STRING_POINTER (string_arg), -+ func_name, -+ s_level); -+ return; -+ } -+ if (reset != NULL_TREE -+ && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) -+ { -+ tree string_arg = TREE_VALUE (TREE_VALUE (reset)); -+ nds32_reset_attribute_parse_string (TREE_STRING_POINTER (string_arg), -+ func_name); -+ return; -+ } -+ /* ------------------------------------------------------------- */ -+ - /* If we are here, either we have interrupt/exception, - or reset attribute. */ - if (intr || excp) -@@ -417,6 +769,9 @@ - /* Add vector_number_offset to get actual vector number. */ - vector_id = TREE_INT_CST_LOW (id) + vector_number_offset; - -+ /* Set security level. */ -+ nds32_isr_vectors[vector_id].security_level = s_level; -+ - /* Enable corresponding vector and set function name. */ - nds32_isr_vectors[vector_id].category = (intr) - ? (NDS32_ISR_INTERRUPT) -@@ -436,6 +791,8 @@ - nds32_isr_vectors[vector_id].nested_type = NDS32_NOT_NESTED; - else if (nested_ready) - nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED_READY; -+ else if (critical) -+ nds32_isr_vectors[vector_id].nested_type = NDS32_CRITICAL; - - /* Advance to next id. */ - id_list = TREE_CHAIN (id_list); -@@ -492,7 +849,6 @@ - } - } - --/* A helper function to handle isr stuff at the beginning of asm file. */ - void - nds32_asm_file_start_for_isr (void) - { -@@ -505,15 +861,14 @@ - strcpy (nds32_isr_vectors[i].func_name, ""); - nds32_isr_vectors[i].save_reg = NDS32_PARTIAL_SAVE; - nds32_isr_vectors[i].nested_type = NDS32_NOT_NESTED; -+ nds32_isr_vectors[i].security_level = 0; - nds32_isr_vectors[i].total_n_vectors = 0; - strcpy (nds32_isr_vectors[i].nmi_name, ""); - strcpy (nds32_isr_vectors[i].warm_name, ""); - } - } - --/* A helper function to handle isr stuff at the end of asm file. */ --void --nds32_asm_file_end_for_isr (void) -+void nds32_asm_file_end_for_isr (void) - { - int i; - -@@ -547,6 +902,8 @@ - /* Found one vector which is interupt or exception. - Output its jmptbl and vector section content. */ - fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i); -+ fprintf (asm_out_file, "\t! security level: %d\n", -+ nds32_isr_vectors[i].security_level); - fprintf (asm_out_file, "\t! ------------------------------------\n"); - nds32_emit_isr_jmptbl_section (i); - fprintf (asm_out_file, "\t! ....................................\n"); -@@ -580,4 +937,65 @@ - || (t_reset != NULL_TREE)); - } - --/* ------------------------------------------------------------------------ */ -+/* Return true if FUNC is a isr function with critical attribute. */ -+bool -+nds32_isr_function_critical_p (tree func) -+{ -+ tree t_intr; -+ tree t_excp; -+ tree t_critical; -+ -+ tree attrs; -+ -+ if (TREE_CODE (func) != FUNCTION_DECL) -+ abort (); -+ -+ attrs = DECL_ATTRIBUTES (func); -+ -+ t_intr = lookup_attribute ("interrupt", attrs); -+ t_excp = lookup_attribute ("exception", attrs); -+ -+ t_critical = lookup_attribute ("critical", attrs); -+ -+ /* If both interrupt and exception attribute does not appear, -+ we can return false immediately. */ -+ if ((t_intr == NULL_TREE) && (t_excp == NULL_TREE)) -+ return false; -+ -+ /* Here we can guarantee either interrupt or ecxception attribute -+ does exist, so further check critical attribute. -+ If it also appears, we can return true. */ -+ if (t_critical != NULL_TREE) -+ return true; -+ -+ /* ------------------------------------------------------------- */ -+ /* FIXME: -+ FOR BACKWARD COMPATIBILITY, we need to handle string type. -+ If the string 'critical' appears in the interrupt/exception -+ string argument, we can return true. */ -+ if (t_intr != NULL_TREE || t_excp != NULL_TREE) -+ { -+ char target_str[100]; -+ char *critical_str; -+ tree t_check; -+ tree string_arg; -+ -+ t_check = t_intr ? t_intr : t_excp; -+ if (TREE_CODE (TREE_VALUE (TREE_VALUE (t_check))) == STRING_CST) -+ { -+ string_arg = TREE_VALUE (TREE_VALUE (t_check)); -+ strcpy (target_str, TREE_STRING_POINTER (string_arg)); -+ critical_str = strstr (target_str, "critical"); -+ -+ /* Found 'critical' string, so return true. */ -+ if (critical_str) -+ return true; -+ } -+ } -+ /* ------------------------------------------------------------- */ -+ -+ /* Other cases, this isr function is not critical type. */ -+ return false; -+} -+ -+/* ------------------------------------------------------------- */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32_isr.h gcc-8.2.0/gcc/config/nds32/nds32_isr.h ---- gcc-8.2.0.orig/gcc/config/nds32/nds32_isr.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32_isr.h 2019-01-25 15:38:32.833242671 +0100 -@@ -0,0 +1,526 @@ -+/* Intrinsic definitions of Andes NDS32 cpu for GNU compiler -+ Copyright (C) 2012-2018 Free Software Foundation, Inc. -+ Contributed by Andes Technology Corporation. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+#ifndef _NDS32_ISR_H -+#define _NDS32_ISR_H -+ -+/* Attribute of a interrupt or exception handler: -+ -+ NDS32_READY_NESTED: This handler is interruptible if user re-enable GIE bit. -+ NDS32_NESTED : This handler is interruptible. This is not suitable -+ exception handler. -+ NDS32_NOT_NESTED : This handler is NOT interruptible. Users have to do -+ some work if nested is wanted -+ NDS32_CRITICAL : This handler is critical ISR, which means it is small -+ and efficient. */ -+#define NDS32_READY_NESTED 0 -+#define NDS32_NESTED 1 -+#define NDS32_NOT_NESTED 2 -+#define NDS32_CRITICAL 3 -+ -+/* Attribute of a interrupt or exception handler: -+ -+ NDS32_SAVE_ALL_REGS : Save all registers in a table. -+ NDS32_SAVE_PARTIAL_REGS: Save partial registers. */ -+#define NDS32_SAVE_CALLER_REGS 0 -+#define NDS32_SAVE_ALL_REGS 1 -+ -+/* There are two version of Register table for interrupt and exception handler, -+ one for 16-register CPU the other for 32-register CPU. These structures are -+ used for context switching or system call handling. The address of this -+ data can be get from the input argument of the handler functions. -+ -+ For system call handling, r0 to r5 are used to pass arguments. If more -+ arguments are used they are put into the stack and its starting address is -+ in sp. Return value of system call can be put into r0 and r1 upon exit from -+ system call handler. System call ID is in a system register and it can be -+ fetched via intrinsic function. For more information please read ABI and -+ other related documents. -+ -+ For context switching, at least 2 values need to saved in kernel. One is -+ IPC and the other is the stack address of current task. Use intrinsic -+ function to get IPC and the input argument of the handler functions + 8 to -+ get stack address of current task. To do context switching, you replace -+ new_sp with the stack address of new task and replace IPC system register -+ with IPC of new task, then, just return from handler. The context switching -+ will happen. */ -+ -+/* Register table for exception handler; 32-register version. */ -+typedef struct -+{ -+ int r0; -+ int r1; -+ int r2; -+ int r3; -+ int r4; -+ int r5; -+ int r6; -+ int r7; -+ int r8; -+ int r9; -+ int r10; -+ int r11; -+ int r12; -+ int r13; -+ int r14; -+ int r15; -+ int r16; -+ int r17; -+ int r18; -+ int r19; -+ int r20; -+ int r21; -+ int r22; -+ int r23; -+ int r24; -+ int r25; -+ int r26; -+ int r27; -+ int fp; -+ int gp; -+ int lp; -+ int sp; -+} NDS32_GPR32; -+ -+/* Register table for exception handler; 16-register version. */ -+typedef struct -+{ -+ int r0; -+ int r1; -+ int r2; -+ int r3; -+ int r4; -+ int r5; -+ int r6; -+ int r7; -+ int r8; -+ int r9; -+ int r10; -+ int r15; -+ int fp; -+ int gp; -+ int lp; -+ int sp; -+} NDS32_GPR16; -+ -+ -+/* Use NDS32_REG32_TAB or NDS32_REG16_TAB in your program to -+ access register table. */ -+typedef struct -+{ -+ union -+ { -+ int reg_a[32] ; -+ NDS32_GPR32 reg_s ; -+ } u ; -+} NDS32_REG32_TAB; -+ -+typedef struct -+{ -+ union -+ { -+ int reg_a[16] ; -+ NDS32_GPR16 reg_s ; -+ } u ; -+} NDS32_REG16_TAB; -+ -+typedef struct -+{ -+ int d0lo; -+ int d0hi; -+ int d1lo; -+ int d1hi; -+} NDS32_DX_TAB; -+ -+typedef struct -+{ -+#ifdef __NDS32_EB__ -+ float fsr0; -+ float fsr1; -+ float fsr2; -+ float fsr3; -+ float fsr4; -+ float fsr5; -+ float fsr6; -+ float fsr7; -+#else -+ float fsr1; -+ float fsr0; -+ float fsr3; -+ float fsr2; -+ float fsr5; -+ float fsr4; -+ float fsr7; -+ float fsr6; -+#endif -+} NDS32_FSR8; -+ -+typedef struct -+{ -+ double dsr0; -+ double dsr1; -+ double dsr2; -+ double dsr3; -+} NDS32_DSR4; -+ -+typedef struct -+{ -+#ifdef __NDS32_EB__ -+ float fsr0; -+ float fsr1; -+ float fsr2; -+ float fsr3; -+ float fsr4; -+ float fsr5; -+ float fsr6; -+ float fsr7; -+ float fsr8; -+ float fsr9; -+ float fsr10; -+ float fsr11; -+ float fsr12; -+ float fsr13; -+ float fsr14; -+ float fsr15; -+#else -+ float fsr1; -+ float fsr0; -+ float fsr3; -+ float fsr2; -+ float fsr5; -+ float fsr4; -+ float fsr7; -+ float fsr6; -+ float fsr9; -+ float fsr8; -+ float fsr11; -+ float fsr10; -+ float fsr13; -+ float fsr12; -+ float fsr15; -+ float fsr14; -+#endif -+} NDS32_FSR16; -+ -+typedef struct -+{ -+ double dsr0; -+ double dsr1; -+ double dsr2; -+ double dsr3; -+ double dsr4; -+ double dsr5; -+ double dsr6; -+ double dsr7; -+} NDS32_DSR8; -+ -+typedef struct -+{ -+#ifdef __NDS32_EB__ -+ float fsr0; -+ float fsr1; -+ float fsr2; -+ float fsr3; -+ float fsr4; -+ float fsr5; -+ float fsr6; -+ float fsr7; -+ float fsr8; -+ float fsr9; -+ float fsr10; -+ float fsr11; -+ float fsr12; -+ float fsr13; -+ float fsr14; -+ float fsr15; -+ float fsr16; -+ float fsr17; -+ float fsr18; -+ float fsr19; -+ float fsr20; -+ float fsr21; -+ float fsr22; -+ float fsr23; -+ float fsr24; -+ float fsr25; -+ float fsr26; -+ float fsr27; -+ float fsr28; -+ float fsr29; -+ float fsr30; -+ float fsr31; -+#else -+ float fsr1; -+ float fsr0; -+ float fsr3; -+ float fsr2; -+ float fsr5; -+ float fsr4; -+ float fsr7; -+ float fsr6; -+ float fsr9; -+ float fsr8; -+ float fsr11; -+ float fsr10; -+ float fsr13; -+ float fsr12; -+ float fsr15; -+ float fsr14; -+ float fsr17; -+ float fsr16; -+ float fsr19; -+ float fsr18; -+ float fsr21; -+ float fsr20; -+ float fsr23; -+ float fsr22; -+ float fsr25; -+ float fsr24; -+ float fsr27; -+ float fsr26; -+ float fsr29; -+ float fsr28; -+ float fsr31; -+ float fsr30; -+#endif -+} NDS32_FSR32; -+ -+typedef struct -+{ -+ double dsr0; -+ double dsr1; -+ double dsr2; -+ double dsr3; -+ double dsr4; -+ double dsr5; -+ double dsr6; -+ double dsr7; -+ double dsr8; -+ double dsr9; -+ double dsr10; -+ double dsr11; -+ double dsr12; -+ double dsr13; -+ double dsr14; -+ double dsr15; -+} NDS32_DSR16; -+ -+typedef struct -+{ -+ double dsr0; -+ double dsr1; -+ double dsr2; -+ double dsr3; -+ double dsr4; -+ double dsr5; -+ double dsr6; -+ double dsr7; -+ double dsr8; -+ double dsr9; -+ double dsr10; -+ double dsr11; -+ double dsr12; -+ double dsr13; -+ double dsr14; -+ double dsr15; -+ double dsr16; -+ double dsr17; -+ double dsr18; -+ double dsr19; -+ double dsr20; -+ double dsr21; -+ double dsr22; -+ double dsr23; -+ double dsr24; -+ double dsr25; -+ double dsr26; -+ double dsr27; -+ double dsr28; -+ double dsr29; -+ double dsr30; -+ double dsr31; -+} NDS32_DSR32; -+ -+typedef struct -+{ -+ union -+ { -+ NDS32_FSR8 fsr_s ; -+ NDS32_DSR4 dsr_s ; -+ } u ; -+} NDS32_FPU8_TAB; -+ -+typedef struct -+{ -+ union -+ { -+ NDS32_FSR16 fsr_s ; -+ NDS32_DSR8 dsr_s ; -+ } u ; -+} NDS32_FPU16_TAB; -+ -+typedef struct -+{ -+ union -+ { -+ NDS32_FSR32 fsr_s ; -+ NDS32_DSR16 dsr_s ; -+ } u ; -+} NDS32_FPU32_TAB; -+ -+typedef struct -+{ -+ union -+ { -+ NDS32_FSR32 fsr_s ; -+ NDS32_DSR32 dsr_s ; -+ } u ; -+} NDS32_FPU64_TAB; -+ -+typedef struct -+{ -+ int ipc; -+ int ipsw; -+#if defined(NDS32_EXT_FPU_CONFIG_0) -+ NDS32_FPU8_TAB fpr; -+#elif defined(NDS32_EXT_FPU_CONFIG_1) -+ NDS32_FPU16_TAB fpr; -+#elif defined(NDS32_EXT_FPU_CONFIG_2) -+ NDS32_FPU32_TAB fpr; -+#elif defined(NDS32_EXT_FPU_CONFIG_3) -+ NDS32_FPU64_TAB fpr; -+#endif -+#if __NDS32_DX_REGS__ -+ NDS32_DX_TAB dxr; -+#endif -+#if __NDS32_EXT_IFC__ -+ int ifc_lp; -+ int filler; -+#endif -+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS -+ NDS32_REG16_TAB gpr; -+#else -+ NDS32_REG32_TAB gpr; -+#endif -+} NDS32_CONTEXT; -+ -+/* Predefined Vector Definition. -+ -+ For IVIC Mode: 9 to 14 are for hardware interrupt -+ and 15 is for software interrupt. -+ For EVIC Mode: 9 to 72 are for hardware interrupt -+ and software interrupt can be routed to any one of them. -+ -+ You may want to define your hardware interrupts in the following way -+ for easy maintainance. -+ -+ IVIC mode: -+ #define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1 -+ #define MY_HW_IVIC_USB NDS32_VECTOR_INTERRUPT_HW0 + 3 -+ EVIC mode: -+ #define MY_HW_EVIC_DMA NDS32_VECTOR_INTERRUPT_HW0 + 2 -+ #define MY_HW_EVIC_SWI NDS32_VECTOR_INTERRUPT_HW0 + 10 */ -+#define NDS32_VECTOR_RESET 0 -+#define NDS32_VECTOR_TLB_FILL 1 -+#define NDS32_VECTOR_PTE_NOT_PRESENT 2 -+#define NDS32_VECTOR_TLB_MISC 3 -+#define NDS32_VECTOR_TLB_VLPT_MISS 4 -+#define NDS32_VECTOR_MACHINE_ERROR 5 -+#define NDS32_VECTOR_DEBUG_RELATED 6 -+#define NDS32_VECTOR_GENERAL_EXCEPTION 7 -+#define NDS32_VECTOR_SYSCALL 8 -+#define NDS32_VECTOR_INTERRUPT_HW0 9 -+#define NDS32_VECTOR_INTERRUPT_HW1 10 -+#define NDS32_VECTOR_INTERRUPT_HW2 11 -+#define NDS32_VECTOR_INTERRUPT_HW3 12 -+#define NDS32_VECTOR_INTERRUPT_HW4 13 -+#define NDS32_VECTOR_INTERRUPT_HW5 14 -+#define NDS32_VECTOR_INTERRUPT_HW6 15 -+#define NDS32_VECTOR_SWI 15 /* THIS IS FOR IVIC MODE ONLY */ -+#define NDS32_VECTOR_INTERRUPT_HW7 16 -+#define NDS32_VECTOR_INTERRUPT_HW8 17 -+#define NDS32_VECTOR_INTERRUPT_HW9 18 -+#define NDS32_VECTOR_INTERRUPT_HW10 19 -+#define NDS32_VECTOR_INTERRUPT_HW11 20 -+#define NDS32_VECTOR_INTERRUPT_HW12 21 -+#define NDS32_VECTOR_INTERRUPT_HW13 22 -+#define NDS32_VECTOR_INTERRUPT_HW14 23 -+#define NDS32_VECTOR_INTERRUPT_HW15 24 -+#define NDS32_VECTOR_INTERRUPT_HW16 25 -+#define NDS32_VECTOR_INTERRUPT_HW17 26 -+#define NDS32_VECTOR_INTERRUPT_HW18 27 -+#define NDS32_VECTOR_INTERRUPT_HW19 28 -+#define NDS32_VECTOR_INTERRUPT_HW20 29 -+#define NDS32_VECTOR_INTERRUPT_HW21 30 -+#define NDS32_VECTOR_INTERRUPT_HW22 31 -+#define NDS32_VECTOR_INTERRUPT_HW23 32 -+#define NDS32_VECTOR_INTERRUPT_HW24 33 -+#define NDS32_VECTOR_INTERRUPT_HW25 34 -+#define NDS32_VECTOR_INTERRUPT_HW26 35 -+#define NDS32_VECTOR_INTERRUPT_HW27 36 -+#define NDS32_VECTOR_INTERRUPT_HW28 37 -+#define NDS32_VECTOR_INTERRUPT_HW29 38 -+#define NDS32_VECTOR_INTERRUPT_HW30 39 -+#define NDS32_VECTOR_INTERRUPT_HW31 40 -+#define NDS32_VECTOR_INTERRUPT_HW32 41 -+#define NDS32_VECTOR_INTERRUPT_HW33 42 -+#define NDS32_VECTOR_INTERRUPT_HW34 43 -+#define NDS32_VECTOR_INTERRUPT_HW35 44 -+#define NDS32_VECTOR_INTERRUPT_HW36 45 -+#define NDS32_VECTOR_INTERRUPT_HW37 46 -+#define NDS32_VECTOR_INTERRUPT_HW38 47 -+#define NDS32_VECTOR_INTERRUPT_HW39 48 -+#define NDS32_VECTOR_INTERRUPT_HW40 49 -+#define NDS32_VECTOR_INTERRUPT_HW41 50 -+#define NDS32_VECTOR_INTERRUPT_HW42 51 -+#define NDS32_VECTOR_INTERRUPT_HW43 52 -+#define NDS32_VECTOR_INTERRUPT_HW44 53 -+#define NDS32_VECTOR_INTERRUPT_HW45 54 -+#define NDS32_VECTOR_INTERRUPT_HW46 55 -+#define NDS32_VECTOR_INTERRUPT_HW47 56 -+#define NDS32_VECTOR_INTERRUPT_HW48 57 -+#define NDS32_VECTOR_INTERRUPT_HW49 58 -+#define NDS32_VECTOR_INTERRUPT_HW50 59 -+#define NDS32_VECTOR_INTERRUPT_HW51 60 -+#define NDS32_VECTOR_INTERRUPT_HW52 61 -+#define NDS32_VECTOR_INTERRUPT_HW53 62 -+#define NDS32_VECTOR_INTERRUPT_HW54 63 -+#define NDS32_VECTOR_INTERRUPT_HW55 64 -+#define NDS32_VECTOR_INTERRUPT_HW56 65 -+#define NDS32_VECTOR_INTERRUPT_HW57 66 -+#define NDS32_VECTOR_INTERRUPT_HW58 67 -+#define NDS32_VECTOR_INTERRUPT_HW59 68 -+#define NDS32_VECTOR_INTERRUPT_HW60 69 -+#define NDS32_VECTOR_INTERRUPT_HW61 70 -+#define NDS32_VECTOR_INTERRUPT_HW62 71 -+#define NDS32_VECTOR_INTERRUPT_HW63 72 -+ -+#define NDS32ATTR_RESET(option) __attribute__((reset(option))) -+#define NDS32ATTR_EXCEPT(type) __attribute__((exception(type))) -+#define NDS32ATTR_EXCEPTION(type) __attribute__((exception(type))) -+#define NDS32ATTR_INTERRUPT(type) __attribute__((interrupt(type))) -+#define NDS32ATTR_ISR(type) __attribute__((interrupt(type))) -+ -+#endif /* nds32_isr.h */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-linux.opt gcc-8.2.0/gcc/config/nds32/nds32-linux.opt ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-linux.opt 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-linux.opt 2019-01-25 15:38:32.829242659 +0100 -@@ -0,0 +1,16 @@ -+mcmodel= -+Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_LARGE) -+Specify the address generation strategy for code model. -+ -+Enum -+Name(nds32_cmodel_type) Type(enum nds32_cmodel_type) -+Known cmodel types (for use with the -mcmodel= option): -+ -+EnumValue -+Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL) -+ -+EnumValue -+Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM) -+ -+EnumValue -+Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.md gcc-8.2.0/gcc/config/nds32/nds32.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32.md 2018-04-08 11:21:30.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32.md 2019-01-25 15:38:32.833242671 +0100 -@@ -56,24 +56,29 @@ - ;; ------------------------------------------------------------------------ - - ;; CPU pipeline model. --(define_attr "pipeline_model" "n7,n8,e8,n9,simple" -+(define_attr "pipeline_model" "n7,n8,e8,n9,n10,graywolf,n13,simple" - (const - (cond [(match_test "nds32_cpu_option == CPU_N7") (const_string "n7") - (match_test "nds32_cpu_option == CPU_E8") (const_string "e8") - (match_test "nds32_cpu_option == CPU_N6 || nds32_cpu_option == CPU_N8") (const_string "n8") - (match_test "nds32_cpu_option == CPU_N9") (const_string "n9") -+ (match_test "nds32_cpu_option == CPU_N10") (const_string "n10") -+ (match_test "nds32_cpu_option == CPU_GRAYWOLF") (const_string "graywolf") -+ (match_test "nds32_cpu_option == CPU_N12") (const_string "n13") -+ (match_test "nds32_cpu_option == CPU_N13") (const_string "n13") - (match_test "nds32_cpu_option == CPU_SIMPLE") (const_string "simple")] - (const_string "n9")))) - - ;; Insn type, it is used to default other attribute values. - (define_attr "type" - "unknown,load,store,load_multiple,store_multiple,alu,alu_shift,pbsad,pbsada,mul,mac,div,branch,mmu,misc,\ -- falu,fmuls,fmuld,fmacs,fmacd,fdivs,fdivd,fsqrts,fsqrtd,fcmp,fabs,fcpy,fcmov,fmfsr,fmfdr,fmtsr,fmtdr,fload,fstore" -+ falu,fmuls,fmuld,fmacs,fmacd,fdivs,fdivd,fsqrts,fsqrtd,fcmp,fabs,fcpy,fcmov,fmfsr,fmfdr,fmtsr,fmtdr,fload,fstore,\ -+ dalu,dalu64,daluround,dcmp,dclip,dmul,dmac,dinsb,dpack,dbpick,dwext" - (const_string "unknown")) - - ;; Insn sub-type - (define_attr "subtype" -- "simple,shift" -+ "simple,shift,saturation" - (const_string "simple")) - - ;; Length, in bytes, default is 4-bytes. -@@ -133,6 +138,7 @@ - - ;; ---------------------------------------------------------------------------- - -+(include "nds32-dspext.md") - - ;; Move instructions. - -@@ -209,6 +215,27 @@ - low12_int)); - DONE; - } -+ -+ if ((REG_P (operands[0]) || GET_CODE (operands[0]) == SUBREG) -+ && SYMBOLIC_CONST_P (operands[1])) -+ { -+ if (TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (operands[1])) -+ { -+ nds32_expand_ict_move (operands); -+ DONE; -+ } -+ else if (nds32_tls_referenced_p (operands [1])) -+ { -+ nds32_expand_tls_move (operands); -+ DONE; -+ } -+ else if (flag_pic) -+ { -+ nds32_expand_pic_move (operands); -+ DONE; -+ } -+ } - }) - - (define_insn "*mov" -@@ -271,8 +298,8 @@ - ;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF - ;; are able to match such instruction template. - (define_insn "move_addr" -- [(set (match_operand:SI 0 "register_operand" "=l, r") -- (match_operand:SI 1 "nds32_symbolic_operand" " i, i"))] -+ [(set (match_operand:SI 0 "nds32_general_register_operand" "=l, r") -+ (match_operand:SI 1 "nds32_nonunspec_symbolic_operand" " i, i"))] - "" - "la\t%0, %1" - [(set_attr "type" "alu") -@@ -351,13 +378,58 @@ - - - ;; ---------------------------------------------------------------------------- -+(define_expand "extv" -+ [(set (match_operand 0 "register_operand" "") -+ (sign_extract (match_operand 1 "nonimmediate_operand" "") -+ (match_operand 2 "const_int_operand" "") -+ (match_operand 3 "const_int_operand" "")))] -+ "" -+{ -+ enum nds32_expand_result_type result = nds32_expand_extv (operands); -+ switch (result) -+ { -+ case EXPAND_DONE: -+ DONE; -+ break; -+ case EXPAND_FAIL: -+ FAIL; -+ break; -+ case EXPAND_CREATE_TEMPLATE: -+ break; -+ default: -+ gcc_unreachable (); -+ } -+}) -+ -+(define_expand "insv" -+ [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") -+ (match_operand 1 "const_int_operand" "") -+ (match_operand 2 "const_int_operand" "")) -+ (match_operand 3 "register_operand" ""))] -+ "" -+{ -+ enum nds32_expand_result_type result = nds32_expand_insv (operands); -+ switch (result) -+ { -+ case EXPAND_DONE: -+ DONE; -+ break; -+ case EXPAND_FAIL: -+ FAIL; -+ break; -+ case EXPAND_CREATE_TEMPLATE: -+ break; -+ default: -+ gcc_unreachable (); -+ } -+}) - - ;; Arithmetic instructions. - - (define_insn "addsi3" - [(set (match_operand:SI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") - (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") -- (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,Iu06, Is15, r")))] -+ (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,IU06, Is15, r")))] - "" - { - switch (which_alternative) -@@ -1428,11 +1500,30 @@ - (clobber (reg:SI LP_REGNUM)) - (clobber (reg:SI TA_REGNUM))])] - "" -- "" -+ { -+ rtx insn; -+ rtx sym = XEXP (operands[0], 0); -+ -+ if (TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (sym)) -+ { -+ rtx reg = gen_reg_rtx (Pmode); -+ emit_move_insn (reg, sym); -+ operands[0] = gen_const_mem (Pmode, reg); -+ } -+ -+ if (flag_pic) -+ { -+ insn = emit_call_insn (gen_call_internal -+ (XEXP (operands[0], 0), GEN_INT (0))); -+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); -+ DONE; -+ } -+ } - ) - - (define_insn "call_internal" -- [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i")) -+ [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, S")) - (match_operand 1)) - (clobber (reg:SI LP_REGNUM)) - (clobber (reg:SI TA_REGNUM))])] -@@ -1474,9 +1565,11 @@ - (const_int 2) - (const_int 4)) - ;; Alternative 1 -- (if_then_else (match_test "nds32_long_call_p (operands[0])") -- (const_int 12) -- (const_int 4)) -+ (if_then_else (match_test "flag_pic") -+ (const_int 16) -+ (if_then_else (match_test "nds32_long_call_p (operands[0])") -+ (const_int 12) -+ (const_int 4))) - ])] - ) - -@@ -1492,11 +1585,33 @@ - (match_operand 2))) - (clobber (reg:SI LP_REGNUM)) - (clobber (reg:SI TA_REGNUM))])] -- "") -+ "" -+ { -+ rtx insn; -+ rtx sym = XEXP (operands[1], 0); -+ -+ if (TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (sym)) -+ { -+ rtx reg = gen_reg_rtx (Pmode); -+ emit_move_insn (reg, sym); -+ operands[1] = gen_const_mem (Pmode, reg); -+ } -+ -+ if (flag_pic) -+ { -+ insn = -+ emit_call_insn (gen_call_value_internal -+ (operands[0], XEXP (operands[1], 0), GEN_INT (0))); -+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); -+ DONE; -+ } -+ } -+) - - (define_insn "call_value_internal" - [(parallel [(set (match_operand 0) -- (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i")) -+ (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, S")) - (match_operand 2))) - (clobber (reg:SI LP_REGNUM)) - (clobber (reg:SI TA_REGNUM))])] -@@ -1538,9 +1653,11 @@ - (const_int 2) - (const_int 4)) - ;; Alternative 1 -- (if_then_else (match_test "nds32_long_call_p (operands[1])") -- (const_int 12) -- (const_int 4)) -+ (if_then_else (match_test "flag_pic") -+ (const_int 16) -+ (if_then_else (match_test "nds32_long_call_p (operands[1])") -+ (const_int 12) -+ (const_int 4))) - ])] - ) - -@@ -1583,10 +1700,21 @@ - (const_int 0)) - (clobber (reg:SI TA_REGNUM)) - (return)])] -- "") -+ "" -+{ -+ rtx sym = XEXP (operands[0], 0); -+ -+ if (TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (sym)) -+ { -+ rtx reg = gen_reg_rtx (Pmode); -+ emit_move_insn (reg, sym); -+ operands[0] = gen_const_mem (Pmode, reg); -+ } -+}) - - (define_insn "sibcall_internal" -- [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i")) -+ [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, S")) - (match_operand 1)) - (clobber (reg:SI TA_REGNUM)) - (return)])] -@@ -1617,9 +1745,11 @@ - (const_int 2) - (const_int 4)) - ;; Alternative 1 -- (if_then_else (match_test "nds32_long_call_p (operands[0])") -- (const_int 12) -- (const_int 4)) -+ (if_then_else (match_test "flag_pic") -+ (const_int 16) -+ (if_then_else (match_test "nds32_long_call_p (operands[0])") -+ (const_int 12) -+ (const_int 4))) - ])] - ) - -@@ -1633,11 +1763,22 @@ - (const_int 0))) - (clobber (reg:SI TA_REGNUM)) - (return)])] -- "") -+ "" -+{ -+ rtx sym = XEXP (operands[1], 0); -+ -+ if (TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (sym)) -+ { -+ rtx reg = gen_reg_rtx (Pmode); -+ emit_move_insn (reg, sym); -+ operands[1] = gen_const_mem (Pmode, reg); -+ } -+}) - - (define_insn "sibcall_value_internal" - [(parallel [(set (match_operand 0) -- (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i")) -+ (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, S")) - (match_operand 2))) - (clobber (reg:SI TA_REGNUM)) - (return)])] -@@ -1668,9 +1809,11 @@ - (const_int 2) - (const_int 4)) - ;; Alternative 1 -- (if_then_else (match_test "nds32_long_call_p (operands[1])") -- (const_int 12) -- (const_int 4)) -+ (if_then_else (match_test "flag_pic") -+ (const_int 16) -+ (if_then_else (match_test "nds32_long_call_p (operands[1])") -+ (const_int 12) -+ (const_int 4))) - ])] - ) - -@@ -1687,12 +1830,33 @@ - nds32_expand_prologue_v3push (); - else - nds32_expand_prologue (); -+ -+ /* If cfun->machine->fp_as_gp_p is true, we can generate special -+ directive to guide linker doing fp-as-gp optimization. -+ However, for a naked function, which means -+ it should not have prologue/epilogue, -+ using fp-as-gp still requires saving $fp by push/pop behavior and -+ there is no benefit to use fp-as-gp on such small function. -+ So we need to make sure this function is NOT naked as well. */ -+ if (cfun->machine->fp_as_gp_p && !cfun->machine->naked_p) -+ emit_insn (gen_omit_fp_begin (gen_rtx_REG (SImode, FP_REGNUM))); -+ - DONE; - }) - - (define_expand "epilogue" [(const_int 0)] - "" - { -+ /* If cfun->machine->fp_as_gp_p is true, we can generate special -+ directive to guide linker doing fp-as-gp optimization. -+ However, for a naked function, which means -+ it should not have prologue/epilogue, -+ using fp-as-gp still requires saving $fp by push/pop behavior and -+ there is no benefit to use fp-as-gp on such small function. -+ So we need to make sure this function is NOT naked as well. */ -+ if (cfun->machine->fp_as_gp_p && !cfun->machine->naked_p) -+ emit_insn (gen_omit_fp_end (gen_rtx_REG (SImode, FP_REGNUM))); -+ - /* Note that only under V3/V3M ISA, we could use v3pop epilogue. - In addition, we need to check if v3push is indeed available. */ - if (NDS32_V3PUSH_AVAILABLE_P) -@@ -1792,7 +1956,8 @@ - "nds32_can_use_return_insn ()" - { - /* Emit as the simple return. */ -- if (cfun->machine->naked_p -+ if (!cfun->machine->fp_as_gp_p -+ && cfun->machine->naked_p - && (cfun->machine->va_args_size == 0)) - { - emit_jump_insn (gen_return_internal ()); -@@ -1802,9 +1967,14 @@ - - ;; This pattern is expanded only by the shrink-wrapping optimization - ;; on paths where the function prologue has not been executed. -+;; However, such optimization may reorder the prologue/epilogue blocks -+;; together with basic blocks within function body. -+;; So we must disable this pattern if we have already decided -+;; to perform fp_as_gp optimization, which requires prologue to be -+;; first block and epilogue to be last block. - (define_expand "simple_return" - [(simple_return)] -- "" -+ "!cfun->machine->fp_as_gp_p" - "" - ) - -@@ -1823,6 +1993,9 @@ - [(simple_return)] - "" - { -+ if (nds32_isr_function_critical_p (current_function_decl)) -+ return "iret"; -+ - if (TARGET_16_BIT) - return "ret5"; - else -@@ -1831,9 +2004,11 @@ - [(set_attr "type" "branch") - (set_attr "enabled" "yes") - (set (attr "length") -- (if_then_else (match_test "TARGET_16_BIT") -- (const_int 2) -- (const_int 4)))]) -+ (if_then_else (match_test "nds32_isr_function_critical_p (current_function_decl)") -+ (const_int 4) -+ (if_then_else (match_test "TARGET_16_BIT") -+ (const_int 2) -+ (const_int 4))))]) - - - ;; ---------------------------------------------------------------------------- -@@ -1868,6 +2043,7 @@ - { - rtx add_tmp; - rtx reg, test; -+ rtx tmp_reg; - - /* Step A: "k <-- (plus (operands[0]) (-operands[1]))". */ - if (operands[1] != const0_rtx) -@@ -1889,9 +2065,14 @@ - emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], - operands[4])); - -- /* Step C, D, E, and F, using another temporary register. */ -- rtx tmp = gen_reg_rtx (SImode); -- emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp)); -+ tmp_reg = gen_reg_rtx (SImode); -+ /* Step C, D, E, and F, using another temporary register tmp_reg. */ -+ if (flag_pic) -+ emit_use (pic_offset_table_rtx); -+ -+ emit_jump_insn (gen_casesi_internal (operands[0], -+ operands[3], -+ tmp_reg)); - DONE; - }) - -@@ -1927,13 +2108,30 @@ - else - return nds32_output_casesi (operands); - } -- [(set_attr "length" "20") -- (set_attr "type" "branch")]) -+ [(set_attr "type" "branch") -+ (set (attr "length") -+ (if_then_else (match_test "flag_pic") -+ (const_int 28) -+ (const_int 20)))]) - - ;; ---------------------------------------------------------------------------- - - ;; Performance Extension - -+; If -fwrapv option is issued, GCC expects there will be -+; signed overflow situation. So the ABS(INT_MIN) is still INT_MIN -+; (e.g. ABS(0x80000000)=0x80000000). -+; However, the hardware ABS instruction of nds32 target -+; always performs saturation: abs 0x80000000 -> 0x7fffffff. -+; So that we can only enable abssi2 pattern if flag_wrapv is NOT presented. -+(define_insn "abssi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (abs:SI (match_operand:SI 1 "register_operand" " r")))] -+ "TARGET_EXT_PERF && TARGET_HW_ABS && !flag_wrapv" -+ "abs\t%0, %1" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")]) -+ - (define_insn "clzsi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (clz:SI (match_operand:SI 1 "register_operand" " r")))] -@@ -1996,6 +2194,25 @@ - [(set_attr "length" "0")] - ) - -+;; Output .omit_fp_begin for fp-as-gp optimization. -+;; Also we have to set $fp register. -+(define_insn "omit_fp_begin" -+ [(set (match_operand:SI 0 "register_operand" "=x") -+ (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_OMIT_FP_BEGIN))] -+ "" -+ "! -----\;.omit_fp_begin\;la\t$fp,_FP_BASE_\;! -----" -+ [(set_attr "length" "8")] -+) -+ -+;; Output .omit_fp_end for fp-as-gp optimization. -+;; Claim that we have to use $fp register. -+(define_insn "omit_fp_end" -+ [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "x")] UNSPEC_VOLATILE_OMIT_FP_END)] -+ "" -+ "! -----\;.omit_fp_end\;! -----" -+ [(set_attr "length" "0")] -+) -+ - (define_insn "pop25return" - [(return) - (unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_POP25_RETURN)] -@@ -2004,6 +2221,36 @@ - [(set_attr "length" "0")] - ) - -+;; Add pc -+(define_insn "add_pc" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (plus:SI (match_operand:SI 1 "register_operand" "0") -+ (pc)))] -+ "TARGET_LINUX_ABI || flag_pic" -+ "add5.pc\t%0" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ -+(define_expand "bswapsi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (bswap:SI (match_operand:SI 1 "register_operand" "r")))] -+ "" -+{ -+ emit_insn (gen_unspec_wsbh (operands[0], operands[1])); -+ emit_insn (gen_rotrsi3 (operands[0], operands[0], GEN_INT (16))); -+ DONE; -+}) -+ -+(define_insn "bswaphi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (bswap:HI (match_operand:HI 1 "register_operand" "r")))] -+ "" -+ "wsbh\t%0, %1" -+ [(set_attr "type" "alu") -+ (set_attr "length" "4")] -+) -+ - ;; ---------------------------------------------------------------------------- - - ;; Patterns for exception handling -@@ -2068,3 +2315,57 @@ - }) - - ;; ---------------------------------------------------------------------------- -+ -+;; Patterns for TLS. -+;; The following two tls patterns don't be expanded directly because the -+;; intermediate value may be spilled into the stack. As a result, it is -+;; hard to analyze the define-use chain in the relax_opt pass. -+ -+ -+;; There is a unspec operand to record RELAX_GROUP number because each -+;; emitted instruction need a relax_hint above it. -+(define_insn "tls_desc" -+ [(set (reg:SI 0) -+ (call (unspec_volatile:SI [(match_operand:SI 0 "nds32_symbolic_operand" "i")] UNSPEC_TLS_DESC) -+ (const_int 1))) -+ (use (unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)) -+ (use (reg:SI GP_REGNUM)) -+ (clobber (reg:SI LP_REGNUM)) -+ (clobber (reg:SI TA_REGNUM))] -+ "" -+ { -+ return nds32_output_tls_desc (operands); -+ } -+ [(set_attr "length" "20") -+ (set_attr "type" "branch")] -+) -+ -+;; There is a unspec operand to record RELAX_GROUP number because each -+;; emitted instruction need a relax_hint above it. -+(define_insn "tls_ie" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "nds32_symbolic_operand" "i")] UNSPEC_TLS_IE)) -+ (use (unspec [(match_operand:SI 2 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)) -+ (use (reg:SI GP_REGNUM))] -+ "" -+ { -+ return nds32_output_tls_ie (operands); -+ } -+ [(set (attr "length") (if_then_else (match_test "flag_pic") -+ (const_int 12) -+ (const_int 8))) -+ (set_attr "type" "misc")] -+) -+ -+;; The pattern is for some relaxation groups that have to keep addsi3 in 32-bit mode. -+(define_insn "addsi3_32bit" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "%r") -+ (match_operand:SI 2 "register_operand" " r")] UNSPEC_ADD32))] -+ "" -+ "add\t%0, %1, %2"; -+ [(set_attr "type" "alu") -+ (set_attr "length" "4") -+ (set_attr "feature" "v1")]) -+ -+;; ---------------------------------------------------------------------------- -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-md-auxiliary.c gcc-8.2.0/gcc/config/nds32/nds32-md-auxiliary.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-md-auxiliary.c 2018-04-08 08:00:34.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-md-auxiliary.c 2019-01-25 15:38:32.829242659 +0100 -@@ -39,6 +39,9 @@ - #include "expr.h" - #include "emit-rtl.h" - #include "explow.h" -+#include "stringpool.h" -+#include "attribs.h" -+ - - /* ------------------------------------------------------------------------ */ - -@@ -261,6 +264,118 @@ - output_asm_insn (pattern, operands); - } - -+static void -+nds32_split_shiftrtdi3 (rtx dst, rtx src, rtx shiftamount, bool logic_shift_p) -+{ -+ rtx src_high_part; -+ rtx dst_high_part, dst_low_part; -+ -+ dst_high_part = nds32_di_high_part_subreg (dst); -+ src_high_part = nds32_di_high_part_subreg (src); -+ dst_low_part = nds32_di_low_part_subreg (dst); -+ -+ if (CONST_INT_P (shiftamount)) -+ { -+ if (INTVAL (shiftamount) < 32) -+ { -+ if (logic_shift_p) -+ { -+ emit_insn (gen_uwext (dst_low_part, src, -+ shiftamount)); -+ emit_insn (gen_lshrsi3 (dst_high_part, src_high_part, -+ shiftamount)); -+ } -+ else -+ { -+ emit_insn (gen_wext (dst_low_part, src, -+ shiftamount)); -+ emit_insn (gen_ashrsi3 (dst_high_part, src_high_part, -+ shiftamount)); -+ } -+ } -+ else -+ { -+ rtx new_shift_amout = gen_int_mode(INTVAL (shiftamount) - 32, SImode); -+ -+ if (logic_shift_p) -+ { -+ emit_insn (gen_lshrsi3 (dst_low_part, src_high_part, -+ new_shift_amout)); -+ emit_move_insn (dst_high_part, const0_rtx); -+ } -+ else -+ { -+ emit_insn (gen_ashrsi3 (dst_low_part, src_high_part, -+ new_shift_amout)); -+ emit_insn (gen_ashrsi3 (dst_high_part, src_high_part, -+ GEN_INT (31))); -+ } -+ } -+ } -+ else -+ { -+ rtx dst_low_part_l32, dst_high_part_l32; -+ rtx dst_low_part_g32, dst_high_part_g32; -+ rtx new_shift_amout, select_reg; -+ dst_low_part_l32 = gen_reg_rtx (SImode); -+ dst_high_part_l32 = gen_reg_rtx (SImode); -+ dst_low_part_g32 = gen_reg_rtx (SImode); -+ dst_high_part_g32 = gen_reg_rtx (SImode); -+ new_shift_amout = gen_reg_rtx (SImode); -+ select_reg = gen_reg_rtx (SImode); -+ -+ emit_insn (gen_andsi3 (shiftamount, shiftamount, GEN_INT (0x3f))); -+ -+ if (logic_shift_p) -+ { -+ /* -+ if (shiftamount < 32) -+ dst_low_part = wext (src, shiftamount) -+ dst_high_part = src_high_part >> shiftamount -+ else -+ dst_low_part = src_high_part >> (shiftamount & 0x1f) -+ dst_high_part = 0 -+ */ -+ emit_insn (gen_uwext (dst_low_part_l32, src, shiftamount)); -+ emit_insn (gen_lshrsi3 (dst_high_part_l32, src_high_part, -+ shiftamount)); -+ -+ emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f))); -+ emit_insn (gen_lshrsi3 (dst_low_part_g32, src_high_part, -+ new_shift_amout)); -+ emit_move_insn (dst_high_part_g32, const0_rtx); -+ } -+ else -+ { -+ /* -+ if (shiftamount < 32) -+ dst_low_part = wext (src, shiftamount) -+ dst_high_part = src_high_part >> shiftamount -+ else -+ dst_low_part = src_high_part >> (shiftamount & 0x1f) -+ # shift 31 for sign extend -+ dst_high_part = src_high_part >> 31 -+ */ -+ emit_insn (gen_wext (dst_low_part_l32, src, shiftamount)); -+ emit_insn (gen_ashrsi3 (dst_high_part_l32, src_high_part, -+ shiftamount)); -+ -+ emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f))); -+ emit_insn (gen_ashrsi3 (dst_low_part_g32, src_high_part, -+ new_shift_amout)); -+ emit_insn (gen_ashrsi3 (dst_high_part_g32, src_high_part, -+ GEN_INT (31))); -+ } -+ -+ emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32))); -+ -+ emit_insn (gen_cmovnsi (dst_low_part, select_reg, -+ dst_low_part_l32, dst_low_part_g32)); -+ emit_insn (gen_cmovnsi (dst_high_part, select_reg, -+ dst_high_part_l32, dst_high_part_g32)); -+ } -+} -+ - /* ------------------------------------------------------------------------ */ - - /* Auxiliary function for expand RTL pattern. */ -@@ -1195,8 +1310,166 @@ - } - } - -+enum nds32_expand_result_type -+nds32_expand_extv (rtx *operands) -+{ -+ gcc_assert (CONST_INT_P (operands[2]) && CONST_INT_P (operands[3])); -+ HOST_WIDE_INT width = INTVAL (operands[2]); -+ HOST_WIDE_INT bitpos = INTVAL (operands[3]); -+ rtx dst = operands[0]; -+ rtx src = operands[1]; -+ -+ if (MEM_P (src) -+ && width == 32 -+ && (bitpos % BITS_PER_UNIT) == 0 -+ && GET_MODE_BITSIZE (GET_MODE (dst)) == width) -+ { -+ rtx newmem = adjust_address (src, GET_MODE (dst), -+ bitpos / BITS_PER_UNIT); -+ -+ rtx base_addr = force_reg (Pmode, XEXP (newmem, 0)); -+ -+ emit_insn (gen_unaligned_loadsi (dst, base_addr)); -+ -+ return EXPAND_DONE; -+ } -+ return EXPAND_FAIL; -+} -+ -+enum nds32_expand_result_type -+nds32_expand_insv (rtx *operands) -+{ -+ gcc_assert (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2])); -+ HOST_WIDE_INT width = INTVAL (operands[1]); -+ HOST_WIDE_INT bitpos = INTVAL (operands[2]); -+ rtx dst = operands[0]; -+ rtx src = operands[3]; -+ -+ if (MEM_P (dst) -+ && width == 32 -+ && (bitpos % BITS_PER_UNIT) == 0 -+ && GET_MODE_BITSIZE (GET_MODE (src)) == width) -+ { -+ rtx newmem = adjust_address (dst, GET_MODE (src), -+ bitpos / BITS_PER_UNIT); -+ -+ rtx base_addr = force_reg (Pmode, XEXP (newmem, 0)); -+ -+ emit_insn (gen_unaligned_storesi (base_addr, src)); -+ -+ return EXPAND_DONE; -+ } -+ return EXPAND_FAIL; -+} -+ - /* ------------------------------------------------------------------------ */ - -+/* Function to generate PC relative jump table. -+ Refer to nds32.md for more details. -+ -+ The following is the sample for the case that diff value -+ can be presented in '.short' size. -+ -+ addi $r1, $r1, -(case_lower_bound) -+ slti $ta, $r1, (case_number) -+ beqz $ta, .L_skip_label -+ -+ la $ta, .L35 ! get jump table address -+ lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry -+ addi $ta, $r1, $ta -+ jr5 $ta -+ -+ ! jump table entry -+ L35: -+ .short .L25-.L35 -+ .short .L26-.L35 -+ .short .L27-.L35 -+ .short .L28-.L35 -+ .short .L29-.L35 -+ .short .L30-.L35 -+ .short .L31-.L35 -+ .short .L32-.L35 -+ .short .L33-.L35 -+ .short .L34-.L35 */ -+const char * -+nds32_output_casesi_pc_relative (rtx *operands) -+{ -+ machine_mode mode; -+ rtx diff_vec; -+ -+ diff_vec = PATTERN (NEXT_INSN (as_a (operands[1]))); -+ -+ gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); -+ -+ /* Step C: "t <-- operands[1]". */ -+ if (flag_pic) -+ { -+ output_asm_insn ("sethi\t$ta, hi20(%l1@GOTOFF)", operands); -+ output_asm_insn ("ori\t$ta, $ta, lo12(%l1@GOTOFF)", operands); -+ output_asm_insn ("add\t$ta, $ta, $gp", operands); -+ } -+ else -+ output_asm_insn ("la\t$ta, %l1", operands); -+ -+ /* Get the mode of each element in the difference vector. */ -+ mode = GET_MODE (diff_vec); -+ -+ /* Step D: "z <-- (mem (plus (operands[0] << m) t))", -+ where m is 0, 1, or 2 to load address-diff value from table. */ -+ switch (mode) -+ { -+ case E_QImode: -+ output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands); -+ break; -+ case E_HImode: -+ output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands); -+ break; -+ case E_SImode: -+ output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); -+ break; -+ default: -+ gcc_unreachable (); -+ } -+ -+ /* Step E: "t <-- z + t". -+ Add table label_ref with address-diff value to -+ obtain target case address. */ -+ output_asm_insn ("add\t$ta, %2, $ta", operands); -+ -+ /* Step F: jump to target with register t. */ -+ if (TARGET_16_BIT) -+ return "jr5\t$ta"; -+ else -+ return "jr\t$ta"; -+} -+ -+/* Function to generate normal jump table. */ -+const char * -+nds32_output_casesi (rtx *operands) -+{ -+ /* Step C: "t <-- operands[1]". */ -+ if (flag_pic) -+ { -+ output_asm_insn ("sethi\t$ta, hi20(%l1@GOTOFF)", operands); -+ output_asm_insn ("ori\t$ta, $ta, lo12(%l1@GOTOFF)", operands); -+ output_asm_insn ("add\t$ta, $ta, $gp", operands); -+ } -+ else -+ output_asm_insn ("la\t$ta, %l1", operands); -+ -+ /* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */ -+ output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); -+ -+ /* No need to perform Step E, which is only used for -+ pc relative jump table. */ -+ -+ /* Step F: jump to target with register z. */ -+ if (TARGET_16_BIT) -+ return "jr5\t%2"; -+ else -+ return "jr\t%2"; -+} -+ - /* Function to return memory format. */ - enum nds32_16bit_address_type - nds32_mem_format (rtx op) -@@ -1757,11 +2030,8 @@ - - /* If we step here, we are going to do v3push or multiple push operation. */ - -- /* The v3push/v3pop instruction should only be applied on -- none-isr and none-variadic function. */ -- if (TARGET_V3PUSH -- && !nds32_isr_function_p (current_function_decl) -- && (cfun->machine->va_args_size == 0)) -+ /* Refer to nds32.h, where we comment when push25/pop25 are available. */ -+ if (NDS32_V3PUSH_AVAILABLE_P) - { - /* For stack v3push: - operands[0]: Re -@@ -1881,11 +2151,8 @@ - - /* If we step here, we are going to do v3pop or multiple pop operation. */ - -- /* The v3push/v3pop instruction should only be applied on -- none-isr and none-variadic function. */ -- if (TARGET_V3PUSH -- && !nds32_isr_function_p (current_function_decl) -- && (cfun->machine->va_args_size == 0)) -+ /* Refer to nds32.h, where we comment when push25/pop25 are available. */ -+ if (NDS32_V3PUSH_AVAILABLE_P) - { - /* For stack v3pop: - operands[0]: Re -@@ -2022,77 +2289,6 @@ - return ""; - } - --/* Function to generate PC relative jump table. -- Refer to nds32.md for more details. -- -- The following is the sample for the case that diff value -- can be presented in '.short' size. -- -- addi $r1, $r1, -(case_lower_bound) -- slti $ta, $r1, (case_number) -- beqz $ta, .L_skip_label -- -- la $ta, .L35 ! get jump table address -- lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry -- addi $ta, $r1, $ta -- jr5 $ta -- -- ! jump table entry -- L35: -- .short .L25-.L35 -- .short .L26-.L35 -- .short .L27-.L35 -- .short .L28-.L35 -- .short .L29-.L35 -- .short .L30-.L35 -- .short .L31-.L35 -- .short .L32-.L35 -- .short .L33-.L35 -- .short .L34-.L35 */ --const char * --nds32_output_casesi_pc_relative (rtx *operands) --{ -- machine_mode mode; -- rtx diff_vec; -- -- diff_vec = PATTERN (NEXT_INSN (as_a (operands[1]))); -- -- gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); -- -- /* Step C: "t <-- operands[1]". */ -- output_asm_insn ("la\t$ta, %l1", operands); -- -- /* Get the mode of each element in the difference vector. */ -- mode = GET_MODE (diff_vec); -- -- /* Step D: "z <-- (mem (plus (operands[0] << m) t))", -- where m is 0, 1, or 2 to load address-diff value from table. */ -- switch (mode) -- { -- case E_QImode: -- output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands); -- break; -- case E_HImode: -- output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands); -- break; -- case E_SImode: -- output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); -- break; -- default: -- gcc_unreachable (); -- } -- -- /* Step E: "t <-- z + t". -- Add table label_ref with address-diff value to -- obtain target case address. */ -- output_asm_insn ("add\t$ta, %2, $ta", operands); -- -- /* Step F: jump to target with register t. */ -- if (TARGET_16_BIT) -- return "jr5\t$ta"; -- else -- return "jr\t$ta"; --} - - /* output a float load instruction */ - const char * -@@ -2250,52 +2446,51 @@ - return ""; - } - --/* Function to generate normal jump table. */ - const char * --nds32_output_casesi (rtx *operands) -+nds32_output_smw_single_word (rtx *operands) - { -- /* Step C: "t <-- operands[1]". */ -- output_asm_insn ("la\t$ta, %l1", operands); -- -- /* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */ -- output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); -- -- /* No need to perform Step E, which is only used for -- pc relative jump table. */ -+ char buff[100]; -+ unsigned regno; -+ int enable4; -+ bool update_base_p; -+ rtx base_addr = operands[0]; -+ rtx base_reg; -+ rtx otherops[2]; - -- /* Step F: jump to target with register z. */ -- if (TARGET_16_BIT) -- return "jr5\t%2"; -+ if (REG_P (XEXP (base_addr, 0))) -+ { -+ update_base_p = false; -+ base_reg = XEXP (base_addr, 0); -+ } - else -- return "jr\t%2"; --} -+ { -+ update_base_p = true; -+ base_reg = XEXP (XEXP (base_addr, 0), 0); -+ } - --/* Auxiliary functions for lwm/smw. */ --bool --nds32_valid_smw_lwm_base_p (rtx op) --{ -- rtx base_addr; -+ const char *update_base = update_base_p ? "m" : ""; - -- if (!MEM_P (op)) -- return false; -+ regno = REGNO (operands[1]); - -- base_addr = XEXP (op, 0); -+ otherops[0] = base_reg; -+ otherops[1] = operands[1]; - -- if (REG_P (base_addr)) -- return true; -+ if (regno >= 28) -+ { -+ enable4 = nds32_regno_to_enable4 (regno); -+ sprintf (buff, "smw.bi%s\t$sp, [%%0], $sp, %x", update_base, enable4); -+ } - else - { -- if (GET_CODE (base_addr) == POST_INC -- && REG_P (XEXP (base_addr, 0))) -- return true; -+ sprintf (buff, "smw.bi%s\t%%1, [%%0], %%1", update_base); - } -- -- return false; -+ output_asm_insn (buff, otherops); -+ return ""; - } - - /* ------------------------------------------------------------------------ */ - const char * --nds32_output_smw_single_word (rtx *operands) -+nds32_output_smw_double_word (rtx *operands) - { - char buff[100]; - unsigned regno; -@@ -2303,7 +2498,7 @@ - bool update_base_p; - rtx base_addr = operands[0]; - rtx base_reg; -- rtx otherops[2]; -+ rtx otherops[3]; - - if (REG_P (XEXP (base_addr, 0))) - { -@@ -2322,15 +2517,22 @@ - - otherops[0] = base_reg; - otherops[1] = operands[1]; -+ otherops[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);; - - if (regno >= 28) - { -- enable4 = nds32_regno_to_enable4 (regno); -+ enable4 = nds32_regno_to_enable4 (regno) -+ | nds32_regno_to_enable4 (regno + 1); - sprintf (buff, "smw.bi%s\t$sp, [%%0], $sp, %x", update_base, enable4); - } -+ else if (regno == 27) -+ { -+ enable4 = nds32_regno_to_enable4 (regno + 1); -+ sprintf (buff, "smw.bi%s\t%%1, [%%0], %%1, %x", update_base, enable4); -+ } - else - { -- sprintf (buff, "smw.bi%s\t%%1, [%%0], %%1", update_base); -+ sprintf (buff, "smw.bi%s\t%%1, [%%0], %%2", update_base); - } - output_asm_insn (buff, otherops); - return ""; -@@ -2415,16 +2617,17 @@ - if (mode == DImode) - { - /* Load doubleword, we need two registers to access. */ -- reg[0] = simplify_gen_subreg (SImode, operands[0], -- GET_MODE (operands[0]), 0); -- reg[1] = simplify_gen_subreg (SImode, operands[0], -- GET_MODE (operands[0]), 4); -+ reg[0] = nds32_di_low_part_subreg (operands[0]); -+ reg[1] = nds32_di_high_part_subreg (operands[0]); - /* A register only store 4 byte. */ - width = GET_MODE_SIZE (SImode) - 1; - } - else - { -- reg[0] = operands[0]; -+ if (VECTOR_MODE_P (mode)) -+ reg[0] = gen_reg_rtx (SImode); -+ else -+ reg[0] = operands[0]; - } - - for (num_reg = (mode == DImode) ? 2 : 1; num_reg > 0; num_reg--) -@@ -2466,6 +2669,8 @@ - offset = offset + offset_adj; - } - } -+ if (VECTOR_MODE_P (mode)) -+ convert_move (operands[0], reg[0], false); - } - - void -@@ -2499,16 +2704,20 @@ - if (mode == DImode) - { - /* Load doubleword, we need two registers to access. */ -- reg[0] = simplify_gen_subreg (SImode, operands[1], -- GET_MODE (operands[1]), 0); -- reg[1] = simplify_gen_subreg (SImode, operands[1], -- GET_MODE (operands[1]), 4); -+ reg[0] = nds32_di_low_part_subreg (operands[1]); -+ reg[1] = nds32_di_high_part_subreg (operands[1]); - /* A register only store 4 byte. */ - width = GET_MODE_SIZE (SImode) - 1; - } - else - { -- reg[0] = operands[1]; -+ if (VECTOR_MODE_P (mode)) -+ { -+ reg[0] = gen_reg_rtx (SImode); -+ convert_move (reg[0], operands[1], false); -+ } -+ else -+ reg[0] = operands[1]; - } - - for (num_reg = (mode == DImode) ? 2 : 1; num_reg > 0; num_reg--) -@@ -2765,6 +2974,36 @@ - return ""; - } - -+const char * -+nds32_output_unpkd8 (rtx output, rtx input, -+ rtx high_idx_rtx, rtx low_idx_rtx, -+ bool signed_p) -+{ -+ char pattern[100]; -+ rtx output_operands[2]; -+ HOST_WIDE_INT high_idx, low_idx; -+ high_idx = INTVAL (high_idx_rtx); -+ low_idx = INTVAL (low_idx_rtx); -+ -+ gcc_assert (high_idx >= 0 && high_idx <= 3); -+ gcc_assert (low_idx >= 0 && low_idx <= 3); -+ -+ /* We only have 10, 20, 30 and 31. */ -+ if ((low_idx != 0 || high_idx == 0) && -+ !(low_idx == 1 && high_idx == 3)) -+ return "#"; -+ -+ char sign_char = signed_p ? 's' : 'z'; -+ -+ sprintf (pattern, -+ "%cunpkd8" HOST_WIDE_INT_PRINT_DEC HOST_WIDE_INT_PRINT_DEC "\t%%0, %%1", -+ sign_char, high_idx, low_idx); -+ output_operands[0] = output; -+ output_operands[1] = input; -+ output_asm_insn (pattern, output_operands); -+ return ""; -+} -+ - /* Return true if SYMBOL_REF X binds locally. */ - - static bool -@@ -2782,22 +3021,15 @@ - char pattern[100]; - bool noreturn_p; - -- if (GET_CODE (symbol) == CONST) -- { -- symbol= XEXP (symbol, 0); -- -- if (GET_CODE (symbol) == PLUS) -- symbol = XEXP (symbol, 0); -- } -- -- gcc_assert (GET_CODE (symbol) == SYMBOL_REF -- || REG_P (symbol)); -- - if (nds32_long_call_p (symbol)) - strcpy (pattern, long_call); - else - strcpy (pattern, call); - -+ if (flag_pic && CONSTANT_P (symbol) -+ && !nds32_symbol_binds_local_p (symbol)) -+ strcat (pattern, "@PLT"); -+ - if (align_p) - strcat (pattern, "\n\t.align 2"); - -@@ -2815,6 +3047,91 @@ - return ""; - } - -+bool -+nds32_need_split_sms_p (rtx in0_idx0, rtx in1_idx0, -+ rtx in0_idx1, rtx in1_idx1) -+{ -+ /* smds or smdrs. */ -+ if (INTVAL (in0_idx0) == INTVAL (in1_idx0) -+ && INTVAL (in0_idx1) == INTVAL (in1_idx1) -+ && INTVAL (in0_idx0) != INTVAL (in0_idx1)) -+ return false; -+ -+ /* smxds. */ -+ if (INTVAL (in0_idx0) != INTVAL (in0_idx1) -+ && INTVAL (in1_idx0) != INTVAL (in1_idx1)) -+ return false; -+ -+ return true; -+} -+ -+const char * -+nds32_output_sms (rtx in0_idx0, rtx in1_idx0, -+ rtx in0_idx1, rtx in1_idx1) -+{ -+ if (nds32_need_split_sms_p (in0_idx0, in1_idx0, -+ in0_idx1, in1_idx1)) -+ return "#"; -+ /* out = in0[in0_idx0] * in1[in1_idx0] - in0[in0_idx1] * in1[in1_idx1] */ -+ -+ /* smds or smdrs. */ -+ if (INTVAL (in0_idx0) == INTVAL (in1_idx0) -+ && INTVAL (in0_idx1) == INTVAL (in1_idx1) -+ && INTVAL (in0_idx0) != INTVAL (in0_idx1)) -+ { -+ if (INTVAL (in0_idx0) == 0) -+ { -+ if (TARGET_BIG_ENDIAN) -+ return "smds\t%0, %1, %2"; -+ else -+ return "smdrs\t%0, %1, %2"; -+ } -+ else -+ { -+ if (TARGET_BIG_ENDIAN) -+ return "smdrs\t%0, %1, %2"; -+ else -+ return "smds\t%0, %1, %2"; -+ } -+ } -+ -+ if (INTVAL (in0_idx0) != INTVAL (in0_idx1) -+ && INTVAL (in1_idx0) != INTVAL (in1_idx1)) -+ { -+ if (INTVAL (in0_idx0) == 1) -+ { -+ if (TARGET_BIG_ENDIAN) -+ return "smxds\t%0, %2, %1"; -+ else -+ return "smxds\t%0, %1, %2"; -+ } -+ else -+ { -+ if (TARGET_BIG_ENDIAN) -+ return "smxds\t%0, %1, %2"; -+ else -+ return "smxds\t%0, %2, %1"; -+ } -+ } -+ -+ gcc_unreachable (); -+ return ""; -+} -+ -+void -+nds32_split_sms (rtx out, rtx in0, rtx in1, -+ rtx in0_idx0, rtx in1_idx0, -+ rtx in0_idx1, rtx in1_idx1) -+{ -+ rtx result0 = gen_reg_rtx (SImode); -+ rtx result1 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3v (result0, in0, in1, -+ in0_idx0, in1_idx0)); -+ emit_insn (gen_mulhisi3v (result1, in0, in1, -+ in0_idx1, in1_idx1)); -+ emit_insn (gen_subsi3 (out, result0, result1)); -+} -+ - /* Spilt a doubleword instrucion to two single word instructions. */ - void - nds32_spilt_doubleword (rtx *operands, bool load_p) -@@ -2846,16 +3163,30 @@ - /* generate low_part and high_part memory format: - low_part: (post_modify ((reg) (plus (reg) (const 4))) - high_part: (post_modify ((reg) (plus (reg) (const -12))) */ -- low_part[mem] = gen_frame_mem (SImode, -- gen_rtx_POST_MODIFY (Pmode, sub_mem, -- gen_rtx_PLUS (Pmode, -- sub_mem, -- GEN_INT (4)))); -- high_part[mem] = gen_frame_mem (SImode, -- gen_rtx_POST_MODIFY (Pmode, sub_mem, -- gen_rtx_PLUS (Pmode, -- sub_mem, -- GEN_INT (-12)))); -+ low_part[mem] = gen_rtx_MEM (SImode, -+ gen_rtx_POST_MODIFY (Pmode, sub_mem, -+ gen_rtx_PLUS (Pmode, -+ sub_mem, -+ GEN_INT (4)))); -+ high_part[mem] = gen_rtx_MEM (SImode, -+ gen_rtx_POST_MODIFY (Pmode, sub_mem, -+ gen_rtx_PLUS (Pmode, -+ sub_mem, -+ GEN_INT (-12)))); -+ } -+ else if (GET_CODE (sub_mem) == POST_INC) -+ { -+ /* memory format is (post_inc (reg)), -+ so that extract (reg) from the (post_inc (reg)) pattern. */ -+ sub_mem = XEXP (sub_mem, 0); -+ -+ /* generate low_part and high_part memory format: -+ low_part: (post_inc (reg)) -+ high_part: (post_inc (reg)) */ -+ low_part[mem] = gen_rtx_MEM (SImode, -+ gen_rtx_POST_INC (Pmode, sub_mem)); -+ high_part[mem] = gen_rtx_MEM (SImode, -+ gen_rtx_POST_INC (Pmode, sub_mem)); - } - else if (GET_CODE (sub_mem) == POST_MODIFY) - { -@@ -2872,14 +3203,14 @@ - /* Generate low_part and high_part memory format: - low_part: (post_modify ((reg) (plus (reg) (const))) - high_part: ((plus (reg) (const 4))) */ -- low_part[mem] = gen_frame_mem (SImode, -- gen_rtx_POST_MODIFY (Pmode, post_mem, -- gen_rtx_PLUS (Pmode, -- post_mem, -- post_val))); -- high_part[mem] = gen_frame_mem (SImode, plus_constant (Pmode, -- post_mem, -- 4)); -+ low_part[mem] = gen_rtx_MEM (SImode, -+ gen_rtx_POST_MODIFY (Pmode, post_mem, -+ gen_rtx_PLUS (Pmode, -+ post_mem, -+ post_val))); -+ high_part[mem] = gen_rtx_MEM (SImode, plus_constant (Pmode, -+ post_mem, -+ 4)); - } - else - { -@@ -2924,11 +3255,516 @@ - } - } - -+void -+nds32_split_ashiftdi3 (rtx dst, rtx src, rtx shiftamount) -+{ -+ rtx src_high_part, src_low_part; -+ rtx dst_high_part, dst_low_part; -+ -+ dst_high_part = nds32_di_high_part_subreg (dst); -+ dst_low_part = nds32_di_low_part_subreg (dst); -+ -+ src_high_part = nds32_di_high_part_subreg (src); -+ src_low_part = nds32_di_low_part_subreg (src); -+ -+ /* We need to handle shift more than 32 bit!!!! */ -+ if (CONST_INT_P (shiftamount)) -+ { -+ if (INTVAL (shiftamount) < 32) -+ { -+ rtx ext_start; -+ ext_start = gen_int_mode(32 - INTVAL (shiftamount), SImode); -+ -+ emit_insn (gen_wext (dst_high_part, src, ext_start)); -+ emit_insn (gen_ashlsi3 (dst_low_part, src_low_part, shiftamount)); -+ } -+ else -+ { -+ rtx new_shift_amout = gen_int_mode(INTVAL (shiftamount) - 32, SImode); -+ -+ emit_insn (gen_ashlsi3 (dst_high_part, src_low_part, -+ new_shift_amout)); -+ -+ emit_move_insn (dst_low_part, GEN_INT (0)); -+ } -+ } -+ else -+ { -+ rtx dst_low_part_l32, dst_high_part_l32; -+ rtx dst_low_part_g32, dst_high_part_g32; -+ rtx new_shift_amout, select_reg; -+ dst_low_part_l32 = gen_reg_rtx (SImode); -+ dst_high_part_l32 = gen_reg_rtx (SImode); -+ dst_low_part_g32 = gen_reg_rtx (SImode); -+ dst_high_part_g32 = gen_reg_rtx (SImode); -+ new_shift_amout = gen_reg_rtx (SImode); -+ select_reg = gen_reg_rtx (SImode); -+ -+ rtx ext_start; -+ ext_start = gen_reg_rtx (SImode); -+ -+ /* -+ if (shiftamount < 32) -+ dst_low_part = src_low_part << shiftamout -+ dst_high_part = wext (src, 32 - shiftamount) -+ # wext can't handle wext (src, 32) since it's only take rb[0:4] -+ # for extract. -+ dst_high_part = shiftamount == 0 ? src_high_part : dst_high_part -+ else -+ dst_low_part = 0 -+ dst_high_part = src_low_part << shiftamount & 0x1f -+ */ -+ -+ emit_insn (gen_subsi3 (ext_start, -+ gen_int_mode (32, SImode), -+ shiftamount)); -+ emit_insn (gen_wext (dst_high_part_l32, src, ext_start)); -+ -+ /* Handle for shiftamout == 0. */ -+ emit_insn (gen_cmovzsi (dst_high_part_l32, shiftamount, -+ src_high_part, dst_high_part_l32)); -+ -+ emit_insn (gen_ashlsi3 (dst_low_part_l32, src_low_part, shiftamount)); -+ -+ emit_move_insn (dst_low_part_g32, const0_rtx); -+ emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f))); -+ emit_insn (gen_ashlsi3 (dst_high_part_g32, src_low_part, -+ new_shift_amout)); -+ -+ emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32))); -+ -+ emit_insn (gen_cmovnsi (dst_low_part, select_reg, -+ dst_low_part_l32, dst_low_part_g32)); -+ emit_insn (gen_cmovnsi (dst_high_part, select_reg, -+ dst_high_part_l32, dst_high_part_g32)); -+ } -+} -+ -+void -+nds32_split_ashiftrtdi3 (rtx dst, rtx src, rtx shiftamount) -+{ -+ nds32_split_shiftrtdi3 (dst, src, shiftamount, false); -+} -+ -+void -+nds32_split_lshiftrtdi3 (rtx dst, rtx src, rtx shiftamount) -+{ -+ nds32_split_shiftrtdi3 (dst, src, shiftamount, true); -+} -+ -+void -+nds32_split_rotatertdi3 (rtx dst, rtx src, rtx shiftamount) -+{ -+ rtx dst_low_part_l32, dst_high_part_l32; -+ rtx dst_low_part_g32, dst_high_part_g32; -+ rtx select_reg, low5bit, low5bit_inv, minus32sa; -+ rtx dst_low_part_g32_tmph; -+ rtx dst_low_part_g32_tmpl; -+ rtx dst_high_part_l32_tmph; -+ rtx dst_high_part_l32_tmpl; -+ -+ rtx src_low_part, src_high_part; -+ rtx dst_high_part, dst_low_part; -+ -+ shiftamount = force_reg (SImode, shiftamount); -+ -+ emit_insn (gen_andsi3 (shiftamount, -+ shiftamount, -+ gen_int_mode (0x3f, SImode))); -+ -+ dst_high_part = nds32_di_high_part_subreg (dst); -+ dst_low_part = nds32_di_low_part_subreg (dst); -+ -+ src_high_part = nds32_di_high_part_subreg (src); -+ src_low_part = nds32_di_low_part_subreg (src); -+ -+ dst_low_part_l32 = gen_reg_rtx (SImode); -+ dst_high_part_l32 = gen_reg_rtx (SImode); -+ dst_low_part_g32 = gen_reg_rtx (SImode); -+ dst_high_part_g32 = gen_reg_rtx (SImode); -+ low5bit = gen_reg_rtx (SImode); -+ low5bit_inv = gen_reg_rtx (SImode); -+ minus32sa = gen_reg_rtx (SImode); -+ select_reg = gen_reg_rtx (SImode); -+ -+ dst_low_part_g32_tmph = gen_reg_rtx (SImode); -+ dst_low_part_g32_tmpl = gen_reg_rtx (SImode); -+ -+ dst_high_part_l32_tmph = gen_reg_rtx (SImode); -+ dst_high_part_l32_tmpl = gen_reg_rtx (SImode); -+ -+ emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32))); -+ -+ /* if shiftamount < 32 -+ dst_low_part = wext(src, shiftamount) -+ else -+ dst_low_part = ((src_high_part >> (shiftamount & 0x1f)) -+ | (src_low_part << (32 - (shiftamount & 0x1f)))) -+ */ -+ emit_insn (gen_andsi3 (low5bit, shiftamount, gen_int_mode (0x1f, SImode))); -+ emit_insn (gen_subsi3 (low5bit_inv, gen_int_mode (32, SImode), low5bit)); -+ -+ emit_insn (gen_wext (dst_low_part_l32, src, shiftamount)); -+ -+ emit_insn (gen_lshrsi3 (dst_low_part_g32_tmpl, src_high_part, low5bit)); -+ emit_insn (gen_ashlsi3 (dst_low_part_g32_tmph, src_low_part, low5bit_inv)); -+ -+ emit_insn (gen_iorsi3 (dst_low_part_g32, -+ dst_low_part_g32_tmpl, -+ dst_low_part_g32_tmph)); -+ -+ emit_insn (gen_cmovnsi (dst_low_part, select_reg, -+ dst_low_part_l32, dst_low_part_g32)); -+ -+ /* if shiftamount < 32 -+ dst_high_part = ((src_high_part >> shiftamount) -+ | (src_low_part << (32 - shiftamount))) -+ dst_high_part = shiftamount == 0 ? src_high_part : dst_high_part -+ else -+ dst_high_part = wext(src, shiftamount & 0x1f) -+ */ -+ -+ emit_insn (gen_subsi3 (minus32sa, gen_int_mode (32, SImode), shiftamount)); -+ -+ emit_insn (gen_lshrsi3 (dst_high_part_l32_tmpl, src_high_part, shiftamount)); -+ emit_insn (gen_ashlsi3 (dst_high_part_l32_tmph, src_low_part, minus32sa)); -+ -+ emit_insn (gen_iorsi3 (dst_high_part_l32, -+ dst_high_part_l32_tmpl, -+ dst_high_part_l32_tmph)); -+ -+ emit_insn (gen_cmovzsi (dst_high_part_l32, shiftamount, -+ src_high_part, dst_high_part_l32)); -+ -+ emit_insn (gen_wext (dst_high_part_g32, src, low5bit)); -+ -+ emit_insn (gen_cmovnsi (dst_high_part, select_reg, -+ dst_high_part_l32, dst_high_part_g32)); -+} -+ -+/* Return true if OP contains a symbol reference. */ -+bool -+symbolic_reference_mentioned_p (rtx op) -+{ -+ const char *fmt; -+ int i; -+ -+ if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) -+ return true; -+ -+ fmt = GET_RTX_FORMAT (GET_CODE (op)); -+ for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) -+ { -+ if (fmt[i] == 'E') -+ { -+ int j; -+ -+ for (j = XVECLEN (op, i) - 1; j >= 0; j--) -+ if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) -+ return true; -+ } -+ -+ else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) -+ return true; -+ } -+ -+ return false; -+} -+ -+/* Expand PIC code for @GOTOFF and @GOT. -+ -+ Example for @GOTOFF: -+ -+ la $r0, symbol@GOTOFF -+ -> sethi $ta, hi20(symbol@GOTOFF) -+ ori $ta, $ta, lo12(symbol@GOTOFF) -+ add $r0, $ta, $gp -+ -+ Example for @GOT: -+ -+ la $r0, symbol@GOT -+ -> sethi $ta, hi20(symbol@GOT) -+ ori $ta, $ta, lo12(symbol@GOT) -+ lw $r0, [$ta + $gp] -+*/ -+rtx -+nds32_legitimize_pic_address (rtx x) -+{ -+ rtx addr = x; -+ rtx reg = gen_reg_rtx (Pmode); -+ rtx pat; -+ -+ if (GET_CODE (x) == LABEL_REF -+ || (GET_CODE (x) == SYMBOL_REF -+ && (CONSTANT_POOL_ADDRESS_P (x) -+ || SYMBOL_REF_LOCAL_P (x)))) -+ { -+ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_GOTOFF); -+ addr = gen_rtx_CONST (SImode, addr); -+ emit_insn (gen_sethi (reg, addr)); -+ emit_insn (gen_lo_sum (reg, reg, addr)); -+ x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx); -+ } -+ else if (GET_CODE (x) == SYMBOL_REF) -+ { -+ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_GOT); -+ addr = gen_rtx_CONST (SImode, addr); -+ emit_insn (gen_sethi (reg, addr)); -+ emit_insn (gen_lo_sum (reg, reg, addr)); -+ -+ x = gen_const_mem (SImode, gen_rtx_PLUS (Pmode, pic_offset_table_rtx, -+ reg)); -+ } -+ else if (GET_CODE (x) == CONST) -+ { -+ /* We don't split constant in expand_pic_move because GOTOFF can combine -+ the addend with the symbol. */ -+ addr = XEXP (x, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ -+ rtx op0 = XEXP (addr, 0); -+ rtx op1 = XEXP (addr, 1); -+ -+ if ((GET_CODE (op0) == LABEL_REF -+ || (GET_CODE (op0) == SYMBOL_REF -+ && (CONSTANT_POOL_ADDRESS_P (op0) -+ || SYMBOL_REF_LOCAL_P (op0)))) -+ && GET_CODE (op1) == CONST_INT) -+ { -+ pat = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), UNSPEC_GOTOFF); -+ pat = gen_rtx_PLUS (Pmode, pat, op1); -+ pat = gen_rtx_CONST (Pmode, pat); -+ emit_insn (gen_sethi (reg, pat)); -+ emit_insn (gen_lo_sum (reg, reg, pat)); -+ x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx); -+ } -+ else if (GET_CODE (op0) == SYMBOL_REF -+ && GET_CODE (op1) == CONST_INT) -+ { -+ /* This is a constant offset from a @GOT symbol reference. */ -+ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, op0), UNSPEC_GOT); -+ addr = gen_rtx_CONST (SImode, addr); -+ emit_insn (gen_sethi (reg, addr)); -+ emit_insn (gen_lo_sum (reg, reg, addr)); -+ addr = gen_const_mem (SImode, gen_rtx_PLUS (Pmode, -+ pic_offset_table_rtx, -+ reg)); -+ emit_move_insn (reg, addr); -+ if (satisfies_constraint_Is15 (op1)) -+ x = gen_rtx_PLUS (Pmode, reg, op1); -+ else -+ { -+ rtx tmp_reg = gen_reg_rtx (SImode); -+ emit_insn (gen_movsi (tmp_reg, op1)); -+ x = gen_rtx_PLUS (Pmode, reg, tmp_reg); -+ } -+ } -+ else -+ { -+ /* Don't handle this pattern. */ -+ debug_rtx (x); -+ gcc_unreachable (); -+ } -+ } -+ return x; -+} -+ -+void -+nds32_expand_pic_move (rtx *operands) -+{ -+ rtx src; -+ -+ src = nds32_legitimize_pic_address (operands[1]); -+ emit_move_insn (operands[0], src); -+} -+ -+/* Expand ICT symbol. -+ Example for @ICT and ICT model=large: -+ -+ la $r0, symbol@ICT -+ -> sethi $rt, hi20(symbol@ICT) -+ lwi $r0, [$rt + lo12(symbol@ICT)] -+ -+*/ -+rtx -+nds32_legitimize_ict_address (rtx x) -+{ -+ rtx symbol = x; -+ rtx addr = x; -+ rtx reg = gen_reg_rtx (Pmode); -+ gcc_assert (GET_CODE (x) == SYMBOL_REF -+ && nds32_indirect_call_referenced_p (x)); -+ -+ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, symbol), UNSPEC_ICT); -+ addr = gen_rtx_CONST (SImode, addr); -+ emit_insn (gen_sethi (reg, addr)); -+ -+ x = gen_const_mem (SImode, gen_rtx_LO_SUM (Pmode, reg, addr)); -+ -+ return x; -+} -+ -+void -+nds32_expand_ict_move (rtx *operands) -+{ -+ rtx src = operands[1]; -+ -+ src = nds32_legitimize_ict_address (src); -+ -+ emit_move_insn (operands[0], src); -+} -+ -+/* Return true X is a indirect call symbol. */ -+bool -+nds32_indirect_call_referenced_p (rtx x) -+{ -+ if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_ICT) -+ x = XVECEXP (x, 0, 0); -+ -+ if (GET_CODE (x) == SYMBOL_REF) -+ { -+ tree decl = SYMBOL_REF_DECL (x); -+ -+ return decl -+ && (lookup_attribute("indirect_call", -+ DECL_ATTRIBUTES(decl)) -+ != NULL); -+ } -+ -+ return false; -+} -+ - /* Return true X is need use long call. */ - bool - nds32_long_call_p (rtx symbol) - { -- return TARGET_CMODEL_LARGE; -+ if (nds32_indirect_call_referenced_p (symbol)) -+ return TARGET_ICT_MODEL_LARGE; -+ else -+ return TARGET_CMODEL_LARGE; -+} -+ -+/* Return true if X contains a thread-local symbol. */ -+bool -+nds32_tls_referenced_p (rtx x) -+{ -+ if (!targetm.have_tls) -+ return false; -+ -+ if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) -+ x = XEXP (XEXP (x, 0), 0); -+ -+ if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x)) -+ return true; -+ -+ return false; -+} -+ -+/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute -+ this (thread-local) address. */ -+rtx -+nds32_legitimize_tls_address (rtx x) -+{ -+ rtx tmp_reg; -+ rtx tp_reg = gen_rtx_REG (Pmode, TP_REGNUM); -+ rtx pat, insns, reg0; -+ -+ if (GET_CODE (x) == SYMBOL_REF) -+ switch (SYMBOL_REF_TLS_MODEL (x)) -+ { -+ case TLS_MODEL_GLOBAL_DYNAMIC: -+ case TLS_MODEL_LOCAL_DYNAMIC: -+ /* Emit UNSPEC_TLS_DESC rather than expand rtl directly because spill -+ may destroy the define-use chain anylysis to insert relax_hint. */ -+ if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC) -+ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSGD); -+ else -+ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSLD); -+ -+ pat = gen_rtx_CONST (SImode, pat); -+ reg0 = gen_rtx_REG (Pmode, 0); -+ /* If we can confirm all clobber reigsters, it doesn't have to use call -+ instruction. */ -+ insns = emit_call_insn (gen_tls_desc (pat, GEN_INT (0))); -+ use_reg (&CALL_INSN_FUNCTION_USAGE (insns), pic_offset_table_rtx); -+ RTL_CONST_CALL_P (insns) = 1; -+ tmp_reg = gen_reg_rtx (SImode); -+ emit_move_insn (tmp_reg, reg0); -+ x = tmp_reg; -+ break; -+ -+ case TLS_MODEL_INITIAL_EXEC: -+ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSIE); -+ tmp_reg = gen_reg_rtx (SImode); -+ pat = gen_rtx_CONST (SImode, pat); -+ emit_insn (gen_tls_ie (tmp_reg, pat, GEN_INT (0))); -+ if (flag_pic) -+ emit_use (pic_offset_table_rtx); -+ x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg); -+ break; -+ -+ case TLS_MODEL_LOCAL_EXEC: -+ /* Expand symbol_ref@TPOFF': -+ sethi $ta, hi20(symbol_ref@TPOFF) -+ ori $ta, $ta, lo12(symbol_ref@TPOFF) -+ add $r0, $ta, $tp */ -+ tmp_reg = gen_reg_rtx (SImode); -+ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSLE); -+ pat = gen_rtx_CONST (SImode, pat); -+ emit_insn (gen_sethi (tmp_reg, pat)); -+ emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat)); -+ x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ else if (GET_CODE (x) == CONST) -+ { -+ rtx base, addend; -+ split_const (x, &base, &addend); -+ -+ if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_EXEC) -+ { -+ /* Expand symbol_ref@TPOFF': -+ sethi $ta, hi20(symbol_ref@TPOFF + addend) -+ ori $ta, $ta, lo12(symbol_ref@TPOFF + addend) -+ add $r0, $ta, $tp */ -+ tmp_reg = gen_reg_rtx (SImode); -+ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, base), UNSPEC_TLSLE); -+ pat = gen_rtx_PLUS (SImode, pat, addend); -+ pat = gen_rtx_CONST (SImode, pat); -+ emit_insn (gen_sethi (tmp_reg, pat)); -+ emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat)); -+ x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg); -+ } -+ } -+ -+ return x; -+} -+ -+void -+nds32_expand_tls_move (rtx *operands) -+{ -+ rtx src = operands[1]; -+ rtx base, addend; -+ -+ if (CONSTANT_P (src)) -+ split_const (src, &base, &addend); -+ -+ if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_EXEC) -+ src = nds32_legitimize_tls_address (src); -+ else -+ { -+ src = nds32_legitimize_tls_address (base); -+ if (addend != const0_rtx) -+ { -+ src = gen_rtx_PLUS (SImode, src, addend); -+ src = force_operand (src, operands[0]); -+ } -+ } -+ -+ emit_move_insn (operands[0], src); - } - - void -@@ -2976,3 +3812,105 @@ - emit_move_insn (target, gen_rtx_fmt_ee (AND, mode, source, temp)); - } - } -+ -+/* Auxiliary functions for lwm/smw. */ -+bool -+nds32_valid_smw_lwm_base_p (rtx op) -+{ -+ rtx base_addr; -+ -+ if (!MEM_P (op)) -+ return false; -+ -+ base_addr = XEXP (op, 0); -+ -+ if (REG_P (base_addr)) -+ return true; -+ else -+ { -+ if (GET_CODE (base_addr) == POST_INC -+ && REG_P (XEXP (base_addr, 0))) -+ return true; -+ } -+ -+ return false; -+} -+ -+/* Auxiliary functions for manipulation DI mode. */ -+rtx nds32_di_high_part_subreg(rtx reg) -+{ -+ unsigned high_part_offset = subreg_highpart_offset (SImode, DImode); -+ -+ return simplify_gen_subreg ( -+ SImode, reg, -+ DImode, high_part_offset); -+} -+ -+rtx nds32_di_low_part_subreg(rtx reg) -+{ -+ unsigned low_part_offset = subreg_lowpart_offset (SImode, DImode); -+ -+ return simplify_gen_subreg ( -+ SImode, reg, -+ DImode, low_part_offset); -+} -+ -+/* ------------------------------------------------------------------------ */ -+ -+/* Auxiliary function for output TLS patterns. */ -+ -+const char * -+nds32_output_tls_desc (rtx *operands) -+{ -+ char pattern[1000]; -+ -+ if (TARGET_RELAX_HINT) -+ snprintf (pattern, sizeof (pattern), -+ ".relax_hint %%1\n\tsethi $r0, hi20(%%0)\n\t" -+ ".relax_hint %%1\n\tori $r0, $r0, lo12(%%0)\n\t" -+ ".relax_hint %%1\n\tlw $r15, [$r0 + $gp]\n\t" -+ ".relax_hint %%1\n\tadd $r0, $r0, $gp\n\t" -+ ".relax_hint %%1\n\tjral $r15"); -+ else -+ snprintf (pattern, sizeof (pattern), -+ "sethi $r0, hi20(%%0)\n\t" -+ "ori $r0, $r0, lo12(%%0)\n\t" -+ "lw $r15, [$r0 + $gp]\n\t" -+ "add $r0, $r0, $gp\n\t" -+ "jral $r15"); -+ output_asm_insn (pattern, operands); -+ return ""; -+} -+ -+const char * -+nds32_output_tls_ie (rtx *operands) -+{ -+ char pattern[1000]; -+ -+ if (flag_pic) -+ { -+ if (TARGET_RELAX_HINT) -+ snprintf (pattern, sizeof (pattern), -+ ".relax_hint %%2\n\tsethi %%0, hi20(%%1)\n\t" -+ ".relax_hint %%2\n\tori %%0, %%0, lo12(%%1)\n\t" -+ ".relax_hint %%2\n\tlw %%0, [%%0 + $gp]"); -+ else -+ snprintf (pattern, sizeof (pattern), -+ "sethi %%0, hi20(%%1)\n\t" -+ "ori %%0, %%0, lo12(%%1)\n\t" -+ "lw %%0, [%%0 + $gp]"); -+ } -+ else -+ { -+ if (TARGET_RELAX_HINT) -+ snprintf (pattern, sizeof (pattern), -+ ".relax_hint %%2\n\tsethi %%0, hi20(%%1)\n\t" -+ ".relax_hint %%2\n\tlwi %%0, [%%0 + lo12(%%1)]"); -+ else -+ snprintf (pattern, sizeof (pattern), -+ "sethi %%0, hi20(%%1)\n\t" -+ "lwi %%0, [%%0 + lo12(%%1)]"); -+ } -+ output_asm_insn (pattern, operands); -+ return ""; -+} -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-memory-manipulation.c gcc-8.2.0/gcc/config/nds32/nds32-memory-manipulation.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-memory-manipulation.c 2018-03-11 09:24:33.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-memory-manipulation.c 2019-01-25 15:38:32.829242659 +0100 -@@ -257,8 +257,124 @@ - nds32_expand_movmemsi_loop_known_size (rtx dstmem, rtx srcmem, - rtx size, rtx alignment) - { -- return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem, -- size, alignment); -+ rtx dst_base_reg, src_base_reg; -+ rtx dst_itr, src_itr; -+ rtx dstmem_m, srcmem_m, dst_itr_m, src_itr_m; -+ rtx dst_end; -+ rtx double_word_mode_loop, byte_mode_loop; -+ rtx tmp; -+ int start_regno; -+ bool align_to_4_bytes = (INTVAL (alignment) & 3) == 0; -+ unsigned HOST_WIDE_INT total_bytes = UINTVAL (size); -+ -+ if (TARGET_ISA_V3M && !align_to_4_bytes) -+ return 0; -+ -+ if (TARGET_REDUCED_REGS) -+ start_regno = 2; -+ else -+ start_regno = 16; -+ -+ dst_itr = gen_reg_rtx (Pmode); -+ src_itr = gen_reg_rtx (Pmode); -+ dst_end = gen_reg_rtx (Pmode); -+ tmp = gen_reg_rtx (QImode); -+ -+ double_word_mode_loop = gen_label_rtx (); -+ byte_mode_loop = gen_label_rtx (); -+ -+ dst_base_reg = copy_to_mode_reg (Pmode, XEXP (dstmem, 0)); -+ src_base_reg = copy_to_mode_reg (Pmode, XEXP (srcmem, 0)); -+ -+ if (total_bytes < 8) -+ { -+ /* Emit total_bytes less than 8 loop version of movmem. -+ add $dst_end, $dst, $size -+ move $dst_itr, $dst -+ .Lbyte_mode_loop: -+ lbi.bi $tmp, [$src_itr], #1 -+ sbi.bi $tmp, [$dst_itr], #1 -+ ! Not readch upper bound. Loop. -+ bne $dst_itr, $dst_end, .Lbyte_mode_loop */ -+ -+ /* add $dst_end, $dst, $size */ -+ dst_end = expand_binop (Pmode, add_optab, dst_base_reg, size, -+ NULL_RTX, 0, OPTAB_WIDEN); -+ /* move $dst_itr, $dst -+ move $src_itr, $src */ -+ emit_move_insn (dst_itr, dst_base_reg); -+ emit_move_insn (src_itr, src_base_reg); -+ -+ /* .Lbyte_mode_loop: */ -+ emit_label (byte_mode_loop); -+ -+ /* lbi.bi $tmp, [$src_itr], #1 */ -+ nds32_emit_post_inc_load_store (tmp, src_itr, QImode, true); -+ -+ /* sbi.bi $tmp, [$dst_itr], #1 */ -+ nds32_emit_post_inc_load_store (tmp, dst_itr, QImode, false); -+ /* ! Not readch upper bound. Loop. -+ bne $dst_itr, $dst_end, .Lbyte_mode_loop */ -+ emit_cmp_and_jump_insns (dst_itr, dst_end, NE, NULL, -+ SImode, 1, byte_mode_loop); -+ return true; -+ } -+ else if (total_bytes % 8 == 0) -+ { -+ /* Emit multiple of 8 loop version of movmem. -+ -+ add $dst_end, $dst, $size -+ move $dst_itr, $dst -+ move $src_itr, $src -+ -+ .Ldouble_word_mode_loop: -+ lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr -+ smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr -+ ! move will delete after register allocation -+ move $src_itr, $src_itr' -+ move $dst_itr, $dst_itr' -+ ! Not readch upper bound. Loop. -+ bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop */ -+ -+ /* add $dst_end, $dst, $size */ -+ dst_end = expand_binop (Pmode, add_optab, dst_base_reg, size, -+ NULL_RTX, 0, OPTAB_WIDEN); -+ -+ /* move $dst_itr, $dst -+ move $src_itr, $src */ -+ emit_move_insn (dst_itr, dst_base_reg); -+ emit_move_insn (src_itr, src_base_reg); -+ -+ /* .Ldouble_word_mode_loop: */ -+ emit_label (double_word_mode_loop); -+ /* lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr -+ smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr */ -+ src_itr_m = src_itr; -+ dst_itr_m = dst_itr; -+ srcmem_m = srcmem; -+ dstmem_m = dstmem; -+ nds32_emit_mem_move_block (start_regno, 2, -+ &dst_itr_m, &dstmem_m, -+ &src_itr_m, &srcmem_m, -+ true); -+ /* move $src_itr, $src_itr' -+ move $dst_itr, $dst_itr' */ -+ emit_move_insn (dst_itr, dst_itr_m); -+ emit_move_insn (src_itr, src_itr_m); -+ -+ /* ! Not readch upper bound. Loop. -+ bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop */ -+ emit_cmp_and_jump_insns (dst_end, dst_itr, NE, NULL, -+ Pmode, 1, double_word_mode_loop); -+ } -+ else -+ { -+ /* Handle size greater than 8, and not a multiple of 8. */ -+ return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem, -+ size, alignment); -+ } -+ -+ return true; - } - - static bool -@@ -433,10 +549,8 @@ - /* Auxiliary function for expand setmem pattern. */ - - static rtx --nds32_gen_dup_4_byte_to_word_value (rtx value) -+nds32_gen_dup_4_byte_to_word_value_aux (rtx value, rtx value4word) - { -- rtx value4word = gen_reg_rtx (SImode); -- - gcc_assert (GET_MODE (value) == QImode || CONST_INT_P (value)); - - if (CONST_INT_P (value)) -@@ -449,36 +563,74 @@ - } - else - { -- /* ! prepare word -- andi $tmp1, $value, 0xff ! $tmp1 <- 0x000000ab -- slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00 -- or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab -- slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000 -- or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */ -- -- rtx tmp1, tmp2, tmp3, tmp4, final_value; -- tmp1 = expand_binop (SImode, and_optab, value, -- gen_int_mode (0xff, SImode), -- NULL_RTX, 0, OPTAB_WIDEN); -- tmp2 = expand_binop (SImode, ashl_optab, tmp1, -- gen_int_mode (8, SImode), -- NULL_RTX, 0, OPTAB_WIDEN); -- tmp3 = expand_binop (SImode, ior_optab, tmp1, tmp2, -- NULL_RTX, 0, OPTAB_WIDEN); -- tmp4 = expand_binop (SImode, ashl_optab, tmp3, -- gen_int_mode (16, SImode), -- NULL_RTX, 0, OPTAB_WIDEN); -- -- final_value = expand_binop (SImode, ior_optab, tmp3, tmp4, -- NULL_RTX, 0, OPTAB_WIDEN); -- emit_move_insn (value4word, final_value); -+ if (NDS32_EXT_DSP_P ()) -+ { -+ /* ! prepare word -+ insb $tmp, $value, 1 ! $tmp <- 0x0000abab -+ pkbb16 $tmp6, $tmp2, $tmp2 ! $value4word <- 0xabababab */ -+ rtx tmp = gen_reg_rtx (SImode); -+ -+ convert_move (tmp, value, true); -+ -+ emit_insn ( -+ gen_insvsi_internal (tmp, gen_int_mode (0x8, SImode), tmp)); -+ -+ emit_insn (gen_pkbbsi_1 (value4word, tmp, tmp)); -+ } -+ else -+ { -+ /* ! prepare word -+ andi $tmp1, $value, 0xff ! $tmp1 <- 0x000000ab -+ slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00 -+ or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab -+ slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000 -+ or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */ -+ -+ rtx tmp1, tmp2, tmp3, tmp4; -+ tmp1 = expand_binop (SImode, and_optab, value, -+ gen_int_mode (0xff, SImode), -+ NULL_RTX, 0, OPTAB_WIDEN); -+ tmp2 = expand_binop (SImode, ashl_optab, tmp1, -+ gen_int_mode (8, SImode), -+ NULL_RTX, 0, OPTAB_WIDEN); -+ tmp3 = expand_binop (SImode, ior_optab, tmp1, tmp2, -+ NULL_RTX, 0, OPTAB_WIDEN); -+ tmp4 = expand_binop (SImode, ashl_optab, tmp3, -+ gen_int_mode (16, SImode), -+ NULL_RTX, 0, OPTAB_WIDEN); -+ -+ emit_insn (gen_iorsi3 (value4word, tmp3, tmp4)); -+ } - } - - return value4word; - } - - static rtx --emit_setmem_word_loop (rtx itr, rtx size, rtx value) -+nds32_gen_dup_4_byte_to_word_value (rtx value) -+{ -+ rtx value4word = gen_reg_rtx (SImode); -+ nds32_gen_dup_4_byte_to_word_value_aux (value, value4word); -+ -+ return value4word; -+} -+ -+static rtx -+nds32_gen_dup_8_byte_to_double_word_value (rtx value) -+{ -+ rtx value4doubleword = gen_reg_rtx (DImode); -+ -+ nds32_gen_dup_4_byte_to_word_value_aux ( -+ value, nds32_di_low_part_subreg(value4doubleword)); -+ -+ emit_move_insn (nds32_di_high_part_subreg(value4doubleword), -+ nds32_di_low_part_subreg(value4doubleword)); -+ return value4doubleword; -+} -+ -+ -+static rtx -+emit_setmem_doubleword_loop (rtx itr, rtx size, rtx value) - { - rtx word_mode_label = gen_label_rtx (); - rtx word_mode_end_label = gen_label_rtx (); -@@ -487,9 +639,9 @@ - rtx word_mode_end = gen_reg_rtx (SImode); - rtx size_for_word = gen_reg_rtx (SImode); - -- /* and $size_for_word, $size, #~3 */ -+ /* and $size_for_word, $size, #~0x7 */ - size_for_word = expand_binop (SImode, and_optab, size, -- gen_int_mode (~3, SImode), -+ gen_int_mode (~0x7, SImode), - NULL_RTX, 0, OPTAB_WIDEN); - - emit_move_insn (byte_mode_size, size); -@@ -501,8 +653,8 @@ - word_mode_end = expand_binop (Pmode, add_optab, itr, size_for_word, - NULL_RTX, 0, OPTAB_WIDEN); - -- /* andi $byte_mode_size, $size, 3 */ -- byte_mode_size_tmp = expand_binop (SImode, and_optab, size, GEN_INT (3), -+ /* andi $byte_mode_size, $size, 0x7 */ -+ byte_mode_size_tmp = expand_binop (SImode, and_optab, size, GEN_INT (0x7), - NULL_RTX, 0, OPTAB_WIDEN); - - emit_move_insn (byte_mode_size, byte_mode_size_tmp); -@@ -512,9 +664,9 @@ - /* ! word-mode set loop - smw.bim $value4word, [$dst_itr], $value4word, 0 - bne $word_mode_end, $dst_itr, .Lword_mode */ -- emit_insn (gen_unaligned_store_update_base_w (itr, -- itr, -- value)); -+ emit_insn (gen_unaligned_store_update_base_dw (itr, -+ itr, -+ value)); - emit_cmp_and_jump_insns (word_mode_end, itr, NE, NULL, - Pmode, 1, word_mode_label); - -@@ -566,7 +718,7 @@ - static bool - nds32_expand_setmem_loop (rtx dstmem, rtx size, rtx value) - { -- rtx value4word; -+ rtx value4doubleword; - rtx value4byte; - rtx dst; - rtx byte_mode_size; -@@ -609,7 +761,7 @@ - or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab - slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000 - or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */ -- value4word = nds32_gen_dup_4_byte_to_word_value (value); -+ value4doubleword = nds32_gen_dup_8_byte_to_double_word_value (value); - - /* and $size_for_word, $size, #-4 - beqz $size_for_word, .Lword_mode_end -@@ -622,7 +774,7 @@ - smw.bim $value4word, [$dst], $value4word, 0 - bne $word_mode_end, $dst, .Lword_mode - .Lword_mode_end: */ -- byte_mode_size = emit_setmem_word_loop (dst, size, value4word); -+ byte_mode_size = emit_setmem_doubleword_loop (dst, size, value4doubleword); - - /* beqz $byte_mode_size, .Lend - add $byte_mode_end, $dst, $byte_mode_size -@@ -633,8 +785,8 @@ - bne $byte_mode_end, $dst, .Lbyte_mode - .Lend: */ - -- value4byte = simplify_gen_subreg (QImode, value4word, SImode, -- subreg_lowpart_offset (QImode, SImode)); -+ value4byte = simplify_gen_subreg (QImode, value4doubleword, DImode, -+ subreg_lowpart_offset (QImode, DImode)); - - emit_setmem_byte_loop (dst, byte_mode_size, value4byte, false); - -@@ -651,14 +803,15 @@ - rtx byte_loop_size = gen_reg_rtx (SImode); - rtx remain_size = gen_reg_rtx (SImode); - rtx new_base_reg; -- rtx value4byte, value4word; -+ rtx value4byte, value4doubleword; - rtx byte_mode_size; - rtx last_byte_loop_label = gen_label_rtx (); - - size = force_reg (SImode, size); - -- value4word = nds32_gen_dup_4_byte_to_word_value (value); -- value4byte = simplify_gen_subreg (QImode, value4word, SImode, 0); -+ value4doubleword = nds32_gen_dup_8_byte_to_double_word_value (value); -+ value4byte = simplify_gen_subreg (QImode, value4doubleword, DImode, -+ subreg_lowpart_offset (QImode, DImode)); - - emit_move_insn (byte_loop_size, size); - emit_move_insn (byte_loop_base, base_reg); -@@ -686,9 +839,9 @@ - emit_insn (gen_subsi3 (remain_size, size, need_align_bytes)); - - /* Set memory word by word. */ -- byte_mode_size = emit_setmem_word_loop (new_base_reg, -- remain_size, -- value4word); -+ byte_mode_size = emit_setmem_doubleword_loop (new_base_reg, -+ remain_size, -+ value4doubleword); - - emit_move_insn (byte_loop_base, new_base_reg); - emit_move_insn (byte_loop_size, byte_mode_size); -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-multiple.md gcc-8.2.0/gcc/config/nds32/nds32-multiple.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-multiple.md 2018-03-11 09:24:33.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-multiple.md 2019-01-25 15:38:32.829242659 +0100 -@@ -2854,6 +2854,25 @@ - (set_attr "length" "4")] - ) - -+(define_expand "unaligned_store_update_base_dw" -+ [(parallel [(set (match_operand:SI 0 "register_operand" "=r") -+ (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 8))) -+ (set (mem:DI (match_dup 1)) -+ (unspec:DI [(match_operand:DI 2 "register_operand" "r")] UNSPEC_UASTORE_DW))])] -+ "" -+{ -+ /* DO NOT emit unaligned_store_w_m immediately since web pass don't -+ recognize post_inc, try it again after GCC 5.0. -+ REF: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156 */ -+ emit_insn (gen_unaligned_store_dw (gen_rtx_MEM (DImode, operands[1]), operands[2])); -+ emit_insn (gen_addsi3 (operands[0], operands[1], gen_int_mode (8, Pmode))); -+ DONE; -+} -+ [(set_attr "type" "store_multiple") -+ (set_attr "combo" "2") -+ (set_attr "length" "4")] -+) -+ - (define_insn "*stmsi25" - [(match_parallel 0 "nds32_store_multiple_operation" - [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-n10.md gcc-8.2.0/gcc/config/nds32/nds32-n10.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-n10.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-n10.md 2019-01-25 15:38:32.829242659 +0100 -@@ -0,0 +1,439 @@ -+;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -+;; Copyright (C) 2012-2018 Free Software Foundation, Inc. -+;; Contributed by Andes Technology Corporation. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published -+;; by the Free Software Foundation; either version 3, or (at your -+;; option) any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but WITHOUT -+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+;; License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+ -+;; ------------------------------------------------------------------------ -+;; Define N10 pipeline settings. -+;; ------------------------------------------------------------------------ -+ -+(define_automaton "nds32_n10_machine") -+ -+;; ------------------------------------------------------------------------ -+;; Pipeline Stages -+;; ------------------------------------------------------------------------ -+;; IF - Instruction Fetch -+;; II - Instruction Issue / Instruction Decode -+;; EX - Instruction Execution -+;; MM - Memory Execution -+;; WB - Instruction Retire / Result Write-Back -+ -+(define_cpu_unit "n10_ii" "nds32_n10_machine") -+(define_cpu_unit "n10_ex" "nds32_n10_machine") -+(define_cpu_unit "n10_mm" "nds32_n10_machine") -+(define_cpu_unit "n10_wb" "nds32_n10_machine") -+(define_cpu_unit "n10f_iq" "nds32_n10_machine") -+(define_cpu_unit "n10f_rf" "nds32_n10_machine") -+(define_cpu_unit "n10f_e1" "nds32_n10_machine") -+(define_cpu_unit "n10f_e2" "nds32_n10_machine") -+(define_cpu_unit "n10f_e3" "nds32_n10_machine") -+(define_cpu_unit "n10f_e4" "nds32_n10_machine") -+ -+(define_insn_reservation "nds_n10_unknown" 1 -+ (and (eq_attr "type" "unknown") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_misc" 1 -+ (and (eq_attr "type" "misc") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_mmu" 1 -+ (and (eq_attr "type" "mmu") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_alu" 1 -+ (and (eq_attr "type" "alu") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_alu_shift" 1 -+ (and (eq_attr "type" "alu_shift") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_pbsad" 1 -+ (and (eq_attr "type" "pbsad") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex*3, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_pbsada" 1 -+ (and (eq_attr "type" "pbsada") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex*3, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_load" 1 -+ (and (match_test "nds32::load_single_p (insn)") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_store" 1 -+ (and (match_test "nds32::store_single_p (insn)") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_1" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "1"))) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_2" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (ior (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "2")) -+ (match_test "nds32::load_double_p (insn)"))) -+ "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_3" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "3"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_4" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "4"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ii+n10_ex+n10_mm+n10_wb, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_5" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "5"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*2, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_6" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "6"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*3, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_7" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "7"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*4, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_load_multiple_N" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "load_multiple") -+ (match_test "get_attr_combo (insn) >= 8"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*5, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_1" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "1"))) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_2" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (ior (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "2")) -+ (match_test "nds32::store_double_p (insn)"))) -+ "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_3" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "3"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_4" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "4"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ii+n10_ex+n10_mm+n10_wb, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_5" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "5"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*2, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_6" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "6"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*3, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_7" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "7"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*4, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_store_multiple_N" 1 -+ (and (eq_attr "pipeline_model" "n10") -+ (and (eq_attr "type" "store_multiple") -+ (match_test "get_attr_combo (insn) >= 8"))) -+ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*5, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") -+ -+(define_insn_reservation "nds_n10_mul" 1 -+ (and (eq_attr "type" "mul") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_mac" 1 -+ (and (eq_attr "type" "mac") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_div" 1 -+ (and (eq_attr "type" "div") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex*34, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_branch" 1 -+ (and (eq_attr "type" "branch") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_alu" 1 -+ (and (eq_attr "type" "dalu") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_alu64" 1 -+ (and (eq_attr "type" "dalu64") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_alu_round" 1 -+ (and (eq_attr "type" "daluround") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_cmp" 1 -+ (and (eq_attr "type" "dcmp") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_clip" 1 -+ (and (eq_attr "type" "dclip") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_mul" 1 -+ (and (eq_attr "type" "dmul") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_mac" 1 -+ (and (eq_attr "type" "dmac") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_insb" 1 -+ (and (eq_attr "type" "dinsb") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_pack" 1 -+ (and (eq_attr "type" "dpack") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_bpick" 1 -+ (and (eq_attr "type" "dbpick") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_dsp_wext" 1 -+ (and (eq_attr "type" "dwext") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ex, n10_mm, n10_wb") -+ -+(define_insn_reservation "nds_n10_fpu_alu" 4 -+ (and (eq_attr "type" "falu") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_muls" 4 -+ (and (eq_attr "type" "fmuls") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_muld" 4 -+ (and (eq_attr "type" "fmuld") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*2, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_macs" 4 -+ (and (eq_attr "type" "fmacs") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*3, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_macd" 4 -+ (and (eq_attr "type" "fmacd") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*4, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_divs" 4 -+ (and (ior (eq_attr "type" "fdivs") -+ (eq_attr "type" "fsqrts")) -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*14, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_divd" 4 -+ (and (ior (eq_attr "type" "fdivd") -+ (eq_attr "type" "fsqrtd")) -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*28, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_fast_alu" 2 -+ (and (ior (eq_attr "type" "fcmp") -+ (ior (eq_attr "type" "fabs") -+ (ior (eq_attr "type" "fcpy") -+ (eq_attr "type" "fcmov")))) -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_fmtsr" 4 -+ (and (eq_attr "type" "fmtsr") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_fmtdr" 4 -+ (and (eq_attr "type" "fmtdr") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ii+n10f_iq, n10f_iq+n10f_rf, n10f_rf+n10f_e1, n10f_e1+n10f_e2, n10f_e2+n10f_e3, n10f_e3+n10f_e4, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_fmfsr" 2 -+ (and (eq_attr "type" "fmfsr") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_fmfdr" 2 -+ (and (eq_attr "type" "fmfdr") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10_ii+n10f_iq, n10f_iq+n10f_rf, n10f_rf+n10f_e1, n10f_e1+n10f_e2, n10f_e2+n10f_e3, n10f_e3+n10f_e4, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_load" 3 -+ (and (eq_attr "type" "fload") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") -+ -+(define_insn_reservation "nds_n10_fpu_store" 1 -+ (and (eq_attr "type" "fstore") -+ (eq_attr "pipeline_model" "n10")) -+ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") -+ -+;; ------------------------------------------------------------------------ -+;; Comment Notations and Bypass Rules -+;; ------------------------------------------------------------------------ -+;; Producers (LHS) -+;; LD -+;; Load data from the memory and produce the loaded data. The result is -+;; ready at MM. -+;; LMW(N, M) -+;; There are N micro-operations within an instruction that loads multiple -+;; words. The result produced by the M-th micro-operation is sent to -+;; consumers. The result is ready at MM. -+;; MUL, MAC -+;; Compute data in the multiply-adder and produce the data. The result -+;; is ready at MM. -+;; DIV -+;; Compute data in the divider and produce the data. The result is ready -+;; at MM. -+;; -+;; Consumers (RHS) -+;; ALU, MOVD44, PBSAD, PBSADA_RaRb, MUL, MAC, DIV, MMU -+;; Require operands at EX. -+;; ALU_SHIFT_Rb -+;; An ALU-SHIFT instruction consists of a shift micro-operation followed -+;; by an arithmetic micro-operation. The operand Rb is used by the first -+;; micro-operation, and there are some latencies if data dependency occurs. -+;; MAC_RaRb -+;; A MAC instruction does multiplication at EX and does accumulation at MM, -+;; so the operand Rt is required at MM, and operands Ra and Rb are required -+;; at EX. -+;; ADDR_IN -+;; If an instruction requires an address as its input operand, the address -+;; is required at EX. -+;; ST -+;; A store instruction requires its data at MM. -+;; SMW(N, M) -+;; There are N micro-operations within an instruction that stores multiple -+;; words. Each M-th micro-operation requires its data at MM. -+;; BR -+;; If a branch instruction is conditional, its input data is required at EX. -+ -+;; FPU_ADDR_OUT -> FPU_ADDR_IN -+;; Main pipeline rules don't need this because those default latency is 1. -+(define_bypass 1 -+ "nds_n10_fpu_load, nds_n10_fpu_store" -+ "nds_n10_fpu_load, nds_n10_fpu_store" -+ "nds32_n10_ex_to_ex_p" -+) -+ -+;; LD, MUL, MAC, DIV, DALU64, DMUL, DMAC, DALUROUND, DBPICK, DWEXT -+;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU, -+;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb -+(define_bypass 2 -+ "nds_n10_load, nds_n10_mul, nds_n10_mac, nds_n10_div,\ -+ nds_n10_dsp_alu64, nds_n10_dsp_mul, nds_n10_dsp_mac,\ -+ nds_n10_dsp_alu_round, nds_n10_dsp_bpick, nds_n10_dsp_wext" -+ "nds_n10_alu, nds_n10_alu_shift,\ -+ nds_n10_pbsad, nds_n10_pbsada,\ -+ nds_n10_mul, nds_n10_mac, nds_n10_div,\ -+ nds_n10_branch,\ -+ nds_n10_load, nds_n10_store,\ -+ nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ -+ nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ -+ nds_n10_load_multiple_7, nds_n10_load_multiple_N,\ -+ nds_n10_store_multiple_1, nds_n10_store_multiple_2, nds_n10_store_multiple_3,\ -+ nds_n10_store_multiple_4, nds_n10_store_multiple_5, nds_n10_store_multiple_6,\ -+ nds_n10_store_multiple_7, nds_n10_store_multiple_N,\ -+ nds_n10_mmu,\ -+ nds_n10_dsp_alu, nds_n10_dsp_alu_round,\ -+ nds_n10_dsp_mul, nds_n10_dsp_mac, nds_n10_dsp_pack,\ -+ nds_n10_dsp_insb, nds_n10_dsp_cmp, nds_n10_dsp_clip,\ -+ nds_n10_dsp_wext, nds_n10_dsp_bpick" -+ "nds32_n10_mm_to_ex_p" -+) -+ -+;; LMW(N, N) -+;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU -+;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb -+(define_bypass 2 -+ "nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ -+ nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ -+ nds_n10_load_multiple_7, nds_n10_load_multiple_N" -+ "nds_n10_alu, nds_n10_alu_shift,\ -+ nds_n10_pbsad, nds_n10_pbsada,\ -+ nds_n10_mul, nds_n10_mac, nds_n10_div,\ -+ nds_n10_branch,\ -+ nds_n10_load, nds_n10_store,\ -+ nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ -+ nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ -+ nds_n10_load_multiple_7, nds_n10_load_multiple_N,\ -+ nds_n10_store_multiple_1, nds_n10_store_multiple_2, nds_n10_store_multiple_3,\ -+ nds_n10_store_multiple_4, nds_n10_store_multiple_5, nds_n10_store_multiple_6,\ -+ nds_n10_store_multiple_7, nds_n10_store_multiple_N,\ -+ nds_n10_mmu,\ -+ nds_n10_dsp_alu, nds_n10_dsp_alu_round,\ -+ nds_n10_dsp_mul, nds_n10_dsp_mac, nds_n10_dsp_pack,\ -+ nds_n10_dsp_insb, nds_n10_dsp_cmp, nds_n10_dsp_clip,\ -+ nds_n10_dsp_wext, nds_n10_dsp_bpick" -+ "nds32_n10_last_load_to_ex_p" -+) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-n13.md gcc-8.2.0/gcc/config/nds32/nds32-n13.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-n13.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-n13.md 2019-01-25 15:38:32.829242659 +0100 -@@ -0,0 +1,401 @@ -+;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -+;; Copyright (C) 2012-2018 Free Software Foundation, Inc. -+;; Contributed by Andes Technology Corporation. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published -+;; by the Free Software Foundation; either version 3, or (at your -+;; option) any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but WITHOUT -+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+;; License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+ -+;; ------------------------------------------------------------------------ -+;; Define N13 pipeline settings. -+;; ------------------------------------------------------------------------ -+ -+(define_automaton "nds32_n13_machine") -+ -+;; ------------------------------------------------------------------------ -+;; Pipeline Stages -+;; ------------------------------------------------------------------------ -+;; F1 - Instruction Fetch First -+;; Instruction Tag/Data Arrays -+;; ITLB Address Translation -+;; Branch Target Buffer Prediction -+;; F2 - Instruction Fetch Second -+;; Instruction Cache Hit Detection -+;; Cache Way Selection -+;; Inustruction Alignment -+;; I1 - Instruction Issue First / Instruction Decode -+;; Instruction Cache Replay Triggering -+;; 32/16-Bit Instruction Decode -+;; Return Address Stack Prediction -+;; I2 - Instruction Issue Second / Register File Access -+;; Instruction Issue Logic -+;; Register File Access -+;; E1 - Instruction Execute First / Address Generation / MAC First -+;; Data Access Address generation -+;; Multiply Operation -+;; E2 - Instruction Execute Second / Data Access First / MAC Second / -+;; ALU Execute -+;; Skewed ALU -+;; Branch/Jump/Return Resolution -+;; Data Tag/Data arrays -+;; DTLB address translation -+;; Accumulation Operation -+;; E3 - Instruction Execute Third / Data Access Second -+;; Data Cache Hit Detection -+;; Cache Way Selection -+;; Data Alignment -+;; E4 - Instruction Execute Fourth / Write Back -+;; Interruption Resolution -+;; Instruction Retire -+;; Register File Write Back -+ -+(define_cpu_unit "n13_i1" "nds32_n13_machine") -+(define_cpu_unit "n13_i2" "nds32_n13_machine") -+(define_cpu_unit "n13_e1" "nds32_n13_machine") -+(define_cpu_unit "n13_e2" "nds32_n13_machine") -+(define_cpu_unit "n13_e3" "nds32_n13_machine") -+(define_cpu_unit "n13_e4" "nds32_n13_machine") -+ -+(define_insn_reservation "nds_n13_unknown" 1 -+ (and (eq_attr "type" "unknown") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_misc" 1 -+ (and (eq_attr "type" "misc") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_mmu" 1 -+ (and (eq_attr "type" "mmu") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_alu" 1 -+ (and (eq_attr "type" "alu") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_alu_shift" 1 -+ (and (eq_attr "type" "alu_shift") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_pbsad" 1 -+ (and (eq_attr "type" "pbsad") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2*2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_pbsada" 1 -+ (and (eq_attr "type" "pbsada") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2*3, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_load" 1 -+ (and (match_test "nds32::load_single_p (insn)") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_store" 1 -+ (and (match_test "nds32::store_single_p (insn)") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_1" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "1")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_2" 1 -+ (and (ior (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "2")) -+ (match_test "nds32::load_double_p (insn)")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_3" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "3")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_4" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "4")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_5" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "5")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_6" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "6")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_7" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "7")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_8" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "8")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_load_multiple_12" 1 -+ (and (and (eq_attr "type" "load_multiple") -+ (eq_attr "combo" "12")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_1" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "1")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_2" 1 -+ (and (ior (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "2")) -+ (match_test "nds32::store_double_p (insn)")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_3" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "3")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_4" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "4")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_5" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "5")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_6" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "6")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_7" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "7")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_8" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "8")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+(define_insn_reservation "nds_n13_store_multiple_12" 1 -+ (and (and (eq_attr "type" "store_multiple") -+ (eq_attr "combo" "12")) -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") -+ -+;; The multiplier at E1 takes two cycles. -+(define_insn_reservation "nds_n13_mul" 1 -+ (and (eq_attr "type" "mul") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_mac" 1 -+ (and (eq_attr "type" "mac") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4") -+ -+;; The cycles consumed at E2 are 32 - CLZ(abs(Ra)) + 2, -+;; so the worst case is 34. -+(define_insn_reservation "nds_n13_div" 1 -+ (and (eq_attr "type" "div") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2*34, n13_e3, n13_e4") -+ -+(define_insn_reservation "nds_n13_branch" 1 -+ (and (eq_attr "type" "branch") -+ (eq_attr "pipeline_model" "n13")) -+ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") -+ -+;; ------------------------------------------------------------------------ -+;; Comment Notations and Bypass Rules -+;; ------------------------------------------------------------------------ -+;; Producers (LHS) -+;; LD -+;; Load data from the memory and produce the loaded data. The result is -+;; ready at E3. -+;; LMW(N, M) -+;; There are N micro-operations within an instruction that loads multiple -+;; words. The result produced by the M-th micro-operation is sent to -+;; consumers. The result is ready at E3. -+;; ADDR_OUT -+;; Most load/store instructions can produce an address output if updating -+;; the base register is required. The result is ready at E2, which is -+;; produced by ALU. -+;; ALU, ALU_SHIFT, SIMD -+;; Compute data in ALU and produce the data. The result is ready at E2. -+;; MUL, MAC -+;; Compute data in the multiply-adder and produce the data. The result -+;; is ready at E2. -+;; DIV -+;; Compute data in the divider and produce the data. The result is ready -+;; at E2. -+;; BR -+;; Branch-with-link instructions produces a result containing the return -+;; address. The result is ready at E2. -+;; -+;; Consumers (RHS) -+;; ALU -+;; General ALU instructions require operands at E2. -+;; ALU_E1 -+;; Some special ALU instructions, such as BSE, BSP and MOVD44, require -+;; operand at E1. -+;; MUL, DIV, PBSAD, MMU -+;; Operands are required at E1. -+;; PBSADA_Rt, PBSADA_RaRb -+;; Operands Ra and Rb are required at E1, and the operand Rt is required -+;; at E2. -+;; ALU_SHIFT_Rb -+;; An ALU-SHIFT instruction consists of a shift micro-operation followed -+;; by an arithmetic micro-operation. The operand Rb is used by the first -+;; micro-operation, and there are some latencies if data dependency occurs. -+;; MAC_RaRb -+;; A MAC instruction does multiplication at E1 and does accumulation at E2, -+;; so the operand Rt is required at E2, and operands Ra and Rb are required -+;; at E1. -+;; ADDR_IN -+;; If an instruction requires an address as its input operand, the address -+;; is required at E1. -+;; ST -+;; A store instruction requires its data at E2. -+;; SMW(N, M) -+;; There are N micro-operations within an instruction that stores multiple -+;; words. Each M-th micro-operation requires its data at E2. -+;; BR -+;; If a branch instruction is conditional, its input data is required at E2. -+ -+;; LD -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN -+(define_bypass 3 -+ "nds_n13_load" -+ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ -+ nds_n13_mul, nds_n13_mac, nds_n13_div,\ -+ nds_n13_mmu,\ -+ nds_n13_load, nds_n13_store,\ -+ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ -+ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ -+ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ -+ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" -+ "nds32_n13_load_to_e1_p" -+) -+ -+;; LD -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1) -+(define_bypass 2 -+ "nds_n13_load" -+ "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\ -+ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ -+ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ -+ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" -+ "nds32_n13_load_to_e2_p" -+) -+ -+;; LMW(N, N) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN -+(define_bypass 3 -+ "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12" -+ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ -+ nds_n13_mul, nds_n13_mac, nds_n13_div,\ -+ nds_n13_mmu,\ -+ nds_n13_load, nds_n13_store,\ -+ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ -+ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ -+ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ -+ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" -+ "nds32_n13_last_load_to_e1_p") -+ -+;; LMW(N, N) -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1) -+(define_bypass 2 -+ "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12" -+ "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\ -+ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ -+ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ -+ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" -+ "nds32_n13_last_load_to_e2_p" -+) -+ -+;; LMW(N, N - 1) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN -+(define_bypass 2 -+ "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12" -+ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ -+ nds_n13_mul, nds_n13_mac, nds_n13_div,\ -+ nds_n13_mmu,\ -+ nds_n13_load, nds_n13_store,\ -+ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ -+ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ -+ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ -+ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" -+ "nds32_n13_last_two_load_to_e1_p") -+ -+;; ALU, ALU_SHIFT, SIMD, BR, MUL, MAC, DIV, ADDR_OUT -+;; -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN -+(define_bypass 2 -+ "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsad, nds_n13_pbsada, nds_n13_branch,\ -+ nds_n13_mul, nds_n13_mac, nds_n13_div,\ -+ nds_n13_load, nds_n13_store,\ -+ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ -+ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ -+ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ -+ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" -+ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ -+ nds_n13_mul, nds_n13_mac, nds_n13_div,\ -+ nds_n13_mmu,\ -+ nds_n13_load, nds_n13_store,\ -+ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ -+ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ -+ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ -+ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ -+ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ -+ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" -+ "nds32_n13_e2_to_e1_p") -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.opt gcc-8.2.0/gcc/config/nds32/nds32.opt ---- gcc-8.2.0.orig/gcc/config/nds32/nds32.opt 2018-04-22 12:10:00.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32.opt 2019-01-25 15:38:32.833242671 +0100 -@@ -32,6 +32,13 @@ - Target RejectNegative Alias(mlittle-endian) - Generate code in little-endian mode. - -+mfp-as-gp -+Target RejectNegative Alias(mforce-fp-as-gp) -+Force performing fp-as-gp optimization. -+ -+mno-fp-as-gp -+Target RejectNegative Alias(mforbid-fp-as-gp) -+Forbid performing fp-as-gp optimization. - - ; --------------------------------------------------------------- - -@@ -85,11 +92,36 @@ - Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN) - Generate code in little-endian mode. - -+mforce-fp-as-gp -+Target Undocumented Mask(FORCE_FP_AS_GP) -+Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization. -+ -+mforbid-fp-as-gp -+Target Undocumented Mask(FORBID_FP_AS_GP) -+Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'. -+ -+mict-model= -+Target Undocumented RejectNegative Joined Enum(nds32_ict_model_type) Var(nds32_ict_model) Init(ICT_MODEL_SMALL) -+Specify the address generation strategy for ICT call's code model. -+ -+Enum -+Name(nds32_ict_model_type) Type(enum nds32_ict_model_type) -+Known cmodel types (for use with the -mict-model= option): -+ -+EnumValue -+Enum(nds32_ict_model_type) String(small) Value(ICT_MODEL_SMALL) -+ -+EnumValue -+Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE) - - mcmov - Target Report Mask(CMOV) - Generate conditional move instructions. - -+mhw-abs -+Target Report Mask(HW_ABS) -+Generate hardware abs instructions. -+ - mext-perf - Target Report Mask(EXT_PERF) - Generate performance extension instructions. -@@ -102,6 +134,10 @@ - Target Report Mask(EXT_STRING) - Generate string extension instructions. - -+mext-dsp -+Target Report Mask(EXT_DSP) -+Generate DSP extension instructions. -+ - mv3push - Target Report Mask(V3PUSH) - Generate v3 push25/pop25 instructions. -@@ -115,13 +151,17 @@ - Insert relax hint for linker to do relaxation. - - mvh --Target Report Mask(VH) -+Target Report Mask(VH) Condition(!TARGET_LINUX_ABI) - Enable Virtual Hosting support. - - misr-vector-size= - Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE) - Specify the size of each interrupt vector, which must be 4 or 16. - -+misr-secure= -+Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0) -+Specify the security level of c-isr for the whole file. -+ - mcache-block-size= - Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE) - Specify the size of each cache block, which must be a power of 2 between 4 and 512. -@@ -141,6 +181,9 @@ - Enum(nds32_arch_type) String(v3) Value(ARCH_V3) - - EnumValue -+Enum(nds32_arch_type) String(v3j) Value(ARCH_V3J) -+ -+EnumValue - Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M) - - EnumValue -@@ -149,23 +192,6 @@ - EnumValue - Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S) - --mcmodel= --Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_LARGE) --Specify the address generation strategy for code model. -- --Enum --Name(nds32_cmodel_type) Type(enum nds32_cmodel_type) --Known cmodel types (for use with the -mcmodel= option): -- --EnumValue --Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL) -- --EnumValue --Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM) -- --EnumValue --Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE) -- - mcpu= - Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9) - Specify the cpu for pipeline model. -@@ -235,6 +261,99 @@ - Enum(nds32_cpu_type) String(n968a) Value(CPU_N9) - - EnumValue -+Enum(nds32_cpu_type) String(n10) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1033) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1033a) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1033-fpu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1033-spu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1068) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1068a) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1068-fpu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1068a-fpu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1068-spu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1068a-spu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(d10) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(d1088) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10) -+ -+EnumValue -+Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF) -+ -+EnumValue -+Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF) -+ -+EnumValue -+Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF) -+ -+EnumValue -+Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n12) Value(CPU_N12) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1213) Value(CPU_N12) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1233) Value(CPU_N12) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1233-fpu) Value(CPU_N12) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1233-spu) Value(CPU_N12) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n13) Value(CPU_N13) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1337) Value(CPU_N13) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1337-fpu) Value(CPU_N13) -+ -+EnumValue -+Enum(nds32_cpu_type) String(n1337-spu) Value(CPU_N13) -+ -+EnumValue - Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE) - - mconfig-fpu= -@@ -321,6 +440,18 @@ - Target Report Mask(FPU_DOUBLE) - Generate double-precision floating-point instructions. - -+mforce-no-ext-dsp -+Target Undocumented Report Mask(FORCE_NO_EXT_DSP) -+Force disable hardware loop, even use -mext-dsp. -+ -+msched-prolog-epilog -+Target Var(flag_sched_prolog_epilog) Init(0) -+Permit scheduling of a function's prologue and epilogue sequence. -+ -+mret-in-naked-func -+Target Var(flag_ret_in_naked_func) Init(1) -+Generate return instruction in naked function. -+ - malways-save-lp - Target Var(flag_always_save_lp) Init(0) - Always save $lp in the stack. -@@ -328,3 +459,7 @@ - munaligned-access - Target Report Var(flag_unaligned_access) Init(0) - Enable unaligned word and halfword accesses to packed data. -+ -+minline-asm-r15 -+Target Report Var(flag_inline_asm_r15) Init(0) -+Allow use r15 for inline ASM. -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-opts.h gcc-8.2.0/gcc/config/nds32/nds32-opts.h ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-opts.h 2018-04-08 11:21:30.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-opts.h 2019-01-25 15:38:32.833242671 +0100 -@@ -29,6 +29,7 @@ - { - ARCH_V2, - ARCH_V3, -+ ARCH_V3J, - ARCH_V3M, - ARCH_V3F, - ARCH_V3S -@@ -42,6 +43,10 @@ - CPU_N8, - CPU_E8, - CPU_N9, -+ CPU_N10, -+ CPU_GRAYWOLF, -+ CPU_N12, -+ CPU_N13, - CPU_SIMPLE - }; - -@@ -53,6 +58,13 @@ - CMODEL_LARGE - }; - -+/* The code model defines the address generation strategy. */ -+enum nds32_ict_model_type -+{ -+ ICT_MODEL_SMALL, -+ ICT_MODEL_LARGE -+}; -+ - /* Multiply instruction configuration. */ - enum nds32_mul_type - { -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-peephole2.md gcc-8.2.0/gcc/config/nds32/nds32-peephole2.md ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-peephole2.md 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/nds32-peephole2.md 2019-01-25 15:38:32.833242671 +0100 -@@ -22,3 +22,139 @@ - ;; Use define_peephole2 to handle possible target-specific optimization. - - ;; ------------------------------------------------------------------------ -+;; Try to utilize 16-bit instruction by swap operand if possible. -+;; ------------------------------------------------------------------------ -+ -+;; Try to make add as add45. -+(define_peephole2 -+ [(set (match_operand:QIHISI 0 "register_operand" "") -+ (plus:QIHISI (match_operand:QIHISI 1 "register_operand" "") -+ (match_operand:QIHISI 2 "register_operand" "")))] -+ "reload_completed -+ && TARGET_16_BIT -+ && REGNO (operands[0]) == REGNO (operands[2]) -+ && REGNO (operands[0]) != REGNO (operands[1]) -+ && TEST_HARD_REG_BIT (reg_class_contents[MIDDLE_REGS], REGNO (operands[0]))" -+ [(set (match_dup 0) (plus:QIHISI (match_dup 2) (match_dup 1)))]) -+ -+;; Try to make xor/ior/and/mult as xor33/ior33/and33/mult33. -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operator:SI 1 "nds32_have_33_inst_operator" -+ [(match_operand:SI 2 "register_operand" "") -+ (match_operand:SI 3 "register_operand" "")]))] -+ "reload_completed -+ && TARGET_16_BIT -+ && REGNO (operands[0]) == REGNO (operands[3]) -+ && REGNO (operands[0]) != REGNO (operands[2]) -+ && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[0])) -+ && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[2]))" -+ [(set (match_dup 0) (match_op_dup 1 [(match_dup 3) (match_dup 2)]))]) -+ -+(define_peephole -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "register_operand" "")) -+ (set (match_operand:SI 2 "register_operand" "") -+ (match_operand:SI 3 "register_operand" ""))] -+ "TARGET_16_BIT -+ && !TARGET_ISA_V2 -+ && NDS32_IS_GPR_REGNUM (REGNO (operands[0])) -+ && NDS32_IS_GPR_REGNUM (REGNO (operands[1])) -+ && ((REGNO (operands[0]) & 0x1) == 0) -+ && ((REGNO (operands[1]) & 0x1) == 0) -+ && (REGNO (operands[0]) + 1) == REGNO (operands[2]) -+ && (REGNO (operands[1]) + 1) == REGNO (operands[3])" -+ "movd44\t%0, %1" -+ [(set_attr "type" "alu") -+ (set_attr "length" "2")]) -+ -+;; Merge two fcpyss to fcpysd. -+(define_peephole2 -+ [(set (match_operand:SF 0 "float_even_register_operand" "") -+ (match_operand:SF 1 "float_even_register_operand" "")) -+ (set (match_operand:SF 2 "float_odd_register_operand" "") -+ (match_operand:SF 3 "float_odd_register_operand" ""))] -+ "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) -+ && REGNO (operands[0]) == REGNO (operands[2]) - 1 -+ && REGNO (operands[1]) == REGNO (operands[3]) - 1" -+ [(set (match_dup 4) (match_dup 5))] -+ { -+ operands[4] = gen_rtx_REG (DFmode, REGNO (operands[0])); -+ operands[5] = gen_rtx_REG (DFmode, REGNO (operands[1])); -+ }) -+ -+(define_peephole2 -+ [(set (match_operand:SF 0 "float_odd_register_operand" "") -+ (match_operand:SF 1 "float_odd_register_operand" "")) -+ (set (match_operand:SF 2 "float_even_register_operand" "") -+ (match_operand:SF 3 "float_even_register_operand" ""))] -+ "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) -+ && REGNO (operands[2]) == REGNO (operands[0]) - 1 -+ && REGNO (operands[3]) == REGNO (operands[1]) - 1" -+ [(set (match_dup 4) (match_dup 5))] -+ { -+ operands[4] = gen_rtx_REG (DFmode, REGNO (operands[2])); -+ operands[5] = gen_rtx_REG (DFmode, REGNO (operands[3])); -+ }) -+ -+;; ------------------------------------------------------------------------ -+;; GCC will prefer [u]divmodsi3 rather than [u]divsi3 even remainder is -+;; unused, so we use split to drop mod operation for lower register pressure. -+ -+(define_split -+ [(set (match_operand:SI 0 "register_operand") -+ (div:SI (match_operand:SI 1 "register_operand") -+ (match_operand:SI 2 "register_operand"))) -+ (set (match_operand:SI 3 "register_operand") -+ (mod:SI (match_dup 1) (match_dup 2)))] -+ "find_regno_note (insn, REG_UNUSED, REGNO (operands[3])) != NULL -+ && can_create_pseudo_p ()" -+ [(set (match_dup 0) -+ (div:SI (match_dup 1) -+ (match_dup 2)))]) -+ -+(define_split -+ [(set (match_operand:SI 0 "register_operand") -+ (udiv:SI (match_operand:SI 1 "register_operand") -+ (match_operand:SI 2 "register_operand"))) -+ (set (match_operand:SI 3 "register_operand") -+ (umod:SI (match_dup 1) (match_dup 2)))] -+ "find_regno_note (insn, REG_UNUSED, REGNO (operands[3])) != NULL -+ && can_create_pseudo_p ()" -+ [(set (match_dup 0) -+ (udiv:SI (match_dup 1) -+ (match_dup 2)))]) -+ -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand") -+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand")) -+ (sign_extend:DI (match_operand:SI 2 "register_operand"))))] -+ "NDS32_EXT_DSP_P () -+ && peep2_regno_dead_p (1, WORDS_BIG_ENDIAN ? REGNO (operands[0]) + 1 : REGNO (operands[0]))" -+ [(const_int 1)] -+{ -+ rtx highpart = nds32_di_high_part_subreg (operands[0]); -+ emit_insn (gen_smulsi3_highpart (highpart, operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_split -+ [(set (match_operand:DI 0 "nds32_general_register_operand" "") -+ (match_operand:DI 1 "nds32_general_register_operand" ""))] -+ "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) != NULL -+ || find_regno_note (insn, REG_UNUSED, REGNO (operands[0]) + 1) != NULL" -+ [(set (match_dup 0) (match_dup 1))] -+{ -+ rtx dead_note = find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0])); -+ HOST_WIDE_INT offset; -+ if (dead_note == NULL_RTX) -+ offset = 0; -+ else -+ offset = 4; -+ operands[0] = simplify_gen_subreg ( -+ SImode, operands[0], -+ DImode, offset); -+ operands[1] = simplify_gen_subreg ( -+ SImode, operands[1], -+ DImode, offset); -+}) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-pipelines-auxiliary.c gcc-8.2.0/gcc/config/nds32/nds32-pipelines-auxiliary.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-pipelines-auxiliary.c 2018-04-08 11:21:30.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-pipelines-auxiliary.c 2019-01-25 15:38:32.833242671 +0100 -@@ -306,6 +306,19 @@ - return false; - } - -+/* Determine if the latency is occured when the consumer PBSADA_INSN uses the -+ value of DEF_REG in its Rt field. */ -+bool -+pbsada_insn_rt_dep_reg_p (rtx pbsada_insn, rtx def_reg) -+{ -+ rtx pbsada_rt = SET_DEST (PATTERN (pbsada_insn)); -+ -+ if (rtx_equal_p (def_reg, pbsada_rt)) -+ return true; -+ -+ return false; -+} -+ - /* Check if INSN is a movd44 insn consuming DEF_REG. */ - bool - movd44_even_dep_p (rtx_insn *insn, rtx def_reg) -@@ -335,6 +348,103 @@ - return false; - } - -+/* Check if INSN is a wext insn consuming DEF_REG. */ -+bool -+wext_odd_dep_p (rtx insn, rtx def_reg) -+{ -+ rtx shift_rtx = XEXP (SET_SRC (PATTERN (insn)), 0); -+ rtx use_reg = XEXP (shift_rtx, 0); -+ rtx pos_rtx = XEXP (shift_rtx, 1); -+ -+ if (REG_P (pos_rtx) && reg_overlap_p (def_reg, pos_rtx)) -+ return true; -+ -+ if (GET_MODE (def_reg) == DImode) -+ return reg_overlap_p (def_reg, use_reg); -+ -+ gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG); -+ gcc_assert (REG_P (use_reg)); -+ -+ if (REG_P (def_reg)) -+ { -+ if (!TARGET_BIG_ENDIAN) -+ return REGNO (def_reg) == REGNO (use_reg) + 1; -+ else -+ return REGNO (def_reg) == REGNO (use_reg); -+ } -+ -+ if (GET_CODE (def_reg) == SUBREG) -+ { -+ if (!reg_overlap_p (def_reg, use_reg)) -+ return false; -+ -+ if (!TARGET_BIG_ENDIAN) -+ return SUBREG_BYTE (def_reg) == 4; -+ else -+ return SUBREG_BYTE (def_reg) == 0; -+ } -+ -+ return false; -+} -+ -+/* Check if INSN is a bpick insn consuming DEF_REG. */ -+bool -+bpick_ra_rb_dep_p (rtx insn, rtx def_reg) -+{ -+ rtx ior_rtx = SET_SRC (PATTERN (insn)); -+ rtx and1_rtx = XEXP (ior_rtx, 0); -+ rtx and2_rtx = XEXP (ior_rtx, 1); -+ rtx reg1_0 = XEXP (and1_rtx, 0); -+ rtx reg1_1 = XEXP (and1_rtx, 1); -+ rtx reg2_0 = XEXP (and2_rtx, 0); -+ rtx reg2_1 = XEXP (and2_rtx, 1); -+ -+ if (GET_CODE (reg1_0) == NOT) -+ { -+ if (rtx_equal_p (reg1_0, reg2_0)) -+ return reg_overlap_p (def_reg, reg1_1) -+ || reg_overlap_p (def_reg, reg2_1); -+ -+ if (rtx_equal_p (reg1_0, reg2_1)) -+ return reg_overlap_p (def_reg, reg1_1) -+ || reg_overlap_p (def_reg, reg2_0); -+ } -+ -+ if (GET_CODE (reg1_1) == NOT) -+ { -+ if (rtx_equal_p (reg1_1, reg2_0)) -+ return reg_overlap_p (def_reg, reg1_0) -+ || reg_overlap_p (def_reg, reg2_1); -+ -+ if (rtx_equal_p (reg1_1, reg2_1)) -+ return reg_overlap_p (def_reg, reg1_0) -+ || reg_overlap_p (def_reg, reg2_0); -+ } -+ -+ if (GET_CODE (reg2_0) == NOT) -+ { -+ if (rtx_equal_p (reg2_0, reg1_0)) -+ return reg_overlap_p (def_reg, reg2_1) -+ || reg_overlap_p (def_reg, reg1_1); -+ -+ if (rtx_equal_p (reg2_0, reg1_1)) -+ return reg_overlap_p (def_reg, reg2_1) -+ || reg_overlap_p (def_reg, reg1_0); -+ } -+ -+ if (GET_CODE (reg2_1) == NOT) -+ { -+ if (rtx_equal_p (reg2_1, reg1_0)) -+ return reg_overlap_p (def_reg, reg2_0) -+ || reg_overlap_p (def_reg, reg1_1); -+ -+ if (rtx_equal_p (reg2_1, reg1_1)) -+ return reg_overlap_p (def_reg, reg2_0) -+ || reg_overlap_p (def_reg, reg1_0); -+ } -+ -+ gcc_unreachable (); -+} - } // namespace scheduling - } // namespace nds32 - -@@ -375,8 +485,7 @@ - operations in order to write two registers. We have to check the - dependency from the producer to the first micro-operation. */ - case TYPE_DIV: -- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 -- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) -+ if (divmod_p (consumer)) - use_rtx = SET_SRC (parallel_element (consumer, 0)); - else - use_rtx = SET_SRC (PATTERN (consumer)); -@@ -506,8 +615,7 @@ - operations in order to write two registers. We have to check the - dependency from the producer to the first micro-operation. */ - case TYPE_DIV: -- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 -- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) -+ if (divmod_p (consumer)) - use_rtx = SET_SRC (parallel_element (consumer, 0)); - else - use_rtx = SET_SRC (PATTERN (consumer)); -@@ -606,8 +714,7 @@ - break; - - case TYPE_DIV: -- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 -- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) -+ if (divmod_p (consumer)) - use_rtx = SET_SRC (parallel_element (consumer, 0)); - else - use_rtx = SET_SRC (PATTERN (consumer)); -@@ -706,13 +813,175 @@ - We have to check the dependency from the producer to the first - micro-operation. */ - case TYPE_DIV: -- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 -- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) -+ if (divmod_p (consumer)) -+ use_rtx = SET_SRC (parallel_element (consumer, 0)); -+ else -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ break; -+ -+ case TYPE_MMU: -+ if (GET_CODE (PATTERN (consumer)) == SET) -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ else -+ return true; -+ break; -+ -+ case TYPE_LOAD: -+ case TYPE_STORE: -+ use_rtx = extract_mem_rtx (consumer); -+ break; -+ -+ case TYPE_LOAD_MULTIPLE: -+ case TYPE_STORE_MULTIPLE: -+ use_rtx = extract_base_reg (consumer); -+ break; -+ -+ case TYPE_BRANCH: -+ use_rtx = PATTERN (consumer); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ if (reg_overlap_p (def_reg, use_rtx)) -+ return true; -+ -+ return false; -+} -+ -+/* Check the dependency between the producer defining DEF_REG and CONSUMER -+ requiring input operand at EX. */ -+bool -+n10_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg) -+{ -+ rtx use_rtx; -+ -+ switch (get_attr_type (consumer)) -+ { -+ case TYPE_ALU: -+ case TYPE_PBSAD: -+ case TYPE_MUL: -+ case TYPE_DALU: -+ case TYPE_DALU64: -+ case TYPE_DMUL: -+ case TYPE_DPACK: -+ case TYPE_DINSB: -+ case TYPE_DCMP: -+ case TYPE_DCLIP: -+ case TYPE_DALUROUND: -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ break; -+ -+ case TYPE_ALU_SHIFT: -+ use_rtx = extract_shift_reg (consumer); -+ break; -+ -+ case TYPE_PBSADA: -+ return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg); -+ -+ case TYPE_MAC: -+ case TYPE_DMAC: -+ use_rtx = extract_mac_non_acc_rtx (consumer); -+ break; -+ -+ /* Some special instructions, divmodsi4 and udivmodsi4, produce two -+ results, the quotient and the remainder. */ -+ case TYPE_DIV: -+ if (divmod_p (consumer)) -+ use_rtx = SET_SRC (parallel_element (consumer, 0)); -+ else -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ break; -+ -+ case TYPE_DWEXT: -+ return wext_odd_dep_p (consumer, def_reg); -+ -+ case TYPE_DBPICK: -+ return bpick_ra_rb_dep_p (consumer, def_reg); -+ -+ case TYPE_MMU: -+ if (GET_CODE (PATTERN (consumer)) == SET) -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ else -+ return true; -+ break; -+ -+ case TYPE_LOAD: -+ case TYPE_STORE: -+ use_rtx = extract_mem_rtx (consumer); -+ break; -+ -+ case TYPE_LOAD_MULTIPLE: -+ case TYPE_STORE_MULTIPLE: -+ use_rtx = extract_base_reg (consumer); -+ break; -+ -+ case TYPE_BRANCH: -+ use_rtx = PATTERN (consumer); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ if (reg_overlap_p (def_reg, use_rtx)) -+ return true; -+ -+ return false; -+} -+ -+/* Check the dependency between the producer defining DEF_REG and CONSUMER -+ requiring input operand at EX. */ -+bool -+gw_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg) -+{ -+ rtx use_rtx; -+ -+ switch (get_attr_type (consumer)) -+ { -+ case TYPE_ALU: -+ case TYPE_PBSAD: -+ case TYPE_MUL: -+ case TYPE_DALU: -+ case TYPE_DALU64: -+ case TYPE_DMUL: -+ case TYPE_DPACK: -+ case TYPE_DINSB: -+ case TYPE_DCMP: -+ case TYPE_DCLIP: -+ case TYPE_DALUROUND: -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ break; -+ -+ case TYPE_ALU_SHIFT: -+ use_rtx = extract_shift_reg (consumer); -+ break; -+ -+ case TYPE_PBSADA: -+ return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg); -+ -+ case TYPE_MAC: -+ case TYPE_DMAC: -+ use_rtx = extract_mac_non_acc_rtx (consumer); -+ break; -+ -+ /* Some special instructions, divmodsi4 and udivmodsi4, produce two -+ results, the quotient and the remainder. We have to check the -+ dependency from the producer to the first micro-operation. */ -+ case TYPE_DIV: -+ if (divmod_p (consumer)) - use_rtx = SET_SRC (parallel_element (consumer, 0)); - else - use_rtx = SET_SRC (PATTERN (consumer)); - break; - -+ case TYPE_DWEXT: -+ return wext_odd_dep_p (consumer, def_reg); -+ -+ case TYPE_DBPICK: -+ return bpick_ra_rb_dep_p (consumer, def_reg); -+ - case TYPE_MMU: - if (GET_CODE (PATTERN (consumer)) == SET) - use_rtx = SET_SRC (PATTERN (consumer)); -@@ -744,7 +1013,153 @@ - return false; - } - -+/* Check dependencies from any stages to ALU_E1 (E1). This is a helper -+ function of n13_consumed_by_e1_dep_p (). */ -+bool -+n13_alu_e1_insn_dep_reg_p (rtx_insn *alu_e1_insn, rtx def_reg) -+{ -+ rtx unspec_rtx, operand_ra, operand_rb; -+ rtx src_rtx, dst_rtx; -+ -+ switch (INSN_CODE (alu_e1_insn)) -+ { -+ /* BSP and BSE are supported by built-in functions, the corresponding -+ patterns are formed by UNSPEC RTXs. We have to handle them -+ individually. */ -+ case CODE_FOR_unspec_bsp: -+ case CODE_FOR_unspec_bse: -+ unspec_rtx = SET_SRC (parallel_element (alu_e1_insn, 0)); -+ gcc_assert (GET_CODE (unspec_rtx) == UNSPEC); -+ -+ operand_ra = XVECEXP (unspec_rtx, 0, 0); -+ operand_rb = XVECEXP (unspec_rtx, 0, 1); -+ -+ if (rtx_equal_p (def_reg, operand_ra) -+ || rtx_equal_p (def_reg, operand_rb)) -+ return true; -+ -+ return false; -+ -+ /* Unlink general ALU instructions, MOVD44 requires operands at E1. */ -+ case CODE_FOR_move_di: -+ case CODE_FOR_move_df: -+ src_rtx = SET_SRC (PATTERN (alu_e1_insn)); -+ dst_rtx = SET_DEST (PATTERN (alu_e1_insn)); -+ -+ if (REG_P (dst_rtx) && REG_P (src_rtx) -+ && rtx_equal_p (src_rtx, def_reg)) -+ return true; -+ -+ return false; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Check the dependency between the producer defining DEF_REG and CONSUMER -+ requiring input operand at E1. Because the address generation unti is -+ at E1, the address input should be ready at E1. Note that the branch -+ target is also a kind of addresses, so we have to check it. */ -+bool -+n13_consumed_by_e1_dep_p (rtx_insn *consumer, rtx def_reg) -+{ -+ rtx use_rtx; -+ -+ switch (get_attr_type (consumer)) -+ { -+ /* ALU_E1 */ -+ case TYPE_ALU: -+ return n13_alu_e1_insn_dep_reg_p (consumer, def_reg); -+ -+ case TYPE_PBSADA: -+ return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg); -+ -+ case TYPE_PBSAD: -+ case TYPE_MUL: -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ break; -+ -+ case TYPE_MAC: -+ use_rtx = extract_mac_non_acc_rtx (consumer); -+ break; -+ -+ case TYPE_DIV: -+ if (divmod_p (consumer)) -+ use_rtx = SET_SRC (parallel_element (consumer, 0)); -+ else -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ break; -+ -+ case TYPE_MMU: -+ if (GET_CODE (PATTERN (consumer)) == SET) -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ else -+ return true; -+ break; -+ -+ case TYPE_BRANCH: -+ use_rtx = extract_branch_target_rtx (consumer); -+ break; -+ -+ case TYPE_LOAD: -+ case TYPE_STORE: -+ use_rtx = extract_mem_rtx (consumer); -+ break; -+ -+ case TYPE_LOAD_MULTIPLE: -+ case TYPE_STORE_MULTIPLE: -+ use_rtx = extract_base_reg (consumer); -+ break; -+ -+ default: -+ return false; -+ } -+ -+ if (reg_overlap_p (def_reg, use_rtx)) -+ return true; -+ -+ return false; -+} -+ -+/* Check the dependency between the producer defining DEF_REG and CONSUMER -+ requiring input operand at E2. */ -+bool -+n13_consumed_by_e2_dep_p (rtx_insn *consumer, rtx def_reg) -+{ -+ rtx use_rtx; -+ -+ switch (get_attr_type (consumer)) -+ { -+ case TYPE_ALU: -+ case TYPE_STORE: -+ use_rtx = SET_SRC (PATTERN (consumer)); -+ break; -+ -+ case TYPE_ALU_SHIFT: -+ use_rtx = extract_shift_reg (consumer); -+ break; -+ -+ case TYPE_PBSADA: -+ return pbsada_insn_rt_dep_reg_p (consumer, def_reg); -+ -+ case TYPE_STORE_MULTIPLE: -+ use_rtx = extract_nth_access_rtx (consumer, 0); -+ break; -+ -+ case TYPE_BRANCH: -+ use_rtx = extract_branch_condition_rtx (consumer); -+ break; -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ if (reg_overlap_p (def_reg, use_rtx)) -+ return true; - -+ return false; -+} - } // anonymous namespace - - /* ------------------------------------------------------------------------ */ -@@ -837,8 +1252,7 @@ - break; - - case TYPE_DIV: -- if (INSN_CODE (producer) == CODE_FOR_divmodsi4 -- || INSN_CODE (producer) == CODE_FOR_udivmodsi4) -+ if (divmod_p (producer)) - def_reg = SET_DEST (parallel_element (producer, 1)); - else - def_reg = SET_DEST (PATTERN (producer)); -@@ -969,8 +1383,7 @@ - break; - - case TYPE_DIV: -- if (INSN_CODE (producer) == CODE_FOR_divmodsi4 -- || INSN_CODE (producer) == CODE_FOR_udivmodsi4) -+ if (divmod_p (producer)) - { - rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); - rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); -@@ -1073,8 +1486,7 @@ - results, the quotient and the remainder. We have to handle them - individually. */ - case TYPE_DIV: -- if (INSN_CODE (producer) == CODE_FOR_divmodsi4 -- || INSN_CODE (producer) == CODE_FOR_udivmodsi4) -+ if (divmod_p (producer)) - { - rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); - rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); -@@ -1132,4 +1544,245 @@ - return n9_3r2w_consumed_by_ex_dep_p (consumer, last_def_reg); - } - -+/* Guard functions for N10 cores. */ -+ -+/* Check dependencies from EX to EX (ADDR_OUT -> ADDR_IN). */ -+bool -+nds32_n10_ex_to_ex_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ gcc_assert (get_attr_type (producer) == TYPE_FLOAD -+ || get_attr_type (producer) == TYPE_FSTORE); -+ gcc_assert (get_attr_type (consumer) == TYPE_FLOAD -+ || get_attr_type (consumer) == TYPE_FSTORE); -+ -+ if (!post_update_insn_p (producer)) -+ return false; -+ -+ return reg_overlap_p (extract_base_reg (producer), -+ extract_mem_rtx (consumer)); -+} -+ -+/* Check dependencies from MM to EX. */ -+bool -+nds32_n10_mm_to_ex_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx def_reg; -+ -+ switch (get_attr_type (producer)) -+ { -+ case TYPE_LOAD: -+ case TYPE_MUL: -+ case TYPE_MAC: -+ case TYPE_DALU64: -+ case TYPE_DMUL: -+ case TYPE_DMAC: -+ case TYPE_DALUROUND: -+ case TYPE_DBPICK: -+ case TYPE_DWEXT: -+ def_reg = SET_DEST (PATTERN (producer)); -+ break; -+ -+ /* Some special instructions, divmodsi4 and udivmodsi4, produce two -+ results, the quotient and the remainder. We have to handle them -+ individually. */ -+ case TYPE_DIV: -+ if (divmod_p (producer)) -+ { -+ rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); -+ rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); -+ -+ return (n10_consumed_by_ex_dep_p (consumer, def_reg1) -+ || n10_consumed_by_ex_dep_p (consumer, def_reg2)); -+ } -+ -+ def_reg = SET_DEST (PATTERN (producer)); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return n10_consumed_by_ex_dep_p (consumer, def_reg); -+} -+ -+/* Check dependencies from LMW(N, N) to EX. */ -+bool -+nds32_n10_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx last_def_reg = extract_nth_access_reg (producer, -1); -+ -+ return n10_consumed_by_ex_dep_p (consumer, last_def_reg); -+} -+ -+/* Guard functions for Graywolf cores. */ -+ -+/* Check dependencies from EX to EX (ADDR_OUT -> ADDR_IN). */ -+bool -+nds32_gw_ex_to_ex_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ return nds32_n10_ex_to_ex_p (producer, consumer); -+} -+ -+/* Check dependencies from MM to EX. */ -+bool -+nds32_gw_mm_to_ex_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx def_reg; -+ -+ switch (get_attr_type (producer)) -+ { -+ case TYPE_LOAD: -+ case TYPE_MUL: -+ case TYPE_MAC: -+ case TYPE_DALU64: -+ case TYPE_DMUL: -+ case TYPE_DMAC: -+ case TYPE_DALUROUND: -+ case TYPE_DBPICK: -+ case TYPE_DWEXT: -+ def_reg = SET_DEST (PATTERN (producer)); -+ break; -+ -+ /* Some special instructions, divmodsi4 and udivmodsi4, produce two -+ results, the quotient and the remainder. We have to handle them -+ individually. */ -+ case TYPE_DIV: -+ if (divmod_p (producer)) -+ { -+ rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); -+ rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); -+ -+ return (gw_consumed_by_ex_dep_p (consumer, def_reg1) -+ || gw_consumed_by_ex_dep_p (consumer, def_reg2)); -+ } -+ -+ def_reg = SET_DEST (PATTERN (producer)); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return gw_consumed_by_ex_dep_p (consumer, def_reg); -+} -+ -+/* Check dependencies from LMW(N, N) to EX. */ -+bool -+nds32_gw_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx last_def_reg = extract_nth_access_reg (producer, -1); -+ -+ return gw_consumed_by_ex_dep_p (consumer, last_def_reg); -+} -+ -+/* Guard functions for N12/N13 cores. */ -+ -+/* Check dependencies from E2 to E1. */ -+bool -+nds32_n13_e2_to_e1_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx def_reg; -+ -+ switch (get_attr_type (producer)) -+ { -+ /* Only post-update load/store instructions are considered. These -+ instructions produces address output at E2. */ -+ case TYPE_LOAD: -+ case TYPE_STORE: -+ case TYPE_LOAD_MULTIPLE: -+ case TYPE_STORE_MULTIPLE: -+ if (!post_update_insn_p (producer)) -+ return false; -+ -+ def_reg = extract_base_reg (producer); -+ break; -+ -+ case TYPE_ALU: -+ case TYPE_ALU_SHIFT: -+ case TYPE_PBSAD: -+ case TYPE_PBSADA: -+ case TYPE_MUL: -+ case TYPE_MAC: -+ def_reg = SET_DEST (PATTERN (producer)); -+ break; -+ -+ case TYPE_BRANCH: -+ return true; -+ -+ case TYPE_DIV: -+ /* Some special instructions, divmodsi4 and udivmodsi4, produce two -+ results, the quotient and the remainder. We have to handle them -+ individually. */ -+ if (divmod_p (producer)) -+ { -+ rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); -+ rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); -+ -+ return (n13_consumed_by_e1_dep_p (consumer, def_reg1) -+ || n13_consumed_by_e1_dep_p (consumer, def_reg2)); -+ } -+ -+ def_reg = SET_DEST (PATTERN (producer)); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return n13_consumed_by_e1_dep_p (consumer, def_reg); -+} -+ -+/* Check dependencies from Load-Store Unit (E3) to E1. */ -+bool -+nds32_n13_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx def_reg = SET_DEST (PATTERN (producer)); -+ -+ gcc_assert (get_attr_type (producer) == TYPE_LOAD); -+ gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG); -+ -+ return n13_consumed_by_e1_dep_p (consumer, def_reg); -+} -+ -+/* Check dependencies from Load-Store Unit (E3) to E2. */ -+bool -+nds32_n13_load_to_e2_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx def_reg = SET_DEST (PATTERN (producer)); -+ -+ gcc_assert (get_attr_type (producer) == TYPE_LOAD); -+ gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG); -+ -+ return n13_consumed_by_e2_dep_p (consumer, def_reg); -+} -+ -+/* Check dependencies from LMW(N, N) to E1. */ -+bool -+nds32_n13_last_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx last_def_reg = extract_nth_access_reg (producer, -1); -+ -+ return n13_consumed_by_e1_dep_p (consumer, last_def_reg); -+} -+ -+/* Check dependencies from LMW(N, N) to E2. */ -+bool -+nds32_n13_last_load_to_e2_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx last_def_reg = extract_nth_access_reg (producer, -1); -+ -+ return n13_consumed_by_e2_dep_p (consumer, last_def_reg); -+} -+ -+/* Check dependencies from LMW(N, N-1) to E2. */ -+bool -+nds32_n13_last_two_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer) -+{ -+ rtx last_two_def_reg = extract_nth_access_reg (producer, -2); -+ -+ if (last_two_def_reg == NULL_RTX) -+ return false; -+ -+ return n13_consumed_by_e1_dep_p (consumer, last_two_def_reg); -+} - /* ------------------------------------------------------------------------ */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-predicates.c gcc-8.2.0/gcc/config/nds32/nds32-predicates.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-predicates.c 2018-05-07 04:22:07.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-predicates.c 2019-01-25 15:41:54.217806220 +0100 -@@ -356,8 +356,8 @@ - } - - /* Function to check if 'bclr' instruction can be used with IVAL. */ --int --nds32_can_use_bclr_p (int ival) -+bool -+nds32_can_use_bclr_p (HOST_WIDE_INT ival) - { - int one_bit_count; - unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); -@@ -373,8 +373,8 @@ - } - - /* Function to check if 'bset' instruction can be used with IVAL. */ --int --nds32_can_use_bset_p (int ival) -+bool -+nds32_can_use_bset_p (HOST_WIDE_INT ival) - { - int one_bit_count; - unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); -@@ -389,8 +389,8 @@ - } - - /* Function to check if 'btgl' instruction can be used with IVAL. */ --int --nds32_can_use_btgl_p (int ival) -+bool -+nds32_can_use_btgl_p (HOST_WIDE_INT ival) - { - int one_bit_count; - unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); -@@ -405,8 +405,8 @@ - } - - /* Function to check if 'bitci' instruction can be used with IVAL. */ --int --nds32_can_use_bitci_p (int ival) -+bool -+nds32_can_use_bitci_p (HOST_WIDE_INT ival) - { - /* If we are using V3 ISA, we have 'bitci' instruction. - Try to see if we can present 'andi' semantic with -@@ -518,4 +518,117 @@ - - return val >= lower && val < upper; - } -+ -+bool -+nds32_const_unspec_p (rtx x) -+{ -+ if (GET_CODE (x) == CONST) -+ { -+ x = XEXP (x, 0); -+ -+ if (GET_CODE (x) == PLUS) -+ x = XEXP (x, 0); -+ -+ if (GET_CODE (x) == UNSPEC) -+ { -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_GOTINIT: -+ case UNSPEC_GOT: -+ case UNSPEC_GOTOFF: -+ case UNSPEC_PLT: -+ case UNSPEC_TLSGD: -+ case UNSPEC_TLSLD: -+ case UNSPEC_TLSIE: -+ case UNSPEC_TLSLE: -+ return false; -+ default: -+ return true; -+ } -+ } -+ } -+ -+ if (GET_CODE (x) == SYMBOL_REF -+ && SYMBOL_REF_TLS_MODEL (x)) -+ return false; -+ -+ return true; -+} -+ -+HOST_WIDE_INT -+const_vector_to_hwint (rtx op) -+{ -+ HOST_WIDE_INT hwint = 0; -+ HOST_WIDE_INT mask; -+ int i; -+ int shift_adv; -+ int shift = 0; -+ int nelem; -+ -+ switch (GET_MODE (op)) -+ { -+ case E_V2HImode: -+ mask = 0xffff; -+ shift_adv = 16; -+ nelem = 2; -+ break; -+ case E_V4QImode: -+ mask = 0xff; -+ shift_adv = 8; -+ nelem = 4; -+ break; -+ default: -+ gcc_unreachable (); -+ } -+ -+ if (TARGET_BIG_ENDIAN) -+ { -+ for (i = 0; i < nelem; ++i) -+ { -+ HOST_WIDE_INT val = XINT (XVECEXP (op, 0, nelem - i - 1), 0); -+ hwint |= (val & mask) << shift; -+ shift = shift + shift_adv; -+ } -+ } -+ else -+ { -+ for (i = 0; i < nelem; ++i) -+ { -+ HOST_WIDE_INT val = XINT (XVECEXP (op, 0, i), 0); -+ hwint |= (val & mask) << shift; -+ shift = shift + shift_adv; -+ } -+ } -+ -+ return hwint; -+} -+ -+bool -+nds32_valid_CVp5_p (rtx op) -+{ -+ HOST_WIDE_INT ival = const_vector_to_hwint (op); -+ return (ival < ((1 << 5) + 16)) && (ival >= (0 + 16)); -+} -+ -+bool -+nds32_valid_CVs5_p (rtx op) -+{ -+ HOST_WIDE_INT ival = const_vector_to_hwint (op); -+ return (ival < (1 << 4)) && (ival >= -(1 << 4)); -+} -+ -+bool -+nds32_valid_CVs2_p (rtx op) -+{ -+ HOST_WIDE_INT ival = const_vector_to_hwint (op); -+ return (ival < (1 << 19)) && (ival >= -(1 << 19)); -+} -+ -+bool -+nds32_valid_CVhi_p (rtx op) -+{ -+ HOST_WIDE_INT ival = const_vector_to_hwint (op); -+ return (ival != 0) && ((ival & 0xfff) == 0); -+} -+ - /* ------------------------------------------------------------------------ */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-protos.h gcc-8.2.0/gcc/config/nds32/nds32-protos.h ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-protos.h 2018-04-22 11:05:10.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-protos.h 2019-01-25 15:38:32.833242671 +0100 -@@ -69,9 +69,10 @@ - - /* ------------------------------------------------------------------------ */ - --/* Auxiliary functions for lwm/smw. */ -+/* Auxiliary functions for manipulation DI mode. */ - --extern bool nds32_valid_smw_lwm_base_p (rtx); -+extern rtx nds32_di_high_part_subreg(rtx); -+extern rtx nds32_di_low_part_subreg(rtx); - - /* Auxiliary functions for expanding rtl used in nds32-multiple.md. */ - -@@ -116,6 +117,20 @@ - extern bool nds32_n9_3r2w_mm_to_ex_p (rtx_insn *, rtx_insn *); - extern bool nds32_n9_last_load_to_ex_p (rtx_insn *, rtx_insn *); - -+extern bool nds32_n10_ex_to_ex_p (rtx_insn *, rtx_insn *); -+extern bool nds32_n10_mm_to_ex_p (rtx_insn *, rtx_insn *); -+extern bool nds32_n10_last_load_to_ex_p (rtx_insn *, rtx_insn *); -+ -+extern bool nds32_gw_ex_to_ex_p (rtx_insn *, rtx_insn *); -+extern bool nds32_gw_mm_to_ex_p (rtx_insn *, rtx_insn *); -+extern bool nds32_gw_last_load_to_ex_p (rtx_insn *, rtx_insn *); -+ -+extern bool nds32_n13_e2_to_e1_p (rtx_insn *, rtx_insn *); -+extern bool nds32_n13_load_to_e1_p (rtx_insn *, rtx_insn *); -+extern bool nds32_n13_load_to_e2_p (rtx_insn *, rtx_insn *); -+extern bool nds32_n13_last_load_to_e1_p (rtx_insn *, rtx_insn *); -+extern bool nds32_n13_last_load_to_e2_p (rtx_insn *, rtx_insn *); -+extern bool nds32_n13_last_two_load_to_e1_p (rtx_insn *, rtx_insn *); - - /* Auxiliary functions for stack operation predicate checking. */ - -@@ -123,24 +138,25 @@ - - /* Auxiliary functions for bit operation detection. */ - --extern int nds32_can_use_bclr_p (int); --extern int nds32_can_use_bset_p (int); --extern int nds32_can_use_btgl_p (int); -+extern bool nds32_can_use_bclr_p (HOST_WIDE_INT); -+extern bool nds32_can_use_bset_p (HOST_WIDE_INT); -+extern bool nds32_can_use_btgl_p (HOST_WIDE_INT); - --extern int nds32_can_use_bitci_p (int); -+extern bool nds32_can_use_bitci_p (HOST_WIDE_INT); - - extern bool nds32_const_double_range_ok_p (rtx, machine_mode, - HOST_WIDE_INT, HOST_WIDE_INT); - -+extern bool nds32_const_unspec_p (rtx x); -+ - /* Auxiliary function for 'Computing the Length of an Insn'. */ - - extern int nds32_adjust_insn_length (rtx_insn *, int); - - /* Auxiliary functions for FP_AS_GP detection. */ - --extern int nds32_fp_as_gp_check_available (void); -- - extern bool nds32_symbol_load_store_p (rtx_insn *); -+extern bool nds32_naked_function_p (tree); - - /* Auxiliary functions for jump table generation. */ - -@@ -159,10 +175,50 @@ - extern enum nds32_expand_result_type nds32_expand_movcc (rtx *); - extern void nds32_expand_float_movcc (rtx *); - -+/* Auxiliary functions for expand extv/insv instruction. */ -+ -+extern enum nds32_expand_result_type nds32_expand_extv (rtx *); -+extern enum nds32_expand_result_type nds32_expand_insv (rtx *); -+ -+/* Auxiliary functions for expand PIC instruction. */ -+ -+extern void nds32_expand_pic_move (rtx *); -+ -+/* Auxiliary functions to legitimize PIC address. */ -+ -+extern rtx nds32_legitimize_pic_address (rtx); -+ -+/* Auxiliary functions for expand TLS instruction. */ -+ -+extern void nds32_expand_tls_move (rtx *); -+ -+/* Auxiliary functions to legitimize TLS address. */ -+ -+extern rtx nds32_legitimize_tls_address (rtx); -+ -+/* Auxiliary functions to identify thread-local symbol. */ -+ -+extern bool nds32_tls_referenced_p (rtx); -+ -+/* Auxiliary functions for expand ICT instruction. */ -+ -+extern void nds32_expand_ict_move (rtx *); -+ -+/* Auxiliary functions to legitimize address for indirect-call symbol. */ -+ -+extern rtx nds32_legitimize_ict_address (rtx); -+ -+/* Auxiliary functions to identify indirect-call symbol. */ -+ -+extern bool nds32_indirect_call_referenced_p (rtx); - - /* Auxiliary functions to identify long-call symbol. */ - extern bool nds32_long_call_p (rtx); - -+/* Auxiliary functions to identify SYMBOL_REF and LABEL_REF pattern. */ -+ -+extern bool symbolic_reference_mentioned_p (rtx); -+ - /* Auxiliary functions to identify conditional move comparison operand. */ - - extern int nds32_cond_move_p (rtx); -@@ -185,6 +241,7 @@ - extern const char *nds32_output_float_load(rtx *); - extern const char *nds32_output_float_store(rtx *); - extern const char *nds32_output_smw_single_word (rtx *); -+extern const char *nds32_output_smw_double_word (rtx *); - extern const char *nds32_output_lmw_single_word (rtx *); - extern const char *nds32_output_double (rtx *, bool); - extern const char *nds32_output_cbranchsi4_equality_zero (rtx_insn *, rtx *); -@@ -193,9 +250,12 @@ - rtx *); - extern const char *nds32_output_cbranchsi4_greater_less_zero (rtx_insn *, rtx *); - -+extern const char *nds32_output_unpkd8 (rtx, rtx, rtx, rtx, bool); -+ - extern const char *nds32_output_call (rtx, rtx *, rtx, - const char *, const char *, bool); -- -+extern const char *nds32_output_tls_desc (rtx *); -+extern const char *nds32_output_tls_ie (rtx *); - - /* Auxiliary functions to output stack push/pop instruction. */ - -@@ -203,9 +263,19 @@ - extern const char *nds32_output_stack_pop (rtx); - extern const char *nds32_output_return (void); - -+ -+/* Auxiliary functions to split/output sms pattern. */ -+extern bool nds32_need_split_sms_p (rtx, rtx, rtx, rtx); -+extern const char *nds32_output_sms (rtx, rtx, rtx, rtx); -+extern void nds32_split_sms (rtx, rtx, rtx, rtx, rtx, rtx, rtx); -+ - /* Auxiliary functions to split double word RTX pattern. */ - - extern void nds32_spilt_doubleword (rtx *, bool); -+extern void nds32_split_ashiftdi3 (rtx, rtx, rtx); -+extern void nds32_split_ashiftrtdi3 (rtx, rtx, rtx); -+extern void nds32_split_lshiftrtdi3 (rtx, rtx, rtx); -+extern void nds32_split_rotatertdi3 (rtx, rtx, rtx); - - /* Auxiliary functions to split large constant RTX pattern. */ - -@@ -237,15 +307,29 @@ - extern void nds32_asm_file_start_for_isr (void); - extern void nds32_asm_file_end_for_isr (void); - extern bool nds32_isr_function_p (tree); -+extern bool nds32_isr_function_critical_p (tree); - - /* Auxiliary functions for cost calculation. */ - -+extern void nds32_init_rtx_costs (void); - extern bool nds32_rtx_costs_impl (rtx, machine_mode, int, int, int *, bool); - extern int nds32_address_cost_impl (rtx, machine_mode, addr_space_t, bool); - - /* Auxiliary functions for pre-define marco. */ - extern void nds32_cpu_cpp_builtins(struct cpp_reader *); - -+/* Auxiliary functions for const_vector's constraints. */ -+ -+extern HOST_WIDE_INT const_vector_to_hwint (rtx); -+extern bool nds32_valid_CVp5_p (rtx); -+extern bool nds32_valid_CVs5_p (rtx); -+extern bool nds32_valid_CVs2_p (rtx); -+extern bool nds32_valid_CVhi_p (rtx); -+ -+/* Auxiliary functions for lwm/smw. */ -+ -+extern bool nds32_valid_smw_lwm_base_p (rtx); -+ - extern bool nds32_split_double_word_load_store_p (rtx *,bool); - - namespace nds32 { -@@ -258,11 +342,13 @@ - bool store_single_p (rtx_insn *); - bool load_double_p (rtx_insn *); - bool store_double_p (rtx_insn *); -+bool store_offset_reg_p (rtx_insn *); - bool post_update_insn_p (rtx_insn *); - bool immed_offset_p (rtx); - int find_post_update_rtx (rtx_insn *); - rtx extract_mem_rtx (rtx_insn *); - rtx extract_base_reg (rtx_insn *); -+rtx extract_offset_rtx (rtx_insn *); - - rtx extract_shift_reg (rtx); - -@@ -271,6 +357,8 @@ - - rtx extract_mac_non_acc_rtx (rtx_insn *); - -+bool divmod_p (rtx_insn *); -+ - rtx extract_branch_target_rtx (rtx_insn *); - rtx extract_branch_condition_rtx (rtx_insn *); - } // namespace nds32 -@@ -279,5 +367,6 @@ - - /* Functions for create nds32 specific optimization pass. */ - extern rtl_opt_pass *make_pass_nds32_relax_opt (gcc::context *); -+extern rtl_opt_pass *make_pass_nds32_fp_as_gp (gcc::context *); - - /* ------------------------------------------------------------------------ */ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-relax-opt.c gcc-8.2.0/gcc/config/nds32/nds32-relax-opt.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-relax-opt.c 2018-04-01 12:07:40.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-relax-opt.c 2019-01-25 15:38:32.833242671 +0100 -@@ -52,6 +52,8 @@ - #include "cfgrtl.h" - #include "tree-pass.h" - -+using namespace nds32; -+ - /* This is used to create unique relax hint id value. - The initial value is 0. */ - static int relax_group_id = 0; -@@ -185,6 +187,121 @@ - return false; - } - -+/* Return true if x is const and the referance is ict symbol. */ -+static bool -+nds32_ict_const_p (rtx x) -+{ -+ if (GET_CODE (x) == CONST) -+ { -+ x = XEXP (x, 0); -+ return nds32_indirect_call_referenced_p (x); -+ } -+ return FALSE; -+} -+ -+/* Group the following pattern as relax candidates: -+ -+ GOT: -+ sethi $ra, hi20(sym) -+ ori $ra, $ra, lo12(sym) -+ lw $rb, [$ra + $gp] -+ -+ GOTOFF, TLSLE: -+ sethi $ra, hi20(sym) -+ ori $ra, $ra, lo12(sym) -+ LS $rb, [$ra + $gp] -+ -+ GOTOFF, TLSLE: -+ sethi $ra, hi20(sym) -+ ori $ra, $ra, lo12(sym) -+ add $rb, $ra, $gp($tp) -+ -+ Initial GOT table: -+ sethi $gp,hi20(sym) -+ ori $gp, $gp, lo12(sym) -+ add5.pc $gp */ -+ -+static auto_vec nds32_group_infos; -+/* Group the PIC and TLS relax candidate instructions for linker. */ -+static bool -+nds32_pic_tls_group (rtx_insn *def_insn, -+ enum nds32_relax_insn_type relax_type, -+ int sym_type) -+{ -+ df_ref def_record; -+ df_link *link; -+ rtx_insn *use_insn = NULL; -+ rtx pat, new_pat; -+ def_record = DF_INSN_DEFS (def_insn); -+ for (link = DF_REF_CHAIN (def_record); link; link = link->next) -+ { -+ if (!DF_REF_INSN_INFO (link->ref)) -+ continue; -+ -+ use_insn = DF_REF_INSN (link->ref); -+ -+ /* Skip if define insn and use insn not in the same basic block. */ -+ if (!dominated_by_p (CDI_DOMINATORS, -+ BLOCK_FOR_INSN (use_insn), -+ BLOCK_FOR_INSN (def_insn))) -+ return FALSE; -+ -+ /* Skip if use_insn not active insn. */ -+ if (!active_insn_p (use_insn)) -+ return FALSE; -+ -+ switch (relax_type) -+ { -+ case RELAX_ORI: -+ -+ /* GOTOFF, TLSLE: -+ sethi $ra, hi20(sym) -+ ori $ra, $ra, lo12(sym) -+ add $rb, $ra, $gp($tp) */ -+ if ((sym_type == UNSPEC_TLSLE -+ || sym_type == UNSPEC_GOTOFF) -+ && (recog_memoized (use_insn) == CODE_FOR_addsi3)) -+ { -+ pat = XEXP (PATTERN (use_insn), 1); -+ new_pat = -+ gen_rtx_UNSPEC (SImode, -+ gen_rtvec (2, XEXP (pat, 0), XEXP (pat, 1)), -+ UNSPEC_ADD32); -+ validate_replace_rtx (pat, new_pat, use_insn); -+ nds32_group_infos.safe_push (use_insn); -+ } -+ else if (nds32_plus_reg_load_store_p (use_insn) -+ && !nds32_sp_base_or_plus_load_store_p (use_insn)) -+ nds32_group_infos.safe_push (use_insn); -+ else -+ return FALSE; -+ break; -+ -+ default: -+ return FALSE; -+ } -+ } -+ return TRUE; -+} -+ -+static int -+nds32_pic_tls_symbol_type (rtx x) -+{ -+ x = XEXP (SET_SRC (PATTERN (x)), 1); -+ -+ if (GET_CODE (x) == CONST) -+ { -+ x = XEXP (x, 0); -+ -+ if (GET_CODE (x) == PLUS) -+ x = XEXP (x, 0); -+ -+ return XINT (x, 1); -+ } -+ -+ return XINT (x, 1); -+} -+ - /* Group the relax candidates with group id. */ - static void - nds32_group_insns (rtx sethi) -@@ -193,6 +310,7 @@ - df_link *link; - rtx_insn *use_insn = NULL; - rtx group_id; -+ bool valid; - - def_record = DF_INSN_DEFS (sethi); - -@@ -242,6 +360,132 @@ - /* Insert .relax_* directive. */ - if (active_insn_p (use_insn)) - emit_insn_before (gen_relax_group (group_id), use_insn); -+ -+ /* Find ori ra, ra, unspec(symbol) instruction. */ -+ if (use_insn != NULL -+ && recog_memoized (use_insn) == CODE_FOR_lo_sum -+ && !nds32_const_unspec_p (XEXP (SET_SRC (PATTERN (use_insn)), 1))) -+ { -+ int sym_type = nds32_pic_tls_symbol_type (use_insn); -+ valid = nds32_pic_tls_group (use_insn, RELAX_ORI, sym_type); -+ -+ /* Insert .relax_* directive. */ -+ while (!nds32_group_infos.is_empty ()) -+ { -+ use_insn = nds32_group_infos.pop (); -+ if (valid) -+ emit_insn_before (gen_relax_group (group_id), use_insn); -+ } -+ } -+ } -+ -+ relax_group_id++; -+} -+ -+/* Convert relax group id in rtl. */ -+ -+static void -+nds32_group_tls_insn (rtx insn) -+{ -+ rtx pat = PATTERN (insn); -+ rtx unspec_relax_group = XEXP (XVECEXP (pat, 0, 1), 0); -+ -+ while (GET_CODE (pat) != SET && GET_CODE (pat) == PARALLEL) -+ { -+ pat = XVECEXP (pat, 0, 0); -+ } -+ -+ if (GET_CODE (unspec_relax_group) == UNSPEC -+ && XINT (unspec_relax_group, 1) == UNSPEC_VOLATILE_RELAX_GROUP) -+ { -+ XVECEXP (unspec_relax_group, 0, 0) = GEN_INT (relax_group_id); -+ } -+ -+ relax_group_id++; -+} -+ -+static bool -+nds32_float_reg_load_store_p (rtx_insn *insn) -+{ -+ rtx pat = PATTERN (insn); -+ -+ if (get_attr_type (insn) == TYPE_FLOAD -+ && GET_CODE (pat) == SET -+ && (GET_MODE (XEXP (pat, 0)) == SFmode -+ || GET_MODE (XEXP (pat, 0)) == DFmode) -+ && MEM_P (XEXP (pat, 1))) -+ { -+ rtx addr = XEXP (XEXP (pat, 1), 0); -+ -+ /* [$ra] */ -+ if (REG_P (addr)) -+ return true; -+ /* [$ra + offset] */ -+ if (GET_CODE (addr) == PLUS -+ && REG_P (XEXP (addr, 0)) -+ && CONST_INT_P (XEXP (addr, 1))) -+ return true; -+ } -+ return false; -+} -+ -+ -+/* Group float load-store instructions: -+ la $ra, symbol -+ flsi $rt, [$ra + offset] */ -+ -+static void -+nds32_group_float_insns (rtx insn) -+{ -+ df_ref def_record, use_record; -+ df_link *link; -+ rtx_insn *use_insn = NULL; -+ rtx group_id; -+ -+ def_record = DF_INSN_DEFS (insn); -+ -+ for (link = DF_REF_CHAIN (def_record); link; link = link->next) -+ { -+ if (!DF_REF_INSN_INFO (link->ref)) -+ continue; -+ -+ use_insn = DF_REF_INSN (link->ref); -+ -+ /* Skip if define insn and use insn not in the same basic block. */ -+ if (!dominated_by_p (CDI_DOMINATORS, -+ BLOCK_FOR_INSN (use_insn), -+ BLOCK_FOR_INSN (insn))) -+ return; -+ -+ /* Skip if the low-part used register is from different high-part -+ instructions. */ -+ use_record = DF_INSN_USES (use_insn); -+ if (DF_REF_CHAIN (use_record) && DF_REF_CHAIN (use_record)->next) -+ return; -+ -+ /* Skip if use_insn not active insn. */ -+ if (!active_insn_p (use_insn)) -+ return; -+ -+ if (!nds32_float_reg_load_store_p (use_insn) -+ || find_post_update_rtx (use_insn) != -1) -+ return; -+ } -+ -+ group_id = GEN_INT (relax_group_id); -+ /* Insert .relax_* directive for insn. */ -+ emit_insn_before (gen_relax_group (group_id), insn); -+ -+ /* Scan the use insns and insert the directive. */ -+ for (link = DF_REF_CHAIN (def_record); link; link = link->next) -+ { -+ if (!DF_REF_INSN_INFO (link->ref)) -+ continue; -+ -+ use_insn = DF_REF_INSN (link->ref); -+ -+ /* Insert .relax_* directive. */ -+ emit_insn_before (gen_relax_group (group_id), use_insn); - } - - relax_group_id++; -@@ -271,8 +515,21 @@ - /* Find sethi ra, symbol instruction. */ - if (recog_memoized (insn) == CODE_FOR_sethi - && nds32_symbolic_operand (XEXP (SET_SRC (PATTERN (insn)), 0), -- SImode)) -+ SImode) -+ && !nds32_ict_const_p (XEXP (SET_SRC (PATTERN (insn)), 0))) - nds32_group_insns (insn); -+ else if (recog_memoized (insn) == CODE_FOR_tls_ie) -+ nds32_group_tls_insn (insn); -+ else if (TARGET_FPU_SINGLE -+ && recog_memoized (insn) == CODE_FOR_move_addr -+ && !nds32_ict_const_p (XEXP (SET_SRC (PATTERN (insn)), 0))) -+ { -+ nds32_group_float_insns (insn); -+ } -+ } -+ else if (CALL_P (insn) && recog_memoized (insn) == CODE_FOR_tls_desc) -+ { -+ nds32_group_tls_insn (insn); - } - } - -diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-utils.c gcc-8.2.0/gcc/config/nds32/nds32-utils.c ---- gcc-8.2.0.orig/gcc/config/nds32/nds32-utils.c 2018-04-08 10:31:52.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/nds32-utils.c 2019-01-25 15:38:32.833242671 +0100 -@@ -142,6 +142,23 @@ - return true; - } - -+bool -+store_offset_reg_p (rtx_insn *insn) -+{ -+ if (get_attr_type (insn) != TYPE_STORE) -+ return false; -+ -+ rtx offset_rtx = extract_offset_rtx (insn); -+ -+ if (offset_rtx == NULL_RTX) -+ return false; -+ -+ if (REG_P (offset_rtx)) -+ return true; -+ -+ return false; -+} -+ - /* Determine if INSN is a post update insn. */ - bool - post_update_insn_p (rtx_insn *insn) -@@ -316,22 +333,114 @@ - if (REG_P (XEXP (mem_rtx, 0))) - return XEXP (mem_rtx, 0); - -+ /* (mem (lo_sum (reg) (symbol_ref)) */ -+ if (GET_CODE (XEXP (mem_rtx, 0)) == LO_SUM) -+ return XEXP (XEXP (mem_rtx, 0), 0); -+ - plus_rtx = XEXP (mem_rtx, 0); - - if (GET_CODE (plus_rtx) == SYMBOL_REF - || GET_CODE (plus_rtx) == CONST) - return NULL_RTX; - -- gcc_assert (GET_CODE (plus_rtx) == PLUS -- || GET_CODE (plus_rtx) == POST_INC -- || GET_CODE (plus_rtx) == POST_DEC -- || GET_CODE (plus_rtx) == POST_MODIFY); -- gcc_assert (REG_P (XEXP (plus_rtx, 0))); - /* (mem (plus (reg) (const_int))) or -+ (mem (plus (mult (reg) (const_int 4)) (reg))) or - (mem (post_inc (reg))) or - (mem (post_dec (reg))) or - (mem (post_modify (reg) (plus (reg) (reg)))) */ -- return XEXP (plus_rtx, 0); -+ gcc_assert (GET_CODE (plus_rtx) == PLUS -+ || GET_CODE (plus_rtx) == POST_INC -+ || GET_CODE (plus_rtx) == POST_DEC -+ || GET_CODE (plus_rtx) == POST_MODIFY); -+ -+ if (REG_P (XEXP (plus_rtx, 0))) -+ return XEXP (plus_rtx, 0); -+ -+ gcc_assert (REG_P (XEXP (plus_rtx, 1))); -+ return XEXP (plus_rtx, 1); -+} -+ -+/* Extract the offset rtx from load/store insns. The function returns -+ NULL_RTX if offset is absent. */ -+rtx -+extract_offset_rtx (rtx_insn *insn) -+{ -+ rtx mem_rtx; -+ rtx plus_rtx; -+ rtx offset_rtx; -+ -+ /* Find the MEM rtx. The multiple load/store insns doens't have -+ the offset field so we can return NULL_RTX here. */ -+ switch (get_attr_type (insn)) -+ { -+ case TYPE_LOAD_MULTIPLE: -+ case TYPE_STORE_MULTIPLE: -+ return NULL_RTX; -+ -+ case TYPE_LOAD: -+ case TYPE_FLOAD: -+ case TYPE_STORE: -+ case TYPE_FSTORE: -+ mem_rtx = extract_mem_rtx (insn); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ gcc_assert (MEM_P (mem_rtx)); -+ -+ /* (mem (reg)) */ -+ if (REG_P (XEXP (mem_rtx, 0))) -+ return NULL_RTX; -+ -+ plus_rtx = XEXP (mem_rtx, 0); -+ -+ switch (GET_CODE (plus_rtx)) -+ { -+ case SYMBOL_REF: -+ case CONST: -+ case POST_INC: -+ case POST_DEC: -+ return NULL_RTX; -+ -+ case PLUS: -+ /* (mem (plus (reg) (const_int))) or -+ (mem (plus (mult (reg) (const_int 4)) (reg))) */ -+ if (REG_P (XEXP (plus_rtx, 0))) -+ offset_rtx = XEXP (plus_rtx, 1); -+ else -+ { -+ gcc_assert (REG_P (XEXP (plus_rtx, 1))); -+ offset_rtx = XEXP (plus_rtx, 0); -+ } -+ -+ if (ARITHMETIC_P (offset_rtx)) -+ { -+ gcc_assert (GET_CODE (offset_rtx) == MULT); -+ gcc_assert (REG_P (XEXP (offset_rtx, 0))); -+ offset_rtx = XEXP (offset_rtx, 0); -+ } -+ break; -+ -+ case LO_SUM: -+ /* (mem (lo_sum (reg) (symbol_ref)) */ -+ offset_rtx = XEXP (plus_rtx, 1); -+ break; -+ -+ case POST_MODIFY: -+ /* (mem (post_modify (reg) (plus (reg) (reg / const_int)))) */ -+ gcc_assert (REG_P (XEXP (plus_rtx, 0))); -+ plus_rtx = XEXP (plus_rtx, 1); -+ gcc_assert (GET_CODE (plus_rtx) == PLUS); -+ offset_rtx = XEXP (plus_rtx, 0); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return offset_rtx; - } - - /* Extract the register of the shift operand from an ALU_SHIFT rtx. */ -@@ -413,6 +522,7 @@ - switch (get_attr_type (insn)) - { - case TYPE_MAC: -+ case TYPE_DMAC: - if (REG_P (XEXP (exp, 0))) - return XEXP (exp, 1); - else -@@ -423,6 +533,19 @@ - } - } - -+/* Check if the DIV insn needs two write ports. */ -+bool -+divmod_p (rtx_insn *insn) -+{ -+ gcc_assert (get_attr_type (insn) == TYPE_DIV); -+ -+ if (INSN_CODE (insn) == CODE_FOR_divmodsi4 -+ || INSN_CODE (insn) == CODE_FOR_udivmodsi4) -+ return true; -+ -+ return false; -+} -+ - /* Extract the rtx representing the branch target to help recognize - data hazards. */ - rtx -diff -urN gcc-8.2.0.orig/gcc/config/nds32/pipelines.md gcc-8.2.0/gcc/config/nds32/pipelines.md ---- gcc-8.2.0.orig/gcc/config/nds32/pipelines.md 2018-04-08 11:21:30.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/pipelines.md 2019-01-25 15:38:32.833242671 +0100 -@@ -44,6 +44,24 @@ - - - ;; ------------------------------------------------------------------------ -+;; Include N10 pipeline settings. -+;; ------------------------------------------------------------------------ -+(include "nds32-n10.md") -+ -+ -+;; ------------------------------------------------------------------------ -+;; Include Graywolf pipeline settings. -+;; ------------------------------------------------------------------------ -+(include "nds32-graywolf.md") -+ -+ -+;; ------------------------------------------------------------------------ -+;; Include N12/N13 pipeline settings. -+;; ------------------------------------------------------------------------ -+(include "nds32-n13.md") -+ -+ -+;; ------------------------------------------------------------------------ - ;; Define simple pipeline settings. - ;; ------------------------------------------------------------------------ - -diff -urN gcc-8.2.0.orig/gcc/config/nds32/predicates.md gcc-8.2.0/gcc/config/nds32/predicates.md ---- gcc-8.2.0.orig/gcc/config/nds32/predicates.md 2018-04-06 07:51:33.000000000 +0200 -+++ gcc-8.2.0/gcc/config/nds32/predicates.md 2019-01-25 15:38:32.833242671 +0100 -@@ -40,7 +40,15 @@ - (match_code "mult,and,ior,xor")) - - (define_predicate "nds32_symbolic_operand" -- (match_code "const,symbol_ref,label_ref")) -+ (and (match_code "const,symbol_ref,label_ref") -+ (match_test "!(TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (op))"))) -+ -+(define_predicate "nds32_nonunspec_symbolic_operand" -+ (and (match_code "const,symbol_ref,label_ref") -+ (match_test "!flag_pic && nds32_const_unspec_p (op) -+ && !(TARGET_ICT_MODEL_LARGE -+ && nds32_indirect_call_referenced_p (op))"))) - - (define_predicate "nds32_reg_constant_operand" - (ior (match_operand 0 "register_operand") -@@ -56,14 +64,51 @@ - (and (match_operand 0 "const_int_operand") - (match_test "satisfies_constraint_Is11 (op)")))) - -+(define_predicate "nds32_imm_0_1_operand" -+ (and (match_operand 0 "const_int_operand") -+ (ior (match_test "satisfies_constraint_Iv00 (op)") -+ (match_test "satisfies_constraint_Iv01 (op)")))) -+ -+(define_predicate "nds32_imm_1_2_operand" -+ (and (match_operand 0 "const_int_operand") -+ (ior (match_test "satisfies_constraint_Iv01 (op)") -+ (match_test "satisfies_constraint_Iv02 (op)")))) -+ -+(define_predicate "nds32_imm_1_2_4_8_operand" -+ (and (match_operand 0 "const_int_operand") -+ (ior (ior (match_test "satisfies_constraint_Iv01 (op)") -+ (match_test "satisfies_constraint_Iv02 (op)")) -+ (ior (match_test "satisfies_constraint_Iv04 (op)") -+ (match_test "satisfies_constraint_Iv08 (op)"))))) -+ -+(define_predicate "nds32_imm2u_operand" -+ (and (match_operand 0 "const_int_operand") -+ (match_test "satisfies_constraint_Iu02 (op)"))) -+ -+(define_predicate "nds32_imm4u_operand" -+ (and (match_operand 0 "const_int_operand") -+ (match_test "satisfies_constraint_Iu04 (op)"))) -+ - (define_predicate "nds32_imm5u_operand" - (and (match_operand 0 "const_int_operand") - (match_test "satisfies_constraint_Iu05 (op)"))) - -+(define_predicate "nds32_imm6u_operand" -+ (and (match_operand 0 "const_int_operand") -+ (match_test "satisfies_constraint_Iu06 (op)"))) -+ -+(define_predicate "nds32_rimm4u_operand" -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "nds32_imm4u_operand"))) -+ - (define_predicate "nds32_rimm5u_operand" - (ior (match_operand 0 "register_operand") - (match_operand 0 "nds32_imm5u_operand"))) - -+(define_predicate "nds32_rimm6u_operand" -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "nds32_imm6u_operand"))) -+ - (define_predicate "nds32_move_operand" - (and (match_operand 0 "general_operand") - (not (match_code "high,const,symbol_ref,label_ref"))) -@@ -78,6 +123,20 @@ - return true; - }) - -+(define_predicate "nds32_vmove_operand" -+ (and (match_operand 0 "general_operand") -+ (not (match_code "high,const,symbol_ref,label_ref"))) -+{ -+ /* If the constant op does NOT satisfy Is20 nor Ihig, -+ we can not perform move behavior by a single instruction. */ -+ if (GET_CODE (op) == CONST_VECTOR -+ && !satisfies_constraint_CVs2 (op) -+ && !satisfies_constraint_CVhi (op)) -+ return false; -+ -+ return true; -+}) -+ - (define_predicate "nds32_and_operand" - (match_operand 0 "nds32_reg_constant_operand") - { -@@ -127,6 +186,15 @@ - (ior (match_operand 0 "nds32_symbolic_operand") - (match_operand 0 "nds32_general_register_operand"))) - -+(define_predicate "nds32_insv_operand" -+ (match_code "const_int") -+{ -+ return INTVAL (op) == 0 -+ || INTVAL (op) == 8 -+ || INTVAL (op) == 16 -+ || INTVAL (op) == 24; -+}) -+ - (define_predicate "nds32_lmw_smw_base_operand" - (and (match_code "mem") - (match_test "nds32_valid_smw_lwm_base_p (op)"))) -diff -urN gcc-8.2.0.orig/gcc/config/nds32/t-elf gcc-8.2.0/gcc/config/nds32/t-elf ---- gcc-8.2.0.orig/gcc/config/nds32/t-elf 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/t-elf 2019-01-25 15:38:32.833242671 +0100 -@@ -0,0 +1,42 @@ -+# The multilib settings of Andes NDS32 cpu for GNU compiler -+# Copyright (C) 2012-2018 Free Software Foundation, Inc. -+# Contributed by Andes Technology Corporation. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published -+# by the Free Software Foundation; either version 3, or (at your -+# option) any later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the -+# driver program which options are defaults for this target and thus -+# do not need to be handled specially. -+MULTILIB_OPTIONS += mcmodel=small/mcmodel=medium/mcmodel=large mvh -+ -+ifneq ($(filter graywolf,$(TM_MULTILIB_CONFIG)),) -+MULTILIB_OPTIONS += mcpu=graywolf -+endif -+ -+ifneq ($(filter dsp,$(TM_MULTILIB_CONFIG)),) -+MULTILIB_OPTIONS += mext-dsp -+endif -+ -+ifneq ($(filter zol,$(TM_MULTILIB_CONFIG)),) -+MULTILIB_OPTIONS += mext-zol -+endif -+ -+ifneq ($(filter v3m+,$(TM_MULTILIB_CONFIG)),) -+MULTILIB_OPTIONS += march=v3m+ -+endif -+ -+# ------------------------------------------------------------------------ -diff -urN gcc-8.2.0.orig/gcc/config/nds32/t-linux gcc-8.2.0/gcc/config/nds32/t-linux ---- gcc-8.2.0.orig/gcc/config/nds32/t-linux 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/config/nds32/t-linux 2019-01-25 15:38:32.833242671 +0100 -@@ -0,0 +1,26 @@ -+# The multilib settings of Andes NDS32 cpu for GNU compiler -+# Copyright (C) 2012-2018 Free Software Foundation, Inc. -+# Contributed by Andes Technology Corporation. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published -+# by the Free Software Foundation; either version 3, or (at your -+# option) any later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the -+# driver program which options are defaults for this target and thus -+# do not need to be handled specially. -+MULTILIB_OPTIONS += -+ -+# ------------------------------------------------------------------------ -diff -urN gcc-8.2.0.orig/gcc/config.gcc gcc-8.2.0/gcc/config.gcc ---- gcc-8.2.0.orig/gcc/config.gcc 2018-06-25 21:34:01.000000000 +0200 -+++ gcc-8.2.0/gcc/config.gcc 2019-01-25 15:38:32.821242637 +0100 -@@ -445,7 +445,17 @@ - ;; - nds32*) - cpu_type=nds32 -- extra_headers="nds32_intrinsic.h" -+ extra_headers="nds32_intrinsic.h nds32_isr.h nds32_init.inc" -+ case ${target} in -+ nds32*-*-linux*) -+ extra_options="${extra_options} nds32/nds32-linux.opt" -+ ;; -+ nds32*-*-elf*) -+ extra_options="${extra_options} nds32/nds32-elf.opt" -+ ;; -+ *) -+ ;; -+ esac - extra_objs="nds32-cost.o nds32-intrinsic.o nds32-isr.o nds32-md-auxiliary.o nds32-pipelines-auxiliary.o nds32-predicates.o nds32-memory-manipulation.o nds32-fp-as-gp.o nds32-relax-opt.o nds32-utils.o" - ;; - nios2-*-*) -@@ -2335,17 +2345,36 @@ - tmake_file="${tmake_file} msp430/t-msp430" - extra_gcc_objs="driver-msp430.o" - ;; --nds32le-*-*) -+nds32*-*-*) - target_cpu_default="0" - tm_defines="${tm_defines}" -- tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} nds32/nds32_intrinsic.h" -- tmake_file="nds32/t-nds32 nds32/t-mlibs" -- ;; --nds32be-*-*) -- target_cpu_default="0|MASK_BIG_ENDIAN" -- tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" -- tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} nds32/nds32_intrinsic.h" -- tmake_file="nds32/t-nds32 nds32/t-mlibs" -+ case ${target} in -+ nds32le*-*-*) -+ ;; -+ nds32be-*-*) -+ target_cpu_default="${target_cpu_default}|MASK_BIG_ENDIAN" -+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" -+ ;; -+ esac -+ case ${target} in -+ nds32*-*-elf*) -+ tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} nds32/elf.h nds32/nds32_intrinsic.h" -+ tmake_file="nds32/t-nds32 nds32/t-elf" -+ ;; -+ nds32*-*-linux*) -+ tm_file="dbxelf.h elfos.h ${tm_file} gnu-user.h linux.h glibc-stdint.h nds32/linux.h nds32/nds32_intrinsic.h" -+ tmake_file="${tmake_file} nds32/t-nds32 nds32/t-linux" -+ ;; -+ esac -+ -+ # Handle --enable-default-relax setting. -+ if test x${enable_default_relax} = xyes; then -+ tm_defines="${tm_defines} TARGET_DEFAULT_RELAX=1" -+ fi -+ # Handle --with-ext-dsp -+ if test x${with_ext_dsp} = xyes; then -+ tm_defines="${tm_defines} TARGET_DEFAULT_EXT_DSP=1" -+ fi - ;; - nios2-*-*) - tm_file="elfos.h ${tm_file}" -@@ -4318,11 +4347,11 @@ - "") - with_cpu=n9 - ;; -- n6 | n7 | n8 | e8 | s8 | n9) -+ n6 | n7 |n8 | e8 | s8 | n9 | n10 | d10 | n12 | n13 | n15) - # OK - ;; - *) -- echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9" 1>&2 -+ echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9 n10 d10 n12 n13 n15" 1>&2 - exit 1 - ;; - esac -@@ -4332,15 +4361,30 @@ - "") - # the default library is newlib - with_nds32_lib=newlib -+ tm_defines="${tm_defines} TARGET_DEFAULT_CTOR_DTOR=1" - ;; - newlib) - # OK -+ tm_defines="${tm_defines} TARGET_DEFAULT_CTOR_DTOR=1" - ;; - mculib) - # OK -+ # for the arch=v3f or arch=v3s under mculib toolchain, -+ # we would like to set -fno-math-errno as default -+ case "${with_arch}" in -+ v3f | v3s) -+ tm_defines="${tm_defines} TARGET_DEFAULT_NO_MATH_ERRNO=1" -+ ;; -+ esac -+ ;; -+ glibc) -+ # OK -+ tm_defines="${tm_defines}" -+ ;; -+ uclibc) - ;; - *) -- echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2 -+ echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib glibc uclibc" 1>&2 - exit 1 - ;; - esac -diff -urN gcc-8.2.0.orig/gcc/configure gcc-8.2.0/gcc/configure ---- gcc-8.2.0.orig/gcc/configure 2018-04-18 11:46:58.000000000 +0200 -+++ gcc-8.2.0/gcc/configure 2019-01-25 15:38:32.837242683 +0100 -@@ -27784,7 +27784,7 @@ - # version to the per-target configury. - case "$cpu_type" in - aarch64 | alpha | arc | arm | avr | bfin | cris | i386 | m32c | m68k \ -- | microblaze | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu \ -+ | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \ - | tilegx | tilepro | visium | xstormy16 | xtensa) - insn="nop" - ;; -diff -urN gcc-8.2.0.orig/gcc/configure.ac gcc-8.2.0/gcc/configure.ac ---- gcc-8.2.0.orig/gcc/configure.ac 2018-04-18 11:46:58.000000000 +0200 -+++ gcc-8.2.0/gcc/configure.ac 2019-01-25 15:38:32.837242683 +0100 -@@ -4910,7 +4910,7 @@ - # version to the per-target configury. - case "$cpu_type" in - aarch64 | alpha | arc | arm | avr | bfin | cris | i386 | m32c | m68k \ -- | microblaze | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu \ -+ | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \ - | tilegx | tilepro | visium | xstormy16 | xtensa) - insn="nop" - ;; -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.c-torture/execute/20010122-1.c gcc-8.2.0/gcc/testsuite/gcc.c-torture/execute/20010122-1.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.c-torture/execute/20010122-1.c 2015-12-10 20:20:14.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.c-torture/execute/20010122-1.c 2019-01-25 15:38:32.837242683 +0100 -@@ -1,4 +1,5 @@ - /* { dg-skip-if "requires frame pointers" { *-*-* } "-fomit-frame-pointer" "" } */ -+/* { dg-additional-options "-malways-save-lp" { target nds32*-*-* } } */ - /* { dg-require-effective-target return_address } */ - - extern void exit (int); -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.dg/lower-subreg-1.c gcc-8.2.0/gcc/testsuite/gcc.dg/lower-subreg-1.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.dg/lower-subreg-1.c 2017-06-17 17:32:28.000000000 +0200 -+++ gcc-8.2.0/gcc/testsuite/gcc.dg/lower-subreg-1.c 2019-01-25 15:38:32.837242683 +0100 -@@ -1,4 +1,4 @@ --/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */ -+/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* nds32*-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */ - /* { dg-options "-O -fdump-rtl-subreg1" } */ - /* { dg-additional-options "-mno-stv" { target ia32 } } */ - /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } } */ -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.dg/stack-usage-1.c gcc-8.2.0/gcc/testsuite/gcc.dg/stack-usage-1.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.dg/stack-usage-1.c 2017-06-17 17:32:28.000000000 +0200 -+++ gcc-8.2.0/gcc/testsuite/gcc.dg/stack-usage-1.c 2019-01-25 15:38:32.837242683 +0100 -@@ -2,6 +2,7 @@ - /* { dg-options "-fstack-usage" } */ - /* nvptx doesn't have a reg allocator, and hence no stack usage data. */ - /* { dg-skip-if "" { nvptx-*-* } } */ -+/* { dg-options "-fstack-usage -fno-omit-frame-pointer" { target { nds32*-*-* } } } */ - - /* This is aimed at testing basic support for -fstack-usage in the back-ends. - See the SPARC back-end for example (grep flag_stack_usage_info in sparc.c). -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isb.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isb.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isb.c 2013-12-03 11:58:05.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isb.c 1970-01-01 01:00:00.000000000 +0100 -@@ -1,11 +0,0 @@ --/* Verify that we generate isb instruction with builtin function. */ -- --/* { dg-do compile } */ --/* { dg-options "-O0" } */ --/* { dg-final { scan-assembler "\\tisb" } } */ -- --void --test (void) --{ -- __builtin_nds32_isb (); --} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isync.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isync.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isync.c 2013-12-03 11:58:05.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isync.c 1970-01-01 01:00:00.000000000 +0100 -@@ -1,12 +0,0 @@ --/* Verify that we generate isync instruction with builtin function. */ -- --/* { dg-do compile } */ --/* { dg-options "-O0" } */ --/* { dg-final { scan-assembler "\\tisync" } } */ -- --void --test (void) --{ -- int *addr = (int *) 0x53000000; -- __builtin_nds32_isync (addr); --} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c 2013-12-03 11:58:05.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c 1970-01-01 01:00:00.000000000 +0100 -@@ -1,17 +0,0 @@ --/* Verify that we generate mfsr/mtsr instruction with builtin function. */ -- --/* { dg-do compile } */ --/* { dg-options "-O0" } */ --/* { dg-final { scan-assembler "\\tmfsr" } } */ --/* { dg-final { scan-assembler "\\tmtsr" } } */ -- --#include -- --void --test (void) --{ -- int ipsw_value; -- -- ipsw_value = __builtin_nds32_mfsr (__NDS32_REG_IPSW__); -- __builtin_nds32_mtsr (ipsw_value, __NDS32_REG_IPSW__); --} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c 2013-12-03 11:58:05.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c 1970-01-01 01:00:00.000000000 +0100 -@@ -1,17 +0,0 @@ --/* Verify that we generate mfusr/mtusr instruction with builtin function. */ -- --/* { dg-do compile } */ --/* { dg-options "-O0" } */ --/* { dg-final { scan-assembler "\\tmfusr" } } */ --/* { dg-final { scan-assembler "\\tmtusr" } } */ -- --#include -- --void --test (void) --{ -- int itype_value; -- -- itype_value = __builtin_nds32_mfusr (__NDS32_REG_ITYPE__); -- __builtin_nds32_mtusr (itype_value, __NDS32_REG_ITYPE__); --} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c 2013-12-03 11:58:05.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c 1970-01-01 01:00:00.000000000 +0100 -@@ -1,11 +0,0 @@ --/* Verify that we generate setgie.d instruction with builtin function. */ -- --/* { dg-do compile } */ --/* { dg-options "-O0" } */ --/* { dg-final { scan-assembler "\\tsetgie.d" } } */ -- --void --test (void) --{ -- __builtin_nds32_setgie_dis (); --} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c 2013-12-03 11:58:05.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c 1970-01-01 01:00:00.000000000 +0100 -@@ -1,11 +0,0 @@ --/* Verify that we generate setgie.e instruction with builtin function. */ -- --/* { dg-do compile } */ --/* { dg-options "-O0" } */ --/* { dg-final { scan-assembler "\\tsetgie.e" } } */ -- --void --test (void) --{ -- __builtin_nds32_setgie_en (); --} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,36 @@ -+/* This is a test program for checking gie with -+ mtsr/mfsr instruction. */ -+ -+/* { dg-do run } */ -+/* { dg-options "-O0" } */ -+ -+#include -+#include -+ -+int -+main () -+{ -+ unsigned int psw; -+ unsigned int gie; -+ unsigned int pfm_ctl; -+ -+ __nds32__setgie_en (); -+ __nds32__dsb(); /* This is needed for waiting pipeline. */ -+ psw = __nds32__mfsr (NDS32_SR_PSW); -+ -+ gie = psw & 0x00000001; -+ -+ if (gie != 1) -+ abort (); -+ -+ psw = psw & 0xFFFFFFFE; -+ __nds32__mtsr (psw,NDS32_SR_PSW); -+ __nds32__dsb(); /* This is needed for waiting pipeline. */ -+ psw = __nds32__mfsr (NDS32_SR_PSW); -+ gie = psw & 0x00000001; -+ -+ if (gie != 0) -+ abort (); -+ else -+ exit (0); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,10 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+void -+main (void) -+{ -+ __nds32__clr_pending_swint (); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,16 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+void -+main (void) -+{ -+ __nds32__clr_pending_hwint (NDS32_INT_H0); -+ __nds32__clr_pending_hwint (NDS32_INT_H1); -+ __nds32__clr_pending_hwint (NDS32_INT_H2); -+ -+ __nds32__clr_pending_hwint (NDS32_INT_H15); -+ __nds32__clr_pending_hwint (NDS32_INT_H16); -+ __nds32__clr_pending_hwint (NDS32_INT_H31); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+void -+main (void) -+{ -+ __nds32__disable_int (NDS32_INT_H15); -+ __nds32__disable_int (NDS32_INT_H16); -+ __nds32__disable_int (NDS32_INT_H31); -+ __nds32__disable_int (NDS32_INT_SWI); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+void -+main (void) -+{ -+ __nds32__enable_int (NDS32_INT_H15); -+ __nds32__enable_int (NDS32_INT_H16); -+ __nds32__enable_int (NDS32_INT_H31); -+ __nds32__enable_int (NDS32_INT_SWI); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,14 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+int -+main (void) -+{ -+ int a = __nds32__get_pending_int (NDS32_INT_H15); -+ int b = __nds32__get_pending_int (NDS32_INT_SWI); -+ int c = __nds32__get_pending_int (NDS32_INT_H16); -+ -+ return a + b + c; -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,14 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+int -+main (void) -+{ -+ int a = __nds32__get_trig_type (NDS32_INT_H0); -+ int b = __nds32__get_trig_type (NDS32_INT_H15); -+ int c = __nds32__get_trig_type (NDS32_INT_H16); -+ int d = __nds32__get_trig_type (NDS32_INT_H31); -+ return a + b + c + d; -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c 2019-01-25 15:38:32.837242683 +0100 -@@ -0,0 +1,11 @@ -+/* Verify that we generate isb instruction with builtin function. */ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O0" } */ -+/* { dg-final { scan-assembler "\\tisb" } } */ -+ -+void -+test (void) -+{ -+ __builtin_nds32_isb (); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,12 @@ -+/* Verify that we generate isync instruction with builtin function. */ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O0" } */ -+/* { dg-final { scan-assembler "\\tisync" } } */ -+ -+void -+test (void) -+{ -+ int *addr = (int *) 0x53000000; -+ __builtin_nds32_isync (addr); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,17 @@ -+/* Verify that we generate mfsr/mtsr instruction with builtin function. */ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O0" } */ -+/* { dg-final { scan-assembler "\\tmfsr" } } */ -+/* { dg-final { scan-assembler "\\tmtsr" } } */ -+ -+#include -+ -+void -+test (void) -+{ -+ int ipsw_value; -+ -+ ipsw_value = __builtin_nds32_mfsr (__NDS32_REG_IPSW__); -+ __builtin_nds32_mtsr (ipsw_value, __NDS32_REG_IPSW__); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,17 @@ -+/* Verify that we generate mfusr/mtusr instruction with builtin function. */ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O0" } */ -+/* { dg-final { scan-assembler "\\tmfusr" } } */ -+/* { dg-final { scan-assembler "\\tmtusr" } } */ -+ -+#include -+ -+void -+test (void) -+{ -+ int itype_value; -+ -+ itype_value = __builtin_nds32_mfusr (__NDS32_REG_ITYPE__); -+ __builtin_nds32_mtusr (itype_value, __NDS32_REG_ITYPE__); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,13 @@ -+/* Verify that we generate setgie.d instruction with builtin function. */ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O0" } */ -+/* { dg-final { scan-assembler "\\tsetgie.d" } } */ -+ -+#include -+ -+void -+test (void) -+{ -+ __nds32__setgie_dis (); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,13 @@ -+/* Verify that we generate setgie.e instruction with builtin function. */ -+ -+/* { dg-do compile */ -+/* { dg-options "-O0" } */ -+/* { dg-final { scan-assembler "\\tsetgie.e" } } */ -+ -+#include -+ -+void -+test (void) -+{ -+ __nds32__setgie_en (); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,10 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+int -+main (void) -+{ -+ __nds32__set_pending_swint (); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+void -+main (void) -+{ -+ __nds32__set_trig_type_edge (NDS32_INT_H0); -+ __nds32__set_trig_type_edge (NDS32_INT_H15); -+ __nds32__set_trig_type_edge (NDS32_INT_H16); -+ __nds32__set_trig_type_edge (NDS32_INT_H31); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ -+ -+#include -+ -+void -+main (void) -+{ -+ __nds32__set_trig_type_level (NDS32_INT_H0); -+ __nds32__set_trig_type_level (NDS32_INT_H15); -+ __nds32__set_trig_type_level (NDS32_INT_H16); -+ __nds32__set_trig_type_level (NDS32_INT_H31); -+} -diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/nds32.exp gcc-8.2.0/gcc/testsuite/gcc.target/nds32/nds32.exp ---- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/nds32.exp 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/nds32.exp 2019-01-25 15:38:32.841242694 +0100 -@@ -38,8 +38,10 @@ - dg-init - - # Main loop. --dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ -+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/compile/*.\[cS\]]] \ - "" $DEFAULT_CFLAGS -+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ -+ "" "" - - # All done. - dg-finish -diff -urN gcc-8.2.0.orig/gcc/testsuite/lib/target-supports.exp gcc-8.2.0/gcc/testsuite/lib/target-supports.exp ---- gcc-8.2.0.orig/gcc/testsuite/lib/target-supports.exp 2018-06-29 00:23:51.000000000 +0200 -+++ gcc-8.2.0/gcc/testsuite/lib/target-supports.exp 2019-01-25 15:38:32.841242694 +0100 -@@ -8783,6 +8783,7 @@ - || [istarget avr*-*-*] - || [istarget crisv32-*-*] || [istarget cris-*-*] - || [istarget mmix-*-*] -+ || [istarget nds32*-*-*] - || [istarget s390*-*-*] - || [istarget powerpc*-*-*] - || [istarget nios2*-*-*] -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/initfini.c gcc-8.2.0/libgcc/config/nds32/initfini.c ---- gcc-8.2.0.orig/libgcc/config/nds32/initfini.c 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/initfini.c 2019-01-25 15:38:32.841242694 +0100 -@@ -25,6 +25,10 @@ - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -+#include -+/* Need header file for `struct object' type. */ -+#include "../libgcc/unwind-dw2-fde.h" -+ - /* Declare a pointer to void function type. */ - typedef void (*func_ptr) (void); - -@@ -42,11 +46,59 @@ - refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__ - symbol in crtinit.o, where they are defined. */ - --static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"))) -- = { (func_ptr) (-1) }; -+static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"), used)) -+ = { (func_ptr) 0 }; -+ -+static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"), used)) -+ = { (func_ptr) 0 }; -+ -+ -+#ifdef SUPPORT_UNWINDING_DWARF2 -+/* Preparation of exception handling with dwar2 mechanism registration. */ -+ -+asm ("\n\ -+ .section .eh_frame,\"aw\",@progbits\n\ -+ .global __EH_FRAME_BEGIN__\n\ -+ .type __EH_FRAME_BEGIN__, @object\n\ -+ .align 2\n\ -+__EH_FRAME_BEGIN__:\n\ -+ ! Beginning location of eh_frame section\n\ -+ .previous\n\ -+"); -+ -+extern func_ptr __EH_FRAME_BEGIN__[]; -+ - --static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"))) -- = { (func_ptr) (-1) }; -+/* Note that the following two functions are going to be chained into -+ constructor and destructor list, repectively. So these two declarations -+ must be placed after __CTOR_LIST__ and __DTOR_LIST. */ -+extern void __nds32_register_eh(void) __attribute__((constructor, used)); -+extern void __nds32_deregister_eh(void) __attribute__((destructor, used)); -+ -+/* Register the exception handling table as the first constructor. */ -+void -+__nds32_register_eh (void) -+{ -+ static struct object object; -+ if (__register_frame_info) -+ __register_frame_info (__EH_FRAME_BEGIN__, &object); -+} -+ -+/* Unregister the exception handling table as a deconstructor. */ -+void -+__nds32_deregister_eh (void) -+{ -+ static int completed = 0; -+ -+ if (completed) -+ return; -+ -+ if (__deregister_frame_info) -+ __deregister_frame_info (__EH_FRAME_BEGIN__); -+ -+ completed = 1; -+} -+#endif - - /* Run all the global destructors on exit from the program. */ - -@@ -63,7 +115,7 @@ - same particular root executable or shared library file. */ - - static void __do_global_dtors (void) --asm ("__do_global_dtors") __attribute__ ((section (".text"))); -+asm ("__do_global_dtors") __attribute__ ((section (".text"), used)); - - static void - __do_global_dtors (void) -@@ -116,23 +168,37 @@ - last, these words naturally end up at the very ends of the two lists - contained in these two sections. */ - --static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"))) -+static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"), used)) - = { (func_ptr) 0 }; - --static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"))) -+static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"), used)) - = { (func_ptr) 0 }; - -+#ifdef SUPPORT_UNWINDING_DWARF2 -+/* ZERO terminator in .eh_frame section. */ -+asm ("\n\ -+ .section .eh_frame,\"aw\",@progbits\n\ -+ .global __EH_FRAME_END__\n\ -+ .type __EH_FRAME_END__, @object\n\ -+ .align 2\n\ -+__EH_FRAME_END__:\n\ -+ ! End location of eh_frame section with ZERO terminator\n\ -+ .word 0\n\ -+ .previous\n\ -+"); -+#endif -+ - /* Run all global constructors for the program. - Note that they are run in reverse order. */ - - static void __do_global_ctors (void) --asm ("__do_global_ctors") __attribute__ ((section (".text"))); -+asm ("__do_global_ctors") __attribute__ ((section (".text"), used)); - - static void - __do_global_ctors (void) - { - func_ptr *p; -- for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--) -+ for (p = __CTOR_END__ - 1; *p; p--) - (*p) (); - } - -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/adj_intr_lvl.inc gcc-8.2.0/libgcc/config/nds32/isr-library/adj_intr_lvl.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/adj_intr_lvl.inc 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/adj_intr_lvl.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -26,13 +26,26 @@ - .macro ADJ_INTR_LVL - #if defined(NDS32_NESTED) /* Nested handler. */ - mfsr $r3, $PSW -+ /* By substracting 1 from $PSW, we can lower PSW.INTL -+ and enable GIE simultaneously. */ - addi $r3, $r3, #-0x1 -+ #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ -+ ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ -+ #endif - mtsr $r3, $PSW - #elif defined(NDS32_NESTED_READY) /* Nested ready handler. */ - /* Save ipc and ipsw and lower INT level. */ - mfsr $r3, $PSW - addi $r3, $r3, #-0x2 -+ #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ -+ ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ -+ #endif - mtsr $r3, $PSW - #else /* Not nested handler. */ -+ #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ -+ mfsr $r3, $PSW -+ ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ -+ mtsr $r3, $PSW -+ #endif - #endif - .endm -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/excp_isr.S gcc-8.2.0/libgcc/config/nds32/isr-library/excp_isr.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/excp_isr.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/excp_isr.S 2019-01-25 15:38:32.841242694 +0100 -@@ -23,6 +23,7 @@ - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -+#include "save_usr_regs.inc" - #include "save_mac_regs.inc" - #include "save_fpu_regs.inc" - #include "save_fpu_regs_00.inc" -@@ -32,35 +33,33 @@ - #include "save_all.inc" - #include "save_partial.inc" - #include "adj_intr_lvl.inc" --#include "restore_mac_regs.inc" - #include "restore_fpu_regs_00.inc" - #include "restore_fpu_regs_01.inc" - #include "restore_fpu_regs_02.inc" - #include "restore_fpu_regs_03.inc" - #include "restore_fpu_regs.inc" -+#include "restore_mac_regs.inc" -+#include "restore_usr_regs.inc" - #include "restore_all.inc" - #include "restore_partial.inc" -+ - .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ - .align 1 --/* -- First Level Handlers -- 1. First Level Handlers are invokded in vector section via jump instruction -- with specific names for different configurations. -- 2. Naming Format: _nds32_e_SR_NT for exception handlers. -- _nds32_i_SR_NT for interrupt handlers. -- 2.1 All upper case letters are replaced with specific lower case letters encodings. -- 2.2 SR: Saved Registers -- sa: Save All regs (context) -- ps: Partial Save (all caller-saved regs) -- 2.3 NT: Nested Type -- ns: nested -- nn: not nested -- nr: nested ready --*/ -- --/* -- This is original 16-byte vector size version. --*/ -+ -+/* First Level Handlers -+ 1. First Level Handlers are invokded in vector section via jump instruction -+ with specific names for different configurations. -+ 2. Naming Format: _nds32_e_SR_NT for exception handlers. -+ _nds32_i_SR_NT for interrupt handlers. -+ 2.1 All upper case letters are replaced with specific lower case letters encodings. -+ 2.2 SR -- Saved Registers -+ sa: Save All regs (context) -+ ps: Partial Save (all caller-saved regs) -+ 2.3 NT -- Nested Type -+ ns: nested -+ nn: not nested -+ nr: nested ready */ -+ - #ifdef NDS32_SAVE_ALL_REGS - #if defined(NDS32_NESTED) - .globl _nds32_e_sa_ns -@@ -91,21 +90,26 @@ - #endif /* endif for Nest Type */ - #endif /* not NDS32_SAVE_ALL_REGS */ - --/* -- This is 16-byte vector size version. -- The vector id was restored into $r0 in vector by compiler. --*/ -+ -+/* For 4-byte vector size version, the vector id is -+ extracted from $ITYPE and is set into $r0 by library. -+ For 16-byte vector size version, the vector id -+ is set into $r0 in vector section by compiler. */ -+ -+/* Save used registers. */ - #ifdef NDS32_SAVE_ALL_REGS - SAVE_ALL - #else - SAVE_PARTIAL - #endif -+ - /* Prepare to call 2nd level handler. */ - la $r2, _nds32_jmptbl_00 - lw $r2, [$r2 + $r0 << #2] - ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ - jral $r2 -- /* Restore used registers. */ -+ -+/* Restore used registers. */ - #ifdef NDS32_SAVE_ALL_REGS - RESTORE_ALL - #else -@@ -113,6 +117,7 @@ - #endif - iret - -+ - #ifdef NDS32_SAVE_ALL_REGS - #if defined(NDS32_NESTED) - .size _nds32_e_sa_ns, .-_nds32_e_sa_ns -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/intr_isr.S gcc-8.2.0/libgcc/config/nds32/isr-library/intr_isr.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/intr_isr.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/intr_isr.S 2019-01-25 15:38:32.841242694 +0100 -@@ -23,6 +23,7 @@ - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -+#include "save_usr_regs.inc" - #include "save_mac_regs.inc" - #include "save_fpu_regs.inc" - #include "save_fpu_regs_00.inc" -@@ -32,35 +33,33 @@ - #include "save_all.inc" - #include "save_partial.inc" - #include "adj_intr_lvl.inc" --#include "restore_mac_regs.inc" - #include "restore_fpu_regs_00.inc" - #include "restore_fpu_regs_01.inc" - #include "restore_fpu_regs_02.inc" - #include "restore_fpu_regs_03.inc" - #include "restore_fpu_regs.inc" -+#include "restore_mac_regs.inc" -+#include "restore_usr_regs.inc" - #include "restore_all.inc" - #include "restore_partial.inc" -+ - .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ - .align 1 --/* -- First Level Handlers -- 1. First Level Handlers are invokded in vector section via jump instruction -- with specific names for different configurations. -- 2. Naming Format: _nds32_e_SR_NT for exception handlers. -- _nds32_i_SR_NT for interrupt handlers. -- 2.1 All upper case letters are replaced with specific lower case letters encodings. -- 2.2 SR: Saved Registers -- sa: Save All regs (context) -- ps: Partial Save (all caller-saved regs) -- 2.3 NT: Nested Type -- ns: nested -- nn: not nested -- nr: nested ready --*/ -- --/* -- This is original 16-byte vector size version. --*/ -+ -+/* First Level Handlers -+ 1. First Level Handlers are invokded in vector section via jump instruction -+ with specific names for different configurations. -+ 2. Naming Format: _nds32_e_SR_NT for exception handlers. -+ _nds32_i_SR_NT for interrupt handlers. -+ 2.1 All upper case letters are replaced with specific lower case letters encodings. -+ 2.2 SR -- Saved Registers -+ sa: Save All regs (context) -+ ps: Partial Save (all caller-saved regs) -+ 2.3 NT -- Nested Type -+ ns: nested -+ nn: not nested -+ nr: nested ready */ -+ - #ifdef NDS32_SAVE_ALL_REGS - #if defined(NDS32_NESTED) - .globl _nds32_i_sa_ns -@@ -91,21 +90,36 @@ - #endif /* endif for Nest Type */ - #endif /* not NDS32_SAVE_ALL_REGS */ - --/* -- This is 16-byte vector size version. -- The vector id was restored into $r0 in vector by compiler. --*/ -+ -+/* For 4-byte vector size version, the vector id is -+ extracted from $ITYPE and is set into $r0 by library. -+ For 16-byte vector size version, the vector id -+ is set into $r0 in vector section by compiler. */ -+ -+/* Save used registers first. */ - #ifdef NDS32_SAVE_ALL_REGS - SAVE_ALL - #else - SAVE_PARTIAL - #endif -- /* Prepare to call 2nd level handler. */ -+ -+/* According to vector size, we need to have different implementation. */ -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* Prepare to call 2nd level handler. */ -+ la $r2, _nds32_jmptbl_00 -+ lw $r2, [$r2 + $r0 << #2] -+ addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */ -+ ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ -+ jral $r2 -+#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ -+ /* Prepare to call 2nd level handler. */ - la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */ - lw $r2, [$r2 + $r0 << #2] - ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ - jral $r2 -- /* Restore used registers. */ -+#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ -+ -+/* Restore used registers. */ - #ifdef NDS32_SAVE_ALL_REGS - RESTORE_ALL - #else -@@ -113,6 +127,7 @@ - #endif - iret - -+ - #ifdef NDS32_SAVE_ALL_REGS - #if defined(NDS32_NESTED) - .size _nds32_i_sa_ns, .-_nds32_i_sa_ns -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/reset.S gcc-8.2.0/libgcc/config/nds32/isr-library/reset.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/reset.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/reset.S 2019-01-25 15:38:32.841242694 +0100 -@@ -26,22 +26,18 @@ - .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ - .align 1 - .weak _SDA_BASE_ /* For reset handler only. */ -- .weak _FP_BASE_ /* For reset handler only. */ - .weak _nds32_init_mem /* User defined memory initialization function. */ - .globl _start - .globl _nds32_reset - .type _nds32_reset, @function - _nds32_reset: - _start: --#ifdef NDS32_EXT_EX9 -- .no_ex9_begin --#endif - /* Handle NMI and warm boot if any of them exists. */ - beqz $sp, 1f /* Reset, NMI or warm boot? */ - /* Either NMI or warm boot; save all regs. */ - - /* Preserve registers for context-switching. */ --#ifdef __NDS32_REDUCED_REGS__ -+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS - /* For 16-reg mode. */ - smw.adm $r0, [$sp], $r10, #0x0 - smw.adm $r15, [$sp], $r15, #0xf -@@ -49,10 +45,9 @@ - /* For 32-reg mode. */ - smw.adm $r0, [$sp], $r27, #0xf - #endif --#ifdef NDS32_EXT_IFC -+#if __NDS32_EXT_IFC__ - mfusr $r1, $IFC_LP -- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep -- stack 8-byte alignment. */ -+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte alignment. */ - #endif - - la $gp, _SDA_BASE_ /* Init GP for small data access. */ -@@ -71,12 +66,11 @@ - bnez $r0, 1f /* If fail to resume, do cold boot. */ - - /* Restore registers for context-switching. */ --#ifdef NDS32_EXT_IFC -- lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep -- stack 8-byte alignment. */ -+#if __NDS32_EXT_IFC__ -+ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep stack 8-byte alignment. */ - mtusr $r1, $IFC_LP - #endif --#ifdef __NDS32_REDUCED_REGS__ -+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS - /* For 16-reg mode. */ - lmw.bim $r15, [$sp], $r15, #0xf - lmw.bim $r0, [$sp], $r10, #0x0 -@@ -88,6 +82,17 @@ - - - 1: /* Cold boot. */ -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* With vector ID feature for v3 architecture, default vector size is 4-byte. */ -+ /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */ -+ mfsr $r0, $IVB -+ li $r1, #0xc000 -+ or $r0, $r0, $r1 -+ xor $r0, $r0, $r1 -+ mtsr $r0, $IVB -+ dsb -+#else -+ /* There is no vector ID feature, so the vector size must be 16-byte. */ - /* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */ - mfsr $r0, $IVB - li $r1, #0xffff3fff -@@ -95,36 +100,54 @@ - ori $r0, $r0, #0x4000 - mtsr $r0, $IVB - dsb -+#endif - - la $gp, _SDA_BASE_ /* Init $gp. */ -- la $fp, _FP_BASE_ /* Init $fp. */ - la $sp, _stack /* Init $sp. */ --#ifdef NDS32_EXT_EX9 --/* -- * Initialize the table base of EX9 instruction -- * ex9 generation needs to disable before the ITB is set -- */ -- mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */ -+ -+#if __NDS32_EXT_EX9__ -+.L_init_itb: -+ /* Initialization for Instruction Table Base (ITB). -+ The symbol _ITB_BASE_ is determined by Linker. -+ Set $ITB only if MSC_CFG.EIT (cr4.b'24) is set. */ -+ mfsr $r0, $MSC_CFG - srli $r0, $r0, 24 - andi $r0, $r0, 0x1 -- beqz $r0, 4f /* Zero means HW does not support EX9. */ -- la $r0, _ITB_BASE_ /* Init $ITB. */ -+ beqz $r0, 4f /* Fall through ? */ -+ la $r0, _ITB_BASE_ - mtusr $r0, $ITB -- .no_ex9_end - 4: - #endif -- la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem -- may written by C language. */ -+ -+#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__ -+.L_init_fpu: -+ /* Initialize FPU -+ Set FUCOP_CTL.CP0EN (fucpr.b'0). */ -+ mfsr $r0, $FUCOP_CTL -+ ori $r0, $r0, 0x1 -+ mtsr $r0, $FUCOP_CTL -+ dsb -+ /* According to [bugzilla #9425], set flush-to-zero mode. -+ That is, set $FPCSR.DNZ(b'12) = 1. */ -+ FMFCSR $r0 -+ ori $r0, $r0, 0x1000 -+ FMTCSR $r0 -+ dsb -+#endif -+ -+ /* Call DRAM init. _nds32_init_mem may written by C language. */ -+ la $r15, _nds32_init_mem - beqz $r15, 6f - jral $r15 - 6: - l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */ - jral $r15 --/* Reset handler() should never return in a RTOS or non-OS system. -- In case it does return, an exception will be generated. -- This exception will be caught either by default break handler or by EDM. -- Default break handle may just do an infinite loop. -- EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ -+ -+ /* Reset handler() should never return in a RTOS or non-OS system. -+ In case it does return, an exception will be generated. -+ This exception will be caught either by default break handler or by EDM. -+ Default break handle may just do an infinite loop. -+ EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ - 5: - break #0x7fff - .size _nds32_reset, .-_nds32_reset -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_all.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_all.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_all.inc 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_all.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -31,15 +31,11 @@ - mtsr $r2, $IPSW - RESTORE_FPU_REGS - RESTORE_MAC_REGS --#ifdef NDS32_EXT_IFC -- lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep -- stack 8-byte alignment. */ -- mtusr $r1, $IFC_LP --#endif --#ifdef __NDS32_REDUCED_REGS__ -+ RESTORE_USR_REGS -+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS - lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */ - lmw.bim $r15, [$sp], $r15, #0xf --#else /* not __NDS32_REDUCED_REGS__ */ -+#else - lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */ - #endif - .endm -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_mac_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_mac_regs.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_mac_regs.inc 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_mac_regs.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -24,7 +24,7 @@ - . */ - - .macro RESTORE_MAC_REGS --#ifdef NDS32_DX_REGS -+#if __NDS32_DX_REGS__ - lmw.bim $r1, [$sp], $r4, #0x0 - mtusr $r1, $d0.lo - mtusr $r2, $d0.hi -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_partial.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_partial.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_partial.inc 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_partial.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -31,15 +31,11 @@ - mtsr $r1, $IPC /* Set IPC. */ - mtsr $r2, $IPSW /* Set IPSW. */ - #endif -- RESTORE_FPU_REGS -- RESTORE_MAC_REGS --#ifdef NDS32_EXT_IFC -- lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep -- stack 8-byte alignment. */ -- mtusr $r1, $IFC_LP --#endif -+ RESTORE_FPU_REGS -+ RESTORE_MAC_REGS -+ RESTORE_USR_REGS - lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */ --#ifdef __NDS32_REDUCED_REGS__ -+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS - lmw.bim $r15, [$sp], $r15, #0x2 - #else - lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */ -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_usr_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_usr_regs.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_usr_regs.inc 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_usr_regs.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,42 @@ -+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler -+ Copyright (C) 2012-2018 Free Software Foundation, Inc. -+ Contributed by Andes Technology Corporation. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+.macro RESTORE_USR_REGS -+#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) -+ lmw.bim $r1, [$sp], $r4, #0x0 -+ mtusr $r1, $IFC_LP -+ mtusr $r2, $LB -+ mtusr $r3, $LE -+ mtusr $r4, $LC -+#elif __NDS32_EXT_IFC__ -+ lmw.bim $r1, [$sp], $r2, #0x0 -+ mtusr $r1, $IFC_LP -+#elif __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ -+ lmw.bim $r1, [$sp], $r4, #0x0 -+ mtusr $r1, $LB -+ mtusr $r2, $LE -+ mtusr $r3, $LC -+#endif -+.endm -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_all.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_all.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_all.inc 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_all.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -23,45 +23,42 @@ - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - --.macro SAVE_ALL_4B --#ifdef __NDS32_REDUCED_REGS__ -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ -+/* If vector size is 4-byte, we have to save registers -+ in the macro implementation. */ -+.macro SAVE_ALL -+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS - smw.adm $r15, [$sp], $r15, #0xf - smw.adm $r0, [$sp], $r10, #0x0 --#else /* not __NDS32_REDUCED_REGS__ */ -+#else - smw.adm $r0, [$sp], $r27, #0xf --#endif /* not __NDS32_REDUCED_REGS__ */ --#ifdef NDS32_EXT_IFC -- mfusr $r1, $IFC_LP -- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep -- stack 8-byte alignment. */ - #endif -- SAVE_MAC_REGS -- SAVE_FPU_REGS -+ SAVE_USR_REGS -+ SAVE_MAC_REGS -+ SAVE_FPU_REGS - mfsr $r1, $IPC /* Get IPC. */ - mfsr $r2, $IPSW /* Get IPSW. */ - smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ - move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ - mfsr $r0, $ITYPE /* Get VID to $r0. */ - srli $r0, $r0, #5 --#ifdef __NDS32_ISA_V2__ - andi $r0, $r0, #127 --#else -- fexti33 $r0, #6 --#endif - .endm - -+#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ -+ -+/* If vector size is 16-byte, some works can be done in -+ the vector section generated by compiler, so that we -+ can implement less in the macro. */ - .macro SAVE_ALL --/* SAVE_REG_TBL code has been moved to -- vector table generated by compiler. */ --#ifdef NDS32_EXT_IFC -- mfusr $r1, $IFC_LP -- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep -- stack 8-byte alignment. */ --#endif -- SAVE_MAC_REGS -- SAVE_FPU_REGS -+ SAVE_USR_REGS -+ SAVE_MAC_REGS -+ SAVE_FPU_REGS - mfsr $r1, $IPC /* Get IPC. */ - mfsr $r2, $IPSW /* Get IPSW. */ - smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ - move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ - .endm -+ -+#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_mac_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_mac_regs.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_mac_regs.inc 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_mac_regs.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -24,7 +24,7 @@ - . */ - - .macro SAVE_MAC_REGS --#ifdef NDS32_DX_REGS -+#if __NDS32_DX_REGS__ - mfusr $r1, $d0.lo - mfusr $r2, $d0.hi - mfusr $r3, $d1.lo -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_partial.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_partial.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_partial.inc 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_partial.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -23,20 +23,20 @@ - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - --.macro SAVE_PARTIAL_4B --#ifdef __NDS32_REDUCED_REGS__ -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ -+/* If vector size is 4-byte, we have to save registers -+ in the macro implementation. */ -+.macro SAVE_PARTIAL -+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS - smw.adm $r15, [$sp], $r15, #0x2 --#else /* not __NDS32_REDUCED_REGS__ */ -+#else - smw.adm $r15, [$sp], $r27, #0x2 --#endif /* not __NDS32_REDUCED_REGS__ */ -- smw.adm $r0, [$sp], $r5, #0x0 --#ifdef NDS32_EXT_IFC -- mfusr $r1, $IFC_LP -- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep -- stack 8-byte alignment. */ - #endif -- SAVE_MAC_REGS -- SAVE_FPU_REGS -+ smw.adm $r0, [$sp], $r5, #0x0 -+ SAVE_USR_REGS -+ SAVE_MAC_REGS -+ SAVE_FPU_REGS - #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) - mfsr $r1, $IPC /* Get IPC. */ - mfsr $r2, $IPSW /* Get IPSW. */ -@@ -44,26 +44,24 @@ - #endif - mfsr $r0, $ITYPE /* Get VID to $r0. */ - srli $r0, $r0, #5 --#ifdef __NDS32_ISA_V2__ - andi $r0, $r0, #127 --#else -- fexti33 $r0, #6 --#endif - .endm - -+#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ -+ -+/* If vector size is 16-byte, some works can be done in -+ the vector section generated by compiler, so that we -+ can implement less in the macro. */ -+ - .macro SAVE_PARTIAL --/* SAVE_CALLER_REGS code has been moved to -- vector table generated by compiler. */ --#ifdef NDS32_EXT_IFC -- mfusr $r1, $IFC_LP -- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep -- stack 8-byte alignment. */ --#endif -- SAVE_MAC_REGS -- SAVE_FPU_REGS -+ SAVE_USR_REGS -+ SAVE_MAC_REGS -+ SAVE_FPU_REGS - #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) - mfsr $r1, $IPC /* Get IPC. */ - mfsr $r2, $IPSW /* Get IPSW. */ - smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ - #endif - .endm -+ -+#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_usr_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_usr_regs.inc ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_usr_regs.inc 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_usr_regs.inc 2019-01-25 15:38:32.841242694 +0100 -@@ -0,0 +1,44 @@ -+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler -+ Copyright (C) 2012-2018 Free Software Foundation, Inc. -+ Contributed by Andes Technology Corporation. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+.macro SAVE_USR_REGS -+/* Store User Special Registers according to supported ISA extension -+ !!! WATCH OUT !!! Take care of 8-byte alignment issue. */ -+#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) -+ mfusr $r1, $IFC_LP -+ mfusr $r2, $LB -+ mfusr $r3, $LE -+ mfusr $r4, $LC -+ smw.adm $r1, [$sp], $r4, #0x0 /* Save even. Ok! */ -+#elif __NDS32_EXT_IFC__ -+ mfusr $r1, $IFC_LP -+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte aligned. */ -+#elif (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) -+ mfusr $r1, $LB -+ mfusr $r2, $LE -+ mfusr $r3, $LC -+ smw.adm $r1, [$sp], $r4, #0x0 /* Save extra $r4 to keep stack 8-byte aligned. */ -+#endif -+.endm -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid00.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid00.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid00.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid00.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.00, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_00 - .type _nds32_vector_00, @function - _nds32_vector_00: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid01.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid01.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid01.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid01.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.01, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_01 - .type _nds32_vector_01, @function - _nds32_vector_01: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid02.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid02.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid02.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid02.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.02, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_02 - .type _nds32_vector_02, @function - _nds32_vector_02: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid03.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid03.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid03.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid03.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.03, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_03 - .type _nds32_vector_03, @function - _nds32_vector_03: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid04.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid04.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid04.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid04.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.04, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_04 - .type _nds32_vector_04, @function - _nds32_vector_04: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid05.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid05.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid05.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid05.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.05, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_05 - .type _nds32_vector_05, @function - _nds32_vector_05: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid06.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid06.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid06.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid06.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.06, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_06 - .type _nds32_vector_06, @function - _nds32_vector_06: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid07.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid07.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid07.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid07.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.07, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_07 - .type _nds32_vector_07, @function - _nds32_vector_07: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid08.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid08.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid08.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid08.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.08, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_08 - .type _nds32_vector_08, @function - _nds32_vector_08: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid09.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid09.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid09.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid09.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.09, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_09 - .type _nds32_vector_09, @function - _nds32_vector_09: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid10.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid10.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid10.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid10.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.10, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_10 - .type _nds32_vector_10, @function - _nds32_vector_10: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid11.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid11.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid11.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid11.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.11, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_11 - .type _nds32_vector_11, @function - _nds32_vector_11: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid12.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid12.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid12.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid12.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.12, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_12 - .type _nds32_vector_12, @function - _nds32_vector_12: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid13.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid13.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid13.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid13.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.13, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_13 - .type _nds32_vector_13, @function - _nds32_vector_13: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid14.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid14.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid14.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid14.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.14, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_14 - .type _nds32_vector_14, @function - _nds32_vector_14: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid15.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid15.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid15.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid15.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.15, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_15 - .type _nds32_vector_15, @function - _nds32_vector_15: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid16.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid16.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid16.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid16.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.16, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_16 - .type _nds32_vector_16, @function - _nds32_vector_16: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid17.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid17.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid17.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid17.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.17, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_17 - .type _nds32_vector_17, @function - _nds32_vector_17: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid18.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid18.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid18.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid18.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.18, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_18 - .type _nds32_vector_18, @function - _nds32_vector_18: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid19.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid19.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid19.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid19.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.19, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_19 - .type _nds32_vector_19, @function - _nds32_vector_19: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid20.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid20.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid20.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid20.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.20, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_20 - .type _nds32_vector_20, @function - _nds32_vector_20: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid21.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid21.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid21.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid21.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.21, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_21 - .type _nds32_vector_21, @function - _nds32_vector_21: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid22.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid22.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid22.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid22.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.22, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_22 - .type _nds32_vector_22, @function - _nds32_vector_22: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid23.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid23.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid23.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid23.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.23, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_23 - .type _nds32_vector_23, @function - _nds32_vector_23: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid24.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid24.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid24.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid24.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.24, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_24 - .type _nds32_vector_24, @function - _nds32_vector_24: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid25.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid25.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid25.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid25.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.25, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_25 - .type _nds32_vector_25, @function - _nds32_vector_25: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid26.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid26.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid26.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid26.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.26, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_26 - .type _nds32_vector_26, @function - _nds32_vector_26: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid27.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid27.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid27.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid27.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.27, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_27 - .type _nds32_vector_27, @function - _nds32_vector_27: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid28.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid28.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid28.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid28.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.28, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_28 - .type _nds32_vector_28, @function - _nds32_vector_28: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid29.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid29.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid29.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid29.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.29, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_29 - .type _nds32_vector_29, @function - _nds32_vector_29: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid30.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid30.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid30.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid30.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.30, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_30 - .type _nds32_vector_30, @function - _nds32_vector_30: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid31.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid31.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid31.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid31.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.31, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_31 - .type _nds32_vector_31, @function - _nds32_vector_31: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid32.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid32.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid32.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid32.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.32, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_32 - .type _nds32_vector_32, @function - _nds32_vector_32: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid33.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid33.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid33.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid33.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.33, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_33 - .type _nds32_vector_33, @function - _nds32_vector_33: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid34.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid34.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid34.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid34.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.34, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_34 - .type _nds32_vector_34, @function - _nds32_vector_34: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid35.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid35.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid35.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid35.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.35, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_35 - .type _nds32_vector_35, @function - _nds32_vector_35: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid36.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid36.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid36.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid36.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.36, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_36 - .type _nds32_vector_36, @function - _nds32_vector_36: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid37.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid37.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid37.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid37.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.37, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_37 - .type _nds32_vector_37, @function - _nds32_vector_37: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid38.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid38.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid38.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid38.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.38, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_38 - .type _nds32_vector_38, @function - _nds32_vector_38: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid39.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid39.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid39.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid39.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.39, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_39 - .type _nds32_vector_39, @function - _nds32_vector_39: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid40.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid40.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid40.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid40.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.40, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_40 - .type _nds32_vector_40, @function - _nds32_vector_40: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid41.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid41.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid41.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid41.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.41, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_41 - .type _nds32_vector_41, @function - _nds32_vector_41: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid42.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid42.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid42.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid42.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.42, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_42 - .type _nds32_vector_42, @function - _nds32_vector_42: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid43.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid43.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid43.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid43.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.43, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_43 - .type _nds32_vector_43, @function - _nds32_vector_43: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid44.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid44.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid44.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid44.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.44, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_44 - .type _nds32_vector_44, @function - _nds32_vector_44: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid45.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid45.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid45.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid45.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.45, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_45 - .type _nds32_vector_45, @function - _nds32_vector_45: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid46.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid46.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid46.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid46.S 2019-01-25 15:38:32.841242694 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.46, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_46 - .type _nds32_vector_46, @function - _nds32_vector_46: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid47.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid47.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid47.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid47.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.47, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_47 - .type _nds32_vector_47, @function - _nds32_vector_47: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid48.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid48.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid48.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid48.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.48, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_48 - .type _nds32_vector_48, @function - _nds32_vector_48: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid49.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid49.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid49.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid49.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.49, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_49 - .type _nds32_vector_49, @function - _nds32_vector_49: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid50.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid50.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid50.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid50.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.50, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_50 - .type _nds32_vector_50, @function - _nds32_vector_50: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid51.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid51.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid51.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid51.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.51, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_51 - .type _nds32_vector_51, @function - _nds32_vector_51: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid52.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid52.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid52.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid52.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.52, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_52 - .type _nds32_vector_52, @function - _nds32_vector_52: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid53.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid53.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid53.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid53.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.53, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_53 - .type _nds32_vector_53, @function - _nds32_vector_53: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid54.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid54.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid54.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid54.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.54, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_54 - .type _nds32_vector_54, @function - _nds32_vector_54: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid55.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid55.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid55.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid55.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.55, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_55 - .type _nds32_vector_55, @function - _nds32_vector_55: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid56.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid56.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid56.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid56.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.56, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_56 - .type _nds32_vector_56, @function - _nds32_vector_56: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid57.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid57.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid57.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid57.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.57, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_57 - .type _nds32_vector_57, @function - _nds32_vector_57: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid58.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid58.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid58.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid58.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.58, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_58 - .type _nds32_vector_58, @function - _nds32_vector_58: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid59.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid59.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid59.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid59.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.59, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_59 - .type _nds32_vector_59, @function - _nds32_vector_59: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid60.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid60.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid60.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid60.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.60, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_60 - .type _nds32_vector_60, @function - _nds32_vector_60: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid61.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid61.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid61.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid61.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.61, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_61 - .type _nds32_vector_61, @function - _nds32_vector_61: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid62.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid62.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid62.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid62.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.62, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_62 - .type _nds32_vector_62, @function - _nds32_vector_62: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid63.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid63.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid63.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid63.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.63, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_63 - .type _nds32_vector_63, @function - _nds32_vector_63: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid64.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid64.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid64.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid64.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.64, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_64 - .type _nds32_vector_64, @function - _nds32_vector_64: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid65.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid65.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid65.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid65.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.65, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_65 - .type _nds32_vector_65, @function - _nds32_vector_65: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid66.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid66.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid66.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid66.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.66, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_66 - .type _nds32_vector_66, @function - _nds32_vector_66: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid67.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid67.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid67.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid67.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.67, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_67 - .type _nds32_vector_67, @function - _nds32_vector_67: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid68.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid68.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid68.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid68.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.68, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_68 - .type _nds32_vector_68, @function - _nds32_vector_68: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid69.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid69.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid69.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid69.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.69, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_69 - .type _nds32_vector_69, @function - _nds32_vector_69: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid70.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid70.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid70.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid70.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.70, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_70 - .type _nds32_vector_70, @function - _nds32_vector_70: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid71.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid71.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid71.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid71.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.71, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_71 - .type _nds32_vector_71, @function - _nds32_vector_71: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid72.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid72.S ---- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid72.S 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid72.S 2019-01-25 15:38:32.845242705 +0100 -@@ -24,8 +24,15 @@ - . */ - - .section .nds32_vector.72, "ax" -+#if __NDS32_ISR_VECTOR_SIZE_4__ -+ /* The vector size is default 4-byte for v3 architecture. */ -+ .vec_size 4 -+ .align 2 -+#else -+ /* The vector size is default 16-byte for other architectures. */ - .vec_size 16 - .align 4 -+#endif - .weak _nds32_vector_72 - .type _nds32_vector_72, @function - _nds32_vector_72: -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/linux-atomic.c gcc-8.2.0/libgcc/config/nds32/linux-atomic.c ---- gcc-8.2.0.orig/libgcc/config/nds32/linux-atomic.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/linux-atomic.c 2019-01-25 15:38:32.845242705 +0100 -@@ -0,0 +1,282 @@ -+/* Linux-specific atomic operations for NDS32 Linux. -+ Copyright (C) 2012-2018 Free Software Foundation, Inc. -+ -+This file is free software; you can redistribute it and/or modify it -+under the terms of the GNU General Public License as published by the -+Free Software Foundation; either version 3, or (at your option) any -+later version. -+ -+This file is distributed in the hope that it will be useful, but -+WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+General Public License for more details. -+ -+Under Section 7 of GPL version 3, you are granted additional -+permissions described in the GCC Runtime Library Exception, version -+3.1, as published by the Free Software Foundation. -+ -+You should have received a copy of the GNU General Public License and -+a copy of the GCC Runtime Library Exception along with this program; -+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+. */ -+ -+/* We implement byte, short and int versions of each atomic operation -+ using the kernel helper defined below. There is no support for -+ 64-bit operations yet. */ -+ -+/* This function copy form NDS32 Linux-kernal. */ -+static inline int -+__kernel_cmpxchg (int oldval, int newval, int *mem) -+{ -+ int temp1, temp2, temp3, offset; -+ -+ asm volatile ("msync\tall\n" -+ "movi\t%0, #0\n" -+ "1:\n" -+ "\tllw\t%1, [%4+%0]\n" -+ "\tsub\t%3, %1, %6\n" -+ "\tcmovz\t%2, %5, %3\n" -+ "\tcmovn\t%2, %1, %3\n" -+ "\tscw\t%2, [%4+%0]\n" -+ "\tbeqz\t%2, 1b\n" -+ : "=&r" (offset), "=&r" (temp3), "=&r" (temp2), "=&r" (temp1) -+ : "r" (mem), "r" (newval), "r" (oldval) : "memory"); -+ -+ return temp1; -+} -+ -+#define HIDDEN __attribute__ ((visibility ("hidden"))) -+ -+#ifdef __NDS32_EL__ -+#define INVERT_MASK_1 0 -+#define INVERT_MASK_2 0 -+#else -+#define INVERT_MASK_1 24 -+#define INVERT_MASK_2 16 -+#endif -+ -+#define MASK_1 0xffu -+#define MASK_2 0xffffu -+ -+#define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP) \ -+ int HIDDEN \ -+ __sync_fetch_and_##OP##_4 (int *ptr, int val) \ -+ { \ -+ int failure, tmp; \ -+ \ -+ do { \ -+ tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \ -+ failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \ -+ } while (failure != 0); \ -+ \ -+ return tmp; \ -+ } -+ -+FETCH_AND_OP_WORD (add, , +) -+FETCH_AND_OP_WORD (sub, , -) -+FETCH_AND_OP_WORD (or, , |) -+FETCH_AND_OP_WORD (and, , &) -+FETCH_AND_OP_WORD (xor, , ^) -+FETCH_AND_OP_WORD (nand, ~, &) -+ -+#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH -+#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH -+ -+/* Implement both __sync__and_fetch and __sync_fetch_and_ for -+ subword-sized quantities. */ -+ -+#define SUBWORD_SYNC_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH, RETURN) \ -+ TYPE HIDDEN \ -+ NAME##_##RETURN (OP, WIDTH) (TYPE *ptr, TYPE val) \ -+ { \ -+ int *wordptr = (int *) ((unsigned long) ptr & ~3); \ -+ unsigned int mask, shift, oldval, newval; \ -+ int failure; \ -+ \ -+ shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ -+ mask = MASK_##WIDTH << shift; \ -+ \ -+ do { \ -+ oldval = __atomic_load_n (wordptr, __ATOMIC_SEQ_CST); \ -+ newval = ((PFX_OP (((oldval & mask) >> shift) \ -+ INF_OP (unsigned int) val)) << shift) & mask; \ -+ newval |= oldval & ~mask; \ -+ failure = __kernel_cmpxchg (oldval, newval, wordptr); \ -+ } while (failure != 0); \ -+ \ -+ return (RETURN & mask) >> shift; \ -+ } -+ -+ -+SUBWORD_SYNC_OP (add, , +, unsigned short, 2, oldval) -+SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, oldval) -+SUBWORD_SYNC_OP (or, , |, unsigned short, 2, oldval) -+SUBWORD_SYNC_OP (and, , &, unsigned short, 2, oldval) -+SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, oldval) -+SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, oldval) -+ -+SUBWORD_SYNC_OP (add, , +, unsigned char, 1, oldval) -+SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, oldval) -+SUBWORD_SYNC_OP (or, , |, unsigned char, 1, oldval) -+SUBWORD_SYNC_OP (and, , &, unsigned char, 1, oldval) -+SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, oldval) -+SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, oldval) -+ -+#define OP_AND_FETCH_WORD(OP, PFX_OP, INF_OP) \ -+ int HIDDEN \ -+ __sync_##OP##_and_fetch_4 (int *ptr, int val) \ -+ { \ -+ int tmp, failure; \ -+ \ -+ do { \ -+ tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \ -+ failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \ -+ } while (failure != 0); \ -+ \ -+ return PFX_OP (tmp INF_OP val); \ -+ } -+ -+OP_AND_FETCH_WORD (add, , +) -+OP_AND_FETCH_WORD (sub, , -) -+OP_AND_FETCH_WORD (or, , |) -+OP_AND_FETCH_WORD (and, , &) -+OP_AND_FETCH_WORD (xor, , ^) -+OP_AND_FETCH_WORD (nand, ~, &) -+ -+SUBWORD_SYNC_OP (add, , +, unsigned short, 2, newval) -+SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, newval) -+SUBWORD_SYNC_OP (or, , |, unsigned short, 2, newval) -+SUBWORD_SYNC_OP (and, , &, unsigned short, 2, newval) -+SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, newval) -+SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, newval) -+ -+SUBWORD_SYNC_OP (add, , +, unsigned char, 1, newval) -+SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, newval) -+SUBWORD_SYNC_OP (or, , |, unsigned char, 1, newval) -+SUBWORD_SYNC_OP (and, , &, unsigned char, 1, newval) -+SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, newval) -+SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, newval) -+ -+int HIDDEN -+__sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval) -+{ -+ int actual_oldval, fail; -+ -+ while (1) -+ { -+ actual_oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); -+ -+ if (oldval != actual_oldval) -+ return actual_oldval; -+ -+ fail = __kernel_cmpxchg (actual_oldval, newval, ptr); -+ -+ if (!fail) -+ return oldval; -+ } -+} -+ -+#define SUBWORD_VAL_CAS(TYPE, WIDTH) \ -+ TYPE HIDDEN \ -+ __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ -+ TYPE newval) \ -+ { \ -+ int *wordptr = (int *)((unsigned long) ptr & ~3), fail; \ -+ unsigned int mask, shift, actual_oldval, actual_newval; \ -+ \ -+ shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ -+ mask = MASK_##WIDTH << shift; \ -+ \ -+ while (1) \ -+ { \ -+ actual_oldval = __atomic_load_n (wordptr, __ATOMIC_SEQ_CST); \ -+ \ -+ if (((actual_oldval & mask) >> shift) != (unsigned int) oldval) \ -+ return (actual_oldval & mask) >> shift; \ -+ \ -+ actual_newval = (actual_oldval & ~mask) \ -+ | (((unsigned int) newval << shift) & mask); \ -+ \ -+ fail = __kernel_cmpxchg (actual_oldval, actual_newval, \ -+ wordptr); \ -+ \ -+ if (!fail) \ -+ return oldval; \ -+ } \ -+ } -+ -+SUBWORD_VAL_CAS (unsigned short, 2) -+SUBWORD_VAL_CAS (unsigned char, 1) -+ -+typedef unsigned char bool; -+ -+bool HIDDEN -+__sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval) -+{ -+ int failure = __kernel_cmpxchg (oldval, newval, ptr); -+ return (failure == 0); -+} -+ -+#define SUBWORD_BOOL_CAS(TYPE, WIDTH) \ -+ bool HIDDEN \ -+ __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ -+ TYPE newval) \ -+ { \ -+ TYPE actual_oldval \ -+ = __sync_val_compare_and_swap_##WIDTH (ptr, oldval, newval); \ -+ return (oldval == actual_oldval); \ -+ } -+ -+SUBWORD_BOOL_CAS (unsigned short, 2) -+SUBWORD_BOOL_CAS (unsigned char, 1) -+ -+int HIDDEN -+__sync_lock_test_and_set_4 (int *ptr, int val) -+{ -+ int failure, oldval; -+ -+ do { -+ oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); -+ failure = __kernel_cmpxchg (oldval, val, ptr); -+ } while (failure != 0); -+ -+ return oldval; -+} -+ -+#define SUBWORD_TEST_AND_SET(TYPE, WIDTH) \ -+ TYPE HIDDEN \ -+ __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val) \ -+ { \ -+ int failure; \ -+ unsigned int oldval, newval, shift, mask; \ -+ int *wordptr = (int *) ((unsigned long) ptr & ~3); \ -+ \ -+ shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ -+ mask = MASK_##WIDTH << shift; \ -+ \ -+ do { \ -+ oldval = __atomic_load_n (wordptr, __ATOMIC_SEQ_CST); \ -+ newval = (oldval & ~mask) \ -+ | (((unsigned int) val << shift) & mask); \ -+ failure = __kernel_cmpxchg (oldval, newval, wordptr); \ -+ } while (failure != 0); \ -+ \ -+ return (oldval & mask) >> shift; \ -+ } -+ -+SUBWORD_TEST_AND_SET (unsigned short, 2) -+SUBWORD_TEST_AND_SET (unsigned char, 1) -+ -+#define SYNC_LOCK_RELEASE(TYPE, WIDTH) \ -+ void HIDDEN \ -+ __sync_lock_release_##WIDTH (TYPE *ptr) \ -+ { \ -+ /* All writes before this point must be seen before we release \ -+ the lock itself. */ \ -+ __builtin_nds32_msync_all (); \ -+ *ptr = 0; \ -+ } -+ -+SYNC_LOCK_RELEASE (int, 4) -+SYNC_LOCK_RELEASE (short, 2) -+SYNC_LOCK_RELEASE (char, 1) -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/linux-unwind.h gcc-8.2.0/libgcc/config/nds32/linux-unwind.h ---- gcc-8.2.0.orig/libgcc/config/nds32/linux-unwind.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/linux-unwind.h 2019-01-25 15:38:32.845242705 +0100 -@@ -0,0 +1,143 @@ -+/* DWARF2 EH unwinding support for NDS32 Linux signal frame. -+ Copyright (C) 2014-2015 Free Software Foundation, Inc. -+ Contributed by Andes Technology Corporation. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+#ifndef inhibit_libc -+ -+/* Do code reading to identify a signal frame, and set the frame -+ state data appropriately. See unwind-dw2.c for the structs. -+ The corresponding bits in the Linux kernel are in -+ arch/nds32/kernel/signal.c. */ -+ -+#include -+#include -+#include -+ -+/* Exactly the same layout as the kernel structures, unique names. */ -+ -+/* arch/nds32/kernel/signal.c */ -+struct _rt_sigframe { -+ siginfo_t info; -+ struct ucontext_t uc; -+}; -+ -+#define RT_SIGRETURN 0x8b00f044 -+ -+#define MD_FALLBACK_FRAME_STATE_FOR nds32_fallback_frame_state -+ -+/* This function is supposed to be invoked by uw_frame_state_for() -+ when there is no unwind data available. -+ -+ Generally, given the _Unwind_Context CONTEXT for a stack frame, -+ we need to look up its caller and decode information into FS. -+ However, if the exception handling happens within a signal handler, -+ the return address of signal handler is a special module, which -+ contains signal return syscall and has no FDE in the .eh_frame section. -+ We need to implement MD_FALLBACK_FRAME_STATE_FOR so that we can -+ unwind through signal frames. */ -+static _Unwind_Reason_Code -+nds32_fallback_frame_state (struct _Unwind_Context *context, -+ _Unwind_FrameState *fs) -+{ -+ u_int32_t *pc = (u_int32_t *) context->ra; -+ struct sigcontext *sc_; -+ _Unwind_Ptr new_cfa; -+ -+#ifdef __NDS32_EB__ -+#error "Signal handler is not supported for force unwind." -+#endif -+ -+ if ((_Unwind_Ptr) pc & 3) -+ return _URC_END_OF_STACK; -+ -+ /* Check if we are going through a signal handler. -+ See arch/nds32/kernel/signal.c implementation. -+ FIXME: Currently we only handle little endian (EL) case. */ -+ if (pc[0] == RT_SIGRETURN) -+ { -+ /* Using '_sigfame' memory address to locate kernal's sigcontext. -+ The sigcontext structures in arch/nds32/include/asm/sigcontext.h. */ -+ struct _rt_sigframe *rt_; -+ rt_ = context->cfa; -+ sc_ = &rt_->uc.uc_mcontext; -+ } -+ else -+ return _URC_END_OF_STACK; -+ -+ /* Update cfa from sigcontext. */ -+ new_cfa = (_Unwind_Ptr) sc_; -+ fs->regs.cfa_how = CFA_REG_OFFSET; -+ fs->regs.cfa_reg = STACK_POINTER_REGNUM; -+ fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa; -+ -+#define NDS32_PUT_FS_REG(NUM, NAME) \ -+ (fs->regs.reg[NUM].how = REG_SAVED_OFFSET, \ -+ fs->regs.reg[NUM].loc.offset = (_Unwind_Ptr) &(sc_->NAME) - new_cfa) -+ -+ /* Restore all registers value. */ -+ NDS32_PUT_FS_REG (0, nds32_r0); -+ NDS32_PUT_FS_REG (1, nds32_r1); -+ NDS32_PUT_FS_REG (2, nds32_r2); -+ NDS32_PUT_FS_REG (3, nds32_r3); -+ NDS32_PUT_FS_REG (4, nds32_r4); -+ NDS32_PUT_FS_REG (5, nds32_r5); -+ NDS32_PUT_FS_REG (6, nds32_r6); -+ NDS32_PUT_FS_REG (7, nds32_r7); -+ NDS32_PUT_FS_REG (8, nds32_r8); -+ NDS32_PUT_FS_REG (9, nds32_r9); -+ NDS32_PUT_FS_REG (10, nds32_r10); -+ NDS32_PUT_FS_REG (11, nds32_r11); -+ NDS32_PUT_FS_REG (12, nds32_r12); -+ NDS32_PUT_FS_REG (13, nds32_r13); -+ NDS32_PUT_FS_REG (14, nds32_r14); -+ NDS32_PUT_FS_REG (15, nds32_r15); -+ NDS32_PUT_FS_REG (16, nds32_r16); -+ NDS32_PUT_FS_REG (17, nds32_r17); -+ NDS32_PUT_FS_REG (18, nds32_r18); -+ NDS32_PUT_FS_REG (19, nds32_r19); -+ NDS32_PUT_FS_REG (20, nds32_r20); -+ NDS32_PUT_FS_REG (21, nds32_r21); -+ NDS32_PUT_FS_REG (22, nds32_r22); -+ NDS32_PUT_FS_REG (23, nds32_r23); -+ NDS32_PUT_FS_REG (24, nds32_r24); -+ NDS32_PUT_FS_REG (25, nds32_r25); -+ -+ NDS32_PUT_FS_REG (28, nds32_fp); -+ NDS32_PUT_FS_REG (29, nds32_gp); -+ NDS32_PUT_FS_REG (30, nds32_lp); -+ NDS32_PUT_FS_REG (31, nds32_sp); -+ -+ /* Restore PC, point to trigger signal instruction. */ -+ NDS32_PUT_FS_REG (32, nds32_ipc); -+ -+#undef NDS32_PUT_FS_REG -+ -+ /* The retaddr is PC, use PC to find FDE. */ -+ fs->retaddr_column = 32; -+ fs->signal_frame = 1; -+ -+ return _URC_NO_REASON; -+} -+ -+#endif -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-glibc gcc-8.2.0/libgcc/config/nds32/t-nds32-glibc ---- gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-glibc 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/t-nds32-glibc 2019-01-25 15:38:37.357255536 +0100 -@@ -0,0 +1,34 @@ -+# Rules of glibc library makefile of Andes NDS32 cpu for GNU compiler -+# Copyright (C) 2012-2015 Free Software Foundation, Inc. -+# Contributed by Andes Technology Corporation. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published -+# by the Free Software Foundation; either version 3, or (at your -+# option) any later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+# Compiler flags to use when compiling 'libgcc2.c' -+HOST_LIBGCC2_CFLAGS = -O2 -fPIC -fwrapv -+LIB2ADD += $(srcdir)/config/nds32/linux-atomic.c -+ -+#LIB1ASMSRC = nds32/lib1asmsrc-newlib.S -+#LIB1ASMFUNCS = _divsi3 _modsi3 _udivsi3 _umodsi3 -+ -+# List of functions not to build from libgcc2.c. -+#LIB2FUNCS_EXCLUDE = _clzsi2 -+ -+# List of extra C and assembler files(*.S) to add to static libgcc2. -+#LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-newlib/_clzsi2.c -+ -+# ------------------------------------------------------------------------ -diff -urN gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-isr gcc-8.2.0/libgcc/config/nds32/t-nds32-isr ---- gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-isr 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.2.0/libgcc/config/nds32/t-nds32-isr 2019-01-25 15:38:37.357255536 +0100 -@@ -23,11 +23,11 @@ - # Makfile fragment rules for libnds32_isr.a to support ISR attribute extension - ############################################################################### - --# basic flags setting -+# Basic flags setting. - ISR_CFLAGS = $(CFLAGS) -c - --# the object files we would like to create --LIBNDS32_ISR_16B_OBJS = \ -+# The object files we would like to create. -+LIBNDS32_ISR_VEC_OBJS = \ - vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \ - vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \ - vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \ -@@ -46,40 +46,9 @@ - vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \ - vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \ - vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \ -- vec_vid72.o \ -- excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \ -- excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \ -- intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \ -- intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \ -- reset.o -- --LIBNDS32_ISR_4B_OBJS = \ -- vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \ -- vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \ -- vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \ -- vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \ -- vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \ -- vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \ -- vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \ -- vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \ -- vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \ -- vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \ -- vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \ -- vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \ -- vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \ -- vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \ -- vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \ -- vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \ -- vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \ -- vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \ -- vec_vid72_4b.o \ -- excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \ -- excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \ -- intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \ -- intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \ -- reset_4b.o -+ vec_vid72.o - --LIBNDS32_ISR_COMMON_OBJS = \ -+LIBNDS32_ISR_JMP_OBJS = \ - jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \ - jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \ - jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \ -@@ -98,29 +67,32 @@ - jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \ - jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \ - jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \ -- jmptbl_vid72.o \ -+ jmptbl_vid72.o -+ -+LIBNDS32_ISR_COMMON_OBJS = \ -+ excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \ -+ excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \ -+ intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \ -+ intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \ -+ reset.o \ - nmih.o \ - wrh.o - --LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS) -- -+LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_VEC_OBJS) $(LIBNDS32_ISR_JMP_OBJS) $(LIBNDS32_ISR_COMMON_OBJS) - --# Build common objects for ISR library --nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o - --wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o - --jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S -+# Build vector vid objects for ISR library. -+vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ - - -- --# Build 16b version objects for ISR library. (no "_4b" postfix string) --vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S -+# Build jump table objects for ISR library. -+jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ - -+ -+# Build commen objects for ISR library. - excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o - -@@ -160,48 +132,12 @@ - reset.o: $(srcdir)/config/nds32/isr-library/reset.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o - --# Build 4b version objects for ISR library. --vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ -- --excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o -- --excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o -- --excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o -- --excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o -- --excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o -- --excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o -- --intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o -- --intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o -- --intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o -- --intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o -- --intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o -+nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S -+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o - --intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o -+wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S -+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o - --reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S -- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o - - - # The rule to create libnds32_isr.a file -diff -urN gcc-8.2.0.orig/libgcc/config.host gcc-8.2.0/libgcc/config.host ---- gcc-8.2.0.orig/libgcc/config.host 2018-04-06 22:04:17.000000000 +0200 -+++ gcc-8.2.0/libgcc/config.host 2019-01-25 15:38:32.841242694 +0100 -@@ -974,6 +974,23 @@ - tmake_file="$tm_file t-crtstuff t-fdpbit msp430/t-msp430" - extra_parts="$extra_parts libmul_none.a libmul_16.a libmul_32.a libmul_f5.a" - ;; -+nds32*-linux*) -+ # Basic makefile fragment and extra_parts for crt stuff. -+ # We also append c-isr library implementation. -+ tmake_file="${tmake_file} t-slibgcc-libgcc" -+ tmake_file="${tmake_file} nds32/t-nds32-glibc nds32/t-crtstuff t-softfp-sfdf t-softfp" -+ # The header file of defining MD_FALLBACK_FRAME_STATE_FOR. -+ md_unwind_header=nds32/linux-unwind.h -+ # Append library definition makefile fragment according to --with-nds32-lib=X setting. -+ case "${with_nds32_lib}" in -+ "" | glibc | uclibc ) -+ ;; -+ *) -+ echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: glibc uclibc" 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; - nds32*-elf*) - # Basic makefile fragment and extra_parts for crt stuff. - # We also append c-isr library implementation. diff --git a/util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch b/util/crossgcc/patches/gcc-9.2.0_ada-musl_workaround.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch rename to util/crossgcc/patches/gcc-9.2.0_ada-musl_workaround.patch diff --git a/util/crossgcc/patches/gcc-8.3.0_gnat.patch b/util/crossgcc/patches/gcc-9.2.0_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.3.0_gnat.patch rename to util/crossgcc/patches/gcc-9.2.0_gnat.patch diff --git a/util/crossgcc/patches/gcc-8.3.0_libgcc.patch b/util/crossgcc/patches/gcc-9.2.0_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.3.0_libgcc.patch rename to util/crossgcc/patches/gcc-9.2.0_libgcc.patch diff --git a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum deleted file mode 100644 index b46ef8c46f..0000000000 --- a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -c27f4499dd263fe4fb01bcc5565917f3698583b2 tarballs/gcc-8.3.0.tar.xz diff --git a/util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum new file mode 100644 index 0000000000..767c6b0a98 --- /dev/null +++ b/util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum @@ -0,0 +1 @@ +306d27c3465fa36862c206738d06d65fff5c3645 tarballs/gcc-9.2.0.tar.xz diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3203d71899..59908c5b08 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -185,8 +185,6 @@ detect_special_flags() { testcc "$GCC" "$CFLAGS_GCC -Wl,--build-id=none" && CFLAGS_GCC="$CFLAGS_GCC -Wl,--build-id=none" - testcc "$GCC" "$CFLAGS_GCC -Wno-address-of-packed-member" && - CFLAGS_GCC="$CFLAGS_GCC -Wno-address-of-packed-member" case "$architecture" in x86) ;; @@ -221,7 +219,7 @@ SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} GCC_CC_${TARCH}:=${GCC} GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} # Generally available for GCC's cc1: -GCC_CFLAGS_${TARCH}+=-fno-delete-null-pointer-checks -Wlogical-op +GCC_CFLAGS_${TARCH}+=-fno-delete-null-pointer-checks -Wlogical-op -Wno-address-of-packed-member GCC_ADAFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} From 44f558ec262c671d4db76ae25eb1b8e24204d002 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 24 Feb 2020 13:26:04 +0100 Subject: [PATCH 0157/1463] treewide: capitalize 'USB' Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/udc/chipidea.c | 4 ++-- payloads/libpayload/drivers/udc/chipidea_priv.h | 2 +- payloads/libpayload/drivers/usb/ehci.c | 2 +- payloads/libpayload/drivers/usb/usb.c | 4 ++-- payloads/libpayload/drivers/usb/usbmsc.c | 8 ++++---- payloads/libpayload/include/usb/usb.h | 4 ++-- src/drivers/usb/ehci_debug.c | 2 +- src/mainboard/google/butterfly/early_init.c | 4 ++-- src/mainboard/google/link/early_init.c | 2 +- src/mainboard/google/mistral/mainboard.c | 2 +- src/mainboard/google/oak/mainboard.c | 2 +- src/mainboard/google/parrot/early_init.c | 2 +- src/mainboard/google/stout/early_init.c | 4 ++-- src/mainboard/intel/emeraldlake2/early_init.c | 2 +- src/mainboard/intel/harcuvar/hsio.h | 10 +++++----- src/mainboard/kontron/ktqm77/early_init.c | 4 ++-- src/mainboard/lenovo/t430s/variants/t431s/romstage.c | 8 ++++---- src/mainboard/samsung/lumpy/early_init.c | 2 +- src/mainboard/samsung/stumpy/early_init.c | 2 +- src/mainboard/scaleway/tagada/hsio.h | 10 +++++----- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/common/block/xhci/elog.c | 4 ++-- src/soc/mediatek/common/usb.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/intel/i82801gx/early_init.c | 2 +- util/uio_usbdebug/uio_usbdebug_intel.c | 2 +- 26 files changed, 47 insertions(+), 47 deletions(-) diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index 702cd6e4d2..d8d02f22c8 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -81,7 +81,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg, memcpy(&this->device_descriptor, dd, sizeof(*dd)); if (p->qhlist == NULL) - die("failed to allocate memory for usb device mode"); + die("failed to allocate memory for USB device mode"); memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS); @@ -102,7 +102,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg, p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; do { - debug("waiting for usb phy clk valid: %x\n", + debug("waiting for USB phy clk valid: %x\n", readl(&p->opreg->susp_ctrl)); mdelay(1); } while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0); diff --git a/payloads/libpayload/drivers/udc/chipidea_priv.h b/payloads/libpayload/drivers/udc/chipidea_priv.h index ede97ab264..82870c3579 100644 --- a/payloads/libpayload/drivers/udc/chipidea_priv.h +++ b/payloads/libpayload/drivers/udc/chipidea_priv.h @@ -47,7 +47,7 @@ struct chipidea_opreg { uint32_t portsc; // 0x174 uint32_t pad178[15]; uint32_t devlc; // 0x1b4 - /* 25:26: host-desired usb version + /* 25:26: host-desired USB version * 23: force full speed */ uint32_t pad1b8[16]; uint32_t usbmode; // 0x1f8 diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 1cfa8bb6d6..bf8a5eaa81 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -291,7 +291,7 @@ static int ehci_set_async_schedule(ehci_t *ehcic, int enable) /* Memory barrier to ensure that all memory accesses before we set the * async schedule are complete. It was observed especially in the case of - * arm64, that netboot and usb stuff resulted in lots of errors possibly + * arm64, that netboot and USB stuff resulted in lots of errors possibly * due to CPU reordering. Hence, enforcing strict CPU ordering. */ mb(); diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index d98fd9e2bc..942e1b1f6b 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -634,14 +634,14 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) /* * Should be called by the hub drivers whenever a physical detach occurs - * and can be called by usb class drivers if they are unsatisfied with a + * and can be called by USB class drivers if they are unsatisfied with a * malfunctioning device. */ void usb_detach_device(hci_t *controller, int devno) { /* check if device exists, as we may have - been called yet by the usb class driver */ + been called yet by the USB class driver */ if (controller->devices[devno]) { controller->devices[devno]->destroy (controller->devices[devno]); diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 50fd24b1f8..ed7ad1acd4 100755 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -126,7 +126,7 @@ enum { * MSC commands can be * successful, * fail with proper response or - * fail totally, which results in detaching of the usb device + * fail totally, which results in detaching of the USB device * and immediate cleanup of the usbdev_t structure. * In the latter case the caller has to make sure, that he won't * use the device any more. @@ -703,14 +703,14 @@ usb_msc_poll (usbdev_t *dev) return; if (!prev_ready && msc->ready) { - usb_debug ("usb msc: not ready -> ready (lun %d)\n", msc->lun); + usb_debug ("USB msc: not ready -> ready (lun %d)\n", msc->lun); usb_msc_create_disk (dev); } else if (prev_ready && !msc->ready) { - usb_debug ("usb msc: ready -> not ready (lun %d)\n", msc->lun); + usb_debug ("USB msc: ready -> not ready (lun %d)\n", msc->lun); usb_msc_remove_disk (dev); } else if (!prev_ready && !msc->ready) { u8 new_lun = (msc->lun + 1) % msc->num_luns; - usb_debug("usb msc: not ready (lun %d) -> lun %d\n", msc->lun, + usb_debug("USB msc: not ready (lun %d) -> lun %d\n", msc->lun, new_lun); msc->lun = new_lun; } diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index 8505c4f60b..5d27f7cbc6 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -217,7 +217,7 @@ struct usbdev { hci_t *controller; endpoint_t endpoints[32]; int num_endp; - int address; // usb address + int address; // USB address int hub; // hub, device is attached to int port; // port where device is attached usb_speed speed; @@ -263,7 +263,7 @@ struct usbdev_hc { u8* (*poll_intr_queue) (void *queue); void *instance; - /* set_address(): Tell the usb device its address (xHCI + /* set_address(): Tell the USB device its address (xHCI controllers want to do this by themselves). Also, allocate the usbdev structure, initialize enpoint 0 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 5a3f2a6e89..97b39f46a0 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -382,7 +382,7 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) u32 portsc; int loop; - /* Reset the usb debug port */ + /* Reset the USB debug port */ portsc = read32(&ehci_regs->port_status[port - 1]); portsc &= ~PORT_PE; portsc |= PORT_RESET; diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 13819f1b90..35f75c4232 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -67,7 +67,7 @@ void mainboard_late_rcba_config(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, -1 }, /* P2: Camera (no OC) */ @@ -120,7 +120,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index c234e5b848..7d1c177d92 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -154,7 +154,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 0, 0, -1 }, /* P0: Empty */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e36a1c70a7..4a109f13d7 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -26,7 +26,7 @@ static struct usb_board_data usb1_board_data = { static void setup_usb(void) { - /* Setting Secondary usb controller */ + /* Setting Secondary USB controller */ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826cdeb..864837bbd4 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -145,7 +145,7 @@ static void configure_usb(void) static void configure_usb_hub(void) { - /* set usb hub reset pin (low active) to high */ + /* set USB hub reset pin (low active) to high */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) gpio_output(GPIO(UTXD3), 1); } diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 01c452637d..917d16591e 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -116,7 +116,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 0, 0, -1 }, /* P0: Empty */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 07c19c5ae0..b4e96f0dd3 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -131,7 +131,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ { 0, 1, 0x0000 }, /* P2: Empty */ @@ -171,7 +171,7 @@ int mainboard_should_reset_usb(int s3resume) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ {0, 0, 0}, /* P2: Empty */ diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 2d97c8599c..0bc5884e6a 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -111,7 +111,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, 0 }, /* P0: Front port (OC0) */ { 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h index ce059fd8fd..c59cfd02f8 100644 --- a/src/mainboard/intel/harcuvar/hsio.h +++ b/src/mainboard/intel/harcuvar/hsio.h @@ -38,7 +38,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { * Lane[19]->USB3 rear I/O panel connector */ - /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */ + /* SKU HSIO 20 (pcie [0-15] sata [16-18] USB [19]) */ {BL_SKU_HSIO_20, {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4}, {/* ME_FIA_MUX_CONFIG */ @@ -155,7 +155,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */ + /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] USB [19]) */ {BL_SKU_HSIO_12, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/*ME_FIA_MUX_CONFIG */ @@ -272,7 +272,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_10, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -388,7 +388,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_08, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -504,7 +504,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */ + /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] USB [19]) */ {BL_SKU_HSIO_06, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index eac19f47bb..df5f57e29a 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -99,7 +99,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ @@ -127,7 +127,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 04ddbe070f..7da2c55533 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -26,9 +26,9 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* SSP1: right */ { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ - { 1, 1, 3 }, /* SSP3: dock usb3 */ - { 1, 1, -1 }, /* B0P4: wwan usb */ - { 1, 1, 2 }, /* B0P5: dock usb2 */ + { 1, 1, 3 }, /* SSP3: dock USB3 */ + { 1, 1, -1 }, /* B0P4: wwan USB */ + { 1, 1, 2 }, /* B0P5: dock USB2 */ { 0, 0, -1 }, /* B0P6 */ { 0, 0, -1 }, /* B0P7 */ { 1, 2, -1 }, /* B0P8: unknown */ @@ -36,7 +36,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 2, 5 }, /* B1P2 */ { 1, 1, -1 }, /* B1P3: fingerprint reader */ { 0, 0, -1 }, /* B1P4 */ - { 1, 1, -1 }, /* B1P5: wlan usb */ + { 1, 1, -1 }, /* B1P5: wlan USB */ { 1, 1, -1 }, /* B1P6: Camera */ }; diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 33802537ab..0249c3bc56 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -178,7 +178,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Port 0 (OC0) */ { 1, 1, 1 }, /* P1: Port 1 (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index d7f9b907be..13da85ada6 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -167,7 +167,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Front port (OC0) */ { 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index e49fefd23f..aa6af53cbb 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -38,7 +38,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { * Lane[19]->USB3 rear I/O panel connector */ - /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_20, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -155,7 +155,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_12, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -273,7 +273,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_10, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -391,7 +391,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_08, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -509,7 +509,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */ + /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] USB []) */ {BL_SKU_HSIO_06, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b9c5a4fa27..03e6dbd038 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -842,7 +842,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) /* * Override GLK xhci clock gating register(XHCLKGTEN) to - * mitigate usb device suspend and resume failure. + * mitigate USB device suspend and resume failure. */ if (CONFIG(SOC_INTEL_GLK)) { uint32_t *cfg; diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index 0fd41bfdf0..d8ee29c9ff 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -84,7 +84,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event) /* * Check if CSC bit is set and port is capable of wake on * connect/disconnect to identify if the port caused wake - * event for usb attach/detach. + * event for USB attach/detach. */ if (pch_xhci_csc_set(port_status) && pch_xhci_wake_capable(port_status)) { @@ -95,7 +95,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event) /* * Check if PLC is set and PLS indicates resume to identify if - * the port caused wake event for usb activity. + * the port caused wake event for USB activity. */ if (pch_xhci_plc_set(port_status) && pch_xhci_resume(port_status)) { diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index d80cfe98b3..b148093af0 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -104,7 +104,7 @@ static int check_ip_clk_status(void) do { if (stopwatch_expired(&sw)) { - u3p_err("usb clocks are not stable!!!\n"); + u3p_err("USB clocks are not stable!!!\n"); return -1; } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index d6003bede2..21c578fa30 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -214,7 +214,7 @@ static struct device_operations usb_ops = { }; /* - * The pci id of usb ctrl 0 and 1 are the same. + * The pci id of USB ctrl 0 and 1 are the same. */ static const struct pci_driver usb_ohci123_driver __pci_driver = { .ops = &usb_ops, diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index a627cc15c7..fa578f7cec 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -99,7 +99,7 @@ void i82801gx_early_init(void) reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - /* usb transient disconnect */ + /* USB transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); diff --git a/util/uio_usbdebug/uio_usbdebug_intel.c b/util/uio_usbdebug/uio_usbdebug_intel.c index 9271896b7d..2295cabbc7 100644 --- a/util/uio_usbdebug/uio_usbdebug_intel.c +++ b/util/uio_usbdebug/uio_usbdebug_intel.c @@ -52,7 +52,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx) void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { - /* claim usb debug port */ + /* claim USB debug port */ const unsigned long dbgctl_addr = ((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET; write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30)); From 6424ac923264f5c3ef03a357c11001f052fc609e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 25 Feb 2020 10:10:42 +0100 Subject: [PATCH 0158/1463] Get rid of ROMCC Change-Id: Ib9816f6a4e064a82e81ca68a1906b1107a2abda3 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39116 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons --- .gitignore | 1 - util/abuild/abuild.1 | 1 - 2 files changed, 2 deletions(-) diff --git a/.gitignore b/.gitignore index 0cc6ae2d3a..86ddd1919b 100644 --- a/.gitignore +++ b/.gitignore @@ -115,7 +115,6 @@ util/nvramtool/.dependencies util/nvramtool/nvramtool util/optionlist/Options.wiki util/pmh7tool/pmh7tool -util/romcc/build util/runfw/googlesnow util/superiotool/superiotool util/vgabios/testbios diff --git a/util/abuild/abuild.1 b/util/abuild/abuild.1 index 2eee84b40a..ccdfff6240 100644 --- a/util/abuild/abuild.1 +++ b/util/abuild/abuild.1 @@ -78,7 +78,6 @@ Please report any bugs on the coreboot mailing list .B abuild is covered by the GNU General Public License (GPL), version 2 or later. .SH SEE ALSO -.BR romcc (1), .BR flashrom (1). .SH COPYRIGHT 2004 Stefan Reinauer From 6130ad26b7fd2f2945d04aca10a5c5961e7d4edc Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 19 Feb 2020 22:49:11 -0700 Subject: [PATCH 0159/1463] mb/google/dedede: Update GPE configuration WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is routed to GPP_C12 GPIO. Update the GPE configuration accordingly. BUG=None TEST=Build the mainboard. Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/dedede/variants/baseboard/devicetree.cb | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 346a3096b6..37bb8f23c2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -11,13 +11,14 @@ chip soc/intel/tigerlake # - GPP_B3 - TRACKPAD_INT_ODL # - GPP_B4 - H1_AP_INT_ODL # DW1 is used by: - # - GPP_D3 - WLAN_PCIE_WAKE_ODL + # - GPP_C12 - AP_PEN_DET_ODL # DW2 is used by: - # - GPP_H16 - WWAN_HOST_WAKE + # - GPP_D0 - WWAN_HOST_WAKE + # - GPP_D3 - WLAN_PCIE_WAKE_ODL # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_H" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_D" # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 From d5a67aa4a46bdb7e1a70c6a429a63bacf4bbc9db Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 21 Jan 2020 15:58:59 +1100 Subject: [PATCH 0160/1463] mainboard/hatch: Fix GPE wake comments The indirection of names is exceedingly confusing for ultimately the single interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on the PCH side. This helps folks chase this indirection down through the code. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/gpio.c | 2 +- .../hatch/variants/baseboard/include/baseboard/gpio.h | 2 +- .../google/hatch/variants/puff/include/variant/ec.h | 7 ++++++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index dcd987fbb4..527bf93118 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -377,7 +377,7 @@ static const struct pad_config gpio_table[] = { /* H23 : GPP_H23_STRAP */ PAD_NC(GPP_H23, NONE), - /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* SD card detect VGPIO */ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index e83732cb62..7bdd912a7b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -22,7 +22,7 @@ #define GPIO_PCH_WP GPP_C20 -/* EC wake pin is LAN_WAKE# */ +/* EC wake pin is routed to GPD2/LAN_WAKE# on PCH */ #define GPE_EC_WAKE GPE0_LAN_WAK /* eSPI virtual wire reporting */ diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 501fab0dde..12837639dc 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -54,7 +54,12 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -/* Provide wake pin for EC for _PRW WoL method */ +/** + * Defines EC wake pin route. + * Note that GPE_EC_WAKE is defined, confusingly, as + * GPE_LAN_WAK which is GPD2/LAN_WAKE# on the PCH or + * as the line EC_PCH_WAKE_ODL on the schematic. + */ #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ From 1f9112f798c127fc9fa50f6f927dcea84baa1845 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 24 Feb 2020 14:43:13 -0600 Subject: [PATCH 0161/1463] ec/purism/librem: fix topstar driver ERAM mapping Correct the offset for the Topstar driver enable/disable bit, which was off by 2 bits compared to a dump of the AMI UEFI ACPI. This prevents the fan mode (FANM) from being inadvertently changed and hopefully fixes some intermittent issues with fan speed on resume from suspend. Signed-off-by: Matt DeVillier Change-Id: Ibc3c39d5b14c753eed6d1ed8cbf161717f8d04e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39105 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/ec/purism/librem/acpi/ec.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index 6f6ced1b5c..b564727614 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -65,6 +65,7 @@ Device (EC) BTLE, 1, /* Bluetooth Enable/Disable */ Offset (0x25), , 5, + FANM, 2, TPSE, 1, /* topstar-laptop driver enable/disable */ Offset (0x31), , 6, From fdba0cd6af05f9317dbd19956d644ce01e37a547 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 19 Feb 2020 00:48:55 -0800 Subject: [PATCH 0162/1463] mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik --- src/mainboard/intel/tglrvp/board_id.h | 7 ++- .../intel/tglrvp/romstage_fsp_params.c | 50 +++++++++++++++- .../spd/Hynix-H9HKNNNEBMAV-4267.spd.hex | 32 ++++++++++ src/mainboard/intel/tglrvp/spd/Makefile.inc | 22 +++++-- .../spd/Micron-MT53D1G64D8SQ-046.spd.hex | 32 ++++++++++ .../spd/Samsung-K4UBE3D4AA-MGCL.spd.hex | 32 ++++++++++ src/mainboard/intel/tglrvp/spd/spd.h | 20 ++++--- .../baseboard/include/baseboard/variants.h | 6 +- .../tglrvp/variants/tglrvp_up3/Makefile.inc | 4 +- .../intel/tglrvp/variants/tglrvp_up3/memory.c | 59 +++++++++++++++++++ 10 files changed, 245 insertions(+), 19 deletions(-) create mode 100644 src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex create mode 100644 src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex create mode 100644 src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex create mode 100644 src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index 9aac527ad0..364f4f7b04 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,11 @@ /* Board/FAB ID Command */ #define EC_FAB_ID_CMD 0x0D +/* TGL-U Board IDs */ +#define TGL_U_LP4_SAMSUNG 0x3 +#define TGL_U_LP4_HYNIX 0xB +#define TGL_U_LP4_MICRON 0x13 + /* * Returns board information (board id[15:8] and * Fab info[7:0]) on success and < 0 on error diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 0ab1f48fee..89ae0ab3fb 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,11 +12,55 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include +#include #include #include +#include +#include +#include +#include +#include +#include "board_id.h" +#include "spd/spd.h" + +static uintptr_t mainboard_get_spd_index(void) +{ + uint8_t board_id = (get_board_id() & 0xFF); + int spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + switch (board_id) { + case TGL_U_LP4_MICRON: + spd_index = SPD_ID_MICRON; + break; + case TGL_U_LP4_SAMSUNG: + spd_index = SPD_ID_SAMSUNG; + break; + case TGL_U_LP4_HYNIX: + spd_index = SPD_ID_HYNIX; + break; + default: + spd_index = SPD_ID_MICRON; + printk(BIOS_WARNING, "Invalid board_id 0x%x\n", board_id); + } + + printk(BIOS_INFO, "SPD index is 0x%x\n", spd_index); + return spd_index; +} void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* ToDo : Fill FSP-M memory params */ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + const struct mb_lpddr4x_cfg *mem_config = variant_memory_params(); + const struct spd_info spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = mainboard_get_spd_index(), + }; + bool half_populated = false; + + meminit_lpddr4x_dimm0(mem_cfg, mem_config, &spd_info, half_populated); + } diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex new file mode 100644 index 0000000000..2ff9ed382e --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00 +00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 56 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc index b8b059a1b7..21ea65e807 100644 --- a/src/mainboard/intel/tglrvp/spd/Makefile.inc +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,8 +13,22 @@ ## GNU General Public License for more details. ## -romstage-y += spd_util.c - SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b000 +SPD_SOURCES = Micron-MT53D1G64D8SQ-046 +SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL +SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex new file mode 100644 index 0000000000..40fccaa76d --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -0,0 +1,32 @@ +23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 +48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex new file mode 100644 index 0000000000..945b2e8e06 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h index ed8b8b6e0d..9e746243cc 100644 --- a/src/mainboard/intel/tglrvp/spd/spd.h +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,14 +16,16 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#include +/* SPD index definition should be matched with the order of SPD_SOURCES */ +#define SPD_ID_MICRON 0x0 +#define SPD_ID_SAMSUNG 0x1 +#define SPD_ID_HYNIX 0x2 -#define RCOMP_TARGET_PARAMS 0x5 +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); -void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); #endif diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index 9220b1140c..25c9755d9d 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ #define __BASEBOARD_VARIANTS_H__ #include +#include #include #include @@ -27,4 +28,7 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +size_t variant_memory_sku(void); +const struct mb_lpddr4x_cfg *variant_memory_params(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc index 23bf160883..c272607042 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -15,4 +15,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c new file mode 100644 index 0000000000..67979b649b --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +size_t __weak variant_memory_sku(void) +{ + return 0; +} + +static const struct mb_lpddr4x_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ + 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ + { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ + 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ + { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ + 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ + { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ + 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ + { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ + 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ + { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ + 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ + { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ + 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ + { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ + 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + }, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +{ + return &mem_config; +} From 1bfd56cb2509c239ed683667e61789a4ba5d3079 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 24 Feb 2020 15:14:22 +0530 Subject: [PATCH 0163/1463] soc/intel/tigerlake: Integrate Legacy 8254 timer support This patch overrides required FSP-S UPDs to enable 8254 timer support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected. TEST=Required to boot TianoCore payload. Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39098 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/fsp_params_tgl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e8f3..d22cde021c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + mainboard_silicon_init_params(params); } From de36d7ebfa52f4cfa2ca9b1f477a2deee6a487f4 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 25 Feb 2020 11:23:43 +0100 Subject: [PATCH 0164/1463] mb/google/hatch: reflow comment Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39118 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../google/hatch/variants/puff/include/variant/ec.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 12837639dc..2c2e62d24f 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -54,11 +54,10 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -/** +/* * Defines EC wake pin route. - * Note that GPE_EC_WAKE is defined, confusingly, as - * GPE_LAN_WAK which is GPD2/LAN_WAKE# on the PCH or - * as the line EC_PCH_WAKE_ODL on the schematic. + * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# + * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE From dba6c4cfc08db8cb41b3f40d9ac9e03f92056046 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Fri, 17 Jan 2020 18:56:58 +0530 Subject: [PATCH 0165/1463] soc/intel/tigerlake: Update FSP params for Jasper Lake Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: V Sowmya Reviewed-by: Subrata Banik Reviewed-by: Rizwan Qureshi --- src/soc/intel/tigerlake/chip.h | 9 ++ src/soc/intel/tigerlake/fsp_params_jsl.c | 143 +++++++++++++++++- .../intel/tigerlake/include/soc/pci_devs.h | 11 ++ .../intel/tigerlake/romstage/fsp_params_jsl.c | 107 ++++++++++++- .../intel/tigerlake/romstage/fsp_params_tgl.c | 9 -- 5 files changed, 265 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 75a399fc27..54423613dc 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -204,6 +204,15 @@ struct soc_intel_tigerlake_config { */ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = (1 << 0), + DEBUG_INTERFACE_UART = (1 << 1), + DEBUG_INTERFACE_USB3 = (1 << 3), + DEBUG_INTERFACE_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_TRACEHUB = (1 << 5), + } debug_interface_flag; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 6fb2f9f597..8eb3fbacaf 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,10 +12,19 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include +#include #include +#include +#include #include +#include +#include +#include +#include #include +#include +#include static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, @@ -32,10 +41,138 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_UART2 }; +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_tigerlake_config *config = config_of_soc(); + + /* LPSS controllers configuration */ + + /* I2C */ + _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= + ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); + memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, + sizeof(config->SerialIoI2cMode)); + + /* GSPI */ + _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >= + ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, + sizeof(config->SerialIoGSpiMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >= + ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode, + sizeof(config->SerialIoGSpiCsMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >= + ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState, + sizeof(config->SerialIoGSpiCsState)); + + /* UART */ + _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >= + ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!"); + memcpy(params->SerialIoUartMode, config->SerialIoUartMode, + sizeof(config->SerialIoUartMode)); +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - /* TODO: Update with UPD override as FSP matures */ + unsigned int i; + struct device *dev; + FSP_S_CONFIG *params = &supd->FspsConfig; + struct soc_intel_tigerlake_config *config = config_of_soc(); + + /* Parse device tree and fill in FSP UPDs */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Check if IGD is present and fill Graphics init param accordingly */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + + /* Unlock upper 8 bytes of RTC RAM */ + params->RtcMemoryLock = 0; + + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + + /* disable Legacy PME */ + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + /* USB configuration */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* SDCard related configuration */ + params->ScsSdCardEnabled = pcidev_path_on_root(PCH_DEVFN_SDCARD) ? dev->enabled : 0; + + params->Device4Enable = config->Device4Enable; + + /* eMMC configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + if (!dev) { + params->ScsEmmcEnabled = 0; + } else { + params->ScsEmmcEnabled = dev->enabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + if (!dev || !xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + + /* Provide correct UART number for FSP debug logs */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + + /* Override/Fill FSP Silicon Param for mainboard */ + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Return list of SOC LPSS controllers */ diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 9a35e73252..ef2dfe3ec4 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -86,6 +86,11 @@ #define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) +#endif + #define PCH_DEV_SLOT_SIO3 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) @@ -122,6 +127,12 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define PCH_DEV_SLOT_STORAGE 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#endif + #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 810cff4a20..e88d809cd3 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,113 @@ * GNU General Public License for more details. */ +#include +#include #include +#include #include +#include +#include + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_tigerlake_config *config) +{ + unsigned int i; + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint32_t mask = 0; + + if (!dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->RMT = config->RMT; + + /* PCIe root port configuration */ + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + + m_cfg->PcieRpEnableMask = mask; + + _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >= + ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!"); + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + + _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >= + ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!"); + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + + /* Set CPU Ratio */ + m_cfg->CpuRatio = 0; + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = config->DebugConsent; + + /* VT-d config */ + m_cfg->VtdDisable = 0; + + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + + /* Audio */ + m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0; + + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(config->PchHdaAudioLinkDmicEnable)); + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(config->PchHdaAudioLinkSspEnable)); + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(config->PchHdaAudioLinkSndwEnable)); +} void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - /* TODO: Update with UPD override as FSP matures */ + const struct soc_intel_tigerlake_config *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 8b32bc056b..ed6aa5a221 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -23,15 +23,6 @@ #include #include -/* Debug interface flag */ -enum debug_interface_flag { - DEBUG_INTERFACE_RAM = 0x1, - DEBUG_INTERFACE_UART = 0x2, - DEBUG_INTERFACE_USB3 = 0x4, - DEBUG_INTERFACE_SERIAL_IO = 0x8, - DEBUG_INTERFACE_TRACEHUB = 0x10 -}; - static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_tigerlake_config *config) { From b7fb24677c4adff1d7648de260c3ee9e7f5b45ee Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 26 Feb 2020 20:16:55 +0530 Subject: [PATCH 0166/1463] soc/intel/tigerlake: Add display related UPD configs for Jasper Lake TEST=Build dedede board Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_jsl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e88d809cd3..829e1e35ea 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -87,6 +87,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + /* Display */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + /* Audio */ m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0; From 6f1bebe9842ae61db7c15af1bbc59a9be367877d Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 26 Feb 2020 20:22:14 +0530 Subject: [PATCH 0167/1463] mb/google/dedede: Enable display support 1. Enable Internal Gfx device. 2. Configure DDI0 for EDP. 3. Configure HPD and DDC suppport for DDI1/DDI2. 4. Configure HPD GPIOs. TEST=Verify display on EDP panel in OS Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- .../google/dedede/variants/baseboard/devicetree.cb | 13 ++++++++++++- .../google/dedede/variants/baseboard/gpio.c | 4 ++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 37bb8f23c2..2529e53feb 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -73,6 +73,17 @@ chip soc/intel/tigerlake # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" + # Display related UPDs + # Select eDP for port A + register "DdiPortAConfig" = "1" + + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -111,7 +122,7 @@ chip soc/intel/tigerlake device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 off end # Integrated Graphics Device + device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index fa975e796b..b8ceae2f8c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -27,6 +27,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A13, NONE), /* A14 : USB_OC3_N */ PAD_NC(GPP_A14, NONE), + /* A16 : EC_AP_USB_C0_HPD */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : USB_OC0_N */ PAD_NC(GPP_A18, NONE), @@ -40,6 +42,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B23 : EC_AP_USB_C1_HDMI_HPD */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), From 1ad159094bb3445e0def0f94b38cbcc57d6e9db0 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 26 Feb 2020 00:40:42 +0530 Subject: [PATCH 0168/1463] mb/google/dedede: configure ESPI IO decode range for chrome EC Configure below ESPI IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. Change-Id: I1e450d6e45242180de715746b9852634de2669c6 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: V Sowmya Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak --- .../google/dedede/variants/baseboard/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2529e53feb..d5f58bae3e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -20,6 +20,12 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 From a5f8b8c8062047a0684623fe58e050e759593cf2 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 26 Feb 2020 11:15:49 -0800 Subject: [PATCH 0169/1463] mb/google/hatch/var/jinlon: Configure GPP_E0 as output Configure GPP_E0 as output for view angle management Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9 Signed-off-by: Rajat Jain . Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/jinlon/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 2bf97b1046..c584d94443 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -31,6 +31,8 @@ static const struct pad_config gpio_table[] = { * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* E0 : View Angle Management */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ From 9ed10bff317097c42b1545279f88af95ca796ab0 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 20 Feb 2020 13:38:49 +1100 Subject: [PATCH 0170/1463] ec/google/chromeec: Introduce SKU_ID helpers The following introduces helpers that, by default, accommodate a larger SKU id space. The following is the rational for that: Allow INT32_MAX SKU id encodings beyond UINT8_MAX. This allows for the SKU id to accommodate up to 4 bytes however we reserve the highest bit for SKU_UNKNOWN to be encoded. However, the legacy UINT8_MAX encoding is supported by leveraging the Kconfig by overriding it with the legacy max of 0xff. Follow ups migrate boards to this common framework. V.2: Fixup array size && drop sku_id SKU_UNKNOWN check and pass whatever is set to userspace as firmware doesn't care about the value. V.3: Use SPDX-License header. BUG=b:149348474 BRANCH=none TEST=tested on hatch. Change-Id: I805b25465a3b4ee3dc0cbda5feb9e9ea2493ff9e Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39018 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/Kconfig | 5 ++++ src/ec/google/chromeec/Makefile.inc | 3 +++ src/ec/google/chromeec/ec.h | 3 +++ src/ec/google/chromeec/ec_skuid.c | 36 +++++++++++++++++++++++++++++ 4 files changed, 47 insertions(+) create mode 100644 src/ec/google/chromeec/ec_skuid.c diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index b33864f09e..554677c387 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -100,6 +100,11 @@ config EC_GOOGLE_CHROMEEC_SPI_CHIP hex default 0x0 +config EC_GOOGLE_CHROMEEC_SKUID + def_bool n + help + Provides common routine for reporting the skuid to ChromeOS. + config EC_GOOGLE_CHROMEEC_BOARDNAME depends on EC_GOOGLE_CHROMEEC string "Chrome EC board name for EC" diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 4994480baa..b57333e202 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -6,6 +6,9 @@ romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c + bootblock-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-y += ec.c crosec_proto.c vstore.c diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 7341636819..f13b5105c2 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -89,6 +89,9 @@ int google_chromeec_cbi_get_fw_config(uint32_t *fw_config); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); +uint32_t google_chromeec_get_board_sku(void); +const char *google_chromeec_smbios_system_sku(void); + /* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */ #define MEC_EMI_BASE 0x800 #define MEC_EMI_SIZE 8 diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c new file mode 100644 index 0000000000..f8fc203c47 --- /dev/null +++ b/src/ec/google/chromeec/ec_skuid.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +#define SKU_UNKNOWN 0xFFFFFFFF + +uint32_t google_chromeec_get_board_sku(void) +{ + MAYBE_STATIC_NONZERO uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *google_chromeec_smbios_system_sku(void) +{ + static char sku_str[14]; /* sku{0..2147483647} */ + uint32_t sku_id = google_chromeec_get_board_sku(); + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} From d51665600e0ddbd4e1ae7144e29d179287ec285f Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 20 Feb 2020 13:46:38 +1100 Subject: [PATCH 0171/1463] mainboard/google/hatch: Migrate onto SKU ID helpers Leverage the common sku id space helper encoders. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 1 + src/mainboard/google/hatch/mainboard.c | 29 +------------------ .../google/hatch/variants/akemi/gpio.c | 3 +- .../google/hatch/variants/akemi/variant.c | 2 +- .../baseboard/include/baseboard/variants.h | 3 -- .../google/hatch/variants/dratini/variant.c | 3 +- .../google/hatch/variants/kindred/gpio.c | 3 +- .../google/hatch/variants/kindred/variant.c | 2 +- 8 files changed, 10 insertions(+), 36 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 783ec735ed..92d94db68c 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -11,6 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_ESPI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index 5761b085dd..888acf720f 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -21,36 +21,9 @@ #include #include -#define SKU_UNKNOWN 0xFFFFFFFF -#define SKU_MAX 255 - -uint32_t get_board_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - const char *smbios_system_sku(void) { - static char sku_str[7]; /* sku{0..255} */ - uint32_t sku_id = get_board_sku(); - - if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; + return google_chromeec_smbios_system_sku(); } const char *smbios_mainboard_manufacturer(void) diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index cfc185e9a5..b141f02ef3 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -17,6 +17,7 @@ #include #include #include +#include static const struct pad_config ssd_sku_gpio_table[] = { /* A18 : NC */ @@ -136,7 +137,7 @@ static const struct pad_config gpio_table[] = { const struct pad_config *override_gpio_table(size_t *num) { - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); /* For SSD SKU */ if ((sku_id == 2) || (sku_id == 4)) { *num = ARRAY_SIZE(ssd_sku_gpio_table); diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 8440b5c2d3..2965659dd8 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -28,7 +28,7 @@ void variant_devtree_update(void) ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); /* SKU ID 2 and 4 do not have eMMC, hence disable it. */ - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if ((sku_id == 2) || (sku_id == 4)) { if (emmc_host == NULL) return; diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 9d1b91e0c7..c780b973ff 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -44,9 +44,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num); /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); -/* Return board SKU */ -uint32_t get_board_sku(void); - /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); diff --git a/src/mainboard/google/hatch/variants/dratini/variant.c b/src/mainboard/google/hatch/variants/dratini/variant.c index 3a51a55bd4..bda30dfb2a 100644 --- a/src/mainboard/google/hatch/variants/dratini/variant.c +++ b/src/mainboard/google/hatch/variants/dratini/variant.c @@ -16,11 +16,12 @@ #include #include #include +#include const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_21_DRAGONAIR: diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index fbb47f95de..f53b91be2b 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -17,6 +17,7 @@ #include #include #include +#include static const struct pad_config ssd_sku_gpio_table[] = { /* A0 : SAR0_INT_ODL */ @@ -191,7 +192,7 @@ static const struct pad_config gpio_table[] = { const struct pad_config *override_gpio_table(size_t *num) { - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); /* For SSD SKU */ if (sku_id == 1 || sku_id == 3 || sku_id == 23 || sku_id == 24) { *num = ARRAY_SIZE(ssd_sku_gpio_table); diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 1e1d083c25..f26486844c 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -28,7 +28,7 @@ void variant_devtree_update(void) ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); /* SKU ID 1/3/23/24 doesn't have a eMMC device, hence disable it. */ - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if (sku_id == 1 || sku_id == 3 || sku_id == 23 || sku_id == 24) { if (emmc_host == NULL) return; From fa043c4e9d8ee07aba02eb9c7bdbe41e4848f5a9 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 21 Feb 2020 16:08:04 +1100 Subject: [PATCH 0172/1463] soc/intel/cannonlake: Plumb TetonGlacierMode into dt The following plumbs through the enabling of Intel's TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives to be accessable via devicetree. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/chip.h | 3 +++ src/soc/intel/cannonlake/fsp_params.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26492..752ec1f315 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ struct soc_intel_cannonlake_config { * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + /* Enables support for Teton Glacier hybrid storage device */ + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f1b8446f48..80918f12d9 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -374,6 +374,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) #endif params->Device4Enable = config->Device4Enable; + /* Teton Glacier hybrid storage support */ + params->TetonGlacierMode = config->TetonGlacierMode; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ From 9bffbc08739e6b879701fbcc2e6dcec79a122856 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 21 Feb 2020 16:15:26 +1100 Subject: [PATCH 0173/1463] mainboard/google/hatch/puff: Toggle on TetonGlacierMode Leverage in Puff to avoid diskswap variants. Later this could become part of the baseboard definition and hatch diskswap variants migrated over to use it as well. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 4ffbfed2b2..cca2d41ce3 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -2,6 +2,9 @@ chip soc/intel/cannonlake # Enable heci communication register "HeciEnabled" = "1" + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -166,6 +169,9 @@ chip soc/intel/cannonlake # PCIe port 7 for LAN register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" @@ -281,6 +287,7 @@ chip soc/intel/cannonlake end end # FSP requires func0 be enabled. device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end From 084233bbb64a1ecfb255fb6ecb25451a5f16c2e6 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Wed, 26 Feb 2020 19:39:48 +0530 Subject: [PATCH 0174/1463] vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2052 The FSP-M/S headers added are generated as per FSP v2052. Change-Id: Icb911418a6f8fe573b8d097b519c433e8ea6bd73 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39130 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Reviewed-by: Karthik Ramasubramanian --- .../intel/fsp/fsp2_0/jasperlake/FspmUpd.h | 86 ++++++----- .../intel/fsp/fsp2_0/jasperlake/FspsUpd.h | 143 +++++++++--------- 2 files changed, 116 insertions(+), 113 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index cce959cb15..4018ed0c68 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,18 +74,20 @@ typedef struct { **/ UINT32 MemorySpdPtr00; -/** Offset 0x0050 - Reserved +/** Offset 0x0050 - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT8 Reserved2[4]; + UINT32 MemorySpdPtr01; /** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr10; -/** Offset 0x0058 - Reserved +/** Offset 0x0058 - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT8 Reserved3[4]; + UINT32 MemorySpdPtr11; /** Offset 0x005C - Dq Byte Map CH0 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent @@ -132,7 +134,7 @@ typedef struct { /** Offset 0x0096 - Reserved **/ - UINT8 Reserved4[6]; + UINT8 Reserved2[6]; /** Offset 0x009C - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied @@ -148,7 +150,7 @@ typedef struct { /** Offset 0x00A4 - Reserved **/ - UINT8 Reserved5[6]; + UINT8 Reserved3[6]; /** Offset 0x00AA - Enable SMBus Enable/disable SMBus controller. @@ -175,7 +177,7 @@ typedef struct { /** Offset 0x00B0 - Reserved **/ - UINT8 Reserved6[2]; + UINT8 Reserved4[2]; /** Offset 0x00B2 - Enable DCI ModPHY Pwoer Gate Enable ModPHY Pwoer Gate when DCI is enabled @@ -185,7 +187,7 @@ typedef struct { /** Offset 0x00B3 - Reserved **/ - UINT8 Reserved7; + UINT8 Reserved5; /** Offset 0x00B4 - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' @@ -196,7 +198,7 @@ typedef struct { /** Offset 0x00B5 - Reserved **/ - UINT8 Reserved8[47]; + UINT8 Reserved6[47]; /** Offset 0x00E4 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) @@ -206,7 +208,7 @@ typedef struct { /** Offset 0x00E5 - Reserved **/ - UINT8 Reserved9[3]; + UINT8 Reserved7[3]; /** Offset 0x00E8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -224,7 +226,7 @@ typedef struct { /** Offset 0x00EA - Reserved **/ - UINT8 Reserved10; + UINT8 Reserved8; /** Offset 0x00EB - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -235,7 +237,7 @@ typedef struct { /** Offset 0x00EC - Reserved **/ - UINT8 Reserved11[2]; + UINT8 Reserved9[2]; /** Offset 0x00EE - SA GV System Agent dynamic frequency support and when enabled memory will be training @@ -246,7 +248,7 @@ typedef struct { /** Offset 0x00EF - Reserved **/ - UINT8 Reserved12[5]; + UINT8 Reserved10[5]; /** Offset 0x00F4 - Rank Margin Tool Enable/disable Rank Margin Tool. @@ -256,7 +258,7 @@ typedef struct { /** Offset 0x00F5 - Reserved **/ - UINT8 Reserved13[24]; + UINT8 Reserved11[24]; /** Offset 0x010D - Memory Reference Clock 100MHz, 133MHz. @@ -266,7 +268,7 @@ typedef struct { /** Offset 0x010E - Reserved **/ - UINT8 Reserved14[26]; + UINT8 Reserved12[26]; /** Offset 0x0128 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -283,7 +285,7 @@ typedef struct { /** Offset 0x012A - Reserved **/ - UINT8 Reserved15[98]; + UINT8 Reserved13[98]; /** Offset 0x018C - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -293,7 +295,7 @@ typedef struct { /** Offset 0x018D - Reserved **/ - UINT8 Reserved16[2]; + UINT8 Reserved14[2]; /** Offset 0x018F - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable @@ -309,7 +311,7 @@ typedef struct { /** Offset 0x0191 - Reserved **/ - UINT8 Reserved17[5]; + UINT8 Reserved15[5]; /** Offset 0x0196 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable @@ -325,7 +327,7 @@ typedef struct { /** Offset 0x0198 - Reserved **/ - UINT8 Reserved18[165]; + UINT8 Reserved16[165]; /** Offset 0x023D - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM @@ -337,7 +339,7 @@ typedef struct { /** Offset 0x023E - Reserved **/ - UINT8 Reserved19[7]; + UINT8 Reserved17[7]; /** Offset 0x0245 - CPU ratio value CPU ratio value. Valid Range 0 to 63 @@ -346,7 +348,7 @@ typedef struct { /** Offset 0x0246 - Reserved **/ - UINT8 Reserved20[4]; + UINT8 Reserved18[4]; /** Offset 0x024A - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. @@ -356,7 +358,7 @@ typedef struct { /** Offset 0x024B - Reserved **/ - UINT8 Reserved21[31]; + UINT8 Reserved19[31]; /** Offset 0x026A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -366,7 +368,7 @@ typedef struct { /** Offset 0x026B - Reserved **/ - UINT8 Reserved22[5]; + UINT8 Reserved20[5]; /** Offset 0x0270 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -380,7 +382,7 @@ typedef struct { /** Offset 0x0278 - Reserved **/ - UINT8 Reserved23[543]; + UINT8 Reserved21[543]; /** Offset 0x0497 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -395,7 +397,7 @@ typedef struct { /** Offset 0x04B7 - Reserved **/ - UINT8 Reserved24[5]; + UINT8 Reserved22[5]; /** Offset 0x04BC - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -418,7 +420,7 @@ typedef struct { /** Offset 0x04C2 - Reserved **/ - UINT8 Reserved25[22]; + UINT8 Reserved23[22]; /** Offset 0x04D8 - Early Command Training Enables/Disable Early Command Training @@ -428,7 +430,7 @@ typedef struct { /** Offset 0x04D9 - Reserved **/ - UINT8 Reserved26[2]; + UINT8 Reserved24[2]; /** Offset 0x04DB - Read MPR Training Enables/Disable Read MPR Training @@ -438,7 +440,7 @@ typedef struct { /** Offset 0x04DC - Reserved **/ - UINT8 Reserved27[7]; + UINT8 Reserved25[7]; /** Offset 0x04E3 - Dimm ODT Training Enables/Disable Dimm ODT Training @@ -454,7 +456,7 @@ typedef struct { /** Offset 0x04E5 - Reserved **/ - UINT8 Reserved28; + UINT8 Reserved26; /** Offset 0x04E6 - Write Slew Rate Training Enables/Disable Write Slew Rate Training @@ -482,7 +484,7 @@ typedef struct { /** Offset 0x04EA - Reserved **/ - UINT8 Reserved29[3]; + UINT8 Reserved27[3]; /** Offset 0x04ED - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D @@ -492,7 +494,7 @@ typedef struct { /** Offset 0x04EE - Reserved **/ - UINT8 Reserved30[3]; + UINT8 Reserved28[3]; /** Offset 0x04F1 - Turn Around Timing Training Enables/Disable Turn Around Timing Training @@ -502,7 +504,7 @@ typedef struct { /** Offset 0x04F2 - Reserved **/ - UINT8 Reserved31[6]; + UINT8 Reserved29[6]; /** Offset 0x04F8 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D @@ -518,7 +520,7 @@ typedef struct { /** Offset 0x04FA - Reserved **/ - UINT8 Reserved32[60]; + UINT8 Reserved30[60]; /** Offset 0x0536 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) @@ -532,7 +534,7 @@ typedef struct { /** Offset 0x0538 - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved31[2]; /** Offset 0x053A - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (224= Def) @@ -541,7 +543,7 @@ typedef struct { /** Offset 0x053C - Reserved **/ - UINT8 Reserved34[68]; + UINT8 Reserved32[68]; /** Offset 0x0580 - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining @@ -551,7 +553,7 @@ typedef struct { /** Offset 0x0581 - Reserved **/ - UINT8 Reserved35[172]; + UINT8 Reserved33[172]; /** Offset 0x062D - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -561,7 +563,7 @@ typedef struct { /** Offset 0x062E - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved34[3]; /** Offset 0x0631 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -570,7 +572,7 @@ typedef struct { /** Offset 0x0633 - Reserved **/ - UINT8 Reserved37[17]; + UINT8 Reserved35[17]; /** Offset 0x0644 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. @@ -580,7 +582,7 @@ typedef struct { /** Offset 0x0645 - Reserved **/ - UINT8 Reserved38[11]; + UINT8 Reserved36[11]; /** Offset 0x0650 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 @@ -594,7 +596,7 @@ typedef struct { /** Offset 0x065A - Reserved **/ - UINT8 Reserved39[7]; + UINT8 Reserved37[7]; /** Offset 0x0661 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. @@ -604,7 +606,7 @@ typedef struct { /** Offset 0x0662 - Reserved **/ - UINT8 Reserved40[22]; + UINT8 Reserved38[22]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index d01ae6ab46..15e78c2c75 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -283,9 +283,21 @@ typedef struct { **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x0250 - Reserved +/** Offset 0x0250 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. **/ - UINT8 Reserved7[72]; + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x0270 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x0290 - Reserved +**/ + UINT8 Reserved7[8]; /** Offset 0x0298 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, @@ -422,20 +434,9 @@ typedef struct { /** Offset 0x0384 - Reserved **/ - UINT8 Reserved14[6]; + UINT8 Reserved14[146]; -/** Offset 0x038A - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x038B - Reserved -**/ - UINT8 Reserved15[141]; - -/** Offset 0x0418 - CdClock Frequency selection +/** Offset 0x0416 - CdClock Frequency selection 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz @@ -444,109 +445,109 @@ typedef struct { **/ UINT8 CdClock; -/** Offset 0x0419 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x0417 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x041A - Reserved +/** Offset 0x0418 - Reserved **/ - UINT8 Reserved16[160]; + UINT8 Reserved15[152]; -/** Offset 0x04BA - Skip Multi-Processor Initialization +/** Offset 0x04B0 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x04BB - Reserved +/** Offset 0x04B1 - Reserved **/ - UINT8 Reserved17[9]; + UINT8 Reserved16[11]; -/** Offset 0x04C4 - CpuMpPpi +/** Offset 0x04BC - CpuMpPpi Pointer for CpuMpPpi **/ UINT32 CpuMpPpi; -/** Offset 0x04C8 - Reserved +/** Offset 0x04C0 - Reserved **/ - UINT8 Reserved18[86]; + UINT8 Reserved17[86]; -/** Offset 0x051E - RTC Cmos Memory Lock +/** Offset 0x0516 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x051F - Reserved +/** Offset 0x0517 - Reserved **/ - UINT8 Reserved19[24]; + UINT8 Reserved18[24]; -/** Offset 0x0537 - Enable PCIE RP Pm Sci +/** Offset 0x052F - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[24]; -/** Offset 0x054F - Reserved +/** Offset 0x0547 - Reserved **/ - UINT8 Reserved20[24]; + UINT8 Reserved19[24]; -/** Offset 0x0567 - Enable PCIE RP Clk Req Detect +/** Offset 0x055F - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[24]; -/** Offset 0x057F - Reserved +/** Offset 0x0577 - Reserved **/ - UINT8 Reserved21[455]; + UINT8 Reserved20[455]; -/** Offset 0x0746 - PCH Pm Slp S3 Min Assert +/** Offset 0x073E - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0747 - Reserved +/** Offset 0x073F - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved21; -/** Offset 0x0748 - PCH Pm Slp Sus Min Assert +/** Offset 0x0740 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0749 - PCH Pm Slp A Min Assert +/** Offset 0x0741 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x074A - Reserved +/** Offset 0x0742 - Reserved **/ - UINT8 Reserved23[11]; + UINT8 Reserved22[11]; -/** Offset 0x0755 - PCH Sata Pwr Opt Enable +/** Offset 0x074D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x0756 - Reserved +/** Offset 0x074E - Reserved **/ - UINT8 Reserved24[146]; + UINT8 Reserved23[146]; -/** Offset 0x07E8 - USB2 Port Over Current Pin +/** Offset 0x07E0 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x07F8 - USB3 Port Over Current Pin +/** Offset 0x07F0 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0802 - Enable 8254 Static Clock Gating +/** Offset 0x07FA - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -554,7 +555,7 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x0803 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x07FB - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -562,21 +563,21 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0804 - Reserved +/** Offset 0x07FC - Reserved **/ - UINT8 Reserved25[531]; + UINT8 Reserved24[511]; -/** Offset 0x0A17 - Enable/Disable IGFX PmSupport +/** Offset 0x09FB - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0A18 - Reserved +/** Offset 0x09FC - Reserved **/ - UINT8 Reserved26[32]; + UINT8 Reserved25[32]; -/** Offset 0x0A38 - TCC Activation Offset +/** Offset 0x0A1C - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -584,50 +585,50 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0A39 - Reserved +/** Offset 0x0A1D - Reserved **/ - UINT8 Reserved27[34]; + UINT8 Reserved26[34]; -/** Offset 0x0A5B - Enable or Disable CPU power states (C-states) +/** Offset 0x0A3F - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0A5C - Reserved +/** Offset 0x0A40 - Reserved **/ - UINT8 Reserved28[74]; + UINT8 Reserved27[74]; -/** Offset 0x0AA6 - Platform Power Pmax +/** Offset 0x0A8A - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0AA8 - Reserved +/** Offset 0x0A8C - Reserved **/ - UINT8 Reserved29[116]; + UINT8 Reserved28[116]; -/** Offset 0x0B1C - End of Post message +/** Offset 0x0B00 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x0B1D - Reserved +/** Offset 0x0B01 - Reserved **/ - UINT8 Reserved30[3]; + UINT8 Reserved29[3]; -/** Offset 0x0B20 - Unlock all GPIO pads +/** Offset 0x0B04 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0B21 - Reserved +/** Offset 0x0B05 - Reserved **/ - UINT8 Reserved31[447]; + UINT8 Reserved30[451]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -642,11 +643,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0CE0 +/** Offset 0x0CC8 **/ - UINT8 UnusedUpdSpace37[6]; + UINT8 UnusedUpdSpace36[6]; -/** Offset 0x0CE6 +/** Offset 0x0CCE **/ UINT16 UpdTerminator; } FSPS_UPD; From 4c28ccd0dc71d91f1a0f098a74add8701515c3a1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 14:06:42 +0100 Subject: [PATCH 0175/1463] Docs/project_ideas.md: Add a memtest libpayload based payload Change-Id: Iebdb75b99e18fe92aa4c801769532781edf44d9a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36747 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- Documentation/contributing/project_ideas.md | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 8271ea91f0..2c621f410d 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -166,3 +166,21 @@ This is a research-heavy project. ### Mentors * Ron Minnich + +## Libpayload based memtest payload +[Memtest86+](https://www.memtest.org/) has some limitations: first and +foremost it only works on x86, while it can print to serial console the +GUI only works in legacy VGA mode. + +This project would involve porting the memtest suite to libpayload and +build a payload around it. + +### Requirements +* coreboot knowledge: Should know how to build coreboot images and + include payloads. +* other knowledge: Knowledge on how dram works is a plus. +* hardware requirements: Initial work can happen on qemu targets, + being able to test on coreboot supported hardware is a plus. + +### Mentors +* TODO From 6d295ac9506864a4e3e156c4cea04d1dc7e00716 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 25 Feb 2020 21:35:45 +0100 Subject: [PATCH 0176/1463] payloads/ext/tianocore/Makefile: Enable quiet mode The build process of this payload is unnecessarily prolix. Therefore, make use of the `-q` flag to abridge the output. TEST=When building for X64, UEFIPAYLOAD.fd does not differ. Change-Id: I6eba069ff5be2813d180dae40ab10155f0542f33 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39123 Reviewed-by: Paul Menzel Reviewed-by: Benjamin Doron Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- payloads/external/tianocore/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 7adb700a6e..af06464fe0 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -49,9 +49,9 @@ TIMER=-DUSE_HPET_TIMER endif ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) - BUILD_STR=-a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) + BUILD_STR=-q -a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) else - BUILD_STR=-a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) + BUILD_STR=-q -a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) endif all: clean build From 2f55726609bb27d550b58f735b1426065558fee0 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 21 Feb 2020 15:14:17 +1100 Subject: [PATCH 0177/1463] mainboard/google/volteer: Migrate onto SKU ID helpers Leverage the common sku id space helper encoders. volteer uses the non-legacy SKU ID space. BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/Kconfig | 1 + src/mainboard/google/volteer/mainboard.c | 29 +----------------------- 2 files changed, 2 insertions(+), 28 deletions(-) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 572a10020e..699cdeae8d 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 51cbc40cfc..dcefb5d9cd 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -17,36 +17,9 @@ #include #include -#define SKU_UNKNOWN 0xFFFFFFFF -#define SKU_MAX 0x7FFFFFFF - -static uint32_t get_board_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - const char *smbios_system_sku(void) { - static char sku_str[14]; /* sku{0..2147483647} */ - uint32_t sku_id = get_board_sku(); - - if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; + return google_chromeec_smbios_system_sku(); } static void mainboard_init(struct device *dev) From 1ac2cc253b120e5fcd8d3cb477724c36b5f35cb5 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 13 Feb 2020 13:00:41 +0100 Subject: [PATCH 0178/1463] superio/common: Validate devicetree As the SSDT generator for LDNs expects a "parent" PNP device for proper ACPI code generation, validate that it is present. Make sure the devicetree looks as expected and print a BUG message if that's not the case. Tested on HP Z220: No BUG message was printed. Change-Id: I6cbcba8ac86a2a837e23055fdd7e529f9b3277a2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38863 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/superio/common/ssdt.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index 7aa24ea794..e31660fad1 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -162,12 +162,33 @@ static const char *name_from_hid(const char *hid) void superio_common_fill_ssdt_generator(struct device *dev) { + if (!dev || !dev->bus || !dev->bus->dev) { + printk(BIOS_CRIT, "BUG: Invalid argument in %s!\n", __func__); + return; + } + const char *scope = acpi_device_scope(dev); const char *name = acpi_device_name(dev); const u8 ldn = dev->path.pnp.device & 0xff; const u8 vldn = (dev->path.pnp.device >> 8) & 0x7; const char *hid; + /* Validate devicetree settings */ + bool bug = false; + if (dev->bus->dev->path.type != DEVICE_PATH_PNP) { + bug = true; + printk(BIOS_CRIT, "BUG: Parent of device %s is not a PNP device\n", + dev_path(dev)); + } else if (dev->bus->dev->path.pnp.port != dev->path.pnp.port) { + bug = true; + printk(BIOS_CRIT, "BUG: Parent of device %s has wrong I/O port\n", + dev_path(dev)); + } + if (bug) { + printk(BIOS_CRIT, "BUG: Check your devicetree!\n"); + return; + } + if (!scope || !name) { printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); return; From 3db439eb1ade91a28cdb34d58b7908024b12d406 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Tue, 25 Feb 2020 03:43:02 +0000 Subject: [PATCH 0179/1463] payloads/tianocore: Enable PS2 keyboard module Upstream UEFIPayload[1] now includes support for PS2 keyboards, but defaults it to disabled. Enable it, as CorebootPayload does. Note that this increases payload size in coreboot by a little over 5 KiB. 1. https://github.com/tianocore/edk2/commit/33a32936510ecff00d0b6aeaeb9c8b2bf5430b8b Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/38960 Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- payloads/external/tianocore/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index af06464fe0..58eb458904 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -24,7 +24,7 @@ upstream_git_repo=https://github.com/tianocore/edk2 ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y) bootloader=UefiPayloadPkg -build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) +build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE TAG=upstream/master else bootloader=CorebootPayloadPkg From 56626cf5d88523ed274c27e9624de7a358efe835 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 27 Feb 2020 19:39:22 +0530 Subject: [PATCH 0180/1463] soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya --- src/soc/intel/icelake/Kconfig | 16 ++++++++++++++++ src/soc/intel/icelake/chip.h | 9 --------- src/soc/intel/icelake/romstage/fsp_params.c | 2 +- src/soc/intel/tigerlake/Kconfig | 15 +++++++++++++++ src/soc/intel/tigerlake/chip.h | 11 ----------- .../intel/tigerlake/romstage/fsp_params_jsl.c | 2 +- .../intel/tigerlake/romstage/fsp_params_tgl.c | 2 +- 7 files changed, 34 insertions(+), 23 deletions(-) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15a5a3120d..9e97d2ca2c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -186,6 +186,22 @@ config FSP_FD_PATH depends on FSP_USE_REPO default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" +config SOC_INTEL_ICELAKE_DEBUG_CONSENT + int "Debug Consent for ICL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug types are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual + config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX bool "Enable display over external PCIE GFX card" select ALWAYS_LOAD_OPROM diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 068751324f..569160f41f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -203,15 +203,6 @@ struct soc_intel_icelake_config { uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 1f9960410e..8dd6bfdcf7 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -87,7 +87,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT; /* Vt-D config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 79d74b4083..8d066f3d45 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -212,4 +212,19 @@ config FSP_FD_PATH default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE +config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT + int "Debug Consent for TGL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual endif diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 54423613dc..02855b1b00 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -169,17 +169,6 @@ struct soc_intel_tigerlake_config { */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - DebugConsent_2WIRE_DCI, - DebugConsent_Manual, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 829e1e35ea..56124f4c04 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -80,7 +80,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a221..d76961515f 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -109,7 +109,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; From e1498ce6da91c3e6bc61c67213f10ab927704510 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 12 Feb 2020 15:23:05 +0100 Subject: [PATCH 0181/1463] superio/nuvoton/npcd378: Switch to superio/common Replace DSDT ACPI code and DSDT injection with a SSDT only solution. The current implementation shows some issues on current Linux, which might be due to external ACPI objects, which are then injected into DSDT or the fact that those objects only use 3 characters. Replace all the DSDT code with an SSDT generator. Tested on HP Z220: Boots into Linux with no ACPI errors. The SSDT can be disassembled. Change-Id: I41616d9bf320fd2b4d8495892b8190cd2a2d057f Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38862 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../compaq_8200_elite_sff/acpi/platform.asl | 2 + .../hp/compaq_8200_elite_sff/acpi/superio.asl | 14 - .../hp/compaq_8200_elite_sff/devicetree.cb | 184 ++++----- .../hp/z220_sff_workstation/acpi/platform.asl | 2 + .../hp/z220_sff_workstation/acpi/superio.asl | 14 - .../hp/z220_sff_workstation/devicetree.cb | 184 ++++----- src/superio/nuvoton/npcd378/Makefile.inc | 2 + src/superio/nuvoton/npcd378/acpi/superio.asl | 321 +-------------- src/superio/nuvoton/npcd378/superio.c | 381 +++++++++++++++--- 9 files changed, 533 insertions(+), 571 deletions(-) diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl index 02a1b54b87..5a861f1f3b 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl @@ -15,6 +15,7 @@ Method(_WAK, 1, NotSerialized) { + // Generated by SSDT \_SB.PCI0.LPCB.SIO0.SIOW (Arg0) Return(Package(){0,0}) @@ -22,5 +23,6 @@ Method(_WAK, 1, NotSerialized) Method(_PTS, 1, NotSerialized) { + // Generated by SSDT \_SB.PCI0.LPCB.SIO0.SIOS (Arg0) } diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl index 630c5e8033..d6acae9c00 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl @@ -13,24 +13,10 @@ * GNU General Public License for more details. */ - -#undef SUPERIO_DEV -#undef SUPERIO_PNP_BASE -#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e - -#define SUPERIO_SHOW_SP2 -#define SUPERIO_SHOW_KBC - #include Scope (\_GPE) { - Method (_L08, 0, NotSerialized) - { - \_SB.PCI0.LPCB.SIO0.SIOH () - } - Method (_L0D, 0, NotSerialized) { Notify (\_SB.PCI0.EHC1, 0x02) diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 9dc18be9b9..915f87d450 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -75,100 +75,104 @@ chip northbridge/intel/sandybridge device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 on end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - chip superio/nuvoton/npcd378 - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel port - # global + chip superio/common + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/npcd378 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global - # serialice: Vendor writes: - irq 0x14 = 0x9c - irq 0x1c = 0xa8 - irq 0x1d = 0x08 - irq 0x22 = 0x3f - irq 0x1a = 0xb0 - # dumped from superiotool: - irq 0x1b = 0x1e - irq 0x27 = 0x04 - irq 0x2a = 0x00 - irq 0x2d = 0x01 - # parallel port - io 0x60 = 0x378 - irq 0x70 = 0x07 - drq 0x74 = 0x01 - end - device pnp 2e.2 off # COM1 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # COM2, IR - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # LED control - io 0x60 = 0x600 - # IOBASE[0h] = bit0 LED red / green - # IOBASE[0h] = bit1-4 LED PWM duty cycle - # IOBASE[1h] = bit6 SWCC + # serialice: Vendor writes: + irq 0x14 = 0x9c + irq 0x1c = 0xa8 + irq 0x1d = 0x08 + irq 0x22 = 0x3f + irq 0x1a = 0xb0 + # dumped from superiotool: + irq 0x1b = 0x1e + irq 0x27 = 0x08 + irq 0x2a = 0x20 + irq 0x2d = 0x01 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 0x07 + drq 0x74 = 0x01 + end + device pnp 2e.2 off # COM1 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # LED control + io 0x60 = 0x600 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC - io 0x62 = 0x610 - # IOBASE [0h] = GPES - # IOBASE [1h] = GPEE - # IOBASE [4h:7h] = 32bit upcounter at 1Mhz - # IOBASE [8h:bh] = GPS - # IOBASE [ch:fh] = GPE - end - device pnp 2e.5 on # Mouse - irq 0x70 = 0xc - end - device pnp 2e.6 on # Keyboard - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 0x01 - # serialice: Vendor writes: - drq 0xf0 = 0x40 - end - device pnp 2e.7 on # WDT ? - io 0x60 = 0x620 - end - device pnp 2e.8 on # HWM - io 0x60 = 0x800 - # IOBASE[0h:feh] HWM page - # IOBASE[ffh] bit0-bit3 page selector + io 0x62 = 0x610 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + device pnp 2e.5 on # Mouse + irq 0x70 = 0xc + end + device pnp 2e.6 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + # serialice: Vendor writes: + drq 0xf0 = 0x40 + end + device pnp 2e.7 on # WDT ? + io 0x60 = 0x620 + end + device pnp 2e.8 on # HWM + io 0x60 = 0x800 + # IOBASE[0h:feh] HWM page + # IOBASE[ffh] bit0-bit3 page selector - drq 0xf0 = 0x20 - drq 0xf1 = 0x01 - drq 0xf2 = 0x40 - drq 0xf3 = 0x01 + drq 0xf0 = 0x20 + drq 0xf1 = 0x01 + drq 0xf2 = 0x40 + drq 0xf3 = 0x01 - drq 0xf4 = 0x66 - drq 0xf5 = 0x67 - drq 0xf6 = 0x66 - drq 0xf7 = 0x01 - end - device pnp 2e.f on # GPIO OD ? - drq 0xf1 = 0x97 - drq 0xf2 = 0x01 - drq 0xf5 = 0x08 - drq 0xfe = 0x80 - end - device pnp 2e.15 on # BUS ? - io 0x60 = 0x0680 - io 0x62 = 0x0690 - end - device pnp 2e.1c on # Suspend Control ? - io 0x60 = 0x640 - # writing to IOBASE[5h] - # 0x0: Power off - # 0x9: Power off and bricked until CMOS battery removed - end - device pnp 2e.1e on # GPIO ? - io 0x60 = 0x660 - drq 0xf4 = 0x01 - # skip the following, as it - # looks like remapped registers - #drq 0xf5 = 0x06 - #drq 0xf6 = 0x60 - #drq 0xfe = 0x03 + drq 0xf4 = 0x66 + drq 0xf5 = 0x67 + drq 0xf6 = 0x66 + drq 0xf7 = 0x01 + end + device pnp 2e.f on # GPIO OD ? + drq 0xf1 = 0x97 + drq 0xf2 = 0x01 + drq 0xf5 = 0x08 + drq 0xfe = 0x80 + end + device pnp 2e.15 on # BUS ? + io 0x60 = 0x0680 + io 0x62 = 0x0690 + end + device pnp 2e.1c on # Suspend Control ? + io 0x60 = 0x640 + # writing to IOBASE[5h] + # 0x0: Power off + # 0x9: Power off and bricked until CMOS battery removed + end + device pnp 2e.1e on # GPIO ? + io 0x60 = 0x660 + drq 0xf4 = 0x01 + # skip the following, as it + # looks like remapped registers + #drq 0xf5 = 0x06 + #drq 0xf6 = 0x60 + #drq 0xfe = 0x03 + end + end end end chip drivers/pc80/tpm diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl index 02a1b54b87..5a861f1f3b 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl +++ b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl @@ -15,6 +15,7 @@ Method(_WAK, 1, NotSerialized) { + // Generated by SSDT \_SB.PCI0.LPCB.SIO0.SIOW (Arg0) Return(Package(){0,0}) @@ -22,5 +23,6 @@ Method(_WAK, 1, NotSerialized) Method(_PTS, 1, NotSerialized) { + // Generated by SSDT \_SB.PCI0.LPCB.SIO0.SIOS (Arg0) } diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl index 630c5e8033..d6acae9c00 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl +++ b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl @@ -13,24 +13,10 @@ * GNU General Public License for more details. */ - -#undef SUPERIO_DEV -#undef SUPERIO_PNP_BASE -#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e - -#define SUPERIO_SHOW_SP2 -#define SUPERIO_SHOW_KBC - #include Scope (\_GPE) { - Method (_L08, 0, NotSerialized) - { - \_SB.PCI0.LPCB.SIO0.SIOH () - } - Method (_L0D, 0, NotSerialized) { Notify (\_SB.PCI0.EHC1, 0x02) diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index ab6ee04f67..6823c9fd1f 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -76,100 +76,104 @@ chip northbridge/intel/sandybridge device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 on end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - chip superio/nuvoton/npcd378 - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel port - # global + chip superio/common + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/npcd378 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global - # serialice: Vendor writes: - irq 0x14 = 0x9c - irq 0x1c = 0xa8 - irq 0x1d = 0x08 - irq 0x22 = 0x3f - irq 0x1a = 0xb0 - # dumped from superiotool: - irq 0x1b = 0x1e - irq 0x27 = 0x08 - irq 0x2a = 0x20 - irq 0x2d = 0x01 - # parallel port - io 0x60 = 0x378 - irq 0x70 = 0x07 - drq 0x74 = 0x01 - end - device pnp 2e.2 off # COM1 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # COM2, IR - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # LED control - io 0x60 = 0x600 - # IOBASE[0h] = bit0 LED red / green - # IOBASE[0h] = bit1-4 LED PWM duty cycle - # IOBASE[1h] = bit6 SWCC + # serialice: Vendor writes: + irq 0x14 = 0x9c + irq 0x1c = 0xa8 + irq 0x1d = 0x08 + irq 0x22 = 0x3f + irq 0x1a = 0xb0 + # dumped from superiotool: + irq 0x1b = 0x1e + irq 0x27 = 0x08 + irq 0x2a = 0x20 + irq 0x2d = 0x01 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 0x07 + drq 0x74 = 0x01 + end + device pnp 2e.2 off # COM1 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # LED control + io 0x60 = 0x600 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC - io 0x62 = 0x610 - # IOBASE [0h] = GPES - # IOBASE [1h] = GPEE - # IOBASE [4h:7h] = 32bit upcounter at 1Mhz - # IOBASE [8h:bh] = GPS - # IOBASE [ch:fh] = GPE - end - device pnp 2e.5 on # Mouse - irq 0x70 = 0xc - end - device pnp 2e.6 on # Keyboard - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 0x01 - # serialice: Vendor writes: - drq 0xf0 = 0x40 - end - device pnp 2e.7 on # WDT ? - io 0x60 = 0x620 - end - device pnp 2e.8 on # HWM - io 0x60 = 0x800 - # IOBASE[0h:feh] HWM page - # IOBASE[ffh] bit0-bit3 page selector + io 0x62 = 0x610 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + device pnp 2e.5 on # Mouse + irq 0x70 = 0xc + end + device pnp 2e.6 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + # serialice: Vendor writes: + drq 0xf0 = 0x40 + end + device pnp 2e.7 on # WDT ? + io 0x60 = 0x620 + end + device pnp 2e.8 on # HWM + io 0x60 = 0x800 + # IOBASE[0h:feh] HWM page + # IOBASE[ffh] bit0-bit3 page selector - drq 0xf0 = 0x20 - drq 0xf1 = 0x01 - drq 0xf2 = 0x40 - drq 0xf3 = 0x01 + drq 0xf0 = 0x20 + drq 0xf1 = 0x01 + drq 0xf2 = 0x40 + drq 0xf3 = 0x01 - drq 0xf4 = 0x66 - drq 0xf5 = 0x67 - drq 0xf6 = 0x66 - drq 0xf7 = 0x01 - end - device pnp 2e.f on # GPIO OD ? - drq 0xf1 = 0x97 - drq 0xf2 = 0x01 - drq 0xf5 = 0x08 - drq 0xfe = 0x80 - end - device pnp 2e.15 on # BUS ? - io 0x60 = 0x0680 - io 0x62 = 0x0690 - end - device pnp 2e.1c on # Suspend Control ? - io 0x60 = 0x640 - # writing to IOBASE[5h] - # 0x0: Power off - # 0x9: Power off and bricked until CMOS battery removed - end - device pnp 2e.1e on # GPIO ? - io 0x60 = 0x660 - drq 0xf4 = 0x01 - # skip the following, as it - # looks like remapped registers - #drq 0xf5 = 0x06 - #drq 0xf6 = 0x60 - #drq 0xfe = 0x03 + drq 0xf4 = 0x66 + drq 0xf5 = 0x67 + drq 0xf6 = 0x66 + drq 0xf7 = 0x01 + end + device pnp 2e.f on # GPIO OD ? + drq 0xf1 = 0x97 + drq 0xf2 = 0x01 + drq 0xf5 = 0x08 + drq 0xfe = 0x80 + end + device pnp 2e.15 on # BUS ? + io 0x60 = 0x0680 + io 0x62 = 0x0690 + end + device pnp 2e.1c on # Suspend Control ? + io 0x60 = 0x640 + # writing to IOBASE[5h] + # 0x0: Power off + # 0x9: Power off and bricked until CMOS battery removed + end + device pnp 2e.1e on # GPIO ? + io 0x60 = 0x660 + drq 0xf4 = 0x01 + # skip the following, as it + # looks like remapped registers + #drq 0xf5 = 0x06 + #drq 0xf6 = 0x60 + #drq 0xfe = 0x03 + end + end end end chip drivers/pc80/tpm diff --git a/src/superio/nuvoton/npcd378/Makefile.inc b/src/superio/nuvoton/npcd378/Makefile.inc index 6dc762605a..e70d69b0f0 100644 --- a/src/superio/nuvoton/npcd378/Makefile.inc +++ b/src/superio/nuvoton/npcd378/Makefile.inc @@ -2,3 +2,5 @@ # This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += superio.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += ../../common/ssdt.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += ../../common/generic.c diff --git a/src/superio/nuvoton/npcd378/acpi/superio.asl b/src/superio/nuvoton/npcd378/acpi/superio.asl index 41efb50b67..cffe33f9a8 100644 --- a/src/superio/nuvoton/npcd378/acpi/superio.asl +++ b/src/superio/nuvoton/npcd378/acpi/superio.asl @@ -1,321 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* - * Include this file into a mainboard's DSDT _SB device tree and it will - * expose the NPCD378 SuperIO and some of its functionality. - * - * It allows the change of IO ports, IRQs and DMA settings on logical - * devices, disabling and reenabling logical devices. - * - * LDN State - * 0x2 SP1 Implemented, untested - * 0x5 KBCK Implemented, untested - */ - -#undef SUPERIO_CHIP_NAME -#define SUPERIO_CHIP_NAME NPCD378 -#include - -#undef PNP_DEFAULT_PSC -#define PNP_DEFAULT_PSC Return (0) /* no power management */ - -Device(SUPERIO_DEV) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("Nuvoton NPCD378 Super I/O")) - Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) - - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - PNP_ADDR_REG, 8, - PNP_DATA_REG, 8, - } - IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ - - Offset (0x30), - PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ - ACT1, 1, /* Logical device activation */ - ACT2, 1, /* Logical device activation */ - ACT3, 1, /* Logical device activation */ - ACT4, 1, /* Logical device activation */ - ACT5, 1, /* Logical device activation */ - ACT6, 1, /* Logical device activation */ - ACT7, 1, /* Logical device activation */ - - Offset (0x60), - PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ - PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ - Offset (0x62), - PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ - PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ - Offset (0x64), - PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ - PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ - - Offset (0x70), - PNP_IRQ0, 8, /* First IRQ */ - Offset (0x72), - PNP_IRQ1, 8, /* Second IRQ */ - } - - #undef PNP_ENTER_MAGIC_1ST - #undef PNP_ENTER_MAGIC_2ND - #undef PNP_ENTER_MAGIC_3RD - #undef PNP_ENTER_MAGIC_4TH - #undef PNP_EXIT_MAGIC_1ST - #undef PNP_EXIT_SPECIAL_REG - #undef PNP_EXIT_SPECIAL_VAL - #define PNP_ENTER_MAGIC_1ST 0x87 - #define PNP_ENTER_MAGIC_2ND 0x87 - #define PNP_EXIT_MAGIC_1ST 0xaa - #include - -#ifdef SUPERIO_SHOW_LPT - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #undef PNP_DEVICE_ACTIVE - #define PNP_DEVICE_ACTIVE ACT3 - #define SUPERIO_PNP_LDN 1 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #include -#endif - -#ifdef SUPERIO_SHOW_SP1 - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 2 - #include -#endif - -#ifdef SUPERIO_SHOW_SP2 - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 3 - #include -#endif - -#ifdef SUPERIO_SHOW_KBC - #undef SUPERIO_KBC_LDN - #undef SUPERIO_KBC_PS2M - #undef SUPERIO_KBC_PS2LDN - #define SUPERIO_KBC_PS2LDN 5 - #define SUPERIO_KBC_LDN 6 - #include -#endif - -#ifdef SUPERIO_SHOW_GPIO - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IO2 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #undef PNP_DEVICE_ACTIVE - #define PNP_DEVICE_ACTIVE ACT3 - #define SUPERIO_PNP_LDN 8 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #include -#endif - - // generated by SSDT - External(SWB, IntObj) - External(SWL, IntObj) - OperationRegion (SWCR, SystemIO, SWB, SWL) - Field (SWCR, ByteAcc, NoLock, Preserve) - { - LEDC, 8, - SWCC, 8 - } - - // generated by SSDT - External(RNB, IntObj) - External(RNL, IntObj) - OperationRegion (RNTR, SystemIO, RNB, RNL) - Field (RNTR, ByteAcc, NoLock, Preserve) - { - GPES, 8, - GPEE, 8, - Offset (0x08), - GPS0, 8, - GPS1, 8, - GPS2, 8, - GPS3, 8, - GPE0, 8, - GPE1, 8, - GPE2, 8, - GPE3, 8 - } - - Name (MSFG, One) - Name (KBFG, One) - Name (PMFG, Zero) // Wake event backup - - Method (_CRS, 0, Serialized) - { - Name (CRS, ResourceTemplate () - { - FixedIO (SUPERIO_PNP_BASE, 0x02) - // filled below - FixedIO (0, 0, CRS1) - FixedIO (0, 0, CRS2) - }) - - CreateWordField (CRS, CRS1._BAS, TMP1) - Store(SWB, TMP1) - CreateByteField (CRS, CRS1._LEN, TMP2) - Store(SWL, TMP2) - - CreateWordField (CRS, CRS2._BAS, TMP3) - Store(RNB, TMP3) - CreateByteField (CRS, CRS2._LEN, TMP4) - Store(RNL, TMP4) - - /* Announce the used I/O ports to the OS */ - Return (CRS) - } - -#ifdef SUPERIO_SHOW_KBC - -#if defined(SUPERIO_KBC_LDN) -#define _PS2_KB SUPERIO_ID(KBD, SUPERIO_KBC_LDN) -#else -#define _PS2_KB PS2K -#endif - Scope (_PS2_KB) - { - Method (_PSW, 1, NotSerialized) - { - KBFG = Arg0 - } - - Method (_PRW, 0, NotSerialized) - { - Return (Package (0x02) {0x08, 0x03}) - } - } - -#if defined(SUPERIO_KBC_PS2M) -#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2M) -#elif defined(SUPERIO_KBC_PS2LDN) -#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN) -#else -#define _PS2_M PS2M -#endif - Scope (_PS2_M) - { - Method (_PSW, 1, NotSerialized) - { - MSFG = Arg0 - } - - Method (_PRW, 0, NotSerialized) - { - Return (Package (0x02) {0x08, 0x03}) - } - } - - Method (SIOH, 0, NotSerialized) - { - If ((PMFG & 0xE8)) - { - Notify (_PS2_KB, 0x02) - } - - If ((PMFG & 0x10)) - { - Notify (_PS2_M, 0x02) - } - } -#else - Method (SIOH, 0, NotSerialized) - { - } -#endif - - /* SuperIO sleep method */ - Method (SIOS, 1, NotSerialized) - { - If ((0x05 != Arg0)) - { - /* Set PS/2 powerstate in S3 */ - If (KBFG) - { - GPE2 |= 0xE8 - } - Else - { - GPE2 &= 0x17 - } - - If (MSFG) - { - GPE2 |= 0x10 - } - Else - { - GPE2 &= 0xEF - } - - /* Enable wake on GPE */ - GPEE = One - If ((0x03 == Arg0)) - { - /* green LED fading */ - Local1 = LEDC - Local1 &= 0xE0 - LEDC = (Local1 | 0x1C) - Local1 = SWCC - Local1 &= 0xBF - SWCC = (Local1 | 0x40) - } - } - - GPE0 = 0x10 - GPE1 = 0x20 - } - - /* SuperIO wake method */ - Method (SIOW, 1, NotSerialized) - { - /* Store wake status */ - PMFG = GPS2 - - /* Disable wake on GPE */ - GPEE = Zero - GPE0 = Zero - GPE1 = Zero - - /* green LED normal */ - Local1 = LEDC - Local1 &= 0xE0 - LEDC = (Local1 | 0x1E) - Local1 = SWCC - SWCC = (Local1 & 0xBF) - } -} +External (\_SB.PCI0.LPCB.SIO0, DeviceObj) +External (\_SB.PCI0.LPCB.SIO0.SIOS, MethodObj) +External (\_SB.PCI0.LPCB.SIO0.SIOW, MethodObj) diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 624c1f0882..a07afdc79c 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include "npcd378.h" @@ -87,62 +89,351 @@ static void npcd378_init(struct device *dev) } #if CONFIG(HAVE_ACPI_TABLES) -static void npcd378_ssdt(struct device *dev) +/* Provide ACPI HIDs for generic Super I/O SSDT */ +static const char *npcd378_acpi_hid(const struct device *dev) { - struct resource *res; + /* Sanity checks */ + if (dev->path.type != DEVICE_PATH_PNP) + return NULL; + if (dev->path.pnp.port == 0) + return NULL; + if ((dev->path.pnp.device & 0xff) > NPCD378_GPIOA) + return NULL; - const char *scope = acpi_device_path(dev); - if (!scope) { - printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); - return; - } - - switch (dev->path.pnp.device) { - case NPCD378_PWR: { - res = find_resource(dev, PNP_IDX_IO0); - if (!res || !res->base) { - printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n", - NPCD378_PWR); - break; - } - - acpigen_write_scope(scope); - acpigen_write_name_integer("SWB", res->base); - acpigen_write_name_integer("SWL", res->size); - acpigen_pop_len(); /* pop scope */ - - res = find_resource(dev, PNP_IDX_IO1); - if (!res || !res->base) { - printk(BIOS_ERR, "NPCD378: LDN%u IOBASE2 not set.\n", - NPCD378_PWR); - break; - } - - acpigen_write_scope(scope); - acpigen_write_name_integer("RNB", res->base); - acpigen_write_name_integer("RNL", res->size); - acpigen_pop_len(); /* pop scope */ - break; - } + switch (dev->path.pnp.device & 0xff) { + case NPCD378_FDC: + return ACPI_HID_FDC; + case NPCD378_PP: + return ACPI_HID_LPT; + case NPCD378_SP1: /* fallthrough */ + case NPCD378_SP2: + return ACPI_HID_COM; + case NPCD378_AUX: + return ACPI_HID_MOUSE; + case NPCD378_KBC: + return ACPI_HID_KEYBOARD; + default: + return ACPI_HID_PNP; } } -static const char *npcd378_acpi_name(const struct device *dev) +static void npcd378_ssdt_aux(struct device *dev) { - return "SIO0"; + /* Scope */ + acpigen_write_scope(acpi_device_path(dev)); + + acpigen_write_method("_PSW", 1); + acpigen_write_store(); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_namestring("^^MSFG"); + acpigen_pop_len(); /* Pop Method */ + + acpigen_write_PRW(8, 3); + + acpigen_pop_len(); /* Pop Scope */ +} + +static void npcd378_ssdt_kbc(struct device *dev) +{ + /* Scope */ + acpigen_write_scope(acpi_device_path(dev)); + + acpigen_write_method("_PSW", 1); + acpigen_write_store(); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_namestring("^^KBFG"); + acpigen_pop_len(); /* Pop Method */ + + acpigen_write_PRW(8, 3); + + acpigen_pop_len(); /* Pop Scope */ +} + +static void npcd378_ssdt_pwr(struct device *dev) +{ + const char *name = acpi_device_path(dev); + const char *scope = acpi_device_scope(dev); + char *tmp_name; + + /* Scope */ + acpigen_write_scope(name); + + acpigen_emit_ext_op(OPREGION_OP); + acpigen_emit_namestring("SWCR"); + acpigen_emit_byte(SYSTEMIO); + acpigen_emit_namestring("IO0B"); + acpigen_emit_namestring("IO0S"); + + struct fieldlist l1[] = { + FIELDLIST_OFFSET(0), + FIELDLIST_NAMESTR("LEDC", 8), + FIELDLIST_NAMESTR("SWCC", 8), + }; + + acpigen_write_field("SWCR", l1, ARRAY_SIZE(l1), FIELD_BYTEACC | + FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_emit_ext_op(OPREGION_OP); + acpigen_emit_namestring("RNTR"); + acpigen_emit_byte(SYSTEMIO); + acpigen_emit_namestring("IO1B"); + acpigen_emit_namestring("IO1S"); + + struct fieldlist l2[] = { + FIELDLIST_OFFSET(0), + FIELDLIST_NAMESTR("GPES", 8), + FIELDLIST_NAMESTR("GPEE", 8), + FIELDLIST_OFFSET(8), + FIELDLIST_NAMESTR("GPS0", 8), + FIELDLIST_NAMESTR("GPS1", 8), + FIELDLIST_NAMESTR("GPS2", 8), + FIELDLIST_NAMESTR("GPS3", 8), + FIELDLIST_NAMESTR("GPE0", 8), + FIELDLIST_NAMESTR("GPE1", 8), + FIELDLIST_NAMESTR("GPE2", 8), + FIELDLIST_NAMESTR("GPE3", 8), + }; + + acpigen_write_field("RNTR", l2, ARRAY_SIZE(l2), FIELD_BYTEACC | + FIELD_NOLOCK | FIELD_PRESERVE); + + /* Method (SIOW, 1, NotSerialized) */ + acpigen_write_method("SIOW", 1); + acpigen_write_store(); + acpigen_emit_namestring("^GPS2"); + acpigen_emit_namestring("^^PMFG"); + + acpigen_write_store(); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_namestring("^GPEE"); + + acpigen_write_store(); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_namestring("^GPE0"); + + acpigen_write_store(); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_namestring("^GPE1"); + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring("^LEDC"); + acpigen_write_integer(0xE0); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_emit_byte(OR_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(0x1E); + acpigen_emit_namestring("^LEDC"); + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring("^SWCC"); + acpigen_write_integer(0xBF); + acpigen_emit_namestring("^SWCC"); + + acpigen_pop_len(); /* SIOW method */ + + /* Method (SIOS, 1, NotSerialized) */ + acpigen_write_method("SIOS", 1); + + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(5); + + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("^^KBFG"); + acpigen_emit_byte(ONE_OP); + + acpigen_emit_byte(OR_OP); + acpigen_emit_namestring("^GPE2"); + acpigen_write_integer(0xE8); + acpigen_emit_namestring("^GPE2"); + + acpigen_pop_len(); /* Pop If */ + acpigen_write_else(); + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring("^GPE2"); + acpigen_write_integer(0x17); + acpigen_emit_namestring("^GPE2"); + + acpigen_pop_len(); /* Pop Else */ + + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("^^MSFG"); + acpigen_emit_byte(ONE_OP); + + acpigen_emit_byte(OR_OP); + acpigen_emit_namestring("^GPE2"); + acpigen_write_integer(0x10); + acpigen_emit_namestring("^GPE2"); + + acpigen_pop_len(); /* Pop If */ + acpigen_write_else(); + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring("^GPE2"); + acpigen_write_integer(0xEF); + acpigen_emit_namestring("^GPE2"); + + acpigen_pop_len(); /* Pop Else */ + + /* Enable wake on GPE */ + acpigen_write_store(); + acpigen_emit_byte(ONE_OP); + acpigen_emit_namestring("^GPEE"); + + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(3); + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring("^LEDC"); + acpigen_write_integer(0xE0); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_emit_byte(OR_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(0x1C); + acpigen_emit_namestring("^LEDC"); + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring("^SWCC"); + acpigen_write_integer(0xBF); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_emit_byte(OR_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(0x40); + acpigen_emit_namestring("^SWCC"); + + acpigen_pop_len(); /* Pop If */ + + acpigen_pop_len(); /* Pop If */ + + acpigen_write_store(); + acpigen_write_integer(0x10); + acpigen_emit_namestring("^GPE0"); + + acpigen_write_store(); + acpigen_write_integer(0x20); + acpigen_emit_namestring("^GPE1"); + + acpigen_pop_len(); /* Pop SIOS method */ + + acpigen_pop_len(); /* Pop Scope */ + + /* Inject into parent: */ + acpigen_write_scope(acpi_device_scope(dev)); + + acpigen_write_name_integer("MSFG", 1); + acpigen_write_name_integer("KBFG", 1); + acpigen_write_name_integer("PMFG", 0); + + /* DSDT must call SIOW on _WAK */ + /* Method (SIOW, 1, NotSerialized) */ + acpigen_write_method("SIOW", 1); + acpigen_emit_byte(RETURN_OP); + tmp_name = strconcat(name, ".SIOW"); + acpigen_emit_namestring(tmp_name); + free(tmp_name); + + acpigen_emit_byte(ARG0_OP); + acpigen_pop_len(); + + /* DSDT must call SIOS on _PTS */ + /* Method (SIOS, 1, NotSerialized) */ + acpigen_write_method("SIOS", 1); + acpigen_emit_byte(RETURN_OP); + tmp_name = strconcat(name, ".SIOS"); + acpigen_emit_namestring(tmp_name); + free(tmp_name); + acpigen_emit_byte(ARG0_OP); + acpigen_pop_len(); /* Pop Method */ + + acpigen_pop_len(); /* Scope */ + + acpigen_write_scope("\\_GPE"); + + /* Method (SIOH, 0, NotSerialized) */ + acpigen_write_method("_L08", 0); + acpigen_emit_byte(AND_OP); + tmp_name = strconcat(scope, ".PMFG"); + acpigen_emit_namestring(tmp_name); + free(tmp_name); + acpigen_write_integer(0xE8); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(ZERO_OP); + + acpigen_emit_byte(NOTIFY_OP); + tmp_name = strconcat(scope, ".L060"); + acpigen_emit_namestring(tmp_name); + free(tmp_name); + acpigen_write_integer(2); + + acpigen_pop_len(); /* Pop If */ + + acpigen_emit_byte(AND_OP); + tmp_name = strconcat(scope, ".PMFG"); + acpigen_emit_namestring(tmp_name); + free(tmp_name); + acpigen_write_integer(0x10); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(ZERO_OP); + + acpigen_emit_byte(NOTIFY_OP); + tmp_name = strconcat(scope, ".L050"); + acpigen_emit_namestring(tmp_name); + free(tmp_name); + acpigen_write_integer(2); + acpigen_pop_len(); /* Pop If */ + + acpigen_pop_len(); /* Pop Method */ + + acpigen_pop_len(); /* Scope */ +} + +static void npcd378_fill_ssdt_generator(struct device *dev) +{ + superio_common_fill_ssdt_generator(dev); + + switch (dev->path.pnp.device) { + case NPCD378_PWR: + npcd378_ssdt_pwr(dev); + break; + case NPCD378_AUX: + npcd378_ssdt_aux(dev); + break; + case NPCD378_KBC: + npcd378_ssdt_kbc(dev); + break; + } } #endif static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = npcd378_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = npcd378_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = npcd378_ssdt, - .acpi_name = npcd378_acpi_name, + .acpi_fill_ssdt_generator = npcd378_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = npcd378_acpi_hid, #endif }; From 977b8e83cb0a71af1143d3ab56fd0f95bf8d6c70 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 23 Jan 2020 13:32:08 +0100 Subject: [PATCH 0182/1463] mb/emulation/qemu-aarch64: Add MMU support Enable MMU in bootblock. Makes qemu look more similar to real hardware. There's no real need to activate the MMU. Tested on qemu-system-aarch64: 5 page entries are used out of 32. Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- .../emulation/qemu-aarch64/Makefile.inc | 2 ++ .../emulation/qemu-aarch64/bootblock.c | 33 +++++++++++++++++++ .../emulation/qemu-aarch64/memlayout.ld | 6 ++-- 3 files changed, 38 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/emulation/qemu-aarch64/bootblock.c diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc index dc0e9f462f..4d5f2bd5fa 100644 --- a/src/mainboard/emulation/qemu-aarch64/Makefile.inc +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -5,6 +5,8 @@ # # SPDX-License-Identifier: GPL-2.0-or-later +bootblock-y += bootblock.c + romstage-y += cbmem.c bootblock-y += media.c diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock.c b/src/mainboard/emulation/qemu-aarch64/bootblock.c new file mode 100644 index 0000000000..280f77ec1e --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/bootblock.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void bootblock_mainboard_init(void) +{ + mmu_init(); + + /* Everything below DRAM is device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram, MA_DEV | MA_RW); + /* Set a dummy value for DRAM. ramstage should update the mapping. */ + mmu_config_range(_dram, 1 * GiB, MA_MEM | MA_RW); + + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); + mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW); + mmu_config_range(_romstage, REGION_SIZE(romstage), MA_MEM | MA_S | MA_RW); + mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW); + + mmu_enable(); +} diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index aba4205750..248d0abef0 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -27,8 +27,8 @@ SECTIONS STACK(0x60020000, 62K) FMAP_CACHE(0x6002F800, 2K) ROMSTAGE(0x60030000, 128K) - RAMSTAGE(0x60070000, 16M) + TTB(0x60070000, 128K) + RAMSTAGE(0x600b0000, 16M) - TTB(0x61100000, 16K) - POSTRAM_CBFS_CACHE(0x61110000, 1M) + POSTRAM_CBFS_CACHE(0x61200000, 1M) } From 792fd51b14d1056514e2ddfeb24cf6436df828fb Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 23 Jan 2020 14:10:07 +0100 Subject: [PATCH 0183/1463] mb/emulation/qemu-aarch64: Add ARM trusted firmware support Linux expects a working PSCI and hangs if not found. Add BL31 into CBFS as '-M virt,secure=on -bios ' commands line arguments cause qemu's internal PSCI emulation to shutdown. BL31 is placed in qemu's SECURERAM memory region and won't conflict with resources in DRAM. Tested on qemu-system-aarch64: Fixes a hang and allows to boot into Linux 5.4.14 userspace. Change-Id: I809742522240185431621cc4fd8b9c7deaf2bb54 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38535 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese Reviewed-by: Arthur Heymans --- src/mainboard/emulation/qemu-aarch64/Kconfig | 1 + src/mainboard/emulation/qemu-aarch64/Makefile.inc | 2 ++ src/mainboard/emulation/qemu-aarch64/bootblock.c | 4 ++++ .../emulation/qemu-aarch64/include/mainboard/addressmap.h | 2 ++ src/mainboard/emulation/qemu-aarch64/mainboard.c | 8 ++++++++ src/mainboard/emulation/qemu-aarch64/memlayout.ld | 1 + 6 files changed, 18 insertions(+) diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 895446ddd7..0579b04c90 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT select MISSING_BOARD_RESET + select ARM64_USE_ARM_TRUSTED_FIRMWARE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc index 4d5f2bd5fa..b710f15587 100644 --- a/src/mainboard/emulation/qemu-aarch64/Makefile.inc +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -24,3 +24,5 @@ ramstage-y += memlayout.ld bootblock-y += bootblock_custom.S CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +BL31_MAKEARGS += PLAT=qemu ARM_ARCH_MAJOR=8 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock.c b/src/mainboard/emulation/qemu-aarch64/bootblock.c index 280f77ec1e..77d7e532de 100644 --- a/src/mainboard/emulation/qemu-aarch64/bootblock.c +++ b/src/mainboard/emulation/qemu-aarch64/bootblock.c @@ -15,6 +15,8 @@ #include #include +extern u8 _secram[], _esecram[]; + void bootblock_mainboard_init(void) { mmu_init(); @@ -29,5 +31,7 @@ void bootblock_mainboard_init(void) mmu_config_range(_romstage, REGION_SIZE(romstage), MA_MEM | MA_S | MA_RW); mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW); + mmu_config_range(_secram, REGION_SIZE(secram), MA_MEM | MA_S | MA_RW); + mmu_enable(); } diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h index 6f0c80257b..7233863934 100644 --- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h @@ -23,6 +23,7 @@ * 0x0905_0000..0x0907_0000: SMMU (smmu-v3) * 0x0a00_0000..0x0a00_0200: MMIO (virtio) * 0x0c00_0000..0x0e00_0000: Platform bus + * 0x0e00_0000..0x0eff_ffff: Secure SRAM * 0x4000_0000..: RAM */ #define VIRT_UART_BASE 0x09000000 @@ -32,3 +33,4 @@ #define VIRT_SMMU_BASE 0x09050000 #define VIRT_MMIO_BASE 0x0a000000 #define VIRT_PLATFORM_BUS_BASE 0x0c000000 +#define VIRT_SECRAM_BASE 0xe000000 diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index 573545532a..2980f483d8 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -10,6 +10,14 @@ #include #include #include +#include + +extern u8 _secram[], _esecram[]; + +void bootmem_platform_add_ranges(void) +{ + bootmem_add_range((uintptr_t)_secram, REGION_SIZE(secram), BM_MEM_BL31); +} static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index 248d0abef0..4af2362474 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -22,6 +22,7 @@ SECTIONS { REGION(flash, 0x00000000, CONFIG_ROM_SIZE, 8) + REGION(secram, 0xe000000, 0x1000000, 4096) DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) STACK(0x60020000, 62K) From aaf28d2507336b809b4420841b537652487439bd Mon Sep 17 00:00:00 2001 From: Usha P Date: Mon, 17 Feb 2020 15:14:18 +0530 Subject: [PATCH 0184/1463] soc/intel/apollolake: Display platform information This patch includes the change required to display Apollo Lake platform information which reports CPU, MCH, PCH and IGD information in romstage. BUG=None TEST= 1. Boot to OS on Bobba board. 2. Verified below info from CPU Console log in romstage CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz CPU: ID 706a1, Geminilake B0, ucode: 00000031 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 31f0 (rev 03) is Geminilake PCH: device id 3197 (rev 03) is Geminilake IGD: device id 3185 (rev 03) is Geminilake EU12 Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/38824 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 1 + .../intel/apollolake/include/soc/romstage.h | 1 + src/soc/intel/apollolake/report_platform.c | 170 ++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 1 + 4 files changed, 173 insertions(+) create mode 100644 src/soc/intel/apollolake/report_platform.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1fbdc91c72..b420dea64d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -24,6 +24,7 @@ bootblock-y += uart.c romstage-y += car.c romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += romstage.c +romstage-y += report_platform.c romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index da30de54e5..3466abe9ce 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -23,5 +23,6 @@ void set_max_freq(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void mainboard_save_dimm_info(void); +void report_platform_info(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c new file mode 100644 index 0000000000..6f4c74ebf5 --- /dev/null +++ b/src/soc/intel/apollolake/report_platform.c @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_APOLLOLAKE_A0, "Apollolake A0" }, + { CPUID_APOLLOLAKE_B0, "Apollolake B0" }, + { CPUID_APOLLOLAKE_E0, "Apollolake E0" }, + { CPUID_GLK_A0, "Geminilake A0" }, + { CPUID_GLK_B0, "Geminilake B0" }, + { CPUID_GLK_R0, "Geminilake R0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_GLK_NB, "Geminilake" }, + { PCI_DEVICE_ID_INTEL_APL_NB, "Apollolake" }, +}; + +static struct { + u16 lpcid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_APL_LPC, "Apollolake" }, + { PCI_DEVICE_ID_INTEL_GLK_LPC, "Geminilake" }, + { PCI_DEVICE_ID_INTEL_GLK_ESPI, "Geminilake" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, "Apollolake HD 505" }, + { PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, "Aplollolake HD 500" }, + { PCI_DEVICE_ID_INTEL_GLK_IGD, "Geminilake" }, + { PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, "Geminilake EU12" }, +}; + +static uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + uint32_t i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + msr_t microcode_ver; + const char *support = "Supported"; + const char *no_support = "Not Supported"; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); + cpu_id = cpu_get_cpuid(); + microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_INFO, "CPU: %s\n", cpu_name); + printk(BIOS_INFO, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, microcode_ver.hi); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + printk(BIOS_INFO, "CPU: AES %s, TXT %s, VT %s\n", + (cpu_feature_flag & CPUID_AES) ? support : no_support, + (cpu_feature_flag & CPUID_SMX) ? support : no_support, + (cpu_feature_flag & CPUID_VMX) ? support : no_support); +} + +static void report_mch_info(void) +{ + uint32_t i; + pci_devfn_t dev = SA_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + uint8_t mch_revision = get_dev_revision(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_INFO, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + uint32_t i; + pci_devfn_t dev = PCH_DEV_LPC; + uint16_t lpcid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].lpcid == lpcid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_INFO, "PCH: device id %04x (rev %02x) is %s\n", + lpcid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + uint32_t i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_INFO, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 258f4ffaf3..13adeeef40 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -198,6 +198,7 @@ void mainboard_romstage_entry(void) const void *new_var_data; soc_early_romstage_init(); + report_platform_info(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); From c2a2d2ba268561fe0d4f076702a77071d6d6b57a Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 27 Feb 2020 17:16:13 +0530 Subject: [PATCH 0185/1463] soc/intel/common: Remove HOST_RESET_ONLY reset type support Remove HOST_RESET_ONLY reset type of GLOBAL_RESET HECI command as it is not supported. Change-Id: I17171e1e5fe79710142369499d3d904a5ba98636 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/39149 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Angel Pons --- src/soc/intel/common/block/cse/cse.c | 6 ++---- src/soc/intel/common/block/include/intelblocks/cse.h | 1 - 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 48c26f3897..b24a99a7f3 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -609,8 +609,7 @@ uint32_t me_read_config32(int offset) } /* - * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/ - * HOST_RESET_ONLY/CSE_RESET_ONLY. + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/CSE_RESET_ONLY. */ int cse_request_global_reset(enum rst_req_type rst_type) { @@ -632,8 +631,7 @@ int cse_request_global_reset(enum rst_req_type rst_type) size_t reply_size; printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); - if (!((rst_type == GLOBAL_RESET) || - (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) { + if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) { printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); return 0; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 59ddc5b5d5..2b07092307 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -121,7 +121,6 @@ uint8_t cse_wait_sec_override_mode(void); enum rst_req_type { GLOBAL_RESET = 1, - HOST_RESET_ONLY = 2, CSE_RESET_ONLY = 3, }; From 24a974a8cbbbf0009cbbec3f5dc11aa8e35c26a8 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 19 Feb 2020 14:41:36 +0530 Subject: [PATCH 0186/1463] soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE lib Move print_me_fw_version(), remove print_me_version/dump_me_version from cnl/skl/apl and make changes to call print_me_version() which is defined in the CSE lib. TEST=Verified on hatch, soraka and bobba. Change-Id: I7567fac100b14dc207b7fc6060e7a064fb05caf6 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/39010 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/soc/intel/apollolake/cse.c | 58 +------------- src/soc/intel/cannonlake/me.c | 80 +------------------ src/soc/intel/common/block/cse/cse.c | 61 ++++++++++++++ .../common/block/include/intelblocks/cse.h | 9 +++ src/soc/intel/skylake/include/soc/me.h | 4 - src/soc/intel/skylake/me.c | 80 ++----------------- 6 files changed, 78 insertions(+), 214 deletions(-) diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 6ee1a155ea..2445289385 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -36,9 +36,6 @@ #define READ_FILE_FLAG_EMULATED (1 << 2) #define READ_FILE_FLAG_HW (1 << 3) -#define MKHI_GROUP_ID_GEN 0xff -#define GET_FW_VERSION 0x02 - #define MCA_MAX_FILE_PATH_SIZE 64 #define FUSE_LOCK_FILE "/fpf/intel/SocCfgLock" @@ -180,59 +177,6 @@ static uint32_t dump_status(int index, int reg_addr) return reg; } -static void dump_cse_version(void *unused) -{ - int res; - size_t reply_size; - struct mkhi_hdr msg; - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_version_response { - struct mkhi_hdr hdr; - struct version code; - struct version nftp; - struct version fitc; - } __packed rsp; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes - * ~0.6 second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - msg.group_id = MKHI_GROUP_ID_GEN; - msg.command = GET_FW_VERSION; - - res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); - - if (!res) { - printk(BIOS_ERR, "Failed to send HECI message.\n"); - return; - } - - reply_size = sizeof(rsp); - res = heci_receive(&rsp, &reply_size); - - if (!res) { - printk(BIOS_ERR, "Failed to receive HECI reply.\n"); - return; - } - - if (rsp.hdr.result != 0) { - printk(BIOS_ERR, "Failed to get ME version.\n"); - return; - } - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", rsp.code.major, - rsp.code.minor, rsp.code.hotfix, rsp.code.build); -} - static void dump_cse_state(void) { uint32_t fwsts1; @@ -289,4 +233,4 @@ void heci_cse_lockdown(void) } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fpf_blown, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, dump_cse_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, print_me_fw_version, NULL); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 3d3fcb8ded..d41b0b8bc8 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -23,14 +23,6 @@ #include #include -/* Miscellaneous constants */ -enum { - MKHI_GEN_GROUP_ID = 0xFF, - MKHI_GET_FW_VERSION = 0x02, - ME_OPMODE_NORMAL = 0x00, - ME_WSTATE_NORMAL = 0x05, -}; - /* Host Firmware Status Register 2 */ union me_hfsts2 { uint32_t raw; @@ -115,76 +107,6 @@ union me_hfsts6 { } __packed fields; }; -/* - * From reading the documentation, this should work for both WHL and CML - * platforms. Also, calling this function from dump_me_status() does not - * work, as the ME does not respond and the command times out. - */ -static void print_me_version(void *unused) -{ - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - union me_hfsts1 hfsts1; - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - - /* Ignore if UART debugging is disabled */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - if (!is_cse_enabled()) - return; - - hfsts1.data = me_read_config32(PCI_ME_HFSTS1); - - /* - * Prerequisites: - * 1) HFSTS1 Current Working State is Normal - * 2) HFSTS1 Current Operation Mode is Normal - * 3) It's after DRAM INIT DONE message (taken care of by calling it - * during ramstage - */ - if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || - (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) - goto fail; - - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, - HECI_MKHI_ADDR)) - goto fail; - - if (!heci_receive(&resp, &resp_size)) - goto fail; - - if (resp.hdr.result) - goto fail; - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -fail: - printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); -} -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); - void dump_me_status(void *unused) { union me_hfsts1 hfsts1; @@ -250,5 +172,5 @@ void dump_me_status(void *unused) printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); } - +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index b24a99a7f3..c9712dbb2c 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -754,6 +754,67 @@ int cse_hmrfpo_get_status(void) return resp.status; } +void print_me_fw_version(void *unused) +{ + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_ver_resp { + struct mkhi_hdr hdr; + struct version code; + struct version rec; + struct version fitc; + } __packed; + + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_GEN_GET_FW_VERSION, + }; + + struct fw_ver_resp resp; + size_t resp_size = sizeof(resp); + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + /* + * Ignore if ME Firmware SKU type is custom since + * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. + */ + if (cse_is_hfs3_fw_sku_custom()) + return; + + /* + * Prerequisites: + * 1) HFSTS1 Current Working State is Normal + * 2) HFSTS1 Current Operation Mode is Normal + * 3) It's after DRAM INIT DONE message (taken care of by calling it + * during ramstage + */ + if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) + goto fail; + + heci_reset(); + + if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size)) + goto fail; + + if (resp.hdr.result) + goto fail; + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + +fail: + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 2b07092307..93d1ce1d04 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -22,6 +22,7 @@ /* MKHI Command groups */ #define MKHI_GROUP_ID_CBM 0x0 #define MKHI_GROUP_ID_HMRFPO 0x5 +#define MKHI_GROUP_ID_GEN 0xff /* Global Reset Command ID */ #define MKHI_CBM_GLOBAL_RESET_REQ 0xb @@ -33,6 +34,9 @@ #define MKHI_HMRFPO_ENABLE 0x1 #define MKHI_HMRFPO_GET_STATUS 0x3 +/* Get Firmware Version Command Id */ +#define MKHI_GEN_GET_FW_VERSION 0x2 + /* ME Current Working States */ #define ME_HFS1_CWS_NORMAL 0x5 @@ -163,6 +167,11 @@ int cse_hmrfpo_get_status(void); /* Host can access ME region */ #define MKHI_HMRFPO_ENABLED 2 +/* + * Queries and logs ME firmware version + */ +void print_me_fw_version(void *unused); + /* * Checks current working operation state is normal or not. * Returns true if CSE's current working state is normal, otherwise false. diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 332340f860..2f581fb3b8 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -192,10 +192,6 @@ union me_hfsts6 { } __packed fields; }; -#define MKHI_GEN_GROUP_ID 0xff - -#define MKHI_GET_FW_VERSION 0x02 - void intel_me_status(void); int send_global_reset(void); diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index b45234ec65..45a7c485ea 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -196,80 +196,6 @@ static const char *const me_progress_bup_values[] = { "M0 kernel load", }; -static void print_me_version(void *unused) -{ - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - union me_hfsts1 hfs1; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes ~1 - * second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - if (!is_cse_enabled()) - return; - - hfs1.data = me_read_config32(PCI_ME_HFSTS1); - /* - * This command can be run only if: - * - Working state is normal and - * - Operation mode is normal. - */ - if ((hfs1.fields.working_state != ME_HFS_CWS_NORMAL) || - (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL)) - goto failed; - - /* - * It is important to do a heci_reset to ensure BIOS and ME are in sync - * before reading firmware version. - */ - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, - HECI_MKHI_ADDR)) - goto failed; - - if (!heci_receive(&resp, &resp_size)) - goto failed; - - if (resp.hdr.result) - goto failed; - - printk(BIOS_DEBUG, "ME: Version : %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -failed: - printk(BIOS_DEBUG, "ME: Version : Unavailable\n"); -} -/* - * This can't be put in intel_me_status because by the time control - * reaches there, ME doesn't respond to GET_FW_VERSION command. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); - void intel_me_status(void) { union me_hfsts1 hfs1; @@ -445,3 +371,9 @@ int send_global_reset(void) ret: return status; } + +/* + * This can't be put in intel_me_status because by the time control + * reaches there, ME doesn't respond to GET_FW_VERSION command. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); From 0751d7bded12440e6228e88b12ce212dcbc7d645 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 26 Feb 2020 14:09:04 +0100 Subject: [PATCH 0187/1463] Documentation: Add tutorial for me_cleaner on Lenovo devices Add a tutorial how to use ME cleaner, and give some basic steps to strip the ME. Update the Lenovo Sandy Bridge documentation that no issues could be observed on X220 and give an example flash layout. Tested on Lenovo X220 with stripped ME and found no issues: commit: cbc5b99ac9e5856631109b1e7f20e80799beb1e4 * Displayport * VGA * USB * Bluetooth * Wifi * Wifi-kill switch * libgfxinit * SATA * Audio * SD-card * Ethernet * Keyboard * Fn-Keys * Display brightness * ACPI S3 resume * Battery events * CPU temperature reporting * FAN managment * Stress test stable * Youtube videos over Wifi * stress -c 2 -m 1 -d 1 * glxgears Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129 Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../mainboard/lenovo/Sandy_Bridge_series.md | 27 ++++++- .../flashlayout_Sandy_Bridge_stripped_me.svg | 74 +++++++++++++++++++ .../intel/sandybridge/me_cleaner.md | 66 ++++++++++++++++- 3 files changed, 163 insertions(+), 4 deletions(-) create mode 100644 Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 0b833f5cc8..dbbbbeef30 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -33,9 +33,7 @@ usable by coreboot. * ROM chip size should be set to 8MiB. -```eval_rst -Please also have a look at :doc:`../../flash_tutorial/index`. -``` +Please also have a look at the [flashing tutorial] ## Flash layout There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions. @@ -46,3 +44,26 @@ region. The update is then written into the EC once. [fl]: flashlayout_Sandy_Bridge.svg +## Reducing Intel Managment Engine firmware size + +It is possible to reduce the Intel ME firmware size to free additional +space for the `bios` region. This is usually refered to as *cleaning the ME* or +*stripping the ME*. +After reducing the Intel ME firmware size you must modify the original IFD +and then write a full ROM using an [external programmer]. +Have a look at the [me_cleaner] for more information. + +Tests on Lenovo X220 showed no issues with a stripped ME firmware. + +**Modified flash layout:** + +![][fl2] + +[fl2]: flashlayout_Sandy_Bridge_stripped_me.svg + +The overall size of the `gbe`, `me,` `ifd` region is less than 128KiB, leaving +the remaining space for the `bios` partition. + + +[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md +[external programmer]: ../../flash_tutorial/index.md diff --git a/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg new file mode 100644 index 0000000000..d8d8213d12 --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg @@ -0,0 +1,74 @@ + + + + + + + + + + + + + + IFD + + + + + + + + + + + + BIOS + + + + + + + + + + + + GBE + + + + 0x000000 + + + 0x001000 + + + 0x003000 + + + 0x020000 + + + 0x800000 + + + + + Flash #0 + + + + + + + + + + + + ME + + + diff --git a/Documentation/northbridge/intel/sandybridge/me_cleaner.md b/Documentation/northbridge/intel/sandybridge/me_cleaner.md index 1086e7e091..b457dcdd3c 100644 --- a/Documentation/northbridge/intel/sandybridge/me_cleaner.md +++ b/Documentation/northbridge/intel/sandybridge/me_cleaner.md @@ -5,7 +5,7 @@ from the ME firmware partition. In this state the ME errors out and doesn't operate any more. **Using a 'cleaned' ME partition may lead to issues and its use should be -carefully evaulated.** +carefully evaluated.** ## Observations with 'cleaned' ME @@ -18,3 +18,67 @@ carefully evaulated.** Always test with unmodified IFD and ME section before reporting bugs to the coreboot project. + +## Tutorial reducing the Intel ME firmware size + +By default the cleaned ME firmware will still occupy the same space in +the firmware image. It's possible to change the firmware partition layout +and reclaim the space for the use by coreboot. +With the reduced Intel ME firmware the `ifd`, `gbe` and `me` regions require +less than 128 KiB of space in the ROM, which leaves the remaining for the +`bios` region. + +This tutorial will guide you through the steps necessary. + +### 1. Obtain a full ROM + +You need a full and working ROM with a full Intel ME firmware. + +### 2. Running me_cleaner + +You need to run the *me_cleaner* on a full ROM, here called `fulldump.rom`: +The full ROM contains: +* IFD +* fully working Intel ME +* GbE (optional) +* BIOS (any firmware) + +Running the command will generate two new files: +```console +./util/me_cleaner/me_cleaner.py -D patched_desciptor.bin -M stripped_me.bin fulldump.rom -t -r -S +``` + +The generated files are: +* a patched IFD called `patched_desciptor.bin` +* stripped Intel ME called `stripped_me.bin` + +The patched IFD has the *AltMeDisable* bit set and a modified flash layout. + + +*Note:* coreboot allows to select `CONFIG_ME_CLEANER` as part of the +build-process, but that doesn't rework the flash layout, it only removes +files from ME and sets the *AltMeDisable*-bit. + +### 3. Build coreboot + +1. Now include the two new files from the previous step into coreboot's + build system. +2. Make sure to also increase the CBFS size + * 0x7E0000 for a 8MiB ROM + * 0xBE0000 for a 12MiB ROM + * 0xFE0000 for a 16MiB ROM +3. Make sure to **not** enable me_cleaner in Kconfig again as + you have already run it + +### 4. Flashing the ROM + +As you have modified the layout you need to write the **full ROM** to flash +using an [external programmer]. +Make sure to include all partitions into the ROM: +* IFD +* EC (might be unused) +* GbE (might be unused) +* ME +* BIOS + +[external programmer]: ../../../flash_tutorial/index.md From 4d9dd22bd1235717d623916f641ce69a6556a5b2 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 27 Feb 2020 14:06:53 +0100 Subject: [PATCH 0188/1463] Documentation: Add Heads to payloads Add a small description about Heads. Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39150 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- Documentation/payloads.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/payloads.md b/Documentation/payloads.md index b1eae615ec..eee841eacd 100644 --- a/Documentation/payloads.md +++ b/Documentation/payloads.md @@ -40,3 +40,15 @@ availability of well-tested, battle-hardened drivers (as compared to firmware project drivers that often reinvent the wheel) and the ability to define boot policy with familiar tools, no matter if those are shell scripts or compiled userland programs written in C, Go or other programming languages. + +## Heads + +[Heads] is a distribution that bundles coreboot, Linux, busybox and custom +tools to provide reproducible ROMs. [Heads] aims to provide a secure and +flexible boot environment for laptops and servers. +It supports features like measured boot, kexec, GPG, OTP, TLS, firmware +updates, but only works on a limited amount of mainboards. +For more details have a look at [heads-wiki]. + +[Heads]: https://github.com/osresearch/heads +[heads-wiki]: http://osresearch.net/ \ No newline at end of file From 310623b2dd192a44caa1a3ee9471127ec3d6cf5e Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 26 Feb 2020 11:02:53 -0800 Subject: [PATCH 0189/1463] arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio Add new helper function in the acpigen library, that use the underlying soc routines. Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7 Signed-off-by: Rajat Jain Reviewed-on: https://review.coreboot.org/c/coreboot/+/39145 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- Documentation/acpi/gpio.md | 9 +++++++++ src/arch/x86/acpigen.c | 17 +++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 10 ++++++++++ 3 files changed, 36 insertions(+) diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md index d42042f36f..abde3a0d3d 100644 --- a/Documentation/acpi/gpio.md +++ b/Documentation/acpi/gpio.md @@ -73,6 +73,15 @@ calling the platform specific acpigen_soc_{set,clear}_tx_gpio functions internally. Thus, all the ACPI AML calling conventions for the platform functions apply to these helper functions as well. +3. Get Rx GPIO + int acpigen_get_rx_gpio(struct acpi_gpio gpio) + +This function takes as input, an struct acpi_gpio type and outputs +AML code to read the *logical* value of a gpio (after taking its +polarity into consideration), into the Local0 variable. It calls +the platform specific acpigen_soc_read_rx_gpio() to actually read +the raw Rx gpio value. + ## Implementation Details ACPI library in coreboot will provide weak definitions for all the diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 72605bb766..9162cdb371 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1203,6 +1203,15 @@ void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res) acpigen_emit_byte(res); } +/* Xor (arg1, arg2, res) */ +void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res) +{ + acpigen_emit_byte(XOR_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); + acpigen_emit_byte(res); +} + /* And (arg1, arg2, res) */ void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res) { @@ -1759,6 +1768,14 @@ int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) return acpigen_soc_clear_tx_gpio(gpio->pins[0]); } +void acpigen_get_rx_gpio(struct acpi_gpio *gpio) +{ + acpigen_soc_read_rx_gpio(gpio->pins[0]); + + if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW) + acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); +} + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 08075585ca..34c5197468 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -361,6 +361,7 @@ void acpigen_write_sleep(uint64_t sleep_ms); void acpigen_write_store(void); void acpigen_write_store_ops(uint8_t src, uint8_t dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_not(uint8_t arg, uint8_t res); void acpigen_write_debug_string(const char *str); @@ -472,6 +473,14 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num); int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); +/* + * Helper function for getting a RX GPIO value based on the GPIO polarity. + * The return value is stored in Local0 variable. + * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks + * into SoC acpigen code + */ +void acpigen_get_rx_gpio(struct acpi_gpio *gpio); + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length); @@ -481,4 +490,5 @@ void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, /* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); + #endif From 7ef06b0234706455d4f24375a9389d718e34dbbb Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 26 Feb 2020 23:28:02 -0800 Subject: [PATCH 0190/1463] drivers/gfx/generic: Add support for gpio based EPS Add support to control EPS via a PCH gpio Change-Id: I6f570fd43e1649fb23255b0890e01086e34f844a Signed-off-by: Rajat Jain Reviewed-on: https://review.coreboot.org/c/coreboot/+/39154 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- src/drivers/gfx/generic/chip.h | 10 ++++ src/drivers/gfx/generic/generic.c | 76 ++++++++++++++++++++++++++----- 2 files changed, 75 insertions(+), 11 deletions(-) diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index 5e855e3853..714a8aba84 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -16,6 +16,8 @@ #ifndef __DRIVERS_GFX_GENERIC_CHIP_H__ #define __DRIVERS_GFX_GENERIC_CHIP_H__ +#include + /* Config for electronic privacy screen */ struct drivers_gfx_generic_privacy_screen_config { /* Is privacy screen available on this graphics device */ @@ -28,6 +30,12 @@ struct drivers_gfx_generic_privacy_screen_config { const char *enable_function; /* ACPI namespace path to privacy screen disable function */ const char *disable_function; + /* + * GPIO used for controlling the privacy screen. If provided, + * the gpio mechanism takes preference over the functions ptrs + * above, if any (GPIO functions override the function ptrs). + */ + struct acpi_gpio gpio; }; /* Config for an output device as defined in section A.5 of the ACPI spec */ @@ -53,4 +61,6 @@ struct drivers_gfx_generic_config { struct drivers_gfx_generic_device_config device[5]; }; +extern struct device *find_gfx_dev(void); + #endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */ diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 8488040d30..0b3fccafde 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -24,6 +24,11 @@ #define ACPI_DSM_PRIVACY_SCREEN_UUID "C7033113-8720-4CEB-9090-9D52B3E52D73" +#define ACPI_METHOD_EPS_PRESENT "EPSP" +#define ACPI_METHOD_EPS_STATE "EPSS" +#define ACPI_METHOD_EPS_ENABLE "EPSE" +#define ACPI_METHOD_EPS_DISABLE "EPSD" + static void privacy_screen_detect_cb(void *arg) { struct drivers_gfx_generic_privacy_screen_config *config = arg; @@ -62,6 +67,52 @@ static void (*privacy_screen_callbacks[])(void *) = { privacy_screen_disable_cb, }; +static void privacy_gpio_acpigen(struct acpi_gpio *gpio) +{ + /* EPS Present */ + acpigen_write_method(ACPI_METHOD_EPS_PRESENT, 0); + acpigen_write_return_byte(1); + acpigen_pop_len(); + + /* EPS State */ + acpigen_write_method(ACPI_METHOD_EPS_STATE, 0); + acpigen_get_rx_gpio(gpio); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); + + /* EPS Enable */ + acpigen_write_method(ACPI_METHOD_EPS_ENABLE, 0); + acpigen_enable_tx_gpio(gpio); + acpigen_pop_len(); + + /* EPS Disable */ + acpigen_write_method(ACPI_METHOD_EPS_DISABLE, 0); + acpigen_disable_tx_gpio(gpio); + acpigen_pop_len(); +} + +static void gfx_fill_privacy_screen_dsm( + struct drivers_gfx_generic_privacy_screen_config *privacy) +{ + if (!privacy->enabled) + return; + + /* Populate ACPI methods, if EPS controlled via gpio */ + if (privacy->gpio.pin_count == 1) { + privacy_gpio_acpigen(&privacy->gpio); + privacy->detect_function = ACPI_METHOD_EPS_PRESENT; + privacy->status_function = ACPI_METHOD_EPS_STATE; + privacy->enable_function = ACPI_METHOD_EPS_ENABLE; + privacy->disable_function = ACPI_METHOD_EPS_DISABLE; + } + + acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, + privacy_screen_callbacks, + ARRAY_SIZE(privacy_screen_callbacks), + privacy); +} + static void gfx_fill_ssdt_generator(struct device *dev) { size_t i; @@ -69,7 +120,7 @@ static void gfx_fill_ssdt_generator(struct device *dev) const char *scope = acpi_device_scope(dev); - if (!scope) + if (!scope || !dev->enabled) return; acpigen_write_scope(scope); @@ -85,17 +136,9 @@ static void gfx_fill_ssdt_generator(struct device *dev) for (i = 0; i < config->device_count; i++) { acpigen_write_device(config->device[i].name); - acpigen_write_name_integer("_ADR", config->device[i].addr); acpigen_write_name_integer("_STA", 0xF); - - if (config->device[i].privacy.enabled) { - acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, - privacy_screen_callbacks, - ARRAY_SIZE(privacy_screen_callbacks), - &config->device[i].privacy); - } - + gfx_fill_privacy_screen_dsm(&config->device[i].privacy); acpigen_pop_len(); /* Device */ } acpigen_pop_len(); /* Scope */ @@ -117,7 +160,7 @@ static void gfx_enable(struct device *dev) { struct drivers_gfx_generic_config *config = dev->chip_info; - if (!config) + if (!config || !dev->enabled) return; dev->ops = &gfx_ops; @@ -127,3 +170,14 @@ struct chip_operations drivers_gfx_generic_ops = { CHIP_NAME("Generic Graphics Device") .enable_dev = gfx_enable }; + +struct device *find_gfx_dev(void) +{ + struct device *dev; + + for (dev = all_devices; dev; dev = dev->next) { + if (dev->chip_ops && dev->chip_ops == &drivers_gfx_generic_ops) + return dev; + } + return NULL; +} From 68cd0d0b2cbc5dbfab25f204122986d64996d166 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 26 Feb 2020 21:10:54 -0800 Subject: [PATCH 0191/1463] mb/google/hatch/var/jinlon: Enable gfx/generic driver Enable the GFX device for Jinlon. Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a Signed-off-by: Rajat Jain Reviewed-on: https://review.coreboot.org/c/coreboot/+/39155 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- src/mainboard/google/hatch/Kconfig.name | 1 + .../google/hatch/variants/jinlon/overridetree.cb | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 2427b12bf4..fc3a66e92e 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -19,6 +19,7 @@ config BOARD_GOOGLE_JINLON bool "-> Jinlon" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index f3f6c3b949..f7ca7d5c39 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -65,6 +65,17 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E0)" + device generic 0 on end + end + end # Integrated Graphics Device device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" From c0380a24e8f487af72fe07e2c1c2602ceb0cc519 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Thu, 27 Feb 2020 00:22:12 -0800 Subject: [PATCH 0192/1463] mb/google/hatch/var/jinlon: Disable EPS on some SKUs Disable EPS on the SKUs that do not have it. Change-Id: I7305097beea3484634933ab856fd084933868a10 Signed-off-by: Rajat Jain Reviewed-on: https://review.coreboot.org/c/coreboot/+/39156 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- .../google/hatch/variants/jinlon/Makefile.inc | 1 + .../variants/jinlon/include/variant/sku.h | 23 ++++++++ .../google/hatch/variants/jinlon/mainboard.c | 55 +++++++++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h create mode 100644 src/mainboard/google/hatch/variants/jinlon/mainboard.c diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index c57d0908ab..d38a5771bb 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -25,4 +25,5 @@ SPD_SOURCES += 16G_3200_4bg # 0b1001 bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += mainboard.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h new file mode 100644 index 0000000000..1d45fcddcd --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __JINLON_SKU_H__ +#define __JINLON_SKU_H__ + +/* + * SKU definition taken from + * https://buganizer.corp.google.com/issues/145688887#comment16 + */ +enum { + JINLON_SKU_01 = 1, /* No LTE, No view-angle-manegement */ + JINLON_SKU_02 = 2, /* No LTE, view-angle-manegement */ + JINLON_SKU_21 = 21, /* LTE, No view-angle-manegement */ + JINLON_SKU_22 = 22, /* LTE, view-angle-manegement */ +}; + +#endif /* __JINLON_SKU_H__ */ diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c new file mode 100644 index 0000000000..db041c4ca8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include +#include +#include + +static bool eps_sku(uint32_t sku_id) +{ + /* + * Assume EPS SKU by default, helpful for testing on + * unprovisioned or development SKUs. + */ + if (sku_id == JINLON_SKU_01 || sku_id == JINLON_SKU_21) + return false; + else + return true; +} + +static void check_for_eps(uint32_t sku_id) +{ + struct device *gfx_dev; + + if (eps_sku(sku_id)) { + printk(BIOS_INFO, "SKU ID %u has EPS\n", sku_id); + return; + } + + gfx_dev = find_gfx_dev(); + if (!gfx_dev) { + printk(BIOS_ERR, + "Error! No EPS dev, view-angle-management won't work\n"); + return; + } + + printk(BIOS_INFO, + "SKU ID %u doesn't have EPS, disabling...\n", + sku_id); + gfx_dev->enabled = 0; +} + +void variant_devtree_update(void) +{ + uint32_t sku_id = google_chromeec_get_board_sku(); + + /* Disable EPS on SKUs that do not support it */ + check_for_eps(sku_id); +} From a1d7db8215add95fa8f8e26c07edc0c12fb183db Mon Sep 17 00:00:00 2001 From: Tommie Date: Tue, 11 Feb 2020 12:53:34 +0800 Subject: [PATCH 0193/1463] mb/google/octopus: support new Elan touch panel for Foob This is new elan touch screen IC, which includes touch panel and USI pen. BUG=b:149800883 BRANCH=octopus TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823 Tested-by: build bot (Jenkins) Reviewed-by: Henry Sun Reviewed-by: Marco Chen --- .../octopus/variants/foob/overridetree.cb | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index b1311737dc..004076d047 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -134,16 +134,17 @@ chip soc/intel/apollolake end end # - I2C 6 device pci 17.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end chip drivers/i2c/hid From 9ab4dc32b43e4c49de710123769de9acc09e7a0f Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Mon, 24 Feb 2020 17:39:05 -0800 Subject: [PATCH 0194/1463] vendorcode/intel/fsp/fsp2_0: Add FSP header files for Skylake-SP Add header files for FSP of Skylake Scalable Processor. These header files are from an Intel SKX-SP FSP engineering build. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Tested-by: johnny_lin@wiwynn.com Change-Id: If47f102c2c7979da1196f8c6b315d5be558e786c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39108 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- .../intel/fsp/fsp2_0/skylake_sp/FspUpd.h | 48 ++ .../intel/fsp/fsp2_0/skylake_sp/FspmUpd.h | 545 ++++++++++++++++++ .../intel/fsp/fsp2_0/skylake_sp/FspsUpd.h | 198 +++++++ .../intel/fsp/fsp2_0/skylake_sp/FsptUpd.h | 108 ++++ .../intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h | 244 ++++++++ .../intel/fsp/fsp2_0/skylake_sp/hob_memmap.h | 119 ++++ 6 files changed, 1262 insertions(+) create mode 100644 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h new file mode 100644 index 0000000000..daa0bb4d3a --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C4E41 /* 'ANLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E41 /* 'ANLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C4E41 /* 'ANLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h new file mode 100644 index 0000000000..80ca157bb4 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -0,0 +1,545 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + +/** + FSP Header Version Number +**/ +#define FSP_UPD_VERSION (0x1947) + +#define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */ +#define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */ + +/** + IIO PCIe Ports + **/ +typedef enum { + PORT_0 = 0, + // IOU2 + PORT_1A, + PORT_1B, + PORT_1C, + PORT_1D, + // IOU0 + PORT_2A, + PORT_2B, + PORT_2C, + PORT_2D, + // IOU1 + PORT_3A, + PORT_3B, + PORT_3C, + PORT_3D, + // MCP0 + PORT_4A, + PORT_4B, + PORT_4C, + PORT_4D, + // MCP1 + PORT_5A, + PORT_5B, + PORT_5C, + PORT_5D, + MAX_PORTS +} PCIE_PORTS; + +/** + IIO Stacks + **/ +typedef enum { + CSTACK = 0, + PSTACK0, + PSTACK1, + PSTACK2, + PSTACK3, + PSTACK4, + MAX_STACKS +} IIO_STACKS; + +/** + NTB Per Port Definition + **/ +typedef enum { + NTB_PORT_TRANSPARENT = 0, + NTB_PORT_NTB_NTB +} NTB_PPD; + +/** + NTB Upstream/Downstream Configuration + **/ +typedef enum { + NTB_XLINK_DSD_USP = 2, + NTB_XLINK_USD_DSP +} NTB_XLINK; + +/** + PCIe Link Speed Selection + **/ +typedef enum { + PcieAuto = 0, + PcieGen1, + PcieGen2, + PcieGen3 +} PCIE_LINK_SPEED; + +/** + GPIO Pad Number +**/ + +typedef UINT32 UPD_GPIO_PAD; + +/** + UPD_GPIO_CONFIG: + 64 bit struct defining GPIO PAD configuration +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig and Host Software Pad Ownership are unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 4; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion Out, both In and Out, + both In with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 5; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting + is applicable only if GPIO is in input mode. + If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 8; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 4; + + /** + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 7; + + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 3; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 2; + + UINT32 RsvdBits : 27; ///< Reserved bits for future extension + + UINT32 RsvdBits1; ///< Reserved bits for future extension +} UPD_GPIO_CONFIG; + +/** + UPD_GPIO_INIT_CONFIG: + Defines a GPIO Pad and its respective configuration + Constitutes one entry in the GPIO config table + Reference FSP implementation: + AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\GpioTable.c + Bootloaders can include the following to define GPIO PADs/other macros: + PurleySktPkg\SouthClusterLbg\Include\Library\GpioLib.h +**/ +typedef struct { + UPD_GPIO_PAD GpioPad; + UPD_GPIO_CONFIG GpioConfig; +} UPD_GPIO_INIT_CONFIG; + +/** + GPIOTABLE_CONFIG: + GpioTable - Base Address of the Gpio Table declared by the + bootloader. + Default: NULL + NumberofEntries - Number of Entries in the GPIO Table provided + Default: 0 + If GpioTable is Null or NumberofEntries is 0, then FSP will handle Gpio Pad + configuration using default GPIO_INIT_CONFIG tables +**/ +typedef struct { + UPD_GPIO_INIT_CONFIG *GpioTable; + UINT32 NumberOfEntries; +} GPIOTABLE_CONFIG; + +/** + UPD_IIO_BIFURCATION_DATA_ENTRY: + Defines IIO Bifurcation for IIO Units + Constitutes one entry in the IIO Bifurcation table, describing bifurcation entries as: + Socket | IOU | Bifurcation + Valid IouNumbers are from 0 to 4 + Reference FSP Implementation : + AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\IioBifurInit.c + Definitions for relevant bifurcation macros: + NumberCpRcPkg\Library\BaseMemoryCoreLib\Chip\Skx\Include\Iio\IioRegs.h +**/ +typedef struct { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; +} UPD_IIO_BIFURCATION_DATA_ENTRY; + +/** + IIOBIFURCATION_CONFIG: + IIoBifurcationTable - Base Address of the IIO Bifurcation table + declared by the bootloader + Default: NULL + NumberofEntries - Number of Entries in the IIO Bifurcation Table + Default: 0 + If IIoBifurcationTable is Null or NumberofEntries is 0, then FSP will handle IIO + bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables +**/ +typedef struct { + UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable; + UINT32 NumberOfEntries; +} IIOBIFURCATION_CONFIG; + +/** + VTD_CONFIG : + VT direct IO Configuration Support + VTdSupport - Enable/Disable VTd Support + CoherencySupport - Enable/Disable Coherency Support + ATS - Enable/Disable Address Translation Services + FSP Will Disable VTd by default +**/ +typedef struct { + UINT8 VTdSupport; + UINT8 CoherencySupport; + UINT8 ATS; +} VTD_CONFIG; + +/** + UPD_PCIE_PORT_CONFIG + PCIe port configuration + PortIndex - Index of the port to be configured as defined by PCI_PORTS + HidePort - Hide the selected port + DeEmphasis - DeEmphasis of the selected PCIe port + PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set + DfxDnTxPreset - PCIe Downstream Tx Preset, valid values (0x00 - 0x09, + 0xFF is Auto, Auto sets 0x07) + DfxRxPreset - PCIe Downstream Rx Preset, valid values (0x00 - 0x06, 0xFF is Auto) + DfxUpTxPreset - PCIe Upstream Tx Preset, valid values (0x00 - 0x09, 0xFF is Auto) + Sris - Enable/Disable SRIS (0x00 - Disable, 0x01 - Enable) + PcieCommonClock - Configure port clocking. (0x00 - Distinct, 0x01 - Common) + MaxPayload - PCIe Max Payload Size on the port + NtbPpd - NTB port Configuration as defined in NTB_PPD + NtbSplitBar - 0: Use one 64, 1: Use two 32-bit split bars + NtbSBar01Prefetch - Configure Split BAR 0/1 as prefetchable + NtbXlinkCtlOverride - NTB Cross-link as defined in NTB_XLINK + NtbBarSizePBar4 - Set Prefetchable BAR 4 size for the primary NTB side in case + Split Bar is Enabled + NtbBarSizePBar5 - Set Prefetchable BAR 5 size for the primary NTB side in case + Split Bar is Enabled + FSP_WA: Till FSP fixes NtbBarSizeOverride, parameters below are MANDATORY!: + These BAR size registers are write once registers and will be programmed with 0 + if not passed as FSP is + hardcoding NtbBarSizeOverride to 0x01 for now. + Split BAR sizes would need to be programmed mandatorily as well in case split bars + are enabled. + NtbBarSizePBar23 - Set Prefetchable BAR 23 size for the primary NTB side + NtbBarSizePBar45 - Used to set bar 4 and 5 sizes in case Split Bar is Disabled + NtbBarSizeSBar23 - Set Prefetchable BAR 23 size for the secondary NTB side + NtbBarSizeSBar45 - Set Prefetchable BAR 45 size for the secondary NTB side in case + Split Bar is disabled +**/ +typedef struct { + UINT32 PortIndex; + UINT8 HidePort; + UINT8 DeEmphasis; + UINT8 PortLinkSpeed; + UINT8 MaxPayload; + UINT8 DfxDnTxPreset; + UINT8 DfxRxPreset; + UINT8 DfxUpTxPreset; + UINT8 Sris; + UINT8 PcieCommonClock; + UINT8 NtbPpd; + UINT8 NtbSplitBar; + UINT8 NtbBarSizePBar23; + UINT8 NtbBarSizePBar4; + UINT8 NtbBarSizePBar5; + UINT8 NtbBarSizePBar45; + UINT8 NtbBarSizeSBar23; + UINT8 NtbBarSizeSBar4; + UINT8 NtbBarSizeSBar5; + UINT8 NtbBarSizeSBar45; + UINT8 NtbSBar01Prefetch; + UINT8 NtbXlinkCtlOverride; +} UPD_PCI_PORT_CONFIG; + +/** + PCIEPORT_CONFIG: + PciePortConfiguration - Pointer to an array of PCIe port configuration structures + as declared above + NumberOfEntries - Number of elements in the PciePortConfiguration Array +**/ +typedef struct { + UPD_PCI_PORT_CONFIG *ConfigurationTable; + + UINT16 NumberOfEntries; +} IIOPCIPORT_CONFIG; + +/** + UPD_IIO_STACK_RESOURCE_CONFIG: + StackIndex - Index of the CPU IIO Stack to be configured as defined by IIO_STACKS + PciResourceIoBase + PciResourceIoLimit + PciResourceMem32Base + PciResourceMem32Limit + PciResourceMem64Base + PciResourceMem64Limit +**/ +typedef struct { + UINT8 StackIndex; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; +} UPD_IIO_STACK_RESOURCE_CONFIG; + +/** + IIORESOURCE_CONFIG: + ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array + NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array +**/ +typedef struct { + UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable; + UINT16 NumberOfEntries; +} IIORESOURCE_CONFIG; + +/** + UPD_PCH_PCIE_PORT: + PortIndex - PCH PCIe Port Index. + Valid Port Numbers are: 0 to 19. + Enable - Enable/Disable PCH PCIe port + PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set +**/ +typedef struct { + UINT8 PortIndex; + UINT8 ForceEnable; + UINT8 PortLinkSpeed; +} UPD_PCH_PCIE_PORT; + +/** + PCHPCIPORT_CONFIG: + PciPortConfig - Pointer to an array of PCH PCI Ports to be configured + RootPortFunctionSwapping - Disable root port swapping based on device + connection status + PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range: 0-20. Auto: 0xFE (sets it to hardware default) + Completely Disable PCIe PLL SSC: 0xFF + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + NumberOfEntries - Number of entries in the PCH PCI Port configuration +**/ +typedef struct { + UPD_PCH_PCIE_PORT *PciPortConfig; + UINT8 RootPortFunctionSwapping; + UINT8 PciePllSsc; + UINT16 NumberOfEntries; +} PCHPCIPORT_CONFIG; + +/** FSP-M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - MRC Debug Print Level + Select the FSP MRC debug message print level. Options are a bitmask, so you can + combine options. BIT0:MIN DEBUG, BIT1:MAX DEBUG, BIT2:TRACE, BIT3:MEM TRAIN, BIT4:TEST, + BIT5:CPGC, BIT6:REG ACCESS +**/ + UINT8 PcdFspMrcDebugPrintErrorLevel; + +/** Offset 0x0041 - KTI Debug Print Level + Select the FSP KTI debug message print level. Options are a bitmask, so you can + combine options. BIT0:ERROR, BIT1:WARNING, BIT2:INFO0, BIT3:INFO1 +**/ + UINT8 PcdFspKtiDebugPrintErrorLevel; + +/** Offset 0x0042 - HSUART Device + Select the PCI High Speed UART Device for Serial Port. + 0:HSUART0, 1:HSUART1, 2:HSUART2 +**/ + UINT8 PcdHsuartDevice; + +/** Offset 0x0043 - Customer Revision + The Customer can set this revision string for their own purpose. +**/ + UINT8 PcdCustomerRevision[32]; + +/** Offset 0x0063 - GpioConfig + GpioConfig Struct. Defaults: GpioTable:NULL, NumberOfEntries:0x00 +**/ + GPIOTABLE_CONFIG GpioConfig; + +/** Offset 0x006B - IioBifurcationConfig + IioBifurcationConfig Table Struct. Defaults: IioBifurcationTable:NULL, + NumberOfEntries:0x00 +**/ + IIOBIFURCATION_CONFIG IioBifurcationConfig; + +/** Offset 0x0073 +**/ + UINT8 UnusedUpdSpace0[16]; + +/** Offset 0x0083 - VTdConfig + VTdConfig Struct. Defaults: All values are set to 0. VTd Disabled. +**/ + VTD_CONFIG VTdConfig; + + UINT8 reserved1[35]; + +/** Offset 0x00A9 - Board ID Number + Select the BoardId based on the target Platform. Default assumes an unknown board. +**/ + UINT8 BoardId; + + UINT8 reserved2[24]; + +/** Offset 0x00C2 **/ + VOID *SetupStructPtr; + + UINT8 reserved3[20]; + +/** Offset 0x00DA - IioPciConfig + IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. +**/ + IIOPCIPORT_CONFIG IioPciConfig; + +/** Offset 0x00E0 - PchPciConfig + PCH Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. +**/ + PCHPCIPORT_CONFIG PchPciConfig; + +/** Offset 0x00E8 - IioResourceConfig + IIO Resource Struct. Defaults: All pointers are NULL. All values are set to zero. +**/ + IIORESOURCE_CONFIG IioResourceConfig; + + UINT8 reserved4[3]; + +/** Offset 0x00F1 - DCI Enable + Enable / Disable DCI + $EN_DIS +**/ + UINT8 PchDciEn; + +/** Offset 0x00F2 - IO Margining Tool (IOMT) Enable + Enable / Disable Io Margining Tool + $EN_DIS +**/ + UINT8 IomtEnable; + +/** Offset 0x00F3 - Hyper Threading (HT) disable + Disable Hyper threading. Disable: 0x01 | Enable: 0x00 | Default - HT enabled + $EN_DIS +**/ + UINT8 HyperThreadingDisable; + +/** Offset 0x00F4 +**/ + UINT8 UnusedUpdSpace1[236]; + +/** Offset 0x01E0 +**/ + UINT8 ReservedMemoryInitUpd[16]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x01F0 - FspmVersion + FSP-M UPD Version Number +**/ + UINT16 FspmUpdVersion; + +/** Offset 0x01F2 +**/ + UINT8 UnusedUpdSpace2[12]; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h new file mode 100644 index 0000000000..b93a1af2a3 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h @@ -0,0 +1,198 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/** FSP-S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - PCIe Controller 0 Bifurcation + Configure PCI Express controller 0 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie0; + +/** Offset 0x0021 - PCIe Controller 1 Bifurcation + Configure PCI Express controller 1 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie1; + +/** Offset 0x0022 - Active Core Count + Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) + 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, + 14:14, 15:15 +**/ + UINT8 PcdActiveCoreCount; + +/** Offset 0x0023 +**/ + UINT32 PcdCpuMicrocodePatchBase; + +/** Offset 0x0027 +**/ + UINT32 PcdCpuMicrocodePatchSize; + +/** Offset 0x002B - PCIe Controller 0 + Enable / Disable PCI Express controller 0 + $EN_DIS +**/ + UINT8 PcdEnablePcie0; + +/** Offset 0x002C - PCIe Controller 1 + Enable / Disable PCI Express controller 1 + $EN_DIS +**/ + UINT8 PcdEnablePcie1; + +/** Offset 0x002D - Embedded Multi-Media Controller (eMMC) + Enable / Disable Embedded Multi-Media controller + $EN_DIS +**/ + UINT8 PcdEnableEmmc; + +/** Offset 0x002E - LAN Controllers + Enable / Disable LAN controllers, refer to FSP Integration Guide for details. + 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only +**/ + UINT8 PcdEnableGbE; + +/** Offset 0x002F +**/ + UINT32 PcdFiaMuxConfigRequestPtr; + +/** Offset 0x0033 +**/ + UINT8 UnusedUpdSpace0[4]; + +/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort0DeEmphasis; + +/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort1DeEmphasis; + +/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort2DeEmphasis; + +/** Offset 0x003A - PCIe Root Port 3 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort3DeEmphasis; + +/** Offset 0x003B - PCIe Root Port 4 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort4DeEmphasis; + +/** Offset 0x003C - PCIe Root Port 5 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort5DeEmphasis; + +/** Offset 0x003D - PCIe Root Port 6 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort6DeEmphasis; + +/** Offset 0x003E - PCIe Root Port 7 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort7DeEmphasis; + +/** Offset 0x003F +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0040 +**/ + UINT32 PcdEMMCDLLConfigPtr; + +/** Offset 0x0044 - Disable Monitor MWAIT + Enable / Disable the Monitor-MWAIT Instruction + $EN_DIS +**/ + UINT8 PcdDisableMonitorFSM; + +/** Offset 0x0045 +**/ + UINT8 UnusedUpdSpace2[155]; + +/** Offset 0x00E0 +**/ + UINT8 ReservedSiliconInitUpd[16]; +} FSPS_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_CONFIG FspsConfig; + +/** Offset 0x00F0 +**/ + UINT8 UnusedUpdSpace3[14]; + +/** Offset 0x00FE +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h new file mode 100644 index 0000000000..23b4a04283 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h @@ -0,0 +1,108 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include + +#pragma pack(1) + +/** FSP-T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0030 +**/ + UINT8 Reserved1[16]; +} FSPT_CORE_UPD; + +/** FSP-T Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Disable Port80 output in FSP-T + Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 + Output, refer to FSP Integration Guide for details + 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output +**/ + UINT8 PcdFsptPort80RouteDisable; + +/** Offset 0x0041 +**/ + UINT8 ReservedTempRamInitUpd[31]; +} FSPT_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ + FSPT_CONFIG FsptConfig; + +/** Offset 0x0060 +**/ + UINT8 UnusedUpdSpace0[30]; + +/** Offset 0x007E +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h new file mode 100644 index 0000000000..91832441b6 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h @@ -0,0 +1,244 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _HOB_IIOUDS_H_ +#define _HOB_IIOUDS_H_ + +#include + +#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \ + 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ + 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ +} + +#define NUMBER_PORTS_PER_SOCKET 21 +#define MAX_SOCKET CONFIG_MAX_SOCKET +#define MAX_IIO MAX_SOCKET +#define MAX_IIO_STACK 6 +#define MAX_KTI_PORTS 3 +#define MAX_IMC 2 +#define MAX_CH 6 +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) +#define SAD_RULES 24 +#define TDP_MAX_LEVEL 5 + +#pragma pack(1) + +//--------------------------------------------------------------------------------------// +// Structure definitions for Universal Data Store (UDS) +//--------------------------------------------------------------------------------------// +typedef struct uint64_t_struct { + uint32_t lo; + uint32_t hi; +} UINT64_STRUCT; + +typedef struct { + uint8_t Device; + uint8_t Function; +} IIO_PORT_INFO; + +typedef struct { + // TRUE, if the link is valid (i.e reached normal operation) + uint8_t Valid; + uint8_t PeerSocId; // Socket ID + uint8_t PeerSocType; // Socket Type (0 - CPU; 1 - IIO) + uint8_t PeerPort; // Port of the peer socket +} QPI_PEER_DATA; + +typedef struct { + uint8_t Valid; + uint8_t SocketFirstBus; + uint8_t SocketLastBus; + uint8_t segmentSocket; + uint8_t PcieSegment; + UINT64_STRUCT SegMmcfgBase; + uint8_t stackPresentBitmap; + uint8_t StackBus[MAX_IIO_STACK]; + uint8_t M2PciePresentBitmap; + uint8_t TotM3Kti; + uint8_t TotCha; + uint32_t ChaList; + uint32_t SocId; + QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + uint8_t Valid; + uint8_t SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef struct _STACK_RES { + uint8_t Personality; + uint8_t BusBase; + uint8_t BusLimit; + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; + uint32_t IoApicBase; + uint32_t IoApicLimit; + uint32_t PciResourceMem32Base; + uint32_t PciResourceMem32Limit; + uint64_t PciResourceMem64Base; + uint64_t PciResourceMem64Limit; + uint32_t VtdBarAddress; +} STACK_RES; + +typedef struct { + uint8_t Valid; + int8_t SocketID; // Socket ID of the IIO (0..3) + uint8_t BusBase; + uint8_t BusLimit; + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; + uint32_t IoApicBase; + uint32_t IoApicLimit; + uint32_t PciResourceMem32Base; + uint32_t PciResourceMem32Limit; + uint64_t PciResourceMem64Base; + uint64_t PciResourceMem64Limit; + STACK_RES StackRes[MAX_IIO_STACK]; + uint32_t RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + uint8_t DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + uint16_t PlatGlobalIoBase; // Global IO Base + uint16_t PlatGlobalIoLimit; // Global IO Limit + uint32_t PlatGlobalMmiolBase; // Global Mmiol base + uint32_t PlatGlobalMmiolLimit; // Global Mmiol limit + uint64_t PlatGlobalMmiohBase; // Global Mmioh Base [43:0] + uint64_t PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + uint32_t MemTsegSize; + uint32_t MemIedSize; + uint64_t PciExpressBase; + uint32_t PciExpressSize; + uint32_t MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + uint8_t numofIIO; + uint8_t MaxBusNumber; + // This data array is valid only for SBSP, not for non-SBSP CPUs. for CpuSv + uint32_t packageBspApicID[MAX_SOCKET]; + uint8_t EVMode; + uint8_t Pci64BitResourceAllocation; + uint8_t SkuPersonality[MAX_SOCKET]; + uint8_t VMDStackEnable[MAX_IIO][MAX_IIO_STACK]; + uint16_t IoGranularity; + uint32_t MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + uint8_t RemoteRequestThreshold; + // bitmap of Softsku sockets with CPUs present detected + uint64_t softskuSocketPresentBitMap; + BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w +} PLATFORM_DATA; + +typedef struct { + uint32_t FILLER_BUG; + // Current programmed CSI (or UPI) Link speed (Slow/Full speed mode) + uint8_t CurrentCsiLinkSpeed; + // Current requested CSI (or UPI) Link frequency (in GT) + uint8_t CurrentCsiLinkFrequency; + // output kti link enabled status for PM + uint32_t OutKtiPerLinkL1En[MAX_SOCKET]; + uint8_t IsocEnable; + // Size of the memory range requested by ME FW, in MB + uint32_t meRequestedSize; + uint8_t DmiVc1; + uint8_t DmiVcm; + uint32_t CpuPCPSInfo; + uint8_t MinimumCpuStepping; + uint8_t LtsxEnable; + uint8_t MctpEn; + uint8_t cpuType; + uint8_t cpuSubType; + uint8_t SystemRasType; + // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC + uint8_t numCpus; + // Fused Core Mask in the package + uint32_t FusedCores[MAX_SOCKET]; + // Current activated core Mask in the package + uint32_t ActiveCores[MAX_SOCKET]; + // Package Max Non-turbo Ratio (per socket). + uint8_t MaxCoreToBusRatio[MAX_SOCKET]; + // Package Maximum Efficiency Ratio (per socket). + uint8_t MinCoreToBusRatio[MAX_SOCKET]; + uint8_t CurrentCoreToBusRatio; // Current system Core to Bus Ratio + // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] + uint32_t IntelSpeedSelectCapable; + uint32_t IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO + // get B2P CONFIG_TDP_GET_TDP_INFO + uint32_t IssConfigTdpTdpInfo[TDP_MAX_LEVEL]; + // get B2P CONFIG_TDP_GET_POWER_INFO + uint32_t IssConfigTdpPowerInfo[TDP_MAX_LEVEL]; + // get B2P CONFIG_TDP_GET_CORE_COUNT + uint8_t IssConfigTdpCoreCount[TDP_MAX_LEVEL]; + // bitmap of sockets with CPUs present detected by QPI RC + uint32_t socketPresentBitMap; + // bitmap of NID w/ fpga present detected by QPI RC + uint32_t FpgaPresentBitMap; + uint16_t tolmLimit; + uint32_t tohmLimit; + uint32_t mmCfgBase; + uint32_t RcVersion; + uint8_t DdrXoverMode; // DDR 2.2 Mode + uint8_t bootMode; + uint8_t OutClusterOnDieEn; // Whether RC enabled COD support + uint8_t OutSncEn; + uint8_t OutNumOfCluster; + uint8_t imcEnabled[MAX_SOCKET][MAX_IMC]; + uint8_t numChPerMC; + uint8_t maxCh; + uint8_t maxIMC; + uint16_t LlcSizeReg; + uint8_t chEnabled[MAX_SOCKET][MAX_CH]; + uint8_t mcId[MAX_SOCKET][MAX_CH]; + uint8_t memNode[MC_MAX_NODE]; + uint8_t IoDcMode; + uint8_t CpuAccSupport; + uint8_t SmbusErrorRecovery; + uint8_t AepDimmPresent; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + uint32_t OemValue; +} IIO_UDS; +#pragma pack() + +void soc_display_iio_universal_data_hob(void); + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h new file mode 100644 index 0000000000..954e43ce1a --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h @@ -0,0 +1,119 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _MEMORY_MAP_GUID_H_ +#define _MEMORY_MAP_GUID_H_ + +#define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \ + 0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \ + 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ + } + +#define MEMTYPE_1LM_MASK (1 << 0) +#define MEMTYPE_2LM_MASK (1 << 1) +#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) + +#define MAX_IMC_PER_SOCKET 2 +#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 +#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \ + MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ + ) + +/* ACPI SRAT Memory Flags */ +#define SRAT_ACPI_MEMORY_ENABLED (1 << 0) +#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) +#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) + +#define MEM_TYPE_RESERVED (1 << 8) +#define MEM_ADDR_64MB_SHIFT_BITS 26 + +// +// System Memory Map HOB information +// + +#pragma pack(1) + +struct SystemMemoryMapElement { + UINT8 NodeId; // Node ID of the HA Owning the memory + UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA + UINT8 ImcInterBitmap; // IMC interleave bitmap for this DRAM rule - ONLY IN NUMA + UINT32 BaseAddress; // Base Address of the element in 64MB chunks + UINT32 ElementSize; // Size of this memory element in 64MB chunks + // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM + // Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region + UINT16 Type; +}; + +struct SystemMemoryMapHob { + UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. + UINT32 asilLoMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 asilHiMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 asilLoMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 asilHiMemSize; // Mem size in 64MB units for above 4GB mem. + + UINT32 memSize; // Total physical memory size + UINT16 memFreq; // Mem Frequency + UINT8 memMode; // 0 - Independent, 1 - Lockstep + UINT8 volMemMode; // 0 - 1LM, 1 - 2LM + UINT8 DimmType; + UINT16 DramType; + UINT8 DdrVoltage; + // If at least one Aep Dimm Present (used by Nfit), then this should get set + UINT8 AepDimmPresent; + UINT8 SADNum; + UINT8 XMPProfilesSup; + UINT8 cpuType; + UINT8 cpuStepping; + UINT8 SystemRasType; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 ExRasModesEnabled; // Extended RAS modes that are enabled + //RAS modes that are supported by current memory population. + UINT8 RasModesSupported; + // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration + UINT8 sncEnabled; + UINT8 NumOfCluster; + UINT8 NumChPerMC; + UINT8 numberEntries; // Number of Memory Map Elements + UINT8 maxIMC; + UINT8 maxCh; + struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES]; + UINT8 reserved1[982]; + UINT8 reserved2[4901*MAX_SOCKET]; + UINT8 reserved3[707]; +}; + +#pragma pack() + +void soc_display_memmap_hob(void); + +#endif From 2a6140ea85fc23e9d024e557714480bfa9afed21 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Tue, 14 Jan 2020 01:16:37 +0100 Subject: [PATCH 0195/1463] drivers/i2c/at24rf08c: Correctly format short multi-line comments Change-Id: I84e09706aceae69671ce429d77e7874128468307 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38391 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering Reviewed-by: HAOUAS Elyes --- src/drivers/i2c/at24rf08c/at24rf08c.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 102e0e8c7c..daf04a9d1a 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -25,7 +25,7 @@ static void at24rf08c_init(struct device *dev) return; /* Ensure that EEPROM/RFID chip is not accessible through RFID. - Need to do it only on 5c. */ + Need to do it only on 5c. */ if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c) return; @@ -34,8 +34,7 @@ static void at24rf08c_init(struct device *dev) for (i = 0; i < 8; i++) { /* After a register write AT24RF08C sometimes stops responding. - Retry several times in case of failure. - */ + Retry several times in case of failure. */ for (j = 0; j < 100; j++) if (smbus_write_byte(dev, i, 0x0f) >= 0) break; From d778b3bc9098a03cf955918e3e3b33a4e4c5e99f Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Tue, 14 Jan 2020 01:21:06 +0100 Subject: [PATCH 0196/1463] drivers/i2c/at24rf08c: Format according to coding style 1. Move opening bracket to line above 2. Remove space after `printk` statements Change-Id: Ia12a4ed6ab2fb2c9848a2688b41fcfa70ab001b0 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38392 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/drivers/i2c/at24rf08c/at24rf08c.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index daf04a9d1a..11a6fd2b3d 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -29,10 +29,9 @@ static void at24rf08c_init(struct device *dev) if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c) return; - printk (BIOS_DEBUG, "Locking EEPROM RFID\n"); + printk(BIOS_DEBUG, "Locking EEPROM RFID\n"); - for (i = 0; i < 8; i++) - { + for (i = 0; i < 8; i++) { /* After a register write AT24RF08C sometimes stops responding. Retry several times in case of failure. */ for (j = 0; j < 100; j++) @@ -40,7 +39,7 @@ static void at24rf08c_init(struct device *dev) break; } - printk (BIOS_DEBUG, "init EEPROM done\n"); + printk(BIOS_DEBUG, "init EEPROM done\n"); } static struct device_operations at24rf08c_operations = { From c8b0f31ca1b6cae993736d47d919080b6c186c6f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 28 Feb 2020 10:19:41 +0100 Subject: [PATCH 0197/1463] acpi: Bump FADT to revision 6 Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Change-Id: I10c1e2517df41159ab9b04f763d3805ecba50ffa Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39157 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/arch/x86/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6dab3733cc..b9e896f7de 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1563,7 +1563,7 @@ int get_acpi_table_revision(enum acpi_tables table) { switch (table) { case FADT: - return ACPI_FADT_REV_ACPI_3_0; + return ACPI_FADT_REV_ACPI_6_0; case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ return 2; case MCFG: diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 68475c157e..67f4be2d53 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -529,8 +529,8 @@ typedef struct acpi_fadt { u32 flags; acpi_addr_t reset_reg; u8 reset_value; - u16 ARM_boot_arch; - u8 FADT_MinorVersion; + u16 ARM_boot_arch; /* Revision 6 only, Revision 5: Must be zero */ + u8 FADT_MinorVersion; /* Revision 6 only, Revision 5: Must be zero */ u32 x_firmware_ctl_l; u32 x_firmware_ctl_h; u32 x_dsdt_l; @@ -543,6 +543,11 @@ typedef struct acpi_fadt { acpi_addr_t x_pm_tmr_blk; acpi_addr_t x_gpe0_blk; acpi_addr_t x_gpe1_blk; + /* Revision 5 */ + acpi_addr_t sleep_control_reg; + acpi_addr_t sleep_status_reg; + /* Revision 6 */ + u64 hypervisor_vendor_identity; } __packed acpi_fadt_t; /* FADT TABLE Revision values */ From 1ee3dbc63b3514b93927b40add395a31b4f1915e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 28 Feb 2020 13:11:13 +0100 Subject: [PATCH 0198/1463] nb/intel/sandybridge: Fix VBOOT The VBOOT code can be compiled but it asserts with: ASSERTION ERROR: file 'src/security/vboot/common.c', line 40 Start VBOOT in bootblock to fix the assertion. Tested on Lenovo X220: The assertion is gone, the platform boots again. Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/parrot/Kconfig | 1 + src/mainboard/google/stout/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/Kconfig | 1 + src/northbridge/intel/sandybridge/Kconfig | 26 ++++++++++++++++++++++- 6 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 92fc236f9b..33a840fd83 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ME_BIN select GFX_GMA_INTERNAL_IS_LVDS select MAINBOARD_HAS_LIBGFXINIT + select SANDYBRIDGE_VBOOT_IN_ROMSTAGE config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 0169beaf3f..c5b680c89b 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # This board also feature sandy-bridge CPU's so must have LVDS select GFX_GMA_INTERNAL_IS_LVDS select MAINBOARD_HAS_LIBGFXINIT + select SANDYBRIDGE_VBOOT_IN_ROMSTAGE config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index a77964b8f8..f945cc0316 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select GFX_GMA_INTERNAL_IS_LVDS select HAVE_IFD_BIN select HAVE_ME_BIN + select SANDYBRIDGE_VBOOT_IN_ROMSTAGE config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index f87ba8f739..56304c9349 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_SMSC_LPC47N207 select DRIVERS_GENERIC_IOAPIC select INTEL_INT15 + select SANDYBRIDGE_VBOOT_IN_ROMSTAGE config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 5deb0f0722..67cc67ebd8 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # not on board, should be made selectable. select SUPERIO_SMSC_LPC47N207 select INTEL_INT15 + select SANDYBRIDGE_VBOOT_IN_ROMSTAGE config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7a27d098c5..06fdc4a0a9 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -23,8 +23,32 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE if NORTHBRIDGE_INTEL_SANDYBRIDGE +config SANDYBRIDGE_VBOOT_IN_ROMSTAGE + bool + default n + help + Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE. + +config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK + depends on VBOOT + depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Sandy Bridge can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Sandy Bridge however uses a mrc.bin to initialize memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. + config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK config USE_NATIVE_RAMINIT bool "Use native raminit" From cb06cfeca6d9bdfc9b7ae311180d3903e13b7ba7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 28 Feb 2020 22:35:56 +0100 Subject: [PATCH 0199/1463] soc/intel/apollolake: Fix flashconsole, again This time, it failed to build if measured boot was not enabled. Fix this problem, and make sure flashconsole will not break like that again. Change-Id: I5f5ffd14a3225804524cb0c1518e3d99737e0a93 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39164 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- configs/config.google_octopus_spi_flash_console | 4 ++++ src/soc/intel/apollolake/Makefile.inc | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) create mode 100644 configs/config.google_octopus_spi_flash_console diff --git a/configs/config.google_octopus_spi_flash_console b/configs/config.google_octopus_spi_flash_console new file mode 100644 index 0000000000..df8889b019 --- /dev/null +++ b/configs/config.google_octopus_spi_flash_console @@ -0,0 +1,4 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_OCTOPUS=y +CONFIG_CONSOLE_SPI_FLASH=y +# CONFIG_VBOOT_MEASURED_BOOT is not set diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b420dea64d..a20a554be1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -78,7 +78,7 @@ postcar-y += i2c.c postcar-y += heci.c postcar-y += reset.c postcar-y += uart.c -postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c +postcar-y += gspi.c verstage-y += car.c verstage-y += i2c.c From 59e7a43f9a3bfad60d2ae0078b65deca8d468381 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 02:06:43 +0100 Subject: [PATCH 0200/1463] mb/**/dsdt.asl: Remove "Some generic macros" comment, again It provides no useful information, so it might as well vanish. This follows commit 0142d441c63a9bb1a7955ea0ba764a2ddbc38d48. Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/dedede/dsdt.asl | 1 - src/mainboard/google/volteer/dsdt.asl | 1 - src/mainboard/intel/jasperlake_rvp/dsdt.asl | 1 - src/mainboard/intel/tglrvp/dsdt.asl | 1 - 4 files changed, 4 deletions(-) diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 3d17017101..4134b036da 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -19,7 +19,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 489d2f0222..e4bbe90d70 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -19,7 +19,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 559e1e36cf..8788a1f71d 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index f21ba5d88a..a17f597e6b 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ From cfe1016883b711e0a76d3dcbc9151813d648619b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 02:12:58 +0100 Subject: [PATCH 0201/1463] mb/**/dsdt.asl: Remove outdated sleepstates.asl comment Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments. This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1. Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/dedede/dsdt.asl | 1 - src/mainboard/google/volteer/dsdt.asl | 1 - src/mainboard/intel/jasperlake_rvp/dsdt.asl | 1 - src/mainboard/intel/tglrvp/dsdt.asl | 1 - 4 files changed, 4 deletions(-) diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 4134b036da..45a1486b55 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -38,7 +38,6 @@ DefinitionBlock( /* Chrome OS specific */ #include - /* Chipset specific sleep states */ #include /* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index e4bbe90d70..f62780bccc 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,6 +47,5 @@ DefinitionBlock( #include } - // Chipset specific sleep states #include } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 8788a1f71d..4b9a696214 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -58,7 +58,6 @@ DefinitionBlock( } #endif - /* Chipset specific sleep states */ #include /* Mainboard specific */ diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index a17f597e6b..8236ccb110 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -58,7 +58,6 @@ DefinitionBlock( } #endif - /* Chipset specific sleep states */ #include /* Mainboard specific */ From 56a0c2579dd5a779ef01b2dbd736520c0271381a Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Wed, 26 Feb 2020 10:41:45 +0900 Subject: [PATCH 0202/1463] mb/google/kohaku: Add LPDDR 16G 2133 support BUG=b:149775711 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot Signed-off-by: Seunghwan Kim Change-Id: I856d7b361e70b657966cd4036c79f2fedfabb766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39126 Reviewed-by: Frans Hendriks Reviewed-by: Tim Wawrzynczak Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/kohaku/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index 6bd29737aa..3fb352dbf5 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -13,6 +13,7 @@ ## SPD_SOURCES = LP_8G_2133 # 0b000 +SPD_SOURCES += LP_16G_2133 # 0b001 romstage-y += memory.c From e5e24107f91a959e24546d0cdad84eecee329f8e Mon Sep 17 00:00:00 2001 From: Alex Rebert Date: Sat, 29 Feb 2020 23:03:54 -0500 Subject: [PATCH 0203/1463] libpayload: cbfs: fix infinite loop in cbfs_get_{handle,attr} cbfs_get_handle() and cbfs_get_attr() are both looping over elements to find a particular one. Each element header contains the element's length, which is used to compute the next element's offset. Invalid or corrupted CBFS files could lead to infinite loops where the offset would remain constant across iterations, due to 0-length elements or integer overflows in the computation of the next offset. This patch makes both functions more robust by adding a check that ensure offsets are strictly monotonic. Instead of infinite looping, the functions are now printing an ERROR and returning a NULL value. Change-Id: I440e82fa969b8c2aacc5800e7e26450c3b97c74a Signed-off-by: Alex Rebert Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- payloads/libpayload/libcbfs/cbfs_core.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index e94e1e76ba..30a41f8a72 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -212,9 +212,15 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) } // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); - if (offset % CBFS_ALIGNMENT) - offset += CBFS_ALIGNMENT - (offset % CBFS_ALIGNMENT); + uint32_t next_offset = offset + ntohl(file.len) + ntohl(file.offset); + if (next_offset % CBFS_ALIGNMENT) + next_offset += CBFS_ALIGNMENT - (next_offset % CBFS_ALIGNMENT); + // Check that offset is strictly monotonic to prevent infinite loop + if (next_offset <= offset) { + ERROR("ERROR: corrupted CBFS file header at 0x%x.\n", offset); + break; + } + offset = next_offset; } media->close(media); LOG("WARNING: '%s' not found.\n", name); @@ -309,7 +315,14 @@ void *cbfs_get_attr(struct cbfs_handle *handle, uint32_t tag) return NULL; } if (ntohl(attr.tag) != tag) { - offset += ntohl(attr.len); + uint32_t next_offset = offset + ntohl(attr.len); + // Check that offset is strictly monotonic to prevent infinite loop + if (next_offset <= offset) { + ERROR("ERROR: corrupted CBFS attribute at 0x%x.\n", offset); + m->close(m); + return NULL; + } + offset = next_offset; continue; } ret = m->map(m, offset, ntohl(attr.len)); From 70282aece0dd33f54ee797486f9d7d03aa8c2346 Mon Sep 17 00:00:00 2001 From: Alex Rebert Date: Sat, 29 Feb 2020 17:36:08 -0500 Subject: [PATCH 0204/1463] lz4: Fix out-of-bounds reads Fix two out-of-bounds reads in lz4 decompression: 1) LZ4_decompress_generic could read one byte past the input buffer when decoding variable length literals due to a missing bounds check. This issue was resolved in libpayload, commonlib and cbfstool 2) ulz4fn could read up to 4 bytes past the input buffer when reading a lz4_block_header due to a missing bounds check. This issue was resolved in libpayload and commonlib. Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc Signed-off-by: Alex Rebert Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39174 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- payloads/libpayload/liblz4/lz4.c.inc | 1 + payloads/libpayload/liblz4/lz4_wrapper.c | 3 +++ src/commonlib/bsd/lz4.c.inc | 1 + src/commonlib/bsd/lz4_wrapper.c | 3 +++ util/cbfstool/lz4/lib/lz4.c | 1 + 5 files changed, 9 insertions(+) diff --git a/payloads/libpayload/liblz4/lz4.c.inc b/payloads/libpayload/liblz4/lz4.c.inc index baa911021d..68fac47c89 100644 --- a/payloads/libpayload/liblz4/lz4.c.inc +++ b/payloads/libpayload/liblz4/lz4.c.inc @@ -150,6 +150,7 @@ FORCE_INLINE int LZ4_decompress_generic( if ((length=(token>>ML_BITS)) == RUN_MASK) { unsigned s; + if ((endOnInput) && unlikely(ip>=iend-RUN_MASK)) goto _output_error; /* overflow detection */ do { s = *ip++; diff --git a/payloads/libpayload/liblz4/lz4_wrapper.c b/payloads/libpayload/liblz4/lz4_wrapper.c index d125ce336f..3d17fe6742 100644 --- a/payloads/libpayload/liblz4/lz4_wrapper.c +++ b/payloads/libpayload/liblz4/lz4_wrapper.c @@ -141,6 +141,9 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) } while (1) { + if ((size_t)(in - src) + sizeof(struct lz4_block_header) > srcn) + break; /* input overrun */ + struct lz4_block_header b = { .raw = le32toh(*(uint32_t *)in) }; in += sizeof(struct lz4_block_header); diff --git a/src/commonlib/bsd/lz4.c.inc b/src/commonlib/bsd/lz4.c.inc index b3be4e5b44..8c75e2f279 100644 --- a/src/commonlib/bsd/lz4.c.inc +++ b/src/commonlib/bsd/lz4.c.inc @@ -150,6 +150,7 @@ FORCE_INLINE int LZ4_decompress_generic( if ((length=(token>>ML_BITS)) == RUN_MASK) { unsigned s; + if ((endOnInput) && unlikely(ip>=iend-RUN_MASK)) goto _output_error; /* overflow detection */ do { s = *ip++; diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index 2367afceaf..3822e8c60f 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -129,6 +129,9 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) } while (1) { + if ((size_t)(in - src) + sizeof(struct lz4_block_header) > srcn) + break; /* input overrun */ + struct lz4_block_header b = { { .raw = le32toh(*(const uint32_t *)in) } }; diff --git a/util/cbfstool/lz4/lib/lz4.c b/util/cbfstool/lz4/lib/lz4.c index 9c9a9a0d00..e393690203 100644 --- a/util/cbfstool/lz4/lib/lz4.c +++ b/util/cbfstool/lz4/lib/lz4.c @@ -1206,6 +1206,7 @@ FORCE_INLINE int LZ4_decompress_generic( if ((length=(token>>ML_BITS)) == RUN_MASK) { unsigned s; + if ((endOnInput) && unlikely(ip>=iend-RUN_MASK)) goto _output_error; /* overflow detection */ do { s = *ip++; From b61a4da5ec440aa8dbf7c5a8671800b564938cf2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 29 Feb 2020 10:37:37 +0100 Subject: [PATCH 0205/1463] lint/check_lint_tests: Fix obsolete paths Change-Id: Ieac6e5ba0d425f873c3d4125d828224313017b69 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/lint/check_lint_tests | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests index 6f6942d549..6c050ee13b 100755 --- a/util/lint/check_lint_tests +++ b/util/lint/check_lint_tests @@ -6,7 +6,7 @@ UNDERSCORE='_' #lint-stable-000-license-headers TESTFILE000a=src/arch/x86/thread.c -TESTFILE000b=src/arch/ppc64/misc.c +TESTFILE000b=src/arch/riscv/misc.c sed -i.bak 's/^[[:space:]]\*[[:space:]].*//' ${TESTFILE000a} sed -i.bak 's/^[[:space:]]\*[[:space:]]but WITHOUT ANY WARRANTY;//' ${TESTFILE000b} @@ -20,12 +20,10 @@ sed -i.bak 's/^done:/ done:/' ${TESTFILE004} #lint-stable-005-board-status TESTFILE005a=src/mainboard/google/storm/board_info.txt -TESTFILE005b=src/mainboard/aaeon/pfm-540i_revb/board_info.txt -rm -f ${TESTFILE005a} -sed -i.bak 's/^Category:.*/Category: lint/' ${TESTFILE005b} +sed -i.bak 's/^Category:.*/Category: lint/' ${TESTFILE005a} #lint-stable-006-board-name -TESTFILE006=src/mainboard/amd/bettong/Kconfig.name +TESTFILE006=src/mainboard/ibase/mb899/Kconfig.name rm -f ${TESTFILE006} #lint-stable-008-kconfig From 10615996cce14e61278e09b7d0531e0c79e2a100 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 29 Feb 2020 10:48:19 +0100 Subject: [PATCH 0206/1463] lint/lint-extended-007-checkpatch: Fix obsolete paths Change-Id: I7a6ca083e79d285b8c596631f21ccdfe2777e20e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39171 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/lint/lint-extended-007-checkpatch | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/util/lint/lint-extended-007-checkpatch b/util/lint/lint-extended-007-checkpatch index 4610b5ea99..c221d4a9f4 100755 --- a/util/lint/lint-extended-007-checkpatch +++ b/util/lint/lint-extended-007-checkpatch @@ -21,9 +21,7 @@ src/cpu/armltd src/cpu/qemu-power8 src/cpu/qemu-x86 \ src/drivers/dec src/drivers/gic src/drivers/ti \ src/ec/purism \ src/include/boot src/include/superio src/include/sys \ -src/mainboard/adlink src/mainboard/linutop \ -src/mainboard/purism src/mainboard/ti \ -src/soc/rdc \ +src/mainboard/adlink src/mainboard/purism src/mainboard/ti \ src/superio/acpi src/superio/common \ " From c105d9ab3faa7aa8ee6ff86f8c4608bad96093e9 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Thu, 10 Jan 2019 15:03:35 +0100 Subject: [PATCH 0207/1463] x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/30806 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/arch/x86/acpi_s3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 52f8a201f7..ecfe34c0cf 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -33,10 +33,10 @@ static void acpi_handoff_wakeup(void) { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } From 4062b6a3b18f8e562b813b94509ecebc4415bfa2 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 3 Jan 2020 19:01:19 -0700 Subject: [PATCH 0208/1463] soc/amd/picasso: Add PCI ID for Dali xHCI soc//picasso is intended to be forward-compatible with the Dali APU, a Family 17h Models 20h-2Fh product. Add the one new device ID it has. See PPR document #55772 (still NDA only) for more information. Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/38169 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Eric Peers Reviewed-by: Martin Roth --- src/include/device/pci_ids.h | 1 + src/soc/amd/picasso/usb.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 47b182577d..e2dc28e17a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -459,6 +459,7 @@ #define PCI_DEVICD_ID_AMD_PCO_ACP 0x15e2 #define PCI_DEVICE_ID_AMD_PCO_XHCI0 0x15e0 #define PCI_DEVICE_ID_AMD_PCO_XHCI1 0x15e1 +#define PCI_DEVICE_ID_AMD_DALI_XHCI 0x15e5 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 80e960cd86..faea3c3af8 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -48,6 +48,7 @@ static struct device_operations usb_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_PCO_XHCI0, PCI_DEVICE_ID_AMD_PCO_XHCI1, + PCI_DEVICE_ID_AMD_DALI_XHCI, 0 }; From c4a8c48b2f70d56c7c318f4ce24a467a1d708ef5 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 21 Jan 2020 17:17:59 -0700 Subject: [PATCH 0209/1463] util/amdfwtool: Clarify APOB NV requirements Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/amdfwtool/amdfwtool.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 379caaab5a..5bcc0a7d77 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -808,6 +808,17 @@ static int have_bios_tables(amd_bios_entry *table) return 0; } +static int find_bios_entry(amd_bios_type type) +{ + int i; + + for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { + if (amd_bios_table[i].type == type) + return i; + } + return -1; +} + static void integrate_bios_firmwares(context *ctx, bios_directory_table *biosdir, bios_directory_table *biosdir2, @@ -817,6 +828,7 @@ static void integrate_bios_firmwares(context *ctx, ssize_t bytes; unsigned int i, count; int level; + int apob_idx; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -843,9 +855,6 @@ static void integrate_bios_firmwares(context *ctx, fw_table[i].type != AMD_BIOS_L2_PTR && fw_table[i].type != AMD_BIOS_BIN)) continue; - /* APOB_NV needs a size, else no S3 and skip item */ - if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) - continue; /* BIOS Directory items may have additional requirements */ @@ -857,6 +866,19 @@ static void integrate_bios_firmwares(context *ctx, exit(1); } } + /* APOB_NV needs a size, else no choice but to skip the item */ + if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) { + /* Attempt to determine whether this is an error */ + apob_idx = find_bios_entry(AMD_BIOS_APOB); + if (apob_idx < 0 || !fw_table[apob_idx].dest) { + /* APOV NV not expected to be used */ + continue; + } else { + printf("Error: APOB NV must have a size\n"); + free(ctx->rom); + exit(1); + } + } /* APOB_DATA needs destination */ if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { From dbc90df35d814ad0d039793139c3e7e683ee0310 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 22 Nov 2019 00:10:20 +0100 Subject: [PATCH 0210/1463] soc/intel/denverton: Move PCI IDs to pci_ids.h This patch moves the PCI ID definitions to pci_ids.h file and replaces every occurrence with the new names. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 337018 Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/37120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Subrata Banik --- src/include/device/pci_ids.h | 34 +++++++++++++++ src/soc/intel/denverton_ns/csme_ie_kt.c | 4 +- .../intel/denverton_ns/include/soc/pci_devs.h | 42 ------------------- src/soc/intel/denverton_ns/lpc.c | 2 +- src/soc/intel/denverton_ns/npk.c | 2 +- src/soc/intel/denverton_ns/pmc.c | 2 +- src/soc/intel/denverton_ns/sata.c | 4 +- src/soc/intel/denverton_ns/systemagent.c | 4 +- src/soc/intel/denverton_ns/uart.c | 2 +- src/soc/intel/denverton_ns/xhci.c | 2 +- 10 files changed, 45 insertions(+), 53 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e2dc28e17a..ccbfe4068d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2680,6 +2680,40 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +/* Intel Denverton (Atom C3000 family) */ +#define PCI_DEVICE_ID_INTEL_DENVERTON_SA 0x1980 +#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA 0x1995 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0 0x19a4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1 0x19a5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2 0x19a6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3 0x19a7 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4 0x19a8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5 0x19a9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6 0x19aa +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7 0x19ab +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS 0x19ac +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1 0x19b2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2 0x19c2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1 0x19d1 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2 0x19d2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1 0x19d3 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2 0x19d4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT 0x19d5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3 0x19d6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART 0x19d8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1 0x19e5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2 0x19e6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT 0x19e8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3 0x19e9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC 0x19db +#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC 0x19dc +#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB 0x19dd +#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC 0x19de +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY 0x19df +#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 143e7b60a8..be8d991618 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -76,8 +76,8 @@ static struct device_operations csme_ie_kt_ops = { }; static const unsigned short pci_device_ids[] = { - ME_MEKT_DEVID, /* DVN CSME KT */ - IE_MEKT_DEVID, /* DVN IE KT */ + PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT, + PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT, 0 }; diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index faa4d927f5..a300fd4cd3 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -158,46 +158,4 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define SA_DEVID 0x1980 -#define SA_DEVID_DNVAD 0x1995 -#define SOC_DEVID SA_DEVID -#define RAS_DEVID 0x19a1 -#define RCEC_DEVID 0x19a2 -#define VRP2_DEVID 0x19a3 -#define PCIE_PORT1_DEVID 0x19a4 -#define PCIE_PORT2_DEVID 0x19a5 -#define PCIE_PORT3_DEVID 0x19a6 -#define PCIE_PORT4_DEVID 0x19a7 -#define PCIE_PORT5_DEVID 0x19a8 -#define PCIE_PORT6_DEVID 0x19a9 -#define PCIE_PORT7_DEVID 0x19aa -#define PCIE_PORT8_DEVID 0x19ab -#define SMBUS2_DEVID 0x19ac -#define AHCI_DEVID 0x19b2 -#define AHCI2_DEVID 0x19c2 -#define XHCI_DEVID 0x19d0 -#define VRP0_DEVID 0x19d1 -#define VRP1_DEVID 0x19d2 -#define ME_HECI1_DEVID 0x19d3 -#define ME_HECI2_DEVID 0x19d4 -#define ME_IEDR_DEVID 0x19ea -#define ME_MEKT_DEVID 0x19d5 -#define ME_HECI3_DEVID 0x19d6 -#define HSUART_DEVID 0x19d8 -#define HSUART1_DEVID HSUART_DEVID -#define HSUART2_DEVID HSUART_DEVID -#define HSUART3_DEVID HSUART_DEVID -#define IE_HECI1_DEVID 0x19e5 -#define IE_HECI2_DEVID 0x19e6 -#define IE_IEDR_DEVID 0x19e7 -#define IE_MEKT_DEVID 0x19e8 -#define IE_HECI3_DEVID 0x19e9 -#define MMC_DEVID 0x19db -#define LPC_DEVID 0x19dc -#define P2SB_DEVID 0x19dd -#define PMC_DEVID 0x19de -#define SMBUS_DEVID 0x19df -#define SPI_DEVID 0x19e0 -#define NPK_DEVID 0x19e1 - #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 123fb24cda..6481cbe00b 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -324,7 +324,7 @@ static struct device_operations device_ops = { static const struct pci_driver lpc_driver __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_LPC, }; static void finalize_chipset(void *unused) diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index 0404893450..631aac762a 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -46,5 +46,5 @@ static struct device_operations pmc_ops = { static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = NPK_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB, }; diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8b520873e5..cbb9a4ead8 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -113,5 +113,5 @@ static struct device_operations pmc_ops = { static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PMC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_PMC, }; diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index ddb8b02192..d53d5535f0 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -74,8 +74,8 @@ static struct device_operations sata_ops = { }; static const unsigned short pci_device_ids[] = { - AHCI_DEVID, /* DVN SATA AHCI */ - AHCI2_DEVID, /* DVN SATA2 AHCI */ + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1, + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2, 0 }; diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 264e139210..d8e42401c1 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -344,8 +344,8 @@ static struct device_operations systemagent_ops = { /* IDs for System Agent device of Intel Denverton SoC */ static const unsigned short systemagent_ids[] = { - SA_DEVID, /* DVN System Agent */ - SA_DEVID_DNVAD, /* DVN-AD System Agent */ + PCI_DEVICE_ID_INTEL_DENVERTON_SA, + PCI_DEVICE_ID_INTEL_DENVERTONAD_SA, 0 }; diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 50f8a290ae..28e0e2e551 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -58,7 +58,7 @@ static struct device_operations uart_ops = { }; static const unsigned short uart_ids[] = { - HSUART_DEVID, /* HSUART 0/1/2 */ + PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, 0 }; diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index 0a4b3b13ae..a0ed6bae2f 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -47,5 +47,5 @@ static struct device_operations usb_xhci_ops = { static const struct pci_driver pch_usb_xhci __pci_driver = { .ops = &usb_xhci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = XHCI_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_XHCI, }; From 23f870ad3a59983533c502e5dd744edde054d193 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 22 Nov 2019 00:31:48 +0100 Subject: [PATCH 0211/1463] soc/intel/denverton/uart.c: Clean up code Since there is only one device ID used for UART, an array is not needed. Therefore, just save the device ID to the device variable. Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/37121 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/denverton_ns/uart.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 28e0e2e551..3b851ee973 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -57,15 +57,10 @@ static struct device_operations uart_ops = { .enable = DEVICE_NOOP }; -static const unsigned short uart_ids[] = { - PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, - 0 -}; - static const struct pci_driver uart_driver __pci_driver = { .ops = &uart_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = uart_ids + .device = PCI_DEVICE_ID_INTEL_DENVERTON_HSUART }; static void hide_hsuarts(void) From 528ae9e811939c5e453c57aea79bc420a5f5fc43 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 28 Feb 2020 17:20:05 -0800 Subject: [PATCH 0212/1463] soc/tigerlake: Correct FSP log interface Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index d76961515f..f0f3b4cadd 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -61,7 +61,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : + DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; From eaba79cc66176ed9d9be23bce122b9d7bc238ed6 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 26 Feb 2020 22:26:17 +0530 Subject: [PATCH 0213/1463] src/soc/tigerlake: Add memory configuration support for Jasper Lake BUG=none BRANCH=none TEST=Build and verify boot of WaddleDoo. Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/39135 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar --- src/soc/intel/tigerlake/Makefile.inc | 1 + .../intel/tigerlake/include/soc/meminit_jsl.h | 119 +++++++++++++++++ src/soc/intel/tigerlake/meminit_jsl.c | 120 ++++++++++++++++++ 3 files changed, 240 insertions(+) create mode 100644 src/soc/intel/tigerlake/include/soc/meminit_jsl.h create mode 100644 src/soc/intel/tigerlake/meminit_jsl.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 56119f50db..89ef877db2 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -26,6 +26,7 @@ bootblock-y += p2sb.c romstage-y += espi.c romstage-y += gpio.c romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += meminit_jsl.c romstage-y += reset.c ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h new file mode 100644 index 0000000000..588ad5c58d --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ +#define _SOC_JASPERLAKE_MEMCFG_INIT_H_ + +#include +#include +#include + +/* Number of dq bits controlled per dqs */ +#define DQ_BITS_PER_DQS 8 + +/* Number of memory packages, where a "package" represents a 64-bit solution */ +#define DDR_NUM_PACKAGES 2 + +/* Number of DQ byte mappings */ +#define DDR_NUM_BYTE_MAPPINGS 6 + +/* 64-bit Channel identification */ +enum { + DDR_CH0, + DDR_CH1, + DDR_NUM_CHANNELS +}; + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory dq mapping information */ +struct mb_cfg { + + /* + * For each channel, there are 6 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, even though the last 3 sets + * are not used in JSL. + * We let the meminit_dq_dqs_map routine take care of clearing the + * unused fields for the caller. + * Note that dq_map is only used by LPDDR; it does not need to be + * initialized for designs using DDR4. + */ + uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES]; + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + * dqs_map is only used by LPDDR; same comments apply as for dq_map + * above. + */ + uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + uint16_t rcomp_resistor[3]; + + /* + * Rcomp target values. These will typically be the following + * values for Jasper Lake : { 80, 40, 40, 40, 30 } + */ + uint16_t rcomp_targets[5]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; + + /* Board type */ + uint8_t UserBd; +}; + +/* + * Initialize default memory configurations for Jasper Lake. + */ + +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated); + +#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit_jsl.c b/src/soc/intel/tigerlake/meminit_jsl.c new file mode 100644 index 0000000000..f977ce2cc3 --- /dev/null +++ b/src/soc/intel/tigerlake/meminit_jsl.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static void spd_read_from_cbfs(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, + size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd_info->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, + size_t *spd_data_len) +{ + if (spd_info->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd_info->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + bool half_populated) +{ + memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, + sizeof(mem_cfg->RcompResistor)); + + memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, + sizeof(mem_cfg->RcompTarget)); + + memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], + sizeof(board_cfg->dq_map[DDR_CH0])); + + memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], + sizeof(board_cfg->dqs_map[DDR_CH0])); + + if (half_populated) + return; + + memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], + sizeof(board_cfg->dq_map[DDR_CH1])); + + memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], + sizeof(board_cfg->dqs_map[DDR_CH1])); +} + +static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + uintptr_t spd_data_ptr, bool half_populated) +{ + /* Channel 0 */ + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + mem_cfg->MemorySpdPtr01 = 0; + + if (half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + spd_data_ptr = 0; + } + + /* Channel 1 */ + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + mem_cfg->MemorySpdPtr11 = 0; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated) +{ + size_t spd_data_len; + uintptr_t spd_data_ptr; + + memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); + get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + + /* Early Command Training Enabled */ + mem_cfg->ECT = board_cfg->ect; + + mem_cfg->UserBd = board_cfg->UserBd; +} From 7af59f709a89d20c1691d1a7316b136c7024aaf9 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 11 Jan 2020 13:53:10 -0500 Subject: [PATCH 0214/1463] sb/intel/i82371eb: Enable upper NVRAM bank Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38368 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82371eb/bootblock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 711b317e16..581db816a8 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -61,4 +61,7 @@ void bootblock_early_southbridge_init(void) reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB; reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ pci_write_config16(dev, XBCS, reg16); + + /* Enable (RTC and) upper NVRAM bank. */ + pci_write_config8(dev, RTCCFG, RTC_POS_DECODE | UPPER_RAM_EN | RTC_ENABLE); } From ce622389983f941f5b86907c41c9c843fadccce0 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 11 Jan 2020 03:49:17 -0500 Subject: [PATCH 0215/1463] sb/intel/i82371eb: Support reconfiguring GPO22/23 XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not required. Turns out asus/p2b-ls is using them to control termination for the onboard SCSI buses. Add support to allow this reconfiguration. Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38352 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82371eb/chip.h | 3 +++ src/southbridge/intel/i82371eb/isa.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h index 28975a2bbb..986208208e 100644 --- a/src/southbridge/intel/i82371eb/chip.h +++ b/src/southbridge/intel/i82371eb/chip.h @@ -28,6 +28,9 @@ struct southbridge_intel_i82371eb_config { int ide1_drive1_udma33_enable:1; int ide_legacy_enable:1; int usb_enable:1; + int gpo22_enable:1; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */ + int gpo22:1; + int gpo23:1; /* acpi */ u32 gpo; /* gpio output default */ u8 lid_polarity; diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bb88f7ddc0..a57d61ae03 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -28,6 +28,7 @@ #include #endif #include "i82371eb.h" +#include "chip.h" #if CONFIG(IOAPIC) static void enable_intel_82093aa_ioapic(void) @@ -63,6 +64,7 @@ static void enable_intel_82093aa_ioapic(void) static void isa_init(struct device *dev) { u32 reg32; + struct southbridge_intel_i82371eb_config *sb = dev->chip_info; /* Initialize the real time clock (RTC). */ cmos_init(0); @@ -80,7 +82,10 @@ static void isa_init(struct device *dev) */ reg32 = pci_read_config32(dev, GENCFG); reg32 |= ISA; /* Select ISA, not EIO. */ - pci_write_config16(dev, GENCFG, reg32); + + /* Some boards use GPO22/23. Select it if configured. */ + reg32 = ONOFF(sb->gpo22_enable, reg32, GPO2223); + pci_write_config32(dev, GENCFG, reg32); /* Initialize ISA DMA. */ isa_dma_init(); From 872fced41dde0b7d168900a61b916682c5cf7b46 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 26 Feb 2020 23:03:47 +0530 Subject: [PATCH 0216/1463] mb/google/dedede: Add memory initialization support for dedede Update memory parameters based on memory type supported by dedede 1. Update dq/dqs mappings 2. Update spd data for Micron Memory 3. Add SPD data binary files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST=Build dedede, flash and boot to kernel. Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e Signed-off-by: Meera Ravindranath Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136 Reviewed-by: Furquan Shaikh Reviewed-by: Ronak Kanabar Reviewed-by: V Sowmya Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/Kconfig | 5 ++ src/mainboard/google/dedede/Makefile.inc | 2 + src/mainboard/google/dedede/romstage.c | 12 ++- src/mainboard/google/dedede/spd/Makefile.inc | 25 +++++++ .../spd/Micron_MT53E512M32D2NP_2GB.spd.hex | 32 ++++++++ src/mainboard/google/dedede/spd/empty.spd.hex | 32 ++++++++ .../dedede/variants/baseboard/Makefile.inc | 2 + .../google/dedede/variants/baseboard/gpio.c | 17 +++++ .../baseboard/include/baseboard/gpio.h | 6 ++ .../baseboard/include/baseboard/variants.h | 6 ++ .../google/dedede/variants/baseboard/memory.c | 73 +++++++++++++++++++ .../dedede/variants/waddledoo/Makefile.inc | 10 +++ 12 files changed, 220 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/dedede/spd/Makefile.inc create mode 100644 src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex create mode 100644 src/mainboard/google/dedede/spd/empty.spd.hex create mode 100644 src/mainboard/google/dedede/variants/baseboard/memory.c create mode 100644 src/mainboard/google/dedede/variants/waddledoo/Makefile.inc diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 3eddabc985..ebca580ffa 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI + select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE @@ -31,6 +32,10 @@ config DEVICETREE string default "variants/baseboard/devicetree.cb" +config DIMM_SPD_SIZE + int + default 512 + config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index 2be3feb679..9af93dd2f2 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -13,6 +13,8 @@ ramstage-y += board_info.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c subdirs-y += variants/baseboard +subdirs-y += spd + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index bba6e1a320..8f4756b5df 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,10 +6,18 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include +#include #include void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* ToDo : Fill FSP-M memory params */ + const struct mb_cfg *board_cfg = variant_memcfg_config(); + const struct spd_info spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = variant_memory_sku(), + }; + /* TODO: Read the resistor strap to get number of memory segments. */ + bool half_populated = 0; + memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc new file mode 100644 index 0000000000..7de7f83a4c --- /dev/null +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +ifneq ($(SPD_SOURCES),) +SPD_BIN = $(obj)/spd.bin + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd +endif diff --git a/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex b/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex new file mode 100644 index 0000000000..71e5456542 --- /dev/null +++ b/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/spd/empty.spd.hex b/src/mainboard/google/dedede/spd/empty.spd.hex new file mode 100644 index 0000000000..67b46cd239 --- /dev/null +++ b/src/mainboard/google/dedede/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc index 7c092e44c2..4f87de9c41 100644 --- a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c smm-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index b8ceae2f8c..83922422c1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -45,6 +45,14 @@ static const struct pad_config gpio_table[] = { /* B23 : EC_AP_USB_C1_HDMI_HPD */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), + /* C0 : RAM_STRAP_0 */ + PAD_CFG_GPI(GPP_C0, NONE, DEEP), + /* C3 : RAM_STRAP_1 */ + PAD_CFG_GPI(GPP_C3, NONE, DEEP), + /* C4 : RAM_STRAP_2 */ + PAD_CFG_GPI(GPP_C4, NONE, DEEP), + /* C5 : RAM_STRAP_3 */ + PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ @@ -113,6 +121,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : RAM_STRAP_0 */ + PAD_CFG_GPI(GPP_C0, NONE, DEEP), + /* C3 : RAM_STRAP_1 */ + PAD_CFG_GPI(GPP_C3, NONE, DEEP), + /* C4 : RAM_STRAP_2 */ + PAD_CFG_GPI(GPP_C4, NONE, DEEP), + /* C5 : RAM_STRAP_3 */ + PAD_CFG_GPI(GPP_C5, NONE, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index fe9c0c5c75..395143b666 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -18,4 +18,10 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C0 +#define GPIO_MEM_CONFIG_1 GPP_C3 +#define GPIO_MEM_CONFIG_2 GPP_C4 +#define GPIO_MEM_CONFIG_3 GPP_C5 + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 32b2c8b4e7..a0facb261d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -28,4 +28,10 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); */ int board_info_get_fw_config(uint32_t *fw_config); +/* Return memory configuration structure. */ +const struct mb_cfg *variant_memcfg_config(void); + +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c new file mode 100644 index 0000000000..bcb12959d1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on SoC + * the value = pin number on LPDDR4 part + */ + + .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6}, + .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6}, + + /* WaddleDoo uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* WaddleDoo Rcomp target values */ + .rcomp_targets = {80, 40, 40, 40, 30}, + + /* Disable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *__weak variant_memcfg_config(void) +{ + return &baseboard_memcfg_cfg; +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc new file mode 100644 index 0000000000..28da8f636b --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -0,0 +1,10 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_SOURCES = empty #0b0000 +SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 From 3fa3bf97e514f046ee9c3d77af4b1a4f8fd07edb Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 23 Nov 2019 12:55:35 +0100 Subject: [PATCH 0217/1463] cpu/intel/slot_1: Cache romstage XIP execution Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37164 Reviewed-by: Angel Pons Reviewed-by: Keith Hui Tested-by: build bot (Jenkins) --- src/cpu/intel/slot_1/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 791997499d..a8d90e8b6f 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select SETUP_XIP_CACHE config DCACHE_RAM_BASE hex From 2b9004de602f98a404b17584ab3e1451f165c1f4 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 27 Jan 2020 18:05:45 -0500 Subject: [PATCH 0218/1463] i82371eb: Drop support for older PIIX chips All boards using this code use i82371eb (that shares PCI ID with i82371ab). Dropping the code lightens compressed ramstage by a few dozen bytes. Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38598 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82371eb/i82371eb.c | 19 +-------- src/southbridge/intel/i82371eb/ide.c | 51 ----------------------- src/southbridge/intel/i82371eb/isa.c | 6 --- src/southbridge/intel/i82371eb/usb.c | 9 ---- 4 files changed, 2 insertions(+), 83 deletions(-) diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 898cdffc25..02812ce40c 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -14,22 +14,9 @@ * GNU General Public License for more details. */ -/* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */ +/* Note: This code supports the 82371AB/EB/MB. */ /* Datasheets: - * - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR - * - URL: http://www.intel.com/design/intarch/datashts/290550.htm - * - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf - * - Date: April 1997 - * - Order Number: 290550-002 - * - * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator - * Specification Update - * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm - * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf - * - Date: March 1998 - * - Order Number: 297658-004 - * * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm @@ -44,10 +31,8 @@ * - Order Number: 297738-017 */ -/* TODO: List the other datasheets. */ - #include const struct chip_operations southbridge_intel_i82371eb_ops = { - CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") + CHIP_NAME("Intel 82371AB/EB/MB Southbridge") }; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 7a72a6552d..1b8136a9ca 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -118,18 +118,6 @@ static void ide_init_udma33(struct device *dev) } } -/** - * IDE init for the Intel 82371FB/SB IDE controller. - * - * These devices do not support UDMA/33, so don't attempt to enable it. - * - * @param dev The device to use. - */ -static void ide_init_i82371fb_sb(struct device *dev) -{ - ide_init_enable(dev); -} - /** * IDE init for the Intel 82371AB/EB/MB IDE controller. * @@ -141,17 +129,6 @@ static void ide_init_i82371ab_eb_mb(struct device *dev) ide_init_udma33(dev); } -/* Intel 82371FB/SB */ -static const struct device_operations ide_ops_fb_sb = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init_i82371fb_sb, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, /* No subsystem IDs on 82371XX! */ -}; - /* Intel 82371AB/EB/MB */ static const struct device_operations ide_ops_ab_eb_mb = { .read_resources = pci_dev_read_resources, @@ -163,34 +140,6 @@ static const struct device_operations ide_ops_ab_eb_mb = { .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; -/* Intel 82371FB (PIIX) */ -static const struct pci_driver ide_driver_fb __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, -}; - -/* Intel 82371SB (PIIX3) */ -static const struct pci_driver ide_driver_sb __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, -}; - -/* Intel 82371MX (MPIIX) */ -static const struct pci_driver ide_driver_mx __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, -}; - -/* Intel 82437MX (part of the 430MX chipset) */ -static const struct pci_driver ide_driver_82437mx __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, -}; - /* Intel 82371AB/EB/MB */ static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { .ops = &ide_ops_ab_eb_mb, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index a57d61ae03..fefead06e4 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -157,9 +157,3 @@ static const struct pci_driver isa_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; - -static const struct pci_driver isa_SB_driver __pci_driver = { - .ops = &isa_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, -}; diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 80b19a187e..38ab167733 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -43,15 +43,6 @@ static const struct device_operations usb_ops = { .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; -/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ - -/* Intel 82371SB (PIIX3) */ -static const struct pci_driver usb_driver_sb __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_USB, -}; - /* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ /* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = { From 2f3c37bd6266dba75498f1f629d42a2886dbc756 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 27 Jan 2020 18:00:40 -0500 Subject: [PATCH 0219/1463] i82371eb: Roll 82093aa init into isa_init() This allows reuse of dev and reg32 already available, and converting the block from #if to simple if. Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38599 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/southbridge/intel/i82371eb/isa.c | 56 +++++++++++----------------- 1 file changed, 22 insertions(+), 34 deletions(-) diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index fefead06e4..bdad959100 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -30,37 +30,6 @@ #include "i82371eb.h" #include "chip.h" -#if CONFIG(IOAPIC) -static void enable_intel_82093aa_ioapic(void) -{ - u16 reg16; - u32 reg32; - u8 ioapic_id = 2; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - struct device *dev; - - dev = dev_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_ISA, 0); - - /* Enable IOAPIC. */ - reg16 = pci_read_config16(dev, XBCS); - reg16 |= (1 << 8); /* APIC Chip Select */ - pci_write_config16(dev, XBCS, reg16); - - /* Set the IOAPIC ID. */ - *ioapic_index = 0; - *ioapic_data = ioapic_id << 24; - - /* Read back and verify the IOAPIC ID. */ - *ioapic_index = 0; - reg32 = (*ioapic_data >> 24) & 0x0f; - printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); - if (reg32 != ioapic_id) - die("IOAPIC error!\n"); -} -#endif - static void isa_init(struct device *dev) { u32 reg32; @@ -90,7 +59,6 @@ static void isa_init(struct device *dev) /* Initialize ISA DMA. */ isa_dma_init(); -#if CONFIG(IOAPIC) /* * Unlike most other southbridges the 82371EB doesn't have a built-in * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs @@ -99,8 +67,28 @@ static void isa_init(struct device *dev) * Thus, we can/must only enable the IOAPIC if it actually exists, * i.e. the respective mainboard does "select IOAPIC". */ - enable_intel_82093aa_ioapic(); -#endif + if (CONFIG(IOAPIC)) { + u16 reg16; + u8 ioapic_id = 2; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + + /* Enable IOAPIC. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= (1 << 8); /* APIC Chip Select */ + pci_write_config16(dev, XBCS, reg16); + + /* Set the IOAPIC ID. */ + *ioapic_index = 0; + *ioapic_data = ioapic_id << 24; + + /* Read back and verify the IOAPIC ID. */ + *ioapic_index = 0; + reg32 = (*ioapic_data >> 24) & 0x0f; + printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); + if (reg32 != ioapic_id) + die("IOAPIC error!\n"); + } } static void sb_read_resources(struct device *dev) From 8e9801380b57bb76bdc2a1f71e48c1605f881d3e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 4 Nov 2019 09:33:04 +0100 Subject: [PATCH 0220/1463] Kconfig: Have GDB_STUB depend on DRIVERS_UART MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no reason to hide the GDB_STUB option when CONSOLE_SERIAL is not set. Change-Id: Icbf9a1ac0e617939cafa3d66774bbd467dc01cbc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36604 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Nico Huber --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 16bc4ab524..d92bfd6769 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -764,7 +764,7 @@ comment "General Debug Settings" config GDB_STUB bool "GDB debugging support" default n - depends on CONSOLE_SERIAL + depends on DRIVERS_UART help If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details. From c052ba0ac11914b8b1bf4dc190a1f6b8d9b6ace1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 19:51:13 +0100 Subject: [PATCH 0221/1463] payloads/ext/Makefile.inc: Fix SeaBIOS race condition For a very long time, SeaBIOS sometimes failed to build when using multiple threads. This known problem has been haunting everyone for a very long time. Until now. Unlike most other payloads, building SeaBIOS results in two files: the SeaBIOS payload itself and SeaVGABIOS. Each file has its own target, and there's a third target called "seabios", which has the same recipe as the SeaBIOS file, which calls `payloads/external/SeaBIOS/Makefile` with a bunch of arguments. In addition, SeaVGABIOS depends on "seabios". When executing serially, if the file of either SeaBIOS or SeaVGABIOS is needed, the SeaBIOS Makefile will be run. This will generate both files, so it is not necessary to run the Makefile more than once. However, when using multiple threads, it can happen that one thread wants to make the SeaBIOS file, while another one wants to make the SeaVGABIOS file, which depends on "seabios". This implies that both threads will execute the SeaBIOS Makefile at about the same time, only to collide when performing git operations. Since git uses a lock file when updating the index, one of the threads will fail to acquire the lock with an error, which will ultimately cause the build to fail. Whenever this happened, manually aborting with Ctrl-C made the build process fail again because of the same error. The only way to get past this problem, other than using one thread, was to let the unfinished jobs complete. The thread that acquired the lock on the SeaBIOS git repository would finish building SeaBIOS, so that target would not need to be remade. When restarting the build, only the target that failed is rebuilt, so it does not collide with any other thread. To address this issue, make the SeaVGABIOS file target depend directly on the SeaBIOS file instead, and remove the duplicate "seabios" target. Change-Id: I251190d3bb27052ff474f3cd1a45022dab6fac31 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39188 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber --- payloads/external/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index b8af8c9120..0a96aff90b 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -78,7 +78,7 @@ etc/grub.cfg-required := the GRUB runtime configuration file ($(CONFIG_GRUB2_RUN # SeaBIOS SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) -payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) +payloads/external/SeaBIOS/seabios/out/bios.bin.elf: $(DOTCONFIG) $(MAKE) -C payloads/external/SeaBIOS \ HOSTCC="$(HOSTCC)" \ CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \ @@ -104,7 +104,7 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \ CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) -payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios +payloads/external/SeaBIOS/seabios/out/vgabios.bin: payloads/external/SeaBIOS/seabios/out/bios.bin.elf payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf From 1c2313d339ba5da92d092451ec2a253acaa2563c Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 16 Dec 2019 18:43:52 +0530 Subject: [PATCH 0222/1463] soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela Signed-off-by: Ronak Kanabar Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- .../block/include/intelblocks/gpio_defs.h | 1 + src/soc/intel/tigerlake/Makefile.inc | 12 +- src/soc/intel/tigerlake/acpi/gpio.asl | 95 +---- src/soc/intel/tigerlake/acpi/gpio_op.asl | 140 +++++++ src/soc/intel/tigerlake/chip.h | 8 +- src/soc/intel/tigerlake/gpio_jsl.c | 211 ++++++++++ .../intel/tigerlake/{gpio.c => gpio_tgl.c} | 2 +- src/soc/intel/tigerlake/include/soc/gpio.h | 22 +- .../intel/tigerlake/include/soc/gpio_defs.h | 304 +------------- .../tigerlake/include/soc/gpio_defs_jsl.h | 273 ++++++++++++ .../tigerlake/include/soc/gpio_defs_tgl.h | 315 ++++++++++++++ .../tigerlake/include/soc/gpio_soc_defs.h | 373 +---------------- .../tigerlake/include/soc/gpio_soc_defs_jsl.h | 359 ++++++++++++++++ .../tigerlake/include/soc/gpio_soc_defs_tgl.h | 395 ++++++++++++++++++ src/soc/intel/tigerlake/include/soc/pmc.h | 43 +- 15 files changed, 1784 insertions(+), 769 deletions(-) create mode 100644 src/soc/intel/tigerlake/acpi/gpio_op.asl create mode 100644 src/soc/intel/tigerlake/gpio_jsl.c rename src/soc/intel/tigerlake/{gpio.c => gpio_tgl.c} (99%) create mode 100644 src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h create mode 100644 src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h create mode 100644 src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h create mode 100644 src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index f460bcd109..3e9250e7c9 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -23,6 +23,7 @@ #define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) #define PAD_CFG0_TX_DISABLE (1 << 8) #define PAD_CFG0_RX_DISABLE (1 << 9) +#define PAD_CFG0_MODE_SHIFT 10 #define PAD_CFG0_MODE_MASK (7 << 10) #define PAD_CFG0_MODE_GPIO (0 << 10) #define PAD_CFG0_MODE_FUNC(x) ((x) << 10) diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 89ef877db2..9d8fa6f692 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -20,13 +20,15 @@ bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-y += gpio.c +bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c +bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c bootblock-y += p2sb.c romstage-y += espi.c -romstage-y += gpio.c romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += meminit_jsl.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c romstage-y += reset.c ramstage-y += acpi.c @@ -37,7 +39,8 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c -ramstage-y += gpio.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c +ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c @@ -47,7 +50,8 @@ ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c -smm-y += gpio.c +smm-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c +smm-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c smm-y += p2sb.c smm-y += pmc.c smm-y += pmutil.c diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index f6cccfb801..0378b52be3 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,10 +15,12 @@ #include #include #include +#include +#include "gpio_op.asl" Device (GCM0) { - Name (_HID, "INT34C5") + Name (_HID, CROS_GPIO_NAME) Name (_UID, 0) Name (_DDN, "GPIO Controller Community 0") @@ -42,7 +44,7 @@ Device (GCM0) Device (GCM1) { - Name (_HID, "INT34C5") + Name (_HID, CROS_GPIO_NAME) Name (_UID, 1) Name (_DDN, "GPIO Controller Community 1") @@ -66,7 +68,7 @@ Device (GCM1) Device (GCM4) { - Name (_HID, "INT34C5") + Name (_HID, CROS_GPIO_NAME) Name (_UID, 4) Name (_DDN, "GPIO Controller Community 4") @@ -90,7 +92,7 @@ Device (GCM4) Device (GCM5) { - Name (_HID, "INT34C5") + Name (_HID, CROS_GPIO_NAME) Name (_UID, 5) Name (_DDN, "GPIO Controller Community 5") @@ -119,95 +121,36 @@ Device (GCM5) Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (Arg0 >= GPP_B0 && Arg0 <= GPP_A24) + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) { Local0 = PID_GPIOCOM0 - Local1 = Arg0 - GPP_B0 + Local1 = Arg0 - GPIO_COM0_START } /* GPIO Community 1 */ - If (Arg0 >= GPP_S0 && Arg0 <= vI2S2_RXD) + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) { Local0 = PID_GPIOCOM1 - Local1 = Arg0 - GPP_S0 + Local1 = Arg0 - GPIO_COM1_START } /* GPIO Community 2 */ - If (Arg0 >= GPD0 && Arg0 <= GPD_DRAM_RESETB) + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) { Local0 = PID_GPIOCOM2 - Local1 = Arg0 - GPD0 + Local1 = Arg0 - GPIO_COM2_START } /* GPIO Community 4 */ - If (Arg0 >= GPP_C0 && Arg0 <= GPP_DBG_PMODE) + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) { Local0 = PID_GPIOCOM4 - Local1 = Arg0 - GPP_C0 + Local1 = Arg0 - GPIO_COM4_START } - /* GPIO Community 5 */ - If (Arg0 >= GPP_R0 && Arg0 <= GPP_CLK_LOOPBK) + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) { Local0 = PID_GPIOCOM5 - Local1 = Arg0 - GPP_R0 + Local1 = Arg0 - GPIO_COM5_START } + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) Return (Local2) } - -/* - * Get GPIO Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT) - - Return (Local0) -} - -/* - * Get GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (GTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Local0 = GPIOTXSTATE_MASK & VAL0 - - Return (Local0) -} - -/* - * Set GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (STXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - VAL0 |= GPIOTXSTATE_MASK -} - -/* - * Clear GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (CTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - VAL0 &= ~GPIOTXSTATE_MASK -} diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl new file mode 100644 index 0000000000..a16ebf753d --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Get GPIO Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (PAD_CFG0_TX_STATE, VAL0, Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (PAD_CFG0_TX_STATE, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0) +} + +/* + * Set Pad mode + * Arg0 - GPIO Number + * Arg1 - Pad mode + * 0 = GPIO control pad + * 1 = Native Function 1 + * 2 = Native Function 2 + * 3 = Native Function 3 + */ +Method (GPMO, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Store (VAL0, Local0) + And (Not (PAD_CFG0_MODE_MASK), Local0, Local0) + And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1) + Or (Local0, Arg1, VAL0) +} + +/* + * Enable/Disable Tx buffer + * Arg0 - GPIO Number + * Arg1 - TxBuffer state + * 0 = Disable Tx Buffer + * 1 = Enable Tx Buffer + */ +Method (GTXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (LEqual (Arg1, 1)) { + And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0) + } ElseIf (LEqual (Arg1, 0)){ + Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0) + } +} + +/* + * Enable/Disable Rx buffer + * Arg0 - GPIO Number + * Arg1 - RxBuffer state + * 0 = Disable Rx Buffer + * 1 = Enable Rx Buffer + */ +Method (GRXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (LEqual (Arg1, 1)) { + And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0) + } ElseIf (LEqual (Arg1, 0)){ + Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0) + } +} diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 02855b1b00..9eee97d53b 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,19 +16,19 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include #include +#include #include #include -#include #include #include -#include #include +#include #include #include #include #include +#include #define MAX_HD_AUDIO_DMIC_LINKS 2 #define MAX_HD_AUDIO_SNDW_LINKS 4 diff --git a/src/soc/intel/tigerlake/gpio_jsl.c b/src/soc/intel/tigerlake/gpio_jsl.c new file mode 100644 index 0000000000..bd0f5004b6 --- /dev/null +++ b/src/soc/intel/tigerlake/gpio_jsl.c @@ -0,0 +1,211 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; + +static const struct reset_mapping rst_map_com0[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO driver for Jasperlake on Windows/Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for JSP at: + * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c + */ +static const struct pad_group jsl_community0_groups[] = { + + INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */ + INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8), + INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ + INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10), + INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ + INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ +}; + +static const struct pad_group jsl_community1_groups[] = { + INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ + INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */ + INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), + INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ + INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group jsl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */ + INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17), +}; + + +static const struct pad_group jsl_community4_groups[] = { + INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23), + INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */ + INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36), +}; + + +static const struct pad_group jsl_community5_groups[] = { + INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */ +}; + +static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { + /* GPP F, B, A, S, R */ + [COMM_0] = { + .port = PID_GPIOCOM0, + .first_pad = GPP_F0, + .last_pad = GPP_R7, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FBASR", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_com0, + .num_reset_vals = ARRAY_SIZE(rst_map_com0), + .groups = jsl_community0_groups, + .num_groups = ARRAY_SIZE(jsl_community0_groups), + }, + /* GPP H, D, VGPIO, C */ + [COMM_1] = { + .port = PID_GPIOCOM1, + .first_pad = GPP_H0, + .last_pad = GPP_C23, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_HDC", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community1_groups, + .num_groups = ARRAY_SIZE(jsl_community1_groups), + }, + /* GPD */ + [COMM_2] = { + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPIO_RSVD_17, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community2_groups, + .num_groups = ARRAY_SIZE(jsl_community2_groups), + }, + /* GPP E */ + [COMM_4] = { + .port = PID_GPIOCOM4, + .first_pad = GPIO_RSVD_18, + .last_pad = GPIO_RSVD_36, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_E", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community4_groups, + .num_groups = ARRAY_SIZE(jsl_community4_groups), + }, + /* GPP G */ + [COMM_5] = { + .port = PID_GPIOCOM5, + .first_pad = GPP_G0, + .last_pad = GPP_G7, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_G", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community5_groups, + .num_groups = ARRAY_SIZE(jsl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(jsl_communities); + return jsl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_A, GPP_A }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPD, GPP_GPD }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_F, GPP_F } + }; + + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio_tgl.c similarity index 99% rename from src/soc/intel/tigerlake/gpio.c rename to src/soc/intel/tigerlake/gpio_tgl.c index 5b06b30d79..54ed5d3f92 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio_tgl.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index ccc274ba3e..3a39e3a153 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,9 +19,21 @@ #include #include -#define CROS_GPIO_COMM0_NAME "INT34C5:00" -#define CROS_GPIO_COMM1_NAME "INT34C5:01" -#define CROS_GPIO_COMM4_NAME "INT34C5:02" -#define CROS_GPIO_COMM5_NAME "INT34C5:03" +#if CONFIG(SOC_INTEL_TIGERLAKE) + + #define CROS_GPIO_NAME "INT34C5" + #define CROS_GPIO_COMM0_NAME "INT34C5:00" + #define CROS_GPIO_COMM1_NAME "INT34C5:01" + #define CROS_GPIO_COMM4_NAME "INT34C5:02" + #define CROS_GPIO_COMM5_NAME "INT34C5:03" + +#elif CONFIG(SOC_INTEL_JASPERLAKE) + + #define CROS_GPIO_NAME "INT34C8" + #define CROS_GPIO_COMM0_NAME "INT34C8:00" + #define CROS_GPIO_COMM1_NAME "INT34C8:01" + #define CROS_GPIO_COMM4_NAME "INT34C8:02" + #define CROS_GPIO_COMM5_NAME "INT34C8:03" +#endif #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index 6a5a6e2329..db5b3741cd 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,303 +16,9 @@ #ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_DEFS_H_ -#ifndef __ACPI__ -#include +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include +#elif CONFIG(SOC_INTEL_JASPERLAKE) + #include #endif -#include - -#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ - -#define NUM_GPIO_COMx_GPI_REGS(n) \ - (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) - -#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) -#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) -#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) -#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) - -#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS) +\ - (NUM_GPIO_COM5_GPI_REGS)) -/* - * IOxAPIC IRQs for the GPIOs - */ - -/* Group B */ -#define GPP_B0_IRQ 0x18 -#define GPP_B1_IRQ 0x19 -#define GPP_B2_IRQ 0x1A -#define GPP_B3_IRQ 0x1B -#define GPP_B4_IRQ 0x1C -#define GPP_B5_IRQ 0x1D -#define GPP_B6_IRQ 0x1E -#define GPP_B7_IRQ 0x1F -#define GPP_B8_IRQ 0x20 -#define GPP_B9_IRQ 0x21 -#define GPP_B10_IRQ 0x22 -#define GPP_B11_IRQ 0x23 -#define GPP_B12_IRQ 0x24 -#define GPP_B13_IRQ 0x25 -#define GPP_B14_IRQ 0x26 -#define GPP_B15_IRQ 0x27 -#define GPP_B16_IRQ 0x28 -#define GPP_B17_IRQ 0x29 -#define GPP_B18_IRQ 0x2A -#define GPP_B19_IRQ 0x2B -#define GPP_B20_IRQ 0x2C -#define GPP_B21_IRQ 0x2D -#define GPP_B22_IRQ 0x2E -#define GPP_B23_IRQ 0x2F - -/* Group T */ -#define GPP_T0_IRQ 0x30 -#define GPP_T1_IRQ 0x31 -#define GPP_T2_IRQ 0x32 -#define GPP_T3_IRQ 0x33 -#define GPP_T4_IRQ 0x34 -#define GPP_T5_IRQ 0x35 -#define GPP_T6_IRQ 0x36 -#define GPP_T7_IRQ 0x37 -#define GPP_T8_IRQ 0x38 -#define GPP_T9_IRQ 0x39 -#define GPP_T10_IRQ 0x3A -#define GPP_T11IRQ 0x3B -#define GPP_T12_IRQ 0x3C -#define GPP_T13_IRQ 0x3D -#define GPP_T14_IRQ 0x3E -#define GPP_T15_IRQ 0x3F - -/* Group A */ -#define GPP_A0_IRQ 0x40 -#define GPP_A1_IRQ 0x41 -#define GPP_A2_IRQ 0x42 -#define GPP_A3_IRQ 0x43 -#define GPP_A4_IRQ 0x44 -#define GPP_A5_IRQ 0x45 -#define GPP_A6_IRQ 0x46 -#define GPP_A7_IRQ 0x47 -#define GPP_A8_IRQ 0x48 -#define GPP_A9_IRQ 0x49 -#define GPP_A10_IRQ 0x4A -#define GPP_A11_IRQ 0x4B -#define GPP_A12_IRQ 0x4C -#define GPP_A13_IRQ 0x4D -#define GPP_A14_IRQ 0x4E -#define GPP_A15_IRQ 0x4F -#define GPP_A16_IRQ 0x50 -#define GPP_A17_IRQ 0x51 -#define GPP_A18_IRQ 0x52 -#define GPP_A19_IRQ 0x53 -#define GPP_A20_IRQ 0x54 -#define GPP_A21_IRQ 0x55 -#define GPP_A22_IRQ 0x56 -#define GPP_A23_IRQ 0x57 - -/* Group R */ -#define GPP_R0_IRQ 0x58 -#define GPP_R1_IRQ 0x59 -#define GPP_R2_IRQ 0x5A -#define GPP_R3_IRQ 0x5B -#define GPP_R4_IRQ 0x5C -#define GPP_R5_IRQ 0x5D -#define GPP_R6_IRQ 0x5E -#define GPP_R7_IRQ 0x5F - - -/* Group D */ -#define GPD0_IRQ 0x60 -#define GPD1_IRQ 0x61 -#define GPD2_IRQ 0x62 -#define GPD3_IRQ 0x63 -#define GPD4_IRQ 0x64 -#define GPD5_IRQ 0x65 -#define GPD6_IRQ 0x66 -#define GPD7_IRQ 0x67 -#define GPD8_IRQ 0x68 -#define GPD9_IRQ 0x69 -#define GPD10_IRQ 0x6A -#define GPD11_IRQ 0x6B - -/* Group S */ -#define GPP_S0_IRQ 0x6C -#define GPP_S1_IRQ 0x6D -#define GPP_S2_IRQ 0x6E -#define GPP_S3_IRQ 0x6F -#define GPP_S4_IRQ 0x70 -#define GPP_S5_IRQ 0x71 -#define GPP_S6_IRQ 0x72 -#define GPP_S7_IRQ 0x73 - -/* Group H */ -#define GPP_H0_IRQ 0x74 -#define GPP_H1_IRQ 0x75 -#define GPP_H2_IRQ 0x76 -#define GPP_H3_IRQ 0x77 -#define GPP_H4_IRQ 0x18 -#define GPP_H5_IRQ 0x19 -#define GPP_H6_IRQ 0x1A -#define GPP_H7_IRQ 0x1B -#define GPP_H8_IRQ 0x1C -#define GPP_H9_IRQ 0x1D -#define GPP_H10_IRQ 0x1E -#define GPP_H11_IRQ 0x1F -#define GPP_H12_IRQ 0x20 -#define GPP_H13_IRQ 0x21 -#define GPP_H14_IRQ 0x22 -#define GPP_H15_IRQ 0x23 -#define GPP_H16_IRQ 0x24 -#define GPP_H17_IRQ 0x25 -#define GPP_H18_IRQ 0x26 -#define GPP_H19_IRQ 0x27 -#define GPP_H20_IRQ 0x28 -#define GPP_H21_IRQ 0x29 -#define GPP_H22_IRQ 0x2A -#define GPP_H23_IRQ 0x2B - -/* Group D */ -#define GPP_D0_IRQ 0x2C -#define GPP_D1_IRQ 0x2D -#define GPP_D2_IRQ 0x2E -#define GPP_D3_IRQ 0x2F -#define GPP_D4_IRQ 0x30 -#define GPP_D5_IRQ 0x31 -#define GPP_D6_IRQ 0x32 -#define GPP_D7_IRQ 0x33 -#define GPP_D8_IRQ 0x34 -#define GPP_D9_IRQ 0x35 -#define GPP_D10_IRQ 0x36 -#define GPP_D11_IRQ 0x37 -#define GPP_D12_IRQ 0x38 -#define GPP_D13_IRQ 0x39 -#define GPP_D14_IRQ 0x3A -#define GPP_D15_IRQ 0x3B -#define GPP_D16_IRQ 0x3C -#define GPP_D17_IRQ 0x3D -#define GPP_D18_IRQ 0x3E -#define GPP_D19_IRQ 0x3F - - -/* Group U */ -#define GPP_U0_IRQ 0x40 -#define GPP_U1IRQ 0x41 -#define GPP_U2_IRQ 0x42 -#define GPP_U3_IRQ 0x43 -#define GPP_U4_IRQ 0x44 -#define GPP_U5_IRQ 0x45 -#define GPP_U6_IRQ 0x46 -#define GPP_U7_IRQ 0x47 -#define GPP_U8_IRQ 0x48 -#define GPP_U9_IRQ 0x49 -#define GPP_U10_IRQ 0x4A -#define GPP_U11_IRQ 0x4B -#define GPP_U12_IRQ 0x4C -#define GPP_U13_IRQ 0x4D -#define GPP_U14_IRQ 0x4E -#define GPP_U15_IRQ 0x4F -#define GPP_U16_IRQ 0x50 -#define GPP_U17_IRQ 0x51 -#define GPP_U18_IRQ 0x52 -#define GPP_U19_IRQ 0x53 - - -#define GPP_VGPIO4_IRQ 0x54 - -/* Group F */ -#define GPP_F0_IRQ 0x56 -#define GPP_F1_IRQ 0x57 -#define GPP_F2_IRQ 0x58 -#define GPP_F3_IRQ 0x59 -#define GPP_F4_IRQ 0x5A -#define GPP_F5_IRQ 0x5B -#define GPP_F6_IRQ 0x5C -#define GPP_F7_IRQ 0x5D -#define GPP_F8_IRQ 0x5E -#define GPP_F9_IRQ 0x5F -#define GPP_F10_IRQ 0x60 -#define GPP_F11_IRQ 0x61 -#define GPP_F12_IRQ 0x62 -#define GPP_F13_IRQ 0x63 -#define GPP_F14_IRQ 0x64 -#define GPP_F15_IRQ 0x65 -#define GPP_F16_IRQ 0x66 -#define GPP_F17_IRQ 0x67 -#define GPP_F18_IRQ 0x68 -#define GPP_F19_IRQ 0x69 -#define GPP_F20_IRQ 0x6A -#define GPP_F21_IRQ 0x6B -#define GPP_F22_IRQ 0x6C -#define GPP_F23_IRQ 0x6D - -/* Group C */ -#define GPP_C0_iIRQ 0x6E -#define GPP_C1_IRQ 0x6F -#define GPP_C2_IRQ 0x70 -#define GPP_C3_IRQ 0x71 -#define GPP_C4_IRQ 0x72 -#define GPP_C5_IRQ 0x73 -#define GPP_C6_IRQ 0x74 -#define GPP_C7_IRQ 0x75 -#define GPP_C8_IRQ 0x76 -#define GPP_C9_IRQ 0x77 -#define GPP_C10_IRQ 0x18 -#define GPP_C11_IRQ 0x19 -#define GPP_C12_IRQ 0x1A -#define GPP_C13_IRQ 0x1B -#define GPP_C14_IRQ 0x1C -#define GPP_C15_IRQ 0x1D -#define GPP_C16_IRQ 0x1E -#define GPP_C17_IRQ 0x1F -#define GPP_C18_IRQ 0x20 -#define GPP_C19_IRQ 0x21 -#define GPP_C20_IRQ 0x22 -#define GPP_C21_IRQ 0x23 -#define GPP_C22_IRQ 0x24 -#define GPP_C23_IRQ 0x25 - - - -/* Group E */ -#define GPP_E0_IRQ 0x26 -#define GPP_E1_IRQ 0x27 -#define GPP_E2_IRQ 0x28 -#define GPP_E3_IRQ 0x29 -#define GPP_E4_IRQ 0x30 -#define GPP_E5_IRQ 0x31 -#define GPP_E6_IRQ 0x32 -#define GPP_E7_IRQ 0x33 -#define GPP_E8_IRQ 0x34 -#define GPP_E9_IRQ 0x35 -#define GPP_E10_IRQ 0x36 -#define GPP_E11_IRQ 0x37 -#define GPP_E12_IRQ 0x38 -#define GPP_E13_IRQ 0x39 -#define GPP_E14_IRQ 0x3A -#define GPP_E15_IRQ 0x3B -#define GPP_E16_IRQ 0x3C -#define GPP_E17_IRQ 0x3D -#define GPP_E18_IRQ 0x3E -#define GPP_E19_IRQ 0x3F -#define GPP_E20_IRQ 0x40 -#define GPP_E21_IRQ 0x41 -#define GPP_E22_IRQ 0x42 -#define GPP_E23_IRQ 0x43 - -/* Register defines. */ -#define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xb0 -#define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x110 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1A0 -#define PAD_CFG_BASE 0x700 - -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h new file mode 100644 index 0000000000..c2d686366d --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_ +#define _SOC_JASPERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include +#endif +#include + + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group F */ +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + +/* Group B */ +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + +/* Group D */ +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b +#define GPP_D20_IRQ 0x3c +#define GPP_D21_IRQ 0x3d +#define GPP_D22_IRQ 0x3e +#define GPP_D23_IRQ 0x3f + +/* Group GPD */ +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group R*/ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1a0 +#define PAD_CFG_BASE 0x600 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h new file mode 100644 index 0000000000..7017aa8e87 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h @@ -0,0 +1,315 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ + +#ifndef __ACPI__ +#include +#endif +#include + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + + +/* Group D */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + + +/* Group U */ +#define GPP_U0_IRQ 0x40 +#define GPP_U1IRQ 0x41 +#define GPP_U2_IRQ 0x42 +#define GPP_U3_IRQ 0x43 +#define GPP_U4_IRQ 0x44 +#define GPP_U5_IRQ 0x45 +#define GPP_U6_IRQ 0x46 +#define GPP_U7_IRQ 0x47 +#define GPP_U8_IRQ 0x48 +#define GPP_U9_IRQ 0x49 +#define GPP_U10_IRQ 0x4A +#define GPP_U11_IRQ 0x4B +#define GPP_U12_IRQ 0x4C +#define GPP_U13_IRQ 0x4D +#define GPP_U14_IRQ 0x4E +#define GPP_U15_IRQ 0x4F +#define GPP_U16_IRQ 0x50 +#define GPP_U17_IRQ 0x51 +#define GPP_U18_IRQ 0x52 +#define GPP_U19_IRQ 0x53 + + +#define GPP_VGPIO4_IRQ 0x54 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + + + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index 62de63f740..145892b7d1 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,372 +14,11 @@ */ #ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ -/* - * Most of the fixed numbers and macros are based on the GPP groups. - * The GPIO groups are accessed through register blocks called - * communities. - */ -#define GPP_B 0x0 -#define GPP_T 0x1 -#define GPP_A 0x2 -#define GPP_R 0x3 -#define GPD 0x4 -#define GPP_S 0x5 -#define GPP_H 0x6 -#define GPP_D 0x7 -#define GPP_U 0x8 -#define GPP_F 0xA -#define GPP_C 0xB -#define GPP_E 0xC -#define GPIO_MAX_NUM_PER_GROUP 27 - -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -/* GPIO community 3 is not exposed to be used and hence is skipped. */ -#define COMM_4 3 -#define COMM_5 4 -/* - * GPIOs are ordered monotonically increasing to match ACPI/OS driver. - */ -/* Group B */ -#define GPP_B0 0 -#define GPP_B1 1 -#define GPP_B2 2 -#define GPP_B3 3 -#define GPP_B4 4 -#define GPP_B5 5 -#define GPP_B6 6 -#define GPP_B7 7 -#define GPP_B8 8 -#define GPP_B9 9 -#define GPP_B10 10 -#define GPP_B11 11 -#define GPP_B12 12 -#define GPP_B13 13 -#define GPP_B14 14 -#define GPP_B15 15 -#define GPP_B16 16 -#define GPP_B17 17 -#define GPP_B18 18 -#define GPP_B19 19 -#define GPP_B20 20 -#define GPP_B21 21 -#define GPP_B22 22 -#define GPP_B23 23 -#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ -#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ - -/* Group T */ -#define GPP_T0 26 -#define GPP_T1 27 -#define GPP_T2 28 -#define GPP_T3 29 -#define GPP_T4 30 -#define GPP_T5 31 -#define GPP_T6 32 -#define GPP_T7 33 -#define GPP_T8 34 -#define GPP_T9 35 -#define GPP_T10 36 -#define GPP_T11 37 -#define GPP_T12 38 -#define GPP_T13 39 -#define GPP_T14 40 -#define GPP_T15 41 - -/* Group A */ -#define GPP_A0 42 -#define GPP_A1 43 -#define GPP_A2 44 -#define GPP_A3 45 -#define GPP_A4 46 -#define GPP_A5 47 -#define GPP_A6 48 -#define GPP_A7 49 -#define GPP_A8 50 -#define GPP_A9 51 -#define GPP_A10 52 -#define GPP_A11 53 -#define GPP_A12 54 -#define GPP_A13 55 -#define GPP_A14 56 -#define GPP_A15 57 -#define GPP_A16 58 -#define GPP_A17 59 -#define GPP_A18 60 -#define GPP_A19 61 -#define GPP_A20 62 -#define GPP_A21 63 -#define GPP_A22 64 -#define GPP_A23 65 -#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ - -#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) - -/* Group S */ -#define GPP_S0 67 -#define GPP_S1 68 -#define GPP_S2 69 -#define GPP_S3 70 -#define GPP_S4 71 -#define GPP_S5 72 -#define GPP_S6 73 -#define GPP_S7 74 - -/* Group H */ -#define GPP_H0 75 -#define GPP_H1 76 -#define GPP_H2 77 -#define GPP_H3 78 -#define GPP_H4 79 -#define GPP_H5 80 -#define GPP_H6 81 -#define GPP_H7 82 -#define GPP_H8 83 -#define GPP_H9 84 -#define GPP_H10 85 -#define GPP_H11 86 -#define GPP_H12 87 -#define GPP_H13 88 -#define GPP_H14 89 -#define GPP_H15 90 -#define GPP_H16 91 -#define GPP_H17 92 -#define GPP_H18 93 -#define GPP_H19 94 -#define GPP_H20 95 -#define GPP_H21 96 -#define GPP_H22 97 -#define GPP_H23 98 - -/* Group D */ -#define GPP_D0 99 -#define GPP_D1 100 -#define GPP_D2 101 -#define GPP_D3 102 -#define GPP_D4 103 -#define GPP_D5 104 -#define GPP_D6 105 -#define GPP_D7 106 -#define GPP_D8 107 -#define GPP_D9 108 -#define GPP_D10 109 -#define GPP_D11 110 -#define GPP_D12 111 -#define GPP_D13 112 -#define GPP_D14 113 -#define GPP_D15 114 -#define GPP_D16 115 -#define GPP_D17 116 -#define GPP_D18 117 -#define GPP_D19 118 -#define GPP_GSPI2_CLK_LOOPBK 119 - -/* Group U */ -#define GPP_U0 120 -#define GPP_U1 121 -#define GPP_U2 122 -#define GPP_U3 123 -#define GPP_U4 124 -#define GPP_U5 125 -#define GPP_U6 126 -#define GPP_U7 127 -#define GPP_U8 128 -#define GPP_U9 129 -#define GPP_U10 130 -#define GPP_U11 131 -#define GPP_U12 132 -#define GPP_U13 133 -#define GPP_U14 134 -#define GPP_U15 135 -#define GPP_U16 136 -#define GPP_U17 137 -#define GPP_U18 138 -#define GPP_U19 139 -#define GPP_GSPI3_CLK_LOOPBK 140 -#define GPP_GSPI4_CLK_LOOPBK 141 -#define GPP_GSPI5_CLK_LOOPBK 142 -#define GPP_GSPI6_CLK_LOOPBK 143 - -/* Group VGPIO */ -#define CNV_BTEN 144 -#define CNV_BT_HOST_WAKEB 145 -#define CNV_BT_IF_SELECT 146 -#define vCNV_BT_UART_TXD 147 -#define vCNV_BT_UART_RXD 148 -#define vCNV_BT_UART_CTS_B 149 -#define vCNV_BT_UART_RTS_B 150 -#define vCNV_MFUART1_TXD 151 -#define vCNV_MFUART1_RXD 152 -#define vCNV_MFUART1_CTS_B 153 -#define vCNV_MFUART1_RTS_B 154 -#define vUART0_TXD 155 -#define vUART0_RXD 156 -#define vUART0_CTS_B 157 -#define vUART0_RTS_B 158 -#define vISH_UART0_TXD 159 -#define vISH_UART0_RXD 160 -#define vISH_UART0_CTS_B 161 -#define vISH_UART0_RTS_B 162 -#define vCNV_BT_I2S_BCLK 163 -#define vCNV_BT_I2S_WS_SYNC 164 -#define vCNV_BT_I2S_SDO 165 -#define vCNV_BT_I2S_SDI 166 -#define vI2S2_SCLK 167 -#define vI2S2_SFRM 168 -#define vI2S2_TXD 169 -#define vI2S2_RXD 170 - -#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) - -/* Group GPD */ -#define GPD0 171 -#define GPD1 172 -#define GPD2 173 -#define GPD3 174 -#define GPD4 175 -#define GPD5 176 -#define GPD6 177 -#define GPD7 178 -#define GPD8 179 -#define GPD9 180 -#define GPD10 181 -#define GPD11 182 -#define GPD_INPUT3VSEL 183 -#define GPD_SLP_LANB 184 -#define GPD__SLP_SUSB 185 -#define GPD_WAKEB 186 -#define GPD_DRAM_RESETB 187 - -#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) - -/* Group C */ -#define GPP_C0 188 -#define GPP_C1 189 -#define GPP_C2 190 -#define GPP_C3 191 -#define GPP_C4 192 -#define GPP_C5 193 -#define GPP_C6 194 -#define GPP_C7 195 -#define GPP_C8 196 -#define GPP_C9 197 -#define GPP_C10 198 -#define GPP_C11 199 -#define GPP_C12 200 -#define GPP_C13 201 -#define GPP_C14 202 -#define GPP_C15 203 -#define GPP_C16 204 -#define GPP_C17 205 -#define GPP_C18 206 -#define GPP_C19 207 -#define GPP_C20 208 -#define GPP_C21 209 -#define GPP_C22 210 -#define GPP_C23 211 - -/* Group F */ -#define GPP_F0 212 -#define GPP_F1 213 -#define GPP_F2 214 -#define GPP_F3 215 -#define GPP_F4 216 -#define GPP_F5 217 -#define GPP_F6 218 -#define GPP_F7 219 -#define GPP_F8 220 -#define GPP_F9 221 -#define GPP_F10 222 -#define GPP_F11 223 -#define GPP_F12 224 -#define GPP_F13 225 -#define GPP_F14 226 -#define GPP_F15 227 -#define GPP_F16 228 -#define GPP_F17 229 -#define GPP_F18 230 -#define GPP_F19 231 -#define GPP_F20 232 -#define GPP_F21 233 -#define GPP_F22 234 -#define GPP_F23 235 -#define GPP_F_CLK_LOOPBK 236 - -/* Group HVCMOS */ -#define GPP_L_BKLTEN 237 -#define GPP_L_BKLTCTL 238 -#define GPP_L_VDDEN 239 -#define GPP_SYS_PWROK 240 -#define GPP_SYS_RESETB 241 -#define GPP_MLK_RSTB 242 - -/* Group E */ -#define GPP_E0 243 -#define GPP_E1 244 -#define GPP_E2 245 -#define GPP_E3 246 -#define GPP_E4 247 -#define GPP_E5 248 -#define GPP_E6 249 -#define GPP_E7 250 -#define GPP_E8 251 -#define GPP_E9 252 -#define GPP_E10 253 -#define GPP_E11 254 -#define GPP_E12 255 -#define GPP_E13 256 -#define GPP_E14 257 -#define GPP_E15 258 -#define GPP_E16 259 -#define GPP_E17 260 -#define GPP_E18 261 -#define GPP_E19 262 -#define GPP_E20 263 -#define GPP_E21 264 -#define GPP_E22 265 -#define GPP_E23 266 -#define GPP_E_CLK_LOOPBK 267 - -/* Group JTAG */ -#define GPP_JTAG_TDO 268 -#define GPP_JTAG_X 269 -#define GPP_JTAG_PRDYB 270 -#define GPP_JTAG_PREQB 271 -#define GPP_CPU_TRSTB 272 -#define GPP_JTAG_TDI 273 -#define GPP_JTAG_TMS 274 -#define GPP_JTAG_TCK 275 -#define GPP_DBG_PMODE 276 - -#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) - -/* Group R */ -#define GPP_R0 277 -#define GPP_R1 278 -#define GPP_R2 279 -#define GPP_R3 280 -#define GPP_R4 281 -#define GPP_R5 282 -#define GPP_R6 283 -#define GPP_R7 284 - -/* Group SPI */ -#define GPP_SPI_IO_2 285 -#define GPP_SPI_IO_3 286 -#define GPP_SPI_MOSI_IO_0 287 -#define GPP_SPI_MOSI_IO_1 288 -#define GPP_SPI_TPM_CSB 289 -#define GPP_SPI_FLASH_0_CSB 290 -#define GPP_SPI_FLASH_1_CSB 291 -#define GPP_SPI_CLK 292 -#define GPP_CLK_LOOPBK 293 - -#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) - -#define TOTAL_GPIO_COMM (COMM_5 + 1) -#define TOTAL_PADS 294 +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "gpio_soc_defs_tgl.h" +#elif CONFIG(SOC_INTEL_JASPERLAKE) + #include "gpio_soc_defs_jsl.h" +#endif #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h new file mode 100644 index 0000000000..ce7d0d87e5 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h @@ -0,0 +1,359 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ +#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ + +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_G 0x2 +#define GPP_C 0x3 +#define GPP_R 0x4 +#define GPP_D 0x5 +#define GPP_S 0x6 +#define GPP_H 0x7 +#define GPP_VGPIO 0x8 +#define GPP_F 0x9 +#define GPP_GPD 0xA +#define GPP_E 0xD + +#define GPIO_NUM_GROUPS 11 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group F */ +#define GPP_F0 0 +#define GPP_F1 1 +#define GPP_F2 2 +#define GPP_F3 3 +#define GPP_F4 4 +#define GPP_F5 5 +#define GPP_F6 6 +#define GPP_F7 7 +#define GPP_F8 8 +#define GPP_F9 9 +#define GPP_F10 10 +#define GPP_F11 11 +#define GPP_F12 12 +#define GPP_F13 13 +#define GPP_F14 14 +#define GPP_F15 15 +#define GPP_F16 16 +#define GPP_F17 17 +#define GPP_F18 18 +#define GPP_F19 19 + +/* Group B */ +#define GPIO_RSVD_0 20 +#define GPIO_RSVD_1 21 +#define GPIO_RSVD_2 22 +#define GPIO_RSVD_3 23 +#define GPIO_RSVD_4 24 +#define GPIO_RSVD_5 25 +#define GPIO_RSVD_6 26 +#define GPIO_RSVD_7 27 +#define GPIO_RSVD_8 28 +#define GPP_B0 29 +#define GPP_B1 30 +#define GPP_B2 31 +#define GPP_B3 32 +#define GPP_B4 33 +#define GPP_B5 34 +#define GPP_B6 35 +#define GPP_B7 36 +#define GPP_B8 37 +#define GPP_B9 38 +#define GPP_B10 39 +#define GPP_B11 40 +#define GPP_B12 41 +#define GPP_B13 42 +#define GPP_B14 43 +#define GPP_B15 44 +#define GPP_B16 45 +#define GPP_B17 46 +#define GPP_B18 47 +#define GPP_B19 48 +#define GPP_B20 49 +#define GPP_B21 50 +#define GPP_B22 51 +#define GPP_B23 52 +#define GPIO_RSVD_9 53 +#define GPIO_RSVD_10 54 + +/* Group A */ +#define GPP_A0 55 +#define GPP_A1 56 +#define GPP_A2 57 +#define GPP_A3 58 +#define GPP_A4 59 +#define GPP_A5 60 +#define GPP_A6 61 +#define GPP_A7 62 +#define GPP_A8 63 +#define GPP_A9 64 +#define GPP_A10 65 +#define GPP_A11 66 +#define GPP_A12 67 +#define GPP_A13 68 +#define GPP_A14 69 +#define GPP_A15 70 +#define GPP_A16 71 +#define GPP_A17 72 +#define GPP_A18 73 +#define GPP_A19 74 +#define GPIO_RSVD_11 75 + +/* Group S */ +#define GPP_S0 76 +#define GPP_S1 77 +#define GPP_S2 78 +#define GPP_S3 79 +#define GPP_S4 80 +#define GPP_S5 81 +#define GPP_S6 82 +#define GPP_S7 83 + +/* Group R */ +#define GPP_R0 84 +#define GPP_R1 85 +#define GPP_R2 86 +#define GPP_R3 87 +#define GPP_R4 88 +#define GPP_R5 89 +#define GPP_R6 90 +#define GPP_R7 91 + +#define GPIO_COM0_START GPP_F0 +#define GPIO_COM0_END GPP_R7 +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group H */ +#define GPP_H0 92 +#define GPP_H1 93 +#define GPP_H2 94 +#define GPP_H3 95 +#define GPP_H4 96 +#define GPP_H5 97 +#define GPP_H6 98 +#define GPP_H7 99 +#define GPP_H8 100 +#define GPP_H9 101 +#define GPP_H10 102 +#define GPP_H11 103 +#define GPP_H12 104 +#define GPP_H13 105 +#define GPP_H14 106 +#define GPP_H15 107 +#define GPP_H16 108 +#define GPP_H17 109 +#define GPP_H18 110 +#define GPP_H19 111 +#define GPP_H20 112 +#define GPP_H21 113 +#define GPP_H22 114 +#define GPP_H23 115 + +/* Group D */ +#define GPP_D0 116 +#define GPP_D1 117 +#define GPP_D2 118 +#define GPP_D3 119 +#define GPP_D4 120 +#define GPP_D5 121 +#define GPP_D6 122 +#define GPP_D7 123 +#define GPP_D8 124 +#define GPP_D9 125 +#define GPP_D10 126 +#define GPP_D11 127 +#define GPP_D12 128 +#define GPP_D13 129 +#define GPP_D14 130 +#define GPP_D15 131 +#define GPP_D16 132 +#define GPP_D17 133 +#define GPP_D18 134 +#define GPP_D19 135 +#define GPP_D20 136 +#define GPP_D21 137 +#define GPP_D22 138 +#define GPP_D23 139 +#define GPIO_RSVD_12 140 +#define GPIO_RSVD_13 141 + +/* Group VGPIO */ +#define VGPIO_0 142 +#define VGPIO_3 143 +#define VGPIO_4 144 +#define VGPIO_5 145 +#define VGPIO_6 146 +#define VGPIO_7 147 +#define VGPIO_8 148 +#define VGPIO_9 149 +#define VGPIO_10 150 +#define VGPIO_11 151 +#define VGPIO_12 152 +#define VGPIO_13 153 +#define VGPIO_18 154 +#define VGPIO_19 155 +#define VGPIO_20 156 +#define VGPIO_21 157 +#define VGPIO_22 158 +#define VGPIO_23 159 +#define VGPIO_24 160 +#define VGPIO_25 161 +#define VGPIO_30 162 +#define VGPIO_31 163 +#define VGPIO_32 164 +#define VGPIO_33 165 +#define VGPIO_34 166 +#define VGPIO_35 167 +#define VGPIO_36 168 +#define VGPIO_37 169 +#define VGPIO_39 170 + +/* Group C */ +#define GPP_C0 171 +#define GPP_C1 172 +#define GPP_C2 173 +#define GPP_C3 174 +#define GPP_C4 175 +#define GPP_C5 176 +#define GPP_C6 177 +#define GPP_C7 178 +#define GPP_C8 179 +#define GPP_C9 180 +#define GPP_C10 181 +#define GPP_C11 182 +#define GPP_C12 183 +#define GPP_C13 184 +#define GPP_C14 185 +#define GPP_C15 186 +#define GPP_C16 187 +#define GPP_C17 188 +#define GPP_C18 189 +#define GPP_C19 190 +#define GPP_C20 191 +#define GPP_C21 192 +#define GPP_C22 193 +#define GPP_C23 194 + +#define GPIO_COM1_START GPP_H0 +#define GPIO_COM1_END GPP_C23 +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 195 +#define GPD1 196 +#define GPD2 197 +#define GPD3 198 +#define GPD4 199 +#define GPD5 200 +#define GPD6 201 +#define GPD7 202 +#define GPD8 203 +#define GPD9 204 +#define GPD10 205 +#define GPIO_RSVD_14 206 +#define GPIO_RSVD_15 207 +#define GPIO_RSVD_16 208 +#define GPIO_RSVD_17 209 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPIO_RSVD_17 +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group E */ +#define GPIO_RSVD_18 210 +#define GPIO_RSVD_19 211 +#define GPIO_RSVD_20 212 +#define GPIO_RSVD_21 213 +#define GPIO_RSVD_22 214 +#define GPIO_RSVD_23 215 +#define GPP_E0 216 +#define GPP_E1 217 +#define GPP_E2 218 +#define GPP_E3 219 +#define GPP_E4 220 +#define GPP_E5 221 +#define GPP_E6 222 +#define GPP_E7 223 +#define GPP_E8 224 +#define GPP_E9 225 +#define GPP_E10 226 +#define GPP_E11 227 +#define GPP_E12 228 +#define GPP_E13 229 +#define GPP_E14 230 +#define GPP_E15 231 +#define GPP_E16 232 +#define GPP_E17 233 +#define GPP_E18 234 +#define GPP_E19 235 +#define GPP_E20 236 +#define GPP_E21 237 +#define GPP_E22 238 +#define GPP_E23 239 +#define GPIO_RSVD_24 240 +#define GPIO_RSVD_25 241 +#define GPIO_RSVD_26 242 +#define GPIO_RSVD_27 243 +#define GPIO_RSVD_28 244 +#define GPIO_RSVD_29 245 +#define GPIO_RSVD_30 246 +#define GPIO_RSVD_31 247 +#define GPIO_RSVD_32 248 +#define GPIO_RSVD_33 249 +#define GPIO_RSVD_34 250 +#define GPIO_RSVD_35 251 +#define GPIO_RSVD_36 252 + +#define GPIO_COM4_START GPIO_RSVD_18 +#define GPIO_COM4_END GPIO_RSVD_36 +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group G */ +#define GPP_G0 253 +#define GPP_G1 254 +#define GPP_G2 255 +#define GPP_G3 256 +#define GPP_G4 257 +#define GPP_G5 258 +#define GPP_G6 259 +#define GPP_G7 260 + +#define GPIO_COM5_START GPP_G0 +#define GPIO_COM5_END GPP_G7 +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_PADS 261 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_4 3 +#define COMM_5 4 +#define TOTAL_GPIO_COMM 5 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h new file mode 100644 index 0000000000..750f589689 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h @@ -0,0 +1,395 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 +#define GPP_S 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_U 0x8 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC + +#define GPIO_MAX_NUM_PER_GROUP 27 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_A24 +#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +/* Group U */ +#define GPP_U0 120 +#define GPP_U1 121 +#define GPP_U2 122 +#define GPP_U3 123 +#define GPP_U4 124 +#define GPP_U5 125 +#define GPP_U6 126 +#define GPP_U7 127 +#define GPP_U8 128 +#define GPP_U9 129 +#define GPP_U10 130 +#define GPP_U11 131 +#define GPP_U12 132 +#define GPP_U13 133 +#define GPP_U14 134 +#define GPP_U15 135 +#define GPP_U16 136 +#define GPP_U17 137 +#define GPP_U18 138 +#define GPP_U19 139 +#define GPP_GSPI3_CLK_LOOPBK 140 +#define GPP_GSPI4_CLK_LOOPBK 141 +#define GPP_GSPI5_CLK_LOOPBK 142 +#define GPP_GSPI6_CLK_LOOPBK 143 + +/* Group VGPIO */ +#define CNV_BTEN 144 +#define CNV_BT_HOST_WAKEB 145 +#define CNV_BT_IF_SELECT 146 +#define vCNV_BT_UART_TXD 147 +#define vCNV_BT_UART_RXD 148 +#define vCNV_BT_UART_CTS_B 149 +#define vCNV_BT_UART_RTS_B 150 +#define vCNV_MFUART1_TXD 151 +#define vCNV_MFUART1_RXD 152 +#define vCNV_MFUART1_CTS_B 153 +#define vCNV_MFUART1_RTS_B 154 +#define vUART0_TXD 155 +#define vUART0_RXD 156 +#define vUART0_CTS_B 157 +#define vUART0_RTS_B 158 +#define vISH_UART0_TXD 159 +#define vISH_UART0_RXD 160 +#define vISH_UART0_CTS_B 161 +#define vISH_UART0_RTS_B 162 +#define vCNV_BT_I2S_BCLK 163 +#define vCNV_BT_I2S_WS_SYNC 164 +#define vCNV_BT_I2S_SDO 165 +#define vCNV_BT_I2S_SDI 166 +#define vI2S2_SCLK 167 +#define vI2S2_SFRM 168 +#define vI2S2_TXD 169 +#define vI2S2_RXD 170 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END vI2S2_RXD +#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) + +/* Group GPD */ +#define GPD0 171 +#define GPD1 172 +#define GPD2 173 +#define GPD3 174 +#define GPD4 175 +#define GPD5 176 +#define GPD6 177 +#define GPD7 178 +#define GPD8 179 +#define GPD9 180 +#define GPD10 181 +#define GPD11 182 +#define GPD_INPUT3VSEL 183 +#define GPD_SLP_LANB 184 +#define GPD__SLP_SUSB 185 +#define GPD_WAKEB 186 +#define GPD_DRAM_RESETB 187 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) + +/* Group C */ +#define GPP_C0 188 +#define GPP_C1 189 +#define GPP_C2 190 +#define GPP_C3 191 +#define GPP_C4 192 +#define GPP_C5 193 +#define GPP_C6 194 +#define GPP_C7 195 +#define GPP_C8 196 +#define GPP_C9 197 +#define GPP_C10 198 +#define GPP_C11 199 +#define GPP_C12 200 +#define GPP_C13 201 +#define GPP_C14 202 +#define GPP_C15 203 +#define GPP_C16 204 +#define GPP_C17 205 +#define GPP_C18 206 +#define GPP_C19 207 +#define GPP_C20 208 +#define GPP_C21 209 +#define GPP_C22 210 +#define GPP_C23 211 + +/* Group F */ +#define GPP_F0 212 +#define GPP_F1 213 +#define GPP_F2 214 +#define GPP_F3 215 +#define GPP_F4 216 +#define GPP_F5 217 +#define GPP_F6 218 +#define GPP_F7 219 +#define GPP_F8 220 +#define GPP_F9 221 +#define GPP_F10 222 +#define GPP_F11 223 +#define GPP_F12 224 +#define GPP_F13 225 +#define GPP_F14 226 +#define GPP_F15 227 +#define GPP_F16 228 +#define GPP_F17 229 +#define GPP_F18 230 +#define GPP_F19 231 +#define GPP_F20 232 +#define GPP_F21 233 +#define GPP_F22 234 +#define GPP_F23 235 +#define GPP_F_CLK_LOOPBK 236 + +/* Group HVCMOS */ +#define GPP_L_BKLTEN 237 +#define GPP_L_BKLTCTL 238 +#define GPP_L_VDDEN 239 +#define GPP_SYS_PWROK 240 +#define GPP_SYS_RESETB 241 +#define GPP_MLK_RSTB 242 + +/* Group E */ +#define GPP_E0 243 +#define GPP_E1 244 +#define GPP_E2 245 +#define GPP_E3 246 +#define GPP_E4 247 +#define GPP_E5 248 +#define GPP_E6 249 +#define GPP_E7 250 +#define GPP_E8 251 +#define GPP_E9 252 +#define GPP_E10 253 +#define GPP_E11 254 +#define GPP_E12 255 +#define GPP_E13 256 +#define GPP_E14 257 +#define GPP_E15 258 +#define GPP_E16 259 +#define GPP_E17 260 +#define GPP_E18 261 +#define GPP_E19 262 +#define GPP_E20 263 +#define GPP_E21 264 +#define GPP_E22 265 +#define GPP_E23 266 +#define GPP_E_CLK_LOOPBK 267 + +/* Group JTAG */ +#define GPP_JTAG_TDO 268 +#define GPP_JTAG_X 269 +#define GPP_JTAG_PRDYB 270 +#define GPP_JTAG_PREQB 271 +#define GPP_CPU_TRSTB 272 +#define GPP_JTAG_TDI 273 +#define GPP_JTAG_TMS 274 +#define GPP_JTAG_TCK 275 +#define GPP_DBG_PMODE 276 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_DBG_PMODE +#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) + +/* Group R */ +#define GPP_R0 277 +#define GPP_R1 278 +#define GPP_R2 279 +#define GPP_R3 280 +#define GPP_R4 281 +#define GPP_R5 282 +#define GPP_R6 283 +#define GPP_R7 284 + +/* Group SPI */ +#define GPP_SPI_IO_2 285 +#define GPP_SPI_IO_3 286 +#define GPP_SPI_MOSI_IO_0 287 +#define GPP_SPI_MOSI_IO_1 288 +#define GPP_SPI_TPM_CSB 289 +#define GPP_SPI_FLASH_0_CSB 290 +#define GPP_SPI_FLASH_1_CSB 291 +#define GPP_SPI_CLK 292 +#define GPP_CLK_LOOPBK 293 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_CLK_LOOPBK +#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS 294 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 513eeb90e6..53076e5885 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -115,18 +115,35 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#define PMC_GPP_B 0x0 -#define PMC_GPP_T 0x1 -#define PMC_GPP_A 0x2 -#define PMC_GPP_R 0x3 -#define PMC_GPD 0x4 -#define PMC_GPP_S 0x5 -#define PMC_GPP_H 0x6 -#define PMC_GPP_D 0x7 -#define PMC_GPP_U 0x8 -#define PMC_GPP_F 0xA -#define PMC_GPP_C 0xB -#define PMC_GPP_E 0xC +#if CONFIG(SOC_INTEL_TIGERLAKE) + + #define PMC_GPP_B 0x0 + #define PMC_GPP_T 0x1 + #define PMC_GPP_A 0x2 + #define PMC_GPP_R 0x3 + #define PMC_GPD 0x4 + #define PMC_GPP_S 0x5 + #define PMC_GPP_H 0x6 + #define PMC_GPP_D 0x7 + #define PMC_GPP_U 0x8 + #define PMC_GPP_F 0xA + #define PMC_GPP_C 0xB + #define PMC_GPP_E 0xC + +#elif CONFIG(SOC_INTEL_JASPERLAKE) + + #define PMC_GPP_A 0x0 + #define PMC_GPP_B 0x1 + #define PMC_GPP_F 0x2 + #define PMC_GPD 0x3 + #define PMC_GPP_R 0x4 + #define PMC_GPP_S 0x6 + #define PMC_GPP_D 0x7 + #define PMC_GPP_C 0x8 + #define PMC_GPP_H 0xA + #define PMC_GPP_E 0xF + +#endif #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) From 73704533d6b0f92914408b7b4a0e4272edc318c5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 16:00:06 +0100 Subject: [PATCH 0223/1463] LGA1155 mainboards: Remove gfx.did and gfx.ndid They are downright useless and result in ACPI errors. So, burn them. Also, do a minor update to autoport's README about these values. Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Patrick Rudolph --- src/mainboard/asrock/b75pro3-m/devicetree.cb | 2 -- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 2 -- src/mainboard/asus/p8z77-m_pro/devicetree.cb | 2 -- src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 3 --- .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb | 2 -- .../gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb | 2 -- src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb | 2 -- src/mainboard/hp/z220_sff_workstation/devicetree.cb | 2 -- src/mainboard/msi/ms7707/devicetree.cb | 2 -- src/mainboard/sapphire/pureplatinumh61/devicetree.cb | 2 -- util/autoport/readme.md | 2 +- 11 files changed, 1 insertion(+), 22 deletions(-) diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 32438a102f..3fa3dec24e 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -15,9 +15,7 @@ # chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "4" diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index ee9a0fc45c..ea643696ee 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb index 0bec95c908..cbc1629c80 100644 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index e581470daa..fbc31b7788 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -1,7 +1,4 @@ chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" device cpu_cluster 0 on chip cpu/intel/model_206ax diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb index e4ec810d45..317d79744c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb index 22d483e12a..a11ba0e84e 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb @@ -14,8 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 915f87d450..d8790a81d0 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -15,9 +15,7 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 6823c9fd1f..a0eed14c54 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -15,9 +15,7 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 9753c3296b..f520ea49e7 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -1,7 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "0" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 468c35a157..9a42a7b453 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -15,8 +15,6 @@ # chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.ndid" = "3" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 9af08f40bc..bfaaef6f4e 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -342,7 +342,7 @@ on laptops (desktops have no "lid"!) but it makes sense to proofread it. ## `gfx.ndid` and `gfx.did` Those describe which video outputs are declared in ACPI tables. -Normally, there is no need to adjust these values, but if you miss some +Normally, there is no need to have these values, but if you miss some non-standard video output, you can declare it there. Bit 31 is set to indicate the presence of the output. Byte 1 is the type and byte 0 is used for disambigution so that ID composed of byte 1 and 0 is unique. From bd6bdc5c1dce962188247e2e7abbd8292a76eb51 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 25 Dec 2018 21:54:52 -0600 Subject: [PATCH 0224/1463] soc/baytrail: hook up smmstore Adapted from implementation in sb/intel/common. Test: build/boot variants of google/rambi with Tianocore and SMMSTORE enabled Change-Id: Id8adeda982feba1cbcf5e04cf0bef0a6710ad4f0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39190 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/baytrail/smihandler.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 3a096e3d80..b8226c29dd 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -282,6 +283,26 @@ static void soc_legacy(void) LPSS_ACPI_MODE_DISABLE(SPI); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -334,6 +355,10 @@ static void southbridge_smi_apmc(void) case APM_CNT_LEGACY: soc_legacy(); break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); From aa3b5e29f2a6f15034f4a195c5871b4189350ddc Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 25 Dec 2018 22:10:48 -0600 Subject: [PATCH 0225/1463] soc/braswell: hook up smmstore Adapted from implementation in sb/intel/common. Test: build/boot variants of google/cyan with Tianocore and SMMSTORE enabled Change-Id: Ife4681983d0eecbc01c539b477664f3dd8bb9368 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39191 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/braswell/smihandler.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 80b142aad8..31b059c545 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -30,6 +30,7 @@ #include #include #include +#include /* GNVS needs to be set by coreboot initiating a software SMI. */ static global_nvs_t *gnvs; @@ -279,6 +280,26 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -330,6 +351,10 @@ static void southbridge_smi_apmc(void) if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); From 3a7a3390f5e98ed62ce912072438d04582407b46 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 25 Dec 2018 22:22:47 -0600 Subject: [PATCH 0226/1463] soc/broadwell: hook up smmstore Adapted from implementation in sb/intel/common. Test: build/boot variants of google/{jecht, auron} with Tianocore and SMMSTORE enabled Change-Id: I4d2aaa80dad229a6c7b947d0edf8fb1174050ad0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39192 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/broadwell/smihandler.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 5b04f799a3..2c388870a0 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -35,6 +35,7 @@ #include #include #include +#include static u8 smm_initialized = 0; @@ -311,6 +312,26 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t101_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { u8 reg8; @@ -352,6 +373,10 @@ static void southbridge_smi_apmc(void) if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); From dc1596c8c8246b22dfb77a7214745782bab02d9e Mon Sep 17 00:00:00 2001 From: Marcello Sylvester Bauer Date: Tue, 11 Feb 2020 13:31:38 +0100 Subject: [PATCH 0227/1463] util/ifdtool: add --output flag Add an optional commandline flag to define the filename of the resulting output file. If this flag is not defined, it will behave like before by using the old filename with a ".new" suffix. With this additional flag it is not necessary to move the output file at build-time, and the stdout print "Writing new image to " makes more sense in the build context. Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2 Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/38828 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- util/ifdtool/ifdtool.c | 52 ++++++++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 84a8ead9f1..97b9cd1fe8 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -854,17 +854,11 @@ static void validate_layout(char *image, int size) static void write_image(const char *filename, char *image, int size) { - char new_filename[FILENAME_MAX]; // allow long file names int new_fd; - - // - 5: leave room for ".new\0" - strncpy(new_filename, filename, FILENAME_MAX - 5); - strncat(new_filename, ".new", FILENAME_MAX - strlen(filename)); - - printf("Writing new image to %s\n", new_filename); + printf("Writing new image to %s\n", filename); // Now write out new image - new_fd = open(new_filename, + new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC | O_BINARY, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); if (new_fd < 0) { @@ -1429,6 +1423,7 @@ static void print_usage(const char *name) " -x | --extract: extract intel fd modules\n" " -i | --inject : inject file into region \n" " -n | --newlayout update regions using a flashrom layout file\n" + " -O | --output output filename\n" " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" " -D | --density <512|1|2|4|8|16|32|64> set chip density (512 in KByte, others in MByte)\n" " -C | --chip <0|1|2> select spi chip on which to operate\n" @@ -1460,6 +1455,7 @@ int main(int argc, char *argv[]) int mode_altmedisable = 0, altmedisable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; + char *new_filename = NULL; int region_type = -1, inputfreq = 0; unsigned int new_density = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; @@ -1470,6 +1466,7 @@ int main(int argc, char *argv[]) {"extract", 0, NULL, 'x'}, {"inject", 1, NULL, 'i'}, {"newlayout", 1, NULL, 'n'}, + {"output", 1, NULL, 'O'}, {"spifreq", 1, NULL, 's'}, {"density", 1, NULL, 'D'}, {"chip", 1, NULL, 'C'}, @@ -1484,7 +1481,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:s:p:eluvth?", + while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:O:s:p:eluvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1543,6 +1540,14 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } break; + case 'O': + new_filename = strdup(optarg); + if (!new_filename) { + fprintf(stderr, "No output filename specified\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + break; case 'D': mode_density = 1; new_density = strtoul(optarg, NULL, 0); @@ -1731,6 +1736,18 @@ int main(int argc, char *argv[]) close(bios_fd); + // generate new filename + if (new_filename == NULL) { + new_filename = (char *) malloc((strlen(filename) + 5) * sizeof(char)); + if (!new_filename) { + printf("Out of memory.\n"); + exit(EXIT_FAILURE); + } + // - 5: leave room for ".new\0" + strcpy(new_filename, filename); + strcat(new_filename, ".new"); + } + check_ifd_version(image, size); if (mode_dump) @@ -1746,34 +1763,35 @@ int main(int argc, char *argv[]) validate_layout(image, size); if (mode_inject) - inject_region(filename, image, size, region_type, + inject_region(new_filename, image, size, region_type, region_fname); if (mode_newlayout) - new_layout(filename, image, size, layout_fname); + new_layout(new_filename, image, size, layout_fname); if (mode_spifreq) - set_spi_frequency(filename, image, size, spifreq); + set_spi_frequency(new_filename, image, size, spifreq); if (mode_density) - set_chipdensity(filename, image, size, new_density); + set_chipdensity(new_filename, image, size, new_density); if (mode_em100) - set_em100_mode(filename, image, size); + set_em100_mode(new_filename, image, size); if (mode_locked) - lock_descriptor(filename, image, size); + lock_descriptor(new_filename, image, size); if (mode_unlocked) - unlock_descriptor(filename, image, size); + unlock_descriptor(new_filename, image, size); if (mode_altmedisable) { fpsba_t *fpsba = find_fpsba(image, size); fmsba_t *fmsba = find_fmsba(image, size); fpsba_set_altmedisable(fpsba, fmsba, altmedisable); - write_image(filename, image, size); + write_image(new_filename, image, size); } + free(new_filename); free(image); return 0; From 3e576739c9d998a679b95c878838f58a491f5fb0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 13:28:36 +0100 Subject: [PATCH 0228/1463] mb/Kconfig: Align ROM size options Change-Id: I0160e72a8961f1aa34982f6348825708e7be9c40 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39180 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/Kconfig | 70 +++++++++++++++++++++---------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index df80e646bb..95459ffd8e 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -44,16 +44,16 @@ config BOARD_ROMSIZE_KB_65536 # TODO: No help text possible for choice fields? choice prompt "ROM chip size" - default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 - default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 - default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 - default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 - default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 - default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 - default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 - default COREBOOT_ROMSIZE_KB_5120 if BOARD_ROMSIZE_KB_5120 - default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 - default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 + default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 + default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 + default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 + default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 + default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 + default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_5120 if BOARD_ROMSIZE_KB_5120 + default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 + default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 @@ -145,16 +145,16 @@ endchoice # Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int - default 64 if COREBOOT_ROMSIZE_KB_64 - default 128 if COREBOOT_ROMSIZE_KB_128 - default 256 if COREBOOT_ROMSIZE_KB_256 - default 512 if COREBOOT_ROMSIZE_KB_512 - default 1024 if COREBOOT_ROMSIZE_KB_1024 - default 2048 if COREBOOT_ROMSIZE_KB_2048 - default 4096 if COREBOOT_ROMSIZE_KB_4096 - default 5120 if COREBOOT_ROMSIZE_KB_5120 - default 6144 if COREBOOT_ROMSIZE_KB_6144 - default 8192 if COREBOOT_ROMSIZE_KB_8192 + default 64 if COREBOOT_ROMSIZE_KB_64 + default 128 if COREBOOT_ROMSIZE_KB_128 + default 256 if COREBOOT_ROMSIZE_KB_256 + default 512 if COREBOOT_ROMSIZE_KB_512 + default 1024 if COREBOOT_ROMSIZE_KB_1024 + default 2048 if COREBOOT_ROMSIZE_KB_2048 + default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 5120 if COREBOOT_ROMSIZE_KB_5120 + default 6144 if COREBOOT_ROMSIZE_KB_6144 + default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 @@ -164,21 +164,21 @@ config COREBOOT_ROMSIZE_KB # Map the config names to a hex value (bytes). config ROM_SIZE hex - default 0x10000 if COREBOOT_ROMSIZE_KB_64 - default 0x20000 if COREBOOT_ROMSIZE_KB_128 - default 0x40000 if COREBOOT_ROMSIZE_KB_256 - default 0x80000 if COREBOOT_ROMSIZE_KB_512 - default 0x100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x500000 if COREBOOT_ROMSIZE_KB_5120 - default 0x600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x800000 if COREBOOT_ROMSIZE_KB_8192 - default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 - default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x4000000 if COREBOOT_ROMSIZE_KB_65536 + default 0x00010000 if COREBOOT_ROMSIZE_KB_64 + default 0x00020000 if COREBOOT_ROMSIZE_KB_128 + default 0x00040000 if COREBOOT_ROMSIZE_KB_256 + default 0x00080000 if COREBOOT_ROMSIZE_KB_512 + default 0x00100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x00200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x00400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x00500000 if COREBOOT_ROMSIZE_KB_5120 + default 0x00600000 if COREBOOT_ROMSIZE_KB_6144 + default 0x00800000 if COREBOOT_ROMSIZE_KB_8192 + default 0x00a00000 if COREBOOT_ROMSIZE_KB_10240 + default 0x00c00000 if COREBOOT_ROMSIZE_KB_12288 + default 0x01000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x02000000 if COREBOOT_ROMSIZE_KB_32768 + default 0x04000000 if COREBOOT_ROMSIZE_KB_65536 config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL From 7671bce33bf85d7b04afc6f6698ad41f11923213 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 13:07:19 +0100 Subject: [PATCH 0229/1463] mb/*/Kconfig: Factor out MAINBOARD_VENDOR Only some mainboard vendors have a prompt for this option. Let's be fair and give this ability to everyone. Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/Kconfig | 3 +++ src/mainboard/adlink/Kconfig | 1 - src/mainboard/amd/Kconfig | 1 - src/mainboard/aopen/Kconfig | 1 - src/mainboard/apple/Kconfig | 1 - src/mainboard/asrock/Kconfig | 2 +- src/mainboard/asus/Kconfig | 2 +- src/mainboard/bap/Kconfig | 1 - src/mainboard/biostar/Kconfig | 2 +- src/mainboard/cavium/Kconfig | 2 +- src/mainboard/compulab/Kconfig | 1 - src/mainboard/elmex/Kconfig | 1 - src/mainboard/emulation/Kconfig | 1 - src/mainboard/facebook/Kconfig | 1 - src/mainboard/foxconn/Kconfig | 2 +- src/mainboard/getac/Kconfig | 2 +- src/mainboard/gigabyte/Kconfig | 2 +- src/mainboard/gizmosphere/Kconfig | 1 - src/mainboard/google/Kconfig | 2 +- src/mainboard/hp/Kconfig | 1 - src/mainboard/ibase/Kconfig | 1 - src/mainboard/intel/Kconfig | 1 - src/mainboard/jetway/Kconfig | 1 - src/mainboard/kontron/Kconfig | 1 - src/mainboard/lenovo/Kconfig | 1 - src/mainboard/lippert/Kconfig | 1 - src/mainboard/msi/Kconfig | 2 +- src/mainboard/opencellular/Kconfig | 2 +- src/mainboard/packardbell/Kconfig | 1 - src/mainboard/pcengines/Kconfig | 1 - src/mainboard/portwell/Kconfig | 1 - src/mainboard/purism/Kconfig | 1 - src/mainboard/razer/Kconfig | 2 -- src/mainboard/roda/Kconfig | 1 - src/mainboard/samsung/Kconfig | 1 - src/mainboard/sapphire/Kconfig | 1 - src/mainboard/scaleway/Kconfig | 1 - src/mainboard/siemens/Kconfig | 1 - src/mainboard/sifive/Kconfig | 1 - src/mainboard/supermicro/Kconfig | 1 - src/mainboard/system76/Kconfig | 1 - src/mainboard/ti/Kconfig | 1 - src/mainboard/up/Kconfig | 1 - 43 files changed, 13 insertions(+), 43 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 95459ffd8e..77fcba16e6 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -10,6 +10,9 @@ endchoice source "src/mainboard/*/Kconfig" +config MAINBOARD_VENDOR + string "Mainboard vendor name" + config BOARD_ROMSIZE_KB_64 bool config BOARD_ROMSIZE_KB_128 diff --git a/src/mainboard/adlink/Kconfig b/src/mainboard/adlink/Kconfig index f71d6a98e4..5890a29c34 100644 --- a/src/mainboard/adlink/Kconfig +++ b/src/mainboard/adlink/Kconfig @@ -4,7 +4,6 @@ comment "see under vendor LiPPERT" # any further boards will then be ADLINK config MAINBOARD_VENDOR - string default "ADLINK" endif # VENDOR_ADLINK diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index 664ebe103e..2e40199e43 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/amd/*/Kconfig" config MAINBOARD_VENDOR - string default "AMD" endif # VENDOR_AMD diff --git a/src/mainboard/aopen/Kconfig b/src/mainboard/aopen/Kconfig index 2208e62ec0..754bab0a50 100644 --- a/src/mainboard/aopen/Kconfig +++ b/src/mainboard/aopen/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/aopen/*/Kconfig" config MAINBOARD_VENDOR - string default "AOpen" endif # VENDOR_AOPEN diff --git a/src/mainboard/apple/Kconfig b/src/mainboard/apple/Kconfig index 0f5e96434b..4801833722 100644 --- a/src/mainboard/apple/Kconfig +++ b/src/mainboard/apple/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/apple/*/Kconfig" config MAINBOARD_VENDOR - string default "Apple" endif # VENDOR_APPLE diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig index 7c4b012e96..f47e3e5dcd 100644 --- a/src/mainboard/asrock/Kconfig +++ b/src/mainboard/asrock/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_ASROCK choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/asrock/*/Kconfig" config MAINBOARD_VENDOR - string default "ASROCK" endif # VENDOR_ASROCK diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 4c0215fba4..f910588a2f 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_ASUS choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/asus/*/Kconfig" config MAINBOARD_VENDOR - string default "ASUS" endif # VENDOR_ASUS diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig index a638509026..c21cf85269 100644 --- a/src/mainboard/bap/Kconfig +++ b/src/mainboard/bap/Kconfig @@ -29,7 +29,6 @@ endchoice source "src/mainboard/bap/*/Kconfig" config MAINBOARD_VENDOR - string default "BAP" endif # VENDOR_BAP diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 43896a3f1f..0f28af33c2 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -13,6 +13,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_BIOSTAR choice @@ -26,7 +27,6 @@ source "src/mainboard/biostar/*/Kconfig" config MAINBOARD_VENDOR - string default "Biostar" endif # VENDOR_BIOSTAR diff --git a/src/mainboard/cavium/Kconfig b/src/mainboard/cavium/Kconfig index ec0a791119..ac16393c7f 100644 --- a/src/mainboard/cavium/Kconfig +++ b/src/mainboard/cavium/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_CAVIUM choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/cavium/*/Kconfig" config MAINBOARD_VENDOR - string "Mainboard Vendor" default "Cavium" endif # VENDOR_CAVIUM diff --git a/src/mainboard/compulab/Kconfig b/src/mainboard/compulab/Kconfig index 813026c7ed..9501be7f2b 100644 --- a/src/mainboard/compulab/Kconfig +++ b/src/mainboard/compulab/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/compulab/*/Kconfig" config MAINBOARD_VENDOR - string default "CompuLab" endif # VENDOR_COMPULAB diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig index 54217ea217..28f264dd13 100644 --- a/src/mainboard/elmex/Kconfig +++ b/src/mainboard/elmex/Kconfig @@ -13,7 +13,6 @@ endchoice source "src/mainboard/elmex/*/Kconfig" config MAINBOARD_VENDOR - string default "ELMEX" endif # VENDOR_ELMEX diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 759b1de091..60aa99477a 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -16,7 +16,6 @@ config BOARD_EMULATION_QEMU_X86 source "src/mainboard/emulation/*/Kconfig" config MAINBOARD_VENDOR - string default "Emulation" endif # VENDOR_EMULATION diff --git a/src/mainboard/facebook/Kconfig b/src/mainboard/facebook/Kconfig index 7e99f01ac7..17366e96bf 100644 --- a/src/mainboard/facebook/Kconfig +++ b/src/mainboard/facebook/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/facebook/*/Kconfig" config MAINBOARD_VENDOR - string default "Facebook" endif # VENDOR_FACEBOOK diff --git a/src/mainboard/foxconn/Kconfig b/src/mainboard/foxconn/Kconfig index 056805ccbf..30994f0e6b 100644 --- a/src/mainboard/foxconn/Kconfig +++ b/src/mainboard/foxconn/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_FOXCONN choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/foxconn/*/Kconfig" config MAINBOARD_VENDOR - string default "Foxconn" endif # VENDOR_FOXCONN diff --git a/src/mainboard/getac/Kconfig b/src/mainboard/getac/Kconfig index c3a78be6d2..2d597b5832 100644 --- a/src/mainboard/getac/Kconfig +++ b/src/mainboard/getac/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_GETAC choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/getac/*/Kconfig" config MAINBOARD_VENDOR - string default "Getac" endif # VENDOR_GETAC diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index 3edf78bb01..dcb57c6b12 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_GIGABYTE choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/gigabyte/*/Kconfig" config MAINBOARD_VENDOR - string default "GIGABYTE" endif # VENDOR_GIGABYTE diff --git a/src/mainboard/gizmosphere/Kconfig b/src/mainboard/gizmosphere/Kconfig index 6022bf698b..d2b335a23a 100644 --- a/src/mainboard/gizmosphere/Kconfig +++ b/src/mainboard/gizmosphere/Kconfig @@ -25,7 +25,6 @@ endchoice source "src/mainboard/gizmosphere/*/Kconfig" config MAINBOARD_VENDOR - string default "GizmoSphere" endif # VENDOR_GIZMOSPHERE diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 6a2540d75d..702ba13c55 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_GOOGLE choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/google/*/Kconfig" config MAINBOARD_VENDOR - string "Mainboard Vendor" default "Google" endif # VENDOR_GOOGLE diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig index 9d768ae647..73e6649d43 100644 --- a/src/mainboard/hp/Kconfig +++ b/src/mainboard/hp/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/hp/*/Kconfig" config MAINBOARD_VENDOR - string default "HP" endif # VENDOR_HP diff --git a/src/mainboard/ibase/Kconfig b/src/mainboard/ibase/Kconfig index 2c33d58caa..5b519b7f50 100644 --- a/src/mainboard/ibase/Kconfig +++ b/src/mainboard/ibase/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/ibase/*/Kconfig" config MAINBOARD_VENDOR - string default "iBase" endif # VENDOR_IBASE diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 9f5e5af9c2..53c5cd168b 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/intel/*/Kconfig" config MAINBOARD_VENDOR - string default "Intel" endif # VENDOR_INTEL diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig index 530700d816..36a064c2e0 100644 --- a/src/mainboard/jetway/Kconfig +++ b/src/mainboard/jetway/Kconfig @@ -13,7 +13,6 @@ endchoice source "src/mainboard/jetway/*/Kconfig" config MAINBOARD_VENDOR - string default "Jetway" endif # VENDOR_JETWAY diff --git a/src/mainboard/kontron/Kconfig b/src/mainboard/kontron/Kconfig index 82d1c4fe30..34af38de5d 100644 --- a/src/mainboard/kontron/Kconfig +++ b/src/mainboard/kontron/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/kontron/*/Kconfig" config MAINBOARD_VENDOR - string default "Kontron" endif # VENDOR_KONTRON diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index ea1ead13e0..467c20abc8 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/lenovo/*/Kconfig" config MAINBOARD_VENDOR - string default "LENOVO" config MAINBOARD_FAMILY diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index e45fc3e6a2..f5213b6e72 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -15,7 +15,6 @@ endchoice source "src/mainboard/lippert/*/Kconfig" config MAINBOARD_VENDOR - string default "LiPPERT" endif # VENDOR_LIPPERT diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig index 0b9228a41f..bd5ab69cd9 100644 --- a/src/mainboard/msi/Kconfig +++ b/src/mainboard/msi/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_MSI choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/msi/*/Kconfig" config MAINBOARD_VENDOR - string default "MSI" endif # VENDOR_MSI diff --git a/src/mainboard/opencellular/Kconfig b/src/mainboard/opencellular/Kconfig index 2df6ba3afe..f82e923829 100644 --- a/src/mainboard/opencellular/Kconfig +++ b/src/mainboard/opencellular/Kconfig @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_OPENCELLULAR choice @@ -24,7 +25,6 @@ endchoice source "src/mainboard/opencellular/*/Kconfig" config MAINBOARD_VENDOR - string default "OpenCellular" endif # VENDOR_OPENCELLULAR diff --git a/src/mainboard/packardbell/Kconfig b/src/mainboard/packardbell/Kconfig index 7fe8d24a88..9d898922a7 100644 --- a/src/mainboard/packardbell/Kconfig +++ b/src/mainboard/packardbell/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/packardbell/*/Kconfig" config MAINBOARD_VENDOR - string default "Packard Bell" endif # VENDOR_PACKARDBELL diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index e173054c07..b4d8a9a7c8 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/pcengines/*/Kconfig" config MAINBOARD_VENDOR - string default "PC Engines" endif # VENDOR_PCENGINES diff --git a/src/mainboard/portwell/Kconfig b/src/mainboard/portwell/Kconfig index 78e5037c30..17912842c7 100644 --- a/src/mainboard/portwell/Kconfig +++ b/src/mainboard/portwell/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/portwell/*/Kconfig" config MAINBOARD_VENDOR - string default "Portwell" endif # VENDOR_PORTWELL diff --git a/src/mainboard/purism/Kconfig b/src/mainboard/purism/Kconfig index ff6eb414e8..a3022d4591 100644 --- a/src/mainboard/purism/Kconfig +++ b/src/mainboard/purism/Kconfig @@ -25,7 +25,6 @@ endchoice source "src/mainboard/purism/*/Kconfig" config MAINBOARD_VENDOR - string "Mainboard Vendor" default "Purism" endif # VENDOR_PURISM diff --git a/src/mainboard/razer/Kconfig b/src/mainboard/razer/Kconfig index bae422eaaa..9d96888c7f 100644 --- a/src/mainboard/razer/Kconfig +++ b/src/mainboard/razer/Kconfig @@ -1,4 +1,3 @@ - if VENDOR_RAZER choice @@ -11,7 +10,6 @@ endchoice source "src/mainboard/razer/*/Kconfig" config MAINBOARD_VENDOR - string "Mainboard Vendor" default "RAZER" endif diff --git a/src/mainboard/roda/Kconfig b/src/mainboard/roda/Kconfig index 8a0107ab04..bc8ebc0af3 100644 --- a/src/mainboard/roda/Kconfig +++ b/src/mainboard/roda/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/roda/*/Kconfig" config MAINBOARD_VENDOR - string default "Roda" endif # VENDOR_RODA diff --git a/src/mainboard/samsung/Kconfig b/src/mainboard/samsung/Kconfig index 06e22d991b..119b63744b 100644 --- a/src/mainboard/samsung/Kconfig +++ b/src/mainboard/samsung/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/samsung/*/Kconfig" config MAINBOARD_VENDOR - string default "SAMSUNG" endif # VENDOR_SAMSUNG diff --git a/src/mainboard/sapphire/Kconfig b/src/mainboard/sapphire/Kconfig index 130c1f4f22..5bb6a5ca4c 100644 --- a/src/mainboard/sapphire/Kconfig +++ b/src/mainboard/sapphire/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/sapphire/*/Kconfig" config MAINBOARD_VENDOR - string default "Sapphire" endif # VENDOR_SAPPHIRE diff --git a/src/mainboard/scaleway/Kconfig b/src/mainboard/scaleway/Kconfig index 2af3e29c36..4635376d1e 100644 --- a/src/mainboard/scaleway/Kconfig +++ b/src/mainboard/scaleway/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/scaleway/*/Kconfig" config MAINBOARD_VENDOR - string default "Scaleway" endif # VENDOR_SCALEWAY diff --git a/src/mainboard/siemens/Kconfig b/src/mainboard/siemens/Kconfig index 9b7c597db3..203b3d01bb 100644 --- a/src/mainboard/siemens/Kconfig +++ b/src/mainboard/siemens/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/siemens/*/Kconfig" config MAINBOARD_VENDOR - string default "Siemens" endif # VENDOR_SIEMENS diff --git a/src/mainboard/sifive/Kconfig b/src/mainboard/sifive/Kconfig index 1527705df1..5731b3eda4 100644 --- a/src/mainboard/sifive/Kconfig +++ b/src/mainboard/sifive/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/sifive/*/Kconfig" config MAINBOARD_VENDOR - string default "SiFive" endif # VENDOR_SIFIVE diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index 2ee9372fc2..b06d20b7d8 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/supermicro/*/Kconfig" config MAINBOARD_VENDOR - string default "Supermicro" endif # VENDOR_SUPERMICRO diff --git a/src/mainboard/system76/Kconfig b/src/mainboard/system76/Kconfig index 62034a4222..785d117ad5 100644 --- a/src/mainboard/system76/Kconfig +++ b/src/mainboard/system76/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/system76/*/Kconfig" config MAINBOARD_VENDOR - string default "System76" endif diff --git a/src/mainboard/ti/Kconfig b/src/mainboard/ti/Kconfig index 05b283b9f3..46a3746d65 100644 --- a/src/mainboard/ti/Kconfig +++ b/src/mainboard/ti/Kconfig @@ -26,7 +26,6 @@ endchoice source "src/mainboard/ti/*/Kconfig" config MAINBOARD_VENDOR - string default "TI" endif # VENDOR_TI diff --git a/src/mainboard/up/Kconfig b/src/mainboard/up/Kconfig index 04e290c0ae..aa8eda66b5 100644 --- a/src/mainboard/up/Kconfig +++ b/src/mainboard/up/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/up/*/Kconfig" config MAINBOARD_VENDOR - string default "UP" endif From 632e2414687f2c58025c27f2d0dac0eba8205fda Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 14:08:11 +0100 Subject: [PATCH 0230/1463] mb/emulation/Kconfig: Redefine BOARD_EMULATION_QEMU_X86 Use CPU_QEMU_X86 as it is selected by both Qemu x86 mainboards. Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39181 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/mainboard/emulation/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 60aa99477a..e069cf0faa 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -11,7 +11,7 @@ endchoice config BOARD_EMULATION_QEMU_X86 bool default y - depends on BOARD_EMULATION_QEMU_X86_I440FX || BOARD_EMULATION_QEMU_X86_Q35 + depends on CPU_QEMU_X86 source "src/mainboard/emulation/*/Kconfig" From d615230cced8238029d579411d8ee69f68c7ec5f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 14:46:38 +0100 Subject: [PATCH 0231/1463] treewide: Replace BOARD_EMULATION_QEMU_X86 It is equivalent to the CPU_QEMU_X86 symbol. Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39182 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/console/Kconfig | 2 +- src/device/pci_rom.c | 2 +- src/drivers/emulation/qemu/Kconfig | 2 +- src/mainboard/emulation/Kconfig | 5 ----- 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index cc18ec3756..b893698a20 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -280,7 +280,7 @@ config CONSOLE_SPI_FLASH_BUFFER_SIZE config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" - depends on BOARD_EMULATION_QEMU_X86 + depends on CPU_QEMU_X86 default y help Send coreboot debug output to QEMU's isa-debugcon device: diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 3676f9cf9b..816255d5e1 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -59,7 +59,7 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if CONFIG(BOARD_EMULATION_QEMU_X86) +#if CONFIG(CPU_QEMU_X86) if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) rom_address = 0xc0000; else diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 58daaa4487..c271825f23 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_EMULATION_QEMU_BOCHS bool "bochs dispi interface vga driver" default y - depends on BOARD_EMULATION_QEMU_X86 + depends on CPU_QEMU_X86 depends on MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index e069cf0faa..45790b1842 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -8,11 +8,6 @@ source "src/mainboard/emulation/*/Kconfig.name" endchoice -config BOARD_EMULATION_QEMU_X86 - bool - default y - depends on CPU_QEMU_X86 - source "src/mainboard/emulation/*/Kconfig" config MAINBOARD_VENDOR From b3fa6a03a895ee43e9679d5c6608e98d1eec6e67 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 27 Feb 2020 15:54:56 -0800 Subject: [PATCH 0232/1463] soc/intel/tigerlake: configure ethernet Configure ethernet based on board config BUG=none BRANCH=none TEST= build TGLRVP and check ethernet is disabled based on devicetree Signed-off-by: Wonkyu Kim Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params_tgl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde021c..fbc9f23083 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* LAN */ + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; From af681b62a045d0c60b7cd6a3a8199eccb5d7c6ae Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 2 Mar 2020 12:20:49 +0800 Subject: [PATCH 0233/1463] mb/google/drallion: Enable cbfs SAR value Enable read SAR value from cbfs. BUG=b:150347463 TEST=NA Signed-off-by: Eric Lai Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194 Tested-by: build bot (Jenkins) Reviewed-by: Ivy Jian --- src/mainboard/google/drallion/Kconfig | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 61bae2b03d..aff19c819c 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -22,9 +22,6 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION - select USE_SAR - select SAR_ENABLE - select DSAR_ENABLE if BOARD_GOOGLE_BASEBOARD_DRALLION @@ -36,6 +33,14 @@ config CHROMEOS select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + select WIFI_SAR_CBFS + config DIMM_MAX int default 2 From 9a768be0a50a110c23373684bab50c3550813647 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Sat, 29 Feb 2020 00:01:16 -0800 Subject: [PATCH 0234/1463] vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake Update FSPM header to add Vtd related Upds for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39168 Tested-by: build bot (Jenkins) Reviewed-by: caveh jalali Reviewed-by: Wonkyu Kim --- .../intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 107 +++++++++++------- 1 file changed, 68 insertions(+), 39 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index e81131db85..9bc1a409c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -269,7 +269,12 @@ typedef struct { /** Offset 0x015C - Reserved **/ - UINT8 Reserved4[40]; + UINT8 Reserved4[4]; + +/** Offset 0x0160 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; /** Offset 0x0184 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) @@ -277,9 +282,33 @@ typedef struct { **/ UINT8 VtdDisable; -/** Offset 0x0185 - Reserved +/** Offset 0x0185 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS **/ - UINT8 Reserved5[4]; + UINT8 VtdIgdEnable; + +/** Offset 0x0186 - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x0187 - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x0188 - Vtd Programming for ITbt + 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdItbtEnable; /** Offset 0x0189 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -297,7 +326,7 @@ typedef struct { /** Offset 0x018B - Reserved **/ - UINT8 Reserved6; + UINT8 Reserved5; /** Offset 0x018C - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -308,7 +337,7 @@ typedef struct { /** Offset 0x018D - Reserved **/ - UINT8 Reserved7[3]; + UINT8 Reserved6[3]; /** Offset 0x0190 - SA GV System Agent dynamic frequency support and when enabled memory will be training @@ -319,7 +348,7 @@ typedef struct { /** Offset 0x0191 - Reserved **/ - UINT8 Reserved8[2]; + UINT8 Reserved7[2]; /** Offset 0x0193 - Rank Margin Tool Enable/disable Rank Margin Tool. @@ -329,7 +358,7 @@ typedef struct { /** Offset 0x0194 - Reserved **/ - UINT8 Reserved9[10]; + UINT8 Reserved8[10]; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -339,7 +368,7 @@ typedef struct { /** Offset 0x019F - Reserved **/ - UINT8 Reserved10[22]; + UINT8 Reserved9[22]; /** Offset 0x01B5 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -355,17 +384,17 @@ typedef struct { /** Offset 0x01B7 - Reserved **/ - UINT8 Reserved11[166]; + UINT8 Reserved10[166]; /** Offset 0x025D - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;1: Enable. $EN_DIS **/ - UINT8 ImguClkOutEn[5]; + UINT8 ImguClkOutEn[6]; -/** Offset 0x0262 - Reserved +/** Offset 0x0263 - Reserved **/ - UINT8 Reserved12[7]; + UINT8 Reserved11[6]; /** Offset 0x0269 - RpClockReqMsgEnable **/ @@ -377,7 +406,7 @@ typedef struct { /** Offset 0x026E - Reserved **/ - UINT8 Reserved13[3]; + UINT8 Reserved12[3]; /** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -477,7 +506,7 @@ typedef struct { /** Offset 0x0281 - Reserved **/ - UINT8 Reserved14[126]; + UINT8 Reserved13[126]; /** Offset 0x02FF - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -486,7 +515,7 @@ typedef struct { /** Offset 0x0307 - Reserved **/ - UINT8 Reserved15[22]; + UINT8 Reserved14[22]; /** Offset 0x031D - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM @@ -498,7 +527,7 @@ typedef struct { /** Offset 0x031E - Reserved **/ - UINT8 Reserved16[5]; + UINT8 Reserved15[5]; /** Offset 0x0323 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable @@ -508,7 +537,7 @@ typedef struct { /** Offset 0x0324 - Reserved **/ - UINT8 Reserved17; + UINT8 Reserved16; /** Offset 0x0325 - CPU ratio value CPU ratio value. Valid Range 0 to 63 @@ -517,7 +546,7 @@ typedef struct { /** Offset 0x0326 - Reserved **/ - UINT8 Reserved18[2]; + UINT8 Reserved17[2]; /** Offset 0x0328 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- @@ -528,7 +557,7 @@ typedef struct { /** Offset 0x0329 - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved18; /** Offset 0x032A - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. @@ -538,7 +567,7 @@ typedef struct { /** Offset 0x032B - Reserved **/ - UINT8 Reserved20[31]; + UINT8 Reserved19[31]; /** Offset 0x034A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -552,7 +581,7 @@ typedef struct { /** Offset 0x034C - Reserved **/ - UINT8 Reserved21[4]; + UINT8 Reserved20[4]; /** Offset 0x0350 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -566,7 +595,7 @@ typedef struct { /** Offset 0x0358 - Reserved **/ - UINT8 Reserved22[8]; + UINT8 Reserved21[8]; /** Offset 0x0360 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -580,7 +609,7 @@ typedef struct { /** Offset 0x0368 - Reserved **/ - UINT8 Reserved23[522]; + UINT8 Reserved22[522]; /** Offset 0x0572 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -589,7 +618,7 @@ typedef struct { /** Offset 0x0573 - Reserved **/ - UINT8 Reserved24[4]; + UINT8 Reserved23[4]; /** Offset 0x0577 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -604,7 +633,7 @@ typedef struct { /** Offset 0x0597 - Reserved **/ - UINT8 Reserved25[5]; + UINT8 Reserved24[5]; /** Offset 0x059C - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -627,7 +656,7 @@ typedef struct { /** Offset 0x05A2 - Reserved **/ - UINT8 Reserved26[14]; + UINT8 Reserved25[14]; /** Offset 0x05B0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -637,7 +666,7 @@ typedef struct { /** Offset 0x05B1 - Reserved **/ - UINT8 Reserved27[4]; + UINT8 Reserved26[4]; /** Offset 0x05B5 - MRC Safe Config Enables/Disable MRC Safe Config @@ -683,7 +712,7 @@ typedef struct { /** Offset 0x05BC - Reserved **/ - UINT8 Reserved28[4]; + UINT8 Reserved27[4]; /** Offset 0x05C0 - Early Command Training Enables/Disable Early Command Training @@ -693,7 +722,7 @@ typedef struct { /** Offset 0x05C1 - Reserved **/ - UINT8 Reserved29[109]; + UINT8 Reserved28[109]; /** Offset 0x062E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -703,7 +732,7 @@ typedef struct { /** Offset 0x0630 - Reserved **/ - UINT8 Reserved30[62]; + UINT8 Reserved29[62]; /** Offset 0x066E - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -716,7 +745,7 @@ typedef struct { /** Offset 0x066F - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved30[2]; /** Offset 0x0671 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -726,7 +755,7 @@ typedef struct { /** Offset 0x0672 - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved31[2]; /** Offset 0x0674 - TCSS USB Port Enable Bitmap for per port enabling @@ -735,7 +764,7 @@ typedef struct { /** Offset 0x0675 - Reserved **/ - UINT8 Reserved33[80]; + UINT8 Reserved32[80]; /** Offset 0x06C5 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -746,7 +775,7 @@ typedef struct { /** Offset 0x06C6 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x06C8 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -756,7 +785,7 @@ typedef struct { /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved35[122]; + UINT8 Reserved34[122]; /** Offset 0x0743 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -766,7 +795,7 @@ typedef struct { /** Offset 0x0744 - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved35[3]; /** Offset 0x0747 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -775,7 +804,7 @@ typedef struct { /** Offset 0x0749 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x074C - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* @@ -795,7 +824,7 @@ typedef struct { /** Offset 0x075D - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved37[3]; /** Offset 0x0760 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -832,7 +861,7 @@ typedef struct { /** Offset 0x0775 - Reserved **/ - UINT8 Reserved39[355]; + UINT8 Reserved38[355]; } FSP_M_CONFIG; /** Fsp M UPD Configuration From 3a02147d227b16f6b6adb0c4b4529cade902f27c Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 16 Feb 2020 11:51:57 +0300 Subject: [PATCH 0235/1463] soc/intel/gpio_defs: add a new macro for pad config Adds PAD_CFG_NF_BUF_IOSSTATE_IOSTERM macro to configure native function, iosstate, iosterm and disable input/output buffer. This is used in the pad configurations for the Kontron COMe-mAL10 module board [1]. [1] https://review.coreboot.org/c/coreboot/+/39133 Change-Id: I7aa4d4dee34bd46a064079c576ed64525fd489e6 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38813 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 3e9250e7c9..dda02472a1 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -226,6 +226,11 @@ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +/* Configure native function, iosstate, iosterm and disable input/output buffer */ +#define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ From 7b98e3ebfc3ac12972ba36418f5de7595cc2fb8f Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 16 Feb 2020 11:51:57 +0300 Subject: [PATCH 0236/1463] soc/intel/apl: disable NPK device in devicetree.cb Allows to enable/disable NPK device from the device tree: device pci 00.2 off end # NPK Tested on Kontron come-mal10. Change-Id: I910245d4ff35a6a0a9059fb6911d4426cdb999b6 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38814 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/chip.c | 6 ++++++ src/soc/intel/apollolake/romstage.c | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 03e6dbd038..37fdfff90b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -425,6 +425,12 @@ static void soc_final(void *data) static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) { switch (dev->path.pci.devfn) { + case PCH_DEVFN_NPK: + /* + * Disable this device in the parse_devicetree_setting() function + * in romstage.c + */ + break; case PCH_DEVFN_ISH: silconfig->IshEnable = 0; break; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 13adeeef40..05cd0db401 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -291,12 +291,12 @@ static void soc_memory_init_params(FSPM_UPD *mupd) static void parse_devicetree_setting(FSPM_UPD *m_upd) { -#if CONFIG(SOC_INTEL_GLK) DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); - if (!dev) - return; - m_upd->FspmConfig.TraceHubEn = dev->enabled; +#if CONFIG(SOC_INTEL_GLK) + m_upd->FspmConfig.TraceHubEn = dev ? dev->enabled : 0; +#else + m_upd->FspmConfig.NpkEn = dev ? dev->enabled : 0; #endif } From f0303dbf919e1a207f2f689e5b344f8e4cee0ab4 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 23 Feb 2020 10:51:00 +0300 Subject: [PATCH 0237/1463] mb/asrock/h110m: Explain why some SATA ports are empty Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39119 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asrock/h110m/devicetree.cb | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index fa94dd9e5b..d42d91e556 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -180,6 +180,11 @@ chip soc/intel/skylake # SATA register "EnableSata" = "1" register "SataSalpSupport" = "1" + # SATA4 and SATA5 are located in the lower right corner of the board, + # but they are not populated. This is because the same PCB is used to + # make boards with better PCHs, which can have up to six SATA ports. + # However, the H110 PCH only has four SATA ports, which explains why + # two connectors are missing. register "SataPortsEnable" = "{ \ [0] = 1, \ [1] = 1, \ @@ -190,8 +195,6 @@ chip soc/intel/skylake [6] = 0, \ [7] = 0, \ }" - # SATA4 and SATA5 are located in the lower right corner - # of the board, but there is no connector for this # PCH UART, SPI, I2C register "SerialIoDevMode" = "{ \ From 63cdea2b2d6062f02a17b9f2e136f714f403f6f4 Mon Sep 17 00:00:00 2001 From: Mete Balci Date: Fri, 8 Mar 2019 11:13:45 +0000 Subject: [PATCH 0238/1463] util/chromeos: Add unzip as a dependency unzip might not be installed by default, so it is added as a dependency in crosfirmware script. Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Signed-off-by: Mete Balci Reviewed-on: https://review.coreboot.org/c/coreboot/+/31821 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/chromeos/crosfirmware.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index dc33fac8ce..5fec96b485 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -37,6 +37,7 @@ exit_if_dependencies_are_missing() { exit_if_uninstalled "debugfs" "e2fsprogs" exit_if_uninstalled "parted" "parted" exit_if_uninstalled "curl" "curl" + exit_if_uninstalled "unzip" "unzip" } get_inventory() From 8187f11d1a3b21a4cf38f4560f9c9921deb06757 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 24 Dec 2018 21:46:46 -0600 Subject: [PATCH 0239/1463] sb/lynxpoint: hook up smmstore Adapted from implementation in sb/intel/common. Test: build/boot variants of google/{beltino,slippy} with Tianocore and SMMSTORE enabled Change-Id: I64f520d17146206b8b9b41fc4f827539c5cfd507 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39189 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/southbridge/intel/lynxpoint/smihandler.c | 26 +++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 72c344757d..4ac4ff948d 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -29,7 +29,7 @@ #include #include #include - +#include #include "me.h" #include "pch.h" #include "nvs.h" @@ -266,6 +266,26 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t101_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { u8 reg8; @@ -332,6 +352,10 @@ static void southbridge_smi_apmc(void) if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); From c6ab2ffaa06182803e9df59060faa34032fdd62e Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 21 Feb 2020 14:58:43 +1100 Subject: [PATCH 0240/1463] mainboard/google/octopus: Migrate onto SKU ID helpers Leverage the common sku id space helper encoders and set the sku id max to 0xff for legacy to ensure we behave the same. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/ec/google/chromeec/Makefile.inc | 1 + src/mainboard/google/octopus/Kconfig | 1 + src/mainboard/google/octopus/Makefile.inc | 1 - src/mainboard/google/octopus/mainboard_misc.c | 29 +------------------ .../baseboard/include/baseboard/variants.h | 2 -- .../google/octopus/variants/bloog/variant.c | 4 +-- .../google/octopus/variants/bobba/gpio.c | 3 +- .../google/octopus/variants/bobba/variant.c | 5 ++-- .../google/octopus/variants/casta/variant.c | 5 ++-- .../google/octopus/variants/dood/gpio.c | 3 +- .../google/octopus/variants/dood/variant.c | 3 +- .../google/octopus/variants/foob/gpio.c | 6 ++-- .../google/octopus/variants/foob/variant.c | 2 +- .../google/octopus/variants/garg/gpio.c | 3 +- .../google/octopus/variants/garg/variant.c | 4 +-- .../google/octopus/variants/meep/gpio.c | 3 +- .../google/octopus/variants/meep/variant.c | 4 +-- 17 files changed, 28 insertions(+), 51 deletions(-) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index b57333e202..2833c87d33 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -6,6 +6,7 @@ romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index a4e49824fc..e52e994433 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index d36d5f7dbe..b8a7366f06 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c smm-y += smihandler.c -smm-y += mainboard_misc.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/octopus/mainboard_misc.c b/src/mainboard/google/octopus/mainboard_misc.c index 3672f66692..8b281da9d0 100644 --- a/src/mainboard/google/octopus/mainboard_misc.c +++ b/src/mainboard/google/octopus/mainboard_misc.c @@ -21,34 +21,7 @@ #include #include -#define SKU_UNKNOWN 0xFFFFFFFF -#define SKU_MAX 255 - -uint32_t get_board_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - const char *smbios_system_sku(void) { - static char sku_str[7]; /* sku{0..255} */ - uint32_t sku_id = get_board_sku(); - - if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; + return google_chromeec_smbios_system_sku(); } diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 2132db591d..bf08a8588d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -35,8 +35,6 @@ extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; const struct lpddr4_cfg *variant_lpddr4_config(void); /* Return memory SKU for the board. */ size_t variant_memory_sku(void); -/* Return board SKU */ -uint32_t get_board_sku(void); /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 6c85e50948..05a1542d9a 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -42,7 +42,7 @@ enum { const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_BLOOG: @@ -67,7 +67,7 @@ const char *mainboard_vbt_filename(void) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_BLOOG: diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 7c522c78ef..dd1084099a 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -18,6 +18,7 @@ #include #include #include +#include enum { SKU_37_DROID = 37, /* LTE */ @@ -60,7 +61,7 @@ static const struct pad_config lte_override_table[] = { const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_37_DROID: diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 1f6e80db78..03eacbfe5d 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -19,6 +19,7 @@ #include #include #include +#include enum { SKU_37_DROID = 37, /* LTE */ @@ -58,7 +59,7 @@ static void power_off_lte_module(u8 slp_typ) const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 41 || sku_id == 42 || sku_id == 43 || sku_id == 44) @@ -74,7 +75,7 @@ void variant_smi_sleep(u8 slp_typ) if (slp_typ != ACPI_S5) return; - switch (get_board_sku()) { + switch (google_chromeec_get_board_sku()) { case SKU_37_DROID: case SKU_38_DROID: case SKU_39_DROID: diff --git a/src/mainboard/google/octopus/variants/casta/variant.c b/src/mainboard/google/octopus/variants/casta/variant.c index 12c8dd747b..4b1e42d9c3 100644 --- a/src/mainboard/google/octopus/variants/casta/variant.c +++ b/src/mainboard/google/octopus/variants/casta/variant.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include @@ -21,7 +22,7 @@ const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); if (sku_id == 2) filename = "wifi_sar-bluebird.hex"; @@ -31,7 +32,7 @@ const char *get_wifi_sar_cbfs_filename(void) bool variant_ext_usb_status(unsigned int port_type, unsigned int port_id) { - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); if (sku_id == 2 && port_id == RIGHT_USB_C_PORT_ID) return false; diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 96b8ac02c7..3d09a39efd 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -18,6 +18,7 @@ #include #include #include +#include enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -60,7 +61,7 @@ static const struct pad_config lte_override_table[] = { const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_1_LTE: diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 694e190892..b54b9fa084 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -19,6 +19,7 @@ #include #include #include +#include enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -63,7 +64,7 @@ void variant_smi_sleep(u8 slp_typ) if (slp_typ != ACPI_S5) return; - switch (get_board_sku()) { + switch (google_chromeec_get_board_sku()) { case SKU_1_LTE: case SKU_3_LTE_2CAM: power_off_lte_module(slp_typ); diff --git a/src/mainboard/google/octopus/variants/foob/gpio.c b/src/mainboard/google/octopus/variants/foob/gpio.c index dec2ff550d..55f8196dbc 100644 --- a/src/mainboard/google/octopus/variants/foob/gpio.c +++ b/src/mainboard/google/octopus/variants/foob/gpio.c @@ -20,8 +20,6 @@ #include #include -#define SKU_UNKNOWN 0xFFFFFFFF - static const struct pad_config default_override_table[] = { PAD_NC(GPIO_52, UP_20K), PAD_NC(GPIO_53, UP_20K), @@ -70,9 +68,9 @@ bool no_touchscreen_sku(uint32_t sku_id) const struct pad_config *variant_override_gpio_table(size_t *num) { const struct pad_config *c; - uint32_t sku_id = SKU_UNKNOWN; + uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if (no_touchscreen_sku(sku_id)) { c = non_touchscreen_override_table; *num = ARRAY_SIZE(non_touchscreen_override_table); diff --git a/src/mainboard/google/octopus/variants/foob/variant.c b/src/mainboard/google/octopus/variants/foob/variant.c index dcc11dd0bb..47639f6345 100644 --- a/src/mainboard/google/octopus/variants/foob/variant.c +++ b/src/mainboard/google/octopus/variants/foob/variant.c @@ -30,7 +30,7 @@ void variant_update_devtree(struct device *dev) return; /* SKU ID 1 does not have a touchscreen device, hence disable it. */ - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if (no_touchscreen_sku(sku_id)) touchscreen_i2c_host->enabled = 0; } diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index eeeb4662e3..987c69e7bd 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -19,6 +19,7 @@ #include #include #include +#include static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -72,7 +73,7 @@ static const struct pad_config lte_override_table[] = { const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_9_HDMI: diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index f5f350a8f0..2afceb9b41 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -54,7 +54,7 @@ const char *mainboard_vbt_filename(void) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_9_HDMI: @@ -72,7 +72,7 @@ void variant_smi_sleep(u8 slp_typ) if (slp_typ != ACPI_S5) return; - switch (get_board_sku()) { + switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: power_off_lte_module(slp_typ); diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 44d9fff129..ed4eb059bf 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -18,6 +18,7 @@ #include #include #include +#include static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -44,7 +45,7 @@ static const struct pad_config hdmi_sku_override_table[] = { const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_DORP: diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index 20aaa0a1f4..7cd1e472bf 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -22,7 +22,7 @@ const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_1_MEEP: @@ -45,7 +45,7 @@ const char *mainboard_vbt_filename(void) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_DORP: From abd02cc1caa72585550d62d653cc5db5dd082fb5 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 21 Feb 2020 15:11:47 +1100 Subject: [PATCH 0241/1463] mainboard/google/dedede: Migrate onto SKU ID/fw_config helpers Leverage the common sku id space helper encoders. dedede uses the non-legacy SKU ID space. squash in, mainboard/google/dedede: Migrate onto get fw_config helper BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/Kconfig | 1 + src/mainboard/google/dedede/board_info.c | 40 +----------------------- 2 files changed, 2 insertions(+), 39 deletions(-) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index ebca580ffa..2606e57364 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_SKUID select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index ee89beb56d..7b10b23009 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -12,37 +12,9 @@ #include #include -#define SKU_UNKNOWN 0xffffffff -#define SKU_MAX 0x7fffffff - -static uint32_t board_info_get_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - const char *smbios_system_sku(void) { - /* sku{0..2147483647} */ - static char sku_str[14]; - uint32_t sku_id = board_info_get_sku(); - - if (sku_id == SKU_UNKNOWN || sku_id > SKU_MAX) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; + return google_chromeec_smbios_system_sku(); } const char *smbios_mainboard_manufacturer(void) @@ -66,15 +38,5 @@ const char *smbios_mainboard_manufacturer(void) int board_info_get_fw_config(uint32_t *fw_config) { - uint32_t sku_id = board_info_get_sku(); - - /* - * FW_CONFIG can potentially have all the bits set. So check the - * sku_id to ensure that the CBI is provisioned before reading the - * FW_CONFIG. - */ - if (sku_id == SKU_UNKNOWN || sku_id > SKU_MAX) - return -1; - return google_chromeec_cbi_get_fw_config(fw_config); } From 2d7bb7e141127eccf5426b7998fa2dce0a186c33 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 27 Feb 2020 15:27:31 +1100 Subject: [PATCH 0242/1463] src/ec,mainboard: Move weak smbios_system_sku() override inwards Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c implementation and simply wrap a call to: google_chromeec_smbios_system_sku(). BUG=b:150735116 BRANCH=none TEST=none Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec_skuid.c | 6 +++++ src/mainboard/google/dedede/board_info.c | 5 ---- src/mainboard/google/hatch/mainboard.c | 5 ---- src/mainboard/google/octopus/Makefile.inc | 1 - src/mainboard/google/octopus/mainboard_misc.c | 27 ------------------- src/mainboard/google/volteer/mainboard.c | 5 ---- 6 files changed, 6 insertions(+), 43 deletions(-) delete mode 100644 src/mainboard/google/octopus/mainboard_misc.c diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index f8fc203c47..ac69b136ee 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -11,6 +11,7 @@ #include #include #include +#include #define SKU_UNKNOWN 0xFFFFFFFF @@ -34,3 +35,8 @@ const char *google_chromeec_smbios_system_sku(void) snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); return sku_str; } + +const char *smbios_system_sku(void) +{ + return google_chromeec_smbios_system_sku(); +} diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index 7b10b23009..1d222b245d 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -12,11 +12,6 @@ #include #include -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} - const char *smbios_mainboard_manufacturer(void) { static char oem_name[32]; diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index 888acf720f..e0e7a32456 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -21,11 +21,6 @@ #include #include -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} - const char *smbios_mainboard_manufacturer(void) { static char oem_name[32]; diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index b8a7366f06..aa055246d2 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -5,7 +5,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c -ramstage-y += mainboard_misc.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/octopus/mainboard_misc.c b/src/mainboard/google/octopus/mainboard_misc.c deleted file mode 100644 index 8b281da9d0..0000000000 --- a/src/mainboard/google/octopus/mainboard_misc.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index dcefb5d9cd..6ed928a76b 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -17,11 +17,6 @@ #include #include -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} - static void mainboard_init(struct device *dev) { mainboard_ec_init(); From fdccfc62676719ff4fa09c9aa485a96fa7e818f7 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 15 Jan 2019 07:29:57 +0100 Subject: [PATCH 0243/1463] soc/intel/denverton_ns: Allow using FSP repo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit is adding a dependency check for the FSP_USE_REPO config option which so far was not able to deal with Denverton systems. Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/30931 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/drivers/intel/fsp2_0/Kconfig | 3 ++- src/soc/intel/denverton_ns/Kconfig | 9 +++++++++ src/soc/intel/denverton_ns/Makefile.inc | 2 -- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 2d45343083..2624644fae 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -55,7 +55,8 @@ config FSP_USE_REPO depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ - SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE + SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 9a611271ab..a74250bab3 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -79,6 +79,15 @@ config FSP_S_ADDR help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 4050f61811..7529892dcc 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -86,10 +86,8 @@ verstage-y += tsc_freq.c verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/denverton_ns ##Set FSP binary blobs memory location - $(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip From 4af0adb443afaed32369fe7a9eb91ff93549ea26 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Sat, 29 Feb 2020 00:32:23 -0800 Subject: [PATCH 0244/1463] soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake update SerialIoUartAutoFlow settings for Tiger Lake platform. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169 Reviewed-by: Wonkyu Kim Reviewed-by: caveh jalali Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params_tgl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index fbc9f23083..0587b88868 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -120,6 +121,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); + params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; /* SATA */ dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); From 63266c7e6697a3ccbe2ec370e89605c8d7ec7e33 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 20 Feb 2020 20:20:00 +0100 Subject: [PATCH 0245/1463] cpu/microcode: Fix config CPU_MICROCODE_CBFS_EXTERNAL_BINS Make the variable override for CPU_MICROCODE_CBFS_EXTERNAL_BINS local to the target. Otherwise, `cpu_microcode_bin +=` lines that are evaluated after `src/cpu/Makefile.inc` still append to it. Change-Id: If81f307afc325ff3c1e987e9483ed5e45fdc403e Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39031 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/cpu/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 0289be0297..92e47aa3a2 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -28,7 +28,7 @@ $(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y) -cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES)) +$(obj)/cpu_microcode_blob.bin: cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES)) endif # otherwise `cpu_microcode_bins` should be filled by platform makefiles From 573481bf6f74af7e84fda2db63a8c6aa2466f746 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 2 Mar 2020 14:21:32 +0100 Subject: [PATCH 0246/1463] cpu/intel/model_206ax: Lock MSR on all cores Lock MSR MSR_PKG_CST_CONFIG_CONTROL on all cores, not only the one handling APM_CNT_FINALIZE. Tested on HP Z220: FWTS no longer reports this as an issue. Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39199 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/cpu/intel/model_206ax/finalize.c | 3 --- src/cpu/intel/model_206ax/model_206ax_init.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index d51fb21847..a7754ae969 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -25,9 +25,6 @@ void intel_model_206ax_finalize_smm(void) { - /* Lock C-State MSR */ - msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); - /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 2571f8cb40..773940850d 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -256,6 +256,8 @@ static void configure_c_states(void) msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection msr.lo |= 7; // No package C-state limit + + msr.lo |= (1 << 15); // Lock C-State MSR wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); From e5b2453f91a1795394cb8c3c51d4f0e1dce7cb22 Mon Sep 17 00:00:00 2001 From: Thomas Heijligen Date: Wed, 10 Jul 2019 16:04:50 +0200 Subject: [PATCH 0247/1463] libpayload: add read64() and write64() Change-Id: I6febf13ed54a7707f5a99d3d2715c36e18517c12 Signed-off-by: Thomas Heijligen Reviewed-on: https://review.coreboot.org/c/coreboot/+/34206 Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- payloads/libpayload/include/x86/arch/io.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index c417ce0c66..46836d9f7b 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -64,6 +64,11 @@ static inline __attribute__((always_inline)) uint32_t read32(const volatile void return *((volatile uint32_t *)(addr)); } +static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr) +{ + return *((volatile uint64_t *)(addr)); +} + static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value) { *((volatile uint8_t *)(addr)) = value; @@ -79,6 +84,11 @@ static inline __attribute__((always_inline)) void write32(volatile void *addr, u *((volatile uint32_t *)(addr)) = value; } +static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value) +{ + *((volatile uint64_t *)(addr)) = value; +} + static inline unsigned int inl(int port) { unsigned long val; From f3161df2eba8d61445372a9c732c61a1947064bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 23 Feb 2020 13:23:04 +0100 Subject: [PATCH 0248/1463] soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current elog implemetation searches for an active PME status bit by iterating the PCI devices. On disabled or hidden devices a BUG gets triggered: BUG: pch_log_rp_wake_source requests hidden ... This is caused by the use of the PCH_DEV_* macros which resolve to _PCH_DEV and finally call pcidev_path_on_root_debug. Disabled devices are skipped already so we can safely use the DEVFNs instead, circumventing the BUG. Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39089 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn --- src/soc/intel/skylake/elog.c | 105 ++++++++++++++--------------------- 1 file changed, 41 insertions(+), 64 deletions(-) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 411b3e99a1..63f382d222 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -41,30 +41,20 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } struct pme_status_info { -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; -#else - struct device *dev; -#endif + pci_devfn_t devfn; uint8_t reg_offset; uint32_t elog_event; }; #define PME_STS_BIT (1 << 15) -#ifdef __SIMPLE_DEVICE__ -static void pch_log_add_elog_event(const struct pme_status_info *info, - pci_devfn_t dev) -#else -static void pch_log_add_elog_event(const struct pme_status_info *info, - struct device *dev) -#endif +static void pch_log_add_elog_event(const struct pme_status_info *info) { /* * If wake source is XHCI, check for detailed wake source events on * USB2/3 ports. */ - if ((info->dev == PCH_DEV_XHCI) && + if ((info->devfn == PCH_DEVFN_XHCI) && pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return; @@ -74,34 +64,28 @@ static void pch_log_add_elog_event(const struct pme_status_info *info, static void pch_log_pme_internal_wake_source(void) { size_t i; -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; -#else - struct device *dev; -#endif uint16_t val; bool dev_found = false; struct pme_status_info pme_status_info[] = { - { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA }, - { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE }, - { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, - { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, - { PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI }, - { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI }, }; for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { - dev = pme_status_info[i].dev; - if (!dev) - continue; + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(pme_status_info[i].devfn), + PCI_FUNC(pme_status_info[i].devfn)); - val = pci_read_config16(dev, pme_status_info[i].reg_offset); + val = pci_s_read_config16(dev, pme_status_info[i].reg_offset); if ((val == 0xFFFF) || !(val & PME_STS_BIT)) continue; - pch_log_add_elog_event(&pme_status_info[i], dev); + pch_log_add_elog_event(&pme_status_info[i]); dev_found = true; } @@ -123,49 +107,42 @@ static void pch_log_pme_internal_wake_source(void) static void pch_log_rp_wake_source(void) { size_t i, maxports; -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; -#else - struct device *dev; -#endif uint32_t val; struct pme_status_info pme_status_info[] = { - { PCH_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 }, - { PCH_DEV_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 }, - { PCH_DEV_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 }, - { PCH_DEV_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 }, - { PCH_DEV_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 }, - { PCH_DEV_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 }, - { PCH_DEV_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 }, - { PCH_DEV_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 }, - { PCH_DEV_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 }, - { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, - { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, - { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, - { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, - { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, - { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, - { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, - { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, - { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, - { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, - { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, - { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, - { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, - { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, - { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, + { PCH_DEVFN_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + { PCH_DEVFN_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { PCH_DEVFN_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, + { PCH_DEVFN_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, + { PCH_DEVFN_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, + { PCH_DEVFN_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, + { PCH_DEVFN_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, + { PCH_DEVFN_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, + { PCH_DEVFN_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, + { PCH_DEVFN_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, + { PCH_DEVFN_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, + { PCH_DEVFN_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, + { PCH_DEVFN_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, }; maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); for (i = 0; i < maxports; i++) { - dev = pme_status_info[i].dev; + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(pme_status_info[i].devfn), + PCI_FUNC(pme_status_info[i].devfn)); - if (!dev) - continue; - - val = pci_read_config32(dev, pme_status_info[i].reg_offset); + val = pci_s_read_config32(dev, pme_status_info[i].reg_offset); if ((val == 0xFFFFFFFF) || !(val & RP_PME_STS_BIT)) continue; @@ -174,7 +151,7 @@ static void pch_log_rp_wake_source(void) * Linux kernel uses PME STS bit information. So do not clear * this bit. */ - pch_log_add_elog_event(&pme_status_info[i], dev); + pch_log_add_elog_event(&pme_status_info[i]); } } From 79ccc6933284ca02d17d9e1eda9a531ce43e1f65 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 24 Feb 2020 13:43:39 +0100 Subject: [PATCH 0249/1463] src: capitalize 'PCIe' Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/amd/agesa/family14/fixme.c | 4 ++-- src/mainboard/asrock/e350m1/acpi/routing.asl | 2 +- src/mainboard/asus/f2a85-m/acpi/routing.asl | 2 +- src/mainboard/gizmosphere/gizmo/acpi/routing.asl | 2 +- src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl | 2 +- src/mainboard/lenovo/g505s/acpi/routing.asl | 2 +- src/mainboard/msi/ms7721/acpi/routing.asl | 2 +- src/mainboard/pcengines/apu1/acpi/routing.asl | 2 +- src/soc/intel/baytrail/acpi/globalnvs.asl | 2 +- src/soc/intel/baytrail/include/soc/nvs.h | 2 +- src/soc/intel/baytrail/pcie.c | 2 +- src/soc/intel/braswell/acpi/globalnvs.asl | 2 +- src/soc/intel/braswell/include/soc/nvs.h | 2 +- src/soc/intel/broadwell/acpi/globalnvs.asl | 2 +- src/soc/intel/broadwell/include/soc/nvs.h | 2 +- src/soc/intel/cannonlake/chip.h | 2 +- src/soc/intel/denverton_ns/smm.c | 2 +- src/soc/intel/icelake/chip.h | 2 +- src/soc/intel/skylake/acpi/globalnvs.asl | 2 +- src/soc/intel/skylake/chip.h | 2 +- src/soc/intel/skylake/include/soc/nvs.h | 2 +- src/soc/intel/tigerlake/chip.h | 2 +- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 2 +- src/southbridge/intel/bd82x6x/nvs.h | 2 +- src/southbridge/intel/bd82x6x/pch.c | 4 ++-- src/southbridge/intel/ibexpeak/nvs.h | 2 +- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 2 +- src/southbridge/intel/lynxpoint/nvs.h | 2 +- 28 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index be7c635471..658434d2c8 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -100,7 +100,7 @@ void amd_initenv(void) PciValue |= 0x80000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize GMM Base Address for Pcie Mode + /* Initialize GMM Base Address for PCIe Mode * Modify B0D1F0x18 */ PciAddress.Address.Bus = 0; @@ -112,7 +112,7 @@ void amd_initenv(void) PciValue |= 0x96000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize FB Base Address for Pcie Mode + /* Initialize FB Base Address for PCIe Mode * Modify B0D1F0x10 */ PciAddress.Address.Register = 0x10; diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 537bcacaa1..06750124e2 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -199,7 +199,7 @@ Scope(\_SB) { /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index c0aef87a15..38ba142795 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -78,7 +78,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index 447d992351..af05ec6848 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -200,7 +200,7 @@ Scope(\_SB) { /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl index 22c45501a6..a1ce860682 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index 22c45501a6..a1ce860682 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl index 0af6b42cad..5443dd5307 100644 --- a/src/mainboard/msi/ms7721/acpi/routing.asl +++ b/src/mainboard/msi/ms7721/acpi/routing.asl @@ -71,7 +71,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index 9a63d72232..79ebef3f03 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -162,7 +162,7 @@ Scope(\_SB) { /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 703e20fa8a..a8b0f53719 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -99,7 +99,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 4a89eb967e..8532728503 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -83,7 +83,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 6dc0346b23..6b6c28d731 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -163,7 +163,7 @@ static u8 all_ports_no_dev_present(struct device *dev) dev->path.pci.devfn &= ~0x7; dev->path.pci.devfn |= func; - /* is pcie device there */ + /* is PCIe device there */ if (pci_read_config32(dev, 0) == 0xFFFFFFFF) continue; diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index a67117da5f..41f1854d30 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -101,7 +101,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 33800ef8fd..f4cd8f2444 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -86,7 +86,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 22a22e3ed1..87c053bc2a 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -91,7 +91,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 456fda6fa6..ea64341e58 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -75,7 +75,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd2; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 752ec1f315..330555c0c0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -180,7 +180,7 @@ struct soc_intel_cannonlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index d05e76bcf9..75f179ec67 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -53,7 +53,7 @@ void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events Disable pcie wake. */ + /* Configure events Disable PCIe wake. */ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); disable_gpe(PME_B0_EN); diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 569160f41f..56f89db5e7 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,7 +134,7 @@ struct soc_intel_icelake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index e17b2604cf..8aeb5a37f0 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -106,7 +106,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b189a16a05..2c3d3a59c8 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -226,7 +226,7 @@ struct soc_intel_skylake_config { u8 PchDciEn; /* - * Pcie Root Port configuration: + * PCIe Root Port configuration: * each element of array corresponds to * respective PCIe root port. */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index d5f62f63fc..24e4cf1a2a 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -88,7 +88,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 9eee97d53b..e57abe857b 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -114,7 +114,7 @@ struct soc_intel_tigerlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 4b54d61b66..5f41f441f5 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -166,7 +166,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index a6b0bdbc55..0ec0c05cb0 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -138,7 +138,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 5c2b130b7e..7c672b3cb5 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -351,8 +351,8 @@ static void pch_pcie_enable(struct device *dev) * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 * - * This check is done here instead of pcie driver - * because the pcie driver enable() handler is not + * This check is done here instead of PCIe driver + * because the PCIe driver enable() handler is not * called unless the device is enabled. */ if ((PCI_FUNC(dev->path.pci.devfn) == 0 || diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index a95639894f..a0422f2bed 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -137,7 +137,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index fddfa701af..3c873a2e60 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -161,7 +161,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 3aca7bbda3..34c2537e2e 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -114,7 +114,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ From ee37c39a4318ff846aa15593f8cc35f701c8575f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 1 Jan 2020 21:29:04 +0100 Subject: [PATCH 0250/1463] include/cpu/amd: Drop unused files Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38055 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/include/cpu/amd/amdfam10_sysconf.h | 75 -------------------------- src/include/cpu/amd/model_10xxx_rev.h | 23 -------- src/include/cpu/amd/multicore.h | 43 --------------- src/include/cpu/amd/powernow.h | 24 --------- 4 files changed, 165 deletions(-) delete mode 100644 src/include/cpu/amd/amdfam10_sysconf.h delete mode 100644 src/include/cpu/amd/model_10xxx_rev.h delete mode 100644 src/include/cpu/amd/multicore.h delete mode 100644 src/include/cpu/amd/powernow.h diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h deleted file mode 100644 index fc7b6bfe47..0000000000 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_SYSCONF_H -#define AMDFAM10_SYSCONF_H - -#include "northbridge/amd/amdfam10/nums.h" - -#include - -struct p_state_t { - unsigned int corefreq; - unsigned int power; - unsigned int transition_lat; - unsigned int busmaster_lat; - unsigned int control; - unsigned int status; -}; - -struct amdfam10_sysconf_t { - //ht - unsigned int hc_possible_num; - unsigned int pci1234[HC_POSSIBLE_NUM]; - unsigned int hcdn[HC_POSSIBLE_NUM]; - unsigned int hcid[HC_POSSIBLE_NUM]; //record ht chain type - unsigned int sbdn; - unsigned int sblk; - - unsigned int nodes; - unsigned int ht_c_num; // we only can have 32 ht chain at most - // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable - unsigned int ht_c_conf_bus[HC_NUMS]; - unsigned int io_addr_num; - unsigned int conf_io_addr[HC_NUMS]; - unsigned int conf_io_addrx[HC_NUMS]; - unsigned int mmio_addr_num; - unsigned int conf_mmio_addr[HC_NUMS*2]; // mem and pref mem - unsigned int conf_mmio_addrx[HC_NUMS*2]; - unsigned int segbit; - unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 - - // quad cores all cores in one node should be the same, and p0,..p5 - msr_t msr_pstate[NODE_NUMS * 5]; - unsigned int needs_update_pstate_msrs; - - unsigned int bsp_apicid; - int enabled_apic_ext_id; - unsigned int lift_bsp_apicid; - int apicid_offset; - - void *mb; // pointer for mb related struct - -}; - -extern struct amdfam10_sysconf_t sysconf; - -void get_bus_conf(void); -void get_pci1234(void); -void get_default_pci1234(int mb_hc_possible); - -extern u8 pirq_router_bus; - -#endif diff --git a/src/include/cpu/amd/model_10xxx_rev.h b/src/include/cpu/amd/model_10xxx_rev.h deleted file mode 100644 index 88d395e5c8..0000000000 --- a/src/include/cpu/amd/model_10xxx_rev.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CPU_AMD_MODEL_10XXX_REV_H__ -#define __CPU_AMD_MODEL_10XXX_REV_H__ - -int init_processor_name(void); - -/* place holder for Family 10 revision code */ - -#endif /* __CPU_AMD_MODEL_10XXX_REV_H__ */ diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h deleted file mode 100644 index 79bea66f68..0000000000 --- a/src/include/cpu/amd/multicore.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CPU_AMD_QUADCORE_H -#define CPU_AMD_QUADCORE_H - -#include -#include - -u32 read_nb_cfg_54(void); - -struct node_core_id { - u32 nodeid; - u32 coreid; -}; - -// it can be used to get unitid and coreid it running only -struct node_core_id get_node_core_id(u32 nb_cfg_54); -struct node_core_id get_node_core_id_x(void); - -u32 get_apicid_base(u32 ioapic_num); -void amd_sibling_init(struct device *cpu); - -void wait_all_core0_started(void); -void wait_all_other_cores_started(u32 bsp_apicid); -void wait_all_aps_started(u32 bsp_apicid); -void wait_all_other_cores_stopped(uint32_t bsp_apicid); -void allow_all_aps_stop(u32 bsp_apicid); -u32 get_initial_apicid(void); - -#endif /* CPU_AMD_QUADCORE_H */ diff --git a/src/include/cpu/amd/powernow.h b/src/include/cpu/amd/powernow.h deleted file mode 100644 index 77df7b031e..0000000000 --- a/src/include/cpu/amd/powernow.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Rudolf Marek - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef POWERNOW_H -#define POWERNOW_H - -void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP); -void amd_powernow_update_fadt(acpi_fadt_t *fadt); - -#endif From 761dbe228d023984efa1d2761a1611e567c26927 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 1 Jan 2020 21:27:37 +0100 Subject: [PATCH 0251/1463] nb/amd/agesa/family14/acpi: Fix comment "amdfam10" is no more. Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38054 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl index add58ff2e5..1f877ccc6e 100644 --- a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl +++ b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl @@ -25,7 +25,7 @@ * Scope (\_SB.PCI0) { * Device (K10M) { * Name (_ADR, 0x00180003) - * #include + * #include * } * } * From 446e4dc238d13ecf22e4aa05d15bf5173f9f547c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 12 Feb 2020 22:59:40 +0100 Subject: [PATCH 0252/1463] util: Remove viatool It somehow creeps into `make clean`, but is not used at all. Since no VIA platform remains in coreboot, drop the utility as well. Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .gitignore | 1 - Documentation/util.md | 2 - util/README.md | 2 - util/testing/Makefile.inc | 3 +- util/viatool/Makefile | 103 --- util/viatool/README | 12 - util/viatool/cpu.c | 1019 ---------------------------- util/viatool/description.md | 1 - util/viatool/quirks/quirks.c | 115 ---- util/viatool/quirks/quirks.h | 34 - util/viatool/quirks/vx900_quirks.c | 81 --- util/viatool/viatool.c | 262 ------- util/viatool/viatool.h | 99 --- 13 files changed, 1 insertion(+), 1733 deletions(-) delete mode 100644 util/viatool/Makefile delete mode 100644 util/viatool/README delete mode 100644 util/viatool/cpu.c delete mode 100644 util/viatool/description.md delete mode 100644 util/viatool/quirks/quirks.c delete mode 100644 util/viatool/quirks/quirks.h delete mode 100644 util/viatool/quirks/vx900_quirks.c delete mode 100644 util/viatool/viatool.c delete mode 100644 util/viatool/viatool.h diff --git a/.gitignore b/.gitignore index 86ddd1919b..5301a6e7f4 100644 --- a/.gitignore +++ b/.gitignore @@ -118,7 +118,6 @@ util/pmh7tool/pmh7tool util/runfw/googlesnow util/superiotool/superiotool util/vgabios/testbios -util/viatool/viatool util/autoport/autoport util/kbc1126/kbc1126_ec_dump util/kbc1126/kbc1126_ec_insert diff --git a/Documentation/util.md b/Documentation/util.md index 1a8f36db2b..feda972e90 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -126,8 +126,6 @@ operating system (only Linux at this time). `C` * __util_readme__ - Creates README.md of description files in `./util` subdirectories `Bash` * __vgabios__ - emulated vga driver for qemu `C` -* __viatool__ - Extract certain configuration bits on VIA chipsets and -CPUs. `C` * __x86__ - Generates 32-bit PAE page tables based on a CSV input file. `Go` * __xcompile__ - Cross compile setup `Bash` diff --git a/util/README.md b/util/README.md index 66438a9ce9..4656084ad7 100644 --- a/util/README.md +++ b/util/README.md @@ -119,8 +119,6 @@ operating system (only Linux at this time). `C` * __util_readme__ - Creates README.md of description files in `./util` subdirectories `Bash` * __vgabios__ - emulated vga driver for qemu `C` -* __viatool__ - Extract certain configuration bits on VIA chipsets and -CPUs. `C` * __x86__ - Generates 32-bit PAE page tables based on a CSV input file. `Go` * __xcompile__ - Cross compile setup `Bash` diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 8e3882f8a5..bf096d3565 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -66,8 +66,7 @@ futility \ inteltool \ intelvbttool \ nvramtool \ -superiotool \ -viatool +superiotool TEST_PAYLOADLIST_INTERNAL= \ coreinfo \ diff --git a/util/viatool/Makefile b/util/viatool/Makefile deleted file mode 100644 index f58cbd37fb..0000000000 --- a/util/viatool/Makefile +++ /dev/null @@ -1,103 +0,0 @@ -# -# Makefile for viatool utility -# -# Copyright (C) 2008 by coresystems GmbH -# written by Stefan Reinauer -# Copyright (C) 2013 Alexandru Gagniuc -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -PROGRAM = viatool - -CC ?= gcc -INSTALL ?= /usr/bin/env install -PREFIX ?= /usr/local -CFLAGS ?= -O2 -g -Wall -Wextra -I$(CURDIR) -LDFLAGS += -lpci -lz - -SRCS = viatool.c \ - cpu.c \ - quirks/quirks.c \ - quirks/vx900_quirks.c - -OBJS = $(sort ${SRCS:.c=.o}) - -OS_ARCH = $(shell uname) -ifeq ($(OS_ARCH), Darwin) -LDFLAGS += -framework DirectHW -endif -ifeq ($(OS_ARCH), FreeBSD) -CFLAGS += -I/usr/local/include -LDFLAGS += -L/usr/local/lib -LIBS = -lz -endif -ifeq ($(OS_ARCH), NetBSD) -CFLAGS += -I/usr/pkg/include -LDFLAGS += -L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib -lz -lpciutils -lpci -l$(shell uname -p) -endif - -all: pciutils dep $(PROGRAM) - -$(PROGRAM): $(OBJS) - $(CC) $(CFLAGS) -o $(PROGRAM) $(OBJS) $(LDFLAGS) - -clean: - # Remove build results - rm -f $(PROGRAM) $(OBJS) - # Remove backup files created by some editors - find ./ |grep *~ |xargs rm -f - rm -f junit.xml - -distclean: clean - rm -f .dependencies - -dep: - @$(CC) $(CFLAGS) -MM *.c > .dependencies - -define LIBPCI_TEST -/* Avoid a failing test due to libpci header symbol shadowing breakage */ -#define index shadow_workaround_index -#ifdef __NetBSD__ -#include -#else -#include -#endif -struct pci_access *pacc; -int main(int argc, char **argv) -{ - (void) argc; - (void) argv; - pacc = pci_alloc(); - return 0; -} -endef -export LIBPCI_TEST - -pciutils: - @printf "\nChecking for pciutils and zlib... " - @echo "$$LIBPCI_TEST" > .test.c - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ - printf "found.\n" || ( printf "not found.\n\n"; \ - printf "Please install pciutils-devel and zlib-devel.\n"; \ - printf "See README for more information.\n\n"; \ - rm -f .test.c .test; exit 1) - @rm -rf .test.c .test .test.dSYM - -install: $(PROGRAM) - mkdir -p $(DESTDIR)$(PREFIX)/sbin - $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin - mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 - -.PHONY: all clean distclean dep pciutils - --include .dependencies diff --git a/util/viatool/README b/util/viatool/README deleted file mode 100644 index 5a007be3db..0000000000 --- a/util/viatool/README +++ /dev/null @@ -1,12 +0,0 @@ -viatool is a utility for extracting useful for extracting certain configuration -bits on VIA chipsets and CPUs. It is a fork of inteltool. - -viatool is currently focused on "quirks". Quirks are device configurations that -cannot be accessed directly. They are implemented as hierarchical configurations -in the PCI or memory address spaces (index/data register pairs). Such -configurations refer to hardware parameters that are board specific. Those -parameters would otherwise be difficult to extract from a system running the -vendor's firmware. - -viatool also preserves inteltool's MSR dumps. VIA CPU and Intel CPU MSRs are -nearly identical. diff --git a/util/viatool/cpu.c b/util/viatool/cpu.c deleted file mode 100644 index cd3b40d605..0000000000 --- a/util/viatool/cpu.c +++ /dev/null @@ -1,1019 +0,0 @@ -/* - * inteltool - dump all registers on an Intel CPU + chipset based system. - * - * Copyright (C) 2008-2010 by coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "viatool.h" - -#ifdef __x86_64__ -# define BREG "%%rbx" -#else -# define BREG "%%ebx" -#endif - -int fd_msr; - -unsigned int cpuid(unsigned int op) -{ - uint32_t ret; - -#if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__) - asm volatile ( - "push " BREG "\n\t" - "cpuid\n\t" - "pop " BREG "\n\t" - : "=a" (ret) : "a" (op) : "%ecx", "%edx" - ); -#else - asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx"); -#endif - - return ret; -} - -#ifndef __DARWIN__ -int msr_readerror = 0; - -msr_t rdmsr(int addr) -{ - uint32_t buf[2]; - msr_t msr = { 0xffffffff, 0xffffffff }; - - if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { - perror("Could not lseek() to MSR"); - close(fd_msr); - exit(1); - } - - if (read(fd_msr, buf, 8) == 8) { - msr.lo = buf[0]; - msr.hi = buf[1]; - return msr; - } - - if (errno == 5) { - printf(" (*)"); // Not all bits of the MSR could be read - msr_readerror = 1; - } else { - // A severe error. - perror("Could not read() MSR"); - close(fd_msr); - exit(1); - } - - return msr; -} -#endif - -int print_intel_core_msrs(void) -{ - unsigned int i, core, id; - msr_t msr; - -#define IA32_PLATFORM_ID 0x0017 -#define EBL_CR_POWERON 0x002a -#define FSB_CLK_STS 0x00cd -#define IA32_TIME_STAMP_COUNTER 0x0010 -#define IA32_APIC_BASE 0x001b - - typedef struct { - int number; - char *name; - } msr_entry_t; - - /* Pentium III */ - static const msr_entry_t model67x_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x0033, "TEST_CTL" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x0088, "BBL_CR_D0" }, - { 0x0089, "BBL_CR_D1" }, - { 0x008a, "BBL_CR_D2" }, - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "PERFCTR0" }, - { 0x00c2, "PERFCTR1" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0116, "BBL_CR_ADDR" }, - { 0x0118, "BBL_CR_DECC" }, - { 0x0119, "BBL_CR_CTL" }, - //{ 0x011a, "BBL_CR_TRIG" }, - { 0x011b, "BBL_CR_BUSY" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x017b, "IA32_MCG_CTL" }, - { 0x0186, "IA32_PERF_EVNTSEL0" }, - { 0x0187, "IA32_PERF_EVNTSEL1" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x01db, "MSR_LASTBRANCHFROMIP" }, - { 0x01dc, "MSR_LASTBRANCHTOIP" }, - { 0x01dd, "MSR_LASTINTFROMIP" }, - { 0x01de, "MSR_LASTINTTOIP" }, - { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x0404, "IA32_MC1_CTL" }, - { 0x0405, "IA32_MC1_STATUS" }, - { 0x0406, "IA32_MC1_ADDR" }, - //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO - { 0x0408, "IA32_MC2_CTL" }, - { 0x0409, "IA32_MC2_STATUS" }, - { 0x040a, "IA32_MC2_ADDR" }, - //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - { 0x0410, "IA32_MC3_CTL" }, - { 0x0411, "IA32_MC3_STATUS" }, - { 0x0412, "IA32_MC3_ADDR" }, - //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO - }; - - /* VIA C3 Nehemiah */ - static const msr_entry_t model69x_global_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x00c1, "PERFCTR0" }, - { 0x00c2, "PERFCTR1" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0186, "EVNTSEL0" }, - { 0x0187, "EVNTSEL1" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x1107, "FCR" }, - { 0x1108, "FCR2" }, -// WRITE ONLY { 0x1109, "FCR3" }, - }; - - static const msr_entry_t model6bx_global_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x0033, "TEST_CTL" }, - { 0x003f, "THERM_DIODE_OFFSET" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "PERFCTR0" }, - { 0x00c2, "PERFCTR1" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; - - static const msr_entry_t model6ex_global_msrs[] = { - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x00cd, "FSB_CLOCK_STS" }, - { 0x00ce, "FSB_CLOCK_VCC" }, - { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, - { 0x00e3, "PMG_IO_BASE_ADDR" }, - { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, - { 0x00ee, "EXT_CONFIG" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0194, "CLOCK_FLEX_MAX" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01aa, "PIC_SENS_CFG" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; - - static const msr_entry_t model6ex_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x003f, "IA32_TEMPERATURE_OFFSET" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x015f, "DTS_CAL_CTRL" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "GV_THERM" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO - }; - - static const msr_entry_t model6fx_global_msrs[] = { - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x003f, "IA32_TEMPERATURE_OFFSET" }, - { 0x00a8, "EMTTM_CR_TABLE0" }, - { 0x00a9, "EMTTM_CR_TABLE1" }, - { 0x00aa, "EMTTM_CR_TABLE2" }, - { 0x00ab, "EMTTM_CR_TABLE3" }, - { 0x00ac, "EMTTM_CR_TABLE4" }, - { 0x00ad, "EMTTM_CR_TABLE5" }, - { 0x00cd, "FSB_CLOCK_STS" }, - { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, - { 0x00e3, "PMG_IO_BASE_ADDR" }, - { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, - { 0x00ee, "EXT_CONFIG" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0194, "CLOCK_FLEX_MAX" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01aa, "PIC_SENS_CFG" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; - - static const msr_entry_t model6fx_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00e1, "SMM_CST_MISC_INFO" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_THERM_CTL" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO - }; - - /* Pentium 4 and XEON */ - /* - * All MSRs per - * - * Intel 64 and IA-32 Architectures Software Developer's Manual - * Volume 3B: System Programming Guide, Part 2 - * - * Table B-5, B-7 - */ - static const msr_entry_t modelf2x_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - /* 0x6: Not available in model 2. */ - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, - { 0x002b, "MSR_EBC_SOFT_POWERON" }, - /* 0x2c: Not available in model 2. */ -// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - { 0x019c, "IA32_THERM_STATUS" }, - /* 0x19d: Not available in model 2. */ - { 0x01a0, "IA32_MISC_ENABLE" }, - /* 0x1a1: Not available in model 2. */ - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0300, "MSR_BPU_COUNTER0" }, - { 0x0301, "MSR_BPU_COUNTER1" }, - { 0x0302, "MSR_BPU_COUNTER2" }, - { 0x0303, "MSR_BPU_COUNTER3" }, - { 0x0304, "MSR_MS_COUNTER0" }, - { 0x0305, "MSR_MS_COUNTER1" }, - { 0x0306, "MSR_MS_COUNTER2" }, - { 0x0307, "MSR_MS_COUNTER3" }, - { 0x0308, "MSR_FLAME_COUNTER0" }, - { 0x0309, "MSR_FLAME_COUNTER1" }, - { 0x030a, "MSR_FLAME_COUNTER2" }, - { 0x030b, "MSR_FLAME_COUNTER3" }, - { 0x030c, "MSR_IQ_COUNTER0" }, - { 0x030d, "MSR_IQ_COUNTER1" }, - { 0x030e, "MSR_IQ_COUNTER2" }, - { 0x030f, "MSR_IQ_COUNTER3" }, - { 0x0310, "MSR_IQ_COUNTER4" }, - { 0x0311, "MSR_IQ_COUNTER5" }, - { 0x0360, "MSR_BPU_CCCR0" }, - { 0x0361, "MSR_BPU_CCCR1" }, - { 0x0362, "MSR_BPU_CCCR2" }, - { 0x0363, "MSR_BPU_CCCR3" }, - { 0x0364, "MSR_MS_CCCR0" }, - { 0x0365, "MSR_MS_CCCR1" }, - { 0x0366, "MSR_MS_CCCR2" }, - { 0x0367, "MSR_MS_CCCR3" }, - { 0x0368, "MSR_FLAME_CCCR0" }, - { 0x0369, "MSR_FLAME_CCCR1" }, - { 0x036a, "MSR_FLAME_CCCR2" }, - { 0x036b, "MSR_FLAME_CCCR3" }, - { 0x036c, "MSR_IQ_CCCR0" }, - { 0x036d, "MSR_IQ_CCCR1" }, - { 0x036e, "MSR_IQ_CCCR2" }, - { 0x036f, "MSR_IQ_CCCR3" }, - { 0x0370, "MSR_IQ_CCCR4" }, - { 0x0371, "MSR_IQ_CCCR5" }, - { 0x03a0, "MSR_BSU_ESCR0" }, - { 0x03a1, "MSR_BSU_ESCR1" }, - { 0x03a2, "MSR_FSB_ESCR0" }, - { 0x03a3, "MSR_FSB_ESCR1" }, - { 0x03a4, "MSR_FIRM_ESCR0" }, - { 0x03a5, "MSR_FIRM_ESCR1" }, - { 0x03a6, "MSR_FLAME_ESCR0" }, - { 0x03a7, "MSR_FLAME_ESCR1" }, - { 0x03a8, "MSR_DAC_ESCR0" }, - { 0x03a9, "MSR_DAC_ESCR1" }, - { 0x03aa, "MSR_MOB_ESCR0" }, - { 0x03ab, "MSR_MOB_ESCR1" }, - { 0x03ac, "MSR_PMH_ESCR0" }, - { 0x03ad, "MSR_PMH_ESCR1" }, - { 0x03ae, "MSR_SAAT_ESCR0" }, - { 0x03af, "MSR_SAAT_ESCR1" }, - { 0x03b0, "MSR_U2L_ESCR0" }, - { 0x03b1, "MSR_U2L_ESCR1" }, - { 0x03b2, "MSR_BPU_ESCR0" }, - { 0x03b3, "MSR_BPU_ESCR1" }, - { 0x03b4, "MSR_IS_ESCR0" }, - { 0x03b5, "MSR_BPU_ESCR1" }, - { 0x03b6, "MSR_ITLB_ESCR0" }, - { 0x03b7, "MSR_ITLB_ESCR1" }, - { 0x03b8, "MSR_CRU_ESCR0" }, - { 0x03b9, "MSR_CRU_ESCR1" }, - { 0x03ba, "MSR_IQ_ESCR0" }, - { 0x03bb, "MSR_IQ_ESCR1" }, - { 0x03bc, "MSR_RAT_ESCR0" }, - { 0x03bd, "MSR_RAT_ESCR1" }, - { 0x03be, "MSR_SSU_ESCR0" }, - { 0x03c0, "MSR_MS_ESCR0" }, - { 0x03c1, "MSR_MS_ESCR1" }, - { 0x03c2, "MSR_TBPU_ESCR0" }, - { 0x03c3, "MSR_TBPU_ESCR1" }, - { 0x03c4, "MSR_TC_ESCR0" }, - { 0x03c5, "MSR_TC_ESCR1" }, - { 0x03c8, "MSR_IX_ESCR0" }, - { 0x03c9, "MSR_IX_ESCR1" }, - { 0x03ca, "MSR_ALF_ESCR0" }, - { 0x03cb, "MSR_ALF_ESCR1" }, - { 0x03cc, "MSR_CRU_ESCR2" }, - { 0x03cd, "MSR_CRU_ESCR3" }, - { 0x03e0, "MSR_CRU_ESCR4" }, - { 0x03e1, "MSR_CRU_ESCR5" }, - { 0x03f0, "MSR_TC_PRECISE_EVENT" }, - { 0x03f1, "MSR_PEBS_ENABLE" }, - { 0x03f2, "MSR_PEBS_MATRIX_VERT" }, - - /* - * All MCX_ADDR and MCX_MISC MSRs depend on a bit being - * set in MCX_STATUS. - */ - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x403, "IA32_MC0_MISC" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x406, "IA32_MC1_ADDR" }, - { 0x407, "IA32_MC1_MISC" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x40b, "IA32_MC2_MISC" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x40f, "IA32_MC3_MISC" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - { 0x412, "IA32_MC4_ADDR" }, - { 0x413, "IA32_MC4_MISC" }, - }; - - static const msr_entry_t modelf2x_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - /* 0x3a: Not available in model 2. */ - { 0x008b, "IA32_BIOS_SIGN_ID" }, - /* 0x9b: Not available in model 2. */ - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x017b, "IA32_MCG_CTL" }, - { 0x0180, "MSR_MCG_RAX" }, - { 0x0181, "MSR_MCG_RBX" }, - { 0x0182, "MSR_MCG_RCX" }, - { 0x0183, "MSR_MCG_RDX" }, - { 0x0184, "MSR_MCG_RSI" }, - { 0x0185, "MSR_MCG_RDI" }, - { 0x0186, "MSR_MCG_RBP" }, - { 0x0187, "MSR_MCG_RSP" }, - { 0x0188, "MSR_MCG_RFLAGS" }, - { 0x0189, "MSR_MCG_RIP" }, - { 0x018a, "MSR_MCG_MISC" }, - /* 0x18b-0x18f: Reserved */ - { 0x0190, "MSR_MCG_R8" }, - { 0x0191, "MSR_MCG_R9" }, - { 0x0192, "MSR_MCG_R10" }, - { 0x0193, "MSR_MCG_R11" }, - { 0x0194, "MSR_MCG_R12" }, - { 0x0195, "MSR_MCG_R13" }, - { 0x0196, "MSR_MCG_R14" }, - { 0x0197, "MSR_MCG_R15" }, - /* 0x198: Not available in model 2. */ - /* 0x199: Not available in model 2. */ - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x01a0, "IA32_MISC_ENABLE" }, - { 0x01d7, "MSR_LER_FROM_LIP" }, - { 0x01d8, "MSR_LER_TO_LIP" }, - { 0x01d9, "MSR_DEBUGCTLA" }, - { 0x01da, "MSR_LASTBRANCH_TOS" }, - { 0x01db, "MSR_LASTBRANCH_0" }, - { 0x01dd, "MSR_LASTBRANCH_2" }, - { 0x01de, "MSR_LASTBRANCH_3" }, - { 0x0277, "IA32_PAT" }, - /* 0x480-0x48b : Not available in model 2. */ - { 0x0600, "IA32_DS_AREA" }, - /* 0x0680 - 0x06cf Branch Records Skipped */ - }; - - static const msr_entry_t modelf4x_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, - { 0x002b, "MSR_EBC_SOFT_POWERON" }, - { 0x002c, "MSR_EBC_FREQUENCY_ID" }, -// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x01a0, "IA32_MISC_ENABLE" }, - { 0x01a1, "MSR_PLATFORM_BRV" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0300, "MSR_BPU_COUNTER0" }, - { 0x0301, "MSR_BPU_COUNTER1" }, - { 0x0302, "MSR_BPU_COUNTER2" }, - { 0x0303, "MSR_BPU_COUNTER3" }, - /* Skipped through 0x3ff for now*/ - - /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being - * set in MCX_STATUS */ - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x403, "IA32_MC0_MISC" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x406, "IA32_MC1_ADDR" }, - { 0x407, "IA32_MC1_MISC" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x40b, "IA32_MC2_MISC" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x40f, "IA32_MC3_MISC" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - { 0x412, "IA32_MC4_ADDR" }, - { 0x413, "IA32_MC4_MISC" }, - }; - - static const msr_entry_t modelf4x_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x009b, "IA32_SMM_MONITOR_CTL" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0180, "MSR_MCG_RAX" }, - { 0x0181, "MSR_MCG_RBX" }, - { 0x0182, "MSR_MCG_RCX" }, - { 0x0183, "MSR_MCG_RDX" }, - { 0x0184, "MSR_MCG_RSI" }, - { 0x0185, "MSR_MCG_RDI" }, - { 0x0186, "MSR_MCG_RBP" }, - { 0x0187, "MSR_MCG_RSP" }, - { 0x0188, "MSR_MCG_RFLAGS" }, - { 0x0189, "MSR_MCG_RIP" }, - { 0x018a, "MSR_MCG_MISC" }, - // 0x18b-f Reserved - { 0x0190, "MSR_MCG_R8" }, - { 0x0191, "MSR_MCG_R9" }, - { 0x0192, "MSR_MCG_R10" }, - { 0x0193, "MSR_MCG_R11" }, - { 0x0194, "MSR_MCG_R12" }, - { 0x0195, "MSR_MCG_R13" }, - { 0x0196, "MSR_MCG_R14" }, - { 0x0197, "MSR_MCG_R15" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x0199, "IA32_PERF_CTL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific - { 0x01d7, "MSR_LER_FROM_LIP" }, - { 0x01d8, "MSR_LER_TO_LIP" }, - { 0x01d9, "MSR_DEBUGCTLA" }, - { 0x01da, "MSR_LASTBRANCH_TOS" }, - { 0x0277, "IA32_PAT" }, - /** Virtualization - { 0x480, "IA32_VMX_BASIC" }, - through - { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, - Not implemented in my CPU - */ - { 0x0600, "IA32_DS_AREA" }, - /* 0x0680 - 0x06cf Branch Records Skipped */ - - }; - - /* Atom N455 - * - * This should apply to the following processors: - * 06_1CH - * 06_26H - * 06_27H - * 06_35 - * 06_36 - */ - /* - * All MSRs per - * - * Intel 64 and IA-32 Architectures Software Developer's Manual - * Volume 3C: System Programming Guide, Part 3 - * Order Number 326019 - * January 2013 - * - * Table 35-4, 35-5 - * - * For now it has only been tested with 06_1CH. - */ - static const msr_entry_t model6_atom_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, - { 0x00cd, "MSR_FSB_FREQ" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x011e, "MSR_BBL_CR_CTL3" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x0345, "IA32_PERF_CAPABILITIES" }, - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - { 0x412, "IA32_MC4_ADDR" }, - /* - * Only 06_27C has the following MSRs - */ - /* - { 0x03f8, "MSR_PKG_C2_RESIDENCY" }, - { 0x03f9, "MSR_PKG_C4_RESIDENCY" }, - { 0x03fa, "MSR_PKG_C6_RESIDENCY" }, - */ - }; - - static const msr_entry_t model6_atom_per_core_msrs[] = { - { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, - { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, - { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, - { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, - { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, - { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, - { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, - { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, - { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, - { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, - { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, - { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, - { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, - { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, - { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, - { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, - /* Write register */ - /* - { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - */ - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "IA32_PMC0" }, - { 0x00c2, "IA32_PMC1" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0186, "IA32_PERF_EVNTSEL0" }, - { 0x0187, "IA32_PERF_EVNTSEL1" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01c9, "MSR_LASTBRANCH_TOS" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x01dd, "MSR_LER_FROM_LIP" }, - { 0x01de, "MSR_LER_TO_LIP" }, - { 0x0277, "IA32_PAT" }, - { 0x0309, "IA32_FIXED_CTR0" }, - { 0x030a, "IA32_FIXED_CTR1" }, - { 0x030b, "IA32_FIXED_CTR2" }, - { 0x038d, "IA32_FIXED_CTR_CTRL" }, - { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, - { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, - { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, - { 0x03f1, "MSR_PEBS_ENABLE" }, - { 0x0480, "IA32_VMX_BASIC" }, - { 0x0481, "IA32_VMX_PINBASED_CTLS" }, - { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, - { 0x0483, "IA32_VMX_EXIT_CTLS" }, - { 0x0484, "IA32_VMX_ENTRY_CTLS" }, - { 0x0485, "IA32_VMX_MISC" }, - { 0x0486, "IA32_VMX_CR0_FIXED0" }, - { 0x0487, "IA32_VMX_CR0_FIXED1" }, - { 0x0488, "IA32_VMX_CR4_FIXED0" }, - { 0x0489, "IA32_VMX_CR4_FIXED1" }, - { 0x048a, "IA32_VMX_VMCS_ENUM" }, - { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, - { 0x0600, "IA32_DS_AREA" }, - }; - - typedef struct { - unsigned int model; - const msr_entry_t *global_msrs; - unsigned int num_global_msrs; - const msr_entry_t *per_core_msrs; - unsigned int num_per_core_msrs; - } cpu_t; - - cpu_t cpulist[] = { - { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 }, - { 0x00690, model69x_global_msrs, ARRAY_SIZE(model69x_global_msrs), NULL, 0 }, - { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, - { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, - { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, - { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, - { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, - { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, - }; - - cpu_t *cpu = NULL; - - /* Get CPU family and model, not the stepping - * (TODO: extended family/model) - */ - id = cpuid(1) & 0xfffff0; - for (i = 0; i < ARRAY_SIZE(cpulist); i++) { - if(cpulist[i].model == id) { - cpu = &cpulist[i]; - break; - } - } - - if (!cpu) { - printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id); - return -1; - } - -#ifndef __DARWIN__ - fd_msr = open("/dev/cpu/0/msr", O_RDWR); - if (fd_msr < 0) { - perror("Error while opening /dev/cpu/0/msr"); - printf("Did you run 'modprobe msr'?\n"); - return -1; - } -#endif - - printf("\n===================== SHARED MSRs (All Cores) =====================\n"); - - for (i = 0; i < cpu->num_global_msrs; i++) { - msr = rdmsr(cpu->global_msrs[i].number); - printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", - cpu->global_msrs[i].number, msr.hi, msr.lo, - cpu->global_msrs[i].name); - } - - close(fd_msr); - - for (core = 0; core < 8; core++) { -#ifndef __DARWIN__ - char msrfilename[64]; - memset(msrfilename, 0, 64); - sprintf(msrfilename, "/dev/cpu/%u/msr", core); - - fd_msr = open(msrfilename, O_RDWR); - - /* If the file is not there, we're probably through. No error, - * since we successfully opened /dev/cpu/0/msr before. - */ - if (fd_msr < 0) - break; -#endif - if (cpu->num_per_core_msrs) - printf("\n====================== UNIQUE MSRs (core %u) ======================\n", core); - - for (i = 0; i < cpu->num_per_core_msrs; i++) { - msr = rdmsr(cpu->per_core_msrs[i].number); - printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", - cpu->per_core_msrs[i].number, msr.hi, msr.lo, - cpu->per_core_msrs[i].name); - } -#ifndef __DARWIN__ - close(fd_msr); -#endif - } - -#ifndef __DARWIN__ - if (msr_readerror) - printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); -#endif - return 0; -} diff --git a/util/viatool/description.md b/util/viatool/description.md deleted file mode 100644 index 7eb8928105..0000000000 --- a/util/viatool/description.md +++ /dev/null @@ -1 +0,0 @@ -Extract certain configuration bits on VIA chipsets and CPUs. `C` diff --git a/util/viatool/quirks/quirks.c b/util/viatool/quirks/quirks.c deleted file mode 100644 index 4721461cee..0000000000 --- a/util/viatool/quirks/quirks.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * viatool - dump all registers on a VIA CPU + chipset based system. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "quirks.h" -#include -#include -#include - -extern struct quirk_list vx900_sb_quirk_list; - -struct quirk_list *sb_quirks[] = { - &vx900_sb_quirk_list, - 0, -}; - -struct quirk_list *nb_quirks[] = { - 0, -}; - -int print_quirks(struct pci_dev *sb, struct pci_access *pacc, - struct quirk_list **qlists); - -int print_quirks_north(struct pci_dev *nb, struct pci_access *pacc) -{ - printf("\n====== Northbridge Quirks =======\n\n"); - return print_quirks(nb, pacc, nb_quirks); -} - -int print_quirks_south(struct pci_dev *sb, struct pci_access *pacc) -{ - printf("\n====== Southbridge Quirks =======\n\n"); - return print_quirks(sb, pacc, sb_quirks); -} - -int print_quirks(struct pci_dev *sb, struct pci_access *pacc, - struct quirk_list **qlists) -{ - size_t i, j; - struct quirk *q; - struct quirk_list *qlist; - struct pci_dev *dev; - - for (i = 0; ; i++) - { - qlist = qlists[i]; - - if (qlist == NULL) { - /* OOPS. We've tried all we know, but no quirk */ - printf("No quirks supported.\n"); - break; - } - - /* Is this the right device ? */ - if ( (qlist->pci_vendor_id != sb->vendor_id) || - qlist->pci_device_id != sb->device_id) - continue; - - for (j = 0; ; j++) - { - q = &qlist->dev_quirks[j]; - - if(q->pci_device_id == 0) - break; - - printf("Probing PCI device %i:%.2x.%i\n", - q->pci_bus, q->pci_dev, q->pci_func); - - dev = pci_get_dev(pacc, q->pci_domain, q->pci_bus, - q->pci_dev, q->pci_func); - - if (!dev) { - perror("Error: no device found\n"); - continue; - } - - pci_fill_info(dev, PCI_FILL_IDENT | - PCI_FILL_BASES | - PCI_FILL_SIZES | - PCI_FILL_CLASS ); - - if (dev->device_id != q->pci_device_id) { - printf("Expected %.4x:%.4x, got %.4x:%.4x\n", - q->pci_vendor_id, q->pci_device_id, - dev->vendor_id, dev->device_id); - continue; - } - - if (!q->quirk_func) { - perror("BUG: Quirk missing.\n"); - continue; - } - - q->quirk_func(dev); - /* On to next quirk */ - } - - /* Done. No need to go through the remainder of the list */ - break; - } - - return 0; -} diff --git a/util/viatool/quirks/quirks.h b/util/viatool/quirks/quirks.h deleted file mode 100644 index 8a3f58d351..0000000000 --- a/util/viatool/quirks/quirks.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * viatool - dump all registers on a VIA CPU + chipset based system. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -struct quirk { - int pci_domain; - int pci_bus; - int pci_dev; - int pci_func; - int pci_vendor_id; - int pci_device_id; - int (*quirk_func)(struct pci_dev *dev); -}; - -struct quirk_list { - int pci_vendor_id; - int pci_device_id; - /* NULL-terminated list of quirks */ - struct quirk *dev_quirks; -}; diff --git a/util/viatool/quirks/vx900_quirks.c b/util/viatool/quirks/vx900_quirks.c deleted file mode 100644 index e4f3e2b85b..0000000000 --- a/util/viatool/quirks/vx900_quirks.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * viatool - dump all registers on a VIA CPU + chipset based system. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "quirks.h" - -#include - -typedef u8 sata_phy_config[64]; - -static u32 sata_phy_read32(struct pci_dev *dev, u8 index) -{ - /* The SATA PHY control registers are accessed by a funny index/value - * scheme. Each byte (0,1,2,3) has its own 4-bit index */ - index = (index >> 2) & 0xf; - u16 i16 = index | (index << 4) | (index << 8)| (index << 12); - /* The index */ - pci_write_word(dev, 0x68, i16); - /* The value */ - return pci_read_long(dev, 0x64); -} - -static void vx900_sata_read_phy_config(struct pci_dev *dev, sata_phy_config cfg) -{ - size_t i; - u32* data = (u32*)cfg; - for (i = 0; i < ( sizeof(sata_phy_config) ) >> 2; i++) { - data[i] = sata_phy_read32(dev, i<<2); - } -} - -static int quirk_vx900_sata(struct pci_dev *dev) -{ - sata_phy_config ephy; - - /* Get all the info in one pass */ - vx900_sata_read_phy_config(dev, ephy); - - /* Put it on the terminal for the user to read and be done with it */ - printf("SATA PHY config:\n"); - unsigned int i; - for (i = 0; i < sizeof(sata_phy_config); i++) { - if ((i & 0x0f) == 0) { - printf("%.2x :", i); - } - if( (i & 0x0f) == 0x08 ) - printf("| "); - printf("%.2x ", ephy[i]); - if ((i & 0x0f) == 0x0f) { - printf("\n"); - } - } - return 0; -} - - - - -static struct quirk vx900_sb_quirks[] = { - {0, 0, 0x0f, 0, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_SATA, - quirk_vx900_sata }, - {0, 0, 0, 0, 0, 0, 0}, -}; - -struct quirk_list vx900_sb_quirk_list = { - .pci_vendor_id = PCI_VENDOR_ID_VIA, - .pci_device_id = PCI_DEVICE_ID_VIA_VX900_LPC, - .dev_quirks = vx900_sb_quirks -}; diff --git a/util/viatool/viatool.c b/util/viatool/viatool.c deleted file mode 100644 index 328377ac09..0000000000 --- a/util/viatool/viatool.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * viatool - dump all registers on an Intel CPU + chipset based system. - * - * Copyright (C) 2008-2010 by coresystems GmbH - * written by Stefan Reinauer - * Copyright (C) 2009 Carl-Daniel Hailfinger - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "viatool.h" - -#ifdef __NetBSD__ -#include -#endif - -/* - * http://pci-ids.ucw.cz/read/PC/8086 - * http://en.wikipedia.org/wiki/Intel_Tick-Tock - * http://en.wikipedia.org/wiki/List_of_Intel_chipsets - * http://en.wikipedia.org/wiki/Intel_Xeon_chipsets - */ -static const struct { - uint16_t vendor_id, device_id; - char *name; -} supported_chips_list[] = { - { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_SATA, "VX900 SATA"}, - /* Host bridges/DRAM controllers (Northbridges) */ - { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900, "VX900"}, - /* Southbridges (LPC controllers) */ - { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_LPC, "VX900" }, -}; - -#ifndef __DARWIN__ -static int fd_mem; - -void *map_physical(uint64_t phys_addr, size_t len) -{ - void *virt_addr; - - virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) phys_addr); - - if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n", - phys_addr, len); - return NULL; - } - - return virt_addr; -} - -void unmap_physical(void *virt_addr, size_t len) -{ - munmap(virt_addr, len); -} -#endif - -void print_version(void) -{ - printf("inteltool v%s -- ", VIATOOL_VERSION); - printf("Copyright (C) 2013 Alexandru Gagniuc\n\n"); - printf( - "This program is free software: you can redistribute it and/or modify\n" - "it under the terms of the GNU General Public License as published by\n" - "the Free Software Foundation, version 2 of the License.\n\n" - "This program is distributed in the hope that it will be useful,\n" - "but WITHOUT ANY WARRANTY; without even the implied warranty of\n" - "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n" - "GNU General Public License for more details.\n\n"); -} - -void print_usage(const char *name) -{ - printf("usage: %s [-vh?gGrpmedPMa]\n", name); - printf("\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" - " -M | --msrs: dump CPU MSRs\n" - " -a | --all: dump all known registers\n" - " -q | --quirks: dump hierarchical configs\n" - "\n"); - exit(1); -} - -int main(int argc, char *argv[]) -{ - struct pci_access *pacc; - struct pci_dev *sb = NULL, *nb, *dev; - int i, opt, option_index = 0; - unsigned int id; - - char *sbname = "unknown", *nbname = "unknown"; - - int dump_coremsrs = 0, dump_quirks = 0; - - static struct option long_options[] = { - {"version", 0, 0, 'v'}, - {"help", 0, 0, 'h'}, - {"mchbar", 0, 0, 'm'}, - {"msrs", 0, 0, 'M'}, - {"quirks", 0, 0, 'q'}, - {"all", 0, 0, 'a'}, - {0, 0, 0, 0} - }; - - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaA", - long_options, &option_index)) != EOF) { - switch (opt) { - case 'v': - print_version(); - exit(0); - break; - case 'M': - dump_coremsrs = 1; - break; - case 'q': - dump_quirks = 1; - break; - case 'a': - dump_coremsrs = 1; - dump_quirks = 1; - break; - case 'h': - case '?': - default: - print_usage(argv[0]); - exit(0); - break; - } - } - -#if defined(__FreeBSD__) - if (open("/dev/io", O_RDWR) < 0) { - perror("/dev/io"); -#elif defined(__NetBSD__) -# ifdef __i386__ - if (i386_iopl(3)) { - perror("iopl"); -# else - if (x86_64_iopl(3)) { - perror("iopl"); -# endif -#else - if (iopl(3)) { - perror("iopl"); -#endif - printf("You need to be root.\n"); - exit(1); - } - -#ifndef __DARWIN__ - if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { - perror("Can not open /dev/mem"); - exit(1); - } -#endif - - pacc = pci_alloc(); - pci_init(pacc); - pci_scan_bus(pacc); - - /* Find the required devices */ - for (dev = pacc->devices; dev; dev = dev->next) { - pci_fill_info(dev, PCI_FILL_CLASS); - /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */ - if (dev->device_class == 0x0601) { /* ISA/LPC bridge */ - if (sb == NULL) - sb = dev; - else - fprintf(stderr, "Multiple devices with class ID" - " 0x0601, using %02x%02x:%02x.%02x\n", - dev->domain, dev->bus, dev->dev, - dev->func); - } - } - - if (!sb) { - printf("No southbridge found.\n"); - exit(1); - } - - pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); - - if (sb->vendor_id != PCI_VENDOR_ID_VIA) { - printf("Not a VIA southbridge.\n"); - exit(1); - } - - nb = pci_get_dev(pacc, 0, 0, 0x00, 0); - if (!nb) { - printf("No northbridge found.\n"); - exit(1); - } - - pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); - - if (nb->vendor_id != PCI_VENDOR_ID_VIA) { - printf("Not a VIA northbridge.\n"); - exit(1); - } - - id = cpuid(1); - - /* Intel has suggested applications to display the family of a CPU as - * the sum of the "Family" and the "Extended Family" fields shown - * above, and the model as the sum of the "Model" and the 4-bit - * left-shifted "Extended Model" fields. - * http://download.intel.com/design/processor/applnots/24161832.pdf - */ - printf("CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", - (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), - ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); - - /* Determine names */ - for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) - if (nb->device_id == supported_chips_list[i].device_id) - nbname = supported_chips_list[i].name; - for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) - if (sb->device_id == supported_chips_list[i].device_id) - sbname = supported_chips_list[i].name; - - printf("Northbridge: %04x:%04x (%s)\n", - nb->vendor_id, nb->device_id, nbname); - - printf("Southbridge: %04x:%04x (%s)\n", - sb->vendor_id, sb->device_id, sbname); - - /* Now do the deed */ - - if (dump_coremsrs) { - print_intel_core_msrs(); - printf("\n\n"); - } - - if (dump_quirks) { - print_quirks_north(nb, pacc); - print_quirks_south(sb, pacc); - } - - /* Clean up */ - pci_free_dev(nb); - // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" - pci_cleanup(pacc); - - return 0; -} diff --git a/util/viatool/viatool.h b/util/viatool/viatool.h deleted file mode 100644 index a95547a169..0000000000 --- a/util/viatool/viatool.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * viatool - dump all registers on an Intel CPU + chipset based system. - * - * Copyright (C) 2008-2010 by coresystems GmbH - * Copyright (C) 2009 Carl-Daniel Hailfinger - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#ifndef _VIATOOL_H -#define _VIATOOL_H - -#if defined(__GLIBC__) -#include -#endif -#if (defined(__MACH__) && defined(__APPLE__)) -/* DirectHW is available here: https://www.coreboot.org/DirectHW */ -#define __DARWIN__ -#include -#endif -#ifdef __NetBSD__ -#include -#else -#include -#endif - -/* This #include is needed for freebsd_{rd,wr}msr. */ -#if defined(__FreeBSD__) -#include -#endif - -#ifdef __NetBSD__ -static inline uint8_t inb(unsigned port) -{ - uint8_t data; - __asm volatile("inb %w1,%0" : "=a" (data) : "d" (port)); - return data; -} -static inline uint16_t inw(unsigned port) -{ - uint16_t data; - __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); - return data; -} -static inline uint32_t inl(unsigned port) -{ - uint32_t data; - __asm volatile("inl %w1,%0": "=a" (data) : "d" (port)); - return data; -} -#endif - -#include - -#define VIATOOL_VERSION "1.0" - -/* Tested chipsets: */ -#define PCI_VENDOR_ID_VIA 0x1106 -#define PCI_DEVICE_ID_VIA_VX900 0x0410 -#define PCI_DEVICE_ID_VIA_VX900_SATA 0x9001 -#define PCI_DEVICE_ID_VIA_VX900_LPC 0x8410 - - -#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) - -#if !defined(__DARWIN__) && !defined(__FreeBSD__) -typedef struct { uint32_t hi, lo; } msr_t; -#endif -#if defined (__FreeBSD__) -/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ -#undef rdmsr -#undef wrmsr -#define rdmsr freebsd_rdmsr -#define wrmsr freebsd_wrmsr -typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); -int freebsd_wrmsr(int addr, msr_t msr); -#endif -typedef struct { uint16_t addr; int size; char *name; } io_register_t; - -void *map_physical(uint64_t phys_addr, size_t len); -void unmap_physical(void *virt_addr, size_t len); - -unsigned int cpuid(unsigned int op); -int print_intel_core_msrs(void); -int print_quirks_north(struct pci_dev *nb, struct pci_access *pacc); -int print_quirks_south(struct pci_dev *sb, struct pci_access *pacc); - -#endif /* _VIATOOL_H */ From 7325ac57408edfa759bcb084744421fc4d9dfc92 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 16 Feb 2020 11:47:52 +0100 Subject: [PATCH 0253/1463] Makefile: Explicitly silence sub-makes GNU Make 4.3 doesn't propagate a global .SILENT to sub-processes anymore. Let's make it explicit to maintain the behaviour we are used to. From the changelog: [SV 54740] Ensure .SILENT settings do not leak into sub-makes Change-Id: I3de51c245d3344b062dc0fe9c62b8d5c0ac5e67d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38931 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 41a9b3afa4..3f60493314 100644 --- a/Makefile +++ b/Makefile @@ -82,6 +82,7 @@ Q:=@ ifneq ($(V),1) ifneq ($(Q),) .SILENT: +MAKEFLAGS += -s endif endif From e7dd38040228eaf6f894456516aa7a55057a9d07 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Nov 2019 12:09:33 +0100 Subject: [PATCH 0254/1463] nb/intel/nehalem: Use cache.h functions Some local functions need renaming to avoid name collision. Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37195 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/nehalem/raminit.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 7735522da9..de02882483 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -96,12 +97,6 @@ struct ram_training { #include /* Prototypes */ - -static void clflush(u32 addr) -{ - asm volatile ("clflush (%0)"::"r" (addr)); -} - typedef struct _u128 { u64 lo; u64 hi; @@ -1956,7 +1951,7 @@ static u32 get_etalon2(int flip, u32 addr) return ret; } -static void disable_cache(void) +static void disable_cache_region(void) { msr_t msr = {.lo = 0, .hi = 0 }; @@ -1964,7 +1959,7 @@ static void disable_cache(void) wrmsr(MTRR_PHYS_MASK(3), msr); } -static void enable_cache(unsigned int base, unsigned int size) +static void enable_cache_region(unsigned int base, unsigned int size) { msr_t msr; msr.lo = base | MTRR_TYPE_WRPROT; @@ -1983,7 +1978,7 @@ static void flush_cache(u32 start, u32 size) end = start + (ALIGN_DOWN(size + 4096, 4096)); for (addr = start; addr < end; addr += 64) - clflush(addr); + clflush((void *)addr); } static void clear_errors(void) @@ -2019,7 +2014,7 @@ static u8 check_testing(struct raminfo *info, u8 total_rank, int flip) int comp1, comp2, comp3; u32 failxor[2] = { 0, 0 }; - enable_cache((total_rank << 28), 1728 * 5 * 4); + enable_cache_region((total_rank << 28), 1728 * 5 * 4); for (comp3 = 0; comp3 < 9 && failmask != 0xff; comp3++) { for (comp1 = 0; comp1 < 4; comp1++) @@ -2042,7 +2037,7 @@ static u8 check_testing(struct raminfo *info, u8 total_rank, int flip) if ((0xff << (8 * (i % 4))) & failxor[i / 4]) failmask |= 1 << i; } - disable_cache(); + disable_cache_region(); flush_cache((total_rank << 28), 1728 * 5 * 4); return failmask; } @@ -2132,7 +2127,7 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block, failxor[0] = 0; failxor[1] = 0; - enable_cache(totalrank << 28, 134217728); + enable_cache_region(totalrank << 28, 134217728); for (comp3 = 0; comp3 < 2 && failmask != 0xff; comp3++) { for (comp1 = 0; comp1 < 16; comp1++) for (comp2 = 0; comp2 < 64; comp2++) { @@ -2148,7 +2143,7 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block, if ((0xff << (8 * (i % 4))) & failxor[i / 4]) failmask |= 1 << i; } - disable_cache(); + disable_cache_region(); flush_cache((totalrank << 28) | (region << 25) | (block << 16), 16384); return failmask; } From 257cc4f9c3168472f5db13154fae2ee50c4160f9 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Tue, 3 Dec 2019 21:34:07 +0100 Subject: [PATCH 0255/1463] mb/lenovo/t530/*/*/devicetree: Align whitespace and comments across the boards Only whitespace changes, minor comments. This helps making diff between devicetrees shorter. Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37601 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../lenovo/t530/variants/t530/devicetree.cb | 24 +++-- .../lenovo/t530/variants/w530/devicetree.cb | 96 +++++++++++-------- 2 files changed, 66 insertions(+), 54 deletions(-) diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 47e40c3790..674b0f8c02 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -39,9 +39,9 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x17aa 0x21f6 inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "2" register "gpi13_routing" = "2" - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" @@ -69,7 +68,7 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x4000201" + register "xhci_overcurrent_mapping" = "0x04000201" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" @@ -86,9 +85,9 @@ chip northbridge/intel/sandybridge device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on + device pci 1c.2 on # PCIe Port #3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #3 (expresscard) + end device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 @@ -96,10 +95,9 @@ chip northbridge/intel/sandybridge device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device pci 1f.0 on # PCI-LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -162,9 +160,9 @@ chip northbridge/intel/sandybridge register "has_thinker1" = "1" end - end # LPC bridge + end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device pci 1f.3 on # SMBus # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -176,7 +174,7 @@ chip northbridge/intel/sandybridge device i2c 5e on end device i2c 5f on end end - end # SMBus + end device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 on end # Thermal end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 135627f702..da5a094b11 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -14,31 +14,40 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0x0 on - chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + device cpu_cluster 0 on + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip device lapic 0x0 on end device lapic 0xacac off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) end end register "pci_mmio_size" = "2048" - device domain 0x0 on + device domain 0 on subsystemid 0x17aa 0x21f6 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f5 + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) @@ -48,20 +57,29 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "c2_latency" = "0x0065" - register "docking_supported" = "1" - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen4_dec" = "0x000c06a1" - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" - register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x04000201" + + register "docking_supported" = "1" + register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x04000201" - register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -71,7 +89,7 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21f3 end device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x83" @@ -90,11 +108,11 @@ chip northbridge/intel/sandybridge device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # PCI-LPC bridge chip ec/lenovo/pmh7 + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on end # dummy end chip drivers/pc80/tpm @@ -102,14 +120,23 @@ chip northbridge/intel/sandybridge end chip ec/lenovo/h8 - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end register "config0" = "0xa7" register "config1" = "0x01" register "config2" = "0xa0" register "config3" = "0xe2" + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xd0" @@ -124,18 +151,9 @@ chip northbridge/intel/sandybridge register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" - register "has_keyboard_backlight" = "1" - register "has_power_management_beeps" = "0" register "has_bdc_detection" = "1" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" - - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end end chip drivers/lenovo/hybrid_graphics device pnp ff.f on end # dummy @@ -154,7 +172,8 @@ chip northbridge/intel/sandybridge end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end device i2c 56 on end @@ -168,10 +187,5 @@ chip northbridge/intel/sandybridge device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f5 - end end end From c46dd3954153414b1e211456cf18b8b181b0f80c Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Tue, 4 Feb 2020 14:45:33 +0100 Subject: [PATCH 0256/1463] mb/lenovo/[tw]530/devicetree: Fix comment about chip codename Change-Id: I3323e713970041b0665ca17bbcad985cba600687 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38708 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/lenovo/t530/variants/t530/devicetree.cb | 2 +- src/mainboard/lenovo/t530/variants/w530/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 674b0f8c02..c5eb02fe62 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -43,7 +43,7 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # PCIe bridge for discrete graphics device pci 02.0 on end # Internal graphics VGA controller - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index da5a094b11..c2e32e3a05 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -48,7 +48,7 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21f5 end - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) From 8d5c17389a06cbf6900f97892b5fb327a23bb85f Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Tue, 4 Feb 2020 14:48:14 +0100 Subject: [PATCH 0257/1463] mb/lenovo/t530/devicetree: Drop unnecessary initialization These two variables are initialized to zero by default. Change-Id: I590f601b5297a9bfa93607442d7e0b8d79f1ab51 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38709 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/lenovo/t530/variants/w530/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index c2e32e3a05..17b0b41a10 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/sandybridge # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" - register "gpu_dp_b_hotplug" = "0" - register "gpu_dp_c_hotplug" = "0" - # Enable Panel as LVDS and configure power delays register "gpu_panel_port_select" = "0" # LVDS register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms From 9364afd3c05da261a097fe6821c913bacc88ea44 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Tue, 4 Feb 2020 14:53:18 +0100 Subject: [PATCH 0258/1463] mb/lenovo/t530/devicetree: Select docking_supported Looks like it should select it like any other Lenovo xx20/xx30 boards around. UNTESTED. Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38710 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/lenovo/t530/variants/t530/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index c5eb02fe62..09fb3cdb59 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -70,6 +70,8 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x04000201" + register "docking_supported" = "1" + register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" From b5b5490bbdc18f44854608baf5c97137c8724656 Mon Sep 17 00:00:00 2001 From: Prasun Gera Date: Mon, 16 Sep 2019 04:16:49 -0400 Subject: [PATCH 0259/1463] src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPU Both T530 and W530 share the same PCI device id of 0166 for the iGPU. Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a Signed-off-by: Prasun Gera Reviewed-on: https://review.coreboot.org/c/coreboot/+/35431 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: Patrick Georgi --- src/mainboard/lenovo/t530/Kconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index d1ba6a8fd0..04b752804c 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -60,7 +60,10 @@ config DRAM_RESET_GATE_GPIO config VGA_BIOS_FILE string - default "pci8086,0106.rom" if BOARD_LENOVO_T530 - default "pci8086,0166.rom" if BOARD_LENOVO_W530 + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" endif From b753006f38976f8735864251e941b9aa2f774f54 Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Tue, 21 Jan 2020 02:30:04 -0700 Subject: [PATCH 0260/1463] vc/amd/agesa/[...]/Proc/Mem: Delete unused function The generic MemNProgramNbPstateDependentRegistersUnb function is unused, and generates a Coverity warning of an unused switch case. Only family specific versions of this function are called elsewhere. Delete unused function. Change-Id: I2afc83861f4b3a13bfc1eef4920cd3023e608e94 Signed-off-by: Joe Moore Found-by: Coverity CID 1241810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38493 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- .../amd/agesa/f14/Proc/Mem/NB/mndct.c | 56 ------------------- src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h | 5 -- .../amd/agesa/f15tn/Proc/Mem/NB/mndct.c | 49 ---------------- src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h | 5 -- 4 files changed, 115 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c index 00024e2fa4..724202b663 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c @@ -1933,62 +1933,6 @@ MemNChangeFrequencyUnb ( } } - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 RdPtrInit; - UINT8 Dct; - - RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 5; - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - switch (RdPtrInit) { - case 4: - if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2); - } else { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - } - break; - case 5: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - break; - case 6: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); - break; - default: - ASSERT (FALSE); - } - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // Set ProcOdtAdv - if (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000); - } - } - } - - NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); -} - /* -----------------------------------------------------------------------------*/ CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h index e25c9389f0..a17906a448 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h @@ -1185,11 +1185,6 @@ MemNChangeFrequencyUnb ( IN OUT MEM_NB_BLOCK *NBPtr ); -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - VOID MemNProgramNbPstateDependentRegistersClientNb ( IN OUT MEM_NB_BLOCK *NBPtr diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c index a3b5d764d1..6aa4868b7f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c @@ -2310,55 +2310,6 @@ MemNChangeFrequencyUnb ( MemFInitTableDrive (NBPtr, MTAfterFreqChg); } - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 RdPtrInit; - - RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 4; - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); - - IDS_HDT_CONSOLE_DEBUG_CODE ( - RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - ); - - switch (RdPtrInit) { - case 4: - if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2); - } else { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - } - break; - case 5: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - break; - case 6: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); - break; - default: - ASSERT (FALSE); - } - - NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); -} - /* -----------------------------------------------------------------------------*/ CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h index 4be78a30fe..c09e2beff7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h @@ -1289,11 +1289,6 @@ MemNChangeFrequencyUnb ( IN OUT MEM_NB_BLOCK *NBPtr ); -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - VOID MemNProgramNbPstateDependentRegistersClientNb ( IN OUT MEM_NB_BLOCK *NBPtr From 53e282acc04d7a8de6ddf5c9453666c02f4d8c43 Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Wed, 1 Jan 2020 09:59:09 -0700 Subject: [PATCH 0261/1463] vc/amd/agesa/f14/Proc/Mem: Fix uninitialized variable Uninitialized variable will contain an arbitrary value left from earlier computations. This issue has already been addressed in the f15tn and f16kb versions of this same file, so am backporting the fix. Change-Id: Id876107265689e08ad6760e514a4911f32b53da7 Signed-off-by: Joe Moore Found-by: Coverity CID 1241856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38048 Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c index 4963b4b056..a19b8bd868 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -249,6 +249,7 @@ MemFS3GetDeviceList ( // Base on the size of the device list, apply for a buffer for it. AllocHeapParams.RequestedBufferSize = BufferSize + sizeof (DEVICE_BLOCK_HEADER); AllocHeapParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE; + AllocHeapParams.Persist = HEAP_S3_RESUME; AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader); if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { return AGESA_FATAL; From c156b584ee820a703073ceda3eaf6cec6afc9966 Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Mon, 25 Nov 2019 05:49:30 -0700 Subject: [PATCH 0262/1463] vc/amd/agesa: Fix uninitialized scalar variable AllocParams.Persist is used uninitialized when calling HeapAllocateBuffer. This could lead to unpredictable or unintended results. The f15tn and f16 versions of AmdS3Save.c have already addressed this by initializing AllocParams.Persist=0 in the same location in the code, so adding to f14 only. Change-Id: I2cbfbc4ad14a861e0cd92f130209b3b0f5b76a17 Signed-off-by: Joe Moore Found-by: Coverity CID 1241806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37194 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks --- src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c index eeab385430..bc5102bbd5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c @@ -202,7 +202,7 @@ AmdS3Save ( // AllocParams.RequestedBufferSize = EarlyBufferSize + LateBufferSize; AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE; - + AllocParams.Persist = 0; AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); if (HeapAllocateBuffer (&AllocParams, &AmdS3SaveParams->StdHeader) != AGESA_SUCCESS) { if (AGESA_ERROR > ReturnStatus) { From a83958185564b2a89ad2053a96874bc883d234d7 Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Tue, 31 Dec 2019 05:20:24 -0700 Subject: [PATCH 0263/1463] vc/amd/agesa: Delete mfParallelTraining.c Potential for out-of-bounds read. However, this code is not used on F14, F15tn, or F16kb platforms. As can be seen in vc/amd/agesa/f15tn/Config/PlatformInstall.h only multiple socket F10 is supported. Tested on Lenovo G505s. Change-Id: Ib71fe32d89840b9f25619d74980e562fd626952b Signed-off-by: Joe Moore Found-by: Coverity CID 1241831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38035 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../f14/Proc/Mem/Feat/PARTRN/Makefile.inc | 1 - .../Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 286 ----------------- .../agesa/f14/Proc/Mem/mfParallelTraining.h | 6 - .../f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc | 1 - .../Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 288 ------------------ .../agesa/f15tn/Proc/Mem/mfParallelTraining.h | 6 - .../f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc | 1 - .../Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 288 ------------------ .../agesa/f16kb/Proc/Mem/mfParallelTraining.h | 6 - 9 files changed, 883 deletions(-) delete mode 100644 src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c delete mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c delete mode 100644 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc index 90c8566627..c88f907b63 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/Makefile.inc @@ -1,2 +1 @@ -libagesa-y += mfParallelTraining.c libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index d8b685960d..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,286 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ - * - **/ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h index 8f5025ec76..3d92c94be1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h @@ -104,12 +104,6 @@ typedef struct _DIE_INFO { *---------------------------------------------------------------------------- */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - #endif /* _MFPARALLELTRAINING_H_ */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc index 90c8566627..c88f907b63 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/Makefile.inc @@ -1,2 +1 @@ -libagesa-y += mfParallelTraining.c libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index 5203b4fe98..0000000000 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,288 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqs2dDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs2dDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h index b85398ade4..acc472b58d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h @@ -102,12 +102,6 @@ typedef struct _DIE_INFO { *---------------------------------------------------------------------------- */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - #endif /* _MFPARALLELTRAINING_H_ */ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc index 90c8566627..c88f907b63 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc @@ -1,2 +1 @@ -libagesa-y += mfParallelTraining.c libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index 2fd10c5e07..0000000000 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,288 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqs2dDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs2dDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h index 312407980d..efca05a589 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h @@ -102,12 +102,6 @@ typedef struct _DIE_INFO { *---------------------------------------------------------------------------- */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - #endif /* _MFPARALLELTRAINING_H_ */ From a608dd80d514a8036954f6a0e5d19645e6ba3d9d Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Sat, 4 Jan 2020 13:33:34 -0700 Subject: [PATCH 0264/1463] vc/amd/agesa/[...]/Config: Avoid out-of-bounds warnings The memNTrainFlowControl array is generating Coverity warnings in multiple places in code where it attempts to write to index 1. The array is defined as either 2 elements or 1 of NULL depending on #if (AGESA_ENTRY_INIT_POST == TRUE). This is likely a false alarm from Coverity (memory should not be training outside of a POST), but adding a second NULL element for the AGESA_ENTRY_INIT_POST == FALSE case. Tested on Lenovo G505s. Change-Id: Iaebe0830471e1854d6191c69cdaa552f900ba7a6 Signed-off-by: Joe Moore Found-by: Coverity CID 1357451, 1357452, 1357453 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38176 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h | 3 ++- src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h | 3 ++- src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h index 57dc0c8801..231b263312 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h @@ -680,7 +680,8 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL + NULL, + NULL, }; /*--------------------------------------------------------------------------------------------------- * DEFAULT TECHNOLOGY BLOCK diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h index 457c51e475..f662db285b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h @@ -4662,7 +4662,8 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL + NULL, + NULL, }; /*--------------------------------------------------------------------------------------------------- * DEFAULT TECHNOLOGY BLOCK diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h index e2d4e03bf9..c5484f1f1c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h @@ -1531,7 +1531,8 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL + NULL, + NULL, }; /*--------------------------------------------------------------------------------------------------- * DEFAULT TECHNOLOGY BLOCK From 6e9f42bed90fb6e8b5642e4e55f1efca999d975a Mon Sep 17 00:00:00 2001 From: Patrick Elsen Date: Sun, 5 Jan 2020 23:34:01 +0100 Subject: [PATCH 0265/1463] util/gitconfig: Fix commit-msg for BSD grep BSD grep (on macOS) doesn't like repeated repetition operators, it throws the error grep: repetition-operator operand invalid This removes the superfluous repetition operator to make the commit-msg hook work on macOS and other platforms not using GNU grep. Change-Id: Id0f57d0f14634f7844b889d71342b2982fcadeb2 Signed-off-by: Patrick Elsen Reviewed-on: https://review.coreboot.org/c/coreboot/+/38205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/gitconfig/commit-msg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 2eef752156..ba6fa3ffb6 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -169,7 +169,7 @@ _gen_ChangeId() { git hash-object -t commit --stdin } -if ! grep -qi '^[[:space:]]*\+Signed-off-by:' "$MSG"; then +if ! grep -qi '^[[:space:]]*Signed-off-by:' "$MSG"; then printf "\nError: No Signed-off-by line in the commit message.\n" exit 1 fi From eb6887e1b62513e02d2b65c783242d411e8b509c Mon Sep 17 00:00:00 2001 From: Idwer Vollering Date: Mon, 6 Jan 2020 16:34:32 +0100 Subject: [PATCH 0266/1463] util/lint: use env to locate the bash binary Otherwise there will, after make gitconfig, be (hidden) shell command failures with 'git commit -s': gmake: util/lint/check-style: Command not found gmake: *** [Makefile.inc:632: check-style] Error 127 Change-Id: I3891dee53702ee10e5e44dae408193e49d7a89f1 Signed-off-by: Idwer Vollering Reviewed-on: https://review.coreboot.org/c/coreboot/+/38227 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/lint/check-style | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/check-style b/util/lint/check-style index f72d7b42c5..5d21b8b2e3 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # git pre-commit hook that runs an clang-format stylecheck. # Features: # - abort commit when commit does not comply with the style guidelines From 6a8cde4927bd6bff60a783c72356fcce801511b8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 22 Oct 2019 21:31:29 +0200 Subject: [PATCH 0267/1463] soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE The cache as ram code will use one form of a non-eviction mode. Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/common/block/cpu/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 - 4 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6c90294d8c..2bc49c838f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -46,7 +46,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA - select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index b68e93d9c1..7474148db4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -74,7 +74,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d3b2..0882dd8827 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -21,6 +21,7 @@ config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT config SOC_INTEL_COMMON_BLOCK_CAR bool default n + select NO_FIXED_XIP_ROM_SIZE help This option allows you to select how cache-as-ram (CAR) is set up. diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 7382df0134..4493f9ba9a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 From e0b74a142c34c9eebbdfd3d96dc8b9076f8c7740 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 3 Mar 2020 22:39:02 +0100 Subject: [PATCH 0268/1463] soc/intel/denverton_ns: Allow including microcode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Felix Singer Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39266 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/Kconfig | 1 + src/soc/intel/denverton_ns/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index a74250bab3..23b84529d2 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select SUPPORT_CPU_UCODE_IN_CBFS config MMCONF_BASE_ADDRESS hex diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 7529892dcc..635dab8908 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -92,4 +92,6 @@ $(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --x $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5f-01 + endif ## CONFIG_SOC_INTEL_DENVERTON_NS From 8bee86ef2334e60e90ecc829f6a55279cbf20b3d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Mar 2020 18:14:54 -0600 Subject: [PATCH 0269/1463] Revert "acpi: Bump FADT to revision 6" This reverts commit c8b0f31ca1b6cae993736d47d919080b6c186c6f. Bumping the FADT table version from 3 to 6 causes Windows 10 to BSOD with an ACPI BIOS error or simply fail to boot on multiple platforms (Haswell, Broadwell, Braswell, Skylake). Revert until the issue can be properly identified and corrected. Change-Id: I261d953321df2616a3f1c3460a535b57a8848315 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39307 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/arch/x86/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 9 ++------- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index b9e896f7de..6dab3733cc 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1563,7 +1563,7 @@ int get_acpi_table_revision(enum acpi_tables table) { switch (table) { case FADT: - return ACPI_FADT_REV_ACPI_6_0; + return ACPI_FADT_REV_ACPI_3_0; case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ return 2; case MCFG: diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 67f4be2d53..68475c157e 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -529,8 +529,8 @@ typedef struct acpi_fadt { u32 flags; acpi_addr_t reset_reg; u8 reset_value; - u16 ARM_boot_arch; /* Revision 6 only, Revision 5: Must be zero */ - u8 FADT_MinorVersion; /* Revision 6 only, Revision 5: Must be zero */ + u16 ARM_boot_arch; + u8 FADT_MinorVersion; u32 x_firmware_ctl_l; u32 x_firmware_ctl_h; u32 x_dsdt_l; @@ -543,11 +543,6 @@ typedef struct acpi_fadt { acpi_addr_t x_pm_tmr_blk; acpi_addr_t x_gpe0_blk; acpi_addr_t x_gpe1_blk; - /* Revision 5 */ - acpi_addr_t sleep_control_reg; - acpi_addr_t sleep_status_reg; - /* Revision 6 */ - u64 hypervisor_vendor_identity; } __packed acpi_fadt_t; /* FADT TABLE Revision values */ From eded500e3cb2d671e18fe6af389bf5b1769dda15 Mon Sep 17 00:00:00 2001 From: Sam McNally Date: Wed, 4 Mar 2020 16:08:06 +1100 Subject: [PATCH 0270/1463] security/vboot: Support enabling EC EFS with EC software sync If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot build must also enable EC EFS. Add an option to control this, passing it through to vboot. BUG=b:150742950 TEST=none BRANCH=none Signed-off-by: Sam McNally Change-Id: I697e90748e19d15af154011413b30c0f2a0bf52e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39272 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak --- src/security/vboot/Kconfig | 8 ++++++++ src/security/vboot/Makefile.inc | 1 + 2 files changed, 9 insertions(+) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e366cc4c09..b6bf542ee6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -260,6 +260,14 @@ config VBOOT_EARLY_EC_SYNC significantly impact boot time, as this operation will be performed later in the boot flow if it is disabled here. +config VBOOT_EC_EFS + bool "Early firmware selection (EFS) EC" + default n + help + CrosEC can support EFS: Early Firmware Selection. If it's enabled, + software sync needs to also support it. This setting tells vboot to + perform EFS software sync. + menu "GBB configuration" config GBB_HWID diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 138273fe4b..d0d3370c6d 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -41,6 +41,7 @@ $$(VBOOT_LIB_$(1)): $(obj)/config.h +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ CC="$$(CC_$(1))" \ CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ + EC_EFS="$(CONFIG_VBOOT_EC_EFS)" \ $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ V=$(V) \ From ce603d59119df32d960fccf84d66e939534673d1 Mon Sep 17 00:00:00 2001 From: Sam McNally Date: Wed, 4 Mar 2020 16:49:24 +1100 Subject: [PATCH 0271/1463] mb/google/hatch/puff: Enable VBOOT_EC_EFS If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP vboot build. BUG=b:150742950 TEST=Puff can boot with EC EFS with hardware write protect enabled BRANCH=none Signed-off-by: Sam McNally Change-Id: I0877000b7d277106436831f2d69775c25299da9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39273 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Paul Menzel --- src/mainboard/google/hatch/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index fc3a66e92e..fe1e334585 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -50,6 +50,7 @@ config BOARD_GOOGLE_PUFF select BOARD_ROMSIZE_KB_32768 select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD + select VBOOT_EC_EFS config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" From 864dc3b0081ad89faf2f2ae02093f009bc0f6ac7 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 4 Mar 2020 13:59:17 +0100 Subject: [PATCH 0272/1463] src/arch/arm: Convert to SPDX license header This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: Ic2bab77edaf7ad97b7f3278cb108226a18cf3791 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39278 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes --- src/arch/arm/Makefile.inc | 10 +---- src/arch/arm/armv4/Makefile.inc | 10 +---- src/arch/arm/armv4/bootblock.S | 14 +------ src/arch/arm/armv4/cache.c | 29 +------------- src/arch/arm/armv7/Makefile.inc | 10 +---- src/arch/arm/armv7/bootblock.S | 18 ++------- src/arch/arm/armv7/bootblock_m.S | 31 +-------------- src/arch/arm/armv7/cache.c | 29 +------------- src/arch/arm/armv7/cache_m.c | 29 +------------- src/arch/arm/armv7/cpu.S | 30 +-------------- src/arch/arm/armv7/exception.c | 30 +-------------- src/arch/arm/armv7/exception_asm.S | 30 +-------------- src/arch/arm/armv7/exception_mr.c | 30 +-------------- src/arch/arm/armv7/mmu.c | 31 +-------------- src/arch/arm/armv7/thread.c | 14 +------ src/arch/arm/asmlib.h | 13 +------ src/arch/arm/boot.c | 14 +------ src/arch/arm/clock.c | 32 ++-------------- src/arch/arm/cpu.c | 32 ++-------------- src/arch/arm/div0.c | 15 +------- src/arch/arm/eabi_compat.c | 17 +-------- src/arch/arm/id.S | 14 +------ src/arch/arm/include/arch/asm.h | 14 +------ src/arch/arm/include/arch/boot/boot.h | 14 +------ src/arch/arm/include/arch/byteorder.h | 14 +------ src/arch/arm/include/arch/cbconfig.h | 14 +------ src/arch/arm/include/arch/clock.h | 14 +------ src/arch/arm/include/arch/header.ld | 14 +------ src/arch/arm/include/arch/hlt.h | 14 +------ src/arch/arm/include/arch/memlayout.h | 14 +------ src/arch/arm/include/arch/pci_ops.h | 14 +------ src/arch/arm/include/arch/stages.h | 14 +------ src/arch/arm/include/armv4/arch/cache.h | 29 +------------- src/arch/arm/include/armv4/arch/cpu.h | 14 +------ src/arch/arm/include/armv4/arch/exception.h | 30 +-------------- src/arch/arm/include/armv4/arch/mmio.h | 16 ++------ .../arm/include/armv4/arch/smp/spinlock.h | 14 +------ src/arch/arm/include/armv7.h | 16 ++------ src/arch/arm/include/armv7/arch/cache.h | 30 +-------------- src/arch/arm/include/armv7/arch/cpu.h | 14 +------ src/arch/arm/include/armv7/arch/exception.h | 30 +-------------- src/arch/arm/include/armv7/arch/mmio.h | 13 +------ src/arch/arm/include/clocks.h | 15 +------- src/arch/arm/include/smp/spinlock.h | 14 +------ src/arch/arm/libgcc/Makefile.inc | 10 +---- src/arch/arm/libgcc/ashldi3.S | 25 +----------- src/arch/arm/libgcc/lib1funcs.S | 25 +----------- src/arch/arm/libgcc/libgcc.h | 14 +------ src/arch/arm/libgcc/lshrdi3.S | 25 +----------- src/arch/arm/libgcc/muldi3.S | 17 ++------- src/arch/arm/libgcc/ucmpdi2.S | 17 ++------- src/arch/arm/libgcc/udivmoddi4.c | 14 +------ src/arch/arm/libgcc/uldivmod.S | 38 +------------------ src/arch/arm/libgcc/umoddi3.c | 14 +------ src/arch/arm/memcpy.S | 13 +------ src/arch/arm/memmove.S | 17 ++------- src/arch/arm/memset.S | 13 +------ src/arch/arm/stages.c | 14 +------ src/arch/arm/tables.c | 14 +------ util/lint/lint-stable-000-license-headers | 4 +- 60 files changed, 126 insertions(+), 1005 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 508b0a80f8..a8abfaf4cc 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -1,16 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ############################################################################### # ARM specific options diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index 2cc5ebba8c..b3366bf9ec 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -1,16 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ############################################################################### armv4_flags = -marm -march=armv4t -I$(src)/arch/arm/include/armv4/ \ diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S index cf37647e27..9bf9614762 100644 --- a/src/arch/arm/armv4/bootblock.S +++ b/src/arch/arm/armv4/bootblock.S @@ -1,16 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Early initialization code for ARM architecture. * * This file is based off of the OMAP3530/ARM Cortex start.S file from Das diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index 140beee060..a79df69203 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -1,31 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R * * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 58592a0818..756412a19c 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -1,16 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ############################################################################### armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7 diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index da2671c519..62d3c1feb8 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -1,22 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Early initialization code for ARMv7 architecture. - * * This file is based off of the OMAP3530/ARM Cortex start.S file from Das * U-Boot, which itself got the file from armboot. */ +/* Early initialization code for ARMv7 architecture. */ + #include .arm diff --git a/src/arch/arm/armv7/bootblock_m.S b/src/arch/arm/armv7/bootblock_m.S index 2e46ca064f..4d691414ba 100644 --- a/src/arch/arm/armv7/bootblock_m.S +++ b/src/arch/arm/armv7/bootblock_m.S @@ -1,32 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index ef3ad018fc..eea63ac27a 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -1,31 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R * * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c index ec8a970167..f4bede6d20 100644 --- a/src/arch/arm/armv7/cache_m.c +++ b/src/arch/arm/armv7/cache_m.c @@ -1,31 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * cache.c: Cache maintenance routines for ARMv7-M */ diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 3f90c0b611..4d1ce8ed96 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -1,32 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright (c) 2010 Per Odlund - * Copyright (c) 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * Optimized assembly for low-level CPU operations on ARMv7 processors. * * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index d6891b0b8d..372cd40311 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm/armv7/exception_asm.S b/src/arch/arm/armv7/exception_asm.S index 6aa4188abc..8d14dbd3b4 100644 --- a/src/arch/arm/armv7/exception_asm.S +++ b/src/arch/arm/armv7/exception_asm.S @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ .text diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c index 01e834ea47..075641b7e9 100644 --- a/src/arch/arm/armv7/exception_mr.c +++ b/src/arch/arm/armv7/exception_mr.c @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 77b9b4b435..36a6a09050 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -1,32 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index 4e82be708c..c5d2bd54d8 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm/asmlib.h b/src/arch/arm/asmlib.h index cae4081efd..6769352d52 100644 --- a/src/arch/arm/asmlib.h +++ b/src/arch/arm/asmlib.h @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * This file contains arm architecture specific defines * for the different processors. * diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 9d1e4cde5f..dfd568fbde 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm/clock.c b/src/arch/arm/clock.c index 5f68e6fa9d..71dfc8df1a 100644 --- a/src/arch/arm/clock.c +++ b/src/arch/arm/clock.c @@ -1,32 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ + #include #include diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index 1e0e0fd60b..f4e7db70ec 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -1,32 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ + #include #include diff --git a/src/arch/arm/div0.c b/src/arch/arm/div0.c index fa3bf7f090..28ca0e3e5e 100644 --- a/src/arch/arm/div0.c +++ b/src/arch/arm/div0.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index b2caf9c377..ec078909da 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is Free Software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Utility functions needed for (some) EABI conformant tool chains. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm/id.S b/src/arch/arm/id.S index 16173fb598..3cdd013535 100644 --- a/src/arch/arm/id.S +++ b/src/arch/arm/id.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm/include/arch/asm.h b/src/arch/arm/include/arch/asm.h index b9591b6b86..7ecdfe18a7 100644 --- a/src/arch/arm/include/arch/asm.h +++ b/src/arch/arm/include/arch/asm.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARM_ASM_H #define __ARM_ASM_H diff --git a/src/arch/arm/include/arch/boot/boot.h b/src/arch/arm/include/arch/boot/boot.h index 07d3adcf7d..c73fe217df 100644 --- a/src/arch/arm/include/arch/boot/boot.h +++ b/src/arch/arm/include/arch/boot/boot.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ASM_ARM_BOOT_H #define ASM_ARM_BOOT_H diff --git a/src/arch/arm/include/arch/byteorder.h b/src/arch/arm/include/arch/byteorder.h index 37cb8b6df6..096ef7585a 100644 --- a/src/arch/arm/include/arch/byteorder.h +++ b/src/arch/arm/include/arch/byteorder.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BYTEORDER_H #define _BYTEORDER_H diff --git a/src/arch/arm/include/arch/cbconfig.h b/src/arch/arm/include/arch/cbconfig.h index 35c1387895..fedc8bdcc6 100644 --- a/src/arch/arm/include/arch/cbconfig.h +++ b/src/arch/arm/include/arch/cbconfig.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_CBCONFIG_H_ #define _ARCH_CBCONFIG_H_ diff --git a/src/arch/arm/include/arch/clock.h b/src/arch/arm/include/arch/clock.h index 248da0607a..2139f017c0 100644 --- a/src/arch/arm/include/arch/clock.h +++ b/src/arch/arm/include/arch/clock.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARM_CLOCK_H_ #define __ARM_CLOCK_H_ diff --git a/src/arch/arm/include/arch/header.ld b/src/arch/arm/include/arch/header.ld index 5d93673579..c834879023 100644 --- a/src/arch/arm/include/arch/header.ld +++ b/src/arch/arm/include/arch/header.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm/include/arch/hlt.h b/src/arch/arm/include/arch/hlt.h index 915f4c003a..064d42583a 100644 --- a/src/arch/arm/include/arch/hlt.h +++ b/src/arch/arm/include/arch/hlt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_HLT_H #define ARCH_HLT_H diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index 26b8ef4708..7a8fc0cb9d 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file contains macro definitions for memlayout.ld linker scripts. */ diff --git a/src/arch/arm/include/arch/pci_ops.h b/src/arch/arm/include/arch/pci_ops.h index 8389f3c4e4..54897fefe0 100644 --- a/src/arch/arm/include/arch/pci_ops.h +++ b/src/arch/arm/include/arch/pci_ops.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_ARM_PCI_OPS_H #define ARCH_ARM_PCI_OPS_H diff --git a/src/arch/arm/include/arch/stages.h b/src/arch/arm/include/arch/stages.h index 795a3a3e7a..09167846cd 100644 --- a/src/arch/arm/include/arch/stages.h +++ b/src/arch/arm/include/arch/stages.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index ed3b96fffe..ee4bf9c603 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -1,31 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * cache.h: Cache maintenance API for ARM */ diff --git a/src/arch/arm/include/armv4/arch/cpu.h b/src/arch/arm/include/armv4/arch/cpu.h index 3a27743cbf..765ea0295d 100644 --- a/src/arch/arm/include/armv4/arch/cpu.h +++ b/src/arch/arm/include/armv4/arch/cpu.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ diff --git a/src/arch/arm/include/armv4/arch/exception.h b/src/arch/arm/include/armv4/arch/exception.h index d4e9658f75..1e71c53f08 100644 --- a/src/arch/arm/include/armv4/arch/exception.h +++ b/src/arch/arm/include/armv4/arch/exception.h @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/arm/include/armv4/arch/mmio.h b/src/arch/arm/include/armv4/arch/mmio.h index 2c43789abf..71bf887ab9 100644 --- a/src/arch/arm/include/armv4/arch/mmio.h +++ b/src/arch/arm/include/armv4/arch/mmio.h @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Originally imported from linux/include/asm-arm/io.h. This file has changed +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* Originally imported from linux/include/asm-arm/io.h. This file has changed * substantially since then. */ diff --git a/src/arch/arm/include/armv4/arch/smp/spinlock.h b/src/arch/arm/include/armv4/arch/smp/spinlock.h index e49dc4440a..59656c3868 100644 --- a/src/arch/arm/include/armv4/arch/smp/spinlock.h +++ b/src/arch/arm/include/armv4/arch/smp/spinlock.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_SMP_SPINLOCK_H #define _ARCH_SMP_SPINLOCK_H diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h index 626e6083f3..7f1d6098f9 100644 --- a/src/arch/arm/include/armv7.h +++ b/src/arch/arm/include/armv7.h @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + #ifndef ARMV7_H #define ARMV7_H #include diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index b2b6a33333..01918a7286 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -1,32 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * cache.h: Cache maintenance API for ARM */ diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 0377e2a5c9..60db1d74eb 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ diff --git a/src/arch/arm/include/armv7/arch/exception.h b/src/arch/arm/include/armv7/arch/exception.h index df3930977b..958a51bdda 100644 --- a/src/arch/arm/include/armv7/arch/exception.h +++ b/src/arch/arm/include/armv7/arch/exception.h @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/mmio.h index 87f68715e8..47b2e84876 100644 --- a/src/arch/arm/include/armv7/arch/mmio.h +++ b/src/arch/arm/include/armv7/arch/mmio.h @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Originally imported from linux/include/asm-arm/io.h. This file has changed * substantially since then. */ diff --git a/src/arch/arm/include/clocks.h b/src/arch/arm/include/clocks.h index 4904b6e96a..4379b63468 100644 --- a/src/arch/arm/include/clocks.h +++ b/src/arch/arm/include/clocks.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* Standard clock speeds */ diff --git a/src/arch/arm/include/smp/spinlock.h b/src/arch/arm/include/smp/spinlock.h index 189bf2c507..3183cc1c80 100644 --- a/src/arch/arm/include/smp/spinlock.h +++ b/src/arch/arm/include/smp/spinlock.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index 2d0f6a81da..b64a5fa1e8 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -1,16 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ################################################################################ libgcc_files = ashldi3.S lib1funcs.S lshrdi3.S muldi3.S ucmpdi2.S uldivmod.S diff --git a/src/arch/arm/libgcc/ashldi3.S b/src/arch/arm/libgcc/ashldi3.S index 473e15f3f3..8243cedc35 100644 --- a/src/arch/arm/libgcc/ashldi3.S +++ b/src/arch/arm/libgcc/ashldi3.S @@ -1,26 +1,5 @@ -/* -This file is part of the coreboot project. - -This file is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. - -In addition to the permissions in the GNU General Public License, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file into combinations with other programs, -and to distribute those combinations without any restriction coming -from the use of this file. (The General Public License restrictions -do apply in other respects; for example, they cover modification of -the file, and distribution when not linked into a combine -executable.) - -This file is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. -*/ - +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/lib1funcs.S b/src/arch/arm/libgcc/lib1funcs.S index 5c2a6ade17..af98022eaf 100644 --- a/src/arch/arm/libgcc/lib1funcs.S +++ b/src/arch/arm/libgcc/lib1funcs.S @@ -1,26 +1,5 @@ -/* -This file is part of the coreboot project. - -This file is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. - -In addition to the permissions in the GNU General Public License, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file into combinations with other programs, -and to distribute those combinations without any restriction coming -from the use of this file. (The General Public License restrictions -do apply in other respects; for example, they cover modification of -the file, and distribution when not linked into a combine -executable.) - -This file is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. -*/ - +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines */ diff --git a/src/arch/arm/libgcc/libgcc.h b/src/arch/arm/libgcc/libgcc.h index 95f4564a29..a8407dd35c 100644 --- a/src/arch/arm/libgcc/libgcc.h +++ b/src/arch/arm/libgcc/libgcc.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ARM_LIBGCC_LIBGCC_H__ #define __ARCH_ARM_LIBGCC_LIBGCC_H__ diff --git a/src/arch/arm/libgcc/lshrdi3.S b/src/arch/arm/libgcc/lshrdi3.S index 5e67690010..4c55384bd8 100644 --- a/src/arch/arm/libgcc/lshrdi3.S +++ b/src/arch/arm/libgcc/lshrdi3.S @@ -1,26 +1,5 @@ -/* -This file is part of the coreboot project. - -This file is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. - -In addition to the permissions in the GNU General Public License, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file into combinations with other programs, -and to distribute those combinations without any restriction coming -from the use of this file. (The General Public License restrictions -do apply in other respects; for example, they cover modification of -the file, and distribution when not linked into a combine -executable.) - -This file is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. -*/ - +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/muldi3.S b/src/arch/arm/libgcc/muldi3.S index c7584745b9..98136f566a 100644 --- a/src/arch/arm/libgcc/muldi3.S +++ b/src/arch/arm/libgcc/muldi3.S @@ -1,17 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Based on linux/arch/arm/lib/muldi3.S - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* Based on linux/arch/arm/lib/muldi3.S */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/ucmpdi2.S b/src/arch/arm/libgcc/ucmpdi2.S index 771e93b502..27671a29fa 100644 --- a/src/arch/arm/libgcc/ucmpdi2.S +++ b/src/arch/arm/libgcc/ucmpdi2.S @@ -1,17 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Based on linux/arch/arm/lib/ucmpdi2.S - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* Based on linux/arch/arm/lib/ucmpdi2.S */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/udivmoddi4.c b/src/arch/arm/libgcc/udivmoddi4.c index 6073848fb2..7c4b2563dd 100644 --- a/src/arch/arm/libgcc/udivmoddi4.c +++ b/src/arch/arm/libgcc/udivmoddi4.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "libgcc.h" diff --git a/src/arch/arm/libgcc/uldivmod.S b/src/arch/arm/libgcc/uldivmod.S index ecbeccfe4b..528be4654e 100644 --- a/src/arch/arm/libgcc/uldivmod.S +++ b/src/arch/arm/libgcc/uldivmod.S @@ -1,39 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2010, Google Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * Neither the name of Google Inc. nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm/libgcc/umoddi3.c b/src/arch/arm/libgcc/umoddi3.c index a1d9a161c2..0f111f2b13 100644 --- a/src/arch/arm/libgcc/umoddi3.c +++ b/src/arch/arm/libgcc/umoddi3.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "libgcc.h" uint64_t __umoddi3(uint64_t num, uint64_t den) diff --git a/src/arch/arm/memcpy.S b/src/arch/arm/memcpy.S index 19592dbfaf..50b34f6e9e 100644 --- a/src/arch/arm/memcpy.S +++ b/src/arch/arm/memcpy.S @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Based on linux/arch/arm/lib/memcpy.S */ diff --git a/src/arch/arm/memmove.S b/src/arch/arm/memmove.S index 3b5681ced2..bcee5c98bd 100644 --- a/src/arch/arm/memmove.S +++ b/src/arch/arm/memmove.S @@ -1,17 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Based on linux/arch/arm/lib/memmove.S - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* Based on linux/arch/arm/lib/memmove.S */ #include #include "asmlib.h" diff --git a/src/arch/arm/memset.S b/src/arch/arm/memset.S index 7d71a88bc3..d4cd2aabb9 100644 --- a/src/arch/arm/memset.S +++ b/src/arch/arm/memset.S @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Based on linux/arch/arm/lib/memset.S * * ASM optimised string functions diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index fc2ebdb2fc..c1ea3d24ad 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file contains entry/exit functions for each stage during coreboot diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index ab2b579f0a..2d79585506 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 99622cc267..14c1339abd 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -7,9 +7,11 @@ # Directories requiring SPDX Identifiers only util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY util/lint/lint-000-license-headers "src/superio" SPDX_ONLY +util/lint/lint-000-license-headers "src/arch/arm" SPDX_ONLY # Top level -util/lint/lint-000-license-headers "src/arch src/commonlib src/console \ +util/lint/lint-000-license-headers "src/arch/arm64 src/arch/ppc64 \ + src/arch/riscv src/arch/x86 src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge" From 0a3d4e0ca0eb2e705c86279bd13efe81b8b2692d Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 4 Mar 2020 14:39:09 +0100 Subject: [PATCH 0273/1463] src/arch/arm64: Convert to SPDX license header This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: Ic5eddc961d015328e5a90994b7963e7af83cddd3 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39279 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/arch/arm64/Makefile.inc | 10 +------ src/arch/arm64/arch_timer.c | 14 ++------- src/arch/arm64/armv8/Makefile.inc | 10 +------ src/arch/arm64/armv8/bootblock.S | 14 ++------- src/arch/arm64/armv8/cache.c | 29 ++---------------- src/arch/arm64/armv8/cpu.S | 13 ++------ src/arch/arm64/armv8/exception.c | 30 ++----------------- src/arch/arm64/armv8/mmu.c | 30 ++----------------- src/arch/arm64/bl31.c | 14 ++------- src/arch/arm64/boot.c | 14 ++------- src/arch/arm64/div0.c | 15 ++-------- src/arch/arm64/eabi_compat.c | 14 ++------- src/arch/arm64/fit_payload.c | 15 ++-------- src/arch/arm64/id.S | 14 ++------- src/arch/arm64/include/arch/acpi.h | 14 ++------- src/arch/arm64/include/arch/acpigen.h | 14 ++------- src/arch/arm64/include/arch/asm.h | 14 ++------- src/arch/arm64/include/arch/boot/boot.h | 14 ++------- src/arch/arm64/include/arch/byteorder.h | 14 ++------- src/arch/arm64/include/arch/cbconfig.h | 14 ++------- src/arch/arm64/include/arch/header.ld | 14 ++------- src/arch/arm64/include/arch/hlt.h | 14 ++------- src/arch/arm64/include/arch/memlayout.h | 14 ++------- src/arch/arm64/include/arch/mpidr.h | 14 ++------- src/arch/arm64/include/arch/pci_ops.h | 14 ++------- src/arch/arm64/include/arch/stages.h | 14 ++------- src/arch/arm64/include/arch/transition.h | 14 ++------- src/arch/arm64/include/armv8/arch/barrier.h | 13 ++------ src/arch/arm64/include/armv8/arch/cache.h | 29 ++---------------- src/arch/arm64/include/armv8/arch/cpu.h | 14 ++------- src/arch/arm64/include/armv8/arch/exception.h | 30 ++----------------- .../arm64/include/armv8/arch/lib_helpers.h | 14 ++------- src/arch/arm64/include/armv8/arch/mmio.h | 13 ++------ src/arch/arm64/include/armv8/arch/mmu.h | 14 ++------- src/arch/arm64/include/bl31.h | 14 ++------- src/arch/arm64/include/clocks.h | 15 ++-------- src/arch/arm64/include/cpu/cortex_a57.h | 14 ++------- src/arch/arm64/memcpy.S | 14 ++------- src/arch/arm64/memmove.S | 14 ++------- src/arch/arm64/memset.S | 14 ++------- src/arch/arm64/ramdetect.c | 7 ++--- src/arch/arm64/romstage.c | 15 ++-------- src/arch/arm64/tables.c | 14 ++------- src/arch/arm64/transition.c | 14 ++------- src/arch/arm64/transition_asm.S | 14 ++------- util/lint/lint-stable-000-license-headers | 3 +- 46 files changed, 90 insertions(+), 607 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index a8742f2e13..c3d1fe5e0e 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -1,16 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ################################################################################ ################################################################################ diff --git a/src/arch/arm64/arch_timer.c b/src/arch/arm64/arch_timer.c index 2db235a5da..3707c89f0d 100644 --- a/src/arch/arm64/arch_timer.c +++ b/src/arch/arm64/arch_timer.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 127c5f114b..c794181c2b 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -1,16 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ################################################################################ ifeq ($(CONFIG_ARCH_ARMV8_EXTENSION),0) diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index 64d2405895..8cfa5606b6 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -1,16 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Early initialization code for aarch64 (a.k.a. armv8) */ diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 46dc85958d..6df38b9bc7 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -1,31 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * cache.c: Cache maintenance routines for ARMv8 (aarch64) * * Reference: ARM Architecture Reference Manual, ARMv8-A edition diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 5f06c7e677..fa4e3bcb67 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Optimized assembly for low-level CPU operations on ARM64 processors. */ diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 4d566aa415..6becf8328e 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index bdec55c8c2..7cce9372a6 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c index c94b1d101e..3677b41540 100644 --- a/src/arch/arm64/bl31.c +++ b/src/arch/arm64/bl31.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 479a910cae..d2cef5b3f0 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/div0.c b/src/arch/arm64/div0.c index daf1d920b0..3cb31cf2da 100644 --- a/src/arch/arm64/div0.c +++ b/src/arch/arm64/div0.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm64/eabi_compat.c b/src/arch/arm64/eabi_compat.c index 79b201758a..22268b266e 100644 --- a/src/arch/arm64/eabi_compat.c +++ b/src/arch/arm64/eabi_compat.c @@ -1,16 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is Free Software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Utility functions needed for (some) EABI conformant tool chains. */ diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index 7009a3f25d..6d8064898e 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/id.S b/src/arch/arm64/id.S index 16173fb598..3cdd013535 100644 --- a/src/arch/arm64/id.S +++ b/src/arch/arm64/id.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm64/include/arch/acpi.h b/src/arch/arm64/include/arch/acpi.h index 4015d18021..5a9005c078 100644 --- a/src/arch/arm64/include/arch/acpi.h +++ b/src/arch/arm64/include/arch/acpi.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ACPI_H_ #define __ARCH_ACPI_H_ diff --git a/src/arch/arm64/include/arch/acpigen.h b/src/arch/arm64/include/arch/acpigen.h index 1ca538e703..8550e69817 100644 --- a/src/arch/arm64/include/arch/acpigen.h +++ b/src/arch/arm64/include/arch/acpigen.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ACPIGEN_H_ #define __ARCH_ACPIGEN_H_ diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index 7d3ad7e6b3..9ed3299bbf 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARM_ARM64_ASM_H #define __ARM_ARM64_ASM_H diff --git a/src/arch/arm64/include/arch/boot/boot.h b/src/arch/arm64/include/arch/boot/boot.h index ae6913cc0c..043481f690 100644 --- a/src/arch/arm64/include/arch/boot/boot.h +++ b/src/arch/arm64/include/arch/boot/boot.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ASM_ARM64_BOOT_H #define ASM_ARM64_BOOT_H diff --git a/src/arch/arm64/include/arch/byteorder.h b/src/arch/arm64/include/arch/byteorder.h index 37cb8b6df6..096ef7585a 100644 --- a/src/arch/arm64/include/arch/byteorder.h +++ b/src/arch/arm64/include/arch/byteorder.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BYTEORDER_H #define _BYTEORDER_H diff --git a/src/arch/arm64/include/arch/cbconfig.h b/src/arch/arm64/include/arch/cbconfig.h index 35c1387895..fedc8bdcc6 100644 --- a/src/arch/arm64/include/arch/cbconfig.h +++ b/src/arch/arm64/include/arch/cbconfig.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_CBCONFIG_H_ #define _ARCH_CBCONFIG_H_ diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index dcba068f9a..9ac6bfd1b1 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm64/include/arch/hlt.h b/src/arch/arm64/include/arch/hlt.h index 915f4c003a..064d42583a 100644 --- a/src/arch/arm64/include/arch/hlt.h +++ b/src/arch/arm64/include/arch/hlt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_HLT_H #define ARCH_HLT_H diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index 984a09b86e..98347cb2b5 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file contains macro definitions for memlayout.ld linker scripts. */ diff --git a/src/arch/arm64/include/arch/mpidr.h b/src/arch/arm64/include/arch/mpidr.h index cc43309e4b..97ea327530 100644 --- a/src/arch/arm64/include/arch/mpidr.h +++ b/src/arch/arm64/include/arch/mpidr.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MPIDR_H__ #define __ARCH_MPIDR_H__ diff --git a/src/arch/arm64/include/arch/pci_ops.h b/src/arch/arm64/include/arch/pci_ops.h index 65dd059529..94992c0c00 100644 --- a/src/arch/arm64/include/arch/pci_ops.h +++ b/src/arch/arm64/include/arch/pci_ops.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_ARM64_PCI_OPS_H #define ARCH_ARM64_PCI_OPS_H diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index c8a3bdd20e..5c44f63929 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H diff --git a/src/arch/arm64/include/arch/transition.h b/src/arch/arm64/include/arch/transition.h index 8a49eed8de..98625946a6 100644 --- a/src/arch/arm64/include/arch/transition.h +++ b/src/arch/arm64/include/arch/transition.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ARM64_TRANSITION_H__ #define __ARCH_ARM64_TRANSITION_H__ diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h index 8da2cc29c8..790a130050 100644 --- a/src/arch/arm64/include/armv8/arch/barrier.h +++ b/src/arch/arm64/include/armv8/arch/barrier.h @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Based on arch/arm/include/asm/barrier.h */ #ifndef __ASM_ARM_BARRIER_H diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 1168992cc4..7b19ca5ad0 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -1,31 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * * cache.h: Cache maintenance API for ARM64 */ diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 9b08bb4f7e..cfccf4c165 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h index 155060f954..35021591ba 100644 --- a/src/arch/arm64/include/armv8/arch/exception.h +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -1,31 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 9d5b508453..cd4aa449c4 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -1,16 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * lib_helpers.h: All library function prototypes and macros are defined in this * file. */ diff --git a/src/arch/arm64/include/armv8/arch/mmio.h b/src/arch/arm64/include/armv8/arch/mmio.h index 4a92ddb38d..47e7f349c0 100644 --- a/src/arch/arm64/include/armv8/arch/mmio.h +++ b/src/arch/arm64/include/armv8/arch/mmio.h @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Originally imported from linux/include/asm-arm/io.h. This file has changed * substantially since then. */ diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index 4b6d78792a..f79510ec31 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ARM64_MMU_H__ #define __ARCH_ARM64_MMU_H__ diff --git a/src/arch/arm64/include/bl31.h b/src/arch/arm64/include/bl31.h index 0f90e774b3..c96bddf5d4 100644 --- a/src/arch/arm64/include/bl31.h +++ b/src/arch/arm64/include/bl31.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BL31_H__ #define __BL31_H__ diff --git a/src/arch/arm64/include/clocks.h b/src/arch/arm64/include/clocks.h index 4904b6e96a..4379b63468 100644 --- a/src/arch/arm64/include/clocks.h +++ b/src/arch/arm64/include/clocks.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* Standard clock speeds */ diff --git a/src/arch/arm64/include/cpu/cortex_a57.h b/src/arch/arm64/include/cpu/cortex_a57.h index 3259934232..9497cd648c 100644 --- a/src/arch/arm64/include/cpu/cortex_a57.h +++ b/src/arch/arm64/include/cpu/cortex_a57.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ARM64_CORTEX_A57_H__ #define __ARCH_ARM64_CORTEX_A57_H__ diff --git a/src/arch/arm64/memcpy.S b/src/arch/arm64/memcpy.S index ef37ea5dc9..a79abd5216 100644 --- a/src/arch/arm64/memcpy.S +++ b/src/arch/arm64/memcpy.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm64/memmove.S b/src/arch/arm64/memmove.S index ac2865054e..23b2a918f0 100644 --- a/src/arch/arm64/memmove.S +++ b/src/arch/arm64/memmove.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include /* diff --git a/src/arch/arm64/memset.S b/src/arch/arm64/memset.S index 5b61b31053..44e1047f4f 100644 --- a/src/arch/arm64/memset.S +++ b/src/arch/arm64/memset.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/arm64/ramdetect.c b/src/arch/arm64/ramdetect.c index bc034c311b..1b2b3cee3f 100644 --- a/src/arch/arm64/ramdetect.c +++ b/src/arch/arm64/ramdetect.c @@ -1,8 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c index 58c47e78f3..3eede4ffc2 100644 --- a/src/arch/arm64/romstage.c +++ b/src/arch/arm64/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 62334a725f..825cef189d 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index ac59d19acf..b21ee05b45 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index bdb412f36d..f62183e823 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * transition_asm.S: This file handles the entry and exit from an exception diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 14c1339abd..d9d1b2ebf3 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -8,9 +8,10 @@ util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY util/lint/lint-000-license-headers "src/superio" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/arm" SPDX_ONLY +util/lint/lint-000-license-headers "src/arch/arm64" SPDX_ONLY # Top level -util/lint/lint-000-license-headers "src/arch/arm64 src/arch/ppc64 \ +util/lint/lint-000-license-headers "src/arch/ppc64 \ src/arch/riscv src/arch/x86 src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge" From 0a2a670502b2a3404fdaf0708b06a96581880aa6 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 4 Mar 2020 14:43:23 +0100 Subject: [PATCH 0274/1463] src/arch/ppc64: Convert to SPDX license header This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: I19b1c379b474dd011e2d0f8c8202ff1351c9290d Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39281 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/arch/ppc64/Makefile.inc | 10 +------- src/arch/ppc64/boot.c | 14 ++-------- src/arch/ppc64/bootblock.S | 14 ++-------- src/arch/ppc64/id.ld | 14 ++-------- src/arch/ppc64/include/arch/byteorder.h | 14 ++-------- src/arch/ppc64/include/arch/cache.h | 31 ++--------------------- src/arch/ppc64/include/arch/cbconfig.h | 14 ++-------- src/arch/ppc64/include/arch/cpu.h | 14 ++-------- src/arch/ppc64/include/arch/exception.h | 14 ++-------- src/arch/ppc64/include/arch/header.ld | 14 ++-------- src/arch/ppc64/include/arch/hlt.h | 14 ++-------- src/arch/ppc64/include/arch/io.h | 14 ++-------- src/arch/ppc64/include/arch/memlayout.h | 14 ++-------- src/arch/ppc64/include/arch/mmio.h | 14 ++-------- src/arch/ppc64/include/arch/stages.h | 14 ++-------- src/arch/ppc64/prologue.inc | 14 ++-------- src/arch/ppc64/rom_media.c | 16 +++--------- src/arch/ppc64/stages.c | 14 ++-------- src/arch/ppc64/tables.c | 14 ++-------- util/lint/lint-stable-000-license-headers | 4 +-- 20 files changed, 40 insertions(+), 245 deletions(-) diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index fae4c926b7..1c35f6f3f8 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -1,16 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ################################################################################ ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8 diff --git a/src/arch/ppc64/boot.c b/src/arch/ppc64/boot.c index 6c13761538..1bd1c09b75 100644 --- a/src/arch/ppc64/boot.c +++ b/src/arch/ppc64/boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S index 2628e0dabe..4c13bc94b6 100644 --- a/src/arch/ppc64/bootblock.S +++ b/src/arch/ppc64/bootblock.S @@ -1,16 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * * Early initialization code for POWER8. */ diff --git a/src/arch/ppc64/id.ld b/src/arch/ppc64/id.ld index 932375665e..4f6853fc9d 100644 --- a/src/arch/ppc64/id.ld +++ b/src/arch/ppc64/id.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ SECTIONS { . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; diff --git a/src/arch/ppc64/include/arch/byteorder.h b/src/arch/ppc64/include/arch/byteorder.h index 37cb8b6df6..096ef7585a 100644 --- a/src/arch/ppc64/include/arch/byteorder.h +++ b/src/arch/ppc64/include/arch/byteorder.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BYTEORDER_H #define _BYTEORDER_H diff --git a/src/arch/ppc64/include/arch/cache.h b/src/arch/ppc64/include/arch/cache.h index 37174475f5..1f0b9c282f 100644 --- a/src/arch/ppc64/include/arch/cache.h +++ b/src/arch/ppc64/include/arch/cache.h @@ -1,32 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H diff --git a/src/arch/ppc64/include/arch/cbconfig.h b/src/arch/ppc64/include/arch/cbconfig.h index 35c1387895..fedc8bdcc6 100644 --- a/src/arch/ppc64/include/arch/cbconfig.h +++ b/src/arch/ppc64/include/arch/cbconfig.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_CBCONFIG_H_ #define _ARCH_CBCONFIG_H_ diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h index 89816903c8..4714b7cc4a 100644 --- a/src/arch/ppc64/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ diff --git a/src/arch/ppc64/include/arch/exception.h b/src/arch/ppc64/include/arch/exception.h index 07030e5b95..c88b55cbac 100644 --- a/src/arch/ppc64/include/arch/exception.h +++ b/src/arch/ppc64/include/arch/exception.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/ppc64/include/arch/header.ld b/src/arch/ppc64/include/arch/header.ld index badeefdf49..d4aa134441 100644 --- a/src/arch/ppc64/include/arch/header.ld +++ b/src/arch/ppc64/include/arch/header.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_ARCH(powerpc) diff --git a/src/arch/ppc64/include/arch/hlt.h b/src/arch/ppc64/include/arch/hlt.h index 1ba1e35b67..37d43026c2 100644 --- a/src/arch/ppc64/include/arch/hlt.h +++ b/src/arch/ppc64/include/arch/hlt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ static __always_inline void hlt(void) { diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 804d7dc1b1..1d865968bf 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ASM_IO_H #define _ASM_IO_H diff --git a/src/arch/ppc64/include/arch/memlayout.h b/src/arch/ppc64/include/arch/memlayout.h index 09e87c9574..c65649c0cc 100644 --- a/src/arch/ppc64/include/arch/memlayout.h +++ b/src/arch/ppc64/include/arch/memlayout.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file contains macro definitions for memlayout.ld linker scripts. */ diff --git a/src/arch/ppc64/include/arch/mmio.h b/src/arch/ppc64/include/arch/mmio.h index 8ffb81691a..55609acdf4 100644 --- a/src/arch/ppc64/include/arch/mmio.h +++ b/src/arch/ppc64/include/arch/mmio.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ diff --git a/src/arch/ppc64/include/arch/stages.h b/src/arch/ppc64/include/arch/stages.h index 37e9f85c8c..92caebc48e 100644 --- a/src/arch/ppc64/include/arch/stages.h +++ b/src/arch/ppc64/include/arch/stages.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H diff --git a/src/arch/ppc64/prologue.inc b/src/arch/ppc64/prologue.inc index 9e22eb3d49..7685f5b625 100644 --- a/src/arch/ppc64/prologue.inc +++ b/src/arch/ppc64/prologue.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c index 0fc8be26e0..90e037331b 100644 --- a/src/arch/ppc64/rom_media.c +++ b/src/arch/ppc64/rom_media.c @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #include /* This assumes that the CBFS resides at 0x0, which is true for the default diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index aacf45f88f..edb49ce29c 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file contains entry/exit functions for each stage during coreboot diff --git a/src/arch/ppc64/tables.c b/src/arch/ppc64/tables.c index e9de4bfd71..eafc87e2af 100644 --- a/src/arch/ppc64/tables.c +++ b/src/arch/ppc64/tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index d9d1b2ebf3..99eea7f6bc 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -9,10 +9,10 @@ util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY util/lint/lint-000-license-headers "src/superio" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/arm" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/arm64" SPDX_ONLY +util/lint/lint-000-license-headers "src/arch/ppc64" SPDX_ONLY # Top level -util/lint/lint-000-license-headers "src/arch/ppc64 \ - src/arch/riscv src/arch/x86 src/commonlib src/console \ +util/lint/lint-000-license-headers "src/arch/riscv src/arch/x86 src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge" From e342cd332265929a85eff8d39df4a26838070b28 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 4 Mar 2020 14:58:49 +0100 Subject: [PATCH 0275/1463] util/lint: Add BSD-4-Clause-UC to acceptable licenses While a 4 clause BSD license "with advertising" is incompatible to the GPL, the University of California declared the problematic clause null and void. See ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change Change-Id: I4ebb822f64989a5fc8f686e548a94653508d1113 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39282 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- util/lint/lint-000-license-headers | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 48f7b400ca..1382d7fe48 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -111,6 +111,13 @@ check_for_license 'SPDX-License-Identifier: ISC' check_for_license 'SPDX-License-Identifier: MIT' check_for_license 'SPDX-License-Identifier: X11' +# This is 4 clause ("with advertising") but the University of Berkeley +# declared that 4th clause void, see +# ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change +# With this, BSD-4-Clause-UC becomes GPLv2 compatible, and so SPDX doesn't +# differentiate between this license with or without advertising. +check_for_license 'SPDX-License-Identifier: BSD-4-Clause-UC' + if [ ! "${SPDX_ONLY}" = "1" ]; then check_for_license "under the terms of the GNU General Public License" \ "WITHOUT ANY WARRANTY" From d1e50f9e9fb8f8dd9726ec838ba4d7c1ca0d265a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 4 Mar 2020 15:00:05 +0100 Subject: [PATCH 0276/1463] src/arch/riscv: Convert to SPDX license header This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: I770c1afd9b68a40ec0e69818f24b5ef3ad4f1d35 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39283 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes --- AUTHORS | 2 ++ src/arch/riscv/Makefile.inc | 13 +-------- src/arch/riscv/arch_timer.c | 16 ++--------- src/arch/riscv/boot.c | 16 ++--------- src/arch/riscv/bootblock.S | 15 ++-------- src/arch/riscv/fit_payload.c | 17 ++---------- src/arch/riscv/fp_asm.S | 16 ++--------- src/arch/riscv/include/arch/barrier.h | 32 ++-------------------- src/arch/riscv/include/arch/boot.h | 16 ++--------- src/arch/riscv/include/arch/byteorder.h | 14 ++-------- src/arch/riscv/include/arch/cache.h | 31 ++------------------- src/arch/riscv/include/arch/cbconfig.h | 16 ++--------- src/arch/riscv/include/arch/cpu.h | 16 ++--------- src/arch/riscv/include/arch/encoding.h | 28 ++----------------- src/arch/riscv/include/arch/errno.h | 28 ++----------------- src/arch/riscv/include/arch/exception.h | 30 ++------------------ src/arch/riscv/include/arch/header.ld | 16 ++--------- src/arch/riscv/include/arch/hlt.h | 14 ++-------- src/arch/riscv/include/arch/memlayout.h | 16 ++--------- src/arch/riscv/include/arch/mmio.h | 14 ++-------- src/arch/riscv/include/arch/pmp.h | 16 ++--------- src/arch/riscv/include/arch/smp/atomic.h | 29 ++------------------ src/arch/riscv/include/arch/smp/smp.h | 16 ++--------- src/arch/riscv/include/arch/smp/spinlock.h | 17 ++---------- src/arch/riscv/include/arch/stages.h | 16 ++--------- src/arch/riscv/include/bits.h | 28 ++----------------- src/arch/riscv/include/mcall.h | 16 ++--------- src/arch/riscv/include/sbi.h | 16 ++--------- src/arch/riscv/include/vm.h | 28 ++----------------- src/arch/riscv/mcall.c | 28 ++----------------- src/arch/riscv/misaligned.c | 16 ++--------- src/arch/riscv/misc.c | 14 ++-------- src/arch/riscv/opensbi.c | 16 ++--------- src/arch/riscv/payload.c | 18 ++---------- src/arch/riscv/pmp.c | 16 ++--------- src/arch/riscv/ramstage.S | 16 ++--------- src/arch/riscv/romstage.c | 16 ++--------- src/arch/riscv/sbi.c | 16 ++--------- src/arch/riscv/smp.c | 16 ++--------- src/arch/riscv/tables.c | 18 ++---------- src/arch/riscv/trap_handler.c | 14 ++-------- src/arch/riscv/trap_util.S | 14 ++-------- src/arch/riscv/virtual_memory.c | 14 ++-------- util/lint/lint-stable-000-license-headers | 3 +- 44 files changed, 88 insertions(+), 695 deletions(-) diff --git a/AUTHORS b/AUTHORS index d41c9583b5..9ec48bbf9d 100644 --- a/AUTHORS +++ b/AUTHORS @@ -52,6 +52,7 @@ Gerd Hoffmann Gergely Kiss Google LLC Greg Watson +HardenedLinux Idwer Vollering Imagination Technologies Infineon Technologies @@ -125,6 +126,7 @@ Syed Mohammed Khasim Texas Instruments The ChromiumOS Authors The Linux Foundation +The Regents of the University of California Thomas Winischhofer Timothy Pearson Tobias Diedrich diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 003852324b..17f225a523 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -1,19 +1,8 @@ ################################################################################ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## Copyright (C) 2014 The ChromiumOS Authors -## Copyright (C) 2018 HardenedLinux -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ################################################################################ ################################################################################ diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 55b1f723ee..af5db5ed61 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Philipp Hug - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index f9f94a7086..0e6e2233f2 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index b0796f9fbc..b25a541949 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,18 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for RISC-V - * - * Copyright 2013 Google Inc. - * Copyright 2016 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 63cda846fc..58d40f3959 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -1,18 +1,5 @@ -/* - * Copyright 2013 Google Inc. - * Copyright 2018 Facebook, Inc. - * Copyright 2019 9elements Agency GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/fp_asm.S b/src/arch/riscv/fp_asm.S index 9c6cc650d8..5961047aa9 100644 --- a/src/arch/riscv/fp_asm.S +++ b/src/arch/riscv/fp_asm.S @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file define some function used to swap value between memory diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h index 257e2a2bc3..d5e61e8b47 100644 --- a/src/arch/riscv/include/arch/barrier.h +++ b/src/arch/riscv/include/arch/barrier.h @@ -1,33 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * Copyright 2016 Jonathan Neuschäfer - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_BARRIER_H_ #define __ARCH_BARRIER_H__ diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h index c05c669f00..be1e6f1ce3 100644 --- a/src/arch/riscv/include/arch/boot.h +++ b/src/arch/riscv/include/arch/boot.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H diff --git a/src/arch/riscv/include/arch/byteorder.h b/src/arch/riscv/include/arch/byteorder.h index 37cb8b6df6..096ef7585a 100644 --- a/src/arch/riscv/include/arch/byteorder.h +++ b/src/arch/riscv/include/arch/byteorder.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BYTEORDER_H #define _BYTEORDER_H diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h index 37d0662de8..b42ad95ea0 100644 --- a/src/arch/riscv/include/arch/cache.h +++ b/src/arch/riscv/include/arch/cache.h @@ -1,32 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H diff --git a/src/arch/riscv/include/arch/cbconfig.h b/src/arch/riscv/include/arch/cbconfig.h index 9467f52646..fedc8bdcc6 100644 --- a/src/arch/riscv/include/arch/cbconfig.h +++ b/src/arch/riscv/include/arch/cbconfig.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_CBCONFIG_H_ #define _ARCH_CBCONFIG_H_ diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index c62199e3f0..e249aa3964 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h index f84c9d4a9d..8aae565ba0 100644 --- a/src/arch/riscv/include/arch/encoding.h +++ b/src/arch/riscv/include/arch/encoding.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2010-2017, The Regents of the University of California - * (Regents). All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H diff --git a/src/arch/riscv/include/arch/errno.h b/src/arch/riscv/include/arch/errno.h index 6f80ee5afd..1aa8eebb87 100644 --- a/src/arch/riscv/include/arch/errno.h +++ b/src/arch/riscv/include/arch/errno.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _RISCV_ERRNO_BASE_H #define _RISCV_ERRNO_BASE_H diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index 6fbbdf0a89..3e8da6c0f4 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -1,31 +1,5 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index 4b1104778c..1168b37b8c 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h index a955ebbb0c..4020defe30 100644 --- a/src/arch/riscv/include/arch/hlt.h +++ b/src/arch/riscv/include/arch/hlt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ static __always_inline void hlt(void) { diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index ac707d0978..fcbe6a7042 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file contains macro definitions for memlayout.ld linker scripts. */ diff --git a/src/arch/riscv/include/arch/mmio.h b/src/arch/riscv/include/arch/mmio.h index 4cbc07bbc7..e66629e4ad 100644 --- a/src/arch/riscv/include/arch/mmio.h +++ b/src/arch/riscv/include/arch/mmio.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ diff --git a/src/arch/riscv/include/arch/pmp.h b/src/arch/riscv/include/arch/pmp.h index 6cdb997220..8335349e4f 100644 --- a/src/arch/riscv/include/arch/pmp.h +++ b/src/arch/riscv/include/arch/pmp.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __RISCV_PMP_H__ #define __RISCV_PMP_H__ diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h index de7fd19bd3..1ac6e79a9a 100644 --- a/src/arch/riscv/include/arch/smp/atomic.h +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -1,30 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * Copyright (c) 2018, HardenedLinux. - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _RISCV_ATOMIC_H #define _RISCV_ATOMIC_H diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h index e996404476..353f8f5f36 100644 --- a/src/arch/riscv/include/arch/smp/smp.h +++ b/src/arch/riscv/include/arch/smp/smp.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _RISCV_SMP_H #define _RISCV_SMP_H diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index 95e60bfefc..c9c2e6c02b 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -1,17 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h index 138298fd03..2d8166894f 100644 --- a/src/arch/riscv/include/arch/stages.h +++ b/src/arch/riscv/include/arch/stages.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h index d824f3ec98..8afb14a5d7 100644 --- a/src/arch/riscv/include/bits.h +++ b/src/arch/riscv/include/bits.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _BITS_H #define _BITS_H diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index d7d67ce33b..44b2d27334 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MCALL_H #define _MCALL_H diff --git a/src/arch/riscv/include/sbi.h b/src/arch/riscv/include/sbi.h index 2943704a84..2905310b88 100644 --- a/src/arch/riscv/include/sbi.h +++ b/src/arch/riscv/include/sbi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RISCV_SBI_H #define RISCV_SBI_H diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 9f6236ea75..5c2b1d4f6a 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #ifndef _VM_H #define _VM_H diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index afb17c1043..8e788a7c70 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -1,29 +1,5 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ +/* SPDX-License-Identifier: BSD-4-Clause-UC */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index ebff2d6678..172b21524c 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c index 1909dbc5f1..71bef1d787 100644 --- a/src/arch/riscv/misc.c +++ b/src/arch/riscv/misc.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index 695c24f756..d9fdc2fb8e 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 9elements Agency GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 297d30d2a5..715d7f378c 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc - * Copyright (C) 2018 HardenedLinux - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c index 5e32f9ca23..e707051a85 100644 --- a/src/arch/riscv/pmp.c +++ b/src/arch/riscv/pmp.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 2468c231bc..676c59ba1f 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c index d5f5a43ce1..0991c681b4 100644 --- a/src/arch/riscv/romstage.c +++ b/src/arch/riscv/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Entry points must be placed at the location the previous stage jumps diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 27701895dd..bbde935ea9 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 95d116a629..eb435d85a4 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index c5bcab0661..8a60b43e62 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 6b39faba79..91db11479b 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for riscv - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b986..0e7d53bfcf 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for riscv - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 2f13ecb398..431f711ba3 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Early initialization code for riscv virtual memory - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. */ #include diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 99eea7f6bc..300fde534c 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -10,9 +10,10 @@ util/lint/lint-000-license-headers "src/superio" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/arm" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/arm64" SPDX_ONLY util/lint/lint-000-license-headers "src/arch/ppc64" SPDX_ONLY +util/lint/lint-000-license-headers "src/arch/riscv" SPDX_ONLY # Top level -util/lint/lint-000-license-headers "src/arch/riscv src/arch/x86 src/commonlib src/console \ +util/lint/lint-000-license-headers "src/arch/x86 src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge" From 11f0079c5ac0c5e98682f3ce67763e684433c7f8 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 4 Mar 2020 15:10:45 +0100 Subject: [PATCH 0277/1463] src/arch/x86: Convert to SPDX license header This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39284 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes --- src/arch/x86/Kconfig | 10 +------- src/arch/x86/Makefile.inc | 10 +------- src/arch/x86/acpi.c | 13 ++-------- src/arch/x86/acpi/debug.asl | 14 ++-------- src/arch/x86/acpi/globutil.asl | 14 ++-------- src/arch/x86/acpi/statdef.asl | 14 ++-------- src/arch/x86/acpi_bert_storage.c | 14 ++-------- src/arch/x86/acpi_device.c | 14 ++-------- src/arch/x86/acpi_pld.c | 14 ++-------- src/arch/x86/acpi_s3.c | 14 ++-------- src/arch/x86/acpigen.c | 14 ++-------- src/arch/x86/acpigen_dsm.c | 14 ++-------- src/arch/x86/assembly_entry.S | 14 ++-------- src/arch/x86/boot.c | 14 ++-------- src/arch/x86/bootblock_crt0.S | 14 ++-------- src/arch/x86/bootblock_normal.c | 14 ++-------- src/arch/x86/c_start.S | 14 ++-------- src/arch/x86/car.ld | 14 ++-------- src/arch/x86/cbmem.c | 14 ++-------- src/arch/x86/cf9_reset.c | 14 ++-------- src/arch/x86/cpu.c | 14 ++-------- src/arch/x86/cpu_common.c | 14 ++-------- src/arch/x86/ebda.c | 15 ++--------- src/arch/x86/exception.c | 14 ++-------- src/arch/x86/exit_car.S | 15 ++--------- src/arch/x86/gdt.c | 14 ++-------- src/arch/x86/gdt_init.S | 15 +++-------- src/arch/x86/id.S | 14 ++-------- src/arch/x86/id.ld | 14 ++-------- src/arch/x86/idt.S | 14 ++-------- src/arch/x86/include/arch/acpi.h | 14 ++-------- src/arch/x86/include/arch/acpi_device.h | 14 ++-------- src/arch/x86/include/arch/acpi_ivrs.h | 14 ++-------- src/arch/x86/include/arch/acpi_pld.h | 14 ++-------- src/arch/x86/include/arch/acpigen.h | 14 ++-------- src/arch/x86/include/arch/acpigen_dsm.h | 14 ++-------- src/arch/x86/include/arch/bert_storage.h | 14 ++-------- src/arch/x86/include/arch/boot/boot.h | 14 ++-------- src/arch/x86/include/arch/bootblock.h | 14 ++-------- src/arch/x86/include/arch/byteorder.h | 14 ++-------- src/arch/x86/include/arch/cache.h | 31 ++--------------------- src/arch/x86/include/arch/cbconfig.h | 14 ++-------- src/arch/x86/include/arch/cpu.h | 14 ++-------- src/arch/x86/include/arch/ebda.h | 15 ++--------- src/arch/x86/include/arch/exception.h | 28 ++------------------ src/arch/x86/include/arch/header.ld | 14 ++-------- src/arch/x86/include/arch/hlt.h | 14 ++-------- src/arch/x86/include/arch/interrupt.h | 15 ++--------- src/arch/x86/include/arch/io.h | 14 ++-------- src/arch/x86/include/arch/ioapic.h | 14 ++-------- src/arch/x86/include/arch/memlayout.h | 14 ++-------- src/arch/x86/include/arch/memory_clear.h | 14 ++-------- src/arch/x86/include/arch/mmio.h | 14 ++-------- src/arch/x86/include/arch/pci_io_cfg.h | 14 ++-------- src/arch/x86/include/arch/pci_ops.h | 14 ++-------- src/arch/x86/include/arch/pirq_routing.h | 16 +++--------- src/arch/x86/include/arch/ram_segs.h | 14 ++-------- src/arch/x86/include/arch/registers.h | 14 ++-------- src/arch/x86/include/arch/rom_segs.h | 14 ++-------- src/arch/x86/include/arch/romstage.h | 14 ++-------- src/arch/x86/include/arch/smp/atomic.h | 14 ++-------- src/arch/x86/include/arch/smp/mpspec.h | 14 ++-------- src/arch/x86/include/arch/smp/spinlock.h | 14 ++-------- src/arch/x86/include/arch/stages.h | 14 ++-------- src/arch/x86/include/arch/symbols.h | 14 ++-------- src/arch/x86/include/cf9_reset.h | 14 ++-------- src/arch/x86/include/smm.h | 14 ++-------- src/arch/x86/ioapic.c | 14 ++-------- src/arch/x86/memcpy.c | 14 ++-------- src/arch/x86/memlayout.ld | 14 ++-------- src/arch/x86/memmove.c | 14 ++-------- src/arch/x86/memset.c | 15 ++--------- src/arch/x86/mmap_boot.c | 14 ++-------- src/arch/x86/mpspec.c | 14 ++-------- src/arch/x86/pirq_routing.c | 16 +++--------- src/arch/x86/post.c | 15 ++--------- src/arch/x86/postcar.c | 14 ++-------- src/arch/x86/postcar_loader.c | 14 ++-------- src/arch/x86/prologue.inc | 14 ++-------- src/arch/x86/rdrand.c | 14 ++-------- src/arch/x86/smbios.c | 15 ++--------- src/arch/x86/tables.c | 14 ++-------- src/arch/x86/thread.c | 14 ++-------- src/arch/x86/thread_switch.S | 15 +++-------- src/arch/x86/timestamp.c | 14 ++-------- src/arch/x86/timestamp.inc | 14 ++-------- src/arch/x86/verstage.c | 14 ++-------- src/arch/x86/wakeup.S | 14 ++-------- src/arch/x86/walkcbfs.S | 14 ++-------- util/lint/lint-stable-000-license-headers | 7 ++--- 90 files changed, 182 insertions(+), 1106 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1c55bdbf3c..810a5bbaab 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -1,15 +1,7 @@ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## config ARCH_X86 bool diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 534f2ce20d..873161237e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,15 +1,7 @@ ## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ifeq ($(CONFIG_POSTCAR_STAGE),y) $(eval $(call init_standard_toolchain,postcar)) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6dab3733cc..317cd483a2 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * coreboot ACPI Table support */ diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index 36afac6211..cde807c17f 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index e9b428ad36..76671000a4 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope(\_SB) { diff --git a/src/arch/x86/acpi/statdef.asl b/src/arch/x86/acpi/statdef.asl index 99194f428c..d6959ffec6 100644 --- a/src/arch/x86/acpi/statdef.asl +++ b/src/arch/x86/acpi/statdef.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Status and notification definitions */ diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 130f97a678..a7061fa7c5 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 1092c7317b..9f1710e35f 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/acpi_pld.c b/src/arch/x86/acpi_pld.c index 6fbbfe74e3..135009a243 100644 --- a/src/arch/x86/acpi_pld.c +++ b/src/arch/x86/acpi_pld.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ecfe34c0cf..bf17980020 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 9162cdb371..a599b0ecdb 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* How much nesting do we support? */ #define ACPIGEN_LENSTACK_SIZE 10 diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 294c6c346b..ecac3fefb8 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index fef5ce9240..d48d28fbb0 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index ada49d0368..ae14bc200a 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 325673162c..5d3ba4ec78 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -1,16 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. * diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index b6b31af89f..e5de25596f 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 887243964e..1148e058cf 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 2e29112467..5e5493a355 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file is included inside a SECTIONS block */ . = CONFIG_DCACHE_RAM_BASE; diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index b20eb67b9b..55215f651a 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index d93bed74a4..675d5edbb3 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 30d2cca87a..4c1bce05d6 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 0fd0af016f..1646b44ecc 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index f92f305d6f..4ac1359faa 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index a599e798c1..e238fe77a1 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 8c2878481b..e9b260decf 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c index 27e4af3d47..511e689c52 100644 --- a/src/arch/x86/gdt.c +++ b/src/arch/x86/gdt.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index f66cd4366b..1bf3910b49 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -1,15 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + .code32 .section ".text._gdt_", "ax", @progbits diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 6151990e3a..dd447e647f 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index 2a50f9ca4f..31d573832a 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ SECTIONS { . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; diff --git a/src/arch/x86/idt.S b/src/arch/x86/idt.S index 9c36d81de7..0d6101ba03 100644 --- a/src/arch/x86/idt.S +++ b/src/arch/x86/idt.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .section ".text._idt", "ax", @progbits #ifdef __x86_64__ diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 68475c157e..d5040adb24 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * coreboot ACPI support - headers and defines. diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 90af81ba21..e9c5cd4de2 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ACPI_DEVICE_H #define __ACPI_DEVICE_H diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h index 784b5a39a2..d8d62d47b5 100644 --- a/src/arch/x86/include/arch/acpi_ivrs.h +++ b/src/arch/x86/include/arch/acpi_ivrs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * AMD I/O Virtualization Technology (IOMMU) diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h index f23aacd539..944eb3154a 100644 --- a/src/arch/x86/include/arch/acpi_pld.h +++ b/src/arch/x86/include/arch/acpi_pld.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ACPI_PLD_H #define __ACPI_PLD_H diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 34c5197468..4aba5f9024 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LIBACPI_H #define LIBACPI_H diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h index 49ed6db632..c51c12b6e3 100644 --- a/src/arch/x86/include/arch/acpigen_dsm.h +++ b/src/arch/x86/include/arch/acpigen_dsm.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ACPIGEN_DSM_H__ #define __ARCH_ACPIGEN_DSM_H__ diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 644f24e50c..3e7b0b560c 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BERT_STORAGE_H_ #define _BERT_STORAGE_H_ diff --git a/src/arch/x86/include/arch/boot/boot.h b/src/arch/x86/include/arch/boot/boot.h index 0c9053fa15..bfa2351130 100644 --- a/src/arch/x86/include/arch/boot/boot.h +++ b/src/arch/x86/include/arch/boot/boot.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ASM_I386_BOOT_H #define ASM_I386_BOOT_H diff --git a/src/arch/x86/include/arch/bootblock.h b/src/arch/x86/include/arch/bootblock.h index 1ca4a762de..a4dcb3a642 100644 --- a/src/arch/x86/include/arch/bootblock.h +++ b/src/arch/x86/include/arch/bootblock.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_BOOTBLOCK_H__ #define __ARCH_BOOTBLOCK_H__ diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h index 37cb8b6df6..096ef7585a 100644 --- a/src/arch/x86/include/arch/byteorder.h +++ b/src/arch/x86/include/arch/byteorder.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BYTEORDER_H #define _BYTEORDER_H diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h index 36476fd0ab..5333c61e1f 100644 --- a/src/arch/x86/include/arch/cache.h +++ b/src/arch/x86/include/arch/cache.h @@ -1,32 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H diff --git a/src/arch/x86/include/arch/cbconfig.h b/src/arch/x86/include/arch/cbconfig.h index b222ef3603..21b49213e3 100644 --- a/src/arch/x86/include/arch/cbconfig.h +++ b/src/arch/x86/include/arch/cbconfig.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_CBCONFIG_H_ #define _ARCH_CBCONFIG_H_ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 59eb9ad32d..e149c38535 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_CPU_H #define ARCH_CPU_H diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 6ee3332540..637ecc959a 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_EBDA_H #define __ARCH_EBDA_H diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index df6f9e5ee7..86cc7d5c69 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -1,29 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This file is part of the coreboot project. */ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 69f6d7d671..01a20e5820 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h index a3f5c853f3..acb43652e4 100644 --- a/src/arch/x86/include/arch/hlt.h +++ b/src/arch/x86/include/arch/hlt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_HLT_H #define ARCH_HLT_H diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index baf6b7829a..cebfcbbe54 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTERRUPT_H #define INTERRUPT_H diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 43cfc1be12..8da75543cf 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_IO_H__ #define __ARCH_IO_H__ diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 5938cdc51d..078b2122df 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __I386_ARCH_IOAPIC_H #define __I386_ARCH_IOAPIC_H diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 11da892af0..2eea83faaf 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H diff --git a/src/arch/x86/include/arch/memory_clear.h b/src/arch/x86/include/arch/memory_clear.h index 2b887b848f..960fe5d42d 100644 --- a/src/arch/x86/include/arch/memory_clear.h +++ b/src/arch/x86/include/arch/memory_clear.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MEMORY_CLEAR_H #define MEMORY_CLEAR_H diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index efdbe2752b..1d7aeea2d3 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 1e6934abcc..c2f85a8df9 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PCI_IO_CFG_H #define _PCI_IO_CFG_H diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index e706216586..f11f612059 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_I386_PCI_OPS_H #define ARCH_I386_PCI_OPS_H diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 60495a1d46..0e1f131b2e 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H diff --git a/src/arch/x86/include/arch/ram_segs.h b/src/arch/x86/include/arch/ram_segs.h index 39d0c64896..0543b22007 100644 --- a/src/arch/x86/include/arch/ram_segs.h +++ b/src/arch/x86/include/arch/ram_segs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAM_SEGS_H #define RAM_SEGS_H diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 8cf0d48486..b47a787470 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_REGISTERS_H #define __ARCH_REGISTERS_H diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h index c11def6b02..da9623cd22 100644 --- a/src/arch/x86/include/arch/rom_segs.h +++ b/src/arch/x86/include/arch/rom_segs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ROM_SEGS_H #define ROM_SEGS_H diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 83d15e420b..0f9a3589bd 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_ROMSTAGE_H__ #define __ARCH_ROMSTAGE_H__ diff --git a/src/arch/x86/include/arch/smp/atomic.h b/src/arch/x86/include/arch/smp/atomic.h index 75650c7f98..7a84e1f83c 100644 --- a/src/arch/x86/include/arch/smp/atomic.h +++ b/src/arch/x86/include/arch/smp/atomic.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_SMP_ATOMIC_H #define ARCH_SMP_ATOMIC_H diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 7500945c42..75f1be76d4 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ASM_MPSPEC_H #define __ASM_MPSPEC_H diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 8bdb125223..c45431d734 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 0726cac1b1..1e3cb97f43 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index efe10fe524..6f06baf51e 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ARCH_SYMBOLS_H #define __ARCH_SYMBOLS_H diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h index e05c2e1c34..9b2f0539a8 100644 --- a/src/arch/x86/include/cf9_reset.h +++ b/src/arch/x86/include/cf9_reset.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef X86_CF9_RESET_H #define X86_CF9_RESET_H diff --git a/src/arch/x86/include/smm.h b/src/arch/x86/include/smm.h index 320bac61aa..e2eb40c14b 100644 --- a/src/arch/x86/include/smm.h +++ b/src/arch/x86/include/smm.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 757f7ee0fd..5293000463 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 80f5989786..ec781b0448 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index eff3738a43..05efac6db5 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/memmove.c b/src/arch/x86/memmove.c index 2cd7e48ded..20a5f1114f 100644 --- a/src/arch/x86/memmove.c +++ b/src/arch/x86/memmove.c @@ -1,17 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * This file is derived from memcpy_32.c in the Linux kernel. - * Unlike many coreboot files, this file may not be re-licensed as GPL V3 */ #include diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 0767683d12..4f92a74a6e 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the GNU C Library. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* From glibc-2.14, sysdeps/i386/memset.c */ diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 74764fc4bf..2358d7201d 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index eeca81606e..edb607ea8e 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index ab3793c3a7..b8d2e256c7 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + #include #include #include diff --git a/src/arch/x86/post.c b/src/arch/x86/post.c index b9cd26b50a..0aaf9b7190 100644 --- a/src/arch/x86/post.c +++ b/src/arch/x86/post.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index add72c2cda..a3a521b374 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index ee2c01b2fc..2efa7ac178 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc index 4036ff9862..4901dc52a1 100644 --- a/src/arch/x86/prologue.inc +++ b/src/arch/x86/prologue.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c index bf9e687ae1..c526975338 100644 --- a/src/arch/x86/rdrand.c +++ b/src/arch/x86/rdrand.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cd4518d13..c047d75a92 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 8ecf86dc3f..066e635675 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index d92d8fdeca..4f98781757 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/arch/x86/thread_switch.S b/src/arch/x86/thread_switch.S index 1c1dedef1b..133be1b5fb 100644 --- a/src/arch/x86/thread_switch.S +++ b/src/arch/x86/thread_switch.S @@ -1,15 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + .code32 .text diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 8cf0f96e31..d156f1d383 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/timestamp.inc b/src/arch/x86/timestamp.inc index 14369066be..052106dc4e 100644 --- a/src/arch/x86/timestamp.inc +++ b/src/arch/x86/timestamp.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Store the initial timestamp for booting in mmx registers. This works diff --git a/src/arch/x86/verstage.c b/src/arch/x86/verstage.c index ad13e60f0c..2be33e230c 100644 --- a/src/arch/x86/verstage.c +++ b/src/arch/x86/verstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index 187b96cab9..cfe0d64539 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define WAKEUP_BASE 0x600 #define RELOCATED(x) (x - __wakeup + WAKEUP_BASE) diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index ded65587ec..4a99add080 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define CBFS_HEADER_PTR 0xfffffffc diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 300fde534c..befdf3cd68 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -6,14 +6,11 @@ # Directories requiring SPDX Identifiers only util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY +util/lint/lint-000-license-headers "src/arch" SPDX_ONLY util/lint/lint-000-license-headers "src/superio" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/arm" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/arm64" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/ppc64" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch/riscv" SPDX_ONLY # Top level -util/lint/lint-000-license-headers "src/arch/x86 src/commonlib src/console \ +util/lint/lint-000-license-headers "src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge" From 17dda3adb3850bdebc94aca693405e753f6910ab Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 3 Mar 2020 17:05:25 +0000 Subject: [PATCH 0278/1463] Revert "i82371eb: Drop support for older PIIX chips" This reverts commit 2b9004de602f98a404b17584ab3e1451f165c1f4. Reason for revert: QEMU emulates that chipset and with that commit a Linux guest kernel can't find IDE devices anymore. Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39238 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Reviewed-by: Keith Hui --- src/southbridge/intel/i82371eb/i82371eb.c | 19 ++++++++- src/southbridge/intel/i82371eb/ide.c | 51 +++++++++++++++++++++++ src/southbridge/intel/i82371eb/isa.c | 6 +++ src/southbridge/intel/i82371eb/usb.c | 9 ++++ 4 files changed, 83 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 02812ce40c..898cdffc25 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -14,9 +14,22 @@ * GNU General Public License for more details. */ -/* Note: This code supports the 82371AB/EB/MB. */ +/* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */ /* Datasheets: + * - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR + * - URL: http://www.intel.com/design/intarch/datashts/290550.htm + * - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf + * - Date: April 1997 + * - Order Number: 290550-002 + * + * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator + * Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm + * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf + * - Date: March 1998 + * - Order Number: 297658-004 + * * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm @@ -31,8 +44,10 @@ * - Order Number: 297738-017 */ +/* TODO: List the other datasheets. */ + #include const struct chip_operations southbridge_intel_i82371eb_ops = { - CHIP_NAME("Intel 82371AB/EB/MB Southbridge") + CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") }; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 1b8136a9ca..7a72a6552d 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -118,6 +118,18 @@ static void ide_init_udma33(struct device *dev) } } +/** + * IDE init for the Intel 82371FB/SB IDE controller. + * + * These devices do not support UDMA/33, so don't attempt to enable it. + * + * @param dev The device to use. + */ +static void ide_init_i82371fb_sb(struct device *dev) +{ + ide_init_enable(dev); +} + /** * IDE init for the Intel 82371AB/EB/MB IDE controller. * @@ -129,6 +141,17 @@ static void ide_init_i82371ab_eb_mb(struct device *dev) ide_init_udma33(dev); } +/* Intel 82371FB/SB */ +static const struct device_operations ide_ops_fb_sb = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init_i82371fb_sb, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + /* Intel 82371AB/EB/MB */ static const struct device_operations ide_ops_ab_eb_mb = { .read_resources = pci_dev_read_resources, @@ -140,6 +163,34 @@ static const struct device_operations ide_ops_ab_eb_mb = { .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; +/* Intel 82371FB (PIIX) */ +static const struct pci_driver ide_driver_fb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, +}; + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver ide_driver_sb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, +}; + +/* Intel 82371MX (MPIIX) */ +static const struct pci_driver ide_driver_mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, +}; + +/* Intel 82437MX (part of the 430MX chipset) */ +static const struct pci_driver ide_driver_82437mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, +}; + /* Intel 82371AB/EB/MB */ static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { .ops = &ide_ops_ab_eb_mb, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bdad959100..3d1970c0ee 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -145,3 +145,9 @@ static const struct pci_driver isa_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; + +static const struct pci_driver isa_SB_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, +}; diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 38ab167733..80b19a187e 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -43,6 +43,15 @@ static const struct device_operations usb_ops = { .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; +/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver usb_driver_sb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_USB, +}; + /* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ /* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = { From ad64781dee9cf513b60d72c0d3ec1c67bac7362d Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 3 Mar 2020 10:03:57 -0800 Subject: [PATCH 0279/1463] soc/intel/tigerlake: Avoid NULL pointer dereference Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference. BUG=CID 1353148 TEST=Built and boot up to kernel. Change-Id: Ic0ad1ec79c950a3c17feccdde4f87f4a107fe8c0 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/39260 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/fsp_params_jsl.c | 11 ++++++++--- src/soc/intel/tigerlake/fsp_params_tgl.c | 10 +++++++--- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 8eb3fbacaf..6cb3b6718d 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -158,9 +158,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!dev || !xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 0587b88868..9e22b58e7c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -115,9 +115,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; From efc4be6bf1b132f8d280b7b840049ea6677405d3 Mon Sep 17 00:00:00 2001 From: Marcello Sylvester Bauer Date: Wed, 4 Mar 2020 12:32:14 +0100 Subject: [PATCH 0280/1463] sb/intel/common/firmware/Makefile.inc: use ifdtool --output flag Use the ifdtool --output flag to modify coreboot.pre inplace, instead of using the `mv` command to get the same result. In this way the stdout will make more sense in the build context. Change-Id: I6dacc8b39052801c770c02fa2aa1b526747ae496 Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/common/firmware/Makefile.inc | 21 +++++++++++-------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 5f3212f487..2352636977 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -55,8 +55,8 @@ ifeq ($(CONFIG_HAVE_ME_BIN),y) $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) \ -i ME:$(CONFIG_ME_BIN_PATH) \ + -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_CHECK_ME),y) util/me_cleaner/me_cleaner.py -c $(obj)/coreboot.pre > /dev/null @@ -72,36 +72,39 @@ ifeq ($(CONFIG_HAVE_GBE_BIN),y) $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) \ -i GbE:$(CONFIG_GBE_BIN_PATH) \ + -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_HAVE_EC_BIN),y) printf " IFDTOOL ec.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) \ -i EC:$(CONFIG_EC_BIN_PATH) \ + -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) printf " IFDTOOL Locking Management Engine\n" $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre + $(IFDTOOL_USE_CHIPSET) -l \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre endif ifeq ($(CONFIG_UNLOCK_FLASH_REGIONS),y) printf " IFDTOOL Unlocking Management Engine\n" $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre + $(IFDTOOL_USE_CHIPSET) -u \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre endif ifeq ($(CONFIG_EM100),y) printf " IFDTOOL Setting EM100 mode\n" $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) --em100 $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre + $(IFDTOOL_USE_CHIPSET) --em100 \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre endif warn_intel_firmware: From 5e5e789f9b115f7fb1e7c453cdf20df088ac893d Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 7 Feb 2020 09:40:42 -0600 Subject: [PATCH 0281/1463] nb/intel/haswell/peg: Add PEG driver stub This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is unable to read the VBIOS of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With this patch DRM works correctly with both the Nouveau driver and the Nvidia proprietary driver. Windows 10 1909 also tested but generates bluescreen once GPU driver is loaded. Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/mainboard/lenovo/t440p.md | 6 +- src/northbridge/intel/haswell/Makefile.inc | 1 + .../intel/haswell/acpi/haswell.asl | 1 + .../intel/haswell/acpi/hostbridge.asl | 3 +- src/northbridge/intel/haswell/acpi/peg.asl | 60 +++++++++++++ src/northbridge/intel/haswell/pcie.c | 88 +++++++++++++++++++ 6 files changed, 154 insertions(+), 5 deletions(-) create mode 100644 src/northbridge/intel/haswell/acpi/peg.asl create mode 100644 src/northbridge/intel/haswell/pcie.c diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md index 98c1da54ac..fb0187075c 100644 --- a/Documentation/mainboard/lenovo/t440p.md +++ b/Documentation/mainboard/lenovo/t440p.md @@ -36,10 +36,7 @@ the laptop able to power on. - Cannot get the mainboard serial number from the mainboard: the OEM UEFI firmware gets the serial number from an "emulated EEPROM" via I/O port 0x1630/0x1634, but it's still unknown how to make it work - -## Untested - -- the dGPU model +- The dGPU does not currently work in Windows. ## Working @@ -61,6 +58,7 @@ the laptop able to power on. - CMOS options: wlan, trackpoint, fn_ctrl_swap - internal flashing when IFD is unlocked - using `me_cleaner` +- dGPU (must be enabled in CMOS options) [Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p [Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp40a25467_04.pdf diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b9863367c9..73a20f2dfb 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += bootblock.c ramstage-y += memmap.c ramstage-y += northbridge.c +ramstage-y += pcie.c ramstage-y += gma.c ramstage-y += acpi.c diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 45ebff29f1..2db72d7842 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@ #include "../haswell.h" #include "hostbridge.asl" +#include "peg.asl" #include /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 19d788ce26..d567701cb7 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -36,7 +36,8 @@ Device (MCHC) MHEN, 1, // Enable , 13, // MHBR, 22, // MCHBAR - + Offset (0x54), + DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl new file mode 100644 index 0000000000..c4af375422 --- /dev/null +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + Method (_STA) + { + Return (((\_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG1) +{ + Name (_ADR, 0x00010001) + + Method (_STA) + { + Return (((\_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG2) +{ + Name (_ADR, 0x00010002) + + Method (_STA) + { + Return (((\_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c new file mode 100644 index 0000000000..b3a21bfc3e --- /dev/null +++ b/src/northbridge/intel/haswell/pcie.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static void pcie_disable(struct device *dev) +{ + printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev)); + dev->enabled = 0; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *pcie_acpi_name(const struct device *dev) +{ + assert(dev); + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + assert(dev->bus); + if (dev->bus->secondary == 0) + switch (dev->path.pci.devfn) { + case PCI_DEVFN(1, 0): + return "PEGP"; + case PCI_DEVFN(1, 1): + return "PEG1"; + case PCI_DEVFN(1, 2): + return "PEG2"; + }; + + struct device *const port = dev->bus->dev; + assert(port); + assert(port->bus); + + if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && + port->bus->secondary == 0 && + (port->path.pci.devfn == PCI_DEVFN(1, 0) || + port->path.pci.devfn == PCI_DEVFN(1, 1) || + port->path.pci.devfn == PCI_DEVFN(1, 2))) + return "DEV0"; + + return NULL; +} +#endif + +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .disable = pcie_disable, + .init = pci_dev_init, + .ops_pci = &pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = pcie_acpi_name, +#endif +}; + +static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; From 1f088c87572697a4c31257d8d8063f2c10234750 Mon Sep 17 00:00:00 2001 From: Jonas Moehle Date: Wed, 25 Dec 2019 03:40:51 +0100 Subject: [PATCH 0282/1463] mb/lenovo/*: Add support for VBOOT on 12MiB devices Enable VBOOT support on all devices that have a 12 MiB flash, using RW_MAIN_A + RW_MAIN_B partition, allowing the use of tianocore payload in both RW_MAIN_A, RW_MAIN_B and WP_RO. * Add VBNV section to cmos.layout * Add FMAP for VBOOT * Select Kconfigs for VBOOT * Enable VBOOT_SLOTS_RW_AB by default The VBNV is intentionally not covered by the CMOS checksum. Tested on x230 and T440p. Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Signed-off-by: Patrick Rudolph Signed-off-by: Jonas Moehle Reviewed-on: https://review.coreboot.org/c/coreboot/+/32617 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: Felix Singer --- src/mainboard/lenovo/t430/Kconfig | 19 +++++++++++ src/mainboard/lenovo/t430/cmos.layout | 3 ++ src/mainboard/lenovo/t430/vboot-rwab.fmd | 34 +++++++++++++++++++ src/mainboard/lenovo/t430s/Kconfig | 19 +++++++++++ src/mainboard/lenovo/t430s/cmos.layout | 3 ++ src/mainboard/lenovo/t430s/vboot-rwab.fmd | 34 +++++++++++++++++++ src/mainboard/lenovo/t440p/Kconfig | 19 +++++++++++ src/mainboard/lenovo/t440p/cmos.layout | 3 ++ src/mainboard/lenovo/t440p/vboot-rwab.fmd | 34 +++++++++++++++++++ src/mainboard/lenovo/t530/Kconfig | 19 +++++++++++ src/mainboard/lenovo/t530/cmos.layout | 3 ++ src/mainboard/lenovo/t530/vboot-rwab.fmd | 34 +++++++++++++++++++ src/mainboard/lenovo/x131e/Kconfig | 19 +++++++++++ src/mainboard/lenovo/x131e/cmos.layout | 3 ++ src/mainboard/lenovo/x131e/vboot-rwab.fmd | 34 +++++++++++++++++++ src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 19 +++++++++++ .../lenovo/x1_carbon_gen1/cmos.layout | 3 ++ .../lenovo/x1_carbon_gen1/vboot-rwab.fmd | 34 +++++++++++++++++++ src/mainboard/lenovo/x230/Kconfig | 19 +++++++++++ src/mainboard/lenovo/x230/cmos.layout | 3 ++ src/mainboard/lenovo/x230/vboot-rwab.fmd | 34 +++++++++++++++++++ 21 files changed, 392 insertions(+) create mode 100644 src/mainboard/lenovo/t430/vboot-rwab.fmd create mode 100644 src/mainboard/lenovo/t430s/vboot-rwab.fmd create mode 100644 src/mainboard/lenovo/t440p/vboot-rwab.fmd create mode 100644 src/mainboard/lenovo/t530/vboot-rwab.fmd create mode 100644 src/mainboard/lenovo/x131e/vboot-rwab.fmd create mode 100644 src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd create mode 100644 src/mainboard/lenovo/x230/vboot-rwab.fmd diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 78da38502b..a73a1b2225 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -26,6 +26,25 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT + config MAINBOARD_DIR string default "lenovo/t430" diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index 1b50e7fa74..f9757f0794 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -80,6 +80,9 @@ entries #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/t430/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 36f03ae468..5162e0568e 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -27,6 +27,25 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT + config MAINBOARD_DIR string default "lenovo/t430s" diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 97d97ed349..891a29414c 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -80,6 +80,9 @@ entries #436 4 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430s/vboot-rwab.fmd b/src/mainboard/lenovo/t430s/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/t430s/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index faaa73a78c..95cb1dc607 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -23,6 +23,25 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select MAINBOARD_USES_IFD_GBE_REGION +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT + config MAINBOARD_DIR string default "lenovo/t440p" diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 9c09104d55..be0b5031bd 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -73,6 +73,9 @@ entries #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/t440p/vboot-rwab.fmd b/src/mainboard/lenovo/t440p/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/t440p/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 04b752804c..233d4d3f60 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -28,6 +28,25 @@ config BOARD_LENOVO_BASEBOARD_T530 if BOARD_LENOVO_BASEBOARD_T530 +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT + config VARIANT_DIR string default "t530" if BOARD_LENOVO_T530 diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 3400a4d4c7..0c8c546e11 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -81,6 +81,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t530/vboot-rwab.fmd b/src/mainboard/lenovo/t530/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/t530/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 2cf3a8f95d..352be84050 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -21,6 +21,25 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE select INTEL_GMA_HAVE_VBT +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT + config MAINBOARD_DIR string default "lenovo/x131e" diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 93c74fbdcc..41b8354dd3 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -79,6 +79,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x131e/vboot-rwab.fmd b/src/mainboard/lenovo/x131e/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/x131e/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 91ba20817c..f49805c36a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -26,6 +26,25 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT + config MAINBOARD_DIR string default "lenovo/x1_carbon_gen1" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index bb252610c1..55a8a58962 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -80,6 +80,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index e7edf6bb61..bf70950532 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -27,6 +27,25 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT + config MAINBOARD_DIR string default "lenovo/x230" diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 27197fb4b8..99034009a4 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -80,6 +80,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x230/vboot-rwab.fmd b/src/mainboard/lenovo/x230/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/x230/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} From 1e67a04ff6e2dc2d337e54f61905fe3da6a197e9 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 4 Mar 2020 16:35:36 -0800 Subject: [PATCH 0283/1463] mb/google/volteer: make variant_early_gpio_table weak Declare variant_early_gpio_table() weak to allow override by variants. BUG=b:148385924, b:150810535 TEST=none Change-Id: Ife5e3b75256f71ecd763c4000fd2c7d7c927bb64 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39300 Reviewed-by: Furquan Shaikh Reviewed-by: caveh jalali Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 2dc340f17c..3f1f2b0e0f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -452,7 +452,7 @@ const struct pad_config *__weak variant_override_gpio_table(size_t *num) return NULL; } -const struct pad_config *variant_early_gpio_table(size_t *num) +const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; From 44fc40e09186cd24df873df6ca4d82af46efc0f4 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 4 Mar 2020 16:43:22 -0800 Subject: [PATCH 0284/1463] mb/google/volteer: add new ripto variant Add a new ripto variant based off of the volteer baseboard design. BUG=b:148385924, b:150810535 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image and verify ripto boots to the kernel. Change-Id: If7606588147500a465f16c7846e2c8429ece93ec Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301 Tested-by: build bot (Jenkins) Reviewed-by: caveh jalali Reviewed-by: Furquan Shaikh Reviewed-by: Srinidhi N Kaushik --- src/mainboard/google/volteer/Kconfig | 4 +- src/mainboard/google/volteer/Kconfig.name | 4 + .../volteer/variants/ripto/Makefile.inc | 20 + .../google/volteer/variants/ripto/gpio.c | 467 ++++++++++++++++++ .../variants/ripto/include/variant/ec.h | 21 + .../variants/ripto/include/variant/gpio.h | 28 ++ .../volteer/variants/ripto/overridetree.cb | 6 + 7 files changed, 549 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/volteer/variants/ripto/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/ripto/gpio.c create mode 100644 src/mainboard/google/volteer/variants/ripto/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h create mode 100644 src/mainboard/google/volteer/variants/ripto/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 699cdeae8d..5bc487686e 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -51,10 +51,11 @@ config MAINBOARD_DIR config MAINBOARD_FAMILY string - default "Google_Volteer" if BOARD_GOOGLE_VOLTEER + default "Google_Volteer" config MAINBOARD_PART_NUMBER string + default "Ripto" if BOARD_GOOGLE_RIPTO default "Volteer" if BOARD_GOOGLE_VOLTEER config MAX_CPUS @@ -67,6 +68,7 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR string + default "ripto" if BOARD_GOOGLE_RIPTO default "volteer" if BOARD_GOOGLE_VOLTEER endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index a3fac9c74c..d60dfb4807 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -3,3 +3,7 @@ comment "Volteer" config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_RIPTO + bool "-> Ripto" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc new file mode 100644 index 0000000000..95401499f7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000 + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c new file mode 100644 index 0000000000..c621b1dffe --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/gpio.c @@ -0,0 +1,467 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> VRALERT_L */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> EN_USB_CAM_PWR */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ + PAD_CFG_GPI(GPP_C11, NONE, DEEP), + /* C12 : UART1_RXD ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_NC(GPP_D0, UP_20K), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), + /* D4 : IMGCLKOUT0 ==> CAM_CVF_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> CVF_ACE_ISH_INT_L */ + PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), + /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT), + /* F9 : Reserved ==> NC */ + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> SAR1_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, PLTRST, EDGE_SINGLE), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> PCH_I2C2_SAR0_WLAN_HDMI_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C2_SCL ==> PCH_I2C2_SAR0_WLAN_HDMI_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> WWAN_CONFIG2 */ + PAD_CFG_GPI(GPP_H14, NONE, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_CAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, PLTRST), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> HDA_RST_L */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, RSMRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h new file mode 100644 index 0000000000..3655f14d77 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h new file mode 100644 index 0000000000..3a3282ee7c --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end From 6704049fc911eba9f4e6dc36a916eccffd04a15e Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 16 Feb 2020 11:51:57 +0300 Subject: [PATCH 0285/1463] soc/apl: add options to override USB port config Allows to override the PortUsb20Enable and PortUsb30Enable FSP options (which are set to 1 by default) to enable/disable USB ports if the usb_config_override flag is set to "1". Therefore, these changes will not affect other boards with an Apollo Lake processor. Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38815 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/chip.c | 21 ++++++++++++++++++-- src/soc/intel/apollolake/chip.h | 5 +++++ src/soc/intel/apollolake/include/soc/usb.h | 23 ++++++++++++++++++++++ 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 37fdfff90b..4eabf8a012 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -558,11 +558,18 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig) static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these - fields in FspsUpd.h yet */ +#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */ uint8_t port; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { + if (cfg->usb_config_override) { + if (!cfg->usb2_port[port].enable) + continue; + + silconfig->PortUsb20Enable[port] = 1; + silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin; + } + if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) silconfig->PortUsb20PerPortTxPeHalf[port] = cfg->usb2eye[port].Usb20PerPortTxPeHalf; @@ -591,6 +598,16 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config silconfig->PortUsb20HsNpreDrvSel[port] = cfg->usb2eye[port].Usb20HsNpreDrvSel; } + + if (cfg->usb_config_override) { + for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) { + if (!cfg->usb3_port[port].enable) + continue; + + silconfig->PortUsb30Enable[port] = 1; + silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin; + } + } #endif } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index e5045d01b1..40cd39b46b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -136,6 +136,11 @@ struct soc_intel_apollolake_config { /* USB2 eye diagram settings per port */ struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; + /* Override USB port configuration */ + uint8_t usb_config_override; + struct usb_port_config usb2_port[APOLLOLAKE_USB2_PORT_MAX]; + struct usb_port_config usb3_port[APOLLOLAKE_USB3_PORT_MAX]; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 28cad37f58..11dec48eb6 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -21,6 +21,12 @@ #include #define APOLLOLAKE_USB2_PORT_MAX 8 +#define APOLLOLAKE_USB3_PORT_MAX 6 + +struct usb_port_config { + uint8_t enable; + uint8_t oc_pin; +}; struct usb2_eye_per_port { uint8_t Usb20PerPortTxPeHalf; @@ -33,4 +39,21 @@ struct usb2_eye_per_port { uint8_t Usb20OverrideEn; }; +/* USB overcurrent pins definition */ +enum { + OC0 = 0, + OC1 = 1, + OC_SKIP = 2, +}; + +#define PORT_EN(pin) { \ + .enable = 1, \ + .oc_pin = (pin), \ +} + +#define PORT_DIS { \ + .enable = 0, \ + .oc_pin = OC_SKIP, \ +} + #endif /* _SOC_APOLLOLAKE_USB_H_ */ From 3b89ebd8913427b018ca895d7a0683f403029bdf Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Tue, 25 Feb 2020 19:32:31 +0300 Subject: [PATCH 0286/1463] mb/up/squared: remove NpkEn option from romstage There is no need to set the NpkEn option to disable the NPK device, since it has already been done in the devicetree. Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39120 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/up/squared/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index f9f0cfc424..55235a8d20 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -169,7 +169,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) config->RmtCheckRun = 0x3; // 0x0 config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 config->EnhancePort8xhDecoding = 0x0; // 0x1 - config->NpkEn = 0x0; // 0x3 config->PrimaryVideoAdaptor = 0x2; // 0x0 config->Ch0_DeviceWidth = 0x1; // 0x0 From bb65180ee8b2cb26ac75fe6ccc9525ecc060c1e3 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Wed, 26 Feb 2020 12:39:09 +0300 Subject: [PATCH 0287/1463] mb/up/squared: move USB config to device tree Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39134 Reviewed-by: Felix Singer Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/up/squared/devicetree.cb | 14 ++++++++++++++ src/mainboard/up/squared/ramstage.c | 10 ---------- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 66be75cc05..d7281a6cd8 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -1,5 +1,19 @@ chip soc/intel/apollolake + # Override USB port configuration + register "usb_config_override" = "1" + # USB 2.0 + register "usb2_port[0]" = "PORT_EN(OC0)" + register "usb2_port[1]" = "PORT_EN(OC1)" + register "usb2_port[2]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC1)" + register "usb2_port[4]" = "PORT_EN(OC1)" + register "usb2_port[5]" = "PORT_EN(OC1)" + register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + # USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + register "enable_vtd" = "1" device cpu_cluster 0 on diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index 637b8d87c9..9ae30ebb16 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -80,14 +80,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; // 0x1 silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; // 0x0 silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; // 0x0 - - silconfig->PortUs30bOverCurrentPin[0] = 0x0; // 0x1 - - silconfig->PortUs20bOverCurrentPin[1] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[2] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[3] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[4] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[5] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[6] = 0x2; // 0x0 - silconfig->PortUs20bOverCurrentPin[7] = 0x2; // 0x0 } From 998737df71c3c2ed97da36305ef065eb280cf2b2 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Fri, 21 Feb 2020 12:00:15 +0800 Subject: [PATCH 0288/1463] soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switch Because eMCP and discrete DDR devices have different DVFS tables, their EMI bandwidth thresholds should also be different. When the EMI total bandwidth reaches the threshold, the system will notify DVFS module to perform DVFS switch for system performance in low power states. This patch increases the threshold from 0xa to 0xd for eMCP DDR devices so that DVFS switch will be less likely to happen. The register table of EMI_BWCT0 is incorrect in the datasheet. According to the hardware design, BW_2ND_INT_BW_THR should be in bits [30:24] instead of [22:16]. However, the logic in DRAM driver is correct, aligned with the hardware design, so we don't need to correct it. BRANCH=kukui BUG=b:142358843 TEST=bootup pass Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39034 Reviewed-by: Hung-Te Lin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/emi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 07d1cc8ee5..e7cbda15d9 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -299,8 +299,10 @@ static void emi_init2(const struct sdram_params *params) setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); - - write32(&emi_regs->bwct0, 0x0a000705); + if (CONFIG(MT8183_DRAM_EMCP)) + write32(&emi_regs->bwct0, 0x0d000705); + else + write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0); /* EMI QoS 0.5 */ From 25930f4a3f7c518afadeb1d0298f9750707748e8 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 30 Dec 2019 13:19:05 +0800 Subject: [PATCH 0289/1463] soc/mediatek/mt8183: Do TX tracking for DRAM DVFS feature The TX window will offset to edge during DVFS switch, which may cause TX data transmission error and random kernel crash. Therefore, use the standard dqsosc (DQS Oscillator) for TX window tracking. BUG=b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81 Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37996 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 4 + .../mt8183/dramc_pi_calibration_api.c | 620 +++++++++++++++++- src/soc/mediatek/mt8183/emi.c | 9 +- .../mt8183/include/soc/dramc_pi_api.h | 5 + .../mt8183/include/soc/dramc_register.h | 152 +++++ 5 files changed, 776 insertions(+), 14 deletions(-) diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 1eb86f406f..c7d6c748e7 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -427,6 +427,9 @@ void dramc_runtime_config(void) transfer_pll_to_spm_control(); setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + dramc_hw_dqsosc(chn); + /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) dramc_rx_input_delay_tracking(chn); @@ -498,6 +501,7 @@ void dramc_runtime_config(void) (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } + dramc_dqs_precalculation_preset(); enable_emi_dcm(); dramc_enable_dramc_dcm(); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 0ec0193664..4ccc7fcb22 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -105,6 +105,25 @@ void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off) CKECTRL_CKEFIXOFF, cke_off); } +static u16 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + u16 value; + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 1); + + /* Wait until MRW command fired */ + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE) + == 0) + udelay(1); + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_REG); + + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 0); + dramc_dbg("Read MR%d =%#x\n", mr_idx, value); + + return value; +} + void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) { u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); @@ -117,7 +136,7 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) /* Wait MRW command fired */ while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) == 0) - ; + udelay(1); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0); write32(&ch[chn].ao.ckectrl, ckectrl_bak); @@ -1577,17 +1596,9 @@ static void dramc_set_tx_dly_center(struct per_byte_dly *center_dly, } } -static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, - struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group, - u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params, - const bool fast_calib) +static u32 get_freq_group_clock(u8 freq_group) { - int index, clock_rate; - u8 use_delay_cell; - u32 byte_dly_cell[DQS_NUMBER] = {0}; - struct per_byte_dly center_dly[DQS_NUMBER]; - u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH]; - + u32 clock_rate = 0; /* * The clock rate is usually (frequency / 2 - delta), where the delta @@ -1609,9 +1620,27 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, break; default: die("Invalid DDR frequency group %u\n", freq_group); - return; + break; } + return clock_rate; +} + +static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, + struct win_perbit_dly *vref_dly, + enum CAL_TYPE type, u8 freq_group, + u16 *tx_dq_precal_result, u16 dly_cell_unit, + const struct sdram_params *params, + const bool fast_calib) +{ + int index, clock_rate; + u8 use_delay_cell; + u32 byte_dly_cell[DQS_NUMBER] = { 0 }; + struct per_byte_dly center_dly[DQS_NUMBER]; + u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH]; + + clock_rate = get_freq_group_clock(freq_group); + if (type == TX_WIN_DQ_ONLY && get_freq_fsq(freq_group) == FSP_1) use_delay_cell = 1; else @@ -1653,7 +1682,7 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, dq_delay_cell[index] = ((tune_diff * 100000000) / (clock_rate * 64)) / dly_cell_unit; byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4)); - dramc_show("u1DelayCellOfst[%d]=%d cells (%d PI)\n", + dramc_dbg("u1DelayCellOfst[%d]=%d cells (%d PI)\n", index, dq_delay_cell[index], tune_diff); } } @@ -2104,6 +2133,566 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) (0xff << 8) | (0x9 << 2) | ROEN); } +static void start_dqsosc(u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 1); + if (!wait_us(100, READ32_BITFIELD(&ch[chn].nao.spcmdresp, + SPCMDRESP_DQSOSCEN_RESPONSE))) { + dramc_err("start dqsosc timed out\n"); + return; + } + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 0); +} + +static void dqsosc_auto(u8 chn, u8 rank, u8 freq_group, + u16 *osc_thrd_inc, u16 *osc_thrd_dec) +{ + u8 mr23 = MR23_DEFAULT_VALUE; + u16 mr18, mr19; + u16 dqsosc_cnt[2], dqs_cnt, dqsosc, thrd_inc, thrd_dec; + u32 clock_rate, tck; + + struct reg_value regs_bak[] = { + {&ch[chn].ao.mrs}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_DQSOSC2RK, 0); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + dramc_mode_reg_write(chn, 23, mr23); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv, + SHU_SCINTV_DQSOSCENDIS, 1); + + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 1); + dramc_cke_fix_onoff(chn, true, false); + + start_dqsosc(chn); + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + + mr18 = dramc_mode_reg_read(chn, 18); + mr19 = dramc_mode_reg_read(chn, 19); + dqsosc_cnt[0] = (mr18 & 0xff) | ((mr19 & 0xff) << 8); + dqsosc_cnt[1] = (mr18 >> 8) | (mr19 & 0xff00); + dramc_dbg("DQSOscCnt B0=%#x, B1=%#x\n", dqsosc_cnt[0], dqsosc_cnt[1]); + + /* get the INC and DEC values */ + clock_rate = get_freq_group_clock(freq_group); + tck = 1000000 / clock_rate; + + dqs_cnt = (mr18 & 0xff) | ((mr19 & 0xff) << 8); + if (dqs_cnt != 0) { + dqsosc = mr23 * 16 * 1000000 / (2 * dqs_cnt * clock_rate); + thrd_inc = mr23 * tck * tck / (dqsosc * dqsosc * 10); + thrd_dec = 3 * mr23 * tck * tck / (dqsosc * dqsosc * 20); + } else { + dqsosc = 0; + thrd_inc = 0x6; + thrd_dec = 0x4; + } + osc_thrd_inc[rank] = thrd_inc; + osc_thrd_dec[rank] = thrd_dec; + dramc_dbg("CH%d_RK%d: MR18=%#x, MR19=%#x, DQSOSC=%d, MR23=%d, " + "INC=%d, DEC=%d\n", + chn, rank, mr18, mr19, dqsosc, mr23, thrd_inc, thrd_dec); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsosc, + SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, dqsosc_cnt[0], + SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, dqsosc_cnt[1]); +} + +void dramc_hw_dqsosc(u8 chn) +{ + u32 freq_shu1 = get_shu_freq(DRAM_DFS_SHUFFLE_1); + u32 freq_shu2 = get_shu_freq(DRAM_DFS_SHUFFLE_2); + u32 freq_shu3 = get_shu_freq(DRAM_DFS_SHUFFLE_3); + + SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, + RK2_DQSOSC_FREQ_RATIO_TX_0, freq_shu2 * 8 / freq_shu1, + RK2_DQSOSC_FREQ_RATIO_TX_1, freq_shu3 * 8 / freq_shu1); + SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc, + RK2_DQSOSC_FREQ_RATIO_TX_3, freq_shu1 * 8 / freq_shu2, + RK2_DQSOSC_FREQ_RATIO_TX_4, freq_shu3 * 8 / freq_shu2); + SET32_BITFIELDS(&ch[chn].ao.rk[2].dummy_rd_bk, + RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, + freq_shu1 * 8 / freq_shu3, + RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, + freq_shu2 * 8 / freq_shu3); + + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], + PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 1, + PRE_TDQSCK1_SHU_PRELOAD_TX_START, 0, + PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 0); + + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPC_BLOCKALE_OPT, 0); + SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 1); + + SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, RK0_DQSOSC_DQSOSCR_RK0EN, 1); + SET32_BITFIELDS(&ch[chn].ao.rk[1].dqsosc, RK1_DQSOSC_DQSOSCR_RK1EN, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv, + SHU_SCINTV_DQSOSCENDIS, 1); +} + +static void dqsosc_shu_settings(u8 chn, u8 freq_group, + u16 *osc_thrd_inc, u16 *osc_thrd_dec) +{ + u8 filt_pithrd, w2r_sel, upd_sel; + u8 mr23 = MR23_DEFAULT_VALUE; + u16 prd_cnt, thrd_inc, thrd_dec; + + SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv, + SHU_SCINTV_DQS2DQ_SHU_PITHRD, 0); + SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, + RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 0); + + switch (freq_group) { + case LP4X_DDR1600: + filt_pithrd = 0x5; + w2r_sel = 0x5; + upd_sel = 0x0; + break; + case LP4X_DDR2400: + filt_pithrd = 0x8; + w2r_sel = 0x2; + upd_sel = 0x0; + break; + case LP4X_DDR3200: + filt_pithrd = 0xA; + w2r_sel = 0x2; + upd_sel = 0x0; + break; + case LP4X_DDR3600: + filt_pithrd = 0xB; + w2r_sel = 0x2; + upd_sel = 0x0; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv, + SHU_SCINTV_DQS2DQ_FILT_PITHRD, filt_pithrd); + SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, + SHU1_WODT_TXUPD_W2R_SEL, w2r_sel, + SHU1_WODT_TXUPD_SEL, upd_sel); + + prd_cnt = mr23 / 4 + 3; + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd, + SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, prd_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr, + SHU_DQSOSCR_DQSOSCRCNT, 0x40); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + thrd_inc = osc_thrd_inc[rk]; + thrd_dec = osc_thrd_dec[rk]; + + if (rk == RANK_0) { + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd, + SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, + thrd_inc); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd, + SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, + thrd_dec); + } else { + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd, + SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, + thrd_inc & 0xFF); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd, + SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, + (thrd_inc & 0xF00) >> 8); + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd, + SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, + thrd_dec); + } + } + + SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr2, + SHU_DQSOSCR2_DQSOSCENCNT, 0x1FF); +} + +void dramc_dqs_precalculation_preset(void) +{ + u32 jump_ratio_index = 0; + u16 jump_ratio[DRAM_DFS_SHUFFLE_MAX * HW_REG_SHUFFLE_MAX] = {0}; + u32 u4value = 0, u4value1 = 0; + + for (u8 shu_src = 0; shu_src < HW_REG_SHUFFLE_MAX; shu_src++) + for (u8 shu_dst = 0; shu_dst < HW_REG_SHUFFLE_MAX; shu_dst++) { + if (shu_src == shu_dst) + continue; + if (shu_src >= DRAM_DFS_SHUFFLE_MAX || + shu_dst >= DRAM_DFS_SHUFFLE_MAX) { + jump_ratio_index++; + continue; + } + + jump_ratio[jump_ratio_index] = DIV_ROUND_CLOSEST( + (get_shu_freq(shu_dst) >> 1) * 32, + get_shu_freq(shu_src) >> 1); + dramc_dbg("Jump_RATIO [%d]: %x Freq %d -> %d DDR%d ->" + " DDR%d\n", + jump_ratio_index, + jump_ratio[jump_ratio_index], + shu_src + 1, shu_dst + 1, + get_shu_freq(shu_src), get_shu_freq(shu_dst)); + jump_ratio_index++; + } + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + struct dramc_ao_regs_shu *shu = &ch[chn].ao.shu[0]; + struct dramc_ao_regs_rk *rk = &ch[chn].ao.rk[0]; + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], + PRE_TDQSCK1_TDQSCK_PRECAL_HW, 1); + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[1], + PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0, jump_ratio[0], + PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1, jump_ratio[1], + PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2, jump_ratio[2], + PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3, jump_ratio[3]); + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[2], + PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4, jump_ratio[4], + PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5, jump_ratio[5], + PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6, jump_ratio[6], + PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7, jump_ratio[7]); + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[3], + PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8, jump_ratio[8], + PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9, jump_ratio[9], + PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10, jump_ratio[10], + PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11, jump_ratio[11]); + + for (u8 rnk = RANK_0; rnk < RANK_MAX; rnk++) { + /* Shuffle 0 */ + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0], + RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS0IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0], + RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0, + u4value); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[2], + RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0, + (u4value << 3) | u4value1); + /* Shuffle 1 */ + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0], + RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS0IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0], + RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0, u4value); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[2], + RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0, + (u4value << 3) | u4value1); + /* Shuffle 2 */ + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[1], + RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS0IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[1], + RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0, + u4value); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[2], + RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0, + (u4value << 3) | u4value1); + + /* Byte 1 */ + /* Shuffle 0 */ + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3], + RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS1IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3], + RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0, + u4value); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[5], + RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0, + (u4value << 3) | u4value1); + /* Shuffle 1 */ + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3], + RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS1IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3], + RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0, + u4value); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[5], + RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0, + (u4value << 3) | u4value1); + /* Shuffle 2 */ + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[4], + RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS1IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[4], + RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0, + u4value); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[5], + RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0, + (u4value << 3) | u4value1); + + /* Byte 2 */ + /* Shuffle 0 */ + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6], + RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS2IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6], + RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0, + u4value); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[8], + RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0, + (u4value << 3) | u4value1); + /* Shuffle 1 */ + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6], + RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS2IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6], + RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0, + u4value); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[8], + RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0, + (u4value << 3) | u4value1); + /* Shuffle 2 */ + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[7], + RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS2IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[7], + RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0, + u4value); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[8], + RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0, + (u4value << 3) | u4value1); + + /* Byte 3 */ + /* Shuffle 0 */ + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9], + RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS3IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9], + RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0, + u4value); + u4value = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[0].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[11], + RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0, + (u4value << 3) | u4value1); + /* Shuffle 1 */ + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9], + RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS3IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9], + RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0, + u4value); + u4value = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[1].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[11], + RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0, + (u4value << 3) | u4value1); + /* Shuffle 2 */ + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[10], + RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, + (u4value << 3) | u4value1); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].dqsien, + SHURK0_DQSIEN_R0DQS3IEN); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[10], + RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, + u4value); + u4value = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg0, + SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1); + u4value1 = READ32_BITFIELD( + &shu[2].rk[rnk].selph_dqsg1, + SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1); + SET32_BITFIELDS(&rk[rnk].pre_tdqsck[11], + RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0, + (u4value << 3) | u4value1); + } + + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], + PRE_TDQSCK1_TDQSCK_REG_DVFS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0], + PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 1); + } +} + int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr) { @@ -2122,6 +2711,8 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, bool test_passed; u8 rx_datlat[RANK_MAX] = {0}; + u16 osc_thrd_inc[RANK_MAX]; + u16 osc_thrd_dec[RANK_MAX]; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", @@ -2146,8 +2737,11 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_TEST_ENG, pams, fast_calib); dramc_auto_refresh_switch(chn, false); + + dqsosc_auto(chn, rk, freq_group, osc_thrd_inc, osc_thrd_dec); } + dqsosc_shu_settings(chn, freq_group, osc_thrd_inc, osc_thrd_dec); dramc_rx_dqs_gating_post_process(chn, freq_group); dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]); } diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index e7cbda15d9..f1a2e39563 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -34,7 +34,7 @@ static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = { [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600, }; -u32 frequency_table[LP4X_DDRFREQ_MAX] = { +static const u32 frequency_table[LP4X_DDRFREQ_MAX] = { [LP4X_DDR1600] = 1600, [LP4X_DDR2400] = 2400, [LP4X_DDR3200] = 3200, @@ -77,6 +77,13 @@ u32 dramc_get_broadcast(void) return read32(&mt8183_infracfg->dramc_wbr); } +u32 get_shu_freq(u8 shu) +{ + const u8 *freq_tbl = CONFIG(MT8183_DRAM_EMCP) ? + freq_shuffle_emcp : freq_shuffle; + return frequency_table[freq_tbl[shu]]; +} + static u64 get_ch_rank_size(u8 chn, u8 rank) { u32 shift_for_16bit = 1; diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 54f009e9f0..59eb6dd3d4 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -29,6 +29,7 @@ #endif #define DATLAT_TAP_NUMBER 32 +#define HW_REG_SHUFFLE_MAX 4 #define DRAMC_BROADCAST_ON 0x1f #define DRAMC_BROADCAST_OFF 0x0 @@ -38,6 +39,7 @@ #define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a #define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16 #define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a +#define MR23_DEFAULT_VALUE 0x3f enum dram_te_op { TE_OP_WRITE_READ_CHECK = 0, @@ -114,5 +116,8 @@ void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off); +u32 get_shu_freq(u8 shu); +void dramc_hw_dqsosc(u8 chn); +void dramc_dqs_precalculation_preset(void); #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index b3ee6af4c7..8c1f9efa4d 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -627,12 +627,18 @@ check_member(emi_mpu_regs, mpu_ctrl, 0x0000); check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24) +DEFINE_BIT(SPCMDRESP_DQSOSCEN_RESPONSE, 10) +DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1) DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0) +DEFINE_BITFIELD(MRR_STATUS_MRR_REG, 15, 0) DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22) DEFINE_BIT(DDRCONF0_RDATRST, 0) DEFINE_BIT(PERFCTL0_RWOFOEN, 4) +DEFINE_BIT(RKCFG_DQSOSC2RK, 11) +DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26) + DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3) DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0) @@ -655,16 +661,19 @@ DEFINE_BITFIELD(MRS_MRSBA, 23, 21) DEFINE_BITFIELD(MRS_MRSMA, 20, 8) DEFINE_BITFIELD(MRS_MRSOP, 7, 0) +DEFINE_BIT(SPCMD_DQSOSCENEN, 10) DEFINE_BIT(SPCMD_DQSGCNTRST, 9) DEFINE_BIT(SPCMD_DQSGCNTEN, 8) DEFINE_BIT(SPCMD_ZQLATEN, 6) DEFINE_BIT(SPCMD_RDDQCEN, 7) DEFINE_BIT(SPCMD_ZQCEN, 4) +DEFINE_BIT(SPCMD_MRREN, 1) DEFINE_BIT(SPCMD_MRWEN, 0) DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11) DEFINE_BIT(MPC_OPTION_MPCRKEN, 17) +DEFINE_BIT(MPC_OPTION_MPC_BLOCKALE_OPT, 0) DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1) @@ -727,7 +736,39 @@ DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24) DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20) DEFINE_BIT(SHU1_WODT_DBIWR, 29) +DEFINE_BIT(SHU_SCINTV_DQSOSCENDIS, 30) +DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_SHU_PITHRD, 23, 18) DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0) +DEFINE_BIT(RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 29) +DEFINE_BIT(RK0_DQSOSC_DQSOSCR_RK0EN, 30) +DEFINE_BIT(RK1_DQSOSC_DQSOSCR_RK1EN, 30) + +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_0, 4, 0) +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_1, 9, 5) +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_3, 19, 15) +DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_4, 24, 20) +DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, 7, 3) +DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, 12, 8) + +DEFINE_BIT(PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 16) +DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_START, 18) +DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 19) + +DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_FILT_PITHRD, 29, 24) +DEFINE_BITFIELD(SHU1_WODT_TXUPD_W2R_SEL, 16, 14) +DEFINE_BITFIELD(SHU1_WODT_TXUPD_SEL, 13, 12) +DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, 9, 0) +DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0) +DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7) +DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24) +DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31) + +DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, 11, 0) +DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, 23, 12) +DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, 31, 24) +DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, 19, 16) +DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, 31, 20) +DEFINE_BITFIELD(SHU_DQSOSCR2_DQSOSCENCNT, 8, 0) DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12) DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4) @@ -736,6 +777,8 @@ DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0) +DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, 15, 0) +DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16) DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16) DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16) @@ -769,6 +812,115 @@ DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0) +/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK1) */ +DEFINE_BIT(PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22) +DEFINE_BIT(PRE_TDQSCK1_TDQSCK_REG_DVFS, 25) +DEFINE_BIT(PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26) + +/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK2) */ +DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3, 7, 0) +DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2, 15, 8) +DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1, 23, 16) +DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0, 31, 24) + +/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK3) */ +DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7, 7, 0) +DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6, 15, 8) +DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5, 23, 16) +DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4, 31, 24) + +/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK4) */ +DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11, 7, 0) +DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10, 15, 8) +DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9, 23, 16) +DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8, 31, 24) + +/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0) */ +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1, 30, 28) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED, 26, 24) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1, 22, 20) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED, 18, 16) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED, 10, 8) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1) */ +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1, 30, 28) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED, 26, 24) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1, 22, 20) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED, 18, 16) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1, 14, 12) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED, 10, 8) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1, 6, 4) +DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED, 2, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0, 25, 19) +DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0, 18, 13) +DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN) */ +DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS3IEN, 30, 24) +DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS2IEN, 22, 16) +DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS1IEN, 14, 8) +DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS0IEN, 6, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK3) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0, 17, 12) +DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0, 11, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK2) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK4) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0, 25, 19) +DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0, 18, 13) +DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK6) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0, 17, 12) +DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0, 11, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK5) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK7) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0, 25, 19) +DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0, 18, 13) +DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK9) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0, 17, 12) +DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0, 11, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK8) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK10) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0, 25, 19) +DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0, 18, 13) +DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK12) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0, 17, 12) +DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0, 11, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0, 5, 0) + +/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK11) */ +DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, 12, 6) +DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, 5, 0) + struct dramc_channel_regs { union { struct dramc_ddrphy_ao_regs phy; From 04571d8dbeb06376564b03759a5e7c22e9ece86a Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Tue, 21 Jan 2020 10:40:01 +0800 Subject: [PATCH 0290/1463] soc/mediatek/mt8183: Improve the DRAMC runtime config flow Move channel loop at the top level to deduplicate the logic. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Iea623d1bd1f7d736e81f66f191a1bf8476d30404 Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38490 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 84 +++++----- .../mt8183/dramc_pi_calibration_api.c | 150 +++++++++--------- .../mt8183/include/soc/dramc_pi_api.h | 2 +- 3 files changed, 111 insertions(+), 125 deletions(-) diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index c7d6c748e7..dc3676a9e3 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -285,13 +285,13 @@ static void dramc_rx_input_delay_tracking(u8 chn) (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); - for (u8 b = 0; b < 2; b++) { + for (u8 b = 0; b < 2; b++) clrsetbits32(&ch[chn].phy.b[b].dq[9], - (0x7 << 28) | (0x7 << 24), - (0x1 << 28) | (0x0 << 24)); - setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); - } + (0x7 << 28) | (0x7 << 24), + (0x1 << 28) | (0x0 << 24)); clrbits32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); + for (u8 b = 0; b < 2; b++) + setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); setbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); setbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); @@ -321,16 +321,14 @@ static void dramc_hw_dqs_gating_tracking(u8 chn) clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 31); } -static void dramc_hw_gating_init(void) +static void dramc_hw_gating_init(u8 chn) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrbits32(&ch[chn].ao.stbcal, - (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); - setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); - setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); + clrbits32(&ch[chn].ao.stbcal, + (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); + setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); - dramc_hw_dqs_gating_tracking(chn); - } + dramc_hw_dqs_gating_tracking(chn); } static void dramc_impedance_tracking_enable(void) @@ -348,19 +346,16 @@ static void dramc_impedance_tracking_enable(void) setbits32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); } -static void dramc_phy_low_power_enable(void) +static void dramc_phy_low_power_enable(u8 chn) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - for (size_t b = 0; b < 2; b++) { - clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2], - 0x3fffff << 10); - write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800); - } - clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2], - 0x3fffff << 10, 0x2 << 10); + for (u8 b = 0; b < 2; b++) { + clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2], 0x3fffff << 10); + write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800); } - write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000); - write32(&ch[1].phy.ca_dll_fine_tune[3], 0x3a000); + clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2], + 0x3fffff << 10, 0x2 << 10); + write32(&ch[chn].phy.ca_dll_fine_tune[3], + (chn == CHANNEL_A) ? 0xba000 : 0x3a000); } static void dramc_dummy_read_for_tracking_enable(u8 chn) @@ -421,46 +416,41 @@ static void dramc_enable_dramc_dcm(void) void dramc_runtime_config(void) { - clrbits32(&ch[0].ao.refctrl0, 0x1 << 29); - clrbits32(&ch[1].ao.refctrl0, 0x1 << 29); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + clrbits32(&ch[chn].ao.refctrl0, 0x1 << 29); transfer_pll_to_spm_control(); setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { dramc_hw_dqsosc(chn); - /* RX_TRACKING: ON */ - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + /* RX_TRACKING: ON */ dramc_rx_input_delay_tracking(chn); - /* HW_GATING: ON */ - dramc_hw_gating_init(); - dramc_hw_gating_onoff(CHANNEL_A, true); - dramc_hw_gating_onoff(CHANNEL_B, true); + /* HW_GATING: ON */ + dramc_hw_gating_init(chn); + dramc_hw_gating_onoff(chn, true); - /* HW_GATING DBG: OFF */ - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + /* HW_GATING DBG: OFF */ clrbits32(&ch[chn].ao.stbcal2, - (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); + (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); - /* DUMMY_READ_FOR_TRACKING: ON */ - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + /* DUMMY_READ_FOR_TRACKING: ON */ dramc_dummy_read_for_tracking_enable(chn); - /* ZQCS_ENABLE_LP4: ON */ - clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits32(&ch[1].ao.spcmdctrl, 0x1 << 30); + /* ZQCS_ENABLE_LP4: ON */ + clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 30); - /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ - dramc_phy_low_power_enable(); - dramc_enable_phy_dcm(true); + /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ + dramc_phy_low_power_enable(chn); + dramc_enable_phy_dcm(chn, true); - /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits32(&ch[chn].ao.shu[shu].dqsg_retry, - (0x1 << 1) | (0x3 << 13)); + (0x1 << 1) | (0x3 << 13)); + } /* SPM_CONTROL_AFTERK: ON */ write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 4ccc7fcb22..b9634a8ca8 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -282,18 +282,16 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); } -static void dramc_read_dbi_onoff(bool on) +static void dramc_read_dbi_onoff(size_t chn, bool on) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - for (size_t b = 0; b < 2; b++) - SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[7], - SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, on); + for (size_t b = 0; b < 2; b++) + SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[7], + SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, on); } -static void dramc_write_dbi_onoff(bool onoff) +static void dramc_write_dbi_onoff(size_t chn, bool onoff) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_DBIWR, onoff); + SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_DBIWR, onoff); } static void dramc_phy_dcm_2_channel(u8 chn, bool en) @@ -313,64 +311,61 @@ static void dramc_phy_dcm_2_channel(u8 chn, bool en) ((en ? 0x7 : 0) << 16) | ((en ? 0x7 : 0) << 20)); } -void dramc_enable_phy_dcm(bool en) +void dramc_enable_phy_dcm(u8 chn, bool en) { - for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) { - clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); - clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); - clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); - for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { - struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - setbits32(&shu->b[0].dll[0], 0x1); - setbits32(&shu->b[1].dll[0], 0x1); - setbits32(&shu->ca_dll[0], 0x1); - } - - clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, - (0x1 << 0) | (0x1 << 1) | (0x1 << 2) | - (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), - ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) | - ((en ? 0x1 : 0) << 2) | ((en ? 0 : 0x1) << 5) | - ((en ? 0 : 0x1) << 26) | ((en ? 0x1 : 0) << 30) | - ((en ? 0x1 : 0) << 31)); - - /* DCM on: CHANNEL_EMI free run; DCM off: mem_dcm */ - write32(&ch[chn].phy.misc_cg_ctrl2, - 0x8060033e | (0x40 << (en ? 0x1 : 0))); - write32(&ch[chn].phy.misc_cg_ctrl2, - 0x8060033f | (0x40 << (en ? 0x1 : 0))); - write32(&ch[chn].phy.misc_cg_ctrl2, - 0x8060033e | (0x40 << (en ? 0x1 : 0))); - - clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, - (en ? 0 : 0x3) << 26); - for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { - u32 mask = 0x7 << 17; - u32 value = (en ? 0x7 : 0) << 17; - struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - - clrsetbits32(&shu->b[0].dq[7], mask, value); - clrsetbits32(&shu->b[1].dq[7], mask, value); - clrsetbits32(&shu->ca_cmd[7], mask, value); - } - - dramc_phy_dcm_2_channel(chn, en); + for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; + setbits32(&shu->b[0].dll[0], 0x1); + setbits32(&shu->b[1].dll[0], 0x1); + setbits32(&shu->ca_dll[0], 0x1); } + + clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, + (0x1 << 0) | (0x1 << 1) | (0x1 << 2) | + (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), + ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) | + ((en ? 0x1 : 0) << 2) | ((en ? 0 : 0x1) << 5) | + ((en ? 0 : 0x1) << 26) | ((en ? 0x1 : 0) << 30) | + ((en ? 0x1 : 0) << 31)); + + /* DCM on: CHANNEL_EMI free run; DCM off: mem_dcm */ + write32(&ch[chn].phy.misc_cg_ctrl2, + 0x8060033e | (0x40 << (en ? 0x1 : 0))); + write32(&ch[chn].phy.misc_cg_ctrl2, + 0x8060033f | (0x40 << (en ? 0x1 : 0))); + write32(&ch[chn].phy.misc_cg_ctrl2, + 0x8060033e | (0x40 << (en ? 0x1 : 0))); + + clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, + (en ? 0 : 0x3) << 26); + for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { + u32 mask = 0x7 << 17; + u32 value = (en ? 0x7 : 0) << 17; + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; + + clrsetbits32(&shu->b[0].dq[7], mask, value); + clrsetbits32(&shu->b[1].dq[7], mask, value); + clrsetbits32(&shu->ca_cmd[7], mask, value); + } + + dramc_phy_dcm_2_channel(chn, en); } -static void dramc_reset_delay_chain_before_calibration(void) +static void dramc_reset_delay_chain_before_calibration(size_t chn) { - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - for (size_t rank = 0; rank < RANK_MAX; rank++) { - struct dramc_ddrphy_regs_shu_rk *rk; - rk = &ch[chn].phy.shu[0].rk[rank]; - clrbits32(&rk->ca_cmd[0], 0xffffff << 0); - clrbits32(&rk->b[0].dq[0], 0xfffffff << 0); - clrbits32(&rk->b[1].dq[0], 0xfffffff << 0); - clrbits32(&rk->b[0].dq[1], 0xf << 0); - clrbits32(&rk->b[1].dq[1], 0xf << 0); - } + for (size_t rank = 0; rank < RANK_MAX; rank++) { + struct dramc_ddrphy_regs_shu_rk *rk = + &ch[chn].phy.shu[0].rk[rank]; + clrbits32(&rk->ca_cmd[0], 0xffffff << 0); + clrbits32(&rk->b[0].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[1].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[0].dq[1], 0xf << 0); + clrbits32(&rk->b[1].dq[1], 0xf << 0); + } } void dramc_hw_gating_onoff(u8 chn, bool on) @@ -394,29 +389,31 @@ static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) void dramc_apply_config_before_calibration(u8 freq_group) { - dramc_enable_phy_dcm(false); - dramc_reset_delay_chain_before_calibration(); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_enable_phy_dcm(chn, false); + dramc_reset_delay_chain_before_calibration(chn); - setbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16); - setbits32(&ch[0].ao.spcmdctrl, 0x1 << 24); - clrsetbits32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); + setbits32(&ch[chn].ao.shu[0].conf[3], 0x1ff << 16); + setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 24); + clrsetbits32(&ch[chn].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); - for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); + for (u8 shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; + shu++) + setbits32(&ch[chn].ao.shu[shu].conf[3], 0x1ff << 0); - clrbits32(&ch[0].ao.dramctrl, 0x1 << 18); - clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 31); - clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits32(&ch[0].ao.dqsoscr, 0x1 << 26); - clrbits32(&ch[0].ao.dqsoscr, 0x1 << 25); + clrbits32(&ch[chn].ao.dramctrl, 0x1 << 18); + clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 31); + clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 26); + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 25); - dramc_write_dbi_onoff(false); - dramc_read_dbi_onoff(false); + dramc_write_dbi_onoff(chn, false); + dramc_read_dbi_onoff(chn, false); - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 29); setbits32(&ch[chn].ao.dqsoscr, 0x1 << 24); - for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + for (u8 shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; + shu++) setbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); clrbits32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); @@ -787,7 +784,6 @@ static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMSTBENCMP_RK, rank); - } static void set_selph_gating_value(uint32_t *addr, u8 dly, u8 dly_p1) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 59eb6dd3d4..c13aa013ee 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -113,7 +113,7 @@ void dramc_apply_config_after_calibration(const struct mr_value *mr); int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr); void dramc_hw_gating_onoff(u8 chn, bool onoff); -void dramc_enable_phy_dcm(bool bEn); +void dramc_enable_phy_dcm(u8 chn, bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off); u32 get_shu_freq(u8 shu); From b2ecc572de7b9c1c0a44f59bc5af22e0bccfc9bb Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 24 Jan 2020 10:43:48 -0800 Subject: [PATCH 0291/1463] mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGL Add support for Max98373 speaker amp & ALC5682 headset codec BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik Change-Id: I013dbc6246b07a501f9bff80c2bca3594e6cc146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38561 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- .../tglrvp/variants/tglrvp_up3/devicetree.cb | 45 ++++++++++++++++++- .../intel/tglrvp/variants/tglrvp_up3/gpio.c | 30 ++++++++++++- 2 files changed, 73 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4b5a39bfd..e61690ea41 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -91,6 +91,20 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoPci, }" + #HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y @@ -122,7 +136,36 @@ chip soc/intel/tigerlake device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 - device pci 15.0 on end # I2C0 0xA0E8 + device pci 15.0 on # I2C0 0xA0E8 + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)" + register "probed" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 device pci 15.1 on end # I2C1 0xA0E9 device pci 15.2 on end # I2C2 0xA0EA device pci 15.3 on end # I2C3 0xA0EB diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 8638b806b6..46ed5a20a9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -50,11 +50,39 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + + /*Audio */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* ToDo: Fill early gpio configurations for TPM and WWAN */ + + /*Audio */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */ + + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */ + + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */ + + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + }; const struct pad_config *variant_gpio_table(size_t *num) From 0c526386f445de72c7790ea9aef041c90ee14ff9 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Thu, 6 Feb 2020 20:31:07 +0100 Subject: [PATCH 0292/1463] mb/lenovo: Remove thermal.h header We include it only in one file. So let's simplify everything and do like autoport does. Change-Id: I71f092ed7582b4931122d72f41d0b42a7569b96e Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38781 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/mainboard/lenovo/l520/acpi_tables.c | 9 ++-- src/mainboard/lenovo/l520/thermal.h | 30 ------------- src/mainboard/lenovo/s230u/acpi_tables.c | 9 ++-- src/mainboard/lenovo/s230u/thermal.h | 30 ------------- src/mainboard/lenovo/t400/acpi_tables.c | 7 +-- src/mainboard/lenovo/t400/thermal.h | 30 ------------- src/mainboard/lenovo/t410/acpi_tables.c | 11 ++--- src/mainboard/lenovo/t410/thermal.h | 26 ----------- src/mainboard/lenovo/t420/acpi_tables.c | 9 ++-- src/mainboard/lenovo/t420/thermal.h | 30 ------------- src/mainboard/lenovo/t420s/acpi_tables.c | 9 ++-- src/mainboard/lenovo/t420s/thermal.h | 30 ------------- src/mainboard/lenovo/t430/acpi_tables.c | 17 ++++--- src/mainboard/lenovo/t430/thermal.h | 44 ------------------- src/mainboard/lenovo/t430s/acpi_tables.c | 9 ++-- src/mainboard/lenovo/t430s/thermal.h | 30 ------------- src/mainboard/lenovo/t440p/acpi_tables.c | 4 +- src/mainboard/lenovo/t520/acpi_tables.c | 9 ++-- src/mainboard/lenovo/t520/thermal.h | 30 ------------- src/mainboard/lenovo/t530/acpi_tables.c | 9 ++-- src/mainboard/lenovo/t530/thermal.h | 30 ------------- src/mainboard/lenovo/t60/acpi_tables.c | 7 +-- src/mainboard/lenovo/t60/thermal.h | 30 ------------- src/mainboard/lenovo/x131e/acpi_tables.c | 9 ++-- src/mainboard/lenovo/x131e/thermal.h | 30 ------------- .../lenovo/x1_carbon_gen1/acpi_tables.c | 9 ++-- src/mainboard/lenovo/x1_carbon_gen1/thermal.h | 30 ------------- src/mainboard/lenovo/x200/acpi_tables.c | 7 +-- src/mainboard/lenovo/x200/thermal.h | 30 ------------- src/mainboard/lenovo/x201/acpi_tables.c | 9 ++-- src/mainboard/lenovo/x201/thermal.h | 30 ------------- src/mainboard/lenovo/x220/acpi_tables.c | 9 ++-- src/mainboard/lenovo/x220/thermal.h | 30 ------------- src/mainboard/lenovo/x230/acpi_tables.c | 9 ++-- src/mainboard/lenovo/x230/thermal.h | 30 ------------- src/mainboard/lenovo/x60/acpi_tables.c | 7 +-- src/mainboard/lenovo/x60/thermal.h | 30 ------------- 37 files changed, 95 insertions(+), 623 deletions(-) delete mode 100644 src/mainboard/lenovo/l520/thermal.h delete mode 100644 src/mainboard/lenovo/s230u/thermal.h delete mode 100644 src/mainboard/lenovo/t400/thermal.h delete mode 100644 src/mainboard/lenovo/t410/thermal.h delete mode 100644 src/mainboard/lenovo/t420/thermal.h delete mode 100644 src/mainboard/lenovo/t420s/thermal.h delete mode 100644 src/mainboard/lenovo/t430/thermal.h delete mode 100644 src/mainboard/lenovo/t430s/thermal.h delete mode 100644 src/mainboard/lenovo/t520/thermal.h delete mode 100644 src/mainboard/lenovo/t530/thermal.h delete mode 100644 src/mainboard/lenovo/t60/thermal.h delete mode 100644 src/mainboard/lenovo/x131e/thermal.h delete mode 100644 src/mainboard/lenovo/x1_carbon_gen1/thermal.h delete mode 100644 src/mainboard/lenovo/x200/thermal.h delete mode 100644 src/mainboard/lenovo/x201/thermal.h delete mode 100644 src/mainboard/lenovo/x220/thermal.h delete mode 100644 src/mainboard/lenovo/x230/thermal.h delete mode 100644 src/mainboard/lenovo/x60/thermal.h diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index d6452afe38..7acbe2c47b 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -17,13 +17,14 @@ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/l520/thermal.h b/src/mainboard/lenovo/l520/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/l520/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index e7ddf82ec6..acb77d43a0 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - /* The LID is open by default */ + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/s230u/thermal.h b/src/mainboard/lenovo/s230u/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/s230u/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 6fed293f78..0e43081a43 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -20,7 +20,6 @@ #include #include #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -31,8 +30,10 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/t400/thermal.h b/src/mainboard/lenovo/t400/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/t400/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c index 2a8d9350e9..3628b772cb 100644 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -16,13 +16,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - - /* the lid is open by default. */ + /* The lid is open by default */ gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t410/thermal.h b/src/mainboard/lenovo/t410/thermal.h deleted file mode 100644 index d8c94805b8..0000000000 --- a/src/mainboard/lenovo/t410/thermal.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Patrick Rudolph - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/t420/acpi_tables.c +++ b/src/mainboard/lenovo/t420/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t420/thermal.h b/src/mainboard/lenovo/t420/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/t420/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t420s/thermal.h b/src/mainboard/lenovo/t420s/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/t420s/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index ea7e52f0e8..82ddd9f269 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -14,17 +14,20 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF; - gnvs->f0on = CTDP_DOWN_THRESHOLD_ON; + /* Config TDP Down */ + gnvs->f0of = 80; + gnvs->f0on = 90; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; + /* Tj_max value for calculating PECI CPU temperature */ + gnvs->tmax = 105; } diff --git a/src/mainboard/lenovo/t430/thermal.h b/src/mainboard/lenovo/t430/thermal.h deleted file mode 100644 index edfe3bc7ce..0000000000 --- a/src/mainboard/lenovo/t430/thermal.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Config TDP Sensor ID */ -#define CTDP_SENSOR_ID 0 /* PECI */ - -/* Config TDP Nominal */ -#define CTDP_NOMINAL_THRESHOLD_OFF 0 -#define CTDP_NOMINAL_THRESHOLD_ON 0 - -/* Config TDP Down */ -#define CTDP_DOWN_THRESHOLD_OFF 80 -#define CTDP_DOWN_THRESHOLD_ON 90 - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t430s/thermal.h b/src/mainboard/lenovo/t430s/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/t430s/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c index ff6c05ae0b..5105053d8a 100644 --- a/src/mainboard/lenovo/t440p/acpi_tables.c +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -19,9 +19,11 @@ void acpi_create_gnvs(global_nvs_t *gnvs) { - /* the lid is open by default */ + /* The lid is open by default. */ gnvs->lids = 1; + /* Temperature at which OS will shutdown. */ gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU. */ gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t520/thermal.h b/src/mainboard/lenovo/t520/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/t520/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/t530/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 46bb0d97fe..a0d493f763 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -15,7 +15,6 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,6 +22,8 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t60/thermal.h b/src/mainboard/lenovo/t60/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/t60/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/x131e/acpi_tables.c +++ b/src/mainboard/lenovo/x131e/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x131e/thermal.h b/src/mainboard/lenovo/x131e/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/x131e/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 6fed293f78..0e43081a43 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -20,7 +20,6 @@ #include #include #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -31,8 +30,10 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x200/thermal.h b/src/mainboard/lenovo/x200/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/x200/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 5065648e60..3628b772cb 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -16,13 +16,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - /* the lid is open by default. */ + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/x201/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x220/thermal.h b/src/mainboard/lenovo/x220/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/x220/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index e2d9814ca0..acb77d43a0 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -14,13 +14,14 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { - // the lid is open by default. + /* The lid is open by default */ gnvs->lids = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/x230/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 46bb0d97fe..a0d493f763 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -15,7 +15,6 @@ */ #include -#include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,6 +22,8 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/x60/thermal.h b/src/mainboard/lenovo/x60/thermal.h deleted file mode 100644 index 72953fd2c2..0000000000 --- a/src/mainboard/lenovo/x60/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ From 8e6fde0157b15b49131224a457a948f5a246f4d2 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Mon, 20 Jan 2020 15:13:09 +0100 Subject: [PATCH 0293/1463] mb/lenovo/x230: List Lenovo X230t convertible/tablet as variant Lenovo ThinkPad X230t Convertible Laptop works well with X230 default image (see CB:34361). Change-Id: Ib0a73fd551f0d26c789d3fd13541b2d1571742cb Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38482 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x230/Kconfig | 7 ++++--- src/mainboard/lenovo/x230/Kconfig.name | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index bf70950532..73dfdf6a10 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X230 +if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T config BOARD_SPECIFIC_OPTIONS def_bool y @@ -52,7 +52,8 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "ThinkPad X230" + default "ThinkPad X230" if BOARD_LENOVO_X230 + default "ThinkPad X230t" if BOARD_LENOVO_X230T config MAX_CPUS int @@ -74,4 +75,4 @@ config VGA_BIOS_ID string default "8086,0166" -endif # BOARD_LENOVO_X230 +endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name index d20765388b..10fdc2ed11 100644 --- a/src/mainboard/lenovo/x230/Kconfig.name +++ b/src/mainboard/lenovo/x230/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_X230 bool "ThinkPad X230" + +config BOARD_LENOVO_X230T + bool "ThinkPad X230t" From 04b02069e26484caf2737a863404daf4a438714b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 3 Mar 2020 18:33:00 +0100 Subject: [PATCH 0294/1463] soc/intel/common/block/tco: clear TCO1_STS register, too MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The register TCO1_STS is never cleared, which will cause SMIs to either retrigger over and over again (e.g. TIMEOUT) or prevent concurrent interrupt events, depending on which event triggered. Clear both TCO2_STS and TCO1_STS. This also fixes the issue where SECOND_TO_STS will always end up set in the SMI handler by unconditionally (re)setting it. Tested on X11SSM-F, where enabling TCO caused the terminal to get flooded with SMI debug messages. With this patch, a message gets written every ~1 second. Signed-off-by: Michael Niewöhner Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39259 Reviewed-by: Patrick Rudolph Reviewed-by: Andrey Petrov Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/smbus/tco.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb69d..bd8790aa6e 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -74,13 +74,13 @@ uint32_t tco_reset_status(void) uint16_t tco1_sts; uint16_t tco2_sts; - /* TCO Status 2 register */ - tco2_sts = tco_read_reg(TCO2_STS); - tco2_sts |= TCO_STS_SECOND_TO; - tco_write_reg(TCO2_STS, tco2_sts); - /* TCO Status 1 register */ tco1_sts = tco_read_reg(TCO1_STS); + tco_write_reg(TCO1_STS, tco1_sts); + + /* TCO Status 2 register */ + tco2_sts = tco_read_reg(TCO2_STS); + tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); return (tco2_sts << 16) | tco1_sts; } From e0060a80f0b662f9e4693785baaac16acb96632b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 5 Mar 2020 08:06:27 -0800 Subject: [PATCH 0295/1463] ec/google/chromeec: Fix dev ops for chromeec CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber --- src/ec/google/chromeec/Makefile.inc | 2 +- src/ec/google/chromeec/ec.c | 25 ------------------- src/ec/google/chromeec/ec.h | 5 ---- .../google/chromeec/{ec_chip.c => ec_acpi.c} | 0 src/ec/google/chromeec/ec_lpc.c | 13 ++++++++-- 5 files changed, 12 insertions(+), 33 deletions(-) rename src/ec/google/chromeec/{ec_chip.c => ec_acpi.c} (100%) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 2833c87d33..590b131355 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -28,7 +28,7 @@ verstage-y += ec.c crosec_proto.c vstore.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c ramstage-$(CONFIG_VBOOT) += vboot_storage.c smm-$(CONFIG_VBOOT) += vboot_storage.c diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 81e68d0f96..3faa29778b 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1525,28 +1525,3 @@ int google_chromeec_wait_for_displayport(long timeout) return 1; } - -#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY -static struct device_operations ec_chromeec_ops = { - .acpi_name = google_chromeec_acpi_name, - .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, -}; -#endif - -/* ec_lpc, ec_spi, or ec_i2c can override this */ -__weak void google_ec_enable_extra(struct device *dev) -{ -} - -static void google_chromeec_enable(struct device *dev) -{ -#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY - dev->ops = &ec_chromeec_ops; -#endif - google_ec_enable_extra(dev); -} - -struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") - .enable_dev = google_chromeec_enable -}; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f13b5105c2..699d7c2793 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -350,9 +350,4 @@ const char *google_chromeec_acpi_name(const struct device *dev); #endif /* HAVE_ACPI_TABLES */ -/* - * Allows bus-specific EC code to perform actions when the device is enabled. - */ -void google_ec_enable_extra(struct device *dev); - #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ diff --git a/src/ec/google/chromeec/ec_chip.c b/src/ec/google/chromeec/ec_acpi.c similarity index 100% rename from src/ec/google/chromeec/ec_chip.c rename to src/ec/google/chromeec/ec_acpi.c diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9afb1fd653..ab0e3cd38a 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -451,18 +451,27 @@ static struct device_operations ops = { .init = lpc_ec_init, .read_resources = lpc_ec_read_resources, .enable_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP + .set_resources = DEVICE_NOOP, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = google_chromeec_acpi_name, + .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, +#endif }; static struct pnp_info pnp_dev_info[] = { { NULL, 0, 0, 0, } }; -void google_ec_enable_extra(struct device *dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } +struct chip_operations ec_google_chromeec_ops = { + CHIP_NAME("Google Chrome EC") + .enable_dev = enable_dev, +}; + static int google_chromeec_data_ready(u16 port) { return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, From e425a09d6a0016e128373941ee1cf223a528a0fc Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 4 Mar 2020 09:38:06 -0800 Subject: [PATCH 0296/1463] vendorcode/intel/fsp/fsp2_0/skylake_sp: update header files Added definitions in FspmUpd.h. Added gpio_fsp.h file which has definitions needed by mainboard gpio header file, to set gpio configuration through FSP-M UPD. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Tested-by: johnny_lin@wiwynn.com Change-Id: I72727952685b5e453f4cde6c2e7e7fc7114c6884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39287 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- .../intel/fsp/fsp2_0/skylake_sp/FspmUpd.h | 45 ++++ .../intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h | 205 ++++++++++++++++++ 2 files changed, 250 insertions(+) create mode 100644 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index 80ca157bb4..0de0fa1ee8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -45,6 +45,51 @@ are permitted provided that the following conditions are met: #define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */ #define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */ +#define HIDE 1 +#define NOT_HIDE 0 + +#define IIO_BIFURCATE_AUTO 0xFF + +/* Ports 1D-1A, 2D-2A, 3D-3A */ +#define IIO_BIFURCATE_x4x4x4x4 0 +#define IIO_BIFURCATE_x4x4xxx8 1 +#define IIO_BIFURCATE_xxx8x4x4 2 +#define IIO_BIFURCATE_xxx8xxx8 3 +#define IIO_BIFURCATE_xxxxxx16 4 +#define IIO_BIFURCATE_xxxxxxxx 0xF + + +typedef enum { + IioPortA = 0, + IioPortB = 1, + IioPortC = 2, + IioPortD = 3 +} IIO_PORTS; + +/** + * Enums and Macro definitions needed for reference RVP and CRB + * table declarations +**/ +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 = 0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + /** IIO PCIe Ports **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h new file mode 100644 index 0000000000..be9d33f860 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/gpio_fsp.h @@ -0,0 +1,205 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _GPIO_FSP_H_ +#define _GPIO_FSP_H_ + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 +#define GPIO_CONF_HOST_OWN_MASK 0x3 +#define GPIO_CONF_HOST_OWN_BIT_POS 0 +#define GPIO_CONF_DIR_MASK 0x7 +#define GPIO_CONF_DIR_BIT_POS 0 +#define GPIO_CONF_INV_MASK 0x18 +#define GPIO_CONF_INV_BIT_POS 3 +#define GPIO_CONF_OUTPUT_MASK 0x3 +#define GPIO_CONF_OUTPUT_BIT_POS 0 +#define GPIO_CONF_INT_ROUTE_MASK 0x1F +#define GPIO_CONF_INT_ROUTE_BIT_POS 0 +#define GPIO_CONF_INT_TRIG_MASK 0xE0 +#define GPIO_CONF_INT_TRIG_BIT_POS 5 +#define GPIO_CONF_RESET_MASK 0x7 +#define GPIO_CONF_RESET_BIT_POS 0 +#define GPIO_CONF_TERM_MASK 0x1F +#define GPIO_CONF_TERM_BIT_POS 0 +#define GPIO_CONF_PADTOL_MASK 0x60 +#define GPIO_CONF_PADTOL_BIT_POS 5 +#define GPIO_CONF_LOCK_MASK 0x7 +#define GPIO_CONF_LOCK_BIT_POS 0 +#define GPIO_CONF_RXRAW_MASK 0x3 +#define GPIO_CONF_RXRAW_BIT_POS 0 + +typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; + +/// +/// GPIO Pad Mode +/// +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/// +/// Host Software Pad Ownership modes +/// +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI + GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = + (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and + ///input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/// +/// GPIO Output State +/// +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/// +/// GPIO interrupt configuration +/// This setting is applicable only if GPIO is in input mode. +/// GPIO_INT_CONFIG allows to choose which interrupt is generated +/// (IOxAPIC/SCI/SMI/NMI) +/// and how it is triggered (edge or level). +/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to +/// GpioIntBothEdgecan +/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel +/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. +/// Not all GPIO are capable of generating an SMI or NMI interrupt +/// + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of + ///edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +/// +/// GPIO Power Configuration +/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified +/// Pad Register fields). +/// +typedef enum { + GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified + GpioResetPwrGood = 0x1, ///< Powergood reset + GpioResetDeep = 0x3, ///< Deep GPIO Reset + GpioResetNormal = 0x5, ///< GPIO Reset + GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) +} GPIO_RESET_CONFIG; + +/// +/// GPIO Electrical Configuration +/// Set GPIO termination and Pad Tolerance (applicable only for some pads) +/// Field from GpioTermDefault to GpioTermNative can be OR'ed with +/// GpioTolerance1v8. +/// +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + GpioTermNative = 0x1F, ///< Native function controls pads termination + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +/// +/// GPIO LockConfiguration +/// Set GPIO configuration lock and output state lock +/// GpioLockPadConfig and GpioLockOutputState can be OR'ed +/// +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +/// +/// Other GPIO Configuration +/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions +/// Supported settings: +/// - RX raw override to '1' - allows to override input value to '1' +/// This setting is applicable only if in input mode (both in GPIO and +/// native usage). +/// The override takes place at the internal pad state directly from buffer +/// and before the RXINV. +/// +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost = 0x0, + GpioPadOwnCsme = 0x1, + GpioPadOwnIsh = 0x2, +} GPIO_PAD_OWN; + +#endif From 8f89549d3c7d41643337662947cfdb2329bd030b Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 16 Jan 2020 11:16:45 -0800 Subject: [PATCH 0297/1463] soc/intel: Add Intel Xeon Scalable Processor support This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/drivers/intel/fsp2_0/Kconfig | 2 +- src/soc/intel/Kconfig | 1 + src/soc/intel/xeon_sp/Kconfig | 134 +++ src/soc/intel/xeon_sp/Makefile.inc | 59 + src/soc/intel/xeon_sp/acpi.c | 1017 +++++++++++++++++ src/soc/intel/xeon_sp/acpi/globalnvs.asl | 82 ++ src/soc/intel/xeon_sp/acpi/iiostack.asl | 92 ++ src/soc/intel/xeon_sp/acpi/pci_irq.asl | 113 ++ src/soc/intel/xeon_sp/acpi/uncore.asl | 48 + src/soc/intel/xeon_sp/acpi/uncore_irq.asl | 566 +++++++++ src/soc/intel/xeon_sp/bootblock/bootblock.c | 61 + src/soc/intel/xeon_sp/chip.c | 603 ++++++++++ src/soc/intel/xeon_sp/chip.h | 87 ++ src/soc/intel/xeon_sp/cpu.c | 260 +++++ src/soc/intel/xeon_sp/hob_display.c | 235 ++++ src/soc/intel/xeon_sp/include/soc/acpi.h | 37 + src/soc/intel/xeon_sp/include/soc/cpu.h | 33 + .../intel/xeon_sp/include/soc/gpio_soc_defs.h | 299 +++++ src/soc/intel/xeon_sp/include/soc/iomap.h | 47 + src/soc/intel/xeon_sp/include/soc/irq.h | 23 + src/soc/intel/xeon_sp/include/soc/msr.h | 113 ++ src/soc/intel/xeon_sp/include/soc/nvs.h | 33 + src/soc/intel/xeon_sp/include/soc/pci_devs.h | 186 +++ src/soc/intel/xeon_sp/include/soc/pcr_ids.h | 23 + src/soc/intel/xeon_sp/include/soc/pm.h | 32 + src/soc/intel/xeon_sp/include/soc/pmc.h | 34 + src/soc/intel/xeon_sp/include/soc/ramstage.h | 30 + src/soc/intel/xeon_sp/include/soc/romstage.h | 26 + src/soc/intel/xeon_sp/include/soc/soc_util.h | 80 ++ src/soc/intel/xeon_sp/lpc.c | 45 + src/soc/intel/xeon_sp/reset.c | 24 + src/soc/intel/xeon_sp/romstage.c | 83 ++ src/soc/intel/xeon_sp/soc_util.c | 577 ++++++++++ src/soc/intel/xeon_sp/spi.c | 28 + src/soc/intel/xeon_sp/uncore.c | 305 +++++ src/soc/intel/xeon_sp/upd_display.c | 80 ++ 36 files changed, 5497 insertions(+), 1 deletion(-) create mode 100644 src/soc/intel/xeon_sp/Kconfig create mode 100644 src/soc/intel/xeon_sp/Makefile.inc create mode 100644 src/soc/intel/xeon_sp/acpi.c create mode 100644 src/soc/intel/xeon_sp/acpi/globalnvs.asl create mode 100644 src/soc/intel/xeon_sp/acpi/iiostack.asl create mode 100644 src/soc/intel/xeon_sp/acpi/pci_irq.asl create mode 100644 src/soc/intel/xeon_sp/acpi/uncore.asl create mode 100644 src/soc/intel/xeon_sp/acpi/uncore_irq.asl create mode 100644 src/soc/intel/xeon_sp/bootblock/bootblock.c create mode 100644 src/soc/intel/xeon_sp/chip.c create mode 100644 src/soc/intel/xeon_sp/chip.h create mode 100644 src/soc/intel/xeon_sp/cpu.c create mode 100644 src/soc/intel/xeon_sp/hob_display.c create mode 100644 src/soc/intel/xeon_sp/include/soc/acpi.h create mode 100644 src/soc/intel/xeon_sp/include/soc/cpu.h create mode 100644 src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h create mode 100644 src/soc/intel/xeon_sp/include/soc/iomap.h create mode 100644 src/soc/intel/xeon_sp/include/soc/irq.h create mode 100644 src/soc/intel/xeon_sp/include/soc/msr.h create mode 100644 src/soc/intel/xeon_sp/include/soc/nvs.h create mode 100644 src/soc/intel/xeon_sp/include/soc/pci_devs.h create mode 100644 src/soc/intel/xeon_sp/include/soc/pcr_ids.h create mode 100644 src/soc/intel/xeon_sp/include/soc/pm.h create mode 100644 src/soc/intel/xeon_sp/include/soc/pmc.h create mode 100644 src/soc/intel/xeon_sp/include/soc/ramstage.h create mode 100644 src/soc/intel/xeon_sp/include/soc/romstage.h create mode 100644 src/soc/intel/xeon_sp/include/soc/soc_util.h create mode 100644 src/soc/intel/xeon_sp/lpc.c create mode 100644 src/soc/intel/xeon_sp/reset.c create mode 100644 src/soc/intel/xeon_sp/romstage.c create mode 100644 src/soc/intel/xeon_sp/soc_util.c create mode 100644 src/soc/intel/xeon_sp/spi.c create mode 100644 src/soc/intel/xeon_sp/uncore.c create mode 100644 src/soc/intel/xeon_sp/upd_display.c diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 2624644fae..024a478eb6 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -56,7 +56,7 @@ config FSP_USE_REPO depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \ - SOC_INTEL_DENVERTON_NS + SOC_INTEL_DENVERTON_NS || SOC_INTEL_XEON_SP help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index e8935b9fd5..47efc4d18f 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -9,6 +9,7 @@ source "src/soc/intel/quark/Kconfig" source "src/soc/intel/skylake/Kconfig" source "src/soc/intel/icelake/Kconfig" source "src/soc/intel/tigerlake/Kconfig" +source "src/soc/intel/xeon_sp/Kconfig" # Load common config source "src/soc/intel/common/Kconfig" diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig new file mode 100644 index 0000000000..8c355c4582 --- /dev/null +++ b/src/soc/intel/xeon_sp/Kconfig @@ -0,0 +1,134 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_INTEL_XEON_SP + bool + help + Intel Xeon SP support + +if SOC_INTEL_XEON_SP + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + select POSTCAR_CONSOLE + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET + select PLATFORM_USES_FSP2_0 + select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS + select FSP_T_XIP + select FSP_M_XIP + select FSP_USE_REPO + select POSTCAR_STAGE + select IOAPIC + select PARALLEL_MP + select SMP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select COMMON_FADT + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_BLOCK_LPC + select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SPI + select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_PCR + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + +config MAINBOARD_USES_FSP2_0 + bool + default y + +config USE_FSP2_0_DRIVER + def_bool y + depends on MAINBOARD_USES_FSP2_0 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_CONSOLE + select POSTCAR_STAGE + +# Fake FSP binary is used, as the current FSP binary for SKX-SP +# is an engineering build. It is not available to the public +# for now. +config FSP_FD_PATH + string "Location of FSP binary" + depends on FSP_USE_REPO + default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" + +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" + +config MAX_SOCKET + int + default 2 + +# For 2S config, the number of cpus could be as high as +# 2 threads * 20 cores * 2 sockets +config MAX_CPUS + int + default 80 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config DCACHE_RAM_BASE + hex + default 0xfe800000 + +config DCACHE_RAM_SIZE + hex + default 0x200000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x10000 + +config MMCONF_BASE_ADDRESS + hex + default 0x80000000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config HEAP_SIZE + hex + default 0x80000 + + +endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc new file mode 100644 index 0000000000..9ad3e77b35 --- /dev/null +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm + +bootblock-y += bootblock/bootblock.c +bootblock-y += spi.c + +postcar-y += soc_util.c +postcar-y += spi.c + +romstage-y += soc_util.c +romstage-y += reset.c +romstage-y += romstage.c +romstage-y += soc_util.c +romstage-y += spi.c +romstage-y += hob_display.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c + +ramstage-y += soc_util.c +ramstage-y += uncore.c +ramstage-y += reset.c +ramstage-y += chip.c +ramstage-y += soc_util.c +ramstage-y += lpc.c +ramstage-y += cpu.c +ramstage-y += spi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-y += hob_display.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include +CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) + +endif ## CONFIG_SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c new file mode 100644 index 0000000000..37dd420cf7 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi.c @@ -0,0 +1,1017 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + int32_t scis; + + scis = soc_read_sci_irq_select(); + scis &= SCI_IRQ_SEL; + scis >>= SCI_IRQ_ADJUST; + + /* Determine how SCI is routed. */ + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +} + +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); + + /* Update the mem console pointer. */ + if (CONFIG(CONSOLE_CBMEM)) + gnvs->cbmc = (uint32_t)cbmem_find(CBMEM_ID_CONSOLE); +} + +uint32_t soc_read_sci_irq_select(void) +{ + struct device *dev = PCH_DEV_PMC; + + if (!dev) + return 0; + + return pci_read_config32(dev, PMC_ACPI_CNT); +} + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + *entries = 0; + return NULL; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); + return current; +} + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci = acpi_sci_irq(); + uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + flags |= soc_madt_sci_irq_polarity(sci); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + + current += + acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0xff, 0x0d, 1); + + return current; +} + +static unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) +{ + struct device *cpu; + int num_cpus = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, + num_cpus, cpu->path.apic.apic_id); + } + + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + size_t hob_size = 0; + const uint8_t fsp_hob_iio_universal_data_guid[16] = + FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + int cur_stack; + + int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; + int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; + + /* Local APICs */ + current = xeonsp_acpi_create_madt_lapics(current); + + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + cur_stack = 0; + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + const STACK_RES *ri = + &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + // TODO: do we have situation with only bus 0 and one stack? + if (ri->BusBase != ri->BusLimit) { + assert(cur_stack < ARRAY_SIZE(ioapic_ids)); + assert(cur_stack < ARRAY_SIZE(gsi_bases)); + int ioapic_id = ioapic_ids[cur_stack]; + int gsi_base = gsi_bases[cur_stack]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + socket, stack, ioapic_id, ri->IoApicBase, gsi_base); + current += acpi_create_madt_ioapic( + (acpi_madt_ioapic_t *)current, + ioapic_id, ri->IoApicBase, gsi_base); + ++cur_stack; + + if (socket == 0 && stack == 0) { + assert(cur_stack < ARRAY_SIZE(ioapic_ids)); + assert(cur_stack < ARRAY_SIZE(gsi_bases)); + ioapic_id = ioapic_ids[cur_stack]; + gsi_base = gsi_bases[cur_stack]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + socket, stack, ioapic_id, + ri->IoApicBase + 0x1000, gsi_base); + current += acpi_create_madt_ioapic( + (acpi_madt_ioapic_t *)current, + ioapic_id, ri->IoApicBase + 0x1000, gsi_base); + ++cur_stack; + } + } + } + } + + return acpi_madt_irq_overrides(current); +} + +__attribute__ ((weak)) void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ +} + +void generate_t_state_entries(int core, int cores_per_package) +{ +} + +void generate_p_state_entries(int core, int cores_per_package) +{ +} + +void generate_cpu_entries(struct device *device) +{ + int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; + int plen = 6; + int total_threads = dev_count_cpu(); + int threads_per_package = get_threads_per_package(); + int numcpus = total_threads / threads_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each, totalcores: %d.\n", + numcpus, threads_per_package, total_threads); + + for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { + for (core_id = 0; core_id < threads_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor((cpu_id) * threads_per_package + + core_id, pcontrol_blk, plen); + + /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ + + /* TODO: Soc specific power states generation */ + acpigen_pop_len(); + } + } + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, threads_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(threads_per_package); +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* System Management */ + if (!CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = 0x00; + fadt->acpi_enable = 0x00; + fadt->acpi_disable = 0x00; + } + + /* Power Control */ + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe1_blk = 0; + + /* Control Registers - Length */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->day_alrm = 0x0D; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + /* Reset Register */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xCF9; + fadt->reset_reg.addrh = 0x00; + fadt->reset_value = 6; + + /* PM1 Status & PM1 Enable */ + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x00; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x00; + + /* PM1 Control Registers */ + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x00; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x00; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x00; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x00; + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x00; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x00; + + motherboard_fill_fadt(fadt); +} + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* Use ACPI 3.0 revision */ + fadt->header.revision = get_acpi_table_revision(FADT); + + fadt->sci_int = acpi_sci_irq(); + /* + TODO: enabled SMM mode switch when SMM handlers are set up. + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + */ + fadt->smi_cmd = 0x00; + fadt->acpi_enable = 0x00; + fadt->acpi_disable = 0x00; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; + if (!CONFIG(NO_FADT_8042)) + fadt->iapc_boot_arch |= ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + soc_fill_fadt(fadt); +} + +static acpi_tstate_t xeon_sp_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = ARRAY_SIZE(xeon_sp_tss_table); + return xeon_sp_tss_table; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + if (sci >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +unsigned long southbridge_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + current = acpi_write_hpet(device, current, rsdp); + current = (ALIGN(current, 16)); + printk(BIOS_DEBUG, "current = %lx\n", current); + return current; +} + +unsigned long acpi_create_srat_lapics(unsigned long current) +{ + struct device *cpu; + int cpu_index = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + +static unsigned long acpi_fill_srat(unsigned long current) +{ + acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; + unsigned int mem_count; + + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); + + mem_count = get_srat_memory_entries(srat_mem); + for (int i = 0; i < mem_count; ++i) { + printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " + "length: 0x%x%x, proximity_domain: %d, flags: %x\n", + i, srat_mem[i].length, + srat_mem[i].base_address_high, srat_mem[i].base_address_low, + srat_mem[i].length_high, srat_mem[i].length_low, + srat_mem[i].proximity_domain, srat_mem[i].flags); + memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); + current += srat_mem[i].length; + } + + return current; +} + +static unsigned long acpi_fill_slit(unsigned long current) +{ + int nodes = get_cpu_count(); + + uint8_t *p = (uint8_t *)current; + memset(p, 0, 8 + nodes * nodes); + *p = (uint8_t)nodes; + p += 8; + + /* this assumes fully connected socket topology */ + for (int i = 0; i < nodes; i++) { + for (int j = 0; j < nodes; j++) { + if (i == j) + p[i*nodes+j] = 10; + else + p[i*nodes+j] = 16; + } + } + + current += 8+nodes*nodes; + return current; +} + +static int get_stack_for_port(int p) +{ + if (p == 0) + return CSTACK; + else if (p >= PORT_1A && p <= PORT_1D) + return PSTACK0; + else if (p >= PORT_2A && p <= PORT_2D) + return PSTACK1; + else if (p >= PORT_3A && p <= PORT_3D) + return PSTACK2; + else if (p >= PORT_4A && p <= PORT_4D) + return PSTACK3; // MCP0 + else + return PSTACK4; // MCP1 +} + +static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +{ + int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + uint32_t enum_id; + unsigned long tmp = current; + + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t reg_base = + hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", + __func__, socket, stack, bus, pcie_seg, reg_base); + + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + + // Add PCH IOAPIC + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, + PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + } + + // Add IOAPIC entry + enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); + + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } + } + + // Add PCIe Ports + if (socket != 0 || stack != CSTACK) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, + bus, dev, func); + } + + // Add VMD + if (hob->PlatformData.VMDStackEnable[socket][stack] && + stack >= PSTACK0 && stack <= PSTACK2) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, + bus, VMD_DEV_NUM, VMD_FUNC_NUM); + } + } + + // Add HPET + if (socket == 0 && stack == CSTACK) { + uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); + uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", + __func__, hpet_capid, num_hpets); + //BIT 15 + if (num_hpets && (num_hpets != 0x1f) && + (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); + current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, + HPET_DEV_NUM, HPET0_FUNC_NUM); + } + } + + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_atsr(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + unsigned long tmp = current; + bool first = true; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + "vtd_mmio_cap: 0x%llx\n", + __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); + + // ATSR is applicable only for platform supporting device IOTLBs + // through the VT-d extended capability register + assert(vtd_mmio_cap != 0xffffffffffffffff); + if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 + continue; + + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (socket == 0 && p == 0) + continue; + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + if (first) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", + 0, pcie_seg); + current += acpi_create_dmar_atsr(current, 0, pcie_seg); + first = 0; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); + } + } + if (tmp != current) + acpi_dmar_atsr_fixup(tmp, current); + } + + return current; +} + +static unsigned long acpi_create_rmrr(unsigned long current) +{ + uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); + + uint32_t *ptr; + + // reserve memory + ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); + if (!ptr) { + ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); + assert(ptr != NULL); + memset(ptr, 0, size); + } + + unsigned long tmp = current; + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " + "End Address (limit): 0x%x\n", + 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, + (uint32_t) ((uint32_t) ptr + size - 1)); + + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, + PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_rhsa(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + + printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " + "Proximity Domain: 0x%x\n", vtd_base, socket); + current += acpi_create_dmar_rhsa(current, vtd_base, socket); + } + } + + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // DRHD + for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { + int socket = iio; + if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry + socket = 0; + + if (socket == 0) { + for (int stack = 1; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, CSTACK); + } else { + for (int stack = 0; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + } + } + + // RMRR + current = acpi_create_rmrr(current); + + // ATSR - causes hang + current = acpi_create_atsr(current); + + // RHSA + current = acpi_create_rhsa(current); + + return current; +} + +unsigned long northbridge_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_dmar_t *dmar; + + const struct soc_intel_xeon_sp_config *const config = config_of(device); + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + + /* DMAR */ + if (config->vtd_support) { + current = ALIGN(current, 8); + dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", + (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); + acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + } + + return current; +} + +void uncore_inject_dsdt(void) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + acpigen_write_scope("\\_SB"); + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + const STACK_RES *ri = &iio_resource.StackRes[stack]; + char rtname[16]; + snprintf(rtname, sizeof(rtname), "RT%02x", + (socket*MAX_IIO_STACK)+stack); + + acpigen_write_name(rtname); + printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", + rtname, socket, stack); + + acpigen_write_resourcetemplate_header(); + + /* bus resource */ + acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, + 0x0, (ri->BusLimit - ri->BusBase + 1)); + + // additional io resources on socket 0 bus 0 + if (socket == 0 && stack == 0) { + /* ACPI 6.4.2.5 I/O Port Descriptor */ + acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); + + /* IO decode CF8-CFF */ + acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, + 0, 0x03B0); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, + 0, 0x0918); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, + 0, 0x000C); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, + 0, 0x0020); + } + + /* IO resource */ + acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, + ri->PciResourceIoLimit, 0x0, + (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); + + // additional mem32 resources on socket 0 bus 0 + if (socket == 0 && stack == 0) { + acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, + (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, + VGA_BASE_SIZE); + acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, + (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, + SPI_BASE_SIZE); + } + + /* Mem32 resource */ + acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, + ri->PciResourceMem32Limit, 0x0, + (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); + + /* Mem64 resource */ + acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, + ri->PciResourceMem64Limit, 0x0, + (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); + + acpigen_write_resourcetemplate_footer(); + } + } + acpigen_pop_len(); +} + +void southbridge_inject_dsdt(struct device *device) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ + // smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } + + // Add IIOStack ACPI Resource Templates + uncore_inject_dsdt(); +} diff --git a/src/soc/intel/xeon_sp/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/acpi/globalnvs.asl new file mode 100644 index 0000000000..c2d5853e06 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/globalnvs.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 + +/* + * Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + + +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + PCNT, 8, // 0x11 - Processor count + TPMP, 8, // 0x12 - TPM Present and Enabled + TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS + PM1I, 64, // 0x15 - PM1 wake status bit + GPEI, 64, // 0x1D - GPE wake status bit + U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap + U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap + + + /* Device Config */ + Offset (0x30), + S5U0, 8, // 0x30 - Enable USB0 in S5 + S5U1, 8, // 0x31 - Enable USB1 in S5 + S3U0, 8, // 0x32 - Enable USB0 in S3 + S3U1, 8, // 0x33 - Enable USB1 in S3 + TACT, 8, // 0x34 - Thermal Active trip point + TPSV, 8, // 0x35 - Thermal Passive trip point + TCRT, 8, // 0x36 - Thermal Critical trip point + DPTE, 8, // 0x37 - Enable DPTF + + /* Base addresses */ + Offset (0x50), + CMEM, 32, // 0x50 - CBMEM TOC + TOLM, 32, // 0x54 - Top of Low Memory + CBMC, 32, // 0x58 - coreboot mem console pointer + MMOB, 32, // 0x5C - MMIO Base Low Base + MMOL, 32, // 0x60 - MMIO Base Low Limit + MMHB, 64, // 0x64 - MMIO Base High Base + MMHL, 64, // 0x6C - MMIO Base High Limit + TSGB, 32, // 0x74 - TSEG Base + TSSZ, 32, // 0x78 - TSEG Size +} diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl new file mode 100644 index 0000000000..2d1187f4c3 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define MAKE_IIO_DEV(id,rt) \ + Device (PC##id) \ + { \ + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ + Name (_UID, 0x##id) \ + Method (_PRT, 0, NotSerialized) \ + { \ + If (PICM) \ + { \ + Return (\_SB_.AR##rt) \ + } \ + Return (\_SB_.PR##rt) \ + } \ + External(\_SB.RT##id) \ + Method (_CRS, 0, NotSerialized) \ + { \ + Return (\_SB.RT##id) \ + } \ + Name (SUPP, 0x00) \ + Name (CTRL, 0x00) \ + Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ + Method (_OSC, 4, NotSerialized) \ + { \ + CreateDWordField (Arg3, 0x00, CDW1) \ + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ + { \ + CreateDWordField (Arg3, 0x04, CDW2) \ + If ((Arg2 > 0x02)) \ + { \ + CreateDWordField (Arg3, 0x08, CDW3) \ + } \ + SUPP = CDW2 \ + CTRL = CDW3 \ + If ((AHPE || ((SUPP & 0x16) != 0x16))) \ + { \ + CTRL &= 0x1E \ + Sleep (0x03E8) \ + } \ + /* Never allow SHPC (no SHPC controller in system) */ \ + CTRL &= 0x1D \ + /* Disable Native PCIe AER handling from OS */ \ + CTRL &= 0x17 \ + If ((Arg1 != One)) /* unknown revision */ \ + { \ + CDW1 |= 0x08 \ + } \ + If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ + { \ + CDW1 |= 0x10 \ + } \ + CDW3 = CTRL \ + Return (Arg3) \ + } \ + Else \ + { \ + /* indicate unrecognized UUID */ \ + CDW1 |= 0x04 \ + IO80 = 0xEE \ + Return (Arg3) \ + } \ + } \ + } + +MAKE_IIO_DEV(00, 00) +MAKE_IIO_DEV(01, 10) +MAKE_IIO_DEV(02, 20) +MAKE_IIO_DEV(03, 28) + +#if MAX_SOCKET > 1 +MAKE_IIO_DEV(06, 40) +MAKE_IIO_DEV(07, 50) +MAKE_IIO_DEV(08, 60) +MAKE_IIO_DEV(09, 68) +#endif diff --git a/src/soc/intel/xeon_sp/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/acpi/pci_irq.asl new file mode 100644 index 0000000000..cfa4ad5c7b --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/pci_irq.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 + * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 + * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 + * + * PIRQ routing control is in PCR ITSS region. + */ + +OperationRegion (ITSS, SystemMemory, + Add (PCR_ITSS_PIRQA_ROUT, + Add (CONFIG_PCR_BASE_ADDRESS, + ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) +Field (ITSS, ByteAcc, NoLock, Preserve) +{ + PIRA, 8, /* PIRQA Routing Control */ + PIRB, 8, /* PIRQB Routing Control */ + PIRC, 8, /* PIRQC Routing Control */ + PIRD, 8, /* PIRQD Routing Control */ + PIRE, 8, /* PIRQE Routing Control */ + PIRF, 8, /* PIRQF Routing Control */ + PIRG, 8, /* PIRQG Routing Control */ + PIRH, 8, /* PIRQH Routing Control */ +} + +Name (IREN, 0x80) /* Interrupt Routing Enable */ +Name (IREM, 0x0f) /* Interrupt Routing Mask */ + +Name (PRSA, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,7,10,11,12,14,15} +}) +Alias (PRSA, PRSB) +Name (PRSC, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,10,11,12,14,15} +}) +Alias (PRSC, PRSD) +Alias (PRSA, PRSE) +Alias (PRSA, PRSF) +Alias (PRSA, PRSG) +Alias (PRSA, PRSH) + +#define MAKE_LINK_DEV(id,uid) \ + Device (LNK##id) \ + { \ + Name (_HID, EISAID ("PNP0C0F")) \ + Name (_UID, ##uid) \ + Method (_PRS, 0, NotSerialized) \ + { \ + Return (PRS##id) \ + } \ + Method (_CRS, 0, Serialized) \ + { \ + Name (RTLA, ResourceTemplate () \ + { \ + IRQ (Level, ActiveLow, Shared) {} \ + }) \ + CreateWordField (RTLA, 1, IRQ0) \ + Store (Zero, IRQ0) \ + \ + /* Set the bit from PIRQ Routing Register */ \ + ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ + Return (RTLA) \ + } \ + Method (_SRS, 1, Serialized) \ + { \ + CreateWordField (Arg0, 1, IRQ0) \ + FindSetRightBit (IRQ0, Local0) \ + Decrement (Local0) \ + Store (Local0, ^^PIR##id) \ + } \ + Method (_STA, 0, Serialized) \ + { \ + If (And (^^PIR##id, ^^IREN)) { \ + Return (0x9) \ + } Else { \ + Return (0xb) \ + } \ + } \ + Method (_DIS, 0, Serialized) \ + { \ + Or (^^PIR##id, ^^IREN, ^^PIR##id) \ + } \ + } + +MAKE_LINK_DEV(A,1) +MAKE_LINK_DEV(B,2) +MAKE_LINK_DEV(C,3) +MAKE_LINK_DEV(D,4) +MAKE_LINK_DEV(E,5) +MAKE_LINK_DEV(F,6) +MAKE_LINK_DEV(G,7) +MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl new file mode 100644 index 0000000000..35fbf98bae --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/uncore.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include +#include +#include + +Scope(\) +{ + // Private Chipset Register(PCR). Memory Mapped through ILB + OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000) + Field(PCRR, DWordAcc, Lock, Preserve) + { + Offset (0xD03100), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } +} + +Scope (_SB) +{ + #include "pci_irq.asl" + #include "uncore_irq.asl" + #include "iiostack.asl" +} diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl new file mode 100644 index 0000000000..8492725334 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl @@ -0,0 +1,566 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Uncore devices PCI interrupt routing packages. + * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. + * The mapping fields ae Address, Pin, Source, Source Index. + */ + +#define GEN_PCIE_LEGACY_IRQ() \ + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ + Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ + Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 } + +#define GEN_UNCORE_LEGACY_IRQ(dev) \ + Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \ + Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \ + Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \ + Package (0x04) { ##dev, 0x03, LNKD, 0x00 } + +#define GEN_PCIE_IOAPIC_IRQ(irq) \ + Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \ + Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq } + +#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ + Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \ + Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \ + Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \ + Package (0x04) { ##dev, 0x03, 0x00, ##irq4 } + +// Socket 0, IIOStack 0 device legacy interrupt routing +Name (PR00, Package (0x28) +{ + // [DMI0]: Legacy PCI Express Port 0 + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + // [CB0A]: CBDMA + // [CB0E]: CBDMA + Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + // [CB0B]: CBDMA + // [CB0F]: CBDMA + Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 }, + // [CB0C]: CBDMA + // [CB0G]: CBDMA + Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 }, + // [CB0D]: CBDMA + // [CB0H]: CBDMA + Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 }, + // Uncore 0 UBOX Device + Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 }, + // [DISP]: Display Controller + Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + // [IHC2]: HECI #2 + Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 }, + // // [XHCI]: xHCI controller 1 on PCH + Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + // [TERM]: Thermal Subsystem on PCH + Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + // [CAMR]: Camera IO Host Controller on PCH + Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 }, + // [HEC2]: HECI #2 on PCH + Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 }, + // [IDER]: ME IDE redirect on PCH + Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 }, + // [MEKT]: MEKT on PCH + Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 }, + // [SAT1]: SATA controller 1 on PCH + Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 }, + // [NAN1]: NAND Cycle Router on PCH + Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 }, + // [RP17]: PCIE PCH Root Port #17 + Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + // [RP18]: PCIE PCH Root Port #18 + Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 }, + // [RP19]: PCIE PCH Root Port #19 + Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 }, + // [RP20]: PCIE PCH Root Port #20 + Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 }, + // [UAR0]: UART #0 on PCH + Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 }, + // [UAR1]: UART #1 on PCH + Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 }, +}) + +// Socket 0, IIOStack 0 device IOAPIC interrupt routing +Name (AR00, Package (0x28) +{ + // [DMI0]: Legacy PCI Express Port 0 + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F }, + // [CB0A]: CB3DMA + // [CB0E]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, + // [CB0B]: CB3DMA + // [CB0F]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + // [CB0C]: CB3DMA + // [CB0G]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + // [CB0D]: CB3DMA + // [CB0H]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + // [UBX0]: Uncore 0 UBOX Device + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E }, + // [DISP]: Display Controller + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 }, + // [IHC2]: HECI #2 + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 }, + // [XHCI]: xHCI controller 1 on PCH + Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 }, + // [TERM]: Thermal Subsystem on PCH + Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 }, + // [CAMR]: Camera IO Host Controller on PCH + Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 }, + // [HEC2]: HECI #2 on PCH + Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 }, + // [IDER]: ME IDE redirect on PCH + Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 }, + // [MEKT]: MEKT on PCH + Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 }, + // [SAT1]: SATA controller 1 on PCH + Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 }, + // [NAN1]: NAND Cycle Router on PCH + Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 }, + // [RP17]: PCIE PCH Root Port #17 + Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + // [RP18]: PCIE PCH Root Port #18 + Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 }, + // [RP19]: PCIE PCH Root Port #19 + Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 }, + // [RP20]: PCIE PCH Root Port #20 + Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 }, + // [UAR0]: UART #0 on PCH + Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 }, + // [UAR1]: UART #1 on PCH + Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 }, +}) + +// Socket 0, IIOStack 1 device legacy interrupt routing +Name (PR10, Package (0x40) +{ + // PCI Express Port 1A-1D + GEN_PCIE_LEGACY_IRQ(), + + // Uncore CHAUTIL Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + + // Uncore CHASAD Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), + + // Uncore CMSCHA Devices + GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), + + // Uncore CHASADALL Device + GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), + + // Uncore PCUCR Device + GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), + + // Uncore VCUCR Device + GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) +}) + +// Socket 0, IIOStack 1 device IOAPIC interrupt routing +Name (AR10, Package (0x40) +{ + // PCI Express Port 1A-1D + GEN_PCIE_IOAPIC_IRQ(0x27), + + // Uncore CHAUTIL Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CHASAD Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CMSCHA Devices + GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CHASADALL Device + GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore PCUCR Device + GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore VCUCR Device + GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x20, 0x24, 0x25, 0x26) +}) + +// Socket 0, IIOStack 2 device legacy interrupt routing +Name (PR20, Package (0x24) +{ + // PCI Express Port 2 on PC02 + GEN_PCIE_LEGACY_IRQ(), + + // Uncore M2MEM Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + + // Uncore MCMAIN Device + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + + // Uncore MCDECS2 Device + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + + // Uncore MCMAIN Device + GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), + + // Uncore MCDECS Device + GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), + + // Uncore Unicast MC0 DDRIO0 Device + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + + // Uncore Unicast MC1 DDRIO0 Device + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 0, IIOStack 2 device IOAPIC interrupt routing +Name (AR20, Package (0x24) +{ + // PCI Express Port 2 on PC02 + GEN_PCIE_IOAPIC_IRQ(0x2F), + + // Uncore M2MEM Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCMAIN Device + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCDECS2 Device + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCMAIN Device + GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCDECS Device + GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore Unicast MC0 DDRIO0 Device + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore Unicast MC1 DDRIO0 Device + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x28, 0x2C, 0x2D, 0x2E) +}) + +// Socket 0, IIOStack 3 device legacy interrupt routing +Name (PR28, Package (0x20) +{ + // PCI Express Port 3 on PC03 + GEN_PCIE_LEGACY_IRQ(), + + // KTI Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + + // M3K Device + GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), + + // M2U Device + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + + // M2D Device + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + + // M20 Device + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 0, IIOStack 3 device IOAPIC interrupt routing +Name (AR28, Package (0x20) +{ + // PCI Express Port 3 on PC03 + GEN_PCIE_IOAPIC_IRQ(0x37), + + // KTI Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x30, 0x34, 0x35, 0x36), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x30, 0x34, 0x35, 0x36), + + // M3K Device + GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x30, 0x34, 0x35, 0x36), + + // M2U Device + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x30, 0x34, 0x35, 0x36), + + // M2D Device + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x30, 0x34, 0x35, 0x36), + + // M20 Device + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x30, 0x34, 0x35, 0x36) +}) + +// Socket 1, IIOStack 0 device legacy interrupt routing +Name (PR40, Package (0x09) +{ + // DMI + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + + // CBDMA + GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), + + // Ubox + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF) +}) + +// Socket 1, IIOStack 0 device IOAPIC interrupt routing +Name (AR40, Package (0x09) +{ + // DMI + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F }, + + // CBDMA + GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), + + // Ubox + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x48, 0x4C, 0x4D, 0x4E), +}) + +// Socket 1, IIOStack 1 device legacy interrupt routing +Name (PR50, Package (0x40) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // CHA Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), + GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), + + // PCU Devices + GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) +}) + +// Socket 1, IIOStack 1 device IOAPIC interrupt routing +Name (AR50, Package (0x40) +{ + // PCI Express Port + GEN_PCIE_IOAPIC_IRQ(0x57), + + // CHA Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x50, 0x54, 0x55, 0x56), + + // PCU Devices + GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x50, 0x54, 0x55, 0x56) +}) + +// Socket 1, IIOStack 2 device legacy interrupt routing +Name (PR60, Package (0x24) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // Integrated Memory Controller + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + + // Uncore Devices + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 1, IIOStack 2 device IOAPIC interrupt routing +Name (AR60, Package (0x24) +{ + // PCI Express Port + GEN_PCIE_IOAPIC_IRQ(0x5F), + + // Integrated Memory Controller + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x58, 0x5C, 0x5D, 0x5E), + + // Uncore Devices + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x58, 0x5C, 0x5D, 0x5E) +}) + +// Socket 1, IIOStack 3 device legacy interrupt routing +Name (PR68, Package (0x20) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // Uncore Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 1, IIOStack 3 device legacy interrupt routing +Name (AR68, Package (0x20) +{ + // PCI Express Port + GEN_PCIE_IOAPIC_IRQ(0x67), + + // Uncore Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x60, 0x64, 0x65, 0x66) +}) diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c new file mode 100644 index 0000000000..482f5b522b --- /dev/null +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = FSPT_UPD_SIGNATURE, + .Revision = 1, + .Reserved = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, + .Reserved1 = {0}, + }, + .FsptConfig = { + .PcdFsptPort80RouteDisable = 0, + .ReservedTempRamInitUpd = {0}, + }, + .UnusedUpdSpace0 = {0}, + .UpdTerminator = 0x55AA, +}; + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + fast_spi_cache_bios_region(); + + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); +} + +void bootblock_soc_init(void) +{ + if (CONFIG(BOOTBLOCK_CONSOLE)) + printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); +} diff --git a/src/soc/intel/xeon_sp/chip.c b/src/soc/intel/xeon_sp/chip.c new file mode 100644 index 0000000000..832f98e63b --- /dev/null +++ b/src/soc/intel/xeon_sp/chip.c @@ -0,0 +1,603 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +struct pci_resource { + struct device *dev; + struct resource *res; + struct pci_resource *next; +}; + +struct stack_dev_resource { + uint8_t align; + struct pci_resource *children; + struct stack_dev_resource *next; +}; + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge); + +static void xeonsp_pci_domain_scan_bus(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + struct bus *link = dev->link_list; + + printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", + __FILE__, __func__, dev_path(dev)); + while (link != NULL) { + if (link->secondary == 0) { // scan only PSTACK buses + struct device *d; + for (d = link->children; d; d = d->sibling) + pci_probe_dev(d, link, d->path.pci.devfn); + scan_bridges(link); + } else { + pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); + } + link = link->next; + } + DEV_FUNC_EXIT(dev); +} + +static void xeonsp_pci_dev_iterator(struct bus *bus, + void (*dev_iterator)(struct device *, void *), + void (*res_iterator)(struct device *, struct resource *, void *), + void *data) +{ + struct device *curdev; + struct resource *res; + + /* Walk through all devices and find which resources they need. */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct bus *link; + + if (!curdev->enabled) + continue; + + if (!curdev->ops || !curdev->ops->read_resources) { + if (curdev->path.type != DEVICE_PATH_APIC) + printk(BIOS_ERR, "%s missing read_resources\n", + dev_path(curdev)); + continue; + } + + if (dev_iterator) + dev_iterator(curdev, data); + + if (res_iterator) { + for (res = curdev->resource_list; res; res = res->next) + res_iterator(curdev, res, data); + } + + /* Read in the resources behind the current device's links. */ + for (link = curdev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); + } +} + +static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) +{ + post_log_path(dev); + dev->ops->read_resources(dev); +} + +static void xeonsp_pci_dev_dummy_func(struct device *dev) +{ +} + +static void xeonsp_reset_pci_op(struct device *dev, void *data) +{ + if (dev->ops) + dev->ops->read_resources = xeonsp_pci_dev_dummy_func; +} + +static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) +{ + for (int i = 0; i < info->no_of_stacks; ++i) { + if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) + return &info->res[i]; + } + return NULL; +} + +static void add_res_to_stack(struct stack_dev_resource **root, + struct device *dev, struct resource *res) +{ + struct stack_dev_resource *cur = *root; + while (cur) { + if (cur->align == res->align || cur->next == NULL) /* equal or last record */ + break; + else if (cur->align > res->align) { + if (cur->next->align < res->align) /* need to insert new record here */ + break; + cur = cur->next; + } else { + break; + } + } + + struct stack_dev_resource *nr; + if (!cur || cur->align != res->align) { /* need to add new record */ + nr = malloc(sizeof(struct stack_dev_resource)); + if (nr == 0) + die("assign_resource_to_stack(): out of memory.\n"); + memset(nr, 0, sizeof(struct stack_dev_resource)); + nr->align = res->align; + if (!cur) { + *root = nr; /* head node */ + } else if (cur->align > nr->align) { + if (cur->next == NULL) { + cur->next = nr; + } else { + nr->next = cur->next; + cur->next = nr; + } + } else { /* insert in the beginning */ + nr->next = cur; + *root = nr; + } + } else { + nr = cur; + } + + assert(nr != NULL && nr->align == res->align); + + struct pci_resource *npr = malloc(sizeof(struct pci_resource)); + if (npr == NULL) + die("%s: out of memory.\n", __func__); + npr->res = res; + npr->dev = dev; + npr->next = NULL; + + if (nr->children == NULL) { + nr->children = npr; + } else { + struct pci_resource *pr = nr->children; + while (pr->next != NULL) + pr = pr->next; + pr->next = npr; + } +} + +static void reserve_dev_resources(STACK_RES *stack, unsigned long res_type, + struct stack_dev_resource *res_root, struct resource *bridge) +{ + uint8_t align; + uint64_t orig_base, base; + + if (res_type & IORESOURCE_IO) + orig_base = stack->PciResourceIoBase; + else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || + (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) + orig_base = stack->PciResourceMem64Base; + else + orig_base = stack->PciResourceMem32Base; + + align = 0; + base = orig_base; + int first = 1; + while (res_root) { /* loop through all devices grouped by alignment requirements */ + struct pci_resource *pr = res_root->children; + while (pr) { + if (first) { + if (bridge) { /* takes highest alignment */ + if (bridge->align < pr->res->align) + bridge->align = pr->res->align; + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + } else { + orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); + } + base = orig_base; + + if (bridge) + bridge->base = base; + pr->res->base = base; + first = 0; + } else { + pr->res->base = ALIGN_UP(base, 1 << pr->res->align); + } + pr->res->limit = pr->res->base + pr->res->size - 1; + base = pr->res->limit + 1; + pr->res->flags |= (IORESOURCE_ASSIGNED); + pr = pr->next; + } + res_root = res_root->next; + } + + if (bridge) { + /* this bridge doesn't have any resources, will set it to default window */ + if (first) { + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + bridge->base = orig_base; + base = orig_base + (1ULL << bridge->gran); + } + + bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; + + bridge->limit = bridge->base + bridge->size - 1; + bridge->flags |= (IORESOURCE_ASSIGNED); + base = bridge->limit + 1; + } + + /* update new limits */ + if (res_type & IORESOURCE_IO) + stack->PciResourceIoBase = base; + else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || + (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) + stack->PciResourceMem64Base = base; + else + stack->PciResourceMem32Base = base; +} + +static void reclaim_resource_mem(struct stack_dev_resource *res_root) +{ + while (res_root) { /* loop through all devices grouped by alignment requirements */ + /* free pci_resource */ + struct pci_resource *pr = res_root->children; + while (pr) { + struct pci_resource *dpr = pr; + pr = pr->next; + free(dpr); + } + + /* free stack_dev_resource */ + struct stack_dev_resource *ddr = res_root; + res_root = res_root->next; + free(ddr); + } +} + +static void assign_bridge_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct resource *res; + if (!dev->enabled) + return; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE) || + (bridge && ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | + IORESOURCE_PREFETCH | IORESOURCE_PCI64)) != + (res->flags & (IORESOURCE_IO | IORESOURCE_MEM | + IORESOURCE_PREFETCH | IORESOURCE_PCI64))))) + continue; + + assign_stack_resources(stack_list, dev, res); + if (!bridge) + continue; + /* for 1st time update, overlading IORESOURCE_ASSIGNED */ + if (!(bridge->flags & IORESOURCE_ASSIGNED)) { + bridge->base = res->base; + bridge->limit = res->limit; + bridge->flags |= (IORESOURCE_ASSIGNED); + } else { + /* update bridge range from child bridge range */ + if (res->base < bridge->base) + bridge->base = res->base; + if (res->limit > bridge->limit) + bridge->limit = res->limit; + } + bridge->size = (bridge->limit - bridge->base + 1); + } +} + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct bus *bus; + + /* Read in the resources behind the current device's links. */ + for (bus = dev->link_list; bus; bus = bus->next) { + struct device *curdev; + STACK_RES *stack; + + /* get IIO stack for this bus */ + stack = find_stack_for_bus(stack_list, bus->secondary); + assert(stack != NULL); + + /* Assign resources to bridge */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) + assign_bridge_resources(stack_list, curdev, bridge); + + /* Pick non-bridged resources for resource allocation for each resource type */ + unsigned long flags[5] = {IORESOURCE_IO, IORESOURCE_MEM, + (IORESOURCE_PCI64|IORESOURCE_MEM), (IORESOURCE_MEM|IORESOURCE_PREFETCH), + (IORESOURCE_PCI64|IORESOURCE_MEM|IORESOURCE_PREFETCH)}; + uint8_t no_res_types = 5; + if (bridge) { + flags[0] = bridge->flags & + (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); + if ((bridge->flags & IORESOURCE_MEM) && + (bridge->flags & IORESOURCE_PREFETCH)) + flags[0] |= IORESOURCE_PCI64; + no_res_types = 1; + } + + /* Process each resource type */ + for (int rt = 0; rt < no_res_types; ++rt) { + struct stack_dev_resource *res_root = NULL; + + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct resource *res; + if (!curdev->enabled) + continue; + + for (res = curdev->resource_list; res; res = res->next) { + if ((res->flags & IORESOURCE_BRIDGE) || (res->flags & + (IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_ASSIGNED) + ) || ((res->flags & (IORESOURCE_IO | + IORESOURCE_MEM | IORESOURCE_PCI64 + | IORESOURCE_PREFETCH)) + != flags[rt]) || res->size == 0) + continue; + else + add_res_to_stack(&res_root, curdev, res); + } + } + + /* Allocate resources and update bridge range */ + if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { + reserve_dev_resources(stack, flags[rt], res_root, bridge); + reclaim_resource_mem(res_root); + } + } + } +} + +static void xeonsp_constrain_pci_resources(struct device *dev, struct resource *res, void *data) +{ + STACK_RES *stack = (STACK_RES *) data; + if (!(res->flags & IORESOURCE_FIXED)) + return; + + uint64_t base, limit; + if (res->flags & IORESOURCE_IO) { + base = stack->PciResourceIoBase; + limit = stack->PciResourceIoLimit; + } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { + base = stack->PciResourceMem64Base; + limit = stack->PciResourceMem64Limit; + } else { + base = stack->PciResourceMem32Base; + limit = stack->PciResourceMem32Limit; + } + + if (((res->base + res->size - 1) < base) || (res->base > limit)) /* outside window */ + return; + + if (res->limit > limit) /* resource end is out of limit */ + limit = res->base - 1; + else + base = res->base + res->size; + + if (res->flags & IORESOURCE_IO) { + stack->PciResourceIoBase = base; + stack->PciResourceIoLimit = limit; + } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { + stack->PciResourceMem64Base = base; + stack->PciResourceMem64Limit = limit; + } else { + stack->PciResourceMem32Base = base; + stack->PciResourceMem32Limit = limit; + } +} + +static void xeonsp_pci_domain_read_resources(struct device *dev) +{ + struct bus *link; + + DEV_FUNC_ENTER(dev); + + pci_domain_read_resources(dev); + + /* + * Walk through all devices in this domain and read resources. + * Since there is no callback when read resource operation is + * complete for all devices, domain read resource function initiates + * read resources for all devices and swaps read resource operation + * with dummy function to avoid warning. + */ + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); + + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); + + /* + * 1. group devices, resources for each stack + * 2. order resources in descending order of requested resource allocation sizes + */ + struct iiostack_resource stack_info = {0}; + get_iiostack_info(&stack_info); + + /* constrain stack window */ + for (link = dev->link_list; link; link = link->next) { + STACK_RES *stack = find_stack_for_bus(&stack_info, link->secondary); + assert(stack != 0); + xeonsp_pci_dev_iterator(link, NULL, xeonsp_constrain_pci_resources, stack); + } + + /* assign resources */ + assign_stack_resources(&stack_info, dev, NULL); + + DEV_FUNC_EXIT(dev); +} + +static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) +{ + if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && + !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { + res->flags &= ~IORESOURCE_ASSIGNED; + } +} + +static void xeonsp_pci_domain_set_resources(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + + print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); + + /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ + xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); + + /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ + xeonsp_pci_domain_read_resources(dev); + + struct bus *link = dev->link_list; + while (link != NULL) { + assign_resources(link); + link = link->next; + } + + print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); + + DEV_FUNC_EXIT(dev); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &xeonsp_pci_domain_set_resources, + .scan_bus = &xeonsp_pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = &northbridge_write_acpi_tables, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = xeon_sp_init_cpus, + .scan_bus = NULL, +#if CONFIG(HAVE_ACPI_TABLES) + /* defined in src/soc/intel/common/block/acpi/acpi.c */ + .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif +}; + +/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ +static void attach_iio_stacks(struct device *dev) +{ + struct bus *iiostack_bus; + struct device dummy; + struct iiostack_resource stack_info = {0}; + + DEV_FUNC_ENTER(dev); + + get_iiostack_info(&stack_info); + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + /* only non zero bus no. needs to be enumerated */ + if (stack_info.res[s].BusBase == 0) + continue; + + iiostack_bus = malloc(sizeof(struct bus)); + if (iiostack_bus == NULL) + die("%s: out of memory.\n", __func__); + memset(iiostack_bus, 0, sizeof(*iiostack_bus)); + memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); + iiostack_bus->secondary = stack_info.res[s].BusBase; + iiostack_bus->subordinate = stack_info.res[s].BusBase; + iiostack_bus->dev = NULL; + iiostack_bus->children = NULL; + iiostack_bus->next = NULL; + iiostack_bus->link_num = 1; + + dummy.bus = iiostack_bus; + dummy.path.type = DEVICE_PATH_PCI; + dummy.path.pci.devfn = 0; + uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); + if (id == 0xffffffff) + printk(BIOS_WARNING, "IIO Stack device %s not visible\n", + dev_path(&dummy)); + + if (dev->link_list == NULL) { + dev->link_list = iiostack_bus; + } else { + struct bus *nlink = dev->link_list; + while (nlink->next != NULL) + nlink = nlink->next; + nlink->next = iiostack_bus; + } + } + + DEV_FUNC_EXIT(dev); +} + +static void soc_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + attach_iio_stacks(dev); + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void soc_init(void *data) +{ + printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); + fsp_silicon_init(false); +} + +static void soc_final(void *data) +{ + // Temp Fix - should be done by FSP, in 2S bios completion + // is not carried out on socket 2 + set_bios_init_completion(); +} + +static void soc_silicon_init_params(FSPS_UPD *silupd) +{ +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) +{ + const struct microcode *microcode_file; + size_t microcode_len; + + microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, µcode_len); + + if ((microcode_file != NULL) && (microcode_len != 0)) { + /* Update CPU Microcode patch base address/size */ + silupd->FspsConfig.PcdCpuMicrocodePatchBase = + (uint32_t)microcode_file; + silupd->FspsConfig.PcdCpuMicrocodePatchSize = + (uint32_t)microcode_len; + } + + soc_silicon_init_params(silupd); + mainboard_silicon_init_params(silupd); +} + +struct chip_operations soc_intel_xeon_sp_ops = { + CHIP_NAME("Intel Xeon-SP SOC") + .enable_dev = soc_enable_dev, + .init = soc_init, + .final = soc_final +}; + +struct pci_operations soc_pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h new file mode 100644 index 0000000000..72f2445bba --- /dev/null +++ b/src/soc/intel/xeon_sp/chip.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include +#include +#include + +struct soc_intel_xeon_sp_config { + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + /** + * Device Interrupt Routing configuration + * Interrupt Pin x Route. + * 0h = PIRQA# + * 1h = PIRQB# + * 2h = PIRQC# + * 3h = PIRQD# + * 4h = PIRQE# + * 5h = PIRQF# + * 6h = PIRQG# + * 7h = PIRQH# + */ + uint16_t ir00_routing; + uint16_t ir01_routing; + uint16_t ir02_routing; + uint16_t ir03_routing; + uint16_t ir04_routing; + + /** + * Device Interrupt Polarity Control + * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + */ + uint32_t ipc0; + uint32_t ipc1; + uint32_t ipc2; + uint32_t ipc3; + + uint64_t turbo_ratio_limit; + uint64_t turbo_ratio_limit_cores; + + uint32_t pstate_req_ratio; + + uint32_t vtd_support; + uint32_t coherency_support; + uint32_t ats_support; +}; + +extern struct chip_operations soc_intel_xeon_sp_ops; + +typedef struct soc_intel_xeon_sp_config config_t; + +#endif diff --git a/src/soc/intel/xeon_sp/cpu.c b/src/soc/intel/xeon_sp/cpu.c new file mode 100644 index 0000000000..1d5c5788ab --- /dev/null +++ b/src/soc/intel/xeon_sp/cpu.c @@ -0,0 +1,260 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static const config_t *chip_config = NULL; + +static void xeon_configure_mca(void) +{ + msr_t msr; + struct cpuid_result cpuid_regs; + + /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE + * and CPUID.(EAX=1):EDX[14]==1 MCA*/ + cpuid_regs = cpuid(1); + if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) + return; + + msr = rdmsr(IA32_MCG_CAP); + if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { + /* Enable all error logging */ + msr.lo = msr.hi = 0xffffffff; + wrmsr(IA32_MCG_CTL, msr); + } + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + of these banks are core vs package scope. For now every CPU clears + every bank. */ + mca_configure(); +} + +static void xeon_sp_core_init(struct device *cpu) +{ + msr_t msr; + + printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + assert(chip_config != NULL); + + /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ + msr.hi = 0; + msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); + + /* set MSR_PMG_IO_CAPTURE_BASE - scope per core */ + msr.hi = 0; + msr.lo = (LVL_2_BASE_ADDRESS | CST_RANGE_MAX_C6); + wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); + + /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE + | PROCHOT_LOCK_ENABLE); + wrmsr(MSR_POWER_CTL, msr); + + /* Set P-State ratio */ + msr = rdmsr(MSR_IA32_PERF_CTRL); + msr.lo &= ~PSTATE_REQ_MASK; + msr.lo |= (chip_config->pstate_req_ratio << PSTATE_REQ_SHIFT); + wrmsr(MSR_IA32_PERF_CTRL, msr); + + /* + * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * TODO: Set LOCK_MISC_PWR_MGMT_MSR, Unexpected Exception if you + * lock & issue wrmsr on every thread + * This is package level MSR. Need to check if it updates correctly on + * multi-socket platform. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ + msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | + LOCK_THERM_INT); + wrmsr(MSR_MISC_PWR_MGMT, msr); + } + + /* TODO MSR_VR_MISC_CONFIG */ + + /* Set current limit lock */ + msr = rdmsr(MSR_VR_CURRENT_CONFIG); + msr.lo |= CURRENT_LIMIT_LOCK; + wrmsr(MSR_VR_CURRENT_CONFIG, msr); + + /* Set Turbo Ratio Limits */ + msr.lo = chip_config->turbo_ratio_limit & 0xffffffff; + msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff; + wrmsr(MSR_TURBO_RATIO_LIMIT, msr); + + /* Set Turbo Ratio Limit Cores */ + msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff; + msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff; + wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr); + + /* set Turbo Activation ratio */ + msr.hi = 0; + msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); + msr.lo |= MAX_NON_TURBO_RATIO; + wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); + + /* Enable Fast Strings */ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= FAST_STRINGS_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + + /* Set energy policy */ + msr_t msr1 = rdmsr(MSR_ENERGY_PERF_BIAS_CONFIG); + msr.lo = (msr1.lo & EPB_ENERGY_POLICY_MASK) >> EPB_ENERGY_POLICY_SHIFT; + msr.hi = 0; + wrmsr(MSR_IA32_ENERGY_PERF_BIAS, msr); + + /* Enable Turbo */ + enable_turbo(); + + /* Enable speed step. */ + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= SPEED_STEP_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + } + + /* Clear out pending MCEs */ + xeon_configure_mca(); +} + +static struct device_operations cpu_dev_ops = { + .init = xeon_sp_core_init, +}; + +static const struct cpu_device_id cpu_table[] = { + /* Skylake-SP A0/A1 CPUID 0x506f0*/ + {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_A0_A1}, + /* Skylake-SP B0 CPUID 0x506f1*/ + {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_B0}, + /* Skylake-SP 4 CPUID 0x50654*/ + {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_4}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +static void set_max_turbo_freq(void) +{ + msr_t msr, perf_ctl; + + FUNC_ENTER(); + perf_ctl.hi = 0; + + /* Check for configurable TDP option */ + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "cpu: frequency set to %d\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + FUNC_EXIT(); +} + +/* + * Do essential initialization tasks before APs can be fired up + * + * Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. + */ +static void pre_mp_init(void) +{ + printk(BIOS_DEBUG, "%s: entry\n", __func__); + + x86_setup_fixed_mtrrs(); +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + set_max_turbo_freq(); + + /* + * TODO: Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ +} + +/* + * CPU initialization recipe + * + * Note that no microcode update is passed to the init function. CSE updates + * the microcode on all cores before releasing them from reset. That means that + * the BSP and all APs will come up with the same microcode revision. + */ +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_platform_thread_count, + //.get_smm_info = get_smm_info, /* TODO */ + .get_smm_info = NULL, + //.pre_mp_smm_init = southcluster_smm_clear_state, /* TODO */ + .pre_mp_smm_init = NULL, + //.relocation_handler = relocation_handler, /* TODO */ + .relocation_handler = NULL, + .post_mp_init = post_mp_init, +}; + + +void xeon_sp_init_cpus(struct device *dev) +{ + FUNC_ENTER(); + + /* + * This gets used in cpu device callback. Other than cpu 0, + * rest of the CPU devices do not have + * chip_info updated. Global chip_config is used as workaround + */ + chip_config = dev->chip_info; + + config_reset_cpl3_csrs(); + + /* calls src/cpu/x86/mp_init.c */ + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); + + /* update numa domain for all cpu devices */ + xeonsp_init_cpu_config(); + + FUNC_EXIT(); +} diff --git a/src/soc/intel/xeon_sp/hob_display.c b/src/soc/intel/xeon_sp/hob_display.c new file mode 100644 index 0000000000..15080112f0 --- /dev/null +++ b/src/soc/intel/xeon_sp/hob_display.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; +static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + +struct guid_name_map { + const void *guid; + const char *name; +}; + +static const struct guid_name_map guid_names[] = { + { fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" }, + { fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" }, +}; + +const char *soc_get_guid_name(const uint8_t *guid) +{ + size_t index; + + /* Compare the GUID values in this module */ + for (index = 0; index < ARRAY_SIZE(guid_names); index++) + if (fsp_guid_compare(guid, guid_names[index].guid)) + return guid_names[index].name; + + return NULL; +} + +void soc_display_hob(const struct hob_header *hob) +{ + const struct hob_resource *res; + + res = fsp_hob_header_to_resource(hob); + assert(res != NULL); + printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n", + res->type, res->attribute_type, res->addr, res->length); + printk(BIOS_DEBUG, "\tOwner GUID: "); + fsp_print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid)); + + if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid) == 0) + soc_display_iio_universal_data_hob(); + else if (fsp_guid_compare(res->owner_guid, fsp_hob_memmap_guid) == 0) + soc_display_memmap_hob(); + else + hexdump(hob, hob->length); +} + +void soc_display_memmap_hob(void) +{ + size_t hob_size = 0; + const struct SystemMemoryMapHob *hob = + fsp_find_extension_hob_by_guid(fsp_hob_memmap_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n"); + printk(BIOS_DEBUG, "hob: %p, hob_size: 0x%lx, SystemMemoryMapHob size: 0x%lx, " + "MAX_SOCKET: %d, SAD_RULES: %d\n", + hob, hob_size, sizeof(struct SystemMemoryMapHob), MAX_SOCKET, SAD_RULES); + printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, " + "highMemSize: 0x%x\n", + hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); + printk(BIOS_DEBUG, "\tasilLoMemBase: 0x%x, asilHiMemBase: 0x%x, asilLoMemSize: 0x%x, " + "asilHiMemSize: 0x%x\n", + hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); + printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x, memMode: 0x%x, volMemMode: 0x%x, " + "DimmType: 0x%x, DramType: 0x%x\n", + hob->memSize, hob->memFreq, hob->memMode, hob->volMemMode, + hob->DimmType, hob->DramType); + printk(BIOS_DEBUG, "\tNumChPerMC: 0x%x, numberEntries: 0x%x, maxIMC: 0x%x, maxCh: 0x%x\n", + hob->NumChPerMC, hob->numberEntries, hob->maxIMC, hob->maxCh); + + printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries); + for (int e = 0; e < hob->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &hob->Element[e]; + printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n", + e, mem_element->BaseAddress, + mem_element->ElementSize, mem_element->Type); + } +} + +void soc_display_iio_universal_data_hob(void) +{ + size_t hob_size = 0; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_uds_guid, &hob_size); + + assert(hob != NULL && hob_size != 0); + + printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n"); + + printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n"); + printk(BIOS_DEBUG, "\tcpuType: 0x%x\n", hob->SystemStatus.cpuType); + printk(BIOS_DEBUG, "\tcpuSubType: 0x%x\n", hob->SystemStatus.cpuSubType); + printk(BIOS_DEBUG, "\tSystemRasType: 0x%x\n", hob->SystemStatus.SystemRasType); + printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus); + for (int x = 0; x < MAX_SOCKET; ++x) { + printk(BIOS_DEBUG, "\tSocket %d FusedCores: 0x%x, ActiveCores: 0x%x, " + "MaxCoreToBusRatio: 0x%x, MinCoreToBusRatio: 0x%x\n", + x, hob->SystemStatus.FusedCores[x], hob->SystemStatus.ActiveCores[x], + hob->SystemStatus.MaxCoreToBusRatio[x], + hob->SystemStatus.MinCoreToBusRatio[x]); + } + printk(BIOS_DEBUG, "\tCurrentCoreToBusRatio: 0x%x\n", + hob->SystemStatus.CurrentCoreToBusRatio); + printk(BIOS_DEBUG, "\tIntelSpeedSelectCapable: 0x%x\n", + hob->SystemStatus.IntelSpeedSelectCapable); + printk(BIOS_DEBUG, "\tIssConfigTdpLevelInfo: 0x%x\n", + hob->SystemStatus.IssConfigTdpLevelInfo); + for (int x = 0; x < TDP_MAX_LEVEL; ++x) { + printk(BIOS_DEBUG, "\t\tTDL Level %d IssConfigTdpTdpInfo: 0x%x, " + "IssConfigTdpPowerInfo: 0x%x, IssConfigTdpCoreCount: 0x%x\n", + x, hob->SystemStatus.IssConfigTdpTdpInfo[x], + hob->SystemStatus.IssConfigTdpPowerInfo[x], + hob->SystemStatus.IssConfigTdpCoreCount[x]); + } + printk(BIOS_DEBUG, "\tsocketPresentBitMap: 0x%x\n", + hob->SystemStatus.socketPresentBitMap); + printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit); + printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit); + printk(BIOS_DEBUG, "\tmmCfgBase: 0x%x\n", hob->SystemStatus.mmCfgBase); + printk(BIOS_DEBUG, "\tnumChPerMC: 0x%x\n", hob->SystemStatus.numChPerMC); + printk(BIOS_DEBUG, "\tmaxCh: 0x%x\n", hob->SystemStatus.maxCh); + printk(BIOS_DEBUG, "\tmaxIMC: 0x%x\n", hob->SystemStatus.maxIMC); + + printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n"); + printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase); + printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit); + printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n", + hob->PlatformData.PlatGlobalMmiolBase); + printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n", + hob->PlatformData.PlatGlobalMmiolLimit); + printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n", + hob->PlatformData.PlatGlobalMmiohBase); + printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n", + hob->PlatformData.PlatGlobalMmiohLimit); + printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize); + printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize); + printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase); + printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize); + printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm); + printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO); + printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber); + printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity); + printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity); + printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n", + hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo); + + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s); + printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", + hob->PlatformData.IIO_resource[s].SocketID); + printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].BusBase); + printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].BusLimit); + printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceIoBase); + printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceIoLimit); + printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].IoApicBase); + printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].IoApicLimit); + printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceMem32Base); + printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceMem32Limit); + printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n", + hob->PlatformData.IIO_resource[s].PciResourceMem64Base); + printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n", + hob->PlatformData.IIO_resource[s].PciResourceMem64Limit); + + printk(BIOS_DEBUG, "\t============ Stack Info ================\n"); + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x); + printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); + printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); + printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", + ri->PciResourceIoBase); + printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", + ri->PciResourceIoLimit); + printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase); + printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit); + printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", + ri->PciResourceMem32Base); + printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", + ri->PciResourceMem32Limit); + printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n", + ri->PciResourceMem64Base); + printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n", + ri->PciResourceMem64Limit); + printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress); + } + + printk(BIOS_DEBUG, "\t============ PcieInfo ================\n"); + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[s]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n", + p, iio_resource.PcieInfo.PortInfo[p].Device, + iio_resource.PcieInfo.PortInfo[p].Function); + } + } + + printk(BIOS_DEBUG, "\t============ Bus Bases ===============\n"); + for (int socket = 0; socket < MAX_SOCKET; ++socket) { + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", + socket, stack, + hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]); + } + } +} diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h new file mode 100644 index 0000000000..641a3c5dc4 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_ACPI_H_ +#define _SOC_ACPI_H_ + +#include +#include + +#define MEM_BLK_COUNT 0x140 +typedef struct { + uint8_t buf[32]; +} MEM_BLK; + +void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +unsigned long acpi_madt_irq_overrides(unsigned long current); +void acpi_init_gnvs(global_nvs_t *gnvs); +unsigned long northbridge_write_acpi_tables(struct device *device, + unsigned long current, struct acpi_rsdp *rsdp); +void uncore_inject_dsdt(void); +void motherboard_fill_fadt(acpi_fadt_t *fadt); + +#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/cpu.h b/src/soc/intel/xeon_sp/include/soc/cpu.h new file mode 100644 index 0000000000..82b893c6b3 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/cpu.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CPU_H_ +#define _SOC_CPU_H_ + +#include + +/* SKXSP CPUID */ +#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 +#define CPUID_SKYLAKE_SP_B0 0x506f1 +#define CPUID_SKYLAKE_SP_4 0x50654 + +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 + +int get_cpu_count(void); +void xeon_sp_init_cpus(struct device *dev); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000000..8cb472d515 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_SOC_DEFS_H_ +#define _GPIO_SOC_DEFS_H_ + +/// +/// Skylake-SP chipset GPIO Groups +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPP_J 0x0109 +#define GPIO_SKL_H_GROUP_GPP_K 0x010A +#define GPIO_SKL_H_GROUP_GPP_L 0x010B +#define GPIO_SKL_H_GROUP_GPD 0x010C + +/// +/// SKL H GPIO pins +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A + +#define GPIO_SKL_H_GPP_J0 0x01090000 +#define GPIO_SKL_H_GPP_J1 0x01090001 +#define GPIO_SKL_H_GPP_J2 0x01090002 +#define GPIO_SKL_H_GPP_J3 0x01090003 +#define GPIO_SKL_H_GPP_J4 0x01090004 +#define GPIO_SKL_H_GPP_J5 0x01090005 +#define GPIO_SKL_H_GPP_J6 0x01090006 +#define GPIO_SKL_H_GPP_J7 0x01090007 +#define GPIO_SKL_H_GPP_J8 0x01090008 +#define GPIO_SKL_H_GPP_J9 0x01090009 +#define GPIO_SKL_H_GPP_J10 0x0109000A +#define GPIO_SKL_H_GPP_J11 0x0109000B +#define GPIO_SKL_H_GPP_J12 0x0109000C +#define GPIO_SKL_H_GPP_J13 0x0109000D +#define GPIO_SKL_H_GPP_J14 0x0109000E +#define GPIO_SKL_H_GPP_J15 0x0109000F +#define GPIO_SKL_H_GPP_J16 0x01090010 +#define GPIO_SKL_H_GPP_J17 0x01090011 +#define GPIO_SKL_H_GPP_J18 0x01090012 +#define GPIO_SKL_H_GPP_J19 0x01090013 +#define GPIO_SKL_H_GPP_J20 0x01090014 +#define GPIO_SKL_H_GPP_J21 0x01090015 +#define GPIO_SKL_H_GPP_J22 0x01090016 +#define GPIO_SKL_H_GPP_J23 0x01090017 +#define GPIO_SKL_H_GPP_K0 0x010A0000 +#define GPIO_SKL_H_GPP_K1 0x010A0001 +#define GPIO_SKL_H_GPP_K2 0x010A0002 +#define GPIO_SKL_H_GPP_K3 0x010A0003 +#define GPIO_SKL_H_GPP_K4 0x010A0004 +#define GPIO_SKL_H_GPP_K5 0x010A0005 +#define GPIO_SKL_H_GPP_K6 0x010A0006 +#define GPIO_SKL_H_GPP_K7 0x010A0007 +#define GPIO_SKL_H_GPP_K8 0x010A0008 +#define GPIO_SKL_H_GPP_K9 0x010A0009 +#define GPIO_SKL_H_GPP_K10 0x010A000A +#define GPIO_SKL_H_GPP_L2 0x010B0002 +#define GPIO_SKL_H_GPP_L3 0x010B0003 +#define GPIO_SKL_H_GPP_L4 0x010B0004 +#define GPIO_SKL_H_GPP_L5 0x010B0005 +#define GPIO_SKL_H_GPP_L6 0x010B0006 +#define GPIO_SKL_H_GPP_L7 0x010B0007 +#define GPIO_SKL_H_GPP_L8 0x010B0008 +#define GPIO_SKL_H_GPP_L9 0x010B0009 +#define GPIO_SKL_H_GPP_L10 0x010B000A +#define GPIO_SKL_H_GPP_L11 0x010B000B +#define GPIO_SKL_H_GPP_L12 0x010B000C +#define GPIO_SKL_H_GPP_L13 0x010B000D +#define GPIO_SKL_H_GPP_L14 0x010B000E +#define GPIO_SKL_H_GPP_L15 0x010B000F +#define GPIO_SKL_H_GPP_L16 0x010B0010 +#define GPIO_SKL_H_GPP_L17 0x010B0011 +#define GPIO_SKL_H_GPP_L18 0x010B0012 +#define GPIO_SKL_H_GPP_L19 0x010B0013 +#define GPIO_SKL_H_GPD0 0x010C0000 +#define GPIO_SKL_H_GPD1 0x010C0001 +#define GPIO_SKL_H_GPD2 0x010C0002 +#define GPIO_SKL_H_GPD3 0x010C0003 +#define GPIO_SKL_H_GPD4 0x010C0004 +#define GPIO_SKL_H_GPD5 0x010C0005 +#define GPIO_SKL_H_GPD6 0x010C0006 +#define GPIO_SKL_H_GPD7 0x010C0007 +#define GPIO_SKL_H_GPD8 0x010C0008 +#define GPIO_SKL_H_GPD9 0x010C0009 +#define GPIO_SKL_H_GPD10 0x010C000A +#define GPIO_SKL_H_GPD11 0x010C000B + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h new file mode 100644 index 0000000000..7c825a46bd --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_IOMAP_H_ +#define _SOC_IOMAP_H_ + +#define MAP_ENTRY(reg_, is_64_, is_limit_, mask_bits_, desc_) \ + { \ + .reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_, \ + .mask_bits = mask_bits_, .description = desc_, \ + } + +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 0, desc_) +#define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_) + +// SPI BAR0 MMIO base address +#define SPI_BASE_ADDRESS 0xfe010000 +#define SPI_BASE_SIZE 0x1000 + +#define ACPI_BASE_ADDRESS 0x500 + +/* Video RAM */ +#define VGA_BASE_ADDRESS 0xa0000 +#define VGA_BASE_SIZE 0x20000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS + +#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h new file mode 100644 index 0000000000..06942aeb43 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/irq.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h new file mode 100644 index 0000000000..6004490b1a --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include + +#define IA32_MCG_CAP 0x179 +#define IA32_MCG_CAP_COUNT_MASK 0xff +#define IA32_MCG_CAP_CTL_P_BIT 8 +#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) + +#define IA32_MCG_CTL 0x17b + +/* IA32_MISC_ENABLE bits */ +#define FAST_STRINGS_ENABLE_BIT (1 << 0) +#define SPEED_STEP_ENABLE_BIT (1 << 16) +#define MONIOR_ENABLE_BIT (1 << 18) + +#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 + +/* MSR_PKG_CST_CONFIG_CONTROL bits */ +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +#define PKG_CSTATE_LIMIT_SHIFT 0 /* 0:3 */ +/* No package C-state limit. All C-States supported by the processor are available. */ +#define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT) +#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) +#define IO_MWAIT_REDIRECTION_SHIFT 10 +#define IO_MWAIT_REDIRECTION_ENABLE (1 << IO_MWAIT_REDIRECTION_SHIFT) +#define CFG_LOCK_SHIFT 15 +#define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT) + +/* MSR_PMG_IO_CAPTURE_BASE bits */ +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define LVL_2_BASE_ADDRESS_SHIFT 0 /* 15:0 bits */ +#define LVL_2_BASE_ADDRESS (0x0514 << LVL_2_BASE_ADDRESS_SHIFT) +#define CST_RANGE_SHIFT 16 /* 18:16 bits */ +#define CST_RANGE_MAX_C6 (0x1 << CST_RANGE_SHIFT) + +/* MSR_POWER_CTL bits */ +#define MSR_POWER_CTL 0x1fc +#define BIDIR_PROCHOT_ENABLE_SHIFT 0 +#define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT) +#define FAST_BRK_SNP_ENABLE_SHIFT 3 +#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) +#define FAST_BRK_INT_ENABLE_SHIFT 4 +#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) +#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 +#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) +#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 +#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) +#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 +#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) +#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 +#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) +#define PROCHOT_LOCK_SHIFT 27 +#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) +#define LTR_IIO_DISABLE_SHIFT 29 +#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) + +/* MSR_IA32_PERF_CTRL (0x199) bits */ +#define MSR_IA32_PERF_CTRL 0x199 +#define PSTATE_REQ_SHIFT 8 /* 8:14 bits */ +#define PSTATE_REQ_MASK (0x7f << PSTATE_REQ_SHIFT) +#define PSTATE_REQ_RATIO (0xa << PSTATE_REQ_SHIFT) + +/* MSR_MISC_PWR_MGMT bits */ +#define MSR_MISC_PWR_MGMT 0x1aa +#define HWP_ENUM_SHIFT 6 +#define HWP_ENUM_ENABLE (1 << HWP_ENUM_SHIFT) +#define HWP_EPP_SHIFT 12 +#define HWP_EPP_ENUM_ENABLE (1 << HWP_EPP_SHIFT) +#define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13 +#define LOCK_MISC_PWR_MGMT_MSR (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT) +#define LOCK_THERM_INT_SHIFT 22 +#define LOCK_THERM_INT (1 << LOCK_THERM_INT_SHIFT) + +/* MSR_TURBO_RATIO_LIMIT bits */ +#define MSR_TURBO_RATIO_LIMIT 0x1ad + +/* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */ +#define MSR_TURBO_RATIO_LIMIT_CORES 0x1ae + +/* MSR_VR_CURRENT_CONFIG bits */ +#define MSR_VR_CURRENT_CONFIG 0x601 +#define CURRENT_LIMIT_LOCK_SHIFT 31 +#define CURRENT_LIMIT_LOCK (0x1 << CURRENT_LIMIT_LOCK_SHIFT) + +/* MSR_TURBO_ACTIVATION_RATIO bits */ +#define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define MAX_NON_TURBO_RATIO_SHIFT 0 +#define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT) + +/* MSR_ENERGY_PERF_BIAS_CONFIG bits */ +#define MSR_ENERGY_PERF_BIAS_CONFIG 0xa01 +#define EPB_ENERGY_POLICY_SHIFT 3 +#define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) + +#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h new file mode 100644 index 0000000000..00dded3427 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 - 2009 coresystems GmbH + * Copyright (C) 2011 Google Inc + * Copyright (C) 2014 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include + +/* TODO - this requires xeon sp, server board support */ +/* NOTE: We do not use intelblocks/nvs.h since it includes + mostly client specific attributes */ +typedef struct global_nvs_t { + uint8_t pcnt; /* 0x00 - Processor Count */ + uint32_t cbmc; /* 0x01 - coreboot memconsole */ + uint8_t rsvd3[251]; +} __packed global_nvs_t; + +#endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pci_devs.h new file mode 100644 index 0000000000..db78c824f3 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pci_devs.h @@ -0,0 +1,186 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PCI_DEVS_H_ +#define _SOC_PCI_DEVS_H_ + +#include +#include + +#define dump_csr(fmt, dev, reg) \ + printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \ + fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ + ((uint32_t)dev >> 12) & 0x07, \ + #reg, reg, pci_mmio_read_config32(dev, reg)) + +#define dump_csr64(fmt, dev, reg) \ + printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \ + fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ + ((uint32_t)dev >> 12) & 0x07, #reg, reg, \ + pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg)) + +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#include +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 5 +#define VTD_FUNC 0 + +#define VTD_TOLM_CSR 0xd0 +#define VTD_TSEG_BASE_CSR 0xa8 +#define VTD_TSEG_LIMIT_CSR 0xac +#define VTD_EXT_CAP_LOW 0x10 +#define VTD_MMCFG_BASE_CSR 0x90 +#define VTD_MMCFG_LIMIT_CSR 0x98 +#define VTD_TOHM_CSR 0xd4 +#define VTD_MMIOL_CSR 0xdc +#define VTD_ME_BASE_CSR 0xf0 +#define VTD_ME_LIMIT_CSR 0xf8 +#define VTD_VERSION 0x00 +#define VTD_CAP 0x08 +#define VTD_CAP_LOW 0x08 +#define VTD_CAP_HIGH 0x0C +#define VTD_EXT_CAP_HIGH 0x14 + +#define SAD_ALL_DEV 29 +#define SAD_ALL_FUNC 0 +#define SAD_ALL_PAM0123_CSR 0x40 +#define SAD_ALL_PAM456_CSR 0x44 + +#define PCU_IIO_STACK 1 +#define PCU_DEV 30 +#define PCU_CR1_FUN 1 + +#define PCU_CR0_FUN 0 +#define PCU_CR0_PLATFORM_INFO 0xa8 +#define PCU_CR0_P_STATE_LIMITS 0xd8 +#define P_STATE_LIMITS_LOCK_SHIFT 31 +#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT) +#define PCU_CR0_TEMPERATURE_TARGET 0xe4 +#define PCU_CR0_PACKAGE_RAPL_LIMIT 0xe8 +#define PCU_CR0_CURRENT_CONFIG 0xf8 +#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ +#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) + +#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 +#define RST_CPL1_MASK ((uint32_t)1 << 1) +#define RST_CPL2_MASK ((uint32_t)1 << 2) +#define RST_CPL3_MASK ((uint32_t)1 << 3) +#define RST_CPL4_MASK ((uint32_t)1 << 4) +#define PCODE_INIT_DONE1_MASK ((uint32_t)1 << 9) +#define PCODE_INIT_DONE2_MASK ((uint32_t)1 << 10) +#define PCODE_INIT_DONE3_MASK ((uint32_t)1 << 11) +#define PCODE_INIT_DONE4_MASK ((uint32_t)1 << 12) + +#define PCU_CR1_BIOS_MB_DATA_REG 0x8c + +#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 +#define BIOS_MB_RUN_BUSY_MASK ((uint32_t)1 << 31) +#define BIOS_MB_CMD_MASK ((uint32_t)0xff) +#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 +#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 +#define BIOS_ERR_INVALID_CMD 0x01 + +#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK ((uint32_t)1 << 31) + +#define PCU_CR1_C2C3TT_REG 0xdc +#define PCU_CR1_PCIE_ILTR_OVRD 0xfc +#define PCU_CR1_SAPMCTL 0xb0 +#define SAPMCTL_LOCK_SHIFT 31 +#define SAPMCTL_LOCK_MASK (1 << SAPMCTL_LOCK_SHIFT) +#define PCU_CR1_MC_BIOS_REQ 0x98 + +#define PCU_CR2_FUN 2 +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c +#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */ +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90 +#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */ +#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc +#define UNCORE_PLIMIT_OVERRIDE_BIT 20 +#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT) +#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 +#define PROCHOT_RATIO 0xa /* bits 0:7 */ + +#define UBOX_DECS_BUS 0 +#define UBOX_DECS_DEV 8 +#define UBOX_DECS_FUNC 2 +#define UBOX_DECS_CPUBUSNO_CSR 0xcc + +#define CHA_UTIL_ALL_DEV 29 +#define CHA_UTIL_ALL_FUNC 1 +#define CHA_UTIL_ALL_MMCFG_CSR 0xc0 + +#define CBDMA_DEV_NUM 0x04 +#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function +#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB + +#define VMD_DEV_NUM 5 +#define VMD_FUNC_NUM 5 + +#define APIC_DEV_NUM 5 +#define APIC_FUNC_NUM 0 + +#define PCH_IOAPIC_BUS_NUMBER 0xF0 +#define PCH_IOAPIC_DEV_NUM 0x1F +#define PCH_IOAPIC_FUNC_NUM 0x00 + +// ================================== IOAPIC Definitions for DMAR/ACPI ==================== +#define PCH_IOAPIC_ID 0x08 +#define PC00_IOAPIC_ID 0x09 +#define PC01_IOAPIC_ID 0x0A +#define PC02_IOAPIC_ID 0x0B +#define PC03_IOAPIC_ID 0x0C +#define PC04_IOAPIC_ID 0x0D +#define PC05_IOAPIC_ID 0x0E +#define PC06_IOAPIC_ID 0x0F +#define PC07_IOAPIC_ID 0x10 +#define PC08_IOAPIC_ID 0x11 +#define PC09_IOAPIC_ID 0x12 +#define PC10_IOAPIC_ID 0x13 +#define PC11_IOAPIC_ID 0x14 + +/* PCH Device info */ + +#define XHCI_BUS_NUMBER 0x0 +#define PCH_DEV_SLOT_XHCI 0x14 +#define XHCI_FUNC_NUM 0x0 + +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0x00 + +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5) + +#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h new file mode 100644 index 0000000000..c67969237f --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PCR_IDS_H_ +#define _PCR_IDS_H_ + +#define PID_ITSS 0xC4 +#define PID_RTC 0xC3 + +#endif /* _PCR_IDS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h new file mode 100644 index 0000000000..ea111cdef9 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#include +#include + +#define PM1_CNT 0x04 +#define PM1_STS 0x00 +#define PM1_TMR 0x08 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x80 + (x * 4)) + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h new file mode 100644 index 0000000000..c080749bf0 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PMC_H_ +#define _SOC_PMC_H_ + +/* PCI Configuration Space (D31:F2): PMC */ +#define PMC_ACPI_CNT 0x44 + +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 + +#define SCI_IRQ_ADJUST 0 + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h new file mode 100644 index 0000000000..c012dd6cbd --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include +#include +#include +#include + +void xeon_sp_init_cpus(struct device *dev); +void mainboard_silicon_init_params(FSPS_UPD *params); + +extern struct pci_operations soc_pci_ops; + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h new file mode 100644 index 0000000000..623306ffbe --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include + +/* These functions are weak and can be overridden by a mainboard functions. */ +void mainboard_memory_init_params(FSPM_UPD * mupd); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/soc_util.h b/src/soc/intel/xeon_sp/include/soc/soc_util.h new file mode 100644 index 0000000000..8b5e1a2ff7 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/soc_util.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_UTIL_H_ +#define _SOC_UTIL_H_ + +#include +#include +#include + +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ + (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) + +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) + +#define FUNC_ENTER() \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) + +#define FUNC_EXIT() \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) + +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; +}; + +uintptr_t get_tolm(uint32_t bus); +void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit); +uintptr_t get_cha_mmcfg_base(uint32_t bus); +uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory + +uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); + +void get_stack_busnos(uint32_t *bus); +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); +void get_iiostack_info(struct iiostack_resource *info); + +int get_threads_per_package(void); +int get_platform_thread_count(void); +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); + +unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem); +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, + uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); + +void unlock_pam_regions(void); +void xeonsp_init_cpu_config(void); +void set_bios_init_completion(void); +void config_reset_cpl3_csrs(void); + +#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c new file mode 100644 index 0000000000..b0ba68147b --- /dev/null +++ b/src/soc/intel/xeon_sp/lpc.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { + { 0, 0 } +}; + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) +{ + return xeon_lpc_fixed_mmio_ranges; +} + +void lpc_soc_init(struct device *dev) +{ + printk(BIOS_SPEW, "pch: lpc_init\n"); + + /* FSP configures IOAPIC and PCHInterrupt Config */ + printk(BIOS_SPEW, "IOAPICID 0x%x, 0x%x\n", + io_apic_read((void *)IO_APIC_ADDR, 0x00), + ((io_apic_read((void *)IO_APIC_ADDR, 0x00) & 0x0f000000) >> 24)); +} + +void pch_lpc_soc_fill_io_resources(struct device *dev) +{ +} diff --git a/src/soc/intel/xeon_sp/reset.c b/src/soc/intel/xeon_sp/reset.c new file mode 100644 index 0000000000..80a452b870 --- /dev/null +++ b/src/soc/intel/xeon_sp/reset.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void chipset_handle_reset(uint32_t status) +{ + die("Reset not implemented!\n"); +} diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c new file mode 100644 index 0000000000..dc94dc6810 --- /dev/null +++ b/src/soc/intel/xeon_sp/romstage.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +asmlinkage void car_stage_entry(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n"); + + console_init(); + rtc_init(); + + fsp_memory_init(false); + printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); + + unlock_pam_regions(); + + if (postcar_frame_init(&pcf, 1 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t)cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram: 0x%lx\n", top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, + MTRR_TYPE_WRBACK); + + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + run_postcar_phase(&pcf); +} + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) +{ +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const config_t *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + mupd->FspmUpdVersion = FSP_UPD_VERSION; + + // ErrorLevel - 0 (disable) to 8 (verbose) + m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; + m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; + + soc_memory_init_params(m_cfg); + + mainboard_memory_init_params(mupd); + + m_cfg->VTdConfig.VTdSupport = config->vtd_support; + m_cfg->VTdConfig.CoherencySupport = config->coherency_support; + m_cfg->VTdConfig.ATS = config->ats_support; +} diff --git a/src/soc/intel/xeon_sp/soc_util.c b/src/soc/intel/xeon_sp/soc_util.c new file mode 100644 index 0000000000..6310bac8a6 --- /dev/null +++ b/src/soc/intel/xeon_sp/soc_util.c @@ -0,0 +1,577 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Get TOLM CSR B0:D5:F0:Offset_d0h + */ +uintptr_t get_tolm(uint32_t bus) +{ + uint32_t w = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TOLM_CSR); + uintptr_t addr = w & 0xfc000000; + printk(BIOS_DEBUG, "VTD_TOLM_CSR 0x%x, addr: 0x%lx\n", w, addr); + return addr; +} + +void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit) +{ + uint32_t w1 = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TSEG_BASE_CSR); + uint32_t wh = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TSEG_LIMIT_CSR); + *base = w1 & 0xfff00000; + *limit = wh & 0xfff00000; +} + +/* + * Get MMCFG CSR B1:D29:F1:Offset_C0h + */ +uintptr_t get_cha_mmcfg_base(uint32_t bus) +{ + uint32_t wl = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, + CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR); + uint32_t wh = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, + CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR + 4); + uintptr_t addr = ((((wh & 0x3fff) << 6) | ((wl >> 26) & 0x3f)) << 26); + printk(BIOS_DEBUG, "CHA_UTIL_ALL_MMCFG_CSR wl: 0x%x, wh: 0x%x, addr: 0x%lx\n", + wl, wh, addr); + return addr; +} + +/* + * Get Socket 0 CPUBUSNO(0), CPUBUSNO(1) PCI bus numbers UBOX (B0:D8:F2:Offset_CCh) + * TODO: D0h + */ +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) +{ + uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, + UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); + if (bus0) + *bus0 = (bus & 0xff); + if (bus1) + *bus1 = (bus >> 8) & 0xff; + if (bus2) + *bus2 = (bus >> 16) & 0xff; + if (bus3) + *bus3 = (bus >> 24) & 0xff; +} + +uint32_t top_of_32bit_ram(void) +{ + uintptr_t mmcfg, tolm; + uint32_t bus0 = 0, bus1 = 0; + uint32_t base = 0, limit = 0; + + get_cpubusnos(&bus0, &bus1, NULL, NULL); + + mmcfg = get_cha_mmcfg_base(bus1); + tolm = get_tolm(bus0); + printk(BIOS_DEBUG, "bus0: 0x%x, bus1: 0x%x, mmcfg: 0x%lx, tolm: 0x%lx\n", + bus0, bus1, mmcfg, tolm); + get_tseg_base_lim(bus0, &base, &limit); + printk(BIOS_DEBUG, "tseg base: 0x%x, limit: 0x%x\n", base, limit); + + /* We will use TSEG base as the top of DRAM */ + return base; +} + +/* + * +-------------------------+ TOLM + * | System Management Mode | + * | code and data | + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + +uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset) +{ + return pci_mmio_read_config32(PCI_DEV(bus, dev, func), offset); +} + +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +{ + size_t hob_size; + const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + + assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); + + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; +} + +/* bus needs to be of size 6 (MAX_IIO_STACK) */ +void get_stack_busnos(uint32_t *bus) +{ + uint32_t reg1, reg2; + + reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xcc); + reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xd0); + + for (int i = 0; i < 4; ++i) + bus[i] = ((reg1 >> (i * 8)) & 0xff); + for (int i = 0; i < 2; ++i) + bus[4+i] = ((reg2 >> (i * 8)) & 0xff); +} + +void unlock_pam_regions(void) +{ + uint32_t bus1 = 0; + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + + get_cpubusnos(NULL, &bus1, NULL, NULL); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + +/* return 1 if command timed out else 0 */ +static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, + uint32_t target) +{ + uint32_t max_delay = 5000; /* 5 seconds max */ + uint32_t step_delay = 50; /* 50 us */ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, max_delay); + while ((pci_mmio_read_config32(dev, reg) & mask) != target) { + udelay(step_delay); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "%s timed out for dev: 0x%x, reg: 0x%x, " + "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); + return 1; /* timedout */ + } + } + return 0; /* successful */ +} + +/* return 1 if command timed out else 0 */ +static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, uint32_t val) +{ + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); + reg &= (uint32_t) ~rst_cpl_mask; + reg |= rst_cpl_mask; + reg |= val; + + /* update BIOS RESET completion bit */ + pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); + + /* wait for PCU ack */ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, + pcode_init_mask); +} + +/* return 1 if command timed out else 0 */ +static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) +{ + /* verify bios is not in busy state */ + if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) + return 1; /* timed out */ + + /* write data to data register */ + printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_DATA_REG, data); + pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); + + /* write the command */ + printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_INTERFACE_REG, + (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); + pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); + + /* wait for completion or time out*/ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + BIOS_MB_RUN_BUSY_MASK, 0); +} + +void config_reset_cpl3_csrs(void) +{ + uint32_t data, plat_info, max_min_turbo_limit_ratio; + + for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + + /* configure PCU_CR0_FUN csrs */ + pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); + data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); + data |= P_STATE_LIMITS_LOCK; + pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + + plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); + dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); + max_min_turbo_limit_ratio = + (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> + MAX_NON_TURBO_LIM_RATIO_SHIFT; + printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", + plat_info, max_min_turbo_limit_ratio); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL); + /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ + data &= 0x0fffffff; + data |= SAPMCTL_LOCK_MASK; + pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); + + data = PCIE_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); + + data = KTI_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); + + data = PROCHOT_RATIO; + printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); + pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); + dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); + + data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); + data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; + pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); + } +} + +static void set_bios_init_completion_for_package(uint32_t socket) +{ + uint32_t data; + uint32_t timedout; + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + /* read pcu config */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) { + /* 2nd try */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) + die("BIOS PCU Misc Config Read timed out.\n"); + + data = pci_mmio_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); + printk(BIOS_SPEW, "%s - pci_mmio_read_config32 reg: 0x%x, data: 0x%x\n", + __func__, PCU_CR1_BIOS_MB_DATA_REG, data); + + /* write PCU config */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); + if (timedout) + die("BIOS PCU Misc Config Write timed out.\n"); + } + + /* update RST_CPL3, PCODE_INIT_DONE3 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, + PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); + if (timedout) + die("BIOS RESET CPL3 timed out.\n"); + + /* update RST_CPL4, PCODE_INIT_DONE4 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, + PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); + if (timedout) + die("BIOS RESET CPL4 timed out.\n"); + /* set CSR_DESIRED_CORES_CFG2 lock bit */ + data = pci_mmio_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); + data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; + printk(BIOS_SPEW, "%s - pci_mmio_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", + __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); + pci_mmio_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); +} + +void set_bios_init_completion(void) +{ + uint32_t sbsp_socket_id = 0; /* TODO - this needs to be configurable */ + + for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { + if (socket == sbsp_socket_id) + continue; + set_bios_init_completion_for_package(socket); + } + set_bios_init_completion_for_package(sbsp_socket_id); +} + +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) +{ + register int ecx; + struct cpuid_result cpuid_regs; + + /* get max index of CPUID */ + cpuid_regs = cpuid(0); + assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ + + *thread_bits = *core_bits = 0; + ecx = 0; + while (1) { + cpuid_regs = cpuid_ext(0xb, ecx); + if (ecx == 0) { + *thread_bits = (cpuid_regs.eax & 0x1f); + } else { + *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; + break; + } + ecx++; + } +} + +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, + uint8_t *package, uint8_t *core, uint8_t *thread) +{ + if (package != NULL) + *package = (apicid >> (thread_bits + core_bits)); + if (core != NULL) + *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); + if (thread != NULL) + *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); +} + +int get_cpu_count(void) +{ + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + + /* these fields are incorrect - need debugging */ + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + return hob->SystemStatus.numCpus; +} + +int get_threads_per_package(void) +{ + unsigned int core_count, thread_count; + cpu_read_topology(&core_count, &thread_count); + return thread_count; +} + +int get_platform_thread_count(void) +{ + return get_cpu_count() * get_threads_per_package(); +} + +void get_iiostack_info(struct iiostack_resource *info) +{ + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + + hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // copy IIO Stack info from FSP HOB + info->no_of_stacks = 0; + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + // TODO: do we have situation with only bux 0 and one stack? + if (ri->BusBase >= ri->BusLimit) + continue; + assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); + memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + } + } +} + +#if ENV_RAMSTAGE + +void xeonsp_init_cpu_config(void) +{ + struct device *dev; + int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; + int num_apics = 0; + uint32_t core_bits, thread_bits; + unsigned int core_count, thread_count; + unsigned int num_cpus; + + /* sort APIC ids in asending order to identify apicid ranges for + each numa domain + */ + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + apic_ids[num_apics++] = dev->path.apic.apic_id; + } + if (num_apics > 1) + bubblesort(apic_ids, num_apics, NUM_ASCENDING); + + num_cpus = get_cpu_count(); + cpu_read_topology(&core_count, &thread_count); + assert(num_apics == (num_cpus * thread_count)); + + /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ + int index = 0; + for (int id = 0; id < num_apics; ++id) { + int apic_id = apic_ids[id]; + if (apic_id & 0x1) { /* 2nd thread */ + apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; + } else { /* 1st thread */ + apic_ids_by_thread[index++] = apic_id; + } + } + + + /* update apic_id, node_id in sorted order */ + num_apics = 0; + get_core_thread_bits(&core_bits, &thread_bits); + for (dev = all_devices; dev; dev = dev->next) { + uint8_t package; + + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; + get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, + &package, NULL, NULL); + dev->path.apic.node_id = package; + printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", + num_apics, dev->path.apic.apic_id, + dev->path.apic.apic_id, dev->path.apic.node_id); + + ++num_apics; + } +} + +unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) +{ + const struct SystemMemoryMapHob *memory_map; + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + unsigned int mmap_index; + + memory_map = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + assert(memory_map != NULL && hob_size != 0); + printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); + + mmap_index = 0; + for (int e = 0; e < memory_map->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; + uint64_t addr = + (uint64_t) ((uint64_t)mem_element->BaseAddress << + MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = + (uint64_t) ((uint64_t)mem_element->ElementSize << + MEM_ADDR_64MB_SHIFT_BITS); + + printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " + "ElementSize: 0x%x, reserved: %d\n", + e, addr, mem_element->BaseAddress, size, + mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); + + assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); + + /* skip reserved memory region */ + if (mem_element->Type & MEM_TYPE_RESERVED) + continue; + + /* skip if this address is already added */ + bool skip = false; + for (int idx = 0; idx < mmap_index; ++idx) { + uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + + srat_mem[idx].base_address_low; + if (addr == base_addr) { + skip = true; + break; + } + } + if (skip) + continue; + + srat_mem[mmap_index].type = 1; /* Memory affinity structure */ + srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); + srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); + srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); + srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); + srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); + srat_mem[mmap_index].proximity_domain = mem_element->SocketId; + srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; + if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) + srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; + ++mmap_index; + } + + return mmap_index; +} + +#endif diff --git a/src/soc/intel/xeon_sp/spi.c b/src/soc/intel/xeon_sp/spi.c new file mode 100644 index 0000000000..18af5e488a --- /dev/null +++ b/src/soc/intel/xeon_sp/spi.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: + return 0; + } + return -1; +} diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c new file mode 100644 index 0000000000..adf3e3e40b --- /dev/null +++ b/src/soc/intel/xeon_sp/uncore.c @@ -0,0 +1,305 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct map_entry { + uint32_t reg; + int is_64_bit; + int is_limit; + int mask_bits; + const char *description; +}; + +enum { + TOHM_REG, + MMIOL_REG, + MMCFG_BASE_REG, + MMCFG_LIMIT_REG, + TOLM_REG, + ME_BASE_REG, + ME_LIMIT_REG, + TSEG_BASE_REG, + TSEG_LIMIT_REG, + /* Must be last. */ + NUM_MAP_ENTRIES +}; + +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"), + [MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"), + [MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(VTD_MMCFG_BASE_CSR, "MMCFG_BASE"), + [MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"), + [TOLM_REG] = MAP_ENTRY_LIMIT_32(VTD_TOLM_CSR, 26, "TOLM"), + [ME_BASE_REG] = MAP_ENTRY_BASE_64(VTD_ME_BASE_CSR, "ME_BASE"), + [ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"), + [TSEG_BASE_REG] = MAP_ENTRY_BASE_32(VTD_TSEG_BASE_CSR, "TSEGMB_BASE"), + [TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"), +}; + +static void read_map_entry(struct device *dev, struct map_entry *entry, + uint64_t *result) +{ + uint64_t value; + uint64_t mask; + + /* All registers are on a 1MiB granularity. */ + mask = ((1ULL << entry->mask_bits) - 1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + sizeof(uint32_t)); + value <<= 32; + } + + value |= (uint64_t)pci_read_config32(dev, entry->reg); + value &= mask; + + if (entry->is_limit) + value |= ~mask; + + *result = value; +} + +static void mc_read_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) + read_map_entry(dev, &memory_map[i], &values[i]); +} + +static void mc_report_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } +} + +/* + * Host Memory Map: + * + * +--------------------------+ TOCM (2 pow 46 - 1) + * | Reserved | + * +--------------------------+ + * | MMIOH (relocatable) | + * +--------------------------+ + * | PCISeg | + * +--------------------------+ TOHM + * | High DRAM Memory | + * +--------------------------+ 4GiB (0x100000000) + * +--------------------------+ 0xFFFF_FFFF + * | Firmware | + * +--------------------------+ 0xFF00_0000 + * | Reserved | + * +--------------------------+ 0xFEF0_0000 + * | Local xAPIC | + * +--------------------------+ 0xFEE0_0000 + * | HPET/LT/TPM/Others | + * +--------------------------+ 0xFED0_0000 + * | I/O xAPIC | + * +--------------------------+ 0xFEC0_0000 + * | Reserved | + * +--------------------------+ 0xFEB8_0000 + * | Reserved | + * +--------------------------+ 0xFEB0_0000 + * | Reserved | + * +--------------------------+ 0xFE00_0000 + * | MMIOL (relocatable) | + * | P2SB PCR cfg BAR | (0xfd000000 - 0xfdffffff + * | BAR space | [mem 0x90000000-0xfcffffff] available for PCI devices + * +--------------------------+ 0x9000_0000 + * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB + * | | (0x80000000 - 0x8fffffff, 0x40000) + * +--------------------------+ TOLM + * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) + * +--------------------------+ + * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ cbmem_top + * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) + * +--------------------------+ + * | Reserved - FSP | (0x6fbfe000 - 0x6fffdfff, 0x400000) + * +--------------------------+ top_of_ram (0x6fbfdfff) + * | Low DRAM Memory | + * +--------------------------+ FFFFF (1MB) + * | E & F segments | + * +--------------------------+ E0000 + * | C & D segments | + * +--------------------------+ C0000 + * | VGA & SMM Memory | + * +--------------------------+ A0000 + * | Conventional Memory | + * | (DOS Range) | + * +--------------------------+ 0 + */ + +static void mc_add_dram_resources(struct device *dev, int *res_count) +{ + struct range_entry fsp_mem; + uint64_t base_kb; + uint64_t size_kb; + uint64_t top_of_ram; + uint64_t mc_values[NUM_MAP_ENTRIES]; + struct resource *resource; + int index = *res_count; + + fsp_find_reserved_memory(&fsp_mem); + + /* Read in the MAP registers and report their values. */ + mc_read_map_entries(dev, &mc_values[0]); + mc_report_map_entries(dev, &mc_values[0]); + + top_of_ram = range_entry_base(&fsp_mem) - 1; + printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", + (uintptr_t) cbmem_top(), range_entry_base(&fsp_mem), + range_entry_end(&fsp_mem), top_of_ram); + + /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ + base_kb = 0; + size_kb = (0xa0000 >> 10); + LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + + /* 1MB -> top_of_ram i.e., fsp_mem_base+1*/ + base_kb = (0x100000 >> 10); + size_kb = (top_of_ram - 0xfffff) >> 10; + LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + + /* + * FSP meomoy, CBMem regions are already added as reserved + * Add TSEG and MESEG Regions as reserved memory + * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM reserved size + * arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE + * typically 0x2000 + * Example config: + * FSP_RESERVED_MEMORY_RESOURCE_HOB + * FspReservedMemoryResource Base : 6FBFE000 + * FspReservedMemoryResource Size : 400000 + * FSP_BOOT_LOADER_TOLUM_HOB + * FspBootLoaderTolum Base : 6FFFE000 + * FspBootLoaderTolum Size : 2000 + */ + + /* Mark TSEG/SMM region as reserved */ + base_kb = (mc_values[TSEG_BASE_REG] >> 10); + size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10; + LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); + reserved_ram_resource(dev, index++, base_kb, size_kb); + + /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ + if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { + base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); + size_kb = (mc_values[TOLM_REG] - mc_values[TSEG_LIMIT_REG]) >> 10; + LOG_MEM_RESOURCE("mmio_tolm", dev, index, base_kb, size_kb); + reserved_ram_resource(dev, index++, base_kb, size_kb); + } + + /* 4GiB -> TOHM */ + if (mc_values[TOHM_REG] > 0x100000000) { + base_kb = (0x100000000 >> 10); + size_kb = (mc_values[TOHM_REG] - 0x100000000 + 1) >> 10; + LOG_MEM_RESOURCE("high_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + } + + /* add MMIO CFG resource */ + resource = new_resource(dev, index++); + resource->base = (resource_t) mc_values[MMCFG_BASE_REG]; + resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - + mc_values[MMCFG_BASE_REG] + 1); + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), + (resource->size >> 10)); + + /* add Local APIC resource */ + resource = new_resource(dev, index++); + resource->base = LAPIC_DEFAULT_BASE; + resource->size = 0x00001000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), + (resource->size >> 10)); + + /* + * Add legacy region as reserved - 0xa000 - 1MB + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + base_kb = VGA_BASE_ADDRESS >> 10; + size_kb = VGA_BASE_SIZE >> 10; + LOG_MEM_RESOURCE("legacy_mmio", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + + base_kb = (0xc0000 >> 10); + size_kb = (0x100000 - 0xc0000) >> 10; + LOG_MEM_RESOURCE("legacy_write_protect", dev, index, base_kb, size_kb); + reserved_ram_resource(dev, index++, base_kb, size_kb); + + *res_count = index; +} + +static void mmapvtd_read_resources(struct device *dev) +{ + int index = 0; + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, &index); +} + +static void mmapvtd_init(struct device *dev) +{ +} + +static struct device_operations mmapvtd_ops = { + .read_resources = mmapvtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = mmapvtd_init, + .ops_pci = &soc_pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_inject_dsdt_generator = NULL, +#endif +}; + +static const unsigned short mmapvtd_ids[] = { + MMAP_VTD_CFG_REG_DEVID, /* Memory Map/Intel® VT-d Configuration Registers */ + 0 +}; + +static const struct pci_driver mmapvtd_driver __pci_driver = { + .ops = &mmapvtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = mmapvtd_ids +}; diff --git a/src/soc/intel/xeon_sp/upd_display.c b/src/soc/intel/xeon_sp/upd_display.c new file mode 100644 index 0000000000..2ae34ed2b9 --- /dev/null +++ b/src/soc/intel/xeon_sp/upd_display.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include + +#define DUMP_UPD(old, new, field) \ + fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field) + +/* Display the UPD parameters for MemoryInit */ +void soc_display_fspm_upd_params( + const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) +{ + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + printk(BIOS_DEBUG, "UPD values for MemoryInit:\n"); + + DUMP_UPD(old, new, PcdFspMrcDebugPrintErrorLevel); + DUMP_UPD(old, new, PcdFspKtiDebugPrintErrorLevel); + DUMP_UPD(old, new, PcdHsuartDevice); + + hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); +} + +/* Display the UPD parameters for SiliconInit */ +void soc_display_fsps_upd_params( + const FSPS_UPD *fsps_old_upd, + const FSPS_UPD *fsps_new_upd) +{ + const FSPS_CONFIG *new; + const FSPS_CONFIG *old; + + old = &fsps_old_upd->FspsConfig; + new = &fsps_new_upd->FspsConfig; + + printk(BIOS_DEBUG, "UPD values for SiliconInit:\n"); + + DUMP_UPD(old, new, PcdBifurcationPcie0); + DUMP_UPD(old, new, PcdBifurcationPcie1); + DUMP_UPD(old, new, PcdActiveCoreCount); + DUMP_UPD(old, new, PcdCpuMicrocodePatchBase); + DUMP_UPD(old, new, PcdCpuMicrocodePatchSize); + DUMP_UPD(old, new, PcdEnablePcie0); + DUMP_UPD(old, new, PcdEnablePcie1); + DUMP_UPD(old, new, PcdEnableEmmc); + DUMP_UPD(old, new, PcdEnableGbE); + DUMP_UPD(old, new, PcdFiaMuxConfigRequestPtr); + DUMP_UPD(old, new, PcdPcieRootPort0DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort1DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort2DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort3DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort4DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort5DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort6DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort7DeEmphasis); + DUMP_UPD(old, new, PcdEMMCDLLConfigPtr); + + hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); +} From 75985f1d0c47ccfcfeaecbfce869dab273b6ad71 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 16 Jan 2020 11:20:09 -0800 Subject: [PATCH 0298/1463] mainboard/ocp: Add support for OCP platform TiogaPass OCP platform Tiogapass is a 2-socket server platform, which is based on a chipset including Intel Skylake-SP processors and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon Scalable Processor family. Following ACPI tables are added: DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR This patchset is tested on a Tiogapass board. It booted with Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets, 18 cores, 2 thread per core); ssh command shows networking is up from Mellanox ConnectX-4 PCIe NIC card. Towards successful gerrit buildbot build, note that: * microcode is in coreboot intel-microcode submodule repo. * IFD binary is included in this patch. * Dummy ME binary is used, as it may take long time for Intel ME binary to be available in public domain. * Fake FSP binary is used, as at this moment the SKX-SP FSP binary is not going to be available in public domain. Known issues (Not intend to address in this initial support for Xeon-SP processors): * c6 state is not supported. * dsdt table is not fully populated, such as processor/socket devices, some PCIe devices. * SMM handlers are not added. Following are some command execution with CentOS booted from local SATA disk: [root@localhost ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 72 On-line CPU(s) list: 0-71 Thread(s) per core: 2 Core(s) per socket: 18 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz Stepping: 4 CPU MHz: 140.415 BogoMIPS: 4626.46 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 25344K NUMA node0 CPU(s): 0-17,36-53 NUMA node1 CPU(s): 18-35,54-71 [root@localhost ~]# ifconfig eth0: flags=4163 mtu 1500 inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255 inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20 inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0 ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet) RX packets 84249 bytes 6371591 (6.0 MiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 8418 bytes 748781 (731.2 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 lo: flags=73 mtu 65536 inet 127.0.0.1 netmask 255.0.0.0 inet6 ::1 prefixlen 128 scopeid 0x10 loop txqueuelen 1000 (Local Loopback) RX packets 613 bytes 63906 (62.4 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 613 bytes 63906 (62.4 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 [root@localhost ~]# cbmem 36 entries total: // Lines were cut to avoid checkpatch.pl warnings Total Time: 96,243,882,140,175,829 Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Tested-by: johnny_lin@wiwynn.com Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- configs/config.ocp_tiogapass | 5 + src/mainboard/ocp/Kconfig | 16 + src/mainboard/ocp/Kconfig.name | 2 + src/mainboard/ocp/tiogapass/Kconfig | 45 + src/mainboard/ocp/tiogapass/Kconfig.name | 2 + src/mainboard/ocp/tiogapass/Makefile.inc | 22 + src/mainboard/ocp/tiogapass/acpi/platform.asl | 382 ++++++ src/mainboard/ocp/tiogapass/acpi_tables.c | 26 + src/mainboard/ocp/tiogapass/board.fmd | 11 + src/mainboard/ocp/tiogapass/board_info.txt | 5 + src/mainboard/ocp/tiogapass/devicetree.cb | 91 ++ src/mainboard/ocp/tiogapass/dsdt.asl | 41 + src/mainboard/ocp/tiogapass/fadt.c | 25 + src/mainboard/ocp/tiogapass/ramstage.c | 21 + src/mainboard/ocp/tiogapass/romstage.c | 60 + src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h | 1019 +++++++++++++++++ src/mainboard/ocp/tiogapass/skxsp_tp_iio.h | 101 ++ 17 files changed, 1874 insertions(+) create mode 100644 configs/config.ocp_tiogapass create mode 100644 src/mainboard/ocp/Kconfig create mode 100644 src/mainboard/ocp/Kconfig.name create mode 100644 src/mainboard/ocp/tiogapass/Kconfig create mode 100644 src/mainboard/ocp/tiogapass/Kconfig.name create mode 100644 src/mainboard/ocp/tiogapass/Makefile.inc create mode 100644 src/mainboard/ocp/tiogapass/acpi/platform.asl create mode 100644 src/mainboard/ocp/tiogapass/acpi_tables.c create mode 100644 src/mainboard/ocp/tiogapass/board.fmd create mode 100644 src/mainboard/ocp/tiogapass/board_info.txt create mode 100644 src/mainboard/ocp/tiogapass/devicetree.cb create mode 100644 src/mainboard/ocp/tiogapass/dsdt.asl create mode 100644 src/mainboard/ocp/tiogapass/fadt.c create mode 100644 src/mainboard/ocp/tiogapass/ramstage.c create mode 100644 src/mainboard/ocp/tiogapass/romstage.c create mode 100644 src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h create mode 100644 src/mainboard/ocp/tiogapass/skxsp_tp_iio.h diff --git a/configs/config.ocp_tiogapass b/configs/config.ocp_tiogapass new file mode 100644 index 0000000000..ca0a5b791a --- /dev/null +++ b/configs/config.ocp_tiogapass @@ -0,0 +1,5 @@ +CONFIG_VENDOR_OCP=y +CONFIG_BOARD_OCP_TIOGAPASS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04" diff --git a/src/mainboard/ocp/Kconfig b/src/mainboard/ocp/Kconfig new file mode 100644 index 0000000000..b748129e81 --- /dev/null +++ b/src/mainboard/ocp/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_OCP + +choice + prompt "Mainboard model" + +source "src/mainboard/ocp/*/Kconfig.name" + +endchoice + +source "src/mainboard/ocp/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Open Compute Project" + +endif # VENDOR_OCP diff --git a/src/mainboard/ocp/Kconfig.name b/src/mainboard/ocp/Kconfig.name new file mode 100644 index 0000000000..f5d8d0a8eb --- /dev/null +++ b/src/mainboard/ocp/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_OCP + bool "Open Compute Project" diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig new file mode 100644 index 0000000000..dfa8f54275 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation. +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_OCP_TIOGAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_XEON_SP + select MAINBOARD_USES_FSP2_0 + select FSP_CAR + +config MAINBOARD_DIR + string + default "ocp/tiogapass" + +config MAINBOARD_PART_NUMBER + string + default "TiogaPass" + +config MAINBOARD_FAMILY + string + default "TiogaPass" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name new file mode 100644 index 0000000000..e1bf821575 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_TIOGAPASS + bool "TiogaPass" diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc new file mode 100644 index 0000000000..f5ea5911f9 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation. +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c + +CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ +CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl new file mode 100644 index 0000000000..e349cf337a --- /dev/null +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -0,0 +1,382 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include + +Name (_S0, Package (0x04) // mandatory system state +{ + 0x00, 0x00, 0x00, 0x00 +}) + +Name (_S5, Package (0x04) // mandatory system state +{ + 0x07, 0x00, 0x00, 0x00 +}) + +/* The APM port can be used for generating software SMIs */ +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + +OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400) +Field (PSYS, ByteAcc, NoLock, Preserve) +{ + PLAT, 32, // Platform ID + + // IOAPIC + APC0, 1, // PCH IOAPIC Enable + AP00, 1, // PC00 IOAPIC Enable + AP01, 1, // PC01 IOAPIC Enable + AP02, 1, // PC02 IOAPIC Enable + AP03, 1, // PC03 IOAPIC Enable + AP04, 1, // PC04 IOAPIC Enable + AP05, 1, // PC05 IOAPIC Enable + AP06, 1, // PC06 IOAPIC Enable + AP07, 1, // PC07 IOAPIC Enable + AP08, 1, // PC08 IOAPIC Enable + AP09, 1, // PC09 IOAPIC Enable + AP10, 1, // PC10 IOAPIC Enable + AP11, 1, // PC11 IOAPIC Enable + AP12, 1, // PC12 IOAPIC Enable + AP13, 1, // PC13 IOAPIC Enable + AP14, 1, // PC14 IOAPIC Enable + AP15, 1, // PC15 IOAPIC Enable + AP16, 1, // PC16 IOAPIC Enable + AP17, 1, // PC17 IOAPIC Enable + AP18, 1, // PC18 IOAPIC Enable + AP19, 1, // PC19 IOAPIC Enable + AP20, 1, // PC20 IOAPIC Enable + AP21, 1, // PC21 IOAPIC Enable + AP22, 1, // PC22 IOAPIC Enable + AP23, 1, // PC23 IOAPIC Enable + RESA, 7, + SKOV, 1, // Override Socket APIC Id + RES0, 7, + + // Power Management + TPME, 1, + CSEN, 1, + C3EN, 1, + C6EN, 1, + C7EN, 1, + MWOS, 1, + PSEN, 1, + EMCA, 1, + HWAL, 2, + KPRS, 1, + MPRS, 1, + TSEN, 1, + FGTS, 1, + OSCX, 1, + RESX, 1, + + // RAS + CPHP, 8, + IIOP, 8, + IIOH, 64, + PRBM, 32, + P0ID, 32, + P1ID, 32, + P2ID, 32, + P3ID, 32, + P4ID, 32, + P5ID, 32, + P6ID, 32, + P7ID, 32, + P0BM, 64, + P1BM, 64, + P2BM, 64, + P3BM, 64, + P4BM, 64, + P5BM, 64, + P6BM, 64, + P7BM, 64, + MEBM, 16, + MEBC, 16, + CFMM, 32, + TSSY, 32, // TODO: This is TSSZ in system booted from production FW + M0BS, 64, + M1BS, 64, + M2BS, 64, + M3BS, 64, + M4BS, 64, + M5BS, 64, + M6BS, 64, + M7BS, 64, + M0RN, 64, + M1RN, 64, + M2RN, 64, + M3RN, 64, + M4RN, 64, + M5RN, 64, + M6RN, 64, + M7RN, 64, + SMI0, 32, + SMI1, 32, + SMI2, 32, + SMI3, 32, + SCI0, 32, + SCI1, 32, + SCI2, 32, + SCI3, 32, + MADD, 64, + CUU0, 128, + CUU1, 128, + CUU2, 128, + CUU3, 128, + CUU4, 128, + CUU5, 128, + CUU6, 128, + CUU7, 128, + CPSP, 8, + ME00, 128, + ME01, 128, + ME10, 128, + ME11, 128, + ME20, 128, + ME21, 128, + ME30, 128, + ME31, 128, + ME40, 128, + ME41, 128, + ME50, 128, + ME51, 128, + ME60, 128, + ME61, 128, + ME70, 128, + ME71, 128, + MESP, 16, + LDIR, 64, + PRID, 32, + AHPE, 8, + + // VTD + DHRD, 192, + ATSR, 192, + RHSA, 192, + + // SR-IOV + WSIC, 8, + WSIS, 16, + WSIB, 8, + WSID, 8, + WSIF, 8, + WSTS, 8, + WHEA, 8, + + // BIOS Guard + BGMA, 64, + BGMS, 8, + BGIO, 16, + BGIL, 8, + CNBS, 8, + + // USB3 + XHMD, 8, + SBV1, 8, + SBV2, 8, + + // HWPM + HWEN, 2, + ACEN, 1, + HWPI, 1, + RES1, 4, + + // IIO + BB00, 8, + BB01, 8, + BB02, 8, + BB03, 8, + BB04, 8, + BB05, 8, + BB06, 8, + BB07, 8, + BB08, 8, + BB09, 8, + BB10, 8, + BB11, 8, + BB12, 8, + BB13, 8, + BB14, 8, + BB15, 8, + BB16, 8, + BB17, 8, + BB18, 8, + BB19, 8, + BB20, 8, + BB21, 8, + BB22, 8, + BB23, 8, + BB24, 8, + BB25, 8, + BB26, 8, + BB27, 8, + BB28, 8, + BB29, 8, + BB30, 8, + BB31, 8, + BB32, 8, + BB33, 8, + BB34, 8, + BB35, 8, + BB36, 8, + BB37, 8, + BB38, 8, + BB39, 8, + BB40, 8, + BB41, 8, + BB42, 8, + BB43, 8, + BB44, 8, + BB45, 8, + BB46, 8, + BB47, 8, + SGEN, 8, + SG00, 8, + SG01, 8, + SG02, 8, + SG03, 8, + SG04, 8, + SG05, 8, + SG06, 8, + SG07, 8, + + // Performance + CLOD, 8, + + // XTU + XTUB, 32, + XTUS, 32, + XMBA, 32, + DDRF, 8, + RT3S, 8, + RTP0, 8, + RTP3, 8, + + // FPGA + FBB0, 8, + FBB1, 8, + FBB2, 8, + FBB3, 8, + FBB4, 8, + FBB5, 8, + FBB6, 8, + FBB7, 8, + FBL0, 8, + FBL1, 8, + FBL2, 8, + FBL3, 8, + FBL4, 8, + FBL5, 8, + FBL6, 8, + FBL7, 8, + P0FB, 8, + P1FB, 8, + P2FB, 8, + P3FB, 8, + P4FB, 8, + P5FB, 8, + P6FB, 8, + P7FB, 8, + FMB0, 32, + FMB1, 32, + FMB2, 32, + FMB3, 32, + FMB4, 32, + FMB5, 32, + FMB6, 32, + FMB7, 32, + FML0, 32, + FML1, 32, + FML2, 32, + FML3, 32, + FML4, 32, + FML5, 32, + FML6, 32, + FML7, 32, + FKPB, 32, + FKB0, 8, + FKB1, 8, + FKB2, 8, + FKB3, 8, + FKB4, 8, + FKB5, 8, + FKB6, 8, + FKB7, 8 +} + +/* SMI I/O Trap */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c new file mode 100644 index 0000000000..c4dda3b357 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +extern const unsigned char AmlCode[]; + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); +} diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd new file mode 100644 index 0000000000..1e3fda7e8b --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board.fmd @@ -0,0 +1,11 @@ +FLASH 32M { + SI_ALL@0x0 0xa36000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0xa23000 + PLATFORM_DATA@0xa26000 0x10000 + } + SI_BIOS@0x1000000 0x1000000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x800 0xfff800 + } +} diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt new file mode 100644 index 0000000000..e86f78f6c3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: TiogaPass +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 2018 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb new file mode 100644 index 0000000000..46311d9823 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -0,0 +1,91 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation. +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/xeon_sp + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # configure device interrupt routing + register "ir00_routing" = "0x3210" # IR00, Dev31 + register "ir01_routing" = "0x3210" # IR01, Dev30 + register "ir02_routing" = "0x3210" # IR02, Dev29 + register "ir03_routing" = "0x3210" # IR03, Dev28 + register "ir04_routing" = "0x3210" # IR04, Dev27 + + # configure interrupt polarity control + register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow + register "ipc1" = "0x00000000" # IPC1 + register "ipc2" = "0x00000000" # IPC2 + register "ipc3" = "0x00000000" # IPC3 + + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + # FB production turbo_ratio_limit is 0x1f1f1f2022222325 + register "turbo_ratio_limit" = "0x1b1b1b1d20222325" + # FB production turbo_ratio_limit_cores is 0x1c1812100c080402 + register "turbo_ratio_limit_cores" = "0x1c1814100c080402" + + # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL + register "pstate_req_ratio" = "0xa" + + # configure VTD + register "vtd_support" = "1" + register "coherency_support" = "1" + register "ats_support" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers + device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers + device pci 05.2 on end # Intel Corporation Device 2025 + device pci 05.4 on end # Intel Corporation Device 2026 + device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers + device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers + device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers + device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0 + device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1 + device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode] + device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller + device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1 + device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2 + device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3 + device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode] + device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1 + device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5 + device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller + device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus + device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller + end +end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl new file mode 100644 index 0000000000..aca6c4d79b --- /dev/null +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include + + #include + + // Xeon-SP ACPI tables + Scope (\_SB) { + #include + } +} diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c new file mode 100644 index 0000000000..6962455813 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/fadt.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->reserved = 0; + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c new file mode 100644 index 0000000000..35a7faa99a --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ +} diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c new file mode 100644 index 0000000000..c95a69674d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "skxsp_tp_gpio.h" +#include "skxsp_tp_iio.h" + +/* +* Configure GPIO depend on platform +*/ +static void mainboard_config_gpios(FSPM_UPD *mupd) +{ + mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table; + mupd->FspmConfig.GpioConfig.NumberOfEntries = + sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG); +} + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = + (UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table; + mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = + ARRAY_SIZE(tp_iio_bifur_table); + + mupd->FspmConfig.IioPciConfig.ConfigurationTable = + (UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0; + mupd->FspmConfig.IioPciConfig.NumberOfEntries = + ARRAY_SIZE(tp_iio_pci_port_skt0); + + mupd->FspmConfig.PchPciConfig.PciPortConfig = + (UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0; + mupd->FspmConfig.PchPciConfig.NumberOfEntries = + ARRAY_SIZE(tp_pch_pci_port_skt0); + + mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; + mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mainboard_config_gpios(mupd); + mainboard_config_iio(mupd); +} diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h new file mode 100644 index 0000000000..5987caa883 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h @@ -0,0 +1,1019 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SKXSP_TP_GPIO_H_ +#define _SKXSP_TP_GPIO_H_ + +#include +#include + +/* + * OCP TiogaPass Gpio Pad Configuration + */ +static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = { + {GPIO_SKL_H_GPP_A0, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + {GPIO_SKL_H_GPP_A1, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_1_LAD_0_ESPI_IO_0 + {GPIO_SKL_H_GPP_A2, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_2_LAD_1_ESPI_IO_1 + {GPIO_SKL_H_GPP_A3, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_3_LAD_2_ESPI_IO_2 + {GPIO_SKL_H_GPP_A4, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_4_LAD_3_ESPI_IO_3 + {GPIO_SKL_H_GPP_A5, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_8_FM_LPC_CLKRUN_N + {GPIO_SKL_H_GPP_A9, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK + {GPIO_SKL_H_GPP_A10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_10_CLKOUT_LPC1 + {GPIO_SKL_H_GPP_A11, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_11_FM_LPC_PME_N + {GPIO_SKL_H_GPP_A12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N + {GPIO_SKL_H_GPP_A13, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK + {GPIO_SKL_H_GPP_A14, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_14_ESPI_RESET_N + {GPIO_SKL_H_GPP_A15, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_15_SUSACK_N + {GPIO_SKL_H_GPP_A16, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_16_CLKOUT_LPC2 + {GPIO_SKL_H_GPP_A17, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_17 + {GPIO_SKL_H_GPP_A18, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_18 + // {GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME + {GPIO_SKL_H_GPP_A20, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } },//GPP_A_20 + {GPIO_SKL_H_GPP_A21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_21 + {GPIO_SKL_H_GPP_A22, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_22 + {GPIO_SKL_H_GPP_A23, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_A_23 + + {GPIO_SKL_H_GPP_B0, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_0_CORE_VID_0 + {GPIO_SKL_H_GPP_B1, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_1_CORE_VID_1 + {GPIO_SKL_H_GPP_B2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_2_VRALERT_N + {GPIO_SKL_H_GPP_B3, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_3_CPU_GP2 + {GPIO_SKL_H_GPP_B4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_4_CPU_GP3 + {GPIO_SKL_H_GPP_B5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_5_SRCCLKREQ0_N + {GPIO_SKL_H_GPP_B6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_6_SRCCLKREQ1_N + {GPIO_SKL_H_GPP_B7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_7_SRCCLKREQ2_N + {GPIO_SKL_H_GPP_B8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_8_SRCCLKREQ3_N + {GPIO_SKL_H_GPP_B9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_9_SRCCLKREQ4_N + {GPIO_SKL_H_GPP_B10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_10_SRCCLKREQ5_N + {GPIO_SKL_H_GPP_B11, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_11 + {GPIO_SKL_H_GPP_B12, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_12_GLB_RST_WARN_N + {GPIO_SKL_H_GPP_B13, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_15 + {GPIO_SKL_H_GPP_B16, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_16 + {GPIO_SKL_H_GPP_B17, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_17 + {GPIO_SKL_H_GPP_B18, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_18 + {GPIO_SKL_H_GPP_B19, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_19 + {GPIO_SKL_H_GPP_B20, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_20 + {GPIO_SKL_H_GPP_B21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_21 + {GPIO_SKL_H_GPP_B22, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_22 + {GPIO_SKL_H_GPP_B23, { + GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N + +// {GPIO_SKL_H_GPP_C0, {} }, //GPP_C_0_SMBCLK, controlled by ME +// {GPIO_SKL_H_GPP_C1, {} }, //GPP_C_1_SMBDATA, controlled by ME + {GPIO_SKL_H_GPP_C2, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_2_SMBALERT_N +// {GPIO_SKL_H_GPP_C3, {} }, //GPP_C_3_SML0CLK_IE, controlled by ME +// {GPIO_SKL_H_GPP_C4, {} }, //GPP_C_4_SML0DATA_IE, controlled by ME + {GPIO_SKL_H_GPP_C5, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_5_SML0ALERT_IE_N +// {GPIO_SKL_H_GPP_C6, {} }, //GPP_C_6_SML1CLK_IE, controlled by ME +// {GPIO_SKL_H_GPP_C7, {} }, //GPP_C_7_SML1DATA_IE, controlled by ME + {GPIO_SKL_H_GPP_C8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_8 + {GPIO_SKL_H_GPP_C9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_9 + {GPIO_SKL_H_GPP_C10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_10 + {GPIO_SKL_H_GPP_C11, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_11 + {GPIO_SKL_H_GPP_C12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_12 + {GPIO_SKL_H_GPP_C13, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_13 + {GPIO_SKL_H_GPP_C14, { + GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, + GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_14 + {GPIO_SKL_H_GPP_C15, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_15 + {GPIO_SKL_H_GPP_C16, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_16 + {GPIO_SKL_H_GPP_C17, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_17 + {GPIO_SKL_H_GPP_C18, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_18 + {GPIO_SKL_H_GPP_C19, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_19 +// {GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME + {GPIO_SKL_H_GPP_C21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_21 + {GPIO_SKL_H_GPP_C22, { + GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, + GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_22 + {GPIO_SKL_H_GPP_C23, { + GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, + GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_C_23 + + {GPIO_SKL_H_GPP_D0, { + GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, + GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_0 + {GPIO_SKL_H_GPP_D1, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_1 + {GPIO_SKL_H_GPP_D2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_2 + {GPIO_SKL_H_GPP_D3, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_3 + {GPIO_SKL_H_GPP_D4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_4 + {GPIO_SKL_H_GPP_D5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_5 + {GPIO_SKL_H_GPP_D6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_6 + {GPIO_SKL_H_GPP_D7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_7 + {GPIO_SKL_H_GPP_D8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_8 + {GPIO_SKL_H_GPP_D9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_9_SSATA_DEVSLP3 + {GPIO_SKL_H_GPP_D10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_10_SSATA_DEVSLP4 + {GPIO_SKL_H_GPP_D11, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_11_SSATA_DEVSLP5 + {GPIO_SKL_H_GPP_D12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_12_SSATA_SDATAOUT1 + {GPIO_SKL_H_GPP_D13, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_13_SML0BLCK_IE + {GPIO_SKL_H_GPP_D14, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_14_SML0BDATA_IE + {GPIO_SKL_H_GPP_D15, { + GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_15_SSATA_SDATAOUT0 + {GPIO_SKL_H_GPP_D16, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_16_SML0BALERT_IE_N + {GPIO_SKL_H_GPP_D17, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_17 + {GPIO_SKL_H_GPP_D18, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_18 + {GPIO_SKL_H_GPP_D19, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock + } }, //GPP_D_19 + {GPIO_SKL_H_GPP_D20, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_20_TP_PCH_GPP_D_20 + {GPIO_SKL_H_GPP_D21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_21_IE_URAT_RX + {GPIO_SKL_H_GPP_D22, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_22_IE_URAT_TX + {GPIO_SKL_H_GPP_D23, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_D_23 + + {GPIO_SKL_H_GPP_E0, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_0_SATAXPCIE0_SATAGP0 + {GPIO_SKL_H_GPP_E1, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_1_SATAXPCIE1_SATAGP1 + {GPIO_SKL_H_GPP_E2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_2_SATAXPCIE2_SATAGP2 + {GPIO_SKL_H_GPP_E3, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_3_CPU_GP0 + {GPIO_SKL_H_GPP_E4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_4_SATA_DEVSLP0 + {GPIO_SKL_H_GPP_E5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_5_SATA_DEVSLP1 + {GPIO_SKL_H_GPP_E6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_6_SATA_DEVSLP2 + {GPIO_SKL_H_GPP_E7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_7_CPU_GP1 + {GPIO_SKL_H_GPP_E8, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_8_SATA_LED_N + {GPIO_SKL_H_GPP_E9, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_9_USB2_OC0_N + {GPIO_SKL_H_GPP_E10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_10_USB2_OC1_N + {GPIO_SKL_H_GPP_E11, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_11_USB2_OC2_N + {GPIO_SKL_H_GPP_E12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_E_12_USB2_OC3_N + + {GPIO_SKL_H_GPP_F0, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_0_SATAXPCIE3_SATAGP3 + {GPIO_SKL_H_GPP_F1, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_1_SATAXPCIE4_SATAGP4 + {GPIO_SKL_H_GPP_F2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_2_SATAXPCIE5_SATAGP5 + {GPIO_SKL_H_GPP_F3, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_3_SATAXPCIE6_SATAGP6 + {GPIO_SKL_H_GPP_F4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_4_SATAXPCIE7_SATAGP7 + {GPIO_SKL_H_GPP_F5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_5_SATA_DEVSLP3 + {GPIO_SKL_H_GPP_F6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_6_SATA_DEVSLP4 + {GPIO_SKL_H_GPP_F7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_7_SATA_DEVSLP5 + {GPIO_SKL_H_GPP_F8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_8_SATA_DEVSLP6 + {GPIO_SKL_H_GPP_F9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_9_SATA_DEVSLP7 + {GPIO_SKL_H_GPP_F10, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_10_SATA_SCLOCK + {GPIO_SKL_H_GPP_F11, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_11_SATA_SLOAD + {GPIO_SKL_H_GPP_F12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_12_SATA_SDATAOUT1 + {GPIO_SKL_H_GPP_F13, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_13_SATA_SDATAOUT0 + {GPIO_SKL_H_GPP_F14, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_14_SSATA_LED_N + {GPIO_SKL_H_GPP_F15, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_15_USB2_OC4_N + {GPIO_SKL_H_GPP_F16, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_16_USB2_OC5_N + {GPIO_SKL_H_GPP_F17, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_17_USB2_OC6_N + {GPIO_SKL_H_GPP_F18, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_18_USB2_OC7_N + {GPIO_SKL_H_GPP_F19, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_19_LAN_SMBCLK + {GPIO_SKL_H_GPP_F20, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_20_LAN_SMBDATA + {GPIO_SKL_H_GPP_F21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_21_LAN_SMBALERT_N + {GPIO_SKL_H_GPP_F22, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_22_SSATA_SCLOCK + {GPIO_SKL_H_GPP_F23, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_F_23_SSATA_SLOAD + + {GPIO_SKL_H_GPP_G0, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_0_FANTACH0_FANTACH0IE + {GPIO_SKL_H_GPP_G1, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_1_FANTACH1_FANTACH1IE + {GPIO_SKL_H_GPP_G2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_2_FANTACH2_FANTACH2IE + {GPIO_SKL_H_GPP_G3, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_3_FANTACH3_FANTACH3IE + {GPIO_SKL_H_GPP_G4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_4_FANTACH4_FANTACH4IE + {GPIO_SKL_H_GPP_G5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_5_FANTACH5_FANTACH5IE + {GPIO_SKL_H_GPP_G6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_6_FANTACH6_FANTACH6IE + {GPIO_SKL_H_GPP_G7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_7_FANTACH7_FANTACH7IE + {GPIO_SKL_H_GPP_G8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_8_FANPWM0_FANPWM0IE + {GPIO_SKL_H_GPP_G9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_9_FANPWM1_FANPWM1IE + {GPIO_SKL_H_GPP_G10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_10_FANPWM2_FANPWM2IE + {GPIO_SKL_H_GPP_G11, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_11_FANPWM3_FANPWM3IE + {GPIO_SKL_H_GPP_G12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_12 + {GPIO_SKL_H_GPP_G13, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_13 + {GPIO_SKL_H_GPP_G14, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_14 + {GPIO_SKL_H_GPP_G15, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_15 + {GPIO_SKL_H_GPP_G16, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_16 + {GPIO_SKL_H_GPP_G17, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_17_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_18_FM_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_19_FM_SMI_ACTIVE_N +// {GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME + {GPIO_SKL_H_GPP_G21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_21_SSATA_DEVSLP1 + {GPIO_SKL_H_GPP_G22, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_22_SSATA_DEVSLP2 + {GPIO_SKL_H_GPP_G23, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_G_23_SSATAXPCIE0_SSATAGP0 + + {GPIO_SKL_H_GPP_H0, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_0_SRCCLKREQ6_N + {GPIO_SKL_H_GPP_H1, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_1_SRCCLKREQ7_N + {GPIO_SKL_H_GPP_H2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_2_SRCCLKREQ8_N + {GPIO_SKL_H_GPP_H3, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_3_SRCCLKREQ9_N + {GPIO_SKL_H_GPP_H4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_4_SRCCLKREQ10_N +// {GPIO_SKL_H_GPP_H5, {} }, //GPP_H_5_SRCCLKREQ11_N + {GPIO_SKL_H_GPP_H6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_6_SRCCLKREQ12_N + {GPIO_SKL_H_GPP_H7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_7_SRCCLKREQ13_N + {GPIO_SKL_H_GPP_H8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_8_SRCCLKREQ14_N + {GPIO_SKL_H_GPP_H9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_9_SRCCLKREQ15_N +// {GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE +// {GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE + {GPIO_SKL_H_GPP_H12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_12_SML2ALERT_N_IE +// {GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE +// {GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE + {GPIO_SKL_H_GPP_H15, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_15_SML3ALERT_N_IE +// {GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE +// {GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE + {GPIO_SKL_H_GPP_H18, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_18_SML4ALERT_N_IE + {GPIO_SKL_H_GPP_H19, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_19_SSATAXPCIE1_SSATAGP1 + {GPIO_SKL_H_GPP_H20, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_20_SSATAXPCIE2_SSATAGP2 + {GPIO_SKL_H_GPP_H21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_21_SSATAXPCIE3_SSATAGP3 + {GPIO_SKL_H_GPP_H22, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_22_SSATAXPCIE4_SSATAGP4 + {GPIO_SKL_H_GPP_H23, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_H_23_SSATAXPCIE5_SSATAGP5 + + {GPIO_SKL_H_GPP_I0, { + GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_0_GBE_TDO + {GPIO_SKL_H_GPP_I1, { + GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_1_GBE_TCK + {GPIO_SKL_H_GPP_I2, { + GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_2_GBE_TMS + {GPIO_SKL_H_GPP_I3, { + GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_3_GBE_TDI + {GPIO_SKL_H_GPP_I4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_4_DO_RESET_IN_N + {GPIO_SKL_H_GPP_I5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_5_DO_RESET_OUT_N + {GPIO_SKL_H_GPP_I6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_6_RESET_DONE + {GPIO_SKL_H_GPP_I7, { + GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_7_JTAG_GBE_TRST_N + {GPIO_SKL_H_GPP_I8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_8_GBE_PCI_DIS + {GPIO_SKL_H_GPP_I9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_9_GBE_LAN_DIS + {GPIO_SKL_H_GPP_I10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_I_10 + + {GPIO_SKL_H_GPP_J0, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_0_LAN_LED_P0_0 + {GPIO_SKL_H_GPP_J1, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_1_LAN_LED_P0_1 + {GPIO_SKL_H_GPP_J2, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_2_LAN_LED_P1_0 + {GPIO_SKL_H_GPP_J3, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_3_LAN_LED_P1_1 + {GPIO_SKL_H_GPP_J4, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_4_LAN_LED_P2_0 + {GPIO_SKL_H_GPP_J5, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_5_LAN_LED_P2_1 + {GPIO_SKL_H_GPP_J6, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_6_LAN_LED_P3_0 + {GPIO_SKL_H_GPP_J7, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_7_LAN_LED_P3_1 + {GPIO_SKL_H_GPP_J8, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_8_LAN_I2C_SCL_MDC_P0 + {GPIO_SKL_H_GPP_J9, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0 + {GPIO_SKL_H_GPP_J10, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_10_LAN_I2C_SCL_MDC_P1 + {GPIO_SKL_H_GPP_J11, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1 + {GPIO_SKL_H_GPP_J12, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_12_LAN_I2C_SCL_MDC_P2 + {GPIO_SKL_H_GPP_J13, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2 + {GPIO_SKL_H_GPP_J14, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_14_LAN_I2C_SCL_MDC_P3 + {GPIO_SKL_H_GPP_J15, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3 + {GPIO_SKL_H_GPP_J16, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_16_LAN_SDP_P0_0 + {GPIO_SKL_H_GPP_J17, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_17_LAN_SDP_P0_1 + {GPIO_SKL_H_GPP_J18, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_18_LAN_SDP_P1_0 + {GPIO_SKL_H_GPP_J19, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_19_LAN_SDP_P1_1 + {GPIO_SKL_H_GPP_J20, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_20_LAN_SDP_P2_0 + {GPIO_SKL_H_GPP_J21, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_21_LAN_SDP_P2_1 + {GPIO_SKL_H_GPP_J22, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_22_LAN_SDP_P3_0 + {GPIO_SKL_H_GPP_J23, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_J_23_LAN_SDP_P3_1 + + {GPIO_SKL_H_GPP_K0, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_0_LAN_NCSI_CLK_IN + {GPIO_SKL_H_GPP_K1, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_1_LAN_NCSI_TXD0 + {GPIO_SKL_H_GPP_K2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_2_LAN_NCSI_TXD1 + {GPIO_SKL_H_GPP_K3, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_3_LAN_NCSI_TX_EN + {GPIO_SKL_H_GPP_K4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_4_LAN_NCSI_CRS_DV + {GPIO_SKL_H_GPP_K5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_5_LAN_NCSI_RXD0 + {GPIO_SKL_H_GPP_K6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_6_LAN_NCSI_RXD1 + {GPIO_SKL_H_GPP_K7, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_7 + {GPIO_SKL_H_GPP_K8, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_8_LAN_NCSI_ARB_IN + {GPIO_SKL_H_GPP_K9, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_9_LAN_NCSI_ARB_OUT + {GPIO_SKL_H_GPP_K10, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_K_10_PE_RST_N + + {GPIO_SKL_H_GPP_L2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_2_TESTCH0_D0 + {GPIO_SKL_H_GPP_L3, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_3_TESTCH0_D1 + {GPIO_SKL_H_GPP_L4, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_4_TESTCH0_D2 + {GPIO_SKL_H_GPP_L5, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_5_TESTCH0_D3 + {GPIO_SKL_H_GPP_L6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_6_TESTCH0_D4 + {GPIO_SKL_H_GPP_L7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_7_TESTCH0_D5 + {GPIO_SKL_H_GPP_L8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_8_TESTCH0_D6 + {GPIO_SKL_H_GPP_L9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_9_TESTCH0_D7 + {GPIO_SKL_H_GPP_L10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_10_TESTCH0_CLK + {GPIO_SKL_H_GPP_L11, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_11_TESTCH1_D0 + {GPIO_SKL_H_GPP_L12, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_12_TESTCH1_D1 + {GPIO_SKL_H_GPP_L13, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_13_TESTCH1_D2 + {GPIO_SKL_H_GPP_L14, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_14_TESTCH1_D3 + {GPIO_SKL_H_GPP_L15, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_15_TESTCH1_D4 + {GPIO_SKL_H_GPP_L16, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_16_TESTCH1_D5 + {GPIO_SKL_H_GPP_L17, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_17_TESTCH1_D6 + {GPIO_SKL_H_GPP_L18, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_18_TESTCH1_D7 + {GPIO_SKL_H_GPP_L19, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock + } }, //GPP_L_19_TESTCH1_CLK + + {GPIO_SKL_H_GPD0, {} }, //GPD_0, controlled by ME + {GPIO_SKL_H_GPD1, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_1_ACPRESENT + {GPIO_SKL_H_GPD2, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_2_GBE_WAKE_N + {GPIO_SKL_H_GPD3, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_3_PWRBTNB_N + {GPIO_SKL_H_GPD4, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_4_SLP_S3B + {GPIO_SKL_H_GPD5, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_5_SLP_S4B + {GPIO_SKL_H_GPD6, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_6_SLPA_N + {GPIO_SKL_H_GPD7, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_7 + {GPIO_SKL_H_GPD8, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD + {GPIO_SKL_H_GPD9, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_9 + {GPIO_SKL_H_GPD10, { + GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_10_FM_SLPS5_N + {GPIO_SKL_H_GPD11, { + GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutLow, + GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock + } }, //GPD_11_GBEPHY +}; + +#endif /* _SKXSP_TP_GPIO_H_ */ diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h new file mode 100644 index 0000000000..0ad92f2fd8 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SKXSP_TP_IIO_H_ +#define _SKXSP_TP_IIO_H_ + +#include +#include + +/* + * Standard Tioga Pass Iio Bifurcation Table + * This is SS 2x16 config. As documented in OCP TP spec, there are + * 3 configs. SS 2x16 is the most common. + * TODO: figure out config through board SKU ID and through PCIe + * config GPIO setting (SLT_CFG0 / SLT_CFG1). + */ +static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */ + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */ + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */ + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */ + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */ + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */ + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ +}; + +/* + * Standard Tioga Pass Iio PCIe Port Table + */ +static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { + // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | + // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | + // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | + // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | + // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride + { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, + { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, + 0x16, 0x00, 0x03 }, +}; + +/* + * Standard Tioga Pass PCH PCIe Port Table + */ +static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = { + //PortIndex ; ForceEnable ; PortLinkSpeed + { 0x00, 0x00, PcieAuto }, + { 0x04, 0x00, PcieAuto }, + { 0x05, 0x00, PcieAuto }, +}; + +#endif /* _SKXSP_TP_IIO_H_ */ From dbc958495d3b7c94046b3b8f826f9316ee528e48 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Thu, 5 Mar 2020 17:02:58 +0800 Subject: [PATCH 0299/1463] mb/google/kahlee/nuwani: Create Nuwani variant This commit creates a nuwani variant for Grunt. The initial settings override the baseboard was copied from variant treeya. BUG=b:144890301 TEST=emerge-grunt coreboot Signed-off-by: Peichao Wang Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39316 Reviewed-by: Martin Roth Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/Kconfig | 1 + src/mainboard/google/kahlee/Kconfig.name | 3 + .../kahlee/variants/nuwani/Makefile.inc | 20 ++ .../kahlee/variants/nuwani/devicetree.cb | 196 ++++++++++++++++++ .../nuwani/include/variant/acpi/gpe.asl | 16 ++ .../nuwani/include/variant/acpi/mainboard.asl | 17 ++ .../nuwani/include/variant/acpi/routing.asl | 16 ++ .../nuwani/include/variant/acpi/sleep.asl | 16 ++ .../nuwani/include/variant/acpi/thermal.asl | 16 ++ .../variants/nuwani/include/variant/ec.h | 25 +++ .../variants/nuwani/include/variant/gpio.h | 19 ++ .../variants/nuwani/include/variant/thermal.h | 38 ++++ .../google/kahlee/variants/nuwani/mainboard.c | 126 +++++++++++ .../kahlee/variants/nuwani/spd/Makefile.inc | 34 +++ 14 files changed, 543 insertions(+) create mode 100644 src/mainboard/google/kahlee/variants/nuwani/Makefile.inc create mode 100644 src/mainboard/google/kahlee/variants/nuwani/devicetree.cb create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h create mode 100644 src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h create mode 100644 src/mainboard/google/kahlee/variants/nuwani/mainboard.c create mode 100644 src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 7d98d89f13..b46c1f6d83 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -66,6 +66,7 @@ config VARIANT_DIR default "careena" if BOARD_GOOGLE_CAREENA default "grunt" if BOARD_GOOGLE_GRUNT default "liara" if BOARD_GOOGLE_LIARA + default "nuwani" if BOARD_GOOGLE_NUWANI default "treeya" if BOARD_GOOGLE_TREEYA config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index 03d7baa1b4..d040f31df5 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -12,6 +12,9 @@ config BOARD_GOOGLE_GRUNT config BOARD_GOOGLE_LIARA bool "-> Liara" select BOARD_GOOGLE_BASEBOARD_KAHLEE +config BOARD_GOOGLE_NUWANI + bool "-> Nuwani" + select BOARD_GOOGLE_BASEBOARD_KAHLEE config BOARD_GOOGLE_TREEYA bool "-> Treeya" select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc new file mode 100644 index 0000000000..3753268749 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2020 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += ./spd + +romstage-y += ../baseboard/romstage.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb new file mode 100644 index 0000000000..6c953b1af4 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -0,0 +1,196 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "16 * MiB" + register "stapm_percent" = "80" + register "stapm_time_ms" = "2000000" + register "stapm_power_mw" = "7800" + register "lvds_poseq_varybl_to_blon" = "0x5" + register "lvds_poseq_blon_to_varybl" = "0x5" + + # Enable I2C0 for audio, USB3 hub at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 3, + }" + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + .data_hold_time_ns = 400, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 16, + .fall_time_ns = 8, + }" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU (Disabled for performance and battery) + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # + device pci 2.2 on end # + device pci 2.3 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # + device pci 2.5 on end # + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 off end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SMbus + end # SMbus + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain + device mmio 0xfedc2000 on + chip drivers/generic/adau7002 + device generic 0.0 on end + end + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" + device i2c 1a on end + end + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + end + device mmio 0xfedc3000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device mmio 0xfedc5000 on + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl new file mode 100644 index 0000000000..7a1e74b2d9 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..acb906e0bc --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl new file mode 100644 index 0000000000..283e332849 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..b69f063bbd --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..56a4da466b --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h new file mode 100644 index 0000000000..4a63722e9e --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h new file mode 100644 index 0000000000..ebd7c5be5a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* EC sync irq is AGPIO 10 */ +#define EC_SYNC_IRQ 10 diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h new file mode 100644 index 0000000000..1bb78efa2a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Stoney Ridge Thermal Requirements 12 (6W) + * TDP (W) 6 + * T die,max (°C) 95 + * T ctl,max 85 + * T die,lmt (default) 90 + * T ctl,lmt (default) 80 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 94 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 85 + +#endif diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c new file mode 100644 index 0000000000..42dbe031f6 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uint32_t sku_id(void) +{ + static int sku = -1; + + if (sku == -1) + sku = google_chromeec_get_sku_id(); + + return sku; +} + +uint8_t variant_board_sku(void) +{ + return sku_id(); +} + +void variant_mainboard_suspend_resume(void) +{ + /* Enable backlight - GPIO 133 active low */ + gpio_set(GPIO_133, 0); +} + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); + + /* Tune VIH */ + pci_write_config32(dev, BH720_PROTECT, + BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF); + bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL); + bh720_pcr_data &= 0xFFFFFF00; + /* CLK = 3 and DAT = 2 */ + bh720_pcr_data |= 0x35; + pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data); + pci_write_config32(dev, BH720_PROTECT, + BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); +} + + +const char *smbios_mainboard_manufacturer(void) +{ + static char oem_bin_data[11]; + static const char *manuf; + + if (!CONFIG(USE_OEM_BIN)) + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + if (manuf) + return manuf; + + if (cbfs_boot_load_file("oem.bin", oem_bin_data, + sizeof(oem_bin_data) - 1, + CBFS_TYPE_RAW)) + manuf = &oem_bin_data[0]; + else + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + return manuf; +} diff --git a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc new file mode 100644 index 0000000000..a2d0d2fc9f --- /dev/null +++ b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 +SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 +SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 +SPD_SOURCES += micron-MT40A1G16KNR-075-E # 0b0011 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0100 +SPD_SOURCES += samsung-K4AAG165WB-MCRC # 0b0101 +SPD_SOURCES += micron-MT40A512M16LY-075-E # 0b0110 +SPD_SOURCES += hynix-H5ANAG6NCMR-VKC # 0b0111 +SPD_SOURCES += hynix-H5AN8G6NCJR-VKC # 0b1000 +SPD_SOURCES += samsung-K4A8G165WC-BCTD # 0b1001 +SPD_SOURCES += samsung-K4AAG165WB-MCTD # 0b1010 +SPD_SOURCES += micron-MT40A512M16TB-062E-J # 0b1011 +SPD_SOURCES += samsung-K4A8G165WC-BCWE # 0b1100 +SPD_SOURCES += hynix-H5AN8G6NCJR-XNC # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 From 8488853fab0417b222ae04924574bd6f2221ca0e Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 5 Mar 2020 00:54:02 -0800 Subject: [PATCH 0300/1463] soc/intel/tigerlake: Enable CNVi Mode Add configs to enable CNVi mode and CNViBtCore. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39317 Reviewed-by: Nick Vaccaro Reviewed-by: caveh jalali Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 4 ++++ src/soc/intel/tigerlake/fsp_params_tgl.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e57abe857b..a6bcf0847f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -208,6 +208,10 @@ struct soc_intel_tigerlake_config { /* Enable Pch iSCLK */ uint8_t pch_isclk; + /* CNVi */ + uint8_t CnviMode; + uint8_t CnviBtCore; + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { FORCE_DISABLE, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 9e22b58e7c..0dae0fed47 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -149,6 +149,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->PchLanEnable = dev->enabled; + /* CNVi */ + params->CnviMode = config->CnviMode; + params->CnviBtCore = config->CnviBtCore; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; From 8247cc3328aef91b4e39b68957acc3dcaebce125 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 19 Dec 2019 17:09:01 +0100 Subject: [PATCH 0301/1463] northbridge: Remove unused include Change-Id: I942457a820a59428f7ae302262c4891a4c5ef1a6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37520 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/acpi.c | 1 - src/northbridge/intel/gm45/northbridge.c | 1 - src/northbridge/intel/haswell/acpi.c | 1 - src/northbridge/intel/i945/acpi.c | 1 - src/northbridge/intel/nehalem/acpi.c | 1 - src/northbridge/intel/nehalem/smi.c | 1 - src/northbridge/intel/pineview/acpi.c | 1 - src/northbridge/intel/pineview/early_init.c | 1 - src/northbridge/intel/pineview/northbridge.c | 1 - src/northbridge/intel/sandybridge/acpi.c | 1 - src/northbridge/intel/sandybridge/common.c | 1 - src/northbridge/intel/x4x/acpi.c | 1 - src/northbridge/intel/x4x/northbridge.c | 1 - 13 files changed, 13 deletions(-) diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 82b622113a..6035b7ecf5 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 5ccafbb876..dd5a7e2a88 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index d92e858d53..a9b687b883 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "haswell.h" #include diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 3a9f6a2b2f..66f26dd9c5 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "i945.h" diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 462cdc07fa..43b13c286a 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -20,7 +20,6 @@ #include #include -#include #include #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 8c19852043..c3433a39e7 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -15,7 +15,6 @@ #include #include -#include #include #include "nehalem.h" diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 9dd8e311be..2e12305e0b 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 8f925f71d7..daf425e4a4 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4193498b50..0b9de19e97 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4afb54646d..9665972545 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "sandybridge.h" #include diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index 8bfd476961..d141c998df 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "sandybridge.h" enum platform_type get_platform_type(void) diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index a91d227c7a..d25eb2b026 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "x4x.h" unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ef34a2eb2d..0e28f56400 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include From d3b4de7bea6aafa351a60aa8070af577fe2705eb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 2 Mar 2020 01:48:56 +0100 Subject: [PATCH 0302/1463] drivers/broadcom: Add ASPM blacklist The Broadcom BCM5751 NIC on a PCIe card will make the computer hang if ASPM gets enabled. Blacklist it. Change-Id: I2cf8d56e9139928a6acfd1d09e47a96b9554fb06 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/broadcom/Makefile.inc | 14 +++++++ src/drivers/broadcom/bcm57xx_aspm_disable.c | 43 +++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 src/drivers/broadcom/Makefile.inc create mode 100644 src/drivers/broadcom/bcm57xx_aspm_disable.c diff --git a/src/drivers/broadcom/Makefile.inc b/src/drivers/broadcom/Makefile.inc new file mode 100644 index 0000000000..88433d291f --- /dev/null +++ b/src/drivers/broadcom/Makefile.inc @@ -0,0 +1,14 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_PCIEXP_ASPM) += bcm57xx_aspm_disable.c diff --git a/src/drivers/broadcom/bcm57xx_aspm_disable.c b/src/drivers/broadcom/bcm57xx_aspm_disable.c new file mode 100644 index 0000000000..427ba623a2 --- /dev/null +++ b/src/drivers/broadcom/bcm57xx_aspm_disable.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static void bcm57xx_disable_aspm(struct device *const dev) +{ + printk(BIOS_INFO, "bcm57xx: Disabling ASPM for %s [%04x/%04x]\n", + dev_path(dev), dev->vendor, dev->device); + + dev->disable_pcie_aspm = 1; +} + +static struct device_operations bcm57xx_aspm_fixup_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = bcm57xx_disable_aspm, +}; + +static const unsigned short pci_device_ids[] = { + 0x1677, /* BCM5751 */ + 0, +}; + +static const struct pci_driver bcm57xx_aspm_fixup __pci_driver = { + .ops = &bcm57xx_aspm_fixup_ops, + .vendor = PCI_VENDOR_ID_BROADCOM, + .devices = pci_device_ids, +}; From 447e33965671450b385b5bec70e5febc10ec9186 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 5 Mar 2020 00:32:02 +0100 Subject: [PATCH 0303/1463] util/autoport: Remove redundant comment Nobody needs "LPC bridge PCI-LPC bridge". Change-Id: Iac833d4fa34b00d89bdfc9aeb06a96583840b900 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39298 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- util/autoport/bd82x6x.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 3ad212b343..87e7584743 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -277,7 +277,7 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { } PutPCIChip(addr, cur) - PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + PutPCIDevParent(addr, "", "lpc") DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/common/acpi/platform.asl", From 69dd524993a2f7ab2e31149934b4af7da582c93a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 4 Mar 2020 12:05:34 +0100 Subject: [PATCH 0304/1463] util/scripts/gerrit-rebase: Improve error message I received feedback that people were confused by "Error: foo", so replace it with something more user friendly that serves the same purpose. Change-Id: I17b902a62020109e079437c8d9ffd7ea5979a3a1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39274 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/scripts/gerrit-rebase | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/scripts/gerrit-rebase b/util/scripts/gerrit-rebase index 276142d6b9..d051103b60 100755 --- a/util/scripts/gerrit-rebase +++ b/util/scripts/gerrit-rebase @@ -71,7 +71,7 @@ to_matches="$(git log ${common_base}..${to} | \ cut -d: -f2-)" # start rebase process, but fail immediately by enforcing an invalid todo -GIT_SEQUENCE_EDITOR="echo foo >" \ +GIT_SEQUENCE_EDITOR="echo Ignore this error, it's intentional>" \ git rebase -i --onto ${to} ${from} ${to} 2>/dev/null # write new rebase todo From fd2d4730c66386e99e5beaa853055a5e92088dab Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 6 Mar 2020 18:10:02 +0100 Subject: [PATCH 0305/1463] lib/spd_bin: Fix grammar mistake in a comment Change-Id: I0a9ec0f9605282cbf4fd0ac05070278a3331b6fa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39361 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/lib/spd_bin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 9e625b5228..25eb552748 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -55,7 +55,7 @@ static int spd_get_banks(const uint8_t spd[], int dram_type) static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; switch (dram_type) { - /* DDR3 and LPDDR3 has the same bank definition */ + /* DDR3 and LPDDR3 have the same bank definition */ case SPD_DRAM_DDR3: case SPD_DRAM_LPDDR3_INTEL: case SPD_DRAM_LPDDR3_JEDEC: From 6e61c5ec00ebfac6c7e695e9eedd53a421e75894 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 4 Mar 2020 18:32:37 +0100 Subject: [PATCH 0306/1463] soc/intel/braswell: Generate microcode binaries from tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Automatically add microcode binaries from intel-microcode 3rdparty respository for Braswell processors using Makefile. Signed-off-by: Michał Żygowski Change-Id: Iec57e4d5cd63b9bccc869bf178053f1c99b81b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39320 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier --- src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/braswell/Makefile.inc | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5b6a9237e7..a437db2580 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER select NO_FIXED_XIP_ROM_SIZE diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index d2626e865e..5923e39a30 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -68,6 +68,8 @@ CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)) CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-4c-*) + ifneq ($(CONFIG_VGA_BIOS_FILE),) #we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE))) From cf4ede85f9df3134d1c0adb7504b299355ec42a4 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 3 Mar 2020 17:32:48 -0800 Subject: [PATCH 0307/1463] mb/intel/tglrvp: Add fixed SKUID to SMBIOS tables Report fixed SKUID (255) to support mosys. BUG=none BRANCH=none TEST=boot tigerlake rvp board and check mosys and SKUID from smbios Signed-off-by: Wonkyu Kim Change-Id: I7a5beed307fd7880a6af127b2dcd06e93e50547d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39269 Reviewed-by: Paul Menzel Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/mainboard.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index d74c11c8ca..9af9d42911 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -18,6 +18,16 @@ #include #include #include +#include + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; /* sku{0..255} */ + uint32_t sku_id = 255; + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} static void mainboard_init(void *chip_info) { From ffcf641cc4cb9fc5b8a49599d001fbe180dea6fa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 5 Mar 2020 01:30:49 +0100 Subject: [PATCH 0308/1463] mb/asus/p8z77-v_lx2: Add new mainboard This is an ATX mainboard with a LGA1155 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Working: - All four DIMM slots - Serial port to emit spam - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - HDMI and VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - Both PCI ports behind the ASM1083 PCI bridge - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - SeaBIOS to boot Arch Linux Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39299 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel --- src/mainboard/asus/p8z77-v_lx2/Kconfig | 44 ++++ src/mainboard/asus/p8z77-v_lx2/Kconfig.name | 2 + src/mainboard/asus/p8z77-v_lx2/Makefile.inc | 7 + src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl | 0 .../asus/p8z77-v_lx2/acpi/platform.asl | 21 ++ .../asus/p8z77-v_lx2/acpi/superio.asl | 1 + src/mainboard/asus/p8z77-v_lx2/acpi_tables.c | 21 ++ src/mainboard/asus/p8z77-v_lx2/board_info.txt | 7 + src/mainboard/asus/p8z77-v_lx2/data.vbt | Bin 0 -> 7168 bytes src/mainboard/asus/p8z77-v_lx2/devicetree.cb | 112 +++++++++ src/mainboard/asus/p8z77-v_lx2/dsdt.asl | 40 ++++ src/mainboard/asus/p8z77-v_lx2/early_init.c | 73 ++++++ .../asus/p8z77-v_lx2/gma-mainboard.ads | 28 +++ src/mainboard/asus/p8z77-v_lx2/gpio.c | 222 ++++++++++++++++++ src/mainboard/asus/p8z77-v_lx2/hda_verb.c | 49 ++++ 15 files changed, 627 insertions(+) create mode 100644 src/mainboard/asus/p8z77-v_lx2/Kconfig create mode 100644 src/mainboard/asus/p8z77-v_lx2/Kconfig.name create mode 100644 src/mainboard/asus/p8z77-v_lx2/Makefile.inc create mode 100644 src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl create mode 100644 src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl create mode 100644 src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl create mode 100644 src/mainboard/asus/p8z77-v_lx2/acpi_tables.c create mode 100644 src/mainboard/asus/p8z77-v_lx2/board_info.txt create mode 100644 src/mainboard/asus/p8z77-v_lx2/data.vbt create mode 100644 src/mainboard/asus/p8z77-v_lx2/devicetree.cb create mode 100644 src/mainboard/asus/p8z77-v_lx2/dsdt.asl create mode 100644 src/mainboard/asus/p8z77-v_lx2/early_init.c create mode 100644 src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads create mode 100644 src/mainboard/asus/p8z77-v_lx2/gpio.c create mode 100644 src/mainboard/asus/p8z77-v_lx2/hda_verb.c diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig new file mode 100644 index 0000000000..2041ce9f56 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Angel Pons +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_V_LX2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select REALTEK_8168_RESET + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default asus/p8z77-v_lx2 + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-V LX2" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig.name b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name new file mode 100644 index 0000000000..0dec75f4a7 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8Z77_V_LX2 + bool "P8Z77-V LX2" diff --git a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc new file mode 100644 index 0000000000..7167e10123 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl new file mode 100644 index 0000000000..b967f584c4 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl new file mode 100644 index 0000000000..f2b35ba9c1 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c new file mode 100644 index 0000000000..7f695721e0 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8z77-v_lx2/board_info.txt b/src/mainboard/asus/p8z77-v_lx2/board_info.txt new file mode 100644 index 0000000000..79c36d6837 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/uk/Motherboards/P8Z77V_LX2/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8z77-v_lx2/data.vbt b/src/mainboard/asus/p8z77-v_lx2/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..f8151e1678f06acf4abe554a52f40c53d0a59014 GIT binary patch literal 7168 zcmeHKUu+!Z5&wO=dv|+#yLan#N-l?EO+tXPYsc%uvVt+{-q{X50&h=){_5HFyJ2Wqtyig=(^pVEp4l)mslB~($a^X;wO z5;w`wDgvaN)$Gj9&Nusgzi(!Cci&uLmS!djJ;k{~_o2x`aeRczaPf|PJD;~xp*T5n zcsM_sKU^4}9J-TU$8|Vue{~Tk3$ep;nTp3wRF<;S9W=9eto+!Km80bcDm}$VLyby9 zMatiIUuCJXvUs9WrkS}r@+8ArM&abqr7}&NeCSAJWq@QX_NLyx{kQZH^}0R1xt^Tc z+e?(|9q8*H$n{yq@W{~Qp;B=?KUB-Szp*TA-Y#G5) zh8|viY~|JDz8OrgPZH?KQJ)p6^0Lvj*XY5XXobczQ=#^sh_Q7@a6kFsbI-c z2uVOvxR{EyW7J6D88wUFs0!Xy4`5N-z^|h&K8dDLW6s3Va10wa8aiC&+n9IjIu>;Y z$C;mI{w4EUx`DTu&oTdw`H#$hVg4KQ-;hj8G;*dAVJ>)LyH_ zV)&}|A!AX~Z`S7|{i!bnHj*n}1HhwSbpiZ^g z_gzc;7JGbNL|AJi*CQg!yQSPBpSAyVP$DZ=cGw!ZsazUi)4nDDe+RP_W87C%eQ>QU z2zwV$d)8913L_bZ*c-hYPei+s`Z+k&uNlQ7-zc=b#{E|I7Z1?6voiXcY>`5T@c0%8 z@cEVo-2<_a;IYm_JP04$>NOpj2Tg%40=M86JL?KO0Z*6y>>w?{gW?>VpcBXkdGJWa zZ{cT$5?8H#NDg#;8_n>&M4&ze*Q&+xo)Z`l$9sEW7)-iiC*kN<=fa zp2mf=Y5MPKdyD*j`Z{IPP;mU~w(zRsMW|+iatUWRVN4|GM8bI{VN?_JcEZ_67#}6* zi-cpC#txGPOlRCQ=1h9rbe=bjGbX)fI_FK}&nCfg9Ls34s9-s>mT|8|YnJnpWvpBD zf#v+kGX83jo^&!vV_%ZSlFmIz^E1s? zE(pJcQ=Jn^Uokl$<`pxLp9`C1By}^tcef+SIT+?8sq@O!Bdn(gz4L99^>@@UY41O! zFkVb1r?7hU2-}NF)<(S!_TDsX- zgzaT7BLv^HrWZZiz#O)>3E2gL?q$wJ8bR{@J#%kPq1`=L4fi6=NLGUu&r@jxhsXC< z*B3JFo=ahazB0K1>FQ2`EBXr7907r;a4XK&yk+lZ$;pL9?^HXbk z-O{gi%27cC6$z;^l8r=gJH3sCwX&O@3UVNf5Ojh6H79u$s{C`3SskGUR&g +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1043 0x84ca inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIEX16_1 + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on end # xHCI + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) + device pci 1c.1 off end # RP #2: + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: RTL8111 GbE NIC + device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge + device pci 1c.6 on end # RP #7: PCIEX1_1 + device pci 1c.7 on end # RP #8: PCIEX1_2 + + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR Wake-up + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 off end # Port 80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl new file mode 100644 index 0000000000..f164b332d0 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c new file mode 100644 index 0000000000..c86dab7666 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/early_init.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads new file mode 100644 index 0000000000..37135f9174 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI3, + Analog, + Others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-v_lx2/gpio.c b/src/mainboard/asus/p8z77-v_lx2/gpio.c new file mode 100644 index 0000000000..634fb2e560 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/gpio.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio28 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c new file mode 100644 index 0000000000..01bea72258 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438445), + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; From 11bf9df9ac73449d3291e927771abbbbcd4af145 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 5 Dec 2019 00:12:38 +0100 Subject: [PATCH 0309/1463] mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant Took less than 30 minutes, and booted on the first try :) Working: - Native raminit, using two 2GB DDR3-1333 DIMMs - S3 suspend/resume - USB ports and headers - EHCI Debug with an FT2232H - Gigabit Ethernet - Integrated DVI/VGA outputs (libgfxinit) - PCIe x16 for a graphics card - PCIe x1 ports - PS/2 port with a keyboard - SATA controller - Audio outputs, both front and rear - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio inputs - Non-Linux OSes - ACPI thermal zone and OS-independent fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash! Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37483 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig | 7 +- .../gigabyte/ga-h61m-s2pv/Kconfig.name | 5 + .../variants/ga-h61m-ds2v/devicetree.cb | 96 +++++++++ .../ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c | 203 ++++++++++++++++++ .../variants/ga-h61m-ds2v/hda_verb.c | 42 ++++ 5 files changed, 350 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb create mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c create mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 62c422aa53..18982c8675 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V +if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V config BOARD_SPECIFIC_OPTIONS def_bool y @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT - select NO_UART_ON_SUPERIO if BOARD_GIGABYTE_GA_H61MA_D3V config MAINBOARD_DIR string @@ -39,11 +38,13 @@ config MAINBOARD_DIR config VARIANT_DIR string default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV + default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V config MAINBOARD_PART_NUMBER string default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV + default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V config DEVICETREE @@ -62,4 +63,4 @@ config USBDEBUG_HCD_INDEX # Bottom left port seen from rear int default 2 -endif # BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V +endif # BOARD_GIGABYTE_GA_H61M* diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name index 83b5803d5f..15d107d8e5 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name @@ -1,5 +1,10 @@ config BOARD_GIGABYTE_GA_H61M_S2PV bool "GA-H61M-S2PV" +config BOARD_GIGABYTE_GA_H61M_DS2V + bool "GA-H61M-DS2V" + select NO_UART_ON_SUPERIO + config BOARD_GIGABYTE_GA_H61MA_D3V bool "GA-H61MA-D3V" + select NO_UART_ON_SUPERIO diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb new file mode 100644 index 0000000000..2cc5b19651 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb @@ -0,0 +1,96 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Angel Pons +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3) + device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #4: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #5: PCIe x1 Port (PCIEX1_2) + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + end + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x73 = 0x00 + irq 0xc1 = 0x37 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x42 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c new file mode 100644 index 0000000000..89bc4d6a86 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c new file mode 100644 index 0000000000..1379b1ac94 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; From 7fa1d9de5c1d8275f49493a39f16b08179f179cb Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Thu, 5 Mar 2020 19:21:56 +0800 Subject: [PATCH 0310/1463] chromeos: stop sharing write protect GPIO with depthcharge wpsw_boot is deprecated in favour of wpsw_cur. As such, coreboot no longer needs to share "write protect" GPIO with depthcharge. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c Signed-off-by: Joel Kitching Cq-Depend: chromium:2088434 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318 Reviewed-by: Furquan Shaikh Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/chromeos.c | 2 -- src/mainboard/google/beltino/chromeos.c | 2 -- src/mainboard/google/butterfly/chromeos.c | 4 ---- src/mainboard/google/cheza/chromeos.c | 2 -- src/mainboard/google/cyan/chromeos.c | 1 - src/mainboard/google/daisy/chromeos.c | 4 ---- src/mainboard/google/dedede/chromeos.c | 1 - src/mainboard/google/dragonegg/chromeos.c | 1 - src/mainboard/google/drallion/chromeos.c | 2 -- src/mainboard/google/eve/chromeos.c | 1 - src/mainboard/google/fizz/chromeos.c | 1 - src/mainboard/google/foster/chromeos.c | 3 --- src/mainboard/google/gale/chromeos.c | 2 -- src/mainboard/google/glados/chromeos.c | 1 - src/mainboard/google/gru/chromeos.c | 2 -- src/mainboard/google/hatch/chromeos.c | 1 - src/mainboard/google/jecht/chromeos.c | 2 -- src/mainboard/google/kahlee/chromeos.c | 1 - src/mainboard/google/kukui/chromeos.c | 2 -- src/mainboard/google/link/chromeos.c | 3 --- src/mainboard/google/nyan/chromeos.c | 2 -- src/mainboard/google/nyan_big/chromeos.c | 2 -- src/mainboard/google/nyan_blaze/chromeos.c | 2 -- src/mainboard/google/oak/chromeos.c | 2 -- src/mainboard/google/octopus/chromeos.c | 1 - src/mainboard/google/parrot/chromeos.c | 3 --- src/mainboard/google/peach_pit/chromeos.c | 4 ---- src/mainboard/google/poppy/chromeos.c | 1 - src/mainboard/google/rambi/chromeos.c | 1 - src/mainboard/google/reef/chromeos.c | 1 - src/mainboard/google/sarien/chromeos.c | 2 -- src/mainboard/google/slippy/chromeos.c | 1 - src/mainboard/google/smaug/chromeos.c | 2 -- src/mainboard/google/storm/chromeos.c | 2 -- src/mainboard/google/stout/chromeos.c | 3 --- src/mainboard/google/trogdor/chromeos.c | 2 -- src/mainboard/google/veyron/chromeos.c | 2 -- src/mainboard/google/veyron_mickey/chromeos.c | 2 -- src/mainboard/google/veyron_rialto/chromeos.c | 2 -- src/mainboard/google/volteer/chromeos.c | 1 - src/mainboard/intel/baskingridge/chromeos.c | 3 --- src/mainboard/intel/cannonlake_rvp/chromeos.c | 1 - src/mainboard/intel/coffeelake_rvp/chromeos.c | 1 - src/mainboard/intel/emeraldlake2/chromeos.c | 3 --- src/mainboard/intel/glkrvp/chromeos.c | 1 - src/mainboard/intel/icelake_rvp/chromeos.c | 1 - src/mainboard/intel/jasperlake_rvp/chromeos.c | 1 - src/mainboard/intel/kblrvp/chromeos.c | 1 - src/mainboard/intel/kunimitsu/chromeos.c | 1 - src/mainboard/intel/strago/chromeos.c | 1 - src/mainboard/intel/tglrvp/chromeos.c | 1 - src/mainboard/intel/wtm2/chromeos.c | 1 - src/mainboard/samsung/lumpy/chromeos.c | 4 ---- src/mainboard/samsung/stumpy/chromeos.c | 4 ---- 54 files changed, 100 deletions(-) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index c82e37d635..a3174b5a48 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -23,8 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {CROS_WP_GPIO, ACTIVE_HIGH, get_write_protect_state(), - "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 8940d360e3..cbe3c727ae 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -30,8 +30,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_SPI_WP, ACTIVE_HIGH, - get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, {-1, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 63e582e48f..10b461864c 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -31,10 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO active Low */ - {WP_GPIO, ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, - /* lid switch value from EC */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index e84061352e..6f713fe08a 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -38,8 +38,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) "EC in RW"}, {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), "EC interrupt"}, - {GPIO_WP_STATE.addr, ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, }; diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 154b913c4c..9b3b5c01e9 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -32,7 +32,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 3525a9813e..e24d8b1138 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -24,10 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - /* Write Protect: active low (WP_GPIO) */ - {EXYNOS5_GPD1, ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, - /* Lid: active high (LID_GPIO) */ {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"}, diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index dc24f5ff81..c2729a1e9d 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -15,7 +15,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 3b69bff47d..2982a2095b 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 00571ed6bc..c584bcbb4f 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -34,8 +34,6 @@ enum rec_mode_state { void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), - "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 9a1dd04f9c..8b40dddeb2 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 25c52a596b..c57fa7e45b 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, 1, "lid"}, /* Lid switch always open */ {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index e14fbcb791..dc7b738a87 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -24,9 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { /* TBD(twarren@nvidia.com): Any analogs for these on Foster-FFD? */ struct lb_gpio chromeos_gpios[] = { - /* Write Protect: active low */ - {-1, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* TODO: Power: active low / high depending on board id */ {GPIO(X5), ACTIVE_LOW, -1, "power"}, diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index d0bdbb0940..5c5a20c74a 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -68,8 +68,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {PP_SW, ACTIVE_LOW, read_gpio(PP_SW), "presence"}, - {get_wp_status_gpio_pin(), ACTIVE_LOW, - !get_write_protect_state(), "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, {-1, ACTIVE_LOW, 0, "lid"}, }; diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index c89a9a8371..5b340db9c5 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index c92a492310..05930dd148 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -32,8 +32,6 @@ int get_write_protect_state(void) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, wp_polarity, - get_write_protect_state() ^ !wp_polarity, "write protect"}, #if CONFIG(GRU_BASEBOARD_SCARLET) {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, #endif diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 4119670ef4..151977cd33 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index e8a9d1abd1..b16e325b38 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -31,8 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_SPI_WP, ACTIVE_HIGH, - get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, {-1, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 195eb94378..3be023edfc 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 2cef10e82b..b001c81d8c 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -33,8 +33,6 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.id, ACTIVE_LOW, - !get_write_protect_state(), "write protect"}, {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 44a2bf5c1c..f7f39de6c8 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -22,9 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO57 = PCH_SPI_WP_D */ - {57, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - /* Lid: the "switch" comes from the EC */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index e3e09e6dbd..710c9e1381 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -20,8 +20,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 1fbaac7234..697b7b1e44 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -20,8 +20,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO(R1), ACTIVE_LOW, - !get_write_protect_state(), "write protect"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index bbb274fb90..697b7b1e44 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -20,8 +20,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index b613cc3a85..c0b25718d2 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -34,8 +34,6 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {WRITE_PROTECT.id, ACTIVE_LOW, - !get_write_protect_state(), "write protect"}, {LID.id, ACTIVE_HIGH, -1, "lid"}, {POWER_BUTTON.id, ACTIVE_HIGH, -1, "power"}, {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index ca9f6fbeb2..795dcb1718 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index ae8da676b3..d60bd5381e 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -31,9 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO70 active high */ - {70, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Lid switch GPIO active high (open). */ {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index f2b1e8ce8b..c229ed6732 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -24,10 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - /* Write Protect: active low (WP_GPIO) */ - {EXYNOS5_GPX3, ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, - /* Lid: active high (LID_GPIO) */ {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X34), "lid"}, diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 23e575d8da..34aad93060 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 3472b1c4b4..ebced06030 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 4dbbe6d581..681008df30 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index bdd414c77c..9077d86679 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -32,8 +32,6 @@ enum rec_mode_state { void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), - "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 772b5a874b..a3245de6cd 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {58, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 3d36cd9dc0..8f76f11b58 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -21,8 +21,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {WRITE_PROTECT_L, ACTIVE_LOW, - !get_write_protect_state(), "write protect"}, {POWER_BUTTON, ACTIVE_LOW, -1, "power"}, {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, {AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"}, diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 9587c3c384..744572e35a 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -40,8 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {DEV_SW, ACTIVE_LOW, read_gpio(REC_SW), "presence"}, - {WP_SW, ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, {-1, ACTIVE_LOW, 0, "lid"}, }; diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index fbb81907ce..482de98555 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -28,9 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO7 */ - {7, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Lid Switch: Virtual switch */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index e84061352e..6f713fe08a 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -38,8 +38,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) "EC in RW"}, {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), "EC interrupt"}, - {GPIO_WP_STATE.addr, ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, }; diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index d27b4dd3d5..e1e232bc08 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -40,8 +40,6 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, ACTIVE_LOW, !get_write_protect_state(), - "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, {GPIO_LID.raw, ACTIVE_HIGH, -1, "lid"}, diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index c549e70b51..79ca8ef76a 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -31,8 +31,6 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, ACTIVE_LOW, - !get_write_protect_state(), "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 65866f3cec..21c741f588 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -36,8 +36,6 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, ACTIVE_LOW, - !get_write_protect_state(), "write protect"}, /* Note for early development, we want to support both servo * and pushkey recovery buttons in firmware boot stages. */ {GPIO_RECOVERY_PUSHKEY.raw, ACTIVE_LOW, diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index eca7e20652..2bcb4ec60a 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -15,7 +15,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index cf89f0da1e..72886d2439 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -23,9 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO22 */ - {0, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 0440994f5a..6815193ff5 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index e7094d71e9..55669bb1a9 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 4b52a2c794..ebf51e3c8e 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -23,9 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO48 */ - {48, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: GPIO22 */ {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 4edd4a0ab4..1cf35801a8 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index da3f1d442d..be1e2914e7 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 372f6cefa2..930f7488b6 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 647a4302b2..d7b98377f2 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 3f3dd409c3..ffdfa37faa 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 540ba6a349..654906f60f 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 372f6cefa2..930f7488b6 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 95664f1d42..d64d9ef552 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, 1, "lid"}, // force open {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 342f7a968a..5b58144fa3 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -38,10 +38,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) u8 lid = ec_read(0x83); struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO24 = KBC3_SPI_WP# */ - {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), - "write protect"}, - /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 955ba5a620..36efb8af64 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -33,10 +33,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); struct lb_gpio chromeos_gpios[] = { - /* Write Protect: GPIO68 = CHP3_SPI_WP */ - {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), - "write protect"}, - /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, From 9a2021c09b7acb0203c8cf6e9f66817840ce3643 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Thu, 5 Mar 2020 19:24:11 +0800 Subject: [PATCH 0311/1463] chromeos: remove unused constants from gnvs.h These constants are not used in coreboot. They can still be found in: depthcharge: src/vboot/util/acpi.h vboot_reference: host/arch/x86/lib/crossystem_arch.c. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I40ad35235c87662a6bcbe6320974a626c6db059e Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/39319 Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/vendorcode/google/chromeos/gnvs.h | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index b114dd0d68..811a3f4994 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -18,26 +18,6 @@ #include -#define BOOT_REASON_OTHER 0 -#define BOOT_REASON_S3DIAG 9 - -#define CHSW_RECOVERY_X86 (1 << 1) -#define CHSW_RECOVERY_EC (1 << 2) -#define CHSW_DEVELOPER_SWITCH (1 << 5) -#define CHSW_FIRMWARE_WP_DIS (1 << 9) - -#define ACTIVE_MAINFW_RECOVERY 0 -#define ACTIVE_MAINFW_RW_A 1 -#define ACTIVE_MAINFW_RW_B 2 - -#define ACTIVE_MAINFW_TYPE_RECOVERY 0 -#define ACTIVE_MAINFW_TYPE_NORMAL 1 -#define ACTIVE_MAINFW_TYPE_DEVELOPER 2 - -#define RECOVERY_REASON_NONE 0 -#define RECOVERY_REASON_ME 1 -// TODO(reinauer) other recovery reasons? - #define ACTIVE_ECFW_RO 0 #define ACTIVE_ECFW_RW 1 From 8034813581ad310d567408f050dfa76d5b29144f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 5 Mar 2020 21:34:43 +0100 Subject: [PATCH 0312/1463] soc/intel/common/block/smm: add Kconfig for TCO SMI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow the user to select if TCO shall issue SMIs or not. Change-Id: Id22777e9573376e5a079a375400caa687bc41afb Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39326 Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/smm/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index ab5ee03a6d..77ba00c027 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -15,6 +15,12 @@ config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE Disable eSPI SMI source to prevent the embedded controller from asserting SMI while in firmware. +config SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE + bool "Enable TCO SMI" + default n + help + Enable TCO SMI source to e.g. handle case instrusion. + config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS int default 100 if CHROMEOS From 7f9ceef51be785781ea4c0035c31d718d590a2fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 3 Mar 2020 20:15:02 +0100 Subject: [PATCH 0313/1463] intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/include/soc/pm.h | 4 ++-- src/soc/intel/cannonlake/include/soc/pm.h | 2 +- src/soc/intel/common/block/smm/smm.c | 5 ++++- src/soc/intel/icelake/include/soc/pm.h | 2 +- src/soc/intel/skylake/include/soc/pm.h | 2 +- src/soc/intel/tigerlake/include/soc/pm.h | 2 +- 6 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 0cf06b2a60..510dd03da7 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -78,7 +78,7 @@ #endif #define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */ #define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */ -#define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */ +#define TCO_SMI_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */ #define GPIO_EN (1 << SMI_GPIO) /* Enable GPIO SMI */ #define BIOS_RLS (1 << SMI_BIOS_RLS) /* asserts SCI on bit set */ /* start software smi timer on bit set */ @@ -99,7 +99,7 @@ * - on eSPI events (does nothing on LPC systems) * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events + * - on TCO events, unless enabled in common code */ #define ENABLE_SMI_PARAMS \ (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN) diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 356f0bcc6f..77109651f0 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -128,7 +128,7 @@ * - on eSPI events (does nothing on LPC systems) * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events + * - on TCO events, unless enabled in common code */ #define ENABLE_SMI_PARAMS \ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index bef923ac1a..ecea473645 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -63,13 +63,16 @@ void smm_southbridge_enable(uint16_t pm1_events) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * - on eSPI events, unless disabled (does nothing on LPC systems) + * - on TCO events (TIMEOUT, case intrusion, ...), if enabled * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE)) smi_params &= ~ESPI_SMI_EN; + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)) + smi_params |= TCO_SMI_EN; + /* Enable SMI generation: */ pmc_enable_smi(smi_params); } diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 34c32a9ac2..5bdefc9e4a 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -126,8 +126,8 @@ * - on writes to GBL_RLS (bios commands) * - on eSPI events (does nothing on LPC systems) * No SMIs: + * - on TCO events, unless enabled in common code * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ #define ENABLE_SMI_PARAMS \ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 007d29cadc..faad1efa05 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -142,8 +142,8 @@ * - on writes to GBL_RLS (bios commands) * - on eSPI events (does nothing on LPC systems) * No SMIs: + * - on TCO events, unless enabled in common code * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ #define ENABLE_SMI_PARAMS \ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index d2f47e271b..588dfba7ba 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -132,8 +132,8 @@ * - on writes to GBL_RLS (bios commands) * - on eSPI events (does nothing on LPC systems) * No SMIs: + * - on TCO events, unless enabled in common code * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ #define ENABLE_SMI_PARAMS \ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) From c96f802f7f126dadc41c95a8b63e9dec85cbbfde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 3 Mar 2020 20:31:58 +0100 Subject: [PATCH 0314/1463] intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/apollolake/include/soc/smbus.h | 5 +++++ src/soc/intel/cannonlake/include/soc/smbus.h | 5 +++++ src/soc/intel/icelake/include/soc/smbus.h | 5 +++++ src/soc/intel/skylake/include/soc/smbus.h | 7 ++++++- src/soc/intel/tigerlake/include/soc/smbus.h | 5 +++++ 5 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 4b252d61a9..965e8bc264 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -21,8 +21,13 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) #endif diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index 54d0d6cfbf..60d155783e 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -24,9 +24,14 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) /* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index 9d8fe46b64..2277ca914e 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -21,9 +21,14 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) /* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index ee257ea613..216e864dbc 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -23,10 +23,15 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO 0x02 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) /* SMBus I/O bits. */ #define SMBUS_SLAVE_ADDR 0x24 diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h index 50ea044e53..0ad565a613 100644 --- a/src/soc/intel/tigerlake/include/soc/smbus.h +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -29,9 +29,14 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) /* * Default slave address value for PCH. This value is set to match default From 4ed2598c67847c6bea629fff59d6fb8643371e57 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Thu, 6 Feb 2020 14:51:27 +0100 Subject: [PATCH 0315/1463] mb/lenovo/*/devicetree: Declare device in one line if possible Change-Id: I708281f7861110e4abc02948c74affad9fa37053 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38732 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/t400/devicetree.cb | 3 +-- src/mainboard/lenovo/t440p/devicetree.cb | 3 +-- src/mainboard/lenovo/t60/devicetree.cb | 10 +++------- src/mainboard/lenovo/thinkcentre_a58/devicetree.cb | 3 +-- src/mainboard/lenovo/x200/devicetree.cb | 3 +-- src/mainboard/lenovo/x201/devicetree.cb | 3 +-- src/mainboard/lenovo/x60/devicetree.cb | 9 +++------ 7 files changed, 11 insertions(+), 23 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 0eea193a13..a61d84eba6 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -152,8 +152,7 @@ chip northbridge/intel/gm45 end chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index b63767e808..1022e7764e 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -73,8 +73,7 @@ chip northbridge/intel/haswell chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy end chip ec/lenovo/h8 register "beepmask0" = "0x00" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index ada50f39ce..702902bb22 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -127,9 +127,7 @@ chip northbridge/intel/i945 device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -182,8 +180,7 @@ chip northbridge/intel/i945 end chip superio/nsc/pc87384 - device pnp 2e.0 off #FDC - end + device pnp 2e.0 off end #FDC device pnp 2e.1 on # Parallel Port io 0x60 = 0x3bc @@ -204,8 +201,7 @@ chip northbridge/intel/i945 io 0x60 = 0x1620 end - device pnp 2e.a off # WDT - end + device pnp 2e.a off end # WDT end end device pci 1f.2 on # SATA diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index 5559f7dcfd..aedbf0ca83 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -51,8 +51,7 @@ chip northbridge/intel/x4x # Northbridge device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 device pci 1c.1 on # PCIe 2: NIC - device pci 00.0 on - end + device pci 00.0 on end end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 3c4e094f35..818eda208d 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -142,8 +142,7 @@ chip northbridge/intel/gm45 end chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" end diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 3ababc9e9c..7f1f55a25b 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -127,8 +127,7 @@ chip northbridge/intel/nehalem end chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 1a914fd009..4b56e93ab7 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -111,8 +111,7 @@ chip northbridge/intel/i945 device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -172,8 +171,7 @@ chip northbridge/intel/i945 end chip superio/nsc/pc87392 - device pnp 2e.0 off #FDC - end + device pnp 2e.0 off end #FDC device pnp 2e.1 on # Parallel Port io 0x60 = 0x3bc @@ -194,8 +192,7 @@ chip northbridge/intel/i945 io 0x60 = 0x1620 end - device pnp 2e.a off # WDT - end + device pnp 2e.a off end # WDT end end device pci 1f.1 on # IDE From dd3604422f5ca4672dc2919805a09c74e732066c Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Thu, 5 Mar 2020 18:16:48 -0800 Subject: [PATCH 0316/1463] mb/google/volteer: add samsung-K4UBE3D4AA-MGCR SPD Add samsung K4UBE3D4AA-MGCR SPD as memory sku id 1. BUG=b:148182234 BRANCH=none TEST=none Change-Id: Ie00c45de4d31856109cda13051a75cfa2c2548f7 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39336 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- .../spd/samsung-K4UBE3D4AA-MGCR.spd.hex | 32 +++++++++++++++++++ .../volteer/variants/volteer/Makefile.inc | 1 + 2 files changed, 33 insertions(+) create mode 100644 src/mainboard/google/volteer/spd/samsung-K4UBE3D4AA-MGCR.spd.hex diff --git a/src/mainboard/google/volteer/spd/samsung-K4UBE3D4AA-MGCR.spd.hex b/src/mainboard/google/volteer/spd/samsung-K4UBE3D4AA-MGCR.spd.hex new file mode 100644 index 0000000000..945b2e8e06 --- /dev/null +++ b/src/mainboard/google/volteer/spd/samsung-K4UBE3D4AA-MGCR.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index 37893c21c6..a6659db315 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -8,3 +8,4 @@ ## Memory Options SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000 +SPD_SOURCES += samsung-K4UBE3D4AA-MGCR # 0b0001 From 34944be317657e29a4bcba82f7f52f12ed90a327 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 2 Mar 2020 22:18:26 -0800 Subject: [PATCH 0317/1463] mb/intel/tglrvp: Update display ports for RVP Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229 Reviewed-by: Shaunak Saha Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 1 + src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e61690ea41..5888db0474 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -52,6 +52,7 @@ chip soc/intel/tigerlake # enabling EDP in PortA register "DdiPortAConfig" = "1" + register "DdiPortBHpd" = "1" register "DdiPort1Hpd" = "1" register "DdiPort1Ddc" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 46ed5a20a9..073926ace5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -61,7 +61,6 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /*Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ @@ -83,6 +82,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + /* DP */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ }; const struct pad_config *variant_gpio_table(size_t *num) From 94b032ee5e38948a88ccfc288b3ebe11c8cf984d Mon Sep 17 00:00:00 2001 From: dnojiri Date: Thu, 5 Mar 2020 10:59:32 -0800 Subject: [PATCH 0318/1463] Update vboot submodule to upstream master Updating from commit id 8b9732f5: 2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was meant to be) to commit id 5059062d: 2020-03-05 02:40:39 (EFS: Implement EFS2 and NO_BOOT mode) This brings in 19 new commits. Change-Id: Ic33500921e2c1a6109c24ad36713b41ab6e43de9 Signed-off-by: dnojiri Reviewed-on: https://review.coreboot.org/c/coreboot/+/39324 Reviewed-by: Julius Werner Reviewed-by: Joel Kitching Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 8b9732f5fc..5059062dd3 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 8b9732f5fcccc1c568e821f144b7ccd94708b45d +Subproject commit 5059062dd352e3864fb68f8a061e87bd7055d12a From 58cf6030f54035148e9f6bf5e2ba60892cfd54da Mon Sep 17 00:00:00 2001 From: dnojiri Date: Tue, 28 Jan 2020 12:34:20 -0800 Subject: [PATCH 0319/1463] vboot: Upgrade kernel space to v1.0 This patch upgrades the kernel space to v1.0 to accommodate EC hash, which is used for CrOS EC's early firmware selection. BUG=chromium:1045217 BRANCH=none TEST=Boot Helios. Verify software sync works. Cq-Depend: chromium:2041695 Change-Id: I525f1551afd1853cae826e87198057410167b239 Signed-off-by: dnojiri Reviewed-on: https://review.coreboot.org/c/coreboot/+/39137 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching Reviewed-by: Julius Werner --- src/security/vboot/secdata_tpm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 96fac29fcf..0ae956276c 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -91,7 +91,7 @@ static uint32_t write_secdata(uint32_t index, const uint8_t *secdata, uint32_t len) { - uint8_t sd[32]; + uint8_t sd[MAX(VB2_SECDATA_KERNEL_SIZE, VB2_SECDATA_FIRMWARE_SIZE)]; uint32_t rv; int attempts = 3; @@ -214,6 +214,8 @@ static uint32_t set_rec_hash_space(const uint8_t *data) static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { + vb2api_secdata_kernel_create(ctx); + RETURN_ON_FAILURE(tlcl_force_clear()); /* @@ -296,6 +298,8 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) TPM_PERMANENT_FLAGS pflags; uint32_t result; + vb2api_secdata_kernel_create_v0(ctx); + result = tlcl_get_permanent_flags(&pflags); if (result != TPM_SUCCESS) return result; @@ -329,10 +333,10 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) /* Define and write secdata_kernel space. */ RETURN_ON_FAILURE(safe_define_space(KERNEL_NV_INDEX, TPM_NV_PER_PPWRITE, - VB2_SECDATA_KERNEL_SIZE)); + VB2_SECDATA_KERNEL_SIZE_V02)); RETURN_ON_FAILURE(write_secdata(KERNEL_NV_INDEX, ctx->secdata_kernel, - VB2_SECDATA_KERNEL_SIZE)); + VB2_SECDATA_KERNEL_SIZE_V02)); /* Define and write secdata_firmware space. */ RETURN_ON_FAILURE(safe_define_space(FIRMWARE_NV_INDEX, @@ -376,9 +380,11 @@ static uint32_t factory_initialize_tpm(struct vb2_context *ctx) { uint32_t result; - /* Set initial values of secdata_firmware and secdata_kernel spaces. */ + /* + * Set initial values of secdata_firmware space. + * kernel space is created in _factory_initialize_tpm(). + */ vb2api_secdata_firmware_create(ctx); - vb2api_secdata_kernel_create(ctx); VBDEBUG("TPM: factory initialization\n"); From 97fe371b9f1f1050ebc2edf87508ced79aa87b46 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 3 Mar 2020 10:48:25 -0800 Subject: [PATCH 0320/1463] soc/intel/tigerlake: Avoid NULL pointer dereference Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference if dev did not point to the audio device. BUG=CID 1420208 TEST=Built image successfully. Change-Id: I2a62da44c7044f9dc281eae0949f7f7b612ab238 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/39261 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/romstage/fsp_params_jsl.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 56124f4c04..9c70f2ece1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -95,7 +95,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->DdiPortCDdc = config->DdiPortCDdc; /* Audio */ - m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0; + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; From 7fc6847dd66b5a78feae51169f3fe3fd8ae1c673 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 3 Mar 2020 10:11:15 +0100 Subject: [PATCH 0321/1463] drivers/usb: Use 'print("%s...", __func__)' Change-Id: Id90496ba54d861157343302c2600adf3b4ccd811 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39230 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/usb/ehci_debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 97b39f46a0..364f8c7772 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -91,7 +91,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) } while (++loop < DBGP_MICROFRAME_TIMEOUT_LOOPS); if (! (ctrl & DBGP_DONE)) { - dprintk(BIOS_ERR, "dbgp_wait_until_complete: retry timeout.\n"); + dprintk(BIOS_ERR, "%s: retry timeout.\n", __func__); return -DBGP_ERR_SIGNAL; } From 682b1668861671dce51db92e5fe14a14250c5921 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 3 Mar 2020 10:21:37 +0100 Subject: [PATCH 0322/1463] mb: Use 'print("%s...", __func__)' Change-Id: I4fa89dc1ad4196a61bb0cdfaa0d59dfe4c6fff12 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39231 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/amd/bettong/irq_tables.c | 2 +- src/mainboard/amd/db-ft3b-lc/irq_tables.c | 2 +- src/mainboard/amd/gardenia/irq_tables.c | 2 +- src/mainboard/amd/inagua/irq_tables.c | 2 +- src/mainboard/amd/lamar/irq_tables.c | 2 +- src/mainboard/amd/olivehill/irq_tables.c | 2 +- src/mainboard/amd/olivehillplus/irq_tables.c | 2 +- src/mainboard/amd/parmer/irq_tables.c | 2 +- src/mainboard/amd/persimmon/irq_tables.c | 2 +- src/mainboard/amd/south_station/irq_tables.c | 2 +- src/mainboard/amd/thatcher/irq_tables.c | 2 +- src/mainboard/amd/union_station/irq_tables.c | 2 +- src/mainboard/asrock/e350m1/irq_tables.c | 2 +- src/mainboard/asrock/imb-a180/irq_tables.c | 2 +- src/mainboard/asus/f2a85-m/irq_tables.c | 2 +- src/mainboard/bap/ode_e20XX/irq_tables.c | 2 +- src/mainboard/bap/ode_e21XX/irq_tables.c | 2 +- src/mainboard/biostar/a68n_5200/irq_tables.c | 2 +- src/mainboard/elmex/pcm205400/irq_tables.c | 2 +- src/mainboard/gizmosphere/gizmo/irq_tables.c | 2 +- src/mainboard/gizmosphere/gizmo2/irq_tables.c | 2 +- src/mainboard/hp/abm/irq_tables.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 2 +- src/mainboard/lenovo/g505s/irq_tables.c | 2 +- src/mainboard/lippert/frontrunner-af/irq_tables.c | 2 +- src/mainboard/lippert/toucan-af/irq_tables.c | 2 +- src/mainboard/msi/ms7721/irq_tables.c | 2 +- src/mainboard/pcengines/apu1/irq_tables.c | 2 +- src/mainboard/pcengines/apu2/irq_tables.c | 2 +- 30 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/bettong/irq_tables.c b/src/mainboard/amd/bettong/irq_tables.c index 45030994ba..7334bb2fd8 100644 --- a/src/mainboard/amd/bettong/irq_tables.c +++ b/src/mainboard/amd/bettong/irq_tables.c @@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/db-ft3b-lc/irq_tables.c b/src/mainboard/amd/db-ft3b-lc/irq_tables.c index 530c132a05..465b3643d4 100644 --- a/src/mainboard/amd/db-ft3b-lc/irq_tables.c +++ b/src/mainboard/amd/db-ft3b-lc/irq_tables.c @@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c index 2aefaea7ba..76e796a647 100644 --- a/src/mainboard/amd/gardenia/irq_tables.c +++ b/src/mainboard/amd/gardenia/irq_tables.c @@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) if (sum != pirq->checksum) pirq->checksum = sum; - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/amd/lamar/irq_tables.c b/src/mainboard/amd/lamar/irq_tables.c index 9cc27f78ca..fc3fbec2d4 100644 --- a/src/mainboard/amd/lamar/irq_tables.c +++ b/src/mainboard/amd/lamar/irq_tables.c @@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 181908a8ad..d8bf5e9806 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/olivehillplus/irq_tables.c b/src/mainboard/amd/olivehillplus/irq_tables.c index 530c132a05..465b3643d4 100644 --- a/src/mainboard/amd/olivehillplus/irq_tables.c +++ b/src/mainboard/amd/olivehillplus/irq_tables.c @@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 181908a8ad..d8bf5e9806 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 181908a8ad..d8bf5e9806 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index 181908a8ad..d8bf5e9806 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index 88d2160000..e0d5ad4641 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c index 181908a8ad..d8bf5e9806 100644 --- a/src/mainboard/bap/ode_e20XX/irq_tables.c +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/bap/ode_e21XX/irq_tables.c b/src/mainboard/bap/ode_e21XX/irq_tables.c index 413ccf8718..5eb5a49c6e 100644 --- a/src/mainboard/bap/ode_e21XX/irq_tables.c +++ b/src/mainboard/bap/ode_e21XX/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/biostar/a68n_5200/irq_tables.c b/src/mainboard/biostar/a68n_5200/irq_tables.c index ab26cbac1f..e19e698bbe 100644 --- a/src/mainboard/biostar/a68n_5200/irq_tables.c +++ b/src/mainboard/biostar/a68n_5200/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index d1149968aa..d83286e1e0 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -103,7 +103,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index 9d74dc8942..01a3411144 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -97,7 +97,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/gizmosphere/gizmo2/irq_tables.c b/src/mainboard/gizmosphere/gizmo2/irq_tables.c index 181908a8ad..d8bf5e9806 100644 --- a/src/mainboard/gizmosphere/gizmo2/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index 181908a8ad..d8bf5e9806 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c index 761bc04dc4..fb04069628 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index d33b5b8cce..bec87cba31 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c index 761bc04dc4..fb04069628 100644 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ b/src/mainboard/lenovo/g505s/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/msi/ms7721/irq_tables.c b/src/mainboard/msi/ms7721/irq_tables.c index 88d2160000..e0d5ad4641 100644 --- a/src/mainboard/msi/ms7721/irq_tables.c +++ b/src/mainboard/msi/ms7721/irq_tables.c @@ -95,7 +95,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c index 1d1e81f05e..3ce0ffcaa8 100644 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ b/src/mainboard/pcengines/apu1/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c index 3d6346e3c0..5f2045d8f4 100644 --- a/src/mainboard/pcengines/apu2/irq_tables.c +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -96,7 +96,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; } From 3cd4327ad97c47b4684861bfd8d1551ca3c6e7eb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Mar 2020 22:01:17 +0100 Subject: [PATCH 0323/1463] src/nb: Use 'print("%s...", __func__)' Change-Id: I7dd6dd8e8debe1b6419625fca38670be375ef581 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39328 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/haswell/raminit.c | 3 +-- src/northbridge/intel/i945/gma.c | 4 ++-- src/northbridge/intel/i945/raminit.c | 6 +++--- src/northbridge/intel/i945/rcven.c | 17 ++++++++--------- src/northbridge/intel/sandybridge/raminit_mrc.c | 2 +- 5 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833858..9615cb08f6 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -133,8 +133,7 @@ void sdram_initialize(struct pei_data *pei_data) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { post_code(POST_RESUME_FAILURE); - printk(BIOS_DEBUG, "Giving up in sdram_initialize: " - "No MRC data\n"); + printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); system_reset(); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 98e30e7d07..05855f3f13 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -88,9 +88,9 @@ static int gtt_setup(u8 *mmiobase) /* verify */ if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + printk(BIOS_DEBUG, "%s is enabled.\n", __func__); } else { - printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); + printk(BIOS_DEBUG, "%s failed!!!\n", __func__); return 1; } write32(mmiobase + GFX_FLSH_CNTL, 0); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f0ea142c5d..cb3b943171 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -111,7 +111,7 @@ static int memclk(void) case 2: return 533; case 3: return 667; default: - printk(BIOS_DEBUG, "memclk: unknown register value %x\n", + printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); } return -1; @@ -125,7 +125,7 @@ static u16 fsbclk(void) case 1: return 533; case 3: return 667; default: - printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", + printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, MCHBAR32(CLKCFG) & 7); } return 0xffff; @@ -135,7 +135,7 @@ static u16 fsbclk(void) case 1: return 533; case 2: return 800; default: - printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", + printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, MCHBAR32(CLKCFG) & 7); } return 0xffff; diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 5a90807543..2768a61773 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -64,7 +64,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) { u32 reg32; - printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse); + printk(BIOS_SPEW, " %s() medium=0x%x, coarse=0x%x\n", __func__, medium, coarse); reg32 = MCHBAR32(C0DRT1 + channel_offset); reg32 &= 0xf0ffffff; @@ -73,7 +73,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) /* This should never happen: */ if (coarse > 0x0f) - printk(BIOS_DEBUG, "set_receive_enable: coarse overflow: 0x%02x.\n", coarse); + printk(BIOS_DEBUG, "%s: coarse overflow: 0x%02x.\n", __func__, coarse); /* medium control * @@ -99,7 +99,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine) { - printk(BIOS_SPEW, " normalize()\n"); + printk(BIOS_SPEW, " %s()\n", __func__); if (*fine < 0x80) return 0; @@ -126,7 +126,7 @@ static int find_preamble(int channel_offset, u8 *mediumcoarse, /* find start of the data phase */ u32 reg32; - printk(BIOS_SPEW, " find_preamble()\n"); + printk(BIOS_SPEW, " %s()\n", __func__); do { if (*mediumcoarse < 4) { @@ -156,7 +156,7 @@ static int find_preamble(int channel_offset, u8 *mediumcoarse, static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine) { - printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n", + printk(BIOS_SPEW, " %s() mediumcoarse=%02x fine=%02x\n", __func__, *mediumcoarse, *fine); if (*fine >= 0x80) { *fine -= 0x80; @@ -183,7 +183,7 @@ static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine, { u32 rcvenmt; - printk(BIOS_SPEW, " find_strobes_low()\n"); + printk(BIOS_SPEW, " %s()\n", __func__); for (;;) { MCHBAR8(C0WL0REOST + channel_offset) = *fine; @@ -219,7 +219,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine, int counter; u32 rcvenmt; - printk(BIOS_SPEW, " find_strobes_edge()\n"); + printk(BIOS_SPEW, " %s()\n", __func__); counter = 8; set_receive_enable(channel_offset, *mediumcoarse & 3, @@ -283,8 +283,7 @@ static int receive_enable_autoconfig(int channel_offset, u8 mediumcoarse; u8 fine; - printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n", - channel_offset ? 1 : 0); + printk(BIOS_SPEW, "%s() for channel %d\n", __func__, channel_offset ? 1 : 0); /* Set initial values */ mediumcoarse = (sysinfo->cas << 2) | 3; diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 8daa9aaad1..db5bffcb11 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -212,7 +212,7 @@ void sdram_initialize(struct pei_data *pei_data) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { - printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); + printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); system_reset(); } From a3eb3df01c9f1ed6fc0bd3ef341a01981d4e7479 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 27 Nov 2019 16:21:46 +0100 Subject: [PATCH 0324/1463] cpu/x86/smm: Add smm_size to relocatable smmstub To mitigate against sinkhole in software which is required on pre-sandybridge hardware, the smm entry point needs to check if the LAPIC base is between smbase and smbase + smmsize. The size needs to be available early so add them to the relocatable module parameters. When the smmstub is used to relocate SMM the default SMM size 0x10000 is provided. On the permanent handler the size provided by get_smm_info() is used. Change-Id: I0df6e51bcba284350f1c849ef3d012860757544b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37288 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/x86/smm/smm_module_loader.c | 11 +++++++---- src/cpu/x86/smm/smm_stub.S | 2 ++ src/include/cpu/x86/smm.h | 1 + 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 856ca7876b..30f115f121 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -174,8 +174,9 @@ static void smm_stub_place_staggered_entry_points(char *base, * concurrent areas requested. The save state always lives at the top of SMRAM * space, and the entry point is at offset 0x8000. */ -static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params, - void *fxsave_area) +static int smm_module_setup_stub(void *smbase, size_t smm_size, + struct smm_loader_params *params, + void *fxsave_area) { size_t total_save_state_size; size_t smm_stub_size; @@ -269,6 +270,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params, stub_params->fxsave_area = (uintptr_t)fxsave_area; stub_params->fxsave_area_size = FXSAVE_SIZE; stub_params->runtime.smbase = (uintptr_t)smbase; + stub_params->runtime.smm_size = smm_size; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; stub_params->runtime.num_cpus = params->num_concurrent_stacks; @@ -309,7 +311,8 @@ int smm_setup_relocation_handler(struct smm_loader_params *params) if (params->num_concurrent_stacks == 0) params->num_concurrent_stacks = CONFIG_MAX_CPUS; - return smm_module_setup_stub(smram, params, fxsave_area_relocation); + return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, + params, fxsave_area_relocation); } /* The SMM module is placed within the provided region in the following @@ -409,5 +412,5 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) params->handler = rmodule_entry(&smm_mod); params->handler_arg = rmodule_parameters(&smm_mod); - return smm_module_setup_stub(smram, params, fxsave_area); + return smm_module_setup_stub(smram, size, params, fxsave_area); } diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 8207d233a0..aa4022389f 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -42,6 +42,8 @@ fxsave_area_size: smm_runtime: smbase: .long 0 +smm_size: +.long 0 save_state_size: .long 0 num_cpus: diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9efe2e04eb..26496eebac 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -63,6 +63,7 @@ extern unsigned char _binary_smm_end[]; struct smm_runtime { u32 smbase; + u32 smm_size; u32 save_state_size; u32 num_cpus; /* STM's 32bit entry into SMI handler */ From a317353f4283bf51f28482c69b0e52d1c4511be8 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 28 Feb 2020 23:31:05 -0800 Subject: [PATCH 0325/1463] mb/intel/tglrvp: Add pin mux for Camera Add additional pin mux for I2C3, I2C5 for Camera. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs. BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera Simple test method to check camera: capture image by below commands from OS console >media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]" >media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]" >yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10 $(media-ctl -e "Intel IPU6 CSI2 BE capture") Signed-off-by: Wonkyu Kim Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39201 Reviewed-by: Paul Menzel Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 073926ace5..30d148a6de 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -24,6 +24,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* Camera */ + PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ PAD_CFG_GPO(GPP_B23, 0, PLTRST), PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_R6, 0, PLTRST), From d0ee87032a589d477eb70f45f60b26fbb6cf53a2 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 6 Mar 2020 21:18:30 +0800 Subject: [PATCH 0326/1463] lib/spd_bin: Extend LPDDR4 SPD information Follow JEDEC 21-C to extend LPDDR4 SPD information. Signed-off-by: Eric Lai Change-Id: I68c9782c543afab4423296fa7ac1c078db5649c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39352 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/include/spd_bin.h | 3 +-- src/lib/spd_bin.c | 8 +++++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index f144b1461c..c78f7c3267 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -28,6 +28,7 @@ #define SPD_DRAM_LPDDR3_INTEL 0xF1 #define SPD_DRAM_LPDDR3_JEDEC 0x0F #define SPD_DRAM_DDR4 0x0C +#define SPD_DRAM_LPDDR4 0x10 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define DDR3_ORGANIZATION 7 @@ -40,8 +41,6 @@ #define LPDDR3_SPD_PART_LEN 18 #define DDR4_SPD_PART_OFF 329 #define DDR4_SPD_PART_LEN 20 -#define LPDDR4_SPD_PART_OFF 329 -#define LPDDR4_SPD_PART_LEN 20 struct spd_block { u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 25eb552748..4bf77d2baf 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -45,6 +45,8 @@ static const char *spd_get_module_type_string(int dram_type) return "LPDDR3"; case SPD_DRAM_DDR4: return "DDR4"; + case SPD_DRAM_LPDDR4: + return "LPDDR4"; } return "UNKNOWN"; } @@ -62,7 +64,9 @@ static int spd_get_banks(const uint8_t spd[], int dram_type) if (index >= ARRAY_SIZE(ddr3_banks)) return -1; return ddr3_banks[index]; + /* DDR4 and LPDDR4 has the same bank definition */ case SPD_DRAM_DDR4: + case SPD_DRAM_LPDDR4: if (index >= ARRAY_SIZE(ddr4_banks)) return -1; return ddr4_banks[index]; @@ -73,7 +77,8 @@ static int spd_get_banks(const uint8_t spd[], int dram_type) static int spd_get_capmb(const uint8_t spd[]) { - static const int spd_capmb[10] = { 1, 2, 4, 8, 16, 32, 64, 128, 48, 96 }; + static const int spd_capmb[13] = { 1, 2, 4, 8, 16, 32, 64, + 128, 48, 96, 12, 24, 72 }; int index = spd[SPD_DENSITY_BANKS] & 0xf; if (index >= ARRAY_SIZE(spd_capmb)) return -1; @@ -145,6 +150,7 @@ static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) spd_name[LPDDR3_SPD_PART_LEN] = 0; break; case SPD_DRAM_DDR4: + case SPD_DRAM_LPDDR4: memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); spd_name[DDR4_SPD_PART_LEN] = 0; break; From 3d676f147ec4ade7539648980eecf5a03219d275 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 6 Mar 2020 23:54:12 +0800 Subject: [PATCH 0327/1463] lib/spd_bin: Add "number" to log message Correct the missing log. Should be the part number not just part. Signed-off-by: Eric Lai Change-Id: I17ac9c6f9545d84645665d3abe1d1613baef4e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39353 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/lib/spd_bin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 4bf77d2baf..84e2123b98 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -177,7 +177,7 @@ void print_spd_info(uint8_t spd[]) /* Module Part Number */ spd_get_name(spd, spd_name, type); - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + printk(BIOS_INFO, "SPD: module part number is %s\n", spd_name); printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", From ac7d6b409e117bb7559d01e5a57e634712503fe5 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 5 Mar 2020 17:19:51 -0800 Subject: [PATCH 0328/1463] mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi. BUG=none BRANCH=none TEST=Build and boot volteer Signed-off-by: Srinidhi N Kaushik Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Nick Vaccaro --- .../google/volteer/variants/baseboard/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b9ed424158..70b6186494 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -226,7 +226,10 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 off end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end device pci 15.0 on chip drivers/i2c/generic From b3bfb2a1a7ffc190dc37905b073da8d1d3b054ba Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Mar 2020 15:41:55 +0100 Subject: [PATCH 0329/1463] util/kconfig: Silence warning about _GNU_SOURCE For some reason, this symbol gets redefined, which causes a warning. Hide the warning by checking whether it is already defined. Change-Id: I70ffc9a799e0b536d6aba7d00f828bd6d915d94c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39183 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/kconfig/nconf.c | 2 ++ util/kconfig/regex.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/util/kconfig/nconf.c b/util/kconfig/nconf.c index 905dcd11bd..42ea494f6b 100644 --- a/util/kconfig/nconf.c +++ b/util/kconfig/nconf.c @@ -5,7 +5,9 @@ * Derived from menuconfig. * */ +#ifndef _GNU_SOURCE #define _GNU_SOURCE +#endif #include #include diff --git a/util/kconfig/regex.c b/util/kconfig/regex.c index a6d947fbd0..d0e1d7b2f5 100644 --- a/util/kconfig/regex.c +++ b/util/kconfig/regex.c @@ -24,7 +24,9 @@ #pragma alloca #endif +#ifndef _GNU_SOURCE #define _GNU_SOURCE +#endif /* We need this for `regex.h', and perhaps for the Emacs include files. */ #include From 7b6a82dc1a6ca7157ba95793ae03afc542cff42f Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 6 Mar 2020 14:45:51 -0800 Subject: [PATCH 0330/1463] vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Patrick Georgi Reviewed-by: Wonkyu Kim --- .../intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 21 ++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 24cbd6e9ef..8ab5878f83 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -635,7 +635,18 @@ typedef struct { /** Offset 0x091A - Reserved **/ - UINT8 Reserved33[438]; + UINT8 Reserved33[3]; + +/** Offset 0x091D - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration +**/ + UINT8 HybridStorageMode; + +/** Offset 0x091E - Reserved +**/ + UINT8 Reserved34[434]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -643,7 +654,7 @@ typedef struct { /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved34[101]; + UINT8 Reserved35[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -661,7 +672,7 @@ typedef struct { /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved35[264]; + UINT8 Reserved36[264]; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -675,7 +686,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved36[269]; + UINT8 Reserved37[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -683,7 +694,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved37[80]; + UINT8 Reserved38[80]; } FSP_S_CONFIG; /** Fsp S UPD Configuration From 7e303581bcda7d7a4a90d75a9b6f6698d55287ce Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 6 Mar 2020 14:36:23 -0800 Subject: [PATCH 0331/1463] mb/intel/tglrvp: Add TGL UP4 RVP Add initial TGL UP4 RVP build enviorment BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Wonkyu Kim Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363 Reviewed-by: Nick Vaccaro Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/Kconfig | 6 +- src/mainboard/intel/tglrvp/Kconfig.name | 5 +- .../tglrvp/variants/tglrvp_up4/Makefile.inc | 20 ++ .../tglrvp/variants/tglrvp_up4/devicetree.cb | 203 ++++++++++++++++++ .../intel/tglrvp/variants/tglrvp_up4/gpio.c | 108 ++++++++++ .../intel/tglrvp/variants/tglrvp_up4/memory.c | 59 +++++ 6 files changed, 398 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc create mode 100644 src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb create mode 100644 src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c create mode 100644 src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 5eec51ee43..2051a056a1 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_TGLRVP_UP3 +if BOARD_INTEL_TGLRVP_UP3 || BOARD_INTEL_TGLRVP_UP4 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,11 +28,13 @@ config MAINBOARD_DIR config VARIANT_DIR string default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3 + default "tglrvp_up4" if BOARD_INTEL_TGLRVP_UP4 config GBB_HWID string depends on CHROMEOS - default "TGLRVP" if BOARD_INTEL_TGLRVP_UP3 + default "TGLRVPUP3" if BOARD_INTEL_TGLRVP_UP3 + default "TGLRVPUP4" if BOARD_INTEL_TGLRVP_UP4 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name index a2271f33cc..eb8e796f69 100644 --- a/src/mainboard/intel/tglrvp/Kconfig.name +++ b/src/mainboard/intel/tglrvp/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_INTEL_TGLRVP_UP3 - bool "Tigerlake UP3 DDR4/LPDDR4 RVP" + bool "Tigerlake UP3 RVP" + +config BOARD_INTEL_TGLRVP_UP4 + bool "Tigerlake UP4 RVP" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc new file mode 100644 index 0000000000..c272607042 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019-2020 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb new file mode 100644 index 0000000000..a937ab3cc8 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -0,0 +1,203 @@ +chip soc/intel/tigerlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + register "SmbusEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "PrmrrSize" = "0x10000000" + + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[10]" = "1" + + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + + register "PcieClkSrcUsage[1]" = "0x2" + register "PcieClkSrcUsage[2]" = "0x3" + register "PcieClkSrcUsage[3]" = "0x8" + + # enabling EDP in PortA + register "DdiPortAConfig" = "1" + + register "DdiPort1Hpd" = "1" + register "DdiPort1Ddc" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + #HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 08.0 off end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 off end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 on end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + device pci 13.0 off end # GSPI3 0xA0FD + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 on end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 15.0 on # I2C0 0xA0E8 + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)" + register "probed" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + device pci 17.0 on end # SATA 0xA0D3 + device pci 19.0 off end # I2C4 0xA0C5 + device pci 19.1 on end # I2C5 0xA0C6 + device pci 19.2 on end # UART2 0xA0C7 + device pci 1c.0 off end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 on end # RP3 0xA0BA + device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 off end # RP6 0xA0BD + device pci 1c.6 off end # RP7 0xA0BE + device pci 1c.7 off end # RP8 0xA0BF + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1e.0 off end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 off end # GSPI0 0xA0AA + device pci 1e.3 off end # GSPI1 0xA0AB + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 on end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 on end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 + end +end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c new file mode 100644 index 0000000000..cc810aa1fc --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* PCH M.2 SSD */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* Camera */ + PAD_CFG_GPO(GPP_B23, 0, PLTRST), + PAD_CFG_GPO(GPP_C15, 0, PLTRST), + PAD_CFG_GPO(GPP_E22, 0, PLTRST), + PAD_CFG_GPO(GPP_H12, 0, PLTRST), + + /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + + /* ISH UART0 RX/TX */ + PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + + /* ISH I2C0 */ + PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + + /* ISH GPI 0-6 */ + PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + + /*Audio */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + /*Audio */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */ + + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */ + + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */ + + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c new file mode 100644 index 0000000000..67979b649b --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +size_t __weak variant_memory_sku(void) +{ + return 0; +} + +static const struct mb_lpddr4x_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ + 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ + { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ + 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ + { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ + 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ + { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ + 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ + { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ + 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ + { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ + 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ + { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ + 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ + { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ + 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + }, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +{ + return &mem_config; +} From 9900cf80091ad1796c78c04b6ef6302410444480 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 6 Mar 2020 16:46:39 -0800 Subject: [PATCH 0332/1463] mb/intel/tglrvp: Add memory config for Tiger Lake UP4 Add LPDDR4 memory configuration for Tiger Lake UP4 platform which includes 1. DQ/DQs Mapping 2. Board id Support 3. SPD indexing BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Srinidhi N Kaushik Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365 Reviewed-by: Nick Vaccaro Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/board_id.h | 11 ++++-- .../intel/tglrvp/romstage_fsp_params.c | 9 +++-- .../intel/tglrvp/variants/tglrvp_up4/memory.c | 34 +++++++++---------- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index 364f4f7b04..8d0a31751b 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -22,9 +22,14 @@ #define EC_FAB_ID_CMD 0x0D /* TGL-U Board IDs */ -#define TGL_U_LP4_SAMSUNG 0x3 -#define TGL_U_LP4_HYNIX 0xB -#define TGL_U_LP4_MICRON 0x13 +#define TGL_UP3_LP4_SAMSUNG 0x3 +#define TGL_UP3_LP4_HYNIX 0xB +#define TGL_UP3_LP4_MICRON 0x13 + +/* TGL-Y Board IDs */ +#define TGL_UP4_LP4_SAMSUNG 0x5 +#define TGL_UP4_LP4_HYNIX 0xD +#define TGL_UP4_LP4_MICRON 0x15 /* * Returns board information (board id[15:8] and diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 89ae0ab3fb..eb8fde0a6a 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -32,13 +32,16 @@ static uintptr_t mainboard_get_spd_index(void) printk(BIOS_INFO, "board id is 0x%x\n", board_id); switch (board_id) { - case TGL_U_LP4_MICRON: + case TGL_UP3_LP4_MICRON: + case TGL_UP4_LP4_MICRON: spd_index = SPD_ID_MICRON; break; - case TGL_U_LP4_SAMSUNG: + case TGL_UP3_LP4_SAMSUNG: + case TGL_UP4_LP4_SAMSUNG: spd_index = SPD_ID_SAMSUNG; break; - case TGL_U_LP4_HYNIX: + case TGL_UP3_LP4_HYNIX: + case TGL_UP4_LP4_HYNIX: spd_index = SPD_ID_HYNIX; break; default: diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index 67979b649b..f3a8a48d45 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -25,28 +25,28 @@ size_t __weak variant_memory_sku(void) static const struct mb_lpddr4x_cfg mem_config = { /* DQ byte map */ .dq_map = { - { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ - 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ - { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ - 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ - { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ - 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ - { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ - 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ - { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ - 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ - { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ - 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ - { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ - 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ - { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ - 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + { 8, 9, 12, 11, 13, 15, 10, 14, /* Byte 0 */ + 4, 6, 0, 2, 5, 7, 1, 3 }, /* Byte 1 */ + { 2, 3, 0, 6, 1, 7, 5, 4, /* Byte 2 */ + 15, 14, 13, 8, 12, 11, 9, 10 }, /* Byte 3 */ + { 1, 0, 3, 2, 5, 4, 7, 6, /* Byte 4 */ + 14, 15, 12, 13, 8, 10, 9, 11 }, /* Byte 5 */ + { 8, 10, 11, 9, 15, 12, 14, 13, /* Byte 6 */ + 4, 7, 6, 5, 2, 0, 1, 3 }, /* Byte 7 */ + { 8, 9, 10, 11, 13, 12, 15, 14, /* Byte 0 */ + 7, 6, 4, 5, 0, 2, 1, 3 }, /* Byte 1 */ + { 1, 3, 0, 2, 6, 4, 5, 7, /* Byte 2 */ + 14, 15, 10, 12, 8, 13, 11, 9 }, /* Byte 3 */ + { 1, 0, 2, 4, 5, 3, 7, 6, /* Byte 4 */ + 12, 14, 15, 13, 9, 10, 8, 11 }, /* Byte 5 */ + { 11, 9, 8, 13, 12, 14, 15, 10, /* Byte 6 */ + 4, 7, 5, 1, 2, 6, 3, 0 } /* Byte 7 */ }, /* DQS CPU<>DRAM map */ .dqs_map = { /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } }, From c97bf6fdb4882f3cee9e6b72dbee1899036f7ecc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 7 Mar 2020 19:55:17 +0100 Subject: [PATCH 0333/1463] util/superiotool: Drop one SCH5317 entry The SCH5317 can have either 0x85 or 0x8c as device ID. However, the former results in false positives on any ITE IT85xx series embedded controller, which has led some people to think that chip was actually in their laptops. Moreover, there is no register dump for the SCH5317. Since nobody has touched this in over a decade, avoid further confusion by dropping the misleading definition. Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39376 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- util/superiotool/smsc.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index ab61ba4d19..7e50548ef9 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -860,9 +860,6 @@ static const struct superio_registers reg_table[] = { {EOT}}}, {0x83, "SCH5514D", { /* From sensors-detect */ {EOT}}}, - {0x85, "SCH5317", { /* From sensors-detect */ - /* The SCH5317 can have either 0x85 or 0x8c as device ID. */ - {EOT}}}, {0x86, "SCH5127", { /* From sensors-detect, dump from datasheet */ {NOLDN, NULL, {0x02,0x03,0x21,0x22,0x23,0x24,0x26,0x27, From e61241822160d9a3e4ce26464798a590fac22a91 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 16 Jan 2020 13:08:18 +0100 Subject: [PATCH 0334/1463] libpayload/corebootfb: Keep local copy of framebuffer info Keeping a local copy of the framebuffer info allows us to make changes, e.g. add offsets. It also avoids trouble with relocation. Change-Id: I852c4eb229dd0724114acb302ab2ed7164712b64 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38537 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- payloads/libpayload/drivers/video/corebootfb.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index 11397ba905..c4b50480dd 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -61,13 +61,12 @@ static const u32 vga_colors[] = { (0xFF << 16) | (0xFF << 8) | 0xFF, }; -/* Addresses for the various components */ -static unsigned long fbinfo; -static unsigned long fbaddr; +struct cb_framebuffer fbinfo; static unsigned short *chars; -#define FI ((struct cb_framebuffer *) phys_to_virt(fbinfo)) -#define FB ((unsigned char *) phys_to_virt(fbaddr)) +/* Addresses for the various components */ +#define FI (&fbinfo) +#define FB ((unsigned char *) phys_to_virt(FI->physical_address)) #define CHARS (chars) static void corebootfb_scroll_up(void) @@ -230,12 +229,9 @@ static int corebootfb_init(void) if (lib_sysinfo.framebuffer == NULL) return -1; - /* We might have been called before relocation (like FILO does). So - just keep the physical address which won't break on relocation. */ - fbinfo = virt_to_phys(lib_sysinfo.framebuffer); + fbinfo = *lib_sysinfo.framebuffer; - fbaddr = FI->physical_address; - if (fbaddr == 0) + if (FI->physical_address == 0) return -1; font_init(FI->x_resolution); From de74842049cccc7c47861ce38029d81058c42fef Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 23 Jan 2020 13:23:09 +0100 Subject: [PATCH 0335/1463] libpayload/corebootfb: Add option to center a 80x25 console This makes payloads which are hardcoded to a 80x25 console look much better, e.g. FILO with its "GRUB" user interface. Change-Id: I9f4752328d85d148cd40a0c2337c7191e1d6a586 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38538 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- payloads/libpayload/Kconfig | 7 ++++++ .../libpayload/drivers/video/corebootfb.c | 23 +++++++++++++++++-- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f7501e36b0..36f4af5215 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -315,6 +315,13 @@ config COREBOOT_VIDEO_CONSOLE Say Y here if coreboot switched to a graphics mode and your payload wants to use it. +config COREBOOT_VIDEO_CENTERED + bool "Center a classic 80x25 console on bigger screens" + depends on COREBOOT_VIDEO_CONSOLE + help + Say 'y' here if your payload is hardcoded to a 80x25 console. Otherwise + its output would look squeezed into the upper-left corner of the screen. + config FONT_SCALE_FACTOR int "Scale factor for the included font" depends on GEODELX_VIDEO_CONSOLE || COREBOOT_VIDEO_CONSOLE diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index c4b50480dd..8e7ac11540 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -236,8 +236,16 @@ static int corebootfb_init(void) font_init(FI->x_resolution); - coreboot_video_console.columns = FI->x_resolution / font_width; - coreboot_video_console.rows = FI->y_resolution / font_height; + /* Draw centered on the framebuffer if requested and feasible, */ + const int center = + IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CENTERED) + && coreboot_video_console.columns * font_width <= FI->x_resolution + && coreboot_video_console.rows * font_height <= FI->y_resolution; + /* adapt to the framebuffer size, otherwise. */ + if (!center) { + coreboot_video_console.columns = FI->x_resolution / font_width; + coreboot_video_console.rows = FI->y_resolution / font_height; + } chars = malloc(coreboot_video_console.rows * coreboot_video_console.columns * 2); @@ -246,6 +254,17 @@ static int corebootfb_init(void) // clear boot splash screen if there is one. corebootfb_clear(); + + if (center) { + FI->physical_address += + (FI->x_resolution - coreboot_video_console.columns * font_width) + / 2 * FI->bits_per_pixel / 8 + + (FI->y_resolution - coreboot_video_console.rows * font_height) + / 2 * FI->bytes_per_line; + FI->x_resolution = coreboot_video_console.columns * font_width; + FI->y_resolution = coreboot_video_console.rows * font_height; + } + return 0; } From ef613b97cf03d764f2894e314c65282589af55b3 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Sun, 16 Feb 2020 02:35:03 +0300 Subject: [PATCH 0336/1463] Documentation: Add Montevina ThinkPads common page - Add a common page about Montevina ThinkPads. - Describe how to disable ME and remove its firmware on these models. - Describe vendor flash layouts. Thanks to swiftgeek for his help when writing this, especially the last paragraph and flash layouts. Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/mainboard/index.md | 1 + .../mainboard/lenovo/montevina_series.md | 164 ++++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100644 Documentation/mainboard/lenovo/montevina_series.md diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 126a8fb875..e46e0f37af 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -77,6 +77,7 @@ The boards in this section are not real mainboards, but emulators. ### GM45 series +- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md) - [X301](lenovo/x301.md) ### Sandy Bridge series diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md new file mode 100644 index 0000000000..ab858a61e5 --- /dev/null +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -0,0 +1,164 @@ +# Lenovo X200 / T400 / T500 / X301 common + +These models are sold with either 8 MiB or 4 MiB flash chip. You can identify +the chip in your machine through flashrom: +```console +# flashrom -p internal +``` + +Note that this does not allow you to determine whether the chip is in a SOIC-8 +or a SOIC-16 package. + +## Installing without ME firmware + +```eval_rst +.. Note:: + **ThinkPad R500** has slightly different flash layout (it doesn't have + ``gbe`` region), so the process would be a little different for that model. +``` + +On Montevina machines it's possible to disable ME and remove its firmware from +SPI flash by modifying the flash descriptor. This also makes it possible to use +the flash region the ME used for `bios` region, allowing for much larger +payloads. + +First of all create a backup of your ROM with an external programmer: +```console +# flashrom -p YOUR_PROGRAMMER -r backup.rom +``` + +Then, split the IFD regions into separate filse with ifdtool. You will need +`flashregion_3_gbe.bin` later. +```console +$ ifdtool -x backup.rom +``` + +Now you need to patch the flash descriptor. You can either [modify the one from +your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or +[generate a completely new one with **bincfg**](#creating-a-new-flash-descriptor-using-bincfg). + +#### Modifying flash descriptor using ifdtool + +Pick the layout according to your chip size from the table below and save it to +the `new_layout.txt` file: + +```eval_rst ++---------------------------+---------------------------+---------------------------+ +| 4 MB chip | 8 MB chip | 16 MB chip | ++===========================+===========================+===========================+ +| .. code-block:: none | .. code-block:: none | .. code-block:: none | +| | | | +| 00000000:00000fff fd | 00000000:00000fff fd | 00000000:00000fff fd | +| 00001000:00002fff gbe | 00001000:00002fff gbe | 00001000:00002fff gbe | +| 00003000:003fffff bios | 00003000:007fffff bios | 00003000:01ffffff bios | +| 00fff000:00000fff pd | 00fff000:00000fff pd | 00fff000:00000fff pd | +| 00fff000:00000fff me | 00fff000:00000fff me | 00fff000:00000fff me | ++---------------------------+---------------------------+---------------------------+ +``` + +The last two lines define `pd` and `me` regions of negative size. This way +ifdtool will mark those as unused. + +Update regions in the flash descrpitor (it was extracted previously with +`ifdtool -x`): +```console +$ ifdtool -n new_layout.txt flashregion_0_flashdescriptor.bin +``` + +Set `MeDisable` bit in ICH0 and MCH0 straps: +```console +$ ifdtool -M 1 flashregion_0_flashdescriptor.bin.new +``` + +Delete previous descriptors and rename the final one: +```console +$ rm flashregion_0_flashdescriptor.bin +$ rm flashregion_0_flashdescriptor.bin.new +$ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin +``` + +Continue to the [Configuring coreboot](#configuring-coreboot) section. + +#### Creating a new flash descriptor using bincfg + +There is a tool to generate a modified flash descriptor called **bincfg**. Go to +`util/bincfg` and build it: +```console +$ cd util/bincfg +$ make +``` + +If your flash is not 8 MB, you need to change values of `flcomp_density1` and +`flreg1_limit` in the ifd-x200.set file according to following table: + +```eval_rst ++-----------------+-------+-------+--------+ +| | 4 MB | 8 MB | 16 MB | ++=================+=======+=======+========+ +| flcomp_density1 | 0x3 | 0x4 | 0x5 | ++-----------------+-------+-------+--------+ +| flreg1_limit | 0x3ff | 0x7ff | 0x1fff | ++-----------------+-------+-------+--------+ +``` + +Then create the flash descriptor: +```console +$ ./bincfg ifd-x200.spec ifd-x200.set ifd.bin +``` + +#### Configuring coreboot + +Now configure coreboot. You need to select correct chip size and specify paths +to flash descriptor and gbe dump. + +``` +Mainboard ---> + ROM chip size (8192 KB (8 MB)) # According to your chip + (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip / 0x1ffd000 for 16 MB chip + +Chipset ---> + [*] Add Intel descriptor.bin file + # Note: if you used bincfg, specify path to generated util/bincfg/ifd.bin + (/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file + + [*] Add gigabit ethernet configuration + (/path/to/flashregion_3_gbe.bin) Path to gigabit ethernet configuration +``` + +Then build coreboot and flash whole `build/coreboot.rom` to the chip. + +## Installing with ME firmware + +To install coreboot and keep ME working, you don't need to do anything special +with the flash descriptor. Just flash only `bios` externally and don't touch any +other regions: +```console +# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios +``` + +## Flash layout + +The flash layouts of the OEM firmware are as follows: + +```eval_rst ++---------------------------------+---------------------------------+ +| 4 MB chip | 8 MB chip | ++=================================+=================================+ +| .. code-block:: none | .. code-block:: none | +| | | +| 00000000:00000fff fd | 00000000:00000fff fd | +| 00001000:001f5fff me | 00001000:005f5fff me | +| 001f6000:001f7fff gbe | 005f6000:005f7fff gbe | +| 001f8000:001fffff pd | 005f8000:005fffff pd | +| 00200000:003fffff bios | 00600000:007fffff bios | +| 00290000:002affff ec | 00690000:006affff ec | +| 003e0000:003fffff bootblock | 007e0000:007fffff bootblock | ++---------------------------------+---------------------------------+ +``` + +On each boot of vendor BIOS `ec` area in flash is checked for having firmware +there, and if there is one, it proceedes to update firmware on H8S/2116 (when +both external power and main battery are attached). Once update is performed, +first 64 KB of `ec` area is erased. Visit +[thinkpad-ec repository](https://github.com/hamishcoleman/thinkpad-ec) to learn +more about how to extract EC firmware from vendor updates. From 9f3e734e5c3760ff30906862a3f9ca724ea5fffb Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 25 Feb 2017 09:56:53 +0100 Subject: [PATCH 0337/1463] libpayload: Improve rtc functions On Lenovo T500 the RTC readings where wrong, as RTC has different encodings, depending on the statusB register. Support BCD vs binary RTC format and AM/PM vs 24h RTC format. Fixes wrong date and time on Lenovo 500. Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/18498 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/libpayload/drivers/nvram.c | 47 +++++++++++++++++++----- payloads/libpayload/include/libpayload.h | 3 ++ 2 files changed, 41 insertions(+), 9 deletions(-) diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index a116d1b65f..34ee0331e1 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2008 Uwe Hermann + * Copyright (C) 2017 Patrick Rudolph * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -111,23 +112,51 @@ int nvram_updating(void) */ void rtc_read_clock(struct tm *time) { + u16 timeout = 10000; + u8 statusB; + u8 reg8; + memset(time, 0, sizeof(*time)); - while(nvram_updating()); + while (nvram_updating()) + if (!timeout--) + return; - time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1; - time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS)); - time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES)); - time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY)); - time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS)); + statusB = nvram_read(NVRAM_RTC_STATUSB); + + if (!(statusB & NVRAM_RTC_FORMAT_BINARY)) { + time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1; + time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS)); + time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES)); + time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY)); + + if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) { + reg8 = nvram_read(NVRAM_RTC_HOURS); + time->tm_hour = bcd2dec(reg8 & 0x7f); + time->tm_hour += (reg8 & 0x80) ? 12 : 0; + time->tm_hour %= 24; + } else + time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS)); + time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR)); + } else { + time->tm_mon = nvram_read(NVRAM_RTC_MONTH) - 1; + time->tm_sec = nvram_read(NVRAM_RTC_SECONDS); + time->tm_min = nvram_read(NVRAM_RTC_MINUTES); + time->tm_mday = nvram_read(NVRAM_RTC_DAY); + if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) { + reg8 = nvram_read(NVRAM_RTC_HOURS); + time->tm_hour = reg8 & 0x7f; + time->tm_hour += (reg8 & 0x80) ? 12 : 0; + time->tm_hour %= 24; + } else + time->tm_hour = nvram_read(NVRAM_RTC_HOURS); + time->tm_year = nvram_read(NVRAM_RTC_YEAR); + } /* Instead of finding the century register, we just make an assumption that if the year value is less then 80, then it is 2000+ */ - - time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR)); - if (time->tm_year < 80) time->tm_year += 100; } diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 4b6a250f28..74969726bf 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -130,6 +130,9 @@ static const char _pstruct(key)[] \ #define NVRAM_RTC_YEAR 9 /**< RTC Year offset in CMOS */ #define NVRAM_RTC_FREQ_SELECT 10 /**< RTC Update Status Register */ #define NVRAM_RTC_UIP 0x80 +#define NVRAM_RTC_STATUSB 11 /**< RTC Status Register B */ +#define NVRAM_RTC_FORMAT_24HOUR 0x02 +#define NVRAM_RTC_FORMAT_BINARY 0x04 /** Broken down time structure */ struct tm { From 4ce52903b00efa45d2ad8cd1f886553e2b21cf91 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 15 Feb 2020 17:56:01 +0100 Subject: [PATCH 0338/1463] 3rdparty/libgfxinit: Update submodule pointer Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- 3rdparty/libgfxinit | 2 +- Documentation/gfx/libgfxinit.md | 26 +++++++++----- src/drivers/intel/gma/Kconfig | 14 +++++--- src/drivers/intel/gma/libgfxinit.h | 3 +- src/mainboard/apple/macbookair4_2/Kconfig | 2 +- .../apple/macbookair4_2/gma-mainboard.ads | 3 +- src/mainboard/google/auron/gma-mainboard.ads | 2 +- src/mainboard/google/butterfly/Kconfig | 2 +- .../google/butterfly/gma-mainboard.ads | 3 +- src/mainboard/google/eve/gma-mainboard.ads | 2 +- src/mainboard/google/glados/gma-mainboard.ads | 2 +- src/mainboard/google/link/gma-mainboard.ads | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/parrot/gma-mainboard.ads | 3 +- src/mainboard/google/poppy/gma-mainboard.ads | 2 +- src/mainboard/google/slippy/gma-mainboard.ads | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/google/stout/gma-mainboard.ads | 3 +- src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 12 +++---- .../variants/2570p/gma-mainboard.ads | 2 +- .../variants/2760p/gma-mainboard.ads | 2 +- .../variants/8460p/gma-mainboard.ads | 3 +- .../variants/8470p/gma-mainboard.ads | 3 +- .../variants/folio_9470m/gma-mainboard.ads | 3 +- .../variants/revolve_810_g1/gma-mainboard.ads | 3 +- src/mainboard/intel/dg43gt/gma-mainboard.ads | 1 - src/mainboard/kontron/ktqm77/Kconfig | 2 +- .../kontron/ktqm77/gma-mainboard.ads | 5 +-- src/mainboard/lenovo/l520/Kconfig | 2 +- src/mainboard/lenovo/l520/gma-mainboard.ads | 3 +- src/mainboard/lenovo/s230u/Kconfig | 2 +- src/mainboard/lenovo/s230u/gma-mainboard.ads | 3 +- .../t400/variants/r500/gma-mainboard.ads | 2 +- .../t400/coronado-5/gma-mainboard.ads | 2 +- .../variants/t400/malibu-3/gma-mainboard.ads | 2 +- src/mainboard/lenovo/t410/gma-mainboard.ads | 2 +- src/mainboard/lenovo/t420/Kconfig | 2 +- src/mainboard/lenovo/t420/gma-mainboard.ads | 3 +- src/mainboard/lenovo/t420s/Kconfig | 2 +- src/mainboard/lenovo/t420s/gma-mainboard.ads | 3 +- src/mainboard/lenovo/t430/Kconfig | 2 +- src/mainboard/lenovo/t430/gma-mainboard.ads | 3 +- src/mainboard/lenovo/t430s/Kconfig | 2 +- src/mainboard/lenovo/t430s/Makefile.inc | 2 +- .../t430s/variants/t430s/gma-mainboard.ads | 34 +++++++++++++++++++ .../{ => variants/t431s}/gma-mainboard.ads | 3 +- src/mainboard/lenovo/t440p/gma-mainboard.ads | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t520/gma-mainboard.ads | 3 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/t530/gma-mainboard.ads | 3 +- src/mainboard/lenovo/x131e/Kconfig | 2 +- src/mainboard/lenovo/x131e/gma-mainboard.ads | 2 +- src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 2 +- .../lenovo/x1_carbon_gen1/gma-mainboard.ads | 2 +- src/mainboard/lenovo/x200/gma-mainboard.ads | 2 +- src/mainboard/lenovo/x201/gma-mainboard.ads | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x220/gma-mainboard.ads | 3 +- src/mainboard/lenovo/x230/Kconfig | 2 +- src/mainboard/lenovo/x230/gma-mainboard.ads | 3 +- .../packardbell/ms2290/gma-mainboard.ads | 3 +- .../purism/librem_bdw/gma-mainboard.ads | 2 +- .../purism/librem_skl/gma-mainboard.ads | 2 +- .../razer/blade_stealth_kbl/gma-mainboard.ads | 2 +- .../roda/rv11/variants/rv11/gma-mainboard.ads | 2 +- .../roda/rv11/variants/rw11/gma-mainboard.ads | 4 +-- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/lumpy/gma-mainboard.ads | 3 +- util/autoport/main.go | 3 +- 70 files changed, 157 insertions(+), 87 deletions(-) create mode 100644 src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads rename src/mainboard/lenovo/t430s/{ => variants/t431s}/gma-mainboard.ads (95%) diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index fe7985f2a0..cdbfce2757 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit fe7985f2a0692bc773d470a92ec54d22d3c12e4b +Subproject commit cdbfce275777f2fd142e3a3c73469807a4c40207 diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index 0608363906..bb4528b958 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -65,11 +65,20 @@ board can initialize graphics through *libgfxinit*: select MAINBOARD_HAS_LIBGFXINIT Internal ports share some hardware blocks (e.g. backlight, panel -power sequencer). Therefore, each board has to select either eDP -or LVDS as the internal port, if any: +power sequencer). Therefore, each system with an integrated panel +should set `GFX_GMA_PANEL_1_PORT` to the respective port, e.g.: - select GFX_GMA_INTERNAL_IS_EDP # the default, or - select GFX_GMA_INTERNAL_IS_LVDS + config GFX_GMA_PANEL_1_PORT + default "DP3" + +For the most common cases, LVDS and eDP, exists a shorthand, one +can select either: + + select GFX_GMA_PANEL_1_ON_EDP # the default, or + select GFX_GMA_PANEL_1_ON_LVDS + +Some newer chips feature a second block of panel control logic. +For this, `GFX_GMA_PANEL_2_PORT` can be set. Boards with a DVI-I connector share the DDC (I2C) pins for both analog and digital displays. In this case, *libgfxinit* needs to @@ -96,7 +105,8 @@ You can select from the following Ports: type Port_Type is (Disabled, -- optionally terminates the list - Internal, -- either eDP or LVDS as selected in Kconfig + LVDS, + eDP, DP1, DP2, DP3, @@ -112,8 +122,7 @@ both DPx and HDMIx should be listed. A good example is the mainboard Kontron/KTQM77, it features two DP++ ports (DP2/HDMI2, DP3/HDMI3), one DVI-I port (HDMI1/Analog), -eDP and LVDS. Due to the constraints mentioned above, only one of -eDP and LVDS can be enabled. It defines `ports` as follows: +eDP and LVDS. It defines `ports` as follows: ports : constant Port_List := (DP2, @@ -122,7 +131,8 @@ eDP and LVDS can be enabled. It defines `ports` as follows: HDMI2, HDMI3, Analog, - Internal, + LVDS, + eDP, others => Disabled); The `GMA.gfxinit()` procedure probes for display EDIDs in the diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 207135139c..d57faa0fa8 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -74,13 +74,13 @@ config GFX_GMA depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE -config GFX_GMA_INTERNAL_IS_EDP +config GFX_GMA_PANEL_1_ON_EDP bool depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT - default n if GFX_GMA_INTERNAL_IS_LVDS + default n if GFX_GMA_PANEL_1_ON_LVDS default y -config GFX_GMA_INTERNAL_IS_LVDS +config GFX_GMA_PANEL_1_ON_LVDS bool depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM @@ -102,11 +102,15 @@ config GFX_GMA_GENERATION default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X -config GFX_GMA_INTERNAL_PORT +config GFX_GMA_PANEL_1_PORT string - default "DP" if GFX_GMA_INTERNAL_IS_EDP + default "eDP" if GFX_GMA_PANEL_1_ON_EDP default "LVDS" +config GFX_GMA_PANEL_2_PORT + string + default "Disabled" + config GFX_GMA_ANALOG_I2C_PORT string default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B diff --git a/src/drivers/intel/gma/libgfxinit.h b/src/drivers/intel/gma/libgfxinit.h index c4a8a5b4d2..7a00b5cf65 100644 --- a/src/drivers/intel/gma/libgfxinit.h +++ b/src/drivers/intel/gma/libgfxinit.h @@ -16,7 +16,8 @@ enum { GMA_PORT_DISABLED, - GMA_PORT_INTERNAL, + GMA_PORT_LVDS, + GMA_PORT_EDP, GMA_PORT_DP1, GMA_PORT_DP2, GMA_PORT_DP3, diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 627b421649..2f48e50458 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP - select GFX_GMA_INTERNAL_IS_EDP + select GFX_GMA_PANEL_1_ON_EDP select MAINBOARD_HAS_LIBGFXINIT select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE diff --git a/src/mainboard/apple/macbookair4_2/gma-mainboard.ads b/src/mainboard/apple/macbookair4_2/gma-mainboard.ads index e45320f36e..64f6981b35 100644 --- a/src/mainboard/apple/macbookair4_2/gma-mainboard.ads +++ b/src/mainboard/apple/macbookair4_2/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + eDP, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/google/auron/gma-mainboard.ads b/src/mainboard/google/auron/gma-mainboard.ads index d110261be2..79ca0075f2 100644 --- a/src/mainboard/google/auron/gma-mainboard.ads +++ b/src/mainboard/google/auron/gma-mainboard.ads @@ -21,7 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, HDMI1, DP1, DP2, diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 33a840fd83..4e014558ca 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE # Workaround for EC/KBC IRQ1. select HAVE_IFD_BIN select HAVE_ME_BIN - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select MAINBOARD_HAS_LIBGFXINIT select SANDYBRIDGE_VBOOT_IN_ROMSTAGE diff --git a/src/mainboard/google/butterfly/gma-mainboard.ads b/src/mainboard/google/butterfly/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/google/butterfly/gma-mainboard.ads +++ b/src/mainboard/google/butterfly/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/google/eve/gma-mainboard.ads b/src/mainboard/google/eve/gma-mainboard.ads index 87cdb5e7c0..52f6783ddb 100644 --- a/src/mainboard/google/eve/gma-mainboard.ads +++ b/src/mainboard/google/eve/gma-mainboard.ads @@ -21,7 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, DP1, DP2, HDMI1, diff --git a/src/mainboard/google/glados/gma-mainboard.ads b/src/mainboard/google/glados/gma-mainboard.ads index 87cdb5e7c0..52f6783ddb 100644 --- a/src/mainboard/google/glados/gma-mainboard.ads +++ b/src/mainboard/google/glados/gma-mainboard.ads @@ -21,7 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, DP1, DP2, HDMI1, diff --git a/src/mainboard/google/link/gma-mainboard.ads b/src/mainboard/google/link/gma-mainboard.ads index 41737255a6..fae0b5b06e 100644 --- a/src/mainboard/google/link/gma-mainboard.ads +++ b/src/mainboard/google/link/gma-mainboard.ads @@ -17,7 +17,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, DP3, HDMI3, others => Disabled); diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index c5b680c89b..4afd76110e 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE # This board also feature sandy-bridge CPU's so must have LVDS - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select MAINBOARD_HAS_LIBGFXINIT select SANDYBRIDGE_VBOOT_IN_ROMSTAGE diff --git a/src/mainboard/google/parrot/gma-mainboard.ads b/src/mainboard/google/parrot/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/google/parrot/gma-mainboard.ads +++ b/src/mainboard/google/parrot/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/google/poppy/gma-mainboard.ads b/src/mainboard/google/poppy/gma-mainboard.ads index 87cdb5e7c0..52f6783ddb 100644 --- a/src/mainboard/google/poppy/gma-mainboard.ads +++ b/src/mainboard/google/poppy/gma-mainboard.ads @@ -21,7 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, DP1, DP2, HDMI1, diff --git a/src/mainboard/google/slippy/gma-mainboard.ads b/src/mainboard/google/slippy/gma-mainboard.ads index cd5e2f51be..e362f891ab 100644 --- a/src/mainboard/google/slippy/gma-mainboard.ads +++ b/src/mainboard/google/slippy/gma-mainboard.ads @@ -22,7 +22,7 @@ private package GMA.Mainboard is ports : constant Port_List := (HDMI1, - Internal, + eDP, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index f945cc0316..b0ab7f948b 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM1 select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select HAVE_IFD_BIN select HAVE_ME_BIN select SANDYBRIDGE_VBOOT_IN_ROMSTAGE diff --git a/src/mainboard/google/stout/gma-mainboard.ads b/src/mainboard/google/stout/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/google/stout/gma-mainboard.ads +++ b/src/mainboard/google/stout/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index 3c95e85e4a..c4a8662e81 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -18,7 +18,7 @@ config BOARD_HP_2570P select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_16384 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION @@ -29,7 +29,7 @@ config BOARD_HP_2760P select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_8192 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION @@ -40,7 +40,7 @@ config BOARD_HP_8460P select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_8192 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM @@ -54,7 +54,7 @@ config BOARD_HP_8470P select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_16384 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION @@ -75,7 +75,7 @@ config BOARD_HP_FOLIO_9470M select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_16384 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT @@ -89,7 +89,7 @@ config BOARD_HP_REVOLVE_810_G1 select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_16384 select GENERIC_SPD_BIN - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads index 1944a24b02..a272d3e0d8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads @@ -26,7 +26,7 @@ private package GMA.Mainboard is HDMI1, HDMI3, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads index 430720aedb..bad712b4de 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads @@ -24,7 +24,7 @@ private package GMA.Mainboard is (DP1, HDMI1, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads index 01ae99aaaf..fe4efa2468 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads index 01ae99aaaf..fe4efa2468 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads index 01ae99aaaf..fe4efa2468 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/intel/dg43gt/gma-mainboard.ads b/src/mainboard/intel/dg43gt/gma-mainboard.ads index 7dab160abf..43a7d89a3a 100644 --- a/src/mainboard/intel/dg43gt/gma-mainboard.ads +++ b/src/mainboard/intel/dg43gt/gma-mainboard.ads @@ -24,7 +24,6 @@ private package GMA.Mainboard is (HDMI1, HDMI2, Analog, - Internal, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 77775e6b8e..a67fa9e13e 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_ANALOG_I2C_HDMI_B - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR diff --git a/src/mainboard/kontron/ktqm77/gma-mainboard.ads b/src/mainboard/kontron/ktqm77/gma-mainboard.ads index 66ce273d77..3ac3cd2769 100644 --- a/src/mainboard/kontron/ktqm77/gma-mainboard.ads +++ b/src/mainboard/kontron/ktqm77/gma-mainboard.ads @@ -21,7 +21,7 @@ private package GMA.Mainboard is -- For a three-pipe setup, bandwidth is shared between the 2nd and -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely - -- have a high-resolution display attached first, `Internal` last. + -- have a high-resolution display attached first, `eDP` last. ports : constant Port_List := (DP2, @@ -30,7 +30,8 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, + LVDS, + eDP, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index a300d167de..6716606ee4 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select NORTHBRIDGE_INTEL_SANDYBRIDGE select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/lenovo/l520/gma-mainboard.ads b/src/mainboard/lenovo/l520/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/lenovo/l520/gma-mainboard.ads +++ b/src/mainboard/lenovo/l520/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 662c9a5ad3..1248906630 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/lenovo/s230u/gma-mainboard.ads b/src/mainboard/lenovo/s230u/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/lenovo/s230u/gma-mainboard.ads +++ b/src/mainboard/lenovo/s230u/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads index 8a72a31c6b..3623d623f4 100644 --- a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads @@ -24,7 +24,7 @@ private package GMA.Mainboard is (DP1, HDMI1, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads index 71d160087a..9bf6352f7b 100644 --- a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads @@ -26,7 +26,7 @@ private package GMA.Mainboard is DP2, HDMI2, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads index 92702b2978..9ab80b59dd 100644 --- a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads @@ -24,7 +24,7 @@ private package GMA.Mainboard is (DP2, HDMI2, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t410/gma-mainboard.ads b/src/mainboard/lenovo/t410/gma-mainboard.ads index 9c2a3cb369..b75db6c693 100644 --- a/src/mainboard/lenovo/t410/gma-mainboard.ads +++ b/src/mainboard/lenovo/t410/gma-mainboard.ads @@ -24,7 +24,7 @@ private package GMA.Mainboard is (DP2, -- DP++ connector on the dock HDMI2, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index d26ad1714b..7c715ed843 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index a19bf339fd..eb0936d810 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -27,6 +27,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 89f84fccd8..6af93ac887 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS diff --git a/src/mainboard/lenovo/t420s/gma-mainboard.ads b/src/mainboard/lenovo/t420s/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/lenovo/t420s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420s/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index a73a1b2225..009377d78f 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads index a19bf339fd..eb0936d810 100644 --- a/src/mainboard/lenovo/t430/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430/gma-mainboard.ads @@ -27,6 +27,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 5162e0568e..3ed0d0ecde 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS if BOARD_LENOVO_T430S + select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_T430S select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T431S diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 425047fe44..d9f54d5989 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -18,5 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd diff --git a/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads b/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads new file mode 100644 index 0000000000..61793e295a --- /dev/null +++ b/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- Copyright (C) 2017 Bill XIE persmule@gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t430s/gma-mainboard.ads b/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads similarity index 95% rename from src/mainboard/lenovo/t430s/gma-mainboard.ads rename to src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads index 8cf5d2fe13..4cc7433eaf 100644 --- a/src/mainboard/lenovo/t430s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + eDP, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t440p/gma-mainboard.ads b/src/mainboard/lenovo/t440p/gma-mainboard.ads index d36cb82e3c..1626f88f5a 100644 --- a/src/mainboard/lenovo/t440p/gma-mainboard.ads +++ b/src/mainboard/lenovo/t440p/gma-mainboard.ads @@ -24,7 +24,7 @@ private package GMA.Mainboard is (DP1, -- MiniDP DP2, -- dock, DP2-1 (DP/HDMI) and DP2-2 (DP/DVI) Analog, - Internal, + eDP, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 6d31be2e6c..a628adc646 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -14,7 +14,7 @@ config BOARD_LENOVO_BASEBOARD_T520 select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/lenovo/t520/gma-mainboard.ads b/src/mainboard/lenovo/t520/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/lenovo/t520/gma-mainboard.ads +++ b/src/mainboard/lenovo/t520/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 233d4d3f60..bef0dee118 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -18,7 +18,7 @@ config BOARD_LENOVO_BASEBOARD_T530 select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_W530 diff --git a/src/mainboard/lenovo/t530/gma-mainboard.ads b/src/mainboard/lenovo/t530/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/lenovo/t530/gma-mainboard.ads +++ b/src/mainboard/lenovo/t530/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 352be84050..29fda105f2 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select SERIRQ_CONTINUOUS_MODE select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/lenovo/x131e/gma-mainboard.ads b/src/mainboard/lenovo/x131e/gma-mainboard.ads index 2df96b5b2b..cd3b98d01d 100644 --- a/src/mainboard/lenovo/x131e/gma-mainboard.ads +++ b/src/mainboard/lenovo/x131e/gma-mainboard.ads @@ -22,7 +22,7 @@ private package GMA.Mainboard is ports : constant Port_List := (HDMI1, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index f49805c36a..830ace427d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads b/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads index 99d0a28b9c..c9a3d47e8e 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads +++ b/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads @@ -25,7 +25,7 @@ private package GMA.Mainboard is HDMI1, HDMI2, HDMI3, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x200/gma-mainboard.ads b/src/mainboard/lenovo/x200/gma-mainboard.ads index 92702b2978..9ab80b59dd 100644 --- a/src/mainboard/lenovo/x200/gma-mainboard.ads +++ b/src/mainboard/lenovo/x200/gma-mainboard.ads @@ -24,7 +24,7 @@ private package GMA.Mainboard is (DP2, HDMI2, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x201/gma-mainboard.ads b/src/mainboard/lenovo/x201/gma-mainboard.ads index 9c2a3cb369..b75db6c693 100644 --- a/src/mainboard/lenovo/x201/gma-mainboard.ads +++ b/src/mainboard/lenovo/x201/gma-mainboard.ads @@ -24,7 +24,7 @@ private package GMA.Mainboard is (DP2, -- DP++ connector on the dock HDMI2, Analog, - Internal, + LVDS, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index b20255e1cc..7c4754dbbd 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/lenovo/x220/gma-mainboard.ads b/src/mainboard/lenovo/x220/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/lenovo/x220/gma-mainboard.ads +++ b/src/mainboard/lenovo/x220/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 73dfdf6a10..b25d7cf858 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/lenovo/x230/gma-mainboard.ads b/src/mainboard/lenovo/x230/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/lenovo/x230/gma-mainboard.ads +++ b/src/mainboard/lenovo/x230/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/packardbell/ms2290/gma-mainboard.ads b/src/mainboard/packardbell/ms2290/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/packardbell/ms2290/gma-mainboard.ads +++ b/src/mainboard/packardbell/ms2290/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/purism/librem_bdw/gma-mainboard.ads b/src/mainboard/purism/librem_bdw/gma-mainboard.ads index 1aba615128..750e46ec10 100644 --- a/src/mainboard/purism/librem_bdw/gma-mainboard.ads +++ b/src/mainboard/purism/librem_bdw/gma-mainboard.ads @@ -21,7 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, HDMI1, others => Disabled); diff --git a/src/mainboard/purism/librem_skl/gma-mainboard.ads b/src/mainboard/purism/librem_skl/gma-mainboard.ads index 1aba615128..750e46ec10 100644 --- a/src/mainboard/purism/librem_skl/gma-mainboard.ads +++ b/src/mainboard/purism/librem_skl/gma-mainboard.ads @@ -21,7 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, HDMI1, others => Disabled); diff --git a/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads index 4d55f2cbc8..82c66e0035 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads +++ b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads @@ -21,7 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (Internal, + (eDP, DP1, DP2, HDMI1, diff --git a/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads b/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads index c9d6a75030..bde759f752 100644 --- a/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads +++ b/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads @@ -20,6 +20,6 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is - ports : constant Port_List := (Internal, HDMI3, others => Disabled); + ports : constant Port_List := (eDP, HDMI3, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads index 5f1bf50e77..fe7487500b 100644 --- a/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads +++ b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads @@ -22,7 +22,7 @@ private package GMA.Mainboard is -- For a three-pipe setup, bandwidth is shared between the 2nd and -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely - -- have a high-resolution display attached first, `Internal` last. + -- have a high-resolution display attached first, `eDP` last. ports : constant Port_List := (DP2, @@ -30,7 +30,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal, + eDP, others => Disabled); end GMA.Mainboard; diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 56304c9349..6e72921504 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select NORTHBRIDGE_INTEL_SANDYBRIDGE select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_PANEL_1_ON_LVDS select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 select HAVE_IFD_BIN diff --git a/src/mainboard/samsung/lumpy/gma-mainboard.ads b/src/mainboard/samsung/lumpy/gma-mainboard.ads index e45320f36e..105b231e4f 100644 --- a/src/mainboard/samsung/lumpy/gma-mainboard.ads +++ b/src/mainboard/samsung/lumpy/gma-mainboard.ads @@ -28,6 +28,7 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + others => Disabled); end GMA.Mainboard; diff --git a/util/autoport/main.go b/util/autoport/main.go index dbd8913723..e3c3fdfa06 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -931,7 +931,8 @@ private package GMA.Mainboard is HDMI2, HDMI3, Analog, - Internal); + LVDS, + eDP); end GMA.Mainboard; `) From f8cd291344f2a8b8ecc90cfb7bb5ca864dcc9441 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sat, 7 Mar 2020 14:55:35 -0700 Subject: [PATCH 0339/1463] drivers/ipmi: Fix buffer double-free If reading the data for the asset_tag fails, that buffer should be freed, not the one for serial_number. Change-Id: I2ecaf7fd0f23f2fb5a6aa0961c7e17fff04847f4 Signed-off-by: Jacob Garber Found-by: Coverity CID 1419481, 1419485 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39378 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/drivers/ipmi/ipmi_fru.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 8be53f8e0a..43ee6b3a35 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -319,7 +319,7 @@ static void read_fru_product_info_area(const int port, const uint8_t id, goto out; } if (!data2str((const uint8_t *)data_ptr, info->asset_tag, length)) - free(info->serial_number); + free(info->asset_tag); } out: From 915d1eaeae417b5e0114da33efe87272e3adb6e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 6 Mar 2020 13:29:08 +0100 Subject: [PATCH 0340/1463] soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to add the smbios_slot_desc for the SMBIOS Type9 entries into the devicetree, and not use numbers but strings like "SlotTypePciExpressGen3X4", smbios.h needs to be included in the static.c. Signed-off-by: Michał Żygowski Change-Id: Id15fe4101d14479b02e536fdf63748a241c02bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39351 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Reviewed-by: Frans Hendriks --- src/soc/intel/braswell/chip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 9f790dc140..ae9787b0a8 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -27,6 +27,7 @@ #include #include #include +#include #define SVID_CONFIG1 1 #define SVID_CONFIG3 3 From acabbce229e05f3a649bd3f97a4254acc7440966 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 Mar 2020 20:10:48 +0100 Subject: [PATCH 0341/1463] mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to rewrite their values in ramstage. Tested, my Asus P5QPL-AM still boots. Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber --- .../variants/p5qpl-am/overridetree.cb | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index e84fd8a212..1305bff368 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -22,9 +22,6 @@ chip northbridge/intel/x4x # Northbridge chip superio/winbond/w83627dhg device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port - # global - irq 0x2c = 0x92 - # parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 @@ -40,16 +37,12 @@ chip northbridge/intel/x4x # Northbridge irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # SPI - device pnp 2e.7 on end # GPIO6 (all input) - device pnp 2e.8 off end # WDT0#, PLED - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xf0 = 0xf3 - end - device pnp 2e.209 on # GPIO4 - irq 0xf4 = 0x00 - end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on end # GPIO4 device pnp 2e.309 off end # GPIO5 device pnp 2e.a on # ACPI irq 0x70 = 0 From d903fffbc9694ca228f60006d272c9cdde41e760 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 Mar 2020 20:55:21 +0100 Subject: [PATCH 0342/1463] mb/asus/p5g41t-m_lx: Correct GPIO direction Not all GPIO4 pins on the SuperIO are configured as outputs. Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/mainboard/asus/p5qpl-am/early_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/p5qpl-am/early_init.c b/src/mainboard/asus/p5qpl-am/early_init.c index 5987033a09..97411fdb94 100644 --- a/src/mainboard/asus/p5qpl-am/early_init.c +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -114,7 +114,7 @@ static int setup_sio_gpio(void) need_reset = (reg != old_reg); pnp_write_config(GPIO_DEV, 0x30, 0x05); pnp_write_config(GPIO_DEV, 0xf6, 0x08); /* invert GPIO43 */ - pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ + pnp_write_config(GPIO_DEV, 0xf4, 0xa4); /* GPIO4 direction */ const int gpio43 = (bsel & 2) >> 1; const int gpio44 = (bsel & 4) >> 2; From 9d422ef3816234195714abae43e3c2d31098e059 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 Mar 2020 19:50:09 +0100 Subject: [PATCH 0343/1463] mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetree This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to clobber the registers with garbage in ramstage. Tested, my Asus P5G41T-M LX still boots and it does not need a full reset on almost every reboot. Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb index 919d409181..2ea157f7d2 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb @@ -23,9 +23,6 @@ chip northbridge/intel/x4x # Northbridge chip superio/winbond/w83627dhg device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port - # global - irq 0x2c = 0xf2 - # parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 @@ -50,8 +47,6 @@ chip northbridge/intel/x4x # Northbridge device pnp 2e.109 off end # GPIO3 device pnp 2e.209 on # GPIO4 irq 0xe8 = 0x80 - irq 0xf4 = 0xa4 - irq 0xf5 = 0x46 end device pnp 2e.309 on # GPIO5 irq 0xfa = 0xff From 83565dea8638841e522b64e74a4240002bba789d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 27 Mar 2019 11:35:48 +0100 Subject: [PATCH 0344/1463] mb/protectli/vault: Add FW2B and FW4B Braswell based boards support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Frans Hendriks --- Documentation/mainboard/index.md | 4 + Documentation/mainboard/protectli/fw2b.jpg | Bin 0 -> 52579 bytes .../mainboard/protectli/fw2b_fw4b.md | 128 ++++++++++ Documentation/mainboard/protectli/fw4b.jpg | Bin 0 -> 59322 bytes src/mainboard/protectli/Kconfig | 16 ++ src/mainboard/protectli/Kconfig.name | 2 + src/mainboard/protectli/vault_bsw/Kconfig | 78 ++++++ .../protectli/vault_bsw/Kconfig.name | 5 + .../protectli/vault_bsw/Makefile.inc | 9 + src/mainboard/protectli/vault_bsw/acpi/ec.asl | 0 .../protectli/vault_bsw/acpi/mainboard.asl | 19 ++ .../protectli/vault_bsw/acpi/superio.asl | 27 ++ .../protectli/vault_bsw/acpi_tables.c | 30 +++ .../protectli/vault_bsw/board_info.txt | 6 + src/mainboard/protectli/vault_bsw/com_init.c | 16 ++ .../protectli/vault_bsw/devicetree.cb | 141 +++++++++++ src/mainboard/protectli/vault_bsw/dsdt.asl | 36 +++ src/mainboard/protectli/vault_bsw/fadt.c | 35 +++ src/mainboard/protectli/vault_bsw/gpio.c | 238 ++++++++++++++++++ src/mainboard/protectli/vault_bsw/irqroute.c | 6 + src/mainboard/protectli/vault_bsw/irqroute.h | 27 ++ src/mainboard/protectli/vault_bsw/mainboard.c | 21 ++ src/mainboard/protectli/vault_bsw/onboard.h | 34 +++ src/mainboard/protectli/vault_bsw/ramstage.c | 9 + src/mainboard/protectli/vault_bsw/romstage.c | 34 +++ src/mainboard/protectli/vault_bsw/spi_vscc.c | 18 ++ .../vault_bsw/variants/fw2b/overridetree.cb | 6 + .../vault_bsw/variants/fw4b/overridetree.cb | 6 + 28 files changed, 951 insertions(+) create mode 100644 Documentation/mainboard/protectli/fw2b.jpg create mode 100644 Documentation/mainboard/protectli/fw2b_fw4b.md create mode 100644 Documentation/mainboard/protectli/fw4b.jpg create mode 100644 src/mainboard/protectli/Kconfig create mode 100644 src/mainboard/protectli/Kconfig.name create mode 100644 src/mainboard/protectli/vault_bsw/Kconfig create mode 100644 src/mainboard/protectli/vault_bsw/Kconfig.name create mode 100644 src/mainboard/protectli/vault_bsw/Makefile.inc create mode 100644 src/mainboard/protectli/vault_bsw/acpi/ec.asl create mode 100644 src/mainboard/protectli/vault_bsw/acpi/mainboard.asl create mode 100644 src/mainboard/protectli/vault_bsw/acpi/superio.asl create mode 100644 src/mainboard/protectli/vault_bsw/acpi_tables.c create mode 100644 src/mainboard/protectli/vault_bsw/board_info.txt create mode 100644 src/mainboard/protectli/vault_bsw/com_init.c create mode 100644 src/mainboard/protectli/vault_bsw/devicetree.cb create mode 100644 src/mainboard/protectli/vault_bsw/dsdt.asl create mode 100644 src/mainboard/protectli/vault_bsw/fadt.c create mode 100644 src/mainboard/protectli/vault_bsw/gpio.c create mode 100644 src/mainboard/protectli/vault_bsw/irqroute.c create mode 100644 src/mainboard/protectli/vault_bsw/irqroute.h create mode 100644 src/mainboard/protectli/vault_bsw/mainboard.c create mode 100644 src/mainboard/protectli/vault_bsw/onboard.h create mode 100644 src/mainboard/protectli/vault_bsw/ramstage.c create mode 100644 src/mainboard/protectli/vault_bsw/romstage.c create mode 100644 src/mainboard/protectli/vault_bsw/spi_vscc.c create mode 100644 src/mainboard/protectli/vault_bsw/variants/fw2b/overridetree.cb create mode 100644 src/mainboard/protectli/vault_bsw/variants/fw4b/overridetree.cb diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e46e0f37af..c509c960f0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -117,6 +117,10 @@ The boards in this section are not real mainboards, but emulators. - [PQ7-M107](portwell/pq7-m107.md) +## Protectli + +- [FW2B / FW4B](protectli/fw2b_fw4b.md) + ## Roda - [RK9 Flash Header](roda/rk9/flash_header.md) diff --git a/Documentation/mainboard/protectli/fw2b.jpg b/Documentation/mainboard/protectli/fw2b.jpg new file mode 100644 index 0000000000000000000000000000000000000000..d6f41059bdedc4c048a9567c57501fb7bf5ec215 GIT binary patch literal 52579 zcmbTdbyyrt*YG*GYl3US1b2509^9P(!6mr6I}8>af_rdx7#xDj;2Jb|aK6cN-|v3U ze*4ev)?799tLihS&nfAv>vYfS((5JwTTV(=3IGEG12Beu0IypgH6=Z)%mDydS$Y66 z002M(V8Orwke~#DW^5?`ZOwpYTo^b247B{4h+z=^!{4Dy@-LS|nf6~9SSYhWe~S(+ z>!6t(%5R}%7c{?t{YTGVT~^`n|IxDvWwb(A04B7Yfo6R;06<1VOiNN008mqxV*13& z_t)J2$o@|$EvukR$9#6R}@wVCE$R)#Vl0SN#PEm+yvSm6@>v3~(71phA|K^Z3T9~l^^ zPq2yq=zsa!4nqBpt%y)RU_t-1V?r73-*$W`!~e_VP)7Jyh8oI9pnvQ^fSw!qU;f)y zDE~4clu`ecXNJoAfRF%xWx1i80QzU_1fiVxFMotG=wJQ>WkBA)ezCE#!sPw$v4G9{ zXDoW40}l5u2VemJ1mFL6{{RY*{^QqQH8B73U)x{`|4Yxm3~dI${TIU*{?iZY&>tiG z+fD+NLHsWnr2k^%|6-K?V$}a)^#9_&=L0aY!2m`x1XiJF2F?HXdBMiU&-Q=Lm4Did z{*_;ghX-KO002Ax)}h6J{QX;^Li7K$+e7>17t{|iR~H8WfR~${la=lNS^l-)Z-#a# z%s+kmR~gK|ybV193tcZzHGn?o7u>&V2N7CF{4d7)m;cJa!2Y9W7+Qh-m%~J%2cQZ0 zKcCnCUgdv{ho12j0+0Y8BO)RpA|N9nA)%lkqoTjXKu1GEC&GP$^_Gm7f}D()l#~+4 zOhfsek&2X*mWPg!m5q~=lY)j%h?iZEnS+!4uM!v(6cltcbV3XaLiTs0@7Vu8r`H|; z4l-aH2I}m404xp+91hIu0DuB&Cj#`E^!Kv#Z-Oo;cmzZwWE501s6Zq3-=2blg@;2x zfQN@l`~F>U@Hhy#@7Tl;->7^>dhhs_JuopJnM%C27f*Hi9LQnf6oi6`Pe4dS{DGQ= zmX4m2i<^g+k6+@Wq?ELbtel#ZGHU%gW#dzk91cfuMoLe6*{<`)b&;H*z7WDtiv;WJn|LxZb038kn zI(Tq601?2S2ioresI;Zjoej;e00U=q|KGz%S9vJED$_26gNbYHOa|ap$9--#VL)Cp zR$X*IU1MJX%PWH^lT)30V?H)G5%R5)_AB;iVZ z&K^kovsn#uCYU^A2Rj6$%x87lnbArz7d(Ki1Avo$dg0Qw2n&gp0~MUIBPM8q_j#h4EQ{#E-(A%8zR5 zyALQ66w)e293lfOZxuPH>wVasmvKZus3kO!H_<^;)Fq{CuK?=@hhIHvx2gmUkvB}7 zZ7l0wDAbHt;&G0q-dfs2tam^IyIA^3xyL#V&Q#-KO9z6#m4|N1Z`lbNrRO=UAMCn( zPQ_;gT{qZc{2Ea%$RnscMH(xkr2i}_7P8D8MBTe^4$FmvdY+;NKb0MpS|fi56G+FU zQ%6GSu_cXP$o*k*Tl!%1@&*eN7uH6TosDR~8A&8zLbLT^BfKh1VP^#F?~2xZU4wbP zgVa1noia8a2yZw`h5w%xAgW{CUxmiMP3K7}*>LEBx zMbL~82^JpT$sJJl${pOmI*h~F>~y1|vZfZfX7ReOAK)n#QdN#|JD|iIikY!0)*Duz zDD5XkVK+^cx(_dAP*0LlXqd`N+KG#rrEf|rrGFE&K|_8w;jVI5Ad$MV?pUrH+M+xi zmVn4dbhyY{^UdWhzoQp)2{dWly?7BRasyepY1VArF;Qw|c$!?XydQ}jF-AuBez?$} z1vYTuwSxKn-v9C?pP8qv|b_>J(y1)5RwLG+0K^?Uy+OBnT;4{S+gHu519 zgXq!sWq1b*e@sTF9MK6uIDz2V-l_YW8cE5GlpDeto+uC1`H&x;c_2g-5+%}?uq=a6 zDxF4(#yj7qU)v^S$;T;nLo^pX6Bd!hIoq_G1NH;-Coo>O!!M2Kr?~hsXe8$F)H^{^ z{tx>NJ_05zEdBKj$~`>oiNkOYv-@WT^r~fC$TwVEMtsZzQc}L zVfrp*%y%GeZ)+h}bi=a!YS|G9nA*`$UEh*jpAJ0he{6jP!03sASCS$YDzgmcM-3%R zvs?>NzbmBQ@K#v_qxTj@2Z{EZxxy{3=H`{Vf2HpQmZ}u0BoqX#z5*V)`MWH?EvJ}V zp*y{=rxoO#!jRBwuo}Hm6RXWx&YpL#z$crFG4|uDaQYVU`5?IWz@eF9@j8D5Aw3h& zOXhj1moXLbd5+UtL0Dei)thX|&GhOFGDV(VSy77}F#-?K(1z>4bW*w=+Qv}NnXh5D zD|pk2lo*2zdv#NJBrs4~C4Xz1Yw<->H6McDrI8Q{Ig3}cp_gH{wIf|kvL2U>b=!13 zeR$ExckqUT3|o>Uq_8CRZR~!dU#2>-;SN_KXSmqn&G8lGQ{{;s{PU{I0mXP! z z5xFmtvb-8mOP@0cKDK0dmvAfKXo5eclMK}Yt}=ekVI>syB%E0+opkqkK0UZ>*InBf zNXX!u$eXNtw4}!GNieaoh&l5f_lE+e`#U&{lQ1$ zAY6E>$>wR%3fJzk-|EZK`^TM)=`?m+01j_;2_0*;(Hp663a1w#*$_W<#j@JilT{nQ zpGp~%MS8FhDf>f~s_}gFp>Z%7WIat-xDle-!aJn9l85a@%)s758Z#|Q_&q?-dq4!O z(L49;kymF#L%IX?)mx4fvrTlDn+eApwwW6xcwL=U>sm;n%Xq|(QSBf^&rQsm>mpB< zp-hi2=PxOYzlcm*?S)JI`@&8uh_&3L<0QAs=4UkOQPVM6lmar;~Vo59wGXt zSTGm7efYkin=D^QXs!-`3E(#+Z>;}r0K{EgTa)NoXYDd613x9OioodbF6$rl8>(3e zSpGgVg*&;@>snL1rxXxVtDW?`ru4opi=1hO=dY~RBXR4I^6c3m&svmp+$O_x`j|oV z4eQ2SCw^?`NBPhIv8ty6ejvc*NLPyTrBT10bzh1myCA5SnZ*oc(fXQbsM%qm#!53a zqksaaC~DXG?G!0@tmIf1Zm^7`Hdv-UhCDjRQD&Vbt5oH)38vS*PRR(HGga)I%VU2< zJ4AP~Tn{C5Qoxl$?sz{|?~HeV6OP3 zZP6smZK=ZUnUlGb5)q?wlu(kdTukz-0)$uoGw}AO|a|bTU$`3F>KIl%+zy&6mpP<{R>~OgLO}0zy)$ zw_+w3H-+)o#(JzzY_Fv$A-&RWn=D?aW4A|?>aW0?MB;n)d^$=ks?gW2WCBQ`AAB|T zEnja-{I+97%~n_1mzcfGlsg7@RhA8^Ltg8Y%OUzET=8{MyEY!iu{q`?<)>64#s!I4 ztUO0~*@v%6Vjv~Io8ezPXyio<1n))@^dM9e3r$8Esc7j`^rST~DdBKI0g@hxN~fgbKqr@ueTp;tNUCd-CD#W zZ+zX40}7*;Mi*g<>B7Zo#*?|8=DJ-JO!460U$k|deZNf?x-h3WEFWS!>IiTqD_i-% zdk6Pgg^LvDk9|CTxU<#Uovl%x)gQ3FT?GKZd`~t%DnFQCbL&~ZRnczy6XmjjNho=r zOcea~a@Nf;<`uv%!Cf)>A_(yLP-6eJ+#v|$yW_P+@wR~)zS7;-8;o>Qtp2`!dX`ZAn$m%7DGuA>5p{P6R?1i(H{KPwbifO|WPC+S$!t;Yi<%Op2f$mqe7I z+Jly}=IO*;@ub^$nGoR9RNqZeHSg#>*o`UVXSx}Gu`(zmJShl%s-WnvXg0)29pjc6 z`V?nVH2W@2NLtx0?_0hJ!NtKn>PWk!@Q?zEu%{SHq~6UldaBe~Y;nTiyP-1(BW@#d;>0GU~&__6>s}2SK z5~YY`aS$G6dXxHyx261jxra19HLK0;VpFtVMDFm0fdS1a7BQc3tH9M(ikA|jJAH!x zWmaA^_j6ZE;|Pz8??ZtIZ`GFlH*!JBpSn*KR?WVh<)IQGH8rFR24(41F<P8o3i)5C7=LkPme!p zYSvLMCGkNfvHTTNO4r|Itb3M>({*5szE?$rIXql1AKI3+>%}pY%KujXMXP&DK0~R3 zj;qzcjuNH)BBwWTHiFk(uV{#QYV!s}pFca_7(3`%SU5c|ZpSRCqM`5ia{XvHE3b@gb($%i8 zaW07e*bySfbiMVJZ0Rh_o@$sB?u6}BQ>{OvYG=&R8KdW0Rub0|<0}C4=r#K!Kqs%A z%&iEMVA1U`i#In!Q*t18if5V<-cJk~jk7K2yV0?)!&-#bs_@}Y`*?nvb!na9Lsy2f zG{k7N&nk{2CB!%3JWY-u@0ZCu{XR=304syqxT`ysBy6bEz~f;;?HO}HN3S*E1nz!O zws?K0R9n)S^yfIC(@*Z*sjpbgau;?UV#P6tI}Q>GrVEi?$8FEFqw%Zd(oZ?~;6Yz@zU2MGxb@P8Q{0GQg3KeDr3 zA0Sr00{SW}a~OykAz#vWPyqoTDYl%hxgrER1kRP|93vZV?@}bz2r5WS7}C>i!6|V# z$lN9Z%+7s!5EHLt{oB6ljeG%TVz!l;mgqpVK1F9UX>&do%@d^!Q{kJY3fe2^eE=Te z63_j!7S*AiF5~p!3suUU6*JJOhZ``ObT}l} zF47;1$-C5BJoaw2$1LdyBQEEz1mR05XSK(`;#Xl!UP3x}^kGFTQ_X7~p4G0mv^W6A z)q^Up=aPWyX$Q-x?*Zd_ljtNRyi2wqNQHb|?s)}RZn|C%a#x4amPrnr z$C|p|W;n^P<#7B~85H=KuenC}P`BT?EJ$TsK{8Ub7?mFvOU! zEKMxW?A%;JB8j7^NorE?HXe}Uoi0I9AF7IcuN>F-?KhPW)f`vk2&}W*{4tN6QR%z~DNWP_G&%m}zm)57)Q`de17pLe@kVb`eT~y+f z3*=(?4;8XwbsWJ^oSln^8Q8Uq+*Ygg8xv9`I}yPKNC}@w*;F_6*lJwEZqrglxpW(A zsCkS6H>DFw_U_wpIj&5vICmL_xX8=T(~U3RrLwA90J@Z%dv-D$r=xW98hBWU(5c;6HACuBsnw8XXXpf!-0qQB*xuO`_@#ZnK3q=rnF}m?~ z8Kkp|tXF{I`h4ilcZBS8Ax+!((L!OypJ^&QG}`fF%gtk#xizE*uYf8Ya=Huh=n5Tr z-6I?UFj)kjzT;v7gM7M9j?(s5wE^z*L-Hz@V8{oon<|t-Z~q2;j_j)r6=tmSz^Th> z3B9h?v;luB&rjz}Q#o#lF(4j_pIWlpgv^|eAx-JYPt!7}ATi8Vr1R~fQ&U|hm6*N7 z)Uksv_xe-awQTLHL+{TVIx6!v9cM3V3YkwBUD0fGesdnnkH0_R09Vz!u{(+FlrOjcB4cSY|0dp4m z)E^DAu6Wk8K2R9~hE!#?^JZQ~ik1yHtedcWo%VG;td@~K=K%-=X#waK_X}YmBDU?g z`b$UHD{Dr2A!aG>`o>7kAeTv(3F^Tk&(^dxW_nJs2xTrIbrHt&aB#y!lfubMMKja( z)N_LJ#(x&kbIfYx5=+%5anx&jb`O9_NeX(e0943OV~4D*9wu7jHpt!e_q{UG$8#AF z!+=Q~pnzVK@Hl5fPVd)VHo?gsaomo2xFg=m$R~#_v&aHpx7lLM#Z~`L^A2|k9q-@7 z%6rfwYVu)Gq@XK6G;L+shr3Pr1N8FzjI*JkCL!yb&!VFb!6KPpU}$9T&f?qxa9!YB zD0{fYyF`a@69>NK!Ibb+S@wdeCqJ6#i<9?r_Efi*UXc4dnNW4Ejq``mqOsOJAPL(B zbQ(RVHzC`enMJzeFr0mu^c=F@jUU`VhTyX?Z818zi6Sa(TO<21-8t#yQPy=^u_ee+ zp1$1B(X_p-X)U5I)zX!Le3GoQK&{Rk$hv^uv4j`7Xw_LIm?;sru7U91@4h(>a5Qu- zeUdvrjVr;MwbW7);8yAA4RBl}8dPt&tIuDRnc)e;mo^2>@bBh6?l;Bc1FNfkStzL2 z+pS(}o6qj*Y&L{`w~%5K1O@EGD|y{7{2oooq7)3$Vn!ij^>SWshs4Kxw#~s15szDo zc&C)v_qa)0!xSWLp&z_?`Blk_80k9BJie}34r&vmj4!2XZKuH&XItp9MEmlkkak@IoogT4S6!0 zmHo5yQY$Z`G|LZHnP=e`4UQmLq_f*6N$Xr3tFNC_J%cb>HKjKGUfGX0H(&?LbOv2G zm$_wlkkmykWLD ztX;;UIlL;}TDzNb?_pFUL4T%euXd3>=~lJ(i)($php6SOfNok7uIc#Y*}2|vSpEQC zVwvOl<*&$FiJvH;hIg+^nK73$31wv2Lu z_e@I<*v@w*0fN(ARC)oLENE7VuK;(au-*q_Etc)}Ur&0D4veW^bv)UUVdve#MkW=M zJuWw|RHbsW*(+V~MNk{q>`D}v3p}XXBojr|H#f<7|9pSk@(a4<$w(&nGb>9jwh9~6 ze}0g0W}6jDBijG{EROBU_8_olZEA0VI^X=qosDW7&zac=JzhTe_*uNF2G-WA)S551 zu;!sav{ngR-h+|@T`zqn1IvpM7oF_=kE&}jkT{_hy!IWuS3o4jBY->8n}F0EtpU2Z z9IJ1Mvph9X)WF6@0+6S?x#TVe6{)KJ>gG<2FO|Ku)1)&31|~K5+CUn*kv+6jW*Yva zDGIxuw#hgO2D?cqNf=6&TD@7<_xwqlIPV!##z)>=<-Hgp7Tw!MYp<;f#u{b!Gh~}k zH%yflCIWwLm->{8=|lNGIU6siSk_dqVngT7hcVCFl+pHR@SMyOiHz^y{7(r_QDpTgg)3>^H@)>${8%7KJjP6A^au~4 zJnxG#?~-qK|4o&}^k>fxpG8v5h|Em#T3!JbLU)D4W+tNH>JcADTCjJjWqJXwB}5f( zh^p1U2&oEag~422Ko-xdrYq|KLeY@&vk2l{AyjCv%<(m|09J_bFwOJ9S(i)F{a* zXEzf&Mm4x`=rGMOcv?CkiX|K*YTBj(=T4uhO5W8s9FS@z{+Ky`(HSuxFk+U#6neNh zRFfo6w{vdA2`5ob-WA5W^9!q*Q$SU9(yWc$7JGzkQRX2LcBT4QkV6ay4qrM|%N}1I5x5#P1@9~nKk)*mNigeVdch#YA6<3epE6`8`D=4G;{3UiGN+O#w7@v}J8Q&SL#>Nsq3j9TMyG;U(e?K*9-I7p0q z_Hr%z=&61W+2197#wzKQfE8prO+A>f--|*g=Qkz&YVG(wnJ2<~Ym`G%HLl-=rw5}45M0Y&V8eELmx%G|aoc}I~E7;%Z z30hOY%6#iu!h%>3LBaj$00~}w%PKWq_eY}t7RArr2)3nfb^~}|ev_JG{OR6&Yhm5Z zj!#N^>MlAIFE|EFsS45cR#fga%{NuP#{L7T*Eg{E(C2b?KliArlN!OtMV)Qd1j{!Q%tI=cVp1j7r>Uj0<%Ya3p1Y zr}Db}mjwZvJ`f@+UQheEg_InHtas2xr}IQ1@^m*xElkV-U4{)Ta7!;jKRauCO1yr! z>(P9M`!Sz~NGB8MZTf&(VVmI!uD~@sinYR}lhs5)HtXHAgEzZ6lm!N@VS0fD?BoaV zj}E;q-Wy9B<5ly(D$xy3`g)r;G`x*0N>cVTOYZ1fR&|lI8%t`o1fKI}xs`Kd%G_WG zRpuxsqTuU%51fz6A>iFj3LgGb<&8m&W(eD+Y(H<_DdX2yip3eTZ3EEIOp3PNE@zTyIR@Nhv z+TMq8;8a;2r)C89m=ItrJzjiNDzeTtuK`*-wRS0-d0V`F# z&uJ<#&M_|gYU47;M!G&{`?<(H$o#4>^fO7_S5{14Ms87+mW9CiX9 zFVYWaSffh+c{k0SfH}(NS97SO`iQOD;h9aVlf%v~ga$3!Ozs=K4s4xPPGm!Xz@vc9;-$V5~m$?Q2yK%0b{mMkeM#%^j86kN93M z!8eAIq={mUiQA0Qi>^o(*N{e`V z8_TMloSz?vh>_s6!{+d7NLq^Vam$y%n$o260pVU}APl435F7xym0?=vCDc zqMl)o+6}#r^D`>au51Z?Ncq@OHjRHJByZ#cm-3RQO?gWG6F5Jm5WOl(411|FRv@6#awa;~?Y#D|Fh7wHzrU<|9 zQBO&3ex{&_d?T!(m%a|w&bcCE3a|gU34ZiZy{Mg2IeX8>N{RnzbJD9{#SlF4J*lIAn#el1^GlvJz|_oDt$L|+;mwPBAZcVD>=aL? zjFTokSggq_+w1WCQ0*gOgI5@W46%_~1_lV5=6D^%TNhkV@5&-Z!-R1yqhYbBhuKT3 zdMy;^+F4W`YAQK<(<~Fy=C#JXn>-zr9o{5`>)p?Ww4ni$_?G-AH|qOgf~HLq@&uHF zy4%^@Mb>^VE!>1h^-r436gKO%e(-jQlWD~cHQj&nGYh~rx1UK7*nnpvBFxaV&&F*w zWU-F4Q-4!|t&{%>_*AFo5nCxq!bUfWZ~I_&wOAvUQoOn1jbi}aEE`H-ee1GHp#mLL z+P56Hd@Vd^{;ayrw4*18??@8|(i$B#0~Jowd{W#gIh7RMYDERMMhVH11~$ zx#A66P&V=~SlS4jmph0XyfsQj0Ez_eQva>;w64#z^0y1qRRg9)TD# zQ{$BCJ?T&q(-`8Qr$9pDow_O94NGjc*dgeOk~ujkG+!_5xHMxHfK|Huemw9-m#(gL zR=uiMZGYH36s~$UDK0!}>D(yvr0N=?S1}-)qp?Nw10Zy<(Y>eU(cbUoRh&)vLo&!L z)E-_m8w7aNcK#WMb)Yd;G}6_?`;3>}q1~*~zAO=AUz;?Rl18*6lA=EU8=g43c_n3q z)Bgq?z%0_)=_^gDRbojjRGeaiqiyQR{bgOIIcqaVs7+HkxPN z1TQj@!pAfzX=oHl?lzl4p?QW$lf*+kR8d~CCG{bPP1}&MF6?sQa-YOZ_Fc=RnT9?R zdVBIt6CdI2TV6|4#RJfxogi}OLKYM}6Gbm4=s)Pz^r!2Cw}P~O{VbEhj~41LB+&tHX@PObL{ByoxU831*22b` zzcRntG~ShwmQ{Z=HNPUCfei{j$k!lNmv#ne(IC;iD< zr_dlaz;oxk#G+Fw51rVNh)Re7=t`{Fl*S(xT>y>Lg`)#{G{JB4*dO1hfFPKiq&q*ZV>d&B*>}wz z)pk2=sWLI_vhRaagha3L8mW+nsDkL<@r)z?>gU=rxg!1+QQXjM>ZQCJ9WUjf6e~#P znBR+;WQR6}W`NY(f-)?TLlo|~o|DQG>0$3s)EK8{E>D}o)mMixoHY8TR)Ij&?deCu zWUU~?O|~t>bYrKuu2L#R=|bPBO{dHe`1_g81I3t(W9J9$CC}btlI!yIrFO zUDmODMbBV^GyG48y`-|-ZgAjiqs=iIJV^0fW1_Kt3Y7`j4=*zp!Qhon4U4iV_gb>G zl{V3+-X9&wF~XQi{)V~V3M5+Un(A7cT67HQ+&ORo0`bBHF`LiyZjV6xL}`n{30n<7 z!oA2bh3BV>p8Fr&D*Csj2)jv@Dx)7lHmg@%Nx~(5Io{2t6h>-&+8<2m3iq+7?a)h2 zWFy{5p=oX{%^1_@NTpn~1My+dy%Xw|Tl>k`a%K;4O>b`55Yi7p*(w1%pW(AHM{yy^Zr8i4Iu|tWX{eljO zJ1L{N-0vj#c>bk0vD(_5N6bFk9AdXmXRI7Msz-LaaNBPBrE0m?)YT3arC0{OR=Tl( zIUJtC1VLE7B58bj=uQO8Z_|&LeR68IckzaP&wp*I$x%ztVw;S=Zz8ntN}n_J6pfeS zC>YxV8a>&{7&`BYL`<`L*?(4A1{nn1EsDq;Ce#M=Q zLeoscu{(X3xxx6Z1r6k)Dz(dIwoJD}%q(t=Ip0;3omW%s_)jEKjc&>Lk&?=TeUa^g z-q|P6_oi9KPujRbp3e*si#L3(gL7K4$=WL`ZyYJxGDlNQ$`SFrl0rAV9~TX7Qw+%U ztj?6O>{BhbV%>ftQMTTm8hSkVcrD~tR6R{t0om>o>2n3V?e4`)C$Y#|Dj{}nL7xWG zPI1;M<$(c^ov}%I+ToqE#|O?;dhLb+y8&a<>=2{Ma5tr0%bB054R^J!MbocD+2=%)$(Yd7=|w?%LNXz5&B&Ip zr9jRyZ1C69n8%kCsaaK!4T+eOhEK#(%OX|i&g>FuO~vRU^TroFI(&JLZS(Z=Uz*~p zq)y1ZRV-!-)sy|7x|>^arcH7^uatd)<1qQEA37?e7ImkqPBTc9yR1_a^?>Nl4D&X0 z0(IMORU~DlL3a;lLKK552FHg@8Nt1Fv?$KA`+iswvq+@=I5kWy8E)D8kEj?2A3i${ z?IZY7m3kOS%yDs)9^or1aZpD8$-_JD9jdXuav-@&>J!FYWV(hppjkEFAyki+2SZZ((nbr2;xYn=IaC>-@5T>icDz6DR zy@An~%5Jvfbx>eU)1?qYZ?jW>#TbyoQ!W8?2e)s~ALnb6anT)#eb)qjAgXt_p-)D8 zq9k49qHg9ytvftp+&};>VSa#*p!EPvp#Plg1yYEcP#Zmj_a*P;ktrt4#6kF(=Ahsa=&x(aC)99DjdA- zRu*DbO>0-0S}gELqpFK^ByT>}XZ6K|gAe^#FCw2<1jZZYxC zOdc!O1&`uT$(>8J!f$2;LUI(osvKcB=Z%#D{XRz9pM3*_(zV1`WZZ6w{{Whi=l!X{ zpX*>jNQ=IyAe($Ai3=&-B(RP0;5(hNe()(E;jdU$Sl>t-Gz1x5@_NUUdISc=pCXYS zgy_TVd*_2eo^Vt$J0Sp#Pq%};CwI)vjFj4%lpXgbJ{9uxXTnt z`HELy-QgM6$_Pr@*^x@oE?CKk3Tvp6SR!??#bsA4$rd1)YtN)UD&Zu-wX+UHnIVzh zRzXHis2lKS8wPj#k+muijAf?8Zc1-se(aa6l{_i9?2|2sJ-|IPsNc)1&evW*2jRA( z+1)L-rNwSWk~G&H4i0I_QOiem`%%D~b{)KOaEd~i=@Z9_8ib^_NL{P%d)Am;`H@V` ziGd|`iBa8Wt?h-=aF{>Ik|3>*Y*8j?-Dq8UuXQ!=DmY`qyGZOnyH9uX<3;`O5^`+p zu4x%0@otf;gy%_)Q64=Z3R5_xzBt9TbqMBr0`#?^MGnbp!YQn~5TWrVHAq__FBLA_ zog-K{r?KACn}n%n7Cb^7_?hM1h(6iI6h+EcKjPlG>K~6i8oU1VzqSyH(HdK9cjE-6 z$5(z-mHkMaVaifnjkahd;gM6C?AhIfgOFV<$b?=2lU8ZxnVF~K z=i3Wwz{@puZ9Kr$o%eO6$CGSHujS?-BQCeZ_m70=j(_Ua$EjK9h*8ZH5gC!u%h$WNn}yX`I)y?gwKVT zA8w4RJ1}Nlv?t9%xNuXN=xOKXOInjulf~0uRJ7>JrFd_vGq-Bm3S2_zXjMduj*2{l@|=~1CD5tA?`<{>U+(ueZ`-Rl()%(&ra z(WC<3-$Lp5VA3{JlQ1BzUf$9ba}?cS?}Xi8pGd&6uX~nY@oWz0#}wTqbv_e4)N9hR zamD#Xrbr|LjglU850+K2sidfVXW#W{bZu z*wifNl(Z5c6a~V%u0BceyYHrAl*#Li)TmGIrybWr+3Aw>RkOf|yHZ#* zd=SScTzD7o#f=_ih!Wi*Shrd8A>^*5E{sT(-0f1Y7*n`0amzq>cKC`}yP*`KBRez^ zAoFZ9-C(1KRu*(P^NpnsR4Z^M+o^SYsw+udJ?ySW`njt?CNTA3{tM;4;8m_%ewD6t zwe}Q7cHhX`H|U>&e;bnrBo2*>Q0e_?Q_SQpa&_bis_;xVIq@Le-Ff;`?XAMC%lzYz ztiU%%)TvAW?2eiJVA@0rg8vCgVhPg~5`H*CucS3)11pNb)d)%R6)M;f`8${PnDHT~ z8*g6B9c(npVmw$Uj1dL^ap=QjNyg1ro%o)xYOMRZ8v+n=7|al0#Pa}zsbHl}`Aa&1 zOxoRkJLX(>2h2l+zq#>2qe;@`*m_+dw&A&1yVU?26A z)2e@Nkylvumm(c-e$u$gBK+0$puWb4`!A`~D=?_)lD36=fU|5!A^`cpB5JGn=M9Q` zP#LZOn~1Oz)+?aAQ^H8k#z1&Txk0wt?nBl`$i+9ABNCz7p9^HWav6S*^mH9P7>!6E zwxYkjnj3xzk{g6dhFUh&BM(`dA~|sOh=Gsbg|1aDLA2!vhGO?>%|@9kGXrX_+nQF|}s*z4F0d?N_qFM>9;s^t>cU$Ls`cSx#a?Z+Dn zAx2A95dDw4=T)&C#{Rn3ocml4sN3(`#^LXK$O=y>v&aP&?NG+qay2MM>ob_CetnM$ zilf>N!ByBY`5Z9@bOvUMfu*S)7GrHPq$7N2fEhlsp7P$r9Tj9dqye&kEpG}5!;K5f zzTc|n%Z+tS-syYkcqWQyroc-NIPyZRNRQw?;disAE6`x^?Af~z?Dq8=j$BcmE7>%7 zNNu87&L`AxBzrGhuUtO`9Sg!^{iEY1x8;b2N-;2Wg6t>UfqrITyaG}r(|?xW%^jb( z5(zIC18W{DWc#IGCbi$F`_ZQ48g^!z;X*pbr+4zKDZ8Q>`h25`l+Kh0apb!}-%~WkiVOt7|$|Kj>O=NG!uq2}3DF8AhZB6vR07 zDj2NZKgwahZ(~Vnh#wQa0qYx1xtA@=IywU{i4gbAnbtdWiO6K-|J2o89=S~6ruBK% zM0Hq|_Wf~N(c%8t6F$+3tTV(*6W=EEd^~uwd_&OvxpYKelHj+To->0JmN2*-`ky)0 zql_#0+uNw+{mb9@d{S~|+<-G_nq2Gc4rx24uJ4~cJ0?Paw!c&9;?vx_*k+^tSbnzJ zn$N3rmMh5Ff45inm19X0oK{rT6X)&}#gV!Lmw2peh;{xPSLI1JX9i2#^z_{kH|wDm zDUKf|YOgkrZ94cVuoAj_lSCmF%U$Una$CG$gW|b0so%JH!e{%0?(s zA=)()ot|q$iXM~fLa|=#K0KW{G_9R2dhX(1<=-S=!7pGOgnWNg5fjPi2ih45H(YxW z9Xkis&N?vC*bajvnb&sXq_7B|js}jRZ3u9M4eG>q3X)#@M=H`*)D9m~QrhX`h1R5| zg8)QE;I`WH4K=o6Cj0Zkx=Y?E&ISgxaa}kEM=OtL@@aONEi8$g?))0na5^ff@jMQn zcC}`QeR=`^u(TiNoX0Wb9nby)FRrtPFU0dzDWc8E#>NC1KtEUIx+Bb8o=8$d3Ik@F z!YG^L*b95nujME-@PQjdQ(jlu(yFZlHE`*09RVb91c5zMwx~CR9oR+&(Hb2*=C1dj z!gdg}T1YSMw30mf6qFP?+GeKf_fYUfr6lM`_yTqB|0UTR2#x}{0bm9L{&gNS=JpEl?20pQ#J^*0f`Vb`( zIx#VyG65N3r@L2~f`=QPke7|+j#odo{UNb=OoA6amO~^s0(@b1zRaC$a^=g%Z>oF+ zSW)@pzd(b*#+M^-O(%ARXo5KjW`AlbEnLN?U_QZqR1wh`~* zqa^FSSfQO-RnQ2-aR0u^AXw(qu-Cfx^xfy5;F9ag{4FM|nx(hT2Jtsl9^Yl&$rKor zM&U{4y@j;WY5Trak@;*S;$ywYT#|DM_UGn3B}8*Y3vfcz6S_pH$+N*4%pq*J@C)Ql z^aLhK(y5xoVDuviS{%w&gs!+N4h^)Z9m_?8c3D8~w5CCRle%;?ql+wa{tXfSdF9YL z{$?)CfIX5?&QDwsYCQ4Uu{(=?93luVs&Hj@$o?CnS39{*d@C?xt}J7}_G{XQDa2sWi_olf<@3GW zX=c{p3-pH@djYpH%4tCzys1p+1Kg_P&!`DsLd>%K8x4;oEz4yYh+2xzeD(_NNCv&+ zMiV`Rtx`3S-mHmT=Gx*INY(`Vd^~r^?Z3VKo#kmm&y7?qp;b36tB~jT>AuL1{7FLo zJJmGRBYhLR0;gcLmxY^@w60&#c_x^+gURtjK+vX3_@p={zjHh3;*5*xzUiLylrYYn zI7$-;^ii~v@fv*;G)GWaQJY-N`6y`wECWjkupe2AQ}3yB|e)o2u8S7=rQAu z9PR#RGoO2ret$AqSV_#35{WC&8MD+qb^terzkAGf?sp&R3)hl}hRo&D>m|yDR#_mM zd>Wz3xSIX zaGYQWryDf7Q&VaNtR5%zwhOrP5|vADy<|dTFF%j}uwYLb5MuMbq^zwjt*p~m4WLjO zW`@h@c{A9^WH5NB@-FR`$6*lsbQ7%6nstFN2oVc$pRyPdX)6g@dvUsDfySMg!~f4pJ;t^XHs01XKl6&VQ)6$KR?9SsAU6c-x{3!C~QF+M3HEi*GC zEdxCpwY&=;-L!nAlXfxKy(24D7Q1 zpSOR5P~rfr4-`-V3l-b{FL40Mo%rw{Y5xD>2B4qtP~|<8H~^LH6aSB7|Nr{(zhwLW z{zv(a4TlXy5Ip?&zrO!JyYK{b4gY%ti^%ia;=c~y@p-xEc}!60(N^f}H4`~OvnxI; zI+<-Q{>?^pE$#m~=K~51tYJUXdGuVVr^WbmwN^EYYU~lX%UM`YDou~w!VX5K)#s0& zGD%C%)s`LwXHSO@cO7UcQwj!CX_kkV#e?m9y?8E*y7SaHOp_r3nZpVm-Ei@^j-Pu8 zyO@at8v*URv}cm3nz*C)*y$XtlY3xVbNrea80rTGqT%qx((SDSwx&Uge#T*eRKO}Z zBC2ALTF|(Aok|@^8m`QMMl4fnW30)Hjtqf;V6*J}QJ25o4;ZAh=1g~7B$lFLS-ls` z^WS5}d{p$qxq|6&EA*aTrce2YJ@B~FDas!+m2jF%YH1ch9EgXiSkB}G(7$}A=P_!b zakw6x!sKJ$)_sFQFBS1s;UJaG6+;gUbW9q|xZ0$v2(lvY`>Ivk zA=>3Ek31B5&XvMQQ^C-LJPMr0p3VwAe90AiB^6JF z^1Vm+R;w(Rm)pnhVF6buYY2qc#au#D82 z@A>P>Lj`^ch3*U8NQ@FoCK04z@uyQJy+Z~|isI$OX8SI7-3sPk*&i9i-fd4#x zXmUX?ttQv&dMEtyP~dvm)4A@2nrbkUk$H$==jd-|neA*?#iUpC)uBZA^qV>nZDaNS6gIkea8f%7E8~;YE3(1K2gv ziD935XYjjX_+xsU-G+&Sh|ek5q`^(==zg1{;5*D7BW6)rw_U{;{*I!$#u!L>&)m2e z;auge!qB}UY9&f3gw#wRa~_6#jQ9d!* zxP{WsW?9+q9+tfd+zX;3uBU&{bemdcNtUZW@u$T4a95=0I&|W|8~fOesFUaG^D=xE z@p%RndqpbEUe1-yg{6_g92GeIz&y;wG#t$Og8o~?`yLcx_Y#bJoUhDgkHBFvy}@B) zg36v6cNnkCk0@_*^T(#9Mc2AUoruE-Lq%#zFBmQM1h!LMhsU6VbtXc(4dOW|7}PvjZfW>4Cli(ZwF=**{N@6c zE}zF{-6nOqi8*BVU?KsTO&6~_q7JA-R7HweLf)@eQw!^qYAE_CV9OC3lir;wZio1Qov>^j z%tO*lY{gBWKdt8C5cE^Qr5ACbr+ccW2nKe4WJT3^;k+QC=}ygIhBoO9ZOBv&9h7MB zAegI+qF-J-VA;*V%yORIOA16c0C!~&B}Gdc9OoMwG|?2Rjj0RDZ#BSBNEzC6o(j%s zqXbM$nJwq3_?~T%%wg)-`Ww3CP_yP6d;yM7HB=9Lnr~@u)&{!R2yj@V0GznA`8PUF z7ryG(!N7P76KTs9_+%4t|jIgR;XVBw}Fo1)7bt%Gq- z=U8(xE`l-#6iM%=Mtp(FbFzeJ(2}pVcm~P4p!nLy14p_Uu>+2DyO8C{3_s z`FrhEu!K{DZ^(;PX+~Pk)$!nRKgmdszdambsGXEy0C9-&mDI<~gWYKn}zx+^fOx0`kGCIVTaaw=+B zD)}^N(=uh&TNy4Iwn-#8K)bo)RA7$9fTvV0#nD|p?}=DwC?{}J02?*J<#t=KAoONx zHlCQG$qAXwPO(QXt11z(X3eIwh?w}#i_W^^B0 zU3wP4&OWWvl1eTWGcTUV<~G`zdUD?2u^6_pO&3&|gHuz~)Diw5AbmB=(!yOC&Z zd6(WyVXM-`yF)7xU_PF(hseY-@H-4kpm5-np|1h8#ns&$t>NXf;NsmGd>24hv174j zF<`rLj9tZcV{%AO7=-AxXqs6SYjt}H?zE<&Wk)F2(<`35I0G1&&KCGuK#N)+4qOUm zgHd!$lAp@sKY10WDxUiNamdA#XQ?mD`#w;wh#Git&bc0RWcLG9Y@qA)?Lh=6PV-gk z*j`cupl2EP+g*S^u{>O)0|sC0poa#dQW>^(PPI_ftIoae`KRx(GwLP487MEFePcEo zFb~J*?scrC=9@znvRU_Nj|TYZ`^3f{ml2OT`PD7*VGDvsY$Wo$@)<_@Xf~whVZ&`0 z+qYg)5^Q8HJ$wHu?z3-!{&F07HAV|oJF21eGdOcBUQ7e3#wh1_ji4W1y18-3k2KSI zIsnY7AADJfm0R<-&NX1D?#4(Q`8S+CQJtR`iX7MU92(p0A8r2P$dmME@t^hRs*rj} zpa*WuxX`d={}^yFW$Gp;SAgfKzWYQqXqH}Y?Wfq9zghyVQQp-2w|CY0-wB%hyumYn zZ(GxV>Fn&PGZ&GGiH>Gpr(Fh3rZEqK@Cw1zJ*UP=8Fui?2aVI_Lef?%zQXt3q&dOj z!o3zS(5Cm*e&pQHfJkH`!Ma@dO2pbM?<{8uPS_^C!L3u<4t!>@R>-w`cVe;J6)O#G9AhXDHxbYK2X!4 zUDKU!rtK)N2&)J5#Q$utvNX|Z#Z>><{eQpx$DQDU!poraGFW6-cqljPzbS4oP{{+26_4;k!==9PF4>=KgNbzv1$mu#7rY_c2vimL{;T|c$d$*ZjQ*uD-f z(fEk3=Wf{SGj?M?Ilfl}YG#G(EsnwxMl2cZDtv)m3TzGfg@)O+k6E{m@tDo#I*=Q5 zUN3*6*OlwK{zal7f{)S}OFI;MGeS>M;6?C~UN%~y5r-n`ZEAh&V%mF@83t^ z&wX2`b)7BnXcrjqP@_hXnuJEj;f_cVq95D9wpZu5*x(T}ovYYdNE8BW93N?m%s$Vl zY_L-PtYDG#(B6FUBwOXvySXm*;Z$z!{p%^#>Z?bu0UgP)vmaBN{&9Q9~B zE~^53F|9IPX^kIg+j1ATyDsZ0W!C?~n$I15#YTvz&BJK_>xtrTD~i&aG-I;C&tg1< z71;F|Ni|D;ewTvbx1fN?REb;!G({kp88} zM{&BfVK#4lB`y<^@ddZ2O0; zLh1w7E+1@IQO;-bx5|S>-=&iKTEDqR$eRckNqAqSF!CpqoaW_`mFCm#eKTs!R1sLD z>HDlJ+P5aV;PXFD64Xk0u0m|d%4J-CBe%_mrGL$|;q^wcUCbT&KYo8Tec>$Ei~<4X z{+hqKa_XQYs?{HSbR`KU2~f6=>|%(!CT;$0xx=oY%AXKIddOEkc+#Mdz!mf~P+SwR zuv~z@;aEq{zl&oFV0;~0TQY-P66_9SeZuxfx4W=ckm)P_vh0BM-1`Crtc86$EC0kx zd0_hL%KYjhf%{$w=s$4MJ2E48DK~X)z)e4tk1N>p3A#qZ9-PK;01o5}EMRqh>ncpZ6Q358s-~h+CCsbMe=B|sdqWyP;l#SFqx`1& z&|Z=U$70%^jk0MgGXnbK-WAoQV^sMM#`BuBgK5CB3juIke7s+fz%Yg`vf|Ayz`Z2w z>-=HXlf&Z0nvEQ0g89$cnmw1&)c39o>@#Cl-(*qFTjSA`mWP(=V*Ruh$>i;#Kc#p! z?Mt?gWT(k{jg=31!s5b&L}ntX-M)e*Ew$9(2KEXU2k~s1%S5w7K--X+J$78TC5}GM z2?M*O2IRXZ+lmt_ez@w*)7P6_r+w>PcoL;u#waewB)(RG{PeAP_J%LB< zt6GPOuu3e4212KyZx3yeR^3>#g@7x1en`sx{Y~qOHe-u1vyNzmZfNB5uKDHN}wiQkhVdMec*W~8rKI*PDeNpe57hIDZ zUwOrl%`BhlX2*A*}Mr+DUp%8E}=D(hSB`_-l7 zPY(laM&s)-aI%59zP6yiKN#{6!_~cjBc8{pH5rDZpOfF2c&=j7H&{R)`zqS3jbMa6 zQ^WD<_f^y{jpbqhTz=%S3Rri7&wopH^u2`dL#dh1`P@g#KK)&VZICU+w)!1w(6O+d zaRf$BqE#DPxF##J%kjLO#67{HdEWwN-_R!KK4^Z zj$DIWXQ%C74Bs!i)pT6Bk*aeIoemu*moiE=ECMh?UbcIJ0q=evtnN+qR}@QySI$^y zs7*1odJc(#yj5LtA5~DjaSFotnKDJNO zx7I%MjoW!NX=10g0CB>v7!*##3dw&o{Ax5#ou4Cc_;k61m%IFF4a8PAMxbSIMlxws zBdky?qg|*fa6wiYi5feR+ket3GB@$DA&gHdYi*cTQ2?>|R+XD6^F^Lx3Du>mWaU>a zQZoW)JC>Pe%tK>S2Ax(%^OS8wtJy+P%{luGQcEk(s|l~NHHAIOOp^JGVpX1c80|M|!h7!o#wy2|@6CW{K)CI*^x&3!nGzfAMsneQ zT$Ld?rJZMU_C@(|YxX9(AJ@@$_SJ1s!WgG)8-9-t~)bQ>-o zHip7-Q@?*OD+!*I?(cfvBTd4a^)!0pBlHn}hjK28N0~K>zqZ#MRs!6XJkg`k4r)Xn z0LvR##Ue{;`E{MxR4a}>GEPbRBX$pJT|lL96g>6O;m?UJlVofVNW0`pH|8=J{PbDD z->?z_qo4S-`T%_TTQ}C%h4UkS-5ML7X0_^EWzYn9C~!M7`Q!@c)Ak|cO|?~Fsja!- z2C}rI>B{n$NY5UmsTIiYV@ED;MS7M)NLA0Yb5WPI<~K&CfO*?>J5`B$mgsxxbLq^G zl;?E6cWFX5vMakMcZ|LI8(Ec5Eah8G9~Wm{L93{;VqZm)F%k zgoL`Uc(;?Ap7}MA{dzyT>@7w4)~~-la?uvg0`wgTwE8B*aQLw~s4-xXwD<;fo1S~BC!Z#-kw!*T) z3udmDcf}EdRU)ub)U_=)t4>`BZ*@Yz#gV5U26frPRaL7SOPns84I$)%Q!F7;47-(0 zxe*P>3MI?6XZ`40mX@;ddQH(L0+7%P_xs&uagBqiz6^?dxoK_Ib93NbTxJbffV0YV z8@Sz<%K&|w;N|S$gDCFLLjSVBhYSxV)h|nld*yM{@d952VjWqH66%nAKVR1G=9p`H zp6d_!)PtN=ep2pD%h{cjSA;r=pGP$2!2?;b@VyG5a@)R;`0){e5rofNx&jEH{eOm`1SA#n<20I!vs$Jlx@5o zepFAXqMWUMa8-yEZ{b6Xcu&`iLNULsjETeFc7eTI zSMmc}zEN!XNN+*nCPa9}(T(xVpH*~*+I7=lLIir<9Jf!%@m62uHtHX_GY?w7nqL-y zyD*zBBQUugbYOx5NjFVf`O*K{-G+2|3Go+V&Im91n{X3tw8M61@AXNQ*O3aZ$)Ur! zD;a2hU?r-I$p;{BeAfMrSEH*mD}AiZ(y2L$U7K4}YsOjO;l_~iZ4!Ekn~Nz_Y3}c> zaH!Ik2kuF&5l#<5#ok_=S!$(&XR~-s?2}J8DM`E;x}YcUW>?!sUL2)KyRo_=8b~5C z6N2vEMw$~z+by~P?Ps!(nulSKTwS?i_`c-T>GGyy==8FQW!Q`@iu&wDPn>DJ^ zN^Zr@bu+ffd~~f(;^}K&hh>*Kef-k*#Xj{%lLlq!7`1ZjJKJ348c`+@N3!M&58sg0 z8+KIH<#t|*8eWg3R3E#kg)E~(qtqI`gk|y#F^CG~QkAlm z0(w5xjNj@!Rs|qbe5&`68vwzkAaX8Zu0xL(%O&@^QPLK3^$X`Z`pdtf5p&AIq!xZ( zXCj9yNbYAVHfo(7kYlpk1w%ttY)k;_l@{3Kqmz%v4(NXx!NK7iv!jYe0J2t93_DZv zy~P7Zq2;-#0#tHDtH(fN{z-%v;5u}gE^>XvRXpEr<>D#B;Y!A*t;G~=(s{4`kza(q zx85|%AM;zYPyEP$&Q7(5t`JKe|18TfiNA$viG>Q*22+J6r#FL&Z9g9xJS5(W?{zZL z35w|vF)|7u=Myii;JyFJ2M5)B&i#XdMk%1QBq)j;@xuq`yy*YLH(+r-P{Cp2QgcZ` z=K^@}G-zloc>gOp0i8LOgoQ3UICY*gQzAS{siDiOEL9+_z0i;R1DSZvtyJz)VicxJ zRbphO%jLQXMWM?p;E3Z}baF{m+6{pSO>|s{F%2#+Clo~>#J`wzy9u*Ci`L+>X^FprWjM>@fBnL*26Mlpg{mJlr^Xu));>bR#oUH0B2*X%0F#^G~-Pr3Qyw5DJv-;{6o4!y0oddbo@Vu zwwwwu->f}Yz!9hl^o?bUG0<4G*KVN9u75~jIg=hFjzb@kAW8O{UCE<6G-KsV{3q$P zI_`w$UI5d}wP+~N8d3hZrK2c`$i4ZXSI8+veE7IzEk{?Sc#>{8)is`eF|ZN8{vbK4 z*S=9A9+!eFE?Xf|&3O*}PAqdo&7|NeH#gFt$5>PCiBk|jkDK^urR(GUC;`osQkl=F zuE_==@!7^C`P59dx%a_hx-`5kyr-z6*3NUktrD+Bv|gr)%`0B-LdT9us;WXsIg?yk zdd!m@(biac`?23nM=d4$KNxGG6pC>|wQQn<9Aa)ARmkE(XJ;ooj$JLA?_`p{w>kk3 znE|R}$6!h*O3K#{+6x3Q%KufR>Y; z=q70|B>D#f5y*`M-fXK{$k3-ks~6%_oDFdoSQITe9__TJx4ucow!9Fe)uRdg{&F@t zvJ=4uvL%#|6I<2FrIP#YT^8YGGJAT$YN(z>0-`c=kv;GOXOX4G%B4E-Qeo z@!-DUNJtxl$EM>cBts8TZi?*;Bvyyp*OO@KUYiV{H1uZ8zEgXAXEcBZ z9aLX%@^JF7<-bE;^9ma5i3)X0eZf#vXcyF$82@8SaPa>zrT<-G0JSA-DmYv&DQa#S zX*?bccni({GNljyZA!ohWXed79C&P3fejJQbZlv&4Of9&)iP{pcuSCd1bJm9GSwFv zWU2_{ncyRc9>6{sKI<1Tyt^>6ZT~UJ*W-_)sBVb7#RT(R@wsar_bzYI@ISDq&Mx zmgv4_HkqTySL!85>yuQLJf1urCL7qByWW|mdE34UK<;|f;Y2!+q<$vu%{>#;QI&&) zBr~RBlwnKt7ztI1S1h^n-b?OHlx=1FJ$%`XK&FZ>gIc6SL>m;%)iXCA9Y66a&s-+g z)x}Ae_&yYWZ+sG&$Xr#JU(yXBQsOJe(0;Zc-e7~(L*U6WJ@2EVuCiGiMDl}{3yWst zDI4)Ur|BnL$4PQCn_q7G5h9X?vs#}T{Y=8t8Pg`nv3l||or!D*-|$Iu#A@i%nkGKQ z(xoa~C@ri+DKDVP9I&vH^_5W3-|XVo=w z@T^G}1LYIzs@2_K6iOBy|G|`wL03)cmmrgj7{;AVSIi-g28k3lWJPL*B+Gh7csQK9T~AQfu-0%} zU5&&yA4edQ{)Ho`qnLqY0G46lO zz2#th#W0sg?0PoKDU?rj<_nhW{tG^iixG0YKi8wXM8@RR^hJEp_fCkk&N| zF+$}#vzlA|a9MMv*-;Ou_9z8ZPx9%0*a;P!mnA4#nO9#>NYw3Mo-aui84r*|-1jFL zps`#xy`2!WNmXLl_oNx^=Jse~!>Q_T*We8Qd(Ax*AW8? zv?aS57O9Ij{}VPxl!S)OmpW7IU+Kr^RNnqV`jju3p2dt*%?Dok&@@~A2>IzYZ6aMw zcQRK5O()VfJ3|(ulH3PeYvmtXL-Kqf+n~8iAr_E5;_SQ4n))A%fG!&64KibZ1i*2_ z739lN85gTo`JM`KrEJ`}#6l(V*R)ltm_R$d#D8dn_N0z`kbq6?xZaw7Fq);$!kSY` zOFPTJX8mpZ20P8wWTC9XbwbROq+!r@^FU z+p2aat(_Ebw>w-0%_m;w{tPR5cPk4_Wg?&yJ)d5pl<`P29;gx7pTC4mIyk5h^0d}# zYtHc4j(gFj=5Qh!ORMq*xjqWG&-o_SMLnmAyxenwii_t@<4oH>R)>zwNBj6e>Hq&= z=z7f$l4C=XV|{7uw+^kEPv4?{TvC2nBBwem)7^E7Nt6eV?^oS1U&$tbHonTBNSYF7(gJaVHcr^@GsVWDwzQ;|6ttLHo~@edWp3zbQCb2gmY^6 z!$*u8%g`Xzv!mcX=7YcdFP8prU1S!eAeq~D1V)IX&zO!k*=X4|x%`RAo^Y`ry+|Jx z#4I)^G)Uf0Wr&EW zW~e-YFMd*%f14;AUvY5~ z#Y&d(md@fcL(x^8TJ~aDG-x`{uHiY;%~D7wc)?lE4BA;WWO~mOo0{LHhU_d~`D`1< z3R2kC>E<(@>13w5wln>#vkAY|J^Yk=M$@spyNa2uR7dVH@1S(bq)BI4O`|wc6mMC_ z>K9zz%{)v)VP_QSeA=n7&k|=fY=rtotXRV|y^C`mHH*X0v8B!9)I>k|#0)z;o#aMS1!egG__wLQFIJH10 z#(p8~oW%o0cS0IEr(LXX-N~z-FF?yH$zPl@)di%?@es~pE%oV}Q``+*VBNmXnJ0eh zd@dfHNYeKzM*qF4T!>V-=SHhL4qX2 zHQWmu!~v}&UTi8U=DYE>54;O{SzSVq0khGHGbOw72Zl=h39}M@ag@~Ir0J$nZ%EJg zJEyMQDNSAFHfV1xlo?$NEUxZHXkpW9ixnlS+36Cp_ulp@5h|UrID2nuU95~4Ec_Y0 zjqeD*YP$k(T3f)^d@0p(X5Cy?0mNxDw@>Kr$PCi0XjZ*Gv76AcdIe;JX5MJ4KQN`~#3CkmYi#>0#yPRO=m>4yV$G2xcW$r< z3fRqQfoIQ@c>I5vkNg$D&{huwIq%s#F@{zSS`8L&e!5USvo?S`i9&DzIs6+77G^|G zmvzNe_KAaon0RC2S?D+5LlBVA+^%1BQq3kx3iMn3FSb@gYR(1o>48BF+FBop^@@^0 z)ZR6uo2m~d;$tsLh0&r%v{txnN}@zX%Xa59t<67}varfN+>GcG<$-P|!wOFsnu^rl z@VXkmyq*Eo4fV>h}{PZDN{zEFEag2>jJ-n40HLE0{%B>PM@sPC_ zf|r!5u);Jt)AXbD{uB@ABQ-#nqN!e%kFlQFVVg@{OI@Yi+GD4#&OK>$3|_I3XzV$n zL*Cp@LToUKrdGRF=9!7O$}{){6SOeCFy#fGq_vqVs*W=01thD8+^&aSNxlLNvQ99_ z>~g4J3uxDtTkzKIX~J$ztDgw1d>h)Cu2?4SYbOFApuL07SXipZmXu}nCCb&@zHzSk z=*+)nMCSyTRAk0va&j}bXRiahiqa3}<@q+I8p|aS<9AN49g+&I9nTXbD!(Ut+u1NS zlH+!!{l%Wl#DCvsO}4RdrAt&SWHFs7nJ!`TI;Y{9?>mf}7f*24&m zI3J#8vPZe?@t$~riaCZDr@FF@PJ$Dg zka66gtK*t4ok;gi>2sXXf|J7-8M`l`)8A9grmPu%Pf_L7@uT))Qo$f~ffi~4eZK>> z_aU_`8{1GH8rrQm$xdB0q7;{E#G2w|?S-T}9iygdUw057+VUTa9u5FUTxIE- zG)rkPk5-IM$CZx=W?W6R=3bb*-`lt^-Ct==&H+@^t~6Qem%566kKc7A<(f1}1SPyG zvbaE#X9D(;j03i6&gii3Hc7%qBJCujSZB9stgd zBF+4aybi`Q;>e$%ZPWq@tsLDVOGB^X-)LLa=zB<4LMv-}Z!K3(a$QxpETp>rXudMe zh#r4LJN(P=pjX@<(>l9TL?hR&z}}HjdRA06Zs`S5BeM(*Z9?JbP4+3W(NWQiZYO}B zE#~TAo}t=<&r`?a@+Bu8a<}_d+ul^w-;7V)=`Fi-2JPY^_)Cydt9yU)dpk#s^;wqY zPsg1>IR^rH7!04P131_*qx5EMYB&<5QVs0ixZ!It={U=$v!vUCeA2$g`SX^a$(do6B+|_gk{P|BU)53a=8!SiTo@8rJKbl_ z_sT=>QS0ELu1ntGG9ib4b7kvkfM!Zi?4k1Xk((&cWKUyNh38?2!@-cQ+g9+rx8<#p zk5bju%xnS+_;#b}LtwhDsXlsFW4l^Brb3S1*&%m&rjsX6Xbad9$zUXGBx@}<|6kjJ+zmp}NLL8JYE?~TgB&yNTC zNvMl*SQ9*nQCbfjm)Rqh7wieO^5QS|5-=+we*M(B6jc|looW8y56eFsvT8AR;rr#`>nk3m%%uM?%L7j4}|3;BxZP~f{E_iB*kja>?nGB&52%&E&(nUz4;&3-srMp0G(GJs|C_5% zHpR4!aWbj>Q_Sg}`F^wp4OM~7+urMIO(D&qxjBs)TAxTN`xPp2CCmA3wxRrzfFK5z~QZNp8Ya8Q?ogsl`Ytih3+fTqm~+(&K|)|8beB1z+c#F`a;CnLDROB*BS(&mM09ic<^Qm{J?ZH3vwJrG;INP|G~e$#Q*=CpYx z@;Lz3FVA>-tV==P0C`(9S*ow`tKF>??q40)lEue!A0;cB7z%RZM%YPqO`OJXe}B_j zj0cj$tfC5F2Cwa!r?NyJjR62SMQ5j6LCMovt;tK>}7w+1x<47 z1}p7K(uG1%1zO%q<7LIBlb-ccyv1o}ocs#&yj#(xGv>Xza2F)kG8}|_?6vhI*wIL^ zip7;nBXXZ}&g0@T04EwH7$~1Ea#?c6OuX%qtqZSN?4bOm+r=zt$YaJJg`$2saNqNg zu@3VmMg~^-c&I#In@ssDagD||VAg?bpRTn`p;lO0__8*Mk}0u3R-ElX%f^ChL0l$1 ziLgK-kkCN?gWDw9N-_Zji6`_#IMHY7Nmg?ZAraXwRm zHix89+fSygKK&ym5{89Y z7&%nA13eIC{v+)8XGm7g!SV5afZt(A^G!OGVfZl#JZRb<(Kq?+B7iT10#{6O0u7pj zFdXW&vSLH?A^vBL7uUDueold{?FnrN$P(vcRB(o z7_ZF$iR6DURHRaV1LK`gW!%O$x+O}3Rd;Q?cLyqZ^}MNSF?EYVhyZ=*^+zR7fczl8 z#}eFvKVlit1d%t_H>=`LGpxc+a`Ex>&$i?X&oLKmjYuErV~@4p!(=c07Rn^WT$E%z zUv~%NWIManRmRr7>wj#oyq2#No{x_P-{JTq>wdEvT}_{gpQrMOzQ^f&-f$Ra&ymUN#Wk|_ezI*C8nso*d>q)K_T^0P z{qZ5Wn-3pN+wfA6?GdHrnO^JlZrN?m8zdSN>C6CcYSSKo@Bjx~;ap41Vg$Ftp5jB( z!igMn=zIm&XRj!bSY_%6a$}Fk!jbAZQ_9Hn%u+uHBG@8hH)8WNaE*lgjABJJ8=l#M zkOPlCj3|P4|L!lvW;>rEe^!0G%zG#I!r{n)UyJ^h3rHsteb8hb+49?0qgf`A8?}s57`Vm9# zP}uj@YF}JCuOGh5(rRnJ2|R}}Ft7~ugjla0aTV>)WGOn>OPe7K->_w!lT-XLBZ|5# zPX&jUj!F>jK(Vxo+V*I#@@ArM9MtucsR;N|NeE~$21VWR)YGJ)m4X7xP_?s$doIym z9kfbGhf-E4=Lx$(LEA-HJlHj=IjXt6U=9@3yT zYB(~ZeLcvOyWuPG+mCDO%z<#EKk1xklGv*3Z9Q(S<@4m-1tlfLCVt*YnFiAGb3GwZ3=VStU>H8$_xbgm~#|y91gx8+CY}(kXQ-5NY3LfU(v9ekBlbPd9 zniZe7Bpw2n7v6>x;5i7m=N~-{`+p# z{39_;6>?|$TArk}+|hLSM#Mbu5p84_n+QDHYeaW*&eYx+0h<_Nf+HU-bfi&GcwH2z z&_etrg?>_?-tZ!(erkFzu&aa^5Ii-vmCQN8o^{_Du3|l1YBKFBa);cJC&O*zJ(Sl%Lz7I=|S5nQQV%%{n)&zc>YZR z7f+Z^T{$<>(+8wog4m9g%F%?3Hmi;@ES4W8~4?jklFYZ=w(eDJl?MTN{Of+S$@ALL7ag&N` zN=LXJ;^lWo_avy10Z<)>g(N;A-77e9R5ZK}CouMSPJ(1F_*^*Q-G_hC-{Cd}H-}Z! z74dwzLc{0GZbR**PTV3ir{#Yd8~h`uU|{i(sdkLrpd%_pg8U-LM6fY#q=M|8M3p7N zM#1~x;(Qqp0EYPtmx6FV3`1T53a%f-zS9dzuu+;m=KSt7V>gjj1 z`_A%)N_*bqgnkg-ABtEAe9RPavr*Rj^VP625ItoNotl|)7jtE^Q~5&&po}?rdRW!^ z>8~WlU;e;pCjqcxOHIgzjsj1Jsp* z8f{a#{+-dR*on42NVXK4aaH`>BRb7|a&43`R6t=IHYQz7vqRE!vc{7wnO)QAwKw?3 z772+|q=j19RAWI?CpeZsCx<^_{q|Sy+m^+LvFYlJIGoahaT&5=g{5!w`qJ4y)iT0t z;rr+{yh+xpgSM8YLsTi-bPK~j(eG%CFRLrG3*u7BaH7O9v+NT`fe@UpPEPY9Z@)jcO2V&U!k zRBq8*OVUEZpZBoDk9U9VlFi!?)rNo7_>+c^MIllXBy%eH4b8uot6)4PUh-lK`MM!w zETn{Up*iZl{Da}X`#g8#HS$IUnm^OK7@}~~QSDy{pH}s)3mPtN3?R)QQ}{_!tlD-~ z?twf0`FtnZ2e^~ST^v^((|FEWW9?PCClKzf@9n^Sf8{dGC9m-%(xh=ods1vF5@$j_ zq|mDJAT&;8Fb~c5e)%J2e~|5&4mog>T!)eJ^vka$mZ|Dk%}a->>_hJ+UpUNWksQou zM~EUUw|-QBa=H78ubbV*^=W>cmKAUR^rX=_Xo}4~TY&4UHyee?I{HV}s$#RER6*$~ zzFOx=x7vFS$%Pr3O&itUIYGt@OYk$a8KyFUH?wxeAjLBBjJ-WUoh8Dv>&^jM2bLoa zSWr$+-$x!6G0rvDKa}nU8fsU~%f__(-d^aGz?nwPg^^bj6kaLfy3XN)rn~&20Xrfvy+Ll}I*fOq`a{ zx6eK?rrFKjYSE^s8|mLcFUt0*H#f)G9sl@RPCg*2 z=}CF@Fis#R#{|(!N7g3rMGhw2@XG)J#nRS1`Zd^-B zw%SI2n_DgvA3gCXmVQig&R_iY=Oj6Yc?Cw1i(D$dEBkB_&w2qfM0si>7l3KvR-?~g zl~olYHT9ecg?$2EHQNzXreAikKLoWtPkF=oETDr)`zxEwZ}W16_Jn%8i9{{w`2usr z8J6mmqUR{VJE%p>;31A3^Ic5iVCXP<{E42$gEvu?`Z3P5<9pO=r$(R1KbShhq_cbz z`>L>mE*`^|il5Vy1q^>OAQszH7`UIk4l!6V3W}O;hY&0mpD;D+TQn;M@`yBxFJUUW z-l$=_zLp~6UurF8`|Hs60#MjBB5^KEg5<$MF+Dm?EAG`fhS1zwX_PW#MAAc=j-L#t zyqPV`J*f#iMyvaH37?F6r)@{hJythxaz7=sS!SRl$dd7ak1d2sxkBns*={QL>?m;3 zU#J;u<;PLC)$G_2R1_?vtDjfFY*gahep#8tdnswy>|dPXqaq_m85m~z80-eF*cEk$ zTWx$j1=1gqJ{#T6$_cAXnvX4Uv1cKrW18&}?^y)JpxG>uG}F+%G;?YNblhb2D9RjZ z*h1FhaBxJ^brF8^DjZFh60lh7Sx+~$aaU$T#|DW^Ip4MMJ5AkC-re!6U#G#H44F&= zNbXUA)KhF~b*VoxD>)5Eh*j*fF_Y1PvJoq(@dq2!Z)mHq0$F405f2MvhS*DEM-^7R zx-H6T_r#XC^5~0*22ExRBbemf9acY-F2kK&_!7cAXFJ@+SFNkyLp)&ptOz+2vopHQ zHJ^2KHzn0X&v}werrPFwN(!1^JHJt8yTW2n-c(S;xd9!4cL7^C7WI!uYNp#q_T9Fu zf)vdzeCXD!=|qcyuQOzP+ZsUEzzDB&|5J?gBlF8TyP#p^4U)byrs-C9eL;^nOpAPn zfr| zJ^6!Z4Hw^=riD66&WtEf^3<*lc^p#wfOzh4b-(`18|>P%>(w<7~OGOW++YygVvS zqq(ju?Ek~pSx2=I{o6jcL(t$5thl=sf)*>m-6gmecS3O~?(P(KC{8I>Tv{9oMT!;I zK7RM!b>I8zO;&O;Yt5RKH92SYoSD5pUr51OPqTxhwJA24J$Aav=i+F0Cae>TD{T(x zk$QcN6+FSflJ5a3ZB+QbC*)3bn{MIVXvN>HOwm@~5kJ#pAwR}dieY@PBZRx!^Yyf| z<8mitezf*dUxJKeGr9W=PrKk2j)-?*k=nnZO%)fK{57XBTyFZoBx;Xit8R*dtejTH z7rQV$@*ryU5m^qacGtbXFz!jp%3enn^=9pq74am47?oelOA=g(!$x#KqGn@@9b>%> zBt-~0C6o554Y8LOx84=Ghm$mQpe|;<1-7pZvw4Sv84ltle;z^hT>A&$rDYBXoI1^6 zMePYCk0HJf*?;lK#YD*%2pG>pUw4n|^~;2+aSF7qy45DKQ;tY^_hjZXhSV|)VN*_o zX>~(*cPUt3m~I5LM^&wNsB1;FzLr#!Ze8Ld8lD;T#O*rM8xQL{+u(wX!`#U#+g3w` zK8^3b?wFQ9SgRu1EQ}{_oLjt=%vr$|8}ZjdWl06M5vE3ah7`w+vJ{S?d4~GH(jZt{ zT4?~V?Gs1$BhxxzJTJ^muqIR%gecFipV)O`!Ms|M+R$HZR$1Qf^I6SZHH|ujA$p9p zc5JOG+}068=j>Nh7PvH%h|ue`V4-4F@pMq~pRIb|*BQ0^qq<$3UgysnxhkJdO|P;< zy{yhT6yb6_(;Whh0?=g1ruI(Mp}WbxjDUp&RH*MZ%kS{3FdQ&Ne6M6xTV2`T;og+V z=+m)f)~z6~IG7}ai4%Zb>7zp2;z3z&r=};jF;;3&SQ$Vmzd0tD7ar?@E^rlrAF>_O zD|AbA$2je3D47~8gYY7vdodX-tB!Di7|Y(!fX)sacZPA7Wz`kNId@syf~8_wiCd?U zbvUtJ-6xrfl&tuTXk*y8!0l-=Sq)aHcCwVAYHa=*$R?WdE^nsC;X2lQyD;X*#UQ zdpS2sgb?FTwuU`!=n!=Z5Lu(sbImF!lXAbp*eZl`@6#2T8{aC!cgnCtl`B6?Ldf(bJ@=yar)idHPmcjGhfO8 z2-+gKgCjm#4ia{C{!wjR79yI2nW-k7Zfw*gET2w$STSWBNV5^MCdUqV+{mWZl`MKw zcWCEZKtfAk)tK`bHse89eNXiz+7BY!d54U@(|^!UXGd&`WYpG21#*Uj*f8->p_3?i z~N9&Ur#|)|BWJFt_ z&G0MmAR@7OP=6o~lg@De_(n)jAoDOS zQl3nWb?wUOOHqN4`#hG7pHBN^rLNc|ps6ovXjSRi>nHo~lLo%0azo2dJy^c@lkh_>((ArXB#nK+J^Y+ivKx;Ro z4nAI3ZeXfe-YC04wP;2iwV5%mxW9}ebERlBu{V#9#?7xwXjNxjp>~~ETxRH@?P=Qt zs?Kj#>c&ZuZ^~K*;RI9m8G*xGf|lm&Su~|NWt#$&PR}DA%(YnSBUR(w`%GQ8(u<>H zJFI?U@i^FB+0NDpqn2mNN$l@wVQ>C6>6PWv`k*%%E$Up52V)ohc$BWYG&G8XaD`Q`Yu0#P|KYioF$}<`*ExR8py5oMRgm*+?u4SVRTsrLhS@JTay{ z@YFEtqYeUicgaZ@OfJWDS#geeo2p~Kqc(L+{8kDjt2^(GSW?;F@!~nM2$hn@MEpIy zmad6|j*D(97`x-GvtRe7_nNdwIThZK)*9O*K#D@Ldy3)3*)lSFZLJa*G*RZtm>5$O z#;oV2iGk}s>b}jHy5mfda$ca*X!3ivA8B%EA>_yR-Vn2AvcRZw3mxWz;e<^dE~O*E z&)&%FHHV4s>-k2+H2|Z>sg*77zdoj#$BfUe`6Xs;Jx!nl**K3E#)bFsvFif85v0RF zwLJ99IJwukagJ1Sw(m{ljn_Kh%N0AkqPLy0#0T*e34f1(rJ1P=m{LhR(a|9Z?TFak zwc|yWUISUaM2BS6_p+cz$VYY+8DZVwD=&;{fzH9uN0q47yg*Vx&zospbwRx0?4lr> z#P_Y5X~xEHvO;|Yaw)Z`gEBacYE6{Gf)NAB{K8h`igz`LK2+PGzHrShoXf<#;*&}H zSXotwzi+b79Yp(? z093LCC-YY^3{W)RY2+1brX0B8Dv9nDok;ytMP*izv znWJW5bFyHBM)$K7cUEs+hzn|Bfd?y}npOW5u{m-nwrM{-W~F1s(4fdM3&M-y}x zx-p@x!g@ejM=1AN5yK#%+fMT#yZc!j38M8c&pwfLm;8#odSae`nM&AYQ zRUY34dioJ-M}V=)l*CNaf~8#EXyG5mj1rCHUXeBJY?29bisJ}g1G}me4k4kmS*#rF z9c^mb6)~*|xJ=c@?yH2ypCP>-6yG;ds#%&>>Wg*)N2$qygda|7rhrk|Fj z4P6+MF~TNO(aEQAD5u3M&imR?2Eq{=iJQpa#OM~d3*|B8mTMfOy`d$Zt2|}G8>cy! zp5!3S4kyt*o6{rT3Yd(hNR9hh5@n;VKvkx+)Y99OS3Xys&V&!WmsK7xmfz_lWl6MF zJ^zxfLVD@2zY~TuGSb|rCGBbTR%Ri{^;qS6ya(T;B&8hJf|hKVeQNB3o8U5!k%A1} zgXFgliRe9fc=V^8qVzdPlpM{olW){nZ(WF=gEBce< z@w6r>{i31f{7;*d!c3?)?b z)xwaNh(YX6_x#ywb6lo{^L&0Es(;UExL>7FU0v7k$|v!8k}9p`NwsIVFEJ{l^6@|P z?Z!zBbs9`zS84n@5}@@II%6m4z~#(;m(AO8iHUPJtXPA3jnnlcjf$&5HL;dR5iWqB z1nPm{!1PuQcDC0?omA|pPoo6cTgD^!-9MA*LQ7c}6hd#T!%Y!b&0@2L*hP|K;CAZA z@_fgfm`(W?UjiCI^E=k&7YMXe3}sS>S3UhA=-EDDZ-hG8^m{caLj22(2>l~KGHa;k zU)BJIpZhK*Tx~kDcFwqtSb9mncO)X~x0fSEs}7@`Zv_t(+`AMpA8|B1zJIdY33yMq z16?SoFH?FX*q;flP}|ZeJ8$aDvQztFhQI|qgftNX>nL^%KF{^tW$RGYvY`E0pKO0f zLTBa?r~d%OFVYi$r7ZwPXC?MH zXPJUX1j+lG)xyu*{I5(Xd|FZsvv3T!MS8k?-hhH#dkBCb#c!~D_4QbB zj|B(;h*tA-m!7<_vN=;WRIQ_Qi+Tlh)Pyg7P&x)To$SA3!eqmmlYNDmU3{EmnltQO z$E)dT9k@s*jClRgi5Z6PjHLvQzc33@)70MB?*ou?npR&dgHLuzd-)^ULX#!WmjR+i zX!p5of-OM`PrO!DITEJk{Q!$UA+#;2Ef4x%a3Qcg|DADc6#&*3=({+@_T01QPsZdbLO zO9scyk{DCWyM7@a03o|7_aMq=XI0wTRC&ITk4|F1aGFh z(%{ho(6?7%+Ie)V2CDd;t17k#l-h*=z?|W!bp%7Lm)~fAfrB4PlU*TzeuoDE;fGCE z`ea>kS}QX4ZAu6LJ^K7oBj_XSRK1`6v?%B2BP{?xlyUmSB+aCXk#JbrLyF~mGz5Tv z`|hRfzI&4{4v==A4sdrAa0DRA_?BcLq}4`Pm0GWA+l+zFJ^=t9Tz5a_`|=2}QfBKs zYO$IeWCGBSOCj+L`Q}Z1Rninis@Bw0dH_U5+C>v1oBR^0Ntk!#cToWaZor!dX;i(Q zf?hMTpoU;~&Gtj_LV!|SifGr>KR|#=*14?A_w@3amVQ8_9?nOYM?Q+4g52;yz~338 zI{<)&4EumCHQEkGxl@fUJ{qO}we#Vv+B;PheUfaf3hPz<2WV~++j{M$H(Rb444)JM zfcL+MZeF)~U67OhyZ!%v{^zkP1ODr<{cn#w(ti!$|Coh=U|Jq&Zm7AGncM4Q*Z+;H zyq4CHdDo6VTXCmV#>z?wP4W-c=2R@Lz-=0A01~gs2s%nW~4|C#9juchLbQ~96WF) zY|2Nf&JmaP5e@-|%APH^VkD`}dp7t!5&Ce2>mE>(Muuf1tu?deKIfc>a#Ua$Sn$`(lDf1qHT6kJ4`${fMHOWy(+H51EYEb z6Ilru9fB)ALHy^gTNSbrP?o+J?hq|2`MwtV1w`{R_)0eYk)RHn)r~sz3ucODN(@hI zqpI*NB>m&&SJ|5*pfc!*1ifPB0PN|bnqYchU-2>NPh^)Llg)DZx>F)qOqdr@Wo2oX zjAEOL^7{8n`~B}hrI5&H+hGPB*=E)ve0>48QGn!))8u0&~b>KMCtM{4K~+;W)X zRRk<&Q^5_FAlAYMLgykAZx0cpG^Vgp?)IJ^SuRuvc*!2F*cHZ9hjas4=`$(QiqLg zv-KWyhRu^T&SG1N1BdwqKMZimxAD`t_TWo?>qCEi;RKQ2_ck@j}vws+*2A;!HNYCNpsf_Bmc4|XJi@5d^1lX2x+>V(lYVkWesjrybu|!#( zbK}3p@sNR2LpU(Ha47}3+_FU>%#g-H`&R@{lnYj4JjN$Iz5(nGUkjrQORHj)R`qQv z^}p;g=M?nvLX9^PDd;}NiLdWp-J)dspa?L=cfP^`+%P4Ib&y^zc}e=LCNhoe7I?>j zIa5J8gUBhdub7*G;2n}YoabW^r>cewG}RW)oPjLPE`B?JgWku_?g^{# z3KrK6i{bq=;3oADBL#3(A(n*v>oIUFa`>xIJf;bAi8b>A!7OSba;327@lGzGE%2A% zDtpt{Z!^@=mFMS9zvtq7^kCt|_^X40^smxY+xYOFg6McH?z?Hjd#6D&!F}Tk=5(b#mKUJCej}bla3&@$Jo5% z7|gT5Pma#A#?!#i6^|f{07|3F^uU-j;^o7wgIpCq(N@K2&$-J3`Bi%HZu4(qW^U>S z=P1e9enRQbBPWWyDM=%kG-zLIt?4*QQR^4 z57fp5h5Hh?BvzPn2Bt>Zc9a#EXL*-Qj)=hnKBt>H7^I3;^8upVux^)w5gE_LlboCu zHo?XKlx9ehm4*1g5?s4u;k27O!{qTn@fN{2MuFSlFgm*6=;!!gIZ7Pa(t>_}&#+h3yONRpn{`6`#I|#dE^W=4z-RUlrWZzjDeHy% zP{z`PpPVv&DLWA^Misz?ZUjQUl8p0;dzbvW?8Fjo7e4T26^7CeGnuCCEi(#s0_S=% z;M-e!%{CC{S^CL@#XhSj30CS@~4H?c*jyv5#Ko_)~Q zw*aPL)k;Lo6um@%B?{CcczD2Xhc`*4!M1;eu0uxFw6=Hnpg{5})x^$BK3@Z%PP_q>d&i|0=MuWOQ( zTI8KTHA$bQya3TbiRB*!dLm~c1w_{lPdW>XqIVA;C!Lz<=A1<9zA`zY&q#i_OQv4kQ67H>GxQg3+aE(pZ!v_@x8_ zo=_(<7baunB1hMZ*ss`I)8<@;@MR^VHrw96Q&&u8|6D}>ewVc=4Ie843T9_sd4Qy< zC<7l6Hm$!v)@SJ!>*{Nb-B zAR@t$J)9zP@X?d;0Nuq85E@cT%|PK;H1fO^V;Hnjg9Qx{4>M{=Kz{D^)RmcQtLGLO zMOV&9^kj@RLjCO@fFJ{75=w*eY9MX@fBd8WlNkOF{qO(!NB`pArpTqAI?&P5^llTp~S_Mf~hdkJ2vU-FY}dWZ`Fz zl`*x_X1-TiUi+f#gD+L3UvU-b+s<$l6N@Qb6fo0Dlv-uy0uS0*egfoY5JX+t4n^DH zYE}N|QSF&Yt~KUq`wOmYW${YZYvHJL6}3@_Fplw9DEUU!mlac8-t`Z#pYo0i^b$i6 zxtHct^CYWH+}%K3eE^O!oVDz~;INl^BYzaAZ`%J6U8m27ZVkn;{?y=iS_@4F?@vsn zYeX`e^L9P1Z8vm4qhlyb12=VygpJO1@4zPvd>c6RaKo4|Lw%L2s-Lvr!@&)gUC@>_ z()ZwWBkHLq^>JyLVlt_7Ubcn3;T4_9HGTsL@D!#cQGb!JqI>;bNS~tuLOY$bad?FZ zxX`;Vj1`TGpsVm3sFEC8g?xY<{dri)vV!~+0V*5}^V0x|5mUU@soVfaISjKQV zbBz(Mgm}w-DYfDq&-=UhK3WxmIwcq18Vu#uBL#krqNHD6ecV4JG-*`V8d+E3wVO9uwXbJ)#zLWP~LIpgi?cjg}d?mMJ-y8V|53 zajKoR-lEu?^A%4ROCiVgSJ(YEVv#c<#!RYpkBjgP{%cvAJ>XoYelfcvHH+>a+?;uJ zzY4Z8dHZb=;XcU5zZhwWP9NJOHv+|=)vA(q1#j(}6h&u5xc6A*o||n#I|&8E=OQ=? zv&Pl&r#_1uIoh&1yki|t00?ZhKX%1|AFj4vQX+jNU5EY+0<&^x=2}eegHPqpcpsEY z&$WPT#8tztfbB{Ivsn|AKqGV|r6p#Wza7Z6k#}RanNC_RoX7W&C_VjOVow&Vm;j0; zt|KEhc2quvBjb-8W*ZVkHJNs!f29mip4gs;EKzD_YYHGet8t|D~PRic|s%E zH=I5@{f=yR2!(|K?BT{!VR7ffBPZWRit`<&*__@?>r zA7CJCF7prL+vV4brjJifBXjtY7wFB*n&+0@s|s zPz7OqvX9}2kSI)q7eY1`JvM*57HRmY#!qnF$uS#9X;xI;nY7ko1!n@gh=iu2QgM;9 z{IN2r)4;vZ6mNm%IDNgAQkN(^Oy!{G-fy}EimZ-h?TAMZM}-n$%;Ggd7H>$4WUF#- zuvAn&nd%f|O((@{{yWp!)n<>Q0(TP}eG!GjnF%uxN7RrWNJEjA+#=9RfBVbvAAqTo zfjwi?)G*)(StL$oM;A-S)EN)81osCmG7kQ5QAu5(rCARGNmXihMCX@==pDU5XnQjJ z3apFyw=YV)#YboKU>rrnKYFOz{P4p=#4F=061I_%GAH*-;2R0Y<(T@n$>vW#msv&k zuQ;DqW!w@xRJ}WvRbe?`6HNaq<&lmUwu@TLPYa( zy?#viNFjnP?y2<-g@eN~czOenW~?y<-wUS^gOLyHmNRxmDS{>vdB?o@yZ%UQC6FI{ z^KYtE$Ju#OmaY!dEt#aFaH3I)B&d;(C2y-U)tATL4%I0N1@0voVEqr-_mF;G^l}dZ>1trA6WFPb8&Q7g;S8c5!KzDrE(H zdXy;f46@qBmMHsA^Q*6=ST>BeZ*1@Ztzpp+iR245f^N!j?JZ3IIQcd8Mr}$>%-J!_ z>|c_%ED7CZzAvVk9U?jIYx2t!%56=Hov#00?1R$E>$>qYp!G{c$vllaiw$HJaT#gGIH^qdM8<0FAf&!wT?{8LHqxmf z%;_1tGA%7fVYWBwdN;Yz{nM1lh2`>QA< zYYgkEvKH-|Z8QZt8ojl0yN}^-KA`EGK@y{;vqdMAo|2DBj8QHs8o0M-6T!h!yLfrg zeP5-yT~0QnZj0cLJ#RcnWQMqO%VmvW3Z3&!;GDmSN9w=Mvh&(m8%LaJVQ6$}7*p@G zCxu-{A#_%Yb=NO+3PlI4;J33*>#~UCvWuh|WFtOJ2%85J6C$9D9p8nC%K2#r1J}Q4 zKjNL$s`9&5e!ab58Q{ZGh)nE+7TI9^oNm)*?^KRYyrh`m5brW7n&w3t<1$W&w|qRo z1eV4|vr&=v%=KM9jObKzk=VX~2O=A5@xDJP_m@V0;eBB8dn^(1y#V4f`!`)6=vTRa zqedfQRQA>}4!hI_xi)pMCiJXH1%z!g`w0^)(X`LQyV zn%^U%oCx~GV7OyS)w3>N5)}y?A>A~kY7_m?Yk!gaSs@v6D zmL8}m^FU&yMDf=4eU|%bXe>@VIeG4b4th+Zhyls$+a91om9M|jTJ(gI^!>H^q1$gd zUHhT6LErY{5e|H;d*dG<(>V@{40fq5piMFtA8lfBdW9ppNgg*#BJ5HytgbgA@ z%;9A5DD25|JDB_}r<;m&%ewk*u`0%pD8-v%#6Ma(E!NQ8sMW@a32EWCtcx9Ux6R#} zM~VBxap$M`&u(?ruAeJmFMo%o!Mk^-s5PpV_0d0v-fogc_P6S$_in!j!*a|?*%ptX zRdgCHUrsq&(zBx?xwVQHZ-W>&C^BS(7O*@H3pxu3ev|AM757usM}2RrIEfTU{}y&q zx2=MAXPkU^7oG0H8y)a|bn@?RNfG!M(L;jxNQanLZLIb$a*tu| z4&P=U@@>#cwb6ypCV6QcGMtn=pom|xpB1zyh}kkO07%WISYM8#v~*oH=WOPC!RJu_ z@4Q}AY2;i!n^6{4c_@_Kkw&4!OAs@R63GP<8>$f4u8NrsKDT<49w$pkOTs`6ocV1} zIj|ePVI7&hR;lYVw1I%4=W)#YowJd!hNxULJ!Ue*R0xYr5!={r#Kkv{s)1QgqFDo^ z9P(B!L3)81WfCV)nSz!yH3W6utL@G)%2hn4WDWzt-{YEC^lN7D%sfx{HpLTR{kbxe z?+b<>=VmSDv#cwzIzqlD6D5(P=_RL0-?tYg>)6P|R3@1Sn9yTt&G2k8*rzpjG6`M7 zqUX!R3~RDO&L~eJ$u{>{=g*2f8Xnc74eB1L3*b~->#|iPTs!r^959M14025_^Yq>9 zEuPXj;i8&=hHk0)iW}9SBcf*JB{^uE&629?t9_fjW;R+tnaC7kHRv?`WvQXt>@aq3 zW7?}e&9(53A|>{561}(>+Z7P&un00iJ2FLH z^AD%W%yUL8`Uw?d8*bfdLtK~lMNsG3U@ZPxHvDBMxaOG??=kH$Ck?Tpluamzy0D_{!VE3PBy5DwV z1D9yMT8l92plbD0q^CxakQt5E;7WXm(mQ3yvj>$%2d0PgJ#AiPA>di7qD(cFet4c4 zs|)8^qpYmP#@!@KnvTT)BwXvoovinfIOZ+4I*;K!7!@%;>ossb?wmkdc1+asS!xx) zQmZlb&c`mj%knQDO46)#vv1{#gi1kYG|EXDHxC8()MId&%~8erOWzn`U7ungh^$Dz z8~d>_Zjc;rN=dsd2w!7=2FYn4?AOI1;orpmjJhHC5Teeex6 zx=21(Dl__zqm4cw-s@kQcIft0D#Q+5aM}SfWqWOh2zzgFF_ z-$%lUd`5RViKCF)M|zvEV+)qX{o0)A^-9fXn zLRtbS`=eaDGQRlfx)%$`<=aCQNp;^9D5_L0es~z+ta2LH?(y#@q4yK66d^a()S3M$q%H0bG@BbU}k>N(ptQo1p2VEbkYm!>1CHI0{I>xbUOf=~m!4jrr%4uNN& zD7)XsF(LN@kC6!|WDZ$=M*`;3+L#LN#Z{xo&BdF-N;w^>T=(HKL7&4N8%JJ2O={?< z+XS=f#=6r{1Z|m)e%lF|fVdK7?NNi8nSXmZ4z#70V}m?jEJRV4Q$jqQGPad^ym zP(U+<1q8$ob3ws?5tWBB^?ogLgbGur6pLQA^F+tb68U!;AJmN2CtAwv_?L+yELW&6$l0Klifn5u`+^4Nx|I82iEU=JVC z+7PGGhtwCAb{d&yxphhMu(sYqmzA6sSco3g?#{dMrZcJPh3UZ0UOZ4noP00DHmrKz z%7f<=I_ymkBxCMtsoKT+)V_~T6JFKl!OWKqhV6JAmodTRHVhK(Dv=0raRM(@ay;U| zA2i$$#IR#kNr66&-eG($ zqGipCR@!)@r5MRWNn7OhBY`d5RN!Q;K;vl9WK|*SynFF@VM}@W$A?NWym?Z>%$&(_ z(QCAM%3dU;zkjxODJM`|F*XebB|VtcSC^aQspl?RpOd&T9Ih(kn7wDSQeI9$s)%Po zR38?8E_+peie)#+Wh%i>3*oO_?eBX-y2(mtVQ6TwaPmkv) zzVjxzxT=J)@67#6e6>3>n<4ktVO05Y^bwz3O+v7CCp75P180G2It-1Y*)|^>mb{&V z*pZHqrO1zxzVo(muq#W7-?0*pa<|IJh@$2!vo_c-CY9omR2OS=DdzjUYTPo94BIRD@&M4H(JP_1+FGAlD zIoq>o1wb`!es2&OZ%(coi4+2;?Tm5-YsilNpiH(_--~-t7LB$*(LB>+LM91u%ax6y zBH9)`v|xXYr|A`$dotJR63TySnpo&mY_zmFpHN5N5Vkqn;4DH9DI;~+(7}CAo75mg zq-Nwlnv{ZZE05zzRK(w!D|8^dm^Mop9HYk z`jp#_gx4g9(&pSJs&L4zUy_w3#GW5<*m%61^$4;3eU>%{7AV2)qXBc5o2l6EC0l?2 zMIXejuM$wag4rXmfND}iG6hxJ@Jll(JE1wH7pihX_)$4ZsUu7b}Z%T^sZZ3$@Ceb3oHp@zb8P!v#Ptui zAlpzZWoOh8X$ABU)CP_<&c!j`V1LU(tB_9C&W)fa7s|b?mS;o$t!3)-oMB10#a*du^@#~ZF(3&H561!H1nB6gd`m93}o zW#Ksmg*@+l!_P7l7j;Lt)&f3am%FFN=u-9<2CJ#lJ;X|=2k6LB%+Lmx#}gh~?N*1W zOO#a9%gy1lOukl+yg?CbYoeh{l@@X&OfTalCPf9Ul5Z<6%zB=P(#K!ZQP#Ryca|?O zKI)s@HW7%`K=1zn3|W*;J_8Z(*{tYF4}#1;ZuKT70%R%escyk0iKoQ~J@Yl2JI(>0 z{S<5v8+o(~n_Z5mKcCA%2Z(#9(qe=R1508<4BW9epZ4h}$&OgMtI5R@3n1#TNfStJ zPFuGx4`0QmCYJv88Y!#wPLdN*I%T#A;$akC6b!o|IwHb87LQ~8ifK290kZx<(Ed)B z(}2&PdO5O&T4oO=&e;$gP>wlO{5n%O9vby)(r;(6iQ9#RGt766p-&k|DU{4y*w_hKpFAG`h z2z;kZRhMNXbi&TB??4|QEr>9*#yy3wK@pzDYKDy6AMM?QD*WEE(&W!n%_lrKyTocK zi|I*+2}iH%L~|S+jbW%t)nX6~8Z{P6{vJKdq)b>tbi^vVbWqm27D-IF?J zYEj6$W42v=&scNcWD>B}&Kt0%3^zlF^qy>2Z@>wd=antfPjmWpiHb472uf44OfUkF zvFV%k*r*|yi;R14o6iY;gNgcV+PMOd%)L z%RU7&3;_+Pm-Cu4p9t_}yJ?{IA`IjXXHQE|yh{|oXmVyU{JL$O4lnhXae|-P3Q|T583mOZ8H=cJm+MZQhLASOhsS|CEp>tj6fyDD4Y>>4=%Ro&0AaDBFh#z z`12BjYKLV^>@41FYE2~ue!azPRbaBJ@b2tmDvwR1pWTrd zO#<6H93>c98%q7bL_#FXym}Jpz!`xCVBK$m8|bh<_*_(|dqi1~*(=)vItX35pg5@e zCXM2i>_7D&|Fc|6t7g*@!1;(cZxhf3mx`KB%z|iBM+fn~K^)Poml!`-gIaS2>c_`N zh<^ zjQ*wg)npQ@Qh`xCEoq^Z)Y}k*kTwj&?>0zNMv6FkLnq+&a;k}MO63!6Gn}7X$lig~ zdeyud zF#_1o-y0Xrb9F=q#$?tS`|aR574t*ech;1j9zG<8E1$qXe=lTRqR;8tTaQpyuFeKc~yWt!|8W(KShOAKn0gfVSYA+vS0^^l6tqpnI()tX&z zMQ-D?X8vHrwtR<&b8d!?R#?kBh!!CWrKqgwf%hZkHrrSk}r(0Z-jA7Dly>kCRHGV>oGK_rrom z=SQgT5n*j-08qynW+~6YCMbl&k;Y2UvONd3p|?C6<31-br?{Efmw7Oei9UdU}Eyh)Oh}6*xYn+vq=^ zcdBh`$7Y}T^@DWRu)%?9;AChEhdw7C{uZuStA$+J9SPJBrvr=B5+naUH(v)Coph1I zPcvTTU3rd7aA{nqQ|kWmHJ6-}bV!2QOLCa4?Dw#b3;3Gg$oa=7shRxHlhU;03{8sG zTT&vTL;l?j(*xzRRh}^(_!Fp4Ujfpuz4Epr#J0-aCB3i=dAO}JlYTC<8lFadp+^iO zy2(PJ+~&kV<|281`(x0ZnXnoEsEnf=_YPVN?`8!>q{MY!OS7TD!?uJ-U^hxPqzC zhfE!|5#!<{{gV+l_Y$qypg;@x?<@C;=(`r8C$MdVxEJi0Muoejyig&+S7&1e`H!gluVF@AA^=R&D#c-cwE zQPJ{UM-o4WIb+PXTf2CF=`d|Oov29&Wkgnh!3pLmm_VA>yezLTAPH-oyDlXbcv>5PKv*Yy(UV0W|k>#;Z0 z^KhuL^-x8~20S(FycIy5YbW4Wo%SRvxNXGIR?;;7ifdQabpc{>xclgk{IR2wOBrr+ zcuZ|x4?zugntPiWhId2e8s?_W#YBsUJnndT%~Jg#kDAl`=O5~^6AgGur0)d}>SEIy zYiuEFuy>%Dm|Cpm9(a}&R>rkMj%7d=_;v;L(Lggu~3d9^CJ`wEJ_|wRnL0kM$HdL^q6Uc;b!qX90!s78Wqclp38@|mE!z>vVs@f4|L+Qd zNcQ_29VF-H?JYL*FG(>#*!d-~M#K)aVGZiaxx#n4nVKW=0_jGL9;MT{oP{}fO*G7; zs+w(>cxo|Zg_5Y5VZyJ=Sx|9IG~rotUoXe<)x(C3DeGfyPcJT%X#v7iv5vU_f&uFG zZV$oLv_pxLE;IYQrCdt@J+}VlweUzoJuSTQf9=;RN z4J{ZqGW66ch6BMUN~!TzELnQ}w_yAaH+2j9oASlO>%1#$O?U#CIsT(X1f4h}iTL`Z zEG9vga}d_k=`~Orh_eR>Usj=s>MWLXeeWc>B^Rx<{azfRL7E}BHCb|TFBZ`->HN(D zAC6fv`QtiZ=t6O5w3Ie-y=v()NY9>eo560SMHm_TJSXhRT@qP<2CUgq56{0K#Yn3z!J%xW*xA9(Xm zG+O7@{16Ow3VluZsOP|sra*i}9jfizUgl6O0>ZVz;xuZ^x`MM&TAQF``pgzdTgNrw zCW;iZ*e;%85uAb>R91Hti7|2ydx@c_G$Lm!;$t0CT(0!~>IJH-4{zLO1lokr#CDuy z9taNcZrHeRfm(^&!~*R~`i*gtFGtf4nC@7$>C8R=ry|TjfG(1q6q3e9(XzOgL(&Z% zc)3NhhyXzH>4>($Fweb4sJ5p5Kh?LwsMMBHK479yafigEiwo<^bQ0iE6w1~OwUYi| zn%X&f5dwAuxd#Apb1XzQojpb{Xv{SqQ%{SJ47dxFH+E_CfE0n^5LgaW(JaUcXwj>Q zAS!xWuZ9GxD)K}Gq?AirT|&|f4dB3Et*|IjVyd-VK%8Z5A@LH?T)O2_<_72vUCNN! zk#8m8^sPqC8=(b4sZ|~&K;&|#B%oMu@xD5WH8wFAjaRV$0OUj;P%!x+P^y61E@C;^ z2~(9`;%-?MD$Ma3+JedsYuiw%aiC6liW-}Ou?=jX^$NgL9uf+$sdn`XLhDqf zB?*&n2h8f%@PDq)NN$;eHdpEg+Dfn|Jnnr1C{%Yci!%DTkRhiyTVE3X$eNE)*GclU zgfJ;aUgF$kT(Oyo2Q3#d)>6Z7n%pEz*&eIvEx61@ZC?MXOmbM0H)I zrgsFGIS&fBFI|>99DZ4AOEuE&B(X_uZ2th*5>`hEMlE%@KuY-*nd^FmFKJ6b?=Y!b z88?`~UT&&97(plCERnAGsH*U{}QQ5aM-UL$~M)+d+02m1YKMFeaE zW&Oi;gaV?`;<_cQeCZOJHIg!zWg5YTiQ0cs*{Geu^A8bGYQvYz6*f{FrfN}TWx=Bp z%T2aN;N;na^^i8b;sc^8y`z{4sBC7v5%f@d%w2ob3X4ZxM z7N!%Jdb-O?583AlRdU@iWq}R=GL!VhSa+w8iQ4`+x+p!jSRu%Et^h-eK0tttKRcTA4Ch zS-Z;`fr75KGU8p~H$eTwH}(GjFn{&@&(f$5KnN+0t^xl563B8It3=PmN(zX>oQy`r zTvG{*Kt$64Ril<1Mw0TL{{Y0UhMJcUTIb?Bsc75l{{Y0;fCG2Vd`c8nhk_w@8Ohw7 z$6D}YDB51;MPR$ycPxS(HZd{L1GVM!Ca|En%bUbosM6o9d_vwEO%=6se8Sib8DE)S z7OvDkFd9m`CDK>l?pPk-p~W65F?n%CdDJ#Vaue21nT26l>OQk5u`AFVM~Xl)jyU32 ztph?W=NZ%$szwbuj;`Pkf<+neJV(HVQV!o8}j*sh|`nwb_}pLsrUom6dv01T&AszAa2B z^0EoOtae*CCVCFj4O)A)eySpp|clQ9n-8F>Z?(Py2T!Xs>hu}`|#R={NUnIEu+1z)Y?|shu z*ZEHGujs3LYHF&wr+eCp*TvTj0H(aOoHPIm3JPEh`2k)x#k-}vtStZlIXOlEA^-qD z0boEu0}vo65ki;{{3ka9LfB9+04PZOClEuy{euf2nB*@mhhX}@JkSu#0l60y64yb9 z6M}IeaTkPep#PQgN0#*$*ni|~Krl)XGyokEPeaHM1^|%N64#NE0{}EMrCAi&1^%e} z5AT0s8960YN={Y|c2;fxCp#y*AUl^JI}arXryvivAU8XJ<4=Nv^B-ad&;v3;{?&O9 zqFnZ0JORPf;s5IMM`yafm=l5l@dyA|NW{*`!44Duum1B8CfL9D5Q3o+{^fy!*aV&M zul$!k`H9H?=n4<913K~Fd~^tg`J0aq!LWZZIRwM~<#_|a2#Npd0|$9F;$QrytdRa< zLI_6w%g+ko_e(?o{Nd$=;P}LU>rNPg6aM0N5S;iID?%_J@2_1P?Cel^|5F#xdH>c$ zH>AR0{^B4E0Dz$2f650?i13eHf5brj#eZ~zD*7)ue=#H*0P|lMw&>q-(1hF!_cxye z!UO+bJP7}V5&sJ#{TD|5FO2$M_|NlNM&APfBN;-g5Nrma|Mz>r$uG$Dzu%RA^FI9L zUyFkUVA25q+kexL=pTFk#K;i(Prd`BT=pS$h`YNv0s!3Hyqw&SSLT1me>C_*kOGDJ zw`?yUDX72rk6>s>dx3}n^g{l?{B1k%kTm>%VZ6Wi4<8itzjB5k3FyE0R0MJX5)l9S zz5aJA|D!zQDX%L4NdO`|JOVr%A_4*e5)vXZDlQr-3JNL_HVy_Z88HPp88Im-B@HVb zB{egUl$4&2ftj6yo12@0PC$g8Q<#;DoAZwlC?q5#R1{P~G&Dj^DpD%W|LgGD4ZuQ# zXmkMsMGb()f`Y+FG_|yKboKO2&CD$>?z6+m*h%(5cQ4eN!1g*)y7h)2I0 zkV1$O*71dPUD?lY8K4}gU&}T0@tLV_d_X?DIrMDMNy{a@D>@7`=FQM_xzEv75P+(W zcE7G}6@GWqOsthsj9oRi!FVAZ=uxwXdO5s(p8u^Gj^;)XnURazmMXdh9bh67_X;ST zj!?Z4cw#{H$Ia}F;VDMu6bCf|L?dGbQlxuBXLx7IhQW zxepy%B>;E=#YRfLK}o3+$KFRe6;WN=m!%_IVKpT#_N`vowrXDK%VD8NCt@Bnd&3{mM#YvffQqG?iAzh^LAhTstT_27@ZnP1$jC!Arhyn+jE_@Zl+Pd z?a^MsTAe$lNK^&YH3&Ws=3Wc2`g1ONwzW+hGqrY5qPG?&kU{hZ!?Ufnt&qLE?(#+! zv#1_uJM=yy7BR0;`+X!R;ORR80>I422~LIoUJ*Z3%J-f}yD{*XLU`g0vlA|_bMym- z@^#~uud~~H5H^jf9-(sx#%19nmx`^)*bh-%7oU6(-iHsfK$-6`E93#!M5Ja|3zvl% zzgbL+GY+k4X2zi`Y^_FvfASjemn|Rq?<#%?zN&WjlQgec%dEhmishd|N^o)=4Sa*w zg05Q&6pjf@OI!PgYVzD+4 zSpG^VB%f3Eabm?uF)k0ZgcY1_9?j&)kb9^|bfa^as2}xnWoC*xo5C!T5ur%ByeeDY$A4P!IYgL@4-Z8q9&WI*?JqfXmAd`_(jq{)nH^;R1oh=?3~ z)`ATqCAL_k>HaFVj{1#nd898NR{Ontt)tSMbbdMaF;N)4J7H3YnCGv{s!kns1z*Ws z!TKM7vI&u+nD*unCWY`q^k3HT+%dpZ3%W9zM<^BaD7)`(pi8$h%goJ?MHFsQ2jl?p zGR_A2b{MX7%jOe5y(V3CA4GE;iebbkcQe}Iw4{*p;9vmA<<^~2R8|F%v+)Im8D=3| zz#KSB))MAK?DBjBJM|V~^(+bSl#<`BeQ73M+fq*se)MH5#w(z_>$5>iiA;SndR%2CavTKbX5pD(klS@K$vTb zM0cyJvn8Sbm|}!ex0VKMEdtMBfh=7r6 zpmNM~ChH1`klt7Guoxeon=fY1@N|nN1z`$fxa!^%(eT+-G;|I#Bb3@%UX9z1P0MhQ z>mhfr+lA&9tF~SWx5~vt){^M55fT;*Gf{R<8rXi8aGE1(p=&Ll9)iL2w_$m?o^&5_BPJ&Gx|poNmCyaMtmpEIX)R$XBdzbtLrH+@UMz0#?6Si^Skhh$$@XKGH6>SRnvr7eo~b)pr1#e^EZVm#)BgBAoI$s%feFR(y$}jlxRl zj|pk_!ITk>-tl#>km2WF4*2-=-DaC+s7$G6DQmCo)4qT&)GgjSD=?qOe2l5tZZ9fFjLql2Mqz70NA9vy*l~B0lun9DgQvp zrkND)YqMDY6{%LD?V}^TlEE$tZLq4MF9W0kFPYv8EYIawH`V#?t|U#CR4KhlhUF-V zbJ-C*=^a!S7{n;nVI<%ZdGBYixn!5JwV?TnD@&M_H|zl$;j%igpA%GRWMH^BRM-DA zxP^Q>QM4m+*gX-Caf!`lz|kJ+T&o-=qEL&!#5%;(bih`pMExchDb6gb6`6)|>JxZj5di|HKw@ zoZ9^Fp_TlzF@i zRKg;4j3+BuD0ZPRmZ4<%jP!E#>)ED)C2}OOz~B>=vVr$@Y$tsk-qPag-MY|Go6abgRub$;cGXwKr%v7tScTc zIs2U}%Wby*H+dTSvyB8e=c4|+ejn0^s_=8Y>n)i@pA|kcZq|AA zS%hJ>`ul15;=cmkybH@c<)(w{YV>`3&Lvu7i(br0@_{|Y5+=kaF>tVTpn-MUipHPu zxjL>(e6NE3M)HOGUTVw-J-u3dv-AXelT?NZUf4LMRXB8&^vve=i6zsk0P7u;79q)J zu^SD;;(-R1k309NNh3elmYza@FtegQFL-0GfL^h(6yqj7mf=ByDv3~%jC~*BANZ@e zDYU?uN%I#uE%UoF;6~^7SHO?rA8B}f6lgYJ!WjoaPeaXkFB#pA*2sAwNiaXHS{BBh ze|Z*j^}u9R>?=U!eDbD!*sk^?k@WHEcEYo>VfJ7i^lERd?Edd1CuxFRkVE5-&D_sz zNw|l*+|crcDBkI=NL8(gwjf!_vRqH z0*sm*g@x>$3ye;^iDl#EKQWfs`7Lhvnl!Y;vD%J)LZzn4bwc?<8b218{|e{|vpvxG zpn{Wb4o`92t}UUwC2G2owPCqjPGWEruA#zPUTZ*Beh1@mfh6=rm1DBlMt8F8SFOQ* zBwCj~ydfz);qiJrwtS9pOj?lFD!ccyEi=g6VOqNSCu#I&b=TOm0k_~B#I0yI5ufvm zjJ+C^&e>whOi741jIG%p!1A1c$4Dgc1q(pTkiogFdbOZ5(IbuGFOqir7wZKin zc^^D8eQTIu&8k}U_-!H-)SI*#`wJY|`3gWBOn0fP;*}0+u{gsgP*cE!#uYPyyO~^mcd*7`DakA2pvhEhurox4nNhC z#u7cgong>PB1>l?Ww|TA;iSz)Zi1a@ze>|mwv+t3*h`2lm`QgwR_aYP?6i%}Fk9L& z)m!+5b@r-BhfYQX26qwd8xjK-v-B0D9PsL_XV&6ybDlf+vN~z=d0NI5H^3(X^$XUf zoEX~=;8}G!3!}33p_2)aVGCCvLz|^Jh-a@+`cYBBCBU5RBKUehrR0h4QIM*oxz-zM z6f@vfMD&!@v$|bs4*X;4*pW_)jj`4#6!5VY6nJ^R+|*$km7)$H@noH+Yef)7cVS}C zO41etN?>`)Py}w!->j~J;Ih2Jlhu+!5Dd37He!oSQIB~VtLIl5fTfHA2y_d@zIYMd zRi|skmKv=R9CVHds}GM9AB}i66Mpn-kC@1b|4MdL`a+k#<4#I0<*`xLTSUiDu{hD( zHXWyiUKBaL`>sa;|2|?;OoH*!U#yJ25M87oT*c+ylOujnhCpGj6q44=!45~kkM*2LT z5IxB6A2gK&q(E(f@zZi8dr{2+G(Q^Wk!5J21O;MPdi|=4u5TZ1$^+P%{3Z38LdRn1 zQlWIuJTdtvKPvw?CmYeDy>4G|SXYf>Zr)KA?G)7EC^!6d7ed$Gnm(nLC~`i?TP6Ur z{Jr=~WtF-|oi?jiq_RU|=Ph3Y29bf@@0mTEVMLn2jhzsm(42zCMhe{Ut&44K-Brd` z2NWMDr87_%3-gsOUHtgXlIMNQ9;_GxkTgVQX1&234SiY(|Im6Yk*C4PP1N-Ba0skbCp&?GgH9t6~laZuZ!H4f{6H7zGcqj5?52ASmP5OG)I^LDV|`m8Nw zY_v<{a>N7?QEs>$zmFzRXQXDLu_CSRR|UW{F^vn0Z5jBpsl%)LeNp64%QCHj`NcC8 z*lSuW_(frFxu$(5CRWMQF*+JC)80cSj(|GV;ZE; zqMM?llknC#At`oFp`V<-wre_PR7Ea>i!xD?x^%+FlxV9;_J{S^aZ=87^Hnj+=a{I) zotKryi+CCfTuwU@aRJff{i(n*m0Kw%okaUt7F>)@?41|)^}d&HVz)9E`H23wYMM|| zxT>%O6I=EeWzh@kxmS+&|L{6~B#03DxOh zfyj=^&iIyI=1eoqIqREfk%mZP8%HOhSt_U5nO8ivAv1H^!ZWi({~AU0w<_H6g{uh% z$1^-dfuE*NT!+~z-#iACc-2}9qIFhfU8L(%4$^X@`r#xx6&73Rk_hy)*SWhTeP;9; zy7}#MuCX5O;ZML|eGlQ*zXF%g3mw*2)r`$PbzDN=|MXE!bCkFHjS) zM9Wbj$8>POMh9*9PdoYBcAt2)ef8mZaX;EsQ`d-s%yMA22bx;-g)&8q2EqMXvaHyM zVTCl!LfW*<=o=DUCyz2UMAf#2PVQylt+vVc9wSrtzNuEA(M6M@v#&0OwkGtu7kUMb z>x7AKTZo3y2KkSa&Pl6STY)0uoqcdpm-d5L-}5}Sn;n?CvU!l7Dw?ln9)5om5YSM% z6Xn1eMv5FNENP0P4y)1exq-6KJqw)-x zV>m9#{D9-lIQ33vkE3+idBI~t<%0wh*tF2HXj}->G^T1XX{Tw9uFR+%(a3A!q$- zK@FAC5>__P={svd7|fWE;nr}Sdmk`DoU-qNSj|B*vHjuFiV;(PH^C4;T4*!y=;hQAep9ABI|TQS)3*=v!=)WtvVC;wNaAt|Yf)jjF3#`DFoO#0j z`6&+V43)2Dw?qdCi(1bT7bjPU!6-IPe7zex59C`-!hHDI&YLT|vQ*aTq(i@hC(~yk zi+&>mEdZv8NEkWP_ z0>Y~!11zPwW!jj!V0cbnlY}C+RznXk!hweK;?6F|lAZxeo#MJ9y5X6eSl{unT7~lQ zg#^-|%i0h5=JJ)}l!Ahx3+VPPDzDOa>Q z35*wVjZ@BYHHt7R?qIP6JvE9=w|G;<1bwvIFpfrR{B`GXq}2BF1tc;e$w)Rb&95c! z;!kgEyZR~RaB1%A7A3#PQG4?%AkON?D#b{v686Zv_c>WV0c&9r$qDk0@ajffYDV-( zc7{AMDO?ReK_opC$w_Xp-&Qxv?^4ly4~i;(QXk^`LGh*+V`&Z`#(V}2umiNnD(!p` zni#l@SFv#{&oj$CD!kjVnIo75u9>bqNfYTDngG1@dWc+}Y59m!E%MHBDDFQZ!96e-`&BVDE97$|GDxx*dM9@oH!( zXzg%*`F8v^5tE(IIOLZ)M{coZibFrl8W?YSRLC<`OHe z{^vJZT2{L~L*0Pw68-)IX1zOq`|2lftGAXeXPGJzB_;~R)}a3n;*H-=Tt$W}MYrsR z!gbuyyB~H5Esthkc0mD39?L8Pzdx}I^vPY`f|T-J0s6z!#Ac0?SqI3%-SjYU9ZUSz z!`(2=+Xgdbg3hT-^=;2`Up1@z<*~iEBxKZ6z&3fFI-YBBZ(-bD0oQvKhoXd2d9gcv zW_ir0`-;(e%KQ|8HG%EX+LOyEv*~jg64Zt{vQPvx&4k)J#-_Q0@e?!4?^lL}V|(HE zq!`CI;$3`ljS%3=`7>5WE(5(;vsh|>m{O4w&44L-9C5$w<3g5A)MpjdkERfUqb-fC zwP~DsVtEs#H7UxDmK%gcCB1AFMVo2^_o>T93yhe5vp8b0{Bpp5+ux771J?uCCbhiA zLmpAyb>mYtk^VRX2+)H}G0)drtaDZ8g&Qq$gf6JfKBT*-0Ag)tE6HWQ@rF=SM^j|w z$W3aT_`L9dHQ*KaJDx#Y!nE0y5eB(K}UZJmmL!PmIVkKy=gqzfCofGh#!FpS{ zN={UAJGsALz$g}>(c{;vTzsQDkCVft<04)aATAs_fUdMk;gsO8ZJDJiEK|mj?pI)Y zyvVre+dA1O=#^Hi{AeMwlb)6CDru^-{wSHZ~(A^^Km7`)nER<*>Yt z)jWEM@`=9>GCjUL(0>KkVCpLyh;a)!DZ3^Ear>Py52GCIQFVAPkY?@OE;2up$&?(a zch$ghq`zru4d%1s6y^s!kdnS6^Ay1y1ASAH#*Gzru4r5s^_cBXOswdBF$y_QrCq9X z7Kc>|e!@KBBf$SnZ9y)Rdii~F{kPb&7ToUDeEm2IGb>&lS>ZL&Z=1Cfw{}xUQhC1x z`XH=}+<=lFRWuJUhO5KO3-WxmASr+cnTo^JPcG33nUq1fOxhLa4YwQeRqgrYB1uSX;dj5j-5=*X8qjn?vCce2}G!h0L7G!k9>#k76w z9$XLcn>LYO4tLY%?qMCoz^i6jqe`^LC+29j2k=KgrbVCf|%Xqy|uk`Ot z-5hp=ysJtj!TBu%Iof8&bxBVrXa}Y&c@QA>OS5R#>IG;^CVUr^%$gDw+)J(kv%p_1 zXkdGEENxpcnyK4AaUt6)MTwKtjUZxMkjz7Kf7R6<*he%{u3h`vsRwnug(RE?`)8y(w6j8-WfyxBjS1VslU9Hh2{1Y&@CEq1`@@e{_gq`ML78ct6k+qmK!UqVrq?6 zL_C;{%Rw(Y3u*}x3`Ba9^9sOxQbs4~*LTU;9tFMv%qnT|cb26iofTZygKDVfpxy`S z0v8fZ)?dmGbPRe7|WSBC*{`Y z8^$1wbN}{mS+u6FAU#7MZJL&Q@|h24x3sjjM$zvEs)+DMAMbnyyfl{9>92lYCR#)% z(hQBO(q6EiyQ->NIgJ{7ixp=GW28+syBEimYVganspzA{^oOz$!Y@m#ri(j6<~=aM zpB*~1x#b)kVWX$Rd+f}E#ezWF@42xm@h#>g-t3cas_8mKgJ4S5Ujdd?E;{o%73M(0 zJ|?)Y_^O|b?P(VBTr-KyQ_53WJnb$d&Cmz?S$7vbP=Z&g9Ku=ITm@1#`z4(}D`R~m84PPFr@6E_=Ah!44=A5FMM1LKA&?xTEu@Rie`+Cb>WC4By5VVvBZ(? ziI2r7tw7|>wHcePaxEUT^!_zT;sO3`D7l2OKtC%mV9>==mq$uWP*dD3tlUZOIoQ43>+$uXo z$#JI(?A7D<|pDOfrAYl+=>})@r?Kki72d`uFLuD z9lwg#dk-rkGiOQ9y3HsK7CODpLUx&pt-o1*P3+N1PnY&W22kE!<;gT!W6F`uG7krL zdOz9L*O1;RVKtp=&6+<=a;ab>Rw4>50OOe!5Aq;8vH$Kb`mLP{USHKv95$VaQ>4R%lpP*{2-KSI%39Q=)5aJhx@FLsuV>b49P&ZnVAXm3+e=@okwWvHZJ=C}sBJyi zW6ZCwX8ftbNOu<1dGS+NHklJ4FVqFolDXPTTYeOEJd~ytMCvH?BRY z^H=oN=(1&~Az^ZKYqUuD?hg4oQhX_4AGb;>wFV{qgy`j3(19T7Ex~+VSbwZwj^IMR zo)=k3a-n}D^0j(N%T=k{qf$n8{JUl0T|y&)$@xyv2?pkDaE3s(7RHF2fUr;Ni&lXr zqDuOEQh_^vgk?%*(z;SW@PQ#l_!IZfyVwgnLamQ0V!deo_)#}0jXC_erqy!VghsYw z!lo8q26V=t5L|K)9;qX&@aRUWy`6uWZMcE+39I}1@Y(S4QFTj)R=y`JR0kIG8aR~? zic^tAhAuqlNN)Nn-Ap#F0I(pN21g4In(KRR<*xFBH?dKBtON)YYXgSo5>#jRm$>%< z#_LXAgu+>F9+K)%zHAu}reYze7^0-QNF;p0?WZ&HU&IE?Y zHACiC>ToKw+&NQONh~aLXVRt-D8a0wEAYK38+&QYL)Kmj-m{cc551Scq*TY;M(QvC0p# zo7wa3*j4{Qc__x}s=t_-XdO$T9Gn^?BY9nc{s=`Axt(9vY!DOjviCuFkG479!F0l@ zVj)*WzQfJ7Mb4RL3szlUC_P;khGH5kVk*68W@JJeGzWI zsR=V7z7qhQfwj_CVRWe0!DW3!s@Ouo`V;((GY~mQf7B6rnA=GbSI;aO&MmpVmk(%l zG;XLO-jXITJ{#ksyMQ|`TQ{P}fFF%vkDxMba z$3tYl`70n|6#Xr_Ahy^Q@tnb;y+s6=ZWIB*#$iH6(Rd#1q}JZNjC+jiv-BLYxY#Ie z&KA$W^mvsGCL`ozMSRS_ttFj^3Xh3KoKL=Kl~k4CnxPDdwB+-=0KWi8EZ0?g#~#$F z4zGk7V8(I6Q3?Z<38aV-=q>9_bn?F95sm%cIo`bNdgB*=?_c=CCw8B*HQj_r$~4y3 zYysCp_{p9@K;Fu{YAVj)J7F(RujR@f8Pn|5N*wQTvc`lE5@I(R=%}e91yi}X#2Du# zK3i-Z?`T)bNj_Rh&c&m z5GM)ZnY}ZvZO&Gcy^pw;<3Ct|EK3{K9p7`x7`X`PXl#CrlFPN`H=P8y89mzoTfrL? zrz|_}+F0$feuEzGOQ_q(9i-P52%)9%!tC&uLDeRH5sKD?PB)vDw(uLf+zsYYKQi4d*04A45bd>1C0 zpy;qsY9S{_1e5h+OcoUQq4*=;jbMK-kzJKVMDQizs*6ac4O(D7@49Z};Fcs6qu>5g z&=s(T?(9^D~lRu`vN55*oJ?l|Vy{87YFBE{|+`Yk~MH>ehar^j7g8|v@y6wteK7g_ z;8#GErqjftT8apq-J!P5Z5gRcJe_?V6vHxJELTRq@yV{9e3J^SF==3e4w03Deq5wB z;8dw93o9pi+WLhlg-n12_FWogKOrywIw^UlI7OAQzV$7Ep4CP|0XkOEI~oSDvFqYT zxW$$Xp^u&44Q#%7!NNV=i-l=m9Rxs~qh^3&j#FeiI-`W>*K&WP0BcI0ZI_OE0tj?P za%1vso6ORmCK*U}*YkBP$?j@=@&Rg6xZU&xkpL#JV>ol+7Jg+>3rQ0HE5O-yKjZ#! zOVR2F7F#UTDm6dwIamoPtGg*<_npUORVyoEidur^$<+|6!&4^6ngZY`8S6ScDDr&d zv#{G96w`+`I2H?f?3i~byf}iX`8A>Jy72V)b3ISVGQX$rxo{}erybRjCiuFWytC{? zc1P27+-3Rsf~&S!E6$1~i!A6C+(}Y@RYDe=At*Jucw%2Ya)MPmgcc&heKc(3TV`Q3 zW+J@`51Buo7fM(tJW7jqiSr?{qXf`J22|1z7x(d-Ti9_XwUa4x-RWSj?73_uHLO7v zVuGZsky_@t_s})W&QI>U&Q|$rKDH~^bFOdsqL`;VaNkpF)9jpaa?K><+FY;*s%I4E z8?stNljp9JL&hDaj>SFhW%qU$%x1}Gw{e6phtBVDZ-6jNGxUb~HV^*!U2z&YH(OL) z3KkK(@!f>eO>C+c?Tu5+@lw>o?#^9lxD>XwoGX=Y?A zAzj{#xa3*jM(1@Qrx$vc5=IjVjuVE-kK3syUE7Q(Z&H<0cAH*KkpsPl4rX>if%=&$ z^OaXsf{u;)?7VnZ|XTV%&TpDU41m1W_WOr=OjP{O$f=W-$*7E}eR=MM} zO?ilTbuwe-aUvn> zyqr2mlNL?wT6EsNbfB<~-ljbkw+K3kap8m$xy7~VGlKjjm!eJY%xwT&Z56W7)KP6K z&VV&xEaEKG&+U8U4^4(ReS8~m?<7jr1-R#vc?l+d3hpd`RB-eQJBlX7C7AN+qkLyC zPVEb`RbT}-Ufjbfy%c2Qlv>(r>#<~`T61_EIb{6I5~dsWenj$1ZnV{#2G3+^l@`-$ zecd6?*=j6_?pJqCN~-f;%;q2Fj$@p@iW2)B;n$v?O_Q8X6MLYVw_}X%JxNw>4?Vp% zDW53x<$EM88g&b!`Gi<_XjTCCFA{x2tBf9E-%pJ#A4K_Yq8TQ~5Vm}L7g%|Ss&^uY zCDew|IpR|J2mI$4M~ZN_>xG9k>g$D05scEin5>=fg{Wm#a#}ffZP$;6xygWvGf$>P zD7wi+n7?V4!iR)WGp^hAr9VOz7%?GT2;fr?5*@&u=dvc&-9X85@Rq=XbrK#+5|61J z1~&R;tLt;Cwy&O6z$F#TQRKZ;6sUY0x1vtAXmQmTEb_c>kUY{#8WUbbVcV>BY2H1^ z^(=E)PF%jNDeU%f5Tj3f75Bo(ikWPd*PXDVL_wajz{sl%&eBRplmBn}fsqt*P%BB|Cr_p7VZ17u_LCecP z4|H~wE}Qv+dY0e4;D}ql(S+zn(<7~`WHEm689)_cDNBI6_qrd+T{-_ysgzM%A0wOx*4?HBrZic0R~~bX-m$5XmDa{We_>=s`GezRmJ3dGkw*CrStbs+ijkh8u8|Q^sC1MYx}& zb0D&y1fFS(?o&THnEYz*c}D*tS=HhUQgfjyeVeo+-PVIPG-W#QXZe)X? zN~8_)-(rHlzBdQ|uFhUWQbh~;PHJ`|oB=*DQgb(V#M^AX+*w?F>jlorNqcGh#AD&% zT%-J)o?HsgNr@$kO!+H$P)yJx%8|QmynZlxlLp!`XitO~{yQiR>c z)i~v17HCZaJ3(}$PPqPD`Yuv?(xZ@bY8i$2$roEPyKuPy=(a!S4y2E-@ zgDf@^GF#+13mG&TgVDzhASa`C6^;9?j<)p?U+<|5q<6N%{-0u7YuwseytWglFVdGh z@Dh5@d={90E|-tnGpAy;+^dZFkZ)`!jQcyt5dY9_m`hcW48@@@+qbgzY+A?>IJ-)@ z7F>e$X~qIn)WODr{4|U+%7jeb{ca zI{0CBcKpzIr~<_5WOo@s>_HpqDITlVES=y`x0QC|)n+m`gQ>LeltQC!at#7dOyq>C zj5ZZSDp-HBwPIB_Yo-dN+`uO~`b8#&Y=7OjQ!EPdV`<9G;siUD8xYk?EQD-0sny4e z1Q!v9bsmpRAvLQY^@ob^6T$}IDbpm*Q_uW@g6wGm5bo7(#<@o?4)J>}9tWUL{CqCQ zU47rAkLvRHNAvC$kk6A?f20NfkVR?ZU$Qf zsBAFKic-z6!6cx4jTYinxh~sD)uatg{%YNPpY{r94Zd}d9daNghtrKw_ppW+5YhS~ z`ZUw9l8Y`?-s>pQ*|cRYTQ??+4j}W{F4k)G`qAvTGh>QneJM-4W=ShcNVM_zFei_% z)5<=|G;8>M?uJEXuYj@QH>~OBqe-919}Uf&8HlWJ5=`ktbw6~yrAzuVmC!c2*n<|{ zw5zy=&7CioD_a?*#8#MeB_>tFV;N^KX8c)0;pl$<+o837+TE%P#GKee_+f3^Q;JMl z`EB>nfy8^c(p5wM_)%g8PTu{SoktItoTc&%H++Jm(nr7Wyxk#aO2KV}gUH3s=_}ni zXv6yxgWRhSFhy{Ay>CuI1+wFQhx$ z&!P&}+XlIfxG0otPck)lm2P)=(~5DmvAS6@smr<>s5vd&-4*N;NRt<&Xe-Wkn($mNeaI>A`rRPm-m7LYY<2J14F&a`yL4MND_x zdEqGV&UWPZDX>Cn3uvsqmd_H?kJ-sJ;O62d(HwFjq|?C06djTX5F@=R_@)*aI`v^H zMmtmpi|ACZZNAaEU@5(tR*EkCXBNI_^03l5LrHVOvE4k64C2@YgMhFTQ^M>u;pyp# z{J`9Z(Ubz0p|-~zM-`D20#bB-u^3+|?=~xZutx1Hp2V;%=WzE? z=!6*ZmDP@%svx_$2x1i$u(Tl37*|aSK*ls6%6gZiGM6|%s?ZVZUG>z*pw^1+#Cx@~ zV>uIfQ$i$7K6hboASk#xR&}#$?%LuVu^@JGRpz4L^3|}3-9E21(f*c0kj5{hJnwwb z*mAm|y3xDIJ85Z94G{%gEl2*jAyaxPti}I!MFj?|a`sK3#CpEXt5YiD9k#cfMc?tZ z01QlSl}g*%xT#>n##WPWge_0|8c`R>5q{vlNRAz0#GBN$`}9b&nsS<^Q!hh1TNmt@ zp@XoGaHpM;3Ku?Y!m!&B+aX-4BEXM8`k=X7oq*a@f$MDNdb`d)5pdeNujEllqiI;o zBxJakVk)pK9C2iO;4fBPG%v`Us_0k6xUTTlE8dd!i_=^1kfHYg#bAorwoI7wV(@}J4RW&S98?G&A7A6p~onZx|+hf1tk6W)x%3Jsull%G zr*2)nvFBYGeM=N?j4l?gqfum}V!0`TDb);CswA|`qkB+SYwGzxpx&6RWap%`sl+ag zun2>-RuvWadv@+@BCRU-H{@&5E&0N8z*1ot8dG}>Ea_s9u63egY7+L&lp*{6YlAVd zcAReP#3|*0?322Q5NwPA;1y5^hj1uYPJEJWS-gBd?<}3@B8w`5v1=6nFgMbWru(Av zmS5yN7i{=p0I?)jBa+DpMOeN>G?zbrpSpX-aeYjB-i2G2a5=M1$XUz$r{6HP%#0ap z7Q8Jm;cBnlInWi?$IY32@g{#l+WS7RfBIXAn@5NYt@ypat5gUW_64sgk-bEjf32Ou zWZ!yxvsl6}N)KO}aB@i^z@q)roFivY@(ypnhqsLMjZyPnp?G~t#1yHuFk%z=Gp&Z8 zI9ox~2km0Kol{~9@fHUniZ9b`nPNyPUfAbbT}CR)$3jKaqZxeuBW&dchnXr6{W+WMy{R0DNj>xrzAd3wfZ$yFY~#D+UO7rNl7vsED~+yVIH!0GG5o95 zcgtGXFd$Nkq)3#UV7MM9c5j{%Q*YX$u+WnaTZ-2;L}xOwTkoZnuwM+R1r!XvI27_D ztL%mvWs)iu7hM9t`NBUlVQPqXa|G5gzAZB)UXrXwRvXv;nv%jZLB7Z6CxBm+dVYNQJgIR)UjJPKy^%uiLAJdFmHdrrF7WgR#9wNL`!Y@6KwWJ=`!q=6v zdhT>2R$6Bief`tS11Dvew!`q+TtngHfr7IOZtY$hZ)ol#x&bPX&o|;cAH9e`+$W;%d=zW)y%zf0>_aOImtm8}qdzOgb9QnZ z$mh^caa);9ODO*^^QKaKvysOEljyzG`s)kGF~$z!=V2GP9i#g~ORf{?{#Fihe56(E z3Mjv&HV@MD(=zGby4gW%c?D?A5D@YAP=5!M}cc5tvyoTM@v+3a)Qc;NA_BR+m1j2BjY zxfy>NKsrR{efR4u{ouQ9RqSYTA`O#-I>WEE;=%)rTN+2Akb!c!e8cM=(Y zLH7F;36i4>O9vb8ksGUHjL6E4wNY0u+?YJv3Bk+Tw#x^t6&1pR^LFmfTT&tjDe&lW z*SF7b-go-xUbwA`&ly6QOe`dW>vSy!quM#M298=TnibKgXa3`=KcC*iXXhK}b{0jO zN}w=p3(!DzgPYHO?JiU!JPS5o;`R0N_6OYnRCf!^N)M;zn!}GXU-Z_{5jO_}IuvX` z;ng}d=g50+uL{WyF2C={$O_9iBo?K$*?&qTjLVF6HT3MS(ihQr7dIL+Ga8T6R@vmL zb#jH0i+RxeQ~#2uv)vGOP~mt`(|6-%(F#ta>_yR#-(J`3l-;pIgA(t-rnF~cL2{QQSUsqfn9ztK=(bX2 z>D9n!R9IDnM%+Wjpnn$jBIaIj?j#LoPk2byL?zvw9(UYY+=m}vg5NjdLV;_a@Xj>3 zK-}6o3^aB`vTd#*=rS7GHOx6kX0h*#^TX9;)Q;W{02$ko%~3H_rLDOUI0~)bY}+N( zJP7*#41|m{s@}`Uzl9D00MLWfeL9c*9cWxX5iktz z?^pYRi-N-L!a_Ou?279Wmv+tuo!G@XqZ{Z4IaT795eH(gd7^!Y&?3C#>OPGPG+bz{ zDz5u(-W<*@082Sk(xCR8s!%egRc)NKP1kUF^*-Iy4yxhuSUoL^o`fXV=0Q;$xoHy{ z<`7rorsh^=SBA^iD zF&vTmgx>2+WfD9VUVQV$+$Pryyd5h3-2poGi=(^qLG}te&&^nVE80PEVE9sRO?T5j zj*IPW-`I6RTBl zmd*lex?3!wWa8FaE$;3eqVLenVxh>?pz@r&PIKm;Uwb zMnOPCMnphCMnXnKMM1+P!N$bEz@#E1!X=>tGBD5q-_SC1i19G93bE0?;g#nT5|@;g zk!IvpQdfMZE+!={`HycmDk>@_IwmDHHl-xX8y3m`>+st9$G7_mY6%7k;@12h-)@M9 zKlC3b=>Ir&Lt+?+%QM8c8{!~M^w&B1zb^jcApQE+#~2d^6XNWB-ThzJ|9?VQWO~(n z3FTnQ|8>7O7SDgO;H@@}_}g3$&wuNU9FI1G%6ETj_9x0>ipzEy1pz1lA>E9WwGt+b z0}2}QgZwk{#JoZO3WMT^(nxf#x3-XUtDu=fEf|TH(6i69ad)jVu8X2g2vN=nP9#9b zWA4$Zl{}I%9oOU?$vC`%{BsT0!aV4*U39EBeP$*&jP7Z4#4}~U$dMy73v=cWL~yfS zp|TO9%|HS2Vm|o8TM%T|-;GN)6ul5__O2)U?d(#^14IG6J(oFUMvtR3@8F@CP8RCO z{t*0O{V9cU^OSiDUD>=6k?{n*dY411@m7HO>;hpqQmPLOZ3tprWa&&s!Ci)~s5ZVYT$r{%u@;Iu6ff>B#ogUC!QH(;ad(0i4GzJb;>8QWrD$;XV!xaI z@BQ$8erK{~WsN-9D`(E0efHV&JSXeYM@b(mqxtQTJM+`*t6lZY)+-|UXlye^6wAET z;N~D}{-V?xFyt~a_=V+|S(T%WfS}SiXfok3e*Ph&&8r6v`f0S{pE}f&Lg=uz-T|voD>2Bs5O`KX6oCK*1?BGB8c8B zL0r~EM*?LMwudryU(&cGECmIdhbE-za4HW0!TP%-O1W?#9fzGh@1*0`A0IP|jnot1&>=CD7R8{jEby3yuLr5nl0xna9ZOP!ze+ zN(Ivp-slZ|V*F7?RJ{dNh~iw9`07`PrBR9C*$6Zup1}HwCEh_;-f;Y5ffZlfi&~y? zT2Yay=vR1XhBXOWv0xMY1_O>GJK`U5$Fk3($3m!eqR~qB=J06DD|r+rAUre(IAo}P zbR7EzwMwqi7(5>ttsxxto&?`P5qgJC9tnAR@P?=e<15Iq|037mpidmFWV2kUml6)k zAvPFJLqV;QKBDvQ5i{h=+7Gy|Dv&x%Cw7s+CDv1G7|i6!;7GFP9CwERJK!iEU16U~ z8P~fYJ(|RjdE%)vlX%~iYMC;}Z5BPPvNOZgc)2&0S)9s2K@XkR>-!rd(5VrFIwJH; zMr%@Q%6c-lp)qo^lbDFa+GaS~d+w`ZWQ*d(Z4bYXqIuV9;)tZqGW&bQ<*8$zLLybZ{d04$2-@~@zPkSTBbQqTouZK#_D7Ds zTi5f4&Yk1DuG_vl-zO83^gle3qx%IY>FMk=|6 zJbZ+LfA9YWK9rt?NX8nsL1MHB>gkN`XqLVfA^5i4;KCshiifFf_N!kLg-TC%%0LFp z?YX*oUAp1~TxqBItz@kAP9E*c0+DjWSpQIC(seu>8Yk22o4wC}Yvn|gs#{b3&)XxBa}a3{ z7uS&y2)RQ`^DK1m|7cHpABS7?U^lbIp62(GY1E(bF|j(->)Sf^1k}kU%BCKeXY?;z z{%-ssZkb_&(#Q7QG5W0Wbi5J))b7tJe*352hy4s`{?jF!hB1ZA?6~D z%R4_p5%zPt<%f#{pgnxB!)Yd^chQ29N|)#!FAaZHf;>gv;17Cmbi<6% zk@tAz`i{Pae5HajV@5l>YnH6T-NOOGyIeQVyjKe4ap3h!F6aD&M}K(yyP}4*6h+eO zI?K4wc;w&lxBp-egtgOS_LVk7VoUwhExuyp2}S5wW!PQ5JX~0<~_g ztv~GDxQ_sfL5j-bv-ma%96!njxVv*$)n?t}BqPX+s^M4&KAntGfWv9vLuIq?i~h+( zP1J&=My4QF^~!{$3odq&JWWommru9qB*tsL?@4Ng_>W_3@oAo)%9ICK2-fVl6l~3N z|8Ou#fpND5dU@AHvo)0w)K|3e^`Fu|ym(!$42tj9Qrf_NH|u<1b!q8ReMUXhQa#feU;o)bPlU>$K~?;rBZWz@g)0z1D>FL3 zaI15qrFBiTZ&6Mrv>Y~!<+5mE38`EN+-nvGGyBrU?MNx?{%Ml=qz}7W$^2)GFehsm zdz*N>mmc~sX!=u+H2Qmu+j(We_u1173Mn4vUh#}tTf}bA*qC)=E+hnb?8%TcInCsh zBkm+RQ{(cVaEN#PMMoEhu6jescj8Kixe$`;an5;%BU6=5j|6Pr0AFO5n1sKNX?_tBa~UByI_}Ym9{v|nmbsGabgu4oTdbga3i`Ohd! z!l*Jy!2Uv^+)5~@1{QgoO&B}MS7&OH7dA+Y$rU#~!SxSotZ$DilEH&{oaIETngnQT z=M3T8n;htx)WTL6cf<5H`1%ivD$8ygHW5we!HBlknzr78am}-qX7D5LdvmEv4^l(46UzMJ-;~@8S-&bd5J&wm0B_iRsm;I1? zpy|%0AIrxEChFKb^jiRC&g-{)gQE(EnpJ(6oCbytF_r?XNx1^-^C5LaeCr!^j_n`H zaKaKliI6xexsL?;D;n@mXdNiTa*g%LXPDf_meo-x0KXx|&+YlQZ{N8im1V;ePnp-h z!a>Q^1=6-a?O&qxohuL(g9HvwC$lm$49}bw9?jF%e3g8*J?D-=yTI=Fju1TeJTiTC ztL%ve@HliP;0%H-k04bT1iCgg4V|Ob->@#?`}fFtpQWPA?c^jemlafkSiQq{W-(FQ zC2`Mla%k+19@00G@b|`kp+S|(^8~OUSU+H7!%mQ~!{sMN-;?0MD2|7l&_2JvWcDcB z1)m|wC8?@&U#$7|KUe{L{uU<-TaIEi6l?TGu<)|>?phJcJ6`(rOojEyDTESA+C|N1JvPqXqk zGH@UL3sW=Y=Ufs$x5;$pJU-*e$IU~$cN3O;Q=|vrWRlxV{jqG75Dgz^@YW$XqmnH@ zw9IK48&JD_%k2vNdmwziuv5@N>bT$^3$2I4a;W4}I<>R+*vXYg+G&9t`+CdVwv>G` zJ(o8cUCYt(C54TntBkKz$sPT2yz2v4n_>lCRbIpP&eFQ+^O6WE3R;}ACx~JJC^+Y^ z#El`1k{h1+f4HA`Hf=MBX@UBO9_6bQ8j8NRvxjj4={@`&DldXm6Jr&n(@d9(P8~Zw zm-f(^ZtmgvU%B^k`4zC*$Z1${OsC4nF_iL#*>7@Gfmy0EJK5t&o+>qPTm&B)Wl;jg zlVMLlb2z#)Z(fgwd(AaRyA$04jDRoC;*z+YE7qi@wPd`(sBx*psVjHc+hx&v@74j7 z-Gfj0_S;vJwf_*R`b6rtLZ=|}Kj4U%oVkK+Ma7m@RdeX+TZFJkU61Y2!|v_am{Kec zhrv+Xs?%i=eZ!o{4H0Iwkg5Yw`ogy6WzI(Qx6*Q`Ynw0R#+Wipvo+yx(A}IGTKh6^GY3OmM@wj!sU&PS0cn+ zkGcW7r|c)My58tEwR_Ggz9wC4zDIWAKU~_DjTQa@Px+9}3EEB9c3jq8`&Ma`NL8jZ zs(4g=ayz;2D7*HEnQoY5yfW$XAhnCPh*cn>9S0@|Nz}PJn9X(BOiI(MFEEzzfK@fF zP9gK|j{hQQ!~)T{xz|8$5%pf$#v_ZJ#dK&5xNyeU7j@>kS)T`1eZwc359|`GqgPl( z2NBBK45>yk(@GeO(^}@zwOX`l+?f=O5qz%=D@mx*j&J(;?zYW)?k((73e1`>@?=G0Kr5U^bmzuGXFeZ{YcAszMGaY&J`h5KG> zVdfTQtu%G;A`Jazf9%Tdr9kB1tsG_O2(bXTqVgM--jAKp@q<6<4JZh@At_`drpj@vuSALu> zZWMOssvXL%qQpjU6rd~CkJGm(jf`U_mgfv{3!ik2b_Du*l^KMDj?x(U92L%pM(WVO z)wE`!7vg4{r(bzXMTTX|ZfljZ45jFzwX==ky?_>Ft6 zooe5(5%Ku_#wJH*8Q?9&5CAPOP}4hK^FDKk)gIAR<%kWp)uMrzk$O8^>(4D=%cFmx zcbW=v`eOCQDlJ7-w#zrpY4@925(F!^#+uen6!aAyO>6Eg&pKHhKBc@{evF1LX@nKJW7m)f-7YwBfKz1Y8k7+z_A=J#e_yS?wbE5vu36 z2%l7c^RhD2Q9$<#wU7QmCPWE(Q>W3H5DnovUgsm~6s1^O$LXShbN#ezx&f6CK+eOM z#RKZNkEdqu
Ao}2suHE(j_&T-8GM}8QK1F>=u>-oZ3hQ!n?0!~xn&6*1~DuPX! z2w!XX97T5+M5|sNJ&E82oU0>G7b=&Xi!Rz9+8zWxJI;lMt!`ChI*ngVJcL8?yJA!3 zYDvU3--p{L_E|$%DdXK?&FkC?EEzZKF5lz0X5?y((C|VPof@n#>)EHw&I`~MU7rOLLk*siyT`7Q_|{e}+uh?> zMCcOtK^M~rJrt?37bWjS>4L4{C4V@H(xQEHX;zmgCKO7YTNlMOHD*X33_nx|q_~%` z$*ZW;0T(_%U9x4?3L>>1cW*d4gSDLCvzIO$B+ZiV6S?yg z`}38!Zt+%Gl8@vJse2w`FlZT_`_0XxKy1D4PKSw0F+Tci4H18j;5d%$=H=vJ>9OXX zO=kr-z(28MesI%pE<@;k*tQ#zxsr-1f-^(<4$EvQg1)5o-2sVPU<-K<5tY%_!Q6-M z%k8F=<&Z*Decp$#AWiU-I-_q29|!0~+?bpz>NZUODx}cR`Wo=j6G=NI*08tQR1ZR}w9{ zen<^Z7hw_PLYS4672^I0B_3>L=n6_~#8K1-GD-?o@<>-xfkTVvioV$!@*4_-?u6em zoHFOp2L6Xod$C7e?@yqZ4AamU*V1eY+(pJ$kD}o6V5WDmzGZe`XjvkLq8p;rPtntl z_aNtOLP34}k1o;u5x#!=NbVt&g|sMTGt#b1N-J%OsBFbM7_J4kaK0g&g%+g`Yj(9g zp!__pp;3OyVhm)9!`u<5D4sSB53C2tkkHX=UJrBYF@#!)i;E1x2Xx}9h*iYf@k!6C zOqyE`-f4v9D-XEj3~q4W=77_<#y~LoRGcy9j$-A4yA5;w6QTPV8({4BbdyBBa^$rs zX{NF2uFj0+m9apXdN~=i7%B1!35TzPLzxS#3UgNli)GMG?G43;pyJ1Vl=qr{I>sky z#hISoy%R0nYv*KU)|j#Eh&3DB$zs-ucT)WEZ#*c0^H48P@4vP86Qq&EuHeI{Bwlq^S&Z zuIn9)t5>^X#r>tq3czfk1STz=TCWJ+7WYbKb>N>KkLT`?N#RYOs%dW_X+6-h_gX>>EkT1fjcFhp6a;d{jvg zneK621a*P7BvbLjY<+|S$%(7pH6lfM06BX6AEPSr{}7b_k~FC#dCA`*F}K`=Q{d*8 z4O7BCW?5?~IuQ-OC;v8mpez}Ta=KtW@K_^B9%`i&#z_at5YcDMiW2((r(3#g-OyV% zNnN&Y6vJ_!v2^Mz{Rs*R$PB%)o?E&`4itkmuHyGYP(K6fxAe^aY7wt-6}ZstgbT`Exgpf7(-U{&rRleKd(|!EjX34 zvgpcSsI)Y}>%iSwoNUdh@^v0|W;K>%-Mh&=k}wUdO#;l$H~dq| zHC{{HyDjXn-Hhe1?iNf-p7na%{W7WEIlpwTuiAK_f7ypYNkW_)Pjy<2FzTiiX-05_ zY*Kiz5L7=X!c6Z#?@?Dx(Mu$W$-0e*$KoLW7}=ly)Ai##v)dwquCTOuM5c1W_jp2a~zC<5?6q_|vhSj8EXw#mQLuHk3y!+)y{W1(nE_j+bK z|E~I^?q);DPl&@s<%FX%4qMc>C|oc^u07nV&9^v|E;$k&(wvwVp4Xg&3d6W`D-3nv zg)qIqSt21jaYjBjGi%Nbuc&j#w<%=aIS0(O&_vS1H}%qYKN7 z^GkOji9=2T=FzsSi-e?&nc5jQIbo{1agp{Kt6iNc+-j9dI}NT~JGR5tq&qm#*2Ln* zRuFMx2j2IfOfPNg=p*BXKar}=SE{#=dhVyP0EttcC(O>L=_=g}RFmH?6h%j3_%-~u zn1_i@OUyXg?nGlsFfQMm6|Q>WIsp?m?mxe+zEM@sCc#o49;bRx|NNkeN>WxkY@gLd z`E({j%Yl7`F!v7C($myD*cda(Kgm6z)yWo~6gqArcsAAl`!w0pOkP3+cptQ3O1hIn z8+(Mehnr(fS{b*H=GP|0GhX#dmTHzmsYHA?6pc8KMNdIl5hxfwNf`4@U489{z+Eu1 zWY>p$(b~DwoI>_vX-pen^jh4aL}9-W!3E$G1~XR zl3;BAmVrN8&-@pIWESE~XVu;&0~Dib)sfYx^BiH^cT zboONI?C{BwT?Nx<#d)Kp5qS@7{js2T7>voUQE@Ta3-vWj@m!7CDfWWb@7!fGUy+{G z13M!QDk7iWkQ;)tyrweh5-*N=tyB+PA>EGwFufe}2#-8r6Wi5?Pu))B2oGYly?`LR zpDLdIE~^%1oF|dJl8i2sUTfc6kcRAVW7q4V`{~@FZ z69_w>fk|4*ZOlQ3!>hvNwjoGRVSLWA6cq;r_a-fz=2D+C>%yNLN3DsSeue861%LdRMeZo|F z&`OtaE3Eo2$rUmaY#*WUDB#K1EVoa;&&D?3cVuu#!EcJbEhniNFw5IGk~+Ks&T-Ta zdZCW|>0zxgqY8rQYIJq$m491yeW*k98oB5hO0tj81yMVkBkg5pks~GC0ggtq?^%Kw zKk(sBbnnI924l|k+7Jp3Ne|qY-1ZM_3jrW;KHk}wVJ=(>-z7M?4}SIjq3auY$#F!> zjs^MNz9qACye6FpXKrVfLS$|zb$d^2^rY=cUL&S8z5aVrZzmn^^Wuy#D)VYig46HU zx~)ez158qJf6sz9cx@rsJMj_R_tLi^eN@Wyxw_d7y}Ba$t~IC~^VzziwXA_iVh}vj zkFTN7aOdQ>dXK4YtU6KzPJVX1+Z0^-nD@7^fl@G{QI%WLso>&8ch3~<$?#8sJFBNC zC@|W~b z+Td^0n&Z8^?|kY^{iAzUe>->XYs#Yu$l%S+nZWx_PWv;bmB{2^m5Mijm88;DtcHHP z;x16=HW(>!IJ;`)ULU053dg?VU003Scl1P7fqr@l6x)3C_%(g6I`aBk@=OSH*DzVL zrR)pPfGicMQK&U*G&5750FIm9bm9m&pW@gSEEGi;eqaUYSDdu7n3lcPZ7u}0_r-EB z9x|Wn_FU%4Uy`rrw@ruLJ=(sCh>&t&#Z6lzlt@*li~O05^#5MthTlXp4|#M9%oRi@ zB4O|PVuz&rM`xKl9b^&^4$5Bot& zM{90}@3{LuONOaqOy2j3NTPFFq1dXivHtnZEYw|-$h0@`nreBRF4acDr`R{Vg`y>n z!(7~t&c{JyYQyE;xuFerRvZFa#v?=iOn4VKPlyA#SagEc)HsmQJXm4wVi}XR?}l@w zGo9yTq=mM4y{3LGBLWv8mh7h23f~*yJ*p$@Whgz@VQ<|-P?gHU#DpbbXtPdBVQk<_};m+aAAa9^K<5e({?((Y65XmI2%>)CdNe+M%2j0Buog2;$r! z9`{XeagvG}@WD*OtY-A;_wOI4L!~m>?7WXn`wu%tRV11eI=J)Ix}if{ZUc5GkI_Km zyAY;Vh0Cb?6RTw%S?D4lI8yz>^}ETCL|2!Ewz=%yh8OS_C)t`Z-@-S)bH%M`*CvCT z`C@4^$Dy7vJf|uiVByXT3sVDlWB88km=J%yH9kRblt9-E##t@5IGdq>RvfKZM%()_ ziF}HZHG^DC7r_Ivj|2f}G4 z@comB5{FHGyCt~_*LP?LztlEPv|07nq}ei~P9(?Qw>iMkk-2$Lzvbt*^Aq4TzoGIe zD!KtQ(6CvVh)?=W3^3pgWtH_gOF`_9Mf<6CBab_7b%=GBYp1&_Zb$T*Iv z|5gBewFEg|#xvmS!{RpK48-GIS9hwc*CAUnZ?7<*+N1K&X=dvTuJNX;JzuYUqj7t@ z2s0Mwk7nVvd_7eb;ijv8UvnhF47&MZEj|>wEiS&+^>U)(aa0&MBT`woK7mhH!(9Hh z;Tsv+B<4>R#4FU^I?B+WvJ7MTT`!Wo&>;WnF9P&5yNBb%6Yrex670G*55)8xEqpO{ z1$G7Si6+dNuIxoxo>wTM1UB0CUBlznyhY&bg_#9A2m&)l!@(bldG>%`4wRse@t{wR zgmwNhlCgG&MGsnj5QN(|^Kglip5)`j``?z?w=8I&rb)09lt^Vkv+)%?e2Up$F1`YU z=9M9_FZ}+zH~(bn^ny7w67e$&hv*vs#L0in_AqeL`1Je87v+#$Y1_H&F4%{QeG=Z> z8esox*_$zQZ zF$&_MA5eV^Yu#*I=QeGApjZl;B+qygon-;0W?10~78dgqW19=Y?7La6c`4|VJ^Hv2 zrfH~a1r30|FnmiKzTN7Q^Zhqc!(k7Q@tm8E5bY*ja!LLig04*i$K1OTZ*M; zV&}Pe|Nju));==-UQ)@24+g%JNNP$c7mpZ&?U{*%z$qQR=-_1d#u~mMu}*C<2tT~S zSN&`S-&~%HjdWdM3WvdqZf9**GUjcGkN@rY-(gJQ*lB93D;-r@tD>T`p17_nWZ!qf zA^B3%l-9|%yBJr<4E_Hh+;6}WrcD1+0)eMX;d(ItuUPJ%5(pMH$=%x>1ubGmFHY@wpvzaD8^J@h;Nyd*qIGlOc*4VVoD{Y#4~I2M_mN z=>aGxWU&Jp654l83J5iK40k6+=d$ti`EFbpy*Y`x(X}rBL-@R?OBU?}$t=U#Q z+`i@Z6mPC-$SUh!fRz54;$oE6={Zf9L8NLpY}_l8tlha(*0LzdAzcryb$;MieAIMa zzETVc#8nu-`#ju!8U9^>a{^qu;7ul%oZ^`OnjoBBa3W#X?>*0=nCIy)qak@lFe97N z@KO(6tu*L9PEMh%VTtxe$J-xCsqx%u=74_%oxWJbD{V4hS z8&9#~%9l?$J=<*IBTOF}P9~Cx*4o`UKtyrFmK<3*9SxsZVvE_IwdY!}<7X}k&^U=O zLQ5j$i7?8ftYowR@Q-w|#kyzd4S}+Uf|ZN&{iG`aj0FT8b%gW|jJwq;Yw zrc2#km@+SPqsbLw?`YLQ-_K-DjBL|q+{H4wWh(>uyr)qP@9 z>UZc8qqqM3FA>!S)7qDc%C8}A+9G7D=CXO(WD)QNz7IqLuo|5ZD(?a1&E{J*%r)Zy_zD-s0 zy@eIJX4w6UHp{?Hs3Gr!?=i70k+`n#lQDj*FG{s+$mMtKWjsKct8LnoOs|IVApfD1 z!peDE#!lZud8Lf)iSy6@5bPT=y()9kVAg2?*k_+dWWV4!+9QQY_UnnJ6)lS3YE#SW zskhv-_%{>?f>?J&QSY&K3?vf3rOZ~srZSm+Ox`z@$vdb*4Fz762}3-A!>VoI;kKb; zAH5dPW_=)GSMBaPY__V898ob@x{4DvaWEBeqLpuv_`WD`NR)dxt@LLvIfrg4X>w3? zsd+c%Ajto-NFwmkqM&g6mTt!}d}unI=LwB(O=FZAX3-TBU=cO*9dA$dN<-({E^O5Q zQ*uyAS9VIr(ph?RpI+iQm6irQx(m0Vxyrhiw*IxZ3AZKR}cIL%_Fr06$~PzxG#%`-wd? zlvJ=1C<_sgW9XSmUTo2mBbjjOBwbZFNO%AmC7*4^n^Q{}+$6M$TB$YCx!8O zvq|7H&y2+-+jbpl@&Ux7;qO1+6yRjk?gksrBm}{|6c z?m^!oAiaZ&j3L4m>HaNm;37qE56bbG{VO64r?{FrE)|!gnS_S9OUVDc=-dD6MVFFw zMvzj(>N90w`T$svlGK$^hDfa6WkJTZ#h-?!i`Atr`n=5MSikY}KER3b6VBwFUJG+U zQf6QpZO$pngb5j5_IY<*Qwwue%Z$EmMki)d#5l7)2S(y<*D)g#U#c`-dg4^@CH-H# zr}>T;hU)U71~`3RQOt7mEbkWu$?s8oRhN_@W9FChHvJv4teLarunrChdSWyH`0m+~sPIVxor0e|&! z3B}&3ABilPer_>j69~W$aBU!kaUBGQi(*hjXzqIv{0cY?-WgA=NzYYQ>IvQS?G+6m zG<~C#+8rB4P#AVaA!Pb+W&FYZflX~ek#^1qGcSE#G3@21}@vuqz(mHWAir3Lgrz+_cWR8^5yyZIq5VZME@ zRcF|8+gAFHeZNSDK8WDYo~+&4m2rDhdLzCc%-?Rfe75Ok8mh7*G3xz#&nbkzC!A^L zb416=ls|+#$sN3#$6-fHJdW&V#hjto)cCaa>%_1$8~<5J`>oGaQmR$PuZg+k5~w;0 z?OfWaRUDCB!qBpnKXc+gprqEvC_8=qMJr$Ch01tm=TeRT5cY;v^hNvk>C-dx0hy_z z=oZXfkis%)e38sf=;qPUV9JigDf4mga^RhC6(h$*Gwb&b4*A4Jlp{C~MY^L2t>?0Z zKa*E=l^0`0SJM43s}Z4|!6&k+77*YZ-lYoZ)H254%_NejO`MfV9nQ<9^g48yxh$r% z_--KOk-LGP(@KQxWstIXB;u-PavzYn>dTRpWfu^O#-J~ip^TS;FQ2)|VGY>#)q(v1 z><%gh;_60pG_F`Tf36&BT?~SEUXZj;hKX*jmRYr4c_#;1??}+w@wIsM3cX7|kLSqE z&q3SgqGJ?Wi-C7)PfWwL(374q+GXQ1dxEHE8pVb-+Lf8@hDNxpa4+!B2VfI(XDk2T z+X`z2es6JSD=^gk{hvn@{GaOG8)PK7@EsE3ze#k2H=o|ZC(yAesW`=5-?6Kkhj1kq z;z&@tLAJhXgr>}>nOXF?6wUs>*>q$v_-y)Sf|Yx59_c=Ng{s)CwIa+WuW0+8(RI9( zM|#Y_2T!s5rMI8W4b?w`SN4@Wna$na`F+GR&RTYv+>Pja*`=zU_KnIHB@m|-h)6cj z_PlE|Y%oaeMMV|%S}#4IH|0+m{xwbNr(M+?Q%44qD5-{w z*o>LxxvG}`5F!F^;DZ3ce*R)ZtdUB}>~%4EPJsl=@EUv&MKEK}3X_P}p&nZv5k^(Z z3t9Bys;li)K#qvK46~)GWi$mCNm>+E?aq1YBo!-{M-j|4c;c5&>WA8meY*xQZhhvw zBef}Mh2^jq??_ksXOcRtss657D-*;~rvH>Gc#(%{k#ndUOg9u5{DQtm%zQ~#3}|Pc_aW-El+S~ zI|(|6jO)bPVq1CR9^9<-WU(f?7g`nyvhc$x4PWk^Q%k&NX_jXWf!4tmrRII9bV{K4 zEa=jaQ75Aoly;_R5mSaJ0?Hy5&J^OVFNqF?4@sA(RY z2_7aTfs$FrcO1G)u&NU`2)+ETC__%pZTPDQ=f(F@DrkYxN5h{}np7)@tp6&N$wph# zR(7Q*lo-l|@3y&CW*8EWjt%wiLx!Z4(!~dh@A`vG(95PN~uTK;&$ zn%;s*iqoamAXh@JQ-ThPOVTnlP=gzy?ZeE7JLE%+3izkyY ze>3+L&~zcUM2)3F!t2sx+9M@!$r34?>SSbV z*dFwuvQp=`)IiM5VEMj8+tWZz(^jN2eM&xsUalOH3bYEN2vrWJQ)>7tc16qq)}X19 zhUu=l`llWkEQ+Z_q5?8%E6DJ!HDqFYs;ucR?bA;Fu6hqa5Dwh}sh-B2!SPcBUb~(l#O#72#5J zFp_HOIQ;ouOm$#d$Kkb94@42U?M@YOq4g{ub)+c>#+KMJ8GgU2x0SfZ%3)0H#6mOq zggMJyw$8mWD|oQtJ5$;*3TMr?O})n*57IVnwUE&^2pAli>?zUm44h6er$sOHdHSTJ zYF?pIe#1*w5lwM*bXRWc|JkPV=s$#A0Q+|TVio-(c6IlZ)yUxPw)ee2^5nxzg**ut zjm8S+D3sv#n(?&TB=?|MK34^uBW+UQ7?HQ`M5`{@(V#4<2lM7I$RMWF1cu8zbYncG zc}smWf@%h!UMcAd9mu7+Z3LyPHF55IkHrsE@WvNj>2&(SoPDMP!bIXNHM-b{s5wzD zW=Idr`9!_CcN$YS%{_G0^WbCx(oc{*QYkY4Mly~fO}+aP)mq`h$j~K{gO*)+ve~_I zBV_^O(9pV-{r=M0<6!``{X!|d!h-ma9zaDt%i{5P29d~O_8_hxwWX2G(G9dEhc2H@ zz?`hcm^%6z88PZ0z@8C~2~FLoDG&GJ+&zK#Y_bTdM@=LlX^GiGm%@wU^uU;k?}F}2 zu=3ry6Sw)h&xUgaE4?%xP+-?b7ipAO+!_17p5BXT&Ed_O_;abO=vp4Mof)Y}+h%d3 z<7e)5_oO#3)8#$;bFy=?Vw?NVq~|9NYAxMEV09AH-BE3ilapB!w*WE%^KQG9wW|4O z`(zmv8;3}(r+o5BL%pjzQ^UV%R->s@8P+oLse-HYcMHqp^QkvSGU&^ni)`^{N0BZ` znprqXa+y`i1S@KP6}<#>1ZT<)P;XISBt~w=>s+;NcF17hd9Al>r_xL$0ydyhtJ^o^ z3s|*`#Y=(rV(K2V^Nn?DN8>>%@#r^);R`SlZihM+hc2ef@>ep4boG>e|4e?R+!ZFa zw(8#XGPF*6s1YISkBA1v;;Gb-!T(a?50_QFt8Wu(JU2(zGnb z7X|ZZ2Zusm?fW%9Hd_6_AuCg)WUWX0c(UeZ)8tROtgT8qqrVMV=v=ixywq8JnQp>T zv{Iw)$kZ))qASqVvAUi{%=6NDF`;(0wz>yAxM0YkuHzp)+51_mtuhDww4w949W9OS zn7Ys$OeB6?{`F5HDExL>s}(~A6~k(=bGxUVii#K&4pp!{zI4x9!!)x#xrruTWhhrFoW^uDMCV2H@C`qQ!xg}|Ii^dv{`Ll9Gjdg&a|Gy z{(k0mC>ftPGnHxTlqTz{d^&!*dFiD&IXg9Ul|oO`;m=p-bh;I^P5q*m2jMf_%rvSU znzd?^0qV5`DrZ+!6zAo#w&TuixD`I-swxfFsgR_3T~#hxTkj6=8xeH+Lxf^%lU-_< zXCD~XAH;fMUlGe_Nmz2FH1kKWVn69>X4lX(Wm(X<#M$CjSZ2%JT8)T1>Ve1nnq9@C zg`9TWOe@45c{Mz>4-&V1RML-lAtY6h=?DJGJO)t=d!z=VQAc*O4t^sFwWYGWDytZ^ zIhQHf$JFNEO(Y_!n5}6~_G94rZo&T$Bnj4|{nq|6j~&;z@=6LTn9!|E?n^g@YU*>r zi%E4z_Uh-T5jPuo8<_Mmd)@qS6hmr?jCFCP4rQIcc+LNZ@E7_d-$>@|5_@@@8OQtS<*{G_r$)&o1;8xwd_)# z#v_sRzBz^TU~`sR!OBsC&*)>tEp-&Oi~HU{(lb$*P87AgvFwI&J_H;gqRzOj^?R~B zigz<|K;Cf`%jkBYv{NbOcr4kF7I zKPDyX%=5{9dRsQb_hsl0Qf$%ZlU^!L6~5xyWmi ze@n4f`mCG&Qg*$k>YD86k+o8Wl&||-V&lxT=Kk0v{i0IVN@}L8=9OjPX&wHFM@kvE zJvdFDMh~uUd`OaVtAA(_0OGCWw_%ekO@0TthOyy!Hm1EZe zbR?w^iidP4pt54skou`ishA!m$BWaD!7yF(9HzUpGnLVZ%M{&i=`;>iDrVSY28~T= zrssmc{Blb=QnNG^pGdGUzV$QCEU(PAgOE6(^Rf_*kNUE2HpO5Sjo_jFoxc;ivjS1m z&hT2J^MhuRHX&oLLlxz_)*qO=k&=C=X;%ek9_9YG+U&}pd^&QYKAcrOoDCHGsDMGc z>dsB{V-nd$;6UI|#M^OKTk{}NOrB(smYass-Lf0frP3mUk0|%EU^=zhxFP_N zG~ds$rWe6Rs3PG;RnN`|hps`(y=FBgZHY;0DR&oVOnDirwQTWeadP~kf{U(l`b05< zu5|JHpD*K4D;_L$8Yg?itFoK|$x{hdGP7hO;P8!6fbqT85samFUQb${3zR#tXU!!5 znwSD=tRAuM{Ts54rqTjTR7cWoE}s6fwVbW{uvBBkbjA3`_NJVsq@3n$6I|b2-5kp` zB$>UC64G}$vvu+H|5Gk5_W3`A2f-N!+28=hSH174TX5?05(R>i4tNzg_sx$Dc;55W zTtqQwx%@p{p?D6yWW%XQZ<~6x0ISqTjPU-JilEYNrN@BbrwowkRlD1$u4s$0aV3g} z9xq|29n23PXqMAdjBk;aZ9ii$9SYSCVcOS3uJQV?twX}DfOCGaT&zgTWy0h}>3!mbxcI}j zvxWf;Sa$UG@aJYv_dD{;rWsZdrlyf#9*fH_n^?70RL_Eb*x3Zc-+V*xs~IA)0w7`i zwE~nbsg_E7Ox$=q*Cby|-7c=!8B`GcgsA2~0fmPXTiiWY`?rs5y&r0+E9SRNi_t0@ znO#AT8^$yPB;$yroISBcCICJF$cqEt6Q$L7oUt>8xli9<^%*UnJ0h!!{0BzAD`CjD zaj7Eq@);BJGr4`qyhyy%zHEFYoOs_gmf!FT=5j;A8 z)Us{CJs!Comf`Zb2GgQ1zBx|JJ6~M8uo#LjIvTq^FPRqpl!9skr1y}WS9H@U<{Sxp z_7KcSsj^?t58B-(r;7Ty{f81Aw(V?YC$d>>%MT9$7n10c6XGoO#;V+Q-58V4O!lm& zqsL1Zf@yelTppw=w&|{*o&I&;t4~Fq{YOx*d03iY%D_WGW15d5(YM_;MK9^Pv@Tk{ zOljB*;tb|Ic0(#O!>CvBre5GbgfH2Q;RPFFWx&~*Uf+wC2`0Tgr(7^tEXK}lmbLSW z&TAtp{B1tY@VtY)cFx|Hyc?NThNy|CND(smr;mZbt?Mc%r%!zx)L0vtZ~FV@ z&V2XJo0()zo>|#BJ11v9XP>>+dcOE#8(SycXND~uF6cA%eOL56K6*Dd%~_+zNIdAM zyVuZe?&F*hDdzZEks}}vT3+QX@Qa`{<4-)S6WMJ|`rL$j2ULn^;a2<@50KCU^Nl=7 z(P(=LFb0CxTDTt&Qr{AI6bh`~-95SR2*dJL=Zv8#w7vM4o$Q#yoJuPeHeqcxIvgn$ z=sg(6a9CWsI|lXuhJ1{yr4nI;sIy>Sa-L|sT4TjEpO=_=sgA7&iK zQt*eiO;$|dkqC(NpSmv)(R%kh#JI%X#G~|k3iTb>RGnS)Th?RmrGEKuJ=*dx%`)ntbB8XgC+uDhMCBS4t>eMBeD**uGz5<2I2DceSIQe9roeJ6M`~ zM`pXNjW_;xTAawfate59`yuZvE<=uH!@4DdmLgKhV>~%gQES;#2!HY%vga}BfW@?` z>}L4@79vN}Sh;Pa!^7fyr8!LWvZeQ>+E0)m$zEI_$TGoL6l}xb@=yowVdry<2DxQ9 zz(<%#H@7nv4cgP9h;y4-4q4v7{DG`c{T^Q#aWGcdpT218IewX`JgrCWA5RS0RXZT5_DetK`r7wcOwOD$z{=3plZA z^pW!(YMv^Z&*K*M_>RdfPk!?2 z0cTbOqEYZ>rVt<$`47Me`VP67*?xGCxi0JM(2g|Tfht|RU|>ud4r{J8EyE}>X1c?X zZwlVbh<(7-H)&6E)COnffjMy-bTauQ#}?cDKKZ6<(h8bOrZQ%|r6^c3)>ZI42Rq#( z(igl<6G$C1BmNSt){tV-U_@BU`P##Afv>1v8xN%-BAVYE{OMk?EEF(=Fbu^X+kcwn zSz{}Dt6o+2t#mx>c0kA6OVP;04f7GBSqbVpYJC!R&!lX8)n3lgy_}_`zk}2GsN9<@ zEMXWXDpR18)b+>236Am5W`g-zSEVCIE7(TjiNSEl4-|%y&~8>T%*-ZSmd`M~GLGiu z%@)wrrL`VyG#{*H^nqx@VdZ8hf$CtnQEeEyuJiMcmPbf3`klrm{%Y?{rN>Yn6BLtO zQyaT3^<|80`gh77ug6i~f^T zr|t8R*CWKxQgh9yZk$P$l(@4`F`E6Rb7g9}u3&8p*I`bzt2Eu8)>1Uvz!KR4J{@oJ zZ&`$Ony1@j1s}745A9q)LHy6^30(XHV3)bjl;+B0H?YyK*VKk5Iqwyf>EPM5G^L7V z01Uwd+O`U>tLb;;bvN=DRwFzF|H!Fkc;n7g?N8y@1JrSB0r5|sjW{eElq{-x&zeiN zaoNOW&?#babKbH~{c2({fo7z$q0dTCWI8E|7iuJZJtA?Ug5=o{f>atvz_1s|O zHVghdMQL6oicmIXR*^J>{$*R6^k#*@H?@|BE;h{U;^JK;!yaVW2+H+o5zYQF#oUQm z__X+n~UlGbv)rx#bc!@4U4P^Zn=EZe!+n>K`;wInG9I~iVO4*$*Cae*H-R-yicet!kt zq8;o7!kLHgqys8I-KGaMpThlR(7hP-9BCTlO5K7g^+(QsSv%xAxuW$rU=|n+s*lkY z6~CCT`ZBWF5LOyKv>j?;$*2S}SY5HwFs5TSQSgDz33p@-$-Eu_Y z&9iB)ebW+WLvkU1rANWorqNRMH#Z@6a10+}>f1sm(|lM&j{1hVx@Zd)vq1YoIvBnHB`|wCB4N6%&R1cy|HK#w+vfgTv5-J26ga;Ji>X0iq%^bPAf~{x~os`lbcSIPXEt>NagTTOh=E0xj z9BT*XobQ1WrFMrTkD~J&?#>H=m)h^U?`|zrGo2BnZ_JArTb}_ff+{1VZCEbf3W|~> zxmrXKk-QmPX-yg%xBMZ-)Q;Y@7|Ymw15p~69fdKB)YX;g zK46EeO0o&+ma>;JsZ1vCN$J)}W)H(WfQD(SjPm1;d?zbvO`U$anx7cXtD8GKI~%V% zN~vHOxQ4ZZkxt!GogxQCm;Y2>N>|2=x?waJS0horp%kyDc_wUp$&J&EV+pIv(FQ3= z?HW)ryrAN#xD7G%YeMMI9Vm$cld5%C{zZktN-d-}`6vglRt~sf)=++!_oHu4KJ;5# z9%N64Z#vegOz5sR;VSijt*3RW+Xa7Z;8r_7#>NX|O`@CU1Y?{@*Lk20d;)cb#vGt| z_3JOljL+6J>fdn3)lA~Xu@;3rFpElP44G(vMiVY>U34jfgmQ`zkuUXLf+aoke_}gk z5+gN0kjC4i>?UDLd4>ei*h8L0DgC)(D)G839n#+> z{f(a34A3O&KT0!MPICGPE@(VCF}H4s+&3N!5`YeMl8)h+8n-+`rzLw}m> zz4WCOaL_d}O*4>?W51~bKW&veI-?Mbpp{&y#kVbuZxw}|J?!)$^oLZr6+1*{=M*Kn zw>%^X8r&@vLNRVhcXC1~b}It6aX->?sF{z7ruqqkMd|!4?`YGt)wIl))2VrU^f>%S zP(h3#8i)H0{ScawQ#>!47$+%G&MmMhVs-%fA%3ssARJ3ppvkjDl~RuW28dlC+QOuAaB0sn;9i8<^-dNB4215-7hGmRaOm6-z+FU<1$f}Nx;>s4*!jo%mt z^?QKyIz;rIL(Y)?om7&`z?z1l;R!YWiJL{X9(boLuV>I*7euSmq&jR2R@MRO6FtcB17*6bI?D0T9Tf7mQN!L&q|?q) zn(eX(N8DLY0;$|eL#!n?2FP~t@U*Z$qJ}?FlBUQa)}I_#-V~Y4AbTvAmQpUlg?$7v zyR(=S4E?S?6e(X6D7aRe`=Aoxiq6;ZgINE@=3cE%L2N*A*0|G$q7U7^PR@MU_&K|K z=>x_qn%U<;ZkXhRg{PfTEB-s?&Pb!;4)PS)v8!2^Ge?%D^1wGP)liEOAHC5~TjHMP z`FzLJ_*G}jS7qV4LH7=043Lx(YVW2nsh4|dQsm#RWM)GH3VR|aOTO*ndJ9h;w%n9& zRThgTw-Fv0?ri-q$&Ecb4uKKPl@x75pd&lgF9&V9YFg&8%&-`j0 zy;wDNc(k)t4=#t#xAutYEOG8K4p!s%u41oEWLl$)631bg>g))WN<+(&(mnzdZ4ezN zd6u<`x@1OVUU@^`ghouYp(TC?YdCjS@p-8GH`lNfd=HC*fhU9yD1)lPMdxHWI{8=s zje1JD$Obg38tl&Kv-|d_uenCrjSEF=A7d`=OJa-&GPnomV&ee{!)|Rw8-F|&l$o15qRv5j zjT7ya0tEJ2TiWtrkMfbU;kGG+EQMy3MCJxby-jMIHnSw4#sV8VqY2xG91ezUX3WMR zr$5Qn6K}jXT$=g)(qiY%FVj@!GIDB?kP^-C{6%;aLNrPxIrWX0NN)J@#tkgtfJFw^nz0StO$*gc$-&SLcScfUtqWEg8$%Zi zWfEEkmjnLPPfiY{0|L{C=EX(bEgg0v!ErWS$%g@|JZ5o0N45_lKL?0OSQrKFEwr21 z)3%H%?M(bCtY>L?t4L(l2{0F87s}{uz69XVn8>&p=IU{waCYWc@l_5UHL8ONJ>#Fq`PAOE{{w6p7c@?eb*PzEMpAqI^muvN+U1;Gt(ww>C1oPp*Lc8GA z(jGDen6n^tw6&jjNd|ztPZ<cNGllhuSwBGc+vUBqt}uEeV2ikn)if{-Mfpb98``9usw}p>GswC!Oa}o840kDh zAB8++uqfL%{zX0hC(X=2Py4Bk;ob@-NE0I<5@i~h@cjb0prX9uxD`jB$MPJ|0 zYD_fls;m*dvXbxle*mtp2lOV2x5J4lQpbu{sKYL3O?`6ZnE*6mL@~AIVmOiV*AwL+ z5sdb9&Xc*wp zN*gR&d%vP8g4(V{4GSs$>~~0=N|m8`_gIzTEM{SMy!@|9cq&k0QwvQ@BSV-YI$Mh} z%=VXP(uD$ug(wSdG#=R~n4>e&WzT8$Qk9v6YA-Y)(!UVX)sC%xhI!*@T(f%^c>?O; zN+Rc_;U{6TTRYPCPQEqjK>Fm(mEp;wAD{@+u1l4=bUhF{y!r79jDh&w&ToJTCo*0t zK+yWpwZq2NjYh_YIEL-ZqO@1dbQ1|EDEh&p(-YQ38(-rXN7~_r6pSJ|Zjk80_(s6? zWKxKnP!M?}Nb6vjWA6Jg&q$>KHp06|XH5U1U1^%M98D&LqvDQ9TUr~qL}*QT5c?54 zqOB71RSEirExy+}@^)-s0yP{1i>!Z!#(`ZffOd!+lLhjdxSCZ6;j14oiyvf2i zNI~Pl#&2@rQ((R&vyy)UqMY&$f8LbuC_)5k6ZfE5EB;&;y)D$6c>wT6lr?X*lTCQ@ zB7jj^1r*rFH}@hSw~}}x(JL<-GEYXPmWiXj`YO#0AkDKJ_hE<7vzbM&z4VI^WCc`Z z2Gy786DvqTHJY$=p1{Z|`rk(>yW*#+>QZE*4%`K|uTkH9c}jhLYl8slqj~Z_JPQGQJ7}psjQvH$j#AJ@vH)qzX z>~@p1nBpHrzLSO?stBck2GFd)kk`f(Ufp?AWMO8(91=BM-*pWXUG$PDWtT6u^0^|? zHu%VHB4pwclCWQZg34BV4MIM!_dTHIuO!WOWhm-=lrtJ5cR828Pmj-I&9>8sF5(CT z#AJs42k=MY-Zz87>cqr#$jUy?rSN0dF>A$h6XX1w)U6ZTXc(Mry?sOWu`o7@5U)`M zDPB&(40-+sD4e3$oINmUm#^}ES5}Y9K;$}lN!K=EgWDwOw~7H94Q7TwaW1|7*v(`@ zb5NhZ9ld1gNQ+U^3bZGUI}NUVSZw?73tk^ym0$;W$P}i;D3bw1gCpmz``gJgD=o1C zWGt=F1T1?*4OSl19_BEf>0WolktQfm>dLe$%Jk_5a8EAC0Zz9=Z@YWEkNtRkjDH*6B;5I7y6kKtg697vDmg+S-> z2rJj(4kVWW?ZbsQ0Fnj9on^3S4Z#lK$BQOQ9SJ@qI=dOU*fX1NRV3nuBb0lYs5Xw^ z+M*wB!(N;flOV1~+sB!_n@2RFLg>Q^12mRVk9Oy2C97!)34itBn z0HhfG87LS7jy!wwkhpo{fJPHTy}s}5&6Tzohiz|irguwqiqY>1ubwce}*eiw_sp#Mk;s3vmLhsw~3RCx`ZzU&K8=mOm1V8KTYIUVhuL9 zRV0>(qk#`2l|9>SxyfwQ8!y@XLvKz;9%Q$I(9syll9O?#VhQq1%`rcrG*jT|Y0f;zHgs(&is{vV({CV1i) z!urm?po%qA!kt*n)4nVJA$)T1KGgIiywl$Nm|Yv=a?mpskbdb;=%Ys6au{ss@E5(H zE?{2s`Gb5*F5S${!jWuR82vyM)?)O;V}KO)y}h>x^L}VmDrn`|>}F$K?JQXRgRWML zd+FKHgjG$(?3L?Tg?0RGV3=`P#9xM)Ib3re%*#r{mTwYw^+Baq`s)iTD^}t=BaYnl z?`ySYF~rVCj^+L39y1LwM6+geyDJi$b#hQx-r_x;`5DUU%qW&PlW3sZoz(9wo)f>^ znOd8Vm+pq0LL&8h^dh8ui;ot`Th0%CqtjLCLZHK|XN;~% zGYAXQZ0yp!uk=-F=rKxeo%~9%{h0&0zGCR8ubbdIy28P|XWbk~x+&V}TsP21No?wL z?PJvcDs7|OsxX|ew=3>}6Y=}+^EvJZwC zEmM4vf(~M+S_;7Y-0_7Wmb;7{<9GjL{+lYgH~@+WVg_jOV$Oc#T$%k|NAX4-meUVu z!T`4=N$9!SW$>N(>c-xU(>3)O5@m38{5ug`S5V?d_VNsKI-zK#1Bqg$BD+SFgoI>` zP=FPPnT$TxKAQtz_GmnUR_h+d+lRt2-W2qj-4yti0f3-ri~XRCnOY~@D0Z(2r*AV( zl4BGA^bKEJf|us+mCef^508H)s9WWjJOF@BYwK3tl&s{>wim25FqMsS!^BRSCGWqdlsfn_JnT(5m?^TE)d7VD2y9?b{zP>C)YUB=FZe)i+qE zAz*;}CG2mp->>GjD>YC~Q6)dA`XwPzQkH5JrXGWbUhjn8+C(f(3QiOdFiaK)_PVTR z-COD2bdwz(b;37=dI;M<=v%eQ&w%dt+o>!2^a(4AH|G*@005_}JY+l?Htt~`zFJ8- zojSMG2oi-7@XWTS(w(qw^Nu`D?J#uG9q#Cd7;(;zmR(n-rdI_8qwCV+e2=kPh=71a zhBlyvvygoKUEiEJr-)}!;F$h_vmz-N-nk(|R*(Xt5p}i=QM!RK1kJ?gsEP`-ckWy2 z`%CfdyzEFi5`qRa%QJ7x@CLtKb&N?)U{SZExBvT#BJEC$e%kvRMbjD-*tkJ(vcYT% zi9!pA$L6Pa_76z8d{M^pp0IBH*FymQt?Ju}dk8ME!|XEA+DLttCw2(r3m8WDT?PIR{_r0`klK|3?6eu8UMf;HK|kd!fj0kEZ^5_6rj}Y zk^Xrml0Qn=L#QLQ315tS(;2KqaIyFPf%D8;Z_aJ*W}+^B`=>e=dcX<(v%(~*-@rgg zQ*(MF*-!_EBR@HRrhr6Ye)z+vl|Vht!5!3J+C606r{35=!UBTd*&DFBjudw`3><<* zUci)x<`D323oWa$iQciT1SrLl($%drC0q!Yh(?YRR_X03?DZRoru;=cBeLbcmNnh( zxKY)5SD%&m_>Z>y3qZ}fkg$prf!OCC0j|S;6oCHbPTGNX|4tR0eQn>mmFC{7R*i+R zJM&R7Y|y_BCSjoa!&2g}Qv-JkhCr3#P)m)wkPg-*Oi$A`+q2LVIlfpD%EJsAsY1ZO z1zZKDu06<@!nt2Ai$r}wQ~D1L5N?E@uq^Un$Tc}fWKhhjPZ{)qL}9k^l<;(fFt{Nq zrMh9g^AI3+KP1cmY7g0=&j_CYj{HcAiETNPnxg;!IORTbJH7rGB)9r_`si_563bYi z`-euXx#rf?8;3^H`VLzZ&eE!CUmMa zhKWiR_SFyrwGH#ypA-NnN^_V!sPg{+pMN%9E5ClrD}A6r7Ke1PAJsFll!1bWc1q5* z^o^$mQSA>T%F+_lUqM|0GFM^ZC{2*E^$hiEE8uX7Q^glHWL=J<=K|#qbp&@SJ z<{o;jo>KTf>B~QLH0FN*Dj%7^`yqGDp2FS#0JmrAX%@#yg;bN|l3t~3))ddb29qbi zd2Civ^T%P^x+tO}-NIi6|1!7*$3Wa5l~ozX8ZO9&#i%^OB#W&3@J1#JOVaf~mhE(w zb2rDinaL|DeS*aDE(dvcJc!VZ#S-QQgO4vh9?Osih2x zyvC*q38}q$X(OJG8bD+RVl5E;Sjz>*M)BZKA5N{goXHj2*{>&H2 zAp3n|ZM$HLI;XmZPjmD9;wkO?+S--Y2^oXEMZFmiKPeg4x9+5C-K4yVM-8DVg2;4!(o;(h*U4^-nO^8R2koo$@&-}Rs`QF&lUx+&MeosZzi@uT?;H(qos3A6mEJD5 zO7uIZj%3jDb}feAlF9feValXTByaNq$A_^BO`Et&G(k8z;BVKDbRMS6c}ec$*`!_S zjt(owW}5Rbbhei`Q@8;PtG~@8$2pj39&-v)zEJk`71d+-W@;GSs1wRk{EzK)wms^NA35nuk_?_-V zOyQNrsz3wDZc}{e#fD5D?TzWA4CrYm%qtGAL@^ups`3G-_}R zCuYKN{_*3_u*5w%2-S!%bL;PZ{p6(PBa54rBxWx0g@>gjdIznjqtHv485C*7n9O%R zStrTnjPMJ@)zLxQ2JQt*@C&7DJUGwiu2-_;s%aJZ)99=&(xtS@kMjnUcwjCi#g7Dp z3579Np#vj#(wk)W?5{_CZw>gM6AdaM{Pqgs_JT!A_xVmbWO6@wdx<+!$64QCP!IBa zXZXn-V>qxuxd@wz(lOhH2BE)!y#eXfm-)C8bw941735WlQ~mwZB_r+S+8mdv5Gk^S z5cautGmTq8YDz(A!dihSaZ+&TkyV}Ff;U9!l^?!3)hMk>|C^RUZyv6TH2JHhQwjVT z{)B3%93l5|glo5?mHXAyu_djK=pcbq`wNy&!5+BF~ggry&S77|-s+Jf>!4}#r8-p8c557t(`*1 zx@bhCz!ysVN1aW!l>`E(YRoQfx&hcir8Q!T+mv`dZEBls+zO)BUp23js|ls>OlEJm z%cc)8@O|OS4So(#^*31ovwB z^hJ?}4e!04BoWo_&vUzpQ6^)~IO1T05+dOF8fV*}b%m2%j1*!3WipRkzvIwuImC5l z++e+8ep!iPo(oZ8TG4y%gBH&Ox%b;6_0oW}*)3Js< z_?Tz1u98k^jJ&4I=6q#+v$ zcxnmfT&b0%RZE)LIquiMS@N@lE3@IBSDfQ0*gQc7|6|iKatre@Up9IGkiMkuJi;d#!4IS(yf( zu_+OG=3bFg5SdM5u4#nFoovRYKUoCw4aDflD}RTN0j(j894i%JLOS4_(JSa_2qbEN z_vHgNJ-RsA*>R?p;t0< zd6>o(YkqxSG~))U#1_N!<-;tehzl#fE7F)@enX_95)`Tsjfwx6jPsW!D)nz6BDFXe zSRQunG^b8qf=w!4J@$^k@$b6Bhh>{_<(p+-#u7)|?;1N?m+s!{rTcd(u}sIKRk8;( z2dPGn2#TGCFLnvGzeHB=xmC(uB^k&=^YsaY+96rZ1wT)Iz*bXK7XQ_0h?`F;T;gCgsz0KW8_yh7C`8)E)uAc=x~E{z zK+m4hXEfuw#z;~gw$1Dlg!IM7#~A6&;)nzG_E* z+ImXTkKj#V1>RBPu%d`Jr6yN|fw-FQAf*I`i*{&Z7p;L20p zcemOSUb`7Gq=7ieNn?uc)gK`HvBKNqV#YPd9q!|$`;2)Y>g*S_R}fDaxt3n;;0}35 zZ@np`AcIS^Y-XnhhtviZdc?&%`mzyy-TVi}O?arn@~Cn0_u^+1ESn4vIo$4J_a$y; z{-3_Nv%L>EG584fN}1h{s7JBFcZ}m;%Sn3Iyn-##d0}2VIz6~T&wx8WYhvPKV|d() zSY}DL;-l@%?BOfC`NxQ&-4x5i^u1R}OuMkzn<3!mb`gRRM9F~FZwUc6ewKu(LwCmM zK1nNhwHO9F^prJxmOj+rx%wtV;gj<`U7y`~MM^h+nLkbZVst-*m(|;^$O|875?(}} z=Y0~vmE(y5q3?v6DnCH_lG6-vZna};!fs{EWF{DE{bHVsDfw((Xb4Wjt zBVJW6z3{u!UHuKVK%n;TvfY`Mb1iWL&GmB`QYJ_RtrUlKARHE?u%g3#3C9WBOTwmF zXNLJ}n_LYT`~(5Py~5u=8=9uU_Y|or7KnDHN?BG?PJy$z1`TL%wNCnu7FzqUf#~&{ z1N(g!sDZ#fnT-C1!UpsI0G7N5_4#U%VRMZmQHga<=Q(GQ1x_vJ&O9)7f}P}SPf;u% zW5=&9B0zthsR<|jxwYir8s{mieH^#B-vm(uYyku^3%t~Nurxsl+36!jmgg+#1oJBv z#U(z}G(^qz`-Nr1WY5fYPD85+9ZuZGhLMqB`bEDiTVv^@l&i^%xlfMmK9i3-_o6;h zEMZ6Hv1qdy1P%=j&3BPY&UJZw@;-tzKul=I`vvHR5 z>-u|^SaMhF4XF)U{*5u60Ttept_0(Z*PN;wJKCd7pp1mzbE1aE!-N%q!{wX=IWx~ zIU@sUf#=?_x#o7I3?4^)tD^~=geFPdyl=ewFWFv!`YLmhyH^8_vl0x3cov+8#YH6w z8nO||d|uqM!};*h%J`#pHYrF2MJ4pFwvg+*8W}-KeLEB4_<}d2x2HhFxn@CH$-?=C zgu*E4HO#r$Xs4pDc9E2Y@hQ+@KculEits6p)kO!{ny=`0WB(GIlHDYjM@leDL`ZrX z8*+L`(?}{r&=HJg47VGbMCzw768s*ubc=u_Tg&NxNfx1aw^KK>C>jfyt&Kbc>|HB!G*I?VYNmF) z+WnirdALBfOBrNp{=F))DXbw%Sh%GP?S!qBe-9=V{+5@6nd|$b+w0bOHgzsg3_o^v z$!x%2W8`eAEv+qazCBfI9V`Tq!OAi4aRp9)}YP-2?Z@;%^kX5BBuLX_%py~a7Z zv@rMs4*EQ`3Eh%Ae3}@t4zgE8rN#%FkPGA-tQyKya#kFG5R+H;6GC!9@4F1i+bOUW zHm{!mp_Hb$No7z0!pXl*No_r5JcJt<&hQ8;931WSQ!~o{t}ScTlET;Y9?8X#MGn40o z14BvaN!qR-etQnnKl#k6)ZbT9uZ(@|XY%|3UBI`Ytu&iKz+@EX0Bdx3SMkU{YQ;DN zx^&&A$=L+JpMUueK#wrnJKYi)HMt6MmvEMm8ZCY1I5f>i^cuM^v4EW@a{CVu$K);C zU*I8*tP?h9c%RDTV)iB?Zv_?FT?&1v;f4|Cv zt*ZP|jiYPMYGK^6@e1`5={e`9b+oq-Sz5fBaopLclO!)Crl9455Cs5F;bROpX@t6l z#e}wJth7iK%Y?+UQvao;}MUIh*I%8dcK7Vkq zc)geHaTCLAK9OZ0L;re127P=wY8|P`EjnqbaR?F^9O)m=M&jAkCUolG0@hNp7TM20 zF}GOnxOX{BjatE>$|+i6NiIj&#^TIJ+9a6M9w2H278K~CoHF1~_=kzA7l%iu>)eZ1 zZ3~2klp9NHMJh?i!>JMa;{6NDJWbEy+p#NIzxXvxSWyypqJHIud74TeO!@N@$)S-tpA(BQ zdcWzY!AAKZ^kAH(VW*r?H1xD{W*m}zx_}YC_RN)_m+GFfuT^Na*ubnW-~zYUNm?Dy zk0|$X{<^@yj4QQ;T8&ml`^s3C0v?hFiWV%Yg^aHO<&=l zq!@8AV95sA&n!+vLYY_fZy<(+zbbqQjD}H<(!raLW*$&!*rsCD!ZIHDt&BOsE)XDB zbME-Ae2(8P;EXgMy}>`&WBoei&3(m2VgYS}@`ZqiE&|K^xJcdQfjN5POL}Ms&=R2A zda;OJGrp6Xmj5-7HB^$unZ%i=!SL`)j&k%O^3258jYWHBjezZ*pjk;HLfQs zJcC14qxFk&TcfXkNJ;p_FR*TIeaTV$ErV>8S4Il&&0GR4sm{=Bh<%lS zOZZN{FiZ?ft5jhLh@4PPUfX13V|;~v8m(V@8zj2VEWq+yw87%{wVDS9^1BkKzJo%M0eY_J)p1Gg10+X1`*jaPc+y$H=wP=k) zHm#y(P+kj7Pr%7B2uY}mn)U!+T@lkepGI}x_fGq&dz8rgnB#L0Z6Oj9wS>kN<%Me| z6(^Oyvnz?)5KRp8aF#xNvE&%0omOgupV5zh%CecQ0HuuFFc^nqCn9ts;cY0-&H|Q? zaN&#x^wCJWH#Z}_m2}kno()cyfN($^ZzLmNZv~Hpoiy&xN{;;+(#)lC9WxG)h^lLh zT8OL`y}zTh2DOh#{q3NK`Xrhk)isHh&4I_j!JA^_;l_yaO@kTxE>+&Q;d7fTbujx6 zovEVzxQs7J3)tEOb~or`?4ekl9*2AC4G6kCcPz0lHlU46Q*_iYE?@w@agdehfEQU# z6l~d*CqLRcg5n~gt*JRNnlH!?l>XQ!X`pp}w5*;a2gLH(rMSb+@)*FX-|+b&?l8{1 zPkz6*M}$J9TdF`7(!8VJFMqoFRjHXQR-VBjTi?zA(=r^smMz)WP@>q}MQHwt-@(u* zKFwGLqY|JPM~AR%hUuZB<%qYMSLyk47sGh?W7iD(ieo1$hB$N5at=K*VK!zlOkCGv zdI|$;;~JjjwTkEH*)uy3VOzHiUU$M2FxScTN!>wz;d{>w%MP%niqs5^4@X=sW8tkogQ$-~##!7AnffANfIL zFxJnJZm6*{$^&CX>Ts37z*1-NHRGWR3ru4Eq+lo}Jq7f=3Z8!9h6@b&HY<}t@xcMz zH#z-FkDZjvddUDS6N}{@miY34rN+Mc6hC88{jNu8piwhS}lBDV>1eVm= zPNrN^{VA1kV>7EKBPb`!5)I!4$sxMk{iouJ@?_cB1&cbI&g$}0hvv#MKZ>d~^5ALQ zwq@)de(jqB3d+JzWzQ&TinG9(`W6*0|HyzLmS$t|G**xuRv2@+7rZ8vbcHyf_d7cJ z59{2<7N>m0QYm*`Xx_@tdfh*7`1B8P)+vq=A29qCpX4~+$T3ShVZYB3Zj#p!S*GDc zpz(ek^q=96RErk9*%Cokg4m!*19?~Q%NMk;O;%o%Q2S|X&faXdb^{N1%Qf*Zx2)X| z8+Q?JZ7I^!*el?bP@P|_E7Y+=>ZTbl0erDNDo8r9lIsc7fq$^8fh;aYq1uaLt1i^N za5D8%)PYrV-gn)Uj3g0rWTGC_|fvXK!TlNGSuSAUpPn&vNFCE zO)Q-V>`k?5GSj_1AbR$}2Ub#v6>V37ap9pf``(@3X5xl5%pJkhkePuTk)AuHCaP{} zsbQzG#44h*G0#_N_B>pApe>7S8YONCwelBjJ}HjAW_Y#@XP&r^V--X*%oz;}Ee^0h)#>tvGCYdl+ox*`f%4jVH%QD1qXa z7s~aY1k@{=wx~2RxauEw#Dp|oL_baP7Ihz@F4-1G`|*7)Cj0hU;bl_)NAK$|dw2Ic z`w(mcyyGLhH|{hR2ycUMh#($bsWY_ELM!c^{gG0u2o=AoLSVSXOmK_--L zC1t2omc&(V&@Q{9L&10fD*_g^vZFtx>Gkar4o{_nk0@!y#@J1BQ zMcp5_gGtYt<`xI~f+{?Or1FDgs6}^0sf4tn*+N5cxAkpI@3B*;0ThB@y!}<>5{xRS zH-K&fyIp0?uB)#bb}2J@Nt_95+@Vy>R({vACTh{5je=(p_Yk`Y;$}4*Tt#NATs{$7Cs(JTrSQ<$mJ{v=eU?lKA#M|Jx;K1(#D@!A`JlcDga^yFY~eQQeAG=SG)aS-rn0$_}9s-!v@HC`FyU7BM_pOY`T*;9`f7(c+hKkGi285}@8PONcwLf$kfo`Eq)h27G;XUQQWkST zOM_U+zf*A8o}~hjrpN~t9p8D8%KXyQ%dYh3M+Vyf;*9PdYxd*k^&~7m9RMs0Gr#ZH z#q)j+R@6+tN@fc|$6MM0Iqu+ku|(DGTgaeZKFunmgb^0!WniWf8?&JPSaE4Qifbc` zEa<;GM4Zc5*ezuE%{5yV7g*ZZTA+kdEl}b46iCOh2?cK|Fx{aDu&-rKiiB>3Gcg`~ zQ#QsUC_yz6JY8X5&1)R{mix=;;ZJ}xwEYCe#A5<-*cwokC_xQ6j%+S0#ULPMS9Ohj z*}Rf!@*x6w&%WgFn-0)g{idBTEv*U2R4w?t^n6}LslRkw z=OA26t(BQ%v!g-fq4&DILgc~&h+5ug|Raxcr zJw^?Oo5_Ydp6HUX3e}N=xj2$p=svzPE5jeS*^%Dja5azenGnA#%YhgW0afxf!kP!l zp)4 zxOm7GNU#qGh9VeI`dNr?b&Kp3pO>kX=!2oye>(crVM+?vq3DT+p|ZP>$xlUV2n-Q$ z?oT7vwfIEg}7preG!r(Q= zqRb3E6U)R`H)>H#LAh#sy-rgJ;XQ?THPzy;DY6fuw%|gDX+7f&N_Z%XOb;<%3oD0W ziQye6Gs6c)?$!x}wJ_MTf5NFYpbM*8Q*bTPR+^bIz(OZnYFsK}II8vP1Vd+Db%&!}3RXZ|tb=b<%L zc@0^din1uErc{&#tz}dCIwVyP(v5*E4w{PSca7rQj_0&n09h~9{}XE;l;90bj$BG$ z(F&DNduX&KQoMzc36Pz?q=R(*3BW<4ECvnp9jH!F8+Cl!uhRq zmPpHK&QQv$$g@@+H7(Qwb~IGPNZAtk5UowwB_}>9e$u`aURJb2p`~UH;A#NrZ`x%- z&q4@9N^PJ%ZWuYV1UvH`T-X+Cx0!nZrGpS~c~F#E+Ew03sdE?4c;tFCZUYroEPyPE z$Dip*UjEb@cbBb92bpy>2t3@dk5>@Qh_u1$5!m`-)6M~BkRi$J5#SYG`_s%ycq~MMX<|5x zS=_4`h09S_ZDI+C-7o?Y-n zd;o*#6g|kV`br{VsNa+U@-wY=lvY7SRb%)mC8TGg`XSI|%k3M$yY!S?BS}&9huVD@ z3MxdbO@vw@VCO6gI1-CXs?WR^suWpplBN4|EK`Lny&Xa57)47M)J3glRnHLMx8O?= zMgZi>Rd_wusGw|E66jp8`vjL36J z?KPd(Xz_LJ=qTwgfdm5FFKtCFOd4#{&-^D6xQ?i8+P1^#52G`M#2e%FiGhN4!0`>h zXaKkLB8x&0W!es*5JciidFjl;PtkQ$%*$j5tH74Y5V6M74TYT<=2*Z*EG>jHbV6|j z1?7m;ZKxBanOIu5@pA(27eO0>sfA>hMP53~*v7-BT=5&U#bKRc?E*5frrhn8YTL=t zTz8mPSA0qWanYG3w}0t29p6YrqV4sXg*B>-rfsN-f)uU6sVbI+t8*QzWA4GlY8-A~ zE@ejsm%ImDY0aIlc!}95qh&_Qwe4G9yk!Lgk1$;5bPsn`+BU_?MXh`2M*(7RErDgA zL?ZNfmw;~RYo60caIZRe{{W+R>G!4Bt60VO@Aizpc+8D`2NLXw7?j|b(%Oe~1kPrV zT*L}$!!wZa08&^hJ?B@GCamhA8NQ%hD{!@oBWhwdM&`XEyj&bsFvN|BrIMRur*hqM z6~%ST6b-AA#~kq!$QODhZvEjB(#vRX+u~gB#C##F11yyFV8pw~=>m6H)cj#SfAqR# z#n1aNNCZzYEW8e$A+{}`u&I7(wypMtQdGb&v*WuvhrB=3lV_d)x0EP4V+^abyQC(P!wg)f`m_XmW+WfBQHJmAbB|^X@1f?Vt zLS+_HE^hHIZQMgQi=3$O=GjiBA{LKFF7&4<7#j4A+u%)pZWV^H@&+{UHdIvWFh-@g z>(H2#JxoTuaWh4OA#=5Vs8|PEydxSS2Hg^oc5}L7fXddvzlnYX34t<%T9rO35Q1>K z{{YB^#JM^5m;t`F!&wXsO~hERr-u{&022+s3Oc#ewtT9X5SJBlh!tT{dW>OZ0jl^7mlJO9!`b6&FG>|DE7Fvfj za+Kp|covIL;EfrwQ+bFIrL#-_0Le@xnlBM8S_VZO>yi}9%PKpVUmAc_HbY1CTc~)3 zR}fi2^?^l2yuv)wye6;f{zXeY$c3SIZWl8fAKNiOJ~!`H}VkTp}D& zm{ij>3{@o*@E}7~Re3m-NIOKa63!rWmJDTLI8Vg8EMkionQeT~8BuCT;hA$OSD!3f zYl3s;SVV6Z?^U^(vP9xbHfi%6jHG=B9*{-~;{?dhC}N4tk7&*=kUoS`_$&v)Xz~3_ zZ$NKUps|aaU}B)aI`)ZeqgA*mgkNeU=;UCOH1I}=OR9}pm|?;n33{?sPzxzSmtw#S zo?>L)$YRG(qKw#|63=A~2IYvOejrs{oYPe@VBdLCz&gHRJ)oGXAcWm7BEGN=Ud#mn z*G6Me(iDq$Y>vW#1JG7?Fo`e}1g^5{ZwRK@gKe_YHJuUV-~a;O!H+;k`l%{lXvM;#35T^#ZZB#>h6lZWyslv6t2v6{)I&Ycmkf za4C)u4HDwG^ds$2p~t*0OVj*j0Vh_z(**f95aF9uzLL_W-bL*x(kN2g8ponx;ZljH zKo-sA+Bm5N!oQiYD01=hxnikR4!MPwM_T0{k%|Rj%KhdbqS7zQ^&5#)JTnTl8TIcP z#guR!B|xEDf})%Qp1xzkD_;JrK_6vRCG^d~se`_8sM<**KHSJ({{SRJHxqWH#TI$A8*6m9+^O;QqD3|nEV&>p;sC zI(wk8w-6zt%7GPSRn&Q;Oc80*<^UJk;hX*```UvB+I0}+Di`8a5lFK+mN+XJGWt%> z_2ygYj_e+3^Qp&J-f-7L5esN> zp@X)f7!pxbYn$RK)d8#Ml*wouFcEXuxrqlzwV>*XS$hn+uzh8di4ezZ#dB%bnPS^- z@Kzg&ifhtmK`=Q^@Y+ucORhV@0i-vg1(L98YK_;uq+4z&PugMt#JOF$Fr_9JBkR9f+9 z!glWyTw0>2w-2 z+A8>7R#Dj^lc>g`n6=L$JBo`+=_w>Q7`jSnl&fYQkmms>Aoq=3-`M`FManR04o$$~ zaFq7DWiih9ryY2O3u~6o#^Tu^(NNz#rwbRvOPmO@m4IX!ho}zpxFsYgyS#Y*SdkBR zej-gUSTppPg3>fKyOb)hFz``~dcq4Li@cLnWOH7~Yj*j*vc)NxWh`+5Se>`U_Jd4W ztfAdNa|0BsYgm2ZWkIIl6KUC7k|WZk9E%0kVDAMl8O&So6tbDE+)K&|#(!8R zILm+=BUF@I@^yeMDr$%sLDSO&IU7_8@SI%43qw|G3=}1X{ZVC-!nF{$r*377aa~}w ziqT4Nh>aOq;w=`ro9z_sT9pe;ltio0MChN?X1P<`Oc5xFKzA*M!IDhpnF{@)7N=l| z1+d)4Iz`urw+3D&G*Vs?Hx`DRch-JPLFis>`4N8{zJNsu^c-`$0aZ0kUD$>M#PR z4h5NW7J)`^4dZgi6wm=tlAu!ccX5tL91hU|17#M5;Vy!l6ywATNUI%oiP*GT1~*;H z7+Q9!;n!|F5ykEIvN)Ip9E*TxjRz+rzfI~Wi@G@@ElZpWf?H5PbMvk-SJguupqfjG z&-GpT&(Vd$Q`RuomUgrSpn(x^%Z47Cn9FcYI_WkEgW4f@;s{UysQk^iZH*N=g51|= zV%2EQKw+mb+9r#B^7(7Lf2pM_4Zgi4fgRDOlpw94&L$`-rcW`bE8h$f2;D_BZC*mj z)US9kvM2&e&b}>B@fNG+4p1|p1)vV_?4ImWKQ?_PyD5jUF zZ7bImu8<5TShwC9G|bFb1Jt>j36irD7m9kK%0j`wix9JDNQP8kIeurnu?UkglJv*O zkkN%pHuV1hQMWIn0A;L9^~77sTcW-r4KamjUzwS*ZlYA0uNMw|Om!BoGjuA3jb2zJ z?l#2DWaw|QE?Hr9Rv;)GK+_h8wNl8*!l6JFBg{r-H*p*D?P!7aK z;2H=MqO?qayL_!RUh>nk0Hq<7bb*0k=!It_sd5Hq|U&fG_n;3dQTNWb)9X&bz8g_!Vz-vUl zrG(Dtoq%&uR(r5N@dM)M_9iJ0<7TQ8F#Al3Dxl0H z!F3#nLTwPyyB~>c^1Hazpy}7VXs~D&u|gU;%Mez4%5815tyin` zfpukt70-yS@~A$4q##w$=2*}dx;yuq5Gj=?k+k8ca<5M<=Owxu;wY731l-0nt9Jwrl^BeZJ8a@)wdzr)tin@^eT2lQn~MPShZ-N2 z=Pje86|xEE_;S07LdxukZNQsGt5T74T~%jJW>)}?Jx*s&(G{bZn0gceSnoNDE7Za| zA|*@B3cRdD;8as=bcA#^xCk})KcDGIRcL3-r9dJI0LPeHjX=zqGhaZK0b9tc+9N|c zG_SL$pAKS6dtwfmEsHABI93eByrV<}p};8KF0-hGVvdt>9Oz}P)d?|Yu~iwSbR8#S z5R%}MqpBhr;d%9zSWzEIL;?y`tIwneY+=L-Cq*{0%D@g*z*v_wFFgo>6u_;7TbRHw zu1MtOS+HF{5x{j$;$o*#GfW*(b<${A&6xy`Nh#VGs2d8d2RUuBaMi;Xgx(9Rsg;?_ zi|bIx0CxTvfF7|?t!mDt3R5}49cnL3MQ{LF#AAw_ztVErU#p3OB&5^@iBCv<5i798 z)$*mQ$ZpVm;xLrmW%=ekKBP4rnd<#zTp5=kBY5))Q5F|4DQYh_is>v?jBzhXfr^Qt zs|Z3RNseVV2;@!cMe4DJYn%l_l(B8*W9sYnh*wIKZw?fXGPcv$bLJ#7FNBc*3u$fi zgv8hdUxbXd+K+02WDS?2a?DjV1}YN)xL2y%Uo${oNos=ONk!mJunAwn1tp9+h&xJ^ z{0H!?vFXfRz6rHHlFsW0S~c1$kS`2xw7P;C*4*c`t_!R;=lZP(Qn9hjt3_W(Sc)A| z38B!)9+2zVcwJD1$^k-%0lPFacw=ooQ$GG4za0W3H zfy5MnfGdels$^ksV1zg-GK9*DmZfh307o1(0j~0p1aRuV zm@NosU}8~%!8U)eR2K^<+3f>)TN6iLnD2l?sUKKI;|&0ICFQp)u1&-XHxjohSMV1# z7oBM8#5qi=Q_g2;nfHLQmZ7soIox&xHZ=%3D8ujlRNbu(O)v>+s#;MESmbib5Zo?N zPk~|U6|$n17PRBy1#p)7%#>ynGq~3&Wqd*~L2l`3xJ7;9-XM?$1iW!Cm1y~tQP)gM z#P+ht+ps{>2PrJwZN)}f)y>K|4z(H19K;|~hggWSsPe%pAUl$XXyJHL5rSH5Wl>>+ zV~I;i1AxyG&dA$n7Q0<6Q*Mw9546alN-r+3K?c^eS3PQ;U^Y<;>s(Qn02@{^*Umz|DYN7cWHFgmDHdFG4odI#B=| zDbaF_5L+a+VRI3z#pWu^3snoWh2)seSxIw)ti22iq9QGlTKKtQ*rPhBNchMw+^e^| z=iE~}K$%+T=;PK4-&I=O%w!ff9x&TZpb-vfIh~E5!|;1; zErdI;WiaUp$d+O~zCab?Y}8PBQ((b*su(*1xyWS@VmV7(Fu7$a6~9!3(yJC?Hkq4k z8qB^X6|PO_ftLeMIEzAy05200x`tfD>e*H*W(m@kkC^_z6`7R*-K=AQhRBU$Yi8x_ zAU9Ev5#czG_XdX8%-?McAz9%Xl!yWWFZ_YjWRqz*i*Aiq542iV+6YT7p*>^u{W{D0 zfzhfT@o~ zkVR_n3PC9~lCsP7i^bqplgWqB_ZWp#&0jDr0q%o_Z&nFZgvKEL;zP!^R;5$jN?AYG zctyeM{=uvrr4TN(KkU05*nu4{rz_*hBgqON*fW#=0CObeQrGh=RC>4i&Gq$9<|Nzs zKbUPO#S8a|Aa@C-Ge(|fFdn8L)Val1+5k`4;ttnW>xl6yzt<7szMtd=(cj_|0BElg z@|5uRekDd&ZViE&pR5d6b3g1VR$;UV1bfAi-IT@}0+j$7T)|#<0$jN`4=5E}7Wzao zCD6CT5(b$q!NH!A-O7L=maLnrvQVf;Ly77A1km5Jeh2TSV=@YGu6i*=oJ&}VGME1Vr4wTKhQQ+) z>oz_J*6hmIa-Gg1V9AmP2%uLmWoRsK{EXRl(1O*o&Mwa1Np$8Zjmv%49i^Jvn(qU5 zp@%LdvRYcOHQFwqHA-#(%Z34+w75LzR=kl77Vo8yAuV`)VlQlFU!uZa5x^A?gOp1| zT7@DL(jel8ClNOH?GWz(jPX!HYO~K#hJisG_KIi;)Z*dVim=ZS4LR9pxVgj&?E#eZQ42U(3kuJ%cJ_HC1(0TXaU>)-6wa_ zI!%4(F@{7ql?iJW$k2x2{o)iL3IaNqXc?Pe!#^aUsZz?ngG#?N6F&3-`_mRZ=#yMf z9S~aIF)@itdSZX1nZE2l(T1O%Q~BW)phW6vi~I}g5|xAK!FgAhbsqA*Uhp?>cwP4= zS@(xg?==+q&0ntL%rgG~fR#|sGV>QRbWE%+CT3o*>5@6Wu{^cF4i-$I5JPdd6nA{P zK`;TLDTs9n3l4e&9O$Se-U^g1AuU{Lqob^7#NK5pa}|e2)*~QNutciw6vl55Y5|T& zZX1SmH2(lh!;#Q^DTh0Qnc0<`O4JwHR4|d29p9K_W>nnV)NvT+5nU1H9Fg3!^!i9- z{)ZQ69?*XTbs5ybF&3tOAd#!@1eK_df#`!i+-=2Ne2EyUZRX0^ns* zR5?d;qExvRU`z85Ay+CE!;a8dmRK>~EC?k-v{lzP%P0ZKeC7#78HGx@Uh||Gd504M ztQku^jWEn5s~^LtCE|0Kx>guvK{Lbp68eq+tgZ?Jr}Xk$7g(!*QX5G4QV3ySjXukaf9(T%P$^g0Mk57A{A`lAijx+93wh;I4&ZP%H|A+xGR`66Byxt zz`)DTsQS!X)(W>1aA}%C(@0|ldW|w--3qmmS8~kyUUZ!9LQ_+@Yl*5L8?L&UVMXGlXz-5H!&tXplLq9Op0IJ2 zQ%vn2oB7R +#include +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset(gnvs, 0, sizeof(*gnvs)); + + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/protectli/vault_bsw/board_info.txt b/src/mainboard/protectli/vault_bsw/board_info.txt new file mode 100644 index 0000000000..74144e8af2 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: FW2B / FW4B +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_bsw/com_init.c b/src/mainboard/protectli/vault_bsw/com_init.c new file mode 100644 index 0000000000..c599039c02 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/com_init.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb new file mode 100644 index 0000000000..94c083d13a --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/devicetree.cb @@ -0,0 +1,141 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "0" + register "PcdEnableDma0" = "0" + register "PcdEnableDma1" = "0" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "0" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "1" # Disable SVID + register "ChvSvidConfig" = "SVID_PMIC_CONFIG" + register "PcdEmmcMode" = "PCH_DISABLED" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "1" + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "6" + register "Usb2Port0IUsbTxEmphasisEn" = "3" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "6" + register "Usb2Port1IUsbTxEmphasisEn" = "3" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "6" + register "Usb2Port2IUsbTxEmphasisEn" = "3" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "6" + register "Usb2Port4IUsbTxEmphasisEn" = "3" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # Enable devices in PCI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping GFX + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 off end # 8086 22dc - PUNIT/DPTF + device pci 10.0 off end # 8086 2294 - MMC Port + device pci 12.0 off end # 8086 2296 - SD Port + device pci 13.0 on end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI + device pci 18.0 off end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 off end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 22ca - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 on # 8086 22ce - PCIe Root Port 4 + smbios_slot_desc + "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "WIFI" "SlotDataBusWidth1X" + end + device pci 1e.0 off end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/protectli/vault_bsw/dsdt.asl b/src/mainboard/protectli/vault_bsw/dsdt.asl new file mode 100644 index 0000000000..34f93fa229 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM revision */ +) +{ + #include "onboard.h" + + #include + + /* global NVS and variables */ + #include + #include + + Device (\_SB.PCI0) + { + #include + + Device (RP03) + { + Name (_ADR, 0x001C0002) // _ADR: Address + OperationRegion(RPXX, PCI_Config, 0x00, 0x10) + } + } + + #include + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/protectli/vault_bsw/fadt.c b/src/mainboard/protectli/vault_bsw/fadt.c new file mode 100644 index 0000000000..a84e063648 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/fadt.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = get_acpi_table_revision(FADT); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (unsigned long)facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + + header->checksum = acpi_checksum((void *)fadt, header->length); +} diff --git a/src/mainboard/protectli/vault_bsw/gpio.c b/src/mainboard/protectli/vault_bsw/gpio.c new file mode 100644 index 0000000000..741d51e33b --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/gpio.c @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + GPIO_NC, /* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_NC, /* 02 MF_PLT_CLK1 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* 05 PWM0*/ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + GPIO_NC, /* 16 SDMMC1_CLK */ + GPIO_NC, /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + GPIO_NC, /* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + GPIO_NC, /* 23 SDMMC1_CMD */ + GPIO_NC, /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + GPIO_NC, /* 26 SDMMC1_D3_CD_B */ + GPIO_NC, /* 30 SDMMC3_D1 */ + GPIO_NC, /* 31 SDMMC3_CLK */ + GPIO_NC, /* 32 SDMMC3_D3 */ + GPIO_NC, /* 33 SDMMC3_D2 */ + GPIO_NC, /* 34 SDMMC3_CMD */ + GPIO_NC, /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + GPIO_NC, /* 60 SPI1_MISO */ + GPIO_NC, /* 61 SPI1_CS0_B */ + GPIO_NC, /* 62 SPI1_CLK */ + GPIO_NC, /* 63 MMC1_D6 */ + GPIO_NC, /* 64 SPI1_MOSI */ + GPIO_NC, /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + GPIO_NC, /* 67 MMC1_D4_SD_WE */ + GPIO_NC, /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), + /* 77 GPIO_ALERT */ + GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ + NATIVE_PU20K(1), /* 79 ILB_SERIRQ */ + NATIVE_PU20K(1), /* 80 USB_OC0_B */ + GPIO_NC, /* 81 SDMMC3_CD_B */ + Native_M1, /* 82 SPKR */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN, /* 84 SDMMC1_RCLK */ + GPIO_NC, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + NATIVE_PU20K(1), /* 00 FST_SPI_D2 */ + NATIVE_PU20K(1), /* 01 FST_SPI_D0 */ + NATIVE_PU20K(1), /* 02 FST_SPI_CLK */ + NATIVE_PU20K(1), /* 03 FST_SPI_D3 */ + GPO_FUNC(P_20K_H, 1), /* 04 FST_SPI_CS1_B */ + NATIVE_PU20K(1), /* 05 FST_SPI_D1 */ + NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */ + GPO_FUNC(P_20K_H, 1), /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + NATIVE_PD20K(2), /* 30 MF_HDA_CLK */ + NATIVE_PD20K(2), /* 31 GPIO_SW31/MF_HDA_RSTB */ + NATIVE_PD20K(2), /* 32 GPIO_SW32/MF_HDA_SDI0 */ + NATIVE_PD20K(2), /* 33 MF_HDA_SDO */ + GPO_FUNC(P_20K_L, 1), /* 34 MF_HDA_DOCKRSTB */ + NATIVE_PD20K(2), /* 35 MF_HDA_SYNC */ + NATIVE_PD20K(2), /* 36 GPIO_SW36/MF_HDA_SDI1 */ + GPIO_INPUT_PD_20K, /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + GPIO_NC, /* 47 I2C6_SDA */ + GPIO_NC, /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + GPIO_NC, /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + GPIO_NC, /* 60 I2C1_SDA */ + GPIO_NC, /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + GPIO_NC, /* 63 I2C1_SCL */ + GPIO_NC, /* 64 I2C3_SDA */ + GPIO_NC, /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_NC, /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 SATA_GP2 */ + NATIVE_PU20K(1), /* 79 MF_SMB_ALERTB */ + GPIO_NC, /* 80 SATA_GP3 */ + NATIVE_PU20K(1), /* 81 MF_SMB_CLK */ + NATIVE_PU20K(1), /* 82 MF_SMB_DATA */ + GPIO_NC, /* 90 PCIE_CLKREQ0B */ + GPIO_NC, /* 91 PCIE_CLKREQ1B */ + GPIO_NC, /* 92 GP_SSP_2_CLK */ + GPIO_NC, /* 93 PCIE_CLKREQ2B */ + GPIO_NC, /* 94 GP_SSP_2_RXD */ + GPIO_NC, /* 95 PCIE_CLKREQ3B */ + GPIO_NC, /* 96 GP_SSP_2_FS */ + GPIO_NC, /* 97 GP_SSP_2_TXD */ + GPIO_END +}; + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, P_20K_L, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(P_20K_L, 1), /* 16 SEC_GPIO_SUS10 */ + NATIVE_PD20K(1), /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L15, P_20K_H, non_maskable, en_edge_rx_data, NA, + SMI), /* 18 GPIO_SUS7 */ + NATIVE_PD20K(1), /* 19 GPIO_SUS1 */ + GPIO_INPUT_PU_20K, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, P_20K_L, non_maskable, en_edge_rx_data, NA, + NA), /* 21 SEC_GPIO_SUS11 */ + NATIVE_PU20K(1), /* 22 GPIO_SUS4 */ + GPI(trig_level_high, L3, P_20K_H, non_maskable, en_rx_data, NA, NA), + /* 23 SEC_GPIO_SUS8 */ + NATIVE_PU20K(1), /* 24 GPIO_SUS2 */ + GPI(trig_edge_low, L14, P_20K_H, non_maskable, en_edge_rx_data, NA, + SCI), /* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_INPUT_PD_20K, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + GPIO_NC, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + NATIVE_TX_RX_EN, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + GPIO_NC, /* 63 PANEL1_BKLTCTL */ + GPIO_NC, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU1K_M1, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + GPIO_NC, /* 69 PANEL1_VDDEN */ + GPIO_NC, /* 70 PANEL1_BKLTEN */ + NATIVE_PU1K_M1, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + NATIVE_PU20K(1), /* 00 PMU_SLP_S3_B */ + NATIVE_PU20K(1), /* 01 PMU_BATLOW_B */ + NATIVE_PU20K(1), /* 02 SUS_STAT_B */ + NATIVE_PU20K(1), /* 03 PMU_SLP_S0IX_B */ + NATIVE_PD20K(1), /* 04 PMU_AC_PRESENT */ + NATIVE_PU20K(1), /* 05 PMU_PLTRST_B */ + NATIVE_PD20K(1), /* 06 PMU_SUSCLK */ + NATIVE_PU20K(1), /* 07 PMU_SLP_LAN_B */ + NATIVE_PU20K(1), /* 08 PMU_PWRBTN_B */ + NATIVE_PU20K(1), /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC_TX_RX(en_rx_data << 2, 1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + + return &gpio_config; +} diff --git a/src/mainboard/protectli/vault_bsw/irqroute.c b/src/mainboard/protectli/vault_bsw/irqroute.c new file mode 100644 index 0000000000..79bce75378 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/irqroute.c @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/protectli/vault_bsw/irqroute.h b/src/mainboard/protectli/vault_bsw/irqroute.h new file mode 100644 index 0000000000..5c2e34dcd5 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/irqroute.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, D, B, C, A), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, C, A, A) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/protectli/vault_bsw/mainboard.c b/src/mainboard/protectli/vault_bsw/mainboard.c new file mode 100644 index 0000000000..1fd891918b --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/mainboard.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +#define BIOS_CONTROL_REG 0xFC +#define BIOS_CONTROL_WPD (1 << 0) + +static void mainboard_enable(struct device *dev) +{ + volatile void *addr = (void *)(SPI_BASE_ADDRESS + BIOS_CONTROL_REG); + + /* Set Bios Write Protect Disable bit to allow saving MRC cache */ + write8(addr, read8(addr) | BIOS_CONTROL_WPD); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/protectli/vault_bsw/onboard.h b/src/mainboard/protectli/vault_bsw/onboard.h new file mode 100644 index 0000000000..fcdb3a70b8 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/onboard.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + + +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 77 + +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 + +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5670" +#define AUDIO_CODEC_CID "10EC5670" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1C + +#define BCRD2_PMIC_I2C_BUS 0x01 + +#endif diff --git a/src/mainboard/protectli/vault_bsw/ramstage.c b/src/mainboard/protectli/vault_bsw/ramstage.c new file mode 100644 index 0000000000..6320ca7a67 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + params->PcdTurboMode = 1; +} diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c new file mode 100644 index 0000000000..37a75dc56c --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void mainboard_after_memory_init(void) +{ + /* + * FSP enables internal UART. Disable it and reenable Super I/O UART to + * prevent loss of debug information on serial. + */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + memory_params->PcdMemChannel0Config = 0; + memory_params->PcdMemChannel1Config = 2; +} diff --git a/src/mainboard/protectli/vault_bsw/spi_vscc.c b/src/mainboard/protectli/vault_bsw/spi_vscc.c new file mode 100644 index 0000000000..529a78eb22 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/spi_vscc.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include + +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct vscc_config spi_config = { + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + return 0; +} diff --git a/src/mainboard/protectli/vault_bsw/variants/fw2b/overridetree.cb b/src/mainboard/protectli/vault_bsw/variants/fw2b/overridetree.cb new file mode 100644 index 0000000000..2cccd8589f --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/variants/fw2b/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/braswell + + device domain 0 on + device pci 1c.2 off end # 8086 22cc - PCIe Root Port 3 + end +end diff --git a/src/mainboard/protectli/vault_bsw/variants/fw4b/overridetree.cb b/src/mainboard/protectli/vault_bsw/variants/fw4b/overridetree.cb new file mode 100644 index 0000000000..a9c0199511 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/variants/fw4b/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/braswell + + device domain 0 on + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + end +end From fa0bdd9ee0210b91907b0bbd397583d643dbb887 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Thu, 5 Mar 2020 18:25:10 -0800 Subject: [PATCH 0345/1463] mb/google/volteer: change two gpio settings - declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment BUG=b:144933687, b:148179954 BRANCH=none TEST=none Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/variants/baseboard/gpio.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 3f1f2b0e0f..f6dbed0bee 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -29,7 +29,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_A9, NONE, DEEP), /* A10 : I2S2_RXD ==> EN_SPKR_PA */ PAD_CFG_GPO(GPP_A10, 1, DEEP), - /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ + /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), @@ -146,7 +146,8 @@ static const struct pad_config gpio_table[] = { /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART2_RXD ==> FPMCU_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_C20, NONE, PLTRST, EDGE_SINGLE), + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ @@ -381,7 +382,7 @@ static const struct pad_config gpio_table[] = { /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ - PAD_CFG_GPI(GPD2, NONE, DEEP), + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ From 3bc41cf7b4a3c5aab69e8c4fd796720cde38a324 Mon Sep 17 00:00:00 2001 From: Alex Levin Date: Fri, 6 Mar 2020 10:54:10 -0800 Subject: [PATCH 0346/1463] mb/google/volteer: Enable FPMCU on volteer BUG=b:147500717 TEST=none Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/baseboard/devicetree.cb | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 70b6186494..070e4f6786 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -153,7 +153,7 @@ chip soc/intel/tigerlake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| GSPI1 | Fingerprint MCU + #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | #| I2C1 | Touchscreen | #| I2C2 | WLAN, SAR0 | @@ -329,7 +329,16 @@ chip soc/intel/tigerlake device spi 0 on end end end # GSPI0 0xA0AA - device pci 1e.3 on end # GSPI1 0xA0AB + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" + device spi 0 on end + end # FPMCU + end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 From 8499f7fb1b961f2d3bf1329897d0c6ff97ab5038 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 5 Mar 2020 01:23:57 -0800 Subject: [PATCH 0347/1463] mb/google/dedede: Add GPIO list Leave all the GPIOs in not connected state so that they can be configured depending on the use-case. This is done to park the GPIOs in a known safe state. This will also help to ensure that the required GPIOs are configured when the concerned use-cases are enabled. Below GPIOs are configured in Native Function 1 and are required for boot-up. * VCCIN_AUX_VID0 * VCCIN_AUX_VID1 * AP_SLP_S0_L * PLT_RST_L * CPU_C10_GATE_L * GPDs BUG=None TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/dedede/variants/baseboard/gpio.c | 279 ++++++++++++++++++ 1 file changed, 279 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 83922422c1..31537e04c3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,19 +21,63 @@ static const struct pad_config gpio_table[] = { /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + /* A7 : SMB_CLK */ + PAD_NC(GPP_A7, NONE), + /* A8 : SMB_DATA */ + PAD_NC(GPP_A8, NONE), + /* A9 : SMB_ALERT_N */ + PAD_NC(GPP_A9, NONE), + /* A10 : WWAN_EN */ + PAD_NC(GPP_A10, NONE), + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), /* A12 : USB_OC1_N */ PAD_NC(GPP_A12, NONE), /* A13 : USB_OC2_N */ PAD_NC(GPP_A13, NONE), /* A14 : USB_OC3_N */ PAD_NC(GPP_A14, NONE), + /* A15 : GPP_A15 */ + PAD_NC(GPP_A15, NONE), /* A16 : EC_AP_USB_C0_HPD */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : EDP_HPD */ + PAD_NC(GPP_A17, NONE), /* A18 : USB_OC0_N */ PAD_NC(GPP_A18, NONE), + /* A19 : PCHHOT_N */ + PAD_NC(GPP_A19, NONE), + /* B0 : VCCIN_AUX_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : VCCIN_AUX_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : PROCHOT_ODL */ + PAD_NC(GPP_B2, NONE), + /* B3 : TRACKPAD_INT_ODL */ + PAD_NC(GPP_B3, NONE), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B5 : PCIE_CLKREQ0_N */ + PAD_NC(GPP_B5, NONE), + /* B6 : PCIE_CLKREQ1_N */ + PAD_NC(GPP_B6, NONE), + /* B7 : PCIE_CLKREQ2_N */ + PAD_NC(GPP_B7, NONE), + /* B8 : PCIE_CLKREQ3_N */ + PAD_NC(GPP_B8, NONE), + /* B9 : PCIE_CLKREQ4_N */ + PAD_NC(GPP_B9, NONE), + /* B10 : PCIE_CLKREQ5_N */ + PAD_NC(GPP_B10, NONE), + /* B11 : PMCALERT_N */ + PAD_NC(GPP_B11, NONE), + /* B12 : AP_SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR/GSPI0_CS1_N */ + PAD_NC(GPP_B14, NONE), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -42,17 +86,49 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0_N */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO */ + PAD_NC(GPP_B21, NONE), + /* B22 : GSPI1_MOSI */ + PAD_NC(GPP_B22, NONE), /* B23 : EC_AP_USB_C1_HDMI_HPD */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* C0 : RAM_STRAP_0 */ PAD_CFG_GPI(GPP_C0, NONE, DEEP), + /* C1 : GPP_C1 */ + PAD_NC(GPP_C1, NONE), + /* C2 : GPP_C2 */ + PAD_NC(GPP_C2, NONE), /* C3 : RAM_STRAP_1 */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* C4 : RAM_STRAP_2 */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* C6 : PMC_SUSWARN_N */ + PAD_NC(GPP_C6, NONE), + /* C7 : PMC_SUSACK_N */ + PAD_NC(GPP_C7, NONE), + /* C8 : GPP_C8/UART0_RXD */ + PAD_NC(GPP_C8, NONE), + /* C9 : GPP_C9/UART0_TXD */ + PAD_NC(GPP_C9, NONE), + /* C10 : GPP_C10/UART0_RTSB */ + PAD_NC(GPP_C10, NONE), + /* C11 : AP_WP_OD */ + PAD_NC(GPP_C11, NONE), + /* C12 : AP_PEN_DET_ODL */ + PAD_NC(GPP_C12, NONE), + /* C13 : GPP_C13/UART1_TXD */ + PAD_NC(GPP_C13, NONE), + /* C14 : EC_IN_RW_OD */ + PAD_NC(GPP_C14, NONE), + /* C15 : EC_AP_MKBP_INT_L */ + PAD_NC(GPP_C15, NONE), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ @@ -70,6 +146,107 @@ static const struct pad_config gpio_table[] = { /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + /* D0 : WWAN_HOST_WAKE */ + PAD_NC(GPP_D0, NONE), + /* D1 : WLAN_PERST_L */ + PAD_NC(GPP_D1, NONE), + /* D2 : WLAN_INT_L */ + PAD_NC(GPP_D2, NONE), + /* D3 : WLAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_D3, NONE), + /* D4 : TOUCH_INT_ODL */ + PAD_NC(GPP_D4, NONE), + /* D5 : TOUCH_RESET_L */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_NC(GPP_D6, NONE), + /* D7 : EMR_INT_ODL */ + PAD_NC(GPP_D7, NONE), + /* D8 : GPP_D8/GSPI2_CS0B/UART0A_RXD */ + PAD_NC(GPP_D8, NONE), + /* D9 : GPP_D9/GSPI2_CLK/UART0A_TXD */ + PAD_NC(GPP_D9, NONE), + /* D10 : GPP_D10/GSPI2_MISO/UART0A_RTSB */ + PAD_NC(GPP_D10, NONE), + /* D11 : GPP_D11/GSPI2_MOSI/UART0A_CTSB */ + PAD_NC(GPP_D11, NONE), + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D16 : HP_INT_ODL */ + PAD_NC(GPP_D16, NONE), + /* D17 : EN_SPK */ + PAD_NC(GPP_D17, NONE), + /* D18 : I2S_MCLK */ + PAD_NC(GPP_D18, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + /* D22 : AP_I2C_SUB_SDA*/ + PAD_NC(GPP_D22, NONE), + /* D23 : AP_I2C_SUB_SCL */ + PAD_NC(GPP_D23, NONE), + + /* E0 : CLK_24M_UCAM */ + PAD_NC(GPP_E0, NONE), + /* E1 : EMR_RESET_L */ + PAD_NC(GPP_E1, NONE), + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E3 : GPP_E3/SATA_0_DEVSLP */ + PAD_NC(GPP_E3, NONE), + /* E4 : IMGCLKOUT_2 */ + PAD_NC(GPP_E4, NONE), + /* E5 : AP_SUB_IO_2 */ + PAD_NC(GPP_E5, NONE), + /* E6 : GPP_E6/IMGCLKOUT_3 */ + PAD_NC(GPP_E6, NONE), + /* E7 : GPP_E7/SATA_1_DEVSLP */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8/SATA_0_GP */ + PAD_NC(GPP_E8, NONE), + /* E9 : GPP_E9/SML_CLK0/SATA_1_GP */ + PAD_NC(GPP_E9, NONE), + /* E10 : GPP_E10/SML_DATA0 */ + PAD_NC(GPP_E10, NONE), + /* E11 : AP_I2C_SUB_INT_ODL */ + PAD_NC(GPP_E11, NONE), + /* E12 : GPP_E12/IMGCLKOUT_4 */ + PAD_NC(GPP_E12, NONE), + /* E13 : GPP_E13/DDI0_DDC_SCL */ + PAD_NC(GPP_E13, NONE), + /* E14 : GPP_E14/DDI0_DDC_SDA */ + PAD_NC(GPP_E14, NONE), + /* E15 : GPP_E15/DDI1_DDC_SCL */ + PAD_NC(GPP_E15, NONE), + /* E16 : GPP_E16/DDI1_DDC_SDA */ + PAD_NC(GPP_E16, NONE), + /* E17 : HDMI_DDC_SCL */ + PAD_NC(GPP_E17, NONE), + /* E18 : HDMI_DDC_SDA */ + PAD_NC(GPP_E18, NONE), + /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ + PAD_NC(GPP_E19, NONE), + /* E20 : CNV_BRI_DT_R */ + PAD_NC(GPP_E20, NONE), + /* E21 : CNV_BRI_RSP */ + PAD_NC(GPP_E21, NONE), + /* E22 : CNV_RGI_DT_R */ + PAD_NC(GPP_E22, NONE), + /* E23 : CNV_RGI_RSP */ + PAD_NC(GPP_E23, NONE), + + + /* F4 : CNV_RF_RST_L */ + PAD_NC(GPP_F4, NONE), /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -95,6 +272,31 @@ static const struct pad_config gpio_table[] = { /* F18 : EMMC_RESET_N */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H0 : WWAN_PERST */ + PAD_NC(GPP_H0, NONE), + /* H1 : EN_PP3300_SD_U */ + PAD_NC(GPP_H1, NONE), + /* H2 : CNV_CLKREQ0 */ + PAD_NC(GPP_H2, NONE), + /* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */ + PAD_NC(GPP_H3, NONE), /* H4 : AP_I2C_TS_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : AP_I2C_TS_SCL */ @@ -107,6 +309,83 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* H9 : AP_I2C_AUDIO_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* H11 : GPP_H11/AV_I2S2_SCLK */ + PAD_NC(GPP_H11, NONE), + /* H12 : GPP_H12/AVS_I2S2_SFRM/CNF_RF_RESET_N */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13/AVS_I2S2_TXD/MODEM_CLKREQ */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14/AVS_I2S2_RXD */ + PAD_NC(GPP_H14, NONE), + /* H15 : I2S_SPK_BCLK */ + PAD_NC(GPP_H15, NONE), + /* H16 : AP_SUB_IO_L */ + PAD_NC(GPP_H16, NONE), + /* H17 : WWAN_RST_L */ + PAD_NC(GPP_H17, NONE), + /* H18 : WLAN_DISABLE_L */ + PAD_NC(GPP_H18, NONE), + /* H19 : BT_DISABLE_L */ + PAD_NC(GPP_H19, NONE), + + /* R0 : I2S_HP_BCLK */ + PAD_NC(GPP_R0, NONE), + /* R1 : I2S_HP_LRCK */ + PAD_NC(GPP_R1, NONE), + /* R2 : I2S_HP_AUDIO */ + PAD_NC(GPP_R2, NONE), + /* R3 : I2S_HP_MIC */ + PAD_NC(GPP_R3, NONE), + /* R4 : GPP_R04/HDA_RST_N */ + PAD_NC(GPP_R4, NONE), + /* R5 : GPP_R05/HDA_SDI1/AVS_I2S1_RXD */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S_SPK_LRCK */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_SPK_AUDIO */ + PAD_NC(GPP_R7, NONE), + + /* S0 : RAM_STRAP_4 */ + PAD_NC(GPP_S0, NONE), + /* S1 : RSVD_STRAP */ + PAD_NC(GPP_S1, NONE), + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), + /* S4 : GPP_S04/SNDW1_CLK */ + PAD_NC(GPP_S4, NONE), + /* S5 : GPP_S05/SNDW1_DATA */ + PAD_NC(GPP_S5, NONE), + /* S6 : DMIC0_CLK */ + PAD_NC(GPP_S6, NONE), + /* S7 : DMIC0_DATA */ + PAD_NC(GPP_S7, NONE), + + /* GPD0 : AP_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1 : GPP_GPD1/ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2 : EC_AP_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3 : EC_AP_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4 : AP_SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5 : AP_SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6 : AP_SLP_A_L */ + PAD_NC(GPD6, NONE), + /* GPD7 : GPP_GPD7 */ + PAD_NC(GPD7, NONE), + /* GPD8 : WLAN_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9 : AP_SLP_WLAN_L */ + PAD_NC(GPD9, NONE), + /* GPD10 : AP_SLP_S5_L */ + PAD_NC(GPD10, NONE), }; /* Early pad configuration in bootblock */ From 2c208bddc97e4eb2d0c5e445672c69b097cbc0cf Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 5 Mar 2020 11:58:34 -0800 Subject: [PATCH 0348/1463] mb/google/dedede: Configure EC <-> AP GPIOs BUG=b:150869661 TEST=Build and boot the mainboard. Trigger apreset from EC console. Trigger reboot from AP console. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/baseboard/gpio.c | 4 ++-- .../google/dedede/variants/baseboard/include/baseboard/ec.h | 3 +++ .../google/dedede/variants/baseboard/include/baseboard/gpio.h | 3 +++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 31537e04c3..ce5e20df71 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -126,9 +126,9 @@ static const struct pad_config gpio_table[] = { /* C13 : GPP_C13/UART1_TXD */ PAD_NC(GPP_C13, NONE), /* C14 : EC_IN_RW_OD */ - PAD_NC(GPP_C14, NONE), + PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* C15 : EC_AP_MKBP_INT_L */ - PAD_NC(GPP_C15, NONE), + PAD_CFG_GPI_APIC(GPP_C15, NONE, PLTRST, LEVEL, INVERT), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h index 2f0024c37a..0f356f882f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -79,4 +79,7 @@ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +/* Enable EC SYNC IRQ, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + #endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index 395143b666..de94e76f3d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -18,6 +18,9 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* EC sync irq is GPP_C15_IRQ */ +#define EC_SYNC_IRQ GPP_C15_IRQ + /* Memory configuration board straps */ #define GPIO_MEM_CONFIG_0 GPP_C0 #define GPIO_MEM_CONFIG_1 GPP_C3 From c83c5af3ae0e52c54ce4cc42134697d2d3ecfc60 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 5 Mar 2020 23:22:17 -0800 Subject: [PATCH 0349/1463] mb/google/dedede: Configure EDP_HPD GPIO This enables display for use by payload. TEST=Build and boot the mainboard. Ensure that the screens displayed by payload are visible. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index ce5e20df71..af95f6a733 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -42,7 +42,7 @@ static const struct pad_config gpio_table[] = { /* A16 : EC_AP_USB_C0_HPD */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A17 : EDP_HPD */ - PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : USB_OC0_N */ PAD_NC(GPP_A18, NONE), /* A19 : PCHHOT_N */ From 4ebe6dff1a9b2643e739371d3399f25a2c0e68a2 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 28 Feb 2020 16:25:08 -0700 Subject: [PATCH 0350/1463] mb/google/dedede: Add PCIe Root Port Configuration Add configuration for all the PCIe Root ports and Clock Source. Configure the Root Ports as disabled and clock sources as not used. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../dedede/variants/baseboard/devicetree.cb | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d5f58bae3e..0efb76dfe0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -76,6 +76,31 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" + # PCIE Root Port Configuration + register "PcieRpEnable[0]" = "0" + register "PcieRpEnable[1]" = "0" + register "PcieRpEnable[2]" = "0" + register "PcieRpEnable[3]" = "0" + register "PcieRpEnable[4]" = "0" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" + + register "PcieClkSrcUsage[0]" = "0xff" + register "PcieClkSrcUsage[1]" = "0xff" + register "PcieClkSrcUsage[2]" = "0xff" + register "PcieClkSrcUsage[3]" = "0xff" + register "PcieClkSrcUsage[4]" = "0xff" + register "PcieClkSrcUsage[5]" = "0xff" + + # PCIE Clock Request to Clock Source Mapping + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" From 0afd3f41d6599be8c1857608f133b16983f2f743 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 8 Mar 2020 13:58:23 +0100 Subject: [PATCH 0351/1463] arch/arm: Use 'print("%s...", __func__)' Change-Id: I83fb453344c31f2cfa97bdaf1b8791a7bef97fd7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39380 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/arch/arm/eabi_compat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index ec078909da..f936176e4b 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -9,7 +9,7 @@ int raise(int signum) __attribute__((used)); int raise(int signum) { - printk(BIOS_CRIT, "raise: Signal # %d caught\n", signum); + printk(BIOS_CRIT, "%s: Signal # %d caught\n", __func__, signum); return 0; } From 45473dd370e9034b30d3929984aa1873424852a9 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Thu, 10 Oct 2019 12:26:15 -0700 Subject: [PATCH 0352/1463] libpayload: Add uart/serial driver support for trogdor Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442 Signed-off-by: T Michael Turney Signed-off-by: Roja Rani Yarubandi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35960 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- payloads/libpayload/Kconfig | 5 + payloads/libpayload/configs/config.trogdor | 2 + payloads/libpayload/drivers/Makefile.inc | 1 + .../drivers/serial/qcom_qupv3_serial.c | 341 ++++++++++++++++++ 4 files changed, 349 insertions(+) create mode 100644 payloads/libpayload/drivers/serial/qcom_qupv3_serial.c diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 36f4af5215..f8e176e998 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -257,6 +257,11 @@ config QCS405_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config QUALCOMM_QUPV3_SERIAL_CONSOLE + bool "Qualcomm QUPV3 serial port driver" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor index 413f66ffe8..6309d2b45f 100644 --- a/payloads/libpayload/configs/config.trogdor +++ b/payloads/libpayload/configs/config.trogdor @@ -4,3 +4,5 @@ CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_USB=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index a3916700df..115cf40285 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -38,6 +38,7 @@ libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c serial/serial.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/qcs405.c serial/serial.c +libc-$(CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE) += serial/qcom_qupv3_serial.c serial/serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c diff --git a/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c b/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c new file mode 100644 index 0000000000..9100a27a8c --- /dev/null +++ b/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c @@ -0,0 +1,341 @@ +/* + * This file is part of the libpayload project. + * Copyright (c) 2020 Qualcomm Technologies. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* For simplicity sake let's rely on coreboot initializing the UART. */ +#include +#include +#include + +#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK 0x1 +#define RX_FIFO_WC_MSK 0x1FFFFFF +#define START_UART_TX 0x8000000 + +union proto_word_len { + u32 uart_tx_word_len; + u32 spi_word_len; +}; + +union proto_tx_trans_len { + u32 uart_tx_stop_bit_len; + u32 i2c_tx_trans_len; + u32 spi_tx_trans_len; +}; + +union proto_rx_trans_len { + u32 uart_tx_trans_len; + u32 i2c_rx_trans_len; + u32 spi_rx_trans_len; +}; + +struct qup_regs { + u32 geni_init_cfg_revision; + u32 geni_s_init_cfg_revision; + u8 _reserved1[0x10 - 0x08]; + u32 geni_general_cfg; + u32 geni_rx_fifo_ctrl; + u8 _reserved2[0x20 - 0x18]; + u32 geni_force_default_reg; + u32 geni_output_ctrl; + u32 geni_cgc_ctrl; + u32 geni_char_cfg; + u32 geni_char_data_n; + u8 _reserved3[0x40 - 0x34]; + u32 geni_status; + u32 geni_test_bus_ctrl; + u32 geni_ser_m_clk_cfg; + u32 geni_ser_s_clk_cfg; + u32 geni_prog_rom_ctrl_reg; + u8 _reserved4[0x60 - 0x54]; + u32 geni_clk_ctrl_ro; + u32 fifo_if_disable_ro; + u32 geni_fw_revision_ro; + u32 geni_s_fw_revision_ro; + u32 geni_fw_multilock_protns_ro; + u32 geni_fw_multilock_msa_ro; + u32 geni_fw_multilock_sp_ro; + u32 geni_clk_sel; + u32 geni_dfs_if_cfg; + u8 _reserved5[0x100 - 0x084]; + u32 geni_cfg_reg0; + u32 geni_cfg_reg1; + u32 geni_cfg_reg2; + u32 geni_cfg_reg3; + u32 geni_cfg_reg4; + u32 geni_cfg_reg5; + u32 geni_cfg_reg6; + u32 geni_cfg_reg7; + u32 geni_cfg_reg8; + u32 geni_cfg_reg9; + u32 geni_cfg_reg10; + u32 geni_cfg_reg11; + u32 geni_cfg_reg12; + u32 geni_cfg_reg13; + u32 geni_cfg_reg14; + u32 geni_cfg_reg15; + u32 geni_cfg_reg16; + u32 geni_cfg_reg17; + u32 geni_cfg_reg18; + u8 _reserved6[0x200 - 0x14C]; + u32 geni_cfg_reg64; + u32 geni_cfg_reg65; + u32 geni_cfg_reg66; + u32 geni_cfg_reg67; + u32 geni_cfg_reg68; + u32 geni_cfg_reg69; + u32 geni_cfg_reg70; + u32 geni_cfg_reg71; + u32 geni_cfg_reg72; + u32 spi_cpha; + u32 geni_cfg_reg74; + u32 proto_loopback_cfg; + u32 spi_cpol; + u32 i2c_noise_cancellation_ctl; + u32 i2c_monitor_ctl; + u32 geni_cfg_reg79; + u32 geni_cfg_reg80; + u32 geni_cfg_reg81; + u32 geni_cfg_reg82; + u32 spi_demux_output_inv; + u32 spi_demux_sel; + u32 geni_byte_granularity; + u32 geni_dma_mode_en; + u32 uart_tx_trans_cfg_reg; + u32 geni_tx_packing_cfg0; + u32 geni_tx_packing_cfg1; + union proto_word_len word_len; + union proto_tx_trans_len tx_trans_len; + union proto_rx_trans_len rx_trans_len; + u32 spi_pre_post_cmd_dly; + u32 i2c_scl_counters; + u32 geni_cfg_reg95; + u32 uart_rx_trans_cfg; + u32 geni_rx_packing_cfg0; + u32 geni_rx_packing_cfg1; + u32 uart_rx_word_len; + u32 geni_cfg_reg100; + u32 uart_rx_stale_cnt; + u32 geni_cfg_reg102; + u32 geni_cfg_reg103; + u32 geni_cfg_reg104; + u32 uart_tx_parity_cfg; + u32 uart_rx_parity_cfg; + u32 uart_manual_rfr; + u32 geni_cfg_reg108; + u32 geni_cfg_reg109; + u32 geni_cfg_reg110; + u8 _reserved7[0x600 - 0x2BC]; + u32 geni_m_cmd0; + u32 geni_m_cmd_ctrl_reg; + u8 _reserved8[0x10 - 0x08]; + u32 geni_m_irq_status; + u32 geni_m_irq_enable; + u32 geni_m_irq_clear; + u32 geni_m_irq_en_set; + u32 geni_m_irq_en_clear; + u32 geni_m_cmd_err_status; + u32 geni_m_fw_err_status; + u8 _reserved9[0x30 - 0x2C]; + u32 geni_s_cmd0; + u32 geni_s_cmd_ctrl_reg; + u8 _reserved10[0x40 - 0x38]; + u32 geni_s_irq_status; + u32 geni_s_irq_enable; + u32 geni_s_irq_clear; + u32 geni_s_irq_en_set; + u32 geni_s_irq_en_clear; + u8 _reserved11[0x700 - 0x654]; + u32 geni_tx_fifon; + u8 _reserved12[0x780 - 0x704]; + u32 geni_rx_fifon; + u8 _reserved13[0x800 - 0x784]; + u32 geni_tx_fifo_status; + u32 geni_rx_fifo_status; + u32 geni_tx_fifo_threshold; + u32 geni_tx_watermark_reg; + u32 geni_rx_watermark_reg; + u32 geni_rx_rfr_watermark_reg; + u8 _reserved14[0x900 - 0x818]; + u32 geni_gp_output_reg; + u8 _reserved15[0x908 - 0x904]; + u32 geni_ios; + u32 geni_timestamp; + u32 geni_m_gp_length; + u32 geni_s_gp_length; + u8 _reserved16[0x920 - 0x918]; + u32 geni_hw_irq_en; + u32 geni_hw_irq_ignore_on_active; + u8 _reserved17[0x930 - 0x928]; + u32 geni_hw_irq_cmd_param_0; + u8 _reserved18[0xA00 - 0x934]; + u32 geni_i3c_ibi_cfg_tablen; + u8 _reserved19[0xA80 - 0xA04]; + u32 geni_i3c_ibi_status; + u32 geni_i3c_ibi_rd_data; + u32 geni_i3c_ibi_search_pattern; + u32 geni_i3c_ibi_search_data; + u32 geni_i3c_sw_ibi_en; + u32 geni_i3c_sw_ibi_en_recover; + u8 _reserved20[0xC30 - 0xA98]; + u32 dma_tx_ptr_l; + u32 dma_tx_ptr_h; + u32 dma_tx_attr; + u32 dma_tx_length; + u32 dma_tx_irq_stat; + u32 dma_tx_irq_clr; + u32 dma_tx_irq_en; + u32 dma_tx_irq_en_set; + u32 dma_tx_irq_en_clr; + u32 dma_tx_length_in; + u32 dma_tx_fsm_rst; + u32 dma_tx_max_burst_size; + u8 _reserved21[0xD30 - 0xC60]; + u32 dma_rx_ptr_l; + u32 dma_rx_ptr_h; + u32 dma_rx_attr; + u32 dma_rx_length; + u32 dma_rx_irq_stat; + u32 dma_rx_irq_clr; + u32 dma_rx_irq_en; + u32 dma_rx_irq_en_set; + u32 dma_rx_irq_en_clr; + u32 dma_rx_length_in; + u32 dma_rx_fsm_rst; + u32 dma_rx_max_burst_size; + u32 dma_rx_flush; + u8 _reserved22[0xE14 - 0xD64]; + u32 se_irq_high_priority; + u32 se_gsi_event_en; + u32 se_irq_en; + u32 dma_if_en_ro; + u32 se_hw_param_0; + u32 se_hw_param_1; + u32 se_hw_param_2; + u32 dma_general_cfg; + u8 _reserved23[0x40 - 0x34]; + u32 dma_debug_reg0; + u32 dma_test_bus_ctrl; + u32 se_top_test_bus_ctrl; + u8 _reserved24[0x1000 - 0x0E4C]; + u32 se_geni_fw_revision; + u32 se_s_fw_revision; + u8 _reserved25[0x10-0x08]; + u32 se_geni_cfg_ramn; + u8 _reserved26[0x2000 - 0x1014]; + u32 se_geni_clk_ctrl; + u32 se_dma_if_en; + u32 se_fifo_if_disable; + u32 se_geni_fw_multilock_protns; + u32 se_geni_fw_multilock_msa; + u32 se_geni_fw_multilock_sp; +}; +check_member(qup_regs, geni_clk_sel, 0x7C); +check_member(qup_regs, geni_cfg_reg108, 0x2B0); +check_member(qup_regs, geni_dma_mode_en, 0x258); +check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84); +check_member(qup_regs, dma_test_bus_ctrl, 0xE44); +check_member(qup_regs, se_geni_cfg_ramn, 0x1010); +check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014); + +static struct console_input_driver consin = { + .havekey = serial_havechar, + .getchar = serial_getchar, + .input_type = CONSOLE_INPUT_TYPE_UART, +}; + +static struct console_output_driver consout = { + .putchar = serial_putchar, +}; + +static struct qup_regs *uart_base_address(void) +{ + return (void *)(uintptr_t)lib_sysinfo.serial->baseaddr; +} + +static void uart_qupv3_tx_flush(void) +{ + struct qup_regs *regs = uart_base_address(); + + while (read32(®s->geni_status) & GENI_STATUS_M_GENI_CMD_ACTIVE_MASK) + ; +} + +static unsigned char uart_qupv3_rx_byte(void) +{ + struct qup_regs *regs = uart_base_address(); + + if (read32(®s->geni_rx_fifo_status) & RX_FIFO_WC_MSK) + return read32(®s->geni_rx_fifon) & 0xFF; + + return 0; +} + +static void uart_qupv3_tx_byte(unsigned char data) +{ + struct qup_regs *regs = uart_base_address(); + + uart_qupv3_tx_flush(); + + write32(®s->rx_trans_len.uart_tx_trans_len, 1); + /* Start TX */ + write32(®s->geni_m_cmd0, START_UART_TX); + write32(®s->geni_tx_fifon, data); +} + +void serial_putchar(unsigned int data) +{ + if (data == 0xa) + uart_qupv3_tx_byte(0xd); + uart_qupv3_tx_byte(data); +} + +int serial_havechar(void) +{ + struct qup_regs *regs = uart_base_address(); + + if (read32(®s->geni_rx_fifo_status) & RX_FIFO_WC_MSK) + return 1; + + return 0; +} + +int serial_getchar(void) +{ + return uart_qupv3_rx_byte(); +} + +void serial_console_init(void) +{ + if (!lib_sysinfo.serial) + return; + + console_add_output_driver(&consout); + console_add_input_driver(&consin); +} From cd0a5fcafc3eff013394c9b264337d2aebb66e3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 9 Mar 2020 22:51:39 +0100 Subject: [PATCH 0353/1463] MAINTAINERS: Add 3mdeb as Protectli mainboards maintainers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I03301441bb07e64aeb59e659ab1b22442b73ca1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39418 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 77769c0487..a79d98f01c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -323,6 +323,12 @@ M: Michał Żygowski S: Supported F: src/mainboard/pcengines/ +PROTECTLI ALL MAINBOARDS +M: Piotr Król +M: Michał Żygowski +S: Maintained +F: src/mainboard/protectli/ + SIEMENS MC_xxxx MAINBOARDS M: Werner Zeh S: Maintained From f6f54dd3fa4f30d2078b76d0adcceb2a14cde3c5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 8 Mar 2020 11:20:08 +0100 Subject: [PATCH 0354/1463] libpayload/corebootfb: Replace obsolete macros FI and CHARS These macros serve no purpose anymore, let's do the substitution manually once and for all. Also update the comment on the macros and fix whitespace on the touched lines. TEST=Checked that there are no changes in compiled code. Change-Id: Ib60f9ab157e2e7d44b551dd4f695a6c25ebeb405 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39379 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- .../libpayload/drivers/video/corebootfb.c | 110 +++++++++--------- 1 file changed, 54 insertions(+), 56 deletions(-) diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index 8e7ac11540..efd13a7d12 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -64,41 +64,39 @@ static const u32 vga_colors[] = { struct cb_framebuffer fbinfo; static unsigned short *chars; -/* Addresses for the various components */ -#define FI (&fbinfo) -#define FB ((unsigned char *) phys_to_virt(FI->physical_address)) -#define CHARS (chars) +/* Shorthand for up-to-date virtual framebuffer address */ +#define FB ((unsigned char *)phys_to_virt(fbinfo.physical_address)) static void corebootfb_scroll_up(void) { unsigned char *dst = FB; - unsigned char *src = FB + (FI->bytes_per_line * font_height); + unsigned char *src = FB + (fbinfo.bytes_per_line * font_height); int y; /* Scroll all lines up */ - for(y = 0; y < FI->y_resolution - font_height; y++) { - memcpy(dst, src, FI->x_resolution * (FI->bits_per_pixel >> 3)); + for (y = 0; y < fbinfo.y_resolution - font_height; y++) { + memcpy(dst, src, fbinfo.x_resolution * (fbinfo.bits_per_pixel >> 3)); - dst += FI->bytes_per_line; - src += FI->bytes_per_line; + dst += fbinfo.bytes_per_line; + src += fbinfo.bytes_per_line; } /* Erase last line */ - dst = FB + (FI->y_resolution - font_height) * FI->bytes_per_line; + dst = FB + (fbinfo.y_resolution - font_height) * fbinfo.bytes_per_line; - for(; y < FI->y_resolution; y++) { - memset(dst, 0, FI->x_resolution * (FI->bits_per_pixel >> 3)); - dst += FI->bytes_per_line; + for (; y < fbinfo.y_resolution; y++) { + memset(dst, 0, fbinfo.x_resolution * (fbinfo.bits_per_pixel >> 3)); + dst += fbinfo.bytes_per_line; } /* And update the char buffer */ - dst = (unsigned char *) CHARS; - src = (unsigned char *) (CHARS + coreboot_video_console.columns); + dst = (unsigned char *)chars; + src = (unsigned char *)(chars + coreboot_video_console.columns); memcpy(dst, src, coreboot_video_console.columns * (coreboot_video_console.rows - 1) * 2); int column; for (column = 0; column < coreboot_video_console.columns; column++) - CHARS[(coreboot_video_console.rows - 1) * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8); + chars[(coreboot_video_console.rows - 1) * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8); cursor_y--; } @@ -109,15 +107,15 @@ static void corebootfb_clear(void) unsigned char *ptr = FB; /* Clear the screen */ - for(row = 0; row < FI->y_resolution; row++) { - memset(ptr, 0, FI->x_resolution * (FI->bits_per_pixel >> 3)); - ptr += FI->bytes_per_line; + for (row = 0; row < fbinfo.y_resolution; row++) { + memset(ptr, 0, fbinfo.x_resolution * (fbinfo.bits_per_pixel >> 3)); + ptr += fbinfo.bytes_per_line; } /* And update the char buffer */ for(row = 0; row < coreboot_video_console.rows; row++) for (column = 0; column < coreboot_video_console.columns; column++) - CHARS[row * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8); + chars[row * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8); } static void corebootfb_putchar(u8 row, u8 col, unsigned int ch) @@ -132,55 +130,55 @@ static void corebootfb_putchar(u8 row, u8 col, unsigned int ch) int x, y; - if (FI->bits_per_pixel > 8) { - bgval = ((((vga_colors[bg] >> 0) & 0xff) >> (8 - FI->blue_mask_size)) << FI->blue_mask_pos) | - ((((vga_colors[bg] >> 8) & 0xff) >> (8 - FI->green_mask_size)) << FI->green_mask_pos) | - ((((vga_colors[bg] >> 16) & 0xff) >> (8 - FI->red_mask_size)) << FI->red_mask_pos); - fgval = ((((vga_colors[fg] >> 0) & 0xff) >> (8 - FI->blue_mask_size)) << FI->blue_mask_pos) | - ((((vga_colors[fg] >> 8) & 0xff) >> (8 - FI->green_mask_size)) << FI->green_mask_pos) | - ((((vga_colors[fg] >> 16) & 0xff) >> (8 - FI->red_mask_size)) << FI->red_mask_pos); + if (fbinfo.bits_per_pixel > 8) { + bgval = ((((vga_colors[bg] >> 0) & 0xff) >> (8 - fbinfo.blue_mask_size)) << fbinfo.blue_mask_pos) | + ((((vga_colors[bg] >> 8) & 0xff) >> (8 - fbinfo.green_mask_size)) << fbinfo.green_mask_pos) | + ((((vga_colors[bg] >> 16) & 0xff) >> (8 - fbinfo.red_mask_size)) << fbinfo.red_mask_pos); + fgval = ((((vga_colors[fg] >> 0) & 0xff) >> (8 - fbinfo.blue_mask_size)) << fbinfo.blue_mask_pos) | + ((((vga_colors[fg] >> 8) & 0xff) >> (8 - fbinfo.green_mask_size)) << fbinfo.green_mask_pos) | + ((((vga_colors[fg] >> 16) & 0xff) >> (8 - fbinfo.red_mask_size)) << fbinfo.red_mask_pos); } - dst = FB + ((row * font_height) * FI->bytes_per_line); - dst += (col * font_width * (FI->bits_per_pixel >> 3)); + dst = FB + ((row * font_height) * fbinfo.bytes_per_line); + dst += (col * font_width * (fbinfo.bits_per_pixel >> 3)); for(y = 0; y < font_height; y++) { for(x = font_width - 1; x >= 0; x--) { - switch (FI->bits_per_pixel) { + switch (fbinfo.bits_per_pixel) { case 8: /* Indexed */ - dst[(font_width - x) * (FI->bits_per_pixel >> 3)] = font_glyph_filled(ch, x, y) ? fg : bg; + dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3)] = font_glyph_filled(ch, x, y) ? fg : bg; break; case 16: /* 16 bpp */ - dst16 = (u16 *)(dst + (font_width - x) * (FI->bits_per_pixel >> 3)); + dst16 = (u16 *)(dst + (font_width - x) * (fbinfo.bits_per_pixel >> 3)); *dst16 = font_glyph_filled(ch, x, y) ? fgval : bgval; break; case 24: /* 24 bpp */ if (font_glyph_filled(ch, x, y)) { - dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 0] = fgval & 0xff; - dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 1] = (fgval >> 8) & 0xff; - dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 2] = (fgval >> 16) & 0xff; + dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 0] = fgval & 0xff; + dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 1] = (fgval >> 8) & 0xff; + dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 2] = (fgval >> 16) & 0xff; } else { - dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 0] = bgval & 0xff; - dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 1] = (bgval >> 8) & 0xff; - dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 2] = (bgval >> 16) & 0xff; + dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 0] = bgval & 0xff; + dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 1] = (bgval >> 8) & 0xff; + dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 2] = (bgval >> 16) & 0xff; } break; case 32: /* 32 bpp */ - dst32 = (u32 *)(dst + (font_width - x) * (FI->bits_per_pixel >> 3)); + dst32 = (u32 *)(dst + (font_width - x) * (fbinfo.bits_per_pixel >> 3)); *dst32 = font_glyph_filled(ch, x, y) ? fgval : bgval; break; } } - dst += FI->bytes_per_line; + dst += fbinfo.bytes_per_line; } } static void corebootfb_putc(u8 row, u8 col, unsigned int ch) { - CHARS[row * coreboot_video_console.columns + col] = ch; + chars[row * coreboot_video_console.columns + col] = ch; corebootfb_putchar(row, col, ch); } @@ -188,10 +186,10 @@ static void corebootfb_update_cursor(void) { int ch, paint; if(cursor_en) { - ch = CHARS[cursor_y * coreboot_video_console.columns + cursor_x]; + ch = chars[cursor_y * coreboot_video_console.columns + cursor_x]; paint = (ch & 0xff) | ((ch << 4) & 0xf000) | ((ch >> 4) & 0x0f00); } else { - paint = CHARS[cursor_y * coreboot_video_console.columns + cursor_x]; + paint = chars[cursor_y * coreboot_video_console.columns + cursor_x]; } if (cursor_y < coreboot_video_console.rows) @@ -231,20 +229,20 @@ static int corebootfb_init(void) fbinfo = *lib_sysinfo.framebuffer; - if (FI->physical_address == 0) + if (fbinfo.physical_address == 0) return -1; - font_init(FI->x_resolution); + font_init(fbinfo.x_resolution); /* Draw centered on the framebuffer if requested and feasible, */ const int center = IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CENTERED) - && coreboot_video_console.columns * font_width <= FI->x_resolution - && coreboot_video_console.rows * font_height <= FI->y_resolution; + && coreboot_video_console.columns * font_width <= fbinfo.x_resolution + && coreboot_video_console.rows * font_height <= fbinfo.y_resolution; /* adapt to the framebuffer size, otherwise. */ if (!center) { - coreboot_video_console.columns = FI->x_resolution / font_width; - coreboot_video_console.rows = FI->y_resolution / font_height; + coreboot_video_console.columns = fbinfo.x_resolution / font_width; + coreboot_video_console.rows = fbinfo.y_resolution / font_height; } chars = malloc(coreboot_video_console.rows * @@ -256,13 +254,13 @@ static int corebootfb_init(void) corebootfb_clear(); if (center) { - FI->physical_address += - (FI->x_resolution - coreboot_video_console.columns * font_width) - / 2 * FI->bits_per_pixel / 8 - + (FI->y_resolution - coreboot_video_console.rows * font_height) - / 2 * FI->bytes_per_line; - FI->x_resolution = coreboot_video_console.columns * font_width; - FI->y_resolution = coreboot_video_console.rows * font_height; + fbinfo.physical_address += + (fbinfo.x_resolution - coreboot_video_console.columns * font_width) + / 2 * fbinfo.bits_per_pixel / 8 + + (fbinfo.y_resolution - coreboot_video_console.rows * font_height) + / 2 * fbinfo.bytes_per_line; + fbinfo.x_resolution = coreboot_video_console.columns * font_width; + fbinfo.y_resolution = coreboot_video_console.rows * font_height; } return 0; From 01ec713c269f68e5a2918cfb8ee14d6d1f40eda8 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Fri, 6 Mar 2020 10:51:30 -0800 Subject: [PATCH 0355/1463] mb/google/volteer: set TcssXhciEn to 1 BUG=144874778 TEST=Built with Volteer recipe and verified USB functionality Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 070e4f6786..dd6895b131 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -110,6 +110,9 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # TCSS USB3 + register "TcssXhciEn" = "1" + # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" From 2b4ded0be8c1c01aba566bb4bbccf5169ce133f7 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 3 Mar 2020 01:43:45 -0800 Subject: [PATCH 0356/1463] soc/intel/tigerlake: Enable Hybrid storage mode To use Optane memory, we need to set 2x2 PCIe lane mode while we need to set 1x4 PCIe lane mode for NVMe. The mode can be selected using the FIT tool at build time. By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe lane mode if Optane memory is not detected and the mode is not 1x4 during boot up. The mode is saved in SPI NOR for next boot. BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP from NVMe and Optane Check PCIe lane configuration. Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae: Signed-off-by: Wonkyu Kim Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232 Reviewed-by: Angel Pons Reviewed-by: Nick Vaccaro Reviewed-by: Srinidhi N Kaushik Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 5 +++++ src/soc/intel/tigerlake/fsp_params_tgl.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a6bcf0847f..d2ea0ddd2f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -266,6 +266,11 @@ struct soc_intel_tigerlake_config { uint8_t DdiPort2Ddc; uint8_t DdiPort3Ddc; uint8_t DdiPort4Ddc; + + /* Hybrid storage mode enable (1) / disable (0) + * This mode makes FSP detect Optane and NVME and set PCIe lane mode + * accordingly */ + uint8_t HybridStorageMode; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 0dae0fed47..14997c519a 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -157,6 +157,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + /* Enable Hybrid storage auto detection */ + params->HybridStorageMode = config->HybridStorageMode; + mainboard_silicon_init_params(params); } From dcd3d072d4760d9040b61d34c5ee6663a963fb54 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 5 Mar 2020 00:41:14 -0800 Subject: [PATCH 0357/1463] mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 +++++- .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 5888db0474..e60e648ef9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -136,7 +136,11 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end + device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/max98373 register "vmon_slot_no" = "4" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index a937ab3cc8..a3539aa937 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -131,7 +131,11 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end + device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/max98373 register "vmon_slot_no" = "4" From 48be6b276a0d7d0376684eaa5c1d92b763f61cc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 27 Jun 2019 12:19:18 +0200 Subject: [PATCH 0358/1463] mb/protectli/vault_kbl: Add FW6 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks --- Documentation/mainboard/index.md | 1 + Documentation/mainboard/protectli/fw6.jpg | Bin 0 -> 50587 bytes Documentation/mainboard/protectli/fw6.md | 137 ++++++++ src/mainboard/protectli/Kconfig | 1 - src/mainboard/protectli/vault_kbl/Kconfig | 59 ++++ .../protectli/vault_kbl/Kconfig.name | 2 + .../protectli/vault_kbl/Makefile.inc | 8 + src/mainboard/protectli/vault_kbl/acpi/ec.asl | 0 .../protectli/vault_kbl/acpi/superio.asl | 0 .../protectli/vault_kbl/board_info.txt | 6 + src/mainboard/protectli/vault_kbl/bootblock.c | 17 + src/mainboard/protectli/vault_kbl/data.vbt | Bin 0 -> 4608 bytes .../protectli/vault_kbl/devicetree.cb | 309 ++++++++++++++++++ src/mainboard/protectli/vault_kbl/dsdt.asl | 25 ++ .../protectli/vault_kbl/gma-mainboard.ads | 16 + src/mainboard/protectli/vault_kbl/gpio.h | 180 ++++++++++ src/mainboard/protectli/vault_kbl/ramstage.c | 21 ++ src/mainboard/protectli/vault_kbl/romstage.c | 66 ++++ 18 files changed, 847 insertions(+), 1 deletion(-) create mode 100644 Documentation/mainboard/protectli/fw6.jpg create mode 100644 Documentation/mainboard/protectli/fw6.md create mode 100644 src/mainboard/protectli/vault_kbl/Kconfig create mode 100644 src/mainboard/protectli/vault_kbl/Kconfig.name create mode 100644 src/mainboard/protectli/vault_kbl/Makefile.inc create mode 100644 src/mainboard/protectli/vault_kbl/acpi/ec.asl create mode 100644 src/mainboard/protectli/vault_kbl/acpi/superio.asl create mode 100644 src/mainboard/protectli/vault_kbl/board_info.txt create mode 100644 src/mainboard/protectli/vault_kbl/bootblock.c create mode 100644 src/mainboard/protectli/vault_kbl/data.vbt create mode 100644 src/mainboard/protectli/vault_kbl/devicetree.cb create mode 100644 src/mainboard/protectli/vault_kbl/dsdt.asl create mode 100644 src/mainboard/protectli/vault_kbl/gma-mainboard.ads create mode 100644 src/mainboard/protectli/vault_kbl/gpio.h create mode 100644 src/mainboard/protectli/vault_kbl/ramstage.c create mode 100644 src/mainboard/protectli/vault_kbl/romstage.c diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c509c960f0..11f964f34d 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -120,6 +120,7 @@ The boards in this section are not real mainboards, but emulators. ## Protectli - [FW2B / FW4B](protectli/fw2b_fw4b.md) +- [FW6A / FW6B / FW6C](protectli/fw6.md) ## Roda diff --git a/Documentation/mainboard/protectli/fw6.jpg b/Documentation/mainboard/protectli/fw6.jpg new file mode 100644 index 0000000000000000000000000000000000000000..0c0b46d5a73b5fa99c242e9cc86812679b350691 GIT binary patch literal 50587 zcmbrlbwE_l8b7?0gmg+H-Mw^3ce8YNcMGU=N_Tg6w}66lr>Jx+NO%4g{l>lTd;fT2 z&Ttr>Ip_1_JTp5xJS{%00?=h8Wh4PmkirPX2mm~N1Bd}o5RqOYA)vfOdWnjPf`&zg zgN2ESMMFe_N5)LY#>z~`#K^%XE5yMi$<4_0MpHymUQty|m0d{3SV!4NRz+3m83YOy z6%`8uiy8-qS_#MmRQi8ip85b72vDuii7-$Y0B8&-7!0VV&j11d6aWSyEa2Y)1p^BW z_X5&~|EvY1{M!Y9f`);Gds+q{!$1L`(P7X50H|BN_y6(0|F-1^ zN+@Y`X+S)H41fR&EsY&k3X7Ya2(CIeHDT%9t$jZIm7KD=+hIbzMoqqPY1SyY9%&qP2r%zA`VSV9ZyNwxJxeOr z#S{=PQrUX?aokFqWYkVOtW+QYCDw;}7^lScv)ACl2nH;slW%rOy{;Z*Wh(h}Ae_h& zYbn>@%BR1upw=}<(PiMUxh3OooR)T>>jQa3XkIkrqoOH;b;o6qkekue17stI(P(d% zj3Rjxok>~B_LFfyanw9u9e07-%39HouXm+?OC}(D6Mz5*8uIn2U&`1z66)1rPQl5x zZXDFzK&09!V%j7oN|VR+uxA9|WE)>hZ%-%?d%5a~_*xz6O2cN`HM`8|bA-AEe3Isp z`u^rWM1-!FEk_+8AM)YSURny;{Vd_(ux`d z6$#N>>H;9MC2JJxY}N)gB-r`Q{w*R2m2WS+6crAb+7Z(khRFrkVETk zTj3@F67ptpb~q)vy0_)r5<$Ql0mg4sozTcHC>p3-bf8{*y=(m&3ZiX1A}?(zWBNtg zt?k}UJ=scpW7=2Bz=ndf@*VlRGavXjLuGuK+J;OAOg#MjWM>OtiVR$Z%*mVkeR+{Z zUbggz7=kt?4B$|`5Sa2A76i1P!0hXNIsHaki9-7iJX87w+s}{Ls%Jz5wu$AsNE7Pk zN&p4J?8U2{-GlgmUpq1b!1tH(!8B&6F|sO!g~j6sr(3fq=Ao%pU*_7D&VaqvU*+ENH3X9y$pdUGyy8uqX9w#K`u z)JGFG+}o>*wj9`)BDohs0?;VMm~v25gOrKMB+g5vou#>FwgHQ=uDY%@6@#|bh;y0c zjP+&iwy6+p3IsXElQ}FJ%mk|TtQRO#?y<9y#Z<1_aZ}6uxGzQTRzHP{NURgbk406;_SwhEBun6DP<<{q5N;@R6udz-?P!4MQ~)|Z_>G$j9{@-q6SP2j9xhMof_ zBO0#cz0c`d{f%W#1-BznJb)LLv5@iPVh%XlxDT{VAzY>0ZkGBk{{Am~0lu4jM6wBG zT_D)BhghJ2MRmKu+$r2_)QU3;gF8X6?r01aHzN``WW62QWr$i-`Y}L1O+BvhbmXTyOqhZ*=(ybjh**g{|r$vp05@ z-RL;c8Y`m`^}`g1sY^eOD%<9>x4&82xVu?9VBjGWv@kNab8#948nR}i!Fi5YeAk)A z^nj7<$=|{s?{9xCM4p3dFsSBVfEd4l*_KNaAz4m|b+dJe8z1~LM_sShs6J5JIIMM= zsBi^S{nW!lOGahLc!`Eapv%D1ka13ms*XnPr_gPQQpEzX&pH4mY40~a#PW6! z%d6v#`79o3DzT^zr7r1_YXeDmd%ZjOx7{23-;!?y;w0i`rQoE)b|xljmk335_aGyR zz|&I(R!N2K8trXuw-3s?N9)}!@rkO;OcZY%=0}}x(vMTs@#0jUJ+pyYTNsO#W}n5| z@h^U>IWxjO+Exi+V-Tstxp}a}?cme0)6AsBx@0`Gliiy-tII-ViR=7U&G(G06@;kw=1&E>-O>;c&z2F_35enn=?Hl{uNw-S(>m;0GJ?57biNxoaP5{Qc#N7BdK z`xNaaNz&G`Grw!^^Pep-CCj%mR?e$h0VNn{B&a+jeq|r;bJ-xkNlCrg=%G7(+xc)) zY+HF=;M<}20fOG~{x5Wx{+f)^@E1A~GZ67XGb1Yv%x^h05r5dv73($2Xm{IEzt!#G z(^c;FOH4-+5!oNK)t<}5`7zHU>8Q>?c{UOaFX?~ZdV1IS>n1<9vYj#^LFGz?Y%DuV zE369d507U*^O22+9-Lpe&R1s}6s5T?<(D%LZ-{O+)F;R<;2-?VY5gThNYC|ZT()B7 zAKKn#H-?tWXJwy z1L5*TUL-jr%Kdyt_SReV0;0zPB1D~l3?L5vSqF^)#1V`tJKC+4eOek0%t_`_(3fW` zg1&o}G*r{`YUTr&KUQu|@0{Gu+{~)wOk{YfI=h68z4sRAw{yWo=+%GNoG@&EARE$G z@Fb~z+wSdJgE3TGN&9g^)R2Bi5Q=MSraRkLr-7x&0&~*E%}GnuiflFV8}V8Xr;dgP z)f#nfO^=X3_fKwr2PE5o>sZ~18Nb1AwoyrAqNgsUE!uUzdBA+G$smh0t1jB}i-IJ- zWb*{J;#S42-EITB-QE54DEFltW+f?u3cA|Q1}1dObbNxQ3Gu*%P{K2_gVL|IDf#;h zbVuVgG%XW*+X+k%d*Pj(&$)VB`^`%K>-0RCd4^0oA6785C-k19a zy&rDp8|8mZN)RrPQ8BKZ8u8T~xYAwyJSL_$@P)Ug||J{rlP>4AqZ(KoHmJdcdHbzTROdj6#a z0Fs}0rPBjnugnhCWM8a*9bQq_Uvv%~BjE$#Y$1Xm09*tLT?P|jni|KVP$!jaSse`JQTekDbB33us$;;}8 zTs*fbLMx_sGAK4tPj<786LHf28{VWntkP0Ve`J5B={d)~FqLpg-chj#m=Wmys9l}! zvE%Qci26}F`J*Sd40y@9u+NYM7di6*k{)ZsvC9F^*R@c-UKJm38a3xz*^?lw{Bu z%TS)o-Crmb-~$C!>+7MkrC8K2PCv@e6;qDrJw z4nkeTzPo4p5}6}Y!?L}q9_?*D%==p-mce=iCL-F!6SY6wT~|Jps70hsrT^xEhS}|g zDH8xmDHoQCeBKs1BNFZyj7#1_nWgo%9{k&T+pYD~<#cSs?{#FR+6~b71)F3APH{i~ zaFY38RD0>bvcN(=fm8t$k5{)5S|y6jqFo;^+U_;$dIN!njPfja@oYbl0zpB&iyg=? zAJwq0p3Yp}7jgF9!c!P{Yx6S$s<*N7TnU|EL^fK=Y-D|@lq7B)M%!A3rrgb2s)%Vo zPRODh0G=3dLLgIzkBo8wm zJv#vcBOTd$YYq|#C!3Gq<)$K#Spp*Fb9pv%yo|stuEdPr%1;~uy9E3OyvbwtZJdUQ z?o()n!K>4W{eiO#W&zXqjmcy?+!2K=DRcLwjm#91sQM($QY~+43cDulP3-wraGXrx ze|@}IPTeK(Lvh|C9?Y__2KqKKKk8gO+K`LDCP33?FP-`45G~uwixa01$IEMK5<$<5 z!G#1C7M>_(nrIue188dE2KbH@yqch^1z{8$r<%l#$l167u|$c z-Hr|g`Q*rtQCCTsO|#}lITT>0gM)Fmmxyqd;^+n%8crTAR?J+1!zmMyb>+7kf=;%4 z!5{*(wtuJjq_d_eR)`rgobAR6ioLmFQ65n{I=jfJVP8FT-c%PjMivWeu=2 zI;NX10m931|6_vR;l<-21D_*0eLZcCV`oJRNBz;~!dIW$+k^5w8pH1C5O`-u#MqmP z2L45$%#h4bX6K}g$dGmE0;9?1*uh~ZDg+XBO?@EnF!ygv$cR=P4-)|6;SK~uNKt0t zB*$v9RBh~muWvmQHP9rTZk;olt$&zJs-nv9G1Bw$^YSxt#Oi3ciR@;M6yTxS&slF= z4A?BY$%tDCZU6pw1c8QpVjWM$MB@q`D1{^wda{J{Fc#?~7H>^G8;LkIC}nqaH)nk* zAoNhO3_Y$4{2M~~FZCa`Y}D;PR+Q#;-lhJT_8}UF8}ezniEK}{E?|>Nv6RYCLd(EH z%K%aVB4n5%u+RXqgjiH1g3b=EI7V%eEluj(-Sm7GA@JYYL89EJGAhZk5a)ncs4NJD973+gbT)Xsuay6W@k%=T z5=2a5E;3b{@O@-Sz-HD-3nF!ZVub93DpMkWI!x>R^WFlc?^ZUPpKoVowqFjfvJVDa zh)=iB_TMOIxZQ4zvEJ^0#zVn``6!@suW>JBybJ1Z#Ml%)26W*Yq6KlxH)QeRa9)>Q zJJWL7)Gq~m2siR&>38p*KdAjK0y;Ot?fhh?75QYIx*Ic$fP}zYX&yd!SZq16_W)SH z^Tr0NcGRLpp__)Q?nXg=z|5i1U+)4=YOm;f@&HxMqc=ui+}lL6iUKIjpc zYC(Gbe->fLo)9xS02&$!3LXaT@4X=?XaEcbCM-G@_G>nFat;wVG78Q&qO3S#PLz<1 zA_U0x5fmKs6X1-HQD-41-?dTEBYb>{_j@*^tAyA(vD!m_*=`&%L(4U$>RrS|BL*eAph|+g#72}cb1ut6TA=Eu6F`Em);WxXF2)r zc2$JWX>)F|l^&329;4Z~mNTCK!m~>2Sd`7i94hHiYCtGpB@=MWRc`?(+w5U8A8;No zG6zhn{4@ofE=wjrnTZ_{wmwGQC2Erxd!^HEg4`Dgux>1so$Hd*_wfRa!IGZ(|b!&8fFpp+XR<7C;Jy4Ehw3j%ox?*EzT#rkFl@q3fv^lIAl`!zYTWGzQfESt2Wxzt>6uF zlSkj_`Su5XQ~p|T%T8rM+JU98x!95SQ8e||l`GTC-Gek}RIVMVD|!d>C!w?@*9#q) zcg+(3VMZ4j{;yvf%%|usg+^SM;h}N>N8`7`1z-bcG;+QT7^hS|m&M%~ol;%w0We`z zM6jnXO*X-Dx5boUiAo;_pU*LHkP+*3-oB~TRDH|xB7m!6n@}|~`c5nexVPq)e9@q( z5)$gqJ@r7UdW`N(TB`_S`u=!&St9|r1h!yrwNaf_b4HS|T7^gvdG$>`)SgK?&_{h6 zXRl;h8K5S;Bvs?Vt-WR_7ljV};-RR?P^#{db$oJEZWa;#@Yz?ZWT!VjvK2NBlxM59q!y*@~sL z771l9W;ojkOJZo^Eu0LM8sroAv9mr|-&GNfJ;df#jh8x9=*+2FSL721yvlB z-N71MvH{Mts+be9r0wA+?5~Zm*}nQVH&htb{DP-~LcPv%QmijQQvVQG3WM#_{o5GV zE7?jvP=6i9_}zcLaWs8TEu94RSUoqNyxg0)L5f%$2do>1HP;L|Xi%}(wO9aSN;V=h zr3O(D7T);CFFBheOkvdocn!7{u51zGycPDQMwv6(Nx=AG}#;3VN7TG?Q&D zOd2Ie4V6P&I;Dy&q^@*z0cbLhX-Jz6S=K`t`S6XQ*?SIndt0 zwN&7FkKU|4*XzCwXSZ0C-2T8(*%Zb_*|;mw6ja|gV_Fk#gk@E#t$YfwXo6P93;Ja0 zAwPaUI+~U>?8kc^h^(_z9IX8r8kfdhc8hgLpbeF8wdix$J(H!9ob!|R`o&|94I~g$b2YyC=wGhzM*weq^c}K7`UP4}@ zi>T2lI2y9Rn1t5c@rwIOs(8H30d3noe?NnSp;r`z;Z(cr! z153u+xySySUc!sknwaR>m_e_5^)ZGL(NB??fzUyE%_)}Cikh-)YoQ25wqy*F2V+6i z{n_M3e5}aidt|%O1|?M>k*UDK_j)mk`CWL0!tTPxYDhMzrbspnS;AMhIRU*pXD4j} zIh}@FR|%J-R#3v>MayjMa-z9T6EL3EAJ%$Q-_p33tWAN5W9scaQ7ny?(0J{9vD^)3k*w4TxvCVhxBgf^O?Ot5Hu|`RKgR$vFw_W z#E_$4}V!KEM9}Pr552j=>(yyi?1~$a>9f_11N7PP4uFMH^T|d!YQ+0<+x9 z{1(Kd+J3AV!v6brV-G#)GyKu5!Qppwfh}i#O1(yBH-ar_5O0rl-97<~JJHzBrq(7k^$O;KIrbY@fV8~ zT_4}U*Y6@0m4SUP+*mJ#V8l_>#PU%Hx}aQjr6jp%aX$1JeUjX5K35pq5~3L`M*S8@ z)PX)$%28*y2JyAX&gokRgQGUzZ$E1;2`9EpHbVDOO!*zv9Tn%Qkf*B3_sbp&3@m| zxF6`Qgm?MP+KjP`)q-{TCoYGiut(+W==JPh*}=Oa_zctI$JbOon#A6o@2yL)5MQu* z`Z^Z673b*;P%7xVBbF+Nz5eisR_4V>@{Xp_V1L`UAbbIMVRH(v*X%yONLg6dL-E}_ zpbO4h5N?%@qxa=PF4X;eN7!gy6FRV60v zRXpsRf>Z5Lu|K7oY7nqaX%<`N9{NutNk^BXPA#aLoyY3H@*?HX-)L|j~8*OX0J%j+k<>xqUqy|~;)g;{NJ(jXnf*8~VGW{|OGba|5(}}^%sov~M#@mvGp8?6&T?8sc=<8FswQ$P zS_%}HP-CNm{N_0(4UUvvzMzJJRg1M0+@;X_u*$`CWNpimE*~FkI367E)fT;-nKQpR zBTZ0J#uizZMoQPA1#^PiWHVwAc6*oENhu8B?8OwUR`M&SvCor@=6~?*e`#iBZ@=() zhif~4lB(7}Tp#Y9hG4)uQWGRNR_S@4CQsax0X9H<9@Tj5H{Dxjj*AsP9eL^}j9``L zX#?hMMe~AnY74`2^@NF?Rw8*ne17}2mK&R(9XSv*Frd2UP`>!B5x4P1Y>s&s;T{;R zWK3;p@j)dIg!Kg2e$Ou&@p`MyK>B8WpXaM-^iOEt|6*A0Ewr}zohu@A$C0){+H9s& zOAxyRqZJhEQ|>08MZcW(5l?k6cV8smME4CtL#B4Qk(iDdADF8=qz!4&)!BQg5#`wqQzafo`w0PMkT^6rioieY4M>08+D^m}tTY%cw(}zwOv#-0>w4N+JUD z6k%!6T;z3aZ8GMxo81P2uUtq>f&O5XeVKkOy;1VX%$qj+k+e*rVYj9X_7K#Iyym+8 zC%_KfxC1d2{@6xgE-^2Wy&RBy@Ce>$z&2EbmJM_EU2Q9jpxEX+_}NZ|=fDg=<605; zc1f?w%%9BNi0Gmg(L8C3t(z~HDfXxojq;(aQM*Ql$FK0Ve;xhAxzdECFfLeP0Zs)= zrs&#cPc1_>uH@w~XQ4H>Pu`M&GG|76Hq3VQ2W4$fD4TM>bHLp3U5xT0t7AcAU#>%uFSvzBDWL(}p*? z)dOpD*un{jSY_l4M9^bo`A{)ax@$SZ0e%9MJS)D!dinkFr_)(S(Oe4%+=iurv`t5* zsVcCh_OZgDM==4RM=&V;f7GS3IM7wXz zE^zZaD4$c_o2cb!-Td4imkDT4x zlwc?C)VB^=c22 zv!fyoMe}zTw9BD#Sr-Tjk&wds=it=7C|0uLMRoEPD6hFw$cEODj4*!Tof^eva6e#b zI-Ts@XzQ4Pcie`sboT2LQScp)~`?5BV_rkz>DkyI$5TyW51iS!2g z3nBnOJBOzIfnIr@$=H4`_zG_XE(WPfHjv^KVi}rtq3k4Hbr&PQ)mR>!7$9RG2$X#Z z9)+hGKqe6uX8NNYgw@KW;1*(auPNJzob8keMWcom2-aM063|j}@5Z2L47%WG;)`?R zoSfp&Wu639rHA=3vb=p(DA+f zkfGY*5~~Nqna^t#NZfX>9UcErGpC4bP<*xa%b+Tk?FC6kv!M^_-P{o02_lU9jw}Kp zR?H-(l=h<&drY3ev08BybB+A@hE}Dn6GOQT2d_{nBO*#`rau`s`&j-Vo&Iuag#&Tu zyOg6pSq|sR6|!KAS6A?IMtE3mJYWJftv}zXoWrt|`Y7usT&jXWl}L*{8P4iLQ4%0Y zy|S~*^@E-b7IFl)rnKAEv=c*&Y*5`Bhc(*S%-Vnt1X=X^MZu|(&06jxT3V7{X&9ll zG(mwcSd4`XyI4IQ9m~8l@m2&U?E7o6l5#*+-?OdQytiTsZxR z2MU2^_urrUbRQ< zE?+l0ndFSVmu+N+l^tJV8kU&sEMu*%>8{nMLUH7f_a@AVt)-PfS^KpU4}T2X&h_i) ziQl2nqG#ybk^L>jxi0$^mJFjsJ%zx+BvxTUiJ{JAU96bA;`H}2OxKzWW?MoH8q8OQ zaE3H`>+YH(zPS6JBR*w02^E}G+wN8(E?|dz7$!(<=Z;R}=PozQ=K5Nq->u>+x%01w z2uKE9E!T zLqm*}!T)0G?y?U>8YtvUN!?ZY^iHnUrb9>=1M;ez}vIfhUGw3LhPm_?Rgw_!huc)fLZgb-N%?R zFA&y>)mulbjlGHd0*kUeEb>+aEdjY|MA!;sm=D?QAwYK$Mh>3VOzVM6Z%7^dzgFwt zl+WJ|=4CFlessC2FaMls^Yxc+8IE~Qe$E2R7&E_?6fp?gI10};-Phcs6U7;dLsa@bX+CWy5W^A7ET7_<10&v64R}|C;_OWCF@#(gRJ-HkLRrrPYezwCJhRgfI7V6SP<1Qp$;r^%XG7Y?2Fg=@0?1Hg=uJ} zf=y(OD|$l<75HMW{3syGu6+6DA!t~1S?p$daY=C!R&Wp@CxDjAzyH}D5o02%ErJN& z6g~@oi_$KiHV`PEmJ%lE`0v+Ae+_!UZe~b&k7@T>6mVX@4~P26q7U)ap-IED4@Bel zM65wMeU*T2V&UBJr!0)|(Ff8^ z=zmzJ)XuW^MHczjLZUHFG!ET2-@@|z{TMiCI& zt@aNa_y1ypOkWIYAGN5+2^N?$J&vh4{U029gArsqPF2Y9vftA=6{<(Xr&O-Yxc?=x z@F|&PjNGCPzOlq~kCu^0;7tz|0h8+^U*izGO9>TgxcKcDyZm#IW8?GC8yw}y{{5_H zZ{Ruvwm|a^FznvbQA#E(1jeK;+s2Yr{(Z+}``2@sY1Op8zqrR$?Pb5EL7v zw2rAZQ`Jj?5G@tAnt9@=pq&8GVE8kCSw@p5z{R<61jPSuQ>(C?)VpTc_H_R?=vS2T zPh|?JnU7&k8KwVea8U}gDuVyIbgBsQ1q;0-laNKq&KALP1{6ZW<{$7dc^bx_&vh--@>pTI2fz8 z@P~?hz_V@*!Ls|TlpUPA9ffgRgwCJ}ge7l$Kp6Txx;3_O7+kx(*gP`AJm8%}rYp@0 zYi@L^+7Nh%I%uZ-KVd?Y8hw-cu9RMJCl8~r-!4hYshmGpWrhCZnz|=aK`V&3uk;Y- zFCq=%n^%&AN@j_%B!V%c|L9C8{Z>4n^Rs4Y#07>yKEtepcUTP@&Ng|M_-~RBM>eH1 zb;-1ipCx$v7-GuGS%^@3n}tP7R8%aW^nk*C*Bn-yD8>I>6Hepn!uue#{vBfN4^-Kt zwtIAZY}3#GG4j1KEB>i}XMseDFT%9q;loYu=+^7fB8+ zh!DhJcwEuAja~{82@-#ZExPzM(aNg z0-&K_;C_Fx_j^vkWJAYdg(Z8<&HlJx?ixfg}XJtO!ql z{`#4mQd&O06EQ?O$Bq}@W>w!GLC0n9{VYOLO2swO{-E)Evw-{Ewt&-u5YRae2s{0p z>qB6ZUQ5%9#;PL4mOWPyX*$?9@uBwf;fbqIs+ie{v$GGdC)rqiUP^D4#G1?ML+!!C zl_QE;6MlvJV+u;XRwyv$sLRE}#9egkpnFk&m6fwn`6OeFIpxW8F6Ce4c6s02^3|9M zltE4Eb7~+3P!psJ1g8ZG)>S4uN_|h)^;PU{c}NvkS3^tN5}fx_J)iC~sAJuEgOmK4 zp14UNk>646i<~$o9)4x>|GJ99g`GO#v<33a6Gj8yoa5_RfXGmhh->*QhKV~~xDt!Z zs*tX}#tKTz-p@lRm?ot4n1jf*$dL*r@qbBKYR@#E;{*{BrWkUob!3}`>=f(hPt}Lo zp{CV`I`n1^D!X$cE8{3}iS)ePFh^Y^<}e%aK*v`X#nlro4>JUz_n3>bEUCP_R2O|n z`p-WSjKw?wp!`f5toU>`=!~&s!&w6OT>8HxLrJO3@?*-$A}Q;m*!o15hw3Sk>m!Wx zTVW4E7Hz&;U12^!wV;3z8zMoPUa~J4Xc8cB-G`}UyF8KX8U_~ z58^&0vcBeRR8-8{|AC>*7j~f-`E!-JS&QVL;Mq|_)v+R<_78r)biaF{7zpWP&${v0 zf*9u0Ugz~2BVhACT>OrXvGA30kDtwRmlw!XRqr0*es0n10Fl7^PaiELD&Q5a4Df=mLk=qX*BcA_Yx+%s@D-}}!@xzB1y1-E5`iq3zZVzp= z>w3czv!3;#cVFV40FhKr09?68#?X6hmh0R;C%3O+W?_bcy~sZ7zcGtTSkvs+%^En3 z(*%Yrdcb4v=2D*k6~HHehV5hJ!h?3rZG+*(pALBI6!;R}#)-b+kV8!xyAx<8^2b<+ zJr;>?V>wpLTk_Fp<%@T@Q^5$;neUvv4Mm@sMb9=ij*@|eHc!j`yU{P_+Ze%2z!PVex$Ub8Y)hKL9SI75j#y>G7_ zR?EA5{l(2U5S8#mR_kR^Xb=E+o;0&Xb6x7Q>^oa{-VK_h_khK_lc1{*zzw&_eY%CBx0oyk7L<-xoW#iC&4aOqVw3CLfI zubVn{T2~G{`RjluA{J+=B~{Hip{xDjTrdP?X}V<)!OXra#^xf2hg8!I_gyX z+Ny$l*-160zj%9{8_^I2sWN@NEEsx30rM8eqBxRn(xXIXQcVF}R{a)17yFhl@!yJO zk;QAwq*n8KOTAYyMJ-QJx_wh%PnIB+J9>TW+QIw2@1&2sa}M-H?bBTw=-tbHNh|9} z8JSCZFtB&MJqJYyC-JAe{&jtjSf5r6x_%2oxZ|4i4+mBQnt($`{=|`K<-E_Tysi{F zu9n~Lk@vI2zShrn=a8n~1aF)YgMPTinpAnxo* zHIT{XkY1-8M1cT6n(lg z47!^hst5_Xpg)RGof)P#7Z4&6TNGs>SUrpomXQh=Ol`-WNoL=h9YgOFGSPQhkmt=% zZwfIth&ns&6wb(r8T0MCN91st)I-?=z7`@#5}QIQ&ot>sv&%NwBsaI~qf_tUq>rn) zEO>h-dGnH^@#|^{_300GF9+4zH9ugT5R#f|2A2g*Oz_Ot$##EX;MvRLc(Jjq&^Qam z(M}%%7BP3!W5>4ycNltgQioKszLnffj@v>tDo5f2g(I?vyJ~8;;gMct4_ew2E)*Ye zduhK5+%vmTdm_K;uFLBZ!d zl=h{zi3D^(Kq9VC634PmuV7Ye-J~zO8$EC9^7tj;j5#N+O;z;WXeS?qhWfs0c^$Ew z-c&{jKKslMg`u|e2pxZ6rGX8iNssvX*J6-<>%Fy z^p{ni?mGC=n!ygHYQp^vFBOBgU2;~}wng8qP-*C1aPM;IGe(u(*ND2cyUuZX@F*QC*GH=wOO38Sdv>FI=aqg&OSH(*}TVu zJUzPfq+W=axtaUqH8Vo>ifpqvhbgB!olmdYuIlyvwXJ#gmopX$-zKXjX)R&cNE|qh zuZE=+-9i>Y&IIdoVZkd!E&_wr@$B`{DHc|0LC0bh5(M~rt4d1?50q;1p1qE)+^;U_ zFNoKei}f1j6-f&HcW!8|czoiLI-E?GVmJ(4)ht(T{hY#147P(4eT()CLe{zcz9cKm zc%mqr0;w}qluU0UIyP9+O!NGt6~bq;i-)uFc1jkI)KBQ9chd4Y^@sd$M&6RViGRHE&(Urzb}>A-gn*3x_Jt6fk})^~q?$QOp8j+T{0q?jhfFiXYY< z>EAnh3BRV5pUs5_ray|gAcB+U)sxZKqXHWgk4&B&>!w~VYd12tqh{FYHOWesrCH~w zNR+6$bgxIwEq*VVTvi`6sa*bclJo>XRjrM!teI8qxR2<))}Sq^?NPqlc#ymb(8Lfb zD4XF-AYFF2!ysMeQJv|5D)h^^m7krVsNhw+m~u;^8EqcRS}gY$Hv4@IiUV zmP4M6xQRZ)348za zS(iKyJTR%R?{H%iM?|8K2A=ax;-y%QP?2hD4!YBI+L`{+qAf7&j$2?g6gka6d`Mlg zIFLR+NieEfr5vd9^?ZS~EU_T&CT4ay*%~bR1aOi0(0Y$5S!~lyQFgtviHp`(Cwjm# zD|B5m3#vY()lA{bU#htZL<1 z=k`E`j5%K=Dr6B{ga}1Y}OalMczSX*EwoIpVOyOX4MRI zllsRvoINC_!Jsr}A@Xe{4N!g^R|}Q}ceEN;QUbB|r7pu!us#G5`Vl^)xbPnQ>R#>{ zQ0yq0wA42rEoht0lde4EVEl^dU~Ev+_+YC=D42US`sh@!@K8f;TC%9;waUE&=c$&W zg`-xAzEDwlp|d{6N;N6D{Vwp`ZS(>-nzXF_pvPo(4#p-0(+^yJMWry1#4PKUGFfrr zS#!_W9I2XBrR_lYlRQKi2^T?Qm3d45q<||e)SqY~Sal{%35PF!&nc4AzBxs-u<;21 zC)n2ONG(tk!`{O-H(N2IqB-1`W%}}r$=^1uP4qEddAUu`josXnSWTs~3Cr8>Mb)k@ zuq~~7=xlbeg4e60aCJu)Rrn?4FVmz!=k0Yh7LoQEaznCOf9&7@-1L`i5WmcLRg|;) zskarT(5Y2ejU{hRsF<%0mw;%CS3(^g;2Fa8P~perlZU^5iGPTk{DK#v#tidw9b;`!pZA6HG6#ZLE{XA{$eiEwD>9M#c{AnP zbQKIfamUFv$_LJ*B*FfWkdFI~Pxb^@4CACo+nH@SbTXq25&A5Z69d#iBY2xZ>nMlh z`?b6CQNrk+R_nC~p7Yf}%q+i?$&wxqcIzb$WI?~JAQuN>X-zs*_KudDY^g1hoF~O= z=BIeq9b!}NE&Ee7C`Z)MI05Z}qTI`s>zi9|K|*Fmr4j>Oo%#j2z}KLHm=GI2v~Bdk zHPPOewKbppP6{rPbOTozh~PNmnJt}N?MabA@*>-O`ICmU1=qFLUCG!$X`HUWok-dbWdl5=n?>40N z>FcLX@P4Q}V>Es3iR0HFaiTB#UWH^QF!Q2?E}bZi#lFy1sVuoH{Ryy{xJTVmunJ1a zMzxFR$ZI>tEE9gs?~`UJvbpRRbz~r}IwP;Z^(A9XJv-hYJ5I;=U2sx&N9ZNQMe@>6(;tgq>0+k! zc??GafFvvs0|p*5qDQ<<@*K!sFFMk;l3*)aXw8hzFT9(=_ zQ0^C)Cz>bH?5<67oAcWTA<@BPG`uqeQ}p|nu&Qb+ekUat*vHntw6YZsQIhMO6D-%& zHtF9jp3#lAhVwg9>4h|z>kp=RFdn)~9)j&00~(P^6o##2am_$KUqp1|r?Vo6jd!^g&A|RQDmcepYYb_3C1908Yf)m~Kv%?T3&jKm@+tgRaCuoc-Hq z{*Tj&S^<#;JZJ*phM-Rs!J|#i=2Pj>O0O^D&cXcFvt@L%t+O4`)h62d(G^78twv9P zBR0?8C%_NnlAeQFdsi{N+IHq>vW8>fR4q2N7q5+io>j_!7a3!0u~uejmb&*&g#bYt zJIw?~ePv_Q>VZ*GGDpZ{R0ZvQfdPd(^T5n1!w(i?!}|nWv(HLcHW}{hbH{U2F7)dh z6Y$VSfggV&cT;@jgHdsJcE=dbc|4Qr4#VeJdrk zJc|RwV>9Np7p%ubgFvzw0cw5O8oyfm-QTRM=ySQ%FBg}@Rt3+=?y%)+_YQ{!_WUaH zdsc-;vmCaWZGX%D3sSXEe!^Lwk0w{$ff}ciw|J}Gb+aj5Fwb&@pdHOu&}k87mod) z;#L3Dy|viHq&1yKU*1*t^ETvLN6`TL4H}d5Te-Jsayxtk+&i%S7feFIOrMu6Yg;@+ z-5@Jwdj?X)lk=nA~jrT&k%!_T~K^lNt!0u zOYP^UlXt8k>aVY{Myu%?u-(P2joZsrR@~K8lV+vc?N)95x5}?@#T;tHZH7P`9Al>7 z7BNN{rMM@+(#ZR=F<8qUFyvbxSH?{c)mM+(hp_1*#q}|k(Nr%rb(@7d>~H%qTITAp{rmZ`s!C$OHiNt;cQ2);}-459VvNfo0e;#j`$4^xT_Ep5!gx(G)5x>Ei;UnNhTXqk zDFopU&y(V~sbitT2(N+sl8s+e8cC=L7RUDF*5w2FF@2jiALmJAP8k%bt1b4q4fC?5 z=;Pbde~{=9>JNg{mwCUgaCl5R+@bU~NT{ro370Qe>~oq_&CucSEf6|0DfqptdR5Kl z8ei_6*oCP~e_ouW^^-f`IfV=dv8}e3lJ-VcG}^Z4&cvClAPmbB!8L45cJwy5#_@Ww zeOvr)v9anPNEy?xu4sVZTw`+HHbT8It4kC;j%>@+fEy#Wzv^cOG$`I!r9x${Spg|` zp(@?PF_#M>R1cXZpG5rTQ|k|xVPG+q!>)_HYkTO3ORRUVnIk4^j-R)*hJ#Wq!RBv< zSB~-oaP>JjTvi9W?HhgO7rpKA8kG7`w1PvJEhlwo^n!xRq0l)9^c_h!Y#bb! ze4Utb9d_6Lwf8yknrjK87JZ>tX}4=-pIk7=FD`f6)TuEfi9~X>3d?ZO`emb)6OQ6Z z%wgVZ+Ej)O9=eWQpd)ZtNv3xvPXS_`V4sR9DayeG9x`u_a0P*W!d^pAUm|rXM;CoO zWuL-6<1XV)CIpHk7nhWL%qq(3QbMKNE>ZN-`qp!Sxz0mJu35%jJ7yI=yR7C%saU#O znBlx`0E~8;iA!(SjqG)woLr_>Q5T{ud&k;9M{}_9(YmbODsk{9UgS*>dnIY8^!^_EuQ!+9f_^c4##pEI5+aoALf`HS`Z+pekC2nhN6+;0gt0M%;;qz=udPt@{Zut3Po;y1C+I zeQ15?a7$R6y`8-svRBfU=VoOc5)!h1&dJFbc`s~w?IUAhuJYm+^%nK|m){l^B@HaA zAlyGqCm>*iEY~GN!oC}XL{3im7`Jz!%2#F|H3#T|0a0~l(c-6w+>lqRJ^>V zEKBn2TgGK!74l-gH8vg;hPkof_cDA(coQ6K!1aHK`^)G!c5Mq3ZpRQaGcz;A7&9|7 zvmLWzW@g9C%nUKJ9kbia3^6l1#=Oqn=iIx`x#Jt-`}JO{M|Ta?EJ-D;l2l7;O=&#W z)tq&3U_3>>!qx&ot6dE?10}C=?ooA@10{r2ehd=!NVx&8tNr;%gPlbA6g{nd$~n$ey?GX9)F+BN0-&D{fN#UkBNOtU9V6V$ondK2kjwF$JLT?TKr zBf9^r#8ODrbQt=T|GL`O*n~OS7MuGj9}ltK5TAz6_?hY=!jPmdfaYlmstX; zkJGX2ZMG<0gA)%q^E@ z)4SB`CVOhkjfiI5yYx)u;ZF?cdH(I>?+Z^=9?D---y(gRK*-C_DxH6jyjxk9pPk=B{iYROxPJpI1djZ!?MpjO zHeAh~ZUw&WcmOSH`F95wTWPgN1EM#FC(EvP4Hn3FgM z$v{3(V}PLO9koK<#)+FD6Fk{PVH5v>g5BSPz<$jd`PnxEWDWISsrX6bROBNdK!6L4MkHzXpuLtrKTzpjkFj0;?1Z(SW^l#TVHcbXy#Ysu}76AAM5?P^% zR$~<%8??q*r@LLeyREx*j#s}PZn^k%mx&zz@py7_)rD4r_Hz|I3V_r2Stq=EDlFlQ zj5~UCh)J9fU6W0kqnp2wwwG*|KnvSL+%2o64|lWDYATb*%0zHS>;X$8kG1nC6pLe+ z8E`RJv&&0XTBlWQH`yR}08G5j;+I907gvEXV&UanLa>+Ur;}GH-y{G0+N)FwhcIW| z=wYuaU$QDSl{ZOkA1RO43^!gvfo<-mv_Hgbd}cKexFT^}3lgsegW8U|R|rxpM9;l>Y! zN>j|!JVXO+Kf*3F&+P}=@A?w2@zQjpn#xpY$?f2uq&+3DTzj6zS6`xeOE3J=AUKsZ zF6pt}RPENTQlrE4zA1K6jsn+V5Re33ms|Y?7GG`ASm6=6Wr#5C@qUot)}QQ zHWI8IC~MJS%OL?^O&D;nG{Nh#Kk|{HGbO89i}z1HAMkoa&I38KV~sblPk#fFP0J`t z;48TvW7Lf@0$R;-S#zar_)F29?6{9*9c^V5MtObf87phWr0+CiYqc*GnV#uf~|0YOv+5UO1<_IGeCU=*k-Y%I|GM)J`U7|FP zZTgCswlBKnN|6CwScw-9R&t+rxqB?@!wTa2b!V&nl@ z5~V7YVFJK4I2@Hh(lOexyR#z7OQV16k-395b__je(zvU!@0VcK05{H1!YA5e7vYSn zb&gsOH^@>>@&l;-Gv!zM@P)OD8y8UV&dr*vSR9dJyrC3AQ(L#pqM?QJ9`uauAD$x+ zy@|_e&it6oBi~iD4z?LX4BySHgQc%qQ#r-Z&;`b~BU@yLOm%QiT(7$f`{u?&Eg?IQ zYRI0y_EU71liFs(-?ke*@@E!lM6iQi2DL9HY1hYVD%Hv-a)VJQRqwF&QHM`c`8 z!g2SkHVsD>_$bNuvJ(!rT;S81wF``-AU^T8UBg@PC5*Tm1JUI&4J5zuonWri4G>by z{>;q6jbtgwy@y&WUcd<&(Xt51z~28Qs`$;V#Qt=EpWEX_L_s!LCX&g*a=eOuq8Itg zYahmg+Md6f4mU__D;gsm%|vNi>%JI!g$sB7U#M;XPO|+Y?bbLrh3<1_|6%eI=YcbZ3}X5c6uanowI#A!A%O_8*;C_4sY(Y za!z=M$}2zDFIoAhHC-OD%K@%BA+#R-bAiBc`y)AkdiQ1^oB&p;W8;KamEe&;E))`8 zQ3vxeI`4cA7o8wIRItjjP0{4cT>ZH)?nJ45>dqKeIw3;_-e2Ry4%-3t-V@m=U+buqJ|n{9OXI zsfB62dKdc?%~0@5%OmZE**BgG^Xv)@pGh%<$kU#8ql_)lqt5t#BnpMItW_lVm)qPD zqd9_s5awF}Qv2gD55{+6-!S*f)ak9aG3eHsuH6sO2ue6>s3V9ZLL%VewH0tq>sXt< zzX1^2$)BaUCZ_Y^aZj(q=Bzz|%<^B(8}GE;STw)Pm50VEOIas4q;O{fK)eL@ z6U6Pz%-Z7f65*@7&4{dOa`wZ9cO0kai*_iIRS@&bd2Td6%a5<9$enHge*@AL=hxCB z(`rAP0f0x*ikn>R`_Y&nb2+icX2bBham2OdYj7C1NO{tFFu|6b>)n9<9)Wc6zz)ye z>ao?b%Je1dpalVRLHXCO(dhWX;rrOuaoXXdNZ0|&4C%w$u@VUvS^b}3OD*YJrW>1e zj+BnI>AX@kPZ1gMC!nd_<=zg05UZfQO-l{<3_i#DDzsX@3#?>yp%u9dJA+HE@!Wgf z?LKDFdQp+xJM*IqfF>x)Ylc-TO-w*4w?)je7qft>iST6coyil;{+~U_C53LCb#`lr zjF-wGHkUA)=eQhMcD&j{DNrAjGzTXm9&t+d@ea_+^+8i&MTOk`7^tcyR=iIG1OU^y zeP;bFaZ}pLGS8(-d=O7q^UMpD5xo}t#!rA%hHECwz~NkOZsW{r(D)3Ggsj`~6Jd|p z#n?g34~NZKH;=eS{!gKOI{2dPUE4NgMqp3bxZyyq0=XZ_{+pC>0tFfk``u~PRr|1C z>HD{hIw0XCCT~8`jk48-e`reVro!bL7xb#^a=v7#TKWjl-tbWg3-s1QPcj}`QldM( zGf+FX%D1!?Ax`l87)H4Ml;zhwvop|e_{bWO+ot(&x(Z+JHP7?q?B~~$?JN=Btk+zJ znG@Jb&mZX#j1PCj4*dmaS?)YMpmx2zlmBiCnqH<~QGW7Op+P{9KzV!}7CJj@bX9j8 zK$_GDHwn~`-gq(BSn$*Qa1s+TkA8Dlm)^Lj&&Eu_8;ua~MJu*8(OW#jNKcgmz?m9F z*_A{yYufrr&d!beWy21t5>YJyyJ?Dbb?rb&L!7MfA~{mV_&bmAwS6GKnlD7*n&CG1 z5t9VLsp_G&Ex^zswZ#s2n-`XLF4Ge#^+QhpjKySR!+aYRYlWGjh~g<~lgVm#rKVN` zf`gl%`|0ye;Q|y^AZbz9M=PP|TyfF_)Z|&?CZl(_{bK^MM$nCwWu~2eCv4Rfdt}91 z%9%}%SMUP9PnAn30Erb9YX>Mt=t8Kx@H3Iie-yC1jDvt>$M=s}XDXX4c32*Cpp?A%&(ERRs ztGUi;^=LK@{Osqe9GP|IF{?#L)$GJPYGCT&Cli&k80d0ZkZ~9GA0ioI(>NgSQy*yp zIXY#96=(0Gq{@b0Lf{TI3Wl-n-+EC`c%_fuDKQ{D_em#DS``RL;;=0o6^k!~90CdI z_5(WQ{4P}9_XSQ=f8JtjyzLY#c!=NL@*)ANAv=d^fH(J-@EqLP@U4-7!=Z%wX^OqU ze&mOHFBuf3H7Uhbc1@s$K=zvGHY_H1GiQ1tcw98pU$OPwRkT|FsymsAobe8Jcp4MG zl{d=n=|s1w0rx~n>sv$DQ91V_jT;oHCPBq)(Dm%Ud#A-!=g3-t-q=jC!IBd^V*`I< zY+iPWW^2gK0v0radmE8V*YOfrRkVMI35UpltjQ%fLeJ}rI{OPpSE&>R@~po@hSGIi zxD1_1lny~Gjqx|2nS0bvGKn90!d_{K?ZBk_5Pzs+c(!ORxXL!%f@y$w<{_(Z*^k9z z0a&MFRDhOt;S6#?m$*Uf4(R_9yVH6xtaU>HByn$xUp_B4TR5CCwJS3^r(x996WB9U z=6t*UP-eu#j8IeeYBC9_TCZsnq85m3f{BfdQ4j?z?Q`EnD&XBTH(Gq(|3XhceoV-c z1+nIyUP3eM;e!eL@jL#BCYC2xkh~7XetA5K*o8_p4!a3@oo+i&xOZID&rUhO=9TpO zg0HYL{DX0}R^m-CyoQwToFmD(D?N~QpB%R)Eybv5r?CQp;lNVS(mO;dKH@!)c@t0;D>|RC87^eUN+v! z=GP{H2TGba;MJ=*GvcsifXw2WecEctp*VIAJ<)|R4`BCKrdKHjjSA$5muPdy^u}vm z^l|8CsjoU=8F73vJ+p0*-wzeiPGhKmd0_Tups}TGd_V!*elB%L!M#>FWzAue1sl7r z`$6+78^COn$j@OO-7!0C3~ zn|YvaLxw6Kk3WM&BfDy7n^S8yUk7~Jd7phVKpVaj?0*j$-FWAe| zF6vWS*3g{q{S6S6sZJVi>Kt(VDSu7J+j_v&n#l-n+N!n|msOPlZCVLLxQ`?1qBvW9 zRqLW8 zA+ZEvA1k>s`}&%vQm`cf+nScHd~1tbasvpS?fUOSdK_ZrY1z)w_DAON7)12!U}<$e zF{v$uf0ejKv&I{oD}Z!JJG!jOuUnQC{)jJ@bi4iIL$aYp?hE9;dT~kq&VI!tX=G8p zTezgfkE&C~uC3-FB-w?7?+j*rLLVo^9>W(=BcU-7`;#x%X zLq0pi+UgCCMY5IThnjjiL#U;|U58&7oc!|FU&=KXU>Jm~V{@xr4LR%T(Z9aV&pKS; zb?-7q$GP^(G`H8cRvN_XE@N=be0jzt0q(%k>3z@u&K&z!!U-VL1D2o43h|-LvT&xd zC`i<5CGUA#E`Kp;%<;(OkhMl<O zNDqZQvhFG{l9>EVu~-xWO}494qCxv{P0bOi;Av;^5JyLzcSx zP1uVr8qAhrraQE{_Y0Osifg=gvUg{65;%9pZk< zcI5b`FIB17ue4KU*SoDL3H{`+os{t8BL<LWy^=1QH*y)`8L^MK8 zOj{2W(`94i_M#jtX&pAnuDQ8RBeYL41-qf4z!JU=bf^$-Q#fKqpS$$eu;4dKfN7!M zQ#d=A9n-}b?8T@BIt78OuE&ZHh~4ID4qJ!J#bS~FiJF^R*F#S}!QFP#4B`6D){wj~_afJ>ZrHID8*#-7 z6G)F-e)$bZE0?Ozy=ADPuPmBzJ<1lTC_X#Tm4nlmHH|V1B^WoVu{CxwbC{wZqNzP` z4mbZ<)5Or75N}$!4(`0T-6Rj?hN2ZZ1Yr~D$#G$}xHFvp<1xK)Zsa9HAo0xnSl|P1 ziX$_j`FqZIb`#ed;!R}zq^~gbb(?2*SIH8(UNNLior>}k*)Qy1p_27ejJIJtELS%0 z!RuDUNxjPfH541BxC@kox#4q>Y~8%HaI_v+z8Ia8uG~@LYgPK8 z7Ig{$$6VX_73M)Oc(7vC8YWD(g5>NJ^3D3Gt@MUj`2L8jF74%@Aqq`deL4GL{!W-{?1Tt2biY{BO{p0N-Y8u`y6V@uu?aDCVq7o;AS*Y|_pfm{ zrUTb`Co`;{xfv+>oTqr|2SQ7(>lA+gnQ3Sh9~j4_f_$@QRSkjUL~_o+r0tLFTQjU0l7 zJUCz*4P?byv2mgjaS>BSDH^{jvKJ-A9lAF z@zlW(*^~80+ST^E#use(vW8iQP3VEh(9vfY0-;#@ZUa48=8m_|cU(40bI1~vIm3Ak zOjL8oo%@INN0V~D0hX)tpJ*!VDxiC`I6b0gKGZ=%!yimvs^h+dVCJO$1_X!Rl&E8< z3t#>caGRgn%jA=AwzOHj?>=N>0^8J5)nf9H4hXQz#yy8rg`x9I6G?PjWN;;lkVC!E z6UChWu>P2|P<#-ZBGOw8Hz?|Bk*3U_Ru*r(upVOiMd2r~KkeYasTMyo&N(%W9` znfxr91AM)BePPmky>d_8Xo=hF2FXt(c}jj%9X6VeJCaDlKuV~T5XVILmqS)+pch#< z4}9DTif=vUFN5;8F7}BuKZUl=rID972SG zBd8|b3ENNFr4GglggUV@Z!8`uQB`! zPE#PtXnHXZn$SyrHCwfQMp^MNOJ)9{+X`R9cYF;|uSZJ_WQgLCO}FK=hF_BzM-u60 zNKX59W`UdZop4PB3DO_|S~sl4(w|D`m>#~1pYMj&_t4zWUQt4T$Tzfms?FiK23j8S zrstLcZtn4fI^WG{CtJ5I6~fMm(wnA^GT1RmbaJfhr|AJ`>HPf3Q?B!HSHd^&6*^in zkJ<{4G0ffNK&5s9(Dy`zw5$?gzY4=Ref}XPk~4io_h4t#o?f_lTu_$Tbi6@5q4{`1 znoZ9mIv4sejv6DnX(RgiGdzu#vFX5^`#DBRmQKp{3J?IPp}miMVflk+opUlX$2duS ztlQjwxr&Uz4*mr-8%C_6I~Bvh;fU)rQid_N76qMJf0;IvFH61;W^E)xhOytMdXp7s zv&Zdnm$0Ym-qy^Y{`QmOhocsM_ZxzD+#gNVZgtH>wKTv=LCJGYh zJZRIg3oml|;Q)2wWZh$dNlHWATqCp^BTbX5HM+DdSRu4cO9H76j93+?!9j^WWHYRds?QMuA8r*~@8yry$H@)wnj0&7@>J*58 zfjgY?F>%0*sh^+TXFs|4UTJ+m$XqM+Yj6QG6IIpwoV}zSK@RBI%#m21dCl;Jz`4n~ zh~Fyt=J9a=ADOEn8AEUyb@xU;f&Q+92{m8`2t>d}?^>B7YM4WDP779Y>jT7md`Fi4 z$^c+=Q08 zu$@hMbaePCCwkL|QB%`Jp_G8#O_j_mkhURNlEOwr{Z7b3g#pF%GmS zD21*r(JDC(%+Y1IRP7>|7#T+j1yGT9&L59$_WrybmkE&ivacNf2x{j3=)#<-@F7w% z`s_e&31eRVXMyOqH7uS0Pvj6hg8>s}y4n5b;-v9(upnm6O}0h!7*7TdXX0Net6|9P9`lG;IW*^o~W{%fVE`_(9b`MGL69$=W!g{Lmtb$+Yc z^U)xztdq6Dph?ZBtzYRiME8(09*dT=@BG&+Wjj$=aQN0 zZ0VG#Nep9FRZ8&3IcmAvDubXWWp9O)EP8XtX`3F$vB!YOo)m`9hKXp0hFEvQ7F}wV zyiVJd449I}rmEtOmhhsm`lVy1aa(sV|LD^NvE0R0C?xb?E*j+K$klIv>A+95_4Ptn zZxOU_evC#VAHbDUZa$I^^r8&gN0;c!M61<}*Qb}@`+N4_O*=fi+;QCe(WTf|_(Ck- z3c$@D924NOEO66cQ2hL2uQ^r9>G1QKoz0820#B8{82`ZGUR5pS!vXJz{&sy?2Z(u2 zBF|;;zPt^$KHc(5ntCzT?BJMEMVpAtExNM__c1`UIDRT7XSVuyojRbCk=;J$weD1( z@E+Xqsx64~veSWLEj^0&y%b6U@`Q;~kHRgiuP;s7nu~>%LFuN?k#mTWda$S560T51 zh!ENvCnnO#%1(?nk+t9U;L%y3RyW> zu;{hdagClkKrvsv;Erq#I@Q=7q+0!glwiGkepD`d!l2s+NYh2hB6eI~CbeDUlYXv+ zn!$hqSI7q`^)qa;hlxj{K^ijD$bkGt9Dkdj>9qrb*p{|1?~0sd5n!1=f1Jp^!Fq{m zyZ(Y8?E#NaB`y`rq?>gglF`^?+g1kNK@&SI0j1S_Gt^R$Nv? z4A??UC|N~l6(M2bt#1aSE#mvy7iAQmg7d2<&Ofh*;+SE(s z>%=U^O{<4A@PP|G|sqXi& z9~hUfpyj21_V3gExT~%C8(@x6LE4x!n^z^UEQ~b`!n17D9TzOU+Qq-SNF@NZ5t^X`^(9Pvg`TmF^ZGk}-!f<~Mf zKPk4I+<57=j!$hp;_MBgXH??}IvdBlzt`XW^OW8{fL=&OAD1$p6nZl~m8{HWvnhqt zvFv=L%Y7}{y^2$Tr5<}pm-L`Ov#HXP@1RmHA6zP|5~z~Tixjb{@PwL8WpT|b5b+y; ztClCmTH5kXVoX5;doA#@OO%`)38Dlc>gxwZf=p4}#3GSbH1q{Bj<9)4sy&74mpi{o zkPU|d|j1MSrI6gH1CLeXjytt9N~M0To9^9_@0kVS0Iy}_??zY4y!Z+Z*r?BCS8UP2kKOd5`I@v~>=3+?&#G*ybU&q|OhTsa-3 zoQjia(x$1yCv8ZYt&=R)pb92jrXT0)IVEto`qjC*ix|M?%nK;7?3`_=PPT3AHWF#X zTGfUJEtORZT%UvN9j)xe-n_;^pXbM%xePn~Wyn@CA%Z{>;$!4{5Ea&{rN`&PnNL35 zBQ{ST;RfhUOWBIZ7K!C0G;ea#~xFK@CU;99GwG)$q6&q%e1z%_;XS-;_YJ8dvGe2zUrIZ_!M` zX8m%ByfdpYm-zHi330Dxc>6ct7(PW<;SJ)A(x`sWP98`vwHTIu5xz1!z{w_LW4r|c!*FZ7ytixcza*_4QK%=V15JEY#-n3TVCEkRFap!0jG_b|6RK0=05rq zEmEgZ8gd!?{biw~iLtrSFR6b2iF;b3#yT}k<(BL;r1%y~hj;$QgIMPYNTQY^miTX2 zn<=rPwsx;~wfSkPhpq1iq2|#<@<6KphHa#vUENmaT%5ODTDfGDNRdr+%b~)s{5Nb& z2Zm28>ifgD4N8m@1%!@oI$buB%>Sqle(&c&ieSjNoi&wg^DLPc(~~}(YRksp0J+yT z15iWrt%nPz^ux|Lt`70o$26zfvS-M>7F`IN6{LRv+1vjKZxReDBw|NbCq#V=oprd2 znPPQeHyk8rkVOA1&6G)mOym9fV@P|*4Rh%&v;&9`9=vf@GWVaLKgUjzY6h~ru4gLx z?5lALOl$Uad+h>AptAgD=rAR&y~Jso18e&vHIURQV~Z*rK)lNI?&bHtxcO#etVhI* z#}E~{ht;U7Ije*08)OQsw+7JcP`@}cJ^&Fam#ySDE< zo{oBYgx21NF|m8d+<&L?8?c^$l86(p=LVA`N10&by=DdcrjEkkcP?4_znHO6D5QsR z>*mb+uS5w`b5>1zmR2zFpu7Cfa8DnM)*xa!_bOUbyJ{nsnQ0Am9;_1bpCAzTC~2V0 zhDnFqm#=c`CFw;HI{UZ}KQKA}r#An_zhMhHdbGWLkSP?Cgq36HzbWxPWrB(F+g7y<2wHgXLbe`dVmuuMiZ&({O zbM68zLplp*142=T$Ez8qwwEZ*KLqCQ3pSdeC?kn*s)ZNaxXn@?4Vq)j6aWNAAVZ^n zWPGs(V=^@!Qv+e!xu2k!!j9_Bb>g405C>HF-(2r0{FN(8RBLlSWjg8nO!6u9`v5K~ zWeRnz`{m!D=LTVjIgys?S-sRYil(LZW(HhAQrm=qEDjJ=+27%5g@ihv5sY^Iq0%*B z@i19yuRYI!6-VIT=l}kHudaicb#_QVu6dRpn^jg%`VC;v)=fwFN0I*k-<7o?M9ee2 zCR!dSsH%rMTx}A4)Zj7yPgljl@PSXKE+R*#b}Xg&MykWcy4$uWp6NgH{0*341y^&` z6QqUImRS?n@@{@B**EjI0_pJnGn~N)!5o_nw0yGZF>P3DYA`F7Q!M*7{-2=VfIEiZ z%$)=}JlQ0I=4IIw9Mizjw4W0Dq~QRaNMwJiJoXxl=DnV1_k$jBy7GR zLGs<}PRosn(qAcb&5(Ayi6!2Q?Y~nS(}MZXL*J}J{vGQ|+d+sNJYV&je*$Rw`Jdsy z%wJL^MaQ;5vzItQiZ~DkqD`z$ivB-Apa&CEhrR){bsM-DkTec6N=f8RD@)5+A-vWwy*m`^4`bVGff3Ny~F=hZj587-M#4Yjh@BK3VCh9>! zW+5gqViptv@k-PyDml(v^mfC7HjFZ%P zcaa}No_-^sh{ZDtIor*U@RT8^;;Jd$j3;SZlV52i=z1^{nVLx(B@_C}TGgHbSJqW1 z(w5hrK`?=M5auk>mcKsD9zzyE@Q~nx*D8t-#pJBBkg-{{cyHpfR+eghV&hrgaQ=6U zIf#OdU#t3L=-cXPg!7J(r8ygoiD{+rd<;#PT6eRIfwg2&rbAeA;{jZOGxl>InYF!1 zK*O?6KOeg2mjtB>RJ;_-Vtg=?$w?b{NwFVR@bc>jq$+qt2$+T|jO6g0;nvB&PT%2g z!(P(X3ufDNC7V}RxyPA4=wzEFJM;Qpk+eR3F+*SobBKe)(8Iu`OUSYQ<~GuGRX0c+ zbKgiGQLb!FTU7G4hVH~m^+s<29$J6~YIOMB$9L3>6Tg1*C8X-im7>`v%5CrQy!KDR zM}>IOtfSfeeC(P^3VIJ~{-$c3m1XaE~qOcc1inZiy>rM{bGR zGb7=Z$Oh&?mgiw1BR73>$nepO1MRO$?)T0PkUvm<53E0TD*;g z!T!r?lk|$$`-sehn~_$g`U@)ePy6g0)Dw3M3_VQ7Yf$lR7pjxz80|O5!^~7m5d%fN zpsON(1B{hr$l)_>?M@jSw^cROK{xst19M{O22?6NBDYJE9}pK_R&=y9z$@G)b~!1o zHtP6>?z8V{RvP8ItB)hvU$00fk`jad;6FQmw%_bS(3JmatVL0o@e7ALIQ-kLl@sc% zK1|lD`$mxrZ}8v6@f1GT-)0W;Uru-z$eP3`~{Q15EuX zAuX15vcKxk`2&;F6`9AELfGW$Xt*q^Ti+{**3L;>2_)gf5wjIG+ryLM_4kZ#nL1{WWY0}xP=3#q5CVWX`faL4(Szo>s|ZEG8@OE3Q`l#JBuNuagVi#Js@o$Xq>U;4*a@yz`*)AMOZM|$c6xUr!fd2f#*O4Ir;pa^Ro+>0PoYql3M!&wj3 zo8WvgJ2X=vFuPZzpx&~&D!F;FNu5Bt2JsdXmHM){aA5n9jVnh7?naE*^t|533&!C1 zu{gsOYRQ4%{DRi)h%qTgvHI>|ZEHEJY7TNFR$m0GYNDPa%CO1#=rBspyo_YgTFTtL!_-=#F%v}Y6jDS*RH&$-l*WOC^Ii-a zhPrscdQw9>fM0IaXcHE2^C_?m-15bt4P5gfu>o%}Z5b7VM@WU8f8fE(L+mnF zwmHf51qiT91t(VF2-Z&MC5kq)H;vhHOL)iBc`=K@zzJ)x)q}bde#0?{Ib<5H4sJ9p z+!PVQf&qdUKKLit*M$u=LhEu$n{?5Hh=W2E6O9|Hc}j(Nt3cd&sS;C;nyn$y$v`(_ zI~-~akn7GLv=q6l%c%3RcO1zVcC(zY`ZF)Wu>1?JoYL|m_TURUco3_TFj{Ind7~~D z?&r|=(8CRFVX;6aQ&~PF@ZPI`{eZoG zz)enXkvFZ6(=B$vV@?Q3S5i8N=QJ-k^Foo_(1Mn_5~IH$KBdY4-SC3aMq+3iNN%bY z@Ju(5_Ho#+TX-bb5gNH1)Sha_;y#(zC%BR;_*Hec7`!K#@HTa*RX?YphHf_unA^z5|4UXnBgOlhx%AvuRzb9+dy@khyS=z<>31KcWpE(3F}VVL-my~coL zWfx<7$iuD8;s#x*1qxSPtX>0DoyE>D2IcTM)aLzCB}KU>!Uex9qM5|=2eET%l|a%q=n5snT2P3g#T2BNV!Ioq zWh}Lzg|223^WiCo^eOecag-pmF~d8Gw`W`6M)ug^sIM@qW(j1thxB10$BNQHxeXaERITaEH!?7Wnh-S!b^3F; zYBg->x)gCLl8mI8ddZt z4!PE>Y@j_1t_^lrEzLKpUyyb0O6=sO3o)|!Pq`X*oaJ^fMx2y$NfMb#Qqq)5>Y)D7 zrfbG|@drwLB~f3_kMO!rG{ymKMJTE}BbWMd1-5wY41v(~n^#4WjGkSwkwfB6^xfzR z*GvT>bA_C$-70Y*qw^@o2+$#}L7HZ=|Mp$T}(FG@QzizrhHhh9~xU5z= z=}>vUMSs5*|NMY|-fw;l|_` zCD{4T3PMaH#ew2cozk-h6H%gt}vnixG@%_ep?|)^l zJsdL|oVaHXU#=Rx^;qVfc*|1tRI((DwizU`>P!o9biS@+syn0^`j@&g2#W;|IDfJ=Co)D%s$* zZyHAs2JPj~->h_9 zDO!%e^-YNM^(#7G#N>S}gNR?q%Zd&HD>OWG4N_R@j{#U5Oh~o|?Tj#;g6Qys4c|;Y z);{3QmK17Tb_&ITnKTfkb)rMAZ>2pW)6lOAljD_=YgF&hF4g(-zJb&nXegcmQ2o1M zf<;U2N)%3SAKk~m&+U;SJROvRYqNmyJ5rZ!S;OIb=B$otvt%jS+|R-{i5-4>wwvy? zyH=XktI2w9-=VB*vVK@6IeH5RMxt<~?zPvOv6rr}yT5l2+xOe-@DP#(Va6uHwCNef zc(@>H7W63^UW`S=G{vuysQAvX4t}d;U9#=(HJcXB+o`AV*MQrPYH*U$EF<{-(G1~q z5zj>I0-0N8R;|og_=2Q?V9;AkKDGiyg^ zsHdbco~lW@x|HFkjFPT*Qs7ZFci!uZ%uI8$@+bXqbStLt&9UJGUfjVYdIC=gNkEOa zw7)ji0l7aw5h`w{4cI1_k`_lHS|1ygLPGwva~sIYAnebSwr;AVgZO3`TZLNOUVtUa zTeax?K8fXxH<`Fi7KuAS<%At!tn0g#M^Yi(cpnLe*EGpKp z!49z`jhctWj;DV}zs@CQLoOz#p{&kgZ#E9=90>;UUYMq-n6M8_To*V-fE9*pivmNS zrlUPSvZ%?v5*MDDQlaS&d54=5dbp^5ua$4tP-mtQAiYVDLpRCHnKy^73wv@g{vg_k zxp@!f(;KjzJU)P@T4~PG4Dxws*2@o#GGftV?p?M77vV@n?XU-gX7PQ@)r{3A)*!8) zRWqe@mJ(W$*O2VbD{A*bVl9Q*EYLXk6ijZ|x}VBpZrh#f#y~$zsjyo*{w74RY`|J# z88j`SojPm;PEoAs>?CWndhRj>#hv7$0a5Drq*Ob)i=2j8nO1T|*Ye)R$u zpS-?#)H%Xn>fMmH{pl-HJ$s8JbwWMj+v2BIOady;%y-ttbe^nuOC#~`iO4@_uZJUF zztcDj>&#$xL958iK97H3q-!KE7G%&l#`cFzxFpLJ7dXH$XcGH`&l_V%HQPDp<&3VO;UMNJU30y zuu8kxae7f%`9Aup$sjkygDXlubgGOcZvP!NKqK^(*xGS0W;+*_NM-*7;SDC*U%aa?VzR zIm)qmSTbVIFY1Bh(`ZH)6`RFhl@WNcWo+s`ZZj?6q+h7LVe!Oymo>s)x6l{dl8D}v zKn$sY8d?l9tXosjvbx(4uJ70Xq4j$J=XI7$@mO6eTupkb25r5q4jmyjZR@QKZ9 z$d3JpIMI^fUQ%lZ5e}kxh!Ek*HH;jAvvG70!;9H&nAU4NLGQbnwc{WVGW$ol9#xtQkzsYC?r)Gm}G2DcIm5N=f!iyp3>CAJ7ZqIF%Cs`U-EZ|Qq;*SXX<*3hpAG74I%Wj zhB{6+PQ!bayO6cDZb-jN1Iv*Ee>Mn=8syzuz^VMTCF7yl<(nZLK4fKBge8}c@ z*AEhzDxV&h(%{2Rg=D1q*J$%AisJ8lYiI>Xtdr!NizlC#xA88qi_mqckqHbNmw-C` zsKs4rfi(l8sHrs_2c&f}`ta%^Kt;$|oT)UMAQzUFE(3XUaee6rvr`5wTbr_)dMB)E z$}QHt+$5KiCXdRL2%c?E(n1x1gcHqzyfl<`<)1o}xTFteWQK73PXqn4Z2c+f^0Srb zT68!jyUG`<92w4xA>s%K%v?zUni1D@)Kz)o!P+YLGu)8DbL~Fb)p>a z$!LALiUy-KF42iSc1(Sv+sQ?o;l5>MZ=0fW95fn3Fr4PT+EvS-UpEvB`Ci=~%c4rSZD8tssg)4{&>lZa$Ww5lCDQbWPPDiZb#E@d$>BQPb+KYT|ND)@wDf z-q%;Gl|(edve6qRFVsXRRKW244kry>M_FNSf>g0t<9iFmwWFTUb-_$2rjFXyupQbD zN5J5k!UyrD{W_ecost^%gx~tL3Gd@B!a5S*{|WFo56AZ|;0&^&@0FO%nBI-Tnrt0V-)jIED;yb zc8aZ_b-KU(N+_5tAyg?=tU=T>bxh|vPs~tCoxmJrGX}_>6cg4_iYeq<&a(!-GYVG>)Vlg)6z3ydZeab( zESBRM{{XXkkkvp@LzGmj094L2&JKBqC6IS1b&j53@Jm4GThE9*L=dX`6%~g3j5?4B zU#6N_B z1)*~a0FW(qtp~iYMX^BjFRo<*O^d4Tyjd#FDK!Im_+?%O>|;w07JL5y`W)4ULo_Q{ zem>#G6K8g8;`i|q^n+JhjB?N70yVrgA;vVXv^sl3>)vaAmeXpo;GBBwnG$TbV2gt|8^PS?s0D3<8c<_EI^ znZ=$13c~6EMD6Al3gAVug7mlM3syX!7OWmE&BX;2tSq(5eMVFb08r+$a4Ac%y^Qtd zTwR)+n^WTD$-uXq>9=WR2SRG-Iq-MHrw;Xq8wbA;@8;5%1@XcSP-DMZ<7}wPHQM1;fRa{`dVwfRJcmF&jGdkLnM`nRh&x5s$X-6M~#C@fRYM&l# zi&w?Me0SVUOUF+_6)*J5;e?6`s+4cE#)r@TqjCx@qv~prTE=g-1#+$}fE8Y%MTqc_ zL+yQ`Xg$z7sH*^tUEkEC6{#(gsmZu#syn4M^9!9_ze!~I$y*Tr03%uol_*-@v|0$I zXKHiba=ath1URmakz~+YF7GUV&q;Y;)|6Y?kHlP?<~d#XU<;oKRVt5JPXJVx4^!G- zrDRy%*E>_;Yofin6EzyerdD>lHAp;{Q9|+*0?@x!6d9WA3V4HIMS#HDhWGIdSR4X? zGnzz&RYrZG;fwJKwJE)WE&PYc0f9?tdBYg}B+S9JZt%_dU!=M2mBiWfzgUXlK*0sN z*5k$E*7f1zyt@Ic4-eqDnNxB{IeQB8E~_roEY)^%D}xrnL{H4I&FA7$puO2fucW%q zSMYpMf(vg%9400=J8786HbclIUm=PQ>8-H&A{LiaG3&M3k^5QTKQh_EJ3*B>kNOW0?IpuS$c~Er2ZV zQq(TRLcktB$WW4`E~^>wE8wlML#K#^U4;vclF59!Lr?RsBibBQUX%sKFPO}VU@eyW zcj5?0>j2r#3{J1&40rJymGuNOhs4Bn=Me2zh@$l?D!rzRp3v-jO70iLsan-3tkZ|A zYf>RDpTUQi|br2&8sGz-M^LYQ_v3oX_3tpBwuB01xa>Ul8{(1(D)! zc4o=S;6LFL5yKpAY5xFwL%iA0w({u!(QPy9-X1B;aC;?22)3<0W7$%~(|6(T4FGXi zGlxB9G`$>qO>OE|1T(oOT*E??>s;SR_^L|}BFD`+>lFsb4a(||9RN?Xw!>@d4G$l4nfl$6;2+ocZ`n1j>Sr!dH~USW$H#rm7<}F*QeQe7 zb4MLx(OXzID;OMb`Ah{?U0*SAE6+Eq%`-wK%{;&tS4Exc9hmSSa=E%QrVEu_qs7Jc zh^!_cMzeV>)T^GvP z&0{P@apX0ljPo6)MPrqA*7^I05eJtl8hF>l#XuY@c})dzEEp2jR7I@v#BLmF*yhe< zsezo6Rc$;(q{wo-EUU)%7$(?UG;2on8#p0hT~3goNQ!{E?vIuGl?pj)57yXF%BpLu zexWYH-dKLLK*stl)4%Q(_jnw_hWjd-#vf9HEgBsc>?H<^qo+gm#IaFWLP09T^7HCN zRiCsZ3pOsy-SYnc2gMD%%|1`L%+vPaJ~8~3U);62y06SURh8VqZ>oID%g#{ga#v;; z0m-3oJ_VoA_;1-XJz)~!bP#CiHh&)|`-2D5UAn>rPk?i*V|YUSE+Riz41S-yNivohiIem-D? ziq)`1!`l2@3!16HP-@!cE>gz=7<1BAe1ypX#)6&;uA;(~0t|u|RpU6ijOPn;VNqB< z`o^fX*|X2P1R?RMK{WKZ)>M2()c5}Yv!Eh0jh=H?>ooXi4YnE4#Syr&9ku6O;f9Je zrocXeX1bi=G%IzwgTrvJwD*>dnnwn+Tw#~$-EzQjn!QQQW66jz!6wi2cpc>E-dc;Q~5MVjWFQ^cq^Pcj+B(BF&ej^54q`L}p<}40* zo250rdTg0S#ry(FQlc_mkEt(UxuZfPyYV^4f{WXhvAfa&*lol!!}MOyA=B- zu0=S#dO~M~7U-tCLLTV)_k_FB&C|9eD|z#O!!&b!+;x^4bS{CntN=-xS69b=Ki;}L zz_qMb3>Zn1W!Z)#+%}rdHuNDEGNGYIK4r!55ZG|d^o63M60Eo~anciEQE2bFXWCQ@ zph#%jsfVpw7H!#!5{6kE)z(bZHy%KS%&@59Wgr*8TxGR>)D$BsJH7XJ4yg?#y!q^f zgkFI-XIE%s2Bg#`SMUMRY{{XBU)atx`CsNy`n4(g{W?Q@aSP%sPM`c&j4g)!} z_Y^_$ZT_Rm2GGefdb_t?Wx`SQCs}4EV&)nFm;~DS5BVQ3FIkcUrQ&|CWcUOw6@-%3 zDxL#BFe+IpO6x1WpYbdmK`EuaDj8I<;0+&2g1ZJ#BpDl3RIo9a?%noOpn;}=Raspx zGdqE70J4Plq5lBy@ZZGI;}X+Pau02rClh_ehsiqbIufD{W_F`pqs0c)qjIV{YyCu0 zRoF$u&2@Y!m(q|?>bkMoj)|FL&pYNO65a?2e(2@FryG@vH0D$U<`K;uu>4BN78Vk^ z3QA%iY(`V|?hVLjd{y2l!!DI74~4d|3txH$QC$gFufSJ#W+03bfR(XW-|a+v#IlWs zt?MyFr5C4PF*S`LX4b_ajA|+oo)+14MwaWY-T9SskdJAtL2`6Hk(^&^)AdBm>LqdcMpP$4-+qz#Tah7EO%LWaT}nF>i_*j7)(P-XGQ zv^IG_uv5p`7}NISJ^}rIhW($-zc2DjTiKf+TSqLw`wy~FE{5@+eq&YAda;@fL?6do zGu8(ddb^LjO^R~=0K#i6p(^`$=@qL3M5sVTq-e1kduNY$<@a9$3qA%Bcv@qt3NgV5 zr!>i9nV9RySy^Q7Ua(NoP}0_y%|i=oMpB}dVd&I$WD;~%d2?Hi^&8t+Rv7n+twG%2 z*Qfl2scMU*%j)BtJo)~v9L3iT65HRyAp)UtS2v`w9;}`_Cr^o!wTyqPrr`ZKYMR)j9<9}b_zli;b zo>YnNerH$1Hb+5tNF|{a?mp6G#-j*XC#NG}U#BE5^&7Sj;$e6&sm4CHTR8 zx+kf-~MYGzIbt<`^_87a1;NRIcF-xwg6*lywfK z`4-D22~ldBt*?ktG7(u3dg#~jb*@U;hW(H}gvY@W^Yi(iEjB@5>cRz!{D{wsui^!J$5;n@v^K7Vn))N+ zCFbZd`%5=xEameD62^{>H3BUkIdRr#{@UYrr{1Puy8tz_oo)**n)Yq^xULL}18sEB z^^Hj`7^;`7)K1n_Wn*rKnm%ETxj5Y#pm(gmq#e)$pzGVTQJ~{s-j|!kd5QwtY^ydh z`%2b(rrL16wFeR)QKf4tI*P~`Rvx`Oz}65fH+vz>U?ngLbB^%kFWoJ;6%_&n1<)^7 zdzjQzDLA6D&uG$O8e3uh%Pn}|8N3qjfLl3MbnYBUSSyXdlm+PHH^hC05Xf&QSUAw; zw~(O5+whg6R!$2W~G^?QL71379tmd*vLFER!XxVe=ElyZy zCG74OGa{*+I$n;?yjEpfufe?#H@iF|z~eDOPZ z{LJs^HcL{sa+oU-`G>EO@MaXvVk0&gGjun+ z^pC!Vm&u4RNw-Y5oNwv|S&-BWKt<(h8Z^4wu?@IT2G)yQ)g7)>5l|o&Bc;w5WaBNB ziao2WbQ?nE6rA>Y%{tF0Fg2Ab&LxC^#j>{ndH02kp9UJCcl%P&Zs|5-sYoN}^spMs z02{VxwpY$>JQr6)v%jIt3C9I!Elgvc7CPM_06BmGo)-^72%P)vu!}5CXS&<}hQj8o9}w88ZmpZkq*PO>afRMhd(l+BK&# zhD*KeLyPo$%OvXB?u%+?FgH*j@tg(fGqmgmgB$6*OYl^eH662_@Di@tdR$qqFX5M+ z3r8J7c&ON6PJxZP^Bme)x^NDoQ2ezwc}H;jADO7{4>rEf;7T-7%iL~VFK20gpT$dX zDhw~;5}g(T>o=$}m81|OmW(}EA_BmAF23N^nl+}crRw`c_R46}ujqaM0L0bpH0q{B zeEvzuIZcp=T?Ni?BkY$XYKMBbP_q#SOKn!+c-Nt@_WVl_VYuZQ^|hHAK)HaK|t>0-=!rNWad_U0m57{fX ziI#A?S9m2iYp2(#7|k(%=x@=@55^Nvtq{=0ZkZx$ZC>ovv~toOPEIqX45P>B&m=}v`2owb396@;AtL?MXNz-&d1u%YJ!%l34$9lSB-p1aJnrG)p_#7FQBkv znqo$xMsz^3@xc1+&YvDMxG4g&%%j%ma z#9Sa}>dA%5md8oP;j;&DKQRiz(W8^3qGK!scKS@+yUlmZ0UPYwm|{C4LJf81H3u+& zWq)Z?i^-E2V_v*!4;v2e_5T1Ofx5+K6;ROe5d|-T=S8BDJ?YPWX!UG0g$q zJ9UJK4A55Vscb`npxCsm;;+PMV`Phrp8YWB*7~#G0 z0CfqVK{|!SoxPwa4>1H_C3=V_Mf%o! z1N#2}4f`gTaVv|YPk-`G%S_obPNO@}E8LFvok#{-i0aWh(H0%Agns#9O?=)Ty%w^Iv9JD#GpFswd~fUgC+wPdO15LPx2yh5z~whg zRNF>;lkAy~H2uQmQw*+3P(@`hb7 z3bnua0dN{D0jf^E(T?rKD(~y(tTJX+OoJEYCKXi~1JlGH($IK=FrQo|+gZO4q)4rT z+Fj({xs8S#Lg&Y5ft3xE2pS?9$f&Iv$INsSYXrK-%*oVmRs`I(Q~}$@;q4U>l;xXx z%n?Yp%MbuMju;iESZThWPvHHJO!x=&{v-IBQLIjfs5Rq1l6>UZ4TZwMh2VX|eg~fa z0K>%LUcnZT(mUc2S*p6__MhS#`H5MLa@^vMkp>7=suDE?0K(66|~nrGo+9$nFJ>x1#$XI{OtYwr_a< z0Et0G7j$Oe1ZaZ0EMfwZN}*gijAYwe0#$tx&5{pnoQqk7R?#iW`R(|NUzn+i8PBY| zz@pS1^#pXX3OX9@kOt7FB7lXfC$!g>iMLgg;Ofc z^0)s0B@RxXNn)(bKU&X#e_!H1i0jcgIfNUIUZkduQ)CuS_ZWxunS$3W`ok;^Gmb&h z8a|*c^V$sgE5XKDV$mC6jk}b&>iBhp7Al#o@?Z(k$A$r}RS@KBiz`>ksz0_O&@*av zmw+%T=MJ~WSU)UjTLI114EAvjI;vq{dOXT2w2ccpGnNiooy{eV6T@=&-N!j*-fbX< zn9GB7ajRyX+}y?DKMI_R@^`o$LyDpRL>d`n$>uLoFiso1dc?gE#a3%PuJaYq)yrb{ zr*CMF7P!)`)ftwMEY4~-rv+9!#6&nND=n5rbHnc`Dq11K@%fjgqebc9iX}=i>3|&>WT-P^yiFqEwc)MtWNO!GJ$;4zEwA@!)=(XTU$Nz1jOF2ZZi; z6rPv;OE7YqB~)@0L8GJWmn*yO1ZJ^@2t6kPa2?X~vl7Pl-emG{Ra9X(FFd!YRjXx? zmQ{L67KEi1g9pY)LI5RJHZHG=_lUL<(+6Sx%Bbm0otwBUAXvPEIj;-|z|gDU?919L z$Y55M(Bd>!r11``o4)XhU|23`y8QQ*LMT{k*HAhySAy}xt01tbpe}s;N@W13Ki`>M ziyI4|cgxvKht&@(q^OHANEzlcv^lE#09c|yH>cmnvhf!QIDTkOKHNo6l0jk&@8kmc)wVQQF`X| z>DpdIW|ej!>ug~ZZ<}pQ%v~-ORa@T1qHzI1jex#4>nV;a57lH-BZ{+C zh95rg9XNumb)ITrWvn~AgW^3<6kUza+!llzsk*{bh$;lxe1S%?UGJ=_a!wA5V?OfP zR?|)$bDEglh*Y;?)TLU`Pfkwa`SiI|vKF>m1&~I{6fZ%bxH3A%l?PL`w$+Fl@;)ZWEW@GQ@=Nl?KXQbl zahWN`$m!BlSTJoSNzyJ013hK$6z1Ewk-0+#sm&cDpjF|z3Vcdd!a&fk5CrD|MzFl} zhvzcIEL~yePXu0Hi&uw8)gXzH)f`af$UKbqB_xr7D64jNo8f_UY~HxZ913D&`Zd<2 zWX`%cANE@$#RVuYdSVU)3gvCZqu3=t{QVGK4!y~momI1rJjqUKBw*zxhe2DlnV8Y`8j|c)KCjwuCQ9&=G9($Ob{)??={+41s%J_f0$8fs!K;^ zw;wp8kqcp`Q|2;fAZcgcF@S8TuLI_)9a@#d1MnPCZH1LIRdH7K zs0PsIAa~sFr!Ee)N`@v;P!Q6t7>~BC;+#Qw`9wrNqFwLOG!)^Wl))EwaEilqrC%%E zTnco6Z!71-2RW@#?cQ7Z;&?OKMYi!{c$HgeXlG zt*scB%u!2=a^fL-*4fivQFh9bhY9Vo(_4ap0VpO5M|!X%K{OcDNhb}DU3vPn2ct|Oqb?m{{X3(8y+t68NVto zz&v-9Kv==nPP}|UV*;26QPK-&=3}{%wW9r=u&7wF$EV}GG^=O=>$9{T6dJImoh8I4 zQ#xrPX`u?Cw9n5@XSVx^)dH#NOq#N|erUki+P-1-{{VylKdmOO6XpFyHELZAW~O5b^Xqf1fMxnTiDx~u;HW2g!mOA@M|xMr~sv?;HUeI*3q zlx?SouvD62Wxl8bZ4et9h%B1!k0|S=DVsdQ zXNU`mR6)w;(kTWb0c9}0(9FPK`uFU6#6O;Fa3xny`7L#X)2p6lN}=>1wI~@YB-v)` z;xuqju>?miH3}e1O$+OA#13r=@~X3lML9T4$Xr->B~z~IF+|o}=h7~00TPmq(-m;t zChSaCEqC`vY{jaTN>PrD!Z-pgDTgNK65fPr*cA(6-)W*KY>uqn%8v+V8koa|JDTEA z!tv<_cb~Q+Zq}Z#uVE)tza$j;5NE7c<^?L}{Ef3;{3fh%KU2{@G5vqkbtlmsR$E4T zOf7q_Jd(E^Utht)8n%`E%8Zy5O6%_tuswnzv68VY1&OJg@#!sy&r-B&=W{bMteZGZ z;|vAvD59JIM2J#qj7%|z6kr!NbB>d)!D=m=$9a2@A_rd(flEF^+oUcil}#4=60uv; z0#Fpj)+FfGki|J_uZc@IGs`MZlxzyksa9*4Ly8cxwb>nZj7FHH+dlsQX5mQEjH-ZbAmLJ)7t!*~ytQndr$saKMZ=->2dI8o>eu{@D*aM&^`E`yp8)>9 z!hXs1O!%;t4^POM4^!%GhM9$)kRk=)3ZC3ULZwKg?`6v!Y_zPs`bP$?iEve4#H2Ef zi))LD(&7g^6_>mX*?2tSIj%#mgKRt`$yZ$>f`!ViG*WVj0hH7S{{V#mD`O}%)X=}| zF3(N8AyAKR%^$bv;x@Kxq2 z4j~X?)!ODB#DQ%)SD`3m|Br{KdAk8Cd@S zV%3eE_W@)f!KSu-%JWrb#ch2<53Se~vsqt=2*Fk{czf1m2`C>UQzy~`{2kfEZzs_c zY5EXWXA|{3Gvj|>;Xh=n=$f60VF(z6%FOu_hA1nL92ILZ3$)p1E7h)H(M6LknVA*G zQN!&64ppM?OOoWE*?s#&No0YywlC^t)P+>9TL>ZMA;bRwf+du`EF-rN%SztXDmTRO zfLi`dG%?LXMQJJ+1_FY8V;9;t(Pr%pej>YqOVwdYe`+YZ!KXh^{6zH@EN#J`EI^0_ z3`JFTb1Tl=!U{SoUns$FNT9G&owBp6y^FPMO6Q1bbdhD)WscW~;y9aWD*F!e8jPhC zi}nuCWlt0U#`w8l2F6MOkVf0Y8lYn@aR>5$$mgRY$-$N}*787Pvo)M<3j|dV->U=O z(ypGCvL5oVvRh><9y`QX4Y$dP{q>DX)a8FNyAdwT;wY+7`+Yet`<8mitW>v|`^Kd`3Z;{{{V^Of0U~mq+B+Xx-MQ6 zqvizmXzb2RWvvpfhOt1qwo0pnISU^L@3ab82(6XRcmNmG4qp&O78=)@35`Hp&17%V zR1BRXgLb_pOP{Xd131*PrI&-4p`>LZ($;Db<%SUEwb!3%c#9=F(_GY4fG;zMBrH}c z%4PMUYGn$&PidCQit80L=tjb-VQg5{KD_l}EzzY!vt5=7L8`}Cx1LROnabRSj*D?O zp`7t*Z>+xFf>zgqgoKF-N^CWrH}Mghg2*DHQpFKZqT1f>6-(XQ&R&+oO-#*bIhjb{ z%rSoR0bFUd;`e{Ki&4XqOHVF&;#`zfYt@Z)@Qy~@8V@!T(bBP_=IT-gG1u~&N5iRWp|rI1$rM#3UP042jdG$#+*C?a7UBxRA=8*2mbfRCnx0tY^q=o~u-!kn zBahLf6mi7;PfYj+_5K_7K&>FC^$=D){zUnYsI4=GSV2cb^9L~+f|1|6Q*IdQJKRLT zT$gQY%rPK_xo{E3s?rYzr?JKMgW^t<<;h*_fV4Cb<>kFvp}#V zx6OEIfgr8?3|yzKx{}7U!SCE(xiiNw52&i|6(7oMeJpE(h#0u_DXS7wQmIx;( zFBRV6r&$KAA<@W}2=!-~5XvkW^ErrQf`<8EkuSTZqufgA%@Cl~Zqr>Htfa zp|=&C!xyYBic>?{3?8tuy3OH^z(sKmJI5@oJ<{xjDZCzQ_pfLlzc3ctyTOX~l_E9* zQnh#ZxXdUt8hGn4%t2$(G+K!A53~#5Uj2wR2~J-Oqhf@htu zLBI{=_KPQ;o`lu9J9tfAC+K=-#y_w2KNB(HrUf%aLr=f_OwPIeLW;_Ng2LttV}P`v zlu(U{VTQ=$7^PN=yGD-k%0P+;z`NHP^Erv{B!N9ceQ-A6FVbrOPXVgvPzo@TnM08@i~WD%7z~edVsmcC)9SZn5{NEW(`~pc!)&DaK$zh>K2j%bCBa zL1$KO+F}q12oC|inYaLAE*ey~%L!J6!)m0&Zz3G9%In@Z@k6dvj^+Bo3@nXRs;qm* z=J=FTOup!{k9k72m8-L&MFRIZmCh!|U$u4Wz@`5H;Sk>UKWo!IG5vLe z&*FSZuzaEX?@}B-zp1((M4;YJndxQ?|SPv9YP9FUJW$_B9TCDxW zNCg!*wtk{wWZ)ao@hUvTD!4L7C?lg`GmNIgR7w)UKT;XED3 zXcY!r%}C?x%o;E))t8OSLsNVTm%+3`_PK0W5b|f3DS=dD!Hz$B#?dzNP0FZZ4Vy+e zmluE(*tdIutd)GzWp$a-rw*5yVp8n1-z{{PgtsoT>nK5026-vwRKh7+tMzn%D8iIp zTkA3av=_3x!#P44@@4{uQk=0x9jjZ*aOtj+wQ2M-HjED6)yjqmdg$v717uL?#Ihp= z0OOx%M7fpGRejOF#NOsPcNu{-$4Oh&V4e}^s+X%bdi~60v2cD^jJvlAXz@Nz z*FFLLf3^6Iyu z6BUWIL5N>Ra$QsTfm>k0;|BnF1Ph;BVw7~_>labF3%A5;9^|z;RCkT6W%lX+0FX>> zSGB&d23N2Bfo=0!{f45RbbQ8bide&LwU5gRTa^9?5uvx}f{DKb&^de%je=ulJ-C0aG6j6}8Q;!g*mikW^sOl*uWqS|y zANWt=waV}bQBIie`zLYshcodjv@yI+qIyiC@G!F6bSfuo>V_3r?4~coj?aw}AhtFbi$##|o)O{pkuBdKL|LVU6xH9XpiPPk zhOq>dq1wwJn8!}s%hoH?Of=;vm*-K~PGfWf^9>HWyb~l%U(pU8Cca->(c}9600H|Z z-V%rURBf;b4xOS}a00t3Z~hf*>xOwm4_nW~K@9<#D(*VH3Godcsd5;UEZqm;Wnlt} zbMUCNnR8~GnCRcXNbJg`6i}IKi(^o(mzA-yu{NM9x(Ugy?_EF@k! zr7G_5e54G!>I?yuZ-em}9KrR%m-iS=%2=|&Yt)XV(oM*Z5E32M-=_7+v0F>R@Z5Ug&F)uPn)uB{Oz3+PWCe@a{MCDb$>FAPB$PK@ff5~UO=@j zw^D`KX;%)0mX9Z7q(F&nlqrOfdrNG;4aHQhY#>Ub;Z=V`R@`m|g>8n!sB@b(dBQ2Q z*L(apgd>z~x@cw?suQzaKEV`j= zo#tPw6~(nIb&Gj>N<;jIyTKKAY3T$eej!+7fC6bs%*?@<%qy54w}B1nFj&oTD<0^D62ukoJ!S?cbC)w3}oXQOueSd zW~U|azY&C?DdA#Q%p~L%ZaYN)8Umq9$y#y5TpeT-(yv`1H6n(_28~xSRca8)&9RJU zqxyf#2?quAzR$2Z)0^a0lD14CdkOe>;c5NO%u3PI0moqyeRh&*^ zxrJh6C^FDmyM$^C7IB7OvA%3#Sg}22oHx-ikHCT;X08yzl)Nz(lIC=PQo%AT9?+$T zxvrlO%csOPyt%}sU(zqTE&;6D*GVS)4r51^74W@;9$3&AFb%G_Q_pF2q*3%o@%@h3^5QP6 zjoFtwFJt_eD_;lsJ1llT$=Q1!igEorPu4#Z zv;8|y);|;X55)cB@jDM^`8#jZwB)XPALIh+x7hyxAQ}gu{zdokKgrL(gZ!F$b*y|v zHr(GI +#include +#include + +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_3vsbsw(GPIO_DEV); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_kbl/data.vbt b/src/mainboard/protectli/vault_kbl/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..4379ed1a6e87de263d0796ce55c8cfd368dbacb4 GIT binary patch literal 4608 zcmeHKUu+a*5TCuhKYQQqUbkD6W5GHi!nHuVSD-?zve&ypk6!6ruhbGvxWXOMc+k=o zQ~bvnYeHf$_n-z1(I!4<@TH0I$ryQ2Nr;Lj{&|xZ6D69Mi17tjXaBSZG|&qPDu%h6 zZ@zDK?zc1Z{hM1c(9w_C?wzSvcPF}(2OWM;4pKXxI+DHFU5QwKY*$CBH{Ok3!`<+% za``+!p5vBCQC*KF4@?w_k-i3kO<~W-?%`sgIZ+sYa$;l@)A1z6_UtJX3u8kQg*;{l zw#LxHlv&52;bI=QAKJgWFxG|yq?0v9*Eg+Oj~H!kp|2j@KwZ5p+S;~ZlgtvG@!p}VGB(R4xa6YIpfP+gdKnf5H5D)|fyasp? zyb2fyh61R70N@2M01!a2oKV2Cf%A}Vr2zi0rI{sy=k2~>8M}mD_$CL6BAh2Ai|Fk> zyQ6SOeTUG1&-PhX7hNmowe%1<^teWVX!Xb{6r5GfN)DY@)0mtlQpkJPN}M&qE3Iag z|D5D0+>1}s``oZO;4A_NaXRb`*27jl0u#Ikp655ha_?ynf(WaF3OqubAwJ_{@GbF= z#J>>#L41ig;Ac=vyp;F>;%4Ga#Bt&t;zx;xi2aA)qUk9?z>c}Zxw6)gpm^bx1}L3y z^(S0?@OPSQBIZibmA0~q#xw%~xNLqI2GbNCwmdKhfx_kzE>f2(Q?}&!v^(x6Y2|9r z9h+t_M?(*NZe7dH04-#PO!Ic{Np-M|HZU)=Pc5@!*#Tg_E%Pu5tk&IYq*tZcMQIx? zdJFuT6MCTCk@MSs^ND7yfTh2B&ITBq4P4-k*8MkoR@RgSK2ByUOU)VIY42p<>I^LF zg71Q*GM>9f5pv6&XZ1Iyx%Y8elOBN%1_O|~5_CZX!jOO!un2OHw(BOrK4-6TqB<2K z)L0wz1{BdC1ncG*oFoEhcoq1E7!EOYoU!K^zQfcH8T*9cPfY!bF;2u)qPj_BaS?|_ z^%;@9B;xy``mxA97x6byHANPbuvt=L66==mprpPiv11Z`AgP~9>?;ZXl+=LCYGr&- zR+BQz%6M2-UzXWxGJYhhU&!ox8869dO^7WC;pUK<39-jQa--@idCqaA+K^r72xAhR zJ%b*}mKQjMq_1Wb-E#9MrS%A1_ExkS@`Ij*5vFSpqJzsYQd;EXsJ``xbM1j<9p?)p zdQRt0uJOjF+kJiokKtHtl+N4jb3Skm6 znqnwdAaG^7`l}M*z2?bt8EvI8c)a2RSN7XJ82*_meCXP2=(}fH4C7PV;rvrXmcoK|n>=*|VrrnhWYr&=jcO%###()8%e z{e;k1nTxVrr)bl@sVdgPn+?-vGgHg;^c#!k5O}alW6khagP=DWr*l(zJ)CjsL7*sj zIy#7Mc1_v{vV-8mDxx^A!E_oI>yjR?L{X;wNIsMT8}0RAE%NKHYEN4!d~oAhV{mO{ zE_kSMe4u|c3-5~t19By(%PC52#Rob>Egw=_(!0__2MWdQL;DN=gMky^joQ^OfPdR* zs?ks0y4JjgJlD{gyWrRsaxzJk`wqIi^00<`9e(DUW&n=P(QVOPH}9YAjgo)onU#UR E0bL-x9{>OV literal 0 HcmV?d00001 diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb new file mode 100644 index 0000000000..d53e43eba3 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -0,0 +1,309 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "s0ix_enable" = "1" + + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # Enable VT-d + register "ignore_vtd" = "0" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "tcc_offset" = "5" # TCC of 95C + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPwrOptEnable" = "1" + register "EnableAzalia" = "0" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "PmTimerDisabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "SaImguEnable" = "0" + register "IslVrCmd" = "2" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable SATA ports 1,2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + + # Enable Root ports. 1-6 for LAN and Root Port 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" # mPCIe WiFi + + # Enable Advanced Error Reporting for RP 1-6, 9 + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + + # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # Enable RP 9 CLKREQ# support + register "PcieRpClkReqSupport[8]" = "1" + # RP 9 uses CLKREQ0# + register "PcieRpClkReqNumber[8]" = "0" + + # Clocks 0-5 for RP 1-6 + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[1]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + register "PcieRpClkSrcNumber[3]" = "3" + register "PcieRpClkSrcNumber[4]" = "4" + register "PcieRpClkSrcNumber[5]" = "5" + # RP 9 shares CLKSRC5# with RP 6 + register "PcieRpClkSrcNumber[8]" = "5" + + + # USB 2.0 enable ports 1-8, disable ports 9-12 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled + + # USB 3.0 enable ports 1-4, disable ports 5-6 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down CHIPSET_LOCKDOWN_COREBOOT + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 off end # Gaussian Mixture Model + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # Thermal Subsystem + device pci 14.3 off end # Camera I/O Host Controller + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 - WiFi + smbios_slot_desc + "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip superio/ite/it8772f + register "peci_tmpin" = "3" + register "tmpin1_mode" = "THERMAL_RESISTOR" + register "tmpin2_mode" = "THERMAL_RESISTOR" + # FAN2 available on fan header but unused + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa40 + io 0x62 = 0xa30 + irq 0x70 = 9 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl new file mode 100644 index 0000000000..624806ca04 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } + + #include +} diff --git a/src/mainboard/protectli/vault_kbl/gma-mainboard.ads b/src/mainboard/protectli/vault_kbl/gma-mainboard.ads new file mode 100644 index 0000000000..b7cae7837a --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/protectli/vault_kbl/gpio.h b/src/mainboard/protectli/vault_kbl/gpio.h new file mode 100644 index 0000000000..3397d79882 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/gpio.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef _GPIOFW6B_H +#define _GPIOFW6B_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, 20K_PU, DEEP, NF1), +/* ISH_GP6 */ PAD_NC(GPP_A12, NONE), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), +/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), +/* SML0_CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE), +/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE), +/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_NC(GPP_C16, NONE), +/* I2C0_SCL */ PAD_NC(GPP_C17, NONE), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE), +/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* FLASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* GPP_D9 */ PAD_NC(GPP_D9, NONE), +/* GPP_D10 */ PAD_NC(GPP_D10, NONE), +/* GPP_D11 */ PAD_NC(GPP_D11, NONE), +/* GPP_D12 */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), +/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE), +/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE), +/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE), +/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_NC(GPP_E14, NONE), +/* DDI3_HPD */ PAD_NC(GPP_E15, NONE), +/* DDI4_HPD */ PAD_NC(GPP_E16, NONE), +/* EDP_HPD */ PAD_NC(GPP_E17, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F9, NONE), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), +/* PCH_BATLOW */ PAD_NC(GPD0, NONE), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE_N */ PAD_NC(GPD2, NONE), +/* PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE), +/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), +}; + +#endif + +#endif diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c new file mode 100644 index 0000000000..e9273ba907 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* + * Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. + */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->TurboMode = 1; + params->PchThermalDeviceEnable = 0; + params->PchPort61hEnable = 1; + params->CdClock = 3; +} diff --git a/src/mainboard/protectli/vault_kbl/romstage.c b/src/mainboard/protectli/vault_kbl/romstage.c new file mode 100644 index 0000000000..e65151bc0e --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/romstage.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} From b9f9f6c12b1a98ce76e3546e9f900ecb45e3c95c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 21 Dec 2018 12:23:27 +0100 Subject: [PATCH 0359/1463] mb/libretrend/lt1000: Add Libretrend LT1000 mainboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks --- Documentation/mainboard/index.md | 4 + Documentation/mainboard/libretrend/lt1000.jpg | Bin 0 -> 80098 bytes Documentation/mainboard/libretrend/lt1000.md | 117 +++++++ MAINTAINERS | 6 + configs/config.libretrend_lt1000 | 5 + src/mainboard/libretrend/Kconfig | 16 + src/mainboard/libretrend/Kconfig.name | 2 + src/mainboard/libretrend/lt1000/Kconfig | 55 ++++ src/mainboard/libretrend/lt1000/Kconfig.name | 2 + src/mainboard/libretrend/lt1000/Makefile.inc | 7 + src/mainboard/libretrend/lt1000/acpi/ec.asl | 0 .../libretrend/lt1000/acpi/superio.asl | 0 .../libretrend/lt1000/board_info.txt | 8 + src/mainboard/libretrend/lt1000/bootblock.c | 35 ++ src/mainboard/libretrend/lt1000/data.vbt | Bin 0 -> 4608 bytes src/mainboard/libretrend/lt1000/devicetree.cb | 298 ++++++++++++++++++ src/mainboard/libretrend/lt1000/dsdt.asl | 25 ++ .../libretrend/lt1000/gma-mainboard.ads | 17 + src/mainboard/libretrend/lt1000/gpio.h | 189 +++++++++++ src/mainboard/libretrend/lt1000/ramstage.c | 15 + src/mainboard/libretrend/lt1000/romstage.c | 63 ++++ 21 files changed, 864 insertions(+) create mode 100644 Documentation/mainboard/libretrend/lt1000.jpg create mode 100644 Documentation/mainboard/libretrend/lt1000.md create mode 100644 configs/config.libretrend_lt1000 create mode 100644 src/mainboard/libretrend/Kconfig create mode 100644 src/mainboard/libretrend/Kconfig.name create mode 100644 src/mainboard/libretrend/lt1000/Kconfig create mode 100644 src/mainboard/libretrend/lt1000/Kconfig.name create mode 100644 src/mainboard/libretrend/lt1000/Makefile.inc create mode 100644 src/mainboard/libretrend/lt1000/acpi/ec.asl create mode 100644 src/mainboard/libretrend/lt1000/acpi/superio.asl create mode 100644 src/mainboard/libretrend/lt1000/board_info.txt create mode 100644 src/mainboard/libretrend/lt1000/bootblock.c create mode 100644 src/mainboard/libretrend/lt1000/data.vbt create mode 100644 src/mainboard/libretrend/lt1000/devicetree.cb create mode 100644 src/mainboard/libretrend/lt1000/dsdt.asl create mode 100644 src/mainboard/libretrend/lt1000/gma-mainboard.ads create mode 100644 src/mainboard/libretrend/lt1000/gpio.h create mode 100644 src/mainboard/libretrend/lt1000/ramstage.c create mode 100644 src/mainboard/libretrend/lt1000/romstage.c diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 11f964f34d..970f18f007 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -71,6 +71,10 @@ The boards in this section are not real mainboards, but emulators. - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +## Libretrend + +- [LT1000](libretrend/lt1000.md) + ### Nehalem series - [T410](lenovo/t410.md) diff --git a/Documentation/mainboard/libretrend/lt1000.jpg b/Documentation/mainboard/libretrend/lt1000.jpg new file mode 100644 index 0000000000000000000000000000000000000000..c450c4add354331ab951955dabb16e0b8794249b GIT binary patch literal 80098 zcmdqIbzED|^EVnOQlQWR#jUsmC>C6byE_Ca4nc}Lv{2jw1PE5#p#=Aq;uLo;?ohly zp$~lI`;&X0KkmPG_Poy7?Ae|7?#!%C&Y#&oKL9TjWaMQ4NDst{#0miXSpY}^FwxPU zqN8Cxefks&6B7%E_yrC&HVy>=Aucg36+Imd6%925knc4EGY>O04Tm@yqbinwVnPxLc7Vc#^KaKmkfoi1WKhsTwIb@}1rE zTt}-;Z0N1~?GC_JN<|ZomyvQbU0ehpNeFk%sPfXE`Fm?|f=WF-W9nj;-RWAXRN;j_ z) zO83g98}>zQPhNd5BY~k_$TR#27I`>QxFn#L$vXoK6l(8K95ErQhygD{lvO8^ z_?L+kMT$g*?M=UK9c)8Ht}I6Ita@syU+PV+6ba2vh7|hv-ERCVT40tH&G4t1xboem zLi=7{J-2S1$ovX&;Ne$#Vn3h#Y3gFR{QO51w(>XJix z5@lU_x*z(x>1q7F>$Ou78&m#k{$>@{dPk?bx6*fyh#=wErc<{R z-ekD7U0YTgww#Z5U91UvoBvi^fDZpfy*cj;d+YFTmMK5CmaStC=kx}zmS5{5-UA}7 z{!VPif;Rmrh3*5TJX~(9gl%*Mn`VkqY=&Gl2adT051jX+z^#^>)uJbFS(TmI-32bJ zjf?zz8V?=;AL;4(&|uTM*{|!qCp9Da^YLz5tst`=5pDLWO>C_igOwDOl{ga^{;kL&SX z^Shn($~S2J6vNoj>Ci_!Byw*OOF@|p+2q}b+y=18aLvs2zW40v&zfH6BO)0tB)(c}jN7u;Yo;hU%^b(6QoIM~f@ru5=uu6Pf?d_* z93SOZojQc0YwWWBN_OH~#kP6eXz6ZYL55cAy>VCLB++n+Bupl5~Z)(oF{;fTPb8wGAF!eD0v9@xfqw$mR;ggM44#dKtCn4KC?rEC- zTjqG%LK9VCio*fMdwi~2BQK4(H>TT84&HD*6tZ~op-Dv_!%?7(lTSpyA~)OE#|bq> z5H@h>*w~ZdPnlknT{7|+fCL(nz|XaRC;&i}97$%49i(4i)!(X1we#DvUt)!T2vxTLOeGg+#aB$Ob3WT*ACv7FGd~)pD;fTMLA-lQ8AfYGrkT3UOL&fg) z{@D=#V5iGr!1u`eNgAcaXF2`XT18R2Au!i6P87Cg-aabFdo*uX!Kg#7V+Uf<#;|hSl z!q&z%uz}O9LECmdW8E2=KLV%@NQbukuR(4^A3@^C?nzP^e75etEn>nN$|~0 zjLV_<=YM$%RB!iVV1>zq1s@I!yW6Q)swilW>v^>`txm^{{+x}oj_<<@31)c1^^DTD zkjdH`v8c71aW*++zj3imcw$|YHSC#Ydra`_27F^1bIYC;up;`yMwbhFNLi8L%hn4b z?5EM0nke{h?7V^e^YFz@t085l^8WH!WnD#T7|YHtfA=*VFZ0e^P}#wvUe<`!04AHMS7yw9a#jDd^{(v3FRKTW3-HjS z_ZDYuoFl_$mb+%trbDobeBWN~N(ZMzRerG&V1Hmj!(bEd>iiG+HdY}ovAUH zd%dncNZydky33|Nmp@F|&V?M06mLNSIBVmU6r3M)*7Y{`otie=AIM5{ThG<)H53h$ zmUq|(U0+>L2;ZsrzX!-WE7WqiVL#$ zqg?#7-MXj0zQ3>EHS^pE_C^DMCZ70;(!5Ggf3eU$PCZ5s?38r{5>ymg4TAY7e`|NO zScaUf)UAld3cd$?1%O!pn*P78I~V($P3(BPFZ;inT=$jo zyXjp>UR*JZiho9+0HSVkWPQRQzAb15^Gs*$fyZxa>N^0B$z!40ChUV~K9E@Gy3ZW1 z`<~wZ*}o(86ZGhzi9)j*N@YxA$H~^E3jIk$Te84$-URM>H@k>>Up;;eyqotQ&o!l*OCU&X4l;+ z_T@4^-_-v?i|DD_ANfaYszdWrDHot=NFuS4wfdkBXQrcVZ-;DUlfmgtzj}o$B-BOa zLzCNRt9G0+33}Ro7c=aNz^5hg_Hyo6^s^l#!YfLe!*}G;O}RX6wb0c*RQVcOGTP=&aUA7K4&ReCv24&d&m4e zC+zi7GUmK0BF*1#D#X7P$Ko~x1Nu3a1WxwW8DYDxhUN$HruO>>^OIc!vN|Y1oUw`9 z+7MgkOzslRsp{G7l~)fak7QbwZlZq{&`y5u6SS6{J;qREEgGe9>b}*m0GnNODad0- z>|_e;#zYSXG!OKK>D826MF2RScIk^u0tcJ~trZy}@3^*`>}v?FGJUU8cb`*^Uv4(A z*Ks@AX%4rAsZhlJr$-@`Y&5&9Uu?JY4R256W~PmA%p}i{&BFwaW30v}E9fV0o-J{Q zR2tU^zF*a)8;z%a_oANW$+C><>j_+I2tBOwB*PKH5VU4MwJKo%W z!Q%Rqd8BC{M(#2zjJAWMin{eM)4`&eGGAb_UN8LiCzQIx`+W0qo58)^alEiCisG63 z!!-9dxs;!skWZB_DM5rq7mv;s(}%mf8xaC;VHME9CK_qumaK}ImvzQ^g-Z5z#zIz# zxE?GsX@|YU^L8%E<^uDEV}u3ap`R1xBpaA6VpAwjC_`dm#<)KOr2X<`fgmnFx?aEElE!~V5oPsxQF$1|GSca+`& z?xQREJLcdR>J){JIAz0ch8c6^O({7m!F>81vYd0uu}@9OGDk)^q$q7^E=m=j4iH-@rLGNv$843~_cO9&zhOnooDIoWdEjc_{V+9$9o zJ=>jaIv2Qbu6iz*s<`B>JW}Z|>LB2rn5`h`#`Uvz$q*+3KzkJ|W#LGTbmmp2O z39>pkxKP0WW+^Sg*3~qbutT$C@qQbo1j8`Z5Z*Md@EpbmB4uTqjTCZMfU-h8`{Y(F zhvb}F?z2HE{^TOY=|$;vv0ngOW?R+Nrb&+wNNZOkQR@3b>>5T}#zs8Db(3|lr!c)4 zjVB;veVCGyORFbsv7=cHF)33>CN!qClG^@xw+*zO3q z&uGK6Qg!c?1X&z67bYfsI?Q^=pp#YRXVZho0G)=fzmX^Di}hjaizu z8ZKZ-?+R(Gb(9eYpD7@uzzUh1CRslrMs#r+&-RQ~Gd1+f7yN2_m7U9$vqfx8dsWRj z7yi};Q#@e|w&I4S!TYC{tL6q;{X@%M8w*3<_xiDu*7TjswdWVW`7FmTb(WypngkI_ z@lX<4Mj8$!8NHhHg``%WHEKZ$fuqmsIv0Y!{eLT8^UHtSx!7bBZMcZMp5cPbxvkG{ z&pt{i2;eATuLl5#Q~HvU2rO}T%L`g9*1JN^yNtY5d#hx_!0ejnuP1s1J|~*HUGSv% z^0HdSC~fN@6uH?1Yj7uF(yjVE2b)Ank~6UxzS^79S4uwQ?mxKuQ!vJs-}W5e2wzwR zhXvYB#6hx6AI0`ax^ch}cSvDId)fwF%TS2bw;3|&#RYJ)t*K&%lIrW!!{HH17>H*m zmTgaSs240hqG@ZQ-%noe>OSpiS-0)B9lei&SQsjoHv2wk01+I~#wiV2kRtO?~9w;I3i(p+-REb+D6AuY_HtLxloK`$Q4W%-@5N*5v47sxknr$yK;%+sB=y zAFRCY51cDEU}1TX4yRUb-7Udz;uYc^$)5us4iuhLdbXCq*U7%{PP@(| zole_Tp5*63cwxh!g)@&IH(usK$v|@*LJaF^+il~)BFYibF8~w^3+ahh4`O_xnaMYh zIyv8To8%cK(40my2{izTBtY=b7Tplo){Ybvdpb3KwpM~xa&h|Ug4w)eEN(r!O$9++ z(`mcdJyGq|Jcw<54hTD9HgeFM_hUnyz+C&xzruR}0HB58c$Nt0DIcsKbIuW-P*Dzo z_J@~23i=K3Oo4OGc8?R+6h-eDM*W>3jqXUpOz-LOW46&{kDkx6tqUw$JBlUgyxVPC zr^9WW?I)C;?RwmLNf`Diyyf+Fu}+BH-nxgq+5@=^DVvw5Z<_+px!gXCph3c#teEw6 zN&8)^M9xY>iWJRl;V%^izhm4JAS?3IlqPGj- z+nH9&KR0I>o~7}PJQ(ZwP^(==gMC5zzM%8I>%#)f!BQx7IOj7DEr{V^2ltFpQg5@| zAmx+hWMZ5$&~b5dyV#vjI@1h=Yant`u_BYrio|Z)5W;hP?6YHBKewg?!P9E#!iw-v zZ2k^U-n2Gi4~XF#5E?Nz1F~9c)i@mUsJ?Zc`)jlUu*4IylMa1I1Uwl$CNF?+rCaru z6oS|b40$&vv=Utk?bAL_V{fg`kf(8Es-%{I40*R|Oh_rG-9KlEo|Tm}fs#SogSo?n zHHuzvyDE{}=*uwh?-XOuz88!`Z+%|nx8;oJGH8DDuNm=Cicfmnwg)$7@@7&D`9hj9 z>}a?ICy2DG%cqAcAmm$hgO=0%<=xWhuV@iRH4EE~n>Cgc+Xd+q>EsG|tSq;oC>%sCZ_Lw1RZ{vw-J}6WKuBB1S{fAN#`X{=Avg zGb9(O_Hm>z_sG))O}rhatm^%wdIt-E>FfQ%CI|)l@3t$Px|-?bCa>7VwiU|SZTY&v zFMHxK)*{uFLXMoyg8P-a7b8tOCxrz{TEx3ig!jKj? zUNZvWn_Y`3WJRjrRd{m3v&9*K$+E(+xy|u=AB#tXe+jvDDk>h;yM^fC5JQLk4Z+p{ z7|BGax*W;avHJ_bSqteGz*DOR<$o9Q{}e;@E+cw{dFH_mAlNDgzXuM@HX^rsn(HCA zE=9cuZhL^<16~X{raw+$|Be2G000i@H34+ftKXse9rb+v3to5l00IC|!>SMLQc12C zKe;jzR0#)Dj> z6rR0Mo^AXZZ2JGq@tDGtJfygZub0&e~+=W=P50sx~MsZmq!0H&MpZkH)N_V+H~eR(B1kp)jXw6LR4 zfBr`tnB#*M??-W!6qF-htq!KsIDo4C!yJiZbrTd7rLjExyQgWYe7(M9-Ao94$F=Bo)eDShUG~X1 zrqa79ckdc(wY5@q9(QE%2RT(y3{5bm9(Rs73Ob)3E)40Wm?-wP1JS|5o~T_L7xB8o zzwfIzCw8&YJe7id{y};=f{M`!hJf&mWI&vJbv*?;vu8r_>DE3F3bP}&g0IX9!yRBt znh|->2)DL?6CKQ`W{7Mqe=&t%^KcqzhX2fuISuLnn0AcWmb=iewhjmyR#KmY4R;xp z0AKxufmVb?^qmjX{Vl}W2TVG&wXT^%HUph3g>JX{tj-&fv~gz>>ab_*+_sLT_3B(3 zZnp$H*CuT$nN`7t)x}sV?Pr4b^D-UuVqz_pAkhg4_&tgFWSjYI;CTm+wIJ6z8o}8a zXCb41&J%frFJC9P&7Ym4XV;h&q+3@uZ<-lT%C#CP*zg)p+PL>SS75Mi+&!mu?^QZZ zQ4BK-FuqW6ERq@KGv>P3q+-8yUwtl`(&UkBBkf~d4_^)9qFp?b+}O(~^R2k8w7-BF zZk)-Jj19Ng?s{_lEkhaa=-Kj6eYpWbyXwNzLu-q!dKLPNGNIG+%`JUl!xZ=Lwq$8J z!I}me$GoiDbkIF}Lxeme*)p1#!@&x_ddq0Tva0m-#HQ=3 zC+I{hb*YoE{%496cBac*wr`LvUEsvvkNwI0NhJ9QGKNSFizP0L&OM~+MAn^gKBa|E zyu4h&K&Zr6-QU&wzuh1GWZW+R$VeziNNA`i51y}w>(LViK*7bsr$&A8l7^F;;1w+g z7tb4U2|AFZ8oiWh{DYJ1>4WPG2^IMd;0w%aHP4%qW7+->;HG>a%Dr{HvtMRzKcOCy zg5E7Ju_xh8uI4$)4egP3)CZ>RXO?B|48E%Ltn@5^n_GP@9R_=O!WOW-UvUi>P~p>i zr2(_dB@~0Dk5HYQ!Q+^GXiY1~x^{70iW2iaHjX+?i-H3;XWZ(I?*@fKL%#i3R7}^l z9qmDNt^hkd`;Y-OGMJX63lyucu-;((RDM$DLY>0`LVG3(S+4h(068d6_HU+63kHf{ zGw))z$ZNiN%f&3=VHbkc+|vrBl(Imw1d!R95sHegq{Er*^JNIex?a2{E$r%g>4IsS z`h>%d`$eG#4?Vxclv$|wimQDC2AK|0!e^qVc`!j+v}x>GOOBr%uMYK-mHikIT8 z84LnX4z;`uBz7gwYh#KxKp8Wd>M}G@8;5k`dIdwW4t*(v8{%ae_efbBGx(A6j1~-L z(^sTgXTbE=->&dw2cIFlSct^SdZ#wFaMVUpPjvdFztR=^-v$V9bD4hu~=CAVqJ_Y+2h#;nh!2_hwuTbaha zq+{<9^BMl4(@Dzz&kVRY`j z)vAZfSsiPz@9S^d7CLuP0is-BX=k3ehw5u|jH6W7PcHO+(8$2h4=Q1xxSI>^ecTQUtSGW(ywIKfTtc|s@ap1H2QA?|# zb0|+Eogp2>)v>}UnzL9;WIA#F-GXZTiY~l&;qF@i!<@7%Modelq>M)~0}S1F+7+4g z`xtg(2px<0s(oHvBUIK#Qm)tIW##bb+^(v%GcDy1tewo|Il+DIfHt$GH$E}@MxHe% z+Ovr-N>&3uvN2p`#t&xRH{yifziPwAqIX;sFU#d7w%(!ecY6ZqXD0`vJmmRL`G?flEry zgY5|Ak}6DPw)BJ1+NbhUNe<4_q3LtJfgIt~YdBj|`oCF-q{oD^ETYe3n}^6|xNNMW zH3zC^gxyCd`}S$BczKfEL>HGBvk3C3N1iyZF(KGh%xZU?FcDzBP4!zVQF(LHj#Gnz zvnFAut6Mn-Ps~03JP=!>dM}C1#H+9Rnd%!{thh+1Kh~=#UNblIVLqLNd*#MIr7mN& zy|M_&Y!#SuAP^7U`Q=(B;qfz=5-&GeCPRJZrTaGukKB)qzrsf6Iq_Q*<-SMfbEdBG z3y<~ard8K5v^pwjyq10&xd5``g)>++jR9jGf>b3>1zzL${|;4ehz9rS80&~Sh*o0} z&m^j&tqYY=tSi}cUw$F9d* z4qBxtwqNtc&c|Z>PzU4*f;tc~p=?2nnSNmyqsKS%>i+aey0*CC^|=27SZSmB{r=+R z{dXpBn%`n6mrOpUqgI_6L3t*6*~Mfo9s!u9I;j6#n(TwCYgNzS?*X?BD+SSt#*Pa0 zcZz*$Zx0TT=;S`ze@I&r?rhymOU*YQxQ9FGveGrxiy0oTkY9#f7F|-?4-yrfG4Aeo zidA70zM<9DFyKh?5wrFUY;3#Ksh%obxWEH?g?x?pf+u_3C&wV6z-!ApwGm#Lyl$nm zu-^4UyQAakIB@O{z-i-_Gu|R<;ySUQ{q3lyz_&6Be)7Qn^I_}HuexuejwdAfm_4T- z>L!Ue`*4oa!t_nPGI&t31g!aj5cCX5htu1#uPh+(?sim^`mUrc90|YIj&edtG7;fxoC6P2G z{S3(${cl$;#pdI7*X;W#0$<+*;Awf9(_%$Bx!6ZiZd={@Z-kJa{7@z%$l@(Z&}fQp z2#=#UQ|RXlPt>>SvNA78D1%E=tZ1}X_#4nj2r2EpGXcSMCR>jtDRni;*wCc&-)Tn7 z&8vfx%35fC#&}}7`G-+d$+uo?SBZG8H67uS8;dT;e9`NOZo>8`3bM!p}FoN z$eZt&dn%SfmnP$jXAf4aFSne@8~Bjr_T%}ShmhdC{Z1qnDNCyFdb)rRuwL;pJM$5N zdBauv-S%Ux(Ge|1dnH_UIz8PIU?+fHKI zhQ^Dfb}DlvJMR10=)X8+W4f_Qp^x19@x`3*ldJ#j0nXS6ye6C`#WrzDR_9KzH~EVP zDJ-zhx8|O}{f&FIA0xes?q8QiW|)xO6`rij#_0L&hkW|Ew2sL1NuQqi@J*`(Es|P; z3?@UbLD|=>{>Hj5EnpuJ)HQ>OjncIbl|DTTD6627#20)QG=}}g%oZj|^)sKOqCtMt7mS&Atk#MeCBh{5;%Ar@+8R!3x6nEz^Ln4X_(p_h7#R4 zwb_8SKo%NwOTTnP_zwUG?y7ig$^fRQsCuf!~Sy&QnO^`VGsO5&cK9N5b|habOJ*mBz$t#MSN6 zGzfkpKLQoB&^M2W#*<4k)XHzP*&&a;t@#7!{{t}J&HmIzZ(`sy!P=;@t|v0rh2S^X zBzQPqJM4w({_cp(KBfGel`F3Cja@=M^MYgG1)-F1l;W5&aA%xx2G$D&lAm7Ty>w5g zT!(l^adHgtNXV0_qYg)4AYZNz5=2*EUM&UI-kztg!(^T4PolJRF^*wR^w-lD)bI<0VeaGK8%Ra7u;#|gICX;^+<^g-fjw>fNZ{MX{ z@&qbVZHT?z`~y%DAv>vjLzEyC*TSh&(Cy(=cUH=B|7EyG-o$2iwSPoGNuBs@f?;M# zoP6CvkirjWYrpaq52VokJ-+TIA~mg<>e7R8u|XVxWv`$)B|mHT8RNI;NdkT=J*z62+~i{N#^~$67{)uu>%$>j7D!=Ziq;$ zVzgePHAW*tafFxDRxYY$3AWasr-(Xj&?Gp&0Z_3Oqe^bm!kjW|JZky_fZXl>0aTGa zVY!LZ62j+uC_D&u8i=d z`zE`9rI-c{i)6}faHK50xGz)e^!GcvMv2Rlx#!rcvx4W>FlKrnb{DlLbT348rdF(t zYNG4CLf!Aaz}{HeUL`?*vw%VR+`W^CE`dcDxmDwkGkhJ?1Bo7$0HSBhgS1j>z1MFW z9MwtRF^NvW=L^kViNV>w^yD_Pk=Hg~#P7%-T@=9N`aL{Css%3$vQ+3AqA>Vif$wBRW5;!gEFsCh~fcX6VWQeVhZOkw=un!8l)iF2S)@r`vyrmu}NXIxJzQoBA7;XN0O;~flAFID+G6)JECsYBi!Rogc>l9FRl zYNM-q=0q#!D}2z=bf|&4+*uDw1jofhSR}E!RNGM)CRQ<~wlj6e%%#eQ;OTXP#4_Yyb1Ol@i8Znv9W%xvpqr$5W3N$C0H9G`%gh{^v^CHU!(nUlM& z3l2g7y{?e+L!5(=eFdg8|Jw?5EB0e?k33Id3l{iJJ-BH3(9bIu@QGU~I#2s0fo&o* zu2E1OQ2ixW+I*lalFr)nYjTu95PSZW*dZD5H1Ml<%^7zo>s2qNDB_+sJ7p8^I@nag zC_L<~lGjQ)58Bj68w+W4MgXZp1WoG~2-{ zWf}frx33FwzTy;iH012pYVhN4Af$e0BJm#B=%7-vnVeGAT-!?4d7sTK;UCp@Tb;OB zb}Kr<>h0wPA(Pb#X}_cDeOaIr{x5o`iksiu|fl8#K;70sNS1 zy8=hB_sNC(jXkq$wnC z^S(Ogds?@HA>3prGTA~>`JAqQ__Sm*ksPrh&&F&Tsu_PYLY;y^8-JwJWHH0X5cNIz zJ z)J0ui*?CZp- z^2omO$h3>Xq}8HSU7$-uwoY0%S%lj$d(Ovjn->B7WLUd?Jj*kg;O@sQzpBEy1P%ikm1)crgK8(WFn|GZd|Ct?#w4Hw?->*V) zfbKUf8!J2sZZ)`X5c#Emm_)Fb{euZ`hPW@~`#XueAVfgY9-)X`6;Wc4#!;U#BboPmhVMc(w^k1qWiFYe()g9I4$8q z(KX_TvyYS%t0}SX+~)j9A5@)f>ppH>{|y(7b)4YklJxPi#|IM^GAE8if01 zEa2oEF44aOdAX{inEj6VWl{M%@6;IUCtkBQy?JrW?mXm}8Xw>1J71sZ+_7_RnJAVA z6J>rYcAG$-OPMw4uN{&+Ub;OHr0#M^v+U0qtEqZNd<44tUH1pTxrvya`hrZEJa?b% zzJ=SzFpt)VMHMbCx2CZ1pTNa{GEfV^PS7WKE#o>#lO+9;IGAfIU%a9U=G`{%wUFRN zUpM7G_*dMf2s^+!o@G3Ixo&TM_cekHDSy63XUUNfwX(KbCQAbaJ6MkgT`IcTC}|a8 z0qUmrE@qQ+b+lVAmlXKyuKvGvV-rfbVuX#h7k~{V{B41)^0y3*;g z#|NGG_?}cO)RYQ)~IUu4{){koZ1!X3a*;?n# z!eDV%gFdUB#^WH|g~u`KJ6LAfuK5|QhuyYaJ5c4Bhy4*mevCq8TQVcLn7QQyo? zV~40TMq7(y@18ZI%Z79C4(J{$x;1x9ITG)Ove2aw61=06E=Z8ZfM#j0>mixtMCWO# z>b$AtSzy9~$QDo|L;X16f*S^S&$7!U(6IJ=fVQyYo> zu9E+~Fi?g7v^t(3L2G9jI1X>TlzHr~jw{hfMxH}B$6`EW07cvHNfyLuh9X|Wa_Quf zGbQM!k+_=kuhepObqN@}R;e_jY|STC=$Ew5#W_IVnL6lYV|fz^`lQjxEqaY#y=MpI zxK0(B%QF-72M<6}XE-Z0!G%rmqP2-K!@XqZ20|5Iv5BLlvO1LXc(kWDgBOs!nW?HW z6P?Eml@0yJ7yCw#3d?H_&wYdQ`x%rV!4kDXCHz+wZ)=`h%W}-i2SvY^`o+2RTtVr#t#aP;8uBB4-)kXOn=b@ zq5tmz(3$PSd)SGF?(v2}uk)<8m^y6s@WTZ)R##sI*R?v0raq7gYc&^2?9BE#r7ijk$uf{10 zn~^Ptc+#1=UtyWxq(7;#CLn0rpg*FAw^Om<45gB=TCA?bU_DuEMyA6o2*C=fquUZU zcjbVp2&ht27u3~TL6=t;fZ(+`sR+t=LkCUC9(!?h&JpsM8`mGl~DvJ%4)PoL6YFZe-E|C)I(zFsxc?k{h^2xMQxf-Lb zwW1DTVSQ4LnG;1mYQ^raLh_X8Jis^iHhJDsh2(DXyg6s?%8m8NxxqFPdtS(CK6$lr zKVYKbR?=*#(6-!hKFoSi_d_G&>XrKsN6;_-AuO`YR@81uYxkEQRcs__>e(SgAUX|> zaWj4^=2gey1tWY2QmEK(*(*`0-}f?C0a8~&GfT&D8*wvRi3=vZe*n~XBMD++32iG0 zBEuI~zU$Yt7uWfhGbeuleSxkUsv{dto*SyJZT`!@?&aj4WQD3Pn2HNgC-#HFeJ=2%a3Pv*fj>EzuBDq2p%EeR(eKVOmh*hKfk;rv99dnM zI$0=jvDr$!pE<=gNU8T5pCERTDU=f`y8qD@=}UBZYz%pq%=7Rg(F8^m89pvAZ_tlK z)jNwTpmZDQq_}dE2*v2k1(0zjX=EPvR^61+a6FNF6lpj);F{S zk?SN!y#c^*^B4@=+;|SLdkHBM!fxK?6%G>bJ$atg?>|^a)*Low4dsS?yL%i^PA6T2 zUVrzAwe`BbAUrY_gXu?7>YS)4^}wute&%$7dRyvnWnOO<6C<>H{Dd>QKgmePXI?q{ zP&T=8`4J*5zW4_8-qwHUO}QWZgPiMS?p`)8s;On5Fy<2~;I--?SBa|Xiu@U4%bDzD z&SiV2ZwF5{&+?3`v7Nvy0;=2Xof{z6;l%ho>uQK2e_eRlvT>Pma@T?ln{t;I>c?dFRpB>Wr)g>_`Z0^m2QZ zO<0uluD~qP4T_wX-_P*(RF#T`S$6 zgSt{tSqiT=H_EJr2Ezvz))-HWq^H=1yz(CWcP%vXFc-XPLh{Uo|A5x>Abp%G!3*`<1 zcKJKuI~lV~L$_vS*A9yZpG74+oZP#!o9mc7ZFv2&ulnaCorfDuRu4bXucL;`7Ktr6 zE8jHv*vnP)E=S0kF6aaZ7s+|oslVAuEu#Vz7nzIs`UgO{W)(|xNEpI!C>wEjL~2@D zam&5iM;!#2JA#vKS+zUmJ>e5LL}>_&k~Vo6P8B6+g zk|E31i!JFqOn=55LXc!|irLB8;3$jP`JANd6kHl5j{+N83{UTdpU8?bmqIFHeWPg9 zTAs4YW$DB`)f&ssKm=Gri+Z@_PVcRWWW{}m!< z`2$Kb;_i&4h=SV?-n#4E=3?Qb)61u^LZ`7{gkcG#rOO;>$r{nbo;+h&M4rze4W)~P zzp~9smBVxRsEf=^(GxGx)u3QA2K~+Q^(~VjdSdAM8g_zrnV#(+qa4yO&3hC?bG~ME<+z2R$2)VE%CGA-hwL=?_x&BX zo=;1*Y8rFca)SlIY7yt@-&$u64j^yecz6|eBfi&<+UH_8uKv{mW0(N^3;GLDYu;vxC%6Rs_;ufw-c}Z zMe@(^{Z)Ar^w@SRY(GNMUp%0nHjp1bXF92?K1!Nk1hwO%`Y~Wqq+!l{Gph>egskdZ z{7m=xrQL?}y@BB8EO2#H_nT=|$ihtLVcDw3)Xzb?Uk-JY!}Xwt7)6?6{-qyUJB5P@ zc3sX~eePrId3_a zN5?>~5t4^j{7KKxVqG~zhv&NhZ{2BvL@=(b!sb(k3r?EET)gw1M!I4d0UHqoi>T~g z2e*EfX5z^#?mH|ir^G1yyiXIB4wiPOW?H+|x;b65GUQ2?I;8@#K`O$SS!;qm5$F_d z>~W}LKbnP!WIxpPZYozqZT9;$y-uM&-Dn4=3_`D6Smj;(pc~ipecSBP5$vikj|C&H zqFGpw8`*gmB5E==`DKEZw&ick4jHm{QC(If2qL8`X-uq&_>Trt(2qKE!trxe)jSX9 zN7W(61EquoYFz^x4V+Jtm}L}V5(?Eq6mbi6fezH61-VviF$G4b#J#h-{lvY{1e3mI zau}p>r!6Utp0;1^)R0o~Vf{#72A%4cehBv7G_WbsIL4lizF#xfguT$&D(mT%MD>6{ z^TXH|CVidJ+5z2&Q`l1U2lm3&p)!P+@TMAkRB3Il#e&Zrq{=b8J1iR`+AOtX(jYb&%Hxp| z^c-I4IG4Ohg%D$%BnvYc%7sxEt)iTPe3z^Zj6)3p`7wgupaJ3vwr4V1XYf)&QoK)V z3zc5J9imH83d#wQjFD?Qe&4@&%CxE9CHarjW5`cMhfvFvRb}ag@7LBYasL&tIkU*AAD5r0ho=AwzS!C%i#bQfl5wQG@6V0*%kk{DVhA8^uYO_*y|L=e$j_)!t$z(zE}d3 zh$1D~U{Ethj)+~^OlO_}D1%d@QcS3&n4jr&= z)~mXKKc33tfnS&>`lhPt-aT2N*W!Z`$4N7X5kq0QKWD>|>iaj5gQN>k-m;mTQ;wKd zD9USN){;v6s0_Xr+oxY0d~3~y@P1Q5SkGcZL)NiFxm|N@DH2kz>iit>`eO9~hI*4V zOMdjGOgz@glqCs_$vol+qzO+^#Az^woC?c#Vr#r`sYLM^qBjS0^OO8x% zt5eB^XwhUj=9im*fiLAO{tDtTox+jt>^*Sw9Ec>s#!dr!)thkUQ}LqpChZf>MZ-pK zs5E!{pDD86IQ;V8x+H)UpTat4y|pS0ZfN?}TY1JW->wZ;X>L47kX;oDj%nzKJSV@{ zQRIWV73byHgb&Qi^@LPz)^IG;2T!2iMSZzS@81*&?e~gkVwG3%FwO&Z>w4XGK zlb#%n{iaP@A9%9vmKO1TwbX3k%fs3Of7q9B%3e4PJ0u0cuPZ)K_>ymmFkn#3G8-{6 zXMIp}2~x%MZ(7~x($tvbQPVd{)(`#f?dr_x4#{Wg3TLyq(jz;Fz?#V5U@%g(hscU94$kJL=$0BV4Gn{VTF%skng;8{GFk)nBl`*V#fs16=&hr1ea`xC)JUb#ib`#p4;mmpfUVv+C(D4Sb+( zMAdQ~Eb;D6{dSv@Z-wU$Bv)7nX+qGGxeR~d7!jU>KGhFOC@Nzqn{{7GK8$~z1&aT( zlg_=CP7DYMq2GDzvL9Ca5bm=G@N*pZ*qvC87E2y{J26q>J@A)o zwDp=+q$FWWuNhsEcC4$P`=vYS{v!Hdhxe)X(~_L!K?$R72H8N&o>b059u~t*-DH>P zphVwf7OfJE0)>rM3~H@1%FZZY1(#XkP;IzFQnX0;s)Blx{oB=nT^oIxenL5fG?X=d zZ6=JZm+)gc)0jNY2D7$RmTF<{Ps(}RN`nMx5ED%kXP7Pa74>m;WnD@K zl4y9%oVqZlG2g1Y5+2!aR^UHS!q9;YT9_xAHYxF?J&>QPqmZ2n_(?ymPrl3WH)+b zQcK->m%=U$;DknjOL10#LNbehMQR>L-t6^!zD2&U?nCY~#x zRjE~3?kvrm(pr+fcrJp-V;YiGca+npk}yxk)XGsx(LQ%8TQr?6o|baf_q$l%~NZzm<|pTH&?co0T}=~#Kso34RH%Wl@yM{Ed(Z1V$M z11xZS!#=EYp=epr!>~l$s^%&wq(O$t_2IvFN|#us`Hy73d#h&C;Gu6CHDyVC$KCsyMnT`aIT; ziu@OAHhM4Lj(XN4Yc?w5J!7vZ7US2Gp_>PO7LR(?XMZOAzvke-OuoC~4}d~nM?2Z_ z;g-U+1s16=#fv?%)^RHPRQ?4}1l@shWlZ-S6v}g_XL{JoKl}cHn;x`;m zQ|y&}@bP(AzznQ+n_-K;(@A$MS-?>VF62?txCgS%^TIA%c{8{v&-duPak?*tub0Cxl%oQfB<`7@-4WPSBy;5G=K^w-QEW%=R>) zg^!d+^eD&wL)BXV#MLtk!<6C_*W&J8tayRNeQ|d$Qrz9$ireCgyE_z@#i2lPDDD*P zzt8);_q+E`ve{%ea!xXtoS8E->G@}`kvQ_hC^#fI`ZrZbj8S+?x8=vc%)pFjg*f}< zKiY*5_i*;|hvuRrbiqF4+M51)3&+XF35 zA5m97SRv}-O_w0us)r%(JMD|7;cGA!q*&kce#ywfWzf}?ZgN&<;;RTf{+0Sb$(_{6 zN+5x6c-^V=ohoy-7N98ET*0G?3}jWFO%a#SpgEJs_DLtFX1Cbi$(5{ZgG6**vAll& z-wn-a`PVl6Id7Y|dzPFVnB{5r|QOS`E%lxgcsLv?q=Sf1u%CnD^MF@>VI+dMp_Y z2DPm6in5vuwz^Z&daC81aU4BdixT9r!Y@C{2DDc%^N}MWWT~`uW6(f9bf~aepETB< zEE<06iDbIhM67kto`C#2w$~$i@0go!CoJY#{J72xFq&QEmnC1_2HPPpe{8SU=eUwryunTSJ0sG7-*s%8~!Qu}s^bP&@ zp~{7&m>RkKXu0_OuxbK*4Q~+m_uL7Wf`$!xOod<*)RMwC^)jg+6 zdPw{l`>_EG7J16Ih3)_@Ol=}%1N(C1@O)Oo;c3(2LuwE~m0kFHbuEmLzc9-1ZPFtV zV?wmjzdp}2YxNk;m43_oqZ36Nmn#oj_fSF6ZpwWev88WOXtff$W%^n|o` zZqxpaij)l{-gIx1KRS&Me_F~kWG_okI~h3FU&_a+0&|It7-6+P>w zW3$`DvV?>;!4jj@mrzc%8pmZa^Z8WRH-da3=x^Nd5QFbNFhSTZdAvS zDAm|(@3@BZNOhW8ZyyJG_)MdDPkGjk(OMc``!>pXYEYy`qMjC2tl3aug6*+Zder^n zs(c@trV2!G9WXC?mdporuTKD~B$;A0Ml@>KVp%k5xz1rI)-4?^8z*MSTKRs<-;k+L z^oY!Eo}AiLR1SDGtf`f;zgtB|W$_!;t8ci>9Gy+RXS(HHCG1fuOH*)fysFjr{v&Bb0Ejs@{P z75*Dy#lNzWv~cVvecKW6YNaf#Bw!jrqf@t+RoDb57AaPYY|5-am-))I!~hD7$m5$- zRmSz^VMCV1j{$%n*1b#_Z8U70?4y+uKk?;!$jguUMo3gAJLj~OFsvj^{xnH@-|QWK zVdxCX5@D4&e<4@oyp0@o;IEW%DrNw0&10)-+Qdjg;Z7i0ROOfnYd=dZ4mbM0GyXpb zY;~H@>n2^+e=d1B%CgkfveZu&%QI(meAOo#_tUEIUJ^!c)!|h= zn-F|oJ((1XL=IJ^1hFgNB}FQw;^YN(OYfUpMjG)qE}__aH`+4w9*p_h+uJ1ecTOzQ zNimp*s2>{CaASz+p+#SmOqq(*sOCwvbE<68+Mn_VQY_yUN$mOW*WNV;ZOBE^=TUr>UsU`9`f=8*waOIMdl z%TUo*bj$kl(B6d{9Yi1Oz0?zM;tTwr7_37i^Uvh_X_=Q?tfb0R(=pFWxCYx%c&p$R za{h&+rSMj;AUC5M@pBqZI&e-vn9+8b%MkGjpL(pd(5&ncTUpbrZ{;Z@EpBb-B`!Yw zpsq;rXhkC3yyz>J@;A09f1T_?xkuWWz&3p9(M43umpBbd6KryReWF&7eZvGx!;47z zLF3{f7Loeruk{s4?zV-yvH&WhMCg!=a9SLeE+$+LBPH&rEV9Ut{r0yLc5uqY_*Oxz zz2Qy5TKbtiM3r^+3T>QrD*($>C}E|3{w3n^UKUsOR7m+h#SMMP2^06#Bc^$1KGWH| zdT6HyL5J!lEb^P?!}_lI6&pdy+{==8*EX&_M3tzuZo6WYP4XyxKjVxp%)AR@hebMv zMIyPi=P`Sg_a2IhuB?BvcbgrPDqgk;6WL)&NF1Wm5-EYoDv;8Hj-XR`4=o*D4-lFy zh%ZZlye#3a{2X96(_>L9u~_5f9VUodhRv&eKMMs7N>h@o#HlGM(5jhbOVlH-#93Ml zI1>+RhbH@$vQTPiSD`pAB2)GW=ke^v=kBW$oa@4<=@wpU z+I|`uc}v^x$@?*PNz8**f(!CsSqJwRZ;Ybe-KC0H(iNj3lIc9MpufiyooOF?y~*dfQ`L^Qq*Nv z`L3J=G7EQ2c=A?}EPzOkJIm<>sW%BClR#5auV;w4q-NeegkD&|8a1ZI@-HIz(CFD@=I?4Zj2F2KB8FExtmZSIFAX5#Tw!V>{;s`7I7yQD3j-IYy8 z_E_)p+BIua;S{~RXu``})QWZyXINKz<)H@XP3f`{6XQq9qJg;7KT|<$FITObz2+Vn z?w*g#4#`IFM;fa5>dP9uoj?1HM|NuG*Ydun?%NG*tyhLD?6x4U(z64;_AukB8o}ez zgqO<{nI;y6XR^lUau!dQVmDb^RZZkbb*I$+w_@uaAPQuGtI5_Po^tOJ@q?W?WTl-H zKSpW*q>uH7p;(h9^2anPJCZXKU5UE)(5shfu+=;+ORTlEQj9ovp~QX)cd89Tau57y zxR8Co>?ro0e%y8gi&9KmqMm6q8QCs?Jvp(F%_&+TM-{r6Ud_Kvybb+@X;?XrHeE$c z`c-JupgC-TEALCij6H}MQ+Ul(f0I!~F9TiN$otzDsdo5#b#2gYKZNd!%!qGUd`~*k z$4L6dO26h;R(NVS6y+Q-8rMiBJ!7|vW*;XPLuMEdPa&Vf#wlt@`W=d@XE#T_EPmIq zC{(Q=w-td*Y%RCatkuYTQe&y-k+3Lik_Ge7M2yBT+YP)#xkOI}V9_YauR`T0)!3+0 zRc^aapXCz9D#&drD4Q(`xpnE5hW`P(e|CXO>p2_lctK=)ZcS|NQ#D3xc}9B%@cK#; zZM|$lGR<)d{;vAyn`BZ+mQG2uC_O6HezrxN4#TMf?ddExXV*U$=-9U}^?izEb{PM2 zCrK;y7#lq9$UA9!8EXq7IbMmR3Y5g3K2ZN^Q+`s(O=LA~lj%n(Y7MsI>K=^;oC=*B!O1 z3a+fLhe5iNJIRWf`S|GZrC8SI#sFE`XT%U<(gaQF(dBP?o0MZBd&NMiTw$1BzMyN_j~ed2PqCWUDEEjhhDwZ4rnWPk`I{$uE~#nYWTa7HYHJGu(F1qGvij zI82OoCMg1m+hiqQ*~?fnwLx`e+J$yUB=rXOigU&C59(((9Wf$ozSQ2=PN1pV5Mn94 zB9nCq-#A>t=@K%$g>tp|F39S#JrnHn(oEfJvE!nA==TBNV_5OOrb+y&w=hxJ6y7yc zr6z z`Z4i&WiH7gz1`xz=C$MGlWXsS(Jo-WJQD3)i+^t-d(5W0Ap+ zVc@GScvn?v2o5se@BCh^_RUIfkx-y6fhut{)^abhRJrDot0p}g)}|bPs$f1#hiYu% z(=%R=RF(}A5c*I$)QhjookrJUnRY@q;M1D%A9>@cm!A^`1kMM!$V&m zLd~*LzQ^X|`hrQN>YRi_@yR5pQ2ZM;hnSjaa(zD>cQ6Qot8yu^y#sG-M&lBaSoB{V zQv^|{j;Zmco2PA0{9uLn^wQ)i|F*zim`(!zKIHDSN{P=qUG8@pZ8;L7 zqr;oluS%tc+wb|lGOf8}8 zm<3C1iQ=%f>WboK@6&18q$FcoZ}K%gG&z+-n!vCW6FzjZs@M&NvBp zt80DuZr_hok0YDC0B-~`E0qp6IN?#t|~l<#jPE; zcRc*#PV=-^0au1(mTuO7KM8cje-zb7cR{GpoG)1Eyrvmx_(>_!k66JriXYC3uE%e* ze~>w;v59zU*uVo4&+O`w<}D8@i=gp9gf2ky!yuTss6E?T-DQItLs~C7*d1A|ucYn= z1nN2+4>oao+x`@_n74+MM_m#S&j`@8G6=ppi#`{rAlFUmPX{{rC9|H?P$#?O(&#!( zQ)%-8r$OsQKbD(tigbrEtrchcUTk}J@u<_6Bnp-wb5sf)*in43Y9#CN__{i6`h=l+ zKnDwsBOw7$-pKo*A-esXCpm_ds|EC1HQLSR^GE5UhDj%-Qkz90>8wdgQXpHq0M% zglAzV73S`d2oPewm9|$W5)*=uI+U}PfypBW7_yHGO?M&IXXTckn{$z@fm`xvBC^; z<_(rR2u0qhOGVo|{)Levt=>6vq?$Vvj$JVduAG5$(2PC%NO#0z`EimVItkB-s0a2)AsB$%NVQ%K{6hVS1YG zs_PfGp(Q=8N0Z{_2=0!Rt0LagN37^G*1bIWcapJFedA8*NZ`f|oCrA4ajbre zP3ieFNyIK#OIo!#y}r1bT)09|cqaO6Wl5`E^`hHQyq>=KC<MX~_p9>Or;O~8x(44m9x-GXvEBqMI-%8-#zsf(l zh`tUxw_xczR`sN(5uZ2wGsS=+hqN|%FP15xl`f@JAUMZ1j3N-Uru)X+VC**X@gRDU zoTJ1M7z`^w*AKxcE+drEM?mG*8JNa*Y7BeV2kJxPQTf81#j=Ym;p=D|5{`JXVYBuQ zorw@&AAE%)e}`M{IBAcvxs?GmQ2iKU}P1{IBQ?r@=w;|C6uxuW2A^I=#k zZ*s^G%sP}p7`(K=x!S{f1ilzCB{DmvM5iy+uH$#wX?o%ZEp>7sWI-qkQJM}W_E*U9 zuEbq%l-wav%9(7l!I?f7u9P!Y+pKB3`~iO;9p-5M9TGcwt`Mt@Zf{D!E*3o3^zFuT zKmL8HQ-sWyNndHA^6q}mv>#>~t|rX?U^UDS8w47g!|6NhbU&P<36ZvHzehY$9d=;A zWNfWuD!XKJo@QBjTzz#DY}5Dd=5wcHGzs z{%`W6J{bL>q1$zr+{hCd+-2>D=jg*?7$WQIqU8WpIn?F!lxhfZM#}&cSc)04Ch;>5 zFUMozNwh%>(IU4h)e6u0y{SAQToXG@zdTN}?@_781oI{&N1PegXO&mfAqe1pq{MZi zn3|JJB(0iwRmryiRdSHSnI1UMU{P%TB!LwF59c0!EA`IGBBrS)vynP&LruesmrSA; zbFELDrq#QC8T15-&?auBuNufl32Z3iGZ(lw1qEV$!DC%1?Wau&2MOGGrGs_S@Lfkj zm>f@!ss@=gY}x}Q6d5yT%#%y|H&CHiBMoi?SJGe!%|YQ`{jPm#tkd4{exo-nv9s=U7rMcz2TN@z;y z8xQ9ks+pQ%b;dCW0vwtR>poSP_)3cR&14}BkhGO|pdGWsB|5-(UNPRFJ9O3`W4ZI$ zuLpGj?L>_mMVUN=zjvi&-Y7jLYG$L)03>B`HFiM4xa*v8z_NrjvnU<>6Y6b95>Ps_`7HE@27mUF<3PA!CJ$RQ@x;=O?nyf~$1YJEP`E$85 z7NExbuG}ejn=xs~c9680Er(9{AQn@Q0=h~r>py$GN?aaH1#cPx0QcACE^_DGlJSa) zo;&{{;${vf%B+$bxgJh%cQpEhj3lYxz*Pn&uP|0Z7L1JgCd>|AT#=G4#ijF?A=B#j zbsbf2eZPJy9X3F8vMizI0VV(;XgtGEolNTegM!PSogz{72X)eC7>-$Oh*`)#^D#&> zJo2`2k$)Wky{-Vup@srulKh)CL*jI!_aWE=x#orvN?BoV`G368Omtp@LXx4An3&0# zFZpI?q<$CTw1}TG6d%Jjsz^KN6PyH2U=%08d3-I{Z0z#aXt!`%cla?W9@1}ss=$Nd zhyfrrVxkb7q;6y0%P@Ot;S#y_+>+}Vs5Rm?n07)c&v_Yy2k!DKdllmZ?#zu?zlFBP1D ztIyT<{ETM(7knAesan(tiTnl~*BBDL)_KeF4Uqj~(Q5aA?|jrJ1OM4`3#`5HncvzY zS)bmps;Q$vB=@?+v$=23`3f~~w^&K;AuAEHzY0UhJsHN*{1o^)&uV}4rBZzd<+PeB zr_3z7QZ7cfH99H6$+sU04>AgmZS*c*bXnpDNqb_@;)@I5!lZjKXfB#Q!a0)S*Acfu z(7ns#0}pCO2Vm)F%~iIbpsowR+UneO zK17U)9}m5)Mt8d?C6L=wvVc5kb7SThdHr6ulEu8E0{UH^Td$8#OaktG=P5(_J2SJbxVN!6>(+Zr}7nhQYA6MzSOsw{^ejVT45@uL)rLad|*{vl+ zLM4m%sZfB$M&j56^!6RAFIQK{NHt0{wXTu+wWMd-<3&2y1{H|^lCEr#H)g*=r zJ38M>)y^qI5x}YD0TE+IofaC!c$Ph$Sf_>(G0jmFZ$|ahp5dZ-AOTm9^Iyj~0Eh@;} z0QAR>BzQ5ae6q!7Z%uDLtQzq+jL?y$3$Z>a>0Icm!pU{}flCzYtjMt~>ZP**V>mKn z+ySo}ejFg$jCQoK)i|Hbn?B?ZKE|LSr;Pj(^mA%H`coDIe_>#%HC^;v?1ZH1ia6+N z5k(9bQbwRcJz-IVKwI9t-Fhp8Wge{Vbm4#;>S67iX618%2GtN8g`zre1I2~mKad6> z&i-MGITq~6XSJ_Q2lyp5(6C>pye=Ll>NQX~o)7T#Gi*RyxgjH^5(gd}BMh8D#ux93SnaP=s+*s?SM6XD3cL^*!o#x%&ION!Uoq z`u%)Ht(@!K1C@bN%oWed>EW@BBQws0ismLZ#h~wW z5;jwQ6q8tj^FC@p&f10~kS7iki5{lvXDu$qG~ubiGuAw&n<$ZJ8v7r>WxU`@` ziljb`;<-o^T(of-HsVLY)2062R73*-S#h)TPaEC6W_m6UdcQ-%Sq1K39@-=IqaZuXJ-10R4EAt;hCjRyMU>bz)0s`=jt$!Qpwl%y0!J4{=-rVqKF zbE^7RMJh&CQ{!_@=_upy6Vik^4k=$^ns^s2X?jO>&QmQiHk=nFuM6s+imam1Q1vFEGdR)xa<9T}fdZ}Is5M8q zVcnV-YLM-6E8|A%^PLFzXVyB^ZQ&X+mxV(UPG>@g@94Dy5_zX?6d-&n} zEToF&MeezNm9hDc|Ly7FA!DT9CgVda%LEscl`_E0+fGC6)OPw&Z+XmI_Vx5#_SyB#;FvgEsZ(5quj00g&g!oN~E7>-OpCG zWY^qZY&xTn*=$4(?l3=Tq)$Cp`dhc5&UzM7A=9{G$8=?R*M6V}%2EBv*FbaN9@dKX ziBBbyBjP5+i(W*XWvD=EnTy{F9s0olCD|^@aVTPu)DTd@rg+L3xQ#{H*T1WrTk|#G zU86DwFo>gb)vF2=;-;cA_W6S^-nk(!F_4l(JUI_jm(z)xu`c9{fz6e`r7$Jn+LQP_{f@0iOo!|ji>WWO+oRZsZC+k2*n^=}zQeccppI71Ks5(!k*qkG2Y_mNO zvskFhcA{MM1dj_rqGI4v# zxabs*1#_H)T_QEzg% z3S$!i7ca0V5tcm=ce~kavUeN&ZSU~&e)^y63h>g zrxe!_ow(a%A*wrhw)sFrb;1c=EF6^z^ZrSOPScAt)%u1A-zl$+vM7jIgaiGgP$sY@;8Ae~T4jUNP0Rff&n$24`c)PjoeYX5 zv*k*k%DkERg6s7b8QLS@hzyX|VL~ZhgvU*DM~@<-()f_)VyHW+5{^5+gd~A@q{Gg> z>qie6=d;3_I|7or@uhAR?Mzx@mEm_jxiyM<35g-32e=;0S$TljyVlVU;bEHZ@ZJ$d zW|1?TBSy}F*&Y4Uw9qry{|`&?3Ini17BeJF5b4dd_DrF38_Zve@toLci3p|~@wCQ* ztz_a4(0PN*x^T@eg$|AnsT&v7UV{*Emnal?mbAEJbFcvDA(df zDDt<9GM|KS-tUU~*=i@{!@DVyKS5yp zpzsd5p5L3hl8&l`vjfut|A*Kw>e;O17>q^$;8U97m5iLkvSYf0uBK^(p+X|Im$@7y(@I;lVsJh~uu`ICFlQ}Kk8rDFWXD~^MhpP@1=HCzl5ZXo+Y%TFL zJQ)xM<}77Bvy}7z_+IFSw!ybs8LpwoZd6T5;Hm+BWm5NGC-DpT-e_EL_sAc|=zrdD z=ho5RaRF023O?92R-FiZ@0#JsR*)+cC*}T$bgiyqoEMq2Y8bk-TcKmHNQz_UF=a?) zvBDC>kr3&mHwhDd zHG#s8(}~>VCJnOFwiv-(BGEOj>>yF!08vh%AfUSY0mF_5@D8#_^mW%^R>k+2ltF-O@wV3qikk0X4Fe!NIv|jzwQT@Fd>1ilQ07~=>Z7l%mB>_iC<%XZMV%OO5x(VV1 z*a=-#*I+}tV1>oWIajSltATH`z>72jp((qRD`LVWLN^^2H zydD($C=NSuC=t9kH5UY4_Wc%jC?KzLi>2cnI=pR`(su^B^C;!73#ml2-CAIZOG(B! zO5TjGoWn%ylA?RmZv|l&{eRvZV!VZ49-dMNl6CH5M z!nDB+!j>x2$rT7u6UH@!?ljX4L=d)*4Q^$Ex|EIFw(BsvQ0jw(JKl%5M{ z7{qDhuBS62@BfI7r!#m^C2zn9brQSK8p8tF&#*DsELsTTvl4~QGE!p}=XzIsl)(hP zOu~K0dZa+8BsV8S*OJ*-B+5$VJKjyTE?oNREQIwWaQV%TN@U?z8WHzs^ihq#WcICD zlLDLH{i+RNWq(-Eic;k#Zb?H^9x^StqN)dvifDpp`vq~w)7a0NCZt$eE$^NS1(|=S z+jlvIeyBIG^h$MT4$_`$?I4!Icxb)@U(bY6 z>~&w~oT#+s+NTp}ud0wW;8;i@027`i^%Rm>yUf*&$uSRH1CM6j)V(}(QT?C1v67%W zPmJK}akkCQgWB*&J4XSq=Kta1{3pq$xS@ih16&hpD7UBh8E<7xfgR$w*%>6(cM|>C z77Ob*j`|xfxy7fzpBlkf;C{3WYN|?jz!BzNu2tF;r-8eU?@^ICC()5c8EOgFId|x} zKp~<3@8U~Ps{hjl_ad(ogmZeRoro0^Acq)@$>FTXH&uD|0UtCX*ud+C1@@v-UN&5G z6nFqtA~3yf?D4^i6zJ+K#1RDUZ+(WbHx%nvHs0?x-IpgQKP5%&^MHTpOus%?eal%4 zVA)sRUhhq3el$DndJlMMzc-r5t9*1h?M;8hCH~;`k6ksuOK-cHUDKb6~gUPJqz`?da% z|Ai^gig?Rg-SrEg5fylo@pof?gKt`TLw%%tgg8F=)en=nJB%joD z>-6)SqgU2#13VQW9^)hFkv7txNL@ zBqrl~FXsnI0i~;vuOQ4L@pybMWp1`#F2yNAur8UOaCPFZI(S0YSF%h3HO-nn5zpbg zeT_qVUNp#X>c#{w$1R1f*c6l*ncuigk$FG7S4bICacJ+Kiwxvgp5m!npBG|&JAd0h zs&)Pg!}r!tpdhR8T*pqhP^5R!CAP5@S0r*8=Cxu>i_TY*L3CWD5cfN`Bp)db2XT|J z%>BGu)#knSts?X-;lm#)_bKm(gsce1grT4g#xM@a@Ibkszc9ym-AP_e5k{F|9bb_< zyL}QK^;*05Opfw?%5GTKM9i2u3J~c!D>yfO{z7f^T;40cXZB1_Hh1IyQN!(QRYbZC z$?rr$&WvfA)Bcye8R{PoqoOIBgn(e@tkp<29?hTxmnpU_&D%|z5aAOOZ#0NA;E@1? z_(yN4i6t}9?1ervJt}nD`wv3=x$ZhP(b&ibU{AWI5X>|`b8F?A!rMp5lq>ROv-4eC zCB#dMjA6{(+K-_xuhnOxTb;ru8@2b93abUO&&F^vv=WkE%hQ70U<*jsU~>2T%Lz$e zaEF0I@WExSgxCrmF)?4L&rTmZm-2ESUVf?ns%W~sXgwf3{Mxi$X$0F=8Ef55qcw&) zfMVYgZZ}Yu^(Ttl+G=VOTB`Tpsq|H`tjw>M<3iB>`;~6=WN=_3E82~YD>WF+;r;1@ zW2x^1d@#gR)3lnejTKLPr0p+Ewk4DP7HnbAP{BGq>U3=b-`3}v&gc<4O;ko5lu@m4 z?^?J!)B$0wi1Yl;LBnT%lT8oj^~C2dB)}}wc!kH7F^-xjI#(T5;Uqrt?gLzR&AibT zQp=;_a(2^6fpP?O%v?IAR(*ppu-v65r+PrE<=DKuU!!3v3^w;$wu@ z#>h8`Gq_8n>{x8@l3FD~ZHZf*>kB(WAlX-LHm=-3Gn@MIsn9%*+Lk_a5!={z=E%RK zICb#F3?jfBeMX<5=kIY1o7QU=Y9JH^X=Uup4?BJo`C`{3Ko>*b!QSDK9&w)Ci76Pw zcYtzop`56d&AI-qVMHS)g&E{Q!wWneN#5u_LCwWe?&x7hRPd&Qg;Rz*B>27@d_@Y8 zwmtS@$J)R#B-@=aR)&SllDHXCchq8SXhoibNp?Kk7&23stSr=#&K6*putI|qXsc``vf(e#CwhlXIUepm zdLj{`j`A)8gpX$^1ax_Zd+!Lo%*(c9S!b^4tCktK?++&?;cxZ^ z`6gm@)z#uYp{*EH;E@p6xL(vu|K2pn9c&8);c662m z(AzDNzs1jk-=yYm=vK+M<8sgBTP}1tyvr@RW4*@hrn=J@0m?fpX#tUq4_^kz&}d6w zwM|y+hm|eqS5Y}2`M8*zOuMHxdpReqPMCN(=_XROzmaP#DJx!jerOblcj+oOoV|DE z%39iC%AERa92kp_95u=6+EguRjFZRnsRc80b3;q)^LJ@!8sDYk$Klmi%#G3}DXH^R zNvZo(afJIOsY@zJ_;&{7BsfG6GJTZumsCbK%62e@pMq%tmweh!sV_!@8}{ThJ5OztFqv8kEjb#w2M0uS(X)*G z24_@RVR?=!z*DQ_nbYjGkDYsgHXK4}OR}9uxty%WQLStyFFa{kKS5VtdzohJ{cwD+ z56MRWUIWUR-3%lMaJ3(EKGFS!DPz3>54kD2Rc5e$E_8>j9hC14f zf1NL(Jho7lP=g8EezUDd-%`gXO&}wO=JMh=_Z1Z$}uZ7k-?q3 znBjXv_J%8EfIJZ5IRd)!OON$tC%iS}JnDk}Fm3oLJ@!22$G5AzE~{F+lVR^G!!Bud ztcfA->ATz$!6lEX8J)aFVbz)AMp5vT&7$dB;WFTa`0M@- zMGAqZf8t*l57zQLhO~Z-?s1QH&YJk^jEEeKw3I5T8RTTxBEi^5_$Ad3%u61IjaQ#8 zxw6t@Up~C|{|!h=F>8WlT5NuXLt5c?+Q2!SLEwVVJn<(Arp`#GQRF@D*vdc` zUnnD-9++et2Gjs*nE}bmesX7@>JIB^^iH=xjyRn;gE@?gTY$6=)f_K#jEEm?p@LrA{%wCE9eN~3#XF_MCNb^L86hxl0cagcb@LqGWL!%IH5G}} zRrC$S<8G>A%6B?#DkKEH7s7Xz*9j;m5Du9Vf^Q)!h_KgYT)Y35Ywb& z8TYACD_)?}mjdS9muUV!>x+Bwn^^Eyl}x@A2&sFI19n^yl+5n~*C}Ub!UYC@^W#?y zt6hsoc91U2I^@|geJ`Jt>q@;c{Yh)wZetrB>>nj6nGaHiP(WnolBXzPOS}>$Clv%6 zBaIx^B_}8gy$@v*&m2hMH}^5$<>R|v^=hMs1UmHapr=-uwCpxr#om){f2VugQ^T~~ zf#I*&padeo%q;(}@1F-`m>Cp4^A;psCIgmQ_nz9etggT1SSIfOpUP7 zb>(Mq@v6zxcb(>B4i37d{nACO3yz{dRq>!>BZk=FZfXN`t8cd1w_cdcTC?yi_ZJ5c zKm2)d+%{jW_7Q94hl>h)(7nA+{#yEc&< zlORVT+SDyVSheVj4xFW9!_ms6}uNkFvpWr^;0z3_kHDheSJV=BUh8ir{`h+oB z{$^}zLY6LHBsP`=%&#lDe%tX!@^yB9!m(#4GjROz$wx7RNDED8n^oqKmixP^Boji| zFWpH->0(Z0I1c*2h)OP`-#K-{7N2k}T$X@#)b9AyRk+rU(=h7EC`j>D zgx4qFYYdZ<4Kv*n>k{;iQg3dRZXnoSf9KAW3eIkecUejD$kAb#qz-Pwp`!`3o3-05 zvsrSQxo8oBRvh$P`^tClX}2JFy}jbw7)U3Ptq}P6i?-NApGVyEZTj^Y7R3>ByKbqpQcN ztRTCjQ(9tC`JvU)@eH@Zb)k{j2leglrRqo%3H6)D@pMOa&p8HrqO%xn!zc}4gQhnH z_OZ?>fBHM|Y}-~w3!5d%YO;oya-|2(A%3x2tfNp2ShS*+gTc+RM$6a~yNMD>|2yzkTGuH;89;g>DQJY%uIV1g0wbWqbzux~u2B1$VPoBNvHaSCNaJ62L@f`GD8%)ak zSK-tAw6cqz*4gTJ)KSg84ip7ZT!(RIP+irs zS=f7oXNcz#JF_rZ1J@khffB5l(|j%pQDEGs9?}P?=`N)3dH6#F5=EPC<06p;CJ9(l zIT`wDX@0{w^~W^!e*_PKiiG(ivZ#6b7eel2jc}($dR#DdZ zErwhq2Dz&88WNNREgJ#rhM54!?lfQPg0yB?S!|u{V0lrQ?1B+g1iZ|*>DL_7D{a33 z?5nI(s{f^sq8N$*^Z-HWCjJD}%4EdVT8yd=_#&LPp|tQ=KP%~u?s413yt^;BD9zxL zB}e#`j7)GowcK=)HOsJU?=5&7wmZQn@ zh#ZpqBJ0n9UE$?^L0|F^tkzvG0BA^kRd++bksN|=O4x7bTGXmJyL(Q?{VmHY< zxh91%F;;O~>Lm%r2ek4jncdx@S!le#;L$J~5r{+fQqt+z@iVqLzaMLF$i!#j( z>hPL`De$dI<*BnU!^fr}LZ62u5-DsNRDN`;gkCR1T5%;$;!hl>GDPExH1v6eF_Q2z zY9*XonvHUbd^Hgca`e2e+FVKTZvGh!oc>n{yteNB_RbAY8R+e@~*v@%4g)P3#j( z8$j2GmevBuHrftfeJkMt^eudsMeu|qju}c3Whq6>Vzbx%B%Z!wP{TylyADT)WO~dD z`ya5D5KR!ry@2Ald zRjfRm7utR%Tg)xzZf;wr?|K@Q4r2j;sO`BB5e6@fPoT8B#~ieL*Ra`}et zfhAX<=IAoyKY|xdw$G^objE`<+{l4x0p%wa^$$PtXxHS2yrFP^kHVXnrcHUA_-P*_ zE^rPe&8cx|lW9}oJw!4qQ5RZ6=PS8{$e&A3MAAb=nxV+x!II>(6}M8~o_8)IcI^CXe|Wl4;*)ha_`va%wJK?KVf8Zas-0ilbaxvD(q+O+`Xv$${y6 zdv%`swTx9ks9JXh4yt!nMx}5k4|AK=Q}d+a0rUt1(KxOuVfewuuxj&Z zApFo(Kb+z8m=28jAAt0U06saqNNE&Ld|pEjaI za$_I8{r>>Y&{P~)@Z&-{szv!jx##t>aXpiIUs5ZUG3~3$u{V07Lw?w5IPy<(B`$wD zWEYS2aE@y#rmJLhxY(~CN9LkW0=T)pI%8w>iXZ$IxzU03ct}@qWUl$_5>|+=IWSb? z%BH>*bGOSb1b%vW$cU?>vMruQaDqQxOs9s-mqkQ{?|(|E4HBEvBE+YC#VsM^-Jdrz zGp9a54_>pD8w3eOXIcZyO6ijPD(G{-1+SKK{@zZ(a7{=XDcowccT0JJ;k(2|=G9dQ z&o^HOZW)ea(dWU>f@erXD#-XH$zfUivdxoznHZeOX$ow<8!_=FOn;sWir8WI(>K>~ z1<-%%d6NPE^38hgXM1bcK{wdhRxPCi9QF(y(pBkx-wpO^ ztlygh@9i+@(c(-mERWO_DIrHbRq&5IHzpJCIT|99g`z%J(cV{a(_}9&e=x5x9i4*M zEOl!up&0w6mR^gNrE6^VU=%UQ!FpQIHuj7)n1E2s+B6jv%quK=;tH#bwEmFWlR%U< zm&3ymcPj($H1tL1?8ANk0*)OLc8!aYgZ24gw?X_N{mK#(Zl!$Ts*dxLcauFUdvbnzyxjRx0%8C)bBixCuwyS{GYH{NiBcdANnCzm+EgDv$aW9vDe^ zFu~6-BJ9w5Fx!cHe?q3hkrqqv-GvY1cwMm(*LR zVA#_<#WK}9!BeiL;U30<>yBcB-Tv+~LY-E>HDsl7_3DVvmq??u3+Zm-nSR3eHjF@I zsDr35`8+d}&~olO9*A*yi^$hlOXtTI?Y%TR=liBEjRrsai#)`Wp3)mLIxK1WKyEW8 zsXq%ssDC9N$-JN+e*HG`^6H+-Cd`n^o461`o5I@H;N_WPE*RlKUd&XFu$&IuRQUa@=PqUamh!CCz?gm1=Np zWO1ME#mCWn!Y5_YJ9{0g?uu|u{994Ah1|KlObPUfd`qE7XiV^Af@Hg|r4+`I!lFp@ zvI|*Nc{5SsLYtVFWl#vQUKC8a)BH@eP~l2A(z>S=w7d71<*M*!025YE6r@}dEfGD0 zdt$eFFE{^n^@0AQF_Yj;yqeFjusduViCDSjCg4Dv==oebb0#IBFY-jbApq?- zFhq}puBBylaD!a$Hxd)VZz~30pPM9fs#W39c1ehg&{MhDWEe-X7Q3@&c!ZS%604V( zw0mBYQ5RP~ph~!f4o~DtXx~Cjjd*)Zm?Oe;MqKp;7+FaV9YzDF9I7VbmZ@K*t6GXz zC$t?J8&?BGygqW7d!~1EU@~yD_AVh_gq>6(K?0-mGOT99|RiBH0?;e3aQYOxZe6e3Hq$ryiX6%n*&c z7-9Nt$PItdYR5I(*_I<{p8NS2$=^hwEo*MB_L z!Oxa`i(?cEbid~Vs&qu19HjFg9+ziIAhv%L^w+`d=KBC=*q zGDSH17nL+L#gDx-qLcwvGT^pA>m1$s7LT`KQrD>zT8Q0vCb-Rzyv(d^^xsC9yYxVs zG_VqPA5|D*bGVLOBre3R5tSW`_`~Cqe zMd4@(kx`~wbqu)l^v3FWw{<;gp43O8oSO_n9uRm(;;mE|zd5F7?jIIyS>76+%g=4n+>E(S1u_ ze<3OTR64m8Z|@}~%#Xlg{5jeQakAMQtdcj=RRVm66;N8u9cSC6;Sh{bovI~q96B@c zcySYAU8ea5;2fs;OIJU*Lf^EeGTYWt^F=@ci_yl_sN58}?!EucE$)LMoy7{Ib=OeZ8~c!WXo*zdyO9Iy}>py8NA8sNar()6$u5FmYs z?8)+%xLi`t(9}endMe%wx5L2?1#XXwHmEZ|%s3UMv)Kr;A>wO8UH^Kvus$K^AG2%I zfDvNuWLYL*`o@*2nx47 zY+tfOl{Q_DEEdyal?sApA85&W4p9uEgRtAL2V6hQ;RbYNrU2qci&wO5$TcWsu&}R6 zmrE?)m%Mk<#vT%bI54dEu23Hz!mayd@pXK*tms1xzjNl3gf)$$$W}Qenvyc2EhWhh zX1btEU^+pju@~RW5L2?!h$A zyHW>RC$aiyyrLzm$c*g+k4d3!ys}yKr&mAkL#QSP7)1?%i7CNv&4@0{6mwE5yo}4I z%)ispR*<{_;UzM%loeIU0!}kpX}Cu_JOL3hTpAvUF@Jl5#%aU$vG76ww%8X*BiwIR`szDwrXa( zrUg1<>ch~DjM@b@>cGEOT2xo*vqhuZ7d;r;MAFXP?q4$kPAb|7M{8%lrUA0UppVar zoFE6YV6=bJN}C)V?19Oy)hh?l+u9WMtu!|PhQ9%H4jb>>*{0HKLh?6yF=`A}H;{qRZNuzqqGju2ZwkhaeAd1#wmx(Xdo#%N3HVic7 zbtIz|6@8rA?+;lUp|nYi$AxNGnlor%sk%Pdm3etYY}`j94#hRp^$b=xUd|D#5xt`^ zV2K?OWR)j>2vUh^d>hdxzk8zYFx=h+NeqBzbz$Tq(oa&oWUkrRdUAdrh22bQSrtGerTou@eiX|92vytU{pspZXa z76X7^qu@eo1G|)@1fG6rE%Dqy^oOj<8vU;E&l)f?zo`#5X87N!^NaMq_w)-ltN@NJ zU9UgEJ11|R)$z_+f3^O)2VG5+-Tt#j!p@>VyzaHB)y5yhm5$Gh=-F1TC?^1P+f;>K#@+M+uzU??cYG z_+p>RG{^etusoJelg3>O(EabeDFuw5gwZr*hJ?S4qbR?9fM<)~E6cy_X~(}6pFLqM zj*4|pU~0XR0vg1x<3SVk>4UuDf>AN`eQIh-09tUu)Px~}&8RVP9}lGO?8l*vn5KzTq0 z%W|DIQr{<}OAqrY3-inlwmnW*|82xk^xS3b)|L5bh7^X8ugV?9DiRW<(-PZu224HJiGDtlU~kaOxg}+`Y;2ml15(i<0(p zv_{v4_Y-ieVmB5J>uNon;7zE0~l zxQ;<>{uJmrGPBRDLlO^$2sMNsT-9SNM=&HaRNH!_p>T%zG~h%h9|S22fo|ubQjHO@ zEm3^Ro=+h$Rx>*VK3FZ+-L%I^)Qg_Sk9&0H?ImnyI zwy2x?S2{hWuh;#UNe%Gu>nnscBg;=u?AaA*Md zNLR9S>aj9laaI3QF?^V+>W`@KdQ9}25hPtF4D{YA=@{=pZt_tlI0bou)A=%st-N9^ z_uwLUyQCShKY)=>cp#Y?X*$S{Go~S)QuX&lXBne4ZZnmjT?tgvh=#c*_e-u_S7bsv z4^bm4ScVF8=gS$dW0Qlp8TfG>i0OtJCOq}Oav=Ou^Jz|hi?`1fz0Z`eaz(m+2DSHQmh+CJkAUq|xS2gtsirPH5NkMp{3NNnUSrK`}B} z6AA>0Ra!l}bKB6jO4xzc8Mg_J&LzzMJvLwVcj1-hEbZabE9Ex^RQp6<_y|1h?Bko66{9Kr zW@Q`MCXSH0h;AE>C!(#+Oj7Gjwr2YAn_1g-6#oozj}n!QXX4?O*mc$=*SNv#w3LNq z!9sOQk4JFF9)h-3alYYUU{l6zaB!7`S%v40mInBmGKAS(WwqCVK0Dy~D&;s( z$#c!<8hM`gHS(Rx=0!g0is9DQESSfvlCnNP*u}}9v_ZtV7f+gjATLqHwmo;|$Zql3 z(qWk>+)g5`k4m)MboP`()$D1cCnGNSacZVt;~KqNHK+X&FwEFnW45jX6Z$%PI8(2E zJQvygRPfW($}7t-`^4g)pU!}g>J_6Jp?%{sIIe)B`6*SyQe?(#n6-%_Fx-vN#9H^I z+IIPz=r!yd>Gvv+GZT@nSp@(|UpLXuW)3 zxoO{X?8DU-WkYE}y(l?@==N*YIBKiC8|G3(La*^rZMQy(tOJWJKl+?HnM_-;maLA} zqSogu>Wr1CL8)UG#t{}qe2X%afa=vX7nwiXxme7L4f-e%TxxQV*G63-JqAxhng;*)|c4sqmCGaZ* z-A0FGL$>MjF(>Eci z#c7@e&6!ykTQci)9rP(%`O~%=0eao!ZEQO1ca@?>MD%J~*>{cqIdGwGqBx{~4!Nej z7PjG0$#8DfsR38vY_sKzEJkAkqw&rAIs;L0e-=XGVrP@ZcH2a@hML4pisg+YBt!Ag zCybq^Z|6PbsjJa<^h()-caeW4;3g_*f~;)V^B+5?JS6EOr{O0GQYl-8^BD0@huuc= z@ua(b`vWkAhdL}1c#tA`qd5qgeA&GV)P9Tb3ociHVeoPRU}cUfvAVLM*csh>0|y9n zq(u)}hB-(Hp5*m$K2L3U@>cQ0Tv~d8^-zUvv{soORp5@e4s1G%p`P)KPrGfu9}`ji zuY)>%$`%Ed7&Oymcc+bn|M*t2KFLB(49rCEIv+?`-Y{mmjU6 zSe&-+$UL7fJyn?&yCgIEw#InW8XF{lpW9qH@5|^I*`$p+J(C3s`gFPFZ@HTLDoZl` zN<{S`3I0%pkn=WZ9K2*!0F8_RbE6`f3I0#~xax>xt*x%Olu&y=zH*nz?weRAqj8Qo+J#TpT)6CU+*MEnFk0evhDxP!Hs;b4(`YCFH>l+QG z^;))3A8GW6IFcDDYze9r+CKm^!)g2^9Lv_3qR9%38v@w)|#K@#bt?V>BrSc%*C8Q^;O3;+Ex46ruC7@c`?v!)R7uykm5L=o$PL zdV90_8TyGn3%uKH-BSfBoz1u?$6(KR1*pI7a z^_@cFpK2Y>4SCv>7y5C|{-c8r?Eb+$mos(nTZr>G#RV)9f<}?vUlDJ8@eUr?(6rCZ z(vnUbUWCXMgo*j?c5F0+oz6RlBjAU>7nk)YXCciW>9nem}3TKh=6eV3Z`0$ z_U?qd9k$)KE8=@*BmQoDjo_D_`H_Ir1L6By5})U!-Zz<@K#FS-w5J4nKR(@4uzvTd`qltUZe3LPyDHzty?raPuUh0@_BM;Eq29rCbW^NgF$|0{;vMNN% zdRL(8V^}c(NoejGdTI7pwYGs^QUNJk1XIL zE(R~*b9Z!39ZW5vtzv`9n!rI3lfowDHJTq7zutU@jZ4UX! z;>u_EwB84%cFlwzz0Gv#S##ED{d7tl%=Zc%oH4hztTky{(Z~q}t-SVZA`wd7I{vg* zcgJhA4q+Vsh9Js>{1^oDNv!Dl8{-~MZ&!Av#1wcMQE#zgy3`F1J%lkckq4p_U0-$P zBX<3}oS>hk4bwh>+YXzQc>aWqv*ENOW&PVrHp$`e5NQv}==8{$W)~1IVwJoF$(}cY z@z5}T&$MaF%AFe{g8ji*3;Zy`uC%T?V*!zMJfBKGkQpmr_LzNUX=OH;|8q0mM#&XFEnLS4BpUAgVamnmx#HmZw8QDfnhRns}!J*en|X69Dl#j$mF#@Z$p z^ACD!gi%hYLTa*H+44$-t8MhLgncD{A{-ZiHOxQX~DfJXnxo z>Rkb1%CSao?I0jP_{O{3#YNPWfK=NqcFVNBa{VQVFAa0Fed>LQN4z+!SS!eR&=u3j zE*kfelSzMMB)sn}Pt1P5V;!XzwFGdSci;!7V~1o~#}(PMPWOW$OW3FPR;@VkPB6ff zjTcU^2rmy-owtrR(pylvI9^~zU99ESD^~u%nEbo+$6^CfghNcl*nI*T17ehsh12Fk z*2i2q}u|#jjH6cd8lxi?5MYtF12QD-9(DknZmfWW#c^cPmvkMU%oq(EQx^J@`ma z;P?DiP|FMp$2C(@E3!3b=txBU-IN&yD^sK_uocB;$7iK_u?}{ZR)3e*h@?AH;_bAAx@WcLl?L05rS8#^Y-r zGPiGuyW`s=Ec?%ie*nX$K~Y`rB8B~Ll}#WeaZmG^x4%SE-hwDPZ=YnQp93lSZ(ery ze~KudUjG5m{Sdh`giZ@A9O0XNr@7U@Z-4!#v@k-+%D?gU>hIKF^!B{$;uTIty&|-S z!!8kmo<|+e1kn!JeRoi*A;L_tBRGZ3nmw9Q;(R{4|csXDUfJ1NB{<9eh` z;=5db_@Mzrv15&cEBaP#Yom-5IRQ0A&^E1AG>ZfIWPkbPldhqm-!#G%uKzdR&B|O z&|OROT;(EaBd(Ray{AuUEiC&jU_P0Oe;WGK{$8g)2O6x3}cdL4-DA$Vj?0vFq`)@%d->3xM4@5x> z2`i^rNj`igAd9b~#d(2PzhHu|_@`MrBT83d=EJ}T=u4E;~>jO#-_07bCQ{mic+re_Us!~RXR(}}ab2Rf6L zi~e}}r^8-68#k!yK0r5(h^ljYqy{JlJs+)~I!x&mzTM|Yg6ue$9)AE$5MgK;)I2gH zdSE+@m~<8Gw283?`0@k6%)wtlvSzhtni)MLD~ESyE_ ziHfj9>qRjEXF>4%k`SWpa{L&^0|U^^0KnoOfaeFw-J8@29-37G~9j-YbNA+X`|$SI?@Kj0|uMg%3`9e*i2)S8q?ZLA9Gf$_Jhwpj8p3 zAAQVs#0~Y$W*u?3alJ#<3aZBXS!hi~Mp#XrrKQ6kfe>DXjboNYmn={6XTI~~#@Tu> zXUIzh#(7GMyKV{=`4;?XUDB>R`9q!T10X;io)&>;gF0$F{#*HHzuhT6w~r7R@p4OvDD5$)y*E2p z!dAR@^uAUuF}XUIGarS1wqIgQ#j-MOvo73R=zD^s3!9}b&9J$%N>aHa)2Qq~javR) zc4HX%?86!Xf4Jx#;Zc@}LSAbUHI7+t(EWlOl{u@g^D_6_1>r#J@w(%o=Z>**8kRS-%5S|I*9IS{+0f{6db-o!fg@( zZBX$JZGT7;-76G@1+=*GElHfbyNgz>m&V9ZL>x(RZ2btRV?;zaqKvE^p-)_ANvu{sJ|B<==-r) z6k+0sOiY51>tj=V zU|FNd5Eeq`sLdm`(3j%Q>DYg`zK_a(WUDfgTNpnW`6Qr=f6;hm9^;c+cW|zkbWs%L z^c~~rNVSqdMmF1@>W6xr{Jy&16id3r>|S=+*94pA;CKipwF(C+@*b)HYIPdi!}vwI z$T6o+_Gc4a8e~UU)j)#oj)kzQnT=ZDxRPlHWk>mpaY+|_U=qO3vDrXgc#eXzuDQy@ zTRsBmP&XLrrRvbSLlugqXC||A{5k$W5!^r#uO4f)_*1`)n2AvaZ4)v2nzlm@_Otxn z@C@z-5i@)Pc$c3P|J=||cszM%gU9S4xXFDSld-Xq{^#+I&~Mcx*o>cHtclBe%mTlJ z0n!(jS)!J{QYZIF*>EQ5zLjdKSRyrs1vo-YaH&hy*k12P^W7v$fwgP0@2mU>aUCT+ zNN?|UlM%2K8||=t!gPa+XgKlQ4DILLyM|HK;yk(_Glv`6c`xTj8-Y^{hbCUu4dGik zsa#R8SNZlbOVgFBxyymVxQYk3NDT_0WC||n1f5RJS9YHT2k`^1gJERK1aF-d7$2 z>Lgkrh0BViPew`kVREk_E-!x1?S8rD54%02qc81sC@hwFi7=5$Z_*}zhd1aV`mYpDB1IBaw%hLYfd zYcRHf0W`2Hq*2FS(Rz%8-|Zce*ETwv z`7_0KnQC|pW0ClpM4h1JR{X%CX)4{*1?J99NRB}w9(fq3w(X1X#~EjJ?w>r`=6 zrGIcjk-da>%<9b;TnR;90E7THwN?`V9PS?ss`C%PVHC=5jW4^j>zCxf%6?~=+kfY( zv1HH9D|9C}cS>ULfod=fZm0?V!A#Qg+6is%>JO>%P91w{U+$x`Q9Cy6Q~$|0 z7*=kfA||56ff5L+nC)r5*xM$9Lq{~}Ulb+4h8o%(UcD^Wp|S6Plw+9%k1Y5v@Yn43 zr`VpjZ1gy2Z2bPHNhCg+Ca^K4Id?6xhPm-i0{-?Q76_x%A>fjXKp7yvD- zqjpnQKZyp3y}Wxhg~1uJ!nOBrww?h2%^cST->6eRvGgyLJG4_Da{Y^u6FOEPi6W1C zS#;$11&Xf%7upFM{{Y@6NI@~cu~(COpw|;1C^5FZ`rfHsoNGF|007E=Xp8!{j#?1S z^@8W_lQgJ(!d7Wyz`_2_7F;tKM?=9K$mXBflJs#SY*%!{GW;({?MF%(7k0~sqXN#< z>MuUT4<}(%DlaGZPm#*~u;9u`lASMN;F}~{LVj;>s2cz=(tnDi;m*om$E>f}Y!i22 zf0JWqoRRGQw_(9yI_o1_WW68T6;qcpt$QhwItq*bEfJ6dJ7d8ES+fSYO@reU*YS0A z639ZCEcLfU0GQ)U^s?Vz^%uCbI4iBXnl!ni!Qj8ZUju1k3sws(@M{7#I`$g(^p$XozWfEiC{qy}E5bFW3ZNrfXQ+gvDIc?=;1l?9?7z$a=R7KG<2iOGPaQ^f`=q304l zIQTsPfR_|plzY=mm1fLZcA##a5ljs}gl0f{wrv8`6aTb3BtrW45wSHIq&#Jjwk<0* z0OcSADJai>3<;Z0>87wTtasjHh6)>Cd@jZHKLB__$ENlc#w_G6R}NeZvSbk&VX){J z5zik0XygMuBB)DFHc}ADSB`ZkoO>A08de$|DyROFHdTx=xNR!OrDeEo#i#87+s;5< zbNlc=*k7B^JB^rqE{T5gv1i#O+*$Jn0qCCqs6$B6gFp%^#D9dl+;U$y+>(lURN^7b z@xAc=MZrNuf^{C?%LHkiN2KYa)vc6@g>TkU2mb~CHQ=Ck8x#))@OMC`|2Oo%?xbJ< zKrjFR>O)olc+vj_|6dap!J2?#gX;jmMFGLqAm{%waz!r_u)(l`y`rQCU@)Zr3;EXx z3M2gwo&Fp0Klfyay|8n_13Bl0R(Oh5;)%=-{ zCIM>mgz3TPeO6h<|0yyHNfuoybvrQ4PDJbFGf0Y*1>v^ScfWt1^WS>?|K9)dilc$% zKp<9eD5$@z;-J?A@RwH{^)It{3aO||aWiYk;{MH`%I$ygii0@HMNt0$Lh}HZF+IP7 zz7NsUXhDH~S*fmbC6cCXd*;)i}2Y-iG)gt9e z)r|@531F1oq99r(e>oVvBQGRCLTt{gj6jKW*?WhptcWH0|!N8Vgu- zQz=J9l7@jv18E0JpR!=3%9n`Liy2~@m-=y^OWciy;Khc;-rL-VMi(89p5aoQOX?K; z2S9yR`7qKc1N>e%e&XBh9{}zm!H+DVApJ8>Qo<3)r8xHv zS~qEE|4*L>!to2#*?($)UnAO&THZ!RGM`oBbtiX81=?ugDJJ(+OomC-@_ZUbZ}+GO zaiJu~HE%;&EFo1*&{ccLnZ0_BE||8gxeLnAxJi*~M!guOMp-aMFwzSpTL z+kr!PmEtyrVU~C7-GLI^23^9`jB9W<=)qkZ8njNREvAy} z7phY%-MmVL#GY*|J_)t~hZF^@H4RLQN10d^;P4=EJKY?pcoVy`-NVk^ynW40`&jHz zj!ipgU~F(7gm{xnL38o?h*03RC~RmgrQ=vk?Lw~F(b>H`=4}O+R==Y)#)`P zz+=QWi{ocT@FGlIvi(Y!50>UgS>5j*rY!ikR5CeIwMxGFMBh+TA#TNQGlqtFu{osnnPLSS*h37V9KxO<5%JCl>tu*96|CeAd{>#ISCsPm; z+cUCL-PLuCbTW~dmaSV`P=!S}#3bf7Eahr|j^VSSRN{eAl`nZgqe|bKA=#rTbtj^1g+26LB|xrap73?p=<%Vp1m> zG2BudbWPHpDS*++uBm3MTIuHn|4CQ}hw7M+&U+ruXTj?O<9%+YAr*ytjkMnmS$EBo z<1!QJqA=oOC7sUI>wnpxmZ60e87hrhTP3H^5F`;+e1rpg=9+tQrkLZzsr|WZ3c@cT zxe@hq#p8WL2l>;W-oaRj$!2t~f{eT4V5*zQo#2Td#}ZZ73(RNto!Euk;@+K%xa^7$ z588Sj4tI1~6CiV+&Nu~2gRw!M_6GN7zZ4}DSL2TnghE%O=3ik`PZXiMZnxNjTY=Qz zLh~bVdVYm5l9k;|JS z*4z`nr8A7RmwKGU$$BsXVYjRSjQ)lCE%I0_J~6iQzfH>305`e*0~ zi+d5oUDhQDZVYuc5*L&l`T3v)ba_RN_RuCXP;OvkZ;$ZYHwK0d`584pmStM2?&N0jT61PE5tS??ji62e3MCL^F{h z@C>`OO0&XNRJ+mn%(*RG3nAbCw{awm@D`7?FgSHu&vqSC7mHjDj{d0AJmERCTXw#^5jB*{0!_Ypa z0o@_;A*%e2%41Nt^xd~39NhD-D*L#K=S}RvWAUsN9z{%Zt_EICS^GS_V7z1ZP&|t9 zxVp_m=9OIWOWVGZEl$L$JqefC?Kxvt<)2GYdx; z=cO)}kl~Nf!B>tB9KPi4Lwk)%1JbDvan65>Oj1?D^L3_CnJA zmbCRD^Am6!s8Mgdq>e;%Psj+r$bn^Q8bNzjfvYFjguNB$EjG9#AQ-B7STWJCxM;!R zL?pFTgt4*+c1i2VU*&r5KiIY%c>|K37A|k@E83#0fm^SH0q0`FKWW#6Xe*EpVny%| z+2MBps;cf_xH74Pm~%*~O>DREf#hw#Ml`7jP8h;+Ft8cLR#-QRBYsJuMqp2_s?CC& zj3zWBszA&PuWkSidiZ8|z8 zohT(ep0u*8+KNxigJ{NKfizmd`U=8&0QdR=$s4msMlsobTrqw|-5HJ#D9NjsfQ?3_ zb+v;$a{ZEi^z=66>i1#62ih~jo>u^ptEi+LG*d~_e?moHAQ!r3PbEhsH%yz6tu1Lq zNmLu0LBMAc2W+|aUa3s(9alVCNLiYO8}|BDosLTvDWy0aUujKaJ=^rO$c?&j$&i~G^SCe`72|FnUpSgo!Ov;Afy9eC)#Rvo54jg=`Yg$-{+)mwg0YI)&w2j_r;mxut27mdgz zWW&#nM8N8*ifA7PJ0#cQk#0n*HX!39^q=ex9pqLlf#QwJ8*czpp<60P%k0e|F`6bg zggwfm(7@M5Ba%wQ%{GfoX!U6=1)_Hq72k!_36cVIdmu*ntG~8%%HTwwyvgV`8wfrF#It`r0fM7kzjEmh3mqLq^mzP5viXW((Nr5N# z!^@O9ShNUEKYc{qI~&%+N0M$mnc2a=id>3L9jEQlUbrYW5n~_tEb$n6%ZG0Rya~@$%?{Ouh(ez@NBD>kYn3P_o}A?{uV z8*XhvT{VbU4>U(!?MxVzq9=DJE@V&5Q66CWlTr_Nwo(uH;{*4mLsRYfW2Kr04d~SK zsIcwu$X+$|1L|2s=(lqJxMbx5x+R}}8H=wAFz)fF)PuF!5uipG%`o^qt>1DMwMwAR zp?1QixTq653&G}A&%ay?%Q|f$pCR~RIx}0r6Grcl*}bp;cNXKU2BN%??UN}xMFzzg z+Ae5jxH33Na0AE@u1`&35`yClq?z2K+KfDOW9oKU1hK<>-6O&DP>HmO_*Gflp(_Ya zfhKIUUB{WWzQwveW=MQt7Ux~}+Ad`%wAZDcTZ32uYSE$c17%j}0~)+Gy1?UzUd?F5 z95P3wlx`b^s&CG45PA?ptSTk?B*xilx1Ks18vhv6UMHe9FTvv9@0Gh(LM(0n+(A43 zZ32uI-WqNElU$7{wlXK4sMd$KLi{Sbv2{RGn6tmrlm+H_SL}@^irG(3RJ}X9G5TLN zZ(&k?2GUe^y(uaFO8*s5v~m73keWKG8zsVvM(U?zuF#|+-A`#A;v<7bSIy#00;j5+ z$PMb6F21fF$5Dl^js_bA90eRNBGpd!?{fWx7eQ8!Ooi8vB41t$GyVY7e~VPV7p{EF z{|y&ueJxynSN`!)s=#o4)D$1{b%%_6gWkI3OOZVlnTqB#f&~?)mb$U$D;Rlav`Yjh z7X~T+Ois)az6PFbD+k-$ef$=Ba?q=Z4hW&s$%j6>YXmarSbh(qO+4GZlN zVCP3e>t|jCQ9l1|dA~7rPrG`B>2rGIadWKdO$Od=&E2)4^jfZ^&qYY`@tw!x!~CRSUw@6e@y2hKbCpJ7{C>i_rysGEV;fYq4k zw>q&DO!o2>8b1+iI*=Af`;Z|Nz0Hg+NcAX+JU(VoJ~5)Lo^_#Od{owuo5wgIUjq$8 zmb}_tA1os;H@{IHZ{D0xCSPv+PX8aa-UArU?`;EKYxTwM>Ydg5>Rpt@>b(ZRt{Oyd z5xrZzEkX2>h?)qAh_bpUAwh^0u{ zbzL7v>cqR(pKkp|uHK>tPE;dR2X7+punhi;ie$h12cXOWU0>S2zPOo{d$)aU{Dk`U z)XhEW;p6KkPe^*Br%CW(vJug$cY+L$E;(sN29jrPtI2_9|JDPz4*rIza`$PJQnP@< z^LYOOptrAYsBZ%g8>-RMGZ$I^0Pd16^ql}!j)tY1`9H{UAd~i@Bwijf;I(`H0Ss+k z-hOcW*iq5x*2R;HXPYOH@1Ah)2RD1#&oMcIS_E4!ug4=dd}dW) zWl@x#@7q?NZ$~%5;3VQVk8AZlTD=sqXf)rszWB?(FCHwXJWji$dlDv#!ya9K6$N<@ zSU+GoO|j+@Xv-0sox=iObq$79h|bHe$qPqETHjYa@hS4aCm#W9Z08g$p6f@B+4Fsq zzn(moeL{`D;r&s!S8PVurpm8oNt4!)nbKz(!7>md#yo!ZQ6=FyP&lmlsz^-4rQtB| z9arXGhCXzG1|o(v$$pSDWHOS2M$pB2=B{c-fHkf`1>5Mdj~jN;#=ZI+;k~TD-$w%02>#sieRX)r*_EyhP{q0e-R7(Y$7d2W~ z+p+7jU%bkRB;V+F!;_!Yh!{`XQeVWXZ-K1uQr*{9S5-if{DD6ONP9y~R`2z*4^+#R zv~BC)R8{!#TAhSgV4;au zHz%fpUP~lDKc?swRapCoyx>g8qJ>fW{JEBF;laJ@k^c?U0SQ3=+P}1p{|(ehKsawB zb+>UkL~Kr*$;K_Sqf_?DZEBO00QlcP9q@5A;?6`#Tcit8s5*rZ=N!yRor=tv0P89#bt_QyWlF5+A?aK^95JE$dojPm%?6YAGbt=m*&7 zf5x@?a8_+hxyraP2h)j)=)Aig(fLw;NGBSLObp8YoMeJbOl?S&@DZ2J%(u5RakNnFdUeML*BZTioH#5G&{`!rjBeIz6f#km&8K6yP z(<}BMs+6v?g>V<52rZ#CpoT7cP#@dw$oMN0?-T~H$=q2$C)oCjkXZdEQ4I*a;s*xI zV!U0a9hsKjY=nL51U7Pu#3!QF96FzVV$`U`f=wVuITcyU`!ME_H0 z@UQS37_VN)TM%VfY^)q?-u-(DQ534GAF|!`>bCOV!Z0#aYcMPQ|ZX$+ju_~6`yy0*#ew}6EZSl@w8Hd)zSq*ylgIzBLbOp zhjl_J*AGBhl+ZesSJB;lEJ8e~fH(~FMbpB0kNh542%e5cA8wtY1=i{cWO9*PI{VFf z6!PkCw<1N+%RvtsiFI3EdrPJe^%(|oNR3Zd<2Q%x4GWc2$0diZVWE)7BC{(}0GPL6 z7h&JZrisU}^7m4x{4QwxxuiNCA%NxIy zr{3Dv|JZ;0+b4~lsT=Bch7jixL-{nbuC7+kB5=;93J1k3J@@v9{QtF%jTNT%Br18Z z%d}g09Hxes7F4h)F{gVTI^5vYbMRnr)4fM)ao#&sR>d{JW7R6q>f)rz=VAe61MHB< zyqN$7M%H|34Lvom$S$vGuMm}tRPPw>aN^f4D+eKFE(5aRmNP#)_i58Xi=0$C#Y^du zzhZYNHQd&6W&F+Un82tVp)F^khQDWWrx0K&YI_0l9PYC3Kz;K}Ju~_%od!Y&r-J2i=9Ln+WxTyi#3>emcgN z?4(pl0fF|saZ0=9wOzJhnE@@E^yD?sscr>Lk(7Bx(t3%fGMRO_^ai=1`Ob?E_Zcpe zVh?tJs0jBt`V*m$l*bJWbV9qS1v~)T%fboXaBhd1!-~JQYBgDwywsaO_a?C8y(;aT z`7kw0L+-{pak*Tf{;&-~$+z15hMJ%FpGMR_1>E1XuYwNxy@b_j`Ek2c5WzO#uJi5R z7#SiwRqGU&lyiVbDN)2@HEyY{T+$_mezjthE_N1Hwu3ST;69ee99&bj{AN}1EBbNV zh_7ngL2|5mDU?fhj^B@jOGf>yqlnSPNgY!eLO)Aq)}?N9`Mj;#illWBsP&`zp%kSx zh|s3WUhL`ysr;b8g>P&Ca;%x_lg%nL@R2n9{qdw+x;4QvI#8E}219gXM?po+LeeAt z5C1jFYx@f~9zIa@N9L*~yb1ax3dxHfP(UvyK3G>Yc(Wy=`LIwyzAv;O|ABJwB z20NUKIbGcKN_#a6GN#?3xCDAIN?bwW>CFRvpWA(Pdxj1MyLxKT=-{@(^wfu0#~gX2 z{~(S#*Cr#uT4??0C5h3Z7hPI9yDTTqq|QdxtM`BQ z%5bN-?NSB5G$Uo@SbuNzu){aONX97F3;pAw4T_@^;eeX;7kZ2nc9q2@owi_nBR6d+ zVQ~Q4q{;Vab5V8Fsp(Ph587qdjS4L(O;7sKjcjYCIDn73Y%+7s}bEW+g&8*VXj z22uyG{H`YNoefRFU9+b$%xfGs=H0^Qj)s?B1$S>72}dkO!L32Y>{K1HL)nfUgemE4 ztDX`LGc}@w5t|6o_Z|#5?2A71G45I3bOxdo#8n0Y;@>MK$kl z`y1c58+t{ry64c1BE$1O@#)s99ka)YR2@Xl!XBcp zZfLtLM`d@aMDtMJywY<$X(9MJ(75lGx1Ff8+oSr=|26A(iLTna1OEojhww~zXlFR@ zeN-(e82Z_Qv|L`?_QpDn@czzIhtHmDT50{uE$=7cS{OUS&#*1hBPY8UtQOvAmvjVdP+!Tybg-2;70^y|W$O@uG-tnx_gK}PgWc&4Qt(EsA3mZ{vTxB}mX4|Q* zwzhRbxLQo{ta6~Z*r3sY*ruu8vkI{_Xwnbp^qcl%v(yy7Dei zE&olokDssfmS00TSj$oRlHY-)!@~!L1q++r2R%KMdetk@t5!ZK3!(wJ!XdDnj{HbB zN<*sSz6m*DAyA>j3)e|4gCD?77X4IpLac#?d9F1vx|hfT;5WBjrc-L=15?b08WagZ z%@GZJj*jLGHWcLcO8B4ZxDFv6JHN>zx@A^b=Yj&29OdojkZUL?MS(6`OBA{{i#eLl5KYG>)SiRWw}kO1{L*#8-VYK<;s zZZHHi8eFA%Ptpz*!Isz^p37U}E$eLB;-|0 z|4z9L1T7!yC;xAm#>Lw6auZ?6Cz$2Pfh!+n{Q3oAD+aLj#p+4y#|C1YccI-iGID8E z!BS{@2kaVSmJ9DPlgWfv6|6Sq1fxIjvS;6W8KmA0@>$26)Q<|$hZ*QAy!Q&{6o%-7 zzm}CdA0>{?Q__QO!8Tncjx46q7R#)}UD-?t_IHzeA7oZOx}*%#_zDq6#BP<9oBAaj zWu&7gGE|w%|2yY%33M4qeb)<*IYltg-C6MtgeBZ&O}0Qn^r7&infv~=)IZE8Ns1p9 zCsSS`SOr^D87%c*dYP1m8bc>M01cwPPJoiH>19&J)E77THi~0)2Pid! zR3F}|1))b&)$&8V)*VT`R`7ny9&QotbrI-QSO%2+m@+vv*)u63-mF$nG~!9GU9b7T z4$=y?&YNQ=Ket_I-+31db$ezSJaTG$l;jgr69^afUhLyzMFJ*2xy?cvka6>`KO3Yu zA+Z)-sbX9kg_H8P$!Y=P#gzCk&iSX-c;nRbC%QHT8CZ2g|7XMRWYR1soZ>e`Php2C zK5!aMrU1r{oj@m4Ah~mqoSdAn zoWhM7mE4f%9nbo)XbilIIYXzf?4y1hgVl9sU zWsLbBQ+xQ1N(xLoJ1L=2`@zbov%-j5*Df)R64dh!sz2d3XHP>aLv$$mqLU@=DM)GE z%k)JJ9uF8}EiOnb^fH^TObrb5tDriz8#8hK4XZ+H{){1#ov@8YyrHZU8NXa!z?=Vk-)o z$j{;id=_pPXiFNk@1lDe=h@|9VM#-CQb_JE(6lzuf}C3SB{f}@X6X*GV3weJn!@yk zO)qxWTK+<-JFGF7KF3p>0mGaWp7DygSaKAGPtT_}T6Gp%^y4D06Ek~(OVNU`_|3Pl zx@PDrxDxNkK4Zcfg3!7xsb^1g|7#m}@N32=%pW@4r5y~c;Cnw3#L6|ORwZ6ljfyi;TD|u=2Lu=-Xx1#C7YaB=>#P$w67M+rT#Nv zP$joMj1UdowYcR?l4GoeKI4NEySSJwrNsNuyU6IKglj)t#|%z+Kz=3}e-3v+e=c5& z^za`l_}%Zw$)YeM2C%5b+7YCNUJG~BEPwdEFMGxk6dDwI{ypg({*9vHTd}FU2kNhM zLUp1YNAF+j|Np-vn0I?rkI6CfN38WiHDxqT_HT0NKLApn8>(Ay)?ND7$>KI&{^qv- z13(6pdA%-RIQ^rT@%qm@ee18^4-UV5`TyQ#YfnzU<-q;QI{jN;dy7zSNcV`E5L>>9 zHvJyWe--mQnlt_HE%>FomDq0udz#@7(-S#EXSvdLi;XiwlB^9)4JgTWJ_3T+6rcji_(tsZ{Z!U`-r}>!E8u={EWL{ZIOHMXlHJ zMf4zlZ8Pj$2!#n%FINM(Nb{-3H?qR`7d<9^n(;5gH_G-r+}uojLEViHl6K!DncL6H zJf)If$ly6gRz>g)u-bRMB(7SK60$e#Uga^U-Nbpxh9RQqy(|Rh$z$f&4CTowdpyB# zb(yIuY{Nmx9a2fohN@VD_w}bxEs8kioj_efXMHy}lvF3$7mQ?1wAw-nClqMym0$B{ z2K4tCPMX>{Hw?KD6g*C(iz@)9yopptHm#BCmLJ22y5K4EKKbJp@nQ-wN@{NNep~7K zdIiFT4Jha2thIqlq~58Jn|qSeB&7?6aT+W^2Q}4eZ0wF>uXB~G{w;E0b=vY$ab{`=SgNimvFYtI^OW0cQ2zg` z2|@_`uO`U9;Ug#);D0qi{v!zj;oLy{A5DUTB)U0z^PAm3g=1CP?Z8d~YS6m#Tx722)P zZ#Tck3|zjEio$W8-Ll;eja@j+`)z|g8Hun>dv@a0{kPe3!vR@VkNAtreIgna%o z5xB4PBsRe?F8nk@z0)w#f06)ZNbPvRYscwi|NGZyMW0O9lU@U*Xj%jRH7I$1cC?D5 zyg;nl5yuY=?GxKvp5Eve@?`2F`q|G!Gq(MysufP--g(Ef+2G zLK@tyD-M|*R%7aW&V4KL$*qj8t78^^mw&b0r_PCyy%>ZOlV$aRYXwrAE*Jd^7{i2= z3b%^RlS^0=ekh+f_Eyvy(x?_UIghQr%;u!^YGz}$d zf_kLenPSL_<9B-eiQl>an8o+fLlCX}^BksF?;MR{S9tgSV&B&nkd4L@-EfRBX$8Q9 zYJ`#AvCW-P?Gyb~xwVlj=1xGaGx0s9?NJUJ!>Z6gtY*Gk(Py-+HY%mvLdof3la!Ji zu>Bw_nX!NPg?dC$U`$M0=kTG6pA52EUX(P0{#BD7(NltQwKtbtXHYP(%FX4?`K?Bi zpczqdI_Lc+v7}6L?x0K&vO9W#&ZQw-!U@zg4xW<<^q& zR~nwY-F|lgW*qDs+H9+Xw3-3!fHA=lTNW`=&5?WG!mrAs>Yp_J$C3Ti2SN+0ak8Y^ zCo!BRq;yaW=JFG#yV!r)A7fffEY2%+OIjWd>?Vckaml_OdL2{}6R8m4#F#((89L%q zq`=btJ=2lw(JOiJLh|v;$SB6)4G+>#s^)IxHv}+DPDb9EY=a0{BF=Y!cW)~R8A@}< z=F6}5^CqIp4{qg|stz2GNsBs76FZJ*NDE&O=lsP0HnwVUV~v~&?Vn@R7E@uz=6C~c z;FKq`{Ou1@%juZ?+Ohy%EaB0@E04OhH+qD)4QTe#Hc+FR%Hcn`%)`ZYM*$Pu2Pp(5 zoJ)>IIGoEI)!P$L8{t^Yqz-q{t2JI38>#nu+T!w?W4XCc-J1}n1@v_`sX)UkAe?4*WinjE4Gor1dJ|6&j)82%@{qEhBRLQBu{z}71WfAHZr$g8qff( z?-k-28c(lbxg`s&?w-lNaGchg4U*ULhTQ$RqI zlC(%B2q$0RmK)H|gUs#!9r^WAE+q^5nz8buYF7+zar)53b)aE{{REHf(F+ z#*8&S5RwQ5Ghv4tSeYwu#y8()zbS~-VOg)Yd`V`m2`D+%LHGz!Wa>{XdQkMpNhlBW zSdY?fyJM80veIFw9QWa=+f;&o)(lXI&9~j5+GD!WxDGaxgMw=>4C_W*&Yw>I*-U!E zRDo6)jNZN4lt!uxI&V>vY=;m^Ox_@z6b0j`zH?u7Zwo&h7LI}63&X|xF+nv1(58oZ z*-Wwskw2>nW`U!+;!<0ytzrwL1m%y{HqxXLCZA8N40pn^Gaysr%Ly-AY?XEMB-TO2 z?zhkm`|Id~Cs{Xvx2J5Ixd>@D&iIE39WWX!_09C)58i`l?w12XoH8ed9Ms>3wD zmaG~pU+!_JGIF?nyOFvN1#l{}A!>r;iL22n{4E1i^& z8}=JsZ}I2F2ad3JWlJ%~S0m*XxG)6AOoP0ns172~Htf<0v`6~U4Rw+;@>Fn8aJn)p z-_gBnqX3eu{;t{MXKO| zpb}Nl&mnvEOATH(H(}nKY#{g3f{k52>1&b-%lcOeP8dKHLvNNuY}BbsaXxTdENuAV zV8<5r*NU@xCe`J+jKqE{5dk2XV+n|bdHw~^wwgWU0|4WwufbwmMn=X~utU?8u{L<) zM|(mto+5&qYh~wBgM9rL+xbuJo8-RUE9D}}_6av{+Nm^DqZxlB5%Z(Zn0F@t337x( zou|En2E7&XvXbjsGjpD6&hG(uQryBz8MDz3X`~{;w|Gp0MMs}q1rHN7z7@4PkKE2g zs@d9efH9wLv^VtC<0^&J%8-AI3>WR96!HeX)_ua>URb_*)qp941v*)QE+ko7e;q|~C$sv{T%v=Fdj?uEid z$TmCl1^41XF5SeCD22ugrybB^{$!iX5>$z$Z1o(Jj-I}~%0!*7Jrb{30@_~?F`vw9 z)I|>q&K1Wgu~IEXX`)F=m3#}3{>tAE$#NR|m`v_BEEBDCBd9&|w$uAbkp_eZ1iP(; zGhOq>Ys8iwSXhlr(cV)Gc&%AX=mhY)PnQrXrqessvsr}$zUpPg{Z;uXP@msn#*aOy zsxH@Rg`LN5Vo_@~QY)o2#mm0YO6yL!uCz;vS6eGvn7C@?%Yi?gC*jZ0trc=^RJq1s zeO^W}%0+QVF!sp)a)kE-pfOr-z|YRYuP6r4NTL|Gg|Y17^N6bg&g)iVZ5K~gt6Aq*`F%#F0}#jDz0`!D3%3UY=>7k4T2qUFAuBVJ~5Zx7880l zbD_=GK04%bB?P1YhIuw3|8Y5*t?d)3{(HhNZ`WvK$t!XsK2bWM67Netk2(9qWMBrc zZ2J5=s+%b&&W_+<%{UoiM9fTcF#VtgElByy42uNBG$$Ku$v3T@yi&qU*h(-B8_6j+ zKOX6nRj8l4CE9<#4;3B!iiQum=oa+{Jhvs!Tqe5M+Vdl#W8ylzWD;WLH*I$;Ergn! z2?;Se003$ z0ra&r@H&l;(AZ#%onag0c_9{V#b@x8o#5iv(0aTr-~N~qlZ@_B-r?RY^eDinTjgFR zv=O1Zbd;ySbEFcbF!fXE+CM}WxvoB%gkSS6F{7YANoz>q>p#a!$IMH&;hq@Kg1H5l ztjMYvng~D$=-(}m$29!TQrS|vW}Ja*;Sw(@TEk>>qQMMmO#x(g753A|tGq<)iGuOC zGPA?f(Gn~J7L|dVU|+;lRS_`h$i=Gv=4IS<*QP~t%*Ks8`NNs|04Z`L` zY{wZ~Weo9*aP?knW}eHI=}N?~?cf!SYl^i;j4yHvqi&b57Qpp=zsUCi%xvfpG+yO^p_KsS%OEb5NAO4*gpV_fGE9SX%;xFTe*6QN-tAgg;+l+9g87Eo_tK`GMSfR zMbmQSm-t=`y+%Tqa?7-z*mLNL@-XdNG45#qP_jX;KR@autF&t-4seEsgbxBiFi2d) zgJvWiK*#oO#S60fly4ZRIWe}trI)FOiW&3`+ubp6)nkIE6sh;QcLA$)PtV2-+;kr?xaxhPEbE$2nQIQ4M~q}h;l7xPG{&F^bk3A|yui@n?u z)RE(gSEy;z;C-C&b)5faBgMnL@?!d=_DSv*5~tf=b8t~rGd5N9&`gy|In@Z$aP=xJ zK77Prxo5BbMD^kN>Um!N`fir}!W_kvl-o@!5J;oFgFK&*-OD4ROgeraAuqBhW_7y^ zk`BFO^edAphBylwZ*5E$XC6zc#VCD(d>b%bkKDKf(q`i_P1l|~jY^N51vw@Kd{d9n zm^tWWQiy9jeWXQFCqy4dLv;TifPwFIy^uwjBtb@|fI@!|fRCjd@!c+!UT+dLKQNTG zc}GN%n-`oCx<_7bLawIUmJ!;QOF#4G&Eg(?wzk$qYUbq>qncWlynvzR>@r0|jV3gj z5<`hGqxljsULzo~91!uY3qizCc-KR8|4vUryTftstD=fjF1@D{A5>YVJW?cpitp-3 zIKWb^>qo>b{Cq8ZDuHu^Yr=ILnI2ODSk*@XJx~1mVDaATvN<`cs3z9gcbc@fNBOw< z7b8#5^prLmaW9zN!@N@to`5c&3?L0^zF84+g^v}5?<%a-$*O6%)?3dGzxAI4@rp1^ z+D8V+1=pmJF(waylTNXOR$(e6?&;*-t zlcR0W>-vKrbFE0J*%#k4$T5*7UaastdWkkc#*e*!7S0A#*QLO1vTCF;IJ|eF55wmk z5egxErR*|{*9hgtvCqut41bq){o%C#g;_U3jZudfMTrw%vwtw zEKtfQQNus!nWH2ITfXRneVmE-Bx0rcNHY93OLe&u*1vz0Y%_L^<DWt7y)%7rf!;;;AS5H=8Setr_Ep?EvbkWDma=d8SqjXC zj|c#MeRIBJ=YEG0-+z=FNPu48mzHn)Lav$)&jH&@1yn)yka-;&_4okdepaV=5h3v% z7Ce2R8sz0#v%=Fl(;DSrxO8Q%{p5OBjAQBKz~2+Tco$o_WqL&_l%DVJ!gyL&&q&YH zUlX?rfN5k<@D{yIWeuTtZ|dl_M`WL}GAMazpf$dr02!1$N;s1lXBaMuZ_O5UcoO-e zxJT-hJkq_+h^<9_Ae8?ku=Ihr{E)u!J7|b58qfn=N4)}CPMT`_5b1Bb`~g2k4R4qD zClFm-&eH^&7>>2zlvPx5(^pDNesnk8@v4&UM9#l$@Ie>fIkr$n!c+kV5z&Z_%- zL(>FGN-T2&(SyWLb^~01%dxO&XuOJLN=MvOuD8FJ8Ly<97$?pplM}@_W7M<#+Z$#``M}FZh+rb}-g`l37@!ndnW9GRf#3N|L^}d^{}qpjDx`Xqc9R zr;S16Xj;Btyn$EzH*KLPEna)m|0WWE(1MCqI-lF`7HE#LX;FJ?=lr64Dc&hu!~3FL zeUB&|<8rni7Nu}Hx^u_)SKq6xh@E#zTR9gG%5UdxhX;}5kK2#^lZ*{us$H*2Z=uEv zSoHT&m&@|wSUz_F0bBj%UpgdC9}MyCwjzJE&HIKOv)V^MZ%qWs_2m!bMH%eDNo*TU z0=*&1?&7rcjw%ngUSWv@`yzCaA&5buN~B45RuWa1>Co4Qn=Uz|1#*u;CH+`T^T5sKy9#YTk)+bdw6iXyfbzWz4ao?HD=Vov$@NOaTFS zK0oZ1MskA=-R?IB_x_^xKOfMLBuf}Q0CM?HL4jaBo_eV?!4VU+SsP_+*kFND*OzOC zWobD;L(M*aDIHMPNuLI}^&%|Rb$-CQ*@x{d6RENPAQxOq-z%UfB~-vzJ9uj&_dKLq zQ}96QFr5yPOXj^`Z2zj4Bhz4kbvNUo^YN5SsZsd*(6MC7-L2}lA#Lx$DE4A&pr~Au zlb9)!Q*gGagyt04fVz8Z$rjb5$oYD|^^EJ0F7`@dOW&N7dpS$o03u92?@)&20P)he z`gqQOB*!|q1WB|JwP4{U0nN{kQ$_@dP&A|U*eAo z{c8sNx(yR|Im^AFi++hBQxZnfSh8XlD_tK9kF-a|#x=Wy6Ak%--q{u-**cEBRPO8( zISBQkBx*`hkxWgy-zZCPAOIl}TS+_!Vb0_JW!=^j(5|-qLP%#wKNc6%lk-hg;Qb6} zkk5C0YmT3PnZJ{LNiklSd}1#=ut_rDQ6O&YkkMdkP(Z`Ls9krQ*FjQ^sONEhe8<=_ z&u9q`lIJ4ju%|djq`{|}*HXKb>|n}HK}ti@^USDvguNq)6{X9wq#~1jZ(CaP;T|6k zSw@|NC2avs&PghHax+WP_5A(h>0S+^;bzk_ED9#sno@Z0s#Mo0Ni9D53fw>Y_Hx)D z8&vCbMCfC2wcX+vfEG#}_2BvAigWF_Um3hT`dl4jWl@Neivb?NtoidqE%g+OMfvOn z4oaaEwq6WM@7#w`Iondg{{D?`S50yOHo-4P35u&UZRgy(({!ai7!={WP`FYlittiD`H9ao#e-Z&xQ@P+-;g_v8=CUwx|uBFwMy%GsbYfwA!oV zJSmlu!UE*tzohcp++xGxD)t*>_6UUH^j=ppR^_Lb^xjkxh7F%2T#J&^z%f0K{IlV) z5H4LKmIj_GBBp-;hzdQZun%T^2$F5%^4^u)%Okz-&)zius);5;ygNkXHi>$9cGgeS z>m?5T2jHf2Q_S%T6TOu4AD>AOg-4C*cX{YCe;n@`h|>1d5?R#q`-R`++m_^{ZztG; zc9Rzu8DGg~tyRA5T?EhYmg($gE)9E*?$TEL+?4W88Yxw=tL7EPa{KUxDBQPH9MN8i z!R|XqT!y{KHUxolh&LHeBZg&th2Y9>_DlM5Mm18_q6$(tEo^70Joo$G^xq@YwNA`a zu-wIHETc1kRPVO(P&@^K=52T>S63*0p&1gZz~`;AXU`2Wqh^WDysz*|xn$~H&Na_z z-hyhlil1*l<=C^Wi&DY!K|5Xs7+IfFm6@bO3>#W#bVHAB^;nYxq5-n`aV@c7Xi}cs zOw~@P<`^0;**J7|_rKCuegVZk&yT8dK zj5#DQX-LZVIsk}(;2(gFt(4}GJU61OGx;dT+8zFrMYu(4+ssu?bJ2;V)sA+8C3u+W zlSQ(NQ*hvZJfkV8d-eE9UO{$+fIi=Y4Cnj=wH!I9y5e`-zAhK5cW_z2n5(N(ET_iRhpr_;bK^J8bw`q18x-I)85Ve?P zWe?!6>t*aIqMnu=boH@GlWv!!X+20pk@62Wh%rkmc_jHX zf}G}!CZBgQJ0mr|ziMf#lpvC4ewxql0REHnBn`zZ@|Lh!<4sM!eB4$WdzVE$>telS zQO?iv?>GK7(`5CthuJAw{xPE~De5;)8+eY?`N3vgWNJd`UNbXV0!i*qI_}yN(@(lF zsLli(NTwPvd>Ya)u+Y*v{B+}VKp~FcYd`E%hEPJLp{3C99{^h{pj-krJ^q(}O#rE( z^vm3<fe#duPwPA>#-*x*Idswv(Ro8<%8!eKUK!&gaS2zlm4<-0~Z5=<($C$eQBkNJjM z5=Ld|&gOO zxTBAv?5KL%4uTd$DNb0}78+M{i2XpRuT#fFz!g6aZ3sQW_LWk%I-M|?EPW0@U&wBd zd>LLd-?ZK`fO7R~HZzr3T~XDzjQiy&s-(rn2C3@qCSF%*iW7-~3_dH>sxVDUIK z6B<6(|5*}aAsu4?Nb+UF8wu3%=-Rr}uKPi@*FCUo0@TXbwRC6>iM+OvYBfq92n0p1l9APKAOL!z-#} z8UEbK25|STMI;#Lwpbyax>l!F0TR6Mj-auV(`qL~sB zf~z(4_3&}OM32pS=FoqGUw1RBb4R`y?9^`k@?Q)A&uZ!AM-no@npCB*gLeIlj;cQ5Mkt}@+e{!ueA17WNh9g5H0102r z6^)Yb|LzxXa*AcS(*j6N869!eU_=8rH4McIhM3fi(0{jSS|Bm|gHthqJ*gDq9IUQW zg^)(B*9)ZMo;X`sG73brhv}ekjA0HK!2?9FFWosi` zWa)cRIRjmk%f&&P4>wGZ#p|gDGs8aMLU?_P!B>HdM)uiZdmKPhP0Izpz`QCa2*Ft? zg$#y%W>qXbP=oH$>^H4V(~;^00q-RlEXmOA~<48Gm9vouXl8@L6{A#Nh(z`(Y+z-K&ZbSQ4+CTBuI53Xvdx zJT(Wnk|Cx~yTS(>3T;~@%|Djkmj7XcZV)>yLYhZ8{~XI-T3i1FAdO}z4l z%&s-7>DCF9e_k`-2XYabQ#-!9VzYLI{5^TOJwy8IQ2r^d0IzQyXmj4cGpOFWXPyLP zvf$_>kTwlC$gDucr9MfL%8f~*auVm(X9f2X{LtDA0HnovLmg%M9W)F50nxCM7);tO^W=!V(}e%*+u_>(qkli^77e%$AtTXj)?&_u71Qt+@mUuuY3|?~T}e2pK0Mr- z+FX40cWa4uJ6S|GHXl%FMEcN*28iuXhY+I+M)K3(sIS2T$O{-yy~-#`3^kBl!zkXk zswq^dAx7qjf80p$dig_uJIrTpI#Po*sbA(1yI(q;6JpxHSep~IWyCd35Q+-2QVKpv zd+p213!dpZ$yRXth~LO(%j}08g(U#$Ob*0%kAVZAlUOXSsWGCP2^!}Gg&;3aa%o6q zl_oOsg?R|nwrC3!0!%}jFqOV!xlar#;$|~EHn4mMepeu*UK&t&?ViSl=xBecXyc;@crK`xe{8r;W z>DU&NOnyi39DCm*o9vD4lirEnOHqHs*IfU6fA=Uimqdg^B2_qZgN@t&4Vg%J`UMZy zs8OgakGeyvS{`Vz-7gRe7_FG@Qs&p5iF54PYS5x%aO=7$< z@*kWe={hS*)d3!1?+@Igdo|!#)J*kC{zu5P5T4@kAovI9*z=t1AP`LEj(H|71&}YH`Bjbmf*I8Gf%RH44$f&%_I_cS zNSd+%TFG4)t`y>oU08g)Wy zttaC40-FhOB??%gEmmygKgj++@o)-C2*Pfeoi)xG+`UM&T;OS`0WBgi$0am<q(QGiPc>6_9bngnxxwRUxe zLj0fjaR{Ot8JAurssN+NY3EMy1FzytAN>OetMUNGL^4n^bNljm5nuKqzOrH3AFTa- zFY+E{6XH9XKG%Uz? z5Wstuv7Q02Oi1FPE(``d--)en4k{T9f6%FY#3_;HN*zhyMVFm`AwAAy`i|Haqh2T9 zsZo}T$*u7YFj7n!Nv3?9P4$3UOfsc$GVZ?r9PMSita>}s#o z3eT+-*JWI7o817Mks|AHc)szEZfrConUZ9A7_8R$7MVz^E#HBrI@?IU)Bz@ENmG8 z$xUw_{TzMvCCBp&hcQTPv~!fe>7pmEtAW6#quQ-H>H|LQ7e42zi*Mslo_<*>Pjm-R z!Cd7g>(b$YkMp?iwcpqymKS8AI&yvlCPIWnlnMEj@b~=tm!lA)(m=phOv3haU3$bX zIC_oLnqmeVG^CVB^kX^RRxQD)w4_hlk`w;QGLw%qhnQY3`Cx&|2Xn?J7R<7o3fm|D z`n7uZwX1wcYy!%TKJZOxS}kgkflZ}dn5myt>35{xgY|^Ru{BNV^`-?`4?4Z)orplR z52oM=s2p1vpU_W20U**BCTtR8-Vn&a9n^%)x)KchlB%t^;5s{{_aDHOHn35*sfI|H zIh2}7nC#t$i^z;DOMH+v*MRDI1m;2wM#E$g za>D)k0h`{7x)k1~eUv|7<*F$sU1rduHA&Lh{)*Ug zq+#PzjGXGFw>X^S(@I`w|K0JPy-ovXH6m_z{>JD)BH zT5?cz@E7!MMe0noP_7%$ zM|lb4@-n~pi-iC|HAO`_6EH0>9&!E;;PrFMSmn7@i7@^g<-t^0pdBD$onCuee_4PP znO(h6)Ez^!d753(hxYIYdwxEEU=b!PlnqRB@)+ZCSLHb$+mdlc&;Ti(HXbF?sAF72 z!Fq~{?+*mNZ&N3kYy+yez@Nqrv?o0s5Y`PP-C{ilJhnVf>DpiIE%P^c@j;ofOje>S zYLSNFqYw$sM!8({VH6WB+oNl{fQH>-1s+7?7?+URQO4uG7^`^hgLuV-<5mAOme53S zZN~8)^K3hBJ{9>ME3i>pZ~WO8zqoIih-)?lR>X{cA-$`;HvOw-`9}Xw0QoBh)c&0z z$izC75PT<>na0sghZDE`+*YwX2PK5;a%!<5kYGX(i0gSyuU7#|Vk?{yRwu{+1c&Du zoDJB;sz8vPwH#!z6e1BaFIkl0%#Ict5wdrXGKG;O4~&iodvkQc-tFQ*bi_+|(tbe) z0wSg(UHjpo>1RQTJkr-pQvwn>0vjxr>sVnSG>p-wg*U($yn4p zPOlkF7S_dB7j_* z?~9PajI8y7`1Zgslp==;lWQ1!pfb%(-ro9f#K#Uh;uZh`1$cKU-#)oh7Qg~|S8rTg zF`Wz8aB3(A!T$hd^rfSq5J4)Cvsnv#bA%dm27L6#2ob1A1idG0ikvBf5Hk!W^=>lT z06-v;bWop$Y{vw9uzy}-oLTSy+OV{W0{CHeG$CV@eOyA_XGQm5!66k(t@ikD1PCbv z&}h_SGdA?V%^^>U-ti^EMo>hlMIIpUh3Z)XCVM`;^6m;0Ny{4x`(t}zFo=z}JM`xc zD2=R6HRWM3Iw~syr)d+XX6LpemJA?CQIJtgV5MqTJ@MB%CxPb(7=#89IV%~_m`Lj; z4OD~kF*6>I$9U#;q3%AICXe-aJS{UGtW{m}@$HI7YG>is5Q%Y5QS`wr_gN(G9+poZ zGw_BejoSvaqX8UJu|8M?ERbM%cxyU|I;oJ=SyhsSo#v2K=&10{K;$-vTCRC^&2fg& zTT4B{tK*Z2WdRAoEm4_u4-1UC~ysNalo znKY5|aHy22z%Pz+vQb;e5Zw`p0D(aS>R7Y2U{myL0Z3iR@?fJ<5ti~(<$@q2q=H8+ z@V>K~y}v*EASzDQno~+}y2+WXHQ`UooTb^AsA#}MinUrS%(Dji9Wa{kEVVx8XYmF> zkYpJKQXk00G{j(r@>Je2kTfrIB+|7;w4?K!Xrge=l|6C}O(q0Ofnxn3tV}^CkPsqt z@b{cSKmydyOp*K$H4~%GDH7l+ES+^xizKG0IH06c88E>`xJw*N;ZROU=%VI0{{S)V zCLz>Y^QId%L}d(c{#GfG1-D5n6V%c@sezw@R7%;--Q!5FG-hHqykg`t(RC(Bg^Ucs2K8^4$LKAjPTdOP z=OqPFLo%wxHoWp;%0prm5j`U!EyfU|%W{12F>DoM6_z`%Obe}9VG=?g41aP!md{$p z6&NTIX_!Esk69}O_*96fw$8*+(lMD42VDOXwsJXZ30+BDt{CO5`7apHnZOq_9tB1sg{haR}8O!nAzCo>+H z%FH2yPddd=15rvo%=XP0^(;=e+XBk5A?0Tgf;xO;kr2Hezbqz5ODzdz>(s}d1TW7Z z1$0n4oV_OzVo)Ny6mK-aZ~z?$50(%Hh?F7mkRUA#AgU&d5u63Y2{kq?taw=%I8!>B^X(W+ zT4?h$udX4$stD}K`RkLY=mPdK@8RalI&>#*wn2FFiHX8n{H&CK8eMN$bLei&1UmJ@ zqC*p4z{J)u3ZykDAt(~{!Ub@GfDs9B z6e4VKiV_@LL#p(N`7#(00^|gWfm1UJh=G>KpfpJbSF;;YIt0w70I=?3XE_m!6O=o3 zFH9`{bR@|<2RIV?f-I&k`qphrNSIC@{{ZnT1p(x7fcB8HDHNSDbYpS@wUID{;al(M!v86Ut6 zcQB_AF&R=gqG7#`w_Wgr4N?~Fee-htVKht9^5C@TKAAJg;$e7wu~H+TxoC1Gv314} z3o$+5-ZyVhOpx<96nxscM4!(12xP+KcV00GHjNqa#w3JN?7ui*@L2{3kp|{{@+P4Y z2u7!Bq#VN-q|^{?Fu>clOpD|$!NP0v*I4HPXPD~!kMoh@i5qO6gC*l$-?l_z2|^~R z)x1k#qC^v8+{ym{zz{?ijpRX~gop@u-b_LY$?mT?IzF=UWnV)phH$=EtOv2f5|IdD zh}BH{Jmks%1@Rs5+=D?9+t(=3s~L8V^!>QhzSZd(p8o(%U?u?-*e-ft3M5HQ;U}>* zuuk|gJC#W+(U3|EY!j%Sm5skF%!gNptoO#q<4ud|&((AF-2Hb9nt;2Gs8)pa$rweN zWPxf8qHITZ?A8S6m*H5hUZzZ71Uwz7aG9LE=f_pL|7( zaR;P{G3|$Fk}`<*zHl>YMiCs(PBKamC1IIQ#~DV7rYCafiR*b2LM%Dvow6$70y-1O z9QnkWg;2zxV$BPUWG8k>xvn*tj?IVRV7^}r3y{#b!hnWv@Wx63x7 z>XnF+d|!-&fW*L=@@d1gOeu4x)ANnuZi#^Aqlw0@%?~TSAkc(PQo`+qPK@c~$Z0Yj z<1ba?i^6MC{Mi~p!*VPo)>Tjm2gt(_fC~%)@pJ30as#MX5c-&DJn?}EBsDhp#O-VX zOPhT#v*gP#K|N=`d>$Iu{O1^jAdkh)P)cYash+q*!Ih`2m-Fd`3kaDSr1r=XW=If+ zAsAz*c_ZH@iW4XaDP`&Q#1)dUvfiI&Ihr-spXf`w!bj1~K*lNK(-#!1%8Qtvk?oNK zup+%zu4*?KA19pR%7iDcoF+(t6cUHi{?U0dIdl*b5Y6=R;9?C0Om&QilM7EwFrP~b z%9M^&b-^?qsM0G!O=Am%a4b$BLLvyBU2qc6$b{KPmtMG>qe2X#q!nx8B3v6UTolI# z7*bTgWXvrZDe>!3F$nAeJ`am{sFQ-JqS}CW!-mR4)CAcN9We@%I-6oTbjo<9fhZfO z9Xe+41zrIpvD(MGjuL{RbW+M0>xp+LBUB*_#;1Mz;UJJ#9aR!#iJ_g$A1nyr6ckzjjrYc2EeymZY2r!rsms|w1;dyz zWq@HP5ZXXzrd)*pSh{=HTFPoby6Ka(2qIt?2AYpvOao_D5JVp41(PU|TV%bra`0uX zCdQDTh-4-W9u$r14Lt;V;+n43s3FGCZv_h>t?FyWQ2RcA_8f7c>9F~hJY{8BmKkMD z0T+g-*gz{VlrJ56;_$iliHgt>msobDs+B^WOie^lgnssZ5%tf)KDqcu*FOmQ;87y| zuQ?$E0T#*A01?}HF&53@NN;0+`y9QX+R&ti#%^pfU~JmP=R|bY@4iMwTxFDf3iRg~ zlaRsEN$z7o(Vc})WDCHQD-AX7=rB)JZ~fb%0eD!M0x-KA|aE!o3vJdBC|ZZBEK)9yM-I*q1EZ5<#T1si?TM428KZ=Y zHOE-*iX_<>w#5h|jA|iSqZq42h8ypXYGjo%Yp13H3lP!6EE0l>SOZ1lI&jXL>#su$ zgNYeYXCO}+Llju}21otC4Px?99n1t%T(b!waYcJrzzD#*Mh&bzA4j;aJoAyF)Ca`F5d;AZ_Wo9)V1#ht z++a5*GRqgL+w{QNm^1{0>YSNeNJ3OT;;z^XQh{U_anQ*bS@6%%^YncEA3sOW(eOBI zKvM7zG=P$)N2WnUK!6l^!^Tvg(PLe=i$oQmmRNZ%IN6ep1f>GmuGm343{8T>&A%@A z41$6HL9U}$#y;{e7HwO%za246ut5%@Z_Xh^K~^0^-FLr+XaQWXOa&!JTJ3;vDN35R z5L|k`JEb$Exo;I~Izcdzlt z&`F>+L#f0~+WFurCVt$7Ks3tQhigyQ1dts|WKO$Z(-UxF6rL=zoVMVl1pqg;I{g?_ zeJgLo{&>a#I8!z(N}G7$#$cMn*ABjnk|J}iyjHrK=)kEKgp6&FsOi@aPKX(pC6v3k z#zEDAEfwe5V;K^F%8b5aAXW%u*{3CiF+@fZ#c0vUWbHo1hyXZ|1fH#8s0$3vVBf4` z1lj>Lpd zOe^F8v;mQj0wq!DbckrAdHXvmKj16li$qEklyK#rMS|Bb7sILg4W)uw|O9t)7 zJuz5{9Mk|?^NEdIxe#g9_RE4mQ9S(&DhSC5u-w~tIT4asQyJ3PYyd`RD~vLLN6Qc` zkRfdBBpigpAg8%=zs=$ixDX7=d*UsT3ZijGrMoXULK7;1su@_Vcg3v3WJ#2qS3v>} z1^D3zLV+R}XVo8$vB!o82$vlT_Pu2V*g^?6z46-^aL$9@G)cv4pGPo5iG!g=M9(o^x(% zn6P0}!6b#>&mdTRkvIkf0)Z)!4vvSXoJRPN)e%FiLlB{pV30_y!2UQAEr2)nWWt^x zS$tL%wYBU^m^wLqg+#QKJU?r^CCZ~oml!r?CUP0z31C1T!k1ih>@2B!(Rm0KC6sM9 z)BMgmGY7r~E5$J`Z`e6O)qyCD0aPAtR;XvO#c0R~+lwUNBRnNzpns`tN*W ziZTbIuAe+_640s|P8KHWHtH64gKsg!)ZK6Fg!-X-IGNisa-NjP5rpIdpEVG2MhdZ7unacJyQkMEKv1)G*G!*; zq6X)t078KU)Xz9J!I?mU5pSFj0#ejL6sdG^x$BIJra^>ibnSyvJ`lzTy!}{FlnmM_ ze|y6UyI2)dTz;^!PrE~YF>-?~6yPM(=&X?lgHU)0U_IIGhc*$>tfd^x*gQrR(xq2N zGR73{Q-F=K8r~LJVkxNV(8tFFg-$8&Mn#R7Of42wiKos@ut2b7Zz$FX2R&VF_j95a z5WwnUdl`Hpq>JAeVL%4P)-njDVsatL>x_4naiTD0_JDZ_DJT#FSYveH{# zyz3a*iVF8-YW_I#wzL8cjnsN&?G8z)%XZlLnFXx|QKcEGl04B$ILK66s4-OmZYmzqlU*g*go#2cMBJt01cd`+6Qs{m85)s+%`0k_uxw3mtrnea zFxjQxz45FHUKyQ2b0*Ts$y%i&Z#^+Yr%FWoSI-b+ra+a_&fYQfoo&^IXlN*?9=M4- zv4=tq_*sUA8AHNr>y2b~j}DV_fQsDC2GYnLGD>5e!p_1`Yr%$+N%sVRc~>CKAzFd{d4g@u6`%=&&2+@_@CE56Z+@ke_Z^}>yTH3U`>fF7;t0(Bn0aBJoa%E z`0oIz6Yj4#&Jf#DlS3;J=Oa6qK+{m?vT_d1;|O;12hoOU>>4K3Q7}h*ppp|HFs0CZ zW1L0G$N(p9avBJzCU$qOHr_&TikSs%aq!8-F}S^=i!smxp~N~wU8Y@dV2qV>w?6m? zy+rlBtEZ+Fkh7+vQ6965EkYyPa~J;LhHz9}c2#lhfMO=txD^rWJ@M-$m!qv;Cm0nwgRhGO>;s$xtbZC8U+#4ggt@Vl48mm@1-Nq{IswUi#*R z^7VS*fvs>$j&?wRn~l4Q#bwzBq|(bLc)>tbA(*Cwbm-t)Nje}1mV2|(up=X09aA z;_!Puke8=^nOqPg4W~t7K;(567^j`i1}-OVhAh-3J*hh(aVGT#cE!AT7pU5z7U`ETC!Lv9eXL1XCRw-)@;2TuPly zUx&{Qxow9B!aVlKbczK^3Ee5K*bSjrgrSr#-yEc(MXFet`S#7Ord`O1U7RD6D>Xoh zbhKV3mwDwQPdBVM76Jm-6CAh{WYQC1^zVWY3@RGI7f=vlLWmI>G0uWCmY8 ze0!MiK$1gI+O?tp&5n5p6paA{$q5)z_{q0QWRr*aTp;8g0L5hOcfY+ zc@Kn*;nSS)!2yVbn0#_ZUl4%8yawI1kf2h~7ww<8=k7WCj(+2xxaaOTK*uCa+pa~3 zVdyvyyMRs9D=V277CCHV5u}3x(?;8+gCjIHVu%Jd?)!Jhu8VAlZC)p~S;CMhJILR! zt|1IwOE`}hs~Kcg=ss8Q$J;_HjI_ttlYVc7^OGcIK`As|rU}GCwVndTZQXXpRrW;g zF|G_Z;TX_|y8-revUFoW3#{Nwor8Fd45aV4#l#f0Qt+N3Nu_H9BCj};>^fi(NHejC znwjSGnaUUd@T(DrDCU!vu%G~gCbJ@#?C;kqt|*~-7UcRk;*g2@?W`JFS=SBK)(GH- zg#Q3tJuutILXMvL^u;=h5*XX?8vK8X{t~i5Ce#rR(1in#$UXe!iIL zf`Kzi;JxXdBL>$D5jk=LuJgt%W4wy**M1}Z+;`XQG4GBB3qZ7xY{z**vP)@o6eQDv zrc=wfiH%HDmmno$2R+%al^Hk*mJU^xRB90Qnx7fB+8DiQP0n2-VOAb@yaPCc zpqAIuhdA((ky6BYtUwGUT*kS_5P=k?evBh?)``J@AQEIh+XVw*M&HqaB(#~1*I0{+ zSqi+(?8QQ265hr0iQE1yQVXiEhW#=W2vV??N9+Q$nh*(ow zz;F;3e=j*O8Kff5Ue9td0uIj-^XoWZa=^%To`3kif$RSOmoJX~r{Ma3;FjNpkLmeN zpWXQ0toT36{{WNt9>4i=`0wg|52yYKZTM*ZpOoqS-;L_egZ#hwKY{E20GBV0{-@yj zf8dtihL7p_PM_WQ-mLgP%l`n96${tYp!oj)QZxV~)c&w}EjLMl{eK73{T9R=r)h7Q z{WknGe?p=*t&n}ctAlnB!^~kaSVBySJhEgcqAD%X>4S_@V12!R_{a_~IAYI);A$YH zETVSTLe7|s`tndno14B&9wd?w2Ra=j3lp~{un5ewz^_(HQEXO8U{I2#%92ZuRh3;A zG239zi)R3D$T1{>5g~($Fut`YBWc6@S5!y8t z07QZ!VHT=+$Hws$1+pPW4P$u|Hsp~Kw)auqGjGF3@Q+l2C?up3Nse+z+&QI4CQR2Z z$w;zY39?OMh;U|$Z0?5WR}qm20hthQFmwS#^@I3A;!r0zorvfJI6UN?CuA9EwjTYm zJu0%Q3Q0jVvG)pC*-Q|N!1Egi{{UPgqzrFb{{TjVrCxWx=n;_<@{i_f6V@;P0KHhT zNFq#fsHG}!2-GIP7q%ei&bSQGD-Oy!pqB{4G;C6NB;z#D#%4%J6&%}zgCMaS2rV$? zu1O?7=#7rDe<{Qm3m}<;herfQPh=81$&euwB^g3uK?;H|OpXnuMPU|ZtzeG$RUk8i z+Iar}@3ukMlPOA_k-Pvqy}XW%Gdm&;$qn0LWeC*a3@mG^2^*1&B*Cn0R)gpz(oIHLO4w*;!+{PbdTX#bf`kc-eXTVih^M=m{e$i5;ZB3Z9j8?paLaN&ng*`V=}>{ z(Yku#F{0Ej2BlG^>%a2p!(iNCNSJaG!-ZH`VKB^b0EXr;+DHgVl}`l~AKgx*1GU#F z=v>((e8XHOr&BedUlG%zh%N|(O(4{sr}lV-ZX`j6Djeg*&1CWVh%>yZL7Y4ku_sPEefPerC zLQSpz0PG>TPZs?#s~hBhFaQ~VB;!UIK)x9#Xhbr}a`T+XU+sTEK)xL_vnZ;aCj=rYi8Cg8;Gly5 z0uI<5t3d(%7MTo?*78qcD?{HuS?hoZ0P+1SjIofsGTEWDIMSFL}`I8Jc6cZ{4#?B3Cc6r7gsH(ftG`ZnS zKm^jwiI4pso#_7nZ;bx;<$53T_=nB^0FT7~0CV#lf4Adz{!v09XT{0X^uD=oLC8xI zp*Cv)JfYP~$vd2>2|$bo)x`)Is=y$({{S+9Ef|qgfnl>nB7Jf|R9g^f$B6pp^8WyA zW^ceQ3|M4U6A)M6*lFe)C3dzrERv4au_^PjfQ-C)@Vcd?(k&)gW~>jchi z6!@EcV899`n02rRGot?hk6aGF zH`fAJ=KAEiPs6S+i_hQ0ZTVq6VyuW(7xh#9zcJVQem8&V`F^bYS5N&28X+TanC*cL z!4^1rXXko9%H6_93|3JnN<{2Ld~YXKLE`@a3}I?LitxWB_{I%wO!>+J97CbOWG2S| zS(_v4lo7~8EqiLyAQ!F)yV2*a~8zCInm6g=`Y3-N8PK#d1p11e^?Ul!*h|{ltF5_s`Zp zd^f^L4>|dczuWP<;)dK$Ve5sHpO@;-#dQAw(4+(a_9qP8ixvnb@sBxM#3%14YebPkdUC7asHJJCOKg8XBl-C@Sy3;k%|K z+R}f0@WULtY5$heX&tkCDBxDS*H-tGLe1vg#KJGlH_PUI3>5?l zm=Q>N*&f(eX%iHs=6)_e7L_RU=K7P&|JDWs{u6K-R^$Y2N zwXKDh=By3RCu19=my^l^~^D34Yo zkTDRwv1$Pzw4@3dHPg;+@%S>N@raG0Mk5r(of3d0E=G0P$|T=-{)Qz$P>Spvi|E!2q^&mP`;<59v^A2QNBDb<-Gam&9{eR%Rsh zaut(IU}RASz?I`Q;>Wg60%Rk&c*jU+%!^9BRh(>u7%uJ^5C#H(m!o(w2396x#N+FM z3uQi7Ikh)T2OQ*m63Det=3`k+a<}wnzAIeH5C&tL)+X5%Fe*2aV+dgWOqlZ&9yPLfVdY~U1f#!r_hA2=vU za=Dt4Ujp9P{KGM1BOC{4#-9lcj)dfI1}Ugg5z~nx31o7P&s-QNV?cLq)-+v-N#442UkJK!Ke89GwhzYIt=a1BthIPH|dqF3o99xkz~5F!SPfIfII zm_S$Dj+q|0g+kGxo@V=D0gWT0k=?0)!(9?d@Zq`wo+K#$7ro8Tv*`{wnX66My|0i3?zzz9_{gv2a( z#H8jnXV2NdoxhJv{CDYq{jawGB5zEAjt<#fIY9Dc7vBB_6vCzg!sQqPMriH(X8C%4 z*f1(PKG+D8&gu5e3wp!tfI;eioL0$xI%d9&ehk_>&*m{*{(hLTe&-e;UtR+P%{)Fm zLyCZDDVHcq$n&}UXSspKbddF23`wVzV$(K$8_vtP-=23G;{5Yc{eJdBAsPHPfU*Si Z`}z33=4j8$zB)CC{G0?}AV2)4|Jj!CUN-;$ literal 0 HcmV?d00001 diff --git a/Documentation/mainboard/libretrend/lt1000.md b/Documentation/mainboard/libretrend/lt1000.md new file mode 100644 index 0000000000..78d5fc056c --- /dev/null +++ b/Documentation/mainboard/libretrend/lt1000.md @@ -0,0 +1,117 @@ +# Libretrend LT1000 + +This page describes how to run coreboot on the [Libretrend LT1000] (aka +Librebox). + +![](lt1000.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done +automatically by coreboot build system and included into the image) from the +*3rdparty/fsp* submodule. + +Microcode updates are automatically included into the coreboot image by build +system from the *3rdparty/intel-microcode* submodule. + +The mainboard code also contains a VBT file (version 1.00, BDB version 2.09) +which is automatically included into the image by coreboot build system. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. It is strongly advised to +flash only the BIOS region if not having an external programmer, see known +issues. + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located on the top middle side of the board near the CPU fan, +between the DIMM slots and the M.2 disk. Use a clip (or solder the wires) to +program the chip. Specifically, it's a Winbond W25Q64FV (3.3V) - +[datasheet][W25Q64FV]. + +## Known issues + +- Fastboot (MRC cache) is not working reliably (missing schematics for CPU to + DIMM wiring). +- Flashing ME region with already cleaned ME firmware may lead to platform not + booting, flashing full ME firmware is needed to recover. +- In order to have the USB device wake support from S3 state using the front + USB 3.0 ports, one has to move the jumper on DUSB1_PWR_SET header (it will + switch the power rails for the USB 3.0 ports). +- There are 6 unknown GPIO pins on the board. + +## Untested + +Not all mainboard's peripherals and functions were tested because of lack of +the cables or not being populated on the board case. + +- LVDS header +- Onboard USB 2.0 and USB 3.0 headers +- Speakers and mic header +- SPDIF header +- Audio header +- PS/2 header +- LPT header +- CIR (infrared header) +- COM2 port RS485 mode (RS232/RS485 mode is controlled via jumper) +- SYS_FAN header + +## Working + +- USB +- Ethernet +- Integrated graphics (with libgfxinit) on VGA and HDMI ports +- flashrom +- PCIe +- NVMe +- WiFi and Bluetooth +- SATA +- Serial ports 1-6 +- SMBus +- HDA (verbs not implemented yet, but works under GNU/Linux (4.15 tested)) +- Initialization with KBL FSP 2.0 +- SeaBIOS payload (version rel-1.13.0) +- TPM2 ([custom module] connected to LPC DEBUG header) +- Automatic fan control +- Platform boots with cleaned ME (MFS partition must be left on SPI flash) + +## Technology + +The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not +sold yet). More details on [baseboard site]. Unfortunately the board manual is +not publicly available. + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i7-6500U | ++------------------+--------------------------------------------------+ +| PCH | Skylake-U Premium | ++------------------+--------------------------------------------------+ +| Super I/O | ITE IT8786E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[Libretrend LT1000]: https://libretrend.com/specs/librebox/ +[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom +[baseboard site]: http://www.minicase.net/product_LR-i7S65T1.html +[custom module]: https://shop.3mdeb.com/product/tpm2-module-for-librebox/ diff --git a/MAINTAINERS b/MAINTAINERS index a79d98f01c..3a31847c9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -317,6 +317,12 @@ M: Vlado Cibic S: Maintained F: src/mainboard/asus/p8z77-m_pro/ +LIBRETREND LT1000 MAINBOARD +M: Piotr Król +M: Michał Żygowski +S: Maintained +F: src/mainboard/libretrend/lt1000 + PC ENGINES ALL MAINBOARDS M: Piotr Król M: Michał Żygowski diff --git a/configs/config.libretrend_lt1000 b/configs/config.libretrend_lt1000 new file mode 100644 index 0000000000..f12ae3f81c --- /dev/null +++ b/configs/config.libretrend_lt1000 @@ -0,0 +1,5 @@ +CONFIG_VENDOR_LIBRETREND=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_USER_TPM2=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y diff --git a/src/mainboard/libretrend/Kconfig b/src/mainboard/libretrend/Kconfig new file mode 100644 index 0000000000..7e1eacdd71 --- /dev/null +++ b/src/mainboard/libretrend/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LIBRETREND + +choice + prompt "Mainboard model" + +source "src/mainboard/libretrend/*/Kconfig.name" + +endchoice + +source "src/mainboard/libretrend/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Libretrend" + +endif # VENDOR_LIBRETREND diff --git a/src/mainboard/libretrend/Kconfig.name b/src/mainboard/libretrend/Kconfig.name new file mode 100644 index 0000000000..cd272b0a31 --- /dev/null +++ b/src/mainboard/libretrend/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LIBRETREND + bool "Libretrend" diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig new file mode 100644 index 0000000000..b4a4e49ef7 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -0,0 +1,55 @@ +if BOARD_LIBRETREND_LT1000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_SKYLAKE + select SPD_READ_BY_WORD + select SUPERIO_ITE_IT8786E + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_PART_NUMBER + string + default "LT1000" + +config MAINBOARD_DIR + string + default "libretrend/lt1000" + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,1916" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CBFS_SIZE + hex + default 0x600000 + +config ADD_FSP_BINARIES + bool + default y + +config FSP_USE_REPO + bool + default y + +endif diff --git a/src/mainboard/libretrend/lt1000/Kconfig.name b/src/mainboard/libretrend/lt1000/Kconfig.name new file mode 100644 index 0000000000..26e5255f05 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LIBRETREND_LT1000 + bool "LT1000" diff --git a/src/mainboard/libretrend/lt1000/Makefile.inc b/src/mainboard/libretrend/lt1000/Makefile.inc new file mode 100644 index 0000000000..cab4a5e194 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This file is part of the coreboot project. + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/libretrend/lt1000/acpi/ec.asl b/src/mainboard/libretrend/lt1000/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/libretrend/lt1000/acpi/superio.asl b/src/mainboard/libretrend/lt1000/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/libretrend/lt1000/board_info.txt b/src/mainboard/libretrend/lt1000/board_info.txt new file mode 100644 index 0000000000..2d7c8933e3 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Libretrend +Board name: LT1000 +Category: desktop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2018 diff --git a/src/mainboard/libretrend/lt1000/bootblock.c b/src/mainboard/libretrend/lt1000/bootblock.c new file mode 100644 index 0000000000..bc85deca9b --- /dev/null +++ b/src/mainboard/libretrend/lt1000/bootblock.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO) +#define SERIAL1_DEV PNP_DEV(0x2e, IT8786E_SP1) +#define SERIAL3_DEV PNP_DEV(0x2e, IT8786E_SP3) +#define SERIAL4_DEV PNP_DEV(0x2e, IT8786E_SP4) +#define SERIAL5_DEV PNP_DEV(0x2e, IT8786E_SP5) +#define SERIAL6_DEV PNP_DEV(0x2e, IT8786E_SP6) + +void bootblock_mainboard_early_init(void) +{ + ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_3vsbsw(GPIO_DEV); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); + + /* + * FIXME: + * IT8786E has 6 COM ports, COM1/3/5 have default IO base 0x3f8 and + * COM2/4/6 have 0x2f8. When enabling devices before setting resources + * from devicetree, the output on debugging COM1 becomes very slow due + * to the same IO bases for multiple COM ports. For now set different + * hardcoded IO bases for COM3/4/5/6 ports, they will be set later to + * desired values from devicetree. They can be also turned off. + */ + ite_enable_serial(SERIAL3_DEV, 0x3e8); + ite_enable_serial(SERIAL4_DEV, 0x2e8); + ite_enable_serial(SERIAL5_DEV, 0x2f0); + ite_enable_serial(SERIAL6_DEV, 0x2e0); +} diff --git a/src/mainboard/libretrend/lt1000/data.vbt b/src/mainboard/libretrend/lt1000/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..cb4a2f4a6cf0e67a08f098ec8478cf27df187f20 GIT binary patch literal 4608 zcmeHKU2GIp6h1SvKeKmcw$mxfvS2+TmTiG{wm^kiWwyJ8F5S}IZmA`ju!UW;aiOIx zrufGiOG08W`=AC5(I!4<>Pr*jlQHsQBq1t3h`z~-i4sjr#P|Y?XMWlW4ef>m6~mc5 z_uPBt&Nt_rd+wdHYx>*!Fx#~!73=Cim-3*)_iBvVh18zx$?i?W`eJ+AQ$6u6{08oY z_tk5c0P-BSLXPTsGl4}6Ko2*hxZK?3r&f_*fZn9BbbgSF}8nyp;#Cl953WC z+rJ}*7N)}5j|>&_xa-KleTC6hBp{t;V{}vF#!ZOPre^x-(aqG=Tca(lo3|<~(Glh0$jV`9_6VAZI}IZ~&Yastn-ZYBP`mL<2+wQ3a0y z9t4jH27;jisvrV*01N;GP%R@=;5TzT>FPxAg)Gf15xijc4QsMX=z$A4P*w2~Az9=H z@Y)@fL$bsnG~8KN+*!_R=_Yc>yORLX>Je5jFsquC96GP2F&RyylJ$$untk%0lLEPW zoy0RMF2rghXa9H*datT2GztXi60_vBHl_IC+;SGoOqDfcLc7Oe92k@q7vuIYDa?Vf!FGxblTOQcJ+bZ zXt9ZyDb* zdAe?2%gzBMvO}hMr}yL<*hw2$5ZfkK*}m)sFyB=Km;hGo?lsbD@@!Jtla{>$zOduE zzs->g+kf*;*vf#Fzwqb%49@#6b0=#4n>{OP>Jpa|+4)p+#&_Gh5x71At2*IApj5_- z_o-rTwR5lb)-?A&Njb@jbTAlz)RmzVA`pTEtbt{agS1^YiS{{roe`C(5TVN2po>r> zOyFY+CQK6n)V~hGBMb+bHpbYC4Bung$Bcc(@JFWo$rvZ$T1nd~vABdolJ>mBj!XEV zqd{<4-!Jd{92Ul zIz^uHPF9c)Z`V(q&rGh?({C-GLl8i6BUuT8-e8=~P3HAb#;FH^ybvfIiEcF~Z3M+Z z@L~mCTnfWf8kg&`9=DzX+lDgjN3x;h-(u&3mEiR wZy^2#T7M6m+)idDsdC>$gvJ?w6LWM&bT=;e&$@W{@7@LY3pRec9{>OV literal 0 HcmV?d00001 diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb new file mode 100644 index 0000000000..f54b877f18 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -0,0 +1,298 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Set the Thermal Control Circuit (TCC) activation value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f + register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef + register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff + register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------------+-------+ + #| Domain/Setting | SA | IA | GT-Unsliced | GT | + #+----------------+-------+-------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" + register "PcieRpClkSrcNumber[9]" = "3" + register "PcieRpClkSrcNumber[10]" = "3" + register "PcieRpClkSrcNumber[11]" = "3" + + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" + end + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "SSD_M.2 2242/2280" "SlotDataBusWidth4X" + end + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip superio/ite/it8786e + register "TMPIN1.mode" = "THERMAL_PECI" + register "TMPIN1.offset" = "100" + register "TMPIN1.min" = "128" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN2.min" = "128" + register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" + register "ec.vin_mask" = "VIN_ALL" + # FAN1 is CPU fan (on board) + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = " 1" + register "FAN1.smart.tmp_off" = "35" + register "FAN1.smart.tmp_start" = "60" + register "FAN1.smart.tmp_full" = "85" + register "FAN1.smart.tmp_delta" = " 2" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "24" + # FAN2 is system fan (4 pin connector populated) + #register "FAN2.mode" = "FAN_MODE_OFF" + # FAN3 PWM is used for LVDS backlight control + #register "FAN3.mode" = "FAN_MODE_OFF" + + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Printer Port + io 0x60 = 0x378 + io 0x62 = 0x778 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa40 + io 0x62 = 0xa30 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO + end + device pnp 2e.8 on # COM 3 + io 0x60 = 0x3e8 + irq 0x70 = 3 + end + device pnp 2e.9 on # COM 4 + io 0x60 = 0x2e8 + irq 0x70 = 4 + end + device pnp 2e.a off end # CIR + device pnp 2e.b on # COM 5 + io 0x60 = 0x2f0 + irq 0x70 = 3 + end + device pnp 2e.c on # COM 6 + io 0x60 = 0x2e0 + irq 0x70 = 4 + end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl new file mode 100644 index 0000000000..624806ca04 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } + + #include +} diff --git a/src/mainboard/libretrend/lt1000/gma-mainboard.ads b/src/mainboard/libretrend/lt1000/gma-mainboard.ads new file mode 100644 index 0000000000..210ea288b8 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/libretrend/lt1000/gpio.h b/src/mainboard/libretrend/lt1000/gpio.h new file mode 100644 index 0000000000..d937ae5945 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/gpio.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef LT1000_GPIO_H +#define LT1000_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* PME# */ PAD_CFG_NC(GPP_A11), +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP), +/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP), +/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* VRALERT# */ PAD_CFG_NC(GPP_B2), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), +/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), +/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP), +/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */ +/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NC(GPP_C12), +/* UART1_TXD */ PAD_CFG_NC(GPP_C13), +/* UART1_RTS# */ PAD_CFG_NC(GPP_C14), +/* UART1_CTS# */ PAD_CFG_NC(GPP_C15), +/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP), +/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP), +/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NC(GPP_C20), +/* UART2_TXD */ PAD_CFG_NC(GPP_C21), +/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), +/* UART2_CTS# */ PAD_CFG_NC(GPP_C23), + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), +/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), +/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), +/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), +/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP), +/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), +/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), + +/* SATAXPCI0 */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), +/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), + +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* I2C5_SDA */ PAD_CFG_NC(GPP_F10), +/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), +/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), +/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), +/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), +/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), +/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), +/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), +/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), +/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), +/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), +/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), + +/* BATLOW# */ PAD_CFG_NC(GPD0), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), +/* LAN_WAKE# */ PAD_CFG_NC(GPD2), +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +#endif + +#endif diff --git a/src/mainboard/libretrend/lt1000/ramstage.c b/src/mainboard/libretrend/lt1000/ramstage.c new file mode 100644 index 0000000000..e9eb80afa2 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* + * Configure pads prior to SiliconInit() in case there are any + * dependencies during hardware initialization. + */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/libretrend/lt1000/romstage.c b/src/mainboard/libretrend/lt1000/romstage.c new file mode 100644 index 0000000000..510038b3b7 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/romstage.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} From 8fb7cd4123a1e60b88b65ebb8e330835adae71e2 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Sat, 7 Mar 2020 13:55:33 +0800 Subject: [PATCH 0360/1463] lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/lib/spd_bin.c | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 84e2123b98..35bcb4c2c7 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -30,9 +30,22 @@ void dump_spd_info(struct spd_block *blk) } } -static bool is_memory_type_ddr4(int dram_type) +static bool use_ddr4_params(int dram_type) { - return (dram_type == SPD_DRAM_DDR4); + switch (dram_type) { + case SPD_DRAM_DDR3: + case SPD_DRAM_LPDDR3_INTEL: + return false; + /* LPDDR3, LPDDR4 and DDR4 share the same attributes */ + case SPD_DRAM_LPDDR3_JEDEC: + case SPD_DRAM_DDR4: + case SPD_DRAM_LPDDR4: + return true; + default: + printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n", + dram_type, __func__); + return true; + } } static const char *spd_get_module_type_string(int dram_type) @@ -57,14 +70,14 @@ static int spd_get_banks(const uint8_t spd[], int dram_type) static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; switch (dram_type) { - /* DDR3 and LPDDR3 have the same bank definition */ + /* DDR3 and LPDDR3_Intel have the same bank definition */ case SPD_DRAM_DDR3: case SPD_DRAM_LPDDR3_INTEL: - case SPD_DRAM_LPDDR3_JEDEC: if (index >= ARRAY_SIZE(ddr3_banks)) return -1; return ddr3_banks[index]; - /* DDR4 and LPDDR4 has the same bank definition */ + /* LPDDR3, LPDDR4 and DDR4 have the same bank definition */ + case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: if (index >= ARRAY_SIZE(ddr4_banks)) @@ -106,8 +119,8 @@ static int spd_get_cols(const uint8_t spd[]) static int spd_get_ranks(const uint8_t spd[], int dram_type) { static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; - int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION - : DDR3_ORGANIZATION; + int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION + : DDR3_ORGANIZATION; int index = (spd[organ_offset] >> 3) & 7; if (index >= ARRAY_SIZE(spd_ranks)) return -1; @@ -117,8 +130,8 @@ static int spd_get_ranks(const uint8_t spd[], int dram_type) static int spd_get_devw(const uint8_t spd[], int dram_type) { static const int spd_devw[4] = { 4, 8, 16, 32 }; - int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION - : DDR3_ORGANIZATION; + int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION + : DDR3_ORGANIZATION; int index = spd[organ_offset] & 7; if (index >= ARRAY_SIZE(spd_devw)) return -1; @@ -128,8 +141,8 @@ static int spd_get_devw(const uint8_t spd[], int dram_type) static int spd_get_busw(const uint8_t spd[], int dram_type) { static const int spd_busw[4] = { 8, 16, 32, 64 }; - int busw_offset = is_memory_type_ddr4(dram_type) ? DDR4_BUS_DEV_WIDTH - : DDR3_BUS_DEV_WIDTH; + int busw_offset = use_ddr4_params(dram_type) ? DDR4_BUS_DEV_WIDTH + : DDR3_BUS_DEV_WIDTH; int index = spd[busw_offset] & 7; if (index >= ARRAY_SIZE(spd_busw)) return -1; @@ -144,11 +157,12 @@ static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) spd_name[DDR3_SPD_PART_LEN] = 0; break; case SPD_DRAM_LPDDR3_INTEL: - case SPD_DRAM_LPDDR3_JEDEC: memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], LPDDR3_SPD_PART_LEN); spd_name[LPDDR3_SPD_PART_LEN] = 0; break; + /* LPDDR3, LPDDR4 and DDR4 have the same part number offset */ + case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); From 0266be0d2bc8d667a705d2df433a0b6b19f614c5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 8 Mar 2020 18:36:00 +0100 Subject: [PATCH 0361/1463] soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries If we don't pretend to have binaries, there is no need to add fake ones. This also fixes building the default config. Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Kconfig | 2 +- src/mainboard/ocp/tiogapass/Kconfig | 1 - src/soc/intel/xeon_sp/Kconfig | 10 +--------- 3 files changed, 2 insertions(+), 11 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 024a478eb6..2624644fae 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -56,7 +56,7 @@ config FSP_USE_REPO depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \ - SOC_INTEL_DENVERTON_NS || SOC_INTEL_XEON_SP + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index dfa8f54275..87e27600dd 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -19,7 +19,6 @@ if BOARD_OCP_TIOGAPASS config BOARD_SPECIFIC_OPTIONS def_bool y - select ADD_FSP_BINARIES select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES select SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 8c355c4582..94c0ac4a8d 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -37,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_T_XIP select FSP_M_XIP - select FSP_USE_REPO select POSTCAR_STAGE select IOAPIC select PARALLEL_MP @@ -55,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE config MAINBOARD_USES_FSP2_0 @@ -69,14 +69,6 @@ config USE_FSP2_0_DRIVER select POSTCAR_CONSOLE select POSTCAR_STAGE -# Fake FSP binary is used, as the current FSP binary for SKX-SP -# is an engineering build. It is not available to the public -# for now. -config FSP_FD_PATH - string "Location of FSP binary" - depends on FSP_USE_REPO - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 From 549a33091a39de94998caa74f41d372118f5c12b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 8 Mar 2020 18:31:44 +0100 Subject: [PATCH 0362/1463] abuild: Always build the default config Abuild allows us to add config files below `configs/` for each mainboard. So far, these were built instead of the default config. However, that allows to hide errors in the default config. Hence, we should build that too in any case. Change-Id: I94075dbaa6fabeb75bdbc92e56f237df80c15cef Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39382 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/abuild/abuild | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 676a44662e..9688c8ce7d 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -526,16 +526,13 @@ function build_target build_dir=$TARGET/${BUILD_NAME} build_config "$MAINBOARD" "$build_dir" "$BUILD_NAME" "$config" remove_target "$BUILD_NAME" - done - else - echo "Building board $MAINBOARD (using default config)" - build_dir=$TARGET/${MAINBOARD} - - build_config "$MAINBOARD" "$build_dir" "$MAINBOARD" - remove_target "$MAINBOARD" fi + echo "Building board $MAINBOARD (using default config)" + build_dir=$TARGET/${MAINBOARD} + build_config "$MAINBOARD" "$build_dir" "$MAINBOARD" + remove_target "$MAINBOARD" } function remove_target From b8634685337b3730f474953e07fe9afd4f94007e Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Tue, 11 Sep 2018 00:02:36 +0300 Subject: [PATCH 0363/1463] util/board_status: Add support of CMOS values dump Change-Id: I89f9a0e9622557b01dda52378f8f1323777bce39 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/28565 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Peter Lemenkov Reviewed-by: Patrick Georgi --- util/board_status/board_status.sh | 48 ++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 0dc96e8bd7..6d6854d071 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -27,6 +27,9 @@ NONFATAL=1 # Used if cbmem is not in default $PATH, e.g. not installed or when using `sudo` CBMEM_PATH="" +# Used if nvramtool is not in default $PATH, e.g. not installed or when using `sudo` +NVRAMTOOL_PATH="" + # test a command # # $1: 0 ($LOCAL) to run command locally, @@ -176,6 +179,8 @@ show_help() { Options -c, --cbmem Path to cbmem on device under test (DUT). + -n, --nvramtool + Path to nvramtool on device under test (DUT). -C, --clobber Clobber temporary output when finished. Useful for debugging. -h, --help @@ -207,7 +212,7 @@ LONGOPTS="cbmem:,clobber,help,image:,remote-host:,upload-results" LONGOPTS="${LONGOPTS},serial-device:,serial-speed:" LONGOPTS="${LONGOPTS},ssh-port:" -ARGS=$(getopt -o c:Chi:r:s:S:u -l "$LONGOPTS" -n "$0" -- "$@"); +ARGS=$(getopt -o c:n:Chi:r:s:S:u -l "$LONGOPTS" -n "$0" -- "$@"); if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi eval set -- "$ARGS" while true ; do @@ -217,6 +222,10 @@ while true ; do shift CBMEM_PATH="$1" ;; + -n|--nvramtool) + shift + NVRAMTOOL_PATH="$1" + ;; -C|--clobber) CLOBBER_OUTPUT=1 ;; @@ -370,6 +379,17 @@ else cbmem_cmd="cbmem" fi +cmos_enabled=0 +if grep -q "CONFIG_USE_OPTION_TABLE=y" "${tmpdir}/${results}/config.short.txt" > /dev/null; then + cmos_enabled=1 +fi + +if [ -n "$NVRAMTOOL_PATH" ]; then + nvramtool_cmd="$NVRAMTOOL_PATH" +else + nvramtool_cmd="nvramtool" +fi + if [ -n "$SERIAL_DEVICE" ]; then get_serial_bootlog "$SERIAL_DEVICE" "$SERIAL_PORT_SPEED" "${tmpdir}/${results}/coreboot_console.txt" elif [ -n "$REMOTE_HOST" ]; then @@ -380,6 +400,13 @@ elif [ -n "$REMOTE_HOST" ]; then echo "Getting timestamp data" cmd_nonfatal $REMOTE "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" + if [ "$cmos_enabled" -eq 1 ]; then + echo "Verifying that nvramtool is available on remote device" + test_cmd $REMOTE "$nvramtool_cmd" + echo "Getting all CMOS values" + cmd $REMOTE "$nvramtool_cmd -a" "${tmpdir}/${results}/cmos_values.txt" + fi + echo "Getting remote dmesg" cmd $REMOTE dmesg "${tmpdir}/${results}/kernel_log.txt" else @@ -402,6 +429,25 @@ else echo "Getting timestamp data" cmd_nonfatal $LOCAL "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" + if [ "$cmos_enabled" -eq 1 ]; then + echo "Verifying that nvramtool is available" + if [ $(id -u) -ne 0 ]; then + command -v "$nvramtool_cmd" >/dev/null + if [ $? -ne 0 ]; then + echo "Failed to run $nvramtool_cmd. Check \$PATH or" \ + "use -n to specify path to nvramtool binary." + exit $EXIT_FAILURE + else + nvramtool_cmd="sudo $nvramtool_cmd" + fi + else + test_cmd $LOCAL "$nvramtool_cmd" + fi + + echo "Getting all CMOS values" + cmd $LOCAL "$nvramtool_cmd -a" "${tmpdir}/${results}/cmos_values.txt" + fi + echo "Getting local dmesg" cmd $LOCAL "sudo dmesg" "${tmpdir}/${results}/kernel_log.txt" fi From 79f7fcc92785c1bb50f1ee22f4adc9c6f3c0fee4 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Sat, 11 Jan 2020 01:26:54 +0300 Subject: [PATCH 0364/1463] util/nvramtool: fix building on OpenBSD OpenBSD's gcc 4.2.1 doesn't know about _Noreturn Change-Id: Ie9e1885c483941d3d0ce8c8948af53f1ef8bb5db Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/38348 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering Reviewed-by: Patrick Georgi --- util/nvramtool/common.c | 2 +- util/nvramtool/common.h | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/util/nvramtool/common.c b/util/nvramtool/common.c index 9b0a6b95ba..5dfc3bd99c 100644 --- a/util/nvramtool/common.c +++ b/util/nvramtool/common.c @@ -56,7 +56,7 @@ int get_line_from_file(FILE * f, char line[], int line_buf_size) * * We ran out of memory. Print an error message and die. ****************************************************************************/ -_Noreturn void out_of_memory(void) +noreturn void out_of_memory(void) { fprintf(stderr, "%s: Out of memory.\n", prog_name); exit(1); diff --git a/util/nvramtool/common.h b/util/nvramtool/common.h index 19ce5666a7..f49bc33831 100644 --- a/util/nvramtool/common.h +++ b/util/nvramtool/common.h @@ -69,6 +69,12 @@ int win32_munmap(void *start, size_t length); #define MAP_SHARED 1 #endif +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define noreturn _Noreturn +#else +#define noreturn +#endif + /* basename of this program, as reported by argv[0] */ extern const char prog_name[]; @@ -76,7 +82,7 @@ extern const char prog_name[]; extern const char prog_version[]; int get_line_from_file(FILE * f, char line[], int line_buf_size); -_Noreturn void out_of_memory(void); +noreturn void out_of_memory(void); void usage(FILE * outfile); #endif /* COMMON_H */ From 49fb39b7830c849d835f0632ab2967def8fa26a9 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Mon, 15 Jul 2019 18:26:23 +0200 Subject: [PATCH 0365/1463] Documentation: Update codenames austin-3 was a devel board, retracting t60 comes in variants with discrete gpu and only intel gpu one Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d Signed-off-by: Sebastian "Swift Geek" Grzywna Reviewed-on: https://review.coreboot.org/c/coreboot/+/34352 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/mainboard/lenovo/codenames.csv | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/mainboard/lenovo/codenames.csv b/Documentation/mainboard/lenovo/codenames.csv index ad77059480..655ff7b07a 100644 --- a/Documentation/mainboard/lenovo/codenames.csv +++ b/Documentation/mainboard/lenovo/codenames.csv @@ -1,4 +1,6 @@ -t60,magi-5|magi-7|austin-3 +t60,magi (dGPU) | lisa (iGPU) +z61m,BW2 +z61t,BV2 t400,malibu-3 t400s,shinai t410,nozomi-1 @@ -16,13 +18,18 @@ w510,kendo-1 workstation w520,kendo-3 workstation w530,kendo-4 workstation w700,n-note +w701,n-note 3.0 (nico-3) x1_carbon_gen1,genesis-1 x60,ks note x61,ks note-3 x200,mocha-1 +x200s,pecan-1 +x200t,caramel-1 x201,mocha-3 x220,dasher-1 +x220t,comet-1 x230,dasher-2 +x230t,comet-2 x230s,rogue-1 x240,rogue-2 x300,kodachi From 54e9894353ec2c6e635bead94a94953db069d49d Mon Sep 17 00:00:00 2001 From: Matt Delco Date: Mon, 9 Mar 2020 12:41:09 -0700 Subject: [PATCH 0366/1463] soc/intel: fix eist enabling There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/cpu.c | 3 ++- src/soc/intel/icelake/cpu.c | 3 ++- src/soc/intel/skylake/cpu.c | 9 +++------ src/soc/intel/tigerlake/cpu.c | 3 ++- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f01b499108..3ba0562980 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -263,9 +263,10 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index e058442585..91282d8a66 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -71,9 +71,10 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f5273f6fc7..d7da56eaf7 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -291,14 +291,11 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - - if (conf->eist_enable) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - else - msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ - wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + /* Disable Thermal interrupts */ msr.lo = 0; msr.hi = 0; diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 5f4f081818..cfbfdb3ea4 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -77,9 +77,10 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; From 2c18ba5bd7e279cd9e55fcfc93c180d52296a374 Mon Sep 17 00:00:00 2001 From: Stephen Douthit Date: Fri, 2 Aug 2019 17:05:03 -0400 Subject: [PATCH 0367/1463] soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode SATA Mode Select is bit 16 of the SATA General Configuration register. This code currently incorrectly pokes at the Port Clock Disable bits in the Port Mapping Register, and without clock the affected ports can't link. Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed Signed-off-by: Stephen Douthit Reviewed-on: https://review.coreboot.org/c/coreboot/+/34663 Tested-by: build bot (Jenkins) Reviewed-by: Vanessa Eusebio Reviewed-by: David Guckian Reviewed-by: Patrick Georgi --- src/soc/intel/denverton_ns/include/soc/sata.h | 7 +++---- src/soc/intel/denverton_ns/sata.c | 8 +++----- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/denverton_ns/include/soc/sata.h b/src/soc/intel/denverton_ns/include/soc/sata.h index afa39b5d65..f38b539353 100644 --- a/src/soc/intel/denverton_ns/include/soc/sata.h +++ b/src/soc/intel/denverton_ns/include/soc/sata.h @@ -23,9 +23,8 @@ #define PCH_SATA0_DEV PCI_DEV(0, SATA_DEV, SATA_FUNC) #define PCH_SATA1_DEV PCI_DEV(0, SATA2_DEV, SATA2_FUNC) -#define SATA_MAP 0x90 -#define SATA_MAP_AHCI (0 << 6) -#define SATA_MAP_RAID (1 << 6) -#define SATA_PSC 0x92 +#define SATAGC 0x9c +#define SATAGC_AHCI (0 << 16) +#define SATAGC_RAID (1 << 16) #endif //_DENVERTON_NS_SATA_H diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index d53d5535f0..891d95f934 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -31,7 +31,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u32 abar; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -46,10 +45,9 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set the controller mode */ - reg16 = pci_read_config16(dev, SATA_MAP); - reg16 &= ~(3 << 6); - reg16 |= SATA_MAP_AHCI; - pci_write_config16(dev, SATA_MAP, reg16); + reg32 = pci_read_config32(dev, SATAGC); + reg32 &= ~SATAGC_AHCI; + pci_write_config32(dev, SATAGC, reg32); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); From 2d6560873313bf7c2a6e02223b77a4510482cf28 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Tue, 31 Oct 2017 17:21:23 +0100 Subject: [PATCH 0368/1463] winbond/w83667hg-a: Disable mouse controller also during resume There is no reason to not disable the controller during resume. That way, no ASL is needed. Change-Id: I282a03647ee0958abb118fafe306abe5782db71c Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/superio/winbond/w83667hg-a/superio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index bc7bd92d03..685062170d 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -36,7 +36,7 @@ static void w83667hg_a_init(struct device *dev) mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); - if (!mouse_detected && !acpi_is_wakeup_s3()) { + if (!mouse_detected) { printk(BIOS_INFO, "%s: Disable mouse controller.", __func__); pnp_enter_conf_mode(dev); From b7731574f498dc8fd81c258b248ddfeda3eab5b5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 29 Dec 2019 11:05:31 +0100 Subject: [PATCH 0369/1463] src: Remove unneeded 'include ' Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/arch/arm/stages.c | 1 - src/arch/arm64/armv8/exception.c | 1 - src/arch/arm64/bl31.c | 1 - src/arch/arm64/boot.c | 1 - src/mainboard/google/daisy/romstage.c | 1 - src/mainboard/google/oak/mainboard.c | 1 - src/mainboard/google/peach_pit/romstage.c | 1 - src/mainboard/google/veyron/mainboard.c | 1 - src/mainboard/google/veyron_mickey/mainboard.c | 1 - src/mainboard/google/veyron_rialto/mainboard.c | 1 - src/soc/nvidia/tegra124/chip.h | 2 +- src/soc/nvidia/tegra210/sdram_lp0.c | 1 - src/soc/nvidia/tegra210/soc.c | 1 - src/soc/qualcomm/sc7180/aop_load_reset.c | 1 - src/soc/qualcomm/sdm845/aop_load_reset.c | 1 - src/soc/rockchip/rk3288/soc.c | 1 - src/soc/rockchip/rk3399/display.c | 1 - 17 files changed, 1 insertion(+), 17 deletions(-) diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index c1ea3d24ad..128b48cf55 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -14,7 +14,6 @@ #include #include -#include /** * generic stage entry point. override this if board specific code is needed. diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 6becf8328e..e2dfea0040 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c index 3677b41540..c06eee07ca 100644 --- a/src/arch/arm64/bl31.c +++ b/src/arch/arm64/bl31.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include #include #include #include diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index d2cef5b3f0..58b33a0915 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */ #include -#include #include #include #include diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 08570249e8..e200640dad 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 864837bbd4..4b3cc01763 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 0c2cb3e3e8..c9c45d27d4 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 8aa20aa006..6d6a2710c8 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index 2de720ccf4..f7af1cf0cf 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 52ecbf6bbc..8c775b63ff 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 7e930d11d6..b2b7490560 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -15,7 +15,7 @@ #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ #define __SOC_NVIDIA_TEGRA124_CHIP_H__ -#include + #include #include diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 09747ea269..85550516be 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index cedcc18094..a4cea7082d 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 5cf2311b70..8b69918d32 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 782c83ae8e..3c73ee60ce 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 31c999806f..9fb27cd326 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 9cd4053335..1db7f99c5e 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include From aa6a8fb9198acfe22fec944bc9484a800d689ff4 Mon Sep 17 00:00:00 2001 From: Praveen Hodagatta Pranesh Date: Tue, 29 Oct 2019 14:47:11 +0800 Subject: [PATCH 0370/1463] mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Signed-off-by: Praveen Hodagatta Pranesh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- src/mainboard/intel/saddlebrook/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 670a474865..ea3578550c 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -34,7 +34,7 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "1" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 5d69e52740..c2dd6f97cf 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -42,7 +42,7 @@ chip soc/intel/skylake register "Device4Enable" = "0" register "Heci3Enabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch From a51f4908704bee5e83f911eaf2fc241795b060ac Mon Sep 17 00:00:00 2001 From: Stephen Douthit Date: Mon, 5 Aug 2019 10:46:02 -0400 Subject: [PATCH 0371/1463] soc/intel/dnv: Fix ACPI reporting of root port interrupt routing pcie_port.asl defines an IRQM method that looks up legacy interrupt swizzling based on incoming interrupt "pin" A-D and root port number. Unfortunately the 8-bit root port number stored at offset 0x4F in the config space matches the device number, not the 1-8 scheme used in the LUT reported to the OS. Fix the case values to match the hardware. Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Signed-off-by: Stephen Douthit Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/denverton_ns/acpi/pcie.asl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index cb14cf8bb3..c9bbd3fa80 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -120,7 +120,7 @@ Method (IRQM, 1, Serialized) { Switch (ToInteger (Arg0)) { /* PCIe Root Port 1 */ - Case (Package() { 1 }) { + Case (Package() { 9 }) { If (PICM) { Return (IQAA) } Else { @@ -129,7 +129,7 @@ Method (IRQM, 1, Serialized) { } /* PCIe Root Port 2 */ - Case (Package() { 2 }) { + Case (Package() { 10 }) { If (PICM) { Return (IQBA) } Else { @@ -138,7 +138,7 @@ Method (IRQM, 1, Serialized) { } /* PCIe Root Port 3 */ - Case (Package() { 3 }) { + Case (Package() { 11 }) { If (PICM) { Return (IQCA) } Else { @@ -147,7 +147,7 @@ Method (IRQM, 1, Serialized) { } /* PCIe Root Port 4 */ - Case (Package() { 4 }) { + Case (Package() { 12 }) { If (PICM) { Return (IQDA) } Else { @@ -156,7 +156,7 @@ Method (IRQM, 1, Serialized) { } /* PCIe Root Port 5 */ - Case (Package() { 5 }) { + Case (Package() { 14 }) { If (PICM) { Return (IQEA) } Else { @@ -165,7 +165,7 @@ Method (IRQM, 1, Serialized) { } /* PCIe Root Port 6 */ - Case (Package() { 6 }) { + Case (Package() { 15 }) { If (PICM) { Return (IQFA) } Else { @@ -174,7 +174,7 @@ Method (IRQM, 1, Serialized) { } /* PCIe Root Port 7 */ - Case (Package() { 7 }) { + Case (Package() { 16 }) { If (PICM) { Return (IQGA) } Else { @@ -183,7 +183,7 @@ Method (IRQM, 1, Serialized) { } /* PCIe Root Port 8 */ - Case (Package() { 8 }) { + Case (Package() { 17 }) { If (PICM) { Return (IQHA) } Else { From ecb0e409a47b75778d1045d5c194f83b0a21eba6 Mon Sep 17 00:00:00 2001 From: Stephen Douthit Date: Mon, 5 Aug 2019 11:53:35 -0400 Subject: [PATCH 0372/1463] soc/intel/dnv: Add ACPI _PRT methods for virtual root ports This eliminates Linux kernel warnings that look like: pcieport 0000:00:17.0: can't derive routing for PCI INT B ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10 Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d Signed-off-by: Stephen Douthit Reviewed-on: https://review.coreboot.org/c/coreboot/+/34713 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/denverton_ns/acpi/northcluster.asl | 5 ++ src/soc/intel/denverton_ns/acpi/pcie.asl | 63 +++++++++++++++++++ .../intel/denverton_ns/acpi/southcluster.asl | 10 +++ 3 files changed, 78 insertions(+) diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index 58d63c26cf..b102f2fdfe 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -167,4 +167,9 @@ Device (RCEC) { // Virtual root port 2 Device (VRP2) { Name (_ADR, 0x00060000) + + Method (_PRT) + { + Return (IRQM (6)) + } } diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index c9bbd3fa80..bc47b77f09 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -118,7 +118,52 @@ Method (IRQM, 1, Serialized) { Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKG, 0 } }) + /* Interrupt Map INTA->INTC, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQIA, Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) + Name (IQIP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQJA, Package() { + Package() { 0x0000ffff, 0, 0, 23 }, + Package() { 0x0000ffff, 1, 0, 20 }, + Package() { 0x0000ffff, 2, 0, 21 }, + Package() { 0x0000ffff, 3, 0, 22 } }) + Name (IQJP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + + /* Interrupt Map INTA->INTB, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQKA, Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) + Name (IQKP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + Switch (ToInteger (Arg0)) { + /* Virtual Root Port 2 - QAT */ + Case (Package() { 6 }) { + If (PICM) { + Return (IQIA) + } Else { + Return (IQIP) + } + } + /* PCIe Root Port 1 */ Case (Package() { 9 }) { If (PICM) { @@ -191,6 +236,24 @@ Method (IRQM, 1, Serialized) { } } + /* Virtual Root Port 0 - LAN 0 */ + Case (Package() { 22 }) { + If (PICM) { + Return (IQJA) + } Else { + Return (IQJP) + } + } + + /* Virtual Root Port 1 - LAN 1 */ + Case (Package() { 23 }) { + If (PICM) { + Return (IQKA) + } Else { + Return (IQKP) + } + } + Default { If (PICM) { Return (IQDA) diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index bcc8a5ca31..674f0435c8 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -62,11 +62,21 @@ Scope(\) // Virtual root port 0 Device (VRP0) { Name (_ADR, 0x00160000) + + Method (_PRT) + { + Return (IRQM (22)) + } } // Virtual root port 1 Device (VRP1) { Name (_ADR, 0x00170000) + + Method (_PRT) + { + Return (IRQM (23)) + } } // ME HECI From 56a74bca6965d0c4dfa3c281d115cc2897eca677 Mon Sep 17 00:00:00 2001 From: Stephen Douthit Date: Mon, 5 Aug 2019 12:49:08 -0400 Subject: [PATCH 0373/1463] soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling This code also sets unused interrupt lines to the recommended safe value of 0xff instead of ignoring such devices. Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434 Signed-off-by: Stephen Douthit Reviewed-on: https://review.coreboot.org/c/coreboot/+/34714 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/denverton_ns/lpc.c | 276 +++++++++++++++++++++++++++++-- 1 file changed, 259 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 6481cbe00b..8c0a181d0c 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -65,6 +65,261 @@ static void pch_enable_ioapic(struct device *dev) io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } +/* interrupt router lookup for internal devices */ +struct dnv_ir_lut { + /* (dev << 3) | fn */ + u8 devfn; + u8 ir; +}; + +#define DEVFN(dev, fn) ((dev << 3) | (fn)) + +static const struct dnv_ir_lut dnv_ir_lut[] = { + {.devfn = DEVFN(0x05, 0), .ir = 3}, /* RCEC */ + {.devfn = DEVFN(0x06, 0), .ir = 4}, /* Virtual RP to QAT */ + {.devfn = DEVFN(0x09, 0), .ir = 7}, /* PCIe RP0 */ + {.devfn = DEVFN(0x0a, 0), .ir = 7}, /* PCIe RP1 */ + {.devfn = DEVFN(0x0b, 0), .ir = 7}, /* PCIe RP2 */ + {.devfn = DEVFN(0x0c, 0), .ir = 7}, /* PCIe RP3 */ + {.devfn = DEVFN(0x0e, 0), .ir = 8}, /* PCIe RP4 */ + {.devfn = DEVFN(0x0f, 0), .ir = 8}, /* PCIe RP5 */ + {.devfn = DEVFN(0x10, 0), .ir = 8}, /* PCIe RP6 */ + {.devfn = DEVFN(0x11, 0), .ir = 8}, /* PCIe RP7 */ + {.devfn = DEVFN(0x12, 0), .ir = 10}, /* SMBus - Host */ + {.devfn = DEVFN(0x13, 0), .ir = 6}, /* AHCI0 */ + {.devfn = DEVFN(0x14, 0), .ir = 11}, /* AHCI1 */ + {.devfn = DEVFN(0x15, 0), .ir = 9}, /* USB */ + {.devfn = DEVFN(0x16, 0), .ir = 1}, /* Virtual RP to LAN0 */ + {.devfn = DEVFN(0x17, 0), .ir = 2}, /* Virtual RP to LAN1 */ + {.devfn = DEVFN(0x18, 0), .ir = 5}, /* ME HECI1 */ + {.devfn = DEVFN(0x18, 1), .ir = 5}, /* ME HECI1 */ + {.devfn = DEVFN(0x18, 2), .ir = 5}, /* ME PTIO-IDER */ + {.devfn = DEVFN(0x18, 3), .ir = 5}, /* ME PTIO-KT */ + {.devfn = DEVFN(0x18, 4), .ir = 5}, /* ME HECI3 */ + {.devfn = DEVFN(0x1a, 0), .ir = 10}, /* HSUART0 */ + {.devfn = DEVFN(0x1a, 1), .ir = 10}, /* HSUART1 */ + {.devfn = DEVFN(0x1a, 2), .ir = 10}, /* HSUART2 */ + {.devfn = DEVFN(0x1b, 0), .ir = 12}, /* IE HECI1 */ + {.devfn = DEVFN(0x1b, 1), .ir = 12}, /* IE HECI1 */ + {.devfn = DEVFN(0x1b, 2), .ir = 12}, /* IE PTIO-IDER */ + {.devfn = DEVFN(0x1b, 3), .ir = 12}, /* IE PTIO-KT */ + {.devfn = DEVFN(0x1b, 4), .ir = 12}, /* IE HECI3 */ + {.devfn = DEVFN(0x1c, 0), .ir = 12}, /* SDHCI */ + {.devfn = DEVFN(0x1f, 0), .ir = 0}, /* LPC */ + {.devfn = DEVFN(0x1f, 1), .ir = 0}, /* PS2B */ + {.devfn = DEVFN(0x1f, 4), .ir = 0}, /* SMBus - Legacy */ + {.devfn = DEVFN(0x1f, 7), .ir = 0}, /* Trace Hub */ +}; + +/* + * Only 6 of the 8 root ports have swizzling, return '1' if this bdf is one of + * them, '0' otherwise + */ +static int is_dnv_swizzled_rp(uint16_t bdf) +{ + switch (bdf) { + case DEVFN(10, 0): + case DEVFN(11, 0): + case DEVFN(12, 0): + case DEVFN(15, 0): + case DEVFN(16, 0): + case DEVFN(17, 0): + return 1; + } + + return 0; +} + +/* + * Figure out which upstream interrupt pin a downstream device gets swizzled to + * + * config - pointer to chip_info containing routing info + * devfn - device/function of root port to check swizzling for + * pin - interrupt pin 1-4 = A-D + * + * Return new pin mapping, 0 if invalid pin + */ +static int dnv_get_swizzled_pin(config_t *config, u8 devfn, u8 pin) +{ + if (pin < 1 || pin > 4) + return 0; + + devfn >>= 3; + if (devfn < 13) + devfn -= 9; + else + devfn -= 14; + + return ((pin - 1 + devfn) % 4) + 1; +} + +/* + * Figure out which upstream interrupt pin a downstream device gets swizzled to + * + * config - pointer to chip_info containing routing info + * devfn - device/function of root port to check swizzling for + * pin - interrupt pin 1-4 = A-D + * + * Return new pin mapping, 0 if invalid pin + */ +static int dnv_get_ir(config_t *config, u8 devfn, u8 pin) +{ + int i = 0; + int line = 0xff; + u16 ir = 0xffff; + + /* The only valid pin values are 1-4 for A-D */ + if (pin < 1 || pin > 4) { + printk(BIOS_WARNING, "%s: pin %d is invalid\n", __func__, pin); + goto dnv_get_ir_done; + } + + for (i = 0; i < ARRAY_SIZE(dnv_ir_lut); i++) { + if (dnv_ir_lut[i].devfn == devfn) + break; + } + + if (i == ARRAY_SIZE(dnv_ir_lut)) { + printk(BIOS_WARNING, "%s: no entry\n", __func__); + goto dnv_get_ir_done; + } + + switch (dnv_ir_lut[i].ir) { + case 0: + ir = config->ir00_routing; + break; + case 1: + ir = config->ir01_routing; + break; + case 2: + ir = config->ir02_routing; + break; + case 3: + ir = config->ir03_routing; + break; + case 4: + ir = config->ir04_routing; + break; + case 5: + ir = config->ir05_routing; + break; + case 6: + ir = config->ir06_routing; + break; + case 7: + ir = config->ir07_routing; + break; + case 8: + ir = config->ir08_routing; + break; + case 9: + ir = config->ir09_routing; + break; + case 10: + ir = config->ir10_routing; + break; + case 11: + ir = config->ir11_routing; + break; + case 12: + ir = config->ir12_routing; + break; + default: + printk(BIOS_ERR, "%s: invalid ir %d for entry %d\n", __func__, dnv_ir_lut[i].ir, + i); + goto dnv_get_ir_done; + } + + ir >>= (pin - 1) * 4; + ir &= 0xf; + switch (ir) { + case 0: + line = config->pirqa_routing; + break; + case 1: + line = config->pirqb_routing; + break; + case 2: + line = config->pirqc_routing; + break; + case 3: + line = config->pirqd_routing; + break; + case 4: + line = config->pirqe_routing; + break; + case 5: + line = config->pirqf_routing; + break; + case 6: + line = config->pirqg_routing; + break; + case 7: + line = config->pirqh_routing; + break; + default: + printk(BIOS_ERR, "%s: invalid ir pirq %d for entry %d\n", __func__, ir, i); + break; + } + +dnv_get_ir_done: + return line; +} + +/* + * PCI devices have the INT_LINE (0x3C) and INT_PIN (0x3D) registers which + * report interrupt routing information to operating systems and drivers. The + * INT_PIN register is generally read only and reports which interrupt pin + * A - D it uses. The INT_LINE register is configurable and reports which IRQ + * (generally the PIC IRQs 1 - 15) it will use. This needs to take interrupt + * pin swizzling on devices that are downstream on a PCI bridge into account. + */ +static u8 dnv_get_int_line(struct device *irq_dev) +{ + config_t *config; + struct device *targ_dev = NULL; + uint16_t parent_bdf = 0; + int8_t original_int_pin = 0, new_int_pin = 0, swiz_int_pin = 0; + uint8_t int_line = 0xff; + + if (irq_dev->path.type != DEVICE_PATH_PCI || !irq_dev->enabled) { + printk(BIOS_ERR, "%s for non pci device?\n", __func__); + goto dnv_get_int_line_done; + } + + /* + * Get the INT_PIN swizzled up to the root port if necessary + * using the existing coreboot pci_device code + */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + goto dnv_get_int_line_done; + + printk(BIOS_DEBUG, "%s: irq_dev %s, targ_dev %s:\n", __func__, dev_path(irq_dev), + dev_path(targ_dev)); + printk(BIOS_DEBUG, "%s: std swizzle %s from %c to %c\n", __func__, dev_path(targ_dev), + '@' + original_int_pin, '@' + new_int_pin); + + /* Swizzle this device if needed */ + config = targ_dev->chip_info; + parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8; + if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) { + swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin); + printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__, + dev_path(targ_dev), '@' + new_int_pin, '@' + swiz_int_pin); + } else { + swiz_int_pin = new_int_pin; + } + + /* Look up the routing for the pin */ + int_line = dnv_get_ir(config, parent_bdf, swiz_int_pin); + +dnv_get_int_line_done: + printk(BIOS_DEBUG, "\tINT_LINE\t\t: %d\n", int_line); + return int_line; +} + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved @@ -150,6 +405,7 @@ static void pch_pirq_init(struct device *dev) config->ipc3); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + int devfn = irq_dev->path.pci.devfn; u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) @@ -157,23 +413,9 @@ static void pch_pirq_init(struct device *dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ - int_line = config->pirqa_routing; - break; - case 2: /* INTB# */ - int_line = config->pirqb_routing; - break; - case 3: /* INTC# */ - int_line = config->pirqc_routing; - break; - case 4: /* INTD# */ - int_line = config->pirqd_routing; - break; - } - - if (!int_line) - continue; + int_line = dnv_get_int_line(irq_dev); + printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__, + irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); } From 47ac6355b3f74a945392eaf670aa38941d04fd60 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 27 Nov 2018 15:25:59 +0100 Subject: [PATCH 0374/1463] soc/intel/common: Add more GPIO definition macros Make i/o-standby state and termination configurable for GPIs. Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/31350 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/common/block/include/intelblocks/gpio_defs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index dda02472a1..1f054dbdcf 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -265,6 +265,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) + +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ From 69a88ddb5d2f7e783f5dbe93e7dcf4594d245aca Mon Sep 17 00:00:00 2001 From: Bartek Pastudzki Date: Fri, 6 Apr 2018 12:40:09 +0200 Subject: [PATCH 0375/1463] util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format Intel supplies microcode (at least for MinnowBoard) in Intel Assembly *.inc format rather than C header. This change allow to pass in configuration directory with *.inc files rather than list of *.h files. Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540 Signed-off-by: Bartek Pastudzki Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/scripts/ucode_h_to_bin.sh | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh index f08b053b8e..436c0fd151 100755 --- a/util/scripts/ucode_h_to_bin.sh +++ b/util/scripts/ucode_h_to_bin.sh @@ -30,7 +30,7 @@ # if [ -z "$1" ] || [ -z "$2" ]; then - printf "Usage: %s \"\"\n" "$0" + printf "Usage: %s \"\"\\n" "$0" fi OUTFILE=$1 @@ -40,8 +40,24 @@ cat > "${TMPFILE}.c" << EOF unsigned int microcode[] = { EOF -for UCODE in ${@:2}; do - echo "#include \"$UCODE\"" >> "${TMPFILE}.c" +include_file() { + if [ "${1: -4}" == ".inc" ]; then + awk '{gsub( /h.*$/, "", $2 ); print "0x" $2 ","; }' "$1" \ + >> "${TMPFILE}.c" + else + echo "#include \"$1\"" >> "${TMPFILE}.c" + fi +} + +for UCODE in "${@:2}"; do + if [ -d "$UCODE" ]; then + for f in "$UCODE/"*.inc + do + include_file "$f" + done + else + include_file "$UCODE" + fi done cat >> "${TMPFILE}.c" << EOF From 5674bf15f929932f7cbfd6c1e36a26510d9ec0bf Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Mon, 9 Mar 2020 14:25:41 +1100 Subject: [PATCH 0376/1463] mb/google/puff: Enable cros_ec_keyb device This is required to transmit button information from EC to kernel. BUG=b:150830342 BRANCH=None TEST=firmware_ECPowerButton test passes on puff Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d Signed-off-by: Kangheui Won Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/variants/puff/include/variant/ec.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 2c2e62d24f..0746c5e6d4 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -51,6 +51,9 @@ * ACPI related definitions for ASL code. */ +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE From 1645ecc8f65a80c93719e62f3e0de0d441c1f822 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 5 Mar 2020 18:04:12 -0800 Subject: [PATCH 0377/1463] cbfs: Remove unused functions cbfs_boot_load_stage_by_name() and cbfs_prog_stage_section() are no longer used. Remove them to make refactoring the rest of the CBFS API easier. Signed-off-by: Julius Werner Change-Id: Ie44a9507c4a03499b06cdf82d9bf9c02a8292d5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Patrick Rudolph --- src/include/cbfs.h | 8 -------- src/lib/cbfs.c | 30 ------------------------------ 2 files changed, 38 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d16aa761a..2fe2ce0f35 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -25,9 +25,6 @@ /* Return mapping of option ROM found in boot device. NULL on error. */ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); -/* Load stage by name into memory. Returns entry address on success. NULL on - * failure. */ -void *cbfs_boot_load_stage_by_name(const char *name); /* Locate file by name and optional type. Return 0 on success. < 0 on error. */ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); /* Map file into memory leaking the mapping. Only should be used when @@ -51,11 +48,6 @@ size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); -/* Return the size and fill base of the memory pstage will occupy after - * loaded. - */ -size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base); - /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c712f76be8..7acfc224e5 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -179,24 +179,6 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); } -void *cbfs_boot_load_stage_by_name(const char *name) -{ - struct cbfsf fh; - struct prog stage = PROG_INIT(PROG_UNKNOWN, name); - uint32_t type = CBFS_TYPE_STAGE; - - if (cbfs_boot_locate(&fh, name, &type)) - return NULL; - - /* Chain data portion in the prog. */ - cbfs_file_data(prog_rdev(&stage), &fh); - - if (cbfs_prog_stage_load(&stage)) - return NULL; - - return prog_entry(&stage); -} - size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, uint32_t type) { @@ -217,18 +199,6 @@ size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, buf, buf_size, compression_algo); } -size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) -{ - struct cbfs_stage stage; - const struct region_device *fh = prog_rdev(pstage); - - if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) - return 0; - - *base = (uintptr_t)stage.load; - return stage.memlen; -} - int cbfs_prog_stage_load(struct prog *pstage) { struct cbfs_stage stage; From 8355aa4de2096561e5a32e7e870da144c1881b14 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 6 Mar 2020 17:59:00 -0800 Subject: [PATCH 0378/1463] prog_loaders: Remove CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING This option is not used on any platform and is not user-visible. It seems that it has not been used by anyone for a long time (maybe ever). Let's get rid of it to make future CBFS / program loader development simpler. Signed-off-by: Julius Werner Change-Id: I2fa4d6d6f7c1d7a5ba552177b45e890b70008f36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39442 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Patrick Rudolph --- src/cpu/x86/Kconfig | 9 ----- src/cpu/x86/Makefile.inc | 1 - src/cpu/x86/mirror_payload.c | 65 ----------------------------------- src/include/program_loading.h | 3 -- src/lib/prog_loaders.c | 6 ---- 5 files changed, 84 deletions(-) delete mode 100644 src/cpu/x86/mirror_payload.c diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 76446a04c0..dd7bb30146 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -169,15 +169,6 @@ config X86_AMD_INIT_SIPI common AP setup. Intel documentation specifies an INIT SIPI SIPI sequence, however this doesn't work on some AMD platforms. -config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING - def_bool n - help - On certain platforms a boot speed gain can be realized if mirroring - the payload data stored in non-volatile storage. On x86 systems the - payload would typically live in a memory-mapped SPI part. Copying - the SPI contents to RAM before performing the load can speed up - the boot process. - config SOC_SETS_MSRS bool default n diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 1191069502..bbe5545dc3 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,7 +1,6 @@ subdirs-y += pae subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c -ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c ramstage-y += backup_default_smm.c subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c deleted file mode 100644 index 9987347f33..0000000000 --- a/src/cpu/x86/mirror_payload.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void mirror_payload(struct prog *payload) -{ - char *buffer; - size_t size; - char *src; - uintptr_t alignment_diff; - const unsigned long cacheline_size = 64; - const uintptr_t intra_cacheline_mask = cacheline_size - 1; - const uintptr_t cacheline_mask = ~intra_cacheline_mask; - - src = prog_start(payload); - size = prog_size(payload); - - /* - * Adjust size so that the start and end points are aligned to a - * cacheline. The SPI hardware controllers on Intel machines should - * cache full length cachelines as well as prefetch data. Once the - * data is mirrored in memory all accesses should hit the CPU's cache. - */ - alignment_diff = (intra_cacheline_mask & (uintptr_t)src); - size += alignment_diff; - - size = ALIGN_UP(size, cacheline_size); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%zx\n", size); - - buffer = bootmem_allocate_buffer(size); - - if (buffer == NULL) { - printk(BIOS_DEBUG, "No buffer for mirroring payload.\n"); - return; - } - - src = (void *)(cacheline_mask & (uintptr_t)src); - - /* - * Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. - */ - memcpy(buffer, src, size); - - /* Update the payload's backing store. */ - prog_set_area(payload, &buffer[alignment_diff], prog_size(payload)); -} diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 320ff3cc1e..d3930083c5 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -205,9 +205,6 @@ void payload_load(void); /* Run the loaded payload. */ void payload_run(void); -/* Mirror the payload to be loaded. */ -void mirror_payload(struct prog *payload); - /* * selfload() and selfload_check() load payloads into memory. * selfload() does not check the payload to see if it targets memory. diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 0319325841..178209c65d 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -170,10 +170,6 @@ fail: static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); -void __weak mirror_payload(struct prog *payload) -{ -} - void payload_load(void) { struct prog *payload = &global_payload; @@ -183,8 +179,6 @@ void payload_load(void) if (prog_locate(payload)) goto out; - mirror_payload(payload); - switch (prog_cbfs_type(payload)) { case CBFS_TYPE_SELF: /* Simple ELF */ selfload_check(payload, BM_MEM_RAM); From 8273e13a115289c48beb7366cf7a03ccd8b5e108 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 10 Mar 2020 22:17:12 +0100 Subject: [PATCH 0379/1463] intel/i945: Call fixup_i945_errata() only for mobile version MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per Mobile Intel ® 945 Express Chipset Family - Specification Update Document Number: 309220-013 (page 15), the power saving optimization Erratum is for Mobile Intel ® 945 Express Chipset family. So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply that function only for I945GM. Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i945/errata.c | 2 +- src/northbridge/intel/i945/raminit.h | 2 +- src/northbridge/intel/i945/romstage.c | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c index 2b9b941aba..4d8b999d46 100644 --- a/src/northbridge/intel/i945/errata.c +++ b/src/northbridge/intel/i945/errata.c @@ -17,7 +17,7 @@ #include "i945.h" #include "raminit.h" -int fixup_i945_errata(void) +int fixup_i945gm_errata(void) { u32 reg32; diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index d417169c62..26a1f5024b 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -67,5 +67,5 @@ struct sys_info { void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); -int fixup_i945_errata(void); +int fixup_i945gm_errata(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 6274e099c8..2333b7d79a 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -76,7 +76,8 @@ void mainboard_romstage_entry(void) mainboard_late_rcba_config(); /* Chipset Errata! */ - fixup_i945_errata(); + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + fixup_i945gm_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); From e13bc1c12ce414307be780c30d2d22074a5fd2c5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 10 Mar 2020 21:30:00 +0100 Subject: [PATCH 0380/1463] mb/amd/lamar: Drop unmaintained ROMCC board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/mainboard/amd/lamar/BiosCallOuts.c | 329 --------------------- src/mainboard/amd/lamar/Kconfig | 82 ----- src/mainboard/amd/lamar/Kconfig.name | 3 - src/mainboard/amd/lamar/Makefile.inc | 20 -- src/mainboard/amd/lamar/OemCustomize.c | 133 --------- src/mainboard/amd/lamar/acpi/gpe.asl | 73 ----- src/mainboard/amd/lamar/acpi/mainboard.asl | 37 --- src/mainboard/amd/lamar/acpi/routing.asl | 300 ------------------- src/mainboard/amd/lamar/acpi/si.asl | 22 -- src/mainboard/amd/lamar/acpi/sleep.asl | 99 ------- src/mainboard/amd/lamar/acpi/thermal.asl | 2 - src/mainboard/amd/lamar/acpi/usb_oc.asl | 27 -- src/mainboard/amd/lamar/acpi_tables.c | 45 --- src/mainboard/amd/lamar/board_info.txt | 5 - src/mainboard/amd/lamar/cmos.layout | 59 ---- src/mainboard/amd/lamar/devicetree.cb | 101 ------- src/mainboard/amd/lamar/dsdt.asl | 88 ------ src/mainboard/amd/lamar/irq_tables.c | 100 ------- src/mainboard/amd/lamar/mainboard.c | 151 ---------- src/mainboard/amd/lamar/mptable.c | 151 ---------- src/mainboard/amd/lamar/romstage.c | 41 --- 21 files changed, 1868 deletions(-) delete mode 100644 src/mainboard/amd/lamar/BiosCallOuts.c delete mode 100644 src/mainboard/amd/lamar/Kconfig delete mode 100644 src/mainboard/amd/lamar/Kconfig.name delete mode 100644 src/mainboard/amd/lamar/Makefile.inc delete mode 100644 src/mainboard/amd/lamar/OemCustomize.c delete mode 100644 src/mainboard/amd/lamar/acpi/gpe.asl delete mode 100644 src/mainboard/amd/lamar/acpi/mainboard.asl delete mode 100644 src/mainboard/amd/lamar/acpi/routing.asl delete mode 100644 src/mainboard/amd/lamar/acpi/si.asl delete mode 100644 src/mainboard/amd/lamar/acpi/sleep.asl delete mode 100644 src/mainboard/amd/lamar/acpi/thermal.asl delete mode 100644 src/mainboard/amd/lamar/acpi/usb_oc.asl delete mode 100644 src/mainboard/amd/lamar/acpi_tables.c delete mode 100644 src/mainboard/amd/lamar/board_info.txt delete mode 100644 src/mainboard/amd/lamar/cmos.layout delete mode 100644 src/mainboard/amd/lamar/devicetree.cb delete mode 100644 src/mainboard/amd/lamar/dsdt.asl delete mode 100644 src/mainboard/amd/lamar/irq_tables.c delete mode 100644 src/mainboard/amd/lamar/mainboard.c delete mode 100644 src/mainboard/amd/lamar/mptable.c delete mode 100644 src/mainboard/amd/lamar/romstage.c diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c deleted file mode 100644 index 30dc0d6d63..0000000000 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "imc.h" -#include "hudson.h" - -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * Realtek ALC272 CODEC Verb Table - */ -static const CODEC_ENTRY Alc272_VerbTbl[] = { - { 0x11, 0x411111F0 }, /* - S/PDIF Output 2 */ - { 0x12, 0x411111F0 }, /* - Digital Mic 1/2 [GPIO0] */ - { 0x13, 0x411111F0 }, /* - Digital Mic 3/4 [GPIO1] */ - { 0x14, 0x411111F0 }, /* Port D - Front Panel headphone */ - { 0x15, 0x411111F0 }, /* Port A - Surround */ - { 0x17, 0x411111F0 }, /* Port H - Mono */ - { 0x18, /* Port B - MIC - pink jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_PINK << 12) - | (4 << 4) - | (0 << 0) - }, - { 0x19, 0x411111F0 }, /* Port F - Front Panel Mic */ - { 0x1A, /* Port C - LineIn1 - blue jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_LINEIN << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_BLUE << 12) - | (4 << 4) - | (0xF << 0) - }, - { 0x1B, 0x411111F0 }, /* Port E - Front Panel line-out */ - { 0x1D, 0x40251E05 }, /* PC Beep - (internal) */ - { 0x1E, /* S/PDIF - Internal Header */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) - | (AZALIA_PINCFG_DEVICE_SPDIF_OUT << 20) - | (AZALIA_PINCFG_CONN_RCA << 16) - | (AZALIA_PINCFG_COLOR_BLACK << 12) - | (1 << 4) - | (0 << 0) - }, - { 0x21, /* Port I - HPout - green jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_GREEN << 12) - | (4 << 4) - | (0 << 0) - }, - { 0xFF, 0xFFFFFFFF }, -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* - * Hardware Monitor Fan Control - * Hardware limitation: - * HWM will fail to read the input temperature via I2C if other - * software switches the I2C address. AMD recommends using IMC - * to control fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - FCH_HWM_FAN_CTR oem_factl[5] = { - /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - - /* Enable IMC fan control. the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /* AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /* AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /* AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /* AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /* AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /* AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /* AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /* AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /* critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /* AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /* AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /* AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8 */ - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. - * so we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, using the alternative method */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - - /* Turn on FCH GPP slots */ - FchParams->FchReset.GppEnable = TRUE; - FchParams->Gpp.GppFunctionEnable = TRUE; - FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; - FchParams->Gpp.PortCfg[0].PortPresent = TRUE; - FchParams->Gpp.PortCfg[1].PortPresent = TRUE; - FchParams->Gpp.PortCfg[2].PortPresent = TRUE; - FchParams->Gpp.PortCfg[3].PortPresent = TRUE; - FchParams->FchReset.SataEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); - FchParams->FchReset.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); - - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* Turn on FCH GPP slots */ - FchParams->Gpp.GppFunctionEnable = TRUE; - FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; - - /* Azalia Controller OEM Codec Table Pointer */ - FchParams->Azalia.AzaliaPinCfg = TRUE; - FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ - .AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03, - .AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03, - .AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03, - .AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03 - }; - FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; - /* Azalia Controller Front Panel OEM Table Pointer */ - - /* Fan Control */ - oem_fan_control(FchParams); - } - printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig deleted file mode 100644 index c8565341d7..0000000000 --- a/src/mainboard/amd/lamar/Kconfig +++ /dev/null @@ -1,82 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_LAMAR - def_bool n - -if BOARD_AMD_LAMAR - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK - select CPU_AMD_PI_00630F01 - select NORTHBRIDGE_AMD_PI_00630F01 - select SOUTHBRIDGE_AMD_PI_BOLTON - select DEFAULT_POST_ON_LPC - select SUPERIO_FINTEK_F81216H - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/lamar" - -config MAINBOARD_PART_NUMBER - string - default "DB-FP3" - -config MAINBOARD_SERIAL_NUMBER - string - default "52198A" - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_XHCI_FWM_FILE - string - default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" - -config AZ_PIN - hex - default 0x02 - -config ENABLE_DP3_DAUGHTER_CARD_IN_J120 - bool "Use J120 as an additional graphics port" - default n - help - The PCI Express slot at J120 can be configured as an additional - DisplayPort connector using an adapter card from AMD or as a normal - PCI Express (x4) slot. - - By default, the connector is configured as a PCI Express (x4) slot. - - Select this option to enable the slot for use with one of AMD's - passive graphics port expander cards (only available from AMD). - -endif # BOARD_AMD_LAMAR diff --git a/src/mainboard/amd/lamar/Kconfig.name b/src/mainboard/amd/lamar/Kconfig.name deleted file mode 100644 index 75eec04ae3..0000000000 --- a/src/mainboard/amd/lamar/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -# Disabled -#config BOARD_AMD_LAMAR -# bool "Lamar" diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc deleted file mode 100644 index 37c1dceead..0000000000 --- a/src/mainboard/amd/lamar/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c deleted file mode 100644 index 4c1832b154..0000000000 --- a/src/mainboard/amd/lamar/OemCustomize.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - - /* - * Lanes to pins to PCI device mapping can be found in section 2.12 of the - * BIOS and Kernel Developer's Guide for AMD Family 15h Models 30h-3Fh - */ - - { /* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 31), - PCIE_PORT_DATA_INITIALIZER_V2( - PortEnabled, - ChannelTypeExt6db, 0, 0, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, - 175, - 0 - ) - }, - - { /* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 11), - PCIE_PORT_DATA_INITIALIZER_V2( - PortEnabled, - ChannelTypeExt6db, 0, 0, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, - 176, - 0 - ) - }, - - { /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */ - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER( - CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine, - 12, 15 - ), - PCIE_PORT_DATA_INITIALIZER_V2( - PortEnabled, - ChannelTypeExt6db, 0, 0, - HotplugDisabled, - PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, - 177, - 0 - ) - }, - -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - { /* DP3 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER( - CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine, - 12, 15 - ), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux4, Hdp4) - }, - - { /* DP2 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 36, 39), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, - - { /* DP1 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - - { /* DP0 */ - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 4, 7), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl deleted file mode 100644 index 297d9b47cb..0000000000 --- a/src/mainboard/amd/lamar/acpi/gpe.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/lamar/acpi/mainboard.asl b/src/mainboard/amd/lamar/acpi/mainboard.asl deleted file mode 100644 index d251657e0b..0000000000 --- a/src/mainboard/amd/lamar/acpi/mainboard.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } diff --git a/src/mainboard/amd/lamar/acpi/routing.asl b/src/mainboard/amd/lamar/acpi/routing.asl deleted file mode 100644 index 531ceeae48..0000000000 --- a/src/mainboard/amd/lamar/acpi/routing.asl +++ /dev/null @@ -1,300 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 Pcie Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS3, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS3, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - }) diff --git a/src/mainboard/amd/lamar/acpi/si.asl b/src/mainboard/amd/lamar/acpi/si.asl deleted file mode 100644 index bec166c72b..0000000000 --- a/src/mainboard/amd/lamar/acpi/si.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl deleted file mode 100644 index f7edfb9119..0000000000 --- a/src/mainboard/amd/lamar/acpi/sleep.asl +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - - Store (0x07, UPWS) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,USBS) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/lamar/acpi/thermal.asl b/src/mainboard/amd/lamar/acpi/thermal.asl deleted file mode 100644 index 73077ac4d3..0000000000 --- a/src/mainboard/amd/lamar/acpi/thermal.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No thermal zone functionality */ diff --git a/src/mainboard/amd/lamar/acpi/usb_oc.asl b/src/mainboard/amd/lamar/acpi/usb_oc.asl deleted file mode 100644 index 4254e7e469..0000000000 --- a/src/mainboard/amd/lamar/acpi/usb_oc.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/lamar/acpi_tables.c b/src/mainboard/amd/lamar/acpi_tables.c deleted file mode 100644 index 65e74baf40..0000000000 --- a/src/mainboard/amd/lamar/acpi_tables.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write southbridge IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/lamar/board_info.txt b/src/mainboard/amd/lamar/board_info.txt deleted file mode 100644 index 8bce92e85c..0000000000 --- a/src/mainboard/amd/lamar/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: DB-FP3 (Lamar) -Category: eval -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/amd/lamar/cmos.layout b/src/mainboard/amd/lamar/cmos.layout deleted file mode 100644 index dc9b789385..0000000000 --- a/src/mainboard/amd/lamar/cmos.layout +++ /dev/null @@ -1,59 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb deleted file mode 100644 index 5c88a3c557..0000000000 --- a/src/mainboard/amd/lamar/devicetree.cb +++ /dev/null @@ -1,101 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# 2013 - 2014 Sage Electronic Engineering, LLC -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/pi/00630F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00630F01 - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - - chip northbridge/amd/pi/00630F01 - device pci 0.0 on end # 0x1422 Root Complex - device pci 0.2 off end # 0x1423 IOMMU - device pci 1.0 on end # 0x13XX Internal Graphics - device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio - device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge - device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) - device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 - device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge - device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) - device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) - device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 - device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 - device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 - device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge -# device pci 4.1 on end # 0x1426 P2P bridge for UMI link -# device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 -# device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 -# device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 -# device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 - end #chip northbridge/amd/pi/00630F01 - - chip southbridge/amd/pi/hudson - device pci 10.0 on end # 0x7814 XHCI HC0 - device pci 10.1 on end # 0x7814 XHCI HC1 - device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) - device pci 12.0 on end # 0x7807 USB OHCI - device pci 12.2 on end # 0x7808 USB EHCI - device pci 13.0 on end # 0x7807 USB OHCI - device pci 13.2 on end # 0x7808 USB EHCI - device pci 14.0 on end # SM - device pci 14.1 on end # 0x780C IDE - device pci 14.2 on end # 0x780D HDA - device pci 14.3 on # 0x780E LPC - chip superio/fintek/f81216h - register "conf_key_mode" = "0x77" - device pnp 4e.0 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.1 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.2 off end # COM3 - device pnp 4e.3 off end # COM4 - device pnp 4e.8 off end # WDT - end # f81865f - end #LPC - device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. - device pci 14.5 on end # 0x7809 USB OHCI - device pci 14.7 on end # 0x7806 SD Flash Controller - device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) - device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) - device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) - device pci 15.3 off end # 0x43A3 SB GPP Port 3 - register "gpp_configuration" = "4" - device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) - end #southbridge/amd/pi/hudson - - chip northbridge/amd/pi/00630F01 - device pci 18.0 on end # 0x141A HT Configuration - device pci 18.1 on end # 0x141B Address Maps - device pci 18.2 on end # 0x141C DRAM Configuration - device pci 18.3 on end # 0x141D Miscellaneous - device pci 18.4 on end # 0x141E Power Management - device pci 18.5 on end # 0x141F Northbridge - - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/pi/00630F01/root_complex diff --git a/src/mainboard/amd/lamar/dsdt.asl b/src/mainboard/amd/lamar/dsdt.asl deleted file mode 100644 index 1db743d5ca..0000000000 --- a/src/mainboard/amd/lamar/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include - - /* Describe the processor tree (\_PR) */ - #include - - /* Contains the supported sleep states for this chipset */ - #include - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/lamar/irq_tables.c b/src/mainboard/amd/lamar/irq_tables.c deleted file mode 100644 index fc3fbec2d4..0000000000 --- a/src/mainboard/amd/lamar/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c deleted file mode 100644 index 264c603357..0000000000 --- a/src/mainboard/amd/lamar/mainboard.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - */ -static const u8 mainboard_picr_data[] = { - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ - [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A, - [0x18] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x28] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22 INTA-C */ - [0x30] = 0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x1F, - [0x38] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [40..41] IDE, SATA */ - [0x40] = 0x1F,0x0F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x48] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [50..53] GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B, - [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x60] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [80..81] Northbridge devices (indices above C00/C01 range) */ - [0x80] = 0x0C,0x1F, -}; - -static const u8 mainboard_intr_data[] = { - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, - [0x18] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x28] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x11,0x12,0x11,0x12,0x11,0x12,0x11,0x1F, - [0x38] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* SATA */ - [0x40] = 0x11,0x13,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x48] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [50..53] GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13, - [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x60] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [80..81] Northbridge devices (indices above C00/C01 range) */ - [0x80] = 0x17,0x10, -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */ - {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */ - {XHCI_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ - {XHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.1 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ - {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* LAN: 15.0 */ - {SB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe J122: 15.1 */ - {SB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe J123: 15.2 */ - {SB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* unused 15.3 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = FCH_INT_TABLE_SIZE /* FIXME sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct) */; - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/************************************************* - * enable the dedicated function in lamar board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c deleted file mode 100644 index 1f2093dd3a..0000000000 --- a/src/mainboard/amd/lamar/mptable.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define NB_APIC_ADDR ((u8 *)0xFEC20000) - -#define PCI_INT(bus, dev, fn, apic, pin) \ - if (((pin) != 0x00) && ((pin) != 0x1F)) \ - { \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \ - } - -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - - u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */ - u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */ - - smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR); - - u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */ - u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */ - - smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]); - PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]); - - /* PCI slots */ - /* NB Gfx PCIe Bridges */ - PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* NB GPP PCIe Bridges */ - PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* PCI slots */ - PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]); - - /* FCH GPP PCIe Bridges */ - PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c deleted file mode 100644 index 66188bdc1c..0000000000 --- a/src/mainboard/amd/lamar/romstage.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) - -static void romstage_main_template(void) -{ - misc_write32(0x28, misc_read32(0x28) | (1 << 18)); /* 24Mhz */ - misc_write32(0x40, misc_read32(0x40) & (~(1 << 2))); /* 24Mhz */ - - if (!cpu_init_detectedx) { - post_code(0x30); - f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); - post_code(0x31); - console_init(); - } -} From f4cfefe78895a445ec8d65176e67f5fcacdfac99 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 10 Mar 2020 21:31:56 +0100 Subject: [PATCH 0381/1463] mb/amd/db-ft3b-lc: Drop unmaintained ROMCC board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c | 319 ------------------ src/mainboard/amd/db-ft3b-lc/Kconfig | 65 ---- src/mainboard/amd/db-ft3b-lc/Kconfig.name | 3 - src/mainboard/amd/db-ft3b-lc/Makefile.inc | 40 --- .../db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex | 237 ------------- src/mainboard/amd/db-ft3b-lc/OemCustomize.c | 208 ------------ src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl | 74 ---- src/mainboard/amd/db-ft3b-lc/acpi/ide.asl | 2 - .../amd/db-ft3b-lc/acpi/mainboard.asl | 35 -- src/mainboard/amd/db-ft3b-lc/acpi/routing.asl | 194 ----------- src/mainboard/amd/db-ft3b-lc/acpi/si.asl | 23 -- src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl | 95 ------ src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl | 2 - src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl | 37 -- src/mainboard/amd/db-ft3b-lc/acpi_tables.c | 46 --- src/mainboard/amd/db-ft3b-lc/board_info.txt | 6 - src/mainboard/amd/db-ft3b-lc/cmos.layout | 66 ---- src/mainboard/amd/db-ft3b-lc/devicetree.cb | 61 ---- src/mainboard/amd/db-ft3b-lc/dsdt.asl | 88 ----- src/mainboard/amd/db-ft3b-lc/irq_tables.c | 100 ------ src/mainboard/amd/db-ft3b-lc/mainboard.c | 124 ------- src/mainboard/amd/db-ft3b-lc/mptable.c | 126 ------- src/mainboard/amd/db-ft3b-lc/romstage.c | 51 --- 23 files changed, 2002 deletions(-) delete mode 100644 src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c delete mode 100644 src/mainboard/amd/db-ft3b-lc/Kconfig delete mode 100644 src/mainboard/amd/db-ft3b-lc/Kconfig.name delete mode 100644 src/mainboard/amd/db-ft3b-lc/Makefile.inc delete mode 100644 src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex delete mode 100644 src/mainboard/amd/db-ft3b-lc/OemCustomize.c delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/ide.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/routing.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/si.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/acpi_tables.c delete mode 100644 src/mainboard/amd/db-ft3b-lc/board_info.txt delete mode 100644 src/mainboard/amd/db-ft3b-lc/cmos.layout delete mode 100644 src/mainboard/amd/db-ft3b-lc/devicetree.cb delete mode 100644 src/mainboard/amd/db-ft3b-lc/dsdt.asl delete mode 100644 src/mainboard/amd/db-ft3b-lc/irq_tables.c delete mode 100644 src/mainboard/amd/db-ft3b-lc/mainboard.c delete mode 100644 src/mainboard/amd/db-ft3b-lc/mptable.c delete mode 100644 src/mainboard/amd/db-ft3b-lc/romstage.c diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c deleted file mode 100644 index ebdea42990..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "imc.h" -#include "hudson.h" - -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * Realtek ALC272 CODEC Verb Table - */ -static const CODEC_ENTRY Alc272_VerbTbl[] = { - { 0x11, 0x411111F0 }, /* - S/PDIF Output 2 */ - { 0x12, 0x411111F0 }, /* - Digital Mic 1/2 [GPIO0] */ - { 0x13, 0x411111F0 }, /* - Digital Mic 3/4 [GPIO1] */ - { 0x14, 0x411111F0 }, /* Port D - Front Panel headphone */ - { 0x15, 0x411111F0 }, /* Port A - Surround */ - { 0x17, 0x411111F0 }, /* Port H - Mono */ - { 0x18, /* Port B - MIC - combo jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_BLACK << 12) - | (4 << 4) - | (0 << 0) - }, - { 0x19, 0x411111F0 }, /* Port F - Front Panel Mic */ - { 0x1A, 0x411111F0 }, /* Port C - LINE1 */ - { 0x1B, 0x411111F0 }, /* Port E - Front Panel line-out */ - { 0x1D, 0x40130605 }, /* - PCBEEP */ - { 0x1E, 0x411111F0 }, /* - SPDIF_OUT1 */ - { 0x21, /* Port I - HPout - combo jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_BLACK << 12) - | (4 << 4) - | (0 << 0) - }, - { 0xFF, 0xFFFFFFFF }, -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, Alc272_VerbTbl}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* - * Hardware Monitor Fan Control - * Hardware limitation: - * HWM will fail to read the input temperature via I2C if other - * software switches the I2C address. AMD recommends using IMC - * to control fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - FCH_HWM_FAN_CTR oem_factl[5] = { - /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* DB-FT3 FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* DB-FT3 FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - - /* Enable IMC fan control. the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; /* 6 | BIT3 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0; /* AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /* AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /* AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /* AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /* AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /* AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /*BIT0 | BIT4 |BIT8; */ - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. - * so we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, using the alternative method */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE; /* 1 enable, 0 disable TSI Auto Polling */ - } -} - -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* Azalia Controller OEM Codec Table Pointer */ - FchParams->Azalia.AzaliaPinCfg = TRUE; - FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ - .AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03, - .AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03, - .AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03, - .AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03 - }; - FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; - /* Azalia Controller Front Panel OEM Table Pointer */ - - /* Fan Control */ - oem_fan_control(FchParams); - - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; - - /* sata configuration */ - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } - } - printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig deleted file mode 100644 index f17d2d34e9..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2015 Kyösti Mälkki -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_DB_FT3B_LC - def_bool n - -if BOARD_AMD_DB_FT3B_LC - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK - select CPU_AMD_PI_00730F01 - select NORTHBRIDGE_AMD_PI_00730F01 - select SOUTHBRIDGE_AMD_PI_AVALON - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/db-ft3b-lc" - -config MAINBOARD_PART_NUMBER - string - default "DB-FT3b-LC" - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -config DIMM_SPD_SIZE - int - default 128 - -endif # BOARD_AMD_DB_FT3B_LC diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig.name b/src/mainboard/amd/db-ft3b-lc/Kconfig.name deleted file mode 100644 index 3197a70694..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -# Disabled -#config BOARD_AMD_DB_FT3B_LC -# bool "DB-FT3b-LC" diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc deleted file mode 100644 index 97c761fa45..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c - -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = Memphis_MEM4G16D3EABG - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex b/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex deleted file mode 100644 index 3bbe027a88..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex +++ /dev/null @@ -1,237 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -# LOWCOST board has 2GB using 4 Memphis MEM4G16D3EABG chips - -# The datasheet is available at: -# http://www.memphis.ag/fileadmin/datasheets/MEM4G16D3EABG_10.pdf - -# SPD contents for LC (LowCost) 4GB DDR3 (1600MHz) soldered down - -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x10 = Revision 1.0 -10 - -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 1 = RDIMM -# bits[3:0]: 2 = UDIMM -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip -# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -04 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 2 = 14 Row Address Bits -# bits[5:3]: 3 = 15 Row Address Bits -# bits[7:6]: reserved -19 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 2 = 16 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -02 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 0 = 0 bits (no bus width extension) -# bits[7:5]: reserved -03 - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x02 divisor -# bits[7:4]: 0x05 dividend -# 5/2 = 2.5ps -52 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) -0A - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 11 - 5 are supported -FE 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x3C = 7.5ns -3C - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x118 = 35ns - DDR3-1600 (see byte 21) -2C - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x186 = 48.75ns - DDR3-1600K -95 - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -# 0x820 = 260ns - for 4 Gigabit chips -20 08 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x0140 = 40ns - DDR3-1600, 2 KB page size -# 0x00F0 = 30ns - DDR3-1600, 2 KB page size -00 F0 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 1 = DLL Off mode supported -83 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 1 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -05 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 0 = Signal Loading not specified -# bits[3:2]: reserved -# bits[6:4]: 0 = Die count not specified -# bit7 : 0 = Standard Monolithic DRAM Device -00 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 - 59 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 116 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x0001 = AMD -00 01 - -# 119 Module ID: Module Manufacturing Location - oem specified -# 120 Module ID: Module Manufacture Year in BCD -# 0x14 = 2014 -00 14 - -# 121 Module ID: Module Manufacture week -# 0x12 = 12th week -12 - -# 122 - 125: Module Serial Number -00 00 00 00 - -# 126 - 127: Cyclical Redundancy Code -00 00 diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c deleted file mode 100644 index e90b92802a..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = { - /* - * The following macros are supported (use comma to separate macros): - * - * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - * The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - * AGESA will base on this value to disable unused MemClk to save power. - * Example: - * BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - * Bit AM3/S1g3 pin name - * 0 M[B,A]_CLK_H/L[0] - * 1 M[B,A]_CLK_H/L[1] - * 2 M[B,A]_CLK_H/L[2] - * 3 M[B,A]_CLK_H/L[3] - * 4 M[B,A]_CLK_H/L[4] - * 5 M[B,A]_CLK_H/L[5] - * 6 M[B,A]_CLK_H/L[6] - * 7 M[B,A]_CLK_H/L[7] - * And platform has the following routing: - * CS0 M[B,A]_CLK_H/L[4] - * CS1 M[B,A]_CLK_H/L[2] - * CS2 M[B,A]_CLK_H/L[3] - * CS3 M[B,A]_CLK_H/L[5] - * Then platform can specify the following macro: - * MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - * - * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - * The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - * AGESA will base on this value to tristate unused CKE to save power. - * - * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - * The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - * AGESA will base on this value to tristate unused ODT pins to save power. - * - * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - * The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - * AGESA will base on this value to tristate unused Chip select to save power. - * - * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - * Specifies the number of DIMM slots per channel. - * - * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - * Specifies the number of Chip selects per channel. - * - * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - * Specifies the number of channels per socket. - * - * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - * Specifies DDR bus speed of channel ChannelID on socket SocketID. - * - * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - * Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - * - * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - * Byte6Seed, Byte7Seed, ByteEccSeed) - * Specifies the write leveling seed for a channel of a socket. - * - * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - * Byte6Seed, Byte7Seed, ByteEccSeed) - * Speicifes the HW RXEN training seed for a channel of a socket - */ - -#define SEED_WL 0x0E -WRITE_LEVELING_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL, - SEED_WL), - -#define SEED_A 0x12 -HW_RXEN_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, - SEED_A), - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS(LAYERS_6), - - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void OemPostParams(AMD_POST_PARAMS *PostParams) -{ - /* Add the memory configuration table needed for soldered down memory */ - PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration; -} diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl deleted file mode 100644 index 87b0d2169d..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl b/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl deleted file mode 100644 index 4a3eac89a3..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No IDE functionality */ diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl b/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl deleted file mode 100644 index 68609d868e..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl b/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl deleted file mode 100644 index 1fb4c1dfdf..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/si.asl b/src/mainboard/amd/db-ft3b-lc/acpi/si.asl deleted file mode 100644 index 292347127e..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/si.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl b/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl deleted file mode 100644 index 0734c8e3c8..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* clear USB wake up signal */ - Store(1, USBS) - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl b/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl deleted file mode 100644 index 73077ac4d3..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No thermal zone functionality */ diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl b/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl deleted file mode 100644 index 4ebb4b64a6..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c b/src/mainboard/amd/db-ft3b-lc/acpi_tables.c deleted file mode 100644 index 20509e9d31..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/db-ft3b-lc/board_info.txt b/src/mainboard/amd/db-ft3b-lc/board_info.txt deleted file mode 100644 index 5854f86515..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Board name: DB-FT3b-LC -Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/db-ft3-lc.htm -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/amd/db-ft3b-lc/cmos.layout b/src/mainboard/amd/db-ft3b-lc/cmos.layout deleted file mode 100644 index e1dbd9a3dd..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/db-ft3b-lc/devicetree.cb b/src/mainboard/amd/db-ft3b-lc/devicetree.cb deleted file mode 100644 index dfbe3e27d7..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/devicetree.cb +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# Copyright (C) 2015 Kyösti Mälkki -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 off end # Edge Connector - device pci 2.5 off end # Edge Connector - device pci 8.0 off end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 - - chip southbridge/amd/pi/hudson - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI #0 - device pci 13.0 on end # EHCI #1 - device pci 14.0 on end # SMBus - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # EHCI #2 - register "sd_mode" = "3" - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/amd/db-ft3b-lc/dsdt.asl b/src/mainboard/amd/db-ft3b-lc/dsdt.asl deleted file mode 100644 index f1ff974b49..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include - - /* Describe the processor tree (\_PR) */ - #include - - /* Contains the supported sleep states for this chipset */ - #include - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/db-ft3b-lc/irq_tables.c b/src/mainboard/amd/db-ft3b-lc/irq_tables.c deleted file mode 100644 index 465b3643d4..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c deleted file mode 100644 index a3396593f4..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/mainboard.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - */ -static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ - [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* SATA */ - [0x41] = 0x0F, -}; - -static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, - /* SATA */ - [0x41] = 0x13, -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ - {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ - {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c deleted file mode 100644 index 40a75ad1e1..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c deleted file mode 100644 index 77250c2259..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void romstage_main_template(void) -{ - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - pm_io_write8(0xd2, 0); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - pm_io_write8(0xea, 1); -} From 3002eb42ed5e844ac6e3967ca0f66e3ae1a9e74d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 10 Mar 2020 21:33:57 +0100 Subject: [PATCH 0382/1463] mb/amd/bettong: Drop unmaintained ROMCC board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: I1bce09ba5041a6636f900de611846467653f35a9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/mainboard/amd/bettong/BiosCallOuts.c | 160 ------------ src/mainboard/amd/bettong/BiosCallOuts.h | 46 ---- src/mainboard/amd/bettong/Kconfig | 60 ----- src/mainboard/amd/bettong/Kconfig.name | 3 - src/mainboard/amd/bettong/Makefile.inc | 23 -- src/mainboard/amd/bettong/OemCustomize.c | 154 ----------- src/mainboard/amd/bettong/README | 25 -- .../amd/bettong/acpi/carrizo_fch.asl | 97 ------- src/mainboard/amd/bettong/acpi/gpe.asl | 74 ------ src/mainboard/amd/bettong/acpi/mainboard.asl | 28 -- src/mainboard/amd/bettong/acpi/routing.asl | 247 ------------------ src/mainboard/amd/bettong/acpi/sleep.asl | 86 ------ src/mainboard/amd/bettong/acpi/usb_oc.asl | 129 --------- src/mainboard/amd/bettong/acpi_tables.c | 48 ---- src/mainboard/amd/bettong/board_info.txt | 1 - src/mainboard/amd/bettong/boardid.c | 48 ---- src/mainboard/amd/bettong/cmos.layout | 101 ------- src/mainboard/amd/bettong/devicetree.cb | 67 ----- src/mainboard/amd/bettong/dsdt.asl | 84 ------ src/mainboard/amd/bettong/fchec.c | 63 ----- src/mainboard/amd/bettong/irq_tables.c | 100 ------- src/mainboard/amd/bettong/mainboard.c | 91 ------- src/mainboard/amd/bettong/mptable.c | 157 ----------- src/mainboard/amd/bettong/romstage.c | 50 ---- 24 files changed, 1942 deletions(-) delete mode 100644 src/mainboard/amd/bettong/BiosCallOuts.c delete mode 100644 src/mainboard/amd/bettong/BiosCallOuts.h delete mode 100644 src/mainboard/amd/bettong/Kconfig delete mode 100644 src/mainboard/amd/bettong/Kconfig.name delete mode 100644 src/mainboard/amd/bettong/Makefile.inc delete mode 100644 src/mainboard/amd/bettong/OemCustomize.c delete mode 100644 src/mainboard/amd/bettong/README delete mode 100644 src/mainboard/amd/bettong/acpi/carrizo_fch.asl delete mode 100644 src/mainboard/amd/bettong/acpi/gpe.asl delete mode 100644 src/mainboard/amd/bettong/acpi/mainboard.asl delete mode 100644 src/mainboard/amd/bettong/acpi/routing.asl delete mode 100644 src/mainboard/amd/bettong/acpi/sleep.asl delete mode 100644 src/mainboard/amd/bettong/acpi/usb_oc.asl delete mode 100644 src/mainboard/amd/bettong/acpi_tables.c delete mode 100644 src/mainboard/amd/bettong/board_info.txt delete mode 100644 src/mainboard/amd/bettong/boardid.c delete mode 100644 src/mainboard/amd/bettong/cmos.layout delete mode 100644 src/mainboard/amd/bettong/devicetree.cb delete mode 100644 src/mainboard/amd/bettong/dsdt.asl delete mode 100644 src/mainboard/amd/bettong/fchec.c delete mode 100644 src/mainboard/amd/bettong/irq_tables.c delete mode 100644 src/mainboard/amd/bettong/mainboard.c delete mode 100644 src/mainboard/amd/bettong/mptable.c delete mode 100644 src/mainboard/amd/bettong/romstage.c diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c deleted file mode 100644 index 22a8403119..0000000000 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "imc.h" -#include "hudson.h" - -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); -static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_READ_SPD, board_ReadSpd }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -static const GPIO_CONTROL oem_bettong_gpio[] = { - {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, - {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, - {-1} -}; - -/* Bettong Hardware Monitor Fan Control - * Hardware limitation: - * HWM will fail to read the input temperature via I2C if other - * software switches the I2C address. AMD recommends using IMC - * to control fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control. the recommand way */ - imc_reg_init(); - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - memset(&FchParams->Imc.EcStruct, 0, sizeof(FCH_EC)); -} - -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such as Azalia, SATA, IMC etc. - */ -AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - - FchParams_reset->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams_reset->FchReset.Xhci1Enable = FALSE; - FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - if (CONFIG(HUDSON_IMC_FWM)) - oem_fan_control(FchParams_env); - - /* XHCI configuration */ - if (CONFIG(HUDSON_XHCI_ENABLE)) - FchParams_env->Usb.Xhci0Enable = TRUE; - else - FchParams_env->Usb.Xhci0Enable = FALSE; - - FchParams_env->Usb.Xhci1Enable = FALSE; - FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is irremovable. */ - - /* sata configuration */ - /* SD configuration */ - /* Rev F has an on-board eMMC, which only supports SD 2.0 */ - if (board_id() == 'F') { - FchParams_env->Sd.SdConfig = SdVer2; - } - } - printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; -} - -static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - int spdAddress; - - if (!ENV_ROMSTAGE) - return AGESA_UNSUPPORTED; - - DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); - - if (dev == NULL) - return AGESA_ERROR; - - DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; - - if (config == NULL) - return AGESA_ERROR; - - UINT8 spdAddrLookup_rev_F [2][2][4]= { - { {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */ - { {0x00, 0x00}, {0x00, 0x00}, }, /* socket 1 - Channel 0 & 1 - 8-bit SPD addresses */ - }; - - if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) - return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) - return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) - return AGESA_ERROR; - if (board_id() == 'F') - spdAddress = spdAddrLookup_rev_F - [info->SocketId] [info->MemChannelId] [info->DimmId]; - else - spdAddress = config->spdAddrLookup - [info->SocketId] [info->MemChannelId] [info->DimmId]; - - if (spdAddress == 0) - return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); - if (err) - return AGESA_ERROR; - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/bettong/BiosCallOuts.h b/src/mainboard/amd/bettong/BiosCallOuts.h deleted file mode 100644 index 8c2a047099..0000000000 --- a/src/mainboard/amd/bettong/BiosCallOuts.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig deleted file mode 100644 index 4617360ea1..0000000000 --- a/src/mainboard/amd/bettong/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_BETTONG - def_bool n - -if BOARD_AMD_BETTONG - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK - select CPU_AMD_PI_00660F01 - select NORTHBRIDGE_AMD_PI_00660F01 - select SOUTHBRIDGE_AMD_PI_KERN - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/bettong" - -config MAINBOARD_PART_NUMBER - string - default "FP4" - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_BETTONG diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name deleted file mode 100644 index 4bd13291cd..0000000000 --- a/src/mainboard/amd/bettong/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -# Disabled -#config BOARD_AMD_BETTONG -# bool "Bettong" diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc deleted file mode 100644 index cfcc9c0744..0000000000 --- a/src/mainboard/amd/bettong/Makefile.inc +++ /dev/null @@ -1,23 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c -romstage-y += boardid.c - -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c -ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c -ramstage-y += boardid.c diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c deleted file mode 100644 index 0e7882fb2e..0000000000 --- a/src/mainboard/amd/bettong/OemCustomize.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 3, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x06, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ - { - DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x07, 0) - }, - -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 */ - { - 0, /*DESCRIPTOR_TERMINATE_LIST, */ - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This is the stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { - DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MOTHER_BOARD_LAYERS(LAYERS_6), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), - PSO_END -}; - -void OemPostParams(AMD_POST_PARAMS *PostParams) -{ - if (board_id() == 'F') { - PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; - } -} diff --git a/src/mainboard/amd/bettong/README b/src/mainboard/amd/bettong/README deleted file mode 100644 index 631cf0f0ef..0000000000 --- a/src/mainboard/amd/bettong/README +++ /dev/null @@ -1,25 +0,0 @@ -coreboot is changing all the time and the patches are reabsed when pushed to -community, so it is a little difficult to provide stable Bettong code. -From now on, AMD provides source code which is validated by QA team. -The code is pushed to github https://github.com/BTDC/coreboot -The version is identified by a tag. All the changes will be pushed to coreboot -community. - -===== -Version: TCMEF1F0 Release Date: 09/29/2015 - -Changes from last version: -1. Fix external graphics issue. -2. Add board ID support. -3. Support DDR4. -4. Support SD 2.0. -5. Fix Windows 7 S4 issue. -6. Add GPIO, I2C and UART support. -7. Fix the interrupt routine. -8. Restruct PCI interrupt table (C00/C01). -9. Fix DSDT issue. -10. Fix the PCIe lane map. -11. Lower the TOM to give more MMIO space. -12. Add USB device. -13. Set the USB3 port as irremovable. -14. Update AGESA to CarrizoPI 1.1.0.1. diff --git a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl deleted file mode 100644 index 79f54203d2..0000000000 --- a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device(GPIO) { - Name (_HID, "AMD0030") - Name (_CID, "AMD0030") - Name(_UID, 0) - - Method (_CRS, 0x0, NotSerialized) { - Name (RBUF, ResourceTemplate () { - // - // Interrupt resource. In this example, banks 0 & 1 share the same - // interrupt to the parent controller and similarly banks 2 & 3. - // - // N.B. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform - // - Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} - - // - // Memory resource. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform. - // - Memory32Fixed(ReadWrite, 0xFED81500, 0x300) - }) - - Return (RBUF) - } - - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(FUR0) { - Name(_HID,"AMD0020") - Name(_UID,0x0) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {10} - Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000) - }) - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(FUR1) { - Name(_HID,"AMD0020") - Name(_UID,0x1) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {11} - Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000) - }) - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(I2CA) { - Name(_HID,"AMD0010") - Name(_UID,0x0) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {3} - Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) - }) - - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(I2CB) -{ - Name(_HID,"AMD0010") - Name(_UID,0x1) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {15} - Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000) - }) - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} diff --git a/src/mainboard/amd/bettong/acpi/gpe.asl b/src/mainboard/amd/bettong/acpi/gpe.asl deleted file mode 100644 index 87b0d2169d..0000000000 --- a/src/mainboard/amd/bettong/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/bettong/acpi/mainboard.asl b/src/mainboard/amd/bettong/acpi/mainboard.asl deleted file mode 100644 index db5731f088..0000000000 --- a/src/mainboard/amd/bettong/acpi/mainboard.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/bettong/acpi/routing.asl b/src/mainboard/amd/bettong/acpi/routing.asl deleted file mode 100644 index 0c4edbbee9..0000000000 --- a/src/mainboard/amd/bettong/acpi/routing.asl +++ /dev/null @@ -1,247 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 43 }, - Package(){0x0001FFFF, 1, 0, 40 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 44 }, - Package(){0x0002FFFF, 1, 0, 45 }, - Package(){0x0002FFFF, 2, 0, 46 }, - Package(){0x0002FFFF, 3, 0, 47 }, - - Package(){0x0003FFFF, 0, 0, 49 }, - Package(){0x0003FFFF, 1, 0, 50 }, - Package(){0x0003FFFF, 2, 0, 51 }, - Package(){0x0003FFFF, 3, 0, 52 }, - - Package(){0x0008FFFF, 0, 0, 35 }, - Package(){0x0008FFFF, 1, 0, 32 }, - Package(){0x0008FFFF, 2, 0, 33 }, - Package(){0x0008FFFF, 3, 0, 34 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 18}, - Package(){0x0010FFFF, 1, 0, 17}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 9, Func 2 - HDAudio */ - Package(){0x0009FFFF, 0, 0, 39 }, - Package(){0x0009FFFF, 1, 0, 36 }, - Package(){0x0009FFFF, 2, 0, 37 }, - Package(){0x0009FFFF, 3, 0, 38 }, -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) - -/* GFX 2 */ -Name(PSA, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APSA, Package(){ - Package(){0x0000FFFF, 0, 0, 52 }, - Package(){0x0000FFFF, 1, 0, 53 }, - Package(){0x0000FFFF, 2, 0, 54 }, - Package(){0x0000FFFF, 3, 0, 55 }, -}) - -/* GFX 3 */ -Name(PSB, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APSB, Package(){ - Package(){0x0000FFFF, 0, 0, 27 }, - Package(){0x0000FFFF, 1, 0, 24 }, - Package(){0x0000FFFF, 2, 0, 25 }, - Package(){0x0000FFFF, 3, 0, 26 }, -}) - -/* GFX 4 */ -Name(PSC, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APSC, Package(){ - Package(){0x0000FFFF, 0, 0, 31 }, - Package(){0x0000FFFF, 1, 0, 28 }, - Package(){0x0000FFFF, 2, 0, 29 }, - Package(){0x0000FFFF, 3, 0, 30 }, -}) diff --git a/src/mainboard/amd/bettong/acpi/sleep.asl b/src/mainboard/amd/bettong/acpi/sleep.asl deleted file mode 100644 index 58f0752f30..0000000000 --- a/src/mainboard/amd/bettong/acpi/sleep.asl +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, PEWD) - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/bettong/acpi/usb_oc.asl b/src/mainboard/amd/bettong/acpi/usb_oc.asl deleted file mode 100644 index 328883af91..0000000000 --- a/src/mainboard/amd/bettong/acpi/usb_oc.asl +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update for Bettong */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif diff --git a/src/mainboard/amd/bettong/acpi_tables.c b/src/mainboard/amd/bettong/acpi_tables.c deleted file mode 100644 index 9117c1ffdf..0000000000 --- a/src/mainboard/amd/bettong/acpi_tables.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define IO_APIC2_ADDR 0xFEC20000 - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Kern IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - IO_APIC2_ADDR, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/bettong/board_info.txt b/src/mainboard/amd/bettong/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/amd/bettong/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c deleted file mode 100644 index 21d0476204..0000000000 --- a/src/mainboard/amd/bettong/boardid.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/** - *Bettong uses 3 GPIO(5-7) pins to identify board. - *The GPIO ports are mapped to MMIO space. - *The GPIO value and board version are mapped as follow: - *GPIO5 GPIO6 GPIO7 Version - * 0 0 0 A - * 0 0 1 B - * ...... - * 1 1 1 H - */ -uint32_t board_id(void) -{ - u8 value = 0; - u8 boardrev = 0; - char boardid; - - value = gpio0_read8((7 << 2) + 2); /* agpio7: board_id2 */ - boardrev = value & 1; - value = gpio0_read8((6 << 2) + 2); /* agpio6: board_id1 */ - boardrev |= (value & 1) << 1; - value = gpio0_read8((5 << 2) + 2); /* agpio5: board_id0 */ - boardrev |= (value & 1) << 2; - - boardid = 'A' + boardrev; - - return boardid; -} diff --git a/src/mainboard/amd/bettong/cmos.layout b/src/mainboard/amd/bettong/cmos.layout deleted file mode 100644 index 49878e25b1..0000000000 --- a/src/mainboard/amd/bettong/cmos.layout +++ /dev/null @@ -1,101 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -386 1 e 1 ECC_memory -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb deleted file mode 100644 index c447bcad95..0000000000 --- a/src/mainboard/amd/bettong/devicetree.cb +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/pi/00660F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00660F01 - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - - chip northbridge/amd/pi/00660F01 - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - device pci 3.0 on end # Edge Connector - device pci 3.1 on end # Edge Connector - end #chip northbridge/amd/pi/00660F01 - - chip southbridge/amd/pi/hudson - device pci 9.0 on end # HDA - device pci 9.2 on end # HDA - device pci 10.0 on end # USB - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 14.0 on end # SM - #device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/pi/hudson - - chip northbridge/amd/pi/00660F01 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/pi/00660F01/root_complex diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl deleted file mode 100644 index f6449ece99..0000000000 --- a/src/mainboard/amd/bettong/dsdt.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include - - /* Describe the processor tree (\_PR) */ - #include - - /* Contains the supported sleep states for this chipset */ - #include - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include - - /* Describe the devices in the Southbridge */ - #include "acpi/carrizo_fch.asl" - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/bettong/fchec.c b/src/mainboard/amd/bettong/fchec.c deleted file mode 100644 index ea7dc569c7..0000000000 --- a/src/mainboard/amd/bettong/fchec.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "fchec.h" - -void agesawrapper_fchecfancontrolservice() -{ - FCH_DATA_BLOCK LateParams; - - /* Thermal Zone Parameter */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111; - - FchECfancontrolservice(&LateParams); -} diff --git a/src/mainboard/amd/bettong/irq_tables.c b/src/mainboard/amd/bettong/irq_tables.c deleted file mode 100644 index 7334bb2fd8..0000000000 --- a/src/mainboard/amd/bettong/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c deleted file mode 100644 index 8e2ecfd8e1..0000000000 --- a/src/mainboard/amd/bettong/mainboard.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - */ -static const u8 mainboard_picr_data[] = { - [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F, - [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, - [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, - [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05, - [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, - [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, - [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, - [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, -}; - -static const u8 mainboard_intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, - [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00, - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, - [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00, - [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, - [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00, - [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00, - [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, - [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - - - -/************************************************* - * enable the dedicated function in bettong board. - *************************************************/ -static void bettong_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = bettong_enable, -}; diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c deleted file mode 100644 index d9632d58d1..0000000000 --- a/src/mainboard/amd/bettong/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c deleted file mode 100644 index 0f41f714e3..0000000000 --- a/src/mainboard/amd/bettong/romstage.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* Mask BIST bit 31. One result of Silicon Observation - * report_bist_failure(bist & 0x7FFFFFFF); - */ - -static void romstage_main_template(void) -{ - u32 val; - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - -#if CONFIG(HUDSON_UART) - configure_hudson_uart(); -#endif - post_code(0x31); - console_init(); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - /* After AMD_INIT_ENV -> move to ramstage ? */ - if (acpi_is_wakeup_s4()) { - outb(0xEE, PM_INDEX); - outb(0x8, PM_DATA); - } -} From 149620fdfd898052910f045b852f5baecd3d87ce Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 10 Mar 2020 21:33:07 +0100 Subject: [PATCH 0383/1463] mb/amd/olivehillplus: Drop unmaintained ROMCC board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Ie79637c992874bd06009ed9b3e9f470b44e749b7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39064 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../amd/olivehillplus/BiosCallOuts.c | 296 ------------------ src/mainboard/amd/olivehillplus/Kconfig | 60 ---- src/mainboard/amd/olivehillplus/Kconfig.name | 3 - src/mainboard/amd/olivehillplus/Makefile.inc | 20 -- .../amd/olivehillplus/OemCustomize.c | 121 ------- src/mainboard/amd/olivehillplus/acpi/gpe.asl | 74 ----- src/mainboard/amd/olivehillplus/acpi/ide.asl | 2 - .../amd/olivehillplus/acpi/mainboard.asl | 35 --- .../amd/olivehillplus/acpi/routing.asl | 194 ------------ src/mainboard/amd/olivehillplus/acpi/si.asl | 23 -- .../amd/olivehillplus/acpi/sleep.asl | 95 ------ .../amd/olivehillplus/acpi/thermal.asl | 2 - .../amd/olivehillplus/acpi/usb_oc.asl | 37 --- src/mainboard/amd/olivehillplus/acpi_tables.c | 46 --- .../amd/olivehillplus/board_info.txt | 6 - src/mainboard/amd/olivehillplus/cmos.layout | 66 ---- src/mainboard/amd/olivehillplus/devicetree.cb | 66 ---- src/mainboard/amd/olivehillplus/dsdt.asl | 88 ------ src/mainboard/amd/olivehillplus/irq_tables.c | 100 ------ src/mainboard/amd/olivehillplus/mainboard.c | 32 -- src/mainboard/amd/olivehillplus/mptable.c | 186 ----------- src/mainboard/amd/olivehillplus/romstage.c | 68 ---- 22 files changed, 1620 deletions(-) delete mode 100644 src/mainboard/amd/olivehillplus/BiosCallOuts.c delete mode 100644 src/mainboard/amd/olivehillplus/Kconfig delete mode 100644 src/mainboard/amd/olivehillplus/Kconfig.name delete mode 100644 src/mainboard/amd/olivehillplus/Makefile.inc delete mode 100644 src/mainboard/amd/olivehillplus/OemCustomize.c delete mode 100644 src/mainboard/amd/olivehillplus/acpi/gpe.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi/ide.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi/mainboard.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi/routing.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi/si.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi/sleep.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi/thermal.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi/usb_oc.asl delete mode 100644 src/mainboard/amd/olivehillplus/acpi_tables.c delete mode 100644 src/mainboard/amd/olivehillplus/board_info.txt delete mode 100644 src/mainboard/amd/olivehillplus/cmos.layout delete mode 100644 src/mainboard/amd/olivehillplus/devicetree.cb delete mode 100644 src/mainboard/amd/olivehillplus/dsdt.asl delete mode 100644 src/mainboard/amd/olivehillplus/irq_tables.c delete mode 100644 src/mainboard/amd/olivehillplus/mainboard.c delete mode 100644 src/mainboard/amd/olivehillplus/mptable.c delete mode 100644 src/mainboard/amd/olivehillplus/romstage.c diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c deleted file mode 100644 index efb658a4e3..0000000000 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "imc.h" -#include "hudson.h" - -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * Realtek ALC272 CODEC Verb Table - */ -static const CODEC_ENTRY Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40251E05}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* - * Hardware Monitor Fan Control - * Hardware limitation: - * HWM will fail to read the input temperature via I2C if other - * software switches the I2C address. AMD recommends using IMC - * to control fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - FCH_HWM_FAN_CTR oem_factl[5] = { - /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* DB-FT3 FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* DB-FT3 FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - - /* Enable IMC fan control. the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. - * so we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, using the alternative method */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE; /* 1 enable, 0 disable TSI Auto Polling */ - } -} - -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* Azalia Controller OEM Codec Table Pointer */ - FchParams->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - /* Azalia Controller Front Panel OEM Table Pointer */ - - /* Fan Control */ - oem_fan_control(FchParams); - - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; - - /* sata configuration */ - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } - } - printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig deleted file mode 100644 index 907de3be03..0000000000 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_OLIVEHILLPLUS - def_bool n - -if BOARD_AMD_OLIVEHILLPLUS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK - select CPU_AMD_PI_00730F01 - select NORTHBRIDGE_AMD_PI_00730F01 - select SOUTHBRIDGE_AMD_PI_AVALON - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/olivehillplus" - -config MAINBOARD_PART_NUMBER - string - default "DB-FT3b" - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_OLIVEHILLPLUS diff --git a/src/mainboard/amd/olivehillplus/Kconfig.name b/src/mainboard/amd/olivehillplus/Kconfig.name deleted file mode 100644 index 1ce4a204b9..0000000000 --- a/src/mainboard/amd/olivehillplus/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -# Disabled -#config BOARD_AMD_OLIVEHILLPLUS -# bool "Olive Hill Plus" diff --git a/src/mainboard/amd/olivehillplus/Makefile.inc b/src/mainboard/amd/olivehillplus/Makefile.inc deleted file mode 100644 index 37c1dceead..0000000000 --- a/src/mainboard/amd/olivehillplus/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehillplus/OemCustomize.c b/src/mainboard/amd/olivehillplus/OemCustomize.c deleted file mode 100644 index 76b7f25522..0000000000 --- a/src/mainboard/amd/olivehillplus/OemCustomize.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} diff --git a/src/mainboard/amd/olivehillplus/acpi/gpe.asl b/src/mainboard/amd/olivehillplus/acpi/gpe.asl deleted file mode 100644 index 87b0d2169d..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehillplus/acpi/ide.asl b/src/mainboard/amd/olivehillplus/acpi/ide.asl deleted file mode 100644 index 4a3eac89a3..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/ide.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No IDE functionality */ diff --git a/src/mainboard/amd/olivehillplus/acpi/mainboard.asl b/src/mainboard/amd/olivehillplus/acpi/mainboard.asl deleted file mode 100644 index 68609d868e..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/mainboard.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/amd/olivehillplus/acpi/routing.asl b/src/mainboard/amd/olivehillplus/acpi/routing.asl deleted file mode 100644 index 1fb4c1dfdf..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/routing.asl +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/amd/olivehillplus/acpi/si.asl b/src/mainboard/amd/olivehillplus/acpi/si.asl deleted file mode 100644 index 292347127e..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/si.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/amd/olivehillplus/acpi/sleep.asl b/src/mainboard/amd/olivehillplus/acpi/sleep.asl deleted file mode 100644 index 0734c8e3c8..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/sleep.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* clear USB wake up signal */ - Store(1, USBS) - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/olivehillplus/acpi/thermal.asl b/src/mainboard/amd/olivehillplus/acpi/thermal.asl deleted file mode 100644 index 73077ac4d3..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/thermal.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No thermal zone functionality */ diff --git a/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl b/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl deleted file mode 100644 index 4ebb4b64a6..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/olivehillplus/acpi_tables.c b/src/mainboard/amd/olivehillplus/acpi_tables.c deleted file mode 100644 index 20509e9d31..0000000000 --- a/src/mainboard/amd/olivehillplus/acpi_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/olivehillplus/board_info.txt b/src/mainboard/amd/olivehillplus/board_info.txt deleted file mode 100644 index d2c6670225..0000000000 --- a/src/mainboard/amd/olivehillplus/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Board name: DB-FT3b (Olive Hill+) -Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/amd/olivehillplus/cmos.layout b/src/mainboard/amd/olivehillplus/cmos.layout deleted file mode 100644 index e1dbd9a3dd..0000000000 --- a/src/mainboard/amd/olivehillplus/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb deleted file mode 100644 index 9b59d99af5..0000000000 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 - - chip southbridge/amd/pi/hudson - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI #0 - device pci 13.0 on end # EHCI #1 - device pci 14.0 on end # SMBus - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # EHCI #2 - end #chip southbridge/amd/pi/hudson - - chip northbridge/amd/pi/00730F01 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl deleted file mode 100644 index f1ff974b49..0000000000 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include - - /* Describe the processor tree (\_PR) */ - #include - - /* Contains the supported sleep states for this chipset */ - #include - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/olivehillplus/irq_tables.c b/src/mainboard/amd/olivehillplus/irq_tables.c deleted file mode 100644 index 465b3643d4..0000000000 --- a/src/mainboard/amd/olivehillplus/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c deleted file mode 100644 index 1367b03307..0000000000 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c deleted file mode 100644 index 6c81d06cc5..0000000000 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c deleted file mode 100644 index 4d7db013ee..0000000000 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void romstage_main_template(void) -{ - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - pm_io_write8(0xd2, 0); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* - * This refers to LpcClkDrvSth settling time. Without this setting, processor - * initialization is slow or incorrect, so this wait has been replicated from - * earlier development boards. - */ - { - int i; - for (i = 0; i < 200000; i++) - inb(0xCD6); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - /* After AMD_INIT_ENV -> move to ramstage ? */ - pm_io_write8(0xea, 1); -} From e3a138669467f2511bdaf23eb78571dca5418556 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 11:36:33 +0100 Subject: [PATCH 0384/1463] mb/asus/am1i-a: Remove old reference to olivehillplus Change-Id: Idfb8c834ae63226546a4e2860d9b206ba0288718 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39078 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/asus/am1i-a/BiosCallOuts.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index a61a72230c..18ba5f6e9f 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -130,7 +130,6 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret); } - // code from olivehillplus (ft3b) - only place where sata is configured switch ((SATA_CLASS)FchParams_env->Sata.SataClass) { case SataLegacyIde: case SataRaid: From 9006df98c70cbee0e508fa7f79c1896be01ede84 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Feb 2020 11:37:33 +0100 Subject: [PATCH 0385/1463] mb/biostar/am1ml: Remove old reference to olivehillplus Change-Id: I219fb2c12bb865288364f6e48b1e3d64c14bc036 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39079 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/biostar/am1ml/BiosCallOuts.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 6181226c30..bb2f915fd2 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -108,7 +108,8 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ FchParams_env->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { // code from olivehillplus (ft3b) - only one place where sata is configured + + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { case SataLegacyIde: case SataRaid: case SataAhci: From fc59f0860b3b5d4a75927571a907141ec85a7e2f Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Wed, 11 Mar 2020 15:36:04 +0300 Subject: [PATCH 0386/1463] Documentation: Fix a typo filse -> files Change-Id: Iaf0c3a064b42dde70b1e01cfc15ad3187bf8bfcc Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/39449 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov --- Documentation/mainboard/lenovo/montevina_series.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index ab858a61e5..62e87969f9 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -27,7 +27,7 @@ First of all create a backup of your ROM with an external programmer: # flashrom -p YOUR_PROGRAMMER -r backup.rom ``` -Then, split the IFD regions into separate filse with ifdtool. You will need +Then, split the IFD regions into separate files with ifdtool. You will need `flashregion_3_gbe.bin` later. ```console $ ifdtool -x backup.rom From 2bd2be545f39db24b6174d57b503d42eddab9371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 3 Mar 2020 20:47:01 +0100 Subject: [PATCH 0387/1463] soc/intel/common/block: tco: enable intruder SMI if selected MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set TCO to issue an SMI when the case instrusion switch gets pressed. The SMI is controlled along with the general TCO SMI Kconfig. Tested on X11SSM-F. Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39264 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/smbus/tco.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index bd8790aa6e..2c0b760481 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -96,6 +97,18 @@ static void tco_timer_disable(void) tco_write_reg(TCO1_CNT, tcocnt); } +/* Enable and initialize TCO intruder SMI */ +static void tco_intruder_smi_enable(void) +{ + uint16_t tcocnt; + + /* Make TCO issue an SMI on INTRD_DET assertion */ + tcocnt = tco_read_reg(TCO2_CNT); + tcocnt &= ~TCO_INTRD_SEL_MASK; + tcocnt |= TCO_INTRD_SEL_SMI; + tco_write_reg(TCO2_CNT, tcocnt); +} + /* Enable TCO BAR using SMBUS TCO base to access TCO related register */ static void tco_enable_bar(void) { @@ -137,4 +150,8 @@ void tco_configure(void) tco_enable_bar(); tco_timer_disable(); + + /* Enable intruder interrupt if TCO interrupts are enabled*/ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)) + tco_intruder_smi_enable(); } From 66815114cf518fa57e8003ed7bf4ff6dceebe90e Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 9 Mar 2020 14:48:51 -0700 Subject: [PATCH 0388/1463] mb/intel/tglrvp: sync up variant folders with latest up3 During intial UP4 patch, below UP3 patches merged which should be applied for UP4. https://review.coreboot.org/c/coreboot/+/39201 https://review.coreboot.org/c/coreboot/+/39229 Merge these patches to UP4 BUG=none BRANCH=none TEST=Build TGL UP4 Signed-off-by: Wonkyu Kim Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Srinidhi N Kaushik Reviewed-by: Shaunak Saha --- .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 1 + .../intel/tglrvp/variants/tglrvp_up4/gpio.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index a3539aa937..1f05e0ee46 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -48,6 +48,7 @@ chip soc/intel/tigerlake # enabling EDP in PortA register "DdiPortAConfig" = "1" + register "DdiPortBHpd" = "1" register "DdiPort1Hpd" = "1" register "DdiPort1Ddc" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index cc810aa1fc..2f952d2188 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -24,6 +24,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* Camera */ + PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ PAD_CFG_GPO(GPP_B23, 0, PLTRST), PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_E22, 0, PLTRST), @@ -83,6 +87,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + /* DP */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ }; const struct pad_config *variant_gpio_table(size_t *num) From 04e0712f46d15e22d640badc7cb96582c3a3fc27 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 9 Mar 2020 18:16:48 +0100 Subject: [PATCH 0389/1463] Treewide: Add some gcc's warning options Change-Id: I789c8906542c59477b0037d39e7aa4fb2dcf22c0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39406 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile.inc b/Makefile.inc index f172005c7f..43b29c73cc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -421,6 +421,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla +CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) From 0965044c99162b27e8c7ca01e4e14ccecd882c1b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 9 Mar 2020 19:56:59 +0100 Subject: [PATCH 0390/1463] commonlib/cbfs.c: Remove unused macro Change-Id: I330de4357fa48ee3d76a97a682b389ef42e7a135 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39410 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/commonlib/cbfs.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index be0de9f6aa..b03a3dcd3a 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -18,9 +18,6 @@ #include #include -#if !defined(ERROR) -#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -#endif #if !defined(LOG) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) #endif From a53dbd4780b2b19b06756f7c119f8c315fca4a58 Mon Sep 17 00:00:00 2001 From: Alex Levin Date: Mon, 9 Mar 2020 16:52:59 -0700 Subject: [PATCH 0391/1463] mb/google/volteer: Disable WWAN PCIe Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer. BUG=b:146226689 BRANCH=none TEST=lsusb shows WWAN device Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/baseboard/devicetree.cb | 8 ++------ src/mainboard/google/volteer/variants/baseboard/gpio.c | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index dd6895b131..b08ff7d5c9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -56,12 +56,8 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" - # Enable WWAN PCIE 6 using clk 2 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcUsage[2]" = "5" - register "PcieClkSrcClkReq[2]" = "2" - # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality + register "PcieClkSrcUsage[2]" = "0xFF" register "PcieClkSrcUsage[4]" = "0xFF" register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[6]" = "0xFF" @@ -309,7 +305,7 @@ chip soc/intel/tigerlake device pci 1c.2 off end # RP3 0xA0BA device pci 1c.3 off end # RP4 0xA0BB device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 on end # WWAN RP6 0xA0BD + device pci 1c.5 off end # WWAN RP6 0xA0BD device pci 1c.6 on end # RP7 0xA0BE device pci 1c.7 on end # SD Card RP8 0xA0BF diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index f6dbed0bee..da3e5423bf 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -170,7 +170,7 @@ static const struct pad_config gpio_table[] = { /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ From 840bef061fca0ee40619e43e75ab073e9dab2d0a Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 9 Mar 2020 11:02:26 -0600 Subject: [PATCH 0392/1463] soc/intel/tigerlake: Fix stale device pointer usage TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39405 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Furquan Shaikh Reviewed-by: Nick Vaccaro Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/fsp_params_jsl.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 6cb3b6718d..96aa7ba016 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -143,7 +143,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* SDCard related configuration */ - params->ScsSdCardEnabled = pcidev_path_on_root(PCH_DEVFN_SDCARD) ? dev->enabled : 0; + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (!dev) + params->ScsSdCardEnabled = 0; + else + params->ScsSdCardEnabled = dev->enabled; params->Device4Enable = config->Device4Enable; From 35d78437991a60882f52dcfe0f653966f10041ff Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Wed, 4 Mar 2020 19:03:47 +0530 Subject: [PATCH 0393/1463] soc/intel/tigerlake: Correct FSP log interface select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly. BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/chip.h | 6 ++++++ src/soc/intel/tigerlake/romstage/fsp_params_jsl.c | 12 +++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d2ea0ddd2f..d23148aac8 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -193,6 +193,12 @@ struct soc_intel_tigerlake_config { */ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * TraceHubMode config + * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode + */ + uint8_t TraceHubMode; + /* Debug interface selection */ enum { DEBUG_INTERFACE_RAM = (1 << 0), diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 9c70f2ece1..a5c4c907e2 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -69,8 +69,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Set CPU Ratio */ m_cfg->CpuRatio = 0; + + /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); From c34bb3807c9318742d7a1224a38bf03fda0c1723 Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Wed, 15 Jan 2020 10:13:26 -0800 Subject: [PATCH 0394/1463] mb/google/volteer: Enable pcie rp11 for optane Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk related pins. Configuring pciecontroller3 to be set from 2x2. This will by done by auto detecting optane memory: enabling HybridStorageMode. BUG=b:148604250 BRANCH=chromeos TEST='Build, boot and look for two NVMe devices with lspci on Volteer' Cq-Depend: chrome-internal:2501837 Signed-off-by: Venkata Krishna Nimmagadda Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628 Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428 Tested-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Wonkyu Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420 Reviewed-by: Wonkyu Kim Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- .../google/volteer/variants/baseboard/devicetree.cb | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b08ff7d5c9..a65e5f1be8 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -46,6 +46,10 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + # Enable Optane PCIE 11 using clk 0 + register "PcieRpEnable[10]" = "1" + register "HybridStorageMode" = "1" + # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" @@ -311,7 +315,7 @@ chip soc/intel/tigerlake device pci 1d.0 on end # RP9 0xA0B0 device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1d.4 off end # RP13 0xA0B4 device pci 1d.5 off end # RP14 0xA0B5 From 6bc471461beb49ae0d489268cec799cb48d807a1 Mon Sep 17 00:00:00 2001 From: raymondchung Date: Wed, 4 Mar 2020 10:59:36 +0800 Subject: [PATCH 0395/1463] mb/google/hatch: Add LP_4G_2133 SPD Add LPDDR3 4GB 2133MHz SPD file. BUG=b:149226871 TEST=Build and check cbfs has the spd.bin Change-Id: I1598774a87eecc76082286540beadaa3c26eda69 Signed-off-by: Raymond Chung Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271 Reviewed-by: Shelley Chen Reviewed-by: Philip Chen Tested-by: build bot (Jenkins) --- .../google/hatch/spd/LP_4G_2133.spd.hex | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex diff --git a/src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex b/src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex new file mode 100644 index 0000000000..fc7b9c866d --- /dev/null +++ b/src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex @@ -0,0 +1,32 @@ +24 20 0F 0E 15 19 01 08 00 00 00 0B 03 03 00 00 +00 00 08 FF D4 01 00 00 78 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 08 7F C2 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From fe2a4c1001dcb92947616213855feccf4495e479 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Mon, 9 Mar 2020 12:56:30 +0530 Subject: [PATCH 0396/1463] =?UTF-8?q?mb/google/drallion/variants/drallion:?= =?UTF-8?q?=20Set=20PCH=20Thermal=20Trip=20point=20to=2077=C2=B0C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion. Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Bora Guvendik --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d0006d64d7..60be8c9fab 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -175,6 +175,9 @@ chip soc/intel/cannonlake register "tcc_offset" = "1" + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { From a02f00e5d6aa8693bfd4a8c66b89c85539555329 Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Tue, 5 Nov 2019 19:19:29 -0800 Subject: [PATCH 0397/1463] soc/intel/tigerlake: Save DIMM info by available nodes TEST=Verified that dmidecode produces output identical to private repo Signed-off-by: Jamie Ryu Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39359 Reviewed-by: Furquan Shaikh Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/romstage.c | 73 +++++++++++---------- 1 file changed, 40 insertions(+), 33 deletions(-) diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 17efc98fac..f592bb0574 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -37,22 +37,23 @@ /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { - int channel, dimm, dimm_max, index; + int node, channel, dimm, dimm_max, index; size_t hob_size; const CONTROLLER_INFO *ctrlr_info; const CHANNEL_INFO *channel_info; const DIMM_INFO *src_dimm; struct dimm_info *dest_dimm; struct memory_info *mem_info; - const MEMORY_INFO_DATA_HOB *memory_info_hob; + const MEMORY_INFO_DATA_HOB *meminfo_hob; const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; /* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = fsp_find_extension_hob_by_guid( + meminfo_hob = fsp_find_extension_hob_by_guid( smbios_memory_info_guid, &hob_size); - if (memory_info_hob == NULL || hob_size == 0) { + if (meminfo_hob == NULL || hob_size == 0) { printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; } @@ -68,40 +69,46 @@ static void save_dimm_info(void) } memset(mem_info, 0, sizeof(*mem_info)); - /* Describe the first N DIMMs in the system */ + /* Save available DIMM information */ index = 0; dimm_max = ARRAY_SIZE(mem_info->dimm); - ctrlr_info = &memory_info_hob->Controller[0]; - for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { - channel_info = &ctrlr_info->ChannelInfo[channel]; - if (channel_info->Status != CHANNEL_PRESENT) - continue; - for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { - src_dimm = &channel_info->DimmInfo[dimm]; - dest_dimm = &mem_info->dimm[index]; - - if (src_dimm->Status != DIMM_PRESENT) + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; + channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) continue; - u8 memProfNum = memory_info_hob->MemoryProfile; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; + dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; - /* Populate the DIMM information */ - dimm_info_fill(dest_dimm, - src_dimm->DimmCapacity, - memory_info_hob->MemoryType, - memory_info_hob->ConfiguredMemoryClockSpeed, - src_dimm->RankInDimm, - channel_info->ChannelId, - src_dimm->DimmId, - (const char *)src_dimm->ModulePartNum, - sizeof(src_dimm->ModulePartNum), - src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth, - memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport, - src_dimm->MfgId, - src_dimm->SpdModuleType); - index++; + u8 memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } } } mem_info->dimm_cnt = index; From 6dc488a6781e4b0ecd0d4cb963d40709f17df0ef Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 28 Feb 2020 10:38:55 +0100 Subject: [PATCH 0398/1463] drivers/intel/gma/acpi: Prevent DivideByZero error In case backlight control isn't enabled BCLM is zero. Return early instead of running into a DivideByZero error. This happens on devices that don't have backlight control, like desktops and servers. The proper fix is to not include those ACPI methods, but that requires a much bigger refactoring. Change-Id: Ie9bdb00949d6d44fd99321db556d6008d2d12a7f Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39158 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/intel/gma/acpi/configure_brightness_levels.asl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 3ec74119f1..21f0b2318e 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -122,6 +122,11 @@ /* Find value closest to BCLV in BRIG (which must be ordered) */ Method (XBQC, 0, NotSerialized) { + /* Prevent DivideByZero if backlight control isn't enabled */ + If (BCLM == 0) + { + Return (Zero) + } /* Local0: current percentage */ Store (DRCL (Multiply (BCLV, 100), BCLM), Local0) From cb858d6d6287d0e5e15583a1ff53f77ffea730bc Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 13 Feb 2020 14:24:16 +0100 Subject: [PATCH 0399/1463] superio/nuvoton/nct5539d: Update documentation and remove DSDT There seems to be no board using this, but some currently under review. Remove the DSDT, which doesn't work together with the SSDT ACPI code generation. Also update the documentation pointing to the SSDT generator. Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- Documentation/superio/index.md | 1 + Documentation/superio/nuvoton/nct5539d.md | 9 + src/superio/nuvoton/nct5539d/acpi/superio.asl | 157 ------------------ 3 files changed, 10 insertions(+), 157 deletions(-) create mode 100644 Documentation/superio/nuvoton/nct5539d.md delete mode 100644 src/superio/nuvoton/nct5539d/acpi/superio.asl diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index 053663b215..81287bb108 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -5,6 +5,7 @@ This section contains documentation about coreboot on specific SuperIOs. ## Nuvoton - [NPCD378](nuvoton/npcd378.md) +- [NCT5539D](nuvoton/nct5539d.md) ## Common - [PNP devices](common/pnp.md) diff --git a/Documentation/superio/nuvoton/nct5539d.md b/Documentation/superio/nuvoton/nct5539d.md new file mode 100644 index 0000000000..e91ebc3abb --- /dev/null +++ b/Documentation/superio/nuvoton/nct5539d.md @@ -0,0 +1,9 @@ +# NCT5539D SuperIO + +The SuperIO has the ID `0xd121` and the source can be found in +`src/superio/nuvoton/nct5539d/`. + +## For developers + +The SuperIO generates ACPI using the +[SSDT generator for generic SuperIOs](../common/ssdt.md). diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl deleted file mode 100644 index 6f494210fc..0000000000 --- a/src/superio/nuvoton/nct5539d/acpi/superio.asl +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* - * Include this file into a mainboard's DSDT _SB device tree and it will - * expose the NCT5539D SuperIO and some of its functionality. - * - * It allows the change of IO ports, IRQs and DMA settings on logical - * devices, disabling and reenabling logical devices. - * - * LDN State - * 0x2 SP1 Implemented, untested - * 0x5 KBC Implemented, untested - * 0x8 GPIO Implemented, untested - * 0xb HWM Implemented, untested - * - * Controllable through preprocessor defines: - * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) - * SUPERIO_PNP_BASE I/O address of the first PnP configuration register - * NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed. - * NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed. - * NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed. - * NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed. - */ - -#undef SUPERIO_CHIP_NAME -#define SUPERIO_CHIP_NAME NCT5539D -#include - -#undef PNP_DEFAULT_PSC -#define PNP_DEFAULT_PSC Return (0) /* no power management */ - -Device(SUPERIO_DEV) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("Nuvoton NCT5539D Super I/O")) - Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) - - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - PNP_ADDR_REG, 8, - PNP_DATA_REG, 8, - } - IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ - - Offset (0x30), - PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ - ACT1, 1, /* Logical device activation */ - ACT2, 1, /* Logical device activation */ - ACT3, 1, /* Logical device activation */ - ACT4, 1, /* Logical device activation */ - ACT5, 1, /* Logical device activation */ - ACT6, 1, /* Logical device activation */ - ACT7, 1, /* Logical device activation */ - - Offset (0x60), - PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ - PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ - Offset (0x62), - PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ - PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ - Offset (0x64), - PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ - PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ - - Offset (0x70), - PNP_IRQ0, 8, /* First IRQ */ - Offset (0x72), - PNP_IRQ1, 8, /* Second IRQ */ - Offset (0x74), - PNP_DMA0, 8, /* DRQ */ - } - - Method (_CRS) - { - /* Announce the used I/O ports to the OS */ - Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) - }) - } - - #undef PNP_ENTER_MAGIC_1ST - #undef PNP_ENTER_MAGIC_2ND - #undef PNP_ENTER_MAGIC_3RD - #undef PNP_ENTER_MAGIC_4TH - #undef PNP_EXIT_MAGIC_1ST - #undef PNP_EXIT_SPECIAL_REG - #undef PNP_EXIT_SPECIAL_VAL - #define PNP_ENTER_MAGIC_1ST 0x87 - #define PNP_ENTER_MAGIC_2ND 0x87 - #define PNP_EXIT_MAGIC_1ST 0xaa - #include - - -#ifdef NCT5539D_SHOW_SP1 - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 2 - #include -#endif - -#ifdef NCT5539D_SHOW_KBC - #undef SUPERIO_KBC_LDN - #undef SUPERIO_KBC_PS2M - #undef SUPERIO_KBC_PS2LDN - #define SUPERIO_KBC_LDN 5 - #define SUPERIO_KBC_PS2M - #include -#endif - -#ifdef NCT5539D_SHOW_HWM - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IO2 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #define SUPERIO_PNP_LDN 11 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #define SUPERIO_PNP_IO1 0x08, 0x08 - #define SUPERIO_PNP_IRQ0 - #include -#endif - -#ifdef NCT5539D_SHOW_GPIO - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IO2 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #undef PNP_DEVICE_ACTIVE - #define PNP_DEVICE_ACTIVE ACT3 - #define SUPERIO_PNP_LDN 8 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #include -#endif -} From 5f26d8cb4ad17570a60f449022574d819f39d6c2 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Fri, 6 Mar 2020 14:31:14 +0530 Subject: [PATCH 0400/1463] mb/google/dedede: Add SPD hex file for Samsung memory part BUG=b:150154457 BRANCH=none TEST=Build dedede, flash and boot to kernel. Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- .../spd/samsung-K4U6E3S4AA-MGCL.spd.hex | 32 +++++++++++++++++++ .../dedede/variants/waddledoo/Makefile.inc | 1 + 2 files changed, 33 insertions(+) create mode 100644 src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex diff --git a/src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex b/src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex new file mode 100644 index 0000000000..e1f27fba56 --- /dev/null +++ b/src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 28da8f636b..c55051b9fc 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -8,3 +8,4 @@ SPD_SOURCES = empty #0b0000 SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 +SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010 From ccde6be13a64f369da61c70be0221d0bc24f0fe2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 3 Mar 2020 20:48:30 +0100 Subject: [PATCH 0401/1463] soc/intel/common/block/smm: add case intrusion to SMI handler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds case intrusion detection to the SMI handler. At this point one can add the code to be executed when the INTRUDER signal gets asserted (iow: when the case is opened). Examples: - issue a warning - trigger an NMI - call poweroff() - ... Tested on X11SSM-F. Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/common/block/smm/smihandler.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 54f4e41e50..12c538eb96 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -453,6 +454,14 @@ void smihandler_southbridge_tco( /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); } + + if (tco_sts & (TCO_INTRD_DET << 16)) { /* INTRUDER# assertion */ + /* + * Handle intrusion event + * If we ever get here, probably the case has been opened. + */ + printk(BIOS_CRIT, "Case intrusion detected.\n"); + } } void smihandler_southbridge_periodic( From f787e8714589da232e198ca5bdcf602fe923b603 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 3 Mar 2020 01:58:17 -0800 Subject: [PATCH 0402/1463] mb/intel/tglrvp: Enable Hybrid storage mode BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check PCIe lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae: Signed-off-by: Wonkyu Kim Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Srinidhi N Kaushik --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 +++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e60e648ef9..4492acb7ea 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -37,6 +37,9 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 1f05e0ee46..643db36c2c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -37,6 +37,9 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3" From 6f785b0f62a672c9211ef545bd307abdcc1fe7b9 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 9 Mar 2020 22:39:25 -0600 Subject: [PATCH 0403/1463] mb/google/dedede: Add ACPI configuration for USB ports Enable USB ACPI driver. Add ACPI configuration for all the USB ports. Since one of the USB ports is used for Bluetooth configure the reset_gpio used by that port. TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest --- src/mainboard/google/dedede/Kconfig | 1 + .../dedede/variants/baseboard/devicetree.cb | 62 ++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2606e57364..36b42bf8b3 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 0efb76dfe0..994e96e489 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -158,7 +158,67 @@ chip soc/intel/tigerlake device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub device pci 12.6 off end # GSPI 2 - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + end + end + end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM device pci 14.3 off end # CNVi wifi From 18129f919ac637e7b728ec7e4d1eb797eb3b465b Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Tue, 10 Mar 2020 15:40:42 -0700 Subject: [PATCH 0404/1463] soc/intel/tigerlake: Enable HDA through dev_enabled Check for dev enabled status for HDA controller and update the UPD accordingly. BUG=151174264 BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441 Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index f0f3b4cadd..4b9b007eb6 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -28,6 +28,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, { unsigned int i; uint32_t mask = 0; + const struct device *dev; /* Set IGD stolen size to 60MB. */ m_cfg->IgdDvmt50PreAlloc = 0xFE; @@ -70,7 +71,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, * Skip IGD initialization in FSP if device * is disable in devicetree.cb. */ - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!dev || !dev->enabled) m_cfg->InternalGfx = 0; else @@ -113,6 +114,12 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, From 9a2922871d365dbaa373e155c3a72bae4a9d8204 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 6 Mar 2020 13:44:50 +0800 Subject: [PATCH 0405/1463] vboot: remove extraneous vboot_recovery_mode_memory_retrain Just call get_recovery_mode_retrain_switch() directly. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: Icb88d6862db1782e0218276984e527638b21fd3a Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/39343 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Angel Pons --- src/drivers/intel/fsp2_0/memory_init.c | 3 ++- src/drivers/mrc_cache/mrc_cache.c | 2 +- src/security/vboot/bootmode.c | 5 ----- src/security/vboot/vboot_common.h | 2 -- src/soc/mediatek/mt8183/memory.c | 3 ++- 5 files changed, 5 insertions(+), 10 deletions(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 455dfa5029..ad95dce12a 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -120,7 +121,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) if (vboot_recovery_mode_enabled()) { if (!CONFIG(HAS_RECOVERY_MRC_CACHE)) return; - if (vboot_recovery_mode_memory_retrain()) + if (get_recovery_mode_retrain_switch()) return; } diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index d4a4aab308..2287f27d4b 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -521,7 +521,7 @@ static void invalidate_normal_cache(void) /* Invalidate only on recovery mode with retraining enabled. */ if (!vboot_recovery_mode_enabled()) return; - if (!vboot_recovery_mode_memory_retrain()) + if (!get_recovery_mode_retrain_switch()) return; if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) { diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 2363bf9588..6cbb1160ca 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -71,11 +71,6 @@ int __weak get_recovery_mode_retrain_switch(void) return 0; } -int vboot_recovery_mode_memory_retrain(void) -{ - return get_recovery_mode_retrain_switch(); -} - #if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** * TODO: Create flash protection interface which implements get_write_protect_state. diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 57f3475adb..8be9d2ac8d 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -67,14 +67,12 @@ void verstage_mainboard_init(void); #if CONFIG(VBOOT) int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); -int vboot_recovery_mode_memory_retrain(void); int vboot_can_enable_udc(void); void vboot_run_logic(void); int vboot_locate_cbfs(struct region_device *rdev); #else /* !CONFIG_VBOOT */ static inline int vboot_developer_mode_enabled(void) { return 0; } static inline int vboot_recovery_mode_enabled(void) { return 0; } -static inline int vboot_recovery_mode_memory_retrain(void) { return 0; } /* If VBOOT is not enabled, we are okay enabling USB device controller (UDC). */ static inline int vboot_can_enable_udc(void) { return 1; } static inline void vboot_run_logic(void) {} diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 78890ea3d2..15ae9cbeea 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -174,7 +175,7 @@ static void mt_mem_init_run(struct dramc_param_ops *dparam_ops) /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); - if (vboot_recovery_mode_memory_retrain() || + if (get_recovery_mode_retrain_switch() || vboot_check_recovery_request() == VB2_RECOVERY_TRAIN_AND_REBOOT) { printk(BIOS_WARNING, "Retrain memory in next boot\n"); /* Use 0xFF as erased flash data. */ From 84b4882b99e92665ea6db933f8180b489b1759b4 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 9 Mar 2020 13:34:38 -0700 Subject: [PATCH 0406/1463] soc/intel/tigerlake: Configure L1Substates for PCH Root ports Set value for PcieRpL1Substates according to devicetree. Chip config parameter PcieRpL1Substates uses (UPD value + 1) because UPD value of 0 for PcieRpL1Substates means disabled for FSP. In order to ensure that mainboard setting does not disable L1 substates incorrectly, chip config parameter values are offset by 1 with 0 meaning use FSP UPD default. get_l1_substate_control() ensures that the right UPD value is set in fsp_params. Chip config parameter values 0: Use FSP UPD default 1: Disable L1 substates 2: Use L1.1 3: Use L1.2 (FSP UPD default) BUG=none BRANCH=none TEST=Boot up and check FSP log for PCIe config for this values Signed-off-by: Wonkyu Kim Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412 Reviewed-by: Caveh Jalali Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 8 ++++++++ src/soc/intel/tigerlake/fsp_params_tgl.c | 24 ++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d23148aac8..9fc70f8a46 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -122,6 +122,14 @@ struct soc_intel_tigerlake_config { * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + /* PCIe RP L1 substate */ + enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, + } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 14997c519a..7230a4c7e0 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -28,6 +28,25 @@ #include #include +/* + * Chip config parameter PcieRpL1Substates uses (UPD value + 1) + * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. + * In order to ensure that mainboard setting does not disable L1 substates + * incorrectly, chip config parameter values are offset by 1 with 0 meaning + * use FSP UPD default. get_l1_substate_control() ensures that the right UPD + * value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable L1 substates + * 2: Use L1.1 + * 3: Use L1.2 (FSP UPD default) + */ +static int get_l1_substate_control(enum L1_substates_control ctl) +{ + if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + ctl = L1_SS_L1_2; + return ctl - 1; +} + static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_tigerlake_config *config; @@ -113,6 +132,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } + /* RP Configs */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + params->PcieRpL1Substates[i] = + get_l1_substate_control(config->PcieRpL1Substates[i]); + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); if (dev) { From 396bb46e7dc14a5feb99de4513a13881de9ef83f Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 9 Mar 2020 13:42:45 -0700 Subject: [PATCH 0407/1463] mb/google/volteer: configure L1Substate for PCIe Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround. Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330 BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe Signed-off-by: Wonkyu Kim Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413 Tested-by: build bot (Jenkins) Reviewed-by: Srinidhi N Kaushik Reviewed-by: Nick Vaccaro --- src/mainboard/google/volteer/variants/ripto/overridetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb index 32204c58e7..162f93bdb7 100644 --- a/src/mainboard/google/volteer/variants/ripto/overridetree.cb +++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/tigerlake + # NVMe warm reboot workaround + # Limit L1.1 (value:2) for RP9, RP11 + register "PcieRpL1Substates[8]" = "2" + register "PcieRpL1Substates[10]" = "2" + device domain 0 on end From d1f3022ebfce359ba26401bba8f71913fbc61886 Mon Sep 17 00:00:00 2001 From: raymondchung Date: Tue, 11 Feb 2020 15:07:39 +0800 Subject: [PATCH 0408/1463] mb/google/hatch: Create nightfury variant Create new variant and build for nightfury. BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 5 + .../hatch/variants/nightfury/Makefile.inc | 24 ++ .../google/hatch/variants/nightfury/gpio.c | 178 +++++++++++ .../nightfury/include/variant/acpi/dptf.asl | 93 ++++++ .../variants/nightfury/include/variant/ec.h | 48 +++ .../variants/nightfury/include/variant/gpio.h | 27 ++ .../google/hatch/variants/nightfury/memory.c | 68 +++++ .../hatch/variants/nightfury/overridetree.cb | 281 ++++++++++++++++++ .../hatch/variants/nightfury/ramstage.c | 29 ++ 10 files changed, 755 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/nightfury/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/nightfury/gpio.c create mode 100644 src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/nightfury/memory.c create mode 100644 src/mainboard/google/hatch/variants/nightfury/overridetree.cb create mode 100644 src/mainboard/google/hatch/variants/nightfury/ramstage.c diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 92d94db68c..b0d2e75933 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -99,6 +99,7 @@ config MAINBOARD_PART_NUMBER default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE @@ -122,6 +123,7 @@ config VARIANT_DIR default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU + default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index fe1e334585..785e2c88f8 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -44,6 +44,11 @@ config BOARD_GOOGLE_MUSHU select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 +config BOARD_GOOGLE_NIGHTFURY + bool "-> Nightfury" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc new file mode 100644 index 0000000000..f46b7b0bcf --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -0,0 +1,24 @@ +## This file is part of the coreboot project. +## +## Copyright 2020 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = LP_8G_2133 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += LP_4G_2133 # 0b010 + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c new file mode 100644 index 0000000000..681f9ecde2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : NC */ + PAD_NC(GPP_A20, NONE), + /* A22 : NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + + /* B8 : NC */ + PAD_NC(GPP_B8, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + + /* C1 : NC */ + PAD_NC(GPP_C1, NONE), + /* C12 : EN_PP3300_TSP_DX */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C13 : EC_PCH_INT_L - needs to wake the system */ + PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + + /* D16 : TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + + /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H4 : NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : NC */ + PAD_NC(GPP_H5, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F3 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* H19 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . + */ +static const struct pad_config default_sleep_gpio_table[] = { + +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..edfad4b8bc --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 50 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 90 +#define DPTF_TSR0_TABLET_PASSIVE 32 +#define DPTF_TSR0_TABLET_CRITICAL 90 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 90 +#define DPTF_TSR1_TABLET_PASSIVE 32 +#define DPTF_TSR1_TABLET_CRITICAL 90 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA" +#define DPTF_TSR2_PASSIVE 45 +#define DPTF_TSR2_CRITICAL 90 +#define DPTF_TSR2_TABLET_PASSIVE 32 +#define DPTF_TSR2_TABLET_CRITICAL 90 + +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT" +#define DPTF_TSR3_PASSIVE 45 +#define DPTF_TSR3_CRITICAL 90 +#define DPTF_TSR3_TABLET_PASSIVE 32 +#define DPTF_TSR3_TABLET_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on 5V (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on IA (TSR2) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on GT (TSR3) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 10, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 7000, /* PowerLimitMinimum */ + 9000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 250 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h new file mode 100644 index 0000000000..5b321a33a8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#define EC_ENABLE_MULTIPLE_DPTF_PROFILES + +/* Add EC_HOST_EVENT_MKBP from baseboard */ +#undef MAINBOARD_EC_S3_WAKE_EVENTS +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Removing EC_HOST_EVENT_MKBP from baseboard mask */ +#undef MAINBOARD_EC_SCI_EVENTS +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#endif /* VARIANT_EC_H */ diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h new file mode 100644 index 0000000000..2193c7b2f7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/nightfury/memory.c b/src/mainboard/google/hatch/variants/nightfury/memory.c new file mode 100644 index 0000000000..7e1594c47e --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/memory.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the SoC pins to the lpddr3 pins + * for both channels. + * + * "The index of the array is CPU byte number, the values are DRAM byte + * numbers." - doc #573387 + * + * the index = pin number on SoC + * the value = pin number on lpddr3 part + */ + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4}, + .dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4}, + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + + /* Nightfury uses 200, 80.6 and 162 rcomp resistors */ + .rcomp_resistor = {200, 81, 162}, + + /* Nightfury Rcomp target values */ + .rcomp_targets = {100, 40, 40, 23, 40}, + + /* Set CaVref config to 0 for LPDDR3 */ + .vref_ca_config = 0, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb new file mode 100644 index 0000000000..0cf18e7db4 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -0,0 +1,281 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "8" + register "tdp_pl2_override" = "51" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Enable DMIC1 + register "PchHdaAudioLinkDmic1" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Digitizer | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 135, + .fall_time_ns = 45, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 55, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + device usb 2.2 off end + end + chip drivers/usb/acpi + device usb 2.3 off end + end + chip drivers/usb/acpi + device usb 2.4 off end + end + chip drivers/usb/acpi + device usb 2.5 off end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + device usb 2.7 off end + end + chip drivers/usb/acpi + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + chip drivers/usb/acpi + device usb 3.3 off end + end + chip drivers/usb/acpi + device usb 3.4 off end + end + end + end + end + + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.probed" = "1" + register "generic.wake" = "GPE0_DW0_21" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x20 on end + end + end # I2C 0 + + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""atmel,maxtouch"" + register "desc" = ""Atmel Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "91" # 90.5 ms + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "enable_delay_ms" = "1" # 90 ns + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + register "probed" = "1" + device i2c 4b on end + end + + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # I2C #1 + + device pci 15.2 off end # I2C #2 + + device pci 19.0 on + chip drivers/i2c/da7219 + # TODO: these settings were copied from another board + # with the same chip. verify the settings + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 0x1a on end + end + end + + # No PCIe WiFi + device pci 1d.5 off end + device pci 1a.0 on end #eMMC + device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end # domain +end diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c new file mode 100644 index 0000000000..44cd89b00e --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Nightfury. + */ +} From 4f8b00602c10088ceee2485821ceb53dbbf717ad Mon Sep 17 00:00:00 2001 From: "Pandya, Varshit B" Date: Tue, 3 Mar 2020 22:45:44 +0530 Subject: [PATCH 0409/1463] mb/google/dedede: Enable trackpad support 1. Configure trackpad interrupt GPIO. 2. Set i2c0 configuration. 3. Add trackpad ACPI support. TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz on trackpad operation. Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6 Signed-off-by: Pandya, Varshit B Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- .../google/dedede/variants/baseboard/gpio.c | 2 +- .../dedede/variants/waddledoo/overridetree.cb | 52 ++++++++++++++++++- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index af95f6a733..fe903bd934 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -55,7 +55,7 @@ static const struct pad_config gpio_table[] = { /* B2 : PROCHOT_ODL */ PAD_NC(GPP_B2, NONE), /* B3 : TRACKPAD_INT_ODL */ - PAD_NC(GPP_B3, NONE), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, LEVEL, INVERT), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), /* B5 : PCIE_CLKREQ0_N */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index ac9d576d01..061a0f865f 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,3 +1,53 @@ chip soc/intel/tigerlake - device domain 0 on end + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + end end From a7ec42619c310a5e72256821d17f62e7e64bce45 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 11 Mar 2020 16:31:59 +0100 Subject: [PATCH 0410/1463] soc/intel/*/smihandler: Only compile in TCO SMI handler if needed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case. Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Michael Niewöhner --- src/soc/intel/apollolake/smihandler.c | 2 ++ src/soc/intel/cannonlake/smihandler.c | 2 ++ src/soc/intel/icelake/smihandler.c | 2 ++ src/soc/intel/skylake/smihandler.c | 2 ++ src/soc/intel/tigerlake/smihandler.c | 2 ++ 5 files changed, 10 insertions(+) diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index e37de92d2a..073d66590d 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -39,7 +39,9 @@ const smi_handler_t southbridge_smi[32] = { [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, [GPIO_STS_BIT] = smihandler_southbridge_gpi, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4be7897f78..f68f4c29bf 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -48,7 +48,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 6be7b70338..ec9deb2858 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -46,7 +46,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 4818c0202e..213de0ac00 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -26,7 +26,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 0e8d345bac..1eb56aac8d 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -46,7 +46,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; From 49111cd2ba12d33caa1031b5be6b631c9f76486a Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 3 Jan 2020 11:01:23 -0800 Subject: [PATCH 0411/1463] soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table. BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/acpi.c | 94 +++++++++++++++++++ src/soc/intel/tigerlake/include/soc/iomap.h | 21 +++++ .../intel/tigerlake/include/soc/pci_devs.h | 6 +- .../intel/tigerlake/include/soc/systemagent.h | 32 ++++++- .../intel/tigerlake/romstage/fsp_params_tgl.c | 14 +++ src/soc/intel/tigerlake/systemagent.c | 10 +- 6 files changed, 174 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index b9cae3c23c..af4076cf60 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include #include #include @@ -191,6 +193,98 @@ uint32_t soc_read_sci_irq_select(void) return read32((void *)pmc_bar + IRQ_REG); } +static unsigned long soc_fill_dmar(unsigned long current) +{ + const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; + bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; + + if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 5, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; + bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; + + if (vtvc0bar && vtvc0en) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* TCSS Thunderbolt root ports */ + for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { + uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK; + bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED; + if (tbtbar && tbten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* + * Create DMAR table only if we have VT-d capability and FSP does not override its + * feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + void acpi_create_gnvs(struct global_nvs_t *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index f403873f10..d9fc01eaa8 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -51,6 +51,27 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 +#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfb000000 #define REG_BASE_SIZE 0x1000 diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index ef2dfe3ec4..af449ba118 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -53,6 +53,10 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 56a2bd8887..92d70723df 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,10 +34,23 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) #define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define IPUVTBAR 0x7880 +#define TBT0BAR 0x7888 +#define TBT1BAR 0x7890 +#define TBT2BAR 0x7898 +#define TBT3BAR 0x78A0 +#define MAX_TBT_PCIE_PORT 4 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 @@ -47,4 +60,21 @@ #define IMRBASE 0x6A40 #define IMRLIMIT 0x6A48 +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + #endif diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 4b9b007eb6..072c99ea7e 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -131,6 +131,20 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + + /* Vt-D config */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdIopEnable = 0x1; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->VtdItbtEnable = 0x1; + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 9c8f64573d..152f8f90d9 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -56,6 +57,13 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); } /* From 6daa8c3ba5fb6524cbfb3f2fa9f66eb6c9c73d5e Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 12 Mar 2020 10:38:01 +1100 Subject: [PATCH 0412/1463] mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on Puff Early ec sync needs to be disabled for EFS2 to function. BUG=b:151115320 BRANCH=none TEST=none Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b0d2e75933..512d3106c3 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -130,7 +130,8 @@ config VARIANT_DIR config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - select VBOOT_EARLY_EC_SYNC + # FIXME: allow kconfig to select on a subset of boards only + select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_PUFF select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_HATCH From 22d5b071607c301b3e7c563e16b2ecc915f864fd Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 6 Mar 2020 10:47:17 -0800 Subject: [PATCH 0413/1463] mb/google/volteer: Enable Audio DSP UPD Provide settings for configuring the link between HD-Audio controller and display unit for purposes of HDMI/DP Audio playback. BUG=b:144708516, b:148385924 TEST=none Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../volteer/variants/baseboard/devicetree.cb | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a65e5f1be8..84d121f2b1 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -110,6 +110,21 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # TCSS USB3 register "TcssXhciEn" = "1" From dabc0adb3af720c71e077f269c937c803580d6c6 Mon Sep 17 00:00:00 2001 From: Prashant Malani Date: Tue, 10 Mar 2020 15:42:54 -0700 Subject: [PATCH 0414/1463] ec/google/chromeec/acpi: Move ECPD under CREC Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP device drivers can access the parent EC device to communicate with the EC. Also, update the Notify() call to reflect the new location of the ECPD device. Signed-off-by: Prashant Malani Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39469 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/ec/google/chromeec/acpi/cros_ec.asl | 4 ++++ src/ec/google/chromeec/acpi/ec.asl | 6 +----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index d41071e731..bcf38d2328 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -60,6 +60,10 @@ Device (CREC) Name (_DDN, "EC Base Switch Device") } #endif + +#ifdef EC_ENABLE_PD_MCU_DEVICE + #include "pd.asl" +#endif Method(_STA, 0) { Return (0xB) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index bf792d3629..fa5eca6321 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -344,7 +344,7 @@ Device (EC0) Method (_Q16, 0, NotSerialized) { Store ("EC: GOT PD EVENT", Debug) - Notify (ECPD, 0x80) + Notify (\_SB.PCI0.LPCB.EC0.CREC.ECPD, 0x80) } #endif @@ -558,10 +558,6 @@ Device (EC0) #include "keyboard_backlight.asl" #endif -#ifdef EC_ENABLE_PD_MCU_DEVICE - #include "pd.asl" -#endif - #ifdef EC_ENABLE_TBMC_DEVICE #include "tbmc.asl" #endif From c04757b108596840535ddbb4704e6b2268edc2d3 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 12 Mar 2020 13:18:19 -0700 Subject: [PATCH 0415/1463] mb/intel/tglrvp: Update GPIO setting Update GPIO reset type from PLTRST to DEEP. DEEP setting is more conservative for S3/S4/S5. Detail information is bug. BUG=b:151305120 TEST=Build and boot to OS Signed-off-by: Wonkyu Kim Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476 Reviewed-by: Nick Vaccaro Reviewed-by: Srinidhi N Kaushik Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/gpio.c | 72 +++++++++--------- .../intel/tglrvp/variants/tglrvp_up4/gpio.c | 73 +++++++++---------- 2 files changed, 72 insertions(+), 73 deletions(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 30d148a6de..b0c5bc1bd4 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -20,52 +20,52 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ - PAD_CFG_GPO(GPP_B16, 1, PLTRST), - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO(GPP_B16, 1, DEEP), + PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Camera */ - PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ - PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ - PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ - PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ - PAD_CFG_GPO(GPP_B23, 0, PLTRST), - PAD_CFG_GPO(GPP_C15, 0, PLTRST), - PAD_CFG_GPO(GPP_R6, 0, PLTRST), - PAD_CFG_GPO(GPP_H12, 0, PLTRST), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* I2C5_SCL */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + PAD_CFG_GPO(GPP_C15, 0, DEEP), + PAD_CFG_GPO(GPP_R6, 0, DEEP), + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ - PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* ISH UART0 RX/TX */ - PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH I2C0 */ - PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* ISH GPI 0-6 */ - PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), - /*Audio */ + /* Audio */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */ - PAD_CFG_GPO(GPP_C5, 1, PLTRST), - PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /*Audio */ + /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ @@ -87,14 +87,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ /* DP */ - PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ - PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ - PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ - PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ - PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ - PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ - PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ - PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 2f952d2188..c00f6d1137 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -20,53 +20,52 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ - PAD_CFG_GPO(GPP_B16, 1, PLTRST), - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO(GPP_B16, 1, DEEP), + PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Camera */ - PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ - PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ - PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ - PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ - PAD_CFG_GPO(GPP_B23, 0, PLTRST), - PAD_CFG_GPO(GPP_C15, 0, PLTRST), - PAD_CFG_GPO(GPP_E22, 0, PLTRST), - PAD_CFG_GPO(GPP_H12, 0, PLTRST), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* I2C5_SCL */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + PAD_CFG_GPO(GPP_C15, 0, DEEP), + PAD_CFG_GPO(GPP_E22, 0, DEEP), + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ - PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* ISH UART0 RX/TX */ - PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH I2C0 */ - PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* ISH GPI 0-6 */ - PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), - /*Audio */ + /* Audio */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */ - PAD_CFG_GPO(GPP_C5, 1, PLTRST), - PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - /*Audio */ + /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ @@ -88,14 +87,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ /* DP */ - PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ - PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ - PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ - PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ - PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ - PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ - PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ - PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ }; const struct pad_config *variant_gpio_table(size_t *num) From f9c6a8821fb9b1adad3b1be462313f53b9e37c7b Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 12 Mar 2020 17:24:34 +0800 Subject: [PATCH 0416/1463] mb/google/drallion: Enable GEO SAR Enable GEO SAR function. BUG=b:150347463 BRANCH=drallion TEST=NA Signed-off-by: Eric Lai Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467 Reviewed-by: Mathew King Reviewed-by: Ivy Jian Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index aff19c819c..c61a5b3d18 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -37,6 +37,7 @@ config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" depends on CHROMEOS select DSAR_ENABLE + select GEO_SAR_ENABLE select SAR_ENABLE select USE_SAR select WIFI_SAR_CBFS From 136e0cbbc139356e39d7f0457dd05cac1ee5183f Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Mar 2020 22:00:24 -0600 Subject: [PATCH 0417/1463] mb/google/dedede: Add BT Disable GPIO configuration Disable the BT module in bootblock and enable it in ramstage. This allows for loading the BT firmware during reboot. TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 1 + src/mainboard/google/dedede/variants/baseboard/gpio.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 994e96e489..5a635b32c3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -190,6 +190,7 @@ chip soc/intel/tigerlake chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" device usb 2.4 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index fe903bd934..20c7be9123 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -328,7 +328,7 @@ static const struct pad_config gpio_table[] = { /* H18 : WLAN_DISABLE_L */ PAD_NC(GPP_H18, NONE), /* H19 : BT_DISABLE_L */ - PAD_NC(GPP_H19, NONE), + PAD_CFG_GPO(GPP_H19, 1, DEEP), /* R0 : I2S_HP_BCLK */ PAD_NC(GPP_R0, NONE), @@ -409,6 +409,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), + + /* H19 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_H19, 0, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) From f354c8c6258aa30c545c78c454c2e174b19abeae Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 28 Feb 2020 17:00:14 -0700 Subject: [PATCH 0418/1463] mb/google/dedede: Configure WLAN Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../dedede/variants/baseboard/devicetree.cb | 16 +++++++--- .../google/dedede/variants/baseboard/gpio.c | 31 ++++++++++--------- .../dedede/variants/waddledoo/overridetree.cb | 7 +++++ 3 files changed, 35 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 5a635b32c3..9a8ad66cdd 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -84,12 +84,14 @@ chip soc/intel/tigerlake register "PcieRpEnable[4]" = "0" register "PcieRpEnable[5]" = "0" register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" + # PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN. + register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[0]" = "0xff" register "PcieClkSrcUsage[1]" = "0xff" register "PcieClkSrcUsage[2]" = "0xff" - register "PcieClkSrcUsage[3]" = "0xff" + # PCIe Clock Source 4 (index 3) is used by WLAN on PCIe Root Port 8 (index 7) + register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcUsage[4]" = "0xff" register "PcieClkSrcUsage[5]" = "0xff" @@ -222,7 +224,10 @@ chip soc/intel/tigerlake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - device pci 14.3 off end # CNVi wifi + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 off end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 @@ -240,11 +245,12 @@ chip soc/intel/tigerlake device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 off end # PCI Express Root Port 3 - device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.3 off end # PCI Express Root Port 4 device pci 1c.4 off end # PCI Express Root Port 5 device pci 1c.5 off end # PCI Express Root Port 6 device pci 1c.6 off end # PCI Express Root Port 7 - device pci 1c.7 off end # PCI Express Root Port 8 + # External PCIe port 4 is mapped to PCIe Root port 8 + device pci 1c.7 on end # PCI Express Root Port 8 - WLAN device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 device pci 1e.2 on diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 20c7be9123..13419b8b66 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -64,8 +64,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_B6, NONE), /* B7 : PCIE_CLKREQ2_N */ PAD_NC(GPP_B7, NONE), - /* B8 : PCIE_CLKREQ3_N */ - PAD_NC(GPP_B8, NONE), + /* B8 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* B9 : PCIE_CLKREQ4_N */ PAD_NC(GPP_B9, NONE), /* B10 : PCIE_CLKREQ5_N */ @@ -149,11 +149,11 @@ static const struct pad_config gpio_table[] = { /* D0 : WWAN_HOST_WAKE */ PAD_NC(GPP_D0, NONE), /* D1 : WLAN_PERST_L */ - PAD_NC(GPP_D1, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), /* D2 : WLAN_INT_L */ PAD_NC(GPP_D2, NONE), /* D3 : WLAN_PCIE_WAKE_ODL */ - PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI_SCI_LOW(GPP_D3, NONE, DEEP, EDGE_SINGLE), /* D4 : TOUCH_INT_ODL */ PAD_NC(GPP_D4, NONE), /* D5 : TOUCH_RESET_L */ @@ -185,11 +185,11 @@ static const struct pad_config gpio_table[] = { /* D18 : I2S_MCLK */ PAD_NC(GPP_D18, NONE), /* D19 : WWAN_WLAN_COEX1 */ - PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : WWAN_WLAN_COEX2 */ - PAD_NC(GPP_D20, NONE), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : WWAN_WLAN_COEX3 */ - PAD_NC(GPP_D21, NONE), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* D22 : AP_I2C_SUB_SDA*/ PAD_NC(GPP_D22, NONE), /* D23 : AP_I2C_SUB_SCL */ @@ -236,17 +236,17 @@ static const struct pad_config gpio_table[] = { /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ PAD_NC(GPP_E19, NONE), /* E20 : CNV_BRI_DT_R */ - PAD_NC(GPP_E20, NONE), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* E21 : CNV_BRI_RSP */ - PAD_NC(GPP_E21, NONE), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* E22 : CNV_RGI_DT_R */ - PAD_NC(GPP_E22, NONE), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* E23 : CNV_RGI_RSP */ - PAD_NC(GPP_E23, NONE), + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* F4 : CNV_RF_RST_L */ - PAD_NC(GPP_F4, NONE), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -294,7 +294,7 @@ static const struct pad_config gpio_table[] = { /* H1 : EN_PP3300_SD_U */ PAD_NC(GPP_H1, NONE), /* H2 : CNV_CLKREQ0 */ - PAD_NC(GPP_H2, NONE), + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */ PAD_NC(GPP_H3, NONE), /* H4 : AP_I2C_TS_SDA */ @@ -326,7 +326,7 @@ static const struct pad_config gpio_table[] = { /* H17 : WWAN_RST_L */ PAD_NC(GPP_H17, NONE), /* H18 : WLAN_DISABLE_L */ - PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H18, 1, DEEP), /* H19 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_H19, 1, DEEP), @@ -410,6 +410,9 @@ static const struct pad_config early_gpio_table[] = { /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* D1 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), + /* H19 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_H19, 0, DEEP), }; diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 061a0f865f..9860e3de46 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -49,5 +49,12 @@ chip soc/intel/tigerlake device i2c 15 on end end end #I2C 0 + + device pci 1c.7 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN end end From 6e5693386ba94ebf05015e7cbcc7dd482119c8e4 Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Wed, 11 Mar 2020 14:48:30 -0700 Subject: [PATCH 0419/1463] coreboot: add Volteer template files Add template files for making a new barebones-copy of Volteer. BUG=b:147483699 BRANCH=None TEST=N/A Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- .../google/volteer/template/Makefile.inc | 3 ++ .../volteer/template/include/variant/ec.h | 23 ++++++++++++++ .../volteer/template/include/variant/gpio.h | 30 +++++++++++++++++++ .../google/volteer/template/overridetree.cb | 6 ++++ 4 files changed, 62 insertions(+) create mode 100644 util/mainboard/google/volteer/template/include/variant/ec.h create mode 100644 util/mainboard/google/volteer/template/include/variant/gpio.h create mode 100644 util/mainboard/google/volteer/template/overridetree.cb diff --git a/util/mainboard/google/volteer/template/Makefile.inc b/util/mainboard/google/volteer/template/Makefile.inc index 38cf728d8f..f130808dfa 100644 --- a/util/mainboard/google/volteer/template/Makefile.inc +++ b/util/mainboard/google/volteer/template/Makefile.inc @@ -1,5 +1,8 @@ +## ## This file is part of the coreboot project. ## +## Copyright 2020 Google LLC +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/util/mainboard/google/volteer/template/include/variant/ec.h b/util/mainboard/google/volteer/template/include/variant/ec.h new file mode 100644 index 0000000000..5d3278f445 --- /dev/null +++ b/util/mainboard/google/volteer/template/include/variant/ec.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/util/mainboard/google/volteer/template/include/variant/gpio.h b/util/mainboard/google/volteer/template/include/variant/gpio.h new file mode 100644 index 0000000000..ad4d68bfd1 --- /dev/null +++ b/util/mainboard/google/volteer/template/include/variant/gpio.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/util/mainboard/google/volteer/template/overridetree.cb b/util/mainboard/google/volteer/template/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/util/mainboard/google/volteer/template/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end From ee47fe42f57b47c5fa301966bbb709abc775f66c Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 10 Mar 2020 11:03:02 -0700 Subject: [PATCH 0420/1463] soc/intel/tigerlake: Configure Vmx support using Kconfig Change VmxEnable UPD value based on Kconfig ENABLE_VMX BUG=None TEST=Built image and booted to kernel. Change-Id: I725474643193223865a135813cf882fd7636d24a Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 072c99ea7e..3872b61cf7 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -145,6 +145,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) From aeaeeb7687d657a3f6d71a63ba717af2f14f3bad Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 10 Mar 2020 00:23:40 -0700 Subject: [PATCH 0421/1463] mb/google/volteer: Use generic SPD files Volteer uses 4 bits (hardware straps) to indicate what memory configuration the board is populated with (i.e. which SPD file to use for the populated memory). This allows for only 16 different SPDs for supporting Volteer and all future variants of Volteer. Currently, each memory chip needs its own SPD file, so we can only support 16 different memory chip options for Volteer and all of its variants. Generic SPD files are just SPD files that have been stripped down to contain only fields that are important for the memory controller (strips out items like vendor info, for example). Using generic SPD files allows for more than 16 different memory options given it's no longer a 1-to-1 mapping as similar memory modules from different vendors can share the same generic SPD file. BUG=b:147857288 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB of memory. Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- ...=> SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex} | 8 ++++---- ...=> SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex} | 6 +++--- src/mainboard/google/volteer/variants/ripto/Makefile.inc | 2 +- .../google/volteer/variants/volteer/Makefile.inc | 4 ++-- 4 files changed, 10 insertions(+), 10 deletions(-) rename src/mainboard/google/volteer/spd/{samsung-K4U6E3S4AA-MGCL.spd.hex => SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex} (87%) rename src/mainboard/google/volteer/spd/{samsung-K4UBE3D4AA-MGCR.spd.hex => SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex} (90%) diff --git a/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex similarity index 87% rename from src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex rename to src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex index e1f27fba56..a94b41a381 100644 --- a/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -1,5 +1,5 @@ -23 11 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 -48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +23 11 11 0E 15 19 95 08 00 00 00 00 02 21 00 00 +48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/samsung-K4UBE3D4AA-MGCR.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex similarity index 90% rename from src/mainboard/google/volteer/spd/samsung-K4UBE3D4AA-MGCR.spd.hex rename to src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex index 945b2e8e06..7ef8220252 100644 --- a/src/mainboard/google/volteer/spd/samsung-K4UBE3D4AA-MGCR.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 -48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc index 95401499f7..eba064ff1b 100644 --- a/src/mainboard/google/volteer/variants/ripto/Makefile.inc +++ b/src/mainboard/google/volteer/variants/ripto/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000 +SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 bootblock-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index a6659db315..3f3f6d5f78 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -7,5 +7,5 @@ ## ## Memory Options -SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000 -SPD_SOURCES += samsung-K4UBE3D4AA-MGCR # 0b0001 +SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 +SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 From 1f4f0b47f5f3a70658912eeca8172bc2f16b8351 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 13 Feb 2020 15:45:19 +0800 Subject: [PATCH 0422/1463] mb/google/hatch: Create palkia variant Add Palkia as a variant of Hatch. BUG=b:150254194 BRANCH=none TEST=none Signed-off-by: Kane Chen Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 7 + .../google/hatch/variants/palkia/Makefile.inc | 15 ++ .../google/hatch/variants/palkia/gpio.c | 141 +++++++++++++ .../palkia/include/variant/acpi/dptf.asl | 121 +++++++++++ .../variants/palkia/include/variant/ec.h | 14 ++ .../variants/palkia/include/variant/gpio.h | 20 ++ .../google/hatch/variants/palkia/memory.c | 64 ++++++ .../hatch/variants/palkia/overridetree.cb | 192 ++++++++++++++++++ 9 files changed, 576 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/palkia/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/palkia/gpio.c create mode 100644 src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/palkia/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/palkia/memory.c create mode 100644 src/mainboard/google/hatch/variants/palkia/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 512d3106c3..2bb878491b 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -99,6 +99,7 @@ config MAINBOARD_PART_NUMBER default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE @@ -123,6 +124,7 @@ config VARIANT_DIR default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU + default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 785e2c88f8..207ba2afe5 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -44,6 +44,13 @@ config BOARD_GOOGLE_MUSHU select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 +config BOARD_GOOGLE_PALKIA + bool "-> Palkia" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 + config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/palkia/Makefile.inc b/src/mainboard/google/hatch/variants/palkia/Makefile.inc new file mode 100644 index 0000000000..b0a69da366 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/Makefile.inc @@ -0,0 +1,15 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Palkia. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_SOURCES = LP_8G_2133 # 0b0000 +SPD_SOURCES += LP_16G_2133 # 0b0001 + +romstage-y += memory.c +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c new file mode 100644 index 0000000000..73868f7246 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A18 : ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A22 : ISH_GP4 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : ISH_GP5 ==> NC */ + PAD_NC(GPP_A23, NONE), + + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK ==> NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO ==> NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_NC(GPP_B22, NONE), + + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C4 : TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), + /* C7 : GPP_C7 ==> Touchscreen_INT_L */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), + /* C11 : UART0_CTS# ==> NC */ + PAD_NC(GPP_C11, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + + /* D16 : USI_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + + /* F0 : GPP_F0 ==> NC */ + PAD_NC(GPP_F0, NONE), + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : GPP_F3 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : GPP_F10 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + + /* G0 : GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), + + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : Touchscreen I2C2_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : Touchscreen I2C2_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..c9b4fb3421 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define DPTF_CPU_PASSIVE 0 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery Charger" +#define DPTF_TSR0_PASSIVE 59 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "5V Regulator" +#define DPTF_TSR1_PASSIVE 0 +#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_ACTIVE_AC0 42 +#define DPTF_TSR1_ACTIVE_AC1 41 +#define DPTF_TSR1_ACTIVE_AC2 39 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 0 +#define DPTF_TSR2_CRITICAL 65 + +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "CPU" +#define DPTF_TSR3_PASSIVE 44 +#define DPTF_TSR3_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 70, 50, 50, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on TSR3 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on TSR0 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 64000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h new file mode 100644 index 0000000000..454c8d01f2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h new file mode 100644 index 0000000000..aaf6f4d433 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c new file mode 100644 index 0000000000..1a4bf383e0 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the SoC pins to the lpddr3 pins + * for both channels. + * + * "The index of the array is CPU byte number, the values are DRAM byte + * numbers." - doc #573387 + * + * the index = pin number on SoC + * the value = pin number on lpddr3 part + */ + .dqs_map[DDR_CH0] = {4, 7, 5, 6, 0, 3, 2, 1}, + .dqs_map[DDR_CH1] = {0, 3, 2, 1, 4, 7, 6, 5}, + + .dq_map[DDR_CH0] = { + {0xf0, 0xf}, + {0x0, 0xf}, + {0xf0, 0xf}, + {0xf0, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + + /* Palkia uses 200, 80.6 and 162 rcomp resistors */ + .rcomp_resistor = {200, 81, 162}, + + /* Palkia Rcomp target values */ + .rcomp_targets = {100, 40, 40, 23, 40}, + + /* Set CaVref config to 0 for LPDDR3 */ + .vref_ca_config = 0, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb new file mode 100644 index 0000000000..0792b9607d --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -0,0 +1,192 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "64" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "usb2_ports[2]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD + + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | 2nd Touchscreen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + .data_hold_time_ns = 330, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Micro SD Card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + # No Right Tpype-C port + device usb 3.1 off end + end + chip drivers/usb/acpi + register "desc" = ""Micro SD card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + end + end + end + + # Native SD Card interface unused + device pci 14.5 off end + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen USI"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C 1 + + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9009"" + register "generic.desc" = ""ELAN Touchscreen USI"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C 2 + + # I2C #3 unused + device pci 15.3 off end + + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Left Speaker Amp"" + register "uid" = "0" + register "name" = ""TL"" + device i2c 38 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Right Speaker Amp"" + register "uid" = "1" + register "name" = ""TR"" + device i2c 39 on end + end + end #I2C #4 + # GSPI #1 unused + device pci 1e.3 off end + + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel I2S + end +end From 3663d55a23fb64ea88dd1fd18ae4b0ce29e71a61 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 12 Mar 2020 01:08:14 -0700 Subject: [PATCH 0423/1463] mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 Enable CNVi in devicetree and add gpio pad configs for CNVi BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik Change-Id: I71146960e0d53dae87946a0365dac6f224a72391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464 Reviewed-by: Nick Vaccaro Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4492acb7ea..a43011f02c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -130,7 +130,7 @@ chip soc/intel/tigerlake device pci 0e.0 on end # VMD 0x9A0B # From PCH EDS(576591) - device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 off end # SensorHUB 0xA0FC diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index b0c5bc1bd4..fa97a503b0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -61,6 +61,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + /* CNVi */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + }; /* Early pad configuration in bootblock */ From 1db5bc7dac2bb592708f26dede339ffdf3246567 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Jan 2020 00:49:03 +0100 Subject: [PATCH 0424/1463] nb/intel/haswell: Tidy up code and comments - Reformat some lines of code - Put names to all used MCHBAR registers - Move MCHBAR registers into a separate file, for future expansion - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) Tested, it does not change the binary of Asrock B85M Pro4. Change-Id: I926289304acb834f9b13cd7902801798f8ee478a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi.c | 35 ++- src/northbridge/intel/haswell/bootblock.c | 20 +- src/northbridge/intel/haswell/chip.h | 4 +- src/northbridge/intel/haswell/early_init.c | 92 ++++---- src/northbridge/intel/haswell/finalize.c | 46 ++-- src/northbridge/intel/haswell/gma.c | 120 +++++----- src/northbridge/intel/haswell/haswell.h | 66 +++--- src/northbridge/intel/haswell/mchbar_regs.h | 61 +++++ src/northbridge/intel/haswell/memmap.c | 9 +- src/northbridge/intel/haswell/minihd.c | 37 ++- src/northbridge/intel/haswell/northbridge.c | 248 +++++++++----------- src/northbridge/intel/haswell/pei_data.h | 5 +- src/northbridge/intel/haswell/raminit.c | 93 ++++---- 13 files changed, 429 insertions(+), 407 deletions(-) create mode 100644 src/northbridge/intel/haswell/mchbar_regs.h diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index a9b687b883..02bc1bf2a7 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -37,35 +37,35 @@ unsigned long acpi_fill_mcfg(unsigned long current) pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - // MMCFG not supported or not enabled. + /* MMCFG not supported or not enabled. */ if (!(pciexbar_reg & (1 << 0))) return current; mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB + case 0: /* 256MB */ pciexbar = pciexbar_reg & mask; max_buses = 256; break; - case 1: // 128M + case 1: /* 128M */ mask |= (1 << 27); pciexbar = pciexbar_reg & mask; max_buses = 128; break; - case 2: // 64M + case 2: /* 64M */ mask |= (1 << 27) | (1 << 26); pciexbar = pciexbar_reg & mask; max_buses = 64; break; - default: // RSVD + default: /* RSVD */ return current; } if (!pciexbar) return current; - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, + max_buses - 1); return current; } @@ -79,8 +79,8 @@ static unsigned long acpi_fill_dmar(unsigned long current) const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -91,24 +91,23 @@ static unsigned long acpi_fill_dmar(unsigned long current) /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); } return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, - unsigned long current, +unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { /* Create DMAR table only if we have VT-d capability. */ diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 04fec6fe65..903c770d9d 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -20,19 +20,17 @@ void bootblock_early_northbridge_init(void) uint32_t reg; /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent + * non-explicit config accesses use MCFG. This code also assumes that + * bootblock_northbridge_init() is the first thing called in the non-asm + * boot block code. The final assumption is that no assembly code is using + * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = 0; - pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 506aaa58e8..27227916f6 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -20,9 +20,9 @@ /* * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse + * 0x04 = Enabled, 2ms short pulse * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse + * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ struct northbridge_intel_haswell_config { diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 6aad4a381f..ea563636f8 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -28,21 +28,21 @@ static void haswell_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); } @@ -55,19 +55,17 @@ static void haswell_setup_igd(void) printk(BIOS_DEBUG, "Initializing IGD...\n"); - igd_enabled = !!(pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) - & DEVEN_D2EN); + igd_enabled = !!(pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN); - ggc = pci_read_config16(PCI_DEV(0, 0, 0), GGC); + ggc = pci_read_config16(HOST_BRIDGE, GGC); ggc &= ~0x3f8; if (igd_enabled) { ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1); ggc &= ~GGC_DISABLE_VGA_IO_DECODE; } else { - ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | - GGC_DISABLE_VGA_IO_DECODE; + ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | GGC_DISABLE_VGA_IO_DECODE; } - pci_write_config16(PCI_DEV(0, 0, 0), GGC, ggc); + pci_write_config16(HOST_BRIDGE, GGC, ggc); if (!igd_enabled) { printk(BIOS_DEBUG, "IGD is disabled.\n"); @@ -104,19 +102,18 @@ static void start_peg2_link_training(const pci_devfn_t dev) printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); /* - * The PEG device is hidden while the MRC runs. This is because the - * MRC makes configurations that are not ideal if it sees a VGA - * device in a PEG slot, and it locks registers preventing changes - * to these configurations. + * Hide the PEG device while the MRC runs. This is because the MRC makes + * configurations that are not ideal if it sees a VGA device in a PEG slot, + * and it locks registers preventing changes to these configurations. */ - pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0); + pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); } void haswell_unhide_peg(void) { - u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); for (u8 fn = 0; fn <= 2; fn++) { if (peg_hidden[fn]) { @@ -126,17 +123,19 @@ void haswell_unhide_peg(void) } } - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); + pci_write_config32(HOST_BRIDGE, DEVEN, deven); } static void haswell_setup_peg(void) { - u32 deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); if (deven & DEVEN_D1F2EN) start_peg2_link_training(PCI_DEV(0, 1, 2)); + if (deven & DEVEN_D1F1EN) start_peg2_link_training(PCI_DEV(0, 1, 1)); + if (deven & DEVEN_D1F0EN) start_peg2_link_training(PCI_DEV(0, 1, 0)); } @@ -146,50 +145,51 @@ static void haswell_setup_misc(void) u32 reg32; /* Erratum workarounds */ - reg32 = MCHBAR32(0x5f00); - reg32 |= (1 << 9)|(1 << 10); - MCHBAR32(0x5f00) = reg32; + reg32 = MCHBAR32(SAPMCTL); + reg32 |= (1 << 9) | (1 << 10); + MCHBAR32(SAPMCTL) = reg32; /* Enable SA Clock Gating */ - reg32 = MCHBAR32(0x5f00); - MCHBAR32(0x5f00) = reg32 | 1; + reg32 = MCHBAR32(SAPMCTL); + MCHBAR32(SAPMCTL) = reg32 | 1; /* GPU RC6 workaround for sighting 366252 */ - reg32 = MCHBAR32(0x5d14); + reg32 = MCHBAR32(SSKPD + 4); reg32 |= (1UL << 31); - MCHBAR32(0x5d14) = reg32; + MCHBAR32(SSKPD + 4) = reg32; - /* VLW */ + /* VLW (Virtual Legacy Wire?) */ reg32 = MCHBAR32(0x6120); reg32 &= ~(1 << 0); MCHBAR32(0x6120) = reg32; - reg32 = MCHBAR32(0x5418); + reg32 = MCHBAR32(INTRDIRCTL); reg32 |= (1 << 4) | (1 << 5); - MCHBAR32(0x5418) = reg32; + MCHBAR32(INTRDIRCTL) = reg32; } static void haswell_setup_iommu(void) { - const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); if (capid0_a & VTD_DISABLE) return; - /* setup BARs: zeroize top 32 bits; set enable bit */ + /* Setup BARs: zeroize top 32 bits; set enable bit */ MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; - MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; - MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; + MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; - /* set L3HIT2PEND_DIS, lock GFXVTBAR policy cfg registers */ + /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ u32 reg32; reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); - write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), - reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); - /* clear SPCAPCTRL */ + write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); + + /* Clear SPCAPCTRL */ reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL; - /* set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy cfg registers */ + + /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */ write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); } diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index ca36634f36..024d44e728 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -17,35 +17,33 @@ #include #include "haswell.h" -#define PCI_DEV_HSW PCI_DEV(0, 0, 0) - void intel_northbridge_haswell_finalize_smm(void) { - pci_or_config16(PCI_DEV_HSW, 0x50, 1 << 0); /* GGC */ - pci_or_config32(PCI_DEV_HSW, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(PCI_DEV_HSW, 0x78, 1 << 10); /* ME */ - pci_or_config32(PCI_DEV_HSW, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(PCI_DEV_HSW, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(PCI_DEV_HSW, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(PCI_DEV_HSW, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(PCI_DEV_HSW, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(PCI_DEV_HSW, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */ + pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */ + pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1UL << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1UL << 31); - MCHBAR32_OR(0x7000, 1UL << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ + MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ - MCHBAR8(0x50fc) = 0x8f; + MCHBAR8(MC_LOCK) = 0x8f; /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); + MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); + MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); } diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 3132c20136..cf56c69539 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -97,9 +97,9 @@ static const struct gt_reg haswell_gt_lock[] = { { 0 }, }; -/* some vga option roms are used for several chipsets but they only have one - * PCI ID in their header. If we encounter such an option rom, we need to do - * the mapping ourselves +/* + * Some VGA option roms are used for several chipsets but they only have one PCI ID in their + * header. If we encounter such an option rom, we need to do the mapping ourselves. */ u32 map_oprom_vendev(u32 vendev) @@ -129,39 +129,41 @@ u32 map_oprom_vendev(u32 vendev) return new_vendev; } -/* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. +/** FIXME: Seems to be outdated. */ +/* + * GTT is the Global Translation Table for the graphics pipeline. It is used to translate + * graphics addresses to physical memory addresses. As in the CPU, GTTs map 4K pages. + * + * The setgtt function adds a further bit of flexibility: it allows you to set a range (the + * first two parameters) to point to a physical address (third parameter); the physical address + * is incremented by a count (fourth parameter) for each GTT in the range. + * + * Why do it this way? For ultrafast startup, we can point all the GTT entries to point to one + * page, and set that page to 0s: + * + * memset(physbase, 0, 4096); + * setgtt(0, 4250, physbase, 0); + * + * this takes about 2 ms, and is a win because zeroing the page takes up to 200 ms. + * + * This call sets the GTT to point to a linear range of pages starting at physbase. */ #define GTT_PTE_BASE (2 << 20) -void -set_translation_table(int start, int end, u64 base, int inc) +void set_translation_table(int start, int end, u64 base, int inc) { int i; for (i = start; i < end; i++){ - u64 physical_address = base + i*inc; + u64 physical_address = base + i * inc; + /* swizzle the 32:39 bits to 4:11 */ u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1; - /* note: we've confirmed by checking - * the values that mrc does no - * useful setup before we run this. + + /* + * Note: we've confirmed by checking the values that MRC does no useful + * setup before we run this. */ gtt_write(GTT_PTE_BASE + i * 4, word); gtt_read(GTT_PTE_BASE + i * 4); @@ -211,6 +213,7 @@ int gtt_poll(u32 reg, u32 mask, u32 value) data = gtt_read(reg); if ((data & mask) == value) return 1; + udelay(10); } @@ -261,10 +264,13 @@ static void gma_pm_init_pre_vbios(struct device *dev) /* Wait for Mailbox Ready */ gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); + /* Mailbox Command */ gtt_write(0x138124, 0x80000004); + /* Wait for Mailbox Ready */ gtt_poll(0x138124, (1UL << 31), (0UL << 31)); @@ -291,7 +297,7 @@ static void init_display_planes(void) gtt_write(CURBASE_IVB(pipe), 0x00000000); } - /* Disable primary plane and set surface base address*/ + /* Disable primary plane and set surface base address */ for (plane = PLANE_A; plane <= PLANE_C; plane++) { gtt_write(DSPCNTR(plane), DISPLAY_PLANE_DISABLE); gtt_write(DSPSURF(plane), 0x00000000); @@ -357,11 +363,12 @@ static void gma_setup_panel(struct device *dev) init_display_planes(); - /* DDI-A params set: - bit 0: Display detected (RO) - bit 4: DDI A supports 4 lanes and DDI E is not used - bit 7: DDI buffer is idle - */ + /* + * DDI-A params set: + * bit 0: Display detected (RO) + * bit 4: DDI A supports 4 lanes and DDI E is not used + * bit 7: DDI buffer is idle + */ reg32 = DDI_BUF_IS_IDLE | DDI_INIT_DISPLAY_DETECTED; if (!conf->gpu_ddi_e_connected) reg32 |= DDI_A_4_LANES; @@ -374,14 +381,14 @@ static void gma_setup_panel(struct device *dev) /* Enable the handshake with PCH display when processing reset */ gtt_write(NDE_RSTWRN_OPT, RST_PCH_HNDSHK_EN); - /* undocumented */ + /* Undocumented */ gtt_write(0x42090, 0x04000000); - gtt_write(0x9840, 0x00000000); + gtt_write(0x9840, 0x00000000); gtt_write(0x42090, 0xa4000000); gtt_write(SOUTH_DSPCLK_GATE_D, PCH_LP_PARTITION_LEVEL_DISABLE); - /* undocumented */ + /* Undocumented */ gtt_write(0x42080, 0x00004000); /* Prepare DDI buffers for DP and FDI */ @@ -393,9 +400,10 @@ static void gma_setup_panel(struct device *dev) /* Enable HPD buffer for digital port D and B */ gtt_write(PCH_PORT_HOTPLUG, PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE); - /* Bits 4:0 - Power cycle delay (default 0x6 --> 500ms) - Bits 31:8 - Reference divider (0x0004af ----> 24MHz) - */ + /* + * Bits 4:0 - Power cycle delay (default 0x6 --> 500ms) + * Bits 31:8 - Reference divider (0x0004af ----> 24MHz) + */ gtt_write(PCH_PP_DIVISOR, 0x0004af06); } @@ -440,12 +448,12 @@ static void gma_enable_swsci(void) { u16 reg16; - /* clear DMISCI status */ + /* Clear DMISCI status */ reg16 = inw(get_pmbase() + TCO1_STS); reg16 &= DMISCI_STS; outw(get_pmbase() + TCO1_STS, reg16); - /* clear and enable ACPI TCO SCI */ + /* Clear and enable ACPI TCO SCI */ enable_tco_sci(); } @@ -491,10 +499,9 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) +const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { - struct device *dev = pcidev_on_root(0x2, 0); + struct device *dev = pcidev_on_root(2, 0); if (!dev) { return NULL; } @@ -512,9 +519,8 @@ static void gma_ssdt(struct device *device) drivers_intel_gma_displays_ssdt_generate(gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) +static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, + struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; global_nvs_t *gnvs; @@ -538,19 +544,19 @@ gma_write_acpi_tables(struct device *const dev, unsigned long current, } static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gma_func0_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, .acpi_fill_ssdt_generator = gma_ssdt, - .scan_bus = 0, - .enable = 0, - .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, + .scan_bus = NULL, + .enable = NULL, + .ops_pci = &gma_pci_ops, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { @@ -570,7 +576,7 @@ static const unsigned short pci_device_ids[] = { }; static const struct pci_driver pch_lpc __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index fce94166a7..b45036ee33 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -26,13 +26,9 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#ifndef __ACPI__ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 @@ -46,6 +42,7 @@ #ifndef __ACPI__ /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x48 @@ -55,9 +52,9 @@ #define GGC 0x50 /* GMCH Graphics Control */ #define GGC_DISABLE_VGA_IO_DECODE (1 << 1) #define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3) -#define GGC_GTT_0MB (0 << 8) -#define GGC_GTT_1MB (1 << 8) -#define GGC_GTT_2MB (2 << 8) +#define GGC_GTT_0MB (0 << 8) +#define GGC_GTT_1MB (1 << 8) +#define GGC_GTT_2MB (2 << 8) #define DEVEN 0x54 /* Device Enable */ #define DEVEN_D7EN (1 << 14) @@ -85,11 +82,11 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ +#define REMAPBASE 0x90 /* Remap base */ +#define REMAPLIMIT 0x98 /* Remap limit */ +#define TOM 0xa0 /* Top of DRAM in memory controller space */ #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ #define BDSM 0xb0 /* Base Data Stolen Memory */ #define BGSM 0xb4 /* Base GTT Stolen Memory */ @@ -117,26 +114,27 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ -#define GFXVTBAR 0x5400 -#define VTVC0BAR 0x5410 - -/* Some power MSRs are also represented in MCHBAR */ -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +/* As there are many registers, define them on a separate file */ +#include "mchbar_regs.h" /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) @@ -167,7 +165,7 @@ * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) @@ -215,9 +213,9 @@ void report_platform_info(void); #include struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, - unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, + struct acpi_rsdp *rsdp); -#endif -#endif +#endif /* __ASSEMBLER__ */ +#endif /* __ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/mchbar_regs.h new file mode 100644 index 0000000000..dfc0f7becf --- /dev/null +++ b/src/northbridge/intel/haswell/mchbar_regs.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __HASWELL_MCHBAR_REGS_H__ +#define __HASWELL_MCHBAR_REGS_H__ + +/* Register definitions */ +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */ +#define MC_INIT_STATE_G 0x5030 +#define MRC_REVISION 0x5034 /* MRC Revision */ + +#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ + +#define GFXVTBAR 0x5400 /* Base address for IGD */ +#define EDRAMBAR 0x5408 /* Base address for eDRAM */ +#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ +#define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ +#define GDXCBAR 0x5420 /* Generic Debug eXternal Connection */ + +/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ +#define MMIO_PAVP_MSG 0x5500 + +/* Some power MSRs are also represented in MCHBAR */ +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define SSKPD 0x5d10 /* 64-bit scratchpad register */ +#define BIOS_RESET_CPL 0x5da8 /* 8-bit */ + +#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ +#define SAPMCTL 0x5f00 + +#define HDAUDRID 0x6008 +#define UMAGFXCTL 0x6020 +#define VDMBDFBARKVM 0x6030 +#define VDMBDFBARPAVP 0x6034 +#define VTDTRKLCK 0x63fc +#define REQLIM 0x6800 +#define DMIVCLIM 0x7000 +#define CRDTLCK 0x77fc + +#endif /* __HASWELL_MCHBAR_REGS_H__ */ diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 74d9292c14..2e8addef97 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -// Use simple device model for this file even in ramstage +/* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ #include @@ -30,7 +30,7 @@ static uintptr_t smm_region_start(void) * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignment. */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); return tom & ~((1 << 20) - 1); } @@ -53,7 +53,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 52b158e0c1..c59d02ed95 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -25,30 +25,30 @@ static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862807, // Codec Vendor / Device ID: Intel Haswell Mini-HD - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862807, /* Codec Vendor / Device ID: Intel Haswell Mini-HD */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of jacks */ /* Enable 3rd Pin and Converter Widget */ 0x00878101, /* Pin Widget 5 - PORT B */ - 0x00571C10, - 0x00571D00, - 0x00571E56, - 0x00571F18, + 0x00571c10, + 0x00571d00, + 0x00571e56, + 0x00571f18, /* Pin Widget 6 - PORT C */ - 0x00671C20, - 0x00671D00, - 0x00671E56, - 0x00671F18, + 0x00671c20, + 0x00671d00, + 0x00671e56, + 0x00671f18, /* Pin Widget 7 - PORT D */ - 0x00771C30, - 0x00771D00, - 0x00771E56, - 0x00771F18, + 0x00771c30, + 0x00771d00, + 0x00771e56, + 0x00771f18, /* Disable 3rd Pin and Converter Widget */ 0x00878100, @@ -94,15 +94,14 @@ static void minihd_init(struct device *dev) if (codec_mask) { for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - sizeof(minihd_verb_table), + hda_codec_init(base, i, sizeof(minihd_verb_table), minihd_verb_table); } } } static struct pci_operations minihd_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations minihd_ops = { @@ -110,7 +109,7 @@ static struct device_operations minihd_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = minihd_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &minihd_pci_ops, }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 79ab747f6d..d1b6ca730f 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,11 +31,9 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 pciexbar_reg; - u32 mask; + u32 pciexbar_reg, mask; *base = 0; *len = 0; @@ -46,18 +44,18 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB + case 0: /* 256MB */ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; - case 1: // 128M + case 1: /* 128M */ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; - case 2: // 64M + case 2: /* 64M */ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; @@ -89,50 +87,47 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - */ +/* + * TODO: We could determine how many PCIe busses we need in the bar. + * For now, that number is hardcoded to a max of 64. + */ static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .acpi_name = northbridge_acpi_name, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .acpi_name = northbridge_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, }; static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = pci_read_config32(dev, index); - bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; } -/* There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, - u32 *base, u32 *len) +/* + * There are special BARs that actually are programmed in the MCHBAR. These Intel special + * features, but they do consume resources that need to be accounted for. + */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = MCHBAR32(index); - bar = MCHBAR32(index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; @@ -141,26 +136,22 @@ static int get_bar_in_mchbar(struct device *dev, unsigned int index, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(struct device *dev, unsigned int index, - u32 *base, u32 *size); + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; -#define SIZE_KB(x) ((x)*1024) +#define SIZE_KB(x) ((x) * 1024) struct fixed_mmio_descriptor mc_fixed_resources[] = { { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, - { 0x5420, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, - { 0x5408, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, + { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, }; #undef SIZE_KB -/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ +/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -173,14 +164,13 @@ static void mc_add_fixed_mmio_resources(struct device *dev) size = mc_fixed_resources[i].size; index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) + if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) continue; resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + resource->base = base; resource->size = size; printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", @@ -205,10 +195,10 @@ static void mc_add_fixed_mmio_resources(struct device *dev) * | Usage DRAM | * +--------------------------+ 0 * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. + * Some of the base registers above can be equal, making the size of the regions within 0. + * This is because the memory controller internally subtracts the base registers from each + * other to determine sizes of the regions. In other words, the memory map regions are always + * in a fixed order, no matter what sizes they have. */ struct map_entry { @@ -218,14 +208,13 @@ struct map_entry { const char *description; }; -static void read_map_entry(struct device *dev, struct map_entry *entry, - uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask; - /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); + /* All registers have a 1MiB granularity */ + mask = ((1ULL << 20) - 1); mask = ~mask; value = 0; @@ -252,12 +241,9 @@ static void read_map_entry(struct device *dev, struct map_entry *entry, .description = desc_, \ } -#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) enum { TOM_REG, @@ -270,21 +256,21 @@ enum { BGSM_REG, BDSM_REG, TSEG_REG, - // Must be last. - NUM_MAP_ENTRIES + /* Must be last */ + NUM_MAP_ENTRIES, }; static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; static void mc_read_map_entries(struct device *dev, uint64_t *values) @@ -302,51 +288,45 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", memory_map[i].description, values[i]); } - /* One can validate the BDSM and BGSM against the GGC. */ + /* One can validate the BDSM and BGSM against the GGC */ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; + unsigned long base_k, size_k, touud_k, index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; - /* Read in the MAP registers and report their values. */ + /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); /* * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable + * - 0 -> 0xa0000: cacheable + * - 0xc0000 -> TSEG: cacheable + * - TSEG -> BGSM: cacheable with standard MTRRs and reserved + * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. + * The default SMRAM space is reserved so that the range doesn't have to be saved + * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a + * bit of an odd place to reserve the region, but the CPU devices don't have + * dev_ops->read_resources() called on them. * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. + * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to + * handle legacy VGA memory. If this range is not omitted the mtrr code will setup + * the area as cacheable, causing VGA access to not work. * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. + * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation + * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing + * MTRRs covering this region. * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. + * It should be noted that cacheable entry types need to be added in order. The reason + * is that the current MTRR code assumes this and falls over itself if it isn't. * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. + * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. */ index = *resource_cnt; @@ -364,18 +344,16 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) resource = new_resource(dev, index++); resource->base = mc_values[TSEG_REG]; resource->size = mc_values[BGSM_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; - /* BGSM -> TOLUD. If the IGD is disabled, BGSM can equal TOLUD */ + /* BGSM -> TOLUD. If the IGD is disabled, BGSM can equal TOLUD. */ if (mc_values[BGSM_REG] != mc_values[TOLUD_REG]) { resource = new_resource(dev, index++); resource->base = mc_values[BGSM_REG]; resource->size = mc_values[TOLUD_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; } /* 4GiB -> TOUUD */ @@ -387,16 +365,16 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) /* Reserve everything between A segment and 1MB: * - * 0xa0000 - 0xbffff: legacy VGA + * 0xa0000 - 0xbffff: Legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); + #if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif *resource_cnt = index; } @@ -404,31 +382,27 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) static void mc_read_resources(struct device *dev) { int index = 0; - const bool vtd_capable = - !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - /* Read standard PCI resources. */ + /* Read standard PCI resources */ pci_dev_read_resources(dev); - /* Add all fixed MMIO resources. */ + /* Add all fixed MMIO resources */ mc_add_fixed_mmio_resources(dev); - /* Add VT-d MMIO resources if capable */ + /* Add VT-d MMIO resources, if capable */ if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, - GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, - VTVC0_BASE_SIZE / KiB); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); } - /* Calculate and add DRAM resources. */ + /* Calculate and add DRAM resources */ mc_add_dram_resources(dev, &index); } /* - * The Mini-HD audio device is disabled whenever the IGD is. This is - * because it provides audio over the integrated graphics port(s), which - * requires the IGD to be functional. + * The Mini-HD audio device is disabled whenever the IGD is. This is because it provides + * audio over the integrated graphics port(s), which requires the IGD to be functional. */ static void disable_devices(void) { @@ -446,7 +420,7 @@ static void disable_devices(void) { PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" }, }; - struct device *host_dev = pcidev_on_root(0x0, 0); + struct device *host_dev = pcidev_on_root(0, 0); u32 deven; size_t i; @@ -470,29 +444,29 @@ static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; - /* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(0x5418); + /* Enable Power Aware Interrupt Routing. */ + pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(0x5418) = pair; + MCHBAR8(INTRDIRCTL) = pair; disable_devices(); /* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management + * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management. */ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); bios_reset_cpl |= 3; MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - /* Configure turbo power limits 1ms after reset complete bit */ + /* Configure turbo power limits 1ms after reset complete bit. */ mdelay(1); set_power_limits(28); - /* Set here before graphics PM init */ - MCHBAR32(0x5500) = 0x00100001; + /* Set here before graphics PM init. */ + MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; } static struct pci_operations intel_pci_ops = { @@ -500,13 +474,13 @@ static struct pci_operations intel_pci_ops = { }; static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, .acpi_fill_ssdt_generator = generate_cpu_entries, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .scan_bus = NULL, + .ops_pci = &intel_pci_ops, }; static const unsigned short mc_pci_device_ids[] = { @@ -528,12 +502,12 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ + /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index dfc34d8ce9..6e537403b3 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -101,10 +101,7 @@ struct pei_data /* Data from MRC that should be saved to flash */ unsigned char *mrc_output; unsigned int mrc_output_len; - /* - * Max frequency DDR3 could be ran at. Could be one of four values: 800, - * 1067, 1333, 1600 - */ + /* Max frequency to run DDR3 at. Can be one of four values: 800, 1067, 1333, 1600 */ uint32_t max_ddr3_freq; /* Route all USB ports to XHCI controller in resume path */ int usb_xhci_on_resume; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9615cb08f6..1eb4f4361b 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -37,71 +37,71 @@ void save_mrc_data(struct pei_data *pei_data) { /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - pei_data->mrc_output, pei_data->mrc_output_len); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, + pei_data->mrc_output_len); } static void prepare_mrc_cache(struct pei_data *pei_data) { struct region_device rdev; - // preset just in case there is an error + /* Preset just in case there is an error */ pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) - /* error message printed in find_current_mrc_cache */ + /* Error message printed in find_current_mrc_cache */ return; pei_data->mrc_input = rdev_mmap_full(&rdev); pei_data->mrc_input_len = region_device_sz(&rdev); - printk(BIOS_DEBUG, "%s: at %p, size %x\n", - __func__, pei_data->mrc_input, pei_data->mrc_input_len); + printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input, + pei_data->mrc_input_len); } static const char *ecc_decoder[] = { "inactive", "active on IO", "disabled on IO", - "active" + "active", }; -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ +/* Print out the memory controller configuration, as per the values in its registers. */ static void report_memory_config(void) { - u32 addr_decoder_common, addr_decode_ch[2]; + u32 addr_decoder_common, addr_decode_chan[2]; int i; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_chan[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_chan[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, + (addr_decoder_common >> 0) & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); + for (i = 0; i < ARRAY_SIZE(addr_decode_chan); i++) { + u32 ch_conf = addr_decode_chan[i]; + + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", ((ch_conf >> 0) & 0xff) * 256, ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", ((ch_conf >> 17) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", ((ch_conf >> 8) & 0xff) * 256, ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", @@ -123,14 +123,11 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); - /* - * Do not pass MRC data in for recovery mode boot, - * Always pass it in for S3 resume. - */ + /* Do not pass MRC data in for recovery mode boot, always pass it in for S3 resume */ if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) prepare_mrc_cache(pei_data); - /* If MRC data is not found we cannot continue S3 resume. */ + /* If MRC data is not found, we cannot continue S3 resume */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { post_code(POST_RESUME_FAILURE); printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); @@ -141,21 +138,20 @@ void sdram_initialize(struct pei_data *pei_data) pei_data->tx_byte = do_putchar; /* - * Locate and call UEFI System Agent binary. The binary needs to be at - * a fixed offset in the flash and can therefore only reside in the - * COREBOOT fmap region + * Locate and call UEFI System Agent binary. The binary needs to be at a fixed offset + * in the flash and can therefore only reside in the COREBOOT fmap region. */ if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) die("mrc.bin not found!"); + /* We don't care about leaking the mapping */ entry = (unsigned long)rdev_mmap_full(&f.data); if (entry) { int rv; - asm volatile ( - "call *%%ecx\n\t" + asm volatile ("call *%%ecx\n\t" :"=a" (rv) : "c" (entry), "a" (pei_data)); - /* mrc.bin reconfigures USB, so reinit it to have debug */ + /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); @@ -177,13 +173,11 @@ void sdram_initialize(struct pei_data *pei_data) die("UEFI PEI System Agent not found.\n"); } - /* For reference print the System Agent version - * after executing the UEFI PEI stage. - */ - u32 version = MCHBAR32(0x5034); + /* For reference, print the System Agent version after executing the UEFI PEI stage */ + u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - version >> 24, (version >> 16) & 0xff, - (version >> 8) & 0xff, version & 0xff); + (version >> 24) & 0xff, (version >> 16) & 0xff, + (version >> 8) & 0xff, (version >> 0) & 0xff); report_memory_config(); } @@ -191,24 +185,23 @@ void sdram_initialize(struct pei_data *pei_data) void setup_sdram_meminfo(struct pei_data *pei_data) { u32 addr_decode_ch[2]; - struct memory_info* mem_info; + struct memory_info *mem_info; struct dimm_info *dimm; - int ddr_frequency; - int dimm_size; - int ch, d_num; + int ddr_frequency, dimm_size, ch, d_num; int dimm_cnt = 0; mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); if (!mem_info) die("Failed to add memory info to CBMEM.\n"); + memset(mem_info, 0, sizeof(struct memory_info)); - /* FIXME: Do we need to read MCHBAR32(0x5000) ? */ - MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + /* FIXME: Do we need to read MCHBAR32(MAD_CHNL) ? (Answer: Nope) */ + MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100; + ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; for (ch = 0; ch < ARRAY_SIZE(addr_decode_ch); ch++) { u32 ch_conf = addr_decode_ch[ch]; @@ -232,7 +225,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) SPD_DIMM_PART_LEN); dimm->mod_id = (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xFF); + (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xff); dimm->mod_type = SPD_SODIMM; dimm->bus_width = 0x3; /* 64-bit */ dimm_cnt++; From 4b9fa2d6ea6107cf0c94b116dfffa553075fcded Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 13 Mar 2020 00:54:30 -0700 Subject: [PATCH 0425/1463] soc/intel/tigerlake: Update Cpu Ratio settings Add config to override CpuRatio or setting CpuRatio to allowed maximum processor non-turbo ratio. BUG=151175469 BRANCH=none TEST=Build and boot tglrvp and observe there is no extra reset in meminit. Signed-off-by: Srinidhi N Kaushik Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493 Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 12 ++++++++++++ src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 9fc70f8a46..5e010bda59 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -285,6 +285,18 @@ struct soc_intel_tigerlake_config { * This mode makes FSP detect Optane and NVME and set PCIe lane mode * accordingly */ uint8_t HybridStorageMode; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * Only override CPU flex ratio to not boot with non-turbo max. + */ + uint8_t cpu_ratio_override; + }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 3872b61cf7..c5629a51c6 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -15,9 +15,11 @@ #include #include +#include #include #include #include +#include #include #include #include @@ -38,6 +40,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; + /* CpuRatio Settings */ + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1 << i); From a6bff2d8ab4824a95221fda8a3b175c3f4337720 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 12 Mar 2020 01:15:43 -0700 Subject: [PATCH 0426/1463] soc/intel/tigerlake: Enable CNVi through dev_enabled Check for dev enabled status for CNVi and update the UPD accordingly. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro --- src/soc/intel/tigerlake/chip.h | 4 ---- src/soc/intel/tigerlake/fsp_params_tgl.c | 7 +++++-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5e010bda59..87aa8943e4 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -222,10 +222,6 @@ struct soc_intel_tigerlake_config { /* Enable Pch iSCLK */ uint8_t pch_isclk; - /* CNVi */ - uint8_t CnviMode; - uint8_t CnviBtCore; - /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { FORCE_DISABLE, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 7230a4c7e0..33abac4411 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -174,8 +174,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchLanEnable = dev->enabled; /* CNVi */ - params->CnviMode = config->CnviMode; - params->CnviBtCore = config->CnviBtCore; + dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); + if (dev) + params->CnviMode = dev->enabled; + else + params->CnviMode = 0; /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; From cb1e386eabfbf2d0851ed58f97d11a7bab431983 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 13 Mar 2020 17:16:20 +0800 Subject: [PATCH 0427/1463] lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type. Signed-off-by: Eric Lai Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/include/spd_bin.h | 3 +++ src/lib/spd_bin.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c78f7c3267..fb771f2bf8 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -29,6 +29,9 @@ #define SPD_DRAM_LPDDR3_JEDEC 0x0F #define SPD_DRAM_DDR4 0x0C #define SPD_DRAM_LPDDR4 0x10 +#define SPD_DRAM_LPDDR4X 0x11 +#define SPD_DRAM_DDR5 0x12 +#define SPD_DRAM_LPDDR5 0x13 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define DDR3_ORGANIZATION 7 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 35bcb4c2c7..f59e187037 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -36,10 +36,11 @@ static bool use_ddr4_params(int dram_type) case SPD_DRAM_DDR3: case SPD_DRAM_LPDDR3_INTEL: return false; - /* LPDDR3, LPDDR4 and DDR4 share the same attributes */ + /* Below DDR type share the same attributes */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: + case SPD_DRAM_LPDDR4X: return true; default: printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n", @@ -60,6 +61,12 @@ static const char *spd_get_module_type_string(int dram_type) return "DDR4"; case SPD_DRAM_LPDDR4: return "LPDDR4"; + case SPD_DRAM_LPDDR4X: + return "LPDDR4X"; + case SPD_DRAM_DDR5: + return "DDR5"; + case SPD_DRAM_LPDDR5: + return "LPDDR5"; } return "UNKNOWN"; } From 4d5fd77cf82e95b74c80790389c3616de2b81411 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 13 Mar 2020 17:21:59 +0800 Subject: [PATCH 0428/1463] lib/spd_bin: Cleanup spd_get_banks Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes. Signed-off-by: Eric Lai Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/lib/spd_bin.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index f59e187037..4be0051844 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -76,22 +76,15 @@ static int spd_get_banks(const uint8_t spd[], int dram_type) static const int ddr3_banks[4] = { 8, 16, 32, 64 }; static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; - switch (dram_type) { - /* DDR3 and LPDDR3_Intel have the same bank definition */ - case SPD_DRAM_DDR3: - case SPD_DRAM_LPDDR3_INTEL: - if (index >= ARRAY_SIZE(ddr3_banks)) - return -1; - return ddr3_banks[index]; - /* LPDDR3, LPDDR4 and DDR4 have the same bank definition */ - case SPD_DRAM_LPDDR3_JEDEC: - case SPD_DRAM_DDR4: - case SPD_DRAM_LPDDR4: + + if (use_ddr4_params(dram_type)) { if (index >= ARRAY_SIZE(ddr4_banks)) return -1; return ddr4_banks[index]; - default: - return -1; + } else { + if (index >= ARRAY_SIZE(ddr3_banks)) + return -1; + return ddr3_banks[index]; } } From 655dba40559e79fcac520a51819d10cd58c25adf Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 12 Mar 2020 18:35:35 -0700 Subject: [PATCH 0429/1463] soc/intel/tigerlake: Match RP number with TGL EDS Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2. BUG=b:151208838 TEST=build RVP successfully Signed-off-by: Wonkyu Kim Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Srinidhi N Kaushik --- src/soc/intel/tigerlake/acpi/pcie.asl | 68 --------------------------- 1 file changed, 68 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index 0191454a5d..c6cfbce57b 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -312,71 +312,3 @@ Device (RP12) Return (IRQM (RPPN)) } } - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} From 9f111859207faf24406dab335eb1192960e200f9 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Wed, 11 Mar 2020 20:05:52 +0100 Subject: [PATCH 0430/1463] soc/intel/icelake: Correct past participle in comment Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39456 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/icelake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 8dd6bfdcf7..99f606b4e2 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -32,7 +32,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, if (!dev || !dev->enabled) { /* * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. + * is disabled in devicetree.cb. */ m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; From dd57ac2f35954af84e4a20451284bbdeaf7f4aa8 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Wed, 11 Mar 2020 20:14:15 +0100 Subject: [PATCH 0431/1463] soc/intel/icelake: Re-flow comment for 96 characters Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39457 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/icelake/romstage/fsp_params.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 99f606b4e2..5aea2ee8af 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -30,10 +30,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t mask = 0; if (!dev || !dev->enabled) { - /* - * Skip IGD initialization in FSP if device - * is disabled in devicetree.cb. - */ + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb. */ m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; } else { From 599bc6070df30373265108a4c9f75dd1123bf71d Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 14 Mar 2020 01:12:21 +0100 Subject: [PATCH 0432/1463] lib/spd_bin: Add spaces around operator Change-Id: Ic0571d06e94708dd5e151621ab7790f3c9f775c2 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39528 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/lib/spd_bin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 4be0051844..47c6dbd7cb 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -175,7 +175,7 @@ static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) void print_spd_info(uint8_t spd[]) { - char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + char spd_name[DDR4_SPD_PART_LEN + 1] = { 0 }; int type = spd[SPD_DRAM_TYPE]; int banks = spd_get_banks(spd, type); int capmb = spd_get_capmb(spd); From fac491dab703ace198f2b1567b8c862166b72b13 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 6 Mar 2020 12:35:38 +0100 Subject: [PATCH 0433/1463] Docs: Fix link for ASUS P8Z77-M PRO Change-Id: I2b8ff31acc7da2b1ded036604fa4a6b6d6d9cac0 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39349 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/mainboard/asus/p8z77-m_pro.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md index 7c841499fc..2d9f61201e 100644 --- a/Documentation/mainboard/asus/p8z77-m_pro.md +++ b/Documentation/mainboard/asus/p8z77-m_pro.md @@ -163,6 +163,6 @@ easy to remove and reflash. - [Flash chip datasheet][W25Q64FVA1Q] -[ASUS P8Z88-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/ +[ASUS P8Z77-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/ [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf [flashrom]: https://flashrom.org/Flashrom From f897623aac1794c8d94ef10b51e56da8e8c1b8dd Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 6 Mar 2020 12:37:06 +0100 Subject: [PATCH 0434/1463] mb/asus/p8z77-m_pro: Use uppercase for *PRO* Consistently use the official uppercase spelling. Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/mainboard/asus/p8z77-m_pro.md | 6 +++--- src/mainboard/asus/p8z77-m_pro/early_init.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md index 2d9f61201e..110108966b 100644 --- a/Documentation/mainboard/asus/p8z77-m_pro.md +++ b/Documentation/mainboard/asus/p8z77-m_pro.md @@ -1,6 +1,6 @@ -# ASUS P8Z77-M Pro +# ASUS P8Z77-M PRO -This page describes how to run coreboot on the [ASUS P8Z77-M Pro] +This page describes how to run coreboot on the [ASUS P8Z77-M PRO] ## Flashing coreboot @@ -163,6 +163,6 @@ easy to remove and reflash. - [Flash chip datasheet][W25Q64FVA1Q] -[ASUS P8Z77-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/ +[ASUS P8Z77-M PRO]: https://www.asus.com/Motherboards/P8Z77M_PRO/ [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf [flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 6c76a7ac29..d2c23559f3 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -154,7 +154,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) */ usb3_streams }, - /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */ + /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ .ddr3lv_support = 1, /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, * but might cause some system instability ! From 842dd3328d250cc2e42032b4f7b875c2061af360 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 14 Mar 2020 10:37:40 +0100 Subject: [PATCH 0435/1463] nb/intel/i945/raminit: Remove space for correct alignment Change-Id: I35d14541e0eab4474b03a9d2f114c7aa3e92918c Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39535 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/i945/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cb3b943171..2489aa7cab 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2029,7 +2029,7 @@ static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo) u32 chan0 = 0, chan1 = 0; int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; - chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); From d789b658f768ccb94641527046ddb5728d980b3f Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 14 Mar 2020 11:50:34 +0100 Subject: [PATCH 0436/1463] nb/intel/i945/raminit: Use boolean type for helper variables Change-Id: I465a68f281534cd9fc5a7bde02c32d1353cfdaed Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39536 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/northbridge/intel/i945/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 2489aa7cab..c50b1d850e 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2027,7 +2027,7 @@ static void sdram_pre_jedec_initialization(void) static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo) { u32 chan0 = 0, chan1 = 0; - int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; + bool chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); From 5ddce58bffa99fcc00193cc7d9478eeb4cc3b8b2 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 13 Mar 2020 17:42:03 +0800 Subject: [PATCH 0437/1463] ec/google/wilco: Store LID status into LIDS and change device name Store LID status into LIDS and change device name to LID0. Then Intel driver can reference it. BUG=b:151134069 TEST=check LID status by evtest Signed-off-by: Eric Lai Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/39497 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/ec/google/wilco/acpi/ec.asl | 3 +++ src/ec/google/wilco/acpi/event.asl | 2 +- src/ec/google/wilco/acpi/lid.asl | 5 +++-- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 8fcd0dd5c2..fddd730258 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -60,6 +60,9 @@ Device (EC0) /* Initialize UCSI */ ^UCSI.INIT () + + // Initialize LID switch state + Store (R (P1LC), \LIDS) } /* diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index f6534d3773..8f6a12333d 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -57,7 +57,7 @@ Method (ECQ1, 1, Serialized) /* LID state changed */ If (EBIT (E1LD, Arg0)) { Printf ("Lid State Changed") - Notify (^LID, 0x80) + Notify (^LID0, 0x80) } /* Power Event */ diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl index 818e1355c0..1697e1da5a 100644 --- a/src/ec/google/wilco/acpi/lid.asl +++ b/src/ec/google/wilco/acpi/lid.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -Device (LID) +Device (LID0) { Name (_HID, EisaId ("PNP0C0D")) Name (_UID, 1) @@ -22,6 +22,7 @@ Device (LID) Method (_LID, 0, NotSerialized) { - Return (R (P1LC)) + Store (R (P1LC), \LIDS) + Return (\LIDS) } } From fdd5afde4944ab173e8d9a9db8cd19586ff09572 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 14 Mar 2020 12:05:54 +0100 Subject: [PATCH 0438/1463] util/inteltool: gpio: drop dead code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop dummy entry. Change-Id: Ic2184453c628c034e40ba877791fab4b7fe1d934 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39558 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/inteltool/gpio.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 9610fd6cb3..55c32baf43 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1076,9 +1076,6 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); return 1; - case 0x1234: // Dummy for non-existent functionality - printf("This southbridge does not have GPIOBASE.\n"); - return 1; default: printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n"); return 1; From 2aff3005e0ebdf99c0a0f063f023536f601a879b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 14 Mar 2020 12:06:12 +0100 Subject: [PATCH 0439/1463] util/inteltool: powermgt: drop dead code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop dummy entry. Change-Id: I1257115bd73fe90c6435116c8705cb5c98d945e1 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39559 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- util/inteltool/powermgt.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 8da12d2826..9933b04891 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -849,10 +849,6 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) pm_registers = sunrise_pm_registers; size = ARRAY_SIZE(sunrise_pm_registers); break; - - case 0x1234: // Dummy for non-existent functionality - printf("This southbridge does not have PMBASE.\n"); - return 1; default: printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); return 1; From 95de2317c6c6379e43d3b3c27d34eb66198dbe0a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 Feb 2020 13:08:53 +0100 Subject: [PATCH 0440/1463] nb/intel/nehalem: Rename to ironlake The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/model_2065x/acpi.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x.h | 2 +- src/cpu/intel/model_2065x/model_2065x_init.c | 2 +- src/cpu/x86/Kconfig | 2 +- src/drivers/intel/gma/Kconfig | 6 +++--- src/mainboard/lenovo/t410/Kconfig | 2 +- src/mainboard/lenovo/t410/devicetree.cb | 2 +- src/mainboard/lenovo/t410/dsdt.asl | 2 +- src/mainboard/lenovo/t410/romstage.c | 2 +- src/mainboard/lenovo/t410/smihandler.c | 2 +- src/mainboard/lenovo/x201/Kconfig | 2 +- src/mainboard/lenovo/x201/devicetree.cb | 2 +- src/mainboard/lenovo/x201/dsdt.asl | 2 +- src/mainboard/lenovo/x201/mainboard.c | 2 +- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x201/smihandler.c | 2 +- src/mainboard/packardbell/ms2290/Kconfig | 2 +- src/mainboard/packardbell/ms2290/devicetree.cb | 2 +- src/mainboard/packardbell/ms2290/dsdt.asl | 2 +- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/packardbell/ms2290/romstage.c | 2 +- src/mainboard/packardbell/ms2290/smihandler.c | 2 +- .../intel/{nehalem => ironlake}/Kconfig | 4 ++-- .../intel/{nehalem => ironlake}/Makefile.inc | 2 +- .../intel/{nehalem => ironlake}/acpi.c | 2 +- .../{nehalem => ironlake}/acpi/hostbridge.asl | 0 .../nehalem.asl => ironlake/acpi/ironlake.asl} | 2 +- .../intel/{nehalem => ironlake}/bootblock.c | 0 .../intel/{nehalem => ironlake}/chip.h | 8 ++++---- .../intel/{nehalem => ironlake}/early_init.c | 10 +++++----- .../intel/{nehalem => ironlake}/finalize.c | 4 ++-- .../intel/{nehalem => ironlake}/gma.c | 8 ++++---- .../{nehalem/nehalem.h => ironlake/ironlake.h} | 18 +++++++++--------- .../intel/{nehalem => ironlake}/memmap.c | 2 +- .../intel/{nehalem => ironlake}/northbridge.c | 8 ++++---- .../intel/{nehalem => ironlake}/raminit.c | 4 ++-- .../intel/{nehalem => ironlake}/raminit.h | 2 +- .../{nehalem => ironlake}/raminit_tables.c | 0 .../{nehalem => ironlake}/raminit_tables.h | 0 .../intel/{nehalem => ironlake}/romstage.c | 8 ++++---- .../intel/{nehalem => ironlake}/smi.c | 2 +- src/southbridge/intel/common/firmware/Kconfig | 4 ++-- src/southbridge/intel/ibexpeak/early_cir.c | 4 ++-- src/southbridge/intel/ibexpeak/early_pch.c | 4 ++-- src/southbridge/intel/ibexpeak/smihandler.c | 4 ++-- .../board-status.html/tohtml.sh | 2 +- 47 files changed, 77 insertions(+), 77 deletions(-) rename src/northbridge/intel/{nehalem => ironlake}/Kconfig (95%) rename src/northbridge/intel/{nehalem => ironlake}/Makefile.inc (94%) rename src/northbridge/intel/{nehalem => ironlake}/acpi.c (98%) rename src/northbridge/intel/{nehalem => ironlake}/acpi/hostbridge.asl (100%) rename src/northbridge/intel/{nehalem/acpi/nehalem.asl => ironlake/acpi/ironlake.asl} (98%) rename src/northbridge/intel/{nehalem => ironlake}/bootblock.c (100%) rename src/northbridge/intel/{nehalem => ironlake}/chip.h (89%) rename src/northbridge/intel/{nehalem => ironlake}/early_init.c (96%) rename src/northbridge/intel/{nehalem => ironlake}/finalize.c (94%) rename src/northbridge/intel/{nehalem => ironlake}/gma.c (96%) rename src/northbridge/intel/{nehalem/nehalem.h => ironlake/ironlake.h} (94%) rename src/northbridge/intel/{nehalem => ironlake}/memmap.c (98%) rename src/northbridge/intel/{nehalem => ironlake}/northbridge.c (98%) rename src/northbridge/intel/{nehalem => ironlake}/raminit.c (99%) rename src/northbridge/intel/{nehalem => ironlake}/raminit.h (97%) rename src/northbridge/intel/{nehalem => ironlake}/raminit_tables.c (100%) rename src/northbridge/intel/{nehalem => ironlake}/raminit_tables.h (100%) rename src/northbridge/intel/{nehalem => ironlake}/romstage.c (92%) rename src/northbridge/intel/{nehalem => ironlake}/smi.c (97%) diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 904b61bba0..1849f19a3e 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -10,7 +10,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 51acc278cc..1868876909 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -216,7 +216,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3; + clock_max = ratio_max * IRONLAKE_BCLK + ratio_max / 3; /* Calculate CPU TDP in mW */ power_max = 25000; @@ -277,7 +277,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * NEHALEM_BCLK + ratio / 3; + clock = ratio * IRONLAKE_BCLK + ratio / 3; acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f6982d9ee9..730ab35e94 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -16,7 +16,7 @@ #define _CPU_INTEL_MODEL_2065X_H /* Nehalem bus clock is fixed at 133MHz */ -#define NEHALEM_BCLK 133 +#define IRONLAKE_BCLK 133 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index a9c28f6fdc..b73694318a 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -197,7 +197,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK); } static void set_energy_perf_bias(u8 policy) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index dd7bb30146..4260278e02 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -140,7 +140,7 @@ config SMM_LAPIC_REMAP_MITIGATION bool default y if NORTHBRIDGE_INTEL_I945 default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_IRONLAKE default n config SERIALIZED_SMM_INITIALIZATION diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index d57faa0fa8..b66d8753ad 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -66,7 +66,7 @@ config GFX_GMA_ANALOG_I2C_HDMI_D config GFX_GMA def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ - || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ + || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ @@ -83,7 +83,7 @@ config GFX_GMA_PANEL_1_ON_EDP config GFX_GMA_PANEL_1_ON_LVDS bool depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT - default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE default n if GFX_GMA @@ -99,7 +99,7 @@ config GFX_GMA_GENERATION default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL - default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE + default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X config GFX_GMA_PANEL_1_PORT diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 5d60565eb5..86cfce8dfc 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T410 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 808e05759e..e18ec385d2 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index 4f67bd8150..f8e989ad1b 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 4908ec5e02..f15a919aa7 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index 91cb0ce2d6..70a9e5dd22 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a94d24ed75..42cf8f956e 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_X201 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 7f1f55a25b..d347261330 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 4f67bd8150..f8e989ad1b 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 4cd3bdee5f..ebfe7a8bc6 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include "dock.h" #include diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index aec63dbfc9..8bf6f902ca 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -21,7 +21,7 @@ #include #include -#include +#include const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 91cb0ce2d6..70a9e5dd22 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 819400257b..4fc971f0ae 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -3,7 +3,7 @@ if BOARD_PACKARDBELL_MS2290 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bf1c171222..21b6a6dc51 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index bbd2b2938c..e53d728b74 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -39,7 +39,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 169b0ac7f8..805eecbece 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 1f9d22982a..03ea86d01c 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -19,7 +19,7 @@ #include #include -#include +#include /* Seems copied from Lenovo Thinkpad x201, might be wrong */ const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index bc5067be1e..2d77564efe 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/ironlake/Kconfig similarity index 95% rename from src/northbridge/intel/nehalem/Kconfig rename to src/northbridge/intel/ironlake/Kconfig index cfd7fe248d..512149bfee 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -config NORTHBRIDGE_INTEL_NEHALEM +config NORTHBRIDGE_INTEL_IRONLAKE bool select CPU_INTEL_MODEL_2065X select VGA @@ -22,7 +22,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP -if NORTHBRIDGE_INTEL_NEHALEM +if NORTHBRIDGE_INTEL_IRONLAKE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc similarity index 94% rename from src/northbridge/intel/nehalem/Makefile.inc rename to src/northbridge/intel/ironlake/Makefile.inc index 225f0ce812..1fde37d9f6 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/ironlake/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE),y) bootblock-y += bootblock.c diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/ironlake/acpi.c similarity index 98% rename from src/northbridge/intel/nehalem/acpi.c rename to src/northbridge/intel/ironlake/acpi.c index 43b13c286a..198b6ecbc5 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -21,7 +21,7 @@ #include #include #include -#include "nehalem.h" +#include "ironlake.h" unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl similarity index 100% rename from src/northbridge/intel/nehalem/acpi/hostbridge.asl rename to src/northbridge/intel/ironlake/acpi/hostbridge.asl diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl similarity index 98% rename from src/northbridge/intel/nehalem/acpi/nehalem.asl rename to src/northbridge/intel/ironlake/acpi/ironlake.asl index 404801ec3f..659234b4aa 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "../nehalem.h" +#include "../ironlake.h" #include "hostbridge.asl" #include diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c similarity index 100% rename from src/northbridge/intel/nehalem/bootblock.c rename to src/northbridge/intel/ironlake/bootblock.c diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/ironlake/chip.h similarity index 89% rename from src/northbridge/intel/nehalem/chip.h rename to src/northbridge/intel/ironlake/chip.h index a9d136baad..dad03dac1b 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H -#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H +#ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H +#define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H #include @@ -25,7 +25,7 @@ * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ -struct northbridge_intel_nehalem_config { +struct northbridge_intel_ironlake_config { u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ @@ -48,4 +48,4 @@ struct northbridge_intel_nehalem_config { u16 pci_mmio_size; }; -#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ +#endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/ironlake/early_init.c similarity index 96% rename from src/northbridge/intel/nehalem/early_init.c rename to src/northbridge/intel/ironlake/early_init.c index a809121310..fe4ad7feff 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -26,9 +26,9 @@ #include #include -#include "nehalem.h" +#include "ironlake.h" -static void nehalem_setup_bars(void) +static void ironlake_setup_bars(void) { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); @@ -114,7 +114,7 @@ static void early_cpu_init (void) wrmsr(IA32_MISC_ENABLE, m); } -void nehalem_early_initialization(int chipset_type) +void ironlake_early_initialization(int chipset_type) { u32 capid0_a; u8 reg8; @@ -126,14 +126,14 @@ void nehalem_early_initialization(int chipset_type) reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); reg8 &= ~7; /* Clear 2:0 */ - if (chipset_type == NEHALEM_MOBILE) + if (chipset_type == IRONLAKE_MOBILE) reg8 |= 1; /* Set bit 0 */ pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); } /* Setup all BARs required for early PCIe and raminit */ - nehalem_setup_bars(); + ironlake_setup_bars(); s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/ironlake/finalize.c similarity index 94% rename from src/northbridge/intel/nehalem/finalize.c rename to src/northbridge/intel/ironlake/finalize.c index c03b067cbf..f76124be76 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ -#include "nehalem.h" +#include "ironlake.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) -void intel_nehalem_finalize_smm(void) +void intel_ironlake_finalize_smm(void) { MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/ironlake/gma.c similarity index 96% rename from src/northbridge/intel/nehalem/gma.c rename to src/northbridge/intel/ironlake/gma.c index d717e48821..27c0827ead 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -33,7 +33,7 @@ #include #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do @@ -93,7 +93,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) static void gma_pm_init_post_vbios(struct device *dev) { - struct northbridge_intel_nehalem_config *conf = dev->chip_info; + struct northbridge_intel_ironlake_config *conf = dev->chip_info; u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); @@ -177,7 +177,7 @@ static void gma_func0_init(struct device *dev) if (!acpi_is_wakeup_s3() && CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - struct northbridge_intel_nehalem_config *conf = dev->chip_info; + struct northbridge_intel_ironlake_config *conf = dev->chip_info; int lightup_ok; printk(BIOS_SPEW, "Initializing VGA without OPROM."); @@ -223,7 +223,7 @@ intel_gma_get_controller_info(void) if (!dev) { return NULL; } - struct northbridge_intel_nehalem_config *chip = dev->chip_info; + struct northbridge_intel_ironlake_config *chip = dev->chip_info; return &chip->gfx; } diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/ironlake/ironlake.h similarity index 94% rename from src/northbridge/intel/nehalem/nehalem.h rename to src/northbridge/intel/ironlake/ironlake.h index 493c5b14cd..aa8cb7f4a6 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ +#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ +#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #ifndef __ASSEMBLER__ @@ -99,9 +99,9 @@ typedef struct { #define D1F0_VC0RCTL 0x114 /* Chipset types */ -#define NEHALEM_MOBILE 0 -#define NEHALEM_DESKTOP 1 -#define NEHALEM_SERVER 2 +#define IRONLAKE_MOBILE 0 +#define IRONLAKE_DESKTOP 1 +#define IRONLAKE_SERVER 2 /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 @@ -249,14 +249,14 @@ typedef struct { #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154 -void intel_nehalem_finalize_smm(void); +void intel_ironlake_finalize_smm(void); int bridge_silicon_revision(void); -void nehalem_early_initialization(int chipset_type); -void nehalem_late_initialization(void); +void ironlake_early_initialization(int chipset_type); +void ironlake_late_initialization(void); void mainboard_pre_raminit(void); void mainboard_get_spd_map(u8 *spd_addrmap); #endif #endif -#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ +#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */ diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/ironlake/memmap.c similarity index 98% rename from src/northbridge/intel/nehalem/memmap.c rename to src/northbridge/intel/ironlake/memmap.c index 5de4b80acf..b2d61fe93a 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -23,7 +23,7 @@ #include #include #include -#include "nehalem.h" +#include "ironlake.h" static uintptr_t smm_region_start(void) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c similarity index 98% rename from src/northbridge/intel/nehalem/northbridge.c rename to src/northbridge/intel/ironlake/northbridge.c index 1718307797..fe8eed36c9 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -26,7 +26,7 @@ #include #include #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" #include static int bridge_revision_id = -1; @@ -228,7 +228,7 @@ static void northbridge_init(struct device *dev) } /* Disable unused PEG devices based on devicetree before PCI enumeration */ -static void nehalem_init(void *const chip_info) +static void ironlake_init(void *const chip_info) { u32 deven_mask = UINT32_MAX; const struct device *dev; @@ -287,8 +287,8 @@ static void enable_dev(struct device *dev) } } -struct chip_operations northbridge_intel_nehalem_ops = { +struct chip_operations northbridge_intel_ironlake_ops = { CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") .enable_dev = enable_dev, - .init = nehalem_init, + .init = ironlake_init, }; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/ironlake/raminit.c similarity index 99% rename from src/northbridge/intel/nehalem/raminit.c rename to src/northbridge/intel/ironlake/raminit.c index de02882483..e702e1749e 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -41,7 +41,7 @@ #include #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" #include "raminit.h" #include "raminit_tables.h" @@ -1362,7 +1362,7 @@ static void program_board_delay(struct raminfo *info) static unsigned int get_mmio_size(void) { const struct device *dev; - const struct northbridge_intel_nehalem_config *cfg = NULL; + const struct northbridge_intel_ironlake_config *cfg = NULL; dev = pcidev_path_on_root(HOST_BRIDGE); if (dev) diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/ironlake/raminit.h similarity index 97% rename from src/northbridge/intel/nehalem/raminit.h rename to src/northbridge/intel/ironlake/raminit.h index 9a200d475f..1a55407d39 100644 --- a/src/northbridge/intel/nehalem/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -16,7 +16,7 @@ #ifndef RAMINIT_H #define RAMINIT_H -#include "nehalem.h" +#include "ironlake.h" void chipset_init(const int s3resume); /* spd_addrmap is array of 4 elements: diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/ironlake/raminit_tables.c similarity index 100% rename from src/northbridge/intel/nehalem/raminit_tables.c rename to src/northbridge/intel/ironlake/raminit_tables.c diff --git a/src/northbridge/intel/nehalem/raminit_tables.h b/src/northbridge/intel/ironlake/raminit_tables.h similarity index 100% rename from src/northbridge/intel/nehalem/raminit_tables.h rename to src/northbridge/intel/ironlake/raminit_tables.h diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/ironlake/romstage.c similarity index 92% rename from src/northbridge/intel/nehalem/romstage.c rename to src/northbridge/intel/ironlake/romstage.c index eceb8c2513..fdd71b486a 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -22,12 +22,12 @@ #include #include #include -#include "nehalem.h" +#include "ironlake.h" #include #include #include -#include -#include +#include +#include #include #include #include @@ -44,7 +44,7 @@ void mainboard_romstage_entry(void) enable_lapic(); /* TODO, make this configurable */ - nehalem_early_initialization(NEHALEM_MOBILE); + ironlake_early_initialization(IRONLAKE_MOBILE); early_pch_init(); diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/ironlake/smi.c similarity index 97% rename from src/northbridge/intel/nehalem/smi.c rename to src/northbridge/intel/ironlake/smi.c index c3433a39e7..73cd06281b 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -16,7 +16,7 @@ #include #include #include -#include "nehalem.h" +#include "ironlake.h" #include diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index eb63d34520..134f780825 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -59,7 +59,7 @@ config ME_BIN_PATH config CHECK_ME bool "Verify the integrity of the supplied ME/TXE firmware" default n - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ @@ -71,7 +71,7 @@ config CHECK_ME config USE_ME_CLEANER bool "Strip down the Intel ME/TXE firmware" - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c index 8d7a918d40..9aac07b075 100644 --- a/src/southbridge/intel/ibexpeak/early_cir.c +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include "pch.h" /* This sets up magic Chipset Initialization Registers */ @@ -53,7 +53,7 @@ void pch_setup_cir(int chipset_type) /* Intel 5 Series Chipset and Intel 3400 Series Chipset External Design Specification (EDS) 13.8.1.1 */ - if (chipset_type == NEHALEM_DESKTOP) + if (chipset_type == IRONLAKE_DESKTOP) pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 56331cc696..b455cef179 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include @@ -47,7 +47,7 @@ void early_pch_init(void) early_gpio_init(); enable_smbus(); /* TODO, make this configurable */ - pch_setup_cir(NEHALEM_MOBILE); + pch_setup_cir(IRONLAKE_MOBILE); southbridge_configure_default_intmap(); pch_default_disable(); early_usb_init(mainboard_usb_ports); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 39881889f1..e670c9ade4 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -34,7 +34,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include +#include #include #include @@ -185,6 +185,6 @@ void southbridge_finalize_all(void) { intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); + intel_ironlake_finalize_smm(); intel_model_2065x_finalize_smm(); } diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 8522fd579b..fa89ae962b 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -470,7 +470,7 @@ EOF ;; "") case $northbridge in - INTEL_NEHALEM) + INTEL_IRONLAKE) cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7" socket_nice="?";; RDC_R8610) From 31b7ee42016f7b54c24f30c271b4b93df16bfa10 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 Feb 2020 14:04:28 +0100 Subject: [PATCH 0441/1463] treewide: Replace uses of "Nehalem" The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- Documentation/mainboard/index.md | 2 +- src/cpu/intel/common/fsb.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_2065x/model_2065x.h | 2 +- src/drivers/intel/gma/Kconfig | 2 +- src/include/cpu/intel/em64t101_save_state.h | 2 +- src/northbridge/intel/ironlake/northbridge.c | 6 +++--- src/security/tpm/Kconfig | 2 +- util/docker/coreboot.org-status/board-status.html/tohtml.sh | 2 +- 9 files changed, 11 insertions(+), 11 deletions(-) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 970f18f007..8cb367077e 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -75,7 +75,7 @@ The boards in this section are not real mainboards, but emulators. - [LT1000](libretrend/lt1000.md) -### Nehalem series +### Arrandale series - [T410](lenovo/t410.md) diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 726ab1c240..3dfcd0b0ae 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -48,7 +48,7 @@ static int get_fsb_tsc(int *fsb, int *ratio) *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; - case 0x25: /* Nehalem BCLK fixed at 133MHz */ + case 0x25: /* Arrandale BCLK fixed at 133MHz */ *fsb = 133; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1868876909..af2606cf33 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -338,5 +338,5 @@ void generate_cpu_entries(struct device *device) } struct chip_operations cpu_intel_model_2065x_ops = { - CHIP_NAME("Intel Nehalem CPU") + CHIP_NAME("Intel Arrandale CPU") }; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 730ab35e94..0a07f3c898 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -15,7 +15,7 @@ #ifndef _CPU_INTEL_MODEL_2065X_H #define _CPU_INTEL_MODEL_2065X_H -/* Nehalem bus clock is fixed at 133MHz */ +/* Arrandale bus clock is fixed at 133MHz */ #define IRONLAKE_BCLK 133 #define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index b66d8753ad..68d4edce03 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -39,7 +39,7 @@ config INTEL_GMA_SSC_ALTERNATE_REF To be set by northbridge or mainboard Kconfig. For most platforms, there is no choice, i.e. for i945 and gm45 the SSC reference always differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz - DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's + DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's the same frequency for SSC/non-SSC (120MHz). The only, currently supported platform with a choice seems to be Pineview, where the alternative is 100MHz vs. the default 96MHz. diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 7493c85049..5d3f9edf9d 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -20,7 +20,7 @@ /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: - * - Nehalem + * - Westmere * - SandyBridge * - IvyBridge * - Haswell diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index fe8eed36c9..91bcc1170b 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -263,10 +263,10 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; -static const struct pci_driver mc_driver_44 __pci_driver = { +static const struct pci_driver mc_driver_ard __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Nehalem */ + .device = 0x0044, /* Arrandale DRAM controller */ }; static struct device_operations cpu_bus_ops = { @@ -288,7 +288,7 @@ static void enable_dev(struct device *dev) } struct chip_operations northbridge_intel_ironlake_ops = { - CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") + CHIP_NAME("Intel i7 (Arrandale) integrated Northbridge") .enable_dev = enable_dev, .init = ironlake_init, }; diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 95c0bb9b7d..fbe1735707 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -99,7 +99,7 @@ config TPM_STARTUP_IGNORE_POSTINIT Select this to ignore POSTINIT INVALID return codes on TPM startup. This is useful on platforms where a previous stage issued a TPM startup. Examples of use cases are Intel TXT - or VBOOT on the Intel Nehalem northbridge which issues a + or VBOOT on the Intel Arrandale processor, which issues a CPU-only reset during the romstage. endmenu # Trusted Platform Module (tpm) diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index fa89ae962b..2606af4065 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -471,7 +471,7 @@ EOF "") case $northbridge in INTEL_IRONLAKE) - cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7" + cpu_nice="Intel® 1st Gen (Westmere) Core i3/i5/i7" socket_nice="?";; RDC_R8610) cpu_nice="RDC 8610" From a8305e74a273dc9805b2a688abcf3857ea962110 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 Feb 2020 14:24:04 +0100 Subject: [PATCH 0442/1463] cpu/intel/model_2065x: Add missing CPU IDs The missing CPU IDs were found on CPU-World's database: - 0x20650: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132688 - 0x20651: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132689 - 0x20652: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132690 - 0x20654: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132692 - 0x20655: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132693 Note that these CPUs are not Nehalem, but rather Arrandale on laptops and Clarkdale on desktops, so also update the comments accordingly. Change-Id: I285961b62b9a8ada5a1659cd9ad75f7075259664 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38943 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index b73694318a..e35d1e748d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -342,9 +342,13 @@ static struct device_operations cpu_dev_ops = { .init = model_2065x_init, }; +/* Arrandale / Clarkdale CPU IDs */ static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x20652 }, /* Intel Nehalem */ - { X86_VENDOR_INTEL, 0x20655 }, /* Intel Nehalem */ + { X86_VENDOR_INTEL, 0x20650 }, + { X86_VENDOR_INTEL, 0x20651 }, + { X86_VENDOR_INTEL, 0x20652 }, + { X86_VENDOR_INTEL, 0x20654 }, + { X86_VENDOR_INTEL, 0x20655 }, { 0, 0 }, }; From ee1739cd004e656a8f8a890e6ee9094f770770ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 21:59:21 +0100 Subject: [PATCH 0443/1463] util/inteltool: powermgt: initialize register size variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize register size variables to prevent segfaults. Change-Id: Ib89bf6f7c7582efdea1c54d1316ed8f33a87cfcc Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39513 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/inteltool/powermgt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 9933b04891..2dfc05d64f 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -669,7 +669,7 @@ static const io_register_t i63xx_pm_registers[] = { int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) { - size_t i, size; + size_t i, size = 0; uint16_t pmbase; const io_register_t *pm_registers; uint64_t pwrmbase_phys = 0; From 099975debd89e72a1f2ea3a62dc1b9685b95533f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 18:48:16 +0100 Subject: [PATCH 0444/1463] util/inteltool: powermgt: rename variable for consistency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename size variable for consistency with the other subsystems. Change-Id: I9407193ac9e34685362619cfd45384156e2385c3 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39507 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/inteltool/powermgt.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 2dfc05d64f..54a3045b84 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -669,7 +669,7 @@ static const io_register_t i63xx_pm_registers[] = { int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) { - size_t i, size = 0; + size_t i, pm_registers_size = 0; uint16_t pmbase; const io_register_t *pm_registers; uint64_t pwrmbase_phys = 0; @@ -757,13 +757,13 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; - size = ARRAY_SIZE(pch_pm_registers); + pm_registers_size = ARRAY_SIZE(pch_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH10: case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = ich10_pm_registers; - size = ARRAY_SIZE(ich10_pm_registers); + pm_registers_size = ARRAY_SIZE(ich10_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: @@ -772,7 +772,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_NM10: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich7_pm_registers; - size = ARRAY_SIZE(ich7_pm_registers); + pm_registers_size = ARRAY_SIZE(ich7_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH9DH: case PCI_DEVICE_ID_INTEL_ICH9DO: @@ -782,39 +782,39 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_ICH9ME: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich9_pm_registers; - size = ARRAY_SIZE(ich9_pm_registers); + pm_registers_size = ARRAY_SIZE(ich9_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: case PCI_DEVICE_ID_INTEL_ICH8ME: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich8_pm_registers; - size = ARRAY_SIZE(ich8_pm_registers); + pm_registers_size = ARRAY_SIZE(ich8_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH6: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich6_pm_registers; - size = ARRAY_SIZE(ich6_pm_registers); + pm_registers_size = ARRAY_SIZE(ich6_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH5: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich5_pm_registers; - size = ARRAY_SIZE(ich5_pm_registers); + pm_registers_size = ARRAY_SIZE(ich5_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH4: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich4_pm_registers; - size = ARRAY_SIZE(ich4_pm_registers); + pm_registers_size = ARRAY_SIZE(ich4_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH2: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich2_pm_registers; - size = ARRAY_SIZE(ich2_pm_registers); + pm_registers_size = ARRAY_SIZE(ich2_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH0: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich0_pm_registers; - size = ARRAY_SIZE(ich0_pm_registers); + pm_registers_size = ARRAY_SIZE(ich0_pm_registers); break; case PCI_DEVICE_ID_INTEL_82371XX: acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 3); @@ -826,13 +826,13 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) pci_free_dev(acpi); pm_registers = i82371xx_pm_registers; - size = ARRAY_SIZE(i82371xx_pm_registers); + pm_registers_size = ARRAY_SIZE(i82371xx_pm_registers); break; case PCI_DEVICE_ID_INTEL_I63XX: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = i63xx_pm_registers; - size = ARRAY_SIZE(i63xx_pm_registers); + pm_registers_size = ARRAY_SIZE(i63xx_pm_registers); break; case PCI_DEVICE_ID_INTEL_CM236: @@ -847,7 +847,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) pci_free_dev(acpi); pm_registers = sunrise_pm_registers; - size = ARRAY_SIZE(sunrise_pm_registers); + pm_registers_size = ARRAY_SIZE(sunrise_pm_registers); break; default: printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); @@ -856,7 +856,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) printf("PMBASE = 0x%04x (IO)\n\n", pmbase); - for (i = 0; i < size; i++) { + for (i = 0; i < pm_registers_size; i++) { switch (pm_registers[i].size) { case 8: printf("pmbase+0x%04x: 0x%08x (%s)\n" From 39ff703aa989ebdc056dd27e181fd135a551f522 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 9 Mar 2020 21:39:44 +0100 Subject: [PATCH 0445/1463] nb/intel/pineview: Clean up code and comments - Reformat some lines of code - Put names to all MCHBAR registers in a separate file - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) - Align a bunch of things Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected. Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/pineview/acpi.c | 4 +- src/northbridge/intel/pineview/bootblock.c | 2 +- src/northbridge/intel/pineview/early_init.c | 111 +- src/northbridge/intel/pineview/gma.c | 111 +- src/northbridge/intel/pineview/iomap.h | 1 + src/northbridge/intel/pineview/mchbar_regs.h | 578 +++++ src/northbridge/intel/pineview/memmap.c | 39 +- src/northbridge/intel/pineview/northbridge.c | 45 +- src/northbridge/intel/pineview/pineview.h | 35 +- src/northbridge/intel/pineview/raminit.c | 1977 +++++++++--------- src/northbridge/intel/pineview/romstage.c | 17 +- 11 files changed, 1789 insertions(+), 1131 deletions(-) create mode 100644 src/northbridge/intel/pineview/mchbar_regs.h diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 2e12305e0b..c3e50ee86a 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -31,8 +31,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; max_buses = length >> 20; - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, + max_buses - 1); return current; } diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 98085a7406..83917c2332 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -20,6 +20,6 @@ void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); } diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index daf425e4a4..c3969f26a4 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -22,14 +22,10 @@ #include #include -#define LPC PCI_DEV(0, 0x1f, 0) -#define D0F0 PCI_DEV(0, 0, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) -#define PCI_GCFC 0xf0 -#define MCH_GCFGC 0xc8c -#define CRCLK_PINEVIEW 0x02 -#define CDCLK_PINEVIEW 0x10 -#define MCH_HPLLVCO 0xc38 +#define CRCLK_PINEVIEW 0x02 +#define CDCLK_PINEVIEW 0x10 static void early_graphics_setup(void) { @@ -40,17 +36,18 @@ static void early_graphics_setup(void) const struct device *d0f0 = pcidev_on_root(0, 0); const struct northbridge_intel_pineview_config *config = d0f0->chip_info; - pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); + pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN); - /* vram size from CMOS option */ + /* Fetch VRAM size from CMOS option */ if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) reg8 = 0; /* 0 for 8MB */ - /* make sure no invalid setting is used */ + + /* Ensure the setting is valid */ if (reg8 > 6) reg8 = 0; + /* Select 1M GTT */ - pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8) - | ((reg8 + 3) << 4)); + pci_write_config16(HOST_BRIDGE, GGC, (1 << 8) | ((reg8 + 3) << 4)); printk(BIOS_SPEW, "Set GFX clocks..."); reg16 = MCHBAR16(MCH_GCFGC); @@ -61,10 +58,10 @@ static void early_graphics_setup(void) MCHBAR16(MCH_GCFGC) = reg16; /* Graphics core */ - reg8 = MCHBAR8(MCH_HPLLVCO); + reg8 = MCHBAR8(HPLLVCO); reg8 &= 0x7; - reg16 = pci_read_config16(PCI_DEV(0,2,0), 0xcc) & ~0x1ff; + reg16 = pci_read_config16(GMCH_IGD, 0xcc) & ~0x1ff; if (reg8 == 0x4) { /* 2666MHz */ @@ -77,60 +74,58 @@ static void early_graphics_setup(void) reg16 |= 0xad; } - pci_write_config16(PCI_DEV(0,2,0), 0xcc, reg16); + pci_write_config16(GMCH_IGD, 0xcc, reg16); - pci_write_config8(PCI_DEV(0,2,0), 0x62, - pci_read_config8(PCI_DEV(0,2,0), 0x62) & ~0x3); - pci_write_config8(PCI_DEV(0,2,0), 0x62, - pci_read_config8(PCI_DEV(0,2,0), 0x62) | 2); + pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) & ~0x3); + pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) | 2); if (config->use_crt) { /* Enable VGA */ - MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 15); + MCHBAR32_OR(DACGIOCTRL1, 1 << 15); } else { /* Disable VGA */ - MCHBAR32(0xb08) = MCHBAR32(0xb08) & ~(1 << 15); + MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15)); } if (config->use_lvds) { /* Enable LVDS */ - reg32 = MCHBAR32(0x3004); + reg32 = MCHBAR32(LVDSICR2); reg32 &= ~0xf1000000; - reg32 |= 0x90000000; - MCHBAR32(0x3004) = reg32; - MCHBAR32(0x3008) = MCHBAR32(0x3008) | (1 << 9); + reg32 |= 0x90000000; + MCHBAR32(LVDSICR2) = reg32; + MCHBAR32_OR(IOCKTRR1, 1 << 9); } else { /* Disable LVDS */ - MCHBAR32(0xb08) = MCHBAR32(0xb08) | (3 << 25); + MCHBAR32_OR(DACGIOCTRL1, 3 << 25); } - MCHBAR32(0xff4) = 0x0c6db8b5f; - MCHBAR16(0xff8) = 0x24f; + MCHBAR32(CICTRL) = 0xc6db8b5f; + MCHBAR16(CISDCTRL) = 0x024f; - MCHBAR32(0xb08) = MCHBAR32(0xb08) & 0xffffff00; - MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 5); + MCHBAR32_AND(DACGIOCTRL1, 0xffffff00); + MCHBAR32_OR(DACGIOCTRL1, 1 << 5); /* Legacy backlight control */ - pci_write_config8(PCI_DEV(0, 2, 0), 0xf4, 0x4c); + pci_write_config8(GMCH_IGD, 0xf4, 0x4c); } static void early_misc_setup(void) { - MCHBAR32(0x30); - MCHBAR32(0x30) = 0x21800; - DMIBAR32(0x2c) = 0x86000040; + MCHBAR32(HIT0); + MCHBAR32(HIT0) = 0x00021800; + DMIBAR32(HTBONUS1) = 0x86000040; pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000); early_graphics_setup(); - MCHBAR32(0x40); - MCHBAR32(0x40) = 0x0; - MCHBAR32(0x40); - MCHBAR32(0x40) = 0x8; + MCHBAR32(HIT4); + MCHBAR32(HIT4) = 0; + MCHBAR32(HIT4); + MCHBAR32(HIT4) = 8; - pci_write_config8(LPC, 0x8, 0x1d); - pci_write_config8(LPC, 0x8, 0x0); + pci_write_config8(LPC_DEV, 0x08, 0x1d); + pci_write_config8(LPC_DEV, 0x08, 0x00); RCBA32(0x3410) = 0x00020465; pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); @@ -138,41 +133,41 @@ static void early_misc_setup(void) pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1); - RCBA32(0x3100) = 0x42210; + RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; RCBA32(0x310c) = 0x00214321; - RCBA32(0x3110) = 0x1; + RCBA32(0x3110) = 1; RCBA32(0x3140) = 0x01460132; RCBA32(0x3142) = 0x02370146; RCBA32(0x3144) = 0x32010237; RCBA32(0x3146) = 0x01463201; - RCBA32(0x3148) = 0x146; + RCBA32(0x3148) = 0x00000146; } static void pineview_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); - pci_write_config8(D0F0, 0x8, 0x69); + pci_write_config8(HOST_BRIDGE, 0x08, 0x69); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(D0F0, PAM0, 0x30); - pci_write_config8(D0F0, PAM1, 0x33); - pci_write_config8(D0F0, PAM2, 0x33); - pci_write_config8(D0F0, PAM3, 0x33); - pci_write_config8(D0F0, PAM4, 0x33); - pci_write_config8(D0F0, PAM5, 0x33); - pci_write_config8(D0F0, PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); } -void pineview_early_initialization(void) +void pineview_early_init(void) { /* Print some chipset specific information */ printk(BIOS_DEBUG, "Intel Pineview northbridge\n"); @@ -180,10 +175,10 @@ void pineview_early_initialization(void) /* Setup all BARs required for early PCIe and raminit */ pineview_setup_bars(); - /* Miscellaneous set up */ + /* Miscellaneous setup */ early_misc_setup(); - /* Change port80 to LPC */ + /* Route port80 to LPC */ RCBA32(GCS) &= (~0x04); RCBA32(0x2010) |= (1 << 10); } diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index dd6cb32596..db2bb825b7 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -36,7 +36,7 @@ #include "chip.h" #include "pineview.h" -#define GTTSIZE (512*1024) +#define GTTSIZE (512 * 1024) #define PGETBL2_CTL 0x20c4 #define PGETBL2_1MB (1 << 8) @@ -54,7 +54,7 @@ ADPA_CRT_HOTPLUG_VOLREF_325MV | \ ADPA_CRT_HOTPLUG_ENABLE) -static struct resource *gtt_res = NULL; +static struct resource *gtt_res = NULL; static struct resource *mmio_res = NULL; uintptr_t gma_get_gnvs_aslb(const void *gnvs) @@ -126,8 +126,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + 0x7041c, 0x0); @@ -137,14 +136,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, write32(mmio + PIPESRC(1), 0x027f01df); vga_misc_write(0x67); - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff + const u8 cr[25] = { + 0x5f, 0x4f, 0x50, 0x82, 0x55, + 0x81, 0xbf, 0x1f, 0x00, 0x4f, + 0x0d, 0x0e, 0x00, 0x00, 0x00, + 0x00, 0x9c, 0x8e, 0x8f, 0x28, + 0x1f, 0x96, 0xb9, 0xa3, 0xff, }; vga_cr_write(0x11, 0); - for (i = 0; i <= 0x18; i++) + for (i = 0; i < ARRAY_SIZE(cr); i++) vga_cr_write(i, cr[i]); // Disable screen memory to prevent garbage from appearing. @@ -157,15 +158,14 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); + | 0x400601); + mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); + | 0x400601); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -173,8 +173,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + HTOTAL(1), 0x031f027f); write32(mmio + HBLANK(1), 0x03170287); @@ -183,23 +182,12 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, write32(mmio + VBLANK(1), 0x020401e7); write32(mmio + VSYNC(1), 0x01eb01e9); - write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); - write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); - - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + write32(mmio + HTOTAL(0), ((hactive - 1) << 16) | (hactive - 1)); + write32(mmio + HBLANK(0), ((hactive - 1) << 16) | (hactive - 1)); + write32(mmio + HSYNC(0), ((hactive - 1) << 16) | (hactive - 1)); + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) | (vactive - 1)); + write32(mmio + VSYNC(0), ((vactive - 1) << 16) | (vactive - 1)); write32(mmio + PF_WIN_POS(0), 0); @@ -228,8 +216,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + DSPFW3, 0x7f3f00c1); write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); @@ -246,16 +233,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, temp = read32(mmio + PGETBL2_CTL); printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp); - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); + /* Clear interrupts */ + write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); - write32(mmio + IIR, 0xffffffff); - write32(mmio + IMR, 0xffffffff); - write32(mmio + EIR, 0xffffffff); + write32(mmio + IIR, 0xffffffff); + write32(mmio + IMR, 0xffffffff); + write32(mmio + EIR, 0xffffffff); vga_textmode_init(); - /* Enable screen memory. */ + /* Enable screen memory */ vga_sr_write(1, vga_sr_read(1) & ~0x20); } @@ -269,7 +256,7 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { - /* PCI Init, will run VBIOS */ + /* PCI init, will run VBIOS */ pci_dev_init(dev); } else { u32 physbase; @@ -280,14 +267,14 @@ static void gma_func0_init(struct device *dev) /* Find base addresses */ mmio_res = find_resource(dev, 0x10); - gtt_res = find_resource(dev, 0x1c); - pio_res = find_resource(dev, 0x14); + gtt_res = find_resource(dev, 0x1c); + pio_res = find_resource(dev, 0x14); physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) { if (vga_disable) { - printk(BIOS_INFO, - "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: " + "skipping NATIVE graphic init\n"); } else { printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n", mmio_res->base); @@ -307,7 +294,7 @@ static void gma_func0_init(struct device *dev) const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { - struct device *dev = pcidev_on_root(0x2, 0); + struct device *dev = pcidev_on_root(2, 0); if (!dev) { printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n"); return NULL; @@ -316,10 +303,8 @@ const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) return &chip->gfx; } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) +static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, + struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; global_nvs_t *gnvs; @@ -352,25 +337,25 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = 0, - .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = &gma_pci_ops, - .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = NULL, + .init = gma_func0_init, + .scan_bus = NULL, + .enable = NULL, + .ops_pci = &gma_pci_ops, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { - 0xa001, 0 + 0xa001, 0, }; static const struct pci_driver gma __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h index 4076e1f08d..9dd478f3db 100644 --- a/src/northbridge/intel/pineview/iomap.h +++ b/src/northbridge/intel/pineview/iomap.h @@ -20,5 +20,6 @@ #define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_PMIOBAR 0x00000400 #endif /* PINEVIEW_IOMAP_H */ diff --git a/src/northbridge/intel/pineview/mchbar_regs.h b/src/northbridge/intel/pineview/mchbar_regs.h new file mode 100644 index 0000000000..2c83b02406 --- /dev/null +++ b/src/northbridge/intel/pineview/mchbar_regs.h @@ -0,0 +1,578 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Angel Pons + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINEVIEW_MCHBAR_REGS_H__ +#define __PINEVIEW_MCHBAR_REGS_H__ + +/* Indexed register helper macros */ +#define Gz(r, z) ((r) + ((z) * 0x100)) +#define Ly(r, y) ((r) + ((y) * 4)) +#define Cx(r, x) ((r) + ((x) * 0x400)) +#define CxLy(r, x, y) (((x) * 0x400) + (r) + ((y) * 4)) + +#define HTPACER 0x10 +#define HPWRCTL1 0x14 +#define HPWRCTL2 0x18 +#define HPWRCTL3 0x1C +#define HTCLKGTCTL 0x20 +#define SLIMCFGTMG 0x24 +#define HTBONUS0 0x28 +#define HTBONUS1 0x2C +#define HIT0 0x30 +#define HIT1 0x34 +#define HIT2 0x38 +#define HIT3 0x3C +#define HIT4 0x40 +#define HIT5 0x44 +#define HICLKGTCTL 0x48 +#define HIBONUS 0x4C +#define XTPR0 0x50 +#define XTPR1 0x54 +#define XTPR2 0x58 +#define XTPR3 0x5C +#define XTPR4 0x60 +#define XTPR5 0x64 +#define XTPR6 0x68 +#define XTPR7 0x6C +#define XTPR8 0x70 +#define XTPR9 0x74 +#define XTPR10 0x78 +#define XTPR11 0x7C +#define XTPR12 0x80 +#define XTPR13 0x84 +#define XTPR14 0x88 +#define XTPR15 0x8C +#define FCCREQ0SET 0x90 +#define FCCREQ1SET 0x98 +#define FCCREQ0MSK 0xA0 +#define FCCREQ1MSK 0xA8 +#define FCCDATASET 0xB0 +#define FCCDATAMSK 0xB8 +#define FCCCTL 0xC0 +#define CFGPOCTL1 0xC8 +#define CFGPOCTL2 0xCC +#define NOACFGBUSCTL 0xD0 +#define POC 0xF4 +#define POCRL 0xFA +#define CHDECMISC 0x111 +#define ZQCALQT 0x114 +#define SHC2REGI 0x115 +#define SHC2REGII 0x117 +#define WRWMCONFIG 0x120 +#define SHC2REGIII 0x124 +#define SHPENDREG 0x125 +#define SHPAGECTRL 0x127 +#define SHCMPLWRCMD 0x129 +#define SHC2MINTM 0x12A +#define SHC2IDLETM 0x12C +#define BYPACTSF 0x12D +#define BYPKNRULE 0x12E +#define SHBONUSREG 0x12F +#define COMPCTRL1 0x130 +#define COMPCTRL2 0x134 +#define COMPCTRL3 0x138 +#define XCOMP 0x13C +#define RCMEASBUFXOVR 0x140 +#define ACTXCOMP 0x144 +#define FINALXRCOMPRD 0x148 +#define SCOMP 0x14C +#define SCMEASBUFOVR 0x150 +#define ACTSCOMP 0x154 +#define FINALXSCOMP 0x158 +#define XSCSTART 0x15A +#define DCOMPRAW1 0x15C +#define DCOMPRAW2 0x160 +#define DCMEASBUFOVR 0x164 +#define FINALDELCOMP 0x168 +#define OFREQDELSEL 0x16C +#define XCOMPDFCTRL 0x170 +#define ZQCALCTRL 0x178 +#define XCOMPCMNBNS 0x17A +#define PSMIOVR 0x17C +#define CSHRPDCTL 0x180 +#define CSPDSLVWT 0x182 +#define CSHRPDSHFTOUTLO 0x184 +#define CSHRFIFOCTL 0x188 +#define CSHWRIOBONUS 0x189 +#define CSHRPDCTL2 0x18A +#define CSHRWRIOMLNS 0x18C +#define CSHRPDCTL3 0x18E +#define CSHRPDCTL4 0x190 +#define CSHWRIOBONUS2 0x192 +#define CSHRMSTDYNDLLENB 0x193 +#define C0TXCCCMISC 0x194 +#define CSHRMSTRCTL0 0x198 +#define CSHRMSTRCTL1 0x19C +#define CSHRDQSTXPGM 0x1A0 +#define CSHRDQSCMN 0x1A4 +#define CSHRDDR3CTL 0x1A8 +#define CSHRDIGANAOBSCTL 0x1B0 +#define CSHRMISCCTL 0x1B4 +#define CSHRMISCCTL1 0x1B6 +#define CSHRDFTCTL 0x1B8 +#define MPLLCTL 0x1C0 +#define MPLLDBG 0x1C4 +#define CREFPI 0x1C8 +#define CSHRDQSDQTX 0x1E0 +#define C0DRB0 0x200 +#define C0DRB1 0x202 +#define C0DRB2 0x204 +#define C0DRB3 0x206 +#define C0DRA01 0x208 +#define C0DRA23 0x20A +#define CLOCKGATINGIII 0x210 +#define SHC3C4REG1 0x212 +#define SHC2REG4 0x216 +#define C0COREBONUS2 0x218 +#define C0GNT2LNCH3 0x21C +#define C0GNT2LNCH1 0x220 +#define C0GNT2LNCH2 0x224 +#define C0MISCTM 0x228 +#define SHCYCTRKRDWRSFLV 0x22C +#define SHCYCTRKRFSHSFLV 0x232 +#define SHCYCTRKCTLLVOV 0x234 +#define C0WRDPYN 0x239 +#define C0C2REG 0x23C +#define C0STATRDADJV 0x23E +#define C0LATCTRL 0x240 +#define C0BYPCTRL 0x241 +#define C0CWBCTRL 0x243 +#define C0ARBCTRL 0x244 +#define C0ADDCSCTRL 0x246 +#define C0STATRDCTRL 0x248 +#define C0RDFIFOCTRL 0x24C +#define C0WRDATACTRL 0x24D +#define C0CYCTRKPCHG 0x250 +#define C0CYCTRKACT 0x252 +#define C0CYCTRKWR 0x256 +#define C0CYCTRKRD 0x258 +#define C0CYCTRKREFR 0x25B +#define C0CYCTRKPCHG2 0x25D +#define C0RDQCTRL 0x25E +#define C0CKECTRL 0x260 +#define C0CKEDELAY 0x264 +#define C0PWLRCTRL 0x265 +#define C0EPCONFIG 0x267 +#define C0REFRCTRL2 0x268 +#define C0REFRCTRL 0x269 +#define C0PVCFG 0x26F +#define C0JEDEC 0x271 +#define C0ARBSPL 0x272 +#define C0DYNRDCTRL 0x274 +#define C0WRWMFLSH 0x278 +#define C0ECCERRLOG 0x280 +#define C0DITCTRL 0x288 +#define C0ODTRKCTRL 0x294 +#define C0ODT 0x298 +#define C0ODTCTRL 0x29C +#define C0GTEW 0x2A0 +#define C0GTC 0x2A4 +#define C0DTPEW 0x2A8 +#define C0DTAEW 0x2AC +#define C0DTC 0x2B4 +#define C0REFCTRL 0x2B8 +#define C0NOASEL 0x2BF +#define C0COREBONUS 0x2C0 +#define C0DARBTEST 0x2C8 +#define CLOCKGATINGI 0x2D1 +#define MEMTDPCTW 0x2D4 +#define MTDPCTWHOTTH 0x2D8 +#define MTDPCTWHOTTH2 0x2DC +#define MTDPCTWHOTTH3 0x2E0 +#define MTDPCTWHOTTH4 0x2E4 +#define MTDPCTWAUXTH 0x2E8 +#define MTDPCTWIRTH 0x2EC +#define MTDPCCRWTWHOTTH 0x2F0 +#define MTDPCCRWTWHOTTH2 0x2F4 +#define MTDPCCRWTWHOTTH3 0x2F8 +#define MTDPCCRWTWHOTTH4 0x2FC +#define MTDPCHOTTHINT 0x300 +#define MTDPCHOTTHINT2 0x304 +#define MTDPCTLAUXTNTINT 0x308 +#define MTDPCMISC 0x30C + +/* RCOMP 0 */ +#define C0RCOMPCTRL0 0x31C +#define C0RCOMPMULT0 0x320 +#define C0RCOMPOVR0 0x322 +#define C0RCOMPOSV0 0x326 +#define C0SCOMPVREF0 0x32A +#define C0SCOMPOVR0 0x32C +#define C0SCOMPOFF0 0x32E +#define C0DCOMP0 0x330 +#define C0SLEWBASE0 0x332 +#define C0SLEWPULUT0 0x334 +#define C0SLEWPDLUT0 0x338 +#define C0DCOMPOVR0 0x33C +#define C0DCOMPOFF0 0x340 + +/* RCOMP 2 */ +#define C0RCOMPCTRL2 0x374 +#define C0RCOMPMULT2 0x378 +#define C0RCOMPOVR2 0x37A +#define C0RCOMPOSV2 0x37E +#define C0SCOMPVREF2 0x382 +#define C0SCOMPOVR2 0x384 +#define C0SCOMPOFF2 0x386 +#define C0DCOMP2 0x388 +#define C0SLEWBASE2 0x38A +#define C0SLEWPULUT2 0x38C +#define C0SLEWPDLUT2 0x390 +#define C0DCOMPOVR2 0x394 +#define C0DCOMPOFF2 0x398 + +/* RCOMP 3 */ +#define C0RCOMPCTRL3 0x3A2 +#define C0RCOMPMULT3 0x3A6 +#define C0RCOMPOVR3 0x3A8 +#define C0RCOMPOSV3 0x3AC +#define C0SCOMPVREF3 0x3B0 +#define C0SCOMPOVR3 0x3B2 +#define C0SCOMPOFF3 0x3B4 +#define C0DCOMP3 0x3B6 +#define C0SLEWBASE3 0x3B8 +#define C0SLEWPULUT3 0x3BA +#define C0SLEWPDLUT3 0x3BE +#define C0DCOMPOVR3 0x3C2 +#define C0DCOMPOFF3 0x3C6 + +/* RCOMP 4 */ +#define C0RCOMPCTRL4 0x3D0 +#define C0RCOMPMULT4 0x3D4 +#define C0RCOMPOVR4 0x3D6 +#define C0RCOMPOSV4 0x3DA +#define C0SCOMPVREF4 0x3DE +#define C0SCOMPOVR4 0x3E0 +#define C0SCOMPOFF4 0x3E2 +#define C0DCOMP4 0x3E4 +#define C0SLEWBASE4 0x3E6 +#define C0SLEWPULUT4 0x3E8 +#define C0SLEWPDLUT4 0x3EC +#define C0DCOMPOVR4 0x3F0 +#define C0DCOMPOFF4 0x3F4 + +/* RCOMP 5 */ +#define C0RCOMPCTRL5 0x3FE +#define C0RCOMPMULT5 0x402 +#define C0RCOMPOVR5 0x404 +#define C0RCOMPOSV5 0x408 +#define C0SCOMPVREF5 0x40C +#define C0SCOMPOVR5 0x40E +#define C0SCOMPOFF5 0x410 +#define C0DCOMP5 0x412 +#define C0SLEWBASE5 0x414 +#define C0SLEWPULUT5 0x416 +#define C0SLEWPDLUT5 0x41A +#define C0DCOMPOVR5 0x41E +#define C0DCOMPOFF5 0x422 + +/* RCOMP 6 */ +#define C0RCOMPCTRL6 0x42C +#define C0RCOMPMULT6 0x430 +#define C0RCOMPOVR6 0x432 +#define C0RCOMPOSV6 0x436 +#define C0SCOMPVREF6 0x43A +#define C0SCOMPOVR6 0x43C +#define C0SCOMPOFF6 0x43E +#define C0DCOMP6 0x440 +#define C0SLEWBASE6 0x442 +#define C0SLEWPULUT6 0x444 +#define C0SLEWPDLUT6 0x448 +#define C0DCOMPOVR6 0x44C +#define C0DCOMPOFF6 0x450 + +#define C0ODTRECORDX 0x45A +#define C0DQSODTRECORDX 0x462 +#define XCOMPSDR0BNS 0x4B0 +#define C0TXDQ0R0DLL 0x500 +#define C0TXDQ0R1DLL 0x501 +#define C0TXDQ0R2DLL 0x502 +#define C0TXDQ0R3DLL 0x503 +#define C0TXDQ1R0DLL 0x504 +#define C0TXDQ1R1DLL 0x505 +#define C0TXDQ1R2DLL 0x506 +#define C0TXDQ1R3DLL 0x507 +#define C0TXDQ2R0DLL 0x508 +#define C0TXDQ2R1DLL 0x509 +#define C0TXDQ2R2DLL 0x50A +#define C0TXDQ2R3DLL 0x50B +#define C0TXDQ3R0DLL 0x50C +#define C0TXDQ3R1DLL 0x50D +#define C0TXDQ3R2DLL 0x50E +#define C0TXDQ3R3DLL 0x50F +#define C0TXDQ4R0DLL 0x510 +#define C0TXDQ4R1DLL 0x511 +#define C0TXDQ4R2DLL 0x512 +#define C0TXDQ4R3DLL 0x513 +#define C0TXDQ5R0DLL 0x514 +#define C0TXDQ5R1DLL 0x515 +#define C0TXDQ5R2DLL 0x516 +#define C0TXDQ5R3DLL 0x517 +#define C0TXDQ6R0DLL 0x518 +#define C0TXDQ6R1DLL 0x519 +#define C0TXDQ6R2DLL 0x51A +#define C0TXDQ6R3DLL 0x51B +#define C0TXDQ7R0DLL 0x51C +#define C0TXDQ7R1DLL 0x51D +#define C0TXDQ7R2DLL 0x51E +#define C0TXDQ7R3DLL 0x51F +#define C0TXDQS0R0DLL 0x520 +#define C0TXDQS0R1DLL 0x521 +#define C0TXDQS0R2DLL 0x522 +#define C0TXDQS0R3DLL 0x523 +#define C0TXDQS1R0DLL 0x524 +#define C0TXDQS1R1DLL 0x525 +#define C0TXDQS1R2DLL 0x526 +#define C0TXDQS1R3DLL 0x527 +#define C0TXDQS2R0DLL 0x528 +#define C0TXDQS2R1DLL 0x529 +#define C0TXDQS2R2DLL 0x52A +#define C0TXDQS2R3DLL 0x52B +#define C0TXDQS3R0DLL 0x52C +#define C0TXDQS3R1DLL 0x52D +#define C0TXDQS3R2DLL 0x52E +#define C0TXDQS3R3DLL 0x52F +#define C0TXDQS4R0DLL 0x530 +#define C0TXDQS4R1DLL 0x531 +#define C0TXDQS4R2DLL 0x532 +#define C0TXDQS4R3DLL 0x533 +#define C0TXDQS5R0DLL 0x534 +#define C0TXDQS5R1DLL 0x535 +#define C0TXDQS5R2DLL 0x536 +#define C0TXDQS5R3DLL 0x537 +#define C0TXDQS6R0DLL 0x538 +#define C0TXDQS6R1DLL 0x539 +#define C0TXDQS6R2DLL 0x53A +#define C0TXDQS6R3DLL 0x53B +#define C0TXDQS7R0DLL 0x53C +#define C0TXDQS7R1DLL 0x53D +#define C0TXDQS7R2DLL 0x53E +#define C0TXDQS7R3DLL 0x53F + +#define C0DLLRCVCTLy(y) Ly(0x540, y) +#define C0RXRCVyDLL(y) Ly(0x560, y) +#define C0MISCCTLy(y) Ly(0x561, y) + +#define C0TXCMD0DLL 0x580 +#define C0TXCK0DLL 0x581 +#define C0TXCK1DLL 0x582 +#define C0TXCMD1DLL 0x583 +#define C0TXCTL0DLL 0x584 +#define C0TXCTL1DLL 0x585 +#define C0TXCTL2DLL 0x586 +#define C0TXCTL3DLL 0x587 +#define C0RCVMISCCTL1 0x588 +#define C0RCVMISCCTL2 0x58C +#define C0MCHODTMISCCTL1 0x590 +#define C0DYNSLVDLLEN 0x592 +#define C0CMDTX1 0x594 +#define C0CMDTX2 0x598 +#define C0CTLTX2 0x59C +#define C0CKTX 0x5A0 + +#define C0DQRyTX1(y) Ly(0x5A4, y) +#define C0DQSRyTX1(y) Ly(0x5B4, y) + +#define C0DQSDQTX2 0x5C4 + +#define C0DQSDQRyTX3(y) Ly(0x5C8, y) + +#define C0RSTCTL 0x5D8 +#define C0MISCCTL 0x5D9 +#define C0MISC2 0x5DA +#define C0BONUS 0x5DB +#define CMNDQFIFORST 0x5DC +#define C0IOBUFACTCTL 0x5DD +#define C0BONUS2 0x5DE +#define C0DLLPIEN 0x5F0 +#define C0COARSEDLY0 0x5FA +#define C0COARSEDLY1 0x5FC +#define SHC3C4REG2 0x610 +#define SHC3C4REG3 0x612 +#define SHC3C4REG4 0x614 +#define SHCYCTRKCKEL 0x62C +#define SHCYCTRKACTSFLV 0x630 +#define SHCYCTRKPCHGSFLV 0x634 +#define C1COREBONUS 0x6C0 +#define CLOCKGATINGII 0x6D1 +#define CLKXSSH2MCBYPPHAS 0x6D4 +#define CLKXSSH2MCBYP 0x6D8 +#define CLKXSSH2MCRDQ 0x6E0 +#define CLKXSSH2MCRDCST 0x6E8 +#define CLKXSSMC2H 0x6F0 +#define CLKXSSMC2HALT 0x6F8 +#define CLKXSSH2MD 0x700 +#define CLKXSSH2X2MD 0x708 +#define XSBFTCTL 0xB00 +#define XSBFTDRR 0xB04 +#define DACGIOCTRL1 0xB08 +#define CLKCFG 0xC00 +#define HMCCMP 0xC04 +#define HMCCMC 0xC08 +#define HMPLLO 0xC10 +#define CPCTL 0xC1C +#define SSKPD 0xC20 +#define HMCCPEXT 0xC28 +#define HMDCPEXT 0xC2C +#define CPBUP 0xC30 +#define HMBYPEXT 0xC34 +#define HPLLVCO 0xC38 +#define HPLLMONCTLA 0xC3C +#define HPLLMONCTLB 0xC40 +#define HPLLMONCTLC 0xC44 +#define DPLLMONCTLA 0xC48 +#define DPLLMONCTLB 0xC4C +#define HMDCMP 0xC50 +#define HMBYPCP 0xC54 +#define FLRCSSEL 0xC58 +#define DPLLMONCTLC 0xC5C +#define MPLLMONCTLA 0xC60 +#define MPLLMONCTLB 0xC64 +#define MPLLMONCTLC 0xC68 +#define PLLFUSEOVR1 0xC70 +#define PLLFUSEOVR2 0xC74 +#define GCRCSCP 0xC80 +#define GCRCSCMP 0xC84 +#define GCRCSBYPCP 0xC86 +#define GCPLLO 0xC88 +#define MCH_GCFGC 0xC8C /* Note: 'GCFGC' is also defined in 'i915_reg.h' */ +#define GTDPCTSHOTTH 0xD00 +#define GTDPCTSHOTTH2 0xD04 +#define MTDPCTSHOTTH 0xD08 +#define MTDPCTSHOTTH2 0xD0C +#define TSROTDPC 0xD10 +#define TSMISC 0xD14 +#define TEST_MC 0xE00 +#define APSMCTL 0xE04 +#define DFT_STRAP1 0xE08 +#define DFT_STRAP2 0xE0C +#define CFGFUSE1 0xE10 +#define FUSEOVR1 0xE1C +#define FUSEOVR2 0xE20 +#define FUSEOVR3 0xE24 +#define FUSEOVR4 0xE28 +#define NOA_RCOMP 0xE2C +#define NOAR1 0xE30 +#define NOAR2 0xE34 +#define NOAR3 0xE38 +#define NOAR4 0xE3C +#define NOAR5 0xE40 +#define NOAR6 0xE44 +#define NOAR7 0xE48 +#define NOAR8 0xE4C +#define NOAR9 0xE50 +#define NOAR10 0xE54 +#define ODOC1 0xE58 +#define ODOC2 0xE5C +#define ODOSTAT 0xE60 +#define ODOSTAT2 0xE64 +#define ODOSTAT3 0xE68 +#define DPLLMMC 0xE6C +#define CFGFUSE2 0xE70 +#define FUSEOVR5 0xE78 +#define NOA_LVDSCTRL 0xE7C +#define NOABUFMSK 0xE80 +#define PMCFG 0xF10 +#define PMSTS 0xF14 +#define PMMISC 0xF18 +#define GTDPCNME 0xF20 +#define GTDPCTW 0xF24 +#define GTDPCTW2 0xF28 +#define GTDPTWHOTTH 0xF2C +#define GTDPTWHOTTH2 0xF30 +#define GTDPTWHOTTH3 0xF34 +#define GTDPTWHOTTH4 0xF38 +#define GTDPTWAUXTH 0xF3C +#define GTDPCTWIRTH 0xF40 +#define GTDPCTWIRTH2NMISC 0xF44 +#define GTDPHTM 0xF48 +#define GTDPHTM2 0xF4C +#define GTDPHTM3 0xF50 +#define GTDPHTM4 0xF54 +#define GTDPAHTMOV 0xF58 +#define GTDPAHTMOV2 0xF5C +#define GTDPAHTMOV3 0xF60 +#define GTDPAHTMOV4 0xF64 +#define GTDPATM 0xF68 +#define GTDPCGC 0xF6C +#define PCWBFC 0xF90 +#define SCWBFC 0xF98 +#define SBCTL 0xFA0 +#define SBCTL2 0xFA4 +#define PCWBPFC 0xFA8 +#define SBCTL3 0xFAC +#define SBCLKGATECTRL 0xFB0 +#define SBBONUS0 0xFB4 +#define SBBONUS1 0xFB6 +#define PSMICTL 0xFC0 +#define PSMIMBASE 0xFC4 +#define PSMIMLIMIT 0xFC8 +#define PSMIDEBUG 0xFCC +#define PSMICTL2 0xFD0 +#define PSMIRPLYNOAMAP 0xFD4 +#define CICGDIS 0xFF0 +#define CICTRL 0xFF4 +#define CISDCTRL 0xFF8 +#define CIMBSR 0xFFC +#define GFXC3C4 0x1104 +#define PMDSLFRC 0x1108 +#define PMMSPMRES 0x110C +#define PMCLKRC 0x1110 +#define PMPXPRC 0x1114 +#define PMC6CTL 0x111C +#define PMICHTST 0x1120 +#define PMBAK 0x1124 +#define C0TXDQDQS0MISC 0x2800 +#define C0TXDQDQS1MISC 0x2804 +#define C0TXDQDQS2MISC 0x2808 +#define C0TXDQDQS3MISC 0x280C +#define C0TXDQDQS4MISC 0x2810 +#define C0TXDQDQS5MISC 0x2814 +#define C0TXDQDQS6MISC 0x2818 +#define C0TXDQDQS7MISC 0x281C +#define CSHRPDCTL5 0x2C00 +#define CSHWRIOBONUSX 0x2C02 +#define C0CALRESULT1 0x2C04 +#define C0CALRESULT2 0x2C08 +#define C0MODREFOFFSET1 0x2C0C +#define C0MODREFOFFSET2 0x2C10 +#define C0SLVDLLOUTEN 0x2C14 +#define C0DYNSLVDLLEN2 0x2C15 +#define LVDSICR1 0x3000 +#define LVDSICR2 0x3004 +#define IOCKTRR1 0x3008 +#define IOCKTRR2 0x300C +#define IOCKTRR3 0x3010 +#define IOCKTSTTR 0x3014 +#define IUB 0x3800 +#define BIR 0x3804 +#define TSC1 0x3808 +#define TSC2 0x3809 +#define TSS 0x380A +#define TR 0x380B +#define TSTTP 0x380C +#define TCO 0x3812 +#define TST 0x3813 +#define THERM1 0x3814 +#define THERM3 0x3816 +#define TIS 0x381A +#define TERRCMD 0x3820 +#define TSMICMD 0x3821 +#define TSCICMD 0x3822 +#define TSC3 0x3824 +#define EXTTSCS 0x3825 +#define C0THRMSTS 0x3830 + +#endif /* __PINEVIEW_MCHBAR_REGS_H__ */ diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 9fde9f7fdb..2e6ed0d668 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -32,7 +32,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) { *base = 0; *len = 0; - const pci_devfn_t dev = PCI_DEV(0,0,0); + const pci_devfn_t dev = HOST_BRIDGE; u32 pciexbar = 0; u32 pciexbar_reg; u32 reg32; @@ -49,7 +49,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - // MMCFG not supported or not enabled. + /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) { printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); return 0; @@ -72,9 +72,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) { - const u32 gmssize[] = { - 0, 1, 4, 8, 16, 32, 48, 64, 128, 256 - }; + const u32 gmssize[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256}; if (gms > 9) { printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n"); @@ -86,9 +84,7 @@ u32 decode_igd_memory_size(const u32 gms) /** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ u32 decode_igd_gtt_size(const u32 gsm) { - const u8 gsmsize[] = { - 0, 1, 0, 0, - }; + const u8 gsmsize[] = {0, 1, 0, 0}; if (gsm > 3) { printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n"); @@ -118,43 +114,42 @@ static u32 decode_tseg_size(const u32 esmramc) static size_t northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); return decode_tseg_size(esmramc); } static uintptr_t northbridge_get_tseg_base(void) { - return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + return pci_read_config32(HOST_BRIDGE, TSEG); } -/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB alignment. As this may cause very greedy MTRR setup, push - * CBMEM top downwards to 4 MiB boundary. +/* + * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. + * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top_chipset(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); } void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); - *size = northbridge_get_tseg_size(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. + /* + * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both + * CBMEM and the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), + MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 0b9de19e97..cde2a2a681 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -25,7 +25,8 @@ #include #include -/* Reserve everything between A segment and 1MB: +/* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) @@ -40,13 +41,14 @@ static void add_fixed_resources(struct device *dev, int index) resource = new_resource(dev, index++); resource->base = (resource_t) 0xfed00000; resource->size = (resource_t) 0x00100000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM + | IORESOURCE_RESERVE + | IORESOURCE_FIXED + | IORESOURCE_STORED + | IORESOURCE_ASSIGNED; - mmio_resource(dev, index++, legacy_hole_base_k, - (0xc0000 >> 10) - legacy_hole_base_k); - reserved_ram_resource(dev, index++, 0xc0000 >> 10, - (0x100000 - 0xc0000) >> 10); + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); } static void mch_domain_read_resources(struct device *dev) @@ -72,11 +74,10 @@ static void mch_domain_read_resources(struct device *dev) tolud <<= 16; /* Top of Memory - does not account for any UMA */ - tom = pci_read_config16(mch, TOM) & 0x1ff; + tom = pci_read_config16(mch, TOM) & 0x01ff; tom <<= 27; - printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", - touud, tolud, tom); + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", touud, tolud, tom); tomk = tolud >> 10; @@ -106,15 +107,14 @@ static void mch_domain_read_resources(struct device *dev) delta_cbmem = tomk - cbmem_topk; tomk -= delta_cbmem; - printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", - delta_cbmem); + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", delta_cbmem); /* Report the memory regions */ ram_resource(dev, index++, 0, 640); ram_resource(dev, index++, 768, tomk - 768); reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); - reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); - reserved_ram_resource(dev, index++, igd_basek, gms_sizek); + reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); + reserved_ram_resource(dev, index++, igd_basek, gms_sizek); reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); /* @@ -125,12 +125,13 @@ static void mch_domain_read_resources(struct device *dev) if (touud > top32memk) { ram_resource(dev, index++, top32memk, touud - top32memk); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud - top32memk) >> 10); + (touud - top32memk) >> 10); } if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n", + pcie_config_base, pcie_config_size); + fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } @@ -185,12 +186,12 @@ static const char *northbridge_acpi_name(const struct device *dev) } static struct device_operations pci_domain_ops = { - .read_resources = mch_domain_read_resources, - .set_resources = mch_domain_set_resources, - .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, + .init = mch_domain_init, + .scan_bus = pci_domain_scan_bus, .acpi_fill_ssdt_generator = generate_cpu_entries, - .acpi_name = northbridge_acpi_name, + .acpi_name = northbridge_acpi_name, }; static struct device_operations cpu_bus_ops = { diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 882f886b21..41ef5d9628 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -31,6 +31,7 @@ #define SYSINFO_DIMM_X8DDS 0x06 /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x48 @@ -38,9 +39,9 @@ #define DMIBAR 0x68 #define PMIOBAR 0x78 -#define GGC 0x52 /* GMCH Graphics Control */ +#define GGC 0x52 /* GMCH Graphics Control */ -#define DEVEN 0x54 /* Device Enable */ +#define DEVEN 0x54 /* Device Enable */ #define DEVEN_D0F0 (1 << 0) #define DEVEN_D1F0 (1 << 1) #define DEVEN_D2F0 (1 << 3) @@ -84,9 +85,10 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ -#define PEGSTS 0x214 /* 32bit */ +#define PEGSTS 0x214 /* 32 bits */ -/* Device 0:2.0 PCI configuration space (Graphics Device) */ +/* Device 0:2.0 PCI configuration space (Integrated Graphics Device) */ +#define GMCH_IGD PCI_DEV(0, 2, 0) #define GMADR 0x18 #define GTTADR 0x1c @@ -98,15 +100,28 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) + +/* As there are many registers, define them on a separate file */ + +#include "mchbar_regs.h" /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) @@ -114,7 +129,7 @@ * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) @@ -229,7 +244,7 @@ struct sysinfo { u8 mvco4x; /* 0 (8x) or 1 (4x) */ }; -void pineview_early_initialization(void); +void pineview_early_init(void); u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_gtt_size(const u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index a9e2c3e17e..9c887c98ab 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -27,7 +27,7 @@ #include #include -/* Debugging macros. */ +/* Debugging macros */ #if CONFIG(DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else @@ -144,7 +144,8 @@ static int decode_spd(struct dimminfo *d, int i) return 0; } -/* Ram Config: DIMMB-DIMMA +/* + * RAM Config: DIMMB-DIMMA * 0 EMPTY-EMPTY * 1 EMPTY-x16SS * 2 EMPTY-x16DS @@ -301,8 +302,7 @@ static void sdram_read_spds(struct sysinfo *s) FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) { find_ramconfig(s, chan); - PRINTK_DEBUG(" Config[CH%d] : %d\n", - chan, s->dimm_config[chan]); + PRINTK_DEBUG(" Config[CH%d] : %d\n", chan, s->dimm_config[chan]); } } @@ -314,11 +314,7 @@ static u32 fsb_reg_to_mhz(u32 speed) static u32 ddr_reg_to_mhz(u32 speed) { - u32 mhz; - mhz = (speed == 0) ? 667 : - (speed == 1) ? 800 : - 0; - return mhz; + return (speed == 0) ? 667 : (speed == 1) ? 800 : 0; } #endif @@ -351,27 +347,27 @@ static void sdram_detect_smallest_params(struct sysinfo *s) u8 i; u32 maxtras = 0; - u32 maxtrp = 0; + u32 maxtrp = 0; u32 maxtrcd = 0; - u32 maxtwr = 0; + u32 maxtwr = 0; u32 maxtrfc = 0; u32 maxtwtr = 0; u32 maxtrrd = 0; u32 maxtrtp = 0; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); - maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); + maxtras = MAX(maxtras, (s->dimms[i].spd_data[30] * 1000)); + maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); - maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); - maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + - (s->dimms[i].spd_data[40] & 0xf)); + maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); + maxtrfc = MAX(maxtrfc, (s->dimms[i].spd_data[42] * 1000) + + (s->dimms[i].spd_data[40] & 0xf)); maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); } /* - * TODO: on ddr3 there might be some minimal required values for some + * TODO: on DDR3 there might be some minimal required values for some * Timings: MIN_TRAS = 9, MIN_TRP = 3, MIN_TRCD = 3, MIN_TWR = 3, * MIN_TWTR = 4, MIN_TRRD = 2, MIN_TRTP = 4 */ @@ -416,11 +412,11 @@ static void sdram_detect_ram_speed(struct sysinfo *s) u32 fsb = 0; u8 i; u8 commoncas = 0; - u8 highcas = 0; - u8 lowcas = 0; + u8 highcas = 0; + u8 lowcas = 0; // Core frequency - fsb = (pci_read_config8(PCI_DEV(0,0,0), 0xe3) & 0x70) >> 4; + fsb = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0x70) >> 4; if (fsb) { fsb = 5 - fsb; } else { @@ -428,8 +424,8 @@ static void sdram_detect_ram_speed(struct sysinfo *s) } // DDR frequency - freq = (pci_read_config8(PCI_DEV(0,0,0), 0xe3) & 0x80) >> 7; - freq |= (pci_read_config8(PCI_DEV(0,0,0), 0xe4) & 0x3) << 1; + freq = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0x80) >> 7; + freq |= (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x03) << 1; if (freq) { freq = 6 - freq; } else { @@ -458,7 +454,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s) FOR_EACH_POPULATED_DIMM(s->dimms, i) { switch (freq) { case MEM_CLOCK_800MHz: - if ((s->dimms[i].spd_data[9] > 0x25) || + if ((s->dimms[i].spd_data[9] > 0x25) || (s->dimms[i].spd_data[10] > 0x40)) { // CAS too fast, lower it highcas--; @@ -469,7 +465,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s) break; case MEM_CLOCK_667MHz: default: - if ((s->dimms[i].spd_data[9] > 0x30) || + if ((s->dimms[i].spd_data[9] > 0x30) || (s->dimms[i].spd_data[10] > 0x45)) { // CAS too fast, lower it highcas--; @@ -494,7 +490,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s) lowcas = lsbp; while (cas == 0 && highcas >= lowcas) { FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if ((s->dimms[i].spd_data[9] > 0x30) || + if ((s->dimms[i].spd_data[9] > 0x30) || (s->dimms[i].spd_data[10] > 0x45)) { // CAS too fast, lower it highcas--; @@ -512,21 +508,25 @@ static void sdram_detect_ram_speed(struct sysinfo *s) s->selected_timings.mem_clock = freq; s->selected_timings.fsb_clock = fsb; - PRINTK_DEBUG("Drive Memory at %dMHz with CAS = %d clocks\n", ddr_reg_to_mhz(s->selected_timings.mem_clock), s->selected_timings.CAS); + PRINTK_DEBUG("Drive Memory at %dMHz with CAS = %d clocks\n", + ddr_reg_to_mhz(s->selected_timings.mem_clock), s->selected_timings.CAS); // Set memory frequency if (s->boot_path == BOOT_PATH_RESET) return; - MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x1; - reg32 = (MCHBAR32(0xc00) & (~0x70)) | (1 << 10); + + MCHBAR32_OR(PMSTS, 1); + + reg32 = (MCHBAR32(CLKCFG) & ~0x70) | (1 << 10); if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { reg8 = 3; } else { reg8 = 2; } reg32 |= reg8 << 4; - MCHBAR32(0xc00) = reg32; - s->selected_timings.mem_clock = ((MCHBAR32(0xc00) >> 4) & 0x7) - 2; + MCHBAR32(CLKCFG) = reg32; + + s->selected_timings.mem_clock = ((MCHBAR32(CLKCFG) >> 4) & 0x7) - 2; if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { PRINTK_DEBUG("MCH validated at 800MHz\n"); s->nodll = 0; @@ -549,7 +549,7 @@ static void enable_hpet(void) { u32 reg32; reg32 = RCBA32(HPTC); - reg32 &= ~0x3; + reg32 &= ~0x03; reg32 |= (1 << 7); RCBA32(HPTC) = reg32; /* On NM10 this only works if read back */ @@ -559,85 +559,99 @@ static void enable_hpet(void) static void sdram_clk_crossing(struct sysinfo *s) { - u8 clk_idx, fsb_idx; + u8 ddr_freq, fsb_freq; static const u32 clkcross[2][2][4] = { { - {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, //667 667 - {0x1F1F1F1F, 0x2A1F1FA5, 0x00000000, 0x05000002}, //667 800 + {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, /* FSB = 667, DDR = 667 */ + {0x1F1F1F1F, 0x2A1F1FA5, 0x00000000, 0x05000002}, /* FSB = 667, DDR = 800 */ }, { - {0x1F1F1F1F, 0x0D07070B, 0x00000000, 0x00000000}, //800 667 - {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, //800 800 - } + {0x1F1F1F1F, 0x0D07070B, 0x00000000, 0x00000000}, /* FSB = 800, DDR = 667 */ + {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, /* FSB = 800, DDR = 800 */ + }, }; - clk_idx = s->selected_timings.mem_clock; - fsb_idx = s->selected_timings.fsb_clock; - MCHBAR32(0xc04) = clkcross[fsb_idx][clk_idx][0]; - MCHBAR32(0xc50) = clkcross[fsb_idx][clk_idx][1]; - MCHBAR32(0xc54) = clkcross[fsb_idx][clk_idx][2]; - MCHBAR32(0xc28) = 0; - MCHBAR32(0xc2c) = clkcross[fsb_idx][clk_idx][3]; - MCHBAR32(0xc08) = MCHBAR32(0xc08) | (1 << 7); + ddr_freq = s->selected_timings.mem_clock; + fsb_freq = s->selected_timings.fsb_clock; - if ((fsb_idx == 0) && (clk_idx == 1)) { - MCHBAR8(0x6d4) = 0; - MCHBAR32(0x700) = 0; - MCHBAR32(0x704) = 0; + MCHBAR32(HMCCMP) = clkcross[fsb_freq][ddr_freq][0]; + MCHBAR32(HMDCMP) = clkcross[fsb_freq][ddr_freq][1]; + MCHBAR32(HMBYPCP) = clkcross[fsb_freq][ddr_freq][2]; + MCHBAR32(HMCCPEXT) = 0; + MCHBAR32(HMDCPEXT) = clkcross[fsb_freq][ddr_freq][3]; + + MCHBAR32_OR(HMCCMC, 1 << 7); + + if ((fsb_freq == 0) && (ddr_freq == 1)) { + MCHBAR8(CLKXSSH2MCBYPPHAS) = 0; + MCHBAR32(CLKXSSH2MD) = 0; + MCHBAR32(CLKXSSH2MD + 4) = 0; } static const u32 clkcross2[2][2][8] = { { - { 0, 0x08010204, 0, 0x08010204, 0, 0, 0, 0x04080102}, // 667 667 - { 0x04080000, 0x10010002, 0x10000000, 0x20010208, 0, 0x00000004, 0x02040000, 0x08100102}, // 667 800 + { // FSB = 667, DDR = 667 + 0x00000000, 0x08010204, 0x00000000, 0x08010204, + 0x00000000, 0x00000000, 0x00000000, 0x04080102, + }, + { // FSB = 667, DDR = 800 + 0x04080000, 0x10010002, 0x10000000, 0x20010208, + 0x00000000, 0x00000004, 0x02040000, 0x08100102, + }, }, { - { 0x10000000, 0x20010208, 0x04080000, 0x10010002, 0, 0, 0x08000000, 0x10200204}, // 800 667 - { 0x00000000, 0x08010204, 0, 0x08010204, 0, 0, 0, 0x04080102}, // 800 800 - } + { // FSB = 800, DDR = 667 + 0x10000000, 0x20010208, 0x04080000, 0x10010002, + 0x00000000, 0x00000000, 0x08000000, 0x10200204, + }, + { // FSB = 800, DDR = 800 + 0x00000000, 0x08010204, 0x00000000, 0x08010204, + 0x00000000, 0x00000000, 0x00000000, 0x04080102, + }, + }, }; - MCHBAR32(0x6d8) = clkcross2[fsb_idx][clk_idx][0]; - MCHBAR32(0x6e0) = clkcross2[fsb_idx][clk_idx][0]; - MCHBAR32(0x6e8) = clkcross2[fsb_idx][clk_idx][0]; - MCHBAR32(0x6d8+4) = clkcross2[fsb_idx][clk_idx][1]; - MCHBAR32(0x6e0+4) = clkcross2[fsb_idx][clk_idx][1]; - MCHBAR32(0x6e8+4) = clkcross2[fsb_idx][clk_idx][1]; - MCHBAR32(0x6f0) = clkcross2[fsb_idx][clk_idx][2]; - MCHBAR32(0x6f4) = clkcross2[fsb_idx][clk_idx][3]; - MCHBAR32(0x6f8) = clkcross2[fsb_idx][clk_idx][4]; - MCHBAR32(0x6fc) = clkcross2[fsb_idx][clk_idx][5]; - MCHBAR32(0x708) = clkcross2[fsb_idx][clk_idx][6]; - MCHBAR32(0x70c) = clkcross2[fsb_idx][clk_idx][7]; + MCHBAR32(CLKXSSH2MCBYP) = clkcross2[fsb_freq][ddr_freq][0]; + MCHBAR32(CLKXSSH2MCRDQ) = clkcross2[fsb_freq][ddr_freq][0]; + MCHBAR32(CLKXSSH2MCRDCST) = clkcross2[fsb_freq][ddr_freq][0]; + MCHBAR32(CLKXSSH2MCBYP + 4) = clkcross2[fsb_freq][ddr_freq][1]; + MCHBAR32(CLKXSSH2MCRDQ + 4) = clkcross2[fsb_freq][ddr_freq][1]; + MCHBAR32(CLKXSSH2MCRDCST + 4) = clkcross2[fsb_freq][ddr_freq][1]; + MCHBAR32(CLKXSSMC2H) = clkcross2[fsb_freq][ddr_freq][2]; + MCHBAR32(CLKXSSMC2H + 4) = clkcross2[fsb_freq][ddr_freq][3]; + MCHBAR32(CLKXSSMC2HALT) = clkcross2[fsb_freq][ddr_freq][4]; + MCHBAR32(CLKXSSMC2HALT + 4) = clkcross2[fsb_freq][ddr_freq][5]; + MCHBAR32(CLKXSSH2X2MD) = clkcross2[fsb_freq][ddr_freq][6]; + MCHBAR32(CLKXSSH2X2MD + 4) = clkcross2[fsb_freq][ddr_freq][7]; } static void sdram_clkmode(struct sysinfo *s) { - u8 reg8; - u16 reg16; + u8 ddr_freq; + u16 mpll_ctl; - MCHBAR16(0x1b6) = MCHBAR16(0x1b6) & ~(1 << 8); - MCHBAR8(0x1b6) = MCHBAR8(0x1b6) & ~0x3f; + MCHBAR16_AND(CSHRMISCCTL1, ~(1 << 8)); + MCHBAR8_AND(CSHRMISCCTL1, ~0x3f); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { - reg8 = 0; - reg16 = 1; + ddr_freq = 0; + mpll_ctl = 1; } else { - reg8 = 1; - reg16 = (1 << 8) | (1 << 5); + ddr_freq = 1; + mpll_ctl = (1 << 8) | (1 << 5); } if (s->boot_path != BOOT_PATH_RESET) - MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16; + MCHBAR16_AND_OR(MPLLCTL, ~(0x033f), mpll_ctl); - MCHBAR32(0x220) = 0x58001117; - MCHBAR32(0x248) = (MCHBAR32(0x248) | (1 << 23)); + MCHBAR32(C0GNT2LNCH1) = 0x58001117; + MCHBAR32_OR(C0STATRDCTRL, 1 << 23); const u32 cas_to_reg[2][4] = { - {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, // 667 - {0x00000000, 0x00030100, 0x0C240201, 0x10450302} // 800 + {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */ + {0x00000000, 0x00030100, 0x0C240201, 0x10450302} /* DDR = 800 */ }; - MCHBAR32(0x224) = cas_to_reg[reg8][s->selected_timings.CAS - 3]; + MCHBAR32(C0GNT2LNCH2) = cas_to_reg[ddr_freq][s->selected_timings.CAS - 3]; } static void sdram_timings(struct sysinfo *s) @@ -646,19 +660,23 @@ static void sdram_timings(struct sysinfo *s) u8 reg8, wl; u16 reg16; u32 reg32, reg2; - static const u8 pagetab[2][2] = {{0xe, 0x12}, {0x10, 0x14}}; - // Only consider DDR2 - wl = s->selected_timings.CAS - 1; - ta1 = ta2 = 6; - ta3 = s->selected_timings.CAS; - ta4 = 8; + static const u8 pagetab[2][2] = { + {0x0e, 0x12}, + {0x10, 0x14}, + }; + + /* Only consider DDR2 */ + wl = s->selected_timings.CAS - 1; + ta1 = ta2 = 6; + ta3 = s->selected_timings.CAS; + ta4 = 8; s->selected_timings.tRFC = (s->selected_timings.tRFC + 1) & 0xfe; - trp = 0; + trp = 0; bank = 1; page = 0; - MCHBAR8(0x240) = ((wl - 3) << 4) | (s->selected_timings.CAS - 3); + MCHBAR8(C0LATCTRL) = ((wl - 3) << 4) | (s->selected_timings.CAS - 3); FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { i = ch << 1; @@ -678,40 +696,42 @@ static void sdram_timings(struct sysinfo *s) flag = 1; } - MCHBAR8(0x26f) = MCHBAR8(0x26f) | 0x3; - MCHBAR16(0x250) = ((wl + 4 + s->selected_timings.tWR) << 6) | - ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; + MCHBAR8_OR(C0PVCFG, 0x03); + MCHBAR16(C0CYCTRKPCHG) = ((wl + 4 + s->selected_timings.tWR) << 6) | + ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; + reg32 = (bank << 21) | (s->selected_timings.tRRD << 17) | - (s->selected_timings.tRP << 13) | - ((s->selected_timings.tRP + trp) << 9) | - s->selected_timings.tRFC; + (s->selected_timings.tRP << 13) | ((s->selected_timings.tRP + trp) << 9) | + s->selected_timings.tRFC; + if (bank == 0) { reg32 |= (pagetab[flag][page] << 22); } - MCHBAR16(0x252) = (u16) reg32; - MCHBAR16(0x254) = (u16) (reg32 >> 16); + /* FIXME: Why not do a single dword write? */ + MCHBAR16(C0CYCTRKACT) = (u16) (reg32); + MCHBAR16(C0CYCTRKACT + 2) = (u16) (reg32 >> 16); - reg16 = (MCHBAR16(0x254) & 0xfc0) >> 6; - MCHBAR16(0x62c) = (MCHBAR16(0x62c) & ~0x1f80) | (reg16 << 7); + /* FIXME: Only applies to DDR2 */ + reg16 = (MCHBAR16(C0CYCTRKACT + 2) & 0x0fc0) >> 6; + MCHBAR16_AND_OR(SHCYCTRKCKEL, ~0x1f80, (reg16 << 7)); reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4; - MCHBAR16(0x256) = reg16; + MCHBAR16(C0CYCTRKWR) = reg16; - reg32 = (s->selected_timings.tRCD << 17) | - ((wl + 4 + s->selected_timings.tWTR) << 12) | + reg32 = (s->selected_timings.tRCD << 17) | ((wl + 4 + s->selected_timings.tWTR) << 12) | (ta3 << 8) | (4 << 4) | ta1; - MCHBAR32(0x258) = reg32; + MCHBAR32(C0CYCTRKRD) = reg32; - reg16 = ((s->selected_timings.tRP + trp) << 9) | - s->selected_timings.tRFC; - MCHBAR8(0x25b) = (u8) reg16; - MCHBAR8(0x25c) = (u8) (reg16 >> 8); + reg16 = ((s->selected_timings.tRP + trp) << 9) | s->selected_timings.tRFC; - MCHBAR16(0x260) = (MCHBAR16(0x260) & ~0x3fe) | (100 << 1); - MCHBAR8(0x25d) = (MCHBAR8(0x25d) & ~0x3f) | s->selected_timings.tRAS; - MCHBAR16(0x244) = 0x2310; + /* FIXME: Why not do a single word write? */ + MCHBAR8(C0CYCTRKREFR) = (u8) (reg16); + MCHBAR8(C0CYCTRKREFR + 1) = (u8) (reg16 >> 8); - MCHBAR8(0x246) = (MCHBAR8(0x246) & ~0x1f) | 1; + MCHBAR16_AND_OR(C0CKECTRL, ~0x03fe, 100 << 1); + MCHBAR8_AND_OR(C0CYCTRKPCHG2, ~0x3f, s->selected_timings.tRAS); + MCHBAR16(C0ARBCTRL) = 0x2310; + MCHBAR8_AND_OR(C0ADDCSCTRL, ~0x1f, 1); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg32 = 3000; @@ -723,8 +743,8 @@ static void sdram_timings(struct sysinfo *s) } else { reg2 = 5000; } - reg16 = (u16)((((s->selected_timings.CAS + 7)*(reg32)) / reg2) << 8); - MCHBAR16(0x248) = (MCHBAR16(0x248) & ~0x1f00) | reg16; + reg16 = (u16)((((s->selected_timings.CAS + 7) * (reg32)) / reg2) << 8); + MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, reg16); flag = 0; if (wl > 2) { @@ -733,154 +753,180 @@ static void sdram_timings(struct sysinfo *s) reg16 = (u8) (wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; - MCHBAR16(0x24d) = (MCHBAR16(0x24d) & ~0x1ff) | reg16; + MCHBAR16_AND_OR(C0WRDATACTRL, ~0x01ff, reg16); - MCHBAR16(0x25e) = 0x1585; - MCHBAR8(0x265) = MCHBAR8(0x265) & ~0x1f; - MCHBAR16(0x265) = (MCHBAR16(0x265) & ~0x3f00) | - ((s->selected_timings.CAS + 9) << 8); + MCHBAR16(C0RDQCTRL) = 0x1585; + MCHBAR8_AND(C0PWLRCTRL, ~0x1f); + + /* rdmodwr_window[5..0] = CL+4+5 265[13..8] (264[21..16]) */ + MCHBAR16_AND_OR(C0PWLRCTRL, ~0x3f00, (s->selected_timings.CAS + 9) << 8); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { - reg16 = 0x514; - reg32 = 0xa28; + reg16 = 0x0514; + reg32 = 0x0a28; } else { - reg16 = 0x618; - reg32 = 0xc30; + reg16 = 0x0618; + reg32 = 0x0c30; } - MCHBAR32(0x268) = (MCHBAR32(0x268) & ~0xfffff00) | - (0x3f << 22) | (reg32 << 8); - MCHBAR8(0x26c) = 0x00; - MCHBAR16(0x2b8) = (MCHBAR16(0x2b8) & 0xc000) | reg16; - MCHBAR8(0x274) = MCHBAR8(0x274) | 1; + MCHBAR32_AND_OR(C0REFRCTRL2, ~0x0fffff00, (0x3f << 22) | (reg32 << 8)); - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0x7f000000) | (0xb << 25); + /* FIXME: Is this weird access necessary? Reference code does it */ + MCHBAR8(C0REFRCTRL + 3) = 0; + MCHBAR16_AND_OR(C0REFCTRL, 0xc000, reg16); + + /* NPUT Static Mode */ + MCHBAR8_OR(C0DYNRDCTRL, 1); + + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x7f000000, 0xb << 25); i = s->selected_timings.mem_clock; j = s->selected_timings.fsb_clock; if (i > j) { - MCHBAR32(0x248) = MCHBAR32(0x248) | (1 << 24); + MCHBAR32_OR(C0STATRDCTRL, 1 << 24); } - MCHBAR8(0x24c) = MCHBAR8(0x24c) & ~0x3; - MCHBAR16(0x24d) = (MCHBAR16(0x24d) & ~0x7c00) | ((wl + 10) << 10); - MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x70e0000) | (3 << 24) | (3 << 17); + MCHBAR8_AND(C0RDFIFOCTRL, ~0x3); + MCHBAR16_AND_OR(C0WRDATACTRL, ~0x7c00, (wl + 10) << 10); + MCHBAR32_AND_OR(C0CKECTRL, ~0x070e0000, (3 << 24) | (3 << 17)); reg16 = 0x15 << 6; reg16 |= 0x1f; reg16 |= (0x6 << 12); - MCHBAR16(0x26d) = (MCHBAR16(0x26d) & ~0x7fff) | reg16; + MCHBAR16_AND_OR(C0REFRCTRL + 4, ~0x7fff, reg16); - reg32 = (0x6 << 27) | (1 << 25); - MCHBAR32(0x268) = (MCHBAR32(0x268) & ~0x30000000) | ((u32)(reg32 << 8)); - MCHBAR8(0x26c) = (MCHBAR8(0x26c) & ~0xfa) | ((u8)(reg32 >> 24)); - MCHBAR8(0x271) = MCHBAR8(0x271) & ~(1 << 7); - MCHBAR8(0x274) = MCHBAR8(0x274) & ~0x6; - reg32 = (u32) (((6 & 0x03) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | - (6 << 10) | (4 << 5) | 1); - MCHBAR32(0x278) = reg32; + reg32 = (0x6 << 27) | (1 << 25); /* FIXME: For DDR3, set BIT26 as well */ + MCHBAR32_AND_OR(C0REFRCTRL2, ~0x30000000, reg32 << 8); + MCHBAR8_AND_OR(C0REFRCTRL + 3, ~0xfa, reg32 >> 24); + MCHBAR8_AND(C0JEDEC, ~(1 << 7)); + MCHBAR8_AND(C0DYNRDCTRL, ~0x6); - MCHBAR16(0x27c) = (MCHBAR16(0x27c) & ~0x1ff) | (8 << 3) | (6 >> 2); - MCHBAR16(0x125) = MCHBAR16(0x125) | 0x1c00 | (0x1f << 5); - MCHBAR8(0x127) = (MCHBAR8(0x127) & ~0xff) | 0x40; - MCHBAR8(0x128) = (MCHBAR8(0x128) & ~0x7) | 0x5; - MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f; - reg8 = 3 << 6; + /* Note: This is a 64-bit register, [34..30] = 0b00110 is split across two writes */ + reg32 = ((6 & 3) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | (6 << 10) | (4 << 5) | 1; + MCHBAR32(C0WRWMFLSH) = reg32; + MCHBAR16_AND_OR(C0WRWMFLSH + 4, ~0x1ff, (8 << 3) | (6 >> 2)); + MCHBAR16_OR(SHPENDREG, 0x1c00 | (0x1f << 5)); + + /* FIXME: Why not do a single word write? */ + MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40); + MCHBAR8_AND_OR(SHPAGECTRL + 1, ~0x07, 0x05); + MCHBAR8_OR(SHCMPLWRCMD, 0x1f); + + reg8 = (3 << 6); reg8 |= (s->dt0mode << 4); reg8 |= 0x0c; - MCHBAR8(0x12f) = (MCHBAR8(0x12f) & ~0xdf) | reg8; - MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x2; - MCHBAR8(0x228) = (MCHBAR8(0x228) & ~0x7) | 0x2; - MCHBAR16(0x241) = (MCHBAR16(0x241) & ~0x3fc) | (4 << 2); - reg32 = (2 << 29) | (1 << 28) | (1 << 23); - MCHBAR32(0x120) = (MCHBAR32(0x120) & ~0xffb00000) | reg32; + MCHBAR8_AND_OR(SHBONUSREG, ~0xdf, reg8); + MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); + MCHBAR8_AND_OR(C0MISCTM, ~0x07, 0x02); + MCHBAR16_AND_OR(C0BYPCTRL, ~0x3fc, 4 << 2); + + /* [31..29] = 0b010 for kN = 2 (2N) */ + reg32 = (2 << 29) | (1 << 28) | (1 << 23); + MCHBAR32_AND_OR(WRWMCONFIG, ~0xffb00000, reg32); + + reg8 = (u8) ((MCHBAR16(C0CYCTRKACT) & 0xe000) >> 13); + reg8 |= (u8) ((MCHBAR16(C0CYCTRKACT + 2) & 1) << 3); + MCHBAR8_AND_OR(BYPACTSF, ~0xf0, reg8 << 4); + + reg8 = (u8) ((MCHBAR32(C0CYCTRKRD) & 0x000f0000) >> 17); + MCHBAR8_AND_OR(BYPACTSF, ~0x0f, reg8); + + /* FIXME: Why not clear everything at once? */ + MCHBAR8_AND(BYPKNRULE, ~0xfc); + MCHBAR8_AND(BYPKNRULE, ~0x03); + MCHBAR8_AND(SHBONUSREG, ~0x03); + MCHBAR8_OR(C0BYPCTRL, 1); + MCHBAR16_OR(CSHRMISCCTL1, 1 << 9); - reg8 = (u8) ((MCHBAR16(0x252) & 0xe000) >> 13); - reg8 |= (u8) ((MCHBAR16(0x254) & 1) << 3); - MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4); - reg8 = (u8) ((MCHBAR32(0x258) & 0xf0000) >> 17); - MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8; - MCHBAR8(0x12e) = MCHBAR8(0x12e) & ~0xfc; - MCHBAR8(0x12e) = MCHBAR8(0x12e) & ~0x3; - MCHBAR8(0x12f) = MCHBAR8(0x12f) & ~0x3; - MCHBAR8(0x241) = MCHBAR8(0x241) | 1; - MCHBAR16(0x1b6) = MCHBAR16(0x1b6) | (1 << 9); for (i = 0; i < 8; i++) { - MCHBAR32(0x540 + i*4) = (MCHBAR32(0x540 + i*4) & ~0x3f3f3f3f) | - 0x0c0c0c0c; + /* FIXME: Hardcoded for DDR2 SO-DIMMs */ + MCHBAR32_AND_OR(C0DLLRCVCTLy(i), ~0x3f3f3f3f, 0x0c0c0c0c); } - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | - ((s->selected_timings.CAS + 1) << 16); + /* RDCS to RCVEN delay: Program coarse common to all bytelanes to default tCL + 1 */ + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, (s->selected_timings.CAS + 1) << 16); + + /* Program RCVEN delay with DLL-safe settings */ for (i = 0; i < 8; i++) { - MCHBAR8(0x560 + i*4) = MCHBAR8(0x560 + i*4) & ~0x3f; - MCHBAR16(0x58c) = MCHBAR16(0x58c) & ((u16) (~(3 << (i*2)))); - MCHBAR16(0x588) = MCHBAR16(0x588) & ((u16) (~(3 << (i*2)))); - MCHBAR16(0x5fa) = MCHBAR16(0x5fa) & ((u16) (~(3 << (i*2)))); + MCHBAR8_AND(C0RXRCVyDLL(i), ~0x3f); + MCHBAR16_AND(C0RCVMISCCTL2, (u16) ~(3 << (i * 2))); + MCHBAR16_AND(C0RCVMISCCTL1, (u16) ~(3 << (i * 2))); + MCHBAR16_AND(C0COARSEDLY0, (u16) ~(3 << (i * 2))); } - MCHBAR8(0x5f0) = MCHBAR8(0x5f0) & ~0x1; - MCHBAR8(0x5f0) = MCHBAR8(0x5f0) | 0x2; - MCHBAR8(0x5f0) = MCHBAR8(0x5f0) | 0x4; - MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0xc0400; - MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31); + MCHBAR8_AND(C0DLLPIEN, ~1); /* Power up receiver */ + MCHBAR8_OR(C0DLLPIEN, 2); /* Enable RCVEN DLL */ + MCHBAR8_OR(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ + MCHBAR32_OR(C0COREBONUS, 0x000c0400); + MCHBAR32_OR(C0CMDTX1, 1 << 31); } +/* Program clkset0's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i) { - MCHBAR16(0x5a0) = (MCHBAR16(0x5a0) & ~0xc440) | + MCHBAR16_AND_OR(C0CKTX, ~0xc440, (pll->clkdelay[f][i] << 14) | (pll->dben[f][i] << 10) | - (pll->dbsel[f][i] << 6); - MCHBAR8(0x581) = (MCHBAR8(0x581) & ~0x3f) | pll->pi[f][i]; + (pll->dbsel[f][i] << 6)); + + MCHBAR8_AND_OR(C0TXCK0DLL, ~0x3f, pll->pi[f][i]); } +/* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i) { - MCHBAR16(0x5a0) = (MCHBAR16(0x5a0) & ~0x30880) | + /* FIXME: This is actually a dword write! */ + MCHBAR16_AND_OR(C0CKTX, ~0x00030880, (pll->clkdelay[f][i] << 16) | (pll->dben[f][i] << 11) | - (pll->dbsel[f][i] << 7); - MCHBAR8(0x582) = (MCHBAR8(0x582) & ~0x3f) | pll->pi[f][i]; + (pll->dbsel[f][i] << 7)); + + MCHBAR8_AND_OR(C0TXCK1DLL, ~0x3f, pll->pi[f][i]); } +/* Program CMD0 and CMD1 registers for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_cmd(const struct pllparam *pll, u8 f, u8 i) { u8 reg8; + /* Clock Group Index 3 */ reg8 = pll->dbsel[f][i] << 5; reg8 |= pll->dben[f][i] << 6; - MCHBAR8(0x594) = (MCHBAR8(0x594) & ~0x60) | reg8; + MCHBAR8_AND_OR(C0CMDTX1, ~0x60, reg8); reg8 = pll->clkdelay[f][i] << 4; - MCHBAR8(0x598) = (MCHBAR8(0x598) & ~0x30) | reg8; + MCHBAR8_AND_OR(C0CMDTX2, ~0x30, reg8); reg8 = pll->pi[f][i]; - MCHBAR8(0x580) = (MCHBAR8(0x580) & ~0x3f) | reg8; - MCHBAR8(0x583) = (MCHBAR8(0x583) & ~0x3f) | reg8; + MCHBAR8_AND_OR(C0TXCMD0DLL, ~0x3f, reg8); + MCHBAR8_AND_OR(C0TXCMD1DLL, ~0x3f, reg8); } +/* Program CTRL registers for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_ctrl(const struct pllparam *pll, u8 f, u8 i) { u8 reg8; u32 reg32; - reg32 = ((u32) pll->dbsel[f][i]) << 20; - reg32 |= ((u32) pll->dben[f][i]) << 21; + + /* CTRL0 and CTRL1 */ + reg32 = ((u32) pll->dbsel[f][i]) << 20; + reg32 |= ((u32) pll->dben[f][i]) << 21; reg32 |= ((u32) pll->dbsel[f][i]) << 22; - reg32 |= ((u32) pll->dben[f][i]) << 23; + reg32 |= ((u32) pll->dben[f][i]) << 23; reg32 |= ((u32) pll->clkdelay[f][i]) << 24; reg32 |= ((u32) pll->clkdelay[f][i]) << 27; - MCHBAR32(0x59c) = (MCHBAR32(0x59c) & ~0x1bf0000) | reg32; + MCHBAR32_AND_OR(C0CTLTX2, ~0x01bf0000, reg32); reg8 = pll->pi[f][i]; - MCHBAR8(0x584) = (MCHBAR8(0x584) & ~0x3f) | reg8; - MCHBAR8(0x585) = (MCHBAR8(0x585) & ~0x3f) | reg8; + MCHBAR8_AND_OR(C0TXCTL0DLL, ~0x3f, reg8); + MCHBAR8_AND_OR(C0TXCTL1DLL, ~0x3f, reg8); - reg32 = ((u32) pll->dbsel[f][i]) << 12; - reg32 |= ((u32) pll->dben[f][i]) << 13; + /* CTRL2 and CTRL3 */ + reg32 = ((u32) pll->dbsel[f][i]) << 12; + reg32 |= ((u32) pll->dben[f][i]) << 13; reg32 |= ((u32) pll->dbsel[f][i]) << 8; - reg32 |= ((u32) pll->dben[f][i]) << 9; + reg32 |= ((u32) pll->dben[f][i]) << 9; reg32 |= ((u32) pll->clkdelay[f][i]) << 14; reg32 |= ((u32) pll->clkdelay[f][i]) << 10; - MCHBAR32(0x598) = (MCHBAR32(0x598) & ~0xff00) | reg32; + MCHBAR32_AND_OR(C0CMDTX2, ~0xff00, reg32); reg8 = pll->pi[f][i]; - MCHBAR8(0x586) = (MCHBAR8(0x586) & ~0x3f) | reg8; - MCHBAR8(0x587) = (MCHBAR8(0x587) & ~0x3f) | reg8; + MCHBAR8_AND_OR(C0TXCTL2DLL, ~0x3f, reg8); + MCHBAR8_AND_OR(C0TXCTL3DLL, ~0x3f, reg8); } static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) @@ -888,23 +934,25 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) u8 rank, dqs, reg8, j; u32 reg32; - j = clk - 40; - reg8 = 0; + j = clk - 40; + reg8 = 0; reg32 = 0; - rank = j % 4; - dqs = j / 4; + rank = j % 4; + dqs = j / 4; - reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); + reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dqs; - MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) & - ~((1 << (dqs+9))|(1 << dqs))) | reg32; - reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16); - MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32; + /* FIXME: Somehow, touching this changes the binary... */ + MCHBAR32(C0DQSRyTX1(rank)) = (MCHBAR32(0x5b4 + (rank * 4)) + & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32; + + reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); + MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), + reg32); reg8 = pll->pi[f][clk]; - MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8; + MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); } @@ -913,98 +961,100 @@ static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) u8 rank, dq, reg8, j; u32 reg32; - j = clk - 8; - reg8 = 0; + j = clk - 8; + reg8 = 0; reg32 = 0; - rank = j % 4; - dq = j / 4; + rank = j % 4; + dq = j / 4; - reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); + reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dq; - MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) & - ~((1 << (dq+9))|(1 << dq))) | reg32; + + /* FIXME: Somehow, touching this changes the binary... */ + MCHBAR32(C0DQRyTX1(rank)) = (MCHBAR32(0x5a4 + rank * 4) + & ~((1 << (dq + 9)) | (1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); - MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32; + MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8; + MCHBAR8_AND_OR(C0TXDQ0R0DLL + j, ~0x3f, reg8); } +/* WDLL programming: Perform HPLL/MPLL calibration after write levelization */ static void sdram_calibratepll(struct sysinfo *s, u8 pidelay) { struct pllparam pll = { .pi = { - { // 667 + { /* DDR = 667 */ 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 7, 7, 7, 7, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 1, 1, 1, 3, 3, 3, 3 + 0, 0, 0, 0, 1, 1, 1, 1, 3, 3, 3, 3, }, - { // 800 - 53, 53, 10, 10, 5, 5, 5, 5, 27, 27, 27, 27, + { /* DDR = 800 */ + 53, 53, 10, 10, 5, 5, 5, 5, 27, 27, 27, 27, 34, 34, 34, 34, 34, 34, 34, 34, 39, 39, 39, 39, 47, 47, 47, 47, 44, 44, 44, 44, 47, 47, 47, 47, - 47, 47, 47, 47, 59, 59, 59, 59, 2, 2, 2, 2, - 2, 2, 2, 2, 7, 7, 7, 7, 15, 15, 15, 15, - 12, 12, 12, 12, 15, 15, 15, 15, 15, 15, 15, 15 + 47, 47, 47, 47, 59, 59, 59, 59, 2, 2, 2, 2, + 2, 2, 2, 2, 7, 7, 7, 7, 15, 15, 15, 15, + 12, 12, 12, 12, 15, 15, 15, 15, 15, 15, 15, 15, }}, .dben = { - { // 667 - 0,0,1,1,1,1,1,1,1,1,1,1, - 1,1,1,1,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 1,1,1,1,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0 + { /* DDR = 667 */ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { // 800 - 1,1,1,1,1,1,1,1,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,1,1,1,1,1,1,1,1, - 1,1,1,1,1,1,1,1,0,0,0,0, - 1,1,1,1,0,0,0,0,0,0,0,0 + { /* DDR = 800 */ + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, }}, .dbsel = { - { // 667 - 0,0,1,1,1,1,1,1,1,1,1,1, - 1,1,1,1,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 1,1,1,1,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0 + { /* DDR = 667 */ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { // 800 - 0,0,1,1,1,1,1,1,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,1,1,1,1, - 1,1,1,1,1,1,1,1,0,0,0,0, - 1,1,1,1,0,0,0,0,0,0,0,0 + { /* DDR = 800 */ + 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, }}, .clkdelay = { - { // 667 - 0,0,1,1,0,0,0,0,1,1,1,1, - 1,1,1,1,1,1,1,1,1,1,1,1, - 1,1,1,1,1,1,1,1,1,1,1,1, - 1,1,1,1,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0 + { /* DDR = 667 */ + 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { // 800 - 0,0,0,0,0,0,0,0,1,1,1,1, - 1,1,1,1,1,1,1,1,1,1,1,1, - 1,1,1,1,1,1,1,1,1,1,1,1, - 1,1,1,1,0,0,0,0,1,1,1,1, - 1,1,1,1,1,1,1,1,1,1,1,1, - 1,1,1,1,1,1,1,1,1,1,1,1 + { /* DDR = 800 */ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }} }; @@ -1018,36 +1068,45 @@ static void sdram_calibratepll(struct sysinfo *s, u8 pidelay) pll.pi[f][i] += pidelay; } - MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~(1 << 7); - MCHBAR16(0x190) = (MCHBAR16(0x190) & (u16) ~(0x3fff)) | 0x1fff; + /* Disable Dynamic DQS Slave Setting Per Rank */ + MCHBAR8_AND(CSHRDQSCMN, ~(1 << 7)); + MCHBAR16_AND_OR(CSHRPDCTL4, ~0x3fff, 0x1fff); sdram_p_clkset0(&pll, f, 0); sdram_p_clkset1(&pll, f, 1); - sdram_p_cmd(&pll, f, 2); - sdram_p_ctrl(&pll, f, 4); + sdram_p_cmd(&pll, f, 2); + sdram_p_ctrl(&pll, f, 4); + for (i = 0; i < 32; i++) { - sdram_p_dqs(&pll, f, i+40); + sdram_p_dqs(&pll, f, i + 40); } for (i = 0; i < 32; i++) { - sdram_p_dq(&pll, f, i+8); + sdram_p_dq(&pll, f, i + 8); } } +/* Perform HMC hardware calibration */ static void sdram_calibratehwpll(struct sysinfo *s) { u8 reg8; s->async = 0; reg8 = 0; - MCHBAR16(0x180) = MCHBAR16(0x180) | (1 << 15); - MCHBAR8(0x180) = MCHBAR8(0x180) & ~(1 << 7); - MCHBAR8(0x180) = MCHBAR8(0x180) | (1 << 3); - MCHBAR8(0x180) = MCHBAR8(0x180) | (1 << 2); - MCHBAR8(0x180) = MCHBAR8(0x180) | (1 << 7); - while ((MCHBAR8(0x180) & (1 << 2)) == 0); + MCHBAR16_OR(CSHRPDCTL, 1 << 15); + MCHBAR8_AND(CSHRPDCTL, ~(1 << 7)); + MCHBAR8_OR(CSHRPDCTL, 1 << 3); + MCHBAR8_OR(CSHRPDCTL, 1 << 2); - reg8 = (MCHBAR8(0x180) & (1 << 3)) >> 3; + /* Start hardware HMC calibration */ + MCHBAR8_OR(CSHRPDCTL, 1 << 7); + + /* Busy-wait until calibration is done */ + while ((MCHBAR8(CSHRPDCTL) & (1 << 2)) == 0) + ; + + /* If hardware HMC calibration failed */ + reg8 = (MCHBAR8(CSHRPDCTL) & (1 << 3)) >> 3; if (reg8 != 0) { s->async = 1; } @@ -1059,81 +1118,104 @@ static void sdram_dlltiming(struct sysinfo *s) u16 reg16; u32 reg32; + /* Configure the Master DLL */ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { - reg32 = 0x8014227; + reg32 = 0x08014227; } else { - reg32 = 0x14221; + reg32 = 0x00014221; } - MCHBAR32(0x19c) = (MCHBAR32(0x19c) & ~0xfffffff) | reg32; - MCHBAR32(0x19c) = MCHBAR32(0x19c) | (1 << 23); - MCHBAR32(0x19c) = MCHBAR32(0x19c) | (1 << 15); - MCHBAR32(0x19c) = MCHBAR32(0x19c) & ~(1 << 15); + MCHBAR32_AND_OR(CSHRMSTRCTL1, ~0x0fffffff, reg32); + MCHBAR32_OR(CSHRMSTRCTL1, 1 << 23); + MCHBAR32_OR(CSHRMSTRCTL1, 1 << 15); + MCHBAR32_AND(CSHRMSTRCTL1, ~(1 << 15)); if (s->nodll) { - MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 0); - MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 2); - MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 4); - MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 8); - MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 10); - MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 12); - MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 14); + /* Disable the Master DLLs by setting these bits, IN ORDER! */ + MCHBAR16_OR(CSHRMSTRCTL0, 1 << 0); + MCHBAR16_OR(CSHRMSTRCTL0, 1 << 2); + MCHBAR16_OR(CSHRMSTRCTL0, 1 << 4); + MCHBAR16_OR(CSHRMSTRCTL0, 1 << 8); + MCHBAR16_OR(CSHRMSTRCTL0, 1 << 10); + MCHBAR16_OR(CSHRMSTRCTL0, 1 << 12); + MCHBAR16_OR(CSHRMSTRCTL0, 1 << 14); } else { - MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 0); - MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 2); - MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 4); - MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 8); - MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 10); - MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 12); - MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 14); + /* Enable the Master DLLs by clearing these bits, IN ORDER! */ + MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 0)); + MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 2)); + MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 4)); + MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 8)); + MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 10)); + MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 12)); + MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 14)); } + /* Initialize the Transmit DLL PI values in the following sequence. */ if (s->nodll) { - MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x3f) | 0x7; + MCHBAR8_AND_OR(CREFPI, ~0x3f, 0x07); } else { - MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x3f); + MCHBAR8_AND(CREFPI, ~0x3f); } sdram_calibratepll(s, 0); // XXX check - MCHBAR16(0x5f0) = MCHBAR16(0x5f0) | (1 << 11); - MCHBAR16(0x5f0) = MCHBAR16(0x5f0) | (1 << 12); + /* Enable all modular Slave DLL */ + MCHBAR16_OR(C0DLLPIEN, 1 << 11); + MCHBAR16_OR(C0DLLPIEN, 1 << 12); for (i = 0; i < 8; i++) { - MCHBAR16(0x5f0) = MCHBAR16(0x5f0) | ((1 << 10) >> i); + MCHBAR16_OR(C0DLLPIEN, (1 << 10) >> i); } - MCHBAR8(0x2c14) = MCHBAR8(0x2c14) | 1; - MCHBAR16(0x182) = 0x5005; - MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x51a; - MCHBAR16(0x2c00) = (MCHBAR16(0x2c00) & ~0xbf3f) | 0x9010; + /* Enable DQ/DQS output */ + MCHBAR8_OR(C0SLVDLLOUTEN, 1); + MCHBAR16(CSPDSLVWT) = 0x5005; + MCHBAR16_AND_OR(CSHRPDCTL2, ~0x1f1f, 0x051a); + MCHBAR16_AND_OR(CSHRPDCTL5, ~0xbf3f, 0x9010); if (s->nodll) { - MCHBAR8(0x18e) = (MCHBAR8(0x18e) & ~0x7f) | 0x6b; + MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x6b); } else { - MCHBAR8(0x18e) = (MCHBAR8(0x18e) & ~0x7f) | 0x55; + MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x55); sdram_calibratehwpll(s); } + /* Disable Dynamic Diff Amp */ + MCHBAR32_AND(C0STATRDCTRL, ~(1 << 22)); - MCHBAR32(0x248) = MCHBAR32(0x248) & ~(1 << 22); - MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2; - MCHBAR8(0x189) = MCHBAR8(0x189) | 0xc0; - MCHBAR8(0x189) = MCHBAR8(0x189) & ~(1 << 5); - MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xc0) | (1 << 6); - MCHBAR8(0x188) = (MCHBAR8(0x188) & ~0x3f) | 0x1a; - MCHBAR8(0x188) = MCHBAR8(0x188) | 1; + /* Now, start initializing the transmit FIFO */ + MCHBAR8_AND(C0MISCCTL, ~0x02); - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1; - MCHBAR32(0x1a0) = 0x551803; + /* Disable (gate) mdclk and mdclkb */ + MCHBAR8_OR(CSHWRIOBONUS, 0xc0); - reg8 = 0x00; //switch all clocks on anyway + /* Select mdmclk */ + MCHBAR8_AND(CSHWRIOBONUS, ~(1 << 5)); + + /* Ungate mdclk */ + MCHBAR8_AND_OR(CSHWRIOBONUS, ~0xc0, 1 << 6); + MCHBAR8_AND_OR(CSHRFIFOCTL, ~0x3f, 0x1a); + + /* Enable the write pointer count */ + MCHBAR8_OR(CSHRFIFOCTL, 1); + + /* Set the DDR3 Reset Enable bit */ + MCHBAR8_OR(CSHRDDR3CTL, 1); + + /* Configure DQS-DQ Transmit */ + MCHBAR32(CSHRDQSTXPGM) = 0x00551803; + + reg8 = 0; /* Switch all clocks on anyway */ + + /* Enable clock groups depending on rank population */ + MCHBAR32_AND_OR(C0CKTX, ~0x3f000000, reg8 << 24); + + /* Enable DDR command output buffers from core */ + MCHBAR8_AND(0x594, ~1); - MCHBAR32(0x5a0) = (MCHBAR32(0x5a0) & ~0x3f000000) | (reg8 << 24); - MCHBAR8(0x594) = MCHBAR8(0x594) & ~1; reg16 = 0; if (!rank_is_populated(s->dimms, 0, 0)) { - reg16 |= (1 << 8) | (1 << 4) | (1 << 0); + reg16 |= (1 << 8) | (1 << 4) | (1 << 0); } if (!rank_is_populated(s->dimms, 0, 1)) { - reg16 |= (1 << 9) | (1 << 5) | (1 << 1); + reg16 |= (1 << 9) | (1 << 5) | (1 << 1); } if (!rank_is_populated(s->dimms, 0, 2)) { reg16 |= (1 << 10) | (1 << 6) | (1 << 2); @@ -1141,95 +1223,123 @@ static void sdram_dlltiming(struct sysinfo *s) if (!rank_is_populated(s->dimms, 0, 3)) { reg16 |= (1 << 11) | (1 << 7) | (1 << 3); } - MCHBAR16(0x59c) = MCHBAR16(0x59c) | reg16; + MCHBAR16_OR(C0CTLTX2, reg16); } +/* Define a shorter name for these to make the lines fit in 96 characters */ +#define TABLE static const + +/* Loop over each RCOMP group, but skip group 1 because it does not exist */ +#define FOR_EACH_RCOMP_GROUP(idx) for (idx = 0; idx < 7; idx++) if (idx != 1) + +/* Define accessors for the RCOMP register banks */ +#define C0RCOMPCTRLx(x) (rcompctl[(x)] + 0x00) +#define C0RCOMPMULTx(x) (rcompctl[(x)] + 0x04) +#define C0RCOMPOVRx(x) (rcompctl[(x)] + 0x06) +#define C0RCOMPOSVx(x) (rcompctl[(x)] + 0x0A) +#define C0SCOMPVREFx(x) (rcompctl[(x)] + 0x0E) +#define C0SCOMPOVRx(x) (rcompctl[(x)] + 0x10) +#define C0SCOMPOFFx(x) (rcompctl[(x)] + 0x12) +#define C0DCOMPx(x) (rcompctl[(x)] + 0x14) +#define C0SLEWBASEx(x) (rcompctl[(x)] + 0x16) +#define C0SLEWPULUTx(x) (rcompctl[(x)] + 0x18) +#define C0SLEWPDLUTx(x) (rcompctl[(x)] + 0x1C) +#define C0DCOMPOVRx(x) (rcompctl[(x)] + 0x20) +#define C0DCOMPOFFx(x) (rcompctl[(x)] + 0x24) + +/* FIXME: This only applies to DDR2 */ static void sdram_rcomp(struct sysinfo *s) { - u8 i, j, reg8, rcompp, rcompn, srup, srun; + u8 i, j, reg8, rcompp, rcompn, srup, srun; u16 reg16; u32 reg32, rcomp1, rcomp2; - static const u8 rcompupdate[7] = { 0, 0, 0, 1, 1, 0, 0 }; - static const u8 rcompslew = 0xa; - static const u8 rcompstr[7] = { 0x66, 0, 0xaa, 0x55, 0x55, 0x77, 0x77 }; - static const u16 rcompscomp[7] = { 0xa22a, 0, 0xe22e, 0xe22e, 0xe22e, 0xa22a, 0xa22a }; - static const u8 rcompdelay[7] = { 1, 0, 0, 0, 0, 1, 1 }; - static const u16 rcompctl[7] = { 0x31c, 0, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; - static const u16 rcompf[7] = { 0x1114, 0, 0x0505, 0x0909, 0x0909, 0x0a0a, 0x0a0a }; + static const u8 rcompslew = 0x0a; + static const u16 rcompctl[7] = { + C0RCOMPCTRL0, + 0, /* This register does not exist */ + C0RCOMPCTRL2, + C0RCOMPCTRL3, + C0RCOMPCTRL4, + C0RCOMPCTRL5, + C0RCOMPCTRL6, + }; - // NC-NC x16SS x16DS x16SS2 x16DS2 x8DS, x8DS2 - static const u8 rcompstr2[7] = { 0x00, 0x55, 0x55, 0xaa, - 0xaa , 0x55, 0xaa}; - static const u16 rcompscomp2[7] = { 0x0000, 0xe22e, 0xe22e, 0xe22e, - 0x8228 , 0xe22e, 0x8228 }; - static const u8 rcompdelay2[7] = { 0, 0, 0, 0, 2 , 0, 2}; + /* RCOMP settings tables = { NC-NC, x16SS, x16DS, x16SS2, x16DS2, x8DS, x8DS2}; */ + TABLE u8 rcompupdate[7] = { 0, 0, 0, 1, 1, 0, 0}; + TABLE u8 rcompstr[7] = { 0x66, 0x00, 0xaa, 0x55, 0x55, 0x77, 0x77}; + TABLE u16 rcompscomp[7] = {0xa22a, 0x0000, 0xe22e, 0xe22e, 0xe22e, 0xa22a, 0xa22a}; + TABLE u8 rcompdelay[7] = { 1, 0, 0, 0, 0, 1, 1}; + TABLE u16 rcompf[7] = {0x1114, 0x0000, 0x0505, 0x0909, 0x0909, 0x0a0a, 0x0a0a}; + TABLE u8 rcompstr2[7] = { 0x00, 0x55, 0x55, 0xaa, 0xaa, 0x55, 0xaa}; + TABLE u16 rcompscomp2[7] = {0x0000, 0xe22e, 0xe22e, 0xe22e, 0x8228, 0xe22e, 0x8228}; + TABLE u8 rcompdelay2[7] = { 0, 0, 0, 0, 2, 0, 2}; - static const u8 rcomplut[64][12] = { - { 9, 9,11,11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 10,9,12, 11, 2, 2, 5,5, 6, 6,5, 5}, - { 10,9,12, 11, 2, 2, 6,5, 7, 6,6, 5}, - { 10,10,12, 12, 2, 2, 6,5, 7, 6,6, 5}, - { 10,10,12, 12, 2, 2, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 2, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 2, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 2, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6}, - { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6}, - { 11,10,12, 12, 3, 3, 6,6, 7, 7,6, 6}, - { 11,10,14, 13, 3, 3, 6,6, 7, 7,6, 6}, - { 12,10,14, 13, 3, 3, 6,6, 7, 7,6, 6}, - { 12,12,14, 13, 3, 3, 7,6, 7, 7,7, 6}, - { 13,12,16, 15, 3, 3, 7,6, 8, 7,7, 6}, - { 13,14,16, 15, 4, 3, 7,7, 8, 8,7, 7}, - { 14,14,16, 17, 4, 3, 7,7, 8, 8,7, 7}, - { 14,16,18, 17, 4, 4, 8,7, 8, 8,8, 7}, - { 15,16,18, 19, 4, 4, 8,7, 9, 8,8, 7}, - { 15,18,18, 19, 4, 4, 8,8, 9, 9,8, 8}, - { 16,18,20, 21, 4, 4, 8,8, 9, 9,8, 8}, - { 16,19,20, 21, 5, 4, 9,8, 10, 9,9, 8}, - { 16,19,20, 23, 5, 5, 9,9, 10, 10,9, 9}, - { 17,19,22, 23, 5, 5, 9,9, 10, 10,9, 9}, - { 17,20,22, 25, 5, 5, 9,9, 10, 10,9, 9}, - { 17,20,22, 25, 5, 5, 9,9, 10, 10,9, 9}, - { 18,20,22, 25, 5, 5, 9,9, 10, 10,9, 9}, - { 18,21,24, 25, 5, 5, 9,9, 11, 10,9, 9}, - { 19,21,24, 27, 5, 5, 9, 9, 11, 11,9, 9}, - { 19,22,24, 27, 5, 5, 10,9, 11, 11,10, 9}, - { 20,22,24, 27, 6, 5, 10,10, 11, 11,10, 10}, - { 20,23,26, 27, 6, 6, 10,10, 12, 12,10, 10}, - { 20,23,26, 29, 6, 6, 10,10, 12, 12,10, 10}, - { 21,24,26, 29, 6, 6, 10,10, 12, 12,10, 10}, - { 21,24,26, 29, 6, 6, 11,10, 12, 13,11, 10}, - { 22,25,28, 29, 6, 6, 11,11, 13, 13,11, 11}, - { 22,25,28, 31, 6, 6, 11,11, 13, 13,11, 11}, - { 22,26,28, 31, 6, 6, 11,11, 13, 14,11, 11}, - { 23,26,30, 31, 7, 6, 12,11, 14, 14,12, 11}, - { 23,27,30, 33, 7, 7, 12,12, 14, 14,12, 12}, - { 23,27,30, 33, 7, 7, 12,12, 14, 15,12, 12}, - { 24,28,32, 33, 7, 7, 12,12, 15, 15,12, 12}, - { 24,28,32, 33, 7, 7, 12,12, 15, 16,12, 12}, - { 24,29,32, 35, 7, 7, 12,12, 15, 16,12, 12}, - { 25,29,32, 35, 7, 7, 12,12, 15, 17,12, 12}, - { 25,30,32, 35, 7, 7, 12,12, 15, 17,12, 12}, - { 25,30,32, 35, 7, 7, 12,12, 15, 17,12, 12}, + TABLE u8 rcomplut[64][12] = { + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + { 9, 9, 11, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + {10, 9, 12, 11, 2, 2, 5, 5, 6, 6, 5, 5}, + {10, 9, 12, 11, 2, 2, 6, 5, 7, 6, 6, 5}, + {10, 10, 12, 12, 2, 2, 6, 5, 7, 6, 6, 5}, + {10, 10, 12, 12, 2, 2, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 2, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 2, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 2, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 3, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 3, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 3, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 3, 6, 6, 7, 7, 6, 6}, + {10, 10, 12, 12, 3, 3, 6, 6, 7, 7, 6, 6}, + {11, 10, 12, 12, 3, 3, 6, 6, 7, 7, 6, 6}, + {11, 10, 14, 13, 3, 3, 6, 6, 7, 7, 6, 6}, + {12, 10, 14, 13, 3, 3, 6, 6, 7, 7, 6, 6}, + {12, 12, 14, 13, 3, 3, 7, 6, 7, 7, 7, 6}, + {13, 12, 16, 15, 3, 3, 7, 6, 8, 7, 7, 6}, + {13, 14, 16, 15, 4, 3, 7, 7, 8, 8, 7, 7}, + {14, 14, 16, 17, 4, 3, 7, 7, 8, 8, 7, 7}, + {14, 16, 18, 17, 4, 4, 8, 7, 8, 8, 8, 7}, + {15, 16, 18, 19, 4, 4, 8, 7, 9, 8, 8, 7}, + {15, 18, 18, 19, 4, 4, 8, 8, 9, 9, 8, 8}, + {16, 18, 20, 21, 4, 4, 8, 8, 9, 9, 8, 8}, + {16, 19, 20, 21, 5, 4, 9, 8, 10, 9, 9, 8}, + {16, 19, 20, 23, 5, 5, 9, 9, 10, 10, 9, 9}, + {17, 19, 22, 23, 5, 5, 9, 9, 10, 10, 9, 9}, + {17, 20, 22, 25, 5, 5, 9, 9, 10, 10, 9, 9}, + {17, 20, 22, 25, 5, 5, 9, 9, 10, 10, 9, 9}, + {18, 20, 22, 25, 5, 5, 9, 9, 10, 10, 9, 9}, + {18, 21, 24, 25, 5, 5, 9, 9, 11, 10, 9, 9}, + {19, 21, 24, 27, 5, 5, 9, 9, 11, 11, 9, 9}, + {19, 22, 24, 27, 5, 5, 10, 9, 11, 11, 10, 9}, + {20, 22, 24, 27, 6, 5, 10, 10, 11, 11, 10, 10}, + {20, 23, 26, 27, 6, 6, 10, 10, 12, 12, 10, 10}, + {20, 23, 26, 29, 6, 6, 10, 10, 12, 12, 10, 10}, + {21, 24, 26, 29, 6, 6, 10, 10, 12, 12, 10, 10}, + {21, 24, 26, 29, 6, 6, 11, 10, 12, 13, 11, 10}, + {22, 25, 28, 29, 6, 6, 11, 11, 13, 13, 11, 11}, + {22, 25, 28, 31, 6, 6, 11, 11, 13, 13, 11, 11}, + {22, 26, 28, 31, 6, 6, 11, 11, 13, 14, 11, 11}, + {23, 26, 30, 31, 7, 6, 12, 11, 14, 14, 12, 11}, + {23, 27, 30, 33, 7, 7, 12, 12, 14, 14, 12, 12}, + {23, 27, 30, 33, 7, 7, 12, 12, 14, 15, 12, 12}, + {24, 28, 32, 33, 7, 7, 12, 12, 15, 15, 12, 12}, + {24, 28, 32, 33, 7, 7, 12, 12, 15, 16, 12, 12}, + {24, 29, 32, 35, 7, 7, 12, 12, 15, 16, 12, 12}, + {25, 29, 32, 35, 7, 7, 12, 12, 15, 17, 12, 12}, + {25, 30, 32, 35, 7, 7, 12, 12, 15, 17, 12, 12}, + {25, 30, 32, 35, 7, 7, 12, 12, 15, 17, 12, 12}, }; srup = 0; @@ -1246,189 +1356,175 @@ static void sdram_rcomp(struct sysinfo *s) rcomp2 = 0x19042827; } - for (i = 0; i < 7; i++) { - if (i == 1) - continue; + FOR_EACH_RCOMP_GROUP(i) { reg8 = rcompupdate[i]; - MCHBAR8(rcompctl[i]) = (MCHBAR8(rcompctl[i]) & ~0x1) | reg8; - MCHBAR8(rcompctl[i]) = MCHBAR8(rcompctl[i]) & ~0x2; - reg16 = (u16) rcompslew; - MCHBAR16(rcompctl[i]) = (MCHBAR16(rcompctl[i]) & ~0xf000) | - (reg16 << 12); - MCHBAR8(rcompctl[i]+4) = rcompstr[i]; - MCHBAR16(rcompctl[i]+0xe) = rcompscomp[i]; - MCHBAR8(rcompctl[i]+0x14) = (MCHBAR8(rcompctl[i]+0x14) & ~0x3) | - rcompdelay[i]; + MCHBAR8_AND_OR(C0RCOMPCTRLx(i), ~1, reg8); + MCHBAR8_AND(C0RCOMPCTRLx(i), ~2); + + reg16 = rcompslew; + MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + + MCHBAR8(C0RCOMPMULTx(i)) = rcompstr[i]; + MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp[i]; + MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay[i]); if (i == 2) { - reg16 = (u16) rcompslew; - MCHBAR16(rcompctl[i]) = (MCHBAR16(rcompctl[i]) & - ~0xf000) | (reg16 << 12); - MCHBAR8(rcompctl[i]+4) = rcompstr2[s->dimm_config[0]]; - MCHBAR16(rcompctl[i]+0xe) = rcompscomp2[s->dimm_config[0]]; - MCHBAR8(rcompctl[i]+0x14) = (MCHBAR8(rcompctl[i]+0x14) & - ~0x3) | rcompdelay2[s->dimm_config[0]]; + /* FIXME: Why are we rewriting this? */ + MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + + MCHBAR8(C0RCOMPMULTx(i)) = rcompstr2[s->dimm_config[0]]; + MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp2[s->dimm_config[0]]; + MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay2[s->dimm_config[0]]); } - MCHBAR16(rcompctl[i]+0x16) = MCHBAR16(rcompctl[i]+0x16) & ~0x7f7f; - MCHBAR16(rcompctl[i]+0x18) = MCHBAR16(rcompctl[i]+0x18) & ~0x3f3f; - MCHBAR16(rcompctl[i]+0x1a) = MCHBAR16(rcompctl[i]+0x1a) & ~0x3f3f; - MCHBAR16(rcompctl[i]+0x1c) = MCHBAR16(rcompctl[i]+0x1c) & ~0x3f3f; - MCHBAR16(rcompctl[i]+0x1e) = MCHBAR16(rcompctl[i]+0x1e) & ~0x3f3f; + MCHBAR16_AND(C0SLEWBASEx(i), ~0x7f7f); + + /* FIXME: Why not do a single dword write? */ + MCHBAR16_AND(C0SLEWPULUTx(i), ~0x3f3f); + MCHBAR16_AND(C0SLEWPULUTx(i) + 2, ~0x3f3f); + + /* FIXME: Why not do a single dword write? */ + MCHBAR16_AND(C0SLEWPDLUTx(i), ~0x3f3f); + MCHBAR16_AND(C0SLEWPDLUTx(i) + 2, ~0x3f3f); } - MCHBAR8(0x45a) = (MCHBAR8(0x45a) & ~0x3f) | 0x36; - MCHBAR8(0x462) = (MCHBAR8(0x462) & ~0x3f) | 0x36; + /* FIXME: Hardcoded */ + MCHBAR8_AND_OR(C0ODTRECORDX, ~0x3f, 0x36); + MCHBAR8_AND_OR(C0DQSODTRECORDX, ~0x3f, 0x36); - for (i = 0; i < 7; i++) { - if (i == 1) - continue; - MCHBAR8(rcompctl[i]) = MCHBAR8(rcompctl[i]) & ~0x60; - MCHBAR16(rcompctl[i]+2) = MCHBAR16(rcompctl[i]+2) & ~0x706; - MCHBAR16(rcompctl[i]+0xa) = MCHBAR16(rcompctl[i]+0xa) & ~0x7f7f; - MCHBAR16(rcompctl[i]+0x12) = MCHBAR16(rcompctl[i]+0x12) & ~0x3f3f; - MCHBAR16(rcompctl[i]+0x24) = MCHBAR16(rcompctl[i]+0x24) & ~0x1f1f; - MCHBAR8(rcompctl[i]+0x26) = MCHBAR8(rcompctl[i]+0x26) & ~0x1f; + FOR_EACH_RCOMP_GROUP(i) { + MCHBAR8_AND(C0RCOMPCTRLx(i), ~0x60); + MCHBAR16_AND(C0RCOMPCTRLx(i) + 2, ~0x0706); + MCHBAR16_AND(C0RCOMPOSVx(i), ~0x7f7f); + MCHBAR16_AND(C0SCOMPOFFx(i), ~0x3f3f); + MCHBAR16_AND(C0DCOMPOFFx(i), ~0x1f1f); + MCHBAR8_AND(C0DCOMPOFFx(i) + 2, ~0x1f); } - MCHBAR16(0x45a) = MCHBAR16(0x45a) & ~0xffc0; - MCHBAR16(0x45c) = MCHBAR16(0x45c) & ~0xf; - MCHBAR16(0x462) = MCHBAR16(0x462) & ~0xffc0; - MCHBAR16(0x464) = MCHBAR16(0x464) & ~0xf; + MCHBAR16_AND(C0ODTRECORDX, ~0xffc0); + MCHBAR16_AND(C0ODTRECORDX + 2, ~0x000f); - for (i = 0; i < 7; i++) { - if (i == 1) - continue; - MCHBAR16(rcompctl[i]+0x10) = rcompf[i]; - MCHBAR16(rcompctl[i]+0x20) = 0x1219; - MCHBAR16(rcompctl[i]+0x22) = 0x000C; + /* FIXME: Why not do a single dword write? */ + MCHBAR16_AND(C0DQSODTRECORDX, ~0xffc0); + MCHBAR16_AND(C0DQSODTRECORDX + 2, ~0x000f); + + FOR_EACH_RCOMP_GROUP(i) { + MCHBAR16(C0SCOMPOVRx(i)) = rcompf[i]; + + /* FIXME: Why not do a single dword write? */ + MCHBAR16(C0DCOMPOVRx(i)) = 0x1219; + MCHBAR16(C0DCOMPOVRx(i) + 2) = 0x000C; } - MCHBAR32(0x164) = (MCHBAR32(0x164) & ~0x1f1f1f) | 0x0c1219; - MCHBAR16(0x4b0) = (MCHBAR16(0x4b0) & ~0x1f00) | 0x1200; - MCHBAR8(0x4b0) = (MCHBAR8(0x4b0) & ~0x1f) | 0x12; - MCHBAR32(0x138) = 0x007C9007; - MCHBAR32(0x16c) = rcomp1; - MCHBAR16(0x17a) = 0x1f7f; - MCHBAR32(0x134) = rcomp2; - MCHBAR16(0x170) = (MCHBAR16(0x170) & ~0xf) | 1; - MCHBAR16(0x178) = 0x134; - MCHBAR32(0x130) = 0x4C293600; - MCHBAR8(0x133) = (MCHBAR8(0x133) & ~0x44) | (1 << 6) | (1 << 2); - MCHBAR16(0x4b0) = MCHBAR16(0x4b0) & ~(1 << 13); - MCHBAR8(0x4b0) = MCHBAR8(0x4b0) & ~(1 << 5); + MCHBAR32_AND_OR(DCMEASBUFOVR, ~0x001f1f1f, 0x000c1219); - for (i = 0; i < 7; i++) { - if (i == 1) - continue; - MCHBAR8(rcompctl[i]+2) = MCHBAR8(rcompctl[i]) & ~0x71; + /* FIXME: Why not do a single word write? */ + MCHBAR16_AND_OR(XCOMPSDR0BNS, ~0x1f00, 0x1200); + MCHBAR8_AND_OR(XCOMPSDR0BNS, ~0x1f, 0x12); + + MCHBAR32(COMPCTRL3) = 0x007C9007; + MCHBAR32(OFREQDELSEL) = rcomp1; + MCHBAR16(XCOMPCMNBNS) = 0x1f7f; + MCHBAR32(COMPCTRL2) = rcomp2; + MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 1); + MCHBAR16(ZQCALCTRL) = 0x0134; + MCHBAR32(COMPCTRL1) = 0x4C293600; + + /* FIXME: wtf did these MRC guys smoke */ + MCHBAR8_AND_OR(COMPCTRL1 + 3, ~0x44, (1 << 6) | (1 << 2)); + MCHBAR16_AND(XCOMPSDR0BNS, ~(1 << 13)); + MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); + + FOR_EACH_RCOMP_GROUP(i) { + /* FIXME: This should be an _AND_OR */ + MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71; } - if ((MCHBAR32(0x130) & (1 << 30)) == 0) { - MCHBAR8(0x130) = MCHBAR8(0x130) | 0x1; - while ((MCHBAR8(0x130) & 0x1) != 0); + if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { + /* Start COMP */ + MCHBAR8_OR(COMPCTRL1, 1); - reg32 = MCHBAR32(0x13c); + /* Wait until COMP is done */ + while ((MCHBAR8(COMPCTRL1) & 1) != 0) + ; + + reg32 = MCHBAR32(XCOMP); rcompp = (u8) ((reg32 & ~(1 << 31)) >> 24); rcompn = (u8) ((reg32 & ~(0xff800000)) >> 16); - for (i = 0; i < 7; i++) { - if (i == 1) - continue; - srup = (MCHBAR8(rcompctl[i]+1) & 0xc0) >> 6; - srun = (MCHBAR8(rcompctl[i]+1) & 0x30) >> 4; + FOR_EACH_RCOMP_GROUP(i) { + srup = (MCHBAR8(C0RCOMPCTRLx(i) + 1) & 0xc0) >> 6; + srun = (MCHBAR8(C0RCOMPCTRLx(i) + 1) & 0x30) >> 4; + + /* FIXME: Why not do a single word write? */ reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8; - MCHBAR16(rcompctl[i]+0x16) = (MCHBAR16(rcompctl[i]+0x16) - & ~0x7f00) | reg16; + MCHBAR16_AND_OR(C0SLEWBASEx(i), ~0x7f00, reg16); + reg16 = (u16)(rcompn - (1 << (srun + 1))); - MCHBAR8(rcompctl[i]+0x16) = (MCHBAR8(rcompctl[i]+0x16) & - ~0x7f) | (u8)reg16; + MCHBAR8_AND_OR(C0SLEWBASEx(i), ~0x7f, (u8)reg16); } reg8 = rcompp - (1 << (srup + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8(rcompctl[0]+0x18+i) = - (MCHBAR8(rcompctl[0]+0x18+i) & ~0x3f) | - rcomplut[j][0]; + MCHBAR8_AND_OR(C0SLEWPULUTx(0) + i, ~0x3f, rcomplut[j][0]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8(rcompctl[2]+0x18+i) = - (MCHBAR8(rcompctl[2]+0x18+i) & ~0x3f) | - rcomplut[j][10]; + MCHBAR8_AND_OR(C0SLEWPULUTx(2) + i, ~0x3f, rcomplut[j][10]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8(rcompctl[3]+0x18+i) = - (MCHBAR8(rcompctl[3]+0x18+i) & ~0x3f) | - rcomplut[j][6]; - MCHBAR8(rcompctl[4]+0x18+i) = - (MCHBAR8(rcompctl[4]+0x18+i) & ~0x3f) | - rcomplut[j][6]; + MCHBAR8_AND_OR(C0SLEWPULUTx(3) + i, ~0x3f, rcomplut[j][6]); + MCHBAR8_AND_OR(C0SLEWPULUTx(4) + i, ~0x3f, rcomplut[j][6]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8(rcompctl[5]+0x18+i) = - (MCHBAR8(rcompctl[5]+0x18+i) & ~0x3f) | - rcomplut[j][8]; - MCHBAR8(rcompctl[6]+0x18+i) = - (MCHBAR8(rcompctl[6]+0x18+i) & ~0x3f) | - rcomplut[j][8]; + MCHBAR8_AND_OR(C0SLEWPULUTx(5) + i, ~0x3f, rcomplut[j][8]); + MCHBAR8_AND_OR(C0SLEWPULUTx(6) + i, ~0x3f, rcomplut[j][8]); } reg8 = rcompn - (1 << (srun + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8(rcompctl[0]+0x1c+i) = - (MCHBAR8(rcompctl[0]+0x1c+i) & ~0x3f) | - rcomplut[j][1]; + MCHBAR8_AND_OR(C0SLEWPDLUTx(0) + i, ~0x3f, rcomplut[j][1]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8(rcompctl[2]+0x1c+i) = - (MCHBAR8(rcompctl[2]+0x1c+i) & ~0x3f) | - rcomplut[j][11]; + MCHBAR8_AND_OR(C0SLEWPDLUTx(2) + i, ~0x3f, rcomplut[j][11]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8(rcompctl[3]+0x1c+i) = - (MCHBAR8(rcompctl[3]+0x1c+i) & ~0x3f) | - rcomplut[j][7]; - MCHBAR8(rcompctl[4]+0x1c+i) = - (MCHBAR8(rcompctl[4]+0x1c+i) & ~0x3f) | - rcomplut[j][7]; + MCHBAR8_AND_OR(C0SLEWPDLUTx(3) + i, ~0x3f, rcomplut[j][7]); + MCHBAR8_AND_OR(C0SLEWPDLUTx(4) + i, ~0x3f, rcomplut[j][7]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8(rcompctl[5]+0x1c+i) = - (MCHBAR8(rcompctl[5]+0x1c+i) & ~0x3f) | - rcomplut[j][9]; - MCHBAR8(rcompctl[6]+0x1c+i) = - (MCHBAR8(rcompctl[6]+0x1c+i) & ~0x3f) | - rcomplut[j][9]; + MCHBAR8_AND_OR(C0SLEWPDLUTx(5) + i, ~0x3f, rcomplut[j][9]); + MCHBAR8_AND_OR(C0SLEWPDLUTx(6) + i, ~0x3f, rcomplut[j][9]); } } - MCHBAR8(0x130) = MCHBAR8(0x130) | 1; + MCHBAR8_OR(COMPCTRL1, 1); } +/* FIXME: The ODT tables are for DDR2 only! */ static void sdram_odt(struct sysinfo *s) { u8 rankindex = 0; - static const u16 odt294[16] = { - 0x0000, 0x0000, 0x0000, 0x0000, - 0x0044, 0x1111, 0x0000, 0x1111, - 0x0000, 0x0000, 0x0000, 0x0000, - 0x0044, 0x1111, 0x0000, 0x1111 - }; - static const u16 odt298[16] = { - 0x0000, 0x0011, 0x0000, 0x0011, - 0x0000, 0x4444, 0x0000, 0x4444, - 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x4444, 0x0000, 0x4444 - }; + static const u16 odt_rankctrl[16] = { + /* NC_NC, 1R_NC, NV, 2R_NC, NC_1R, 1R_1R, NV, 2R_1R, */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0044, 0x1111, 0x0000, 0x1111, + /* NV, NV, NV, NV, NC_2R, 1R_2R, NV, 2R_2R, */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0044, 0x1111, 0x0000, 0x1111, + }; + static const u16 odt_matrix[16] = { + /* NC_NC, 1R_NC, NV, 2R_NC, NC_1R, 1R_1R, NV, 2R_1R, */ + 0x0000, 0x0011, 0x0000, 0x0011, 0x0000, 0x4444, 0x0000, 0x4444, + /* NV, NV, NV, NV, NC_2R, 1R_2R, NV, 2R_2R, */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4444, 0x0000, 0x4444, + }; switch (s->dimms[0].ranks) { case 0: @@ -1460,68 +1556,60 @@ static void sdram_odt(struct sysinfo *s) break; } - MCHBAR16(0x298) = odt298[rankindex]; - MCHBAR16(0x294) = odt294[rankindex]; + /* Program the ODT Matrix */ + MCHBAR16(C0ODT) = odt_matrix[rankindex]; + + /* Program the ODT Rank Control */ + MCHBAR16(C0ODTRKCTRL) = odt_rankctrl[rankindex]; } static void sdram_mmap(struct sysinfo *s) { - static const u32 w260[7] = {0, 0x400001, 0xc00001, 0x500000, 0xf00000, - 0xc00001, 0xf00000}; - static const u32 w208[7] = {0, 0x10000, 0x1010000, 0x10001, 0x1010101, - 0x1010000, 0x1010101}; - static const u32 w200[7] = {0, 0, 0, 0x20002, 0x40002, 0, 0x40002}; - static const u32 w204[7] = {0, 0x20002, 0x40002, 0x40004, 0x80006, - 0x40002, 0x80006}; + TABLE u32 w260[7] = {0, 0x400001, 0xc00001, 0x500000, 0xf00000, 0xc00001, 0xf00000}; + TABLE u32 w208[7] = {0, 0x10000, 0x1010000, 0x10001, 0x1010101, 0x1010000, 0x1010101}; + TABLE u32 w200[7] = {0, 0, 0, 0x20002, 0x40002, 0, 0x40002}; + TABLE u32 w204[7] = {0, 0x20002, 0x40002, 0x40004, 0x80006, 0x40002, 0x80006}; - static const u16 tolud[7] = {0x800, 0x800, 0x1000, 0x1000, 0x2000, - 0x1000, 0x2000}; - static const u16 tom[7] = {0x2, 0x2, 0x4, 0x4, 0x8, 0x4, 0x8}; - static const u16 touud[7] = {0x80, 0x80, 0x100, 0x100, 0x200, 0x100, - 0x200}; - static const u32 gbsm[7] = {0x8000000, 0x8000000, 0x10000000, 0x8000000, - 0x20000000, 0x10000000, 0x20000000}; - static const u32 bgsm[7] = {0x8000000, 0x8000000, 0x10000000, 0x8000000, - 0x20000000, 0x10000000, 0x20000000}; - static const u32 tsegmb[7] = {0x8000000, 0x8000000, 0x10000000, - 0x8000000, 0x20000000, 0x10000000, - 0x20000000}; + TABLE u16 tolud[7] = {2048, 2048, 4096, 4096, 8192, 4096, 8192}; + TABLE u16 tom[7] = { 2, 2, 4, 4, 8, 4, 8}; + TABLE u16 touud[7] = { 128, 128, 256, 256, 512, 256, 512}; + TABLE u32 gbsm[7] = {1 << 27, 1 << 27, 1 << 28, 1 << 27, 1 << 29, 1 << 28, 1 << 29}; + TABLE u32 bgsm[7] = {1 << 27, 1 << 27, 1 << 28, 1 << 27, 1 << 29, 1 << 28, 1 << 29}; + TABLE u32 tsegmb[7] = {1 << 27, 1 << 27, 1 << 28, 1 << 27, 1 << 29, 1 << 28, 1 << 29}; if ((s->dimm_config[0] < 3) && rank_is_populated(s->dimms, 0, 0)) { if (s->dimms[0].sides > 1) { // 2R/NC - MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | 0x300001; - MCHBAR32(0x208) = 0x101; - MCHBAR32(0x200) = 0x40002; - MCHBAR32(0x204) = w204[s->dimm_config[0]]; + MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + MCHBAR32(C0DRA01) = 0x00000101; + MCHBAR32(C0DRB0) = 0x00040002; + MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } else { // 1R/NC - MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | 0x100001; - MCHBAR32(0x208) = 0x1; - MCHBAR32(0x200) = 0x20002; - MCHBAR32(0x204) = w204[s->dimm_config[0]]; + MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x100001); + MCHBAR32(C0DRA01) = 0x00000001; + MCHBAR32(C0DRB0) = 0x00020002; + MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } } else if ((s->dimm_config[0] == 5) && rank_is_populated(s->dimms, 0, 0)) { - - MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | 0x300001; - MCHBAR32(0x208) = 0x101; - MCHBAR32(0x200) = 0x40002; - MCHBAR32(0x204) = 0x40004; + MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + MCHBAR32(C0DRA01) = 0x00000101; + MCHBAR32(C0DRB0) = 0x00040002; + MCHBAR32(C0DRB2) = 0x00040004; } else { - MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | w260[s->dimm_config[0]]; - MCHBAR32(0x208) = w208[s->dimm_config[0]]; - MCHBAR32(0x200) = w200[s->dimm_config[0]]; - MCHBAR32(0x204) = w204[s->dimm_config[0]]; + MCHBAR32_AND_OR(C0CKECTRL, ~1, w260[s->dimm_config[0]]); + MCHBAR32(C0DRA01) = w208[s->dimm_config[0]]; + MCHBAR32(C0DRB0) = w200[s->dimm_config[0]]; + MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } - pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud[s->dimm_config[0]]); - pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom[s->dimm_config[0]]); - pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud[s->dimm_config[0]]); - pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gbsm[s->dimm_config[0]]); - pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, bgsm[s->dimm_config[0]]); - pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegmb[s->dimm_config[0]]); + pci_write_config16(HOST_BRIDGE, 0xb0, tolud[s->dimm_config[0]]); + pci_write_config16(HOST_BRIDGE, 0xa0, tom[s->dimm_config[0]]); + pci_write_config16(HOST_BRIDGE, 0xa2, touud[s->dimm_config[0]]); + pci_write_config32(HOST_BRIDGE, 0xa4, gbsm[s->dimm_config[0]]); + pci_write_config32(HOST_BRIDGE, 0xa8, bgsm[s->dimm_config[0]]); + pci_write_config32(HOST_BRIDGE, 0xac, tsegmb[s->dimm_config[0]]); } -#if 1 static void hpet_udelay(u32 del) { u32 start, finish, now; @@ -1542,18 +1630,17 @@ static void hpet_udelay(u32 del) } } } -#endif static u8 sdram_checkrcompoverride(void) { u32 xcomp; u8 aa, bb, a, b, c, d; - xcomp = MCHBAR32(0x13c); + xcomp = MCHBAR32(XCOMP); a = (u8)((xcomp & 0x7f000000) >> 24); - b = (u8)((xcomp & 0x7f0000) >> 16); - c = (u8)((xcomp & 0x3f00) >> 8); - d = (u8)(xcomp & 0x3f); + b = (u8)((xcomp & 0x007f0000) >> 16); + c = (u8)((xcomp & 0x00003f00) >> 8); + d = (u8)((xcomp & 0x0000003f) >> 0); if (a > b) { aa = a - b; @@ -1565,10 +1652,9 @@ static u8 sdram_checkrcompoverride(void) } else { bb = d - c; } - if ((aa > 18) || (bb > 7) || - (a <= 5) || (b <= 5) || (c <= 5) || (d <= 5) || + if ((aa > 18) || (bb > 7) || (a <= 5) || (b <= 5) || (c <= 5) || (d <= 5) || (a >= 0x7a) || (b >= 0x7a) || (c >= 0x3a) || (d >= 0x3a)) { - MCHBAR32(0x140) = 0x9718a729; + MCHBAR32(RCMEASBUFXOVR) = 0x9718a729; return 1; } return 0; @@ -1580,24 +1666,26 @@ static void sdram_rcompupdate(struct sysinfo *s) u32 reg32a, reg32b; ok = 0; - MCHBAR8(0x170) = MCHBAR8(0x170) & ~(1 << 3); - MCHBAR8(0x130) = MCHBAR8(0x130) & ~(1 << 7); + MCHBAR8_AND(XCOMPDFCTRL, ~(1 << 3)); + MCHBAR8_AND(COMPCTRL1, ~(1 << 7)); for (i = 0; i < 3; i++) { - MCHBAR8(0x130) = MCHBAR8(0x130) | 1; + MCHBAR8_OR(COMPCTRL1, 1); hpet_udelay(1000); - while ((MCHBAR8(0x130) & 0x1) != 0); + while ((MCHBAR8(COMPCTRL1) & 1) != 0) + ; ok |= sdram_checkrcompoverride(); } if (!ok) { - reg32a = MCHBAR32(0x13c); - reg32b = (reg32a >> 16) & 0x0000ffff; + reg32a = MCHBAR32(XCOMP); + reg32b = ((reg32a >> 16) & 0x0000ffff); reg32a = ((reg32a << 16) & 0xffff0000) | reg32b; reg32a |= (1 << 31) | (1 << 15); - MCHBAR32(0x140) = reg32a; + MCHBAR32(RCMEASBUFXOVR) = reg32a; } - MCHBAR8(0x130) = MCHBAR8(0x130) | 1; + MCHBAR8_OR(COMPCTRL1, 1); hpet_udelay(1000); - while ((MCHBAR8(0x130) & 0x1) != 0); + while ((MCHBAR8(COMPCTRL1) & 1) != 0) + ; } static void __attribute__((noinline)) @@ -1606,8 +1694,8 @@ sdram_jedec(struct sysinfo *s, u8 rank, u8 jmode, u16 jval) u32 reg32; reg32 = jval << 3; - reg32 |= rank * 0x8000000; - MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | jmode; + reg32 |= rank * (1 << 27); + MCHBAR8_AND_OR(C0JEDEC, ~0x3e, jmode); read32((void *)reg32); barrier(); hpet_udelay(1); // 1us @@ -1616,11 +1704,10 @@ sdram_jedec(struct sysinfo *s, u8 rank, u8 jmode, u16 jval) static void sdram_zqcl(struct sysinfo *s) { if (s->boot_path == BOOT_PATH_RESUME) { - MCHBAR32(0x260) = MCHBAR32(0x260) | (1 << 27); - MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0xe) | NORMAL_OP_CMD; - MCHBAR8(0x271) = MCHBAR8(0x271) & ~0x30; - MCHBAR32(0x268) = (MCHBAR32(0x268) & ~((1 << 30) | (1 << 31))) | - (1 << 30) | (1 << 31); + MCHBAR32_OR(C0CKECTRL, 1 << 27); + MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); + MCHBAR8_AND(C0JEDEC, ~0x30); + MCHBAR32_AND_OR(C0REFRCTRL2, ~(3 << 30), 3 << 30); } } @@ -1650,7 +1737,8 @@ static void sdram_jedecinit(struct sysinfo *s) }; mrs = (s->selected_timings.CAS << 4) | - ((s->selected_timings.tWR - 1) << 9) | (1 << 3) | (1 << 1) | 1; + ((s->selected_timings.tWR - 1) << 9) | (1 << 3) | (1 << 1) | 3; + rttnom = (1 << 2); if (rank_is_populated(s->dimms, 0, 0) && rank_is_populated(s->dimms, 0, 2)) { rttnom |= (1 << 6); @@ -1683,14 +1771,14 @@ static void sdram_misc(struct sysinfo *s) u32 reg32; reg32 = 0; - reg32 |= (0x4 << 13); - reg32 |= (0x6 << 8); - MCHBAR32(0x274) = (MCHBAR32(0x274) & ~0x3ff00) | reg32; - MCHBAR8(0x274) = MCHBAR8(0x274) & ~(1 << 7); - MCHBAR8(0x26c) = MCHBAR8(0x26c) | 1; + reg32 |= (4 << 13); + reg32 |= (6 << 8); + MCHBAR32_AND_OR(C0DYNRDCTRL, ~0x3ff00, reg32); + MCHBAR8_AND(C0DYNRDCTRL, ~(1 << 7)); + MCHBAR8_OR(C0REFRCTRL + 3, 1); if (s->boot_path != BOOT_PATH_RESUME) { - MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0xe) | NORMAL_OP_CMD; - MCHBAR8(0x271) = MCHBAR8(0x271) & ~0x30; + MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); + MCHBAR8_AND(C0JEDEC, ~0x30); } else { sdram_zqcl(s); } @@ -1767,7 +1855,8 @@ static void sdram_dradrb(struct sysinfo *s) FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { i = r / 2; PRINTK_DEBUG("RANK %d PRESENT\n", r); - dra = dratab[s->dimms[i].banks] + dra = dratab + [s->dimms[i].banks] [s->dimms[i].width] [s->dimms[i].cols - 9] [s->dimms[i].rows - 12]; @@ -1775,9 +1864,9 @@ static void sdram_dradrb(struct sysinfo *s) if (s->dimms[i].banks == 1) { dra |= (1 << 7); } - reg32 |= (dra << (r*8)); + reg32 |= (dra << (r * 8)); } - MCHBAR32(0x208) = reg32; + MCHBAR32(C0DRA01) = reg32; c0dra = reg32; PRINTK_DEBUG("C0DRA = 0x%08x\n", c0dra); @@ -1786,17 +1875,17 @@ static void sdram_dradrb(struct sysinfo *s) reg32 |= (1 << r); } reg8 = (u8)(reg32 << 4) & 0xf0; - MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | reg8; - if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || - ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { - MCHBAR8(0x260) = MCHBAR8(0x260) | 1; + MCHBAR8_AND_OR(C0CKECTRL + 2, ~0xf0, reg8); + + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { + MCHBAR8_OR(C0CKECTRL, 1); } - addr = 0x200; + addr = C0DRB0; c0drb = 0; FOR_EACH_RANK(ch, r) { if (rank_is_populated(s->dimms, ch, r)) { - ind = (c0dra >> (8*r)) & 0x7f; + ind = (c0dra >> (8 * r)) & 0x7f; c0drb = (u16)(c0drb + dradrb[ind][5]); s->channel_capacity[0] += dradrb[ind][5] << 6; } @@ -1810,9 +1899,9 @@ static u8 sampledqs(u32 dqshighaddr, u32 strobeaddr, u8 highlow, u8 count) { u8 dqsmatches = 1; while (count--) { - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0x2; + MCHBAR8_AND(C0RSTCTL, ~2); hpet_udelay(1); - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; + MCHBAR8_OR(C0RSTCTL, 2); hpet_udelay(1); barrier(); read32((void *)strobeaddr); @@ -1827,82 +1916,81 @@ static u8 sampledqs(u32 dqshighaddr, u32 strobeaddr, u8 highlow, u8 count) return dqsmatches; } -static void rcvenclock(u8 *coarse, u8 *medium, u8 bytelane) +static void rcvenclock(u8 *coarse, u8 *medium, u8 lane) { if (*medium < 3) { (*medium)++; - MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~(0x3 << (bytelane*2)))) - | (*medium << (bytelane*2)); + MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); } else { *medium = 0; (*coarse)++; - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (*coarse << 16); - MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~0x3 << (bytelane*2))) - | (*medium << (bytelane*2)); + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, *coarse << 16); + MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); } } static void sdram_rcven(struct sysinfo *s) { - u8 curcoarse, savecoarse; - u8 curmedium, savemedium; + u8 coarse, savecoarse; + u8 medium, savemedium; u8 pi, savepi; - u8 bytelane; - u8 bytelanecoarse[8] = { 0 }; - u8 minbytelanecoarse = 0xff; - u8 bytelaneoffset; - u8 maxbytelane = 8; + u8 lane; + u8 lanecoarse[8] = {0}; + u8 minlanecoarse = 0xff; + u8 offset; + u8 maxlane = 8; /* Since dra/drb is already set up we know that at address 0x00000000 we will always find the first available rank */ u32 strobeaddr = 0; u32 dqshighaddr; - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc; - MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; + MCHBAR8_AND(C0RSTCTL, ~0x0c); + MCHBAR8_AND(CMNDQFIFORST, ~0x80); PRINTK_DEBUG("rcven 0\n"); - for (bytelane = 0; bytelane < maxbytelane; bytelane++) { - PRINTK_DEBUG("rcven bytelane %d\n", bytelane); -//trylaneagain: - dqshighaddr = 0x561 + (bytelane << 2); + for (lane = 0; lane < maxlane; lane++) { + PRINTK_DEBUG("rcven lane %d\n", lane); +// trylaneagain: + dqshighaddr = C0MISCCTLy(lane); - curcoarse = s->selected_timings.CAS + 1; + coarse = s->selected_timings.CAS + 1; pi = 0; - curmedium = 0; + medium = 0; - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (curcoarse << 16); - MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~(0x3 << (bytelane*2)))) - | (curmedium << (bytelane*2)); - MCHBAR8(0x560+bytelane*4) = MCHBAR8(0x560+bytelane*4) & ~0x3f; + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); - savecoarse = curcoarse; - savemedium = curmedium; + MCHBAR8_AND(C0RXRCVyDLL(lane), ~0x3f); + + savecoarse = coarse; + savemedium = medium; savepi = pi; PRINTK_DEBUG("rcven 0.1\n"); - //MCHBAR16(0x588) = (MCHBAR16(0x588) & (u16)~(0x3 << (bytelane*2))) | (1 << (bytelane*2)); // XXX comment out + // XXX comment out + // MCHBAR16_AND_OR(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { - //printk(BIOS_DEBUG, "coarse=%d medium=%d\n", curcoarse, curmedium); - rcvenclock(&curcoarse, &curmedium, bytelane); - if (curcoarse > 0xf) { + // printk(BIOS_DEBUG, "coarse=%d medium=%d\n", coarse, medium); + rcvenclock(&coarse, &medium, lane); + if (coarse > 0xf) { PRINTK_DEBUG("Error: coarse > 0xf\n"); - //goto trylaneagain; + // goto trylaneagain; break; } } PRINTK_DEBUG("rcven 0.2\n"); - savecoarse = curcoarse; - savemedium = curmedium; - rcvenclock(&curcoarse, &curmedium, bytelane); + savecoarse = coarse; + savemedium = medium; + rcvenclock(&coarse, &medium, lane); while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) { - savecoarse = curcoarse; - savemedium = curmedium; - rcvenclock(&curcoarse, &curmedium, bytelane); - if (curcoarse > 0xf) { + savecoarse = coarse; + savemedium = medium; + rcvenclock(&coarse, &medium, lane); + if (coarse > 0xf) { PRINTK_DEBUG("Error: coarse > 0xf\n"); //goto trylaneagain; break; @@ -1910,201 +1998,200 @@ static void sdram_rcven(struct sysinfo *s) } PRINTK_DEBUG("rcven 0.3\n"); - curcoarse = savecoarse; - curmedium = savemedium; - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (curcoarse << 16); - MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~(0x3 << bytelane*2))) - | (curmedium << (bytelane*2)); + coarse = savecoarse; + medium = savemedium; + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) { savepi = pi; pi++; if (pi > s->maxpi) { - //if (s->nodll) { + // if (s->nodll) { pi = savepi = s->maxpi; break; - //} + // } } - MCHBAR8(0x560 + bytelane*4) = (MCHBAR8(0x560 + bytelane*4) - & ~0x3f) | (pi << s->pioffset); + MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); } PRINTK_DEBUG("rcven 0.4\n"); pi = savepi; - MCHBAR8(0x560 + bytelane*4) = (MCHBAR8(0x560 + bytelane*4) & ~0x3f) - | (pi << s->pioffset); - rcvenclock(&curcoarse, &curmedium, bytelane); + MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + rcvenclock(&coarse, &medium, lane); + if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) { PRINTK_DEBUG("Error: DQS not high\n"); - //goto trylaneagain; + // goto trylaneagain; } PRINTK_DEBUG("rcven 0.5\n"); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { - curcoarse--; - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) - | (curcoarse << 16); - if (curcoarse == 0) { + coarse--; + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + if (coarse == 0) { PRINTK_DEBUG("Error: DQS did not hit 0\n"); break; } } PRINTK_DEBUG("rcven 0.6\n"); - rcvenclock(&curcoarse, &curmedium, bytelane); - s->pi[bytelane] = pi; - bytelanecoarse[bytelane] = curcoarse; + rcvenclock(&coarse, &medium, lane); + s->pi[lane] = pi; + lanecoarse[lane] = coarse; } PRINTK_DEBUG("rcven 1\n"); - bytelane = maxbytelane; + lane = maxlane; do { - bytelane--; - if (minbytelanecoarse > bytelanecoarse[bytelane]) { - minbytelanecoarse = bytelanecoarse[bytelane]; + lane--; + if (minlanecoarse > lanecoarse[lane]) { + minlanecoarse = lanecoarse[lane]; } - } while (bytelane != 0); + } while (lane != 0); - bytelane = maxbytelane; + lane = maxlane; do { - bytelane--; - bytelaneoffset = bytelanecoarse[bytelane] - minbytelanecoarse; - MCHBAR16(0x5fa) = (MCHBAR16(0x5fa) & (u16)(~(0x3 << (bytelane*2)))) - | (bytelaneoffset << (bytelane*2)); - } while (bytelane != 0); + lane--; + offset = lanecoarse[lane] - minlanecoarse; + MCHBAR16_AND_OR(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); + } while (lane != 0); - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (minbytelanecoarse << 16); + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, minlanecoarse << 16); - s->coarsectrl = minbytelanecoarse; - s->coarsedelay = MCHBAR16(0x5fa); - s->mediumphase = MCHBAR16(0x58c); - s->readptrdelay = MCHBAR16(0x588); + s->coarsectrl = minlanecoarse; + s->coarsedelay = MCHBAR16(C0COARSEDLY0); + s->mediumphase = MCHBAR16(C0RCVMISCCTL2); + s->readptrdelay = MCHBAR16(C0RCVMISCCTL1); PRINTK_DEBUG("rcven 2\n"); - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xe; - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x4; - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x8; + MCHBAR8_AND(C0RSTCTL, ~0x0e); + MCHBAR8_OR(C0RSTCTL, 0x02); + MCHBAR8_OR(C0RSTCTL, 0x04); + MCHBAR8_OR(C0RSTCTL, 0x08); - MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; - MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; - MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; + MCHBAR8_OR(CMNDQFIFORST, 0x80); + MCHBAR8_AND(CMNDQFIFORST, ~0x80); + MCHBAR8_OR(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 3\n"); } +/* NOTE: Unless otherwise specified, the values are expressed in MiB */ static void sdram_mmap_regs(struct sysinfo *s) { bool reclaim; - u32 tsegsize; - u32 mmiosize; - u32 tom, tolud, touud, reclaimbase, reclaimlimit; - u32 gfxbase, gfxsize, gttbase, gttsize, tsegbase; + u32 mmiosize, tom, tolud, touud, reclaimbase, reclaimlimit; + u32 gfxbase, gfxsize, gttbase, gttsize, tsegbase, tsegsize; u16 ggc; - u16 ggc_to_uma[10] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256 }; - u8 ggc_to_gtt[4] = { 0, 1, 0, 0 }; + u16 ggc_to_uma[10] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256}; + u8 ggc_to_gtt[4] = {0, 1, 0, 0}; - reclaimbase = 0; + reclaimbase = 0; reclaimlimit = 0; - ggc = pci_read_config16(PCI_DEV(0,0,0), GGC); + + ggc = pci_read_config16(HOST_BRIDGE, GGC); printk(BIOS_DEBUG, "GGC = 0x%04x\n", ggc); - gfxsize = ggc_to_uma[(ggc & 0xf0) >> 4]; - gttsize = ggc_to_gtt[(ggc & 0x300) >> 8]; + + gfxsize = ggc_to_uma[(ggc & 0x00f0) >> 4]; + + gttsize = ggc_to_gtt[(ggc & 0x0300) >> 8]; + tom = s->channel_capacity[0]; - /* with GTT always being 1M, TSEG 1M is the only setting that can + /* With GTT always being 1M, TSEG 1M is the only setting that can be covered by SMRR which has alignment requirements. */ - tsegsize = 0x1; - mmiosize = 0x400; // 1GB + tsegsize = 1; + mmiosize = 1024; reclaim = false; - tolud = MIN(0x1000 - mmiosize, tom); - if ((tom - tolud) > 0x40) { + tolud = MIN(4096 - mmiosize, tom); + if ((tom - tolud) > 64) { reclaim = true; } if (reclaim) { tolud = tolud & ~0x3f; - tom = tom & ~0x3f; - reclaimbase = MAX(0x1000, tom); - reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; + tom = tom & ~0x3f; + reclaimbase = MAX(4096, tom); + reclaimlimit = reclaimbase + (MIN(4096, tom) - tolud) - 0x40; } touud = tom; if (reclaim) { - touud = reclaimlimit + 0x40; + touud = reclaimlimit + 64; } - gfxbase = tolud - gfxsize; - gttbase = gfxbase - gttsize; + gfxbase = tolud - gfxsize; + gttbase = gfxbase - gttsize; tsegbase = gttbase - tsegsize; /* Program the regs */ - pci_write_config16(PCI_DEV(0,0,0), TOLUD, (u16)(tolud << 4)); - pci_write_config16(PCI_DEV(0,0,0), TOM, (u16)(tom >> 6)); + pci_write_config16(HOST_BRIDGE, TOLUD, (u16)(tolud << 4)); + pci_write_config16(HOST_BRIDGE, TOM, (u16)(tom >> 6)); if (reclaim) { - pci_write_config16(PCI_DEV(0,0,0), 0x98, (u16)(reclaimbase >> 6)); - pci_write_config16(PCI_DEV(0,0,0), 0x9a, (u16)(reclaimlimit >> 6)); + pci_write_config16(HOST_BRIDGE, 0x98, (u16)(reclaimbase >> 6)); + pci_write_config16(HOST_BRIDGE, 0x9a, (u16)(reclaimlimit >> 6)); } - pci_write_config16(PCI_DEV(0,0,0), TOUUD, (u16)(touud)); - pci_write_config32(PCI_DEV(0,0,0), GBSM, gfxbase << 20); - pci_write_config32(PCI_DEV(0,0,0), BGSM, gttbase << 20); - pci_write_config32(PCI_DEV(0,0,0), TSEG, tsegbase << 20); + pci_write_config16(HOST_BRIDGE, TOUUD, (u16)(touud)); + pci_write_config32(HOST_BRIDGE, GBSM, gfxbase << 20); + pci_write_config32(HOST_BRIDGE, BGSM, gttbase << 20); + pci_write_config32(HOST_BRIDGE, TSEG, tsegbase << 20); - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); - reg8 &= ~0x7; + u8 reg8 = pci_read_config8(HOST_BRIDGE, ESMRAMC); + reg8 &= ~0x07; reg8 |= (0 << 1) | (1 << 0); /* 1M and TSEG_Enable */ - pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); + pci_write_config8(HOST_BRIDGE, ESMRAMC, reg8); printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n", - pci_read_config32(PCI_DEV(0,0,0), GBSM), gfxbase << 20); + pci_read_config32(HOST_BRIDGE, GBSM), gfxbase << 20); printk(BIOS_DEBUG, "BGSM (gtt) = verified %08x (written %08x)\n", - pci_read_config32(PCI_DEV(0,0,0), BGSM), gttbase << 20); + pci_read_config32(HOST_BRIDGE, BGSM), gttbase << 20); printk(BIOS_DEBUG, "TSEG (smm) = verified %08x (written %08x)\n", - pci_read_config32(PCI_DEV(0,0,0), TSEG), tsegbase << 20); + pci_read_config32(HOST_BRIDGE, TSEG), tsegbase << 20); } static void sdram_enhancedmode(struct sysinfo *s) { - u8 reg8, ch, r, j, i; + u8 reg8, ch, r, fsb_freq, ddr_freq; u32 mask32, reg32; - MCHBAR8(0x246) = MCHBAR8(0x246) | 1; - MCHBAR8(0x269 + 3) = MCHBAR8(0x269 + 3) | 1; + MCHBAR8_OR(C0ADDCSCTRL, 1); + MCHBAR8_OR(C0REFRCTRL + 3, 1); mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f; - reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10; - MCHBAR32(0x120) = (MCHBAR32(0x120) & ~mask32) | reg32; - MCHBAR8(0x288 + 1) = 0x2; - MCHBAR16(0x288 + 2) = 0x0804; - MCHBAR16(0x288 + 4) = 0x2010; - MCHBAR8(0x288 + 6) = 0x40; - MCHBAR16(0x288 + 8) = 0x091c; - MCHBAR8(0x288 + 10) = 0xf2; - MCHBAR8(0x241) = MCHBAR8(0x241) | 1; - MCHBAR8(0x243) = MCHBAR8(0x243) | 1; - MCHBAR16(0x272) = MCHBAR16(0x272) | 0x100; + reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10; + MCHBAR32_AND_OR(WRWMCONFIG, ~mask32, reg32); + MCHBAR8(C0DITCTRL + 1) = 2; + MCHBAR16(C0DITCTRL + 2) = 0x0804; + MCHBAR16(C0DITCTRL + 4) = 0x2010; + MCHBAR8(C0DITCTRL + 6) = 0x40; + MCHBAR16(C0DITCTRL + 8) = 0x091c; + MCHBAR8(C0DITCTRL + 10) = 0xf2; + MCHBAR8_OR(C0BYPCTRL, 1); + MCHBAR8_OR(C0CWBCTRL, 1); + MCHBAR16_OR(C0ARBSPL, 0x0100); - reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); - pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 | 1); - MCHBAR32(0xfa0) = 0x00000002; - MCHBAR32(0xfa4) = 0x20310002; - MCHBAR32(0x24) = 0x02020302; - MCHBAR32(0x30) = 0x001f1806; - MCHBAR32(0x34) = 0x01102800; - MCHBAR32(0x38) = 0x07000000; - MCHBAR32(0x3c) = 0x01014010; - MCHBAR32(0x40) = 0x0f038000; - reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); - pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1); + reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); + pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1); + MCHBAR32(SBCTL) = 0x00000002; + MCHBAR32(SBCTL2) = 0x20310002; + MCHBAR32(SLIMCFGTMG) = 0x02020302; + MCHBAR32(HIT0) = 0x001f1806; + MCHBAR32(HIT1) = 0x01102800; + MCHBAR32(HIT2) = 0x07000000; + MCHBAR32(HIT3) = 0x01014010; + MCHBAR32(HIT4) = 0x0f038000; + reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); + pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1); u32 nranks, curranksize, maxranksize, dra; u8 rankmismatch; - static const u8 drbtab[10] = { 0x4, 0x2, 0x8, 0x4, 0x8, 0x4, 0x10, 0x8, - 0x20, 0x10 }; + static const u8 drbtab[10] = {0x4, 0x2, 0x8, 0x4, 0x8, 0x4, 0x10, 0x8, 0x20, 0x10}; nranks = 0; curranksize = 0; maxranksize = 0; rankmismatch = 0; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { nranks++; - dra = (u8) ((MCHBAR32(0x208) >> (8*r)) & 0x7f); + dra = (u8) ((MCHBAR32(C0DRA01) >> (8 * r)) & 0x7f); curranksize = drbtab[dra]; if (maxranksize == 0) { maxranksize = curranksize; @@ -2138,45 +2225,47 @@ static void sdram_enhancedmode(struct sysinfo *s) die("Invalid number of ranks found, halt\n"); break; } - MCHBAR8(0x111) = (MCHBAR8(0x111) & ~0xfc) | (reg8 & 0xfc); - MCHBAR32(0xd0) = MCHBAR32(0xd0) & ~0x80000000; + MCHBAR8_AND_OR(CHDECMISC, ~0xfc, reg8 & 0xfc); + MCHBAR32_AND(NOACFGBUSCTL, ~0x80000000); - MCHBAR32(0x28) = 0xf; - MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 1; + MCHBAR32(HTBONUS0) = 0x0000000f; + MCHBAR8_OR(C0COREBONUS + 4, 1); + + MCHBAR32_AND(HIT3, ~0x0e000000); + MCHBAR32_AND_OR(HIT4, ~0x000c0000, 0x00040000); - MCHBAR32(0x3c) = MCHBAR32(0x3c) & ~0xe000000; - MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0xc0000) | 0x40000; u32 clkcx[2][2][3] = { - { - {0, 0x0c080302, 0x08010204}, // 667 - {0x02040000, 0x08100102, 0} - }, - { - {0x18000000, 0x3021060c, 0x20010208}, - {0, 0x0c090306, 0} // 800 - } - }; - j = s->selected_timings.fsb_clock; - i = s->selected_timings.mem_clock; + { + {0x00000000, 0x0c080302, 0x08010204}, /* FSB = 667, DDR = 667 */ + {0x02040000, 0x08100102, 0x00000000}, /* FSB = 667, DDR = 800 */ + }, + { + {0x18000000, 0x3021060c, 0x20010208}, /* FSB = 800, DDR = 667 */ + {0x00000000, 0x0c090306, 0x00000000}, /* FSB = 800, DDR = 800 */ + } + }; - MCHBAR32(0x708) = clkcx[j][i][0]; - MCHBAR32(0x70c) = clkcx[j][i][1]; - MCHBAR32(0x6dc) = clkcx[j][i][2]; - MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2; + fsb_freq = s->selected_timings.fsb_clock; + ddr_freq = s->selected_timings.mem_clock; + + MCHBAR32(CLKXSSH2X2MD) = clkcx[fsb_freq][ddr_freq][0]; + MCHBAR32(CLKXSSH2X2MD + 4) = clkcx[fsb_freq][ddr_freq][1]; + MCHBAR32(CLKXSSH2MCBYP + 4) = clkcx[fsb_freq][ddr_freq][2]; + + MCHBAR8_AND(HIT4, ~0x02); } static void sdram_periodic_rcomp(void) { - MCHBAR8(0x130) = MCHBAR8(0x130) & ~0x2; - while ((MCHBAR32(0x130) & 0x80000000) > 0) { + MCHBAR8_AND(COMPCTRL1, ~0x02); + while ((MCHBAR32(COMPCTRL1) & 0x80000000) > 0) { ; } - MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x3000); + MCHBAR16_AND(CSHRMISCCTL, ~0x3000); + MCHBAR8_OR(CMNDQFIFORST, 0x80); + MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 0x09); - MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; - MCHBAR16(0x170) = (MCHBAR16(0x170) & ~0xf) | 0x9; - - MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82; + MCHBAR8_OR(COMPCTRL1, 0x82); } static void sdram_new_trd(struct sysinfo *s) @@ -2224,22 +2313,22 @@ static void sdram_new_trd(struct sysinfo *s) pidelay = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 24 : 20; for (i = 0; i < 8; i++) { - rcvendelay = ((u32)((s->coarsedelay >> (i << 1)) & 0x3) * (u32)(tmclk)); - rcvendelay += ((u32)((s->readptrdelay >> (i << 1)) & 0x3) * (u32)(tmclk) / 2); - rcvendelay += ((u32)((s->mediumphase >> (i << 1)) & 0x3) * (u32)(tmclk) / 4); - rcvendelay += (u32)(pidelay * s->pi[i]); + rcvendelay = ((u32)((s->coarsedelay >> (i << 1)) & 3) * (u32)(tmclk)); + rcvendelay += ((u32)((s->readptrdelay >> (i << 1)) & 3) * (u32)(tmclk) / 2); + rcvendelay += ((u32)((s->mediumphase >> (i << 1)) & 3) * (u32)(tmclk) / 4); + rcvendelay += (u32)(pidelay * s->pi[i]); maxrcvendelay = MAX(maxrcvendelay, rcvendelay); } - if ((MCHBAR8(0xc54+3) == 0xff) && (MCHBAR8(0xc08) & 0x80)) { + if ((MCHBAR8(HMBYPCP + 3) == 0xff) && (MCHBAR8(HMCCMC) & 0x80)) { bypass = 1; } else { bypass = 0; } txfifo = 0; - reg8 = (MCHBAR8(0x188) & 0xe) >> 1; - txfifo = txfifo_lut[reg8] & 0x7; + reg8 = (MCHBAR8(CSHRFIFOCTL) & 0x0e) >> 1; + txfifo = txfifo_lut[reg8] & 0x07; datadelay = tmclk * (2*txfifo + 4*s->coarsectrl + 4*(bypass-1) + 13) / 4 + tio + maxrcvendelay + pidelay + buffertocore + postcalib; @@ -2264,7 +2353,7 @@ static void sdram_new_trd(struct sysinfo *s) } } - MCHBAR16(0x248) = (MCHBAR16(0x248) & ~0x1f00) | (trd << 8); + MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, trd << 8); } static void sdram_powersettings(struct sysinfo *s) @@ -2273,136 +2362,142 @@ static void sdram_powersettings(struct sysinfo *s) u32 reg32; /* Thermal sensor */ - MCHBAR8(0x3808) = 0x9b; - MCHBAR32(0x380c) = (MCHBAR32(0x380c) & ~0x00ffffff) | 0x1d00; - MCHBAR8(0x3814) = 0x08; - MCHBAR8(0x3824) = 0x00; - MCHBAR8(0x3809) = (MCHBAR8(0x3809) & ~0xf) | 0x4; - MCHBAR8(0x3814) = (MCHBAR8(0x3814) & ~1) | 1; - MCHBAR8(0x3812) = (MCHBAR8(0x3812) & ~0x80) | 0x80; + MCHBAR8(TSC1) = 0x9b; + MCHBAR32_AND_OR(TSTTP, ~0x00ffffff, 0x1d00); + MCHBAR8(THERM1) = 0x08; + MCHBAR8(TSC3) = 0x00; + MCHBAR8_AND_OR(TSC2, ~0x0f, 0x04); + MCHBAR8_AND_OR(THERM1, ~1, 1); + MCHBAR8_AND_OR(TCO, ~0x80, 0x80); /* Clock gating */ - MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0x00040001; - MCHBAR8(0xfac+3) = MCHBAR8(0xfac+3) & ~0x80; - MCHBAR8(0xff8+3) = MCHBAR8(0xff8+3) & ~0x80; - MCHBAR16(0xff0) = MCHBAR16(0xff0) & ~0x1fff; - MCHBAR32(0xfb0) = MCHBAR32(0xfb0) & ~0x0001ffff; - MCHBAR16(0x48) = (MCHBAR16(0x48) & ~0x03ff) & 0x6; - MCHBAR32(0x20) = (MCHBAR32(0x20) & ~0xffffffff) | 0x20; - MCHBAR8(0xd14) = MCHBAR8(0xd14) & ~1; - MCHBAR8(0x239) = s->selected_timings.CAS - 1 + 0x15; - MCHBAR16(0x2d1) = (MCHBAR16(0x2d1) & ~0x07fc) | 0x40; - MCHBAR16(0x6d1) = (MCHBAR16(0x6d1) & ~0x0fff) | 0xd00; - MCHBAR16(0x210) = MCHBAR16(0x210) & ~0x0d80; - MCHBAR16(0xf6c+2) = 0xffff; + MCHBAR32_AND(PMMISC, ~0x00040001); + MCHBAR8_AND(SBCTL3 + 3, ~0x80); + MCHBAR8_AND(CISDCTRL + 3, ~0x80); + MCHBAR16_AND(CICGDIS, ~0x1fff); + MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); + MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); + MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); + MCHBAR8_AND(TSMISC, ~1); + MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; + MCHBAR16_AND_OR(CLOCKGATINGI, ~0x07fc, 0x0040); + MCHBAR16_AND_OR(CLOCKGATINGII, ~0x0fff, 0x0d00); + MCHBAR16_AND(CLOCKGATINGIII, ~0x0d80); + MCHBAR16(GTDPCGC + 2) = 0xffff; /* Sequencing */ - MCHBAR32(0x14) = (MCHBAR32(0x14) & ~0x1fffffff) | 0x1f643fff; - MCHBAR32(0x18) = (MCHBAR32(0x18) & ~0xffffff7f) | 0x02010000; - MCHBAR16(0x1c) = (MCHBAR16(0x1c) & ~0x7000) | (0x3 << 12); + MCHBAR32(HPWRCTL1) = (MCHBAR32(HPWRCTL1) & ~0x1fffffff) | 0x1f643fff; + MCHBAR32(HPWRCTL2) = (MCHBAR32(HPWRCTL2) & ~0xffffff7f) | 0x02010000; + MCHBAR16(HPWRCTL3) = (MCHBAR16(HPWRCTL3) & ~0x7000) | (3 << 12); /* Power */ - MCHBAR32(0x1104) = (MCHBAR32(0x1104) & ~0xffff0003) | 0x10100000; - MCHBAR32(0x1108) = (MCHBAR32(0x1108) & ~0x0001bff7) | 0x00000078; - if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) { - MCHBAR16(0x110c) = (MCHBAR16(0x110c) & ~0x03ff) | 0xc8; - } else { - MCHBAR16(0x110c) = (MCHBAR16(0x110c) & ~0x03ff) | 0x100; - } + MCHBAR32(GFXC3C4) = (MCHBAR32(GFXC3C4) & ~0xffff0003) | 0x10100000; + MCHBAR32(PMDSLFRC) = (MCHBAR32(PMDSLFRC) & ~0x0001bff7) | 0x00000078; + + if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) + MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x00c8); + else + MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x0100); + j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1; - MCHBAR32(0x1110) = (MCHBAR32(0x1110) & ~0x1fff37f) | 0x10810700; - MCHBAR8(0x1114) = (MCHBAR8(0x1114) & ~0x07) | 1; - MCHBAR8(0x1124) = MCHBAR8(0x1124) & ~0x02; + MCHBAR32_AND_OR(PMCLKRC, ~0x01fff37f, 0x10810700); + MCHBAR8_AND_OR(PMPXPRC, ~0x07, 1); + MCHBAR8_AND(PMBAK, ~0x02); - static const u16 ddr2lut[2][4][2] = {{ - {0x0000, 0x0000}, - {0x019A, 0x0039}, - {0x0099, 0x1049}, - {0x0000, 0x0000} - }, - { - {0x0000, 0x0000}, - {0x019A, 0x0039}, - {0x0099, 0x1049}, - {0x0099, 0x2159} - }}; + static const u16 ddr2lut[2][4][2] = { + { + {0x0000, 0x0000}, + {0x019A, 0x0039}, + {0x0099, 0x1049}, + {0x0000, 0x0000}, + }, + { + {0x0000, 0x0000}, + {0x019A, 0x0039}, + {0x0099, 0x1049}, + {0x0099, 0x2159}, + }, + }; - MCHBAR16(0x23c) = 0x7a89; - MCHBAR8(0x117) = 0xaa; - MCHBAR16(0x118) = ddr2lut[j][s->selected_timings.CAS - 3][1]; - MCHBAR16(0x115) = (MCHBAR16(0x115) & ~0x7fff) | ddr2lut[j] - [s->selected_timings.CAS - 3][0]; - MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0xf000) | 0xf000; - MCHBAR8(0x2c02) = (MCHBAR8(0x2c02) & ~0x77) | (4 << 4 | 4); - if (s->nodll) { - reg32 = 0x30000000; - } else { - reg32 = 0; - } - MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x0f000000) | 0x20000000 | reg32; - MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0x00f00000) | 0x00f00000; - MCHBAR32(0x6d0) = (MCHBAR32(0x6d0) & ~0x001ff000) | (0xbf << 20); - MCHBAR16(0x610) = (MCHBAR16(0x610) & ~0x1f7f) | (0xb << 8) | (7 << 4) | 0xb; - MCHBAR16(0x612) = 0x3264; - MCHBAR16(0x614) = (MCHBAR16(0x614) & ~0x3f3f) | (0x14 << 8) | 0xa; + MCHBAR16(C0C2REG) = 0x7a89; + MCHBAR8(SHC2REGII) = 0xaa; + MCHBAR16(SHC2REGII + 1) = ddr2lut[j][s->selected_timings.CAS - 3][1]; + MCHBAR16_AND_OR(SHC2REGI, ~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); + MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, 0xf000); + MCHBAR8(CSHWRIOBONUSX) = (MCHBAR8(CSHWRIOBONUSX) & ~0x77) | (4 << 4 | 4); - MCHBAR32(0x6c0) = MCHBAR32(0x6c0) | 0x80002000; + reg32 = s->nodll ? 0x30000000 : 0; + + /* FIXME: Compacting this results in changes to the binary */ + MCHBAR32(C0COREBONUS) = (MCHBAR32(C0COREBONUS) & ~0x0f000000) | 0x20000000 | reg32; + + MCHBAR32_AND_OR(CLOCKGATINGI, ~0x00f00000, 0x00f00000); + MCHBAR32_AND_OR(CLOCKGATINGII - 1, ~0x001ff000, 0xbf << 20); + MCHBAR16_AND_OR(SHC3C4REG2, ~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); + MCHBAR16(SHC3C4REG3) = 0x3264; + MCHBAR16_AND_OR(SHC3C4REG4, ~0x3f3f, (0x14 << 8) | 0x0a); + + MCHBAR32_OR(C1COREBONUS, 0x80002000); } static void sdram_programddr(void) { - MCHBAR16(0x6d1) = (MCHBAR16(0x6d1) & ~0x03ff) | 0x100; - MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x003f) | 0x10; - MCHBAR16(0x2d1) = (MCHBAR16(0x2d1) & ~0x7000) | 0x2000; - MCHBAR8(0x180) = MCHBAR8(0x180) & ~0xe; - MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0xc; - MCHBAR8(0x561) = MCHBAR8(0x561) & ~0xe; - MCHBAR8(0x565) = MCHBAR8(0x565) & ~0xe; - MCHBAR8(0x569) = MCHBAR8(0x569) & ~0xe; - MCHBAR8(0x56d) = MCHBAR8(0x56d) & ~0xe; - MCHBAR8(0x571) = MCHBAR8(0x571) & ~0xe; - MCHBAR8(0x575) = MCHBAR8(0x575) & ~0xe; - MCHBAR8(0x579) = MCHBAR8(0x579) & ~0xe; - MCHBAR8(0x57d) = MCHBAR8(0x57d) & ~0xe; - MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x2; - MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x400; - MCHBAR16(0x210) = MCHBAR16(0x210) & ~0xdc0; - MCHBAR8(0x239) = MCHBAR8(0x239) & ~0x80; - MCHBAR32(0x2c0) = MCHBAR32(0x2c0) & ~(1 << 22); - MCHBAR16(0x2d1) = MCHBAR16(0x2d1) & ~0x80fc; - MCHBAR16(0x6d1) = MCHBAR16(0x6d1) & ~0xc00; - MCHBAR8(0x180) = MCHBAR8(0x180) & ~0xd; - MCHBAR8(0x561) = MCHBAR8(0x561) & ~1; - MCHBAR8(0x565) = MCHBAR8(0x565) & ~1; - MCHBAR8(0x569) = MCHBAR8(0x569) & ~1; - MCHBAR8(0x56d) = MCHBAR8(0x56d) & ~1; - MCHBAR8(0x571) = MCHBAR8(0x571) & ~1; - MCHBAR8(0x575) = MCHBAR8(0x575) & ~1; - MCHBAR8(0x579) = MCHBAR8(0x579) & ~1; - MCHBAR8(0x57d) = MCHBAR8(0x57d) & ~1; - MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0x700000) | (0x3 << 20); - MCHBAR32(0x2c0) = MCHBAR32(0x2c0) & ~0x100000; - MCHBAR8(0x592) = MCHBAR8(0x592) | 0x1e; - MCHBAR8(0x2c15) = MCHBAR8(0x2c15) | 0x3; - MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000; - MCHBAR16(0x248) = MCHBAR16(0x248) | 0x6000; - MCHBAR32(0x260) = MCHBAR32(0x260) | 0x10000; - MCHBAR8(0x2c0) = MCHBAR8(0x2c0) | 0x10; - MCHBAR32(0x2d0) = MCHBAR32(0x2d0) | (0xf << 24); - MCHBAR8(0x189) = MCHBAR8(0x189) | 0x7; - MCHBAR8(0x592) = MCHBAR8(0x592) | 0xc0; - MCHBAR8(0x124) = MCHBAR8(0x124) | 0x7; - MCHBAR16(0x12a) = (MCHBAR16(0x12a) & ~0xffff) | 0x0080; - MCHBAR8(0x12c) = (MCHBAR8(0x12c) & ~0xff) | 0x10; - MCHBAR16(0x2c0) = MCHBAR16(0x2c0) | 0x1e0; - MCHBAR8(0x189) = MCHBAR8(0x189) | 0x18; - MCHBAR8(0x193) = MCHBAR8(0x193) | 0xd; - MCHBAR16(0x212) = MCHBAR16(0x212) | 0xa3f; - MCHBAR8(0x248) = MCHBAR8(0x248) | 0x3; - MCHBAR8(0x268) = (MCHBAR8(0x268) & ~0xff) | 0x4a; - MCHBAR8(0x2c4) = MCHBAR8(0x2c4) & ~0x60; - MCHBAR16(0x592) = MCHBAR16(0x592) | 0x321; + MCHBAR16_AND_OR(CLOCKGATINGII, ~0x03ff, 0x0100); + MCHBAR16_AND_OR(CLOCKGATINGIII, ~0x003f, 0x0010); + MCHBAR16_AND_OR(CLOCKGATINGI, ~0x7000, 0x2000); + + MCHBAR8_AND(CSHRPDCTL, ~0x0e); + MCHBAR8_AND(CSHRWRIOMLNS, ~0x0c); + MCHBAR8_AND(C0MISCCTLy(0), ~0x0e); + MCHBAR8_AND(C0MISCCTLy(1), ~0x0e); + MCHBAR8_AND(C0MISCCTLy(2), ~0x0e); + MCHBAR8_AND(C0MISCCTLy(3), ~0x0e); + MCHBAR8_AND(C0MISCCTLy(4), ~0x0e); + MCHBAR8_AND(C0MISCCTLy(5), ~0x0e); + MCHBAR8_AND(C0MISCCTLy(6), ~0x0e); + MCHBAR8_AND(C0MISCCTLy(7), ~0x0e); + MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); + + MCHBAR16_AND(CSHRMISCCTL, ~0x0400); + MCHBAR16_AND(CLOCKGATINGIII, ~0x0dc0); + MCHBAR8_AND(C0WRDPYN, ~0x80); + MCHBAR32_AND(C0COREBONUS, ~(1 << 22)); + MCHBAR16_AND(CLOCKGATINGI, ~0x80fc); + MCHBAR16_AND(CLOCKGATINGII, ~0x0c00); + + MCHBAR8_AND(CSHRPDCTL, ~0x0d); + MCHBAR8_AND(C0MISCCTLy(0), ~1); + MCHBAR8_AND(C0MISCCTLy(1), ~1); + MCHBAR8_AND(C0MISCCTLy(2), ~1); + MCHBAR8_AND(C0MISCCTLy(3), ~1); + MCHBAR8_AND(C0MISCCTLy(4), ~1); + MCHBAR8_AND(C0MISCCTLy(5), ~1); + MCHBAR8_AND(C0MISCCTLy(6), ~1); + MCHBAR8_AND(C0MISCCTLy(7), ~1); + + MCHBAR32_AND_OR(C0STATRDCTRL, ~0x00700000, 3 << 20); + MCHBAR32_AND(C0COREBONUS, ~0x00100000); + MCHBAR8_OR(C0DYNSLVDLLEN, 0x1e); + MCHBAR8_OR(C0DYNSLVDLLEN2, 0x03); + MCHBAR32_AND_OR(SHCYCTRKCKEL, ~0x0c000000, 0x04000000); + MCHBAR16_OR(C0STATRDCTRL, 0x6000); + MCHBAR32_OR(C0CKECTRL, 0x00010000); + MCHBAR8_OR(C0COREBONUS, 0x10); + MCHBAR32_OR(CLOCKGATINGI - 1, 0xf << 24); + MCHBAR8_OR(CSHWRIOBONUS, 0x07); + MCHBAR8_OR(C0DYNSLVDLLEN, 0xc0); + MCHBAR8_OR(SHC2REGIII, 7); + MCHBAR16_AND_OR(SHC2MINTM, ~0xffff, 0x0080); + MCHBAR8_AND_OR(SHC2IDLETM, ~0xff, 0x10); + MCHBAR16_OR(C0COREBONUS, 0x01e0); + MCHBAR8_OR(CSHWRIOBONUS, 0x18); + MCHBAR8_OR(CSHRMSTDYNDLLENB, 0x0d); + MCHBAR16_OR(SHC3C4REG1, 0x0a3f); + MCHBAR8_OR(C0STATRDCTRL, 3); + MCHBAR8_AND_OR(C0REFRCTRL2, ~0xff, 0x4a); + MCHBAR8_AND(C0COREBONUS + 4, ~0x60); + MCHBAR16_OR(C0DYNSLVDLLEN, 0x0321); } static void sdram_programdqdqs(struct sysinfo *s) @@ -2412,7 +2507,7 @@ static void sdram_programdqdqs(struct sysinfo *s) u8 repeat, halfclk, feature, reg8, push; u16 cwb, pimdclk; u32 reg32; - static const u8 txfifotab[8] = { 0, 7, 6, 5, 2, 1, 4, 3 }; + static const u8 txfifotab[8] = {0, 7, 6, 5, 2, 1, 4, 3}; tpi = 3000; dqdqs_out = 4382; @@ -2434,22 +2529,22 @@ static void sdram_programdqdqs(struct sysinfo *s) mdclk = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 3000 : 2500; refclk = 3000 - mdclk; - coretomcp = ((MCHBAR8(0x246) >> 2) & 0x3) + 1; + coretomcp = ((MCHBAR8(C0ADDCSCTRL) >> 2) & 0x3) + 1; coretomcp *= mdclk; - reg8 = (MCHBAR8(0x188) & 0xe) >> 1; + reg8 = (MCHBAR8(CSHRFIFOCTL) & 0x0e) >> 1; while (repeat) { txdelay = mdclk * ( - ((MCHBAR16(0x220) >> 8) & 0x7) + - (MCHBAR8(0x24d) & 0xf) + - (MCHBAR8(0x24e) & 0x1) + ((MCHBAR16(C0GNT2LNCH1) >> 8) & 0x7) + + (MCHBAR8(C0WRDATACTRL) & 0xf) + + (MCHBAR8(C0WRDATACTRL + 1) & 0x1) ) + - txfifotab[reg8]*(mdclk/2) + + txfifotab[reg8]*(mdclk / 2) + coretomcp + refclk + cwb; - halfclk = (MCHBAR8(0x5d9) >> 1) & 0x1; + halfclk = (MCHBAR8(C0MISCCTL) >> 1) & 0x1; if (halfclk) { txdelay -= mdclk / 2; reg32 = dqdqs_outdelay + coretomcp - mdclk / 2; @@ -2462,25 +2557,25 @@ static void sdram_programdqdqs(struct sysinfo *s) if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) { if (repeat == 2) { - MCHBAR32(0x2c0) = MCHBAR32(0x2c0) & ~(1 << 23); + MCHBAR32_AND(C0COREBONUS, ~(1 << 23)); } feature = 1; repeat = 0; } else { repeat--; - MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | (1 << 23); + MCHBAR32_OR(C0COREBONUS, 1 << 23); cwb = 2 * mdclk; } } if (!feature) { - MCHBAR8(0x2d1) = MCHBAR8(0x2d1) & ~0x3; + MCHBAR8(CLOCKGATINGI) = MCHBAR8(CLOCKGATINGI) & ~0x3; return; } - MCHBAR8(0x2d1) = MCHBAR8(0x2d1) | 0x3; - MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0xf000) | (pimdclk << 12); - MCHBAR8(0x2c02) = (MCHBAR8(0x2c02) & ~0x77) | (push << 4) | push; - MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xf000000) | 0x3000000; + MCHBAR8_OR(CLOCKGATINGI, 3); + MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, pimdclk << 12); + MCHBAR8_AND_OR(CSHWRIOBONUSX, ~0x77, (push << 4) | push); + MCHBAR32_AND_OR(C0COREBONUS, ~0x0f000000, 0x03000000); } /** @@ -2490,7 +2585,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) { struct sysinfo si; u8 reg8; - const char *boot_str[] = { "Normal", "Reset", "Resume"}; + const char *boot_str[] = {"Normal", "Reset", "Resume"}; PRINTK_DEBUG("Setting up RAM controller.\n"); @@ -2514,7 +2609,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Enable HPET */ enable_hpet(); - MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); + MCHBAR16_OR(CPCTL, 1 << 15); sdram_clk_crossing(&si); @@ -2541,24 +2636,24 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) PRINTK_DEBUG("Done odt\n"); if (si.boot_path != BOOT_PATH_RESET) { - while ((MCHBAR8(0x130) & 0x1) != 0) + while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; } sdram_mmap(&si); PRINTK_DEBUG("Done mmap\n"); - // Enable DDR IO buffer - MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x8; - MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x1; + /* Enable DDR IO buffer */ + MCHBAR8_AND_OR(C0IOBUFACTCTL, ~0x3f, 0x08); + MCHBAR8_OR(C0RSTCTL, 1); sdram_rcompupdate(&si); PRINTK_DEBUG("Done RCOMP update\n"); - MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2; + MCHBAR8_OR(HIT4, 2); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32(0x260) = MCHBAR32(0x260) | (1 << 27); + MCHBAR32_OR(C0CKECTRL, 1 << 27); sdram_jedecinit(&si); PRINTK_DEBUG("Done MRS\n"); @@ -2571,7 +2666,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) PRINTK_DEBUG("Done zqcl\n"); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32(0x268) = MCHBAR32(0x268) | 0xc0000000; + MCHBAR32_OR(C0REFRCTRL2, 3 << 30); } sdram_dradrb(&si); @@ -2602,15 +2697,15 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) PRINTK_DEBUG("Done periodic RCOMP\n"); /* Set init done */ - MCHBAR32(0x268) = MCHBAR32(0x268) | 0x40000000; + MCHBAR32_OR(C0REFRCTRL2, 1 << 30); /* Tell ICH7 that we're done */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80); /* Tell northbridge we're done */ - reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf4); - pci_write_config8(PCI_DEV(0,0,0), 0xf4, reg8 | 1); + reg8 = pci_read_config8(HOST_BRIDGE, 0xf4); + pci_write_config8(HOST_BRIDGE, 0xf4, reg8 | 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index ce4cd5531b..9a8f5d50f6 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -13,10 +13,6 @@ * GNU General Public License for more details. */ -/* Platform has no romstage entry point under mainboard directory, - * so this one is named with prefix mainboard. - */ - #include #include #include @@ -32,7 +28,7 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ + /* Set up Virtual Channel 0 */ RCBA32(0x0014) = 0x80000001; RCBA32(0x001c) = 0x03128010; } @@ -41,8 +37,7 @@ __weak void mb_pirq_setup(void) { } -#define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0) - +/* The romstage entry point for this platform is not mainboard-specific, hence the name. */ void mainboard_romstage_entry(void) { u8 spd_addrmap[4] = {}; @@ -51,11 +46,9 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* Do some early chipset init, necessary for RAM init to work */ i82801gx_early_init(); - pineview_early_initialization(); + pineview_early_init(); post_code(0x30); @@ -64,7 +57,7 @@ void mainboard_romstage_entry(void) if (s3resume) { boot_path = BOOT_PATH_RESUME; } else { - if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */ + if (MCHBAR32(PMSTS) & (1 << 8)) /* HOT RESET */ boot_path = BOOT_PATH_RESET; else boot_path = BOOT_PATH_NORMAL; From d16187ed2a6bf23022119c735d24c14d6fafae4b Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 27 Nov 2019 16:02:47 +0530 Subject: [PATCH 0446/1463] soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command Below changes are done: 1. Allow execution of HMRFPO_ENABLE command if CSE meets below prerequisites: - Current operation mode(COM) is Normal and Curret working state(CWS) is Normal. -(or) COM is Soft Temp Disable and CWS is Normal if ME's Firmware SKU is Custom. 2. Check response status. 3. Add documentation for send_hmrfpo_enable_msg(). 4. Rename padding field of hmrfpo_enable_resp to reserved. The HMRFPO (Host ME Region Flash Protection Override) mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perform updates to it. This command is only valid before EOP(End of Post). For Custom SKU, follow below procedure to place CSE in HMRFPO mode: 1. Ensure CSE boots from BP1. When CSE boots from BP1, it will have opmode Temp Disable Mode. 2. Send HMRFPO_ENABLE command to CSE. Then, CSE enters HMRFPO mode. CSE Firmware Custom SKU Image Layout: = [RO] + [RW + DATA PART] = [BP1] + [BP2 + DATA PART] Here, BP1 will have reduced functionality of BP2, and the BP1 will be CSE's RO partition and [BP2 + DATA PART] together will represent CSE's RW partition. CSE can boot from either BP1(RO) or BP2(RW). CSE Image Layout in Consumer SKU: BP2 + BP3 + DATA PART TEST=Verfied on hatch board. Change-Id: I7c87998fa105947e5ba4638a8e68625e46703448 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/37283 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/block/cse/cse.c | 48 +++++++++++++------ .../common/block/include/intelblocks/cse.h | 16 ++++++- 2 files changed, 47 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c9712dbb2c..041656a498 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -650,6 +650,26 @@ int cse_request_global_reset(enum rst_req_type rst_type) return status; } +static bool cse_is_hmrfpo_enable_allowed(void) +{ + /* + * Allow sending HMRFPO ENABLE command only if: + * - CSE's current working state is Normal and current operation mode is Normal + * - (or) cse's current working state is normal and current operation mode is + * Soft Temp Disable if CSE's Firmware SKU is Custom + */ + if (!cse_is_hfs1_cws_normal()) + return false; + + if (cse_is_hfs1_com_normal()) + return true; + + if (cse_is_hfs3_fw_sku_custom() && cse_is_hfs1_com_soft_temp_disable()) + return true; + + return false; +} + /* Sends HMRFPO Enable command to CSE */ int cse_hmrfpo_enable(void) { @@ -675,36 +695,34 @@ int cse_hmrfpo_enable(void) /* Length of factory data area, not relevant for client SKUs */ uint32_t fct_limit; uint8_t status; - uint8_t padding[3]; + uint8_t reserved[3]; } __packed; struct hmrfpo_enable_resp resp; size_t resp_size = sizeof(struct hmrfpo_enable_resp); printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); - /* - * This command can be run only if: - * - Working state is normal and - * - Operation mode is normal or temporary disable mode. - */ - if (!cse_is_hfs1_cws_normal() || - (!cse_is_hfs1_com_normal() && !cse_is_hfs1_com_soft_temp_disable())) { - printk(BIOS_ERR, "HECI: ME not in required Mode\n"); - goto failed; + + if (!cse_is_hmrfpo_enable_allowed()) { + printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); + return 0; } if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), &resp, &resp_size)) - goto failed; + return 0; if (resp.hdr.result) { printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); - goto failed; + return 0; } - return 1; -failed: - return 0; + if (resp.status) { + printk(BIOS_ERR, "HECI: HMRFPO_Enable Failed (resp status: %d)\n", resp.status); + return 0; + } + + return 1; } /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 93d1ce1d04..595c7d8d6b 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -136,8 +136,20 @@ enum rst_req_type { int cse_request_global_reset(enum rst_req_type rst_type); /* - * Send HMRFPO_ENABLE command. - * returns 0 on failure and 1 on success. + * Sends HMRFPO_ENABLE command. + * HMRFPO - Host ME Region Flash Protection Override. + * For CSE Firmware SKU Custom, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode: + * 1. Ensure CSE boots from BP1(RO). + * - Send set_next_boot_partition(BP1) + * - Issue CSE Only Reset + * 2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required. + * + * The HMRFPO mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks + * the CSE region to perform updates to it. + * This command is only valid before EOP. + * + * Returns 0 on failure to send HECI command and to enable HMRFPO mode, and 1 on success. + * */ int cse_hmrfpo_enable(void); From 59c7cb7d372ee1a90972de9de933af880fd8a042 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Fri, 7 Feb 2020 11:59:30 +0530 Subject: [PATCH 0447/1463] soc/intel/common: Check prerequisites for GLOBAL_RESET command Check prerequisites before sending GLOBAL RESET command to CSE. TEST=Verified on hatch. Change-Id: Ia583e4033f15ec20e942202fa78e7884cf370ce4 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/38800 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/block/cse/cse.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 041656a498..648ec6a6f1 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -608,6 +608,28 @@ uint32_t me_read_config32(int offset) return pci_read_config32(PCH_DEV_CSE, offset); } +static bool cse_is_global_reset_allowed(void) +{ + /* + * Allow sending GLOBAL_RESET command only if: + * - CSE's current working state is Normal and current operation mode is Normal. + * - (or) CSE's current working state is normal and current operation mode can + * be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is + * Custom. + */ + if (!cse_is_hfs1_cws_normal()) + return false; + + if (cse_is_hfs1_com_normal()) + return true; + + if (cse_is_hfs3_fw_sku_custom()) { + if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg()) + return true; + } + return false; +} + /* * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/CSE_RESET_ONLY. */ @@ -631,11 +653,17 @@ int cse_request_global_reset(enum rst_req_type rst_type) size_t reply_size; printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); + if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) { printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); return 0; } + if (!cse_is_global_reset_allowed()) { + printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); + return 0; + } + heci_reset(); reply_size = sizeof(reply); From 083e4ef1effd87b9cab70588186f389219e1037d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 25 Dec 2018 22:22:34 -0600 Subject: [PATCH 0448/1463] drivers/smmstore: default to selected for Tianocore payload Now that SMMSTORE is implemented across all platforms that Tianocore supports, default to selected so that NVRAM functions and Tianocore setting saved as users expect. Change-Id: I067e5faee73cba585a1123215ed2d80e3eaa7877 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39570 Tested-by: build bot (Jenkins) Reviewed-by: Benjamin Doron Reviewed-by: Angel Pons --- src/drivers/smmstore/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 333f5e1d7c..bb90809553 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -13,8 +13,8 @@ config SMMSTORE bool "Support for flash based, SMM mediated data store" - default n depends on BOOT_DEVICE_SUPPORTS_WRITES + default y if PAYLOAD_TIANOCORE select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP config SMMSTORE_IN_CBFS From 03abf8dbd16fa10a513c8d6dc831315b9cc73144 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 14 Mar 2020 13:19:14 +0530 Subject: [PATCH 0449/1463] soc/intel/Kconfig: Avoid specifying dedicated chipset name This patch ensures all IA chipsets and common Kconfig files are getting included without specifying dedicated chipset names. TEST=Able to compile CML and TGL RVP. Change-Id: Ic2d8a8ac1c4acfabd4ded1bfd4ff359e820e174b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39530 Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/soc/intel/Kconfig | 14 ++------------ src/soc/intel/common/{Kconfig => Kconfig.common} | 0 2 files changed, 2 insertions(+), 12 deletions(-) rename src/soc/intel/common/{Kconfig => Kconfig.common} (100%) diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 47efc4d18f..d5190683ae 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -1,18 +1,8 @@ # Load all chipsets -source "src/soc/intel/apollolake/Kconfig" -source "src/soc/intel/baytrail/Kconfig" -source "src/soc/intel/braswell/Kconfig" -source "src/soc/intel/broadwell/Kconfig" -source "src/soc/intel/cannonlake/Kconfig" -source "src/soc/intel/denverton_ns/Kconfig" -source "src/soc/intel/quark/Kconfig" -source "src/soc/intel/skylake/Kconfig" -source "src/soc/intel/icelake/Kconfig" -source "src/soc/intel/tigerlake/Kconfig" -source "src/soc/intel/xeon_sp/Kconfig" +source "src/soc/intel/*/Kconfig" # Load common config -source "src/soc/intel/common/Kconfig" +source "src/soc/intel/common/Kconfig.common" config INTEL_HAS_TOP_SWAP bool diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig.common similarity index 100% rename from src/soc/intel/common/Kconfig rename to src/soc/intel/common/Kconfig.common From 93b0c7cfc632e7b57f1f4915886bf53397a12f25 Mon Sep 17 00:00:00 2001 From: Tommie Date: Fri, 13 Mar 2020 16:37:21 +0800 Subject: [PATCH 0450/1463] mb/google/kahlee/nuwani: support new Elan touch panel for Nuwani This is new Elan touch screen IC, which includes touch panel and USI pen. BUG=b:151514167 TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin Change-Id: I98801b8c31812637f71d7eaaa0f12b47901dc47a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39494 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../google/kahlee/variants/nuwani/devicetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index 6c953b1af4..689e6042d7 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -155,6 +155,19 @@ chip soc/amd/stoneyridge end end device mmio 0xfedc5000 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" From 2677e2dbf6a2733de6a7d6c4ff0975d8a2650e13 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 14 Mar 2020 16:22:01 -0500 Subject: [PATCH 0451/1463] ec/51nb: add support for NPCE985LA0DX EC Add support for the NPCE985LA0DX, as used on the 51NB X210 (to be added in a follow-on commit, and from which this was extracted). Original source: https://review.coreboot.org/c/coreboot/+/32531/37 Change-Id: I5798fad7fd18083cde1aa647fd91ca9c5ce963b7 Signed-off-by: Matt DeVillier Signed-off-by: Matthew Garrett Reviewed-on: https://review.coreboot.org/c/coreboot/+/39567 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/ec/51nb/npce985la0dx/Kconfig | 28 +++++++++++++++++++++++++ src/ec/51nb/npce985la0dx/Makefile.inc | 23 ++++++++++++++++++++ src/ec/51nb/npce985la0dx/npce985la0dx.c | 23 ++++++++++++++++++++ 3 files changed, 74 insertions(+) create mode 100644 src/ec/51nb/npce985la0dx/Kconfig create mode 100644 src/ec/51nb/npce985la0dx/Makefile.inc create mode 100644 src/ec/51nb/npce985la0dx/npce985la0dx.c diff --git a/src/ec/51nb/npce985la0dx/Kconfig b/src/ec/51nb/npce985la0dx/Kconfig new file mode 100644 index 0000000000..caa5624ab9 --- /dev/null +++ b/src/ec/51nb/npce985la0dx/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. + +config EC_51NB_NPCE985LA0DX + bool + default n + help + Support for the 51NB NPCE985LA0DX EC + +if EC_51NB_NPCE985LA0DX + +comment "Please select the following otherwise your laptop cannot be powered on." + +config EC_51NB_NPCE985LA0DX_FIRMWARE + bool "Add firmware image for 51NB NPCE985LA0DX EC" + depends on EC_51NB_NPCE985LA0DX + default n + help + Select this option to add the firmware blob for the 51NB EC. + You need this blob to power on your machine. + +config EC_51NB_NPCE985LA0DX_FW + string "51NB EC firmware path" + depends on EC_51NB_NPCE985LA0DX_FIRMWARE + default "ec.bin" + help + The path and filename of the file to use as 51NB firmware. +endif diff --git a/src/ec/51nb/npce985la0dx/Makefile.inc b/src/ec/51nb/npce985la0dx/Makefile.inc new file mode 100644 index 0000000000..810b324b8a --- /dev/null +++ b/src/ec/51nb/npce985la0dx/Makefile.inc @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. + +ifeq ($(CONFIG_EC_51NB_NPCE985LA0DX),y) + +files_added:: +ifeq ($(CONFIG_EC_51NB_NPCE985LA0DX_FIRMWARE),y) + $(CBFSTOOL) $(obj)/coreboot.rom write -r EC -f $(CONFIG_EC_51NB_NPCE985LA0DX_FW) --fill-upward +endif + +build_complete:: +ifeq ($(CONFIG_EC_51NB_NPCE985LA0DX_FIRMWARE),) + printf "\n** WARNING **\n" + printf "You haven't added the firmware blobs for 51NB EC.\n" + printf "You may be unable to power on your laptop without these blobs.\n" + printf "Please select the following option to add them:\n\n" + printf " Chipset --->\n" + printf " [*] Add firmware images for 51NB EC\n\n" +endif + +ramstage-y += npce985la0dx.c + +endif diff --git a/src/ec/51nb/npce985la0dx/npce985la0dx.c b/src/ec/51nb/npce985la0dx/npce985la0dx.c new file mode 100644 index 0000000000..0e0fcd1b90 --- /dev/null +++ b/src/ec/51nb/npce985la0dx/npce985la0dx.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include + +/* + * This embedded controller looks awfully like a Super I/O chip. LDNs 5 and 6 + * need to be enabled to turn on the keyboard and mouse controller, and LDN + * 0x11 needs to be enabled to turn on ACPI embedded controller functionality. + */ +static struct pnp_info dev_infos[] = { + { NULL, 0x05 }, { NULL, 0x06 }, { NULL, 0x11 } +}; + +static void ec_51nb_npce985la0dx_ops_enable(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(dev_infos), dev_infos); +} + +struct chip_operations ec_51nb_npce985la0dx_ops = { + CHIP_NAME("51NB EC") + .enable_dev = ec_51nb_npce985la0dx_ops_enable, +}; From 2f62a352ea3f62e58c166c430d37ec2d2565eeca Mon Sep 17 00:00:00 2001 From: Matthew Garrett Date: Tue, 24 Jul 2018 14:06:39 -0700 Subject: [PATCH 0452/1463] mb/51nb: Add support for the 51nb X210 The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes: * EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different All hardware appears to work as expected, although the SD reader is untested. Signed-off-by: Matthew Garrett Signed-off-by: Matt DeVillier Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Held --- Documentation/mainboard/51nb/x210.jpg | Bin 0 -> 48701 bytes Documentation/mainboard/51nb/x210.md | 45 +++++ Documentation/mainboard/index.md | 4 + src/mainboard/51nb/Kconfig | 19 +++ src/mainboard/51nb/Kconfig.name | 2 + src/mainboard/51nb/x210/Kconfig | 53 ++++++ src/mainboard/51nb/x210/Kconfig.name | 2 + src/mainboard/51nb/x210/Makefile.inc | 4 + src/mainboard/51nb/x210/acpi/battery.asl | 93 +++++++++++ src/mainboard/51nb/x210/acpi/ec.asl | 115 +++++++++++++ src/mainboard/51nb/x210/acpi/graphics.asl | 60 +++++++ src/mainboard/51nb/x210/acpi/mainboard.asl | 42 +++++ src/mainboard/51nb/x210/acpi/platform.asl | 37 +++++ src/mainboard/51nb/x210/acpi/superio.asl | 4 + src/mainboard/51nb/x210/board.fmd | 15 ++ src/mainboard/51nb/x210/board_info.txt | 8 + src/mainboard/51nb/x210/devicetree.cb | 167 +++++++++++++++++++ src/mainboard/51nb/x210/dsdt.asl | 34 ++++ src/mainboard/51nb/x210/gpio.h | 182 +++++++++++++++++++++ src/mainboard/51nb/x210/hda_verb.c | 40 +++++ src/mainboard/51nb/x210/mainboard.c | 22 +++ src/mainboard/51nb/x210/romstage.c | 45 +++++ 22 files changed, 993 insertions(+) create mode 100644 Documentation/mainboard/51nb/x210.jpg create mode 100644 Documentation/mainboard/51nb/x210.md create mode 100644 src/mainboard/51nb/Kconfig create mode 100644 src/mainboard/51nb/Kconfig.name create mode 100644 src/mainboard/51nb/x210/Kconfig create mode 100644 src/mainboard/51nb/x210/Kconfig.name create mode 100644 src/mainboard/51nb/x210/Makefile.inc create mode 100644 src/mainboard/51nb/x210/acpi/battery.asl create mode 100644 src/mainboard/51nb/x210/acpi/ec.asl create mode 100644 src/mainboard/51nb/x210/acpi/graphics.asl create mode 100644 src/mainboard/51nb/x210/acpi/mainboard.asl create mode 100644 src/mainboard/51nb/x210/acpi/platform.asl create mode 100644 src/mainboard/51nb/x210/acpi/superio.asl create mode 100644 src/mainboard/51nb/x210/board.fmd create mode 100644 src/mainboard/51nb/x210/board_info.txt create mode 100644 src/mainboard/51nb/x210/devicetree.cb create mode 100644 src/mainboard/51nb/x210/dsdt.asl create mode 100644 src/mainboard/51nb/x210/gpio.h create mode 100644 src/mainboard/51nb/x210/hda_verb.c create mode 100644 src/mainboard/51nb/x210/mainboard.c create mode 100644 src/mainboard/51nb/x210/romstage.c diff --git a/Documentation/mainboard/51nb/x210.jpg b/Documentation/mainboard/51nb/x210.jpg new file mode 100644 index 0000000000000000000000000000000000000000..66fb7e3a8eabb1d874f58751a3db0d078e1b74a0 GIT binary patch literal 48701 zcmb4}Q*>t0vbMk2$rszUZQEAI>Dac-4m!4Nr(@f;opkKe`;2|YfBo00yIOOOc~NVP z`MmXhuYT_WfHD%&5&#eo0089Q1NhzmhyuVsLI0Eg0{mY>Ktn))gG0bVK|w;p!@|SE z!NS2IAff;f5Rnn#;D8uFWK=YCbaZ$mOe_pEEEF_!wEt`Z0`_kWI0Os?1PmGi90J<^ zcYOB)kf8xjAW~o;$N*4e5HMtr??C`Q0Pyc*Apbeh5prF6k0q|h|%0MvSzm+2O5iZ+FQ~%daw(HI$^-pMBZ_7})qb^+xA@sUT{2`W>0Ku*UA~^e z{6^KY$_Ul$!^PsOwlcNt=Qp#Uub0t^*3NMmw@ADqplwP7U12o2|2S*z)%-(yo(f4? zQLH0pS3M;pE4+Rl(pFmh#)$WFbeM$u<4KAG?X(O;IX_tkp@~AB-`ylX{W3U?8980g zcn8J`8c70p&Dy~PYD=$JVPlI|gLY3-#L4qwq`#`GH7mJe6cddPpTr)NW4xeM!N)_& zgu#Dh>uaDGZ~L4%?bGP`NkKs_J~O(9ja+X<9_wr4OM&a9By!O9iO#I4D8i_{AVW;t zBKP;JB5dW7ehQ`HLlNlcJ%; z?Qg(>z@Oj1&)L_SAJu@xe(8ikX!I3P1$~iIPAhV*xqUc<#c2ys7R*OCWT_!$_&m#x z3xP@7=hin9uaxtBE}7`cb)O6QT?F#7N<$OIF3vM}1Y+OGhrcI1bx+K?S-;J_1`|0{ zwG&VL!Y3C-_ho~)aF_Mr1c1Go*C8jQ9rD%=O|HU4TdQc7J=m}!L&X`Ibd`|VnBXmp zbG)CYNftTT+m#p0sljRT-l&Nua)5!`Kl%yicSbuPJMimdv!7%si-kWe)-97F25YS)bMWnyX3^UFL+Jcq=zB za?s+=RoLpYd!01ODM;N_(Btyhaoj$htO{1hz?T1X;{ij>8(<%Q66#tT*hs3*EN_0j z4(luOg7ZEsZ+gA4wrph^tFO)yuZ&ZsKth@OIb_4W0RQyiQG>>jaS7?33|n?v@(q}J zx(U&F-j2Sp%vF`wwWu??wy)kKfebjdcL|V#9NpcLRgQG6gnx=tD3=7=9I*vdZ)#AI zFKkk6MHI;vpTu~517=DzO{rucLvgG?XG5G(>(_#JoO4(`Ax#L>ONH(<4GM|ZrF*FJ(eaj1)0Q}%d$tA!X(4T5I0$||bEZje_l;(~+6 z&$h;0owccET7HA~8^D*_El&TwGO<0fG%&!RHAT+d`d&?6KKu38+zJS2n6BKP9+;ip6^2*+K{i7pX*x-q#T$3uro(`HP{>2UKXqj98s7rB*z zGwxh<0fHsnzp>~JTaBt<_M&SS1eK{j|8CI%TPiNvC2E;_=6%DlQU!-YBtSbe{j0du z16Ia2&XV>~o4Y)Is#cuvrl0>dKKy~?He4l;qDIRcJnelGCVcu++LBgkosgYm?KSAR z_s`TS$!4$mQR_kt>k^f{Gd2HMwgk%!s!Q&#bHoOhnw7S&W&RrP#TnRNy_#-5KmEw8 zM0^^8qURz#>NQloe4c+#POz?E80C!!Et?g)u*%UHg1_cVyp;}Qv4J8&seL_O^;LY@O<8cGZ=xsbCE~R@v=L;Ys=U8V|%>U_X+*o66H_cclzZ1!WjOI zF60XpP!-ir)cmHEcpWhEijTF-W+G}PWo*6zcao48HnA~KKdZg4Vb4J@aJ+e~tfp^O zz-t%pr1|?{1xor}!GSGSY(}q2`H<7`&uQwZAgkc!VhTLC)H++vkgTm;p#ito2TfJ1 zuXond`KD;(fgb=kFa(6quzVHlb;^HSecP(`+WbLJ3`bFhO@3S*S&f47wsI0#d`+aJm?=71&41fBI4~ zs;LKdj&)Kw#`ROfPYHxAja5G`SL)gQVQlt-ZZ-}H3ZQngAFm~^x?-s^$}3p$mp2Ua zsGHXd+c4GmAsFW8-%!fB;(4{S6`+mixu-FHPqSS>YobYSf9|PrU0qWhb8XV!C)oxw zU;p}*lu4)?>qR%sKd~U-&pz4P56~oB@RRsD?!@P-Rpytt#ApKwDAO(@=z};?Xh=q{ zdF2jN!0rx2!=d1dEALM|`EG0#Z|LI%w!xSc2y=>a3~o&j7isF-I3I+lTa&$N=1XX- zh}iE!9xTL0#l7IsS(_6TZY-;?h%wzvJUlm3PO2F@ucS;qXO(Wpya zcHD7^9j;o@s7u}Q4GjMxP?-V3LdlpL7YBpe&sxh0<4c^C8t}JjB+=sB_@q(5g zJ@Uqx;OJeqFc2MV-nginp_1_?uS6XumsfmPfiHt!)tbwgw_YkgKMKaAoF6&)_X|or zMj0TD`ppTHR;045oWG?B|KTM9C~`3e^CRAPDK?(rZeX`cI7+C0!7$_gJha$8KU^JE z3Z&mPM7-2gRZ!?5Q#YDK?6W#*f=xwIr)J7x1cFOcu5orcm=x?y{*PwEpp z_M}f$dXg>{KPxX#9g->bhBXjtrdC0)`dj1AgrI@)c2CnKrAj00So9ftr7#Q5thP(Z ze2prvuI;I^^b{K?{E4B5l5nwu^9*FX=kce?knfRf`=)RCG(@!KX{$mBJ!HocT?8TD zIAvSz2_Y`Oi5j%0PNm+b!27mji!gsZ^+6p;d7lfEueg+s&+yIiV&L#nvl=NKhKK6o zZ%gN1le}FV+8jPt9BMA8`=d+Dye*4%g77Bi&b+QGrc~iUUMw1W#)m?ql$?U8#sF9! z&r`z}L3S?21T&1kzPO8PH{Lfk4uV)Io3xw=*sYK)~e$~q`>lC~`Lr~=~5 zlnJzEV(C7pswFmppFfY@7i-ra8@3WcD#|~adF?|^F;W@t@#YU9?*&641MD&KE+lp|4d`zRYLJn zR3ay7l%$(#HhiV~$rmgArM_~MTEHBlh@g};I89tSM*%-l2|p(C&c7*iZPf>bDn>c> z87JBhEgkvo39bIyz;KmOqML9C{}i_ zxKT>}(zlxT;_q4)_tSMGBp;az(bO!Y{UN6+_O?0ouqMzx!*MKwHS|aFR0`Eep=FDY z;9*#p7gaa;fXgPA;XL(AsGW9f%_|Aev9F!u`rLAl@#QhP4ZC|wt>8Xi=d$G zM$ySP;D_;X)vc3a@mu)H&tvf$ljXz5?9aQ*$it84?gz88655s&$x_(J7XMYx*^eg6 z-HN_&!sTLyi4$3=tF6C#C(eJ{NtzzOJ;&>V!rm5ZtkEhbS)06g^$9}10X$tz6v*Qo zcC{$lA>=jFNcPsBFwA1}V>&m3XsX^9lrmjU%NzdiJ0r+9|Cose_z$T-{ulQCi&g&+ z3LJopf(n5~3?v~%XJ%m~V-qHV{6|pG|K0$B0NXYpT2KS&PH)R!9+gI$)p_$A8@DA!z7KN8C}^#rc!J!uk5#>UDv4DdOGK)N7@DGv0`Mqn>$<5dRqdi1G5xGAXgdzMjgL z#m@N_gpL&9aCSQTO}N4+>pBI^um>dFdjR9DFwwk)btjbW2m6&%^~i+ea|f5f;xN1R z_*CHV;MeHrXgonAS7r8~9j$Q5=Tg(S|N4U*OtNNeJ}7T&MaZB;Sa!>5zFq@9M??-C zmOB(~+rv+Ll08hj2%GVHuT^vlp_JW_ET@~z6^@ahW^Ba)!W-R>xwL0^XAMGx(b30< zSyTR&CrHQQNM}M#v}x;E?h-nABa6o&RZb%<^eXHcE&honGV?nd-FodZ1Fw&pom?e9 zUzuTF`Im`ni-4Rc+j6ZjTSnW)9M&FOg_#sh`uayP32af?#y+x_sndh{L;;g|);KtN z$l=Am8Zu~+oe&Z9&lLq+kr#kQn~deo1dQFNJ<#>8=-`%YR67}?H}`Bg*W$zs{~<;v z>vg>)mY__to4TV+Ml`J79R(jNR9pChhtl9&#Ew|X;1LOZ8%(UVRqV0qjY)Q-Kjx5< z_vvx5I!$49i=azAr(OCttd_#c=l#yCs&M0QN~P|%@huHMPZmC=(|PuSWl@3SaTT(? z6!7gKO1ZA;NJFHzD)t2ILW)JLtdl$r8c0UTm6VQTo+`h-V|(COFcDgC@U z^>+a2T#GGMeU_?^Z$KEo3V7t)U0K1siEr9+%xAjoABXf2NNHUFDOIJQ& z8|Y_4jw^Af0#8r`z-PEBAI4wvXrz^u=xJBzOw00;3);0L3k9^)HW3v>W0rwnFwT@+ ztsX^yW1faQ0b*VqcSQ3tYaC{ zYDzik0#VwOVO_NbWD`HhN%oL^UT+>OlvNvjjkVf=WJs8nR2W9>>@}^?A441p?rT4- z&JzAsCf*K|>Ld#-JnTl~q+#>ZQ3|9s5L;H-xHX=L!H6}OSgr^ibV+HV6eW=* zsqI9^nOzY7)71?jo+k=k@?@I@t3gVkSE6YtUF~Lqtv!OWz@oDMLz%9AHhO&qd)dF* zfg4?P3q7J`@>DQY7vWC5E8%60e^sdOt|eGzA9$xyg~lJZ`Bw=g%0{l1*wmqk>2FjF zeydMQf^4j-JF5l9k10)i;jm~-!=Wp1aJbsjZ$O3B_;da>!`6WcV9C`G9Xjd>R0znh zV^U<*Lby?0Ba_;(8;{)7JyFN>J!BgHlwlQ+_=TU%eoPfH{*cwvQm zutl6ezIpF1Ix^bivhAwSrbOz-qrpEFl2OSL*kbbyFd;?d*^u(#^GQvVqYWUFx37T_ zmkeBG9G<ke+NY1DS zZyW4rkUfXH=Dq#R@`9=`B*M!AZu3z%jTC9ZUT3PKW8-|kAMK_oYx5`l!n%dUWz$e> zo98?y?<_>_Q;x61XLt))kOsJ{8E$0?(Ml;j`hGwPhFx?(PwSlhL)2H^yx+l&QbJp; zF$J5PUOqG?sW7%U@fjh6-l0Rt8s|OdEg?@{i|zIsK%VSI zugc%F;f9Q?(B@~v40R~1%w;!YISRX)7PVSRZS#{U6D!I-JOotPS zcfWA8Xa3rX?UpQqKMg+A8)kBiWp(r26`07|z}9b67=}_HHCPyjFH@L6_fVi>F-sW} z$~}KWFeaN)Ayqh0`j|>XJXAVBCs5YlaDE6VGx23Mv?77EWiE3%Lre~0t=&Q*D z8S~j!%f0Zg&nhnE1#x;(&@(YU)Y?mH*!1ld$KYtOZHlt<$Jf-xa(D6Aj$=AkSbrBu zB4i8A{3V@|-dsdlwmkjyNBnJV9b6Jnb2S=R z2hvqd0d&$iUESMr>7}B^*jOmfkXw&j?_xw|o8=+8FI&)> zB&Tr$5(;`Zty~d2M1B^(SK|efl5WT(eZuZvcGzyP;g9UT4PY5qV0} zhnEbc|(d z)Z`R~LaZhGNW&FJU4$*+gb~C<&NcYKuZz2T%UHoZjciSxldSvDnz?r^z4m-7ls_gL z=A%s&eAY`eaX})uh{opHo+X8Fk|28N?APnN>XLSUextipy^nRO3Ioa+=5s;RC9b?U1W6huHlqxY>aP0>(kBa71Rn)4=mDLfLOa`p2*UfAM zN`~q6r5%_TlfoBCX>qY^=YN)*AyHK|Y^mxmK5i)8m%BXnK>aG@R1iht%#p^p);PqK z#O-d&4@HVskPf(pmVl3;dzID{N(;5L4anJ#Cs=6uTzb;_y~=(hR$kQwqMss~zLHGU z$JhFq?Htlp$$&R^W>JgZ&{(FSh!8eL6KQEaA#TQSs0)8Ut~#kPTIC80;;LijRt5I? z4Ty+kF+p-Me7`vROmL|y>_T;A!+G_!y|LbeaG`c)V~-Vz z$Nn*swQZGRq~2x(dM-Hn&gBSrm#bi>l3F|HE|Vjn-U- zGr{5K-QDfLl1qFqjr*KBTT~icWlE(YKF^-16=_)OC-(lq^y;vf<&Q{hNHsD9S!Ers zu&QPaw3ygAqn2m*k%(B<7Pr+{icL!Yn#QD)IYqYPGrG9y5viJC*0QcfbK5O^(&LhS zma5NKY`t}Chm}FwtuAMen4iqgo++WRyNEw(Wm*e$F!=A$#M1^eWwK*>0Co015s^A?Vh?j#8nNB&s|F4;Ag zlSpyeMW;;3rY2RI6&DE&AkTh^ENq!O#zl6fYu~Tuzi{1?mAdH^G@d3?;~7uv@<%f1 zvon(Hds?`5Ot^ef?p)@lQzjJ7T2m$qH`$dAA`-Dok(JWD0c{q3mid~gFcd>ArVs^e zT^SvBnD8T(^NCURdphi|Ek_9R>6@YsE1No)OO~3JFd;Q&P#P(+nJC1gIR)8prI`;6 z(C}ww4MS0P765UpUl5>qhR!zTt5fNXl-CUlG_y$)Q+vFenOxD3aAQ-Pit_L3*)&twZh$7LlPfK2MDMwgrPdMz!wGpAWN;{L5yJXgwW- zJwxt20?`hw4p{;0n#11;S<-&+ zHBFwJm#fBvT?kIg)Xa0(+23F1+Uc@ntfot(l@3Unsh-7+6bdX-XHN=-=bH%3+%;Wl&eS;LE*;bZD7_Vb`8iQuW_%ESmNZmm^m1lG zsW;&Eq9R`MN^BAXKYWlMYC7w~36cb0i!NC26-{|=DHMYF(CRm0-e~MLxHc)VRLMW_ zQ!K%9Kp*XL$7@yxv8m(PVwu7H%I~F4TprbI6S%3!&OUZ)HgTdwf;@Kp1<$+<$gWYc zH45YAZD$PeHgl$pk3OjujuOAb#;{|_5nggVM4UMS*v<=W;Kc&cz-s6Rn&qw*nq%R& z5O$qv6DH~r-%DqS>+_vmY2B_HG8TZ_*(r~sA$LtCHG8FO{9F+`x{uUt-vD;G9ebCr zikx@f{Aaamx22wrN4p#o*!-qV2?kBoZT}{mLGQ@}93m@siPI4?By@jLL9mLF8k|rt z(m(|Q=L{_?m>U4PXrqTkSLhz5UlJMYX3iPak&YS|?xO3S<}ZFB5WVb+>3{k!I|mM< z^}*4ZNu!JmQ)8Jz--{M*XOk(n4N^uuO3>vuv$Bv}_I@A|c4(;TV~PxC@9mvP+e|c; z3Zf%pDdP1r4cp`ExTKs1uI#3rwipy_U<#qIeK`w(4hW(NFBP?jSlb40jhA@OKy?HQ z(Iw?AG5_xLB0VlwUC(R|N0dU{>Tzji+J@O0*2wX0+s)$yf$C&_t5Cq<;*&cs@kH0a zW68Jy4dRb0o>4@D;Yhi_$rH_$<$BhvvY(Ql(weadJIw6-R7-^9o-uiWKf*#O_u_&$ z@bD;9088_%thSE-0o|FNGn^BCncHa78blecUi2beLlqv_+v9Rl(W~pswq0 z!rzvOKY=ZlglS5@m5*d#%2^Fu#bd`7egu#+X%`yO69rXlxLm-d64KFB+JI+OhEr~Q3Qy-C9nB#se%aLySb`ww~P4xiaEr=t&w|wryL0 zoXK@XcRj~Z?QGr)0*{-Ldmr;a*m;}P0G0kNRZFh-I^Rkmvc0(VOd+437!o3a_6$62 zhT{$R!X`b&3(>{MkgP#@tPxzC{vZ+F{-uICuYmM7AaTc@d2hw2tyyj2P>$kn4$O6r zw-CIOx<5%tKYr4HzUtrWv$4C~j9vZsXIL-<%5>o>w|OqMJ$rkJ>P|5s*Bl1qK)paeXoS%{-QuDVHsCovBq?F+gIUP6 ztNal6T8?DX9$2DZ;8Ceulw;p-%K-!o9iHciateXkEvY|vz1M{3Szc7vgjn%tTYw77 zL0lz}*x~z|u6gSS$ExN(n_?v&x1>FXIN&9?dO<0|P-n6#2?Z%UKq!~W0rl7~{pBir zvWP0GxSUn3TRYWET{VOo6E!NA8C2l!pW;vP z0S8zVANKeO5vNo+t7g1^p=y+-2;Ro9^EQg|!FkZIJS}C>l=RyAqc?E<-q=fiwv~Uy z{X^KnId*z-T3dXYJ2xcGdYJ`qTvPKy$vl8b@lXf)C>ME$uOF()?>s5T|H@_6miU+< z5EpAb&N#Rtf-Hq=>x?RMh%{1I=WvWir$O1J&h1s|yfBc!l*r@$DilwNuH4Nx$l&9d+V|Xpk?=NyZuaEyRpFP6=Q;3pzx$n z01sKHv)IZsg96=}%gq?bD9X2~@RkiU%AVcLo~rmm{~jw9Q2yY|ctl?XJLQ z_5cA~=la2j%O_~jQ~h9@?BkMBW>u^2+LE}6P9JwNzT^5E*Zv&>#P_!n+(+L`-?YP@C=p{g(cf^svgWq~VCt4va;`+6Rwx!4q*@Ps4+auC_to9qHq$UyIehQ=}kjLY)aJwGj_fA`**M zKQ6A{KCNWcUjctgz<1csmResy!h+dL!NZ*`U+3|&NK)kot!|?9>=MhLr1oY!jhI`} z=SykE`@v-*&So&Dt5nl9hYl4eCO$BjkJy6;%tmLy=Q>W`FCfM1!~qKr9q&2(luT1n z!(n!YtSE#teW!5Izu%)Sj#;}t;i<0NaV~-2hyT=tGKxnNy6Xy zP06I`D&d@BJG`w@hJtPF{Hr9hyn7@uO%&NPKEryWg2A^{548fSY1gQ5x2kcCY>)eC zz^=JXfB7(YTOFKZ6}c-?Ps3i79ds~wH>tO0iKTz6PEdMuwobD+6TIzOH*l@7pNnTHG4b}mBqfn*a zzR?RVg>v%R6aTqk#JfDYTU$i%G~zd^a)~8Zaw3{3h@hTqWxI*bv`lycAsuIyUxTtUa;c}P-J&dScV`BORff0YH z!}*Sk!S)Rh$zXJjc!H*?-zN<;IQP5wlzOXuB!=>ju-#ndD=yscS!6v9eOxuEsAR`7 z3o(2e+$H`a-j%ASne^dzcC{*njm#}+MZ+m&t(q~M?Oncjp;k76X`W_RvCQ{(f%Y3f zI!-`zDop)AonGorR|?zAp@iO)+w`*=rmE~J`CXjTOile*X%Jnt#?SZny8v|zC3rwU z^b9AX+Rl~GTLNM=OiqN&MxYYnUu%DOM#>5uefqt(kJ;5O^|HIu^)KWp_M;6=_LWQ% zQ2(bIS5X=HgDf+(T*QWOwT`jYevEwUT6IiJ8RYE#dxoyItK9el==1F7*0FI ztTamwid)d$Ch0A>Z_Es|7T4vXRdW?x^A0>@oV)U8vfV{|bv$gg$RfqJRsPQU<^^|U z36#aOMW{UuFF%{95-1oP0ZHNIN{)xpHLU+ou-t)Gfv=<8NRy)4l0}1~j864i0RmbEJ^JBr4S_ zhLvwchtYX2!_+8$UWhLrDhmz!VD{tu5KZ zg>6RW5VCoU>a(}}BA--TlVT{K=6xHph;1ox94l;8%kHjR#5ghw`;cy7p4o#*IC-VaQeImj<|JX3=!$dSGfWk943K zD7UoNx*eDvRJan^?eo3hXShjuOPJ7{VY!fcIB$&dpyp|hH5MTJ&474B47!G!Yf&Uu z$t(vPI<9dTaqPua&i?Y8Nw2j#_-81h$<#J&@=@*iOPQ(+a?9uaW5z4@GK~(sWZt>+ z8{m@?!Z%>o^chquyxfo(x0e-MaV_4@k@Ll_Gu1DBxn$L>Q-+^B@!ps&mKw_qLGL&= zn+F%L{hY{`ND;T`q${UvIn*w;SlGhHS%8{@w`~ZcU7@HYc4ZF5FixIvTK@Cm*eSHa zrVTe_kBxi5A&Xx9K4ee1^|};HK0ohNL2Z2{^`g(_>|~r_PUjAsh)=}GBAV^AwtZng zlEnn5^2ln8lOiqNUs%K!uwg5Kkf739x_v=R??Tvt|Fu6{-LcJqs!lZ{>B5tg-K|^sbLWn!CSKVM^m)Gp)3?sg{VzxbNlgqXv%jE7S8aE$+?f%b|9rp@jC#+p3x% zX~Fq`>Xn)U+_HpnGB2J$I){wlp+>0dO6Nr+QNfZW4J(6fA-KFJ~*;k)RNW{p9L*+*QoDebP_N zkv=f%nI?_08^__AL0d+RKn&b14>$-nDX^VOz12V=mQu?l(lUkCBw$Q2Av8y|Y)&}d z?M#=$lX8&1RVP(a&Ad**?o=ZzH~6Q>QU1qD@EH|M>_6S)c->g!bH6i2Fckz$NfS=)l`%?_)*I8j9R74sp$3M9%CP&3+Nqa zw{w=ZeNGv~r6kigEYGaqiA)cpQv9^&SqtONoI?e{F6e+5XgU-E|4T#&7-)qIqKrO} z7#qej*ytq$=yFYs*5I8ol;~A_p|3@>lRv~0?-7D~iZ5$Yv+_a3le`?imPyUEW^)UN zz5&<=LHFQN)}}B|{N{gxL!;ja^z#1hrD5%nzlN(UhN5%{Md**~v}owToih|dSVJLN z`~l^kicfQH1uDOKzJ{a#B+FgXP<2>}3SY?c(?Id_2+#5_+UQ~wIOmx`xe#@~HhG|% zL_$Hi%AklMlt%8;y~k6mY1By==03j)wm6kL5Ll``QAR<)>e5%agQn|qr5*PXpP@sH z35U-4Ec%M^iz&gd5I5zh6TNk(gr)kx4|3@K1NBV3%^Ny+J=YHs)%SU|$Ss zSE)1|Mz~1Oe0|{vk+Z6+6JT{*zX40=4e+*^_f&>d3N!(Brd9I^!%e?Jdtq64L(P8m zSVS=E*?&dsLeoc3COijGw>ZHl+{}feP6mPCf>n^->@yU@5e8B@bjd2C#XCj^>)B|& zGqvw8mxK_lMs*=#!s=RA1Rpr{nGP-}F$~*| zZnr6(ac6L3kwmMYm)#)`1;plZ>=@cN)HS36nLjEvuEa_QdAa9;0@(C zz8{{=1X_g!9lA9kK#(bdilC#+=!F-DCL&+U%9NX{FFQ`$9XTlw^#+^x7GWY6qLUPA z;|45Nemt?)jgu?TtC*FE_RK(-4XI)LecYsixkp}%rdslm*2`YQ@eCw0t+5VZEu(oz z#q8kB94`cHg=%|AB^P2M;~NY{k&q%sP+w>w*ieRDu%zGm22gzvpF+U(hB$M< z{~o>rza4%eMobpo3!Zo*=7a_%hUGevzwqvt*@he4jbPKEX#gk4Ca4~nBy#Ab&A0YlStNr-;;ATXC-aHs21 zxa5YeG@^7lM1X*CzC}zKY=o6_G~~D)qc|5tGD+}P)xV)41gnv5zWeq^8Yy>a?EUI# zZu{}`V8du!@=1FL422!DhA;7_*tHGm%!CC)QwROVWyGcB_F>?wZIdDvq&`-@iKyVv zMo@;c(nef$z*6g&--_hmZa$)3*`m`6yDZuScW_?RlWX zW@st{CVl9a55!^{Ae~1bA(DLrY6XL(ye&dhxZ}s8^U5G}q7=nZK%*7p0;Bh>uznq) z1;#OeuTV=Zv#-UE!`uo1tB8#aKYC-3!Lb;QT*ic72xi}UcKbO|TzR5Qem_r2;ed?w zH_uzQ0oF%}5l3po`WCBLqxw9eQJ#c0fnv%Tvy459?)!So^5H7e^`~-bi&0Z3&_sPrT0N`*dIma)fJ%hNo08&?@lKyIE=)NGOut%`-!??O}{87_1i2`yDfGB#V`GVYFwNYCcJfE zT{#tW_1m=@T~0DFbU+wwf>-iBI>cY5VBuyQN1<oPJb41dS;t^`f)ZiQMk^>2*eAAdWleSHL!@?GJKG(a1uwFN3 zu|Yj~rpDTR69|UIALhq{!dnCx3PJ5ZZXJZ$B(&6mBdc7LcL9Y;suC^m2D3qgIW~X- z#Kr$bhlMSU;r-p0nK`4MR!YiDOvZR)fNZI47G_~R4}&rV_E$V07z+#UD#sWw3f-N8 z%mxhyU<(op)dRVsSrr!vvjRp~YX*NT4myjNu-pWrK_o!!`=bP?lpbB@4FXYye?5}{ zI47-=A^EF^AgSgdl5&*H7hxH2>M)4#MPqnP;zfZ#^w3{78YrGX%6-5j=3Gj0eIt^V z5-c1<$R<+PyM!>&sVtZYHT3Ur?jY$h?Bk$5%<=#-QWaiB;5Pu3AEVuGu8;ay7!vFv zh}IoVnl!Dm-^z;5Gawe8vjs8{dbN}G3J;6F^|$`;pGLga_dvdGGlQ~NHVu5fzOel= z@zzZ=gfMA}6lj$$7a&~VLq2G1$xbMuFNy6eU=SeP0Y_IrKCagl8!DZ;0Vu5S;iXx`Fk)9e}C}>JUj8XsqO{iHB{6YMfmw zVgiDoTr5;)P-mG}gBf$>Tp%z@JPR67V6Y-^k^T5Y1lA8X@G1m4iXkJMo7;sEfmEyv z13M1?dq51Th?`{VZE}*r&~ecwGR%akvl|StrA_J7>KbQLEaV`Sg{TG2gj74wQF5L3 z4!Y~SBTO~__77fPuN}z9XMj4i`ltD3Le92vVK^@4PK2>?OL%V?PM>`Q*cM#EF&2Ea z=%P-f4k!Tm7a@RX+;tEZmNyLn?=yeCt}s}sw6K$pbQDZ$-p^R|ml7v7Fgp}P%f;}> z2-iX6M_teay#KG^fWlP$U<9$jNvhh(cBUGSMW&p)MA~?hAOstzmoNrz9xG&5`I1F;?e? zj6NX5!@*|H4IC)x&;WVF`4$-RisGv`XvCptO_^R@nh6YWAd~iXXNl0j&RQVhRF zB~bU0zJ_{?8kEpGQdyR%f$ofBXh|}MNKdH)_7<{eg^&kP`oUjC5=IdBI zgYacqMJNdXQtdQ=d(AyZ9Zc-t6tr3(j9(p9ULIe{JyS=JXYe)UdO-fOOgngGx$R|W zZ#1#EBlp(JSx_nW?D=H85d62~r7;wPp`6OLxFN6%Ps- z}nUjKL5KK|k3SYgr9S--t_z0}@4CG9JTfmoBK|gd@D4KZKr%5Q1OxA*kRyLL>_> z156Z~2qwjG4CFc<1ILSz45kf*=*=}zPkTijOpw9IO;LF=Ace4@BJV`QjOk=?Ko`;D z8vG=iyv-~^oe?v5G`s=|GQny7g#8uvQpTIm9}?n(4Hl|T=m+>JT_JKx{VZcMB27xe z3{GO29HNg$1cHe2BkghV8;=S%Q!hQHw}D{ov@-2O2+{4rtP+CTX$>Y=3@EpD_xcrD z3t>SfiO|r|?)-LZLnHE-9pHijl-|Qdpu2=>sVP^5V8Wehj7jY9j7qY2 zy@FNlgJE^dfO&!a5_UbO@kG-gebSI3C$b;_M`j_<&U2!Sqn}9ThXL~`Z@mQs^%f9> zVZ!0oHbs+mZKxm&@gIs2f>>w2)5<16Y?7fpxL}z*f`PDEJ*GMVXOOA&#|9w*`BN-j z=j3hE7I3hUsglLw&#{U?KccwVg7i*k*5iyzTi?D$jjlMsw$4e%D<5D zWc$?^q4obj z!xN-?IrgP2k(HKlf~SQLmzXGylm`Lu@-S-e(YYYZuv*r`0B{J&LL&Gsd%gI2phi#u zLWfTVGLSfd_Xri-2TFKRTEyFgOL)d3P`4bM)IJKP2mO={1c^aGf=2vMdx{StbB3*9 z$?795yN0|PfVM|x?__a=UmY*O4orw_5M^MaT)|pmz$$}a?ji8T^UX>ou;+N~2&M;u zi+PLNh*x33^x9s)Dosy&z^cR8N^KDqv6WvG1r* zDWL*cYA+<4*⪙ag6vOEyRrb{orlMH3I*ieMq$sl?4afd5Re0VCzZG5Gd~E*N}^u zq5x$WP~>y*7WNXF8n7zKwk#aBP9O*Pzw9Apv+??byJ3q(!lO zl=5J2|FQvW>O6reu_Mlay_ZxiRVq}LD8fyl0}$|NH@x-vGpac6G!UZkoC!^YSUOS#lXVCCI$0o)V6=&N+}len920xT-wyc)B4{V>;j%*0W26Ow-d5Yr9< z$deV66{xoz1SsKzB3Kb)0pBEX0Py{W@fat!D2juA(|R0>-aA#}CDMHacn<-8{Q|&v zpr)|qi=&$E{)zMfF#N|DP2OCR4-|^lWO76|ehEXNyhTC(1D8N(zcK;eT9@RZNM;MS z-eMg^@*{ck_l3;H@1Fzh{{XQM)&Q)VlQry=xIoymeZfvtAV7SOW5p6TIg4t@iKE9* zpiG%Ic$ptU09gM3W1Av?o&pdY8UBPhGe9id@QfxlrH38G5oRJrY`D3Z;K+`;xT*Q5 zT?lyte4^OC}0QUEUaxN$Yk~k6+rP31#yPG*aJVpq(Ee}8B7RaY)g2{%k*eZB{J|eJ% z3Ld&}by52KKA(|+&f{wcEr6kiLJl{)>3hz%yk}0# z5`;A+UgSMW=|O?TI|aZK1EQR24PK|_BDb8@NVrgZR7io0LRx4pP*{6@Ux*;M-M^SC zT$lD{5(r46%sc`6hcv!G3ThlcUjB|G0+~ySE5*$RTfq1|X=lU2XSq`?F>&l5C-0FcQC#}fYlKp>Xl z6Garzes+xGJ3-4Z4_0sk)}XeClnPs*4Z@{bzp!Km#iD-aHu-KKykx~U`ki4LyI&a0r2IK z)#i6pg>B3wPACo{2xNevr5y%inNt-yL1=np4i69yLkDe)N0B6Q&VNzSBOJUzq39_W zgZGs3ZFo6sVzEq~JB8+w2TJY_;%FsQ^n9l+JzxpSWnm-j5HY?1Fi&umvX-8CVbCvScU~qaFy{ajge*z83M&zN`Sg=e8FsW0Kx4lvSO)M z1YuQ`^SCy!LV1)k510x_xFXGr364bx0tpu|F7MJ59jPgse833U-R1tmb3h{X?=HBe ztii(GA(8;X@yxK~Edl|L@*EyziRONMt40_}`vp`Na7dRM7;h7}!%zW<%K>rb3yA|W z|HJ?$5CH%J0s;X90|5a60RR91009vp05L&PVR38H2Z*vHdfFR#q*NoSFWl1#0*3VcPT+U;UTLICdBU6WE_{+=sZ@f_f z1T(qL1T)4Fujl^&S^a14Cb)Bz5;A+aZ-TOue*XZ0*);2J>yiviMefloeijRHW#7k&pE7$ww#*qU0StcYMZ>=?9iMoai7 z`|l@NZ4h5hmJyD~I0*o0=wlDd0B)5M=+KGMl4|}A&5M}ELQR9he1(N9>&e%7nzk_&P5q0qZshD zhG7$b81RoLwpCvPL>gEUJ=~n*-(l`cdzm%vwaZc+*PmdR~Pk4yQ)?aC!G1Rx?8(=k>Xo3)x2Rp?=3LqKU1Oe^FNJrZb z*?@jAG@#ckcDhaZn@W(~6=t`M}N@jN&1FydV6w zVNGcW_Xs>*M|=U34#fjK`Ni@XHLS@ujFD$|0BpLM+ayt3#o&TXCjn>gBneBC6w-(r zB$DD-zA{Hh1d=7adv6y|>@ae3Fidmc!pxM^(gi{KnGc|u2l0k!eAnu3}KU4`bB+- zX4ScrI&}X4Sp*iZ5FYV>_mJ%-DLm(L?9Buohu%2klEB?Vag*VGX(UIaUI##25P#S2 z7Mlf))BZ5zPz3xx?n2w)-I0{Mo|Yej4mkT%=_k^?vLmIvvTgxKChNI(@DXuD__eqb09>d((<7zpE%^RF;IdvMP1$!#Lg{} z5=Mf`GD=$#4S$(M_6G7(rD3jce{s`p)LNEtg6;%^QizBSubg^!0M%=Oh&=8X;zGa5tz%>B{3QkBOYh%W`F2r1|&9 zINXyQ=7gbz9bIBM8dEO*^^v#&97c=*r5wAOz)^BWfW_b?PirWj9@ud)tI&d*h|N5V zqf_+j))Bga`KSZFE$nB8@)t;y)DZnSo1uQlEF)gtYYecrSlFW!x z)2J|U(D})>umT)FJg#9qMHt}aFho+7J+dK4T{B&tdFLU*I1R$F+WFS-1}>16 z-TJN&4l^iM(+lS(Nd)kdb;^0iU%f>&s-S}!)ZIs6MbFL=vjI z+laIX+H!}7(bg=h-Vll~QvD`yB~h#(;v7Tgql!Pq0@Pu*4LVm-klPGVB}nYFag2u* zQMR&ZNdnV<)&Bs1t*gJAyhiO(xcj&yX=bUvQfSwwUS$r8T2zu62%?*`3{<6H| zZkbP1eXuCV6Aa%IfTTi&CPoO`8&(19Bx zbva3XKt)c@JaZTgLR=Lygz06;6jih#}HJTK2!(;3bfqr8Y_ zA>=7g|MvtS(fS9cm!wS6^@K(iwOd7NM$w?x2>3PB|g^NLT z@t$oE`_JbfzMJA2A}P{EVY{gG#mBryz8Y+0>;)s2k8IWFDz5KbhX~Wk3p($vF|832 z8c#miKOj~r;xZB8oax0eE$Tewr38@0Df+`w*%raE1J5vd;CUj%Mq`?Y`2PT|C#?i4 zt~v3Ol0X&~Pn&*+0d^FC3lV#D{$(wT0=f>IAJdy#U=$+*gveotU5}Phj2* zW=%IgZ-=v@d883lctfN2jwnT5kQYmya=Eo6`v-71CB8B zt#Ao;1;B5Nu|k3iBm^fy=9em0q9GZBo}5J2%=QcD`@pI9H~kn1AtXQ=$eEECORf-R zHhdT$RDo(ik8EW~#b*dnNJ!)v+^;3~BZC&>O(N|#VWr))qMl7PXalO_X`R?&5_RngY%nJJ%I=SJ9=1o>F z<|zjPFXI8V6`{3EY?bqQ57rgIWG#BK8&aOL*kfn}f?~N(r?wp(U`8OcQFLQ2gTO0M zg6n{C9>y+FtH=_wWh)c-!_>^A0R*#sZNeCNhnME(;|thR(pwYT(0O8Uz{3)Q(s$b7 z0!UHNsPR~zQfiNc=8EdTCv|JF;@-AU7lw#=0V4@BVEXkJ*I$O$2oQ^d-jw`{# z@}{^(Dd(&qU4sx{Xf-D@iqeK6BHrGn0Se`LHcfr@_y$OhX%_c>2VZ!T!D)vA!1!|r?HbLN@$9o6~~YpB3(Wr z@fJl1WuJ6UzCT47v}mvrdb+AIb^ieO;@9IFgEZDXF&S2yrlD^k>-5P0j+gy0XqE=V zK0Y$x-DrCUyjAR2MZ!96amrRM;MSyhEg6SXu5@4s-IivQ}DMw`Ha(D|0 zn@18&znphkk`@AHYGzZW@H_mOgAA2CJ~8CB1_a5JWxg`ZAhoS8h*vX(XdqU*4FUDZ z6QM2AW%B#wGmwoVI`Cz=+(2(0t!d5pqd=e@iuA^Og==aJTzii=-l#q+_2VGg3enm6 zGB-fsRXVW^#w$bq3^%Q{8%2!Q2{U&y$)Q9Sfzv%A3yB>aUs)8UwNzaBGM!QMQo#1hV5QyJdM9sKT zFVEHkfP{!&cj#uBkA^~Q2J3WT+o8Dmj44jkps0(keX>eZA`DAGOBwMwqqGrEnO(q$xolgD8Zl-)s1eLaEdU}ox(MLoR@n*dXG{cEREbCJ`XJ4G;S-i z!EQ)TFgx6Jc=fE4sSx6knh6q`eq#|YQt>(1AFMk|gy@F6gW8*u8TtwdC-xBQ4^Jlo%ml zIYUVr1(LgqeEQ?Ng+e4Z;o*0{2`nVkiL=N*SwzbV)=`e@XnIP1F&2+%;?=|l0hTJS zK^|DM(+$ZyFvc*$Nx606ellqOLr=1Pn@Vdyl0-hWQY+jF^3{XfDqidU)~sSj=?S7A2P|}NYAQzWwfi4Ua#jpJbT_RgPFxT zkNspHvrZ5PEmlI3(-60lPWKsAO_GI(uaCwgNK~>R>(?y9P`FwS97LIoAX+)REQH<| zEij?i&I$l@GJ0%GbmDWasPqk_zd3J&GctBwj-Gp-{T;)WiQIn@!;|&tn z*j~~2z$M6DBS8>0d5OOAGh|OFf$Am-Yc7Wm+p!rTfL!vpH8EM1O$i)+FDJ{K& z&QEbHq@=!(M_a+}T`v(k{{SNvg`|o!q9ei`;1;RUA=ZO_SO)4%K4f^B-V}RK2?W>H zGfKU0{K8Ow20}3=2~C%d-$^Rk23y_Fp3tYhMhnEMv_8bokj6>&-VJwbpy@N6^OM>_ z02$xRVlaGJk~bsx$&R{la->}+F=i@BRM4~I8=DBFK^sh&D2fs!6rvN-an3IP024XE zU40)-0uuZsFyZGcaJ!@6Z=V?&pp9v_so!QPMgXk7O7+``TI%D6tTh09c~Sbr0H)tN zKfQ8gmvVo4{`oQ$-}m?QW|;EIfhSmjhuT*TA+;5Iewa*Ys<)5t{myvXIqER7GLW?R z%`bY02fu%e0hnrdlYDE|GOMx}#!~Eveeg}fWTXq1bo}59*}?)#=g-rY zt-UNq$McHLpc4N8-dcc7bOY@eG{{lQ&*uqG91lRwR#(sn#=%503l#KZ;S$xX7;UAF zF>rQuK#)Cml_ZOViu?vN2Pp3-YZ+6>X#3z=D9BMAd5jxqTS>QA%@0hWLL2tVaY-aX z!nU{85Ugq?M3bgZY@IB;gS?{zW`j`~ArE{D)1{G;R@%3dE-8Z2Jbhz_0$zZCz59B7 za^>88;jvoxfW>wX#6}D(DJCTEE$X;a*S5XAvC0j#U*FwgKjR7v`NT#+A^Y^nwh&Cq z2haCDFvyZV5TD%QiIsL&_FHv=SVgUm>j~`UFqy0k(qSm5;ap%0BqTH{a4QO2Svva4 zbcbB1ezJipL27LG&5s{rh1{s;8VWOTpYx1G=W5SxJUPSJ4FN?m7kp1Rt|X}t1Ah5C zh^1mSbz8$#YBvat(T4Z;m;DqmB9AuSn6bOd3`X%b!xmt8ikb^U37#NgOj1c?3vx{m zg?E)3lC5HPJNe1}3Aq$>VS4Pzb+2@qqCEaEM`Zc1g(#(07-M&kOvhLx3vD?Ohsp9| zMHKYNpKAroi6BdZaXIz$%@{=__PKYHJ*A?PG(L;Oi14cfhV~w%{$;Bk1Jqx^ixWy` zct3Mt17rK^C`I>se}3{^F!7vo+c@4@sVHm64?017{!?yv;3}Up|=OsDlotFBY89xk_N_SZZN|Xt|?;i<> z08-)WB@wBK9@n_R5Dc)!D*bUSo7S~++G8AyB4c-b3}p!^`J3P83Wh3`?k(Gr>7Z{h zUZyi-g9_ZSS|bn(V-EXCI{Luy5781QADTz0Z)wHy;wVeG6#1KL4HY4T5bw7)^^mPl z)qNq(2V%VW@$Z)+EqPe|PDY#)*}1^V=*K_C7a0;j`P}*b{o`93Es&qT=bRvN>u9~k zRWa9D?Tb<8V&7RgC)UnqxrZ@vJp~#*k-TC;0>W+M#v5Rq2=hieM8cAu3FicxAQC7s z@%5EJ^G$l!H;ywfQ@QchvDEf6T0ia=ltLim#zKhRA~??VB2VVA7ohpZiRUW4l$%qZ zTtgi=w3ZD)mqoS%Ebx`U!=`}3r;CDc&Jy_o2}djsvumb{SKqcw-(W2Z&zE^MkZ_A< za~uZ;IR%B!ttN~I*vr%ta*mY~887Z|nVNjV-xTo$C^Qc*IJHbL4nzI21!G?7g--$N zSQ$h}MP-7hd!kPATbWYH#nm$W;KMjalyiV0_*Fe;ExUFN5TV@R4Apba37-yEV;Ds; zp%4vD=CI~)3y^Eu0_~>w!g)M8z;#0)<=C5(dt4P0(Pim8Cx~IuDB>mfjOOc&@)7CI zIc$Z_5u&-nUQw%}D9*$}NisP!(J-WTBsX08V>+0WWK5Ut=OziVAEqEGFd}2?sm?ve zbFwk@kZ9;9w+-VUhCjK>7su-Wr6b6P^`4{~5-$sn`+!kWAOdt@Wq^)r1%RS^z?2GB zG+ab=kV>48N_6cumBu*P!BkKx3hN{r#gvn$hu$zLB^adC)Ixl{;_k_`TN>Tn9L4>StoBqMHGyr!0vVnfwfL9K(q z=++$rX$1E<&10ppC8f6GD?BQW9g~3n07TIlJUxBmsRazGm3~*_E$S?eq{zQQw3V>( zWsZV7_4xGhg=2)oA?E8F!<;>;lnGA{IG8^%n3<~d6y#;z&@HUH01VK^7a$;z4Nv#R zAw)JFT{vLl)r(#hc;^jA;~5Uq$)wW<=PFb>;2B6mB|wqioEqOasVib5z+q3ik7Dru z0O1go+FlX>%aU`A4g?$sT!^9PRsbjZv6v92&lE2&JUCypF$O+Bm(XBd2`zxX2YBuF z#*U&efkk!%&&c`3JuXd02@_+bh|l8nje~CR5|`9K!|x-Vq_OQjawZlpYq{FT2W}e6 z9t7~2LI<(NN3m0>RvXpLR4B;F2j5(In_-o-PZC>R%$^Vpgk|hbo=i(2obuU^g`Ti} zi^u%rTHOfz;PNzV{1{-&(f$rlE=ecZ%aGJ6%gFY|Y0~>=sCs14IACdi<{~4gUnjmp ze8RL7Jos?2gp@RB=LFr0BpXM4uTFAFy62_Ft|W(L!jFsNXo+iPafhLGvF!YG3;|uX0IrEwm z9z64fddASbgv9g8y5Li}eX=|Hq~O7!#VMrMzHFDVC48m^P~IoB8;=i+G`D-xZ+wQ7 zIB=-PMd^^UNb$23TO?T56IJ%Yk1&HQN-oc!yJSKl=#Ra zwZ2l?_{jV~g6dIT7*+^LNN2An#xUea8*?2v$ULnZ5|QqlKUnmxCMrh`a&g+sJE6to z)>ejn6_l#zPMDSBS>e_y1ys@Ti5hV%kL&Y<+IQF+1Ou0A@Oo_{bs>nJA1( zQW)dc3kDM%aGbACzAL&VG50s4;|5Y06`pV0J~5sT;pd6fG3W_{m5k74b&``hxX(yv zrPN?E(vbzc%Hp|+0D%vpIm#|&$aq~e6^_PE4HKSw^O~IpHVwRRVqrzd>>CW&9sk^_VGf4s5g`o$JYG!@%tzE6*nBp4SPhWj1kqgnHPV1K#} zArLExOp*}12E}%`j5a1Agx|XiSyi&F32-f8^k*ydRWLHD7?WqvoP&}?Hz7brvuflO z5CL}9RRDk-6Qo%WoqTN(TliJzYau?8W1a01{vMvrQ2Sa zCi6rD-#gALM=-Fv@t#KM^fDyG%!k>LXhA@35;aeZVhnu2t8HZDcpE1JpQ92N85PFO z!N+v)GMG1^Ob48Ur=!Y#*j3~Lx465bm^F&LB@&|P8z487$j0^;0NoALw9=U!@C2dp z@&IoIk%-)@!uEg!DF8*1p<7}GJ)>S!UpN+LKJ&b}jEou0@Jct&2PTHGr>xRdH%(-t zbVrsjF_^jb-dYr zt_H|+%;T3qshjl=IO`~8{{XoeGl5kpBM9+UExU@!NYYjA1SDXLR1uc~)^N8bi77C| z^AnEH@ZlmqrwB7BnS&xu4h^W@S?@PnPzkZ6xw13Q=^PAR*${%*9pjDP^a}fo5QZ6( zZ07g=ht1%TlWgB_5TXwZ3<)bIsl+M3@-nH^YW9!K?;T1hteubWUH< zkjm#WeIpnttU=)_%$|7|1HKxOU4T1A@LO!@R17_i8Ig-P(k${~5BhME2EAk33V{HJ zFsb#30X2SddG3^y%6(+Q3f>c$=T8_DWulLjG3$YvXP)u2F&$>G{V{0EM7e#}oJ}eS zMg|-8$%~o06ff0a?ik_L=wF%DZHZq1tAVk#p#P1RaVgVPU&v`qj=9sW-R=pp1L7vCCph!@UIF5s$%_ef~ z^kF}ICQTA|QchI*nY$#Guni)no{n#peyXQKe^H)MwHl^GJhR)-VWFTcr(AM>+0Op} zgCF=={{WefC&7>(qai8iFwj*;85`(ps6^o@NSGpuCntUhkP7nVOp35mG9XmvN6sn7 zj0C3;9a+OMJz+mKKuPm@VpZCtAUcbAoIJNvP>)&VS#+8O3Ok2UloIt|<^KS)B6)Sf z&E%C+GYjb*#@PpF@+0sg?OHVa=_U#ylF4BjBVtY|P?Zx{ z^aKDlouCzdFjqW}RtW@p;3vJfHCKul5!g^f`J3qDL?o68Q)}-KZ*d7pm$4$w8p36k zOc9R0GDI-S+gk!WV6Xxn5ynZpIAt^QMfMl7B zZ=HwVANzS#t_X|Vf6!nI44s(bOHc*4IhwFyPo5VlvzovTCJ0QvQY6HYafgB-5Vv+k zCr(C-CO%IF$nVCm7EoIx9f7IGyGnH^Z`N@OdI{yANs=>j)Bs9Q?PIqqjm8>+q;acX7!9IK^iyuJu8>ER2QzV93_>Jgriz2eeBhp14jrDc8m~AzGvG2+ zA+=wO``lxm{Nqzbt)q3uNHl+hIGiGxp&-WRrR3IZu+_A8GwXhAt7H1)}iJtv!?`NWT;1=BZG&Q!|tWZAq10d4}mgQq5Lu7vZ5gJDHsx3AU7k5loH zzxOC&NW$oo#sO1Z4h?Glt0Z78-PQ?5&T;<$&jO-*{G6-3S|`KRl5dItln75*QKm+R zPE0t5)!uK9%^^{1$vhHeV4%!tT-E@PA-tAdXWXgiy>WtuJb1V0;Ha^&)`ufT9T;7- z`+FH6kx7;*o@L)SMyxunPTU|Y+7mIK|HJ?#5CH)I0|5X700RL50RaI4009vIAu&Nw zVR3= z%d2Hjpi6~teh$G=CSL_M>l-apq!LtrI>`YxUhV8}^@gIwhHn&nRtQbId4b=Xpmx7n z$Dje_$p`?8t&9~3l&}gsZWfw3g^*{RnnNfA4M#Z|Qdx>bDJZL~cLo?`Be%NnP37b? zCQU@F(Kmxg+XEy(h-!%90F_kWEq%4EqLdJ7W!03)T!@8{Y`H(kgc#%{wF0iz%GLqe zB9bUKl$f1BV(rSYoWXrjKwq6h&Tod(HX+neVKw+N3PH=jiVC+t1zJD#iJgpS6_-=< zc>sX0Z|KQJaP`m?{g4tA(yjW_8Q=swpzraARH_|zAI;12n>HdB?`{P04Q%i`DRJs_ z)DuZ#rJiu3oP-Zz6XV9?G;0aL)785$ID;HtPrJ@BRZRnY1TLr zHQB@IOg6g^H2|zPp(@*jYXKB2P^!$le#05j70tD#Y%7{)XU$&_2P|&)@ltyb3PpqTm4mK68L4rYMvUhO<}3u>dXo%MIvJq8MI8Q@V1_ z*u23i2zLk$kzv>nA9OuPC@I6z9v+t5#H6EO%x6ML8N^`y;qWs?!3f~n{=Qu- z7`2(EFDODyj4B*f6S=BEucP3>Z667{W{n!lO}IPE5b#n1H<2c8ASfhK+XIlKW#E)L z3Ttkl%M?dlZ4ml5Itvs5MdA(H*MdRN=s<=EK!(~OW)NC+W(IQI>_DVaQZP15eA!mf zOG97*=oK)rXHBe>fI9|FiV)G;WE!~?fUPWCy2y|a@dRLF-mp~5&<@RT{^8ZiXCat^ zZJ(}8N)x3vU*Nzt%9Sv`jq!|}6B;Pbtz0b*C!-VfC-a4YoiebGt&`%Xm^UtlXRaHUqK~!d1AWZI6V~mSXMykwE1p~5(DK;TQ zxc~#CJ%d3jg93z%A^@!k$NbHo1QSasCn97S5kB4+=R%X&i~T^OqKQD!I!HO?pWO)~ zA20yoA%Uw7?RpphDH;otKFETM!a%!HVHe`HF$q8lN>^n7!ovVta8C4<5fUjlGD1pF zhsm3KF@Xl#Y~#eu1=^EA0f(;SnWmUQ4G==~fYRg8P1ZUJR3Mm3nJf*Mh@pE!56byy zAuW6xgPV)F>OcdU4~%Vg_hMAkWF7e6D#x;L%9KX|f@bv+sU1(!G2MN6-#P>W>Jt@L zwnVjxIKL*U#pzHnD3=WlP0jUCDF{h#VW*Hw=HV}jIBf^}aP%x8qI8GO<8AcWBS*(` z@Q-ksAe3#s)MCB2CE^!QrF3TAfmqtVWD~$*8={cvi}j)X;3Zx8;ee!bNWog{@3>ta zXTUO50+0#`VQK(8CTp;b3%9fjWTKa#m==_%Eu`&c4bZsXp+X~+=%`A={?eC-NUPQp zAJz<%8ovB61$gLPIDg;4#RI}O!ml|6H1nCP2inqr0FbXhNMyWlF;d(CG!+OTj5aFc z1Gu|>*C={$L4#G(l{pg+yLJl#91C~jpmprZnF^$jUEbTl&u~Rp2-KmtYnRi4+$yC^ z4v4Si&vso|o(A+ztZ>t|0{c>+=cV905wdO;%>!D$vqw7Qj1#Ex|QDfZ=x_SMdzbh+}bE1h_*t!MKVyY-|Iw?o(oJwW{Y zP)!s`@<$sT2<&Q-X-@5O#_`vZNAMwnp$Jv9@MeepV2wMLP${TI#}Kgu{{Ui`XRZVa zYqeXfWD(s2O*=ST8e^MjyC(L(x@Nmzh#5UWEt);X*njZK)Psn18=GEnrm&SHfIgQw z11^9ODkKn`u&Ik&h;4=JEJQ^Yc<1E-yxKQf!{$h=nuaNXKo4sr&o3}R8aMo|2+Fbw zZFeVxGTF~fQfSFQkjdiV>`Gz;id7|6m`}=hBTD(BxAn)W!lfuN>?dZH<`}q(Q0YlP zMxZ1aH@IYC5#-1rB5@v!0Lnn*5pwTFAkcBpfE8$0Dwhs?g{cJLE?!IEIMIgP963Qm z&?d={Xn7E?#_-r|JD(laZ5Eq9j&8(%E*9=mVqHcJ1p>s?1|J%&820QXHt%JL->P^8 z$r9s^K!}c#kQ=7YsVph!VNx>%U>6Wsgrv>E}#&Opb$6q*v3Xzp;t zZ0fN)rC*LrI3B76__$#k#T0dhAsss^21DTnvu7RDS7xFiy$S5U=~jzZ<9G`+!UvpT1gxAQkhtJKAPDS(C`psgz|t;z`X6fld3d_C>BUBwU>W*HvJSn6P`P6YuBgK4_xRTf-I~VGoSAK3m(CDEO(5eE z+m`Sr$TiVC=on21r{-HALsp5MOcf|>LvZkmii-n$p{FClZ``=5h|e}?q1ZaWZb&jJ z947~Z1irhZ5|508V>`DhZ(lid3XdY+=x`(LWGH<{-mz4K)qv@U2_20S(+$>v1byCZ z!Wb2mWAg{c4d79GQm9l!0(fr|dOJ?R7HmnL2Fr`D49r8c2Tg}eD$#AVBki_goUk|I zEAMv+dYT^sr{1PG6GZfA{_u{@L8oi~0ORK#5`o+3f4FgMLv>x#dneN*KG{}<8)5J_ z7;d1+T1Q1adV4ZjLqbRI6%B-DCD<)BLB5LlUjq-ZvArvxC0#}>2Vb$IbNU#Yu1X=? z1y8*DaVs&P2%}Nh7uSxDb|H$0iK^0`h+>7nggZrs%9Dr*{R9cRcSrQQxOqxQ#|Ofp zei6mT;_Rz|FZjz>UnXQCU1Lf|7W)C#Bq&a|#Kn~J3U?oTXOUQCre4P^*kVzinX%)< za1CIjhHNlcb@Np@GK2T4mVf4oMFs2A!R^A8@v7XwP@}l6m zb0mfZ(KeBN<{b=*KzyJ#AO8R<4~2rA`NQ!F^BlqyE1WTuJA7t?5Rxng{`;3U?q@ZDz;};?;4W6q+389HT=~^&!V}u|0Msl*OU6aDhoCQA~4ffS2*7 z+k)V0bR^f)PsxSM(xNyKecq1)jy`9B*lDt#95Rw*Si&n-EZ`h+jy$z-uR#N~_+=IJ zJulYns`A&UN|{GPW})oDxo9SVV>?11c2RJya2ddY_!E$d`R<* zxrf_*1Oa&bF=!-XI+yHF)lXdA#M+| zZ&Z%}B|;7uDU3J~0*aujQ${nOjmY57LnJW(^QYcqp2Lrp*Q*15^-)!m&fpJ{VSyOkod_E6BnK^@3q% zLMgJ7nO_73bNU4rb}==!IiqjZqtmQTh~(8VKx#u_%S6X9EF$_h=Saj-)KpRg-JnY` z4&O38UI8Bvn&~<^#U;8R5EM3^PA3^}~=wsS3NMKY*fQ zA*8jV&NqxNZ+4+H8Z;mcMsB+z6=1sn71Uu=z6QYsfiMngON5S;>O{~4`A%+B)MqfK zLJkW&l+qHX5Y32m494FW-^zptxy}ydpZ0!65;XyjJi|rssw)B+f*rPa5%i{woyEl( zwC@rV;0naMP|%lAL9UeydmA}ZyU;)&*M*W$pmGN9+2``^0Cd10&=ZnjLm0HN0r)X# z%Kd-uUUrP zkB#BmMFden0ZeI$yb{nb`t@){4Q%S*@OAF$l-Mh1A1)~rtw7ov-C;F1GuyM$r_CbH zo1-1+U`CA;h=o>b3wKV$!8rz@(&)|JePALxN)RmW_6mWq8&1(+8q_e0n;VMFdI=4y z7+RPpiIEiSQV!ojXS8?T8YmXZihzKfMx-;5ptg|=cc5V8x&nl+gN7yKOqwQuaaJ8L zN!H+2fQX}IemOH(wumWhlHKTWb`AKXN488Gca2fW?X)Lu%?1TXT=D>=B)cN;!BpE5 z-GX)c=)SPdj)SrC4eT|%H)Sq#Pp@g>cMYs(W44E(iT?nu)m{zowBp)h@teC)2SHRv z%MNNdH|k=B`3@14v7T3w%nzoyAo_JJA_~o2YAQ)TtK|Sy=X&E%XbK1$W=!V$&Q#e4cHxQDEkgC zh*VgL?iK5Xp-z@RDc4x(9&arm4%?5%p-)Lhf#7Mj;K@YPdWiu{x^Lwa_?#rD63RQR z3=V7d0a~yMcKnNz6*egs1h*uB_XMB855}4Vi?%PWa_*Ky5BfU7)3Rfv)j%JLW~QL9 z2{nU)XdGnmYfE8~3wor%Uc;7x;Y!blR-;g#YQbM9>w)qB{j&xj;n6Z*oD+#IbQUWw zMIg?!(8MLm8*FzjP)B2G*(4B0Ou00MQj|g$NGHAQsw(ZLoaxe}cHroJeTVcoZl-jNPRM&hILuPu|TH9qhcH?A-)spJknm=WB~1itk&<@ zfHHv!jY1$Lc(`8&AqU@6S`2F&0HonS9ozC_J{S^F2zJ}h#Gy9Rz(kF(>^Dq8K@-A2 z6$%y!5L%m5l&PRyqoi@pj75~43uVaN;Fb*IS#6f!d9hqtrCSi~$gOgqrcpL7A+CQv6fx+v zy#)Qro`{T}zBqah7YuA3gs2{b@YZ&CaFXE;3Zgy^D<(5bP&peEiBlE=?TVUX#eY{$ z(}eTjeXMEDYx&33B(o&e{{W3+94L2>)_mEC8k^5R-oYFw0uc1<{{VhfTssf}V!9MV z0a(zua|}ZXOgY>T_MB2hKzBFr5MC%lskHbQr_>(>0cr%`IJR?)fQqVDCdWy++(9(7 zRCnp$^vY^5rB0fM=lPm@&^Q-6<`j7c*<3v+Vs4XA*!b7EC@nKs7I$~4!w{qZV9P#H zLHmGFr27Ro@H@{ZV696d_EVb3YG1YL0tkmqxC=C?XGbV{M6Kb&V9G6m$kJ`@1osq` z=6xE<;hwpmb|FC)JqD=_+Fu?lAc+wM2J?hyI)paEZiFz~>)Rn4I(-+`IbhBPB>sO4 zA?Z;Zq8hwzDsx&D;`b_fP*axQ3M?s6AK$N#Eu!fJMRsC3++`O)RRgrOxhqgr3JKwf6imfv zn(UDv3LAdiz#v)}SCttsJB2{r>jzM2lt zBIP!0%!gWwLC&6{#E^E5#YMf)VFAdRh%$mS+L!_)1Pvt}oou@9eH)bstv5|WoX84} zLLv=l7xD89LV*`jIM8UR*}M)jsXeb+pzbus5r0 zJHrzJnp6lU&(0Ri%EwLj!9QlOXULYj39|?ze&SeZR1B1$p$%=7M$8JO3pQCYJ5T@u zED}<=7Gu1ob&)G!QEJbMwETX%8PbmeuM+gPuHyJm2%)P+gCZJJQ9{Ng4RcqOt8< z{{T!MvPwmbPl}iUg-9&0U#KU<&0skIK#$SO%?DT^^XOGimfjuRmupZ_H1r=o^Z1Wf zD6@lR$MuW`Ae%T#@!@SHDSxU6&Gq6DQ@#d?&UBa)ShZs^*3T30mIN9(?g%5VqiJXb zl{In4Ca4!f6<<;YQaCt-jU?Z!zF^!AB$YMMK-vRCD3Q8GU^BF9ghAFl*ZC- zEX)A&OZvemen&A7iX`PS7Y2wTMD@48WZ@`xW0DOafb#*$9SEZ6gGzCXbeG*4*=NDB zT#~a&9sp>LNCq}2M0zK>5CB6BIdJ~n1X@jFi%^t+4v2{?*x!c)X37F5+iyNza~1x; z6t;dwTVg~y2-oRMU_*dkKC#HcZ?&p^J5$_Bh*s!@e_Vdr;9CIf0q{Hz!=dVZKbr6{ zP6-MGX-+f@4S`}u1eR;gX3jKJ>!(LCG?7xPXSvzYR0sQJUA$HzA}K^{rMxlhN-NKV zK;yV(Kt01C@~W@Pg$GkA1B$d4>nBT~h(O#KuEqI|nTvB;FxdPT3+&m_he(t}H=B+Y z6j84C{4my}G`^ZEtFPRp@J-R-TG!_y-+*!^^!z{TDJY8l7XhLur`EAaIc=nti@Mg_ z52fmWNfZDXj3PijMuY@S80FEy1|+y%7lM2VzD)DYDWgX%`n*853@P z5Q*jhvlavbA#hPVoF`y=IUEx}HKTDADvSm_s`wP!4Vd3LBWGIy);K^B0vd+;!z9z# zq#fZ}T(b5R-Iyj1aSMW{LO+xDSgTvqjRA!rqXueQs4F6$qaR0$C?3GFg5C|`LJAJ# z3>MLj(^8Xx^Nisy&Y>9eFY$);X=$<5I%>6qMkQ}RP@2Fir=nrxq^=rPPvYkL4vGf= zKn{H7vm)*W%6e-d%m|k>P>okP-^NlY@;Jp5OJH?nt3h6~9)%6*u8+^M z?6Yy92t`5;C)6&Cp8A!H8*#c8h6L4>S%WaEY@)5fi&T)0lo?L<-9vTq~^k#21to`3!0 zA6fwtA2Z(ToF`b*1=5@vQ>X53{Fan~OW!9*YZzJw&4pifdyPY&!W0yA9v zWcK(3A7A~Lnx^s}+vh2@+^ftVG(q{(fOU%t@)%c3Aa8gV>GwCAaQ;WBcH2BSVif(6 zkw{n!-|3BIOqD68$hQf1nGqTQ8wL0VMVwt3wueC~=rG#5L^pi7Ag0x_wnPV|lUJgY zBa*JjJK9Y_F#JYBT?HTkhU(xO69|2)P=KWq2ha{901GE=IF2XO&C}6Nu~tB6A{&By z8`+C5o`fMoU@!Dzi|@)k6LuUz?5<;>D5{UDdgBL23Tpv~*JL2vtLqVTi&)tTPVDv1 zNU><}y7{HF2$N}U=A=KHfrZ;^?+$+CYMndZuUNB-h#$*i$&%hgRUA!0hd!~nHsJ@% z`|*4nXrENSg1j_*4qHG8U&KOxm_iLg&6dz00sC=mz%AY_Q|XJquzvK{_nN??f&BaZVRatm$_1_< zIb16oTyjB0O)bzkr86l zez4qLiLekY3q%zz@PtfrH<%E0_r>oXn-etJy5zW^@`RC|9RqL2p~ElVGCSz-6wX!U zDrlXqoB6j zA<~q$2%L`ldeGN;&#X{T1zwbhT`8yQ53(USVxnF}S(b+YIzkA{JTrHMJQYi~U+ln8 z+ZLsw3$(q-7UA2Ql$W{OmqiGJJ`d&%!t60X8s~6AJsS97_QUI{{^J66lAaCqv*o?R zJY=h4loY9cn8$P#XwY4>SJCmC;#}2h9X{A3U1T>x1cQFAQ8^5N3a`N7OvpSus1Zd2 z;%4(79Ol3TQs^=K7(RiMq+ijFI+#S-^t=Zfd_}Sjh+|j5jo@^bp&QwHWDYu&41hAAn#>4m(gs`IW^L4XjZrvsy6WSpZ>G z0=@%yMxL=6HplJB`DzLx0S*Z@RY(i^pGGRWI)c(7$U-`mC49hC>x3+{M>YD>xb9^< z6`CU;s3;~Rk%fmFX=-#{z{Q0$eNRI>LV+e8_}obQeJnd5`HQ7L^3sz`rKk96)C~08^#d@WG&vK^=fX@5zME*buN<*v5}7-s0h@`KmYOyd{`J z0qdpb{{Su?5yu%iRw})$rjZc$W>I%u6A_B@tw|Jk02l=d7y8y|e!c}LU0-9~V20;| z0bWBwk%WC=_&q%--2)H1r5&4M?8sY_-A6`mpC*Kst0IQlfKJsJ_iU2Rb z+mt3)S(GZ;2DBJjv_eCiUJd}#;wY8ibTWiEIKE;nb$)UhTp-SDg53t!0ffIA!1|xw zF94MaE9A=JQ9?H2{{H~3R0vkt&=>dqWBuVzRRBdH9t%hfHgG<`N~4R-Ibvji9<+)< zBtggfPHeDEp~mjb+5Z4v`B@CotsYFg=Dsy_a6_S{noP%VwZK$}b|5hH^?I?MQp2(e$oIi}Y-G8&}-1j7|A z1_3~zN}Ej8J)66d9UN(gVKw&5?QRMb*a(S0Cf5Yf5gZA19T-}+sF%H=JzbbRbP!7S zehPYirNG@Sv{(a)_%6GjKF_=qOCTe<<^UMzRGFnN zO^5#CVDUy%c7NQe4DGKq@$NTb`=M_@v^-j1Kaz#Yz$hOPG43twhSUo^GT8fN%nA_@ zd|*1LF>YqiRDf5!`Ofhwj?e$8bUb-@dCCaZ5|GK35)J4%tO zitG6uumyKPSe7kRFy^-717Q*Y%v<9Ml7c1kR!Xm`yQ~7JHqvW0f0&q}hh^G0%>1Px zxne^pm;{ZU zJ$s9{hS1P}uTYa$UCj}apedNz`bnsFKTu;f>UA~<6xdj~dJQKj=mCPKRCMDy_)S?Q z0UH6*uwG!Jv;Z)sj;A2?vP#!yAW%LE^lT6GI9(9@;@jEqoJ%15;So>MjRv-m9X?@b zpeguI{lLY#Vj(YdE3NAX(voO}78h%Xv}>2uvem6^aJ%g=JTA(V^BZxaAPRlwS6BxQ zoD>zUJ3btT-fYdI$$m9afXWNQ%H-~;BH+3MCnK(4})}<01mPen|u)1tlo2sWLjoGbDud$LZF ze?L7`Ro;vL05PI}GXocA#%8K|#=o4~%r%kr!+NWbhB!3yU)Lz*GheHkmMN7s>VzJ`$KI6(!JtLX+F>U1)(3KnS!c zy)e7|j`)IhUEXCyE`hRZ?wk6-Na`ed0bW!u)x%t)6d5f5(OCm0Qok`S6gZg$zap1G z{X2aNTfA^`Q*6Vi+!y2|GHe0M**4((8GIiP{{ZbG3AYTXFvTK-Hq+J3GLRHn)!M;?YbZlzg@O~{!0Ezr4gkWRjaV9L;Qi+@Q(wyhXmpcO z$~1+bwmAO)ys0G)sUMx2a3?{VKx{5!1n4g@NCxgg4S9CM`NLfL@(BgZs6XvL@xak( z17iK?$vP|H#dM~N%Znt?kONDE1>T5=hw%@>XCy%xHpxq;S1(FJszQ&N9ClG#B{%b_ zlf^@$OJ_B=27{9NYDf8(@%^1bQMlSTH}@AME!d+F7ai?_Aj~=fis`Ih5W8Rkmbec8 z0F-i2LJsyRGD#c4Q(81U(V}Adr)Ut#+q$1tm`egK6Uf#pfZ2K`ym3dVH9DD~h?1z|#sw|)MO0meurB?&C={XI?e7uTBdb~lk0@?U7`+-@ zskC2i-r;D{-oPf0M+9CGK<0+fFUCr&pi#6whq$MRb@5~>cPqQZAfo9CJK)5JK`Cwz zY#e7&R4AuOXgYM=;o%~3laY19q(^275rb-=K#IDNb&W8LiX-er6va;5J22f2sx#u} z|HJ?-5dZ=L0RsdA0s#a90{{R3009C30}%ugAq5j6F%U8oK_CVrGeQ+nBs6jV+5iXv z0s#RC03?rFo(5(chjjXDPZ4X5GgDYv-E~0R&Tl zEb`)3F%4~;g+|Xdw#ET>ZW9A^Y%PN|I@rud>Mzq1RHnNKntE(3EnRH}^o`SP9!k1P zgJ7i%j1<$Vc}-5`!&Zh0w_k?4E_8J|$wd z(<~S{kM+zyI1>UR6d0Yu4V-iKOn{^g6LxuMB~@j)6({Y2A;`y$WnWl*#yDxK)uxq8 zy?T*y3j*7L4Wf4jI5uK;0T4V^T=Jno%q4f?J*!g#30!54G6??wX{#Bbr%$(G3VVIK zP9VjV;xO~TEF&Wf2HeX4+b95h7(a#IK>}K(s~}R0DhkNB9|i(rXB;w_ zhKv2$@ZGi^iauu69{v@W^DZZM!gE|!BbmIB1>V(_RR$p-#W<7@UTZWTk#_M|*??Fn zj0V`!kAw0)H6L*VR1d_!Q48@Ev&26NdHCv?rcumLy~a<IongBYHz!}qs>~nHCl(Tk*y`06?AvqW2Ig2qYx0lnOD$>+Bn=pAE-ii0SNJO zv_7aPGf%o@v8b}R7TO40Y*a|z^F?0CK+w5 z4kB8vaIN>3u&E2pS5R$Z3WrG6y*i^*>iTh{v+`-7mDIG+*woqGZFZ8aZ5_Y^HO80K z->FLWQP4A6+(D|mLgh}-is}qDxCBboTxM(w$llB7SZ2~rU{fnlPnDL|tSbV=hXt&|g8VP9FH)ao=Ae}7+FUtawxe{k)l+C}GP zpQrUYwF)$M+tIJDQ~1P>&>hQ0V<{E^Ey%DFYj5Ri&Q4FwXc*wNYNH_reX7>EF<15x zNk|utN`fI68JG1lywjtvrCq39`oYpQwEqC>r%=^t4{uYa>Y8hxYbXF@wL!rXP17sV zzV+L@;cnFxT#YF#!KL^P+0j3oy?B(_w$oE}eIiqTdTDCzv9kBCw(VN7fLr=5y; zf~6k2Nt2d4P8OzOvv_5}R8qK_%k1hm{w*497Mn+bTW5agK*%!VoM%~~qgPo2qV2m( zQT8fw2@L}RLWk28N5-Fa6t=7Ul8!7GZa|vQ)#?$4RMFR~3t`lB%djjdy60^rH0W$L zigfFzRjgFPwL{`bKK}rDjG?)X6d9G3syDY(UtNUTxD;PPqDa6Sz~nAW#tc5-P<^`O zkSjho_}1On)4Pt3r!~@Te?S0z{8{yj$rVgX13;@%X*zOLzG}>?uzG|~-@u)g{k3~WU>V{H8#xBM1XN*@ zDgbiA#9u-3WsISOXH3rGk43{V#bd|gtdKO^(Y3VonVqT%_Q~dUjJC2CDuBC>L}R|z zfiiOdKem0G!(j?s)qj5sb%0<%a73rhp&JYeo}YdFJ>K0mqU$ey<)hwaPr!@@J_PQh zYbqnjUYzmVQR!`8+ggW-y0E+gTyte)uw`+U!C)m=&mmJhDuOUJ;Lfu{-KQPCo3F1? zSgOE<8;<*Wo#t)@jKtz~4NY2l7!HkDuS^-kfjfdb2I31GaSN7UCZuM(%;03`TQ$oV zEs?-5jEqbWVEH2=ZNY@%TT-YSR-_A(su{3eqyvPhHstIC;xYiaio{nthtwoDvH}4b@g~UbvmGo`R(#Jmr3s{{DM#Asmn{X#Px4j~Q<8hy)?*dX!RBimL{wv$6= zixH7>Q~Ys#LySdCCgWX2jO-A?SQtK37vu_siliN-*U2jZa2LKF6m7XExI$p%vTaa# ziCZ%9xQ`e)NWO%-?GyY)9zmTs`Pwds-MdMO!oj!@BTN(MR>$A232EHH=kh1y#Jm&B z+NT(?)!a1hC#k4l%YdKbiyPDoeH3&04%?y297je&iRFklLK*__7SB7F4goN+{fi2N zwO=DAaP<|l#Cpkm#TW!f9FRJAA?5z&!q2)RgcyU7n0DvOqVz2`t54l-snaa!?m=e{ z>47t8%%JLfQj@lUfsDw{f#gO4Zv&U((BSZJS0o^1-V1V8D->cyPA=rN zDm;&i?Z@31ZQT;(ilFchwZ{#8L+E$;8N598o z=v3LnYFpgwIgYHH8oeKZ?i%pBpro7;btQ6OeX6(?rPDRXKwFtAKSo&R{2YL%Vp&)D-~s(hAV= z6-{gzHTsQCq=9a;rtTZmVSR2e7XJWTKe_$M{lOU-y@c2aVV`q9_uON|4&>rlV;0&| z(2Q_mlI@9N0C`&roJ$xX%tv-OE^#}JfCY-9n9c#*p>VmMxo6re2yvLegPEvi1`BKe z%`36?0QW99T*_a4D$rmKRFBafgy3RfTwwnI^1D#U>RXMdaYRC_HUd96e=>f2ahU2}hdZI^fMrUsAuY z0mD{61a3U^=Gq-fox%*akOwW0O#P3O^Nhq%{=|%7NOS2J=LIS(nS^jeshA84co~(x z_RM=bXE5qFaRF??$I)8z%mJ0QyO0l#T5o7shckOZ#QPlkTMd4h*||TCt}<6m`h!oj z%Yd7AR~2kVPM1&Lj}}>7o5&uVkTO0edNu=P3;32xXk|m-t6%!AU7?fR(`;oDrRVovyGruCko79}_LSQm6}oa>Aib0re?GDUztZjsQ3| z1kVnDjtB#SLEDj2I-J5$PGd0~t$^>`+nLbid~8BMzy=6Cz_|FsOf&(Z4KULO_7^_8 zB#5A`T%aAIWjBOgT&7C}Y~oTKcNH7|0B^jGP?u5-U_L~43fPR5-Ui?mRE1Cq69MC$ zJ7s6=OMM9c0BD5diD~UC7tnuDRdv0HTp=P9?uaVw^DYa!kXV9CHa3}4Zb6tbU<4j! z@@C>Ea&IONP^R&TO-r0jO@_O+s%luS*tR$rhbAw$z62She1?eJMz{#JVYpV<=2+Qm z%)~sHgDD8Y%_k!et|R?KC8J2J*qyd&HcE()ROwt|I zDTnnJ-@u>$!~il800IC70|NpB2m%8D00000009CJ5g;KkK~XSaaRU+}GC(6jfsvuH z!O`LH1Y+_3+5iXv0s#p>02S^}t%>MXXhyO^9NeD6H68BsAx+SVuDkS~Mc{a~&tb_5 zY-6!hR5cZwE|QZS?!-DHN_0@Q#GJS{M-tbd<$+BKdRVHvnl6Ht#};yH)j~KH2x=oH zwr8cu$3aO8qJ%3p82*v&G8VsMMkea^9y^q9^_N>G7U+dkzuXJ#)1zN|$(6M^{{U(_ z#`NWP@I_dwTGtfdbcUM0D6hBL+vEQLMO2hOwq?b-jnLL=Y|l}Qa@h`v@3QX9C66x| zLd;lw_s`@yMaS}d&kx7@LKQ{WRP=e^qx9SMs&8G{MAx<&cv%#bwY_Ff=oV#Csu-}} z_V_+{aSTg?=7*8eCAVSHEk6RZOD|`joL-DsYqw!m8hexBEf<>5Uld;xd$$%{d8FLk zjABiS=%~oBIp~L@At5-oE062An}2a}3*8qlBuzdKQyf(EtKAia(|rb-9;V~eqobv|4v}oT@-L13 z-Jg}Xs-C~~@xcAia`_?qHumIS63E;wXUX#$jATP8G%?A^$&Qf2s~5%0^b&>bMY!_| zpyY)|T8fU&Me%Lqik`J__Mwka>l5Ao07NY)erL0NkBN84sbUd>HaiuM$CFsUYnR>} zkd18D20gT?AG*64i}>Tgr%g!=W4D$3oEgoG(zYTRI@;*sRDJ&d&Ip@+dJb%3mWGmc zs?pc*qZJ}s8VY|i&{S^4kDz0~$78pF3a7x@&cuG@%YUKiRro*S*YrIPZ|X%}!lPeE z$7ATTGOY(=`XnhajCMQ>V;IIUjz~fw=xJliK3g5S-0wmcK}l7L%#ZBe?{4K9c}&6_ zm5NIfSLkRXTNWnBoREblNikuLsc75NvJ!7*E%m*RpvEzgQS?;#5yaLdp~c8sjB;a|9SE#@*z$)}`I?atG9n~KMnr}oNsdTT(pnCOGk0K#{$^#jL0-p! z)pKGM$kvl*7di{*5QT}c$;pik4GvGEp1T<4>|>sT7{)Q!#3Npk5Ug0J#w=Kj4t&~# zAx+Ck^K%%-dcu<2Lg*s}Gc-{o zLPP)B00;pC0RadA5-J&82HJd3{d*5?|s)QQ3F7V_+IS7Z!mlzGV0k<%Z75H%~v7P*+K%-y|L=0%k0H$cj9CDmaq#UrUByB2^bZVma zIJ0>^eul)b#^1PLjK;(k0~a9jo?cW4V=x}m9VMjtV=6b(x}UCJ`N^}BVP?;8fU1|b z5l38rA8O1bUUh?>+B6D}T6GSw0ptUfB#J3HO(gZEU6JiwN~q@%#H-y!kzH9%vXs&5 zg36vYCT9mbj6T`RjSV`Gap!j+&k`pFX(BCw z;sXoEmL4`g5W!C%lksj(VsjzfLd43xXp;MLkbgXJ+m~Wd{o!4Y2;Mc3{owxqSe#d0 zC)|K{k772~2jvWfL~@N~H9p~XS3n$7qmb9!n_*tB(}6`-LX&|AMVy9xhEvEAwS%xZ zT7GV(G> zvdfB%y=PD9_UtFZ^?9O@td(dR9vU}2J$r1@hdWm!>v125$Zbzn#^EbHi4BSQ5_4zk zG&4i+$Q)?TLyp~5tO3MTW;^9kfDN?;Sd2J+^@!YCdG1%rkbkTnSn3#LXJc4Cuwnf6 zgD#D=?aA@0@_&@_v{8IT?XSus&Ryq9>G91Wce&Ckl>Mo?rMe%qmb#?(PzHj-!ho$b zvw1u3W0J|hwO5sPBkrPLC)}aO{zU#Zb7vP0Zvyg&;E*Q4iIZgIcTJ3P1cZidoqh%f z)TIiYoF7@RKKH@*oyEY)a1efv;U$sKGTe}~yF9isxdyrAUc*7NiEc@JHEyFVQo$Ro z+$U`;@=C>?6396%DUW<}gRLcK*kt$Nvfact5Dqy5g1ZjG+zfDcycwZ~7w;SE1}6Jw zQwA(S1n|&;Uf2PG^7&z1dBOLC>|-XZa?O3~q^xrj6WZzgWD(`AjVv*D1W}nbGOtXM z&d7LL7UPv@t%L#YR5f2lmV|4&i0w1+rwCwOg_!)VS5)@$F@uSPP8iIxFb0(S#)yJQ zNEz3~SYN)NMbjmb7?Oshov9T8kQ}VMfdW7lVT{|>53lt+f}n~@HV~PaP!Tjign+g5TDF$NaXfc4^{0*z5JOwy2Y0J&VMdld zp#m@&46)e`>C^sE$-iSL1+iy%l%`d7GbqlLUKe&|nJCF06ueRi3dh=KJHRBa-N8?) z*_SOra?1%>Mzxinhn%v_-BLc(62Itkc?r{NE|rdLGwKXX_D!N!i;tKId{mJ^^M~(z$ ztpRM7b5d^9bfc0alV29k#fHX!- z3i&bZ*T+n4SWw8uGGu7uGm|V}{7Zcd}pHR=YrgI6n12<8f zXPlIJ_Zhd2%q3Kjabf~MNRv1n5Pi zmDt;XI;=8P?=R5EP1#qPNertp_il!b$1ALosuZjWmd~x=+4>IOSy2{EhcLw)WtOsc zm`ZHiOHi`p5tz&8OOShY?t-RY7AuxN7^zs1)gkoP>2&_s^&eDU{Yt0M^-t0#^&8Wj zbr5y?UV!xXsUd4#m+GIUeyixn7_hq&v~q4`aVfXe=C>F}VZV?{Z#X-7BoZXyr#mr5(KjF`QiWtG_myLEc?YX2%c!Yz>7m;@)_N^+}jB^w`fVlc%-kGD*eG}4C)ctF&`md{cnpS(J6?F>TwF+azjiXIxroC;| zy+3j#AF9+-rFxLqTNV;U(yx`$#aWngE(vrw5(H-p2l2=9G(hs%O~kdDJn5HOrzo-> zqY^QQwxB^~TNdL~GgxVvq%sDToM?at)^8^TpnhzzS8dp}knf(Hv9vaCleFr)HS z>7=ri5s6knv5{j#oSoKCGfY!iCzl}FjL9Qvk^PP*?>!IEk6rZ*N_qOR*VgA=PLEmv z+%7P9@t@xD4$h6IWsq_GQ;8*yr3aEQvS|_ok6UIcc;ie|Y*vtRAXjaTV|`;CIRmE3 z5sYW7^$7YjDQUee>IT2cSGUw&Sw0RG+qh4kvHp@#oPtf5W`Zypv&sJe60I8%ogZg! zmhw0xLjB5JxQP;_imKZ&+^-`1WxZZC)5m_Rr^ZV)na(MRZ4en(Y}ek-P-N?d+6`#x1~K3(?FA`^)J+(n^KGP&q}3-nc1eD*_ezfcYtwVaiWB# z@ktVmMc{*<`Il2f9Dto`C5)loDZ%(Zl68QBGq*1ESEjqCAUbmc<@$GzHY*qzP=Ak; z>`h)+Kxc>kw3!+sMmaQ5fJ)HmiE%bhOM2{h3NyyQntiU&5;E5sB0~UDW8|Q#D<0&9 zn05*PWT>(+<6aR6;fGv&#t<%8tt8TJHlZ@9W>K~Bq>+r_91|0A3UGa8uPf#fanrdN z%^1%Tt+V(#{`LpaJNi}s0NnwfhSeAfyD%PE1DQ-MgnWHvD;J^!0)kGV-iRd+<-v(6;U3mGd*M# z#Dcj#-PL2S8>mz4lLQg}0Q*-Fq`w9PNXIv%Q;#`X$`L2nO^Mm2A)dfhXIQPNO|+Ah zaIrMwXK~sxM#f1kh~oq_%D^0s(C5Xh-S0esI$Y+)!>m!ig05C!7>Y#V1~RJ;G9sb) z{rNx9#E7u);KX!&LC}v^jLjV@R(e&P9+}k_sKOaRZ|iO`?5dd8C$fFVacAzg?@JFa z`BG`+vfFs;zYtCRII&I;JE6|ET~5eY|bL#Z1TfsHp>NX%Mp zaed^b9y<|sUM|^sRkz0?RExroGJ?~H`%H2bM}Y3NXk@CynkPVHwEe7)of|?@FhmI% zW?2@?M~O7hfu_AV8fa`Y$O9fa8UzjPB{8mp%4GZI%kmzp=my~TwfZkto2E_TjsF1h z5s9NMCUr?sqyi|;+%t7qmR=kxNLE!D)Esw57A$<^j~tLHn1=}6L}nm^k!UsIGXeWf z*LZNSILN~wUQr;*^+Ly{6qpinYG}%(VyB=^NlI_!kih)aBrqp+jx9jwazuDGnO&vf z#S@S`a@-}h#-z_)M=1wUo?j+d<7s=&sa@j)_N$*O+Es2r=am__^!}kdlZfR5?|ui{ z71kC9!Sz3;%CWas(zdQGwTc-i&l>Z?(xv`~N}n60*f_LoB)z(*b1Cl0SrD8#PKqP$x6jD<#}UID%TvIITut&V-dRb7~8-| zUT>B+PkCe@R)wqE`9t$o#^t{|IkSgsIA=?xz{p{I;YH$#(N5>MlEV@BO*B>|0L1V{O2>ZeK?paFJxIXo4pnJ>eV9CwSvWJdv!?2M6Gie*XX<5ze`NyCyR; z{{Ss8`bph92AWs-H4dn;#DJUeGV(UM?AtM+u_UAe(#i6s!Q_DE@DsdjZJgG=%{e1t z0D??v@{{A+OmNkkA&qM z^yrmAS$b?y0Qmmc4HR1ZHfl!!IPgRxv#EOn!Lwv0@~G+DER=Klaa`EbuJ zccsHT!vyl2cWDnN*(YYJ1(``+ppn1=-Rg4KjG&~9+G8yxYT{8h?8q4@$=-f42qM#H z!5EC3>DCq~h&OtaadM1Ic}Pg;@Vxc7<^G;z+PJQepN+E2+FD{Zh%-jfcv51Ej@Go$ z$iWGgBgsvOpk~VumWYMv(@zm67Fp~khlW`9&Xlasamz7??Z)9qC`Ny058wKGd6)SZ zBsml=r1EGaC%}SHoCx1FqVtQ?rdU-8a-gF z^|vrJH&L6+@ zh;n;{y?+p%hoC_XNG3bXA&1!*Dmb7vW!n8hBWGY7A^vj+DDR(EW`bO|HJ@0 z5dZ=K0t5pE1_T5K0{{R30003I0wEAFK~V!BVG<&7fsrsWp|Qcy1O*fDGeUyl1{5Pe zLy}U`@&DQY2mu2D2|oZfBO&NyJ7jNzG9E3C{OZg?6u8EfE1|9V6~}|c2t(HgbY?h< znSW+=`HED0P8VhLMq;tB#OL9IE-Wd?P*O~qZX~pYVUGvxSnfL&*(Oi;>gB4|s@raG)Cl9(0_?0xAUI>T;Vy^<_FH4E&XWTWBuy=r!7#ZhOwEy(Cr<;4B@sHyTWd zDoAR@U6-+SCU`A-yob@#|GLNb_jrronRo-Q~4RMz+U3M$(3@#M{!F~!Q(LQ?j}LtCTO{dx`-RXzGHodp$B=*w;5OPeHjsa9IG z{fKn8BJ9@@Ye!!my-jXZIdWW5#MQpop=crG#7AUQ0^(u@o}GGYmPIbEHx@rf zhOXhKQi;vfmug?TNyKl3Q|(hqZ?j6eN-}x-%}J8Wr-m9FX6UMO@nDRJ%m@QA#yXI>lBQ`_9X0-Ata3)iRVia5KXM&YQ6}RCL z^JsF{616X-RTV;w2ZMqoT>d3I7_Ds5p)V;_8qwG>GOwK3i(O(VGFDZ3U(tAuYin!m0;#BHYw%uK)ny=Bh z)P3iBWf-!SxD-^Kb!iFvzt!%QDyiY6LTgr()#%%&`d=>o+NpB|aLSY-w929EhE%5t zu2pf5Pq5x*La^c<)1wpoRTWt$cOEq=trC6$z6;6rQ%QC1*Ghl&XXk5$MOReR=#~Ef zW~zhyK}_lVKmCu+Y2zwy6n1aosO?nON@1Udd>UW#KJTJZ{OYMy(5bqd%iYZU+kS78 zKW?lsjCqdZ&e$Pba5Z%X=457AiGiqV3ZlYHLL3j;zDiL|g%%jbHJ{PpQ0&U#_?1nH zo_mbj2XWZQcPuvpW>PlOGn^3lGvt-wVZ~`fUtUdcvcq8}%n#ytlK8Vsm#hB5MJDB>-w&g-VnuZYulsAg~|G!!vrD;g9h7=q2!a`$ z;O;Y3_7%UnDPDtW@X zLg-Z{La|h=S*b}*6=*qJn%l^x+N7=H1uwIcDU>ucK@vG)6^)c5BXJJq6pL?{kkI6OTUwiSaAB#J`Ee zUZ)We0}o0*Rx4kTlWha-W=>@y(<+{xIcdbJ`fQ)K2%QNKMsuZXci!H#@L zRb>j+GcqSJ3gW?Ki-a-Qszz#TDJfGq!0=KyOZ|+Y&yCEHmK2m + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS) + Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS) + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl new file mode 100644 index 0000000000..cb77a3c7a8 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/superio.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include diff --git a/src/mainboard/51nb/x210/board.fmd b/src/mainboard/51nb/x210/board.fmd new file mode 100644 index 0000000000..1955a05409 --- /dev/null +++ b/src/mainboard/51nb/x210/board.fmd @@ -0,0 +1,15 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the base of the BIOS region. +# + +FLASH 8M { + BIOS@0x200000 0x600000 { + EC@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + SMMSTORE@0x20000 0x40000 + CONSOLE@0x60000 0x20000 + FMAP@0x80000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/51nb/x210/board_info.txt b/src/mainboard/51nb/x210/board_info.txt new file mode 100644 index 0000000000..65c46089bc --- /dev/null +++ b/src/mainboard/51nb/x210/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: 51NB +Board name: Thinkpad X210 +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb new file mode 100644 index 0000000000..7ee3b2c87e --- /dev/null +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -0,0 +1,167 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "1" + register "deep_s3_enable_dc" = "1" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c1641" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + + # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPwrOptEnable" = "1" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + register "PmConfigPciClockRun" = "1" + + # Enable Root Ports 3, 4 and 9 + register "PcieRpEnable[2]" = "1" # Ethernet controller + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "0" + register "PcieRpClkSrcNumber[2]" = "0" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + + register "PcieRpEnable[3]" = "1" # Wireless controller + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + + register "PcieRpEnable[8]" = "1" # NVMe controller + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL1 override 25W + register "tdp_pl1_override" = "25" + + # PL2 override 44W + register "tdp_pl2_override" = "44" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/51nb/npce985la0dx + device pnp 0c09.0 on end + device pnp 4e.5 on end + device pnp 4e.6 on end + device pnp 4e.11 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl new file mode 100644 index 0000000000..441a80dd4a --- /dev/null +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + Name(\DSEN, 1) + + #include "acpi/platform.asl" + + #include + + #include + + Device (\_SB.PCI0) + { + #include + #include + #include "acpi/graphics.asl" + } + + #include + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h new file mode 100644 index 0000000000..3e22ddee27 --- /dev/null +++ b/src/mainboard/51nb/x210/gpio.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), +/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), +/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), +/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), +/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), +/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), +/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), +/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), +/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), +/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), +/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), +/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), +/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), +/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), +/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), +/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), +/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), +/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), +/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), +/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), +/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), +/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), +/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), +/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), +/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), +/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), +/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), +/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), +/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), +/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), +/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), +/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), +/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), +/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), +/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), +/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), +/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), +/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), +/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), +/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), +/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), +/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), +/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), +/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), +/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), +/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), +/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), +/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), +/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), +/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), +/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), +/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), +/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), +/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), +/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), +/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), +/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), +/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), +/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), +/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), +/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), +/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), +/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), +/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), +/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), +/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), +/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), +/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), +/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), +/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), +/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), +/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), +/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +}; + +#endif + +#endif diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c new file mode 100644 index 0000000000..973024a376 --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa2155, /* Subsystem ID */ + 12, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x17aa2155), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x19, 0x042140f0), + AZALIA_PIN_CFG(0, 0x1a, 0x61a190f0), + AZALIA_PIN_CFG(0, 0x1b, 0x04a190f0), + AZALIA_PIN_CFG(0, 0x1c, 0x612140f0), + AZALIA_PIN_CFG(0, 0x1d, 0x601700f0), + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1f, 0x901701f0), + AZALIA_PIN_CFG(0, 0x1B, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x23, 0x90a601f0), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c new file mode 100644 index 0000000000..4364dd1519 --- /dev/null +++ b/src/mainboard/51nb/x210/mainboard.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void mainboard_enable(struct device *dev) +{ + /* Route 0x4e/4f to LPC */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c new file mode 100644 index 0000000000..4ef10248c9 --- /dev/null +++ b/src/mainboard/51nb/x210/romstage.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} From 6d6fb6bdd2c3fe5f198bb37c51609b4768c7fd74 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 26 Feb 2020 12:55:49 -0600 Subject: [PATCH 0453/1463] mb/51nb/x210: add libgfxinit support Derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Test: build/boot x210, test eDP, MiniDP, VGA outputs Change-Id: Ie2b79b236a458ebd243c992d6e615e41930eeb50 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39106 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/mainboard/51nb/x210/Kconfig | 1 + src/mainboard/51nb/x210/Makefile.inc | 1 + src/mainboard/51nb/x210/devicetree.cb | 7 +++++++ src/mainboard/51nb/x210/gma-mainboard.ads | 18 ++++++++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 src/mainboard/51nb/x210/gma-mainboard.ads diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig index 70b3da86f9..44c0f862c5 100644 --- a/src/mainboard/51nb/x210/Kconfig +++ b/src/mainboard/51nb/x210/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_51NB_NPCE985LA0DX select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_KABYLAKE select SPD_READ_BY_WORD diff --git a/src/mainboard/51nb/x210/Makefile.inc b/src/mainboard/51nb/x210/Makefile.inc index 6555e990e6..9121ccffc4 100644 --- a/src/mainboard/51nb/x210/Makefile.inc +++ b/src/mainboard/51nb/x210/Makefile.inc @@ -2,3 +2,4 @@ # This file is part of the coreboot project. ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 7ee3b2c87e..6bfbe1d879 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -1,5 +1,12 @@ chip soc/intel/skylake + # Enable Panel as eDP and configure power delays + register "gpu_pp_up_delay_ms" = "210" # T3 + register "gpu_pp_down_delay_ms" = "500" # T10 + register "gpu_pp_cycle_delay_ms" = "5000" # T12 + register "gpu_pp_backlight_on_delay_ms" = "1" # T7 + register "gpu_pp_backlight_off_delay_ms" = "200" # T9 + # Enable deep Sx states register "deep_s3_enable_ac" = "1" register "deep_s3_enable_dc" = "1" diff --git a/src/mainboard/51nb/x210/gma-mainboard.ads b/src/mainboard/51nb/x210/gma-mainboard.ads new file mode 100644 index 0000000000..f012560f6c --- /dev/null +++ b/src/mainboard/51nb/x210/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + eDP, + Others => Disabled); + +end GMA.Mainboard; From 75afc79aae192629c66e0472a6f365f566be8412 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 26 Feb 2020 13:06:01 -0600 Subject: [PATCH 0454/1463] mb/51nb/x210: update devicetree - Add USB ports for SD card reader, fingerprint reader, and internal port. - Enable PcieRpClkReqSupport on NVMe root port, correct values for ClkReq/ClkSrc. - Improve comment for M.2-2230 USB port (BT) Parts derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39143 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/mainboard/51nb/x210/devicetree.cb | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 6bfbe1d879..ee6e5ffd59 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -99,17 +99,20 @@ chip soc/intel/skylake register "PcieRpLtrEnable[3]" = "1" register "PcieRpEnable[8]" = "1" # NVMe controller - register "PcieRpClkReqSupport[8]" = "0" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # M.2-2230 USB (BT) register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) From 01b6b245f00a3fb498f43c8d59e144c86a51c84a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 26 Feb 2020 13:10:17 -0600 Subject: [PATCH 0455/1463] mb/51nb/x210: correct battery ACPI The X210 EC reports battery values in broken mAh. These have to be adjusted by 10000 * DGVO, as documented in https://github.com/torvalds/linux/blob/master/drivers/acpi/battery.c. Taken from https://github.com/harrykipper/coreboot, commits 2f68f138adb25605e5715896636cf33f6de5bd95 c1c72cc43708a6647f263a767c39cf3072908e20 Change-Id: Ie097272443b18b16c3937034f874d3b5a6bdd62a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39142 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/acpi/battery.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl index 9064ad5cee..25a2b01928 100644 --- a/src/mainboard/51nb/x210/acpi/battery.asl +++ b/src/mainboard/51nb/x210/acpi/battery.asl @@ -38,16 +38,16 @@ Device (BAT) Method (_BIF, 0, Serialized) { /* Design Capacity */ - Store (DGCP, Index (PBIF, 1)) + Store (DGCP * 10000 / DGVO, Index (PBIF, 1)) /* Last Full Charge Capacity */ - Store (FLCP, Index (PBIF, 2)) + Store (FLCP * 10000 / DGVO, Index (PBIF, 2)) /* Design Voltage */ Store (DGVO, Index (PBIF, 4)) /* Design Capacity of Warning */ - Store (BDW, Index (PBIF, 5)) + Store (BDW * 10000 / DGVO, Index (PBIF, 5)) /* Design Capacity of Low */ Store (BDL, Index (PBIF, 6)) @@ -81,7 +81,7 @@ Device (BAT) /* * 2: BATTERY REMAINING CAPACITY */ - Store (BRC, Index (PBST, 2)) + Store (BRC * 10000 / DGVO, Index (PBST, 2)) /* * 3: BATTERY PRESENT VOLTAGE From 0d1366dedcba06264c7215de9f0aac10c7b02f8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 14 Mar 2020 22:39:30 +0100 Subject: [PATCH 0456/1463] util/inteltool: add 6th gen. mobile core u/y series MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the 6th gen. mobile core u/y series. Change-Id: I7d802452353afe568e3880765dcd340f0437b392 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39568 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/inteltool/inteltool.c | 4 ++++ util/inteltool/inteltool.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index c20aafe601..d51767c9fa 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -130,6 +130,10 @@ static const struct { "6th generation (Skylake-S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E, "6th generation (Skylake family) Core Processor Xeon E (Server)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U, + "6th generation (Skylake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y, + "6th generation (Skylake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1c1841c2de..950943f234 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -284,6 +284,8 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ From e7a5062997011d4cc9eb2b95ffe74b9ff75d7a48 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 15 Mar 2020 09:43:31 -0600 Subject: [PATCH 0457/1463] util/crossgcc: Temporarily disable GDB build test on server The latest debian builder image doesn't compile GDB correctly. Disable the build test until I can get it working again. Signed-off-by: Martin Roth Change-Id: I7852a39ed40a7364d24d0bbf014fd25058491083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39575 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- util/crossgcc/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 108612fd0a..ed8d66e410 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -79,7 +79,9 @@ endif # ifeq ($(COMPILER_OUT_OF_DATE),1) # This target controls what the jenkins builder tests jenkins-build-toolchain: BUILDGCC_OPTIONS ?= -y --nocolor jenkins-build-toolchain: - $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' + $(MAKE) crossgcc clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' + #TODO: Re-enable gdb build after the builders can build it again. + #$(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' rm -f .xcompile PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does -cat .xcompile From 6b88f90f06c81ff8849511be1ba63c5faff56f1a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 15 Mar 2020 07:29:14 +0100 Subject: [PATCH 0458/1463] Revert "crossgcc: Upgrade GCC to 9.2.0" Revert the upgrade as it breaks at least the devicetree parser on aarch64, tested on qemu aarch64 target. This reverts commit dfd3f211740be4cf0d234bf4621ac384758a24ce. Change-Id: I65607817188db21533014caa6d15be9a2004d498 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/crossgcc/buildgcc | 2 +- ...ch => gcc-8.3.0_ada-musl_workaround.patch} | 0 .../patches/gcc-8.3.0_gnat-bad_constant.patch | 150 + ...-9.2.0_gnat.patch => gcc-8.3.0_gnat.patch} | 0 ....0_libgcc.patch => gcc-8.3.0_libgcc.patch} | 0 .../patches/gcc-8.3.0_nds32_ite.patch | 21019 ++++++++++++++++ util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum | 1 + util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum | 1 - util/xcompile/xcompile | 4 +- 9 files changed, 21174 insertions(+), 3 deletions(-) rename util/crossgcc/patches/{gcc-9.2.0_ada-musl_workaround.patch => gcc-8.3.0_ada-musl_workaround.patch} (100%) create mode 100644 util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch rename util/crossgcc/patches/{gcc-9.2.0_gnat.patch => gcc-8.3.0_gnat.patch} (100%) rename util/crossgcc/patches/{gcc-9.2.0_libgcc.patch => gcc-8.3.0_libgcc.patch} (100%) create mode 100644 util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch create mode 100644 util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum delete mode 100644 util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9920799796..150e616652 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -50,7 +50,7 @@ THREADS=1 GMP_VERSION=6.1.2 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 -GCC_VERSION=9.2.0 +GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 diff --git a/util/crossgcc/patches/gcc-9.2.0_ada-musl_workaround.patch b/util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch similarity index 100% rename from util/crossgcc/patches/gcc-9.2.0_ada-musl_workaround.patch rename to util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch diff --git a/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch b/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch new file mode 100644 index 0000000000..e98f933a13 --- /dev/null +++ b/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch @@ -0,0 +1,150 @@ +commit b6f742f96c62bab0582021455328ae3be58e16d3 +Author: pmderodat +Date: Fri May 25 09:05:10 2018 +0000 + + [Ada] Remove "constant" attribute on Osint.Unknown_Attributes + + 2018-05-25 Arnaud Charlet + + gcc/ada/ + + * exp_aggr.adb (Convert_To_Positional): Bump default for + Max_Others_Replicate to 32. Update comments. + * osint.ads (Unknown_Attributes): No longer pretend this is a constant. + (No_File_Info_Cache): Initialize separately. + * osint.adb (No_File_Info_Cache): Update initializer. + + git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260739 138bc75d-0d04-0410-961f-82ee72b054a4 + +diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog +index e4127e472aa..d56240b7b82 100644 +--- a/gcc/ada/ChangeLog ++++ b/gcc/ada/ChangeLog +@@ -188,6 +188,14 @@ + an allocator if the type is an unconstrained record type with default + discriminant. + ++2018-05-25 Arnaud Charlet ++ ++ * exp_aggr.adb (Convert_To_Positional): Bump default for ++ Max_Others_Replicate to 32. Update comments. ++ * osint.ads (Unknown_Attributes): No longer pretend this is a constant. ++ (No_File_Info_Cache): Initialize separately. ++ * osint.adb (No_File_Info_Cache): Update initializer. ++ + 2018-05-04 John Marino + + PR ada/85635 +diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb +index f723c1b4d99..ff5210eb4e4 100644 +--- a/gcc/ada/exp_aggr.adb ++++ b/gcc/ada/exp_aggr.adb +@@ -284,14 +284,14 @@ package body Exp_Aggr is + + procedure Convert_To_Positional + (N : Node_Id; +- Max_Others_Replicate : Nat := 5; ++ Max_Others_Replicate : Nat := 32; + Handle_Bit_Packed : Boolean := False); + -- If possible, convert named notation to positional notation. This + -- conversion is possible only in some static cases. If the conversion is + -- possible, then N is rewritten with the analyzed converted aggregate. + -- The parameter Max_Others_Replicate controls the maximum number of + -- values corresponding to an others choice that will be converted to +- -- positional notation (the default of 5 is the normal limit, and reflects ++ -- positional notation (the default of 32 is the normal limit, and reflects + -- the fact that normally the loop is better than a lot of separate + -- assignments). Note that this limit gets overridden in any case if + -- either of the restrictions No_Elaboration_Code or No_Implicit_Loops is +@@ -301,11 +301,6 @@ package body Exp_Aggr is + -- Packed_Array_Aggregate_Handled, we set this parameter to True, since + -- these are cases we handle in there. + +- -- It would seem useful to have a higher default for Max_Others_Replicate, +- -- but aggregates in the compiler make this impossible: the compiler +- -- bootstrap fails if Max_Others_Replicate is greater than 25. This +- -- is unexpected ??? +- + procedure Expand_Array_Aggregate (N : Node_Id); + -- This is the top-level routine to perform array aggregate expansion. + -- N is the N_Aggregate node to be expanded. +@@ -4292,7 +4287,7 @@ package body Exp_Aggr is + + procedure Convert_To_Positional + (N : Node_Id; +- Max_Others_Replicate : Nat := 5; ++ Max_Others_Replicate : Nat := 32; + Handle_Bit_Packed : Boolean := False) + is + Typ : constant Entity_Id := Etype (N); +diff --git a/gcc/ada/osint.adb b/gcc/ada/osint.adb +index 0c23761b6dc..896fbc7ee37 100644 +--- a/gcc/ada/osint.adb ++++ b/gcc/ada/osint.adb +@@ -250,8 +250,7 @@ package body Osint is + Attr : aliased File_Attributes; + end record; + +- No_File_Info_Cache : constant File_Info_Cache := +- (No_File, Unknown_Attributes); ++ No_File_Info_Cache : constant File_Info_Cache := (No_File, (others => 0)); + + package File_Name_Hash_Table is new GNAT.HTable.Simple_HTable ( + Header_Num => File_Hash_Num, +diff --git a/gcc/ada/osint.ads b/gcc/ada/osint.ads +index 65a87fe4ce3..6c75b521456 100644 +--- a/gcc/ada/osint.ads ++++ b/gcc/ada/osint.ads +@@ -255,10 +255,26 @@ package Osint is + -- from the disk and then cached in the File_Attributes parameter (possibly + -- along with other values). + +- type File_Attributes is private; +- Unknown_Attributes : constant File_Attributes; ++ File_Attributes_Size : constant Natural := 32; ++ -- This should be big enough to fit a "struct file_attributes" on any ++ -- system. It doesn't cause any malfunction if it is too big (which avoids ++ -- the need for either mapping the struct exactly or importing the sizeof ++ -- from C, which would result in dynamic code). However, it does waste ++ -- space (e.g. when a component of this type appears in a record, if it is ++ -- unnecessarily large). Note: for runtime units, use System.OS_Constants. ++ -- SIZEOF_struct_file_attributes instead, which has the exact value. ++ ++ type File_Attributes is ++ array (1 .. File_Attributes_Size) ++ of System.Storage_Elements.Storage_Element; ++ for File_Attributes'Alignment use Standard'Maximum_Alignment; ++ ++ Unknown_Attributes : File_Attributes; + -- A cache for various attributes for a file (length, accessibility,...) +- -- This must be initialized to Unknown_Attributes prior to the first call. ++ -- Will be initialized properly at elaboration (for efficiency later on, ++ -- avoid function calls every time we want to reset the attributes) prior ++ -- to the first usage. We cannot make it constant since the compiler may ++ -- put it in a read-only section. + + function Is_Directory + (Name : C_File_Name; +@@ -754,22 +770,4 @@ private + -- detected, the file being written is deleted, and a fatal error is + -- signalled. + +- File_Attributes_Size : constant Natural := 32; +- -- This should be big enough to fit a "struct file_attributes" on any +- -- system. It doesn't cause any malfunction if it is too big (which avoids +- -- the need for either mapping the struct exactly or importing the sizeof +- -- from C, which would result in dynamic code). However, it does waste +- -- space (e.g. when a component of this type appears in a record, if it is +- -- unnecessarily large). Note: for runtime units, use System.OS_Constants. +- -- SIZEOF_struct_file_attributes instead, which has the exact value. +- +- type File_Attributes is +- array (1 .. File_Attributes_Size) +- of System.Storage_Elements.Storage_Element; +- for File_Attributes'Alignment use Standard'Maximum_Alignment; +- +- Unknown_Attributes : constant File_Attributes := (others => 0); +- -- Will be initialized properly at elaboration (for efficiency later on, +- -- avoid function calls every time we want to reset the attributes). +- + end Osint; diff --git a/util/crossgcc/patches/gcc-9.2.0_gnat.patch b/util/crossgcc/patches/gcc-8.3.0_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-9.2.0_gnat.patch rename to util/crossgcc/patches/gcc-8.3.0_gnat.patch diff --git a/util/crossgcc/patches/gcc-9.2.0_libgcc.patch b/util/crossgcc/patches/gcc-8.3.0_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-9.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-8.3.0_libgcc.patch diff --git a/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch b/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch new file mode 100644 index 0000000000..2f0780be7f --- /dev/null +++ b/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch @@ -0,0 +1,21019 @@ +diff -urN gcc-8.2.0.orig/gcc/common/config/nds32/nds32-common.c gcc-8.2.0/gcc/common/config/nds32/nds32-common.c +--- gcc-8.2.0.orig/gcc/common/config/nds32/nds32-common.c 2018-04-06 07:51:33.000000000 +0200 ++++ gcc-8.2.0/gcc/common/config/nds32/nds32-common.c 2019-01-25 15:38:32.817242625 +0100 +@@ -53,6 +53,16 @@ + + return true; + ++ case OPT_misr_secure_: ++ /* Check the valid security level: 0 1 2 3. */ ++ if (value < 0 || value > 3) ++ { ++ error_at (loc, "for the option -misr-secure=X, the valid X " ++ "must be: 0, 1, 2, or 3"); ++ return false; ++ } ++ return true; ++ + case OPT_mcache_block_size_: + /* Check valid value: 4 8 16 32 64 128 256 512. */ + if (exact_log2 (value) < 2 || exact_log2 (value) > 9) +@@ -74,12 +84,19 @@ + /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ + static const struct default_options nds32_option_optimization_table[] = + { ++#if TARGET_LINUX_ABI == 0 ++ /* Disable -fdelete-null-pointer-checks by default in ELF toolchain. */ ++ { OPT_LEVELS_ALL, OPT_fdelete_null_pointer_checks, ++ NULL, 0 }, ++#endif + /* Enable -fsched-pressure by default at -O1 and above. */ + { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 }, + /* Enable -fomit-frame-pointer by default at all optimization levels. */ + { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 1 }, + /* Enable -mrelax-hint by default at all optimization levels. */ + { OPT_LEVELS_ALL, OPT_mrelax_hint, NULL, 1 }, ++ /* Enalbe -malways-align by default at -O1 and above, but not -Os or -Og. */ ++ { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_malways_align, NULL, 1 }, + /* Enable -mv3push by default at -Os, but it is useless under V2 ISA. */ + { OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 }, + +@@ -87,6 +104,19 @@ + }; + + /* ------------------------------------------------------------------------ */ ++ ++/* Implement TARGET_EXCEPT_UNWIND_INFO. */ ++static enum unwind_info_type ++nds32_except_unwind_info (struct gcc_options *opts ATTRIBUTE_UNUSED) ++{ ++ if (TARGET_LINUX_ABI) ++ return UI_DWARF2; ++ ++ return UI_SJLJ; ++} ++ ++/* ------------------------------------------------------------------------ */ ++ + + /* Run-time Target Specification. */ + +@@ -103,6 +133,7 @@ + TARGET_EXT_PERF : Generate performance extention instrcution. + TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution. + TARGET_EXT_STRING : Generate string extention instrcution. ++ TARGET_HW_ABS : Generate hardware abs instruction. + TARGET_CMOV : Generate conditional move instruction. */ + #undef TARGET_DEFAULT_TARGET_FLAGS + #define TARGET_DEFAULT_TARGET_FLAGS \ +@@ -113,6 +144,7 @@ + | MASK_EXT_PERF \ + | MASK_EXT_PERF2 \ + | MASK_EXT_STRING \ ++ | MASK_HW_ABS \ + | MASK_CMOV) + + #undef TARGET_HANDLE_OPTION +@@ -125,7 +157,7 @@ + /* Defining the Output Assembler Language. */ + + #undef TARGET_EXCEPT_UNWIND_INFO +-#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info ++#define TARGET_EXCEPT_UNWIND_INFO nds32_except_unwind_info + + /* ------------------------------------------------------------------------ */ + +diff -urN gcc-8.2.0.orig/gcc/config/nds32/constants.md gcc-8.2.0/gcc/config/nds32/constants.md +--- gcc-8.2.0.orig/gcc/config/nds32/constants.md 2018-04-22 09:46:39.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/constants.md 2019-01-25 15:38:32.821242637 +0100 +@@ -23,6 +23,7 @@ + (define_constants + [(R8_REGNUM 8) + (TA_REGNUM 15) ++ (TP_REGNUM 25) + (FP_REGNUM 28) + (GP_REGNUM 29) + (LP_REGNUM 30) +@@ -49,6 +50,16 @@ + UNSPEC_FFB + UNSPEC_FFMISM + UNSPEC_FLMISM ++ UNSPEC_KDMBB ++ UNSPEC_KDMBT ++ UNSPEC_KDMTB ++ UNSPEC_KDMTT ++ UNSPEC_KHMBB ++ UNSPEC_KHMBT ++ UNSPEC_KHMTB ++ UNSPEC_KHMTT ++ UNSPEC_KSLRAW ++ UNSPEC_KSLRAWU + UNSPEC_SVA + UNSPEC_SVS + UNSPEC_WSBH +@@ -62,6 +73,29 @@ + UNSPEC_UASTORE_HW + UNSPEC_UASTORE_W + UNSPEC_UASTORE_DW ++ UNSPEC_GOTINIT ++ UNSPEC_GOT ++ UNSPEC_GOTOFF ++ UNSPEC_PLT ++ UNSPEC_TLSGD ++ UNSPEC_TLSLD ++ UNSPEC_TLSIE ++ UNSPEC_TLSLE ++ UNSPEC_ROUND ++ UNSPEC_VEC_COMPARE ++ UNSPEC_KHM ++ UNSPEC_KHMX ++ UNSPEC_CLIP_OV ++ UNSPEC_CLIPS_OV ++ UNSPEC_BITREV ++ UNSPEC_KABS ++ UNSPEC_LOOP_END ++ UNSPEC_TLS_DESC ++ UNSPEC_TLS_IE ++ UNSPEC_ADD32 ++ UNSPEC_ICT ++ UNSPEC_KADDH ++ UNSPEC_KSUBH + ]) + + ;; The unspec_volatile operation index. +@@ -135,10 +169,14 @@ + UNSPEC_VOLATILE_SET_TRIG_EDGE + UNSPEC_VOLATILE_GET_TRIG_TYPE + UNSPEC_VOLATILE_RELAX_GROUP ++ UNSPEC_VOLATILE_OMIT_FP_BEGIN ++ UNSPEC_VOLATILE_OMIT_FP_END + UNSPEC_VOLATILE_POP25_RETURN + UNSPEC_VOLATILE_UNALIGNED_FEATURE + UNSPEC_VOLATILE_ENABLE_UNALIGNED + UNSPEC_VOLATILE_DISABLE_UNALIGNED ++ UNSPEC_VOLATILE_RDOV ++ UNSPEC_VOLATILE_CLROV + ]) + + ;; ------------------------------------------------------------------------ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/constraints.md gcc-8.2.0/gcc/config/nds32/constraints.md +--- gcc-8.2.0.orig/gcc/config/nds32/constraints.md 2018-04-06 07:51:33.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/constraints.md 2019-01-25 15:38:32.821242637 +0100 +@@ -127,6 +127,11 @@ + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -31, 0)"))) + ++(define_constraint "Iu06" ++ "Unsigned immediate 6-bit value" ++ (and (match_code "const_int") ++ (match_test "ival < (1 << 6) && ival >= 0"))) ++ + ;; Ip05 is special and dedicated for v3 movpi45 instruction. + ;; movpi45 has imm5u field but the range is 16 ~ 47. + (define_constraint "Ip05" +@@ -136,10 +141,10 @@ + && ival >= (0 + 16) + && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) + +-(define_constraint "Iu06" ++(define_constraint "IU06" + "Unsigned immediate 6-bit value constraint for addri36.sp instruction" + (and (match_code "const_int") +- (match_test "ival < (1 << 6) ++ (match_test "ival < (1 << 8) + && ival >= 0 + && (ival % 4 == 0) + && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) +@@ -302,6 +307,25 @@ + (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M) + && (IN_RANGE (exact_log2 (ival + 1), 1, 8))"))) + ++(define_constraint "CVp5" ++ "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47" ++ (and (match_code "const_vector") ++ (match_test "nds32_valid_CVp5_p (op)"))) ++ ++(define_constraint "CVs5" ++ "Signed immediate 5-bit value" ++ (and (match_code "const_vector") ++ (match_test "nds32_valid_CVs5_p (op)"))) ++ ++(define_constraint "CVs2" ++ "Signed immediate 20-bit value" ++ (and (match_code "const_vector") ++ (match_test "nds32_valid_CVs2_p (op)"))) ++ ++(define_constraint "CVhi" ++ "The immediate value that can be simply set high 20-bit" ++ (and (match_code "const_vector") ++ (match_test "nds32_valid_CVhi_p (op)"))) + + (define_memory_constraint "U33" + "Memory constraint for 333 format" +@@ -349,4 +373,9 @@ + (match_test "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) + && nds32_float_mem_operand_p (op)"))) + ++(define_constraint "S" ++ "@internal ++ A constant call address." ++ (match_operand 0 "nds32_symbolic_operand")) ++ + ;; ------------------------------------------------------------------------ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/elf.h gcc-8.2.0/gcc/config/nds32/elf.h +--- gcc-8.2.0.orig/gcc/config/nds32/elf.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/elf.h 2019-01-25 15:38:32.821242637 +0100 +@@ -0,0 +1,81 @@ ++/* Definitions of target machine of Andes NDS32 cpu for GNU compiler ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. ++ Contributed by Andes Technology Corporation. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with GCC; see the file COPYING3. If not see ++ . */ ++ ++ ++/* ------------------------------------------------------------------------ */ ++ ++#define TARGET_LINUX_ABI 0 ++ ++/* In the configure stage we may use options --enable-default-relax, ++ --enable-Os-default-ifc and --enable-Os-default-ex9. They effect ++ the default spec of passing --relax, --mifc, and --mex9 to linker. ++ We use NDS32_RELAX_SPEC, NDS32_IFC_SPEC, and NDS32_EX9_SPEC ++ so that we can customize them conveniently. */ ++#define LINK_SPEC \ ++ " %{G*}" \ ++ " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ ++ " %{shared:-shared}" \ ++ NDS32_RELAX_SPEC ++ ++#define LIB_SPEC \ ++ " -lc -lgloss" ++ ++#define LIBGCC_SPEC \ ++ " -lgcc" ++ ++/* The option -mno-ctor-dtor can disable constructor/destructor feature ++ by applying different crt stuff. In the convention, crt0.o is the ++ startup file without constructor/destructor; ++ crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the ++ startup files with constructor/destructor. ++ Note that crt0.o, crt1.o, crti.o, and crtn.o are provided ++ by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are ++ currently provided by GCC for nds32 target. ++ ++ For nds32 target so far: ++ If -mno-ctor-dtor, we are going to link ++ "crt0.o [user objects]". ++ If -mctor-dtor, we are going to link ++ "crt1.o crtbegin1.o [user objects] crtend1.o". ++ ++ Note that the TARGET_DEFAULT_CTOR_DTOR would effect the ++ default behavior. Check gcc/config.gcc for more information. */ ++#ifdef TARGET_DEFAULT_CTOR_DTOR ++ #define STARTFILE_SPEC \ ++ " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ ++ " %{!mno-ctor-dtor:crtbegin1.o%s}" \ ++ " %{mcrt-arg:crtarg.o%s}" ++ #define ENDFILE_SPEC \ ++ " %{!mno-ctor-dtor:crtend1.o%s}" ++#else ++ #define STARTFILE_SPEC \ ++ " %{mctor-dtor|coverage:crt1.o%s;:crt0.o%s}" \ ++ " %{mctor-dtor|coverage:crtbegin1.o%s}" \ ++ " %{mcrt-arg:crtarg.o%s}" ++ #define ENDFILE_SPEC \ ++ " %{mctor-dtor|coverage:crtend1.o%s}" ++#endif ++ ++#define STARTFILE_CXX_SPEC \ ++ " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ ++ " %{!mno-ctor-dtor:crtbegin1.o%s}" \ ++ " %{mcrt-arg:crtarg.o%s}" ++#define ENDFILE_CXX_SPEC \ ++ " %{!mno-ctor-dtor:crtend1.o%s}" +diff -urN gcc-8.2.0.orig/gcc/config/nds32/iterators.md gcc-8.2.0/gcc/config/nds32/iterators.md +--- gcc-8.2.0.orig/gcc/config/nds32/iterators.md 2018-04-06 07:51:33.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/iterators.md 2019-01-25 15:38:32.821242637 +0100 +@@ -68,6 +68,28 @@ + ;; shifts + (define_code_iterator shift_rotate [ashift ashiftrt lshiftrt rotatert]) + ++(define_code_iterator shifts [ashift ashiftrt lshiftrt]) ++ ++(define_code_iterator shiftrt [ashiftrt lshiftrt]) ++ ++(define_code_iterator sat_plus [ss_plus us_plus]) ++ ++(define_code_iterator all_plus [plus ss_plus us_plus]) ++ ++(define_code_iterator sat_minus [ss_minus us_minus]) ++ ++(define_code_iterator all_minus [minus ss_minus us_minus]) ++ ++(define_code_iterator plus_minus [plus minus]) ++ ++(define_code_iterator extend [sign_extend zero_extend]) ++ ++(define_code_iterator sumax [smax umax]) ++ ++(define_code_iterator sumin [smin umin]) ++ ++(define_code_iterator sumin_max [smax umax smin umin]) ++ + ;;---------------------------------------------------------------------------- + ;; Code attributes. + ;;---------------------------------------------------------------------------- +@@ -76,5 +98,23 @@ + (define_code_attr shift + [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr") (rotatert "rotr")]) + ++(define_code_attr su ++ [(ashiftrt "") (lshiftrt "u") (sign_extend "s") (zero_extend "u")]) ++ ++(define_code_attr zs ++ [(sign_extend "s") (zero_extend "z")]) ++ ++(define_code_attr uk ++ [(plus "") (ss_plus "k") (us_plus "uk") ++ (minus "") (ss_minus "k") (us_minus "uk")]) ++ ++(define_code_attr opcode ++ [(plus "add") (minus "sub") (smax "smax") (umax "umax") (smin "smin") (umin "umin")]) ++ ++(define_code_attr add_rsub ++ [(plus "a") (minus "rs")]) ++ ++(define_code_attr add_sub ++ [(plus "a") (minus "s")]) + + ;;---------------------------------------------------------------------------- +diff -urN gcc-8.2.0.orig/gcc/config/nds32/linux.h gcc-8.2.0/gcc/config/nds32/linux.h +--- gcc-8.2.0.orig/gcc/config/nds32/linux.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/linux.h 2019-01-25 15:38:32.821242637 +0100 +@@ -0,0 +1,86 @@ ++/* Definitions of target machine of Andes NDS32 cpu for GNU compiler ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. ++ Contributed by Andes Technology Corporation. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with GCC; see the file COPYING3. If not see ++ . */ ++ ++ ++/* ------------------------------------------------------------------------ */ ++ ++#define TARGET_LINUX_ABI 1 ++ ++#undef SIZE_TYPE ++#define SIZE_TYPE "unsigned int" ++ ++#undef PTRDIFF_TYPE ++#define PTRDIFF_TYPE "int" ++ ++#define TARGET_OS_CPP_BUILTINS() \ ++ do \ ++ { \ ++ GNU_USER_TARGET_OS_CPP_BUILTINS(); \ ++ } \ ++ while (0) ++ ++#ifdef TARGET_BIG_ENDIAN_DEFAULT ++#define LD_SO_ENDIAN_SPEC "%{mlittle-endian:le}%{!mlittle-endian:be}" ++#else ++#define LD_SO_ENDIAN_SPEC "%{mbig-endian:be}%{!mbig-endian:le}" ++#endif ++ ++/* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI, ++ 1 means hard ABI and using full floating-point instruction, ++ 2 means hard ABI and only using single-precision floating-point ++ instruction */ ++#if TARGET_ARCH_DEFAULT ++#define LD_SO_ABI_SPEC "%{!mabi=2:f}" ++#else ++#define LD_SO_ABI_SPEC "%{mabi=2fp+:f}" ++#endif ++ ++#define GLIBC_DYNAMIC_LINKER \ ++ "/lib/ld-linux-nds32" LD_SO_ENDIAN_SPEC LD_SO_ABI_SPEC ".so.1" ++ ++/* In the configure stage we may use options --enable-default-relax, ++ --enable-Os-default-ifc and --enable-Os-default-ex9. They effect ++ the default spec of passing --relax, --mifc, and --mex9 to linker. ++ We use NDS32_RELAX_SPEC, NDS32_IFC_SPEC, and NDS32_EX9_SPEC ++ so that we can customize them conveniently. */ ++#define LINK_SPEC \ ++ " %{G*}" \ ++ " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ ++ " %{shared:-shared} \ ++ %{!shared: \ ++ %{!static: \ ++ %{rdynamic:-export-dynamic} \ ++ -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \ ++ %{static:-static}}" \ ++ NDS32_RELAX_SPEC ++ ++#define LINK_PIE_SPEC "%{pie:%{!fno-pie:%{!fno-PIE:%{!static:-pie}}}} " ++ ++#define CPP_SPEC "%{pthread:-D_REENTRANT}" ++ ++/* The SYNC operations are implemented as library functions, not ++ INSN patterns. As a result, the HAVE defines for the patterns are ++ not defined. We need to define them to generate the corresponding ++ __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* and __GCC_ATOMIC_*_LOCK_FREE ++ defines. ++ Ref: https://sourceware.org/ml/libc-alpha/2014-09/msg00322.html */ ++#define HAVE_sync_compare_and_swapqi 1 ++#define HAVE_sync_compare_and_swaphi 1 ++#define HAVE_sync_compare_and_swapsi 1 +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.c gcc-8.2.0/gcc/config/nds32/nds32.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32.c 2018-05-07 03:38:02.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32.c 2019-01-25 15:38:32.833242671 +0100 +@@ -305,6 +305,7 @@ + { "nested", 0, 0, false, false, false, false, NULL, NULL }, + { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, + { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, ++ { "critical", 0, 0, false, false, false, false, NULL, NULL }, + + /* The attributes describing isr register save scheme. */ + { "save_all", 0, 0, false, false, false, false, NULL, NULL }, +@@ -314,9 +315,19 @@ + { "nmi", 1, 1, false, false, false, false, NULL, NULL }, + { "warm", 1, 1, false, false, false, false, NULL, NULL }, + ++ /* The attributes describing isr security level. */ ++ { "secure", 1, 1, false, false, false, false, NULL, NULL }, ++ + /* The attribute telling no prologue/epilogue. */ + { "naked", 0, 0, false, false, false, false, NULL, NULL }, + ++ /* The attribute is used to tell this function to be ROM patch. */ ++ { "indirect_call",0, 0, false, false, false, false, NULL, NULL }, ++ ++ /* FOR BACKWARD COMPATIBILITY, ++ this attribute also tells no prologue/epilogue. */ ++ { "no_prologue", 0, 0, false, false, false, false, NULL, NULL }, ++ + /* The last attribute spec is set to be NULL. */ + { NULL, 0, 0, false, false, false, false, NULL, NULL } + }; +@@ -345,6 +356,10 @@ + /* Initially this function is not under strictly aligned situation. */ + machine->strict_aligned_p = 0; + ++ /* Initially this function has no naked and no_prologue attributes. */ ++ machine->attr_naked_p = 0; ++ machine->attr_no_prologue_p = 0; ++ + return machine; + } + +@@ -362,6 +377,15 @@ + needs prologue/epilogue. */ + cfun->machine->naked_p = 0; + ++ /* We need to mark whether this function has naked and no_prologue ++ attribute so that we can distinguish the difference if users applies ++ -mret-in-naked-func option. */ ++ cfun->machine->attr_naked_p ++ = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) ++ ? 1 : 0; ++ cfun->machine->attr_no_prologue_p ++ = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) ++ ? 1 : 0; + + /* If __builtin_eh_return is used, we better have frame pointer needed + so that we can easily locate the stack slot of return address. */ +@@ -432,7 +456,8 @@ + + /* If $gp value is required to be saved on stack, it needs 4 bytes space. + Check whether we are using PIC code genration. */ +- cfun->machine->gp_size = (flag_pic) ? 4 : 0; ++ cfun->machine->gp_size = ++ (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; + + /* If $lp value is required to be saved on stack, it needs 4 bytes space. + Check whether $lp is ever live. */ +@@ -497,7 +522,7 @@ + } + + /* Check if this function can omit prologue/epilogue code fragment. +- If there is 'naked' attribute in this function, ++ If there is 'no_prologue'/'naked'/'secure' attribute in this function, + we can set 'naked_p' flag to indicate that + we do not have to generate prologue/epilogue. + Or, if all the following conditions succeed, +@@ -510,14 +535,17 @@ + is no outgoing size. + condition 3: There is no local_size, which means + we do not need to adjust $sp. */ +- if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) ++ if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) ++ || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) ++ || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl)) + || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM + && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM + && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM + && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM + && !df_regs_ever_live_p (FP_REGNUM) + && !df_regs_ever_live_p (LP_REGNUM) +- && cfun->machine->local_size == 0)) ++ && cfun->machine->local_size == 0 ++ && !flag_pic)) + { + /* Set this function 'naked_p' and other functions can check this flag. + Note that in nds32 port, the 'naked_p = 1' JUST means there is no +@@ -1259,6 +1287,32 @@ + REG_NOTES (parallel_insn) = dwarf; + } + ++static void ++nds32_emit_load_gp (void) ++{ ++ rtx got_symbol, pat; ++ ++ /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ ++ emit_insn (gen_blockage ()); ++ ++ got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); ++ /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */ ++ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); ++ pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8))); ++ emit_insn (gen_sethi (pic_offset_table_rtx,pat)); ++ ++ /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */ ++ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); ++ pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4))); ++ emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat)); ++ ++ /* add5.pc $gp */ ++ emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx)); ++ ++ /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ ++ emit_insn (gen_blockage ()); ++} ++ + /* Function that may creates more instructions + for large value on adjusting stack pointer. + +@@ -1342,17 +1396,25 @@ + } + + /* Return true if FUNC is a naked function. */ +-static bool ++bool + nds32_naked_function_p (tree func) + { +- tree t; ++ /* FOR BACKWARD COMPATIBILITY, ++ we need to support 'no_prologue' attribute as well. */ ++ tree t_naked; ++ tree t_no_prologue; + + if (TREE_CODE (func) != FUNCTION_DECL) + abort (); + +- t = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); ++ /* We have to use lookup_attribute() to check attributes. ++ Because attr_naked_p and attr_no_prologue_p are set in ++ nds32_compute_stack_frame() and the function has not been ++ invoked yet. */ ++ t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); ++ t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func)); + +- return (t != NULL_TREE); ++ return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE)); + } + + /* Function that determine whether a load postincrement is a good thing to use +@@ -1570,6 +1632,11 @@ + nds32_register_passes (void) + { + nds32_register_pass ( ++ make_pass_nds32_fp_as_gp, ++ PASS_POS_INSERT_BEFORE, ++ "ira"); ++ ++ nds32_register_pass ( + make_pass_nds32_relax_opt, + PASS_POS_INSERT_AFTER, + "mach"); +@@ -1636,6 +1703,9 @@ + { + int regno; + ++ if (TARGET_LINUX_ABI) ++ fixed_regs[TP_REGNUM] = 1; ++ + if (TARGET_HARD_FLOAT) + { + for (regno = NDS32_FIRST_FPR_REGNUM; +@@ -1987,6 +2057,16 @@ + : PARM_BOUNDARY); + } + ++bool ++nds32_vector_mode_supported_p (machine_mode mode) ++{ ++ if (mode == V4QImode ++ || mode == V2HImode) ++ return NDS32_EXT_DSP_P (); ++ ++ return false; ++} ++ + /* -- How Scalar Function Values Are Returned. */ + + static rtx +@@ -2124,56 +2204,12 @@ + nds32_asm_function_end_prologue (FILE *file) + { + fprintf (file, "\t! END PROLOGUE\n"); +- +- /* If frame pointer is NOT needed and -mfp-as-gp is issued, +- we can generate special directive: ".omit_fp_begin" +- to guide linker doing fp-as-gp optimization. +- However, for a naked function, which means +- it should not have prologue/epilogue, +- using fp-as-gp still requires saving $fp by push/pop behavior and +- there is no benefit to use fp-as-gp on such small function. +- So we need to make sure this function is NOT naked as well. */ +- if (!frame_pointer_needed +- && !cfun->machine->naked_p +- && cfun->machine->fp_as_gp_p) +- { +- fprintf (file, "\t! ----------------------------------------\n"); +- fprintf (file, "\t! Guide linker to do " +- "link time optimization: fp-as-gp\n"); +- fprintf (file, "\t! We add one more instruction to " +- "initialize $fp near to $gp location.\n"); +- fprintf (file, "\t! If linker fails to use fp-as-gp transformation,\n"); +- fprintf (file, "\t! this extra instruction should be " +- "eliminated at link stage.\n"); +- fprintf (file, "\t.omit_fp_begin\n"); +- fprintf (file, "\tla\t$fp,_FP_BASE_\n"); +- fprintf (file, "\t! ----------------------------------------\n"); +- } + } + + /* Before rtl epilogue has been expanded, this function is used. */ + static void + nds32_asm_function_begin_epilogue (FILE *file) + { +- /* If frame pointer is NOT needed and -mfp-as-gp is issued, +- we can generate special directive: ".omit_fp_end" +- to claim fp-as-gp optimization range. +- However, for a naked function, +- which means it should not have prologue/epilogue, +- using fp-as-gp still requires saving $fp by push/pop behavior and +- there is no benefit to use fp-as-gp on such small function. +- So we need to make sure this function is NOT naked as well. */ +- if (!frame_pointer_needed +- && !cfun->machine->naked_p +- && cfun->machine->fp_as_gp_p) +- { +- fprintf (file, "\t! ----------------------------------------\n"); +- fprintf (file, "\t! Claim the range of fp-as-gp " +- "link time optimization\n"); +- fprintf (file, "\t.omit_fp_end\n"); +- fprintf (file, "\t! ----------------------------------------\n"); +- } +- + fprintf (file, "\t! BEGIN EPILOGUE\n"); + } + +@@ -2200,6 +2236,26 @@ + ? 1 + : 0); + ++ if (flag_pic) ++ { ++ fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n"); ++ fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n", ++ reg_names [PIC_OFFSET_TABLE_REGNUM]); ++ fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n", ++ reg_names [PIC_OFFSET_TABLE_REGNUM], ++ reg_names [PIC_OFFSET_TABLE_REGNUM]); ++ ++ if (TARGET_ISA_V3) ++ fprintf (file, "\tadd5.pc\t$gp\n"); ++ else ++ { ++ fprintf (file, "\tmfusr\t$ta, $pc\n"); ++ fprintf (file, "\tadd\t%s, $ta, %s\n", ++ reg_names [PIC_OFFSET_TABLE_REGNUM], ++ reg_names [PIC_OFFSET_TABLE_REGNUM]); ++ } ++ } ++ + if (delta != 0) + { + if (satisfies_constraint_Is15 (GEN_INT (delta))) +@@ -2224,9 +2280,23 @@ + } + } + +- fprintf (file, "\tb\t"); +- assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); +- fprintf (file, "\n"); ++ if (flag_pic) ++ { ++ fprintf (file, "\tla\t$ta, "); ++ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); ++ fprintf (file, "@PLT\n"); ++ fprintf (file, "\t! epilogue\n"); ++ fprintf (file, "\tlwi.bi\t%s, [%s], 4\n", ++ reg_names[PIC_OFFSET_TABLE_REGNUM], ++ reg_names[STACK_POINTER_REGNUM]); ++ fprintf (file, "\tbr\t$ta\n"); ++ } ++ else ++ { ++ fprintf (file, "\tb\t"); ++ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); ++ fprintf (file, "\n"); ++ } + + final_end_function (); + } +@@ -2242,15 +2312,20 @@ + + /* 1. Do not apply sibling call if -mv3push is enabled, + because pop25 instruction also represents return behavior. +- 2. If this function is a variadic function, do not apply sibling call ++ 2. If this function is a isr function, do not apply sibling call ++ because it may perform the behavior that user does not expect. ++ 3. If this function is a variadic function, do not apply sibling call + because the stack layout may be a mess. +- 3. We don't want to apply sibling call optimization for indirect ++ 4. We don't want to apply sibling call optimization for indirect + sibcall because the pop behavior in epilogue may pollute the + content of caller-saved regsiter when the register is used for +- indirect sibcall. */ ++ indirect sibcall. ++ 5. In pic mode, it may use some registers for PLT call. */ + return (!TARGET_V3PUSH ++ && !nds32_isr_function_p (current_function_decl) + && (cfun->machine->va_args_size == 0) +- && decl); ++ && decl ++ && !flag_pic); + } + + /* Determine whether we need to enable warning for function return check. */ +@@ -2566,6 +2641,13 @@ + + case SYMBOL_REF: + /* (mem (symbol_ref A)) => [symbol_ref] */ ++ ++ if (flag_pic || SYMBOL_REF_TLS_MODEL (x)) ++ return false; ++ ++ if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) ++ return false; ++ + /* If -mcmodel=large, the 'symbol_ref' is not a valid address + during or after LRA/reload phase. */ + if (TARGET_CMODEL_LARGE +@@ -2577,7 +2659,8 @@ + the 'symbol_ref' is not a valid address during or after + LRA/reload phase. */ + if (TARGET_CMODEL_MEDIUM +- && NDS32_SYMBOL_REF_RODATA_P (x) ++ && (NDS32_SYMBOL_REF_RODATA_P (x) ++ || CONSTANT_POOL_ADDRESS_P (x)) + && (reload_completed + || reload_in_progress + || lra_in_progress)) +@@ -2599,6 +2682,10 @@ + { + /* Now we see the [ + const_addr ] pattern, but we need + some further checking. */ ++ ++ if (flag_pic || SYMBOL_REF_TLS_MODEL (op0)) ++ return false; ++ + /* If -mcmodel=large, the 'const_addr' is not a valid address + during or after LRA/reload phase. */ + if (TARGET_CMODEL_LARGE +@@ -2675,17 +2762,202 @@ + + case LO_SUM: + /* (mem (lo_sum (reg) (symbol_ref))) */ +- /* (mem (lo_sum (reg) (const))) */ +- gcc_assert (REG_P (XEXP (x, 0))); +- if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF +- || GET_CODE (XEXP (x, 1)) == CONST) +- return nds32_legitimate_address_p (mode, XEXP (x, 1), strict); +- else ++ /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */ ++ /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */ ++ /* The LO_SUM is a valid address if and only if we would like to ++ generate 32-bit full address memory access with any of following ++ circumstance: ++ 1. -mcmodel=large. ++ 2. -mcmodel=medium and the symbol_ref references to rodata. */ ++ { ++ rtx sym = NULL_RTX; ++ ++ if (flag_pic) ++ return false; ++ ++ if (!REG_P (XEXP (x, 0))) ++ return false; ++ ++ if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF) ++ sym = XEXP (x, 1); ++ else if (GET_CODE (XEXP (x, 1)) == CONST) ++ { ++ rtx plus = XEXP(XEXP (x, 1), 0); ++ if (GET_CODE (plus) == PLUS) ++ sym = XEXP (plus, 0); ++ else if (GET_CODE (plus) == UNSPEC) ++ sym = XVECEXP (plus, 0, 0); ++ } ++ else ++ return false; ++ ++ gcc_assert (GET_CODE (sym) == SYMBOL_REF); ++ ++ if (TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (sym)) ++ return true; ++ ++ if (TARGET_CMODEL_LARGE) ++ return true; ++ else if (TARGET_CMODEL_MEDIUM ++ && NDS32_SYMBOL_REF_RODATA_P (sym)) ++ return true; ++ else ++ return false; ++ } ++ ++ default: ++ return false; ++ } ++} ++ ++static rtx ++nds32_legitimize_address (rtx x, ++ rtx oldx ATTRIBUTE_UNUSED, ++ machine_mode mode ATTRIBUTE_UNUSED) ++{ ++ if (nds32_tls_referenced_p (x)) ++ x = nds32_legitimize_tls_address (x); ++ else if (flag_pic && SYMBOLIC_CONST_P (x)) ++ x = nds32_legitimize_pic_address (x); ++ else if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) ++ x = nds32_legitimize_ict_address (x); ++ ++ return x; ++} ++ ++static bool ++nds32_legitimate_constant_p (machine_mode mode, rtx x) ++{ ++ switch (GET_CODE (x)) ++ { ++ case CONST_DOUBLE: ++ if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ++ && (mode == DFmode || mode == SFmode)) + return false; ++ break; ++ case CONST: ++ x = XEXP (x, 0); ++ ++ if (GET_CODE (x) == PLUS) ++ { ++ if (!CONST_INT_P (XEXP (x, 1))) ++ return false; ++ x = XEXP (x, 0); ++ } ++ ++ if (GET_CODE (x) == UNSPEC) ++ { ++ switch (XINT (x, 1)) ++ { ++ case UNSPEC_GOT: ++ case UNSPEC_GOTOFF: ++ case UNSPEC_PLT: ++ case UNSPEC_TLSGD: ++ case UNSPEC_TLSLD: ++ case UNSPEC_TLSIE: ++ case UNSPEC_TLSLE: ++ case UNSPEC_ICT: ++ return false; ++ default: ++ return true; ++ } ++ } ++ break; ++ case SYMBOL_REF: ++ /* TLS symbols need a call to resolve in ++ precompute_register_parameters. */ ++ if (SYMBOL_REF_TLS_MODEL (x)) ++ return false; ++ break; ++ default: ++ return true; ++ } ++ ++ return true; ++} ++ ++/* Reorgnize the UNSPEC CONST and return its direct symbol. */ ++static rtx ++nds32_delegitimize_address (rtx x) ++{ ++ x = delegitimize_mem_from_attrs (x); ++ ++ if (GET_CODE(x) == CONST) ++ { ++ rtx inner = XEXP (x, 0); ++ ++ /* Handle for GOTOFF. */ ++ if (GET_CODE (inner) == PLUS) ++ inner = XEXP (inner, 0); ++ ++ if (GET_CODE (inner) == UNSPEC) ++ { ++ switch (XINT (inner, 1)) ++ { ++ case UNSPEC_GOTINIT: ++ case UNSPEC_GOT: ++ case UNSPEC_GOTOFF: ++ case UNSPEC_PLT: ++ case UNSPEC_TLSGD: ++ case UNSPEC_TLSLD: ++ case UNSPEC_TLSIE: ++ case UNSPEC_TLSLE: ++ case UNSPEC_ICT: ++ x = XVECEXP (inner, 0, 0); ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ return x; ++} + ++static machine_mode ++nds32_vectorize_preferred_simd_mode (scalar_mode mode) ++{ ++ if (!NDS32_EXT_DSP_P ()) ++ return word_mode; ++ ++ switch (mode) ++ { ++ case E_QImode: ++ return V4QImode; ++ case E_HImode: ++ return V2HImode; ++ default: ++ return word_mode; ++ } ++} ++ ++static bool ++nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) ++{ ++ switch (GET_CODE (x)) ++ { ++ case CONST: ++ return !nds32_legitimate_constant_p (mode, x); ++ case SYMBOL_REF: ++ /* All symbols have to be accessed through gp-relative in PIC mode. */ ++ /* We don't want to force symbol as constant pool in .text section, ++ because we use the gp-relatived instruction to load in small ++ or medium model. */ ++ if (flag_pic ++ || SYMBOL_REF_TLS_MODEL (x) ++ || TARGET_CMODEL_SMALL ++ || TARGET_CMODEL_MEDIUM) ++ return true; ++ break; ++ case CONST_INT: ++ case CONST_DOUBLE: ++ if (flag_pic && (lra_in_progress || reload_completed)) ++ return true; ++ break; + default: + return false; + } ++ return false; + } + + +@@ -2731,13 +3003,33 @@ + /* Describing Relative Costs of Operations. */ + + static int +-nds32_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, ++nds32_register_move_cost (machine_mode mode, + reg_class_t from, + reg_class_t to) + { ++ /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ ++ if (TARGET_PIPELINE_GRAYWOLF) ++ { ++ if (GET_MODE_SIZE (mode) == 8) ++ { ++ /* DPR to GPR. */ ++ if (from == FP_REGS && to != FP_REGS) ++ return 3; ++ /* GPR to DPR. */ ++ if (from != FP_REGS && to == FP_REGS) ++ return 2; ++ } ++ else ++ { ++ if ((from == FP_REGS && to != FP_REGS) ++ || (from != FP_REGS && to == FP_REGS)) ++ return 2; ++ } ++ } ++ + if ((from == FP_REGS && to != FP_REGS) + || (from != FP_REGS && to == FP_REGS)) +- return 9; ++ return 3; + else if (from == HIGH_REGS || to == HIGH_REGS) + return optimize_size ? 6 : 2; + else +@@ -2825,6 +3117,9 @@ + { + default_file_start (); + ++ if (flag_pic) ++ fprintf (asm_out_file, "\t.pic\n"); ++ + /* Tell assembler which ABI we are using. */ + fprintf (asm_out_file, "\t! ABI version\n"); + if (TARGET_HARD_FLOAT) +@@ -2835,10 +3130,36 @@ + /* Tell assembler that this asm code is generated by compiler. */ + fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); + fprintf (asm_out_file, "\t.flag\tverbatim\n"); +- /* Give assembler the size of each vector for interrupt handler. */ +- fprintf (asm_out_file, "\t! This vector size directive is required " +- "for checking inconsistency on interrupt handler\n"); +- fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); ++ ++ /* Insert directive for linker to distinguish object's ict flag. */ ++ if (!TARGET_LINUX_ABI) ++ { ++ if (TARGET_ICT_MODEL_LARGE) ++ fprintf (asm_out_file, "\t.ict_model\tlarge\n"); ++ else ++ fprintf (asm_out_file, "\t.ict_model\tsmall\n"); ++ } ++ ++ /* We need to provide the size of each vector for interrupt handler ++ under elf toolchain. */ ++ if (!TARGET_LINUX_ABI) ++ { ++ fprintf (asm_out_file, "\t! This vector size directive is required " ++ "for checking inconsistency on interrupt handler\n"); ++ fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); ++ } ++ ++ /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os, ++ the compiler may produce 'la $fp,_FP_BASE_' instruction ++ at prologue for fp-as-gp optimization. ++ We should emit weak reference of _FP_BASE_ to avoid undefined reference ++ in case user does not pass '--relax' option to linker. */ ++ if (!TARGET_LINUX_ABI && (TARGET_FORCE_FP_AS_GP || optimize_size)) ++ { ++ fprintf (asm_out_file, "\t! This weak reference is required to do " ++ "fp-as-gp link time optimization\n"); ++ fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n"); ++ } + + fprintf (asm_out_file, "\t! ------------------------------------\n"); + +@@ -2849,6 +3170,49 @@ + if (TARGET_ISA_V3M) + fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); + ++ switch (nds32_cpu_option) ++ { ++ case CPU_N6: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N6"); ++ break; ++ ++ case CPU_N7: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N7"); ++ break; ++ ++ case CPU_N8: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8"); ++ break; ++ ++ case CPU_E8: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "E8"); ++ break; ++ ++ case CPU_N9: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N9"); ++ break; ++ ++ case CPU_N10: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10"); ++ break; ++ ++ case CPU_GRAYWOLF: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "Graywolf"); ++ break; ++ ++ case CPU_N12: ++ case CPU_N13: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N13"); ++ break; ++ ++ case CPU_SIMPLE: ++ fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE"); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ + if (TARGET_CMODEL_SMALL) + fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); + if (TARGET_CMODEL_MEDIUM) +@@ -2926,9 +3290,65 @@ + { + nds32_asm_file_end_for_isr (); + ++ /* The NDS32 Linux stack is mapped non-executable by default, so add a ++ .note.GNU-stack section. */ ++ if (TARGET_LINUX_ABI) ++ file_end_indicate_exec_stack (); ++ + fprintf (asm_out_file, "\t! ------------------------------------\n"); + } + ++static bool ++nds32_asm_output_addr_const_extra (FILE *file, rtx x) ++{ ++ if (GET_CODE (x) == UNSPEC) ++ { ++ switch (XINT (x, 1)) ++ { ++ case UNSPEC_GOTINIT: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ break; ++ case UNSPEC_GOTOFF: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@GOTOFF", file); ++ break; ++ case UNSPEC_GOT: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@GOT", file); ++ break; ++ case UNSPEC_PLT: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@PLT", file); ++ break; ++ case UNSPEC_TLSGD: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@TLSDESC", file); ++ break; ++ case UNSPEC_TLSLD: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@TLSDESC", file); ++ break; ++ case UNSPEC_TLSIE: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@GOTTPOFF", file); ++ break; ++ case UNSPEC_TLSLE: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@TPOFF", file); ++ break; ++ case UNSPEC_ICT: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@ICT", file); ++ break; ++ default: ++ return false; ++ } ++ return true; ++ } ++ else ++ return false; ++} ++ + /* -- Output and Generation of Labels. */ + + static void +@@ -2978,6 +3398,18 @@ + + /* No need to handle following process, so return immediately. */ + return; ++ ++ case 'v': ++ gcc_assert (CONST_INT_P (x) ++ && (INTVAL (x) == 0 ++ || INTVAL (x) == 8 ++ || INTVAL (x) == 16 ++ || INTVAL (x) == 24)); ++ fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8); ++ ++ /* No need to handle following process, so return immediately. */ ++ return; ++ + case 'B': + /* Use exact_log2() to search the 1-bit position. */ + gcc_assert (CONST_INT_P (x)); +@@ -3084,8 +3516,15 @@ + switch (GET_CODE (x)) + { + case LABEL_REF: ++ output_addr_const (stream, x); ++ break; ++ + case SYMBOL_REF: + output_addr_const (stream, x); ++ ++ if (!TARGET_LINUX_ABI && nds32_indirect_call_referenced_p (x)) ++ fprintf (stream, "@ICT"); ++ + break; + + case REG: +@@ -3168,6 +3607,17 @@ + output_addr_const (stream, x); + break; + ++ case CONST_VECTOR: ++ fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x)); ++ break; ++ ++ case LO_SUM: ++ /* This is a special case for inline assembly using memory address 'p'. ++ The inline assembly code is expected to use pesudo instruction ++ for the operand. EX: la */ ++ output_addr_const (stream, XEXP(x, 1)); ++ break; ++ + default: + /* Generally, output_addr_const () is able to handle most cases. + We want to see what CODE could appear, +@@ -3179,7 +3629,9 @@ + } + + static void +-nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) ++nds32_print_operand_address (FILE *stream, ++ machine_mode mode ATTRIBUTE_UNUSED, ++ rtx x) + { + rtx op0, op1; + +@@ -3194,6 +3646,16 @@ + fputs ("]", stream); + break; + ++ case LO_SUM: ++ /* This is a special case for inline assembly using memory operand 'm'. ++ The inline assembly code is expected to use pesudo instruction ++ for the operand. EX: [ls].[bhw] */ ++ fputs ("[ + ", stream); ++ op1 = XEXP (x, 1); ++ output_addr_const (stream, op1); ++ fputs ("]", stream); ++ break; ++ + case REG: + /* Forbid using static chain register ($r16) + on reduced-set registers configuration. */ +@@ -3260,6 +3722,20 @@ + reg_names[REGNO (XEXP (op0, 0))], + sv); + } ++ else if (GET_CODE (op0) == ASHIFT && REG_P (op1)) ++ { ++ /* [Ra + Rb << sv] ++ In normal, ASHIFT can be converted to MULT like above case. ++ But when the address rtx does not go through canonicalize_address ++ defined in fwprop, we'll need this case. */ ++ int sv = INTVAL (XEXP (op0, 1)); ++ gcc_assert (sv <= 3 && sv >=0); ++ ++ fprintf (stream, "[%s + %s << %d]", ++ reg_names[REGNO (op1)], ++ reg_names[REGNO (XEXP (op0, 0))], ++ sv); ++ } + else + { + /* The control flow is not supposed to be here. */ +@@ -3454,6 +3930,27 @@ + static void + nds32_insert_attributes (tree decl, tree *attributes) + { ++ /* A "indirect_call" function attribute implies "noinline" and "noclone" ++ for elf toolchain to support ROM patch mechanism. */ ++ if (TREE_CODE (decl) == FUNCTION_DECL ++ && lookup_attribute ("indirect_call", *attributes) != NULL) ++ { ++ tree new_attrs = *attributes; ++ ++ if (TARGET_LINUX_ABI) ++ error("cannot use indirect_call attribute under linux toolchain"); ++ ++ if (lookup_attribute ("noinline", new_attrs) == NULL) ++ new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs); ++ if (lookup_attribute ("noclone", new_attrs) == NULL) ++ new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs); ++ ++ if (!TREE_PUBLIC (decl)) ++ error("indirect_call attribute can't apply for static function"); ++ ++ *attributes = new_attrs; ++ } ++ + /* For function declaration, we need to check isr-specific attributes: + 1. Call nds32_check_isr_attrs_conflict() to check any conflict. + 2. Check valid integer value for interrupt/exception. +@@ -3479,6 +3976,38 @@ + excp = lookup_attribute ("exception", func_attrs); + reset = lookup_attribute ("reset", func_attrs); + ++ /* The following code may use attribute arguments. If there is no ++ argument from source code, it will cause segmentation fault. ++ Therefore, return dircetly and report error message later. */ ++ if ((intr && TREE_VALUE (intr) == NULL) ++ || (excp && TREE_VALUE (excp) == NULL) ++ || (reset && TREE_VALUE (reset) == NULL)) ++ return; ++ ++ /* ------------------------------------------------------------- */ ++ /* FIXME: ++ FOR BACKWARD COMPATIBILITY, we need to support following patterns: ++ ++ __attribute__((interrupt("XXX;YYY;id=ZZZ"))) ++ __attribute__((exception("XXX;YYY;id=ZZZ"))) ++ __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) ++ ++ If interrupt/exception/reset appears and its argument is a ++ STRING_CST, we will use other functions to parse string in the ++ nds32_construct_isr_vectors_information() and then set necessary ++ isr information in the nds32_isr_vectors[] array. Here we can ++ just return immediately to avoid new-syntax checking. */ ++ if (intr != NULL_TREE ++ && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) ++ return; ++ if (excp != NULL_TREE ++ && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) ++ return; ++ if (reset != NULL_TREE ++ && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) ++ return; ++ /* ------------------------------------------------------------- */ ++ + if (intr || excp) + { + /* Deal with interrupt/exception. */ +@@ -3598,7 +4127,9 @@ + } + if (TARGET_ISA_V3) + { +- /* Under V3 ISA, currently nothing should be strictly set. */ ++ /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */ ++ if (nds32_arch_option == ARCH_V3J) ++ target_flags |= MASK_REDUCED_REGS; + } + if (TARGET_ISA_V3M) + { +@@ -3610,6 +4141,9 @@ + target_flags &= ~MASK_EXT_PERF2; + /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ + target_flags &= ~MASK_EXT_STRING; ++ ++ if (flag_pic) ++ error ("not support -fpic option for v3m toolchain"); + } + + /* See if we are using reduced-set registers: +@@ -3627,6 +4161,12 @@ + fixed_regs[r] = call_used_regs[r] = 1; + } + ++ /* See if user explicitly would like to use fp-as-gp optimization. ++ If so, we must prevent $fp from being allocated ++ during register allocation. */ ++ if (TARGET_FORCE_FP_AS_GP) ++ fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1; ++ + if (!TARGET_16_BIT) + { + /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ +@@ -3643,9 +4183,7 @@ + "must be enable '-mext-fpu-sp' or '-mext-fpu-dp'"); + } + +- /* Currently, we don't support PIC code generation yet. */ +- if (flag_pic) +- sorry ("position-independent code not supported"); ++ nds32_init_rtx_costs (); + + nds32_register_passes (); + } +@@ -3659,8 +4197,11 @@ + vec &constraints ATTRIBUTE_UNUSED, + vec &clobbers, HARD_REG_SET &clobbered_regs) + { +- clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); +- SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); ++ if (!flag_inline_asm_r15) ++ { ++ clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); ++ SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); ++ } + return NULL; + } + +@@ -3687,6 +4228,13 @@ + return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); + } + ++/* Implement TARGET_INIT_LIBFUNCS. */ ++static void ++nds32_init_libfuncs (void) ++{ ++ if (TARGET_LINUX_ABI) ++ init_sync_libfuncs (UNITS_PER_WORD); ++} + + /* ------------------------------------------------------------------------ */ + +@@ -3703,6 +4251,16 @@ + builtin_define ("__nds32__"); + builtin_define ("__NDS32__"); + ++ /* We need to provide builtin macro to describe the size of ++ each vector for interrupt handler under elf toolchain. */ ++ if (!TARGET_LINUX_ABI) ++ { ++ if (TARGET_ISR_VECTOR_SIZE_4_BYTE) ++ builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__"); ++ else ++ builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__"); ++ } ++ + if (TARGET_HARD_FLOAT) + builtin_define ("__NDS32_ABI_2FP_PLUS__"); + else +@@ -3770,6 +4328,8 @@ + builtin_define ("__NDS32_GP_DIRECT__"); + if (TARGET_VH) + builtin_define ("__NDS32_VH__"); ++ if (NDS32_EXT_DSP_P ()) ++ builtin_define ("__NDS32_EXT_DSP__"); + + if (TARGET_BIG_ENDIAN) + builtin_define ("__big_endian__"); +@@ -4042,6 +4602,10 @@ + The result will be in cfun->machine. */ + nds32_compute_stack_frame (); + ++ /* Check frame_pointer_needed again to prevent fp is need after reload. */ ++ if (frame_pointer_needed) ++ cfun->machine->fp_as_gp_p = false; ++ + /* If this is a variadic function, first we need to push argument + registers that hold the unnamed argument value. */ + if (cfun->machine->va_args_size != 0) +@@ -4066,7 +4630,7 @@ + + /* If the function is 'naked', + we do not have to generate prologue code fragment. */ +- if (cfun->machine->naked_p) ++ if (cfun->machine->naked_p && !flag_pic) + return; + + /* Get callee_first_regno and callee_last_regno. */ +@@ -4195,9 +4759,15 @@ + -1 * sp_adjust); + } + +- /* Prevent the instruction scheduler from +- moving instructions across the boundary. */ +- emit_insn (gen_blockage ()); ++ /* Emit gp setup instructions for -fpic. */ ++ if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ++ nds32_emit_load_gp (); ++ ++ /* If user applies -mno-sched-prolog-epilog option, ++ we need to prevent instructions of function body from being ++ scheduled with stack adjustment in prologue. */ ++ if (!flag_sched_prolog_epilog) ++ emit_insn (gen_blockage ()); + } + + /* Function for normal multiple pop epilogue. */ +@@ -4211,9 +4781,11 @@ + The result will be in cfun->machine. */ + nds32_compute_stack_frame (); + +- /* Prevent the instruction scheduler from +- moving instructions across the boundary. */ +- emit_insn (gen_blockage ()); ++ /* If user applies -mno-sched-prolog-epilog option, ++ we need to prevent instructions of function body from being ++ scheduled with stack adjustment in epilogue. */ ++ if (!flag_sched_prolog_epilog) ++ emit_insn (gen_blockage ()); + + /* If the function is 'naked', we do not have to generate + epilogue code fragment BUT 'ret' instruction. +@@ -4239,7 +4811,16 @@ + /* Generate return instruction by using 'return_internal' pattern. + Make sure this instruction is after gen_blockage(). */ + if (!sibcall_p) +- emit_jump_insn (gen_return_internal ()); ++ { ++ /* We need to further check attributes to determine whether ++ there should be return instruction at epilogue. ++ If the attribute naked exists but -mno-ret-in-naked-func ++ is issued, there is NO need to generate return instruction. */ ++ if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) ++ return; ++ ++ emit_jump_insn (gen_return_internal ()); ++ } + return; + } + +@@ -4436,9 +5017,13 @@ + if (cfun->machine->callee_saved_gpr_regs_size > 0) + df_set_regs_ever_live (FP_REGNUM, 1); + ++ /* Check frame_pointer_needed again to prevent fp is need after reload. */ ++ if (frame_pointer_needed) ++ cfun->machine->fp_as_gp_p = false; ++ + /* If the function is 'naked', + we do not have to generate prologue code fragment. */ +- if (cfun->machine->naked_p) ++ if (cfun->machine->naked_p && !flag_pic) + return; + + /* Get callee_first_regno and callee_last_regno. */ +@@ -4566,6 +5151,10 @@ + -1 * sp_adjust); + } + ++ /* Emit gp setup instructions for -fpic. */ ++ if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ++ nds32_emit_load_gp (); ++ + /* Prevent the instruction scheduler from + moving instructions across the boundary. */ + emit_insn (gen_blockage ()); +@@ -4591,9 +5180,19 @@ + if (cfun->machine->naked_p) + { + /* Generate return instruction by using 'return_internal' pattern. +- Make sure this instruction is after gen_blockage(). */ ++ Make sure this instruction is after gen_blockage(). ++ First we need to check this is a function without sibling call. */ + if (!sibcall_p) +- emit_jump_insn (gen_return_internal ()); ++ { ++ /* We need to further check attributes to determine whether ++ there should be return instruction at epilogue. ++ If the attribute naked exists but -mno-ret-in-naked-func ++ is issued, there is NO need to generate return instruction. */ ++ if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) ++ return; ++ ++ emit_jump_insn (gen_return_internal ()); ++ } + return; + } + +@@ -4757,6 +5356,11 @@ + if (!reload_completed) + return 0; + ++ /* If attribute 'naked' appears but -mno-ret-in-naked-func is used, ++ we cannot use return instruction. */ ++ if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) ++ return 0; ++ + sp_adjust = cfun->machine->local_size + + cfun->machine->out_args_size + + cfun->machine->callee_saved_area_gpr_padding_bytes +@@ -5010,6 +5614,9 @@ + #undef TARGET_FUNCTION_ARG_BOUNDARY + #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary + ++#undef TARGET_VECTOR_MODE_SUPPORTED_P ++#define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p ++ + /* -- How Scalar Function Values Are Returned. */ + + #undef TARGET_FUNCTION_VALUE +@@ -5087,6 +5694,21 @@ + #undef TARGET_LEGITIMATE_ADDRESS_P + #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p + ++#undef TARGET_LEGITIMIZE_ADDRESS ++#define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address ++ ++#undef TARGET_LEGITIMATE_CONSTANT_P ++#define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p ++ ++#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE ++#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode ++ ++#undef TARGET_CANNOT_FORCE_CONST_MEM ++#define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem ++ ++#undef TARGET_DELEGITIMIZE_ADDRESS ++#define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address ++ + + /* Anchored Addresses. */ + +@@ -5147,6 +5769,9 @@ + #undef TARGET_ASM_ALIGNED_SI_OP + #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" + ++#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA ++#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra ++ + /* -- Output of Uninitialized Variables. */ + + /* -- Output and Generation of Labels. */ +@@ -5216,6 +5841,9 @@ + + /* Emulating TLS. */ + ++#undef TARGET_HAVE_TLS ++#define TARGET_HAVE_TLS TARGET_LINUX_ABI ++ + + /* Defining coprocessor specifics for MIPS targets. */ + +@@ -5243,6 +5871,8 @@ + #undef TARGET_EXPAND_BUILTIN + #define TARGET_EXPAND_BUILTIN nds32_expand_builtin + ++#undef TARGET_INIT_LIBFUNCS ++#define TARGET_INIT_LIBFUNCS nds32_init_libfuncs + + #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P + #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-cost.c gcc-8.2.0/gcc/config/nds32/nds32-cost.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-cost.c 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-cost.c 2019-01-25 15:38:32.821242637 +0100 +@@ -34,66 +34,379 @@ + #include "optabs.h" /* For GEN_FCN. */ + #include "recog.h" + #include "tm-constrs.h" ++#include "tree-pass.h" + + /* ------------------------------------------------------------------------ */ + +-bool +-nds32_rtx_costs_impl (rtx x, +- machine_mode mode ATTRIBUTE_UNUSED, +- int outer_code, +- int opno ATTRIBUTE_UNUSED, +- int *total, +- bool speed) +-{ +- int code = GET_CODE (x); ++typedef bool (*rtx_cost_func) (rtx, int, int, int, int*); + +- /* According to 'speed', goto suitable cost model section. */ +- if (speed) +- goto performance_cost; +- else +- goto size_cost; +- +- +-performance_cost: +- /* This is section for performance cost model. */ ++struct rtx_cost_model_t { ++ rtx_cost_func speed_prefer; ++ rtx_cost_func size_prefer; ++}; ++ ++static rtx_cost_model_t rtx_cost_model; ++ ++static int insn_size_16bit; /* Initial at nds32_init_rtx_costs. */ ++static const int insn_size_32bit = 4; ++ ++static bool ++nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED, ++ int code, ++ int outer_code ATTRIBUTE_UNUSED, ++ int opno ATTRIBUTE_UNUSED, ++ int *total) ++{ ++ rtx op0; ++ rtx op1; ++ machine_mode mode = GET_MODE (x); ++ /* Scale cost by mode size. */ ++ int cost = COSTS_N_INSNS (GET_MODE_SIZE (mode) / GET_MODE_SIZE (SImode)); + +- /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4. +- We treat it as 4-cycle cost for each instruction +- under performance consideration. */ + switch (code) + { +- case SET: +- /* For 'SET' rtx, we need to return false +- so that it can recursively calculate costs. */ +- return false; +- + case USE: + /* Used in combine.c as a marker. */ + *total = 0; +- break; ++ return true; ++ ++ case CONST_INT: ++ /* When not optimizing for size, we care more about the cost ++ of hot code, and hot code is often in a loop. If a constant ++ operand needs to be forced into a register, we will often be ++ able to hoist the constant load out of the loop, so the load ++ should not contribute to the cost. */ ++ if (outer_code == SET || outer_code == PLUS) ++ *total = satisfies_constraint_Is20 (x) ? 0 : 4; ++ else if (outer_code == AND || outer_code == IOR || outer_code == XOR ++ || outer_code == MINUS) ++ *total = satisfies_constraint_Iu15 (x) ? 0 : 4; ++ else if (outer_code == ASHIFT || outer_code == ASHIFTRT ++ || outer_code == LSHIFTRT) ++ *total = satisfies_constraint_Iu05 (x) ? 0 : 4; ++ else if (GET_RTX_CLASS (outer_code) == RTX_COMPARE ++ || GET_RTX_CLASS (outer_code) == RTX_COMM_COMPARE) ++ *total = satisfies_constraint_Is16 (x) ? 0 : 4; ++ else ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case CONST: ++ case LO_SUM: ++ case HIGH: ++ case SYMBOL_REF: ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case MEM: ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case SET: ++ op0 = SET_DEST (x); ++ op1 = SET_SRC (x); ++ mode = GET_MODE (op0); ++ /* Scale cost by mode size. */ ++ cost = COSTS_N_INSNS (GET_MODE_SIZE (mode) / GET_MODE_SIZE (SImode)); ++ ++ switch (GET_CODE (op1)) ++ { ++ case REG: ++ case SUBREG: ++ /* Register move and Store instructions. */ ++ if ((REG_P (op0) || MEM_P (op0)) ++ && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode)) ++ *total = COSTS_N_INSNS (1); ++ else ++ *total = cost; ++ return true; ++ ++ case MEM: ++ /* Load instructions. */ ++ if (REG_P (op0) && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode)) ++ *total = COSTS_N_INSNS (1); ++ else ++ *total = cost; ++ return true; ++ ++ case CONST_INT: ++ /* movi instruction. */ ++ if (REG_P (op0) && GET_MODE_SIZE (mode) < GET_MODE_SIZE (DImode)) ++ { ++ if (satisfies_constraint_Is20 (op1)) ++ *total = COSTS_N_INSNS (1) - 1; ++ else ++ *total = COSTS_N_INSNS (2); ++ } ++ else ++ *total = cost; ++ return true; ++ ++ case CONST: ++ case SYMBOL_REF: ++ case LABEL_REF: ++ /* la instruction. */ ++ if (REG_P (op0) && GET_MODE_SIZE (mode) < GET_MODE_SIZE (DImode)) ++ *total = COSTS_N_INSNS (1) - 1; ++ else ++ *total = cost; ++ return true; ++ case VEC_SELECT: ++ *total = cost; ++ return true; ++ ++ default: ++ *total = cost; ++ return true; ++ } ++ ++ case PLUS: ++ op0 = XEXP (x, 0); ++ op1 = XEXP (x, 1); ++ ++ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) ++ *total = cost; ++ else if (GET_CODE (op0) == MULT || GET_CODE (op0) == LSHIFTRT ++ || GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT) ++ /* ALU_SHIFT */ ++ *total = COSTS_N_INSNS (2); ++ ++ else if ((GET_CODE (op1) == CONST_INT ++ && satisfies_constraint_Is15 (op1)) ++ || REG_P (op1)) ++ /* ADD instructions */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* ADD instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ return true; ++ ++ case MINUS: ++ op0 = XEXP (x, 0); ++ op1 = XEXP (x, 1); ++ ++ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) ++ *total = cost; ++ else if (GET_CODE (op0) == MULT || GET_CODE (op0) == LSHIFTRT ++ || GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT) ++ /* ALU_SHIFT */ ++ *total = COSTS_N_INSNS (2); ++ else if ((GET_CODE (op0) == CONST_INT ++ && satisfies_constraint_Is15 (op0)) ++ || REG_P (op0)) ++ /* SUB instructions */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* SUB instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ return true; ++ ++ case TRUNCATE: ++ /* TRUNCATE and AND behavior is same. */ ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case AND: ++ case IOR: ++ case XOR: ++ op0 = XEXP (x, 0); ++ op1 = XEXP (x, 1); ++ ++ if (NDS32_EXT_DSP_P ()) ++ { ++ /* We prefer (and (ior) (ior)) than (ior (and) (and)) for ++ synthetize pk** and insb instruction. */ ++ if (code == AND && GET_CODE (op0) == IOR && GET_CODE (op1) == IOR) ++ return COSTS_N_INSNS (1); ++ ++ if (code == IOR && GET_CODE (op0) == AND && GET_CODE (op1) == AND) ++ return COSTS_N_INSNS (10); ++ } ++ ++ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) ++ *total = cost; ++ else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFTRT) ++ *total = COSTS_N_INSNS (2); ++ else if ((GET_CODE (op1) == CONST_INT ++ && satisfies_constraint_Iu15 (op1)) ++ || REG_P (op1)) ++ /* AND, OR, XOR instructions */ ++ *total = COSTS_N_INSNS (1); ++ else if (code == AND || GET_CODE (op0) == NOT) ++ /* BITC instruction */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* AND, OR, XOR instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ return true; + + case MULT: ++ if (GET_MODE (x) == DImode ++ || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND ++ || GET_CODE (XEXP (x, 1)) == ZERO_EXTEND) ++ /* MUL instructions */ ++ *total = COSTS_N_INSNS (1); ++ else if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) ++ *total = cost; ++ else if (outer_code == PLUS || outer_code == MINUS) ++ *total = COSTS_N_INSNS (2); ++ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT ++ && satisfies_constraint_Iu05 (XEXP (x, 1))) ++ || REG_P (XEXP (x, 1))) ++ /* MUL instructions */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* MUL instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ ++ if (TARGET_MUL_SLOW) ++ *total += COSTS_N_INSNS (4); ++ ++ return true; ++ ++ case LSHIFTRT: ++ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) ++ *total = cost; ++ else if (outer_code == PLUS || outer_code == MINUS ++ || outer_code == AND || outer_code == IOR ++ || outer_code == XOR) ++ *total = COSTS_N_INSNS (2); ++ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT ++ && satisfies_constraint_Iu05 (XEXP (x, 1))) ++ || REG_P (XEXP (x, 1))) ++ /* SRL instructions */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* SRL instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ return true; ++ ++ case ASHIFT: ++ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) ++ *total = cost; ++ else if (outer_code == AND || outer_code == IOR ++ || outer_code == XOR) ++ *total = COSTS_N_INSNS (2); ++ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT ++ && satisfies_constraint_Iu05 (XEXP (x, 1))) ++ || REG_P (XEXP (x, 1))) ++ /* SLL instructions */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* SLL instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ return true; ++ ++ case ASHIFTRT: ++ case ROTATERT: ++ if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode)) ++ *total = cost; ++ else if ((GET_CODE (XEXP (x, 1)) == CONST_INT ++ && satisfies_constraint_Iu05 (XEXP (x, 1))) ++ || REG_P (XEXP (x, 1))) ++ /* ROTR, SLL instructions */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* ROTR, SLL instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ return true; ++ ++ case LT: ++ case LTU: ++ if (outer_code == SET) ++ { ++ if ((GET_CODE (XEXP (x, 1)) == CONST_INT ++ && satisfies_constraint_Iu15 (XEXP (x, 1))) ++ || REG_P (XEXP (x, 1))) ++ /* SLT, SLTI instructions */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* SLT, SLT instructions: IMM out of range. */ ++ *total = COSTS_N_INSNS (2); ++ } ++ else ++ /* branch */ ++ *total = COSTS_N_INSNS (2); ++ return true; ++ ++ case EQ: ++ case NE: ++ case GE: ++ case LE: ++ case GT: ++ /* branch */ ++ *total = COSTS_N_INSNS (2); ++ return true; ++ ++ case IF_THEN_ELSE: ++ if (GET_CODE (XEXP (x, 1)) == LABEL_REF) ++ /* branch */ ++ *total = COSTS_N_INSNS (2); ++ else ++ /* cmovz, cmovn instructions */ ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case LABEL_REF: ++ if (outer_code == IF_THEN_ELSE) ++ /* branch */ ++ *total = COSTS_N_INSNS (2); ++ else ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case ZERO_EXTEND: ++ case SIGN_EXTEND: ++ if (MEM_P (XEXP (x, 0))) ++ /* Using memory access. */ ++ *total = COSTS_N_INSNS (1); ++ else ++ /* Zero extend and sign extend instructions. */ ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case NEG: ++ case NOT: + *total = COSTS_N_INSNS (1); +- break; ++ return true; + + case DIV: + case UDIV: + case MOD: + case UMOD: +- *total = COSTS_N_INSNS (7); +- break; +- +- default: +- *total = COSTS_N_INSNS (1); +- break; +- } ++ *total = COSTS_N_INSNS (20); ++ return true; + +- return true; ++ case CALL: ++ *total = COSTS_N_INSNS (2); ++ return true; + ++ case CLZ: ++ case SMIN: ++ case SMAX: ++ case ZERO_EXTRACT: ++ if (TARGET_EXT_PERF) ++ *total = COSTS_N_INSNS (1); ++ else ++ *total = COSTS_N_INSNS (3); ++ return true; ++ case VEC_SELECT: ++ *total = COSTS_N_INSNS (1); ++ return true; + +-size_cost: +- /* This is section for size cost model. */ ++ default: ++ *total = COSTS_N_INSNS (3); ++ return true; ++ } ++} + ++static bool ++nds32_rtx_costs_size_prefer (rtx x, ++ int code, ++ int outer_code, ++ int opno ATTRIBUTE_UNUSED, ++ int *total) ++{ + /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4. + We treat it as 4-byte cost for each instruction + under code size consideration. */ +@@ -118,85 +431,162 @@ + (set X imm20s), use movi, 4-byte cost. + (set X BIG_INT), use sethi/ori, 8-byte cost. */ + if (satisfies_constraint_Is05 (x)) +- *total = COSTS_N_INSNS (1) - 2; ++ *total = insn_size_16bit; + else if (satisfies_constraint_Is20 (x)) +- *total = COSTS_N_INSNS (1); ++ *total = insn_size_32bit; + else +- *total = COSTS_N_INSNS (2); ++ *total = insn_size_32bit * 2; + } + else if (outer_code == PLUS || outer_code == MINUS) + { + /* Possible addi333/subi333 or subi45/addi45, 2-byte cost. + General case, cost 1 instruction with 4-byte. */ + if (satisfies_constraint_Iu05 (x)) +- *total = COSTS_N_INSNS (1) - 2; ++ *total = insn_size_16bit; + else +- *total = COSTS_N_INSNS (1); ++ *total = insn_size_32bit; + } + else if (outer_code == ASHIFT) + { + /* Possible slli333, 2-byte cost. + General case, cost 1 instruction with 4-byte. */ + if (satisfies_constraint_Iu03 (x)) +- *total = COSTS_N_INSNS (1) - 2; ++ *total = insn_size_16bit; + else +- *total = COSTS_N_INSNS (1); ++ *total = insn_size_32bit; + } + else if (outer_code == ASHIFTRT || outer_code == LSHIFTRT) + { + /* Possible srai45 or srli45, 2-byte cost. + General case, cost 1 instruction with 4-byte. */ + if (satisfies_constraint_Iu05 (x)) +- *total = COSTS_N_INSNS (1) - 2; ++ *total = insn_size_16bit; + else +- *total = COSTS_N_INSNS (1); ++ *total = insn_size_32bit; + } + else + { + /* For other cases, simply set it 4-byte cost. */ +- *total = COSTS_N_INSNS (1); ++ *total = insn_size_32bit; + } + break; + + case CONST_DOUBLE: + /* It requires high part and low part processing, set it 8-byte cost. */ +- *total = COSTS_N_INSNS (2); ++ *total = insn_size_32bit * 2; ++ break; ++ ++ case CONST: ++ case SYMBOL_REF: ++ *total = insn_size_32bit * 2; + break; + + default: + /* For other cases, generally we set it 4-byte cost +- and stop resurively traversing. */ +- *total = COSTS_N_INSNS (1); ++ and stop resurively traversing. */ ++ *total = insn_size_32bit; + break; + } + + return true; + } + +-int +-nds32_address_cost_impl (rtx address, +- machine_mode mode ATTRIBUTE_UNUSED, +- addr_space_t as ATTRIBUTE_UNUSED, +- bool speed) ++void ++nds32_init_rtx_costs (void) ++{ ++ rtx_cost_model.speed_prefer = nds32_rtx_costs_speed_prefer; ++ rtx_cost_model.size_prefer = nds32_rtx_costs_size_prefer; ++ ++ if (TARGET_16_BIT) ++ insn_size_16bit = 2; ++ else ++ insn_size_16bit = 4; ++} ++ ++/* This target hook describes the relative costs of RTL expressions. ++ Return 'true' when all subexpressions of x have been processed. ++ Return 'false' to sum the costs of sub-rtx, plus cost of this operation. ++ Refer to gcc/rtlanal.c for more information. */ ++bool ++nds32_rtx_costs_impl (rtx x, ++ machine_mode mode ATTRIBUTE_UNUSED, ++ int outer_code, ++ int opno, ++ int *total, ++ bool speed) ++{ ++ int code = GET_CODE (x); ++ ++ /* According to 'speed', use suitable cost model section. */ ++ if (speed) ++ return rtx_cost_model.speed_prefer(x, code, outer_code, opno, total); ++ else ++ return rtx_cost_model.size_prefer(x, code, outer_code, opno, total); ++} ++ ++ ++int nds32_address_cost_speed_prefer (rtx address) + { + rtx plus0, plus1; + enum rtx_code code; + + code = GET_CODE (address); + +- /* According to 'speed', goto suitable cost model section. */ +- if (speed) +- goto performance_cost; +- else +- goto size_cost; ++ switch (code) ++ { ++ case POST_MODIFY: ++ case POST_INC: ++ case POST_DEC: ++ /* We encourage that rtx contains ++ POST_MODIFY/POST_INC/POST_DEC behavior. */ ++ return COSTS_N_INSNS (1) - 2; ++ ++ case SYMBOL_REF: ++ /* We can have gp-relative load/store for symbol_ref. ++ Have it 4-byte cost. */ ++ return COSTS_N_INSNS (2); ++ ++ case CONST: ++ /* It is supposed to be the pattern (const (plus symbol_ref const_int)). ++ Have it 4-byte cost. */ ++ return COSTS_N_INSNS (2); ++ ++ case REG: ++ /* Simply return 4-byte costs. */ ++ return COSTS_N_INSNS (1) - 2; ++ ++ case PLUS: ++ /* We do not need to check if the address is a legitimate address, ++ because this hook is never called with an invalid address. ++ But we better check the range of ++ const_int value for cost, if it exists. */ ++ plus0 = XEXP (address, 0); ++ plus1 = XEXP (address, 1); + +-performance_cost: +- /* This is section for performance cost model. */ ++ if (REG_P (plus0) && CONST_INT_P (plus1)) ++ return COSTS_N_INSNS (1) - 2; ++ else if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1)) ++ return COSTS_N_INSNS (1) - 1; ++ else if (REG_P (plus0) && REG_P (plus1)) ++ return COSTS_N_INSNS (1); + +- /* FALLTHRU, currently we use same cost model as size_cost. */ ++ /* For other 'plus' situation, make it cost 4-byte. */ ++ return COSTS_N_INSNS (1); + +-size_cost: +- /* This is section for size cost model. */ ++ default: ++ break; ++ } ++ ++ return COSTS_N_INSNS (4); ++ ++} ++ ++int nds32_address_cost_speed_fwprop (rtx address) ++{ ++ rtx plus0, plus1; ++ enum rtx_code code; ++ ++ code = GET_CODE (address); + + switch (code) + { +@@ -210,12 +600,12 @@ + case SYMBOL_REF: + /* We can have gp-relative load/store for symbol_ref. + Have it 4-byte cost. */ +- return COSTS_N_INSNS (1); ++ return COSTS_N_INSNS (2); + + case CONST: + /* It is supposed to be the pattern (const (plus symbol_ref const_int)). + Have it 4-byte cost. */ +- return COSTS_N_INSNS (1); ++ return COSTS_N_INSNS (2); + + case REG: + /* Simply return 4-byte costs. */ +@@ -233,11 +623,78 @@ + { + /* If it is possible to be lwi333/swi333 form, + make it 2-byte cost. */ +- if (satisfies_constraint_Iu05 (plus1)) ++ if (satisfies_constraint_Iu03 (plus1)) + return (COSTS_N_INSNS (1) - 2); + else + return COSTS_N_INSNS (1); + } ++ if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1)) ++ return COSTS_N_INSNS (1) - 2; ++ else if (REG_P (plus0) && REG_P (plus1)) ++ return COSTS_N_INSNS (1); ++ ++ /* For other 'plus' situation, make it cost 4-byte. */ ++ return COSTS_N_INSNS (1); ++ ++ default: ++ break; ++ } ++ ++ return COSTS_N_INSNS (4); ++} ++ ++ ++int nds32_address_cost_size_prefer (rtx address) ++{ ++ rtx plus0, plus1; ++ enum rtx_code code; ++ ++ code = GET_CODE (address); ++ ++ switch (code) ++ { ++ case POST_MODIFY: ++ case POST_INC: ++ case POST_DEC: ++ /* We encourage that rtx contains ++ POST_MODIFY/POST_INC/POST_DEC behavior. */ ++ return 0; ++ ++ case SYMBOL_REF: ++ /* We can have gp-relative load/store for symbol_ref. ++ Have it 4-byte cost. */ ++ return COSTS_N_INSNS (2); ++ ++ case CONST: ++ /* It is supposed to be the pattern (const (plus symbol_ref const_int)). ++ Have it 4-byte cost. */ ++ return COSTS_N_INSNS (2); ++ ++ case REG: ++ /* Simply return 4-byte costs. */ ++ return COSTS_N_INSNS (1) - 1; ++ ++ case PLUS: ++ /* We do not need to check if the address is a legitimate address, ++ because this hook is never called with an invalid address. ++ But we better check the range of ++ const_int value for cost, if it exists. */ ++ plus0 = XEXP (address, 0); ++ plus1 = XEXP (address, 1); ++ ++ if (REG_P (plus0) && CONST_INT_P (plus1)) ++ { ++ /* If it is possible to be lwi333/swi333 form, ++ make it 2-byte cost. */ ++ if (satisfies_constraint_Iu03 (plus1)) ++ return (COSTS_N_INSNS (1) - 2); ++ else ++ return COSTS_N_INSNS (1) - 1; ++ } ++ ++ /* (plus (reg) (mult (reg) (const))) */ ++ if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1)) ++ return (COSTS_N_INSNS (1) - 1); + + /* For other 'plus' situation, make it cost 4-byte. */ + return COSTS_N_INSNS (1); +@@ -247,6 +704,23 @@ + } + + return COSTS_N_INSNS (4); ++ ++} ++ ++int nds32_address_cost_impl (rtx address, ++ machine_mode mode ATTRIBUTE_UNUSED, ++ addr_space_t as ATTRIBUTE_UNUSED, ++ bool speed_p) ++{ ++ if (speed_p) ++ { ++ if (current_pass->tv_id == TV_FWPROP) ++ return nds32_address_cost_speed_fwprop (address); ++ else ++ return nds32_address_cost_speed_prefer (address); ++ } ++ else ++ return nds32_address_cost_size_prefer (address); + } + + /* ------------------------------------------------------------------------ */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-doubleword.md gcc-8.2.0/gcc/config/nds32/nds32-doubleword.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-doubleword.md 2018-05-07 04:09:58.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-doubleword.md 2019-01-25 15:38:32.821242637 +0100 +@@ -136,10 +136,28 @@ + } + ) + ++;; Split move_di pattern when the hard register is odd. ++(define_split ++ [(set (match_operand:DIDF 0 "register_operand" "") ++ (match_operand:DIDF 1 "register_operand" ""))] ++ "(NDS32_IS_GPR_REGNUM (REGNO (operands[0])) ++ && ((REGNO (operands[0]) & 0x1) == 1)) ++ || (NDS32_IS_GPR_REGNUM (REGNO (operands[1])) ++ && ((REGNO (operands[1]) & 0x1) == 1))" ++ [(set (match_dup 2) (match_dup 3)) ++ (set (match_dup 4) (match_dup 5))] ++ { ++ operands[2] = gen_lowpart (SImode, operands[0]); ++ operands[4] = gen_highpart (SImode, operands[0]); ++ operands[3] = gen_lowpart (SImode, operands[1]); ++ operands[5] = gen_highpart (SImode, operands[1]); ++ } ++) ++ + (define_split + [(set (match_operand:DIDF 0 "register_operand" "") + (match_operand:DIDF 1 "const_double_operand" ""))] +- "reload_completed" ++ "flag_pic || reload_completed" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5))] + { +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-dspext.md gcc-8.2.0/gcc/config/nds32/nds32-dspext.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-dspext.md 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-dspext.md 2019-01-25 15:38:32.825242648 +0100 +@@ -0,0 +1,5278 @@ ++;; Machine description of Andes NDS32 cpu for GNU compiler ++;; Copyright (C) 2012-2018 Free Software Foundation, Inc. ++;; Contributed by Andes Technology Corporation. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 3, or (at your ++;; option) any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_expand "mov" ++ [(set (match_operand:VQIHI 0 "general_operand" "") ++ (match_operand:VQIHI 1 "general_operand" ""))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ /* Need to force register if mem <- !reg. */ ++ if (MEM_P (operands[0]) && !REG_P (operands[1])) ++ operands[1] = force_reg (mode, operands[1]); ++ ++ /* If operands[1] is a large constant and cannot be performed ++ by a single instruction, we need to split it. */ ++ if (GET_CODE (operands[1]) == CONST_VECTOR ++ && !satisfies_constraint_CVs2 (operands[1]) ++ && !satisfies_constraint_CVhi (operands[1])) ++ { ++ HOST_WIDE_INT ival = const_vector_to_hwint (operands[1]); ++ rtx tmp_rtx; ++ ++ tmp_rtx = can_create_pseudo_p () ++ ? gen_reg_rtx (SImode) ++ : simplify_gen_subreg (SImode, operands[0], mode, 0); ++ ++ emit_move_insn (tmp_rtx, gen_int_mode (ival, SImode)); ++ convert_move (operands[0], tmp_rtx, false); ++ DONE; ++ } ++ ++ if (REG_P (operands[0]) && SYMBOLIC_CONST_P (operands[1])) ++ { ++ if (nds32_tls_referenced_p (operands [1])) ++ { ++ nds32_expand_tls_move (operands); ++ DONE; ++ } ++ else if (flag_pic) ++ { ++ nds32_expand_pic_move (operands); ++ DONE; ++ } ++ } ++}) ++ ++(define_insn "*mov" ++ [(set (match_operand:VQIHI 0 "nonimmediate_operand" "=r, r,$U45,$U33,$U37,$U45, m,$ l,$ l,$ l,$ d, d, r,$ d, r, r, r, *f, *f, r, *f, Q") ++ (match_operand:VQIHI 1 "nds32_vmove_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45,Ufe, m, CVp5, CVs5, CVs2, CVhi, *f, r, *f, Q, *f"))] ++ "NDS32_EXT_DSP_P () ++ && (register_operand(operands[0], mode) ++ || register_operand(operands[1], mode))" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "mov55\t%0, %1"; ++ case 1: ++ return "ori\t%0, %1, 0"; ++ case 2: ++ case 3: ++ case 4: ++ case 5: ++ return nds32_output_16bit_store (operands, ); ++ case 6: ++ return nds32_output_32bit_store (operands, ); ++ case 7: ++ case 8: ++ case 9: ++ case 10: ++ case 11: ++ return nds32_output_16bit_load (operands, ); ++ case 12: ++ return nds32_output_32bit_load (operands, ); ++ case 13: ++ return "movpi45\t%0, %1"; ++ case 14: ++ return "movi55\t%0, %1"; ++ case 15: ++ return "movi\t%0, %1"; ++ case 16: ++ return "sethi\t%0, hi20(%1)"; ++ case 17: ++ if (TARGET_FPU_SINGLE) ++ return "fcpyss\t%0, %1, %1"; ++ else ++ return "#"; ++ case 18: ++ return "fmtsr\t%1, %0"; ++ case 19: ++ return "fmfsr\t%0, %1"; ++ case 20: ++ return nds32_output_float_load (operands); ++ case 21: ++ return nds32_output_float_store (operands); ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,load,alu,alu,alu,alu,fcpy,fmtsr,fmfsr,fload,fstore") ++ (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 4, 2, 2, 4, 4, 4, 4, 4, 4, 4") ++ (set_attr "feature" " v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v3m, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")]) ++ ++(define_expand "movv2si" ++ [(set (match_operand:V2SI 0 "general_operand" "") ++ (match_operand:V2SI 1 "general_operand" ""))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ /* Need to force register if mem <- !reg. */ ++ if (MEM_P (operands[0]) && !REG_P (operands[1])) ++ operands[1] = force_reg (V2SImode, operands[1]); ++}) ++ ++(define_insn "*movv2si" ++ [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r, r, r, r, Da, m, f, Q, f, r, f") ++ (match_operand:V2SI 1 "general_operand" " r, i, Da, m, r, r, Q, f, f, f, r"))] ++ "NDS32_EXT_DSP_P () ++ && (register_operand(operands[0], V2SImode) ++ || register_operand(operands[1], V2SImode))" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "movd44\t%0, %1"; ++ case 1: ++ /* reg <- const_int, we ask gcc to split instruction. */ ++ return "#"; ++ case 2: ++ /* The memory format is (mem (reg)), ++ we can generate 'lmw.bi' instruction. */ ++ return nds32_output_double (operands, true); ++ case 3: ++ /* We haven't 64-bit load instruction, ++ we split this pattern to two SImode pattern. */ ++ return "#"; ++ case 4: ++ /* The memory format is (mem (reg)), ++ we can generate 'smw.bi' instruction. */ ++ return nds32_output_double (operands, false); ++ case 5: ++ /* We haven't 64-bit store instruction, ++ we split this pattern to two SImode pattern. */ ++ return "#"; ++ case 6: ++ return nds32_output_float_load (operands); ++ case 7: ++ return nds32_output_float_store (operands); ++ case 8: ++ return "fcpysd\t%0, %1, %1"; ++ case 9: ++ return "fmfdr\t%0, %1"; ++ case 10: ++ return "fmtdr\t%1, %0"; ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu,alu,load,load,store,store,unknown,unknown,unknown,unknown,unknown") ++ (set_attr_alternative "length" ++ [ ++ ;; Alternative 0 ++ (if_then_else (match_test "!TARGET_16_BIT") ++ (const_int 4) ++ (const_int 2)) ++ ;; Alternative 1 ++ (const_int 16) ++ ;; Alternative 2 ++ (const_int 4) ++ ;; Alternative 3 ++ (const_int 8) ++ ;; Alternative 4 ++ (const_int 4) ++ ;; Alternative 5 ++ (const_int 8) ++ ;; Alternative 6 ++ (const_int 4) ++ ;; Alternative 7 ++ (const_int 4) ++ ;; Alternative 8 ++ (const_int 4) ++ ;; Alternative 9 ++ (const_int 4) ++ ;; Alternative 10 ++ (const_int 4) ++ ]) ++ (set_attr "feature" " v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")]) ++ ++(define_expand "movmisalign" ++ [(set (match_operand:VQIHI 0 "general_operand" "") ++ (match_operand:VQIHI 1 "general_operand" ""))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ rtx addr; ++ if (MEM_P (operands[0]) && !REG_P (operands[1])) ++ operands[1] = force_reg (mode, operands[1]); ++ ++ if (MEM_P (operands[0])) ++ { ++ addr = force_reg (Pmode, XEXP (operands[0], 0)); ++ emit_insn (gen_unaligned_store (addr, operands[1])); ++ } ++ else ++ { ++ addr = force_reg (Pmode, XEXP (operands[1], 0)); ++ emit_insn (gen_unaligned_load (operands[0], addr)); ++ } ++ DONE; ++}) ++ ++(define_expand "unaligned_load" ++ [(set (match_operand:VQIHI 0 "register_operand" "=r") ++ (unspec:VQIHI [(mem:VQIHI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_ISA_V3M) ++ nds32_expand_unaligned_load (operands, mode); ++ else ++ emit_insn (gen_unaligned_load_w (operands[0], gen_rtx_MEM (mode, operands[1]))); ++ DONE; ++}) ++ ++(define_insn "unaligned_load_w" ++ [(set (match_operand:VQIHI 0 "register_operand" "= r") ++ (unspec:VQIHI [(match_operand:VQIHI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ return nds32_output_lmw_single_word (operands); ++} ++ [(set_attr "type" "load") ++ (set_attr "length" "4")] ++) ++ ++(define_expand "unaligned_store" ++ [(set (mem:VQIHI (match_operand:SI 0 "register_operand" "r")) ++ (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" "r")] UNSPEC_UASTORE_W))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_ISA_V3M) ++ nds32_expand_unaligned_store (operands, mode); ++ else ++ emit_insn (gen_unaligned_store_w (gen_rtx_MEM (mode, operands[0]), operands[1])); ++ DONE; ++}) ++ ++(define_insn "unaligned_store_w" ++ [(set (match_operand:VQIHI 0 "nds32_lmw_smw_base_operand" "=Umw") ++ (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" " r")] UNSPEC_UASTORE_W))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ return nds32_output_smw_single_word (operands); ++} ++ [(set_attr "type" "store") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "add3" ++ [(set (match_operand:VQIHI 0 "register_operand" "=r") ++ (all_plus:VQIHI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "add %0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "adddi3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (all_plus:DI (match_operand:DI 1 "register_operand" " r") ++ (match_operand:DI 2 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "add64 %0, %1, %2" ++ [(set_attr "type" "dalu64") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "raddv4qi3" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (truncate:V4QI ++ (ashiftrt:V4HI ++ (plus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) ++ (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "radd8\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++ ++(define_insn "uraddv4qi3" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (truncate:V4QI ++ (lshiftrt:V4HI ++ (plus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) ++ (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "uradd8\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "raddv2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (truncate:V2HI ++ (ashiftrt:V2SI ++ (plus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) ++ (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "radd16\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "uraddv2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (truncate:V2HI ++ (lshiftrt:V2SI ++ (plus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) ++ (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "uradd16\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "radddi3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (truncate:DI ++ (ashiftrt:TI ++ (plus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r")) ++ (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "radd64\t%0, %1, %2" ++ [(set_attr "type" "dalu64") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++ ++(define_insn "uradddi3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (truncate:DI ++ (lshiftrt:TI ++ (plus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r")) ++ (zero_extend:TI (match_operand:DI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "uradd64\t%0, %1, %2" ++ [(set_attr "type" "dalu64") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "sub3" ++ [(set (match_operand:VQIHI 0 "register_operand" "=r") ++ (all_minus:VQIHI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "sub %0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "subdi3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (all_minus:DI (match_operand:DI 1 "register_operand" " r") ++ (match_operand:DI 2 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "sub64 %0, %1, %2" ++ [(set_attr "type" "dalu64") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++(define_insn "rsubv4qi3" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (truncate:V4QI ++ (ashiftrt:V4HI ++ (minus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) ++ (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "rsub8\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "ursubv4qi3" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (truncate:V4QI ++ (lshiftrt:V4HI ++ (minus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) ++ (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "ursub8\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rsubv2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (truncate:V2HI ++ (ashiftrt:V2SI ++ (minus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) ++ (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "rsub16\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "ursubv2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (truncate:V2HI ++ (lshiftrt:V2SI ++ (minus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) ++ (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "ursub16\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rsubdi3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (truncate:DI ++ (ashiftrt:TI ++ (minus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r")) ++ (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "rsub64\t%0, %1, %2" ++ [(set_attr "type" "dalu64") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "ursubdi3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (truncate:DI ++ (lshiftrt:TI ++ (minus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r")) ++ (zero_extend:TI (match_operand:DI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "ursub64\t%0, %1, %2" ++ [(set_attr "type" "dalu64") ++ (set_attr "length" "4")]) ++ ++(define_expand "cras16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_cras16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_cras16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "cras16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (plus:HI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "cras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "cras16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (plus:HI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "cras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "kcras16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kcras16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_kcras16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "kcras16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (ss_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (ss_plus:HI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "kcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "kcras16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (ss_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (ss_plus:HI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "kcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "ukcras16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_ukcras16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_ukcras16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "ukcras16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (us_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (us_plus:HI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "ukcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "ukcras16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (us_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (us_plus:HI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "ukcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "crsa16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_crsa16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_crsa16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "crsa16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (plus:HI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "crsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "crsa16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (plus:HI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "crsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "kcrsa16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kcrsa16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_kcrsa16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "kcrsa16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (ss_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (ss_plus:HI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "kcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "kcrsa16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (ss_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (ss_plus:HI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "kcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "ukcrsa16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_ukcrsa16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_ukcrsa16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "ukcrsa16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (us_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (us_plus:HI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "ukcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "ukcrsa16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (us_minus:HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (us_plus:HI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "ukcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "rcras16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_rcras16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_rcras16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "rcras16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (minus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (plus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "rcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "rcras16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (minus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (plus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "rcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "urcras16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_urcras16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_urcras16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "urcras16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (minus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (plus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "urcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "urcras16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (minus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (plus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "urcras16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "rcrsa16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_rcrsa16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_rcrsa16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "rcrsa16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (minus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (plus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "rcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "rcrsa16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (minus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (ashiftrt:SI ++ (plus:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "rcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "urcrsa16_1" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_urcrsa16_1_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_urcrsa16_1_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_insn "urcrsa16_1_le" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (minus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (plus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "urcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_insn "urcrsa16_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (minus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (const_int 1)))) ++ (vec_duplicate:V2HI ++ (truncate:HI ++ (lshiftrt:SI ++ (plus:SI ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)]))) ++ (zero_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])))) ++ (const_int 1)))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "urcrsa16\t%0, %1, %2" ++ [(set_attr "type" "dalu")] ++) ++ ++(define_expand "v2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "") ++ (shifts:V2HI (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:SI 2 "nds32_rimm4u_operand" "")))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (operands[2] == const0_rtx) ++ { ++ emit_move_insn (operands[0], operands[1]); ++ DONE; ++ } ++}) ++ ++(define_insn "*ashlv2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ slli16\t%0, %1, %2 ++ sll16\t%0, %1, %2" ++ [(set_attr "type" "dalu,dalu") ++ (set_attr "length" " 4, 4")]) ++ ++(define_insn "kslli16" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (ss_ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ kslli16\t%0, %1, %2 ++ ksll16\t%0, %1, %2" ++ [(set_attr "type" "dalu,dalu") ++ (set_attr "length" " 4, 4")]) ++ ++(define_insn "*ashrv2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ srai16\t%0, %1, %2 ++ sra16\t%0, %1, %2" ++ [(set_attr "type" "dalu,dalu") ++ (set_attr "length" " 4, 4")]) ++ ++(define_insn "sra16_round" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))] ++ UNSPEC_ROUND))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ srai16.u\t%0, %1, %2 ++ sra16.u\t%0, %1, %2" ++ [(set_attr "type" "daluround,daluround") ++ (set_attr "length" " 4, 4")]) ++ ++(define_insn "*lshrv2hi3" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ srli16\t%0, %1, %2 ++ srl16\t%0, %1, %2" ++ [(set_attr "type" "dalu,dalu") ++ (set_attr "length" " 4, 4")]) ++ ++(define_insn "srl16_round" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (unspec:V2HI [(lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))] ++ UNSPEC_ROUND))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ srli16.u\t%0, %1, %2 ++ srl16.u\t%0, %1, %2" ++ [(set_attr "type" "daluround,daluround") ++ (set_attr "length" " 4, 4")]) ++ ++(define_insn "kslra16" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (if_then_else:V2HI ++ (lt:SI (match_operand:SI 2 "register_operand" " r") ++ (const_int 0)) ++ (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r") ++ (neg:SI (match_dup 2))) ++ (ashift:V2HI (match_dup 1) ++ (match_dup 2))))] ++ "NDS32_EXT_DSP_P ()" ++ "kslra16\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "kslra16_round" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (if_then_else:V2HI ++ (lt:SI (match_operand:SI 2 "register_operand" " r") ++ (const_int 0)) ++ (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r") ++ (neg:SI (match_dup 2)))] ++ UNSPEC_ROUND) ++ (ashift:V2HI (match_dup 1) ++ (match_dup 2))))] ++ "NDS32_EXT_DSP_P ()" ++ "kslra16.u\t%0, %1, %2" ++ [(set_attr "type" "daluround") ++ (set_attr "length" "4")]) ++ ++(define_insn "cmpeq" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(eq:SI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r"))] ++ UNSPEC_VEC_COMPARE))] ++ "NDS32_EXT_DSP_P ()" ++ "cmpeq\t%0, %1, %2" ++ [(set_attr "type" "dcmp") ++ (set_attr "length" "4")]) ++ ++(define_insn "scmplt" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(lt:SI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r"))] ++ UNSPEC_VEC_COMPARE))] ++ "NDS32_EXT_DSP_P ()" ++ "scmplt\t%0, %1, %2" ++ [(set_attr "type" "dcmp") ++ (set_attr "length" "4")]) ++ ++(define_insn "scmple" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(le:SI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r"))] ++ UNSPEC_VEC_COMPARE))] ++ "NDS32_EXT_DSP_P ()" ++ "scmple\t%0, %1, %2" ++ [(set_attr "type" "dcmp") ++ (set_attr "length" "4")]) ++ ++(define_insn "ucmplt" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(ltu:SI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r"))] ++ UNSPEC_VEC_COMPARE))] ++ "NDS32_EXT_DSP_P ()" ++ "ucmplt\t%0, %1, %2" ++ [(set_attr "type" "dcmp") ++ (set_attr "length" "4")]) ++ ++(define_insn "ucmple" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(leu:SI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r"))] ++ UNSPEC_VEC_COMPARE))] ++ "NDS32_EXT_DSP_P ()" ++ "ucmple\t%0, %1, %2" ++ [(set_attr "type" "dcmp") ++ (set_attr "length" "4")]) ++ ++(define_insn "sclip16" ++ [(set (match_operand:V2HI 0 "register_operand" "= r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") ++ (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")] ++ UNSPEC_CLIPS))] ++ "NDS32_EXT_DSP_P ()" ++ "sclip16\t%0, %1, %2" ++ [(set_attr "type" "dclip") ++ (set_attr "length" "4")]) ++ ++(define_insn "uclip16" ++ [(set (match_operand:V2HI 0 "register_operand" "= r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") ++ (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")] ++ UNSPEC_CLIP))] ++ "NDS32_EXT_DSP_P ()" ++ "uclip16\t%0, %1, %2" ++ [(set_attr "type" "dclip") ++ (set_attr "length" "4")]) ++ ++(define_insn "khm16" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") ++ (match_operand:V2HI 2 "register_operand" " r")] ++ UNSPEC_KHM))] ++ "NDS32_EXT_DSP_P ()" ++ "khm16\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_insn "khmx16" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") ++ (match_operand:V2HI 2 "register_operand" " r")] ++ UNSPEC_KHMX))] ++ "NDS32_EXT_DSP_P ()" ++ "khmx16\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_expand "vec_setv4qi" ++ [(match_operand:V4QI 0 "register_operand" "") ++ (match_operand:QI 1 "register_operand" "") ++ (match_operand:SI 2 "immediate_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ HOST_WIDE_INT pos = INTVAL (operands[2]); ++ if (pos > 4) ++ gcc_unreachable (); ++ HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos; ++ emit_insn (gen_vec_setv4qi_internal (operands[0], operands[1], ++ operands[0], GEN_INT (elem))); ++ DONE; ++}) ++ ++(define_expand "insb" ++ [(match_operand:V4QI 0 "register_operand" "") ++ (match_operand:V4QI 1 "register_operand" "") ++ (match_operand:SI 2 "register_operand" "") ++ (match_operand:SI 3 "const_int_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (INTVAL (operands[3]) > 3 || INTVAL (operands[3]) < 0) ++ gcc_unreachable (); ++ ++ rtx src = gen_reg_rtx (QImode); ++ ++ convert_move (src, operands[2], false); ++ ++ HOST_WIDE_INT selector_index; ++ /* Big endian need reverse index. */ ++ if (TARGET_BIG_ENDIAN) ++ selector_index = 4 - INTVAL (operands[3]) - 1; ++ else ++ selector_index = INTVAL (operands[3]); ++ rtx selector = gen_int_mode (1 << selector_index, SImode); ++ emit_insn (gen_vec_setv4qi_internal (operands[0], src, ++ operands[1], selector)); ++ DONE; ++}) ++ ++(define_expand "insvsi" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "const_int_operand" "") ++ (match_operand:SI 2 "nds32_insv_operand" "")) ++ (match_operand:SI 3 "register_operand" ""))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (INTVAL (operands[1]) != 8) ++ FAIL; ++} ++ [(set_attr "type" "dinsb") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "insvsi_internal" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (const_int 8) ++ (match_operand:SI 1 "nds32_insv_operand" "i")) ++ (match_operand:SI 2 "register_operand" "r"))] ++ "NDS32_EXT_DSP_P ()" ++ "insb\t%0, %2, %v1" ++ [(set_attr "type" "dinsb") ++ (set_attr "length" "4")]) ++ ++(define_insn "insvsiqi_internal" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (const_int 8) ++ (match_operand:SI 1 "nds32_insv_operand" "i")) ++ (zero_extend:SI (match_operand:QI 2 "register_operand" "r")))] ++ "NDS32_EXT_DSP_P ()" ++ "insb\t%0, %2, %v1" ++ [(set_attr "type" "dinsb") ++ (set_attr "length" "4")]) ++ ++;; Intermedium pattern for synthetize insvsiqi_internal ++;; v0 = ((v1 & 0xff) << 8) ++(define_insn_and_split "and0xff_s8" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") ++ (const_int 8)) ++ (const_int 65280)))] ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, operands[1], gen_int_mode (8, SImode))); ++ emit_insn (gen_andsi3 (operands[0], tmp, gen_int_mode (0xffff, SImode))); ++ DONE; ++}) ++ ++;; v0 = (v1 & 0xff00ffff) | ((v2 << 16) | 0xff0000) ++(define_insn_and_split "insbsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") ++ (const_int -16711681)) ++ (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") ++ (const_int 16)) ++ (const_int 16711680))))] ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_move_insn (tmp, operands[1]); ++ emit_insn (gen_insvsi_internal (tmp, gen_int_mode(16, SImode), operands[2])); ++ emit_move_insn (operands[0], tmp); ++ DONE; ++}) ++ ++;; v0 = (v1 & 0xff00ffff) | v2 ++(define_insn_and_split "ior_and0xff00ffff_reg" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") ++ (const_int -16711681)) ++ (match_operand:SI 2 "register_operand" "r")))] ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_andsi3 (tmp, operands[1], gen_int_mode (0xff00ffff, SImode))); ++ emit_insn (gen_iorsi3 (operands[0], tmp, operands[2])); ++ DONE; ++}) ++ ++(define_insn "vec_setv4qi_internal" ++ [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r") ++ (vec_merge:V4QI ++ (vec_duplicate:V4QI ++ (match_operand:QI 1 "register_operand" " r, r, r, r")) ++ (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0") ++ (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "insb\t%0, %1, 3", ++ "insb\t%0, %1, 2", ++ "insb\t%0, %1, 1", ++ "insb\t%0, %1, 0" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "insb\t%0, %1, 0", ++ "insb\t%0, %1, 1", ++ "insb\t%0, %1, 2", ++ "insb\t%0, %1, 3" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dinsb") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_setv4qi_internal_vec" ++ [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r") ++ (vec_merge:V4QI ++ (vec_duplicate:V4QI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r, r, r, r") ++ (parallel [(const_int 0)]))) ++ (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0") ++ (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ insb\t%0, %1, 0 ++ insb\t%0, %1, 1 ++ insb\t%0, %1, 2 ++ insb\t%0, %1, 3" ++ [(set_attr "type" "dinsb") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_mergev4qi_and_cv0_1" ++ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") ++ (vec_merge:V4QI ++ (vec_duplicate:V4QI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " l,r") ++ (parallel [(const_int 0)]))) ++ (const_vector:V4QI [ ++ (const_int 0) ++ (const_int 0) ++ (const_int 0) ++ (const_int 0)]) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeb33\t%0, %1 ++ zeb\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_mergev4qi_and_cv0_2" ++ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") ++ (vec_merge:V4QI ++ (const_vector:V4QI [ ++ (const_int 0) ++ (const_int 0) ++ (const_int 0) ++ (const_int 0)]) ++ (vec_duplicate:V4QI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " l,r") ++ (parallel [(const_int 0)]))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeb33\t%0, %1 ++ zeb\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_mergeqi_and_cv0_1" ++ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") ++ (vec_merge:V4QI ++ (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r")) ++ (const_vector:V4QI [ ++ (const_int 0) ++ (const_int 0) ++ (const_int 0) ++ (const_int 0)]) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeb33\t%0, %1 ++ zeb\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_mergeqi_and_cv0_2" ++ [(set (match_operand:V4QI 0 "register_operand" "=$l,r") ++ (vec_merge:V4QI ++ (const_vector:V4QI [ ++ (const_int 0) ++ (const_int 0) ++ (const_int 0) ++ (const_int 0)]) ++ (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r")) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeb33\t%0, %1 ++ zeb\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_expand "vec_setv2hi" ++ [(match_operand:V2HI 0 "register_operand" "") ++ (match_operand:HI 1 "register_operand" "") ++ (match_operand:SI 2 "immediate_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ HOST_WIDE_INT pos = INTVAL (operands[2]); ++ if (pos > 2) ++ gcc_unreachable (); ++ HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos; ++ emit_insn (gen_vec_setv2hi_internal (operands[0], operands[1], ++ operands[0], GEN_INT (elem))); ++ DONE; ++}) ++ ++(define_insn "vec_setv2hi_internal" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (match_operand:HI 1 "register_operand" " r, r")) ++ (match_operand:V2HI 2 "register_operand" " r, r") ++ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "pkbb16\t%0, %1, %2", ++ "pktb16\t%0, %2, %1" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "pktb16\t%0, %2, %1", ++ "pkbb16\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_mergev2hi_and_cv0_1" ++ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " l,r") ++ (parallel [(const_int 0)]))) ++ (const_vector:V2HI [ ++ (const_int 0) ++ (const_int 0)]) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeh33\t%0, %1 ++ zeh\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_mergev2hi_and_cv0_2" ++ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") ++ (vec_merge:V2HI ++ (const_vector:V2HI [ ++ (const_int 0) ++ (const_int 0)]) ++ (vec_duplicate:V2HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " l,r") ++ (parallel [(const_int 0)]))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeh33\t%0, %1 ++ zeh\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_mergehi_and_cv0_1" ++ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r")) ++ (const_vector:V2HI [ ++ (const_int 0) ++ (const_int 0)]) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeh33\t%0, %1 ++ zeh\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_mergehi_and_cv0_2" ++ [(set (match_operand:V2HI 0 "register_operand" "=$l,r") ++ (vec_merge:V2HI ++ (const_vector:V2HI [ ++ (const_int 0) ++ (const_int 0)]) ++ (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r")) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ zeh33\t%0, %1 ++ zeh\t%0, %1" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_expand "pkbb" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V2HI 1 "register_operand") ++ (match_operand:V2HI 2 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (1), GEN_INT (1), GEN_INT (1))); ++ } ++ else ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (2), GEN_INT (0), GEN_INT (0))); ++ } ++ DONE; ++}) ++ ++(define_insn "pkbbsi_1" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") ++ (const_int 65535)) ++ (ashift:SI (match_operand:SI 2 "register_operand" "r") ++ (const_int 16))))] ++ "NDS32_EXT_DSP_P ()" ++ "pkbb16\t%0, %2, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "pkbbsi_2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") ++ (const_int 16)) ++ (and:SI (match_operand:SI 1 "register_operand" "r") ++ (const_int 65535))))] ++ "NDS32_EXT_DSP_P ()" ++ "pkbb16\t%0, %2, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "pkbbsi_3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) ++ (ashift:SI (match_operand:SI 2 "register_operand" "r") ++ (const_int 16))))] ++ "NDS32_EXT_DSP_P ()" ++ "pkbb16\t%0, %2, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "pkbbsi_4" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") ++ (const_int 16)) ++ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))))] ++ "NDS32_EXT_DSP_P ()" ++ "pkbb16\t%0, %2, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++;; v0 = (v1 & 0xffff0000) | (v2 & 0xffff) ++(define_insn "pktbsi_1" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") ++ (const_int -65536)) ++ (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] ++ "NDS32_EXT_DSP_P ()" ++ "pktb16\t%0, %1, %2" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "pktbsi_2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") ++ (const_int -65536)) ++ (and:SI (match_operand:SI 2 "register_operand" "r") ++ (const_int 65535))))] ++ "NDS32_EXT_DSP_P ()" ++ "pktb16\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "pktbsi_3" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (const_int 16 ) ++ (const_int 0)) ++ (match_operand:SI 1 "register_operand" " r"))] ++ "NDS32_EXT_DSP_P ()" ++ "pktb16\t%0, %0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "pktbsi_4" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (const_int 16 ) ++ (const_int 0)) ++ (zero_extend:SI (match_operand:HI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "pktb16\t%0, %0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "pkttsi" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (and:SI (match_operand:SI 1 "register_operand" " r") ++ (const_int -65536)) ++ (lshiftrt:SI (match_operand:SI 2 "register_operand" " r") ++ (const_int 16))))] ++ "NDS32_EXT_DSP_P ()" ++ "pktt16\t%0, %1, %2" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_expand "pkbt" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V2HI 1 "register_operand") ++ (match_operand:V2HI 2 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (1), GEN_INT (1), GEN_INT (0))); ++ } ++ else ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (2), GEN_INT (0), GEN_INT (1))); ++ } ++ DONE; ++}) ++ ++(define_expand "pktt" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V2HI 1 "register_operand") ++ (match_operand:V2HI 2 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (1), GEN_INT (0), GEN_INT (0))); ++ } ++ else ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (2), GEN_INT (1), GEN_INT (1))); ++ } ++ DONE; ++}) ++ ++(define_expand "pktb" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V2HI 1 "register_operand") ++ (match_operand:V2HI 2 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (1), GEN_INT (0), GEN_INT (1))); ++ } ++ else ++ { ++ emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], ++ GEN_INT (2), GEN_INT (1), GEN_INT (0))); ++ } ++ DONE; ++}) ++ ++(define_insn "vec_mergerr" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (match_operand:HI 1 "register_operand" " r, r")) ++ (vec_duplicate:V2HI ++ (match_operand:HI 2 "register_operand" " r, r")) ++ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ pkbb16\t%0, %2, %1 ++ pkbb16\t%0, %1, %2" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "vec_merge" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r") ++ (vec_merge:V2HI ++ (match_operand:V2HI 1 "register_operand" " r, r") ++ (match_operand:V2HI 2 "register_operand" " r, r") ++ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "pktb16\t%0, %1, %2", ++ "pktb16\t%0, %2, %1" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "pktb16\t%0, %2, %1", ++ "pktb16\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_mergerv" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (match_operand:HI 1 "register_operand" " r, r, r, r")) ++ (vec_duplicate:V2HI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")]))) ++ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ pkbb16\t%0, %2, %1 ++ pktb16\t%0, %2, %1 ++ pkbb16\t%0, %1, %2 ++ pkbt16\t%0, %1, %2" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_mergevr" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")]))) ++ (vec_duplicate:V2HI ++ (match_operand:HI 2 "register_operand" " r, r, r, r")) ++ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ pkbb16\t%0, %2, %1 ++ pkbt16\t%0, %2, %1 ++ pkbb16\t%0, %1, %2 ++ pktb16\t%0, %1, %2" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_mergevv" ++ [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r, r, r, r, r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r, r, r, r, r, r, r, r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01")]))) ++ (vec_duplicate:V2HI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r, r, r, r, r, r, r") ++ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01, Iv00")]))) ++ (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv01, Iv01, Iv02, Iv02, Iv02, Iv02")))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "pktt16\t%0, %1, %2", ++ "pktb16\t%0, %1, %2", ++ "pkbb16\t%0, %1, %2", ++ "pkbt16\t%0, %1, %2", ++ "pktt16\t%0, %2, %1", ++ "pkbt16\t%0, %2, %1", ++ "pkbb16\t%0, %2, %1", ++ "pktb16\t%0, %2, %1" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "pkbb16\t%0, %2, %1", ++ "pktb16\t%0, %2, %1", ++ "pktt16\t%0, %2, %1", ++ "pkbt16\t%0, %2, %1", ++ "pkbb16\t%0, %1, %2", ++ "pkbt16\t%0, %1, %2", ++ "pktt16\t%0, %1, %2", ++ "pktb16\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_expand "vec_extractv4qi" ++ [(set (match_operand:QI 0 "register_operand" "") ++ (vec_select:QI ++ (match_operand:V4QI 1 "nonimmediate_operand" "") ++ (parallel [(match_operand:SI 2 "const_int_operand" "")])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ if (INTVAL (operands[2]) != 0 ++ && INTVAL (operands[2]) != 1 ++ && INTVAL (operands[2]) != 2 ++ && INTVAL (operands[2]) != 3) ++ gcc_unreachable (); ++ ++ if (INTVAL (operands[2]) != 0 && MEM_P (operands[0])) ++ FAIL; ++}) ++ ++(define_insn "vec_extractv4qi0" ++ [(set (match_operand:QI 0 "register_operand" "=l,r,r") ++ (vec_select:QI ++ (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") ++ (parallel [(const_int 0)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "zeb33\t%0, %1"; ++ case 1: ++ return "zeb\t%0, %1"; ++ case 2: ++ return nds32_output_32bit_load (operands, 1); ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_extractv4qi0_ze" ++ [(set (match_operand:SI 0 "register_operand" "=l,r,r") ++ (zero_extend:SI ++ (vec_select:QI ++ (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") ++ (parallel [(const_int 0)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "zeb33\t%0, %1"; ++ case 1: ++ return "zeb\t%0, %1"; ++ case 2: ++ return nds32_output_32bit_load (operands, 1); ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_extractv4qi0_se" ++ [(set (match_operand:SI 0 "register_operand" "=l,r,r") ++ (sign_extend:SI ++ (vec_select:QI ++ (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") ++ (parallel [(const_int 0)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "seb33\t%0, %1"; ++ case 1: ++ return "seb\t%0, %1"; ++ case 2: ++ return nds32_output_32bit_load_s (operands, 1); ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "vec_extractv4qi1" ++ [(set (match_operand:QI 0 "register_operand" "=r") ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 1)])))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (V4QImode); ++ emit_insn (gen_rotrv4qi_1 (tmp, operands[1])); ++ emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "vec_extractv4qi2" ++ [(set (match_operand:QI 0 "register_operand" "=r") ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2)])))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (V4QImode); ++ emit_insn (gen_rotrv4qi_2 (tmp, operands[1])); ++ emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "vec_extractv4qi3" ++ [(set (match_operand:QI 0 "register_operand" "=r") ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)])))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (V4QImode); ++ emit_insn (gen_rotrv4qi_3 (tmp, operands[1])); ++ emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "vec_extractv4qi3_se" ++ [(set (match_operand:SI 0 "register_operand" "=$d,r") ++ (sign_extend:SI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " 0,r") ++ (parallel [(const_int 3)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ srai45\t%0, 24 ++ srai\t%0, %1, 24" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_extractv4qi3_ze" ++ [(set (match_operand:SI 0 "register_operand" "=$d,r") ++ (zero_extend:SI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " 0,r") ++ (parallel [(const_int 3)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ srli45\t%0, 24 ++ srli\t%0, %1, 24" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn_and_split "vec_extractv4qihi0" ++ [(set (match_operand:HI 0 "register_operand" "=r") ++ (sign_extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (QImode); ++ emit_insn (gen_vec_extractv4qi0 (tmp, operands[1])); ++ emit_insn (gen_extendqihi2 (operands[0], tmp)); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "vec_extractv4qihi1" ++ [(set (match_operand:HI 0 "register_operand" "=r") ++ (sign_extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (QImode); ++ emit_insn (gen_vec_extractv4qi1 (tmp, operands[1])); ++ emit_insn (gen_extendqihi2 (operands[0], tmp)); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "vec_extractv4qihi2" ++ [(set (match_operand:HI 0 "register_operand" "=r") ++ (sign_extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2)]))))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (QImode); ++ emit_insn (gen_vec_extractv4qi2 (tmp, operands[1])); ++ emit_insn (gen_extendqihi2 (operands[0], tmp)); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "vec_extractv4qihi3" ++ [(set (match_operand:HI 0 "register_operand" "=r") ++ (sign_extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)]))))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx tmp = gen_reg_rtx (QImode); ++ emit_insn (gen_vec_extractv4qi3 (tmp, operands[1])); ++ emit_insn (gen_extendqihi2 (operands[0], tmp)); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_expand "vec_extractv2hi" ++ [(set (match_operand:HI 0 "register_operand" "") ++ (vec_select:HI ++ (match_operand:V2HI 1 "nonimmediate_operand" "") ++ (parallel [(match_operand:SI 2 "const_int_operand" "")])))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (INTVAL (operands[2]) != 0 ++ && INTVAL (operands[2]) != 1) ++ gcc_unreachable (); ++ ++ if (INTVAL (operands[2]) != 0 && MEM_P (operands[0])) ++ FAIL; ++}) ++ ++(define_insn "vec_extractv2hi0" ++ [(set (match_operand:HI 0 "register_operand" "=$l,r,r") ++ (vec_select:HI ++ (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") ++ (parallel [(const_int 0)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "seh33\t%0, %1"; ++ case 1: ++ return "seh\t%0, %1"; ++ case 2: ++ return nds32_output_32bit_load_s (operands, 2); ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu,alu,load") ++ (set_attr "length" " 2, 4, 4")]) ++ ++(define_insn "vec_extractv2hi0_ze" ++ [(set (match_operand:SI 0 "register_operand" "=$l, r,$ l, *r") ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "nonimmediate_operand" " l, r, U33, m") ++ (parallel [(const_int 0)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "zeh33\t%0, %1"; ++ case 1: ++ return "zeh\t%0, %1"; ++ case 2: ++ return nds32_output_16bit_load (operands, 2); ++ case 3: ++ return nds32_output_32bit_load (operands, 2); ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu,alu,load,load") ++ (set_attr "length" " 2, 4, 2, 4")]) ++ ++(define_insn "vec_extractv2hi0_se" ++ [(set (match_operand:SI 0 "register_operand" "=$l, r, r") ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") ++ (parallel [(const_int 0)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "seh33\t%0, %1"; ++ case 1: ++ return "seh\t%0, %1"; ++ case 2: ++ return nds32_output_32bit_load_s (operands, 2); ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu,alu,load") ++ (set_attr "length" " 2, 4, 4")]) ++ ++(define_insn "vec_extractv2hi0_be" ++ [(set (match_operand:HI 0 "register_operand" "=$d,r") ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " 0,r") ++ (parallel [(const_int 0)])))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "@ ++ srai45\t%0, 16 ++ srai\t%0, %1, 16" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_extractv2hi1" ++ [(set (match_operand:HI 0 "register_operand" "=$d,r") ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " 0,r") ++ (parallel [(const_int 1)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ srai45\t%0, 16 ++ srai\t%0, %1, 16" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_extractv2hi1_se" ++ [(set (match_operand:SI 0 "register_operand" "=$d,r") ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " 0,r") ++ (parallel [(const_int 1)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ srai45\t%0, 16 ++ srai\t%0, %1, 16" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_extractv2hi1_ze" ++ [(set (match_operand:SI 0 "register_operand" "=$d,r") ++ (zero_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " 0,r") ++ (parallel [(const_int 1)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "@ ++ srli45\t%0, 16 ++ srli\t%0, %1, 16" ++ [(set_attr "type" "alu,alu") ++ (set_attr "length" " 2, 4")]) ++ ++(define_insn "vec_extractv2hi1_be" ++ [(set (match_operand:HI 0 "register_operand" "=$l,r,r") ++ (vec_select:HI ++ (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") ++ (parallel [(const_int 1)])))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "seh33\t%0, %1"; ++ case 1: ++ return "seh\t%0, %1"; ++ case 2: ++ return nds32_output_32bit_load_s (operands, 2); ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ [(set_attr "type" "alu,alu,load") ++ (set_attr "length" " 2, 4, 4")]) ++ ++(define_insn "mul16" ++ [(set (match_operand:V2SI 0 "register_operand" "=r") ++ (mult:V2SI (extend:V2SI (match_operand:V2HI 1 "register_operand" "%r")) ++ (extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))))] ++ "NDS32_EXT_DSP_P ()" ++ "mul16\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_insn "mulx16" ++ [(set (match_operand:V2SI 0 "register_operand" "=r") ++ (vec_merge:V2SI ++ (vec_duplicate:V2SI ++ (mult:SI ++ (extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))))) ++ (vec_duplicate:V2SI ++ (mult:SI ++ (extend:SI ++ (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)]))) ++ (extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P ()" ++ "mulx16\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv2hi_1" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_select:V2HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1) (const_int 0)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 16" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv2hi_1_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_select:V2HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0) (const_int 1)])))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 16" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv4qi_1" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 0)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 8" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv4qi_1_be" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2) (const_int 1) (const_int 0) (const_int 3)])))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 8" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv4qi_2" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 16" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv4qi_2_be" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 16" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv4qi_3" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3) (const_int 0) (const_int 1) (const_int 2)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 24" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "rotrv4qi_3_be" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0) (const_int 3) (const_int 2) (const_int 1)])))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "rotri\t%0, %1, 24" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "v4qi_dup_10" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0) (const_int 1) (const_int 0) (const_int 1)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "pkbb\t%0, %1, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "v4qi_dup_32" ++ [(set (match_operand:V4QI 0 "register_operand" "=r") ++ (vec_select:V4QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)])))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "pktt\t%0, %1, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_expand "vec_unpacks_lo_v4qi" ++ [(match_operand:V2HI 0 "register_operand" "=r") ++ (match_operand:V4QI 1 "register_operand" " r")] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++{ ++ emit_insn (gen_sunpkd810 (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_expand "sunpkd810" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_sunpkd810_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_sunpkd810_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_insn "unpkd810_imp" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd810\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd810_imp_inv" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd810\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd810_imp_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 3)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd810\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd810_imp_inv_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 2)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd810\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_expand "sunpkd820" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_sunpkd820_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_sunpkd820_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_insn "unpkd820_imp" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd820\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd820_imp_inv" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 2)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd820\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd820_imp_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 3)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd820\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd820_imp_inv_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd820\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_expand "sunpkd830" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_sunpkd830_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_sunpkd830_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_insn "unpkd830_imp" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd830\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd830_imp_inv" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 3)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd830\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd830_imp_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 3)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd830\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd830_imp_inv_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd830\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_expand "sunpkd831" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_sunpkd831_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_sunpkd831_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_insn "unpkd831_imp" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 1)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd831\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd831_imp_inv" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 3)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "unpkd831\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd831_imp_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 2)])))) ++ (const_int 1)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd831\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "unpkd831_imp_inv_be" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2)])))) ++ (vec_duplicate:V2HI ++ (extend:HI ++ (vec_select:QI ++ (match_dup 1) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "unpkd831\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_expand "zunpkd810" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_zunpkd810_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_zunpkd810_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_expand "zunpkd820" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_zunpkd820_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_zunpkd820_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_expand "zunpkd830" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_zunpkd830_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_zunpkd830_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_expand "zunpkd831" ++ [(match_operand:V2HI 0 "register_operand") ++ (match_operand:V4QI 1 "register_operand")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_zunpkd831_imp_be (operands[0], operands[1])); ++ else ++ emit_insn (gen_zunpkd831_imp (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_expand "smbb" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], ++ GEN_INT (1), GEN_INT (1))); ++ else ++ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], ++ GEN_INT (0), GEN_INT (0))); ++ DONE; ++}) ++ ++(define_expand "smbt" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], ++ GEN_INT (1), GEN_INT (0))); ++ else ++ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], ++ GEN_INT (0), GEN_INT (1))); ++ DONE; ++}) ++ ++(define_expand "smtt" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], ++ GEN_INT (0), GEN_INT (0))); ++ else ++ emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], ++ GEN_INT (1), GEN_INT (1))); ++ DONE; ++}) ++ ++(define_insn "mulhisi3v" ++ [(set (match_operand:SI 0 "register_operand" "= r, r, r, r") ++ (mult:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "smtt\t%0, %1, %2", ++ "smbt\t%0, %2, %1", ++ "smbb\t%0, %1, %2", ++ "smbt\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "smbb\t%0, %1, %2", ++ "smbt\t%0, %1, %2", ++ "smtt\t%0, %1, %2", ++ "smbt\t%0, %2, %1" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_expand "kmabb" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], ++ GEN_INT (1), GEN_INT (1), ++ operands[1])); ++ else ++ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], ++ GEN_INT (0), GEN_INT (0), ++ operands[1])); ++ DONE; ++}) ++ ++(define_expand "kmabt" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], ++ GEN_INT (1), GEN_INT (0), ++ operands[1])); ++ else ++ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], ++ GEN_INT (0), GEN_INT (1), ++ operands[1])); ++ DONE; ++}) ++ ++(define_expand "kmatt" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], ++ GEN_INT (0), GEN_INT (0), ++ operands[1])); ++ else ++ emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], ++ GEN_INT (1), GEN_INT (1), ++ operands[1])); ++ DONE; ++}) ++ ++(define_insn "kma_internal" ++ [(set (match_operand:SI 0 "register_operand" "= r, r, r, r") ++ (ss_plus:SI ++ (mult:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))) ++ (match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "kmatt\t%0, %1, %2", ++ "kmabt\t%0, %2, %1", ++ "kmabb\t%0, %1, %2", ++ "kmabt\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "kmabb\t%0, %1, %2", ++ "kmabt\t%0, %1, %2", ++ "kmatt\t%0, %1, %2", ++ "kmabt\t%0, %2, %1" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_expand "smds" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smds_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_smds_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_expand "smds_le" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++}) ++ ++(define_expand "smds_be" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++}) ++ ++(define_expand "smdrs" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smdrs_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_smdrs_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_expand "smdrs_le" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++}) ++ ++(define_expand "smdrs_be" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++}) ++ ++(define_expand "smxdsv" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:V2HI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smxdsv_be (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_smxdsv_le (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++ ++(define_expand "smxdsv_le" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++}) ++ ++(define_expand "smxdsv_be" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++}) ++ ++(define_insn "smal1" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI (match_operand:DI 1 "register_operand" " r") ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smal2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI (match_operand:DI 1 "register_operand" " r") ++ (mult:DI ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))))))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smal3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI (match_operand:DI 1 "register_operand" " r") ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smal4" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI (match_operand:DI 1 "register_operand" " r") ++ (mult:DI ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))))))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smal5" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))))) ++ (match_operand:DI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smal6" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (mult:DI ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)])))) ++ (match_operand:DI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smal7" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))))) ++ (match_operand:DI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smal8" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (mult:DI ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)])))) ++ (match_operand:DI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "smal\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++;; We need this dummy pattern for smal ++(define_insn_and_split "extendsidi2" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (sign_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))] ++ "NDS32_EXT_DSP_P ()" ++ "#" ++ "NDS32_EXT_DSP_P ()" ++ [(const_int 0)] ++{ ++ rtx high_part_dst, low_part_dst; ++ ++ low_part_dst = nds32_di_low_part_subreg (operands[0]); ++ high_part_dst = nds32_di_high_part_subreg (operands[0]); ++ ++ emit_move_insn (low_part_dst, operands[1]); ++ emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31))); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++;; We need this dummy pattern for usmar64/usmsr64 ++(define_insn_and_split "zero_extendsidi2" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (zero_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))] ++ "NDS32_EXT_DSP_P ()" ++ "#" ++ "NDS32_EXT_DSP_P ()" ++ [(const_int 0)] ++{ ++ rtx high_part_dst, low_part_dst; ++ ++ low_part_dst = nds32_di_low_part_subreg (operands[0]); ++ high_part_dst = nds32_di_high_part_subreg (operands[0]); ++ ++ emit_move_insn (low_part_dst, operands[1]); ++ emit_move_insn (high_part_dst, const0_rtx); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] ++ "NDS32_EXT_DSP_P ()" ++ "#" ++ "NDS32_EXT_DSP_P ()" ++ [(const_int 0)] ++{ ++ rtx high_part_dst, low_part_dst; ++ ++ low_part_dst = nds32_di_low_part_subreg (operands[0]); ++ high_part_dst = nds32_di_high_part_subreg (operands[0]); ++ ++ ++ emit_insn (gen_extendhisi2 (low_part_dst, operands[1])); ++ emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31))); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_insn "extendqihi2" ++ [(set (match_operand:HI 0 "register_operand" "=r") ++ (sign_extend:HI (match_operand:QI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "sunpkd820\t%0, %1" ++ [(set_attr "type" "dpack") ++ (set_attr "length" "4")]) ++ ++(define_insn "smulsi3_highpart" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI ++ (lshiftrt:DI ++ (mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) ++ (const_int 32))))] ++ "NDS32_EXT_DSP_P ()" ++ "smmul\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_insn "smmul_round" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI ++ (lshiftrt:DI ++ (unspec:DI [(mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))] ++ UNSPEC_ROUND) ++ (const_int 32))))] ++ "NDS32_EXT_DSP_P ()" ++ "smmul.u\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmmac" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI (match_operand:SI 1 "register_operand" " 0") ++ (truncate:SI ++ (lshiftrt:DI ++ (mult:DI ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) ++ (sign_extend:DI (match_operand:SI 3 "register_operand" " r"))) ++ (const_int 32)))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmmac\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmmac_round" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI (match_operand:SI 1 "register_operand" " 0") ++ (truncate:SI ++ (lshiftrt:DI ++ (unspec:DI [(mult:DI ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) ++ (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))] ++ UNSPEC_ROUND) ++ (const_int 32)))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmmac.u\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmmsb" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_minus:SI (match_operand:SI 1 "register_operand" " 0") ++ (truncate:SI ++ (lshiftrt:DI ++ (mult:DI ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) ++ (sign_extend:DI (match_operand:SI 3 "register_operand" " r"))) ++ (const_int 32)))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmmsb\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmmsb_round" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_minus:SI (match_operand:SI 1 "register_operand" " 0") ++ (truncate:SI ++ (lshiftrt:DI ++ (unspec:DI [(mult:DI ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) ++ (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))] ++ UNSPEC_ROUND) ++ (const_int 32)))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmmsb.u\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kwmmul" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI ++ (lshiftrt:DI ++ (ss_mult:DI ++ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2)) ++ (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2))) ++ (const_int 32))))] ++ "NDS32_EXT_DSP_P ()" ++ "kwmmul\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_insn "kwmmul_round" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI ++ (lshiftrt:DI ++ (unspec:DI [ ++ (ss_mult:DI ++ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2)) ++ (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))] ++ UNSPEC_ROUND) ++ (const_int 32))))] ++ "NDS32_EXT_DSP_P ()" ++ "kwmmul.u\t%0, %1, %2" ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_expand "smmwb" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1))); ++ else ++ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0))); ++ DONE; ++}) ++ ++(define_expand "smmwt" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0))); ++ else ++ emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1))); ++ DONE; ++}) ++ ++(define_insn "smulhisi3_highpart_1" ++ [(set (match_operand:SI 0 "register_operand" "= r, r") ++ (truncate:SI ++ (lshiftrt:DI ++ (mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))) ++ (const_int 16))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "smmwt\t%0, %1, %2", ++ "smmwb\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "smmwb\t%0, %1, %2", ++ "smmwt\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_insn "smulhisi3_highpart_2" ++ [(set (match_operand:SI 0 "register_operand" "= r, r") ++ (truncate:SI ++ (lshiftrt:DI ++ (mult:DI ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r, r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))) ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r, r"))) ++ (const_int 16))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "smmwt\t%0, %1, %2", ++ "smmwb\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "smmwb\t%0, %1, %2", ++ "smmwt\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_expand "smmwb_round" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1))); ++ else ++ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0))); ++ DONE; ++}) ++ ++(define_expand "smmwt_round" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0))); ++ else ++ emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1))); ++ DONE; ++}) ++ ++(define_insn "smmw_round_internal" ++ [(set (match_operand:SI 0 "register_operand" "= r, r") ++ (truncate:SI ++ (lshiftrt:DI ++ (unspec:DI ++ [(mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))] ++ UNSPEC_ROUND) ++ (const_int 16))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "smmwt.u\t%0, %1, %2", ++ "smmwb.u\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "smmwb.u\t%0, %1, %2", ++ "smmwt.u\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmul") ++ (set_attr "length" "4")]) ++ ++(define_expand "kmmawb" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:SI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); ++ else ++ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); ++ DONE; ++}) ++ ++(define_expand "kmmawt" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:SI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); ++ else ++ emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); ++ DONE; ++}) ++ ++(define_insn "kmmaw_internal" ++ [(set (match_operand:SI 0 "register_operand" "= r, r") ++ (ss_plus:SI ++ (match_operand:SI 4 "register_operand" " 0, 0") ++ (truncate:SI ++ (lshiftrt:DI ++ (mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))) ++ (const_int 16)))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "kmmawt\t%0, %1, %2", ++ "kmmawb\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "kmmawb\t%0, %1, %2", ++ "kmmawt\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_expand "kmmawb_round" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:SI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); ++ else ++ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); ++ DONE; ++} ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ ++(define_expand "kmmawt_round" ++ [(match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "") ++ (match_operand:SI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); ++ else ++ emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); ++ DONE; ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "kmmaw_round_internal" ++ [(set (match_operand:SI 0 "register_operand" "= r, r") ++ (ss_plus:SI ++ (match_operand:SI 4 "register_operand" " 0, 0") ++ (truncate:SI ++ (lshiftrt:DI ++ (unspec:DI ++ [(mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))] ++ UNSPEC_ROUND) ++ (const_int 16)))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "kmmawt.u\t%0, %1, %2", ++ "kmmawb.u\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "kmmawb.u\t%0, %1, %2", ++ "kmmawt.u\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_expand "smalbb" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smaddhidi (operands[0], operands[2], ++ operands[3], operands[1], ++ GEN_INT (1), GEN_INT (1))); ++ else ++ emit_insn (gen_smaddhidi (operands[0], operands[2], ++ operands[3], operands[1], ++ GEN_INT (0), GEN_INT (0))); ++ DONE; ++}) ++ ++(define_expand "smalbt" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smaddhidi (operands[0], operands[2], ++ operands[3], operands[1], ++ GEN_INT (1), GEN_INT (0))); ++ else ++ emit_insn (gen_smaddhidi (operands[0], operands[2], ++ operands[3], operands[1], ++ GEN_INT (0), GEN_INT (1))); ++ DONE; ++}) ++ ++(define_expand "smaltt" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" "") ++ (match_operand:V2HI 3 "register_operand" "")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smaddhidi (operands[0], operands[2], ++ operands[3], operands[1], ++ GEN_INT (0), GEN_INT (0))); ++ else ++ emit_insn (gen_smaddhidi (operands[0], operands[2], ++ operands[3], operands[1], ++ GEN_INT (1), GEN_INT (1))); ++ DONE; ++}) ++ ++(define_insn "smaddhidi" ++ [(set (match_operand:DI 0 "register_operand" "= r, r, r, r") ++ (plus:DI ++ (match_operand:DI 3 "register_operand" " 0, 0, 0, 0") ++ (mult:DI ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "smaltt\t%0, %1, %2", ++ "smalbt\t%0, %2, %1", ++ "smalbb\t%0, %1, %2", ++ "smalbt\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "smalbb\t%0, %1, %2", ++ "smalbt\t%0, %1, %2", ++ "smaltt\t%0, %1, %2", ++ "smalbt\t%0, %2, %1" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smaddhidi2" ++ [(set (match_operand:DI 0 "register_operand" "= r, r, r, r") ++ (plus:DI ++ (mult:DI ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) ++ (sign_extend:DI ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r, r, r, r") ++ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))) ++ (match_operand:DI 3 "register_operand" " 0, 0, 0, 0")))] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ { ++ const char *pats[] = { "smaltt\t%0, %1, %2", ++ "smalbt\t%0, %2, %1", ++ "smalbb\t%0, %1, %2", ++ "smalbt\t%0, %1, %2" }; ++ return pats[which_alternative]; ++ } ++ else ++ { ++ const char *pats[] = { "smalbb\t%0, %1, %2", ++ "smalbt\t%0, %1, %2", ++ "smaltt\t%0, %1, %2", ++ "smalbt\t%0, %2, %1" }; ++ return pats[which_alternative]; ++ } ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_expand "smalda1" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" " r") ++ (match_operand:V2HI 3 "register_operand" " r")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smalda1_be (operands[0], operands[1], operands[2], operands[3])); ++ else ++ emit_insn (gen_smalda1_le (operands[0], operands[1], operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_expand "smalds1" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" " r") ++ (match_operand:V2HI 3 "register_operand" " r")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smalds1_be (operands[0], operands[1], operands[2], operands[3])); ++ else ++ emit_insn (gen_smalds1_le (operands[0], operands[1], operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "smalda1_le" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)]))))))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "smalda\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smalds1_le" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)]))))))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "smalds\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smalda1_be" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)]))))))))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "smalda\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smalds1_be" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)]))))))))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "smalds\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_expand "smaldrs3" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" " r") ++ (match_operand:V2HI 3 "register_operand" " r")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smaldrs3_be (operands[0], operands[1], operands[2], operands[3])); ++ else ++ emit_insn (gen_smaldrs3_le (operands[0], operands[1], operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "smaldrs3_le" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)]))))))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "smaldrs\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smaldrs3_be" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)]))))))))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "smaldrs\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_expand "smalxda1" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" " r") ++ (match_operand:V2HI 3 "register_operand" " r")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smalxda1_be (operands[0], operands[1], operands[2], operands[3])); ++ else ++ emit_insn (gen_smalxda1_le (operands[0], operands[1], operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_expand "smalxds1" ++ [(match_operand:DI 0 "register_operand" "") ++ (match_operand:DI 1 "register_operand" "") ++ (match_operand:V2HI 2 "register_operand" " r") ++ (match_operand:V2HI 3 "register_operand" " r")] ++ "NDS32_EXT_DSP_P ()" ++{ ++ if (TARGET_BIG_ENDIAN) ++ emit_insn (gen_smalxds1_be (operands[0], operands[1], operands[2], operands[3])); ++ else ++ emit_insn (gen_smalxds1_le (operands[0], operands[1], operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "smalxd1_le" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (plus_minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)]))))))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "smalxd\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "smalxd1_be" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (plus_minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)]))))))))] ++ "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" ++ "smalxd\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smslda1" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (minus:DI ++ (minus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))))) ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "smslda\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "smslxda1" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (minus:DI ++ (minus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))))) ++ (sign_extend:DI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "smslxda\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++;; mada for synthetize smalda ++(define_insn_and_split "mada1" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" "r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" "r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx result0 = gen_reg_rtx (SImode); ++ rtx result1 = gen_reg_rtx (SImode); ++ emit_insn (gen_mulhisi3v (result0, operands[1], operands[2], ++ operands[3], operands[4])); ++ emit_insn (gen_mulhisi3v (result1, operands[1], operands[2], ++ operands[5], operands[6])); ++ emit_insn (gen_addsi3 (operands[0], result0, result1)); ++ DONE; ++}) ++ ++(define_insn_and_split "mada2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" "r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" "r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 1)] ++{ ++ rtx result0 = gen_reg_rtx (SImode); ++ rtx result1 = gen_reg_rtx (SImode); ++ emit_insn (gen_mulhisi3v (result0, operands[1], operands[2], ++ operands[3], operands[4])); ++ emit_insn (gen_mulhisi3v (result1, operands[1], operands[2], ++ operands[6], operands[5])); ++ emit_insn (gen_addsi3 (operands[0], result0, result1)); ++ DONE; ++}) ++ ++;; sms for synthetize smalds ++(define_insn_and_split "sms1" ++ [(set (match_operand:SI 0 "register_operand" "= r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] ++ "NDS32_EXT_DSP_P () ++ && (!reload_completed ++ || !nds32_need_split_sms_p (operands[3], operands[4], ++ operands[5], operands[6]))" ++ ++{ ++ return nds32_output_sms (operands[3], operands[4], ++ operands[5], operands[6]); ++} ++ "NDS32_EXT_DSP_P () ++ && !reload_completed ++ && nds32_need_split_sms_p (operands[3], operands[4], ++ operands[5], operands[6])" ++ [(const_int 1)] ++{ ++ nds32_split_sms (operands[0], operands[1], operands[2], ++ operands[3], operands[4], ++ operands[5], operands[6]); ++ DONE; ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "sms2" ++ [(set (match_operand:SI 0 "register_operand" "= r") ++ (minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] ++ "NDS32_EXT_DSP_P () ++ && (!reload_completed ++ || !nds32_need_split_sms_p (operands[3], operands[4], ++ operands[6], operands[5]))" ++{ ++ return nds32_output_sms (operands[3], operands[4], ++ operands[6], operands[5]); ++} ++ "NDS32_EXT_DSP_P () ++ && !reload_completed ++ && nds32_need_split_sms_p (operands[3], operands[4], ++ operands[6], operands[5])" ++ [(const_int 1)] ++{ ++ nds32_split_sms (operands[0], operands[1], operands[2], ++ operands[3], operands[4], ++ operands[6], operands[5]); ++ DONE; ++} ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmda" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" "r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" "r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmda\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmxda" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" "r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" "r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 1) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmxda\t%0, %1, %2" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmada" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmada\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmada2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmada\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmaxda" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_plus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmaxda\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmads" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmads\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmadrs" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmadrs\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmaxds" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmaxds\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmsda" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_minus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 0)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmsda\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmsxda" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_minus:SI ++ (match_operand:SI 1 "register_operand" " 0") ++ (ss_minus:SI ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_operand:V2HI 3 "register_operand" " r") ++ (parallel [(const_int 0)])))) ++ (mult:SI ++ (sign_extend:SI (vec_select:HI ++ (match_dup 2) ++ (parallel [(const_int 0)]))) ++ (sign_extend:SI (vec_select:HI ++ (match_dup 3) ++ (parallel [(const_int 1)])))))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmsxda\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++;; smax[8|16] and umax[8|16] ++(define_insn "3" ++ [(set (match_operand:VQIHI 0 "register_operand" "=r") ++ (sumax:VQIHI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++;; smin[8|16] and umin[8|16] ++(define_insn "3" ++ [(set (match_operand:VQIHI 0 "register_operand" "=r") ++ (sumin:VQIHI (match_operand:VQIHI 1 "register_operand" " r") ++ (match_operand:VQIHI 2 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "3_bb" ++ [(set (match_operand: 0 "register_operand" "=r") ++ (sumin_max: (vec_select: ++ (match_operand:VQIHI 1 "register_operand" " r") ++ (parallel [(const_int 0)])) ++ (vec_select: ++ (match_operand:VQIHI 2 "register_operand" " r") ++ (parallel [(const_int 0)]))))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "3_tt" ++ [(set (match_operand: 0 "register_operand" "=r") ++ (sumin_max: (vec_select: ++ (match_operand:VQIHI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select: ++ (match_operand:VQIHI 2 "register_operand" " r") ++ (parallel [(const_int 1)]))))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 0)] ++{ ++ rtx tmp = gen_reg_rtx (mode); ++ emit_insn (gen_3 (tmp, operands[1], operands[2])); ++ emit_insn (gen_rotr_1 (tmp, tmp)); ++ emit_move_insn (operands[0], simplify_gen_subreg (mode, tmp, mode, 0)); ++ DONE; ++} ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "v4qi3_22" ++ [(set (match_operand:QI 0 "register_operand" "=r") ++ (sumin_max:QI (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 2)])) ++ (vec_select:QI ++ (match_operand:V4QI 2 "register_operand" " r") ++ (parallel [(const_int 2)]))))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 0)] ++{ ++ rtx tmp = gen_reg_rtx (V4QImode); ++ emit_insn (gen_v4qi3 (tmp, operands[1], operands[2])); ++ emit_insn (gen_rotrv4qi_2 (tmp, tmp)); ++ emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0)); ++ DONE; ++} ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "v4qi3_33" ++ [(set (match_operand:QI 0 "register_operand" "=r") ++ (sumin_max:QI (vec_select:QI ++ (match_operand:V4QI 1 "register_operand" " r") ++ (parallel [(const_int 3)])) ++ (vec_select:QI ++ (match_operand:V4QI 2 "register_operand" " r") ++ (parallel [(const_int 3)]))))] ++ "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 0)] ++{ ++ rtx tmp = gen_reg_rtx (V4QImode); ++ emit_insn (gen_v4qi3 (tmp, operands[1], operands[2])); ++ emit_insn (gen_rotrv4qi_3 (tmp, tmp)); ++ emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0)); ++ DONE; ++} ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "v2hi3_bbtt" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (vec_merge:V2HI ++ (vec_duplicate:V2HI ++ (sumin_max:HI (vec_select:HI ++ (match_operand:V2HI 1 "register_operand" " r") ++ (parallel [(const_int 1)])) ++ (vec_select:HI ++ (match_operand:V2HI 2 "register_operand" " r") ++ (parallel [(const_int 1)])))) ++ (vec_duplicate:V2HI ++ (sumin_max:HI (vec_select:HI ++ (match_dup:V2HI 1) ++ (parallel [(const_int 0)])) ++ (vec_select:HI ++ (match_dup:V2HI 2) ++ (parallel [(const_int 0)])))) ++ (const_int 2)))] ++ "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" ++ "#" ++ "NDS32_EXT_DSP_P ()" ++ [(const_int 0)] ++{ ++ emit_insn (gen_v2hi3 (operands[0], operands[1], operands[2])); ++ DONE; ++} ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_expand "abs2" ++ [(set (match_operand:VQIHI 0 "register_operand" "=r") ++ (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P () && TARGET_HW_ABS && !flag_wrapv" ++{ ++}) ++ ++(define_insn "kabs2" ++ [(set (match_operand:VQIHI 0 "register_operand" "=r") ++ (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))] ++ "NDS32_EXT_DSP_P ()" ++ "kabs\t%0, %1" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "mar64_1" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (mult:DI ++ (extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (extend:DI ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "mar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "mar64_2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (mult:DI ++ (extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (extend:DI ++ (match_operand:SI 3 "register_operand" " r"))) ++ (match_operand:DI 1 "register_operand" " 0")))] ++ "NDS32_EXT_DSP_P ()" ++ "mar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "mar64_3" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (extend:DI ++ (mult:SI ++ (match_operand:SI 2 "register_operand" " r") ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "mar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "mar64_4" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (plus:DI ++ (extend:DI ++ (mult:SI ++ (match_operand:SI 2 "register_operand" " r") ++ (match_operand:SI 3 "register_operand" " r"))) ++ (match_operand:DI 1 "register_operand" " 0")))] ++ "NDS32_EXT_DSP_P ()" ++ "mar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "msr64" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (minus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (mult:DI ++ (extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (extend:DI ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "msr64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "msr64_2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (minus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (extend:DI ++ (mult:SI ++ (match_operand:SI 2 "register_operand" " r") ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "msr64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++;; kmar64, kmsr64, ukmar64 and ukmsr64 ++(define_insn "kmar64_1" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (ss_plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (mult:DI ++ (sign_extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (sign_extend:DI ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmar64_2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (ss_plus:DI ++ (mult:DI ++ (sign_extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (sign_extend:DI ++ (match_operand:SI 3 "register_operand" " r"))) ++ (match_operand:DI 1 "register_operand" " 0")))] ++ "NDS32_EXT_DSP_P ()" ++ "kmar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "kmsr64" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (ss_minus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (mult:DI ++ (sign_extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (sign_extend:DI ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "kmsr64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "ukmar64_1" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (us_plus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (mult:DI ++ (zero_extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (zero_extend:DI ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "ukmar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "ukmar64_2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (us_plus:DI ++ (mult:DI ++ (zero_extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (zero_extend:DI ++ (match_operand:SI 3 "register_operand" " r"))) ++ (match_operand:DI 1 "register_operand" " 0")))] ++ "NDS32_EXT_DSP_P ()" ++ "ukmar64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "ukmsr64" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (us_minus:DI ++ (match_operand:DI 1 "register_operand" " 0") ++ (mult:DI ++ (zero_extend:DI ++ (match_operand:SI 2 "register_operand" " r")) ++ (zero_extend:DI ++ (match_operand:SI 3 "register_operand" " r")))))] ++ "NDS32_EXT_DSP_P ()" ++ "ukmsr64\t%0, %2, %3" ++ [(set_attr "type" "dmac") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick1" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (match_operand:SI 1 "register_operand" " r") ++ (match_operand:SI 3 "register_operand" " r")) ++ (and:SI ++ (match_operand:SI 2 "register_operand" " r") ++ (not:SI (match_dup 3)))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %1, %2, %3" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (match_operand:SI 1 "register_operand" " r") ++ (match_operand:SI 2 "register_operand" " r")) ++ (and:SI ++ (not:SI (match_dup 2)) ++ (match_operand:SI 3 "register_operand" " r"))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %1, %3, %2" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (match_operand:SI 1 "register_operand" " r") ++ (match_operand:SI 2 "register_operand" " r")) ++ (and:SI ++ (match_operand:SI 3 "register_operand" " r") ++ (not:SI (match_dup 1)))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %2, %3, %1" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick4" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (match_operand:SI 1 "register_operand" " r") ++ (match_operand:SI 2 "register_operand" " r")) ++ (and:SI ++ (not:SI (match_dup 1)) ++ (match_operand:SI 3 "register_operand" " r"))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %2, %3, %1" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick5" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (match_operand:SI 1 "register_operand" " r") ++ (not:SI (match_operand:SI 2 "register_operand" " r"))) ++ (and:SI ++ (match_operand:SI 3 "register_operand" " r") ++ (match_dup 2))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %3, %1, %2" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick6" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (not:SI (match_operand:SI 1 "register_operand" " r")) ++ (match_operand:SI 2 "register_operand" " r")) ++ (and:SI ++ (match_operand:SI 3 "register_operand" " r") ++ (match_dup 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %3, %2, %1" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick7" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (match_operand:SI 1 "register_operand" " r") ++ (not:SI (match_operand:SI 2 "register_operand" " r"))) ++ (and:SI ++ (match_dup 2) ++ (match_operand:SI 3 "register_operand" " r"))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %3, %1, %2" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "bpick8" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI ++ (and:SI ++ (not:SI (match_operand:SI 1 "register_operand" " r")) ++ (match_operand:SI 2 "register_operand" " r")) ++ (and:SI ++ (match_dup 1) ++ (match_operand:SI 3 "register_operand" " r"))))] ++ "NDS32_EXT_DSP_P ()" ++ "bpick\t%0, %3, %2, %1" ++ [(set_attr "type" "dbpick") ++ (set_attr "length" "4")]) ++ ++(define_insn "sraiu" ++ [(set (match_operand:SI 0 "register_operand" "= r, r") ++ (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r"))] ++ UNSPEC_ROUND))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ srai.u\t%0, %1, %2 ++ sra.u\t%0, %1, %2" ++ [(set_attr "type" "daluround") ++ (set_attr "length" "4")]) ++ ++(define_insn "kssl" ++ [(set (match_operand:SI 0 "register_operand" "= r, r") ++ (ss_ashift:SI (match_operand:SI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ kslli\t%0, %1, %2 ++ ksll\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++(define_insn "kslraw_round" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI ++ (lt:SI (match_operand:SI 2 "register_operand" " r") ++ (const_int 0)) ++ (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r") ++ (neg:SI (match_dup 2)))] ++ UNSPEC_ROUND) ++ (ss_ashift:SI (match_dup 1) ++ (match_dup 2))))] ++ "NDS32_EXT_DSP_P ()" ++ "kslraw.u\t%0, %1, %2" ++ [(set_attr "type" "daluround") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "di3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (shift_rotate:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:SI 2 "nds32_rimm6u_operand" "")))] ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ "#" ++ "NDS32_EXT_DSP_P () && !reload_completed" ++ [(const_int 0)] ++{ ++ if (REGNO (operands[0]) == REGNO (operands[1])) ++ { ++ rtx tmp = gen_reg_rtx (DImode); ++ nds32_split_di3 (tmp, operands[1], operands[2]); ++ emit_move_insn (operands[0], tmp); ++ } ++ else ++ nds32_split_di3 (operands[0], operands[1], operands[2]); ++ DONE; ++}) ++ ++(define_insn "sclip32" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIPS_OV))] ++ "NDS32_EXT_DSP_P ()" ++ "sclip32\t%0, %1, %2" ++ [(set_attr "type" "dclip") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "uclip32" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIP_OV))] ++ "NDS32_EXT_DSP_P ()" ++ "uclip32\t%0, %1, %2" ++ [(set_attr "type" "dclip") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "bitrev" ++ [(set (match_operand:SI 0 "register_operand" "=r, r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm5u_operand" " r, Iu05")] ++ UNSPEC_BITREV))] ++ "" ++ "@ ++ bitrev\t%0, %1, %2 ++ bitrevi\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")] ++) ++ ++;; wext, wexti ++(define_insn "wext" ++ [(set (match_operand:SI 0 "register_operand" "=r, r") ++ (truncate:SI ++ (shiftrt:DI ++ (match_operand:DI 1 "register_operand" " r, r") ++ (match_operand:SI 2 "nds32_rimm5u_operand" " r,Iu05"))))] ++ "NDS32_EXT_DSP_P ()" ++ "@ ++ wext\t%0, %1, %2 ++ wexti\t%0, %1, %2" ++ [(set_attr "type" "dwext") ++ (set_attr "length" "4")]) ++ ++;; 32-bit add/sub instruction: raddw and rsubw. ++(define_insn "rsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI ++ (ashiftrt:DI ++ (plus_minus:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) ++ (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "rw\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) ++ ++;; 32-bit add/sub instruction: uraddw and ursubw. ++(define_insn "ursi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI ++ (lshiftrt:DI ++ (plus_minus:DI ++ (zero_extend:DI (match_operand:SI 1 "register_operand" " r")) ++ (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))) ++ (const_int 1))))] ++ "NDS32_EXT_DSP_P ()" ++ "urw\t%0, %1, %2" ++ [(set_attr "type" "dalu") ++ (set_attr "length" "4")]) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-elf.opt gcc-8.2.0/gcc/config/nds32/nds32-elf.opt +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-elf.opt 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-elf.opt 2019-01-25 15:38:32.825242648 +0100 +@@ -0,0 +1,16 @@ ++mcmodel= ++Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_MEDIUM) ++Specify the address generation strategy for code model. ++ ++Enum ++Name(nds32_cmodel_type) Type(enum nds32_cmodel_type) ++Known cmodel types (for use with the -mcmodel= option): ++ ++EnumValue ++Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL) ++ ++EnumValue ++Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM) ++ ++EnumValue ++Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-fp-as-gp.c gcc-8.2.0/gcc/config/nds32/nds32-fp-as-gp.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-fp-as-gp.c 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-fp-as-gp.c 2019-01-25 15:38:32.825242648 +0100 +@@ -26,19 +26,256 @@ + #include "system.h" + #include "coretypes.h" + #include "backend.h" ++#include "hard-reg-set.h" ++#include "tm_p.h" ++#include "rtl.h" ++#include "memmodel.h" ++#include "emit-rtl.h" ++#include "insn-config.h" ++#include "regs.h" ++#include "hard-reg-set.h" ++#include "ira.h" ++#include "ira-int.h" ++#include "df.h" ++#include "tree-core.h" ++#include "tree-pass.h" ++#include "nds32-protos.h" + + /* ------------------------------------------------------------------------ */ + ++/* A helper function to check if this function should contain prologue. */ ++static bool ++nds32_have_prologue_p (void) ++{ ++ int i; ++ ++ for (i = 0; i < 28; i++) ++ if (NDS32_REQUIRED_CALLEE_SAVED_P (i)) ++ return true; ++ ++ return (flag_pic ++ || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM) ++ || NDS32_REQUIRED_CALLEE_SAVED_P (LP_REGNUM)); ++} ++ ++static int ++nds32_get_symbol_count (void) ++{ ++ int symbol_count = 0; ++ rtx_insn *insn; ++ basic_block bb; ++ ++ FOR_EACH_BB_FN (bb, cfun) ++ { ++ FOR_BB_INSNS (bb, insn) ++ { ++ /* Counting the insn number which the addressing mode is symbol. */ ++ if (single_set (insn) && nds32_symbol_load_store_p (insn)) ++ { ++ rtx pattern = PATTERN (insn); ++ rtx mem; ++ gcc_assert (GET_CODE (pattern) == SET); ++ if (GET_CODE (SET_SRC (pattern)) == REG ) ++ mem = SET_DEST (pattern); ++ else ++ mem = SET_SRC (pattern); ++ ++ /* We have only lwi37 and swi37 for fp-as-gp optimization, ++ so don't count any other than SImode. ++ MEM for QImode and HImode will wrap by ZERO_EXTEND ++ or SIGN_EXTEND */ ++ if (GET_CODE (mem) == MEM) ++ symbol_count++; ++ } ++ } ++ } ++ ++ return symbol_count; ++} ++ + /* Function to determine whether it is worth to do fp_as_gp optimization. +- Return 0: It is NOT worth to do fp_as_gp optimization. +- Return 1: It is APPROXIMATELY worth to do fp_as_gp optimization. ++ Return false: It is NOT worth to do fp_as_gp optimization. ++ Return true: It is APPROXIMATELY worth to do fp_as_gp optimization. + Note that if it is worth to do fp_as_gp optimization, + we MUST set FP_REGNUM ever live in this function. */ +-int ++static bool + nds32_fp_as_gp_check_available (void) + { +- /* By default we return 0. */ +- return 0; ++ basic_block bb; ++ basic_block exit_bb; ++ edge_iterator ei; ++ edge e; ++ bool first_exit_blocks_p; ++ ++ /* If there exists ANY of following conditions, ++ we DO NOT perform fp_as_gp optimization: ++ 1. TARGET_FORBID_FP_AS_GP is set ++ regardless of the TARGET_FORCE_FP_AS_GP. ++ 2. User explicitly uses 'naked'/'no_prologue' attribute. ++ We use nds32_naked_function_p() to help such checking. ++ 3. Not optimize for size. ++ 4. Need frame pointer. ++ 5. If $fp is already required to be saved, ++ it means $fp is already choosen by register allocator. ++ Thus we better not to use it for fp_as_gp optimization. ++ 6. This function is a vararg function. ++ DO NOT apply fp_as_gp optimization on this function ++ because it may change and break stack frame. ++ 7. The epilogue is empty. ++ This happens when the function uses exit() ++ or its attribute is no_return. ++ In that case, compiler will not expand epilogue ++ so that we have no chance to output .omit_fp_end directive. */ ++ if (TARGET_FORBID_FP_AS_GP ++ || nds32_naked_function_p (current_function_decl) ++ || !optimize_size ++ || frame_pointer_needed ++ || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM) ++ || (cfun->stdarg == 1) ++ || (find_fallthru_edge (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == NULL)) ++ return false; ++ ++ /* Disable fp_as_gp if there is any infinite loop since the fp may ++ reuse in infinite loops by register rename. ++ For check infinite loops we should make sure exit_bb is post dominate ++ all other basic blocks if there is no infinite loops. */ ++ first_exit_blocks_p = true; ++ exit_bb = NULL; ++ ++ FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) ++ { ++ /* More than one exit block also do not perform fp_as_gp optimization. */ ++ if (!first_exit_blocks_p) ++ return false; ++ ++ exit_bb = e->src; ++ first_exit_blocks_p = false; ++ } ++ ++ /* Not found exit_bb? just abort fp_as_gp! */ ++ if (!exit_bb) ++ return false; ++ ++ /* Each bb should post dominate by exit_bb if there is no infinite loop! */ ++ FOR_EACH_BB_FN (bb, cfun) ++ { ++ if (!dominated_by_p (CDI_POST_DOMINATORS, ++ bb, ++ exit_bb)) ++ return false; ++ } ++ ++ /* Now we can check the possibility of using fp_as_gp optimization. */ ++ if (TARGET_FORCE_FP_AS_GP) ++ { ++ /* User explicitly issues -mforce-fp-as-gp option. */ ++ return true; ++ } ++ else ++ { ++ /* In the following we are going to evaluate whether ++ it is worth to do fp_as_gp optimization. */ ++ bool good_gain = false; ++ int symbol_count; ++ ++ int threshold; ++ ++ /* We check if there already requires prologue. ++ Note that $gp will be saved in prologue for PIC code generation. ++ After that, we can set threshold by the existence of prologue. ++ Each fp-implied instruction will gain 2-byte code size ++ from gp-aware instruction, so we have following heuristics. */ ++ if (flag_pic ++ || nds32_have_prologue_p ()) ++ { ++ /* Have-prologue: ++ Compiler already intends to generate prologue content, ++ so the fp_as_gp optimization will only insert ++ 'la $fp,_FP_BASE_' instruction, which will be ++ converted into 4-byte instruction at link time. ++ The threshold is "3" symbol accesses, 2 + 2 + 2 > 4. */ ++ threshold = 3; ++ } ++ else ++ { ++ /* None-prologue: ++ Compiler originally does not generate prologue content, ++ so the fp_as_gp optimization will NOT ONLY insert ++ 'la $fp,_FP_BASE' instruction, but also causes ++ push/pop instructions. ++ If we are using v3push (push25/pop25), ++ the threshold is "5" symbol accesses, 5*2 > 4 + 2 + 2; ++ If we are using normal push (smw/lmw), ++ the threshold is "5+2" symbol accesses 7*2 > 4 + 4 + 4. */ ++ threshold = 5 + (TARGET_V3PUSH ? 0 : 2); ++ } ++ ++ symbol_count = nds32_get_symbol_count (); ++ ++ if (symbol_count >= threshold) ++ good_gain = true; ++ ++ /* Enable fp_as_gp optimization when potential gain is good enough. */ ++ return good_gain; ++ } ++} ++ ++static unsigned int ++nds32_fp_as_gp (void) ++{ ++ bool fp_as_gp_p; ++ calculate_dominance_info (CDI_POST_DOMINATORS); ++ fp_as_gp_p = nds32_fp_as_gp_check_available (); ++ ++ /* Here is a hack to IRA for enable/disable a hard register per function. ++ We *MUST* review this way after migrate gcc 4.9! */ ++ if (fp_as_gp_p) { ++ SET_HARD_REG_BIT(this_target_ira_int->x_no_unit_alloc_regs, FP_REGNUM); ++ df_set_regs_ever_live (FP_REGNUM, 1); ++ } else { ++ CLEAR_HARD_REG_BIT(this_target_ira_int->x_no_unit_alloc_regs, FP_REGNUM); ++ } ++ ++ cfun->machine->fp_as_gp_p = fp_as_gp_p; ++ ++ free_dominance_info (CDI_POST_DOMINATORS); ++ return 1; ++} ++ ++const pass_data pass_data_nds32_fp_as_gp = ++{ ++ RTL_PASS, /* type */ ++ "fp_as_gp", /* name */ ++ OPTGROUP_NONE, /* optinfo_flags */ ++ TV_MACH_DEP, /* tv_id */ ++ 0, /* properties_required */ ++ 0, /* properties_provided */ ++ 0, /* properties_destroyed */ ++ 0, /* todo_flags_start */ ++ 0 /* todo_flags_finish */ ++}; ++ ++class pass_nds32_fp_as_gp : public rtl_opt_pass ++{ ++public: ++ pass_nds32_fp_as_gp (gcc::context *ctxt) ++ : rtl_opt_pass (pass_data_nds32_fp_as_gp, ctxt) ++ {} ++ ++ /* opt_pass methods: */ ++ bool gate (function *) ++ { ++ return !TARGET_LINUX_ABI ++ && TARGET_16_BIT ++ && optimize_size; ++ } ++ unsigned int execute (function *) { return nds32_fp_as_gp (); } ++}; ++ ++rtl_opt_pass * ++make_pass_nds32_fp_as_gp (gcc::context *ctxt) ++{ ++ return new pass_nds32_fp_as_gp (ctxt); + } + + /* ------------------------------------------------------------------------ */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-fpu.md gcc-8.2.0/gcc/config/nds32/nds32-fpu.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-fpu.md 2018-04-06 07:51:33.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-fpu.md 2019-01-25 15:38:32.825242648 +0100 +@@ -1,5 +1,5 @@ + ;; Machine description of Andes NDS32 cpu for GNU compiler +-;; Copyright (C) 2012-2015 Free Software Foundation, Inc. ++;; Copyright (C) 2012-2018 Free Software Foundation, Inc. + ;; Contributed by Andes Technology Corporation. + ;; + ;; This file is part of GCC. +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-graywolf.md gcc-8.2.0/gcc/config/nds32/nds32-graywolf.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-graywolf.md 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-graywolf.md 2019-01-25 15:38:32.825242648 +0100 +@@ -0,0 +1,471 @@ ++;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler ++;; Copyright (C) 2012-2013 Free Software Foundation, Inc. ++;; Contributed by Andes Technology Corporation. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 3, or (at your ++;; option) any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++;; ------------------------------------------------------------------------ ++;; Define Graywolf pipeline settings. ++;; ------------------------------------------------------------------------ ++ ++(define_automaton "nds32_graywolf_machine") ++ ++(define_cpu_unit "gw_ii_0" "nds32_graywolf_machine") ++(define_cpu_unit "gw_ii_1" "nds32_graywolf_machine") ++(define_cpu_unit "gw_ex_p0" "nds32_graywolf_machine") ++(define_cpu_unit "gw_mm_p0" "nds32_graywolf_machine") ++(define_cpu_unit "gw_wb_p0" "nds32_graywolf_machine") ++(define_cpu_unit "gw_ex_p1" "nds32_graywolf_machine") ++(define_cpu_unit "gw_mm_p1" "nds32_graywolf_machine") ++(define_cpu_unit "gw_wb_p1" "nds32_graywolf_machine") ++(define_cpu_unit "gw_iq_p2" "nds32_graywolf_machine") ++(define_cpu_unit "gw_rf_p2" "nds32_graywolf_machine") ++(define_cpu_unit "gw_e1_p2" "nds32_graywolf_machine") ++(define_cpu_unit "gw_e2_p2" "nds32_graywolf_machine") ++(define_cpu_unit "gw_e3_p2" "nds32_graywolf_machine") ++(define_cpu_unit "gw_e4_p2" "nds32_graywolf_machine") ++ ++(define_reservation "gw_ii" "gw_ii_0 | gw_ii_1") ++(define_reservation "gw_ex" "gw_ex_p0 | gw_ex_p1") ++(define_reservation "gw_mm" "gw_mm_p0 | gw_mm_p1") ++(define_reservation "gw_wb" "gw_wb_p0 | gw_wb_p1") ++ ++(define_reservation "gw_ii_all" "gw_ii_0 + gw_ii_1") ++ ++(define_insn_reservation "nds_gw_unknown" 1 ++ (and (eq_attr "type" "unknown") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_misc" 1 ++ (and (eq_attr "type" "misc") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_mmu" 1 ++ (and (eq_attr "type" "mmu") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_alu" 1 ++ (and (and (eq_attr "type" "alu") ++ (match_test "!nds32::movd44_insn_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_movd44" 1 ++ (and (and (eq_attr "type" "alu") ++ (match_test "nds32::movd44_insn_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_alu_shift" 1 ++ (and (eq_attr "type" "alu_shift") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex*2, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_pbsad" 1 ++ (and (eq_attr "type" "pbsad") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex*3, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_pbsada" 1 ++ (and (eq_attr "type" "pbsada") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex*3, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_load" 1 ++ (and (and (eq_attr "type" "load") ++ (match_test "!nds32::post_update_insn_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_2w" 1 ++ (and (and (eq_attr "type" "load") ++ (match_test "nds32::post_update_insn_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store" 1 ++ (and (and (eq_attr "type" "store") ++ (match_test "!nds32::store_offset_reg_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_3r" 1 ++ (and (and (eq_attr "type" "store") ++ (match_test "nds32::store_offset_reg_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_1" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "1")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_2" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "2")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_3" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "3")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_4" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "4")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_5" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "5")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_6" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "6")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_7" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "7")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_8" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "8")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_load_multiple_12" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "12")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_1" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "1")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_2" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "2")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_3" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "3")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_4" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "4")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_5" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "5")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_6" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "6")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_7" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "7")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_8" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "8")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_store_multiple_12" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "12")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") ++ ++(define_insn_reservation "nds_gw_mul_fast1" 1 ++ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") ++ (and (eq_attr "type" "mul") ++ (eq_attr "pipeline_model" "graywolf"))) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_mul_fast2" 1 ++ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") ++ (and (eq_attr "type" "mul") ++ (eq_attr "pipeline_model" "graywolf"))) ++ "gw_ii_0, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_mul_slow" 1 ++ (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") ++ (and (eq_attr "type" "mul") ++ (eq_attr "pipeline_model" "graywolf"))) ++ "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_mac_fast1" 1 ++ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") ++ (and (eq_attr "type" "mac") ++ (eq_attr "pipeline_model" "graywolf"))) ++ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_mac_fast2" 1 ++ (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") ++ (and (eq_attr "type" "mac") ++ (eq_attr "pipeline_model" "graywolf"))) ++ "gw_ii_all, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_mac_slow" 1 ++ (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") ++ (and (eq_attr "type" "mac") ++ (eq_attr "pipeline_model" "graywolf"))) ++ "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_div" 1 ++ (and (and (eq_attr "type" "div") ++ (match_test "!nds32::divmod_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_div_2w" 1 ++ (and (and (eq_attr "type" "div") ++ (match_test "nds32::divmod_p (insn)")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_branch" 1 ++ (and (eq_attr "type" "branch") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_alu" 1 ++ (and (eq_attr "type" "dalu") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ex, gw_mm, gw_wb") ++ ++(define_insn_reservation "nds_gw_dsp_alu64" 1 ++ (and (eq_attr "type" "dalu64") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_alu_round" 1 ++ (and (eq_attr "type" "daluround") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_cmp" 1 ++ (and (eq_attr "type" "dcmp") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_clip" 1 ++ (and (eq_attr "type" "dclip") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_mul" 1 ++ (and (eq_attr "type" "dmul") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_mac" 1 ++ (and (eq_attr "type" "dmac") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_insb" 1 ++ (and (eq_attr "type" "dinsb") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_pack" 1 ++ (and (eq_attr "type" "dpack") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_bpick" 1 ++ (and (eq_attr "type" "dbpick") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_dsp_wext" 1 ++ (and (eq_attr "type" "dwext") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") ++ ++(define_insn_reservation "nds_gw_fpu_alu" 4 ++ (and (eq_attr "type" "falu") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_muls" 4 ++ (and (eq_attr "type" "fmuls") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_muld" 4 ++ (and (eq_attr "type" "fmuld") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*2, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_macs" 4 ++ (and (eq_attr "type" "fmacs") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*3, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_macd" 4 ++ (and (eq_attr "type" "fmacd") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*4, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_divs" 4 ++ (and (ior (eq_attr "type" "fdivs") ++ (eq_attr "type" "fsqrts")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*14, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_divd" 4 ++ (and (ior (eq_attr "type" "fdivd") ++ (eq_attr "type" "fsqrtd")) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*28, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_fast_alu" 2 ++ (and (ior (eq_attr "type" "fcmp") ++ (ior (eq_attr "type" "fabs") ++ (ior (eq_attr "type" "fcpy") ++ (eq_attr "type" "fcmov")))) ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_fmtsr" 1 ++ (and (eq_attr "type" "fmtsr") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_fmtdr" 1 ++ (and (eq_attr "type" "fmtdr") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_fmfsr" 1 ++ (and (eq_attr "type" "fmfsr") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_fmfdr" 1 ++ (and (eq_attr "type" "fmfdr") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_load" 3 ++ (and (eq_attr "type" "fload") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") ++ ++(define_insn_reservation "nds_gw_fpu_store" 1 ++ (and (eq_attr "type" "fstore") ++ (eq_attr "pipeline_model" "graywolf")) ++ "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") ++ ++;; FPU_ADDR_OUT -> FPU_ADDR_IN ++;; Main pipeline rules don't need this because those default latency is 1. ++(define_bypass 1 ++ "nds_gw_fpu_load, nds_gw_fpu_store" ++ "nds_gw_fpu_load, nds_gw_fpu_store" ++ "nds32_gw_ex_to_ex_p" ++) ++ ++;; LD, MUL, MAC, DIV, DALU64, DMUL, DMAC, DALUROUND, DBPICK, DWEXT ++;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU, ++;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb ++(define_bypass 2 ++ "nds_gw_load, nds_gw_load_2w,\ ++ nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ ++ nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ ++ nds_gw_div, nds_gw_div_2w,\ ++ nds_gw_dsp_alu64, nds_gw_dsp_mul, nds_gw_dsp_mac,\ ++ nds_gw_dsp_alu_round, nds_gw_dsp_bpick, nds_gw_dsp_wext" ++ "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ ++ nds_gw_pbsad, nds_gw_pbsada,\ ++ nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ ++ nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ ++ nds_gw_branch,\ ++ nds_gw_div, nds_gw_div_2w,\ ++ nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ ++ nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ ++ nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ ++ nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ ++ nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ ++ nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ ++ nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ ++ nds_gw_mmu,\ ++ nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ ++ nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ ++ nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ ++ nds_gw_dsp_wext, nds_gw_dsp_bpick" ++ "nds32_gw_mm_to_ex_p" ++) ++ ++;; LMW(N, N) ++;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU ++;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb ++(define_bypass 2 ++ "nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ ++ nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ ++ nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12" ++ "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ ++ nds_gw_pbsad, nds_gw_pbsada,\ ++ nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ ++ nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ ++ nds_gw_branch,\ ++ nds_gw_div, nds_gw_div_2w,\ ++ nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ ++ nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ ++ nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ ++ nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ ++ nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ ++ nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ ++ nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ ++ nds_gw_mmu,\ ++ nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ ++ nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ ++ nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ ++ nds_gw_dsp_wext, nds_gw_dsp_bpick" ++ "nds32_gw_last_load_to_ex_p" ++) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.h gcc-8.2.0/gcc/config/nds32/nds32.h +--- gcc-8.2.0.orig/gcc/config/nds32/nds32.h 2018-05-07 03:27:52.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32.h 2019-01-25 15:44:03.534160189 +0100 +@@ -36,6 +36,16 @@ + #define NDS32_SYMBOL_REF_RODATA_P(x) \ + ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0) + ++enum nds32_relax_insn_type ++{ ++ RELAX_ORI, ++ RELAX_PLT_ADD, ++ RELAX_TLS_ADD_or_LW, ++ RELAX_TLS_ADD_LW, ++ RELAX_TLS_LW_JRAL, ++ RELAX_DONE ++}; ++ + /* Classifies expand result for expand helper function. */ + enum nds32_expand_result_type + { +@@ -140,6 +150,9 @@ + Check gcc/common/config/nds32/nds32-common.c for the optimizations that + apply -malways-align. */ + #define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN) ++ ++#define NDS32_EXT_DSP_P() (TARGET_EXT_DSP && !TARGET_FORCE_NO_EXT_DSP) ++ + /* Get alignment according to mode or type information. + When 'type' is nonnull, there is no need to look at 'mode'. */ + #define NDS32_MODE_TYPE_ALIGN(mode, type) \ +@@ -305,6 +318,10 @@ + 2. The rtl lowering and optimization are close to target code. + For this case we need address to be strictly aligned. */ + int strict_aligned_p; ++ ++ /* Record two similar attributes status. */ ++ int attr_naked_p; ++ int attr_no_prologue_p; + }; + + /* A C structure that contains the arguments information. */ +@@ -350,7 +367,8 @@ + { + NDS32_NESTED, + NDS32_NOT_NESTED, +- NDS32_NESTED_READY ++ NDS32_NESTED_READY, ++ NDS32_CRITICAL + }; + + /* Define structure to record isr information. +@@ -378,6 +396,13 @@ + unless user specifies attribute to change it. */ + enum nds32_isr_nested_type nested_type; + ++ /* Secure isr level. ++ Currently we have 0-3 security level. ++ It should be set to 0 by default. ++ For security processors, this is determined by secure ++ attribute or compiler options. */ ++ unsigned int security_level; ++ + /* Total vectors. + The total vectors = interrupt + exception numbers + reset. + It should be set to 0 by default. +@@ -439,7 +464,30 @@ + NDS32_BUILTIN_FFB, + NDS32_BUILTIN_FFMISM, + NDS32_BUILTIN_FLMISM, +- ++ NDS32_BUILTIN_KADDW, ++ NDS32_BUILTIN_KSUBW, ++ NDS32_BUILTIN_KADDH, ++ NDS32_BUILTIN_KSUBH, ++ NDS32_BUILTIN_KDMBB, ++ NDS32_BUILTIN_V_KDMBB, ++ NDS32_BUILTIN_KDMBT, ++ NDS32_BUILTIN_V_KDMBT, ++ NDS32_BUILTIN_KDMTB, ++ NDS32_BUILTIN_V_KDMTB, ++ NDS32_BUILTIN_KDMTT, ++ NDS32_BUILTIN_V_KDMTT, ++ NDS32_BUILTIN_KHMBB, ++ NDS32_BUILTIN_V_KHMBB, ++ NDS32_BUILTIN_KHMBT, ++ NDS32_BUILTIN_V_KHMBT, ++ NDS32_BUILTIN_KHMTB, ++ NDS32_BUILTIN_V_KHMTB, ++ NDS32_BUILTIN_KHMTT, ++ NDS32_BUILTIN_V_KHMTT, ++ NDS32_BUILTIN_KSLRAW, ++ NDS32_BUILTIN_KSLRAW_U, ++ NDS32_BUILTIN_RDOV, ++ NDS32_BUILTIN_CLROV, + NDS32_BUILTIN_ROTR, + NDS32_BUILTIN_SVA, + NDS32_BUILTIN_SVS, +@@ -512,7 +560,295 @@ + NDS32_BUILTIN_SET_TRIG_LEVEL, + NDS32_BUILTIN_SET_TRIG_EDGE, + NDS32_BUILTIN_GET_TRIG_TYPE, +- ++ NDS32_BUILTIN_DSP_BEGIN, ++ NDS32_BUILTIN_ADD16, ++ NDS32_BUILTIN_V_UADD16, ++ NDS32_BUILTIN_V_SADD16, ++ NDS32_BUILTIN_RADD16, ++ NDS32_BUILTIN_V_RADD16, ++ NDS32_BUILTIN_URADD16, ++ NDS32_BUILTIN_V_URADD16, ++ NDS32_BUILTIN_KADD16, ++ NDS32_BUILTIN_V_KADD16, ++ NDS32_BUILTIN_UKADD16, ++ NDS32_BUILTIN_V_UKADD16, ++ NDS32_BUILTIN_SUB16, ++ NDS32_BUILTIN_V_USUB16, ++ NDS32_BUILTIN_V_SSUB16, ++ NDS32_BUILTIN_RSUB16, ++ NDS32_BUILTIN_V_RSUB16, ++ NDS32_BUILTIN_URSUB16, ++ NDS32_BUILTIN_V_URSUB16, ++ NDS32_BUILTIN_KSUB16, ++ NDS32_BUILTIN_V_KSUB16, ++ NDS32_BUILTIN_UKSUB16, ++ NDS32_BUILTIN_V_UKSUB16, ++ NDS32_BUILTIN_CRAS16, ++ NDS32_BUILTIN_V_UCRAS16, ++ NDS32_BUILTIN_V_SCRAS16, ++ NDS32_BUILTIN_RCRAS16, ++ NDS32_BUILTIN_V_RCRAS16, ++ NDS32_BUILTIN_URCRAS16, ++ NDS32_BUILTIN_V_URCRAS16, ++ NDS32_BUILTIN_KCRAS16, ++ NDS32_BUILTIN_V_KCRAS16, ++ NDS32_BUILTIN_UKCRAS16, ++ NDS32_BUILTIN_V_UKCRAS16, ++ NDS32_BUILTIN_CRSA16, ++ NDS32_BUILTIN_V_UCRSA16, ++ NDS32_BUILTIN_V_SCRSA16, ++ NDS32_BUILTIN_RCRSA16, ++ NDS32_BUILTIN_V_RCRSA16, ++ NDS32_BUILTIN_URCRSA16, ++ NDS32_BUILTIN_V_URCRSA16, ++ NDS32_BUILTIN_KCRSA16, ++ NDS32_BUILTIN_V_KCRSA16, ++ NDS32_BUILTIN_UKCRSA16, ++ NDS32_BUILTIN_V_UKCRSA16, ++ NDS32_BUILTIN_ADD8, ++ NDS32_BUILTIN_V_UADD8, ++ NDS32_BUILTIN_V_SADD8, ++ NDS32_BUILTIN_RADD8, ++ NDS32_BUILTIN_V_RADD8, ++ NDS32_BUILTIN_URADD8, ++ NDS32_BUILTIN_V_URADD8, ++ NDS32_BUILTIN_KADD8, ++ NDS32_BUILTIN_V_KADD8, ++ NDS32_BUILTIN_UKADD8, ++ NDS32_BUILTIN_V_UKADD8, ++ NDS32_BUILTIN_SUB8, ++ NDS32_BUILTIN_V_USUB8, ++ NDS32_BUILTIN_V_SSUB8, ++ NDS32_BUILTIN_RSUB8, ++ NDS32_BUILTIN_V_RSUB8, ++ NDS32_BUILTIN_URSUB8, ++ NDS32_BUILTIN_V_URSUB8, ++ NDS32_BUILTIN_KSUB8, ++ NDS32_BUILTIN_V_KSUB8, ++ NDS32_BUILTIN_UKSUB8, ++ NDS32_BUILTIN_V_UKSUB8, ++ NDS32_BUILTIN_SRA16, ++ NDS32_BUILTIN_V_SRA16, ++ NDS32_BUILTIN_SRA16_U, ++ NDS32_BUILTIN_V_SRA16_U, ++ NDS32_BUILTIN_SRL16, ++ NDS32_BUILTIN_V_SRL16, ++ NDS32_BUILTIN_SRL16_U, ++ NDS32_BUILTIN_V_SRL16_U, ++ NDS32_BUILTIN_SLL16, ++ NDS32_BUILTIN_V_SLL16, ++ NDS32_BUILTIN_KSLL16, ++ NDS32_BUILTIN_V_KSLL16, ++ NDS32_BUILTIN_KSLRA16, ++ NDS32_BUILTIN_V_KSLRA16, ++ NDS32_BUILTIN_KSLRA16_U, ++ NDS32_BUILTIN_V_KSLRA16_U, ++ NDS32_BUILTIN_CMPEQ16, ++ NDS32_BUILTIN_V_SCMPEQ16, ++ NDS32_BUILTIN_V_UCMPEQ16, ++ NDS32_BUILTIN_SCMPLT16, ++ NDS32_BUILTIN_V_SCMPLT16, ++ NDS32_BUILTIN_SCMPLE16, ++ NDS32_BUILTIN_V_SCMPLE16, ++ NDS32_BUILTIN_UCMPLT16, ++ NDS32_BUILTIN_V_UCMPLT16, ++ NDS32_BUILTIN_UCMPLE16, ++ NDS32_BUILTIN_V_UCMPLE16, ++ NDS32_BUILTIN_CMPEQ8, ++ NDS32_BUILTIN_V_SCMPEQ8, ++ NDS32_BUILTIN_V_UCMPEQ8, ++ NDS32_BUILTIN_SCMPLT8, ++ NDS32_BUILTIN_V_SCMPLT8, ++ NDS32_BUILTIN_SCMPLE8, ++ NDS32_BUILTIN_V_SCMPLE8, ++ NDS32_BUILTIN_UCMPLT8, ++ NDS32_BUILTIN_V_UCMPLT8, ++ NDS32_BUILTIN_UCMPLE8, ++ NDS32_BUILTIN_V_UCMPLE8, ++ NDS32_BUILTIN_SMIN16, ++ NDS32_BUILTIN_V_SMIN16, ++ NDS32_BUILTIN_UMIN16, ++ NDS32_BUILTIN_V_UMIN16, ++ NDS32_BUILTIN_SMAX16, ++ NDS32_BUILTIN_V_SMAX16, ++ NDS32_BUILTIN_UMAX16, ++ NDS32_BUILTIN_V_UMAX16, ++ NDS32_BUILTIN_SCLIP16, ++ NDS32_BUILTIN_V_SCLIP16, ++ NDS32_BUILTIN_UCLIP16, ++ NDS32_BUILTIN_V_UCLIP16, ++ NDS32_BUILTIN_KHM16, ++ NDS32_BUILTIN_V_KHM16, ++ NDS32_BUILTIN_KHMX16, ++ NDS32_BUILTIN_V_KHMX16, ++ NDS32_BUILTIN_KABS16, ++ NDS32_BUILTIN_V_KABS16, ++ NDS32_BUILTIN_SMIN8, ++ NDS32_BUILTIN_V_SMIN8, ++ NDS32_BUILTIN_UMIN8, ++ NDS32_BUILTIN_V_UMIN8, ++ NDS32_BUILTIN_SMAX8, ++ NDS32_BUILTIN_V_SMAX8, ++ NDS32_BUILTIN_UMAX8, ++ NDS32_BUILTIN_V_UMAX8, ++ NDS32_BUILTIN_KABS8, ++ NDS32_BUILTIN_V_KABS8, ++ NDS32_BUILTIN_SUNPKD810, ++ NDS32_BUILTIN_V_SUNPKD810, ++ NDS32_BUILTIN_SUNPKD820, ++ NDS32_BUILTIN_V_SUNPKD820, ++ NDS32_BUILTIN_SUNPKD830, ++ NDS32_BUILTIN_V_SUNPKD830, ++ NDS32_BUILTIN_SUNPKD831, ++ NDS32_BUILTIN_V_SUNPKD831, ++ NDS32_BUILTIN_ZUNPKD810, ++ NDS32_BUILTIN_V_ZUNPKD810, ++ NDS32_BUILTIN_ZUNPKD820, ++ NDS32_BUILTIN_V_ZUNPKD820, ++ NDS32_BUILTIN_ZUNPKD830, ++ NDS32_BUILTIN_V_ZUNPKD830, ++ NDS32_BUILTIN_ZUNPKD831, ++ NDS32_BUILTIN_V_ZUNPKD831, ++ NDS32_BUILTIN_RADDW, ++ NDS32_BUILTIN_URADDW, ++ NDS32_BUILTIN_RSUBW, ++ NDS32_BUILTIN_URSUBW, ++ NDS32_BUILTIN_SRA_U, ++ NDS32_BUILTIN_KSLL, ++ NDS32_BUILTIN_PKBB16, ++ NDS32_BUILTIN_V_PKBB16, ++ NDS32_BUILTIN_PKBT16, ++ NDS32_BUILTIN_V_PKBT16, ++ NDS32_BUILTIN_PKTB16, ++ NDS32_BUILTIN_V_PKTB16, ++ NDS32_BUILTIN_PKTT16, ++ NDS32_BUILTIN_V_PKTT16, ++ NDS32_BUILTIN_SMMUL, ++ NDS32_BUILTIN_SMMUL_U, ++ NDS32_BUILTIN_KMMAC, ++ NDS32_BUILTIN_KMMAC_U, ++ NDS32_BUILTIN_KMMSB, ++ NDS32_BUILTIN_KMMSB_U, ++ NDS32_BUILTIN_KWMMUL, ++ NDS32_BUILTIN_KWMMUL_U, ++ NDS32_BUILTIN_SMMWB, ++ NDS32_BUILTIN_V_SMMWB, ++ NDS32_BUILTIN_SMMWB_U, ++ NDS32_BUILTIN_V_SMMWB_U, ++ NDS32_BUILTIN_SMMWT, ++ NDS32_BUILTIN_V_SMMWT, ++ NDS32_BUILTIN_SMMWT_U, ++ NDS32_BUILTIN_V_SMMWT_U, ++ NDS32_BUILTIN_KMMAWB, ++ NDS32_BUILTIN_V_KMMAWB, ++ NDS32_BUILTIN_KMMAWB_U, ++ NDS32_BUILTIN_V_KMMAWB_U, ++ NDS32_BUILTIN_KMMAWT, ++ NDS32_BUILTIN_V_KMMAWT, ++ NDS32_BUILTIN_KMMAWT_U, ++ NDS32_BUILTIN_V_KMMAWT_U, ++ NDS32_BUILTIN_SMBB, ++ NDS32_BUILTIN_V_SMBB, ++ NDS32_BUILTIN_SMBT, ++ NDS32_BUILTIN_V_SMBT, ++ NDS32_BUILTIN_SMTT, ++ NDS32_BUILTIN_V_SMTT, ++ NDS32_BUILTIN_KMDA, ++ NDS32_BUILTIN_V_KMDA, ++ NDS32_BUILTIN_KMXDA, ++ NDS32_BUILTIN_V_KMXDA, ++ NDS32_BUILTIN_SMDS, ++ NDS32_BUILTIN_V_SMDS, ++ NDS32_BUILTIN_SMDRS, ++ NDS32_BUILTIN_V_SMDRS, ++ NDS32_BUILTIN_SMXDS, ++ NDS32_BUILTIN_V_SMXDS, ++ NDS32_BUILTIN_KMABB, ++ NDS32_BUILTIN_V_KMABB, ++ NDS32_BUILTIN_KMABT, ++ NDS32_BUILTIN_V_KMABT, ++ NDS32_BUILTIN_KMATT, ++ NDS32_BUILTIN_V_KMATT, ++ NDS32_BUILTIN_KMADA, ++ NDS32_BUILTIN_V_KMADA, ++ NDS32_BUILTIN_KMAXDA, ++ NDS32_BUILTIN_V_KMAXDA, ++ NDS32_BUILTIN_KMADS, ++ NDS32_BUILTIN_V_KMADS, ++ NDS32_BUILTIN_KMADRS, ++ NDS32_BUILTIN_V_KMADRS, ++ NDS32_BUILTIN_KMAXDS, ++ NDS32_BUILTIN_V_KMAXDS, ++ NDS32_BUILTIN_KMSDA, ++ NDS32_BUILTIN_V_KMSDA, ++ NDS32_BUILTIN_KMSXDA, ++ NDS32_BUILTIN_V_KMSXDA, ++ NDS32_BUILTIN_SMAL, ++ NDS32_BUILTIN_V_SMAL, ++ NDS32_BUILTIN_BITREV, ++ NDS32_BUILTIN_WEXT, ++ NDS32_BUILTIN_BPICK, ++ NDS32_BUILTIN_INSB, ++ NDS32_BUILTIN_SADD64, ++ NDS32_BUILTIN_UADD64, ++ NDS32_BUILTIN_RADD64, ++ NDS32_BUILTIN_URADD64, ++ NDS32_BUILTIN_KADD64, ++ NDS32_BUILTIN_UKADD64, ++ NDS32_BUILTIN_SSUB64, ++ NDS32_BUILTIN_USUB64, ++ NDS32_BUILTIN_RSUB64, ++ NDS32_BUILTIN_URSUB64, ++ NDS32_BUILTIN_KSUB64, ++ NDS32_BUILTIN_UKSUB64, ++ NDS32_BUILTIN_SMAR64, ++ NDS32_BUILTIN_SMSR64, ++ NDS32_BUILTIN_UMAR64, ++ NDS32_BUILTIN_UMSR64, ++ NDS32_BUILTIN_KMAR64, ++ NDS32_BUILTIN_KMSR64, ++ NDS32_BUILTIN_UKMAR64, ++ NDS32_BUILTIN_UKMSR64, ++ NDS32_BUILTIN_SMALBB, ++ NDS32_BUILTIN_V_SMALBB, ++ NDS32_BUILTIN_SMALBT, ++ NDS32_BUILTIN_V_SMALBT, ++ NDS32_BUILTIN_SMALTT, ++ NDS32_BUILTIN_V_SMALTT, ++ NDS32_BUILTIN_SMALDA, ++ NDS32_BUILTIN_V_SMALDA, ++ NDS32_BUILTIN_SMALXDA, ++ NDS32_BUILTIN_V_SMALXDA, ++ NDS32_BUILTIN_SMALDS, ++ NDS32_BUILTIN_V_SMALDS, ++ NDS32_BUILTIN_SMALDRS, ++ NDS32_BUILTIN_V_SMALDRS, ++ NDS32_BUILTIN_SMALXDS, ++ NDS32_BUILTIN_V_SMALXDS, ++ NDS32_BUILTIN_SMUL16, ++ NDS32_BUILTIN_V_SMUL16, ++ NDS32_BUILTIN_SMULX16, ++ NDS32_BUILTIN_V_SMULX16, ++ NDS32_BUILTIN_UMUL16, ++ NDS32_BUILTIN_V_UMUL16, ++ NDS32_BUILTIN_UMULX16, ++ NDS32_BUILTIN_V_UMULX16, ++ NDS32_BUILTIN_SMSLDA, ++ NDS32_BUILTIN_V_SMSLDA, ++ NDS32_BUILTIN_SMSLXDA, ++ NDS32_BUILTIN_V_SMSLXDA, ++ NDS32_BUILTIN_UCLIP32, ++ NDS32_BUILTIN_SCLIP32, ++ NDS32_BUILTIN_KABS, ++ NDS32_BUILTIN_UALOAD_U16, ++ NDS32_BUILTIN_UALOAD_S16, ++ NDS32_BUILTIN_UALOAD_U8, ++ NDS32_BUILTIN_UALOAD_S8, ++ NDS32_BUILTIN_UASTORE_U16, ++ NDS32_BUILTIN_UASTORE_S16, ++ NDS32_BUILTIN_UASTORE_U8, ++ NDS32_BUILTIN_UASTORE_S8, ++ NDS32_BUILTIN_DSP_END, + NDS32_BUILTIN_UNALIGNED_FEATURE, + NDS32_BUILTIN_ENABLE_UNALIGNED, + NDS32_BUILTIN_DISABLE_UNALIGNED, +@@ -521,16 +857,30 @@ + + /* ------------------------------------------------------------------------ */ + +-#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) ++#define TARGET_ISR_VECTOR_SIZE_4_BYTE \ ++ (nds32_isr_vector_size == 4) + ++#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) + #define TARGET_ISA_V3 \ + (nds32_arch_option == ARCH_V3 \ ++ || nds32_arch_option == ARCH_V3J \ + || nds32_arch_option == ARCH_V3F \ + || nds32_arch_option == ARCH_V3S) + #define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M) + ++#define TARGET_PIPELINE_N7 \ ++ (nds32_cpu_option == CPU_N7) ++#define TARGET_PIPELINE_N8 \ ++ (nds32_cpu_option == CPU_N6 \ ++ || nds32_cpu_option == CPU_N8) + #define TARGET_PIPELINE_N9 \ + (nds32_cpu_option == CPU_N9) ++#define TARGET_PIPELINE_N10 \ ++ (nds32_cpu_option == CPU_N10) ++#define TARGET_PIPELINE_N13 \ ++ (nds32_cpu_option == CPU_N12 || nds32_cpu_option == CPU_N13) ++#define TARGET_PIPELINE_GRAYWOLF \ ++ (nds32_cpu_option == CPU_GRAYWOLF) + #define TARGET_PIPELINE_SIMPLE \ + (nds32_cpu_option == CPU_SIMPLE) + +@@ -541,6 +891,12 @@ + #define TARGET_CMODEL_LARGE \ + (nds32_cmodel_option == CMODEL_LARGE) + ++#define TARGET_ICT_MODEL_SMALL \ ++ (nds32_ict_model == ICT_MODEL_SMALL) ++ ++#define TARGET_ICT_MODEL_LARGE \ ++ (nds32_ict_model == ICT_MODEL_LARGE) ++ + /* When -mcmodel=small or -mcmodel=medium, + compiler may generate gp-base instruction directly. */ + #define TARGET_GP_DIRECT \ +@@ -576,6 +932,21 @@ + #endif + + #define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2 ++ ++/* ------------------------------------------------------------------------ */ ++ ++#ifdef TARGET_DEFAULT_RELAX ++# define NDS32_RELAX_SPEC " %{!mno-relax:--relax}" ++#else ++# define NDS32_RELAX_SPEC " %{mrelax:--relax}" ++#endif ++ ++#ifdef TARGET_DEFAULT_EXT_DSP ++# define NDS32_EXT_DSP_SPEC " %{!mno-ext-dsp:-mext-dsp}" ++#else ++# define NDS32_EXT_DSP_SPEC "" ++#endif ++ + /* ------------------------------------------------------------------------ */ + + /* Controlling the Compilation Driver. */ +@@ -591,11 +962,15 @@ + {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" } + + #define CC1_SPEC \ +- "" ++ NDS32_EXT_DSP_SPEC + + #define ASM_SPEC \ + " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ + " %{march=*:-march=%*}" \ ++ " %{mno-16-bit|mno-16bit:-mno-16bit-ext}" \ ++ " %{march=v3m:%{!mfull-regs:%{!mreduced-regs:-mreduced-regs}}}" \ ++ " %{mfull-regs:-mno-reduced-regs}" \ ++ " %{mreduced-regs:-mreduced-regs}" \ + " %{mabi=*:-mabi=v%*}" \ + " %{mconfig-fpu=*:-mfpu-freg=%*}" \ + " %{mext-fpu-mac:-mmac}" \ +@@ -603,35 +978,9 @@ + " %{mext-fpu-sp:-mfpu-sp-ext}" \ + " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \ + " %{mext-fpu-dp:-mfpu-dp-ext}" \ +- " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" +- +-/* If user issues -mrelax, we need to pass '--relax' to linker. */ +-#define LINK_SPEC \ +- " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ +- " %{mrelax:--relax}" +- +-#define LIB_SPEC \ +- " -lc -lgloss" +- +-/* The option -mno-ctor-dtor can disable constructor/destructor feature +- by applying different crt stuff. In the convention, crt0.o is the +- startup file without constructor/destructor; +- crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the +- startup files with constructor/destructor. +- Note that crt0.o, crt1.o, crti.o, and crtn.o are provided +- by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are +- currently provided by GCC for nds32 target. +- +- For nds32 target so far: +- If -mno-ctor-dtor, we are going to link +- "crt0.o [user objects]". +- If general cases, we are going to link +- "crt1.o crtbegin1.o [user objects] crtend1.o". */ +-#define STARTFILE_SPEC \ +- " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ +- " %{!mno-ctor-dtor:crtbegin1.o%s}" +-#define ENDFILE_SPEC \ +- " %{!mno-ctor-dtor:crtend1.o%s}" ++ " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" \ ++ " %{mext-dsp:-mdsp-ext}" \ ++ " %{O|O1|O2|O3|Ofast:-O1;:-Os}" + + /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we + configure gcc with --target=nds32be-* setting. +@@ -642,9 +991,11 @@ + # define NDS32_ENDIAN_DEFAULT "mlittle-endian" + #endif + +-/* Currently we only have elf toolchain, +- where -mcmodel=medium is always the default. */ +-#define NDS32_CMODEL_DEFAULT "mcmodel=medium" ++#if TARGET_ELF ++# define NDS32_CMODEL_DEFAULT "mcmodel=medium" ++#else ++# define NDS32_CMODEL_DEFAULT "mcmodel=large" ++#endif + + #define MULTILIB_DEFAULTS \ + { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT } +@@ -1139,6 +1490,11 @@ + + #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM + ++#define SYMBOLIC_CONST_P(X) \ ++(GET_CODE (X) == SYMBOL_REF \ ++ || GET_CODE (X) == LABEL_REF \ ++ || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) ++ + + /* Defining the Output Assembler Language. */ + +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32_init.inc gcc-8.2.0/gcc/config/nds32/nds32_init.inc +--- gcc-8.2.0.orig/gcc/config/nds32/nds32_init.inc 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32_init.inc 2019-01-25 15:38:32.833242671 +0100 +@@ -0,0 +1,43 @@ ++/* ++ * nds32_init.inc ++ * ++ * NDS32 architecture startup assembler header file ++ * ++ */ ++ ++.macro nds32_init ++ ++ ! Initialize GP for data access ++ la $gp, _SDA_BASE_ ++ ++#if defined(__NDS32_EXT_EX9__) ++ ! Check HW for EX9 ++ mfsr $r0, $MSC_CFG ++ li $r1, (1 << 24) ++ and $r2, $r0, $r1 ++ beqz $r2, 1f ++ ++ ! Initialize the table base of EX9 instruction ++ la $r0, _ITB_BASE_ ++ mtusr $r0, $ITB ++1: ++#endif ++ ++#if defined(__NDS32_EXT_FPU_DP__) || defined(__NDS32_EXT_FPU_SP__) ++ ! Enable FPU ++ mfsr $r0, $FUCOP_CTL ++ ori $r0, $r0, #0x1 ++ mtsr $r0, $FUCOP_CTL ++ dsb ++ ++ ! Enable denormalized flush-to-Zero mode ++ fmfcsr $r0 ++ ori $r0,$r0,#0x1000 ++ fmtcsr $r0 ++ dsb ++#endif ++ ++ ! Initialize default stack pointer ++ la $sp, _stack ++ ++.endm +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.c gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.c 2018-04-22 09:46:39.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.c 2019-01-25 15:38:32.825242648 +0100 +@@ -519,6 +519,7 @@ + { + NDS32_BUILTIN(unspec_fmfcfg, "fmfcfg", FMFCFG) + NDS32_BUILTIN(unspec_fmfcsr, "fmfcsr", FMFCSR) ++ NDS32_BUILTIN(unspec_volatile_rdov, "rdov", RDOV) + NDS32_BUILTIN(unspec_get_current_sp, "get_current_sp", GET_CURRENT_SP) + NDS32_BUILTIN(unspec_return_address, "return_address", RETURN_ADDRESS) + NDS32_BUILTIN(unspec_get_all_pending_int, "get_all_pending_int", +@@ -558,6 +559,31 @@ + NDS32_NO_TARGET_BUILTIN(unspec_ret_itoff, "ret_itoff", RET_ITOFF) + NDS32_NO_TARGET_BUILTIN(unspec_set_current_sp, + "set_current_sp", SET_CURRENT_SP) ++ NDS32_BUILTIN(kabsv2hi2, "kabs16", KABS16) ++ NDS32_BUILTIN(kabsv2hi2, "v_kabs16", V_KABS16) ++ NDS32_BUILTIN(kabsv4qi2, "kabs8", KABS8) ++ NDS32_BUILTIN(kabsv4qi2, "v_kabs8", V_KABS8) ++ NDS32_BUILTIN(sunpkd810, "sunpkd810", SUNPKD810) ++ NDS32_BUILTIN(sunpkd810, "v_sunpkd810", V_SUNPKD810) ++ NDS32_BUILTIN(sunpkd820, "sunpkd820", SUNPKD820) ++ NDS32_BUILTIN(sunpkd820, "v_sunpkd820", V_SUNPKD820) ++ NDS32_BUILTIN(sunpkd830, "sunpkd830", SUNPKD830) ++ NDS32_BUILTIN(sunpkd830, "v_sunpkd830", V_SUNPKD830) ++ NDS32_BUILTIN(sunpkd831, "sunpkd831", SUNPKD831) ++ NDS32_BUILTIN(sunpkd831, "v_sunpkd831", V_SUNPKD831) ++ NDS32_BUILTIN(zunpkd810, "zunpkd810", ZUNPKD810) ++ NDS32_BUILTIN(zunpkd810, "v_zunpkd810", V_ZUNPKD810) ++ NDS32_BUILTIN(zunpkd820, "zunpkd820", ZUNPKD820) ++ NDS32_BUILTIN(zunpkd820, "v_zunpkd820", V_ZUNPKD820) ++ NDS32_BUILTIN(zunpkd830, "zunpkd830", ZUNPKD830) ++ NDS32_BUILTIN(zunpkd830, "v_zunpkd830", V_ZUNPKD830) ++ NDS32_BUILTIN(zunpkd831, "zunpkd831", ZUNPKD831) ++ NDS32_BUILTIN(zunpkd831, "v_zunpkd831", V_ZUNPKD831) ++ NDS32_BUILTIN(unspec_kabs, "kabs", KABS) ++ NDS32_BUILTIN(unaligned_loadv2hi, "get_unaligned_u16x2", UALOAD_U16) ++ NDS32_BUILTIN(unaligned_loadv2hi, "get_unaligned_s16x2", UALOAD_S16) ++ NDS32_BUILTIN(unaligned_loadv4qi, "get_unaligned_u8x4", UALOAD_U8) ++ NDS32_BUILTIN(unaligned_loadv4qi, "get_unaligned_s8x4", UALOAD_S8) + }; + + /* Intrinsics that take just one argument. and the argument is immediate. */ +@@ -593,6 +619,28 @@ + NDS32_BUILTIN(unspec_ffb, "ffb", FFB) + NDS32_BUILTIN(unspec_ffmism, "ffmsim", FFMISM) + NDS32_BUILTIN(unspec_flmism, "flmism", FLMISM) ++ NDS32_BUILTIN(unspec_kaddw, "kaddw", KADDW) ++ NDS32_BUILTIN(unspec_kaddh, "kaddh", KADDH) ++ NDS32_BUILTIN(unspec_ksubw, "ksubw", KSUBW) ++ NDS32_BUILTIN(unspec_ksubh, "ksubh", KSUBH) ++ NDS32_BUILTIN(unspec_kdmbb, "kdmbb", KDMBB) ++ NDS32_BUILTIN(unspec_kdmbb, "v_kdmbb", V_KDMBB) ++ NDS32_BUILTIN(unspec_kdmbt, "kdmbt", KDMBT) ++ NDS32_BUILTIN(unspec_kdmbt, "v_kdmbt", V_KDMBT) ++ NDS32_BUILTIN(unspec_kdmtb, "kdmtb", KDMTB) ++ NDS32_BUILTIN(unspec_kdmtb, "v_kdmtb", V_KDMTB) ++ NDS32_BUILTIN(unspec_kdmtt, "kdmtt", KDMTT) ++ NDS32_BUILTIN(unspec_kdmtt, "v_kdmtt", V_KDMTT) ++ NDS32_BUILTIN(unspec_khmbb, "khmbb", KHMBB) ++ NDS32_BUILTIN(unspec_khmbb, "v_khmbb", V_KHMBB) ++ NDS32_BUILTIN(unspec_khmbt, "khmbt", KHMBT) ++ NDS32_BUILTIN(unspec_khmbt, "v_khmbt", V_KHMBT) ++ NDS32_BUILTIN(unspec_khmtb, "khmtb", KHMTB) ++ NDS32_BUILTIN(unspec_khmtb, "v_khmtb", V_KHMTB) ++ NDS32_BUILTIN(unspec_khmtt, "khmtt", KHMTT) ++ NDS32_BUILTIN(unspec_khmtt, "v_khmtt", V_KHMTT) ++ NDS32_BUILTIN(unspec_kslraw, "kslraw", KSLRAW) ++ NDS32_BUILTIN(unspec_kslrawu, "kslraw_u", KSLRAW_U) + NDS32_BUILTIN(rotrsi3, "rotr", ROTR) + NDS32_BUILTIN(unspec_sva, "sva", SVA) + NDS32_BUILTIN(unspec_svs, "svs", SVS) +@@ -603,7 +651,202 @@ + NDS32_NO_TARGET_BUILTIN(unaligned_store_hw, "unaligned_store_hw", UASTORE_HW) + NDS32_NO_TARGET_BUILTIN(unaligned_storesi, "unaligned_store_hw", UASTORE_W) + NDS32_NO_TARGET_BUILTIN(unaligned_storedi, "unaligned_store_hw", UASTORE_DW) +- ++ NDS32_BUILTIN(addv2hi3, "add16", ADD16) ++ NDS32_BUILTIN(addv2hi3, "v_uadd16", V_UADD16) ++ NDS32_BUILTIN(addv2hi3, "v_sadd16", V_SADD16) ++ NDS32_BUILTIN(raddv2hi3, "radd16", RADD16) ++ NDS32_BUILTIN(raddv2hi3, "v_radd16", V_RADD16) ++ NDS32_BUILTIN(uraddv2hi3, "uradd16", URADD16) ++ NDS32_BUILTIN(uraddv2hi3, "v_uradd16", V_URADD16) ++ NDS32_BUILTIN(kaddv2hi3, "kadd16", KADD16) ++ NDS32_BUILTIN(kaddv2hi3, "v_kadd16", V_KADD16) ++ NDS32_BUILTIN(ukaddv2hi3, "ukadd16", UKADD16) ++ NDS32_BUILTIN(ukaddv2hi3, "v_ukadd16", V_UKADD16) ++ NDS32_BUILTIN(subv2hi3, "sub16", SUB16) ++ NDS32_BUILTIN(subv2hi3, "v_usub16", V_USUB16) ++ NDS32_BUILTIN(subv2hi3, "v_ssub16", V_SSUB16) ++ NDS32_BUILTIN(rsubv2hi3, "rsub16", RSUB16) ++ NDS32_BUILTIN(rsubv2hi3, "v_rsub16", V_RSUB16) ++ NDS32_BUILTIN(ursubv2hi3, "ursub16", URSUB16) ++ NDS32_BUILTIN(ursubv2hi3, "v_ursub16", V_URSUB16) ++ NDS32_BUILTIN(ksubv2hi3, "ksub16", KSUB16) ++ NDS32_BUILTIN(ksubv2hi3, "v_ksub16", V_KSUB16) ++ NDS32_BUILTIN(uksubv2hi3, "uksub16", UKSUB16) ++ NDS32_BUILTIN(uksubv2hi3, "v_uksub16", V_UKSUB16) ++ NDS32_BUILTIN(cras16_1, "cras16", CRAS16) ++ NDS32_BUILTIN(cras16_1, "v_ucras16", V_UCRAS16) ++ NDS32_BUILTIN(cras16_1, "v_scras16", V_SCRAS16) ++ NDS32_BUILTIN(rcras16_1, "rcras16", RCRAS16) ++ NDS32_BUILTIN(rcras16_1, "v_rcras16", V_RCRAS16) ++ NDS32_BUILTIN(urcras16_1, "urcras16", URCRAS16) ++ NDS32_BUILTIN(urcras16_1, "v_urcras16", V_URCRAS16) ++ NDS32_BUILTIN(kcras16_1, "kcras16", KCRAS16) ++ NDS32_BUILTIN(kcras16_1, "v_kcras16", V_KCRAS16) ++ NDS32_BUILTIN(ukcras16_1, "ukcras16", UKCRAS16) ++ NDS32_BUILTIN(ukcras16_1, "v_ukcras16", V_UKCRAS16) ++ NDS32_BUILTIN(crsa16_1, "crsa16", CRSA16) ++ NDS32_BUILTIN(crsa16_1, "v_ucrsa16", V_UCRSA16) ++ NDS32_BUILTIN(crsa16_1, "v_scrsa16", V_SCRSA16) ++ NDS32_BUILTIN(rcrsa16_1, "rcrsa16", RCRSA16) ++ NDS32_BUILTIN(rcrsa16_1, "v_rcrsa16", V_RCRSA16) ++ NDS32_BUILTIN(urcrsa16_1, "urcrsa16", URCRSA16) ++ NDS32_BUILTIN(urcrsa16_1, "v_urcrsa16", V_URCRSA16) ++ NDS32_BUILTIN(kcrsa16_1, "kcrsa16", KCRSA16) ++ NDS32_BUILTIN(kcrsa16_1, "v_kcrsa16", V_KCRSA16) ++ NDS32_BUILTIN(ukcrsa16_1, "ukcrsa16", UKCRSA16) ++ NDS32_BUILTIN(ukcrsa16_1, "v_ukcrsa16", V_UKCRSA16) ++ NDS32_BUILTIN(addv4qi3, "add8", ADD8) ++ NDS32_BUILTIN(addv4qi3, "v_uadd8", V_UADD8) ++ NDS32_BUILTIN(addv4qi3, "v_sadd8", V_SADD8) ++ NDS32_BUILTIN(raddv4qi3, "radd8", RADD8) ++ NDS32_BUILTIN(raddv4qi3, "v_radd8", V_RADD8) ++ NDS32_BUILTIN(uraddv4qi3, "uradd8", URADD8) ++ NDS32_BUILTIN(uraddv4qi3, "v_uradd8", V_URADD8) ++ NDS32_BUILTIN(kaddv4qi3, "kadd8", KADD8) ++ NDS32_BUILTIN(kaddv4qi3, "v_kadd8", V_KADD8) ++ NDS32_BUILTIN(ukaddv4qi3, "ukadd8", UKADD8) ++ NDS32_BUILTIN(ukaddv4qi3, "v_ukadd8", V_UKADD8) ++ NDS32_BUILTIN(subv4qi3, "sub8", SUB8) ++ NDS32_BUILTIN(subv4qi3, "v_usub8", V_USUB8) ++ NDS32_BUILTIN(subv4qi3, "v_ssub8", V_SSUB8) ++ NDS32_BUILTIN(rsubv4qi3, "rsub8", RSUB8) ++ NDS32_BUILTIN(rsubv4qi3, "v_rsub8", V_RSUB8) ++ NDS32_BUILTIN(ursubv4qi3, "ursub8", URSUB8) ++ NDS32_BUILTIN(ursubv4qi3, "v_ursub8", V_URSUB8) ++ NDS32_BUILTIN(ksubv4qi3, "ksub8", KSUB8) ++ NDS32_BUILTIN(ksubv4qi3, "v_ksub8", V_KSUB8) ++ NDS32_BUILTIN(uksubv4qi3, "uksub8", UKSUB8) ++ NDS32_BUILTIN(uksubv4qi3, "v_uksub8", V_UKSUB8) ++ NDS32_BUILTIN(ashrv2hi3, "sra16", SRA16) ++ NDS32_BUILTIN(ashrv2hi3, "v_sra16", V_SRA16) ++ NDS32_BUILTIN(sra16_round, "sra16_u", SRA16_U) ++ NDS32_BUILTIN(sra16_round, "v_sra16_u", V_SRA16_U) ++ NDS32_BUILTIN(lshrv2hi3, "srl16", SRL16) ++ NDS32_BUILTIN(lshrv2hi3, "v_srl16", V_SRL16) ++ NDS32_BUILTIN(srl16_round, "srl16_u", SRL16_U) ++ NDS32_BUILTIN(srl16_round, "v_srl16_u", V_SRL16_U) ++ NDS32_BUILTIN(ashlv2hi3, "sll16", SLL16) ++ NDS32_BUILTIN(ashlv2hi3, "v_sll16", V_SLL16) ++ NDS32_BUILTIN(kslli16, "ksll16", KSLL16) ++ NDS32_BUILTIN(kslli16, "v_ksll16", V_KSLL16) ++ NDS32_BUILTIN(kslra16, "kslra16", KSLRA16) ++ NDS32_BUILTIN(kslra16, "v_kslra16", V_KSLRA16) ++ NDS32_BUILTIN(kslra16_round, "kslra16_u", KSLRA16_U) ++ NDS32_BUILTIN(kslra16_round, "v_kslra16_u", V_KSLRA16_U) ++ NDS32_BUILTIN(cmpeq16, "cmpeq16", CMPEQ16) ++ NDS32_BUILTIN(cmpeq16, "v_scmpeq16", V_SCMPEQ16) ++ NDS32_BUILTIN(cmpeq16, "v_ucmpeq16", V_UCMPEQ16) ++ NDS32_BUILTIN(scmplt16, "scmplt16", SCMPLT16) ++ NDS32_BUILTIN(scmplt16, "v_scmplt16", V_SCMPLT16) ++ NDS32_BUILTIN(scmple16, "scmple16", SCMPLE16) ++ NDS32_BUILTIN(scmple16, "v_scmple16", V_SCMPLE16) ++ NDS32_BUILTIN(ucmplt16, "ucmplt16", UCMPLT16) ++ NDS32_BUILTIN(ucmplt16, "v_ucmplt16", V_UCMPLT16) ++ NDS32_BUILTIN(ucmplt16, "ucmple16", UCMPLE16) ++ NDS32_BUILTIN(ucmplt16, "v_ucmple16", V_UCMPLE16) ++ NDS32_BUILTIN(cmpeq8, "cmpeq8", CMPEQ8) ++ NDS32_BUILTIN(cmpeq8, "v_scmpeq8", V_SCMPEQ8) ++ NDS32_BUILTIN(cmpeq8, "v_ucmpeq8", V_UCMPEQ8) ++ NDS32_BUILTIN(scmplt8, "scmplt8", SCMPLT8) ++ NDS32_BUILTIN(scmplt8, "v_scmplt8", V_SCMPLT8) ++ NDS32_BUILTIN(scmple8, "scmple8", SCMPLE8) ++ NDS32_BUILTIN(scmple8, "v_scmple8", V_SCMPLE8) ++ NDS32_BUILTIN(ucmplt8, "ucmplt8", UCMPLT8) ++ NDS32_BUILTIN(ucmplt8, "v_ucmplt8", V_UCMPLT8) ++ NDS32_BUILTIN(ucmplt8, "ucmple8", UCMPLE8) ++ NDS32_BUILTIN(ucmplt8, "v_ucmple8", V_UCMPLE8) ++ NDS32_BUILTIN(sminv2hi3, "smin16", SMIN16) ++ NDS32_BUILTIN(sminv2hi3, "v_smin16", V_SMIN16) ++ NDS32_BUILTIN(uminv2hi3, "umin16", UMIN16) ++ NDS32_BUILTIN(uminv2hi3, "v_umin16", V_UMIN16) ++ NDS32_BUILTIN(smaxv2hi3, "smax16", SMAX16) ++ NDS32_BUILTIN(smaxv2hi3, "v_smax16", V_SMAX16) ++ NDS32_BUILTIN(umaxv2hi3, "umax16", UMAX16) ++ NDS32_BUILTIN(umaxv2hi3, "v_umax16", V_UMAX16) ++ NDS32_BUILTIN(khm16, "khm16", KHM16) ++ NDS32_BUILTIN(khm16, "v_khm16", V_KHM16) ++ NDS32_BUILTIN(khmx16, "khmx16", KHMX16) ++ NDS32_BUILTIN(khmx16, "v_khmx16", V_KHMX16) ++ NDS32_BUILTIN(sminv4qi3, "smin8", SMIN8) ++ NDS32_BUILTIN(sminv4qi3, "v_smin8", V_SMIN8) ++ NDS32_BUILTIN(uminv4qi3, "umin8", UMIN8) ++ NDS32_BUILTIN(uminv4qi3, "v_umin8", V_UMIN8) ++ NDS32_BUILTIN(smaxv4qi3, "smax8", SMAX8) ++ NDS32_BUILTIN(smaxv4qi3, "v_smax8", V_SMAX8) ++ NDS32_BUILTIN(umaxv4qi3, "umax8", UMAX8) ++ NDS32_BUILTIN(umaxv4qi3, "v_umax8", V_UMAX8) ++ NDS32_BUILTIN(raddsi3, "raddw", RADDW) ++ NDS32_BUILTIN(uraddsi3, "uraddw", URADDW) ++ NDS32_BUILTIN(rsubsi3, "rsubw", RSUBW) ++ NDS32_BUILTIN(ursubsi3, "ursubw", URSUBW) ++ NDS32_BUILTIN(sraiu, "sra_u", SRA_U) ++ NDS32_BUILTIN(kssl, "ksll", KSLL) ++ NDS32_BUILTIN(pkbb, "pkbb16", PKBB16) ++ NDS32_BUILTIN(pkbb, "v_pkbb16", V_PKBB16) ++ NDS32_BUILTIN(pkbt, "pkbt16", PKBT16) ++ NDS32_BUILTIN(pkbt, "v_pkbt16", V_PKBT16) ++ NDS32_BUILTIN(pktb, "pktb16", PKTB16) ++ NDS32_BUILTIN(pktb, "v_pktb16", V_PKTB16) ++ NDS32_BUILTIN(pktt, "pktt16", PKTT16) ++ NDS32_BUILTIN(pktt, "v_pktt16", V_PKTT16) ++ NDS32_BUILTIN(smulsi3_highpart, "smmul", SMMUL) ++ NDS32_BUILTIN(smmul_round, "smmul_u", SMMUL_U) ++ NDS32_BUILTIN(smmwb, "smmwb", SMMWB) ++ NDS32_BUILTIN(smmwb, "v_smmwb", V_SMMWB) ++ NDS32_BUILTIN(smmwb_round, "smmwb_u", SMMWB_U) ++ NDS32_BUILTIN(smmwb_round, "v_smmwb_u", V_SMMWB_U) ++ NDS32_BUILTIN(smmwt, "smmwt", SMMWT) ++ NDS32_BUILTIN(smmwt, "v_smmwt", V_SMMWT) ++ NDS32_BUILTIN(smmwt_round, "smmwt_u", SMMWT_U) ++ NDS32_BUILTIN(smmwt_round, "v_smmwt_u", V_SMMWT_U) ++ NDS32_BUILTIN(smbb, "smbb", SMBB) ++ NDS32_BUILTIN(smbb, "v_smbb", V_SMBB) ++ NDS32_BUILTIN(smbt, "smbt", SMBT) ++ NDS32_BUILTIN(smbt, "v_smbt", V_SMBT) ++ NDS32_BUILTIN(smtt, "smtt", SMTT) ++ NDS32_BUILTIN(smtt, "v_smtt", V_SMTT) ++ NDS32_BUILTIN(kmda, "kmda", KMDA) ++ NDS32_BUILTIN(kmda, "v_kmda", V_KMDA) ++ NDS32_BUILTIN(kmxda, "kmxda", KMXDA) ++ NDS32_BUILTIN(kmxda, "v_kmxda", V_KMXDA) ++ NDS32_BUILTIN(smds, "smds", SMDS) ++ NDS32_BUILTIN(smds, "v_smds", V_SMDS) ++ NDS32_BUILTIN(smdrs, "smdrs", SMDRS) ++ NDS32_BUILTIN(smdrs, "v_smdrs", V_SMDRS) ++ NDS32_BUILTIN(smxdsv, "smxds", SMXDS) ++ NDS32_BUILTIN(smxdsv, "v_smxds", V_SMXDS) ++ NDS32_BUILTIN(smal1, "smal", SMAL) ++ NDS32_BUILTIN(smal1, "v_smal", V_SMAL) ++ NDS32_BUILTIN(bitrev, "bitrev", BITREV) ++ NDS32_BUILTIN(wext, "wext", WEXT) ++ NDS32_BUILTIN(adddi3, "sadd64", SADD64) ++ NDS32_BUILTIN(adddi3, "uadd64", UADD64) ++ NDS32_BUILTIN(radddi3, "radd64", RADD64) ++ NDS32_BUILTIN(uradddi3, "uradd64", URADD64) ++ NDS32_BUILTIN(kadddi3, "kadd64", KADD64) ++ NDS32_BUILTIN(ukadddi3, "ukadd64", UKADD64) ++ NDS32_BUILTIN(subdi3, "ssub64", SSUB64) ++ NDS32_BUILTIN(subdi3, "usub64", USUB64) ++ NDS32_BUILTIN(rsubdi3, "rsub64", RSUB64) ++ NDS32_BUILTIN(ursubdi3, "ursub64", URSUB64) ++ NDS32_BUILTIN(ksubdi3, "ksub64", KSUB64) ++ NDS32_BUILTIN(uksubdi3, "uksub64", UKSUB64) ++ NDS32_BUILTIN(smul16, "smul16", SMUL16) ++ NDS32_BUILTIN(smul16, "v_smul16", V_SMUL16) ++ NDS32_BUILTIN(smulx16, "smulx16", SMULX16) ++ NDS32_BUILTIN(smulx16, "v_smulx16", V_SMULX16) ++ NDS32_BUILTIN(umul16, "umul16", UMUL16) ++ NDS32_BUILTIN(umul16, "v_umul16", V_UMUL16) ++ NDS32_BUILTIN(umulx16, "umulx16", UMULX16) ++ NDS32_BUILTIN(umulx16, "v_umulx16", V_UMULX16) ++ NDS32_BUILTIN(kwmmul, "kwmmul", KWMMUL) ++ NDS32_BUILTIN(kwmmul_round, "kwmmul_u", KWMMUL_U) ++ NDS32_NO_TARGET_BUILTIN(unaligned_storev2hi, ++ "put_unaligned_u16x2", UASTORE_U16) ++ NDS32_NO_TARGET_BUILTIN(unaligned_storev2hi, ++ "put_unaligned_s16x2", UASTORE_S16) ++ NDS32_NO_TARGET_BUILTIN(unaligned_storev4qi, "put_unaligned_u8x4", UASTORE_U8) ++ NDS32_NO_TARGET_BUILTIN(unaligned_storev4qi, "put_unaligned_s8x4", UASTORE_S8) + }; + + /* Two-argument intrinsics with an immediate second argument. */ +@@ -617,6 +860,22 @@ + NDS32_BUILTIN(unspec_clips, "clips", CLIPS) + NDS32_NO_TARGET_BUILTIN(unspec_teqz, "teqz", TEQZ) + NDS32_NO_TARGET_BUILTIN(unspec_tnez, "tnez", TNEZ) ++ NDS32_BUILTIN(ashrv2hi3, "srl16", SRL16) ++ NDS32_BUILTIN(ashrv2hi3, "v_srl16", V_SRL16) ++ NDS32_BUILTIN(srl16_round, "srl16_u", SRL16_U) ++ NDS32_BUILTIN(srl16_round, "v_srl16_u", V_SRL16_U) ++ NDS32_BUILTIN(kslli16, "ksll16", KSLL16) ++ NDS32_BUILTIN(kslli16, "v_ksll16", V_KSLL16) ++ NDS32_BUILTIN(sclip16, "sclip16", SCLIP16) ++ NDS32_BUILTIN(sclip16, "v_sclip16", V_SCLIP16) ++ NDS32_BUILTIN(uclip16, "uclip16", UCLIP16) ++ NDS32_BUILTIN(uclip16, "v_uclip16", V_UCLIP16) ++ NDS32_BUILTIN(sraiu, "sra_u", SRA_U) ++ NDS32_BUILTIN(kssl, "ksll", KSLL) ++ NDS32_BUILTIN(bitrev, "bitrev", BITREV) ++ NDS32_BUILTIN(wext, "wext", WEXT) ++ NDS32_BUILTIN(uclip32, "uclip32", UCLIP32) ++ NDS32_BUILTIN(sclip32, "sclip32", SCLIP32) + }; + + /* Intrinsics that take three arguments. */ +@@ -625,6 +884,67 @@ + NDS32_BUILTIN(unspec_pbsada, "pbsada", PBSADA) + NDS32_NO_TARGET_BUILTIN(bse, "bse", BSE) + NDS32_NO_TARGET_BUILTIN(bsp, "bsp", BSP) ++ NDS32_BUILTIN(kmabb, "kmabb", KMABB) ++ NDS32_BUILTIN(kmabb, "v_kmabb", V_KMABB) ++ NDS32_BUILTIN(kmabt, "kmabt", KMABT) ++ NDS32_BUILTIN(kmabt, "v_kmabt", V_KMABT) ++ NDS32_BUILTIN(kmatt, "kmatt", KMATT) ++ NDS32_BUILTIN(kmatt, "v_kmatt", V_KMATT) ++ NDS32_BUILTIN(kmada, "kmada", KMADA) ++ NDS32_BUILTIN(kmada, "v_kmada", V_KMADA) ++ NDS32_BUILTIN(kmaxda, "kmaxda", KMAXDA) ++ NDS32_BUILTIN(kmaxda, "v_kmaxda", V_KMAXDA) ++ NDS32_BUILTIN(kmads, "kmads", KMADS) ++ NDS32_BUILTIN(kmads, "v_kmads", V_KMADS) ++ NDS32_BUILTIN(kmadrs, "kmadrs", KMADRS) ++ NDS32_BUILTIN(kmadrs, "v_kmadrs", V_KMADRS) ++ NDS32_BUILTIN(kmaxds, "kmaxds", KMAXDS) ++ NDS32_BUILTIN(kmaxds, "v_kmaxds", V_KMAXDS) ++ NDS32_BUILTIN(kmsda, "kmsda", KMSDA) ++ NDS32_BUILTIN(kmsda, "v_kmsda", V_KMSDA) ++ NDS32_BUILTIN(kmsxda, "kmsxda", KMSXDA) ++ NDS32_BUILTIN(kmsxda, "v_kmsxda", V_KMSXDA) ++ NDS32_BUILTIN(bpick1, "bpick", BPICK) ++ NDS32_BUILTIN(smar64_1, "smar64", SMAR64) ++ NDS32_BUILTIN(smsr64, "smsr64", SMSR64) ++ NDS32_BUILTIN(umar64_1, "umar64", UMAR64) ++ NDS32_BUILTIN(umsr64, "umsr64", UMSR64) ++ NDS32_BUILTIN(kmar64_1, "kmar64", KMAR64) ++ NDS32_BUILTIN(kmsr64, "kmsr64", KMSR64) ++ NDS32_BUILTIN(ukmar64_1, "ukmar64", UKMAR64) ++ NDS32_BUILTIN(ukmsr64, "ukmsr64", UKMSR64) ++ NDS32_BUILTIN(smalbb, "smalbb", SMALBB) ++ NDS32_BUILTIN(smalbb, "v_smalbb", V_SMALBB) ++ NDS32_BUILTIN(smalbt, "smalbt", SMALBT) ++ NDS32_BUILTIN(smalbt, "v_smalbt", V_SMALBT) ++ NDS32_BUILTIN(smaltt, "smaltt", SMALTT) ++ NDS32_BUILTIN(smaltt, "v_smaltt", V_SMALTT) ++ NDS32_BUILTIN(smalda1, "smalda", SMALDA) ++ NDS32_BUILTIN(smalda1, "v_smalda", V_SMALDA) ++ NDS32_BUILTIN(smalxda1, "smalxda", SMALXDA) ++ NDS32_BUILTIN(smalxda1, "v_smalxda", V_SMALXDA) ++ NDS32_BUILTIN(smalds1, "smalds", SMALDS) ++ NDS32_BUILTIN(smalds1, "v_smalds", V_SMALDS) ++ NDS32_BUILTIN(smaldrs3, "smaldrs", SMALDRS) ++ NDS32_BUILTIN(smaldrs3, "v_smaldrs", V_SMALDRS) ++ NDS32_BUILTIN(smalxds1, "smalxds", SMALXDS) ++ NDS32_BUILTIN(smalxds1, "v_smalxds", V_SMALXDS) ++ NDS32_BUILTIN(smslda1, "smslda", SMSLDA) ++ NDS32_BUILTIN(smslda1, "v_smslda", V_SMSLDA) ++ NDS32_BUILTIN(smslxda1, "smslxda", SMSLXDA) ++ NDS32_BUILTIN(smslxda1, "v_smslxda", V_SMSLXDA) ++ NDS32_BUILTIN(kmmawb, "kmmawb", KMMAWB) ++ NDS32_BUILTIN(kmmawb, "v_kmmawb", V_KMMAWB) ++ NDS32_BUILTIN(kmmawb_round, "kmmawb_u", KMMAWB_U) ++ NDS32_BUILTIN(kmmawb_round, "v_kmmawb_u", V_KMMAWB_U) ++ NDS32_BUILTIN(kmmawt, "kmmawt", KMMAWT) ++ NDS32_BUILTIN(kmmawt, "v_kmmawt", V_KMMAWT) ++ NDS32_BUILTIN(kmmawt_round, "kmmawt_u", KMMAWT_U) ++ NDS32_BUILTIN(kmmawt_round, "v_kmmawt_u", V_KMMAWT_U) ++ NDS32_BUILTIN(kmmac, "kmmac", KMMAC) ++ NDS32_BUILTIN(kmmac_round, "kmmac_u", KMMAC_U) ++ NDS32_BUILTIN(kmmsb, "kmmsb", KMMSB) ++ NDS32_BUILTIN(kmmsb_round, "kmmsb_u", KMMSB_U) + }; + + /* Three-argument intrinsics with an immediate third argument. */ +@@ -634,6 +954,7 @@ + NDS32_NO_TARGET_BUILTIN(prefetch_hw, "prefetch_hw", DPREF_HW) + NDS32_NO_TARGET_BUILTIN(prefetch_w, "prefetch_w", DPREF_W) + NDS32_NO_TARGET_BUILTIN(prefetch_dw, "prefetch_dw", DPREF_DW) ++ NDS32_BUILTIN(insb, "insb", INSB) + }; + + /* Intrinsics that load a value. */ +@@ -676,6 +997,11 @@ + unsigned i; + struct builtin_description *d; + ++ if (!NDS32_EXT_DSP_P () ++ && fcode > NDS32_BUILTIN_DSP_BEGIN ++ && fcode < NDS32_BUILTIN_DSP_END) ++ error ("don't support DSP extension instructions"); ++ + switch (fcode) + { + /* FPU Register Transfer. */ +@@ -812,6 +1138,9 @@ + case NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL: + emit_insn (gen_cctl_l1d_wball_one_lvl()); + return target; ++ case NDS32_BUILTIN_CLROV: ++ emit_insn (gen_unspec_volatile_clrov ()); ++ return target; + case NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT: + emit_insn (gen_unspec_standby_no_wake_grant ()); + return target; +@@ -947,10 +1276,18 @@ + NDS32_BUILTIN_ ## CODE, BUILT_IN_MD, NULL, NULL_TREE) + + /* Looking for return type and argument can be found in tree.h file. */ ++ tree ptr_char_type_node = build_pointer_type (char_type_node); + tree ptr_uchar_type_node = build_pointer_type (unsigned_char_type_node); + tree ptr_ushort_type_node = build_pointer_type (short_unsigned_type_node); ++ tree ptr_short_type_node = build_pointer_type (short_integer_type_node); + tree ptr_uint_type_node = build_pointer_type (unsigned_type_node); + tree ptr_ulong_type_node = build_pointer_type (long_long_unsigned_type_node); ++ tree v4qi_type_node = build_vector_type (intQI_type_node, 4); ++ tree u_v4qi_type_node = build_vector_type (unsigned_intQI_type_node, 4); ++ tree v2hi_type_node = build_vector_type (intHI_type_node, 2); ++ tree u_v2hi_type_node = build_vector_type (unsigned_intHI_type_node, 2); ++ tree v2si_type_node = build_vector_type (intSI_type_node, 2); ++ tree u_v2si_type_node = build_vector_type (unsigned_intSI_type_node, 2); + + /* Cache. */ + ADD_NDS32_BUILTIN1 ("isync", void, ptr_uint, ISYNC); +@@ -1050,6 +1387,31 @@ + ADD_NDS32_BUILTIN2 ("se_ffmism", integer, unsigned, unsigned, FFMISM); + ADD_NDS32_BUILTIN2 ("se_flmism", integer, unsigned, unsigned, FLMISM); + ++ /* SATURATION */ ++ ADD_NDS32_BUILTIN2 ("kaddw", integer, integer, integer, KADDW); ++ ADD_NDS32_BUILTIN2 ("ksubw", integer, integer, integer, KSUBW); ++ ADD_NDS32_BUILTIN2 ("kaddh", integer, integer, integer, KADDH); ++ ADD_NDS32_BUILTIN2 ("ksubh", integer, integer, integer, KSUBH); ++ ADD_NDS32_BUILTIN2 ("kdmbb", integer, unsigned, unsigned, KDMBB); ++ ADD_NDS32_BUILTIN2 ("v_kdmbb", integer, v2hi, v2hi, V_KDMBB); ++ ADD_NDS32_BUILTIN2 ("kdmbt", integer, unsigned, unsigned, KDMBT); ++ ADD_NDS32_BUILTIN2 ("v_kdmbt", integer, v2hi, v2hi, V_KDMBT); ++ ADD_NDS32_BUILTIN2 ("kdmtb", integer, unsigned, unsigned, KDMTB); ++ ADD_NDS32_BUILTIN2 ("v_kdmtb", integer, v2hi, v2hi, V_KDMTB); ++ ADD_NDS32_BUILTIN2 ("kdmtt", integer, unsigned, unsigned, KDMTT); ++ ADD_NDS32_BUILTIN2 ("v_kdmtt", integer, v2hi, v2hi, V_KDMTT); ++ ADD_NDS32_BUILTIN2 ("khmbb", integer, unsigned, unsigned, KHMBB); ++ ADD_NDS32_BUILTIN2 ("v_khmbb", integer, v2hi, v2hi, V_KHMBB); ++ ADD_NDS32_BUILTIN2 ("khmbt", integer, unsigned, unsigned, KHMBT); ++ ADD_NDS32_BUILTIN2 ("v_khmbt", integer, v2hi, v2hi, V_KHMBT); ++ ADD_NDS32_BUILTIN2 ("khmtb", integer, unsigned, unsigned, KHMTB); ++ ADD_NDS32_BUILTIN2 ("v_khmtb", integer, v2hi, v2hi, V_KHMTB); ++ ADD_NDS32_BUILTIN2 ("khmtt", integer, unsigned, unsigned, KHMTT); ++ ADD_NDS32_BUILTIN2 ("v_khmtt", integer, v2hi, v2hi, V_KHMTT); ++ ADD_NDS32_BUILTIN2 ("kslraw", integer, integer, integer, KSLRAW); ++ ADD_NDS32_BUILTIN2 ("kslraw_u", integer, integer, integer, KSLRAW_U); ++ ADD_NDS32_BUILTIN0 ("rdov", unsigned, RDOV); ++ ADD_NDS32_BUILTIN0 ("clrov", void, CLROV); + + /* ROTR */ + ADD_NDS32_BUILTIN2 ("rotr", unsigned, unsigned, unsigned, ROTR); +@@ -1109,4 +1471,384 @@ + ADD_NDS32_BUILTIN0 ("enable_unaligned", void, ENABLE_UNALIGNED); + ADD_NDS32_BUILTIN0 ("disable_unaligned", void, DISABLE_UNALIGNED); + ++ /* DSP Extension: SIMD 16bit Add and Subtract. */ ++ ADD_NDS32_BUILTIN2 ("add16", unsigned, unsigned, unsigned, ADD16); ++ ADD_NDS32_BUILTIN2 ("v_uadd16", u_v2hi, u_v2hi, u_v2hi, V_UADD16); ++ ADD_NDS32_BUILTIN2 ("v_sadd16", v2hi, v2hi, v2hi, V_SADD16); ++ ADD_NDS32_BUILTIN2 ("radd16", unsigned, unsigned, unsigned, RADD16); ++ ADD_NDS32_BUILTIN2 ("v_radd16", v2hi, v2hi, v2hi, V_RADD16); ++ ADD_NDS32_BUILTIN2 ("uradd16", unsigned, unsigned, unsigned, URADD16); ++ ADD_NDS32_BUILTIN2 ("v_uradd16", u_v2hi, u_v2hi, u_v2hi, V_URADD16); ++ ADD_NDS32_BUILTIN2 ("kadd16", unsigned, unsigned, unsigned, KADD16); ++ ADD_NDS32_BUILTIN2 ("v_kadd16", v2hi, v2hi, v2hi, V_KADD16); ++ ADD_NDS32_BUILTIN2 ("ukadd16", unsigned, unsigned, unsigned, UKADD16); ++ ADD_NDS32_BUILTIN2 ("v_ukadd16", u_v2hi, u_v2hi, u_v2hi, V_UKADD16); ++ ADD_NDS32_BUILTIN2 ("sub16", unsigned, unsigned, unsigned, SUB16); ++ ADD_NDS32_BUILTIN2 ("v_usub16", u_v2hi, u_v2hi, u_v2hi, V_USUB16); ++ ADD_NDS32_BUILTIN2 ("v_ssub16", v2hi, v2hi, v2hi, V_SSUB16); ++ ADD_NDS32_BUILTIN2 ("rsub16", unsigned, unsigned, unsigned, RSUB16); ++ ADD_NDS32_BUILTIN2 ("v_rsub16", v2hi, v2hi, v2hi, V_RSUB16); ++ ADD_NDS32_BUILTIN2 ("ursub16", unsigned, unsigned, unsigned, URSUB16); ++ ADD_NDS32_BUILTIN2 ("v_ursub16", u_v2hi, u_v2hi, u_v2hi, V_URSUB16); ++ ADD_NDS32_BUILTIN2 ("ksub16", unsigned, unsigned, unsigned, KSUB16); ++ ADD_NDS32_BUILTIN2 ("v_ksub16", v2hi, v2hi, v2hi, V_KSUB16); ++ ADD_NDS32_BUILTIN2 ("uksub16", unsigned, unsigned, unsigned, UKSUB16); ++ ADD_NDS32_BUILTIN2 ("v_uksub16", u_v2hi, u_v2hi, u_v2hi, V_UKSUB16); ++ ADD_NDS32_BUILTIN2 ("cras16", unsigned, unsigned, unsigned, CRAS16); ++ ADD_NDS32_BUILTIN2 ("v_ucras16", u_v2hi, u_v2hi, u_v2hi, V_UCRAS16); ++ ADD_NDS32_BUILTIN2 ("v_scras16", v2hi, v2hi, v2hi, V_SCRAS16); ++ ADD_NDS32_BUILTIN2 ("rcras16", unsigned, unsigned, unsigned, RCRAS16); ++ ADD_NDS32_BUILTIN2 ("v_rcras16", v2hi, v2hi, v2hi, V_RCRAS16); ++ ADD_NDS32_BUILTIN2 ("urcras16", unsigned, unsigned, unsigned, URCRAS16); ++ ADD_NDS32_BUILTIN2 ("v_urcras16", u_v2hi, u_v2hi, u_v2hi, V_URCRAS16); ++ ADD_NDS32_BUILTIN2 ("kcras16", unsigned, unsigned, unsigned, KCRAS16); ++ ADD_NDS32_BUILTIN2 ("v_kcras16", v2hi, v2hi, v2hi, V_KCRAS16); ++ ADD_NDS32_BUILTIN2 ("ukcras16", unsigned, unsigned, unsigned, UKCRAS16); ++ ADD_NDS32_BUILTIN2 ("v_ukcras16", u_v2hi, u_v2hi, u_v2hi, V_UKCRAS16); ++ ADD_NDS32_BUILTIN2 ("crsa16", unsigned, unsigned, unsigned, CRSA16); ++ ADD_NDS32_BUILTIN2 ("v_ucrsa16", u_v2hi, u_v2hi, u_v2hi, V_UCRSA16); ++ ADD_NDS32_BUILTIN2 ("v_scrsa16", v2hi, v2hi, v2hi, V_SCRSA16); ++ ADD_NDS32_BUILTIN2 ("rcrsa16", unsigned, unsigned, unsigned, RCRSA16); ++ ADD_NDS32_BUILTIN2 ("v_rcrsa16", v2hi, v2hi, v2hi, V_RCRSA16); ++ ADD_NDS32_BUILTIN2 ("urcrsa16", unsigned, unsigned, unsigned, URCRSA16); ++ ADD_NDS32_BUILTIN2 ("v_urcrsa16", u_v2hi, u_v2hi, u_v2hi, V_URCRSA16); ++ ADD_NDS32_BUILTIN2 ("kcrsa16", unsigned, unsigned, unsigned, KCRSA16); ++ ADD_NDS32_BUILTIN2 ("v_kcrsa16", v2hi, v2hi, v2hi, V_KCRSA16); ++ ADD_NDS32_BUILTIN2 ("ukcrsa16", unsigned, unsigned, unsigned, UKCRSA16); ++ ADD_NDS32_BUILTIN2 ("v_ukcrsa16", u_v2hi, u_v2hi, u_v2hi, V_UKCRSA16); ++ ++ /* DSP Extension: SIMD 8bit Add and Subtract. */ ++ ADD_NDS32_BUILTIN2 ("add8", integer, integer, integer, ADD8); ++ ADD_NDS32_BUILTIN2 ("v_uadd8", u_v4qi, u_v4qi, u_v4qi, V_UADD8); ++ ADD_NDS32_BUILTIN2 ("v_sadd8", v4qi, v4qi, v4qi, V_SADD8); ++ ADD_NDS32_BUILTIN2 ("radd8", unsigned, unsigned, unsigned, RADD8); ++ ADD_NDS32_BUILTIN2 ("v_radd8", v4qi, v4qi, v4qi, V_RADD8); ++ ADD_NDS32_BUILTIN2 ("uradd8", unsigned, unsigned, unsigned, URADD8); ++ ADD_NDS32_BUILTIN2 ("v_uradd8", u_v4qi, u_v4qi, u_v4qi, V_URADD8); ++ ADD_NDS32_BUILTIN2 ("kadd8", unsigned, unsigned, unsigned, KADD8); ++ ADD_NDS32_BUILTIN2 ("v_kadd8", v4qi, v4qi, v4qi, V_KADD8); ++ ADD_NDS32_BUILTIN2 ("ukadd8", unsigned, unsigned, unsigned, UKADD8); ++ ADD_NDS32_BUILTIN2 ("v_ukadd8", u_v4qi, u_v4qi, u_v4qi, V_UKADD8); ++ ADD_NDS32_BUILTIN2 ("sub8", integer, integer, integer, SUB8); ++ ADD_NDS32_BUILTIN2 ("v_usub8", u_v4qi, u_v4qi, u_v4qi, V_USUB8); ++ ADD_NDS32_BUILTIN2 ("v_ssub8", v4qi, v4qi, v4qi, V_SSUB8); ++ ADD_NDS32_BUILTIN2 ("rsub8", unsigned, unsigned, unsigned, RSUB8); ++ ADD_NDS32_BUILTIN2 ("v_rsub8", v4qi, v4qi, v4qi, V_RSUB8); ++ ADD_NDS32_BUILTIN2 ("ursub8", unsigned, unsigned, unsigned, URSUB8); ++ ADD_NDS32_BUILTIN2 ("v_ursub8", u_v4qi, u_v4qi, u_v4qi, V_URSUB8); ++ ADD_NDS32_BUILTIN2 ("ksub8", unsigned, unsigned, unsigned, KSUB8); ++ ADD_NDS32_BUILTIN2 ("v_ksub8", v4qi, v4qi, v4qi, V_KSUB8); ++ ADD_NDS32_BUILTIN2 ("uksub8", unsigned, unsigned, unsigned, UKSUB8); ++ ADD_NDS32_BUILTIN2 ("v_uksub8", u_v4qi, u_v4qi, u_v4qi, V_UKSUB8); ++ ++ /* DSP Extension: SIMD 16bit Shift. */ ++ ADD_NDS32_BUILTIN2 ("sra16", unsigned, unsigned, unsigned, SRA16); ++ ADD_NDS32_BUILTIN2 ("v_sra16", v2hi, v2hi, unsigned, V_SRA16); ++ ADD_NDS32_BUILTIN2 ("sra16_u", unsigned, unsigned, unsigned, SRA16_U); ++ ADD_NDS32_BUILTIN2 ("v_sra16_u", v2hi, v2hi, unsigned, V_SRA16_U); ++ ADD_NDS32_BUILTIN2 ("srl16", unsigned, unsigned, unsigned, SRL16); ++ ADD_NDS32_BUILTIN2 ("v_srl16", u_v2hi, u_v2hi, unsigned, V_SRL16); ++ ADD_NDS32_BUILTIN2 ("srl16_u", unsigned, unsigned, unsigned, SRL16_U); ++ ADD_NDS32_BUILTIN2 ("v_srl16_u", u_v2hi, u_v2hi, unsigned, V_SRL16_U); ++ ADD_NDS32_BUILTIN2 ("sll16", unsigned, unsigned, unsigned, SLL16); ++ ADD_NDS32_BUILTIN2 ("v_sll16", u_v2hi, u_v2hi, unsigned, V_SLL16); ++ ADD_NDS32_BUILTIN2 ("ksll16", unsigned, unsigned, unsigned, KSLL16); ++ ADD_NDS32_BUILTIN2 ("v_ksll16", v2hi, v2hi, unsigned, V_KSLL16); ++ ADD_NDS32_BUILTIN2 ("kslra16", unsigned, unsigned, unsigned, KSLRA16); ++ ADD_NDS32_BUILTIN2 ("v_kslra16", v2hi, v2hi, unsigned, V_KSLRA16); ++ ADD_NDS32_BUILTIN2 ("kslra16_u", unsigned, unsigned, unsigned, KSLRA16_U); ++ ADD_NDS32_BUILTIN2 ("v_kslra16_u", v2hi, v2hi, unsigned, V_KSLRA16_U); ++ ++ /* DSP Extension: 16bit Compare. */ ++ ADD_NDS32_BUILTIN2 ("cmpeq16", unsigned, unsigned, unsigned, CMPEQ16); ++ ADD_NDS32_BUILTIN2 ("v_scmpeq16", u_v2hi, v2hi, v2hi, V_SCMPEQ16); ++ ADD_NDS32_BUILTIN2 ("v_ucmpeq16", u_v2hi, u_v2hi, u_v2hi, V_UCMPEQ16); ++ ADD_NDS32_BUILTIN2 ("scmplt16", unsigned, unsigned, unsigned, SCMPLT16); ++ ADD_NDS32_BUILTIN2 ("v_scmplt16", u_v2hi, v2hi, v2hi, V_SCMPLT16); ++ ADD_NDS32_BUILTIN2 ("scmple16", unsigned, unsigned, unsigned, SCMPLE16); ++ ADD_NDS32_BUILTIN2 ("v_scmple16", u_v2hi, v2hi, v2hi, V_SCMPLE16); ++ ADD_NDS32_BUILTIN2 ("ucmplt16", unsigned, unsigned, unsigned, UCMPLT16); ++ ADD_NDS32_BUILTIN2 ("v_ucmplt16", u_v2hi, u_v2hi, u_v2hi, V_UCMPLT16); ++ ADD_NDS32_BUILTIN2 ("ucmple16", unsigned, unsigned, unsigned, UCMPLE16); ++ ADD_NDS32_BUILTIN2 ("v_ucmple16", u_v2hi, u_v2hi, u_v2hi, V_UCMPLE16); ++ ++ /* DSP Extension: 8bit Compare. */ ++ ADD_NDS32_BUILTIN2 ("cmpeq8", unsigned, unsigned, unsigned, CMPEQ8); ++ ADD_NDS32_BUILTIN2 ("v_scmpeq8", u_v4qi, v4qi, v4qi, V_SCMPEQ8); ++ ADD_NDS32_BUILTIN2 ("v_ucmpeq8", u_v4qi, u_v4qi, u_v4qi, V_UCMPEQ8); ++ ADD_NDS32_BUILTIN2 ("scmplt8", unsigned, unsigned, unsigned, SCMPLT8); ++ ADD_NDS32_BUILTIN2 ("v_scmplt8", u_v4qi, v4qi, v4qi, V_SCMPLT8); ++ ADD_NDS32_BUILTIN2 ("scmple8", unsigned, unsigned, unsigned, SCMPLE8); ++ ADD_NDS32_BUILTIN2 ("v_scmple8", u_v4qi, v4qi, v4qi, V_SCMPLE8); ++ ADD_NDS32_BUILTIN2 ("ucmplt8", unsigned, unsigned, unsigned, UCMPLT8); ++ ADD_NDS32_BUILTIN2 ("v_ucmplt8", u_v4qi, u_v4qi, u_v4qi, V_UCMPLT8); ++ ADD_NDS32_BUILTIN2 ("ucmple8", unsigned, unsigned, unsigned, UCMPLE8); ++ ADD_NDS32_BUILTIN2 ("v_ucmple8", u_v4qi, u_v4qi, u_v4qi, V_UCMPLE8); ++ ++ /* DSP Extension: SIMD 16bit MISC. */ ++ ADD_NDS32_BUILTIN2 ("smin16", unsigned, unsigned, unsigned, SMIN16); ++ ADD_NDS32_BUILTIN2 ("v_smin16", v2hi, v2hi, v2hi, V_SMIN16); ++ ADD_NDS32_BUILTIN2 ("umin16", unsigned, unsigned, unsigned, UMIN16); ++ ADD_NDS32_BUILTIN2 ("v_umin16", u_v2hi, u_v2hi, u_v2hi, V_UMIN16); ++ ADD_NDS32_BUILTIN2 ("smax16", unsigned, unsigned, unsigned, SMAX16); ++ ADD_NDS32_BUILTIN2 ("v_smax16", v2hi, v2hi, v2hi, V_SMAX16); ++ ADD_NDS32_BUILTIN2 ("umax16", unsigned, unsigned, unsigned, UMAX16); ++ ADD_NDS32_BUILTIN2 ("v_umax16", u_v2hi, u_v2hi, u_v2hi, V_UMAX16); ++ ADD_NDS32_BUILTIN2 ("sclip16", unsigned, unsigned, unsigned, SCLIP16); ++ ADD_NDS32_BUILTIN2 ("v_sclip16", v2hi, v2hi, unsigned, V_SCLIP16); ++ ADD_NDS32_BUILTIN2 ("uclip16", unsigned, unsigned, unsigned, UCLIP16); ++ ADD_NDS32_BUILTIN2 ("v_uclip16", v2hi, v2hi, unsigned, V_UCLIP16); ++ ADD_NDS32_BUILTIN2 ("khm16", unsigned, unsigned, unsigned, KHM16); ++ ADD_NDS32_BUILTIN2 ("v_khm16", v2hi, v2hi, v2hi, V_KHM16); ++ ADD_NDS32_BUILTIN2 ("khmx16", unsigned, unsigned, unsigned, KHMX16); ++ ADD_NDS32_BUILTIN2 ("v_khmx16", v2hi, v2hi, v2hi, V_KHMX16); ++ ADD_NDS32_BUILTIN1 ("kabs16", unsigned, unsigned, KABS16); ++ ADD_NDS32_BUILTIN1 ("v_kabs16", v2hi, v2hi, V_KABS16); ++ ADD_NDS32_BUILTIN2 ("smul16", long_long_unsigned, unsigned, unsigned, SMUL16); ++ ADD_NDS32_BUILTIN2 ("v_smul16", v2si, v2hi, v2hi, V_SMUL16); ++ ADD_NDS32_BUILTIN2 ("smulx16", ++ long_long_unsigned, unsigned, unsigned, SMULX16); ++ ADD_NDS32_BUILTIN2 ("v_smulx16", v2si, v2hi, v2hi, V_SMULX16); ++ ADD_NDS32_BUILTIN2 ("umul16", long_long_unsigned, unsigned, unsigned, UMUL16); ++ ADD_NDS32_BUILTIN2 ("v_umul16", u_v2si, u_v2hi, u_v2hi, V_UMUL16); ++ ADD_NDS32_BUILTIN2 ("umulx16", ++ long_long_unsigned, unsigned, unsigned, UMULX16); ++ ADD_NDS32_BUILTIN2 ("v_umulx16", u_v2si, u_v2hi, u_v2hi, V_UMULX16); ++ ++ /* DSP Extension: SIMD 8bit MISC. */ ++ ADD_NDS32_BUILTIN2 ("smin8", unsigned, unsigned, unsigned, SMIN8); ++ ADD_NDS32_BUILTIN2 ("v_smin8", v4qi, v4qi, v4qi, V_SMIN8); ++ ADD_NDS32_BUILTIN2 ("umin8", unsigned, unsigned, unsigned, UMIN8); ++ ADD_NDS32_BUILTIN2 ("v_umin8", u_v4qi, u_v4qi, u_v4qi, V_UMIN8); ++ ADD_NDS32_BUILTIN2 ("smax8", unsigned, unsigned, unsigned, SMAX8); ++ ADD_NDS32_BUILTIN2 ("v_smax8", v4qi, v4qi, v4qi, V_SMAX8); ++ ADD_NDS32_BUILTIN2 ("umax8", unsigned, unsigned, unsigned, UMAX8); ++ ADD_NDS32_BUILTIN2 ("v_umax8", u_v4qi, u_v4qi, u_v4qi, V_UMAX8); ++ ADD_NDS32_BUILTIN1 ("kabs8", unsigned, unsigned, KABS8); ++ ADD_NDS32_BUILTIN1 ("v_kabs8", v4qi, v4qi, V_KABS8); ++ ++ /* DSP Extension: 8bit Unpacking. */ ++ ADD_NDS32_BUILTIN1 ("sunpkd810", unsigned, unsigned, SUNPKD810); ++ ADD_NDS32_BUILTIN1 ("v_sunpkd810", v2hi, v4qi, V_SUNPKD810); ++ ADD_NDS32_BUILTIN1 ("sunpkd820", unsigned, unsigned, SUNPKD820); ++ ADD_NDS32_BUILTIN1 ("v_sunpkd820", v2hi, v4qi, V_SUNPKD820); ++ ADD_NDS32_BUILTIN1 ("sunpkd830", unsigned, unsigned, SUNPKD830); ++ ADD_NDS32_BUILTIN1 ("v_sunpkd830", v2hi, v4qi, V_SUNPKD830); ++ ADD_NDS32_BUILTIN1 ("sunpkd831", unsigned, unsigned, SUNPKD831); ++ ADD_NDS32_BUILTIN1 ("v_sunpkd831", v2hi, v4qi, V_SUNPKD831); ++ ADD_NDS32_BUILTIN1 ("zunpkd810", unsigned, unsigned, ZUNPKD810); ++ ADD_NDS32_BUILTIN1 ("v_zunpkd810", u_v2hi, u_v4qi, V_ZUNPKD810); ++ ADD_NDS32_BUILTIN1 ("zunpkd820", unsigned, unsigned, ZUNPKD820); ++ ADD_NDS32_BUILTIN1 ("v_zunpkd820", u_v2hi, u_v4qi, V_ZUNPKD820); ++ ADD_NDS32_BUILTIN1 ("zunpkd830", unsigned, unsigned, ZUNPKD830); ++ ADD_NDS32_BUILTIN1 ("v_zunpkd830", u_v2hi, u_v4qi, V_ZUNPKD830); ++ ADD_NDS32_BUILTIN1 ("zunpkd831", unsigned, unsigned, ZUNPKD831); ++ ADD_NDS32_BUILTIN1 ("v_zunpkd831", u_v2hi, u_v4qi, V_ZUNPKD831); ++ ++ /* DSP Extension: 32bit Add and Subtract. */ ++ ADD_NDS32_BUILTIN2 ("raddw", integer, integer, integer, RADDW); ++ ADD_NDS32_BUILTIN2 ("uraddw", unsigned, unsigned, unsigned, URADDW); ++ ADD_NDS32_BUILTIN2 ("rsubw", integer, integer, integer, RSUBW); ++ ADD_NDS32_BUILTIN2 ("ursubw", unsigned, unsigned, unsigned, URSUBW); ++ ++ /* DSP Extension: 32bit Shift. */ ++ ADD_NDS32_BUILTIN2 ("sra_u", integer, integer, unsigned, SRA_U); ++ ADD_NDS32_BUILTIN2 ("ksll", integer, integer, unsigned, KSLL); ++ ++ /* DSP Extension: 16bit Packing. */ ++ ADD_NDS32_BUILTIN2 ("pkbb16", unsigned, unsigned, unsigned, PKBB16); ++ ADD_NDS32_BUILTIN2 ("v_pkbb16", u_v2hi, u_v2hi, u_v2hi, V_PKBB16); ++ ADD_NDS32_BUILTIN2 ("pkbt16", unsigned, unsigned, unsigned, PKBT16); ++ ADD_NDS32_BUILTIN2 ("v_pkbt16", u_v2hi, u_v2hi, u_v2hi, V_PKBT16); ++ ADD_NDS32_BUILTIN2 ("pktb16", unsigned, unsigned, unsigned, PKTB16); ++ ADD_NDS32_BUILTIN2 ("v_pktb16", u_v2hi, u_v2hi, u_v2hi, V_PKTB16); ++ ADD_NDS32_BUILTIN2 ("pktt16", unsigned, unsigned, unsigned, PKTT16); ++ ADD_NDS32_BUILTIN2 ("v_pktt16", u_v2hi, u_v2hi, u_v2hi, V_PKTT16); ++ ++ /* DSP Extension: Signed MSW 32x32 Multiply and ADD. */ ++ ADD_NDS32_BUILTIN2 ("smmul", integer, integer, integer, SMMUL); ++ ADD_NDS32_BUILTIN2 ("smmul_u", integer, integer, integer, SMMUL_U); ++ ADD_NDS32_BUILTIN3 ("kmmac", integer, integer, integer, integer, KMMAC); ++ ADD_NDS32_BUILTIN3 ("kmmac_u", integer, integer, integer, integer, KMMAC_U); ++ ADD_NDS32_BUILTIN3 ("kmmsb", integer, integer, integer, integer, KMMSB); ++ ADD_NDS32_BUILTIN3 ("kmmsb_u", integer, integer, integer, integer, KMMSB_U); ++ ADD_NDS32_BUILTIN2 ("kwmmul", integer, integer, integer, KWMMUL); ++ ADD_NDS32_BUILTIN2 ("kwmmul_u", integer, integer, integer, KWMMUL_U); ++ ++ /* DSP Extension: Most Significant Word 32x16 Multiply and ADD. */ ++ ADD_NDS32_BUILTIN2 ("smmwb", integer, integer, unsigned, SMMWB); ++ ADD_NDS32_BUILTIN2 ("v_smmwb", integer, integer, v2hi, V_SMMWB); ++ ADD_NDS32_BUILTIN2 ("smmwb_u", integer, integer, unsigned, SMMWB_U); ++ ADD_NDS32_BUILTIN2 ("v_smmwb_u", integer, integer, v2hi, V_SMMWB_U); ++ ADD_NDS32_BUILTIN2 ("smmwt", integer, integer, unsigned, SMMWT); ++ ADD_NDS32_BUILTIN2 ("v_smmwt", integer, integer, v2hi, V_SMMWT); ++ ADD_NDS32_BUILTIN2 ("smmwt_u", integer, integer, unsigned, SMMWT_U); ++ ADD_NDS32_BUILTIN2 ("v_smmwt_u", integer, integer, v2hi, V_SMMWT_U); ++ ADD_NDS32_BUILTIN3 ("kmmawb", integer, integer, integer, unsigned, KMMAWB); ++ ADD_NDS32_BUILTIN3 ("v_kmmawb", integer, integer, integer, v2hi, V_KMMAWB); ++ ADD_NDS32_BUILTIN3 ("kmmawb_u", ++ integer, integer, integer, unsigned, KMMAWB_U); ++ ADD_NDS32_BUILTIN3 ("v_kmmawb_u", ++ integer, integer, integer, v2hi, V_KMMAWB_U); ++ ADD_NDS32_BUILTIN3 ("kmmawt", integer, integer, integer, unsigned, KMMAWT); ++ ADD_NDS32_BUILTIN3 ("v_kmmawt", integer, integer, integer, v2hi, V_KMMAWT); ++ ADD_NDS32_BUILTIN3 ("kmmawt_u", ++ integer, integer, integer, unsigned, KMMAWT_U); ++ ADD_NDS32_BUILTIN3 ("v_kmmawt_u", ++ integer, integer, integer, v2hi, V_KMMAWT_U); ++ ++ /* DSP Extension: Signed 16bit Multiply with ADD/Subtract. */ ++ ADD_NDS32_BUILTIN2 ("smbb", integer, unsigned, unsigned, SMBB); ++ ADD_NDS32_BUILTIN2 ("v_smbb", integer, v2hi, v2hi, V_SMBB); ++ ADD_NDS32_BUILTIN2 ("smbt", integer, unsigned, unsigned, SMBT); ++ ADD_NDS32_BUILTIN2 ("v_smbt", integer, v2hi, v2hi, V_SMBT); ++ ADD_NDS32_BUILTIN2 ("smtt", integer, unsigned, unsigned, SMTT); ++ ADD_NDS32_BUILTIN2 ("v_smtt", integer, v2hi, v2hi, V_SMTT); ++ ADD_NDS32_BUILTIN2 ("kmda", integer, unsigned, unsigned, KMDA); ++ ADD_NDS32_BUILTIN2 ("v_kmda", integer, v2hi, v2hi, V_KMDA); ++ ADD_NDS32_BUILTIN2 ("kmxda", integer, unsigned, unsigned, KMXDA); ++ ADD_NDS32_BUILTIN2 ("v_kmxda", integer, v2hi, v2hi, V_KMXDA); ++ ADD_NDS32_BUILTIN2 ("smds", integer, unsigned, unsigned, SMDS); ++ ADD_NDS32_BUILTIN2 ("v_smds", integer, v2hi, v2hi, V_SMDS); ++ ADD_NDS32_BUILTIN2 ("smdrs", integer, unsigned, unsigned, SMDRS); ++ ADD_NDS32_BUILTIN2 ("v_smdrs", integer, v2hi, v2hi, V_SMDRS); ++ ADD_NDS32_BUILTIN2 ("smxds", integer, unsigned, unsigned, SMXDS); ++ ADD_NDS32_BUILTIN2 ("v_smxds", integer, v2hi, v2hi, V_SMXDS); ++ ADD_NDS32_BUILTIN3 ("kmabb", integer, integer, unsigned, unsigned, KMABB); ++ ADD_NDS32_BUILTIN3 ("v_kmabb", integer, integer, v2hi, v2hi, V_KMABB); ++ ADD_NDS32_BUILTIN3 ("kmabt", integer, integer, unsigned, unsigned, KMABT); ++ ADD_NDS32_BUILTIN3 ("v_kmabt", integer, integer, v2hi, v2hi, V_KMABT); ++ ADD_NDS32_BUILTIN3 ("kmatt", integer, integer, unsigned, unsigned, KMATT); ++ ADD_NDS32_BUILTIN3 ("v_kmatt", integer, integer, v2hi, v2hi, V_KMATT); ++ ADD_NDS32_BUILTIN3 ("kmada", integer, integer, unsigned, unsigned, KMADA); ++ ADD_NDS32_BUILTIN3 ("v_kmada", integer, integer, v2hi, v2hi, V_KMADA); ++ ADD_NDS32_BUILTIN3 ("kmaxda", integer, integer, unsigned, unsigned, KMAXDA); ++ ADD_NDS32_BUILTIN3 ("v_kmaxda", integer, integer, v2hi, v2hi, V_KMAXDA); ++ ADD_NDS32_BUILTIN3 ("kmads", integer, integer, unsigned, unsigned, KMADS); ++ ADD_NDS32_BUILTIN3 ("v_kmads", integer, integer, v2hi, v2hi, V_KMADS); ++ ADD_NDS32_BUILTIN3 ("kmadrs", integer, integer, unsigned, unsigned, KMADRS); ++ ADD_NDS32_BUILTIN3 ("v_kmadrs", integer, integer, v2hi, v2hi, V_KMADRS); ++ ADD_NDS32_BUILTIN3 ("kmaxds", integer, integer, unsigned, unsigned, KMAXDS); ++ ADD_NDS32_BUILTIN3 ("v_kmaxds", integer, integer, v2hi, v2hi, V_KMAXDS); ++ ADD_NDS32_BUILTIN3 ("kmsda", integer, integer, unsigned, unsigned, KMSDA); ++ ADD_NDS32_BUILTIN3 ("v_kmsda", integer, integer, v2hi, v2hi, V_KMSDA); ++ ADD_NDS32_BUILTIN3 ("kmsxda", integer, integer, unsigned, unsigned, KMSXDA); ++ ADD_NDS32_BUILTIN3 ("v_kmsxda", integer, integer, v2hi, v2hi, V_KMSXDA); ++ ++ /* DSP Extension: Signed 16bit Multiply with 64bit ADD/Subtract. */ ++ ADD_NDS32_BUILTIN2 ("smal", long_long_integer, ++ long_long_integer, unsigned, SMAL); ++ ADD_NDS32_BUILTIN2 ("v_smal", long_long_integer, ++ long_long_integer, v2hi, V_SMAL); ++ ++ /* DSP Extension: 32bit MISC. */ ++ ADD_NDS32_BUILTIN2 ("bitrev", unsigned, unsigned, unsigned, BITREV); ++ ADD_NDS32_BUILTIN2 ("wext", unsigned, long_long_integer, unsigned, WEXT); ++ ADD_NDS32_BUILTIN3 ("bpick", unsigned, unsigned, unsigned, unsigned, BPICK); ++ ADD_NDS32_BUILTIN3 ("insb", unsigned, unsigned, unsigned, unsigned, INSB); ++ ++ /* DSP Extension: 64bit Add and Subtract. */ ++ ADD_NDS32_BUILTIN2 ("sadd64", long_long_integer, ++ long_long_integer, long_long_integer, SADD64); ++ ADD_NDS32_BUILTIN2 ("uadd64", long_long_unsigned, ++ long_long_unsigned, long_long_unsigned, UADD64); ++ ADD_NDS32_BUILTIN2 ("radd64", long_long_integer, ++ long_long_integer, long_long_integer, RADD64); ++ ADD_NDS32_BUILTIN2 ("uradd64", long_long_unsigned, ++ long_long_unsigned, long_long_unsigned, URADD64); ++ ADD_NDS32_BUILTIN2 ("kadd64", long_long_integer, ++ long_long_integer, long_long_integer, KADD64); ++ ADD_NDS32_BUILTIN2 ("ukadd64", long_long_unsigned, ++ long_long_unsigned, long_long_unsigned, UKADD64); ++ ADD_NDS32_BUILTIN2 ("ssub64", long_long_integer, ++ long_long_integer, long_long_integer, SSUB64); ++ ADD_NDS32_BUILTIN2 ("usub64", long_long_unsigned, ++ long_long_unsigned, long_long_unsigned, USUB64); ++ ADD_NDS32_BUILTIN2 ("rsub64", long_long_integer, ++ long_long_integer, long_long_integer, RSUB64); ++ ADD_NDS32_BUILTIN2 ("ursub64", long_long_unsigned, ++ long_long_unsigned, long_long_unsigned, URSUB64); ++ ADD_NDS32_BUILTIN2 ("ksub64", long_long_integer, ++ long_long_integer, long_long_integer, KSUB64); ++ ADD_NDS32_BUILTIN2 ("uksub64", long_long_unsigned, ++ long_long_unsigned, long_long_unsigned, UKSUB64); ++ ++ /* DSP Extension: 32bit Multiply with 64bit Add/Subtract. */ ++ ADD_NDS32_BUILTIN3 ("smar64", long_long_integer, ++ long_long_integer, integer, integer, SMAR64); ++ ADD_NDS32_BUILTIN3 ("smsr64", long_long_integer, ++ long_long_integer, integer, integer, SMSR64); ++ ADD_NDS32_BUILTIN3 ("umar64", long_long_unsigned, ++ long_long_unsigned, unsigned, unsigned, UMAR64); ++ ADD_NDS32_BUILTIN3 ("umsr64", long_long_unsigned, ++ long_long_unsigned, unsigned, unsigned, UMSR64); ++ ADD_NDS32_BUILTIN3 ("kmar64", long_long_integer, ++ long_long_integer, integer, integer, KMAR64); ++ ADD_NDS32_BUILTIN3 ("kmsr64", long_long_integer, ++ long_long_integer, integer, integer, KMSR64); ++ ADD_NDS32_BUILTIN3 ("ukmar64", long_long_unsigned, ++ long_long_unsigned, unsigned, unsigned, UKMAR64); ++ ADD_NDS32_BUILTIN3 ("ukmsr64", long_long_unsigned, ++ long_long_unsigned, unsigned, unsigned, UKMSR64); ++ ++ /* DSP Extension: Signed 16bit Multiply with 64bit Add/Subtract. */ ++ ADD_NDS32_BUILTIN3 ("smalbb", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALBB); ++ ADD_NDS32_BUILTIN3 ("v_smalbb", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALBB); ++ ADD_NDS32_BUILTIN3 ("smalbt", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALBT); ++ ADD_NDS32_BUILTIN3 ("v_smalbt", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALBT); ++ ADD_NDS32_BUILTIN3 ("smaltt", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALTT); ++ ADD_NDS32_BUILTIN3 ("v_smaltt", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALTT); ++ ADD_NDS32_BUILTIN3 ("smalda", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALDA); ++ ADD_NDS32_BUILTIN3 ("v_smalda", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALDA); ++ ADD_NDS32_BUILTIN3 ("smalxda", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALXDA); ++ ADD_NDS32_BUILTIN3 ("v_smalxda", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALXDA); ++ ADD_NDS32_BUILTIN3 ("smalds", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALDS); ++ ADD_NDS32_BUILTIN3 ("v_smalds", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALDS); ++ ADD_NDS32_BUILTIN3 ("smaldrs", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALDRS); ++ ADD_NDS32_BUILTIN3 ("v_smaldrs", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALDRS); ++ ADD_NDS32_BUILTIN3 ("smalxds", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMALXDS); ++ ADD_NDS32_BUILTIN3 ("v_smalxds", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMALXDS); ++ ADD_NDS32_BUILTIN3 ("smslda", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMSLDA); ++ ADD_NDS32_BUILTIN3 ("v_smslda", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMSLDA); ++ ADD_NDS32_BUILTIN3 ("smslxda", long_long_integer, ++ long_long_integer, unsigned, unsigned, SMSLXDA); ++ ADD_NDS32_BUILTIN3 ("v_smslxda", long_long_integer, ++ long_long_integer, v2hi, v2hi, V_SMSLXDA); ++ ++ /* DSP Extension: augmented baseline. */ ++ ADD_NDS32_BUILTIN2 ("uclip32", unsigned, integer, unsigned, UCLIP32); ++ ADD_NDS32_BUILTIN2 ("sclip32", integer, integer, unsigned, SCLIP32); ++ ADD_NDS32_BUILTIN1 ("kabs", integer, integer, KABS); ++ ++ /* DSP Extension: vector type unaligned Load/Store */ ++ ADD_NDS32_BUILTIN1 ("get_unaligned_u16x2", u_v2hi, ptr_ushort, UALOAD_U16); ++ ADD_NDS32_BUILTIN1 ("get_unaligned_s16x2", v2hi, ptr_short, UALOAD_S16); ++ ADD_NDS32_BUILTIN1 ("get_unaligned_u8x4", u_v4qi, ptr_uchar, UALOAD_U8); ++ ADD_NDS32_BUILTIN1 ("get_unaligned_s8x4", v4qi, ptr_char, UALOAD_S8); ++ ADD_NDS32_BUILTIN2 ("put_unaligned_u16x2", void, ptr_ushort, ++ u_v2hi, UASTORE_U16); ++ ADD_NDS32_BUILTIN2 ("put_unaligned_s16x2", void, ptr_short, ++ v2hi, UASTORE_S16); ++ ADD_NDS32_BUILTIN2 ("put_unaligned_u8x4", void, ptr_uchar, ++ u_v4qi, UASTORE_U8); ++ ADD_NDS32_BUILTIN2 ("put_unaligned_s8x4", void, ptr_char, ++ v4qi, UASTORE_S8); + } +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32_intrinsic.h gcc-8.2.0/gcc/config/nds32/nds32_intrinsic.h +--- gcc-8.2.0.orig/gcc/config/nds32/nds32_intrinsic.h 2018-04-22 09:46:39.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32_intrinsic.h 2019-01-25 15:38:32.833242671 +0100 +@@ -26,6 +26,13 @@ + #ifndef _NDS32_INTRINSIC_H + #define _NDS32_INTRINSIC_H + ++typedef signed char int8x4_t __attribute ((vector_size(4))); ++typedef short int16x2_t __attribute ((vector_size(4))); ++typedef int int32x2_t __attribute__((vector_size(8))); ++typedef unsigned char uint8x4_t __attribute__ ((vector_size (4))); ++typedef unsigned short uint16x2_t __attribute__ ((vector_size (4))); ++typedef unsigned int uint32x2_t __attribute__((vector_size(8))); ++ + /* General instrinsic register names. */ + enum nds32_intrinsic_registers + { +@@ -691,6 +698,55 @@ + #define __nds32__tlbop_flua() \ + (__builtin_nds32_tlbop_flua()) + ++#define __nds32__kaddw(a, b) \ ++ (__builtin_nds32_kaddw ((a), (b))) ++#define __nds32__kaddh(a, b) \ ++ (__builtin_nds32_kaddh ((a), (b))) ++#define __nds32__ksubw(a, b) \ ++ (__builtin_nds32_ksubw ((a), (b))) ++#define __nds32__ksubh(a, b) \ ++ (__builtin_nds32_ksubh ((a), (b))) ++#define __nds32__kdmbb(a, b) \ ++ (__builtin_nds32_kdmbb ((a), (b))) ++#define __nds32__v_kdmbb(a, b) \ ++ (__builtin_nds32_v_kdmbb ((a), (b))) ++#define __nds32__kdmbt(a, b) \ ++ (__builtin_nds32_kdmbt ((a), (b))) ++#define __nds32__v_kdmbt(a, b) \ ++ (__builtin_nds32_v_kdmbt ((a), (b))) ++#define __nds32__kdmtb(a, b) \ ++ (__builtin_nds32_kdmtb ((a), (b))) ++#define __nds32__v_kdmtb(a, b) \ ++ (__builtin_nds32_v_kdmtb ((a), (b))) ++#define __nds32__kdmtt(a, b) \ ++ (__builtin_nds32_kdmtt ((a), (b))) ++#define __nds32__v_kdmtt(a, b) \ ++ (__builtin_nds32_v_kdmtt ((a), (b))) ++#define __nds32__khmbb(a, b) \ ++ (__builtin_nds32_khmbb ((a), (b))) ++#define __nds32__v_khmbb(a, b) \ ++ (__builtin_nds32_v_khmbb ((a), (b))) ++#define __nds32__khmbt(a, b) \ ++ (__builtin_nds32_khmbt ((a), (b))) ++#define __nds32__v_khmbt(a, b) \ ++ (__builtin_nds32_v_khmbt ((a), (b))) ++#define __nds32__khmtb(a, b) \ ++ (__builtin_nds32_khmtb ((a), (b))) ++#define __nds32__v_khmtb(a, b) \ ++ (__builtin_nds32_v_khmtb ((a), (b))) ++#define __nds32__khmtt(a, b) \ ++ (__builtin_nds32_khmtt ((a), (b))) ++#define __nds32__v_khmtt(a, b) \ ++ (__builtin_nds32_v_khmtt ((a), (b))) ++#define __nds32__kslraw(a, b) \ ++ (__builtin_nds32_kslraw ((a), (b))) ++#define __nds32__kslraw_u(a, b) \ ++ (__builtin_nds32_kslraw_u ((a), (b))) ++ ++#define __nds32__rdov() \ ++ (__builtin_nds32_rdov()) ++#define __nds32__clrov() \ ++ (__builtin_nds32_clrov()) + #define __nds32__gie_dis() \ + (__builtin_nds32_gie_dis()) + #define __nds32__gie_en() \ +@@ -720,10 +776,622 @@ + #define __nds32__get_trig_type(a) \ + (__builtin_nds32_get_trig_type ((a))) + ++#define __nds32__get_unaligned_hw(a) \ ++ (__builtin_nds32_unaligned_load_hw ((a))) ++#define __nds32__get_unaligned_w(a) \ ++ (__builtin_nds32_unaligned_load_w ((a))) ++#define __nds32__get_unaligned_dw(a) \ ++ (__builtin_nds32_unaligned_load_dw ((a))) ++#define __nds32__put_unaligned_hw(a, data) \ ++ (__builtin_nds32_unaligned_store_hw ((a), (data))) ++#define __nds32__put_unaligned_w(a, data) \ ++ (__builtin_nds32_unaligned_store_w ((a), (data))) ++#define __nds32__put_unaligned_dw(a, data) \ ++ (__builtin_nds32_unaligned_store_dw ((a), (data))) ++ ++#define __nds32__add16(a, b) \ ++ (__builtin_nds32_add16 ((a), (b))) ++#define __nds32__v_uadd16(a, b) \ ++ (__builtin_nds32_v_uadd16 ((a), (b))) ++#define __nds32__v_sadd16(a, b) \ ++ (__builtin_nds32_v_sadd16 ((a), (b))) ++#define __nds32__radd16(a, b) \ ++ (__builtin_nds32_radd16 ((a), (b))) ++#define __nds32__v_radd16(a, b) \ ++ (__builtin_nds32_v_radd16 ((a), (b))) ++#define __nds32__uradd16(a, b) \ ++ (__builtin_nds32_uradd16 ((a), (b))) ++#define __nds32__v_uradd16(a, b) \ ++ (__builtin_nds32_v_uradd16 ((a), (b))) ++#define __nds32__kadd16(a, b) \ ++ (__builtin_nds32_kadd16 ((a), (b))) ++#define __nds32__v_kadd16(a, b) \ ++ (__builtin_nds32_v_kadd16 ((a), (b))) ++#define __nds32__ukadd16(a, b) \ ++ (__builtin_nds32_ukadd16 ((a), (b))) ++#define __nds32__v_ukadd16(a, b) \ ++ (__builtin_nds32_v_ukadd16 ((a), (b))) ++#define __nds32__sub16(a, b) \ ++ (__builtin_nds32_sub16 ((a), (b))) ++#define __nds32__v_usub16(a, b) \ ++ (__builtin_nds32_v_usub16 ((a), (b))) ++#define __nds32__v_ssub16(a, b) \ ++ (__builtin_nds32_v_ssub16 ((a), (b))) ++#define __nds32__rsub16(a, b) \ ++ (__builtin_nds32_rsub16 ((a), (b))) ++#define __nds32__v_rsub16(a, b) \ ++ (__builtin_nds32_v_rsub16 ((a), (b))) ++#define __nds32__ursub16(a, b) \ ++ (__builtin_nds32_ursub16 ((a), (b))) ++#define __nds32__v_ursub16(a, b) \ ++ (__builtin_nds32_v_ursub16 ((a), (b))) ++#define __nds32__ksub16(a, b) \ ++ (__builtin_nds32_ksub16 ((a), (b))) ++#define __nds32__v_ksub16(a, b) \ ++ (__builtin_nds32_v_ksub16 ((a), (b))) ++#define __nds32__uksub16(a, b) \ ++ (__builtin_nds32_uksub16 ((a), (b))) ++#define __nds32__v_uksub16(a, b) \ ++ (__builtin_nds32_v_uksub16 ((a), (b))) ++#define __nds32__cras16(a, b) \ ++ (__builtin_nds32_cras16 ((a), (b))) ++#define __nds32__v_ucras16(a, b) \ ++ (__builtin_nds32_v_ucras16 ((a), (b))) ++#define __nds32__v_scras16(a, b) \ ++ (__builtin_nds32_v_scras16 ((a), (b))) ++#define __nds32__rcras16(a, b) \ ++ (__builtin_nds32_rcras16 ((a), (b))) ++#define __nds32__v_rcras16(a, b) \ ++ (__builtin_nds32_v_rcras16 ((a), (b))) ++#define __nds32__urcras16(a, b) \ ++ (__builtin_nds32_urcras16 ((a), (b))) ++#define __nds32__v_urcras16(a, b) \ ++ (__builtin_nds32_v_urcras16 ((a), (b))) ++#define __nds32__kcras16(a, b) \ ++ (__builtin_nds32_kcras16 ((a), (b))) ++#define __nds32__v_kcras16(a, b) \ ++ (__builtin_nds32_v_kcras16 ((a), (b))) ++#define __nds32__ukcras16(a, b) \ ++ (__builtin_nds32_ukcras16 ((a), (b))) ++#define __nds32__v_ukcras16(a, b) \ ++ (__builtin_nds32_v_ukcras16 ((a), (b))) ++#define __nds32__crsa16(a, b) \ ++ (__builtin_nds32_crsa16 ((a), (b))) ++#define __nds32__v_ucrsa16(a, b) \ ++ (__builtin_nds32_v_ucrsa16 ((a), (b))) ++#define __nds32__v_scrsa16(a, b) \ ++ (__builtin_nds32_v_scrsa16 ((a), (b))) ++#define __nds32__rcrsa16(a, b) \ ++ (__builtin_nds32_rcrsa16 ((a), (b))) ++#define __nds32__v_rcrsa16(a, b) \ ++ (__builtin_nds32_v_rcrsa16 ((a), (b))) ++#define __nds32__urcrsa16(a, b) \ ++ (__builtin_nds32_urcrsa16 ((a), (b))) ++#define __nds32__v_urcrsa16(a, b) \ ++ (__builtin_nds32_v_urcrsa16 ((a), (b))) ++#define __nds32__kcrsa16(a, b) \ ++ (__builtin_nds32_kcrsa16 ((a), (b))) ++#define __nds32__v_kcrsa16(a, b) \ ++ (__builtin_nds32_v_kcrsa16 ((a), (b))) ++#define __nds32__ukcrsa16(a, b) \ ++ (__builtin_nds32_ukcrsa16 ((a), (b))) ++#define __nds32__v_ukcrsa16(a, b) \ ++ (__builtin_nds32_v_ukcrsa16 ((a), (b))) ++ ++#define __nds32__add8(a, b) \ ++ (__builtin_nds32_add8 ((a), (b))) ++#define __nds32__v_uadd8(a, b) \ ++ (__builtin_nds32_v_uadd8 ((a), (b))) ++#define __nds32__v_sadd8(a, b) \ ++ (__builtin_nds32_v_sadd8 ((a), (b))) ++#define __nds32__radd8(a, b) \ ++ (__builtin_nds32_radd8 ((a), (b))) ++#define __nds32__v_radd8(a, b) \ ++ (__builtin_nds32_v_radd8 ((a), (b))) ++#define __nds32__uradd8(a, b) \ ++ (__builtin_nds32_uradd8 ((a), (b))) ++#define __nds32__v_uradd8(a, b) \ ++ (__builtin_nds32_v_uradd8 ((a), (b))) ++#define __nds32__kadd8(a, b) \ ++ (__builtin_nds32_kadd8 ((a), (b))) ++#define __nds32__v_kadd8(a, b) \ ++ (__builtin_nds32_v_kadd8 ((a), (b))) ++#define __nds32__ukadd8(a, b) \ ++ (__builtin_nds32_ukadd8 ((a), (b))) ++#define __nds32__v_ukadd8(a, b) \ ++ (__builtin_nds32_v_ukadd8 ((a), (b))) ++#define __nds32__sub8(a, b) \ ++ (__builtin_nds32_sub8 ((a), (b))) ++#define __nds32__v_usub8(a, b) \ ++ (__builtin_nds32_v_usub8 ((a), (b))) ++#define __nds32__v_ssub8(a, b) \ ++ (__builtin_nds32_v_ssub8 ((a), (b))) ++#define __nds32__rsub8(a, b) \ ++ (__builtin_nds32_rsub8 ((a), (b))) ++#define __nds32__v_rsub8(a, b) \ ++ (__builtin_nds32_v_rsub8 ((a), (b))) ++#define __nds32__ursub8(a, b) \ ++ (__builtin_nds32_ursub8 ((a), (b))) ++#define __nds32__v_ursub8(a, b) \ ++ (__builtin_nds32_v_ursub8 ((a), (b))) ++#define __nds32__ksub8(a, b) \ ++ (__builtin_nds32_ksub8 ((a), (b))) ++#define __nds32__v_ksub8(a, b) \ ++ (__builtin_nds32_v_ksub8 ((a), (b))) ++#define __nds32__uksub8(a, b) \ ++ (__builtin_nds32_uksub8 ((a), (b))) ++#define __nds32__v_uksub8(a, b) \ ++ (__builtin_nds32_v_uksub8 ((a), (b))) ++ ++#define __nds32__sra16(a, b) \ ++ (__builtin_nds32_sra16 ((a), (b))) ++#define __nds32__v_sra16(a, b) \ ++ (__builtin_nds32_v_sra16 ((a), (b))) ++#define __nds32__sra16_u(a, b) \ ++ (__builtin_nds32_sra16_u ((a), (b))) ++#define __nds32__v_sra16_u(a, b) \ ++ (__builtin_nds32_v_sra16_u ((a), (b))) ++#define __nds32__srl16(a, b) \ ++ (__builtin_nds32_srl16 ((a), (b))) ++#define __nds32__v_srl16(a, b) \ ++ (__builtin_nds32_v_srl16 ((a), (b))) ++#define __nds32__srl16_u(a, b) \ ++ (__builtin_nds32_srl16_u ((a), (b))) ++#define __nds32__v_srl16_u(a, b) \ ++ (__builtin_nds32_v_srl16_u ((a), (b))) ++#define __nds32__sll16(a, b) \ ++ (__builtin_nds32_sll16 ((a), (b))) ++#define __nds32__v_sll16(a, b) \ ++ (__builtin_nds32_v_sll16 ((a), (b))) ++#define __nds32__ksll16(a, b) \ ++ (__builtin_nds32_ksll16 ((a), (b))) ++#define __nds32__v_ksll16(a, b) \ ++ (__builtin_nds32_v_ksll16 ((a), (b))) ++#define __nds32__kslra16(a, b) \ ++ (__builtin_nds32_kslra16 ((a), (b))) ++#define __nds32__v_kslra16(a, b) \ ++ (__builtin_nds32_v_kslra16 ((a), (b))) ++#define __nds32__kslra16_u(a, b) \ ++ (__builtin_nds32_kslra16_u ((a), (b))) ++#define __nds32__v_kslra16_u(a, b) \ ++ (__builtin_nds32_v_kslra16_u ((a), (b))) ++ ++#define __nds32__cmpeq16(a, b) \ ++ (__builtin_nds32_cmpeq16 ((a), (b))) ++#define __nds32__v_scmpeq16(a, b) \ ++ (__builtin_nds32_v_scmpeq16 ((a), (b))) ++#define __nds32__v_ucmpeq16(a, b) \ ++ (__builtin_nds32_v_ucmpeq16 ((a), (b))) ++#define __nds32__scmplt16(a, b) \ ++ (__builtin_nds32_scmplt16 ((a), (b))) ++#define __nds32__v_scmplt16(a, b) \ ++ (__builtin_nds32_v_scmplt16 ((a), (b))) ++#define __nds32__scmple16(a, b) \ ++ (__builtin_nds32_scmple16 ((a), (b))) ++#define __nds32__v_scmple16(a, b) \ ++ (__builtin_nds32_v_scmple16 ((a), (b))) ++#define __nds32__ucmplt16(a, b) \ ++ (__builtin_nds32_ucmplt16 ((a), (b))) ++#define __nds32__v_ucmplt16(a, b) \ ++ (__builtin_nds32_v_ucmplt16 ((a), (b))) ++#define __nds32__ucmple16(a, b) \ ++ (__builtin_nds32_ucmple16 ((a), (b))) ++#define __nds32__v_ucmple16(a, b) \ ++ (__builtin_nds32_v_ucmple16 ((a), (b))) ++ ++#define __nds32__cmpeq8(a, b) \ ++ (__builtin_nds32_cmpeq8 ((a), (b))) ++#define __nds32__v_scmpeq8(a, b) \ ++ (__builtin_nds32_v_scmpeq8 ((a), (b))) ++#define __nds32__v_ucmpeq8(a, b) \ ++ (__builtin_nds32_v_ucmpeq8 ((a), (b))) ++#define __nds32__scmplt8(a, b) \ ++ (__builtin_nds32_scmplt8 ((a), (b))) ++#define __nds32__v_scmplt8(a, b) \ ++ (__builtin_nds32_v_scmplt8 ((a), (b))) ++#define __nds32__scmple8(a, b) \ ++ (__builtin_nds32_scmple8 ((a), (b))) ++#define __nds32__v_scmple8(a, b) \ ++ (__builtin_nds32_v_scmple8 ((a), (b))) ++#define __nds32__ucmplt8(a, b) \ ++ (__builtin_nds32_ucmplt8 ((a), (b))) ++#define __nds32__v_ucmplt8(a, b) \ ++ (__builtin_nds32_v_ucmplt8 ((a), (b))) ++#define __nds32__ucmple8(a, b) \ ++ (__builtin_nds32_ucmple8 ((a), (b))) ++#define __nds32__v_ucmple8(a, b) \ ++ (__builtin_nds32_v_ucmple8 ((a), (b))) ++ ++#define __nds32__smin16(a, b) \ ++ (__builtin_nds32_smin16 ((a), (b))) ++#define __nds32__v_smin16(a, b) \ ++ (__builtin_nds32_v_smin16 ((a), (b))) ++#define __nds32__umin16(a, b) \ ++ (__builtin_nds32_umin16 ((a), (b))) ++#define __nds32__v_umin16(a, b) \ ++ (__builtin_nds32_v_umin16 ((a), (b))) ++#define __nds32__smax16(a, b) \ ++ (__builtin_nds32_smax16 ((a), (b))) ++#define __nds32__v_smax16(a, b) \ ++ (__builtin_nds32_v_smax16 ((a), (b))) ++#define __nds32__umax16(a, b) \ ++ (__builtin_nds32_umax16 ((a), (b))) ++#define __nds32__v_umax16(a, b) \ ++ (__builtin_nds32_v_umax16 ((a), (b))) ++#define __nds32__sclip16(a, b) \ ++ (__builtin_nds32_sclip16 ((a), (b))) ++#define __nds32__v_sclip16(a, b) \ ++ (__builtin_nds32_v_sclip16 ((a), (b))) ++#define __nds32__uclip16(a, b) \ ++ (__builtin_nds32_uclip16 ((a), (b))) ++#define __nds32__v_uclip16(a, b) \ ++ (__builtin_nds32_v_uclip16 ((a), (b))) ++#define __nds32__khm16(a, b) \ ++ (__builtin_nds32_khm16 ((a), (b))) ++#define __nds32__v_khm16(a, b) \ ++ (__builtin_nds32_v_khm16 ((a), (b))) ++#define __nds32__khmx16(a, b) \ ++ (__builtin_nds32_khmx16 ((a), (b))) ++#define __nds32__v_khmx16(a, b) \ ++ (__builtin_nds32_v_khmx16 ((a), (b))) ++#define __nds32__kabs16(a) \ ++ (__builtin_nds32_kabs16 ((a))) ++#define __nds32__v_kabs16(a) \ ++ (__builtin_nds32_v_kabs16 ((a))) ++ ++#define __nds32__smin8(a, b) \ ++ (__builtin_nds32_smin8 ((a), (b))) ++#define __nds32__v_smin8(a, b) \ ++ (__builtin_nds32_v_smin8 ((a), (b))) ++#define __nds32__umin8(a, b) \ ++ (__builtin_nds32_umin8 ((a), (b))) ++#define __nds32__v_umin8(a, b) \ ++ (__builtin_nds32_v_umin8 ((a), (b))) ++#define __nds32__smax8(a, b) \ ++ (__builtin_nds32_smax8 ((a), (b))) ++#define __nds32__v_smax8(a, b) \ ++ (__builtin_nds32_v_smax8 ((a), (b))) ++#define __nds32__umax8(a, b) \ ++ (__builtin_nds32_umax8 ((a), (b))) ++#define __nds32__v_umax8(a, b) \ ++ (__builtin_nds32_v_umax8 ((a), (b))) ++#define __nds32__kabs8(a) \ ++ (__builtin_nds32_kabs8 ((a))) ++#define __nds32__v_kabs8(a) \ ++ (__builtin_nds32_v_kabs8 ((a))) ++ ++#define __nds32__sunpkd810(a) \ ++ (__builtin_nds32_sunpkd810 ((a))) ++#define __nds32__v_sunpkd810(a) \ ++ (__builtin_nds32_v_sunpkd810 ((a))) ++#define __nds32__sunpkd820(a) \ ++ (__builtin_nds32_sunpkd820 ((a))) ++#define __nds32__v_sunpkd820(a) \ ++ (__builtin_nds32_v_sunpkd820 ((a))) ++#define __nds32__sunpkd830(a) \ ++ (__builtin_nds32_sunpkd830 ((a))) ++#define __nds32__v_sunpkd830(a) \ ++ (__builtin_nds32_v_sunpkd830 ((a))) ++#define __nds32__sunpkd831(a) \ ++ (__builtin_nds32_sunpkd831 ((a))) ++#define __nds32__v_sunpkd831(a) \ ++ (__builtin_nds32_v_sunpkd831 ((a))) ++#define __nds32__zunpkd810(a) \ ++ (__builtin_nds32_zunpkd810 ((a))) ++#define __nds32__v_zunpkd810(a) \ ++ (__builtin_nds32_v_zunpkd810 ((a))) ++#define __nds32__zunpkd820(a) \ ++ (__builtin_nds32_zunpkd820 ((a))) ++#define __nds32__v_zunpkd820(a) \ ++ (__builtin_nds32_v_zunpkd820 ((a))) ++#define __nds32__zunpkd830(a) \ ++ (__builtin_nds32_zunpkd830 ((a))) ++#define __nds32__v_zunpkd830(a) \ ++ (__builtin_nds32_v_zunpkd830 ((a))) ++#define __nds32__zunpkd831(a) \ ++ (__builtin_nds32_zunpkd831 ((a))) ++#define __nds32__v_zunpkd831(a) \ ++ (__builtin_nds32_v_zunpkd831 ((a))) ++ ++#define __nds32__raddw(a, b) \ ++ (__builtin_nds32_raddw ((a), (b))) ++#define __nds32__uraddw(a, b) \ ++ (__builtin_nds32_uraddw ((a), (b))) ++#define __nds32__rsubw(a, b) \ ++ (__builtin_nds32_rsubw ((a), (b))) ++#define __nds32__ursubw(a, b) \ ++ (__builtin_nds32_ursubw ((a), (b))) ++ ++#define __nds32__sra_u(a, b) \ ++ (__builtin_nds32_sra_u ((a), (b))) ++#define __nds32__ksll(a, b) \ ++ (__builtin_nds32_ksll ((a), (b))) ++#define __nds32__pkbb16(a, b) \ ++ (__builtin_nds32_pkbb16 ((a), (b))) ++#define __nds32__v_pkbb16(a, b) \ ++ (__builtin_nds32_v_pkbb16 ((a), (b))) ++#define __nds32__pkbt16(a, b) \ ++ (__builtin_nds32_pkbt16 ((a), (b))) ++#define __nds32__v_pkbt16(a, b) \ ++ (__builtin_nds32_v_pkbt16 ((a), (b))) ++#define __nds32__pktb16(a, b) \ ++ (__builtin_nds32_pktb16 ((a), (b))) ++#define __nds32__v_pktb16(a, b) \ ++ (__builtin_nds32_v_pktb16 ((a), (b))) ++#define __nds32__pktt16(a, b) \ ++ (__builtin_nds32_pktt16 ((a), (b))) ++#define __nds32__v_pktt16(a, b) \ ++ (__builtin_nds32_v_pktt16 ((a), (b))) ++ ++#define __nds32__smmul(a, b) \ ++ (__builtin_nds32_smmul ((a), (b))) ++#define __nds32__smmul_u(a, b) \ ++ (__builtin_nds32_smmul_u ((a), (b))) ++#define __nds32__kmmac(r, a, b) \ ++ (__builtin_nds32_kmmac ((r), (a), (b))) ++#define __nds32__kmmac_u(r, a, b) \ ++ (__builtin_nds32_kmmac_u ((r), (a), (b))) ++#define __nds32__kmmsb(r, a, b) \ ++ (__builtin_nds32_kmmsb ((r), (a), (b))) ++#define __nds32__kmmsb_u(r, a, b) \ ++ (__builtin_nds32_kmmsb_u ((r), (a), (b))) ++#define __nds32__kwmmul(a, b) \ ++ (__builtin_nds32_kwmmul ((a), (b))) ++#define __nds32__kwmmul_u(a, b) \ ++ (__builtin_nds32_kwmmul_u ((a), (b))) ++ ++#define __nds32__smmwb(a, b) \ ++ (__builtin_nds32_smmwb ((a), (b))) ++#define __nds32__v_smmwb(a, b) \ ++ (__builtin_nds32_v_smmwb ((a), (b))) ++#define __nds32__smmwb_u(a, b) \ ++ (__builtin_nds32_smmwb_u ((a), (b))) ++#define __nds32__v_smmwb_u(a, b) \ ++ (__builtin_nds32_v_smmwb_u ((a), (b))) ++#define __nds32__smmwt(a, b) \ ++ (__builtin_nds32_smmwt ((a), (b))) ++#define __nds32__v_smmwt(a, b) \ ++ (__builtin_nds32_v_smmwt ((a), (b))) ++#define __nds32__smmwt_u(a, b) \ ++ (__builtin_nds32_smmwt_u ((a), (b))) ++#define __nds32__v_smmwt_u(a, b) \ ++ (__builtin_nds32_v_smmwt_u ((a), (b))) ++#define __nds32__kmmawb(r, a, b) \ ++ (__builtin_nds32_kmmawb ((r), (a), (b))) ++#define __nds32__v_kmmawb(r, a, b) \ ++ (__builtin_nds32_v_kmmawb ((r), (a), (b))) ++#define __nds32__kmmawb_u(r, a, b) \ ++ (__builtin_nds32_kmmawb_u ((r), (a), (b))) ++#define __nds32__v_kmmawb_u(r, a, b) \ ++ (__builtin_nds32_v_kmmawb_u ((r), (a), (b))) ++#define __nds32__kmmawt(r, a, b) \ ++ (__builtin_nds32_kmmawt ((r), (a), (b))) ++#define __nds32__v_kmmawt(r, a, b) \ ++ (__builtin_nds32_v_kmmawt ((r), (a), (b))) ++#define __nds32__kmmawt_u(r, a, b) \ ++ (__builtin_nds32_kmmawt_u ((r), (a), (b))) ++#define __nds32__v_kmmawt_u(r, a, b) \ ++ (__builtin_nds32_v_kmmawt_u ((r), (a), (b))) ++ ++#define __nds32__smbb(a, b) \ ++ (__builtin_nds32_smbb ((a), (b))) ++#define __nds32__v_smbb(a, b) \ ++ (__builtin_nds32_v_smbb ((a), (b))) ++#define __nds32__smbt(a, b) \ ++ (__builtin_nds32_smbt ((a), (b))) ++#define __nds32__v_smbt(a, b) \ ++ (__builtin_nds32_v_smbt ((a), (b))) ++#define __nds32__smtt(a, b) \ ++ (__builtin_nds32_smtt ((a), (b))) ++#define __nds32__v_smtt(a, b) \ ++ (__builtin_nds32_v_smtt ((a), (b))) ++#define __nds32__kmda(a, b) \ ++ (__builtin_nds32_kmda ((a), (b))) ++#define __nds32__v_kmda(a, b) \ ++ (__builtin_nds32_v_kmda ((a), (b))) ++#define __nds32__kmxda(a, b) \ ++ (__builtin_nds32_kmxda ((a), (b))) ++#define __nds32__v_kmxda(a, b) \ ++ (__builtin_nds32_v_kmxda ((a), (b))) ++#define __nds32__smds(a, b) \ ++ (__builtin_nds32_smds ((a), (b))) ++#define __nds32__v_smds(a, b) \ ++ (__builtin_nds32_v_smds ((a), (b))) ++#define __nds32__smdrs(a, b) \ ++ (__builtin_nds32_smdrs ((a), (b))) ++#define __nds32__v_smdrs(a, b) \ ++ (__builtin_nds32_v_smdrs ((a), (b))) ++#define __nds32__smxds(a, b) \ ++ (__builtin_nds32_smxds ((a), (b))) ++#define __nds32__v_smxds(a, b) \ ++ (__builtin_nds32_v_smxds ((a), (b))) ++#define __nds32__kmabb(r, a, b) \ ++ (__builtin_nds32_kmabb ((r), (a), (b))) ++#define __nds32__v_kmabb(r, a, b) \ ++ (__builtin_nds32_v_kmabb ((r), (a), (b))) ++#define __nds32__kmabt(r, a, b) \ ++ (__builtin_nds32_kmabt ((r), (a), (b))) ++#define __nds32__v_kmabt(r, a, b) \ ++ (__builtin_nds32_v_kmabt ((r), (a), (b))) ++#define __nds32__kmatt(r, a, b) \ ++ (__builtin_nds32_kmatt ((r), (a), (b))) ++#define __nds32__v_kmatt(r, a, b) \ ++ (__builtin_nds32_v_kmatt ((r), (a), (b))) ++#define __nds32__kmada(r, a, b) \ ++ (__builtin_nds32_kmada ((r), (a), (b))) ++#define __nds32__v_kmada(r, a, b) \ ++ (__builtin_nds32_v_kmada ((r), (a), (b))) ++#define __nds32__kmaxda(r, a, b) \ ++ (__builtin_nds32_kmaxda ((r), (a), (b))) ++#define __nds32__v_kmaxda(r, a, b) \ ++ (__builtin_nds32_v_kmaxda ((r), (a), (b))) ++#define __nds32__kmads(r, a, b) \ ++ (__builtin_nds32_kmads ((r), (a), (b))) ++#define __nds32__v_kmads(r, a, b) \ ++ (__builtin_nds32_v_kmads ((r), (a), (b))) ++#define __nds32__kmadrs(r, a, b) \ ++ (__builtin_nds32_kmadrs ((r), (a), (b))) ++#define __nds32__v_kmadrs(r, a, b) \ ++ (__builtin_nds32_v_kmadrs ((r), (a), (b))) ++#define __nds32__kmaxds(r, a, b) \ ++ (__builtin_nds32_kmaxds ((r), (a), (b))) ++#define __nds32__v_kmaxds(r, a, b) \ ++ (__builtin_nds32_v_kmaxds ((r), (a), (b))) ++#define __nds32__kmsda(r, a, b) \ ++ (__builtin_nds32_kmsda ((r), (a), (b))) ++#define __nds32__v_kmsda(r, a, b) \ ++ (__builtin_nds32_v_kmsda ((r), (a), (b))) ++#define __nds32__kmsxda(r, a, b) \ ++ (__builtin_nds32_kmsxda ((r), (a), (b))) ++#define __nds32__v_kmsxda(r, a, b) \ ++ (__builtin_nds32_v_kmsxda ((r), (a), (b))) ++ ++#define __nds32__smal(a, b) \ ++ (__builtin_nds32_smal ((a), (b))) ++#define __nds32__v_smal(a, b) \ ++ (__builtin_nds32_v_smal ((a), (b))) ++ ++#define __nds32__bitrev(a, b) \ ++ (__builtin_nds32_bitrev ((a), (b))) ++#define __nds32__wext(a, b) \ ++ (__builtin_nds32_wext ((a), (b))) ++#define __nds32__bpick(r, a, b) \ ++ (__builtin_nds32_bpick ((r), (a), (b))) ++#define __nds32__insb(r, a, b) \ ++ (__builtin_nds32_insb ((r), (a), (b))) ++ ++#define __nds32__sadd64(a, b) \ ++ (__builtin_nds32_sadd64 ((a), (b))) ++#define __nds32__uadd64(a, b) \ ++ (__builtin_nds32_uadd64 ((a), (b))) ++#define __nds32__radd64(a, b) \ ++ (__builtin_nds32_radd64 ((a), (b))) ++#define __nds32__uradd64(a, b) \ ++ (__builtin_nds32_uradd64 ((a), (b))) ++#define __nds32__kadd64(a, b) \ ++ (__builtin_nds32_kadd64 ((a), (b))) ++#define __nds32__ukadd64(a, b) \ ++ (__builtin_nds32_ukadd64 ((a), (b))) ++#define __nds32__ssub64(a, b) \ ++ (__builtin_nds32_ssub64 ((a), (b))) ++#define __nds32__usub64(a, b) \ ++ (__builtin_nds32_usub64 ((a), (b))) ++#define __nds32__rsub64(a, b) \ ++ (__builtin_nds32_rsub64 ((a), (b))) ++#define __nds32__ursub64(a, b) \ ++ (__builtin_nds32_ursub64 ((a), (b))) ++#define __nds32__ksub64(a, b) \ ++ (__builtin_nds32_ksub64 ((a), (b))) ++#define __nds32__uksub64(a, b) \ ++ (__builtin_nds32_uksub64 ((a), (b))) ++ ++#define __nds32__smar64(r, a, b) \ ++ (__builtin_nds32_smar64 ((r), (a), (b))) ++#define __nds32__smsr64(r, a, b) \ ++ (__builtin_nds32_smsr64 ((r), (a), (b))) ++#define __nds32__umar64(r, a, b) \ ++ (__builtin_nds32_umar64 ((r), (a), (b))) ++#define __nds32__umsr64(r, a, b) \ ++ (__builtin_nds32_umsr64 ((r), (a), (b))) ++#define __nds32__kmar64(r, a, b) \ ++ (__builtin_nds32_kmar64 ((r), (a), (b))) ++#define __nds32__kmsr64(r, a, b) \ ++ (__builtin_nds32_kmsr64 ((r), (a), (b))) ++#define __nds32__ukmar64(r, a, b) \ ++ (__builtin_nds32_ukmar64 ((r), (a), (b))) ++#define __nds32__ukmsr64(r, a, b) \ ++ (__builtin_nds32_ukmsr64 ((r), (a), (b))) ++ ++#define __nds32__smalbb(r, a, b) \ ++ (__builtin_nds32_smalbb ((r), (a), (b))) ++#define __nds32__v_smalbb(r, a, b) \ ++ (__builtin_nds32_v_smalbb ((r), (a), (b))) ++#define __nds32__smalbt(r, a, b) \ ++ (__builtin_nds32_smalbt ((r), (a), (b))) ++#define __nds32__v_smalbt(r, a, b) \ ++ (__builtin_nds32_v_smalbt ((r), (a), (b))) ++#define __nds32__smaltt(r, a, b) \ ++ (__builtin_nds32_smaltt ((r), (a), (b))) ++#define __nds32__v_smaltt(r, a, b) \ ++ (__builtin_nds32_v_smaltt ((r), (a), (b))) ++#define __nds32__smalda(r, a, b) \ ++ (__builtin_nds32_smalda ((r), (a), (b))) ++#define __nds32__v_smalda(r, a, b) \ ++ (__builtin_nds32_v_smalda ((r), (a), (b))) ++#define __nds32__smalxda(r, a, b) \ ++ (__builtin_nds32_smalxda ((r), (a), (b))) ++#define __nds32__v_smalxda(r, a, b) \ ++ (__builtin_nds32_v_smalxda ((r), (a), (b))) ++#define __nds32__smalds(r, a, b) \ ++ (__builtin_nds32_smalds ((r), (a), (b))) ++#define __nds32__v_smalds(r, a, b) \ ++ (__builtin_nds32_v_smalds ((r), (a), (b))) ++#define __nds32__smaldrs(r, a, b) \ ++ (__builtin_nds32_smaldrs ((r), (a), (b))) ++#define __nds32__v_smaldrs(r, a, b) \ ++ (__builtin_nds32_v_smaldrs ((r), (a), (b))) ++#define __nds32__smalxds(r, a, b) \ ++ (__builtin_nds32_smalxds ((r), (a), (b))) ++#define __nds32__v_smalxds(r, a, b) \ ++ (__builtin_nds32_v_smalxds ((r), (a), (b))) ++#define __nds32__smslda(r, a, b) \ ++ (__builtin_nds32_smslda ((r), (a), (b))) ++#define __nds32__v_smslda(r, a, b) \ ++ (__builtin_nds32_v_smslda ((r), (a), (b))) ++#define __nds32__smslxda(r, a, b) \ ++ (__builtin_nds32_smslxda ((r), (a), (b))) ++#define __nds32__v_smslxda(r, a, b) \ ++ (__builtin_nds32_v_smslxda ((r), (a), (b))) ++ ++#define __nds32__smul16(a, b) \ ++ (__builtin_nds32_smul16 ((a), (b))) ++#define __nds32__v_smul16(a, b) \ ++ (__builtin_nds32_v_smul16 ((a), (b))) ++#define __nds32__smulx16(a, b) \ ++ (__builtin_nds32_smulx16 ((a), (b))) ++#define __nds32__v_smulx16(a, b) \ ++ (__builtin_nds32_v_smulx16 ((a), (b))) ++#define __nds32__umul16(a, b) \ ++ (__builtin_nds32_umul16 ((a), (b))) ++#define __nds32__v_umul16(a, b) \ ++ (__builtin_nds32_v_umul16 ((a), (b))) ++#define __nds32__umulx16(a, b) \ ++ (__builtin_nds32_umulx16 ((a), (b))) ++#define __nds32__v_umulx16(a, b) \ ++ (__builtin_nds32_v_umulx16 ((a), (b))) ++ ++#define __nds32__uclip32(a, imm) \ ++ (__builtin_nds32_uclip32 ((a), (imm))) ++#define __nds32__sclip32(a, imm) \ ++ (__builtin_nds32_sclip32 ((a), (imm))) ++#define __nds32__kabs(a) \ ++ (__builtin_nds32_kabs ((a))) ++ + #define __nds32__unaligned_feature() \ + (__builtin_nds32_unaligned_feature()) + #define __nds32__enable_unaligned() \ + (__builtin_nds32_enable_unaligned()) + #define __nds32__disable_unaligned() \ + (__builtin_nds32_disable_unaligned()) ++ ++#define __nds32__get_unaligned_u16x2(a) \ ++ (__builtin_nds32_get_unaligned_u16x2 ((a))) ++#define __nds32__get_unaligned_s16x2(a) \ ++ (__builtin_nds32_get_unaligned_s16x2 ((a))) ++#define __nds32__get_unaligned_u8x4(a) \ ++ (__builtin_nds32_get_unaligned_u8x4 ((a))) ++#define __nds32__get_unaligned_s8x4(a) \ ++ (__builtin_nds32_get_unaligned_s8x4 ((a))) ++ ++#define __nds32__put_unaligned_u16x2(a, data) \ ++ (__builtin_nds32_put_unaligned_u16x2 ((a), (data))) ++#define __nds32__put_unaligned_s16x2(a, data) \ ++ (__builtin_nds32_put_unaligned_s16x2 ((a), (data))) ++#define __nds32__put_unaligned_u8x4(a, data) \ ++ (__builtin_nds32_put_unaligned_u8x4 ((a), (data))) ++#define __nds32__put_unaligned_s8x4(a, data) \ ++ (__builtin_nds32_put_unaligned_s8x4 ((a), (data))) ++ ++#define NDS32ATTR_SIGNATURE __attribute__((signature)) ++ + #endif /* nds32_intrinsic.h */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.md gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-intrinsic.md 2018-04-22 09:46:39.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-intrinsic.md 2019-01-25 15:38:32.825242648 +0100 +@@ -1037,6 +1037,187 @@ + (set_attr "length" "4")] + ) + ++;; SATURATION ++ ++(define_insn "unspec_kaddw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")))] ++ "" ++ "kaddw\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_ksubw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_minus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")))] ++ "" ++ "ksubw\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kaddh" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KADDH))] ++ "" ++ "kaddh\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_ksubh" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSUBH))] ++ "" ++ "ksubh\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kaddh_dsp" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")) ++ (const_int 15)] UNSPEC_CLIPS))] ++ "NDS32_EXT_DSP_P ()" ++ "kaddh\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_ksubh_dsp" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(minus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")) ++ (const_int 15)] UNSPEC_CLIPS))] ++ "NDS32_EXT_DSP_P ()" ++ "ksubh\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kdmbb" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMBB))] ++ "" ++ "kdmbb\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kdmbt" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMBT))] ++ "" ++ "kdmbt\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kdmtb" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMTB))] ++ "" ++ "kdmtb\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kdmtt" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMTT))] ++ "" ++ "kdmtt\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_khmbb" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMBB))] ++ "" ++ "khmbb\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_khmbt" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMBT))] ++ "" ++ "khmbt\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_khmtb" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMTB))] ++ "" ++ "khmtb\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_khmtt" ++ [(set (match_operand:V2HI 0 "register_operand" "=r") ++ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r") ++ (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMTT))] ++ "" ++ "khmtt\t%0, %1, %2" ++ [(set_attr "type" "mul") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kslraw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAW))] ++ "" ++ "kslraw\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_kslrawu" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAWU))] ++ "" ++ "kslraw.u\t%0, %1, %2" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_volatile_rdov" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_RDOV))] ++ "" ++ "rdov\t%0" ++ [(set_attr "type" "misc") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "unspec_volatile_clrov" ++ [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CLROV)] ++ "" ++ "clrov" ++ [(set_attr "type" "misc") ++ (set_attr "length" "4")] ++) ++ + ;; System + + (define_insn "unspec_sva" +@@ -1415,22 +1596,17 @@ + if (TARGET_ISA_V3M) + nds32_expand_unaligned_store (operands, DImode); + else +- emit_insn (gen_unaligned_store_dw (operands[0], operands[1])); ++ emit_insn (gen_unaligned_store_dw (gen_rtx_MEM (DImode, operands[0]), ++ operands[1])); + DONE; + }) + + (define_insn "unaligned_store_dw" +- [(set (mem:DI (match_operand:SI 0 "register_operand" "r")) +- (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))] ++ [(set (match_operand:DI 0 "nds32_lmw_smw_base_operand" "=Umw") ++ (unspec:DI [(match_operand:DI 1 "register_operand" " r")] UNSPEC_UASTORE_DW))] + "" + { +- rtx otherops[3]; +- otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1])); +- otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); +- otherops[2] = operands[0]; +- +- output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops); +- return ""; ++ return nds32_output_smw_double_word (operands); + } + [(set_attr "type" "store") + (set_attr "length" "4")] +@@ -1495,4 +1671,15 @@ + DONE; + }) + ++;; abs alias kabs ++ ++(define_insn "unspec_kabs" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_KABS))] ++ "" ++ "kabs\t%0, %1" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ + ;; ------------------------------------------------------------------------ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-isr.c gcc-8.2.0/gcc/config/nds32/nds32-isr.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-isr.c 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-isr.c 2019-01-25 15:38:32.829242659 +0100 +@@ -43,7 +43,260 @@ + We use an array to record essential information for each vector. */ + static struct nds32_isr_info nds32_isr_vectors[NDS32_N_ISR_VECTORS]; + +-/* ------------------------------------------------------------------------ */ ++/* ------------------------------------------------------------- */ ++/* FIXME: ++ FOR BACKWARD COMPATIBILITY, we need to support following patterns: ++ ++ __attribute__((interrupt("XXX;YYY;id=ZZZ"))) ++ __attribute__((exception("XXX;YYY;id=ZZZ"))) ++ __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) ++ ++ We provide several functions to parse the strings. */ ++ ++static void ++nds32_interrupt_attribute_parse_string (const char *original_str, ++ const char *func_name, ++ unsigned int s_level) ++{ ++ char target_str[100]; ++ enum nds32_isr_save_reg save_reg; ++ enum nds32_isr_nested_type nested_type; ++ ++ char *save_all_regs_str, *save_caller_regs_str; ++ char *nested_str, *not_nested_str, *ready_nested_str, *critical_str; ++ char *id_str, *value_str; ++ ++ /* Copy original string into a character array so that ++ the string APIs can handle it. */ ++ strcpy (target_str, original_str); ++ ++ /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL ++ 'save_caller_regs' : NDS32_PARTIAL_SAVE */ ++ save_all_regs_str = strstr (target_str, "save_all_regs"); ++ save_caller_regs_str = strstr (target_str, "save_caller_regs"); ++ ++ /* Note that if no argument is found, ++ use NDS32_PARTIAL_SAVE by default. */ ++ if (save_all_regs_str) ++ save_reg = NDS32_SAVE_ALL; ++ else if (save_caller_regs_str) ++ save_reg = NDS32_PARTIAL_SAVE; ++ else ++ save_reg = NDS32_PARTIAL_SAVE; ++ ++ /* 2. Detect 'nested' : NDS32_NESTED ++ 'not_nested' : NDS32_NOT_NESTED ++ 'ready_nested' : NDS32_NESTED_READY ++ 'critical' : NDS32_CRITICAL */ ++ nested_str = strstr (target_str, "nested"); ++ not_nested_str = strstr (target_str, "not_nested"); ++ ready_nested_str = strstr (target_str, "ready_nested"); ++ critical_str = strstr (target_str, "critical"); ++ ++ /* Note that if no argument is found, ++ use NDS32_NOT_NESTED by default. ++ Also, since 'not_nested' and 'ready_nested' both contains ++ 'nested' string, we check 'nested' with lowest priority. */ ++ if (not_nested_str) ++ nested_type = NDS32_NOT_NESTED; ++ else if (ready_nested_str) ++ nested_type = NDS32_NESTED_READY; ++ else if (nested_str) ++ nested_type = NDS32_NESTED; ++ else if (critical_str) ++ nested_type = NDS32_CRITICAL; ++ else ++ nested_type = NDS32_NOT_NESTED; ++ ++ /* 3. Traverse each id value and set corresponding information. */ ++ id_str = strstr (target_str, "id="); ++ ++ /* If user forgets to assign 'id', issue an error message. */ ++ if (id_str == NULL) ++ error ("require id argument in the string"); ++ /* Extract the value_str first. */ ++ id_str = strtok (id_str, "="); ++ value_str = strtok (NULL, ";"); ++ ++ /* Pick up the first id value token. */ ++ value_str = strtok (value_str, ","); ++ while (value_str != NULL) ++ { ++ int i; ++ i = atoi (value_str); ++ ++ /* For interrupt(0..63), the actual vector number is (9..72). */ ++ i = i + 9; ++ if (i < 9 || i > 72) ++ error ("invalid id value for interrupt attribute"); ++ ++ /* Setup nds32_isr_vectors[] array. */ ++ nds32_isr_vectors[i].category = NDS32_ISR_INTERRUPT; ++ strcpy (nds32_isr_vectors[i].func_name, func_name); ++ nds32_isr_vectors[i].save_reg = save_reg; ++ nds32_isr_vectors[i].nested_type = nested_type; ++ nds32_isr_vectors[i].security_level = s_level; ++ ++ /* Fetch next token. */ ++ value_str = strtok (NULL, ","); ++ } ++ ++ return; ++} ++ ++static void ++nds32_exception_attribute_parse_string (const char *original_str, ++ const char *func_name, ++ unsigned int s_level) ++{ ++ char target_str[100]; ++ enum nds32_isr_save_reg save_reg; ++ enum nds32_isr_nested_type nested_type; ++ ++ char *save_all_regs_str, *save_caller_regs_str; ++ char *nested_str, *not_nested_str, *ready_nested_str, *critical_str; ++ char *id_str, *value_str; ++ ++ /* Copy original string into a character array so that ++ the string APIs can handle it. */ ++ strcpy (target_str, original_str); ++ ++ /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL ++ 'save_caller_regs' : NDS32_PARTIAL_SAVE */ ++ save_all_regs_str = strstr (target_str, "save_all_regs"); ++ save_caller_regs_str = strstr (target_str, "save_caller_regs"); ++ ++ /* Note that if no argument is found, ++ use NDS32_PARTIAL_SAVE by default. */ ++ if (save_all_regs_str) ++ save_reg = NDS32_SAVE_ALL; ++ else if (save_caller_regs_str) ++ save_reg = NDS32_PARTIAL_SAVE; ++ else ++ save_reg = NDS32_PARTIAL_SAVE; ++ ++ /* 2. Detect 'nested' : NDS32_NESTED ++ 'not_nested' : NDS32_NOT_NESTED ++ 'ready_nested' : NDS32_NESTED_READY ++ 'critical' : NDS32_CRITICAL */ ++ nested_str = strstr (target_str, "nested"); ++ not_nested_str = strstr (target_str, "not_nested"); ++ ready_nested_str = strstr (target_str, "ready_nested"); ++ critical_str = strstr (target_str, "critical"); ++ ++ /* Note that if no argument is found, ++ use NDS32_NOT_NESTED by default. ++ Also, since 'not_nested' and 'ready_nested' both contains ++ 'nested' string, we check 'nested' with lowest priority. */ ++ if (not_nested_str) ++ nested_type = NDS32_NOT_NESTED; ++ else if (ready_nested_str) ++ nested_type = NDS32_NESTED_READY; ++ else if (nested_str) ++ nested_type = NDS32_NESTED; ++ else if (critical_str) ++ nested_type = NDS32_CRITICAL; ++ else ++ nested_type = NDS32_NOT_NESTED; ++ ++ /* 3. Traverse each id value and set corresponding information. */ ++ id_str = strstr (target_str, "id="); ++ ++ /* If user forgets to assign 'id', issue an error message. */ ++ if (id_str == NULL) ++ error ("require id argument in the string"); ++ /* Extract the value_str first. */ ++ id_str = strtok (id_str, "="); ++ value_str = strtok (NULL, ";"); ++ ++ /* Pick up the first id value token. */ ++ value_str = strtok (value_str, ","); ++ while (value_str != NULL) ++ { ++ int i; ++ i = atoi (value_str); ++ ++ /* For exception(1..8), the actual vector number is (1..8). */ ++ if (i < 1 || i > 8) ++ error ("invalid id value for exception attribute"); ++ ++ /* Setup nds32_isr_vectors[] array. */ ++ nds32_isr_vectors[i].category = NDS32_ISR_EXCEPTION; ++ strcpy (nds32_isr_vectors[i].func_name, func_name); ++ nds32_isr_vectors[i].save_reg = save_reg; ++ nds32_isr_vectors[i].nested_type = nested_type; ++ nds32_isr_vectors[i].security_level = s_level; ++ ++ /* Fetch next token. */ ++ value_str = strtok (NULL, ","); ++ } ++ ++ return; ++} ++ ++static void ++nds32_reset_attribute_parse_string (const char *original_str, ++ const char *func_name) ++{ ++ char target_str[100]; ++ char *vectors_str, *nmi_str, *warm_str, *value_str; ++ ++ /* Deal with reset attribute. Its vector number is always 0. */ ++ nds32_isr_vectors[0].category = NDS32_ISR_RESET; ++ ++ ++ /* 1. Parse 'vectors=XXXX'. */ ++ ++ /* Copy original string into a character array so that ++ the string APIs can handle it. */ ++ strcpy (target_str, original_str); ++ vectors_str = strstr (target_str, "vectors="); ++ /* The total vectors = interrupt + exception numbers + reset. ++ There are 8 exception and 1 reset in nds32 architecture. ++ If user forgets to assign 'vectors', user default 16 interrupts. */ ++ if (vectors_str != NULL) ++ { ++ /* Extract the value_str. */ ++ vectors_str = strtok (vectors_str, "="); ++ value_str = strtok (NULL, ";"); ++ nds32_isr_vectors[0].total_n_vectors = atoi (value_str) + 8 + 1; ++ } ++ else ++ nds32_isr_vectors[0].total_n_vectors = 16 + 8 + 1; ++ strcpy (nds32_isr_vectors[0].func_name, func_name); ++ ++ ++ /* 2. Parse 'nmi_func=YYYY'. */ ++ ++ /* Copy original string into a character array so that ++ the string APIs can handle it. */ ++ strcpy (target_str, original_str); ++ nmi_str = strstr (target_str, "nmi_func="); ++ if (nmi_str != NULL) ++ { ++ /* Extract the value_str. */ ++ nmi_str = strtok (nmi_str, "="); ++ value_str = strtok (NULL, ";"); ++ strcpy (nds32_isr_vectors[0].nmi_name, value_str); ++ } ++ ++ /* 3. Parse 'warm_func=ZZZZ'. */ ++ ++ /* Copy original string into a character array so that ++ the string APIs can handle it. */ ++ strcpy (target_str, original_str); ++ warm_str = strstr (target_str, "warm_func="); ++ if (warm_str != NULL) ++ { ++ /* Extract the value_str. */ ++ warm_str = strtok (warm_str, "="); ++ value_str = strtok (NULL, ";"); ++ strcpy (nds32_isr_vectors[0].warm_name, value_str); ++ } ++ ++ return; ++} ++/* ------------------------------------------------------------- */ + + /* A helper function to emit section head template. */ + static void +@@ -79,6 +332,15 @@ + char section_name[100]; + char symbol_name[100]; + ++ /* A critical isr does not need jump table section because ++ its behavior is not performed by two-level handler. */ ++ if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL) ++ { ++ fprintf (asm_out_file, "\t! The vector %02d is a critical isr !\n", ++ vector_id); ++ return; ++ } ++ + /* Prepare jmptbl section and symbol name. */ + snprintf (section_name, sizeof (section_name), + ".nds32_jmptbl.%02d", vector_id); +@@ -99,7 +361,6 @@ + const char *c_str = "CATEGORY"; + const char *sr_str = "SR"; + const char *nt_str = "NT"; +- const char *vs_str = "VS"; + char first_level_handler_name[100]; + char section_name[100]; + char symbol_name[100]; +@@ -147,30 +408,47 @@ + case NDS32_NESTED_READY: + nt_str = "nr"; + break; ++ case NDS32_CRITICAL: ++ /* The critical isr is not performed by two-level handler. */ ++ nt_str = ""; ++ break; + } + +- /* Currently we have 4-byte or 16-byte size for each vector. +- If it is 4-byte, the first level handler name has suffix string "_4b". */ +- vs_str = (nds32_isr_vector_size == 4) ? "_4b" : ""; +- + /* Now we can create first level handler name. */ +- snprintf (first_level_handler_name, sizeof (first_level_handler_name), +- "_nds32_%s_%s_%s%s", c_str, sr_str, nt_str, vs_str); ++ if (nds32_isr_vectors[vector_id].security_level == 0) ++ { ++ /* For security level 0, use normal first level handler name. */ ++ snprintf (first_level_handler_name, sizeof (first_level_handler_name), ++ "_nds32_%s_%s_%s", c_str, sr_str, nt_str); ++ } ++ else ++ { ++ /* For security level 1-3, use corresponding spl_1, spl_2, or spl_3. */ ++ snprintf (first_level_handler_name, sizeof (first_level_handler_name), ++ "_nds32_spl_%d", nds32_isr_vectors[vector_id].security_level); ++ } + + /* Prepare vector section and symbol name. */ + snprintf (section_name, sizeof (section_name), + ".nds32_vector.%02d", vector_id); + snprintf (symbol_name, sizeof (symbol_name), +- "_nds32_vector_%02d%s", vector_id, vs_str); ++ "_nds32_vector_%02d", vector_id); + + + /* Everything is ready. We can start emit vector section content. */ + nds32_emit_section_head_template (section_name, symbol_name, + floor_log2 (nds32_isr_vector_size), false); + +- /* According to the vector size, the instructions in the +- vector section may be different. */ +- if (nds32_isr_vector_size == 4) ++ /* First we check if it is a critical isr. ++ If so, jump to user handler directly; otherwise, the instructions ++ in the vector section may be different according to the vector size. */ ++ if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL) ++ { ++ /* This block is for critical isr. Jump to user handler directly. */ ++ fprintf (asm_out_file, "\tj\t%s ! jump to user handler directly\n", ++ nds32_isr_vectors[vector_id].func_name); ++ } ++ else if (nds32_isr_vector_size == 4) + { + /* This block is for 4-byte vector size. + Hardware $VID support is necessary and only one instruction +@@ -239,13 +517,11 @@ + { + unsigned int i; + unsigned int total_n_vectors; +- const char *vs_str; + char reset_handler_name[100]; + char section_name[100]; + char symbol_name[100]; + + total_n_vectors = nds32_isr_vectors[0].total_n_vectors; +- vs_str = (nds32_isr_vector_size == 4) ? "_4b" : ""; + + fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - BEGIN !\n"); + +@@ -261,7 +537,7 @@ + /* Emit vector references. */ + fprintf (asm_out_file, "\t ! references to vector section entries\n"); + for (i = 0; i < total_n_vectors; i++) +- fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d%s\n", i, vs_str); ++ fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d\n", i); + + /* Emit jmptbl_00 section. */ + snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.00"); +@@ -275,9 +551,9 @@ + + /* Emit vector_00 section. */ + snprintf (section_name, sizeof (section_name), ".nds32_vector.00"); +- snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00%s", vs_str); ++ snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00"); + snprintf (reset_handler_name, sizeof (reset_handler_name), +- "_nds32_reset%s", vs_str); ++ "_nds32_reset"); + + fprintf (asm_out_file, "\t! ....................................\n"); + nds32_emit_section_head_template (section_name, symbol_name, +@@ -323,12 +599,12 @@ + nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs) + { + int save_all_p, partial_save_p; +- int nested_p, not_nested_p, nested_ready_p; ++ int nested_p, not_nested_p, nested_ready_p, critical_p; + int intr_p, excp_p, reset_p; + + /* Initialize variables. */ + save_all_p = partial_save_p = 0; +- nested_p = not_nested_p = nested_ready_p = 0; ++ nested_p = not_nested_p = nested_ready_p = critical_p = 0; + intr_p = excp_p = reset_p = 0; + + /* We must check at MOST one attribute to set save-reg. */ +@@ -347,8 +623,10 @@ + not_nested_p = 1; + if (lookup_attribute ("nested_ready", func_attrs)) + nested_ready_p = 1; ++ if (lookup_attribute ("critical", func_attrs)) ++ critical_p = 1; + +- if ((nested_p + not_nested_p + nested_ready_p) > 1) ++ if ((nested_p + not_nested_p + nested_ready_p + critical_p) > 1) + error ("multiple nested types attributes to function %qD", func_decl); + + /* We must check at MOST one attribute to +@@ -362,6 +640,17 @@ + + if ((intr_p + excp_p + reset_p) > 1) + error ("multiple interrupt attributes to function %qD", func_decl); ++ ++ /* Do not allow isr attributes under linux toolchain. */ ++ if (TARGET_LINUX_ABI && intr_p) ++ error ("cannot use interrupt attributes to function %qD " ++ "under linux toolchain", func_decl); ++ if (TARGET_LINUX_ABI && excp_p) ++ error ("cannot use exception attributes to function %qD " ++ "under linux toolchain", func_decl); ++ if (TARGET_LINUX_ABI && reset_p) ++ error ("cannot use reset attributes to function %qD " ++ "under linux toolchain", func_decl); + } + + /* Function to construct isr vectors information array. +@@ -373,15 +662,21 @@ + const char *func_name) + { + tree save_all, partial_save; +- tree nested, not_nested, nested_ready; ++ tree nested, not_nested, nested_ready, critical; + tree intr, excp, reset; + ++ tree secure; ++ tree security_level_list; ++ tree security_level; ++ unsigned int s_level; ++ + save_all = lookup_attribute ("save_all", func_attrs); + partial_save = lookup_attribute ("partial_save", func_attrs); + + nested = lookup_attribute ("nested", func_attrs); + not_nested = lookup_attribute ("not_nested", func_attrs); + nested_ready = lookup_attribute ("nested_ready", func_attrs); ++ critical = lookup_attribute ("critical", func_attrs); + + intr = lookup_attribute ("interrupt", func_attrs); + excp = lookup_attribute ("exception", func_attrs); +@@ -391,6 +686,63 @@ + if (!intr && !excp && !reset) + return; + ++ /* At first, we need to retrieve security level. */ ++ secure = lookup_attribute ("secure", func_attrs); ++ if (secure != NULL) ++ { ++ security_level_list = TREE_VALUE (secure); ++ security_level = TREE_VALUE (security_level_list); ++ s_level = TREE_INT_CST_LOW (security_level); ++ } ++ else ++ { ++ /* If there is no secure attribute, the security level is set by ++ nds32_isr_secure_level, which is controlled by -misr-secure=X option. ++ By default nds32_isr_secure_level should be 0. */ ++ s_level = nds32_isr_secure_level; ++ } ++ ++ /* ------------------------------------------------------------- */ ++ /* FIXME: ++ FOR BACKWARD COMPATIBILITY, we need to support following patterns: ++ ++ __attribute__((interrupt("XXX;YYY;id=ZZZ"))) ++ __attribute__((exception("XXX;YYY;id=ZZZ"))) ++ __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) ++ ++ If interrupt/exception/reset appears and its argument is a ++ STRING_CST, we will parse string with some auxiliary functions ++ which set necessary isr information in the nds32_isr_vectors[] array. ++ After that, we can return immediately to avoid new-syntax isr ++ information construction. */ ++ if (intr != NULL_TREE ++ && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) ++ { ++ tree string_arg = TREE_VALUE (TREE_VALUE (intr)); ++ nds32_interrupt_attribute_parse_string (TREE_STRING_POINTER (string_arg), ++ func_name, ++ s_level); ++ return; ++ } ++ if (excp != NULL_TREE ++ && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) ++ { ++ tree string_arg = TREE_VALUE (TREE_VALUE (excp)); ++ nds32_exception_attribute_parse_string (TREE_STRING_POINTER (string_arg), ++ func_name, ++ s_level); ++ return; ++ } ++ if (reset != NULL_TREE ++ && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) ++ { ++ tree string_arg = TREE_VALUE (TREE_VALUE (reset)); ++ nds32_reset_attribute_parse_string (TREE_STRING_POINTER (string_arg), ++ func_name); ++ return; ++ } ++ /* ------------------------------------------------------------- */ ++ + /* If we are here, either we have interrupt/exception, + or reset attribute. */ + if (intr || excp) +@@ -417,6 +769,9 @@ + /* Add vector_number_offset to get actual vector number. */ + vector_id = TREE_INT_CST_LOW (id) + vector_number_offset; + ++ /* Set security level. */ ++ nds32_isr_vectors[vector_id].security_level = s_level; ++ + /* Enable corresponding vector and set function name. */ + nds32_isr_vectors[vector_id].category = (intr) + ? (NDS32_ISR_INTERRUPT) +@@ -436,6 +791,8 @@ + nds32_isr_vectors[vector_id].nested_type = NDS32_NOT_NESTED; + else if (nested_ready) + nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED_READY; ++ else if (critical) ++ nds32_isr_vectors[vector_id].nested_type = NDS32_CRITICAL; + + /* Advance to next id. */ + id_list = TREE_CHAIN (id_list); +@@ -492,7 +849,6 @@ + } + } + +-/* A helper function to handle isr stuff at the beginning of asm file. */ + void + nds32_asm_file_start_for_isr (void) + { +@@ -505,15 +861,14 @@ + strcpy (nds32_isr_vectors[i].func_name, ""); + nds32_isr_vectors[i].save_reg = NDS32_PARTIAL_SAVE; + nds32_isr_vectors[i].nested_type = NDS32_NOT_NESTED; ++ nds32_isr_vectors[i].security_level = 0; + nds32_isr_vectors[i].total_n_vectors = 0; + strcpy (nds32_isr_vectors[i].nmi_name, ""); + strcpy (nds32_isr_vectors[i].warm_name, ""); + } + } + +-/* A helper function to handle isr stuff at the end of asm file. */ +-void +-nds32_asm_file_end_for_isr (void) ++void nds32_asm_file_end_for_isr (void) + { + int i; + +@@ -547,6 +902,8 @@ + /* Found one vector which is interupt or exception. + Output its jmptbl and vector section content. */ + fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i); ++ fprintf (asm_out_file, "\t! security level: %d\n", ++ nds32_isr_vectors[i].security_level); + fprintf (asm_out_file, "\t! ------------------------------------\n"); + nds32_emit_isr_jmptbl_section (i); + fprintf (asm_out_file, "\t! ....................................\n"); +@@ -580,4 +937,65 @@ + || (t_reset != NULL_TREE)); + } + +-/* ------------------------------------------------------------------------ */ ++/* Return true if FUNC is a isr function with critical attribute. */ ++bool ++nds32_isr_function_critical_p (tree func) ++{ ++ tree t_intr; ++ tree t_excp; ++ tree t_critical; ++ ++ tree attrs; ++ ++ if (TREE_CODE (func) != FUNCTION_DECL) ++ abort (); ++ ++ attrs = DECL_ATTRIBUTES (func); ++ ++ t_intr = lookup_attribute ("interrupt", attrs); ++ t_excp = lookup_attribute ("exception", attrs); ++ ++ t_critical = lookup_attribute ("critical", attrs); ++ ++ /* If both interrupt and exception attribute does not appear, ++ we can return false immediately. */ ++ if ((t_intr == NULL_TREE) && (t_excp == NULL_TREE)) ++ return false; ++ ++ /* Here we can guarantee either interrupt or ecxception attribute ++ does exist, so further check critical attribute. ++ If it also appears, we can return true. */ ++ if (t_critical != NULL_TREE) ++ return true; ++ ++ /* ------------------------------------------------------------- */ ++ /* FIXME: ++ FOR BACKWARD COMPATIBILITY, we need to handle string type. ++ If the string 'critical' appears in the interrupt/exception ++ string argument, we can return true. */ ++ if (t_intr != NULL_TREE || t_excp != NULL_TREE) ++ { ++ char target_str[100]; ++ char *critical_str; ++ tree t_check; ++ tree string_arg; ++ ++ t_check = t_intr ? t_intr : t_excp; ++ if (TREE_CODE (TREE_VALUE (TREE_VALUE (t_check))) == STRING_CST) ++ { ++ string_arg = TREE_VALUE (TREE_VALUE (t_check)); ++ strcpy (target_str, TREE_STRING_POINTER (string_arg)); ++ critical_str = strstr (target_str, "critical"); ++ ++ /* Found 'critical' string, so return true. */ ++ if (critical_str) ++ return true; ++ } ++ } ++ /* ------------------------------------------------------------- */ ++ ++ /* Other cases, this isr function is not critical type. */ ++ return false; ++} ++ ++/* ------------------------------------------------------------- */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32_isr.h gcc-8.2.0/gcc/config/nds32/nds32_isr.h +--- gcc-8.2.0.orig/gcc/config/nds32/nds32_isr.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32_isr.h 2019-01-25 15:38:32.833242671 +0100 +@@ -0,0 +1,526 @@ ++/* Intrinsic definitions of Andes NDS32 cpu for GNU compiler ++ Copyright (C) 2012-2018 Free Software Foundation, Inc. ++ Contributed by Andes Technology Corporation. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++#ifndef _NDS32_ISR_H ++#define _NDS32_ISR_H ++ ++/* Attribute of a interrupt or exception handler: ++ ++ NDS32_READY_NESTED: This handler is interruptible if user re-enable GIE bit. ++ NDS32_NESTED : This handler is interruptible. This is not suitable ++ exception handler. ++ NDS32_NOT_NESTED : This handler is NOT interruptible. Users have to do ++ some work if nested is wanted ++ NDS32_CRITICAL : This handler is critical ISR, which means it is small ++ and efficient. */ ++#define NDS32_READY_NESTED 0 ++#define NDS32_NESTED 1 ++#define NDS32_NOT_NESTED 2 ++#define NDS32_CRITICAL 3 ++ ++/* Attribute of a interrupt or exception handler: ++ ++ NDS32_SAVE_ALL_REGS : Save all registers in a table. ++ NDS32_SAVE_PARTIAL_REGS: Save partial registers. */ ++#define NDS32_SAVE_CALLER_REGS 0 ++#define NDS32_SAVE_ALL_REGS 1 ++ ++/* There are two version of Register table for interrupt and exception handler, ++ one for 16-register CPU the other for 32-register CPU. These structures are ++ used for context switching or system call handling. The address of this ++ data can be get from the input argument of the handler functions. ++ ++ For system call handling, r0 to r5 are used to pass arguments. If more ++ arguments are used they are put into the stack and its starting address is ++ in sp. Return value of system call can be put into r0 and r1 upon exit from ++ system call handler. System call ID is in a system register and it can be ++ fetched via intrinsic function. For more information please read ABI and ++ other related documents. ++ ++ For context switching, at least 2 values need to saved in kernel. One is ++ IPC and the other is the stack address of current task. Use intrinsic ++ function to get IPC and the input argument of the handler functions + 8 to ++ get stack address of current task. To do context switching, you replace ++ new_sp with the stack address of new task and replace IPC system register ++ with IPC of new task, then, just return from handler. The context switching ++ will happen. */ ++ ++/* Register table for exception handler; 32-register version. */ ++typedef struct ++{ ++ int r0; ++ int r1; ++ int r2; ++ int r3; ++ int r4; ++ int r5; ++ int r6; ++ int r7; ++ int r8; ++ int r9; ++ int r10; ++ int r11; ++ int r12; ++ int r13; ++ int r14; ++ int r15; ++ int r16; ++ int r17; ++ int r18; ++ int r19; ++ int r20; ++ int r21; ++ int r22; ++ int r23; ++ int r24; ++ int r25; ++ int r26; ++ int r27; ++ int fp; ++ int gp; ++ int lp; ++ int sp; ++} NDS32_GPR32; ++ ++/* Register table for exception handler; 16-register version. */ ++typedef struct ++{ ++ int r0; ++ int r1; ++ int r2; ++ int r3; ++ int r4; ++ int r5; ++ int r6; ++ int r7; ++ int r8; ++ int r9; ++ int r10; ++ int r15; ++ int fp; ++ int gp; ++ int lp; ++ int sp; ++} NDS32_GPR16; ++ ++ ++/* Use NDS32_REG32_TAB or NDS32_REG16_TAB in your program to ++ access register table. */ ++typedef struct ++{ ++ union ++ { ++ int reg_a[32] ; ++ NDS32_GPR32 reg_s ; ++ } u ; ++} NDS32_REG32_TAB; ++ ++typedef struct ++{ ++ union ++ { ++ int reg_a[16] ; ++ NDS32_GPR16 reg_s ; ++ } u ; ++} NDS32_REG16_TAB; ++ ++typedef struct ++{ ++ int d0lo; ++ int d0hi; ++ int d1lo; ++ int d1hi; ++} NDS32_DX_TAB; ++ ++typedef struct ++{ ++#ifdef __NDS32_EB__ ++ float fsr0; ++ float fsr1; ++ float fsr2; ++ float fsr3; ++ float fsr4; ++ float fsr5; ++ float fsr6; ++ float fsr7; ++#else ++ float fsr1; ++ float fsr0; ++ float fsr3; ++ float fsr2; ++ float fsr5; ++ float fsr4; ++ float fsr7; ++ float fsr6; ++#endif ++} NDS32_FSR8; ++ ++typedef struct ++{ ++ double dsr0; ++ double dsr1; ++ double dsr2; ++ double dsr3; ++} NDS32_DSR4; ++ ++typedef struct ++{ ++#ifdef __NDS32_EB__ ++ float fsr0; ++ float fsr1; ++ float fsr2; ++ float fsr3; ++ float fsr4; ++ float fsr5; ++ float fsr6; ++ float fsr7; ++ float fsr8; ++ float fsr9; ++ float fsr10; ++ float fsr11; ++ float fsr12; ++ float fsr13; ++ float fsr14; ++ float fsr15; ++#else ++ float fsr1; ++ float fsr0; ++ float fsr3; ++ float fsr2; ++ float fsr5; ++ float fsr4; ++ float fsr7; ++ float fsr6; ++ float fsr9; ++ float fsr8; ++ float fsr11; ++ float fsr10; ++ float fsr13; ++ float fsr12; ++ float fsr15; ++ float fsr14; ++#endif ++} NDS32_FSR16; ++ ++typedef struct ++{ ++ double dsr0; ++ double dsr1; ++ double dsr2; ++ double dsr3; ++ double dsr4; ++ double dsr5; ++ double dsr6; ++ double dsr7; ++} NDS32_DSR8; ++ ++typedef struct ++{ ++#ifdef __NDS32_EB__ ++ float fsr0; ++ float fsr1; ++ float fsr2; ++ float fsr3; ++ float fsr4; ++ float fsr5; ++ float fsr6; ++ float fsr7; ++ float fsr8; ++ float fsr9; ++ float fsr10; ++ float fsr11; ++ float fsr12; ++ float fsr13; ++ float fsr14; ++ float fsr15; ++ float fsr16; ++ float fsr17; ++ float fsr18; ++ float fsr19; ++ float fsr20; ++ float fsr21; ++ float fsr22; ++ float fsr23; ++ float fsr24; ++ float fsr25; ++ float fsr26; ++ float fsr27; ++ float fsr28; ++ float fsr29; ++ float fsr30; ++ float fsr31; ++#else ++ float fsr1; ++ float fsr0; ++ float fsr3; ++ float fsr2; ++ float fsr5; ++ float fsr4; ++ float fsr7; ++ float fsr6; ++ float fsr9; ++ float fsr8; ++ float fsr11; ++ float fsr10; ++ float fsr13; ++ float fsr12; ++ float fsr15; ++ float fsr14; ++ float fsr17; ++ float fsr16; ++ float fsr19; ++ float fsr18; ++ float fsr21; ++ float fsr20; ++ float fsr23; ++ float fsr22; ++ float fsr25; ++ float fsr24; ++ float fsr27; ++ float fsr26; ++ float fsr29; ++ float fsr28; ++ float fsr31; ++ float fsr30; ++#endif ++} NDS32_FSR32; ++ ++typedef struct ++{ ++ double dsr0; ++ double dsr1; ++ double dsr2; ++ double dsr3; ++ double dsr4; ++ double dsr5; ++ double dsr6; ++ double dsr7; ++ double dsr8; ++ double dsr9; ++ double dsr10; ++ double dsr11; ++ double dsr12; ++ double dsr13; ++ double dsr14; ++ double dsr15; ++} NDS32_DSR16; ++ ++typedef struct ++{ ++ double dsr0; ++ double dsr1; ++ double dsr2; ++ double dsr3; ++ double dsr4; ++ double dsr5; ++ double dsr6; ++ double dsr7; ++ double dsr8; ++ double dsr9; ++ double dsr10; ++ double dsr11; ++ double dsr12; ++ double dsr13; ++ double dsr14; ++ double dsr15; ++ double dsr16; ++ double dsr17; ++ double dsr18; ++ double dsr19; ++ double dsr20; ++ double dsr21; ++ double dsr22; ++ double dsr23; ++ double dsr24; ++ double dsr25; ++ double dsr26; ++ double dsr27; ++ double dsr28; ++ double dsr29; ++ double dsr30; ++ double dsr31; ++} NDS32_DSR32; ++ ++typedef struct ++{ ++ union ++ { ++ NDS32_FSR8 fsr_s ; ++ NDS32_DSR4 dsr_s ; ++ } u ; ++} NDS32_FPU8_TAB; ++ ++typedef struct ++{ ++ union ++ { ++ NDS32_FSR16 fsr_s ; ++ NDS32_DSR8 dsr_s ; ++ } u ; ++} NDS32_FPU16_TAB; ++ ++typedef struct ++{ ++ union ++ { ++ NDS32_FSR32 fsr_s ; ++ NDS32_DSR16 dsr_s ; ++ } u ; ++} NDS32_FPU32_TAB; ++ ++typedef struct ++{ ++ union ++ { ++ NDS32_FSR32 fsr_s ; ++ NDS32_DSR32 dsr_s ; ++ } u ; ++} NDS32_FPU64_TAB; ++ ++typedef struct ++{ ++ int ipc; ++ int ipsw; ++#if defined(NDS32_EXT_FPU_CONFIG_0) ++ NDS32_FPU8_TAB fpr; ++#elif defined(NDS32_EXT_FPU_CONFIG_1) ++ NDS32_FPU16_TAB fpr; ++#elif defined(NDS32_EXT_FPU_CONFIG_2) ++ NDS32_FPU32_TAB fpr; ++#elif defined(NDS32_EXT_FPU_CONFIG_3) ++ NDS32_FPU64_TAB fpr; ++#endif ++#if __NDS32_DX_REGS__ ++ NDS32_DX_TAB dxr; ++#endif ++#if __NDS32_EXT_IFC__ ++ int ifc_lp; ++ int filler; ++#endif ++#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS ++ NDS32_REG16_TAB gpr; ++#else ++ NDS32_REG32_TAB gpr; ++#endif ++} NDS32_CONTEXT; ++ ++/* Predefined Vector Definition. ++ ++ For IVIC Mode: 9 to 14 are for hardware interrupt ++ and 15 is for software interrupt. ++ For EVIC Mode: 9 to 72 are for hardware interrupt ++ and software interrupt can be routed to any one of them. ++ ++ You may want to define your hardware interrupts in the following way ++ for easy maintainance. ++ ++ IVIC mode: ++ #define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1 ++ #define MY_HW_IVIC_USB NDS32_VECTOR_INTERRUPT_HW0 + 3 ++ EVIC mode: ++ #define MY_HW_EVIC_DMA NDS32_VECTOR_INTERRUPT_HW0 + 2 ++ #define MY_HW_EVIC_SWI NDS32_VECTOR_INTERRUPT_HW0 + 10 */ ++#define NDS32_VECTOR_RESET 0 ++#define NDS32_VECTOR_TLB_FILL 1 ++#define NDS32_VECTOR_PTE_NOT_PRESENT 2 ++#define NDS32_VECTOR_TLB_MISC 3 ++#define NDS32_VECTOR_TLB_VLPT_MISS 4 ++#define NDS32_VECTOR_MACHINE_ERROR 5 ++#define NDS32_VECTOR_DEBUG_RELATED 6 ++#define NDS32_VECTOR_GENERAL_EXCEPTION 7 ++#define NDS32_VECTOR_SYSCALL 8 ++#define NDS32_VECTOR_INTERRUPT_HW0 9 ++#define NDS32_VECTOR_INTERRUPT_HW1 10 ++#define NDS32_VECTOR_INTERRUPT_HW2 11 ++#define NDS32_VECTOR_INTERRUPT_HW3 12 ++#define NDS32_VECTOR_INTERRUPT_HW4 13 ++#define NDS32_VECTOR_INTERRUPT_HW5 14 ++#define NDS32_VECTOR_INTERRUPT_HW6 15 ++#define NDS32_VECTOR_SWI 15 /* THIS IS FOR IVIC MODE ONLY */ ++#define NDS32_VECTOR_INTERRUPT_HW7 16 ++#define NDS32_VECTOR_INTERRUPT_HW8 17 ++#define NDS32_VECTOR_INTERRUPT_HW9 18 ++#define NDS32_VECTOR_INTERRUPT_HW10 19 ++#define NDS32_VECTOR_INTERRUPT_HW11 20 ++#define NDS32_VECTOR_INTERRUPT_HW12 21 ++#define NDS32_VECTOR_INTERRUPT_HW13 22 ++#define NDS32_VECTOR_INTERRUPT_HW14 23 ++#define NDS32_VECTOR_INTERRUPT_HW15 24 ++#define NDS32_VECTOR_INTERRUPT_HW16 25 ++#define NDS32_VECTOR_INTERRUPT_HW17 26 ++#define NDS32_VECTOR_INTERRUPT_HW18 27 ++#define NDS32_VECTOR_INTERRUPT_HW19 28 ++#define NDS32_VECTOR_INTERRUPT_HW20 29 ++#define NDS32_VECTOR_INTERRUPT_HW21 30 ++#define NDS32_VECTOR_INTERRUPT_HW22 31 ++#define NDS32_VECTOR_INTERRUPT_HW23 32 ++#define NDS32_VECTOR_INTERRUPT_HW24 33 ++#define NDS32_VECTOR_INTERRUPT_HW25 34 ++#define NDS32_VECTOR_INTERRUPT_HW26 35 ++#define NDS32_VECTOR_INTERRUPT_HW27 36 ++#define NDS32_VECTOR_INTERRUPT_HW28 37 ++#define NDS32_VECTOR_INTERRUPT_HW29 38 ++#define NDS32_VECTOR_INTERRUPT_HW30 39 ++#define NDS32_VECTOR_INTERRUPT_HW31 40 ++#define NDS32_VECTOR_INTERRUPT_HW32 41 ++#define NDS32_VECTOR_INTERRUPT_HW33 42 ++#define NDS32_VECTOR_INTERRUPT_HW34 43 ++#define NDS32_VECTOR_INTERRUPT_HW35 44 ++#define NDS32_VECTOR_INTERRUPT_HW36 45 ++#define NDS32_VECTOR_INTERRUPT_HW37 46 ++#define NDS32_VECTOR_INTERRUPT_HW38 47 ++#define NDS32_VECTOR_INTERRUPT_HW39 48 ++#define NDS32_VECTOR_INTERRUPT_HW40 49 ++#define NDS32_VECTOR_INTERRUPT_HW41 50 ++#define NDS32_VECTOR_INTERRUPT_HW42 51 ++#define NDS32_VECTOR_INTERRUPT_HW43 52 ++#define NDS32_VECTOR_INTERRUPT_HW44 53 ++#define NDS32_VECTOR_INTERRUPT_HW45 54 ++#define NDS32_VECTOR_INTERRUPT_HW46 55 ++#define NDS32_VECTOR_INTERRUPT_HW47 56 ++#define NDS32_VECTOR_INTERRUPT_HW48 57 ++#define NDS32_VECTOR_INTERRUPT_HW49 58 ++#define NDS32_VECTOR_INTERRUPT_HW50 59 ++#define NDS32_VECTOR_INTERRUPT_HW51 60 ++#define NDS32_VECTOR_INTERRUPT_HW52 61 ++#define NDS32_VECTOR_INTERRUPT_HW53 62 ++#define NDS32_VECTOR_INTERRUPT_HW54 63 ++#define NDS32_VECTOR_INTERRUPT_HW55 64 ++#define NDS32_VECTOR_INTERRUPT_HW56 65 ++#define NDS32_VECTOR_INTERRUPT_HW57 66 ++#define NDS32_VECTOR_INTERRUPT_HW58 67 ++#define NDS32_VECTOR_INTERRUPT_HW59 68 ++#define NDS32_VECTOR_INTERRUPT_HW60 69 ++#define NDS32_VECTOR_INTERRUPT_HW61 70 ++#define NDS32_VECTOR_INTERRUPT_HW62 71 ++#define NDS32_VECTOR_INTERRUPT_HW63 72 ++ ++#define NDS32ATTR_RESET(option) __attribute__((reset(option))) ++#define NDS32ATTR_EXCEPT(type) __attribute__((exception(type))) ++#define NDS32ATTR_EXCEPTION(type) __attribute__((exception(type))) ++#define NDS32ATTR_INTERRUPT(type) __attribute__((interrupt(type))) ++#define NDS32ATTR_ISR(type) __attribute__((interrupt(type))) ++ ++#endif /* nds32_isr.h */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-linux.opt gcc-8.2.0/gcc/config/nds32/nds32-linux.opt +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-linux.opt 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-linux.opt 2019-01-25 15:38:32.829242659 +0100 +@@ -0,0 +1,16 @@ ++mcmodel= ++Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_LARGE) ++Specify the address generation strategy for code model. ++ ++Enum ++Name(nds32_cmodel_type) Type(enum nds32_cmodel_type) ++Known cmodel types (for use with the -mcmodel= option): ++ ++EnumValue ++Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL) ++ ++EnumValue ++Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM) ++ ++EnumValue ++Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.md gcc-8.2.0/gcc/config/nds32/nds32.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32.md 2018-04-08 11:21:30.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32.md 2019-01-25 15:38:32.833242671 +0100 +@@ -56,24 +56,29 @@ + ;; ------------------------------------------------------------------------ + + ;; CPU pipeline model. +-(define_attr "pipeline_model" "n7,n8,e8,n9,simple" ++(define_attr "pipeline_model" "n7,n8,e8,n9,n10,graywolf,n13,simple" + (const + (cond [(match_test "nds32_cpu_option == CPU_N7") (const_string "n7") + (match_test "nds32_cpu_option == CPU_E8") (const_string "e8") + (match_test "nds32_cpu_option == CPU_N6 || nds32_cpu_option == CPU_N8") (const_string "n8") + (match_test "nds32_cpu_option == CPU_N9") (const_string "n9") ++ (match_test "nds32_cpu_option == CPU_N10") (const_string "n10") ++ (match_test "nds32_cpu_option == CPU_GRAYWOLF") (const_string "graywolf") ++ (match_test "nds32_cpu_option == CPU_N12") (const_string "n13") ++ (match_test "nds32_cpu_option == CPU_N13") (const_string "n13") + (match_test "nds32_cpu_option == CPU_SIMPLE") (const_string "simple")] + (const_string "n9")))) + + ;; Insn type, it is used to default other attribute values. + (define_attr "type" + "unknown,load,store,load_multiple,store_multiple,alu,alu_shift,pbsad,pbsada,mul,mac,div,branch,mmu,misc,\ +- falu,fmuls,fmuld,fmacs,fmacd,fdivs,fdivd,fsqrts,fsqrtd,fcmp,fabs,fcpy,fcmov,fmfsr,fmfdr,fmtsr,fmtdr,fload,fstore" ++ falu,fmuls,fmuld,fmacs,fmacd,fdivs,fdivd,fsqrts,fsqrtd,fcmp,fabs,fcpy,fcmov,fmfsr,fmfdr,fmtsr,fmtdr,fload,fstore,\ ++ dalu,dalu64,daluround,dcmp,dclip,dmul,dmac,dinsb,dpack,dbpick,dwext" + (const_string "unknown")) + + ;; Insn sub-type + (define_attr "subtype" +- "simple,shift" ++ "simple,shift,saturation" + (const_string "simple")) + + ;; Length, in bytes, default is 4-bytes. +@@ -133,6 +138,7 @@ + + ;; ---------------------------------------------------------------------------- + ++(include "nds32-dspext.md") + + ;; Move instructions. + +@@ -209,6 +215,27 @@ + low12_int)); + DONE; + } ++ ++ if ((REG_P (operands[0]) || GET_CODE (operands[0]) == SUBREG) ++ && SYMBOLIC_CONST_P (operands[1])) ++ { ++ if (TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (operands[1])) ++ { ++ nds32_expand_ict_move (operands); ++ DONE; ++ } ++ else if (nds32_tls_referenced_p (operands [1])) ++ { ++ nds32_expand_tls_move (operands); ++ DONE; ++ } ++ else if (flag_pic) ++ { ++ nds32_expand_pic_move (operands); ++ DONE; ++ } ++ } + }) + + (define_insn "*mov" +@@ -271,8 +298,8 @@ + ;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF + ;; are able to match such instruction template. + (define_insn "move_addr" +- [(set (match_operand:SI 0 "register_operand" "=l, r") +- (match_operand:SI 1 "nds32_symbolic_operand" " i, i"))] ++ [(set (match_operand:SI 0 "nds32_general_register_operand" "=l, r") ++ (match_operand:SI 1 "nds32_nonunspec_symbolic_operand" " i, i"))] + "" + "la\t%0, %1" + [(set_attr "type" "alu") +@@ -351,13 +378,58 @@ + + + ;; ---------------------------------------------------------------------------- ++(define_expand "extv" ++ [(set (match_operand 0 "register_operand" "") ++ (sign_extract (match_operand 1 "nonimmediate_operand" "") ++ (match_operand 2 "const_int_operand" "") ++ (match_operand 3 "const_int_operand" "")))] ++ "" ++{ ++ enum nds32_expand_result_type result = nds32_expand_extv (operands); ++ switch (result) ++ { ++ case EXPAND_DONE: ++ DONE; ++ break; ++ case EXPAND_FAIL: ++ FAIL; ++ break; ++ case EXPAND_CREATE_TEMPLATE: ++ break; ++ default: ++ gcc_unreachable (); ++ } ++}) ++ ++(define_expand "insv" ++ [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") ++ (match_operand 1 "const_int_operand" "") ++ (match_operand 2 "const_int_operand" "")) ++ (match_operand 3 "register_operand" ""))] ++ "" ++{ ++ enum nds32_expand_result_type result = nds32_expand_insv (operands); ++ switch (result) ++ { ++ case EXPAND_DONE: ++ DONE; ++ break; ++ case EXPAND_FAIL: ++ FAIL; ++ break; ++ case EXPAND_CREATE_TEMPLATE: ++ break; ++ default: ++ gcc_unreachable (); ++ } ++}) + + ;; Arithmetic instructions. + + (define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") + (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") +- (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,Iu06, Is15, r")))] ++ (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,IU06, Is15, r")))] + "" + { + switch (which_alternative) +@@ -1428,11 +1500,30 @@ + (clobber (reg:SI LP_REGNUM)) + (clobber (reg:SI TA_REGNUM))])] + "" +- "" ++ { ++ rtx insn; ++ rtx sym = XEXP (operands[0], 0); ++ ++ if (TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (sym)) ++ { ++ rtx reg = gen_reg_rtx (Pmode); ++ emit_move_insn (reg, sym); ++ operands[0] = gen_const_mem (Pmode, reg); ++ } ++ ++ if (flag_pic) ++ { ++ insn = emit_call_insn (gen_call_internal ++ (XEXP (operands[0], 0), GEN_INT (0))); ++ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); ++ DONE; ++ } ++ } + ) + + (define_insn "call_internal" +- [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i")) ++ [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, S")) + (match_operand 1)) + (clobber (reg:SI LP_REGNUM)) + (clobber (reg:SI TA_REGNUM))])] +@@ -1474,9 +1565,11 @@ + (const_int 2) + (const_int 4)) + ;; Alternative 1 +- (if_then_else (match_test "nds32_long_call_p (operands[0])") +- (const_int 12) +- (const_int 4)) ++ (if_then_else (match_test "flag_pic") ++ (const_int 16) ++ (if_then_else (match_test "nds32_long_call_p (operands[0])") ++ (const_int 12) ++ (const_int 4))) + ])] + ) + +@@ -1492,11 +1585,33 @@ + (match_operand 2))) + (clobber (reg:SI LP_REGNUM)) + (clobber (reg:SI TA_REGNUM))])] +- "") ++ "" ++ { ++ rtx insn; ++ rtx sym = XEXP (operands[1], 0); ++ ++ if (TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (sym)) ++ { ++ rtx reg = gen_reg_rtx (Pmode); ++ emit_move_insn (reg, sym); ++ operands[1] = gen_const_mem (Pmode, reg); ++ } ++ ++ if (flag_pic) ++ { ++ insn = ++ emit_call_insn (gen_call_value_internal ++ (operands[0], XEXP (operands[1], 0), GEN_INT (0))); ++ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); ++ DONE; ++ } ++ } ++) + + (define_insn "call_value_internal" + [(parallel [(set (match_operand 0) +- (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i")) ++ (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, S")) + (match_operand 2))) + (clobber (reg:SI LP_REGNUM)) + (clobber (reg:SI TA_REGNUM))])] +@@ -1538,9 +1653,11 @@ + (const_int 2) + (const_int 4)) + ;; Alternative 1 +- (if_then_else (match_test "nds32_long_call_p (operands[1])") +- (const_int 12) +- (const_int 4)) ++ (if_then_else (match_test "flag_pic") ++ (const_int 16) ++ (if_then_else (match_test "nds32_long_call_p (operands[1])") ++ (const_int 12) ++ (const_int 4))) + ])] + ) + +@@ -1583,10 +1700,21 @@ + (const_int 0)) + (clobber (reg:SI TA_REGNUM)) + (return)])] +- "") ++ "" ++{ ++ rtx sym = XEXP (operands[0], 0); ++ ++ if (TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (sym)) ++ { ++ rtx reg = gen_reg_rtx (Pmode); ++ emit_move_insn (reg, sym); ++ operands[0] = gen_const_mem (Pmode, reg); ++ } ++}) + + (define_insn "sibcall_internal" +- [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i")) ++ [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, S")) + (match_operand 1)) + (clobber (reg:SI TA_REGNUM)) + (return)])] +@@ -1617,9 +1745,11 @@ + (const_int 2) + (const_int 4)) + ;; Alternative 1 +- (if_then_else (match_test "nds32_long_call_p (operands[0])") +- (const_int 12) +- (const_int 4)) ++ (if_then_else (match_test "flag_pic") ++ (const_int 16) ++ (if_then_else (match_test "nds32_long_call_p (operands[0])") ++ (const_int 12) ++ (const_int 4))) + ])] + ) + +@@ -1633,11 +1763,22 @@ + (const_int 0))) + (clobber (reg:SI TA_REGNUM)) + (return)])] +- "") ++ "" ++{ ++ rtx sym = XEXP (operands[1], 0); ++ ++ if (TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (sym)) ++ { ++ rtx reg = gen_reg_rtx (Pmode); ++ emit_move_insn (reg, sym); ++ operands[1] = gen_const_mem (Pmode, reg); ++ } ++}) + + (define_insn "sibcall_value_internal" + [(parallel [(set (match_operand 0) +- (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i")) ++ (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, S")) + (match_operand 2))) + (clobber (reg:SI TA_REGNUM)) + (return)])] +@@ -1668,9 +1809,11 @@ + (const_int 2) + (const_int 4)) + ;; Alternative 1 +- (if_then_else (match_test "nds32_long_call_p (operands[1])") +- (const_int 12) +- (const_int 4)) ++ (if_then_else (match_test "flag_pic") ++ (const_int 16) ++ (if_then_else (match_test "nds32_long_call_p (operands[1])") ++ (const_int 12) ++ (const_int 4))) + ])] + ) + +@@ -1687,12 +1830,33 @@ + nds32_expand_prologue_v3push (); + else + nds32_expand_prologue (); ++ ++ /* If cfun->machine->fp_as_gp_p is true, we can generate special ++ directive to guide linker doing fp-as-gp optimization. ++ However, for a naked function, which means ++ it should not have prologue/epilogue, ++ using fp-as-gp still requires saving $fp by push/pop behavior and ++ there is no benefit to use fp-as-gp on such small function. ++ So we need to make sure this function is NOT naked as well. */ ++ if (cfun->machine->fp_as_gp_p && !cfun->machine->naked_p) ++ emit_insn (gen_omit_fp_begin (gen_rtx_REG (SImode, FP_REGNUM))); ++ + DONE; + }) + + (define_expand "epilogue" [(const_int 0)] + "" + { ++ /* If cfun->machine->fp_as_gp_p is true, we can generate special ++ directive to guide linker doing fp-as-gp optimization. ++ However, for a naked function, which means ++ it should not have prologue/epilogue, ++ using fp-as-gp still requires saving $fp by push/pop behavior and ++ there is no benefit to use fp-as-gp on such small function. ++ So we need to make sure this function is NOT naked as well. */ ++ if (cfun->machine->fp_as_gp_p && !cfun->machine->naked_p) ++ emit_insn (gen_omit_fp_end (gen_rtx_REG (SImode, FP_REGNUM))); ++ + /* Note that only under V3/V3M ISA, we could use v3pop epilogue. + In addition, we need to check if v3push is indeed available. */ + if (NDS32_V3PUSH_AVAILABLE_P) +@@ -1792,7 +1956,8 @@ + "nds32_can_use_return_insn ()" + { + /* Emit as the simple return. */ +- if (cfun->machine->naked_p ++ if (!cfun->machine->fp_as_gp_p ++ && cfun->machine->naked_p + && (cfun->machine->va_args_size == 0)) + { + emit_jump_insn (gen_return_internal ()); +@@ -1802,9 +1967,14 @@ + + ;; This pattern is expanded only by the shrink-wrapping optimization + ;; on paths where the function prologue has not been executed. ++;; However, such optimization may reorder the prologue/epilogue blocks ++;; together with basic blocks within function body. ++;; So we must disable this pattern if we have already decided ++;; to perform fp_as_gp optimization, which requires prologue to be ++;; first block and epilogue to be last block. + (define_expand "simple_return" + [(simple_return)] +- "" ++ "!cfun->machine->fp_as_gp_p" + "" + ) + +@@ -1823,6 +1993,9 @@ + [(simple_return)] + "" + { ++ if (nds32_isr_function_critical_p (current_function_decl)) ++ return "iret"; ++ + if (TARGET_16_BIT) + return "ret5"; + else +@@ -1831,9 +2004,11 @@ + [(set_attr "type" "branch") + (set_attr "enabled" "yes") + (set (attr "length") +- (if_then_else (match_test "TARGET_16_BIT") +- (const_int 2) +- (const_int 4)))]) ++ (if_then_else (match_test "nds32_isr_function_critical_p (current_function_decl)") ++ (const_int 4) ++ (if_then_else (match_test "TARGET_16_BIT") ++ (const_int 2) ++ (const_int 4))))]) + + + ;; ---------------------------------------------------------------------------- +@@ -1868,6 +2043,7 @@ + { + rtx add_tmp; + rtx reg, test; ++ rtx tmp_reg; + + /* Step A: "k <-- (plus (operands[0]) (-operands[1]))". */ + if (operands[1] != const0_rtx) +@@ -1889,9 +2065,14 @@ + emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], + operands[4])); + +- /* Step C, D, E, and F, using another temporary register. */ +- rtx tmp = gen_reg_rtx (SImode); +- emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp)); ++ tmp_reg = gen_reg_rtx (SImode); ++ /* Step C, D, E, and F, using another temporary register tmp_reg. */ ++ if (flag_pic) ++ emit_use (pic_offset_table_rtx); ++ ++ emit_jump_insn (gen_casesi_internal (operands[0], ++ operands[3], ++ tmp_reg)); + DONE; + }) + +@@ -1927,13 +2108,30 @@ + else + return nds32_output_casesi (operands); + } +- [(set_attr "length" "20") +- (set_attr "type" "branch")]) ++ [(set_attr "type" "branch") ++ (set (attr "length") ++ (if_then_else (match_test "flag_pic") ++ (const_int 28) ++ (const_int 20)))]) + + ;; ---------------------------------------------------------------------------- + + ;; Performance Extension + ++; If -fwrapv option is issued, GCC expects there will be ++; signed overflow situation. So the ABS(INT_MIN) is still INT_MIN ++; (e.g. ABS(0x80000000)=0x80000000). ++; However, the hardware ABS instruction of nds32 target ++; always performs saturation: abs 0x80000000 -> 0x7fffffff. ++; So that we can only enable abssi2 pattern if flag_wrapv is NOT presented. ++(define_insn "abssi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (abs:SI (match_operand:SI 1 "register_operand" " r")))] ++ "TARGET_EXT_PERF && TARGET_HW_ABS && !flag_wrapv" ++ "abs\t%0, %1" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")]) ++ + (define_insn "clzsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (clz:SI (match_operand:SI 1 "register_operand" " r")))] +@@ -1996,6 +2194,25 @@ + [(set_attr "length" "0")] + ) + ++;; Output .omit_fp_begin for fp-as-gp optimization. ++;; Also we have to set $fp register. ++(define_insn "omit_fp_begin" ++ [(set (match_operand:SI 0 "register_operand" "=x") ++ (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_OMIT_FP_BEGIN))] ++ "" ++ "! -----\;.omit_fp_begin\;la\t$fp,_FP_BASE_\;! -----" ++ [(set_attr "length" "8")] ++) ++ ++;; Output .omit_fp_end for fp-as-gp optimization. ++;; Claim that we have to use $fp register. ++(define_insn "omit_fp_end" ++ [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "x")] UNSPEC_VOLATILE_OMIT_FP_END)] ++ "" ++ "! -----\;.omit_fp_end\;! -----" ++ [(set_attr "length" "0")] ++) ++ + (define_insn "pop25return" + [(return) + (unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_POP25_RETURN)] +@@ -2004,6 +2221,36 @@ + [(set_attr "length" "0")] + ) + ++;; Add pc ++(define_insn "add_pc" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_operand:SI 1 "register_operand" "0") ++ (pc)))] ++ "TARGET_LINUX_ABI || flag_pic" ++ "add5.pc\t%0" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ ++(define_expand "bswapsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (bswap:SI (match_operand:SI 1 "register_operand" "r")))] ++ "" ++{ ++ emit_insn (gen_unspec_wsbh (operands[0], operands[1])); ++ emit_insn (gen_rotrsi3 (operands[0], operands[0], GEN_INT (16))); ++ DONE; ++}) ++ ++(define_insn "bswaphi2" ++ [(set (match_operand:HI 0 "register_operand" "=r") ++ (bswap:HI (match_operand:HI 1 "register_operand" "r")))] ++ "" ++ "wsbh\t%0, %1" ++ [(set_attr "type" "alu") ++ (set_attr "length" "4")] ++) ++ + ;; ---------------------------------------------------------------------------- + + ;; Patterns for exception handling +@@ -2068,3 +2315,57 @@ + }) + + ;; ---------------------------------------------------------------------------- ++ ++;; Patterns for TLS. ++;; The following two tls patterns don't be expanded directly because the ++;; intermediate value may be spilled into the stack. As a result, it is ++;; hard to analyze the define-use chain in the relax_opt pass. ++ ++ ++;; There is a unspec operand to record RELAX_GROUP number because each ++;; emitted instruction need a relax_hint above it. ++(define_insn "tls_desc" ++ [(set (reg:SI 0) ++ (call (unspec_volatile:SI [(match_operand:SI 0 "nds32_symbolic_operand" "i")] UNSPEC_TLS_DESC) ++ (const_int 1))) ++ (use (unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)) ++ (use (reg:SI GP_REGNUM)) ++ (clobber (reg:SI LP_REGNUM)) ++ (clobber (reg:SI TA_REGNUM))] ++ "" ++ { ++ return nds32_output_tls_desc (operands); ++ } ++ [(set_attr "length" "20") ++ (set_attr "type" "branch")] ++) ++ ++;; There is a unspec operand to record RELAX_GROUP number because each ++;; emitted instruction need a relax_hint above it. ++(define_insn "tls_ie" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "nds32_symbolic_operand" "i")] UNSPEC_TLS_IE)) ++ (use (unspec [(match_operand:SI 2 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)) ++ (use (reg:SI GP_REGNUM))] ++ "" ++ { ++ return nds32_output_tls_ie (operands); ++ } ++ [(set (attr "length") (if_then_else (match_test "flag_pic") ++ (const_int 12) ++ (const_int 8))) ++ (set_attr "type" "misc")] ++) ++ ++;; The pattern is for some relaxation groups that have to keep addsi3 in 32-bit mode. ++(define_insn "addsi3_32bit" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "%r") ++ (match_operand:SI 2 "register_operand" " r")] UNSPEC_ADD32))] ++ "" ++ "add\t%0, %1, %2"; ++ [(set_attr "type" "alu") ++ (set_attr "length" "4") ++ (set_attr "feature" "v1")]) ++ ++;; ---------------------------------------------------------------------------- +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-md-auxiliary.c gcc-8.2.0/gcc/config/nds32/nds32-md-auxiliary.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-md-auxiliary.c 2018-04-08 08:00:34.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-md-auxiliary.c 2019-01-25 15:38:32.829242659 +0100 +@@ -39,6 +39,9 @@ + #include "expr.h" + #include "emit-rtl.h" + #include "explow.h" ++#include "stringpool.h" ++#include "attribs.h" ++ + + /* ------------------------------------------------------------------------ */ + +@@ -261,6 +264,118 @@ + output_asm_insn (pattern, operands); + } + ++static void ++nds32_split_shiftrtdi3 (rtx dst, rtx src, rtx shiftamount, bool logic_shift_p) ++{ ++ rtx src_high_part; ++ rtx dst_high_part, dst_low_part; ++ ++ dst_high_part = nds32_di_high_part_subreg (dst); ++ src_high_part = nds32_di_high_part_subreg (src); ++ dst_low_part = nds32_di_low_part_subreg (dst); ++ ++ if (CONST_INT_P (shiftamount)) ++ { ++ if (INTVAL (shiftamount) < 32) ++ { ++ if (logic_shift_p) ++ { ++ emit_insn (gen_uwext (dst_low_part, src, ++ shiftamount)); ++ emit_insn (gen_lshrsi3 (dst_high_part, src_high_part, ++ shiftamount)); ++ } ++ else ++ { ++ emit_insn (gen_wext (dst_low_part, src, ++ shiftamount)); ++ emit_insn (gen_ashrsi3 (dst_high_part, src_high_part, ++ shiftamount)); ++ } ++ } ++ else ++ { ++ rtx new_shift_amout = gen_int_mode(INTVAL (shiftamount) - 32, SImode); ++ ++ if (logic_shift_p) ++ { ++ emit_insn (gen_lshrsi3 (dst_low_part, src_high_part, ++ new_shift_amout)); ++ emit_move_insn (dst_high_part, const0_rtx); ++ } ++ else ++ { ++ emit_insn (gen_ashrsi3 (dst_low_part, src_high_part, ++ new_shift_amout)); ++ emit_insn (gen_ashrsi3 (dst_high_part, src_high_part, ++ GEN_INT (31))); ++ } ++ } ++ } ++ else ++ { ++ rtx dst_low_part_l32, dst_high_part_l32; ++ rtx dst_low_part_g32, dst_high_part_g32; ++ rtx new_shift_amout, select_reg; ++ dst_low_part_l32 = gen_reg_rtx (SImode); ++ dst_high_part_l32 = gen_reg_rtx (SImode); ++ dst_low_part_g32 = gen_reg_rtx (SImode); ++ dst_high_part_g32 = gen_reg_rtx (SImode); ++ new_shift_amout = gen_reg_rtx (SImode); ++ select_reg = gen_reg_rtx (SImode); ++ ++ emit_insn (gen_andsi3 (shiftamount, shiftamount, GEN_INT (0x3f))); ++ ++ if (logic_shift_p) ++ { ++ /* ++ if (shiftamount < 32) ++ dst_low_part = wext (src, shiftamount) ++ dst_high_part = src_high_part >> shiftamount ++ else ++ dst_low_part = src_high_part >> (shiftamount & 0x1f) ++ dst_high_part = 0 ++ */ ++ emit_insn (gen_uwext (dst_low_part_l32, src, shiftamount)); ++ emit_insn (gen_lshrsi3 (dst_high_part_l32, src_high_part, ++ shiftamount)); ++ ++ emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f))); ++ emit_insn (gen_lshrsi3 (dst_low_part_g32, src_high_part, ++ new_shift_amout)); ++ emit_move_insn (dst_high_part_g32, const0_rtx); ++ } ++ else ++ { ++ /* ++ if (shiftamount < 32) ++ dst_low_part = wext (src, shiftamount) ++ dst_high_part = src_high_part >> shiftamount ++ else ++ dst_low_part = src_high_part >> (shiftamount & 0x1f) ++ # shift 31 for sign extend ++ dst_high_part = src_high_part >> 31 ++ */ ++ emit_insn (gen_wext (dst_low_part_l32, src, shiftamount)); ++ emit_insn (gen_ashrsi3 (dst_high_part_l32, src_high_part, ++ shiftamount)); ++ ++ emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f))); ++ emit_insn (gen_ashrsi3 (dst_low_part_g32, src_high_part, ++ new_shift_amout)); ++ emit_insn (gen_ashrsi3 (dst_high_part_g32, src_high_part, ++ GEN_INT (31))); ++ } ++ ++ emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32))); ++ ++ emit_insn (gen_cmovnsi (dst_low_part, select_reg, ++ dst_low_part_l32, dst_low_part_g32)); ++ emit_insn (gen_cmovnsi (dst_high_part, select_reg, ++ dst_high_part_l32, dst_high_part_g32)); ++ } ++} ++ + /* ------------------------------------------------------------------------ */ + + /* Auxiliary function for expand RTL pattern. */ +@@ -1195,8 +1310,166 @@ + } + } + ++enum nds32_expand_result_type ++nds32_expand_extv (rtx *operands) ++{ ++ gcc_assert (CONST_INT_P (operands[2]) && CONST_INT_P (operands[3])); ++ HOST_WIDE_INT width = INTVAL (operands[2]); ++ HOST_WIDE_INT bitpos = INTVAL (operands[3]); ++ rtx dst = operands[0]; ++ rtx src = operands[1]; ++ ++ if (MEM_P (src) ++ && width == 32 ++ && (bitpos % BITS_PER_UNIT) == 0 ++ && GET_MODE_BITSIZE (GET_MODE (dst)) == width) ++ { ++ rtx newmem = adjust_address (src, GET_MODE (dst), ++ bitpos / BITS_PER_UNIT); ++ ++ rtx base_addr = force_reg (Pmode, XEXP (newmem, 0)); ++ ++ emit_insn (gen_unaligned_loadsi (dst, base_addr)); ++ ++ return EXPAND_DONE; ++ } ++ return EXPAND_FAIL; ++} ++ ++enum nds32_expand_result_type ++nds32_expand_insv (rtx *operands) ++{ ++ gcc_assert (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2])); ++ HOST_WIDE_INT width = INTVAL (operands[1]); ++ HOST_WIDE_INT bitpos = INTVAL (operands[2]); ++ rtx dst = operands[0]; ++ rtx src = operands[3]; ++ ++ if (MEM_P (dst) ++ && width == 32 ++ && (bitpos % BITS_PER_UNIT) == 0 ++ && GET_MODE_BITSIZE (GET_MODE (src)) == width) ++ { ++ rtx newmem = adjust_address (dst, GET_MODE (src), ++ bitpos / BITS_PER_UNIT); ++ ++ rtx base_addr = force_reg (Pmode, XEXP (newmem, 0)); ++ ++ emit_insn (gen_unaligned_storesi (base_addr, src)); ++ ++ return EXPAND_DONE; ++ } ++ return EXPAND_FAIL; ++} ++ + /* ------------------------------------------------------------------------ */ + ++/* Function to generate PC relative jump table. ++ Refer to nds32.md for more details. ++ ++ The following is the sample for the case that diff value ++ can be presented in '.short' size. ++ ++ addi $r1, $r1, -(case_lower_bound) ++ slti $ta, $r1, (case_number) ++ beqz $ta, .L_skip_label ++ ++ la $ta, .L35 ! get jump table address ++ lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry ++ addi $ta, $r1, $ta ++ jr5 $ta ++ ++ ! jump table entry ++ L35: ++ .short .L25-.L35 ++ .short .L26-.L35 ++ .short .L27-.L35 ++ .short .L28-.L35 ++ .short .L29-.L35 ++ .short .L30-.L35 ++ .short .L31-.L35 ++ .short .L32-.L35 ++ .short .L33-.L35 ++ .short .L34-.L35 */ ++const char * ++nds32_output_casesi_pc_relative (rtx *operands) ++{ ++ machine_mode mode; ++ rtx diff_vec; ++ ++ diff_vec = PATTERN (NEXT_INSN (as_a (operands[1]))); ++ ++ gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); ++ ++ /* Step C: "t <-- operands[1]". */ ++ if (flag_pic) ++ { ++ output_asm_insn ("sethi\t$ta, hi20(%l1@GOTOFF)", operands); ++ output_asm_insn ("ori\t$ta, $ta, lo12(%l1@GOTOFF)", operands); ++ output_asm_insn ("add\t$ta, $ta, $gp", operands); ++ } ++ else ++ output_asm_insn ("la\t$ta, %l1", operands); ++ ++ /* Get the mode of each element in the difference vector. */ ++ mode = GET_MODE (diff_vec); ++ ++ /* Step D: "z <-- (mem (plus (operands[0] << m) t))", ++ where m is 0, 1, or 2 to load address-diff value from table. */ ++ switch (mode) ++ { ++ case E_QImode: ++ output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands); ++ break; ++ case E_HImode: ++ output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands); ++ break; ++ case E_SImode: ++ output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ /* Step E: "t <-- z + t". ++ Add table label_ref with address-diff value to ++ obtain target case address. */ ++ output_asm_insn ("add\t$ta, %2, $ta", operands); ++ ++ /* Step F: jump to target with register t. */ ++ if (TARGET_16_BIT) ++ return "jr5\t$ta"; ++ else ++ return "jr\t$ta"; ++} ++ ++/* Function to generate normal jump table. */ ++const char * ++nds32_output_casesi (rtx *operands) ++{ ++ /* Step C: "t <-- operands[1]". */ ++ if (flag_pic) ++ { ++ output_asm_insn ("sethi\t$ta, hi20(%l1@GOTOFF)", operands); ++ output_asm_insn ("ori\t$ta, $ta, lo12(%l1@GOTOFF)", operands); ++ output_asm_insn ("add\t$ta, $ta, $gp", operands); ++ } ++ else ++ output_asm_insn ("la\t$ta, %l1", operands); ++ ++ /* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */ ++ output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); ++ ++ /* No need to perform Step E, which is only used for ++ pc relative jump table. */ ++ ++ /* Step F: jump to target with register z. */ ++ if (TARGET_16_BIT) ++ return "jr5\t%2"; ++ else ++ return "jr\t%2"; ++} ++ + /* Function to return memory format. */ + enum nds32_16bit_address_type + nds32_mem_format (rtx op) +@@ -1757,11 +2030,8 @@ + + /* If we step here, we are going to do v3push or multiple push operation. */ + +- /* The v3push/v3pop instruction should only be applied on +- none-isr and none-variadic function. */ +- if (TARGET_V3PUSH +- && !nds32_isr_function_p (current_function_decl) +- && (cfun->machine->va_args_size == 0)) ++ /* Refer to nds32.h, where we comment when push25/pop25 are available. */ ++ if (NDS32_V3PUSH_AVAILABLE_P) + { + /* For stack v3push: + operands[0]: Re +@@ -1881,11 +2151,8 @@ + + /* If we step here, we are going to do v3pop or multiple pop operation. */ + +- /* The v3push/v3pop instruction should only be applied on +- none-isr and none-variadic function. */ +- if (TARGET_V3PUSH +- && !nds32_isr_function_p (current_function_decl) +- && (cfun->machine->va_args_size == 0)) ++ /* Refer to nds32.h, where we comment when push25/pop25 are available. */ ++ if (NDS32_V3PUSH_AVAILABLE_P) + { + /* For stack v3pop: + operands[0]: Re +@@ -2022,77 +2289,6 @@ + return ""; + } + +-/* Function to generate PC relative jump table. +- Refer to nds32.md for more details. +- +- The following is the sample for the case that diff value +- can be presented in '.short' size. +- +- addi $r1, $r1, -(case_lower_bound) +- slti $ta, $r1, (case_number) +- beqz $ta, .L_skip_label +- +- la $ta, .L35 ! get jump table address +- lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry +- addi $ta, $r1, $ta +- jr5 $ta +- +- ! jump table entry +- L35: +- .short .L25-.L35 +- .short .L26-.L35 +- .short .L27-.L35 +- .short .L28-.L35 +- .short .L29-.L35 +- .short .L30-.L35 +- .short .L31-.L35 +- .short .L32-.L35 +- .short .L33-.L35 +- .short .L34-.L35 */ +-const char * +-nds32_output_casesi_pc_relative (rtx *operands) +-{ +- machine_mode mode; +- rtx diff_vec; +- +- diff_vec = PATTERN (NEXT_INSN (as_a (operands[1]))); +- +- gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); +- +- /* Step C: "t <-- operands[1]". */ +- output_asm_insn ("la\t$ta, %l1", operands); +- +- /* Get the mode of each element in the difference vector. */ +- mode = GET_MODE (diff_vec); +- +- /* Step D: "z <-- (mem (plus (operands[0] << m) t))", +- where m is 0, 1, or 2 to load address-diff value from table. */ +- switch (mode) +- { +- case E_QImode: +- output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands); +- break; +- case E_HImode: +- output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands); +- break; +- case E_SImode: +- output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); +- break; +- default: +- gcc_unreachable (); +- } +- +- /* Step E: "t <-- z + t". +- Add table label_ref with address-diff value to +- obtain target case address. */ +- output_asm_insn ("add\t$ta, %2, $ta", operands); +- +- /* Step F: jump to target with register t. */ +- if (TARGET_16_BIT) +- return "jr5\t$ta"; +- else +- return "jr\t$ta"; +-} + + /* output a float load instruction */ + const char * +@@ -2250,52 +2446,51 @@ + return ""; + } + +-/* Function to generate normal jump table. */ + const char * +-nds32_output_casesi (rtx *operands) ++nds32_output_smw_single_word (rtx *operands) + { +- /* Step C: "t <-- operands[1]". */ +- output_asm_insn ("la\t$ta, %l1", operands); +- +- /* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */ +- output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands); +- +- /* No need to perform Step E, which is only used for +- pc relative jump table. */ ++ char buff[100]; ++ unsigned regno; ++ int enable4; ++ bool update_base_p; ++ rtx base_addr = operands[0]; ++ rtx base_reg; ++ rtx otherops[2]; + +- /* Step F: jump to target with register z. */ +- if (TARGET_16_BIT) +- return "jr5\t%2"; ++ if (REG_P (XEXP (base_addr, 0))) ++ { ++ update_base_p = false; ++ base_reg = XEXP (base_addr, 0); ++ } + else +- return "jr\t%2"; +-} ++ { ++ update_base_p = true; ++ base_reg = XEXP (XEXP (base_addr, 0), 0); ++ } + +-/* Auxiliary functions for lwm/smw. */ +-bool +-nds32_valid_smw_lwm_base_p (rtx op) +-{ +- rtx base_addr; ++ const char *update_base = update_base_p ? "m" : ""; + +- if (!MEM_P (op)) +- return false; ++ regno = REGNO (operands[1]); + +- base_addr = XEXP (op, 0); ++ otherops[0] = base_reg; ++ otherops[1] = operands[1]; + +- if (REG_P (base_addr)) +- return true; ++ if (regno >= 28) ++ { ++ enable4 = nds32_regno_to_enable4 (regno); ++ sprintf (buff, "smw.bi%s\t$sp, [%%0], $sp, %x", update_base, enable4); ++ } + else + { +- if (GET_CODE (base_addr) == POST_INC +- && REG_P (XEXP (base_addr, 0))) +- return true; ++ sprintf (buff, "smw.bi%s\t%%1, [%%0], %%1", update_base); + } +- +- return false; ++ output_asm_insn (buff, otherops); ++ return ""; + } + + /* ------------------------------------------------------------------------ */ + const char * +-nds32_output_smw_single_word (rtx *operands) ++nds32_output_smw_double_word (rtx *operands) + { + char buff[100]; + unsigned regno; +@@ -2303,7 +2498,7 @@ + bool update_base_p; + rtx base_addr = operands[0]; + rtx base_reg; +- rtx otherops[2]; ++ rtx otherops[3]; + + if (REG_P (XEXP (base_addr, 0))) + { +@@ -2322,15 +2517,22 @@ + + otherops[0] = base_reg; + otherops[1] = operands[1]; ++ otherops[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);; + + if (regno >= 28) + { +- enable4 = nds32_regno_to_enable4 (regno); ++ enable4 = nds32_regno_to_enable4 (regno) ++ | nds32_regno_to_enable4 (regno + 1); + sprintf (buff, "smw.bi%s\t$sp, [%%0], $sp, %x", update_base, enable4); + } ++ else if (regno == 27) ++ { ++ enable4 = nds32_regno_to_enable4 (regno + 1); ++ sprintf (buff, "smw.bi%s\t%%1, [%%0], %%1, %x", update_base, enable4); ++ } + else + { +- sprintf (buff, "smw.bi%s\t%%1, [%%0], %%1", update_base); ++ sprintf (buff, "smw.bi%s\t%%1, [%%0], %%2", update_base); + } + output_asm_insn (buff, otherops); + return ""; +@@ -2415,16 +2617,17 @@ + if (mode == DImode) + { + /* Load doubleword, we need two registers to access. */ +- reg[0] = simplify_gen_subreg (SImode, operands[0], +- GET_MODE (operands[0]), 0); +- reg[1] = simplify_gen_subreg (SImode, operands[0], +- GET_MODE (operands[0]), 4); ++ reg[0] = nds32_di_low_part_subreg (operands[0]); ++ reg[1] = nds32_di_high_part_subreg (operands[0]); + /* A register only store 4 byte. */ + width = GET_MODE_SIZE (SImode) - 1; + } + else + { +- reg[0] = operands[0]; ++ if (VECTOR_MODE_P (mode)) ++ reg[0] = gen_reg_rtx (SImode); ++ else ++ reg[0] = operands[0]; + } + + for (num_reg = (mode == DImode) ? 2 : 1; num_reg > 0; num_reg--) +@@ -2466,6 +2669,8 @@ + offset = offset + offset_adj; + } + } ++ if (VECTOR_MODE_P (mode)) ++ convert_move (operands[0], reg[0], false); + } + + void +@@ -2499,16 +2704,20 @@ + if (mode == DImode) + { + /* Load doubleword, we need two registers to access. */ +- reg[0] = simplify_gen_subreg (SImode, operands[1], +- GET_MODE (operands[1]), 0); +- reg[1] = simplify_gen_subreg (SImode, operands[1], +- GET_MODE (operands[1]), 4); ++ reg[0] = nds32_di_low_part_subreg (operands[1]); ++ reg[1] = nds32_di_high_part_subreg (operands[1]); + /* A register only store 4 byte. */ + width = GET_MODE_SIZE (SImode) - 1; + } + else + { +- reg[0] = operands[1]; ++ if (VECTOR_MODE_P (mode)) ++ { ++ reg[0] = gen_reg_rtx (SImode); ++ convert_move (reg[0], operands[1], false); ++ } ++ else ++ reg[0] = operands[1]; + } + + for (num_reg = (mode == DImode) ? 2 : 1; num_reg > 0; num_reg--) +@@ -2765,6 +2974,36 @@ + return ""; + } + ++const char * ++nds32_output_unpkd8 (rtx output, rtx input, ++ rtx high_idx_rtx, rtx low_idx_rtx, ++ bool signed_p) ++{ ++ char pattern[100]; ++ rtx output_operands[2]; ++ HOST_WIDE_INT high_idx, low_idx; ++ high_idx = INTVAL (high_idx_rtx); ++ low_idx = INTVAL (low_idx_rtx); ++ ++ gcc_assert (high_idx >= 0 && high_idx <= 3); ++ gcc_assert (low_idx >= 0 && low_idx <= 3); ++ ++ /* We only have 10, 20, 30 and 31. */ ++ if ((low_idx != 0 || high_idx == 0) && ++ !(low_idx == 1 && high_idx == 3)) ++ return "#"; ++ ++ char sign_char = signed_p ? 's' : 'z'; ++ ++ sprintf (pattern, ++ "%cunpkd8" HOST_WIDE_INT_PRINT_DEC HOST_WIDE_INT_PRINT_DEC "\t%%0, %%1", ++ sign_char, high_idx, low_idx); ++ output_operands[0] = output; ++ output_operands[1] = input; ++ output_asm_insn (pattern, output_operands); ++ return ""; ++} ++ + /* Return true if SYMBOL_REF X binds locally. */ + + static bool +@@ -2782,22 +3021,15 @@ + char pattern[100]; + bool noreturn_p; + +- if (GET_CODE (symbol) == CONST) +- { +- symbol= XEXP (symbol, 0); +- +- if (GET_CODE (symbol) == PLUS) +- symbol = XEXP (symbol, 0); +- } +- +- gcc_assert (GET_CODE (symbol) == SYMBOL_REF +- || REG_P (symbol)); +- + if (nds32_long_call_p (symbol)) + strcpy (pattern, long_call); + else + strcpy (pattern, call); + ++ if (flag_pic && CONSTANT_P (symbol) ++ && !nds32_symbol_binds_local_p (symbol)) ++ strcat (pattern, "@PLT"); ++ + if (align_p) + strcat (pattern, "\n\t.align 2"); + +@@ -2815,6 +3047,91 @@ + return ""; + } + ++bool ++nds32_need_split_sms_p (rtx in0_idx0, rtx in1_idx0, ++ rtx in0_idx1, rtx in1_idx1) ++{ ++ /* smds or smdrs. */ ++ if (INTVAL (in0_idx0) == INTVAL (in1_idx0) ++ && INTVAL (in0_idx1) == INTVAL (in1_idx1) ++ && INTVAL (in0_idx0) != INTVAL (in0_idx1)) ++ return false; ++ ++ /* smxds. */ ++ if (INTVAL (in0_idx0) != INTVAL (in0_idx1) ++ && INTVAL (in1_idx0) != INTVAL (in1_idx1)) ++ return false; ++ ++ return true; ++} ++ ++const char * ++nds32_output_sms (rtx in0_idx0, rtx in1_idx0, ++ rtx in0_idx1, rtx in1_idx1) ++{ ++ if (nds32_need_split_sms_p (in0_idx0, in1_idx0, ++ in0_idx1, in1_idx1)) ++ return "#"; ++ /* out = in0[in0_idx0] * in1[in1_idx0] - in0[in0_idx1] * in1[in1_idx1] */ ++ ++ /* smds or smdrs. */ ++ if (INTVAL (in0_idx0) == INTVAL (in1_idx0) ++ && INTVAL (in0_idx1) == INTVAL (in1_idx1) ++ && INTVAL (in0_idx0) != INTVAL (in0_idx1)) ++ { ++ if (INTVAL (in0_idx0) == 0) ++ { ++ if (TARGET_BIG_ENDIAN) ++ return "smds\t%0, %1, %2"; ++ else ++ return "smdrs\t%0, %1, %2"; ++ } ++ else ++ { ++ if (TARGET_BIG_ENDIAN) ++ return "smdrs\t%0, %1, %2"; ++ else ++ return "smds\t%0, %1, %2"; ++ } ++ } ++ ++ if (INTVAL (in0_idx0) != INTVAL (in0_idx1) ++ && INTVAL (in1_idx0) != INTVAL (in1_idx1)) ++ { ++ if (INTVAL (in0_idx0) == 1) ++ { ++ if (TARGET_BIG_ENDIAN) ++ return "smxds\t%0, %2, %1"; ++ else ++ return "smxds\t%0, %1, %2"; ++ } ++ else ++ { ++ if (TARGET_BIG_ENDIAN) ++ return "smxds\t%0, %1, %2"; ++ else ++ return "smxds\t%0, %2, %1"; ++ } ++ } ++ ++ gcc_unreachable (); ++ return ""; ++} ++ ++void ++nds32_split_sms (rtx out, rtx in0, rtx in1, ++ rtx in0_idx0, rtx in1_idx0, ++ rtx in0_idx1, rtx in1_idx1) ++{ ++ rtx result0 = gen_reg_rtx (SImode); ++ rtx result1 = gen_reg_rtx (SImode); ++ emit_insn (gen_mulhisi3v (result0, in0, in1, ++ in0_idx0, in1_idx0)); ++ emit_insn (gen_mulhisi3v (result1, in0, in1, ++ in0_idx1, in1_idx1)); ++ emit_insn (gen_subsi3 (out, result0, result1)); ++} ++ + /* Spilt a doubleword instrucion to two single word instructions. */ + void + nds32_spilt_doubleword (rtx *operands, bool load_p) +@@ -2846,16 +3163,30 @@ + /* generate low_part and high_part memory format: + low_part: (post_modify ((reg) (plus (reg) (const 4))) + high_part: (post_modify ((reg) (plus (reg) (const -12))) */ +- low_part[mem] = gen_frame_mem (SImode, +- gen_rtx_POST_MODIFY (Pmode, sub_mem, +- gen_rtx_PLUS (Pmode, +- sub_mem, +- GEN_INT (4)))); +- high_part[mem] = gen_frame_mem (SImode, +- gen_rtx_POST_MODIFY (Pmode, sub_mem, +- gen_rtx_PLUS (Pmode, +- sub_mem, +- GEN_INT (-12)))); ++ low_part[mem] = gen_rtx_MEM (SImode, ++ gen_rtx_POST_MODIFY (Pmode, sub_mem, ++ gen_rtx_PLUS (Pmode, ++ sub_mem, ++ GEN_INT (4)))); ++ high_part[mem] = gen_rtx_MEM (SImode, ++ gen_rtx_POST_MODIFY (Pmode, sub_mem, ++ gen_rtx_PLUS (Pmode, ++ sub_mem, ++ GEN_INT (-12)))); ++ } ++ else if (GET_CODE (sub_mem) == POST_INC) ++ { ++ /* memory format is (post_inc (reg)), ++ so that extract (reg) from the (post_inc (reg)) pattern. */ ++ sub_mem = XEXP (sub_mem, 0); ++ ++ /* generate low_part and high_part memory format: ++ low_part: (post_inc (reg)) ++ high_part: (post_inc (reg)) */ ++ low_part[mem] = gen_rtx_MEM (SImode, ++ gen_rtx_POST_INC (Pmode, sub_mem)); ++ high_part[mem] = gen_rtx_MEM (SImode, ++ gen_rtx_POST_INC (Pmode, sub_mem)); + } + else if (GET_CODE (sub_mem) == POST_MODIFY) + { +@@ -2872,14 +3203,14 @@ + /* Generate low_part and high_part memory format: + low_part: (post_modify ((reg) (plus (reg) (const))) + high_part: ((plus (reg) (const 4))) */ +- low_part[mem] = gen_frame_mem (SImode, +- gen_rtx_POST_MODIFY (Pmode, post_mem, +- gen_rtx_PLUS (Pmode, +- post_mem, +- post_val))); +- high_part[mem] = gen_frame_mem (SImode, plus_constant (Pmode, +- post_mem, +- 4)); ++ low_part[mem] = gen_rtx_MEM (SImode, ++ gen_rtx_POST_MODIFY (Pmode, post_mem, ++ gen_rtx_PLUS (Pmode, ++ post_mem, ++ post_val))); ++ high_part[mem] = gen_rtx_MEM (SImode, plus_constant (Pmode, ++ post_mem, ++ 4)); + } + else + { +@@ -2924,11 +3255,516 @@ + } + } + ++void ++nds32_split_ashiftdi3 (rtx dst, rtx src, rtx shiftamount) ++{ ++ rtx src_high_part, src_low_part; ++ rtx dst_high_part, dst_low_part; ++ ++ dst_high_part = nds32_di_high_part_subreg (dst); ++ dst_low_part = nds32_di_low_part_subreg (dst); ++ ++ src_high_part = nds32_di_high_part_subreg (src); ++ src_low_part = nds32_di_low_part_subreg (src); ++ ++ /* We need to handle shift more than 32 bit!!!! */ ++ if (CONST_INT_P (shiftamount)) ++ { ++ if (INTVAL (shiftamount) < 32) ++ { ++ rtx ext_start; ++ ext_start = gen_int_mode(32 - INTVAL (shiftamount), SImode); ++ ++ emit_insn (gen_wext (dst_high_part, src, ext_start)); ++ emit_insn (gen_ashlsi3 (dst_low_part, src_low_part, shiftamount)); ++ } ++ else ++ { ++ rtx new_shift_amout = gen_int_mode(INTVAL (shiftamount) - 32, SImode); ++ ++ emit_insn (gen_ashlsi3 (dst_high_part, src_low_part, ++ new_shift_amout)); ++ ++ emit_move_insn (dst_low_part, GEN_INT (0)); ++ } ++ } ++ else ++ { ++ rtx dst_low_part_l32, dst_high_part_l32; ++ rtx dst_low_part_g32, dst_high_part_g32; ++ rtx new_shift_amout, select_reg; ++ dst_low_part_l32 = gen_reg_rtx (SImode); ++ dst_high_part_l32 = gen_reg_rtx (SImode); ++ dst_low_part_g32 = gen_reg_rtx (SImode); ++ dst_high_part_g32 = gen_reg_rtx (SImode); ++ new_shift_amout = gen_reg_rtx (SImode); ++ select_reg = gen_reg_rtx (SImode); ++ ++ rtx ext_start; ++ ext_start = gen_reg_rtx (SImode); ++ ++ /* ++ if (shiftamount < 32) ++ dst_low_part = src_low_part << shiftamout ++ dst_high_part = wext (src, 32 - shiftamount) ++ # wext can't handle wext (src, 32) since it's only take rb[0:4] ++ # for extract. ++ dst_high_part = shiftamount == 0 ? src_high_part : dst_high_part ++ else ++ dst_low_part = 0 ++ dst_high_part = src_low_part << shiftamount & 0x1f ++ */ ++ ++ emit_insn (gen_subsi3 (ext_start, ++ gen_int_mode (32, SImode), ++ shiftamount)); ++ emit_insn (gen_wext (dst_high_part_l32, src, ext_start)); ++ ++ /* Handle for shiftamout == 0. */ ++ emit_insn (gen_cmovzsi (dst_high_part_l32, shiftamount, ++ src_high_part, dst_high_part_l32)); ++ ++ emit_insn (gen_ashlsi3 (dst_low_part_l32, src_low_part, shiftamount)); ++ ++ emit_move_insn (dst_low_part_g32, const0_rtx); ++ emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f))); ++ emit_insn (gen_ashlsi3 (dst_high_part_g32, src_low_part, ++ new_shift_amout)); ++ ++ emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32))); ++ ++ emit_insn (gen_cmovnsi (dst_low_part, select_reg, ++ dst_low_part_l32, dst_low_part_g32)); ++ emit_insn (gen_cmovnsi (dst_high_part, select_reg, ++ dst_high_part_l32, dst_high_part_g32)); ++ } ++} ++ ++void ++nds32_split_ashiftrtdi3 (rtx dst, rtx src, rtx shiftamount) ++{ ++ nds32_split_shiftrtdi3 (dst, src, shiftamount, false); ++} ++ ++void ++nds32_split_lshiftrtdi3 (rtx dst, rtx src, rtx shiftamount) ++{ ++ nds32_split_shiftrtdi3 (dst, src, shiftamount, true); ++} ++ ++void ++nds32_split_rotatertdi3 (rtx dst, rtx src, rtx shiftamount) ++{ ++ rtx dst_low_part_l32, dst_high_part_l32; ++ rtx dst_low_part_g32, dst_high_part_g32; ++ rtx select_reg, low5bit, low5bit_inv, minus32sa; ++ rtx dst_low_part_g32_tmph; ++ rtx dst_low_part_g32_tmpl; ++ rtx dst_high_part_l32_tmph; ++ rtx dst_high_part_l32_tmpl; ++ ++ rtx src_low_part, src_high_part; ++ rtx dst_high_part, dst_low_part; ++ ++ shiftamount = force_reg (SImode, shiftamount); ++ ++ emit_insn (gen_andsi3 (shiftamount, ++ shiftamount, ++ gen_int_mode (0x3f, SImode))); ++ ++ dst_high_part = nds32_di_high_part_subreg (dst); ++ dst_low_part = nds32_di_low_part_subreg (dst); ++ ++ src_high_part = nds32_di_high_part_subreg (src); ++ src_low_part = nds32_di_low_part_subreg (src); ++ ++ dst_low_part_l32 = gen_reg_rtx (SImode); ++ dst_high_part_l32 = gen_reg_rtx (SImode); ++ dst_low_part_g32 = gen_reg_rtx (SImode); ++ dst_high_part_g32 = gen_reg_rtx (SImode); ++ low5bit = gen_reg_rtx (SImode); ++ low5bit_inv = gen_reg_rtx (SImode); ++ minus32sa = gen_reg_rtx (SImode); ++ select_reg = gen_reg_rtx (SImode); ++ ++ dst_low_part_g32_tmph = gen_reg_rtx (SImode); ++ dst_low_part_g32_tmpl = gen_reg_rtx (SImode); ++ ++ dst_high_part_l32_tmph = gen_reg_rtx (SImode); ++ dst_high_part_l32_tmpl = gen_reg_rtx (SImode); ++ ++ emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32))); ++ ++ /* if shiftamount < 32 ++ dst_low_part = wext(src, shiftamount) ++ else ++ dst_low_part = ((src_high_part >> (shiftamount & 0x1f)) ++ | (src_low_part << (32 - (shiftamount & 0x1f)))) ++ */ ++ emit_insn (gen_andsi3 (low5bit, shiftamount, gen_int_mode (0x1f, SImode))); ++ emit_insn (gen_subsi3 (low5bit_inv, gen_int_mode (32, SImode), low5bit)); ++ ++ emit_insn (gen_wext (dst_low_part_l32, src, shiftamount)); ++ ++ emit_insn (gen_lshrsi3 (dst_low_part_g32_tmpl, src_high_part, low5bit)); ++ emit_insn (gen_ashlsi3 (dst_low_part_g32_tmph, src_low_part, low5bit_inv)); ++ ++ emit_insn (gen_iorsi3 (dst_low_part_g32, ++ dst_low_part_g32_tmpl, ++ dst_low_part_g32_tmph)); ++ ++ emit_insn (gen_cmovnsi (dst_low_part, select_reg, ++ dst_low_part_l32, dst_low_part_g32)); ++ ++ /* if shiftamount < 32 ++ dst_high_part = ((src_high_part >> shiftamount) ++ | (src_low_part << (32 - shiftamount))) ++ dst_high_part = shiftamount == 0 ? src_high_part : dst_high_part ++ else ++ dst_high_part = wext(src, shiftamount & 0x1f) ++ */ ++ ++ emit_insn (gen_subsi3 (minus32sa, gen_int_mode (32, SImode), shiftamount)); ++ ++ emit_insn (gen_lshrsi3 (dst_high_part_l32_tmpl, src_high_part, shiftamount)); ++ emit_insn (gen_ashlsi3 (dst_high_part_l32_tmph, src_low_part, minus32sa)); ++ ++ emit_insn (gen_iorsi3 (dst_high_part_l32, ++ dst_high_part_l32_tmpl, ++ dst_high_part_l32_tmph)); ++ ++ emit_insn (gen_cmovzsi (dst_high_part_l32, shiftamount, ++ src_high_part, dst_high_part_l32)); ++ ++ emit_insn (gen_wext (dst_high_part_g32, src, low5bit)); ++ ++ emit_insn (gen_cmovnsi (dst_high_part, select_reg, ++ dst_high_part_l32, dst_high_part_g32)); ++} ++ ++/* Return true if OP contains a symbol reference. */ ++bool ++symbolic_reference_mentioned_p (rtx op) ++{ ++ const char *fmt; ++ int i; ++ ++ if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) ++ return true; ++ ++ fmt = GET_RTX_FORMAT (GET_CODE (op)); ++ for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) ++ { ++ if (fmt[i] == 'E') ++ { ++ int j; ++ ++ for (j = XVECLEN (op, i) - 1; j >= 0; j--) ++ if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) ++ return true; ++ } ++ ++ else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) ++ return true; ++ } ++ ++ return false; ++} ++ ++/* Expand PIC code for @GOTOFF and @GOT. ++ ++ Example for @GOTOFF: ++ ++ la $r0, symbol@GOTOFF ++ -> sethi $ta, hi20(symbol@GOTOFF) ++ ori $ta, $ta, lo12(symbol@GOTOFF) ++ add $r0, $ta, $gp ++ ++ Example for @GOT: ++ ++ la $r0, symbol@GOT ++ -> sethi $ta, hi20(symbol@GOT) ++ ori $ta, $ta, lo12(symbol@GOT) ++ lw $r0, [$ta + $gp] ++*/ ++rtx ++nds32_legitimize_pic_address (rtx x) ++{ ++ rtx addr = x; ++ rtx reg = gen_reg_rtx (Pmode); ++ rtx pat; ++ ++ if (GET_CODE (x) == LABEL_REF ++ || (GET_CODE (x) == SYMBOL_REF ++ && (CONSTANT_POOL_ADDRESS_P (x) ++ || SYMBOL_REF_LOCAL_P (x)))) ++ { ++ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_GOTOFF); ++ addr = gen_rtx_CONST (SImode, addr); ++ emit_insn (gen_sethi (reg, addr)); ++ emit_insn (gen_lo_sum (reg, reg, addr)); ++ x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx); ++ } ++ else if (GET_CODE (x) == SYMBOL_REF) ++ { ++ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_GOT); ++ addr = gen_rtx_CONST (SImode, addr); ++ emit_insn (gen_sethi (reg, addr)); ++ emit_insn (gen_lo_sum (reg, reg, addr)); ++ ++ x = gen_const_mem (SImode, gen_rtx_PLUS (Pmode, pic_offset_table_rtx, ++ reg)); ++ } ++ else if (GET_CODE (x) == CONST) ++ { ++ /* We don't split constant in expand_pic_move because GOTOFF can combine ++ the addend with the symbol. */ ++ addr = XEXP (x, 0); ++ gcc_assert (GET_CODE (addr) == PLUS); ++ ++ rtx op0 = XEXP (addr, 0); ++ rtx op1 = XEXP (addr, 1); ++ ++ if ((GET_CODE (op0) == LABEL_REF ++ || (GET_CODE (op0) == SYMBOL_REF ++ && (CONSTANT_POOL_ADDRESS_P (op0) ++ || SYMBOL_REF_LOCAL_P (op0)))) ++ && GET_CODE (op1) == CONST_INT) ++ { ++ pat = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), UNSPEC_GOTOFF); ++ pat = gen_rtx_PLUS (Pmode, pat, op1); ++ pat = gen_rtx_CONST (Pmode, pat); ++ emit_insn (gen_sethi (reg, pat)); ++ emit_insn (gen_lo_sum (reg, reg, pat)); ++ x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx); ++ } ++ else if (GET_CODE (op0) == SYMBOL_REF ++ && GET_CODE (op1) == CONST_INT) ++ { ++ /* This is a constant offset from a @GOT symbol reference. */ ++ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, op0), UNSPEC_GOT); ++ addr = gen_rtx_CONST (SImode, addr); ++ emit_insn (gen_sethi (reg, addr)); ++ emit_insn (gen_lo_sum (reg, reg, addr)); ++ addr = gen_const_mem (SImode, gen_rtx_PLUS (Pmode, ++ pic_offset_table_rtx, ++ reg)); ++ emit_move_insn (reg, addr); ++ if (satisfies_constraint_Is15 (op1)) ++ x = gen_rtx_PLUS (Pmode, reg, op1); ++ else ++ { ++ rtx tmp_reg = gen_reg_rtx (SImode); ++ emit_insn (gen_movsi (tmp_reg, op1)); ++ x = gen_rtx_PLUS (Pmode, reg, tmp_reg); ++ } ++ } ++ else ++ { ++ /* Don't handle this pattern. */ ++ debug_rtx (x); ++ gcc_unreachable (); ++ } ++ } ++ return x; ++} ++ ++void ++nds32_expand_pic_move (rtx *operands) ++{ ++ rtx src; ++ ++ src = nds32_legitimize_pic_address (operands[1]); ++ emit_move_insn (operands[0], src); ++} ++ ++/* Expand ICT symbol. ++ Example for @ICT and ICT model=large: ++ ++ la $r0, symbol@ICT ++ -> sethi $rt, hi20(symbol@ICT) ++ lwi $r0, [$rt + lo12(symbol@ICT)] ++ ++*/ ++rtx ++nds32_legitimize_ict_address (rtx x) ++{ ++ rtx symbol = x; ++ rtx addr = x; ++ rtx reg = gen_reg_rtx (Pmode); ++ gcc_assert (GET_CODE (x) == SYMBOL_REF ++ && nds32_indirect_call_referenced_p (x)); ++ ++ addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, symbol), UNSPEC_ICT); ++ addr = gen_rtx_CONST (SImode, addr); ++ emit_insn (gen_sethi (reg, addr)); ++ ++ x = gen_const_mem (SImode, gen_rtx_LO_SUM (Pmode, reg, addr)); ++ ++ return x; ++} ++ ++void ++nds32_expand_ict_move (rtx *operands) ++{ ++ rtx src = operands[1]; ++ ++ src = nds32_legitimize_ict_address (src); ++ ++ emit_move_insn (operands[0], src); ++} ++ ++/* Return true X is a indirect call symbol. */ ++bool ++nds32_indirect_call_referenced_p (rtx x) ++{ ++ if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_ICT) ++ x = XVECEXP (x, 0, 0); ++ ++ if (GET_CODE (x) == SYMBOL_REF) ++ { ++ tree decl = SYMBOL_REF_DECL (x); ++ ++ return decl ++ && (lookup_attribute("indirect_call", ++ DECL_ATTRIBUTES(decl)) ++ != NULL); ++ } ++ ++ return false; ++} ++ + /* Return true X is need use long call. */ + bool + nds32_long_call_p (rtx symbol) + { +- return TARGET_CMODEL_LARGE; ++ if (nds32_indirect_call_referenced_p (symbol)) ++ return TARGET_ICT_MODEL_LARGE; ++ else ++ return TARGET_CMODEL_LARGE; ++} ++ ++/* Return true if X contains a thread-local symbol. */ ++bool ++nds32_tls_referenced_p (rtx x) ++{ ++ if (!targetm.have_tls) ++ return false; ++ ++ if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) ++ x = XEXP (XEXP (x, 0), 0); ++ ++ if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x)) ++ return true; ++ ++ return false; ++} ++ ++/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute ++ this (thread-local) address. */ ++rtx ++nds32_legitimize_tls_address (rtx x) ++{ ++ rtx tmp_reg; ++ rtx tp_reg = gen_rtx_REG (Pmode, TP_REGNUM); ++ rtx pat, insns, reg0; ++ ++ if (GET_CODE (x) == SYMBOL_REF) ++ switch (SYMBOL_REF_TLS_MODEL (x)) ++ { ++ case TLS_MODEL_GLOBAL_DYNAMIC: ++ case TLS_MODEL_LOCAL_DYNAMIC: ++ /* Emit UNSPEC_TLS_DESC rather than expand rtl directly because spill ++ may destroy the define-use chain anylysis to insert relax_hint. */ ++ if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC) ++ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSGD); ++ else ++ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSLD); ++ ++ pat = gen_rtx_CONST (SImode, pat); ++ reg0 = gen_rtx_REG (Pmode, 0); ++ /* If we can confirm all clobber reigsters, it doesn't have to use call ++ instruction. */ ++ insns = emit_call_insn (gen_tls_desc (pat, GEN_INT (0))); ++ use_reg (&CALL_INSN_FUNCTION_USAGE (insns), pic_offset_table_rtx); ++ RTL_CONST_CALL_P (insns) = 1; ++ tmp_reg = gen_reg_rtx (SImode); ++ emit_move_insn (tmp_reg, reg0); ++ x = tmp_reg; ++ break; ++ ++ case TLS_MODEL_INITIAL_EXEC: ++ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSIE); ++ tmp_reg = gen_reg_rtx (SImode); ++ pat = gen_rtx_CONST (SImode, pat); ++ emit_insn (gen_tls_ie (tmp_reg, pat, GEN_INT (0))); ++ if (flag_pic) ++ emit_use (pic_offset_table_rtx); ++ x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg); ++ break; ++ ++ case TLS_MODEL_LOCAL_EXEC: ++ /* Expand symbol_ref@TPOFF': ++ sethi $ta, hi20(symbol_ref@TPOFF) ++ ori $ta, $ta, lo12(symbol_ref@TPOFF) ++ add $r0, $ta, $tp */ ++ tmp_reg = gen_reg_rtx (SImode); ++ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSLE); ++ pat = gen_rtx_CONST (SImode, pat); ++ emit_insn (gen_sethi (tmp_reg, pat)); ++ emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat)); ++ x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ else if (GET_CODE (x) == CONST) ++ { ++ rtx base, addend; ++ split_const (x, &base, &addend); ++ ++ if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_EXEC) ++ { ++ /* Expand symbol_ref@TPOFF': ++ sethi $ta, hi20(symbol_ref@TPOFF + addend) ++ ori $ta, $ta, lo12(symbol_ref@TPOFF + addend) ++ add $r0, $ta, $tp */ ++ tmp_reg = gen_reg_rtx (SImode); ++ pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, base), UNSPEC_TLSLE); ++ pat = gen_rtx_PLUS (SImode, pat, addend); ++ pat = gen_rtx_CONST (SImode, pat); ++ emit_insn (gen_sethi (tmp_reg, pat)); ++ emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat)); ++ x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg); ++ } ++ } ++ ++ return x; ++} ++ ++void ++nds32_expand_tls_move (rtx *operands) ++{ ++ rtx src = operands[1]; ++ rtx base, addend; ++ ++ if (CONSTANT_P (src)) ++ split_const (src, &base, &addend); ++ ++ if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_EXEC) ++ src = nds32_legitimize_tls_address (src); ++ else ++ { ++ src = nds32_legitimize_tls_address (base); ++ if (addend != const0_rtx) ++ { ++ src = gen_rtx_PLUS (SImode, src, addend); ++ src = force_operand (src, operands[0]); ++ } ++ } ++ ++ emit_move_insn (operands[0], src); + } + + void +@@ -2976,3 +3812,105 @@ + emit_move_insn (target, gen_rtx_fmt_ee (AND, mode, source, temp)); + } + } ++ ++/* Auxiliary functions for lwm/smw. */ ++bool ++nds32_valid_smw_lwm_base_p (rtx op) ++{ ++ rtx base_addr; ++ ++ if (!MEM_P (op)) ++ return false; ++ ++ base_addr = XEXP (op, 0); ++ ++ if (REG_P (base_addr)) ++ return true; ++ else ++ { ++ if (GET_CODE (base_addr) == POST_INC ++ && REG_P (XEXP (base_addr, 0))) ++ return true; ++ } ++ ++ return false; ++} ++ ++/* Auxiliary functions for manipulation DI mode. */ ++rtx nds32_di_high_part_subreg(rtx reg) ++{ ++ unsigned high_part_offset = subreg_highpart_offset (SImode, DImode); ++ ++ return simplify_gen_subreg ( ++ SImode, reg, ++ DImode, high_part_offset); ++} ++ ++rtx nds32_di_low_part_subreg(rtx reg) ++{ ++ unsigned low_part_offset = subreg_lowpart_offset (SImode, DImode); ++ ++ return simplify_gen_subreg ( ++ SImode, reg, ++ DImode, low_part_offset); ++} ++ ++/* ------------------------------------------------------------------------ */ ++ ++/* Auxiliary function for output TLS patterns. */ ++ ++const char * ++nds32_output_tls_desc (rtx *operands) ++{ ++ char pattern[1000]; ++ ++ if (TARGET_RELAX_HINT) ++ snprintf (pattern, sizeof (pattern), ++ ".relax_hint %%1\n\tsethi $r0, hi20(%%0)\n\t" ++ ".relax_hint %%1\n\tori $r0, $r0, lo12(%%0)\n\t" ++ ".relax_hint %%1\n\tlw $r15, [$r0 + $gp]\n\t" ++ ".relax_hint %%1\n\tadd $r0, $r0, $gp\n\t" ++ ".relax_hint %%1\n\tjral $r15"); ++ else ++ snprintf (pattern, sizeof (pattern), ++ "sethi $r0, hi20(%%0)\n\t" ++ "ori $r0, $r0, lo12(%%0)\n\t" ++ "lw $r15, [$r0 + $gp]\n\t" ++ "add $r0, $r0, $gp\n\t" ++ "jral $r15"); ++ output_asm_insn (pattern, operands); ++ return ""; ++} ++ ++const char * ++nds32_output_tls_ie (rtx *operands) ++{ ++ char pattern[1000]; ++ ++ if (flag_pic) ++ { ++ if (TARGET_RELAX_HINT) ++ snprintf (pattern, sizeof (pattern), ++ ".relax_hint %%2\n\tsethi %%0, hi20(%%1)\n\t" ++ ".relax_hint %%2\n\tori %%0, %%0, lo12(%%1)\n\t" ++ ".relax_hint %%2\n\tlw %%0, [%%0 + $gp]"); ++ else ++ snprintf (pattern, sizeof (pattern), ++ "sethi %%0, hi20(%%1)\n\t" ++ "ori %%0, %%0, lo12(%%1)\n\t" ++ "lw %%0, [%%0 + $gp]"); ++ } ++ else ++ { ++ if (TARGET_RELAX_HINT) ++ snprintf (pattern, sizeof (pattern), ++ ".relax_hint %%2\n\tsethi %%0, hi20(%%1)\n\t" ++ ".relax_hint %%2\n\tlwi %%0, [%%0 + lo12(%%1)]"); ++ else ++ snprintf (pattern, sizeof (pattern), ++ "sethi %%0, hi20(%%1)\n\t" ++ "lwi %%0, [%%0 + lo12(%%1)]"); ++ } ++ output_asm_insn (pattern, operands); ++ return ""; ++} +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-memory-manipulation.c gcc-8.2.0/gcc/config/nds32/nds32-memory-manipulation.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-memory-manipulation.c 2018-03-11 09:24:33.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-memory-manipulation.c 2019-01-25 15:38:32.829242659 +0100 +@@ -257,8 +257,124 @@ + nds32_expand_movmemsi_loop_known_size (rtx dstmem, rtx srcmem, + rtx size, rtx alignment) + { +- return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem, +- size, alignment); ++ rtx dst_base_reg, src_base_reg; ++ rtx dst_itr, src_itr; ++ rtx dstmem_m, srcmem_m, dst_itr_m, src_itr_m; ++ rtx dst_end; ++ rtx double_word_mode_loop, byte_mode_loop; ++ rtx tmp; ++ int start_regno; ++ bool align_to_4_bytes = (INTVAL (alignment) & 3) == 0; ++ unsigned HOST_WIDE_INT total_bytes = UINTVAL (size); ++ ++ if (TARGET_ISA_V3M && !align_to_4_bytes) ++ return 0; ++ ++ if (TARGET_REDUCED_REGS) ++ start_regno = 2; ++ else ++ start_regno = 16; ++ ++ dst_itr = gen_reg_rtx (Pmode); ++ src_itr = gen_reg_rtx (Pmode); ++ dst_end = gen_reg_rtx (Pmode); ++ tmp = gen_reg_rtx (QImode); ++ ++ double_word_mode_loop = gen_label_rtx (); ++ byte_mode_loop = gen_label_rtx (); ++ ++ dst_base_reg = copy_to_mode_reg (Pmode, XEXP (dstmem, 0)); ++ src_base_reg = copy_to_mode_reg (Pmode, XEXP (srcmem, 0)); ++ ++ if (total_bytes < 8) ++ { ++ /* Emit total_bytes less than 8 loop version of movmem. ++ add $dst_end, $dst, $size ++ move $dst_itr, $dst ++ .Lbyte_mode_loop: ++ lbi.bi $tmp, [$src_itr], #1 ++ sbi.bi $tmp, [$dst_itr], #1 ++ ! Not readch upper bound. Loop. ++ bne $dst_itr, $dst_end, .Lbyte_mode_loop */ ++ ++ /* add $dst_end, $dst, $size */ ++ dst_end = expand_binop (Pmode, add_optab, dst_base_reg, size, ++ NULL_RTX, 0, OPTAB_WIDEN); ++ /* move $dst_itr, $dst ++ move $src_itr, $src */ ++ emit_move_insn (dst_itr, dst_base_reg); ++ emit_move_insn (src_itr, src_base_reg); ++ ++ /* .Lbyte_mode_loop: */ ++ emit_label (byte_mode_loop); ++ ++ /* lbi.bi $tmp, [$src_itr], #1 */ ++ nds32_emit_post_inc_load_store (tmp, src_itr, QImode, true); ++ ++ /* sbi.bi $tmp, [$dst_itr], #1 */ ++ nds32_emit_post_inc_load_store (tmp, dst_itr, QImode, false); ++ /* ! Not readch upper bound. Loop. ++ bne $dst_itr, $dst_end, .Lbyte_mode_loop */ ++ emit_cmp_and_jump_insns (dst_itr, dst_end, NE, NULL, ++ SImode, 1, byte_mode_loop); ++ return true; ++ } ++ else if (total_bytes % 8 == 0) ++ { ++ /* Emit multiple of 8 loop version of movmem. ++ ++ add $dst_end, $dst, $size ++ move $dst_itr, $dst ++ move $src_itr, $src ++ ++ .Ldouble_word_mode_loop: ++ lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr ++ smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr ++ ! move will delete after register allocation ++ move $src_itr, $src_itr' ++ move $dst_itr, $dst_itr' ++ ! Not readch upper bound. Loop. ++ bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop */ ++ ++ /* add $dst_end, $dst, $size */ ++ dst_end = expand_binop (Pmode, add_optab, dst_base_reg, size, ++ NULL_RTX, 0, OPTAB_WIDEN); ++ ++ /* move $dst_itr, $dst ++ move $src_itr, $src */ ++ emit_move_insn (dst_itr, dst_base_reg); ++ emit_move_insn (src_itr, src_base_reg); ++ ++ /* .Ldouble_word_mode_loop: */ ++ emit_label (double_word_mode_loop); ++ /* lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr ++ smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr */ ++ src_itr_m = src_itr; ++ dst_itr_m = dst_itr; ++ srcmem_m = srcmem; ++ dstmem_m = dstmem; ++ nds32_emit_mem_move_block (start_regno, 2, ++ &dst_itr_m, &dstmem_m, ++ &src_itr_m, &srcmem_m, ++ true); ++ /* move $src_itr, $src_itr' ++ move $dst_itr, $dst_itr' */ ++ emit_move_insn (dst_itr, dst_itr_m); ++ emit_move_insn (src_itr, src_itr_m); ++ ++ /* ! Not readch upper bound. Loop. ++ bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop */ ++ emit_cmp_and_jump_insns (dst_end, dst_itr, NE, NULL, ++ Pmode, 1, double_word_mode_loop); ++ } ++ else ++ { ++ /* Handle size greater than 8, and not a multiple of 8. */ ++ return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem, ++ size, alignment); ++ } ++ ++ return true; + } + + static bool +@@ -433,10 +549,8 @@ + /* Auxiliary function for expand setmem pattern. */ + + static rtx +-nds32_gen_dup_4_byte_to_word_value (rtx value) ++nds32_gen_dup_4_byte_to_word_value_aux (rtx value, rtx value4word) + { +- rtx value4word = gen_reg_rtx (SImode); +- + gcc_assert (GET_MODE (value) == QImode || CONST_INT_P (value)); + + if (CONST_INT_P (value)) +@@ -449,36 +563,74 @@ + } + else + { +- /* ! prepare word +- andi $tmp1, $value, 0xff ! $tmp1 <- 0x000000ab +- slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00 +- or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab +- slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000 +- or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */ +- +- rtx tmp1, tmp2, tmp3, tmp4, final_value; +- tmp1 = expand_binop (SImode, and_optab, value, +- gen_int_mode (0xff, SImode), +- NULL_RTX, 0, OPTAB_WIDEN); +- tmp2 = expand_binop (SImode, ashl_optab, tmp1, +- gen_int_mode (8, SImode), +- NULL_RTX, 0, OPTAB_WIDEN); +- tmp3 = expand_binop (SImode, ior_optab, tmp1, tmp2, +- NULL_RTX, 0, OPTAB_WIDEN); +- tmp4 = expand_binop (SImode, ashl_optab, tmp3, +- gen_int_mode (16, SImode), +- NULL_RTX, 0, OPTAB_WIDEN); +- +- final_value = expand_binop (SImode, ior_optab, tmp3, tmp4, +- NULL_RTX, 0, OPTAB_WIDEN); +- emit_move_insn (value4word, final_value); ++ if (NDS32_EXT_DSP_P ()) ++ { ++ /* ! prepare word ++ insb $tmp, $value, 1 ! $tmp <- 0x0000abab ++ pkbb16 $tmp6, $tmp2, $tmp2 ! $value4word <- 0xabababab */ ++ rtx tmp = gen_reg_rtx (SImode); ++ ++ convert_move (tmp, value, true); ++ ++ emit_insn ( ++ gen_insvsi_internal (tmp, gen_int_mode (0x8, SImode), tmp)); ++ ++ emit_insn (gen_pkbbsi_1 (value4word, tmp, tmp)); ++ } ++ else ++ { ++ /* ! prepare word ++ andi $tmp1, $value, 0xff ! $tmp1 <- 0x000000ab ++ slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00 ++ or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab ++ slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000 ++ or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */ ++ ++ rtx tmp1, tmp2, tmp3, tmp4; ++ tmp1 = expand_binop (SImode, and_optab, value, ++ gen_int_mode (0xff, SImode), ++ NULL_RTX, 0, OPTAB_WIDEN); ++ tmp2 = expand_binop (SImode, ashl_optab, tmp1, ++ gen_int_mode (8, SImode), ++ NULL_RTX, 0, OPTAB_WIDEN); ++ tmp3 = expand_binop (SImode, ior_optab, tmp1, tmp2, ++ NULL_RTX, 0, OPTAB_WIDEN); ++ tmp4 = expand_binop (SImode, ashl_optab, tmp3, ++ gen_int_mode (16, SImode), ++ NULL_RTX, 0, OPTAB_WIDEN); ++ ++ emit_insn (gen_iorsi3 (value4word, tmp3, tmp4)); ++ } + } + + return value4word; + } + + static rtx +-emit_setmem_word_loop (rtx itr, rtx size, rtx value) ++nds32_gen_dup_4_byte_to_word_value (rtx value) ++{ ++ rtx value4word = gen_reg_rtx (SImode); ++ nds32_gen_dup_4_byte_to_word_value_aux (value, value4word); ++ ++ return value4word; ++} ++ ++static rtx ++nds32_gen_dup_8_byte_to_double_word_value (rtx value) ++{ ++ rtx value4doubleword = gen_reg_rtx (DImode); ++ ++ nds32_gen_dup_4_byte_to_word_value_aux ( ++ value, nds32_di_low_part_subreg(value4doubleword)); ++ ++ emit_move_insn (nds32_di_high_part_subreg(value4doubleword), ++ nds32_di_low_part_subreg(value4doubleword)); ++ return value4doubleword; ++} ++ ++ ++static rtx ++emit_setmem_doubleword_loop (rtx itr, rtx size, rtx value) + { + rtx word_mode_label = gen_label_rtx (); + rtx word_mode_end_label = gen_label_rtx (); +@@ -487,9 +639,9 @@ + rtx word_mode_end = gen_reg_rtx (SImode); + rtx size_for_word = gen_reg_rtx (SImode); + +- /* and $size_for_word, $size, #~3 */ ++ /* and $size_for_word, $size, #~0x7 */ + size_for_word = expand_binop (SImode, and_optab, size, +- gen_int_mode (~3, SImode), ++ gen_int_mode (~0x7, SImode), + NULL_RTX, 0, OPTAB_WIDEN); + + emit_move_insn (byte_mode_size, size); +@@ -501,8 +653,8 @@ + word_mode_end = expand_binop (Pmode, add_optab, itr, size_for_word, + NULL_RTX, 0, OPTAB_WIDEN); + +- /* andi $byte_mode_size, $size, 3 */ +- byte_mode_size_tmp = expand_binop (SImode, and_optab, size, GEN_INT (3), ++ /* andi $byte_mode_size, $size, 0x7 */ ++ byte_mode_size_tmp = expand_binop (SImode, and_optab, size, GEN_INT (0x7), + NULL_RTX, 0, OPTAB_WIDEN); + + emit_move_insn (byte_mode_size, byte_mode_size_tmp); +@@ -512,9 +664,9 @@ + /* ! word-mode set loop + smw.bim $value4word, [$dst_itr], $value4word, 0 + bne $word_mode_end, $dst_itr, .Lword_mode */ +- emit_insn (gen_unaligned_store_update_base_w (itr, +- itr, +- value)); ++ emit_insn (gen_unaligned_store_update_base_dw (itr, ++ itr, ++ value)); + emit_cmp_and_jump_insns (word_mode_end, itr, NE, NULL, + Pmode, 1, word_mode_label); + +@@ -566,7 +718,7 @@ + static bool + nds32_expand_setmem_loop (rtx dstmem, rtx size, rtx value) + { +- rtx value4word; ++ rtx value4doubleword; + rtx value4byte; + rtx dst; + rtx byte_mode_size; +@@ -609,7 +761,7 @@ + or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab + slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000 + or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */ +- value4word = nds32_gen_dup_4_byte_to_word_value (value); ++ value4doubleword = nds32_gen_dup_8_byte_to_double_word_value (value); + + /* and $size_for_word, $size, #-4 + beqz $size_for_word, .Lword_mode_end +@@ -622,7 +774,7 @@ + smw.bim $value4word, [$dst], $value4word, 0 + bne $word_mode_end, $dst, .Lword_mode + .Lword_mode_end: */ +- byte_mode_size = emit_setmem_word_loop (dst, size, value4word); ++ byte_mode_size = emit_setmem_doubleword_loop (dst, size, value4doubleword); + + /* beqz $byte_mode_size, .Lend + add $byte_mode_end, $dst, $byte_mode_size +@@ -633,8 +785,8 @@ + bne $byte_mode_end, $dst, .Lbyte_mode + .Lend: */ + +- value4byte = simplify_gen_subreg (QImode, value4word, SImode, +- subreg_lowpart_offset (QImode, SImode)); ++ value4byte = simplify_gen_subreg (QImode, value4doubleword, DImode, ++ subreg_lowpart_offset (QImode, DImode)); + + emit_setmem_byte_loop (dst, byte_mode_size, value4byte, false); + +@@ -651,14 +803,15 @@ + rtx byte_loop_size = gen_reg_rtx (SImode); + rtx remain_size = gen_reg_rtx (SImode); + rtx new_base_reg; +- rtx value4byte, value4word; ++ rtx value4byte, value4doubleword; + rtx byte_mode_size; + rtx last_byte_loop_label = gen_label_rtx (); + + size = force_reg (SImode, size); + +- value4word = nds32_gen_dup_4_byte_to_word_value (value); +- value4byte = simplify_gen_subreg (QImode, value4word, SImode, 0); ++ value4doubleword = nds32_gen_dup_8_byte_to_double_word_value (value); ++ value4byte = simplify_gen_subreg (QImode, value4doubleword, DImode, ++ subreg_lowpart_offset (QImode, DImode)); + + emit_move_insn (byte_loop_size, size); + emit_move_insn (byte_loop_base, base_reg); +@@ -686,9 +839,9 @@ + emit_insn (gen_subsi3 (remain_size, size, need_align_bytes)); + + /* Set memory word by word. */ +- byte_mode_size = emit_setmem_word_loop (new_base_reg, +- remain_size, +- value4word); ++ byte_mode_size = emit_setmem_doubleword_loop (new_base_reg, ++ remain_size, ++ value4doubleword); + + emit_move_insn (byte_loop_base, new_base_reg); + emit_move_insn (byte_loop_size, byte_mode_size); +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-multiple.md gcc-8.2.0/gcc/config/nds32/nds32-multiple.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-multiple.md 2018-03-11 09:24:33.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-multiple.md 2019-01-25 15:38:32.829242659 +0100 +@@ -2854,6 +2854,25 @@ + (set_attr "length" "4")] + ) + ++(define_expand "unaligned_store_update_base_dw" ++ [(parallel [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 8))) ++ (set (mem:DI (match_dup 1)) ++ (unspec:DI [(match_operand:DI 2 "register_operand" "r")] UNSPEC_UASTORE_DW))])] ++ "" ++{ ++ /* DO NOT emit unaligned_store_w_m immediately since web pass don't ++ recognize post_inc, try it again after GCC 5.0. ++ REF: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156 */ ++ emit_insn (gen_unaligned_store_dw (gen_rtx_MEM (DImode, operands[1]), operands[2])); ++ emit_insn (gen_addsi3 (operands[0], operands[1], gen_int_mode (8, Pmode))); ++ DONE; ++} ++ [(set_attr "type" "store_multiple") ++ (set_attr "combo" "2") ++ (set_attr "length" "4")] ++) ++ + (define_insn "*stmsi25" + [(match_parallel 0 "nds32_store_multiple_operation" + [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-n10.md gcc-8.2.0/gcc/config/nds32/nds32-n10.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-n10.md 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-n10.md 2019-01-25 15:38:32.829242659 +0100 +@@ -0,0 +1,439 @@ ++;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler ++;; Copyright (C) 2012-2018 Free Software Foundation, Inc. ++;; Contributed by Andes Technology Corporation. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 3, or (at your ++;; option) any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++ ++;; ------------------------------------------------------------------------ ++;; Define N10 pipeline settings. ++;; ------------------------------------------------------------------------ ++ ++(define_automaton "nds32_n10_machine") ++ ++;; ------------------------------------------------------------------------ ++;; Pipeline Stages ++;; ------------------------------------------------------------------------ ++;; IF - Instruction Fetch ++;; II - Instruction Issue / Instruction Decode ++;; EX - Instruction Execution ++;; MM - Memory Execution ++;; WB - Instruction Retire / Result Write-Back ++ ++(define_cpu_unit "n10_ii" "nds32_n10_machine") ++(define_cpu_unit "n10_ex" "nds32_n10_machine") ++(define_cpu_unit "n10_mm" "nds32_n10_machine") ++(define_cpu_unit "n10_wb" "nds32_n10_machine") ++(define_cpu_unit "n10f_iq" "nds32_n10_machine") ++(define_cpu_unit "n10f_rf" "nds32_n10_machine") ++(define_cpu_unit "n10f_e1" "nds32_n10_machine") ++(define_cpu_unit "n10f_e2" "nds32_n10_machine") ++(define_cpu_unit "n10f_e3" "nds32_n10_machine") ++(define_cpu_unit "n10f_e4" "nds32_n10_machine") ++ ++(define_insn_reservation "nds_n10_unknown" 1 ++ (and (eq_attr "type" "unknown") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_misc" 1 ++ (and (eq_attr "type" "misc") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_mmu" 1 ++ (and (eq_attr "type" "mmu") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_alu" 1 ++ (and (eq_attr "type" "alu") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_alu_shift" 1 ++ (and (eq_attr "type" "alu_shift") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_pbsad" 1 ++ (and (eq_attr "type" "pbsad") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex*3, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_pbsada" 1 ++ (and (eq_attr "type" "pbsada") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex*3, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_load" 1 ++ (and (match_test "nds32::load_single_p (insn)") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_store" 1 ++ (and (match_test "nds32::store_single_p (insn)") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_1" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "1"))) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_2" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (ior (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "2")) ++ (match_test "nds32::load_double_p (insn)"))) ++ "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_3" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "3"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_4" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "4"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ii+n10_ex+n10_mm+n10_wb, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_5" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "5"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*2, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_6" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "6"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*3, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_7" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "7"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*4, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_load_multiple_N" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "load_multiple") ++ (match_test "get_attr_combo (insn) >= 8"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*5, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_1" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "1"))) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_2" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (ior (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "2")) ++ (match_test "nds32::store_double_p (insn)"))) ++ "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_3" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "3"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_4" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "4"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ii+n10_ex+n10_mm+n10_wb, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_5" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "5"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*2, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_6" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "6"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*3, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_7" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "7"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*4, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_store_multiple_N" 1 ++ (and (eq_attr "pipeline_model" "n10") ++ (and (eq_attr "type" "store_multiple") ++ (match_test "get_attr_combo (insn) >= 8"))) ++ "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*5, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") ++ ++(define_insn_reservation "nds_n10_mul" 1 ++ (and (eq_attr "type" "mul") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_mac" 1 ++ (and (eq_attr "type" "mac") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_div" 1 ++ (and (eq_attr "type" "div") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex*34, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_branch" 1 ++ (and (eq_attr "type" "branch") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_alu" 1 ++ (and (eq_attr "type" "dalu") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_alu64" 1 ++ (and (eq_attr "type" "dalu64") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_alu_round" 1 ++ (and (eq_attr "type" "daluround") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_cmp" 1 ++ (and (eq_attr "type" "dcmp") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_clip" 1 ++ (and (eq_attr "type" "dclip") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_mul" 1 ++ (and (eq_attr "type" "dmul") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_mac" 1 ++ (and (eq_attr "type" "dmac") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_insb" 1 ++ (and (eq_attr "type" "dinsb") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_pack" 1 ++ (and (eq_attr "type" "dpack") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_bpick" 1 ++ (and (eq_attr "type" "dbpick") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_dsp_wext" 1 ++ (and (eq_attr "type" "dwext") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ex, n10_mm, n10_wb") ++ ++(define_insn_reservation "nds_n10_fpu_alu" 4 ++ (and (eq_attr "type" "falu") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_muls" 4 ++ (and (eq_attr "type" "fmuls") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_muld" 4 ++ (and (eq_attr "type" "fmuld") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*2, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_macs" 4 ++ (and (eq_attr "type" "fmacs") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*3, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_macd" 4 ++ (and (eq_attr "type" "fmacd") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*4, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_divs" 4 ++ (and (ior (eq_attr "type" "fdivs") ++ (eq_attr "type" "fsqrts")) ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*14, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_divd" 4 ++ (and (ior (eq_attr "type" "fdivd") ++ (eq_attr "type" "fsqrtd")) ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*28, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_fast_alu" 2 ++ (and (ior (eq_attr "type" "fcmp") ++ (ior (eq_attr "type" "fabs") ++ (ior (eq_attr "type" "fcpy") ++ (eq_attr "type" "fcmov")))) ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_fmtsr" 4 ++ (and (eq_attr "type" "fmtsr") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_fmtdr" 4 ++ (and (eq_attr "type" "fmtdr") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ii+n10f_iq, n10f_iq+n10f_rf, n10f_rf+n10f_e1, n10f_e1+n10f_e2, n10f_e2+n10f_e3, n10f_e3+n10f_e4, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_fmfsr" 2 ++ (and (eq_attr "type" "fmfsr") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_fmfdr" 2 ++ (and (eq_attr "type" "fmfdr") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10_ii+n10f_iq, n10f_iq+n10f_rf, n10f_rf+n10f_e1, n10f_e1+n10f_e2, n10f_e2+n10f_e3, n10f_e3+n10f_e4, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_load" 3 ++ (and (eq_attr "type" "fload") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") ++ ++(define_insn_reservation "nds_n10_fpu_store" 1 ++ (and (eq_attr "type" "fstore") ++ (eq_attr "pipeline_model" "n10")) ++ "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") ++ ++;; ------------------------------------------------------------------------ ++;; Comment Notations and Bypass Rules ++;; ------------------------------------------------------------------------ ++;; Producers (LHS) ++;; LD ++;; Load data from the memory and produce the loaded data. The result is ++;; ready at MM. ++;; LMW(N, M) ++;; There are N micro-operations within an instruction that loads multiple ++;; words. The result produced by the M-th micro-operation is sent to ++;; consumers. The result is ready at MM. ++;; MUL, MAC ++;; Compute data in the multiply-adder and produce the data. The result ++;; is ready at MM. ++;; DIV ++;; Compute data in the divider and produce the data. The result is ready ++;; at MM. ++;; ++;; Consumers (RHS) ++;; ALU, MOVD44, PBSAD, PBSADA_RaRb, MUL, MAC, DIV, MMU ++;; Require operands at EX. ++;; ALU_SHIFT_Rb ++;; An ALU-SHIFT instruction consists of a shift micro-operation followed ++;; by an arithmetic micro-operation. The operand Rb is used by the first ++;; micro-operation, and there are some latencies if data dependency occurs. ++;; MAC_RaRb ++;; A MAC instruction does multiplication at EX and does accumulation at MM, ++;; so the operand Rt is required at MM, and operands Ra and Rb are required ++;; at EX. ++;; ADDR_IN ++;; If an instruction requires an address as its input operand, the address ++;; is required at EX. ++;; ST ++;; A store instruction requires its data at MM. ++;; SMW(N, M) ++;; There are N micro-operations within an instruction that stores multiple ++;; words. Each M-th micro-operation requires its data at MM. ++;; BR ++;; If a branch instruction is conditional, its input data is required at EX. ++ ++;; FPU_ADDR_OUT -> FPU_ADDR_IN ++;; Main pipeline rules don't need this because those default latency is 1. ++(define_bypass 1 ++ "nds_n10_fpu_load, nds_n10_fpu_store" ++ "nds_n10_fpu_load, nds_n10_fpu_store" ++ "nds32_n10_ex_to_ex_p" ++) ++ ++;; LD, MUL, MAC, DIV, DALU64, DMUL, DMAC, DALUROUND, DBPICK, DWEXT ++;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU, ++;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb ++(define_bypass 2 ++ "nds_n10_load, nds_n10_mul, nds_n10_mac, nds_n10_div,\ ++ nds_n10_dsp_alu64, nds_n10_dsp_mul, nds_n10_dsp_mac,\ ++ nds_n10_dsp_alu_round, nds_n10_dsp_bpick, nds_n10_dsp_wext" ++ "nds_n10_alu, nds_n10_alu_shift,\ ++ nds_n10_pbsad, nds_n10_pbsada,\ ++ nds_n10_mul, nds_n10_mac, nds_n10_div,\ ++ nds_n10_branch,\ ++ nds_n10_load, nds_n10_store,\ ++ nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ ++ nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ ++ nds_n10_load_multiple_7, nds_n10_load_multiple_N,\ ++ nds_n10_store_multiple_1, nds_n10_store_multiple_2, nds_n10_store_multiple_3,\ ++ nds_n10_store_multiple_4, nds_n10_store_multiple_5, nds_n10_store_multiple_6,\ ++ nds_n10_store_multiple_7, nds_n10_store_multiple_N,\ ++ nds_n10_mmu,\ ++ nds_n10_dsp_alu, nds_n10_dsp_alu_round,\ ++ nds_n10_dsp_mul, nds_n10_dsp_mac, nds_n10_dsp_pack,\ ++ nds_n10_dsp_insb, nds_n10_dsp_cmp, nds_n10_dsp_clip,\ ++ nds_n10_dsp_wext, nds_n10_dsp_bpick" ++ "nds32_n10_mm_to_ex_p" ++) ++ ++;; LMW(N, N) ++;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU ++;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb ++(define_bypass 2 ++ "nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ ++ nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ ++ nds_n10_load_multiple_7, nds_n10_load_multiple_N" ++ "nds_n10_alu, nds_n10_alu_shift,\ ++ nds_n10_pbsad, nds_n10_pbsada,\ ++ nds_n10_mul, nds_n10_mac, nds_n10_div,\ ++ nds_n10_branch,\ ++ nds_n10_load, nds_n10_store,\ ++ nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ ++ nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ ++ nds_n10_load_multiple_7, nds_n10_load_multiple_N,\ ++ nds_n10_store_multiple_1, nds_n10_store_multiple_2, nds_n10_store_multiple_3,\ ++ nds_n10_store_multiple_4, nds_n10_store_multiple_5, nds_n10_store_multiple_6,\ ++ nds_n10_store_multiple_7, nds_n10_store_multiple_N,\ ++ nds_n10_mmu,\ ++ nds_n10_dsp_alu, nds_n10_dsp_alu_round,\ ++ nds_n10_dsp_mul, nds_n10_dsp_mac, nds_n10_dsp_pack,\ ++ nds_n10_dsp_insb, nds_n10_dsp_cmp, nds_n10_dsp_clip,\ ++ nds_n10_dsp_wext, nds_n10_dsp_bpick" ++ "nds32_n10_last_load_to_ex_p" ++) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-n13.md gcc-8.2.0/gcc/config/nds32/nds32-n13.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-n13.md 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-n13.md 2019-01-25 15:38:32.829242659 +0100 +@@ -0,0 +1,401 @@ ++;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler ++;; Copyright (C) 2012-2018 Free Software Foundation, Inc. ++;; Contributed by Andes Technology Corporation. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 3, or (at your ++;; option) any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++ ++;; ------------------------------------------------------------------------ ++;; Define N13 pipeline settings. ++;; ------------------------------------------------------------------------ ++ ++(define_automaton "nds32_n13_machine") ++ ++;; ------------------------------------------------------------------------ ++;; Pipeline Stages ++;; ------------------------------------------------------------------------ ++;; F1 - Instruction Fetch First ++;; Instruction Tag/Data Arrays ++;; ITLB Address Translation ++;; Branch Target Buffer Prediction ++;; F2 - Instruction Fetch Second ++;; Instruction Cache Hit Detection ++;; Cache Way Selection ++;; Inustruction Alignment ++;; I1 - Instruction Issue First / Instruction Decode ++;; Instruction Cache Replay Triggering ++;; 32/16-Bit Instruction Decode ++;; Return Address Stack Prediction ++;; I2 - Instruction Issue Second / Register File Access ++;; Instruction Issue Logic ++;; Register File Access ++;; E1 - Instruction Execute First / Address Generation / MAC First ++;; Data Access Address generation ++;; Multiply Operation ++;; E2 - Instruction Execute Second / Data Access First / MAC Second / ++;; ALU Execute ++;; Skewed ALU ++;; Branch/Jump/Return Resolution ++;; Data Tag/Data arrays ++;; DTLB address translation ++;; Accumulation Operation ++;; E3 - Instruction Execute Third / Data Access Second ++;; Data Cache Hit Detection ++;; Cache Way Selection ++;; Data Alignment ++;; E4 - Instruction Execute Fourth / Write Back ++;; Interruption Resolution ++;; Instruction Retire ++;; Register File Write Back ++ ++(define_cpu_unit "n13_i1" "nds32_n13_machine") ++(define_cpu_unit "n13_i2" "nds32_n13_machine") ++(define_cpu_unit "n13_e1" "nds32_n13_machine") ++(define_cpu_unit "n13_e2" "nds32_n13_machine") ++(define_cpu_unit "n13_e3" "nds32_n13_machine") ++(define_cpu_unit "n13_e4" "nds32_n13_machine") ++ ++(define_insn_reservation "nds_n13_unknown" 1 ++ (and (eq_attr "type" "unknown") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_misc" 1 ++ (and (eq_attr "type" "misc") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_mmu" 1 ++ (and (eq_attr "type" "mmu") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_alu" 1 ++ (and (eq_attr "type" "alu") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_alu_shift" 1 ++ (and (eq_attr "type" "alu_shift") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_pbsad" 1 ++ (and (eq_attr "type" "pbsad") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2*2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_pbsada" 1 ++ (and (eq_attr "type" "pbsada") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2*3, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_load" 1 ++ (and (match_test "nds32::load_single_p (insn)") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_store" 1 ++ (and (match_test "nds32::store_single_p (insn)") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_1" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "1")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_2" 1 ++ (and (ior (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "2")) ++ (match_test "nds32::load_double_p (insn)")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_3" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "3")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_4" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "4")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_5" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "5")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_6" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "6")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_7" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "7")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_8" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "8")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_load_multiple_12" 1 ++ (and (and (eq_attr "type" "load_multiple") ++ (eq_attr "combo" "12")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_1" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "1")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_2" 1 ++ (and (ior (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "2")) ++ (match_test "nds32::store_double_p (insn)")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_3" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "3")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_4" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "4")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_5" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "5")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_6" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "6")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_7" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "7")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_8" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "8")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++(define_insn_reservation "nds_n13_store_multiple_12" 1 ++ (and (and (eq_attr "type" "store_multiple") ++ (eq_attr "combo" "12")) ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4") ++ ++;; The multiplier at E1 takes two cycles. ++(define_insn_reservation "nds_n13_mul" 1 ++ (and (eq_attr "type" "mul") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_mac" 1 ++ (and (eq_attr "type" "mac") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4") ++ ++;; The cycles consumed at E2 are 32 - CLZ(abs(Ra)) + 2, ++;; so the worst case is 34. ++(define_insn_reservation "nds_n13_div" 1 ++ (and (eq_attr "type" "div") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2*34, n13_e3, n13_e4") ++ ++(define_insn_reservation "nds_n13_branch" 1 ++ (and (eq_attr "type" "branch") ++ (eq_attr "pipeline_model" "n13")) ++ "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4") ++ ++;; ------------------------------------------------------------------------ ++;; Comment Notations and Bypass Rules ++;; ------------------------------------------------------------------------ ++;; Producers (LHS) ++;; LD ++;; Load data from the memory and produce the loaded data. The result is ++;; ready at E3. ++;; LMW(N, M) ++;; There are N micro-operations within an instruction that loads multiple ++;; words. The result produced by the M-th micro-operation is sent to ++;; consumers. The result is ready at E3. ++;; ADDR_OUT ++;; Most load/store instructions can produce an address output if updating ++;; the base register is required. The result is ready at E2, which is ++;; produced by ALU. ++;; ALU, ALU_SHIFT, SIMD ++;; Compute data in ALU and produce the data. The result is ready at E2. ++;; MUL, MAC ++;; Compute data in the multiply-adder and produce the data. The result ++;; is ready at E2. ++;; DIV ++;; Compute data in the divider and produce the data. The result is ready ++;; at E2. ++;; BR ++;; Branch-with-link instructions produces a result containing the return ++;; address. The result is ready at E2. ++;; ++;; Consumers (RHS) ++;; ALU ++;; General ALU instructions require operands at E2. ++;; ALU_E1 ++;; Some special ALU instructions, such as BSE, BSP and MOVD44, require ++;; operand at E1. ++;; MUL, DIV, PBSAD, MMU ++;; Operands are required at E1. ++;; PBSADA_Rt, PBSADA_RaRb ++;; Operands Ra and Rb are required at E1, and the operand Rt is required ++;; at E2. ++;; ALU_SHIFT_Rb ++;; An ALU-SHIFT instruction consists of a shift micro-operation followed ++;; by an arithmetic micro-operation. The operand Rb is used by the first ++;; micro-operation, and there are some latencies if data dependency occurs. ++;; MAC_RaRb ++;; A MAC instruction does multiplication at E1 and does accumulation at E2, ++;; so the operand Rt is required at E2, and operands Ra and Rb are required ++;; at E1. ++;; ADDR_IN ++;; If an instruction requires an address as its input operand, the address ++;; is required at E1. ++;; ST ++;; A store instruction requires its data at E2. ++;; SMW(N, M) ++;; There are N micro-operations within an instruction that stores multiple ++;; words. Each M-th micro-operation requires its data at E2. ++;; BR ++;; If a branch instruction is conditional, its input data is required at E2. ++ ++;; LD -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN ++(define_bypass 3 ++ "nds_n13_load" ++ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ ++ nds_n13_mul, nds_n13_mac, nds_n13_div,\ ++ nds_n13_mmu,\ ++ nds_n13_load, nds_n13_store,\ ++ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ ++ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ ++ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ ++ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" ++ "nds32_n13_load_to_e1_p" ++) ++ ++;; LD -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1) ++(define_bypass 2 ++ "nds_n13_load" ++ "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\ ++ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ ++ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ ++ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" ++ "nds32_n13_load_to_e2_p" ++) ++ ++;; LMW(N, N) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN ++(define_bypass 3 ++ "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12" ++ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ ++ nds_n13_mul, nds_n13_mac, nds_n13_div,\ ++ nds_n13_mmu,\ ++ nds_n13_load, nds_n13_store,\ ++ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ ++ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ ++ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ ++ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" ++ "nds32_n13_last_load_to_e1_p") ++ ++;; LMW(N, N) -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1) ++(define_bypass 2 ++ "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12" ++ "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\ ++ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ ++ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ ++ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" ++ "nds32_n13_last_load_to_e2_p" ++) ++ ++;; LMW(N, N - 1) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN ++(define_bypass 2 ++ "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12" ++ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ ++ nds_n13_mul, nds_n13_mac, nds_n13_div,\ ++ nds_n13_mmu,\ ++ nds_n13_load, nds_n13_store,\ ++ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ ++ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ ++ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ ++ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" ++ "nds32_n13_last_two_load_to_e1_p") ++ ++;; ALU, ALU_SHIFT, SIMD, BR, MUL, MAC, DIV, ADDR_OUT ++;; -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN ++(define_bypass 2 ++ "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsad, nds_n13_pbsada, nds_n13_branch,\ ++ nds_n13_mul, nds_n13_mac, nds_n13_div,\ ++ nds_n13_load, nds_n13_store,\ ++ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ ++ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ ++ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ ++ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" ++ "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\ ++ nds_n13_mul, nds_n13_mac, nds_n13_div,\ ++ nds_n13_mmu,\ ++ nds_n13_load, nds_n13_store,\ ++ nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\ ++ nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\ ++ nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\ ++ nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\ ++ nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\ ++ nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12" ++ "nds32_n13_e2_to_e1_p") +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32.opt gcc-8.2.0/gcc/config/nds32/nds32.opt +--- gcc-8.2.0.orig/gcc/config/nds32/nds32.opt 2018-04-22 12:10:00.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32.opt 2019-01-25 15:38:32.833242671 +0100 +@@ -32,6 +32,13 @@ + Target RejectNegative Alias(mlittle-endian) + Generate code in little-endian mode. + ++mfp-as-gp ++Target RejectNegative Alias(mforce-fp-as-gp) ++Force performing fp-as-gp optimization. ++ ++mno-fp-as-gp ++Target RejectNegative Alias(mforbid-fp-as-gp) ++Forbid performing fp-as-gp optimization. + + ; --------------------------------------------------------------- + +@@ -85,11 +92,36 @@ + Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN) + Generate code in little-endian mode. + ++mforce-fp-as-gp ++Target Undocumented Mask(FORCE_FP_AS_GP) ++Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization. ++ ++mforbid-fp-as-gp ++Target Undocumented Mask(FORBID_FP_AS_GP) ++Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'. ++ ++mict-model= ++Target Undocumented RejectNegative Joined Enum(nds32_ict_model_type) Var(nds32_ict_model) Init(ICT_MODEL_SMALL) ++Specify the address generation strategy for ICT call's code model. ++ ++Enum ++Name(nds32_ict_model_type) Type(enum nds32_ict_model_type) ++Known cmodel types (for use with the -mict-model= option): ++ ++EnumValue ++Enum(nds32_ict_model_type) String(small) Value(ICT_MODEL_SMALL) ++ ++EnumValue ++Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE) + + mcmov + Target Report Mask(CMOV) + Generate conditional move instructions. + ++mhw-abs ++Target Report Mask(HW_ABS) ++Generate hardware abs instructions. ++ + mext-perf + Target Report Mask(EXT_PERF) + Generate performance extension instructions. +@@ -102,6 +134,10 @@ + Target Report Mask(EXT_STRING) + Generate string extension instructions. + ++mext-dsp ++Target Report Mask(EXT_DSP) ++Generate DSP extension instructions. ++ + mv3push + Target Report Mask(V3PUSH) + Generate v3 push25/pop25 instructions. +@@ -115,13 +151,17 @@ + Insert relax hint for linker to do relaxation. + + mvh +-Target Report Mask(VH) ++Target Report Mask(VH) Condition(!TARGET_LINUX_ABI) + Enable Virtual Hosting support. + + misr-vector-size= + Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE) + Specify the size of each interrupt vector, which must be 4 or 16. + ++misr-secure= ++Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0) ++Specify the security level of c-isr for the whole file. ++ + mcache-block-size= + Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE) + Specify the size of each cache block, which must be a power of 2 between 4 and 512. +@@ -141,6 +181,9 @@ + Enum(nds32_arch_type) String(v3) Value(ARCH_V3) + + EnumValue ++Enum(nds32_arch_type) String(v3j) Value(ARCH_V3J) ++ ++EnumValue + Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M) + + EnumValue +@@ -149,23 +192,6 @@ + EnumValue + Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S) + +-mcmodel= +-Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_LARGE) +-Specify the address generation strategy for code model. +- +-Enum +-Name(nds32_cmodel_type) Type(enum nds32_cmodel_type) +-Known cmodel types (for use with the -mcmodel= option): +- +-EnumValue +-Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL) +- +-EnumValue +-Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM) +- +-EnumValue +-Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE) +- + mcpu= + Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9) + Specify the cpu for pipeline model. +@@ -235,6 +261,99 @@ + Enum(nds32_cpu_type) String(n968a) Value(CPU_N9) + + EnumValue ++Enum(nds32_cpu_type) String(n10) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1033) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1033a) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1033-fpu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1033-spu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1068) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1068a) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1068-fpu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1068a-fpu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1068-spu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1068a-spu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(d10) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(d1088) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10) ++ ++EnumValue ++Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF) ++ ++EnumValue ++Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF) ++ ++EnumValue ++Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF) ++ ++EnumValue ++Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n12) Value(CPU_N12) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1213) Value(CPU_N12) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1233) Value(CPU_N12) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1233-fpu) Value(CPU_N12) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1233-spu) Value(CPU_N12) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n13) Value(CPU_N13) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1337) Value(CPU_N13) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1337-fpu) Value(CPU_N13) ++ ++EnumValue ++Enum(nds32_cpu_type) String(n1337-spu) Value(CPU_N13) ++ ++EnumValue + Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE) + + mconfig-fpu= +@@ -321,6 +440,18 @@ + Target Report Mask(FPU_DOUBLE) + Generate double-precision floating-point instructions. + ++mforce-no-ext-dsp ++Target Undocumented Report Mask(FORCE_NO_EXT_DSP) ++Force disable hardware loop, even use -mext-dsp. ++ ++msched-prolog-epilog ++Target Var(flag_sched_prolog_epilog) Init(0) ++Permit scheduling of a function's prologue and epilogue sequence. ++ ++mret-in-naked-func ++Target Var(flag_ret_in_naked_func) Init(1) ++Generate return instruction in naked function. ++ + malways-save-lp + Target Var(flag_always_save_lp) Init(0) + Always save $lp in the stack. +@@ -328,3 +459,7 @@ + munaligned-access + Target Report Var(flag_unaligned_access) Init(0) + Enable unaligned word and halfword accesses to packed data. ++ ++minline-asm-r15 ++Target Report Var(flag_inline_asm_r15) Init(0) ++Allow use r15 for inline ASM. +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-opts.h gcc-8.2.0/gcc/config/nds32/nds32-opts.h +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-opts.h 2018-04-08 11:21:30.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-opts.h 2019-01-25 15:38:32.833242671 +0100 +@@ -29,6 +29,7 @@ + { + ARCH_V2, + ARCH_V3, ++ ARCH_V3J, + ARCH_V3M, + ARCH_V3F, + ARCH_V3S +@@ -42,6 +43,10 @@ + CPU_N8, + CPU_E8, + CPU_N9, ++ CPU_N10, ++ CPU_GRAYWOLF, ++ CPU_N12, ++ CPU_N13, + CPU_SIMPLE + }; + +@@ -53,6 +58,13 @@ + CMODEL_LARGE + }; + ++/* The code model defines the address generation strategy. */ ++enum nds32_ict_model_type ++{ ++ ICT_MODEL_SMALL, ++ ICT_MODEL_LARGE ++}; ++ + /* Multiply instruction configuration. */ + enum nds32_mul_type + { +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-peephole2.md gcc-8.2.0/gcc/config/nds32/nds32-peephole2.md +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-peephole2.md 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/nds32-peephole2.md 2019-01-25 15:38:32.833242671 +0100 +@@ -22,3 +22,139 @@ + ;; Use define_peephole2 to handle possible target-specific optimization. + + ;; ------------------------------------------------------------------------ ++;; Try to utilize 16-bit instruction by swap operand if possible. ++;; ------------------------------------------------------------------------ ++ ++;; Try to make add as add45. ++(define_peephole2 ++ [(set (match_operand:QIHISI 0 "register_operand" "") ++ (plus:QIHISI (match_operand:QIHISI 1 "register_operand" "") ++ (match_operand:QIHISI 2 "register_operand" "")))] ++ "reload_completed ++ && TARGET_16_BIT ++ && REGNO (operands[0]) == REGNO (operands[2]) ++ && REGNO (operands[0]) != REGNO (operands[1]) ++ && TEST_HARD_REG_BIT (reg_class_contents[MIDDLE_REGS], REGNO (operands[0]))" ++ [(set (match_dup 0) (plus:QIHISI (match_dup 2) (match_dup 1)))]) ++ ++;; Try to make xor/ior/and/mult as xor33/ior33/and33/mult33. ++(define_peephole2 ++ [(set (match_operand:SI 0 "register_operand" "") ++ (match_operator:SI 1 "nds32_have_33_inst_operator" ++ [(match_operand:SI 2 "register_operand" "") ++ (match_operand:SI 3 "register_operand" "")]))] ++ "reload_completed ++ && TARGET_16_BIT ++ && REGNO (operands[0]) == REGNO (operands[3]) ++ && REGNO (operands[0]) != REGNO (operands[2]) ++ && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[0])) ++ && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[2]))" ++ [(set (match_dup 0) (match_op_dup 1 [(match_dup 3) (match_dup 2)]))]) ++ ++(define_peephole ++ [(set (match_operand:SI 0 "register_operand" "") ++ (match_operand:SI 1 "register_operand" "")) ++ (set (match_operand:SI 2 "register_operand" "") ++ (match_operand:SI 3 "register_operand" ""))] ++ "TARGET_16_BIT ++ && !TARGET_ISA_V2 ++ && NDS32_IS_GPR_REGNUM (REGNO (operands[0])) ++ && NDS32_IS_GPR_REGNUM (REGNO (operands[1])) ++ && ((REGNO (operands[0]) & 0x1) == 0) ++ && ((REGNO (operands[1]) & 0x1) == 0) ++ && (REGNO (operands[0]) + 1) == REGNO (operands[2]) ++ && (REGNO (operands[1]) + 1) == REGNO (operands[3])" ++ "movd44\t%0, %1" ++ [(set_attr "type" "alu") ++ (set_attr "length" "2")]) ++ ++;; Merge two fcpyss to fcpysd. ++(define_peephole2 ++ [(set (match_operand:SF 0 "float_even_register_operand" "") ++ (match_operand:SF 1 "float_even_register_operand" "")) ++ (set (match_operand:SF 2 "float_odd_register_operand" "") ++ (match_operand:SF 3 "float_odd_register_operand" ""))] ++ "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ++ && REGNO (operands[0]) == REGNO (operands[2]) - 1 ++ && REGNO (operands[1]) == REGNO (operands[3]) - 1" ++ [(set (match_dup 4) (match_dup 5))] ++ { ++ operands[4] = gen_rtx_REG (DFmode, REGNO (operands[0])); ++ operands[5] = gen_rtx_REG (DFmode, REGNO (operands[1])); ++ }) ++ ++(define_peephole2 ++ [(set (match_operand:SF 0 "float_odd_register_operand" "") ++ (match_operand:SF 1 "float_odd_register_operand" "")) ++ (set (match_operand:SF 2 "float_even_register_operand" "") ++ (match_operand:SF 3 "float_even_register_operand" ""))] ++ "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ++ && REGNO (operands[2]) == REGNO (operands[0]) - 1 ++ && REGNO (operands[3]) == REGNO (operands[1]) - 1" ++ [(set (match_dup 4) (match_dup 5))] ++ { ++ operands[4] = gen_rtx_REG (DFmode, REGNO (operands[2])); ++ operands[5] = gen_rtx_REG (DFmode, REGNO (operands[3])); ++ }) ++ ++;; ------------------------------------------------------------------------ ++;; GCC will prefer [u]divmodsi3 rather than [u]divsi3 even remainder is ++;; unused, so we use split to drop mod operation for lower register pressure. ++ ++(define_split ++ [(set (match_operand:SI 0 "register_operand") ++ (div:SI (match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "register_operand"))) ++ (set (match_operand:SI 3 "register_operand") ++ (mod:SI (match_dup 1) (match_dup 2)))] ++ "find_regno_note (insn, REG_UNUSED, REGNO (operands[3])) != NULL ++ && can_create_pseudo_p ()" ++ [(set (match_dup 0) ++ (div:SI (match_dup 1) ++ (match_dup 2)))]) ++ ++(define_split ++ [(set (match_operand:SI 0 "register_operand") ++ (udiv:SI (match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "register_operand"))) ++ (set (match_operand:SI 3 "register_operand") ++ (umod:SI (match_dup 1) (match_dup 2)))] ++ "find_regno_note (insn, REG_UNUSED, REGNO (operands[3])) != NULL ++ && can_create_pseudo_p ()" ++ [(set (match_dup 0) ++ (udiv:SI (match_dup 1) ++ (match_dup 2)))]) ++ ++(define_peephole2 ++ [(set (match_operand:DI 0 "register_operand") ++ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand")) ++ (sign_extend:DI (match_operand:SI 2 "register_operand"))))] ++ "NDS32_EXT_DSP_P () ++ && peep2_regno_dead_p (1, WORDS_BIG_ENDIAN ? REGNO (operands[0]) + 1 : REGNO (operands[0]))" ++ [(const_int 1)] ++{ ++ rtx highpart = nds32_di_high_part_subreg (operands[0]); ++ emit_insn (gen_smulsi3_highpart (highpart, operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_split ++ [(set (match_operand:DI 0 "nds32_general_register_operand" "") ++ (match_operand:DI 1 "nds32_general_register_operand" ""))] ++ "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) != NULL ++ || find_regno_note (insn, REG_UNUSED, REGNO (operands[0]) + 1) != NULL" ++ [(set (match_dup 0) (match_dup 1))] ++{ ++ rtx dead_note = find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0])); ++ HOST_WIDE_INT offset; ++ if (dead_note == NULL_RTX) ++ offset = 0; ++ else ++ offset = 4; ++ operands[0] = simplify_gen_subreg ( ++ SImode, operands[0], ++ DImode, offset); ++ operands[1] = simplify_gen_subreg ( ++ SImode, operands[1], ++ DImode, offset); ++}) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-pipelines-auxiliary.c gcc-8.2.0/gcc/config/nds32/nds32-pipelines-auxiliary.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-pipelines-auxiliary.c 2018-04-08 11:21:30.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-pipelines-auxiliary.c 2019-01-25 15:38:32.833242671 +0100 +@@ -306,6 +306,19 @@ + return false; + } + ++/* Determine if the latency is occured when the consumer PBSADA_INSN uses the ++ value of DEF_REG in its Rt field. */ ++bool ++pbsada_insn_rt_dep_reg_p (rtx pbsada_insn, rtx def_reg) ++{ ++ rtx pbsada_rt = SET_DEST (PATTERN (pbsada_insn)); ++ ++ if (rtx_equal_p (def_reg, pbsada_rt)) ++ return true; ++ ++ return false; ++} ++ + /* Check if INSN is a movd44 insn consuming DEF_REG. */ + bool + movd44_even_dep_p (rtx_insn *insn, rtx def_reg) +@@ -335,6 +348,103 @@ + return false; + } + ++/* Check if INSN is a wext insn consuming DEF_REG. */ ++bool ++wext_odd_dep_p (rtx insn, rtx def_reg) ++{ ++ rtx shift_rtx = XEXP (SET_SRC (PATTERN (insn)), 0); ++ rtx use_reg = XEXP (shift_rtx, 0); ++ rtx pos_rtx = XEXP (shift_rtx, 1); ++ ++ if (REG_P (pos_rtx) && reg_overlap_p (def_reg, pos_rtx)) ++ return true; ++ ++ if (GET_MODE (def_reg) == DImode) ++ return reg_overlap_p (def_reg, use_reg); ++ ++ gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG); ++ gcc_assert (REG_P (use_reg)); ++ ++ if (REG_P (def_reg)) ++ { ++ if (!TARGET_BIG_ENDIAN) ++ return REGNO (def_reg) == REGNO (use_reg) + 1; ++ else ++ return REGNO (def_reg) == REGNO (use_reg); ++ } ++ ++ if (GET_CODE (def_reg) == SUBREG) ++ { ++ if (!reg_overlap_p (def_reg, use_reg)) ++ return false; ++ ++ if (!TARGET_BIG_ENDIAN) ++ return SUBREG_BYTE (def_reg) == 4; ++ else ++ return SUBREG_BYTE (def_reg) == 0; ++ } ++ ++ return false; ++} ++ ++/* Check if INSN is a bpick insn consuming DEF_REG. */ ++bool ++bpick_ra_rb_dep_p (rtx insn, rtx def_reg) ++{ ++ rtx ior_rtx = SET_SRC (PATTERN (insn)); ++ rtx and1_rtx = XEXP (ior_rtx, 0); ++ rtx and2_rtx = XEXP (ior_rtx, 1); ++ rtx reg1_0 = XEXP (and1_rtx, 0); ++ rtx reg1_1 = XEXP (and1_rtx, 1); ++ rtx reg2_0 = XEXP (and2_rtx, 0); ++ rtx reg2_1 = XEXP (and2_rtx, 1); ++ ++ if (GET_CODE (reg1_0) == NOT) ++ { ++ if (rtx_equal_p (reg1_0, reg2_0)) ++ return reg_overlap_p (def_reg, reg1_1) ++ || reg_overlap_p (def_reg, reg2_1); ++ ++ if (rtx_equal_p (reg1_0, reg2_1)) ++ return reg_overlap_p (def_reg, reg1_1) ++ || reg_overlap_p (def_reg, reg2_0); ++ } ++ ++ if (GET_CODE (reg1_1) == NOT) ++ { ++ if (rtx_equal_p (reg1_1, reg2_0)) ++ return reg_overlap_p (def_reg, reg1_0) ++ || reg_overlap_p (def_reg, reg2_1); ++ ++ if (rtx_equal_p (reg1_1, reg2_1)) ++ return reg_overlap_p (def_reg, reg1_0) ++ || reg_overlap_p (def_reg, reg2_0); ++ } ++ ++ if (GET_CODE (reg2_0) == NOT) ++ { ++ if (rtx_equal_p (reg2_0, reg1_0)) ++ return reg_overlap_p (def_reg, reg2_1) ++ || reg_overlap_p (def_reg, reg1_1); ++ ++ if (rtx_equal_p (reg2_0, reg1_1)) ++ return reg_overlap_p (def_reg, reg2_1) ++ || reg_overlap_p (def_reg, reg1_0); ++ } ++ ++ if (GET_CODE (reg2_1) == NOT) ++ { ++ if (rtx_equal_p (reg2_1, reg1_0)) ++ return reg_overlap_p (def_reg, reg2_0) ++ || reg_overlap_p (def_reg, reg1_1); ++ ++ if (rtx_equal_p (reg2_1, reg1_1)) ++ return reg_overlap_p (def_reg, reg2_0) ++ || reg_overlap_p (def_reg, reg1_0); ++ } ++ ++ gcc_unreachable (); ++} + } // namespace scheduling + } // namespace nds32 + +@@ -375,8 +485,7 @@ + operations in order to write two registers. We have to check the + dependency from the producer to the first micro-operation. */ + case TYPE_DIV: +- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 +- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) ++ if (divmod_p (consumer)) + use_rtx = SET_SRC (parallel_element (consumer, 0)); + else + use_rtx = SET_SRC (PATTERN (consumer)); +@@ -506,8 +615,7 @@ + operations in order to write two registers. We have to check the + dependency from the producer to the first micro-operation. */ + case TYPE_DIV: +- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 +- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) ++ if (divmod_p (consumer)) + use_rtx = SET_SRC (parallel_element (consumer, 0)); + else + use_rtx = SET_SRC (PATTERN (consumer)); +@@ -606,8 +714,7 @@ + break; + + case TYPE_DIV: +- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 +- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) ++ if (divmod_p (consumer)) + use_rtx = SET_SRC (parallel_element (consumer, 0)); + else + use_rtx = SET_SRC (PATTERN (consumer)); +@@ -706,13 +813,175 @@ + We have to check the dependency from the producer to the first + micro-operation. */ + case TYPE_DIV: +- if (INSN_CODE (consumer) == CODE_FOR_divmodsi4 +- || INSN_CODE (consumer) == CODE_FOR_udivmodsi4) ++ if (divmod_p (consumer)) ++ use_rtx = SET_SRC (parallel_element (consumer, 0)); ++ else ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ break; ++ ++ case TYPE_MMU: ++ if (GET_CODE (PATTERN (consumer)) == SET) ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ else ++ return true; ++ break; ++ ++ case TYPE_LOAD: ++ case TYPE_STORE: ++ use_rtx = extract_mem_rtx (consumer); ++ break; ++ ++ case TYPE_LOAD_MULTIPLE: ++ case TYPE_STORE_MULTIPLE: ++ use_rtx = extract_base_reg (consumer); ++ break; ++ ++ case TYPE_BRANCH: ++ use_rtx = PATTERN (consumer); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (reg_overlap_p (def_reg, use_rtx)) ++ return true; ++ ++ return false; ++} ++ ++/* Check the dependency between the producer defining DEF_REG and CONSUMER ++ requiring input operand at EX. */ ++bool ++n10_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg) ++{ ++ rtx use_rtx; ++ ++ switch (get_attr_type (consumer)) ++ { ++ case TYPE_ALU: ++ case TYPE_PBSAD: ++ case TYPE_MUL: ++ case TYPE_DALU: ++ case TYPE_DALU64: ++ case TYPE_DMUL: ++ case TYPE_DPACK: ++ case TYPE_DINSB: ++ case TYPE_DCMP: ++ case TYPE_DCLIP: ++ case TYPE_DALUROUND: ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ break; ++ ++ case TYPE_ALU_SHIFT: ++ use_rtx = extract_shift_reg (consumer); ++ break; ++ ++ case TYPE_PBSADA: ++ return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg); ++ ++ case TYPE_MAC: ++ case TYPE_DMAC: ++ use_rtx = extract_mac_non_acc_rtx (consumer); ++ break; ++ ++ /* Some special instructions, divmodsi4 and udivmodsi4, produce two ++ results, the quotient and the remainder. */ ++ case TYPE_DIV: ++ if (divmod_p (consumer)) ++ use_rtx = SET_SRC (parallel_element (consumer, 0)); ++ else ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ break; ++ ++ case TYPE_DWEXT: ++ return wext_odd_dep_p (consumer, def_reg); ++ ++ case TYPE_DBPICK: ++ return bpick_ra_rb_dep_p (consumer, def_reg); ++ ++ case TYPE_MMU: ++ if (GET_CODE (PATTERN (consumer)) == SET) ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ else ++ return true; ++ break; ++ ++ case TYPE_LOAD: ++ case TYPE_STORE: ++ use_rtx = extract_mem_rtx (consumer); ++ break; ++ ++ case TYPE_LOAD_MULTIPLE: ++ case TYPE_STORE_MULTIPLE: ++ use_rtx = extract_base_reg (consumer); ++ break; ++ ++ case TYPE_BRANCH: ++ use_rtx = PATTERN (consumer); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (reg_overlap_p (def_reg, use_rtx)) ++ return true; ++ ++ return false; ++} ++ ++/* Check the dependency between the producer defining DEF_REG and CONSUMER ++ requiring input operand at EX. */ ++bool ++gw_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg) ++{ ++ rtx use_rtx; ++ ++ switch (get_attr_type (consumer)) ++ { ++ case TYPE_ALU: ++ case TYPE_PBSAD: ++ case TYPE_MUL: ++ case TYPE_DALU: ++ case TYPE_DALU64: ++ case TYPE_DMUL: ++ case TYPE_DPACK: ++ case TYPE_DINSB: ++ case TYPE_DCMP: ++ case TYPE_DCLIP: ++ case TYPE_DALUROUND: ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ break; ++ ++ case TYPE_ALU_SHIFT: ++ use_rtx = extract_shift_reg (consumer); ++ break; ++ ++ case TYPE_PBSADA: ++ return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg); ++ ++ case TYPE_MAC: ++ case TYPE_DMAC: ++ use_rtx = extract_mac_non_acc_rtx (consumer); ++ break; ++ ++ /* Some special instructions, divmodsi4 and udivmodsi4, produce two ++ results, the quotient and the remainder. We have to check the ++ dependency from the producer to the first micro-operation. */ ++ case TYPE_DIV: ++ if (divmod_p (consumer)) + use_rtx = SET_SRC (parallel_element (consumer, 0)); + else + use_rtx = SET_SRC (PATTERN (consumer)); + break; + ++ case TYPE_DWEXT: ++ return wext_odd_dep_p (consumer, def_reg); ++ ++ case TYPE_DBPICK: ++ return bpick_ra_rb_dep_p (consumer, def_reg); ++ + case TYPE_MMU: + if (GET_CODE (PATTERN (consumer)) == SET) + use_rtx = SET_SRC (PATTERN (consumer)); +@@ -744,7 +1013,153 @@ + return false; + } + ++/* Check dependencies from any stages to ALU_E1 (E1). This is a helper ++ function of n13_consumed_by_e1_dep_p (). */ ++bool ++n13_alu_e1_insn_dep_reg_p (rtx_insn *alu_e1_insn, rtx def_reg) ++{ ++ rtx unspec_rtx, operand_ra, operand_rb; ++ rtx src_rtx, dst_rtx; ++ ++ switch (INSN_CODE (alu_e1_insn)) ++ { ++ /* BSP and BSE are supported by built-in functions, the corresponding ++ patterns are formed by UNSPEC RTXs. We have to handle them ++ individually. */ ++ case CODE_FOR_unspec_bsp: ++ case CODE_FOR_unspec_bse: ++ unspec_rtx = SET_SRC (parallel_element (alu_e1_insn, 0)); ++ gcc_assert (GET_CODE (unspec_rtx) == UNSPEC); ++ ++ operand_ra = XVECEXP (unspec_rtx, 0, 0); ++ operand_rb = XVECEXP (unspec_rtx, 0, 1); ++ ++ if (rtx_equal_p (def_reg, operand_ra) ++ || rtx_equal_p (def_reg, operand_rb)) ++ return true; ++ ++ return false; ++ ++ /* Unlink general ALU instructions, MOVD44 requires operands at E1. */ ++ case CODE_FOR_move_di: ++ case CODE_FOR_move_df: ++ src_rtx = SET_SRC (PATTERN (alu_e1_insn)); ++ dst_rtx = SET_DEST (PATTERN (alu_e1_insn)); ++ ++ if (REG_P (dst_rtx) && REG_P (src_rtx) ++ && rtx_equal_p (src_rtx, def_reg)) ++ return true; ++ ++ return false; ++ ++ default: ++ return false; ++ } ++} ++ ++/* Check the dependency between the producer defining DEF_REG and CONSUMER ++ requiring input operand at E1. Because the address generation unti is ++ at E1, the address input should be ready at E1. Note that the branch ++ target is also a kind of addresses, so we have to check it. */ ++bool ++n13_consumed_by_e1_dep_p (rtx_insn *consumer, rtx def_reg) ++{ ++ rtx use_rtx; ++ ++ switch (get_attr_type (consumer)) ++ { ++ /* ALU_E1 */ ++ case TYPE_ALU: ++ return n13_alu_e1_insn_dep_reg_p (consumer, def_reg); ++ ++ case TYPE_PBSADA: ++ return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg); ++ ++ case TYPE_PBSAD: ++ case TYPE_MUL: ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ break; ++ ++ case TYPE_MAC: ++ use_rtx = extract_mac_non_acc_rtx (consumer); ++ break; ++ ++ case TYPE_DIV: ++ if (divmod_p (consumer)) ++ use_rtx = SET_SRC (parallel_element (consumer, 0)); ++ else ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ break; ++ ++ case TYPE_MMU: ++ if (GET_CODE (PATTERN (consumer)) == SET) ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ else ++ return true; ++ break; ++ ++ case TYPE_BRANCH: ++ use_rtx = extract_branch_target_rtx (consumer); ++ break; ++ ++ case TYPE_LOAD: ++ case TYPE_STORE: ++ use_rtx = extract_mem_rtx (consumer); ++ break; ++ ++ case TYPE_LOAD_MULTIPLE: ++ case TYPE_STORE_MULTIPLE: ++ use_rtx = extract_base_reg (consumer); ++ break; ++ ++ default: ++ return false; ++ } ++ ++ if (reg_overlap_p (def_reg, use_rtx)) ++ return true; ++ ++ return false; ++} ++ ++/* Check the dependency between the producer defining DEF_REG and CONSUMER ++ requiring input operand at E2. */ ++bool ++n13_consumed_by_e2_dep_p (rtx_insn *consumer, rtx def_reg) ++{ ++ rtx use_rtx; ++ ++ switch (get_attr_type (consumer)) ++ { ++ case TYPE_ALU: ++ case TYPE_STORE: ++ use_rtx = SET_SRC (PATTERN (consumer)); ++ break; ++ ++ case TYPE_ALU_SHIFT: ++ use_rtx = extract_shift_reg (consumer); ++ break; ++ ++ case TYPE_PBSADA: ++ return pbsada_insn_rt_dep_reg_p (consumer, def_reg); ++ ++ case TYPE_STORE_MULTIPLE: ++ use_rtx = extract_nth_access_rtx (consumer, 0); ++ break; ++ ++ case TYPE_BRANCH: ++ use_rtx = extract_branch_condition_rtx (consumer); ++ break; ++ ++ default: ++ gcc_unreachable(); ++ } ++ ++ if (reg_overlap_p (def_reg, use_rtx)) ++ return true; + ++ return false; ++} + } // anonymous namespace + + /* ------------------------------------------------------------------------ */ +@@ -837,8 +1252,7 @@ + break; + + case TYPE_DIV: +- if (INSN_CODE (producer) == CODE_FOR_divmodsi4 +- || INSN_CODE (producer) == CODE_FOR_udivmodsi4) ++ if (divmod_p (producer)) + def_reg = SET_DEST (parallel_element (producer, 1)); + else + def_reg = SET_DEST (PATTERN (producer)); +@@ -969,8 +1383,7 @@ + break; + + case TYPE_DIV: +- if (INSN_CODE (producer) == CODE_FOR_divmodsi4 +- || INSN_CODE (producer) == CODE_FOR_udivmodsi4) ++ if (divmod_p (producer)) + { + rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); + rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); +@@ -1073,8 +1486,7 @@ + results, the quotient and the remainder. We have to handle them + individually. */ + case TYPE_DIV: +- if (INSN_CODE (producer) == CODE_FOR_divmodsi4 +- || INSN_CODE (producer) == CODE_FOR_udivmodsi4) ++ if (divmod_p (producer)) + { + rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); + rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); +@@ -1132,4 +1544,245 @@ + return n9_3r2w_consumed_by_ex_dep_p (consumer, last_def_reg); + } + ++/* Guard functions for N10 cores. */ ++ ++/* Check dependencies from EX to EX (ADDR_OUT -> ADDR_IN). */ ++bool ++nds32_n10_ex_to_ex_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ gcc_assert (get_attr_type (producer) == TYPE_FLOAD ++ || get_attr_type (producer) == TYPE_FSTORE); ++ gcc_assert (get_attr_type (consumer) == TYPE_FLOAD ++ || get_attr_type (consumer) == TYPE_FSTORE); ++ ++ if (!post_update_insn_p (producer)) ++ return false; ++ ++ return reg_overlap_p (extract_base_reg (producer), ++ extract_mem_rtx (consumer)); ++} ++ ++/* Check dependencies from MM to EX. */ ++bool ++nds32_n10_mm_to_ex_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx def_reg; ++ ++ switch (get_attr_type (producer)) ++ { ++ case TYPE_LOAD: ++ case TYPE_MUL: ++ case TYPE_MAC: ++ case TYPE_DALU64: ++ case TYPE_DMUL: ++ case TYPE_DMAC: ++ case TYPE_DALUROUND: ++ case TYPE_DBPICK: ++ case TYPE_DWEXT: ++ def_reg = SET_DEST (PATTERN (producer)); ++ break; ++ ++ /* Some special instructions, divmodsi4 and udivmodsi4, produce two ++ results, the quotient and the remainder. We have to handle them ++ individually. */ ++ case TYPE_DIV: ++ if (divmod_p (producer)) ++ { ++ rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); ++ rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); ++ ++ return (n10_consumed_by_ex_dep_p (consumer, def_reg1) ++ || n10_consumed_by_ex_dep_p (consumer, def_reg2)); ++ } ++ ++ def_reg = SET_DEST (PATTERN (producer)); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ return n10_consumed_by_ex_dep_p (consumer, def_reg); ++} ++ ++/* Check dependencies from LMW(N, N) to EX. */ ++bool ++nds32_n10_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx last_def_reg = extract_nth_access_reg (producer, -1); ++ ++ return n10_consumed_by_ex_dep_p (consumer, last_def_reg); ++} ++ ++/* Guard functions for Graywolf cores. */ ++ ++/* Check dependencies from EX to EX (ADDR_OUT -> ADDR_IN). */ ++bool ++nds32_gw_ex_to_ex_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ return nds32_n10_ex_to_ex_p (producer, consumer); ++} ++ ++/* Check dependencies from MM to EX. */ ++bool ++nds32_gw_mm_to_ex_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx def_reg; ++ ++ switch (get_attr_type (producer)) ++ { ++ case TYPE_LOAD: ++ case TYPE_MUL: ++ case TYPE_MAC: ++ case TYPE_DALU64: ++ case TYPE_DMUL: ++ case TYPE_DMAC: ++ case TYPE_DALUROUND: ++ case TYPE_DBPICK: ++ case TYPE_DWEXT: ++ def_reg = SET_DEST (PATTERN (producer)); ++ break; ++ ++ /* Some special instructions, divmodsi4 and udivmodsi4, produce two ++ results, the quotient and the remainder. We have to handle them ++ individually. */ ++ case TYPE_DIV: ++ if (divmod_p (producer)) ++ { ++ rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); ++ rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); ++ ++ return (gw_consumed_by_ex_dep_p (consumer, def_reg1) ++ || gw_consumed_by_ex_dep_p (consumer, def_reg2)); ++ } ++ ++ def_reg = SET_DEST (PATTERN (producer)); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ return gw_consumed_by_ex_dep_p (consumer, def_reg); ++} ++ ++/* Check dependencies from LMW(N, N) to EX. */ ++bool ++nds32_gw_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx last_def_reg = extract_nth_access_reg (producer, -1); ++ ++ return gw_consumed_by_ex_dep_p (consumer, last_def_reg); ++} ++ ++/* Guard functions for N12/N13 cores. */ ++ ++/* Check dependencies from E2 to E1. */ ++bool ++nds32_n13_e2_to_e1_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx def_reg; ++ ++ switch (get_attr_type (producer)) ++ { ++ /* Only post-update load/store instructions are considered. These ++ instructions produces address output at E2. */ ++ case TYPE_LOAD: ++ case TYPE_STORE: ++ case TYPE_LOAD_MULTIPLE: ++ case TYPE_STORE_MULTIPLE: ++ if (!post_update_insn_p (producer)) ++ return false; ++ ++ def_reg = extract_base_reg (producer); ++ break; ++ ++ case TYPE_ALU: ++ case TYPE_ALU_SHIFT: ++ case TYPE_PBSAD: ++ case TYPE_PBSADA: ++ case TYPE_MUL: ++ case TYPE_MAC: ++ def_reg = SET_DEST (PATTERN (producer)); ++ break; ++ ++ case TYPE_BRANCH: ++ return true; ++ ++ case TYPE_DIV: ++ /* Some special instructions, divmodsi4 and udivmodsi4, produce two ++ results, the quotient and the remainder. We have to handle them ++ individually. */ ++ if (divmod_p (producer)) ++ { ++ rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); ++ rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); ++ ++ return (n13_consumed_by_e1_dep_p (consumer, def_reg1) ++ || n13_consumed_by_e1_dep_p (consumer, def_reg2)); ++ } ++ ++ def_reg = SET_DEST (PATTERN (producer)); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ return n13_consumed_by_e1_dep_p (consumer, def_reg); ++} ++ ++/* Check dependencies from Load-Store Unit (E3) to E1. */ ++bool ++nds32_n13_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx def_reg = SET_DEST (PATTERN (producer)); ++ ++ gcc_assert (get_attr_type (producer) == TYPE_LOAD); ++ gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG); ++ ++ return n13_consumed_by_e1_dep_p (consumer, def_reg); ++} ++ ++/* Check dependencies from Load-Store Unit (E3) to E2. */ ++bool ++nds32_n13_load_to_e2_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx def_reg = SET_DEST (PATTERN (producer)); ++ ++ gcc_assert (get_attr_type (producer) == TYPE_LOAD); ++ gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG); ++ ++ return n13_consumed_by_e2_dep_p (consumer, def_reg); ++} ++ ++/* Check dependencies from LMW(N, N) to E1. */ ++bool ++nds32_n13_last_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx last_def_reg = extract_nth_access_reg (producer, -1); ++ ++ return n13_consumed_by_e1_dep_p (consumer, last_def_reg); ++} ++ ++/* Check dependencies from LMW(N, N) to E2. */ ++bool ++nds32_n13_last_load_to_e2_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx last_def_reg = extract_nth_access_reg (producer, -1); ++ ++ return n13_consumed_by_e2_dep_p (consumer, last_def_reg); ++} ++ ++/* Check dependencies from LMW(N, N-1) to E2. */ ++bool ++nds32_n13_last_two_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer) ++{ ++ rtx last_two_def_reg = extract_nth_access_reg (producer, -2); ++ ++ if (last_two_def_reg == NULL_RTX) ++ return false; ++ ++ return n13_consumed_by_e1_dep_p (consumer, last_two_def_reg); ++} + /* ------------------------------------------------------------------------ */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-predicates.c gcc-8.2.0/gcc/config/nds32/nds32-predicates.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-predicates.c 2018-05-07 04:22:07.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-predicates.c 2019-01-25 15:41:54.217806220 +0100 +@@ -356,8 +356,8 @@ + } + + /* Function to check if 'bclr' instruction can be used with IVAL. */ +-int +-nds32_can_use_bclr_p (int ival) ++bool ++nds32_can_use_bclr_p (HOST_WIDE_INT ival) + { + int one_bit_count; + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); +@@ -373,8 +373,8 @@ + } + + /* Function to check if 'bset' instruction can be used with IVAL. */ +-int +-nds32_can_use_bset_p (int ival) ++bool ++nds32_can_use_bset_p (HOST_WIDE_INT ival) + { + int one_bit_count; + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); +@@ -389,8 +389,8 @@ + } + + /* Function to check if 'btgl' instruction can be used with IVAL. */ +-int +-nds32_can_use_btgl_p (int ival) ++bool ++nds32_can_use_btgl_p (HOST_WIDE_INT ival) + { + int one_bit_count; + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); +@@ -405,8 +405,8 @@ + } + + /* Function to check if 'bitci' instruction can be used with IVAL. */ +-int +-nds32_can_use_bitci_p (int ival) ++bool ++nds32_can_use_bitci_p (HOST_WIDE_INT ival) + { + /* If we are using V3 ISA, we have 'bitci' instruction. + Try to see if we can present 'andi' semantic with +@@ -518,4 +518,117 @@ + + return val >= lower && val < upper; + } ++ ++bool ++nds32_const_unspec_p (rtx x) ++{ ++ if (GET_CODE (x) == CONST) ++ { ++ x = XEXP (x, 0); ++ ++ if (GET_CODE (x) == PLUS) ++ x = XEXP (x, 0); ++ ++ if (GET_CODE (x) == UNSPEC) ++ { ++ switch (XINT (x, 1)) ++ { ++ case UNSPEC_GOTINIT: ++ case UNSPEC_GOT: ++ case UNSPEC_GOTOFF: ++ case UNSPEC_PLT: ++ case UNSPEC_TLSGD: ++ case UNSPEC_TLSLD: ++ case UNSPEC_TLSIE: ++ case UNSPEC_TLSLE: ++ return false; ++ default: ++ return true; ++ } ++ } ++ } ++ ++ if (GET_CODE (x) == SYMBOL_REF ++ && SYMBOL_REF_TLS_MODEL (x)) ++ return false; ++ ++ return true; ++} ++ ++HOST_WIDE_INT ++const_vector_to_hwint (rtx op) ++{ ++ HOST_WIDE_INT hwint = 0; ++ HOST_WIDE_INT mask; ++ int i; ++ int shift_adv; ++ int shift = 0; ++ int nelem; ++ ++ switch (GET_MODE (op)) ++ { ++ case E_V2HImode: ++ mask = 0xffff; ++ shift_adv = 16; ++ nelem = 2; ++ break; ++ case E_V4QImode: ++ mask = 0xff; ++ shift_adv = 8; ++ nelem = 4; ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (TARGET_BIG_ENDIAN) ++ { ++ for (i = 0; i < nelem; ++i) ++ { ++ HOST_WIDE_INT val = XINT (XVECEXP (op, 0, nelem - i - 1), 0); ++ hwint |= (val & mask) << shift; ++ shift = shift + shift_adv; ++ } ++ } ++ else ++ { ++ for (i = 0; i < nelem; ++i) ++ { ++ HOST_WIDE_INT val = XINT (XVECEXP (op, 0, i), 0); ++ hwint |= (val & mask) << shift; ++ shift = shift + shift_adv; ++ } ++ } ++ ++ return hwint; ++} ++ ++bool ++nds32_valid_CVp5_p (rtx op) ++{ ++ HOST_WIDE_INT ival = const_vector_to_hwint (op); ++ return (ival < ((1 << 5) + 16)) && (ival >= (0 + 16)); ++} ++ ++bool ++nds32_valid_CVs5_p (rtx op) ++{ ++ HOST_WIDE_INT ival = const_vector_to_hwint (op); ++ return (ival < (1 << 4)) && (ival >= -(1 << 4)); ++} ++ ++bool ++nds32_valid_CVs2_p (rtx op) ++{ ++ HOST_WIDE_INT ival = const_vector_to_hwint (op); ++ return (ival < (1 << 19)) && (ival >= -(1 << 19)); ++} ++ ++bool ++nds32_valid_CVhi_p (rtx op) ++{ ++ HOST_WIDE_INT ival = const_vector_to_hwint (op); ++ return (ival != 0) && ((ival & 0xfff) == 0); ++} ++ + /* ------------------------------------------------------------------------ */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-protos.h gcc-8.2.0/gcc/config/nds32/nds32-protos.h +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-protos.h 2018-04-22 11:05:10.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-protos.h 2019-01-25 15:38:32.833242671 +0100 +@@ -69,9 +69,10 @@ + + /* ------------------------------------------------------------------------ */ + +-/* Auxiliary functions for lwm/smw. */ ++/* Auxiliary functions for manipulation DI mode. */ + +-extern bool nds32_valid_smw_lwm_base_p (rtx); ++extern rtx nds32_di_high_part_subreg(rtx); ++extern rtx nds32_di_low_part_subreg(rtx); + + /* Auxiliary functions for expanding rtl used in nds32-multiple.md. */ + +@@ -116,6 +117,20 @@ + extern bool nds32_n9_3r2w_mm_to_ex_p (rtx_insn *, rtx_insn *); + extern bool nds32_n9_last_load_to_ex_p (rtx_insn *, rtx_insn *); + ++extern bool nds32_n10_ex_to_ex_p (rtx_insn *, rtx_insn *); ++extern bool nds32_n10_mm_to_ex_p (rtx_insn *, rtx_insn *); ++extern bool nds32_n10_last_load_to_ex_p (rtx_insn *, rtx_insn *); ++ ++extern bool nds32_gw_ex_to_ex_p (rtx_insn *, rtx_insn *); ++extern bool nds32_gw_mm_to_ex_p (rtx_insn *, rtx_insn *); ++extern bool nds32_gw_last_load_to_ex_p (rtx_insn *, rtx_insn *); ++ ++extern bool nds32_n13_e2_to_e1_p (rtx_insn *, rtx_insn *); ++extern bool nds32_n13_load_to_e1_p (rtx_insn *, rtx_insn *); ++extern bool nds32_n13_load_to_e2_p (rtx_insn *, rtx_insn *); ++extern bool nds32_n13_last_load_to_e1_p (rtx_insn *, rtx_insn *); ++extern bool nds32_n13_last_load_to_e2_p (rtx_insn *, rtx_insn *); ++extern bool nds32_n13_last_two_load_to_e1_p (rtx_insn *, rtx_insn *); + + /* Auxiliary functions for stack operation predicate checking. */ + +@@ -123,24 +138,25 @@ + + /* Auxiliary functions for bit operation detection. */ + +-extern int nds32_can_use_bclr_p (int); +-extern int nds32_can_use_bset_p (int); +-extern int nds32_can_use_btgl_p (int); ++extern bool nds32_can_use_bclr_p (HOST_WIDE_INT); ++extern bool nds32_can_use_bset_p (HOST_WIDE_INT); ++extern bool nds32_can_use_btgl_p (HOST_WIDE_INT); + +-extern int nds32_can_use_bitci_p (int); ++extern bool nds32_can_use_bitci_p (HOST_WIDE_INT); + + extern bool nds32_const_double_range_ok_p (rtx, machine_mode, + HOST_WIDE_INT, HOST_WIDE_INT); + ++extern bool nds32_const_unspec_p (rtx x); ++ + /* Auxiliary function for 'Computing the Length of an Insn'. */ + + extern int nds32_adjust_insn_length (rtx_insn *, int); + + /* Auxiliary functions for FP_AS_GP detection. */ + +-extern int nds32_fp_as_gp_check_available (void); +- + extern bool nds32_symbol_load_store_p (rtx_insn *); ++extern bool nds32_naked_function_p (tree); + + /* Auxiliary functions for jump table generation. */ + +@@ -159,10 +175,50 @@ + extern enum nds32_expand_result_type nds32_expand_movcc (rtx *); + extern void nds32_expand_float_movcc (rtx *); + ++/* Auxiliary functions for expand extv/insv instruction. */ ++ ++extern enum nds32_expand_result_type nds32_expand_extv (rtx *); ++extern enum nds32_expand_result_type nds32_expand_insv (rtx *); ++ ++/* Auxiliary functions for expand PIC instruction. */ ++ ++extern void nds32_expand_pic_move (rtx *); ++ ++/* Auxiliary functions to legitimize PIC address. */ ++ ++extern rtx nds32_legitimize_pic_address (rtx); ++ ++/* Auxiliary functions for expand TLS instruction. */ ++ ++extern void nds32_expand_tls_move (rtx *); ++ ++/* Auxiliary functions to legitimize TLS address. */ ++ ++extern rtx nds32_legitimize_tls_address (rtx); ++ ++/* Auxiliary functions to identify thread-local symbol. */ ++ ++extern bool nds32_tls_referenced_p (rtx); ++ ++/* Auxiliary functions for expand ICT instruction. */ ++ ++extern void nds32_expand_ict_move (rtx *); ++ ++/* Auxiliary functions to legitimize address for indirect-call symbol. */ ++ ++extern rtx nds32_legitimize_ict_address (rtx); ++ ++/* Auxiliary functions to identify indirect-call symbol. */ ++ ++extern bool nds32_indirect_call_referenced_p (rtx); + + /* Auxiliary functions to identify long-call symbol. */ + extern bool nds32_long_call_p (rtx); + ++/* Auxiliary functions to identify SYMBOL_REF and LABEL_REF pattern. */ ++ ++extern bool symbolic_reference_mentioned_p (rtx); ++ + /* Auxiliary functions to identify conditional move comparison operand. */ + + extern int nds32_cond_move_p (rtx); +@@ -185,6 +241,7 @@ + extern const char *nds32_output_float_load(rtx *); + extern const char *nds32_output_float_store(rtx *); + extern const char *nds32_output_smw_single_word (rtx *); ++extern const char *nds32_output_smw_double_word (rtx *); + extern const char *nds32_output_lmw_single_word (rtx *); + extern const char *nds32_output_double (rtx *, bool); + extern const char *nds32_output_cbranchsi4_equality_zero (rtx_insn *, rtx *); +@@ -193,9 +250,12 @@ + rtx *); + extern const char *nds32_output_cbranchsi4_greater_less_zero (rtx_insn *, rtx *); + ++extern const char *nds32_output_unpkd8 (rtx, rtx, rtx, rtx, bool); ++ + extern const char *nds32_output_call (rtx, rtx *, rtx, + const char *, const char *, bool); +- ++extern const char *nds32_output_tls_desc (rtx *); ++extern const char *nds32_output_tls_ie (rtx *); + + /* Auxiliary functions to output stack push/pop instruction. */ + +@@ -203,9 +263,19 @@ + extern const char *nds32_output_stack_pop (rtx); + extern const char *nds32_output_return (void); + ++ ++/* Auxiliary functions to split/output sms pattern. */ ++extern bool nds32_need_split_sms_p (rtx, rtx, rtx, rtx); ++extern const char *nds32_output_sms (rtx, rtx, rtx, rtx); ++extern void nds32_split_sms (rtx, rtx, rtx, rtx, rtx, rtx, rtx); ++ + /* Auxiliary functions to split double word RTX pattern. */ + + extern void nds32_spilt_doubleword (rtx *, bool); ++extern void nds32_split_ashiftdi3 (rtx, rtx, rtx); ++extern void nds32_split_ashiftrtdi3 (rtx, rtx, rtx); ++extern void nds32_split_lshiftrtdi3 (rtx, rtx, rtx); ++extern void nds32_split_rotatertdi3 (rtx, rtx, rtx); + + /* Auxiliary functions to split large constant RTX pattern. */ + +@@ -237,15 +307,29 @@ + extern void nds32_asm_file_start_for_isr (void); + extern void nds32_asm_file_end_for_isr (void); + extern bool nds32_isr_function_p (tree); ++extern bool nds32_isr_function_critical_p (tree); + + /* Auxiliary functions for cost calculation. */ + ++extern void nds32_init_rtx_costs (void); + extern bool nds32_rtx_costs_impl (rtx, machine_mode, int, int, int *, bool); + extern int nds32_address_cost_impl (rtx, machine_mode, addr_space_t, bool); + + /* Auxiliary functions for pre-define marco. */ + extern void nds32_cpu_cpp_builtins(struct cpp_reader *); + ++/* Auxiliary functions for const_vector's constraints. */ ++ ++extern HOST_WIDE_INT const_vector_to_hwint (rtx); ++extern bool nds32_valid_CVp5_p (rtx); ++extern bool nds32_valid_CVs5_p (rtx); ++extern bool nds32_valid_CVs2_p (rtx); ++extern bool nds32_valid_CVhi_p (rtx); ++ ++/* Auxiliary functions for lwm/smw. */ ++ ++extern bool nds32_valid_smw_lwm_base_p (rtx); ++ + extern bool nds32_split_double_word_load_store_p (rtx *,bool); + + namespace nds32 { +@@ -258,11 +342,13 @@ + bool store_single_p (rtx_insn *); + bool load_double_p (rtx_insn *); + bool store_double_p (rtx_insn *); ++bool store_offset_reg_p (rtx_insn *); + bool post_update_insn_p (rtx_insn *); + bool immed_offset_p (rtx); + int find_post_update_rtx (rtx_insn *); + rtx extract_mem_rtx (rtx_insn *); + rtx extract_base_reg (rtx_insn *); ++rtx extract_offset_rtx (rtx_insn *); + + rtx extract_shift_reg (rtx); + +@@ -271,6 +357,8 @@ + + rtx extract_mac_non_acc_rtx (rtx_insn *); + ++bool divmod_p (rtx_insn *); ++ + rtx extract_branch_target_rtx (rtx_insn *); + rtx extract_branch_condition_rtx (rtx_insn *); + } // namespace nds32 +@@ -279,5 +367,6 @@ + + /* Functions for create nds32 specific optimization pass. */ + extern rtl_opt_pass *make_pass_nds32_relax_opt (gcc::context *); ++extern rtl_opt_pass *make_pass_nds32_fp_as_gp (gcc::context *); + + /* ------------------------------------------------------------------------ */ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-relax-opt.c gcc-8.2.0/gcc/config/nds32/nds32-relax-opt.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-relax-opt.c 2018-04-01 12:07:40.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-relax-opt.c 2019-01-25 15:38:32.833242671 +0100 +@@ -52,6 +52,8 @@ + #include "cfgrtl.h" + #include "tree-pass.h" + ++using namespace nds32; ++ + /* This is used to create unique relax hint id value. + The initial value is 0. */ + static int relax_group_id = 0; +@@ -185,6 +187,121 @@ + return false; + } + ++/* Return true if x is const and the referance is ict symbol. */ ++static bool ++nds32_ict_const_p (rtx x) ++{ ++ if (GET_CODE (x) == CONST) ++ { ++ x = XEXP (x, 0); ++ return nds32_indirect_call_referenced_p (x); ++ } ++ return FALSE; ++} ++ ++/* Group the following pattern as relax candidates: ++ ++ GOT: ++ sethi $ra, hi20(sym) ++ ori $ra, $ra, lo12(sym) ++ lw $rb, [$ra + $gp] ++ ++ GOTOFF, TLSLE: ++ sethi $ra, hi20(sym) ++ ori $ra, $ra, lo12(sym) ++ LS $rb, [$ra + $gp] ++ ++ GOTOFF, TLSLE: ++ sethi $ra, hi20(sym) ++ ori $ra, $ra, lo12(sym) ++ add $rb, $ra, $gp($tp) ++ ++ Initial GOT table: ++ sethi $gp,hi20(sym) ++ ori $gp, $gp, lo12(sym) ++ add5.pc $gp */ ++ ++static auto_vec nds32_group_infos; ++/* Group the PIC and TLS relax candidate instructions for linker. */ ++static bool ++nds32_pic_tls_group (rtx_insn *def_insn, ++ enum nds32_relax_insn_type relax_type, ++ int sym_type) ++{ ++ df_ref def_record; ++ df_link *link; ++ rtx_insn *use_insn = NULL; ++ rtx pat, new_pat; ++ def_record = DF_INSN_DEFS (def_insn); ++ for (link = DF_REF_CHAIN (def_record); link; link = link->next) ++ { ++ if (!DF_REF_INSN_INFO (link->ref)) ++ continue; ++ ++ use_insn = DF_REF_INSN (link->ref); ++ ++ /* Skip if define insn and use insn not in the same basic block. */ ++ if (!dominated_by_p (CDI_DOMINATORS, ++ BLOCK_FOR_INSN (use_insn), ++ BLOCK_FOR_INSN (def_insn))) ++ return FALSE; ++ ++ /* Skip if use_insn not active insn. */ ++ if (!active_insn_p (use_insn)) ++ return FALSE; ++ ++ switch (relax_type) ++ { ++ case RELAX_ORI: ++ ++ /* GOTOFF, TLSLE: ++ sethi $ra, hi20(sym) ++ ori $ra, $ra, lo12(sym) ++ add $rb, $ra, $gp($tp) */ ++ if ((sym_type == UNSPEC_TLSLE ++ || sym_type == UNSPEC_GOTOFF) ++ && (recog_memoized (use_insn) == CODE_FOR_addsi3)) ++ { ++ pat = XEXP (PATTERN (use_insn), 1); ++ new_pat = ++ gen_rtx_UNSPEC (SImode, ++ gen_rtvec (2, XEXP (pat, 0), XEXP (pat, 1)), ++ UNSPEC_ADD32); ++ validate_replace_rtx (pat, new_pat, use_insn); ++ nds32_group_infos.safe_push (use_insn); ++ } ++ else if (nds32_plus_reg_load_store_p (use_insn) ++ && !nds32_sp_base_or_plus_load_store_p (use_insn)) ++ nds32_group_infos.safe_push (use_insn); ++ else ++ return FALSE; ++ break; ++ ++ default: ++ return FALSE; ++ } ++ } ++ return TRUE; ++} ++ ++static int ++nds32_pic_tls_symbol_type (rtx x) ++{ ++ x = XEXP (SET_SRC (PATTERN (x)), 1); ++ ++ if (GET_CODE (x) == CONST) ++ { ++ x = XEXP (x, 0); ++ ++ if (GET_CODE (x) == PLUS) ++ x = XEXP (x, 0); ++ ++ return XINT (x, 1); ++ } ++ ++ return XINT (x, 1); ++} ++ + /* Group the relax candidates with group id. */ + static void + nds32_group_insns (rtx sethi) +@@ -193,6 +310,7 @@ + df_link *link; + rtx_insn *use_insn = NULL; + rtx group_id; ++ bool valid; + + def_record = DF_INSN_DEFS (sethi); + +@@ -242,6 +360,132 @@ + /* Insert .relax_* directive. */ + if (active_insn_p (use_insn)) + emit_insn_before (gen_relax_group (group_id), use_insn); ++ ++ /* Find ori ra, ra, unspec(symbol) instruction. */ ++ if (use_insn != NULL ++ && recog_memoized (use_insn) == CODE_FOR_lo_sum ++ && !nds32_const_unspec_p (XEXP (SET_SRC (PATTERN (use_insn)), 1))) ++ { ++ int sym_type = nds32_pic_tls_symbol_type (use_insn); ++ valid = nds32_pic_tls_group (use_insn, RELAX_ORI, sym_type); ++ ++ /* Insert .relax_* directive. */ ++ while (!nds32_group_infos.is_empty ()) ++ { ++ use_insn = nds32_group_infos.pop (); ++ if (valid) ++ emit_insn_before (gen_relax_group (group_id), use_insn); ++ } ++ } ++ } ++ ++ relax_group_id++; ++} ++ ++/* Convert relax group id in rtl. */ ++ ++static void ++nds32_group_tls_insn (rtx insn) ++{ ++ rtx pat = PATTERN (insn); ++ rtx unspec_relax_group = XEXP (XVECEXP (pat, 0, 1), 0); ++ ++ while (GET_CODE (pat) != SET && GET_CODE (pat) == PARALLEL) ++ { ++ pat = XVECEXP (pat, 0, 0); ++ } ++ ++ if (GET_CODE (unspec_relax_group) == UNSPEC ++ && XINT (unspec_relax_group, 1) == UNSPEC_VOLATILE_RELAX_GROUP) ++ { ++ XVECEXP (unspec_relax_group, 0, 0) = GEN_INT (relax_group_id); ++ } ++ ++ relax_group_id++; ++} ++ ++static bool ++nds32_float_reg_load_store_p (rtx_insn *insn) ++{ ++ rtx pat = PATTERN (insn); ++ ++ if (get_attr_type (insn) == TYPE_FLOAD ++ && GET_CODE (pat) == SET ++ && (GET_MODE (XEXP (pat, 0)) == SFmode ++ || GET_MODE (XEXP (pat, 0)) == DFmode) ++ && MEM_P (XEXP (pat, 1))) ++ { ++ rtx addr = XEXP (XEXP (pat, 1), 0); ++ ++ /* [$ra] */ ++ if (REG_P (addr)) ++ return true; ++ /* [$ra + offset] */ ++ if (GET_CODE (addr) == PLUS ++ && REG_P (XEXP (addr, 0)) ++ && CONST_INT_P (XEXP (addr, 1))) ++ return true; ++ } ++ return false; ++} ++ ++ ++/* Group float load-store instructions: ++ la $ra, symbol ++ flsi $rt, [$ra + offset] */ ++ ++static void ++nds32_group_float_insns (rtx insn) ++{ ++ df_ref def_record, use_record; ++ df_link *link; ++ rtx_insn *use_insn = NULL; ++ rtx group_id; ++ ++ def_record = DF_INSN_DEFS (insn); ++ ++ for (link = DF_REF_CHAIN (def_record); link; link = link->next) ++ { ++ if (!DF_REF_INSN_INFO (link->ref)) ++ continue; ++ ++ use_insn = DF_REF_INSN (link->ref); ++ ++ /* Skip if define insn and use insn not in the same basic block. */ ++ if (!dominated_by_p (CDI_DOMINATORS, ++ BLOCK_FOR_INSN (use_insn), ++ BLOCK_FOR_INSN (insn))) ++ return; ++ ++ /* Skip if the low-part used register is from different high-part ++ instructions. */ ++ use_record = DF_INSN_USES (use_insn); ++ if (DF_REF_CHAIN (use_record) && DF_REF_CHAIN (use_record)->next) ++ return; ++ ++ /* Skip if use_insn not active insn. */ ++ if (!active_insn_p (use_insn)) ++ return; ++ ++ if (!nds32_float_reg_load_store_p (use_insn) ++ || find_post_update_rtx (use_insn) != -1) ++ return; ++ } ++ ++ group_id = GEN_INT (relax_group_id); ++ /* Insert .relax_* directive for insn. */ ++ emit_insn_before (gen_relax_group (group_id), insn); ++ ++ /* Scan the use insns and insert the directive. */ ++ for (link = DF_REF_CHAIN (def_record); link; link = link->next) ++ { ++ if (!DF_REF_INSN_INFO (link->ref)) ++ continue; ++ ++ use_insn = DF_REF_INSN (link->ref); ++ ++ /* Insert .relax_* directive. */ ++ emit_insn_before (gen_relax_group (group_id), use_insn); + } + + relax_group_id++; +@@ -271,8 +515,21 @@ + /* Find sethi ra, symbol instruction. */ + if (recog_memoized (insn) == CODE_FOR_sethi + && nds32_symbolic_operand (XEXP (SET_SRC (PATTERN (insn)), 0), +- SImode)) ++ SImode) ++ && !nds32_ict_const_p (XEXP (SET_SRC (PATTERN (insn)), 0))) + nds32_group_insns (insn); ++ else if (recog_memoized (insn) == CODE_FOR_tls_ie) ++ nds32_group_tls_insn (insn); ++ else if (TARGET_FPU_SINGLE ++ && recog_memoized (insn) == CODE_FOR_move_addr ++ && !nds32_ict_const_p (XEXP (SET_SRC (PATTERN (insn)), 0))) ++ { ++ nds32_group_float_insns (insn); ++ } ++ } ++ else if (CALL_P (insn) && recog_memoized (insn) == CODE_FOR_tls_desc) ++ { ++ nds32_group_tls_insn (insn); + } + } + +diff -urN gcc-8.2.0.orig/gcc/config/nds32/nds32-utils.c gcc-8.2.0/gcc/config/nds32/nds32-utils.c +--- gcc-8.2.0.orig/gcc/config/nds32/nds32-utils.c 2018-04-08 10:31:52.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/nds32-utils.c 2019-01-25 15:38:32.833242671 +0100 +@@ -142,6 +142,23 @@ + return true; + } + ++bool ++store_offset_reg_p (rtx_insn *insn) ++{ ++ if (get_attr_type (insn) != TYPE_STORE) ++ return false; ++ ++ rtx offset_rtx = extract_offset_rtx (insn); ++ ++ if (offset_rtx == NULL_RTX) ++ return false; ++ ++ if (REG_P (offset_rtx)) ++ return true; ++ ++ return false; ++} ++ + /* Determine if INSN is a post update insn. */ + bool + post_update_insn_p (rtx_insn *insn) +@@ -316,22 +333,114 @@ + if (REG_P (XEXP (mem_rtx, 0))) + return XEXP (mem_rtx, 0); + ++ /* (mem (lo_sum (reg) (symbol_ref)) */ ++ if (GET_CODE (XEXP (mem_rtx, 0)) == LO_SUM) ++ return XEXP (XEXP (mem_rtx, 0), 0); ++ + plus_rtx = XEXP (mem_rtx, 0); + + if (GET_CODE (plus_rtx) == SYMBOL_REF + || GET_CODE (plus_rtx) == CONST) + return NULL_RTX; + +- gcc_assert (GET_CODE (plus_rtx) == PLUS +- || GET_CODE (plus_rtx) == POST_INC +- || GET_CODE (plus_rtx) == POST_DEC +- || GET_CODE (plus_rtx) == POST_MODIFY); +- gcc_assert (REG_P (XEXP (plus_rtx, 0))); + /* (mem (plus (reg) (const_int))) or ++ (mem (plus (mult (reg) (const_int 4)) (reg))) or + (mem (post_inc (reg))) or + (mem (post_dec (reg))) or + (mem (post_modify (reg) (plus (reg) (reg)))) */ +- return XEXP (plus_rtx, 0); ++ gcc_assert (GET_CODE (plus_rtx) == PLUS ++ || GET_CODE (plus_rtx) == POST_INC ++ || GET_CODE (plus_rtx) == POST_DEC ++ || GET_CODE (plus_rtx) == POST_MODIFY); ++ ++ if (REG_P (XEXP (plus_rtx, 0))) ++ return XEXP (plus_rtx, 0); ++ ++ gcc_assert (REG_P (XEXP (plus_rtx, 1))); ++ return XEXP (plus_rtx, 1); ++} ++ ++/* Extract the offset rtx from load/store insns. The function returns ++ NULL_RTX if offset is absent. */ ++rtx ++extract_offset_rtx (rtx_insn *insn) ++{ ++ rtx mem_rtx; ++ rtx plus_rtx; ++ rtx offset_rtx; ++ ++ /* Find the MEM rtx. The multiple load/store insns doens't have ++ the offset field so we can return NULL_RTX here. */ ++ switch (get_attr_type (insn)) ++ { ++ case TYPE_LOAD_MULTIPLE: ++ case TYPE_STORE_MULTIPLE: ++ return NULL_RTX; ++ ++ case TYPE_LOAD: ++ case TYPE_FLOAD: ++ case TYPE_STORE: ++ case TYPE_FSTORE: ++ mem_rtx = extract_mem_rtx (insn); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ gcc_assert (MEM_P (mem_rtx)); ++ ++ /* (mem (reg)) */ ++ if (REG_P (XEXP (mem_rtx, 0))) ++ return NULL_RTX; ++ ++ plus_rtx = XEXP (mem_rtx, 0); ++ ++ switch (GET_CODE (plus_rtx)) ++ { ++ case SYMBOL_REF: ++ case CONST: ++ case POST_INC: ++ case POST_DEC: ++ return NULL_RTX; ++ ++ case PLUS: ++ /* (mem (plus (reg) (const_int))) or ++ (mem (plus (mult (reg) (const_int 4)) (reg))) */ ++ if (REG_P (XEXP (plus_rtx, 0))) ++ offset_rtx = XEXP (plus_rtx, 1); ++ else ++ { ++ gcc_assert (REG_P (XEXP (plus_rtx, 1))); ++ offset_rtx = XEXP (plus_rtx, 0); ++ } ++ ++ if (ARITHMETIC_P (offset_rtx)) ++ { ++ gcc_assert (GET_CODE (offset_rtx) == MULT); ++ gcc_assert (REG_P (XEXP (offset_rtx, 0))); ++ offset_rtx = XEXP (offset_rtx, 0); ++ } ++ break; ++ ++ case LO_SUM: ++ /* (mem (lo_sum (reg) (symbol_ref)) */ ++ offset_rtx = XEXP (plus_rtx, 1); ++ break; ++ ++ case POST_MODIFY: ++ /* (mem (post_modify (reg) (plus (reg) (reg / const_int)))) */ ++ gcc_assert (REG_P (XEXP (plus_rtx, 0))); ++ plus_rtx = XEXP (plus_rtx, 1); ++ gcc_assert (GET_CODE (plus_rtx) == PLUS); ++ offset_rtx = XEXP (plus_rtx, 0); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ return offset_rtx; + } + + /* Extract the register of the shift operand from an ALU_SHIFT rtx. */ +@@ -413,6 +522,7 @@ + switch (get_attr_type (insn)) + { + case TYPE_MAC: ++ case TYPE_DMAC: + if (REG_P (XEXP (exp, 0))) + return XEXP (exp, 1); + else +@@ -423,6 +533,19 @@ + } + } + ++/* Check if the DIV insn needs two write ports. */ ++bool ++divmod_p (rtx_insn *insn) ++{ ++ gcc_assert (get_attr_type (insn) == TYPE_DIV); ++ ++ if (INSN_CODE (insn) == CODE_FOR_divmodsi4 ++ || INSN_CODE (insn) == CODE_FOR_udivmodsi4) ++ return true; ++ ++ return false; ++} ++ + /* Extract the rtx representing the branch target to help recognize + data hazards. */ + rtx +diff -urN gcc-8.2.0.orig/gcc/config/nds32/pipelines.md gcc-8.2.0/gcc/config/nds32/pipelines.md +--- gcc-8.2.0.orig/gcc/config/nds32/pipelines.md 2018-04-08 11:21:30.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/pipelines.md 2019-01-25 15:38:32.833242671 +0100 +@@ -44,6 +44,24 @@ + + + ;; ------------------------------------------------------------------------ ++;; Include N10 pipeline settings. ++;; ------------------------------------------------------------------------ ++(include "nds32-n10.md") ++ ++ ++;; ------------------------------------------------------------------------ ++;; Include Graywolf pipeline settings. ++;; ------------------------------------------------------------------------ ++(include "nds32-graywolf.md") ++ ++ ++;; ------------------------------------------------------------------------ ++;; Include N12/N13 pipeline settings. ++;; ------------------------------------------------------------------------ ++(include "nds32-n13.md") ++ ++ ++;; ------------------------------------------------------------------------ + ;; Define simple pipeline settings. + ;; ------------------------------------------------------------------------ + +diff -urN gcc-8.2.0.orig/gcc/config/nds32/predicates.md gcc-8.2.0/gcc/config/nds32/predicates.md +--- gcc-8.2.0.orig/gcc/config/nds32/predicates.md 2018-04-06 07:51:33.000000000 +0200 ++++ gcc-8.2.0/gcc/config/nds32/predicates.md 2019-01-25 15:38:32.833242671 +0100 +@@ -40,7 +40,15 @@ + (match_code "mult,and,ior,xor")) + + (define_predicate "nds32_symbolic_operand" +- (match_code "const,symbol_ref,label_ref")) ++ (and (match_code "const,symbol_ref,label_ref") ++ (match_test "!(TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (op))"))) ++ ++(define_predicate "nds32_nonunspec_symbolic_operand" ++ (and (match_code "const,symbol_ref,label_ref") ++ (match_test "!flag_pic && nds32_const_unspec_p (op) ++ && !(TARGET_ICT_MODEL_LARGE ++ && nds32_indirect_call_referenced_p (op))"))) + + (define_predicate "nds32_reg_constant_operand" + (ior (match_operand 0 "register_operand") +@@ -56,14 +64,51 @@ + (and (match_operand 0 "const_int_operand") + (match_test "satisfies_constraint_Is11 (op)")))) + ++(define_predicate "nds32_imm_0_1_operand" ++ (and (match_operand 0 "const_int_operand") ++ (ior (match_test "satisfies_constraint_Iv00 (op)") ++ (match_test "satisfies_constraint_Iv01 (op)")))) ++ ++(define_predicate "nds32_imm_1_2_operand" ++ (and (match_operand 0 "const_int_operand") ++ (ior (match_test "satisfies_constraint_Iv01 (op)") ++ (match_test "satisfies_constraint_Iv02 (op)")))) ++ ++(define_predicate "nds32_imm_1_2_4_8_operand" ++ (and (match_operand 0 "const_int_operand") ++ (ior (ior (match_test "satisfies_constraint_Iv01 (op)") ++ (match_test "satisfies_constraint_Iv02 (op)")) ++ (ior (match_test "satisfies_constraint_Iv04 (op)") ++ (match_test "satisfies_constraint_Iv08 (op)"))))) ++ ++(define_predicate "nds32_imm2u_operand" ++ (and (match_operand 0 "const_int_operand") ++ (match_test "satisfies_constraint_Iu02 (op)"))) ++ ++(define_predicate "nds32_imm4u_operand" ++ (and (match_operand 0 "const_int_operand") ++ (match_test "satisfies_constraint_Iu04 (op)"))) ++ + (define_predicate "nds32_imm5u_operand" + (and (match_operand 0 "const_int_operand") + (match_test "satisfies_constraint_Iu05 (op)"))) + ++(define_predicate "nds32_imm6u_operand" ++ (and (match_operand 0 "const_int_operand") ++ (match_test "satisfies_constraint_Iu06 (op)"))) ++ ++(define_predicate "nds32_rimm4u_operand" ++ (ior (match_operand 0 "register_operand") ++ (match_operand 0 "nds32_imm4u_operand"))) ++ + (define_predicate "nds32_rimm5u_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "nds32_imm5u_operand"))) + ++(define_predicate "nds32_rimm6u_operand" ++ (ior (match_operand 0 "register_operand") ++ (match_operand 0 "nds32_imm6u_operand"))) ++ + (define_predicate "nds32_move_operand" + (and (match_operand 0 "general_operand") + (not (match_code "high,const,symbol_ref,label_ref"))) +@@ -78,6 +123,20 @@ + return true; + }) + ++(define_predicate "nds32_vmove_operand" ++ (and (match_operand 0 "general_operand") ++ (not (match_code "high,const,symbol_ref,label_ref"))) ++{ ++ /* If the constant op does NOT satisfy Is20 nor Ihig, ++ we can not perform move behavior by a single instruction. */ ++ if (GET_CODE (op) == CONST_VECTOR ++ && !satisfies_constraint_CVs2 (op) ++ && !satisfies_constraint_CVhi (op)) ++ return false; ++ ++ return true; ++}) ++ + (define_predicate "nds32_and_operand" + (match_operand 0 "nds32_reg_constant_operand") + { +@@ -127,6 +186,15 @@ + (ior (match_operand 0 "nds32_symbolic_operand") + (match_operand 0 "nds32_general_register_operand"))) + ++(define_predicate "nds32_insv_operand" ++ (match_code "const_int") ++{ ++ return INTVAL (op) == 0 ++ || INTVAL (op) == 8 ++ || INTVAL (op) == 16 ++ || INTVAL (op) == 24; ++}) ++ + (define_predicate "nds32_lmw_smw_base_operand" + (and (match_code "mem") + (match_test "nds32_valid_smw_lwm_base_p (op)"))) +diff -urN gcc-8.2.0.orig/gcc/config/nds32/t-elf gcc-8.2.0/gcc/config/nds32/t-elf +--- gcc-8.2.0.orig/gcc/config/nds32/t-elf 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/t-elf 2019-01-25 15:38:32.833242671 +0100 +@@ -0,0 +1,42 @@ ++# The multilib settings of Andes NDS32 cpu for GNU compiler ++# Copyright (C) 2012-2018 Free Software Foundation, Inc. ++# Contributed by Andes Technology Corporation. ++# ++# This file is part of GCC. ++# ++# GCC is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published ++# by the Free Software Foundation; either version 3, or (at your ++# option) any later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the ++# driver program which options are defaults for this target and thus ++# do not need to be handled specially. ++MULTILIB_OPTIONS += mcmodel=small/mcmodel=medium/mcmodel=large mvh ++ ++ifneq ($(filter graywolf,$(TM_MULTILIB_CONFIG)),) ++MULTILIB_OPTIONS += mcpu=graywolf ++endif ++ ++ifneq ($(filter dsp,$(TM_MULTILIB_CONFIG)),) ++MULTILIB_OPTIONS += mext-dsp ++endif ++ ++ifneq ($(filter zol,$(TM_MULTILIB_CONFIG)),) ++MULTILIB_OPTIONS += mext-zol ++endif ++ ++ifneq ($(filter v3m+,$(TM_MULTILIB_CONFIG)),) ++MULTILIB_OPTIONS += march=v3m+ ++endif ++ ++# ------------------------------------------------------------------------ +diff -urN gcc-8.2.0.orig/gcc/config/nds32/t-linux gcc-8.2.0/gcc/config/nds32/t-linux +--- gcc-8.2.0.orig/gcc/config/nds32/t-linux 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/config/nds32/t-linux 2019-01-25 15:38:32.833242671 +0100 +@@ -0,0 +1,26 @@ ++# The multilib settings of Andes NDS32 cpu for GNU compiler ++# Copyright (C) 2012-2018 Free Software Foundation, Inc. ++# Contributed by Andes Technology Corporation. ++# ++# This file is part of GCC. ++# ++# GCC is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published ++# by the Free Software Foundation; either version 3, or (at your ++# option) any later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the ++# driver program which options are defaults for this target and thus ++# do not need to be handled specially. ++MULTILIB_OPTIONS += ++ ++# ------------------------------------------------------------------------ +diff -urN gcc-8.2.0.orig/gcc/config.gcc gcc-8.2.0/gcc/config.gcc +--- gcc-8.2.0.orig/gcc/config.gcc 2018-06-25 21:34:01.000000000 +0200 ++++ gcc-8.2.0/gcc/config.gcc 2019-01-25 15:38:32.821242637 +0100 +@@ -445,7 +445,17 @@ + ;; + nds32*) + cpu_type=nds32 +- extra_headers="nds32_intrinsic.h" ++ extra_headers="nds32_intrinsic.h nds32_isr.h nds32_init.inc" ++ case ${target} in ++ nds32*-*-linux*) ++ extra_options="${extra_options} nds32/nds32-linux.opt" ++ ;; ++ nds32*-*-elf*) ++ extra_options="${extra_options} nds32/nds32-elf.opt" ++ ;; ++ *) ++ ;; ++ esac + extra_objs="nds32-cost.o nds32-intrinsic.o nds32-isr.o nds32-md-auxiliary.o nds32-pipelines-auxiliary.o nds32-predicates.o nds32-memory-manipulation.o nds32-fp-as-gp.o nds32-relax-opt.o nds32-utils.o" + ;; + nios2-*-*) +@@ -2335,17 +2345,36 @@ + tmake_file="${tmake_file} msp430/t-msp430" + extra_gcc_objs="driver-msp430.o" + ;; +-nds32le-*-*) ++nds32*-*-*) + target_cpu_default="0" + tm_defines="${tm_defines}" +- tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} nds32/nds32_intrinsic.h" +- tmake_file="nds32/t-nds32 nds32/t-mlibs" +- ;; +-nds32be-*-*) +- target_cpu_default="0|MASK_BIG_ENDIAN" +- tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" +- tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} nds32/nds32_intrinsic.h" +- tmake_file="nds32/t-nds32 nds32/t-mlibs" ++ case ${target} in ++ nds32le*-*-*) ++ ;; ++ nds32be-*-*) ++ target_cpu_default="${target_cpu_default}|MASK_BIG_ENDIAN" ++ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" ++ ;; ++ esac ++ case ${target} in ++ nds32*-*-elf*) ++ tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} nds32/elf.h nds32/nds32_intrinsic.h" ++ tmake_file="nds32/t-nds32 nds32/t-elf" ++ ;; ++ nds32*-*-linux*) ++ tm_file="dbxelf.h elfos.h ${tm_file} gnu-user.h linux.h glibc-stdint.h nds32/linux.h nds32/nds32_intrinsic.h" ++ tmake_file="${tmake_file} nds32/t-nds32 nds32/t-linux" ++ ;; ++ esac ++ ++ # Handle --enable-default-relax setting. ++ if test x${enable_default_relax} = xyes; then ++ tm_defines="${tm_defines} TARGET_DEFAULT_RELAX=1" ++ fi ++ # Handle --with-ext-dsp ++ if test x${with_ext_dsp} = xyes; then ++ tm_defines="${tm_defines} TARGET_DEFAULT_EXT_DSP=1" ++ fi + ;; + nios2-*-*) + tm_file="elfos.h ${tm_file}" +@@ -4318,11 +4347,11 @@ + "") + with_cpu=n9 + ;; +- n6 | n7 | n8 | e8 | s8 | n9) ++ n6 | n7 |n8 | e8 | s8 | n9 | n10 | d10 | n12 | n13 | n15) + # OK + ;; + *) +- echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9" 1>&2 ++ echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9 n10 d10 n12 n13 n15" 1>&2 + exit 1 + ;; + esac +@@ -4332,15 +4361,30 @@ + "") + # the default library is newlib + with_nds32_lib=newlib ++ tm_defines="${tm_defines} TARGET_DEFAULT_CTOR_DTOR=1" + ;; + newlib) + # OK ++ tm_defines="${tm_defines} TARGET_DEFAULT_CTOR_DTOR=1" + ;; + mculib) + # OK ++ # for the arch=v3f or arch=v3s under mculib toolchain, ++ # we would like to set -fno-math-errno as default ++ case "${with_arch}" in ++ v3f | v3s) ++ tm_defines="${tm_defines} TARGET_DEFAULT_NO_MATH_ERRNO=1" ++ ;; ++ esac ++ ;; ++ glibc) ++ # OK ++ tm_defines="${tm_defines}" ++ ;; ++ uclibc) + ;; + *) +- echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2 ++ echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib glibc uclibc" 1>&2 + exit 1 + ;; + esac +diff -urN gcc-8.2.0.orig/gcc/configure gcc-8.2.0/gcc/configure +--- gcc-8.2.0.orig/gcc/configure 2018-04-18 11:46:58.000000000 +0200 ++++ gcc-8.2.0/gcc/configure 2019-01-25 15:38:32.837242683 +0100 +@@ -27784,7 +27784,7 @@ + # version to the per-target configury. + case "$cpu_type" in + aarch64 | alpha | arc | arm | avr | bfin | cris | i386 | m32c | m68k \ +- | microblaze | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu \ ++ | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \ + | tilegx | tilepro | visium | xstormy16 | xtensa) + insn="nop" + ;; +diff -urN gcc-8.2.0.orig/gcc/configure.ac gcc-8.2.0/gcc/configure.ac +--- gcc-8.2.0.orig/gcc/configure.ac 2018-04-18 11:46:58.000000000 +0200 ++++ gcc-8.2.0/gcc/configure.ac 2019-01-25 15:38:32.837242683 +0100 +@@ -4910,7 +4910,7 @@ + # version to the per-target configury. + case "$cpu_type" in + aarch64 | alpha | arc | arm | avr | bfin | cris | i386 | m32c | m68k \ +- | microblaze | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu \ ++ | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \ + | tilegx | tilepro | visium | xstormy16 | xtensa) + insn="nop" + ;; +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.c-torture/execute/20010122-1.c gcc-8.2.0/gcc/testsuite/gcc.c-torture/execute/20010122-1.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.c-torture/execute/20010122-1.c 2015-12-10 20:20:14.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.c-torture/execute/20010122-1.c 2019-01-25 15:38:32.837242683 +0100 +@@ -1,4 +1,5 @@ + /* { dg-skip-if "requires frame pointers" { *-*-* } "-fomit-frame-pointer" "" } */ ++/* { dg-additional-options "-malways-save-lp" { target nds32*-*-* } } */ + /* { dg-require-effective-target return_address } */ + + extern void exit (int); +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.dg/lower-subreg-1.c gcc-8.2.0/gcc/testsuite/gcc.dg/lower-subreg-1.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.dg/lower-subreg-1.c 2017-06-17 17:32:28.000000000 +0200 ++++ gcc-8.2.0/gcc/testsuite/gcc.dg/lower-subreg-1.c 2019-01-25 15:38:32.837242683 +0100 +@@ -1,4 +1,4 @@ +-/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */ ++/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* nds32*-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */ + /* { dg-options "-O -fdump-rtl-subreg1" } */ + /* { dg-additional-options "-mno-stv" { target ia32 } } */ + /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } } */ +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.dg/stack-usage-1.c gcc-8.2.0/gcc/testsuite/gcc.dg/stack-usage-1.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.dg/stack-usage-1.c 2017-06-17 17:32:28.000000000 +0200 ++++ gcc-8.2.0/gcc/testsuite/gcc.dg/stack-usage-1.c 2019-01-25 15:38:32.837242683 +0100 +@@ -2,6 +2,7 @@ + /* { dg-options "-fstack-usage" } */ + /* nvptx doesn't have a reg allocator, and hence no stack usage data. */ + /* { dg-skip-if "" { nvptx-*-* } } */ ++/* { dg-options "-fstack-usage -fno-omit-frame-pointer" { target { nds32*-*-* } } } */ + + /* This is aimed at testing basic support for -fstack-usage in the back-ends. + See the SPARC back-end for example (grep flag_stack_usage_info in sparc.c). +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isb.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isb.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isb.c 2013-12-03 11:58:05.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isb.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,11 +0,0 @@ +-/* Verify that we generate isb instruction with builtin function. */ +- +-/* { dg-do compile } */ +-/* { dg-options "-O0" } */ +-/* { dg-final { scan-assembler "\\tisb" } } */ +- +-void +-test (void) +-{ +- __builtin_nds32_isb (); +-} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isync.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isync.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-isync.c 2013-12-03 11:58:05.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-isync.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,12 +0,0 @@ +-/* Verify that we generate isync instruction with builtin function. */ +- +-/* { dg-do compile } */ +-/* { dg-options "-O0" } */ +-/* { dg-final { scan-assembler "\\tisync" } } */ +- +-void +-test (void) +-{ +- int *addr = (int *) 0x53000000; +- __builtin_nds32_isync (addr); +-} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c 2013-12-03 11:58:05.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,17 +0,0 @@ +-/* Verify that we generate mfsr/mtsr instruction with builtin function. */ +- +-/* { dg-do compile } */ +-/* { dg-options "-O0" } */ +-/* { dg-final { scan-assembler "\\tmfsr" } } */ +-/* { dg-final { scan-assembler "\\tmtsr" } } */ +- +-#include +- +-void +-test (void) +-{ +- int ipsw_value; +- +- ipsw_value = __builtin_nds32_mfsr (__NDS32_REG_IPSW__); +- __builtin_nds32_mtsr (ipsw_value, __NDS32_REG_IPSW__); +-} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c 2013-12-03 11:58:05.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,17 +0,0 @@ +-/* Verify that we generate mfusr/mtusr instruction with builtin function. */ +- +-/* { dg-do compile } */ +-/* { dg-options "-O0" } */ +-/* { dg-final { scan-assembler "\\tmfusr" } } */ +-/* { dg-final { scan-assembler "\\tmtusr" } } */ +- +-#include +- +-void +-test (void) +-{ +- int itype_value; +- +- itype_value = __builtin_nds32_mfusr (__NDS32_REG_ITYPE__); +- __builtin_nds32_mtusr (itype_value, __NDS32_REG_ITYPE__); +-} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c 2013-12-03 11:58:05.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,11 +0,0 @@ +-/* Verify that we generate setgie.d instruction with builtin function. */ +- +-/* { dg-do compile } */ +-/* { dg-options "-O0" } */ +-/* { dg-final { scan-assembler "\\tsetgie.d" } } */ +- +-void +-test (void) +-{ +- __builtin_nds32_setgie_dis (); +-} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c 2013-12-03 11:58:05.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,11 +0,0 @@ +-/* Verify that we generate setgie.e instruction with builtin function. */ +- +-/* { dg-do compile } */ +-/* { dg-options "-O0" } */ +-/* { dg-final { scan-assembler "\\tsetgie.e" } } */ +- +-void +-test (void) +-{ +- __builtin_nds32_setgie_en (); +-} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,36 @@ ++/* This is a test program for checking gie with ++ mtsr/mfsr instruction. */ ++ ++/* { dg-do run } */ ++/* { dg-options "-O0" } */ ++ ++#include ++#include ++ ++int ++main () ++{ ++ unsigned int psw; ++ unsigned int gie; ++ unsigned int pfm_ctl; ++ ++ __nds32__setgie_en (); ++ __nds32__dsb(); /* This is needed for waiting pipeline. */ ++ psw = __nds32__mfsr (NDS32_SR_PSW); ++ ++ gie = psw & 0x00000001; ++ ++ if (gie != 1) ++ abort (); ++ ++ psw = psw & 0xFFFFFFFE; ++ __nds32__mtsr (psw,NDS32_SR_PSW); ++ __nds32__dsb(); /* This is needed for waiting pipeline. */ ++ psw = __nds32__mfsr (NDS32_SR_PSW); ++ gie = psw & 0x00000001; ++ ++ if (gie != 0) ++ abort (); ++ else ++ exit (0); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++void ++main (void) ++{ ++ __nds32__clr_pending_swint (); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-clr-pending-hw.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++void ++main (void) ++{ ++ __nds32__clr_pending_hwint (NDS32_INT_H0); ++ __nds32__clr_pending_hwint (NDS32_INT_H1); ++ __nds32__clr_pending_hwint (NDS32_INT_H2); ++ ++ __nds32__clr_pending_hwint (NDS32_INT_H15); ++ __nds32__clr_pending_hwint (NDS32_INT_H16); ++ __nds32__clr_pending_hwint (NDS32_INT_H31); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-disable.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++void ++main (void) ++{ ++ __nds32__disable_int (NDS32_INT_H15); ++ __nds32__disable_int (NDS32_INT_H16); ++ __nds32__disable_int (NDS32_INT_H31); ++ __nds32__disable_int (NDS32_INT_SWI); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-enable.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++void ++main (void) ++{ ++ __nds32__enable_int (NDS32_INT_H15); ++ __nds32__enable_int (NDS32_INT_H16); ++ __nds32__enable_int (NDS32_INT_H31); ++ __nds32__enable_int (NDS32_INT_SWI); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-pending-int.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++int ++main (void) ++{ ++ int a = __nds32__get_pending_int (NDS32_INT_H15); ++ int b = __nds32__get_pending_int (NDS32_INT_SWI); ++ int c = __nds32__get_pending_int (NDS32_INT_H16); ++ ++ return a + b + c; ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-get-trig.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++int ++main (void) ++{ ++ int a = __nds32__get_trig_type (NDS32_INT_H0); ++ int b = __nds32__get_trig_type (NDS32_INT_H15); ++ int c = __nds32__get_trig_type (NDS32_INT_H16); ++ int d = __nds32__get_trig_type (NDS32_INT_H31); ++ return a + b + c + d; ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isb.c 2019-01-25 15:38:32.837242683 +0100 +@@ -0,0 +1,11 @@ ++/* Verify that we generate isb instruction with builtin function. */ ++ ++/* { dg-do compile } */ ++/* { dg-options "-O0" } */ ++/* { dg-final { scan-assembler "\\tisb" } } */ ++ ++void ++test (void) ++{ ++ __builtin_nds32_isb (); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-isync.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,12 @@ ++/* Verify that we generate isync instruction with builtin function. */ ++ ++/* { dg-do compile } */ ++/* { dg-options "-O0" } */ ++/* { dg-final { scan-assembler "\\tisync" } } */ ++ ++void ++test (void) ++{ ++ int *addr = (int *) 0x53000000; ++ __builtin_nds32_isync (addr); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfsr-mtsr.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,17 @@ ++/* Verify that we generate mfsr/mtsr instruction with builtin function. */ ++ ++/* { dg-do compile } */ ++/* { dg-options "-O0" } */ ++/* { dg-final { scan-assembler "\\tmfsr" } } */ ++/* { dg-final { scan-assembler "\\tmtsr" } } */ ++ ++#include ++ ++void ++test (void) ++{ ++ int ipsw_value; ++ ++ ipsw_value = __builtin_nds32_mfsr (__NDS32_REG_IPSW__); ++ __builtin_nds32_mtsr (ipsw_value, __NDS32_REG_IPSW__); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-mfusr-mtusr.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,17 @@ ++/* Verify that we generate mfusr/mtusr instruction with builtin function. */ ++ ++/* { dg-do compile } */ ++/* { dg-options "-O0" } */ ++/* { dg-final { scan-assembler "\\tmfusr" } } */ ++/* { dg-final { scan-assembler "\\tmtusr" } } */ ++ ++#include ++ ++void ++test (void) ++{ ++ int itype_value; ++ ++ itype_value = __builtin_nds32_mfusr (__NDS32_REG_ITYPE__); ++ __builtin_nds32_mtusr (itype_value, __NDS32_REG_ITYPE__); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-dis.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,13 @@ ++/* Verify that we generate setgie.d instruction with builtin function. */ ++ ++/* { dg-do compile } */ ++/* { dg-options "-O0" } */ ++/* { dg-final { scan-assembler "\\tsetgie.d" } } */ ++ ++#include ++ ++void ++test (void) ++{ ++ __nds32__setgie_dis (); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-setgie-en.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,13 @@ ++/* Verify that we generate setgie.e instruction with builtin function. */ ++ ++/* { dg-do compile */ ++/* { dg-options "-O0" } */ ++/* { dg-final { scan-assembler "\\tsetgie.e" } } */ ++ ++#include ++ ++void ++test (void) ++{ ++ __nds32__setgie_en (); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-pending.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++int ++main (void) ++{ ++ __nds32__set_pending_swint (); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-edge.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++void ++main (void) ++{ ++ __nds32__set_trig_type_edge (NDS32_INT_H0); ++ __nds32__set_trig_type_edge (NDS32_INT_H15); ++ __nds32__set_trig_type_edge (NDS32_INT_H16); ++ __nds32__set_trig_type_edge (NDS32_INT_H31); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/compile/builtin-set-trig-level.c 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++void ++main (void) ++{ ++ __nds32__set_trig_type_level (NDS32_INT_H0); ++ __nds32__set_trig_type_level (NDS32_INT_H15); ++ __nds32__set_trig_type_level (NDS32_INT_H16); ++ __nds32__set_trig_type_level (NDS32_INT_H31); ++} +diff -urN gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/nds32.exp gcc-8.2.0/gcc/testsuite/gcc.target/nds32/nds32.exp +--- gcc-8.2.0.orig/gcc/testsuite/gcc.target/nds32/nds32.exp 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/gcc/testsuite/gcc.target/nds32/nds32.exp 2019-01-25 15:38:32.841242694 +0100 +@@ -38,8 +38,10 @@ + dg-init + + # Main loop. +-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/compile/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS ++gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ ++ "" "" + + # All done. + dg-finish +diff -urN gcc-8.2.0.orig/gcc/testsuite/lib/target-supports.exp gcc-8.2.0/gcc/testsuite/lib/target-supports.exp +--- gcc-8.2.0.orig/gcc/testsuite/lib/target-supports.exp 2018-06-29 00:23:51.000000000 +0200 ++++ gcc-8.2.0/gcc/testsuite/lib/target-supports.exp 2019-01-25 15:38:32.841242694 +0100 +@@ -8783,6 +8783,7 @@ + || [istarget avr*-*-*] + || [istarget crisv32-*-*] || [istarget cris-*-*] + || [istarget mmix-*-*] ++ || [istarget nds32*-*-*] + || [istarget s390*-*-*] + || [istarget powerpc*-*-*] + || [istarget nios2*-*-*] +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/initfini.c gcc-8.2.0/libgcc/config/nds32/initfini.c +--- gcc-8.2.0.orig/libgcc/config/nds32/initfini.c 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/initfini.c 2019-01-25 15:38:32.841242694 +0100 +@@ -25,6 +25,10 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + ++#include ++/* Need header file for `struct object' type. */ ++#include "../libgcc/unwind-dw2-fde.h" ++ + /* Declare a pointer to void function type. */ + typedef void (*func_ptr) (void); + +@@ -42,11 +46,59 @@ + refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__ + symbol in crtinit.o, where they are defined. */ + +-static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"))) +- = { (func_ptr) (-1) }; ++static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"), used)) ++ = { (func_ptr) 0 }; ++ ++static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"), used)) ++ = { (func_ptr) 0 }; ++ ++ ++#ifdef SUPPORT_UNWINDING_DWARF2 ++/* Preparation of exception handling with dwar2 mechanism registration. */ ++ ++asm ("\n\ ++ .section .eh_frame,\"aw\",@progbits\n\ ++ .global __EH_FRAME_BEGIN__\n\ ++ .type __EH_FRAME_BEGIN__, @object\n\ ++ .align 2\n\ ++__EH_FRAME_BEGIN__:\n\ ++ ! Beginning location of eh_frame section\n\ ++ .previous\n\ ++"); ++ ++extern func_ptr __EH_FRAME_BEGIN__[]; ++ + +-static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"))) +- = { (func_ptr) (-1) }; ++/* Note that the following two functions are going to be chained into ++ constructor and destructor list, repectively. So these two declarations ++ must be placed after __CTOR_LIST__ and __DTOR_LIST. */ ++extern void __nds32_register_eh(void) __attribute__((constructor, used)); ++extern void __nds32_deregister_eh(void) __attribute__((destructor, used)); ++ ++/* Register the exception handling table as the first constructor. */ ++void ++__nds32_register_eh (void) ++{ ++ static struct object object; ++ if (__register_frame_info) ++ __register_frame_info (__EH_FRAME_BEGIN__, &object); ++} ++ ++/* Unregister the exception handling table as a deconstructor. */ ++void ++__nds32_deregister_eh (void) ++{ ++ static int completed = 0; ++ ++ if (completed) ++ return; ++ ++ if (__deregister_frame_info) ++ __deregister_frame_info (__EH_FRAME_BEGIN__); ++ ++ completed = 1; ++} ++#endif + + /* Run all the global destructors on exit from the program. */ + +@@ -63,7 +115,7 @@ + same particular root executable or shared library file. */ + + static void __do_global_dtors (void) +-asm ("__do_global_dtors") __attribute__ ((section (".text"))); ++asm ("__do_global_dtors") __attribute__ ((section (".text"), used)); + + static void + __do_global_dtors (void) +@@ -116,23 +168,37 @@ + last, these words naturally end up at the very ends of the two lists + contained in these two sections. */ + +-static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"))) ++static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"), used)) + = { (func_ptr) 0 }; + +-static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"))) ++static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"), used)) + = { (func_ptr) 0 }; + ++#ifdef SUPPORT_UNWINDING_DWARF2 ++/* ZERO terminator in .eh_frame section. */ ++asm ("\n\ ++ .section .eh_frame,\"aw\",@progbits\n\ ++ .global __EH_FRAME_END__\n\ ++ .type __EH_FRAME_END__, @object\n\ ++ .align 2\n\ ++__EH_FRAME_END__:\n\ ++ ! End location of eh_frame section with ZERO terminator\n\ ++ .word 0\n\ ++ .previous\n\ ++"); ++#endif ++ + /* Run all global constructors for the program. + Note that they are run in reverse order. */ + + static void __do_global_ctors (void) +-asm ("__do_global_ctors") __attribute__ ((section (".text"))); ++asm ("__do_global_ctors") __attribute__ ((section (".text"), used)); + + static void + __do_global_ctors (void) + { + func_ptr *p; +- for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--) ++ for (p = __CTOR_END__ - 1; *p; p--) + (*p) (); + } + +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/adj_intr_lvl.inc gcc-8.2.0/libgcc/config/nds32/isr-library/adj_intr_lvl.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/adj_intr_lvl.inc 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/adj_intr_lvl.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -26,13 +26,26 @@ + .macro ADJ_INTR_LVL + #if defined(NDS32_NESTED) /* Nested handler. */ + mfsr $r3, $PSW ++ /* By substracting 1 from $PSW, we can lower PSW.INTL ++ and enable GIE simultaneously. */ + addi $r3, $r3, #-0x1 ++ #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ ++ ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ ++ #endif + mtsr $r3, $PSW + #elif defined(NDS32_NESTED_READY) /* Nested ready handler. */ + /* Save ipc and ipsw and lower INT level. */ + mfsr $r3, $PSW + addi $r3, $r3, #-0x2 ++ #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ ++ ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ ++ #endif + mtsr $r3, $PSW + #else /* Not nested handler. */ ++ #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ ++ mfsr $r3, $PSW ++ ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ ++ mtsr $r3, $PSW ++ #endif + #endif + .endm +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/excp_isr.S gcc-8.2.0/libgcc/config/nds32/isr-library/excp_isr.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/excp_isr.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/excp_isr.S 2019-01-25 15:38:32.841242694 +0100 +@@ -23,6 +23,7 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + ++#include "save_usr_regs.inc" + #include "save_mac_regs.inc" + #include "save_fpu_regs.inc" + #include "save_fpu_regs_00.inc" +@@ -32,35 +33,33 @@ + #include "save_all.inc" + #include "save_partial.inc" + #include "adj_intr_lvl.inc" +-#include "restore_mac_regs.inc" + #include "restore_fpu_regs_00.inc" + #include "restore_fpu_regs_01.inc" + #include "restore_fpu_regs_02.inc" + #include "restore_fpu_regs_03.inc" + #include "restore_fpu_regs.inc" ++#include "restore_mac_regs.inc" ++#include "restore_usr_regs.inc" + #include "restore_all.inc" + #include "restore_partial.inc" ++ + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 +-/* +- First Level Handlers +- 1. First Level Handlers are invokded in vector section via jump instruction +- with specific names for different configurations. +- 2. Naming Format: _nds32_e_SR_NT for exception handlers. +- _nds32_i_SR_NT for interrupt handlers. +- 2.1 All upper case letters are replaced with specific lower case letters encodings. +- 2.2 SR: Saved Registers +- sa: Save All regs (context) +- ps: Partial Save (all caller-saved regs) +- 2.3 NT: Nested Type +- ns: nested +- nn: not nested +- nr: nested ready +-*/ +- +-/* +- This is original 16-byte vector size version. +-*/ ++ ++/* First Level Handlers ++ 1. First Level Handlers are invokded in vector section via jump instruction ++ with specific names for different configurations. ++ 2. Naming Format: _nds32_e_SR_NT for exception handlers. ++ _nds32_i_SR_NT for interrupt handlers. ++ 2.1 All upper case letters are replaced with specific lower case letters encodings. ++ 2.2 SR -- Saved Registers ++ sa: Save All regs (context) ++ ps: Partial Save (all caller-saved regs) ++ 2.3 NT -- Nested Type ++ ns: nested ++ nn: not nested ++ nr: nested ready */ ++ + #ifdef NDS32_SAVE_ALL_REGS + #if defined(NDS32_NESTED) + .globl _nds32_e_sa_ns +@@ -91,21 +90,26 @@ + #endif /* endif for Nest Type */ + #endif /* not NDS32_SAVE_ALL_REGS */ + +-/* +- This is 16-byte vector size version. +- The vector id was restored into $r0 in vector by compiler. +-*/ ++ ++/* For 4-byte vector size version, the vector id is ++ extracted from $ITYPE and is set into $r0 by library. ++ For 16-byte vector size version, the vector id ++ is set into $r0 in vector section by compiler. */ ++ ++/* Save used registers. */ + #ifdef NDS32_SAVE_ALL_REGS + SAVE_ALL + #else + SAVE_PARTIAL + #endif ++ + /* Prepare to call 2nd level handler. */ + la $r2, _nds32_jmptbl_00 + lw $r2, [$r2 + $r0 << #2] + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ + jral $r2 +- /* Restore used registers. */ ++ ++/* Restore used registers. */ + #ifdef NDS32_SAVE_ALL_REGS + RESTORE_ALL + #else +@@ -113,6 +117,7 @@ + #endif + iret + ++ + #ifdef NDS32_SAVE_ALL_REGS + #if defined(NDS32_NESTED) + .size _nds32_e_sa_ns, .-_nds32_e_sa_ns +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/intr_isr.S gcc-8.2.0/libgcc/config/nds32/isr-library/intr_isr.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/intr_isr.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/intr_isr.S 2019-01-25 15:38:32.841242694 +0100 +@@ -23,6 +23,7 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + ++#include "save_usr_regs.inc" + #include "save_mac_regs.inc" + #include "save_fpu_regs.inc" + #include "save_fpu_regs_00.inc" +@@ -32,35 +33,33 @@ + #include "save_all.inc" + #include "save_partial.inc" + #include "adj_intr_lvl.inc" +-#include "restore_mac_regs.inc" + #include "restore_fpu_regs_00.inc" + #include "restore_fpu_regs_01.inc" + #include "restore_fpu_regs_02.inc" + #include "restore_fpu_regs_03.inc" + #include "restore_fpu_regs.inc" ++#include "restore_mac_regs.inc" ++#include "restore_usr_regs.inc" + #include "restore_all.inc" + #include "restore_partial.inc" ++ + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 +-/* +- First Level Handlers +- 1. First Level Handlers are invokded in vector section via jump instruction +- with specific names for different configurations. +- 2. Naming Format: _nds32_e_SR_NT for exception handlers. +- _nds32_i_SR_NT for interrupt handlers. +- 2.1 All upper case letters are replaced with specific lower case letters encodings. +- 2.2 SR: Saved Registers +- sa: Save All regs (context) +- ps: Partial Save (all caller-saved regs) +- 2.3 NT: Nested Type +- ns: nested +- nn: not nested +- nr: nested ready +-*/ +- +-/* +- This is original 16-byte vector size version. +-*/ ++ ++/* First Level Handlers ++ 1. First Level Handlers are invokded in vector section via jump instruction ++ with specific names for different configurations. ++ 2. Naming Format: _nds32_e_SR_NT for exception handlers. ++ _nds32_i_SR_NT for interrupt handlers. ++ 2.1 All upper case letters are replaced with specific lower case letters encodings. ++ 2.2 SR -- Saved Registers ++ sa: Save All regs (context) ++ ps: Partial Save (all caller-saved regs) ++ 2.3 NT -- Nested Type ++ ns: nested ++ nn: not nested ++ nr: nested ready */ ++ + #ifdef NDS32_SAVE_ALL_REGS + #if defined(NDS32_NESTED) + .globl _nds32_i_sa_ns +@@ -91,21 +90,36 @@ + #endif /* endif for Nest Type */ + #endif /* not NDS32_SAVE_ALL_REGS */ + +-/* +- This is 16-byte vector size version. +- The vector id was restored into $r0 in vector by compiler. +-*/ ++ ++/* For 4-byte vector size version, the vector id is ++ extracted from $ITYPE and is set into $r0 by library. ++ For 16-byte vector size version, the vector id ++ is set into $r0 in vector section by compiler. */ ++ ++/* Save used registers first. */ + #ifdef NDS32_SAVE_ALL_REGS + SAVE_ALL + #else + SAVE_PARTIAL + #endif +- /* Prepare to call 2nd level handler. */ ++ ++/* According to vector size, we need to have different implementation. */ ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* Prepare to call 2nd level handler. */ ++ la $r2, _nds32_jmptbl_00 ++ lw $r2, [$r2 + $r0 << #2] ++ addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */ ++ ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ ++ jral $r2 ++#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ ++ /* Prepare to call 2nd level handler. */ + la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */ + lw $r2, [$r2 + $r0 << #2] + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ + jral $r2 +- /* Restore used registers. */ ++#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ ++ ++/* Restore used registers. */ + #ifdef NDS32_SAVE_ALL_REGS + RESTORE_ALL + #else +@@ -113,6 +127,7 @@ + #endif + iret + ++ + #ifdef NDS32_SAVE_ALL_REGS + #if defined(NDS32_NESTED) + .size _nds32_i_sa_ns, .-_nds32_i_sa_ns +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/reset.S gcc-8.2.0/libgcc/config/nds32/isr-library/reset.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/reset.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/reset.S 2019-01-25 15:38:32.841242694 +0100 +@@ -26,22 +26,18 @@ + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 + .weak _SDA_BASE_ /* For reset handler only. */ +- .weak _FP_BASE_ /* For reset handler only. */ + .weak _nds32_init_mem /* User defined memory initialization function. */ + .globl _start + .globl _nds32_reset + .type _nds32_reset, @function + _nds32_reset: + _start: +-#ifdef NDS32_EXT_EX9 +- .no_ex9_begin +-#endif + /* Handle NMI and warm boot if any of them exists. */ + beqz $sp, 1f /* Reset, NMI or warm boot? */ + /* Either NMI or warm boot; save all regs. */ + + /* Preserve registers for context-switching. */ +-#ifdef __NDS32_REDUCED_REGS__ ++#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS + /* For 16-reg mode. */ + smw.adm $r0, [$sp], $r10, #0x0 + smw.adm $r15, [$sp], $r15, #0xf +@@ -49,10 +45,9 @@ + /* For 32-reg mode. */ + smw.adm $r0, [$sp], $r27, #0xf + #endif +-#ifdef NDS32_EXT_IFC ++#if __NDS32_EXT_IFC__ + mfusr $r1, $IFC_LP +- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep +- stack 8-byte alignment. */ ++ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte alignment. */ + #endif + + la $gp, _SDA_BASE_ /* Init GP for small data access. */ +@@ -71,12 +66,11 @@ + bnez $r0, 1f /* If fail to resume, do cold boot. */ + + /* Restore registers for context-switching. */ +-#ifdef NDS32_EXT_IFC +- lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep +- stack 8-byte alignment. */ ++#if __NDS32_EXT_IFC__ ++ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep stack 8-byte alignment. */ + mtusr $r1, $IFC_LP + #endif +-#ifdef __NDS32_REDUCED_REGS__ ++#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS + /* For 16-reg mode. */ + lmw.bim $r15, [$sp], $r15, #0xf + lmw.bim $r0, [$sp], $r10, #0x0 +@@ -88,6 +82,17 @@ + + + 1: /* Cold boot. */ ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* With vector ID feature for v3 architecture, default vector size is 4-byte. */ ++ /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */ ++ mfsr $r0, $IVB ++ li $r1, #0xc000 ++ or $r0, $r0, $r1 ++ xor $r0, $r0, $r1 ++ mtsr $r0, $IVB ++ dsb ++#else ++ /* There is no vector ID feature, so the vector size must be 16-byte. */ + /* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */ + mfsr $r0, $IVB + li $r1, #0xffff3fff +@@ -95,36 +100,54 @@ + ori $r0, $r0, #0x4000 + mtsr $r0, $IVB + dsb ++#endif + + la $gp, _SDA_BASE_ /* Init $gp. */ +- la $fp, _FP_BASE_ /* Init $fp. */ + la $sp, _stack /* Init $sp. */ +-#ifdef NDS32_EXT_EX9 +-/* +- * Initialize the table base of EX9 instruction +- * ex9 generation needs to disable before the ITB is set +- */ +- mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */ ++ ++#if __NDS32_EXT_EX9__ ++.L_init_itb: ++ /* Initialization for Instruction Table Base (ITB). ++ The symbol _ITB_BASE_ is determined by Linker. ++ Set $ITB only if MSC_CFG.EIT (cr4.b'24) is set. */ ++ mfsr $r0, $MSC_CFG + srli $r0, $r0, 24 + andi $r0, $r0, 0x1 +- beqz $r0, 4f /* Zero means HW does not support EX9. */ +- la $r0, _ITB_BASE_ /* Init $ITB. */ ++ beqz $r0, 4f /* Fall through ? */ ++ la $r0, _ITB_BASE_ + mtusr $r0, $ITB +- .no_ex9_end + 4: + #endif +- la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem +- may written by C language. */ ++ ++#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__ ++.L_init_fpu: ++ /* Initialize FPU ++ Set FUCOP_CTL.CP0EN (fucpr.b'0). */ ++ mfsr $r0, $FUCOP_CTL ++ ori $r0, $r0, 0x1 ++ mtsr $r0, $FUCOP_CTL ++ dsb ++ /* According to [bugzilla #9425], set flush-to-zero mode. ++ That is, set $FPCSR.DNZ(b'12) = 1. */ ++ FMFCSR $r0 ++ ori $r0, $r0, 0x1000 ++ FMTCSR $r0 ++ dsb ++#endif ++ ++ /* Call DRAM init. _nds32_init_mem may written by C language. */ ++ la $r15, _nds32_init_mem + beqz $r15, 6f + jral $r15 + 6: + l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */ + jral $r15 +-/* Reset handler() should never return in a RTOS or non-OS system. +- In case it does return, an exception will be generated. +- This exception will be caught either by default break handler or by EDM. +- Default break handle may just do an infinite loop. +- EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ ++ ++ /* Reset handler() should never return in a RTOS or non-OS system. ++ In case it does return, an exception will be generated. ++ This exception will be caught either by default break handler or by EDM. ++ Default break handle may just do an infinite loop. ++ EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ + 5: + break #0x7fff + .size _nds32_reset, .-_nds32_reset +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_all.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_all.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_all.inc 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_all.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -31,15 +31,11 @@ + mtsr $r2, $IPSW + RESTORE_FPU_REGS + RESTORE_MAC_REGS +-#ifdef NDS32_EXT_IFC +- lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep +- stack 8-byte alignment. */ +- mtusr $r1, $IFC_LP +-#endif +-#ifdef __NDS32_REDUCED_REGS__ ++ RESTORE_USR_REGS ++#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS + lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */ + lmw.bim $r15, [$sp], $r15, #0xf +-#else /* not __NDS32_REDUCED_REGS__ */ ++#else + lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */ + #endif + .endm +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_mac_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_mac_regs.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_mac_regs.inc 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_mac_regs.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -24,7 +24,7 @@ + . */ + + .macro RESTORE_MAC_REGS +-#ifdef NDS32_DX_REGS ++#if __NDS32_DX_REGS__ + lmw.bim $r1, [$sp], $r4, #0x0 + mtusr $r1, $d0.lo + mtusr $r2, $d0.hi +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_partial.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_partial.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_partial.inc 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_partial.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -31,15 +31,11 @@ + mtsr $r1, $IPC /* Set IPC. */ + mtsr $r2, $IPSW /* Set IPSW. */ + #endif +- RESTORE_FPU_REGS +- RESTORE_MAC_REGS +-#ifdef NDS32_EXT_IFC +- lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep +- stack 8-byte alignment. */ +- mtusr $r1, $IFC_LP +-#endif ++ RESTORE_FPU_REGS ++ RESTORE_MAC_REGS ++ RESTORE_USR_REGS + lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */ +-#ifdef __NDS32_REDUCED_REGS__ ++#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS + lmw.bim $r15, [$sp], $r15, #0x2 + #else + lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */ +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_usr_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/restore_usr_regs.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/restore_usr_regs.inc 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/restore_usr_regs.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,42 @@ ++/* c-isr library stuff of Andes NDS32 cpu for GNU compiler ++ Copyright (C) 2012-2018 Free Software Foundation, Inc. ++ Contributed by Andes Technology Corporation. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++.macro RESTORE_USR_REGS ++#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) ++ lmw.bim $r1, [$sp], $r4, #0x0 ++ mtusr $r1, $IFC_LP ++ mtusr $r2, $LB ++ mtusr $r3, $LE ++ mtusr $r4, $LC ++#elif __NDS32_EXT_IFC__ ++ lmw.bim $r1, [$sp], $r2, #0x0 ++ mtusr $r1, $IFC_LP ++#elif __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ ++ lmw.bim $r1, [$sp], $r4, #0x0 ++ mtusr $r1, $LB ++ mtusr $r2, $LE ++ mtusr $r3, $LC ++#endif ++.endm +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_all.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_all.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_all.inc 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_all.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -23,45 +23,42 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +-.macro SAVE_ALL_4B +-#ifdef __NDS32_REDUCED_REGS__ ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ ++/* If vector size is 4-byte, we have to save registers ++ in the macro implementation. */ ++.macro SAVE_ALL ++#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS + smw.adm $r15, [$sp], $r15, #0xf + smw.adm $r0, [$sp], $r10, #0x0 +-#else /* not __NDS32_REDUCED_REGS__ */ ++#else + smw.adm $r0, [$sp], $r27, #0xf +-#endif /* not __NDS32_REDUCED_REGS__ */ +-#ifdef NDS32_EXT_IFC +- mfusr $r1, $IFC_LP +- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep +- stack 8-byte alignment. */ + #endif +- SAVE_MAC_REGS +- SAVE_FPU_REGS ++ SAVE_USR_REGS ++ SAVE_MAC_REGS ++ SAVE_FPU_REGS + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ + move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ + mfsr $r0, $ITYPE /* Get VID to $r0. */ + srli $r0, $r0, #5 +-#ifdef __NDS32_ISA_V2__ + andi $r0, $r0, #127 +-#else +- fexti33 $r0, #6 +-#endif + .endm + ++#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ ++ ++/* If vector size is 16-byte, some works can be done in ++ the vector section generated by compiler, so that we ++ can implement less in the macro. */ + .macro SAVE_ALL +-/* SAVE_REG_TBL code has been moved to +- vector table generated by compiler. */ +-#ifdef NDS32_EXT_IFC +- mfusr $r1, $IFC_LP +- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep +- stack 8-byte alignment. */ +-#endif +- SAVE_MAC_REGS +- SAVE_FPU_REGS ++ SAVE_USR_REGS ++ SAVE_MAC_REGS ++ SAVE_FPU_REGS + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ + move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ + .endm ++ ++#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_mac_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_mac_regs.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_mac_regs.inc 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_mac_regs.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -24,7 +24,7 @@ + . */ + + .macro SAVE_MAC_REGS +-#ifdef NDS32_DX_REGS ++#if __NDS32_DX_REGS__ + mfusr $r1, $d0.lo + mfusr $r2, $d0.hi + mfusr $r3, $d1.lo +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_partial.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_partial.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_partial.inc 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_partial.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -23,20 +23,20 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +-.macro SAVE_PARTIAL_4B +-#ifdef __NDS32_REDUCED_REGS__ ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ ++/* If vector size is 4-byte, we have to save registers ++ in the macro implementation. */ ++.macro SAVE_PARTIAL ++#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS + smw.adm $r15, [$sp], $r15, #0x2 +-#else /* not __NDS32_REDUCED_REGS__ */ ++#else + smw.adm $r15, [$sp], $r27, #0x2 +-#endif /* not __NDS32_REDUCED_REGS__ */ +- smw.adm $r0, [$sp], $r5, #0x0 +-#ifdef NDS32_EXT_IFC +- mfusr $r1, $IFC_LP +- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep +- stack 8-byte alignment. */ + #endif +- SAVE_MAC_REGS +- SAVE_FPU_REGS ++ smw.adm $r0, [$sp], $r5, #0x0 ++ SAVE_USR_REGS ++ SAVE_MAC_REGS ++ SAVE_FPU_REGS + #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ +@@ -44,26 +44,24 @@ + #endif + mfsr $r0, $ITYPE /* Get VID to $r0. */ + srli $r0, $r0, #5 +-#ifdef __NDS32_ISA_V2__ + andi $r0, $r0, #127 +-#else +- fexti33 $r0, #6 +-#endif + .endm + ++#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ ++ ++/* If vector size is 16-byte, some works can be done in ++ the vector section generated by compiler, so that we ++ can implement less in the macro. */ ++ + .macro SAVE_PARTIAL +-/* SAVE_CALLER_REGS code has been moved to +- vector table generated by compiler. */ +-#ifdef NDS32_EXT_IFC +- mfusr $r1, $IFC_LP +- smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep +- stack 8-byte alignment. */ +-#endif +- SAVE_MAC_REGS +- SAVE_FPU_REGS ++ SAVE_USR_REGS ++ SAVE_MAC_REGS ++ SAVE_FPU_REGS + #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ + #endif + .endm ++ ++#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_usr_regs.inc gcc-8.2.0/libgcc/config/nds32/isr-library/save_usr_regs.inc +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/save_usr_regs.inc 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/save_usr_regs.inc 2019-01-25 15:38:32.841242694 +0100 +@@ -0,0 +1,44 @@ ++/* c-isr library stuff of Andes NDS32 cpu for GNU compiler ++ Copyright (C) 2012-2018 Free Software Foundation, Inc. ++ Contributed by Andes Technology Corporation. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++.macro SAVE_USR_REGS ++/* Store User Special Registers according to supported ISA extension ++ !!! WATCH OUT !!! Take care of 8-byte alignment issue. */ ++#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) ++ mfusr $r1, $IFC_LP ++ mfusr $r2, $LB ++ mfusr $r3, $LE ++ mfusr $r4, $LC ++ smw.adm $r1, [$sp], $r4, #0x0 /* Save even. Ok! */ ++#elif __NDS32_EXT_IFC__ ++ mfusr $r1, $IFC_LP ++ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte aligned. */ ++#elif (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) ++ mfusr $r1, $LB ++ mfusr $r2, $LE ++ mfusr $r3, $LC ++ smw.adm $r1, [$sp], $r4, #0x0 /* Save extra $r4 to keep stack 8-byte aligned. */ ++#endif ++.endm +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid00.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid00.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid00.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid00.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.00, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_00 + .type _nds32_vector_00, @function + _nds32_vector_00: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid01.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid01.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid01.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid01.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.01, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_01 + .type _nds32_vector_01, @function + _nds32_vector_01: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid02.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid02.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid02.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid02.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.02, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_02 + .type _nds32_vector_02, @function + _nds32_vector_02: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid03.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid03.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid03.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid03.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.03, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_03 + .type _nds32_vector_03, @function + _nds32_vector_03: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid04.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid04.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid04.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid04.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.04, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_04 + .type _nds32_vector_04, @function + _nds32_vector_04: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid05.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid05.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid05.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid05.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.05, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_05 + .type _nds32_vector_05, @function + _nds32_vector_05: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid06.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid06.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid06.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid06.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.06, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_06 + .type _nds32_vector_06, @function + _nds32_vector_06: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid07.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid07.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid07.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid07.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.07, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_07 + .type _nds32_vector_07, @function + _nds32_vector_07: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid08.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid08.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid08.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid08.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.08, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_08 + .type _nds32_vector_08, @function + _nds32_vector_08: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid09.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid09.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid09.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid09.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.09, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_09 + .type _nds32_vector_09, @function + _nds32_vector_09: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid10.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid10.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid10.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid10.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.10, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_10 + .type _nds32_vector_10, @function + _nds32_vector_10: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid11.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid11.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid11.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid11.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.11, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_11 + .type _nds32_vector_11, @function + _nds32_vector_11: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid12.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid12.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid12.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid12.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.12, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_12 + .type _nds32_vector_12, @function + _nds32_vector_12: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid13.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid13.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid13.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid13.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.13, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_13 + .type _nds32_vector_13, @function + _nds32_vector_13: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid14.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid14.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid14.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid14.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.14, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_14 + .type _nds32_vector_14, @function + _nds32_vector_14: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid15.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid15.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid15.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid15.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.15, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_15 + .type _nds32_vector_15, @function + _nds32_vector_15: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid16.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid16.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid16.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid16.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.16, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_16 + .type _nds32_vector_16, @function + _nds32_vector_16: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid17.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid17.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid17.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid17.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.17, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_17 + .type _nds32_vector_17, @function + _nds32_vector_17: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid18.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid18.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid18.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid18.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.18, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_18 + .type _nds32_vector_18, @function + _nds32_vector_18: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid19.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid19.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid19.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid19.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.19, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_19 + .type _nds32_vector_19, @function + _nds32_vector_19: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid20.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid20.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid20.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid20.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.20, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_20 + .type _nds32_vector_20, @function + _nds32_vector_20: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid21.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid21.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid21.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid21.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.21, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_21 + .type _nds32_vector_21, @function + _nds32_vector_21: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid22.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid22.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid22.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid22.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.22, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_22 + .type _nds32_vector_22, @function + _nds32_vector_22: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid23.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid23.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid23.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid23.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.23, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_23 + .type _nds32_vector_23, @function + _nds32_vector_23: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid24.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid24.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid24.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid24.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.24, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_24 + .type _nds32_vector_24, @function + _nds32_vector_24: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid25.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid25.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid25.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid25.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.25, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_25 + .type _nds32_vector_25, @function + _nds32_vector_25: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid26.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid26.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid26.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid26.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.26, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_26 + .type _nds32_vector_26, @function + _nds32_vector_26: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid27.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid27.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid27.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid27.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.27, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_27 + .type _nds32_vector_27, @function + _nds32_vector_27: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid28.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid28.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid28.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid28.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.28, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_28 + .type _nds32_vector_28, @function + _nds32_vector_28: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid29.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid29.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid29.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid29.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.29, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_29 + .type _nds32_vector_29, @function + _nds32_vector_29: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid30.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid30.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid30.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid30.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.30, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_30 + .type _nds32_vector_30, @function + _nds32_vector_30: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid31.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid31.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid31.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid31.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.31, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_31 + .type _nds32_vector_31, @function + _nds32_vector_31: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid32.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid32.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid32.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid32.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.32, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_32 + .type _nds32_vector_32, @function + _nds32_vector_32: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid33.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid33.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid33.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid33.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.33, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_33 + .type _nds32_vector_33, @function + _nds32_vector_33: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid34.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid34.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid34.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid34.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.34, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_34 + .type _nds32_vector_34, @function + _nds32_vector_34: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid35.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid35.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid35.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid35.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.35, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_35 + .type _nds32_vector_35, @function + _nds32_vector_35: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid36.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid36.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid36.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid36.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.36, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_36 + .type _nds32_vector_36, @function + _nds32_vector_36: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid37.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid37.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid37.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid37.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.37, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_37 + .type _nds32_vector_37, @function + _nds32_vector_37: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid38.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid38.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid38.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid38.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.38, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_38 + .type _nds32_vector_38, @function + _nds32_vector_38: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid39.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid39.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid39.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid39.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.39, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_39 + .type _nds32_vector_39, @function + _nds32_vector_39: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid40.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid40.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid40.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid40.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.40, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_40 + .type _nds32_vector_40, @function + _nds32_vector_40: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid41.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid41.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid41.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid41.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.41, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_41 + .type _nds32_vector_41, @function + _nds32_vector_41: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid42.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid42.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid42.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid42.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.42, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_42 + .type _nds32_vector_42, @function + _nds32_vector_42: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid43.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid43.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid43.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid43.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.43, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_43 + .type _nds32_vector_43, @function + _nds32_vector_43: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid44.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid44.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid44.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid44.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.44, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_44 + .type _nds32_vector_44, @function + _nds32_vector_44: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid45.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid45.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid45.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid45.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.45, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_45 + .type _nds32_vector_45, @function + _nds32_vector_45: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid46.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid46.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid46.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid46.S 2019-01-25 15:38:32.841242694 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.46, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_46 + .type _nds32_vector_46, @function + _nds32_vector_46: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid47.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid47.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid47.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid47.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.47, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_47 + .type _nds32_vector_47, @function + _nds32_vector_47: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid48.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid48.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid48.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid48.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.48, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_48 + .type _nds32_vector_48, @function + _nds32_vector_48: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid49.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid49.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid49.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid49.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.49, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_49 + .type _nds32_vector_49, @function + _nds32_vector_49: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid50.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid50.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid50.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid50.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.50, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_50 + .type _nds32_vector_50, @function + _nds32_vector_50: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid51.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid51.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid51.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid51.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.51, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_51 + .type _nds32_vector_51, @function + _nds32_vector_51: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid52.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid52.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid52.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid52.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.52, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_52 + .type _nds32_vector_52, @function + _nds32_vector_52: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid53.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid53.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid53.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid53.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.53, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_53 + .type _nds32_vector_53, @function + _nds32_vector_53: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid54.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid54.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid54.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid54.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.54, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_54 + .type _nds32_vector_54, @function + _nds32_vector_54: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid55.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid55.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid55.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid55.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.55, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_55 + .type _nds32_vector_55, @function + _nds32_vector_55: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid56.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid56.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid56.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid56.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.56, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_56 + .type _nds32_vector_56, @function + _nds32_vector_56: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid57.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid57.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid57.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid57.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.57, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_57 + .type _nds32_vector_57, @function + _nds32_vector_57: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid58.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid58.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid58.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid58.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.58, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_58 + .type _nds32_vector_58, @function + _nds32_vector_58: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid59.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid59.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid59.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid59.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.59, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_59 + .type _nds32_vector_59, @function + _nds32_vector_59: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid60.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid60.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid60.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid60.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.60, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_60 + .type _nds32_vector_60, @function + _nds32_vector_60: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid61.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid61.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid61.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid61.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.61, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_61 + .type _nds32_vector_61, @function + _nds32_vector_61: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid62.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid62.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid62.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid62.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.62, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_62 + .type _nds32_vector_62, @function + _nds32_vector_62: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid63.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid63.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid63.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid63.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.63, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_63 + .type _nds32_vector_63, @function + _nds32_vector_63: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid64.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid64.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid64.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid64.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.64, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_64 + .type _nds32_vector_64, @function + _nds32_vector_64: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid65.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid65.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid65.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid65.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.65, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_65 + .type _nds32_vector_65, @function + _nds32_vector_65: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid66.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid66.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid66.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid66.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.66, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_66 + .type _nds32_vector_66, @function + _nds32_vector_66: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid67.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid67.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid67.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid67.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.67, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_67 + .type _nds32_vector_67, @function + _nds32_vector_67: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid68.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid68.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid68.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid68.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.68, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_68 + .type _nds32_vector_68, @function + _nds32_vector_68: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid69.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid69.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid69.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid69.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.69, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_69 + .type _nds32_vector_69, @function + _nds32_vector_69: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid70.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid70.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid70.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid70.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.70, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_70 + .type _nds32_vector_70, @function + _nds32_vector_70: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid71.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid71.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid71.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid71.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.71, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_71 + .type _nds32_vector_71, @function + _nds32_vector_71: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid72.S gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid72.S +--- gcc-8.2.0.orig/libgcc/config/nds32/isr-library/vec_vid72.S 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/isr-library/vec_vid72.S 2019-01-25 15:38:32.845242705 +0100 +@@ -24,8 +24,15 @@ + . */ + + .section .nds32_vector.72, "ax" ++#if __NDS32_ISR_VECTOR_SIZE_4__ ++ /* The vector size is default 4-byte for v3 architecture. */ ++ .vec_size 4 ++ .align 2 ++#else ++ /* The vector size is default 16-byte for other architectures. */ + .vec_size 16 + .align 4 ++#endif + .weak _nds32_vector_72 + .type _nds32_vector_72, @function + _nds32_vector_72: +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/linux-atomic.c gcc-8.2.0/libgcc/config/nds32/linux-atomic.c +--- gcc-8.2.0.orig/libgcc/config/nds32/linux-atomic.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/linux-atomic.c 2019-01-25 15:38:32.845242705 +0100 +@@ -0,0 +1,282 @@ ++/* Linux-specific atomic operations for NDS32 Linux. ++ Copyright (C) 2012-2018 Free Software Foundation, Inc. ++ ++This file is free software; you can redistribute it and/or modify it ++under the terms of the GNU General Public License as published by the ++Free Software Foundation; either version 3, or (at your option) any ++later version. ++ ++This file is distributed in the hope that it will be useful, but ++WITHOUT ANY WARRANTY; without even the implied warranty of ++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++General Public License for more details. ++ ++Under Section 7 of GPL version 3, you are granted additional ++permissions described in the GCC Runtime Library Exception, version ++3.1, as published by the Free Software Foundation. ++ ++You should have received a copy of the GNU General Public License and ++a copy of the GCC Runtime Library Exception along with this program; ++see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++. */ ++ ++/* We implement byte, short and int versions of each atomic operation ++ using the kernel helper defined below. There is no support for ++ 64-bit operations yet. */ ++ ++/* This function copy form NDS32 Linux-kernal. */ ++static inline int ++__kernel_cmpxchg (int oldval, int newval, int *mem) ++{ ++ int temp1, temp2, temp3, offset; ++ ++ asm volatile ("msync\tall\n" ++ "movi\t%0, #0\n" ++ "1:\n" ++ "\tllw\t%1, [%4+%0]\n" ++ "\tsub\t%3, %1, %6\n" ++ "\tcmovz\t%2, %5, %3\n" ++ "\tcmovn\t%2, %1, %3\n" ++ "\tscw\t%2, [%4+%0]\n" ++ "\tbeqz\t%2, 1b\n" ++ : "=&r" (offset), "=&r" (temp3), "=&r" (temp2), "=&r" (temp1) ++ : "r" (mem), "r" (newval), "r" (oldval) : "memory"); ++ ++ return temp1; ++} ++ ++#define HIDDEN __attribute__ ((visibility ("hidden"))) ++ ++#ifdef __NDS32_EL__ ++#define INVERT_MASK_1 0 ++#define INVERT_MASK_2 0 ++#else ++#define INVERT_MASK_1 24 ++#define INVERT_MASK_2 16 ++#endif ++ ++#define MASK_1 0xffu ++#define MASK_2 0xffffu ++ ++#define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP) \ ++ int HIDDEN \ ++ __sync_fetch_and_##OP##_4 (int *ptr, int val) \ ++ { \ ++ int failure, tmp; \ ++ \ ++ do { \ ++ tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \ ++ failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \ ++ } while (failure != 0); \ ++ \ ++ return tmp; \ ++ } ++ ++FETCH_AND_OP_WORD (add, , +) ++FETCH_AND_OP_WORD (sub, , -) ++FETCH_AND_OP_WORD (or, , |) ++FETCH_AND_OP_WORD (and, , &) ++FETCH_AND_OP_WORD (xor, , ^) ++FETCH_AND_OP_WORD (nand, ~, &) ++ ++#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH ++#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH ++ ++/* Implement both __sync__and_fetch and __sync_fetch_and_ for ++ subword-sized quantities. */ ++ ++#define SUBWORD_SYNC_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH, RETURN) \ ++ TYPE HIDDEN \ ++ NAME##_##RETURN (OP, WIDTH) (TYPE *ptr, TYPE val) \ ++ { \ ++ int *wordptr = (int *) ((unsigned long) ptr & ~3); \ ++ unsigned int mask, shift, oldval, newval; \ ++ int failure; \ ++ \ ++ shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ ++ mask = MASK_##WIDTH << shift; \ ++ \ ++ do { \ ++ oldval = __atomic_load_n (wordptr, __ATOMIC_SEQ_CST); \ ++ newval = ((PFX_OP (((oldval & mask) >> shift) \ ++ INF_OP (unsigned int) val)) << shift) & mask; \ ++ newval |= oldval & ~mask; \ ++ failure = __kernel_cmpxchg (oldval, newval, wordptr); \ ++ } while (failure != 0); \ ++ \ ++ return (RETURN & mask) >> shift; \ ++ } ++ ++ ++SUBWORD_SYNC_OP (add, , +, unsigned short, 2, oldval) ++SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, oldval) ++SUBWORD_SYNC_OP (or, , |, unsigned short, 2, oldval) ++SUBWORD_SYNC_OP (and, , &, unsigned short, 2, oldval) ++SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, oldval) ++SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, oldval) ++ ++SUBWORD_SYNC_OP (add, , +, unsigned char, 1, oldval) ++SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, oldval) ++SUBWORD_SYNC_OP (or, , |, unsigned char, 1, oldval) ++SUBWORD_SYNC_OP (and, , &, unsigned char, 1, oldval) ++SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, oldval) ++SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, oldval) ++ ++#define OP_AND_FETCH_WORD(OP, PFX_OP, INF_OP) \ ++ int HIDDEN \ ++ __sync_##OP##_and_fetch_4 (int *ptr, int val) \ ++ { \ ++ int tmp, failure; \ ++ \ ++ do { \ ++ tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \ ++ failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \ ++ } while (failure != 0); \ ++ \ ++ return PFX_OP (tmp INF_OP val); \ ++ } ++ ++OP_AND_FETCH_WORD (add, , +) ++OP_AND_FETCH_WORD (sub, , -) ++OP_AND_FETCH_WORD (or, , |) ++OP_AND_FETCH_WORD (and, , &) ++OP_AND_FETCH_WORD (xor, , ^) ++OP_AND_FETCH_WORD (nand, ~, &) ++ ++SUBWORD_SYNC_OP (add, , +, unsigned short, 2, newval) ++SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, newval) ++SUBWORD_SYNC_OP (or, , |, unsigned short, 2, newval) ++SUBWORD_SYNC_OP (and, , &, unsigned short, 2, newval) ++SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, newval) ++SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, newval) ++ ++SUBWORD_SYNC_OP (add, , +, unsigned char, 1, newval) ++SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, newval) ++SUBWORD_SYNC_OP (or, , |, unsigned char, 1, newval) ++SUBWORD_SYNC_OP (and, , &, unsigned char, 1, newval) ++SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, newval) ++SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, newval) ++ ++int HIDDEN ++__sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval) ++{ ++ int actual_oldval, fail; ++ ++ while (1) ++ { ++ actual_oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); ++ ++ if (oldval != actual_oldval) ++ return actual_oldval; ++ ++ fail = __kernel_cmpxchg (actual_oldval, newval, ptr); ++ ++ if (!fail) ++ return oldval; ++ } ++} ++ ++#define SUBWORD_VAL_CAS(TYPE, WIDTH) \ ++ TYPE HIDDEN \ ++ __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ ++ TYPE newval) \ ++ { \ ++ int *wordptr = (int *)((unsigned long) ptr & ~3), fail; \ ++ unsigned int mask, shift, actual_oldval, actual_newval; \ ++ \ ++ shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ ++ mask = MASK_##WIDTH << shift; \ ++ \ ++ while (1) \ ++ { \ ++ actual_oldval = __atomic_load_n (wordptr, __ATOMIC_SEQ_CST); \ ++ \ ++ if (((actual_oldval & mask) >> shift) != (unsigned int) oldval) \ ++ return (actual_oldval & mask) >> shift; \ ++ \ ++ actual_newval = (actual_oldval & ~mask) \ ++ | (((unsigned int) newval << shift) & mask); \ ++ \ ++ fail = __kernel_cmpxchg (actual_oldval, actual_newval, \ ++ wordptr); \ ++ \ ++ if (!fail) \ ++ return oldval; \ ++ } \ ++ } ++ ++SUBWORD_VAL_CAS (unsigned short, 2) ++SUBWORD_VAL_CAS (unsigned char, 1) ++ ++typedef unsigned char bool; ++ ++bool HIDDEN ++__sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval) ++{ ++ int failure = __kernel_cmpxchg (oldval, newval, ptr); ++ return (failure == 0); ++} ++ ++#define SUBWORD_BOOL_CAS(TYPE, WIDTH) \ ++ bool HIDDEN \ ++ __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ ++ TYPE newval) \ ++ { \ ++ TYPE actual_oldval \ ++ = __sync_val_compare_and_swap_##WIDTH (ptr, oldval, newval); \ ++ return (oldval == actual_oldval); \ ++ } ++ ++SUBWORD_BOOL_CAS (unsigned short, 2) ++SUBWORD_BOOL_CAS (unsigned char, 1) ++ ++int HIDDEN ++__sync_lock_test_and_set_4 (int *ptr, int val) ++{ ++ int failure, oldval; ++ ++ do { ++ oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); ++ failure = __kernel_cmpxchg (oldval, val, ptr); ++ } while (failure != 0); ++ ++ return oldval; ++} ++ ++#define SUBWORD_TEST_AND_SET(TYPE, WIDTH) \ ++ TYPE HIDDEN \ ++ __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val) \ ++ { \ ++ int failure; \ ++ unsigned int oldval, newval, shift, mask; \ ++ int *wordptr = (int *) ((unsigned long) ptr & ~3); \ ++ \ ++ shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ ++ mask = MASK_##WIDTH << shift; \ ++ \ ++ do { \ ++ oldval = __atomic_load_n (wordptr, __ATOMIC_SEQ_CST); \ ++ newval = (oldval & ~mask) \ ++ | (((unsigned int) val << shift) & mask); \ ++ failure = __kernel_cmpxchg (oldval, newval, wordptr); \ ++ } while (failure != 0); \ ++ \ ++ return (oldval & mask) >> shift; \ ++ } ++ ++SUBWORD_TEST_AND_SET (unsigned short, 2) ++SUBWORD_TEST_AND_SET (unsigned char, 1) ++ ++#define SYNC_LOCK_RELEASE(TYPE, WIDTH) \ ++ void HIDDEN \ ++ __sync_lock_release_##WIDTH (TYPE *ptr) \ ++ { \ ++ /* All writes before this point must be seen before we release \ ++ the lock itself. */ \ ++ __builtin_nds32_msync_all (); \ ++ *ptr = 0; \ ++ } ++ ++SYNC_LOCK_RELEASE (int, 4) ++SYNC_LOCK_RELEASE (short, 2) ++SYNC_LOCK_RELEASE (char, 1) +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/linux-unwind.h gcc-8.2.0/libgcc/config/nds32/linux-unwind.h +--- gcc-8.2.0.orig/libgcc/config/nds32/linux-unwind.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/linux-unwind.h 2019-01-25 15:38:32.845242705 +0100 +@@ -0,0 +1,143 @@ ++/* DWARF2 EH unwinding support for NDS32 Linux signal frame. ++ Copyright (C) 2014-2015 Free Software Foundation, Inc. ++ Contributed by Andes Technology Corporation. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++#ifndef inhibit_libc ++ ++/* Do code reading to identify a signal frame, and set the frame ++ state data appropriately. See unwind-dw2.c for the structs. ++ The corresponding bits in the Linux kernel are in ++ arch/nds32/kernel/signal.c. */ ++ ++#include ++#include ++#include ++ ++/* Exactly the same layout as the kernel structures, unique names. */ ++ ++/* arch/nds32/kernel/signal.c */ ++struct _rt_sigframe { ++ siginfo_t info; ++ struct ucontext_t uc; ++}; ++ ++#define RT_SIGRETURN 0x8b00f044 ++ ++#define MD_FALLBACK_FRAME_STATE_FOR nds32_fallback_frame_state ++ ++/* This function is supposed to be invoked by uw_frame_state_for() ++ when there is no unwind data available. ++ ++ Generally, given the _Unwind_Context CONTEXT for a stack frame, ++ we need to look up its caller and decode information into FS. ++ However, if the exception handling happens within a signal handler, ++ the return address of signal handler is a special module, which ++ contains signal return syscall and has no FDE in the .eh_frame section. ++ We need to implement MD_FALLBACK_FRAME_STATE_FOR so that we can ++ unwind through signal frames. */ ++static _Unwind_Reason_Code ++nds32_fallback_frame_state (struct _Unwind_Context *context, ++ _Unwind_FrameState *fs) ++{ ++ u_int32_t *pc = (u_int32_t *) context->ra; ++ struct sigcontext *sc_; ++ _Unwind_Ptr new_cfa; ++ ++#ifdef __NDS32_EB__ ++#error "Signal handler is not supported for force unwind." ++#endif ++ ++ if ((_Unwind_Ptr) pc & 3) ++ return _URC_END_OF_STACK; ++ ++ /* Check if we are going through a signal handler. ++ See arch/nds32/kernel/signal.c implementation. ++ FIXME: Currently we only handle little endian (EL) case. */ ++ if (pc[0] == RT_SIGRETURN) ++ { ++ /* Using '_sigfame' memory address to locate kernal's sigcontext. ++ The sigcontext structures in arch/nds32/include/asm/sigcontext.h. */ ++ struct _rt_sigframe *rt_; ++ rt_ = context->cfa; ++ sc_ = &rt_->uc.uc_mcontext; ++ } ++ else ++ return _URC_END_OF_STACK; ++ ++ /* Update cfa from sigcontext. */ ++ new_cfa = (_Unwind_Ptr) sc_; ++ fs->regs.cfa_how = CFA_REG_OFFSET; ++ fs->regs.cfa_reg = STACK_POINTER_REGNUM; ++ fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa; ++ ++#define NDS32_PUT_FS_REG(NUM, NAME) \ ++ (fs->regs.reg[NUM].how = REG_SAVED_OFFSET, \ ++ fs->regs.reg[NUM].loc.offset = (_Unwind_Ptr) &(sc_->NAME) - new_cfa) ++ ++ /* Restore all registers value. */ ++ NDS32_PUT_FS_REG (0, nds32_r0); ++ NDS32_PUT_FS_REG (1, nds32_r1); ++ NDS32_PUT_FS_REG (2, nds32_r2); ++ NDS32_PUT_FS_REG (3, nds32_r3); ++ NDS32_PUT_FS_REG (4, nds32_r4); ++ NDS32_PUT_FS_REG (5, nds32_r5); ++ NDS32_PUT_FS_REG (6, nds32_r6); ++ NDS32_PUT_FS_REG (7, nds32_r7); ++ NDS32_PUT_FS_REG (8, nds32_r8); ++ NDS32_PUT_FS_REG (9, nds32_r9); ++ NDS32_PUT_FS_REG (10, nds32_r10); ++ NDS32_PUT_FS_REG (11, nds32_r11); ++ NDS32_PUT_FS_REG (12, nds32_r12); ++ NDS32_PUT_FS_REG (13, nds32_r13); ++ NDS32_PUT_FS_REG (14, nds32_r14); ++ NDS32_PUT_FS_REG (15, nds32_r15); ++ NDS32_PUT_FS_REG (16, nds32_r16); ++ NDS32_PUT_FS_REG (17, nds32_r17); ++ NDS32_PUT_FS_REG (18, nds32_r18); ++ NDS32_PUT_FS_REG (19, nds32_r19); ++ NDS32_PUT_FS_REG (20, nds32_r20); ++ NDS32_PUT_FS_REG (21, nds32_r21); ++ NDS32_PUT_FS_REG (22, nds32_r22); ++ NDS32_PUT_FS_REG (23, nds32_r23); ++ NDS32_PUT_FS_REG (24, nds32_r24); ++ NDS32_PUT_FS_REG (25, nds32_r25); ++ ++ NDS32_PUT_FS_REG (28, nds32_fp); ++ NDS32_PUT_FS_REG (29, nds32_gp); ++ NDS32_PUT_FS_REG (30, nds32_lp); ++ NDS32_PUT_FS_REG (31, nds32_sp); ++ ++ /* Restore PC, point to trigger signal instruction. */ ++ NDS32_PUT_FS_REG (32, nds32_ipc); ++ ++#undef NDS32_PUT_FS_REG ++ ++ /* The retaddr is PC, use PC to find FDE. */ ++ fs->retaddr_column = 32; ++ fs->signal_frame = 1; ++ ++ return _URC_NO_REASON; ++} ++ ++#endif +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-glibc gcc-8.2.0/libgcc/config/nds32/t-nds32-glibc +--- gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-glibc 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/t-nds32-glibc 2019-01-25 15:38:37.357255536 +0100 +@@ -0,0 +1,34 @@ ++# Rules of glibc library makefile of Andes NDS32 cpu for GNU compiler ++# Copyright (C) 2012-2015 Free Software Foundation, Inc. ++# Contributed by Andes Technology Corporation. ++# ++# This file is part of GCC. ++# ++# GCC is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published ++# by the Free Software Foundation; either version 3, or (at your ++# option) any later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# Compiler flags to use when compiling 'libgcc2.c' ++HOST_LIBGCC2_CFLAGS = -O2 -fPIC -fwrapv ++LIB2ADD += $(srcdir)/config/nds32/linux-atomic.c ++ ++#LIB1ASMSRC = nds32/lib1asmsrc-newlib.S ++#LIB1ASMFUNCS = _divsi3 _modsi3 _udivsi3 _umodsi3 ++ ++# List of functions not to build from libgcc2.c. ++#LIB2FUNCS_EXCLUDE = _clzsi2 ++ ++# List of extra C and assembler files(*.S) to add to static libgcc2. ++#LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-newlib/_clzsi2.c ++ ++# ------------------------------------------------------------------------ +diff -urN gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-isr gcc-8.2.0/libgcc/config/nds32/t-nds32-isr +--- gcc-8.2.0.orig/libgcc/config/nds32/t-nds32-isr 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.2.0/libgcc/config/nds32/t-nds32-isr 2019-01-25 15:38:37.357255536 +0100 +@@ -23,11 +23,11 @@ + # Makfile fragment rules for libnds32_isr.a to support ISR attribute extension + ############################################################################### + +-# basic flags setting ++# Basic flags setting. + ISR_CFLAGS = $(CFLAGS) -c + +-# the object files we would like to create +-LIBNDS32_ISR_16B_OBJS = \ ++# The object files we would like to create. ++LIBNDS32_ISR_VEC_OBJS = \ + vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \ + vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \ + vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \ +@@ -46,40 +46,9 @@ + vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \ + vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \ + vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \ +- vec_vid72.o \ +- excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \ +- excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \ +- intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \ +- intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \ +- reset.o +- +-LIBNDS32_ISR_4B_OBJS = \ +- vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \ +- vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \ +- vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \ +- vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \ +- vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \ +- vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \ +- vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \ +- vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \ +- vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \ +- vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \ +- vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \ +- vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \ +- vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \ +- vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \ +- vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \ +- vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \ +- vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \ +- vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \ +- vec_vid72_4b.o \ +- excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \ +- excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \ +- intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \ +- intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \ +- reset_4b.o ++ vec_vid72.o + +-LIBNDS32_ISR_COMMON_OBJS = \ ++LIBNDS32_ISR_JMP_OBJS = \ + jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \ + jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \ + jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \ +@@ -98,29 +67,32 @@ + jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \ + jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \ + jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \ +- jmptbl_vid72.o \ ++ jmptbl_vid72.o ++ ++LIBNDS32_ISR_COMMON_OBJS = \ ++ excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \ ++ excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \ ++ intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \ ++ intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \ ++ reset.o \ + nmih.o \ + wrh.o + +-LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS) +- ++LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_VEC_OBJS) $(LIBNDS32_ISR_JMP_OBJS) $(LIBNDS32_ISR_COMMON_OBJS) + +-# Build common objects for ISR library +-nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o + +-wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o + +-jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S ++# Build vector vid objects for ISR library. ++vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ + + +- +-# Build 16b version objects for ISR library. (no "_4b" postfix string) +-vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S ++# Build jump table objects for ISR library. ++jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ + ++ ++# Build commen objects for ISR library. + excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o + +@@ -160,48 +132,12 @@ + reset.o: $(srcdir)/config/nds32/isr-library/reset.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o + +-# Build 4b version objects for ISR library. +-vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ +- +-excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o +- +-excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o +- +-excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o +- +-excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o +- +-excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o +- +-excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o +- +-intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o +- +-intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o +- +-intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o +- +-intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o +- +-intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o ++nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S ++ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o + +-intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o ++wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S ++ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o + +-reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S +- $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o + + + # The rule to create libnds32_isr.a file +diff -urN gcc-8.2.0.orig/libgcc/config.host gcc-8.2.0/libgcc/config.host +--- gcc-8.2.0.orig/libgcc/config.host 2018-04-06 22:04:17.000000000 +0200 ++++ gcc-8.2.0/libgcc/config.host 2019-01-25 15:38:32.841242694 +0100 +@@ -974,6 +974,23 @@ + tmake_file="$tm_file t-crtstuff t-fdpbit msp430/t-msp430" + extra_parts="$extra_parts libmul_none.a libmul_16.a libmul_32.a libmul_f5.a" + ;; ++nds32*-linux*) ++ # Basic makefile fragment and extra_parts for crt stuff. ++ # We also append c-isr library implementation. ++ tmake_file="${tmake_file} t-slibgcc-libgcc" ++ tmake_file="${tmake_file} nds32/t-nds32-glibc nds32/t-crtstuff t-softfp-sfdf t-softfp" ++ # The header file of defining MD_FALLBACK_FRAME_STATE_FOR. ++ md_unwind_header=nds32/linux-unwind.h ++ # Append library definition makefile fragment according to --with-nds32-lib=X setting. ++ case "${with_nds32_lib}" in ++ "" | glibc | uclibc ) ++ ;; ++ *) ++ echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: glibc uclibc" 1>&2 ++ exit 1 ++ ;; ++ esac ++ ;; + nds32*-elf*) + # Basic makefile fragment and extra_parts for crt stuff. + # We also append c-isr library implementation. diff --git a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum new file mode 100644 index 0000000000..b46ef8c46f --- /dev/null +++ b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum @@ -0,0 +1 @@ +c27f4499dd263fe4fb01bcc5565917f3698583b2 tarballs/gcc-8.3.0.tar.xz diff --git a/util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum deleted file mode 100644 index 767c6b0a98..0000000000 --- a/util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -306d27c3465fa36862c206738d06d65fff5c3645 tarballs/gcc-9.2.0.tar.xz diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 59908c5b08..3203d71899 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -185,6 +185,8 @@ detect_special_flags() { testcc "$GCC" "$CFLAGS_GCC -Wl,--build-id=none" && CFLAGS_GCC="$CFLAGS_GCC -Wl,--build-id=none" + testcc "$GCC" "$CFLAGS_GCC -Wno-address-of-packed-member" && + CFLAGS_GCC="$CFLAGS_GCC -Wno-address-of-packed-member" case "$architecture" in x86) ;; @@ -219,7 +221,7 @@ SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} GCC_CC_${TARCH}:=${GCC} GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} # Generally available for GCC's cc1: -GCC_CFLAGS_${TARCH}+=-fno-delete-null-pointer-checks -Wlogical-op -Wno-address-of-packed-member +GCC_CFLAGS_${TARCH}+=-fno-delete-null-pointer-checks -Wlogical-op GCC_ADAFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} From b4d9f229d4485c8cd42e7f1e07e2c592729e18b6 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 14 Mar 2020 10:34:29 +0100 Subject: [PATCH 0459/1463] nb/intel/i945/raminit: Simplify if condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use De Morgan’s law to simplify the condition by getting rid of the negations. TEST=With `make BUILD_TIMELESS=1` getac/p470 remains unchanged. Change-Id: I041f2740d6991f9b4e6b8f77988b970c028ca512 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39534 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i945/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c50b1d850e..a92118c338 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2437,8 +2437,8 @@ static void sdram_on_die_termination(struct sys_info *sysinfo) reg32 |= (1 << 14) | (1 << 6) | (2 << 16); MCHBAR32(ODTC) = reg32; - if (!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) { + if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { printk(BIOS_DEBUG, "one dimm per channel config..\n"); reg32 = MCHBAR32(C0ODT); From b159d443dd6e2bd977d30b3cb5db86b38430c1ea Mon Sep 17 00:00:00 2001 From: John Zhao Date: Thu, 12 Mar 2020 15:49:12 -0700 Subject: [PATCH 0460/1463] src/soc/tigerlake_dev: Update PMC IPC Hardware ID Change PMC IPC HID from INT34D2 to INTC1026 along with new kernel pmc ipc driver. BUG=b:148949891 BRANCH=none TEST=Boot on Volteer and validate DP tunneling. Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479 Tested-by: build bot (Jenkins) Reviewed-by: Divya S Sasidharan Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/acpi/pmc.asl | 32 ++++++++++++++++++++ src/soc/intel/tigerlake/acpi/southbridge.asl | 5 ++- 2 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 src/soc/intel/tigerlake/acpi/pmc.asl diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl new file mode 100644 index 0000000000..0d62edd926 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Scope (\_SB.PCI0) { + + Device (PMC) + { + Name (_HID, "INTC1026") + Name (_DDN, "Intel(R) Tiger Lake IPC Controller") + /* + * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. + * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + }) + } +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 8593d07326..9d25a735f5 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,6 +40,9 @@ /* PCIE Ports */ #include "pcie.asl" +/* pmc 0:1f.2 */ +#include "pmc.asl" + /* Serial IO */ #include "serialio.asl" From 2cf9d3883cc09aa2410135b87d715f47608ae38d Mon Sep 17 00:00:00 2001 From: li feng Date: Thu, 12 Mar 2020 16:09:53 -0700 Subject: [PATCH 0461/1463] soc/intel/tigerlake: Support ISH Add ACPI Object for ISH SSDT Enable/disable ISH based on devicetree BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo Signed-off-by: li feng Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/acpi/ish.asl | 22 +++++++++++++++++++ src/soc/intel/tigerlake/acpi/southbridge.asl | 3 +++ src/soc/intel/tigerlake/chip.c | 1 + .../intel/tigerlake/romstage/fsp_params_tgl.c | 7 ++++++ 4 files changed, 33 insertions(+) create mode 100644 src/soc/intel/tigerlake/acpi/ish.asl diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl new file mode 100644 index 0000000000..186a147f44 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/ish.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Integrated Sensor Hub Controller 0:12.0 */ + +Device (ISHB) +{ + Name (_ADR, 0x00120000) + Name (_DDN, "Integrated Sensor Hub Controller") +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 9d25a735f5..1403eb4b13 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -49,6 +49,9 @@ /* SMBus 0:1f.4 */ #include "smbus.asl" +/* ISH 0:12.0 */ +#include "ish.asl" + /* USB XHCI 0:14.0 */ #include "xhci.asl" diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 6f6e153ca6..dc36da34c4 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -71,6 +71,7 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index c5629a51c6..b46f3a3f10 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -89,6 +89,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, else m_cfg->InternalGfx = 0x1; + /* ISH */ + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + if (!dev || !dev->enabled) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = 1; + /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; m_cfg->DdiPortBConfig = config->DdiPortBConfig; From db992acb73611285ac433d9c7cdf09480be17b54 Mon Sep 17 00:00:00 2001 From: li feng Date: Thu, 12 Mar 2020 11:37:13 -0700 Subject: [PATCH 0462/1463] drivers/intel/ish: Add TGL ISH PCI id BRANCH=none BUG=b:145946347 TEST==boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo Signed-off-by: li feng Change-Id: I3a4f73e82f62def3adb2cb1332a315366078c918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39478 Reviewed-by: Wonkyu Kim Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/drivers/intel/ish/Kconfig | 1 + src/drivers/intel/ish/ish.c | 1 + src/include/device/pci_ids.h | 1 + 3 files changed, 3 insertions(+) diff --git a/src/drivers/intel/ish/Kconfig b/src/drivers/intel/ish/Kconfig index 635864e143..a2828d1349 100644 --- a/src/drivers/intel/ish/Kconfig +++ b/src/drivers/intel/ish/Kconfig @@ -1,5 +1,6 @@ config DRIVERS_INTEL_ISH bool + default n help When enabled, chip driver/intel/ish will publish information to the SSDT _DSD table for the ISH device. diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index e9d5ae96b1..d542bd371a 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -65,6 +65,7 @@ static const struct device_operations pci_ish_device_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_ISHB, PCI_DEVICE_ID_INTEL_CML_ISHB, + PCI_DEVICE_ID_INTEL_TGL_ISHB, 0 }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ccbfe4068d..3da326b7bc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2105,6 +2105,7 @@ #define PCI_DEVICE_ID_INTEL_82439TX 0x7100 #define PCI_DEVICE_ID_INTEL_CNL_ISHB 0x9dfc #define PCI_DEVICE_ID_INTEL_CML_ISHB 0x02fc +#define PCI_DEVICE_ID_INTEL_TGL_ISHB 0xa0fc /* Intel 82371FB (PIIX) */ #define PCI_DEVICE_ID_INTEL_82371FB_ISA 0x122e From 23954256533dff885b0291c11b1c00b63617a98d Mon Sep 17 00:00:00 2001 From: li feng Date: Thu, 12 Mar 2020 16:38:34 -0700 Subject: [PATCH 0463/1463] mb/intel/tglrvp: Enable ISH driver and register firmware name BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3, then copied ISH firmware to host file system /lib/firmware/intel/tglrvp_ish.bin check "dmesg |grep ish", it shows: ish-loader: ISH firmware intel/tglrvp_ish.bin loaded cros_ec_ishtp: Chrome EC device registered Those means shim loader in coreboot has loaded ISH firmware, and firmware is running successfully. Signed-off-by: Hu, Hebo Signed-off-by: li feng Change-Id: I1ee8050aef6ec0828f16ef2695b5347278caa820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39481 Reviewed-by: Wonkyu Kim Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/Kconfig | 1 + .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 7 ++++++- .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 7 ++++++- 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 2051a056a1..d60918fdb4 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select GENERATE_SMBIOS_TABLES select SOC_INTEL_TIGERLAKE select INTEL_LPSS_UART_FOR_CONSOLE + select DRIVERS_INTEL_ISH config CHROMEOS bool diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index a43011f02c..41a361c016 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -133,7 +133,12 @@ chip soc/intel/tigerlake device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 - device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.0 on # SensorHUB 0xA0FC + chip drivers/intel/ish + register "firmware_name" = ""tglrvp_ish.bin"" + device generic 0 on end + end + end device pci 12.6 off end # GSPI2 0x34FB device pci 13.0 off end # GSPI3 0xA0FD device pci 14.0 on end # USB3.1 xHCI 0xA0ED diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 643db36c2c..586fd26da7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -129,7 +129,12 @@ chip soc/intel/tigerlake device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 - device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.0 on # SensorHUB 0xA0FC + chip drivers/intel/ish + register "firmware_name" = ""tglrvp_ish.bin"" + device generic 0 on end + end + end device pci 12.6 off end # GSPI2 0x34FB device pci 13.0 off end # GSPI3 0xA0FD device pci 14.0 on end # USB3.1 xHCI 0xA0ED From dca20cd77f53d410fcc72cd1b6ec0939a4391f1d Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Wed, 29 Jan 2020 09:14:18 +0100 Subject: [PATCH 0464/1463] util/inteltool: Move Ice Lake definitions into their own header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Ice Lake definitions into its own header. Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/inteltool/gpio_groups.c | 488 +----------------------- util/inteltool/gpio_names/gpio_groups.h | 18 + util/inteltool/gpio_names/icelake.h | 478 +++++++++++++++++++++++ 3 files changed, 498 insertions(+), 486 deletions(-) create mode 100644 util/inteltool/gpio_names/gpio_groups.h create mode 100644 util/inteltool/gpio_names/icelake.h diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 4ec79c4c6e..62d0798a5b 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -23,23 +23,11 @@ #include "inteltool.h" #include "pcr.h" +#include "gpio_names/icelake.h" + #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -struct gpio_group { - const char *display; - size_t pad_count; - size_t func_count; - const char *const *pad_names; /* indexed by 'pad * func_count + func' */ -}; - -struct gpio_community { - const char *name; - uint8_t pcr_port_id; - size_t group_count; - const struct gpio_group *const *groups; -}; - /* * Names prefixed with an *asterisk are the default. * (if it's the first column, GPIO is the default, no matter the name) @@ -2157,478 +2145,6 @@ static const struct gpio_community *const cannonlake_pch_h_communities[] = { &cannonlake_pch_h_community_4, }; -/* Ice Lake-LP */ -static const char *const icelake_pch_h_group_g_names[] = { - /* GPP_G */ - "GPP_G0", "SD3_CMD", - "GPP_G1", "SD3_D0", - "GPP_G2", "SD3_D1", - "GPP_G3", "SD3_D2", - "GPP_G4", "SD3_D3", - "GPP_G5", "SD3_CDB", - "GPP_G6", "SD3_CLK", - "GPP_G7", "SD3_WP", -}; - -static const char *const icelake_pch_h_group_b_names[] = { - /* GPP_B */ - "GPP_B0", "CORE_VID_0", - "GPP_B1", "CORE_VID_1", - "GPP_B2", "VRALERTB", - "GPP_B3", "CPU_GP_2", - "GPP_B4", "CPU_GP_3", - "GPP_B5", "ISH_I2C0_SDA", - "GPP_B6", "ISH_I2C0_SCL", - "GPP_B7", "ISH_I2C1_SDA", - "GPP_B8", "ISH_I2C1_SCL", - "GPP_B9", "I2C5_SDA", - "GPP_B10", "I2C5_SCL", - "GPP_B11", "PMCALERTB", - "GPP_B12", "SLP_S0B", - "GPP_B13", "PLTRSTB", - "GPP_B14", "SPKR", - "GPP_B15", "GSPI0_CS0B", - "GPP_B16", "GSPI0_CLK", - "GPP_B17", "GSPI0_MISO", - "GPP_B18", "GSPI0_MOSI", - "GPP_B19", "GSPI1_CS0B", - "GPP_B20", "GSPI1_CLK", - "GPP_B21", "GSPI1_MISO", - "GPP_B22", "GSPI1_MOSI", - "GPP_B23", "SML1ALERTB", - "GPP_B24", "GSPI0_CLK_LOOPBK", - "GPP_B25", "GSPI1_CLK_LOOPBK", -}; - -static const char *const icelake_pch_h_group_a_names[] = { - /* GPP_A */ - "GPP_A0", "ESPI_IO_0", - "GPP_A1", "ESPI_IO_1", - "GPP_A2", "ESPI_IO_2", - "GPP_A3", "ESPI_IO_3", - "GPP_A4", "ESPI_CSB", - "GPP_A5", "ESPI_CLK", - "GPP_A6", "ESPI_RESETB", - "GPP_A7", "I2S2_SCLK", - "GPP_A8", "I2S2_SFRM", - "GPP_A9", "I2S2_TXD", - "GPP_A10", "I2S2_RXD", - "GPP_A11", "SATA_DEVSLP_2", - "GPP_A12", "SATAXPCIE_1", - "GPP_A13", "SATAXPCIE_2", - "GPP_A14", "USB2_OCB_1", - "GPP_A15", "USB2_OCB_2", - "GPP_A16", "USB2_OCB_3", - "GPP_A17", "DDSP_HPD_C", - "GPP_A18", "DDSP_HPD_B", - "GPP_A19", "DDSP_HPD_1", - "GPP_A20", "DDSP_HPD_2", - "GPP_A21", "I2S5_TXD", - "GPP_A22", "I2S5_RXD", - "GPP_A23", "I2S1_SCLK", - "GPP_A24", "ESPI_CLK_LOOPBK", -}; - -static const char *const icelake_pch_h_group_h_names[] = { - /* GPP_H */ - "GPP_H0", "SD_1P8_SEL", - "GPP_H1", "SD_PWR_EN_B", - "GPP_H2", "GPPC_H_2", - "GPP_H3", "SX_EXIT_HOLDOFFB", - "GPP_H4", "I2C2_SDA", - "GPP_H5", "I2C2_SCL", - "GPP_H6", "I2C3_SDA", - "GPP_H7", "I2C3_SCL", - "GPP_H8", "I2C4_SDA", - "GPP_H9", "I2C4_SCL", - "GPP_H10", "SRCCLKREQB_4", - "GPP_H11", "SRCCLKREQB_5", - "GPP_H12", "M2_SKT2_CFG_0", - "GPP_H13", "M2_SKT2_CFG_1", - "GPP_H14", "M2_SKT2_CFG_2", - "GPP_H15", "M2_SKT2_CFG_3", - "GPP_H16", "DDPB_CTRLCLK", - "GPP_H17", "DDPB_CTRLDATA", - "GPP_H18", "CPU_VCCIO_PWR_GATEB", - "GPP_H19", "TIME_SYNC_0", - "GPP_H20", "IMGCLKOUT_1", - "GPP_H21", "IMGCLKOUT_2", - "GPP_H22", "IMGCLKOUT_3", - "GPP_H23", "IMGCLKOUT_4", -}; - -static const char *const icelake_pch_h_group_d_names[] = { - /* GPP_D */ - "GPP_D0", "ISH_GP_0", - "GPP_D1", "ISH_GP_1", - "GPP_D2", "ISH_GP_2", - "GPP_D3", "ISH_GP_3", - "GPP_D4", "IMGCLKOUT_0", - "GPP_D5", "SRCCLKREQB_0", - "GPP_D6", "SRCCLKREQB_1", - "GPP_D7", "SRCCLKREQB_2", - "GPP_D8", "SRCCLKREQB_3", - "GPP_D9", "ISH_SPI_CSB", - "GPP_D10", "ISH_SPI_CLK", - "GPP_D11", "ISH_SPI_MISO", - "GPP_D12", "ISH_SPI_MOSI", - "GPP_D13", "ISH_UART0_RXD", - "GPP_D14", "ISH_UART0_TXD", - "GPP_D15", "ISH_UART0_RTSB", - "GPP_D16", "ISH_UART0_CTSB", - "GPP_D17", "ISH_GP_4", - "GPP_D18", "ISH_GP_5", - "GPP_D19", "I2S_MCLK", - "GPP_D10", "GSPI2_CLK_LOOPBK", -}; - -static const char *const icelake_pch_h_group_f_names[] = { - /* GPP_F */ - "GPP_F0", "CNV_BRI_DT", - "GPP_F1", "CNV_BRI_RSP", - "GPP_F2", "CNV_RGI_DT", - "GPP_F3", "CNV_RGI_RSP", - "GPP_F4", "CNV_RF_RESET_B", - "GPP_F5", "EMMC_HIP_MON", - "GPP_F6", "CNV_PA_BLANKING", - "GPP_F7", "EMMC_CMD", - "GPP_F8", "EMMC_DATA0", - "GPP_F9", "EMMC_DATA1", - "GPP_F10", "EMMC_DATA2", - "GPP_F11", "EMMC_DATA3", - "GPP_F12", "EMMC_DATA4", - "GPP_F13", "EMMC_DATA5", - "GPP_F14", "EMMC_DATA6", - "GPP_F15", "EMMC_DATA7", - "GPP_F16", "EMMC_RCLK", - "GPP_F17", "EMMC_CLK", - "GPP_F18", "EMMC_RESETB", - "GPP_F19", "A4WP_PRESENT", -}; - -static const char *const icelake_pch_h_group_vgpio_names[] = { - /* vGPIO */ - "CNV_BTEN", "", - "CNV_WCEN", "", - "CNV_BT_HOST_WAKEB", "", - "CNV_BT_IF_SELECT", "", - "vCNV_BT_UART_TXD", "", - "vCNV_BT_UART_RXD", "", - "vCNV_BT_UART_CTS_B", "", - "vCNV_BT_UART_RTS_B", "", - "vCNV_MFUART1_TXD", "", - "vCNV_MFUART1_RXD", "", - "vCNV_MFUART1_CTS_B", "", - "vCNV_MFUART1_RTS_B", "", - "vUART0_TXD", "", - "vUART0_RXD", "", - "vUART0_CTS_B", "", - "vUART0_RTS_B", "", - "vISH_UART0_TXD", "", - "vISH_UART0_RXD", "", - "vISH_UART0_CTS_B", "", - "vISH_UART0_RTS_B", "", - "vCNV_BT_I2S_BCLK", "", - "vCNV_BT_I2S_WS_SYNC", "", - "vCNV_BT_I2S_SDO", "", - "vCNV_BT_I2S_SDI", "", - "vI2S2_SCLK", "", - "vI2S2_SFRM", "", - "vI2S2_TXD", "", - "vI2S2_RXD", "", - "vSD3_CD_B", "", -}; - -static const char *const icelake_pch_h_group_c_names[] = { - /* GPP_C */ - "GPP_C0", "SMBCLK", - "GPP_C1", "SMBDATA", - "GPP_C2", "SMBALERTB", - "GPP_C3", "SML0CLK", - "GPP_C4", "SML0DATA", - "GPP_C5", "SML0ALERTB", - "GPP_C6", "SML1CLK", - "GPP_C7", "SML1DATA", - "GPP_C8", "UART0_RXD", - "GPP_C9", "UART0_TXD", - "GPP_C10", "UART0_RTSB", - "GPP_C11", "UART0_CTSB", - "GPP_C12", "UART1_RXD", - "GPP_C13", "UART1_TXD", - "GPP_C14", "UART1_RTSB", - "GPP_C15", "UART1_CTSB", - "GPP_C16", "I2C0_SDA", - "GPP_C17", "I2C0_SCL", - "GPP_C18", "I2C1_SDA", - "GPP_C19", "I2C1_SCL", - "GPP_C20", "UART2_RXD", - "GPP_C21", "UART2_TXD", - "GPP_C22", "UART2_RTSB", - "GPP_C23", "UART2_CTSB", -}; - -static const char *const icelake_pch_h_group_hvcmos_names[] = { - /* HVCMOS */ - "L_BKLTEN", "", - "L_BKLTCTL", "", - "L_VDDEN", "", - "SYS_PWROK", "", - "SYS_RESETB", "", - "MLK_RSTB", "", -}; - -static const char *const icelake_pch_h_group_e_names[] = { - /* GPP_E */ - "GPP_E0", "SATAXPCIE_0", - "GPP_E1", "SPI1_IO_2", - "GPP_E2", "SPI1_IO_3", - "GPP_E3", "CPU_GP_0", - "GPP_E4", "SATA_DEVSLP_0", - "GPP_E5", "SATA_DEVSLP_1", - "GPP_E6", "GPPC_E_6", - "GPP_E7", "CPU_GP_1", - "GPP_E8", "SATA_LEDB", - "GPP_E9", "USB2_OCB_0", - "GPP_E10", "SPI1_CSB", - "GPP_E11", "SPI1_CLK", - "GPP_E12", "SPI1_MISO_IO_1", - "GPP_E13", "SPI1_MOSI_IO_0", - "GPP_E14", "DDSP_HPD_A", - "GPP_E15", "ISH_GP_6", - "GPP_E16", "ISH_GP_7", - "GPP_E17", "DISP_MISC_4", - "GPP_E18", "DDP1_CTRLCLK", - "GPP_E19", "DDP1_CTRLDATA", - "GPP_E20", "DDP2_CTRLCLK", - "GPP_E21", "DDP2_CTRLDATA", - "GPP_E22", "DDPA_CTRLCLK", - "GPP_E23", "DDPA_CTRLDATA", -}; - -static const char *const icelake_pch_h_group_jtag_names[] = { - /* JTAG */ - "JTAG0", "JTAG_TDO", - "JTAG1", "JTAGX", - "JTAG2", "PRDYB", - "JTAG3", "PREQB", - "JTAG4", "CPU_TRSTB", - "JTAG5", "JTAG_TDI", - "JTAG6", "JTAG_TMS", - "JTAG7", "JTAG_TCK", - "JTAG8", "ITP_PMODE", -}; - -static const char *const icelake_pch_h_group_r_names[] = { - /* GPP_R */ - "GPP_R0", "HDA_BCLK", - "GPP_R1", "HDA_SYNC", - "GPP_R2", "HDA_SDO", - "GPP_R3", "HDA_SDI_0", - "GPP_R4", "HDA_RSTB", - "GPP_R5", "HDA_SDI_1", - "GPP_R6", "I2S1_TXD", - "GPP_R7", "I2S1_RXD", -}; - -static const char *const icelake_pch_h_group_s_names[] = { - /* GPP_S */ - "GPP_S0", "SNDW1_CLK", - "GPP_S1", "SNDW1_DATA", - "GPP_S2", "SNDW2_CLK", - "GPP_S3", "SNDW2_DATA", - "GPP_S4", "SNDW3_CLK", - "GPP_S5", "SNDW3_DATA", - "GPP_S6", "SNDW4_CLK", - "GPP_S7", "SNDW4_DATA", -}; - -static const char *const icelake_pch_h_group_spi_names[] = { - /* SPI */ - "SPIP0", "SPI0_IO_2", - "SPIP1", "SPI0_IO_3", - "SPIP2", "SPI0_MOSI_IO_0", - "SPIP3", "SPI0_MISO_IO_1", - "SPIP4", "SPI0_TPM_CSB", - "SPIP5", "SPI0_FLASH_0_CSB", - "SPIP6", "SPI0_FLASH_1_CSB", - "SPIP7", "SPI0_CLK", - "SPIP8", "SPI0_CLK_LOOPBK", -}; - -static const struct gpio_group icelake_pch_h_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_g_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_g_names, -}; - -static const struct gpio_group icelake_pch_h_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_b_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_b_names, -}; - -static const struct gpio_group icelake_pch_h_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_a_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_a_names, -}; - -static const struct gpio_group *const icelake_pch_h_community_0_groups[] = { - &icelake_pch_h_group_g, - &icelake_pch_h_group_b, - &icelake_pch_h_group_a, -}; - -static const struct gpio_community icelake_pch_h_community_0 = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0x6e, - .group_count = ARRAY_SIZE(icelake_pch_h_community_0_groups), - .groups = icelake_pch_h_community_0_groups, -}; - -static const struct gpio_group icelake_pch_h_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_h_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_h_names, -}; - -static const struct gpio_group icelake_pch_h_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_d_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_d_names, -}; - -static const struct gpio_group icelake_pch_h_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_f_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_f_names, -}; - -static const struct gpio_group icelake_pch_h_group_vgpio_0 = { - .display = "------- GPIO Group vGPIO_0 -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_vgpio_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_vgpio_names, -}; - -static const struct gpio_group *const icelake_pch_h_community_1_groups[] = { - &icelake_pch_h_group_h, - &icelake_pch_h_group_d, - &icelake_pch_h_group_f, - &icelake_pch_h_group_vgpio_0, -}; - -static const struct gpio_community icelake_pch_h_community_1 = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0x6d, - .group_count = ARRAY_SIZE(icelake_pch_h_community_1_groups), - .groups = icelake_pch_h_community_1_groups, -}; - - -static const struct gpio_community icelake_pch_h_community_2 = { - .name = "------- GPIO Community 2 (skipped)-------", - .pcr_port_id = 0x6c, - .group_count = 0, -}; - -static const struct gpio_community icelake_pch_h_community_3 = { - .name = "------- GPIO Community 3 (skipped)-------", - .pcr_port_id = 0x6b, - .group_count = 0, -}; - -static const struct gpio_group icelake_pch_h_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_c_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_c_names, -}; - -static const struct gpio_group icelake_pch_h_group_hvcmos = { - .display = "------- GPIO Group HVCMOS -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_hvcmos_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_hvcmos_names, -}; - -static const struct gpio_group icelake_pch_h_group_e = { - .display = "------- GPIO Group E -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_e_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_e_names, -}; - -static const struct gpio_group icelake_pch_h_group_jtag = { - .display = "------- GPIO Group JTAG -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_jtag_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_jtag_names, -}; - -static const struct gpio_group *const icelake_pch_h_community_4_groups[] = { - &icelake_pch_h_group_c, - &icelake_pch_h_group_hvcmos, - &icelake_pch_h_group_e, - &icelake_pch_h_group_jtag, -}; - -static const struct gpio_community icelake_pch_h_community_4 = { - .name = "------- GPIO Community 4 -------", - .pcr_port_id = 0x6a, - .group_count = ARRAY_SIZE(icelake_pch_h_community_4_groups), - .groups = icelake_pch_h_community_4_groups, -}; - -static const struct gpio_group icelake_pch_h_group_r = { - .display = "------- GPIO Group R -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_r_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_r_names, -}; - -static const struct gpio_group icelake_pch_h_group_s = { - .display = "------- GPIO Group S -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_s_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_s_names, -}; - -static const struct gpio_group icelake_pch_h_group_spi = { - .display = "------- GPIO Group SPI -------", - .pad_count = ARRAY_SIZE(icelake_pch_h_group_spi_names) / 2, - .func_count = 2, - .pad_names = icelake_pch_h_group_spi_names, -}; - -static const struct gpio_group *const icelake_pch_h_community_5_groups[] = { - &icelake_pch_h_group_r, - &icelake_pch_h_group_s, - &icelake_pch_h_group_spi, -}; - -static const struct gpio_community icelake_pch_h_community_5 = { - .name = "------- GPIO Community 5 -------", - .pcr_port_id = 0x69, - .group_count = ARRAY_SIZE(icelake_pch_h_community_5_groups), - .groups = icelake_pch_h_community_5_groups, -}; - -static const struct gpio_community *const icelake_pch_h_communities[] = { - &icelake_pch_h_community_0, - &icelake_pch_h_community_1, - &icelake_pch_h_community_2, - &icelake_pch_h_community_3, - &icelake_pch_h_community_4, - &icelake_pch_h_community_5, -}; - static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { diff --git a/util/inteltool/gpio_names/gpio_groups.h b/util/inteltool/gpio_names/gpio_groups.h new file mode 100644 index 0000000000..711b298bd3 --- /dev/null +++ b/util/inteltool/gpio_names/gpio_groups.h @@ -0,0 +1,18 @@ +#ifndef GPIO_NAMES_GPIO_GROUPS_H +#define GPIO_NAMES_GPIO_GROUPS_H + +struct gpio_group { + const char *display; + size_t pad_count; + size_t func_count; + const char *const *pad_names; /* indexed by 'pad * func_count + func' */ +}; + +struct gpio_community { + const char *name; + uint8_t pcr_port_id; + size_t group_count; + const struct gpio_group *const *groups; +}; + +#endif diff --git a/util/inteltool/gpio_names/icelake.h b/util/inteltool/gpio_names/icelake.h new file mode 100644 index 0000000000..48b8431943 --- /dev/null +++ b/util/inteltool/gpio_names/icelake.h @@ -0,0 +1,478 @@ +#ifndef GPIO_NAMES_ICELAKE_H +#define GPIO_NAMES_ICELAKE_H + +#include "gpio_groups.h" + +static const char *const icelake_pch_h_group_g_names[] = { + /* GPP_G */ + "GPP_G0", "SD3_CMD", + "GPP_G1", "SD3_D0", + "GPP_G2", "SD3_D1", + "GPP_G3", "SD3_D2", + "GPP_G4", "SD3_D3", + "GPP_G5", "SD3_CDB", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +static const char *const icelake_pch_h_group_b_names[] = { + /* GPP_B */ + "GPP_B0", "CORE_VID_0", + "GPP_B1", "CORE_VID_1", + "GPP_B2", "VRALERTB", + "GPP_B3", "CPU_GP_2", + "GPP_B4", "CPU_GP_3", + "GPP_B5", "ISH_I2C0_SDA", + "GPP_B6", "ISH_I2C0_SCL", + "GPP_B7", "ISH_I2C1_SDA", + "GPP_B8", "ISH_I2C1_SCL", + "GPP_B9", "I2C5_SDA", + "GPP_B10", "I2C5_SCL", + "GPP_B11", "PMCALERTB", + "GPP_B12", "SLP_S0B", + "GPP_B13", "PLTRSTB", + "GPP_B14", "SPKR", + "GPP_B15", "GSPI0_CS0B", + "GPP_B16", "GSPI0_CLK", + "GPP_B17", "GSPI0_MISO", + "GPP_B18", "GSPI0_MOSI", + "GPP_B19", "GSPI1_CS0B", + "GPP_B20", "GSPI1_CLK", + "GPP_B21", "GSPI1_MISO", + "GPP_B22", "GSPI1_MOSI", + "GPP_B23", "SML1ALERTB", + "GPP_B24", "GSPI0_CLK_LOOPBK", + "GPP_B25", "GSPI1_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_a_names[] = { + /* GPP_A */ + "GPP_A0", "ESPI_IO_0", + "GPP_A1", "ESPI_IO_1", + "GPP_A2", "ESPI_IO_2", + "GPP_A3", "ESPI_IO_3", + "GPP_A4", "ESPI_CSB", + "GPP_A5", "ESPI_CLK", + "GPP_A6", "ESPI_RESETB", + "GPP_A7", "I2S2_SCLK", + "GPP_A8", "I2S2_SFRM", + "GPP_A9", "I2S2_TXD", + "GPP_A10", "I2S2_RXD", + "GPP_A11", "SATA_DEVSLP_2", + "GPP_A12", "SATAXPCIE_1", + "GPP_A13", "SATAXPCIE_2", + "GPP_A14", "USB2_OCB_1", + "GPP_A15", "USB2_OCB_2", + "GPP_A16", "USB2_OCB_3", + "GPP_A17", "DDSP_HPD_C", + "GPP_A18", "DDSP_HPD_B", + "GPP_A19", "DDSP_HPD_1", + "GPP_A20", "DDSP_HPD_2", + "GPP_A21", "I2S5_TXD", + "GPP_A22", "I2S5_RXD", + "GPP_A23", "I2S1_SCLK", + "GPP_A24", "ESPI_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_h_names[] = { + /* GPP_H */ + "GPP_H0", "SD_1P8_SEL", + "GPP_H1", "SD_PWR_EN_B", + "GPP_H2", "GPPC_H_2", + "GPP_H3", "SX_EXIT_HOLDOFFB", + "GPP_H4", "I2C2_SDA", + "GPP_H5", "I2C2_SCL", + "GPP_H6", "I2C3_SDA", + "GPP_H7", "I2C3_SCL", + "GPP_H8", "I2C4_SDA", + "GPP_H9", "I2C4_SCL", + "GPP_H10", "SRCCLKREQB_4", + "GPP_H11", "SRCCLKREQB_5", + "GPP_H12", "M2_SKT2_CFG_0", + "GPP_H13", "M2_SKT2_CFG_1", + "GPP_H14", "M2_SKT2_CFG_2", + "GPP_H15", "M2_SKT2_CFG_3", + "GPP_H16", "DDPB_CTRLCLK", + "GPP_H17", "DDPB_CTRLDATA", + "GPP_H18", "CPU_VCCIO_PWR_GATEB", + "GPP_H19", "TIME_SYNC_0", + "GPP_H20", "IMGCLKOUT_1", + "GPP_H21", "IMGCLKOUT_2", + "GPP_H22", "IMGCLKOUT_3", + "GPP_H23", "IMGCLKOUT_4", +}; + +static const char *const icelake_pch_h_group_d_names[] = { + /* GPP_D */ + "GPP_D0", "ISH_GP_0", + "GPP_D1", "ISH_GP_1", + "GPP_D2", "ISH_GP_2", + "GPP_D3", "ISH_GP_3", + "GPP_D4", "IMGCLKOUT_0", + "GPP_D5", "SRCCLKREQB_0", + "GPP_D6", "SRCCLKREQB_1", + "GPP_D7", "SRCCLKREQB_2", + "GPP_D8", "SRCCLKREQB_3", + "GPP_D9", "ISH_SPI_CSB", + "GPP_D10", "ISH_SPI_CLK", + "GPP_D11", "ISH_SPI_MISO", + "GPP_D12", "ISH_SPI_MOSI", + "GPP_D13", "ISH_UART0_RXD", + "GPP_D14", "ISH_UART0_TXD", + "GPP_D15", "ISH_UART0_RTSB", + "GPP_D16", "ISH_UART0_CTSB", + "GPP_D17", "ISH_GP_4", + "GPP_D18", "ISH_GP_5", + "GPP_D19", "I2S_MCLK", + "GPP_D10", "GSPI2_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_f_names[] = { + /* GPP_F */ + "GPP_F0", "CNV_BRI_DT", + "GPP_F1", "CNV_BRI_RSP", + "GPP_F2", "CNV_RGI_DT", + "GPP_F3", "CNV_RGI_RSP", + "GPP_F4", "CNV_RF_RESET_B", + "GPP_F5", "EMMC_HIP_MON", + "GPP_F6", "CNV_PA_BLANKING", + "GPP_F7", "EMMC_CMD", + "GPP_F8", "EMMC_DATA0", + "GPP_F9", "EMMC_DATA1", + "GPP_F10", "EMMC_DATA2", + "GPP_F11", "EMMC_DATA3", + "GPP_F12", "EMMC_DATA4", + "GPP_F13", "EMMC_DATA5", + "GPP_F14", "EMMC_DATA6", + "GPP_F15", "EMMC_DATA7", + "GPP_F16", "EMMC_RCLK", + "GPP_F17", "EMMC_CLK", + "GPP_F18", "EMMC_RESETB", + "GPP_F19", "A4WP_PRESENT", +}; + +static const char *const icelake_pch_h_group_vgpio_names[] = { + /* vGPIO */ + "CNV_BTEN", "", + "CNV_WCEN", "", + "CNV_BT_HOST_WAKEB", "", + "CNV_BT_IF_SELECT", "", + "vCNV_BT_UART_TXD", "", + "vCNV_BT_UART_RXD", "", + "vCNV_BT_UART_CTS_B", "", + "vCNV_BT_UART_RTS_B", "", + "vCNV_MFUART1_TXD", "", + "vCNV_MFUART1_RXD", "", + "vCNV_MFUART1_CTS_B", "", + "vCNV_MFUART1_RTS_B", "", + "vUART0_TXD", "", + "vUART0_RXD", "", + "vUART0_CTS_B", "", + "vUART0_RTS_B", "", + "vISH_UART0_TXD", "", + "vISH_UART0_RXD", "", + "vISH_UART0_CTS_B", "", + "vISH_UART0_RTS_B", "", + "vCNV_BT_I2S_BCLK", "", + "vCNV_BT_I2S_WS_SYNC", "", + "vCNV_BT_I2S_SDO", "", + "vCNV_BT_I2S_SDI", "", + "vI2S2_SCLK", "", + "vI2S2_SFRM", "", + "vI2S2_TXD", "", + "vI2S2_RXD", "", + "vSD3_CD_B", "", +}; + +static const char *const icelake_pch_h_group_c_names[] = { + /* GPP_C */ + "GPP_C0", "SMBCLK", + "GPP_C1", "SMBDATA", + "GPP_C2", "SMBALERTB", + "GPP_C3", "SML0CLK", + "GPP_C4", "SML0DATA", + "GPP_C5", "SML0ALERTB", + "GPP_C6", "SML1CLK", + "GPP_C7", "SML1DATA", + "GPP_C8", "UART0_RXD", + "GPP_C9", "UART0_TXD", + "GPP_C10", "UART0_RTSB", + "GPP_C11", "UART0_CTSB", + "GPP_C12", "UART1_RXD", + "GPP_C13", "UART1_TXD", + "GPP_C14", "UART1_RTSB", + "GPP_C15", "UART1_CTSB", + "GPP_C16", "I2C0_SDA", + "GPP_C17", "I2C0_SCL", + "GPP_C18", "I2C1_SDA", + "GPP_C19", "I2C1_SCL", + "GPP_C20", "UART2_RXD", + "GPP_C21", "UART2_TXD", + "GPP_C22", "UART2_RTSB", + "GPP_C23", "UART2_CTSB", +}; + +static const char *const icelake_pch_h_group_hvcmos_names[] = { + /* HVCMOS */ + "L_BKLTEN", "", + "L_BKLTCTL", "", + "L_VDDEN", "", + "SYS_PWROK", "", + "SYS_RESETB", "", + "MLK_RSTB", "", +}; + +static const char *const icelake_pch_h_group_e_names[] = { + /* GPP_E */ + "GPP_E0", "SATAXPCIE_0", + "GPP_E1", "SPI1_IO_2", + "GPP_E2", "SPI1_IO_3", + "GPP_E3", "CPU_GP_0", + "GPP_E4", "SATA_DEVSLP_0", + "GPP_E5", "SATA_DEVSLP_1", + "GPP_E6", "GPPC_E_6", + "GPP_E7", "CPU_GP_1", + "GPP_E8", "SATA_LEDB", + "GPP_E9", "USB2_OCB_0", + "GPP_E10", "SPI1_CSB", + "GPP_E11", "SPI1_CLK", + "GPP_E12", "SPI1_MISO_IO_1", + "GPP_E13", "SPI1_MOSI_IO_0", + "GPP_E14", "DDSP_HPD_A", + "GPP_E15", "ISH_GP_6", + "GPP_E16", "ISH_GP_7", + "GPP_E17", "DISP_MISC_4", + "GPP_E18", "DDP1_CTRLCLK", + "GPP_E19", "DDP1_CTRLDATA", + "GPP_E20", "DDP2_CTRLCLK", + "GPP_E21", "DDP2_CTRLDATA", + "GPP_E22", "DDPA_CTRLCLK", + "GPP_E23", "DDPA_CTRLDATA", +}; + +static const char *const icelake_pch_h_group_jtag_names[] = { + /* JTAG */ + "JTAG0", "JTAG_TDO", + "JTAG1", "JTAGX", + "JTAG2", "PRDYB", + "JTAG3", "PREQB", + "JTAG4", "CPU_TRSTB", + "JTAG5", "JTAG_TDI", + "JTAG6", "JTAG_TMS", + "JTAG7", "JTAG_TCK", + "JTAG8", "ITP_PMODE", +}; + +static const char *const icelake_pch_h_group_r_names[] = { + /* GPP_R */ + "GPP_R0", "HDA_BCLK", + "GPP_R1", "HDA_SYNC", + "GPP_R2", "HDA_SDO", + "GPP_R3", "HDA_SDI_0", + "GPP_R4", "HDA_RSTB", + "GPP_R5", "HDA_SDI_1", + "GPP_R6", "I2S1_TXD", + "GPP_R7", "I2S1_RXD", +}; + +static const char *const icelake_pch_h_group_s_names[] = { + /* GPP_S */ + "GPP_S0", "SNDW1_CLK", + "GPP_S1", "SNDW1_DATA", + "GPP_S2", "SNDW2_CLK", + "GPP_S3", "SNDW2_DATA", + "GPP_S4", "SNDW3_CLK", + "GPP_S5", "SNDW3_DATA", + "GPP_S6", "SNDW4_CLK", + "GPP_S7", "SNDW4_DATA", +}; + +static const char *const icelake_pch_h_group_spi_names[] = { + /* SPI */ + "SPIP0", "SPI0_IO_2", + "SPIP1", "SPI0_IO_3", + "SPIP2", "SPI0_MOSI_IO_0", + "SPIP3", "SPI0_MISO_IO_1", + "SPIP4", "SPI0_TPM_CSB", + "SPIP5", "SPI0_FLASH_0_CSB", + "SPIP6", "SPI0_FLASH_1_CSB", + "SPIP7", "SPI0_CLK", + "SPIP8", "SPI0_CLK_LOOPBK", +}; + +/* Ice Lake-LP */ +static const struct gpio_group icelake_pch_h_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_g_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_g_names, +}; + +static const struct gpio_group icelake_pch_h_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_b_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_b_names, +}; + +static const struct gpio_group icelake_pch_h_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_a_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_a_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_0_groups[] = { + &icelake_pch_h_group_g, + &icelake_pch_h_group_b, + &icelake_pch_h_group_a, +}; + +static const struct gpio_community icelake_pch_h_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(icelake_pch_h_community_0_groups), + .groups = icelake_pch_h_community_0_groups, +}; + +static const struct gpio_group icelake_pch_h_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_h_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_h_names, +}; + +static const struct gpio_group icelake_pch_h_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_d_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_d_names, +}; + +static const struct gpio_group icelake_pch_h_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_f_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_f_names, +}; + +static const struct gpio_group icelake_pch_h_group_vgpio_0 = { + .display = "------- GPIO Group vGPIO_0 -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_vgpio_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_1_groups[] = { + &icelake_pch_h_group_h, + &icelake_pch_h_group_d, + &icelake_pch_h_group_f, + &icelake_pch_h_group_vgpio_0, +}; + +static const struct gpio_community icelake_pch_h_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(icelake_pch_h_community_1_groups), + .groups = icelake_pch_h_community_1_groups, +}; + + +static const struct gpio_community icelake_pch_h_community_2 = { + .name = "------- GPIO Community 2 (skipped)-------", + .pcr_port_id = 0x6c, + .group_count = 0, +}; + +static const struct gpio_community icelake_pch_h_community_3 = { + .name = "------- GPIO Community 3 (skipped)-------", + .pcr_port_id = 0x6b, + .group_count = 0, +}; + +static const struct gpio_group icelake_pch_h_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_c_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_c_names, +}; + +static const struct gpio_group icelake_pch_h_group_hvcmos = { + .display = "------- GPIO Group HVCMOS -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_hvcmos_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_hvcmos_names, +}; + +static const struct gpio_group icelake_pch_h_group_e = { + .display = "------- GPIO Group E -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_e_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_e_names, +}; + +static const struct gpio_group icelake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_jtag_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_4_groups[] = { + &icelake_pch_h_group_c, + &icelake_pch_h_group_hvcmos, + &icelake_pch_h_group_e, + &icelake_pch_h_group_jtag, +}; + +static const struct gpio_community icelake_pch_h_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(icelake_pch_h_community_4_groups), + .groups = icelake_pch_h_community_4_groups, +}; + +static const struct gpio_group icelake_pch_h_group_r = { + .display = "------- GPIO Group R -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_r_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_r_names, +}; + +static const struct gpio_group icelake_pch_h_group_s = { + .display = "------- GPIO Group S -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_s_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_s_names, +}; + +static const struct gpio_group icelake_pch_h_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_spi_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_spi_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_5_groups[] = { + &icelake_pch_h_group_r, + &icelake_pch_h_group_s, + &icelake_pch_h_group_spi, +}; + +static const struct gpio_community icelake_pch_h_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(icelake_pch_h_community_5_groups), + .groups = icelake_pch_h_community_5_groups, +}; + +static const struct gpio_community *const icelake_pch_h_communities[] = { + &icelake_pch_h_community_0, + &icelake_pch_h_community_1, + &icelake_pch_h_community_2, + &icelake_pch_h_community_3, + &icelake_pch_h_community_4, + &icelake_pch_h_community_5, +}; + +#endif From d5a65304c07e746b0f4dfc05cfc1af2bfc54b54e Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Wed, 29 Jan 2020 09:16:06 +0100 Subject: [PATCH 0465/1463] util/inteltool: Move Cannon Lake definitions into their own header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Cannon Lake definitions into its own header. Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Tested-by: build bot (Jenkins) --- util/inteltool/gpio_groups.c | 521 +----------------------- util/inteltool/gpio_names/cannonlake.h | 526 +++++++++++++++++++++++++ 2 files changed, 527 insertions(+), 520 deletions(-) create mode 100644 util/inteltool/gpio_names/cannonlake.h diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 62d0798a5b..ae494aa1d9 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -23,6 +23,7 @@ #include "inteltool.h" #include "pcr.h" +#include "gpio_names/cannonlake.h" #include "gpio_names/icelake.h" #define SBBAR_SIZE (16 * MiB) @@ -1625,526 +1626,6 @@ static const struct gpio_community *const denverton_communities[] = { &denverton_community_north, &denverton_community_south, }; - -static const char *const cannonlake_pch_h_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUSACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", - "GPIO_RSVD_0", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_a_names) / 4, - .func_count = 4, - .pad_names = cannonlake_pch_h_group_a_names, -}; - -static const char *const cannonlake_pch_h_group_b_names[] = { - "GPP_B0", "GSPI0_CS1#", "n/a", - "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", - "GPP_B2", "VRALERT#", "n/a", - "GPP_B3", "CPU_GP2", "n/a", - "GPP_B4", "CPU_GP3", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", - "GPP_B11", "I2S_MCLK", "n/a", - "GPP_B12", "SLP_S0#", "n/a", - "GPP_B13", "PLTRST#", "n/a", - "GPP_B14", "SPKR", "n/a", - "GPP_B15", "GSPI0_CS0#", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", - "GPP_B19", "GSPI1_CS0#", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", - "GPIO_RSVD_1", "n/a", "n/a", - "GPIO_RSVD_2", "n/a", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_b_names) / 3, - .func_count = 3, - .pad_names = cannonlake_pch_h_group_b_names, -}; - -static const char *const cannonlake_pch_h_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", - "GPP_C1", "SMBDATA", "n/a", - "GPP_C2", "SMBALERT#", "n/a", - "GPP_C3", "SML0CLK", "n/a", - "GPP_C4", "SML0DATA", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", - "GPP_C6", "SML1CLK", "n/a", - "GPP_C7", "SML1DATA", "n/a", - "GPP_C8", "UART0A_RXD", "n/a", - "GPP_C9", "UART0A_TXD", "n/a", - "GPP_C10", "UART0A_RTS#", "n/a", - "GPP_C11", "UART0A_CTS#", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", - "GPP_C16", "I2C0_SDA", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", - "GPP_C20", "UART2_RXD", "n/a", - "GPP_C21", "UART2_TXD", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_c_names) / 3, - .func_count = 3, - .pad_names = cannonlake_pch_h_group_c_names, -}; - -static const char *const cannonlake_pch_h_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "n/a", "SBK0", "BK0", - "GPP_D1", "SPI1_CLK", "n/a", "SBK1", "BK1", - "GPP_D2", "SPI1_MISO", "n/a", "SBK2", "BK2", - "GPP_D3", "SPI1_MOSI", "n/a", "SBK3", "BK3", - "GPP_D4", "I2C2_SDA", "I2C3_SDA", "SBK4", "BK4", - "GPP_D5", "I2S2_SFRM", "n/a", "CNV_RF_RESET#", "n/a", - "GPP_D6", "I2S2_TXD", "n/a", "MODEM_CLKREQ", "n/a", - "GPP_D7", "I2S2_RXD", "n/a", "n/a", "n/a", - "GPP_D8", "I2S2_SCLK", "n/a", "n/a", "n/a", - "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", "n/a", - "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", "n/a", - "GPP_D11", "ISH_SPI_MISO", "GP_BSSB_CLK", "GSPI2_MISO", "n/a", - "GPP_D12", "ISH_SPI_MOSI", "GP_BSSB_DI", "GSPI2_MOSI", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", "n/a", - "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", "n/a", - "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", "CNV_WFEN", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "CNV_WCEN", - "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", "n/a", - "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_d_names) / 5, - .func_count = 5, - .pad_names = cannonlake_pch_h_group_d_names, -}; - -static const char *const cannonlake_pch_h_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", - "GPP_E1", "SATAXPCIE1", "SATAGP1", - "GPP_E2", "SATAXPCIE2", "SATAGP2", - "GPP_E3", "CPU_GP0", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", - "GPP_E7", "CPU_GP1", "n/a", - "GPP_E8", "SATALED#", "n/a", - "GPP_E9", "USB2_OC0#", "n/a", - "GPP_E10", "USB2_OC1#", "n/a", - "GPP_E11", "USB2_OC2#", "n/a", - "GPP_E12", "USB2_OC3#", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_e_names) / 3, - .func_count = 3, - .pad_names = cannonlake_pch_h_group_e_names, -}; - -static const char *const cannonlake_pch_h_group_f_names[] = { - "GPP_F0", "SATAXPCIE3", "SATAGP3", - "GPP_F1", "SATAXPCIE4", "SATAGP4", - "GPP_F2", "SATAXPCIE5", "SATAGP5", - "GPP_F3", "SATAXPCIE6", "SATAGP6", - "GPP_F4", "SATAXPCIE7", "SATAGP7", - "GPP_F5", "SATA_DEVSLP3", "n/a", - "GPP_F6", "SATA_DEVSLP4", "n/a", - "GPP_F7", "SATA_DEVSLP5", "n/a", - "GPP_F8", "SATA_DEVSLP6", "n/a", - "GPP_F9", "SATA_DEVSLP7", "n/a", - "GPP_F10", "SATA_SCLOCK", "n/a", - "GPP_F11", "SATA_SLOAD", "n/a", - "GPP_F12", "SATA_SDATAOUT1", "n/a", - "GPP_F13", "SATA_SDATAOUT0", "n/a", - "GPP_F14", "n/a", "PS_ON#", - "GPP_F15", "USB2_OC4#", "n/a", - "GPP_F16", "USB2_OC5#", "n/a", - "GPP_F17", "USB2_OC6#", "n/a", - "GPP_F18", "USB2_OC7#", "n/a", - "GPP_F19", "eDP_VDDEN", "n/a", - "GPP_F20", "eDP_BKLTEN", "n/a", - "GPP_F21", "eDP_BKLTCTL", "n/a", - "GPP_F22", "DDPF_CTRLCLK", "n/a", - "GPP_F23", "DDPF_CTRLDATA", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_f_names) / 3, - .func_count = 3, - .pad_names = cannonlake_pch_h_group_f_names, -}; - -static const char *const cannonlake_pch_h_group_spi_names[] = { - "GPIO_RSVD_11", - "GPIO_RSVD_12", - "GPIO_RSVD_13", - "GPIO_RSVD_14", - "GPIO_RSVD_15", - "GPIO_RSVD_16", - "GPIO_RSVD_17", - "GPIO_RSVD_18", - "GPIO_RSVD_19", -}; - -static const struct gpio_group cannonlake_pch_h_group_spi = { - .display = "------- GPIO Group SPI -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 1, - .func_count = 1, - .pad_names = cannonlake_pch_h_group_spi_names, -}; - -static const char *const cannonlake_pch_h_group_g_names[] = { - "GPP_G0", "SD_CMD", - "GPP_G1", "SD_DATA0", - "GPP_G2", "SD_DATA1", - "GPP_G3", "SD_DATA2", - "GPP_G4", "SD_DATA3", - "GPP_G5", "SD_CD#", - "GPP_G6", "SD_CLK", - "GPP_G7", "SD_WP", -}; - -static const struct gpio_group cannonlake_pch_h_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_g_names) / 2, - .func_count = 2, - .pad_names = cannonlake_pch_h_group_g_names, -}; - -static const char *const cannonlake_pch_h_group_aza_names[] = { - "GPIO_RSVD_3", - "GPIO_RSVD_4", - "GPIO_RSVD_5", - "GPIO_RSVD_6", - "GPIO_RSVD_7", - "GPIO_RSVD_8", - "GPIO_RSVD_9", - "GPIO_RSVD_10", -}; - -static const struct gpio_group cannonlake_pch_h_group_aza = { - .display = "------- GPIO Grpoup AZA -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 1, - .func_count = 1, - .pad_names = cannonlake_pch_h_group_aza_names, -}; - -static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { - "CNV_BTEN", - "CNV_GNEN", - "CNV_WFEN", - "CNV_WCEN", - "CNV_BT_HOST_WAKEB", - "vCNV_GNSS_HOST_WAKEB", - "vSD3_CD_B", - "CNV_BT_IF_SELECT", - "vCNV_BT_UART_TXD", - "vCNV_BT_UART_RXD", - "vCNV_BT_UART_CTS_B", - "vCNV_BT_UART_RTS_B", - "vCNV_MFUART1_TXD", - "vCNV_MFUART1_RXD", - "vCNV_MFUART1_CTS_B", - "vCNV_MFUART1_RTS_B", - "vCNV_GNSS_UART_TXD", - "vCNV_GNSS_UART_RXD", - "vCNV_GNSS_UART_CTS_B", - "vCNV_GNSS_UART_RTS_B", - "vUART0_TXD", - "vUART0_RXD", - "vUART0_CTS_B", - "vUART0_RTSB", - "vISH_UART0_TXD", - "vISH_UART0_RXD", - "vISH_UART0_CTS_B", - "vISH_UART0_RTSB", - "vISH_UART1_TXD", - "vISH_UART1_RXD", - "vISH_UART1_CTS_B", - "vISH_UART1_RTS_B", -}; - -static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = { - .display = "------- GPIO Grpoup VGPIO_0 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 1, - .func_count = 1, - .pad_names = cannonlake_pch_h_group_vgpio_0_names, -}; - -static const char *const cannonlake_pch_h_group_vgpio_1_names[] = { - "vCNV_BT_I2S_BCLK", - "vCNV_BT_I2S_WS_SYNC", - "vCNV_BT_I2S_SDO", - "vCNV_BT_I2S_SDI", - "vSSP2_SCLK", - "vSSP2_SFRM", - "vSSP2_TXD", - "vSSP2_RXD", -}; - -static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = { - .display = "------- GPIO Grpoup VGPIO_1 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 1, - .func_count = 1, - .pad_names = cannonlake_pch_h_group_vgpio_1_names, -}; - -static const char *const cannonlake_pch_h_group_h_names[] = { - "GPP_H0", "SRCCLKREQ6#", - "GPP_H1", "SRCCLKREQ7#", - "GPP_H2", "SRCCLKREQ8#", - "GPP_H3", "SRCCLKREQ9#", - "GPP_H4", "SRCCLKREQ10#", - "GPP_H5", "SRCCLKREQ11#", - "GPP_H6", "SRCCLKREQ12#", - "GPP_H7", "SRCCLKREQ13#", - "GPP_H8", "SRCCLKREQ14#", - "GPP_H9", "SRCCLKREQ15#", - "GPP_H10", "SML2CLK", - "GPP_H11", "SML2DATA", - "GPP_H12", "SML2ALERT#", - "GPP_H13", "SML3CLK", - "GPP_H14", "SML3DATA", - "GPP_H15", "SML3ALERT#", - "GPP_H16", "SML4CLK", - "GPP_H17", "SML4DATA", - "GPP_H18", "SML4ALERT#", - "GPP_H19", "ISH_I2C0_SDA", - "GPP_H20", "ISH_I2C0_SCL", - "GPP_H21", "ISH_I2C1_SDA", - "GPP_H22", "ISH_I2C1_SCL", - "GPP_H23", "TIME_SYNC0", -}; - -static const struct gpio_group cannonlake_pch_h_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_h_names) / 2, - .func_count = 2, - .pad_names = cannonlake_pch_h_group_h_names, -}; - -static const char *const cannonlake_pch_h_group_i_names[] = { - "GPP_I0", "DDPB_HPD0", "DISP_MISC0", - "GPP_I1", "DDPB_HPD1", "DISP_MISC1", - "GPP_I2", "DDPB_HPD2", "DISP_MISC2", - "GPP_I3", "DDPB_HPD3", "DISP_MISC3", - "GPP_I4", "EDP_HPD", "DISP_MISC4", - "GPP_I5", "DDPB_CTRLCLK", "n/a", - "GPP_I6", "DDPB_CTRLDATA", "n/a", - "GPP_I7", "DDPC_CTRLCLK", "n/a", - "GPP_I8", "DDPC_CTRLDATA", "n/a", - "GPP_I9", "DDPD_CTRLCLK", "n/a", - "GPP_I10", "DDPD_CTRLDATA", "n/a", - "GPP_I11", "M2_SKT2_CFG0", "n/a", - "GPP_I12", "M2_SKT2_CFG1", "n/a", - "GPP_I13", "M2_SKT2_CFG2", "n/a", - "GPP_I14", "M2_SKT2_CFG3", "n/a", - "GPIO_RSVD_40", "n/a", "n/a", - "GPIO_RSVD_41", "n/a", "n/a", - "GPIO_RSVD_42", "n/a", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_i = { - .display = "-------GPIO Group GPP_I -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3, - .func_count = 3, - .pad_names = cannonlake_pch_h_group_i_names, -}; - -static const char *const cannonlake_pch_h_group_j_names[] = { - "GPP_J0", "CNV_PA_BLANKING", "n/a", - "GPP_J1", "n/a", "CPU_C10_GATE#", - "GPP_J2", "n/a", "n/a", - "GPP_J3", "n/a", "n/a", - "GPP_J4", "CNV_BRI_DT", "UART0B_RTS#", - "GPP_J5", "CNV_BRI_RSP", "UART0B_RXD", - "GPP_J6", "CNV_RGI_DT", "UART0B_TXD", - "GPP_J7", "CNV_RGI_RSP", "UART0B_CTS#", - "GPP_J8", "CNV_MFUART2_RXD", "n/a", - "GPP_J9", "CNV_MFUART2_TXD", "n/a", - "GPP_J10", "n/a", "n/a", - "GPP_J11", "A4WP_PRESENT", "n/a", -}; - -static const struct gpio_group cannonlake_pch_h_group_j = { - .display = "------- GPIO Group GPP_J -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_j_names) / 3, - .func_count = 3, - .pad_names = cannonlake_pch_h_group_j_names, -}; - -static const char *const cannonlake_pch_h_group_k_names[] = { - "GPP_K0", "n/a", - "GPP_K1", "n/a", - "GPP_K2", "n/a", - "GPP_K3", "n/a", - "GPP_K4", "n/a", - "GPP_K5", "n/a", - "GPP_K6", "n/a", - "GPP_K7", "n/a", - "GPP_K8", "Reserved", - "GPP_K9", "Reserved", - "GPP_K10", "Reserved", - "GPP_K11", "Reserved", - "GPP_K12", "GSXOUT", - "GPP_K13", "GSXSLOAD", - "GPP_K14", "GSXDIN", - "GPP_K15", "GSXSRESET#", - "GPP_K16", "GSXCLK", - "GPP_K17", "ADR_COMPLETE", - "GPP_K18", "NMI#", - "GPP_K19", "SMI#", - "GPP_K20", "Reserved", - "GPP_K21", "Reserved", - "GPP_K22", "IMGCLKOUT0", - "GPP_K23", "IMGCLKOUT1", -}; - -static const struct gpio_group cannonlake_pch_h_group_k = { - .display = "------- GPIO Group GPP_K -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_k_names) / 2, - .func_count = 2, - .pad_names = cannonlake_pch_h_group_k_names, -}; - -static const char *const cannonlake_pch_h_group_gpd_names[] = { - "GPD0", "BATLOW#", - "GPD1", "ACPRESENT", - "GPD2", "LAN_WAKE#", - "GPD3", "PRWBTN#", - "GPD4", "SLP_S3#", - "GPD5", "SLP_S4#", - "GPD6", "SLP_A#", - "GPD7", "n/a", - "GPD8", "SUSCLK", - "GPD9", "SLP_WLAN#", - "GPD10", "SLP_S5#", - "GPD11", "LANPHYPC", -}; -static const struct gpio_group cannonlake_pch_h_group_gpd = { - .display = "------- GPIO Group GPD -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_gpd_names) / 2, - .func_count = 2, - .pad_names = cannonlake_pch_h_group_gpd_names, -}; - -static const struct gpio_group *const cannonlake_pch_h_community_0_groups[] = { - &cannonlake_pch_h_group_a, - &cannonlake_pch_h_group_b, -}; -static const struct gpio_community cannonlake_pch_h_community_0 = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0x6e, - .group_count = ARRAY_SIZE(cannonlake_pch_h_community_0_groups), - .groups = cannonlake_pch_h_community_0_groups, -}; - -static const struct gpio_group *const cannonlake_pch_h_community_1_groups[] = { - &cannonlake_pch_h_group_c, - &cannonlake_pch_h_group_d, - &cannonlake_pch_h_group_g, - &cannonlake_pch_h_group_aza, - &cannonlake_pch_h_group_vgpio_0, - &cannonlake_pch_h_group_vgpio_1, -}; -static const struct gpio_community cannonlake_pch_h_community_1 = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0x6d, - .group_count = ARRAY_SIZE(cannonlake_pch_h_community_1_groups), - .groups = cannonlake_pch_h_community_1_groups, -}; - -static const struct gpio_group *const cannonlake_pch_h_community_2_groups[] = { - &cannonlake_pch_h_group_gpd, -}; -static const struct gpio_community cannonlake_pch_h_community_2 = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0x6c, - .group_count = ARRAY_SIZE(cannonlake_pch_h_community_2_groups), - .groups = cannonlake_pch_h_community_2_groups, -}; - -static const struct gpio_group *const cannonlake_pch_h_community_3_groups[] = { - &cannonlake_pch_h_group_k, - &cannonlake_pch_h_group_h, - &cannonlake_pch_h_group_e, - &cannonlake_pch_h_group_f, - &cannonlake_pch_h_group_spi, -}; -static const struct gpio_community cannonlake_pch_h_community_3 = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0x6b, - .group_count = ARRAY_SIZE(cannonlake_pch_h_community_3_groups), - .groups = cannonlake_pch_h_community_3_groups, -}; - -static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = { - &cannonlake_pch_h_group_i, - &cannonlake_pch_h_group_j, -}; -static const struct gpio_community cannonlake_pch_h_community_4 = { - .name = "------- GPIO Community 4 -------", - .pcr_port_id = 0x6a, - .group_count = ARRAY_SIZE(cannonlake_pch_h_community_4_groups), - .groups = cannonlake_pch_h_community_4_groups, -}; - -static const struct gpio_community *const cannonlake_pch_h_communities[] = { - &cannonlake_pch_h_community_0, - &cannonlake_pch_h_community_1, - &cannonlake_pch_h_community_2, - &cannonlake_pch_h_community_3, - &cannonlake_pch_h_community_4, -}; - static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h new file mode 100644 index 0000000000..5d806941f0 --- /dev/null +++ b/util/inteltool/gpio_names/cannonlake.h @@ -0,0 +1,526 @@ +#ifndef GPIO_NAMES_CANNONLAKE_H +#define GPIO_NAMES_CANNONLAKE_H + +#include "gpio_groups.h" + +static const char *const cannonlake_pch_h_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "GPIO_RSVD_0", "n/a", "n/a", "n/a", +}; + +static const char *const cannonlake_pch_h_group_b_names[] = { + "GPP_B0", "GSPI0_CS1#", "n/a", + "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "I2S_MCLK", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GPIO_RSVD_1", "n/a", "n/a", + "GPIO_RSVD_2", "n/a", "n/a", +}; + +static const char *const cannonlake_pch_h_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", + "GPP_C1", "SMBDATA", "n/a", + "GPP_C2", "SMBALERT#", "n/a", + "GPP_C3", "SML0CLK", "n/a", + "GPP_C4", "SML0DATA", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", + "GPP_C6", "SML1CLK", "n/a", + "GPP_C7", "SML1DATA", "n/a", + "GPP_C8", "UART0A_RXD", "n/a", + "GPP_C9", "UART0A_TXD", "n/a", + "GPP_C10", "UART0A_RTS#", "n/a", + "GPP_C11", "UART0A_CTS#", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", + "GPP_C16", "I2C0_SDA", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", + "GPP_C20", "UART2_RXD", "n/a", + "GPP_C21", "UART2_TXD", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", +}; + +static const char *const cannonlake_pch_h_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "SBK0", "BK0", + "GPP_D1", "SPI1_CLK", "n/a", "SBK1", "BK1", + "GPP_D2", "SPI1_MISO", "n/a", "SBK2", "BK2", + "GPP_D3", "SPI1_MOSI", "n/a", "SBK3", "BK3", + "GPP_D4", "I2C2_SDA", "I2C3_SDA", "SBK4", "BK4", + "GPP_D5", "I2S2_SFRM", "n/a", "CNV_RF_RESET#", "n/a", + "GPP_D6", "I2S2_TXD", "n/a", "MODEM_CLKREQ", "n/a", + "GPP_D7", "I2S2_RXD", "n/a", "n/a", "n/a", + "GPP_D8", "I2S2_SCLK", "n/a", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", "n/a", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", "n/a", + "GPP_D11", "ISH_SPI_MISO", "GP_BSSB_CLK", "GSPI2_MISO", "n/a", + "GPP_D12", "ISH_SPI_MOSI", "GP_BSSB_DI", "GSPI2_MOSI", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", "CNV_WFEN", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "CNV_WCEN", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", "n/a", + "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", "n/a", +}; + +static const char *const cannonlake_pch_h_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", + "GPP_E1", "SATAXPCIE1", "SATAGP1", + "GPP_E2", "SATAXPCIE2", "SATAGP2", + "GPP_E3", "CPU_GP0", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", + "GPP_E7", "CPU_GP1", "n/a", + "GPP_E8", "SATALED#", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", +}; + +static const char *const cannonlake_pch_h_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", + "GPP_F13", "SATA_SDATAOUT0", "n/a", + "GPP_F14", "n/a", "PS_ON#", + "GPP_F15", "USB2_OC4#", "n/a", + "GPP_F16", "USB2_OC5#", "n/a", + "GPP_F17", "USB2_OC6#", "n/a", + "GPP_F18", "USB2_OC7#", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", + "GPP_F22", "DDPF_CTRLCLK", "n/a", + "GPP_F23", "DDPF_CTRLDATA", "n/a", +}; + +static const char *const cannonlake_pch_h_group_spi_names[] = { + "GPIO_RSVD_11", + "GPIO_RSVD_12", + "GPIO_RSVD_13", + "GPIO_RSVD_14", + "GPIO_RSVD_15", + "GPIO_RSVD_16", + "GPIO_RSVD_17", + "GPIO_RSVD_18", + "GPIO_RSVD_19", +}; + +static const char *const cannonlake_pch_h_group_g_names[] = { + "GPP_G0", "SD_CMD", + "GPP_G1", "SD_DATA0", + "GPP_G2", "SD_DATA1", + "GPP_G3", "SD_DATA2", + "GPP_G4", "SD_DATA3", + "GPP_G5", "SD_CD#", + "GPP_G6", "SD_CLK", + "GPP_G7", "SD_WP", +}; + +static const char *const cannonlake_pch_h_group_aza_names[] = { + "GPIO_RSVD_3", + "GPIO_RSVD_4", + "GPIO_RSVD_5", + "GPIO_RSVD_6", + "GPIO_RSVD_7", + "GPIO_RSVD_8", + "GPIO_RSVD_9", + "GPIO_RSVD_10", +}; + +static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { + "CNV_BTEN", + "CNV_GNEN", + "CNV_WFEN", + "CNV_WCEN", + "CNV_BT_HOST_WAKEB", + "vCNV_GNSS_HOST_WAKEB", + "vSD3_CD_B", + "CNV_BT_IF_SELECT", + "vCNV_BT_UART_TXD", + "vCNV_BT_UART_RXD", + "vCNV_BT_UART_CTS_B", + "vCNV_BT_UART_RTS_B", + "vCNV_MFUART1_TXD", + "vCNV_MFUART1_RXD", + "vCNV_MFUART1_CTS_B", + "vCNV_MFUART1_RTS_B", + "vCNV_GNSS_UART_TXD", + "vCNV_GNSS_UART_RXD", + "vCNV_GNSS_UART_CTS_B", + "vCNV_GNSS_UART_RTS_B", + "vUART0_TXD", + "vUART0_RXD", + "vUART0_CTS_B", + "vUART0_RTSB", + "vISH_UART0_TXD", + "vISH_UART0_RXD", + "vISH_UART0_CTS_B", + "vISH_UART0_RTSB", + "vISH_UART1_TXD", + "vISH_UART1_RXD", + "vISH_UART1_CTS_B", + "vISH_UART1_RTS_B", +}; + +static const char *const cannonlake_pch_h_group_vgpio_1_names[] = { + "vCNV_BT_I2S_BCLK", + "vCNV_BT_I2S_WS_SYNC", + "vCNV_BT_I2S_SDO", + "vCNV_BT_I2S_SDI", + "vSSP2_SCLK", + "vSSP2_SFRM", + "vSSP2_TXD", + "vSSP2_RXD", +}; + +static const char *const cannonlake_pch_h_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", + "GPP_H1", "SRCCLKREQ7#", + "GPP_H2", "SRCCLKREQ8#", + "GPP_H3", "SRCCLKREQ9#", + "GPP_H4", "SRCCLKREQ10#", + "GPP_H5", "SRCCLKREQ11#", + "GPP_H6", "SRCCLKREQ12#", + "GPP_H7", "SRCCLKREQ13#", + "GPP_H8", "SRCCLKREQ14#", + "GPP_H9", "SRCCLKREQ15#", + "GPP_H10", "SML2CLK", + "GPP_H11", "SML2DATA", + "GPP_H12", "SML2ALERT#", + "GPP_H13", "SML3CLK", + "GPP_H14", "SML3DATA", + "GPP_H15", "SML3ALERT#", + "GPP_H16", "SML4CLK", + "GPP_H17", "SML4DATA", + "GPP_H18", "SML4ALERT#", + "GPP_H19", "ISH_I2C0_SDA", + "GPP_H20", "ISH_I2C0_SCL", + "GPP_H21", "ISH_I2C1_SDA", + "GPP_H22", "ISH_I2C1_SCL", + "GPP_H23", "TIME_SYNC0", +}; + +static const char *const cannonlake_pch_h_group_i_names[] = { + "GPP_I0", "DDPB_HPD0", "DISP_MISC0", + "GPP_I1", "DDPB_HPD1", "DISP_MISC1", + "GPP_I2", "DDPB_HPD2", "DISP_MISC2", + "GPP_I3", "DDPB_HPD3", "DISP_MISC3", + "GPP_I4", "EDP_HPD", "DISP_MISC4", + "GPP_I5", "DDPB_CTRLCLK", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", + "GPP_I9", "DDPD_CTRLCLK", "n/a", + "GPP_I10", "DDPD_CTRLDATA", "n/a", + "GPP_I11", "M2_SKT2_CFG0", "n/a", + "GPP_I12", "M2_SKT2_CFG1", "n/a", + "GPP_I13", "M2_SKT2_CFG2", "n/a", + "GPP_I14", "M2_SKT2_CFG3", "n/a", + "GPIO_RSVD_40", "n/a", "n/a", + "GPIO_RSVD_41", "n/a", "n/a", + "GPIO_RSVD_42", "n/a", "n/a", +}; + +static const char *const cannonlake_pch_h_group_j_names[] = { + "GPP_J0", "CNV_PA_BLANKING", "n/a", + "GPP_J1", "n/a", "CPU_C10_GATE#", + "GPP_J2", "n/a", "n/a", + "GPP_J3", "n/a", "n/a", + "GPP_J4", "CNV_BRI_DT", "UART0B_RTS#", + "GPP_J5", "CNV_BRI_RSP", "UART0B_RXD", + "GPP_J6", "CNV_RGI_DT", "UART0B_TXD", + "GPP_J7", "CNV_RGI_RSP", "UART0B_CTS#", + "GPP_J8", "CNV_MFUART2_RXD", "n/a", + "GPP_J9", "CNV_MFUART2_TXD", "n/a", + "GPP_J10", "n/a", "n/a", + "GPP_J11", "A4WP_PRESENT", "n/a", +}; + +static const char *const cannonlake_pch_h_group_k_names[] = { + "GPP_K0", "n/a", + "GPP_K1", "n/a", + "GPP_K2", "n/a", + "GPP_K3", "n/a", + "GPP_K4", "n/a", + "GPP_K5", "n/a", + "GPP_K6", "n/a", + "GPP_K7", "n/a", + "GPP_K8", "Reserved", + "GPP_K9", "Reserved", + "GPP_K10", "Reserved", + "GPP_K11", "Reserved", + "GPP_K12", "GSXOUT", + "GPP_K13", "GSXSLOAD", + "GPP_K14", "GSXDIN", + "GPP_K15", "GSXSRESET#", + "GPP_K16", "GSXCLK", + "GPP_K17", "ADR_COMPLETE", + "GPP_K18", "NMI#", + "GPP_K19", "SMI#", + "GPP_K20", "Reserved", + "GPP_K21", "Reserved", + "GPP_K22", "IMGCLKOUT0", + "GPP_K23", "IMGCLKOUT1", +}; + +static const char *const cannonlake_pch_h_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PRWBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", +}; + +static const struct gpio_group cannonlake_pch_h_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_a_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_h_group_a_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_b_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_h_group_b_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_c_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_h_group_c_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_d_names) / 5, + .func_count = 5, + .pad_names = cannonlake_pch_h_group_d_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_e_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_h_group_e_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_f_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_h_group_f_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 1, + .func_count = 1, + .pad_names = cannonlake_pch_h_group_spi_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_g_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_g_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_aza = { + .display = "------- GPIO Grpoup AZA -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 1, + .func_count = 1, + .pad_names = cannonlake_pch_h_group_aza_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = { + .display = "------- GPIO Grpoup VGPIO_0 -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 1, + .func_count = 1, + .pad_names = cannonlake_pch_h_group_vgpio_0_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = { + .display = "------- GPIO Grpoup VGPIO_1 -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 1, + .func_count = 1, + .pad_names = cannonlake_pch_h_group_vgpio_1_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_h_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_h_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_i = { + .display = "-------GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_h_group_i_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_j = { + .display = "------- GPIO Group GPP_J -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_j_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_h_group_j_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_k = { + .display = "------- GPIO Group GPP_K -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_k_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_k_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_gpd_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_gpd_names, +}; + +static const struct gpio_group *const cannonlake_pch_h_community_0_groups[] = { + &cannonlake_pch_h_group_a, + &cannonlake_pch_h_group_b, +}; +static const struct gpio_community cannonlake_pch_h_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(cannonlake_pch_h_community_0_groups), + .groups = cannonlake_pch_h_community_0_groups, +}; + +static const struct gpio_group *const cannonlake_pch_h_community_1_groups[] = { + &cannonlake_pch_h_group_c, + &cannonlake_pch_h_group_d, + &cannonlake_pch_h_group_g, + &cannonlake_pch_h_group_aza, + &cannonlake_pch_h_group_vgpio_0, + &cannonlake_pch_h_group_vgpio_1, +}; +static const struct gpio_community cannonlake_pch_h_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(cannonlake_pch_h_community_1_groups), + .groups = cannonlake_pch_h_community_1_groups, +}; + +static const struct gpio_group *const cannonlake_pch_h_community_2_groups[] = { + &cannonlake_pch_h_group_gpd, +}; +static const struct gpio_community cannonlake_pch_h_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(cannonlake_pch_h_community_2_groups), + .groups = cannonlake_pch_h_community_2_groups, +}; + +static const struct gpio_group *const cannonlake_pch_h_community_3_groups[] = { + &cannonlake_pch_h_group_k, + &cannonlake_pch_h_group_h, + &cannonlake_pch_h_group_e, + &cannonlake_pch_h_group_f, + &cannonlake_pch_h_group_spi, +}; +static const struct gpio_community cannonlake_pch_h_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(cannonlake_pch_h_community_3_groups), + .groups = cannonlake_pch_h_community_3_groups, +}; + +static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = { + &cannonlake_pch_h_group_i, + &cannonlake_pch_h_group_j, +}; +static const struct gpio_community cannonlake_pch_h_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(cannonlake_pch_h_community_4_groups), + .groups = cannonlake_pch_h_community_4_groups, +}; + +static const struct gpio_community *const cannonlake_pch_h_communities[] = { + &cannonlake_pch_h_community_0, + &cannonlake_pch_h_community_1, + &cannonlake_pch_h_community_2, + &cannonlake_pch_h_community_3, + &cannonlake_pch_h_community_4, +}; + +#endif From f80c5d9133ccd727353975fe7720bb14112a0ea6 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Wed, 29 Jan 2020 09:20:23 +0100 Subject: [PATCH 0466/1463] util/inteltool: Move Apollo Lake definitions into their own header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Apollo Lake definitions into its own header. Change-Id: I44b21092f5495f758c1f2151a913c074dfc658f5 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38627 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Tested-by: build bot (Jenkins) --- util/inteltool/gpio_groups.c | 341 +----------------------- util/inteltool/gpio_names/apollolake.h | 345 +++++++++++++++++++++++++ 2 files changed, 346 insertions(+), 340 deletions(-) create mode 100644 util/inteltool/gpio_names/apollolake.h diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index ae494aa1d9..c19f37406c 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -23,352 +23,13 @@ #include "inteltool.h" #include "pcr.h" +#include "gpio_names/apollolake.h" #include "gpio_names/cannonlake.h" #include "gpio_names/icelake.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -/* - * Names prefixed with an *asterisk are the default. - * (if it's the first column, GPIO is the default, no matter the name) - */ - -static const char *const apl_group_north_names[] = { - "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_2", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_3", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_4", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_5", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_6", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_7", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_8", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_9", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_10", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_11", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_12", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_13", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_14", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_15", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_16", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_17", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_18", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_19", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_20", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_21", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_22", "n/a", "n/a", "n/a", "n/a", "SATA_GP0", - "*GPIO_23", "n/a", "n/a", "n/a", "n/a", "SATA_GP1", - "*GPIO_24", "n/a", "n/a", "n/a", "n/a", "SATA_DEVSLP0", - "*GPIO_25", "n/a", "n/a", "n/a", "n/a", "SATA_DEVSLP1", - "*GPIO_26", "n/a", "n/a", "n/a", "n/a", "SATA_LEDN", - "*GPIO_27", "n/a", "n/a", "n/a", "n/a", "n/a", - "*GPIO_28", "n/a", "ISH_GPIO_10", "n/a", "n/a", "n/a", - "*GPIO_29", "n/a", "ISH_GPIO_11", "n/a", "n/a", "n/a", - "*GPIO_30", "ISH_GPIO_12", "n/a", "n/a", "n/a", "n/a", - "*GPIO_31", "ISH_GPIO_13", "n/a", "n/a", "n/a", "SUSCLK1", - "*GPIO_32", "ISH_GPIO_14", "n/a", "n/a", "n/a", "SUSCLK2", - "*GPIO_33", "ISH_GPIO_15", "n/a", "n/a", "n/a", "SUSCLK3", - "*GPIO_34", "PWM0", "n/a", "n/a", "n/a", "n/a", - "*GPIO_35", "PWM1", "n/a", "n/a", "n/a", "n/a", - "*GPIO_36", "PWM2", "n/a", "n/a", "n/a", "n/a", - "*GPIO_37", "PWM3", "n/a", "n/a", "n/a", "n/a", - "*GPIO_38", "LPSS_UART0_RXD", "n/a", "n/a", "n/a", "n/a", - "*GPIO_39", "LPSS_UART0_TXD", "n/a", "n/a", "n/a", "n/a", - "*GPIO_40", "LPSS_UART0_RTS_N", "n/a", "n/a", "n/a", "n/a", - "*GPIO_41", "LPSS_UART0_CTS_N", "n/a", "n/a", "n/a", "n/a", - "*GPIO_42", "LPSS_UART1_RXD", "n/a", "n/a", "n/a", "n/a", - "*GPIO_43", "LPSS_UART1_TXD", "n/a", "n/a", "n/a", "n/a", - "*GPIO_44", "LPSS_UART1_RTS_N", "n/a", "n/a", "n/a", "n/a", - "*GPIO_45", "LPSS_UART1_CTS_N", "n/a", "n/a", "n/a", "n/a", - "*GPIO_46", "LPSS_UART2_RXD", "n/a", "n/a", "n/a", "n/a", - "*GPIO_47", "LPSS_UART2_TXD", "n/a", "n/a", "n/a", "n/a", - "*GPIO_48", "LPSS_UART2_RTS_N", "n/a", "n/a", "n/a", "n/a", - "*GPIO_49", "LPSS_UART2_CTS_N", "n/a", "n/a", "n/a", "n/a", - "*GPIO_62", "GP_CAMERASB0", "n/a", "n/a", "n/a", "n/a", - "*GPIO_63", "GP_CAMERASB1", "n/a", "n/a", "n/a", "n/a", - "*GPIO_64", "GP_CAMERASB2", "n/a", "n/a", "n/a", "n/a", - "*GPIO_65", "GP_CAMERASB3", "n/a", "n/a", "n/a", "n/a", - "*GPIO_66", "GP_CAMERASB4", "n/a", "n/a", "n/a", "n/a", - "*GPIO_67", "GP_CAMERASB5", "n/a", "n/a", "n/a", "n/a", - "*GPIO_68", "GP_CAMERASB6", "n/a", "n/a", "n/a", "n/a", - "*GPIO_69", "GP_CAMERASB7", "n/a", "n/a", "n/a", "n/a", - "*GPIO_70", "GP_CAMERASB8", "n/a", "n/a", "n/a", "n/a", - "*GPIO_71", "GP_CAMERASB9", "n/a", "n/a", "n/a", "n/a", - "*GPIO_72", "GP_CAMERASB10","n/a", "n/a", "n/a", "n/a", - "*GPIO_73", "GP_CAMERASB11","n/a", "n/a", "n/a", "n/a", - "TCK", "*JTAG_TCK", "n/a", "n/a", "n/a", "n/a", - "TRST_B", "*JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", - "TMS", "*JTAG_TMS", "n/a", "n/a", "n/a", "n/a", - "TDI", "*JTAG_TDI", "n/a", "n/a", "n/a", "n/a", - "CX_PMODE", "*JTAG_PMODE", "n/a", "n/a", "n/a", "n/a", - "CX_PREQ_B", "*JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", - "JTAGX" , "*JTAGX", "n/a", "n/a", "n/a", "n/a", - "CX_PRDY_B", "*JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", - "TDO", "*JTAG_TDO", "n/a", "n/a", "n/a", "n/a", - "CNV_BRI_DT", "*GPIO_216", "n/a", "n/a", "n/a", "n/a", - "CNV_BRI_RSP", "*GPIO_217", "n/a", "n/a", "n/a", "n/a", - "CNV_RGI_DT", "*GPIO_218", "n/a", "n/a", "n/a", "n/a", - "CNV_RGI_RSP", "*n/a", "n/a", "n/a", "n/a", "n/a", - "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", - "SVID0_DATA", "*SVID0_DATA", "n/a", "n/a", "n/a", "n/a", - "SVID0_CLK", "*SVID0_CLK", "n/a", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group apl_group_north = { - .display = "------- GPIO Group North -------", - .pad_count = ARRAY_SIZE(apl_group_north_names) / 6, - .func_count = 6, - .pad_names = apl_group_north_names, -}; - -static const struct gpio_group *const apl_community_north_groups[] = { - &apl_group_north, -}; - -static const struct gpio_community apl_community_north = { - .name = "----- GPIO Community North -----", - .pcr_port_id = 0xc5, - .group_count = ARRAY_SIZE(apl_community_north_groups), - .groups = apl_community_north_groups, -}; - -static const char *const apl_group_northwest_names[] = { - "GPIO_187", "*DDI0_DDC_SDA", "n/a", "n/a", - "GPIO_188", "*DDI0_DDC_SCL", "n/a", "n/a", - "GPIO_189", "*DDI1_DDC_SDA", "n/a", "n/a", - "GPIO_190", "*DDI1_DDC_SCL", "n/a", "n/a", - "GPIO_191", "*MIPI_I2C_SDA", "n/a", "n/a", - "GPIO_192", "*MIPI_I2C_SCL", "n/a", "n/a", - "GPIO_193", "*PNL0_VDDEN", "n/a", "n/a", - "GPIO_194", "*PNL0_BKLTEN", "n/a", "n/a", - "GPIO_195", "*PNL0_BKLTCTL", "n/a", "n/a", - "GPIO_196", "*PNL1_VDDEN", "n/a", "n/a", - "GPIO_197", "*PNL1_BKLTEN", "n/a", "n/a", - "GPIO_198", "*PNL1_BKLTCTL", "n/a", "n/a", - "GPIO_199", "*GPIO_199", "DDI1_HPD", "n/a", - "GPIO_200", "*GPIO_200", "DDI0_HPD", "n/a", - "GPIO_201", "*MDSI_A_TE", "n/a", "n/a", - "GPIO_202", "*MDSI_C_TE", "n/a", "n/a", - "GPIO_203", "*USB_OC0_N", "n/a", "n/a", - "GPIO_204", "*USB_OC1_N", "n/a", "n/a", - "PMC_SPI_FS0", "*PMC_SPI_FS0", "n/a", "n/a", - "PMC_SPI_FS1", "*PMC_SPI_FS1", "DDI2_HPD", "n/a", - "PMC_SPI_FS2", "*PMC_SPI_FS2", "FST_SPI_CS2_N","n/a", - "PMC_SPI_RXD", "*PMC_SPI_RXD", "n/a", "n/a", - "PMC_SPI_TXD", "*PMC_SPI_TXD", "n/a", "n/a", - "PMC_SPI_CLK", "*PMC_SPI_CLK", "n/a", "n/a", - "PMIC_PWRGOOD", "*n/a", "n/a", "n/a", - "PMIC_RESET_B", "*GPIO_223", "n/a", "n/a", - "GPIO_213", "*GPIO_213", "n/a", "n/a", - "GPIO_214", "*GPIO_214", "n/a", "n/a", - "GPIO_215", "*GPIO_215", "n/a", "n/a", - "PMIC_THERMTRIP_B", "*THERMTRIP_N", "n/a", "n/a", - "PMIC_STDBY", "*GPIO_224", "n/a", "n/a", - "PROCHOT_B", "*PROCHOT_N", "n/a", "n/a", - "PMIC_I2C_SCL", "*PMIC_I2C_SCL", "n/a", "n/a", - "PMIC_I2C_SDA", "*PMIC_I2C_SDA", "n/a", "n/a", - "*GPIO_74", "AVS_I2S1_MCLK" , "n/a", "n/a", - "*GPIO_75", "AVS_I2S1_BCLK", "n/a", "n/a", - "*GPIO_76", "AVS_I2S1_WS_SYNC", "n/a", "n/a", - "*GPIO_77", "AVS_I2S1_SDI", "n/a", "n/a", - "*GPIO_78", "AVS_I2S1_SDO", "n/a", "n/a", - "*GPIO_79", "AVS_DMIC_CLK_A1", "AVS_I2S4_BCLK","n/a", - "*GPIO_80", "AVS_DMIC_CLK_B1", "AVS_I2S4_WS_SYNC","n/a", - "*GPIO_81", "AVS_DMIC_DATA_1", "AVS_I2C4_SDI", "n/a", - "*GPIO_82", "AVS_DMIC_CLK_AB2", "AVS_I2S4_SDO", "n/a", - "*GPIO_83", "AVS_DMIC_DATA_2", "n/a", "n/a", - "*GPIO_84", "AVS_I2S2_MCLK", "AVS_HDA_RST_N","n/a", - "*GPIO_85", "AVS_I2S2_BCLK", "n/a", "n/a", - "*GPIO_86", "AVS_I2S2_WS_SYNC", "n/a", "n/a", - "*GPIO_87", "AVS_I2S2_SDI", "n/a", "n/a", - "*GPIO_88", "AVS_I2S2_SDO", "n/a", "n/a", - "*GPIO_89", "AVS_I2S3_BCLK", "n/a", "n/a", - "*GPIO_90", "AVS_I2S3_WS_SYNC", "n/a", "n/a", - "*GPIO_91", "AVS_I2S3_SDI", "n/a", "n/a", - "*GPIO_92", "AVS_I2S3_SDO", "n/a", "n/a", - "GPIO_97", "*FST_SPI_CS0_N", "n/a", "n/a", - "GPIO_98", "*FST_SPI_CS1_N", "n/a", "n/a", - "GPIO_99", "*FST_SPI_MOSI_IO0", "n/a", "n/a", - "GPIO_100", "*FST_SPI_MISO_IO1", "n/a", "n/a", - "GPIO_101", "*FST_SPI_IO2", "n/a", "n/a", - "GPIO_102", "*FST_SPI_IO3", "n/a", "n/a", - "GPIO_103", "*FST_SPI_CLK", "n/a", "n/a", - "FST_SPI_CLK_FB", "*n/a", "n/a", "n/a", - "*GPIO_104", "SIO_SPI_0_CLK", "n/a", "n/a", - "*GPIO_105", "SIO_SPI_0_FS0", "n/a", "n/a", - "*GPIO_106", "SIO_SPI_0_FS1", "n/a", "FST_SPI_CS2_N", - "*GPIO_109", "SIO_SPI_0_RXD", "n/a", "n/a", - "*GPIO_110", "SIO_SPI_0_TXD", "n/a", "n/a", - "*GPIO_111", "SIO_SPI_1_CLK", "n/a", "n/a", - "*GPIO_112", "SIO_SPI_1_FS0", "n/a", "n/a", - "*GPIO_113", "SIO_SPI_1_FS1", "n/a", "n/a", - "*GPIO_116", "SIO_SPI_1_RXD", "n/a", "n/a", - "*GPIO_117", "SIO_SPI_1_TXD", "n/a", "n/a", - "*GPIO_118", "SIO_SPI_2_CLK", "n/a", "n/a", - "*GPIO_119", "SIO_SPI_2_FS0", "n/a", "n/a", - "*GPIO_120", "SIO_SPI_2_FS1", "n/a", "n/a", - "*GPIO_121", "SIO_SPI_2_FS2", "n/a", "n/a", - "*GPIO_122", "SIO_SPI_2_RXD", "n/a", "n/a", - "*GPIO_123", "SIO_SPI_2_TXD", "n/a", "n/a", -}; - -static const struct gpio_group apl_group_northwest = { - .display = "----- GPIO Group NorthWest -----", - .pad_count = ARRAY_SIZE(apl_group_northwest_names) / 4, - .func_count = 4, - .pad_names = apl_group_northwest_names, -}; - -static const struct gpio_group *const apl_community_northwest_groups[] = { - &apl_group_northwest, -}; - -static const struct gpio_community apl_community_northwest = { - .name = "--- GPIO Community NorthWest ---", - .pcr_port_id = 0xc4, - .group_count = ARRAY_SIZE(apl_community_northwest_groups), - .groups = apl_community_northwest_groups, -}; - - -static const char *const apl_group_west_names[] = { - "*GPIO_124", "LPSS_I2C0_SDA", "n/a", "n/a", - "*GPIO_125", "LPSS_I2C0_SCL", "n/a", "n/a", - "*GPIO_126", "LPSS_I2C1_SDA", "n/a", "n/a", - "*GPIO_127", "LPSS_I2C1_SCL", "n/a", "n/a", - "*GPIO_128", "LPSS_I2C2_SDA", "n/a", "n/a", - "*GPIO_129", "LPSS_I2C2_SCL", "n/a", "n/a", - "*GPIO_130", "LPSS_I2C3_SDA", "n/a", "n/a", - "*GPIO_131", "LPSS_I2C3_SCL", "n/a", "n/a", - "*GPIO_132", "LPSS_I2C4_SDA", "n/a", "n/a", - "*GPIO_133", "LPSS_I2C4_SCL", "n/a", "n/a", - "*GPIO_134", "LPSS_I2C5_SDA","ISH_I2C0_SDA", "n/a", - "*GPIO_135", "LPSS_I2C5_SCL","ISH_I2C0_SCL", "n/a", - "*GPIO_136", "LPSS_I2C6_SDA","ISH_I2C1_SDA", "n/a", - "*GPIO_137", "LPSS_I2C6_SCL","ISH_I2C1_SCL", "n/a", - "*GPIO_138", "LPSS_I2C7_SDA","ISH_I2C2_SDA", "n/a", - "*GPIO_139", "LPSS_I2C7_SCL","ISH_I2C2_SCL", "n/a", - "*GPIO_146", "ISH_GPIO_0", "AVS_I2S6_BCLK", "AVS_HDA_BCLK", - "*GPIO_147", "ISH_GPIO_1", "AVS_I2S6_WS_SYNC", "AVS_HDA_WS_SYNC", - "*GPIO_148", "ISH_GPIO_2", "AVS_I2S6_SDI", "AVS_HDA_SDI", - "*GPIO_149", "ISH_GPIO_3", "AVS_I2S6_SDO", "AVS_HDA_SDO", - "*GPIO_150", "ISH_GPIO_4", "AVS_I2S5_BCLK", "LPSS_UART2_RXD", - "*GPIO_151", "ISH_GPIO_5", "AVS_I2S5_WS_SYNC", "LPSS_UART2_TXD", - "*GPIO_152", "ISH_GPIO_6", "AVS_I2S5_SDI", "LPSS_UART2_RTS_B", - "*GPIO_153", "ISH_GPIO_7", "AVS_I2S5_SDO", "LPSS_UART2_CTS_B", - "*GPIO_154", "ISH_GPIO_8", "n/a", "n/a", - "*GPIO_155", "ISH_GPIO_9", "SPKR", "n/a", - "GPIO_209", "*PCIE_CLKREQ0_N", "MODEM_CLKREQ", "n/a", - "GPIO_210", "*PCIE_CLKREQ1_N", "n/a", "n/a", - "GPIO_211", "*PCIE_CLKREQ2_N", "n/a", "n/a", - "GPIO_212", "*PCIE_CLKREQ3_N", "n/a", "n/a", - "OSC_CLK_OUT_0","*OSC_CLK_OUT_0", "n/a", "n/a", - "OSC_CLK_OUT_1","*OSC_CLK_OUT_1", "n/a", "n/a", - "OSC_CLK_OUT_2","*OSC_CLK_OUT_2", "n/a", "n/a", - "OSC_CLK_OUT_3","*OSC_CLK_OUT_3", "n/a", "n/a", - "OSC_CLK_OUT_4","*OSC_CLK_OUT_4", "n/a", "n/a", - "*PMU_AC_PRESENT","PMU_AC_PRESENT", "n/a", "n/a", - "PMU_BATLOW_B", "*PMU_BATLOW_N", "n/a", "n/a", - "PMU_PLTRST_B", "*PMU_PLTRST_N", "n/a", "n/a", - "PMU_PWRBTN_B", "*PMU_PWRBTN_N", "n/a", "n/a", - "PMU_RESETBUTTON_B", "*PMU_RSTBTN_N", "n/a", "n/a", - "PMU_SLP_S0_B", "*PMU_SLP_S0_N", "n/a", "n/a", - "PMU_SLP_S3_B", "*PMU_SLP_S3_N", "n/a", "n/a", - "PMU_SLP_S4_B", "*PMU_SLP_S4_N", "n/a", "n/a", - "PMU_SUSCLK", "*PMU_SUSCLK", "n/a", "n/a", - "*PMU_WAKE_B", "PMU_WAKE_B/EMMC_PWR_EN_N","n/a", "n/a", - "SUS_STAT_B", "*SUS_STAT_B", "n/a", "n/a", - "SUSPWRDNACK", "*SUSPWRDNACK", "n/a", "n/a", -}; - -static const struct gpio_group apl_group_west = { - .display = "-------- GPIO Group West -------", - .pad_count = ARRAY_SIZE(apl_group_west_names) / 4, - .func_count = 4, - .pad_names = apl_group_west_names, -}; - -static const struct gpio_group *const apl_community_west_groups[] = { - &apl_group_west, -}; - -static const struct gpio_community apl_community_west = { - .name = "------ GPIO Community West -----", - .pcr_port_id = 0xc7, - .group_count = ARRAY_SIZE(apl_community_west_groups), - .groups = apl_community_west_groups, -}; - -static const char *const apl_group_southwest_names[] = { - "*GPIO_205", "PCIE_WAKE0_N", "n/a", - "*GPIO_206", "PCIE_WAKE1_N", "n/a", - "*GPIO_207", "PCIE_WAKE2_N", "n/a", - "*GPIO_208", "PCIE_WAKE3_N", "n/a", - "GPIO_156", "*EMMC_CLK", "n/a", - "GPIO_157", "*EMMC_D0", "n/a", - "GPIO_158", "*EMMC_D1", "n/a", - "GPIO_159", "*EMMC_D2", "n/a", - "GPIO_160", "*EMMC_D3", "n/a", - "GPIO_161", "*EMMC_D4", "n/a", - "GPIO_162", "*EMMC_D5", "n/a", - "GPIO_163", "*EMMC_D6", "n/a", - "GPIO_164", "*EMMC_D7", "n/a", - "GPIO_165", "*EMMC_CMD", "n/a", - "*GPIO_166", "GPIO_166", "n/a", - "*GPIO_167", "GPIO_167", "n/a", - "*GPIO_168", "GPIO_168", "n/a", - "*GPIO_169", "GPIO_169", "n/a", - "*GPIO_170", "GPIO_170", "n/a", - "*GPIO_171", "GPIO_171", "n/a", - "*GPIO_172", "SDCARD_CLK", "n/a", - "*GPIO_179", "n/a", "n/a", - "*GPIO_173", "SDCARD_D0", "n/a", - "*GPIO_174", "SDCARD_D1", "n/a", - "*GPIO_175", "SDCARD_D2", "n/a", - "*GPIO_176", "SDCARD_D3", "n/a", - "*GPIO_177", "SDCARD_CD_B", "n/a", - "*GPIO_178", "SDCARD_CMD", "n/a", - "*GPIO_186", "SDCARD_LVL_WP", "n/a", - "GPIO_182", "*EMMC_RCLK", "n/a", - "GPIO_183", "GPIO_183", "n/a", - "*SMB_ALERTB", "SMB_ALERT_N", "n/a", - "*SMB_CLK", "SMB_CLK", "LPSS_I2C7_SCL", - "*SMB_DATA", "SMB_DATA", "LPSS_I2C7_SDA", - "*LPC_ILB_SERIRQ", "LPC_ILB_SERIRQ", "n/a", - "*LPC_CLKOUT0", "LPC_CLKOUT0", "n/a", - "*LPC_CLKOUT1", "LPC_CLKOUT1", "n/a", - "*LPC_AD0", "LPC_AD0", "n/a", - "*LPC_AD1", "LPC_AD1", "n/a", - "*LPC_AD2", "LPC_AD2", "n/a", - "*LPC_AD3", "LPC_AD3", "n/a", - "*LPC_CLKRUNB", "LPC_CLKRUNB", "n/a", - "*LPC_FRAMEB", "LPC_FRAMEB", "n/a", -}; - -static const struct gpio_group apl_group_southwest = { - .display = "----- GPIO Group SouthWest -----", - .pad_count = ARRAY_SIZE(apl_group_southwest_names) / 3, - .func_count = 3, - .pad_names = apl_group_southwest_names, -}; - -static const struct gpio_group *const apl_community_southwest_groups[] = { - &apl_group_southwest, -}; - -static const struct gpio_community apl_community_southwest = { - .name = "--- GPIO Community SouthWest ---", - .pcr_port_id = 0xc0, - .group_count = ARRAY_SIZE(apl_community_southwest_groups), - .groups = apl_community_southwest_groups, -}; - -static const struct gpio_community *const apl_communities[] = { - &apl_community_north, &apl_community_northwest, - &apl_community_west, &apl_community_southwest, -}; - static const char *const sunrise_group_a_names[] = { "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", "GPP_A1", "LAD0", "n/a", "ESPI_IO0", diff --git a/util/inteltool/gpio_names/apollolake.h b/util/inteltool/gpio_names/apollolake.h new file mode 100644 index 0000000000..ec4a934f6a --- /dev/null +++ b/util/inteltool/gpio_names/apollolake.h @@ -0,0 +1,345 @@ +#ifndef GPIO_NAMES_APOLLOLAKE_H +#define GPIO_NAMES_APOLLOLAKE_H + +#include "gpio_groups.h" + +/* + * Names prefixed with an *asterisk are the default. + * (if it's the first column, GPIO is the default, no matter the name) + */ + +static const char *const apl_group_north_names[] = { + "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_2", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_3", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_4", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_5", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_6", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_7", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_8", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_9", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_10", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_11", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_12", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_13", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_14", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_15", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_16", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_17", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_18", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_19", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_20", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_21", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_22", "n/a", "n/a", "n/a", "n/a", "SATA_GP0", + "*GPIO_23", "n/a", "n/a", "n/a", "n/a", "SATA_GP1", + "*GPIO_24", "n/a", "n/a", "n/a", "n/a", "SATA_DEVSLP0", + "*GPIO_25", "n/a", "n/a", "n/a", "n/a", "SATA_DEVSLP1", + "*GPIO_26", "n/a", "n/a", "n/a", "n/a", "SATA_LEDN", + "*GPIO_27", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_28", "n/a", "ISH_GPIO_10", "n/a", "n/a", "n/a", + "*GPIO_29", "n/a", "ISH_GPIO_11", "n/a", "n/a", "n/a", + "*GPIO_30", "ISH_GPIO_12", "n/a", "n/a", "n/a", "n/a", + "*GPIO_31", "ISH_GPIO_13", "n/a", "n/a", "n/a", "SUSCLK1", + "*GPIO_32", "ISH_GPIO_14", "n/a", "n/a", "n/a", "SUSCLK2", + "*GPIO_33", "ISH_GPIO_15", "n/a", "n/a", "n/a", "SUSCLK3", + "*GPIO_34", "PWM0", "n/a", "n/a", "n/a", "n/a", + "*GPIO_35", "PWM1", "n/a", "n/a", "n/a", "n/a", + "*GPIO_36", "PWM2", "n/a", "n/a", "n/a", "n/a", + "*GPIO_37", "PWM3", "n/a", "n/a", "n/a", "n/a", + "*GPIO_38", "LPSS_UART0_RXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_39", "LPSS_UART0_TXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_40", "LPSS_UART0_RTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_41", "LPSS_UART0_CTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_42", "LPSS_UART1_RXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_43", "LPSS_UART1_TXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_44", "LPSS_UART1_RTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_45", "LPSS_UART1_CTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_46", "LPSS_UART2_RXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_47", "LPSS_UART2_TXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_48", "LPSS_UART2_RTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_49", "LPSS_UART2_CTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_62", "GP_CAMERASB0", "n/a", "n/a", "n/a", "n/a", + "*GPIO_63", "GP_CAMERASB1", "n/a", "n/a", "n/a", "n/a", + "*GPIO_64", "GP_CAMERASB2", "n/a", "n/a", "n/a", "n/a", + "*GPIO_65", "GP_CAMERASB3", "n/a", "n/a", "n/a", "n/a", + "*GPIO_66", "GP_CAMERASB4", "n/a", "n/a", "n/a", "n/a", + "*GPIO_67", "GP_CAMERASB5", "n/a", "n/a", "n/a", "n/a", + "*GPIO_68", "GP_CAMERASB6", "n/a", "n/a", "n/a", "n/a", + "*GPIO_69", "GP_CAMERASB7", "n/a", "n/a", "n/a", "n/a", + "*GPIO_70", "GP_CAMERASB8", "n/a", "n/a", "n/a", "n/a", + "*GPIO_71", "GP_CAMERASB9", "n/a", "n/a", "n/a", "n/a", + "*GPIO_72", "GP_CAMERASB10","n/a", "n/a", "n/a", "n/a", + "*GPIO_73", "GP_CAMERASB11","n/a", "n/a", "n/a", "n/a", + "TCK", "*JTAG_TCK", "n/a", "n/a", "n/a", "n/a", + "TRST_B", "*JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", + "TMS", "*JTAG_TMS", "n/a", "n/a", "n/a", "n/a", + "TDI", "*JTAG_TDI", "n/a", "n/a", "n/a", "n/a", + "CX_PMODE", "*JTAG_PMODE", "n/a", "n/a", "n/a", "n/a", + "CX_PREQ_B", "*JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", + "JTAGX" , "*JTAGX", "n/a", "n/a", "n/a", "n/a", + "CX_PRDY_B", "*JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", + "TDO", "*JTAG_TDO", "n/a", "n/a", "n/a", "n/a", + "CNV_BRI_DT", "*GPIO_216", "n/a", "n/a", "n/a", "n/a", + "CNV_BRI_RSP", "*GPIO_217", "n/a", "n/a", "n/a", "n/a", + "CNV_RGI_DT", "*GPIO_218", "n/a", "n/a", "n/a", "n/a", + "CNV_RGI_RSP", "*n/a", "n/a", "n/a", "n/a", "n/a", + "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", + "SVID0_DATA", "*SVID0_DATA", "n/a", "n/a", "n/a", "n/a", + "SVID0_CLK", "*SVID0_CLK", "n/a", "n/a", "n/a", "n/a", +}; + +static const char *const apl_group_northwest_names[] = { + "GPIO_187", "*DDI0_DDC_SDA", "n/a", "n/a", + "GPIO_188", "*DDI0_DDC_SCL", "n/a", "n/a", + "GPIO_189", "*DDI1_DDC_SDA", "n/a", "n/a", + "GPIO_190", "*DDI1_DDC_SCL", "n/a", "n/a", + "GPIO_191", "*MIPI_I2C_SDA", "n/a", "n/a", + "GPIO_192", "*MIPI_I2C_SCL", "n/a", "n/a", + "GPIO_193", "*PNL0_VDDEN", "n/a", "n/a", + "GPIO_194", "*PNL0_BKLTEN", "n/a", "n/a", + "GPIO_195", "*PNL0_BKLTCTL", "n/a", "n/a", + "GPIO_196", "*PNL1_VDDEN", "n/a", "n/a", + "GPIO_197", "*PNL1_BKLTEN", "n/a", "n/a", + "GPIO_198", "*PNL1_BKLTCTL", "n/a", "n/a", + "GPIO_199", "*GPIO_199", "DDI1_HPD", "n/a", + "GPIO_200", "*GPIO_200", "DDI0_HPD", "n/a", + "GPIO_201", "*MDSI_A_TE", "n/a", "n/a", + "GPIO_202", "*MDSI_C_TE", "n/a", "n/a", + "GPIO_203", "*USB_OC0_N", "n/a", "n/a", + "GPIO_204", "*USB_OC1_N", "n/a", "n/a", + "PMC_SPI_FS0", "*PMC_SPI_FS0", "n/a", "n/a", + "PMC_SPI_FS1", "*PMC_SPI_FS1", "DDI2_HPD", "n/a", + "PMC_SPI_FS2", "*PMC_SPI_FS2", "FST_SPI_CS2_N","n/a", + "PMC_SPI_RXD", "*PMC_SPI_RXD", "n/a", "n/a", + "PMC_SPI_TXD", "*PMC_SPI_TXD", "n/a", "n/a", + "PMC_SPI_CLK", "*PMC_SPI_CLK", "n/a", "n/a", + "PMIC_PWRGOOD", "*n/a", "n/a", "n/a", + "PMIC_RESET_B", "*GPIO_223", "n/a", "n/a", + "GPIO_213", "*GPIO_213", "n/a", "n/a", + "GPIO_214", "*GPIO_214", "n/a", "n/a", + "GPIO_215", "*GPIO_215", "n/a", "n/a", + "PMIC_THERMTRIP_B", "*THERMTRIP_N", "n/a", "n/a", + "PMIC_STDBY", "*GPIO_224", "n/a", "n/a", + "PROCHOT_B", "*PROCHOT_N", "n/a", "n/a", + "PMIC_I2C_SCL", "*PMIC_I2C_SCL", "n/a", "n/a", + "PMIC_I2C_SDA", "*PMIC_I2C_SDA", "n/a", "n/a", + "*GPIO_74", "AVS_I2S1_MCLK" , "n/a", "n/a", + "*GPIO_75", "AVS_I2S1_BCLK", "n/a", "n/a", + "*GPIO_76", "AVS_I2S1_WS_SYNC", "n/a", "n/a", + "*GPIO_77", "AVS_I2S1_SDI", "n/a", "n/a", + "*GPIO_78", "AVS_I2S1_SDO", "n/a", "n/a", + "*GPIO_79", "AVS_DMIC_CLK_A1", "AVS_I2S4_BCLK","n/a", + "*GPIO_80", "AVS_DMIC_CLK_B1", "AVS_I2S4_WS_SYNC","n/a", + "*GPIO_81", "AVS_DMIC_DATA_1", "AVS_I2C4_SDI", "n/a", + "*GPIO_82", "AVS_DMIC_CLK_AB2", "AVS_I2S4_SDO", "n/a", + "*GPIO_83", "AVS_DMIC_DATA_2", "n/a", "n/a", + "*GPIO_84", "AVS_I2S2_MCLK", "AVS_HDA_RST_N","n/a", + "*GPIO_85", "AVS_I2S2_BCLK", "n/a", "n/a", + "*GPIO_86", "AVS_I2S2_WS_SYNC", "n/a", "n/a", + "*GPIO_87", "AVS_I2S2_SDI", "n/a", "n/a", + "*GPIO_88", "AVS_I2S2_SDO", "n/a", "n/a", + "*GPIO_89", "AVS_I2S3_BCLK", "n/a", "n/a", + "*GPIO_90", "AVS_I2S3_WS_SYNC", "n/a", "n/a", + "*GPIO_91", "AVS_I2S3_SDI", "n/a", "n/a", + "*GPIO_92", "AVS_I2S3_SDO", "n/a", "n/a", + "GPIO_97", "*FST_SPI_CS0_N", "n/a", "n/a", + "GPIO_98", "*FST_SPI_CS1_N", "n/a", "n/a", + "GPIO_99", "*FST_SPI_MOSI_IO0", "n/a", "n/a", + "GPIO_100", "*FST_SPI_MISO_IO1", "n/a", "n/a", + "GPIO_101", "*FST_SPI_IO2", "n/a", "n/a", + "GPIO_102", "*FST_SPI_IO3", "n/a", "n/a", + "GPIO_103", "*FST_SPI_CLK", "n/a", "n/a", + "FST_SPI_CLK_FB", "*n/a", "n/a", "n/a", + "*GPIO_104", "SIO_SPI_0_CLK", "n/a", "n/a", + "*GPIO_105", "SIO_SPI_0_FS0", "n/a", "n/a", + "*GPIO_106", "SIO_SPI_0_FS1", "n/a", "FST_SPI_CS2_N", + "*GPIO_109", "SIO_SPI_0_RXD", "n/a", "n/a", + "*GPIO_110", "SIO_SPI_0_TXD", "n/a", "n/a", + "*GPIO_111", "SIO_SPI_1_CLK", "n/a", "n/a", + "*GPIO_112", "SIO_SPI_1_FS0", "n/a", "n/a", + "*GPIO_113", "SIO_SPI_1_FS1", "n/a", "n/a", + "*GPIO_116", "SIO_SPI_1_RXD", "n/a", "n/a", + "*GPIO_117", "SIO_SPI_1_TXD", "n/a", "n/a", + "*GPIO_118", "SIO_SPI_2_CLK", "n/a", "n/a", + "*GPIO_119", "SIO_SPI_2_FS0", "n/a", "n/a", + "*GPIO_120", "SIO_SPI_2_FS1", "n/a", "n/a", + "*GPIO_121", "SIO_SPI_2_FS2", "n/a", "n/a", + "*GPIO_122", "SIO_SPI_2_RXD", "n/a", "n/a", + "*GPIO_123", "SIO_SPI_2_TXD", "n/a", "n/a", +}; + +static const char *const apl_group_west_names[] = { + "*GPIO_124", "LPSS_I2C0_SDA", "n/a", "n/a", + "*GPIO_125", "LPSS_I2C0_SCL", "n/a", "n/a", + "*GPIO_126", "LPSS_I2C1_SDA", "n/a", "n/a", + "*GPIO_127", "LPSS_I2C1_SCL", "n/a", "n/a", + "*GPIO_128", "LPSS_I2C2_SDA", "n/a", "n/a", + "*GPIO_129", "LPSS_I2C2_SCL", "n/a", "n/a", + "*GPIO_130", "LPSS_I2C3_SDA", "n/a", "n/a", + "*GPIO_131", "LPSS_I2C3_SCL", "n/a", "n/a", + "*GPIO_132", "LPSS_I2C4_SDA", "n/a", "n/a", + "*GPIO_133", "LPSS_I2C4_SCL", "n/a", "n/a", + "*GPIO_134", "LPSS_I2C5_SDA","ISH_I2C0_SDA", "n/a", + "*GPIO_135", "LPSS_I2C5_SCL","ISH_I2C0_SCL", "n/a", + "*GPIO_136", "LPSS_I2C6_SDA","ISH_I2C1_SDA", "n/a", + "*GPIO_137", "LPSS_I2C6_SCL","ISH_I2C1_SCL", "n/a", + "*GPIO_138", "LPSS_I2C7_SDA","ISH_I2C2_SDA", "n/a", + "*GPIO_139", "LPSS_I2C7_SCL","ISH_I2C2_SCL", "n/a", + "*GPIO_146", "ISH_GPIO_0", "AVS_I2S6_BCLK", "AVS_HDA_BCLK", + "*GPIO_147", "ISH_GPIO_1", "AVS_I2S6_WS_SYNC", "AVS_HDA_WS_SYNC", + "*GPIO_148", "ISH_GPIO_2", "AVS_I2S6_SDI", "AVS_HDA_SDI", + "*GPIO_149", "ISH_GPIO_3", "AVS_I2S6_SDO", "AVS_HDA_SDO", + "*GPIO_150", "ISH_GPIO_4", "AVS_I2S5_BCLK", "LPSS_UART2_RXD", + "*GPIO_151", "ISH_GPIO_5", "AVS_I2S5_WS_SYNC", "LPSS_UART2_TXD", + "*GPIO_152", "ISH_GPIO_6", "AVS_I2S5_SDI", "LPSS_UART2_RTS_B", + "*GPIO_153", "ISH_GPIO_7", "AVS_I2S5_SDO", "LPSS_UART2_CTS_B", + "*GPIO_154", "ISH_GPIO_8", "n/a", "n/a", + "*GPIO_155", "ISH_GPIO_9", "SPKR", "n/a", + "GPIO_209", "*PCIE_CLKREQ0_N", "MODEM_CLKREQ", "n/a", + "GPIO_210", "*PCIE_CLKREQ1_N", "n/a", "n/a", + "GPIO_211", "*PCIE_CLKREQ2_N", "n/a", "n/a", + "GPIO_212", "*PCIE_CLKREQ3_N", "n/a", "n/a", + "OSC_CLK_OUT_0","*OSC_CLK_OUT_0", "n/a", "n/a", + "OSC_CLK_OUT_1","*OSC_CLK_OUT_1", "n/a", "n/a", + "OSC_CLK_OUT_2","*OSC_CLK_OUT_2", "n/a", "n/a", + "OSC_CLK_OUT_3","*OSC_CLK_OUT_3", "n/a", "n/a", + "OSC_CLK_OUT_4","*OSC_CLK_OUT_4", "n/a", "n/a", + "*PMU_AC_PRESENT","PMU_AC_PRESENT", "n/a", "n/a", + "PMU_BATLOW_B", "*PMU_BATLOW_N", "n/a", "n/a", + "PMU_PLTRST_B", "*PMU_PLTRST_N", "n/a", "n/a", + "PMU_PWRBTN_B", "*PMU_PWRBTN_N", "n/a", "n/a", + "PMU_RESETBUTTON_B", "*PMU_RSTBTN_N", "n/a", "n/a", + "PMU_SLP_S0_B", "*PMU_SLP_S0_N", "n/a", "n/a", + "PMU_SLP_S3_B", "*PMU_SLP_S3_N", "n/a", "n/a", + "PMU_SLP_S4_B", "*PMU_SLP_S4_N", "n/a", "n/a", + "PMU_SUSCLK", "*PMU_SUSCLK", "n/a", "n/a", + "*PMU_WAKE_B", "PMU_WAKE_B/EMMC_PWR_EN_N","n/a", "n/a", + "SUS_STAT_B", "*SUS_STAT_B", "n/a", "n/a", + "SUSPWRDNACK", "*SUSPWRDNACK", "n/a", "n/a", +}; + +static const char *const apl_group_southwest_names[] = { + "*GPIO_205", "PCIE_WAKE0_N", "n/a", + "*GPIO_206", "PCIE_WAKE1_N", "n/a", + "*GPIO_207", "PCIE_WAKE2_N", "n/a", + "*GPIO_208", "PCIE_WAKE3_N", "n/a", + "GPIO_156", "*EMMC_CLK", "n/a", + "GPIO_157", "*EMMC_D0", "n/a", + "GPIO_158", "*EMMC_D1", "n/a", + "GPIO_159", "*EMMC_D2", "n/a", + "GPIO_160", "*EMMC_D3", "n/a", + "GPIO_161", "*EMMC_D4", "n/a", + "GPIO_162", "*EMMC_D5", "n/a", + "GPIO_163", "*EMMC_D6", "n/a", + "GPIO_164", "*EMMC_D7", "n/a", + "GPIO_165", "*EMMC_CMD", "n/a", + "*GPIO_166", "GPIO_166", "n/a", + "*GPIO_167", "GPIO_167", "n/a", + "*GPIO_168", "GPIO_168", "n/a", + "*GPIO_169", "GPIO_169", "n/a", + "*GPIO_170", "GPIO_170", "n/a", + "*GPIO_171", "GPIO_171", "n/a", + "*GPIO_172", "SDCARD_CLK", "n/a", + "*GPIO_179", "n/a", "n/a", + "*GPIO_173", "SDCARD_D0", "n/a", + "*GPIO_174", "SDCARD_D1", "n/a", + "*GPIO_175", "SDCARD_D2", "n/a", + "*GPIO_176", "SDCARD_D3", "n/a", + "*GPIO_177", "SDCARD_CD_B", "n/a", + "*GPIO_178", "SDCARD_CMD", "n/a", + "*GPIO_186", "SDCARD_LVL_WP", "n/a", + "GPIO_182", "*EMMC_RCLK", "n/a", + "GPIO_183", "GPIO_183", "n/a", + "*SMB_ALERTB", "SMB_ALERT_N", "n/a", + "*SMB_CLK", "SMB_CLK", "LPSS_I2C7_SCL", + "*SMB_DATA", "SMB_DATA", "LPSS_I2C7_SDA", + "*LPC_ILB_SERIRQ", "LPC_ILB_SERIRQ", "n/a", + "*LPC_CLKOUT0", "LPC_CLKOUT0", "n/a", + "*LPC_CLKOUT1", "LPC_CLKOUT1", "n/a", + "*LPC_AD0", "LPC_AD0", "n/a", + "*LPC_AD1", "LPC_AD1", "n/a", + "*LPC_AD2", "LPC_AD2", "n/a", + "*LPC_AD3", "LPC_AD3", "n/a", + "*LPC_CLKRUNB", "LPC_CLKRUNB", "n/a", + "*LPC_FRAMEB", "LPC_FRAMEB", "n/a", +}; + +static const struct gpio_group apl_group_north = { + .display = "------- GPIO Group North -------", + .pad_count = ARRAY_SIZE(apl_group_north_names) / 6, + .func_count = 6, + .pad_names = apl_group_north_names, +}; + +static const struct gpio_group *const apl_community_north_groups[] = { + &apl_group_north, +}; + +static const struct gpio_community apl_community_north = { + .name = "----- GPIO Community North -----", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(apl_community_north_groups), + .groups = apl_community_north_groups, +}; + +static const struct gpio_group apl_group_northwest = { + .display = "----- GPIO Group NorthWest -----", + .pad_count = ARRAY_SIZE(apl_group_northwest_names) / 4, + .func_count = 4, + .pad_names = apl_group_northwest_names, +}; + +static const struct gpio_group *const apl_community_northwest_groups[] = { + &apl_group_northwest, +}; + +static const struct gpio_community apl_community_northwest = { + .name = "--- GPIO Community NorthWest ---", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(apl_community_northwest_groups), + .groups = apl_community_northwest_groups, +}; + +static const struct gpio_group apl_group_west = { + .display = "-------- GPIO Group West -------", + .pad_count = ARRAY_SIZE(apl_group_west_names) / 4, + .func_count = 4, + .pad_names = apl_group_west_names, +}; + +static const struct gpio_group *const apl_community_west_groups[] = { + &apl_group_west, +}; + +static const struct gpio_community apl_community_west = { + .name = "------ GPIO Community West -----", + .pcr_port_id = 0xc7, + .group_count = ARRAY_SIZE(apl_community_west_groups), + .groups = apl_community_west_groups, +}; + +static const struct gpio_group apl_group_southwest = { + .display = "----- GPIO Group SouthWest -----", + .pad_count = ARRAY_SIZE(apl_group_southwest_names) / 3, + .func_count = 3, + .pad_names = apl_group_southwest_names, +}; + +static const struct gpio_group *const apl_community_southwest_groups[] = { + &apl_group_southwest, +}; + +static const struct gpio_community apl_community_southwest = { + .name = "--- GPIO Community SouthWest ---", + .pcr_port_id = 0xc0, + .group_count = ARRAY_SIZE(apl_community_southwest_groups), + .groups = apl_community_southwest_groups, +}; + +static const struct gpio_community *const apl_communities[] = { + &apl_community_north, &apl_community_northwest, + &apl_community_west, &apl_community_southwest, +}; + +#endif From e98af86a2effab94c3922d96d08005b7134b321d Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Wed, 29 Jan 2020 09:25:45 +0100 Subject: [PATCH 0467/1463] util/inteltool: Move Sunrise Point (LP) definitions into their own header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Sunrise Point and Sunrise Point LP definitions into its own header. Change-Id: I06efbee700f1525770365428fb85ef700ac53b80 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38628 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Tested-by: build bot (Jenkins) --- util/inteltool/gpio_groups.c | 581 +-------------------------- util/inteltool/gpio_names/sunrise.h | 586 ++++++++++++++++++++++++++++ 2 files changed, 587 insertions(+), 580 deletions(-) create mode 100644 util/inteltool/gpio_names/sunrise.h diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index c19f37406c..f2700a0e98 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -26,590 +26,11 @@ #include "gpio_names/apollolake.h" #include "gpio_names/cannonlake.h" #include "gpio_names/icelake.h" +#include "gpio_names/sunrise.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -static const char *const sunrise_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "ISH_GP7", "n/a", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_a_names, -}; - -static const char *const sunrise_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "n/a", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "n/a", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_a = { - .display = "------- GPIO group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_a_names, -}; - -static const char *const sunrise_group_b_names[] = { - "GPP_B0", "n/a", "n/a", "n/a", - "GPP_B1", "n/a", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "n/a", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPIO_CS#", "n/a", "n/a", - "GPP_B16", "GSPIO_CLK", "n/a", "n/a", - "GPP_B17", "GSPIO_MISO", "n/a", "n/a", - "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_b_names, -}; - -static const char *const sunrise_lp_group_b_names[] = { - "GPP_B0", "CORE_VID0", "n/a", "n/a", - "GPP_B1", "CORE_VID1", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPI0_CS#", "n/a", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_b_names, -}; - -static const struct gpio_group *const sunrise_community_ab_groups[] = { - &sunrise_group_a, &sunrise_group_b, -}; - -static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { - &sunrise_lp_group_a, &sunrise_lp_group_b, -}; - -static const struct gpio_community sunrise_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_community_ab_groups), - .groups = sunrise_community_ab_groups, -}; - -static const struct gpio_community sunrise_lp_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), - .groups = sunrise_lp_community_ab_groups, -}; - -static const char *const sunrise_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", "n/a", - "GPP_C1", "SMBDATA", "n/a", "n/a", - "GPP_C2", "SMBALERT#", "n/a", "n/a", - "GPP_C3", "SML0CLK", "n/a", "n/a", - "GPP_C4", "SML0DATA", "n/a", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", "n/a", - "GPP_C6", "SML1CLK", "n/a", "n/a", - "GPP_C7", "SML1DATA", "n/a", "n/a", - "GPP_C8", "UART0_RXD", "n/a", "n/a", - "GPP_C9", "UART0_TXD", "n/a", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", - "GPP_C16", "I2C0_SDA", "n/a", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", "n/a", - "GPP_C20", "UART2_RXD", "n/a", "n/a", - "GPP_C21", "UART2_TXD", "n/a", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_c_names, -}; - -static const char *const sunrise_group_d_names[] = { - "GPP_D0", "n/a", "n/a", "n/a", - "GPP_D1", "n/a", "n/a", "n/a", - "GPP_D2", "n/a", "n/a", "n/a", - "GPP_D3", "n/a", "n/a", "n/a", - "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", - "GPP_D5", "I2S_SFRM", "n/a", "n/a", - "GPP_D6", "I2S_TXD", "n/a", "n/a", - "GPP_D7", "I2S_RXD", "n/a", "n/a", - "GPP_D8", "I2S_SCLK", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", - "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "n/a", "n/a", "n/a", - "GPP_D22", "n/a", "n/a", "n/a", - "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", -}; - -static const struct gpio_group sunrise_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_d_names, -}; - -static const char *const sunrise_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "n/a", "n/a", - "GPP_D1", "SPI1_CLK", "n/a", "n/a", - "GPP_D2", "SPI1_MISO", "n/a", "n/a", - "GPP_D3", "SPI1_MOSI", "n/a", "n/a", - "GPP_D4", "FLASHTRIG", "n/a", "n/a", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", - "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_d_names, -}; - -static const char *const sunrise_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATA_LED#", "n/a", "n/a", - "GPP_E9", "USB_OC0#", "n/a", "n/a", - "GPP_E10", "USB_OC1#", "n/a", "n/a", - "GPP_E11", "USB_OC2#", "n/a", "n/a", - "GPP_E12", "USB_OC3#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_e_names, -}; - -static const char *const sunrise_lp_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATALED#", "n/a", "n/a", - "GPP_E9", "USB2_OC0#", "n/a", "n/a", - "GPP_E10", "USB2_OC1#", "n/a", "n/a", - "GPP_E11", "USB2_OC2#", "n/a", "n/a", - "GPP_E12", "USB2_OC3#", "n/a", "n/a", - "GPP_E13", "DDPB_HPD0", "n/a", "n/a", - "GPP_E14", "DDPC_HPD1", "n/a", "n/a", - "GPP_E15", "DDPD_HPD2", "n/a", "n/a", - "GPP_E16", "DDPE_HPD3", "n/a", "n/a", - "GPP_E17", "EDP_HPD", "n/a", "n/a", - "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_E22", "n/a", "n/a", "n/a", - "GPP_E23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_e_names, -}; - -static const char *const sunrise_group_f_names[] = { - "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", - "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", - "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", - "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", - "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", - "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", - "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", - "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", - "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", - "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", - "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", - "GPP_F11", "SATA_SLOAD", "n/a", "n/a", - "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", - "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", - "GPP_F14", "n/a", "n/a", "n/a", - "GPP_F15", "USB_OC4#", "n/a", "n/a", - "GPP_F16", "USB_OC5#", "n/a", "n/a", - "GPP_F17", "USB_OC6#", "n/a", "n/a", - "GPP_F18", "USB_OC7#", "n/a", "n/a", - "GPP_F19", "eDP_VDDEN", "n/a", "n/a", - "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", - "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", - "GPP_F22", "n/a", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_f_names, -}; - -static const char *const sunrise_lp_group_f_names[] = { - "GPP_F0", "I2S2_SCLK", "n/a", "n/a", - "GPP_F1", "I2S2_SFRM", "n/a", "n/a", - "GPP_F2", "I2S2_TXD", "n/a", "n/a", - "GPP_F3", "I2S2_RXD", "n/a", "n/a", - "GPP_F4", "I2C2_SDA", "n/a", "n/a", - "GPP_F5", "I2C2_SCL", "n/a", "n/a", - "GPP_F6", "I2C3_SDA", "n/a", "n/a", - "GPP_F7", "I2C3_SCL", "n/a", "n/a", - "GPP_F8", "I2C4_SDA", "n/a", "n/a", - "GPP_F9", "I2C4_SCL", "n/a", "n/a", - "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", - "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", - "GPP_F12", "EMMC_CMD", "n/a", "n/a", - "GPP_F13", "EMMC_DATA0", "n/a", "n/a", - "GPP_F14", "EMMC_DATA1", "n/a", "n/a", - "GPP_F15", "EMMC_DATA2", "n/a", "n/a", - "GPP_F16", "EMMC_DATA3", "n/a", "n/a", - "GPP_F17", "EMMC_DATA4", "n/a", "n/a", - "GPP_F18", "EMMC_DATA5", "n/a", "n/a", - "GPP_F19", "EMMC_DATA6", "n/a", "n/a", - "GPP_F20", "EMMC_DATA7", "n/a", "n/a", - "GPP_F21", "EMMC_RCLK", "n/a", "n/a", - "GPP_F22", "EMMC_CLK", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_f_names, -}; - -static const char *const sunrise_group_g_names[] = { - "GPP_G0", "FAN_TACH_0", "n/a", "n/a", - "GPP_G1", "FAN_TACH_1", "n/a", "n/a", - "GPP_G2", "FAN_TACH_2", "n/a", "n/a", - "GPP_G3", "FAN_TACH_3", "n/a", "n/a", - "GPP_G4", "FAN_TACH_4", "n/a", "n/a", - "GPP_G5", "FAN_TACH_5", "n/a", "n/a", - "GPP_G6", "FAN_TACH_6", "n/a", "n/a", - "GPP_G7", "FAN_TACH_7", "n/a", "n/a", - "GPP_G8", "FAN_PWM_0", "n/a", "n/a", - "GPP_G9", "FAN_PWM_1", "n/a", "n/a", - "GPP_G10", "FAN_PWM_2", "n/a", "n/a", - "GPP_G11", "FAN_PWM_3", "n/a", "n/a", - "GPP_G12", "GSXDOUT", "n/a", "n/a", - "GPP_G13", "GSXSLOAD", "n/a", "n/a", - "GPP_G14", "GSXDIN", "n/a", "n/a", - "GPP_G15", "GSXRESET#", "n/a", "n/a", - "GPP_G16", "GSXCLK", "n/a", "n/a", - "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", - "GPP_G18", "NMI#", "n/a", "n/a", - "GPP_G19", "SMI#", "n/a", "n/a", - "GPP_G20", "n/a", "n/a", "n/a", - "GPP_G21", "n/a", "n/a", "n/a", - "GPP_G22", "n/a", "n/a", "n/a", - "GPP_G23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_g_names, -}; - -static const char *const sunrise_lp_group_g_names[] = { - "GPP_G0", "SD_CMD", "n/a", "n/a", - "GPP_G1", "SD_DATA0", "n/a", "n/a", - "GPP_G2", "SD_DATA1", "n/a", "n/a", - "GPP_G3", "SD_DATA2", "n/a", "n/a", - "GPP_G4", "SD_DATA3", "n/a", "n/a", - "GPP_G5", "SD_CD#", "n/a", "n/a", - "GPP_G6", "SD_CLK", "n/a", "n/a", - "GPP_G7", "SD_WP", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_g_names, -}; - -static const char *const sunrise_group_h_names[] = { - "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", - "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", - "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", - "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", - "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", - "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", - "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", - "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", - "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", - "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", - "GPP_H10", "SML2CLK", "n/a", "n/a", - "GPP_H11", "SML2DATA", "n/a", "n/a", - "GPP_H12", "SML2ALERT#", "n/a", "n/a", - "GPP_H13", "SML3CLK", "n/a", "n/a", - "GPP_H14", "SML3DATA", "n/a", "n/a", - "GPP_H15", "SML3ALERT#", "n/a", "n/a", - "GPP_H16", "SML4CLK", "n/a", "n/a", - "GPP_H17", "SML4DATA", "n/a", "n/a", - "GPP_H18", "SML4ALERT#", "n/a", "n/a", - "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_H23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_h_names, -}; - -static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { - &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, - &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, -}; - -static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { - &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, -}; - -static const struct gpio_community sunrise_community_cdefgh = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), - .groups = sunrise_community_cdefgh_groups, -}; - -static const struct gpio_community sunrise_lp_community_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), - .groups = sunrise_lp_community_cde_groups, -}; - -static const char *const sunrise_group_gpd_names[] = { - "GPD0", "BATLOW#", "n/a", "n/a", - "GPD1", "ACPRESENT", "n/a", "n/a", - "GPD2", "LAN_WAKE#", "n/a", "n/a", - "GPD3", "PWRBTN#", "n/a", "n/a", - "GPD4", "SLP_S3#", "n/a", "n/a", - "GPD5", "SLP_S4#", "n/a", "n/a", - "GPD6", "SLP_A#", "n/a", "n/a", - "GPD7", "RESERVED", "n/a", "n/a", - "GPD8", "SUSCLK", "n/a", "n/a", - "GPD9", "SLP_WLAN#", "n/a", "n/a", - "GPD10", "SLP_S5#", "n/a", "n/a", - "GPD11", "LANPHYPC", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_gpd = { - .display = "-------- GPIO Group GPD --------", - .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_gpd_names, -}; - -static const struct gpio_group *const sunrise_community_gpd_groups[] = { - &sunrise_group_gpd, -}; - -static const struct gpio_community sunrise_community_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), - .groups = sunrise_community_gpd_groups, -}; - -static const char *const sunrise_group_i_names[] = { - "GPP_I0", "DDPB_HPD0", "n/a", "n/a", - "GPP_I1", "DDPC_HPD1", "n/a", "n/a", - "GPP_I2", "DDPD_HPD2", "n/a", "n/a", - "GPP_I3", "DDPE_HPD3", "n/a", "n/a", - "GPP_I4", "EDP_HPD", "n/a", "n/a", - "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", - "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_i = { - .display = "------- GPIO Group GPP_I -------", - .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_i_names, -}; - -static const struct gpio_group *const sunrise_community_i_groups[] = { - &sunrise_group_i, -}; - -static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { - &sunrise_lp_group_f, &sunrise_lp_group_g, -}; - -static const struct gpio_community sunrise_community_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_community_i_groups), - .groups = sunrise_community_i_groups, -}; - -static const struct gpio_community sunrise_lp_community_fg = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), - .groups = sunrise_lp_community_fg_groups, -}; - -static const struct gpio_community *const sunrise_communities[] = { - &sunrise_community_ab, &sunrise_community_cdefgh, - &sunrise_community_gpd, &sunrise_community_i, -}; - -static const struct gpio_community *const sunrise_lp_communities[] = { - &sunrise_lp_community_ab, &sunrise_lp_community_cde, - &sunrise_community_gpd, &sunrise_lp_community_fg, -}; - static const char *const lewisburg_group_a_names[] = { "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", "GPP_A1", "LAD0", "n/a", "ESPI_IO0", diff --git a/util/inteltool/gpio_names/sunrise.h b/util/inteltool/gpio_names/sunrise.h new file mode 100644 index 0000000000..ff3d1dd9d9 --- /dev/null +++ b/util/inteltool/gpio_names/sunrise.h @@ -0,0 +1,586 @@ +#ifndef GPIO_NAMES_SUNRISE_H +#define GPIO_NAMES_SUNRISE_H + +#include "gpio_groups.h" + +static const char *const sunrise_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "ISH_GP7", "n/a", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const char *const sunrise_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "n/a", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const char *const sunrise_group_b_names[] = { + "GPP_B0", "n/a", "n/a", "n/a", + "GPP_B1", "n/a", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPIO_CS#", "n/a", "n/a", + "GPP_B16", "GSPIO_CLK", "n/a", "n/a", + "GPP_B17", "GSPIO_MISO", "n/a", "n/a", + "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const char *const sunrise_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPI0_CS#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const char *const sunrise_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", +}; + +static const char *const sunrise_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "n/a", + "GPP_D1", "n/a", "n/a", "n/a", + "GPP_D2", "n/a", "n/a", "n/a", + "GPP_D3", "n/a", "n/a", "n/a", + "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", + "GPP_D5", "I2S_SFRM", "n/a", "n/a", + "GPP_D6", "I2S_TXD", "n/a", "n/a", + "GPP_D7", "I2S_RXD", "n/a", "n/a", + "GPP_D8", "I2S_SCLK", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "n/a", + "GPP_D22", "n/a", "n/a", "n/a", + "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", +}; + +static const char *const sunrise_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "n/a", + "GPP_D1", "SPI1_CLK", "n/a", "n/a", + "GPP_D2", "SPI1_MISO", "n/a", "n/a", + "GPP_D3", "SPI1_MOSI", "n/a", "n/a", + "GPP_D4", "FLASHTRIG", "n/a", "n/a", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +static const char *const sunrise_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATA_LED#", "n/a", "n/a", + "GPP_E9", "USB_OC0#", "n/a", "n/a", + "GPP_E10", "USB_OC1#", "n/a", "n/a", + "GPP_E11", "USB_OC2#", "n/a", "n/a", + "GPP_E12", "USB_OC3#", "n/a", "n/a", +}; + +static const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "n/a", "n/a", + "GPP_E14", "DDPC_HPD1", "n/a", "n/a", + "GPP_E15", "DDPD_HPD2", "n/a", "n/a", + "GPP_E16", "DDPE_HPD3", "n/a", "n/a", + "GPP_E17", "EDP_HPD", "n/a", "n/a", + "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + +static const char *const sunrise_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", + "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", + "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", + "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", + "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "n/a", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const char *const sunrise_lp_group_f_names[] = { + "GPP_F0", "I2S2_SCLK", "n/a", "n/a", + "GPP_F1", "I2S2_SFRM", "n/a", "n/a", + "GPP_F2", "I2S2_TXD", "n/a", "n/a", + "GPP_F3", "I2S2_RXD", "n/a", "n/a", + "GPP_F4", "I2C2_SDA", "n/a", "n/a", + "GPP_F5", "I2C2_SCL", "n/a", "n/a", + "GPP_F6", "I2C3_SDA", "n/a", "n/a", + "GPP_F7", "I2C3_SCL", "n/a", "n/a", + "GPP_F8", "I2C4_SDA", "n/a", "n/a", + "GPP_F9", "I2C4_SCL", "n/a", "n/a", + "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_F12", "EMMC_CMD", "n/a", "n/a", + "GPP_F13", "EMMC_DATA0", "n/a", "n/a", + "GPP_F14", "EMMC_DATA1", "n/a", "n/a", + "GPP_F15", "EMMC_DATA2", "n/a", "n/a", + "GPP_F16", "EMMC_DATA3", "n/a", "n/a", + "GPP_F17", "EMMC_DATA4", "n/a", "n/a", + "GPP_F18", "EMMC_DATA5", "n/a", "n/a", + "GPP_F19", "EMMC_DATA6", "n/a", "n/a", + "GPP_F20", "EMMC_DATA7", "n/a", "n/a", + "GPP_F21", "EMMC_RCLK", "n/a", "n/a", + "GPP_F22", "EMMC_CLK", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const char *const sunrise_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "n/a", "n/a", + "GPP_G1", "FAN_TACH_1", "n/a", "n/a", + "GPP_G2", "FAN_TACH_2", "n/a", "n/a", + "GPP_G3", "FAN_TACH_3", "n/a", "n/a", + "GPP_G4", "FAN_TACH_4", "n/a", "n/a", + "GPP_G5", "FAN_TACH_5", "n/a", "n/a", + "GPP_G6", "FAN_TACH_6", "n/a", "n/a", + "GPP_G7", "FAN_TACH_7", "n/a", "n/a", + "GPP_G8", "FAN_PWM_0", "n/a", "n/a", + "GPP_G9", "FAN_PWM_1", "n/a", "n/a", + "GPP_G10", "FAN_PWM_2", "n/a", "n/a", + "GPP_G11", "FAN_PWM_3", "n/a", "n/a", + "GPP_G12", "GSXDOUT", "n/a", "n/a", + "GPP_G13", "GSXSLOAD", "n/a", "n/a", + "GPP_G14", "GSXDIN", "n/a", "n/a", + "GPP_G15", "GSXRESET#", "n/a", "n/a", + "GPP_G16", "GSXCLK", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "n/a", "n/a", + "GPP_G21", "n/a", "n/a", "n/a", + "GPP_G22", "n/a", "n/a", "n/a", + "GPP_G23", "n/a", "n/a", "n/a", +}; + +static const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", + "GPP_G3", "SD_DATA2", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", +}; + +static const char *const sunrise_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "n/a", "n/a", + "GPP_H11", "SML2DATA", "n/a", "n/a", + "GPP_H12", "SML2ALERT#", "n/a", "n/a", + "GPP_H13", "SML3CLK", "n/a", "n/a", + "GPP_H14", "SML3DATA", "n/a", "n/a", + "GPP_H15", "SML3ALERT#", "n/a", "n/a", + "GPP_H16", "SML4CLK", "n/a", "n/a", + "GPP_H17", "SML4DATA", "n/a", "n/a", + "GPP_H18", "SML4ALERT#", "n/a", "n/a", + "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +static const char *const sunrise_group_gpd_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", +}; + +static const char *const sunrise_group_i_names[] = { + "GPP_I0", "DDPB_HPD0", "n/a", "n/a", + "GPP_I1", "DDPC_HPD1", "n/a", "n/a", + "GPP_I2", "DDPD_HPD2", "n/a", "n/a", + "GPP_I3", "DDPE_HPD3", "n/a", "n/a", + "GPP_I4", "EDP_HPD", "n/a", "n/a", + "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", + "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_a_names, +}; + +static const struct gpio_group sunrise_lp_group_a = { + .display = "------- GPIO group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_a_names, +}; + +static const struct gpio_group sunrise_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_b_names, +}; + +static const struct gpio_group sunrise_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_b_names, +}; + +static const struct gpio_group *const sunrise_community_ab_groups[] = { + &sunrise_group_a, &sunrise_group_b, +}; + +static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { + &sunrise_lp_group_a, &sunrise_lp_group_b, +}; + +static const struct gpio_community sunrise_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_community_ab_groups), + .groups = sunrise_community_ab_groups, +}; + +static const struct gpio_community sunrise_lp_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), + .groups = sunrise_lp_community_ab_groups, +}; + +static const struct gpio_group sunrise_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_c_names, +}; + +static const struct gpio_group sunrise_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_d_names, +}; + +static const struct gpio_group sunrise_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_d_names, +}; + +static const struct gpio_group sunrise_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + +static const struct gpio_group sunrise_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_f_names, +}; + +static const struct gpio_group sunrise_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_f_names, +}; + +static const struct gpio_group sunrise_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_g_names, +}; + +static const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + +static const struct gpio_group sunrise_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_h_names, +}; + +static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { + &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, + &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, +}; + +static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, +}; + +static const struct gpio_community sunrise_community_cdefgh = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), + .groups = sunrise_community_cdefgh_groups, +}; + +static const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + +static const struct gpio_group sunrise_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_gpd_names, +}; + +static const struct gpio_group *const sunrise_community_gpd_groups[] = { + &sunrise_group_gpd, +}; + +static const struct gpio_community sunrise_community_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), + .groups = sunrise_community_gpd_groups, +}; + +static const struct gpio_group sunrise_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_i_names, +}; + +static const struct gpio_group *const sunrise_community_i_groups[] = { + &sunrise_group_i, +}; + +static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_lp_group_f, &sunrise_lp_group_g, +}; + +static const struct gpio_community sunrise_community_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_community_i_groups), + .groups = sunrise_community_i_groups, +}; + +static const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + +static const struct gpio_community *const sunrise_communities[] = { + &sunrise_community_ab, &sunrise_community_cdefgh, + &sunrise_community_gpd, &sunrise_community_i, +}; + +static const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_lp_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +}; + +#endif From aff7d1f8642c7dea52e7aff09891087adfd9edf3 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Wed, 29 Jan 2020 09:29:39 +0100 Subject: [PATCH 0468/1463] util/inteltool: Move Lewisburg definitions into their own header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Lewisburg definitions into its own header. Change-Id: I7900f1d8b3ca022112874ac2fa7326d538166008 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38629 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Tested-by: build bot (Jenkins) --- util/inteltool/gpio_groups.c | 456 +------------------------ util/inteltool/gpio_names/lewisburg.h | 462 ++++++++++++++++++++++++++ 2 files changed, 463 insertions(+), 455 deletions(-) create mode 100644 util/inteltool/gpio_names/lewisburg.h diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index f2700a0e98..a2181e1cc1 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -26,466 +26,12 @@ #include "gpio_names/apollolake.h" #include "gpio_names/cannonlake.h" #include "gpio_names/icelake.h" +#include "gpio_names/lewisburg.h" #include "gpio_names/sunrise.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -static const char *const lewisburg_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "n/a", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "n/a", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_LPC2", "n/a", "n/a", - "GPP_A17", "n/a", "n/a", "n/a", - "GPP_A18", "n/a", "n/a", "n/a", - "GPP_A19", "n/a", "n/a", "n/a", - "GPP_A20", "n/a", "n/a", "n/a", - "GPP_A21", "n/a", "n/a", "n/a", - "GPP_A22", "n/a", "n/a", "n/a", - "GPP_A23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(lewisburg_group_a_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_a_names, -}; - -static const char *const lewisburg_group_b_names[] = { - "GPP_B0", "CORE_VID0", "n/a", "n/a", - "GPP_B1", "CORE_VID1", "n/a", "n/a", - "GPP_B2", "n/a", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "n/a", "n/a", "n/a", - "GPP_B12", "GLB_RST_WARN_N#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "n/a", "n/a", "n/a", - "GPP_B16", "n/a", "n/a", "n/a", - "GPP_B17", "n/a", "n/a", "n/a", - "GPP_B18", "n/a", "n/a", "n/a", - "GPP_B19", "n/a", "n/a", "n/a", - "GPP_B20", "n/a", "n/a", "n/a", - "GPP_B21", "n/a", "n/a", "n/a", - "GPP_B22", "n/a", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "MEIE_SML1ALRT#", -}; - -static const struct gpio_group lewisburg_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(lewisburg_group_b_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_b_names, -}; - -static const char *const lewisburg_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", "n/a", - "GPP_C1", "SMBDATA", "n/a", "n/a", - "GPP_C2", "SMBALERT#", "n/a", "n/a", - "GPP_C3", "SML0CLK", "SML0CLK_IE#", "n/a", - "GPP_C4", "SML0DATA", "SML0DATA_IE", "n/a", - "GPP_C5", "SML0ALERT#", "SML0ALERT_IE#", "n/a", - "GPP_C6", "SML1CLK", "SML1CLK_IE", "n/a", - "GPP_C7", "SML1DATA", "SML1DATA_IE", "n/a", - "GPP_C8", "n/a", "n/a", "n/a", - "GPP_C9", "n/a", "n/a", "n/a", - "GPP_C10", "n/a", "n/a", "n/a", - "GPP_C11", "n/a", "n/a", "n/a", - "GPP_C12", "n/a", "n/a", "n/a", - "GPP_C13", "n/a", "n/a", "n/a", - "GPP_C14", "n/a", "n/a", "n/a", - "GPP_C15", "n/a", "n/a", "n/a", - "GPP_C16", "n/a", "n/a", "n/a", - "GPP_C17", "n/a", "n/a", "n/a", - "GPP_C18", "n/a", "n/a", "n/a", - "GPP_C19", "n/a", "n/a", "n/a", - "GPP_C20", "n/a", "n/a", "n/a", - "GPP_C21", "n/a", "n/a", "n/a", - "GPP_C22", "n/a", "n/a", "n/a", - "GPP_C23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(lewisburg_group_c_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_c_names, -}; - -static const char *const lewisburg_group_d_names[] = { - "GPP_D0", "n/a", "n/a", "SERIAL_BLINK", - "GPP_D1", "n/a", "n/a", "SERIAL_BLINK", - "GPP_D2", "n/a", "n/a", "SERIAL_BLINK", - "GPP_D3", "n/a", "n/a", "SERIAL_BLINK", - "GPP_D4", "n/a", "n/a", "SERIAL_BLINK", - "GPP_D5", "n/a", "n/a", "n/a", - "GPP_D6", "n/a", "n/a", "n/a", - "GPP_D7", "n/a", "n/a", "n/a", - "GPP_D8", "n/a", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "SSATA_DEVSLP3", - "GPP_D10", "n/a", "n/a", "SSATA_DEVSLP4", - "GPP_D11", "n/a", "n/a", "SSATA_DEVSLP5", - "GPP_D12", "n/a", "n/a", "SSATA_SDATAOUT1", - "GPP_D13", "n/a", "SML0BCLK", "SML0BCLK_IE", - "GPP_D14", "n/a", "SML0BDATA", "SML0BDATA_IE", - "GPP_D15", "n/a", "n/a", "SSATA_SDATAOUT0", - "GPP_D16", "n/a", "SML0BALERT#", "SML0BALERT_IE#", - "GPP_D17", "n/a", "n/a", "n/a", - "GPP_D18", "n/a", "n/a", "n/a", - "GPP_D19", "n/a", "n/a", "n/a", - "GPP_D20", "n/a", "n/a", "n/a", - "GPP_D21", "n/a", "n/a", "IE_UART_RX", - "GPP_D22", "n/a", "n/a", "IE_UART_TX", - "GPP_D23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(lewisburg_group_d_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_d_names, -}; - -/* The functions in this group are the same as in the pad group E for - the Sunrise-H PCH */ -static const struct gpio_group lewisburg_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_e_names, -}; - -static const char *const lewisburg_group_f_names[] = { - "GPP_F0", "SATAXPCIE3", "n/a", "SATAGP3", - "GPP_F1", "SATAXPCIE4", "n/a", "SATAGP4", - "GPP_F2", "SATAXPCIE5", "n/a", "SATAGP5", - "GPP_F3", "SATAXPCIE6", "n/a", "SATAGP6", - "GPP_F4", "SATAXPCIE7", "n/a", "SATAGP7", - "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", - "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", - "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", - "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", - "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", - "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", - "GPP_F11", "SATA_SLOAD", "n/a", "n/a", - "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", - "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", - "GPP_F14", "n/a", "n/a", "SSATA_LED#", - "GPP_F15", "USB_OC4#", "n/a", "n/a", - "GPP_F16", "USB_OC5#", "n/a", "n/a", - "GPP_F17", "USB_OC6#", "n/a", "n/a", - "GPP_F18", "USB_OC7#", "n/a", "n/a", - "GPP_F19", "LAN_SMBCLK", "n/a", "n/a", - "GPP_F20", "LAN_SMBDATA", "n/a", "n/a", - "GPP_F21", "LAN_SMBALRT#", "n/a", "n/a", - "GPP_F22", "n/a", "n/a", "SSATA_SCLOCK", - "GPP_F23", "n/a", "n/a", "SSATA_SLOAD", -}; - -static const struct gpio_group lewisburg_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(lewisburg_group_f_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_f_names, -}; - -static const char *const lewisburg_group_g_names[] = { - "GPP_G0", "FAN_TACH_0", "FAN_TACH_0_IE", "n/a", - "GPP_G1", "FAN_TACH_1", "FAN_TACH_1_IE", "n/a", - "GPP_G2", "FAN_TACH_2", "FAN_TACH_2_IE", "n/a", - "GPP_G3", "FAN_TACH_3", "FAN_TACH_3_IE", "n/a", - "GPP_G4", "FAN_TACH_4", "FAN_TACH_4_IE", "n/a", - "GPP_G5", "FAN_TACH_5", "FAN_TACH_5_IE", "n/a", - "GPP_G6", "FAN_TACH_6", "FAN_TACH_6_IE", "n/a", - "GPP_G7", "FAN_TACH_7", "FAN_TACH_7_IE", "n/a", - "GPP_G8", "FAN_PWM_0", "FAN_PWM_0_IE", "n/a", - "GPP_G9", "FAN_PWM_1", "FAN_PWM_1_IE", "n/a", - "GPP_G10", "FAN_PWM_2", "FAN_PWM_2_IE", "n/a", - "GPP_G11", "FAN_PWM_3", "FAN_PWM_3_IE", "n/a", - "GPP_G12", "n/a", "n/a", "n/a", - "GPP_G13", "n/a", "n/a", "n/a", - "GPP_G14", "n/a", "n/a", "n/a", - "GPP_G15", "n/a", "n/a", "n/a", - "GPP_G16", "n/a", "n/a", "n/a", - "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", - "GPP_G18", "NMI#", "n/a", "n/a", - "GPP_G19", "SMI#", "n/a", "n/a", - "GPP_G20", "n/a", "SSATA_DEVSLP0", "n/a", - "GPP_G21", "n/a", "SSATA_DEVSLP1", "n/a", - "GPP_G22", "n/a", "SSATA_DEVSLP2", "n/a", - "GPP_G23", "n/a", "SSATAXPCIE0", "SSATAGP0", -}; - -static const struct gpio_group lewisburg_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(lewisburg_group_g_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_g_names, -}; - -static const char *const lewisburg_group_h_names[] = { - "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", - "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", - "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", - "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", - "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", - "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", - "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", - "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", - "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", - "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", - "GPP_H10", "SML2CLK", "SML2CLK_IE", "n/a", - "GPP_H11", "SML2DATA", "SML2DATA_IE", "n/a", - "GPP_H12", "SML2ALERT#", "SML2ALERT#_IE#", "n/a", - "GPP_H13", "SML3CLK", "SML3CLK_IE", "n/a", - "GPP_H14", "SML3DATA", "SML3DATA_IE", "n/a", - "GPP_H15", "SML3ALERT#", "SML3ALERT#_IE#", "n/a", - "GPP_H16", "SML4CLK", "SML4CLK_IE", "n/a", - "GPP_H17", "SML4DATA", "SML4DATA_IE", "n/a", - "GPP_H18", "SML4ALERT#", "SML4ALERT#_IE#", "n/a", - "GPP_H19", "n/a", "SSATAXPCIE1", "SSATAGP1", - "GPP_H20", "n/a", "SSATAXPCIE2", "SSATAGP2", - "GPP_H21", "n/a", "SSATAXPCIE3", "SSATAGP3", - "GPP_H22", "n/a", "SSATAXPCIE4", "SSATAGP4", - "GPP_H23", "n/a", "SSATAXPCIE5", "SSATAGP5", -}; - -static const struct gpio_group lewisburg_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(lewisburg_group_h_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_h_names, -}; - -static const char *const lewisburg_group_i_names[] = { - "GPP_I0", "n/a", "LAN_TDO", "n/a", - "GPP_I1", "n/a", "LAN_TCK", "n/a", - "GPP_I2", "n/a", "LAN_TMS", "n/a", - "GPP_I3", "n/a", "LAN_TDI", "n/a", - "GPP_I4", "n/a", "RESET_IN#", "n/a", - "GPP_I5", "n/a", "RESET_OUT#", "n/a", - "GPP_I6", "n/a", "RESET_DONE", "n/a", - "GPP_I7", "n/a", "LAN_TRST_IN", "n/a", - "GPP_I8", "n/a", "PCI_DIS", "n/a", - "GPP_I9", "n/a", "LAN_DIS", "n/a", - "GPP_I10", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_i = { - .display = "------- GPIO Group GPP_I -------", - .pad_count = ARRAY_SIZE(lewisburg_group_i_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_i_names, -}; - -static const char *const lewisburg_group_j_names[] = { - "GPP_J0", "LAN_LED_P0_0", "n/a", "n/a", - "GPP_J1", "LAN_LED_P0_1", "n/a", "n/a", - "GPP_J2", "LAN_LED_P1_0", "n/a", "n/a", - "GPP_J3", "LAN_LED_P1_1", "n/a", "n/a", - "GPP_J4", "LAN_LED_P2_0", "n/a", "n/a", - "GPP_J5", "LAN_LED_P2_1", "n/a", "n/a", - "GPP_J6", "LAN_LED_P3_0", "n/a", "n/a", - "GPP_J7", "LAN_LED_P3_1", "n/a", "n/a", - "GPP_J8", "LAN_I2C_SCL_MDC_P0", "n/a", "n/a", - "GPP_J9", "LAN_I2C_SDA_MDIO_P0", "n/a", "n/a", - "GPP_J10", "LAN_I2C_SCL_MDC_P1", "n/a", "n/a", - "GPP_J11", "LAN_I2C_SDA_MDIO_P1", "n/a", "n/a", - "GPP_J12", "LAN_I2C_SCL_MDC_P2", "n/a", "n/a", - "GPP_J13", "LAN_I2C_SDA_MDIO_P2", "n/a", "n/a", - "GPP_J14", "LAN_I2C_SCL_MDC_P3", "n/a", "n/a", - "GPP_J15", "LAN_I2C_SDA_MDIO_P3", "n/a", "n/a", - "GPP_J16", "LAN_SDP_P0_0", "n/a", "n/a", - "GPP_J17", "LAN_SDP_P0_1", "n/a", "n/a", - "GPP_J18", "LAN_SDP_P1_0", "n/a", "n/a", - "GPP_J19", "LAN_SDP_P1_1", "n/a", "n/a", - "GPP_J20", "LAN_SDP_P2_0", "n/a", "n/a", - "GPP_J21", "LAN_SDP_P2_1", "n/a", "n/a", - "GPP_J22", "LAN_SDP_P3_0", "n/a", "n/a", - "GPP_J23", "LAN_SDP_P3_1", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_j = { - .display = "------- GPIO Group GPP_J -------", - .pad_count = ARRAY_SIZE(lewisburg_group_j_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_j_names, -}; - -static const char *const lewisburg_group_k_names[] = { - "GPP_K0", "LAN_NCSI_CLK_IN", "n/a", "n/a", - "GPP_K1", "LAN_NCSI_TXD0", "n/a", "n/a", - "GPP_K2", "LAN_NCSI_TXD1", "n/a", "n/a", - "GPP_K3", "LAN_NCSI_TX_EN", "n/a", "n/a", - "GPP_K4", "LAN_NCSI_CRS_DV", "n/a", "n/a", - "GPP_K5", "LAN_NCSI_RXD0", "n/a", "n/a", - "GPP_K6", "LAN_NCSI_RXD1", "n/a", "n/a", - "GPP_K7", "RESERVED", "n/a", "n/a", - "GPP_K8", "LAN_NCSI_ARB_IN", "n/a", "n/a", - "GPP_K9", "LAN_NCSI_ARB_OUT", "n/a", "n/a", - "GPP_K10", "PE_RST#", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_k = { - .display = "------- GPIO Group GPP_K -------", - .pad_count = ARRAY_SIZE(lewisburg_group_k_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_k_names, -}; - -static const char *const lewisburg_group_l_names[] = { - "GPP_L2", "TESTCH0_D0", "n/a", "n/a", - "GPP_L3", "TESTCH0_D1", "n/a", "n/a", - "GPP_L4", "TESTCH0_D2", "n/a", "n/a", - "GPP_L5", "TESTCH0_D3", "n/a", "n/a", - "GPP_L6", "TESTCH0_D4", "n/a", "n/a", - "GPP_L7", "TESTCH0_D5", "n/a", "n/a", - "GPP_L8", "TESTCH0_D6", "n/a", "n/a", - "GPP_L9", "TESTCH0_D7", "n/a", "n/a", - "GPP_L10", "TESTCH0_CLK", "n/a", "n/a", - "GPP_L11", "TESTCH1_D0", "n/a", "n/a", - "GPP_L12", "TESTCH1_D1", "n/a", "n/a", - "GPP_L13", "TESTCH1_D2", "n/a", "n/a", - "GPP_L14", "TESTCH1_D3", "n/a", "n/a", - "GPP_L15", "TESTCH1_D4", "n/a", "n/a", - "GPP_L16", "TESTCH1_D5", "n/a", "n/a", - "GPP_L17", "TESTCH1_D6", "n/a", "n/a", - "GPP_L18", "TESTCH1_D7", "n/a", "n/a", - "GPP_L19", "TESTCH1_CLK", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_l = { - .display = "------- GPIO Group GPP_L -------", - .pad_count = ARRAY_SIZE(lewisburg_group_l_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_l_names, -}; - -static const char *const lewisburg_group_gpd_names[] = { - "GPD0", "POWER_DEBUG_N", "n/a", "n/a", - "GPD1", "ACPRESENT", "n/a", "n/a", - "GPD2", "GBE_WAKE#", "n/a", "n/a", - "GPD3", "PWRBTN#", "n/a", "n/a", - "GPD4", "SLP_S3#", "n/a", "n/a", - "GPD5", "SLP_S4#", "n/a", "n/a", - "GPD6", "SLP_A#", "n/a", "n/a", - "GPD7", "RESERVED", "n/a", "n/a", - "GPD8", "SUSCLK", "n/a", "n/a", - "GPD9", "RESERVED", "n/a", "n/a", - "GPD10", "SLP_S5#", "n/a", "n/a", - "GPD11", "GBEPHY", "n/a", "n/a", -}; - -static const struct gpio_group lewisburg_group_gpd = { - .display = "-------- GPIO Group GPD --------", - .pad_count = ARRAY_SIZE(lewisburg_group_gpd_names) / 4, - .func_count = 4, - .pad_names = lewisburg_group_gpd_names, -}; - -static const struct gpio_group *const lewisburg_community0_abf_groups[] = { - &lewisburg_group_a, - &lewisburg_group_b, - &lewisburg_group_f, -}; - -static const struct gpio_community lewisburg_community0_abf = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), - .groups = lewisburg_community0_abf_groups, -}; - -static const struct gpio_group *const lewisburg_community1_cde_groups[] = { - &lewisburg_group_c, - &lewisburg_group_d, - &lewisburg_group_e, -}; - -static const struct gpio_community lewisburg_community1_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), - .groups = lewisburg_community1_cde_groups, -}; - -static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { - &lewisburg_group_gpd, -}; - -static const struct gpio_community lewisburg_community2_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), - .groups = lewisburg_community2_gpd_groups, -}; - -static const struct gpio_group *const lewisburg_community3_i_groups[] = { - &lewisburg_group_i, -}; - -static const struct gpio_community lewisburg_community3_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), - .groups = lewisburg_community3_i_groups, -}; - -static const struct gpio_group *const lewisburg_community4_jk_groups[] = { - &lewisburg_group_j, - &lewisburg_group_k, -}; - -static const struct gpio_community lewisburg_community4_jk = { - .name = "------- GPIO Community 4 -------", - .pcr_port_id = 0xab, - .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), - .groups = lewisburg_community4_jk_groups, -}; - -static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { - &lewisburg_group_g, - &lewisburg_group_h, - &lewisburg_group_l, -}; - -static const struct gpio_community lewisburg_community5_ghl = { - .name = "------- GPIO Community 5 -------", - .pcr_port_id = 0x11, - .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), - .groups = lewisburg_community5_ghl_groups, -}; - -static const struct gpio_community *const lewisburg_communities[] = { - &lewisburg_community0_abf, - &lewisburg_community1_cde, - &lewisburg_community2_gpd, - &lewisburg_community3_i, - &lewisburg_community4_jk, - &lewisburg_community5_ghl, -}; - static const char *const denverton_group_north_all_names[] = { "NORTH_ALL_GBE0_SDP0", "NORTH_ALL_GBE1_SDP0", diff --git a/util/inteltool/gpio_names/lewisburg.h b/util/inteltool/gpio_names/lewisburg.h new file mode 100644 index 0000000000..4d5917798b --- /dev/null +++ b/util/inteltool/gpio_names/lewisburg.h @@ -0,0 +1,462 @@ +#ifndef GPIO_NAMES_LEWISBURG_H +#define GPIO_NAMES_LEWISBURG_H + +#include "gpio_groups.h" +#include "sunrise.h" + +static const char *const lewisburg_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "n/a", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "n/a", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_LPC2", "n/a", "n/a", + "GPP_A17", "n/a", "n/a", "n/a", + "GPP_A18", "n/a", "n/a", "n/a", + "GPP_A19", "n/a", "n/a", "n/a", + "GPP_A20", "n/a", "n/a", "n/a", + "GPP_A21", "n/a", "n/a", "n/a", + "GPP_A22", "n/a", "n/a", "n/a", + "GPP_A23", "n/a", "n/a", "n/a", +}; + +static const char *const lewisburg_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "n/a", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "GLB_RST_WARN_N#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "n/a", "n/a", "n/a", + "GPP_B16", "n/a", "n/a", "n/a", + "GPP_B17", "n/a", "n/a", "n/a", + "GPP_B18", "n/a", "n/a", "n/a", + "GPP_B19", "n/a", "n/a", "n/a", + "GPP_B20", "n/a", "n/a", "n/a", + "GPP_B21", "n/a", "n/a", "n/a", + "GPP_B22", "n/a", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "MEIE_SML1ALRT#", +}; + +static const char *const lewisburg_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "SML0CLK_IE#", "n/a", + "GPP_C4", "SML0DATA", "SML0DATA_IE", "n/a", + "GPP_C5", "SML0ALERT#", "SML0ALERT_IE#", "n/a", + "GPP_C6", "SML1CLK", "SML1CLK_IE", "n/a", + "GPP_C7", "SML1DATA", "SML1DATA_IE", "n/a", + "GPP_C8", "n/a", "n/a", "n/a", + "GPP_C9", "n/a", "n/a", "n/a", + "GPP_C10", "n/a", "n/a", "n/a", + "GPP_C11", "n/a", "n/a", "n/a", + "GPP_C12", "n/a", "n/a", "n/a", + "GPP_C13", "n/a", "n/a", "n/a", + "GPP_C14", "n/a", "n/a", "n/a", + "GPP_C15", "n/a", "n/a", "n/a", + "GPP_C16", "n/a", "n/a", "n/a", + "GPP_C17", "n/a", "n/a", "n/a", + "GPP_C18", "n/a", "n/a", "n/a", + "GPP_C19", "n/a", "n/a", "n/a", + "GPP_C20", "n/a", "n/a", "n/a", + "GPP_C21", "n/a", "n/a", "n/a", + "GPP_C22", "n/a", "n/a", "n/a", + "GPP_C23", "n/a", "n/a", "n/a", +}; + +static const char *const lewisburg_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D1", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D2", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D3", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D4", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D5", "n/a", "n/a", "n/a", + "GPP_D6", "n/a", "n/a", "n/a", + "GPP_D7", "n/a", "n/a", "n/a", + "GPP_D8", "n/a", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "SSATA_DEVSLP3", + "GPP_D10", "n/a", "n/a", "SSATA_DEVSLP4", + "GPP_D11", "n/a", "n/a", "SSATA_DEVSLP5", + "GPP_D12", "n/a", "n/a", "SSATA_SDATAOUT1", + "GPP_D13", "n/a", "SML0BCLK", "SML0BCLK_IE", + "GPP_D14", "n/a", "SML0BDATA", "SML0BDATA_IE", + "GPP_D15", "n/a", "n/a", "SSATA_SDATAOUT0", + "GPP_D16", "n/a", "SML0BALERT#", "SML0BALERT_IE#", + "GPP_D17", "n/a", "n/a", "n/a", + "GPP_D18", "n/a", "n/a", "n/a", + "GPP_D19", "n/a", "n/a", "n/a", + "GPP_D20", "n/a", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "IE_UART_RX", + "GPP_D22", "n/a", "n/a", "IE_UART_TX", + "GPP_D23", "n/a", "n/a", "n/a", +}; + +static const char *const lewisburg_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "n/a", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "n/a", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "n/a", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "n/a", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "n/a", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "SSATA_LED#", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "LAN_SMBCLK", "n/a", "n/a", + "GPP_F20", "LAN_SMBDATA", "n/a", "n/a", + "GPP_F21", "LAN_SMBALRT#", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "SSATA_SCLOCK", + "GPP_F23", "n/a", "n/a", "SSATA_SLOAD", +}; + +static const char *const lewisburg_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "FAN_TACH_0_IE", "n/a", + "GPP_G1", "FAN_TACH_1", "FAN_TACH_1_IE", "n/a", + "GPP_G2", "FAN_TACH_2", "FAN_TACH_2_IE", "n/a", + "GPP_G3", "FAN_TACH_3", "FAN_TACH_3_IE", "n/a", + "GPP_G4", "FAN_TACH_4", "FAN_TACH_4_IE", "n/a", + "GPP_G5", "FAN_TACH_5", "FAN_TACH_5_IE", "n/a", + "GPP_G6", "FAN_TACH_6", "FAN_TACH_6_IE", "n/a", + "GPP_G7", "FAN_TACH_7", "FAN_TACH_7_IE", "n/a", + "GPP_G8", "FAN_PWM_0", "FAN_PWM_0_IE", "n/a", + "GPP_G9", "FAN_PWM_1", "FAN_PWM_1_IE", "n/a", + "GPP_G10", "FAN_PWM_2", "FAN_PWM_2_IE", "n/a", + "GPP_G11", "FAN_PWM_3", "FAN_PWM_3_IE", "n/a", + "GPP_G12", "n/a", "n/a", "n/a", + "GPP_G13", "n/a", "n/a", "n/a", + "GPP_G14", "n/a", "n/a", "n/a", + "GPP_G15", "n/a", "n/a", "n/a", + "GPP_G16", "n/a", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "SSATA_DEVSLP0", "n/a", + "GPP_G21", "n/a", "SSATA_DEVSLP1", "n/a", + "GPP_G22", "n/a", "SSATA_DEVSLP2", "n/a", + "GPP_G23", "n/a", "SSATAXPCIE0", "SSATAGP0", +}; + +static const char *const lewisburg_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "SML2CLK_IE", "n/a", + "GPP_H11", "SML2DATA", "SML2DATA_IE", "n/a", + "GPP_H12", "SML2ALERT#", "SML2ALERT#_IE#", "n/a", + "GPP_H13", "SML3CLK", "SML3CLK_IE", "n/a", + "GPP_H14", "SML3DATA", "SML3DATA_IE", "n/a", + "GPP_H15", "SML3ALERT#", "SML3ALERT#_IE#", "n/a", + "GPP_H16", "SML4CLK", "SML4CLK_IE", "n/a", + "GPP_H17", "SML4DATA", "SML4DATA_IE", "n/a", + "GPP_H18", "SML4ALERT#", "SML4ALERT#_IE#", "n/a", + "GPP_H19", "n/a", "SSATAXPCIE1", "SSATAGP1", + "GPP_H20", "n/a", "SSATAXPCIE2", "SSATAGP2", + "GPP_H21", "n/a", "SSATAXPCIE3", "SSATAGP3", + "GPP_H22", "n/a", "SSATAXPCIE4", "SSATAGP4", + "GPP_H23", "n/a", "SSATAXPCIE5", "SSATAGP5", +}; + +static const char *const lewisburg_group_i_names[] = { + "GPP_I0", "n/a", "LAN_TDO", "n/a", + "GPP_I1", "n/a", "LAN_TCK", "n/a", + "GPP_I2", "n/a", "LAN_TMS", "n/a", + "GPP_I3", "n/a", "LAN_TDI", "n/a", + "GPP_I4", "n/a", "RESET_IN#", "n/a", + "GPP_I5", "n/a", "RESET_OUT#", "n/a", + "GPP_I6", "n/a", "RESET_DONE", "n/a", + "GPP_I7", "n/a", "LAN_TRST_IN", "n/a", + "GPP_I8", "n/a", "PCI_DIS", "n/a", + "GPP_I9", "n/a", "LAN_DIS", "n/a", + "GPP_I10", "n/a", "n/a", "n/a", +}; + +static const char *const lewisburg_group_j_names[] = { + "GPP_J0", "LAN_LED_P0_0", "n/a", "n/a", + "GPP_J1", "LAN_LED_P0_1", "n/a", "n/a", + "GPP_J2", "LAN_LED_P1_0", "n/a", "n/a", + "GPP_J3", "LAN_LED_P1_1", "n/a", "n/a", + "GPP_J4", "LAN_LED_P2_0", "n/a", "n/a", + "GPP_J5", "LAN_LED_P2_1", "n/a", "n/a", + "GPP_J6", "LAN_LED_P3_0", "n/a", "n/a", + "GPP_J7", "LAN_LED_P3_1", "n/a", "n/a", + "GPP_J8", "LAN_I2C_SCL_MDC_P0", "n/a", "n/a", + "GPP_J9", "LAN_I2C_SDA_MDIO_P0", "n/a", "n/a", + "GPP_J10", "LAN_I2C_SCL_MDC_P1", "n/a", "n/a", + "GPP_J11", "LAN_I2C_SDA_MDIO_P1", "n/a", "n/a", + "GPP_J12", "LAN_I2C_SCL_MDC_P2", "n/a", "n/a", + "GPP_J13", "LAN_I2C_SDA_MDIO_P2", "n/a", "n/a", + "GPP_J14", "LAN_I2C_SCL_MDC_P3", "n/a", "n/a", + "GPP_J15", "LAN_I2C_SDA_MDIO_P3", "n/a", "n/a", + "GPP_J16", "LAN_SDP_P0_0", "n/a", "n/a", + "GPP_J17", "LAN_SDP_P0_1", "n/a", "n/a", + "GPP_J18", "LAN_SDP_P1_0", "n/a", "n/a", + "GPP_J19", "LAN_SDP_P1_1", "n/a", "n/a", + "GPP_J20", "LAN_SDP_P2_0", "n/a", "n/a", + "GPP_J21", "LAN_SDP_P2_1", "n/a", "n/a", + "GPP_J22", "LAN_SDP_P3_0", "n/a", "n/a", + "GPP_J23", "LAN_SDP_P3_1", "n/a", "n/a", +}; + +static const char *const lewisburg_group_k_names[] = { + "GPP_K0", "LAN_NCSI_CLK_IN", "n/a", "n/a", + "GPP_K1", "LAN_NCSI_TXD0", "n/a", "n/a", + "GPP_K2", "LAN_NCSI_TXD1", "n/a", "n/a", + "GPP_K3", "LAN_NCSI_TX_EN", "n/a", "n/a", + "GPP_K4", "LAN_NCSI_CRS_DV", "n/a", "n/a", + "GPP_K5", "LAN_NCSI_RXD0", "n/a", "n/a", + "GPP_K6", "LAN_NCSI_RXD1", "n/a", "n/a", + "GPP_K7", "RESERVED", "n/a", "n/a", + "GPP_K8", "LAN_NCSI_ARB_IN", "n/a", "n/a", + "GPP_K9", "LAN_NCSI_ARB_OUT", "n/a", "n/a", + "GPP_K10", "PE_RST#", "n/a", "n/a", +}; + +static const char *const lewisburg_group_l_names[] = { + "GPP_L2", "TESTCH0_D0", "n/a", "n/a", + "GPP_L3", "TESTCH0_D1", "n/a", "n/a", + "GPP_L4", "TESTCH0_D2", "n/a", "n/a", + "GPP_L5", "TESTCH0_D3", "n/a", "n/a", + "GPP_L6", "TESTCH0_D4", "n/a", "n/a", + "GPP_L7", "TESTCH0_D5", "n/a", "n/a", + "GPP_L8", "TESTCH0_D6", "n/a", "n/a", + "GPP_L9", "TESTCH0_D7", "n/a", "n/a", + "GPP_L10", "TESTCH0_CLK", "n/a", "n/a", + "GPP_L11", "TESTCH1_D0", "n/a", "n/a", + "GPP_L12", "TESTCH1_D1", "n/a", "n/a", + "GPP_L13", "TESTCH1_D2", "n/a", "n/a", + "GPP_L14", "TESTCH1_D3", "n/a", "n/a", + "GPP_L15", "TESTCH1_D4", "n/a", "n/a", + "GPP_L16", "TESTCH1_D5", "n/a", "n/a", + "GPP_L17", "TESTCH1_D6", "n/a", "n/a", + "GPP_L18", "TESTCH1_D7", "n/a", "n/a", + "GPP_L19", "TESTCH1_CLK", "n/a", "n/a", +}; + +static const char *const lewisburg_group_gpd_names[] = { + "GPD0", "POWER_DEBUG_N", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "GBE_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "RESERVED", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "GBEPHY", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(lewisburg_group_a_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_a_names, +}; + +static const struct gpio_group lewisburg_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(lewisburg_group_b_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_b_names, +}; + +static const struct gpio_group lewisburg_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(lewisburg_group_c_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_c_names, +}; + +static const struct gpio_group lewisburg_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(lewisburg_group_d_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_d_names, +}; + +/* The functions in this group are the same as in the pad group E for + the Sunrise-H PCH */ +static const struct gpio_group lewisburg_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const struct gpio_group lewisburg_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(lewisburg_group_f_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_f_names, +}; + +static const struct gpio_group lewisburg_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(lewisburg_group_g_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_g_names, +}; + +static const struct gpio_group lewisburg_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(lewisburg_group_h_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_h_names, +}; + +static const struct gpio_group lewisburg_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(lewisburg_group_i_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_i_names, +}; + +static const struct gpio_group lewisburg_group_j = { + .display = "------- GPIO Group GPP_J -------", + .pad_count = ARRAY_SIZE(lewisburg_group_j_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_j_names, +}; + +static const struct gpio_group lewisburg_group_k = { + .display = "------- GPIO Group GPP_K -------", + .pad_count = ARRAY_SIZE(lewisburg_group_k_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_k_names, +}; + +static const struct gpio_group lewisburg_group_l = { + .display = "------- GPIO Group GPP_L -------", + .pad_count = ARRAY_SIZE(lewisburg_group_l_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_l_names, +}; + +static const struct gpio_group lewisburg_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(lewisburg_group_gpd_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_gpd_names, +}; + +static const struct gpio_group *const lewisburg_community0_abf_groups[] = { + &lewisburg_group_a, + &lewisburg_group_b, + &lewisburg_group_f, +}; + +static const struct gpio_community lewisburg_community0_abf = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), + .groups = lewisburg_community0_abf_groups, +}; + +static const struct gpio_group *const lewisburg_community1_cde_groups[] = { + &lewisburg_group_c, + &lewisburg_group_d, + &lewisburg_group_e, +}; + +static const struct gpio_community lewisburg_community1_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), + .groups = lewisburg_community1_cde_groups, +}; + +static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { + &lewisburg_group_gpd, +}; + +static const struct gpio_community lewisburg_community2_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), + .groups = lewisburg_community2_gpd_groups, +}; + +static const struct gpio_group *const lewisburg_community3_i_groups[] = { + &lewisburg_group_i, +}; + +static const struct gpio_community lewisburg_community3_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), + .groups = lewisburg_community3_i_groups, +}; + +static const struct gpio_group *const lewisburg_community4_jk_groups[] = { + &lewisburg_group_j, + &lewisburg_group_k, +}; + +static const struct gpio_community lewisburg_community4_jk = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0xab, + .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), + .groups = lewisburg_community4_jk_groups, +}; + +static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { + &lewisburg_group_g, + &lewisburg_group_h, + &lewisburg_group_l, +}; + +static const struct gpio_community lewisburg_community5_ghl = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x11, + .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), + .groups = lewisburg_community5_ghl_groups, +}; + +static const struct gpio_community *const lewisburg_communities[] = { + &lewisburg_community0_abf, + &lewisburg_community1_cde, + &lewisburg_community2_gpd, + &lewisburg_community3_i, + &lewisburg_community4_jk, + &lewisburg_community5_ghl, +}; + +#endif From 7da602ff47a7681e5d2d0c1a42e8a7ea46b57e49 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Wed, 29 Jan 2020 09:51:25 +0100 Subject: [PATCH 0469/1463] util/inteltool: Move Denverton definitions into their own header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moved the Denverton definitions into its own header. Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Tested-by: build bot (Jenkins) --- util/inteltool/gpio_groups.c | 223 +------------------------ util/inteltool/gpio_names/denverton.h | 229 ++++++++++++++++++++++++++ 2 files changed, 230 insertions(+), 222 deletions(-) create mode 100644 util/inteltool/gpio_names/denverton.h diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index a2181e1cc1..8b60c2b5b6 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -25,6 +25,7 @@ #include "gpio_names/apollolake.h" #include "gpio_names/cannonlake.h" +#include "gpio_names/denverton.h" #include "gpio_names/icelake.h" #include "gpio_names/lewisburg.h" #include "gpio_names/sunrise.h" @@ -32,228 +33,6 @@ #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -static const char *const denverton_group_north_all_names[] = { - "NORTH_ALL_GBE0_SDP0", - "NORTH_ALL_GBE1_SDP0", - "NORTH_ALL_GBE0_SDP1", - "NORTH_ALL_GBE1_SDP1", - "NORTH_ALL_GBE0_SDP2", - "NORTH_ALL_GBE1_SDP2", - "NORTH_ALL_GBE0_SDP3", - "NORTH_ALL_GBE1_SDP3", - "NORTH_ALL_GBE2_LED0", - "NORTH_ALL_GBE2_LED1", - "NORTH_ALL_GBE0_I2C_CLK", - "NORTH_ALL_GBE0_I2C_DATA", - "NORTH_ALL_GBE1_I2C_CLK", - "NORTH_ALL_GBE1_I2C_DATA", - "NORTH_ALL_NCSI_RXD0", - "NORTH_ALL_NCSI_CLK_IN", - "NORTH_ALL_NCSI_RXD1", - "NORTH_ALL_NCSI_CRS_DV", - "NORTH_ALL_NCSI_ARB_IN", - "NORTH_ALL_NCSI_TX_EN", - "NORTH_ALL_NCSI_TXD0", - "NORTH_ALL_NCSI_TXD1", - "NORTH_ALL_NCSI_ARB_OUT", - "NORTH_ALL_GBE0_LED0", - "NORTH_ALL_GBE0_LED1", - "NORTH_ALL_GBE1_LED0", - "NORTH_ALL_GBE1_LED1", - "NORTH_ALL_GPIO_0", - "NORTH_ALL_PCIE_CLKREQ0_N", - "NORTH_ALL_PCIE_CLKREQ1_N", - "NORTH_ALL_PCIE_CLKREQ2_N", - "NORTH_ALL_PCIE_CLKREQ3_N", - "NORTH_ALL_PCIE_CLKREQ4_N", - "NORTH_ALL_GPIO_1", - "NORTH_ALL_GPIO_2", - "NORTH_ALL_SVID_ALERT_N", - "NORTH_ALL_SVID_DATA", - "NORTH_ALL_SVID_CLK", - "NORTH_ALL_THERMTRIP_N", - "NORTH_ALL_PROCHOT_N", - "NORTH_ALL_MEMHOT_N", -}; - -static const struct gpio_group denverton_group_north_all = { - .display = "------- GPIO Group North All -------", - .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, - .func_count = 1, - .pad_names = denverton_group_north_all_names, -}; - -static const struct gpio_group *const denverton_community_north_groups[] = { - &denverton_group_north_all, -}; - -static const struct gpio_community denverton_community_north = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xc2, - .group_count = ARRAY_SIZE(denverton_community_north_groups), - .groups = denverton_community_north_groups, -}; - -static const char *const denverton_group_south_dfx_names[] = { - "SOUTH_DFX_DFX_PORT_CLK0", - "SOUTH_DFX_DFX_PORT_CLK1", - "SOUTH_DFX_DFX_PORT0", - "SOUTH_DFX_DFX_PORT1", - "SOUTH_DFX_DFX_PORT2", - "SOUTH_DFX_DFX_PORT3", - "SOUTH_DFX_DFX_PORT4", - "SOUTH_DFX_DFX_PORT5", - "SOUTH_DFX_DFX_PORT6", - "SOUTH_DFX_DFX_PORT7", - "SOUTH_DFX_DFX_PORT8", - "SOUTH_DFX_DFX_PORT9", - "SOUTH_DFX_DFX_PORT10", - "SOUTH_DFX_DFX_PORT11", - "SOUTH_DFX_DFX_PORT12", - "SOUTH_DFX_DFX_PORT13", - "SOUTH_DFX_DFX_PORT14", - "SOUTH_DFX_DFX_PORT15", -}; - -static const struct gpio_group denverton_group_south_dfx = { - .display = "------- GPIO Group South DFX -------", - .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_dfx_names, -}; - -static const char *const denverton_group_south_group0_names[] = { - "SOUTH_GROUP0_GPIO_12", - "SOUTH_GROUP0_SMB5_GBE_ALRT_N", - "SOUTH_GROUP0_PCIE_CLKREQ5_N", - "SOUTH_GROUP0_PCIE_CLKREQ6_N", - "SOUTH_GROUP0_PCIE_CLKREQ7_N", - "SOUTH_GROUP0_UART0_RXD", - "SOUTH_GROUP0_UART0_TXD", - "SOUTH_GROUP0_SMB5_GBE_CLK", - "SOUTH_GROUP0_SMB5_GBE_DATA", - "SOUTH_GROUP0_ERROR2_N", - "SOUTH_GROUP0_ERROR1_N", - "SOUTH_GROUP0_ERROR0_N", - "SOUTH_GROUP0_IERR_N", - "SOUTH_GROUP0_MCERR_N", - "SOUTH_GROUP0_SMB0_LEG_CLK", - "SOUTH_GROUP0_SMB0_LEG_DATA", - "SOUTH_GROUP0_SMB0_LEG_ALRT_N", - "SOUTH_GROUP0_SMB1_HOST_DATA", - "SOUTH_GROUP0_SMB1_HOST_CLK", - "SOUTH_GROUP0_SMB2_PECI_DATA", - "SOUTH_GROUP0_SMB2_PECI_CLK", - "SOUTH_GROUP0_SMB4_CSME0_DATA", - "SOUTH_GROUP0_SMB4_CSME0_CLK", - "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", - "SOUTH_GROUP0_USB_OC0_N", - "SOUTH_GROUP0_FLEX_CLK_SE0", - "SOUTH_GROUP0_FLEX_CLK_SE1", - "SOUTH_GROUP0_GPIO_4", - "SOUTH_GROUP0_GPIO_5", - "SOUTH_GROUP0_GPIO_6", - "SOUTH_GROUP0_GPIO_7", - "SOUTH_GROUP0_SATA0_LED_N", - "SOUTH_GROUP0_SATA1_LED_N", - "SOUTH_GROUP0_SATA_PDETECT0", - "SOUTH_GROUP0_SATA_PDETECT1", - "SOUTH_GROUP0_SATA0_SDOUT", - "SOUTH_GROUP0_SATA1_SDOUT", - "SOUTH_GROUP0_UART1_RXD", - "SOUTH_GROUP0_UART1_TXD", - "SOUTH_GROUP0_GPIO_8", - "SOUTH_GROUP0_GPIO_9", - "SOUTH_GROUP0_TCK", - "SOUTH_GROUP0_TRST_N", - "SOUTH_GROUP0_TMS", - "SOUTH_GROUP0_TDI", - "SOUTH_GROUP0_TDO", - "SOUTH_GROUP0_CX_PRDY_N", - "SOUTH_GROUP0_CX_PREQ_N", - "SOUTH_GROUP0_CTBTRIGINOUT", - "SOUTH_GROUP0_CTBTRIGOUT", - "SOUTH_GROUP0_DFX_SPARE2", - "SOUTH_GROUP0_DFX_SPARE3", - "SOUTH_GROUP0_DFX_SPARE4", -}; - -static const struct gpio_group denverton_group_south_group0 = { - .display = "------- GPIO Group South Group0 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group0_names, -}; - -static const char *const denverton_group_south_group1_names[] = { - "SOUTH_GROUP1_SUSPWRDNACK", - "SOUTH_GROUP1_PMU_SUSCLK", - "SOUTH_GROUP1_ADR_TRIGGER", - "SOUTH_GROUP1_PMU_SLP_S45_N", - "SOUTH_GROUP1_PMU_SLP_S3_N", - "SOUTH_GROUP1_PMU_WAKE_N", - "SOUTH_GROUP1_PMU_PWRBTN_N", - "SOUTH_GROUP1_PMU_RESETBUTTON_N", - "SOUTH_GROUP1_PMU_PLTRST_N", - "SOUTH_GROUP1_SUS_STAT_N", - "SOUTH_GROUP1_SLP_S0IX_N", - "SOUTH_GROUP1_SPI_CS0_N", - "SOUTH_GROUP1_SPI_CS1_N", - "SOUTH_GROUP1_SPI_MOSI_IO0", - "SOUTH_GROUP1_SPI_MISO_IO1", - "SOUTH_GROUP1_SPI_IO2", - "SOUTH_GROUP1_SPI_IO3", - "SOUTH_GROUP1_SPI_CLK", - "SOUTH_GROUP1_SPI_CLK_LOOPBK", - "SOUTH_GROUP1_ESPI_IO0", - "SOUTH_GROUP1_ESPI_IO1", - "SOUTH_GROUP1_ESPI_IO2", - "SOUTH_GROUP1_ESPI_IO3", - "SOUTH_GROUP1_ESPI_CS0_N", - "SOUTH_GROUP1_ESPI_CLK", - "SOUTH_GROUP1_ESPI_RST_N", - "SOUTH_GROUP1_ESPI_ALRT0_N", - "SOUTH_GROUP1_GPIO_10", - "SOUTH_GROUP1_GPIO_11", - "SOUTH_GROUP1_ESPI_CLK_LOOPBK", - "SOUTH_GROUP1_EMMC_CMD", - "SOUTH_GROUP1_EMMC_STROBE", - "SOUTH_GROUP1_EMMC_CLK", - "SOUTH_GROUP1_EMMC_D0", - "SOUTH_GROUP1_EMMC_D1", - "SOUTH_GROUP1_EMMC_D2", - "SOUTH_GROUP1_EMMC_D3", - "SOUTH_GROUP1_EMMC_D4", - "SOUTH_GROUP1_EMMC_D5", - "SOUTH_GROUP1_EMMC_D6", - "SOUTH_GROUP1_EMMC_D7", - "SOUTH_GROUP1_GPIO_3", -}; - -static const struct gpio_group denverton_group_south_group1 = { - .display = "------- GPIO Group South Group1 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group1_names, -}; - -static const struct gpio_group *const denverton_community_south_groups[] = { - &denverton_group_south_dfx, - &denverton_group_south_group0, - &denverton_group_south_group1, -}; - -static const struct gpio_community denverton_community_south = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xc5, - .group_count = ARRAY_SIZE(denverton_community_south_groups), - .groups = denverton_community_south_groups, -}; - -static const struct gpio_community *const denverton_communities[] = { - &denverton_community_north, &denverton_community_south, -}; - static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { diff --git a/util/inteltool/gpio_names/denverton.h b/util/inteltool/gpio_names/denverton.h new file mode 100644 index 0000000000..8c56cd275b --- /dev/null +++ b/util/inteltool/gpio_names/denverton.h @@ -0,0 +1,229 @@ +#ifndef GPIO_NAMES_DENVERTON_H +#define GPIO_NAMES_DENVERTON_H + +#include "gpio_groups.h" + +static const char *const denverton_group_north_all_names[] = { + "NORTH_ALL_GBE0_SDP0", + "NORTH_ALL_GBE1_SDP0", + "NORTH_ALL_GBE0_SDP1", + "NORTH_ALL_GBE1_SDP1", + "NORTH_ALL_GBE0_SDP2", + "NORTH_ALL_GBE1_SDP2", + "NORTH_ALL_GBE0_SDP3", + "NORTH_ALL_GBE1_SDP3", + "NORTH_ALL_GBE2_LED0", + "NORTH_ALL_GBE2_LED1", + "NORTH_ALL_GBE0_I2C_CLK", + "NORTH_ALL_GBE0_I2C_DATA", + "NORTH_ALL_GBE1_I2C_CLK", + "NORTH_ALL_GBE1_I2C_DATA", + "NORTH_ALL_NCSI_RXD0", + "NORTH_ALL_NCSI_CLK_IN", + "NORTH_ALL_NCSI_RXD1", + "NORTH_ALL_NCSI_CRS_DV", + "NORTH_ALL_NCSI_ARB_IN", + "NORTH_ALL_NCSI_TX_EN", + "NORTH_ALL_NCSI_TXD0", + "NORTH_ALL_NCSI_TXD1", + "NORTH_ALL_NCSI_ARB_OUT", + "NORTH_ALL_GBE0_LED0", + "NORTH_ALL_GBE0_LED1", + "NORTH_ALL_GBE1_LED0", + "NORTH_ALL_GBE1_LED1", + "NORTH_ALL_GPIO_0", + "NORTH_ALL_PCIE_CLKREQ0_N", + "NORTH_ALL_PCIE_CLKREQ1_N", + "NORTH_ALL_PCIE_CLKREQ2_N", + "NORTH_ALL_PCIE_CLKREQ3_N", + "NORTH_ALL_PCIE_CLKREQ4_N", + "NORTH_ALL_GPIO_1", + "NORTH_ALL_GPIO_2", + "NORTH_ALL_SVID_ALERT_N", + "NORTH_ALL_SVID_DATA", + "NORTH_ALL_SVID_CLK", + "NORTH_ALL_THERMTRIP_N", + "NORTH_ALL_PROCHOT_N", + "NORTH_ALL_MEMHOT_N", +}; + +static const char *const denverton_group_south_dfx_names[] = { + "SOUTH_DFX_DFX_PORT_CLK0", + "SOUTH_DFX_DFX_PORT_CLK1", + "SOUTH_DFX_DFX_PORT0", + "SOUTH_DFX_DFX_PORT1", + "SOUTH_DFX_DFX_PORT2", + "SOUTH_DFX_DFX_PORT3", + "SOUTH_DFX_DFX_PORT4", + "SOUTH_DFX_DFX_PORT5", + "SOUTH_DFX_DFX_PORT6", + "SOUTH_DFX_DFX_PORT7", + "SOUTH_DFX_DFX_PORT8", + "SOUTH_DFX_DFX_PORT9", + "SOUTH_DFX_DFX_PORT10", + "SOUTH_DFX_DFX_PORT11", + "SOUTH_DFX_DFX_PORT12", + "SOUTH_DFX_DFX_PORT13", + "SOUTH_DFX_DFX_PORT14", + "SOUTH_DFX_DFX_PORT15", +}; + +static const char *const denverton_group_south_group0_names[] = { + "SOUTH_GROUP0_GPIO_12", + "SOUTH_GROUP0_SMB5_GBE_ALRT_N", + "SOUTH_GROUP0_PCIE_CLKREQ5_N", + "SOUTH_GROUP0_PCIE_CLKREQ6_N", + "SOUTH_GROUP0_PCIE_CLKREQ7_N", + "SOUTH_GROUP0_UART0_RXD", + "SOUTH_GROUP0_UART0_TXD", + "SOUTH_GROUP0_SMB5_GBE_CLK", + "SOUTH_GROUP0_SMB5_GBE_DATA", + "SOUTH_GROUP0_ERROR2_N", + "SOUTH_GROUP0_ERROR1_N", + "SOUTH_GROUP0_ERROR0_N", + "SOUTH_GROUP0_IERR_N", + "SOUTH_GROUP0_MCERR_N", + "SOUTH_GROUP0_SMB0_LEG_CLK", + "SOUTH_GROUP0_SMB0_LEG_DATA", + "SOUTH_GROUP0_SMB0_LEG_ALRT_N", + "SOUTH_GROUP0_SMB1_HOST_DATA", + "SOUTH_GROUP0_SMB1_HOST_CLK", + "SOUTH_GROUP0_SMB2_PECI_DATA", + "SOUTH_GROUP0_SMB2_PECI_CLK", + "SOUTH_GROUP0_SMB4_CSME0_DATA", + "SOUTH_GROUP0_SMB4_CSME0_CLK", + "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", + "SOUTH_GROUP0_USB_OC0_N", + "SOUTH_GROUP0_FLEX_CLK_SE0", + "SOUTH_GROUP0_FLEX_CLK_SE1", + "SOUTH_GROUP0_GPIO_4", + "SOUTH_GROUP0_GPIO_5", + "SOUTH_GROUP0_GPIO_6", + "SOUTH_GROUP0_GPIO_7", + "SOUTH_GROUP0_SATA0_LED_N", + "SOUTH_GROUP0_SATA1_LED_N", + "SOUTH_GROUP0_SATA_PDETECT0", + "SOUTH_GROUP0_SATA_PDETECT1", + "SOUTH_GROUP0_SATA0_SDOUT", + "SOUTH_GROUP0_SATA1_SDOUT", + "SOUTH_GROUP0_UART1_RXD", + "SOUTH_GROUP0_UART1_TXD", + "SOUTH_GROUP0_GPIO_8", + "SOUTH_GROUP0_GPIO_9", + "SOUTH_GROUP0_TCK", + "SOUTH_GROUP0_TRST_N", + "SOUTH_GROUP0_TMS", + "SOUTH_GROUP0_TDI", + "SOUTH_GROUP0_TDO", + "SOUTH_GROUP0_CX_PRDY_N", + "SOUTH_GROUP0_CX_PREQ_N", + "SOUTH_GROUP0_CTBTRIGINOUT", + "SOUTH_GROUP0_CTBTRIGOUT", + "SOUTH_GROUP0_DFX_SPARE2", + "SOUTH_GROUP0_DFX_SPARE3", + "SOUTH_GROUP0_DFX_SPARE4", +}; + +static const char *const denverton_group_south_group1_names[] = { + "SOUTH_GROUP1_SUSPWRDNACK", + "SOUTH_GROUP1_PMU_SUSCLK", + "SOUTH_GROUP1_ADR_TRIGGER", + "SOUTH_GROUP1_PMU_SLP_S45_N", + "SOUTH_GROUP1_PMU_SLP_S3_N", + "SOUTH_GROUP1_PMU_WAKE_N", + "SOUTH_GROUP1_PMU_PWRBTN_N", + "SOUTH_GROUP1_PMU_RESETBUTTON_N", + "SOUTH_GROUP1_PMU_PLTRST_N", + "SOUTH_GROUP1_SUS_STAT_N", + "SOUTH_GROUP1_SLP_S0IX_N", + "SOUTH_GROUP1_SPI_CS0_N", + "SOUTH_GROUP1_SPI_CS1_N", + "SOUTH_GROUP1_SPI_MOSI_IO0", + "SOUTH_GROUP1_SPI_MISO_IO1", + "SOUTH_GROUP1_SPI_IO2", + "SOUTH_GROUP1_SPI_IO3", + "SOUTH_GROUP1_SPI_CLK", + "SOUTH_GROUP1_SPI_CLK_LOOPBK", + "SOUTH_GROUP1_ESPI_IO0", + "SOUTH_GROUP1_ESPI_IO1", + "SOUTH_GROUP1_ESPI_IO2", + "SOUTH_GROUP1_ESPI_IO3", + "SOUTH_GROUP1_ESPI_CS0_N", + "SOUTH_GROUP1_ESPI_CLK", + "SOUTH_GROUP1_ESPI_RST_N", + "SOUTH_GROUP1_ESPI_ALRT0_N", + "SOUTH_GROUP1_GPIO_10", + "SOUTH_GROUP1_GPIO_11", + "SOUTH_GROUP1_ESPI_CLK_LOOPBK", + "SOUTH_GROUP1_EMMC_CMD", + "SOUTH_GROUP1_EMMC_STROBE", + "SOUTH_GROUP1_EMMC_CLK", + "SOUTH_GROUP1_EMMC_D0", + "SOUTH_GROUP1_EMMC_D1", + "SOUTH_GROUP1_EMMC_D2", + "SOUTH_GROUP1_EMMC_D3", + "SOUTH_GROUP1_EMMC_D4", + "SOUTH_GROUP1_EMMC_D5", + "SOUTH_GROUP1_EMMC_D6", + "SOUTH_GROUP1_EMMC_D7", + "SOUTH_GROUP1_GPIO_3", +}; + + +static const struct gpio_group denverton_group_north_all = { + .display = "------- GPIO Group North All -------", + .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, + .func_count = 1, + .pad_names = denverton_group_north_all_names, +}; + +static const struct gpio_group *const denverton_community_north_groups[] = { + &denverton_group_north_all, +}; + +static const struct gpio_community denverton_community_north = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xc2, + .group_count = ARRAY_SIZE(denverton_community_north_groups), + .groups = denverton_community_north_groups, +}; + +static const struct gpio_group denverton_group_south_dfx = { + .display = "------- GPIO Group South DFX -------", + .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_dfx_names, +}; + +static const struct gpio_group denverton_group_south_group0 = { + .display = "------- GPIO Group South Group0 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group0_names, +}; + +static const struct gpio_group denverton_group_south_group1 = { + .display = "------- GPIO Group South Group1 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group1_names, +}; + +static const struct gpio_group *const denverton_community_south_groups[] = { + &denverton_group_south_dfx, + &denverton_group_south_group0, + &denverton_group_south_group1, +}; + +static const struct gpio_community denverton_community_south = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(denverton_community_south_groups), + .groups = denverton_community_south_groups, +}; + +static const struct gpio_community *const denverton_communities[] = { + &denverton_community_north, &denverton_community_south, +}; + +#endif From e32ded82f051ded75e0589b15c3e31db56ff8aea Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Wed, 29 Jan 2020 10:08:17 +0100 Subject: [PATCH 0470/1463] util/inteltool: Split GPIO community switch-case into its own function So far printing the GPIO groups chose the community definition. As the list of supported platforms grows the massive switch case gets repetetive and hinders the readers view. It also reduces the ability to reuse the code in a potential libinteltool. To takle these issues the detection logic was split into its own function. Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38631 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/inteltool/gpio_groups.c | 70 ++++++++++++++++++------------------ util/inteltool/inteltool.h | 3 ++ 2 files changed, 38 insertions(+), 35 deletions(-) diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 8b60c2b5b6..3d7d708d0c 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -96,11 +96,11 @@ static void print_gpio_community(const struct gpio_community *const community, } } -void print_gpio_groups(struct pci_dev *const sb) +const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb, + size_t* community_count, + size_t* pad_stepping) { - size_t community_count; - const struct gpio_community *const *communities; - size_t pad_stepping = 8; + *pad_stepping = 8; switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_H110: @@ -114,10 +114,8 @@ void print_gpio_groups(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: - community_count = ARRAY_SIZE(sunrise_communities); - communities = sunrise_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(sunrise_communities); + return sunrise_communities; case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: @@ -128,10 +126,8 @@ void print_gpio_groups(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: - community_count = ARRAY_SIZE(sunrise_lp_communities); - communities = sunrise_lp_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(sunrise_lp_communities); + return sunrise_lp_communities; case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C624: @@ -145,20 +141,14 @@ void print_gpio_groups(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_C621_SUPER: case PCI_DEVICE_ID_INTEL_C627_SUPER_2: case PCI_DEVICE_ID_INTEL_C628_SUPER: - community_count = ARRAY_SIZE(lewisburg_communities); - communities = lewisburg_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(lewisburg_communities); + return lewisburg_communities; case PCI_DEVICE_ID_INTEL_DNV_LPC: - community_count = ARRAY_SIZE(denverton_communities); - communities = denverton_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(denverton_communities); + return denverton_communities; case PCI_DEVICE_ID_INTEL_APL_LPC: - community_count = ARRAY_SIZE(apl_communities); - communities = apl_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(apl_communities); + return apl_communities; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: @@ -169,20 +159,30 @@ void print_gpio_groups(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: - community_count = ARRAY_SIZE(cannonlake_pch_h_communities); - communities = cannonlake_pch_h_communities; - pad_stepping = 16; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(cannonlake_pch_h_communities); + *pad_stepping = 16; + return cannonlake_pch_h_communities; case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: - community_count = ARRAY_SIZE(icelake_pch_h_communities); - communities = icelake_pch_h_communities; - pad_stepping = 16; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(icelake_pch_h_communities); + *pad_stepping = 16; + return icelake_pch_h_communities; default: - return; + return NULL; } +} + +void print_gpio_groups(struct pci_dev *const sb) +{ + size_t community_count; + const struct gpio_community *const *communities; + size_t pad_stepping; + + communities = get_gpio_communities(sb, &community_count, &pad_stepping); + + if (!communities) + return; + + pcr_init(sb); printf("\n============= GPIOS =============\n\n"); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 950943f234..49af276107 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -395,6 +395,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); +const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb, + size_t* community_count, + size_t* pad_stepping); void print_gpio_groups(struct pci_dev *sb); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); From 3c78445ad938ee1241f570b9fb1560e66f3e6438 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 11 Jun 2019 23:23:46 -0500 Subject: [PATCH 0471/1463] inteltool: add support for CannonPoint-LP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for CannonPoint-LP U Premium (CoffeeLake-U and WhiskeyLake-U) GPIO info taken from: - Intel doc #337867-002 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs.h Test: Read GPIOs from out-of-tree WhiskeyLake-U board Signed-off-by: Matt DeVillier Change-Id: I70f23eec71abb8d7c2a7a109c9e760bb31dee2ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/39393 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/inteltool/gpio.c | 1 + util/inteltool/gpio_groups.c | 5 + util/inteltool/gpio_names/cannonlake_lp.h | 341 ++++++++++++++++++++++ util/inteltool/inteltool.c | 6 + util/inteltool/inteltool.h | 3 + util/inteltool/memory.c | 2 + util/inteltool/pcie.c | 6 + util/inteltool/pcr.c | 1 + util/inteltool/powermgt.c | 1 + 9 files changed, 366 insertions(+) create mode 100644 util/inteltool/gpio_names/cannonlake_lp.h diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 55c32baf43..01b187f731 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1047,6 +1047,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C624: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 3d7d708d0c..bb196a914e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -25,6 +25,7 @@ #include "gpio_names/apollolake.h" #include "gpio_names/cannonlake.h" +#include "gpio_names/cannonlake_lp.h" #include "gpio_names/denverton.h" #include "gpio_names/icelake.h" #include "gpio_names/lewisburg.h" @@ -149,6 +150,10 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s case PCI_DEVICE_ID_INTEL_APL_LPC: *community_count = ARRAY_SIZE(apl_communities); return apl_communities; + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: + *community_count = ARRAY_SIZE(cannonlake_pch_lp_communities); + *pad_stepping = 16; + return cannonlake_pch_lp_communities; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h new file mode 100644 index 0000000000..0aa69b0101 --- /dev/null +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -0,0 +1,341 @@ +#ifndef GPIO_NAMES_CANNONLAKE_LP +#define GPIO_NAMES_CANNONLAKE_LP + +#include "gpio_groups.h" + +const char *const cannonlake_pch_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", + "GPP_A1", "LAD0", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "GPIO_RSVD_0", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_a_names, +}; + +const char *const cannonlake_pch_lp_group_b_names[] = { + "GPP_B0", "Reserved", "n/a", + "GPP_B1", "Reserved", "n/a", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GPIO_RSVD_1", "n/a", "n/a", + "GPIO_RSVD_2", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_b_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_b_names, +}; + +const char *const cannonlake_pch_lp_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", + "GPP_C1", "SMBDATA", "n/a", + "GPP_C2", "SMBALERT#", "n/a", + "GPP_C3", "SML0CLK", "n/a", + "GPP_C4", "SML0DATA", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", + "GPP_C6", "SML1CLK", "n/a", + "GPP_C7", "SML1DATA", "n/a", + "GPP_C8", "UART0_RXD", "n/a", + "GPP_C9", "UART0_TXD", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", + "GPP_C16", "I2C0_SDA", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", + "GPP_C20", "UART2_RXD", "n/a", + "GPP_C21", "UART2_TXD", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_c_names, +}; + +const char *const cannonlake_pch_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "BK0", "SBK0", + "GPP_D1", "SPI1_CLK", "BK1", "SBK1", + "GPP_D2", "SPI1_MISO", "BK2", "SBK2", + "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", + "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", + "GPIO_RSVD_12", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_d_names, +}; + +const char *const cannonlake_pch_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "n/a", "n/a", + "GPP_E2", "SATAXPCIE2", "n/a", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "DISP_MISC0", "n/a", + "GPP_E14", "DDPC_HPD1", "DISP_MISC1", "n/a", + "GPP_E15", "DDPD_HPD2", "DISP_MISC2", "n/a", + "GPP_E16", "n/a", "DISP_MISC3", "n/a", + "GPP_E17", "EDP_HPD", "DISP_MISC4", "n/a", + "GPP_E18", "DPPB_CTRLCLK", "n/a", "CNV_BT_HOST_WAKE#", + "GPP_E19", "DPPB_CTRLDATA", "n/a", "CNV_BT_IF_SELECT", + "GPP_E20", "DPPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DPPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "DPPD_CTRLCLK", "n/a", "n/a", + "GPP_E23", "DPPD_CTRLDATA", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_e_names, +}; + +const char *const cannonlake_pch_lp_group_f_names[] = { + "GPP_F0", "CNV_PA_BLANKING", "n/a", + "GPP_F1", "n/a", "n/a", + "GPP_F2", "n/a", "n/a", + "GPP_F3", "n/a", "n/a", + "GPP_F4", "CNV_BRI_DT", "UART0_RTS#", + "GPP_F5", "CNV_BRI_RSP", "UART0_RXD", + "GPP_F6", "CNV_RGI_DT", "UART0_TXD", + "GPP_F7", "CNV_RGI_RSP", "UART0_CTS#", + "GPP_F8", "CNV_MFUART2_RXD", "n/a", + "GPP_F9", "CNV_MFUART2_TXD", "n/a", + "GPP_F10", "n/a", "n/a", + "GPP_F11", "EMMC_CMD", "n/a", + "GPP_F12", "EMMC_DATA0", "n/a", + "GPP_F13", "EMMC_DATA1", "n/a", + "GPP_F14", "EMMC_DATA2", "n/a", + "GPP_F15", "EMMC_DATA3", "n/a", + "GPP_F16", "EMMC_DATA4", "n/a", + "GPP_F17", "EMMC_DATA5", "n/a", + "GPP_F18", "EMMC_DATA6", "n/a", + "GPP_F19", "EMMC_DATA7", "n/a", + "GPP_F20", "EMMC_RCLK", "n/a", + "GPP_F21", "EMMC_CLK", "n/a", + "GPP_F22", "EMMC_RESET#", "n/a", + "GPP_F23", "A4WP_PRESENT", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_f_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_f_names, +}; + +const char *const cannonlake_pch_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", + "GPP_G1", "SD_DATA0", + "GPP_G2", "SD_DATA1", + "GPP_G3", "SD_DATA2", + "GPP_G4", "SD_DATA3", + "GPP_G5", "SD3_CD#", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +const struct gpio_group cannonlake_pch_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_g_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_g_names, +}; + +const char *const cannonlake_pch_lp_group_h_names[] = { + "GPP_H0", "I2S2_SCLK", "CNV_BT_I2S_SCLK", "n/a", + "GPP_H1", "I2S2_SFRM", "CNV_BT_I2S_BCLK", "CNV_RF_RESET#", + "GPP_H2", "I2S2_TXD", "CNV_BT_I2S_SDI", "MODEM_CLKREQ", + "GPP_H3", "I2S2_RXD", "CNV_BT_I2S_SDO", "n/a", + "GPP_H4", "I2C2_SDA", "n/a", "n/a", + "GPP_H5", "I2C2_SCL", "n/a", "n/a", + "GPP_H6", "I2C3_SDA", "n/a", "n/a", + "GPP_H7", "I2C3_SCL", "n/a", "n/a", + "GPP_H8", "I2C4_SDA", "n/a", "n/a", + "GPP_H9", "I2C4_SCL", "n/a", "n/a", + "GPP_H10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_H11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_H12", "M2_SKT2_CFG0", "n/a", "n/a", + "GPP_H13", "M2_SKT2_CFG1", "n/a", "n/a", + "GPP_H14", "M2_SKT2_CFG2", "n/a", "n/a", + "GPP_H15", "M2_SKT2_CFG3", "n/a", "n/a", + "GPP_H16", "n/a", "n/a", "n/a", + "GPP_H17", "n/a", "n/a", "n/a", + "GPP_H18", "CPU_C10_GATE#", "n/a", "n/a", + "GPP_H19", "TIME_SYNC0", "n/a", "n/a", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", + "GPP_H21", "n/a", "n/a", "n/a", + "GPP_H22", "n/a", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_h_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_h_names, +}; + +const char *const cannonlake_pch_lp_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PRWBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", +}; +const struct gpio_group cannonlake_pch_lp_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_gpd_names, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = { + &cannonlake_pch_lp_group_a, + &cannonlake_pch_lp_group_b, + &cannonlake_pch_lp_group_g, +}; +const struct gpio_community cannonlake_pch_lp_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_0_groups), + .groups = cannonlake_pch_lp_community_0_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_1_groups[] = { + &cannonlake_pch_lp_group_d, + &cannonlake_pch_lp_group_f, + &cannonlake_pch_lp_group_h, +}; +const struct gpio_community cannonlake_pch_lp_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_1_groups), + .groups = cannonlake_pch_lp_community_1_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_2_groups[] = { + &cannonlake_pch_lp_group_gpd, +}; + +const struct gpio_community cannonlake_pch_lp_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_2_groups), + .groups = cannonlake_pch_lp_community_2_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = { + &cannonlake_pch_lp_group_c, + &cannonlake_pch_lp_group_e, +}; + +const struct gpio_community cannonlake_pch_lp_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_4_groups), + .groups = cannonlake_pch_lp_community_4_groups, +}; + +const struct gpio_community *const cannonlake_pch_lp_communities[] = { + &cannonlake_pch_lp_community_0, + &cannonlake_pch_lp_community_1, + &cannonlake_pch_lp_community_2, + &cannonlake_pch_lp_community_4, +}; + +#endif diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index d51767c9fa..0e84b550fc 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -143,6 +143,10 @@ static const struct { "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1, + "8th generation (Coffee Lake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2, + "8th generation (Whiskey Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U, "10th generation (Icelake family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ @@ -258,6 +262,8 @@ static const struct { "Sunrise Point-LP U iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM, "Sunrise Point-LP Y iHDCP 2.2 Premium/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM, + "Cannon Point-LP U Premium/CoffeeLake/Whiskeylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 49af276107..2bd2afcb40 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -156,6 +156,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b +#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 #define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_Z170 0xa145 @@ -294,6 +295,8 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index e7523f3501..22de2a9f9d 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -227,6 +227,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index b7c72cb140..9b13087c5d 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -272,6 +272,8 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -399,6 +401,8 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: dmi_registers = skylake_dmi_registers; size = ARRAY_SIZE(skylake_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -510,6 +514,8 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: + case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index f4bf87bfb2..8131fdd6a7 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -132,6 +132,7 @@ void pcr_init(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: sbbar_phys = 0xfd000000; use_p2sb = false; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 54a3045b84..3f489b88fa 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -837,6 +837,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 2); if (!acpi) { printf("PMC device not found.\n"); From 8676c268a033f997e4859fd7608d281f00937c8a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 21:15:55 +0100 Subject: [PATCH 0472/1463] util/inteltool: ahci: rework AHCI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rework AHCI to align the code with the rest of inteltool. Change-Id: I37116f8e269d0376e147dd6de7365c45ac90bda0 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39504 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- util/inteltool/ahci.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 22a5b011ed..09f6427ee4 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -59,7 +59,7 @@ static void print_port(const uint8_t *const mmio, size_t port) int print_ahci(struct pci_dev *ahci) { - size_t mmio_size, i; + size_t ahci_registers_size = 0, i; if (!ahci) { puts("No SATA device found"); @@ -67,15 +67,19 @@ int print_ahci(struct pci_dev *ahci) } printf("\n============= AHCI Registers ==============\n\n"); - if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA || - ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA) - mmio_size = 0x800; - else - mmio_size = 0x400; + switch (ahci->device_id) { + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA: + ahci_registers_size = 0x800; + break; + default: + ahci_registers_size = 0x400; + } - const pciaddr_t mmio_phys = ahci->base_addr[5] & ~0x7ULL; - printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)mmio_phys); - const uint8_t *const mmio = map_physical(mmio_phys, mmio_size); + const pciaddr_t ahci_phys = ahci->base_addr[5] & ~0x7ULL; + printf("\n============= ABAR ==============\n\n"); + printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)ahci_phys); + const uint8_t *const mmio = map_physical(ahci_phys, ahci_registers_size); if (mmio == NULL) { perror("Error mapping MMIO"); exit(1); @@ -91,21 +95,18 @@ int print_ahci(struct pci_dev *ahci) } } - const size_t max_ports = (mmio_size - 0x100) / 0x80; + const size_t max_ports = (ahci_registers_size - 0x100) / 0x80; for (i = 0; i < max_ports; i++) { if (MMIO(0x0c) & 1 << i) print_port(mmio, i); } - if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA || - ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA) { - puts("\nOther registers:"); - for (i = 0x500; i < mmio_size; i += 4) { - if (MMIO(i)) - printf("0x%03zx: 0x%08x\n", i, MMIO(i)); - } + puts("\nOther registers:"); + for (i = 0x500; i < ahci_registers_size; i += 4) { + if (MMIO(i)) + printf("0x%03zx: 0x%08x\n", i, MMIO(i)); } - unmap_physical((void *)mmio, mmio_size); + unmap_physical((void *)mmio, ahci_registers_size); return 0; } From e6cff0d8304b650f0371938fdb9f545032c8ce16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 21:17:21 +0100 Subject: [PATCH 0473/1463] util/inteltool: ahci: add code for dumping config and SIR registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the code required to dump config and SIR registers. Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- util/inteltool/ahci.c | 54 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 09f6427ee4..3a18993e01 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -60,6 +60,11 @@ static void print_port(const uint8_t *const mmio, size_t port) int print_ahci(struct pci_dev *ahci) { size_t ahci_registers_size = 0, i; + size_t ahci_cfg_registers_size = 0; + const io_register_t *ahci_cfg_registers; + size_t ahci_sir_offset = 0; + size_t ahci_sir_registers_size = 0; + const io_register_t *ahci_sir_registers; if (!ahci) { puts("No SATA device found"); @@ -76,6 +81,55 @@ int print_ahci(struct pci_dev *ahci) ahci_registers_size = 0x400; } + printf("\n============= AHCI Configuration Registers ==============\n\n"); + for (i = 0; i < ahci_cfg_registers_size; i++) { + switch (ahci_cfg_registers[i].size) { + case 4: + printf("0x%04x: 0x%08x (%s)\n", + ahci_cfg_registers[i].addr, + pci_read_long(ahci, ahci_cfg_registers[i].addr), + ahci_cfg_registers[i].name); + break; + case 2: + printf("0x%04x: 0x%04x (%s)\n", + ahci_cfg_registers[i].addr, + pci_read_word(ahci, ahci_cfg_registers[i].addr), + ahci_cfg_registers[i].name); + break; + case 1: + printf("0x%04x: 0x%02x (%s)\n", + ahci_cfg_registers[i].addr, + pci_read_byte(ahci, ahci_cfg_registers[i].addr), + ahci_cfg_registers[i].name); + break; + } + } + + printf("\n============= SATA Initialization Registers ==============\n\n"); + for (i = 0; i < ahci_sir_registers_size; i++) { + pci_write_byte(ahci, ahci_sir_offset, ahci_sir_registers[i].addr); + switch (ahci_sir_registers[i].size) { + case 4: + printf("0x%02x: 0x%08x (%s)\n", + ahci_sir_registers[i].addr, + pci_read_long(ahci, ahci_sir_offset), + ahci_sir_registers[i].name); + break; + case 2: + printf("0x%02x: 0x%04x (%s)\n", + ahci_sir_registers[i].addr, + pci_read_word(ahci, ahci_sir_offset), + ahci_sir_registers[i].name); + break; + case 1: + printf("0x%02x: 0x%02x (%s)\n", + ahci_sir_registers[i].addr, + pci_read_byte(ahci, ahci_sir_offset), + ahci_sir_registers[i].name); + break; + } + } + const pciaddr_t ahci_phys = ahci->base_addr[5] & ~0x7ULL; printf("\n============= ABAR ==============\n\n"); printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)ahci_phys); From fe8170f909dc682e529c8fe8d9dadf3b13acdef6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 21:18:04 +0100 Subject: [PATCH 0474/1463] util/inteltool: ahci: add Sunrise Point config and SIR registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the Sunrise Point AHCI config and SIR registers from doc#332691-003EN. Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39506 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- util/inteltool/ahci.c | 52 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 3a18993e01..90a1617f8f 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -34,6 +34,53 @@ static const char *port_ctl_regs[] = { "PxFBS", "PxDEVSLP", "Reserved" }; +static const io_register_t sunrise_ahci_cfg_registers[] = { + {0x0, 4, "ID"}, + {0x4, 2, "CMD"}, + {0x6, 2, "STS"}, + {0x8, 1, "RID"}, + {0x9, 1, "PI"}, + {0xa, 2, "CC"}, + {0xc, 1, "CLS"}, + {0xd, 1, "MLT"}, + {0xe, 1, "HTYPE"}, + {0x10, 4, "MXTBA"}, + {0x14, 4, "MXPBA"}, + {0x20, 4, "AIDPBA"}, + {0x24, 4, "ABAR"}, + {0x2c, 4, "SS"}, + {0x34, 1, "CAP"}, + {0x3c, 2, "INTR"}, + {0x70, 2, "PID"}, + {0x72, 2, "PC"}, + {0x74, 2, "PMCS"}, + {0x80, 2, "MID"}, + {0x82, 2, "MC"}, + {0x84, 4, "MA"}, + {0x88, 2, "MD"}, + {0x90, 4, "MAP"}, + {0x94, 4, "PCS"}, + {0x9c, 4, "SATAGC"}, + {0xa0, 1, "SIRI"}, + {0xa4, 4, "SIRD"}, + {0xa8, 4, "SATACR0"}, + {0xac, 4, "SATACR1"}, + {0xc0, 4, "SP"}, + {0xd0, 2, "MXID"}, + {0xd2, 2, "MXC"}, + {0xd4, 4, "MXT"}, + {0xd8, 4, "MXP"}, + {0xe0, 4, "BFCS"}, + {0xe4, 4, "BFTD1"}, + {0xe8, 4, "BFTD2"}, +}; + +static const io_register_t sunrise_ahci_sir_registers[] = { + {0x80, 4, "SQUELCH"}, + {0x90, 4, "SATA_MPHY_PG"}, + {0xa4, 4, "OOBRETR"}, +}; + #define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0])) #define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0])) @@ -76,6 +123,11 @@ int print_ahci(struct pci_dev *ahci) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA: ahci_registers_size = 0x800; + ahci_sir_offset = 0xa0; + ahci_cfg_registers = sunrise_ahci_cfg_registers; + ahci_cfg_registers_size = ARRAY_SIZE(sunrise_ahci_cfg_registers); + ahci_sir_registers = sunrise_ahci_sir_registers; + ahci_sir_registers_size = ARRAY_SIZE(sunrise_ahci_sir_registers); break; default: ahci_registers_size = 0x400; From 9952e72d066b3d25355ccf43b396ab0ad5b98a78 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 22:22:26 +0100 Subject: [PATCH 0475/1463] util/inteltool: add code for dumping LPC registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the implementation for dumping LPC registers Change-Id: I50ae4913933f7594f0d63ce3f752302ed5c461e2 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39517 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- util/inteltool/Makefile | 2 +- util/inteltool/inteltool.c | 16 +++- util/inteltool/inteltool.h | 1 + util/inteltool/lpc.c | 163 +++++++++++++++++++++++++++++++++++++ 4 files changed, 179 insertions(+), 3 deletions(-) create mode 100644 util/inteltool/lpc.c diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 23ea8a6ee6..b15ae8ec54 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -29,7 +29,7 @@ CPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o lpc.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 0e84b550fc..8d5d9942a7 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -494,7 +494,7 @@ static void print_version(void) static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrplmedPMaAsfSRx]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -505,6 +505,7 @@ static void print_usage(const char *name) " -G | --gpio-diffs: show GPIO differences from defaults\n" " -r | --rcba: dump southbridge RCBA registers\n" " -p | --pmbase: dump southbridge Power Management registers\n\n" + " -l | --lpc: dump southbridge LPC/eSPI Interface registers\n\n" " -m | --mchbar: dump northbridge Memory Controller registers\n" " -S FILE | --spd=FILE: create a file storing current timings (implies -m)\n" " -e | --epbar: dump northbridge EPBAR registers\n" @@ -574,6 +575,7 @@ int main(int argc, char *argv[]) int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0; + int dump_lpc = 0; int show_gpio_diffs = 0; size_t pcr_count = 0; uint8_t dump_pcr[MAX_PCR_PORTS]; @@ -586,6 +588,7 @@ int main(int argc, char *argv[]) {"mchbar", 0, 0, 'm'}, {"rcba", 0, 0, 'r'}, {"pmbase", 0, 0, 'p'}, + {"lpc", 0, 0, 'l'}, {"epbar", 0, 0, 'e'}, {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, @@ -601,7 +604,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrplmedPMaAsfRS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -633,6 +636,9 @@ int main(int argc, char *argv[]) case 'p': dump_pmbase = 1; break; + case 'l': + dump_lpc = 1; + break; case 'e': dump_epbar = 1; break; @@ -651,6 +657,7 @@ int main(int argc, char *argv[]) dump_mchbar = 1; dump_rcba = 1; dump_pmbase = 1; + dump_lpc = 1; dump_epbar = 1; dump_dmibar = 1; dump_pciexbar = 1; @@ -816,6 +823,11 @@ int main(int argc, char *argv[]) printf("\n\n"); } + if (dump_lpc) { + print_lpc(sb, pacc); + printf("\n\n"); + } + if (dump_mchbar) { print_mchbar(nb, pacc, dump_spd_file); printf("\n\n"); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 2bd2afcb40..85f29fd8f9 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -396,6 +396,7 @@ unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file); int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); +int print_lpc(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb, diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c new file mode 100644 index 0000000000..247c37acb9 --- /dev/null +++ b/util/inteltool/lpc.c @@ -0,0 +1,163 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2008-2010 by coresystems GmbH + * written by Stefan Reinauer + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2020 Michael Niewöhner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "inteltool.h" + +#define SUNRISE_LPC_BC 0xdc + +static const io_register_t sunrise_lpc_cfg_registers[] = { + {0x00, 4, "ID"}, + {0x04, 2, "CMD"}, + {0x06, 2, "STS"}, + {0x08, 1, "RID"}, + {0x09, 1, "CC[3]"}, + {0x0A, 1, "CC[2]"}, + {0x0B, 1, "CC[1]"}, + {0x0C, 1, "CC[0]"}, + {0x0E, 1, "HTYPE"}, + {0x2C, 4, "SS"}, + {0x34, 1, "CAPP"}, + {0x64, 1, "SCNT"}, + {0x80, 2, "IOD"}, + {0x82, 2, "IOE"}, + {0x84, 4, "LGIR1"}, + {0x88, 4, "LGIR2"}, + {0x8C, 4, "LGIR3"}, + {0x90, 4, "LGIR4"}, + {0x94, 4, "ULKMC"}, + {0x98, 4, "LGMR"}, + {0xD0, 2, "FS1"}, + {0xD4, 2, "FS2"}, + {0xD8, 2, "BDE"}, + {0xDC, 1, "BC"}, + {0xE0, 4, "PCCTL"}, +}; + +static const io_register_t sunrise_espi_cfg_registers[] = { + {0x00, 4, "ESPI_DID_VID"}, + {0x04, 4, "ESPI_STS_CMD"}, + {0x08, 4, "ESPI_CC_RID"}, + {0x0C, 4, "ESPI_BIST_HTYPE_PLT_CLS"}, + {0x2C, 4, "ESPI_SS"}, + {0x34, 4, "ESPI_CAPP"}, + {0x80, 4, "ESPI_IOD_IOE"}, + {0x84, 4, "ESPI_LGIR1"}, + {0x88, 4, "ESPI_LGIR2"}, + {0x8C, 4, "ESPI_LGIR3"}, + {0x90, 4, "ESPI_LGIR4"}, + {0x94, 4, "ESPI_ULKMC"}, + {0x98, 4, "ESPI_LGMR"}, + {0xD0, 4, "ESPI_FS1"}, + {0xD4, 4, "ESPI_FS2"}, + {0xD8, 4, "ESPI_BDE"}, + {0xDC, 4, "ESPI_BC"}, +}; + +int print_lpc(struct pci_dev *sb, struct pci_access *pacc) +{ + size_t i, cfg_registers_size = 0; + const io_register_t *cfg_registers; + struct pci_dev *dev = NULL; + uint32_t bc; + + printf("\n========== LPC/eSPI =========\n\n"); + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: + case PCI_DEVICE_ID_INTEL_B150: + case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_HM175: + case PCI_DEVICE_ID_INTEL_QM175: + case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); + if (!dev) { + printf("LPC/eSPI interface not found.\n"); + return 1; + } + bc = pci_read_long(dev, SUNRISE_LPC_BC); + if (bc & (1 << 2)) { + printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n"); + cfg_registers = sunrise_espi_cfg_registers; + cfg_registers_size = ARRAY_SIZE(sunrise_espi_cfg_registers); + + } else { + printf("Device 0:1f.0 is LPC (BC.LPC_ESPI=0)\n\n"); + cfg_registers = sunrise_lpc_cfg_registers; + cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers); + } + break; + + default: + printf("Error: Dumping LPC/eSPI on this southbridge is not (yet) supported.\n"); + return 1; + } + + for (i = 0; i < cfg_registers_size; i++) { + switch (cfg_registers[i].size) { + case 4: + printf("0x%04x: 0x%08x (%s)\n", + cfg_registers[i].addr, + pci_read_long(dev, cfg_registers[i].addr), + cfg_registers[i].name); + break; + case 2: + printf("0x%04x: 0x%04x (%s)\n", + cfg_registers[i].addr, + pci_read_word(dev, cfg_registers[i].addr), + cfg_registers[i].name); + break; + case 1: + printf("0x%04x: 0x%02x (%s)\n", + cfg_registers[i].addr, + pci_read_byte(dev, cfg_registers[i].addr), + cfg_registers[i].name); + break; + default: + printf("Error: register size %d not implemented.\n", + cfg_registers[i].size); + break; + } + } + + if (dev) + pci_free_dev(dev); + + return 0; +} From d3dab12244f7d0a704b6e245204e4ca52aaf699a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 18:58:44 +0100 Subject: [PATCH 0476/1463] util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a bunch of missing chipsets to print_bioscntl. Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39563 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- util/inteltool/spi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index e8289acaf3..ca29fcc099 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -175,6 +175,20 @@ static int print_bioscntl(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: + case PCI_DEVICE_ID_INTEL_B150: + case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_HM175: + case PCI_DEVICE_ID_INTEL_QM175: + case PCI_DEVICE_ID_INTEL_CM238: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: From 672f7d7b2d7adbd7e2d041d627d96a33de9b8b11 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Sun, 15 Mar 2020 23:25:37 -0600 Subject: [PATCH 0477/1463] mb/google/dedede: Add waddledee variant Add initial support for waddledee variant board. BUG=b:151576904 TEST=Build the mainboard and variant board. Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/Kconfig | 2 + src/mainboard/google/dedede/Kconfig.name | 6 +++ .../dedede/variants/waddledee/Makefile.inc | 11 +++++ .../variants/waddledee/include/variant/ec.h | 14 +++++++ .../variants/waddledee/include/variant/gpio.h | 14 +++++++ .../dedede/variants/waddledee/overridetree.cb | 40 +++++++++++++++++++ 6 files changed, 87 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/waddledee/Makefile.inc create mode 100644 src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h create mode 100644 src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h create mode 100644 src/mainboard/google/dedede/variants/waddledee/overridetree.cb diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 36b42bf8b3..e2afc66a05 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -53,6 +53,7 @@ config MAINBOARD_PART_NUMBER string default "Dedede" if BOARD_GOOGLE_DEDEDE default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "Waddledee" if BOARD_GOOGLE_WADDLEDEE config MAX_CPUS int @@ -74,5 +75,6 @@ config VARIANT_DIR string default "dedede" if BOARD_GOOGLE_DEDEDE default "waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "waddledee" if BOARD_GOOGLE_WADDLEDEE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index ae5df66df5..d083d2dd8a 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -9,3 +9,9 @@ config BOARD_GOOGLE_WADDLEDOO select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + +config BOARD_GOOGLE_WADDLEDEE + bool "Waddledee" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc new file mode 100644 index 0000000000..c55051b9fc --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -0,0 +1,11 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_SOURCES = empty #0b0000 +SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 +SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010 diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h new file mode 100644 index 0000000000..cc897dcdcf --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h new file mode 100644 index 0000000000..bf23f6e457 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb new file mode 100644 index 0000000000..23db34e66c --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -0,0 +1,40 @@ +chip soc/intel/tigerlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on end +end From 1429092d02e8157c8e6c26849e0c8aa096da9c0c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 11 Mar 2020 14:35:35 -0700 Subject: [PATCH 0478/1463] memrange: Enable memranges to support different alignments This change enables memranges library to support addresses with different alignments. Before this change, memranges library supported aligning addresses to 4KiB only. Though this works for most cases, it might not be the right alignment for every use case. Example: There are some resource allocator changes coming up that require a different alignment when handling the range list. This change adds a align parameter to struct memranges that determines the alignment of all range lists in that memrange. In order to continue supporting current users of memranges, default alignment is maintained as 4KiB. BUG=b:149186922 Signed-off-by: Furquan Shaikh Change-Id: I1da0743ff89da734c9a0972e3c56d9f512b3d1e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39483 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/include/memrange.h | 29 +++++++++++++++++++++++------ src/lib/memrange.c | 26 +++++++++++++++++--------- 2 files changed, 40 insertions(+), 15 deletions(-) diff --git a/src/include/memrange.h b/src/include/memrange.h index 7f42aa2b0b..0d20236d61 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -24,6 +24,8 @@ struct memranges { /* coreboot doesn't have a free() function. Therefore, keep a cache of * free'd entries. */ struct range_entry *free_list; + /* Alignment for base and end addresses of the range. (Must be power of 2). */ + size_t align; }; /* Each region within a memranges structure is represented by a @@ -86,17 +88,32 @@ static inline void range_entry_update_tag(struct range_entry *r, #define memranges_each_entry(r, ranges) \ for (r = (ranges)->entries; r != NULL; r = r->next) + /* Initialize memranges structure providing an optional array of range_entry - * to use as the free list. */ -void memranges_init_empty(struct memranges *ranges, struct range_entry *free, - size_t num_free); + * to use as the free list. Additionally, it accepts an align parameter that + * determines the alignment of addresses. (Alignment must be a power of 2). */ +void memranges_init_empty_with_alignment(struct memranges *ranges, + struct range_entry *free, + size_t num_free, size_t align); /* Initialize and fill a memranges structure according to the * mask and match type for all memory resources. Tag each entry with the - * specified type. */ -void memranges_init(struct memranges *ranges, + * specified type. Additionally, it accepts an align parameter that + * determines the alignment of addresses. (Alignment must be a power of 2). */ +void memranges_init_with_alignment(struct memranges *ranges, unsigned long mask, unsigned long match, - unsigned long tag); + unsigned long tag, size_t align); + +/* Initialize memranges structure providing an optional array of range_entry + * to use as the free list. Addresses are default aligned to 4KiB. */ +#define memranges_init_empty(__ranges, __free, __num_free) \ + memranges_init_empty_with_alignment(__ranges, __free, __num_free, 4 * KiB) + +/* Initialize and fill a memranges structure according to the + * mask and match type for all memory resources. Tag each entry with the + * specified type. Addresses are default aligned to 4KiB. */ +#define memranges_init(__ranges, __mask, __match, __tag) \ + memranges_init_with_alignment(__ranges, __mask, __match, __tag, 4 * KiB) /* Clone a memrange. The new memrange has the same entries as the old one. */ void memranges_clone(struct memranges *newranges, struct memranges *oldranges); diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 79a1b0ee49..21fff003a1 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -12,7 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include #include +#include #include #include @@ -231,9 +234,9 @@ static void do_action(struct memranges *ranges, /* The addresses are aligned to 4096 bytes: the begin address is * aligned down while the end address is aligned up to be conservative * about the full range covered. */ - begin = ALIGN_DOWN(base, 4096); + begin = ALIGN_DOWN(base, ranges->align); end = begin + size + (base - begin); - end = ALIGN_UP(end, 4096) - 1; + end = ALIGN_UP(end, ranges->align) - 1; action(ranges, begin, end, tag); } @@ -290,23 +293,28 @@ void memranges_add_resources(struct memranges *ranges, memranges_add_resources_filter(ranges, mask, match, tag, NULL); } -void memranges_init_empty(struct memranges *ranges, struct range_entry *to_free, - size_t num_free) +void memranges_init_empty_with_alignment(struct memranges *ranges, + struct range_entry *to_free, + size_t num_free, size_t align) { size_t i; + /* Alignment must be a power of 2. */ + assert(IS_POWER_OF_2(align)); + ranges->entries = NULL; ranges->free_list = NULL; + ranges->align = align; for (i = 0; i < num_free; i++) range_entry_link(&ranges->free_list, &to_free[i]); } -void memranges_init(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) +void memranges_init_with_alignment(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag, size_t align) { - memranges_init_empty(ranges, NULL, 0); + memranges_init_empty_with_alignment(ranges, NULL, 0, align); memranges_add_resources(ranges, mask, match, tag); } @@ -316,7 +324,7 @@ void memranges_clone(struct memranges *newranges, struct memranges *oldranges) struct range_entry *r, *cur; struct range_entry **prev_ptr; - memranges_init_empty(newranges, NULL, 0); + memranges_init_empty_with_alignment(newranges, NULL, 0, oldranges->align); prev_ptr = &newranges->entries; memranges_each_entry(r, oldranges) { From 9c6274cd8fb1c9ee0eb674ce5945a05f818cb32e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 11 Mar 2020 19:06:24 -0700 Subject: [PATCH 0479/1463] memrange: Add support for stealing required memory from given ranges This change adds memranges_steal() which allows the user to steal memory from the list of available ranges by providing a set of constraints (limit, size, alignment, tag). It tries to find the first big enough range that can satisfy the constraints, creates a hole as per the request and returns base of the stolen memory. BUG=b:149186922 Signed-off-by: Furquan Shaikh Change-Id: Ibe9cfae18fc6101ab2e7e27233e45324c8117708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39484 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/include/memrange.h | 15 ++++++++++++ src/lib/memrange.c | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h index 0d20236d61..f8fa033cee 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -16,6 +16,7 @@ #define MEMRANGE_H_ #include +#include /* A memranges structure consists of a list of range_entry(s). The structure * is exposed so that a memranges can be used on the stack if needed. */ @@ -166,4 +167,18 @@ void memranges_update_tag(struct memranges *ranges, unsigned long old_tag, /* Returns next entry after the provided entry. NULL if r is last. */ struct range_entry *memranges_next_entry(struct memranges *ranges, const struct range_entry *r); + +/* Steals memory from the available list in given ranges as per the constraints: + * limit = Upper bound for the memory range to steal. + * size = Requested size for the stolen memory. + * align = Alignment requirements for the starting address of the stolen memory. + * (Alignment must be a power of 2). + * tag = Use a range that matches the given tag. + * + * If the constraints can be satisfied, this function creates a hole in the memrange, + * writes the base address of that hole to stolen_base and returns true. Otherwise it returns + * false. */ +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, size_t align, + unsigned long tag, resource_t *stolen_base); + #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 21fff003a1..b9c09e8782 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -391,3 +391,58 @@ struct range_entry *memranges_next_entry(struct memranges *ranges, { return r->next; } + +/* Find a range entry that satisfies the given constraints to fit a hole that matches the + * required alignment, is big enough, does not exceed the limit and has a matching tag. */ +static const struct range_entry *memranges_find_entry(struct memranges *ranges, + resource_t limit, resource_t size, + size_t align, unsigned long tag) +{ + const struct range_entry *r; + resource_t base, end; + + if (size == 0) + return NULL; + + if (!IS_POWER_OF_2(align)) + return NULL; + + if (!IS_ALIGNED(align, ranges->align)) + return NULL; + + memranges_each_entry(r, ranges) { + + if (r->tag != tag) + continue; + + base = ALIGN_UP(r->begin, align); + end = base + size - 1; + + if (end > r->end) + continue; + + if (end > limit) + continue; + + return r; + } + + return NULL; +} + +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, size_t align, + unsigned long tag, resource_t *stolen_base) +{ + resource_t base; + const struct range_entry *r = memranges_find_entry(ranges, limit, size, align, tag); + + if (r == NULL) + return false; + + base = ALIGN_UP(r->begin, align); + + memranges_create_hole(ranges, base, size); + *stolen_base = base; + + return true; +} From 2190a632e0942455f572bb408077670e3280c4e5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 12 Mar 2020 16:43:49 -0700 Subject: [PATCH 0480/1463] memrange: Add a helper function to determine if memranges is empty This change adds a helper function memranges_is_empty() which returns true if there are no entries in memranges. BUG=b:149186922 Signed-off-by: Furquan Shaikh Change-Id: If841c42a9722cbc73ef321568928bc175bf88fd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39485 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/include/memrange.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h index f8fa033cee..ea3b118d41 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -81,6 +81,11 @@ static inline void range_entry_update_tag(struct range_entry *r, r->tag = new_tag; } +static inline bool memranges_is_empty(struct memranges *ranges) +{ + return ranges->entries == NULL; +} + /* Iterate over each entry in a memranges structure. Ranges cannot * be deleted while processing each entry as the list cannot be safely * traversed after such an operation. From 2d977b2dcbe83b2518c172de52014fe781135bd2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 14 Jan 2019 03:08:31 -0600 Subject: [PATCH 0481/1463] mb/purism: remove duplicate ACPI power button These platforms use the standard fixed function power button and do not need a second power button device declared or the kernel will end up with two devices reporting the same event. Same change was applied to all google mainboards in CB:27272 which contains more detail. Change-Id: I17c85e43493530d04f4fa13f33bec6d027cb3147 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39577 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_bdw/acpi/mainboard.asl | 12 ------------ src/mainboard/purism/librem_skl/acpi/mainboard.asl | 12 ------------ 2 files changed, 24 deletions(-) diff --git a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl index f0b2c1d046..0e4842d1d8 100644 --- a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl @@ -30,18 +30,6 @@ Scope (\_SB) } } - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - - Method (_STA) - { - Return (0xF) - } - - Name (_PRW, Package () { 27, 4 }) - } - Device (SLPB) { Name (_HID, EisaId ("PNP0C0E")) diff --git a/src/mainboard/purism/librem_skl/acpi/mainboard.asl b/src/mainboard/purism/librem_skl/acpi/mainboard.asl index f0b2c1d046..0e4842d1d8 100644 --- a/src/mainboard/purism/librem_skl/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_skl/acpi/mainboard.asl @@ -30,18 +30,6 @@ Scope (\_SB) } } - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - - Method (_STA) - { - Return (0xF) - } - - Name (_PRW, Package () { 27, 4 }) - } - Device (SLPB) { Name (_HID, EisaId ("PNP0C0E")) From 2974ec2cbf6df4ca09cb472eb7465f3846c28747 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 15 Mar 2020 16:12:58 -0500 Subject: [PATCH 0482/1463] soc/broadwell: remove unused function init_one_gpio() Function was copied as part of upstreaming from Chromium tree, but isn't used and has never been used best I can tell. Change-Id: I53b8702c97d7a694450aa05ba49da6c26c30f725 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/soc/intel/broadwell/gpio.c | 48 ---------------------- src/soc/intel/broadwell/include/soc/gpio.h | 1 - 2 files changed, 49 deletions(-) diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/gpio.c index 81ad9d4266..8975f5e913 100644 --- a/src/soc/intel/broadwell/gpio.c +++ b/src/soc/intel/broadwell/gpio.c @@ -49,54 +49,6 @@ static int gpio_to_pirq(int gpio) }; } -void init_one_gpio(int gpio_num, struct gpio_config *config) -{ - u32 owner, route, irqen, reset; - int set, bit; - - if (gpio_num > MAX_GPIO_NUMBER || !config) - return; - - outl(config->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); - outl(config->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio_num)); - - /* Determine set and bit based on GPIO number */ - set = gpio_num >> 5; - bit = gpio_num % 32; - - /* Save settings from current GPIO config */ - owner = inl(GPIO_BASE_ADDRESS + GPIO_OWNER(set)); - route = inl(GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); - irqen = inl(GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); - reset = inl(GPIO_BASE_ADDRESS + GPIO_RESET(set)); - - owner |= config->owner << bit; - route |= config->route << bit; - irqen |= config->irqen << bit; - reset |= config->reset << bit; - - outl(owner, GPIO_BASE_ADDRESS + GPIO_OWNER(set)); - outl(route, GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); - outl(irqen, GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); - outl(reset, GPIO_BASE_ADDRESS + GPIO_RESET(set)); - - if (set == 0) { - u32 blink = inl(GPIO_BASE_ADDRESS + GPIO_BLINK); - blink |= config->blink << bit; - outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK); - } - - /* PIRQ to IO-APIC map */ - if (config->pirq == GPIO_PIRQ_APIC_ROUTE) { - u32 pirq2apic = inl(GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); - set = gpio_to_pirq(gpio_num); - if (set >= 0) { - pirq2apic |= 1 << set; - outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); - } - } -} - void init_gpios(const struct gpio_config config[]) { const struct gpio_config *entry; diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index c0ac13497b..3c7f08ad97 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -175,7 +175,6 @@ struct gpio_config { } __packed; /* Configure GPIOs with mainboard provided settings */ -void init_one_gpio(int gpio_num, struct gpio_config *config); void init_gpios(const struct gpio_config config[]); /* Get GPIO pin value */ From bfb0f755b9fa0bf25b4575b39db348121431f325 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Tue, 10 Mar 2020 18:49:54 +0800 Subject: [PATCH 0483/1463] mb/google/octopus: Add custom SAR values for Foob360 Foob360 would prefer to use different SAR values. Since Foob360 sku id is 9. BUG=b:149362272 BRANCH=octopus TEST=build Signed-off-by: peichao.wang Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39424 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen --- src/mainboard/google/octopus/variants/foob/variant.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/google/octopus/variants/foob/variant.c b/src/mainboard/google/octopus/variants/foob/variant.c index 47639f6345..d5d76585d9 100644 --- a/src/mainboard/google/octopus/variants/foob/variant.c +++ b/src/mainboard/google/octopus/variants/foob/variant.c @@ -16,6 +16,7 @@ #include #include #include +#include #define SKU_UNKNOWN 0xFFFFFFFF @@ -34,3 +35,14 @@ void variant_update_devtree(struct device *dev) if (no_touchscreen_sku(sku_id)) touchscreen_i2c_host->enabled = 0; } + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id = SKU_UNKNOWN; + + sku_id = google_chromeec_get_board_sku(); + if (sku_id == 9) + filename = "wifi_sar-foob360.hex"; + return filename; +} From b6e2afb1ffe7683118ba879ca19ef6343f641d17 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 21 Jan 2020 08:57:00 -0700 Subject: [PATCH 0484/1463] src/device/pci_rom.c: Show device IDs on oprom failure On a device/option-rom ID mismatch, the option rom's IDs would get shown twice instead of showing the actual device's IDs. This was very confusing because the error showed matching IDs. BUG=None TEST=Shows mismatched IDs when option rom doesn't match the hardware Change-Id: I5a06d6a7319aa653c8a5e32ec3c5afb651d83140 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2013180 Reviewed-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39586 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/device/pci_rom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 816255d5e1..27f2d8dca2 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -98,7 +98,7 @@ struct rom_header *pci_rom_probe(struct device *dev) || dev->device != rom_data->device) && (vendev == mapped_vendev)) { printk(BIOS_ERR, "ID mismatch: vendor ID %04x, " - "device ID %04x\n", rom_data->vendor, rom_data->device); + "device ID %04x\n", dev->vendor, dev->device); return NULL; } From 1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 20 Feb 2019 16:39:55 -0700 Subject: [PATCH 0485/1463] soc/intel/cannonlake: Set correct serirq mode Set FSP params PchSirqEnable/PchSirqMode based on board setting of serirq_mode. Matches implementation on Skylake. This is a no-change for existing boards since the default remains SERIRQ_QUIET mode. Tested on system76 galp3-c, out-of-tree WHL-U board Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Signed-off-by: Jeremy Soller Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Nathaniel L Desimone --- src/soc/intel/cannonlake/chip.h | 3 +++ src/soc/intel/cannonlake/fsp_params.c | 4 ++++ src/soc/intel/cannonlake/lpc.c | 7 +++---- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 330555c0c0..b14c3c50dc 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -360,6 +361,8 @@ struct soc_intel_cannonlake_config { */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + enum serirq_mode serirq_mode; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 80918f12d9..9d6ed387d6 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -416,6 +416,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Unlock all GPIO pads */ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; + /* Set correct Sirq mode based on config */ + params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; + params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; + /* * GSPI Chip Select parameters * The GSPI driver assumes that CS0 is the used chip-select line, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index c4eb884a75..8b9802220e 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -210,6 +210,8 @@ static void pch_misc_init(void) void lpc_soc_init(struct device *dev) { + const config_t *config = dev->chip_info; + /* Legacy initialization */ isa_dma_init(); pch_misc_init(); @@ -218,10 +220,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (CONFIG(SERIRQ_CONTINUOUS_MODE)) - lpc_set_serirq_mode(SERIRQ_CONTINUOUS); - else - lpc_set_serirq_mode(SERIRQ_QUIET); + lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ pch_enable_ioapic(dev); From bc25a361dc7096b51f56640273269e4867eb0881 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 13 Mar 2020 15:20:18 -0700 Subject: [PATCH 0486/1463] src/include/device: Add Intel Tiger Lake Thunderbolt device Id Tiger Lake Thunderbolt(TBT) has 4 PCIe root ports. Add those TBT root port devices Id from EDS #575683. BUG=None TEST=built image and booted to kernel successfully. Change-Id: Ia117d63daa15dfb21db28fd76723e97ab030da92 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/39526 Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Reviewed-by: Srinidhi N Kaushik Reviewed-by: Divya S Sasidharan Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3da326b7bc..8d634f8106 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3624,6 +3624,12 @@ #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 #define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4 +/* Intel Thunderbolt device Ids */ +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP0 0x9a23 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 + /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 #define PCI_DEVICE_ID_6005_SERIES_WIFI 0x0085 From 789bdc3d9bdd4f4a7587b8dd2dc7cc21e1f2495c Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Fri, 13 Mar 2020 18:13:50 +0530 Subject: [PATCH 0487/1463] src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASL Method RAOW is assuming that the first argument is a Field object and writing to it expecting the register to get updated. However, the callers are passing in the value of the Field object instead. This eventually is resulting the IMGCLK not getting enable/disabled on the platform. Fix this by sending the exact address of the register to be updated. Also MCCT was setting the clock frequency in both case i.e, Clock Enable and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing like below MCON: Set frequency Enable clock MCOF: Disable clock Also, make use of MCON and MCOF methods for camera clock control in tglrvp. This is to avoid the buildbot marking the patch unstable. BUG=None BRANCH=None TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Signed-off-by: Rizwan Qureshi Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- .../intel/tglrvp/acpi/mipi_camera.asl | 8 +- .../intel/tigerlake/acpi/camera_clock_ctl.asl | 127 +++++------------- 2 files changed, 38 insertions(+), 97 deletions(-) diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index c830ea1f46..5d42a29aee 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -177,7 +177,7 @@ Scope (\_SB.PCI0.I2C3) If ((STA == Zero)) { /* Enable CLK0 with 19.2MHz */ - MCCT(0,1,1) + MCON(0,1) /* Pull PWREN(GPIO B23) high */ STXS(GPP_B23) Sleep(5) @@ -200,7 +200,7 @@ Scope (\_SB.PCI0.I2C3) /* Pull PWREN low */ CTXS(GPP_B23) /* Disable CLK0 */ - MCCT(0,0,1) + MCOF(0) Store(0,STA) } } @@ -380,7 +380,7 @@ Scope (\_SB.PCI0.I2C5) If ((STA == Zero)) { /* Enable CLK1 with 19.2MHz */ - MCCT(1,1,1) + MCON(1,1) /* Pull PWREN(GPIO R6) high */ STXS(GPP_R6) Sleep(5) @@ -403,7 +403,7 @@ Scope (\_SB.PCI0.I2C5) /* Pull PWREN low */ CTXS(GPP_R6) /* Disable CLK1 */ - MCCT(1,0,1) + MCOF(1) Store(0,STA) } } diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index ab1097e274..c9da977c7d 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -18,22 +18,23 @@ #define B_ICLK_PCR_FREQUENCY 0x1 #define B_ICLK_PCR_REQUEST 0x2 +/* The clock control registers for each IMGCLK are offset by 0xC */ +#define B_ICLK_PCR_OFFSET 0xC + Scope (\_SB.PCI0) { - /* IsCLK PCH register for clock settings */ - OperationRegion (ICLK, SystemMemory, PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, 0x40) - Field (ICLK, AnyAcc, Lock, Preserve) + + /* IsCLK PCH base register for clock settings */ + Name (ICKB, 0) + Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) + + /* + * Arg0 : Clock Number + * Return : Offset of register to control the clock in Arg0 + * + */ + Method (OFST, 0x1, NotSerialized) { - CLK1, 8, - Offset(0x0C), - CLK2, 8, - Offset(0x18), - CLK3, 8, - Offset(0x24), - CLK4, 8, - Offset(0x30), - CLK5, 8, - Offset(0x3C), - CLK6, 8, + Return (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)) } /* @@ -42,95 +43,35 @@ Scope (\_SB.PCI0) { * Arg1 : And data * Arg2 : Or data */ - Method (RAOW, 0x3, NotSerialized) + Method (RAOW, 0x3, Serialized) { - Local0 = Arg0 - Arg0 = Local0 & Arg1 | Arg2 - } - - /* - * Clock Control - * Arg0 - Clock number (0:IMGCLKOUT_0, etc) - * Arg1 - Desired state (0:Disable, 1:Enable) - */ - Method(CLKC, 0x2, NotSerialized) - { - - Switch (ToInteger (Arg0)) + OperationRegion (ICLK, SystemMemory, OFST(Arg0), 4) + Field (ICLK, AnyAcc, NoLock, Preserve) { - Case (0) - { - RAOW (CLK1, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (1) - { - RAOW (CLK2, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (2) - { - RAOW (CLK3, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (3) - { - RAOW (CLK4, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (4) - { - RAOW (CLK5, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (5) - { - RAOW (CLK6, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - } - } - - /* - * Clock Frequency - * Arg0 - Clock number (0:IMGCLKOUT_0, etc) - * Arg1 - Clock frequency (0:24MHz, 1:19.2MHz) - */ - Method (CLKF, 0x2, NotSerialized) - { - Switch (ToInteger (Arg0)) - { - Case (0) - { - RAOW (CLK1, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (1) - { - RAOW (CLK2, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (2) - { - RAOW (CLK3, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (3) - { - RAOW (CLK4, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (4) - { - RAOW (CLK5, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (5) - { - RAOW (CLK6, ~B_ICLK_PCR_FREQUENCY, Arg1) - } + VAL0, 32 } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 } /* * Clock control Method * Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3, * 4: IMGCLKOUT_4, 5: IMGCLKOUT_5) - * Arg1: Clock Enable / Disable (0: Disable, 1: Enable) - * Arg2: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz) + * Arg1: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz) */ - Method (MCCT, 0x3, NotSerialized) + Method (MCON, 0x2, NotSerialized) { - CLKF (Arg0, Arg2) - CLKC (Arg0, Arg1) + /* Set Clock Frequency */ + RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) + + /* Enable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST) + } + + Method (MCOF, 0x1, NotSerialized) + { + /* Disable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0) } } From 0ae21ff7ff5cee842fd18bbd0e84821f5ab945d8 Mon Sep 17 00:00:00 2001 From: Daniel Kang Date: Fri, 13 Mar 2020 18:19:24 -0700 Subject: [PATCH 0488/1463] src/mb/intel/tglrvp: Update camera ACPI configuration * Change power sequence to make it closer to ov8856 sensor data sheet version 2 * Handle different PWREN GPIO pins for up3 and up4 * Add link frequencies definitions to sensor side * Clean up format BUG=None BRANCH=None TEST=Build and boot TGLRVP U or Y. Start camera app and able to capture images. Signed-off-by: Daniel Kang Change-Id: Ic11a36f1f82fe425c1a5796847ce020007064403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39529 Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- .../intel/tglrvp/acpi/mipi_camera.asl | 204 ++++++++++-------- 1 file changed, 115 insertions(+), 89 deletions(-) diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 5d42a29aee..af03ddc03c 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -15,7 +15,7 @@ Scope (\_SB.PCI0.IPU0) { - Name (_DSD, Package (0x02) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x02) @@ -25,7 +25,6 @@ Scope (\_SB.PCI0.IPU0) "port0", "PRT0" }, - Package (0x02) { "port1", @@ -45,7 +44,6 @@ Scope (\_SB.PCI0.IPU0) One } }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { @@ -81,7 +79,7 @@ Scope (\_SB.PCI0.IPU0) }) } -Scope (_SB.PCI0.IPU0) +Scope (\_SB.PCI0.IPU0) { Name (EP00, Package (0x02) { @@ -93,13 +91,11 @@ Scope (_SB.PCI0.IPU0) "endpoint", Zero }, - Package (0x02) { "clock-lanes", Zero }, - Package (0x02) { "data-lanes", @@ -111,7 +107,6 @@ Scope (_SB.PCI0.IPU0) 0x04 } }, - Package (0x02) { "remote-endpoint", @@ -134,13 +129,11 @@ Scope (_SB.PCI0.IPU0) "endpoint", Zero }, - Package (0x02) { "clock-lanes", Zero }, - Package (0x02) { "data-lanes", @@ -172,40 +165,45 @@ Scope (\_SB.PCI0.I2C3) PowerResource (RCPR, 0x00, 0x0000) { Name (STA, Zero) - Method (_ON, 0, Serialized) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ { If ((STA == Zero)) { - /* Enable CLK0 with 19.2MHz */ - MCON(0,1) - /* Pull PWREN(GPIO B23) high */ - STXS(GPP_B23) - Sleep(5) - /* Pull RST(GPIO C15) low */ + /* Enable IMG_CLK */ + MCON(0,1) /* Clock 0, 19.2MHz */ + + /* Pull RST low */ CTXS(GPP_C15) - Sleep(5) + + /* Pull PWREN high */ + STXS(GPP_B23) + Sleep(2) /* reset pulse width */ + /* Pull RST high */ STXS(GPP_C15) - Sleep(5) + Sleep(1) /* t2 */ + Store(1,STA) } } - - Method (_OFF, 0, Serialized) + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { If ((STA == One)) { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(0) /* Clock 0 */ + /* Pull RST low */ CTXS(GPP_C15) + /* Pull PWREN low */ CTXS(GPP_B23) - /* Disable CLK0 */ - MCOF(0) + Store(0,STA) } } - - Method (_STA, 0, NotSerialized) + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (STA) } @@ -213,33 +211,29 @@ Scope (\_SB.PCI0.I2C3) Device (CAM0) { - Name (_HID, "OVTI8856") - Name (_UID, Zero) - Name (_DDN, "Ov 8856 Camera") - Method (_STA, 0, NotSerialized) + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (0x0F) } - - Name (_CRS, ResourceTemplate () + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ { I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C3", 0x00, ResourceConsumer, , ) }) - - Name (_PR0, Package (0x01) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { RCPR }) - - Name (_PR3, Package (0x01) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { RCPR }) - - Name (_DSD, Package (0x04) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) @@ -250,7 +244,6 @@ Scope (\_SB.PCI0.I2C3) "PRT0" } }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x02) { @@ -269,7 +262,6 @@ Scope (\_SB.PCI0.I2C3) } } }) - Name (PRT0, Package (0x04) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), @@ -281,7 +273,6 @@ Scope (\_SB.PCI0.I2C3) Zero } }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { @@ -292,24 +283,39 @@ Scope (\_SB.PCI0.I2C3) } } }) - Name (EP00, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x03) + Package (0x05) { Package (0x02) { "endpoint", Zero }, - + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, Package (0x02) { "link-frequencies", - Package (0x01) + Package (0x02) { - 0x325AA000 + 0x15752A00, + 0xABA9500 } }, Package (0x02) @@ -328,34 +334,33 @@ Scope (\_SB.PCI0.I2C3) Device (VCM0) { - Name (_HID, "PRP0001") - Name (_UID, 0x03) - Name (_DDN, "DW9714 VCM") - Method (_STA, 0, NotSerialized) + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (0x0F) } - - Name (_CRS, ResourceTemplate () + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ { I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C3", 0x00, ResourceConsumer, , ) }) - Name (_DEP, Package (0x01) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ { CAM0 }) - Name (_PR0, Package (0x01) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { RCPR }) - Name (_PR3, Package (0x01) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { RCPR }) - Name (_DSD, Package (0x02) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x01) @@ -375,40 +380,53 @@ Scope (\_SB.PCI0.I2C5) PowerResource (FCPR, 0x00, 0x0000) { Name (STA, Zero) - Method (_ON, 0, Serialized) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ { If ((STA == Zero)) { - /* Enable CLK1 with 19.2MHz */ - MCON(1,1) - /* Pull PWREN(GPIO R6) high */ - STXS(GPP_R6) - Sleep(5) - /* Pull RST(GPIO H12) low */ + /* Enable IMG_CLK */ + MCON(1,1) /* Clock 1, 19.2MHz */ + + /* Pull RST low */ CTXS(GPP_H12) - Sleep(5) + + /* Pull PWREN high */ +#if CONFIG_BOARD_INTEL_TIGERLAKE_RVPY + STXS(GPP_E22) +#else + STXS(GPP_R6) +#endif + Sleep(2) /* reset pulse width */ + /* Pull RST high */ STXS(GPP_H12) - Sleep(5) + Sleep(1) /* t2 */ + Store(1,STA) } } - - Method (_OFF, 0, Serialized) + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { If ((STA == One)) { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(1) /* Clock 1 */ + /* Pull RST low */ CTXS(GPP_H12) + /* Pull PWREN low */ +#if CONFIG_BOARD_INTEL_TIGERLAKE_RVPY + CTXS(GPP_E22) +#else CTXS(GPP_R6) - /* Disable CLK1 */ - MCOF(1) +#endif + Store(0,STA) } } - - Method (_STA, 0, NotSerialized) // _STA: Status + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (STA) } @@ -416,33 +434,29 @@ Scope (\_SB.PCI0.I2C5) Device (CAM1) { - Name (_HID, "OVTI8856") - Name (_UID, Zero) - Name (_DDN, "Ov 8856 Camera") - Method (_STA, 0, NotSerialized) + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (0x0F) } - - Name (_CRS, ResourceTemplate () + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ { I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C5", 0x00, ResourceConsumer, , ) }) - - Name (_PR0, Package (0x01) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { FCPR }) - - Name (_PR3, Package (0x01) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { FCPR }) - - Name (_DSD, Package (0x04) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) @@ -453,7 +467,6 @@ Scope (\_SB.PCI0.I2C5) "PRT0" } }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x01) { @@ -464,7 +477,6 @@ Scope (\_SB.PCI0.I2C5) } } }) - Name (PRT0, Package (0x04) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), @@ -476,7 +488,6 @@ Scope (\_SB.PCI0.I2C5) Zero } }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { @@ -487,24 +498,39 @@ Scope (\_SB.PCI0.I2C5) } } }) - Name (EP00, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x03) + Package (0x05) { Package (0x02) { "endpoint", Zero }, - + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, Package (0x02) { "link-frequencies", - Package (0x01) + Package (0x02) { - 0x325AA000 + 0x15752A00, + 0xABA9500 } }, Package (0x02) From 7790cb680a58bf2a5c869dadbb23fbd6bd680f7d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 15 Mar 2020 17:11:18 -0500 Subject: [PATCH 0489/1463] sb/lynxpoint/gpio: fix interrupt storm On newer kernels (> 4.9 LTS), the GPIO ACPI device's interrupt resource causes an interrupt storm which prevents the CPU from properly idling, significantly increasing power consumption. This was fixed for soc/broadwell (which also supports lynxpoint-lp) by removing the interrupt resource, so apply the same fix here. Original fix: https://chromium-review.googlesource.com/203645 Test: build/boot google/wolf, verify CPU0 idles correctly and power consumption drop via powertop in kernels 4.16.18 and 5.x. Change-Id: Ic4963f2f0225b5f44a7604b0107911640345c855 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39578 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 88138a1d61..2a3c096099 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -551,8 +551,9 @@ Device (GPIO) , // ResourceSourceIndex , // ResourceSource BAR0) - Interrupt (ResourceConsumer, - Level, ActiveHigh, Shared, , ,) {14} + // Disabled due to IRQ storm: http://crosbug.com/p/29548 + //Interrupt (ResourceConsumer, + // Level, ActiveHigh, Shared, , , ) {14} }) Method (_CRS, 0, NotSerialized) From cbae2e401e536c63c47ed4042b19d53bcfe48ae2 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 21 Jan 2020 21:50:59 -0700 Subject: [PATCH 0490/1463] soc/amd/picasso: Move get_soc_config to common location Multiple files can eventually take advantage of the static function in i2c.c. Move get_soc_config() into a new common location for all to use. Signed-off-by: Marshall Dawson Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38695 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/cfg_util.c | 30 ++++++++++++++++++++++++++++++ src/soc/amd/picasso/i2c.c | 13 ------------- 3 files changed, 31 insertions(+), 13 deletions(-) create mode 100644 src/soc/amd/picasso/cfg_util.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 680f0fa956..89fd5c4c39 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -78,6 +78,7 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c +all-y += cfg_util.c all-y += reset.c smm-y += smihandler.c diff --git a/src/soc/amd/picasso/cfg_util.c b/src/soc/amd/picasso/cfg_util.c new file mode 100644 index 0000000000..60555e44c5 --- /dev/null +++ b/src/soc/amd/picasso/cfg_util.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "chip.h" + +const config_t *get_soc_config(void) +{ + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return NULL; + } + + return dev->chip_info; +} diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index bcdf3850a8..408b60b315 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -42,19 +42,6 @@ uintptr_t dw_i2c_base_address(unsigned int bus) return i2c_bus_address[bus - APU_I2C_MIN_BUS]; } -static const struct soc_amd_picasso_config *get_soc_config(void) -{ - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - return dev->chip_info; -} - const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; From 69cfbb075021cc1d2f39bb5b87755a9a4424903f Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 20 Jan 2020 22:58:51 -0700 Subject: [PATCH 0491/1463] soc/amd/picasso: Remove unused defines from cpu.h Signed-off-by: Marshall Dawson Change-Id: I4ed3e7c82ef5808a0e96c07c16f4872f8ca3ec76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38693 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/include/soc/cpu.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 9af4c0c843..338e8718e9 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,9 +18,6 @@ #include -#define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_TEMPRAM 2 - #define CSTATE_BASE_REG 0xc0010073 void picasso_init_cpus(struct device *dev); From 8e04a1762b98f14c31b99bbb0a43c1280cc21a3a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 12:51:24 +0100 Subject: [PATCH 0492/1463] AUTHORS: Move authors from src to AUTHORS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is in preparation of replacing all license headers with a spdx identifier, removal of copyright notices in individual files comes later. The missing authors were determined by "git grep Copyright src" Change-Id: Id9942f9f9a26484bbc22584bba7b3af5846eefe8 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39605 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Reviewed-by: Felix Held Reviewed-by: HAOUAS Elyes Reviewed-by: Alexander Couzens Reviewed-by: David Hendricks --- AUTHORS | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 2 deletions(-) diff --git a/AUTHORS b/AUTHORS index 9ec48bbf9d..f3c0aaa986 100644 --- a/AUTHORS +++ b/AUTHORS @@ -8,28 +8,43 @@ # To see a list of contributors: git log --pretty=format:%an | sort | uniq # For patches adding or removing a name: git log -i -S "NAME" --source --all +3mdeb Embedded Systems Consulting 9elements Agency GmbH +Abhinav Hardikar +Advanced Computing Lab, LANL Advanced Micro Devices, Inc. +AdaCore AG Electronics Ltd. Alex Züpke Alexander Couzens Alexandru Gagniuc Analog Devices Inc. +Analogix Semiconductor +Andre Heider Andy Fleming +Angel Pons ARM Limited and Contributors Arthur Heymans +Asami Doi ASPEED Technology Inc. Atheros Corporation Atmel Corporation BAP - Bruhnspace Advanced Projects +Bill Xie +Bitland Tech Inc. Carl-Daniel Hailfinger +Cavium Inc. Christoph Grenz +Code Aurora Forum coresystems GmbH Corey Osgood Damien Zammit +Dave Airlie David Brownell +David Greenman David Hendricks David Mosberger-Tang +David Mueller Denis Dowling DENX Software Engineering Digital Design Corporation @@ -38,49 +53,78 @@ Drew Eckhardt Dynon Avionics Edward O'Callaghan Egbert Eich +ELSOFT AG Eltan B.V +Elyes Haouas Eric Biederman Eswar Nallusamy +Evgeny Zinoviev Fabian Kunkel +Fabrice Bellard Facebook, Inc. Felix Held +Felix Singer Frederic Potter Free Software Foundation, Inc. Freescale Semiconductor, Inc. Gary Jennejohn +George Trudeau Gerd Hoffmann Gergely Kiss Google LLC Greg Watson +Guennadi Liakhovetski +Hal Martin HardenedLinux +Hewlett-Packard Development Company, L.P. +Hewlett Packard Enterprise Development LP +Huaqin Telecom Inc. +IBM Corporation Idwer Vollering +Igor Pavlov Imagination Technologies Infineon Technologies Intel Corporation +Iru Cai +Isaku Yamahata +Ivan Vatlin +James Ye Jason Zhao +Johanna Schander +Jonas 'Sortie' Termansen Jonathan Neuschäfer Jordan Crouse Joseph Smith Keith Hui Keith Packard Kevin Cody-Little +Kevin O'Connor +Kontron Europe GmbH Kshitij Kyösti Mälkki Lei Wen Li-Ta Lo Libra Li Libretrend LDA +Linaro Limited Linus Torvalds Linux Networx, Inc. +LiPPERT ADLINK Technology GmbH Luc Verhaegen +Maciej Matuszczyk +Marc Bertens Marc Jones Marek Vasut Marius Gröger Martin Mares +Martin Renters Marvell International Ltd. Marvell Semiconductor Inc. Matt DeVillier +Maxim Polyakov MediaTek Inc. +Michael Schroeder +Mika Westerberg Mondrian Nuessle MontaVista Software, Inc. Myles Watson @@ -88,23 +132,35 @@ Network Appliance Inc. Nicholas Sielicki Nick Barker Nico Huber +Nico Rikken Nicola Corna +Nokia Corporation +NVIDIA Corporation Ollie Lo Omar Pakker +Online SAS Orion Technologies, LLC Patrick Georgi Patrick Rudolph +Pattrick Hueper +Paulo Alcantara Pavel Sayekat PC Engines GmbH Per Odlund Peter Stuge Philipp Degler +Philipp Hug Protectli +Purism SPC +Qualcomm Technologies Raptor Engineering, LLC -Red Hat Inc +Red Hat, Inc Reinhard Meyer +Renze Nicolai Richard Spiegel Richard Woodruff +Robert Reeves +Rockchip, Inc. Ronald G. Minnich Rudolf Marek Russell King @@ -114,15 +170,19 @@ Samuel Holland SciTech Software, Inc. Sebastian Grzywna secunet Security Networks AG +Sergej Ivanov Siemens AG +SiFive, Inc Silicon Integrated System Corporation -Silverback ltd. +Silverback Ltd. Stefan Reinauer +Stefan Tauner Steve Magnani ST Microelectronics SUSE LINUX AG Sven Schnelle Syed Mohammed Khasim +System76 Texas Instruments The ChromiumOS Authors The Linux Foundation @@ -130,6 +190,7 @@ The Regents of the University of California Thomas Winischhofer Timothy Pearson Tobias Diedrich +Tristan Corrick Tungsten Graphics, Inc. Tyan Computer Corp. ucRobotics Inc. @@ -138,10 +199,13 @@ Uwe Hermann VIA Technologies, Inc Vipin Kumar Vladimir Serbinenko +Vlado Cibic Wang Qing Pei Ward Vandewege Win Enterprises +Wiwynn Corp. Wolfgang Denk +Yann Collet Yinghai Lu From f3f36faf352c72d793899a8b0dce60423a7480fa Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 12:51:24 +0100 Subject: [PATCH 0493/1463] src (minus soc and mainboard): Remove copyright notices They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/Kconfig | 2 -- src/commonlib/include/commonlib/stdlib.h | 2 -- src/cpu/x86/16bit/entry16.inc | 2 -- src/cpu/x86/64bit/entry64.inc | 1 - src/drivers/amd/agesa/exit_car.S | 1 - src/drivers/analogix/anx7625/Kconfig | 1 - src/drivers/analogix/anx7625/Makefile.inc | 1 - src/drivers/analogix/anx7625/anx7625.c | 1 - src/drivers/analogix/anx7625/anx7625.h | 5 ----- src/drivers/aspeed/common/ast_drv.h | 2 -- src/drivers/aspeed/common/ast_main.c | 2 -- src/drivers/aspeed/common/ast_post.c | 2 -- src/drivers/aspeed/common/ast_tables.h | 1 - src/drivers/gfx/generic/chip.h | 1 - src/drivers/gfx/generic/generic.c | 1 - src/drivers/i2c/ptn3460/ptn3460.c | 1 - src/drivers/i2c/ptn3460/ptn3460.h | 1 - src/drivers/i2c/rt1011/chip.h | 1 - src/drivers/i2c/rt1011/rt1011.c | 1 - src/drivers/ipmi/ipmi_fru.c | 1 - src/drivers/ipmi/ipmi_ops.c | 1 - src/drivers/ipmi/ipmi_ops.h | 1 - src/drivers/spi/spi_sdcard.c | 1 - src/drivers/uart/pl011.h | 2 -- src/ec/acpi/ec.asl | 1 - src/ec/acpi/ec.c | 1 - src/ec/acpi/ec.h | 1 - src/ec/compal/ene932/acpi/ac.asl | 1 - src/ec/compal/ene932/acpi/battery.asl | 1 - src/ec/compal/ene932/acpi/ec.asl | 1 - src/ec/compal/ene932/acpi/superio.asl | 1 - src/ec/compal/ene932/chip.h | 1 - src/ec/compal/ene932/ec.c | 1 - src/ec/compal/ene932/ec.h | 1 - src/ec/ec.h | 1 - src/ec/google/chromeec/acpi/ac.asl | 1 - src/ec/google/chromeec/acpi/als.asl | 1 - src/ec/google/chromeec/acpi/battery.asl | 1 - src/ec/google/chromeec/acpi/cros_ec.asl | 1 - src/ec/google/chromeec/acpi/ec.asl | 1 - src/ec/google/chromeec/acpi/emem.asl | 1 - src/ec/google/chromeec/acpi/keyboard_backlight.asl | 1 - src/ec/google/chromeec/acpi/pd.asl | 1 - src/ec/google/chromeec/acpi/superio.asl | 1 - src/ec/google/chromeec/acpi/tbmc.asl | 1 - src/ec/google/chromeec/chip.h | 1 - src/ec/google/chromeec/crosec_proto.c | 1 - src/ec/google/chromeec/ec.c | 1 - src/ec/google/chromeec/ec.h | 1 - src/ec/google/chromeec/ec_acpi.c | 1 - src/ec/google/chromeec/ec_boardid.c | 1 - src/ec/google/chromeec/ec_i2c.c | 1 - src/ec/google/chromeec/ec_lpc.c | 1 - src/ec/google/chromeec/ec_skuid.c | 1 - src/ec/google/chromeec/ec_spi.c | 1 - src/ec/google/chromeec/smihandler.c | 1 - src/ec/google/chromeec/smm.h | 1 - src/ec/google/chromeec/switches.c | 1 - src/ec/google/chromeec/vboot_storage.c | 1 - src/ec/google/chromeec/vstore.c | 1 - src/ec/google/common/mec.c | 1 - src/ec/google/common/mec.h | 1 - src/ec/google/wilco/acpi/ac.asl | 1 - src/ec/google/wilco/acpi/battery.asl | 1 - src/ec/google/wilco/acpi/dptf.asl | 1 - src/ec/google/wilco/acpi/ec.asl | 1 - src/ec/google/wilco/acpi/ec_dev.asl | 1 - src/ec/google/wilco/acpi/ec_ram.asl | 1 - src/ec/google/wilco/acpi/event.asl | 1 - src/ec/google/wilco/acpi/lid.asl | 1 - src/ec/google/wilco/acpi/platform.asl | 1 - src/ec/google/wilco/acpi/privacy.asl | 1 - src/ec/google/wilco/acpi/superio.asl | 1 - src/ec/google/wilco/acpi/ucsi.asl | 1 - src/ec/google/wilco/acpi/vbtn.asl | 1 - src/ec/google/wilco/boardid.c | 1 - src/ec/google/wilco/bootblock.c | 1 - src/ec/google/wilco/bootblock.h | 1 - src/ec/google/wilco/chip.c | 1 - src/ec/google/wilco/chip.h | 1 - src/ec/google/wilco/commands.c | 1 - src/ec/google/wilco/commands.h | 1 - src/ec/google/wilco/ec.h | 1 - src/ec/google/wilco/mailbox.c | 1 - src/ec/google/wilco/romstage.c | 1 - src/ec/google/wilco/romstage.h | 1 - src/ec/google/wilco/smihandler.c | 1 - src/ec/google/wilco/smm.h | 1 - src/ec/hp/kbc1126/Kconfig | 1 - src/ec/hp/kbc1126/Makefile.inc | 1 - src/ec/hp/kbc1126/acpi/ac.asl | 1 - src/ec/hp/kbc1126/acpi/battery.asl | 1 - src/ec/hp/kbc1126/acpi/ec.asl | 1 - src/ec/hp/kbc1126/acpi/lid.asl | 1 - src/ec/hp/kbc1126/chip.h | 1 - src/ec/hp/kbc1126/early_init.c | 1 - src/ec/hp/kbc1126/ec.c | 2 -- src/ec/hp/kbc1126/ec.h | 1 - src/ec/kontron/it8516e/acpi/ec.asl | 1 - src/ec/kontron/it8516e/acpi/pm_channels.asl | 1 - src/ec/kontron/it8516e/chip.h | 1 - src/ec/kontron/it8516e/ec.c | 1 - src/ec/kontron/it8516e/ec.h | 1 - src/ec/kontron/kempld/chip.h | 1 - src/ec/kontron/kempld/early_kempld.c | 1 - src/ec/kontron/kempld/kempld.c | 1 - src/ec/kontron/kempld/kempld.h | 1 - src/ec/kontron/kempld/kempld_internal.h | 1 - src/ec/lenovo/h8/acpi/ac.asl | 1 - src/ec/lenovo/h8/acpi/battery.asl | 1 - src/ec/lenovo/h8/acpi/beep.asl | 1 - src/ec/lenovo/h8/acpi/ec.asl | 2 -- src/ec/lenovo/h8/acpi/lid.asl | 1 - src/ec/lenovo/h8/acpi/sleepbutton.asl | 1 - src/ec/lenovo/h8/acpi/systemstatus.asl | 1 - src/ec/lenovo/h8/acpi/thinkpad.asl | 1 - src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl | 2 -- src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl | 2 -- src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl | 2 -- src/ec/lenovo/h8/bluetooth.c | 1 - src/ec/lenovo/h8/chip.h | 1 - src/ec/lenovo/h8/h8.c | 1 - src/ec/lenovo/h8/h8.h | 1 - src/ec/lenovo/h8/panic.c | 1 - src/ec/lenovo/h8/sense.c | 1 - src/ec/lenovo/h8/ssdt.c | 1 - src/ec/lenovo/h8/vboot.c | 1 - src/ec/lenovo/h8/wwan.c | 1 - src/ec/lenovo/pmh7/chip.h | 1 - src/ec/lenovo/pmh7/pmh7.c | 1 - src/ec/lenovo/pmh7/pmh7.h | 1 - src/ec/purism/librem/acpi/ac.asl | 1 - src/ec/purism/librem/acpi/battery.asl | 1 - src/ec/purism/librem/acpi/ec.asl | 1 - src/ec/quanta/ene_kb3940q/acpi/ac.asl | 1 - src/ec/quanta/ene_kb3940q/acpi/battery.asl | 1 - src/ec/quanta/ene_kb3940q/acpi/ec.asl | 1 - src/ec/quanta/ene_kb3940q/acpi/superio.asl | 1 - src/ec/quanta/ene_kb3940q/chip.h | 1 - src/ec/quanta/ene_kb3940q/ec.c | 1 - src/ec/quanta/ene_kb3940q/ec.h | 1 - src/ec/quanta/it8518/acpi/ac.asl | 1 - src/ec/quanta/it8518/acpi/battery.asl | 1 - src/ec/quanta/it8518/acpi/ec.asl | 1 - src/ec/quanta/it8518/acpi/superio.asl | 1 - src/ec/quanta/it8518/chip.h | 1 - src/ec/quanta/it8518/ec.c | 1 - src/ec/quanta/it8518/ec.h | 1 - src/ec/roda/it8518/Kconfig | 1 - src/ec/roda/it8518/Makefile.inc | 1 - src/ec/roda/it8518/acpi/ac.asl | 1 - src/ec/roda/it8518/acpi/battery.asl | 1 - src/ec/roda/it8518/acpi/ec.asl | 1 - src/ec/roda/it8518/acpi/lid.asl | 1 - src/ec/roda/it8518/chip.h | 1 - src/ec/roda/it8518/ec.c | 1 - src/ec/smsc/mec1308/acpi/ac.asl | 1 - src/ec/smsc/mec1308/acpi/battery.asl | 1 - src/ec/smsc/mec1308/acpi/ec.asl | 1 - src/ec/smsc/mec1308/chip.h | 1 - src/ec/smsc/mec1308/ec.c | 1 - src/ec/smsc/mec1308/ec.h | 1 - src/include/assert.h | 1 - src/include/base3.h | 1 - src/include/bcd.h | 1 - src/include/boardid.h | 1 - src/include/boot_device.h | 1 - src/include/bootblock_common.h | 1 - src/include/bootmem.h | 1 - src/include/bootmode.h | 1 - src/include/bootsplash.h | 1 - src/include/bootstate.h | 1 - src/include/cbfs.h | 1 - src/include/cbmem.h | 2 -- src/include/console/cbmem_console.h | 1 - src/include/console/console.h | 1 - src/include/console/flash.h | 1 - src/include/console/ne2k.h | 1 - src/include/console/post_codes.h | 1 - src/include/console/spi.h | 1 - src/include/console/uart.h | 1 - src/include/console/usb.h | 2 -- src/include/console/vtxprintf.h | 1 - src/include/cper.h | 1 - src/include/cpu/amd/msr.h | 3 --- src/include/cpu/intel/l2_cache.h | 1 - src/include/cpu/intel/microcode.h | 2 -- src/include/cpu/intel/speedstep.h | 2 -- src/include/cpu/intel/turbo.h | 1 - src/include/cpu/x86/cache.h | 1 - src/include/cpu/x86/cr.h | 1 - src/include/cpu/x86/mp.h | 1 - src/include/cpu/x86/name.h | 1 - src/include/cpu/x86/pae.h | 2 -- src/include/cpu/x86/smm.h | 1 - src/include/crc_byte.h | 1 - src/include/device/azalia.h | 1 - src/include/device/azalia_device.h | 1 - src/include/device/dram/common.h | 2 -- src/include/device/dram/ddr2.h | 1 - src/include/device/dram/ddr3.h | 1 - src/include/device/dram/ddr4.h | 1 - src/include/device/i2c.h | 1 - src/include/device/i2c_simple.h | 1 - src/include/device/pci_ehci.h | 2 -- src/include/device/pci_mmio_cfg.h | 1 - src/include/device/pci_ops.h | 3 --- src/include/device/spi.h | 1 - src/include/dimm_info_util.h | 1 - src/include/edid.h | 1 - src/include/efi/efi_datatype.h | 1 - src/include/elog.h | 1 - src/include/fmap.h | 1 - src/include/gic.h | 1 - src/include/gpio.h | 1 - src/include/halt.h | 1 - src/include/imd.h | 1 - src/include/lib.h | 1 - src/include/memlayout.h | 1 - src/include/memrange.h | 1 - src/include/mrc_cache.h | 1 - src/include/nhlt.h | 1 - src/include/pc80/i8254.h | 1 - src/include/pc80/i8259.h | 2 -- src/include/pc80/vga.h | 1 - src/include/pc80/vga_io.h | 1 - src/include/program_loading.h | 3 --- src/include/random.h | 1 - src/include/reg_script.h | 1 - src/include/region_file.h | 1 - src/include/rmodule.h | 1 - src/include/romstage_handoff.h | 1 - src/include/rtc.h | 1 - src/include/sar.h | 1 - src/include/sdram_mode.h | 1 - src/include/smbios.h | 3 --- src/include/smmstore.h | 1 - src/include/spd.h | 2 -- src/include/spd_bin.h | 1 - src/include/spd_ddr2.h | 2 -- src/include/spi_bitbang.h | 1 - src/include/spi_sdcard.h | 1 - src/include/stage_cache.h | 1 - src/include/superio/conf_mode.h | 2 -- src/include/symbols.h | 1 - src/include/thread.h | 1 - src/include/timer.h | 1 - src/include/timestamp.h | 2 -- src/include/trace.h | 1 - src/include/types.h | 1 - src/include/uuid.h | 1 - src/include/wrdd.h | 2 -- src/lib/Makefile.inc | 1 - src/lib/boot_device.c | 1 - src/lib/bootblock.c | 1 - src/lib/bootmem.c | 3 --- src/lib/bootmode.c | 1 - src/lib/bootsplash.c | 1 - src/lib/cbfs.c | 2 -- src/lib/cbmem_common.c | 1 - src/lib/cbmem_console.c | 1 - src/lib/cbmem_stage_cache.c | 1 - src/lib/coreboot_table.c | 2 -- src/lib/crc_byte.c | 1 - src/lib/decompressor.c | 1 - src/lib/dimm_info_util.c | 1 - src/lib/ext_stage_cache.c | 1 - src/lib/fit_payload.c | 3 --- src/lib/fmap.c | 1 - src/lib/gcc.c | 1 - src/lib/gcov-glue.c | 1 - src/lib/gnat/Makefile.inc | 1 - src/lib/gpio.c | 1 - src/lib/halt.c | 1 - src/lib/hardwaremain.c | 1 - src/lib/hw-time-timer.adb | 1 - src/lib/imd.c | 1 - src/lib/imd_cbmem.c | 1 - src/lib/jpeg.c | 1 - src/lib/jpeg.h | 1 - src/lib/libgcc.c | 1 - src/lib/memrange.c | 1 - src/lib/nhlt.c | 1 - src/lib/primitive_memtest.c | 1 - src/lib/prog_loaders.c | 2 -- src/lib/prog_ops.c | 2 -- src/lib/program.ld | 1 - src/lib/reg_script.c | 1 - src/lib/region_file.c | 1 - src/lib/reset.c | 1 - src/lib/rmodule.c | 1 - src/lib/romstage_handoff.c | 1 - src/lib/rtc.c | 1 - src/lib/selfboot.c | 3 --- src/lib/spd_bin.c | 1 - src/lib/thread.c | 1 - src/lib/timer.c | 1 - src/lib/timer_queue.c | 1 - src/lib/timestamp.c | 2 -- src/lib/trace.c | 1 - src/lib/wrdd.c | 2 -- src/northbridge/amd/agesa/BiosCallOuts.h | 2 -- src/northbridge/amd/agesa/Kconfig | 1 - src/northbridge/amd/agesa/Makefile.inc | 1 - src/northbridge/amd/agesa/agesa_helper.h | 1 - src/northbridge/amd/agesa/dimmSpd.h | 1 - src/northbridge/amd/agesa/family14/Kconfig | 1 - src/northbridge/amd/agesa/family14/Makefile.inc | 1 - src/northbridge/amd/agesa/family14/acpi/northbridge.asl | 1 - src/northbridge/amd/agesa/family14/chip.h | 1 - src/northbridge/amd/agesa/family14/dimmSpd.c | 1 - src/northbridge/amd/agesa/family14/northbridge.c | 1 - src/northbridge/amd/agesa/family14/pci_devs.h | 1 - src/northbridge/amd/agesa/family14/state_machine.c | 1 - src/northbridge/amd/agesa/family15tn/Kconfig | 1 - src/northbridge/amd/agesa/family15tn/Makefile.inc | 1 - src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl | 1 - src/northbridge/amd/agesa/family15tn/chip.h | 1 - src/northbridge/amd/agesa/family15tn/dimmSpd.c | 1 - src/northbridge/amd/agesa/family15tn/iommu.c | 1 - src/northbridge/amd/agesa/family15tn/northbridge.c | 2 -- src/northbridge/amd/agesa/family15tn/pci_devs.h | 1 - src/northbridge/amd/agesa/family15tn/state_machine.c | 1 - src/northbridge/amd/agesa/family16kb/Kconfig | 2 -- src/northbridge/amd/agesa/family16kb/Makefile.inc | 1 - src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl | 1 - src/northbridge/amd/agesa/family16kb/chip.h | 1 - src/northbridge/amd/agesa/family16kb/dimmSpd.c | 1 - src/northbridge/amd/agesa/family16kb/northbridge.c | 1 - src/northbridge/amd/agesa/family16kb/pci_devs.h | 1 - src/northbridge/amd/agesa/family16kb/state_machine.c | 1 - src/northbridge/amd/agesa/state_machine.h | 1 - src/northbridge/amd/pi/00630F01/Kconfig | 1 - src/northbridge/amd/pi/00630F01/Makefile.inc | 1 - src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 1 - src/northbridge/amd/pi/00630F01/chip.h | 1 - src/northbridge/amd/pi/00630F01/dimmSpd.c | 1 - src/northbridge/amd/pi/00630F01/iommu.c | 1 - src/northbridge/amd/pi/00630F01/northbridge.c | 1 - src/northbridge/amd/pi/00630F01/pci_devs.h | 1 - src/northbridge/amd/pi/00660F01/Kconfig | 1 - src/northbridge/amd/pi/00660F01/Makefile.inc | 1 - src/northbridge/amd/pi/00660F01/acpi/northbridge.asl | 1 - src/northbridge/amd/pi/00660F01/chip.h | 1 - src/northbridge/amd/pi/00660F01/dimmSpd.c | 1 - src/northbridge/amd/pi/00660F01/northbridge.c | 1 - src/northbridge/amd/pi/00730F01/Kconfig | 2 -- src/northbridge/amd/pi/00730F01/Makefile.inc | 1 - src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 1 - src/northbridge/amd/pi/00730F01/chip.h | 1 - src/northbridge/amd/pi/00730F01/dimmSpd.c | 1 - src/northbridge/amd/pi/00730F01/iommu.c | 1 - src/northbridge/amd/pi/00730F01/northbridge.c | 3 --- src/northbridge/amd/pi/00730F01/pci_devs.h | 1 - src/northbridge/amd/pi/00730F01/state_machine.c | 1 - src/northbridge/amd/pi/Kconfig | 1 - src/northbridge/amd/pi/Makefile.inc | 1 - src/northbridge/amd/pi/dimmSpd.h | 1 - src/northbridge/intel/e7505/Kconfig | 1 - src/northbridge/intel/e7505/e7505.h | 1 - src/northbridge/intel/e7505/romstage.c | 1 - src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/gm45/Makefile.inc | 1 - src/northbridge/intel/gm45/acpi.c | 1 - src/northbridge/intel/gm45/acpi/gm45.asl | 1 - src/northbridge/intel/gm45/acpi/hostbridge.asl | 1 - src/northbridge/intel/gm45/acpi/peg.asl | 1 - src/northbridge/intel/gm45/chip.h | 2 -- src/northbridge/intel/gm45/early_init.c | 1 - src/northbridge/intel/gm45/early_reset.c | 1 - src/northbridge/intel/gm45/gm45.h | 2 -- src/northbridge/intel/gm45/gma.c | 2 -- src/northbridge/intel/gm45/igd.c | 1 - src/northbridge/intel/gm45/iommu.c | 1 - src/northbridge/intel/gm45/memmap.c | 1 - src/northbridge/intel/gm45/northbridge.c | 1 - src/northbridge/intel/gm45/pcie.c | 1 - src/northbridge/intel/gm45/pm.c | 1 - src/northbridge/intel/gm45/raminit.c | 1 - src/northbridge/intel/gm45/raminit_rcomp_calibration.c | 2 -- src/northbridge/intel/gm45/raminit_read_write_training.c | 2 -- .../intel/gm45/raminit_receive_enable_calibration.c | 2 -- src/northbridge/intel/gm45/romstage.c | 3 --- src/northbridge/intel/gm45/thermal.c | 1 - src/northbridge/intel/haswell/Kconfig | 1 - src/northbridge/intel/haswell/Makefile.inc | 1 - src/northbridge/intel/haswell/acpi.c | 2 -- src/northbridge/intel/haswell/acpi/haswell.asl | 1 - src/northbridge/intel/haswell/acpi/hostbridge.asl | 1 - src/northbridge/intel/haswell/acpi/peg.asl | 1 - src/northbridge/intel/haswell/chip.h | 1 - src/northbridge/intel/haswell/early_init.c | 2 -- src/northbridge/intel/haswell/finalize.c | 1 - src/northbridge/intel/haswell/gma.c | 1 - src/northbridge/intel/haswell/haswell.h | 2 -- src/northbridge/intel/haswell/mchbar_regs.h | 2 -- src/northbridge/intel/haswell/memmap.c | 1 - src/northbridge/intel/haswell/minihd.c | 3 --- src/northbridge/intel/haswell/northbridge.c | 2 -- src/northbridge/intel/haswell/pcie.c | 1 - src/northbridge/intel/haswell/raminit.c | 1 - src/northbridge/intel/haswell/raminit.h | 1 - src/northbridge/intel/haswell/report_platform.c | 1 - src/northbridge/intel/i440bx/Kconfig | 1 - src/northbridge/intel/i440bx/Makefile.inc | 1 - src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl | 1 - src/northbridge/intel/i440bx/i440bx.h | 1 - src/northbridge/intel/i440bx/memmap.c | 1 - src/northbridge/intel/i440bx/northbridge.h | 1 - src/northbridge/intel/i440bx/raminit.c | 2 -- src/northbridge/intel/i440bx/raminit.h | 1 - src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/i945/Makefile.inc | 1 - src/northbridge/intel/i945/acpi.c | 1 - src/northbridge/intel/i945/acpi/hostbridge.asl | 1 - src/northbridge/intel/i945/acpi/i945.asl | 1 - src/northbridge/intel/i945/acpi/igd.asl | 1 - src/northbridge/intel/i945/acpi/peg.asl | 1 - src/northbridge/intel/i945/debug.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/i945/errata.c | 1 - src/northbridge/intel/i945/gma.c | 1 - src/northbridge/intel/i945/i945.h | 1 - src/northbridge/intel/i945/memmap.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/i945/raminit.c | 2 -- src/northbridge/intel/i945/raminit.h | 1 - src/northbridge/intel/i945/rcven.c | 1 - src/northbridge/intel/i945/romstage.c | 1 - src/northbridge/intel/ironlake/Kconfig | 1 - src/northbridge/intel/ironlake/Makefile.inc | 1 - src/northbridge/intel/ironlake/acpi.c | 3 --- src/northbridge/intel/ironlake/acpi/hostbridge.asl | 1 - src/northbridge/intel/ironlake/acpi/ironlake.asl | 1 - src/northbridge/intel/ironlake/chip.h | 1 - src/northbridge/intel/ironlake/early_init.c | 3 --- src/northbridge/intel/ironlake/finalize.c | 1 - src/northbridge/intel/ironlake/gma.c | 2 -- src/northbridge/intel/ironlake/ironlake.h | 3 --- src/northbridge/intel/ironlake/memmap.c | 2 -- src/northbridge/intel/ironlake/northbridge.c | 3 --- src/northbridge/intel/ironlake/raminit.c | 1 - src/northbridge/intel/ironlake/raminit.h | 1 - src/northbridge/intel/ironlake/raminit_tables.c | 1 - src/northbridge/intel/ironlake/raminit_tables.h | 1 - src/northbridge/intel/ironlake/romstage.c | 3 --- src/northbridge/intel/pineview/Kconfig | 2 -- src/northbridge/intel/pineview/Makefile.inc | 2 -- src/northbridge/intel/pineview/acpi.c | 2 -- src/northbridge/intel/pineview/acpi/hostbridge.asl | 1 - src/northbridge/intel/pineview/acpi/peg.asl | 1 - src/northbridge/intel/pineview/acpi/pineview.asl | 1 - src/northbridge/intel/pineview/early_init.c | 1 - src/northbridge/intel/pineview/gma.c | 3 --- src/northbridge/intel/pineview/iomap.h | 1 - src/northbridge/intel/pineview/mchbar_regs.h | 1 - src/northbridge/intel/pineview/memmap.c | 2 -- src/northbridge/intel/pineview/northbridge.c | 2 -- src/northbridge/intel/pineview/pineview.h | 1 - src/northbridge/intel/pineview/raminit.c | 1 - src/northbridge/intel/pineview/raminit.h | 1 - src/northbridge/intel/pineview/romstage.c | 1 - src/northbridge/intel/sandybridge/Kconfig | 1 - src/northbridge/intel/sandybridge/Makefile.inc | 1 - src/northbridge/intel/sandybridge/acpi.c | 2 -- src/northbridge/intel/sandybridge/acpi/hostbridge.asl | 1 - src/northbridge/intel/sandybridge/acpi/peg.asl | 1 - src/northbridge/intel/sandybridge/acpi/sandybridge.asl | 2 -- src/northbridge/intel/sandybridge/chip.h | 1 - src/northbridge/intel/sandybridge/common.c | 2 -- src/northbridge/intel/sandybridge/early_dmi.c | 1 - src/northbridge/intel/sandybridge/early_init.c | 4 ---- src/northbridge/intel/sandybridge/finalize.c | 1 - src/northbridge/intel/sandybridge/gma.c | 1 - src/northbridge/intel/sandybridge/gma.h | 1 - src/northbridge/intel/sandybridge/memmap.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 2 -- src/northbridge/intel/sandybridge/pcie.c | 1 - src/northbridge/intel/sandybridge/raminit.c | 3 --- src/northbridge/intel/sandybridge/raminit.h | 1 - src/northbridge/intel/sandybridge/raminit_common.c | 3 --- src/northbridge/intel/sandybridge/raminit_common.h | 3 --- src/northbridge/intel/sandybridge/raminit_ivy.c | 3 --- src/northbridge/intel/sandybridge/raminit_mrc.c | 1 - src/northbridge/intel/sandybridge/raminit_native.h | 1 - src/northbridge/intel/sandybridge/raminit_sandy.c | 3 --- src/northbridge/intel/sandybridge/romstage.c | 3 --- src/northbridge/intel/sandybridge/sandybridge.h | 2 -- src/northbridge/intel/x4x/Kconfig | 2 -- src/northbridge/intel/x4x/Makefile.inc | 2 -- src/northbridge/intel/x4x/acpi.c | 2 -- src/northbridge/intel/x4x/acpi/hostbridge.asl | 2 -- src/northbridge/intel/x4x/acpi/peg.asl | 2 -- src/northbridge/intel/x4x/acpi/x4x.asl | 2 -- src/northbridge/intel/x4x/bootblock.c | 1 - src/northbridge/intel/x4x/chip.h | 1 - src/northbridge/intel/x4x/dq_dqs.c | 1 - src/northbridge/intel/x4x/early_init.c | 2 -- src/northbridge/intel/x4x/gma.c | 3 --- src/northbridge/intel/x4x/iomap.h | 1 - src/northbridge/intel/x4x/memmap.c | 2 -- src/northbridge/intel/x4x/northbridge.c | 2 -- src/northbridge/intel/x4x/raminit.c | 1 - src/northbridge/intel/x4x/raminit_ddr23.c | 1 - src/northbridge/intel/x4x/raminit_tables.c | 1 - src/northbridge/intel/x4x/rcven.c | 2 -- src/northbridge/intel/x4x/x4x.h | 3 --- src/security/Kconfig | 1 - src/security/intel/Kconfig | 2 -- src/security/intel/txt/Kconfig | 2 -- src/security/memory/Kconfig | 2 -- src/security/memory/memory.c | 2 -- src/security/memory/memory.h | 2 -- src/security/memory/memory_clear.c | 2 -- src/security/tpm/Kconfig | 2 -- src/security/tpm/tis.h | 1 - src/security/tpm/tspi.h | 3 --- src/security/tpm/tspi/log.c | 1 - src/security/tpm/tspi/tspi.c | 3 --- src/security/tpm/tss/common/tss_common.h | 2 -- src/security/tpm/tss/tcg-1.2/tss_commands.h | 2 -- src/security/tpm/tss/vendor/cr50/Kconfig | 2 -- src/security/tpm/tss/vendor/cr50/cr50.h | 2 -- src/security/vboot/Kconfig | 2 -- src/security/vboot/Makefile.inc | 2 -- src/security/vboot/bootmode.c | 1 - src/security/vboot/common.c | 1 - src/security/vboot/misc.h | 1 - src/security/vboot/mrc_cache_hash_tpm.c | 4 ---- src/security/vboot/symbols.h | 1 - src/security/vboot/vbnv.c | 1 - src/security/vboot/vbnv.h | 1 - src/security/vboot/vbnv_cmos.c | 1 - src/security/vboot/vbnv_ec.c | 1 - src/security/vboot/vbnv_flash.c | 1 - src/security/vboot/vbnv_layout.h | 1 - src/security/vboot/vboot_common.c | 1 - src/security/vboot/vboot_common.h | 1 - src/security/vboot/vboot_crtm.c | 1 - src/security/vboot/vboot_crtm.h | 1 - src/security/vboot/vboot_loader.c | 1 - src/security/vboot/vboot_logic.c | 1 - src/security/vboot/verstage.c | 1 - src/southbridge/amd/agesa/Kconfig | 1 - src/southbridge/amd/agesa/Makefile.inc | 1 - src/southbridge/amd/agesa/hudson/Kconfig | 1 - src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl | 1 - src/southbridge/amd/agesa/hudson/acpi/audio.asl | 1 - src/southbridge/amd/agesa/hudson/acpi/fch.asl | 2 -- src/southbridge/amd/agesa/hudson/acpi/lpc.asl | 1 - src/southbridge/amd/agesa/hudson/acpi/pci_int.asl | 1 - src/southbridge/amd/agesa/hudson/acpi/pcie.asl | 1 - src/southbridge/amd/agesa/hudson/acpi/usb.asl | 1 - src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 1 - src/southbridge/amd/agesa/hudson/amd_pci_int_types.h | 1 - src/southbridge/amd/agesa/hudson/bootblock.c | 1 - src/southbridge/amd/agesa/hudson/chip.h | 1 - src/southbridge/amd/agesa/hudson/early_setup.c | 1 - src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 1 - src/southbridge/amd/agesa/hudson/fadt.c | 1 - src/southbridge/amd/agesa/hudson/hda.c | 1 - src/southbridge/amd/agesa/hudson/hudson.c | 1 - src/southbridge/amd/agesa/hudson/hudson.h | 2 -- src/southbridge/amd/agesa/hudson/ide.c | 1 - src/southbridge/amd/agesa/hudson/imc.c | 1 - src/southbridge/amd/agesa/hudson/imc.h | 1 - src/southbridge/amd/agesa/hudson/lpc.c | 2 -- src/southbridge/amd/agesa/hudson/pci.c | 2 -- src/southbridge/amd/agesa/hudson/pci_devs.h | 1 - src/southbridge/amd/agesa/hudson/pcie.c | 1 - src/southbridge/amd/agesa/hudson/ramtop.c | 1 - src/southbridge/amd/agesa/hudson/reset.c | 1 - src/southbridge/amd/agesa/hudson/resume.c | 1 - src/southbridge/amd/agesa/hudson/sata.c | 1 - src/southbridge/amd/agesa/hudson/sd.c | 1 - src/southbridge/amd/agesa/hudson/sm.c | 1 - src/southbridge/amd/agesa/hudson/smbus.c | 1 - src/southbridge/amd/agesa/hudson/smbus.h | 1 - src/southbridge/amd/agesa/hudson/smbus_spd.c | 1 - src/southbridge/amd/agesa/hudson/smi.c | 1 - src/southbridge/amd/agesa/hudson/smi.h | 1 - src/southbridge/amd/agesa/hudson/smi_util.c | 1 - src/southbridge/amd/agesa/hudson/smihandler.c | 1 - src/southbridge/amd/agesa/hudson/spi.c | 1 - src/southbridge/amd/agesa/hudson/usb.c | 1 - src/southbridge/amd/cimx/Kconfig | 1 - src/southbridge/amd/cimx/Makefile.inc | 1 - src/southbridge/amd/cimx/sb800/Amd.h | 1 - src/southbridge/amd/cimx/sb800/AmdSbLib.h | 1 - src/southbridge/amd/cimx/sb800/Kconfig | 1 - src/southbridge/amd/cimx/sb800/Makefile.inc | 1 - src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 1 - src/southbridge/amd/cimx/sb800/acpi/audio.asl | 1 - src/southbridge/amd/cimx/sb800/acpi/fch.asl | 1 - src/southbridge/amd/cimx/sb800/acpi/lpc.asl | 1 - src/southbridge/amd/cimx/sb800/acpi/pcie.asl | 1 - src/southbridge/amd/cimx/sb800/acpi/smbus.asl | 1 - src/southbridge/amd/cimx/sb800/acpi/usb.asl | 1 - src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h | 1 - src/southbridge/amd/cimx/sb800/amd_pci_int_types.h | 1 - src/southbridge/amd/cimx/sb800/bootblock.c | 1 - src/southbridge/amd/cimx/sb800/cfg.c | 1 - src/southbridge/amd/cimx/sb800/cfg.h | 1 - src/southbridge/amd/cimx/sb800/chip.h | 1 - src/southbridge/amd/cimx/sb800/early.c | 1 - src/southbridge/amd/cimx/sb800/fadt.c | 1 - src/southbridge/amd/cimx/sb800/fan.c | 1 - src/southbridge/amd/cimx/sb800/fan.h | 1 - src/southbridge/amd/cimx/sb800/late.c | 2 -- src/southbridge/amd/cimx/sb800/lpc.c | 2 -- src/southbridge/amd/cimx/sb800/lpc.h | 2 -- src/southbridge/amd/cimx/sb800/pci_devs.h | 1 - src/southbridge/amd/cimx/sb800/ramtop.c | 1 - src/southbridge/amd/cimx/sb800/reset.c | 1 - src/southbridge/amd/cimx/sb800/sb_cimx.h | 1 - src/southbridge/amd/cimx/sb800/smbus.c | 1 - src/southbridge/amd/cimx/sb800/smbus.h | 1 - src/southbridge/amd/cimx/sb800/smbus_spd.c | 1 - src/southbridge/amd/cimx/sb800/smbus_spd.h | 1 - src/southbridge/amd/cimx/sb800/spi.c | 1 - src/southbridge/amd/common/acpi/sleepstates.asl | 2 -- src/southbridge/amd/common/amd_defs.h | 1 - src/southbridge/amd/common/amd_pci_util.c | 1 - src/southbridge/amd/common/amd_pci_util.h | 1 - src/southbridge/amd/common/reset.h | 1 - src/southbridge/amd/pi/Kconfig | 1 - src/southbridge/amd/pi/Makefile.inc | 1 - src/southbridge/amd/pi/hudson/Kconfig | 1 - src/southbridge/amd/pi/hudson/Makefile.inc | 4 ---- src/southbridge/amd/pi/hudson/acpi/AmdImc.asl | 1 - src/southbridge/amd/pi/hudson/acpi/audio.asl | 1 - src/southbridge/amd/pi/hudson/acpi/fch.asl | 2 -- src/southbridge/amd/pi/hudson/acpi/lpc.asl | 1 - src/southbridge/amd/pi/hudson/acpi/pci_int.asl | 1 - src/southbridge/amd/pi/hudson/acpi/pcie.asl | 1 - src/southbridge/amd/pi/hudson/acpi/usb.asl | 1 - src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 1 - src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 1 - src/southbridge/amd/pi/hudson/bootblock.c | 1 - src/southbridge/amd/pi/hudson/chip.h | 1 - src/southbridge/amd/pi/hudson/early_setup.c | 1 - src/southbridge/amd/pi/hudson/enable_usbdebug.c | 1 - src/southbridge/amd/pi/hudson/fadt.c | 1 - src/southbridge/amd/pi/hudson/fchec.h | 1 - src/southbridge/amd/pi/hudson/gpio.c | 3 --- src/southbridge/amd/pi/hudson/gpio.h | 1 - src/southbridge/amd/pi/hudson/hda.c | 1 - src/southbridge/amd/pi/hudson/hudson.c | 1 - src/southbridge/amd/pi/hudson/hudson.h | 2 -- src/southbridge/amd/pi/hudson/ide.c | 1 - src/southbridge/amd/pi/hudson/imc.c | 1 - src/southbridge/amd/pi/hudson/imc.h | 1 - src/southbridge/amd/pi/hudson/lpc.c | 2 -- src/southbridge/amd/pi/hudson/pci.c | 2 -- src/southbridge/amd/pi/hudson/pci_devs.h | 1 - src/southbridge/amd/pi/hudson/pcie.c | 1 - src/southbridge/amd/pi/hudson/reset.c | 1 - src/southbridge/amd/pi/hudson/sata.c | 1 - src/southbridge/amd/pi/hudson/sd.c | 1 - src/southbridge/amd/pi/hudson/sm.c | 1 - src/southbridge/amd/pi/hudson/smbus.c | 1 - src/southbridge/amd/pi/hudson/smbus.h | 1 - src/southbridge/amd/pi/hudson/smbus_spd.c | 1 - src/southbridge/amd/pi/hudson/smi.c | 1 - src/southbridge/amd/pi/hudson/smi.h | 1 - src/southbridge/amd/pi/hudson/smi_util.c | 1 - src/southbridge/amd/pi/hudson/smihandler.c | 1 - src/southbridge/amd/pi/hudson/uart.c | 1 - src/southbridge/amd/pi/hudson/usb.c | 1 - src/southbridge/intel/bd82x6x/Kconfig | 1 - src/southbridge/intel/bd82x6x/Makefile.inc | 1 - src/southbridge/intel/bd82x6x/acpi/audio.asl | 1 - src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 2 -- src/southbridge/intel/bd82x6x/acpi/irqlinks.asl | 1 - src/southbridge/intel/bd82x6x/acpi/lpc.asl | 1 - src/southbridge/intel/bd82x6x/acpi/pch.asl | 1 - src/southbridge/intel/bd82x6x/acpi/sata.asl | 1 - src/southbridge/intel/bd82x6x/acpi/usb.asl | 1 - src/southbridge/intel/bd82x6x/azalia.c | 3 --- src/southbridge/intel/bd82x6x/bootblock.c | 1 - src/southbridge/intel/bd82x6x/chip.h | 1 - src/southbridge/intel/bd82x6x/early_me.c | 1 - src/southbridge/intel/bd82x6x/early_me_mrc.c | 1 - src/southbridge/intel/bd82x6x/early_pch.c | 1 - src/southbridge/intel/bd82x6x/early_rcba.c | 3 --- src/southbridge/intel/bd82x6x/early_smbus.c | 1 - src/southbridge/intel/bd82x6x/early_thermal.c | 1 - src/southbridge/intel/bd82x6x/early_usb.c | 1 - src/southbridge/intel/bd82x6x/early_usb_mrc.c | 1 - src/southbridge/intel/bd82x6x/elog.c | 1 - src/southbridge/intel/bd82x6x/lpc.c | 1 - src/southbridge/intel/bd82x6x/me.c | 1 - src/southbridge/intel/bd82x6x/me.h | 1 - src/southbridge/intel/bd82x6x/me_8.x.c | 1 - src/southbridge/intel/bd82x6x/me_status.c | 1 - src/southbridge/intel/bd82x6x/nvs.h | 2 -- src/southbridge/intel/bd82x6x/pch.c | 2 -- src/southbridge/intel/bd82x6x/pch.h | 2 -- src/southbridge/intel/bd82x6x/pci.c | 1 - src/southbridge/intel/bd82x6x/pcie.c | 1 - src/southbridge/intel/bd82x6x/sata.c | 1 - src/southbridge/intel/bd82x6x/smbus.c | 1 - src/southbridge/intel/bd82x6x/smihandler.c | 1 - src/southbridge/intel/bd82x6x/usb_ehci.c | 1 - src/southbridge/intel/bd82x6x/usb_xhci.c | 1 - src/southbridge/intel/common/Makefile.inc | 1 - src/southbridge/intel/common/acpi/pcie.asl | 2 -- src/southbridge/intel/common/acpi/pcie_port.asl | 1 - src/southbridge/intel/common/acpi/platform.asl | 1 - src/southbridge/intel/common/acpi/sleepstates.asl | 1 - src/southbridge/intel/common/acpi/smbus.asl | 1 - src/southbridge/intel/common/acpi_pirq_gen.c | 1 - src/southbridge/intel/common/acpi_pirq_gen.h | 1 - src/southbridge/intel/common/finalize.c | 1 - src/southbridge/intel/common/finalize.h | 1 - src/southbridge/intel/common/firmware/Kconfig | 2 -- src/southbridge/intel/common/firmware/Makefile.inc | 2 -- src/southbridge/intel/common/gpio.c | 1 - src/southbridge/intel/common/gpio.h | 1 - src/southbridge/intel/common/madt.c | 1 - src/southbridge/intel/common/pciehp.c | 1 - src/southbridge/intel/common/pmbase.c | 1 - src/southbridge/intel/common/pmbase.h | 1 - src/southbridge/intel/common/pmclib.c | 1 - src/southbridge/intel/common/pmclib.h | 1 - src/southbridge/intel/common/pmutil.c | 1 - src/southbridge/intel/common/pmutil.h | 1 - src/southbridge/intel/common/rcba.h | 2 -- src/southbridge/intel/common/rcba_pirq.c | 1 - src/southbridge/intel/common/rcba_pirq.h | 2 -- src/southbridge/intel/common/rtc.c | 1 - src/southbridge/intel/common/rtc.h | 1 - src/southbridge/intel/common/smbus.c | 4 ---- src/southbridge/intel/common/smi.c | 1 - src/southbridge/intel/common/smihandler.c | 1 - src/southbridge/intel/common/spi.c | 4 ---- src/southbridge/intel/common/tco.h | 1 - src/southbridge/intel/common/usb_debug.c | 1 - src/southbridge/intel/common/watchdog.c | 2 -- src/southbridge/intel/i82371eb/Makefile.inc | 1 - src/southbridge/intel/i82371eb/acpi/i82371eb.asl | 3 --- src/southbridge/intel/i82371eb/acpi/intx.asl | 1 - src/southbridge/intel/i82371eb/acpi/isabridge.asl | 2 -- src/southbridge/intel/i82371eb/acpi/pirq.asl | 1 - src/southbridge/intel/i82371eb/acpi_tables.c | 3 --- src/southbridge/intel/i82371eb/bootblock.c | 1 - src/southbridge/intel/i82371eb/chip.h | 1 - src/southbridge/intel/i82371eb/early_pm.c | 1 - src/southbridge/intel/i82371eb/early_smbus.c | 1 - src/southbridge/intel/i82371eb/fadt.c | 2 -- src/southbridge/intel/i82371eb/i82371eb.c | 1 - src/southbridge/intel/i82371eb/i82371eb.h | 1 - src/southbridge/intel/i82371eb/ide.c | 1 - src/southbridge/intel/i82371eb/isa.c | 1 - src/southbridge/intel/i82371eb/smbus.c | 4 ---- src/southbridge/intel/i82371eb/usb.c | 1 - src/southbridge/intel/i82371eb/wakeup.c | 1 - src/southbridge/intel/i82801dx/Kconfig | 1 - src/southbridge/intel/i82801dx/Makefile.inc | 1 - src/southbridge/intel/i82801dx/ac97.c | 1 - src/southbridge/intel/i82801dx/chip.h | 1 - src/southbridge/intel/i82801dx/early_smbus.c | 1 - src/southbridge/intel/i82801dx/i82801dx.c | 1 - src/southbridge/intel/i82801dx/i82801dx.h | 3 --- src/southbridge/intel/i82801dx/ide.c | 1 - src/southbridge/intel/i82801dx/lpc.c | 4 ---- src/southbridge/intel/i82801dx/nvs.h | 1 - src/southbridge/intel/i82801dx/pci.c | 1 - src/southbridge/intel/i82801dx/smi.c | 1 - src/southbridge/intel/i82801dx/smihandler.c | 1 - src/southbridge/intel/i82801dx/usb.c | 1 - src/southbridge/intel/i82801dx/usb2.c | 1 - src/southbridge/intel/i82801gx/Kconfig | 1 - src/southbridge/intel/i82801gx/Makefile.inc | 1 - src/southbridge/intel/i82801gx/ac97.c | 1 - src/southbridge/intel/i82801gx/acpi/ac97.asl | 1 - src/southbridge/intel/i82801gx/acpi/audio.asl | 1 - src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 1 - src/southbridge/intel/i82801gx/acpi/ich7.asl | 1 - src/southbridge/intel/i82801gx/acpi/irqlinks.asl | 1 - src/southbridge/intel/i82801gx/acpi/lpc.asl | 1 - src/southbridge/intel/i82801gx/acpi/pata.asl | 1 - src/southbridge/intel/i82801gx/acpi/pci.asl | 1 - src/southbridge/intel/i82801gx/acpi/sata.asl | 1 - src/southbridge/intel/i82801gx/acpi/usb.asl | 1 - src/southbridge/intel/i82801gx/azalia.c | 2 -- src/southbridge/intel/i82801gx/bootblock.c | 1 - src/southbridge/intel/i82801gx/chip.h | 1 - src/southbridge/intel/i82801gx/early_smbus.c | 1 - src/southbridge/intel/i82801gx/i82801gx.c | 1 - src/southbridge/intel/i82801gx/i82801gx.h | 1 - src/southbridge/intel/i82801gx/ide.c | 1 - src/southbridge/intel/i82801gx/lpc.c | 1 - src/southbridge/intel/i82801gx/nic.c | 1 - src/southbridge/intel/i82801gx/nvs.h | 1 - src/southbridge/intel/i82801gx/pci.c | 1 - src/southbridge/intel/i82801gx/pcie.c | 1 - src/southbridge/intel/i82801gx/sata.c | 2 -- src/southbridge/intel/i82801gx/sata.h | 1 - src/southbridge/intel/i82801gx/smbus.c | 1 - src/southbridge/intel/i82801gx/smihandler.c | 1 - src/southbridge/intel/i82801gx/usb.c | 1 - src/southbridge/intel/i82801gx/usb_ehci.c | 1 - src/southbridge/intel/i82801ix/Kconfig | 2 -- src/southbridge/intel/i82801ix/Makefile.inc | 2 -- src/southbridge/intel/i82801ix/acpi/audio.asl | 1 - src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 1 - src/southbridge/intel/i82801ix/acpi/ich9.asl | 1 - src/southbridge/intel/i82801ix/acpi/irqlinks.asl | 1 - src/southbridge/intel/i82801ix/acpi/lpc.asl | 1 - src/southbridge/intel/i82801ix/acpi/pci.asl | 1 - src/southbridge/intel/i82801ix/acpi/sata.asl | 1 - src/southbridge/intel/i82801ix/acpi/usb.asl | 1 - src/southbridge/intel/i82801ix/bootblock.c | 1 - src/southbridge/intel/i82801ix/chip.h | 2 -- src/southbridge/intel/i82801ix/dmi_setup.c | 1 - src/southbridge/intel/i82801ix/early_init.c | 1 - src/southbridge/intel/i82801ix/early_smbus.c | 2 -- src/southbridge/intel/i82801ix/hdaudio.c | 3 --- src/southbridge/intel/i82801ix/i82801ix.c | 3 --- src/southbridge/intel/i82801ix/i82801ix.h | 3 --- src/southbridge/intel/i82801ix/lpc.c | 2 -- src/southbridge/intel/i82801ix/nvs.h | 1 - src/southbridge/intel/i82801ix/pci.c | 1 - src/southbridge/intel/i82801ix/pcie.c | 2 -- src/southbridge/intel/i82801ix/sata.c | 2 -- src/southbridge/intel/i82801ix/smbus.c | 1 - src/southbridge/intel/i82801ix/smi.c | 1 - src/southbridge/intel/i82801ix/smihandler.c | 2 -- src/southbridge/intel/i82801ix/thermal.c | 2 -- src/southbridge/intel/i82801ix/usb_ehci.c | 1 - src/southbridge/intel/i82801jx/Kconfig | 2 -- src/southbridge/intel/i82801jx/Makefile.inc | 2 -- src/southbridge/intel/i82801jx/acpi/audio.asl | 1 - src/southbridge/intel/i82801jx/acpi/globalnvs.asl | 1 - src/southbridge/intel/i82801jx/acpi/ich10.asl | 1 - src/southbridge/intel/i82801jx/acpi/irqlinks.asl | 1 - src/southbridge/intel/i82801jx/acpi/lpc.asl | 1 - src/southbridge/intel/i82801jx/acpi/pci.asl | 1 - src/southbridge/intel/i82801jx/acpi/sata.asl | 1 - src/southbridge/intel/i82801jx/acpi/usb.asl | 1 - src/southbridge/intel/i82801jx/bootblock.c | 1 - src/southbridge/intel/i82801jx/chip.h | 2 -- src/southbridge/intel/i82801jx/early_smbus.c | 2 -- src/southbridge/intel/i82801jx/hdaudio.c | 3 --- src/southbridge/intel/i82801jx/i82801jx.c | 3 --- src/southbridge/intel/i82801jx/i82801jx.h | 3 --- src/southbridge/intel/i82801jx/lpc.c | 2 -- src/southbridge/intel/i82801jx/nvs.h | 1 - src/southbridge/intel/i82801jx/pci.c | 1 - src/southbridge/intel/i82801jx/pcie.c | 2 -- src/southbridge/intel/i82801jx/sata.c | 2 -- src/southbridge/intel/i82801jx/smbus.c | 1 - src/southbridge/intel/i82801jx/smihandler.c | 2 -- src/southbridge/intel/i82801jx/thermal.c | 2 -- src/southbridge/intel/i82801jx/usb_ehci.c | 1 - src/southbridge/intel/ibexpeak/Kconfig | 1 - src/southbridge/intel/ibexpeak/Makefile.inc | 1 - src/southbridge/intel/ibexpeak/azalia.c | 3 --- src/southbridge/intel/ibexpeak/bootblock.c | 1 - src/southbridge/intel/ibexpeak/chip.h | 1 - src/southbridge/intel/ibexpeak/early_pch.c | 3 --- src/southbridge/intel/ibexpeak/early_smbus.c | 1 - src/southbridge/intel/ibexpeak/early_thermal.c | 1 - src/southbridge/intel/ibexpeak/early_usb.c | 1 - src/southbridge/intel/ibexpeak/lpc.c | 2 -- src/southbridge/intel/ibexpeak/madt.c | 2 -- src/southbridge/intel/ibexpeak/me.c | 1 - src/southbridge/intel/ibexpeak/me.h | 1 - src/southbridge/intel/ibexpeak/nvs.h | 2 -- src/southbridge/intel/ibexpeak/pch.c | 2 -- src/southbridge/intel/ibexpeak/pch.h | 2 -- src/southbridge/intel/ibexpeak/sata.c | 2 -- src/southbridge/intel/ibexpeak/smbus.c | 1 - src/southbridge/intel/ibexpeak/smihandler.c | 1 - src/southbridge/intel/ibexpeak/thermal.c | 1 - src/southbridge/intel/ibexpeak/usb_ehci.c | 2 -- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 1 - src/southbridge/intel/lynxpoint/acpi.c | 2 -- src/southbridge/intel/lynxpoint/acpi/audio.asl | 1 - src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 2 -- src/southbridge/intel/lynxpoint/acpi/irqlinks.asl | 1 - src/southbridge/intel/lynxpoint/acpi/lpc.asl | 1 - src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl | 1 - src/southbridge/intel/lynxpoint/acpi/pch.asl | 1 - src/southbridge/intel/lynxpoint/acpi/sata.asl | 1 - src/southbridge/intel/lynxpoint/acpi/serialio.asl | 1 - src/southbridge/intel/lynxpoint/acpi/usb.asl | 1 - src/southbridge/intel/lynxpoint/azalia.c | 3 --- src/southbridge/intel/lynxpoint/bootblock.c | 1 - src/southbridge/intel/lynxpoint/chip.h | 1 - src/southbridge/intel/lynxpoint/early_me.c | 1 - src/southbridge/intel/lynxpoint/early_pch.c | 1 - src/southbridge/intel/lynxpoint/early_smbus.c | 1 - src/southbridge/intel/lynxpoint/early_usb.c | 1 - src/southbridge/intel/lynxpoint/elog.c | 1 - src/southbridge/intel/lynxpoint/hda_verb.c | 3 --- src/southbridge/intel/lynxpoint/hda_verb.h | 1 - src/southbridge/intel/lynxpoint/lp_gpio.c | 1 - src/southbridge/intel/lynxpoint/lp_gpio.h | 1 - src/southbridge/intel/lynxpoint/lpc.c | 2 -- src/southbridge/intel/lynxpoint/me.h | 1 - src/southbridge/intel/lynxpoint/me_9.x.c | 1 - src/southbridge/intel/lynxpoint/me_status.c | 1 - src/southbridge/intel/lynxpoint/nvs.h | 2 -- src/southbridge/intel/lynxpoint/pch.c | 2 -- src/southbridge/intel/lynxpoint/pch.h | 2 -- src/southbridge/intel/lynxpoint/pcie.c | 1 - src/southbridge/intel/lynxpoint/pmutil.c | 1 - src/southbridge/intel/lynxpoint/rcba.c | 1 - src/southbridge/intel/lynxpoint/sata.c | 1 - src/southbridge/intel/lynxpoint/serialio.c | 1 - src/southbridge/intel/lynxpoint/smbus.c | 1 - src/southbridge/intel/lynxpoint/smi.c | 1 - src/southbridge/intel/lynxpoint/smihandler.c | 2 -- src/southbridge/intel/lynxpoint/usb_ehci.c | 1 - src/southbridge/intel/lynxpoint/usb_xhci.c | 1 - src/southbridge/ricoh/rl5c476/Kconfig | 1 - src/southbridge/ricoh/rl5c476/rl5c476.c | 1 - src/southbridge/ricoh/rl5c476/rl5c476.h | 1 - src/southbridge/ti/pci1x2x/pci1x2x.c | 1 - src/southbridge/ti/pci7420/Kconfig | 1 - src/southbridge/ti/pci7420/Makefile.inc | 1 - src/southbridge/ti/pci7420/cardbus.c | 1 - src/southbridge/ti/pci7420/chip.h | 1 - src/southbridge/ti/pci7420/firewire.c | 1 - src/southbridge/ti/pci7420/pci7420.h | 1 - src/southbridge/ti/pcixx12/Kconfig | 1 - src/southbridge/ti/pcixx12/Makefile.inc | 1 - src/southbridge/ti/pcixx12/pcixx12.c | 1 - src/vendorcode/amd/Kconfig | 1 - src/vendorcode/amd/agesa/common/Makefile.inc | 3 --- src/vendorcode/amd/agesa/f14/Makefile.inc | 3 --- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 3 --- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 3 --- src/vendorcode/amd/cimx/sb800/Makefile.inc | 2 -- src/vendorcode/amd/cimx/sb900/Makefile.inc | 2 -- src/vendorcode/amd/pi/00670F00/Makefile.inc | 4 ---- src/vendorcode/cavium/Kconfig | 1 - src/vendorcode/cavium/Makefile.inc | 1 - src/vendorcode/eltan/Makefile.inc | 1 - src/vendorcode/eltan/security/Kconfig | 1 - src/vendorcode/eltan/security/Makefile.inc | 1 - src/vendorcode/eltan/security/mboot/Kconfig | 1 - src/vendorcode/eltan/security/mboot/Makefile.inc | 1 - src/vendorcode/eltan/security/mboot/mboot.c | 2 -- src/vendorcode/eltan/security/mboot/mboot.h | 2 -- src/vendorcode/eltan/security/mboot/mboot_func.c | 1 - src/vendorcode/eltan/security/verified_boot/Kconfig | 1 - src/vendorcode/eltan/security/verified_boot/Makefile.inc | 1 - src/vendorcode/eltan/security/verified_boot/vboot_check.c | 2 -- src/vendorcode/eltan/security/verified_boot/vboot_check.h | 2 -- src/vendorcode/google/Kconfig | 1 - src/vendorcode/google/Makefile.inc | 1 - src/vendorcode/google/chromeos/Kconfig | 1 - src/vendorcode/google/chromeos/Makefile.inc | 1 - src/vendorcode/google/chromeos/acpi.c | 1 - src/vendorcode/google/chromeos/acpi/amac.asl | 1 - src/vendorcode/google/chromeos/acpi/chromeos.asl | 1 - src/vendorcode/google/chromeos/acpi/gnvs.asl | 1 - src/vendorcode/google/chromeos/acpi/ramoops.asl | 1 - src/vendorcode/google/chromeos/acpi/vpd.asl | 1 - src/vendorcode/google/chromeos/chromeos.h | 1 - src/vendorcode/google/chromeos/cr50_enable_update.c | 1 - src/vendorcode/google/chromeos/dsm_calib.c | 1 - src/vendorcode/google/chromeos/elog.c | 1 - src/vendorcode/google/chromeos/gnvs.c | 1 - src/vendorcode/google/chromeos/gnvs.h | 1 - src/vendorcode/google/chromeos/ramoops.c | 1 - src/vendorcode/google/chromeos/sar.c | 1 - src/vendorcode/google/chromeos/symbols.h | 1 - src/vendorcode/google/chromeos/tpm2.c | 1 - src/vendorcode/google/chromeos/vpd_calibration.c | 1 - src/vendorcode/google/chromeos/vpd_mac.c | 1 - src/vendorcode/google/chromeos/vpd_serialno.c | 1 - src/vendorcode/google/chromeos/watchdog.c | 1 - src/vendorcode/google/chromeos/wrdd.c | 2 -- src/vendorcode/google/smbios.c | 1 - src/vendorcode/intel/Kconfig | 2 -- src/vendorcode/intel/Makefile.inc | 2 -- src/vendorcode/siemens/Kconfig | 1 - src/vendorcode/siemens/Makefile.inc | 1 - src/vendorcode/siemens/hwilib/Makefile.inc | 1 - src/vendorcode/siemens/hwilib/hwilib.c | 1 - src/vendorcode/siemens/hwilib/hwilib.h | 1 - 986 files changed, 1256 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index d92bfd6769..da21af1dd1 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Alexandru Gagniuc -## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/commonlib/include/commonlib/stdlib.h b/src/commonlib/include/commonlib/stdlib.h index 4a3671c7ab..9a9d44544e 100644 --- a/src/commonlib/include/commonlib/stdlib.h +++ b/src/commonlib/include/commonlib/stdlib.h @@ -1,8 +1,6 @@ /* * This file is part of the libpayload project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright 2013 Google Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 40c0e991a6..f7fd416d42 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -19,8 +19,6 @@ * such modified SOFTWARE should be clearly marked, so as not to confuse * it with the version available from LANL. * - * Copyright (C) 2000, Ron Minnich rminnich@lanl.gov - * Advanced Computing Lab, LANL */ diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index f726fab506..81a9bab33c 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2019 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S index f9d056e599..89b0609117 100644 --- a/src/drivers/amd/agesa/exit_car.S +++ b/src/drivers/amd/agesa/exit_car.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/analogix/anx7625/Kconfig b/src/drivers/analogix/anx7625/Kconfig index 196ae1123b..a172d940e4 100644 --- a/src/drivers/analogix/anx7625/Kconfig +++ b/src/drivers/analogix/anx7625/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2019 Analogix Semiconductor. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/drivers/analogix/anx7625/Makefile.inc b/src/drivers/analogix/anx7625/Makefile.inc index 9a46338cd4..068225a43a 100644 --- a/src/drivers/analogix/anx7625/Makefile.inc +++ b/src/drivers/analogix/anx7625/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2019 Analogix Semiconductor. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 9387a83bd9..e8e5bf583c 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Analogix Semiconductor. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h index 361ab13b4b..c0b33b2eea 100644 --- a/src/drivers/analogix/anx7625/anx7625.h +++ b/src/drivers/analogix/anx7625/anx7625.h @@ -1,9 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. - * - */ - #include #include diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index 1c44026a43..eb52da0783 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Red Hat Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 0a26a9c922..d84678d05a 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Red Hat Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index d4ee8b45dd..d9c2d2db27 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Red Hat Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 27b01725b5..9b91b2b981 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2005 ASPEED Technology Inc. * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index 714a8aba84..258cda9c5c 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 0b3fccafde..9e952e8571 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index ef25745ed1..2345136108 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/i2c/ptn3460/ptn3460.h b/src/drivers/i2c/ptn3460/ptn3460.h index f8242f8aef..d91386035d 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.h +++ b/src/drivers/i2c/ptn3460/ptn3460.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/i2c/rt1011/chip.h b/src/drivers/i2c/rt1011/chip.h index 6bbddac3fd..fa759edc43 100644 --- a/src/drivers/i2c/rt1011/chip.h +++ b/src/drivers/i2c/rt1011/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index 792992e355..8dc3cd9bb0 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 43ee6b3a35..590e606424 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Wiwynn Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index a53929a29a..ef9319204e 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Wiwynn Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index dd12786b8e..cbd9657558 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -3,7 +3,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Wiwynn Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index c2f8da6ff4..3c70915c6c 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/drivers/uart/pl011.h b/src/drivers/uart/pl011.h index 2568dbcb80..ddc36d321b 100644 --- a/src/drivers/uart/pl011.h +++ b/src/drivers/uart/pl011.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright 2018-present Facebook, Inc. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/src/ec/acpi/ec.asl b/src/ec/acpi/ec.asl index 6b04f304ed..f5b574b196 100644 --- a/src/ec/acpi/ec.asl +++ b/src/ec/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 939ff781fa..24926a7073 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h index 86fa4e55d5..125ee61a9a 100644 --- a/src/ec/acpi/ec.h +++ b/src/ec/acpi/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/compal/ene932/acpi/ac.asl b/src/ec/compal/ene932/acpi/ac.asl index 8db53d4c3d..88330ea8fc 100644 --- a/src/ec/compal/ene932/acpi/ac.asl +++ b/src/ec/compal/ene932/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl index f86cb0169e..878bcda0ac 100644 --- a/src/ec/compal/ene932/acpi/battery.asl +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 7caf8d4b62..4db43f6e87 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index 034f6ded94..21d291683e 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/compal/ene932/chip.h b/src/ec/compal/ene932/chip.h index 94f975282b..8dedfee83a 100644 --- a/src/ec/compal/ene932/chip.h +++ b/src/ec/compal/ene932/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 5bade10ea9..f6691cd692 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index 839bc45815..ba78cdde24 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/ec.h b/src/ec/ec.h index ea48f5b382..2787b3a752 100644 --- a/src/ec/ec.h +++ b/src/ec/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/ac.asl b/src/ec/google/chromeec/acpi/ac.asl index 47c401f90c..024d4a8ba6 100644 --- a/src/ec/google/chromeec/acpi/ac.asl +++ b/src/ec/google/chromeec/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/als.asl b/src/ec/google/chromeec/acpi/als.asl index 35468b2c37..26d682de50 100644 --- a/src/ec/google/chromeec/acpi/als.asl +++ b/src/ec/google/chromeec/acpi/als.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 025339540f..9cf3abd831 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index bcf38d2328..5e86a81c2b 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index fa5eca6321..95494eaba7 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 982ec5bf89..cbc125343c 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/keyboard_backlight.asl b/src/ec/google/chromeec/acpi/keyboard_backlight.asl index 1edce819d1..7cfbabe0d2 100644 --- a/src/ec/google/chromeec/acpi/keyboard_backlight.asl +++ b/src/ec/google/chromeec/acpi/keyboard_backlight.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/pd.asl b/src/ec/google/chromeec/acpi/pd.asl index 7b799e82ee..1509a9eef2 100644 --- a/src/ec/google/chromeec/acpi/pd.asl +++ b/src/ec/google/chromeec/acpi/pd.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index fc5fc8c266..a672c5c24e 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/acpi/tbmc.asl b/src/ec/google/chromeec/acpi/tbmc.asl index 86a6de86ba..639de4a2bc 100644 --- a/src/ec/google/chromeec/acpi/tbmc.asl +++ b/src/ec/google/chromeec/acpi/tbmc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 1c9a7f59e7..2b7170f00d 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index e2fa3ddd97..291cd94c49 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 3faa29778b..8f1f86407a 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 699d7c2793..60afb50522 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index db78bdb853..4dfd44bf4e 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 1307ce17b6..11b1675c51 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index dc012fcd9e..f5eb3513e7 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index ab0e3cd38a..4b97ff98d7 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index ac69b136ee..665d425fac 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index 84a605bf9c..f90b313d78 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index add0db3409..3738f24261 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/smm.h b/src/ec/google/chromeec/smm.h index 3d63a64bbf..4fe229203c 100644 --- a/src/ec/google/chromeec/smm.h +++ b/src/ec/google/chromeec/smm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 1eb2f2f6ef..080b3596e9 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c index f47c2f14e9..df9d39256e 100644 --- a/src/ec/google/chromeec/vboot_storage.c +++ b/src/ec/google/chromeec/vboot_storage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 50e964f27b..1e1a003adf 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/common/mec.c b/src/ec/google/common/mec.c index 06a6bca553..32bea3617b 100644 --- a/src/ec/google/common/mec.c +++ b/src/ec/google/common/mec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/common/mec.h b/src/ec/google/common/mec.h index 3452bada7a..2d3c9b5064 100644 --- a/src/ec/google/common/mec.h +++ b/src/ec/google/common/mec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/acpi/ac.asl b/src/ec/google/wilco/acpi/ac.asl index 5d51ce4639..a05b7fb9e3 100644 --- a/src/ec/google/wilco/acpi/ac.asl +++ b/src/ec/google/wilco/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/battery.asl b/src/ec/google/wilco/acpi/battery.asl index e03d3dd6b1..5e1e122ba6 100644 --- a/src/ec/google/wilco/acpi/battery.asl +++ b/src/ec/google/wilco/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index 42fc9fdeed..b13ea9c2ce 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index fddd730258..a04def1e52 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/ec_dev.asl b/src/ec/google/wilco/acpi/ec_dev.asl index 634e243075..190b36c5d3 100644 --- a/src/ec/google/wilco/acpi/ec_dev.asl +++ b/src/ec/google/wilco/acpi/ec_dev.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index af8fc0effc..764341a0ac 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 8f6a12333d..828c554d98 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl index 1697e1da5a..1412b998ee 100644 --- a/src/ec/google/wilco/acpi/lid.asl +++ b/src/ec/google/wilco/acpi/lid.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/platform.asl b/src/ec/google/wilco/acpi/platform.asl index 802c8f780f..fc276cbbe0 100644 --- a/src/ec/google/wilco/acpi/platform.asl +++ b/src/ec/google/wilco/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/privacy.asl b/src/ec/google/wilco/acpi/privacy.asl index 5c620b0fca..b1a7f2fc88 100644 --- a/src/ec/google/wilco/acpi/privacy.asl +++ b/src/ec/google/wilco/acpi/privacy.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl index 42575bd654..7567408bc7 100644 --- a/src/ec/google/wilco/acpi/superio.asl +++ b/src/ec/google/wilco/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/acpi/ucsi.asl b/src/ec/google/wilco/acpi/ucsi.asl index 0d2c5a6336..2c5b2473ec 100644 --- a/src/ec/google/wilco/acpi/ucsi.asl +++ b/src/ec/google/wilco/acpi/ucsi.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/acpi/vbtn.asl b/src/ec/google/wilco/acpi/vbtn.asl index 201ab51002..7346455b56 100644 --- a/src/ec/google/wilco/acpi/vbtn.asl +++ b/src/ec/google/wilco/acpi/vbtn.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/google/wilco/boardid.c b/src/ec/google/wilco/boardid.c index 2a7e5755ea..17412128e6 100644 --- a/src/ec/google/wilco/boardid.c +++ b/src/ec/google/wilco/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/bootblock.c b/src/ec/google/wilco/bootblock.c index daf2d7f6c1..aaa555b69d 100644 --- a/src/ec/google/wilco/bootblock.c +++ b/src/ec/google/wilco/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/bootblock.h b/src/ec/google/wilco/bootblock.h index 8130dd76b7..03b475ae15 100644 --- a/src/ec/google/wilco/bootblock.h +++ b/src/ec/google/wilco/bootblock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 5729b4aa27..e1181eee87 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/chip.h b/src/ec/google/wilco/chip.h index 06d889c108..c79b5a175e 100644 --- a/src/ec/google/wilco/chip.h +++ b/src/ec/google/wilco/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index 791141e814..99cae75035 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 3d2ae46fae..de95f610a5 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/ec.h b/src/ec/google/wilco/ec.h index c46acdc0aa..ab649b19ec 100644 --- a/src/ec/google/wilco/ec.h +++ b/src/ec/google/wilco/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/mailbox.c b/src/ec/google/wilco/mailbox.c index 3414c4af14..54bdc7f2fc 100644 --- a/src/ec/google/wilco/mailbox.c +++ b/src/ec/google/wilco/mailbox.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/romstage.c b/src/ec/google/wilco/romstage.c index 4f5eef2aeb..63229dcc04 100644 --- a/src/ec/google/wilco/romstage.c +++ b/src/ec/google/wilco/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/romstage.h b/src/ec/google/wilco/romstage.h index fbbbdc428e..bfb9dcd4f2 100644 --- a/src/ec/google/wilco/romstage.h +++ b/src/ec/google/wilco/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/smihandler.c b/src/ec/google/wilco/smihandler.c index e127434726..b325596397 100644 --- a/src/ec/google/wilco/smihandler.c +++ b/src/ec/google/wilco/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/google/wilco/smm.h b/src/ec/google/wilco/smm.h index 692cdef2fe..f0bdd7195a 100644 --- a/src/ec/google/wilco/smm.h +++ b/src/ec/google/wilco/smm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index eb6bd90077..c7157fcd78 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Iru Cai ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index a70a223d24..bff48cbf52 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Iru Cai ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/ec/hp/kbc1126/acpi/ac.asl b/src/ec/hp/kbc1126/acpi/ac.asl index 3a80f8dedb..76ff3e0884 100644 --- a/src/ec/hp/kbc1126/acpi/ac.asl +++ b/src/ec/hp/kbc1126/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/hp/kbc1126/acpi/battery.asl b/src/ec/hp/kbc1126/acpi/battery.asl index 0cc98544ce..97feeaa5db 100644 --- a/src/ec/hp/kbc1126/acpi/battery.asl +++ b/src/ec/hp/kbc1126/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/hp/kbc1126/acpi/ec.asl b/src/ec/hp/kbc1126/acpi/ec.asl index 6e636ed3ff..5854470450 100644 --- a/src/ec/hp/kbc1126/acpi/ec.asl +++ b/src/ec/hp/kbc1126/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/hp/kbc1126/acpi/lid.asl b/src/ec/hp/kbc1126/acpi/lid.asl index c123c4c1f1..2bdca8917e 100644 --- a/src/ec/hp/kbc1126/acpi/lid.asl +++ b/src/ec/hp/kbc1126/acpi/lid.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/hp/kbc1126/chip.h b/src/ec/hp/kbc1126/chip.h index 009aa6bd06..d3c9421ab6 100644 --- a/src/ec/hp/kbc1126/chip.h +++ b/src/ec/hp/kbc1126/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/hp/kbc1126/early_init.c b/src/ec/hp/kbc1126/early_init.c index 844794e9b2..2123820598 100644 --- a/src/ec/hp/kbc1126/early_init.c +++ b/src/ec/hp/kbc1126/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index a3e6e9c69c..8b8b92c6f3 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/hp/kbc1126/ec.h b/src/ec/hp/kbc1126/ec.h index 372f2a13e9..2a7cc531c6 100644 --- a/src/ec/hp/kbc1126/ec.h +++ b/src/ec/hp/kbc1126/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/it8516e/acpi/ec.asl b/src/ec/kontron/it8516e/acpi/ec.asl index 66ae001f0f..170077be78 100644 --- a/src/ec/kontron/it8516e/acpi/ec.asl +++ b/src/ec/kontron/it8516e/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/it8516e/acpi/pm_channels.asl b/src/ec/kontron/it8516e/acpi/pm_channels.asl index 2c97de8c75..fc6b4bba06 100644 --- a/src/ec/kontron/it8516e/acpi/pm_channels.asl +++ b/src/ec/kontron/it8516e/acpi/pm_channels.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/it8516e/chip.h b/src/ec/kontron/it8516e/chip.h index 09b2e44592..6034c46585 100644 --- a/src/ec/kontron/it8516e/chip.h +++ b/src/ec/kontron/it8516e/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index ca695b3378..cabac234cd 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/it8516e/ec.h b/src/ec/kontron/it8516e/ec.h index 83e96d1f41..9e6171c2dd 100644 --- a/src/ec/kontron/it8516e/ec.h +++ b/src/ec/kontron/it8516e/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h index 7f0693782a..597f281ca1 100644 --- a/src/ec/kontron/kempld/chip.h +++ b/src/ec/kontron/kempld/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/kontron/kempld/early_kempld.c b/src/ec/kontron/kempld/early_kempld.c index 44eea187a8..c47274669f 100644 --- a/src/ec/kontron/kempld/early_kempld.c +++ b/src/ec/kontron/kempld/early_kempld.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c index b87238b649..6f2b2689bf 100644 --- a/src/ec/kontron/kempld/kempld.c +++ b/src/ec/kontron/kempld/kempld.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/kempld/kempld.h b/src/ec/kontron/kempld/kempld.h index fe5f54f02a..6e5000a5b1 100644 --- a/src/ec/kontron/kempld/kempld.h +++ b/src/ec/kontron/kempld/kempld.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/kontron/kempld/kempld_internal.h b/src/ec/kontron/kempld/kempld_internal.h index 93351ce772..4f90f45808 100644 --- a/src/ec/kontron/kempld/kempld_internal.h +++ b/src/ec/kontron/kempld/kempld_internal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/acpi/ac.asl b/src/ec/lenovo/h8/acpi/ac.asl index 43b43d7e78..d67bfbc062 100644 --- a/src/ec/lenovo/h8/acpi/ac.asl +++ b/src/ec/lenovo/h8/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 5f97ed9dc5..79773c9d80 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/beep.asl b/src/ec/lenovo/h8/acpi/beep.asl index 0a2371f4a9..7f385c6a47 100644 --- a/src/ec/lenovo/h8/acpi/beep.asl +++ b/src/ec/lenovo/h8/acpi/beep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 5a116818df..893732f56d 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle - * Copyright (c) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index c9142f5ff9..5c21744d3d 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl index 2f36c4b229..184829d713 100644 --- a/src/ec/lenovo/h8/acpi/sleepbutton.asl +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/systemstatus.asl b/src/ec/lenovo/h8/acpi/systemstatus.asl index 378ce01c9b..11b42a86da 100644 --- a/src/ec/lenovo/h8/acpi/systemstatus.asl +++ b/src/ec/lenovo/h8/acpi/systemstatus.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index 7f592c1bbf..eb49511f2e 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl index 519e64b245..92d4a31f84 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2017 Arthur Heymans - * Copyright (c) 2018 Evgeny Zinoviev * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl index 52176490f4..438ac91277 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2017 Arthur Heymans - * Copyright (c) 2018 Evgeny Zinoviev * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl index 88a66f0e4a..260bd8e95f 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2017 Arthur Heymans - * Copyright (c) 2018 Evgeny Zinoviev * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c index 436b319084..aba6ec1d6b 100644 --- a/src/ec/lenovo/h8/bluetooth.c +++ b/src/ec/lenovo/h8/bluetooth.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 25512bc3b3..665cbdf38d 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index ed46a3f659..cafbe645b4 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 6dad2889ad..9e2cfa044d 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/panic.c b/src/ec/lenovo/h8/panic.c index 4981b861db..23eda97e17 100644 --- a/src/ec/lenovo/h8/panic.c +++ b/src/ec/lenovo/h8/panic.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/sense.c b/src/ec/lenovo/h8/sense.c index b929d7ede3..d0f07fd642 100644 --- a/src/ec/lenovo/h8/sense.c +++ b/src/ec/lenovo/h8/sense.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/ssdt.c b/src/ec/lenovo/h8/ssdt.c index eccefe25ee..af041c3683 100644 --- a/src/ec/lenovo/h8/ssdt.c +++ b/src/ec/lenovo/h8/ssdt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index 3b9f74a117..28ce6af617 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index e79cb61332..7aa996c772 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h index 46f74c1071..0bc83dedbf 100644 --- a/src/ec/lenovo/pmh7/chip.h +++ b/src/ec/lenovo/pmh7/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 42e5238c42..37a9351dfe 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index 313a560937..141c250c9c 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/purism/librem/acpi/ac.asl b/src/ec/purism/librem/acpi/ac.asl index 99d17ee104..08d6b6d47d 100644 --- a/src/ec/purism/librem/acpi/ac.asl +++ b/src/ec/purism/librem/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/purism/librem/acpi/battery.asl b/src/ec/purism/librem/acpi/battery.asl index 5a4891ee87..f2e3881351 100644 --- a/src/ec/purism/librem/acpi/battery.asl +++ b/src/ec/purism/librem/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index b564727614..e64770adb9 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/ene_kb3940q/acpi/ac.asl b/src/ec/quanta/ene_kb3940q/acpi/ac.asl index 8db53d4c3d..88330ea8fc 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ac.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl index dd9ba2ff99..dbfd477024 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/battery.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 70f1366859..0f66413e68 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl index 88dccc907a..86950f1e05 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/superio.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/quanta/ene_kb3940q/chip.h b/src/ec/quanta/ene_kb3940q/chip.h index b812a18b36..77357f3223 100644 --- a/src/ec/quanta/ene_kb3940q/chip.h +++ b/src/ec/quanta/ene_kb3940q/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 5de6336040..e37b980572 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h index b04809e0f7..5b278c114f 100644 --- a/src/ec/quanta/ene_kb3940q/ec.h +++ b/src/ec/quanta/ene_kb3940q/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/quanta/it8518/acpi/ac.asl b/src/ec/quanta/it8518/acpi/ac.asl index fb3a688f6b..64353295f3 100644 --- a/src/ec/quanta/it8518/acpi/ac.asl +++ b/src/ec/quanta/it8518/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 862e907772..fcfae755f2 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index 22c7352652..3a61d5d9cc 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/quanta/it8518/acpi/superio.asl b/src/ec/quanta/it8518/acpi/superio.asl index 8b93aa440e..8363fb9079 100644 --- a/src/ec/quanta/it8518/acpi/superio.asl +++ b/src/ec/quanta/it8518/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/quanta/it8518/chip.h b/src/ec/quanta/it8518/chip.h index 5dd14f6b29..67cf694f61 100644 --- a/src/ec/quanta/it8518/chip.h +++ b/src/ec/quanta/it8518/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 4853eb333f..593eddc194 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 6fca3b94fb..4cc88a3e37 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/Kconfig b/src/ec/roda/it8518/Kconfig index 452c34541e..9376a2a6d0 100644 --- a/src/ec/roda/it8518/Kconfig +++ b/src/ec/roda/it8518/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/Makefile.inc b/src/ec/roda/it8518/Makefile.inc index a0998880d9..bafe9d2c0e 100644 --- a/src/ec/roda/it8518/Makefile.inc +++ b/src/ec/roda/it8518/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/acpi/ac.asl b/src/ec/roda/it8518/acpi/ac.asl index 33c62ee8dd..359181c89e 100644 --- a/src/ec/roda/it8518/acpi/ac.asl +++ b/src/ec/roda/it8518/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/acpi/battery.asl b/src/ec/roda/it8518/acpi/battery.asl index ffe2c2f6e9..c18b9d3bf5 100644 --- a/src/ec/roda/it8518/acpi/battery.asl +++ b/src/ec/roda/it8518/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/acpi/ec.asl b/src/ec/roda/it8518/acpi/ec.asl index 94b00ce067..084d788cbd 100644 --- a/src/ec/roda/it8518/acpi/ec.asl +++ b/src/ec/roda/it8518/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/acpi/lid.asl b/src/ec/roda/it8518/acpi/lid.asl index f793838863..e218d76153 100644 --- a/src/ec/roda/it8518/acpi/lid.asl +++ b/src/ec/roda/it8518/acpi/lid.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/chip.h b/src/ec/roda/it8518/chip.h index 8091525e9b..a18d791795 100644 --- a/src/ec/roda/it8518/chip.h +++ b/src/ec/roda/it8518/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c index 09ff480a99..a9dfb0afae 100644 --- a/src/ec/roda/it8518/ec.c +++ b/src/ec/roda/it8518/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/smsc/mec1308/acpi/ac.asl b/src/ec/smsc/mec1308/acpi/ac.asl index a41d9492ef..c7aa5173f1 100644 --- a/src/ec/smsc/mec1308/acpi/ac.asl +++ b/src/ec/smsc/mec1308/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/smsc/mec1308/acpi/battery.asl b/src/ec/smsc/mec1308/acpi/battery.asl index 6c10225e05..4040be8f53 100644 --- a/src/ec/smsc/mec1308/acpi/battery.asl +++ b/src/ec/smsc/mec1308/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/smsc/mec1308/acpi/ec.asl b/src/ec/smsc/mec1308/acpi/ec.asl index a7a07393fa..f2b8f1c5d0 100644 --- a/src/ec/smsc/mec1308/acpi/ec.asl +++ b/src/ec/smsc/mec1308/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ec/smsc/mec1308/chip.h b/src/ec/smsc/mec1308/chip.h index 8df043c665..297e10855d 100644 --- a/src/ec/smsc/mec1308/chip.h +++ b/src/ec/smsc/mec1308/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index c6e282a015..2493f00e58 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/ec/smsc/mec1308/ec.h b/src/ec/smsc/mec1308/ec.h index feedfb915d..b143c51581 100644 --- a/src/ec/smsc/mec1308/ec.h +++ b/src/ec/smsc/mec1308/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/assert.h b/src/include/assert.h index e0db0bc05c..8f5af1f255 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/include/base3.h b/src/include/base3.h index 1c19274541..b14028a8d5 100644 --- a/src/include/base3.h +++ b/src/include/base3.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/bcd.h b/src/include/bcd.h index faf3b18a42..06dfb0349f 100644 --- a/src/include/bcd.h +++ b/src/include/bcd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/boardid.h b/src/include/boardid.h index a959b85367..26725c7a68 100644 --- a/src/include/boardid.h +++ b/src/include/boardid.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/boot_device.h b/src/include/boot_device.h index f392c10148..9f26c161f4 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index eb9c24c75d..04a22f6543 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 165f7da571..2763f1aa8b 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 3ae87461a9..258eba1660 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index af09922a5f..ef7b53eb8f 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/bootstate.h b/src/include/bootstate.h index c53884e944..bb2242bd59 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2fe2ce0f35..823368644b 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cbmem.h b/src/include/cbmem.h index cf79f41a71..a67c5b84da 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 38495a724d..42e05e75ad 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/console.h b/src/include/console/console.h index 9983cefd21..96fc8b5faf 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/flash.h b/src/include/console/flash.h index 6d678f76d0..51ac460f1c 100644 --- a/src/include/console/flash.h +++ b/src/include/console/flash.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 88590f8ddc..fe9e471d42 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 9877a5ea1f..a9094929c6 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Alexandru Gagniuc * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/spi.h b/src/include/console/spi.h index a425bf4ab3..29c500d769 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 162b1108a9..3e38bc8c7f 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/usb.h b/src/include/console/usb.h index ad57d522dc..e7871c404d 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index ebef43784c..f6e985c09d 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cper.h b/src/include/cper.h index 60cced5852..298fe28b24 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 0f88e516d1..d5804d6853 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 1303148025..74d5acc64a 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index af06dd1543..c4e15c5064 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2000 Ronald G. Minnich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 05d83ed341..26c74655be 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 0880ebb07d..191bf2e631 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 0331e27161..2b1418fcb8 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Eric W. Biederman * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 0339aa3937..e790a1bf85 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -2,7 +2,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 3ab45cd3c3..3a22deea76 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/x86/name.h b/src/include/cpu/x86/name.h index 98edb9e2ac..0b8ee92334 100644 --- a/src/include/cpu/x86/name.h +++ b/src/include/cpu/x86/name.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 72bae53d68..b188f63ddb 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 9elements Agency GmbH - * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 26496eebac..8abf5d5930 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index c0df5b0ce4..dacb8869c5 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/azalia.h b/src/include/device/azalia.h index 7abf8e8c06..c85be88077 100644 --- a/src/include/device/azalia.h +++ b/src/include/device/azalia.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index cbc5b4ec8e..00899f3c24 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 DMP Electronics Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index e5fb534551..5dc15e3e4c 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Alexandru Gagniuc - * Copyright (C) 2017 Patrick Rudolph * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 9bbbfe9652..1da9681169 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0f9373e220..51207e9999 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Alexandru Gagniuc * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index faa32995f8..4a371b5d67 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index d6ee15aa5a..d3637212f1 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index e3cc8921fd..3651d58cf2 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index e9a7776d46..a0e0269628 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index aa159705d1..e46d45da99 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 805c087de7..3757d3073b 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/spi.h b/src/include/device/spi.h index 4315ebce14..f8ccca1185 100644 --- a/src/include/device/spi.h +++ b/src/include/device/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/dimm_info_util.h b/src/include/dimm_info_util.h index fd13447c52..d6603ed60f 100644 --- a/src/include/dimm_info_util.h +++ b/src/include/dimm_info_util.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License version diff --git a/src/include/edid.h b/src/include/edid.h index a97b99b579..4d5839f7a3 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index 053d7133c4..70bd791855 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/elog.h b/src/include/elog.h index 8d1b3ba067..0b86e09d7a 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/fmap.h b/src/include/fmap.h index 9c974cea2e..e6f1d05740 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/gic.h b/src/include/gic.h index ab06fc2275..b37c2499b0 100644 --- a/src/include/gic.h +++ b/src/include/gic.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/gpio.h b/src/include/gpio.h index 0a37ee7087..e2de6a18de 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/halt.h b/src/include/halt.h index e2aa11cb6f..1c1cb26b46 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 The ChromiumOS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/include/imd.h b/src/include/imd.h index 6575312f3d..3d9ca1791f 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/lib.h b/src/include/lib.h index d1bbe93a37..f57221ca79 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Myles Watson * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/memlayout.h b/src/include/memlayout.h index e3aeec68b1..62c9f7b7aa 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/memrange.h b/src/include/memrange.h index ea3b118d41..cfd29e7079 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 498ecbf86c..1b4840e04f 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/nhlt.h b/src/include/nhlt.h index e4cfcf63fb..9ef95a6390 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index 21e47c2ece..6936d4bdaf 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/pc80/i8259.h b/src/include/pc80/i8259.h index 857c5c88b2..ef64f214fc 100644 --- a/src/include/pc80/i8259.h +++ b/src/include/pc80/i8259.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/pc80/vga.h b/src/include/pc80/vga.h index c8d1c9bccd..0e3d5f5895 100644 --- a/src/include/pc80/vga.h +++ b/src/include/pc80/vga.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 Luc Verhaegen * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/pc80/vga_io.h b/src/include/pc80/vga_io.h index c3141acff3..1f258c4f15 100644 --- a/src/include/pc80/vga_io.h +++ b/src/include/pc80/vga_io.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Luc Verhaegen * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/program_loading.h b/src/include/program_loading.h index d3930083c5..9e9b222993 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (C) 2014 Imagination Technologies - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/random.h b/src/include/random.h index cdb44151e0..a32a779034 100644 --- a/src/include/random.h +++ b/src/include/random.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 1d0c0d68dc..9759167b10 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/region_file.h b/src/include/region_file.h index 0b79be3687..baae9ea050 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/rmodule.h b/src/include/rmodule.h index bd202488a9..c066d7b0a8 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index db998ec3b2..481af804a6 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/rtc.h b/src/include/rtc.h index f006e7a5cd..2c0704ecf6 100644 --- a/src/include/rtc.h +++ b/src/include/rtc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/sar.h b/src/include/sar.h index 527a51a89d..3659e76fb1 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/sdram_mode.h b/src/include/sdram_mode.h index 78002b7031..763dd562b3 100644 --- a/src/include/sdram_mode.h +++ b/src/include/sdram_mode.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/smbios.h b/src/include/smbios.h index 129977636c..4e94fc45f2 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , - * Raptor Engineering - * Copyright (C) various authors, the coreboot project * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/smmstore.h b/src/include/smmstore.h index a535c5ba35..d367c2c767 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/spd.h b/src/include/spd.h index e9c23f2652..80d14c1685 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) 2006 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index fb771f2bf8..5027309b40 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h index c5b2763e86..086f3323be 100644 --- a/src/include/spd_ddr2.h +++ b/src/include/spd_ddr2.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/spi_bitbang.h b/src/include/spi_bitbang.h index 710fefb1bf..ac6924e223 100644 --- a/src/include/spi_bitbang.h +++ b/src/include/spi_bitbang.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h index ca0dd1d10a..ac91530279 100644 --- a/src/include/spi_sdcard.h +++ b/src/include/spi_sdcard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 3c7d9face0..f379bc51db 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index 8e753ea43b..171c38e14b 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Nico Huber - * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/symbols.h b/src/include/symbols.h index eec47010e4..94e4668ecb 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/thread.h b/src/include/thread.h index b66803e3c0..bd5750b2c2 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/timer.h b/src/include/timer.h index 3560966b0b..4fa24fb35a 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/timestamp.h b/src/include/timestamp.h index f20fc6800a..7c723698db 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/trace.h b/src/include/trace.h index aed69a8963..07b6570326 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/types.h b/src/include/types.h index ffb14c9db4..40209e0291 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/uuid.h b/src/include/uuid.h index b8827b0510..c8604bb3b0 100644 --- a/src/include/uuid.h +++ b/src/include/uuid.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010, Intel Corp. Huang Ying * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/wrdd.h b/src/include/wrdd.h index fea3e2fdda..a79046d06f 100644 --- a/src/include/wrdd.h +++ b/src/include/wrdd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2333f64468..085f6b2821 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2009 coresystems GmbH # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index e91a97f461..dfb4066198 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 386f4e38d7..0731a72069 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2010 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 0397594ef0..0fd5be0ac0 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Eric Biederman - * Copyright (C) 2005-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 06f6d05e47..1356333b15 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 8364afa0b9..f577e9eff0 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 7acfc224e5..b8f3d5cb61 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 secunet Security Networks AG - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index b018acb4fa..836406cbd6 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index f6a055e079..270bd63dc5 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index dd56f62392..f8a725471f 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index bd09697618..947a33f162 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Eric Biederman - * Copyright (C) 2005-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/lib/crc_byte.c b/src/lib/crc_byte.c index c04449d13f..55529a2346 100644 --- a/src/lib/crc_byte.c +++ b/src/lib/crc_byte.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index 947105920a..4b7cb975c5 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/lib/dimm_info_util.c b/src/lib/dimm_info_util.c index a45667ed25..84c0a05ee2 100644 --- a/src/lib/dimm_info_util.c +++ b/src/lib/dimm_info_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 466a65f53a..825a7f0439 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 83e9b8e901..9e2cadc24d 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Eric Biederman - * Copyright (C) 2005-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/fmap.c b/src/lib/fmap.c index c8843a7340..d004d8ed11 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012-2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/gcc.c b/src/lib/gcc.c index 5a93f45e34..b6208f5288 100644 --- a/src/lib/gcc.c +++ b/src/lib/gcc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index abeafa5546..48dc46d563 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google, Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index ebd04862bf..456cf58eca 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Nico Huber ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 8ea3b5eb8e..a453bc7417 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/halt.c b/src/lib/halt.c index 67ae2ee5e9..d5db09755e 100644 --- a/src/lib/halt.c +++ b/src/lib/halt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 The ChromiumOS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index eba5f12625..72e3376028 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/hw-time-timer.adb b/src/lib/hw-time-timer.adb index 643cc98610..e31b19ff62 100644 --- a/src/lib/hw-time-timer.adb +++ b/src/lib/hw-time-timer.adb @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2016 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/lib/imd.c b/src/lib/imd.c index 4fa8f7023b..2cfd3ec5fc 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 5be7dc46f5..ed98947fcc 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/jpeg.c b/src/lib/jpeg.c index e5b09ea709..47d3fe33c5 100644 --- a/src/lib/jpeg.c +++ b/src/lib/jpeg.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Michael Schroeder * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/lib/jpeg.h b/src/lib/jpeg.h index cc2c65ddc8..de9be5b9e9 100644 --- a/src/lib/jpeg.h +++ b/src/lib/jpeg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Michael Schroeder * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index b8bcd1c412..7fe20a1644 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/memrange.c b/src/lib/memrange.c index b9c09e8782..5fb40dfca7 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 5001c385c5..d65bfda55c 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/primitive_memtest.c b/src/lib/primitive_memtest.c index aa013772a8..2e23b45107 100644 --- a/src/lib/primitive_memtest.c +++ b/src/lib/primitive_memtest.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 178209c65d..8cc8e12edb 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index 2641ac6d05..52ed465c03 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/program.ld b/src/lib/program.ld index a9d4e48293..40bbb31e5a 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 299fd75028..baec94e342 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/region_file.c b/src/lib/region_file.c index 05d619c9a4..d847e9872a 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/reset.c b/src/lib/reset.c index 61163f13a3..feba3c2306 100644 --- a/src/lib/reset.c +++ b/src/lib/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 96cee8aad3..88ab06d8a4 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index 04ead0a83f..b4b817ed66 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/rtc.c b/src/lib/rtc.c index 3e4c3f77c3..8a807cef82 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 11fdff3ba1..eef857719e 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric W. Biederman - * Copyright (C) 2009 Ron Minnich - * Copyright (C) 2016 George Trudeau * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 47c6dbd7cb..df310f3e56 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/thread.c b/src/lib/thread.c index 281885ff9b..d61222da63 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/timer.c b/src/lib/timer.c index 19b423a398..ef097e68b4 100644 --- a/src/lib/timer.c +++ b/src/lib/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index 5eaaa936f6..bc5d782407 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 9cbe30807c..4dc6623869 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/trace.c b/src/lib/trace.c index 826fa3b671..b028bcacd0 100644 --- a/src/lib/trace.c +++ b/src/lib/trace.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c index 53c3fbbeee..859c550db2 100644 --- a/src/lib/wrdd.c +++ b/src/lib/wrdd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h index 42e9440314..d48a6c5d51 100644 --- a/src/northbridge/amd/agesa/BiosCallOuts.h +++ b/src/northbridge/amd/agesa/BiosCallOuts.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011,2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index e1e129a97d..19b62f2cd8 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 54418a9649..b1790897ce 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index a52b069d13..a8b3dcc5f4 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/dimmSpd.h b/src/northbridge/amd/agesa/dimmSpd.h index aaa6aa3d78..05b6ee3aa5 100644 --- a/src/northbridge/amd/agesa/dimmSpd.h +++ b/src/northbridge/amd/agesa/dimmSpd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 173714fa4c..96f75ca8d9 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index ad39325247..83ac7e534c 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 8130791cc9..72efeca1cf 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h index 211ee240ab..2f7110f69b 100644 --- a/src/northbridge/amd/agesa/family14/chip.h +++ b/src/northbridge/amd/agesa/family14/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 652555236a..778083f2a8 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index aba107bbcc..4086173d7e 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/pci_devs.h b/src/northbridge/amd/agesa/family14/pci_devs.h index 5076ede65d..e110831dc6 100644 --- a/src/northbridge/amd/agesa/family14/pci_devs.h +++ b/src/northbridge/amd/agesa/family14/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index b49dac0079..2c57283e54 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index a0841eb0d1..6c24f8774d 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index 9e9283c4be..d15703ec10 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index c360da6ecf..ce3715e4c1 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h index a5207086ea..1aae0bbfe8 100644 --- a/src/northbridge/amd/agesa/family15tn/chip.h +++ b/src/northbridge/amd/agesa/family15tn/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 30fd74bb72..aab815bb67 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 8bfd0b14fb..a7bf958865 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 074b4b9fbe..3519ab0e5b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h index 60834e4768..501fdcbd52 100644 --- a/src/northbridge/amd/agesa/family15tn/pci_devs.h +++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index dafb64c7eb..1346660425 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 2be2fd32c7..739668b639 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2014 Sage Electronic Engineering, LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index 3021ef48da..83ac7e534c 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index ce889c716a..cdfab58b04 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/chip.h b/src/northbridge/amd/agesa/family16kb/chip.h index 37b5cc106f..d5f4bb1021 100644 --- a/src/northbridge/amd/agesa/family16kb/chip.h +++ b/src/northbridge/amd/agesa/family16kb/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index 78dc128fe4..51081837a0 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 794428b077..96d71cdc18 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h index b2d02d8f33..9a1762200a 100644 --- a/src/northbridge/amd/agesa/family16kb/pci_devs.h +++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 7794f2d6b0..c10d4e66a1 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 6e86f535fc..057d404d67 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 9a529f0c4e..8eb3205ef3 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/Makefile.inc b/src/northbridge/amd/pi/00630F01/Makefile.inc index a188a91fad..a882b7ef2b 100644 --- a/src/northbridge/amd/pi/00630F01/Makefile.inc +++ b/src/northbridge/amd/pi/00630F01/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index ffe1367cdc..621efb526b 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/chip.h b/src/northbridge/amd/pi/00630F01/chip.h index 35b4a573c1..8ec10c6466 100644 --- a/src/northbridge/amd/pi/00630F01/chip.h +++ b/src/northbridge/amd/pi/00630F01/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index 845dad19a0..8dfba7b4ab 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/iommu.c b/src/northbridge/amd/pi/00630F01/iommu.c index 0154acefbd..77eea90769 100644 --- a/src/northbridge/amd/pi/00630F01/iommu.c +++ b/src/northbridge/amd/pi/00630F01/iommu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 2295cd6abc..2df105a4fb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00630F01/pci_devs.h b/src/northbridge/amd/pi/00630F01/pci_devs.h index 7db99768a0..74ad44a1ae 100644 --- a/src/northbridge/amd/pi/00630F01/pci_devs.h +++ b/src/northbridge/amd/pi/00630F01/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index c19ad14487..105fbc83db 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00660F01/Makefile.inc b/src/northbridge/amd/pi/00660F01/Makefile.inc index 7107d84a94..2fadfa9d08 100644 --- a/src/northbridge/amd/pi/00660F01/Makefile.inc +++ b/src/northbridge/amd/pi/00660F01/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 28e22244dd..464ecc621c 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00660F01/chip.h b/src/northbridge/amd/pi/00660F01/chip.h index ab0e3d20d5..611f692aa4 100644 --- a/src/northbridge/amd/pi/00660F01/chip.h +++ b/src/northbridge/amd/pi/00660F01/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index d25a35f795..d6a0b4d3c8 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 3e04ec3167..855936af79 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 441d8a1992..cdc974a900 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2014 Sage Electronic Engineering, LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index 33f2b79940..1af4e14a96 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index ce889c716a..cdfab58b04 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/chip.h b/src/northbridge/amd/pi/00730F01/chip.h index 3db79d4784..de11c20d2e 100644 --- a/src/northbridge/amd/pi/00730F01/chip.h +++ b/src/northbridge/amd/pi/00730F01/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index bbcac9079f..7b5f011764 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index 5ff631c405..a9f6f9772a 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index cf4d78b4a6..8f23e682e1 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Raptor Engineering, LLC - * Copyright (C) 2018 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/pci_devs.h b/src/northbridge/amd/pi/00730F01/pci_devs.h index 043902874f..280546d038 100644 --- a/src/northbridge/amd/pi/00730F01/pci_devs.h +++ b/src/northbridge/amd/pi/00730F01/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index 5cb77fc0fa..4a049e5cef 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 38ee5b32ab..74c993b4e7 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index 61917c9d48..c79a37f975 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/amd/pi/dimmSpd.h b/src/northbridge/amd/pi/dimmSpd.h index aaa6aa3d78..05b6ee3aa5 100644 --- a/src/northbridge/amd/pi/dimmSpd.h +++ b/src/northbridge/amd/pi/dimmSpd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index 1b01653a28..b056fa7d4c 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2012 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index faf91440e8..47add723cf 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index f506bf4894..4ce5bdcfda 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 69b055e96c..752af43ba1 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 20fdbbe32c..4334b0f75e 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 secunet Security Networks AG # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 6035b7ecf5..03daf7b9dc 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index a3f9e9071f..3a7e46487d 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index 22e2fdac5e..4bf47b35bb 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/acpi/peg.asl b/src/northbridge/intel/gm45/acpi/peg.asl index 227ca27004..6b9d47dd1e 100644 --- a/src/northbridge/intel/gm45/acpi/peg.asl +++ b/src/northbridge/intel/gm45/acpi/peg.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 150dd9b33d..6527181586 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 539d62c408..e54b0f6539 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index b5aa8044be..5d3278cb12 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5c28f533a9..3ee50b0374 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 1e6da69878..eed0b92d78 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Chromium OS Authors - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 28e93b858e..6681b2cc7e 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index b6e38e7e72..5d9f6ad1fc 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 33abc510a1..6855835eca 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index dd5a7e2a88..a0ff04fa25 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 4199274f3c..165336bf0e 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index d96bcf4528..33027bf8aa 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 90dfa92a60..6370e703e8 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c index b060b4fa47..4f86fd9e88 100644 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 8b1e29287d..6d40fd47d1 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 7c7f56dc1b..4e3b36268c 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index a146734158..b61774f5bb 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 1629a67b8d..7fa245d466 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 6dc4ef03d7..5e631cf025 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 73a20f2dfb..84424c2dff 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2010 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 02bc1bf2a7..ba86abe18e 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 2db72d7842..c0de8532fd 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index d567701cb7..7c33d20605 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl index c4af375422..bab9d18e8b 100644 --- a/src/northbridge/intel/haswell/acpi/peg.asl +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 27227916f6..cfc28845b2 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index ea563636f8..f61d609f8f 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 024d44e728..d067e0dafb 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index cf56c69539..eed6740bc3 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b45036ee33..695a39c57d 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/mchbar_regs.h index dfc0f7becf..701e1bf0be 100644 --- a/src/northbridge/intel/haswell/mchbar_regs.h +++ b/src/northbridge/intel/haswell/mchbar_regs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 2e8addef97..14d569b5bb 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index c59d02ed95..5a1e7a8ef9 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index d1b6ca730f..c8273a1e62 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index b3a21bfc3e..14fb12b0f9 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1eb4f4361b..40cb80f5f2 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index b42fcf87d6..b782d8396c 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index df3204753b..f7d77b7e98 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 010a6e7cb4..0161eb3020 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 57025859d3..708a41f6e8 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 89cca4d7de..054c8030a3 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 6e93e83d1a..3a2b3f4f4b 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 5c47ed0608..c4df33896d 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/northbridge.h b/src/northbridge/intel/i440bx/northbridge.h index 8df5666d4b..f42211e66a 100644 --- a/src/northbridge/intel/i440bx/northbridge.h +++ b/src/northbridge/intel/i440bx/northbridge.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 0a864e864a..e2db5e70ea 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 Uwe Hermann - * Copyright (C) 2010,2017 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 1e9f25b8be..dcc800713f 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index c22275a6b1..2abc201977 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 36dee6e571..bae0589619 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2009 coresystems GmbH # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 66f26dd9c5..97e7129bdf 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index db493eabac..d1497a4dda 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 50fabdc5de..777d03055e 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 68bd9b24ed..a017df35b4 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/i945/acpi/peg.asl b/src/northbridge/intel/i945/acpi/peg.asl index 227ca27004..6b9d47dd1e 100644 --- a/src/northbridge/intel/i945/acpi/peg.asl +++ b/src/northbridge/intel/i945/acpi/peg.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 2acbc57f3c..14d5e35e1a 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 44d25846c2..3a9766f93b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c index 4d8b999d46..ee77d93dc0 100644 --- a/src/northbridge/intel/i945/errata.c +++ b/src/northbridge/intel/i945/errata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 05855f3f13..f4d6aaf5c6 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 82f80ff725..11ea580291 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 83157d88ac..f528ec0af3 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 2242883186..a91efbf275 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a92118c338..134d11fbdc 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 26a1f5024b..56f96ce263 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 2768a61773..eebd492979 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 2333b7d79a..6d83d0fd31 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 512149bfee..638f295dc0 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc index 1fde37d9f6..29f22752a2 100644 --- a/src/northbridge/intel/ironlake/Makefile.inc +++ b/src/northbridge/intel/ironlake/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2010 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 198b6ecbc5..09d024a2b5 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index 2b26096be6..57d6ba0f82 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 659234b4aa..52fec1e731 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index dad03dac1b..84f8f62a38 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index fe4ad7feff..a349dcdc69 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index f76124be76..23771adc2d 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 27c0827ead..cba25aa64a 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Chromium OS Authors - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index aa8cb7f4a6..12166eb8ce 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index b2d61fe93a..e43fcde824 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google LLC - * Copyright (C) 2013 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 91bcc1170b..1af4a1ce63 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index e702e1749e..2f1ce066d3 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h index 1a55407d39..b4560373eb 100644 --- a/src/northbridge/intel/ironlake/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/raminit_tables.c b/src/northbridge/intel/ironlake/raminit_tables.c index 1bd73305ea..f06918c961 100644 --- a/src/northbridge/intel/ironlake/raminit_tables.c +++ b/src/northbridge/intel/ironlake/raminit_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/raminit_tables.h b/src/northbridge/intel/ironlake/raminit_tables.h index d912d6b18a..160c90b2fb 100644 --- a/src/northbridge/intel/ironlake/raminit_tables.h +++ b/src/northbridge/intel/ironlake/raminit_tables.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index fdd71b486a..e8e5c56ece 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 73060363f5..f7ffa87ead 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2015 Damien Zammit ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 81ee783304..2b633944bc 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2009 coresystems GmbH -# Copyright (C) 2015 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index c3e50ee86a..9501d65801 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 6b6ef4afe2..4de9302802 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/acpi/peg.asl b/src/northbridge/intel/pineview/acpi/peg.asl index 227ca27004..6b9d47dd1e 100644 --- a/src/northbridge/intel/pineview/acpi/peg.asl +++ b/src/northbridge/intel/pineview/acpi/peg.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index c7602e10f8..89c9fbf19c 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index c3969f26a4..4a50b1328f 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index db2bb825b7..0b04ade697 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Chromium OS Authors - * Copyright (C) 2013 Vladimir Serbinenko - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h index 9dd478f3db..fadd097f8b 100644 --- a/src/northbridge/intel/pineview/iomap.h +++ b/src/northbridge/intel/pineview/iomap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/mchbar_regs.h b/src/northbridge/intel/pineview/mchbar_regs.h index 2c83b02406..dc9a1f7ed6 100644 --- a/src/northbridge/intel/pineview/mchbar_regs.h +++ b/src/northbridge/intel/pineview/mchbar_regs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 2e6ed0d668..58dea581cd 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index cde2a2a681..727db82b09 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 41ef5d9628..42f9d0fd9e 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 9c887c98ab..18e1faa490 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h index dc8de74634..0bde7d8194 100644 --- a/src/northbridge/intel/pineview/raminit.h +++ b/src/northbridge/intel/pineview/raminit.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 9a8f5d50f6..f2dab268bb 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 06fdc4a0a9..7c16632072 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 7390d2b40b..5fb9fdbc9a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2010 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 9665972545..074e9413fa 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 8f35137a38..9dd6fc0782 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index afc24dfe85..4ebf74389a 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 0670c7b0a6..546dac92dd 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2017-2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 7dddb8abd0..5f5bf31f34 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index d141c998df..59972dc72d 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 6d41a2da96..99705bb358 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index e966095c84..10ac071f52 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2015 secunet Security Networks AG - * Copyright (C) 2011 Google Inc - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index e3383724cd..6a3156e4bc 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 19df8d4cc8..e6dfbc4548 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Chromium OS Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 5b10920f7d..899edbb1aa 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Chromium OS Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 0784c11313..03e8db6cd7 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index cc8a62ced1..eb102db933 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 618ee52c7b..258ade2de8 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 4ec8492b18..60217b4070 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Damien Zammit - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 4bc9de610e..1939c83095 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7136cd42d2..3c3546a65e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Damien Zammit - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 8aa3068df2..b1abf5e83a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Damien Zammit - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 8013636f92..a992d9c98c 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Damien Zammit - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index db5bffcb11..9e07e2ebaf 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 2a91772152..ecf13cf1f8 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 8417c2fea4..b5169e7525 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Damien Zammit - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 7d1c019207..81049e55c4 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ffc1d9f7fa..0bbb6fc6d2 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 247686ade3..8c0be74bf2 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2015 Damien Zammit ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index cde7121f93..9dd0cd85a5 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 secunet Security Networks AG -# Copyright (C) 2015 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index d25eb2b026..ddd26e865f 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index e3ea18c008..caa490c836 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/acpi/peg.asl b/src/northbridge/intel/x4x/acpi/peg.asl index 9406688cdd..d93ceb1fa5 100644 --- a/src/northbridge/intel/x4x/acpi/peg.asl +++ b/src/northbridge/intel/x4x/acpi/peg.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index a486808124..5f93b3eee3 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 0120132c78..ab5ddfd320 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/chip.h b/src/northbridge/intel/x4x/chip.h index 1fb54ccf86..28a95f5163 100644 --- a/src/northbridge/intel/x4x/chip.h +++ b/src/northbridge/intel/x4x/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index d48601d300..614fd05e64 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index fbcfadbd9c..8c9918e1ca 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 6956f87b4d..d43ddf9a36 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Chromium OS Authors - * Copyright (C) 2013 Vladimir Serbinenko - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h index 0d5ab64ec1..3dc01b64b7 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/iomap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 334e6c7a37..bcba561f80 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 0e28f56400..732d97ece3 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index df2d31ede9..f1dc8817e6 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 1e871c7600..237060ad48 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index b2b36ca7c8..5f23994355 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 36a6ebd259..ea5762188c 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index aaaa28aeac..9b86e74016 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/Kconfig b/src/security/Kconfig index 4e08bbd883..b967311345 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Facebook Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig index aa24e8ac68..01410371ba 100644 --- a/src/security/intel/Kconfig +++ b/src/security/intel/Kconfig @@ -1,7 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2019 9elements Agency GmbH -## Copyright (C) 2019 Facebook Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 7451cca728..04c2b6d4cb 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -1,7 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2019 9elements Agency GmbH -## Copyright (C) 2019 Facebook Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/memory/Kconfig b/src/security/memory/Kconfig index d84b80d382..29ca5c86e7 100644 --- a/src/security/memory/Kconfig +++ b/src/security/memory/Kconfig @@ -1,7 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Facebook Inc. -## Copyright (C) 2019 9elements Agency GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/memory/memory.c b/src/security/memory/memory.c index c815236c9c..f2c35c0431 100644 --- a/src/security/memory/memory.c +++ b/src/security/memory/memory.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 9elements Agency GmbH - * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/memory/memory.h b/src/security/memory/memory.h index ccb07d76ad..91638f4cc1 100644 --- a/src/security/memory/memory.h +++ b/src/security/memory/memory.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 9elements Agency GmbH - * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 255ddccfaa..d9d053d4b6 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 9elements Agency GmbH - * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index fbe1735707..1766939c4c 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -1,7 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (c) 2013 The Chromium OS Authors. All rights reserved. -## Copyright (C) 2018 Facebook Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index db7d92bfee..c5452e6032 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 55f883c481..6854401d03 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Copyright 2018 Facebook Inc. - * Copyright 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 8a9cc88827..068d78da19 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 5fcf92df65..0095183ca2 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Copyright 2017 Facebook Inc. - * Copyright 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tss/common/tss_common.h b/src/security/tpm/tss/common/tss_common.h index 47c9c29e05..5804cc400f 100644 --- a/src/security/tpm/tss/common/tss_common.h +++ b/src/security/tpm/tss/common/tss_common.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Copyright 2018 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tss/tcg-1.2/tss_commands.h b/src/security/tpm/tss/tcg-1.2/tss_commands.h index acdc8be713..5184ff97c1 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_commands.h +++ b/src/security/tpm/tss/tcg-1.2/tss_commands.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Copyright 2018 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tss/vendor/cr50/Kconfig b/src/security/tpm/tss/vendor/cr50/Kconfig index 4a2ad4f880..637669d3d2 100644 --- a/src/security/tpm/tss/vendor/cr50/Kconfig +++ b/src/security/tpm/tss/vendor/cr50/Kconfig @@ -1,7 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (c) 2013 The Chromium OS Authors. All rights reserved. -## Copyright (C) 2018 Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 6a160e0a23..55c3fd2fa0 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Copyright 2018 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index b6bf542ee6..6e0021d58d 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -1,7 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. -## Copyright (C) 2018 Siemens AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d0d3370c6d..e7560dd911 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. -## Copyright (C) 2018 Siemens AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 6cbb1160ca..9c4eb2bb36 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index ffd9353260..855406547e 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 97944d92a6..7e479678e1 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index d54f8f4618..0e9b9a865c 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Facebook Inc - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/symbols.h b/src/security/vboot/symbols.h index f286ad09bc..778c8ee949 100644 --- a/src/security/vboot/symbols.h +++ b/src/security/vboot/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index a5a780664c..5c0ff970a6 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index 12b939986b..0a582ff1f1 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index fe5d6ce922..56f207e243 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vbnv_ec.c b/src/security/vboot/vbnv_ec.c index d73423eb75..58f7d03f62 100644 --- a/src/security/vboot/vbnv_ec.c +++ b/src/security/vboot/vbnv_ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vbnv_flash.c b/src/security/vboot/vbnv_flash.c index 58d3aba2a7..7e44d62aae 100644 --- a/src/security/vboot/vbnv_flash.c +++ b/src/security/vboot/vbnv_flash.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index a3c2490c0d..4c320b1db0 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 3342524ad0..b5815abf5a 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 8be9d2ac8d..e9221288ad 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index f68ab0a4bc..40b56ed881 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2b40..ba3dd45abe 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 7e637759ce..4cf3eea35d 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index df2f00243b..b72df9650b 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/security/vboot/verstage.c b/src/security/vboot/verstage.c index ef0bd48850..1fa6a90741 100644 --- a/src/security/vboot/verstage.c +++ b/src/security/vboot/verstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/Kconfig b/src/southbridge/amd/agesa/Kconfig index 7162c27bff..432d90b8cd 100644 --- a/src/southbridge/amd/agesa/Kconfig +++ b/src/southbridge/amd/agesa/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index cf4d7908a3..fa33120f3e 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 96857b06f1..5e56db434f 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl index 19ea8f5f78..89189b8de9 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/acpi/audio.asl b/src/southbridge/amd/agesa/hudson/acpi/audio.asl index e35ae85510..bac56b0d50 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/audio.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 825e35464e..d77503281e 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl index 2044085793..adb98ffc89 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl index 52e9e28e39..17e1deaf57 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl index df299c1ffc..9faee36194 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl index cc07565795..0e0f982611 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index ee55be174f..9385088789 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 1b33a0c9c8..5fb231610a 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 2fa0da61e8..c8605fecd7 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h index 873d7fb92e..926f88f620 100644 --- a/src/southbridge/amd/agesa/hudson/chip.h +++ b/src/southbridge/amd/agesa/hudson/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 2e3ff303c9..c83fe535b8 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 47b5990a69..067ba9b880 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 425a084a07..4fe7f91458 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index 725bb0b951..3acbdf0fc4 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index d586d33f73..99f581f2e2 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 8a36ea2251..bd9250a42b 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c index aa2b66f8d5..69d95912d8 100644 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ b/src/southbridge/amd/agesa/hudson/ide.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 934d1e95da..9bc12eba9d 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h index 0fcc187a4e..434bd28226 100644 --- a/src/southbridge/amd/agesa/hudson/imc.h +++ b/src/southbridge/amd/agesa/hudson/imc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 9c65d04729..b6a8494362 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 5564533b76..e8f316a1dd 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index 3406051414..97892db9c9 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/pcie.c b/src/southbridge/amd/agesa/hudson/pcie.c index 9f7e84b6c8..b4329639ec 100644 --- a/src/southbridge/amd/agesa/hudson/pcie.c +++ b/src/southbridge/amd/agesa/hudson/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c index 2af95df034..33ffb9ae4c 100644 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index ff77eb87d3..c1043342d7 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index efc35bd8d1..7f2c06d21d 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index f6d3689231..2ca85913f3 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index 25acf0cc1f..0da763172f 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 07646c862c..ec10a41647 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index bc985e2300..8a97667c31 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 7bf29ad8d0..555210410f 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 9ddae38c5b..7adee8a399 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 7f76cd59d0..d59b03d003 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index b1156a8e1f..381391424b 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c index 80329541a8..d92f0b4b4e 100644 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index 1b60f18652..3f350ba5d1 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 9656027993..a2b5a559e5 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c index d6f38790f0..c634830064 100644 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ b/src/southbridge/amd/agesa/hudson/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 3e12327708..6fdd86fc58 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 6161c1493a..d6f50382ed 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index 066c4a3e9f..47afc33889 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -13,7 +13,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h index 10a88f2a47..82485b9b04 100644 --- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h @@ -3,7 +3,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index d62b638c30..e50f7391ac 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 2c516485f2..dcf2539c65 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 7ea2caa83b..596f711d4c 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -3,7 +3,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/acpi/audio.asl b/src/southbridge/amd/cimx/sb800/acpi/audio.asl index e51233a227..79490883f0 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/audio.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index b837b4cfc9..4c11644fc4 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl index 98d5aa53e8..7d602ba214 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index a9f588af09..c341e2335d 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index f88153a7e0..206ee05ce5 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/acpi/usb.asl b/src/southbridge/amd/cimx/sb800/acpi/usb.asl index e516903e42..a7a702d09c 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/usb.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h index 161fa521b5..e312d1fd6b 100644 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h index 300969ddde..d7072dcdd2 100644 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 6e0b54434c..45a861b297 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 921a4f239c..8d815366fa 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h index f546f7d710..b169648bf3 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.h +++ b/src/southbridge/amd/cimx/sb800/cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h index d848215e32..9bd0c54599 100644 --- a/src/southbridge/amd/cimx/sb800/chip.h +++ b/src/southbridge/amd/cimx/sb800/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 2ee4d40230..d5d0ab04dc 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 5a5643f413..08fbecb554 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index 42c13d74a7..2da6716901 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index 3734da10a0..b2a3556dc3 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 21c578fa30..f8773fcd10 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 79f402993f..cb2b266f95 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index b478eb40a7..f992e2d60e 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/pci_devs.h b/src/southbridge/amd/cimx/sb800/pci_devs.h index 5d57951efd..38faff6384 100644 --- a/src/southbridge/amd/cimx/sb800/pci_devs.h +++ b/src/southbridge/amd/cimx/sb800/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index 98d12c7101..76e5d674e1 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 787f7426ce..7ea6e6f9ab 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 6c924caed2..62d76a7e4d 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index a4426ff431..4e9f7b68e4 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h index 82db12a823..6bfb8e9ca4 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ b/src/southbridge/amd/cimx/sb800/smbus.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c index a574072388..e1bcb50615 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.h b/src/southbridge/amd/cimx/sb800/smbus_spd.h index c699ad0208..20d57c2917 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.h +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index fcb4fa1111..7e30e75ac5 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/common/acpi/sleepstates.asl b/src/southbridge/amd/common/acpi/sleepstates.asl index 9ee20b5dfa..8de2108e84 100644 --- a/src/southbridge/amd/common/acpi/sleepstates.asl +++ b/src/southbridge/amd/common/acpi/sleepstates.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/common/amd_defs.h b/src/southbridge/amd/common/amd_defs.h index 55db30f409..52f9ad72d6 100644 --- a/src/southbridge/amd/common/amd_defs.h +++ b/src/southbridge/amd/common/amd_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index b6d6308710..3cd725e74a 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index 0a3ce23a84..c665ace5d1 100644 --- a/src/southbridge/amd/common/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/common/reset.h b/src/southbridge/amd/common/reset.h index ce101cb2dc..006dd8c04d 100644 --- a/src/southbridge/amd/common/reset.h +++ b/src/southbridge/amd/common/reset.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/Kconfig b/src/southbridge/amd/pi/Kconfig index 531b460ea5..0b48d192cb 100644 --- a/src/southbridge/amd/pi/Kconfig +++ b/src/southbridge/amd/pi/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc index 5e0e3c3117..eb06873a32 100644 --- a/src/southbridge/amd/pi/Makefile.inc +++ b/src/southbridge/amd/pi/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 4884b73177..84031c16ed 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010-2016 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 9d985e6d7b..0ddba480dc 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -1,9 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016 Advanced Micro Devices, Inc. -# 2013 - 2014, Sage Electronic Engineering, LLC -# All rights reserved. -# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright diff --git a/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl b/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl index 19ea8f5f78..89189b8de9 100644 --- a/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl +++ b/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/acpi/audio.asl b/src/southbridge/amd/pi/hudson/acpi/audio.asl index e35ae85510..bac56b0d50 100644 --- a/src/southbridge/amd/pi/hudson/acpi/audio.asl +++ b/src/southbridge/amd/pi/hudson/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 4e1e7d1856..f0eb1fd1ec 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/acpi/lpc.asl b/src/southbridge/amd/pi/hudson/acpi/lpc.asl index 2578c153ba..001dd766cf 100644 --- a/src/southbridge/amd/pi/hudson/acpi/lpc.asl +++ b/src/southbridge/amd/pi/hudson/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl index 52e9e28e39..17e1deaf57 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/acpi/pcie.asl b/src/southbridge/amd/pi/hudson/acpi/pcie.asl index adb5c4d2bf..bffae17969 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl index 423c48a42a..914d9ae607 100644 --- a/src/southbridge/amd/pi/hudson/acpi/usb.asl +++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 448b85e72b..fd630ce13f 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index fc7a5d1cfd..5682e88e29 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index 6b7595fc0e..9b71c7d47e 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/chip.h b/src/southbridge/amd/pi/hudson/chip.h index 511b586cb4..9de5cd1856 100644 --- a/src/southbridge/amd/pi/hudson/chip.h +++ b/src/southbridge/amd/pi/hudson/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index fe75115233..9d04d2775d 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index 9ad03dcc75..8d9d7b8b22 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 61e046df0f..8573c8bf4c 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/fchec.h b/src/southbridge/amd/pi/hudson/fchec.h index b34f73371b..04d0610a4b 100644 --- a/src/southbridge/amd/pi/hudson/fchec.h +++ b/src/southbridge/amd/pi/hudson/fchec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/gpio.c b/src/southbridge/amd/pi/hudson/gpio.c index 8e3c969f3f..fc8e60bae3 100644 --- a/src/southbridge/amd/pi/hudson/gpio.c +++ b/src/southbridge/amd/pi/hudson/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/gpio.h b/src/southbridge/amd/pi/hudson/gpio.h index f07855d765..0e3785a872 100644 --- a/src/southbridge/amd/pi/hudson/gpio.h +++ b/src/southbridge/amd/pi/hudson/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 8bd54a8f62..49d1ddf9ff 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 51c37a1ca0..74020555a2 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6264319dd4..7c1044a006 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/ide.c b/src/southbridge/amd/pi/hudson/ide.c index aa2b66f8d5..69d95912d8 100644 --- a/src/southbridge/amd/pi/hudson/ide.c +++ b/src/southbridge/amd/pi/hudson/ide.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 3c6054d147..8ae0b084ec 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/imc.h b/src/southbridge/amd/pi/hudson/imc.h index 0fcc187a4e..434bd28226 100644 --- a/src/southbridge/amd/pi/hudson/imc.h +++ b/src/southbridge/amd/pi/hudson/imc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 6c3561f0c3..239dda8e74 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index c8e51b1a19..eec0180676 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 579dfaede2..7069fef55c 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/pcie.c b/src/southbridge/amd/pi/hudson/pcie.c index 9f7e84b6c8..b4329639ec 100644 --- a/src/southbridge/amd/pi/hudson/pcie.c +++ b/src/southbridge/amd/pi/hudson/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index ff77eb87d3..c1043342d7 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 08e967dd8e..58e0c57e5a 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index c22b988f53..01a23430ba 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 7ecb8df2ab..fd36a6fcf1 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c index bc985e2300..8a97667c31 100644 --- a/src/southbridge/amd/pi/hudson/smbus.c +++ b/src/southbridge/amd/pi/hudson/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index ac197a3c6b..2a78ef5f2a 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index 8523db5054..d8910fd2c0 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 7f76cd59d0..d59b03d003 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index 4faee1512f..dde0fb928d 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index 80329541a8..d92f0b4b4e 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 1b60f18652..3f350ba5d1 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c index 5d88204f33..c803852144 100644 --- a/src/southbridge/amd/pi/hudson/uart.c +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index 2f50c3f713..e465c1484e 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 8b8f6b361a..2124d919a9 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 5140d23388..15ff98d386 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/acpi/audio.asl b/src/southbridge/intel/bd82x6x/acpi/audio.asl index 0dd9269cc6..b0adf82c87 100644 --- a/src/southbridge/intel/bd82x6x/acpi/audio.asl +++ b/src/southbridge/intel/bd82x6x/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 5f41f441f5..3e7874cfaa 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl index c78ec1b8ec..739e6d8915 100644 --- a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl +++ b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 06c9ada15b..cd2ea09802 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 8dae5fff2a..78db0ba498 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index 3c01893dc7..3a2f46b482 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index 1d79aacfec..2060065740 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 744fe7d6a6..15178cbf9d 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index f2e32da130..8df42bde81 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 9f9c4455bb..6d8e1f0848 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index f82ed3e979..3bc3836545 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index f6b26bf9e6..eeffd287ca 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 2213878307..efa6479a48 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 0dd7a562b1..3e3a927c13 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 91f1bc3448..4d34877a4c 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 63da2d65f4..6cfdb56944 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index e735e21656..7749d5f41a 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index f5df5a3bb2..c106f1eec3 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index e96c38da6b..ac10a936c4 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 01576a683a..46ab5fc47a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 15f99cdf78..15cbd7663c 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 203d0c038b..3131ba24da 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced939a..e4167aeaa3 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index e0b2cbeb47..f18f8124ac 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 0ec0c05cb0..326c2ea0d5 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 7c672b3cb5..0839ecfb77 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 534847805d..3af2624662 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 833512a5b7..634371b0aa 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 739f6ce8a8..84309a4e9a 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index f5243f6507..ba3630ac3e 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index b011c493a7..ba9b9766e6 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index ceac5982a3..8a9cb86ca1 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 98a4bdbe60..26d2bd1688 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 55c8948063..7af3b08f46 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index c8521e1b5a..b48cb8a6c3 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl index d7842cd677..ad33d4b4f9 100644 --- a/src/southbridge/intel/common/acpi/pcie.asl +++ b/src/southbridge/intel/common/acpi/pcie.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl index 4e04ab2338..86cc0bdf87 100644 --- a/src/southbridge/intel/common/acpi/pcie_port.asl +++ b/src/southbridge/intel/common/acpi/pcie_port.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index 057d5c28d8..011f708c59 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl index 32cc22bd39..89dfc57169 100644 --- a/src/southbridge/intel/common/acpi/sleepstates.asl +++ b/src/southbridge/intel/common/acpi/sleepstates.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/acpi/smbus.asl b/src/southbridge/intel/common/acpi/smbus.asl index 268298fb4c..8a1d1f9b64 100644 --- a/src/southbridge/intel/common/acpi/smbus.asl +++ b/src/southbridge/intel/common/acpi/smbus.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index ade1a98b62..1df828e0fb 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h index 9fdee1a45b..3d911c2315 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.h +++ b/src/southbridge/intel/common/acpi_pirq_gen.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 80c65bb028..d143e58565 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/finalize.h b/src/southbridge/intel/common/finalize.h index 4a8cbc0413..c071690637 100644 --- a/src/southbridge/intel/common/finalize.h +++ b/src/southbridge/intel/common/finalize.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 134f780825..d72ff76b18 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Google Inc. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 2352636977..dde673beac 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 9731d75086..568806d630 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2016 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index eba2d0130f..60c6e551c2 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2016 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index 238e3c80cb..851b3fb4b2 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index 8ff41b3cf2..eb8477af3f 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ff0410adba..5174ed7cfa 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h index fdef8887b1..8738b03599 100644 --- a/src/southbridge/intel/common/pmbase.h +++ b/src/southbridge/intel/common/pmbase.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c index 198562baee..997a053c27 100644 --- a/src/southbridge/intel/common/pmclib.c +++ b/src/southbridge/intel/common/pmclib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h index 075f707b1b..a74380c5ea 100644 --- a/src/southbridge/intel/common/pmclib.h +++ b/src/southbridge/intel/common/pmclib.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index f7f08c8db1..0a3bd4b6f7 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index cea5c82502..dc9fa1fa9e 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 225cd26086..7a8bcea7db 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 366fe08ccf..53274e346d 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h index e5ac4094f2..c2610c6149 100644 --- a/src/southbridge/intel/common/rcba_pirq.h +++ b/src/southbridge/intel/common/rcba_pirq.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index 3ee12aa169..799d94e56d 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/rtc.h b/src/southbridge/intel/common/rtc.h index 0d04a51b5e..2d147286c2 100644 --- a/src/southbridge/intel/common/rtc.h +++ b/src/southbridge/intel/common/rtc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index b54f1d7a11..0fb6386d4c 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 1348174389..ca2b7a3b1b 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 9fba12f9ef..3fdee84d8c 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 828520095c..5e967af7cc 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -1,8 +1,4 @@ /* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger - * Copyright (C) 2011 Stefan Tauner - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 9d6f15326e..62708604c5 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2019 Elyes Haouas * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index d60264a15b..9f5b0b5840 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 2eaedab2e8..ce9bb33df7 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index f30360f766..1a1a0a10ea 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index cef36e924d..bbb56e6c86 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007 Rudolf Marek - * Copyright (C) 2017 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl index 97e67037ff..eb913678e6 100644 --- a/src/southbridge/intel/i82371eb/acpi/intx.asl +++ b/src/southbridge/intel/i82371eb/acpi/intx.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/acpi/isabridge.asl b/src/southbridge/intel/i82371eb/acpi/isabridge.asl index 2f842d62a4..86d6c6707b 100644 --- a/src/southbridge/intel/i82371eb/acpi/isabridge.asl +++ b/src/southbridge/intel/i82371eb/acpi/isabridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl index 6525e1eae8..eaacccb58b 100644 --- a/src/southbridge/intel/i82371eb/acpi/pirq.asl +++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 4b7dcf848f..8059c2c87a 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2005 Nick Barker - * Copyright (C) 2007 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 581db816a8..4e48fca6d5 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h index 986208208e..87a91add93 100644 --- a/src/southbridge/intel/i82371eb/chip.h +++ b/src/southbridge/intel/i82371eb/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 465710d03d..1e0bf8752f 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 671bfc5854..46f973df23 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 15ab0eec0d..b26628d075 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -3,8 +3,6 @@ * * Based on src/southbridge/via/vt8237r/vt8237_fadt.c * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2009 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 898cdffc25..4c33f93947 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index a566af7767..5fcc484439 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 7a72a6552d..b21887f8d9 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 3d1970c0ee..6e1347d0b3 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 9d7107442e..f9690c34ad 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann - * Copyright (C) 2010 Keith Hui - * Copyright (C) 2010 Idwer Vollering - * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 80b19a187e..d4fffa4619 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index b4d55a9188..253433368e 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 5dad02ef2f..1ed45043f8 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index a8931fffc1..3acd618dbf 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index cbbc370252..ba17b7e973 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h index a0961ee76d..b4becce200 100644 --- a/src/southbridge/intel/i82801dx/chip.h +++ b/src/southbridge/intel/i82801dx/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Eric Biederman * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 5ab7f8d211..c447413831 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Ronald G. Minnich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index 765bcb2587..303c33b3bf 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Ron G. Minnich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 18db9e99ca..71c2b2fab6 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Ron G. Minnich - * Copyright (C) 2004 Eric Biederman - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c index 2881cc0333..c94779b0f4 100644 --- a/src/southbridge/intel/i82801dx/ide.c +++ b/src/southbridge/intel/i82801dx/ide.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Ronald G. Minnich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 0e2aead4e4..b7eba17da6 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Linux Networx - * Copyright (C) 2004 SuSE Linux AG - * Copyright (C) 2004 Tyan Computer - * Copyright (C) 2010 Joseph Smith * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 3a72f4d7e9..b95f9c95fa 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801dx/pci.c b/src/southbridge/intel/i82801dx/pci.c index a48eed06fa..837e3401bc 100644 --- a/src/southbridge/intel/i82801dx/pci.c +++ b/src/southbridge/intel/i82801dx/pci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Ronald G. Minnich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index dc53220fc1..0de98aca9a 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index d9720e0c0c..96bf36ceeb 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c index 518f608fe9..f6cb6e48f4 100644 --- a/src/southbridge/intel/i82801dx/usb.c +++ b/src/southbridge/intel/i82801dx/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Ronald G. Minnich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c index dda3d95493..9d48b8996a 100644 --- a/src/southbridge/intel/i82801dx/usb2.c +++ b/src/southbridge/intel/i82801dx/usb2.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Tyan * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index deb11299e9..e57a3ea2a8 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index c9ed899578..27e16305df 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index f18aedbca7..606faa4c38 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/ac97.asl b/src/southbridge/intel/i82801gx/acpi/ac97.asl index e1db234a63..1ed067f83b 100644 --- a/src/southbridge/intel/i82801gx/acpi/ac97.asl +++ b/src/southbridge/intel/i82801gx/acpi/ac97.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/audio.asl b/src/southbridge/intel/i82801gx/acpi/audio.asl index 9e0d997482..49b9bc4363 100644 --- a/src/southbridge/intel/i82801gx/acpi/audio.asl +++ b/src/southbridge/intel/i82801gx/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 23ba6afdfc..5787cec5c2 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index c3b9687255..6bb06a242f 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/irqlinks.asl b/src/southbridge/intel/i82801gx/acpi/irqlinks.asl index 2d029242d8..0bfdbdedad 100644 --- a/src/southbridge/intel/i82801gx/acpi/irqlinks.asl +++ b/src/southbridge/intel/i82801gx/acpi/irqlinks.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index d5201b2fff..29014ded85 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/pata.asl b/src/southbridge/intel/i82801gx/acpi/pata.asl index 923c33c321..4833dbce92 100644 --- a/src/southbridge/intel/i82801gx/acpi/pata.asl +++ b/src/southbridge/intel/i82801gx/acpi/pata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/pci.asl b/src/southbridge/intel/i82801gx/acpi/pci.asl index cb079c223e..4820830c6b 100644 --- a/src/southbridge/intel/i82801gx/acpi/pci.asl +++ b/src/southbridge/intel/i82801gx/acpi/pci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/sata.asl b/src/southbridge/intel/i82801gx/acpi/sata.asl index 44ce576e71..5c22e623ae 100644 --- a/src/southbridge/intel/i82801gx/acpi/sata.asl +++ b/src/southbridge/intel/i82801gx/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/acpi/usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl index fc5f07c5b2..1ea75a042d 100644 --- a/src/southbridge/intel/i82801gx/acpi/usb.asl +++ b/src/southbridge/intel/i82801gx/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 56baab1edc..c18eb4b818 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index f470526589..5376234414 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 75b957573e..48f50c21e0 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index b89e57d859..45844c4cf3 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 6aab741737..0be9e28ee2 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 688f1c3211..dbc1430128 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 672ee432fd..2bb6be4312 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 779d3195e9..743dbba676 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/nic.c b/src/southbridge/intel/i82801gx/nic.c index a4c9baea7b..b7b061fb65 100644 --- a/src/southbridge/intel/i82801gx/nic.c +++ b/src/southbridge/intel/i82801gx/nic.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index c13ad7021e..a0f91cda68 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 5ff9d38192..c8e7346208 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 0d8b474d9b..8ebbd8118f 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 47c35ba7c6..a658057e11 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/sata.h b/src/southbridge/intel/i82801gx/sata.h index 9eec0dfd55..2515470885 100644 --- a/src/southbridge/intel/i82801gx/sata.h +++ b/src/southbridge/intel/i82801gx/sata.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 9261690dbd..fb15ba5825 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index c7ee5664bd..f8c8bec8eb 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index cd43e03750..21d1a6b491 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 0a94d3b5f2..368eebfffa 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 1e2ee475a6..7f69845336 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH -## 2012 secunet security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 41d1b89430..3c949f6a46 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH -## 2012 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/acpi/audio.asl b/src/southbridge/intel/i82801ix/acpi/audio.asl index b09f2af34d..94504af7ec 100644 --- a/src/southbridge/intel/i82801ix/acpi/audio.asl +++ b/src/southbridge/intel/i82801ix/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 1fc5b74591..a419fdb685 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 5a9d2994ad..9844c3437f 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/acpi/irqlinks.asl b/src/southbridge/intel/i82801ix/acpi/irqlinks.asl index 2d029242d8..0bfdbdedad 100644 --- a/src/southbridge/intel/i82801ix/acpi/irqlinks.asl +++ b/src/southbridge/intel/i82801ix/acpi/irqlinks.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index 07ce43aa89..1d720f0119 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/acpi/pci.asl b/src/southbridge/intel/i82801ix/acpi/pci.asl index f2988e1951..7711e915d6 100644 --- a/src/southbridge/intel/i82801ix/acpi/pci.asl +++ b/src/southbridge/intel/i82801ix/acpi/pci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/acpi/sata.asl b/src/southbridge/intel/i82801ix/acpi/sata.asl index ad4883219c..19028ed639 100644 --- a/src/southbridge/intel/i82801ix/acpi/sata.asl +++ b/src/southbridge/intel/i82801ix/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/acpi/usb.asl b/src/southbridge/intel/i82801ix/acpi/usb.asl index 5fa751a20d..cba9b07b40 100644 --- a/src/southbridge/intel/i82801ix/acpi/usb.asl +++ b/src/southbridge/intel/i82801ix/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index b2701514a9..90c542dd73 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 73ee822f74..31d99c785c 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index 663c6d363d..2f9012398d 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 9c1e6c0dc2..882d725c46 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 60f49d2e9b..7c4f5b2c79 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 5099f167b9..65492d64ce 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 753c336aac..7feed34610 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index f60aad387e..d155e22836 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bac48c256d..8b5efd9f2e 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index fab74ddcb7..cb4fb45519 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c index 889e042514..5b14ab0cc1 100644 --- a/src/southbridge/intel/i82801ix/pci.c +++ b/src/southbridge/intel/i82801ix/pci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index bdfc84db43..d66a4bd1d1 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 546acdfc00..49d60f285f 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index bd84807823..fecf71b563 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5f73f411dc..25d3515134 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8090a09040..1bfe85c502 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 8946b020d8..4d49af4f5b 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 4c875ad035..7eb7243147 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 0e756a8da7..1d175ab803 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH -## 2012 secunet security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 1527b8adb0..49ef51e8ec 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH -## 2012 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801jx/acpi/audio.asl b/src/southbridge/intel/i82801jx/acpi/audio.asl index afae905079..327e10fa99 100644 --- a/src/southbridge/intel/i82801jx/acpi/audio.asl +++ b/src/southbridge/intel/i82801jx/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index c7354a028b..3c9dbc3f40 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index 2c277986ad..e63c23bc43 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/acpi/irqlinks.asl b/src/southbridge/intel/i82801jx/acpi/irqlinks.asl index 2d029242d8..0bfdbdedad 100644 --- a/src/southbridge/intel/i82801jx/acpi/irqlinks.asl +++ b/src/southbridge/intel/i82801jx/acpi/irqlinks.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index 7f16e08fae..b903aa7b45 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/acpi/pci.asl b/src/southbridge/intel/i82801jx/acpi/pci.asl index de164249ee..f8a435e159 100644 --- a/src/southbridge/intel/i82801jx/acpi/pci.asl +++ b/src/southbridge/intel/i82801jx/acpi/pci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/acpi/sata.asl b/src/southbridge/intel/i82801jx/acpi/sata.asl index ad4883219c..19028ed639 100644 --- a/src/southbridge/intel/i82801jx/acpi/sata.asl +++ b/src/southbridge/intel/i82801jx/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/acpi/usb.asl b/src/southbridge/intel/i82801jx/acpi/usb.asl index b621263cd4..6432ed030e 100644 --- a/src/southbridge/intel/i82801jx/acpi/usb.asl +++ b/src/southbridge/intel/i82801jx/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 567679ebcc..3ed6c32eb9 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index e4c68fb95a..d82323c682 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 8e3329cd71..6284c62578 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0628c435a9..0a964be2ea 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index ebd427fdd5..214a263a15 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index abf6187552..0139613262 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 91b1bde93a..e3fdde75e9 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 88944c0ebd..26ecda33c8 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c index 69189229c2..718f45ade6 100644 --- a/src/southbridge/intel/i82801jx/pci.c +++ b/src/southbridge/intel/i82801jx/pci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 64da5a734b..08b0e98f52 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index ce8ae470a1..69df88c4cb 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 68f2317ff0..413471421d 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6a8a8daed7..3435287813 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 65d897f288..d2744c8bd5 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index a24685a26c..8290112d63 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f94e7a8e72..2b59134ae2 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index dc35de561c..9f724cc447 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 5b38ea760a..2fceced9b4 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 0076864db9..82cb29fb35 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h index ae282117e0..fbbb0a17e8 100644 --- a/src/southbridge/intel/ibexpeak/chip.h +++ b/src/southbridge/intel/ibexpeak/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index b455cef179..00d58221a8 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 52d483d3b3..4db81bca4b 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index defe145404..2838db1e98 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index 53c4ae7a95..4fdb1e5a4a 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 851f4f51ea..5c1b77fe43 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 3676a47b20..1baa7df6bb 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6ace8..31a0261da6 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 5694dd763b..2864c51a91 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index a0422f2bed..a551fa473c 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 9148b44a8e..1b9f51533d 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 424bf4203c..6ec17a7c47 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 04e056492b..e4eebcb8a9 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index accbe68bd0..eafb1ee2df 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e670c9ade4..937078dfb4 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 597d388b9d..e9a542e692 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index d31fd7028c..ce169945fc 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 87f72984f4..fd557577f2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d826..1b6513dd47 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 83c455f012..8bf40f5fbb 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Chromium OS Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index 19193e4458..a953e7daa2 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 3c873a2e60..149b75be6e 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl b/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl index 2d029242d8..0bfdbdedad 100644 --- a/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl +++ b/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index ddd5a2f53d..e8d8ba85ee 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl index 431c61e74e..b165cfa5e3 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a21cd2d819..9fcbeca8ff 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/sata.asl b/src/southbridge/intel/lynxpoint/acpi/sata.asl index 5c5098b6d0..49adadc86b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/sata.asl +++ b/src/southbridge/intel/lynxpoint/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 2a3c096099..8dd0b1ddc1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index ee883031ed..790f2fec19 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index cb1c190b39..eb505ed42e 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 21475745c1..0660072790 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index e56b32b9ec..517516d120 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index b02f19580c..fa5d26c55d 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index e0e4613d0b..6dab182781 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 91f1bc3448..4d34877a4c 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index cd3609426f..81aceac4b8 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 6f12c70f61..3de3532c78 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 1b3c695175..31618e805f 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h index 973b9d79d8..8c6ccd01cd 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ b/src/southbridge/intel/lynxpoint/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 1919d58998..60b612ca5b 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 8436243f59..84b5690c17 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4b39829e0d..745c2315c0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 3b4bd510ca..09d12a04dc 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 2df03c9cdc..fd8d3f5479 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 8f6932bec4..c26d63ad17 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 34c2537e2e..5222db2c45 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index cb50c125ec..1413d9441d 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9622c67255..0a62803ca2 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 92dd02e2ed..83eac8d023 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index cc494771dd..f7762ac93c 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/rcba.c b/src/southbridge/intel/lynxpoint/rcba.c index 57253cb7f3..71f46fc5b0 100644 --- a/src/southbridge/intel/lynxpoint/rcba.c +++ b/src/southbridge/intel/lynxpoint/rcba.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 75bfbde2dd..8570dab197 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 60668dd4c1..da2a47a033 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index ff659b837a..3dc8ac4156 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index e5c390ef50..ed3c6cce7b 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 4ac4ff948d..58729105f1 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 3e50beeb09..574b6d17f5 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 4818d626f0..99e5314e4d 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/ricoh/rl5c476/Kconfig b/src/southbridge/ricoh/rl5c476/Kconfig index 3d37cbdbf7..77d88662c7 100644 --- a/src/southbridge/ricoh/rl5c476/Kconfig +++ b/src/southbridge/ricoh/rl5c476/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 0bcf9c5f93..67173a2f87 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004-2005 Nick Barker * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 646650a42a..cfaf3c80bd 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Nick Barker * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 1789f6e232..c07e76439b 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Marc Bertens * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/Kconfig b/src/southbridge/ti/pci7420/Kconfig index 2d0f239967..3ff9f21c65 100644 --- a/src/southbridge/ti/pci7420/Kconfig +++ b/src/southbridge/ti/pci7420/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc index c8b4c9e021..6b9dfe3223 100644 --- a/src/southbridge/ti/pci7420/Makefile.inc +++ b/src/southbridge/ti/pci7420/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 44a38ea05c..5964aa97f5 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/chip.h b/src/southbridge/ti/pci7420/chip.h index 3a22824e74..266c121c10 100644 --- a/src/southbridge/ti/pci7420/chip.h +++ b/src/southbridge/ti/pci7420/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index dac273a9e0..126a8cf40d 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index 508178ad4b..2c7449ef23 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pcixx12/Kconfig b/src/southbridge/ti/pcixx12/Kconfig index 42932c843f..55736fb56c 100644 --- a/src/southbridge/ti/pcixx12/Kconfig +++ b/src/southbridge/ti/pcixx12/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pcixx12/Makefile.inc b/src/southbridge/ti/pcixx12/Makefile.inc index d64bf0fb20..e4ef6ad0fa 100644 --- a/src/southbridge/ti/pcixx12/Makefile.inc +++ b/src/southbridge/ti/pcixx12/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index 984b60f8ea..48305215e1 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 4e6624412d..3e3a0e99ee 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013-2017 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc index 247969477c..a7ddc7f04a 100644 --- a/src/vendorcode/amd/agesa/common/Makefile.inc +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -1,8 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2011, Advanced Micro Devices, Inc. -# All rights reserved. -# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 9726345b94..5fb9fc0fc5 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -1,8 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2011, Advanced Micro Devices, Inc. -# All rights reserved. -# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 24528da7f6..674ec60e68 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -1,8 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2012, Advanced Micro Devices, Inc. -# All rights reserved. -# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index ddd6d62df7..ed21b165d7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -1,8 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2012, Advanced Micro Devices, Inc. -# All rights reserved. -# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc index 86a51f77f9..192cd33141 100644 --- a/src/vendorcode/amd/cimx/sb800/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc index 0c62cdde14..79ebcf8e39 100644 --- a/src/vendorcode/amd/cimx/sb900/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 34dae71851..46af6559bd 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -1,9 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016 Advanced Micro Devices, Inc. -# 2013 - 2014, Sage Electronic Engineering, LLC -# All rights reserved. -# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright diff --git a/src/vendorcode/cavium/Kconfig b/src/vendorcode/cavium/Kconfig index 9538d1cab2..7d739956a0 100644 --- a/src/vendorcode/cavium/Kconfig +++ b/src/vendorcode/cavium/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/cavium/Makefile.inc b/src/vendorcode/cavium/Makefile.inc index 855b3c6218..d44a4965e9 100644 --- a/src/vendorcode/cavium/Makefile.inc +++ b/src/vendorcode/cavium/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/Makefile.inc b/src/vendorcode/eltan/Makefile.inc index 1f6a4065cf..4d8597500f 100644 --- a/src/vendorcode/eltan/Makefile.inc +++ b/src/vendorcode/eltan/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2018 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig index 9a89381d73..eb5c32dc5f 100644 --- a/src/vendorcode/eltan/security/Kconfig +++ b/src/vendorcode/eltan/security/Kconfig @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc index c0d9057977..de6ebae2bb 100644 --- a/src/vendorcode/eltan/security/Makefile.inc +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index b95c125578..003db90c72 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/mboot/Makefile.inc b/src/vendorcode/eltan/security/mboot/Makefile.inc index 68b38586b1..f81d6bbb6a 100644 --- a/src/vendorcode/eltan/security/mboot/Makefile.inc +++ b/src/vendorcode/eltan/security/mboot/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index 4429c1f5a0..47a5280f84 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 9cb94b11df..4e4179e1c4 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/mboot/mboot_func.c b/src/vendorcode/eltan/security/mboot/mboot_func.c index 67922048a2..b0e4aa0075 100644 --- a/src/vendorcode/eltan/security/mboot/mboot_func.c +++ b/src/vendorcode/eltan/security/mboot/mboot_func.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index d6ff541744..5f09044c0a 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 2acad84367..02a7b93c7b 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 9d99e02e71..fd0d82b3f7 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * Copyright (C) 2017-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h index d4f3b5ef9c..722064da76 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.h +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * Copyright (C) 2017-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig index 498d0edb08..6247bc813b 100644 --- a/src/vendorcode/google/Kconfig +++ b/src/vendorcode/google/Kconfig @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc index 60ff84d01e..bfce7cd840 100644 --- a/src/vendorcode/google/Makefile.inc +++ b/src/vendorcode/google/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index cdb4305fdd..5469fd421d 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index b509af7483..994f3563cb 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 59c4901754..39939dcb15 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl index 5a091ddfaa..d8661be763 100644 --- a/src/vendorcode/google/chromeos/acpi/amac.asl +++ b/src/vendorcode/google/chromeos/acpi/amac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 4852600748..b1b58315cc 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 69e848a1aa..7f87d7425e 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/acpi/ramoops.asl b/src/vendorcode/google/chromeos/acpi/ramoops.asl index 810ff91a01..4262d9457d 100644 --- a/src/vendorcode/google/chromeos/acpi/ramoops.asl +++ b/src/vendorcode/google/chromeos/acpi/ramoops.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl index 8f8b0e571d..eded65b938 100644 --- a/src/vendorcode/google/chromeos/acpi/vpd.asl +++ b/src/vendorcode/google/chromeos/acpi/vpd.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a40c4c9a88..7d610148e0 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index f2cdbfd39c..2fc7158dcf 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/dsm_calib.c b/src/vendorcode/google/chromeos/dsm_calib.c index d3b14cb03c..341e428845 100644 --- a/src/vendorcode/google/chromeos/dsm_calib.c +++ b/src/vendorcode/google/chromeos/dsm_calib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index 17cb4d9018..a723319d9b 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 04680c0974..89db0ee20f 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 811a3f4994..66de15f27f 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 9ea112a5c4..78b5b4d372 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 01de60c835..f514928862 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/symbols.h b/src/vendorcode/google/chromeos/symbols.h index 53476455c3..e1c3770957 100644 --- a/src/vendorcode/google/chromeos/symbols.h +++ b/src/vendorcode/google/chromeos/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/tpm2.c b/src/vendorcode/google/chromeos/tpm2.c index 08e8ddb995..6feba27f8d 100644 --- a/src/vendorcode/google/chromeos/tpm2.c +++ b/src/vendorcode/google/chromeos/tpm2.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/vpd_calibration.c b/src/vendorcode/google/chromeos/vpd_calibration.c index 7f9910b3f9..55da66a04a 100644 --- a/src/vendorcode/google/chromeos/vpd_calibration.c +++ b/src/vendorcode/google/chromeos/vpd_calibration.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/vpd_mac.c b/src/vendorcode/google/chromeos/vpd_mac.c index fcd3efec9e..04b58191d0 100644 --- a/src/vendorcode/google/chromeos/vpd_mac.c +++ b/src/vendorcode/google/chromeos/vpd_mac.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/vpd_serialno.c b/src/vendorcode/google/chromeos/vpd_serialno.c index 8cae5d6d20..a186aefa96 100644 --- a/src/vendorcode/google/chromeos/vpd_serialno.c +++ b/src/vendorcode/google/chromeos/vpd_serialno.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c index 2b2959f016..f763affcea 100644 --- a/src/vendorcode/google/chromeos/watchdog.c +++ b/src/vendorcode/google/chromeos/watchdog.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c index 093e6cdb74..23fd79ef6f 100644 --- a/src/vendorcode/google/chromeos/wrdd.c +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/google/smbios.c b/src/vendorcode/google/smbios.c index 7b147cdfe4..2b8f6c23d9 100644 --- a/src/vendorcode/google/smbios.c +++ b/src/vendorcode/google/smbios.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index e1458db829..59bfba6a13 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## Copyright (C) 2018 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 7b9ca5167e..7969f75e06 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2018 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/siemens/Kconfig b/src/vendorcode/siemens/Kconfig index 6684b8af97..42938f4203 100644 --- a/src/vendorcode/siemens/Kconfig +++ b/src/vendorcode/siemens/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Siemens AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/siemens/Makefile.inc b/src/vendorcode/siemens/Makefile.inc index ece2b4dfc7..e02badf5c1 100644 --- a/src/vendorcode/siemens/Makefile.inc +++ b/src/vendorcode/siemens/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Siemens AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/siemens/hwilib/Makefile.inc b/src/vendorcode/siemens/hwilib/Makefile.inc index 1c6f6c92b2..41c108b38f 100644 --- a/src/vendorcode/siemens/hwilib/Makefile.inc +++ b/src/vendorcode/siemens/hwilib/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Siemens AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index a4b8e547ae..fde97678bf 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index 6850f070e5..a4c376ed6e 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by From ba37b94e8e7819913a53b62143ee1e7fb897592e Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 16 Dec 2019 23:19:29 -0700 Subject: [PATCH 0494/1463] drivers/i2c/designware: Add 150MHz clock speed BUG=b:143885765 TEST=I2C clock speed on trembyle is 400kHz Change-Id: I50e904822823a6fc173d4d4b76f0882b4ce81ae8 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/1970655 Reviewed-by: Daniel Kurtz Reviewed-on: https://review.coreboot.org/c/coreboot/+/39588 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/i2c/designware/dw_i2c.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 9eda827f30..5e57e5a5a6 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -213,6 +213,13 @@ static const struct soc_clock { .ns = 3000, }, }, + { + .clk_speed_mhz = 150, + .freq = { + .ticks = 600, + .ns = 4000, + }, + }, { .clk_speed_mhz = 216, .freq = { From 4017de0d10d4b464ec14663dfd0c8bd1cbcfba20 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 16 Dec 2019 23:21:05 -0700 Subject: [PATCH 0495/1463] soc/amd/picasso: Set I2C clock reference to 150MHz Picasso uses a 150MHz reference clock for the Designware I2C devices. This update allows us to get the correct speeds out. BUG=b:143885765 TEST=Trembyle has 400kHz I2C clock Change-Id: Ia888a74e51201b6c911e0e810f0535403204cf60 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/1970656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39589 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/soc/amd/picasso/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index acceb00cad..e19375567e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -196,7 +196,7 @@ config RO_REGION_ONLY config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default 133 + default 150 config PICASSO_LPC_IOMUX bool From af505671a19f8d760093ada3c1a8f6e2a62d2728 Mon Sep 17 00:00:00 2001 From: Eric Peers Date: Thu, 5 Mar 2020 16:04:15 -0700 Subject: [PATCH 0496/1463] util/amdfwtool: Fix file open error msg Print out the name of the file that failed to open. BUG=none TEST=rerun build-board.sh with missing files BRANCH=none Signed-off-by: Eric Peers Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb Reviewed-on: https://chromium-review.googlesource.com/2090667 Reviewed-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/amdfwtool/amdfwtool.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 5bcc0a7d77..4f1e8ba0b7 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -575,7 +575,8 @@ static ssize_t copy_blob(void *dest, const char *src_file, size_t room) fd = open(src_file, O_RDONLY); if (fd < 0) { - printf("Error: %s\n", strerror(errno)); + printf("Error opening file: %s: %s\n", + src_file, strerror(errno)); return -1; } From 3b618bbe31e06a1dbea3656b234718971e30af14 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 12:51:24 +0100 Subject: [PATCH 0497/1463] mainboard/[a-f]*: Remove copyright notices They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Angel Pons Reviewed-by: David Hendricks Reviewed-by: Frans Hendriks Reviewed-by: Tristan Corrick --- src/mainboard/amd/gardenia/BiosCallOuts.c | 1 - src/mainboard/amd/gardenia/Kconfig | 1 - src/mainboard/amd/gardenia/Makefile.inc | 1 - src/mainboard/amd/gardenia/OemCustomize.c | 1 - src/mainboard/amd/gardenia/acpi/gpe.asl | 1 - src/mainboard/amd/gardenia/acpi/mainboard.asl | 1 - src/mainboard/amd/gardenia/acpi/routing.asl | 2 -- src/mainboard/amd/gardenia/acpi/sleep.asl | 1 - src/mainboard/amd/gardenia/acpi/usb_oc.asl | 2 -- src/mainboard/amd/gardenia/bootblock/OemCustomize.c | 1 - src/mainboard/amd/gardenia/bootblock/bootblock.c | 1 - src/mainboard/amd/gardenia/devicetree.cb | 1 - src/mainboard/amd/gardenia/dsdt.asl | 1 - src/mainboard/amd/gardenia/gpio.c | 1 - src/mainboard/amd/gardenia/gpio.h | 1 - src/mainboard/amd/gardenia/irq_tables.c | 1 - src/mainboard/amd/gardenia/mainboard.c | 1 - src/mainboard/amd/gardenia/mptable.c | 1 - src/mainboard/amd/gardenia/romstage.c | 1 - src/mainboard/amd/inagua/BiosCallOuts.c | 1 - src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/inagua/Makefile.inc | 1 - src/mainboard/amd/inagua/OemCustomize.c | 1 - src/mainboard/amd/inagua/OptionsIds.h | 1 - src/mainboard/amd/inagua/acpi/gpe.asl | 1 - src/mainboard/amd/inagua/acpi/ide.asl | 1 - src/mainboard/amd/inagua/acpi/mainboard.asl | 1 - src/mainboard/amd/inagua/acpi/routing.asl | 1 - src/mainboard/amd/inagua/acpi/sata.asl | 1 - src/mainboard/amd/inagua/acpi/sleep.asl | 1 - src/mainboard/amd/inagua/acpi/usb_oc.asl | 1 - src/mainboard/amd/inagua/acpi_tables.c | 1 - src/mainboard/amd/inagua/bootblock.c | 1 - src/mainboard/amd/inagua/buildOpts.c | 1 - src/mainboard/amd/inagua/cmos.layout | 1 - src/mainboard/amd/inagua/devicetree.cb | 1 - src/mainboard/amd/inagua/dsdt.asl | 1 - src/mainboard/amd/inagua/irq_tables.c | 1 - src/mainboard/amd/inagua/mainboard.c | 1 - src/mainboard/amd/inagua/mptable.c | 1 - src/mainboard/amd/inagua/platform_cfg.h | 1 - src/mainboard/amd/olivehill/BiosCallOuts.c | 1 - src/mainboard/amd/olivehill/Kconfig | 1 - src/mainboard/amd/olivehill/Makefile.inc | 1 - src/mainboard/amd/olivehill/OemCustomize.c | 1 - src/mainboard/amd/olivehill/OptionsIds.h | 1 - src/mainboard/amd/olivehill/acpi/gpe.asl | 1 - src/mainboard/amd/olivehill/acpi/ide.asl | 1 - src/mainboard/amd/olivehill/acpi/mainboard.asl | 1 - src/mainboard/amd/olivehill/acpi/routing.asl | 2 -- src/mainboard/amd/olivehill/acpi/sata.asl | 1 - src/mainboard/amd/olivehill/acpi/si.asl | 1 - src/mainboard/amd/olivehill/acpi/sleep.asl | 1 - src/mainboard/amd/olivehill/acpi/usb_oc.asl | 2 -- src/mainboard/amd/olivehill/acpi_tables.c | 1 - src/mainboard/amd/olivehill/buildOpts.c | 1 - src/mainboard/amd/olivehill/cmos.layout | 1 - src/mainboard/amd/olivehill/devicetree.cb | 1 - src/mainboard/amd/olivehill/dsdt.asl | 2 -- src/mainboard/amd/olivehill/irq_tables.c | 1 - src/mainboard/amd/olivehill/mainboard.c | 1 - src/mainboard/amd/olivehill/mptable.c | 1 - src/mainboard/amd/padmelon/BiosCallOuts.c | 1 - src/mainboard/amd/padmelon/BiosCallOuts.h | 1 - src/mainboard/amd/padmelon/Kconfig | 1 - src/mainboard/amd/padmelon/Makefile.inc | 1 - src/mainboard/amd/padmelon/OemCustomize.c | 1 - src/mainboard/amd/padmelon/acpi/gpe.asl | 1 - src/mainboard/amd/padmelon/acpi/mainboard.asl | 1 - src/mainboard/amd/padmelon/acpi/routing.asl | 2 -- src/mainboard/amd/padmelon/acpi/sleep.asl | 1 - src/mainboard/amd/padmelon/acpi/usb_oc.asl | 2 -- src/mainboard/amd/padmelon/bootblock/OemCustomize.c | 1 - src/mainboard/amd/padmelon/bootblock/bootblock.c | 1 - src/mainboard/amd/padmelon/devicetree.cb | 1 - src/mainboard/amd/padmelon/dsdt.asl | 1 - src/mainboard/amd/padmelon/fan_init.c | 2 -- src/mainboard/amd/padmelon/gpio.c | 1 - src/mainboard/amd/padmelon/gpio.h | 1 - src/mainboard/amd/padmelon/hda_verb.c | 1 - src/mainboard/amd/padmelon/mainboard.c | 1 - src/mainboard/amd/parmer/BiosCallOuts.c | 1 - src/mainboard/amd/parmer/Kconfig | 1 - src/mainboard/amd/parmer/Makefile.inc | 1 - src/mainboard/amd/parmer/OemCustomize.c | 1 - src/mainboard/amd/parmer/OptionsIds.h | 1 - src/mainboard/amd/parmer/acpi/gpe.asl | 1 - src/mainboard/amd/parmer/acpi/mainboard.asl | 1 - src/mainboard/amd/parmer/acpi/routing.asl | 2 -- src/mainboard/amd/parmer/acpi/si.asl | 1 - src/mainboard/amd/parmer/acpi/sleep.asl | 1 - src/mainboard/amd/parmer/acpi/usb_oc.asl | 2 -- src/mainboard/amd/parmer/acpi_tables.c | 1 - src/mainboard/amd/parmer/bootblock.c | 1 - src/mainboard/amd/parmer/buildOpts.c | 1 - src/mainboard/amd/parmer/cmos.layout | 1 - src/mainboard/amd/parmer/devicetree.cb | 1 - src/mainboard/amd/parmer/dsdt.asl | 2 -- src/mainboard/amd/parmer/irq_tables.c | 1 - src/mainboard/amd/parmer/mainboard.c | 1 - src/mainboard/amd/parmer/mptable.c | 1 - src/mainboard/amd/persimmon/BiosCallOuts.c | 1 - src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/persimmon/Makefile.inc | 1 - src/mainboard/amd/persimmon/OemCustomize.c | 1 - src/mainboard/amd/persimmon/OptionsIds.h | 1 - src/mainboard/amd/persimmon/acpi/gpe.asl | 1 - src/mainboard/amd/persimmon/acpi/ide.asl | 1 - src/mainboard/amd/persimmon/acpi/mainboard.asl | 1 - src/mainboard/amd/persimmon/acpi/routing.asl | 1 - src/mainboard/amd/persimmon/acpi/sata.asl | 1 - src/mainboard/amd/persimmon/acpi/sleep.asl | 1 - src/mainboard/amd/persimmon/acpi/usb_oc.asl | 1 - src/mainboard/amd/persimmon/acpi_tables.c | 1 - src/mainboard/amd/persimmon/bootblock.c | 1 - src/mainboard/amd/persimmon/buildOpts.c | 1 - src/mainboard/amd/persimmon/cmos.layout | 1 - src/mainboard/amd/persimmon/devicetree.cb | 1 - src/mainboard/amd/persimmon/dsdt.asl | 1 - src/mainboard/amd/persimmon/irq_tables.c | 1 - src/mainboard/amd/persimmon/mainboard.c | 2 -- src/mainboard/amd/persimmon/mptable.c | 2 -- src/mainboard/amd/persimmon/platform_cfg.h | 1 - src/mainboard/amd/south_station/BiosCallOuts.c | 1 - src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/south_station/Makefile.inc | 1 - src/mainboard/amd/south_station/OemCustomize.c | 1 - src/mainboard/amd/south_station/OptionsIds.h | 1 - src/mainboard/amd/south_station/acpi/gpe.asl | 1 - src/mainboard/amd/south_station/acpi/ide.asl | 1 - src/mainboard/amd/south_station/acpi/mainboard.asl | 1 - src/mainboard/amd/south_station/acpi/routing.asl | 1 - src/mainboard/amd/south_station/acpi/sata.asl | 1 - src/mainboard/amd/south_station/acpi/sleep.asl | 1 - src/mainboard/amd/south_station/acpi/usb_oc.asl | 1 - src/mainboard/amd/south_station/acpi_tables.c | 1 - src/mainboard/amd/south_station/bootblock.c | 1 - src/mainboard/amd/south_station/buildOpts.c | 1 - src/mainboard/amd/south_station/cmos.layout | 1 - src/mainboard/amd/south_station/devicetree.cb | 1 - src/mainboard/amd/south_station/dsdt.asl | 1 - src/mainboard/amd/south_station/irq_tables.c | 1 - src/mainboard/amd/south_station/mainboard.c | 1 - src/mainboard/amd/south_station/mptable.c | 1 - src/mainboard/amd/south_station/platform_cfg.h | 1 - src/mainboard/amd/thatcher/BiosCallOuts.c | 1 - src/mainboard/amd/thatcher/Kconfig | 1 - src/mainboard/amd/thatcher/Makefile.inc | 1 - src/mainboard/amd/thatcher/OemCustomize.c | 1 - src/mainboard/amd/thatcher/OptionsIds.h | 1 - src/mainboard/amd/thatcher/acpi/cpstate.asl | 1 - src/mainboard/amd/thatcher/acpi/gpe.asl | 1 - src/mainboard/amd/thatcher/acpi/mainboard.asl | 1 - src/mainboard/amd/thatcher/acpi/routing.asl | 2 -- src/mainboard/amd/thatcher/acpi/si.asl | 1 - src/mainboard/amd/thatcher/acpi/sleep.asl | 1 - src/mainboard/amd/thatcher/acpi/usb_oc.asl | 2 -- src/mainboard/amd/thatcher/acpi_tables.c | 1 - src/mainboard/amd/thatcher/buildOpts.c | 1 - src/mainboard/amd/thatcher/cmos.layout | 1 - src/mainboard/amd/thatcher/devicetree.cb | 1 - src/mainboard/amd/thatcher/dsdt.asl | 2 -- src/mainboard/amd/thatcher/irq_tables.c | 1 - src/mainboard/amd/thatcher/mainboard.c | 1 - src/mainboard/amd/thatcher/mptable.c | 1 - src/mainboard/amd/union_station/BiosCallOuts.c | 1 - src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/amd/union_station/Makefile.inc | 1 - src/mainboard/amd/union_station/OemCustomize.c | 1 - src/mainboard/amd/union_station/OptionsIds.h | 1 - src/mainboard/amd/union_station/acpi/gpe.asl | 1 - src/mainboard/amd/union_station/acpi/ide.asl | 1 - src/mainboard/amd/union_station/acpi/mainboard.asl | 1 - src/mainboard/amd/union_station/acpi/routing.asl | 1 - src/mainboard/amd/union_station/acpi/sata.asl | 1 - src/mainboard/amd/union_station/acpi/sleep.asl | 1 - src/mainboard/amd/union_station/acpi/usb_oc.asl | 1 - src/mainboard/amd/union_station/acpi_tables.c | 1 - src/mainboard/amd/union_station/bootblock.c | 1 - src/mainboard/amd/union_station/buildOpts.c | 1 - src/mainboard/amd/union_station/cmos.layout | 1 - src/mainboard/amd/union_station/devicetree.cb | 1 - src/mainboard/amd/union_station/dsdt.asl | 1 - src/mainboard/amd/union_station/irq_tables.c | 1 - src/mainboard/amd/union_station/mainboard.c | 1 - src/mainboard/amd/union_station/mptable.c | 1 - src/mainboard/amd/union_station/platform_cfg.h | 1 - src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl | 1 - src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 1 - src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 1 - src/mainboard/aopen/dxplplusu/acpi/p64h2.asl | 1 - src/mainboard/aopen/dxplplusu/acpi/power.asl | 1 - src/mainboard/aopen/dxplplusu/acpi/scsi.asl | 1 - src/mainboard/aopen/dxplplusu/acpi/superio.asl | 1 - src/mainboard/aopen/dxplplusu/acpi_tables.c | 3 --- src/mainboard/aopen/dxplplusu/bootblock.c | 1 - src/mainboard/aopen/dxplplusu/devicetree.cb | 1 - src/mainboard/aopen/dxplplusu/dsdt.asl | 1 - src/mainboard/aopen/dxplplusu/fadt.c | 1 - src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/apple/macbook21/acpi/platform.asl | 1 - src/mainboard/apple/macbook21/acpi_tables.c | 1 - src/mainboard/apple/macbook21/cmos.layout | 1 - src/mainboard/apple/macbook21/devicetree.cb | 2 -- src/mainboard/apple/macbook21/dsdt.asl | 1 - src/mainboard/apple/macbook21/early_init.c | 2 -- src/mainboard/apple/macbook21/gpio.c | 1 - src/mainboard/apple/macbook21/hda_verb.c | 1 - src/mainboard/apple/macbook21/mainboard.c | 2 -- src/mainboard/apple/macbook21/mptable.c | 1 - src/mainboard/apple/macbook21/smihandler.c | 1 - src/mainboard/asrock/Kconfig | 1 - src/mainboard/asrock/b75pro3-m/Kconfig | 1 - src/mainboard/asrock/b75pro3-m/Makefile.inc | 1 - src/mainboard/asrock/b75pro3-m/acpi/pci.asl | 1 - src/mainboard/asrock/b75pro3-m/acpi/platform.asl | 1 - src/mainboard/asrock/b75pro3-m/acpi/superio.asl | 3 --- src/mainboard/asrock/b75pro3-m/acpi_tables.c | 2 -- src/mainboard/asrock/b75pro3-m/devicetree.cb | 1 - src/mainboard/asrock/b75pro3-m/dsdt.asl | 2 -- src/mainboard/asrock/b75pro3-m/early_init.c | 1 - src/mainboard/asrock/b75pro3-m/gpio.c | 2 -- src/mainboard/asrock/b75pro3-m/hda_verb.c | 2 -- src/mainboard/asrock/b75pro3-m/mainboard.c | 1 - src/mainboard/asrock/e350m1/BiosCallOuts.c | 1 - src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asrock/e350m1/Makefile.inc | 1 - src/mainboard/asrock/e350m1/OemCustomize.c | 1 - src/mainboard/asrock/e350m1/OptionsIds.h | 1 - src/mainboard/asrock/e350m1/acpi/gpe.asl | 1 - src/mainboard/asrock/e350m1/acpi/mainboard.asl | 1 - src/mainboard/asrock/e350m1/acpi/routing.asl | 1 - src/mainboard/asrock/e350m1/acpi/sata.asl | 1 - src/mainboard/asrock/e350m1/acpi/sleep.asl | 1 - src/mainboard/asrock/e350m1/acpi/usb_oc.asl | 1 - src/mainboard/asrock/e350m1/acpi_tables.c | 1 - src/mainboard/asrock/e350m1/bootblock.c | 1 - src/mainboard/asrock/e350m1/buildOpts.c | 1 - src/mainboard/asrock/e350m1/cmos.layout | 1 - src/mainboard/asrock/e350m1/devicetree.cb | 1 - src/mainboard/asrock/e350m1/dsdt.asl | 1 - src/mainboard/asrock/e350m1/irq_tables.c | 1 - src/mainboard/asrock/e350m1/mainboard.c | 1 - src/mainboard/asrock/e350m1/mptable.c | 1 - src/mainboard/asrock/e350m1/platform_cfg.h | 1 - src/mainboard/asrock/g41c-gs/Kconfig | 2 -- src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/asrock/g41c-gs/acpi_tables.c | 2 -- src/mainboard/asrock/g41c-gs/cmos.layout | 2 -- src/mainboard/asrock/g41c-gs/cstates.c | 1 - src/mainboard/asrock/g41c-gs/dsdt.asl | 2 -- src/mainboard/asrock/g41c-gs/early_init.c | 2 -- src/mainboard/asrock/g41c-gs/hda_verb.c | 1 - .../asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb | 1 - src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c | 1 - src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb | 1 - src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c | 1 - src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 1 - src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c | 1 - src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb | 1 - src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c | 1 - .../asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb | 1 - src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c | 1 - src/mainboard/asrock/h110m/Makefile.inc | 2 -- src/mainboard/asrock/h110m/acpi/dptf.asl | 3 --- src/mainboard/asrock/h110m/bootblock.c | 2 -- src/mainboard/asrock/h110m/cmos.layout | 2 -- src/mainboard/asrock/h110m/devicetree.cb | 2 -- src/mainboard/asrock/h110m/dsdt.asl | 4 ---- src/mainboard/asrock/h110m/gma-mainboard.ads | 2 -- src/mainboard/asrock/h110m/hda_verb.c | 3 --- src/mainboard/asrock/h110m/include/gpio.h | 1 - src/mainboard/asrock/h110m/mainboard.c | 2 -- src/mainboard/asrock/h110m/ramstage.c | 2 -- src/mainboard/asrock/h110m/romstage.c | 2 -- src/mainboard/asrock/h81m-hds/Kconfig | 1 - src/mainboard/asrock/h81m-hds/Makefile.inc | 1 - src/mainboard/asrock/h81m-hds/acpi/platform.asl | 1 - src/mainboard/asrock/h81m-hds/acpi/superio.asl | 1 - src/mainboard/asrock/h81m-hds/acpi_tables.c | 1 - src/mainboard/asrock/h81m-hds/bootblock.c | 3 --- src/mainboard/asrock/h81m-hds/cmos.layout | 2 -- src/mainboard/asrock/h81m-hds/devicetree.cb | 1 - src/mainboard/asrock/h81m-hds/dsdt.asl | 1 - src/mainboard/asrock/h81m-hds/gma-mainboard.ads | 1 - src/mainboard/asrock/h81m-hds/gpio.c | 1 - src/mainboard/asrock/h81m-hds/hda_verb.c | 1 - src/mainboard/asrock/h81m-hds/mainboard.c | 1 - src/mainboard/asrock/h81m-hds/romstage.c | 3 --- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 1 - src/mainboard/asrock/imb-a180/Kconfig | 1 - src/mainboard/asrock/imb-a180/Makefile.inc | 1 - src/mainboard/asrock/imb-a180/OemCustomize.c | 1 - src/mainboard/asrock/imb-a180/OptionsIds.h | 1 - src/mainboard/asrock/imb-a180/acpi/gpe.asl | 1 - src/mainboard/asrock/imb-a180/acpi/ide.asl | 1 - src/mainboard/asrock/imb-a180/acpi/mainboard.asl | 1 - src/mainboard/asrock/imb-a180/acpi/routing.asl | 2 -- src/mainboard/asrock/imb-a180/acpi/sata.asl | 1 - src/mainboard/asrock/imb-a180/acpi/si.asl | 1 - src/mainboard/asrock/imb-a180/acpi/sleep.asl | 1 - src/mainboard/asrock/imb-a180/acpi/usb_oc.asl | 2 -- src/mainboard/asrock/imb-a180/acpi_tables.c | 1 - src/mainboard/asrock/imb-a180/buildOpts.c | 1 - src/mainboard/asrock/imb-a180/cmos.layout | 1 - src/mainboard/asrock/imb-a180/devicetree.cb | 1 - src/mainboard/asrock/imb-a180/dsdt.asl | 2 -- src/mainboard/asrock/imb-a180/irq_tables.c | 1 - src/mainboard/asrock/imb-a180/mainboard.c | 1 - src/mainboard/asrock/imb-a180/mptable.c | 1 - src/mainboard/asus/Kconfig | 1 - src/mainboard/asus/am1i-a/BiosCallOuts.c | 3 --- src/mainboard/asus/am1i-a/Makefile.inc | 1 - src/mainboard/asus/am1i-a/OemCustomize.c | 2 -- src/mainboard/asus/am1i-a/OptionsIds.h | 1 - src/mainboard/asus/am1i-a/acpi/mainboard.asl | 1 - src/mainboard/asus/am1i-a/acpi/routing.asl | 3 --- src/mainboard/asus/am1i-a/acpi/sata.asl | 1 - src/mainboard/asus/am1i-a/acpi/si.asl | 1 - src/mainboard/asus/am1i-a/acpi/sleep.asl | 1 - src/mainboard/asus/am1i-a/acpi/superio.asl | 3 --- src/mainboard/asus/am1i-a/acpi_tables.c | 1 - src/mainboard/asus/am1i-a/buildOpts.c | 1 - src/mainboard/asus/am1i-a/cmos.layout | 2 -- src/mainboard/asus/am1i-a/devicetree.cb | 3 --- src/mainboard/asus/am1i-a/dsdt.asl | 4 ---- src/mainboard/asus/am1i-a/irq_tables.c | 1 - src/mainboard/asus/am1i-a/mainboard.c | 4 ---- src/mainboard/asus/am1i-a/mptable.c | 2 -- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 1 - src/mainboard/asus/f2a85-m/Kconfig | 2 -- src/mainboard/asus/f2a85-m/Makefile.inc | 1 - src/mainboard/asus/f2a85-m/OemCustomize.c | 1 - src/mainboard/asus/f2a85-m/OptionsIds.h | 1 - src/mainboard/asus/f2a85-m/acpi/cpstate.asl | 1 - src/mainboard/asus/f2a85-m/acpi/gpe.asl | 1 - src/mainboard/asus/f2a85-m/acpi/mainboard.asl | 1 - src/mainboard/asus/f2a85-m/acpi/routing.asl | 2 -- src/mainboard/asus/f2a85-m/acpi/si.asl | 1 - src/mainboard/asus/f2a85-m/acpi/sleep.asl | 1 - src/mainboard/asus/f2a85-m/acpi/usb_oc.asl | 2 -- src/mainboard/asus/f2a85-m/acpi_tables.c | 1 - src/mainboard/asus/f2a85-m/bootblock.c | 2 -- src/mainboard/asus/f2a85-m/buildOpts.c | 1 - src/mainboard/asus/f2a85-m/cmos.layout | 1 - src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb | 1 - src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb | 1 - src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb | 1 - src/mainboard/asus/f2a85-m/dsdt.asl | 2 -- src/mainboard/asus/f2a85-m/irq_tables.c | 1 - src/mainboard/asus/f2a85-m/mainboard.c | 1 - src/mainboard/asus/f2a85-m/mptable.c | 1 - src/mainboard/asus/f2a85-m/romstage.c | 2 -- src/mainboard/asus/h61m-cs/acpi/platform.asl | 1 - src/mainboard/asus/h61m-cs/acpi_tables.c | 2 -- src/mainboard/asus/h61m-cs/cmos.layout | 2 -- src/mainboard/asus/h61m-cs/devicetree.cb | 1 - src/mainboard/asus/h61m-cs/dsdt.asl | 1 - src/mainboard/asus/h61m-cs/early_init.c | 2 -- src/mainboard/asus/h61m-cs/gma-mainboard.ads | 1 - src/mainboard/asus/h61m-cs/gpio.c | 2 -- src/mainboard/asus/h61m-cs/hda_verb.c | 2 -- src/mainboard/asus/h61m-cs/mainboard.c | 2 -- src/mainboard/asus/maximus_iv_gene-z/Kconfig | 1 - src/mainboard/asus/maximus_iv_gene-z/Makefile.inc | 1 - src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl | 1 - src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl | 1 - src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c | 1 - src/mainboard/asus/maximus_iv_gene-z/cmos.layout | 2 -- src/mainboard/asus/maximus_iv_gene-z/devicetree.cb | 1 - src/mainboard/asus/maximus_iv_gene-z/dsdt.asl | 1 - src/mainboard/asus/maximus_iv_gene-z/early_init.c | 1 - src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads | 1 - src/mainboard/asus/maximus_iv_gene-z/gpio.c | 1 - src/mainboard/asus/maximus_iv_gene-z/hda_verb.c | 1 - src/mainboard/asus/maximus_iv_gene-z/mainboard.c | 1 - src/mainboard/asus/p2b-d/Kconfig | 1 - src/mainboard/asus/p2b-d/irq_tables.c | 1 - src/mainboard/asus/p2b-d/mptable.c | 1 - src/mainboard/asus/p2b-d/romstage.c | 1 - src/mainboard/asus/p2b-ds/Kconfig | 1 - src/mainboard/asus/p2b-ds/irq_tables.c | 1 - src/mainboard/asus/p2b-ds/mptable.c | 1 - src/mainboard/asus/p2b-ds/romstage.c | 1 - src/mainboard/asus/p2b-f/Kconfig | 1 - src/mainboard/asus/p2b-f/irq_tables.c | 1 - src/mainboard/asus/p2b-f/romstage.c | 1 - src/mainboard/asus/p2b-ls/Kconfig | 1 - src/mainboard/asus/p2b-ls/acpi_tables.c | 1 - src/mainboard/asus/p2b-ls/dsdt.asl | 1 - src/mainboard/asus/p2b-ls/irq_tables.c | 1 - src/mainboard/asus/p2b-ls/romstage.c | 1 - src/mainboard/asus/p2b/Kconfig | 1 - src/mainboard/asus/p2b/acpi_tables.c | 1 - src/mainboard/asus/p2b/dsdt.asl | 2 -- src/mainboard/asus/p2b/irq_tables.c | 1 - src/mainboard/asus/p2b/romstage.c | 1 - src/mainboard/asus/p3b-f/Kconfig | 1 - src/mainboard/asus/p3b-f/irq_tables.c | 1 - src/mainboard/asus/p3b-f/romstage.c | 1 - src/mainboard/asus/p5gc-mx/Kconfig | 2 -- src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/asus/p5gc-mx/acpi/mainboard.asl | 1 - src/mainboard/asus/p5gc-mx/acpi_tables.c | 1 - src/mainboard/asus/p5gc-mx/cmos.layout | 1 - src/mainboard/asus/p5gc-mx/devicetree.cb | 2 -- src/mainboard/asus/p5gc-mx/dsdt.asl | 1 - src/mainboard/asus/p5gc-mx/early_init.c | 3 --- src/mainboard/asus/p5gc-mx/gpio.c | 1 - src/mainboard/asus/p5gc-mx/hda_verb.c | 1 - src/mainboard/asus/p5qc/Kconfig | 3 --- src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl | 1 - src/mainboard/asus/p5qc/acpi_tables.c | 2 -- src/mainboard/asus/p5qc/cmos.layout | 2 -- src/mainboard/asus/p5qc/dsdt.asl | 2 -- src/mainboard/asus/p5qc/early_init.c | 1 - src/mainboard/asus/p5qc/gpio.c | 1 - src/mainboard/asus/p5qc/hda_verb.c | 1 - src/mainboard/asus/p5qc/variants/p5q/devicetree.cb | 3 --- src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb | 2 -- src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb | 2 -- src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb | 2 -- src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c | 1 - src/mainboard/asus/p5qpl-am/Kconfig | 2 -- src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/asus/p5qpl-am/acpi_tables.c | 2 -- src/mainboard/asus/p5qpl-am/cmos.layout | 2 -- src/mainboard/asus/p5qpl-am/cstates.c | 1 - src/mainboard/asus/p5qpl-am/devicetree.cb | 2 -- src/mainboard/asus/p5qpl-am/dsdt.asl | 2 -- src/mainboard/asus/p5qpl-am/early_init.c | 2 -- src/mainboard/asus/p5qpl-am/hda_verb.c | 1 - src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c | 1 - .../asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb | 2 -- src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c | 1 - src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb | 1 - src/mainboard/asus/p8h61-m_lx/Kconfig | 1 - src/mainboard/asus/p8h61-m_lx/Makefile.inc | 1 - src/mainboard/asus/p8h61-m_lx/acpi/platform.asl | 1 - src/mainboard/asus/p8h61-m_lx/acpi/superio.asl | 1 - src/mainboard/asus/p8h61-m_lx/acpi_tables.c | 1 - src/mainboard/asus/p8h61-m_lx/cmos.layout | 2 -- src/mainboard/asus/p8h61-m_lx/devicetree.cb | 1 - src/mainboard/asus/p8h61-m_lx/dsdt.asl | 1 - src/mainboard/asus/p8h61-m_lx/early_init.c | 1 - src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads | 1 - src/mainboard/asus/p8h61-m_lx/gpio.c | 1 - src/mainboard/asus/p8h61-m_lx/hda_verb.c | 1 - src/mainboard/asus/p8h61-m_lx/mainboard.c | 1 - src/mainboard/asus/p8h61-m_pro/Kconfig | 1 - src/mainboard/asus/p8h61-m_pro/acpi/platform.asl | 1 - src/mainboard/asus/p8h61-m_pro/acpi/superio.asl | 1 - src/mainboard/asus/p8h61-m_pro/acpi_tables.c | 3 --- src/mainboard/asus/p8h61-m_pro/cmos.layout | 2 -- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 1 - src/mainboard/asus/p8h61-m_pro/dsdt.asl | 1 - src/mainboard/asus/p8h61-m_pro/early_init.c | 1 - src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads | 1 - src/mainboard/asus/p8h61-m_pro/gpio.c | 1 - src/mainboard/asus/p8h61-m_pro/hda_verb.c | 1 - src/mainboard/asus/p8z77-m_pro/Kconfig | 1 - src/mainboard/asus/p8z77-m_pro/Kconfig.name | 1 - src/mainboard/asus/p8z77-m_pro/Makefile.inc | 1 - src/mainboard/asus/p8z77-m_pro/acpi/platform.asl | 1 - src/mainboard/asus/p8z77-m_pro/acpi/superio.asl | 1 - src/mainboard/asus/p8z77-m_pro/acpi_tables.c | 1 - src/mainboard/asus/p8z77-m_pro/cmos.default | 1 - src/mainboard/asus/p8z77-m_pro/cmos.layout | 1 - src/mainboard/asus/p8z77-m_pro/devicetree.cb | 1 - src/mainboard/asus/p8z77-m_pro/dsdt.asl | 1 - src/mainboard/asus/p8z77-m_pro/early_init.c | 1 - src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads | 1 - src/mainboard/asus/p8z77-m_pro/gpio.c | 3 --- src/mainboard/asus/p8z77-m_pro/hda_verb.c | 3 --- src/mainboard/asus/p8z77-m_pro/mainboard.c | 1 - src/mainboard/asus/p8z77-v_lx2/Kconfig | 1 - src/mainboard/asus/p8z77-v_lx2/devicetree.cb | 1 - src/mainboard/asus/p8z77-v_lx2/dsdt.asl | 1 - src/mainboard/bap/Kconfig | 2 -- src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex | 3 --- src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex | 3 --- src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 1 - src/mainboard/bap/ode_e20XX/Kconfig | 2 -- src/mainboard/bap/ode_e20XX/Makefile.inc | 2 -- src/mainboard/bap/ode_e20XX/OemCustomize.c | 1 - src/mainboard/bap/ode_e20XX/OptionsIds.h | 1 - src/mainboard/bap/ode_e20XX/acpi/gpe.asl | 1 - src/mainboard/bap/ode_e20XX/acpi/ide.asl | 1 - src/mainboard/bap/ode_e20XX/acpi/mainboard.asl | 1 - src/mainboard/bap/ode_e20XX/acpi/routing.asl | 2 -- src/mainboard/bap/ode_e20XX/acpi/si.asl | 1 - src/mainboard/bap/ode_e20XX/acpi/sleep.asl | 1 - src/mainboard/bap/ode_e20XX/acpi/superio.asl | 3 --- src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl | 2 -- src/mainboard/bap/ode_e20XX/acpi_tables.c | 1 - src/mainboard/bap/ode_e20XX/buildOpts.c | 1 - src/mainboard/bap/ode_e20XX/cmos.layout | 1 - src/mainboard/bap/ode_e20XX/devicetree.cb | 1 - src/mainboard/bap/ode_e20XX/dsdt.asl | 2 -- src/mainboard/bap/ode_e20XX/irq_tables.c | 1 - src/mainboard/bap/ode_e20XX/mainboard.c | 3 --- src/mainboard/bap/ode_e20XX/mptable.c | 1 - src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex | 3 --- src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex | 3 --- src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex | 3 --- src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 1 - src/mainboard/bap/ode_e21XX/Kconfig | 1 - src/mainboard/bap/ode_e21XX/Makefile.inc | 1 - src/mainboard/bap/ode_e21XX/OemCustomize.c | 1 - src/mainboard/bap/ode_e21XX/acpi/gpe.asl | 1 - src/mainboard/bap/ode_e21XX/acpi/mainboard.asl | 1 - src/mainboard/bap/ode_e21XX/acpi/routing.asl | 2 -- src/mainboard/bap/ode_e21XX/acpi/si.asl | 1 - src/mainboard/bap/ode_e21XX/acpi/sleep.asl | 1 - src/mainboard/bap/ode_e21XX/acpi/superio.asl | 3 --- src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl | 2 -- src/mainboard/bap/ode_e21XX/acpi_tables.c | 1 - src/mainboard/bap/ode_e21XX/cmos.layout | 1 - src/mainboard/bap/ode_e21XX/devicetree.cb | 1 - src/mainboard/bap/ode_e21XX/dsdt.asl | 2 -- src/mainboard/bap/ode_e21XX/irq_tables.c | 1 - src/mainboard/bap/ode_e21XX/mainboard.c | 1 - src/mainboard/bap/ode_e21XX/mptable.c | 1 - src/mainboard/bap/ode_e21XX/romstage.c | 1 - src/mainboard/biostar/Kconfig | 2 -- src/mainboard/biostar/a68n_5200/BiosCallOuts.c | 1 - src/mainboard/biostar/a68n_5200/Kconfig | 3 --- src/mainboard/biostar/a68n_5200/Makefile.inc | 1 - src/mainboard/biostar/a68n_5200/OemCustomize.c | 1 - src/mainboard/biostar/a68n_5200/OptionsIds.h | 1 - src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl | 1 - src/mainboard/biostar/a68n_5200/acpi/gpe.asl | 1 - src/mainboard/biostar/a68n_5200/acpi/ide.asl | 1 - src/mainboard/biostar/a68n_5200/acpi/mainboard.asl | 1 - src/mainboard/biostar/a68n_5200/acpi/routing.asl | 2 -- src/mainboard/biostar/a68n_5200/acpi/sata.asl | 1 - src/mainboard/biostar/a68n_5200/acpi/si.asl | 1 - src/mainboard/biostar/a68n_5200/acpi/sleep.asl | 1 - src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl | 2 -- src/mainboard/biostar/a68n_5200/acpi_tables.c | 1 - src/mainboard/biostar/a68n_5200/bootblock.c | 3 --- src/mainboard/biostar/a68n_5200/buildOpts.c | 1 - src/mainboard/biostar/a68n_5200/cmos.layout | 1 - src/mainboard/biostar/a68n_5200/devicetree.cb | 3 --- src/mainboard/biostar/a68n_5200/dsdt.asl | 2 -- src/mainboard/biostar/a68n_5200/irq_tables.c | 1 - src/mainboard/biostar/a68n_5200/mainboard.c | 1 - src/mainboard/biostar/a68n_5200/mptable.c | 1 - src/mainboard/biostar/am1ml/BiosCallOuts.c | 2 -- src/mainboard/biostar/am1ml/Kconfig | 2 -- src/mainboard/biostar/am1ml/Makefile.inc | 1 - src/mainboard/biostar/am1ml/OemCustomize.c | 1 - src/mainboard/biostar/am1ml/OptionsIds.h | 1 - src/mainboard/biostar/am1ml/acpi/flag0.asl | 1 - src/mainboard/biostar/am1ml/acpi/gpe.asl | 1 - src/mainboard/biostar/am1ml/acpi/ide.asl | 1 - src/mainboard/biostar/am1ml/acpi/mainboard.asl | 1 - src/mainboard/biostar/am1ml/acpi/routing.asl | 2 -- src/mainboard/biostar/am1ml/acpi/sata.asl | 1 - src/mainboard/biostar/am1ml/acpi/si.asl | 1 - src/mainboard/biostar/am1ml/acpi/sio.asl | 1 - src/mainboard/biostar/am1ml/acpi/sleep.asl | 1 - src/mainboard/biostar/am1ml/acpi/superio.asl | 2 -- src/mainboard/biostar/am1ml/acpi/usb_oc.asl | 2 -- src/mainboard/biostar/am1ml/acpi_tables.c | 1 - src/mainboard/biostar/am1ml/buildOpts.c | 1 - src/mainboard/biostar/am1ml/cmos.layout | 1 - src/mainboard/biostar/am1ml/devicetree.cb | 2 -- src/mainboard/biostar/am1ml/dsdt.asl | 3 --- src/mainboard/biostar/am1ml/irq_tables.c | 1 - src/mainboard/biostar/am1ml/mainboard.c | 4 ---- src/mainboard/biostar/am1ml/mptable.c | 1 - src/mainboard/cavium/Kconfig | 1 - src/mainboard/cavium/cn8100_sff_evb/Kconfig | 1 - src/mainboard/cavium/cn8100_sff_evb/Makefile.inc | 1 - src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c | 1 - src/mainboard/cavium/cn8100_sff_evb/bootblock.c | 1 - src/mainboard/cavium/cn8100_sff_evb/devicetree.cb | 1 - src/mainboard/cavium/cn8100_sff_evb/mainboard.c | 2 -- src/mainboard/cavium/cn8100_sff_evb/romstage.c | 1 - src/mainboard/compulab/intense_pc/acpi/ec.asl | 1 - src/mainboard/compulab/intense_pc/acpi/platform.asl | 1 - src/mainboard/compulab/intense_pc/acpi/superio.asl | 1 - src/mainboard/compulab/intense_pc/acpi_tables.c | 3 --- src/mainboard/compulab/intense_pc/devicetree.cb | 1 - src/mainboard/compulab/intense_pc/dsdt.asl | 1 - src/mainboard/compulab/intense_pc/early_init.c | 1 - src/mainboard/compulab/intense_pc/gpio.c | 2 -- src/mainboard/compulab/intense_pc/hda_verb.c | 3 --- src/mainboard/compulab/intense_pc/mainboard.c | 1 - src/mainboard/elmex/pcm205400/BiosCallOuts.c | 1 - src/mainboard/elmex/pcm205400/Kconfig | 1 - src/mainboard/elmex/pcm205400/Makefile.inc | 1 - src/mainboard/elmex/pcm205400/OemCustomize.c | 1 - src/mainboard/elmex/pcm205400/OptionsIds.h | 1 - src/mainboard/elmex/pcm205400/acpi/gpe.asl | 1 - src/mainboard/elmex/pcm205400/acpi/ide.asl | 1 - src/mainboard/elmex/pcm205400/acpi/mainboard.asl | 1 - src/mainboard/elmex/pcm205400/acpi/routing.asl | 1 - src/mainboard/elmex/pcm205400/acpi/sata.asl | 1 - src/mainboard/elmex/pcm205400/acpi/sleep.asl | 1 - src/mainboard/elmex/pcm205400/acpi/usb_oc.asl | 1 - src/mainboard/elmex/pcm205400/acpi_tables.c | 1 - src/mainboard/elmex/pcm205400/bootblock.c | 1 - src/mainboard/elmex/pcm205400/buildOpts.c | 1 - src/mainboard/elmex/pcm205400/cmos.layout | 1 - src/mainboard/elmex/pcm205400/devicetree.cb | 1 - src/mainboard/elmex/pcm205400/dsdt.asl | 1 - src/mainboard/elmex/pcm205400/irq_tables.c | 1 - src/mainboard/elmex/pcm205400/mainboard.c | 2 -- src/mainboard/elmex/pcm205400/mptable.c | 2 -- src/mainboard/elmex/pcm205400/platform_cfg.h | 1 - src/mainboard/elmex/pcm205401/Kconfig | 1 - src/mainboard/emulation/qemu-aarch64/Kconfig | 1 - src/mainboard/emulation/qemu-aarch64/Makefile.inc | 1 - src/mainboard/emulation/qemu-aarch64/bootblock_custom.S | 1 - src/mainboard/emulation/qemu-aarch64/cbmem.c | 1 - src/mainboard/emulation/qemu-aarch64/devicetree.cb | 1 - .../emulation/qemu-aarch64/include/mainboard/addressmap.h | 1 - src/mainboard/emulation/qemu-aarch64/mainboard.c | 1 - src/mainboard/emulation/qemu-aarch64/media.c | 1 - src/mainboard/emulation/qemu-aarch64/memlayout.ld | 1 - src/mainboard/emulation/qemu-aarch64/mmio.c | 1 - src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/mainboard/emulation/qemu-armv7/Makefile.inc | 1 - src/mainboard/emulation/qemu-armv7/devicetree.cb | 1 - src/mainboard/emulation/qemu-armv7/mainboard.c | 1 - src/mainboard/emulation/qemu-armv7/media.c | 1 - src/mainboard/emulation/qemu-armv7/memlayout.ld | 1 - src/mainboard/emulation/qemu-armv7/romstage.c | 1 - src/mainboard/emulation/qemu-armv7/timer.c | 1 - src/mainboard/emulation/qemu-i440fx/acpi_tables.c | 1 - src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 -- src/mainboard/emulation/qemu-i440fx/memmap.c | 1 - src/mainboard/emulation/qemu-i440fx/memory.h | 2 -- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 -- src/mainboard/emulation/qemu-power8/Kconfig | 1 - src/mainboard/emulation/qemu-power8/Makefile.inc | 1 - src/mainboard/emulation/qemu-power8/bootblock.c | 1 - src/mainboard/emulation/qemu-power8/cbmem.c | 1 - src/mainboard/emulation/qemu-power8/devicetree.cb | 1 - src/mainboard/emulation/qemu-power8/mainboard.c | 1 - src/mainboard/emulation/qemu-power8/memlayout.ld | 2 -- src/mainboard/emulation/qemu-power8/romstage.c | 1 - src/mainboard/emulation/qemu-power8/uart.c | 1 - src/mainboard/emulation/qemu-q35/acpi_tables.c | 1 - src/mainboard/emulation/qemu-q35/mainboard.c | 2 -- src/mainboard/emulation/qemu-q35/romstage.c | 2 -- src/mainboard/emulation/qemu-riscv/Kconfig | 1 - src/mainboard/emulation/qemu-riscv/Makefile.inc | 1 - src/mainboard/emulation/qemu-riscv/clint.c | 1 - src/mainboard/emulation/qemu-riscv/devicetree.cb | 1 - .../emulation/qemu-riscv/include/mainboard/addressmap.h | 1 - src/mainboard/emulation/qemu-riscv/mainboard.c | 1 - src/mainboard/emulation/qemu-riscv/memlayout.ld | 1 - src/mainboard/emulation/qemu-riscv/rom_media.c | 1 - src/mainboard/emulation/qemu-riscv/romstage.c | 1 - src/mainboard/emulation/qemu-riscv/uart.c | 1 - src/mainboard/emulation/spike-riscv/Kconfig | 1 - src/mainboard/emulation/spike-riscv/Makefile.inc | 1 - src/mainboard/emulation/spike-riscv/clint.c | 1 - src/mainboard/emulation/spike-riscv/devicetree.cb | 1 - src/mainboard/emulation/spike-riscv/mainboard.c | 1 - src/mainboard/emulation/spike-riscv/memlayout.ld | 1 - src/mainboard/emulation/spike-riscv/rom_media.c | 2 -- src/mainboard/emulation/spike-riscv/romstage.c | 1 - src/mainboard/emulation/spike-riscv/uart.c | 1 - src/mainboard/facebook/fbg1701/Kconfig | 1 - src/mainboard/facebook/fbg1701/Makefile.inc | 3 --- src/mainboard/facebook/fbg1701/acpi/mainboard.asl | 3 --- src/mainboard/facebook/fbg1701/acpi/superio.asl | 3 --- src/mainboard/facebook/fbg1701/acpi_tables.c | 3 --- src/mainboard/facebook/fbg1701/board_mboot.h | 1 - src/mainboard/facebook/fbg1701/board_verified_boot.c | 1 - src/mainboard/facebook/fbg1701/board_verified_boot.h | 1 - src/mainboard/facebook/fbg1701/cmos.layout | 3 --- src/mainboard/facebook/fbg1701/com_init.c | 3 --- src/mainboard/facebook/fbg1701/cpld.c | 1 - src/mainboard/facebook/fbg1701/cpld.h | 1 - src/mainboard/facebook/fbg1701/dsdt.asl | 4 ---- src/mainboard/facebook/fbg1701/fadt.c | 3 --- src/mainboard/facebook/fbg1701/gpio.c | 3 --- src/mainboard/facebook/fbg1701/hda_verb.c | 1 - src/mainboard/facebook/fbg1701/irqroute.c | 1 - src/mainboard/facebook/fbg1701/irqroute.h | 3 --- src/mainboard/facebook/fbg1701/mainboard.c | 4 ---- src/mainboard/facebook/fbg1701/manifest.h | 1 - src/mainboard/facebook/fbg1701/ramstage.c | 2 -- src/mainboard/facebook/fbg1701/romstage.c | 3 --- .../facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex | 2 -- .../facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex | 1 - .../facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex | 1 - src/mainboard/facebook/fbg1701/w25q64.c | 3 --- src/mainboard/facebook/monolith/Makefile.inc | 3 --- src/mainboard/facebook/monolith/acpi/dptf.asl | 2 -- src/mainboard/facebook/monolith/acpi/ec.asl | 1 - src/mainboard/facebook/monolith/acpi/mainboard.asl | 3 --- src/mainboard/facebook/monolith/acpi/superio.asl | 3 --- src/mainboard/facebook/monolith/cmos.layout | 3 --- src/mainboard/facebook/monolith/com_init.c | 3 --- src/mainboard/facebook/monolith/dsdt.asl | 4 ---- src/mainboard/facebook/monolith/gpio.h | 3 --- src/mainboard/facebook/monolith/mainboard.c | 4 ---- src/mainboard/facebook/monolith/onboard.h | 3 --- src/mainboard/facebook/monolith/ramstage.c | 2 -- src/mainboard/facebook/monolith/romstage.c | 2 -- src/mainboard/facebook/monolith/spd/Makefile.inc | 3 --- src/mainboard/facebook/monolith/spd/spd.h | 2 -- src/mainboard/facebook/monolith/spd/spd_util.c | 1 - src/mainboard/foxconn/Kconfig | 1 - src/mainboard/foxconn/d41s/Kconfig | 1 - src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/foxconn/d41s/acpi/superio.asl | 2 -- src/mainboard/foxconn/d41s/acpi_tables.c | 1 - src/mainboard/foxconn/d41s/cmos.layout | 2 -- src/mainboard/foxconn/d41s/cstates.c | 1 - src/mainboard/foxconn/d41s/devicetree.cb | 2 -- src/mainboard/foxconn/d41s/dsdt.asl | 2 -- src/mainboard/foxconn/d41s/early_init.c | 2 -- src/mainboard/foxconn/d41s/gpio.c | 2 -- src/mainboard/foxconn/d41s/hda_verb.c | 1 - src/mainboard/foxconn/d41s/mainboard.c | 1 - src/mainboard/foxconn/g41s-k/Kconfig | 2 -- src/mainboard/foxconn/g41s-k/acpi/superio.asl | 2 -- src/mainboard/foxconn/g41s-k/acpi_tables.c | 3 --- src/mainboard/foxconn/g41s-k/cmos.layout | 2 -- src/mainboard/foxconn/g41s-k/cstates.c | 2 -- src/mainboard/foxconn/g41s-k/devicetree.cb | 3 --- src/mainboard/foxconn/g41s-k/dsdt.asl | 2 -- src/mainboard/foxconn/g41s-k/early_init.c | 3 --- src/mainboard/foxconn/g41s-k/gpio.c | 2 -- src/mainboard/foxconn/g41s-k/hda_verb.c | 2 -- .../foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl | 2 -- .../foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl | 2 -- 734 files changed, 987 deletions(-) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index ee923265e9..06185ec6bf 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index e97a3bad78..76f59abe4c 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index dd7133142c..6506e151de 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index f4d77696af..0bb9658541 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl index 6429bc604a..63cbd02780 100644 --- a/src/mainboard/amd/gardenia/acpi/gpe.asl +++ b/src/mainboard/amd/gardenia/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/acpi/mainboard.asl b/src/mainboard/amd/gardenia/acpi/mainboard.asl index db5731f088..b74b07c2be 100644 --- a/src/mainboard/amd/gardenia/acpi/mainboard.asl +++ b/src/mainboard/amd/gardenia/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/acpi/routing.asl b/src/mainboard/amd/gardenia/acpi/routing.asl index f81b94c2e2..7c120dde2b 100644 --- a/src/mainboard/amd/gardenia/acpi/routing.asl +++ b/src/mainboard/amd/gardenia/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/acpi/sleep.asl b/src/mainboard/amd/gardenia/acpi/sleep.asl index 58f0752f30..b23f09d779 100644 --- a/src/mainboard/amd/gardenia/acpi/sleep.asl +++ b/src/mainboard/amd/gardenia/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/acpi/usb_oc.asl b/src/mainboard/amd/gardenia/acpi/usb_oc.asl index ed32c70149..69c42c0af7 100644 --- a/src/mainboard/amd/gardenia/acpi/usb_oc.asl +++ b/src/mainboard/amd/gardenia/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c index 0d837ccc34..710ff78275 100644 --- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c +++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index 2f4be03ddf..c3833f7aca 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb index 027a820466..3a85c04ae0 100644 --- a/src/mainboard/amd/gardenia/devicetree.cb +++ b/src/mainboard/amd/gardenia/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 52bd90b9d2..f1a49ef5c9 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 837d031abd..1d58a604d1 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h index 1d3a8a2508..da75c10895 100644 --- a/src/mainboard/amd/gardenia/gpio.h +++ b/src/mainboard/amd/gardenia/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c index 76e796a647..761fd060a3 100644 --- a/src/mainboard/amd/gardenia/irq_tables.c +++ b/src/mainboard/amd/gardenia/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 26c80c037d..01c7061607 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index 5bb70e9449..130a728483 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 9a7f168f25..979facc851 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 0ae9f28f98..f88929a94c 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index e24af4044a..db66a2fd21 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2010-2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc index bf86007cec..f0a8fe6109 100644 --- a/src/mainboard/amd/inagua/Makefile.inc +++ b/src/mainboard/amd/inagua/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index fa2d7e4b51..4e02ba0155 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ b/src/mainboard/amd/inagua/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 3cf38c035a..af4e2e48b7 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi/ide.asl b/src/mainboard/amd/inagua/acpi/ide.asl index 59ea078593..6286ade685 100644 --- a/src/mainboard/amd/inagua/acpi/ide.asl +++ b/src/mainboard/amd/inagua/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi/mainboard.asl b/src/mainboard/amd/inagua/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/amd/inagua/acpi/mainboard.asl +++ b/src/mainboard/amd/inagua/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl index 537bcacaa1..51215f5de6 100644 --- a/src/mainboard/amd/inagua/acpi/routing.asl +++ b/src/mainboard/amd/inagua/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/amd/inagua/acpi/sata.asl +++ b/src/mainboard/amd/inagua/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl index 47de049dbc..08144ff427 100644 --- a/src/mainboard/amd/inagua/acpi/sleep.asl +++ b/src/mainboard/amd/inagua/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl index a209909b32..5b22875dd1 100644 --- a/src/mainboard/amd/inagua/acpi/usb_oc.asl +++ b/src/mainboard/amd/inagua/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/bootblock.c b/src/mainboard/amd/inagua/bootblock.c index 78d8fca8f3..711d075e19 100644 --- a/src/mainboard/amd/inagua/bootblock.c +++ b/src/mainboard/amd/inagua/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index fe6fac03cb..6ef93c750d 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index f9f52f7546..275de95ad2 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 946bd59078..3855f99048 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 5496288651..13df85b261 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 47a267b323..87c26024b2 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 1b4e64aa1a..e49ccf172f 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index d39a3abe70..f1898e257d 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 6e29d84179..c86a22722c 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index bd3dd9384c..32af0f6ede 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index df13fa502f..e207c0303a 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ b/src/mainboard/amd/olivehill/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ b/src/mainboard/amd/olivehill/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/ide.asl b/src/mainboard/amd/olivehill/acpi/ide.asl index e7f4625506..e17d93befd 100644 --- a/src/mainboard/amd/olivehill/acpi/ide.asl +++ b/src/mainboard/amd/olivehill/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/mainboard.asl b/src/mainboard/amd/olivehill/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/amd/olivehill/acpi/mainboard.asl +++ b/src/mainboard/amd/olivehill/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/amd/olivehill/acpi/routing.asl +++ b/src/mainboard/amd/olivehill/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/sata.asl b/src/mainboard/amd/olivehill/acpi/sata.asl index 6755258f4d..00d855adb0 100644 --- a/src/mainboard/amd/olivehill/acpi/sata.asl +++ b/src/mainboard/amd/olivehill/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/si.asl b/src/mainboard/amd/olivehill/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/amd/olivehill/acpi/si.asl +++ b/src/mainboard/amd/olivehill/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ b/src/mainboard/amd/olivehill/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi/usb_oc.asl b/src/mainboard/amd/olivehill/acpi/usb_oc.asl index 513d66d1d7..7ceb70ce04 100644 --- a/src/mainboard/amd/olivehill/acpi/usb_oc.asl +++ b/src/mainboard/amd/olivehill/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 65b86b88f7..0b89298b9d 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/amd/olivehill/cmos.layout +++ b/src/mainboard/amd/olivehill/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb index b29d32796d..924cb326dc 100644 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ b/src/mainboard/amd/olivehill/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index c4fc93484e..a7914191d0 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index d8bf5e9806..5f0654ad1e 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index 65e838bd9f..b3e47f8ec3 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 52374f1529..6e1d402833 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index 3ac305db4c..9ba0a63c8f 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.h b/src/mainboard/amd/padmelon/BiosCallOuts.h index 239f7d8f89..661aa5a7ed 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.h +++ b/src/mainboard/amd/padmelon/BiosCallOuts.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index e9d2acb1c2..98753cff6b 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2018 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc index d73c854567..056157096a 100644 --- a/src/mainboard/amd/padmelon/Makefile.inc +++ b/src/mainboard/amd/padmelon/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c index bb92733e1e..099f41f6d6 100644 --- a/src/mainboard/amd/padmelon/OemCustomize.c +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl index c7ea19f8f1..e306202b07 100644 --- a/src/mainboard/amd/padmelon/acpi/gpe.asl +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/acpi/mainboard.asl b/src/mainboard/amd/padmelon/acpi/mainboard.asl index db5731f088..b74b07c2be 100644 --- a/src/mainboard/amd/padmelon/acpi/mainboard.asl +++ b/src/mainboard/amd/padmelon/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl index 64d975e107..b99befab25 100644 --- a/src/mainboard/amd/padmelon/acpi/routing.asl +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl index 58f0752f30..b23f09d779 100644 --- a/src/mainboard/amd/padmelon/acpi/sleep.asl +++ b/src/mainboard/amd/padmelon/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/acpi/usb_oc.asl b/src/mainboard/amd/padmelon/acpi/usb_oc.asl index bd98ed26c9..e1dc35d969 100644 --- a/src/mainboard/amd/padmelon/acpi/usb_oc.asl +++ b/src/mainboard/amd/padmelon/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c index 02f83cc1bd..469b93733c 100644 --- a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index 9886b61b71..e6bd7d792b 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index be0fdfc2a0..4306593602 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 493c4acd78..e39ce0c836 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/fan_init.c b/src/mainboard/amd/padmelon/fan_init.c index 2c3200525d..b6cfd230d3 100644 --- a/src/mainboard/amd/padmelon/fan_init.c +++ b/src/mainboard/amd/padmelon/fan_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Richard Spiegel - * Copyright (C) 2019 Silverback ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index 09e580e89d..ea031bd074 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/gpio.h b/src/mainboard/amd/padmelon/gpio.h index b448d3c733..d95390c352 100644 --- a/src/mainboard/amd/padmelon/gpio.h +++ b/src/mainboard/amd/padmelon/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/hda_verb.c b/src/mainboard/amd/padmelon/hda_verb.c index 23d566de96..b4d80beaa5 100644 --- a/src/mainboard/amd/padmelon/hda_verb.c +++ b/src/mainboard/amd/padmelon/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index c8eef29bf4..4aae6c44de 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 322b22019a..690dcb294c 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 820d43ebf6..4d05e761cf 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index 2eed8b21d3..2ca9481a67 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ b/src/mainboard/amd/parmer/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index 32d5a2a321..f8e34a8995 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/acpi/mainboard.asl b/src/mainboard/amd/parmer/acpi/mainboard.asl index fb75289e55..e97cdecfcc 100644 --- a/src/mainboard/amd/parmer/acpi/mainboard.asl +++ b/src/mainboard/amd/parmer/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl index 56bd465fd5..10b197221a 100644 --- a/src/mainboard/amd/parmer/acpi/routing.asl +++ b/src/mainboard/amd/parmer/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/acpi/si.asl b/src/mainboard/amd/parmer/acpi/si.asl index ff0c3cfc0d..cc27e983e1 100644 --- a/src/mainboard/amd/parmer/acpi/si.asl +++ b/src/mainboard/amd/parmer/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl index d516ccedb0..d5a1f683a8 100644 --- a/src/mainboard/amd/parmer/acpi/sleep.asl +++ b/src/mainboard/amd/parmer/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/acpi/usb_oc.asl b/src/mainboard/amd/parmer/acpi/usb_oc.asl index f5d6980d15..e1dc35d969 100644 --- a/src/mainboard/amd/parmer/acpi/usb_oc.asl +++ b/src/mainboard/amd/parmer/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index fd59a3aade..be2669eeb8 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/bootblock.c b/src/mainboard/amd/parmer/bootblock.c index fea4d7b632..01587d079c 100644 --- a/src/mainboard/amd/parmer/bootblock.c +++ b/src/mainboard/amd/parmer/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 7ff6caa828..6f74eac801 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/amd/parmer/cmos.layout +++ b/src/mainboard/amd/parmer/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index aad3413279..a818ac3e09 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index 77bd704590..14a38c23bf 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index d8bf5e9806..5f0654ad1e 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 0051d74d39..79954aceef 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index c2b9f98e68..8ffd517fe7 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 23a0e9f1e6..152860fad2 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 41bf3c9c2e..f0ccba8395 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index bf86007cec..f0a8fe6109 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 68de6527d8..7249a16a56 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ b/src/mainboard/amd/persimmon/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 3cf38c035a..af4e2e48b7 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi/ide.asl b/src/mainboard/amd/persimmon/acpi/ide.asl index 59ea078593..6286ade685 100644 --- a/src/mainboard/amd/persimmon/acpi/ide.asl +++ b/src/mainboard/amd/persimmon/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi/mainboard.asl b/src/mainboard/amd/persimmon/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/amd/persimmon/acpi/mainboard.asl +++ b/src/mainboard/amd/persimmon/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index 2cf17a7f69..70c5da5ef0 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi/sata.asl b/src/mainboard/amd/persimmon/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/amd/persimmon/acpi/sata.asl +++ b/src/mainboard/amd/persimmon/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl index 47de049dbc..08144ff427 100644 --- a/src/mainboard/amd/persimmon/acpi/sleep.asl +++ b/src/mainboard/amd/persimmon/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi/usb_oc.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl index a209909b32..5b22875dd1 100644 --- a/src/mainboard/amd/persimmon/acpi/usb_oc.asl +++ b/src/mainboard/amd/persimmon/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/bootblock.c b/src/mainboard/amd/persimmon/bootblock.c index 6cd9e2a59a..4afb0970c5 100644 --- a/src/mainboard/amd/persimmon/bootblock.c +++ b/src/mainboard/amd/persimmon/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index d99cc8107c..ceb6b8869b 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index f9f52f7546..275de95ad2 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 73cf19d4d8..7d97d596e7 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 5496288651..13df85b261 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 6ca8a80771..218024134a 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index bc7a3ac38f..7b8476db20 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 660be41aa1..212c4bdcae 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 45a40b497b..751822b682 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index a059403c7b..070d7b4cdd 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index ffea060d80..55bdeb552e 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 45c9f11d57..722d74976d 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index e7a320eda5..c8ff6ea30c 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl index 59ea078593..6286ade685 100644 --- a/src/mainboard/amd/south_station/acpi/ide.asl +++ b/src/mainboard/amd/south_station/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi/mainboard.asl b/src/mainboard/amd/south_station/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/amd/south_station/acpi/mainboard.asl +++ b/src/mainboard/amd/south_station/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index 537bcacaa1..51215f5de6 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/amd/south_station/acpi/sata.asl +++ b/src/mainboard/amd/south_station/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl index 0069aa9db2..f54fe2a9b7 100644 --- a/src/mainboard/amd/south_station/acpi/sleep.asl +++ b/src/mainboard/amd/south_station/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl index 13111b778e..8112d85ee3 100644 --- a/src/mainboard/amd/south_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/south_station/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/bootblock.c b/src/mainboard/amd/south_station/bootblock.c index 6cd9e2a59a..4afb0970c5 100644 --- a/src/mainboard/amd/south_station/bootblock.c +++ b/src/mainboard/amd/south_station/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 244229d30d..e6e3e8e9d4 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index f9f52f7546..275de95ad2 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index ccb60ffae0..5b23f78d71 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 5496288651..13df85b261 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index d9e4c5ff1a..0e86c739d7 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c38708e76b..5f1413dc37 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index d39a3abe70..f1898e257d 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 01dc5ab777..77ae68a2a8 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e1c5aee487..b4b16431cb 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index be09a25c8d..3133c9ef99 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl index 3cbc0ad60b..c88aa64bcf 100644 --- a/src/mainboard/amd/thatcher/acpi/cpstate.asl +++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index 32d5a2a321..f8e34a8995 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi/mainboard.asl b/src/mainboard/amd/thatcher/acpi/mainboard.asl index fb75289e55..e97cdecfcc 100644 --- a/src/mainboard/amd/thatcher/acpi/mainboard.asl +++ b/src/mainboard/amd/thatcher/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi/routing.asl b/src/mainboard/amd/thatcher/acpi/routing.asl index 56bd465fd5..10b197221a 100644 --- a/src/mainboard/amd/thatcher/acpi/routing.asl +++ b/src/mainboard/amd/thatcher/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi/si.asl b/src/mainboard/amd/thatcher/acpi/si.asl index ff0c3cfc0d..cc27e983e1 100644 --- a/src/mainboard/amd/thatcher/acpi/si.asl +++ b/src/mainboard/amd/thatcher/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl index 9dd24e42b3..1d86801d94 100644 --- a/src/mainboard/amd/thatcher/acpi/sleep.asl +++ b/src/mainboard/amd/thatcher/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi/usb_oc.asl b/src/mainboard/amd/thatcher/acpi/usb_oc.asl index f5d6980d15..e1dc35d969 100644 --- a/src/mainboard/amd/thatcher/acpi/usb_oc.asl +++ b/src/mainboard/amd/thatcher/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index fd59a3aade..be2669eeb8 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 96847a74fb..417548bf78 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/amd/thatcher/cmos.layout +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index fd4cbef85f..0f5035ed1f 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index 77bd704590..14a38c23bf 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index d8bf5e9806..5f0654ad1e 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index ef8f9c1011..7218afabea 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index b23d036daf..e23b0171da 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index c701a7e4e2..3175f4c3e8 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 72881b8d4c..626d3af269 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index ffea060d80..55bdeb552e 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 866be54d37..8192510da4 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index e7a320eda5..c8ff6ea30c 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl index 59ea078593..6286ade685 100644 --- a/src/mainboard/amd/union_station/acpi/ide.asl +++ b/src/mainboard/amd/union_station/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi/mainboard.asl b/src/mainboard/amd/union_station/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/amd/union_station/acpi/mainboard.asl +++ b/src/mainboard/amd/union_station/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl index 537bcacaa1..51215f5de6 100644 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/amd/union_station/acpi/sata.asl +++ b/src/mainboard/amd/union_station/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi/sleep.asl b/src/mainboard/amd/union_station/acpi/sleep.asl index 0069aa9db2..f54fe2a9b7 100644 --- a/src/mainboard/amd/union_station/acpi/sleep.asl +++ b/src/mainboard/amd/union_station/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl index 13111b778e..8112d85ee3 100644 --- a/src/mainboard/amd/union_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/union_station/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/bootblock.c b/src/mainboard/amd/union_station/bootblock.c index f0361d6cf0..ec565a8c7f 100644 --- a/src/mainboard/amd/union_station/bootblock.c +++ b/src/mainboard/amd/union_station/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 244229d30d..e6e3e8e9d4 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index f9f52f7546..275de95ad2 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index 7bdc5f900c..9b8b2ec05f 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 5496288651..13df85b261 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index d680520d47..2c7626a5d1 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c38708e76b..5f1413dc37 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index d39a3abe70..f1898e257d 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl index 566704bddf..c096e1ce6e 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 620799cf2b..3f57b4d459 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index 5cd077baa1..8d65e56a0a 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl index ccaa6e3118..f39e99d37d 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl index 69c1d62d2d..646432ac6f 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/power.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/power.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl index e76deb7bca..773b613d63 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl index c042c3231b..fec77abc53 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/superio.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 84bb64e993..ffa997dd15 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Written by Stefan Reinauer - * (C) 2005 Stefan Reinauer - * (C) 2005 Digital Design Corporation * * Ported to Intel XE7501DEVKIT by Agami Aruma * Ported to AOpen DXPL Plus-U by Kyösti Mälkki diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c index db55f95e8d..95d010318d 100644 --- a/src/mainboard/aopen/dxplplusu/bootblock.c +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index bc80e87ce4..8400eeec57 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Kyösti Mälkki ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 4fde2442e9..cfde2cb2f8 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index a716a02e9b..f9c81b1918 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl index fb80f420b6..5a09b686bd 100644 --- a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl index 84807ec4af..4777e19b2d 100644 --- a/src/mainboard/apple/macbook21/acpi/platform.asl +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index d58151c1ac..0675b4114d 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 39bf6080a2..7953d7cc22 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 137c8fc929..8caaa503c5 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 97a4b05077..ffd5973f14 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/early_init.c b/src/mainboard/apple/macbook21/early_init.c index 081e55ade4..3878ec7f2f 100644 --- a/src/mainboard/apple/macbook21/early_init.c +++ b/src/mainboard/apple/macbook21/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c index 3ce6cf3777..695c3c9227 100644 --- a/src/mainboard/apple/macbook21/gpio.c +++ b/src/mainboard/apple/macbook21/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index fa20f386e0..76bae0c1a3 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 6c649e0f81..95bf4ada5d 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index 021115a85f..059abad075 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 6e8601b434..7cf97af155 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig index f47e3e5dcd..54922c2a6e 100644 --- a/src/mainboard/asrock/Kconfig +++ b/src/mainboard/asrock/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig index 561bea5006..e9aa5888ea 100644 --- a/src/mainboard/asrock/b75pro3-m/Kconfig +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index 598cd90e49..3ed751d7b5 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Iru Cai ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/b75pro3-m/acpi/pci.asl b/src/mainboard/asrock/b75pro3-m/acpi/pci.asl index b40a573034..5a9cb0cbfc 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi/pci.asl +++ b/src/mainboard/asrock/b75pro3-m/acpi/pci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/acpi/platform.asl b/src/mainboard/asrock/b75pro3-m/acpi/platform.asl index f7e56eac68..8a77c9ba4a 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi/platform.asl +++ b/src/mainboard/asrock/b75pro3-m/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/acpi/superio.asl b/src/mainboard/asrock/b75pro3-m/acpi/superio.asl index 1253d87823..5b5095461d 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi/superio.asl +++ b/src/mainboard/asrock/b75pro3-m/acpi/superio.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2017 Tobias Diedrich - * Copyright (C) 2018 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c index 6727616f4b..2b8c10087b 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi_tables.c +++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 3fa3dec24e..3a2f134a98 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 86b29d6a7c..ad1349553e 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 8fed7994ae..fd82c00ec7 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/gpio.c b/src/mainboard/asrock/b75pro3-m/gpio.c index 9775f71146..fa17a2d629 100644 --- a/src/mainboard/asrock/b75pro3-m/gpio.c +++ b/src/mainboard/asrock/b75pro3-m/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c index 9f98ccfc34..6c63926c73 100644 --- a/src/mainboard/asrock/b75pro3-m/hda_verb.c +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/mainboard.c b/src/mainboard/asrock/b75pro3-m/mainboard.c index 6d12c32791..a3d8b3409a 100644 --- a/src/mainboard/asrock/b75pro3-m/mainboard.c +++ b/src/mainboard/asrock/b75pro3-m/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index c9ecad746a..b80b4ca67a 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 3bbc2a5150..29b042bcc5 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc index ffea060d80..55bdeb552e 100644 --- a/src/mainboard/asrock/e350m1/Makefile.inc +++ b/src/mainboard/asrock/e350m1/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index 3534c80992..bd4a6d2327 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h index 936612c793..610c24096c 100644 --- a/src/mainboard/asrock/e350m1/OptionsIds.h +++ b/src/mainboard/asrock/e350m1/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl index 7994ae31a5..4b29c0d8ee 100644 --- a/src/mainboard/asrock/e350m1/acpi/gpe.asl +++ b/src/mainboard/asrock/e350m1/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/acpi/mainboard.asl b/src/mainboard/asrock/e350m1/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/asrock/e350m1/acpi/mainboard.asl +++ b/src/mainboard/asrock/e350m1/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 06750124e2..dd63e9b63e 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/acpi/sata.asl b/src/mainboard/asrock/e350m1/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/asrock/e350m1/acpi/sata.asl +++ b/src/mainboard/asrock/e350m1/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/acpi/sleep.asl b/src/mainboard/asrock/e350m1/acpi/sleep.asl index 47de049dbc..08144ff427 100644 --- a/src/mainboard/asrock/e350m1/acpi/sleep.asl +++ b/src/mainboard/asrock/e350m1/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl index a209909b32..5b22875dd1 100644 --- a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl +++ b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/bootblock.c b/src/mainboard/asrock/e350m1/bootblock.c index ea6aac093a..0ee1c39235 100644 --- a/src/mainboard/asrock/e350m1/bootblock.c +++ b/src/mainboard/asrock/e350m1/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 0125b5667f..bac9539320 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index a812876c69..c32435c6aa 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index b6ec209eb0..53aa6e0eb3 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index a958ce5f80..95821ec402 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 96744a39bd..1d49f790c3 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 6093e8f082..2b0916c586 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 5e93dc1934..c7b8a80296 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index 5f66969100..46e296f070 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl index 96870997f5..f5427b08fa 100644 --- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c index dede3173d0..b0370c1ef4 100644 --- a/src/mainboard/asrock/g41c-gs/acpi_tables.c +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index e6df510341..bdbf2e13dc 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/cstates.c b/src/mainboard/asrock/g41c-gs/cstates.c index 128f6558e7..2a6d8ad816 100644 --- a/src/mainboard/asrock/g41c-gs/cstates.c +++ b/src/mainboard/asrock/g41c-gs/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index cddaa3af4e..6120949269 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/g41c-gs/early_init.c b/src/mainboard/asrock/g41c-gs/early_init.c index b86c2d2c9d..d35bb5dcc2 100644 --- a/src/mainboard/asrock/g41c-gs/early_init.c +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c index 1c0474bbcd..11fd3edf80 100644 --- a/src/mainboard/asrock/g41c-gs/hda_verb.c +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index b68aaa9fa7..fd73fb30ed 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c index 6299d62dae..17961af1d9 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 160d025ca7..112cce0352 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c index 52cd611982..f00ab12008 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 0a8f27546d..1af0c1c7f9 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c index cea01cffc3..867fbdac66 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 8119ced94c..42d2a97c02 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c index 5b759f9828..4ee3e0273e 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index e5e3cf9b90..5753057074 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c index c67571b45b..4ca8d5aef0 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc index ce6cf8029a..def1c7fa61 100644 --- a/src/mainboard/asrock/h110m/Makefile.inc +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2016 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/acpi/dptf.asl b/src/mainboard/asrock/h110m/acpi/dptf.asl index 4453f3ba0e..440ef534a8 100644 --- a/src/mainboard/asrock/h110m/acpi/dptf.asl +++ b/src/mainboard/asrock/h110m/acpi/dptf.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2019 Maxim Polyakov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c index 96ce2053a7..e50120ceec 100644 --- a/src/mainboard/asrock/h110m/bootblock.c +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2019 Maxim Polyakov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index 916db62983..a0edabdccb 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2016 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index d42d91e556..6154d2a7ac 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Intel Corporation. -## Copyright (C) 2019 Maxim Polyakov ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index 1f3537e12b..06b53b2ee2 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation - * Copyright (C) 2019 Maxim Polyakov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/gma-mainboard.ads b/src/mainboard/asrock/h110m/gma-mainboard.ads index 86a3a62a18..1af3a93423 100644 --- a/src/mainboard/asrock/h110m/gma-mainboard.ads +++ b/src/mainboard/asrock/h110m/gma-mainboard.ads @@ -1,8 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2018 Tristan Corrick --- Copyright (C) 2019 Maxim Polyakov -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c index 04104bf7e2..1f8d3f4b95 100644 --- a/src/mainboard/asrock/h110m/hda_verb.c +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation - * (Written by Naresh G Solanki for Intel Corp.) - * Copyright (C) 2019 Maxim Polyakov * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 0b330782c7..cfd743679f 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Maxim Polyakov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/mainboard.c b/src/mainboard/asrock/h110m/mainboard.c index 4c1c6cd4d3..01f0575226 100644 --- a/src/mainboard/asrock/h110m/mainboard.c +++ b/src/mainboard/asrock/h110m/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick - * Copyright (C) 2019 Maxim Polyakov * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index a247b72587..37542ec566 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation - * Copyright (C) 2019 Maxim Polyakov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index a068713fc2..62f0e384a5 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. - * Copyright (C) 2019 Maxim Polyakov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 7088cbbbe6..dd26464e2d 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index de18bc5aa8..45798d3b9f 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/acpi/platform.asl b/src/mainboard/asrock/h81m-hds/acpi/platform.asl index adaf51a5ec..26a10c57b4 100644 --- a/src/mainboard/asrock/h81m-hds/acpi/platform.asl +++ b/src/mainboard/asrock/h81m-hds/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/acpi/superio.asl b/src/mainboard/asrock/h81m-hds/acpi/superio.asl index b671e3cb37..25a0c5cbfa 100644 --- a/src/mainboard/asrock/h81m-hds/acpi/superio.asl +++ b/src/mainboard/asrock/h81m-hds/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c index a43b499017..54796d54eb 100644 --- a/src/mainboard/asrock/h81m-hds/acpi_tables.c +++ b/src/mainboard/asrock/h81m-hds/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/bootblock.c b/src/mainboard/asrock/h81m-hds/bootblock.c index 7a841b84aa..11097fcb0f 100644 --- a/src/mainboard/asrock/h81m-hds/bootblock.c +++ b/src/mainboard/asrock/h81m-hds/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2018 Tristan Corrick * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout index 4926a45eb9..3f62e4757e 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 58a319d086..5be3791f18 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 8c4d5b8d5d..1b1ec6eaef 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/gma-mainboard.ads b/src/mainboard/asrock/h81m-hds/gma-mainboard.ads index c0260da588..54f85f2e95 100644 --- a/src/mainboard/asrock/h81m-hds/gma-mainboard.ads +++ b/src/mainboard/asrock/h81m-hds/gma-mainboard.ads @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2018 Tristan Corrick -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/gpio.c b/src/mainboard/asrock/h81m-hds/gpio.c index a03a52e726..4474f79d92 100644 --- a/src/mainboard/asrock/h81m-hds/gpio.c +++ b/src/mainboard/asrock/h81m-hds/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/hda_verb.c b/src/mainboard/asrock/h81m-hds/hda_verb.c index 187b7c42d2..9de7845a95 100644 --- a/src/mainboard/asrock/h81m-hds/hda_verb.c +++ b/src/mainboard/asrock/h81m-hds/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/mainboard.c b/src/mainboard/asrock/h81m-hds/mainboard.c index 54176c4e90..01f0575226 100644 --- a/src/mainboard/asrock/h81m-hds/mainboard.c +++ b/src/mainboard/asrock/h81m-hds/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3deae7510f..503bc72a5b 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2018 Tristan Corrick * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index 1cadd6b200..bbf9d8f239 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 8fca61c899..cd8330d699 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/Makefile.inc b/src/mainboard/asrock/imb-a180/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/asrock/imb-a180/Makefile.inc +++ b/src/mainboard/asrock/imb-a180/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index eaa27b7957..e0baf34370 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/OptionsIds.h b/src/mainboard/asrock/imb-a180/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/asrock/imb-a180/OptionsIds.h +++ b/src/mainboard/asrock/imb-a180/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/gpe.asl b/src/mainboard/asrock/imb-a180/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/asrock/imb-a180/acpi/gpe.asl +++ b/src/mainboard/asrock/imb-a180/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/ide.asl b/src/mainboard/asrock/imb-a180/acpi/ide.asl index e7f4625506..e17d93befd 100644 --- a/src/mainboard/asrock/imb-a180/acpi/ide.asl +++ b/src/mainboard/asrock/imb-a180/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/mainboard.asl b/src/mainboard/asrock/imb-a180/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/asrock/imb-a180/acpi/mainboard.asl +++ b/src/mainboard/asrock/imb-a180/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/routing.asl b/src/mainboard/asrock/imb-a180/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/asrock/imb-a180/acpi/routing.asl +++ b/src/mainboard/asrock/imb-a180/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/sata.asl b/src/mainboard/asrock/imb-a180/acpi/sata.asl index 6755258f4d..00d855adb0 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sata.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/si.asl b/src/mainboard/asrock/imb-a180/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/asrock/imb-a180/acpi/si.asl +++ b/src/mainboard/asrock/imb-a180/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/sleep.asl b/src/mainboard/asrock/imb-a180/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sleep.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl index 9e0d032c71..82235e55a4 100644 --- a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl +++ b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index caa5e3bc44..5cdf669a11 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/cmos.layout b/src/mainboard/asrock/imb-a180/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/asrock/imb-a180/cmos.layout +++ b/src/mainboard/asrock/imb-a180/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/devicetree.cb b/src/mainboard/asrock/imb-a180/devicetree.cb index 536236ed4b..9502d2f0cf 100644 --- a/src/mainboard/asrock/imb-a180/devicetree.cb +++ b/src/mainboard/asrock/imb-a180/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index c4fc93484e..a7914191d0 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index d8bf5e9806..5f0654ad1e 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 65e838bd9f..b3e47f8ec3 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 37080ea320..1901e0e870 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index f910588a2f..d079f371df 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index 18ba5f6e9f..e081062799 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov - * Copyright (C) 2018 Gergely Kiss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/asus/am1i-a/Makefile.inc +++ b/src/mainboard/asus/am1i-a/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c index e001d43d4a..7515afce42 100644 --- a/src/mainboard/asus/am1i-a/OemCustomize.c +++ b/src/mainboard/asus/am1i-a/OemCustomize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2018 Gergely Kiss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/OptionsIds.h b/src/mainboard/asus/am1i-a/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/asus/am1i-a/OptionsIds.h +++ b/src/mainboard/asus/am1i-a/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/acpi/mainboard.asl b/src/mainboard/asus/am1i-a/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/asus/am1i-a/acpi/mainboard.asl +++ b/src/mainboard/asus/am1i-a/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/acpi/routing.asl b/src/mainboard/asus/am1i-a/acpi/routing.asl index 8b21a25776..3ddaebff45 100644 --- a/src/mainboard/asus/am1i-a/acpi/routing.asl +++ b/src/mainboard/asus/am1i-a/acpi/routing.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2018 Gergely Kiss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/acpi/sata.asl b/src/mainboard/asus/am1i-a/acpi/sata.asl index 9349be71e6..b25c9d84dc 100644 --- a/src/mainboard/asus/am1i-a/acpi/sata.asl +++ b/src/mainboard/asus/am1i-a/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/acpi/si.asl b/src/mainboard/asus/am1i-a/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/asus/am1i-a/acpi/si.asl +++ b/src/mainboard/asus/am1i-a/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/acpi/sleep.asl b/src/mainboard/asus/am1i-a/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/asus/am1i-a/acpi/sleep.asl +++ b/src/mainboard/asus/am1i-a/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/acpi/superio.asl b/src/mainboard/asus/am1i-a/acpi/superio.asl index 6ff5b7fc09..c56e337d0e 100644 --- a/src/mainboard/asus/am1i-a/acpi/superio.asl +++ b/src/mainboard/asus/am1i-a/acpi/superio.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2015 Sergej Ivanov - * Copyright (C) 2018 Gergely Kiss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c index 447c89573e..2c7bacf0eb 100644 --- a/src/mainboard/asus/am1i-a/acpi_tables.c +++ b/src/mainboard/asus/am1i-a/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 30c06997e4..b0ef51d872 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/cmos.layout b/src/mainboard/asus/am1i-a/cmos.layout index 7553811323..3f685eeae6 100644 --- a/src/mainboard/asus/am1i-a/cmos.layout +++ b/src/mainboard/asus/am1i-a/cmos.layout @@ -2,8 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2018 Gergely Kiss # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb index 2d7265a20d..c28ab5dc7e 100644 --- a/src/mainboard/asus/am1i-a/devicetree.cb +++ b/src/mainboard/asus/am1i-a/devicetree.cb @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# Copyright (C) 2015 Sergej Ivanov -# Copyright (C) 2018 Gergely Kiss # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index 88222bda63..fcae00b660 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2015 Sergej Ivanov - * Copyright (C) 2018 Gergely Kiss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c index 84110d1882..7ef3c8dc9d 100644 --- a/src/mainboard/asus/am1i-a/irq_tables.c +++ b/src/mainboard/asus/am1i-a/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Gergely Kiss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c index f9a12e58dc..f060899f19 100644 --- a/src/mainboard/asus/am1i-a/mainboard.c +++ b/src/mainboard/asus/am1i-a/mainboard.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * Copyright (C) 2015 Sergej Ivanov - * Copyright (C) 2018 Gergely Kiss * * All Rights Reserved * diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c index 3a6131f1d2..9828577196 100644 --- a/src/mainboard/asus/am1i-a/mptable.c +++ b/src/mainboard/asus/am1i-a/mptable.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2018 Gergely Kiss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 15ce47e17b..90d9eda654 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index c1dd063c77..9c646cc0fa 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2012 Rudolf Marek # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/asus/f2a85-m/Makefile.inc +++ b/src/mainboard/asus/f2a85-m/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index ec79fc832b..97ea78481e 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h index b45f5a8766..dc507e8241 100644 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ b/src/mainboard/asus/f2a85-m/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl index 3cbc0ad60b..c88aa64bcf 100644 --- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl index 297db37a67..be9f9fce2d 100644 --- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl +++ b/src/mainboard/asus/f2a85-m/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m/acpi/mainboard.asl index 8398c88c68..8cad2d8160 100644 --- a/src/mainboard/asus/f2a85-m/acpi/mainboard.asl +++ b/src/mainboard/asus/f2a85-m/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index 38ba142795..32cfbd3055 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi/si.asl b/src/mainboard/asus/f2a85-m/acpi/si.asl index ff0c3cfc0d..cc27e983e1 100644 --- a/src/mainboard/asus/f2a85-m/acpi/si.asl +++ b/src/mainboard/asus/f2a85-m/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi/sleep.asl b/src/mainboard/asus/f2a85-m/acpi/sleep.asl index 08b7de47f3..1ce04c2336 100644 --- a/src/mainboard/asus/f2a85-m/acpi/sleep.asl +++ b/src/mainboard/asus/f2a85-m/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl index f5d6980d15..e1dc35d969 100644 --- a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl +++ b/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index fd59a3aade..be2669eeb8 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c index 3d980a663d..b60cc533a1 100644 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2012 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 8a1391d262..f68aa628e0 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb index 7a22d78871..f676341594 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb index 7d0e820007..619b5032a3 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 97405aa313..7681ff48b0 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index 45a2606611..ad9ce1bc21 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index e0d5ad4641..4022ebb513 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 2a0e618b24..32ebebef30 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 303f3bf5c4..b9eba0bedb 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 5b7494d9ee..7519c2002e 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2012 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/acpi/platform.asl b/src/mainboard/asus/h61m-cs/acpi/platform.asl index d4f24db252..d356d9b52b 100644 --- a/src/mainboard/asus/h61m-cs/acpi/platform.asl +++ b/src/mainboard/asus/h61m-cs/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Abhinav Hardikar * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c index dccc02ff56..985d0866bf 100644 --- a/src/mainboard/asus/h61m-cs/acpi_tables.c +++ b/src/mainboard/asus/h61m-cs/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/h61m-cs/cmos.layout b/src/mainboard/asus/h61m-cs/cmos.layout index 095e3833e1..c31d568140 100644 --- a/src/mainboard/asus/h61m-cs/cmos.layout +++ b/src/mainboard/asus/h61m-cs/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb index 9a4c6fee2f..57ec653c0e 100644 --- a/src/mainboard/asus/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Abhinav Hardikar ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 8a052a321c..42fc8abb15 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Abhinav Hardikar * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/early_init.c b/src/mainboard/asus/h61m-cs/early_init.c index 726507e0f8..54034d1f3a 100644 --- a/src/mainboard/asus/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61m-cs/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/h61m-cs/gma-mainboard.ads b/src/mainboard/asus/h61m-cs/gma-mainboard.ads index d2aec66280..8544f77be9 100644 --- a/src/mainboard/asus/h61m-cs/gma-mainboard.ads +++ b/src/mainboard/asus/h61m-cs/gma-mainboard.ads @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2018 Angel Pons -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/gpio.c b/src/mainboard/asus/h61m-cs/gpio.c index b963f6e9c3..e535a90c23 100644 --- a/src/mainboard/asus/h61m-cs/gpio.c +++ b/src/mainboard/asus/h61m-cs/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/h61m-cs/hda_verb.c b/src/mainboard/asus/h61m-cs/hda_verb.c index f985419e9a..a92dfec6b4 100644 --- a/src/mainboard/asus/h61m-cs/hda_verb.c +++ b/src/mainboard/asus/h61m-cs/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/h61m-cs/mainboard.c b/src/mainboard/asus/h61m-cs/mainboard.c index d198020bd3..36a140bbb9 100644 --- a/src/mainboard/asus/h61m-cs/mainboard.c +++ b/src/mainboard/asus/h61m-cs/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig index be832ce044..da2e48e14f 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index be8d9c3e85..85cc888553 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl index adaf51a5ec..26a10c57b4 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl index ab41034eb2..bef9a0325e 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c index 1a584e08c2..9c02dd5485 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout index 9fe6fc2b92..6f172ece2a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 0c25d4d91a..7a5f348036 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017–2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index 0cdc58c0ef..a9b0faa5b4 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index 2c8b5d9280..f5757c9482 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017–2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads b/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads index a8b0a47029..393d1a1822 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads +++ b/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2017 Tristan Corrick -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/gpio.c b/src/mainboard/asus/maximus_iv_gene-z/gpio.c index 5a2aabebff..b0dcee2942 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/gpio.c +++ b/src/mainboard/asus/maximus_iv_gene-z/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c index 8c8b35f215..9859c8d86f 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c +++ b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/mainboard.c b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c index 43350868ab..01f0575226 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/mainboard.c +++ b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig index 8db9b7ad43..2b61db7012 100644 --- a/src/mainboard/asus/p2b-d/Kconfig +++ b/src/mainboard/asus/p2b-d/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b-d/irq_tables.c index cb72254ece..0bc944060f 100644 --- a/src/mainboard/asus/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b-d/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c index 8f643d1e99..6c238f1da2 100644 --- a/src/mainboard/asus/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b-d/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 7fad06bf50..b996f1ee57 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig index 8b55174f41..be03d1b44f 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ b/src/mainboard/asus/p2b-ds/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b-ds/irq_tables.c index 2240b44ccf..2da3346988 100644 --- a/src/mainboard/asus/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b-ds/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c index b4925118a3..a180194b30 100644 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b-ds/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index d0456e5296..67ba632ece 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig index efe625c5d2..cb220c9913 100644 --- a/src/mainboard/asus/p2b-f/Kconfig +++ b/src/mainboard/asus/p2b-f/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b-f/irq_tables.c index eb30881e63..368c0e56e7 100644 --- a/src/mainboard/asus/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b-f/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 31a100c74c..f91a806b5e 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig index 60124fe750..2d12c86045 100644 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ b/src/mainboard/asus/p2b-ls/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2010 Keith Hui ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c index d740ee1c5a..f1e1994802 100644 --- a/src/mainboard/asus/p2b-ls/acpi_tables.c +++ b/src/mainboard/asus/p2b-ls/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 83e1df6bc4..938caa5a7c 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b-ls/irq_tables.c index d8bce7ca71..b7536eb397 100644 --- a/src/mainboard/asus/p2b-ls/irq_tables.c +++ b/src/mainboard/asus/p2b-ls/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index b79ac82918..546d9ed419 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 65e7681485..f55b3a6d46 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/acpi_tables.c b/src/mainboard/asus/p2b/acpi_tables.c index d740ee1c5a..f1e1994802 100644 --- a/src/mainboard/asus/p2b/acpi_tables.c +++ b/src/mainboard/asus/p2b/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 279f772e96..c67e50fd79 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Tobias Diedrich - * Copyright (C) 2017 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c index ee8b969c43..4601f0850e 100644 --- a/src/mainboard/asus/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index fbd7124105..67ba632ece 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p3b-f/Kconfig b/src/mainboard/asus/p3b-f/Kconfig index 179fed29c3..eee97d5a88 100644 --- a/src/mainboard/asus/p3b-f/Kconfig +++ b/src/mainboard/asus/p3b-f/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index bbd00170a2..483b4eecde 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 209dd96c50..e3a78978c0 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index 7b5cd19ac4..48f648806b 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 coresystems GmbH -## Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5gc-mx/gpio.c b/src/mainboard/asus/p5gc-mx/gpio.c index d225ba00c5..07f8038abc 100644 --- a/src/mainboard/asus/p5gc-mx/gpio.c +++ b/src/mainboard/asus/p5gc-mx/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c index a9c25f3593..7edd1710a2 100644 --- a/src/mainboard/asus/p5gc-mx/hda_verb.c +++ b/src/mainboard/asus/p5gc-mx/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index e7d23bdaac..63f531145d 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2018 Arthur Heymans -# Copyright (C) 2019 Ivan Vatlin # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl index e8cb26eb65..638a9ba127 100644 --- a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl +++ b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 22743730da..7e45c750c2 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout index e1d4e2b630..701116631b 100644 --- a/src/mainboard/asus/p5qc/cmos.layout +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index 75e3b98d6d..5b15298a1e 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qc/early_init.c b/src/mainboard/asus/p5qc/early_init.c index cbc84ba101..6a7ac89e00 100644 --- a/src/mainboard/asus/p5qc/early_init.c +++ b/src/mainboard/asus/p5qc/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/gpio.c b/src/mainboard/asus/p5qc/gpio.c index fdafafcae5..74ac8ecad7 100644 --- a/src/mainboard/asus/p5qc/gpio.c +++ b/src/mainboard/asus/p5qc/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c index 22832bbb19..8a56a75973 100644 --- a/src/mainboard/asus/p5qc/hda_verb.c +++ b/src/mainboard/asus/p5qc/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index a1211ccd29..a33533b15a 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2018 Arthur Heymans -# Copyright (C) 2019 Ivan Vatlin # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index f697bff010..c384795c69 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2018 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 94ef717e60..a129500fce 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2018 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 91e45b4f29..633ca8141a 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2018 Angel Pons # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c b/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c index 8775e1ee61..d6325ceada 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index 0932241655..d2551d895c 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl index ec461679f7..50e63a81a0 100644 --- a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c index dede3173d0..b0370c1ef4 100644 --- a/src/mainboard/asus/p5qpl-am/acpi_tables.c +++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout index 0a59868efd..ac83eb86b0 100644 --- a/src/mainboard/asus/p5qpl-am/cmos.layout +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/cstates.c b/src/mainboard/asus/p5qpl-am/cstates.c index 128f6558e7..2a6d8ad816 100644 --- a/src/mainboard/asus/p5qpl-am/cstates.c +++ b/src/mainboard/asus/p5qpl-am/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index fb3366c99f..efecc58458 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans -# Copyright (C) 2019 Angel Pons # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index cddaa3af4e..6120949269 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qpl-am/early_init.c b/src/mainboard/asus/p5qpl-am/early_init.c index 97411fdb94..afcd531ed4 100644 --- a/src/mainboard/asus/p5qpl-am/early_init.c +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c index f941a75228..76b249b2ba 100644 --- a/src/mainboard/asus/p5qpl-am/hda_verb.c +++ b/src/mainboard/asus/p5qpl-am/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c index 90fd9e4265..1a7739bdde 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb index 2ea157f7d2..f85ed1d2ec 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans -# Copyright (C) 2019 Angel Pons # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c index 1f794bed71..b97804d984 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index 1305bff368..2f00e1f028 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index 2210b1a59e..54ba360d06 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index 28f5e60f5d..85cc888553 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl index adaf51a5ec..26a10c57b4 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl +++ b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl index b671e3cb37..25a0c5cbfa 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl +++ b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c index 1a584e08c2..9c02dd5485 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.layout b/src/mainboard/asus/p8h61-m_lx/cmos.layout index 892e70c574..5e3fa2e236 100644 --- a/src/mainboard/asus/p8h61-m_lx/cmos.layout +++ b/src/mainboard/asus/p8h61-m_lx/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index 27705b91f7..777c9d1981 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index 0cdc58c0ef..a9b0faa5b4 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/early_init.c b/src/mainboard/asus/p8h61-m_lx/early_init.c index e38e8822e4..0d4f227e5a 100644 --- a/src/mainboard/asus/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/p8h61-m_lx/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads index 652fa3f726..a161d2d22a 100644 --- a/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads +++ b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2018 Tristan Corrick -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/gpio.c b/src/mainboard/asus/p8h61-m_lx/gpio.c index 2a6632214e..3b46845764 100644 --- a/src/mainboard/asus/p8h61-m_lx/gpio.c +++ b/src/mainboard/asus/p8h61-m_lx/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/p8h61-m_lx/hda_verb.c index b24df6411c..17e2e8d9b5 100644 --- a/src/mainboard/asus/p8h61-m_lx/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_lx/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/mainboard.c b/src/mainboard/asus/p8h61-m_lx/mainboard.c index 54176c4e90..01f0575226 100644 --- a/src/mainboard/asus/p8h61-m_lx/mainboard.c +++ b/src/mainboard/asus/p8h61-m_lx/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index e9b8ab0f07..5b9bbd3ad5 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl b/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl index d8d33208f8..92c98614d7 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl +++ b/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl b/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl index ab41034eb2..bef9a0325e 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl +++ b/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c index 23537a44d3..2f1c8c0aff 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/cmos.layout b/src/mainboard/asus/p8h61-m_pro/cmos.layout index 095e3833e1..c31d568140 100644 --- a/src/mainboard/asus/p8h61-m_pro/cmos.layout +++ b/src/mainboard/asus/p8h61-m_pro/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index ea643696ee..0ad35776a9 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index e8ff31143e..4080e2facd 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/early_init.c b/src/mainboard/asus/p8h61-m_pro/early_init.c index 27045bf594..7ba8751e8d 100644 --- a/src/mainboard/asus/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/p8h61-m_pro/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads index d2233d68e8..4e89f3af5d 100644 --- a/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads +++ b/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2018 Angel Pons -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/gpio.c b/src/mainboard/asus/p8h61-m_pro/gpio.c index b1b819eca0..ea28bdc50f 100644 --- a/src/mainboard/asus/p8h61-m_pro/gpio.c +++ b/src/mainboard/asus/p8h61-m_pro/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/p8h61-m_pro/hda_verb.c index fc73c29b27..1a6b2499e7 100644 --- a/src/mainboard/asus/p8h61-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_pro/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig b/src/mainboard/asus/p8z77-m_pro/Kconfig index 8d29a9bc21..0b4315417c 100644 --- a/src/mainboard/asus/p8z77-m_pro/Kconfig +++ b/src/mainboard/asus/p8z77-m_pro/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Vlado Cibic ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig.name b/src/mainboard/asus/p8z77-m_pro/Kconfig.name index c492094508..dc96c854b6 100644 --- a/src/mainboard/asus/p8z77-m_pro/Kconfig.name +++ b/src/mainboard/asus/p8z77-m_pro/Kconfig.name @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Vlado Cibic ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc index e9fbd3cf88..d989b7d22d 100644 --- a/src/mainboard/asus/p8z77-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8z77-m_pro/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Vlado Cibic ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl index 3a696211c1..d356d9b52b 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl +++ b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Vlado Cibic * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl index 7f1d04c9ba..bef9a0325e 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl +++ b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Vlado Cibic * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c index 9c22f190b1..da96b49f40 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Vlado Cibic * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8z77-m_pro/cmos.default index 725ab9851d..36946eab07 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.default +++ b/src/mainboard/asus/p8z77-m_pro/cmos.default @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Vlado Cibic ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index 4ac7b5d2eb..6b0f13fac3 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Vlado Cibic ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb index cbc1629c80..8a8f37599c 100644 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Vlado Cibic ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 62d44eabe9..663aeb001e 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Vlado Cibic * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index d2c23559f3..69c79e881b 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Vlado Cibic * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads index f9dd430d24..9e6cb3e51f 100644 --- a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads +++ b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2019 Vlado Cibic -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/gpio.c b/src/mainboard/asus/p8z77-m_pro/gpio.c index c8842159d3..30dfb5c37d 100644 --- a/src/mainboard/asus/p8z77-m_pro/gpio.c +++ b/src/mainboard/asus/p8z77-m_pro/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2019 Vlado Cibic * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c index b8e8d87a5a..f28a64db7a 100644 --- a/src/mainboard/asus/p8z77-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8z77-m_pro/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2019 Vlado Cibic * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p8z77-m_pro/mainboard.c b/src/mainboard/asus/p8z77-m_pro/mainboard.c index 6cb41cc738..5f2c766a7d 100644 --- a/src/mainboard/asus/p8z77-m_pro/mainboard.c +++ b/src/mainboard/asus/p8z77-m_pro/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Vlado Cibic * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig index 2041ce9f56..bf9cbca9cf 100644 --- a/src/mainboard/asus/p8z77-v_lx2/Kconfig +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2020 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 7ce2840d36..630b10dc5a 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2020 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl index f164b332d0..a17d64be99 100644 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig index c21cf85269..234c2c6aba 100644 --- a/src/mainboard/bap/Kconfig +++ b/src/mainboard/bap/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -## (Written by Fabian Kunkel for BAP) ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex index f3e3e75ded..f214570540 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -# (Written by Fabian Kunkel for BAP) # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex index 6e90bfa92d..5ba55243df 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -# (Written by Fabian Kunkel for BAP) # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 27d1dcaa9a..6b83e16b70 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 4df74c0c24..90f425d852 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 8747d2fecb..98abec1231 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 29d01d6355..a429a1d8a9 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/OptionsIds.h b/src/mainboard/bap/ode_e20XX/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/bap/ode_e20XX/OptionsIds.h +++ b/src/mainboard/bap/ode_e20XX/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/ide.asl b/src/mainboard/bap/ode_e20XX/acpi/ide.asl index e7f4625506..e17d93befd 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/ide.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/routing.asl b/src/mainboard/bap/ode_e20XX/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/routing.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/si.asl b/src/mainboard/bap/ode_e20XX/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/si.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/superio.asl b/src/mainboard/bap/ode_e20XX/acpi/superio.asl index 92bd10680b..5c53f116bf 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/superio.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/superio.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl index c0202167da..bf00545927 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 6c405cc18e..9ec18e9344 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/bap/ode_e20XX/cmos.layout +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index 893d32366b..084e6073ea 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index c4fc93484e..a7914191d0 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c index d8bf5e9806..5f0654ad1e 100644 --- a/src/mainboard/bap/ode_e20XX/irq_tables.c +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index 2fcc1d6e6b..c7d8ee45f3 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * All Rights Reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c index e4edc5fe7a..e0a407bb25 100644 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex index 51e3501067..950ccf4125 100644 --- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -# (Written by Fabian Kunkel for BAP) # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex index 7949ce81b9..09444d9359 100644 --- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -# (Written by Fabian Kunkel for BAP) # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex index 6653aa43b4..5c98dfe7b9 100644 --- a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -# (Written by Fabian Kunkel for BAP) # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index cc2e2d3282..c9144449ef 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index ff71d5bdc3..fecceea01d 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc index b0ce62781a..f86d28d730 100644 --- a/src/mainboard/bap/ode_e21XX/Makefile.inc +++ b/src/mainboard/bap/ode_e21XX/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c index 97aaa4e6d0..bab757e7b3 100644 --- a/src/mainboard/bap/ode_e21XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi/gpe.asl b/src/mainboard/bap/ode_e21XX/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/gpe.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi/routing.asl b/src/mainboard/bap/ode_e21XX/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/routing.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi/si.asl b/src/mainboard/bap/ode_e21XX/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/si.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi/sleep.asl b/src/mainboard/bap/ode_e21XX/acpi/sleep.asl index 0734c8e3c8..19dd289560 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/sleep.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi/superio.asl b/src/mainboard/bap/ode_e21XX/acpi/superio.asl index 92bd10680b..5c53f116bf 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/superio.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/superio.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl index 4ebb4b64a6..83cd750b4a 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/acpi_tables.c b/src/mainboard/bap/ode_e21XX/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/bap/ode_e21XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e21XX/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/cmos.layout b/src/mainboard/bap/ode_e21XX/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/bap/ode_e21XX/cmos.layout +++ b/src/mainboard/bap/ode_e21XX/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/devicetree.cb b/src/mainboard/bap/ode_e21XX/devicetree.cb index 021ee90157..ce7362ac9d 100644 --- a/src/mainboard/bap/ode_e21XX/devicetree.cb +++ b/src/mainboard/bap/ode_e21XX/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl index 0c8fa71095..4bf4dc8276 100644 --- a/src/mainboard/bap/ode_e21XX/dsdt.asl +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/irq_tables.c b/src/mainboard/bap/ode_e21XX/irq_tables.c index 5eb5a49c6e..6133bc8620 100644 --- a/src/mainboard/bap/ode_e21XX/irq_tables.c +++ b/src/mainboard/bap/ode_e21XX/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index 1367b03307..c664be3876 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c index 6c81d06cc5..f942dc9e66 100644 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index a60e571367..0c017fdf12 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 0f28af33c2..daabb5e5c0 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann -## Copyright (C) 2015 Sergej Ivanov ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c index fe4fab5a12..ecc7985932 100644 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index e4271d34fe..13206c1e2a 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2016 Edward O'Callaghan -# Copyright (C) 2017 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/Makefile.inc b/src/mainboard/biostar/a68n_5200/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/biostar/a68n_5200/Makefile.inc +++ b/src/mainboard/biostar/a68n_5200/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c index df13fa502f..e207c0303a 100644 --- a/src/mainboard/biostar/a68n_5200/OemCustomize.c +++ b/src/mainboard/biostar/a68n_5200/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/OptionsIds.h b/src/mainboard/biostar/a68n_5200/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/biostar/a68n_5200/OptionsIds.h +++ b/src/mainboard/biostar/a68n_5200/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl index aa941ba9ae..0910e6a2b6 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/ide.asl b/src/mainboard/biostar/a68n_5200/acpi/ide.asl index e7f4625506..e17d93befd 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/ide.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/routing.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/sata.asl b/src/mainboard/biostar/a68n_5200/acpi/sata.asl index 6755258f4d..00d855adb0 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/sata.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/si.asl b/src/mainboard/biostar/a68n_5200/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/si.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl index 513d66d1d7..7ceb70ce04 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/biostar/a68n_5200/acpi_tables.c +++ b/src/mainboard/biostar/a68n_5200/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/bootblock.c b/src/mainboard/biostar/a68n_5200/bootblock.c index 395419b76f..df033c1ef7 100644 --- a/src/mainboard/biostar/a68n_5200/bootblock.c +++ b/src/mainboard/biostar/a68n_5200/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Edward O'Callaghan - * Copyright (C) 2017 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 65b86b88f7..0b89298b9d 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/biostar/a68n_5200/cmos.layout +++ b/src/mainboard/biostar/a68n_5200/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb index fd9b6edfb5..559a90098b 100644 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ b/src/mainboard/biostar/a68n_5200/devicetree.cb @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# Copyright (C) 2016 Edward O'Callaghan -# Copyright (C) 2017 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index c4fc93484e..a7914191d0 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/irq_tables.c b/src/mainboard/biostar/a68n_5200/irq_tables.c index e19e698bbe..6fb65c00ba 100644 --- a/src/mainboard/biostar/a68n_5200/irq_tables.c +++ b/src/mainboard/biostar/a68n_5200/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c index 65e838bd9f..b3e47f8ec3 100644 --- a/src/mainboard/biostar/a68n_5200/mainboard.c +++ b/src/mainboard/biostar/a68n_5200/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index 52374f1529..6e1d402833 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index bb2f915fd2..0ea90d53cf 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 9eaa6fb98c..b2ef6d51ee 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2015 Sergej Ivanov # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/Makefile.inc b/src/mainboard/biostar/am1ml/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/biostar/am1ml/Makefile.inc +++ b/src/mainboard/biostar/am1ml/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index 2f7666ee3a..3ea2310181 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/OptionsIds.h b/src/mainboard/biostar/am1ml/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/biostar/am1ml/OptionsIds.h +++ b/src/mainboard/biostar/am1ml/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/flag0.asl b/src/mainboard/biostar/am1ml/acpi/flag0.asl index ca3b4fd49b..649ff9d582 100644 --- a/src/mainboard/biostar/am1ml/acpi/flag0.asl +++ b/src/mainboard/biostar/am1ml/acpi/flag0.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/gpe.asl b/src/mainboard/biostar/am1ml/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/biostar/am1ml/acpi/gpe.asl +++ b/src/mainboard/biostar/am1ml/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/ide.asl b/src/mainboard/biostar/am1ml/acpi/ide.asl index 52d85ab28e..06fe163a1c 100644 --- a/src/mainboard/biostar/am1ml/acpi/ide.asl +++ b/src/mainboard/biostar/am1ml/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/mainboard.asl b/src/mainboard/biostar/am1ml/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/biostar/am1ml/acpi/mainboard.asl +++ b/src/mainboard/biostar/am1ml/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/routing.asl b/src/mainboard/biostar/am1ml/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/biostar/am1ml/acpi/routing.asl +++ b/src/mainboard/biostar/am1ml/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl index c8cf86d671..dc015dcb5a 100644 --- a/src/mainboard/biostar/am1ml/acpi/sata.asl +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/si.asl b/src/mainboard/biostar/am1ml/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/biostar/am1ml/acpi/si.asl +++ b/src/mainboard/biostar/am1ml/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/sio.asl b/src/mainboard/biostar/am1ml/acpi/sio.asl index 7778faa4bb..a43f9ac013 100644 --- a/src/mainboard/biostar/am1ml/acpi/sio.asl +++ b/src/mainboard/biostar/am1ml/acpi/sio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/sleep.asl b/src/mainboard/biostar/am1ml/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/biostar/am1ml/acpi/sleep.asl +++ b/src/mainboard/biostar/am1ml/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/superio.asl b/src/mainboard/biostar/am1ml/acpi/superio.asl index f7f0027a00..20c9e94297 100644 --- a/src/mainboard/biostar/am1ml/acpi/superio.asl +++ b/src/mainboard/biostar/am1ml/acpi/superio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2015 Sergej Ivanov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi/usb_oc.asl b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl index 70a4678a1d..20189c94dd 100644 --- a/src/mainboard/biostar/am1ml/acpi/usb_oc.asl +++ b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c index 447c89573e..2c7bacf0eb 100644 --- a/src/mainboard/biostar/am1ml/acpi_tables.c +++ b/src/mainboard/biostar/am1ml/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 74216f0556..1806580d06 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/cmos.layout b/src/mainboard/biostar/am1ml/cmos.layout index 9ea8dda79c..0bcd1d0d83 100644 --- a/src/mainboard/biostar/am1ml/cmos.layout +++ b/src/mainboard/biostar/am1ml/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/devicetree.cb b/src/mainboard/biostar/am1ml/devicetree.cb index dfe537cda3..c07644a613 100644 --- a/src/mainboard/biostar/am1ml/devicetree.cb +++ b/src/mainboard/biostar/am1ml/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# Copyright (C) 2015 Sergej Ivanov # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index 945319b8a8..907b2d172d 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2015 Sergej Ivanov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c index 87dafa099c..0044ab7bd0 100644 --- a/src/mainboard/biostar/am1ml/irq_tables.c +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Sergej Ivanov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index 9d218d8e44..bd198ce8eb 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * Copyright (C) 2015 Sergej Ivanov - * All Rights Reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index 659a141f95..2eced4e45e 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/Kconfig b/src/mainboard/cavium/Kconfig index ac16393c7f..7843dd1a3d 100644 --- a/src/mainboard/cavium/Kconfig +++ b/src/mainboard/cavium/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Facebook Inc ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig b/src/mainboard/cavium/cn8100_sff_evb/Kconfig index 03e65f5de9..adf363ee8a 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Kconfig +++ b/src/mainboard/cavium/cn8100_sff_evb/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc index 72736255f8..b930c30880 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc +++ b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c index 237e73d917..62ea3a6093 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c index ad758c92cc..ff158aecde 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb index 00be155fca..8305a391b3 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb +++ b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c index fd0d9285ed..dbf71c282e 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c +++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. (support@cavium.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c index 81a41009bc..3be4966bcb 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c +++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/acpi/ec.asl b/src/mainboard/compulab/intense_pc/acpi/ec.asl index cc80166e85..95bb1eb7f8 100644 --- a/src/mainboard/compulab/intense_pc/acpi/ec.asl +++ b/src/mainboard/compulab/intense_pc/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/acpi/platform.asl b/src/mainboard/compulab/intense_pc/acpi/platform.asl index a726eed8f9..705d5bdce9 100644 --- a/src/mainboard/compulab/intense_pc/acpi/platform.asl +++ b/src/mainboard/compulab/intense_pc/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/acpi/superio.asl b/src/mainboard/compulab/intense_pc/acpi/superio.asl index becdf3df85..606085fafe 100644 --- a/src/mainboard/compulab/intense_pc/acpi/superio.asl +++ b/src/mainboard/compulab/intense_pc/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/acpi_tables.c b/src/mainboard/compulab/intense_pc/acpi_tables.c index 33abf477a6..a393cc6ff3 100644 --- a/src/mainboard/compulab/intense_pc/acpi_tables.c +++ b/src/mainboard/compulab/intense_pc/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 93cb5d2b7f..4717eca3eb 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -1,6 +1,5 @@ # This file is part of the coreboot project. # -# Copyright (C) 2017 Hal Martin # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index f769a0fe43..4b750174a4 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index 7078199f7e..cf2306a17f 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/gpio.c b/src/mainboard/compulab/intense_pc/gpio.c index dc98da8e57..cd7e6b7926 100644 --- a/src/mainboard/compulab/intense_pc/gpio.c +++ b/src/mainboard/compulab/intense_pc/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/compulab/intense_pc/hda_verb.c b/src/mainboard/compulab/intense_pc/hda_verb.c index 569b9d5277..7eb7e0c27a 100644 --- a/src/mainboard/compulab/intense_pc/hda_verb.c +++ b/src/mainboard/compulab/intense_pc/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/compulab/intense_pc/mainboard.c b/src/mainboard/compulab/intense_pc/mainboard.c index 45a4059cf3..9e41c09292 100644 --- a/src/mainboard/compulab/intense_pc/mainboard.c +++ b/src/mainboard/compulab/intense_pc/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Hal Martin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 01f06bd765..6d195816b4 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 7dc67d17ea..5a0f28f30c 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc index bf86007cec..f0a8fe6109 100644 --- a/src/mainboard/elmex/pcm205400/Makefile.inc +++ b/src/mainboard/elmex/pcm205400/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index f8a26132ba..b38ce25b00 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/OptionsIds.h b/src/mainboard/elmex/pcm205400/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/elmex/pcm205400/OptionsIds.h +++ b/src/mainboard/elmex/pcm205400/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl index 3cf38c035a..af4e2e48b7 100644 --- a/src/mainboard/elmex/pcm205400/acpi/gpe.asl +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl index 59ea078593..6286ade685 100644 --- a/src/mainboard/elmex/pcm205400/acpi/ide.asl +++ b/src/mainboard/elmex/pcm205400/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl +++ b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl index 2cf17a7f69..70c5da5ef0 100644 --- a/src/mainboard/elmex/pcm205400/acpi/routing.asl +++ b/src/mainboard/elmex/pcm205400/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/elmex/pcm205400/acpi/sata.asl +++ b/src/mainboard/elmex/pcm205400/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl index 47de049dbc..08144ff427 100644 --- a/src/mainboard/elmex/pcm205400/acpi/sleep.asl +++ b/src/mainboard/elmex/pcm205400/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl index a209909b32..5b22875dd1 100644 --- a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl +++ b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/bootblock.c b/src/mainboard/elmex/pcm205400/bootblock.c index 6cd9e2a59a..4afb0970c5 100644 --- a/src/mainboard/elmex/pcm205400/bootblock.c +++ b/src/mainboard/elmex/pcm205400/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index 863a552430..77551070de 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout index 1144223c24..abee2f269f 100644 --- a/src/mainboard/elmex/pcm205400/cmos.layout +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index 902b892adb..db62099aef 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index 5496288651..13df85b261 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index d83286e1e0..3da820e067 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 6ca8a80771..218024134a 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index bc7a3ac38f..7b8476db20 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index 593ccc790b..2f178292a6 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index a9bbe6e471..510c418ae3 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 0579b04c90..fcf2468854 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Asami Doi . # # SPDX-License-Identifier: GPL-2.0-or-later diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc index b710f15587..cdedfd46e2 100644 --- a/src/mainboard/emulation/qemu-aarch64/Makefile.inc +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Asami Doi # # SPDX-License-Identifier: GPL-2.0-or-later diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S index f9e85d0efc..50fb0ae873 100644 --- a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S +++ b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S @@ -1,7 +1,6 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2019 Asami Doi * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index 43894333e4..d02a3b293c 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Asami Doi * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb index 010cae8e91..424ce2b14b 100644 --- a/src/mainboard/emulation/qemu-aarch64/devicetree.cb +++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Asami Doi . # # SPDX-License-Identifier: GPL-2.0-or-later diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h index 7233863934..9769902ea6 100644 --- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Asami Doi * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index 2980f483d8..1cdebc0d2d 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Asami Doi * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/emulation/qemu-aarch64/media.c b/src/mainboard/emulation/qemu-aarch64/media.c index 03f0eb1bf8..3d21650109 100644 --- a/src/mainboard/emulation/qemu-aarch64/media.c +++ b/src/mainboard/emulation/qemu-aarch64/media.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Asami Doi * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index 4af2362474..eef6c96786 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Asami Doi * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c index 717d8581d2..c913532dac 100644 --- a/src/mainboard/emulation/qemu-aarch64/mmio.c +++ b/src/mainboard/emulation/qemu-aarch64/mmio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Asami Doi . * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 181f9a45a9..cc24676640 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index c62915bc78..d45234810a 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-armv7/devicetree.cb b/src/mainboard/emulation/qemu-armv7/devicetree.cb index 91534427a9..bce9ed81f5 100644 --- a/src/mainboard/emulation/qemu-armv7/devicetree.cb +++ b/src/mainboard/emulation/qemu-armv7/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google, Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 338cff9321..d3e14c1fb0 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c index c0f6a39e70..d271afef4a 100644 --- a/src/mainboard/emulation/qemu-armv7/media.c +++ b/src/mainboard/emulation/qemu-armv7/media.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 2b33cb39f3..aa8588254a 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c index 684b2490a0..e881ca1a77 100644 --- a/src/mainboard/emulation/qemu-armv7/romstage.c +++ b/src/mainboard/emulation/qemu-armv7/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-armv7/timer.c b/src/mainboard/emulation/qemu-armv7/timer.c index 13abe19ef1..5359827e65 100644 --- a/src/mainboard/emulation/qemu-armv7/timer.c +++ b/src/mainboard/emulation/qemu-armv7/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index 2829289867..e4763cdbdd 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 0b3689731e..6f0cd18349 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2010 Kevin O'Connor * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 098b3c2632..bc9fc602b3 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-i440fx/memory.h b/src/mainboard/emulation/qemu-i440fx/memory.h index d3b21a6673..33201b6f7f 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.h +++ b/src/mainboard/emulation/qemu-i440fx/memory.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 8e5691fc71..6c9d946ce6 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index 0496178bd9..1ed1041754 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index 307cb191bd..3e0dfa1d39 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index d59ab37351..c984039c97 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 7d6d4a80d9..2bacc2b07c 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-power8/devicetree.cb b/src/mainboard/emulation/qemu-power8/devicetree.cb index 6096ad0a6f..b99d29507c 100644 --- a/src/mainboard/emulation/qemu-power8/devicetree.cb +++ b/src/mainboard/emulation/qemu-power8/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google, Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c index 6d75bb1aae..6bfd0b3867 100644 --- a/src/mainboard/emulation/qemu-power8/mainboard.c +++ b/src/mainboard/emulation/qemu-power8/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index c22d3e4f25..fe7070b642 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Raptor Engineering, LLC - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-power8/romstage.c b/src/mainboard/emulation/qemu-power8/romstage.c index 684b2490a0..e881ca1a77 100644 --- a/src/mainboard/emulation/qemu-power8/romstage.c +++ b/src/mainboard/emulation/qemu-power8/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 27eb2f4f8f..661b680dcc 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index d137f52ead..65ff8870fd 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index ae3f96a158..1784321da0 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2010 Kevin O'Connor * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index b7fdac2552..602b981b15 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 4d4c900138..8788f33920 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 2ca75fdae1..5c283ab2f1 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 4a00bc2142..deceb5b804 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb index e3ce08829e..6276a59002 100644 --- a/src/mainboard/emulation/qemu-riscv/devicetree.cb +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google, Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index fd8c136548..d0a8f39091 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 88898087f4..de7765e5d6 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index e53df3845e..2fb1b1bb98 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 79e5ca8f54..7543ab9ab4 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c index 52c69f93d6..82f1a360db 100644 --- a/src/mainboard/emulation/qemu-riscv/romstage.c +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 271e994493..3adc61ecc0 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index 2fe0e1798f..cfaee34cb3 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index bfeaf58867..da092e72cc 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index c39e05831c..c3fa3387f0 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/spike-riscv/devicetree.cb b/src/mainboard/emulation/spike-riscv/devicetree.cb index e3ce08829e..6276a59002 100644 --- a/src/mainboard/emulation/spike-riscv/devicetree.cb +++ b/src/mainboard/emulation/spike-riscv/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google, Inc. ## ## This software is licensed under the terms of the GNU General Public ## License version 2, as published by the Free Software Foundation, and diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv/mainboard.c index 5d2b0b9c7b..1369a54d70 100644 --- a/src/mainboard/emulation/spike-riscv/mainboard.c +++ b/src/mainboard/emulation/spike-riscv/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index b6e4d9d5e8..6b647b6e5b 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv/rom_media.c index 10952a39ee..2ee04927e8 100644 --- a/src/mainboard/emulation/spike-riscv/rom_media.c +++ b/src/mainboard/emulation/spike-riscv/rom_media.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright 2016 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv/romstage.c index b3d1b4d559..118e9562b9 100644 --- a/src/mainboard/emulation/spike-riscv/romstage.c +++ b/src/mainboard/emulation/spike-riscv/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index b44c7b3496..f916f61fb2 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index abccfe1371..4c177e914a 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index 07b3e351af..09142b7605 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl index a7c9849011..1f9de2d03c 100644 --- a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl +++ b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl index 4fa6772128..7bcd3cc08e 100644 --- a/src/mainboard/facebook/fbg1701/acpi/superio.asl +++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index 15c955afc2..f831352086 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 69272de78b..12b35accad 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index d2ba78de2b..f869773c56 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.h b/src/mainboard/facebook/fbg1701/board_verified_boot.h index 20f53285ab..a8734166d5 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.h +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout index c293c5f989..e809c23a59 100644 --- a/src/mainboard/facebook/fbg1701/cmos.layout +++ b/src/mainboard/facebook/fbg1701/cmos.layout @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corp. -## Copyright (C) 2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/com_init.c b/src/mainboard/facebook/fbg1701/com_init.c index fc640dd236..e1ddc617af 100644 --- a/src/mainboard/facebook/fbg1701/com_init.c +++ b/src/mainboard/facebook/fbg1701/com_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/cpld.c b/src/mainboard/facebook/fbg1701/cpld.c index 7d1117f6ad..8dbd579a43 100644 --- a/src/mainboard/facebook/fbg1701/cpld.c +++ b/src/mainboard/facebook/fbg1701/cpld.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/cpld.h b/src/mainboard/facebook/fbg1701/cpld.h index 9604cfbc51..08a91cb7a2 100644 --- a/src/mainboard/facebook/fbg1701/cpld.h +++ b/src/mainboard/facebook/fbg1701/cpld.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index 707e48b504..f343f32c05 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015-2018 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/fadt.c b/src/mainboard/facebook/fbg1701/fadt.c index 544d24ba55..abc1bdd77e 100644 --- a/src/mainboard/facebook/fbg1701/fadt.c +++ b/src/mainboard/facebook/fbg1701/fadt.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/gpio.c b/src/mainboard/facebook/fbg1701/gpio.c index 5a73ca9148..1cc07c5859 100644 --- a/src/mainboard/facebook/fbg1701/gpio.c +++ b/src/mainboard/facebook/fbg1701/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/hda_verb.c b/src/mainboard/facebook/fbg1701/hda_verb.c index c06bbb3485..f0481cf93d 100644 --- a/src/mainboard/facebook/fbg1701/hda_verb.c +++ b/src/mainboard/facebook/fbg1701/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/facebook/fbg1701/irqroute.c b/src/mainboard/facebook/fbg1701/irqroute.c index a4ff6bf2b2..f0855adbc2 100644 --- a/src/mainboard/facebook/fbg1701/irqroute.c +++ b/src/mainboard/facebook/fbg1701/irqroute.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/irqroute.h b/src/mainboard/facebook/fbg1701/irqroute.h index 6b7cb4169e..6e3a083087 100644 --- a/src/mainboard/facebook/fbg1701/irqroute.h +++ b/src/mainboard/facebook/fbg1701/irqroute.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c index 8524b24000..9425c11139 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/manifest.h b/src/mainboard/facebook/fbg1701/manifest.h index caf9e5ecd6..0a82b22a59 100644 --- a/src/mainboard/facebook/fbg1701/manifest.h +++ b/src/mainboard/facebook/fbg1701/manifest.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 055c733fef..01af4aca09 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019 Facebook, Inc - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index b6ea03f969..7f453f535c 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c018620d3b..fa56b54d96 100644 --- a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Facebook, Inc. -# Copyright (C) 2019 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex index f18cbc2a87..410ca84659 100644 --- a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index 64faf1e163..ef862dab48 100644 --- a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2018-2019 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c index 2f131f4ec6..24d69dcee9 100644 --- a/src/mainboard/facebook/fbg1701/w25q64.c +++ b/src/mainboard/facebook/fbg1701/w25q64.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/Makefile.inc b/src/mainboard/facebook/monolith/Makefile.inc index 0cccd26f71..91867e8d4c 100644 --- a/src/mainboard/facebook/monolith/Makefile.inc +++ b/src/mainboard/facebook/monolith/Makefile.inc @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2016 Intel Corporation. -## Copyright (C) 2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/acpi/dptf.asl b/src/mainboard/facebook/monolith/acpi/dptf.asl index 181f7bc251..5eb87cb78b 100644 --- a/src/mainboard/facebook/monolith/acpi/dptf.asl +++ b/src/mainboard/facebook/monolith/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl index dc7a4ead55..94012bf0c8 100644 --- a/src/mainboard/facebook/monolith/acpi/ec.asl +++ b/src/mainboard/facebook/monolith/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/facebook/monolith/acpi/mainboard.asl b/src/mainboard/facebook/monolith/acpi/mainboard.asl index f40af806d2..525126269d 100644 --- a/src/mainboard/facebook/monolith/acpi/mainboard.asl +++ b/src/mainboard/facebook/monolith/acpi/mainboard.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl index 537d9f8419..a7763b91e0 100644 --- a/src/mainboard/facebook/monolith/acpi/superio.asl +++ b/src/mainboard/facebook/monolith/acpi/superio.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout index 04b2e15a3d..25ce77a647 100644 --- a/src/mainboard/facebook/monolith/cmos.layout +++ b/src/mainboard/facebook/monolith/cmos.layout @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2016 Intel Corporation. -## Copyright (C) 2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c index d2519fa26d..a7ad263bc3 100644 --- a/src/mainboard/facebook/monolith/com_init.c +++ b/src/mainboard/facebook/monolith/com_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 004cc62a0f..892456757c 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h index 4dae94bca5..a007f37537 100644 --- a/src/mainboard/facebook/monolith/gpio.h +++ b/src/mainboard/facebook/monolith/gpio.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/mainboard.c b/src/mainboard/facebook/monolith/mainboard.c index 3d6532e2d8..9425c11139 100644 --- a/src/mainboard/facebook/monolith/mainboard.c +++ b/src/mainboard/facebook/monolith/mainboard.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/onboard.h b/src/mainboard/facebook/monolith/onboard.h index 68b5feaec5..83f51034b3 100644 --- a/src/mainboard/facebook/monolith/onboard.h +++ b/src/mainboard/facebook/monolith/onboard.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c index 05cbf31adc..0c8273ef58 100644 --- a/src/mainboard/facebook/monolith/ramstage.c +++ b/src/mainboard/facebook/monolith/ramstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corporation - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/romstage.c b/src/mainboard/facebook/monolith/romstage.c index 7c54708f2c..2674f0c7d9 100644 --- a/src/mainboard/facebook/monolith/romstage.c +++ b/src/mainboard/facebook/monolith/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corporation. - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/spd/Makefile.inc b/src/mainboard/facebook/monolith/spd/Makefile.inc index b4b42f7856..b312ae55f3 100644 --- a/src/mainboard/facebook/monolith/spd/Makefile.inc +++ b/src/mainboard/facebook/monolith/spd/Makefile.inc @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. -## Copyright (C) 2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/spd/spd.h b/src/mainboard/facebook/monolith/spd/spd.h index e24be2fc22..5468eba1a7 100644 --- a/src/mainboard/facebook/monolith/spd/spd.h +++ b/src/mainboard/facebook/monolith/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/facebook/monolith/spd/spd_util.c b/src/mainboard/facebook/monolith/spd/spd_util.c index b85454a788..63c035e6e6 100644 --- a/src/mainboard/facebook/monolith/spd/spd_util.c +++ b/src/mainboard/facebook/monolith/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/Kconfig b/src/mainboard/foxconn/Kconfig index 30994f0e6b..a18997cdb9 100644 --- a/src/mainboard/foxconn/Kconfig +++ b/src/mainboard/foxconn/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Samuel Holland ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig index 4805fe0fd4..4741012602 100644 --- a/src/mainboard/foxconn/d41s/Kconfig +++ b/src/mainboard/foxconn/d41s/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl index 23c39ef5f2..6323193c96 100644 --- a/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/d41s/acpi/superio.asl b/src/mainboard/foxconn/d41s/acpi/superio.asl index 07742e88a2..d3d0252932 100644 --- a/src/mainboard/foxconn/d41s/acpi/superio.asl +++ b/src/mainboard/foxconn/d41s/acpi/superio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c index 6e619f494f..69787a93ea 100644 --- a/src/mainboard/foxconn/d41s/acpi_tables.c +++ b/src/mainboard/foxconn/d41s/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index b006973cc3..9fb41481e4 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/d41s/cstates.c b/src/mainboard/foxconn/d41s/cstates.c index bee17799df..62b3bd3fba 100644 --- a/src/mainboard/foxconn/d41s/cstates.c +++ b/src/mainboard/foxconn/d41s/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 4ada05cc1e..7594f489a4 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2018 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl index a0e9b626f7..88b4e126e5 100644 --- a/src/mainboard/foxconn/d41s/dsdt.asl +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/d41s/early_init.c b/src/mainboard/foxconn/d41s/early_init.c index ea3f6a9ca7..e37cc82265 100644 --- a/src/mainboard/foxconn/d41s/early_init.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2018 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/d41s/gpio.c b/src/mainboard/foxconn/d41s/gpio.c index e88e4db0c6..5da221d047 100644 --- a/src/mainboard/foxconn/d41s/gpio.c +++ b/src/mainboard/foxconn/d41s/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/d41s/hda_verb.c b/src/mainboard/foxconn/d41s/hda_verb.c index dbe383e6f3..93d0144f83 100644 --- a/src/mainboard/foxconn/d41s/hda_verb.c +++ b/src/mainboard/foxconn/d41s/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/d41s/mainboard.c b/src/mainboard/foxconn/d41s/mainboard.c index 3263f9a065..dd930d31ad 100644 --- a/src/mainboard/foxconn/d41s/mainboard.c +++ b/src/mainboard/foxconn/d41s/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig index c35575835d..e05d9c3cc5 100644 --- a/src/mainboard/foxconn/g41s-k/Kconfig +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Damien Zammit -## Copyright (C) 2017 Samuel Holland ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl index 62470113ea..2767faaad8 100644 --- a/src/mainboard/foxconn/g41s-k/acpi/superio.asl +++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c index 7c0ee9a807..b0940a0063 100644 --- a/src/mainboard/foxconn/g41s-k/acpi_tables.c +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index e6df510341..bdbf2e13dc 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/cstates.c b/src/mainboard/foxconn/g41s-k/cstates.c index 3ac18c24c5..2a6d8ad816 100644 --- a/src/mainboard/foxconn/g41s-k/cstates.c +++ b/src/mainboard/foxconn/g41s-k/cstates.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 270d1355f1..dfc1534997 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Damien Zammit -## Copyright (C) 2017 Arthur Heymans -## Copyright (C) 2017 Samuel Holland ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index cddaa3af4e..6120949269 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/g41s-k/early_init.c b/src/mainboard/foxconn/g41s-k/early_init.c index 454b1ea0b0..c2d7c1b331 100644 --- a/src/mainboard/foxconn/g41s-k/early_init.c +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/gpio.c b/src/mainboard/foxconn/g41s-k/gpio.c index 6162898d5a..8d43757fd5 100644 --- a/src/mainboard/foxconn/g41s-k/gpio.c +++ b/src/mainboard/foxconn/g41s-k/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c index bb787b202b..f92d75164c 100644 --- a/src/mainboard/foxconn/g41s-k/hda_verb.c +++ b/src/mainboard/foxconn/g41s-k/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl index f1f3462d49..b5d41b2e67 100644 --- a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl index 9d10d81d69..1ecd961916 100644 --- a/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans - * Copyright (C) 2017 Samuel Holland * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as From 53a9e418913df9becc5a42a8e4e33466db528e1b Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 12:51:24 +0100 Subject: [PATCH 0498/1463] mainboard/[^a-p]*: Remove copyright notices They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: David Hendricks Reviewed-by: Tristan Corrick --- src/mainboard/razer/blade_stealth_kbl/Makefile.inc | 1 - src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl | 1 - src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl | 1 - src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl | 1 - src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl | 1 - src/mainboard/razer/blade_stealth_kbl/dsdt.asl | 3 --- src/mainboard/razer/blade_stealth_kbl/gpio.h | 1 - src/mainboard/razer/blade_stealth_kbl/hda_verb.c | 2 -- src/mainboard/razer/blade_stealth_kbl/mainboard.c | 1 - src/mainboard/razer/blade_stealth_kbl/ramstage.c | 2 -- src/mainboard/razer/blade_stealth_kbl/romstage.c | 4 ---- src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc | 1 - src/mainboard/razer/blade_stealth_kbl/spd/spd.h | 3 --- src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c | 1 - src/mainboard/roda/rk886ex/Makefile.inc | 1 - src/mainboard/roda/rk886ex/acpi/battery.asl | 1 - src/mainboard/roda/rk886ex/acpi/ec.asl | 1 - src/mainboard/roda/rk886ex/acpi/gpe.asl | 1 - src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/roda/rk886ex/acpi/mainboard.asl | 1 - src/mainboard/roda/rk886ex/acpi/platform.asl | 1 - src/mainboard/roda/rk886ex/acpi/superio.asl | 1 - src/mainboard/roda/rk886ex/acpi/thermal.asl | 1 - src/mainboard/roda/rk886ex/acpi_tables.c | 1 - src/mainboard/roda/rk886ex/cmos.layout | 1 - src/mainboard/roda/rk886ex/devicetree.cb | 1 - src/mainboard/roda/rk886ex/dsdt.asl | 1 - src/mainboard/roda/rk886ex/early_init.c | 1 - src/mainboard/roda/rk886ex/gpio.c | 1 - src/mainboard/roda/rk886ex/irq_tables.c | 1 - src/mainboard/roda/rk886ex/m3885.c | 1 - src/mainboard/roda/rk886ex/m3885.h | 1 - src/mainboard/roda/rk886ex/mainboard.c | 1 - src/mainboard/roda/rk886ex/mptable.c | 1 - src/mainboard/roda/rk9/Makefile.inc | 1 - src/mainboard/roda/rk9/acpi/battery.asl | 2 -- src/mainboard/roda/rk9/acpi/ec.asl | 2 -- src/mainboard/roda/rk9/acpi/gpe.asl | 1 - src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl | 1 - src/mainboard/roda/rk9/acpi/mainboard.asl | 1 - src/mainboard/roda/rk9/acpi/platform.asl | 1 - src/mainboard/roda/rk9/acpi/superio.asl | 1 - src/mainboard/roda/rk9/acpi/thermal.asl | 2 -- src/mainboard/roda/rk9/acpi_tables.c | 1 - src/mainboard/roda/rk9/blc.c | 1 - src/mainboard/roda/rk9/bootblock.c | 1 - src/mainboard/roda/rk9/cmos.layout | 2 -- src/mainboard/roda/rk9/cstates.c | 1 - src/mainboard/roda/rk9/dsdt.asl | 1 - src/mainboard/roda/rk9/fadt.c | 1 - src/mainboard/roda/rk9/hda_verb.c | 2 -- src/mainboard/roda/rk9/mainboard.c | 1 - src/mainboard/roda/rk9/romstage.c | 1 - src/mainboard/roda/rk9/smihandler.c | 1 - src/mainboard/roda/rk9/ti_pci7xx1.c | 1 - src/mainboard/roda/rv11/Makefile.inc | 1 - src/mainboard/roda/rv11/acpi/alsd.asl | 1 - src/mainboard/roda/rv11/acpi/ec.asl | 1 - src/mainboard/roda/rv11/acpi/mainboard.asl | 1 - src/mainboard/roda/rv11/acpi/platform.asl | 1 - src/mainboard/roda/rv11/acpi/thermal.asl | 1 - src/mainboard/roda/rv11/acpi_tables.c | 1 - src/mainboard/roda/rv11/cmos.layout | 2 -- src/mainboard/roda/rv11/dsdt.asl | 1 - src/mainboard/roda/rv11/early_init.c | 1 - src/mainboard/roda/rv11/gpio.c | 1 - src/mainboard/roda/rv11/hda_verb.c | 1 - src/mainboard/roda/rv11/variants/rv11/devicetree.cb | 1 - src/mainboard/roda/rv11/variants/rv11/early_init.c | 1 - .../roda/rv11/variants/rv11/include/variant/hda_verb.h | 1 - .../roda/rv11/variants/rv11/include/variant/thermal.h | 1 - src/mainboard/roda/rv11/variants/rw11/devicetree.cb | 1 - src/mainboard/roda/rv11/variants/rw11/early_init.c | 1 - .../roda/rv11/variants/rw11/include/acpi/superio.asl | 1 - .../roda/rv11/variants/rw11/include/variant/hda_verb.h | 1 - .../roda/rv11/variants/rw11/include/variant/thermal.h | 1 - src/mainboard/samsung/lumpy/Makefile.inc | 1 - src/mainboard/samsung/lumpy/acpi/ec.asl | 1 - src/mainboard/samsung/lumpy/acpi/mainboard.asl | 1 - src/mainboard/samsung/lumpy/acpi/platform.asl | 1 - src/mainboard/samsung/lumpy/acpi/superio.asl | 1 - src/mainboard/samsung/lumpy/acpi/thermal.asl | 1 - src/mainboard/samsung/lumpy/acpi_tables.c | 1 - src/mainboard/samsung/lumpy/chromeos.c | 1 - src/mainboard/samsung/lumpy/cmos.layout | 1 - src/mainboard/samsung/lumpy/dsdt.asl | 2 -- src/mainboard/samsung/lumpy/early_init.c | 2 -- src/mainboard/samsung/lumpy/ec.c | 1 - src/mainboard/samsung/lumpy/ec.h | 1 - src/mainboard/samsung/lumpy/gpio.c | 1 - src/mainboard/samsung/lumpy/hda_verb.c | 1 - src/mainboard/samsung/lumpy/mainboard.c | 2 -- src/mainboard/samsung/lumpy/onboard.h | 1 - src/mainboard/samsung/lumpy/smihandler.c | 1 - src/mainboard/samsung/lumpy/thermal.h | 1 - src/mainboard/samsung/stumpy/Makefile.inc | 1 - src/mainboard/samsung/stumpy/acpi/mainboard.asl | 1 - src/mainboard/samsung/stumpy/acpi/platform.asl | 1 - src/mainboard/samsung/stumpy/acpi/superio.asl | 1 - src/mainboard/samsung/stumpy/acpi/thermal.asl | 1 - src/mainboard/samsung/stumpy/acpi_tables.c | 1 - src/mainboard/samsung/stumpy/chromeos.c | 1 - src/mainboard/samsung/stumpy/cmos.layout | 1 - src/mainboard/samsung/stumpy/dsdt.asl | 2 -- src/mainboard/samsung/stumpy/early_init.c | 2 -- src/mainboard/samsung/stumpy/gpio.c | 1 - src/mainboard/samsung/stumpy/hda_verb.c | 1 - src/mainboard/samsung/stumpy/mainboard.c | 2 -- src/mainboard/samsung/stumpy/smihandler.c | 1 - src/mainboard/samsung/stumpy/thermal.h | 1 - src/mainboard/sapphire/pureplatinumh61/Makefile.inc | 1 - src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl | 1 - src/mainboard/sapphire/pureplatinumh61/acpi_tables.c | 1 - src/mainboard/sapphire/pureplatinumh61/cmos.layout | 2 -- src/mainboard/sapphire/pureplatinumh61/devicetree.cb | 1 - src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 1 - src/mainboard/sapphire/pureplatinumh61/early_init.c | 1 - src/mainboard/sapphire/pureplatinumh61/gpio.c | 1 - src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 1 - src/mainboard/sapphire/pureplatinumh61/mainboard.c | 1 - src/mainboard/scaleway/tagada/Kconfig | 2 -- src/mainboard/scaleway/tagada/Makefile.inc | 2 -- src/mainboard/scaleway/tagada/acpi/mainboard.asl | 2 -- src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl | 1 - src/mainboard/scaleway/tagada/acpi/platform.asl | 3 --- src/mainboard/scaleway/tagada/acpi/thermal.asl | 1 - src/mainboard/scaleway/tagada/acpi_tables.c | 2 -- src/mainboard/scaleway/tagada/bmcinfo.c | 1 - src/mainboard/scaleway/tagada/bmcinfo.h | 1 - src/mainboard/scaleway/tagada/bootblock.c | 1 - src/mainboard/scaleway/tagada/devicetree.cb | 1 - src/mainboard/scaleway/tagada/dsdt.asl | 3 --- src/mainboard/scaleway/tagada/fadt.c | 3 --- src/mainboard/scaleway/tagada/gpio.h | 2 -- src/mainboard/scaleway/tagada/hsio.c | 2 -- src/mainboard/scaleway/tagada/hsio.h | 2 -- src/mainboard/scaleway/tagada/ramstage.c | 2 -- src/mainboard/scaleway/tagada/romstage.c | 2 -- src/mainboard/siemens/mc_apl1/bootblock.c | 1 - src/mainboard/siemens/mc_apl1/dsdt.asl | 1 - src/mainboard/siemens/mc_apl1/mainboard.c | 2 -- src/mainboard/siemens/mc_apl1/romstage.c | 2 -- src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c | 2 -- .../mc_apl1/variants/baseboard/include/baseboard/variants.h | 2 -- src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c | 2 -- src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c | 1 - src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c | 1 - src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c | 2 -- src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c | 1 - src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c | 2 -- src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | 1 - src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c | 2 -- src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c | 1 - src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c | 2 -- src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c | 2 -- src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c | 1 - src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c | 1 - src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c | 2 -- src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c | 1 - src/mainboard/sifive/hifive-unleashed/Kconfig | 1 - src/mainboard/sifive/hifive-unleashed/Makefile.inc | 1 - src/mainboard/sifive/hifive-unleashed/devicetree.cb | 1 - src/mainboard/sifive/hifive-unleashed/fixup_fdt.c | 1 - src/mainboard/sifive/hifive-unleashed/mainboard.c | 1 - src/mainboard/sifive/hifive-unleashed/media.c | 2 -- src/mainboard/sifive/hifive-unleashed/memlayout.ld | 1 - src/mainboard/sifive/hifive-unleashed/romstage.c | 1 - src/mainboard/supermicro/x10slm-f/Kconfig | 1 - src/mainboard/supermicro/x10slm-f/Makefile.inc | 1 - src/mainboard/supermicro/x10slm-f/acpi/platform.asl | 1 - src/mainboard/supermicro/x10slm-f/acpi/superio.asl | 1 - src/mainboard/supermicro/x10slm-f/acpi_tables.c | 1 - src/mainboard/supermicro/x10slm-f/bootblock.c | 1 - src/mainboard/supermicro/x10slm-f/cmos.layout | 2 -- src/mainboard/supermicro/x10slm-f/devicetree.cb | 1 - src/mainboard/supermicro/x10slm-f/dsdt.asl | 1 - src/mainboard/supermicro/x10slm-f/gpio.c | 1 - src/mainboard/supermicro/x10slm-f/hda_verb.c | 1 - src/mainboard/supermicro/x10slm-f/mainboard.c | 1 - src/mainboard/supermicro/x10slm-f/romstage.c | 3 --- src/mainboard/supermicro/x11-lga1151-series/Makefile.inc | 2 -- src/mainboard/supermicro/x11-lga1151-series/bootblock.c | 1 - src/mainboard/supermicro/x11-lga1151-series/cmos.layout | 1 - src/mainboard/supermicro/x11-lga1151-series/dsdt.asl | 3 --- src/mainboard/supermicro/x11-lga1151-series/mainboard.c | 3 --- .../variants/x11ssh-tf/include/variant/gpio.h | 1 - .../variants/x11ssm-f/include/variant/gpio.h | 1 - src/mainboard/system76/lemp9/acpi/ac.asl | 1 - src/mainboard/system76/lemp9/acpi/battery.asl | 1 - src/mainboard/system76/lemp9/acpi/buttons.asl | 1 - src/mainboard/system76/lemp9/acpi/ec.asl | 1 - src/mainboard/system76/lemp9/acpi/ec_ram.asl | 1 - src/mainboard/system76/lemp9/acpi/gpe.asl | 1 - src/mainboard/system76/lemp9/acpi/hid.asl | 1 - src/mainboard/system76/lemp9/acpi/lid.asl | 1 - src/mainboard/system76/lemp9/acpi/mainboard.asl | 1 - src/mainboard/system76/lemp9/acpi/s76.asl | 1 - src/mainboard/system76/lemp9/acpi/sleep.asl | 1 - src/mainboard/system76/lemp9/bootblock.c | 1 - src/mainboard/system76/lemp9/dsdt.asl | 3 --- src/mainboard/system76/lemp9/gpio.h | 1 - src/mainboard/system76/lemp9/hda_verb.c | 1 - src/mainboard/system76/lemp9/ramstage.c | 1 - src/mainboard/system76/lemp9/romstage.c | 1 - src/mainboard/ti/Kconfig | 1 - src/mainboard/ti/beaglebone/Kconfig | 1 - src/mainboard/ti/beaglebone/Makefile.inc | 1 - src/mainboard/ti/beaglebone/bootblock.c | 1 - src/mainboard/ti/beaglebone/devicetree.cb | 1 - src/mainboard/ti/beaglebone/romstage.c | 1 - src/mainboard/up/squared/bootblock.c | 1 - src/mainboard/up/squared/dsdt.asl | 1 - src/mainboard/up/squared/gpio.h | 1 - src/mainboard/up/squared/ramstage.c | 1 - src/mainboard/up/squared/romstage.c | 1 - 215 files changed, 274 deletions(-) diff --git a/src/mainboard/razer/blade_stealth_kbl/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc index e517484499..75cee14559 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Makefile.inc +++ b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl index 813c008e68..08d6b6d47d 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl index a89496d69e..a7a279877f 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 62a8622dc1..4b4356c857 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl index 6b8cb51380..7bc42ecb7c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index ef487451ea..87ad7c9811 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index 5bf1bc48df..bee21ce7a0 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c index 457d1d9447..5da6d53414 100644 --- a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c +++ b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/razer/blade_stealth_kbl/mainboard.c b/src/mainboard/razer/blade_stealth_kbl/mainboard.c index 7f1f11416a..6c0832f214 100644 --- a/src/mainboard/razer/blade_stealth_kbl/mainboard.c +++ b/src/mainboard/razer/blade_stealth_kbl/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Purism SPC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/ramstage.c b/src/mainboard/razer/blade_stealth_kbl/ramstage.c index 94f8071340..975951ecae 100644 --- a/src/mainboard/razer/blade_stealth_kbl/ramstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/ramstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index 445f620020..db7027ab4f 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Purism SPC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc index 3188dbf80e..c223562fb6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc +++ b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Johanna Schander ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h index 36363cc702..d02bb3415f 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2019 Johanna Schander * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c index a81653f7fd..cd6596043a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc index ab011673fd..decfef7d08 100644 --- a/src/mainboard/roda/rk886ex/Makefile.inc +++ b/src/mainboard/roda/rk886ex/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl index 8de0b7fdd1..59b17e1a6d 100644 --- a/src/mainboard/roda/rk886ex/acpi/battery.asl +++ b/src/mainboard/roda/rk886ex/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index fd5ae35f40..6839f8e0bf 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi/gpe.asl b/src/mainboard/roda/rk886ex/acpi/gpe.asl index ef3c86dadb..2e27d9faf7 100644 --- a/src/mainboard/roda/rk886ex/acpi/gpe.asl +++ b/src/mainboard/roda/rk886ex/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl index 321be6e113..c49624fec9 100644 --- a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi/mainboard.asl b/src/mainboard/roda/rk886ex/acpi/mainboard.asl index 5411f116ae..460360a9b4 100644 --- a/src/mainboard/roda/rk886ex/acpi/mainboard.asl +++ b/src/mainboard/roda/rk886ex/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index ebd22afe07..e873efff56 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index d1776096f1..1d5ef74c9b 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index 6a4d701988..405a9e0bb9 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index d58151c1ac..0675b4114d 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 57ffa43e73..03c865c5b8 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 93a40417fc..5c868b75cd 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index a27ba350fa..45adb82081 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index b0d08f4dd2..a0ae5fcee5 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/gpio.c b/src/mainboard/roda/rk886ex/gpio.c index 72868ca351..f1c6af0781 100644 --- a/src/mainboard/roda/rk886ex/gpio.c +++ b/src/mainboard/roda/rk886ex/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c index 29331fce2e..bc9fe78db7 100644 --- a/src/mainboard/roda/rk886ex/irq_tables.c +++ b/src/mainboard/roda/rk886ex/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index d4e90b83cc..5c514dc6c1 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/m3885.h b/src/mainboard/roda/rk886ex/m3885.h index d2dcb146a7..ccf3aca770 100644 --- a/src/mainboard/roda/rk886ex/m3885.h +++ b/src/mainboard/roda/rk886ex/m3885.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 922eba2d43..d203716dad 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index e17dcc2e4f..88d2aa29f1 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index 1140e11d0f..ffedbf60e1 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk9/acpi/battery.asl b/src/mainboard/roda/rk9/acpi/battery.asl index 2f793d8ca8..c4875786fa 100644 --- a/src/mainboard/roda/rk9/acpi/battery.asl +++ b/src/mainboard/roda/rk9/acpi/battery.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index aef4d321c6..dbe7f29ee6 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi/gpe.asl b/src/mainboard/roda/rk9/acpi/gpe.asl index 5ba35386c1..8d08361b65 100644 --- a/src/mainboard/roda/rk9/acpi/gpe.asl +++ b/src/mainboard/roda/rk9/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl index b206c2b992..ecc805abcf 100644 --- a/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl +++ b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi/mainboard.asl b/src/mainboard/roda/rk9/acpi/mainboard.asl index 892637d45b..204f8308aa 100644 --- a/src/mainboard/roda/rk9/acpi/mainboard.asl +++ b/src/mainboard/roda/rk9/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl index 45ac1dd2c2..451d19785f 100644 --- a/src/mainboard/roda/rk9/acpi/platform.asl +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi/superio.asl b/src/mainboard/roda/rk9/acpi/superio.asl index d1776096f1..1d5ef74c9b 100644 --- a/src/mainboard/roda/rk9/acpi/superio.asl +++ b/src/mainboard/roda/rk9/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index d7f8364f60..de6fd028a3 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 4337fac04d..fc9a16ce82 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/blc.c b/src/mainboard/roda/rk9/blc.c index 4b6104ec05..a8171a26c4 100644 --- a/src/mainboard/roda/rk9/blc.c +++ b/src/mainboard/roda/rk9/blc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 arthur@aheymans.xyz * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk9/bootblock.c b/src/mainboard/roda/rk9/bootblock.c index 454c3a0418..a7f4b3aaf7 100644 --- a/src/mainboard/roda/rk9/bootblock.c +++ b/src/mainboard/roda/rk9/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index d794306e22..7e3319be02 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH -# 2012 secunet Security Networks AG # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c index fea92769b5..a167f91135 100644 --- a/src/mainboard/roda/rk9/cstates.c +++ b/src/mainboard/roda/rk9/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index c9bd5c7d18..5a1d21b53e 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index 9f4ebf6fe5..c3c9015ab6 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/hda_verb.c b/src/mainboard/roda/rk9/hda_verb.c index a7d26987ce..088f99a195 100644 --- a/src/mainboard/roda/rk9/hda_verb.c +++ b/src/mainboard/roda/rk9/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 6057901f2c..a72ae76afd 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 48ca6b6b7d..beebb70051 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c index 72f1d35ea4..fc730cbd3b 100644 --- a/src/mainboard/roda/rk9/smihandler.c +++ b/src/mainboard/roda/rk9/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c index 4154cc86bd..e55542907a 100644 --- a/src/mainboard/roda/rk9/ti_pci7xx1.c +++ b/src/mainboard/roda/rk9/ti_pci7xx1.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index a3d6d5913f..e715be723e 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015-2016 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/acpi/alsd.asl b/src/mainboard/roda/rv11/acpi/alsd.asl index 120332d862..3b90d1eefa 100644 --- a/src/mainboard/roda/rv11/acpi/alsd.asl +++ b/src/mainboard/roda/rv11/acpi/alsd.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/acpi/ec.asl b/src/mainboard/roda/rv11/acpi/ec.asl index a1bcbb1fc8..9a9decaf3e 100644 --- a/src/mainboard/roda/rv11/acpi/ec.asl +++ b/src/mainboard/roda/rv11/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/acpi/mainboard.asl b/src/mainboard/roda/rv11/acpi/mainboard.asl index a91c5d6ba5..4c111e2351 100644 --- a/src/mainboard/roda/rv11/acpi/mainboard.asl +++ b/src/mainboard/roda/rv11/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/acpi/platform.asl b/src/mainboard/roda/rv11/acpi/platform.asl index df21c8c70c..cb4c8835e7 100644 --- a/src/mainboard/roda/rv11/acpi/platform.asl +++ b/src/mainboard/roda/rv11/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/acpi/thermal.asl b/src/mainboard/roda/rv11/acpi/thermal.asl index f18ee292fb..4f56d207d6 100644 --- a/src/mainboard/roda/rv11/acpi/thermal.asl +++ b/src/mainboard/roda/rv11/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/acpi_tables.c b/src/mainboard/roda/rv11/acpi_tables.c index 8c7d62d2d5..7ff962f54c 100644 --- a/src/mainboard/roda/rv11/acpi_tables.c +++ b/src/mainboard/roda/rv11/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/cmos.layout b/src/mainboard/roda/rv11/cmos.layout index c8b94c060a..8d383a3d6e 100644 --- a/src/mainboard/roda/rv11/cmos.layout +++ b/src/mainboard/roda/rv11/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index fb3b227949..f42cef7ee9 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/early_init.c b/src/mainboard/roda/rv11/early_init.c index 5c5e8d8b93..bb6ff0d0c2 100644 --- a/src/mainboard/roda/rv11/early_init.c +++ b/src/mainboard/roda/rv11/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/gpio.c b/src/mainboard/roda/rv11/gpio.c index 54930d082e..751ccc727e 100644 --- a/src/mainboard/roda/rv11/gpio.c +++ b/src/mainboard/roda/rv11/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/hda_verb.c b/src/mainboard/roda/rv11/hda_verb.c index fbaec16d9c..8ab845deda 100644 --- a/src/mainboard/roda/rv11/hda_verb.c +++ b/src/mainboard/roda/rv11/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 68f2ba437f..29bf6c9c72 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015-2016 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index bd4d5c5726..1a9c47e328 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h index e80edc5217..bb92eab2dc 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h +++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h index 31cf28e4f2..e742e677dc 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h +++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 76ad9859c6..ea05ddc444 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index cefb6d653b..da19839359 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl index ae531670a7..0ced6ad3a4 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl +++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h index edc5f64624..d86e335bd2 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h +++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h index d3b72cd9f4..1da8621eb0 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h +++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index e6e65aa096..cf8ef70d11 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/acpi/ec.asl b/src/mainboard/samsung/lumpy/acpi/ec.asl index 79b2edebf6..9d50a588d9 100644 --- a/src/mainboard/samsung/lumpy/acpi/ec.asl +++ b/src/mainboard/samsung/lumpy/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index 0fceabf4a9..080bff9b79 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl index bbd3d41f71..11a304e90f 100644 --- a/src/mainboard/samsung/lumpy/acpi/platform.asl +++ b/src/mainboard/samsung/lumpy/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl index 988ec429f1..dfd89f751c 100644 --- a/src/mainboard/samsung/lumpy/acpi/superio.asl +++ b/src/mainboard/samsung/lumpy/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/acpi/thermal.asl b/src/mainboard/samsung/lumpy/acpi/thermal.asl index 330d9af656..b1df43e487 100644 --- a/src/mainboard/samsung/lumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/lumpy/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 3e921870fc..9ef9d1cc28 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 5b58144fa3..55dee06e5a 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index b400faf3ff..d68a85aa3f 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index eb22e6a4a3..a6f38d9da3 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 0249c3bc56..bfb1b49f8b 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index 708031c8f1..492e6e9133 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/ec.h b/src/mainboard/samsung/lumpy/ec.h index 0cdb87e8ae..b0114ade6f 100644 --- a/src/mainboard/samsung/lumpy/ec.h +++ b/src/mainboard/samsung/lumpy/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c index 103763d6e2..565a9facc3 100644 --- a/src/mainboard/samsung/lumpy/gpio.c +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c index f889259137..12de96ab00 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.c +++ b/src/mainboard/samsung/lumpy/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index e28e0d82ef..44360ee896 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index 75a9da544a..63f019061f 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 627a3a7719..fc10b35111 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/lumpy/thermal.h b/src/mainboard/samsung/lumpy/thermal.h index 4dd37bb7b9..64145f59f3 100644 --- a/src/mainboard/samsung/lumpy/thermal.h +++ b/src/mainboard/samsung/lumpy/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index de233ce0cd..5c6d56ab90 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/acpi/mainboard.asl b/src/mainboard/samsung/stumpy/acpi/mainboard.asl index 57811834e1..b41486f960 100644 --- a/src/mainboard/samsung/stumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/stumpy/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/samsung/stumpy/acpi/platform.asl b/src/mainboard/samsung/stumpy/acpi/platform.asl index aee066bf89..e48bc4367d 100644 --- a/src/mainboard/samsung/stumpy/acpi/platform.asl +++ b/src/mainboard/samsung/stumpy/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/acpi/superio.asl b/src/mainboard/samsung/stumpy/acpi/superio.asl index 5ec96a42e4..73737f3817 100644 --- a/src/mainboard/samsung/stumpy/acpi/superio.asl +++ b/src/mainboard/samsung/stumpy/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl index 9987257508..896d001976 100644 --- a/src/mainboard/samsung/stumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 07f4fda32a..637abfabe6 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 36efb8af64..d8e2c87720 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index d54ae7df24..885c3e2e53 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index b135097983..425efa88fe 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 13da85ada6..d6ace45337 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/gpio.c b/src/mainboard/samsung/stumpy/gpio.c index 282f816c53..f4ca4209ce 100644 --- a/src/mainboard/samsung/stumpy/gpio.c +++ b/src/mainboard/samsung/stumpy/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/hda_verb.c b/src/mainboard/samsung/stumpy/hda_verb.c index e3677defac..23063707b8 100644 --- a/src/mainboard/samsung/stumpy/hda_verb.c +++ b/src/mainboard/samsung/stumpy/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index a62ad12c8d..45a60c670a 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index b78d9383f3..3bcb1dff23 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/samsung/stumpy/thermal.h b/src/mainboard/samsung/stumpy/thermal.h index ed40e9d5a4..9b8db33c4a 100644 --- a/src/mainboard/samsung/stumpy/thermal.h +++ b/src/mainboard/samsung/stumpy/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 8d8f3ee51f..56b1e09dda 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Nicola Corna # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl index 86af6f437c..cb4c8835e7 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl +++ b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c index a27584394a..f8bbf887d3 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Nicola Corna * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout index 15a0633c6b..68acd817bb 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.layout +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 9a42a7b453..529e6feb29 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Nicola Corna # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index be30f638e1..8b23ee7b85 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Nicola Corna * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index 9a1b6856ff..a13e580b4c 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Nicola Corna * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c index b58e0edca4..33dd607a45 100644 --- a/src/mainboard/sapphire/pureplatinumh61/gpio.c +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Nicola Corna * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c index 415eb87134..f0ed031328 100644 --- a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Nicola Corna * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c index 2267ec73ca..e142ee20ea 100644 --- a/src/mainboard/sapphire/pureplatinumh61/mainboard.c +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Nicola Corna * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig index 21088cbb00..6c4f57a9b0 100644 --- a/src/mainboard/scaleway/tagada/Kconfig +++ b/src/mainboard/scaleway/tagada/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2017 Intel Corporation. -## Copyright (C) 2017 - 2018 Online SAS ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc index 8370c8aaac..38763e53bb 100644 --- a/src/mainboard/scaleway/tagada/Makefile.inc +++ b/src/mainboard/scaleway/tagada/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2017 Intel Corporation. -## Copyright (C) 2017 Online SAS. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard.asl b/src/mainboard/scaleway/tagada/acpi/mainboard.asl index 41da3824ef..8d3f505cc6 100644 --- a/src/mainboard/scaleway/tagada/acpi/mainboard.asl +++ b/src/mainboard/scaleway/tagada/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl index e253cea8a2..b7254c91ba 100644 --- a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl +++ b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/acpi/platform.asl b/src/mainboard/scaleway/tagada/acpi/platform.asl index 8d8229ab43..a1a1d214b9 100644 --- a/src/mainboard/scaleway/tagada/acpi/platform.asl +++ b/src/mainboard/scaleway/tagada/acpi/platform.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/acpi/thermal.asl b/src/mainboard/scaleway/tagada/acpi/thermal.asl index 5f9164da0d..8244266532 100644 --- a/src/mainboard/scaleway/tagada/acpi/thermal.asl +++ b/src/mainboard/scaleway/tagada/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 1f92419a75..551d51a47d 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 61dac153af..d07ed3063f 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 - 2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/bmcinfo.h b/src/mainboard/scaleway/tagada/bmcinfo.h index 8e64a84b29..e433d037c1 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.h +++ b/src/mainboard/scaleway/tagada/bmcinfo.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/bootblock.c b/src/mainboard/scaleway/tagada/bootblock.c index b03583c4a2..301a9b260a 100644 --- a/src/mainboard/scaleway/tagada/bootblock.c +++ b/src/mainboard/scaleway/tagada/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb index acf56a072d..6f766a6a7f 100644 --- a/src/mainboard/scaleway/tagada/devicetree.cb +++ b/src/mainboard/scaleway/tagada/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index 32d6e3d395..41e9b5d957 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright 2011 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index f40841efc3..bb4b31eb46 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. - * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/gpio.h b/src/mainboard/scaleway/tagada/gpio.h index b1572d292e..3edb1baa8d 100644 --- a/src/mainboard/scaleway/tagada/gpio.h +++ b/src/mainboard/scaleway/tagada/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. - * Copyright (C) 2017 - 2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index a8a2035f26..94db73d831 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * Copyright (C) 2017 - 2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index aa6af53cbb..f651855cbf 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corporation. - * Copyright (C) 2017 - 2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c index d592d99cf4..f064b74ad9 100644 --- a/src/mainboard/scaleway/tagada/ramstage.c +++ b/src/mainboard/scaleway/tagada/ramstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation - * Copyright (C) 2017 - 2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c index f14c1b6e3c..5d024c8780 100644 --- a/src/mainboard/scaleway/tagada/romstage.c +++ b/src/mainboard/scaleway/tagada/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. - * Copyright (C) 2017 - 2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index e35e8b8e7f..3c8d5bd89c 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index 8e08b16626..b597480330 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 784a08c670..716f4e0f74 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 14836362d6..c967063416 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index dd9736401a..eeab878610 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h index 6828ed81e3..1ee4281aca 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c index 51bf40e245..c90e1e4a94 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c index e61588a02e..5efced8bd5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index f119d5d19b..9698c2b007 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index b316d9727d..4a7255e665 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 2502a921fe..e6aff80055 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index 7401c74a01..12f8339fd0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 6a883c6a26..36c736bd26 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index 492dae6418..8b3e7e2693 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c index abfcfe37a8..641b7488a6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c index 9820f1e34e..af0bf4672a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index 3edf14f8c2..39e086a39e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c index 1b0f730d0b..90aade5b45 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index f43cf8588c..4c696adbb3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c index 43c2487032..38b7c4473e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index f908ab6713..6ba13fea92 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 460fdfb234..d45b6596ed 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -1,6 +1,5 @@ # This file is part of the coreboot project. # -# Copyright (C) 2018 Jonathan Neuschäfer # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 88ea145eef..3d31c73b58 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -1,6 +1,5 @@ # This file is part of the coreboot project. # -# Copyright (C) 2018 Jonathan Neuschäfer # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/devicetree.cb b/src/mainboard/sifive/hifive-unleashed/devicetree.cb index 1c9f79ad92..c28752a4e6 100644 --- a/src/mainboard/sifive/hifive-unleashed/devicetree.cb +++ b/src/mainboard/sifive/hifive-unleashed/devicetree.cb @@ -1,6 +1,5 @@ # This file is part of the coreboot project. # -# Copyright (C) 2018 Jonathan Neuschäfer # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index 3d431812fa..f5c827b5ab 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/mainboard.c b/src/mainboard/sifive/hifive-unleashed/mainboard.c index 96a2678ee0..86231302b6 100644 --- a/src/mainboard/sifive/hifive-unleashed/mainboard.c +++ b/src/mainboard/sifive/hifive-unleashed/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index 9942912730..757b50ac28 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer - * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/memlayout.ld b/src/mainboard/sifive/hifive-unleashed/memlayout.ld index d1a6d65a00..9572a5ef8f 100644 --- a/src/mainboard/sifive/hifive-unleashed/memlayout.ld +++ b/src/mainboard/sifive/hifive-unleashed/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 34c81a2dea..2c757c6aa5 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 3945c090cc..0f531773b9 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc index 301070b084..f4ca029066 100644 --- a/src/mainboard/supermicro/x10slm-f/Makefile.inc +++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl index adaf51a5ec..26a10c57b4 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl +++ b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl index b12aabd04c..3f2ac82c92 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl +++ b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c index a43b499017..54796d54eb 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi_tables.c +++ b/src/mainboard/supermicro/x10slm-f/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm-f/bootblock.c index aeffa69e88..c0d4502664 100644 --- a/src/mainboard/supermicro/x10slm-f/bootblock.c +++ b/src/mainboard/supermicro/x10slm-f/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout index cce1f1844e..74998bd704 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.layout +++ b/src/mainboard/supermicro/x10slm-f/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 434fb59f49..2dd5c5dfe8 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Tristan Corrick ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 57e9a864f5..9b4cb92bfb 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/gpio.c b/src/mainboard/supermicro/x10slm-f/gpio.c index a1668f1d1d..53d15699e1 100644 --- a/src/mainboard/supermicro/x10slm-f/gpio.c +++ b/src/mainboard/supermicro/x10slm-f/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm-f/hda_verb.c index 0944532636..2a293190da 100644 --- a/src/mainboard/supermicro/x10slm-f/hda_verb.c +++ b/src/mainboard/supermicro/x10slm-f/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index 56674b9873..249659492a 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 552ebd2113..9885a3d5e1 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2018 Tristan Corrick * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index cab662a4bf..965e5281d6 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2016 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 75afd2ead1..01a75ca65b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout index 03aea17f8f..90db74e028 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index 8d6dc2e6dd..fa047f8d6b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 750c8561a6..92104e3365 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index 3eeef29257..6c8bde224d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index d27e234ff2..153edfea29 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/acpi/ac.asl b/src/mainboard/system76/lemp9/acpi/ac.asl index 6574c61e41..2355ed5fbc 100644 --- a/src/mainboard/system76/lemp9/acpi/ac.asl +++ b/src/mainboard/system76/lemp9/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/system76/lemp9/acpi/battery.asl b/src/mainboard/system76/lemp9/acpi/battery.asl index c1e6c6ce1d..cf2ce19f4c 100644 --- a/src/mainboard/system76/lemp9/acpi/battery.asl +++ b/src/mainboard/system76/lemp9/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/system76/lemp9/acpi/buttons.asl b/src/mainboard/system76/lemp9/acpi/buttons.asl index 62847b5c09..f8f2910970 100644 --- a/src/mainboard/system76/lemp9/acpi/buttons.asl +++ b/src/mainboard/system76/lemp9/acpi/buttons.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/acpi/ec.asl b/src/mainboard/system76/lemp9/acpi/ec.asl index c26670a009..0e3a68dda5 100644 --- a/src/mainboard/system76/lemp9/acpi/ec.asl +++ b/src/mainboard/system76/lemp9/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/system76/lemp9/acpi/ec_ram.asl b/src/mainboard/system76/lemp9/acpi/ec_ram.asl index 4bb452b6e3..ea57291cf4 100644 --- a/src/mainboard/system76/lemp9/acpi/ec_ram.asl +++ b/src/mainboard/system76/lemp9/acpi/ec_ram.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/system76/lemp9/acpi/gpe.asl b/src/mainboard/system76/lemp9/acpi/gpe.asl index e68c9cd306..99f77f347d 100644 --- a/src/mainboard/system76/lemp9/acpi/gpe.asl +++ b/src/mainboard/system76/lemp9/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/acpi/hid.asl b/src/mainboard/system76/lemp9/acpi/hid.asl index 1f151d5582..f89bc82208 100644 --- a/src/mainboard/system76/lemp9/acpi/hid.asl +++ b/src/mainboard/system76/lemp9/acpi/hid.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/system76/lemp9/acpi/lid.asl b/src/mainboard/system76/lemp9/acpi/lid.asl index 729a0d9090..3d7dddbc20 100644 --- a/src/mainboard/system76/lemp9/acpi/lid.asl +++ b/src/mainboard/system76/lemp9/acpi/lid.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/system76/lemp9/acpi/mainboard.asl b/src/mainboard/system76/lemp9/acpi/mainboard.asl index d065ee166e..1f2b33d2a8 100644 --- a/src/mainboard/system76/lemp9/acpi/mainboard.asl +++ b/src/mainboard/system76/lemp9/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/acpi/s76.asl b/src/mainboard/system76/lemp9/acpi/s76.asl index 145feb0c72..042e7e2431 100644 --- a/src/mainboard/system76/lemp9/acpi/s76.asl +++ b/src/mainboard/system76/lemp9/acpi/s76.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/system76/lemp9/acpi/sleep.asl b/src/mainboard/system76/lemp9/acpi/sleep.asl index 9a3ecaa373..bb01a96a9b 100644 --- a/src/mainboard/system76/lemp9/acpi/sleep.asl +++ b/src/mainboard/system76/lemp9/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/bootblock.c b/src/mainboard/system76/lemp9/bootblock.c index 00c4588f5f..989ea3cc14 100644 --- a/src/mainboard/system76/lemp9/bootblock.c +++ b/src/mainboard/system76/lemp9/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl index 75a98885ed..7e3fdf503b 100644 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ b/src/mainboard/system76/lemp9/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h index 0d8737ad20..f837ea4c72 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/lemp9/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/lemp9/hda_verb.c index 0539e89831..4f8aa2d117 100644 --- a/src/mainboard/system76/lemp9/hda_verb.c +++ b/src/mainboard/system76/lemp9/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/ramstage.c b/src/mainboard/system76/lemp9/ramstage.c index 97d3dff10f..e73a892ef3 100644 --- a/src/mainboard/system76/lemp9/ramstage.c +++ b/src/mainboard/system76/lemp9/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/system76/lemp9/romstage.c b/src/mainboard/system76/lemp9/romstage.c index 6b9b02eb92..e456ffc51f 100644 --- a/src/mainboard/system76/lemp9/romstage.c +++ b/src/mainboard/system76/lemp9/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 System76 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ti/Kconfig b/src/mainboard/ti/Kconfig index 46a3746d65..fa33740600 100644 --- a/src/mainboard/ti/Kconfig +++ b/src/mainboard/ti/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index e4075d0d62..ca0f578a98 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc index 6c137d295d..7e9919e86c 100644 --- a/src/mainboard/ti/beaglebone/Makefile.inc +++ b/src/mainboard/ti/beaglebone/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 25e7434591..ec5fa4e91b 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ti/beaglebone/devicetree.cb b/src/mainboard/ti/beaglebone/devicetree.cb index 681c1e60e1..2bb3851ea6 100644 --- a/src/mainboard/ti/beaglebone/devicetree.cb +++ b/src/mainboard/ti/beaglebone/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c index cbae566e54..27069005bc 100644 --- a/src/mainboard/ti/beaglebone/romstage.c +++ b/src/mainboard/ti/beaglebone/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/up/squared/bootblock.c b/src/mainboard/up/squared/bootblock.c index e35e8b8e7f..3c8d5bd89c 100644 --- a/src/mainboard/up/squared/bootblock.c +++ b/src/mainboard/up/squared/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl index 94dc024b32..f6f274489f 100644 --- a/src/mainboard/up/squared/dsdt.asl +++ b/src/mainboard/up/squared/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index eb3081bc54..52a67ee67c 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Felix Singer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index 9ae30ebb16..dd9bff5294 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Felix Singer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 55235a8d20..12c3006627 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Felix Singer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by From 5f2adfe1a30627b0a416418a0cac59b9104bfbef Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 3 Feb 2020 15:32:54 +0100 Subject: [PATCH 0499/1463] soc/intel/skylake: Control fixed IO decode from devicetree The current implementation doesn't allow custom values for the LPC IO decodes and IO enables. Add the lpc_ioe and lpc_iod values. If they are not zero, they will be used instead of the current handling for COMA and COMB. BUG=N/A TEST=tested on facebook monolith Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38748 Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../common/block/include/intelblocks/lpc_lib.h | 2 ++ src/soc/intel/common/block/lpc/lpc_lib.c | 11 +++++++++++ src/soc/intel/skylake/bootblock/pch.c | 13 ++++++++++--- src/soc/intel/skylake/chip.h | 4 ++++ 4 files changed, 27 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index cf6d8e9bdc..25a7370f83 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -72,6 +72,8 @@ struct lpc_mmio_range { uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables); /* Return the current decode settings */ uint16_t lpc_get_fixed_io_decode(void); +/* Set the current decode ranges */ +uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask); /* Open a generic IO window to the LPC bus. Four windows are available. */ void lpc_open_pmio_window(uint16_t base, uint16_t size); /* Close all generic IO windows to the LPC bus. */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 5b30a8121b..8edbd2ed7c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -42,6 +42,17 @@ uint16_t lpc_get_fixed_io_decode(void) return pci_read_config16(PCH_DEV_LPC, LPC_IO_DECODE); } +uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask) +{ + uint16_t reg_io_ranges; + + reg_io_ranges = lpc_get_fixed_io_decode() & ~mask; + io_ranges |= reg_io_ranges & mask; + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); + + return io_ranges; +} + /* * Find the first unused IO window. * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ... diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index d5d3aedc3d..b9a5633026 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -127,9 +127,16 @@ void pch_early_iorange_init(void) uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66; - /* IO Decode Range */ - if (CONFIG(DRIVERS_UART_8250IO)) - lpc_io_setup_comm_a_b(); + const config_t *config = config_of_soc(); + + if (config->lpc_ioe) { + io_enables = config->lpc_ioe & 0x3f0f; + lpc_set_fixed_io_ranges(config->lpc_iod, 0x1377); + } else { + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + } /* IO Decode Enable */ if (pch_check_decode_enable() == 0) { diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2c3d3a59c8..69b818bab9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -79,6 +79,10 @@ struct soc_intel_skylake_config { uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + /* LPC fixed enables and ranges */ + uint16_t lpc_iod; + uint16_t lpc_ioe; + /* Generic IO decode ranges */ uint32_t gen1_dec; uint32_t gen2_dec; From a808d63cd1ceb04ea1134f6a714fe733d3d0f25b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 23:25:28 +0100 Subject: [PATCH 0500/1463] util/inteltool: Makefile: add src/arch to includes. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add src/arch to includes. Change-Id: I157178a055a259e40c57f3915671d3b8966fbb96 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39525 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/inteltool/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index b15ae8ec54..0a21c07f53 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -26,6 +26,7 @@ CFLAGS ?= -O2 -g -Wall -Wextra -Wmissing-prototypes LDFLAGS += -lpci -lz CPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include +CPPFLAGS += -I$(top)/src/arch/x86/include OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ From a2fe7789e9e4a81f449dea8aa159ac2667396050 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 12:51:24 +0100 Subject: [PATCH 0501/1463] mainboard/google: Remove copyright notices They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- src/mainboard/google/Kconfig | 1 - src/mainboard/google/auron/Makefile.inc | 1 - src/mainboard/google/auron/acpi/ec.asl | 1 - src/mainboard/google/auron/acpi/mainboard.asl | 1 - src/mainboard/google/auron/acpi/superio.asl | 1 - src/mainboard/google/auron/acpi/thermal.asl | 1 - src/mainboard/google/auron/acpi/video.asl | 1 - src/mainboard/google/auron/acpi_tables.c | 1 - src/mainboard/google/auron/chromeos.c | 1 - src/mainboard/google/auron/cmos.layout | 1 - src/mainboard/google/auron/dsdt.asl | 2 -- src/mainboard/google/auron/ec.c | 1 - src/mainboard/google/auron/ec.h | 1 - src/mainboard/google/auron/fadt.c | 2 -- src/mainboard/google/auron/mainboard.c | 2 -- src/mainboard/google/auron/romstage.c | 2 -- src/mainboard/google/auron/smihandler.c | 2 -- src/mainboard/google/auron/variants/auron_paine/gpio.c | 1 - .../variants/auron_paine/include/variant/acpi/mainboard.asl | 1 - .../auron/variants/auron_paine/include/variant/hda_verb.h | 1 - .../auron/variants/auron_paine/include/variant/onboard.h | 1 - .../google/auron/variants/auron_paine/include/variant/spd.h | 1 - .../auron/variants/auron_paine/include/variant/thermal.h | 1 - src/mainboard/google/auron/variants/auron_paine/pei_data.c | 1 - .../google/auron/variants/auron_paine/spd/Makefile.inc | 1 - src/mainboard/google/auron/variants/auron_paine/spd/spd.c | 1 - src/mainboard/google/auron/variants/auron_yuna/gpio.c | 1 - .../variants/auron_yuna/include/variant/acpi/mainboard.asl | 1 - .../auron/variants/auron_yuna/include/variant/hda_verb.h | 1 - .../google/auron/variants/auron_yuna/include/variant/onboard.h | 1 - .../google/auron/variants/auron_yuna/include/variant/spd.h | 1 - .../google/auron/variants/auron_yuna/include/variant/thermal.h | 1 - src/mainboard/google/auron/variants/auron_yuna/pei_data.c | 1 - .../google/auron/variants/auron_yuna/spd/Makefile.inc | 1 - src/mainboard/google/auron/variants/auron_yuna/spd/spd.c | 1 - src/mainboard/google/auron/variants/buddy/gpio.c | 1 - .../auron/variants/buddy/include/variant/acpi/mainboard.asl | 1 - .../google/auron/variants/buddy/include/variant/hda_verb.h | 1 - .../google/auron/variants/buddy/include/variant/onboard.h | 1 - .../google/auron/variants/buddy/include/variant/spd.h | 1 - .../google/auron/variants/buddy/include/variant/thermal.h | 1 - src/mainboard/google/auron/variants/buddy/pei_data.c | 1 - src/mainboard/google/auron/variants/buddy/spd/Makefile.inc | 1 - src/mainboard/google/auron/variants/buddy/spd/spd.c | 1 - src/mainboard/google/auron/variants/gandof/gpio.c | 1 - .../auron/variants/gandof/include/variant/acpi/mainboard.asl | 1 - .../google/auron/variants/gandof/include/variant/hda_verb.h | 1 - .../google/auron/variants/gandof/include/variant/onboard.h | 1 - .../google/auron/variants/gandof/include/variant/spd.h | 1 - .../google/auron/variants/gandof/include/variant/thermal.h | 1 - src/mainboard/google/auron/variants/gandof/pei_data.c | 1 - src/mainboard/google/auron/variants/gandof/spd/Makefile.inc | 1 - src/mainboard/google/auron/variants/gandof/spd/spd.c | 1 - src/mainboard/google/auron/variants/lulu/gpio.c | 2 -- .../auron/variants/lulu/include/variant/acpi/mainboard.asl | 1 - .../google/auron/variants/lulu/include/variant/hda_verb.h | 1 - .../google/auron/variants/lulu/include/variant/onboard.h | 1 - src/mainboard/google/auron/variants/lulu/include/variant/spd.h | 2 -- .../google/auron/variants/lulu/include/variant/thermal.h | 1 - src/mainboard/google/auron/variants/lulu/pei_data.c | 1 - src/mainboard/google/auron/variants/lulu/spd/Makefile.inc | 2 -- src/mainboard/google/auron/variants/lulu/spd/spd.c | 2 -- src/mainboard/google/auron/variants/samus/board_version.c | 1 - src/mainboard/google/auron/variants/samus/gpio.c | 1 - .../auron/variants/samus/include/variant/acpi/mainboard.asl | 1 - .../auron/variants/samus/include/variant/board_version.h | 1 - .../google/auron/variants/samus/include/variant/onboard.h | 1 - .../google/auron/variants/samus/include/variant/spd.h | 1 - .../google/auron/variants/samus/include/variant/thermal.h | 1 - src/mainboard/google/auron/variants/samus/pei_data.c | 1 - src/mainboard/google/auron/variants/samus/spd/Makefile.inc | 1 - src/mainboard/google/auron/variants/samus/spd/spd.c | 1 - src/mainboard/google/beltino/Makefile.inc | 1 - src/mainboard/google/beltino/acpi/mainboard.asl | 1 - src/mainboard/google/beltino/acpi/platform.asl | 2 -- src/mainboard/google/beltino/acpi/superio.asl | 1 - src/mainboard/google/beltino/acpi/thermal.asl | 1 - src/mainboard/google/beltino/acpi/usb.asl | 1 - src/mainboard/google/beltino/acpi_tables.c | 1 - src/mainboard/google/beltino/chromeos.c | 1 - src/mainboard/google/beltino/cmos.layout | 1 - src/mainboard/google/beltino/dsdt.asl | 2 -- src/mainboard/google/beltino/lan.c | 1 - src/mainboard/google/beltino/mainboard.c | 2 -- src/mainboard/google/beltino/romstage.c | 2 -- src/mainboard/google/beltino/smihandler.c | 2 -- src/mainboard/google/beltino/variants/mccloud/hda_verb.c | 1 - .../google/beltino/variants/mccloud/include/variant/gpio.h | 1 - .../google/beltino/variants/mccloud/include/variant/thermal.h | 1 - src/mainboard/google/beltino/variants/mccloud/led.c | 1 - src/mainboard/google/beltino/variants/monroe/hda_verb.c | 1 - .../google/beltino/variants/monroe/include/variant/gpio.h | 1 - .../google/beltino/variants/monroe/include/variant/thermal.h | 1 - src/mainboard/google/beltino/variants/monroe/led.c | 1 - src/mainboard/google/beltino/variants/panther/hda_verb.c | 1 - .../google/beltino/variants/panther/include/variant/gpio.h | 1 - .../google/beltino/variants/panther/include/variant/thermal.h | 1 - src/mainboard/google/beltino/variants/panther/led.c | 1 - src/mainboard/google/beltino/variants/tricky/hda_verb.c | 1 - .../google/beltino/variants/tricky/include/variant/gpio.h | 1 - .../google/beltino/variants/tricky/include/variant/thermal.h | 1 - src/mainboard/google/beltino/variants/tricky/led.c | 1 - src/mainboard/google/beltino/variants/zako/hda_verb.c | 1 - .../google/beltino/variants/zako/include/variant/gpio.h | 1 - .../google/beltino/variants/zako/include/variant/thermal.h | 1 - src/mainboard/google/beltino/variants/zako/led.c | 1 - src/mainboard/google/butterfly/Makefile.inc | 1 - src/mainboard/google/butterfly/acpi/ec.asl | 1 - src/mainboard/google/butterfly/acpi/mainboard.asl | 1 - src/mainboard/google/butterfly/acpi/platform.asl | 1 - src/mainboard/google/butterfly/acpi/superio.asl | 1 - src/mainboard/google/butterfly/acpi/thermal.asl | 1 - src/mainboard/google/butterfly/acpi_tables.c | 1 - src/mainboard/google/butterfly/chromeos.c | 1 - src/mainboard/google/butterfly/cmos.layout | 1 - src/mainboard/google/butterfly/dsdt.asl | 2 -- src/mainboard/google/butterfly/early_init.c | 2 -- src/mainboard/google/butterfly/ec.c | 1 - src/mainboard/google/butterfly/ec.h | 1 - src/mainboard/google/butterfly/gpio.c | 1 - src/mainboard/google/butterfly/hda_verb.c | 1 - src/mainboard/google/butterfly/mainboard.c | 2 -- src/mainboard/google/butterfly/mainboard_smi.c | 1 - src/mainboard/google/butterfly/onboard.h | 1 - src/mainboard/google/butterfly/thermal.h | 1 - src/mainboard/google/cheza/Makefile.inc | 1 - src/mainboard/google/cheza/board.h | 1 - src/mainboard/google/cheza/boardid.c | 1 - src/mainboard/google/cheza/bootblock.c | 1 - src/mainboard/google/cheza/chromeos.c | 1 - src/mainboard/google/cheza/chromeos.fmd | 1 - src/mainboard/google/cheza/devicetree.cb | 1 - src/mainboard/google/cheza/mainboard.c | 1 - src/mainboard/google/cheza/memlayout.ld | 1 - src/mainboard/google/cheza/reset.c | 1 - src/mainboard/google/cheza/romstage.c | 1 - src/mainboard/google/cyan/Makefile.inc | 2 -- src/mainboard/google/cyan/acpi/codec_maxim.asl | 2 -- src/mainboard/google/cyan/acpi/codec_realtek.asl | 2 -- src/mainboard/google/cyan/acpi/dptf.asl | 3 --- src/mainboard/google/cyan/acpi/ec.asl | 2 -- src/mainboard/google/cyan/acpi/mainboard.asl | 2 -- src/mainboard/google/cyan/acpi/superio.asl | 2 -- src/mainboard/google/cyan/acpi/touchscreen_elan.asl | 2 -- src/mainboard/google/cyan/acpi/touchscreen_melfas.asl | 2 -- src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl | 2 -- src/mainboard/google/cyan/acpi/trackpad_atmel.asl | 2 -- src/mainboard/google/cyan/acpi/trackpad_elan.asl | 2 -- src/mainboard/google/cyan/acpi_tables.c | 2 -- src/mainboard/google/cyan/chromeos.c | 2 -- src/mainboard/google/cyan/cmos.layout | 2 -- src/mainboard/google/cyan/com_init.c | 2 -- src/mainboard/google/cyan/dsdt.asl | 3 --- src/mainboard/google/cyan/ec.c | 2 -- src/mainboard/google/cyan/ec.h | 2 -- src/mainboard/google/cyan/fadt.c | 2 -- src/mainboard/google/cyan/irqroute.c | 2 -- src/mainboard/google/cyan/irqroute.h | 2 -- src/mainboard/google/cyan/mainboard.c | 3 --- src/mainboard/google/cyan/romstage.c | 2 -- src/mainboard/google/cyan/smihandler.c | 2 -- src/mainboard/google/cyan/spd/spd.c | 2 -- src/mainboard/google/cyan/spd/spd_util.h | 1 - src/mainboard/google/cyan/variants/banon/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/banon/gpio.c | 2 -- .../google/cyan/variants/banon/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/banon/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/banon/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/banon/romstage.c | 2 -- src/mainboard/google/cyan/variants/banon/spd_util.c | 3 --- .../cyan/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/cyan/variants/celes/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/celes/gpio.c | 2 -- .../google/cyan/variants/celes/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/celes/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/celes/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/celes/ramstage.c | 1 - src/mainboard/google/cyan/variants/celes/spd_util.c | 3 --- src/mainboard/google/cyan/variants/cyan/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/cyan/gpio.c | 2 -- .../google/cyan/variants/cyan/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/cyan/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/cyan/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/cyan/spd_util.c | 3 --- src/mainboard/google/cyan/variants/edgar/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/edgar/gpio.c | 2 -- .../google/cyan/variants/edgar/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/edgar/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/edgar/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/edgar/romstage.c | 2 -- src/mainboard/google/cyan/variants/edgar/spd_util.c | 3 --- src/mainboard/google/cyan/variants/kefka/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/kefka/gpio.c | 2 -- .../google/cyan/variants/kefka/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/kefka/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/kefka/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/kefka/ramstage.c | 1 - src/mainboard/google/cyan/variants/kefka/romstage.c | 2 -- src/mainboard/google/cyan/variants/kefka/spd_util.c | 3 --- src/mainboard/google/cyan/variants/reks/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/reks/gpio.c | 2 -- .../google/cyan/variants/reks/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/reks/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/reks/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/reks/ramstage.c | 1 - src/mainboard/google/cyan/variants/reks/romstage.c | 2 -- src/mainboard/google/cyan/variants/reks/spd_util.c | 3 --- src/mainboard/google/cyan/variants/relm/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/relm/gpio.c | 2 -- .../google/cyan/variants/relm/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/relm/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/relm/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/relm/ramstage.c | 1 - src/mainboard/google/cyan/variants/relm/romstage.c | 2 -- src/mainboard/google/cyan/variants/relm/spd_util.c | 3 --- src/mainboard/google/cyan/variants/setzer/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/setzer/gpio.c | 2 -- .../google/cyan/variants/setzer/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/setzer/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/setzer/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/setzer/ramstage.c | 1 - src/mainboard/google/cyan/variants/setzer/romstage.c | 2 -- src/mainboard/google/cyan/variants/setzer/spd_util.c | 3 --- src/mainboard/google/cyan/variants/terra/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/terra/gpio.c | 2 -- .../cyan/variants/terra/include/variant/acpi/charger.asl | 2 -- .../google/cyan/variants/terra/include/variant/acpi/cpu.asl | 1 - .../google/cyan/variants/terra/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/terra/include/variant/acpi/mainboard.asl | 1 - .../cyan/variants/terra/include/variant/acpi/thermal.asl | 2 -- .../google/cyan/variants/terra/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/terra/ramstage.c | 1 - src/mainboard/google/cyan/variants/terra/romstage.c | 2 -- src/mainboard/google/cyan/variants/terra/spd_util.c | 3 --- src/mainboard/google/cyan/variants/ultima/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/ultima/gpio.c | 2 -- .../google/cyan/variants/ultima/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/ultima/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/ultima/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/ultima/ramstage.c | 1 - src/mainboard/google/cyan/variants/ultima/spd_util.c | 3 --- src/mainboard/google/cyan/variants/wizpig/Makefile.inc | 2 -- src/mainboard/google/cyan/variants/wizpig/gpio.c | 2 -- .../google/cyan/variants/wizpig/include/variant/acpi/dptf.asl | 2 -- .../cyan/variants/wizpig/include/variant/acpi/mainboard.asl | 1 - .../google/cyan/variants/wizpig/include/variant/onboard.h | 2 -- src/mainboard/google/cyan/variants/wizpig/spd_util.c | 3 --- src/mainboard/google/cyan/w25q64.c | 2 -- src/mainboard/google/daisy/Kconfig | 1 - src/mainboard/google/daisy/Makefile.inc | 1 - src/mainboard/google/daisy/chromeos.c | 1 - src/mainboard/google/daisy/devicetree.cb | 1 - src/mainboard/google/daisy/exynos5250.h | 1 - src/mainboard/google/daisy/mainboard.c | 1 - src/mainboard/google/daisy/memory.c | 2 -- src/mainboard/google/daisy/romstage.c | 1 - src/mainboard/google/daisy/wakeup.c | 1 - src/mainboard/google/dedede/board_info.c | 1 - src/mainboard/google/dedede/bootblock.c | 1 - src/mainboard/google/dedede/chromeos.c | 1 - src/mainboard/google/dedede/dsdt.asl | 1 - src/mainboard/google/dedede/ec.c | 1 - src/mainboard/google/dedede/mainboard.c | 1 - src/mainboard/google/dedede/romstage.c | 1 - src/mainboard/google/dedede/smihandler.c | 1 - src/mainboard/google/dedede/spd/Makefile.inc | 1 - src/mainboard/google/dedede/variants/baseboard/gpio.c | 1 - .../google/dedede/variants/baseboard/include/baseboard/ec.h | 1 - .../google/dedede/variants/baseboard/include/baseboard/gpio.h | 1 - .../dedede/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/dedede/variants/baseboard/memory.c | 1 - .../google/dedede/variants/dedede/include/variant/ec.h | 1 - .../google/dedede/variants/dedede/include/variant/gpio.h | 1 - src/mainboard/google/dedede/variants/waddledee/Makefile.inc | 1 - .../google/dedede/variants/waddledee/include/variant/ec.h | 1 - .../google/dedede/variants/waddledee/include/variant/gpio.h | 1 - src/mainboard/google/dedede/variants/waddledoo/Makefile.inc | 1 - .../google/dedede/variants/waddledoo/include/variant/ec.h | 1 - .../google/dedede/variants/waddledoo/include/variant/gpio.h | 1 - src/mainboard/google/dragonegg/Makefile.inc | 1 - src/mainboard/google/dragonegg/bootblock.c | 1 - src/mainboard/google/dragonegg/chromeos.c | 1 - src/mainboard/google/dragonegg/dsdt.asl | 1 - src/mainboard/google/dragonegg/ec.c | 1 - src/mainboard/google/dragonegg/mainboard.c | 1 - src/mainboard/google/dragonegg/romstage_fsp_params.c | 1 - src/mainboard/google/dragonegg/smihandler.c | 1 - src/mainboard/google/dragonegg/spd/Makefile.inc | 1 - src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc | 1 - src/mainboard/google/dragonegg/variants/baseboard/gpio.c | 1 - .../google/dragonegg/variants/baseboard/include/baseboard/ec.h | 1 - .../dragonegg/variants/baseboard/include/baseboard/gpio.h | 1 - .../dragonegg/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/dragonegg/variants/baseboard/memory.c | 1 - .../google/dragonegg/variants/dragonegg/include/variant/ec.h | 1 - .../google/dragonegg/variants/dragonegg/include/variant/gpio.h | 1 - src/mainboard/google/drallion/Makefile.inc | 1 - src/mainboard/google/drallion/bootblock.c | 1 - src/mainboard/google/drallion/chromeos.c | 1 - src/mainboard/google/drallion/dsdt.asl | 1 - src/mainboard/google/drallion/ec.c | 1 - src/mainboard/google/drallion/hda_verb.c | 1 - src/mainboard/google/drallion/ramstage.c | 1 - src/mainboard/google/drallion/romstage.c | 1 - src/mainboard/google/drallion/smihandler.c | 1 - src/mainboard/google/drallion/spd/Makefile.inc | 1 - .../drallion/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/drallion/variants/drallion/Makefile.inc | 1 - src/mainboard/google/drallion/variants/drallion/gpio.c | 1 - .../drallion/variants/drallion/include/variant/acpi/dptf.asl | 1 - .../variants/drallion/include/variant/acpi/mainboard.asl | 1 - .../google/drallion/variants/drallion/include/variant/ec.h | 1 - .../google/drallion/variants/drallion/include/variant/gpio.h | 1 - .../drallion/variants/drallion/include/variant/hda_verb.h | 1 - .../drallion/variants/drallion/include/variant/variant.h | 1 - src/mainboard/google/drallion/variants/drallion/memory.c | 1 - src/mainboard/google/drallion/variants/drallion/sku.c | 1 - src/mainboard/google/drallion/variants/drallion/smbios.c | 1 - src/mainboard/google/eve/Makefile.inc | 1 - src/mainboard/google/eve/acpi/dptf.asl | 2 -- src/mainboard/google/eve/bootblock.c | 2 -- src/mainboard/google/eve/chromeos.c | 2 -- src/mainboard/google/eve/dsdt.asl | 1 - src/mainboard/google/eve/ec.c | 2 -- src/mainboard/google/eve/ec.h | 2 -- src/mainboard/google/eve/gpio.h | 1 - src/mainboard/google/eve/mainboard.c | 2 -- src/mainboard/google/eve/romstage.c | 2 -- src/mainboard/google/eve/smihandler.c | 1 - src/mainboard/google/eve/spd/Makefile.inc | 2 -- src/mainboard/google/eve/spd/spd.c | 2 -- src/mainboard/google/eve/spd/spd.h | 2 -- src/mainboard/google/fizz/Makefile.inc | 1 - src/mainboard/google/fizz/acpi/usb.asl | 1 - src/mainboard/google/fizz/bootblock.c | 1 - src/mainboard/google/fizz/chromeos.c | 1 - src/mainboard/google/fizz/dsdt.asl | 1 - src/mainboard/google/fizz/ec.c | 1 - src/mainboard/google/fizz/mainboard.c | 1 - src/mainboard/google/fizz/romstage.c | 1 - src/mainboard/google/fizz/smihandler.c | 1 - src/mainboard/google/fizz/variants/baseboard/gpio.c | 1 - .../fizz/variants/baseboard/include/baseboard/acpi/dptf.asl | 2 -- .../google/fizz/variants/baseboard/include/baseboard/ec.h | 1 - .../google/fizz/variants/baseboard/include/baseboard/gpio.h | 1 - .../fizz/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/fizz/variants/baseboard/nhlt.c | 1 - src/mainboard/google/fizz/variants/endeavour/gpio.c | 1 - .../fizz/variants/endeavour/include/variant/acpi/dptf.asl | 1 - .../google/fizz/variants/endeavour/include/variant/ec.h | 1 - .../google/fizz/variants/endeavour/include/variant/gpio.h | 1 - src/mainboard/google/fizz/variants/endeavour/nhlt.c | 1 - .../google/fizz/variants/fizz/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/fizz/variants/fizz/include/variant/ec.h | 1 - src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h | 1 - src/mainboard/google/fizz/variants/karma/gpio.c | 1 - .../google/fizz/variants/karma/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/fizz/variants/karma/include/variant/ec.h | 1 - .../google/fizz/variants/karma/include/variant/gpio.h | 1 - src/mainboard/google/fizz/variants/karma/nhlt.c | 1 - src/mainboard/google/fizz/variants/karma/smihandler.c | 1 - src/mainboard/google/foster/Kconfig | 1 - src/mainboard/google/foster/Makefile.inc | 2 -- src/mainboard/google/foster/bct/Makefile.inc | 2 -- src/mainboard/google/foster/bct/cfg2inc.sh | 1 - src/mainboard/google/foster/bct/emmc.cfg | 1 - src/mainboard/google/foster/bct/spi.cfg | 1 - src/mainboard/google/foster/boardid.c | 2 -- src/mainboard/google/foster/bootblock.c | 2 -- src/mainboard/google/foster/chromeos.c | 2 -- src/mainboard/google/foster/devicetree.cb | 1 - src/mainboard/google/foster/mainboard.c | 2 -- src/mainboard/google/foster/pmic.c | 2 -- src/mainboard/google/foster/pmic.h | 2 -- src/mainboard/google/foster/reset.c | 2 -- src/mainboard/google/foster/romstage.c | 2 -- src/mainboard/google/foster/sdram_configs.c | 2 -- src/mainboard/google/gale/Kconfig | 1 - src/mainboard/google/gale/Makefile.inc | 1 - src/mainboard/google/gale/blsp.c | 1 - src/mainboard/google/gale/boardid.c | 1 - src/mainboard/google/gale/bootblock.c | 2 +- src/mainboard/google/gale/cdp.c | 1 - src/mainboard/google/gale/chromeos.c | 1 - src/mainboard/google/gale/devicetree.cb | 1 - src/mainboard/google/gale/mainboard.c | 2 -- src/mainboard/google/gale/mmu.c | 2 +- src/mainboard/google/gale/mmu.h | 2 +- src/mainboard/google/gale/reset.c | 2 -- src/mainboard/google/gale/romstage.c | 2 -- src/mainboard/google/gale/verstage.c | 1 - src/mainboard/google/glados/Makefile.inc | 1 - src/mainboard/google/glados/acpi/dptf.asl | 2 -- src/mainboard/google/glados/acpi/ec.asl | 1 - src/mainboard/google/glados/acpi/mainboard.asl | 1 - src/mainboard/google/glados/acpi/superio.asl | 1 - src/mainboard/google/glados/bootblock_mainboard.c | 1 - src/mainboard/google/glados/chromeos.c | 2 -- src/mainboard/google/glados/cmos.layout | 2 -- src/mainboard/google/glados/dsdt.asl | 3 --- src/mainboard/google/glados/ec.c | 2 -- src/mainboard/google/glados/ec.h | 2 -- src/mainboard/google/glados/mainboard.c | 3 --- src/mainboard/google/glados/romstage.c | 3 --- src/mainboard/google/glados/smihandler.c | 2 -- src/mainboard/google/glados/spd/spd.c | 2 -- src/mainboard/google/glados/spd/spd.h | 2 -- src/mainboard/google/glados/variants/asuka/Makefile.inc | 2 -- .../google/glados/variants/asuka/include/variant/acpi/dptf.asl | 2 -- .../google/glados/variants/asuka/include/variant/gpio.h | 2 -- src/mainboard/google/glados/variants/asuka/variant.c | 2 -- src/mainboard/google/glados/variants/caroline/Makefile.inc | 2 -- .../glados/variants/caroline/include/variant/acpi/dptf.asl | 2 -- .../variants/caroline/include/variant/acpi/mainboard.asl | 1 - .../google/glados/variants/caroline/include/variant/ec.h | 1 - .../google/glados/variants/caroline/include/variant/gpio.h | 1 - src/mainboard/google/glados/variants/caroline/variant.c | 2 -- src/mainboard/google/glados/variants/cave/Makefile.inc | 2 -- .../google/glados/variants/cave/include/variant/acpi/dptf.asl | 2 -- src/mainboard/google/glados/variants/cave/include/variant/ec.h | 1 - .../google/glados/variants/cave/include/variant/gpio.h | 1 - src/mainboard/google/glados/variants/cave/variant.c | 2 -- src/mainboard/google/glados/variants/chell/Makefile.inc | 2 -- .../google/glados/variants/chell/include/variant/acpi/dptf.asl | 2 -- .../google/glados/variants/chell/include/variant/ec.h | 1 - .../google/glados/variants/chell/include/variant/gpio.h | 1 - src/mainboard/google/glados/variants/chell/variant.c | 2 -- src/mainboard/google/glados/variants/glados/Makefile.inc | 2 -- .../glados/variants/glados/include/variant/acpi/dptf.asl | 2 -- .../google/glados/variants/glados/include/variant/ec.h | 1 - .../google/glados/variants/glados/include/variant/gpio.h | 1 - src/mainboard/google/glados/variants/glados/variant.c | 2 -- src/mainboard/google/glados/variants/lars/Makefile.inc | 2 -- .../google/glados/variants/lars/include/variant/acpi/dptf.asl | 2 -- src/mainboard/google/glados/variants/lars/include/variant/ec.h | 1 - .../google/glados/variants/lars/include/variant/gpio.h | 2 -- src/mainboard/google/glados/variants/lars/variant.c | 2 -- src/mainboard/google/glados/variants/sentry/Makefile.inc | 2 -- .../glados/variants/sentry/include/variant/acpi/dptf.asl | 2 -- .../google/glados/variants/sentry/include/variant/ec.h | 1 - .../google/glados/variants/sentry/include/variant/gpio.h | 2 -- src/mainboard/google/glados/variants/sentry/variant.c | 2 -- src/mainboard/google/gru/Kconfig | 1 - src/mainboard/google/gru/Makefile.inc | 1 - src/mainboard/google/gru/board.h | 1 - src/mainboard/google/gru/boardid.c | 1 - src/mainboard/google/gru/bootblock.c | 1 - src/mainboard/google/gru/chromeos.c | 1 - src/mainboard/google/gru/devicetree.cb | 1 - src/mainboard/google/gru/devicetree.scarlet.cb | 1 - src/mainboard/google/gru/mainboard.c | 1 - src/mainboard/google/gru/memlayout.ld | 1 - src/mainboard/google/gru/pwm_regulator.c | 1 - src/mainboard/google/gru/pwm_regulator.h | 1 - src/mainboard/google/gru/reset.c | 1 - src/mainboard/google/gru/romstage.c | 1 - src/mainboard/google/gru/sdram_configs.c | 1 - src/mainboard/google/gru/sdram_params/Makefile.inc | 1 - src/mainboard/google/hatch/Makefile.inc | 1 - src/mainboard/google/hatch/bootblock.c | 1 - src/mainboard/google/hatch/chromeos.c | 1 - src/mainboard/google/hatch/dsdt.asl | 1 - src/mainboard/google/hatch/ec.c | 1 - src/mainboard/google/hatch/mainboard.c | 1 - src/mainboard/google/hatch/ramstage.c | 1 - src/mainboard/google/hatch/romstage_spd_cbfs.c | 1 - src/mainboard/google/hatch/romstage_spd_smbus.c | 1 - src/mainboard/google/hatch/smihandler.c | 1 - src/mainboard/google/hatch/spd/Makefile.inc | 1 - src/mainboard/google/hatch/variants/akemi/Makefile.inc | 1 - src/mainboard/google/hatch/variants/akemi/gpio.c | 1 - .../google/hatch/variants/akemi/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/hatch/variants/akemi/include/variant/ec.h | 1 - .../google/hatch/variants/akemi/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/akemi/variant.c | 1 - src/mainboard/google/hatch/variants/baseboard/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/baseboard/gpio.c | 1 - .../hatch/variants/baseboard/include/baseboard/acpi/dptf.asl | 1 - .../google/hatch/variants/baseboard/include/baseboard/ec.h | 1 - .../google/hatch/variants/baseboard/include/baseboard/gpio.h | 1 - .../hatch/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/hatch/variants/baseboard/memory.c | 1 - src/mainboard/google/hatch/variants/dratini/Makefile.inc | 1 - src/mainboard/google/hatch/variants/dratini/gpio.c | 1 - .../hatch/variants/dratini/include/variant/acpi/dptf.asl | 1 - .../google/hatch/variants/dratini/include/variant/ec.h | 1 - .../google/hatch/variants/dratini/include/variant/gpio.h | 1 - .../google/hatch/variants/dratini/include/variant/sku.h | 1 - src/mainboard/google/hatch/variants/dratini/ramstage.c | 1 - src/mainboard/google/hatch/variants/dratini/variant.c | 1 - src/mainboard/google/hatch/variants/hatch/Makefile.inc | 1 - src/mainboard/google/hatch/variants/hatch/gpio.c | 1 - .../google/hatch/variants/hatch/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/hatch/variants/hatch/include/variant/ec.h | 1 - .../google/hatch/variants/hatch/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/hatch/ramstage.c | 1 - src/mainboard/google/hatch/variants/helios/Makefile.inc | 1 - src/mainboard/google/hatch/variants/helios/gpio.c | 1 - .../google/hatch/variants/helios/include/variant/acpi/dptf.asl | 1 - .../google/hatch/variants/helios/include/variant/ec.h | 1 - .../google/hatch/variants/helios/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/helios/memory.c | 1 - src/mainboard/google/hatch/variants/helios/ramstage.c | 1 - src/mainboard/google/hatch/variants/jinlon/Makefile.inc | 1 - src/mainboard/google/hatch/variants/jinlon/gpio.c | 1 - .../google/hatch/variants/jinlon/include/variant/acpi/dptf.asl | 1 - .../google/hatch/variants/jinlon/include/variant/ec.h | 1 - .../google/hatch/variants/jinlon/include/variant/gpio.h | 1 - .../google/hatch/variants/jinlon/include/variant/sku.h | 1 - src/mainboard/google/hatch/variants/jinlon/mainboard.c | 1 - src/mainboard/google/hatch/variants/jinlon/ramstage.c | 1 - src/mainboard/google/hatch/variants/kindred/Makefile.inc | 1 - src/mainboard/google/hatch/variants/kindred/gpio.c | 1 - .../hatch/variants/kindred/include/variant/acpi/dptf.asl | 1 - .../google/hatch/variants/kindred/include/variant/ec.h | 1 - .../google/hatch/variants/kindred/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/kindred/variant.c | 1 - src/mainboard/google/hatch/variants/kohaku/Makefile.inc | 1 - src/mainboard/google/hatch/variants/kohaku/gpio.c | 1 - .../google/hatch/variants/kohaku/include/variant/acpi/dptf.asl | 1 - .../google/hatch/variants/kohaku/include/variant/ec.h | 1 - .../google/hatch/variants/kohaku/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/kohaku/memory.c | 1 - src/mainboard/google/hatch/variants/kohaku/ramstage.c | 1 - src/mainboard/google/hatch/variants/mushu/Makefile.inc | 1 - src/mainboard/google/hatch/variants/mushu/gpio.c | 1 - .../google/hatch/variants/mushu/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/hatch/variants/mushu/include/variant/ec.h | 1 - .../google/hatch/variants/mushu/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/mushu/ramstage.c | 1 - src/mainboard/google/hatch/variants/nightfury/Makefile.inc | 1 - src/mainboard/google/hatch/variants/nightfury/gpio.c | 1 - .../hatch/variants/nightfury/include/variant/acpi/dptf.asl | 1 - .../google/hatch/variants/nightfury/include/variant/ec.h | 1 - .../google/hatch/variants/nightfury/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/nightfury/memory.c | 1 - src/mainboard/google/hatch/variants/nightfury/ramstage.c | 1 - src/mainboard/google/hatch/variants/palkia/Makefile.inc | 1 - src/mainboard/google/hatch/variants/palkia/gpio.c | 1 - .../google/hatch/variants/palkia/include/variant/acpi/dptf.asl | 1 - .../google/hatch/variants/palkia/include/variant/ec.h | 1 - .../google/hatch/variants/palkia/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/palkia/memory.c | 1 - src/mainboard/google/hatch/variants/puff/Makefile.inc | 1 - src/mainboard/google/hatch/variants/puff/gpio.c | 1 - src/mainboard/google/hatch/variants/puff/include/variant/ec.h | 2 -- .../google/hatch/variants/puff/include/variant/gpio.h | 1 - src/mainboard/google/hatch/variants/puff/mainboard.c | 1 - src/mainboard/google/hatch/variants/stryke/gpio.c | 1 - src/mainboard/google/jecht/Makefile.inc | 1 - src/mainboard/google/jecht/acpi/mainboard.asl | 1 - src/mainboard/google/jecht/acpi/platform.asl | 2 -- src/mainboard/google/jecht/acpi/superio.asl | 1 - src/mainboard/google/jecht/acpi_tables.c | 1 - src/mainboard/google/jecht/bootblock.c | 2 -- src/mainboard/google/jecht/chromeos.c | 1 - src/mainboard/google/jecht/cmos.layout | 1 - src/mainboard/google/jecht/dsdt.asl | 2 -- src/mainboard/google/jecht/fadt.c | 2 -- src/mainboard/google/jecht/hda_verb.c | 1 - src/mainboard/google/jecht/lan.c | 1 - src/mainboard/google/jecht/led.c | 1 - src/mainboard/google/jecht/mainboard.c | 2 -- src/mainboard/google/jecht/onboard.h | 1 - src/mainboard/google/jecht/romstage.c | 2 -- src/mainboard/google/jecht/smihandler.c | 2 -- src/mainboard/google/jecht/spd/Makefile.inc | 1 - src/mainboard/google/jecht/spd/spd.c | 1 - src/mainboard/google/jecht/spd/spd.h | 1 - src/mainboard/google/jecht/variants/guado/gpio.c | 1 - .../jecht/variants/guado/include/variant/acpi/thermal.asl | 1 - .../google/jecht/variants/guado/include/variant/thermal.h | 1 - src/mainboard/google/jecht/variants/guado/pei_data.c | 1 - src/mainboard/google/jecht/variants/jecht/gpio.c | 1 - .../jecht/variants/jecht/include/variant/acpi/thermal.asl | 1 - .../google/jecht/variants/jecht/include/variant/thermal.h | 1 - src/mainboard/google/jecht/variants/jecht/pei_data.c | 1 - src/mainboard/google/jecht/variants/rikku/gpio.c | 1 - .../jecht/variants/rikku/include/variant/acpi/thermal.asl | 1 - .../google/jecht/variants/rikku/include/variant/thermal.h | 1 - src/mainboard/google/jecht/variants/rikku/pei_data.c | 1 - src/mainboard/google/jecht/variants/tidus/gpio.c | 1 - .../jecht/variants/tidus/include/variant/acpi/thermal.asl | 1 - .../google/jecht/variants/tidus/include/variant/thermal.h | 1 - src/mainboard/google/jecht/variants/tidus/pei_data.c | 1 - src/mainboard/google/kahlee/BiosCallOuts.c | 1 - src/mainboard/google/kahlee/Kconfig | 1 - src/mainboard/google/kahlee/Makefile.inc | 1 - src/mainboard/google/kahlee/OemCustomize.c | 1 - src/mainboard/google/kahlee/bootblock/bootblock.c | 1 - src/mainboard/google/kahlee/chromeos.c | 3 --- src/mainboard/google/kahlee/dsdt.asl | 1 - src/mainboard/google/kahlee/ec.c | 1 - src/mainboard/google/kahlee/irq_tables.c | 1 - src/mainboard/google/kahlee/mainboard.c | 1 - src/mainboard/google/kahlee/mptable.c | 1 - src/mainboard/google/kahlee/romstage.c | 1 - src/mainboard/google/kahlee/smihandler.c | 2 -- src/mainboard/google/kahlee/variants/aleena/Makefile.inc | 1 - src/mainboard/google/kahlee/variants/aleena/devicetree.cb | 1 - .../google/kahlee/variants/aleena/include/variant/gpio.h | 1 - .../google/kahlee/variants/aleena/include/variant/thermal.h | 2 -- src/mainboard/google/kahlee/variants/baseboard/Makefile.inc | 1 - src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c | 1 - src/mainboard/google/kahlee/variants/baseboard/gpio.c | 1 - .../kahlee/variants/baseboard/include/baseboard/acpi/audio.asl | 1 - .../kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl | 1 - .../variants/baseboard/include/baseboard/acpi/mainboard.asl | 1 - .../variants/baseboard/include/baseboard/acpi/routing.asl | 2 -- .../kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl | 1 - .../variants/baseboard/include/baseboard/acpi/thermal.asl | 1 - .../google/kahlee/variants/baseboard/include/baseboard/ec.h | 1 - .../google/kahlee/variants/baseboard/include/baseboard/gpio.h | 1 - .../kahlee/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/kahlee/variants/baseboard/mainboard.c | 1 - src/mainboard/google/kahlee/variants/baseboard/memory.c | 1 - src/mainboard/google/kahlee/variants/baseboard/romstage.c | 1 - .../google/kahlee/variants/baseboard/spd/Makefile.inc | 2 -- src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c | 1 - src/mainboard/google/kahlee/variants/careena/Makefile.inc | 1 - src/mainboard/google/kahlee/variants/careena/devicetree.cb | 1 - .../google/kahlee/variants/careena/include/variant/gpio.h | 1 - .../google/kahlee/variants/careena/include/variant/thermal.h | 2 -- src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc | 2 -- src/mainboard/google/kahlee/variants/grunt/Makefile.inc | 1 - src/mainboard/google/kahlee/variants/grunt/devicetree.cb | 1 - .../google/kahlee/variants/grunt/include/variant/acpi/gpe.asl | 1 - .../kahlee/variants/grunt/include/variant/acpi/mainboard.asl | 1 - .../kahlee/variants/grunt/include/variant/acpi/routing.asl | 1 - .../kahlee/variants/grunt/include/variant/acpi/sleep.asl | 1 - .../kahlee/variants/grunt/include/variant/acpi/thermal.asl | 1 - .../google/kahlee/variants/grunt/include/variant/gpio.h | 1 - .../google/kahlee/variants/grunt/include/variant/thermal.h | 2 -- src/mainboard/google/kahlee/variants/liara/Makefile.inc | 1 - src/mainboard/google/kahlee/variants/liara/devicetree.cb | 1 - .../google/kahlee/variants/liara/include/variant/gpio.h | 1 - .../google/kahlee/variants/liara/include/variant/thermal.h | 2 -- src/mainboard/google/kahlee/variants/nuwani/Makefile.inc | 1 - src/mainboard/google/kahlee/variants/nuwani/devicetree.cb | 1 - .../google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl | 1 - .../kahlee/variants/nuwani/include/variant/acpi/mainboard.asl | 1 - .../kahlee/variants/nuwani/include/variant/acpi/routing.asl | 1 - .../kahlee/variants/nuwani/include/variant/acpi/sleep.asl | 1 - .../kahlee/variants/nuwani/include/variant/acpi/thermal.asl | 1 - .../google/kahlee/variants/nuwani/include/variant/ec.h | 1 - .../google/kahlee/variants/nuwani/include/variant/gpio.h | 1 - .../google/kahlee/variants/nuwani/include/variant/thermal.h | 2 -- src/mainboard/google/kahlee/variants/nuwani/mainboard.c | 1 - src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc | 2 -- src/mainboard/google/kahlee/variants/treeya/Makefile.inc | 1 - src/mainboard/google/kahlee/variants/treeya/devicetree.cb | 1 - .../google/kahlee/variants/treeya/include/variant/acpi/gpe.asl | 1 - .../kahlee/variants/treeya/include/variant/acpi/mainboard.asl | 1 - .../kahlee/variants/treeya/include/variant/acpi/routing.asl | 1 - .../kahlee/variants/treeya/include/variant/acpi/sleep.asl | 1 - .../kahlee/variants/treeya/include/variant/acpi/thermal.asl | 1 - .../google/kahlee/variants/treeya/include/variant/ec.h | 1 - .../google/kahlee/variants/treeya/include/variant/gpio.h | 1 - .../google/kahlee/variants/treeya/include/variant/thermal.h | 2 -- src/mainboard/google/kahlee/variants/treeya/mainboard.c | 1 - src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc | 2 -- src/mainboard/google/kukui/Kconfig | 1 - src/mainboard/google/kukui/boardid.c | 1 - src/mainboard/google/kukui/bootblock.c | 1 - src/mainboard/google/kukui/chromeos.c | 1 - src/mainboard/google/kukui/devicetree.cb | 1 - src/mainboard/google/kukui/early_init.c | 1 - src/mainboard/google/kukui/early_init.h | 1 - src/mainboard/google/kukui/gpio.h | 1 - src/mainboard/google/kukui/mainboard.c | 1 - src/mainboard/google/kukui/memlayout.ld | 1 - src/mainboard/google/kukui/panel.h | 1 - src/mainboard/google/kukui/panel_anx7625.c | 1 - src/mainboard/google/kukui/panel_flapjack.c | 1 - src/mainboard/google/kukui/panel_kakadu.c | 1 - src/mainboard/google/kukui/panel_kodama.c | 1 - src/mainboard/google/kukui/panel_krane.c | 1 - src/mainboard/google/kukui/panel_kukui.c | 1 - .../google/kukui/panel_params/panel-AUO_B101UAN08_3.c | 1 - .../google/kukui/panel_params/panel-AUO_KD101N80_45NA.c | 1 - src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c | 1 - .../google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c | 1 - .../google/kukui/panel_params/panel-BOE_TV101WUM_N53.c | 1 - .../google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c | 1 - .../google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c | 1 - .../google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c | 1 - .../google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c | 1 - .../google/kukui/panel_params/panel-INX_OTA7290D10P.c | 1 - src/mainboard/google/kukui/panel_ps8640.c | 1 - src/mainboard/google/kukui/reset.c | 1 - src/mainboard/google/kukui/romstage.c | 1 - src/mainboard/google/kukui/sdram_configs.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c | 1 - .../kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c | 1 - src/mainboard/google/kukui/verstage.c | 1 - src/mainboard/google/link/Makefile.inc | 1 - src/mainboard/google/link/acpi/ec.asl | 1 - src/mainboard/google/link/acpi/mainboard.asl | 1 - src/mainboard/google/link/acpi/platform.asl | 1 - src/mainboard/google/link/acpi/superio.asl | 1 - src/mainboard/google/link/acpi/thermal.asl | 1 - src/mainboard/google/link/acpi_tables.c | 1 - src/mainboard/google/link/chromeos.c | 1 - src/mainboard/google/link/cmos.layout | 1 - src/mainboard/google/link/dsdt.asl | 2 -- src/mainboard/google/link/early_init.c | 2 -- src/mainboard/google/link/ec.c | 1 - src/mainboard/google/link/ec.h | 1 - src/mainboard/google/link/gpio.c | 1 - src/mainboard/google/link/hda_verb.c | 1 - src/mainboard/google/link/mainboard.c | 2 -- src/mainboard/google/link/mainboard_smi.c | 1 - src/mainboard/google/link/onboard.h | 1 - src/mainboard/google/link/thermal.h | 1 - src/mainboard/google/mistral/bootblock.c | 1 - src/mainboard/google/mistral/chromeos.c | 1 - src/mainboard/google/mistral/chromeos.fmd | 1 - src/mainboard/google/mistral/devicetree.cb | 1 - src/mainboard/google/mistral/mainboard.c | 1 - src/mainboard/google/mistral/memlayout.ld | 1 - src/mainboard/google/mistral/reset.c | 2 -- src/mainboard/google/mistral/romstage.c | 1 - src/mainboard/google/mistral/verstage.c | 1 - src/mainboard/google/nyan/Kconfig | 1 - src/mainboard/google/nyan/Makefile.inc | 1 - src/mainboard/google/nyan/bct/Makefile.inc | 1 - src/mainboard/google/nyan/bct/cfg2inc.sh | 1 - src/mainboard/google/nyan/bct/emmc.cfg | 1 - src/mainboard/google/nyan/bct/spi.cfg | 1 - src/mainboard/google/nyan/boardid.c | 1 - src/mainboard/google/nyan/bootblock.c | 1 - src/mainboard/google/nyan/chromeos.c | 1 - src/mainboard/google/nyan/devicetree.cb | 1 - src/mainboard/google/nyan/early_configs.c | 1 - src/mainboard/google/nyan/mainboard.c | 1 - src/mainboard/google/nyan/pmic.c | 2 -- src/mainboard/google/nyan/pmic.h | 1 - src/mainboard/google/nyan/reset.c | 1 - src/mainboard/google/nyan/romstage.c | 1 - src/mainboard/google/nyan/sdram_configs.c | 1 - src/mainboard/google/nyan/sdram_configs.h | 1 - src/mainboard/google/nyan_big/Kconfig | 1 - src/mainboard/google/nyan_big/Makefile.inc | 1 - src/mainboard/google/nyan_big/bct/Makefile.inc | 1 - src/mainboard/google/nyan_big/bct/emmc.cfg | 1 - src/mainboard/google/nyan_big/bct/spi.cfg | 1 - src/mainboard/google/nyan_big/boardid.c | 1 - src/mainboard/google/nyan_big/bootblock.c | 1 - src/mainboard/google/nyan_big/chromeos.c | 1 - src/mainboard/google/nyan_big/devicetree.cb | 1 - src/mainboard/google/nyan_big/early_configs.c | 1 - src/mainboard/google/nyan_big/mainboard.c | 1 - src/mainboard/google/nyan_big/pmic.c | 2 -- src/mainboard/google/nyan_big/pmic.h | 1 - src/mainboard/google/nyan_big/reset.c | 1 - src/mainboard/google/nyan_big/romstage.c | 1 - src/mainboard/google/nyan_big/sdram_configs.c | 1 - src/mainboard/google/nyan_big/sdram_configs.h | 1 - src/mainboard/google/nyan_blaze/Kconfig | 1 - src/mainboard/google/nyan_blaze/Makefile.inc | 1 - src/mainboard/google/nyan_blaze/bct/Makefile.inc | 1 - src/mainboard/google/nyan_blaze/bct/emmc.cfg | 1 - src/mainboard/google/nyan_blaze/bct/spi.cfg | 1 - src/mainboard/google/nyan_blaze/boardid.c | 1 - src/mainboard/google/nyan_blaze/bootblock.c | 1 - src/mainboard/google/nyan_blaze/chromeos.c | 1 - src/mainboard/google/nyan_blaze/devicetree.cb | 1 - src/mainboard/google/nyan_blaze/early_configs.c | 1 - src/mainboard/google/nyan_blaze/mainboard.c | 1 - src/mainboard/google/nyan_blaze/pmic.c | 2 -- src/mainboard/google/nyan_blaze/pmic.h | 1 - src/mainboard/google/nyan_blaze/reset.c | 1 - src/mainboard/google/nyan_blaze/romstage.c | 1 - src/mainboard/google/nyan_blaze/sdram_configs.c | 1 - src/mainboard/google/nyan_blaze/sdram_configs.h | 1 - src/mainboard/google/oak/Kconfig | 1 - src/mainboard/google/oak/Makefile.inc | 1 - src/mainboard/google/oak/boardid.c | 1 - src/mainboard/google/oak/bootblock.c | 1 - src/mainboard/google/oak/chromeos.c | 1 - src/mainboard/google/oak/devicetree.cb | 1 - src/mainboard/google/oak/gpio.h | 1 - src/mainboard/google/oak/mainboard.c | 1 - src/mainboard/google/oak/romstage.c | 1 - src/mainboard/google/oak/sdram_configs.c | 1 - src/mainboard/google/oak/tpm_tis.c | 1 - src/mainboard/google/octopus/bootblock.c | 1 - src/mainboard/google/octopus/chromeos.c | 1 - src/mainboard/google/octopus/dsdt.asl | 1 - src/mainboard/google/octopus/ec.c | 1 - src/mainboard/google/octopus/mainboard.c | 1 - src/mainboard/google/octopus/romstage.c | 1 - src/mainboard/google/octopus/smihandler.c | 1 - src/mainboard/google/octopus/variants/ampton/gpio.c | 1 - .../octopus/variants/ampton/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/ampton/include/variant/ec.h | 1 - .../google/octopus/variants/ampton/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/baseboard/gpio.c | 1 - .../octopus/variants/baseboard/include/baseboard/acpi/dptf.asl | 1 - .../google/octopus/variants/baseboard/include/baseboard/ec.h | 1 - .../google/octopus/variants/baseboard/include/baseboard/gpio.h | 1 - .../octopus/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/octopus/variants/baseboard/memory.c | 1 - src/mainboard/google/octopus/variants/baseboard/nhlt.c | 1 - src/mainboard/google/octopus/variants/bloog/gpio.c | 1 - .../octopus/variants/bloog/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/bloog/include/variant/ec.h | 1 - .../google/octopus/variants/bloog/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/bloog/variant.c | 1 - src/mainboard/google/octopus/variants/bobba/gpio.c | 1 - .../octopus/variants/bobba/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/bobba/include/variant/ec.h | 1 - .../google/octopus/variants/bobba/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/bobba/variant.c | 1 - src/mainboard/google/octopus/variants/casta/gpio.c | 1 - .../octopus/variants/casta/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/casta/include/variant/ec.h | 1 - .../google/octopus/variants/casta/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/casta/variant.c | 1 - src/mainboard/google/octopus/variants/dood/gpio.c | 1 - .../google/octopus/variants/dood/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/dood/include/variant/ec.h | 1 - .../google/octopus/variants/dood/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/dood/variant.c | 1 - src/mainboard/google/octopus/variants/fleex/gpio.c | 1 - .../octopus/variants/fleex/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/fleex/include/variant/ec.h | 1 - .../google/octopus/variants/fleex/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/foob/gpio.c | 1 - .../google/octopus/variants/foob/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/foob/include/variant/ec.h | 1 - .../google/octopus/variants/foob/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/foob/variant.c | 1 - src/mainboard/google/octopus/variants/garg/gpio.c | 1 - .../google/octopus/variants/garg/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/garg/include/variant/ec.h | 1 - .../google/octopus/variants/garg/include/variant/gpio.h | 1 - .../google/octopus/variants/garg/include/variant/sku.h | 1 - src/mainboard/google/octopus/variants/garg/variant.c | 1 - src/mainboard/google/octopus/variants/lick/gpio.c | 1 - .../google/octopus/variants/lick/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/lick/include/variant/ec.h | 1 - .../google/octopus/variants/lick/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/meep/gpio.c | 1 - .../google/octopus/variants/meep/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/meep/include/variant/ec.h | 1 - .../google/octopus/variants/meep/include/variant/gpio.h | 1 - .../google/octopus/variants/meep/include/variant/sku.h | 1 - src/mainboard/google/octopus/variants/meep/variant.c | 1 - .../octopus/variants/octopus/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/octopus/include/variant/ec.h | 1 - .../google/octopus/variants/octopus/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/phaser/gpio.c | 1 - .../octopus/variants/phaser/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/phaser/include/variant/ec.h | 1 - .../google/octopus/variants/phaser/include/variant/gpio.h | 1 - src/mainboard/google/octopus/variants/phaser/mainboard.c | 1 - src/mainboard/google/octopus/variants/phaser/variant.c | 1 - src/mainboard/google/octopus/variants/yorp/gpio.c | 1 - .../google/octopus/variants/yorp/include/variant/acpi/dptf.asl | 1 - .../google/octopus/variants/yorp/include/variant/ec.h | 1 - .../google/octopus/variants/yorp/include/variant/gpio.h | 1 - src/mainboard/google/parrot/Makefile.inc | 1 - src/mainboard/google/parrot/acpi/ec.asl | 1 - src/mainboard/google/parrot/acpi/mainboard.asl | 1 - src/mainboard/google/parrot/acpi/platform.asl | 1 - src/mainboard/google/parrot/acpi/superio.asl | 1 - src/mainboard/google/parrot/acpi/thermal.asl | 1 - src/mainboard/google/parrot/acpi_tables.c | 1 - src/mainboard/google/parrot/chromeos.c | 1 - src/mainboard/google/parrot/cmos.layout | 1 - src/mainboard/google/parrot/dsdt.asl | 2 -- src/mainboard/google/parrot/early_init.c | 2 -- src/mainboard/google/parrot/ec.c | 1 - src/mainboard/google/parrot/ec.h | 1 - src/mainboard/google/parrot/gpio.c | 1 - src/mainboard/google/parrot/hda_verb.c | 1 - src/mainboard/google/parrot/mainboard.c | 2 -- src/mainboard/google/parrot/onboard.h | 1 - src/mainboard/google/parrot/smihandler.c | 1 - src/mainboard/google/parrot/thermal.h | 1 - src/mainboard/google/peach_pit/Kconfig | 1 - src/mainboard/google/peach_pit/Makefile.inc | 1 - src/mainboard/google/peach_pit/chromeos.c | 1 - src/mainboard/google/peach_pit/devicetree.cb | 1 - src/mainboard/google/peach_pit/mainboard.c | 1 - src/mainboard/google/peach_pit/memory.c | 2 -- src/mainboard/google/peach_pit/romstage.c | 1 - src/mainboard/google/peach_pit/wakeup.c | 1 - src/mainboard/google/poppy/Makefile.inc | 1 - src/mainboard/google/poppy/bootblock.c | 1 - src/mainboard/google/poppy/chromeos.c | 1 - src/mainboard/google/poppy/dsdt.asl | 1 - src/mainboard/google/poppy/ec.c | 1 - src/mainboard/google/poppy/mainboard.c | 1 - src/mainboard/google/poppy/ramstage.c | 1 - src/mainboard/google/poppy/romstage.c | 1 - src/mainboard/google/poppy/smihandler.c | 1 - src/mainboard/google/poppy/variants/atlas/gpio.c | 1 - .../google/poppy/variants/atlas/include/variant/acpi/cam0.asl | 1 - .../poppy/variants/atlas/include/variant/acpi/camera.asl | 1 - .../google/poppy/variants/atlas/include/variant/acpi/dptf.asl | 2 -- .../variants/atlas/include/variant/acpi/ipu_endpoints.asl | 1 - .../variants/atlas/include/variant/acpi/ipu_mainboard.asl | 1 - src/mainboard/google/poppy/variants/atlas/include/variant/ec.h | 1 - .../google/poppy/variants/atlas/include/variant/gpio.h | 1 - src/mainboard/google/poppy/variants/atlas/mainboard.c | 2 -- src/mainboard/google/poppy/variants/atlas/memory.c | 1 - src/mainboard/google/poppy/variants/atlas/nhlt.c | 1 - src/mainboard/google/poppy/variants/baseboard/gpio.c | 1 - .../poppy/variants/baseboard/include/baseboard/acpi/cam0.asl | 1 - .../poppy/variants/baseboard/include/baseboard/acpi/cam1.asl | 1 - .../poppy/variants/baseboard/include/baseboard/acpi/camera.asl | 1 - .../variants/baseboard/include/baseboard/acpi/camera_pmic.asl | 1 - .../poppy/variants/baseboard/include/baseboard/acpi/dptf.asl | 2 -- .../baseboard/include/baseboard/acpi/ipu_endpoints.asl | 1 - .../baseboard/include/baseboard/acpi/ipu_mainboard.asl | 1 - .../google/poppy/variants/baseboard/include/baseboard/ec.h | 1 - .../google/poppy/variants/baseboard/include/baseboard/gpio.h | 1 - .../poppy/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/poppy/variants/baseboard/memory.c | 1 - src/mainboard/google/poppy/variants/baseboard/nhlt.c | 1 - src/mainboard/google/poppy/variants/nami/gpio.c | 1 - .../google/poppy/variants/nami/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/poppy/variants/nami/include/variant/ec.h | 1 - .../google/poppy/variants/nami/include/variant/gpio.h | 1 - src/mainboard/google/poppy/variants/nami/include/variant/sku.h | 1 - src/mainboard/google/poppy/variants/nami/mainboard.c | 1 - src/mainboard/google/poppy/variants/nami/memory.c | 1 - src/mainboard/google/poppy/variants/nami/nhlt.c | 1 - src/mainboard/google/poppy/variants/nami/smihandler.c | 1 - src/mainboard/google/poppy/variants/nautilus/gpio.c | 1 - .../poppy/variants/nautilus/include/variant/acpi/cam0.asl | 1 - .../poppy/variants/nautilus/include/variant/acpi/camera.asl | 1 - .../poppy/variants/nautilus/include/variant/acpi/dptf.asl | 2 -- .../variants/nautilus/include/variant/acpi/ipu_endpoints.asl | 1 - .../variants/nautilus/include/variant/acpi/ipu_mainboard.asl | 1 - .../google/poppy/variants/nautilus/include/variant/ec.h | 1 - .../google/poppy/variants/nautilus/include/variant/gpio.h | 1 - .../google/poppy/variants/nautilus/include/variant/sku.h | 1 - src/mainboard/google/poppy/variants/nautilus/mainboard.c | 1 - src/mainboard/google/poppy/variants/nautilus/memory.c | 1 - src/mainboard/google/poppy/variants/nautilus/nhlt.c | 1 - src/mainboard/google/poppy/variants/nautilus/sku.c | 1 - src/mainboard/google/poppy/variants/nautilus/smihandler.c | 1 - src/mainboard/google/poppy/variants/nocturne/ec.c | 1 - src/mainboard/google/poppy/variants/nocturne/gpio.c | 1 - .../poppy/variants/nocturne/include/variant/acpi/cam0.asl | 1 - .../poppy/variants/nocturne/include/variant/acpi/cam1.asl | 1 - .../poppy/variants/nocturne/include/variant/acpi/camera.asl | 1 - .../poppy/variants/nocturne/include/variant/acpi/dptf.asl | 2 -- .../variants/nocturne/include/variant/acpi/ipu_endpoints.asl | 1 - .../variants/nocturne/include/variant/acpi/ipu_mainboard.asl | 1 - .../google/poppy/variants/nocturne/include/variant/ec.h | 1 - .../google/poppy/variants/nocturne/include/variant/gpio.h | 1 - src/mainboard/google/poppy/variants/nocturne/mainboard.c | 2 -- src/mainboard/google/poppy/variants/nocturne/memory.c | 1 - src/mainboard/google/poppy/variants/nocturne/nhlt.c | 1 - .../poppy/variants/poppy/include/variant/acpi/camera.asl | 1 - .../google/poppy/variants/poppy/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/poppy/variants/poppy/include/variant/ec.h | 1 - .../google/poppy/variants/poppy/include/variant/gpio.h | 1 - src/mainboard/google/poppy/variants/rammus/gpio.c | 1 - .../google/poppy/variants/rammus/include/variant/acpi/dptf.asl | 1 - .../google/poppy/variants/rammus/include/variant/ec.h | 1 - .../google/poppy/variants/rammus/include/variant/gpio.h | 1 - src/mainboard/google/poppy/variants/rammus/mainboard.c | 1 - src/mainboard/google/poppy/variants/rammus/memory.c | 1 - src/mainboard/google/poppy/variants/rammus/nhlt.c | 1 - src/mainboard/google/poppy/variants/soraka/gpio.c | 1 - .../poppy/variants/soraka/include/variant/acpi/camera.asl | 1 - .../google/poppy/variants/soraka/include/variant/acpi/dptf.asl | 2 -- .../google/poppy/variants/soraka/include/variant/ec.h | 1 - .../google/poppy/variants/soraka/include/variant/gpio.h | 1 - src/mainboard/google/rambi/Makefile.inc | 1 - src/mainboard/google/rambi/acpi/ec.asl | 1 - src/mainboard/google/rambi/acpi/mainboard.asl | 1 - src/mainboard/google/rambi/acpi/superio.asl | 1 - src/mainboard/google/rambi/acpi_tables.c | 1 - src/mainboard/google/rambi/chromeos.c | 1 - src/mainboard/google/rambi/cmos.layout | 1 - src/mainboard/google/rambi/dsdt.asl | 2 -- src/mainboard/google/rambi/ec.c | 1 - src/mainboard/google/rambi/ec.h | 1 - src/mainboard/google/rambi/fadt.c | 1 - src/mainboard/google/rambi/irqroute.c | 1 - src/mainboard/google/rambi/irqroute.h | 1 - src/mainboard/google/rambi/mainboard.c | 2 -- src/mainboard/google/rambi/mainboard_smi.c | 1 - src/mainboard/google/rambi/romstage.c | 1 - src/mainboard/google/rambi/variants/banjo/Makefile.inc | 1 - src/mainboard/google/rambi/variants/banjo/gpio.c | 1 - .../rambi/variants/banjo/include/variant/acpi/mainboard.asl | 1 - .../google/rambi/variants/banjo/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/candy/Makefile.inc | 1 - src/mainboard/google/rambi/variants/candy/gpio.c | 1 - .../google/rambi/variants/candy/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/clapper/Makefile.inc | 1 - src/mainboard/google/rambi/variants/clapper/gpio.c | 1 - .../google/rambi/variants/clapper/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/enguarde/Makefile.inc | 1 - src/mainboard/google/rambi/variants/enguarde/gpio.c | 1 - .../google/rambi/variants/enguarde/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/glimmer/Makefile.inc | 1 - src/mainboard/google/rambi/variants/glimmer/gpio.c | 1 - .../google/rambi/variants/glimmer/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/gnawty/Makefile.inc | 1 - src/mainboard/google/rambi/variants/gnawty/gpio.c | 1 - .../google/rambi/variants/gnawty/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/heli/Makefile.inc | 1 - src/mainboard/google/rambi/variants/heli/gpio.c | 1 - .../google/rambi/variants/heli/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/kip/Makefile.inc | 1 - src/mainboard/google/rambi/variants/kip/gpio.c | 1 - .../google/rambi/variants/kip/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/ninja/Makefile.inc | 1 - src/mainboard/google/rambi/variants/ninja/gpio.c | 1 - .../google/rambi/variants/ninja/include/variant/acpi/dptf.asl | 1 - .../google/rambi/variants/ninja/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/ninja/lan.c | 1 - src/mainboard/google/rambi/variants/orco/Makefile.inc | 1 - src/mainboard/google/rambi/variants/orco/gpio.c | 1 - .../google/rambi/variants/orco/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/quawks/Makefile.inc | 1 - src/mainboard/google/rambi/variants/quawks/gpio.c | 1 - .../google/rambi/variants/quawks/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/rambi/Makefile.inc | 1 - src/mainboard/google/rambi/variants/rambi/gpio.c | 1 - .../google/rambi/variants/rambi/include/variant/acpi/dptf.asl | 1 - .../google/rambi/variants/rambi/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/squawks/Makefile.inc | 1 - src/mainboard/google/rambi/variants/squawks/gpio.c | 1 - .../google/rambi/variants/squawks/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/sumo/Makefile.inc | 1 - src/mainboard/google/rambi/variants/sumo/gpio.c | 1 - .../google/rambi/variants/sumo/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/sumo/lan.c | 1 - src/mainboard/google/rambi/variants/swanky/Makefile.inc | 1 - src/mainboard/google/rambi/variants/swanky/gpio.c | 1 - .../google/rambi/variants/swanky/include/variant/onboard.h | 1 - src/mainboard/google/rambi/variants/winky/Makefile.inc | 1 - src/mainboard/google/rambi/variants/winky/gpio.c | 1 - .../google/rambi/variants/winky/include/variant/onboard.h | 1 - src/mainboard/google/rambi/w25q64.c | 1 - src/mainboard/google/reef/bootblock.c | 1 - src/mainboard/google/reef/chromeos.c | 1 - src/mainboard/google/reef/dsdt.asl | 1 - src/mainboard/google/reef/ec.c | 1 - src/mainboard/google/reef/mainboard.c | 1 - src/mainboard/google/reef/romstage.c | 1 - src/mainboard/google/reef/smihandler.c | 2 -- src/mainboard/google/reef/variants/baseboard/gpio.c | 1 - .../reef/variants/baseboard/include/baseboard/acpi/dptf.asl | 2 -- .../google/reef/variants/baseboard/include/baseboard/ec.h | 1 - .../google/reef/variants/baseboard/include/baseboard/gpio.h | 1 - .../reef/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/reef/variants/baseboard/memory.c | 1 - src/mainboard/google/reef/variants/baseboard/nhlt.c | 1 - src/mainboard/google/reef/variants/coral/gpio.c | 1 - .../google/reef/variants/coral/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/reef/variants/coral/include/variant/ec.h | 1 - .../google/reef/variants/coral/include/variant/gpio.h | 1 - src/mainboard/google/reef/variants/coral/mainboard.c | 1 - .../google/reef/variants/nasher/include/variant/acpi/dptf.asl | 2 -- src/mainboard/google/reef/variants/nasher/include/variant/ec.h | 1 - .../google/reef/variants/nasher/include/variant/gpio.h | 1 - .../google/reef/variants/pyro/include/variant/acpi/dptf.asl | 2 -- src/mainboard/google/reef/variants/pyro/include/variant/ec.h | 1 - src/mainboard/google/reef/variants/pyro/include/variant/gpio.h | 1 - src/mainboard/google/reef/variants/pyro/memory.c | 1 - .../google/reef/variants/reef/include/variant/acpi/dptf.asl | 1 - src/mainboard/google/reef/variants/reef/include/variant/ec.h | 1 - src/mainboard/google/reef/variants/reef/include/variant/gpio.h | 1 - .../google/reef/variants/sand/include/variant/acpi/dptf.asl | 2 -- src/mainboard/google/reef/variants/sand/include/variant/ec.h | 1 - src/mainboard/google/reef/variants/sand/include/variant/gpio.h | 1 - .../google/reef/variants/snappy/include/variant/acpi/dptf.asl | 2 -- src/mainboard/google/reef/variants/snappy/include/variant/ec.h | 1 - .../google/reef/variants/snappy/include/variant/gpio.h | 1 - src/mainboard/google/reef/variants/snappy/mainboard.c | 1 - src/mainboard/google/sarien/Makefile.inc | 1 - src/mainboard/google/sarien/bootblock.c | 1 - src/mainboard/google/sarien/chromeos.c | 1 - src/mainboard/google/sarien/dsdt.asl | 1 - src/mainboard/google/sarien/ec.c | 1 - src/mainboard/google/sarien/hda_verb.c | 1 - src/mainboard/google/sarien/ramstage.c | 1 - src/mainboard/google/sarien/romstage.c | 1 - src/mainboard/google/sarien/sku.c | 1 - src/mainboard/google/sarien/smihandler.c | 1 - src/mainboard/google/sarien/variants/arcada/Makefile.inc | 1 - src/mainboard/google/sarien/variants/arcada/gpio.c | 1 - .../sarien/variants/arcada/include/variant/acpi/dptf.asl | 1 - .../sarien/variants/arcada/include/variant/acpi/mainboard.asl | 1 - .../google/sarien/variants/arcada/include/variant/ec.h | 1 - .../google/sarien/variants/arcada/include/variant/gpio.h | 1 - .../google/sarien/variants/arcada/include/variant/hda_verb.h | 1 - .../google/sarien/variants/arcada/include/variant/variant.h | 1 - src/mainboard/google/sarien/variants/sarien/Makefile.inc | 1 - src/mainboard/google/sarien/variants/sarien/gpio.c | 1 - .../sarien/variants/sarien/include/variant/acpi/dptf.asl | 1 - .../sarien/variants/sarien/include/variant/acpi/mainboard.asl | 1 - .../google/sarien/variants/sarien/include/variant/ec.h | 1 - .../google/sarien/variants/sarien/include/variant/gpio.h | 1 - .../google/sarien/variants/sarien/include/variant/hda_verb.h | 1 - .../google/sarien/variants/sarien/include/variant/variant.h | 1 - src/mainboard/google/slippy/Makefile.inc | 1 - src/mainboard/google/slippy/acpi/ec.asl | 1 - src/mainboard/google/slippy/acpi/platform.asl | 2 -- src/mainboard/google/slippy/acpi/superio.asl | 1 - src/mainboard/google/slippy/acpi/thermal.asl | 1 - src/mainboard/google/slippy/acpi_tables.c | 1 - src/mainboard/google/slippy/chromeos.c | 1 - src/mainboard/google/slippy/cmos.layout | 1 - src/mainboard/google/slippy/dsdt.asl | 2 -- src/mainboard/google/slippy/ec.c | 1 - src/mainboard/google/slippy/ec.h | 1 - src/mainboard/google/slippy/gma-mainboard.ads | 1 - src/mainboard/google/slippy/mainboard.c | 2 -- src/mainboard/google/slippy/onboard.h | 1 - src/mainboard/google/slippy/romstage.c | 2 -- src/mainboard/google/slippy/smihandler.c | 2 -- src/mainboard/google/slippy/thermal.h | 1 - src/mainboard/google/slippy/variant.h | 1 - src/mainboard/google/slippy/variants/falco/Makefile.inc | 1 - src/mainboard/google/slippy/variants/falco/hda_verb.c | 1 - .../slippy/variants/falco/include/variant/acpi/mainboard.asl | 1 - .../google/slippy/variants/falco/include/variant/gpio.h | 1 - src/mainboard/google/slippy/variants/falco/romstage.c | 2 -- src/mainboard/google/slippy/variants/leon/Makefile.inc | 1 - src/mainboard/google/slippy/variants/leon/hda_verb.c | 1 - .../slippy/variants/leon/include/variant/acpi/mainboard.asl | 1 - .../google/slippy/variants/leon/include/variant/gpio.h | 1 - src/mainboard/google/slippy/variants/leon/romstage.c | 2 -- src/mainboard/google/slippy/variants/peppy/Makefile.inc | 1 - src/mainboard/google/slippy/variants/peppy/hda_verb.c | 1 - .../slippy/variants/peppy/include/variant/acpi/mainboard.asl | 1 - .../google/slippy/variants/peppy/include/variant/gpio.h | 1 - src/mainboard/google/slippy/variants/peppy/romstage.c | 2 -- src/mainboard/google/slippy/variants/wolf/Makefile.inc | 1 - src/mainboard/google/slippy/variants/wolf/hda_verb.c | 1 - .../slippy/variants/wolf/include/variant/acpi/mainboard.asl | 1 - .../google/slippy/variants/wolf/include/variant/gpio.h | 1 - src/mainboard/google/slippy/variants/wolf/romstage.c | 2 -- src/mainboard/google/smaug/Kconfig | 1 - src/mainboard/google/smaug/Makefile.inc | 1 - src/mainboard/google/smaug/bct/Makefile.inc | 2 -- src/mainboard/google/smaug/bct/cfg2inc.sh | 1 - src/mainboard/google/smaug/bct/emmc.cfg | 1 - src/mainboard/google/smaug/bct/spi.cfg | 1 - src/mainboard/google/smaug/boardid.c | 1 - src/mainboard/google/smaug/bootblock.c | 1 - src/mainboard/google/smaug/chromeos.c | 1 - src/mainboard/google/smaug/devicetree.cb | 1 - src/mainboard/google/smaug/gpio.h | 1 - src/mainboard/google/smaug/mainboard.c | 2 -- src/mainboard/google/smaug/pmic.c | 2 -- src/mainboard/google/smaug/pmic.h | 2 -- src/mainboard/google/smaug/reset.c | 1 - src/mainboard/google/smaug/romstage.c | 1 - src/mainboard/google/smaug/sdram_configs.c | 2 -- src/mainboard/google/storm/Kconfig | 1 - src/mainboard/google/storm/Makefile.inc | 1 - src/mainboard/google/storm/boardid.c | 1 - src/mainboard/google/storm/bootblock.c | 2 +- src/mainboard/google/storm/cdp.c | 1 - src/mainboard/google/storm/chromeos.c | 1 - src/mainboard/google/storm/devicetree.cb | 1 - src/mainboard/google/storm/gsbi.c | 1 - src/mainboard/google/storm/mainboard.c | 2 -- src/mainboard/google/storm/mmu.c | 2 +- src/mainboard/google/storm/mmu.h | 2 +- src/mainboard/google/storm/reset.c | 2 -- src/mainboard/google/storm/romstage.c | 2 -- src/mainboard/google/stout/Makefile.inc | 1 - src/mainboard/google/stout/acpi/ec.asl | 1 - src/mainboard/google/stout/acpi/mainboard.asl | 1 - src/mainboard/google/stout/acpi/platform.asl | 1 - src/mainboard/google/stout/acpi/superio.asl | 1 - src/mainboard/google/stout/acpi/thermal.asl | 1 - src/mainboard/google/stout/acpi_tables.c | 1 - src/mainboard/google/stout/chromeos.c | 1 - src/mainboard/google/stout/cmos.layout | 1 - src/mainboard/google/stout/dsdt.asl | 2 -- src/mainboard/google/stout/early_init.c | 2 -- src/mainboard/google/stout/ec.c | 1 - src/mainboard/google/stout/ec.h | 1 - src/mainboard/google/stout/gpio.c | 1 - src/mainboard/google/stout/hda_verb.c | 1 - src/mainboard/google/stout/mainboard.c | 2 -- src/mainboard/google/stout/mainboard_smi.c | 1 - src/mainboard/google/stout/onboard.h | 1 - src/mainboard/google/stout/thermal.h | 1 - src/mainboard/google/trogdor/Makefile.inc | 2 -- src/mainboard/google/trogdor/board.h | 1 - src/mainboard/google/trogdor/boardid.c | 2 -- src/mainboard/google/trogdor/bootblock.c | 1 - src/mainboard/google/trogdor/chromeos.c | 1 - src/mainboard/google/trogdor/chromeos.fmd | 1 - src/mainboard/google/trogdor/devicetree.cb | 1 - src/mainboard/google/trogdor/mainboard.c | 1 - src/mainboard/google/trogdor/memlayout.ld | 1 - src/mainboard/google/trogdor/reset.c | 2 -- src/mainboard/google/trogdor/romstage.c | 1 - src/mainboard/google/veyron/Kconfig | 1 - src/mainboard/google/veyron/Makefile.inc | 1 - src/mainboard/google/veyron/board.h | 1 - src/mainboard/google/veyron/boardid.c | 1 - src/mainboard/google/veyron/bootblock.c | 2 -- src/mainboard/google/veyron/chromeos.c | 1 - src/mainboard/google/veyron/devicetree.cb | 1 - src/mainboard/google/veyron/mainboard.c | 1 - src/mainboard/google/veyron/reset.c | 1 - src/mainboard/google/veyron/romstage.c | 1 - src/mainboard/google/veyron/sdram_configs.c | 1 - src/mainboard/google/veyron_mickey/Kconfig | 1 - src/mainboard/google/veyron_mickey/Makefile.inc | 1 - src/mainboard/google/veyron_mickey/board.h | 1 - src/mainboard/google/veyron_mickey/boardid.c | 1 - src/mainboard/google/veyron_mickey/bootblock.c | 2 -- src/mainboard/google/veyron_mickey/chromeos.c | 1 - src/mainboard/google/veyron_mickey/devicetree.cb | 1 - src/mainboard/google/veyron_mickey/mainboard.c | 1 - src/mainboard/google/veyron_mickey/reset.c | 1 - src/mainboard/google/veyron_mickey/romstage.c | 1 - src/mainboard/google/veyron_mickey/sdram_configs.c | 1 - src/mainboard/google/veyron_rialto/Kconfig | 1 - src/mainboard/google/veyron_rialto/Makefile.inc | 1 - src/mainboard/google/veyron_rialto/board.h | 1 - src/mainboard/google/veyron_rialto/boardid.c | 1 - src/mainboard/google/veyron_rialto/bootblock.c | 2 -- src/mainboard/google/veyron_rialto/chromeos.c | 1 - src/mainboard/google/veyron_rialto/devicetree.cb | 1 - src/mainboard/google/veyron_rialto/mainboard.c | 1 - src/mainboard/google/veyron_rialto/reset.c | 1 - src/mainboard/google/veyron_rialto/romstage.c | 1 - src/mainboard/google/veyron_rialto/sdram_configs.c | 1 - src/mainboard/google/volteer/Makefile.inc | 1 - src/mainboard/google/volteer/bootblock.c | 1 - src/mainboard/google/volteer/chromeos.c | 1 - src/mainboard/google/volteer/dsdt.asl | 1 - src/mainboard/google/volteer/ec.c | 1 - src/mainboard/google/volteer/mainboard.c | 1 - src/mainboard/google/volteer/romstage.c | 1 - src/mainboard/google/volteer/smihandler.c | 1 - src/mainboard/google/volteer/spd/Makefile.inc | 1 - src/mainboard/google/volteer/variants/baseboard/Makefile.inc | 1 - src/mainboard/google/volteer/variants/baseboard/gpio.c | 1 - .../google/volteer/variants/baseboard/include/baseboard/ec.h | 1 - .../google/volteer/variants/baseboard/include/baseboard/gpio.h | 1 - .../volteer/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/google/volteer/variants/baseboard/memory.c | 1 - src/mainboard/google/volteer/variants/ripto/Makefile.inc | 1 - src/mainboard/google/volteer/variants/ripto/gpio.c | 1 - .../google/volteer/variants/ripto/include/variant/ec.h | 1 - .../google/volteer/variants/ripto/include/variant/gpio.h | 1 - src/mainboard/google/volteer/variants/volteer/Makefile.inc | 1 - .../volteer/variants/volteer/include/variant/acpi/dptf.asl | 1 - .../google/volteer/variants/volteer/include/variant/ec.h | 1 - .../google/volteer/variants/volteer/include/variant/gpio.h | 1 - 1266 files changed, 6 insertions(+), 1527 deletions(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 702ba13c55..475668d428 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index ca42470796..2fbfe30789 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/acpi/ec.asl b/src/mainboard/google/auron/acpi/ec.asl index 5740c27d32..d495af4bcd 100644 --- a/src/mainboard/google/auron/acpi/ec.asl +++ b/src/mainboard/google/auron/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index cd6a830564..e726fe6dcf 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/acpi/superio.asl b/src/mainboard/google/auron/acpi/superio.asl index 88e96e1d25..a64734771e 100644 --- a/src/mainboard/google/auron/acpi/superio.asl +++ b/src/mainboard/google/auron/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl index 922b5c1fc8..0e57afae36 100644 --- a/src/mainboard/google/auron/acpi/thermal.asl +++ b/src/mainboard/google/auron/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/acpi/video.asl b/src/mainboard/google/auron/acpi/video.asl index 68946552a6..e4b8b8e2c7 100644 --- a/src/mainboard/google/auron/acpi/video.asl +++ b/src/mainboard/google/auron/acpi/video.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 7b0899a065..042c1be8c5 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index a3174b5a48..a268f0ab77 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index 39f9516e0b..014f442651 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index ad5eed1e18..f7c5000e9c 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index 0589864d7f..089dbeef81 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/ec.h b/src/mainboard/google/auron/ec.h index d1a54a9093..1242c7e3f5 100644 --- a/src/mainboard/google/auron/ec.h +++ b/src/mainboard/google/auron/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index a24cf52134..6afc8e23c0 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 2cbd0e78c2..da72d8f430 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index d5687f211c..34749c42fc 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 862e2c32e0..324227e704 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_paine/gpio.c b/src/mainboard/google/auron/variants/auron_paine/gpio.c index e8b6c065b1..59593da4f0 100644 --- a/src/mainboard/google/auron/variants/auron_paine/gpio.c +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl index 1befc4b239..c521937177 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h index d560ccf968..66ff8afbfe 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h index 97975a1302..4f4dfeb970 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h index 0a37a700c0..aaa2ae0f1e 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h index 0b66c0b58f..cc87da619f 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index 96dbe660e0..f86b8f64a4 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc index 44edc70dbb..9e2c76af8f 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 2991d15eff..2baac7b916 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_yuna/gpio.c b/src/mainboard/google/auron/variants/auron_yuna/gpio.c index e8b6c065b1..59593da4f0 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/gpio.c +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl index 1befc4b239..c521937177 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h index 70913215c9..4b37e986d3 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h index 97975a1302..4f4dfeb970 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h index 0a37a700c0..aaa2ae0f1e 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h index 0b66c0b58f..cc87da619f 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index 96dbe660e0..f86b8f64a4 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc index 44edc70dbb..9e2c76af8f 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 2991d15eff..2baac7b916 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/buddy/gpio.c b/src/mainboard/google/auron/variants/buddy/gpio.c index fbb682abf9..ec660c526b 100644 --- a/src/mainboard/google/auron/variants/buddy/gpio.c +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index 5ca7cfb64b..a56deb2202 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h index 7d0af93481..5dec333265 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h index 0b2c6641f0..3a1b48f0f0 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h index cfdaca05a6..ea0a5c45ab 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h b/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h index ae5c8f0e97..1fb6b859dc 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index a0436ecc89..5840a9cb14 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc index 275d9836dd..cc9726f5fb 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index 93e9fb2551..fe0892a807 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/gandof/gpio.c b/src/mainboard/google/auron/variants/gandof/gpio.c index 3de9a0b9d7..b789b87321 100644 --- a/src/mainboard/google/auron/variants/gandof/gpio.c +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl index bfdf4769f2..c521937177 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h index 23e9146751..8b9e76fe82 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h b/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h index 97975a1302..4f4dfeb970 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h index 8720ab02a3..4bbf0efa8d 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h b/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h index cd0bacb765..7136afaf3f 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index a86fb0e9b3..f86b8f64a4 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc index 23d0b4e0c3..8b387816bb 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 2991d15eff..2baac7b916 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/lulu/gpio.c b/src/mainboard/google/auron/variants/lulu/gpio.c index a46c4d4e2a..8aac461477 100644 --- a/src/mainboard/google/auron/variants/lulu/gpio.c +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Sage Electronic Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl index 1f91456d77..a781ea4e6f 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h index cfc279ac0b..da4e92c290 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h index 0adc5890eb..9e46521d06 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h index a7df6f425c..503b192eb1 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Sage Electronic Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h index 0b66c0b58f..cc87da619f 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index e5976bcebf..e547438db1 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc index 86cb2d2119..b29e8766aa 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Sage Electronic Engineering ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index bd76947d68..30e7fd71bb 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Sage Electronic Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/board_version.c b/src/mainboard/google/auron/variants/samus/board_version.c index dfb7c248a1..2853d44dcc 100644 --- a/src/mainboard/google/auron/variants/samus/board_version.c +++ b/src/mainboard/google/auron/variants/samus/board_version.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/gpio.c b/src/mainboard/google/auron/variants/samus/gpio.c index 72ddcb2259..f6b6c71d9b 100644 --- a/src/mainboard/google/auron/variants/samus/gpio.c +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 40a4df051c..2253fd71a1 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/include/variant/board_version.h b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h index 55c8360b0a..6129ce5591 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/board_version.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/include/variant/onboard.h b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h index dcbfc6ed43..1e1373a223 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h index da48521a7e..e22a40ecc0 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/include/variant/thermal.h b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h index 8019f780ef..cc87da619f 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index 051653f0e6..be6b49a101 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc index a026ef3c66..f57e9e7688 100644 --- a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index ffb90f997d..5a9e2d3ff8 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 3b763a08c4..bb9bf7f19f 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 692d635ac6..d73ff8b56a 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/beltino/acpi/platform.asl b/src/mainboard/google/beltino/acpi/platform.asl index 54a9cd43e1..c0fac8da72 100644 --- a/src/mainboard/google/beltino/acpi/platform.asl +++ b/src/mainboard/google/beltino/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/acpi/superio.asl b/src/mainboard/google/beltino/acpi/superio.asl index 7ccdf148f0..5bc7fdab46 100644 --- a/src/mainboard/google/beltino/acpi/superio.asl +++ b/src/mainboard/google/beltino/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index a064121d73..7aed671b9a 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/acpi/usb.asl b/src/mainboard/google/beltino/acpi/usb.asl index 59c96544c0..92b6dc97d8 100644 --- a/src/mainboard/google/beltino/acpi/usb.asl +++ b/src/mainboard/google/beltino/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 09ac6504ef..9d47b976f8 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index cbe3c727ae..9637c8efa7 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index 39f9516e0b..014f442651 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 79981254b8..f494d2fd79 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 1c38e45e43..0e18e83569 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index bbac6ecb48..2b42ceb115 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 607c8a4d48..c50787eae9 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index d2f923a7cf..c6677341e5 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 57e5fa2dca..9f0671b160 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h b/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h index 116eeeb07a..2245ce155b 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h index 7c52c95e29..0920bb3bc7 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/mccloud/led.c b/src/mainboard/google/beltino/variants/mccloud/led.c index 332f4c7f93..00e45d131d 100644 --- a/src/mainboard/google/beltino/variants/mccloud/led.c +++ b/src/mainboard/google/beltino/variants/mccloud/led.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 0e71960ee1..5b084ac17a 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h b/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h index 8423e1e2ab..7684956e17 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h index 4ae1dac70a..898e029c4b 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/monroe/led.c b/src/mainboard/google/beltino/variants/monroe/led.c index 8900338e9c..9e2c698be0 100644 --- a/src/mainboard/google/beltino/variants/monroe/led.c +++ b/src/mainboard/google/beltino/variants/monroe/led.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 57e5fa2dca..9f0671b160 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h b/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h index e48f0b4b41..6536e52462 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h index 9dd3551440..8ea3823bec 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/panther/led.c b/src/mainboard/google/beltino/variants/panther/led.c index e40c40d2c8..5c91eb859c 100644 --- a/src/mainboard/google/beltino/variants/panther/led.c +++ b/src/mainboard/google/beltino/variants/panther/led.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 57e5fa2dca..9f0671b160 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h b/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h index 6980ebbe75..3aefce0544 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h index ed9e6828dd..ff11d7a8db 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/tricky/led.c b/src/mainboard/google/beltino/variants/tricky/led.c index e688a0cc64..d22bc9cc7f 100644 --- a/src/mainboard/google/beltino/variants/tricky/led.c +++ b/src/mainboard/google/beltino/variants/tricky/led.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 57e5fa2dca..9f0671b160 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h b/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h index dffefd6243..606cdb6a9c 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h index 4a4c4fac17..60f86cfd27 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/beltino/variants/zako/led.c b/src/mainboard/google/beltino/variants/zako/led.c index 15148adeb1..e44aa489ed 100644 --- a/src/mainboard/google/beltino/variants/zako/led.c +++ b/src/mainboard/google/beltino/variants/zako/led.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 18f200647a..202cb38cfd 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/acpi/ec.asl b/src/mainboard/google/butterfly/acpi/ec.asl index 404b84d07c..faba3ff412 100644 --- a/src/mainboard/google/butterfly/acpi/ec.asl +++ b/src/mainboard/google/butterfly/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index 2b1d6373e3..11b6852b20 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/butterfly/acpi/platform.asl b/src/mainboard/google/butterfly/acpi/platform.asl index 0acd4a262e..01e106b13f 100644 --- a/src/mainboard/google/butterfly/acpi/platform.asl +++ b/src/mainboard/google/butterfly/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/acpi/superio.asl b/src/mainboard/google/butterfly/acpi/superio.asl index d31c9462fd..cb06a9aec4 100644 --- a/src/mainboard/google/butterfly/acpi/superio.asl +++ b/src/mainboard/google/butterfly/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/acpi/thermal.asl b/src/mainboard/google/butterfly/acpi/thermal.asl index 8268799c75..f9964e966b 100644 --- a/src/mainboard/google/butterfly/acpi/thermal.asl +++ b/src/mainboard/google/butterfly/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 5ab22e1fd5..0e930aa78e 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 10b461864c..74a3031d6d 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index e41ab4fa88..8bafde2b35 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index dce14a4c58..2596de25ba 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 35f75c4232..a3cea3f5e2 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/ec.c b/src/mainboard/google/butterfly/ec.c index 75b144470a..6e1fc349a7 100644 --- a/src/mainboard/google/butterfly/ec.c +++ b/src/mainboard/google/butterfly/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/ec.h b/src/mainboard/google/butterfly/ec.h index 6cb0748ded..47acc0c4fa 100644 --- a/src/mainboard/google/butterfly/ec.h +++ b/src/mainboard/google/butterfly/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c index 2630177cf1..167731b9c6 100644 --- a/src/mainboard/google/butterfly/gpio.c +++ b/src/mainboard/google/butterfly/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c index 973bf73978..de08867e76 100644 --- a/src/mainboard/google/butterfly/hda_verb.c +++ b/src/mainboard/google/butterfly/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index eb4d15bea7..37c17ee514 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index cd669c9dca..eb069ea758 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index f890eb3cf8..3aad95924d 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/butterfly/thermal.h b/src/mainboard/google/butterfly/thermal.h index eea634ea15..9cfc5d77bd 100644 --- a/src/mainboard/google/butterfly/thermal.h +++ b/src/mainboard/google/butterfly/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc index ff94b76377..8c621a1f74 100644 --- a/src/mainboard/google/cheza/Makefile.inc +++ b/src/mainboard/google/cheza/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h index f83ca06003..bf53a44c03 100644 --- a/src/mainboard/google/cheza/board.h +++ b/src/mainboard/google/cheza/board.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/boardid.c b/src/mainboard/google/cheza/boardid.c index fffac82ab6..bca28693bd 100644 --- a/src/mainboard/google/cheza/boardid.c +++ b/src/mainboard/google/cheza/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c index ad858429c7..05da53ed6c 100644 --- a/src/mainboard/google/cheza/bootblock.c +++ b/src/mainboard/google/cheza/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 6f713fe08a..4abe1f13de 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index b0d2d99996..429fa124db 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018, The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb index 1116cca15c..0e5ca5eaa6 100644 --- a/src/mainboard/google/cheza/devicetree.cb +++ b/src/mainboard/google/cheza/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018, The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 804906a37a..1e46167c90 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld index cbc50e2d11..9f22755be0 100644 --- a/src/mainboard/google/cheza/memlayout.ld +++ b/src/mainboard/google/cheza/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/reset.c b/src/mainboard/google/cheza/reset.c index b3cd192ec5..c566e127fe 100644 --- a/src/mainboard/google/cheza/reset.c +++ b/src/mainboard/google/cheza/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index de737b1159..fd54e9e186 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 86198a61dc..d9b15c78d5 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index b3eb25aeb0..4f69daf92d 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index 0d188701e7..9ebef19065 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 81e9fee397..97dd96f04d 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl index 271fd0a867..da185cbc80 100644 --- a/src/mainboard/google/cyan/acpi/ec.asl +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index af0dc75d5d..0fc0d94a15 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index b3961c00c2..ff98b9053a 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl index 1fc362ef85..2b6f148631 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl index e8bc0f290c..9391be7fed 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl index 421119a129..7585cb75f8 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index 9e63d128f9..a1335d9952 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl index 4a80c19d3c..9163cff52a 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_elan.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index 0db58242f7..00b3c08165 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 9b3b5c01e9..2968f8d676 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index cc5ec2dabe..a0edabdccb 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c index b08dbce630..8c456d3422 100644 --- a/src/mainboard/google/cyan/com_init.c +++ b/src/mainboard/google/cyan/com_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 45aeeb4224..90dfa37ff5 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index 9ff06391a1..8ebd096da5 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h index 1092977b03..450d863ba3 100644 --- a/src/mainboard/google/cyan/ec.h +++ b/src/mainboard/google/cyan/ec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index 2a54254aa1..9e5af024e4 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c index 79dc8d6c91..f0855adbc2 100644 --- a/src/mainboard/google/cyan/irqroute.c +++ b/src/mainboard/google/cyan/irqroute.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h index c80594541b..85d8a5f93b 100644 --- a/src/mainboard/google/cyan/irqroute.h +++ b/src/mainboard/google/cyan/irqroute.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 4cce5a51ed..0d137f1861 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index dea73e9eee..7116b71ffc 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 4db638441b..2871915106 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 8dd4366ad0..cb65b091db 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h index 0c5b3265ef..cd65be50a4 100644 --- a/src/mainboard/google/cyan/spd/spd_util.h +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/banon/Makefile.inc b/src/mainboard/google/cyan/variants/banon/Makefile.inc index a0adcd47f4..273895f5a5 100644 --- a/src/mainboard/google/cyan/variants/banon/Makefile.inc +++ b/src/mainboard/google/cyan/variants/banon/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index 2a3e8fc8ec..c0a1cb25b6 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl index c7c20cea4d..9be7ba5dd3 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl index 9876f87e43..e2a50d6161 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h b/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h index 5f2ce28f31..d8d91af1f8 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c index e516bb8446..22787aae27 100644 --- a/src/mainboard/google/cyan/variants/banon/romstage.c +++ b/src/mainboard/google/cyan/variants/banon/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/banon/spd_util.c b/src/mainboard/google/cyan/variants/banon/spd_util.c index ddae835a38..1b31e63d8a 100644 --- a/src/mainboard/google/cyan/variants/banon/spd_util.c +++ b/src/mainboard/google/cyan/variants/banon/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h index 2a16f04d2a..3609df5874 100644 --- a/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc index 0fcc9add0b..839647463a 100644 --- a/src/mainboard/google/cyan/variants/celes/Makefile.inc +++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index 6f53f2ea37..5304ed0615 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl index fa2eea92d0..6c53db92ad 100644 --- a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl index 75797f8bc4..3ee5394431 100644 --- a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h index f156004f9b..ec45a1eb9a 100644 --- a/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index 6c522a1d0c..bc8c3a97c7 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/celes/spd_util.c b/src/mainboard/google/cyan/variants/celes/spd_util.c index baf67053f6..58726c182a 100644 --- a/src/mainboard/google/cyan/variants/celes/spd_util.c +++ b/src/mainboard/google/cyan/variants/celes/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc index ea80446156..da6f751fc9 100644 --- a/src/mainboard/google/cyan/variants/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 05ba93e102..1e8590ed56 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl index 3c8dbe4a52..83ba03035a 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl index e9b16fcf78..dd30a68f2f 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h index 9d8cd25a0e..5d5ffbc2f1 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/cyan/spd_util.c b/src/mainboard/google/cyan/variants/cyan/spd_util.c index 75d7509b73..fc0eebb87b 100644 --- a/src/mainboard/google/cyan/variants/cyan/spd_util.c +++ b/src/mainboard/google/cyan/variants/cyan/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index ad9ac8a422..5c80941095 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index 59486af102..487046a3f2 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl index 8f54bb69d6..f76f282f68 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl index 217f77f09f..19ec65ae63 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h index d68aa13e01..e676768c23 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c index 12fef77394..1cfc978680 100644 --- a/src/mainboard/google/cyan/variants/edgar/romstage.c +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/edgar/spd_util.c b/src/mainboard/google/cyan/variants/edgar/spd_util.c index f9b368117b..5197d1b33c 100644 --- a/src/mainboard/google/cyan/variants/edgar/spd_util.c +++ b/src/mainboard/google/cyan/variants/edgar/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc index d37ba1da08..9153eb43f2 100644 --- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc +++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 1036cc6985..1fe8f604a0 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl index 6f8017960f..7fc05e0d33 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl index ca0627cbca..8cee066038 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h b/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h index 9b77c243dd..a596f3898e 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c index d790708cce..9dee808d6a 100644 --- a/src/mainboard/google/cyan/variants/kefka/ramstage.c +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/kefka/romstage.c b/src/mainboard/google/cyan/variants/kefka/romstage.c index bdaf885f2e..f2bf5a65c6 100644 --- a/src/mainboard/google/cyan/variants/kefka/romstage.c +++ b/src/mainboard/google/cyan/variants/kefka/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/kefka/spd_util.c b/src/mainboard/google/cyan/variants/kefka/spd_util.c index 9db56b9492..f7f387409b 100644 --- a/src/mainboard/google/cyan/variants/kefka/spd_util.c +++ b/src/mainboard/google/cyan/variants/kefka/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index da5b5cc153..42097b0acc 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index 955dc51fb7..82341e4c5d 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl index fa6d113658..e70eae0294 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl index 4eeab42822..4a77209ed3 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h index ec4fa62496..eead309cf3 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/reks/ramstage.c b/src/mainboard/google/cyan/variants/reks/ramstage.c index 27f9dfa241..e212131773 100644 --- a/src/mainboard/google/cyan/variants/reks/ramstage.c +++ b/src/mainboard/google/cyan/variants/reks/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c index 5414cbd7d5..312709b7eb 100644 --- a/src/mainboard/google/cyan/variants/reks/romstage.c +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/reks/spd_util.c b/src/mainboard/google/cyan/variants/reks/spd_util.c index d2a130f664..00b47deb1b 100644 --- a/src/mainboard/google/cyan/variants/reks/spd_util.c +++ b/src/mainboard/google/cyan/variants/reks/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/relm/Makefile.inc b/src/mainboard/google/cyan/variants/relm/Makefile.inc index c2c1b25155..199295d4d8 100644 --- a/src/mainboard/google/cyan/variants/relm/Makefile.inc +++ b/src/mainboard/google/cyan/variants/relm/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index e9014ac6f0..d452622e9d 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl index 2c93061857..e70eae0294 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl index 4eeab42822..4a77209ed3 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h b/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h index e809f536d8..6d4d682e37 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c index 3fbd2aebd9..0030d9f48c 100644 --- a/src/mainboard/google/cyan/variants/relm/ramstage.c +++ b/src/mainboard/google/cyan/variants/relm/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/relm/romstage.c b/src/mainboard/google/cyan/variants/relm/romstage.c index 5414cbd7d5..312709b7eb 100644 --- a/src/mainboard/google/cyan/variants/relm/romstage.c +++ b/src/mainboard/google/cyan/variants/relm/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/relm/spd_util.c b/src/mainboard/google/cyan/variants/relm/spd_util.c index 904c8c186e..5315c5bae3 100644 --- a/src/mainboard/google/cyan/variants/relm/spd_util.c +++ b/src/mainboard/google/cyan/variants/relm/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/setzer/Makefile.inc b/src/mainboard/google/cyan/variants/setzer/Makefile.inc index 1f7c470459..66b666cdea 100644 --- a/src/mainboard/google/cyan/variants/setzer/Makefile.inc +++ b/src/mainboard/google/cyan/variants/setzer/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index 517d06971a..70ffeba09d 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl index 5ac2a09532..324d8bc351 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl index c77d99ae1b..c976fb96d0 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h b/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h index 3ebdc5afe5..3f9f4a9b26 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/setzer/ramstage.c b/src/mainboard/google/cyan/variants/setzer/ramstage.c index 38bc34cb35..84d2f43822 100644 --- a/src/mainboard/google/cyan/variants/setzer/ramstage.c +++ b/src/mainboard/google/cyan/variants/setzer/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/setzer/romstage.c b/src/mainboard/google/cyan/variants/setzer/romstage.c index 13f798924a..b36f09c0c9 100644 --- a/src/mainboard/google/cyan/variants/setzer/romstage.c +++ b/src/mainboard/google/cyan/variants/setzer/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/setzer/spd_util.c b/src/mainboard/google/cyan/variants/setzer/spd_util.c index cd1a2e35d0..43b57376c3 100644 --- a/src/mainboard/google/cyan/variants/setzer/spd_util.c +++ b/src/mainboard/google/cyan/variants/setzer/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/Makefile.inc b/src/mainboard/google/cyan/variants/terra/Makefile.inc index 48d1d96d2a..23a7c4166a 100644 --- a/src/mainboard/google/cyan/variants/terra/Makefile.inc +++ b/src/mainboard/google/cyan/variants/terra/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index dc10ceff85..1f484fe51d 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl index ee247f2065..8c8495f540 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl index 5f212bdb85..bdd9792e8c 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl index 775e27b816..4ace7195d6 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl index 32bdbfbb92..ad8f4de332 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl index 77482a4bd4..09f4b6d7f8 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h index 613039b98f..2a8ff9f294 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/ramstage.c b/src/mainboard/google/cyan/variants/terra/ramstage.c index 51857f9819..edbe7e06ad 100644 --- a/src/mainboard/google/cyan/variants/terra/ramstage.c +++ b/src/mainboard/google/cyan/variants/terra/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c index 8b30d69c92..b1850c5491 100644 --- a/src/mainboard/google/cyan/variants/terra/romstage.c +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/terra/spd_util.c b/src/mainboard/google/cyan/variants/terra/spd_util.c index 72d17d5085..1483bab84a 100644 --- a/src/mainboard/google/cyan/variants/terra/spd_util.c +++ b/src/mainboard/google/cyan/variants/terra/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/ultima/Makefile.inc b/src/mainboard/google/cyan/variants/ultima/Makefile.inc index 54234095fa..19acf48e47 100644 --- a/src/mainboard/google/cyan/variants/ultima/Makefile.inc +++ b/src/mainboard/google/cyan/variants/ultima/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 3cae31384f..78d8a36d97 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl index 534143cf03..1499545e13 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl index ca0627cbca..8cee066038 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h index 027c55ec82..73121a16c8 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/ultima/ramstage.c b/src/mainboard/google/cyan/variants/ultima/ramstage.c index 0e299648a6..8ffee5ae75 100644 --- a/src/mainboard/google/cyan/variants/ultima/ramstage.c +++ b/src/mainboard/google/cyan/variants/ultima/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/ultima/spd_util.c b/src/mainboard/google/cyan/variants/ultima/spd_util.c index ff3ac71015..ce3cf7fd87 100644 --- a/src/mainboard/google/cyan/variants/ultima/spd_util.c +++ b/src/mainboard/google/cyan/variants/ultima/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc index 4f233f49bb..5ba9b840d9 100644 --- a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc +++ b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index ecd74ef386..d96c848f6d 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl index d5548e1e11..775971ac31 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl index ca0627cbca..8cee066038 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h b/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h index 5db44ecbbe..4be300d83e 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/variants/wizpig/spd_util.c b/src/mainboard/google/cyan/variants/wizpig/spd_util.c index 80526a1861..f055fee423 100644 --- a/src/mainboard/google/cyan/variants/wizpig/spd_util.c +++ b/src/mainboard/google/cyan/variants/wizpig/spd_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Matt DeVillier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c index 5eea802942..9780e0ac1c 100644 --- a/src/mainboard/google/cyan/w25q64.c +++ b/src/mainboard/google/cyan/w25q64.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index 61bb80b3a8..dc54f916b4 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/Makefile.inc b/src/mainboard/google/daisy/Makefile.inc index 65e0ea20ee..fd76686e40 100644 --- a/src/mainboard/google/daisy/Makefile.inc +++ b/src/mainboard/google/daisy/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index e24d8b1138..ae4da39e3d 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/devicetree.cb b/src/mainboard/google/daisy/devicetree.cb index 93a7ea7f2f..aeb2fc8f2f 100644 --- a/src/mainboard/google/daisy/devicetree.cb +++ b/src/mainboard/google/daisy/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/exynos5250.h b/src/mainboard/google/daisy/exynos5250.h index d742b55db9..8fb3704751 100644 --- a/src/mainboard/google/daisy/exynos5250.h +++ b/src/mainboard/google/daisy/exynos5250.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 30f8805c41..ae6d866e5a 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index c5b752c2bf..3f75fd0fb8 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index e200640dad..bb91d07db7 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/daisy/wakeup.c b/src/mainboard/google/daisy/wakeup.c index 5a2af5b4e2..b4af25615c 100644 --- a/src/mainboard/google/daisy/wakeup.c +++ b/src/mainboard/google/daisy/wakeup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index 1d222b245d..d49ae9692a 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/bootblock.c b/src/mainboard/google/dedede/bootblock.c index 8685fa776a..6439b32334 100644 --- a/src/mainboard/google/dedede/bootblock.c +++ b/src/mainboard/google/dedede/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index c2729a1e9d..a9cc602e8d 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 45a1486b55..53423b8cb9 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/ec.c b/src/mainboard/google/dedede/ec.c index 7aa4773ebe..98509c3b53 100644 --- a/src/mainboard/google/dedede/ec.c +++ b/src/mainboard/google/dedede/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 3ac273af2c..4df190c2be 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 8f4756b5df..9c220d4538 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 4e3c830384..f7c2643f88 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc index 7de7f83a4c..091c6d0457 100644 --- a/src/mainboard/google/dedede/spd/Makefile.inc +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Authors. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 13419b8b66..390910470e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h index 0f356f882f..9190c8574c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index de94e76f3d..dfb2cd1bd7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index a0facb261d..8fd5119bd4 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index bcb12959d1..ff8a4ec661 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h index cc897dcdcf..70bd8e7785 100644 --- a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h b/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h index bf23f6e457..fd92743190 100644 --- a/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index c55051b9fc..3e06d73658 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Authors. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h index cc897dcdcf..70bd8e7785 100644 --- a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h index bf23f6e457..fd92743190 100644 --- a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index c55051b9fc..3e06d73658 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Authors. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h index cc897dcdcf..70bd8e7785 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h index bf23f6e457..fd92743190 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index 8cb746e0a0..7773477da1 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/bootblock.c b/src/mainboard/google/dragonegg/bootblock.c index 86559474da..c43ea9a503 100644 --- a/src/mainboard/google/dragonegg/bootblock.c +++ b/src/mainboard/google/dragonegg/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 2982a2095b..c87b16a3d0 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index f84b0b5a60..081fcb053a 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/ec.c b/src/mainboard/google/dragonegg/ec.c index 4fd6807215..a1f272fa16 100644 --- a/src/mainboard/google/dragonegg/ec.c +++ b/src/mainboard/google/dragonegg/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c index df83f38c3e..64f7a92525 100644 --- a/src/mainboard/google/dragonegg/mainboard.c +++ b/src/mainboard/google/dragonegg/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index f1f5143ab5..0cc54d56c1 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c index 8d2afd60b7..524dabaf07 100644 --- a/src/mainboard/google/dragonegg/smihandler.c +++ b/src/mainboard/google/dragonegg/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc index 2fdd9d47f8..7aaf00da40 100644 --- a/src/mainboard/google/dragonegg/spd/Makefile.inc +++ b/src/mainboard/google/dragonegg/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc index 22736b9001..7a3ce63467 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c index 56f62193bd..fa27b74997 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c +++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h index 03096ac777..b697b6d8bf 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h index 99bbb71333..e083789e3c 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h index 37a7c053b7..6dcbd09f5a 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c index 3c458e800e..b383805391 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/memory.c +++ b/src/mainboard/google/dragonegg/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h index af41bf4008..bf2a7a65a8 100644 --- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h +++ b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h index ea1c708153..bcb87cb1d7 100644 --- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h +++ b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index 6f4f169f0e..d45b53a8cc 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/bootblock.c b/src/mainboard/google/drallion/bootblock.c index bee9b1ad7a..813409433b 100644 --- a/src/mainboard/google/drallion/bootblock.c +++ b/src/mainboard/google/drallion/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index c584bcbb4f..b75b63017c 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 33ede7a2b1..bc1eb0bd45 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/ec.c b/src/mainboard/google/drallion/ec.c index fd8e84fbc8..c0edf680c8 100644 --- a/src/mainboard/google/drallion/ec.c +++ b/src/mainboard/google/drallion/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/hda_verb.c b/src/mainboard/google/drallion/hda_verb.c index 9ab4778274..3fbc3a24c3 100644 --- a/src/mainboard/google/drallion/hda_verb.c +++ b/src/mainboard/google/drallion/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 385504522f..38dc133382 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index ed9923f990..ef64c3d155 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/smihandler.c b/src/mainboard/google/drallion/smihandler.c index 18dbfbc154..0dee122c91 100644 --- a/src/mainboard/google/drallion/smihandler.c +++ b/src/mainboard/google/drallion/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc index 9ab7394b30..4b400761f3 100644 --- a/src/mainboard/google/drallion/spd/Makefile.inc +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h index eb1d9aec48..1058dff22f 100644 --- a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index b584a91a27..8c9fc57e58 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index d26abdb2be..fe4fd3be3f 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl index 6f114b7c8b..c078b87c04 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index dbe487e8ac..225660be28 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h index 11e3be8404..7063927273 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index 219e0c4b37..98044fd47e 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h index d50fc1e34a..f62f417074 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index bf08ec30dc..74f6e5de3f 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index a56fb53a14..2509d561bb 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/sku.c b/src/mainboard/google/drallion/variants/drallion/sku.c index 736a14579a..24f4a117ae 100644 --- a/src/mainboard/google/drallion/variants/drallion/sku.c +++ b/src/mainboard/google/drallion/variants/drallion/sku.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/drallion/variants/drallion/smbios.c b/src/mainboard/google/drallion/variants/drallion/smbios.c index 45bd31d7b0..6d82af66cb 100644 --- a/src/mainboard/google/drallion/variants/drallion/smbios.c +++ b/src/mainboard/google/drallion/variants/drallion/smbios.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index ed1933ec55..f9be75a94e 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl index 7dd42492ef..ecda97f598 100644 --- a/src/mainboard/google/eve/acpi/dptf.asl +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index 5e92bb0e69..fc60230926 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 8b40dddeb2..c6b8cf37d4 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 5615e43e54..ea0424a219 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/ec.c b/src/mainboard/google/eve/ec.c index 893255ad47..2414475e22 100644 --- a/src/mainboard/google/eve/ec.c +++ b/src/mainboard/google/eve/ec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/ec.h b/src/mainboard/google/eve/ec.h index f7fea1448e..254a9ae0b5 100644 --- a/src/mainboard/google/eve/ec.h +++ b/src/mainboard/google/eve/ec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 2eb51bab8c..ca6c4152e9 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index aceb7b7f6d..37b4b673f3 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 7114715fbc..d3843df2d6 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/smihandler.c b/src/mainboard/google/eve/smihandler.c index 5bca488d7c..d5d8a28197 100644 --- a/src/mainboard/google/eve/smihandler.c +++ b/src/mainboard/google/eve/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc index cb4f8a8124..de94ad1a9f 100644 --- a/src/mainboard/google/eve/spd/Makefile.inc +++ b/src/mainboard/google/eve/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Google Inc. -## Copyright (C) 2016 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index fca670cbb9..5b83ce02b5 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 6d8d0a615c..8e8f614d0e 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 9721c45c7d..05557a602c 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl index f769a20317..6712860346 100644 --- a/src/mainboard/google/fizz/acpi/usb.asl +++ b/src/mainboard/google/fizz/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/bootblock.c b/src/mainboard/google/fizz/bootblock.c index ce669ccb38..fe2262c1d5 100644 --- a/src/mainboard/google/fizz/bootblock.c +++ b/src/mainboard/google/fizz/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index c57fa7e45b..7769ddc3f8 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index b847df6b97..0b891ced6d 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/ec.c b/src/mainboard/google/fizz/ec.c index 63a32a8c72..ec4ef983f2 100644 --- a/src/mainboard/google/fizz/ec.c +++ b/src/mainboard/google/fizz/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 89795f5eb3..6bb298b8d6 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 335662ef6d..7279ad5d84 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c index d20780c709..ae8b70196a 100644 --- a/src/mainboard/google/fizz/smihandler.c +++ b/src/mainboard/google/fizz/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index 4cd38652a2..d094e4cb7e 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl index f877c71c03..f98047dfd6 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h index a372f8dfb9..1fd85b2191 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h index f5bcc74f04..1778b81cbc 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h index 40dfeebc23..a1fbb83e8d 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/baseboard/nhlt.c b/src/mainboard/google/fizz/variants/baseboard/nhlt.c index 6918d9a5f1..1e43c79f9e 100644 --- a/src/mainboard/google/fizz/variants/baseboard/nhlt.c +++ b/src/mainboard/google/fizz/variants/baseboard/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 08cba211f1..0cde4f7520 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl index f1f09438fa..7d9006a068 100644 --- a/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h index 2463118648..51dffa5d34 100644 --- a/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h index 3edbe7b5c9..e37307225f 100644 --- a/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/endeavour/nhlt.c b/src/mainboard/google/fizz/variants/endeavour/nhlt.c index c047aea2f1..ede8213f0b 100644 --- a/src/mainboard/google/fizz/variants/endeavour/nhlt.c +++ b/src/mainboard/google/fizz/variants/endeavour/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl index a9afa73115..7d9006a068 100644 --- a/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h b/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h index 3d4fc8fa53..51dffa5d34 100644 --- a/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h b/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h index cd34cf060a..bcb87cb1d7 100644 --- a/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 0c775b696c..5e1ec222c9 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl index b170c39c66..7d9006a068 100644 --- a/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/karma/include/variant/ec.h b/src/mainboard/google/fizz/variants/karma/include/variant/ec.h index 0e96db8ddb..51dffa5d34 100644 --- a/src/mainboard/google/fizz/variants/karma/include/variant/ec.h +++ b/src/mainboard/google/fizz/variants/karma/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h b/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h index 20482b06f4..bcb87cb1d7 100644 --- a/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h +++ b/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/karma/nhlt.c b/src/mainboard/google/fizz/variants/karma/nhlt.c index df04167874..30e353ed71 100644 --- a/src/mainboard/google/fizz/variants/karma/nhlt.c +++ b/src/mainboard/google/fizz/variants/karma/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/fizz/variants/karma/smihandler.c b/src/mainboard/google/fizz/variants/karma/smihandler.c index 1bfae4dfe7..aa7a5bd1c7 100644 --- a/src/mainboard/google/fizz/variants/karma/smihandler.c +++ b/src/mainboard/google/fizz/variants/karma/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index eefc2c085b..efa9a4b82e 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc index f26358dc0f..342cd17556 100644 --- a/src/mainboard/google/foster/Makefile.inc +++ b/src/mainboard/google/foster/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. -## Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/bct/Makefile.inc b/src/mainboard/google/foster/bct/Makefile.inc index 37efa54e8b..463eece617 100644 --- a/src/mainboard/google/foster/bct/Makefile.inc +++ b/src/mainboard/google/foster/bct/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. -## Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/bct/cfg2inc.sh b/src/mainboard/google/foster/bct/cfg2inc.sh index 0d0369746c..d7b6c46495 100644 --- a/src/mainboard/google/foster/bct/cfg2inc.sh +++ b/src/mainboard/google/foster/bct/cfg2inc.sh @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright 2014 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/bct/emmc.cfg b/src/mainboard/google/foster/bct/emmc.cfg index 4b6b5d5672..be321cb1b5 100644 --- a/src/mainboard/google/foster/bct/emmc.cfg +++ b/src/mainboard/google/foster/bct/emmc.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2015 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00210001; diff --git a/src/mainboard/google/foster/bct/spi.cfg b/src/mainboard/google/foster/bct/spi.cfg index 2cf9e56da5..44cc88352d 100644 --- a/src/mainboard/google/foster/bct/spi.cfg +++ b/src/mainboard/google/foster/bct/spi.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2015 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00210001; diff --git a/src/mainboard/google/foster/boardid.c b/src/mainboard/google/foster/boardid.c index ed37babd7b..61c2e93be6 100644 --- a/src/mainboard/google/foster/boardid.c +++ b/src/mainboard/google/foster/boardid.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/bootblock.c b/src/mainboard/google/foster/bootblock.c index b13bf55840..1067c91266 100644 --- a/src/mainboard/google/foster/bootblock.c +++ b/src/mainboard/google/foster/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index dc7b738a87..aa9647f8aa 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/devicetree.cb b/src/mainboard/google/foster/devicetree.cb index 0255b5364a..33088dcba2 100644 --- a/src/mainboard/google/foster/devicetree.cb +++ b/src/mainboard/google/foster/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/mainboard.c b/src/mainboard/google/foster/mainboard.c index 14de42ef36..324b014fae 100644 --- a/src/mainboard/google/foster/mainboard.c +++ b/src/mainboard/google/foster/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index af6a364903..29e14ae4f7 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/pmic.h b/src/mainboard/google/foster/pmic.h index b4735bde95..584bb8dcc5 100644 --- a/src/mainboard/google/foster/pmic.h +++ b/src/mainboard/google/foster/pmic.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/reset.c b/src/mainboard/google/foster/reset.c index 60e8133776..305d8a3646 100644 --- a/src/mainboard/google/foster/reset.c +++ b/src/mainboard/google/foster/reset.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/romstage.c b/src/mainboard/google/foster/romstage.c index fa5ff71fed..e0f9a4317b 100644 --- a/src/mainboard/google/foster/romstage.c +++ b/src/mainboard/google/foster/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/foster/sdram_configs.c b/src/mainboard/google/foster/sdram_configs.c index 633a0bf7db..ca71bb78d6 100644 --- a/src/mainboard/google/foster/sdram_configs.c +++ b/src/mainboard/google/foster/sdram_configs.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index 81aaabf452..4f0d1ff125 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/Makefile.inc b/src/mainboard/google/gale/Makefile.inc index acdca2b920..fea77d2064 100644 --- a/src/mainboard/google/gale/Makefile.inc +++ b/src/mainboard/google/gale/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c index 2bc562a630..6cffaf8290 100644 --- a/src/mainboard/google/gale/blsp.c +++ b/src/mainboard/google/gale/blsp.c @@ -1,7 +1,6 @@ /* * This file is part of the depthcharge project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/mainboard/google/gale/boardid.c b/src/mainboard/google/gale/boardid.c index 082cc26876..027346a562 100644 --- a/src/mainboard/google/gale/boardid.c +++ b/src/mainboard/google/gale/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/bootblock.c b/src/mainboard/google/gale/bootblock.c index 63167cc620..d919839401 100644 --- a/src/mainboard/google/gale/bootblock.c +++ b/src/mainboard/google/gale/bootblock.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index 2b1d145d86..3f99a679bf 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 5c5a20c74a..0c0e2ddd51 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/devicetree.cb b/src/mainboard/google/gale/devicetree.cb index f34a309caf..92fdb4d11d 100644 --- a/src/mainboard/google/gale/devicetree.cb +++ b/src/mainboard/google/gale/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index 8025374efa..0282c70e99 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index 7ac8b9207a..94c5fa6e86 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/gale/mmu.h b/src/mainboard/google/gale/mmu.h index f7bffd26af..a07e4bc784 100644 --- a/src/mainboard/google/gale/mmu.h +++ b/src/mainboard/google/gale/mmu.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c index 1820ac9593..5da2f50af9 100644 --- a/src/mainboard/google/gale/reset.c +++ b/src/mainboard/google/gale/reset.c @@ -2,8 +2,6 @@ * * This file is part of the coreboot project. * - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/romstage.c b/src/mainboard/google/gale/romstage.c index c1b86541fb..cb5a493453 100644 --- a/src/mainboard/google/gale/romstage.c +++ b/src/mainboard/google/gale/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index 1edd8a7020..d7622d6efa 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index af43f7c495..371efaff95 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/acpi/dptf.asl b/src/mainboard/google/glados/acpi/dptf.asl index 0af7e9b94a..9a335098f9 100644 --- a/src/mainboard/google/glados/acpi/dptf.asl +++ b/src/mainboard/google/glados/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl index 5e7a1bad7c..b0dd43af70 100644 --- a/src/mainboard/google/glados/acpi/ec.asl +++ b/src/mainboard/google/glados/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index 22c7427514..b3e741a6d0 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/acpi/superio.asl b/src/mainboard/google/glados/acpi/superio.asl index dbfd3958f1..bd1bbd1e4c 100644 --- a/src/mainboard/google/glados/acpi/superio.asl +++ b/src/mainboard/google/glados/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/bootblock_mainboard.c b/src/mainboard/google/glados/bootblock_mainboard.c index dde7e8612a..6d1885ecb4 100644 --- a/src/mainboard/google/glados/bootblock_mainboard.c +++ b/src/mainboard/google/glados/bootblock_mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 5b340db9c5..3e9c90bc62 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index 270f3e0a4c..a0edabdccb 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index fbb2371449..879e888c4e 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c index 372237800e..f5329db526 100644 --- a/src/mainboard/google/glados/ec.c +++ b/src/mainboard/google/glados/ec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h index 2e383a9266..21a4ade540 100644 --- a/src/mainboard/google/glados/ec.h +++ b/src/mainboard/google/glados/ec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 516d7bae2a..1f5f6a8ea0 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 113d28bd50..4f9022b165 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index c10ae0e4d7..3d4d119715 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 324d3be866..13e1dbb339 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index c8e7b3304a..c28e3caf35 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/asuka/Makefile.inc b/src/mainboard/google/glados/variants/asuka/Makefile.inc index e8e2f237c1..a88ed7df53 100644 --- a/src/mainboard/google/glados/variants/asuka/Makefile.inc +++ b/src/mainboard/google/glados/variants/asuka/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. -## Copyright (C) 2015 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl index c2d2914d52..c57935ab1c 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index f477594bed..ea04abe530 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 75e0ea689d..4312dde3e6 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/caroline/Makefile.inc b/src/mainboard/google/glados/variants/caroline/Makefile.inc index 21b20e6912..eaa316e410 100644 --- a/src/mainboard/google/glados/variants/caroline/Makefile.inc +++ b/src/mainboard/google/glados/variants/caroline/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Google Inc. -## Copyright (C) 2016 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl index 064cd018e4..f6e1400d44 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl index d0324cf187..d4bc3507b4 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/ec.h b/src/mainboard/google/glados/variants/caroline/include/variant/ec.h index 955820c44c..04894b616e 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index d20252f7d0..1a74445b8f 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index 4338d55602..5757cd15a9 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc index f3b52c2398..65ae1b7d7f 100644 --- a/src/mainboard/google/glados/variants/cave/Makefile.inc +++ b/src/mainboard/google/glados/variants/cave/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Google Inc. -## Copyright (C) 2016 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl index 33b25a41ec..49321a65a5 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/cave/include/variant/ec.h b/src/mainboard/google/glados/variants/cave/include/variant/ec.h index f733bfbd70..dfd09fdd61 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index 6674b0edba..2961588ec3 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index d625f1700a..a3a62bb9a8 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/chell/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index 986bdd8552..1f3fadefb7 100644 --- a/src/mainboard/google/glados/variants/chell/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. -## Copyright (C) 2015 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl index ad370982ab..b3da88984b 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/chell/include/variant/ec.h b/src/mainboard/google/glados/variants/chell/include/variant/ec.h index be6c0a55d6..15b68189c4 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index ebece32f12..da30cbdfd5 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 892dbeed38..65ad017789 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/glados/Makefile.inc b/src/mainboard/google/glados/variants/glados/Makefile.inc index b6dbbd4562..8d7111d77e 100644 --- a/src/mainboard/google/glados/variants/glados/Makefile.inc +++ b/src/mainboard/google/glados/variants/glados/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. -## Copyright (C) 2015 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl index 85afd8c2bb..90af48b68e 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/glados/include/variant/ec.h b/src/mainboard/google/glados/variants/glados/include/variant/ec.h index 3c094b5cc6..ee4b415c66 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index aa5ca0be23..2d783ca5b1 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index d625f1700a..a3a62bb9a8 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/lars/Makefile.inc b/src/mainboard/google/glados/variants/lars/Makefile.inc index 5ee7410572..2772dd0c75 100644 --- a/src/mainboard/google/glados/variants/lars/Makefile.inc +++ b/src/mainboard/google/glados/variants/lars/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl index 1f464c5074..ca776edfff 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/lars/include/variant/ec.h b/src/mainboard/google/glados/variants/lars/include/variant/ec.h index 3c094b5cc6..ee4b415c66 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index a05c7022d8..1f390fc911 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index c24950d814..5717484a90 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/sentry/Makefile.inc b/src/mainboard/google/glados/variants/sentry/Makefile.inc index a60bcaedf0..778143f9ec 100644 --- a/src/mainboard/google/glados/variants/sentry/Makefile.inc +++ b/src/mainboard/google/glados/variants/sentry/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl index c9913737a2..2e99dd9da7 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/ec.h b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h index f56154bab9..fe31d0e653 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 600a3192c5..5864469f35 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index b77e5edc7f..126fc1515e 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 6cf165c395..819c448f15 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2016 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index 11100d7979..2526445d9b 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2016 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index acf3fb99a3..c29aa51d50 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index efba922e80..f3cda66604 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 79d9b0f640..b09542e266 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 05930dd148..3b2711e563 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb index 6f177edaf3..8da218e70f 100644 --- a/src/mainboard/google/gru/devicetree.cb +++ b/src/mainboard/google/gru/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2016 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb index c4417c594c..601af69161 100644 --- a/src/mainboard/google/gru/devicetree.scarlet.cb +++ b/src/mainboard/google/gru/devicetree.scarlet.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 4ebe143dea..7d3c1a79d5 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/memlayout.ld b/src/mainboard/google/gru/memlayout.ld index 04e3f6bc74..4b3e957339 100644 --- a/src/mainboard/google/gru/memlayout.ld +++ b/src/mainboard/google/gru/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 6c64990794..7f42f890e8 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/pwm_regulator.h b/src/mainboard/google/gru/pwm_regulator.h index 6ef0c59331..6e5160b15b 100644 --- a/src/mainboard/google/gru/pwm_regulator.h +++ b/src/mainboard/google/gru/pwm_regulator.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c index 5bf7260523..c84e33af93 100644 --- a/src/mainboard/google/gru/reset.c +++ b/src/mainboard/google/gru/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index 57c716590b..ba0c7066e4 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 5e9e15f1df..176e01c847 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/gru/sdram_params/Makefile.inc b/src/mainboard/google/gru/sdram_params/Makefile.inc index 68232b9b82..f01f354a26 100644 --- a/src/mainboard/google/gru/sdram_params/Makefile.inc +++ b/src/mainboard/google/gru/sdram_params/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 7ad7849b58..b430fa7c80 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c index 15dfe933eb..be773f260d 100644 --- a/src/mainboard/google/hatch/bootblock.c +++ b/src/mainboard/google/hatch/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 151977cd33..8d6cb57666 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 16a8a661b7..7ca266e2f9 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/ec.c b/src/mainboard/google/hatch/ec.c index 9fb3d80195..57241e3efd 100644 --- a/src/mainboard/google/hatch/ec.c +++ b/src/mainboard/google/hatch/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index e0e7a32456..17f233c7c3 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index e4de3a2174..005a1a9f70 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index a94fab5df9..b22ad8afb5 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 9073744850..3f91fd5916 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c index c7833e3900..51ace6d515 100644 --- a/src/mainboard/google/hatch/smihandler.c +++ b/src/mainboard/google/hatch/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc index 97a4dfdace..b67438b1e6 100644 --- a/src/mainboard/google/hatch/spd/Makefile.inc +++ b/src/mainboard/google/hatch/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/akemi/Makefile.inc b/src/mainboard/google/hatch/variants/akemi/Makefile.inc index c9627c449f..103d9e1990 100644 --- a/src/mainboard/google/hatch/variants/akemi/Makefile.inc +++ b/src/mainboard/google/hatch/variants/akemi/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index b141f02ef3..92041d63ff 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl index ae689d8072..f05d2c847d 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h index 768987d225..e2b5a5a94b 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h index b257589a0e..99d3f6d247 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 2965659dd8..93a28042e2 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc index 5d5695fe5f..13c45cbf45 100644 --- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -1,7 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 527bf93118..f149fe41e0 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index b18932ec6c..caa47a253d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index 3aa94144cb..c904be84f8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index 7bdd912a7b..14e0108a1b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index c780b973ff..34014a30d9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index bcfc49f20e..fb4864e668 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index 0d577cde51..ada9a960c9 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index e3b3d8a23a..25ba729bb4 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl index 21498b9d73..aa7aeafc9b 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h index 768987d225..e2b5a5a94b 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h index 92f9d412fd..99d3f6d247 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h index a9a50e499a..5766b79f12 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/ramstage.c b/src/mainboard/google/hatch/variants/dratini/ramstage.c index 9b919fccd8..20ae7e35cb 100644 --- a/src/mainboard/google/hatch/variants/dratini/ramstage.c +++ b/src/mainboard/google/hatch/variants/dratini/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/dratini/variant.c b/src/mainboard/google/hatch/variants/dratini/variant.c index bda30dfb2a..04a305f0eb 100644 --- a/src/mainboard/google/hatch/variants/dratini/variant.c +++ b/src/mainboard/google/hatch/variants/dratini/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index 4bf640a7f4..77cb535095 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 2c4fa50cd6..6ff3cc7395 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl index 31f72b3f03..7d9006a068 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h index c36f957737..e2b5a5a94b 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h index e7d8a75937..89e64fbe3a 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c index 5459f55cd1..b1ab80c130 100644 --- a/src/mainboard/google/hatch/variants/hatch/ramstage.c +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index be074b770d..acf6a751d6 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index afe1c85160..ac0f88686f 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index f40d10abf8..e918718650 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/ec.h b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h index 768987d225..e2b5a5a94b 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h index 92f9d412fd..99d3f6d247 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/helios/memory.c b/src/mainboard/google/hatch/variants/helios/memory.c index a3cd813f09..2a8971ecac 100644 --- a/src/mainboard/google/hatch/variants/helios/memory.c +++ b/src/mainboard/google/hatch/variants/helios/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/helios/ramstage.c b/src/mainboard/google/hatch/variants/helios/ramstage.c index 9b919fccd8..20ae7e35cb 100644 --- a/src/mainboard/google/hatch/variants/helios/ramstage.c +++ b/src/mainboard/google/hatch/variants/helios/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index d38a5771bb..0803710802 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index c584d94443..2e09488078 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl index ffa7590c3b..4f440e50e1 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h index 768987d225..e2b5a5a94b 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h index 92f9d412fd..99d3f6d247 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h index 1d45fcddcd..fddc42be0b 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index db041c4ca8..07775855e4 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/jinlon/ramstage.c b/src/mainboard/google/hatch/variants/jinlon/ramstage.c index 9b919fccd8..20ae7e35cb 100644 --- a/src/mainboard/google/hatch/variants/jinlon/ramstage.c +++ b/src/mainboard/google/hatch/variants/jinlon/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc index 8b7e3d1014..6f8d94be3f 100644 --- a/src/mainboard/google/hatch/variants/kindred/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index f53b91be2b..7ce62f0daa 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl index 43c1b08508..def0df4c27 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h index 768987d225..e2b5a5a94b 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h index 92f9d412fd..99d3f6d247 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index f26486844c..72bed92398 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index 3fb352dbf5..ea2a901f68 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 91ade86b32..d98a25cdd4 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl index 13a501a29e..756f8aacb4 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index 377b703cdd..f17fbc1dee 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h index 29e590422f..89e64fbe3a 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c index 490124776e..4d111e2844 100644 --- a/src/mainboard/google/hatch/variants/kohaku/memory.c +++ b/src/mainboard/google/hatch/variants/kohaku/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c index 9b919fccd8..20ae7e35cb 100644 --- a/src/mainboard/google/hatch/variants/kohaku/ramstage.c +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index 4bf640a7f4..77cb535095 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index fd12eb0e52..e01d1b4d48 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl index 31f72b3f03..7d9006a068 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h index 768987d225..e2b5a5a94b 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h index 29e590422f..89e64fbe3a 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c index 5459f55cd1..b1ab80c130 100644 --- a/src/mainboard/google/hatch/variants/mushu/ramstage.c +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc index f46b7b0bcf..f44654a8f6 100644 --- a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2020 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index 681f9ecde2..6c9c40e0dd 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl index edfad4b8bc..756f8aacb4 100644 --- a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h index 5b321a33a8..f17fbc1dee 100644 --- a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h index 2193c7b2f7..99d3f6d247 100644 --- a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/nightfury/memory.c b/src/mainboard/google/hatch/variants/nightfury/memory.c index 7e1594c47e..358982efff 100644 --- a/src/mainboard/google/hatch/variants/nightfury/memory.c +++ b/src/mainboard/google/hatch/variants/nightfury/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c index 44cd89b00e..2201efded3 100644 --- a/src/mainboard/google/hatch/variants/nightfury/ramstage.c +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/palkia/Makefile.inc b/src/mainboard/google/hatch/variants/palkia/Makefile.inc index b0a69da366..50287002a5 100644 --- a/src/mainboard/google/hatch/variants/palkia/Makefile.inc +++ b/src/mainboard/google/hatch/variants/palkia/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Palkia. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index 73868f7246..67d070a537 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Palkia. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl index c9b4fb3421..6b6c06aa79 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Palkia. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h index 454c8d01f2..b0a0c0a919 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Palkia. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h index aaf6f4d433..afe5145d5b 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Palkia. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c index 1a4bf383e0..05a7fa8afc 100644 --- a/src/mainboard/google/hatch/variants/palkia/memory.c +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Palkia. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc index 2d1440e3ac..8cbad31648 100644 --- a/src/mainboard/google/hatch/variants/puff/Makefile.inc +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -1,6 +1,5 @@ ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c index 57327fed9a..d1465fe9fa 100644 --- a/src/mainboard/google/hatch/variants/puff/gpio.c +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 0746c5e6d4..9a3c64e5b0 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h index d99e2bbd65..40e13ebd77 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index 7354ce92cc..7dcd8c756c 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 82ffb6cb61..58511cae1e 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index ed7177617b..777974cee6 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/acpi/mainboard.asl b/src/mainboard/google/jecht/acpi/mainboard.asl index bf6070e81f..e9ba368fde 100644 --- a/src/mainboard/google/jecht/acpi/mainboard.asl +++ b/src/mainboard/google/jecht/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/jecht/acpi/platform.asl b/src/mainboard/google/jecht/acpi/platform.asl index fee0670b1d..665f79f968 100644 --- a/src/mainboard/google/jecht/acpi/platform.asl +++ b/src/mainboard/google/jecht/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/acpi/superio.asl b/src/mainboard/google/jecht/acpi/superio.asl index b773d7af4e..623f4e63fb 100644 --- a/src/mainboard/google/jecht/acpi/superio.asl +++ b/src/mainboard/google/jecht/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 48b7a36797..937b68de13 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c index 43725cd747..2bb93f5496 100644 --- a/src/mainboard/google/jecht/bootblock.c +++ b/src/mainboard/google/jecht/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index b16e325b38..6f8c7a5212 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index c948969231..a0edabdccb 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index eb1c097287..fc86907a33 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index a24cf52134..6afc8e23c0 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 0b0127e2b5..abb798e430 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index bd08b0916b..0a9c6eaaa6 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index 9c3878f3cf..5af12b478a 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index 0a827c6067..2a8a7fc645 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index fba132377c..284ae399af 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 4e32ab227b..cf8465bd48 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index f324813337..337cf43fff 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/spd/Makefile.inc b/src/mainboard/google/jecht/spd/Makefile.inc index 275d9836dd..cc9726f5fb 100644 --- a/src/mainboard/google/jecht/spd/Makefile.inc +++ b/src/mainboard/google/jecht/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 25409644d3..c9284b4bd4 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/spd/spd.h b/src/mainboard/google/jecht/spd/spd.h index 02709cd5fe..d7ba63bce3 100644 --- a/src/mainboard/google/jecht/spd/spd.h +++ b/src/mainboard/google/jecht/spd/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/guado/gpio.c b/src/mainboard/google/jecht/variants/guado/gpio.c index 60e769dbd0..e2be9a20d6 100644 --- a/src/mainboard/google/jecht/variants/guado/gpio.c +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl index fcf5a38113..0782df1bcc 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h index d299b14d08..58f841399b 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 87ca1dc0c6..3908969ff7 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/jecht/gpio.c b/src/mainboard/google/jecht/variants/jecht/gpio.c index 6a2a64cd7b..968bb4efb1 100644 --- a/src/mainboard/google/jecht/variants/jecht/gpio.c +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl index fcf5a38113..0782df1bcc 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h index 29559eb754..350f66e932 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index 87ca1dc0c6..3908969ff7 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/rikku/gpio.c b/src/mainboard/google/jecht/variants/rikku/gpio.c index bc065a03a1..e2be9a20d6 100644 --- a/src/mainboard/google/jecht/variants/rikku/gpio.c +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl index 2cacc031cd..0782df1bcc 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h index b9144531e1..3266f2d5de 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index 14f96767fd..3908969ff7 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/tidus/gpio.c b/src/mainboard/google/jecht/variants/tidus/gpio.c index 78aa177679..7c4631b24a 100644 --- a/src/mainboard/google/jecht/variants/tidus/gpio.c +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl index 3feec34c5a..7793463f27 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h index 4236424a35..45a3ffd629 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index b7974ea774..03889e5222 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index 7f7e575794..d9d51c9820 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index b46c1f6d83..85384dc019 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 0abd8840ec..097566c1e5 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 8e5d8eb5b1..f39f946714 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index e403684a41..805793d049 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 3be023edfc..f02092883e 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 4a3a8ece88..7e83f06710 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 1080902702..cb4723b456 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/irq_tables.c b/src/mainboard/google/kahlee/irq_tables.c index b134c6bac0..b6dfd5d60b 100644 --- a/src/mainboard/google/kahlee/irq_tables.c +++ b/src/mainboard/google/kahlee/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 42a82d4f30..9650298d53 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index 5bb70e9449..130a728483 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index ebe59ac77f..bfadb5c6f2 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c index 6e823bfa8b..a13dc6c597 100644 --- a/src/mainboard/google/kahlee/smihandler.c +++ b/src/mainboard/google/kahlee/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc index 0579e1899f..0346f39c5a 100644 --- a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Google, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 3dc2c2aabc..cf0978fa5f 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h index 3ddabb1f27..b9f1e45c25 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h index 1bb78efa2a..b04194fb52 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index 88ab91a3c0..efcf35de0f 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2018 Google LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 42d9a49c7e..ab128c556b 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 4c2483f1b0..f21a97f845 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 9b88cdd517..0084325102 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl index dc7c804faa..c2be6f320e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl index 8bee63af58..c118337c04 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl index 585c0154cc..fd760f4686 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl index 13c111e20b..2dbefb9931 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl index 86f8758892..54b7d4e4d4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h index ae648b5308..2d8d348df1 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h index be1daa5b15..f1de4abe80 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index e3cde3ef17..348f24f9b1 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 69b9b40f8d..95cbd911e0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 67402fb585..23d0f7974b 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/romstage.c b/src/mainboard/google/kahlee/variants/baseboard/romstage.c index e716f6f55b..cbb4d3054d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/romstage.c +++ b/src/mainboard/google/kahlee/variants/baseboard/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc index b6a57b73ba..bc3f6b6879 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c index fe5e42c4ad..b3c6fd5450 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index 17ea78eee0..3dfc57c491 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Google, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 3387b6f40b..ac07aa1e93 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h index 5a6b54044f..bc01d14833 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h index 1bb78efa2a..b04194fb52 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc index e764bafb27..8deec06321 100644 --- a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc index 0579e1899f..0346f39c5a 100644 --- a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Google, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index a0a1876c3c..18053d782f 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl index 0a08774206..750254f4ad 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl index 4f91d72822..01d015c89e 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl index 233494f51e..95b37951c2 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl index c5a1557962..ca791f011e 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl index 77137bb903..cf0aee679f 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h index 5a6b54044f..bc01d14833 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h index 1bb78efa2a..b04194fb52 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/liara/Makefile.inc b/src/mainboard/google/kahlee/variants/liara/Makefile.inc index 0579e1899f..0346f39c5a 100644 --- a/src/mainboard/google/kahlee/variants/liara/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/liara/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Google, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 30028275c8..7dd34f3465 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h index 5a6b54044f..bc01d14833 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h index 1bb78efa2a..b04194fb52 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc index 3753268749..8823259bd7 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2020 Google, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index 689e6042d7..6828d363c3 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl index 7a1e74b2d9..750254f4ad 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl index acb906e0bc..01d015c89e 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl index 283e332849..95b37951c2 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl index b69f063bbd..ca791f011e 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl index 56a4da466b..cf0aee679f 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h index 4a63722e9e..89c53be8f1 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h index ebd7c5be5a..b9f1e45c25 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h index 1bb78efa2a..b04194fb52 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c index 42dbe031f6..cf10d8f2dd 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c +++ b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc index a2d0d2fc9f..307b499b50 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index a8ef4baab3..8823259bd7 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Google, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 6c953b1af4..f92767ff27 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl index 0a08774206..750254f4ad 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl index 4f91d72822..01d015c89e 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl index 233494f51e..95b37951c2 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl index c5a1557962..ca791f011e 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl index 77137bb903..cf0aee679f 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h index 2d48018ee5..89c53be8f1 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h index 3ddabb1f27..b9f1e45c25 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h index 1bb78efa2a..b04194fb52 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c index cd42b563e3..cf10d8f2dd 100644 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc index a2d0d2fc9f..307b499b50 100644 --- a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 6236ea9f8a..82845a8d0d 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2019 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index ad7fb364df..1b610ed333 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 61f30aff44..38eb1d757b 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index b001c81d8c..240a0cf571 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/devicetree.cb b/src/mainboard/google/kukui/devicetree.cb index e2f2be34a2..f11ca45a0e 100644 --- a/src/mainboard/google/kukui/devicetree.cb +++ b/src/mainboard/google/kukui/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 MediaTek Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index 7eee080412..4d257f2418 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/early_init.h b/src/mainboard/google/kukui/early_init.h index a849fe835a..3ec00f35d8 100644 --- a/src/mainboard/google/kukui/early_init.h +++ b/src/mainboard/google/kukui/early_init.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index 977acc3739..72d72d7022 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 844496d7a0..5bf9121821 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/memlayout.ld b/src/mainboard/google/kukui/memlayout.ld index f10e55b7bf..9572a5ef8f 100644 --- a/src/mainboard/google/kukui/memlayout.ld +++ b/src/mainboard/google/kukui/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel.h b/src/mainboard/google/kukui/panel.h index 0156cd68bf..5f073e7c47 100644 --- a/src/mainboard/google/kukui/panel.h +++ b/src/mainboard/google/kukui/panel.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index b6a57e4c14..8a7889806f 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_flapjack.c b/src/mainboard/google/kukui/panel_flapjack.c index b10cc709a7..ce668e7769 100644 --- a/src/mainboard/google/kukui/panel_flapjack.c +++ b/src/mainboard/google/kukui/panel_flapjack.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_kakadu.c b/src/mainboard/google/kukui/panel_kakadu.c index 3cb18ba918..08b9c228e9 100644 --- a/src/mainboard/google/kukui/panel_kakadu.c +++ b/src/mainboard/google/kukui/panel_kakadu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Bitland Tech Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_kodama.c b/src/mainboard/google/kukui/panel_kodama.c index 033e469964..c18ee74ff0 100644 --- a/src/mainboard/google/kukui/panel_kodama.c +++ b/src/mainboard/google/kukui/panel_kodama.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Bitland Tech Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c index 4694e49485..ba30505deb 100644 --- a/src/mainboard/google/kukui/panel_krane.c +++ b/src/mainboard/google/kukui/panel_krane.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c index bca5c6ef26..4162326c75 100644 --- a/src/mainboard/google/kukui/panel_kukui.c +++ b/src/mainboard/google/kukui/panel_kukui.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c b/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c index a3da2a8876..ed9026a52b 100644 --- a/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Bitland Tech Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c b/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c index 924b566fbd..7c8e251b7d 100644 --- a/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c b/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c index 8fca7df162..f9b5b5443f 100644 --- a/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c index 5e56eb9ac0..e096e161ba 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c index 10753d960f..0ec9534a5e 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Bitland Tech Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c index bb4452ed90..8a54d07e49 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c index 928f7fecb9..dea16ef82a 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c index 45068839ff..8d09a9641a 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Bitland Tech Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c b/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c index f9523358f7..f17cfbf9f9 100644 --- a/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c +++ b/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c b/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c index 069fb639e5..a615481198 100644 --- a/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c +++ b/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Huaqin Telecom Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c index 6381228c09..5d8fe0caec 100644 --- a/src/mainboard/google/kukui/panel_ps8640.c +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/reset.c b/src/mainboard/google/kukui/reset.c index 609ecb4c1a..a13007b2ce 100644 --- a/src/mainboard/google/kukui/reset.c +++ b/src/mainboard/google/kukui/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 2b7dd6a20c..aae4529529 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index b6277eaebf..5ed10958b4 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index 5471f0154f..8ff616be0b 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 5743304bc9..91706de19c 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index de06818460..8b200546ec 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index fb83e6f418..0a239a8cd1 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 415dbda827..2090904365 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index bf3fe892c3..1f210e7dfe 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index e5b3dcc990..49a93c101f 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index cb923f5551..80c5c5188d 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/kukui/verstage.c b/src/mainboard/google/kukui/verstage.c index c12d1b66d0..fa46fcab9e 100644 --- a/src/mainboard/google/kukui/verstage.c +++ b/src/mainboard/google/kukui/verstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 22c28c8059..9152656415 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/acpi/ec.asl b/src/mainboard/google/link/acpi/ec.asl index f94d8caccb..a8f46ec81a 100644 --- a/src/mainboard/google/link/acpi/ec.asl +++ b/src/mainboard/google/link/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl index 79c45c8622..c4fb708e15 100644 --- a/src/mainboard/google/link/acpi/mainboard.asl +++ b/src/mainboard/google/link/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl index 5c4a6da6c9..794d525d81 100644 --- a/src/mainboard/google/link/acpi/platform.asl +++ b/src/mainboard/google/link/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/acpi/superio.asl b/src/mainboard/google/link/acpi/superio.asl index 266a67c6b8..98edbd97ea 100644 --- a/src/mainboard/google/link/acpi/superio.asl +++ b/src/mainboard/google/link/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl index d1b3255010..abe72cd4a0 100644 --- a/src/mainboard/google/link/acpi/thermal.asl +++ b/src/mainboard/google/link/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index 891151a4cb..b7765780cd 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index f7f39de6c8..b6d00f9bcd 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index 36506dfeda..615ff29dce 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index 18c7fc5681..2596de25ba 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 7d1c177d92..d3e9a60e0b 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 37949f6855..9ee98a845a 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/ec.h b/src/mainboard/google/link/ec.h index 1235d58f58..a2755327b8 100644 --- a/src/mainboard/google/link/ec.h +++ b/src/mainboard/google/link/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c index 035cf6da3f..212bf5b1d7 100644 --- a/src/mainboard/google/link/gpio.c +++ b/src/mainboard/google/link/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/hda_verb.c b/src/mainboard/google/link/hda_verb.c index 11c92a9ed6..302ee7224e 100644 --- a/src/mainboard/google/link/hda_verb.c +++ b/src/mainboard/google/link/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 32e5487278..4551be8125 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index cd8fb092dd..7dce4cbbd2 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index 7bc213b8e0..cd673ec08c 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/link/thermal.h b/src/mainboard/google/link/thermal.h index 4a1f31b505..2b7b957918 100644 --- a/src/mainboard/google/link/thermal.h +++ b/src/mainboard/google/link/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index 4ef8fec6c3..d4446864b2 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 538e46fa4b..c92be26fdb 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 4d5f666ce8..44a463b749 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018, The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/devicetree.cb b/src/mainboard/google/mistral/devicetree.cb index 977f4c68d9..337a20ec8c 100644 --- a/src/mainboard/google/mistral/devicetree.cb +++ b/src/mainboard/google/mistral/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018, The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 4a109f13d7..13c9cb27e1 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/memlayout.ld b/src/mainboard/google/mistral/memlayout.ld index cbabf2ee37..174ae545fa 100644 --- a/src/mainboard/google/mistral/memlayout.ld +++ b/src/mainboard/google/mistral/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/reset.c b/src/mainboard/google/mistral/reset.c index 107e79c888..f3deb44306 100644 --- a/src/mainboard/google/mistral/reset.c +++ b/src/mainboard/google/mistral/reset.c @@ -2,8 +2,6 @@ * * This file is part of the coreboot project. * - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 41ee4edcbb..ccba032223 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c index a34e4fa361..19d9eb3ea3 100644 --- a/src/mainboard/google/mistral/verstage.c +++ b/src/mainboard/google/mistral/verstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index cc649e6e40..3dc552020e 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 408763a4b8..463747d9c4 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc index ded6ff3a44..311f34c7ef 100644 --- a/src/mainboard/google/nyan/bct/Makefile.inc +++ b/src/mainboard/google/nyan/bct/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/bct/cfg2inc.sh b/src/mainboard/google/nyan/bct/cfg2inc.sh index 0d0369746c..d7b6c46495 100755 --- a/src/mainboard/google/nyan/bct/cfg2inc.sh +++ b/src/mainboard/google/nyan/bct/cfg2inc.sh @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright 2014 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/bct/emmc.cfg b/src/mainboard/google/nyan/bct/emmc.cfg index be8f79fd07..f146b64bdc 100644 --- a/src/mainboard/google/nyan/bct/emmc.cfg +++ b/src/mainboard/google/nyan/bct/emmc.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00350001; diff --git a/src/mainboard/google/nyan/bct/spi.cfg b/src/mainboard/google/nyan/bct/spi.cfg index 7d05363446..05f6e6b8b6 100644 --- a/src/mainboard/google/nyan/bct/spi.cfg +++ b/src/mainboard/google/nyan/bct/spi.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00350001; diff --git a/src/mainboard/google/nyan/boardid.c b/src/mainboard/google/nyan/boardid.c index 57b75da24d..cf3b28173b 100644 --- a/src/mainboard/google/nyan/boardid.c +++ b/src/mainboard/google/nyan/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index 2c969dd913..bb8e60ed88 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 710c9e1381..be43119df1 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index ae4f5bc1f7..015a84c779 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/early_configs.c b/src/mainboard/google/nyan/early_configs.c index 8e190d70ce..61afa28472 100644 --- a/src/mainboard/google/nyan/early_configs.c +++ b/src/mainboard/google/nyan/early_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 7fa47bbcb5..1022d3aedf 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index 75b888865b..527aae3223 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h index 639725e431..1a95e2a9f1 100644 --- a/src/mainboard/google/nyan/pmic.h +++ b/src/mainboard/google/nyan/pmic.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c index 468b0c2599..d29514e1e7 100644 --- a/src/mainboard/google/nyan/reset.c +++ b/src/mainboard/google/nyan/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 5cc7f6eef1..d18eb3d4cf 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c index a09a4f6b16..b4a3954721 100644 --- a/src/mainboard/google/nyan/sdram_configs.c +++ b/src/mainboard/google/nyan/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan/sdram_configs.h b/src/mainboard/google/nyan/sdram_configs.h index 1b5091fe96..590ff9db54 100644 --- a/src/mainboard/google/nyan/sdram_configs.h +++ b/src/mainboard/google/nyan/sdram_configs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 87e39aa755..14a28cd7b8 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index eb70157b92..d6729a108b 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/bct/Makefile.inc b/src/mainboard/google/nyan_big/bct/Makefile.inc index baba65bca3..b918e15fc5 100644 --- a/src/mainboard/google/nyan_big/bct/Makefile.inc +++ b/src/mainboard/google/nyan_big/bct/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/bct/emmc.cfg b/src/mainboard/google/nyan_big/bct/emmc.cfg index c93cf4685b..f146b64bdc 100644 --- a/src/mainboard/google/nyan_big/bct/emmc.cfg +++ b/src/mainboard/google/nyan_big/bct/emmc.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00350001; diff --git a/src/mainboard/google/nyan_big/bct/spi.cfg b/src/mainboard/google/nyan_big/bct/spi.cfg index c84fe81908..05f6e6b8b6 100644 --- a/src/mainboard/google/nyan_big/bct/spi.cfg +++ b/src/mainboard/google/nyan_big/bct/spi.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00350001; diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 49a9938cbb..d859b3f56e 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c index e5234fbf38..bb8e60ed88 100644 --- a/src/mainboard/google/nyan_big/bootblock.c +++ b/src/mainboard/google/nyan_big/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 697b7b1e44..be43119df1 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb index ae4f5bc1f7..015a84c779 100644 --- a/src/mainboard/google/nyan_big/devicetree.cb +++ b/src/mainboard/google/nyan_big/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/early_configs.c b/src/mainboard/google/nyan_big/early_configs.c index 8e190d70ce..61afa28472 100644 --- a/src/mainboard/google/nyan_big/early_configs.c +++ b/src/mainboard/google/nyan_big/early_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 115f73aa1e..0f42309544 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index 0564f3d597..0faffa5b13 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/pmic.h b/src/mainboard/google/nyan_big/pmic.h index e4fbb8d56c..2dd6a627e8 100644 --- a/src/mainboard/google/nyan_big/pmic.h +++ b/src/mainboard/google/nyan_big/pmic.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c index 468b0c2599..d29514e1e7 100644 --- a/src/mainboard/google/nyan_big/reset.c +++ b/src/mainboard/google/nyan_big/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 5cc7f6eef1..d18eb3d4cf 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c index 6f792d0ace..e3b6da8d28 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.c +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_big/sdram_configs.h b/src/mainboard/google/nyan_big/sdram_configs.h index 5be4ed35e9..99e37a14a8 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.h +++ b/src/mainboard/google/nyan_big/sdram_configs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 82a28ed421..35bd69190a 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index e5f15365db..c5d6a10a6f 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/bct/Makefile.inc b/src/mainboard/google/nyan_blaze/bct/Makefile.inc index 795561fe0a..d098a6ed75 100644 --- a/src/mainboard/google/nyan_blaze/bct/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/bct/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/bct/emmc.cfg b/src/mainboard/google/nyan_blaze/bct/emmc.cfg index c93cf4685b..f146b64bdc 100644 --- a/src/mainboard/google/nyan_blaze/bct/emmc.cfg +++ b/src/mainboard/google/nyan_blaze/bct/emmc.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00350001; diff --git a/src/mainboard/google/nyan_blaze/bct/spi.cfg b/src/mainboard/google/nyan_blaze/bct/spi.cfg index c84fe81908..05f6e6b8b6 100644 --- a/src/mainboard/google/nyan_blaze/bct/spi.cfg +++ b/src/mainboard/google/nyan_blaze/bct/spi.cfg @@ -1,4 +1,3 @@ -# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00350001; diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 49a9938cbb..d859b3f56e 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/bootblock.c b/src/mainboard/google/nyan_blaze/bootblock.c index e5234fbf38..bb8e60ed88 100644 --- a/src/mainboard/google/nyan_blaze/bootblock.c +++ b/src/mainboard/google/nyan_blaze/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 697b7b1e44..be43119df1 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb index ae4f5bc1f7..015a84c779 100644 --- a/src/mainboard/google/nyan_blaze/devicetree.cb +++ b/src/mainboard/google/nyan_blaze/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/early_configs.c b/src/mainboard/google/nyan_blaze/early_configs.c index 8e190d70ce..61afa28472 100644 --- a/src/mainboard/google/nyan_blaze/early_configs.c +++ b/src/mainboard/google/nyan_blaze/early_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index d57ac8bdd8..9e2b65d361 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index 0564f3d597..0faffa5b13 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/pmic.h b/src/mainboard/google/nyan_blaze/pmic.h index 02b3e81a9c..df8bca0eb1 100644 --- a/src/mainboard/google/nyan_blaze/pmic.h +++ b/src/mainboard/google/nyan_blaze/pmic.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c index 468b0c2599..d29514e1e7 100644 --- a/src/mainboard/google/nyan_blaze/reset.c +++ b/src/mainboard/google/nyan_blaze/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 7a1b5fa98a..bdc4f71b97 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index b4f2a8e07e..03d6cada99 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.h b/src/mainboard/google/nyan_blaze/sdram_configs.h index 2a2025b411..0bc402e735 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.h +++ b/src/mainboard/google/nyan_blaze/sdram_configs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index dc12816d6c..d1c5a9e211 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 MediaTek Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index aa7abc27f0..b6998528a7 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 MediaTek Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c index ada2de5041..dc8678a10d 100644 --- a/src/mainboard/google/oak/boardid.c +++ b/src/mainboard/google/oak/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 73e50fda63..a53192f89f 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index c0b25718d2..cdfe5fa545 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/devicetree.cb b/src/mainboard/google/oak/devicetree.cb index ed21df26c6..be8698996f 100644 --- a/src/mainboard/google/oak/devicetree.cb +++ b/src/mainboard/google/oak/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 MediaTek Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index 13636c7b0b..6b95c63ddf 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 4b3cc01763..ae340ed650 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index 754c40ce66..c3230b54ba 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index 34191082ca..a8ad5d91c9 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/oak/tpm_tis.c b/src/mainboard/google/oak/tpm_tis.c index 303cfc72b4..4ab14f2bd9 100644 --- a/src/mainboard/google/oak/tpm_tis.c +++ b/src/mainboard/google/oak/tpm_tis.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/bootblock.c b/src/mainboard/google/octopus/bootblock.c index 4da3e94b83..5f1b34e829 100644 --- a/src/mainboard/google/octopus/bootblock.c +++ b/src/mainboard/google/octopus/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 795dcb1718..9fd0d02ff3 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index b19390913b..294e350a71 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/ec.c b/src/mainboard/google/octopus/ec.c index 469980687c..17b7418739 100644 --- a/src/mainboard/google/octopus/ec.c +++ b/src/mainboard/google/octopus/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 0ab4693bfc..6dc661dc3f 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index d878d0d33f..4fcfd21764 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index 855c9825e8..aa7b04d979 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c index 6044cd2785..bf02cc6f28 100644 --- a/src/mainboard/google/octopus/variants/ampton/gpio.c +++ b/src/mainboard/google/octopus/variants/ampton/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl index cc17d560cf..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h index b75794a124..2183187b61 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h index a59bbf4a9e..c2f559210c 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 6f685227c4..1a40eb531a 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl index 363effa89c..7d504bdc97 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index e86dc2db80..73d7a4ee80 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h index b40840377f..de3e11f253 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index bf08a8588d..8bcb5a920a 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index 233ef84b80..990872ece7 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index 914f71c50d..8d6542bf1c 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c index cf3bc4caf7..716344f698 100644 --- a/src/mainboard/google/octopus/variants/bloog/gpio.c +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl index 4f6497ab2d..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h b/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h index feb6c71655..4d96aec700 100644 --- a/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h b/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h index 750b0d4ccc..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 05a1542d9a..98879504fc 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index dd1084099a..5500d7dd47 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl index cc17d560cf..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h index 196d52e3e9..4d96aec700 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h b/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h index 1fd1e11716..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 03eacbfe5d..d1b66ea5fa 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index 3a9a4410cb..c0d6feb05b 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl index cc17d560cf..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/ec.h b/src/mainboard/google/octopus/variants/casta/include/variant/ec.h index 16f931b6cd..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/casta/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h b/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h index 1fd1e11716..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/casta/variant.c b/src/mainboard/google/octopus/variants/casta/variant.c index 4b1e42d9c3..90a8e524af 100644 --- a/src/mainboard/google/octopus/variants/casta/variant.c +++ b/src/mainboard/google/octopus/variants/casta/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 3d09a39efd..96050cd293 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 The coreboot project Authors. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl index 1406d3488f..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 The coreboot project Authors. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/ec.h b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h index a8640cd186..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/dood/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 The coreboot project Authors. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h index d7e9ddb6fb..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 The coreboot project Authors. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index b54b9fa084..e22c2e4657 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 5924fa03a0..6a0e1e8b32 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl index d5943c7e41..93b60a3736 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h index 16f931b6cd..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h b/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h index 1fd1e11716..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/foob/gpio.c b/src/mainboard/google/octopus/variants/foob/gpio.c index 55f8196dbc..0fc034a9a6 100644 --- a/src/mainboard/google/octopus/variants/foob/gpio.c +++ b/src/mainboard/google/octopus/variants/foob/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl index 4f6497ab2d..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/ec.h b/src/mainboard/google/octopus/variants/foob/include/variant/ec.h index 260d7d43b2..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/foob/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/foob/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h b/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h index 750b0d4ccc..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/foob/variant.c b/src/mainboard/google/octopus/variants/foob/variant.c index d5d76585d9..e5fd0679e3 100644 --- a/src/mainboard/google/octopus/variants/foob/variant.c +++ b/src/mainboard/google/octopus/variants/foob/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 987c69e7bd..9da8ace50d 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl index 4f6497ab2d..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/ec.h b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h index feb6c71655..4d96aec700 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h index 750b0d4ccc..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index 432f3c54cd..72acceba78 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 2afceb9b41..55dcff7866 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c index d0599826b4..c74a74464a 100644 --- a/src/mainboard/google/octopus/variants/lick/gpio.c +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl index 4f6497ab2d..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h index 260d7d43b2..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h index 750b0d4ccc..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index ed4eb059bf..59497e4f42 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl index cc17d560cf..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h index 196d52e3e9..4d96aec700 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h index 1fd1e11716..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h index c3a18c4452..269152d2f3 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index 7cd1e472bf..ed46885dc9 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl index f3ff04b5e9..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h b/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h index 586f1064f4..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h b/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h index 6d1ce5a0e4..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 281bde06a4..4d1678d2fb 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl index cc17d560cf..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h index 16f931b6cd..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h b/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h index 1fd1e11716..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/phaser/mainboard.c b/src/mainboard/google/octopus/variants/phaser/mainboard.c index 2d44830661..2239aa2eb8 100644 --- a/src/mainboard/google/octopus/variants/phaser/mainboard.c +++ b/src/mainboard/google/octopus/variants/phaser/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/phaser/variant.c b/src/mainboard/google/octopus/variants/phaser/variant.c index aeefda54bc..ef06106c30 100644 --- a/src/mainboard/google/octopus/variants/phaser/variant.c +++ b/src/mainboard/google/octopus/variants/phaser/variant.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index 571988868f..ffc7e4a63f 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl index cc17d560cf..2e6e9feadf 100644 --- a/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h b/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h index 16f931b6cd..87f03b1ece 100644 --- a/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h b/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h index 1fd1e11716..3777fed07b 100644 --- a/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index a2ed11e580..15adb811fa 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl index b9243c52e5..145aeb632a 100644 --- a/src/mainboard/google/parrot/acpi/ec.asl +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 8fe68c5805..aaac6d3dc1 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/parrot/acpi/platform.asl b/src/mainboard/google/parrot/acpi/platform.asl index d59e293103..ee04e2fdeb 100644 --- a/src/mainboard/google/parrot/acpi/platform.asl +++ b/src/mainboard/google/parrot/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/acpi/superio.asl b/src/mainboard/google/parrot/acpi/superio.asl index 5e90f3e73c..cf409543e4 100644 --- a/src/mainboard/google/parrot/acpi/superio.asl +++ b/src/mainboard/google/parrot/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/acpi/thermal.asl b/src/mainboard/google/parrot/acpi/thermal.asl index 728280e463..fa3b79ff6f 100644 --- a/src/mainboard/google/parrot/acpi/thermal.asl +++ b/src/mainboard/google/parrot/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index bd7df70cb0..731b1f432f 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index d60bd5381e..e1619d57d0 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index 36506dfeda..615ff29dce 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index e4921fa0b9..73714ce20a 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 917d16591e..f483984373 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index 623c0bc77c..fcdfcf44e3 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h index e389a77602..413de1557d 100644 --- a/src/mainboard/google/parrot/ec.h +++ b/src/mainboard/google/parrot/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c index 359b6ecc6d..854d0aac0b 100644 --- a/src/mainboard/google/parrot/gpio.c +++ b/src/mainboard/google/parrot/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index e22f6edde3..0c21edc51e 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 873776beff..6b242ffda9 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index ab0718ff11..1ec86a2ec1 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index c0a5d01385..758399e3a7 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/parrot/thermal.h b/src/mainboard/google/parrot/thermal.h index 82c0fec772..f5a057de51 100644 --- a/src/mainboard/google/parrot/thermal.h +++ b/src/mainboard/google/parrot/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 - 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index b0b4d233bb..13c44f29a8 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/Makefile.inc b/src/mainboard/google/peach_pit/Makefile.inc index 65e0ea20ee..fd76686e40 100644 --- a/src/mainboard/google/peach_pit/Makefile.inc +++ b/src/mainboard/google/peach_pit/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index c229ed6732..f063b25bea 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/devicetree.cb b/src/mainboard/google/peach_pit/devicetree.cb index 06bd34bc46..a86fb22695 100644 --- a/src/mainboard/google/peach_pit/devicetree.cb +++ b/src/mainboard/google/peach_pit/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 553c2adbd5..8b1fbabfa2 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c index 541e3b04c1..d4f0d70d95 100644 --- a/src/mainboard/google/peach_pit/memory.c +++ b/src/mainboard/google/peach_pit/memory.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index c9c45d27d4..98425f33e1 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/peach_pit/wakeup.c b/src/mainboard/google/peach_pit/wakeup.c index 9eadf1f876..d8d964bf28 100644 --- a/src/mainboard/google/peach_pit/wakeup.c +++ b/src/mainboard/google/peach_pit/wakeup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 9d26430343..69cfe29400 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/bootblock.c b/src/mainboard/google/poppy/bootblock.c index b82a8053d5..fe2262c1d5 100644 --- a/src/mainboard/google/poppy/bootblock.c +++ b/src/mainboard/google/poppy/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 34aad93060..329d53e701 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index bf8d221832..dceccc2650 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/ec.c b/src/mainboard/google/poppy/ec.c index a93bf19edf..4fbea2e845 100644 --- a/src/mainboard/google/poppy/ec.c +++ b/src/mainboard/google/poppy/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 5aa45d40a8..4c75a10a4d 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c index 29a83df69b..bdcaa321f3 100644 --- a/src/mainboard/google/poppy/ramstage.c +++ b/src/mainboard/google/poppy/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 9de1602a1a..8c5d3085a3 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c index 44ab10cdf1..21ae5f8216 100644 --- a/src/mainboard/google/poppy/smihandler.c +++ b/src/mainboard/google/poppy/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 5cc1a4fc5d..b8ad480cce 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl index 0a703d4147..0f433eaba9 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl index d7ca972606..5f0e71214d 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 68633723ea..5f08a1d2b4 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl index 5dc747bd04..89396f087c 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl index ec4eb1e2bf..03cba8cac2 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h index 484510bf05..cb2ca72d81 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h index a2f29fb453..d439f89765 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index e1538c67b6..8b475d4928 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c index 022b733398..7db8339a8b 100644 --- a/src/mainboard/google/poppy/variants/atlas/memory.c +++ b/src/mainboard/google/poppy/variants/atlas/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/atlas/nhlt.c b/src/mainboard/google/poppy/variants/atlas/nhlt.c index 4d0fd1ee0a..0d909695b5 100644 --- a/src/mainboard/google/poppy/variants/atlas/nhlt.c +++ b/src/mainboard/google/poppy/variants/atlas/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index c731b52c6e..7c2d282513 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl index 5bb8df5b75..6bc5a68ce3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl index d7640b249d..154a62b6a3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl index 5e34ba4a9e..fafa29f30a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index d15f5c63d8..02c18e119a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl index 52901f933c..e2c1c01bbc 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl index 9d6de6098f..d96416e279 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl index 6f4a87b82b..a8a7e4ad13 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h index 5edbe59a44..f89808c6a3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h index 4c9ade3e66..4e1506069f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index 4c26d5e086..63cc123b05 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/memory.c b/src/mainboard/google/poppy/variants/baseboard/memory.c index 59a2d6cbd0..ac8e90815c 100644 --- a/src/mainboard/google/poppy/variants/baseboard/memory.c +++ b/src/mainboard/google/poppy/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/baseboard/nhlt.c b/src/mainboard/google/poppy/variants/baseboard/nhlt.c index 1014cfb5e9..3d8d29fd70 100644 --- a/src/mainboard/google/poppy/variants/baseboard/nhlt.c +++ b/src/mainboard/google/poppy/variants/baseboard/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 42f84f57f4..93b8e15375 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl index 2b3bd255a5..ee038fb9c7 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/ec.h b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h index 843161ae5e..d7fcf5548e 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h index 98450f602f..ab76d7b498 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 7ff3cc7551..9b146c76df 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 6d54e174c8..9a08597d04 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index b6e3d2cd08..5ab78eeb98 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c index c3096d4765..50bd7eaf21 100644 --- a/src/mainboard/google/poppy/variants/nami/nhlt.c +++ b/src/mainboard/google/poppy/variants/nami/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nami/smihandler.c b/src/mainboard/google/poppy/variants/nami/smihandler.c index 61162b40b1..6d9c227d49 100644 --- a/src/mainboard/google/poppy/variants/nami/smihandler.c +++ b/src/mainboard/google/poppy/variants/nami/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 4f80e2f301..5f83a5f7b6 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl index 92612cd6cb..456bc10d2b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl index 7993a66fde..a265c5d4ae 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl index 3fd4a1d748..2d09608ed4 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl index 933a831a69..e5eed8eb53 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl index b21cdcfa90..5626b6c223 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h index 127282cf9a..d6eb4f1649 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h index 7482e74374..97774271b3 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h index c101451641..1d019c3f82 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 84855078cf..223ad49fb1 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/memory.c b/src/mainboard/google/poppy/variants/nautilus/memory.c index a0dd76bcb6..dd8608f2d5 100644 --- a/src/mainboard/google/poppy/variants/nautilus/memory.c +++ b/src/mainboard/google/poppy/variants/nautilus/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/nhlt.c b/src/mainboard/google/poppy/variants/nautilus/nhlt.c index 1fe366800d..08c057a8c1 100644 --- a/src/mainboard/google/poppy/variants/nautilus/nhlt.c +++ b/src/mainboard/google/poppy/variants/nautilus/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/sku.c b/src/mainboard/google/poppy/variants/nautilus/sku.c index 55b118d847..2040f144ca 100644 --- a/src/mainboard/google/poppy/variants/nautilus/sku.c +++ b/src/mainboard/google/poppy/variants/nautilus/sku.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nautilus/smihandler.c b/src/mainboard/google/poppy/variants/nautilus/smihandler.c index f23798eac3..3b6c45aa3c 100644 --- a/src/mainboard/google/poppy/variants/nautilus/smihandler.c +++ b/src/mainboard/google/poppy/variants/nautilus/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/ec.c b/src/mainboard/google/poppy/variants/nocturne/ec.c index 76d80d2ccb..90f1187a24 100644 --- a/src/mainboard/google/poppy/variants/nocturne/ec.c +++ b/src/mainboard/google/poppy/variants/nocturne/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index c62317a04b..0c8947b15a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl index 1213270dd1..bbf534a2e4 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl index 19146dcfd0..4d87b2910e 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl index 7e63340bb6..6c74ef1498 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index 059c7f016e..1ca8b55d2a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl index 7f6a4efa9c..0e729a5a56 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl index ec5347d320..f489990a78 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h index dfb0f7449e..bb98e65e97 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h index 45bb76b7b6..7fbd04f3d1 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 3743cf70b1..e9cec1e9b1 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/memory.c b/src/mainboard/google/poppy/variants/nocturne/memory.c index b6c77a3993..59490bad26 100644 --- a/src/mainboard/google/poppy/variants/nocturne/memory.c +++ b/src/mainboard/google/poppy/variants/nocturne/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/nocturne/nhlt.c b/src/mainboard/google/poppy/variants/nocturne/nhlt.c index 04a44825eb..0b0efdc368 100644 --- a/src/mainboard/google/poppy/variants/nocturne/nhlt.c +++ b/src/mainboard/google/poppy/variants/nocturne/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl index 45522f98c1..14fa2113db 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl index a9ec74269f..7d9006a068 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h b/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h index 81f92b7844..fbae57d7fc 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h b/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h index 4f79495e4f..bcb87cb1d7 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index d82eeafae0..0cae82f404 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl index a9afa73115..7d9006a068 100644 --- a/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h index ac17745fa0..2711481903 100644 --- a/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h b/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h index cd34cf060a..bcb87cb1d7 100644 --- a/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/rammus/mainboard.c b/src/mainboard/google/poppy/variants/rammus/mainboard.c index 5c5b258885..c3f5b2af83 100644 --- a/src/mainboard/google/poppy/variants/rammus/mainboard.c +++ b/src/mainboard/google/poppy/variants/rammus/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/rammus/memory.c b/src/mainboard/google/poppy/variants/rammus/memory.c index 92e66bd9fb..1a4fe05f20 100644 --- a/src/mainboard/google/poppy/variants/rammus/memory.c +++ b/src/mainboard/google/poppy/variants/rammus/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c index efa08ee213..c22f672eca 100644 --- a/src/mainboard/google/poppy/variants/rammus/nhlt.c +++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 0e24bb76dd..c59c572e03 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl index 45522f98c1..14fa2113db 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl index e42c8ea385..c44e6515b8 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h b/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h index 216c0d01fa..1bee0bb741 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h b/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h index 4f79495e4f..bcb87cb1d7 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 0e80b64252..f9b0d7992d 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/acpi/ec.asl b/src/mainboard/google/rambi/acpi/ec.asl index febe102c17..f66955aa7b 100644 --- a/src/mainboard/google/rambi/acpi/ec.asl +++ b/src/mainboard/google/rambi/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index e9422b1db2..a17ecaee19 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl index e3557d9316..9f3fe50293 100644 --- a/src/mainboard/google/rambi/acpi/superio.asl +++ b/src/mainboard/google/rambi/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 867b2203a9..4538bdb29d 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index ebced06030..fbb709d42b 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index 39f9516e0b..014f442651 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 8adde36cd2..3a8d1a1a30 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 60f3d30d70..39d3aac7b0 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/ec.h b/src/mainboard/google/rambi/ec.h index 4eda99757f..6dd15badef 100644 --- a/src/mainboard/google/rambi/ec.h +++ b/src/mainboard/google/rambi/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index 9cccde6f06..6afc8e23c0 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/irqroute.c b/src/mainboard/google/rambi/irqroute.c index db8c512a43..f0855adbc2 100644 --- a/src/mainboard/google/rambi/irqroute.c +++ b/src/mainboard/google/rambi/irqroute.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index 701eac386a..fd28367235 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 7e9b343880..4ecb08eeae 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index 250e636fca..9f2098e9aa 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index f74d77d3f3..d786ee6711 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/banjo/Makefile.inc b/src/mainboard/google/rambi/variants/banjo/Makefile.inc index 0c31309750..379f85cd3f 100644 --- a/src/mainboard/google/rambi/variants/banjo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/banjo/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c index e22c8db35d..60d809323e 100644 --- a/src/mainboard/google/rambi/variants/banjo/gpio.c +++ b/src/mainboard/google/rambi/variants/banjo/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl index 5a46bdc9e7..f64eeff40e 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h index 617fe021b9..71ce0e52f9 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/candy/Makefile.inc b/src/mainboard/google/rambi/variants/candy/Makefile.inc index 219cab4049..d69b72c2a6 100644 --- a/src/mainboard/google/rambi/variants/candy/Makefile.inc +++ b/src/mainboard/google/rambi/variants/candy/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c index 61050e58b1..5f15a15452 100644 --- a/src/mainboard/google/rambi/variants/candy/gpio.c +++ b/src/mainboard/google/rambi/variants/candy/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h index 22372d7bf1..ff737235c2 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc index 0d13f0db02..1d09e1ef3b 100644 --- a/src/mainboard/google/rambi/variants/clapper/Makefile.inc +++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c index e1bcefa6e9..7eacfd1797 100644 --- a/src/mainboard/google/rambi/variants/clapper/gpio.c +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h index 3fbd77f5d1..8c135423f9 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc index 4b3037ccba..98a7e3d087 100644 --- a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc +++ b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/enguarde/gpio.c b/src/mainboard/google/rambi/variants/enguarde/gpio.c index 784ed23cc5..df15054e97 100644 --- a/src/mainboard/google/rambi/variants/enguarde/gpio.c +++ b/src/mainboard/google/rambi/variants/enguarde/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h index f1460678f8..a693c71213 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc index 760a86e84a..5fcea881bc 100644 --- a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc +++ b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c index 504d64adda..57b9653ae0 100644 --- a/src/mainboard/google/rambi/variants/glimmer/gpio.c +++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h index 3fbd77f5d1..8c135423f9 100644 --- a/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc index 47be14247f..d21bd46b06 100644 --- a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc +++ b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c index 7e2361c086..2b4af4a53d 100644 --- a/src/mainboard/google/rambi/variants/gnawty/gpio.c +++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h index c188ccfe06..ff737235c2 100644 --- a/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/heli/Makefile.inc b/src/mainboard/google/rambi/variants/heli/Makefile.inc index 38dd56c9ad..e2f7af17fd 100644 --- a/src/mainboard/google/rambi/variants/heli/Makefile.inc +++ b/src/mainboard/google/rambi/variants/heli/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c index bcb1430c98..ead1341a0f 100644 --- a/src/mainboard/google/rambi/variants/heli/gpio.c +++ b/src/mainboard/google/rambi/variants/heli/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h index 8134ab412b..71ce0e52f9 100644 --- a/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/kip/Makefile.inc b/src/mainboard/google/rambi/variants/kip/Makefile.inc index 8ca5f69f46..017e8e2495 100644 --- a/src/mainboard/google/rambi/variants/kip/Makefile.inc +++ b/src/mainboard/google/rambi/variants/kip/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c index 56942bd2be..9180b880f7 100644 --- a/src/mainboard/google/rambi/variants/kip/gpio.c +++ b/src/mainboard/google/rambi/variants/kip/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h index 684aac81bb..a693c71213 100644 --- a/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/ninja/Makefile.inc b/src/mainboard/google/rambi/variants/ninja/Makefile.inc index 65e4e95c7b..6c094eef0d 100644 --- a/src/mainboard/google/rambi/variants/ninja/Makefile.inc +++ b/src/mainboard/google/rambi/variants/ninja/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/ninja/gpio.c b/src/mainboard/google/rambi/variants/ninja/gpio.c index 2d8285c6d6..945182c236 100644 --- a/src/mainboard/google/rambi/variants/ninja/gpio.c +++ b/src/mainboard/google/rambi/variants/ninja/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl index 7ab3356350..a460908726 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h index 6a91314830..2d7594a1f8 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index 5b220e0efa..a5e5c4bfe8 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/orco/Makefile.inc b/src/mainboard/google/rambi/variants/orco/Makefile.inc index 78cdb986ea..a5c8f31523 100644 --- a/src/mainboard/google/rambi/variants/orco/Makefile.inc +++ b/src/mainboard/google/rambi/variants/orco/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c index afa50cf1ce..08cb034d16 100644 --- a/src/mainboard/google/rambi/variants/orco/gpio.c +++ b/src/mainboard/google/rambi/variants/orco/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h index ba316e9018..71ce0e52f9 100644 --- a/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/quawks/Makefile.inc b/src/mainboard/google/rambi/variants/quawks/Makefile.inc index 20ecf6e5dd..19b5093cbc 100644 --- a/src/mainboard/google/rambi/variants/quawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/quawks/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c index 56942bd2be..9180b880f7 100644 --- a/src/mainboard/google/rambi/variants/quawks/gpio.c +++ b/src/mainboard/google/rambi/variants/quawks/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h index 684aac81bb..a693c71213 100644 --- a/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/rambi/Makefile.inc b/src/mainboard/google/rambi/variants/rambi/Makefile.inc index 253bced3cd..df68deb472 100644 --- a/src/mainboard/google/rambi/variants/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/variants/rambi/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/rambi/gpio.c b/src/mainboard/google/rambi/variants/rambi/gpio.c index 56942bd2be..9180b880f7 100644 --- a/src/mainboard/google/rambi/variants/rambi/gpio.c +++ b/src/mainboard/google/rambi/variants/rambi/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl index d07ac418bc..f8409eed13 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h b/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h index a424f2f23f..62a0884d15 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/squawks/Makefile.inc b/src/mainboard/google/rambi/variants/squawks/Makefile.inc index 20ecf6e5dd..19b5093cbc 100644 --- a/src/mainboard/google/rambi/variants/squawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/squawks/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c index 56942bd2be..9180b880f7 100644 --- a/src/mainboard/google/rambi/variants/squawks/gpio.c +++ b/src/mainboard/google/rambi/variants/squawks/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h index 684aac81bb..a693c71213 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/sumo/Makefile.inc b/src/mainboard/google/rambi/variants/sumo/Makefile.inc index 65e4e95c7b..6c094eef0d 100644 --- a/src/mainboard/google/rambi/variants/sumo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/sumo/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c index c4cc40aa98..6dc8851e65 100644 --- a/src/mainboard/google/rambi/variants/sumo/gpio.c +++ b/src/mainboard/google/rambi/variants/sumo/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h index 7003b9db0a..601b137461 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index d6cd580588..97495049ad 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/swanky/Makefile.inc b/src/mainboard/google/rambi/variants/swanky/Makefile.inc index 62bfb5db49..d7bee39c03 100644 --- a/src/mainboard/google/rambi/variants/swanky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/swanky/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c index 3b62880b0d..951ee54593 100644 --- a/src/mainboard/google/rambi/variants/swanky/gpio.c +++ b/src/mainboard/google/rambi/variants/swanky/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h index 8134ab412b..71ce0e52f9 100644 --- a/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/winky/Makefile.inc b/src/mainboard/google/rambi/variants/winky/Makefile.inc index 552e69ace9..dc861bf8f5 100644 --- a/src/mainboard/google/rambi/variants/winky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/winky/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c index 9c3a33875b..6924044276 100644 --- a/src/mainboard/google/rambi/variants/winky/gpio.c +++ b/src/mainboard/google/rambi/variants/winky/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h index 065ec17249..0f554211d5 100644 --- a/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c index a9ed8ac98b..104414265f 100644 --- a/src/mainboard/google/rambi/w25q64.c +++ b/src/mainboard/google/rambi/w25q64.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index dd06f649e2..fe2513ba05 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 681008df30..c770b8cc6f 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 6de58d85c8..294e350a71 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c index 11d63ea25d..ddcf6093df 100644 --- a/src/mainboard/google/reef/ec.c +++ b/src/mainboard/google/reef/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 20b6a26459..2ba1e67065 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index 0e9917fd53..c99b8cb20c 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index 1743860a37..2f019cf4c1 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 054edaa7fb..40aee4db2f 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index af8d75a9bf..7e04b5b463 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h index 6e1de7a58b..4bd3103698 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index 1db742240d..7fb9a7e26d 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index 8611ecd4f3..b93421fce4 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index 76731070db..21844d5162 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index f2ef80fbe3..f413d01237 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 0c762c0dd3..25036f770a 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl index f3ff04b5e9..2e6e9feadf 100644 --- a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/coral/include/variant/ec.h b/src/mainboard/google/reef/variants/coral/include/variant/ec.h index 4f5051b384..4d96aec700 100644 --- a/src/mainboard/google/reef/variants/coral/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/coral/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/coral/include/variant/gpio.h b/src/mainboard/google/reef/variants/coral/include/variant/gpio.h index 6d1ce5a0e4..3777fed07b 100644 --- a/src/mainboard/google/reef/variants/coral/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/coral/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index aad65f085a..0e21b87c2b 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016, 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl index fe4bf01871..f3723b0c40 100644 --- a/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/nasher/include/variant/ec.h b/src/mainboard/google/reef/variants/nasher/include/variant/ec.h index 94424e1064..1c26344731 100644 --- a/src/mainboard/google/reef/variants/nasher/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/nasher/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h b/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h index 5eeeec94ff..28a21f0014 100644 --- a/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl index eabd6128c0..b8d5bf7454 100644 --- a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h index 586f1064f4..87f03b1ece 100644 --- a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h index 6d1ce5a0e4..3777fed07b 100644 --- a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c index 71ee060610..fe4b8c5afc 100644 --- a/src/mainboard/google/reef/variants/pyro/memory.c +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl index f3ff04b5e9..2e6e9feadf 100644 --- a/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/reef/include/variant/ec.h b/src/mainboard/google/reef/variants/reef/include/variant/ec.h index 586f1064f4..87f03b1ece 100644 --- a/src/mainboard/google/reef/variants/reef/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/reef/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/reef/include/variant/gpio.h b/src/mainboard/google/reef/variants/reef/include/variant/gpio.h index 6d1ce5a0e4..3777fed07b 100644 --- a/src/mainboard/google/reef/variants/reef/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/reef/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl index 807e0a5f57..4af1d3171a 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/sand/include/variant/ec.h b/src/mainboard/google/reef/variants/sand/include/variant/ec.h index 63f1346898..cb4509f590 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/sand/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/sand/include/variant/gpio.h b/src/mainboard/google/reef/variants/sand/include/variant/gpio.h index 5eeeec94ff..28a21f0014 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/sand/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl index d523d9f5bd..81b167955d 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/ec.h b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h index 4f5051b384..4d96aec700 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h index 6d1ce5a0e4..3777fed07b 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c index b34b8e2c92..2ce262b974 100644 --- a/src/mainboard/google/reef/variants/snappy/mainboard.c +++ b/src/mainboard/google/reef/variants/snappy/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016, 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 7e230447aa..0595623b37 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/bootblock.c b/src/mainboard/google/sarien/bootblock.c index bee9b1ad7a..813409433b 100644 --- a/src/mainboard/google/sarien/bootblock.c +++ b/src/mainboard/google/sarien/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 9077d86679..2c8dbca844 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 8acd0b59d7..2b35bda27a 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/ec.c b/src/mainboard/google/sarien/ec.c index fd8e84fbc8..c0edf680c8 100644 --- a/src/mainboard/google/sarien/ec.c +++ b/src/mainboard/google/sarien/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/hda_verb.c b/src/mainboard/google/sarien/hda_verb.c index 9ab4778274..3fbc3a24c3 100644 --- a/src/mainboard/google/sarien/hda_verb.c +++ b/src/mainboard/google/sarien/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index d57c6fe08c..7df73b0148 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index 20eee7f34b..eefe295df2 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/sku.c b/src/mainboard/google/sarien/sku.c index d0b48f0572..d47dc82e51 100644 --- a/src/mainboard/google/sarien/sku.c +++ b/src/mainboard/google/sarien/sku.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/smihandler.c b/src/mainboard/google/sarien/smihandler.c index 18dbfbc154..0dee122c91 100644 --- a/src/mainboard/google/sarien/smihandler.c +++ b/src/mainboard/google/sarien/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/arcada/Makefile.inc b/src/mainboard/google/sarien/variants/arcada/Makefile.inc index 2bf028eb1f..c8d31fdea6 100644 --- a/src/mainboard/google/sarien/variants/arcada/Makefile.inc +++ b/src/mainboard/google/sarien/variants/arcada/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index ff0240c991..2cf52a1fee 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 73e1decc1b..9be278631c 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 41121d28fe..ba3dd00918 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h index 01a17b5f99..49e455a659 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h index f7e0403e59..97fe7823ff 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h index d50fc1e34a..f62f417074 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h index da1189e14c..3170a47342 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/sarien/Makefile.inc b/src/mainboard/google/sarien/variants/sarien/Makefile.inc index 2bf028eb1f..c8d31fdea6 100644 --- a/src/mainboard/google/sarien/variants/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/variants/sarien/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 78db12e8a1..aac4055355 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 0cdbcd1400..7b94a216e4 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 41121d28fe..ba3dd00918 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h index 01a17b5f99..49e455a659 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h index f7e0403e59..97fe7823ff 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h index e2c0647f12..baf7192c62 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h index bbb3e9e68d..42d4b938c6 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 921f9e7585..eb75196f2d 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/acpi/ec.asl b/src/mainboard/google/slippy/acpi/ec.asl index 7189ef1a9e..964ed765bf 100644 --- a/src/mainboard/google/slippy/acpi/ec.asl +++ b/src/mainboard/google/slippy/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl index 5b0d27657e..ddeea8a95d 100644 --- a/src/mainboard/google/slippy/acpi/platform.asl +++ b/src/mainboard/google/slippy/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/acpi/superio.asl b/src/mainboard/google/slippy/acpi/superio.asl index 0460b2b3b2..02c320af60 100644 --- a/src/mainboard/google/slippy/acpi/superio.asl +++ b/src/mainboard/google/slippy/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/acpi/thermal.asl b/src/mainboard/google/slippy/acpi/thermal.asl index ac4d61099b..3ea7aa2f37 100644 --- a/src/mainboard/google/slippy/acpi/thermal.asl +++ b/src/mainboard/google/slippy/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index d7a8cbbdb6..ae79d94bad 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index a3245de6cd..a92572f4aa 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index 39f9516e0b..014f442651 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 3338d842b4..373e31a9b9 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index e296575a92..417dd79f17 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/ec.h b/src/mainboard/google/slippy/ec.h index ae947a1b9a..8653c8ad82 100644 --- a/src/mainboard/google/slippy/ec.h +++ b/src/mainboard/google/slippy/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/gma-mainboard.ads b/src/mainboard/google/slippy/gma-mainboard.ads index e362f891ab..4d1b6c0248 100644 --- a/src/mainboard/google/slippy/gma-mainboard.ads +++ b/src/mainboard/google/slippy/gma-mainboard.ads @@ -1,5 +1,4 @@ -- --- Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 5a1af73a79..b7af3668f8 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 7c40e23183..5ad47e2835 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 3a2d96f3a0..7a9715443f 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 48175880ce..41e9d5a2ab 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/thermal.h b/src/mainboard/google/slippy/thermal.h index a2f8e7128f..c01481ab0f 100644 --- a/src/mainboard/google/slippy/thermal.h +++ b/src/mainboard/google/slippy/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index 87a228c89c..ab5dc414ea 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/falco/Makefile.inc b/src/mainboard/google/slippy/variants/falco/Makefile.inc index 38d27a4ceb..650d12e740 100644 --- a/src/mainboard/google/slippy/variants/falco/Makefile.inc +++ b/src/mainboard/google/slippy/variants/falco/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/falco/hda_verb.c b/src/mainboard/google/slippy/variants/falco/hda_verb.c index 745a3a7d4c..30a419e9db 100644 --- a/src/mainboard/google/slippy/variants/falco/hda_verb.c +++ b/src/mainboard/google/slippy/variants/falco/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl index acf8a034db..b8f5f14723 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h b/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h index c35b81eea4..6419e32b9b 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index c193d20e41..ee78a705e9 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/leon/Makefile.inc b/src/mainboard/google/slippy/variants/leon/Makefile.inc index 5d8d9d3d6f..2ba682e2ec 100644 --- a/src/mainboard/google/slippy/variants/leon/Makefile.inc +++ b/src/mainboard/google/slippy/variants/leon/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/leon/hda_verb.c b/src/mainboard/google/slippy/variants/leon/hda_verb.c index 13fbb4d53a..4fe9278639 100644 --- a/src/mainboard/google/slippy/variants/leon/hda_verb.c +++ b/src/mainboard/google/slippy/variants/leon/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl index 8542f97043..9ac43e8a1e 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h b/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h index 7527ff2103..798890ac2a 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 9e9cf73656..edf974826f 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/peppy/Makefile.inc b/src/mainboard/google/slippy/variants/peppy/Makefile.inc index d5c59e3b49..f43ccf5a4b 100644 --- a/src/mainboard/google/slippy/variants/peppy/Makefile.inc +++ b/src/mainboard/google/slippy/variants/peppy/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/peppy/hda_verb.c b/src/mainboard/google/slippy/variants/peppy/hda_verb.c index 0b1b69c370..267e3e9087 100644 --- a/src/mainboard/google/slippy/variants/peppy/hda_verb.c +++ b/src/mainboard/google/slippy/variants/peppy/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index 4c930de9ca..536a7a4969 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h b/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h index 8eb3da9d70..0da2652446 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 8adf4b2647..a9e1812829 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/wolf/Makefile.inc b/src/mainboard/google/slippy/variants/wolf/Makefile.inc index 0c860bfc80..249f5633e8 100644 --- a/src/mainboard/google/slippy/variants/wolf/Makefile.inc +++ b/src/mainboard/google/slippy/variants/wolf/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c index e1eb5eda50..63cb8fa171 100644 --- a/src/mainboard/google/slippy/variants/wolf/hda_verb.c +++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl index 8542f97043..9ac43e8a1e 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h index 5c72f7356c..c7e65d2305 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 651d8b1d35..bb61a45e7f 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index fa08251b24..fa2313c154 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/Makefile.inc b/src/mainboard/google/smaug/Makefile.inc index e7b26f5321..7b848774c5 100644 --- a/src/mainboard/google/smaug/Makefile.inc +++ b/src/mainboard/google/smaug/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/bct/Makefile.inc b/src/mainboard/google/smaug/bct/Makefile.inc index ac3aa66862..4147ba6d3f 100644 --- a/src/mainboard/google/smaug/bct/Makefile.inc +++ b/src/mainboard/google/smaug/bct/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 Google Inc. -## Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/bct/cfg2inc.sh b/src/mainboard/google/smaug/bct/cfg2inc.sh index 4295ed0452..d7b6c46495 100644 --- a/src/mainboard/google/smaug/bct/cfg2inc.sh +++ b/src/mainboard/google/smaug/bct/cfg2inc.sh @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright 2015 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/bct/emmc.cfg b/src/mainboard/google/smaug/bct/emmc.cfg index 13ee04716f..be321cb1b5 100644 --- a/src/mainboard/google/smaug/bct/emmc.cfg +++ b/src/mainboard/google/smaug/bct/emmc.cfg @@ -1,4 +1,3 @@ -# Copyright 2015 Google Inc. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00210001; diff --git a/src/mainboard/google/smaug/bct/spi.cfg b/src/mainboard/google/smaug/bct/spi.cfg index 63e2750efa..44cc88352d 100644 --- a/src/mainboard/google/smaug/bct/spi.cfg +++ b/src/mainboard/google/smaug/bct/spi.cfg @@ -1,4 +1,3 @@ -# Copyright 2015 Google Inc. All rights reserved. # Distributed under the terms of the GNU General Public License v2 Version = 0x00210001; diff --git a/src/mainboard/google/smaug/boardid.c b/src/mainboard/google/smaug/boardid.c index 74f6f11e22..bbff820a40 100644 --- a/src/mainboard/google/smaug/boardid.c +++ b/src/mainboard/google/smaug/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/bootblock.c b/src/mainboard/google/smaug/bootblock.c index 65ef1a1343..c50e20c70e 100644 --- a/src/mainboard/google/smaug/bootblock.c +++ b/src/mainboard/google/smaug/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 8f76f11b58..293f41e737 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb index 5d7bf86c5f..d90b4ea376 100644 --- a/src/mainboard/google/smaug/devicetree.cb +++ b/src/mainboard/google/smaug/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/gpio.h b/src/mainboard/google/smaug/gpio.h index bf6fd53d99..01cf76dcae 100644 --- a/src/mainboard/google/smaug/gpio.h +++ b/src/mainboard/google/smaug/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 37d49bd00e..5795fda243 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index fdbabacc9c..7e128fb23b 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/pmic.h b/src/mainboard/google/smaug/pmic.h index 130f134d95..643d714c17 100644 --- a/src/mainboard/google/smaug/pmic.h +++ b/src/mainboard/google/smaug/pmic.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/reset.c b/src/mainboard/google/smaug/reset.c index 1d96343b49..2fe55ee068 100644 --- a/src/mainboard/google/smaug/reset.c +++ b/src/mainboard/google/smaug/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/romstage.c b/src/mainboard/google/smaug/romstage.c index 1d10d0e1aa..37187d835f 100644 --- a/src/mainboard/google/smaug/romstage.c +++ b/src/mainboard/google/smaug/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/smaug/sdram_configs.c b/src/mainboard/google/smaug/sdram_configs.c index 91e5aefdeb..02c871546f 100644 --- a/src/mainboard/google/smaug/sdram_configs.c +++ b/src/mainboard/google/smaug/sdram_configs.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 0bd8f5aad1..6095354bc8 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index 232ff487a6..e3c199209b 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index d952155e8d..f2837f9319 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/bootblock.c b/src/mainboard/google/storm/bootblock.c index 8313501eff..186673c4af 100644 --- a/src/mainboard/google/storm/bootblock.c +++ b/src/mainboard/google/storm/bootblock.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 18b22c13ce..e59b393e36 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 744572e35a..f34501cabb 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/devicetree.cb b/src/mainboard/google/storm/devicetree.cb index 130a882075..c8c8a8251f 100644 --- a/src/mainboard/google/storm/devicetree.cb +++ b/src/mainboard/google/storm/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/gsbi.c b/src/mainboard/google/storm/gsbi.c index 915f317df9..3243680bca 100644 --- a/src/mainboard/google/storm/gsbi.c +++ b/src/mainboard/google/storm/gsbi.c @@ -1,7 +1,6 @@ /* * This file is part of the depthcharge project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 783e6ad7a1..0aae56e198 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 3f1515ab06..8d0a166cd3 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/storm/mmu.h b/src/mainboard/google/storm/mmu.h index 956553d2c3..1bf7e4f5fa 100644 --- a/src/mainboard/google/storm/mmu.h +++ b/src/mainboard/google/storm/mmu.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c index 0ab5054470..f8724cfdb7 100644 --- a/src/mainboard/google/storm/reset.c +++ b/src/mainboard/google/storm/reset.c @@ -2,8 +2,6 @@ * * This file is part of the coreboot project. * - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index c1b86541fb..cb5a493453 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 3add36258b..5cc2bd4ced 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/acpi/ec.asl b/src/mainboard/google/stout/acpi/ec.asl index 3379ebf673..c3db9e6aea 100644 --- a/src/mainboard/google/stout/acpi/ec.asl +++ b/src/mainboard/google/stout/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/acpi/mainboard.asl b/src/mainboard/google/stout/acpi/mainboard.asl index 92f160deed..ff7ff92852 100644 --- a/src/mainboard/google/stout/acpi/mainboard.asl +++ b/src/mainboard/google/stout/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/stout/acpi/platform.asl b/src/mainboard/google/stout/acpi/platform.asl index 6d8b46118b..757558e1dc 100644 --- a/src/mainboard/google/stout/acpi/platform.asl +++ b/src/mainboard/google/stout/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/acpi/superio.asl b/src/mainboard/google/stout/acpi/superio.asl index 3bf2f36eea..b9709a9539 100644 --- a/src/mainboard/google/stout/acpi/superio.asl +++ b/src/mainboard/google/stout/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/acpi/thermal.asl b/src/mainboard/google/stout/acpi/thermal.asl index 0cda0783be..3e826340e1 100644 --- a/src/mainboard/google/stout/acpi/thermal.asl +++ b/src/mainboard/google/stout/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 089fdee270..6e28ca3678 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 482de98555..4c39b54ce4 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index 36506dfeda..615ff29dce 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 976649e073..1a91515b24 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index b4e96f0dd3..2742ded5ad 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 3e91282f10..ac2fea011f 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h index f035e246be..f90dd7913c 100644 --- a/src/mainboard/google/stout/ec.h +++ b/src/mainboard/google/stout/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c index 014037e4b9..9849fdf4e9 100644 --- a/src/mainboard/google/stout/gpio.c +++ b/src/mainboard/google/stout/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/hda_verb.c b/src/mainboard/google/stout/hda_verb.c index abaa8020f8..485a6dde9f 100644 --- a/src/mainboard/google/stout/hda_verb.c +++ b/src/mainboard/google/stout/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index dcd8fc656a..23d2889f01 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index ce89f9c375..43df830945 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index e9ce9b3f42..b88d3a452d 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/stout/thermal.h b/src/mainboard/google/stout/thermal.h index 83f2113ff4..11336091ad 100644 --- a/src/mainboard/google/stout/thermal.h +++ b/src/mainboard/google/stout/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc index bda55be4fb..5c85351a69 100644 --- a/src/mainboard/google/trogdor/Makefile.inc +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Google LLC -## Copyright 2019 The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index f024e13646..acaf02288c 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index def3068d31..2036da6b1f 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * Copyright 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c index c658093d07..05da53ed6c 100644 --- a/src/mainboard/google/trogdor/bootblock.c +++ b/src/mainboard/google/trogdor/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 6f713fe08a..4abe1f13de 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 9af3d51cb8..383d3acae8 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/devicetree.cb b/src/mainboard/google/trogdor/devicetree.cb index d64ade4fce..3720374155 100644 --- a/src/mainboard/google/trogdor/devicetree.cb +++ b/src/mainboard/google/trogdor/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 0dd26243a8..a2cee53fc5 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/memlayout.ld b/src/mainboard/google/trogdor/memlayout.ld index 74790f5404..174ae545fa 100644 --- a/src/mainboard/google/trogdor/memlayout.ld +++ b/src/mainboard/google/trogdor/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/reset.c b/src/mainboard/google/trogdor/reset.c index 558f63d79f..c566e127fe 100644 --- a/src/mainboard/google/trogdor/reset.c +++ b/src/mainboard/google/trogdor/reset.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * Copyright 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 872798a791..1e87c4d305 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 38c5c3b552..db72485307 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc index 0abb668c1a..5bcdb013cd 100644 --- a/src/mainboard/google/veyron/Makefile.inc +++ b/src/mainboard/google/veyron/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/board.h b/src/mainboard/google/veyron/board.h index e6c300cb09..185bbbe9b7 100644 --- a/src/mainboard/google/veyron/board.h +++ b/src/mainboard/google/veyron/board.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index bf311cf605..6df66730a7 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index ad5e70944c..a97b5e5300 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index e1e232bc08..957102ec09 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb index d52b7636bf..ca359f40de 100644 --- a/src/mainboard/google/veyron/devicetree.cb +++ b/src/mainboard/google/veyron/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 6d6a2710c8..b49aedd86c 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c index 512ea770cd..c84e33af93 100644 --- a/src/mainboard/google/veyron/reset.c +++ b/src/mainboard/google/veyron/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index eba96c4650..cc83015006 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 291bc33fe9..62a69c7ca7 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 1bedab71d8..7f790cbf38 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/Makefile.inc b/src/mainboard/google/veyron_mickey/Makefile.inc index 0abb668c1a..5bcdb013cd 100644 --- a/src/mainboard/google/veyron_mickey/Makefile.inc +++ b/src/mainboard/google/veyron_mickey/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/board.h b/src/mainboard/google/veyron_mickey/board.h index c99146f217..2d6302e4f2 100644 --- a/src/mainboard/google/veyron_mickey/board.h +++ b/src/mainboard/google/veyron_mickey/board.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c index 9c53e374d8..7645952c12 100644 --- a/src/mainboard/google/veyron_mickey/boardid.c +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index ec55f7e452..15be677fec 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 79ca8ef76a..09ba0f1a85 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/devicetree.cb b/src/mainboard/google/veyron_mickey/devicetree.cb index 2752fc68ac..374dccb6a6 100644 --- a/src/mainboard/google/veyron_mickey/devicetree.cb +++ b/src/mainboard/google/veyron_mickey/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index f7af1cf0cf..e081a99e88 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/reset.c b/src/mainboard/google/veyron_mickey/reset.c index 512ea770cd..c84e33af93 100644 --- a/src/mainboard/google/veyron_mickey/reset.c +++ b/src/mainboard/google/veyron_mickey/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index d20bdb4c6d..ab9e7e5e38 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 291bc33fe9..62a69c7ca7 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 5d4fab3182..a9f85a2343 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/Makefile.inc b/src/mainboard/google/veyron_rialto/Makefile.inc index 0abb668c1a..5bcdb013cd 100644 --- a/src/mainboard/google/veyron_rialto/Makefile.inc +++ b/src/mainboard/google/veyron_rialto/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/board.h b/src/mainboard/google/veyron_rialto/board.h index def5246ef2..ea557592eb 100644 --- a/src/mainboard/google/veyron_rialto/board.h +++ b/src/mainboard/google/veyron_rialto/board.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c index 9c53e374d8..7645952c12 100644 --- a/src/mainboard/google/veyron_rialto/boardid.c +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 2379ae2478..44d1a4402d 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 21c741f588..5d69f90ff6 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/devicetree.cb b/src/mainboard/google/veyron_rialto/devicetree.cb index 7cc35dcc91..e2a1548a56 100644 --- a/src/mainboard/google/veyron_rialto/devicetree.cb +++ b/src/mainboard/google/veyron_rialto/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 8c775b63ff..11e90f214b 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/reset.c b/src/mainboard/google/veyron_rialto/reset.c index 512ea770cd..c84e33af93 100644 --- a/src/mainboard/google/veyron_rialto/reset.c +++ b/src/mainboard/google/veyron_rialto/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index ac651ef1d9..2d6d0f9b67 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 8eae71dcbd..8393ffb81c 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index 1b6b880806..9d1bb3f05b 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Authors. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c index 8685fa776a..6439b32334 100644 --- a/src/mainboard/google/volteer/bootblock.c +++ b/src/mainboard/google/volteer/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 2bcb4ec60a..0312179b0e 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index f62780bccc..4533f8937d 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c index 568738dd0c..d36c1e33af 100644 --- a/src/mainboard/google/volteer/ec.c +++ b/src/mainboard/google/volteer/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 6ed928a76b..2d505e1c58 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 7e87a2ad78..5d588b2d1d 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c index b44c2b57ea..c0dfc2d952 100644 --- a/src/mainboard/google/volteer/smihandler.c +++ b/src/mainboard/google/volteer/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc index 9f0106ba83..b6d85e34bb 100644 --- a/src/mainboard/google/volteer/spd/Makefile.inc +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Authors. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc index 87a8667bc6..954b9d2412 100644 --- a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Authors. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index da3e5423bf..fff03812d3 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h index 6920287ef5..a8ba27c84f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h index 51f4d376a4..55e86f9c79 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 3f8597f9f4..f368d886d2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index 111719871d..db2946dd33 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc index eba064ff1b..ebfdbd5a73 100644 --- a/src/mainboard/google/volteer/variants/ripto/Makefile.inc +++ b/src/mainboard/google/volteer/variants/ripto/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c index c621b1dffe..4159cb8d5b 100644 --- a/src/mainboard/google/volteer/variants/ripto/gpio.c +++ b/src/mainboard/google/volteer/variants/ripto/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h index 3655f14d77..36cdff8e56 100644 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h index 3a3282ee7c..412796914a 100644 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index 3f3f6d5f78..3c3eba069b 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2020 The coreboot project Authors. ## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl index 74769e3390..1a06678a13 100644 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h index cc897dcdcf..70bd8e7785 100644 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h index bf23f6e457..fd92743190 100644 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ From 078bc41ce21c282d4d0ef10595c2c80d274865a0 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 12:51:24 +0100 Subject: [PATCH 0502/1463] mainboard/[g-p]*: Remove copyright notices They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn Reviewed-by: Angel Pons Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/mainboard/getac/Kconfig | 1 - src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/getac/p470/Makefile.inc | 1 - src/mainboard/getac/p470/acpi/battery.asl | 1 - src/mainboard/getac/p470/acpi/ec.asl | 1 - src/mainboard/getac/p470/acpi/gpe.asl | 1 - src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/getac/p470/acpi/mainboard.asl | 1 - src/mainboard/getac/p470/acpi/platform.asl | 1 - src/mainboard/getac/p470/acpi/superio.asl | 1 - src/mainboard/getac/p470/acpi/thermal.asl | 1 - src/mainboard/getac/p470/acpi_tables.c | 1 - src/mainboard/getac/p470/cmos.layout | 1 - src/mainboard/getac/p470/devicetree.cb | 1 - src/mainboard/getac/p470/dsdt.asl | 1 - src/mainboard/getac/p470/early_init.c | 1 - src/mainboard/getac/p470/ec_oem.c | 1 - src/mainboard/getac/p470/ec_oem.h | 1 - src/mainboard/getac/p470/gpio.c | 1 - src/mainboard/getac/p470/hda_verb.c | 1 - src/mainboard/getac/p470/irq_tables.c | 1 - src/mainboard/getac/p470/mainboard.c | 1 - src/mainboard/getac/p470/mptable.c | 1 - src/mainboard/getac/p470/smihandler.c | 1 - src/mainboard/gigabyte/Kconfig | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 2 -- src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 2 -- src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c | 2 -- src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c | 1 - src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 1 - src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 1 - src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl | 1 - src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl | 1 - src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl | 1 - src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 1 - src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 2 -- src/mainboard/gigabyte/ga-b75m-d3h/early_init.c | 1 - src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 3 --- src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 2 -- .../ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads | 1 - src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c | 2 -- .../ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads | 1 - src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 - src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c | 2 -- src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 2 -- src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 1 - src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 1 - src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 2 -- src/mainboard/gigabyte/ga-g41m-es2l/early_init.c | 1 - src/mainboard/gigabyte/ga-g41m-es2l/gpio.c | 1 - src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout | 2 -- src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb | 1 - .../gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c | 2 -- .../gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c | 1 - src/mainboard/gizmosphere/Kconfig | 1 - src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 1 - src/mainboard/gizmosphere/gizmo/Kconfig | 2 -- src/mainboard/gizmosphere/gizmo/Makefile.inc | 2 -- src/mainboard/gizmosphere/gizmo/OemCustomize.c | 2 -- src/mainboard/gizmosphere/gizmo/OptionsIds.h | 2 -- src/mainboard/gizmosphere/gizmo/acpi/gpe.asl | 2 -- src/mainboard/gizmosphere/gizmo/acpi/ide.asl | 2 -- src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl | 2 -- src/mainboard/gizmosphere/gizmo/acpi/routing.asl | 2 -- src/mainboard/gizmosphere/gizmo/acpi/sata.asl | 2 -- src/mainboard/gizmosphere/gizmo/acpi/sleep.asl | 2 -- src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl | 2 -- src/mainboard/gizmosphere/gizmo/acpi_tables.c | 2 -- src/mainboard/gizmosphere/gizmo/buildOpts.c | 2 -- src/mainboard/gizmosphere/gizmo/cmos.layout | 2 -- src/mainboard/gizmosphere/gizmo/devicetree.cb | 2 -- src/mainboard/gizmosphere/gizmo/dsdt.asl | 2 -- src/mainboard/gizmosphere/gizmo/irq_tables.c | 2 -- src/mainboard/gizmosphere/gizmo/mainboard.c | 2 -- src/mainboard/gizmosphere/gizmo/mptable.c | 2 -- src/mainboard/gizmosphere/gizmo/platform_cfg.h | 2 -- src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c | 1 - src/mainboard/gizmosphere/gizmo2/Kconfig | 2 -- src/mainboard/gizmosphere/gizmo2/Makefile.inc | 2 -- src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex | 1 - src/mainboard/gizmosphere/gizmo2/OemCustomize.c | 1 - src/mainboard/gizmosphere/gizmo2/OptionsIds.h | 1 - src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl | 1 - src/mainboard/gizmosphere/gizmo2/acpi/ide.asl | 1 - src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl | 1 - src/mainboard/gizmosphere/gizmo2/acpi/routing.asl | 2 -- src/mainboard/gizmosphere/gizmo2/acpi/sata.asl | 1 - src/mainboard/gizmosphere/gizmo2/acpi/si.asl | 1 - src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl | 1 - src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl | 2 -- src/mainboard/gizmosphere/gizmo2/acpi_tables.c | 1 - src/mainboard/gizmosphere/gizmo2/buildOpts.c | 1 - src/mainboard/gizmosphere/gizmo2/cmos.layout | 1 - src/mainboard/gizmosphere/gizmo2/devicetree.cb | 1 - src/mainboard/gizmosphere/gizmo2/dsdt.asl | 2 -- src/mainboard/gizmosphere/gizmo2/irq_tables.c | 1 - src/mainboard/gizmosphere/gizmo2/mainboard.c | 3 --- src/mainboard/gizmosphere/gizmo2/mptable.c | 1 - src/mainboard/hp/abm/BiosCallOuts.c | 2 -- src/mainboard/hp/abm/Kconfig | 2 -- src/mainboard/hp/abm/Makefile.inc | 1 - src/mainboard/hp/abm/OemCustomize.c | 2 -- src/mainboard/hp/abm/OptionsIds.h | 2 -- src/mainboard/hp/abm/acpi/gpe.asl | 1 - src/mainboard/hp/abm/acpi/ide.asl | 1 - src/mainboard/hp/abm/acpi/mainboard.asl | 1 - src/mainboard/hp/abm/acpi/routing.asl | 2 -- src/mainboard/hp/abm/acpi/sata.asl | 1 - src/mainboard/hp/abm/acpi/si.asl | 1 - src/mainboard/hp/abm/acpi/sleep.asl | 1 - src/mainboard/hp/abm/acpi/usb_oc.asl | 2 -- src/mainboard/hp/abm/acpi_tables.c | 1 - src/mainboard/hp/abm/buildOpts.c | 2 -- src/mainboard/hp/abm/cmos.layout | 1 - src/mainboard/hp/abm/devicetree.cb | 2 -- src/mainboard/hp/abm/dsdt.asl | 2 -- src/mainboard/hp/abm/irq_tables.c | 1 - src/mainboard/hp/abm/mainboard.c | 2 -- src/mainboard/hp/abm/mptable.c | 1 - src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl | 1 - src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl | 1 - src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c | 3 --- src/mainboard/hp/compaq_8200_elite_sff/cmos.layout | 3 --- src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb | 1 - src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl | 1 - src/mainboard/hp/compaq_8200_elite_sff/early_init.c | 3 --- src/mainboard/hp/compaq_8200_elite_sff/gpio.c | 3 --- src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c | 2 -- src/mainboard/hp/compaq_8200_elite_sff/mainboard.c | 2 -- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 - src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 1 - src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h | 1 - src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 1 - src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 1 - src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 1 - src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl | 2 -- src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl | 1 - src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl | 1 - src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl | 2 -- src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb | 1 - src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 2 -- src/mainboard/hp/pavilion_m6_1035dx/ec.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/ec.h | 1 - src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mainboard.h | 1 - src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 1 - src/mainboard/hp/snb_ivb_laptops/Kconfig | 1 - src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 1 - src/mainboard/hp/snb_ivb_laptops/Makefile.inc | 1 - src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl | 1 - src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl | 1 - src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl | 1 - src/mainboard/hp/snb_ivb_laptops/acpi_tables.c | 2 -- src/mainboard/hp/snb_ivb_laptops/cmos.layout | 2 -- src/mainboard/hp/snb_ivb_laptops/devicetree.cb | 1 - src/mainboard/hp/snb_ivb_laptops/dsdt.asl | 1 - src/mainboard/hp/snb_ivb_laptops/mainboard.c | 1 - src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c | 1 - src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c | 2 -- src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c | 2 -- .../hp/snb_ivb_laptops/variants/2570p/overridetree.cb | 1 - src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c | 1 - src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c | 1 - src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c | 3 --- .../hp/snb_ivb_laptops/variants/2760p/overridetree.cb | 1 - src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c | 1 - src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c | 2 -- src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c | 2 -- .../hp/snb_ivb_laptops/variants/8460p/overridetree.cb | 1 - src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c | 1 - src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c | 2 -- src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c | 3 --- .../hp/snb_ivb_laptops/variants/8470p/overridetree.cb | 1 - src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c | 2 -- src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c | 2 -- src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c | 4 ---- .../hp/snb_ivb_laptops/variants/8770w/overridetree.cb | 2 -- .../hp/snb_ivb_laptops/variants/folio_9470m/early_init.c | 2 -- src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c | 2 -- .../hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c | 2 -- .../hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb | 1 - .../hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c | 2 -- .../hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c | 2 -- .../hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c | 2 -- .../snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb | 1 - src/mainboard/hp/z220_sff_workstation/acpi/platform.asl | 1 - src/mainboard/hp/z220_sff_workstation/acpi/superio.asl | 1 - src/mainboard/hp/z220_sff_workstation/acpi_tables.c | 3 --- src/mainboard/hp/z220_sff_workstation/cmos.layout | 3 --- src/mainboard/hp/z220_sff_workstation/devicetree.cb | 1 - src/mainboard/hp/z220_sff_workstation/dsdt.asl | 1 - src/mainboard/hp/z220_sff_workstation/early_init.c | 3 --- src/mainboard/hp/z220_sff_workstation/gpio.c | 2 -- src/mainboard/hp/z220_sff_workstation/hda_verb.c | 2 -- src/mainboard/hp/z220_sff_workstation/mainboard.c | 2 -- src/mainboard/ibase/mb899/acpi/ec.asl | 1 - src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/ibase/mb899/acpi/platform.asl | 1 - src/mainboard/ibase/mb899/acpi/superio.asl | 1 - src/mainboard/ibase/mb899/acpi_tables.c | 1 - src/mainboard/ibase/mb899/cmos.layout | 1 - src/mainboard/ibase/mb899/dsdt.asl | 1 - src/mainboard/ibase/mb899/early_init.c | 1 - src/mainboard/ibase/mb899/irq_tables.c | 1 - src/mainboard/ibase/mb899/mainboard.c | 1 - src/mainboard/ibase/mb899/mptable.c | 1 - src/mainboard/ibase/mb899/superio_hwm.c | 2 -- src/mainboard/ibase/mb899/superio_hwm.h | 1 - src/mainboard/intel/apollolake_rvp/dsdt.asl | 2 -- src/mainboard/intel/apollolake_rvp/romstage.c | 2 -- src/mainboard/intel/baskingridge/Makefile.inc | 1 - src/mainboard/intel/baskingridge/acpi/mainboard.asl | 1 - src/mainboard/intel/baskingridge/acpi/platform.asl | 2 -- src/mainboard/intel/baskingridge/acpi/superio.asl | 1 - src/mainboard/intel/baskingridge/acpi/thermal.asl | 1 - src/mainboard/intel/baskingridge/acpi_tables.c | 1 - src/mainboard/intel/baskingridge/chromeos.c | 1 - src/mainboard/intel/baskingridge/cmos.layout | 1 - src/mainboard/intel/baskingridge/dsdt.asl | 2 -- src/mainboard/intel/baskingridge/gpio.h | 1 - src/mainboard/intel/baskingridge/hda_verb.c | 1 - src/mainboard/intel/baskingridge/mainboard.c | 2 -- src/mainboard/intel/baskingridge/mainboard_smi.c | 1 - src/mainboard/intel/baskingridge/romstage.c | 2 -- src/mainboard/intel/baskingridge/thermal.h | 1 - src/mainboard/intel/cannonlake_rvp/Makefile.inc | 2 -- src/mainboard/intel/cannonlake_rvp/bootblock.c | 1 - src/mainboard/intel/cannonlake_rvp/chromeos.c | 1 - src/mainboard/intel/cannonlake_rvp/dsdt.asl | 3 --- src/mainboard/intel/cannonlake_rvp/mainboard.c | 1 - src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c | 1 - src/mainboard/intel/cannonlake_rvp/smihandler.c | 2 -- src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc | 2 -- src/mainboard/intel/cannonlake_rvp/spd/spd.h | 2 -- src/mainboard/intel/cannonlake_rvp/spd/spd_util.c | 1 - src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c | 1 - .../variants/baseboard/include/baseboard/gpio.h | 1 - .../variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c | 1 - .../cannonlake_rvp/variants/cnl_u/include/variant/gpio.h | 1 - .../cannonlake_rvp/variants/cnl_y/include/variant/gpio.h | 1 - src/mainboard/intel/coffeelake_rvp/Makefile.inc | 2 -- src/mainboard/intel/coffeelake_rvp/bootblock.c | 1 - src/mainboard/intel/coffeelake_rvp/chromeos.c | 1 - src/mainboard/intel/coffeelake_rvp/dsdt.asl | 3 --- src/mainboard/intel/coffeelake_rvp/hda_verb.c | 1 - src/mainboard/intel/coffeelake_rvp/mainboard.c | 1 - src/mainboard/intel/coffeelake_rvp/memory.c | 2 -- src/mainboard/intel/coffeelake_rvp/romstage.c | 2 -- src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c | 1 - .../variants/baseboard/include/baseboard/gpio.h | 1 - .../variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c | 1 - .../coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h | 2 -- .../coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h | 2 -- .../coffeelake_rvp/variants/cml_u/include/variant/gpio.h | 1 - .../coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h | 1 - .../coffeelake_rvp/variants/whl_u/include/variant/gpio.h | 1 - .../coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h | 1 - src/mainboard/intel/d510mo/Kconfig | 1 - src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl | 2 -- src/mainboard/intel/d510mo/acpi_tables.c | 1 - src/mainboard/intel/d510mo/cmos.layout | 2 -- src/mainboard/intel/d510mo/cstates.c | 1 - src/mainboard/intel/d510mo/devicetree.cb | 1 - src/mainboard/intel/d510mo/dsdt.asl | 2 -- src/mainboard/intel/d510mo/early_init.c | 1 - src/mainboard/intel/d510mo/gpio.c | 1 - src/mainboard/intel/d510mo/hda_verb.c | 1 - src/mainboard/intel/d510mo/mainboard.c | 1 - src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/intel/d945gclf/acpi/ec.asl | 1 - src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/intel/d945gclf/acpi/mainboard.asl | 1 - src/mainboard/intel/d945gclf/acpi/platform.asl | 1 - src/mainboard/intel/d945gclf/acpi/superio.asl | 1 - src/mainboard/intel/d945gclf/acpi_tables.c | 1 - src/mainboard/intel/d945gclf/cmos.layout | 1 - src/mainboard/intel/d945gclf/devicetree.cb | 1 - src/mainboard/intel/d945gclf/dsdt.asl | 1 - src/mainboard/intel/d945gclf/early_init.c | 1 - src/mainboard/intel/d945gclf/gpio.c | 1 - src/mainboard/intel/d945gclf/irq_tables.c | 1 - src/mainboard/intel/d945gclf/mptable.c | 1 - src/mainboard/intel/dcp847ske/acpi/platform.asl | 1 - src/mainboard/intel/dcp847ske/acpi/superio.asl | 2 -- src/mainboard/intel/dcp847ske/acpi_tables.c | 2 -- src/mainboard/intel/dcp847ske/dsdt.asl | 1 - src/mainboard/intel/dcp847ske/early_southbridge.c | 3 --- src/mainboard/intel/dcp847ske/gma-mainboard.ads | 1 - src/mainboard/intel/dcp847ske/gpio.c | 2 -- src/mainboard/intel/dcp847ske/hda_verb.c | 2 -- src/mainboard/intel/dcp847ske/mainboard.c | 1 - src/mainboard/intel/dcp847ske/romstage.c | 3 --- src/mainboard/intel/dcp847ske/smihandler.c | 1 - src/mainboard/intel/dcp847ske/superio.h | 1 - src/mainboard/intel/dcp847ske/thermal.h | 3 --- src/mainboard/intel/dcp847ske/usb.h | 1 - src/mainboard/intel/dg41wv/Kconfig | 2 -- src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/intel/dg41wv/acpi_tables.c | 2 -- src/mainboard/intel/dg41wv/cmos.layout | 2 -- src/mainboard/intel/dg41wv/cstates.c | 1 - src/mainboard/intel/dg41wv/devicetree.cb | 1 - src/mainboard/intel/dg41wv/dsdt.asl | 2 -- src/mainboard/intel/dg41wv/early_init.c | 2 -- src/mainboard/intel/dg41wv/gpio.c | 1 - src/mainboard/intel/dg41wv/hda_verb.c | 1 - src/mainboard/intel/dg43gt/Kconfig | 2 -- src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl | 1 - src/mainboard/intel/dg43gt/acpi_tables.c | 2 -- src/mainboard/intel/dg43gt/cmos.layout | 2 -- src/mainboard/intel/dg43gt/devicetree.cb | 2 -- src/mainboard/intel/dg43gt/dsdt.asl | 2 -- src/mainboard/intel/dg43gt/early_init.c | 1 - src/mainboard/intel/dg43gt/gpio.c | 1 - src/mainboard/intel/dg43gt/hda_verb.c | 1 - src/mainboard/intel/emeraldlake2/Makefile.inc | 1 - src/mainboard/intel/emeraldlake2/acpi/mainboard.asl | 1 - src/mainboard/intel/emeraldlake2/acpi/platform.asl | 2 -- src/mainboard/intel/emeraldlake2/acpi/superio.asl | 1 - src/mainboard/intel/emeraldlake2/acpi/thermal.asl | 1 - src/mainboard/intel/emeraldlake2/acpi_tables.c | 1 - src/mainboard/intel/emeraldlake2/chromeos.c | 1 - src/mainboard/intel/emeraldlake2/cmos.layout | 1 - src/mainboard/intel/emeraldlake2/dsdt.asl | 2 -- src/mainboard/intel/emeraldlake2/early_init.c | 2 -- src/mainboard/intel/emeraldlake2/ec.c | 1 - src/mainboard/intel/emeraldlake2/ec.h | 1 - src/mainboard/intel/emeraldlake2/gpio.c | 1 - src/mainboard/intel/emeraldlake2/hda_verb.c | 1 - src/mainboard/intel/emeraldlake2/mainboard.c | 2 -- src/mainboard/intel/emeraldlake2/smihandler.c | 1 - src/mainboard/intel/emeraldlake2/thermal.h | 1 - src/mainboard/intel/galileo/Kconfig | 1 - src/mainboard/intel/galileo/Kconfig.name | 1 - src/mainboard/intel/galileo/Makefile.inc | 1 - src/mainboard/intel/galileo/acpi_tables.c | 2 -- src/mainboard/intel/galileo/devicetree.cb | 2 -- src/mainboard/intel/galileo/dsdt.asl | 3 --- src/mainboard/intel/galileo/gen1.h | 1 - src/mainboard/intel/galileo/gen2.h | 1 - src/mainboard/intel/galileo/gpio.c | 1 - src/mainboard/intel/galileo/mainboard.c | 1 - src/mainboard/intel/galileo/reg_access.c | 1 - src/mainboard/intel/galileo/reg_access.h | 1 - src/mainboard/intel/galileo/sd.c | 1 - src/mainboard/intel/glkrvp/boardid.c | 1 - src/mainboard/intel/glkrvp/bootblock.c | 1 - src/mainboard/intel/glkrvp/chromeos.c | 1 - src/mainboard/intel/glkrvp/dsdt.asl | 1 - src/mainboard/intel/glkrvp/ec.c | 1 - src/mainboard/intel/glkrvp/mainboard.c | 1 - src/mainboard/intel/glkrvp/romstage.c | 1 - src/mainboard/intel/glkrvp/smihandler.c | 1 - src/mainboard/intel/glkrvp/touchpad.asl | 1 - src/mainboard/intel/glkrvp/touchpanel.asl | 1 - src/mainboard/intel/glkrvp/variants/baseboard/boardid.c | 1 - src/mainboard/intel/glkrvp/variants/baseboard/gpio.c | 1 - .../glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl | 1 - .../intel/glkrvp/variants/baseboard/include/baseboard/ec.h | 1 - .../intel/glkrvp/variants/baseboard/include/baseboard/gpio.h | 1 - .../glkrvp/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/intel/glkrvp/variants/baseboard/memory.c | 1 - src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c | 1 - .../glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl | 1 - .../intel/glkrvp/variants/glkrvp/include/variant/ec.h | 1 - .../intel/glkrvp/variants/glkrvp/include/variant/gpio.h | 1 - src/mainboard/intel/harcuvar/Kconfig | 1 - src/mainboard/intel/harcuvar/Makefile.inc | 2 -- src/mainboard/intel/harcuvar/acpi/mainboard.asl | 2 -- src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl | 1 - src/mainboard/intel/harcuvar/acpi/platform.asl | 3 --- src/mainboard/intel/harcuvar/acpi/thermal.asl | 1 - src/mainboard/intel/harcuvar/acpi_tables.c | 2 -- src/mainboard/intel/harcuvar/boardid.c | 1 - src/mainboard/intel/harcuvar/devicetree.cb | 1 - src/mainboard/intel/harcuvar/dsdt.asl | 3 --- src/mainboard/intel/harcuvar/emmc.h | 1 - src/mainboard/intel/harcuvar/fadt.c | 2 -- src/mainboard/intel/harcuvar/gpio.h | 1 - src/mainboard/intel/harcuvar/harcuvar_boardid.h | 1 - src/mainboard/intel/harcuvar/hsio.c | 2 -- src/mainboard/intel/harcuvar/hsio.h | 1 - src/mainboard/intel/harcuvar/ramstage.c | 1 - src/mainboard/intel/harcuvar/romstage.c | 1 - src/mainboard/intel/harcuvar/spd/Makefile.inc | 2 -- src/mainboard/intel/harcuvar/spd/spd.c | 2 -- src/mainboard/intel/harcuvar/spd/spd.h | 2 -- src/mainboard/intel/icelake_rvp/Makefile.inc | 1 - src/mainboard/intel/icelake_rvp/acpi/mainboard.asl | 1 - src/mainboard/intel/icelake_rvp/board_id.c | 1 - src/mainboard/intel/icelake_rvp/board_id.h | 1 - src/mainboard/intel/icelake_rvp/bootblock.c | 1 - src/mainboard/intel/icelake_rvp/chromeos.c | 1 - src/mainboard/intel/icelake_rvp/dsdt.asl | 1 - src/mainboard/intel/icelake_rvp/hda_verb.c | 1 - src/mainboard/intel/icelake_rvp/mainboard.c | 1 - src/mainboard/intel/icelake_rvp/romstage_fsp_params.c | 1 - src/mainboard/intel/icelake_rvp/spd/Makefile.inc | 1 - src/mainboard/intel/icelake_rvp/spd/spd.h | 1 - src/mainboard/intel/icelake_rvp/spd/spd_util.c | 1 - .../icelake_rvp/variants/baseboard/include/baseboard/ec.h | 1 - .../icelake_rvp/variants/baseboard/include/baseboard/gpio.h | 1 - .../variants/baseboard/include/baseboard/hda_verb.h | 1 - .../variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc | 1 - src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c | 1 - src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc | 1 - src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c | 1 - src/mainboard/intel/jasperlake_rvp/Makefile.inc | 1 - src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl | 1 - src/mainboard/intel/jasperlake_rvp/board_id.c | 1 - src/mainboard/intel/jasperlake_rvp/board_id.h | 1 - src/mainboard/intel/jasperlake_rvp/bootblock.c | 1 - src/mainboard/intel/jasperlake_rvp/chromeos.c | 1 - src/mainboard/intel/jasperlake_rvp/dsdt.asl | 1 - src/mainboard/intel/jasperlake_rvp/mainboard.c | 1 - src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c | 1 - src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc | 1 - src/mainboard/intel/jasperlake_rvp/spd/spd.h | 1 - src/mainboard/intel/jasperlake_rvp/spd/spd_util.c | 1 - .../jasperlake_rvp/variants/baseboard/include/baseboard/ec.h | 1 - .../variants/baseboard/include/baseboard/gpio.h | 1 - .../variants/baseboard/include/baseboard/variants.h | 1 - .../intel/jasperlake_rvp/variants/jslrvp/Makefile.inc | 1 - src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c | 1 - src/mainboard/intel/kblrvp/Makefile.inc | 2 -- src/mainboard/intel/kblrvp/acpi/dptf.asl | 2 -- src/mainboard/intel/kblrvp/acpi/ec.asl | 1 - src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl | 1 - src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 -- src/mainboard/intel/kblrvp/acpi/mipi_camera.asl | 1 - src/mainboard/intel/kblrvp/acpi/superio.asl | 1 - src/mainboard/intel/kblrvp/board_id.c | 1 - src/mainboard/intel/kblrvp/board_id.h | 1 - src/mainboard/intel/kblrvp/bootblock.c | 1 - src/mainboard/intel/kblrvp/chromeos.c | 2 -- src/mainboard/intel/kblrvp/cmos.layout | 2 -- src/mainboard/intel/kblrvp/dsdt.asl | 3 --- src/mainboard/intel/kblrvp/ec.c | 2 -- src/mainboard/intel/kblrvp/ec.h | 2 -- src/mainboard/intel/kblrvp/hda_verb.c | 2 -- src/mainboard/intel/kblrvp/mainboard.c | 3 --- src/mainboard/intel/kblrvp/ramstage.c | 1 - src/mainboard/intel/kblrvp/romstage.c | 1 - src/mainboard/intel/kblrvp/smihandler.c | 2 -- src/mainboard/intel/kblrvp/spd/Makefile.inc | 2 -- src/mainboard/intel/kblrvp/spd/spd.h | 2 -- src/mainboard/intel/kblrvp/spd/spd_util.c | 1 - .../intel/kblrvp/variants/rvp11/include/variant/gpio.h | 1 - .../intel/kblrvp/variants/rvp11/include/variant/hda_verb.h | 1 - .../intel/kblrvp/variants/rvp3/include/variant/gpio.h | 2 -- .../intel/kblrvp/variants/rvp3/include/variant/hda_verb.h | 2 -- .../intel/kblrvp/variants/rvp7/include/variant/gpio.h | 2 -- .../intel/kblrvp/variants/rvp7/include/variant/hda_verb.h | 2 -- .../intel/kblrvp/variants/rvp8/include/variant/gpio.h | 1 - src/mainboard/intel/kunimitsu/Makefile.inc | 2 -- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 2 -- src/mainboard/intel/kunimitsu/acpi/ec.asl | 1 - src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 2 -- src/mainboard/intel/kunimitsu/acpi/superio.asl | 1 - src/mainboard/intel/kunimitsu/bootblock_mainboard.c | 1 - src/mainboard/intel/kunimitsu/chromeos.c | 2 -- src/mainboard/intel/kunimitsu/cmos.layout | 2 -- src/mainboard/intel/kunimitsu/dsdt.asl | 3 --- src/mainboard/intel/kunimitsu/ec.c | 2 -- src/mainboard/intel/kunimitsu/ec.h | 2 -- src/mainboard/intel/kunimitsu/gpio.h | 2 -- src/mainboard/intel/kunimitsu/mainboard.c | 3 --- src/mainboard/intel/kunimitsu/ramstage.c | 1 - src/mainboard/intel/kunimitsu/romstage.c | 1 - src/mainboard/intel/kunimitsu/smihandler.c | 2 -- src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 -- src/mainboard/intel/kunimitsu/spd/spd.h | 2 -- src/mainboard/intel/kunimitsu/spd/spd_util.c | 1 - src/mainboard/intel/leafhill/bootblock.c | 1 - src/mainboard/intel/leafhill/brd_gpio.h | 1 - src/mainboard/intel/leafhill/dsdt.asl | 1 - src/mainboard/intel/leafhill/mainboard.c | 1 - src/mainboard/intel/leafhill/romstage.c | 1 - src/mainboard/intel/minnow3/bootblock.c | 1 - src/mainboard/intel/minnow3/dsdt.asl | 1 - src/mainboard/intel/minnow3/gpio.c | 1 - src/mainboard/intel/minnow3/gpio.h | 1 - src/mainboard/intel/minnow3/mainboard.c | 1 - src/mainboard/intel/minnow3/romstage.c | 1 - src/mainboard/intel/saddlebrook/Kconfig | 1 - src/mainboard/intel/saddlebrook/Makefile.inc | 2 -- src/mainboard/intel/saddlebrook/acpi/mainboard.asl | 2 -- src/mainboard/intel/saddlebrook/bootblock.c | 1 - src/mainboard/intel/saddlebrook/cmos.layout | 2 -- src/mainboard/intel/saddlebrook/devicetree.cb | 1 - src/mainboard/intel/saddlebrook/dsdt.asl | 3 --- src/mainboard/intel/saddlebrook/gpio.h | 2 -- src/mainboard/intel/saddlebrook/ramstage.c | 1 - src/mainboard/intel/saddlebrook/romstage.c | 3 --- src/mainboard/intel/saddlebrook/spd/Makefile.inc | 2 -- src/mainboard/intel/saddlebrook/spd/spd.h | 2 -- src/mainboard/intel/saddlebrook/spd/spd_util.c | 1 - src/mainboard/intel/strago/Makefile.inc | 2 -- src/mainboard/intel/strago/acpi/dptf.asl | 2 -- src/mainboard/intel/strago/acpi/ec.asl | 2 -- src/mainboard/intel/strago/acpi/mainboard.asl | 2 -- src/mainboard/intel/strago/acpi/superio.asl | 2 -- src/mainboard/intel/strago/acpi_tables.c | 2 -- src/mainboard/intel/strago/chromeos.c | 2 -- src/mainboard/intel/strago/cmos.layout | 2 -- src/mainboard/intel/strago/com_init.c | 2 -- src/mainboard/intel/strago/dsdt.asl | 3 --- src/mainboard/intel/strago/ec.c | 2 -- src/mainboard/intel/strago/ec.h | 2 -- src/mainboard/intel/strago/fadt.c | 2 -- src/mainboard/intel/strago/gpio.c | 2 -- src/mainboard/intel/strago/irqroute.c | 2 -- src/mainboard/intel/strago/irqroute.h | 2 -- src/mainboard/intel/strago/mainboard.c | 3 --- src/mainboard/intel/strago/onboard.h | 2 -- src/mainboard/intel/strago/ramstage.c | 1 - src/mainboard/intel/strago/romstage.c | 2 -- src/mainboard/intel/strago/smihandler.c | 2 -- src/mainboard/intel/strago/w25q64.c | 2 -- src/mainboard/intel/tglrvp/Makefile.inc | 1 - src/mainboard/intel/tglrvp/acpi/mainboard.asl | 1 - src/mainboard/intel/tglrvp/acpi/mipi_camera.asl | 1 - src/mainboard/intel/tglrvp/board_id.c | 1 - src/mainboard/intel/tglrvp/board_id.h | 1 - src/mainboard/intel/tglrvp/bootblock.c | 1 - src/mainboard/intel/tglrvp/chromeos.c | 1 - src/mainboard/intel/tglrvp/dsdt.asl | 1 - src/mainboard/intel/tglrvp/mainboard.c | 1 - src/mainboard/intel/tglrvp/romstage_fsp_params.c | 1 - src/mainboard/intel/tglrvp/spd/Makefile.inc | 1 - src/mainboard/intel/tglrvp/spd/spd.h | 1 - src/mainboard/intel/tglrvp/spd/spd_util.c | 1 - .../intel/tglrvp/variants/baseboard/include/baseboard/ec.h | 1 - .../intel/tglrvp/variants/baseboard/include/baseboard/gpio.h | 1 - .../tglrvp/variants/baseboard/include/baseboard/variants.h | 1 - src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc | 1 - src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 1 - src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c | 1 - src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc | 1 - src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c | 1 - src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c | 1 - src/mainboard/intel/wtm2/Makefile.inc | 1 - src/mainboard/intel/wtm2/acpi/mainboard.asl | 1 - src/mainboard/intel/wtm2/acpi/platform.asl | 2 -- src/mainboard/intel/wtm2/acpi/thermal.asl | 1 - src/mainboard/intel/wtm2/acpi_tables.c | 1 - src/mainboard/intel/wtm2/chromeos.c | 1 - src/mainboard/intel/wtm2/cmos.layout | 1 - src/mainboard/intel/wtm2/dsdt.asl | 2 -- src/mainboard/intel/wtm2/fadt.c | 1 - src/mainboard/intel/wtm2/gpio.c | 1 - src/mainboard/intel/wtm2/hda_verb.c | 1 - src/mainboard/intel/wtm2/mainboard.c | 2 -- src/mainboard/intel/wtm2/pei_data.c | 2 -- src/mainboard/intel/wtm2/romstage.c | 2 -- src/mainboard/intel/wtm2/thermal.h | 1 - src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 1 - src/mainboard/jetway/nf81-t56n-lf/Kconfig | 2 -- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 1 - src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c | 2 -- src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 1 - src/mainboard/jetway/nf81-t56n-lf/bootblock.c | 2 -- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 1 - src/mainboard/jetway/nf81-t56n-lf/cmos.layout | 1 - src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 -- src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 1 - src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 1 - src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 3 --- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 3 --- src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 2 -- src/mainboard/kontron/986lcd-m/acpi/ec.asl | 1 - src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/kontron/986lcd-m/acpi/platform.asl | 1 - src/mainboard/kontron/986lcd-m/acpi/superio.asl | 1 - src/mainboard/kontron/986lcd-m/acpi_tables.c | 1 - src/mainboard/kontron/986lcd-m/cmos.layout | 1 - src/mainboard/kontron/986lcd-m/dsdt.asl | 1 - src/mainboard/kontron/986lcd-m/early_init.c | 1 - src/mainboard/kontron/986lcd-m/gpio.c | 1 - src/mainboard/kontron/986lcd-m/irq_tables.c | 1 - src/mainboard/kontron/986lcd-m/mainboard.c | 1 - src/mainboard/kontron/986lcd-m/mptable.c | 1 - src/mainboard/kontron/ktqm77/acpi/mainboard.asl | 1 - src/mainboard/kontron/ktqm77/acpi/platform.asl | 2 -- src/mainboard/kontron/ktqm77/acpi/thermal.asl | 2 -- src/mainboard/kontron/ktqm77/acpi_tables.c | 1 - src/mainboard/kontron/ktqm77/cmos.layout | 1 - src/mainboard/kontron/ktqm77/dsdt.asl | 2 -- src/mainboard/kontron/ktqm77/early_init.c | 2 -- src/mainboard/kontron/ktqm77/gpio.c | 1 - src/mainboard/kontron/ktqm77/hda_verb.c | 2 -- src/mainboard/kontron/ktqm77/mainboard.c | 3 --- src/mainboard/kontron/ktqm77/thermal.h | 1 - src/mainboard/lenovo/g505s/BiosCallOuts.c | 1 - src/mainboard/lenovo/g505s/Kconfig | 1 - src/mainboard/lenovo/g505s/Makefile.inc | 1 - src/mainboard/lenovo/g505s/OemCustomize.c | 1 - src/mainboard/lenovo/g505s/OptionsIds.h | 1 - src/mainboard/lenovo/g505s/acpi/ec.asl | 1 - src/mainboard/lenovo/g505s/acpi/gpe.asl | 1 - src/mainboard/lenovo/g505s/acpi/mainboard.asl | 1 - src/mainboard/lenovo/g505s/acpi/routing.asl | 2 -- src/mainboard/lenovo/g505s/acpi/si.asl | 1 - src/mainboard/lenovo/g505s/acpi/sleep.asl | 1 - src/mainboard/lenovo/g505s/acpi/superio.asl | 1 - src/mainboard/lenovo/g505s/acpi/usb_oc.asl | 2 -- src/mainboard/lenovo/g505s/acpi_tables.c | 1 - src/mainboard/lenovo/g505s/buildOpts.c | 1 - src/mainboard/lenovo/g505s/cmos.layout | 1 - src/mainboard/lenovo/g505s/devicetree.cb | 1 - src/mainboard/lenovo/g505s/dsdt.asl | 2 -- src/mainboard/lenovo/g505s/ec.c | 1 - src/mainboard/lenovo/g505s/ec.h | 1 - src/mainboard/lenovo/g505s/irq_tables.c | 1 - src/mainboard/lenovo/g505s/mainboard.c | 1 - src/mainboard/lenovo/g505s/mainboard.h | 1 - src/mainboard/lenovo/g505s/mainboard_smi.c | 1 - src/mainboard/lenovo/g505s/mptable.c | 1 - src/mainboard/lenovo/l520/Makefile.inc | 1 - src/mainboard/lenovo/l520/acpi/ec.asl | 1 - src/mainboard/lenovo/l520/acpi/platform.asl | 1 - src/mainboard/lenovo/l520/acpi/superio.asl | 1 - src/mainboard/lenovo/l520/acpi_tables.c | 2 -- src/mainboard/lenovo/l520/cmos.layout | 2 -- src/mainboard/lenovo/l520/early_init.c | 2 -- src/mainboard/lenovo/l520/gpio.c | 2 -- src/mainboard/lenovo/l520/hda_verb.c | 2 -- src/mainboard/lenovo/l520/mainboard.c | 2 -- src/mainboard/lenovo/l520/smihandler.c | 2 -- src/mainboard/lenovo/s230u/acpi/ec.asl | 3 --- src/mainboard/lenovo/s230u/acpi/gpe.asl | 1 - src/mainboard/lenovo/s230u/acpi/platform.asl | 1 - src/mainboard/lenovo/s230u/acpi_tables.c | 1 - src/mainboard/lenovo/s230u/early_init.c | 1 - src/mainboard/lenovo/s230u/ec.c | 1 - src/mainboard/lenovo/s230u/ec.h | 1 - src/mainboard/lenovo/s230u/gpio.c | 1 - src/mainboard/lenovo/s230u/hda_verb.c | 3 --- src/mainboard/lenovo/s230u/mainboard.c | 3 --- src/mainboard/lenovo/s230u/smihandler.c | 3 --- src/mainboard/lenovo/t400/Makefile.inc | 1 - src/mainboard/lenovo/t400/acpi/dock.asl | 1 - src/mainboard/lenovo/t400/acpi/gpe.asl | 1 - src/mainboard/lenovo/t400/acpi/graphics.asl | 1 - src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl | 1 - src/mainboard/lenovo/t400/acpi/platform.asl | 1 - src/mainboard/lenovo/t400/acpi_tables.c | 1 - src/mainboard/lenovo/t400/blc.c | 1 - src/mainboard/lenovo/t400/cmos.layout | 2 -- src/mainboard/lenovo/t400/cstates.c | 1 - src/mainboard/lenovo/t400/dock.c | 2 -- src/mainboard/lenovo/t400/dock.h | 1 - src/mainboard/lenovo/t400/dsdt.asl | 1 - src/mainboard/lenovo/t400/fadt.c | 1 - src/mainboard/lenovo/t400/hda_verb.c | 2 -- src/mainboard/lenovo/t400/mainboard.c | 1 - src/mainboard/lenovo/t400/romstage.c | 1 - src/mainboard/lenovo/t410/Makefile.inc | 1 - src/mainboard/lenovo/t410/acpi/dock.asl | 1 - src/mainboard/lenovo/t410/acpi/ec.asl | 1 - src/mainboard/lenovo/t410/acpi/gpe.asl | 1 - src/mainboard/lenovo/t410/acpi/platform.asl | 1 - src/mainboard/lenovo/t410/acpi_tables.c | 2 -- src/mainboard/lenovo/t410/cmos.layout | 2 -- src/mainboard/lenovo/t410/devicetree.cb | 2 -- src/mainboard/lenovo/t410/dock.c | 2 -- src/mainboard/lenovo/t410/dock.h | 1 - src/mainboard/lenovo/t410/dsdt.asl | 1 - src/mainboard/lenovo/t410/early_init.c | 1 - src/mainboard/lenovo/t410/gpio.c | 1 - src/mainboard/lenovo/t410/hda_verb.c | 1 - src/mainboard/lenovo/t410/mainboard.c | 3 --- src/mainboard/lenovo/t410/romstage.c | 3 --- src/mainboard/lenovo/t410/smihandler.c | 1 - src/mainboard/lenovo/t420/Makefile.inc | 1 - src/mainboard/lenovo/t420/acpi/ec.asl | 1 - src/mainboard/lenovo/t420/acpi/platform.asl | 1 - src/mainboard/lenovo/t420/acpi_tables.c | 1 - src/mainboard/lenovo/t420/cmos.layout | 2 -- src/mainboard/lenovo/t420/dsdt.asl | 3 --- src/mainboard/lenovo/t420/early_init.c | 3 --- src/mainboard/lenovo/t420/hda_verb.c | 2 -- src/mainboard/lenovo/t420/mainboard.c | 3 --- src/mainboard/lenovo/t420/smihandler.c | 2 -- src/mainboard/lenovo/t420s/Makefile.inc | 1 - src/mainboard/lenovo/t420s/acpi/ec.asl | 1 - src/mainboard/lenovo/t420s/acpi/platform.asl | 1 - src/mainboard/lenovo/t420s/acpi_tables.c | 1 - src/mainboard/lenovo/t420s/cmos.layout | 2 -- src/mainboard/lenovo/t420s/dsdt.asl | 3 --- src/mainboard/lenovo/t420s/early_init.c | 3 --- src/mainboard/lenovo/t420s/hda_verb.c | 2 -- src/mainboard/lenovo/t420s/mainboard.c | 3 --- src/mainboard/lenovo/t420s/smihandler.c | 2 -- src/mainboard/lenovo/t430/acpi/ec.asl | 1 - src/mainboard/lenovo/t430/acpi/platform.asl | 1 - src/mainboard/lenovo/t430/acpi/superio.asl | 1 - src/mainboard/lenovo/t430/acpi_tables.c | 1 - src/mainboard/lenovo/t430/cmos.layout | 2 -- src/mainboard/lenovo/t430/dsdt.asl | 3 --- src/mainboard/lenovo/t430/early_init.c | 1 - src/mainboard/lenovo/t430/gpio.c | 1 - src/mainboard/lenovo/t430/hda_verb.c | 1 - src/mainboard/lenovo/t430/mainboard.c | 1 - src/mainboard/lenovo/t430/smihandler.c | 2 -- src/mainboard/lenovo/t430s/Makefile.inc | 1 - src/mainboard/lenovo/t430s/acpi/ec.asl | 1 - src/mainboard/lenovo/t430s/acpi/platform.asl | 1 - src/mainboard/lenovo/t430s/acpi_tables.c | 1 - src/mainboard/lenovo/t430s/cmos.layout | 2 -- src/mainboard/lenovo/t430s/dsdt.asl | 3 --- src/mainboard/lenovo/t430s/mainboard.c | 3 --- src/mainboard/lenovo/t430s/smihandler.c | 2 -- src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c | 2 -- src/mainboard/lenovo/t430s/variants/t430s/romstage.c | 3 --- src/mainboard/lenovo/t430s/variants/t431s/gpio.c | 2 -- src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c | 2 -- src/mainboard/lenovo/t430s/variants/t431s/romstage.c | 3 --- src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc | 1 - src/mainboard/lenovo/t440p/acpi/ec.asl | 1 - src/mainboard/lenovo/t440p/acpi/platform.asl | 1 - src/mainboard/lenovo/t440p/acpi/superio.asl | 1 - src/mainboard/lenovo/t440p/acpi_tables.c | 2 -- src/mainboard/lenovo/t440p/cmos.layout | 2 -- src/mainboard/lenovo/t440p/dsdt.asl | 1 - src/mainboard/lenovo/t440p/gpio.c | 2 -- src/mainboard/lenovo/t440p/hda_verb.c | 2 -- src/mainboard/lenovo/t440p/mainboard.c | 1 - src/mainboard/lenovo/t440p/romstage.c | 2 -- src/mainboard/lenovo/t440p/smihandler.c | 2 -- src/mainboard/lenovo/t520/Makefile.inc | 1 - src/mainboard/lenovo/t520/acpi/ec.asl | 1 - src/mainboard/lenovo/t520/acpi/platform.asl | 1 - src/mainboard/lenovo/t520/acpi_tables.c | 1 - src/mainboard/lenovo/t520/cmos.layout | 3 --- src/mainboard/lenovo/t520/dsdt.asl | 3 --- src/mainboard/lenovo/t520/early_init.c | 3 --- src/mainboard/lenovo/t520/hda_verb.c | 2 -- src/mainboard/lenovo/t520/mainboard.c | 3 --- src/mainboard/lenovo/t520/smihandler.c | 2 -- src/mainboard/lenovo/t520/variants/t520/gpio.c | 1 - src/mainboard/lenovo/t520/variants/t520/romstage.c | 3 --- src/mainboard/lenovo/t520/variants/w520/gpio.c | 2 -- src/mainboard/lenovo/t520/variants/w520/romstage.c | 3 --- src/mainboard/lenovo/t530/Makefile.inc | 1 - src/mainboard/lenovo/t530/acpi/ec.asl | 1 - src/mainboard/lenovo/t530/acpi/platform.asl | 1 - src/mainboard/lenovo/t530/acpi_tables.c | 1 - src/mainboard/lenovo/t530/cmos.layout | 2 -- src/mainboard/lenovo/t530/dsdt.asl | 3 --- src/mainboard/lenovo/t530/early_init.c | 3 --- src/mainboard/lenovo/t530/hda_verb.c | 2 -- src/mainboard/lenovo/t530/mainboard.c | 3 --- src/mainboard/lenovo/t530/smihandler.c | 2 -- src/mainboard/lenovo/t530/variants/t530/romstage.c | 3 --- src/mainboard/lenovo/t530/variants/w530/gpio.c | 2 -- src/mainboard/lenovo/t530/variants/w530/romstage.c | 3 --- src/mainboard/lenovo/t60/Makefile.inc | 1 - src/mainboard/lenovo/t60/acpi/dock.asl | 1 - src/mainboard/lenovo/t60/acpi/ec.asl | 1 - src/mainboard/lenovo/t60/acpi/gpe.asl | 1 - src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/lenovo/t60/acpi/platform.asl | 1 - src/mainboard/lenovo/t60/acpi/video.asl | 1 - src/mainboard/lenovo/t60/acpi_tables.c | 1 - src/mainboard/lenovo/t60/cmos.layout | 1 - src/mainboard/lenovo/t60/devicetree.cb | 2 -- src/mainboard/lenovo/t60/dock.c | 1 - src/mainboard/lenovo/t60/dock.h | 1 - src/mainboard/lenovo/t60/dsdt.asl | 1 - src/mainboard/lenovo/t60/early_init.c | 2 -- src/mainboard/lenovo/t60/gpio.c | 2 -- src/mainboard/lenovo/t60/mainboard.c | 2 -- src/mainboard/lenovo/t60/mptable.c | 1 - src/mainboard/lenovo/t60/smi.h | 1 - src/mainboard/lenovo/t60/smihandler.c | 1 - src/mainboard/lenovo/t60/variants/t60/overridetree.cb | 2 -- src/mainboard/lenovo/t60/variants/z61t/overridetree.cb | 2 -- src/mainboard/lenovo/thinkcentre_a58/Kconfig | 2 -- src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c | 2 -- src/mainboard/lenovo/thinkcentre_a58/cmos.layout | 2 -- src/mainboard/lenovo/thinkcentre_a58/cstates.c | 1 - src/mainboard/lenovo/thinkcentre_a58/devicetree.cb | 1 - src/mainboard/lenovo/thinkcentre_a58/dsdt.asl | 2 -- src/mainboard/lenovo/thinkcentre_a58/early_init.c | 2 -- src/mainboard/lenovo/thinkcentre_a58/gpio.c | 1 - src/mainboard/lenovo/thinkcentre_a58/hda_verb.c | 1 - src/mainboard/lenovo/x131e/Makefile.inc | 1 - src/mainboard/lenovo/x131e/acpi/ec.asl | 2 -- src/mainboard/lenovo/x131e/acpi/platform.asl | 1 - src/mainboard/lenovo/x131e/acpi/superio.asl | 1 - src/mainboard/lenovo/x131e/acpi_tables.c | 1 - src/mainboard/lenovo/x131e/cmos.layout | 2 -- src/mainboard/lenovo/x131e/dsdt.asl | 4 ---- src/mainboard/lenovo/x131e/early_init.c | 3 --- src/mainboard/lenovo/x131e/gpio.c | 1 - src/mainboard/lenovo/x131e/hda_verb.c | 2 -- src/mainboard/lenovo/x131e/mainboard.c | 1 - src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc | 1 - src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl | 1 - src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl | 1 - src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c | 1 - src/mainboard/lenovo/x1_carbon_gen1/cmos.layout | 2 -- src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 3 --- src/mainboard/lenovo/x1_carbon_gen1/early_init.c | 4 ---- src/mainboard/lenovo/x1_carbon_gen1/gpio.c | 2 -- src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c | 2 -- src/mainboard/lenovo/x1_carbon_gen1/mainboard.c | 3 --- src/mainboard/lenovo/x1_carbon_gen1/smihandler.c | 2 -- src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc | 1 - src/mainboard/lenovo/x200/Makefile.inc | 1 - src/mainboard/lenovo/x200/acpi/dock.asl | 1 - src/mainboard/lenovo/x200/acpi/gpe.asl | 1 - src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl | 1 - src/mainboard/lenovo/x200/acpi/platform.asl | 1 - src/mainboard/lenovo/x200/acpi_tables.c | 1 - src/mainboard/lenovo/x200/blc.c | 1 - src/mainboard/lenovo/x200/cmos.layout | 2 -- src/mainboard/lenovo/x200/cstates.c | 1 - src/mainboard/lenovo/x200/dock.h | 1 - src/mainboard/lenovo/x200/dsdt.asl | 1 - src/mainboard/lenovo/x200/fadt.c | 1 - src/mainboard/lenovo/x200/hda_verb.c | 2 -- src/mainboard/lenovo/x200/mainboard.c | 1 - src/mainboard/lenovo/x200/romstage.c | 1 - src/mainboard/lenovo/x200/variants/x200/dock.c | 2 -- src/mainboard/lenovo/x201/Makefile.inc | 1 - src/mainboard/lenovo/x201/acpi/dock.asl | 1 - src/mainboard/lenovo/x201/acpi/ec.asl | 1 - src/mainboard/lenovo/x201/acpi/gpe.asl | 1 - src/mainboard/lenovo/x201/acpi/platform.asl | 1 - src/mainboard/lenovo/x201/acpi_tables.c | 2 -- src/mainboard/lenovo/x201/cmos.layout | 2 -- src/mainboard/lenovo/x201/devicetree.cb | 2 -- src/mainboard/lenovo/x201/dock.c | 2 -- src/mainboard/lenovo/x201/dock.h | 1 - src/mainboard/lenovo/x201/dsdt.asl | 1 - src/mainboard/lenovo/x201/early_init.c | 3 --- src/mainboard/lenovo/x201/gpio.c | 1 - src/mainboard/lenovo/x201/hda_verb.c | 1 - src/mainboard/lenovo/x201/mainboard.c | 3 --- src/mainboard/lenovo/x201/romstage.c | 3 --- src/mainboard/lenovo/x201/smihandler.c | 1 - src/mainboard/lenovo/x220/Makefile.inc | 1 - src/mainboard/lenovo/x220/acpi/ec.asl | 1 - src/mainboard/lenovo/x220/acpi/platform.asl | 1 - src/mainboard/lenovo/x220/acpi_tables.c | 1 - src/mainboard/lenovo/x220/cmos.layout | 2 -- src/mainboard/lenovo/x220/dsdt.asl | 3 --- src/mainboard/lenovo/x220/early_init.c | 3 --- src/mainboard/lenovo/x220/hda_verb.c | 2 -- src/mainboard/lenovo/x220/mainboard.c | 3 --- src/mainboard/lenovo/x220/smihandler.c | 2 -- src/mainboard/lenovo/x220/variants/x1/gpio.c | 3 --- src/mainboard/lenovo/x220/variants/x1/romstage.c | 3 --- src/mainboard/lenovo/x220/variants/x220/romstage.c | 3 --- src/mainboard/lenovo/x230/Makefile.inc | 1 - src/mainboard/lenovo/x230/acpi/ec.asl | 1 - src/mainboard/lenovo/x230/acpi/platform.asl | 1 - src/mainboard/lenovo/x230/acpi_tables.c | 1 - src/mainboard/lenovo/x230/cmos.layout | 2 -- src/mainboard/lenovo/x230/dsdt.asl | 3 --- src/mainboard/lenovo/x230/early_init.c | 3 --- src/mainboard/lenovo/x230/gpio.c | 2 -- src/mainboard/lenovo/x230/hda_verb.c | 2 -- src/mainboard/lenovo/x230/mainboard.c | 3 --- src/mainboard/lenovo/x230/smihandler.c | 2 -- src/mainboard/lenovo/x60/Makefile.inc | 1 - src/mainboard/lenovo/x60/acpi/dock.asl | 1 - src/mainboard/lenovo/x60/acpi/ec.asl | 1 - src/mainboard/lenovo/x60/acpi/gpe.asl | 1 - src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl | 1 - src/mainboard/lenovo/x60/acpi/platform.asl | 1 - src/mainboard/lenovo/x60/acpi_tables.c | 1 - src/mainboard/lenovo/x60/cmos.layout | 1 - src/mainboard/lenovo/x60/devicetree.cb | 2 -- src/mainboard/lenovo/x60/dock.c | 1 - src/mainboard/lenovo/x60/dock.h | 1 - src/mainboard/lenovo/x60/dsdt.asl | 1 - src/mainboard/lenovo/x60/early_init.c | 2 -- src/mainboard/lenovo/x60/gpio.c | 1 - src/mainboard/lenovo/x60/irq_tables.c | 1 - src/mainboard/lenovo/x60/mainboard.c | 2 -- src/mainboard/lenovo/x60/mptable.c | 1 - src/mainboard/lenovo/x60/smi.h | 1 - src/mainboard/lenovo/x60/smihandler.c | 1 - src/mainboard/lippert/frontrunner-af/BiosCallOuts.c | 1 - src/mainboard/lippert/frontrunner-af/Kconfig | 1 - src/mainboard/lippert/frontrunner-af/Makefile.inc | 1 - src/mainboard/lippert/frontrunner-af/OemCustomize.c | 1 - src/mainboard/lippert/frontrunner-af/OptionsIds.h | 1 - src/mainboard/lippert/frontrunner-af/acpi/routing.asl | 1 - src/mainboard/lippert/frontrunner-af/acpi/sata.asl | 1 - src/mainboard/lippert/frontrunner-af/acpi/superio.asl | 2 -- src/mainboard/lippert/frontrunner-af/acpi/usb.asl | 1 - src/mainboard/lippert/frontrunner-af/acpi_tables.c | 1 - src/mainboard/lippert/frontrunner-af/bootblock.c | 1 - src/mainboard/lippert/frontrunner-af/buildOpts.c | 1 - src/mainboard/lippert/frontrunner-af/cmos.layout | 1 - src/mainboard/lippert/frontrunner-af/devicetree.cb | 1 - src/mainboard/lippert/frontrunner-af/dsdt.asl | 1 - src/mainboard/lippert/frontrunner-af/irq_tables.c | 1 - src/mainboard/lippert/frontrunner-af/mainboard.c | 1 - src/mainboard/lippert/frontrunner-af/mptable.c | 1 - src/mainboard/lippert/frontrunner-af/platform_cfg.h | 1 - src/mainboard/lippert/toucan-af/BiosCallOuts.c | 1 - src/mainboard/lippert/toucan-af/Kconfig | 1 - src/mainboard/lippert/toucan-af/Makefile.inc | 1 - src/mainboard/lippert/toucan-af/OemCustomize.c | 1 - src/mainboard/lippert/toucan-af/OptionsIds.h | 1 - src/mainboard/lippert/toucan-af/acpi/routing.asl | 1 - src/mainboard/lippert/toucan-af/acpi/sata.asl | 1 - src/mainboard/lippert/toucan-af/acpi/superio.asl | 2 -- src/mainboard/lippert/toucan-af/acpi/usb.asl | 1 - src/mainboard/lippert/toucan-af/acpi_tables.c | 1 - src/mainboard/lippert/toucan-af/bootblock.c | 1 - src/mainboard/lippert/toucan-af/buildOpts.c | 1 - src/mainboard/lippert/toucan-af/cmos.layout | 1 - src/mainboard/lippert/toucan-af/devicetree.cb | 1 - src/mainboard/lippert/toucan-af/dsdt.asl | 1 - src/mainboard/lippert/toucan-af/irq_tables.c | 1 - src/mainboard/lippert/toucan-af/mainboard.c | 1 - src/mainboard/lippert/toucan-af/mptable.c | 1 - src/mainboard/lippert/toucan-af/platform_cfg.h | 1 - src/mainboard/msi/Kconfig | 1 - src/mainboard/msi/ms7707/acpi/platform.asl | 1 - src/mainboard/msi/ms7707/acpi_tables.c | 2 -- src/mainboard/msi/ms7707/dsdt.asl | 1 - src/mainboard/msi/ms7707/early_init.c | 2 -- src/mainboard/msi/ms7707/gpio.c | 2 -- src/mainboard/msi/ms7707/hda_verb.c | 2 -- src/mainboard/msi/ms7721/BiosCallOuts.c | 2 -- src/mainboard/msi/ms7721/Kconfig | 3 --- src/mainboard/msi/ms7721/Makefile.inc | 1 - src/mainboard/msi/ms7721/OemCustomize.c | 2 -- src/mainboard/msi/ms7721/OptionsIds.h | 1 - src/mainboard/msi/ms7721/acpi/cpstate.asl | 1 - src/mainboard/msi/ms7721/acpi/gpe.asl | 1 - src/mainboard/msi/ms7721/acpi/mainboard.asl | 1 - src/mainboard/msi/ms7721/acpi/routing.asl | 2 -- src/mainboard/msi/ms7721/acpi/si.asl | 1 - src/mainboard/msi/ms7721/acpi/sleep.asl | 1 - src/mainboard/msi/ms7721/acpi_tables.c | 1 - src/mainboard/msi/ms7721/bootblock.c | 3 --- src/mainboard/msi/ms7721/buildOpts.c | 1 - src/mainboard/msi/ms7721/cmos.layout | 1 - src/mainboard/msi/ms7721/devicetree.cb | 2 -- src/mainboard/msi/ms7721/dsdt.asl | 3 --- src/mainboard/msi/ms7721/irq_tables.c | 1 - src/mainboard/msi/ms7721/mainboard.c | 1 - src/mainboard/msi/ms7721/mptable.c | 1 - src/mainboard/msi/ms7721/romstage.c | 3 --- src/mainboard/ocp/tiogapass/Kconfig | 2 -- src/mainboard/ocp/tiogapass/Makefile.inc | 2 -- src/mainboard/ocp/tiogapass/acpi/platform.asl | 4 ---- src/mainboard/ocp/tiogapass/acpi_tables.c | 2 -- src/mainboard/ocp/tiogapass/devicetree.cb | 2 -- src/mainboard/ocp/tiogapass/dsdt.asl | 2 -- src/mainboard/ocp/tiogapass/fadt.c | 2 -- src/mainboard/ocp/tiogapass/ramstage.c | 2 -- src/mainboard/ocp/tiogapass/romstage.c | 2 -- src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h | 2 -- src/mainboard/ocp/tiogapass/skxsp_tp_iio.h | 2 -- src/mainboard/opencellular/Kconfig | 1 - src/mainboard/opencellular/elgon/Kconfig | 1 - src/mainboard/opencellular/elgon/Makefile.inc | 1 - src/mainboard/opencellular/elgon/bdk_devicetree.c | 1 - src/mainboard/opencellular/elgon/bootblock.c | 1 - src/mainboard/opencellular/elgon/death.c | 1 - src/mainboard/opencellular/elgon/devicetree.cb | 1 - src/mainboard/opencellular/elgon/gbcv2.dts | 1 - src/mainboard/opencellular/elgon/mainboard.c | 2 -- src/mainboard/opencellular/elgon/mainboard.h | 1 - src/mainboard/opencellular/elgon/romstage.c | 1 - src/mainboard/packardbell/ms2290/Makefile.inc | 1 - src/mainboard/packardbell/ms2290/acpi/ac.asl | 1 - src/mainboard/packardbell/ms2290/acpi/ec.asl | 1 - src/mainboard/packardbell/ms2290/acpi/gpe.asl | 1 - src/mainboard/packardbell/ms2290/acpi/platform.asl | 1 - src/mainboard/packardbell/ms2290/acpi_tables.c | 2 -- src/mainboard/packardbell/ms2290/cmos.layout | 2 -- src/mainboard/packardbell/ms2290/devicetree.cb | 2 -- src/mainboard/packardbell/ms2290/dsdt.asl | 1 - src/mainboard/packardbell/ms2290/hda_verb.c | 1 - src/mainboard/packardbell/ms2290/mainboard.c | 3 --- src/mainboard/packardbell/ms2290/romstage.c | 3 --- src/mainboard/packardbell/ms2290/smihandler.c | 1 - src/mainboard/pcengines/apu1/BiosCallOuts.c | 1 - src/mainboard/pcengines/apu1/Kconfig | 2 -- src/mainboard/pcengines/apu1/Makefile.inc | 2 -- src/mainboard/pcengines/apu1/OemCustomize.c | 2 -- src/mainboard/pcengines/apu1/OptionsIds.h | 1 - src/mainboard/pcengines/apu1/acpi/buttons.asl | 1 - src/mainboard/pcengines/apu1/acpi/gpe.asl | 1 - src/mainboard/pcengines/apu1/acpi/gpio.asl | 1 - src/mainboard/pcengines/apu1/acpi/leds.asl | 1 - src/mainboard/pcengines/apu1/acpi/mainboard.asl | 1 - src/mainboard/pcengines/apu1/acpi/routing.asl | 1 - src/mainboard/pcengines/apu1/acpi/sata.asl | 1 - src/mainboard/pcengines/apu1/acpi/sleep.asl | 1 - src/mainboard/pcengines/apu1/acpi/usb_oc.asl | 1 - src/mainboard/pcengines/apu1/acpi_tables.c | 1 - src/mainboard/pcengines/apu1/buildOpts.c | 1 - src/mainboard/pcengines/apu1/devicetree.cb | 2 -- src/mainboard/pcengines/apu1/dsdt.asl | 2 -- src/mainboard/pcengines/apu1/gpio_ftns.c | 1 - src/mainboard/pcengines/apu1/gpio_ftns.h | 1 - src/mainboard/pcengines/apu1/irq_tables.c | 1 - src/mainboard/pcengines/apu1/mainboard.c | 2 -- src/mainboard/pcengines/apu1/mptable.c | 2 -- src/mainboard/pcengines/apu1/platform_cfg.h | 1 - src/mainboard/pcengines/apu1/romstage.c | 3 --- src/mainboard/pcengines/apu2/BiosCallOuts.c | 1 - src/mainboard/pcengines/apu2/Kconfig | 3 --- src/mainboard/pcengines/apu2/Makefile.inc | 2 -- src/mainboard/pcengines/apu2/OemCustomize.c | 1 - src/mainboard/pcengines/apu2/acpi/gpe.asl | 1 - src/mainboard/pcengines/apu2/acpi/mainboard.asl | 1 - src/mainboard/pcengines/apu2/acpi/routing.asl | 2 -- src/mainboard/pcengines/apu2/acpi/si.asl | 1 - src/mainboard/pcengines/apu2/acpi/sleep.asl | 1 - src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 2 -- src/mainboard/pcengines/apu2/acpi_tables.c | 1 - src/mainboard/pcengines/apu2/cmos.layout | 1 - src/mainboard/pcengines/apu2/dsdt.asl | 2 -- src/mainboard/pcengines/apu2/gpio_ftns.c | 1 - src/mainboard/pcengines/apu2/gpio_ftns.h | 1 - src/mainboard/pcengines/apu2/irq_tables.c | 1 - src/mainboard/pcengines/apu2/mainboard.c | 1 - src/mainboard/pcengines/apu2/mptable.c | 2 -- src/mainboard/pcengines/apu2/romstage.c | 1 - src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb | 1 - src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 1 - src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb | 1 - src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb | 1 - src/mainboard/portwell/m107/Kconfig | 2 -- src/mainboard/portwell/m107/Makefile.inc | 3 --- src/mainboard/portwell/m107/acpi/superio.asl | 3 --- src/mainboard/portwell/m107/acpi_tables.c | 3 --- src/mainboard/portwell/m107/cmos.layout | 3 --- src/mainboard/portwell/m107/com_init.c | 3 --- src/mainboard/portwell/m107/dsdt.asl | 4 ---- src/mainboard/portwell/m107/fadt.c | 3 --- src/mainboard/portwell/m107/gpio.c | 3 --- src/mainboard/portwell/m107/hda_verb.c | 1 - src/mainboard/portwell/m107/irqroute.c | 3 --- src/mainboard/portwell/m107/irqroute.h | 3 --- src/mainboard/portwell/m107/mainboard.c | 4 ---- src/mainboard/portwell/m107/romstage.c | 3 --- .../portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex | 2 -- .../portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex | 1 - .../portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex | 1 - src/mainboard/portwell/m107/w25q64.c | 3 --- src/mainboard/purism/Kconfig | 1 - src/mainboard/purism/librem_bdw/Makefile.inc | 1 - src/mainboard/purism/librem_bdw/acpi/ec.asl | 1 - src/mainboard/purism/librem_bdw/acpi/mainboard.asl | 1 - src/mainboard/purism/librem_bdw/acpi/superio.asl | 1 - src/mainboard/purism/librem_bdw/acpi_tables.c | 1 - src/mainboard/purism/librem_bdw/dsdt.asl | 1 - src/mainboard/purism/librem_bdw/fadt.c | 1 - src/mainboard/purism/librem_bdw/gpio.c | 1 - src/mainboard/purism/librem_bdw/hda_verb.c | 1 - src/mainboard/purism/librem_bdw/mainboard.c | 1 - src/mainboard/purism/librem_bdw/romstage.c | 1 - .../purism/librem_bdw/variants/librem13v1/pei_data.c | 1 - .../purism/librem_bdw/variants/librem15v2/pei_data.c | 1 - src/mainboard/purism/librem_skl/Makefile.inc | 1 - src/mainboard/purism/librem_skl/acpi/ec.asl | 1 - src/mainboard/purism/librem_skl/acpi/mainboard.asl | 1 - src/mainboard/purism/librem_skl/acpi/superio.asl | 1 - src/mainboard/purism/librem_skl/dsdt.asl | 3 --- src/mainboard/purism/librem_skl/gpio.h | 1 - src/mainboard/purism/librem_skl/hda_verb.c | 1 - src/mainboard/purism/librem_skl/mainboard.c | 1 - src/mainboard/purism/librem_skl/ramstage.c | 2 -- src/mainboard/purism/librem_skl/romstage.c | 4 ---- 1121 files changed, 1628 deletions(-) diff --git a/src/mainboard/getac/Kconfig b/src/mainboard/getac/Kconfig index 2d597b5832..a8e858d9be 100644 --- a/src/mainboard/getac/Kconfig +++ b/src/mainboard/getac/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 7394ea4c14..6bc16cce39 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc index c8c8e0cc4a..7aaf0d9929 100644 --- a/src/mainboard/getac/p470/Makefile.inc +++ b/src/mainboard/getac/p470/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index 592bce037b..006dbae999 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 6783289b94..618055bed0 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi/gpe.asl b/src/mainboard/getac/p470/acpi/gpe.asl index dcf8e99b5f..95ce678740 100644 --- a/src/mainboard/getac/p470/acpi/gpe.asl +++ b/src/mainboard/getac/p470/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl index 8a926cb984..94152f4080 100644 --- a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi/mainboard.asl b/src/mainboard/getac/p470/acpi/mainboard.asl index d067acc54e..4357fc86e6 100644 --- a/src/mainboard/getac/p470/acpi/mainboard.asl +++ b/src/mainboard/getac/p470/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index e722ca368d..6d1948fe75 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl index 9bf07ce18f..89b63a75fb 100644 --- a/src/mainboard/getac/p470/acpi/superio.asl +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 6c9f2e9bf9..9e83384856 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index e646984454..c2a0920885 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index fd627a5835..6a155ac43d 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index e2001d91d1..248ce60520 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index ce36c28872..8da962ecb4 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index f4f974a849..c12cc6f7de 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c index 874016779e..344374b358 100644 --- a/src/mainboard/getac/p470/ec_oem.c +++ b/src/mainboard/getac/p470/ec_oem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h index 5d5610787d..5f9616fab0 100644 --- a/src/mainboard/getac/p470/ec_oem.h +++ b/src/mainboard/getac/p470/ec_oem.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c index be52a86ce1..c19e27a29e 100644 --- a/src/mainboard/getac/p470/gpio.c +++ b/src/mainboard/getac/p470/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c index d46b87fa33..23e8be686a 100644 --- a/src/mainboard/getac/p470/hda_verb.c +++ b/src/mainboard/getac/p470/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c index 06d1492b63..c279d6b684 100644 --- a/src/mainboard/getac/p470/irq_tables.c +++ b/src/mainboard/getac/p470/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index c20da65981..6d9e0620ae 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index 795ac08ff0..b9d7632eb4 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 5a82044661..aaf123b654 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index dcb57c6b12..8863184000 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index ea1a2fc689..b37f774028 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 coresystems GmbH -## Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c index 1b57dfadf6..55cff054c2 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 0abe48248e..fe6210f536 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl index a1c79896d7..b7b6195a62 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl index e98c0a2286..722a5d9f18 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Bill Xie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl index 10856d3394..90db019a82 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl index ca561a5039..c035abbcce 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c index b9d951091b..9ef2b66097 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout index 095e3833e1..c31d568140 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 9fb3cad618..9a2b4a3dec 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index cc26757914..80554a9823 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h index 9db69104a0..31462781e0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads index 416732dc2b..93f8e37f49 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads @@ -1,5 +1,4 @@ -- --- Copyright (C) 2017 Bill XIE persmule@gmail.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c index 763dfadefd..012773574a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads index 416732dc2b..93f8e37f49 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads @@ -1,5 +1,4 @@ -- --- Copyright (C) 2017 Bill XIE persmule@gmail.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index e928cbecaf..5157ff0cdb 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl index 099a53f968..20d7562770 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index 11f3af2036..02ddd77af4 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 749f91d83e..bc987e32c8 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index fa542eb083..1ba78ac31e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 76dd819d09..cd535058d9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index cddaa3af4e..6120949269 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index aa92671f3b..fdeb72e558 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c b/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c index e06a8f1ec9..bb05851c88 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c index d606582265..ad0642b965 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 18982c8675..f82ce4a83d 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl index 34de86f976..0483c161be 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl index d8d33208f8..92c98614d7 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl index 450c7fda75..606085fafe 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl index ca561a5039..c035abbcce 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c index b5b4b4065f..5a6a5e4de4 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout index 095e3833e1..c31d568140 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index b1ecdfd076..61eb8efeb9 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c index ea15d56488..d006745f1b 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads index 2083ff0f1f..98b462a2b9 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads @@ -1,7 +1,6 @@ -- -- This file is part of the coreboot project. -- --- Copyright (C) 2018 Angel Pons -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c b/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c index b8a659bfa3..e14e31c041 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb index 2cc5b19651..de9c2131c3 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c index 89bc4d6a86..a438cda4fa 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c index 1379b1ac94..069ba8fade 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Angel Pons * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb index 317d79744c..c898fad228 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c index f7de3bd9c2..800298d882 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c index c6df4caf3f..069ba8fade 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Angel Pons * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb index a11ba0e84e..1b10533ef2 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Angel Pons ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c index b7173749d1..d24d16233d 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c index 13e5c38467..0baeed019c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Angel Pons * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gizmosphere/Kconfig b/src/mainboard/gizmosphere/Kconfig index d2b335a23a..f9c662089a 100644 --- a/src/mainboard/gizmosphere/Kconfig +++ b/src/mainboard/gizmosphere/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 233c40f0ca..6600c6c47a 100644 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e195e8f0a2..f8a9a16080 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2013 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index a2a8dadd1e..8264df8f6b 100644 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2013 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index 23426ca76f..f25d8cf38f 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/OptionsIds.h b/src/mainboard/gizmosphere/gizmo/OptionsIds.h index 8b497aa962..b4fe940569 100644 --- a/src/mainboard/gizmosphere/gizmo/OptionsIds.h +++ b/src/mainboard/gizmosphere/gizmo/OptionsIds.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl index e520724101..af4e2e48b7 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi/ide.asl b/src/mainboard/gizmosphere/gizmo/acpi/ide.asl index f4fd21ab14..00c4f8841d 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/ide.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/ide.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl b/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl index 651c8a6fb0..3d4abb5d7b 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index af05ec6848..dd63e9b63e 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi/sata.asl b/src/mainboard/gizmosphere/gizmo/acpi/sata.asl index 118c1bba3d..9729500d48 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/sata.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/sata.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl b/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl index 669e195074..08144ff427 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl index c6d570051d..5b22875dd1 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 364c915efc..9e3032474e 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 1c72f7cf2d..bec93772b2 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/cmos.layout b/src/mainboard/gizmosphere/gizmo/cmos.layout index aa6317339c..275de95ad2 100644 --- a/src/mainboard/gizmosphere/gizmo/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo/cmos.layout @@ -2,8 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2013 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index 3a1b5d071f..3cf6ed33f1 100644 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2013 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index fe6254dcce..47ab7cfe99 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index 01a3411144..f962314546 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 63d94530e9..14a60e691a 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index dca5f3c273..5746cadec9 100644 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index c56b537f9d..7d5396b6cd 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index 8fa8ab5bf3..6966cff36a 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 47a39b694b..07da78c8f4 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc index 2a7d26bd6b..c7f7be7d4e 100644 --- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex b/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex index 510f690b53..39a764772a 100644 --- a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex +++ b/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c index 6b21f0c177..d61960528b 100644 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/OptionsIds.h b/src/mainboard/gizmosphere/gizmo2/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/gizmosphere/gizmo2/OptionsIds.h +++ b/src/mainboard/gizmosphere/gizmo2/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl b/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl index e7f4625506..e17d93befd 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl b/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl index 6755258f4d..00d855adb0 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/si.asl b/src/mainboard/gizmosphere/gizmo2/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/si.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl index c0202167da..bf00545927 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 6c405cc18e..9ec18e9344 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/cmos.layout b/src/mainboard/gizmosphere/gizmo2/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/gizmosphere/gizmo2/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo2/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/devicetree.cb b/src/mainboard/gizmosphere/gizmo2/devicetree.cb index e35249e734..8714b48f32 100644 --- a/src/mainboard/gizmosphere/gizmo2/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo2/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index c4fc93484e..a7914191d0 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/irq_tables.c b/src/mainboard/gizmosphere/gizmo2/irq_tables.c index d8bf5e9806..5f0654ad1e 100644 --- a/src/mainboard/gizmosphere/gizmo2/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index a6c1a6da04..13d185ebb8 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * All Rights Reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index e4edc5fe7a..e0a407bb25 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 4728c59708..2ee00fc22e 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index f4883b0331..89ddb23a3f 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012-2014 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/Makefile.inc b/src/mainboard/hp/abm/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/hp/abm/Makefile.inc +++ b/src/mainboard/hp/abm/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c index 424b68a936..bc311cc457 100644 --- a/src/mainboard/hp/abm/OemCustomize.c +++ b/src/mainboard/hp/abm/OemCustomize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h index 544ac5374a..b796375146 100644 --- a/src/mainboard/hp/abm/OptionsIds.h +++ b/src/mainboard/hp/abm/OptionsIds.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/gpe.asl b/src/mainboard/hp/abm/acpi/gpe.asl index 87b0d2169d..72bcf765c3 100644 --- a/src/mainboard/hp/abm/acpi/gpe.asl +++ b/src/mainboard/hp/abm/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/ide.asl b/src/mainboard/hp/abm/acpi/ide.asl index e7f4625506..e17d93befd 100644 --- a/src/mainboard/hp/abm/acpi/ide.asl +++ b/src/mainboard/hp/abm/acpi/ide.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/mainboard.asl b/src/mainboard/hp/abm/acpi/mainboard.asl index ed97d4e669..993000d2c6 100644 --- a/src/mainboard/hp/abm/acpi/mainboard.asl +++ b/src/mainboard/hp/abm/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/routing.asl b/src/mainboard/hp/abm/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/hp/abm/acpi/routing.asl +++ b/src/mainboard/hp/abm/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/sata.asl b/src/mainboard/hp/abm/acpi/sata.asl index 6755258f4d..00d855adb0 100644 --- a/src/mainboard/hp/abm/acpi/sata.asl +++ b/src/mainboard/hp/abm/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/si.asl b/src/mainboard/hp/abm/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/hp/abm/acpi/si.asl +++ b/src/mainboard/hp/abm/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/sleep.asl b/src/mainboard/hp/abm/acpi/sleep.asl index 1225a62785..9f1f4c72de 100644 --- a/src/mainboard/hp/abm/acpi/sleep.asl +++ b/src/mainboard/hp/abm/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl index c0202167da..bf00545927 100644 --- a/src/mainboard/hp/abm/acpi/usb_oc.asl +++ b/src/mainboard/hp/abm/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/acpi_tables.c b/src/mainboard/hp/abm/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/hp/abm/acpi_tables.c +++ b/src/mainboard/hp/abm/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index bc1b1728cb..1b0e853ad6 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index cd0b354598..f3f5459745 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index c4fc93484e..a7914191d0 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index d8bf5e9806..5f0654ad1e 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index aaa899b55d..7a96b6dff1 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 52374f1529..6e1d402833 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl index 5a861f1f3b..440ec7a71f 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl index d6acae9c00..501cffb566 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c index 8866557eee..2b8c10087b 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout index a3ae3479ac..0f7fdaf3e6 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## Copyright (C) 2018 Patrick Rudolph ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index d8790a81d0..0cc4f9db13 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Patrick Rudolph ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 9bb96146ae..2ab4c15802 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c index c0139eb4b9..66f35dd136 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gpio.c b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c index 8786e2874a..0fbb24b749 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/gpio.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c index 3ad452e7d5..4813fa8cb4 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c index 2d6499f9dd..68b60257bc 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index dfe53eaad9..f51a65ca35 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index c6c35df390..0683e2d8ba 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index f030989b36..f56c5e5bac 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 43786af295..da11d010d3 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h index eaf2442651..bf0588d00f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl index ccceba4cfd..d49c26b118 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index ace1d2692e..869b6c0ac6 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 5068e9fe9e..3bbd215f83 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl index a1ce860682..7b9534437e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl index ff0c3cfc0d..cc27e983e1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl index d516ccedb0..d5a1f683a8 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl index f5d6980d15..e1dc35d969 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index fd59a3aade..be2669eeb8 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index e56d513cf2..09a7825cfe 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index 8d705ede3a..9e238647af 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index bc9a13f73a..224dd14d18 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.c b/src/mainboard/hp/pavilion_m6_1035dx/ec.c index 47260c31fd..d5928aa258 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 55672513e5..6a375bfb06 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c index fb04069628..7864872b45 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index da450c6813..bd1a671d50 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h index 057eb1dc23..8b55c50665 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index 27b1ac2a7c..a0c35a33e9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index f3c2f0a572..e426b4d0e3 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index d0105ff01a..52297febad 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Iru Cai ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index c4a8662e81..f013dfc437 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Iru Cai ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index 50cea25914..c757a2ff6e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl b/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl index ac65fb399f..86acea9715 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl +++ b/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl b/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl index fe0f936a61..f7f8066ecf 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl +++ b/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl b/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl index b3ea115115..606085fafe 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl +++ b/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c index 114f6e1228..831ec53c44 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c +++ b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.layout b/src/mainboard/hp/snb_ivb_laptops/cmos.layout index f1526f34c9..8343734a38 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.layout +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 5a1d3f087e..d4827cffcc 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 81f45c155e..2ab4c15802 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/mainboard.c b/src/mainboard/hp/snb_ivb_laptops/mainboard.c index aefe4c0141..d1aad59d01 100644 --- a/src/mainboard/hp/snb_ivb_laptops/mainboard.c +++ b/src/mainboard/hp/snb_ivb_laptops/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c index b72dd304a4..ef66127101 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c index c8646fe1fc..971d2fd866 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c index 71556c0b96..0aabe19967 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb index 7ad436d1d5..e6701d6bac 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c index b33216b620..b43815ca87 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c index ceaf591594..b3a68a49c9 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c index 309d50d5be..9b32e23c12 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb index 4a797584d5..86b4da92a3 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c index 1ff0f6ef15..7bf19875ca 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c index 3951d88ca3..2a9bb1f402 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c index 7404576796..e954689f9f 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb index 9d5069a40e..0d678e684c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c index 51b0b4dcbb..a89741610d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c index 768af5c821..ea8b74983d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c index 69fc26ad86..83b14891f5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb index c4d83c3dc9..432294e3b5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c index 6690196894..5e33cf1a8a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Iru Cai - * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c index 84ca7f67d5..8ed54a1419 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c index f4a83b7d13..3eb82daf5d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Iru Cai - * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index a4500ae248..b625500af8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Iru Cai -# Copyright (C) 2018 Robert Reeves # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c index ba507cc249..1efdcde355 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c index 292180c4d1..7e50750dc4 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c index 03caeb271e..c32ea606d6 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index 835d39155b..5179e3ad9f 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2018 Bill Xie # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c index 29be074db1..8b45b009cb 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c index 5a9d87592d..9cfab29848 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c index c421b1b818..f353184c97 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index b05db7adc0..2a02a1b3b1 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Bill Xie # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl index 5a861f1f3b..440ec7a71f 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl +++ b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl index d6acae9c00..501cffb566 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl +++ b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c index 8866557eee..2b8c10087b 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c +++ b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.layout b/src/mainboard/hp/z220_sff_workstation/cmos.layout index 6602afad2d..e42e487c85 100644 --- a/src/mainboard/hp/z220_sff_workstation/cmos.layout +++ b/src/mainboard/hp/z220_sff_workstation/cmos.layout @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## Copyright (C) 2018 Patrick Rudolph ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index a0eed14c54..9f184e8c75 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Patrick Rudolph ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 9bb96146ae..2ab4c15802 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/z220_sff_workstation/early_init.c b/src/mainboard/hp/z220_sff_workstation/early_init.c index d0ea1affed..d21eed740f 100644 --- a/src/mainboard/hp/z220_sff_workstation/early_init.c +++ b/src/mainboard/hp/z220_sff_workstation/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/z220_sff_workstation/gpio.c b/src/mainboard/hp/z220_sff_workstation/gpio.c index 397f08b955..c79c285ca6 100644 --- a/src/mainboard/hp/z220_sff_workstation/gpio.c +++ b/src/mainboard/hp/z220_sff_workstation/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/z220_sff_workstation/hda_verb.c index cea4e04ab0..40bc9e18b5 100644 --- a/src/mainboard/hp/z220_sff_workstation/hda_verb.c +++ b/src/mainboard/hp/z220_sff_workstation/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.c b/src/mainboard/hp/z220_sff_workstation/mainboard.c index 2d6499f9dd..68b60257bc 100644 --- a/src/mainboard/hp/z220_sff_workstation/mainboard.c +++ b/src/mainboard/hp/z220_sff_workstation/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/ibase/mb899/acpi/ec.asl b/src/mainboard/ibase/mb899/acpi/ec.asl index 14bdbcad87..0cd354a09b 100644 --- a/src/mainboard/ibase/mb899/acpi/ec.asl +++ b/src/mainboard/ibase/mb899/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl b/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl index 67915f281f..953989bfa4 100644 --- a/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/acpi/platform.asl b/src/mainboard/ibase/mb899/acpi/platform.asl index 98661102fb..4b161bc565 100644 --- a/src/mainboard/ibase/mb899/acpi/platform.asl +++ b/src/mainboard/ibase/mb899/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/acpi/superio.asl b/src/mainboard/ibase/mb899/acpi/superio.asl index 37a48091a2..b49fe477a9 100644 --- a/src/mainboard/ibase/mb899/acpi/superio.asl +++ b/src/mainboard/ibase/mb899/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index 447b448231..a1f5397852 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index daa2999d44..1e88c3e18f 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index 2ed2c2e738..ead4771ca5 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index 838d3a31ed..10b8b33b32 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index 9c8a5ccc82..d1aa86a57f 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index d4d05c31dc..ce00fa5400 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index b24d8bf3c6..9a05fa4a50 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index f57a06dd66..6a2a875c23 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Edward O'Callaghan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ibase/mb899/superio_hwm.h b/src/mainboard/ibase/mb899/superio_hwm.h index c69ebc80a5..06b92301e4 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.h +++ b/src/mainboard/ibase/mb899/superio_hwm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Edward O'Callaghan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index ba17f289da..e4e121bf36 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index f013f698d6..ce38130106 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index e34704d79d..657f849c71 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/acpi/mainboard.asl b/src/mainboard/intel/baskingridge/acpi/mainboard.asl index c43d2dba7d..91bfe1a09d 100644 --- a/src/mainboard/intel/baskingridge/acpi/mainboard.asl +++ b/src/mainboard/intel/baskingridge/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/baskingridge/acpi/platform.asl b/src/mainboard/intel/baskingridge/acpi/platform.asl index bb2d6f9e86..9a79b56e72 100644 --- a/src/mainboard/intel/baskingridge/acpi/platform.asl +++ b/src/mainboard/intel/baskingridge/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/acpi/superio.asl b/src/mainboard/intel/baskingridge/acpi/superio.asl index 61b0e60f30..2d151969d4 100644 --- a/src/mainboard/intel/baskingridge/acpi/superio.asl +++ b/src/mainboard/intel/baskingridge/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl index 0c2779e61b..b7864f8599 100644 --- a/src/mainboard/intel/baskingridge/acpi/thermal.asl +++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 26d555008f..f688af22f8 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 72886d2439..a814c94ae6 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index 5251f25fed..4d77d7e308 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 1fcb967381..e185335439 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h index f2be9e3c84..7a18085d83 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/hda_verb.c b/src/mainboard/intel/baskingridge/hda_verb.c index 9a29297cf1..11041770e4 100644 --- a/src/mainboard/intel/baskingridge/hda_verb.c +++ b/src/mainboard/intel/baskingridge/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index ca93d31f7d..28dabf0f1c 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index da6f8e8199..cc9b0e7473 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1a10931431..2f89262c4d 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/baskingridge/thermal.h b/src/mainboard/intel/baskingridge/thermal.h index 41366f2636..e8a93cc01a 100644 --- a/src/mainboard/intel/baskingridge/thermal.h +++ b/src/mainboard/intel/baskingridge/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index d98477118d..acd9f112fe 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/bootblock.c b/src/mainboard/intel/cannonlake_rvp/bootblock.c index 710f513f81..c43ea9a503 100644 --- a/src/mainboard/intel/cannonlake_rvp/bootblock.c +++ b/src/mainboard/intel/cannonlake_rvp/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 6815193ff5..c23c49640b 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index c6070dd72f..6455c123a6 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c index 3dbae702e2..7cf4bfaa3f 100644 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c index edb5894ba5..91daaaebc8 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/smihandler.c b/src/mainboard/intel/cannonlake_rvp/smihandler.c index d5f6daeeb1..e2573d022a 100644 --- a/src/mainboard/intel/cannonlake_rvp/smihandler.c +++ b/src/mainboard/intel/cannonlake_rvp/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc index 026b541dfb..e76f5662de 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h index 4193e9cb2f..fc5686004a 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd.h +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 2499b32e2d..72439aa0d6 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index 2455422b74..560aab90da 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h index 934302c751..84d0c9ec9c 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h index 056c57b813..1f54bf7065 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c index 343b721031..42573712d9 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h index 4b6f579013..bcb87cb1d7 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h index 4b6f579013..bcb87cb1d7 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index a978dcbd27..cfa4a8497c 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c index cac219eca4..bba133f9bd 100644 --- a/src/mainboard/intel/coffeelake_rvp/bootblock.c +++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 55669bb1a9..48db5bcdbb 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 316fe55a9f..03ecf114a3 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/hda_verb.c index 9ab4778274..3fbc3a24c3 100644 --- a/src/mainboard/intel/coffeelake_rvp/hda_verb.c +++ b/src/mainboard/intel/coffeelake_rvp/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index aabb3edd57..6343f885e3 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index b093a20d2c..85d089f74a 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index 09ef148e36..e0532db7e3 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index 709249e918..62b0b372a8 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h index 36318d5ef7..84d0c9ec9c 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index 64ff69fcd4..bbdcedfdf6 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c index 34b161f919..d342678c3e 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h index f921f3ff1f..c285da7644 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Damien Zammit - * Copyright 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h index f921f3ff1f..c285da7644 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Damien Zammit - * Copyright 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h index 97c7113bfd..bcb87cb1d7 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h index 7a68625a28..d776f4c1b3 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h index c34a9b3cd9..bcb87cb1d7 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h index d821a26531..d776f4c1b3 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 003e009733..738eabc4e6 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl index debf4b123f..dc58f02077 100644 --- a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c index 6e619f494f..69787a93ea 100644 --- a/src/mainboard/intel/d510mo/acpi_tables.c +++ b/src/mainboard/intel/d510mo/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index b006973cc3..9fb41481e4 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c index bee17799df..62b3bd3fba 100644 --- a/src/mainboard/intel/d510mo/cstates.c +++ b/src/mainboard/intel/d510mo/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 825611ef22..c1d7a5dc89 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index a0e9b626f7..88b4e126e5 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d510mo/early_init.c b/src/mainboard/intel/d510mo/early_init.c index 3181d3f91b..68e1141abc 100644 --- a/src/mainboard/intel/d510mo/early_init.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d510mo/gpio.c b/src/mainboard/intel/d510mo/gpio.c index 81e23bade0..71e93613f2 100644 --- a/src/mainboard/intel/d510mo/gpio.c +++ b/src/mainboard/intel/d510mo/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c index a0dba38f59..6561ddf3a9 100644 --- a/src/mainboard/intel/d510mo/hda_verb.c +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index 3263f9a065..dd930d31ad 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 683ea2de06..6c78c1d3e3 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d945gclf/acpi/ec.asl b/src/mainboard/intel/d945gclf/acpi/ec.asl index 5362bb2e59..f42855b182 100644 --- a/src/mainboard/intel/d945gclf/acpi/ec.asl +++ b/src/mainboard/intel/d945gclf/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl index 0da7e7075c..a079c059e0 100644 --- a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl index 0454c3fe0a..5187b2a973 100644 --- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl +++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 21eb3df00d..01c7a94906 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/acpi/superio.asl b/src/mainboard/intel/d945gclf/acpi/superio.asl index 152302e7af..23e5fd5d26 100644 --- a/src/mainboard/intel/d945gclf/acpi/superio.asl +++ b/src/mainboard/intel/d945gclf/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index c212315d14..69787a93ea 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index 881fd41921..e5677fdcf1 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 7114a29a83..3d7e8c632a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index b94f5bd460..c9d81f523d 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c index d31fcc5907..61fa10ccd9 100644 --- a/src/mainboard/intel/d945gclf/early_init.c +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/gpio.c b/src/mainboard/intel/d945gclf/gpio.c index f5787f9d76..5c672afd8b 100644 --- a/src/mainboard/intel/d945gclf/gpio.c +++ b/src/mainboard/intel/d945gclf/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d945gclf/irq_tables.c b/src/mainboard/intel/d945gclf/irq_tables.c index 1a7e85b9a9..9235d23f22 100644 --- a/src/mainboard/intel/d945gclf/irq_tables.c +++ b/src/mainboard/intel/d945gclf/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index 89df425152..62d014733f 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/acpi/platform.asl b/src/mainboard/intel/dcp847ske/acpi/platform.asl index ff5b176923..5cce4b4997 100644 --- a/src/mainboard/intel/dcp847ske/acpi/platform.asl +++ b/src/mainboard/intel/dcp847ske/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index 20c71a333b..abf7e244e5 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index 0d9c2c55bb..c546640ba3 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 3ef27ebe3d..faf012600a 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 5610301fb3..f0b82f02f2 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/gma-mainboard.ads b/src/mainboard/intel/dcp847ske/gma-mainboard.ads index 493051edd6..4a7a7ac5b8 100644 --- a/src/mainboard/intel/dcp847ske/gma-mainboard.ads +++ b/src/mainboard/intel/dcp847ske/gma-mainboard.ads @@ -1,6 +1,5 @@ -- This file is part of the coreboot project. -- --- Copyright (C) 2017 Tobias Diedrich -- -- This program is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/gpio.c b/src/mainboard/intel/dcp847ske/gpio.c index 5b07d8032d..ebfefdf3dc 100644 --- a/src/mainboard/intel/dcp847ske/gpio.c +++ b/src/mainboard/intel/dcp847ske/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c index 25bf012285..1282140a25 100644 --- a/src/mainboard/intel/dcp847ske/hda_verb.c +++ b/src/mainboard/intel/dcp847ske/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/dcp847ske/mainboard.c index 1fc68fe6b0..8c443682ef 100644 --- a/src/mainboard/intel/dcp847ske/mainboard.c +++ b/src/mainboard/intel/dcp847ske/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 235ad228f8..34698f97e2 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/smihandler.c b/src/mainboard/intel/dcp847ske/smihandler.c index 7ae3f3982f..b8f4e765f0 100644 --- a/src/mainboard/intel/dcp847ske/smihandler.c +++ b/src/mainboard/intel/dcp847ske/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/dcp847ske/superio.h index 6f74d3e72c..31dc7d91cd 100644 --- a/src/mainboard/intel/dcp847ske/superio.h +++ b/src/mainboard/intel/dcp847ske/superio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h index 914b3232a4..1b7e863d9c 100644 --- a/src/mainboard/intel/dcp847ske/thermal.h +++ b/src/mainboard/intel/dcp847ske/thermal.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h index c6a529562a..10110fc010 100644 --- a/src/mainboard/intel/dcp847ske/usb.h +++ b/src/mainboard/intel/dcp847ske/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig index 648634ee51..f45e1ec131 100644 --- a/src/mainboard/intel/dg41wv/Kconfig +++ b/src/mainboard/intel/dg41wv/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl index 18e1f00145..3e37d9cd91 100644 --- a/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c index dede3173d0..b0370c1ef4 100644 --- a/src/mainboard/intel/dg41wv/acpi_tables.c +++ b/src/mainboard/intel/dg41wv/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index 0a59868efd..ac83eb86b0 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/cstates.c b/src/mainboard/intel/dg41wv/cstates.c index 128f6558e7..2a6d8ad816 100644 --- a/src/mainboard/intel/dg41wv/cstates.c +++ b/src/mainboard/intel/dg41wv/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index c00e998bcc..e24e304bbe 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index cddaa3af4e..6120949269 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg41wv/early_init.c b/src/mainboard/intel/dg41wv/early_init.c index 3cb40955d0..584b936eca 100644 --- a/src/mainboard/intel/dg41wv/early_init.c +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/gpio.c b/src/mainboard/intel/dg41wv/gpio.c index 404b4db3b9..643b6d4d2b 100644 --- a/src/mainboard/intel/dg41wv/gpio.c +++ b/src/mainboard/intel/dg41wv/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/hda_verb.c b/src/mainboard/intel/dg41wv/hda_verb.c index 23d566de96..b4d80beaa5 100644 --- a/src/mainboard/intel/dg41wv/hda_verb.c +++ b/src/mainboard/intel/dg41wv/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index 3c457ba1e2..bb7867694e 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl index 19882b87d0..8d12675cff 100644 --- a/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl +++ b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 22743730da..7e45c750c2 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index abeff71f8b..b92a95e997 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 07223b6614..86fae88c65 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index 71d175f705..87696d5dda 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg43gt/early_init.c b/src/mainboard/intel/dg43gt/early_init.c index 8457707ba1..3c1c7d178a 100644 --- a/src/mainboard/intel/dg43gt/early_init.c +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg43gt/gpio.c b/src/mainboard/intel/dg43gt/gpio.c index 69cd10a764..fdb25b41aa 100644 --- a/src/mainboard/intel/dg43gt/gpio.c +++ b/src/mainboard/intel/dg43gt/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg43gt/hda_verb.c b/src/mainboard/intel/dg43gt/hda_verb.c index e9b1fae1f9..fbc3eebf93 100644 --- a/src/mainboard/intel/dg43gt/hda_verb.c +++ b/src/mainboard/intel/dg43gt/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 3e78db075b..ab7044da5c 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl b/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl index c43d2dba7d..91bfe1a09d 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl index 8f4e6369af..f7f187d66e 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/platform.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl index 61b0e60f30..2d151969d4 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl index c3ec240ecf..62b5f5d10c 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index f9681ddf32..ebb9ba700b 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index ebf51e3c8e..1f087cec43 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 42da4adccb..84ed31fd01 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index c222888ede..f7e22a71d3 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 0bc5884e6a..23229b83b1 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index 350344a7ee..009e90f973 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/ec.h b/src/mainboard/intel/emeraldlake2/ec.h index e5746a561c..3e44b584e6 100644 --- a/src/mainboard/intel/emeraldlake2/ec.h +++ b/src/mainboard/intel/emeraldlake2/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c index 90010b9170..e8f7b10f0b 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.c +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/hda_verb.c b/src/mainboard/intel/emeraldlake2/hda_verb.c index 9a29297cf1..11041770e4 100644 --- a/src/mainboard/intel/emeraldlake2/hda_verb.c +++ b/src/mainboard/intel/emeraldlake2/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 2f09a7850c..d6141c7aa8 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index fd43334f54..b267f20a7b 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/emeraldlake2/thermal.h b/src/mainboard/intel/emeraldlake2/thermal.h index 3111e0a681..2fa579816e 100644 --- a/src/mainboard/intel/emeraldlake2/thermal.h +++ b/src/mainboard/intel/emeraldlake2/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 4ea7f474e3..26d56bc987 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015-2018 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name index 124aa7a737..d570f24c32 100644 --- a/src/mainboard/intel/galileo/Kconfig.name +++ b/src/mainboard/intel/galileo/Kconfig.name @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index d2ba44ff89..9e1defddfd 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015-2016 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/acpi_tables.c b/src/mainboard/intel/galileo/acpi_tables.c index bba8cedf30..80f4222b0e 100644 --- a/src/mainboard/intel/galileo/acpi_tables.c +++ b/src/mainboard/intel/galileo/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index f7d666d6f5..01182aa9b1 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015-2016 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl index 38d787db7d..b69ed78652 100644 --- a/src/mainboard/intel/galileo/dsdt.asl +++ b/src/mainboard/intel/galileo/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index 524daf8f67..fbe5edece5 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h index 253976e6df..30abe1ee94 100644 --- a/src/mainboard/intel/galileo/gen2.h +++ b/src/mainboard/intel/galileo/gen2.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 1fd7fce0c7..c29769e504 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/mainboard.c b/src/mainboard/intel/galileo/mainboard.c index 0237916e17..234a154b58 100644 --- a/src/mainboard/intel/galileo/mainboard.c +++ b/src/mainboard/intel/galileo/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index 7aca458839..c78ef8e2ac 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/reg_access.h b/src/mainboard/intel/galileo/reg_access.h index 451dc877a4..53ffc66265 100644 --- a/src/mainboard/intel/galileo/reg_access.h +++ b/src/mainboard/intel/galileo/reg_access.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/galileo/sd.c b/src/mainboard/intel/galileo/sd.c index fe2563ceae..f832876e2f 100644 --- a/src/mainboard/intel/galileo/sd.c +++ b/src/mainboard/intel/galileo/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 1a7b3e383f..3b377f21dd 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/bootblock.c b/src/mainboard/intel/glkrvp/bootblock.c index 1bf1aa3aa6..fe2513ba05 100644 --- a/src/mainboard/intel/glkrvp/bootblock.c +++ b/src/mainboard/intel/glkrvp/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 1cf35801a8..2e8d85af38 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 76b3f32954..294e350a71 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c index 44b7824224..9782397526 100644 --- a/src/mainboard/intel/glkrvp/ec.c +++ b/src/mainboard/intel/glkrvp/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index ddb805adbe..139d879def 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index 7811d06044..5420a16183 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c index 9af899398f..a08e17cdb8 100644 --- a/src/mainboard/intel/glkrvp/smihandler.c +++ b/src/mainboard/intel/glkrvp/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/touchpad.asl b/src/mainboard/intel/glkrvp/touchpad.asl index 6168fbbca3..fe7e9e5f8b 100644 --- a/src/mainboard/intel/glkrvp/touchpad.asl +++ b/src/mainboard/intel/glkrvp/touchpad.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/touchpanel.asl b/src/mainboard/intel/glkrvp/touchpanel.asl index 225b891ed4..53b6b68b77 100644 --- a/src/mainboard/intel/glkrvp/touchpanel.asl +++ b/src/mainboard/intel/glkrvp/touchpanel.asl @@ -2,7 +2,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 89a736f1bf..e05cd5d5fa 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 3cbb4bcd44..a08381d8a9 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl index f61f0b682e..8d18f92cec 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h index d31d35a403..f3c1fb9cba 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index 170e87c988..440b71bb7a 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h index cf91a049e9..0641a84555 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c index 1173ee4745..d1403e5005 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c index c35a2923f5..a5929d3db0 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl index f3ff04b5e9..2e6e9feadf 100644 --- a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl +++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h index 586f1064f4..87f03b1ece 100644 --- a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h +++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h index 6d1ce5a0e4..3777fed07b 100644 --- a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig index 271ff81892..e7a7e2b9d0 100644 --- a/src/mainboard/intel/harcuvar/Kconfig +++ b/src/mainboard/intel/harcuvar/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/Makefile.inc b/src/mainboard/intel/harcuvar/Makefile.inc index 271a577cd9..d8b174412a 100644 --- a/src/mainboard/intel/harcuvar/Makefile.inc +++ b/src/mainboard/intel/harcuvar/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2017 Intel Corporation. -## Copyright (C) 2017 Online SAS. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard.asl b/src/mainboard/intel/harcuvar/acpi/mainboard.asl index 41da3824ef..8d3f505cc6 100644 --- a/src/mainboard/intel/harcuvar/acpi/mainboard.asl +++ b/src/mainboard/intel/harcuvar/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl index e253cea8a2..b7254c91ba 100644 --- a/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl +++ b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/acpi/platform.asl b/src/mainboard/intel/harcuvar/acpi/platform.asl index 8d8229ab43..a1a1d214b9 100644 --- a/src/mainboard/intel/harcuvar/acpi/platform.asl +++ b/src/mainboard/intel/harcuvar/acpi/platform.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/acpi/thermal.asl b/src/mainboard/intel/harcuvar/acpi/thermal.asl index 5f9164da0d..8244266532 100644 --- a/src/mainboard/intel/harcuvar/acpi/thermal.asl +++ b/src/mainboard/intel/harcuvar/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 1f92419a75..551d51a47d 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/boardid.c b/src/mainboard/intel/harcuvar/boardid.c index 7edf3643ef..7ea9f87759 100644 --- a/src/mainboard/intel/harcuvar/boardid.c +++ b/src/mainboard/intel/harcuvar/boardid.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/devicetree.cb b/src/mainboard/intel/harcuvar/devicetree.cb index 7fce2113b6..4d45dd9c33 100644 --- a/src/mainboard/intel/harcuvar/devicetree.cb +++ b/src/mainboard/intel/harcuvar/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 32d6e3d395..41e9b5d957 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright 2011 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/emmc.h b/src/mainboard/intel/harcuvar/emmc.h index 9832191525..cc51b7c4f8 100644 --- a/src/mainboard/intel/harcuvar/emmc.h +++ b/src/mainboard/intel/harcuvar/emmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index d26987187b..bb4b31eb46 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/gpio.h b/src/mainboard/intel/harcuvar/gpio.h index 1ef465aa19..db4cc5c1d5 100644 --- a/src/mainboard/intel/harcuvar/gpio.h +++ b/src/mainboard/intel/harcuvar/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/harcuvar_boardid.h b/src/mainboard/intel/harcuvar/harcuvar_boardid.h index 3bcd60c831..d85b6d90c1 100644 --- a/src/mainboard/intel/harcuvar/harcuvar_boardid.h +++ b/src/mainboard/intel/harcuvar/harcuvar_boardid.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/hsio.c b/src/mainboard/intel/harcuvar/hsio.c index fa17130075..0c1861ce1b 100644 --- a/src/mainboard/intel/harcuvar/hsio.c +++ b/src/mainboard/intel/harcuvar/hsio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h index c59cfd02f8..f32fd3fd83 100644 --- a/src/mainboard/intel/harcuvar/hsio.h +++ b/src/mainboard/intel/harcuvar/hsio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/ramstage.c b/src/mainboard/intel/harcuvar/ramstage.c index 4d908587f9..92fcc7d096 100644 --- a/src/mainboard/intel/harcuvar/ramstage.c +++ b/src/mainboard/intel/harcuvar/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index 53ecdec0da..a5c13277f1 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/spd/Makefile.inc b/src/mainboard/intel/harcuvar/spd/Makefile.inc index 38d5046138..bd71aa3ad5 100644 --- a/src/mainboard/intel/harcuvar/spd/Makefile.inc +++ b/src/mainboard/intel/harcuvar/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 - 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index 61bf2e589b..ca1cc2b283 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/harcuvar/spd/spd.h b/src/mainboard/intel/harcuvar/spd/spd.h index 9c0174f9d2..1de7bed57d 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.h +++ b/src/mainboard/intel/harcuvar/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index 74d02cb293..b9dd971ddf 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl index ef2e164c93..521dfcb3cf 100644 --- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl +++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c index c0def22d38..c284df1f77 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ b/src/mainboard/intel/icelake_rvp/board_id.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/board_id.h b/src/mainboard/intel/icelake_rvp/board_id.h index 3ccfe37f42..6629244d92 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.h +++ b/src/mainboard/intel/icelake_rvp/board_id.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c index 300488f9a0..9022af8e8c 100644 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ b/src/mainboard/intel/icelake_rvp/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index be1e2914e7..e72333262a 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 5d730babb4..1a425f71d5 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c index f6ae630c98..2a2a31d7d9 100644 --- a/src/mainboard/intel/icelake_rvp/hda_verb.c +++ b/src/mainboard/intel/icelake_rvp/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 67695fa827..051c6a671f 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index 5a4d6814c4..833dcb9a1a 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc index d92ce96308..e9d660285e 100644 --- a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/spd/spd.h b/src/mainboard/intel/icelake_rvp/spd/spd.h index fbc4919372..fc5686004a 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd.h +++ b/src/mainboard/intel/icelake_rvp/spd/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index cb4a7928e7..36ba7d09c5 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h index ed335472e7..60ae713c5d 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h index ca303f9705..8d56b32f80 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h index d821a26531..d776f4c1b3 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index a00b3441d2..6beef66559 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc index 0c1af69985..9d44bb02d0 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index 36bfa233ee..be0cf111d9 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc index 0c1af69985..9d44bb02d0 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index 36bfa233ee..be0cf111d9 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index 81cbc6ee3a..745e0cfddb 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl b/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl index 6647ac183f..521dfcb3cf 100644 --- a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl +++ b/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.c b/src/mainboard/intel/jasperlake_rvp/board_id.c index 23312565b1..1913d3f0fc 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.c +++ b/src/mainboard/intel/jasperlake_rvp/board_id.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.h b/src/mainboard/intel/jasperlake_rvp/board_id.h index 9aac527ad0..86923b9b12 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.h +++ b/src/mainboard/intel/jasperlake_rvp/board_id.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/bootblock.c b/src/mainboard/intel/jasperlake_rvp/bootblock.c index 01b257cf9e..9022af8e8c 100644 --- a/src/mainboard/intel/jasperlake_rvp/bootblock.c +++ b/src/mainboard/intel/jasperlake_rvp/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 930f7488b6..2f2abb5e6b 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 4b9a696214..c996717b0e 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index d74c11c8ca..2f84d7af1f 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 0ab1f48fee..b072a9099d 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index b8b059a1b7..4cde260d52 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd.h b/src/mainboard/intel/jasperlake_rvp/spd/spd.h index ed8b8b6e0d..dcc0144a0b 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd.h +++ b/src/mainboard/intel/jasperlake_rvp/spd/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c index bdf8edea93..92d183dbc9 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h index a8a147a3cd..60ae713c5d 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h index 227ec7563a..8d56b32f80 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index 9220b1140c..6beef66559 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc index 23bf160883..9d44bb02d0 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index bf6d517691..91292b8c40 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index ffed7a257d..dbea38e62a 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2016 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl index c33bb064e3..0e19caab6d 100644 --- a/src/mainboard/intel/kblrvp/acpi/dptf.asl +++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index efed4de820..eb9eb0eb7c 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl b/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl index 211ca43ad6..a498246e65 100644 --- a/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 531cd21336..521dfcb3cf 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index 1efad473f1..c1c9bbb127 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/acpi/superio.asl b/src/mainboard/intel/kblrvp/acpi/superio.asl index 803d2e3f47..f5178b3ed0 100644 --- a/src/mainboard/intel/kblrvp/acpi/superio.asl +++ b/src/mainboard/intel/kblrvp/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/board_id.c b/src/mainboard/intel/kblrvp/board_id.c index dc5afcfbcf..9d87a3eda1 100644 --- a/src/mainboard/intel/kblrvp/board_id.c +++ b/src/mainboard/intel/kblrvp/board_id.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/board_id.h b/src/mainboard/intel/kblrvp/board_id.h index 16eab690c6..db9d2ba9cf 100644 --- a/src/mainboard/intel/kblrvp/board_id.h +++ b/src/mainboard/intel/kblrvp/board_id.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c index dde7e8612a..6d1885ecb4 100644 --- a/src/mainboard/intel/kblrvp/bootblock.c +++ b/src/mainboard/intel/kblrvp/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index d7b98377f2..c862907170 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 916db62983..a0edabdccb 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2016 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 3da6547f54..97fe66892b 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/ec.c b/src/mainboard/intel/kblrvp/ec.c index b40aabf73c..eb5456a231 100644 --- a/src/mainboard/intel/kblrvp/ec.c +++ b/src/mainboard/intel/kblrvp/ec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/ec.h b/src/mainboard/intel/kblrvp/ec.h index 2498244f21..dcdaae404e 100644 --- a/src/mainboard/intel/kblrvp/ec.h +++ b/src/mainboard/intel/kblrvp/ec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/hda_verb.c b/src/mainboard/intel/kblrvp/hda_verb.c index fdd196dc88..50468cd135 100644 --- a/src/mainboard/intel/kblrvp/hda_verb.c +++ b/src/mainboard/intel/kblrvp/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation - * (Written by Naresh G Solanki for Intel Corp.) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index d2e8719f33..46c35cb0db 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index a19e96ec70..f276913725 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 1ae7d6e504..35ba6ed3d2 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index e2fc7da6f0..1673cd0df1 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index 966dec0c29..7651bd3cbd 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index e745a25f7b..de348f5000 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index a0a81ba06e..33970e147f 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index 74c885f643..5a26b61d18 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h index 4119e695ee..1b083a3ee6 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h index 64d0259404..7265b1affa 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h index 9d6e8b00ec..725623ae0d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation - * (Written by Naresh G Solanki for Intel Corp.) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index 07b52d3056..2c8c1df378 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h index d0f68c8366..0a38bed223 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation - * (Written by Naresh G Solanki for Intel Corp.) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index f8db6cd258..320e7a6c20 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 9a667d6a36..46ea86cddc 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index df2c0eb21b..b2b702d93b 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/acpi/ec.asl b/src/mainboard/intel/kunimitsu/acpi/ec.asl index 4599e1266f..09f5892067 100644 --- a/src/mainboard/intel/kunimitsu/acpi/ec.asl +++ b/src/mainboard/intel/kunimitsu/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index 7416934a81..0e84faab18 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/acpi/superio.asl b/src/mainboard/intel/kunimitsu/acpi/superio.asl index 803d2e3f47..f5178b3ed0 100644 --- a/src/mainboard/intel/kunimitsu/acpi/superio.asl +++ b/src/mainboard/intel/kunimitsu/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c index 627b4e8b08..534dad9b3d 100644 --- a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c +++ b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index ffdfa37faa..c7454b49fa 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index d032d604e3..a0edabdccb 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index fbb2371449..879e888c4e 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/ec.c b/src/mainboard/intel/kunimitsu/ec.c index 32ae8ba22f..eb5456a231 100644 --- a/src/mainboard/intel/kunimitsu/ec.c +++ b/src/mainboard/intel/kunimitsu/ec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/ec.h b/src/mainboard/intel/kunimitsu/ec.h index fcb0a70796..dcdaae404e 100644 --- a/src/mainboard/intel/kunimitsu/ec.h +++ b/src/mainboard/intel/kunimitsu/ec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 43a7f06d3b..fff0fc4e41 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index be2f262d2d..40275fd6c6 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 44fb9cdc9f..975951ecae 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index e2b065c1cc..ddd3c03565 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 490812138b..35945851cf 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 814d04df4b..b673a71c9a 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index ad6453e7b8..8fbc09a777 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 2fe4596e56..39a189b0ec 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c index e35e8b8e7f..3c8d5bd89c 100644 --- a/src/mainboard/intel/leafhill/bootblock.c +++ b/src/mainboard/intel/leafhill/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h index 18d130b450..25e1029397 100644 --- a/src/mainboard/intel/leafhill/brd_gpio.h +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index 94dc024b32..f6f274489f 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/leafhill/mainboard.c b/src/mainboard/intel/leafhill/mainboard.c index f7a2ef1c99..1bc4152be2 100644 --- a/src/mainboard/intel/leafhill/mainboard.c +++ b/src/mainboard/intel/leafhill/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c index 5c784ba629..154a838e1b 100644 --- a/src/mainboard/intel/leafhill/romstage.c +++ b/src/mainboard/intel/leafhill/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c index 93236f029b..1f5bddbc0e 100644 --- a/src/mainboard/intel/minnow3/bootblock.c +++ b/src/mainboard/intel/minnow3/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index 94dc024b32..f6f274489f 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/minnow3/gpio.c b/src/mainboard/intel/minnow3/gpio.c index 330a24258b..f8ff0e42cd 100644 --- a/src/mainboard/intel/minnow3/gpio.c +++ b/src/mainboard/intel/minnow3/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/minnow3/gpio.h b/src/mainboard/intel/minnow3/gpio.h index 60d5e31fbf..57cece9783 100644 --- a/src/mainboard/intel/minnow3/gpio.h +++ b/src/mainboard/intel/minnow3/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/minnow3/mainboard.c b/src/mainboard/intel/minnow3/mainboard.c index f9e932e2ff..574ef039d4 100644 --- a/src/mainboard/intel/minnow3/mainboard.c +++ b/src/mainboard/intel/minnow3/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c index 451e7b4739..66a40a1f0a 100644 --- a/src/mainboard/intel/minnow3/romstage.c +++ b/src/mainboard/intel/minnow3/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 315104e846..411e3d57b9 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc index 683462b9de..b62bcf9c27 100644 --- a/src/mainboard/intel/saddlebrook/Makefile.inc +++ b/src/mainboard/intel/saddlebrook/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2016 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl index 5174eeb887..55d11ab44c 100644 --- a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl +++ b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/bootblock.c b/src/mainboard/intel/saddlebrook/bootblock.c index cf9740db80..9d0a99b44b 100644 --- a/src/mainboard/intel/saddlebrook/bootblock.c +++ b/src/mainboard/intel/saddlebrook/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout index 83a2e05351..3fc1ee0a7e 100644 --- a/src/mainboard/intel/saddlebrook/cmos.layout +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2016 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index c2dd6f97cf..333212593c 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index 8d6dc2e6dd..fa047f8d6b 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index 98feea2f22..4db74cfe88 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c index ed37681822..975951ecae 100644 --- a/src/mainboard/intel/saddlebrook/ramstage.c +++ b/src/mainboard/intel/saddlebrook/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 8e280de638..a9447a2218 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/spd/Makefile.inc b/src/mainboard/intel/saddlebrook/spd/Makefile.inc index 721736dcbc..b312ae55f3 100644 --- a/src/mainboard/intel/saddlebrook/spd/Makefile.inc +++ b/src/mainboard/intel/saddlebrook/spd/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index d7936636df..cb38a1b1db 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index b6cf08547a..2f9fd07527 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 3f88b3d64e..70bfb5a686 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl index 2a95703b6e..6ac42aa8cf 100644 --- a/src/mainboard/intel/strago/acpi/dptf.asl +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl index e023f3ba2b..0b131615fb 100644 --- a/src/mainboard/intel/strago/acpi/ec.asl +++ b/src/mainboard/intel/strago/acpi/ec.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index caaae86b95..b43219e1e3 100644 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/strago/acpi/superio.asl b/src/mainboard/intel/strago/acpi/superio.asl index 340243a953..35be89e496 100644 --- a/src/mainboard/intel/strago/acpi/superio.asl +++ b/src/mainboard/intel/strago/acpi/superio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 518e0aa41c..265d110829 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 654906f60f..ef61cadbdf 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index cc5ec2dabe..a0edabdccb 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index 695ea9806b..88d8d091b6 100644 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index 0028fd7a53..8ce41a99de 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index 9ff06391a1..8ebd096da5 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/ec.h b/src/mainboard/intel/strago/ec.h index 1092977b03..450d863ba3 100644 --- a/src/mainboard/intel/strago/ec.h +++ b/src/mainboard/intel/strago/ec.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index 2a54254aa1..9e5af024e4 100644 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 9acc8a00c5..3a2adffb59 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/irqroute.c b/src/mainboard/intel/strago/irqroute.c index 79dc8d6c91..f0855adbc2 100644 --- a/src/mainboard/intel/strago/irqroute.c +++ b/src/mainboard/intel/strago/irqroute.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/irqroute.h b/src/mainboard/intel/strago/irqroute.h index c80594541b..85d8a5f93b 100644 --- a/src/mainboard/intel/strago/irqroute.h +++ b/src/mainboard/intel/strago/irqroute.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 21a57cbc39..8e7deff412 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index a6176dd52e..c483b27c51 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index a05cd90eff..47f791dc1c 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 1dc7ba32fc..b312e53441 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index a52c4ca76f..f378eb7bea 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c index 5598de48a1..9e0b30a5fb 100644 --- a/src/mainboard/intel/strago/w25q64.c +++ b/src/mainboard/intel/strago/w25q64.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 81cbc6ee3a..745e0cfddb 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl index 6647ac183f..521dfcb3cf 100644 --- a/src/mainboard/intel/tglrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/tglrvp/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index af03ddc03c..9cb8817098 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/board_id.c b/src/mainboard/intel/tglrvp/board_id.c index 23312565b1..1913d3f0fc 100644 --- a/src/mainboard/intel/tglrvp/board_id.c +++ b/src/mainboard/intel/tglrvp/board_id.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index 8d0a31751b..748e9d912f 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c index 01b257cf9e..9022af8e8c 100644 --- a/src/mainboard/intel/tglrvp/bootblock.c +++ b/src/mainboard/intel/tglrvp/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 930f7488b6..2f2abb5e6b 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index 8236ccb110..89104e9ab0 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 9af9d42911..e773df5883 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index eb8fde0a6a..d636bc89c4 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc index 21ea65e807..131e938e21 100644 --- a/src/mainboard/intel/tglrvp/spd/Makefile.inc +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h index 9e746243cc..f5ba411a50 100644 --- a/src/mainboard/intel/tglrvp/spd/spd.h +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/spd/spd_util.c b/src/mainboard/intel/tglrvp/spd/spd_util.c index 4bfd964e30..fa1204ec74 100644 --- a/src/mainboard/intel/tglrvp/spd/spd_util.c +++ b/src/mainboard/intel/tglrvp/spd/spd_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index a8a147a3cd..60ae713c5d 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h index 227ec7563a..8d56b32f80 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index 25c9755d9d..29f9a7176c 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc index c272607042..7a3ce63467 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index fa97a503b0..4b600e6d0b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index 67979b649b..1cb0df52df 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc index c272607042..7a3ce63467 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index c00f6d1137..3ee9ec7022 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index f3a8a48d45..651550c753 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index c4afb98cc5..9dd899cdf3 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/acpi/mainboard.asl b/src/mainboard/intel/wtm2/acpi/mainboard.asl index 0140343164..776b63e2fc 100644 --- a/src/mainboard/intel/wtm2/acpi/mainboard.asl +++ b/src/mainboard/intel/wtm2/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/wtm2/acpi/platform.asl b/src/mainboard/intel/wtm2/acpi/platform.asl index b510fc13b2..92c98614d7 100644 --- a/src/mainboard/intel/wtm2/acpi/platform.asl +++ b/src/mainboard/intel/wtm2/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/acpi/thermal.asl b/src/mainboard/intel/wtm2/acpi/thermal.asl index 5eb885efcf..e8af50bf87 100644 --- a/src/mainboard/intel/wtm2/acpi/thermal.asl +++ b/src/mainboard/intel/wtm2/acpi/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 8ceea46e07..727d17572c 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index d64d9ef552..6926ed08aa 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index 39f9516e0b..014f442651 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 7b676f41a4..d4de0ca0b1 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 7d9096c804..621beb9655 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/gpio.c b/src/mainboard/intel/wtm2/gpio.c index c81ad10081..c2d7bf87d2 100644 --- a/src/mainboard/intel/wtm2/gpio.c +++ b/src/mainboard/intel/wtm2/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/hda_verb.c b/src/mainboard/intel/wtm2/hda_verb.c index 8718e5f295..11041770e4 100644 --- a/src/mainboard/intel/wtm2/hda_verb.c +++ b/src/mainboard/intel/wtm2/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 8ce494b5fc..fbe3981cc5 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index 705904e5d9..c1e3f21d4a 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 9edc170a21..db2ecf5bcd 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/wtm2/thermal.h b/src/mainboard/intel/wtm2/thermal.h index 9408c91eba..e26631fd7b 100644 --- a/src/mainboard/intel/wtm2/thermal.h +++ b/src/mainboard/intel/wtm2/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index c2227ae935..c27a33d183 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index d2dda6725f..35c9e27e23 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Edward O'Callaghan . # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index bf86007cec..f0a8fe6109 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index 73f5c2ccfb..4fbe3b8a11 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan . * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h +++ b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index 3cf38c035a..af4e2e48b7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl index 2cf17a7f69..70c5da5ef0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl index 47de049dbc..08144ff427 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl index 4f23d99904..db519899e8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl @@ -3,7 +3,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2014 Edward O'Callaghan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl index a209909b32..5b22875dd1 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c index 5ecfaf74f8..6a8e578fa7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c +++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan . * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 65986e26fc..583dfb2e58 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout index f9f52f7546..275de95ad2 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout +++ b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index b5d51ef501..1a414dac22 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Edward O'Callaghan . # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index 1b66682b73..d190f8c8e8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index bec87cba31..8239e77015 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index cbf75a49ce..55dee3314a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Edward O'Callaghan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 9a983b41f9..5ef3850a20 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Edward O'Callaghan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index 314daa8143..666d528ede 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan . * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/acpi/ec.asl b/src/mainboard/kontron/986lcd-m/acpi/ec.asl index 5b3a2318b1..a4510d8de5 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/ec.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl index 67915f281f..953989bfa4 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/acpi/platform.asl b/src/mainboard/kontron/986lcd-m/acpi/platform.asl index 98661102fb..4b161bc565 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/platform.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/acpi/superio.asl b/src/mainboard/kontron/986lcd-m/acpi/superio.asl index 37a48091a2..b49fe477a9 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/superio.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 447b448231..a1f5397852 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index 135c19acdc..f9084b3a9c 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 8c5d6e177a..64ad9c77f1 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 827f792946..2e4ef822bb 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/gpio.c b/src/mainboard/kontron/986lcd-m/gpio.c index c879a9ca34..aa529a5819 100644 --- a/src/mainboard/kontron/986lcd-m/gpio.c +++ b/src/mainboard/kontron/986lcd-m/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index fc67c22ea7..979863c004 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 30368e8f91..b072ba4b95 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index a5018f2233..103dfbc81a 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/acpi/mainboard.asl b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl index 3b6df54821..53ec05098a 100644 --- a/src/mainboard/kontron/ktqm77/acpi/mainboard.asl +++ b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/kontron/ktqm77/acpi/platform.asl b/src/mainboard/kontron/ktqm77/acpi/platform.asl index 49bcea191f..b345b6d19f 100644 --- a/src/mainboard/kontron/ktqm77/acpi/platform.asl +++ b/src/mainboard/kontron/ktqm77/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/acpi/thermal.asl b/src/mainboard/kontron/ktqm77/acpi/thermal.asl index 3d01b6d2e8..7dfd7ab248 100644 --- a/src/mainboard/kontron/ktqm77/acpi/thermal.asl +++ b/src/mainboard/kontron/ktqm77/acpi/thermal.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index b9d951091b..9ef2b66097 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 4ad959660c..f180754492 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index cbabce4f4a..d8071f5b74 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index df5f57e29a..c76acbf63e 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/gpio.c b/src/mainboard/kontron/ktqm77/gpio.c index 4b886575a2..d64f8d8f13 100644 --- a/src/mainboard/kontron/ktqm77/gpio.c +++ b/src/mainboard/kontron/ktqm77/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/hda_verb.c b/src/mainboard/kontron/ktqm77/hda_verb.c index 9935ca498e..b485831875 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.c +++ b/src/mainboard/kontron/ktqm77/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2013 secunet Security Networks AG - * Copyright (C) 2013 Nico Huber * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 5cd3fc4234..6dffa4cda2 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/kontron/ktqm77/thermal.h b/src/mainboard/kontron/ktqm77/thermal.h index e0e10708cc..a0235c7f18 100644 --- a/src/mainboard/kontron/ktqm77/thermal.h +++ b/src/mainboard/kontron/ktqm77/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index dfe53eaad9..f51a65ca35 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 6ffe508ff9..fda7505344 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index f030989b36..f56c5e5bac 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index f842129ae2..7cf1ab8eac 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/OptionsIds.h b/src/mainboard/lenovo/g505s/OptionsIds.h index b1dc4ae997..bc9ab3221c 100644 --- a/src/mainboard/lenovo/g505s/OptionsIds.h +++ b/src/mainboard/lenovo/g505s/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/ec.asl b/src/mainboard/lenovo/g505s/acpi/ec.asl index ccceba4cfd..d49c26b118 100644 --- a/src/mainboard/lenovo/g505s/acpi/ec.asl +++ b/src/mainboard/lenovo/g505s/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index f28ad50207..b986afd065 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl index 5068e9fe9e..3bbd215f83 100644 --- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl +++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index a1ce860682..7b9534437e 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/si.asl b/src/mainboard/lenovo/g505s/acpi/si.asl index ff0c3cfc0d..cc27e983e1 100644 --- a/src/mainboard/lenovo/g505s/acpi/si.asl +++ b/src/mainboard/lenovo/g505s/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl index d516ccedb0..d5a1f683a8 100644 --- a/src/mainboard/lenovo/g505s/acpi/sleep.asl +++ b/src/mainboard/lenovo/g505s/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl index 4719f5f594..e5182fc4c8 100644 --- a/src/mainboard/lenovo/g505s/acpi/superio.asl +++ b/src/mainboard/lenovo/g505s/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Edward O'Callaghan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl index ae064feb1f..1f1419d526 100644 --- a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl +++ b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c index fd59a3aade..be2669eeb8 100644 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ b/src/mainboard/lenovo/g505s/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 66cdefda67..1c8e1e6d66 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index dcbf81b7a1..001a9e07fc 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 623a78b108..be5c1f5cdb 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index ce11be8caa..b36a1de71d 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/ec.c b/src/mainboard/lenovo/g505s/ec.c index bc2bb24df3..8471167c5a 100644 --- a/src/mainboard/lenovo/g505s/ec.c +++ b/src/mainboard/lenovo/g505s/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index 63579b1bc4..2826494353 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c index fb04069628..7864872b45 100644 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ b/src/mainboard/lenovo/g505s/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index c9e00b6982..b7effa2bcb 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h index ebae80c8c4..06abb1151b 100644 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/mainboard_smi.c index 27b1ac2a7c..a0c35a33e9 100644 --- a/src/mainboard/lenovo/g505s/mainboard_smi.c +++ b/src/mainboard/lenovo/g505s/mainboard_smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index 3b2c4a2988..421253e3b6 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index c03276795c..c35b4c5dd7 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/l520/acpi/ec.asl b/src/mainboard/lenovo/l520/acpi/ec.asl index 9b60a68c28..45bafff30d 100644 --- a/src/mainboard/lenovo/l520/acpi/ec.asl +++ b/src/mainboard/lenovo/l520/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index 534408e509..d63f75aaa8 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/acpi/superio.asl b/src/mainboard/lenovo/l520/acpi/superio.asl index 7b69fda7fc..03ab48a04c 100644 --- a/src/mainboard/lenovo/l520/acpi/superio.asl +++ b/src/mainboard/lenovo/l520/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index 7acbe2c47b..2081a80998 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout index 9faee06496..12941f3482 100644 --- a/src/mainboard/lenovo/l520/cmos.layout +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c index 2d1f8b5c8f..fdbfa0976c 100644 --- a/src/mainboard/lenovo/l520/early_init.c +++ b/src/mainboard/lenovo/l520/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/gpio.c b/src/mainboard/lenovo/l520/gpio.c index c7818abdf7..d5328fbd33 100644 --- a/src/mainboard/lenovo/l520/gpio.c +++ b/src/mainboard/lenovo/l520/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c index 5181978fc7..4f741eec10 100644 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index 88c7884f28..b2cb5521ff 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c index 425c05d47c..e15a06bb37 100644 --- a/src/mainboard/lenovo/l520/smihandler.c +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index b59c269ebf..87adcb2cc1 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle - * Copyright (c) 2013 Vladimir Serbinenko - * Copyright (c) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/acpi/gpe.asl b/src/mainboard/lenovo/s230u/acpi/gpe.asl index e6f4153aca..747a2aec37 100644 --- a/src/mainboard/lenovo/s230u/acpi/gpe.asl +++ b/src/mainboard/lenovo/s230u/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/acpi/platform.asl b/src/mainboard/lenovo/s230u/acpi/platform.asl index d90715ab51..e5008952dc 100644 --- a/src/mainboard/lenovo/s230u/acpi/platform.asl +++ b/src/mainboard/lenovo/s230u/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index a0fc2ecd59..d3c7a8f51f 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/s230u/ec.c b/src/mainboard/lenovo/s230u/ec.c index f3e01b68be..dd59cc31d9 100644 --- a/src/mainboard/lenovo/s230u/ec.c +++ b/src/mainboard/lenovo/s230u/ec.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index d65b2e1026..ddb4280786 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/s230u/gpio.c b/src/mainboard/lenovo/s230u/gpio.c index 31bb6fa885..9cf64e263c 100644 --- a/src/mainboard/lenovo/s230u/gpio.c +++ b/src/mainboard/lenovo/s230u/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c index d3c1cdd9e4..15bedc85ae 100644 --- a/src/mainboard/lenovo/s230u/hda_verb.c +++ b/src/mainboard/lenovo/s230u/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c index ea4b9b6773..42bddf749a 100644 --- a/src/mainboard/lenovo/s230u/mainboard.c +++ b/src/mainboard/lenovo/s230u/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c index 668fe697dd..58683d6aca 100644 --- a/src/mainboard/lenovo/s230u/smihandler.c +++ b/src/mainboard/lenovo/s230u/smihandler.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Tobias Diedrich * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index 5d5669e2a3..9fff90c804 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t400/acpi/dock.asl b/src/mainboard/lenovo/t400/acpi/dock.asl index 4a0ccf3b1f..40add6d703 100644 --- a/src/mainboard/lenovo/t400/acpi/dock.asl +++ b/src/mainboard/lenovo/t400/acpi/dock.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/acpi/gpe.asl b/src/mainboard/lenovo/t400/acpi/gpe.asl index 3b45262652..a32dacdb85 100644 --- a/src/mainboard/lenovo/t400/acpi/gpe.asl +++ b/src/mainboard/lenovo/t400/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl index 038774fdfd..8901bbf93d 100644 --- a/src/mainboard/lenovo/t400/acpi/graphics.asl +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl index b206c2b992..ecc805abcf 100644 --- a/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl +++ b/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/acpi/platform.asl b/src/mainboard/lenovo/t400/acpi/platform.asl index 85357a50df..eca012be8e 100644 --- a/src/mainboard/lenovo/t400/acpi/platform.asl +++ b/src/mainboard/lenovo/t400/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 0e43081a43..66accb94ce 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/blc.c b/src/mainboard/lenovo/t400/blc.c index 02c883c781..b42eee01b8 100644 --- a/src/mainboard/lenovo/t400/blc.c +++ b/src/mainboard/lenovo/t400/blc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 arthur@aheymans.xyz * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 9ab29b4ed1..73236cf8b7 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH -# 2012 secunet Security Networks AG # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c index 34bceafac7..d6143d11b6 100644 --- a/src/mainboard/lenovo/t400/cstates.c +++ b/src/mainboard/lenovo/t400/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 2eb9903bb7..3236117830 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/dock.h b/src/mainboard/lenovo/t400/dock.h index 4d2b32b9b7..cec94e7271 100644 --- a/src/mainboard/lenovo/t400/dock.h +++ b/src/mainboard/lenovo/t400/dock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index edf69ab359..6ea787b7f4 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index 9f4ebf6fe5..c3c9015ab6 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/hda_verb.c b/src/mainboard/lenovo/t400/hda_verb.c index 98901511cc..3c42b3c47d 100644 --- a/src/mainboard/lenovo/t400/hda_verb.c +++ b/src/mainboard/lenovo/t400/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t400/mainboard.c b/src/mainboard/lenovo/t400/mainboard.c index b475e0979b..26bb537938 100644 --- a/src/mainboard/lenovo/t400/mainboard.c +++ b/src/mainboard/lenovo/t400/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 4b0a4c7352..75adc5bb52 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index 518d91a2b6..fa6e7057fe 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t410/acpi/dock.asl b/src/mainboard/lenovo/t410/acpi/dock.asl index 2bba82141c..d38f03c03c 100644 --- a/src/mainboard/lenovo/t410/acpi/dock.asl +++ b/src/mainboard/lenovo/t410/acpi/dock.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/acpi/ec.asl b/src/mainboard/lenovo/t410/acpi/ec.asl index c00121bab5..5ca4034f2b 100644 --- a/src/mainboard/lenovo/t410/acpi/ec.asl +++ b/src/mainboard/lenovo/t410/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl index 3b45262652..a32dacdb85 100644 --- a/src/mainboard/lenovo/t410/acpi/gpe.asl +++ b/src/mainboard/lenovo/t410/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/acpi/platform.asl b/src/mainboard/lenovo/t410/acpi/platform.asl index c2cb94c242..a5c80f2e39 100644 --- a/src/mainboard/lenovo/t410/acpi/platform.asl +++ b/src/mainboard/lenovo/t410/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c index 3628b772cb..3794345dc5 100644 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout index 5c7defa839..12b6568cc4 100644 --- a/src/mainboard/lenovo/t410/cmos.layout +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2013 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index e18ec385d2..c48285e44c 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c index 1575aa1906..8e32b6a758 100644 --- a/src/mainboard/lenovo/t410/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/dock.h b/src/mainboard/lenovo/t410/dock.h index 6a08d81836..af368b3ddd 100644 --- a/src/mainboard/lenovo/t410/dock.h +++ b/src/mainboard/lenovo/t410/dock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index f8e989ad1b..f3592cac2e 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/early_init.c b/src/mainboard/lenovo/t410/early_init.c index ba222f60d3..6a6b2e8521 100644 --- a/src/mainboard/lenovo/t410/early_init.c +++ b/src/mainboard/lenovo/t410/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/gpio.c index 2eeeca5469..f5e9a04aad 100644 --- a/src/mainboard/lenovo/t410/gpio.c +++ b/src/mainboard/lenovo/t410/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 7f60c0d10d..523ff73599 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index 8b6a737e0e..cc4eb38d33 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index f15a919aa7..7b87c31d3d 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index 70a9e5dd22..5ff6125f1e 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 080812e44a..05befddc9b 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420/acpi/ec.asl b/src/mainboard/lenovo/t420/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/t420/acpi/ec.asl +++ b/src/mainboard/lenovo/t420/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/t420/acpi/platform.asl +++ b/src/mainboard/lenovo/t420/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/t420/acpi_tables.c +++ b/src/mainboard/lenovo/t420/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index a9f5f5ff47..f9b75f293f 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index 43cb236439..7130c6a3ff 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index c675512d6f..1d267d1db7 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index ede37f3fbb..62b2eab41d 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index bc6dcb17dc..d4be588542 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c index bc92cf1b78..a87e9089fd 100644 --- a/src/mainboard/lenovo/t420/smihandler.c +++ b/src/mainboard/lenovo/t420/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 080812e44a..05befddc9b 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/t420s/acpi/ec.asl +++ b/src/mainboard/lenovo/t420s/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ b/src/mainboard/lenovo/t420s/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 172191a59a..26e63005bb 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index 43cb236439..7130c6a3ff 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 276c66e18e..6c19a5ef4f 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420s/hda_verb.c index e2841162c8..c3ac350f0c 100644 --- a/src/mainboard/lenovo/t420s/hda_verb.c +++ b/src/mainboard/lenovo/t420s/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index bc6dcb17dc..d4be588542 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 044da44021..f0ecb0ba1e 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl index ec45363125..2fd8472cdf 100644 --- a/src/mainboard/lenovo/t430/acpi/ec.asl +++ b/src/mainboard/lenovo/t430/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl index ed8e16c09e..d7adb54b47 100644 --- a/src/mainboard/lenovo/t430/acpi/platform.asl +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl index 8964c36efa..606085fafe 100644 --- a/src/mainboard/lenovo/t430/acpi/superio.asl +++ b/src/mainboard/lenovo/t430/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index 82ddd9f269..8c10384915 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index f9757f0794..05c659777a 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index b22dc37041..8f68174840 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 27258a3a57..5e4c6ac2be 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c index 4a90179ebf..c266330351 100644 --- a/src/mainboard/lenovo/t430/gpio.c +++ b/src/mainboard/lenovo/t430/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c index 833f98e01d..874e26c47b 100644 --- a/src/mainboard/lenovo/t430/hda_verb.c +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index a86a90e553..d4be588542 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c index 6c887d608f..b3d5ea3676 100644 --- a/src/mainboard/lenovo/t430/smihandler.c +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index d9f54d5989..42879bcd79 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/acpi/ec.asl b/src/mainboard/lenovo/t430s/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/t430s/acpi/ec.asl +++ b/src/mainboard/lenovo/t430s/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/t430s/acpi/platform.asl +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 891a29414c..29d865232b 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index 43cb236439..7130c6a3ff 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index bc6dcb17dc..d4be588542 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index f06eaf717f..a51eddc0e2 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c index 250f3b6de6..ba97d987da 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index 84bd447ab2..d939072251 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/variants/t431s/gpio.c b/src/mainboard/lenovo/t430s/variants/t431s/gpio.c index 5e0684cf6c..f4d147bdcc 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/gpio.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c index 0442f05eef..2782d729e7 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 7da2c55533..e3679a46ad 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc index 72657b4c23..f920859216 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc +++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Alexander Couzens ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/acpi/ec.asl b/src/mainboard/lenovo/t440p/acpi/ec.asl index 3ff0ff7cbc..e3a00aac2c 100644 --- a/src/mainboard/lenovo/t440p/acpi/ec.asl +++ b/src/mainboard/lenovo/t440p/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Iru Cai * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/acpi/platform.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl index add8c2da18..567d302031 100644 --- a/src/mainboard/lenovo/t440p/acpi/platform.asl +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Iru Cai * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/acpi/superio.asl b/src/mainboard/lenovo/t440p/acpi/superio.asl index 3139e35be5..bef9a0325e 100644 --- a/src/mainboard/lenovo/t440p/acpi/superio.asl +++ b/src/mainboard/lenovo/t440p/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Iru Cai * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c index 5105053d8a..445d4b57a7 100644 --- a/src/mainboard/lenovo/t440p/acpi_tables.c +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index be0b5031bd..54277c94c0 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 69cd4160e6..94e70433df 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Iru Cai * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/gpio.c b/src/mainboard/lenovo/t440p/gpio.c index cdb707ac1a..36443df7b4 100644 --- a/src/mainboard/lenovo/t440p/gpio.c +++ b/src/mainboard/lenovo/t440p/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c index 3f1ee36e0a..d1843456e2 100644 --- a/src/mainboard/lenovo/t440p/hda_verb.c +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t440p/mainboard.c b/src/mainboard/lenovo/t440p/mainboard.c index 0881c2dda6..6f3b5b89d9 100644 --- a/src/mainboard/lenovo/t440p/mainboard.c +++ b/src/mainboard/lenovo/t440p/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Iru Cai * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 283a52b460..1e4f17a797 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index eafb2aee9b..f5dd8a3cec 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 8f3c154418..58815b6c6a 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/acpi/ec.asl b/src/mainboard/lenovo/t520/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/t520/acpi/ec.asl +++ b/src/mainboard/lenovo/t520/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index ec6ce858eb..592dfcab02 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## Copyright (C) 2018 Nico Rikken ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 43cb236439..7130c6a3ff 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index 8e5bf2ae44..22dcb25348 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/hda_verb.c b/src/mainboard/lenovo/t520/hda_verb.c index e431172bbe..e141fde3da 100644 --- a/src/mainboard/lenovo/t520/hda_verb.c +++ b/src/mainboard/lenovo/t520/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 6825b6b29f..38ef280bf4 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index f06eaf717f..a51eddc0e2 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t520/variants/t520/gpio.c b/src/mainboard/lenovo/t520/variants/t520/gpio.c index a4351bb5ba..6b329c69e9 100644 --- a/src/mainboard/lenovo/t520/variants/t520/gpio.c +++ b/src/mainboard/lenovo/t520/variants/t520/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/variants/t520/romstage.c b/src/mainboard/lenovo/t520/variants/t520/romstage.c index 6db4d6913d..a77445502a 100644 --- a/src/mainboard/lenovo/t520/variants/t520/romstage.c +++ b/src/mainboard/lenovo/t520/variants/t520/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/variants/w520/gpio.c b/src/mainboard/lenovo/t520/variants/w520/gpio.c index 9d9a83a1fe..2f9c9957f9 100644 --- a/src/mainboard/lenovo/t520/variants/w520/gpio.c +++ b/src/mainboard/lenovo/t520/variants/w520/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t520/variants/w520/romstage.c b/src/mainboard/lenovo/t520/variants/w520/romstage.c index aeee54a208..5c37237df0 100644 --- a/src/mainboard/lenovo/t520/variants/w520/romstage.c +++ b/src/mainboard/lenovo/t520/variants/w520/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 8f3c154418..58815b6c6a 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/acpi/ec.asl b/src/mainboard/lenovo/t530/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/t530/acpi/ec.asl +++ b/src/mainboard/lenovo/t530/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 0c8c546e11..791885a4d1 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 43cb236439..7130c6a3ff 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c index c6ff7e7038..76a5deb5ef 100644 --- a/src/mainboard/lenovo/t530/early_init.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 916268f010..a6b3e6a9ee 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 144fde7f2e..d6a8ed788c 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index f06eaf717f..a51eddc0e2 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c index 7138de2fb9..dfe0085eb3 100644 --- a/src/mainboard/lenovo/t530/variants/t530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t530/variants/w530/gpio.c b/src/mainboard/lenovo/t530/variants/w530/gpio.c index 8eb776bfae..4ed4a528c9 100644 --- a/src/mainboard/lenovo/t530/variants/w530/gpio.c +++ b/src/mainboard/lenovo/t530/variants/w530/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c index 9fe6f84647..7520bc3b1a 100644 --- a/src/mainboard/lenovo/t530/variants/w530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index b604b6b126..3cac95eda0 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t60/acpi/dock.asl b/src/mainboard/lenovo/t60/acpi/dock.asl index 5085b29fb3..7801a04ce9 100644 --- a/src/mainboard/lenovo/t60/acpi/dock.asl +++ b/src/mainboard/lenovo/t60/acpi/dock.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/acpi/ec.asl b/src/mainboard/lenovo/t60/acpi/ec.asl index fe7115aa77..579f77460f 100644 --- a/src/mainboard/lenovo/t60/acpi/ec.asl +++ b/src/mainboard/lenovo/t60/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/acpi/gpe.asl b/src/mainboard/lenovo/t60/acpi/gpe.asl index 3b45262652..a32dacdb85 100644 --- a/src/mainboard/lenovo/t60/acpi/gpe.asl +++ b/src/mainboard/lenovo/t60/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl index 4c7c3a3757..38cf00dcd3 100644 --- a/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl index f9e991b984..bbbc2ff05a 100644 --- a/src/mainboard/lenovo/t60/acpi/platform.asl +++ b/src/mainboard/lenovo/t60/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl index 6db3a44c9e..62d7132744 100644 --- a/src/mainboard/lenovo/t60/acpi/video.asl +++ b/src/mainboard/lenovo/t60/acpi/video.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index a0d493f763..4bb6b50b56 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index d7ff0f2907..f765b75436 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 702902bb22..08c8fca2c6 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 05dd65ef3e..080a9c84ab 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h index 6a9efc2ef9..219f673fff 100644 --- a/src/mainboard/lenovo/t60/dock.h +++ b/src/mainboard/lenovo/t60/dock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 749f852edf..e7a7e50c15 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c index edd167a7ec..23502c3091 100644 --- a/src/mainboard/lenovo/t60/early_init.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/gpio.c b/src/mainboard/lenovo/t60/gpio.c index 2ddeb0436f..a316e4eb5e 100644 --- a/src/mainboard/lenovo/t60/gpio.c +++ b/src/mainboard/lenovo/t60/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans - * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 93cad771ae..9a09c7d39f 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 85b569a560..4f5166393b 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/smi.h b/src/mainboard/lenovo/t60/smi.h index f20314f743..a4cb73d3b4 100644 --- a/src/mainboard/lenovo/t60/smi.h +++ b/src/mainboard/lenovo/t60/smi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 3e97ed4a73..c84712fd0b 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb index eee3a4d575..2933fcb1b7 100644 --- a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb index d29df3b488..113db0b018 100644 --- a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index b42866cee7..150072b06c 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl index 4540ce814d..31744e4636 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c index dede3173d0..b0370c1ef4 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout index 0a59868efd..ac83eb86b0 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout +++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/cstates.c b/src/mainboard/lenovo/thinkcentre_a58/cstates.c index 128f6558e7..2a6d8ad816 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cstates.c +++ b/src/mainboard/lenovo/thinkcentre_a58/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index aedbf0ca83..b9a53dffc1 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Arthur Heymans # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index cddaa3af4e..6120949269 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/thinkcentre_a58/early_init.c b/src/mainboard/lenovo/thinkcentre_a58/early_init.c index a8f6443948..483e22a666 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/early_init.c +++ b/src/mainboard/lenovo/thinkcentre_a58/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/gpio.c b/src/mainboard/lenovo/thinkcentre_a58/gpio.c index bd3d581faa..758198f37c 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/gpio.c +++ b/src/mainboard/lenovo/thinkcentre_a58/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c index 94ffcfe4a8..57c632457b 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c +++ b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Arthur Heymans * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 1d258758be..3ed751d7b5 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/acpi/ec.asl b/src/mainboard/lenovo/x131e/acpi/ec.asl index acbb778800..579f77460f 100644 --- a/src/mainboard/lenovo/x131e/acpi/ec.asl +++ b/src/mainboard/lenovo/x131e/acpi/ec.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle - * Copyright (c) 2017 James Ye * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/x131e/acpi/platform.asl +++ b/src/mainboard/lenovo/x131e/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/acpi/superio.asl b/src/mainboard/lenovo/x131e/acpi/superio.asl index 253a358202..606085fafe 100644 --- a/src/mainboard/lenovo/x131e/acpi/superio.asl +++ b/src/mainboard/lenovo/x131e/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/x131e/acpi_tables.c +++ b/src/mainboard/lenovo/x131e/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 41b8354dd3..10d62dec45 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index ff80f1599c..4aa74c5d2c 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c index 49ee92c37c..8cbcf29b94 100644 --- a/src/mainboard/lenovo/x131e/early_init.c +++ b/src/mainboard/lenovo/x131e/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/gpio.c b/src/mainboard/lenovo/x131e/gpio.c index e51e9af3d1..47aad82e14 100644 --- a/src/mainboard/lenovo/x131e/gpio.c +++ b/src/mainboard/lenovo/x131e/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/hda_verb.c b/src/mainboard/lenovo/x131e/hda_verb.c index 0c3dac910b..3ff0fa4784 100644 --- a/src/mainboard/lenovo/x131e/hda_verb.c +++ b/src/mainboard/lenovo/x131e/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 50b4de1ee2..d4be588542 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index f6331a61d1..c4fea34ec1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index 55a8a58962..06832bbdf4 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 29235d77a1..862c869a3a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 859148abc2..52c317c30e 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Alexander Couzens * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c index e5beabc5c2..cc2011bb9c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c index d07672d79b..b2de7b1ea8 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index bc6dcb17dc..d4be588542 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c index 6c887d608f..b3d5ea3676 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index 235fc102d1..76a181efe2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Alexander Couzens ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index 7e38a78b4c..3df6377657 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x200/acpi/dock.asl b/src/mainboard/lenovo/x200/acpi/dock.asl index 93ad24c418..1edead0af2 100644 --- a/src/mainboard/lenovo/x200/acpi/dock.asl +++ b/src/mainboard/lenovo/x200/acpi/dock.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/acpi/gpe.asl b/src/mainboard/lenovo/x200/acpi/gpe.asl index 3b45262652..a32dacdb85 100644 --- a/src/mainboard/lenovo/x200/acpi/gpe.asl +++ b/src/mainboard/lenovo/x200/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl index b206c2b992..ecc805abcf 100644 --- a/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl +++ b/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index 85357a50df..eca012be8e 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 0e43081a43..66accb94ce 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/blc.c b/src/mainboard/lenovo/x200/blc.c index 42b5df24ed..cdd39a11b5 100644 --- a/src/mainboard/lenovo/x200/blc.c +++ b/src/mainboard/lenovo/x200/blc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 arthur@aheymans.xyz * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index ebae12d452..f8e3f8e134 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH -# 2012 secunet Security Networks AG # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c index 34bceafac7..d6143d11b6 100644 --- a/src/mainboard/lenovo/x200/cstates.c +++ b/src/mainboard/lenovo/x200/cstates.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x200/dock.h b/src/mainboard/lenovo/x200/dock.h index a129cd04a3..c68d4c23bb 100644 --- a/src/mainboard/lenovo/x200/dock.h +++ b/src/mainboard/lenovo/x200/dock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 1290ece4b3..e97d47e223 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index 9f4ebf6fe5..c3c9015ab6 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/hda_verb.c b/src/mainboard/lenovo/x200/hda_verb.c index 890b6c52c6..001e436f25 100644 --- a/src/mainboard/lenovo/x200/hda_verb.c +++ b/src/mainboard/lenovo/x200/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 37fe865e81..37823bc92f 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index f7d8487530..f90f04b4ff 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x200/variants/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c index 8aa39bbd6e..d51afec7a6 100644 --- a/src/mainboard/lenovo/x200/variants/x200/dock.c +++ b/src/mainboard/lenovo/x200/variants/x200/dock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index 548beff15d..1c32e5648b 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl index b3381a710c..35e62dfbc0 100644 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ b/src/mainboard/lenovo/x201/acpi/dock.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl index 411a0ece82..6085f18463 100644 --- a/src/mainboard/lenovo/x201/acpi/ec.asl +++ b/src/mainboard/lenovo/x201/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index 3b45262652..a32dacdb85 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index ece96c4408..4694d9c43e 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 3628b772cb..3794345dc5 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 990db6df06..2a8b27e1cd 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2013 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index d347261330..8b6f1486cd 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index 58510ced89..d5f122e5e0 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h index 6a08d81836..af368b3ddd 100644 --- a/src/mainboard/lenovo/x201/dock.h +++ b/src/mainboard/lenovo/x201/dock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index f8e989ad1b..f3592cac2e 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/early_init.c b/src/mainboard/lenovo/x201/early_init.c index 7383381ce9..6a6b2e8521 100644 --- a/src/mainboard/lenovo/x201/early_init.c +++ b/src/mainboard/lenovo/x201/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/x201/gpio.c index ee63f87137..fd370d8a62 100644 --- a/src/mainboard/lenovo/x201/gpio.c +++ b/src/mainboard/lenovo/x201/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c index 5e9a9fd8e5..d521321e24 100644 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ b/src/mainboard/lenovo/x201/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index ebfe7a8bc6..212f3a90cf 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8bf6f902ca..4b4177a699 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 70a9e5dd22..5ff6125f1e 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 4363770d28..5ef50e8fe1 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/acpi/ec.asl b/src/mainboard/lenovo/x220/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/x220/acpi/ec.asl +++ b/src/mainboard/lenovo/x220/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index dc98010ea2..43c468318b 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 43cb236439..7130c6a3ff 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 3429c1b9bf..9750b8a6bf 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/hda_verb.c b/src/mainboard/lenovo/x220/hda_verb.c index 470c639dff..8b32616043 100644 --- a/src/mainboard/lenovo/x220/hda_verb.c +++ b/src/mainboard/lenovo/x220/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 144fde7f2e..d6a8ed788c 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index f06eaf717f..a51eddc0e2 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x220/variants/x1/gpio.c b/src/mainboard/lenovo/x220/variants/x1/gpio.c index 023f3f3f9d..cd68e8c5cf 100644 --- a/src/mainboard/lenovo/x220/variants/x1/gpio.c +++ b/src/mainboard/lenovo/x220/variants/x1/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Bill Xie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x220/variants/x1/romstage.c b/src/mainboard/lenovo/x220/variants/x1/romstage.c index a1932cc8e2..41757b26b7 100644 --- a/src/mainboard/lenovo/x220/variants/x1/romstage.c +++ b/src/mainboard/lenovo/x220/variants/x1/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x220/variants/x220/romstage.c b/src/mainboard/lenovo/x220/variants/x220/romstage.c index 88a93961df..2b68275ed6 100644 --- a/src/mainboard/lenovo/x220/variants/x220/romstage.c +++ b/src/mainboard/lenovo/x220/variants/x220/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 080812e44a..05befddc9b 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/acpi/ec.asl b/src/mainboard/lenovo/x230/acpi/ec.asl index 4b11e56bed..825ff7a6af 100644 --- a/src/mainboard/lenovo/x230/acpi/ec.asl +++ b/src/mainboard/lenovo/x230/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index e4c8a24f78..f3b0e1ad28 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index acb77d43a0..c828ea1bec 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 99034009a4..3155dd79c3 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 43cb236439..7130c6a3ff 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c index 70240a7832..30e5846579 100644 --- a/src/mainboard/lenovo/x230/early_init.c +++ b/src/mainboard/lenovo/x230/early_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/gpio.c b/src/mainboard/lenovo/x230/gpio.c index 85d086c2f1..47cd5ffc05 100644 --- a/src/mainboard/lenovo/x230/gpio.c +++ b/src/mainboard/lenovo/x230/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index f5b5bfdab0..e3faeef4c2 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 144fde7f2e..d6a8ed788c 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 6c887d608f..b3d5ea3676 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index 7fb2f0268e..ceed4a4491 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index 5a931d4ab1..4f601e386c 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl index fe7115aa77..579f77460f 100644 --- a/src/mainboard/lenovo/x60/acpi/ec.asl +++ b/src/mainboard/lenovo/x60/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 3b45262652..a32dacdb85 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl index 4c7c3a3757..38cf00dcd3 100644 --- a/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl index f9e991b984..bbbc2ff05a 100644 --- a/src/mainboard/lenovo/x60/acpi/platform.asl +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index a0d493f763..4bb6b50b56 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index bfc78bc414..58fbef590a 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 4b56e93ab7..2ebd981950 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index b94d818077..d44105e51f 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/dock.h b/src/mainboard/lenovo/x60/dock.h index a8911ddf04..4c41c88fdd 100644 --- a/src/mainboard/lenovo/x60/dock.h +++ b/src/mainboard/lenovo/x60/dock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 32465d3ef4..2828e323b7 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/early_init.c b/src/mainboard/lenovo/x60/early_init.c index 8cf5ab498d..8c4fc1dfd8 100644 --- a/src/mainboard/lenovo/x60/early_init.c +++ b/src/mainboard/lenovo/x60/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/gpio.c b/src/mainboard/lenovo/x60/gpio.c index 0498443513..74fcfa7483 100644 --- a/src/mainboard/lenovo/x60/gpio.c +++ b/src/mainboard/lenovo/x60/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Arthur Heymans * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x60/irq_tables.c b/src/mainboard/lenovo/x60/irq_tables.c index 01e1c29d05..e5519c7c33 100644 --- a/src/mainboard/lenovo/x60/irq_tables.c +++ b/src/mainboard/lenovo/x60/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 964e9c0b52..7b399e4478 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 22c5907e8e..8abb2a26de 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x60/smi.h b/src/mainboard/lenovo/x60/smi.h index cf7a1922a6..9ab047eaf3 100644 --- a/src/mainboard/lenovo/x60/smi.h +++ b/src/mainboard/lenovo/x60/smi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index d5c92e5ae0..df33133ade 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index 9ce9ec768e..536ea44907 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 92d77434f5..e7952037bd 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 46a44d20ef..0576704326 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c index 5010c63c76..6f2ba23fc3 100644 --- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c +++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/frontrunner-af/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/lippert/frontrunner-af/OptionsIds.h +++ b/src/mainboard/lippert/frontrunner-af/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index 985cac0b31..b09b7b2eda 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/acpi/sata.asl b/src/mainboard/lippert/frontrunner-af/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/sata.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/acpi/superio.asl b/src/mainboard/lippert/frontrunner-af/acpi/superio.asl index 57ef408a2e..0ad6829902 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/superio.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/superio.asl @@ -3,8 +3,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2012 LiPPERT ADLINK Technology GmbH - * (Written by Jens Rottmann for LiPPERT) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index cd76bf1f94..77a4855274 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/bootblock.c index e0dddc20cc..a9a24a91c1 100644 --- a/src/mainboard/lippert/frontrunner-af/bootblock.c +++ b/src/mainboard/lippert/frontrunner-af/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 0563243623..cbf94e9c3e 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout index f9f52f7546..275de95ad2 100644 --- a/src/mainboard/lippert/frontrunner-af/cmos.layout +++ b/src/mainboard/lippert/frontrunner-af/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb index 0f89d255b0..1a2250abde 100644 --- a/src/mainboard/lippert/frontrunner-af/devicetree.cb +++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 9fcc7aef03..bf166c67af 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 9e3eab7a6c..5285bf48d3 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 347b7810b6..463262dd61 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index c64ad04dfa..7bd11ded16 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 7e6d0c485e..3f90631448 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 74b335a9fa..03c9d666cd 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index 7e4f2804bb..ed4ad12c3f 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c index 22addb5b75..7674021e02 100644 --- a/src/mainboard/lippert/toucan-af/OemCustomize.c +++ b/src/mainboard/lippert/toucan-af/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/lippert/toucan-af/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ b/src/mainboard/lippert/toucan-af/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/acpi/routing.asl b/src/mainboard/lippert/toucan-af/acpi/routing.asl index 997843d3ac..4f31f6dc4c 100644 --- a/src/mainboard/lippert/toucan-af/acpi/routing.asl +++ b/src/mainboard/lippert/toucan-af/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/acpi/sata.asl b/src/mainboard/lippert/toucan-af/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/lippert/toucan-af/acpi/sata.asl +++ b/src/mainboard/lippert/toucan-af/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/acpi/superio.asl b/src/mainboard/lippert/toucan-af/acpi/superio.asl index 57ef408a2e..0ad6829902 100644 --- a/src/mainboard/lippert/toucan-af/acpi/superio.asl +++ b/src/mainboard/lippert/toucan-af/acpi/superio.asl @@ -3,8 +3,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2012 LiPPERT ADLINK Technology GmbH - * (Written by Jens Rottmann for LiPPERT) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl index cd76bf1f94..77a4855274 100644 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ b/src/mainboard/lippert/toucan-af/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/bootblock.c b/src/mainboard/lippert/toucan-af/bootblock.c index 39b108e6dc..b5625f5008 100644 --- a/src/mainboard/lippert/toucan-af/bootblock.c +++ b/src/mainboard/lippert/toucan-af/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 0563243623..cbf94e9c3e 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/cmos.layout b/src/mainboard/lippert/toucan-af/cmos.layout index f9f52f7546..275de95ad2 100644 --- a/src/mainboard/lippert/toucan-af/cmos.layout +++ b/src/mainboard/lippert/toucan-af/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index ce05afc9ce..2003d9e970 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 4e36c2b152..cc2a48ed5e 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 158613fcac..0993baaf8a 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 347b7810b6..463262dd61 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index 3285d16c28..122191411f 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig index bd5ab69cd9..4b920441a6 100644 --- a/src/mainboard/msi/Kconfig +++ b/src/mainboard/msi/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7707/acpi/platform.asl b/src/mainboard/msi/ms7707/acpi/platform.asl index 7c3b3c61ff..d356d9b52b 100644 --- a/src/mainboard/msi/ms7707/acpi/platform.asl +++ b/src/mainboard/msi/ms7707/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7707/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c index 6727616f4b..2b8c10087b 100644 --- a/src/mainboard/msi/ms7707/acpi_tables.c +++ b/src/mainboard/msi/ms7707/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 553754d160..ca6f5a0d3a 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Tristan Corrick * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7707/early_init.c b/src/mainboard/msi/ms7707/early_init.c index 480e196e90..535ac23ff2 100644 --- a/src/mainboard/msi/ms7707/early_init.c +++ b/src/mainboard/msi/ms7707/early_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/msi/ms7707/gpio.c b/src/mainboard/msi/ms7707/gpio.c index 8fd8e44581..18e55c0c4c 100644 --- a/src/mainboard/msi/ms7707/gpio.c +++ b/src/mainboard/msi/ms7707/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c index 5221c6d29c..a508c5ebf9 100644 --- a/src/mainboard/msi/ms7707/hda_verb.c +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c index eb3c43cb13..ed1809d4f6 100644 --- a/src/mainboard/msi/ms7721/BiosCallOuts.c +++ b/src/mainboard/msi/ms7721/BiosCallOuts.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Renze Nicolai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 1fee74790e..9d92c35bb1 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2012 Rudolf Marek -# Copyright (C) 2016 Renze Nicolai # # This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/msi/ms7721/Makefile.inc b/src/mainboard/msi/ms7721/Makefile.inc index 4dde2cfd1e..55bdeb552e 100644 --- a/src/mainboard/msi/ms7721/Makefile.inc +++ b/src/mainboard/msi/ms7721/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 4782e11271..7c81afa37c 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Renze Nicolai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/OptionsIds.h b/src/mainboard/msi/ms7721/OptionsIds.h index b45f5a8766..dc507e8241 100644 --- a/src/mainboard/msi/ms7721/OptionsIds.h +++ b/src/mainboard/msi/ms7721/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/acpi/cpstate.asl b/src/mainboard/msi/ms7721/acpi/cpstate.asl index 3cbc0ad60b..c88aa64bcf 100644 --- a/src/mainboard/msi/ms7721/acpi/cpstate.asl +++ b/src/mainboard/msi/ms7721/acpi/cpstate.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/acpi/gpe.asl b/src/mainboard/msi/ms7721/acpi/gpe.asl index 297db37a67..be9f9fce2d 100644 --- a/src/mainboard/msi/ms7721/acpi/gpe.asl +++ b/src/mainboard/msi/ms7721/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/acpi/mainboard.asl b/src/mainboard/msi/ms7721/acpi/mainboard.asl index 8398c88c68..8cad2d8160 100644 --- a/src/mainboard/msi/ms7721/acpi/mainboard.asl +++ b/src/mainboard/msi/ms7721/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl index 5443dd5307..e6deee00dc 100644 --- a/src/mainboard/msi/ms7721/acpi/routing.asl +++ b/src/mainboard/msi/ms7721/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/acpi/si.asl b/src/mainboard/msi/ms7721/acpi/si.asl index ff0c3cfc0d..cc27e983e1 100644 --- a/src/mainboard/msi/ms7721/acpi/si.asl +++ b/src/mainboard/msi/ms7721/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/acpi/sleep.asl b/src/mainboard/msi/ms7721/acpi/sleep.asl index 08b7de47f3..1ce04c2336 100644 --- a/src/mainboard/msi/ms7721/acpi/sleep.asl +++ b/src/mainboard/msi/ms7721/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/acpi_tables.c b/src/mainboard/msi/ms7721/acpi_tables.c index fd59a3aade..be2669eeb8 100644 --- a/src/mainboard/msi/ms7721/acpi_tables.c +++ b/src/mainboard/msi/ms7721/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/bootblock.c b/src/mainboard/msi/ms7721/bootblock.c index 7274bc3317..23570cd427 100644 --- a/src/mainboard/msi/ms7721/bootblock.c +++ b/src/mainboard/msi/ms7721/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2012 Rudolf Marek - * Copyright (C) 2016 Renze Nicolai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 2dd223d73d..436844f324 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout index e1dbd9a3dd..4a18471301 100644 --- a/src/mainboard/msi/ms7721/cmos.layout +++ b/src/mainboard/msi/ms7721/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index cb860742ed..e77cf912f4 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2016 Renze Nicolai # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index cfa74c89ff..d10d953f8e 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2016 Renze Nicolai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/irq_tables.c b/src/mainboard/msi/ms7721/irq_tables.c index e0d5ad4641..4022ebb513 100644 --- a/src/mainboard/msi/ms7721/irq_tables.c +++ b/src/mainboard/msi/ms7721/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c index 2a0e618b24..32ebebef30 100644 --- a/src/mainboard/msi/ms7721/mainboard.c +++ b/src/mainboard/msi/ms7721/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index 303f3bf5c4..b9eba0bedb 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index cb87615424..637360b05b 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2012 Rudolf Marek - * Copyright (C) 2016 Renze Nicolai * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 87e27600dd..b3b43fb20d 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 - 2020 Intel Corporation. -## Copyright (C) 2019 - 2020 Facebook Inc ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index f5ea5911f9..7a0a43fb8f 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 - 2020 Intel Corporation. -## Copyright (C) 2019 - 2020 Facebook Inc ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl index e349cf337a..a10c4068f7 100644 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 - 2020 Intel Corporation. - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index c4dda3b357..76778a9bed 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 46311d9823..4a5bb1d3f2 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 - 2020 Intel Corporation. -## Copyright (C) 2019 - 2020 Facebook Inc ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index aca6c4d79b..41c006bc92 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c index 6962455813..00a54db816 100644 --- a/src/mainboard/ocp/tiogapass/fadt.c +++ b/src/mainboard/ocp/tiogapass/fadt.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 35a7faa99a..8282eb09f4 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index c95a69674d..8f9806f250 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h index 5987caa883..44098b1290 100644 --- a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h index 0ad92f2fd8..403702035c 100644 --- a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/Kconfig b/src/mainboard/opencellular/Kconfig index f82e923829..f1b4bd4659 100644 --- a/src/mainboard/opencellular/Kconfig +++ b/src/mainboard/opencellular/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 3ba2a60bc4..69725ad899 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2018 Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/Makefile.inc b/src/mainboard/opencellular/elgon/Makefile.inc index 343a52ec0b..7ee8abb124 100644 --- a/src/mainboard/opencellular/elgon/Makefile.inc +++ b/src/mainboard/opencellular/elgon/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/bdk_devicetree.c b/src/mainboard/opencellular/elgon/bdk_devicetree.c index 9f8c64efa4..7836c21485 100644 --- a/src/mainboard/opencellular/elgon/bdk_devicetree.c +++ b/src/mainboard/opencellular/elgon/bdk_devicetree.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c index baf6391ce6..cce1afa243 100644 --- a/src/mainboard/opencellular/elgon/bootblock.c +++ b/src/mainboard/opencellular/elgon/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/death.c b/src/mainboard/opencellular/elgon/death.c index ac58e846a0..72be17dc2a 100644 --- a/src/mainboard/opencellular/elgon/death.c +++ b/src/mainboard/opencellular/elgon/death.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/devicetree.cb b/src/mainboard/opencellular/elgon/devicetree.cb index 07d508a8b3..e2c38db059 100644 --- a/src/mainboard/opencellular/elgon/devicetree.cb +++ b/src/mainboard/opencellular/elgon/devicetree.cb @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/gbcv2.dts b/src/mainboard/opencellular/elgon/gbcv2.dts index 299794768c..04453a2ab1 100644 --- a/src/mainboard/opencellular/elgon/gbcv2.dts +++ b/src/mainboard/opencellular/elgon/gbcv2.dts @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/mainboard.c b/src/mainboard/opencellular/elgon/mainboard.c index 74e31e1709..14411089e5 100644 --- a/src/mainboard/opencellular/elgon/mainboard.c +++ b/src/mainboard/opencellular/elgon/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. (support@cavium.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/mainboard.h b/src/mainboard/opencellular/elgon/mainboard.h index f268649e05..2e4d01cec4 100644 --- a/src/mainboard/opencellular/elgon/mainboard.h +++ b/src/mainboard/opencellular/elgon/mainboard.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/opencellular/elgon/romstage.c b/src/mainboard/opencellular/elgon/romstage.c index d907351d94..3e4ba490da 100644 --- a/src/mainboard/opencellular/elgon/romstage.c +++ b/src/mainboard/opencellular/elgon/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index c35cde680f..d8200f9e36 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/packardbell/ms2290/acpi/ac.asl b/src/mainboard/packardbell/ms2290/acpi/ac.asl index 536c3ad658..b3e960c06b 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ac.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ac.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl index 4f3e5b6c16..5b214b692b 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ec.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/acpi/gpe.asl b/src/mainboard/packardbell/ms2290/acpi/gpe.asl index 4f12532642..bc2b470fce 100644 --- a/src/mainboard/packardbell/ms2290/acpi/gpe.asl +++ b/src/mainboard/packardbell/ms2290/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index a8296cc677..73ed8e7826 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index 4bc39b1af6..1a932a6ba9 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout index 1670cb0a6f..590dda2935 100644 --- a/src/mainboard/packardbell/ms2290/cmos.layout +++ b/src/mainboard/packardbell/ms2290/cmos.layout @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2013 Vladimir Serbinenko ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 21b6a6dc51..231e2cbf3e 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle ## ## This program is free software; you can redistribute it and/or ## modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index e53d728b74..bb96c79bc0 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/hda_verb.c b/src/mainboard/packardbell/ms2290/hda_verb.c index 7a90d1e0f6..68646d7661 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.c +++ b/src/mainboard/packardbell/ms2290/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 805eecbece..cc9421526e 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 03ea86d01c..d502741174 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index 2d77564efe..694cd8c72a 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index f738aa363d..d2a598aae0 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3396845559..d25825eb38 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Kyösti Mälkki # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index 3aa3bbe67c..57c78fa005 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2013 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 9febec73d0..14ee634cc1 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/OptionsIds.h b/src/mainboard/pcengines/apu1/OptionsIds.h index 2d8381b28c..b4fe940569 100644 --- a/src/mainboard/pcengines/apu1/OptionsIds.h +++ b/src/mainboard/pcengines/apu1/OptionsIds.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/buttons.asl b/src/mainboard/pcengines/apu1/acpi/buttons.asl index a2120a98e2..c5733fa15a 100644 --- a/src/mainboard/pcengines/apu1/acpi/buttons.asl +++ b/src/mainboard/pcengines/apu1/acpi/buttons.asl @@ -3,7 +3,6 @@ * * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ * - * Copyright (C) 2015 Tobias Diedrich, Mika Westerberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl index 3cf38c035a..af4e2e48b7 100644 --- a/src/mainboard/pcengines/apu1/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu1/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/gpio.asl b/src/mainboard/pcengines/apu1/acpi/gpio.asl index 5f0ae71fbf..570da93ee7 100644 --- a/src/mainboard/pcengines/apu1/acpi/gpio.asl +++ b/src/mainboard/pcengines/apu1/acpi/gpio.asl @@ -3,7 +3,6 @@ * * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ * - * Copyright (C) 2015 Tobias Diedrich, Mika Westerberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/leds.asl b/src/mainboard/pcengines/apu1/acpi/leds.asl index 1e447f1eb5..b4ccf188b2 100644 --- a/src/mainboard/pcengines/apu1/acpi/leds.asl +++ b/src/mainboard/pcengines/apu1/acpi/leds.asl @@ -3,7 +3,6 @@ * * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ * - * Copyright (C) 2015 Tobias Diedrich, Mika Westerberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/mainboard.asl b/src/mainboard/pcengines/apu1/acpi/mainboard.asl index 702cb92032..3d4abb5d7b 100644 --- a/src/mainboard/pcengines/apu1/acpi/mainboard.asl +++ b/src/mainboard/pcengines/apu1/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index 79ebef3f03..befa15d272 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/sata.asl b/src/mainboard/pcengines/apu1/acpi/sata.asl index 9e0e535da6..9729500d48 100644 --- a/src/mainboard/pcengines/apu1/acpi/sata.asl +++ b/src/mainboard/pcengines/apu1/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl index 47de049dbc..08144ff427 100644 --- a/src/mainboard/pcengines/apu1/acpi/sleep.asl +++ b/src/mainboard/pcengines/apu1/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl index a209909b32..5b22875dd1 100644 --- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/acpi_tables.c b/src/mainboard/pcengines/apu1/acpi_tables.c index 97ea6492fb..9e3032474e 100644 --- a/src/mainboard/pcengines/apu1/acpi_tables.c +++ b/src/mainboard/pcengines/apu1/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 3c037e524b..2b73fb1dcb 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 767b0b0626..60509982e9 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Kyösti Mälkki # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index efb584e92c..d461220b0e 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 206dc63c9d..bd1342c363 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h index fb582721d2..551f009817 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.h +++ b/src/mainboard/pcengines/apu1/gpio_ftns.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c index 3ce0ffcaa8..f962314546 100644 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ b/src/mainboard/pcengines/apu1/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 0528468e5d..14eab8b490 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index 89e5dfc35b..b6cb9d13b7 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 7172e8283e..ed1ce3b5cb 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index df91b04c0a..42d85ace80 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC - * Copyright (C) 2014 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 1ae5301267..d6f8d84300 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 501d583c68..b434ddc810 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2015 Kyösti Mälkki -# Copyright (C) 2016 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 84ea41485c..94ca4335b0 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2016 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 7ef7e00fc7..99b9d518e7 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl index 4a6f6f8158..573c847f76 100644 --- a/src/mainboard/pcengines/apu2/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl index 68609d868e..837292b76d 100644 --- a/src/mainboard/pcengines/apu2/acpi/mainboard.asl +++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl index 1fb4c1dfdf..0411c2a6b7 100644 --- a/src/mainboard/pcengines/apu2/acpi/routing.asl +++ b/src/mainboard/pcengines/apu2/acpi/routing.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl index 292347127e..0f8d8b1f7f 100644 --- a/src/mainboard/pcengines/apu2/acpi/si.asl +++ b/src/mainboard/pcengines/apu2/acpi/si.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl index 0734c8e3c8..19dd289560 100644 --- a/src/mainboard/pcengines/apu2/acpi/sleep.asl +++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl index 4ebb4b64a6..83cd750b4a 100644 --- a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index 20509e9d31..a40e86fe00 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout index fff7497289..7c63043519 100644 --- a/src/mainboard/pcengines/apu2/cmos.layout +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -2,7 +2,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 3bf0ed615b..9d6138a844 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index 170acca8d3..5242327354 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 49169be121..3acf2a8654 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c index 5f2045d8f4..8e6223792a 100644 --- a/src/mainboard/pcengines/apu2/irq_tables.c +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index bd2ca392f1..14ed39ffc9 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 772ee31734..36bd340fb0 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 27f0183787..7565bfca1d 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 443e1500cb..a8be385a79 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 524f30f3d8..f7593784f6 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index 5aa0748901..d481004a36 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index c819114be8..677b171e72 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2013 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index a89daa1309..03c6c32a29 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index 5d88549ab5..42e11523e4 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. -## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl index aecd174fc8..7bcd3cc08e 100644 --- a/src/mainboard/portwell/m107/acpi/superio.asl +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index 15c955afc2..f831352086 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/cmos.layout b/src/mainboard/portwell/m107/cmos.layout index c293c5f989..e809c23a59 100644 --- a/src/mainboard/portwell/m107/cmos.layout +++ b/src/mainboard/portwell/m107/cmos.layout @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corp. -## Copyright (C) 2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/com_init.c b/src/mainboard/portwell/m107/com_init.c index fc640dd236..e1ddc617af 100644 --- a/src/mainboard/portwell/m107/com_init.c +++ b/src/mainboard/portwell/m107/com_init.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl index 586a5e19ff..8fa1990e39 100644 --- a/src/mainboard/portwell/m107/dsdt.asl +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015-2018 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c index 544d24ba55..abc1bdd77e 100644 --- a/src/mainboard/portwell/m107/fadt.c +++ b/src/mainboard/portwell/m107/fadt.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/gpio.c b/src/mainboard/portwell/m107/gpio.c index 5a73ca9148..1cc07c5859 100644 --- a/src/mainboard/portwell/m107/gpio.c +++ b/src/mainboard/portwell/m107/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/hda_verb.c b/src/mainboard/portwell/m107/hda_verb.c index 868e5244da..0bdb74d186 100644 --- a/src/mainboard/portwell/m107/hda_verb.c +++ b/src/mainboard/portwell/m107/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/portwell/m107/irqroute.c b/src/mainboard/portwell/m107/irqroute.c index e5d1d62949..f0855adbc2 100644 --- a/src/mainboard/portwell/m107/irqroute.c +++ b/src/mainboard/portwell/m107/irqroute.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/irqroute.h b/src/mainboard/portwell/m107/irqroute.h index 6b7cb4169e..6e3a083087 100644 --- a/src/mainboard/portwell/m107/irqroute.h +++ b/src/mainboard/portwell/m107/irqroute.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/mainboard.c b/src/mainboard/portwell/m107/mainboard.c index d540c25246..0c929a2ecc 100644 --- a/src/mainboard/portwell/m107/mainboard.c +++ b/src/mainboard/portwell/m107/mainboard.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index 1307717b55..f383d60679 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c018620d3b..fa56b54d96 100644 --- a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Facebook, Inc. -# Copyright (C) 2019 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex index f18cbc2a87..410ca84659 100644 --- a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index 64faf1e163..ef862dab48 100644 --- a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2018-2019 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c index 2f131f4ec6..24d69dcee9 100644 --- a/src/mainboard/portwell/m107/w25q64.c +++ b/src/mainboard/portwell/m107/w25q64.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/Kconfig b/src/mainboard/purism/Kconfig index a3022d4591..93388e377a 100644 --- a/src/mainboard/purism/Kconfig +++ b/src/mainboard/purism/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/Makefile.inc b/src/mainboard/purism/librem_bdw/Makefile.inc index 13c0af4c8d..a03f360adc 100644 --- a/src/mainboard/purism/librem_bdw/Makefile.inc +++ b/src/mainboard/purism/librem_bdw/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/acpi/ec.asl b/src/mainboard/purism/librem_bdw/acpi/ec.asl index a660a526f4..2d23edc07e 100644 --- a/src/mainboard/purism/librem_bdw/acpi/ec.asl +++ b/src/mainboard/purism/librem_bdw/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl index 0e4842d1d8..1357de19f6 100644 --- a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/acpi/superio.asl b/src/mainboard/purism/librem_bdw/acpi/superio.asl index 92c272e4b6..606085fafe 100644 --- a/src/mainboard/purism/librem_bdw/acpi/superio.asl +++ b/src/mainboard/purism/librem_bdw/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 918398ec0b..5677e2e735 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 0e5d7a1fc6..f14a27f9a5 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index 533370161d..923b3c8e1c 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/gpio.c b/src/mainboard/purism/librem_bdw/gpio.c index 510299659e..d085702b78 100644 --- a/src/mainboard/purism/librem_bdw/gpio.c +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/hda_verb.c b/src/mainboard/purism/librem_bdw/hda_verb.c index 958a9391af..30c6769808 100644 --- a/src/mainboard/purism/librem_bdw/hda_verb.c +++ b/src/mainboard/purism/librem_bdw/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/mainboard.c b/src/mainboard/purism/librem_bdw/mainboard.c index 2ca559ab22..c5825f93b1 100644 --- a/src/mainboard/purism/librem_bdw/mainboard.c +++ b/src/mainboard/purism/librem_bdw/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 72b3fe25cd..00edc575bb 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c index e6b857d141..1aa0b29ff9 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c index 83de020cf8..7408a50d0a 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc index ad4fd525dc..31043ac4a6 100644 --- a/src/mainboard/purism/librem_skl/Makefile.inc +++ b/src/mainboard/purism/librem_skl/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/acpi/ec.asl b/src/mainboard/purism/librem_skl/acpi/ec.asl index c440ff87e4..dc42606cc3 100644 --- a/src/mainboard/purism/librem_skl/acpi/ec.asl +++ b/src/mainboard/purism/librem_skl/acpi/ec.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/acpi/mainboard.asl b/src/mainboard/purism/librem_skl/acpi/mainboard.asl index 0e4842d1d8..1357de19f6 100644 --- a/src/mainboard/purism/librem_skl/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_skl/acpi/mainboard.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/acpi/superio.asl b/src/mainboard/purism/librem_skl/acpi/superio.asl index 92c272e4b6..606085fafe 100644 --- a/src/mainboard/purism/librem_skl/acpi/superio.asl +++ b/src/mainboard/purism/librem_skl/acpi/superio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 0f78d5f7f1..57ed3ab81f 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/gpio.h b/src/mainboard/purism/librem_skl/gpio.h index e3328a3336..73917671d2 100644 --- a/src/mainboard/purism/librem_skl/gpio.h +++ b/src/mainboard/purism/librem_skl/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c index 812def67d2..33f471a169 100644 --- a/src/mainboard/purism/librem_skl/hda_verb.c +++ b/src/mainboard/purism/librem_skl/hda_verb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Purism SPC. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/purism/librem_skl/mainboard.c b/src/mainboard/purism/librem_skl/mainboard.c index 462b995ae0..2fa8e4c3ef 100644 --- a/src/mainboard/purism/librem_skl/mainboard.c +++ b/src/mainboard/purism/librem_skl/mainboard.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Purism SPC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/ramstage.c b/src/mainboard/purism/librem_skl/ramstage.c index 94f8071340..975951ecae 100644 --- a/src/mainboard/purism/librem_skl/ramstage.c +++ b/src/mainboard/purism/librem_skl/ramstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 42003738c3..56dc582cec 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Purism SPC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by From 1c6d8a9cf4f0b18cb816c7b95a2656e162ed39d7 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 12:51:24 +0100 Subject: [PATCH 0503/1463] soc: Remove copyright notices They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- src/soc/amd/common/acpi/gpio_bank_lib.asl | 1 - src/soc/amd/common/acpi/lpc.asl | 1 - src/soc/amd/common/block/acpi/acpi.c | 1 - src/soc/amd/common/block/acpimmio/mmio_util.c | 1 - src/soc/amd/common/block/alink/alink.c | 1 - src/soc/amd/common/block/cpu/car/ap_exit_car.S | 1 - src/soc/amd/common/block/cpu/car/cache_as_ram.S | 1 - src/soc/amd/common/block/cpu/car/exit_car.S | 1 - src/soc/amd/common/block/gpio_banks/gpio.c | 3 --- src/soc/amd/common/block/hda/hda.c | 1 - src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h | 2 -- src/soc/amd/common/block/include/amdblocks/acpi.h | 1 - src/soc/amd/common/block/include/amdblocks/acpimmio.h | 2 -- src/soc/amd/common/block/include/amdblocks/acpimmio_map.h | 2 -- src/soc/amd/common/block/include/amdblocks/agesawrapper.h | 1 - src/soc/amd/common/block/include/amdblocks/alink.h | 1 - src/soc/amd/common/block/include/amdblocks/amd_pci_util.h | 2 -- src/soc/amd/common/block/include/amdblocks/car.h | 1 - src/soc/amd/common/block/include/amdblocks/dimm_spd.h | 1 - src/soc/amd/common/block/include/amdblocks/gpio_banks.h | 1 - src/soc/amd/common/block/include/amdblocks/image.h | 1 - src/soc/amd/common/block/include/amdblocks/lpc.h | 1 - src/soc/amd/common/block/include/amdblocks/psp.h | 1 - src/soc/amd/common/block/include/amdblocks/reset.h | 1 - src/soc/amd/common/block/include/amdblocks/s3_resume.h | 1 - src/soc/amd/common/block/include/amdblocks/sata.h | 1 - src/soc/amd/common/block/iommu/iommu.c | 1 - src/soc/amd/common/block/lpc/lpc.c | 2 -- src/soc/amd/common/block/lpc/lpc_util.c | 1 - src/soc/amd/common/block/pci/amd_pci_util.c | 2 -- src/soc/amd/common/block/pi/agesawrapper.c | 2 -- src/soc/amd/common/block/pi/amd_late_init.c | 1 - src/soc/amd/common/block/pi/amd_resume_final.c | 1 - src/soc/amd/common/block/pi/def_callouts.c | 2 -- src/soc/amd/common/block/pi/image.c | 1 - src/soc/amd/common/block/pi/refcode_loader.c | 1 - src/soc/amd/common/block/psp/psp.c | 1 - src/soc/amd/common/block/s3/s3_resume.c | 2 -- src/soc/amd/common/block/sata/sata.c | 1 - src/soc/amd/common/block/smbus/sm.c | 1 - src/soc/amd/common/block/smbus/smbus.c | 1 - src/soc/amd/common/block/spi/fch_spi_ctrl.c | 1 - src/soc/amd/picasso/Kconfig | 1 - src/soc/amd/picasso/Makefile.inc | 3 --- src/soc/amd/picasso/acp.c | 1 - src/soc/amd/picasso/acpi.c | 2 -- src/soc/amd/picasso/acpi/acpi_wake_source.asl | 1 - src/soc/amd/picasso/acpi/cpu.asl | 1 - src/soc/amd/picasso/acpi/globalnvs.asl | 2 -- src/soc/amd/picasso/acpi/northbridge.asl | 2 -- src/soc/amd/picasso/acpi/pci_int.asl | 1 - src/soc/amd/picasso/acpi/pcie.asl | 1 - src/soc/amd/picasso/acpi/sb_fch.asl | 1 - src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 2 -- src/soc/amd/picasso/acpi/sleepstates.asl | 2 -- src/soc/amd/picasso/acpi/soc.asl | 1 - src/soc/amd/picasso/acpi/usb.asl | 1 - src/soc/amd/picasso/chip.c | 1 - src/soc/amd/picasso/chip.h | 1 - src/soc/amd/picasso/cpu.c | 2 -- src/soc/amd/picasso/finalize.c | 1 - src/soc/amd/picasso/gpio.c | 3 --- src/soc/amd/picasso/i2c.c | 1 - src/soc/amd/picasso/include/soc/acpi.h | 2 -- src/soc/amd/picasso/include/soc/amd_pci_int_defs.h | 2 -- src/soc/amd/picasso/include/soc/cpu.h | 1 - src/soc/amd/picasso/include/soc/gpio.h | 1 - src/soc/amd/picasso/include/soc/i2c.h | 1 - src/soc/amd/picasso/include/soc/iomap.h | 2 -- src/soc/amd/picasso/include/soc/northbridge.h | 2 -- src/soc/amd/picasso/include/soc/nvs.h | 2 -- src/soc/amd/picasso/include/soc/pci_devs.h | 1 - src/soc/amd/picasso/include/soc/romstage.h | 1 - src/soc/amd/picasso/include/soc/smi.h | 2 -- src/soc/amd/picasso/include/soc/southbridge.h | 2 -- src/soc/amd/picasso/mca.c | 1 - src/soc/amd/picasso/memmap.c | 1 - src/soc/amd/picasso/northbridge.c | 1 - src/soc/amd/picasso/pmutil.c | 1 - src/soc/amd/picasso/reset.c | 2 -- src/soc/amd/picasso/sata.c | 1 - src/soc/amd/picasso/smi.c | 1 - src/soc/amd/picasso/smi_util.c | 1 - src/soc/amd/picasso/smihandler.c | 2 -- src/soc/amd/picasso/southbridge.c | 1 - src/soc/amd/picasso/tsc_freq.c | 2 -- src/soc/amd/picasso/uart.c | 1 - src/soc/amd/picasso/usb.c | 1 - src/soc/amd/stoneyridge/BiosCallOuts.c | 3 --- src/soc/amd/stoneyridge/Kconfig | 1 - src/soc/amd/stoneyridge/Makefile.inc | 3 --- src/soc/amd/stoneyridge/acpi.c | 2 -- src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl | 1 - src/soc/amd/stoneyridge/acpi/cpu.asl | 1 - src/soc/amd/stoneyridge/acpi/globalnvs.asl | 2 -- src/soc/amd/stoneyridge/acpi/northbridge.asl | 2 -- src/soc/amd/stoneyridge/acpi/pci_int.asl | 1 - src/soc/amd/stoneyridge/acpi/pcie.asl | 1 - src/soc/amd/stoneyridge/acpi/sb_fch.asl | 1 - src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 2 -- src/soc/amd/stoneyridge/acpi/sleepstates.asl | 2 -- src/soc/amd/stoneyridge/acpi/soc.asl | 1 - src/soc/amd/stoneyridge/acpi/usb.asl | 1 - src/soc/amd/stoneyridge/bootblock/bootblock.c | 2 -- src/soc/amd/stoneyridge/chip.c | 1 - src/soc/amd/stoneyridge/chip.h | 1 - src/soc/amd/stoneyridge/cpu.c | 2 -- src/soc/amd/stoneyridge/enable_usbdebug.c | 1 - src/soc/amd/stoneyridge/finalize.c | 1 - src/soc/amd/stoneyridge/gpio.c | 3 --- src/soc/amd/stoneyridge/i2c.c | 1 - src/soc/amd/stoneyridge/include/soc/acpi.h | 2 -- src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h | 2 -- src/soc/amd/stoneyridge/include/soc/cpu.h | 1 - src/soc/amd/stoneyridge/include/soc/gpio.h | 1 - src/soc/amd/stoneyridge/include/soc/i2c.h | 1 - src/soc/amd/stoneyridge/include/soc/iomap.h | 2 -- src/soc/amd/stoneyridge/include/soc/northbridge.h | 2 -- src/soc/amd/stoneyridge/include/soc/nvs.h | 2 -- src/soc/amd/stoneyridge/include/soc/pci_devs.h | 1 - src/soc/amd/stoneyridge/include/soc/romstage.h | 1 - src/soc/amd/stoneyridge/include/soc/smi.h | 2 -- src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 -- src/soc/amd/stoneyridge/mca.c | 1 - src/soc/amd/stoneyridge/memmap.c | 1 - src/soc/amd/stoneyridge/monotonic_timer.c | 1 - src/soc/amd/stoneyridge/northbridge.c | 1 - src/soc/amd/stoneyridge/pmutil.c | 1 - src/soc/amd/stoneyridge/reset.c | 2 -- src/soc/amd/stoneyridge/romstage.c | 2 -- src/soc/amd/stoneyridge/sata.c | 1 - src/soc/amd/stoneyridge/smbus_spd.c | 1 - src/soc/amd/stoneyridge/smi.c | 1 - src/soc/amd/stoneyridge/smi_util.c | 1 - src/soc/amd/stoneyridge/smihandler.c | 2 -- src/soc/amd/stoneyridge/southbridge.c | 1 - src/soc/amd/stoneyridge/tsc_freq.c | 2 -- src/soc/amd/stoneyridge/uart.c | 1 - src/soc/amd/stoneyridge/usb.c | 1 - src/soc/cavium/cn81xx/Makefile.inc | 1 - src/soc/cavium/cn81xx/bl31_plat_params.c | 1 - src/soc/cavium/cn81xx/bootblock.c | 2 -- src/soc/cavium/cn81xx/bootblock_custom.S | 2 -- src/soc/cavium/cn81xx/cbmem.c | 2 -- src/soc/cavium/cn81xx/chip.h | 1 - src/soc/cavium/cn81xx/clock.c | 2 -- src/soc/cavium/cn81xx/cpu.c | 1 - src/soc/cavium/cn81xx/cpu_secondary.S | 2 -- src/soc/cavium/cn81xx/ecam0.c | 2 -- src/soc/cavium/cn81xx/gpio.c | 1 - src/soc/cavium/cn81xx/include/atf/plat_params.h | 1 - src/soc/cavium/cn81xx/include/soc/addressmap.h | 1 - src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h | 1 - src/soc/cavium/cn81xx/include/soc/clock.h | 2 -- src/soc/cavium/cn81xx/include/soc/cpu.h | 2 -- src/soc/cavium/cn81xx/include/soc/ecam0.h | 1 - src/soc/cavium/cn81xx/include/soc/gpio.h | 2 -- src/soc/cavium/cn81xx/include/soc/memlayout.ld | 2 -- src/soc/cavium/cn81xx/include/soc/mmu.h | 1 - src/soc/cavium/cn81xx/include/soc/sdram.h | 2 -- src/soc/cavium/cn81xx/include/soc/soc.h | 1 - src/soc/cavium/cn81xx/include/soc/spi.h | 1 - src/soc/cavium/cn81xx/include/soc/timer.h | 1 - src/soc/cavium/cn81xx/include/soc/twsi.h | 1 - src/soc/cavium/cn81xx/include/soc/uart.h | 1 - src/soc/cavium/cn81xx/mmu.c | 2 -- src/soc/cavium/cn81xx/sdram.c | 3 --- src/soc/cavium/cn81xx/soc.c | 2 -- src/soc/cavium/cn81xx/spi.c | 2 -- src/soc/cavium/cn81xx/timer.c | 2 -- src/soc/cavium/cn81xx/twsi.c | 2 -- src/soc/cavium/cn81xx/uart.c | 2 -- src/soc/cavium/common/Makefile.inc | 1 - src/soc/cavium/common/bdk-coreboot.c | 2 -- src/soc/cavium/common/bootblock.c | 1 - src/soc/cavium/common/ecam.c | 3 --- src/soc/cavium/common/include/soc/bootblock.h | 1 - src/soc/cavium/common/include/soc/ecam.h | 2 -- src/soc/cavium/common/include/soc/sysreg.h | 2 -- src/soc/cavium/common/pci/chip.h | 1 - src/soc/cavium/common/pci/uart.c | 1 - src/soc/intel/apollolake/acpi.c | 3 --- src/soc/intel/apollolake/acpi/dptf.asl | 1 - src/soc/intel/apollolake/acpi/globalnvs.asl | 2 -- src/soc/intel/apollolake/acpi/gpio.asl | 2 -- src/soc/intel/apollolake/acpi/gpiolib.asl | 1 - src/soc/intel/apollolake/acpi/lpss.asl | 2 -- src/soc/intel/apollolake/acpi/northbridge.asl | 2 -- src/soc/intel/apollolake/acpi/pch_hda.asl | 2 -- src/soc/intel/apollolake/acpi/pci_irqs.asl | 2 -- src/soc/intel/apollolake/acpi/pcie.asl | 1 - src/soc/intel/apollolake/acpi/pcie_port.asl | 1 - src/soc/intel/apollolake/acpi/platform.asl | 3 --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 1 - src/soc/intel/apollolake/acpi/scs.asl | 1 - src/soc/intel/apollolake/acpi/soc_int.asl | 2 -- src/soc/intel/apollolake/acpi/southbridge.asl | 2 -- src/soc/intel/apollolake/acpi/xhci.asl | 1 - src/soc/intel/apollolake/acpi/xhci_apl_ports.asl | 2 -- src/soc/intel/apollolake/acpi/xhci_glk_ports.asl | 2 -- src/soc/intel/apollolake/bootblock/bootblock.c | 2 -- src/soc/intel/apollolake/car.c | 2 -- src/soc/intel/apollolake/chip.c | 4 ---- src/soc/intel/apollolake/chip.h | 3 --- src/soc/intel/apollolake/cpu.c | 4 ---- src/soc/intel/apollolake/cse.c | 1 - src/soc/intel/apollolake/elog.c | 2 -- src/soc/intel/apollolake/fspcar.c | 1 - src/soc/intel/apollolake/gpio_apl.c | 2 -- src/soc/intel/apollolake/gpio_glk.c | 2 -- src/soc/intel/apollolake/graphics.c | 2 -- src/soc/intel/apollolake/gspi.c | 1 - src/soc/intel/apollolake/heci.c | 1 - src/soc/intel/apollolake/i2c.c | 2 -- src/soc/intel/apollolake/include/soc/cpu.h | 2 -- src/soc/intel/apollolake/include/soc/gpe.h | 1 - src/soc/intel/apollolake/include/soc/gpio.h | 1 - src/soc/intel/apollolake/include/soc/gpio_apl.h | 2 -- src/soc/intel/apollolake/include/soc/gpio_glk.h | 1 - src/soc/intel/apollolake/include/soc/heci.h | 1 - src/soc/intel/apollolake/include/soc/iomap.h | 2 -- src/soc/intel/apollolake/include/soc/itss.h | 1 - src/soc/intel/apollolake/include/soc/me.h | 1 - src/soc/intel/apollolake/include/soc/meminit.h | 1 - src/soc/intel/apollolake/include/soc/nhlt.h | 1 - src/soc/intel/apollolake/include/soc/nvs.h | 2 -- src/soc/intel/apollolake/include/soc/p2sb.h | 1 - src/soc/intel/apollolake/include/soc/pcr_ids.h | 2 -- src/soc/intel/apollolake/include/soc/pm.h | 2 -- src/soc/intel/apollolake/include/soc/pnpconfig.h | 1 - src/soc/intel/apollolake/include/soc/ramstage.h | 3 --- src/soc/intel/apollolake/include/soc/romstage.h | 2 -- src/soc/intel/apollolake/include/soc/smbus.h | 1 - src/soc/intel/apollolake/include/soc/soc_chip.h | 1 - src/soc/intel/apollolake/include/soc/systemagent.h | 3 --- src/soc/intel/apollolake/include/soc/usb.h | 2 -- src/soc/intel/apollolake/lpc.c | 1 - src/soc/intel/apollolake/meminit.c | 1 - src/soc/intel/apollolake/meminit_util_apl.c | 1 - src/soc/intel/apollolake/meminit_util_glk.c | 1 - src/soc/intel/apollolake/mmap_boot.c | 3 --- src/soc/intel/apollolake/nhlt.c | 1 - src/soc/intel/apollolake/pdpt.c | 1 - src/soc/intel/apollolake/pmc.c | 2 -- src/soc/intel/apollolake/pmutil.c | 2 -- src/soc/intel/apollolake/pnpconfig.c | 1 - src/soc/intel/apollolake/pt.c | 1 - src/soc/intel/apollolake/report_platform.c | 1 - src/soc/intel/apollolake/reset.c | 1 - src/soc/intel/apollolake/romstage.c | 3 --- src/soc/intel/apollolake/sd.c | 1 - src/soc/intel/apollolake/smihandler.c | 2 -- src/soc/intel/apollolake/spi.c | 2 -- src/soc/intel/apollolake/systemagent.c | 4 ---- src/soc/intel/apollolake/uart.c | 1 - src/soc/intel/apollolake/xdci.c | 1 - src/soc/intel/apollolake/xhci.c | 1 - src/soc/intel/baytrail/acpi.c | 2 -- src/soc/intel/baytrail/acpi/device_nvs.asl | 1 - src/soc/intel/baytrail/acpi/globalnvs.asl | 1 - src/soc/intel/baytrail/acpi/gpio.asl | 1 - src/soc/intel/baytrail/acpi/irq_helper.h | 1 - src/soc/intel/baytrail/acpi/irqlinks.asl | 1 - src/soc/intel/baytrail/acpi/irqroute.asl | 2 -- src/soc/intel/baytrail/acpi/lpc.asl | 2 -- src/soc/intel/baytrail/acpi/lpe.asl | 1 - src/soc/intel/baytrail/acpi/lpss.asl | 1 - src/soc/intel/baytrail/acpi/pcie.asl | 2 -- src/soc/intel/baytrail/acpi/platform.asl | 2 -- src/soc/intel/baytrail/acpi/scc.asl | 1 - src/soc/intel/baytrail/acpi/southcluster.asl | 1 - src/soc/intel/baytrail/acpi/xhci.asl | 1 - src/soc/intel/baytrail/bootblock/bootblock.c | 1 - src/soc/intel/baytrail/chip.c | 1 - src/soc/intel/baytrail/chip.h | 1 - src/soc/intel/baytrail/cpu.c | 1 - src/soc/intel/baytrail/dptf.c | 1 - src/soc/intel/baytrail/ehci.c | 1 - src/soc/intel/baytrail/elog.c | 1 - src/soc/intel/baytrail/emmc.c | 1 - src/soc/intel/baytrail/gfx.c | 1 - src/soc/intel/baytrail/gpio.c | 1 - src/soc/intel/baytrail/hda.c | 1 - src/soc/intel/baytrail/include/soc/acpi.h | 1 - src/soc/intel/baytrail/include/soc/device_nvs.h | 1 - src/soc/intel/baytrail/include/soc/efi_wrapper.h | 1 - src/soc/intel/baytrail/include/soc/ehci.h | 1 - src/soc/intel/baytrail/include/soc/gfx.h | 1 - src/soc/intel/baytrail/include/soc/gpio.h | 1 - src/soc/intel/baytrail/include/soc/iomap.h | 1 - src/soc/intel/baytrail/include/soc/iosf.h | 1 - src/soc/intel/baytrail/include/soc/irq.h | 1 - src/soc/intel/baytrail/include/soc/lpc.h | 1 - src/soc/intel/baytrail/include/soc/mrc_wrapper.h | 1 - src/soc/intel/baytrail/include/soc/msr.h | 1 - src/soc/intel/baytrail/include/soc/nvs.h | 2 -- src/soc/intel/baytrail/include/soc/pattrs.h | 1 - src/soc/intel/baytrail/include/soc/pci_devs.h | 1 - src/soc/intel/baytrail/include/soc/pcie.h | 1 - src/soc/intel/baytrail/include/soc/pmc.h | 1 - src/soc/intel/baytrail/include/soc/ramstage.h | 1 - src/soc/intel/baytrail/include/soc/romstage.h | 1 - src/soc/intel/baytrail/include/soc/sata.h | 1 - src/soc/intel/baytrail/include/soc/smm.h | 1 - src/soc/intel/baytrail/include/soc/spi.h | 1 - src/soc/intel/baytrail/include/soc/xhci.h | 1 - src/soc/intel/baytrail/iosf.c | 1 - src/soc/intel/baytrail/lpe.c | 1 - src/soc/intel/baytrail/lpss.c | 1 - src/soc/intel/baytrail/memmap.c | 1 - src/soc/intel/baytrail/northcluster.c | 1 - src/soc/intel/baytrail/pcie.c | 1 - src/soc/intel/baytrail/perf_power.c | 1 - src/soc/intel/baytrail/pmutil.c | 1 - src/soc/intel/baytrail/ramstage.c | 1 - src/soc/intel/baytrail/refcode.c | 1 - src/soc/intel/baytrail/romstage/gfx.c | 1 - src/soc/intel/baytrail/romstage/pmc.c | 1 - src/soc/intel/baytrail/romstage/raminit.c | 1 - src/soc/intel/baytrail/romstage/romstage.c | 1 - src/soc/intel/baytrail/sata.c | 1 - src/soc/intel/baytrail/scc.c | 1 - src/soc/intel/baytrail/sd.c | 1 - src/soc/intel/baytrail/smihandler.c | 1 - src/soc/intel/baytrail/smm.c | 1 - src/soc/intel/baytrail/southcluster.c | 3 --- src/soc/intel/baytrail/tsc_freq.c | 1 - src/soc/intel/baytrail/xhci.c | 1 - src/soc/intel/braswell/acpi.c | 4 ---- src/soc/intel/braswell/acpi/device_nvs.asl | 1 - src/soc/intel/braswell/acpi/dptf/cpu.asl | 1 - src/soc/intel/braswell/acpi/dptf/thermal.asl | 1 - src/soc/intel/braswell/acpi/globalnvs.asl | 1 - src/soc/intel/braswell/acpi/gpio.asl | 1 - src/soc/intel/braswell/acpi/irq_helper.h | 1 - src/soc/intel/braswell/acpi/irqlinks.asl | 2 -- src/soc/intel/braswell/acpi/irqroute.asl | 2 -- src/soc/intel/braswell/acpi/lpc.asl | 3 --- src/soc/intel/braswell/acpi/lpe.asl | 1 - src/soc/intel/braswell/acpi/lpss.asl | 2 -- src/soc/intel/braswell/acpi/platform.asl | 2 -- src/soc/intel/braswell/acpi/scc.asl | 1 - src/soc/intel/braswell/acpi/southcluster.asl | 1 - src/soc/intel/braswell/acpi/xhci.asl | 1 - src/soc/intel/braswell/bootblock/bootblock.c | 3 --- src/soc/intel/braswell/chip.c | 2 -- src/soc/intel/braswell/chip.h | 3 --- src/soc/intel/braswell/cpu.c | 3 --- src/soc/intel/braswell/elog.c | 2 -- src/soc/intel/braswell/emmc.c | 2 -- src/soc/intel/braswell/gfx.c | 2 -- src/soc/intel/braswell/gpio.c | 2 -- src/soc/intel/braswell/gpio_support.c | 1 - src/soc/intel/braswell/include/soc/acpi.h | 2 -- src/soc/intel/braswell/include/soc/device_nvs.h | 3 --- src/soc/intel/braswell/include/soc/ehci.h | 2 -- src/soc/intel/braswell/include/soc/gfx.h | 2 -- src/soc/intel/braswell/include/soc/gpio.h | 2 -- src/soc/intel/braswell/include/soc/gpio_defs.h | 2 -- src/soc/intel/braswell/include/soc/hda.h | 2 -- src/soc/intel/braswell/include/soc/iomap.h | 3 --- src/soc/intel/braswell/include/soc/iosf.h | 2 -- src/soc/intel/braswell/include/soc/irq.h | 3 --- src/soc/intel/braswell/include/soc/lpc.h | 3 --- src/soc/intel/braswell/include/soc/msr.h | 2 -- src/soc/intel/braswell/include/soc/nvs.h | 3 --- src/soc/intel/braswell/include/soc/pattrs.h | 2 -- src/soc/intel/braswell/include/soc/pci_devs.h | 3 --- src/soc/intel/braswell/include/soc/pcie.h | 2 -- src/soc/intel/braswell/include/soc/pm.h | 2 -- src/soc/intel/braswell/include/soc/ramstage.h | 2 -- src/soc/intel/braswell/include/soc/romstage.h | 2 -- src/soc/intel/braswell/include/soc/sata.h | 2 -- src/soc/intel/braswell/include/soc/smbus.h | 3 --- src/soc/intel/braswell/include/soc/smm.h | 2 -- src/soc/intel/braswell/include/soc/spi.h | 3 --- src/soc/intel/braswell/include/soc/xhci.h | 2 -- src/soc/intel/braswell/iosf.c | 2 -- src/soc/intel/braswell/lpc_init.c | 1 - src/soc/intel/braswell/lpe.c | 2 -- src/soc/intel/braswell/lpss.c | 2 -- src/soc/intel/braswell/memmap.c | 2 -- src/soc/intel/braswell/northcluster.c | 3 --- src/soc/intel/braswell/pcie.c | 2 -- src/soc/intel/braswell/placeholders.c | 1 - src/soc/intel/braswell/pmutil.c | 2 -- src/soc/intel/braswell/ramstage.c | 3 --- src/soc/intel/braswell/romstage/romstage.c | 3 --- src/soc/intel/braswell/sata.c | 2 -- src/soc/intel/braswell/scc.c | 2 -- src/soc/intel/braswell/sd.c | 2 -- src/soc/intel/braswell/smbus.c | 3 --- src/soc/intel/braswell/smihandler.c | 2 -- src/soc/intel/braswell/smm.c | 2 -- src/soc/intel/braswell/southcluster.c | 4 ---- src/soc/intel/braswell/tsc_freq.c | 2 -- src/soc/intel/braswell/xhci.c | 2 -- src/soc/intel/broadwell/acpi.c | 2 -- src/soc/intel/broadwell/acpi/adsp.asl | 1 - src/soc/intel/broadwell/acpi/ctdp.asl | 1 - src/soc/intel/broadwell/acpi/device_nvs.asl | 1 - src/soc/intel/broadwell/acpi/ehci.asl | 1 - src/soc/intel/broadwell/acpi/globalnvs.asl | 2 -- src/soc/intel/broadwell/acpi/gpio.asl | 1 - src/soc/intel/broadwell/acpi/hda.asl | 2 -- src/soc/intel/broadwell/acpi/irqlinks.asl | 2 -- src/soc/intel/broadwell/acpi/lpc.asl | 2 -- src/soc/intel/broadwell/acpi/pch.asl | 2 -- src/soc/intel/broadwell/acpi/pci_irqs.asl | 2 -- src/soc/intel/broadwell/acpi/pcie.asl | 2 -- src/soc/intel/broadwell/acpi/pcie_port.asl | 1 - src/soc/intel/broadwell/acpi/platform.asl | 2 -- src/soc/intel/broadwell/acpi/sata.asl | 2 -- src/soc/intel/broadwell/acpi/serialio.asl | 1 - src/soc/intel/broadwell/acpi/smbus.asl | 2 -- src/soc/intel/broadwell/acpi/systemagent.asl | 2 -- src/soc/intel/broadwell/acpi/xhci.asl | 2 -- src/soc/intel/broadwell/adsp.c | 1 - src/soc/intel/broadwell/bootblock/cpu.c | 1 - src/soc/intel/broadwell/bootblock/pch.c | 1 - src/soc/intel/broadwell/bootblock/systemagent.c | 1 - src/soc/intel/broadwell/chip.c | 1 - src/soc/intel/broadwell/chip.h | 2 -- src/soc/intel/broadwell/cpu.c | 2 -- src/soc/intel/broadwell/cpu_info.c | 2 -- src/soc/intel/broadwell/ehci.c | 2 -- src/soc/intel/broadwell/elog.c | 1 - src/soc/intel/broadwell/finalize.c | 1 - src/soc/intel/broadwell/gpio.c | 1 - src/soc/intel/broadwell/hda.c | 3 --- src/soc/intel/broadwell/igd.c | 1 - src/soc/intel/broadwell/include/soc/acpi.h | 1 - src/soc/intel/broadwell/include/soc/adsp.h | 1 - src/soc/intel/broadwell/include/soc/cpu.h | 1 - src/soc/intel/broadwell/include/soc/device_nvs.h | 1 - src/soc/intel/broadwell/include/soc/ehci.h | 1 - src/soc/intel/broadwell/include/soc/gpio.h | 1 - src/soc/intel/broadwell/include/soc/iobp.h | 1 - src/soc/intel/broadwell/include/soc/iomap.h | 1 - src/soc/intel/broadwell/include/soc/lpc.h | 1 - src/soc/intel/broadwell/include/soc/me.h | 1 - src/soc/intel/broadwell/include/soc/msr.h | 1 - src/soc/intel/broadwell/include/soc/nvs.h | 2 -- src/soc/intel/broadwell/include/soc/pch.h | 2 -- src/soc/intel/broadwell/include/soc/pci_devs.h | 1 - src/soc/intel/broadwell/include/soc/pei_data.h | 1 - src/soc/intel/broadwell/include/soc/pei_wrapper.h | 1 - src/soc/intel/broadwell/include/soc/pm.h | 1 - src/soc/intel/broadwell/include/soc/ramstage.h | 1 - src/soc/intel/broadwell/include/soc/rcba.h | 1 - src/soc/intel/broadwell/include/soc/romstage.h | 1 - src/soc/intel/broadwell/include/soc/sata.h | 1 - src/soc/intel/broadwell/include/soc/serialio.h | 1 - src/soc/intel/broadwell/include/soc/smbus.h | 3 --- src/soc/intel/broadwell/include/soc/spi.h | 1 - src/soc/intel/broadwell/include/soc/systemagent.h | 2 -- src/soc/intel/broadwell/include/soc/xhci.h | 1 - src/soc/intel/broadwell/iobp.c | 1 - src/soc/intel/broadwell/lpc.c | 2 -- src/soc/intel/broadwell/me.c | 1 - src/soc/intel/broadwell/me_status.c | 1 - src/soc/intel/broadwell/memmap.c | 1 - src/soc/intel/broadwell/minihd.c | 3 --- src/soc/intel/broadwell/pch.c | 2 -- src/soc/intel/broadwell/pcie.c | 2 -- src/soc/intel/broadwell/pei_data.c | 1 - src/soc/intel/broadwell/pmutil.c | 1 - src/soc/intel/broadwell/ramstage.c | 1 - src/soc/intel/broadwell/refcode.c | 1 - src/soc/intel/broadwell/romstage/cpu.c | 1 - src/soc/intel/broadwell/romstage/pch.c | 1 - src/soc/intel/broadwell/romstage/power_state.c | 1 - src/soc/intel/broadwell/romstage/raminit.c | 1 - src/soc/intel/broadwell/romstage/report_platform.c | 1 - src/soc/intel/broadwell/romstage/romstage.c | 1 - src/soc/intel/broadwell/romstage/smbus.c | 2 -- src/soc/intel/broadwell/romstage/systemagent.c | 2 -- src/soc/intel/broadwell/romstage/uart.c | 1 - src/soc/intel/broadwell/sata.c | 2 -- src/soc/intel/broadwell/serialio.c | 1 - src/soc/intel/broadwell/smbus.c | 2 -- src/soc/intel/broadwell/smi.c | 2 -- src/soc/intel/broadwell/smihandler.c | 2 -- src/soc/intel/broadwell/smmrelocate.c | 1 - src/soc/intel/broadwell/systemagent.c | 2 -- src/soc/intel/broadwell/tsc_freq.c | 1 - src/soc/intel/broadwell/usb_debug.c | 1 - src/soc/intel/broadwell/xhci.c | 1 - src/soc/intel/cannonlake/acpi.c | 3 --- src/soc/intel/cannonlake/acpi/dptf.asl | 1 - src/soc/intel/cannonlake/acpi/gfx.asl | 1 - src/soc/intel/cannonlake/acpi/gpio.asl | 2 -- src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl | 1 - src/soc/intel/cannonlake/acpi/gpio_op.asl | 1 - src/soc/intel/cannonlake/acpi/ish.asl | 1 - src/soc/intel/cannonlake/acpi/lpit.asl | 1 - src/soc/intel/cannonlake/acpi/pch_glan.asl | 3 --- src/soc/intel/cannonlake/acpi/pch_hda.asl | 2 -- src/soc/intel/cannonlake/acpi/pci_irqs.asl | 2 -- src/soc/intel/cannonlake/acpi/pcie.asl | 1 - src/soc/intel/cannonlake/acpi/platform.asl | 3 --- src/soc/intel/cannonlake/acpi/scs.asl | 1 - src/soc/intel/cannonlake/acpi/serialio.asl | 2 -- src/soc/intel/cannonlake/acpi/smbus.asl | 3 --- src/soc/intel/cannonlake/acpi/southbridge.asl | 2 -- src/soc/intel/cannonlake/acpi/xhci.asl | 3 --- src/soc/intel/cannonlake/bootblock/bootblock.c | 1 - src/soc/intel/cannonlake/bootblock/cpu.c | 2 -- src/soc/intel/cannonlake/bootblock/pch.c | 2 -- src/soc/intel/cannonlake/bootblock/report_platform.c | 2 -- src/soc/intel/cannonlake/chip.c | 1 - src/soc/intel/cannonlake/chip.h | 3 --- src/soc/intel/cannonlake/cnl_memcfg_init.c | 1 - src/soc/intel/cannonlake/cpu.c | 1 - src/soc/intel/cannonlake/elog.c | 2 -- src/soc/intel/cannonlake/finalize.c | 2 -- src/soc/intel/cannonlake/fsp_params.c | 1 - src/soc/intel/cannonlake/gpio.c | 1 - src/soc/intel/cannonlake/gpio_cnp_h.c | 1 - src/soc/intel/cannonlake/gpio_common.c | 1 - src/soc/intel/cannonlake/graphics.c | 1 - src/soc/intel/cannonlake/gspi.c | 1 - src/soc/intel/cannonlake/i2c.c | 2 -- src/soc/intel/cannonlake/include/soc/bootblock.h | 1 - src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h | 1 - src/soc/intel/cannonlake/include/soc/cpu.h | 2 -- src/soc/intel/cannonlake/include/soc/gpe.h | 1 - src/soc/intel/cannonlake/include/soc/gpio.h | 1 - src/soc/intel/cannonlake/include/soc/gpio_common.h | 1 - src/soc/intel/cannonlake/include/soc/gpio_defs.h | 1 - src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h | 1 - src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h | 2 -- .../intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h | 1 - src/soc/intel/cannonlake/include/soc/iomap.h | 2 -- src/soc/intel/cannonlake/include/soc/irq.h | 2 -- src/soc/intel/cannonlake/include/soc/itss.h | 1 - src/soc/intel/cannonlake/include/soc/lpc.h | 2 -- src/soc/intel/cannonlake/include/soc/me.h | 1 - src/soc/intel/cannonlake/include/soc/msr.h | 2 -- src/soc/intel/cannonlake/include/soc/nhlt.h | 1 - src/soc/intel/cannonlake/include/soc/nvs.h | 3 --- src/soc/intel/cannonlake/include/soc/p2sb.h | 1 - src/soc/intel/cannonlake/include/soc/pch.h | 3 --- src/soc/intel/cannonlake/include/soc/pci_devs.h | 2 -- src/soc/intel/cannonlake/include/soc/pcr_ids.h | 1 - src/soc/intel/cannonlake/include/soc/pm.h | 2 -- src/soc/intel/cannonlake/include/soc/pmc.h | 2 -- src/soc/intel/cannonlake/include/soc/ramstage.h | 2 -- src/soc/intel/cannonlake/include/soc/romstage.h | 2 -- src/soc/intel/cannonlake/include/soc/sata.h | 1 - src/soc/intel/cannonlake/include/soc/serialio.h | 2 -- src/soc/intel/cannonlake/include/soc/smbus.h | 4 ---- src/soc/intel/cannonlake/include/soc/soc_chip.h | 1 - src/soc/intel/cannonlake/include/soc/systemagent.h | 3 --- src/soc/intel/cannonlake/include/soc/usb.h | 1 - src/soc/intel/cannonlake/include/soc/vr_config.h | 1 - src/soc/intel/cannonlake/lockdown.c | 1 - src/soc/intel/cannonlake/lpc.c | 3 --- src/soc/intel/cannonlake/me.c | 1 - src/soc/intel/cannonlake/nhlt.c | 1 - src/soc/intel/cannonlake/p2sb.c | 1 - src/soc/intel/cannonlake/pmc.c | 3 --- src/soc/intel/cannonlake/pmutil.c | 2 -- src/soc/intel/cannonlake/reset.c | 1 - src/soc/intel/cannonlake/romstage/Makefile.inc | 1 - src/soc/intel/cannonlake/romstage/fsp_params.c | 1 - src/soc/intel/cannonlake/romstage/pch.c | 1 - src/soc/intel/cannonlake/romstage/romstage.c | 1 - src/soc/intel/cannonlake/romstage/systemagent.c | 3 --- src/soc/intel/cannonlake/sd.c | 1 - src/soc/intel/cannonlake/smihandler.c | 3 --- src/soc/intel/cannonlake/smmrelocate.c | 2 -- src/soc/intel/cannonlake/spi.c | 2 -- src/soc/intel/cannonlake/systemagent.c | 3 --- src/soc/intel/cannonlake/uart.c | 1 - src/soc/intel/cannonlake/vr_config.c | 1 - src/soc/intel/cannonlake/xhci.c | 1 - src/soc/intel/common/acpi/acpi_debug.asl | 1 - src/soc/intel/common/acpi/acpi_wake_source.asl | 1 - src/soc/intel/common/acpi/dptf/charger.asl | 2 -- src/soc/intel/common/acpi/dptf/cpu.asl | 2 -- src/soc/intel/common/acpi/dptf/dptf.asl | 2 -- src/soc/intel/common/acpi/dptf/fan.asl | 1 - src/soc/intel/common/acpi/dptf/thermal.asl | 2 -- src/soc/intel/common/acpi/pci_osc.asl | 1 - src/soc/intel/common/acpi/pcr.asl | 2 -- src/soc/intel/common/acpi/platform.asl | 3 --- src/soc/intel/common/acpi/sgx.asl | 1 - src/soc/intel/common/acpi/wifi.asl | 3 --- src/soc/intel/common/acpi_wake_source.c | 1 - src/soc/intel/common/block/acpi/acpi.c | 1 - src/soc/intel/common/block/acpi/acpi/globalnvs.asl | 1 - src/soc/intel/common/block/acpi/acpi/ipu.asl | 1 - src/soc/intel/common/block/acpi/acpi/lpc.asl | 3 --- src/soc/intel/common/block/acpi/acpi/northbridge.asl | 1 - src/soc/intel/common/block/chip/chip.c | 1 - src/soc/intel/common/block/cpu/car/cache_as_ram.S | 1 - src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 1 - src/soc/intel/common/block/cpu/car/exit_car.S | 1 - src/soc/intel/common/block/cpu/car/exit_car_fsp.S | 1 - src/soc/intel/common/block/cpu/cpulib.c | 3 --- src/soc/intel/common/block/cpu/mp_init.c | 1 - src/soc/intel/common/block/cse/cse.c | 1 - src/soc/intel/common/block/cse/disable_heci.c | 1 - src/soc/intel/common/block/dsp/dsp.c | 2 -- src/soc/intel/common/block/fast_spi/fast_spi.c | 1 - src/soc/intel/common/block/fast_spi/fast_spi_def.h | 1 - src/soc/intel/common/block/fast_spi/fast_spi_flash.c | 1 - src/soc/intel/common/block/gpio/gpio.c | 1 - src/soc/intel/common/block/graphics/graphics.c | 1 - src/soc/intel/common/block/gspi/gspi.c | 1 - src/soc/intel/common/block/hda/hda.c | 2 -- src/soc/intel/common/block/i2c/i2c.c | 1 - src/soc/intel/common/block/imc/imc.c | 1 - src/soc/intel/common/block/include/intelblocks/acpi.h | 2 -- src/soc/intel/common/block/include/intelblocks/cfg.h | 1 - src/soc/intel/common/block/include/intelblocks/cpulib.h | 2 -- src/soc/intel/common/block/include/intelblocks/cse.h | 1 - src/soc/intel/common/block/include/intelblocks/fast_spi.h | 1 - src/soc/intel/common/block/include/intelblocks/gpio.h | 1 - .../intel/common/block/include/intelblocks/gpio_defs.h | 1 - src/soc/intel/common/block/include/intelblocks/graphics.h | 1 - src/soc/intel/common/block/include/intelblocks/gspi.h | 1 - src/soc/intel/common/block/include/intelblocks/imc.h | 1 - src/soc/intel/common/block/include/intelblocks/itss.h | 1 - src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 2 -- src/soc/intel/common/block/include/intelblocks/lpss.h | 1 - src/soc/intel/common/block/include/intelblocks/mmc.h | 1 - src/soc/intel/common/block/include/intelblocks/mp_init.h | 1 - src/soc/intel/common/block/include/intelblocks/msr.h | 1 - src/soc/intel/common/block/include/intelblocks/nvs.h | 1 - src/soc/intel/common/block/include/intelblocks/p2sb.h | 2 -- src/soc/intel/common/block/include/intelblocks/pcr.h | 1 - src/soc/intel/common/block/include/intelblocks/pmc.h | 1 - src/soc/intel/common/block/include/intelblocks/pmclib.h | 1 - src/soc/intel/common/block/include/intelblocks/rtc.h | 1 - src/soc/intel/common/block/include/intelblocks/sd.h | 1 - src/soc/intel/common/block/include/intelblocks/sgx.h | 1 - src/soc/intel/common/block/include/intelblocks/smbus.h | 1 - .../intel/common/block/include/intelblocks/smihandler.h | 1 - src/soc/intel/common/block/include/intelblocks/spi.h | 1 - src/soc/intel/common/block/include/intelblocks/sram.h | 1 - .../intel/common/block/include/intelblocks/systemagent.h | 1 - src/soc/intel/common/block/include/intelblocks/tco.h | 1 - src/soc/intel/common/block/include/intelblocks/thermal.h | 1 - src/soc/intel/common/block/include/intelblocks/uart.h | 1 - src/soc/intel/common/block/include/intelblocks/xdci.h | 1 - src/soc/intel/common/block/include/intelblocks/xhci.h | 1 - src/soc/intel/common/block/itss/itss.c | 2 -- src/soc/intel/common/block/lpc/lpc.c | 1 - src/soc/intel/common/block/lpc/lpc_def.h | 1 - src/soc/intel/common/block/lpc/lpc_lib.c | 2 -- src/soc/intel/common/block/lpss/lpss.c | 1 - src/soc/intel/common/block/p2sb/p2sb.c | 2 -- src/soc/intel/common/block/pcie/pcie.c | 1 - src/soc/intel/common/block/pcie/pcie_rp.c | 1 - src/soc/intel/common/block/pcr/pcr.c | 1 - src/soc/intel/common/block/pmc/pmc.c | 1 - src/soc/intel/common/block/pmc/pmclib.c | 1 - src/soc/intel/common/block/rtc/rtc.c | 1 - src/soc/intel/common/block/sata/sata.c | 1 - src/soc/intel/common/block/scs/early_mmc.c | 1 - src/soc/intel/common/block/scs/mmc.c | 1 - src/soc/intel/common/block/scs/sd.c | 2 -- src/soc/intel/common/block/sgx/sgx.c | 1 - src/soc/intel/common/block/smbus/smbus.c | 1 - src/soc/intel/common/block/smbus/smbus_early.c | 1 - src/soc/intel/common/block/smbus/smbuslib.c | 1 - src/soc/intel/common/block/smbus/smbuslib.h | 1 - src/soc/intel/common/block/smbus/tco.c | 1 - src/soc/intel/common/block/smm/smihandler.c | 2 -- src/soc/intel/common/block/smm/smitraphandler.c | 2 -- src/soc/intel/common/block/smm/smm.c | 3 --- src/soc/intel/common/block/spi/spi.c | 1 - src/soc/intel/common/block/sram/sram.c | 1 - src/soc/intel/common/block/systemagent/memmap.c | 2 -- src/soc/intel/common/block/systemagent/systemagent.c | 2 -- src/soc/intel/common/block/systemagent/systemagent_def.h | 1 - .../intel/common/block/systemagent/systemagent_early.c | 1 - src/soc/intel/common/block/thermal/thermal.c | 1 - src/soc/intel/common/block/timer/timer.c | 1 - src/soc/intel/common/block/uart/uart.c | 1 - src/soc/intel/common/block/xdci/xdci.c | 2 -- src/soc/intel/common/block/xhci/elog.c | 1 - src/soc/intel/common/block/xhci/xhci.c | 2 -- src/soc/intel/common/hda_verb.c | 3 --- src/soc/intel/common/hda_verb.h | 1 - src/soc/intel/common/mma.c | 1 - src/soc/intel/common/mma.h | 1 - src/soc/intel/common/nhlt.c | 1 - src/soc/intel/common/pch/include/intelpch/lockdown.h | 1 - src/soc/intel/common/pch/lockdown/lockdown.c | 1 - src/soc/intel/common/reset.c | 1 - src/soc/intel/common/smbios.c | 1 - src/soc/intel/common/smbios.h | 1 - src/soc/intel/common/tpm_tis.c | 1 - src/soc/intel/common/vbt.c | 1 - src/soc/intel/common/vbt.h | 1 - src/soc/intel/denverton_ns/Kconfig | 1 - src/soc/intel/denverton_ns/Makefile.inc | 1 - src/soc/intel/denverton_ns/acpi.c | 4 ---- src/soc/intel/denverton_ns/acpi/globalnvs.asl | 2 -- src/soc/intel/denverton_ns/acpi/irqlinks.asl | 2 -- src/soc/intel/denverton_ns/acpi/lpc.asl | 2 -- src/soc/intel/denverton_ns/acpi/northcluster.asl | 2 -- src/soc/intel/denverton_ns/acpi/npk.asl | 1 - src/soc/intel/denverton_ns/acpi/pcie.asl | 3 --- src/soc/intel/denverton_ns/acpi/pcie_port.asl | 2 -- src/soc/intel/denverton_ns/acpi/pmc.asl | 1 - src/soc/intel/denverton_ns/acpi/sata.asl | 1 - src/soc/intel/denverton_ns/acpi/sata2.asl | 1 - src/soc/intel/denverton_ns/acpi/smbus.asl | 2 -- src/soc/intel/denverton_ns/acpi/smbus2.asl | 1 - src/soc/intel/denverton_ns/acpi/southcluster.asl | 2 -- src/soc/intel/denverton_ns/acpi/xhci.asl | 2 -- src/soc/intel/denverton_ns/bootblock/bootblock.c | 1 - src/soc/intel/denverton_ns/bootblock/uart.c | 1 - src/soc/intel/denverton_ns/chip.c | 2 -- src/soc/intel/denverton_ns/chip.h | 1 - src/soc/intel/denverton_ns/cpu.c | 2 -- src/soc/intel/denverton_ns/csme_ie_kt.c | 1 - src/soc/intel/denverton_ns/fiamux.c | 2 -- src/soc/intel/denverton_ns/gpio.c | 3 --- src/soc/intel/denverton_ns/gpio_dnv.c | 1 - src/soc/intel/denverton_ns/hob_display.c | 1 - src/soc/intel/denverton_ns/hob_mem.c | 3 --- src/soc/intel/denverton_ns/include/soc/acpi.h | 2 -- src/soc/intel/denverton_ns/include/soc/bootblock.h | 1 - src/soc/intel/denverton_ns/include/soc/cpu.h | 1 - src/soc/intel/denverton_ns/include/soc/fiamux.h | 2 -- src/soc/intel/denverton_ns/include/soc/gpio.h | 1 - src/soc/intel/denverton_ns/include/soc/gpio_defs.h | 2 -- src/soc/intel/denverton_ns/include/soc/gpio_dnv.h | 1 - src/soc/intel/denverton_ns/include/soc/hob_mem.h | 3 --- src/soc/intel/denverton_ns/include/soc/iomap.h | 2 -- src/soc/intel/denverton_ns/include/soc/lpc.h | 3 --- src/soc/intel/denverton_ns/include/soc/msr.h | 2 -- src/soc/intel/denverton_ns/include/soc/nvs.h | 3 --- src/soc/intel/denverton_ns/include/soc/p2sb.h | 1 - src/soc/intel/denverton_ns/include/soc/pattrs.h | 2 -- src/soc/intel/denverton_ns/include/soc/pci_devs.h | 2 -- src/soc/intel/denverton_ns/include/soc/pcr.h | 1 - src/soc/intel/denverton_ns/include/soc/pm.h | 2 -- src/soc/intel/denverton_ns/include/soc/pmc.h | 2 -- src/soc/intel/denverton_ns/include/soc/ramstage.h | 1 - src/soc/intel/denverton_ns/include/soc/romstage.h | 1 - src/soc/intel/denverton_ns/include/soc/sata.h | 2 -- src/soc/intel/denverton_ns/include/soc/smbus.h | 4 ---- src/soc/intel/denverton_ns/include/soc/smm.h | 2 -- src/soc/intel/denverton_ns/include/soc/soc_util.h | 1 - src/soc/intel/denverton_ns/include/soc/systemagent.h | 3 --- src/soc/intel/denverton_ns/include/soc/uart.h | 1 - src/soc/intel/denverton_ns/lpc.c | 1 - src/soc/intel/denverton_ns/memmap.c | 1 - src/soc/intel/denverton_ns/npk.c | 1 - src/soc/intel/denverton_ns/pmc.c | 1 - src/soc/intel/denverton_ns/pmutil.c | 2 -- src/soc/intel/denverton_ns/reset.c | 1 - src/soc/intel/denverton_ns/romstage.c | 2 -- src/soc/intel/denverton_ns/sata.c | 2 -- src/soc/intel/denverton_ns/smihandler.c | 2 -- src/soc/intel/denverton_ns/smm.c | 2 -- src/soc/intel/denverton_ns/soc_util.c | 1 - src/soc/intel/denverton_ns/spi.c | 1 - src/soc/intel/denverton_ns/systemagent.c | 3 --- src/soc/intel/denverton_ns/tsc_freq.c | 2 -- src/soc/intel/denverton_ns/uart.c | 1 - src/soc/intel/denverton_ns/uart_debug.c | 1 - src/soc/intel/denverton_ns/upd_display.c | 1 - src/soc/intel/denverton_ns/xhci.c | 1 - src/soc/intel/icelake/acpi.c | 1 - src/soc/intel/icelake/acpi/gpio.asl | 1 - src/soc/intel/icelake/acpi/pch_glan.asl | 3 --- src/soc/intel/icelake/acpi/pch_hda.asl | 1 - src/soc/intel/icelake/acpi/pci_irqs.asl | 2 -- src/soc/intel/icelake/acpi/pcie.asl | 1 - src/soc/intel/icelake/acpi/platform.asl | 1 - src/soc/intel/icelake/acpi/scs.asl | 1 - src/soc/intel/icelake/acpi/serialio.asl | 1 - src/soc/intel/icelake/acpi/smbus.asl | 1 - src/soc/intel/icelake/acpi/southbridge.asl | 2 -- src/soc/intel/icelake/acpi/xhci.asl | 1 - src/soc/intel/icelake/bootblock/bootblock.c | 1 - src/soc/intel/icelake/bootblock/cpu.c | 1 - src/soc/intel/icelake/bootblock/pch.c | 1 - src/soc/intel/icelake/bootblock/report_platform.c | 1 - src/soc/intel/icelake/chip.c | 1 - src/soc/intel/icelake/chip.h | 1 - src/soc/intel/icelake/cpu.c | 1 - src/soc/intel/icelake/elog.c | 2 -- src/soc/intel/icelake/espi.c | 1 - src/soc/intel/icelake/finalize.c | 1 - src/soc/intel/icelake/fsp_params.c | 1 - src/soc/intel/icelake/gpio.c | 1 - src/soc/intel/icelake/graphics.c | 1 - src/soc/intel/icelake/gspi.c | 1 - src/soc/intel/icelake/i2c.c | 1 - src/soc/intel/icelake/include/soc/bootblock.h | 1 - src/soc/intel/icelake/include/soc/cpu.h | 1 - src/soc/intel/icelake/include/soc/espi.h | 1 - src/soc/intel/icelake/include/soc/gpe.h | 1 - src/soc/intel/icelake/include/soc/gpio.h | 1 - src/soc/intel/icelake/include/soc/gpio_defs.h | 1 - src/soc/intel/icelake/include/soc/gpio_soc_defs.h | 1 - src/soc/intel/icelake/include/soc/iomap.h | 1 - src/soc/intel/icelake/include/soc/irq.h | 1 - src/soc/intel/icelake/include/soc/itss.h | 1 - src/soc/intel/icelake/include/soc/me.h | 1 - src/soc/intel/icelake/include/soc/msr.h | 1 - src/soc/intel/icelake/include/soc/nvs.h | 1 - src/soc/intel/icelake/include/soc/p2sb.h | 1 - src/soc/intel/icelake/include/soc/pch.h | 1 - src/soc/intel/icelake/include/soc/pci_devs.h | 1 - src/soc/intel/icelake/include/soc/pcr_ids.h | 1 - src/soc/intel/icelake/include/soc/pm.h | 1 - src/soc/intel/icelake/include/soc/pmc.h | 1 - src/soc/intel/icelake/include/soc/ramstage.h | 1 - src/soc/intel/icelake/include/soc/romstage.h | 1 - src/soc/intel/icelake/include/soc/serialio.h | 1 - src/soc/intel/icelake/include/soc/smbus.h | 1 - src/soc/intel/icelake/include/soc/soc_chip.h | 1 - src/soc/intel/icelake/include/soc/systemagent.h | 1 - src/soc/intel/icelake/include/soc/usb.h | 1 - src/soc/intel/icelake/lockdown.c | 1 - src/soc/intel/icelake/p2sb.c | 1 - src/soc/intel/icelake/pmc.c | 1 - src/soc/intel/icelake/pmutil.c | 1 - src/soc/intel/icelake/reset.c | 1 - src/soc/intel/icelake/romstage/Makefile.inc | 1 - src/soc/intel/icelake/romstage/fsp_params.c | 1 - src/soc/intel/icelake/romstage/pch.c | 1 - src/soc/intel/icelake/romstage/romstage.c | 1 - src/soc/intel/icelake/romstage/systemagent.c | 1 - src/soc/intel/icelake/sd.c | 1 - src/soc/intel/icelake/smihandler.c | 1 - src/soc/intel/icelake/smmrelocate.c | 1 - src/soc/intel/icelake/spi.c | 1 - src/soc/intel/icelake/systemagent.c | 1 - src/soc/intel/icelake/uart.c | 1 - src/soc/intel/quark/Kconfig | 1 - src/soc/intel/quark/Makefile.inc | 1 - src/soc/intel/quark/acpi.c | 3 --- src/soc/intel/quark/bootblock/bootblock.c | 2 -- src/soc/intel/quark/bootblock/esram_init.S | 1 - src/soc/intel/quark/chip.c | 2 -- src/soc/intel/quark/chip.h | 3 --- src/soc/intel/quark/ehci.c | 1 - src/soc/intel/quark/fsp_params.c | 1 - src/soc/intel/quark/gpio_i2c.c | 1 - src/soc/intel/quark/i2c.c | 1 - src/soc/intel/quark/include/soc/IntelQNCConfig.h | 1 - src/soc/intel/quark/include/soc/Ioh.h | 1 - src/soc/intel/quark/include/soc/QuarkNcSocId.h | 1 - src/soc/intel/quark/include/soc/acpi.h | 2 -- src/soc/intel/quark/include/soc/car.h | 1 - src/soc/intel/quark/include/soc/cpu.h | 1 - src/soc/intel/quark/include/soc/i2c.h | 1 - src/soc/intel/quark/include/soc/iomap.h | 2 -- src/soc/intel/quark/include/soc/pci_devs.h | 3 --- src/soc/intel/quark/include/soc/pei_wrapper.h | 2 -- src/soc/intel/quark/include/soc/pm.h | 2 -- src/soc/intel/quark/include/soc/ramstage.h | 2 -- src/soc/intel/quark/include/soc/reg_access.h | 1 - src/soc/intel/quark/include/soc/romstage.h | 3 --- src/soc/intel/quark/include/soc/sd.h | 1 - src/soc/intel/quark/include/soc/spi.h | 1 - src/soc/intel/quark/include/soc/storage_test.h | 1 - src/soc/intel/quark/lpc.c | 3 --- src/soc/intel/quark/memmap.c | 1 - src/soc/intel/quark/northcluster.c | 3 --- src/soc/intel/quark/reg_access.c | 1 - src/soc/intel/quark/reset.c | 1 - src/soc/intel/quark/romstage/Makefile.inc | 1 - src/soc/intel/quark/romstage/car.c | 2 -- src/soc/intel/quark/romstage/debug.c | 1 - src/soc/intel/quark/romstage/fsp_params.c | 1 - src/soc/intel/quark/romstage/mtrr.c | 2 -- src/soc/intel/quark/romstage/pcie.c | 1 - src/soc/intel/quark/romstage/report_platform.c | 2 -- src/soc/intel/quark/romstage/romstage.c | 2 -- src/soc/intel/quark/sd.c | 1 - src/soc/intel/quark/spi.c | 1 - src/soc/intel/quark/spi_debug.c | 1 - src/soc/intel/quark/storage_test.c | 1 - src/soc/intel/quark/tsc_freq.c | 2 -- src/soc/intel/quark/uart.c | 3 --- src/soc/intel/quark/uart_common.c | 3 --- src/soc/intel/skylake/acpi.c | 3 --- src/soc/intel/skylake/acpi/dptf/charger.asl | 2 -- src/soc/intel/skylake/acpi/dptf/cpu.asl | 2 -- src/soc/intel/skylake/acpi/dptf/dptf.asl | 2 -- src/soc/intel/skylake/acpi/dptf/fan.asl | 1 - src/soc/intel/skylake/acpi/dptf/thermal.asl | 2 -- src/soc/intel/skylake/acpi/globalnvs.asl | 3 --- src/soc/intel/skylake/acpi/gpio.asl | 2 -- src/soc/intel/skylake/acpi/ipu.asl | 1 - src/soc/intel/skylake/acpi/irqlinks.asl | 3 --- src/soc/intel/skylake/acpi/lpc.asl | 3 --- src/soc/intel/skylake/acpi/pch.asl | 3 --- src/soc/intel/skylake/acpi/pch_hda.asl | 2 -- src/soc/intel/skylake/acpi/pci_irqs.asl | 3 --- src/soc/intel/skylake/acpi/pcie.asl | 3 --- src/soc/intel/skylake/acpi/platform.asl | 3 --- src/soc/intel/skylake/acpi/pmc.asl | 1 - src/soc/intel/skylake/acpi/scs.asl | 2 -- src/soc/intel/skylake/acpi/serialio.asl | 2 -- src/soc/intel/skylake/acpi/smbus.asl | 3 --- src/soc/intel/skylake/acpi/systemagent.asl | 3 --- src/soc/intel/skylake/acpi/xhci.asl | 3 --- src/soc/intel/skylake/bootblock/bootblock.c | 1 - src/soc/intel/skylake/bootblock/cpu.c | 2 -- src/soc/intel/skylake/bootblock/pch.c | 2 -- src/soc/intel/skylake/bootblock/report_platform.c | 2 -- src/soc/intel/skylake/chip.c | 1 - src/soc/intel/skylake/chip.h | 3 --- src/soc/intel/skylake/cpu.c | 3 --- src/soc/intel/skylake/elog.c | 2 -- src/soc/intel/skylake/finalize.c | 2 -- src/soc/intel/skylake/gpio.c | 2 -- src/soc/intel/skylake/graphics.c | 2 -- src/soc/intel/skylake/gspi.c | 1 - src/soc/intel/skylake/i2c.c | 2 -- src/soc/intel/skylake/include/soc/acpi.h | 2 -- src/soc/intel/skylake/include/soc/bootblock.h | 1 - src/soc/intel/skylake/include/soc/cpu.h | 2 -- src/soc/intel/skylake/include/soc/device_nvs.h | 2 -- src/soc/intel/skylake/include/soc/gpe.h | 1 - src/soc/intel/skylake/include/soc/gpio.h | 2 -- src/soc/intel/skylake/include/soc/gpio_defs.h | 1 - src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h | 1 - src/soc/intel/skylake/include/soc/gpio_soc_defs.h | 1 - src/soc/intel/skylake/include/soc/interrupt.h | 2 -- src/soc/intel/skylake/include/soc/iomap.h | 2 -- src/soc/intel/skylake/include/soc/irq.h | 2 -- src/soc/intel/skylake/include/soc/itss.h | 1 - src/soc/intel/skylake/include/soc/me.h | 3 --- src/soc/intel/skylake/include/soc/msr.h | 2 -- src/soc/intel/skylake/include/soc/nhlt.h | 1 - src/soc/intel/skylake/include/soc/nvs.h | 3 --- src/soc/intel/skylake/include/soc/p2sb.h | 1 - src/soc/intel/skylake/include/soc/pch.h | 3 --- src/soc/intel/skylake/include/soc/pci_devs.h | 2 -- src/soc/intel/skylake/include/soc/pcr_ids.h | 1 - src/soc/intel/skylake/include/soc/pm.h | 2 -- src/soc/intel/skylake/include/soc/pmc.h | 2 -- src/soc/intel/skylake/include/soc/ramstage.h | 2 -- src/soc/intel/skylake/include/soc/romstage.h | 2 -- src/soc/intel/skylake/include/soc/serialio.h | 2 -- src/soc/intel/skylake/include/soc/smbus.h | 4 ---- src/soc/intel/skylake/include/soc/soc_chip.h | 1 - src/soc/intel/skylake/include/soc/systemagent.h | 3 --- src/soc/intel/skylake/include/soc/usb.h | 2 -- src/soc/intel/skylake/include/soc/vr_config.h | 2 -- src/soc/intel/skylake/irq.c | 1 - src/soc/intel/skylake/lockdown.c | 1 - src/soc/intel/skylake/lpc.c | 3 --- src/soc/intel/skylake/me.c | 1 - src/soc/intel/skylake/nhlt/da7219.c | 1 - src/soc/intel/skylake/nhlt/dmic.c | 1 - src/soc/intel/skylake/nhlt/max98357.c | 1 - src/soc/intel/skylake/nhlt/max98373.c | 1 - src/soc/intel/skylake/nhlt/max98927.c | 1 - src/soc/intel/skylake/nhlt/nau88l25.c | 1 - src/soc/intel/skylake/nhlt/rt5514.c | 1 - src/soc/intel/skylake/nhlt/rt5663.c | 1 - src/soc/intel/skylake/nhlt/ssm4567.c | 1 - src/soc/intel/skylake/p2sb.c | 1 - src/soc/intel/skylake/pmc.c | 3 --- src/soc/intel/skylake/pmutil.c | 2 -- src/soc/intel/skylake/reset.c | 1 - src/soc/intel/skylake/romstage/pch.c | 1 - src/soc/intel/skylake/romstage/romstage.c | 1 - src/soc/intel/skylake/romstage/systemagent.c | 3 --- src/soc/intel/skylake/sd.c | 1 - src/soc/intel/skylake/smihandler.c | 3 --- src/soc/intel/skylake/smmrelocate.c | 2 -- src/soc/intel/skylake/spi.c | 2 -- src/soc/intel/skylake/systemagent.c | 3 --- src/soc/intel/skylake/uart.c | 2 -- src/soc/intel/skylake/vr_config.c | 1 - src/soc/intel/skylake/xhci.c | 1 - src/soc/intel/tigerlake/acpi.c | 1 - src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl | 1 - src/soc/intel/tigerlake/acpi/gpio.asl | 1 - src/soc/intel/tigerlake/acpi/gpio_op.asl | 1 - src/soc/intel/tigerlake/acpi/ipu.asl | 1 - src/soc/intel/tigerlake/acpi/ish.asl | 1 - src/soc/intel/tigerlake/acpi/pch_glan.asl | 3 --- src/soc/intel/tigerlake/acpi/pch_hda.asl | 1 - src/soc/intel/tigerlake/acpi/pci_irqs.asl | 1 - src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl | 1 - src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl | 1 - src/soc/intel/tigerlake/acpi/pcie.asl | 1 - src/soc/intel/tigerlake/acpi/platform.asl | 1 - src/soc/intel/tigerlake/acpi/pmc.asl | 1 - src/soc/intel/tigerlake/acpi/scs.asl | 1 - src/soc/intel/tigerlake/acpi/serialio.asl | 1 - src/soc/intel/tigerlake/acpi/smbus.asl | 1 - src/soc/intel/tigerlake/acpi/southbridge.asl | 1 - src/soc/intel/tigerlake/acpi/xhci.asl | 1 - src/soc/intel/tigerlake/acpi/xhci_jsl.asl | 1 - src/soc/intel/tigerlake/acpi/xhci_tgl.asl | 1 - src/soc/intel/tigerlake/bootblock/bootblock.c | 1 - src/soc/intel/tigerlake/bootblock/cpu.c | 1 - src/soc/intel/tigerlake/bootblock/pch.c | 1 - src/soc/intel/tigerlake/bootblock/report_platform.c | 1 - src/soc/intel/tigerlake/chip.c | 1 - src/soc/intel/tigerlake/chip.h | 1 - src/soc/intel/tigerlake/cpu.c | 1 - src/soc/intel/tigerlake/elog.c | 2 -- src/soc/intel/tigerlake/espi.c | 1 - src/soc/intel/tigerlake/finalize.c | 1 - src/soc/intel/tigerlake/fsp_params_jsl.c | 1 - src/soc/intel/tigerlake/fsp_params_tgl.c | 1 - src/soc/intel/tigerlake/gpio_jsl.c | 1 - src/soc/intel/tigerlake/gpio_tgl.c | 1 - src/soc/intel/tigerlake/graphics.c | 1 - src/soc/intel/tigerlake/gspi.c | 1 - src/soc/intel/tigerlake/i2c.c | 1 - src/soc/intel/tigerlake/include/soc/bootblock.h | 1 - src/soc/intel/tigerlake/include/soc/cpu.h | 1 - src/soc/intel/tigerlake/include/soc/espi.h | 1 - src/soc/intel/tigerlake/include/soc/gpe.h | 1 - src/soc/intel/tigerlake/include/soc/gpio.h | 1 - src/soc/intel/tigerlake/include/soc/gpio_defs.h | 1 - src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h | 1 - src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h | 1 - src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h | 1 - src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h | 1 - src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h | 1 - src/soc/intel/tigerlake/include/soc/iomap.h | 1 - src/soc/intel/tigerlake/include/soc/irq.h | 1 - src/soc/intel/tigerlake/include/soc/irq_jsl.h | 1 - src/soc/intel/tigerlake/include/soc/irq_tgl.h | 1 - src/soc/intel/tigerlake/include/soc/itss.h | 1 - src/soc/intel/tigerlake/include/soc/me.h | 1 - src/soc/intel/tigerlake/include/soc/meminit_jsl.h | 1 - src/soc/intel/tigerlake/include/soc/meminit_tgl.h | 1 - src/soc/intel/tigerlake/include/soc/msr.h | 1 - src/soc/intel/tigerlake/include/soc/nvs.h | 1 - src/soc/intel/tigerlake/include/soc/p2sb.h | 1 - src/soc/intel/tigerlake/include/soc/pch.h | 1 - src/soc/intel/tigerlake/include/soc/pci_devs.h | 1 - src/soc/intel/tigerlake/include/soc/pcr_ids.h | 1 - src/soc/intel/tigerlake/include/soc/pm.h | 1 - src/soc/intel/tigerlake/include/soc/pmc.h | 1 - src/soc/intel/tigerlake/include/soc/ramstage.h | 1 - src/soc/intel/tigerlake/include/soc/romstage.h | 1 - src/soc/intel/tigerlake/include/soc/serialio.h | 1 - src/soc/intel/tigerlake/include/soc/smbus.h | 1 - src/soc/intel/tigerlake/include/soc/soc_chip.h | 1 - src/soc/intel/tigerlake/include/soc/systemagent.h | 1 - src/soc/intel/tigerlake/include/soc/usb.h | 1 - src/soc/intel/tigerlake/lockdown.c | 1 - src/soc/intel/tigerlake/meminit_jsl.c | 1 - src/soc/intel/tigerlake/meminit_tgl.c | 1 - src/soc/intel/tigerlake/p2sb.c | 1 - src/soc/intel/tigerlake/pmc.c | 1 - src/soc/intel/tigerlake/pmutil.c | 1 - src/soc/intel/tigerlake/reset.c | 1 - src/soc/intel/tigerlake/romstage/Makefile.inc | 1 - src/soc/intel/tigerlake/romstage/fsp_params_jsl.c | 1 - src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 1 - src/soc/intel/tigerlake/romstage/pch.c | 1 - src/soc/intel/tigerlake/romstage/romstage.c | 1 - src/soc/intel/tigerlake/romstage/systemagent.c | 1 - src/soc/intel/tigerlake/sd.c | 1 - src/soc/intel/tigerlake/smihandler.c | 1 - src/soc/intel/tigerlake/smmrelocate.c | 1 - src/soc/intel/tigerlake/spi.c | 1 - src/soc/intel/tigerlake/systemagent.c | 1 - src/soc/intel/tigerlake/uart.c | 1 - src/soc/intel/xeon_sp/Kconfig | 2 -- src/soc/intel/xeon_sp/Makefile.inc | 2 -- src/soc/intel/xeon_sp/acpi.c | 2 -- src/soc/intel/xeon_sp/acpi/globalnvs.asl | 3 --- src/soc/intel/xeon_sp/acpi/iiostack.asl | 2 -- src/soc/intel/xeon_sp/acpi/pci_irq.asl | 4 ---- src/soc/intel/xeon_sp/acpi/uncore.asl | 2 -- src/soc/intel/xeon_sp/acpi/uncore_irq.asl | 2 -- src/soc/intel/xeon_sp/bootblock/bootblock.c | 1 - src/soc/intel/xeon_sp/chip.c | 2 -- src/soc/intel/xeon_sp/chip.h | 2 -- src/soc/intel/xeon_sp/cpu.c | 2 -- src/soc/intel/xeon_sp/hob_display.c | 2 -- src/soc/intel/xeon_sp/include/soc/acpi.h | 1 - src/soc/intel/xeon_sp/include/soc/cpu.h | 1 - src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h | 1 - src/soc/intel/xeon_sp/include/soc/iomap.h | 1 - src/soc/intel/xeon_sp/include/soc/irq.h | 1 - src/soc/intel/xeon_sp/include/soc/msr.h | 1 - src/soc/intel/xeon_sp/include/soc/nvs.h | 3 --- src/soc/intel/xeon_sp/include/soc/pci_devs.h | 1 - src/soc/intel/xeon_sp/include/soc/pcr_ids.h | 1 - src/soc/intel/xeon_sp/include/soc/pm.h | 2 -- src/soc/intel/xeon_sp/include/soc/pmc.h | 1 - src/soc/intel/xeon_sp/include/soc/ramstage.h | 1 - src/soc/intel/xeon_sp/include/soc/romstage.h | 1 - src/soc/intel/xeon_sp/include/soc/soc_util.h | 1 - src/soc/intel/xeon_sp/lpc.c | 2 -- src/soc/intel/xeon_sp/reset.c | 2 -- src/soc/intel/xeon_sp/romstage.c | 2 -- src/soc/intel/xeon_sp/soc_util.c | 2 -- src/soc/intel/xeon_sp/spi.c | 2 -- src/soc/intel/xeon_sp/uncore.c | 2 -- src/soc/intel/xeon_sp/upd_display.c | 2 -- src/soc/mediatek/common/cbmem.c | 1 - src/soc/mediatek/common/ddp.c | 1 - src/soc/mediatek/common/dsi.c | 1 - src/soc/mediatek/common/gpio.c | 1 - src/soc/mediatek/common/i2c.c | 1 - src/soc/mediatek/common/include/soc/ddp_common.h | 1 - src/soc/mediatek/common/include/soc/dsi_common.h | 1 - src/soc/mediatek/common/include/soc/gpio_common.h | 1 - src/soc/mediatek/common/include/soc/i2c_common.h | 1 - src/soc/mediatek/common/include/soc/mmu_operations.h | 1 - src/soc/mediatek/common/include/soc/mtcmos.h | 1 - src/soc/mediatek/common/include/soc/pll_common.h | 1 - src/soc/mediatek/common/include/soc/pmic_wrap_common.h | 1 - src/soc/mediatek/common/include/soc/rtc_common.h | 1 - src/soc/mediatek/common/include/soc/spi_common.h | 1 - src/soc/mediatek/common/include/soc/timer.h | 1 - src/soc/mediatek/common/include/soc/usb_common.h | 1 - src/soc/mediatek/common/include/soc/wdt.h | 1 - src/soc/mediatek/common/memory_test.c | 1 - src/soc/mediatek/common/mmu_operations.c | 1 - src/soc/mediatek/common/mtcmos.c | 1 - src/soc/mediatek/common/pll.c | 1 - src/soc/mediatek/common/pmic_wrap.c | 1 - src/soc/mediatek/common/reset.c | 1 - src/soc/mediatek/common/rtc.c | 1 - src/soc/mediatek/common/spi.c | 1 - src/soc/mediatek/common/timer.c | 1 - src/soc/mediatek/common/uart.c | 1 - src/soc/mediatek/common/usb.c | 1 - src/soc/mediatek/common/wdt.c | 1 - src/soc/mediatek/mt8173/Makefile.inc | 1 - src/soc/mediatek/mt8173/bootblock.c | 1 - src/soc/mediatek/mt8173/da9212.c | 1 - src/soc/mediatek/mt8173/ddp.c | 1 - src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 1 - src/soc/mediatek/mt8173/dramc_pi_calibration_api.c | 1 - src/soc/mediatek/mt8173/dsi.c | 1 - src/soc/mediatek/mt8173/emi.c | 1 - src/soc/mediatek/mt8173/flash_controller.c | 1 - src/soc/mediatek/mt8173/gpio.c | 1 - src/soc/mediatek/mt8173/gpio_init.c | 1 - src/soc/mediatek/mt8173/i2c.c | 1 - src/soc/mediatek/mt8173/include/soc/addressmap.h | 1 - src/soc/mediatek/mt8173/include/soc/da9212.h | 1 - src/soc/mediatek/mt8173/include/soc/ddp.h | 1 - src/soc/mediatek/mt8173/include/soc/dramc_common.h | 1 - src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h | 1 - src/soc/mediatek/mt8173/include/soc/dramc_register.h | 1 - src/soc/mediatek/mt8173/include/soc/dsi.h | 1 - src/soc/mediatek/mt8173/include/soc/emi.h | 1 - src/soc/mediatek/mt8173/include/soc/flash_controller.h | 1 - src/soc/mediatek/mt8173/include/soc/gpio.h | 1 - src/soc/mediatek/mt8173/include/soc/gpio_base.h | 1 - src/soc/mediatek/mt8173/include/soc/i2c.h | 1 - src/soc/mediatek/mt8173/include/soc/infracfg.h | 1 - src/soc/mediatek/mt8173/include/soc/mcucfg.h | 1 - src/soc/mediatek/mt8173/include/soc/memlayout.ld | 1 - src/soc/mediatek/mt8173/include/soc/mipi.h | 1 - src/soc/mediatek/mt8173/include/soc/mt6311.h | 1 - src/soc/mediatek/mt8173/include/soc/mt6391.h | 1 - src/soc/mediatek/mt8173/include/soc/pericfg.h | 1 - src/soc/mediatek/mt8173/include/soc/pll.h | 1 - src/soc/mediatek/mt8173/include/soc/pmic_wrap.h | 1 - src/soc/mediatek/mt8173/include/soc/rtc.h | 1 - src/soc/mediatek/mt8173/include/soc/spi.h | 1 - src/soc/mediatek/mt8173/include/soc/spm.h | 1 - src/soc/mediatek/mt8173/include/soc/symbols.h | 1 - src/soc/mediatek/mt8173/include/soc/usb.h | 1 - src/soc/mediatek/mt8173/memory.c | 1 - src/soc/mediatek/mt8173/mmu_operations.c | 1 - src/soc/mediatek/mt8173/mt6311.c | 1 - src/soc/mediatek/mt8173/mt6391.c | 1 - src/soc/mediatek/mt8173/pll.c | 1 - src/soc/mediatek/mt8173/pmic_wrap.c | 1 - src/soc/mediatek/mt8173/rtc.c | 1 - src/soc/mediatek/mt8173/soc.c | 1 - src/soc/mediatek/mt8173/spi.c | 1 - src/soc/mediatek/mt8173/timer.c | 1 - src/soc/mediatek/mt8173/usb.c | 1 - src/soc/mediatek/mt8183/auxadc.c | 1 - src/soc/mediatek/mt8183/bootblock.c | 1 - src/soc/mediatek/mt8183/ddp.c | 1 - src/soc/mediatek/mt8183/decompressor.c | 1 - src/soc/mediatek/mt8183/dramc_init_setting.c | 1 - src/soc/mediatek/mt8183/dramc_param.c | 1 - src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 1 - src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 1 - src/soc/mediatek/mt8183/dsi.c | 1 - src/soc/mediatek/mt8183/emi.c | 1 - src/soc/mediatek/mt8183/gpio.c | 1 - src/soc/mediatek/mt8183/i2c.c | 1 - src/soc/mediatek/mt8183/include/soc/addressmap.h | 1 - src/soc/mediatek/mt8183/include/soc/auxadc.h | 1 - src/soc/mediatek/mt8183/include/soc/ddp.h | 1 - src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h | 1 - src/soc/mediatek/mt8183/include/soc/dramc_param.h | 1 - src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 1 - src/soc/mediatek/mt8183/include/soc/dramc_register.h | 1 - src/soc/mediatek/mt8183/include/soc/dsi.h | 1 - src/soc/mediatek/mt8183/include/soc/efuse.h | 1 - src/soc/mediatek/mt8183/include/soc/emi.h | 1 - src/soc/mediatek/mt8183/include/soc/flash_controller.h | 1 - src/soc/mediatek/mt8183/include/soc/gpio.h | 1 - src/soc/mediatek/mt8183/include/soc/gpio_base.h | 1 - src/soc/mediatek/mt8183/include/soc/i2c.h | 1 - src/soc/mediatek/mt8183/include/soc/infracfg.h | 1 - src/soc/mediatek/mt8183/include/soc/mcucfg.h | 1 - src/soc/mediatek/mt8183/include/soc/md_ctrl.h | 1 - src/soc/mediatek/mt8183/include/soc/memlayout.ld | 1 - src/soc/mediatek/mt8183/include/soc/mt6358.h | 1 - src/soc/mediatek/mt8183/include/soc/mt8183.h | 1 - src/soc/mediatek/mt8183/include/soc/pll.h | 1 - src/soc/mediatek/mt8183/include/soc/pmic_wrap.h | 1 - src/soc/mediatek/mt8183/include/soc/rtc.h | 1 - src/soc/mediatek/mt8183/include/soc/smi.h | 1 - src/soc/mediatek/mt8183/include/soc/spi.h | 1 - src/soc/mediatek/mt8183/include/soc/spm.h | 1 - src/soc/mediatek/mt8183/include/soc/sspm.h | 1 - src/soc/mediatek/mt8183/include/soc/usb.h | 1 - src/soc/mediatek/mt8183/md_ctrl.c | 1 - src/soc/mediatek/mt8183/memory.c | 1 - src/soc/mediatek/mt8183/mmu_operations.c | 1 - src/soc/mediatek/mt8183/mt6358.c | 1 - src/soc/mediatek/mt8183/mt8183.c | 1 - src/soc/mediatek/mt8183/mtcmos.c | 1 - src/soc/mediatek/mt8183/pll.c | 1 - src/soc/mediatek/mt8183/pmic_wrap.c | 1 - src/soc/mediatek/mt8183/rtc.c | 1 - src/soc/mediatek/mt8183/soc.c | 1 - src/soc/mediatek/mt8183/spi.c | 1 - src/soc/mediatek/mt8183/spm.c | 1 - src/soc/mediatek/mt8183/sspm.c | 1 - src/soc/nvidia/tegra/apbmisc.c | 1 - src/soc/nvidia/tegra/apbmisc.h | 1 - src/soc/nvidia/tegra/dc.h | 4 ---- src/soc/nvidia/tegra/displayport.h | 1 - src/soc/nvidia/tegra/gpio.c | 1 - src/soc/nvidia/tegra/gpio.h | 1 - src/soc/nvidia/tegra/i2c.c | 1 - src/soc/nvidia/tegra/i2c.h | 1 - src/soc/nvidia/tegra/pingroup.c | 1 - src/soc/nvidia/tegra/pingroup.h | 1 - src/soc/nvidia/tegra/pinmux.c | 1 - src/soc/nvidia/tegra/pinmux.h | 1 - src/soc/nvidia/tegra/pwm.h | 4 ---- src/soc/nvidia/tegra/software_i2c.c | 1 - src/soc/nvidia/tegra/types.h | 1 - src/soc/nvidia/tegra/usb.c | 1 - src/soc/nvidia/tegra/usb.h | 1 - src/soc/nvidia/tegra124/bootblock.c | 1 - src/soc/nvidia/tegra124/bootblock_asm.S | 8 -------- src/soc/nvidia/tegra124/cache.c | 1 - src/soc/nvidia/tegra124/cbmem.c | 1 - src/soc/nvidia/tegra124/chip.h | 1 - src/soc/nvidia/tegra124/clock.c | 2 -- src/soc/nvidia/tegra124/display.c | 1 - src/soc/nvidia/tegra124/dma.c | 3 --- src/soc/nvidia/tegra124/dp.c | 2 -- src/soc/nvidia/tegra124/i2c.c | 1 - src/soc/nvidia/tegra124/include/soc/addressmap.h | 5 ----- src/soc/nvidia/tegra124/include/soc/cache.h | 1 - src/soc/nvidia/tegra124/include/soc/clk_rst.h | 1 - src/soc/nvidia/tegra124/include/soc/clock.h | 2 -- src/soc/nvidia/tegra124/include/soc/display.h | 1 - src/soc/nvidia/tegra124/include/soc/dma.h | 3 --- src/soc/nvidia/tegra124/include/soc/early_configs.h | 1 - src/soc/nvidia/tegra124/include/soc/emc.h | 2 -- src/soc/nvidia/tegra124/include/soc/flow.h | 1 - src/soc/nvidia/tegra124/include/soc/gpio.h | 1 - src/soc/nvidia/tegra124/include/soc/maincpu.h | 1 - src/soc/nvidia/tegra124/include/soc/mc.h | 2 -- src/soc/nvidia/tegra124/include/soc/memlayout.ld | 1 - src/soc/nvidia/tegra124/include/soc/pingroup.h | 1 - src/soc/nvidia/tegra124/include/soc/pinmux.h | 1 - src/soc/nvidia/tegra124/include/soc/pmc.h | 1 - src/soc/nvidia/tegra124/include/soc/power.h | 1 - src/soc/nvidia/tegra124/include/soc/sdram.h | 1 - src/soc/nvidia/tegra124/include/soc/sdram_param.h | 2 -- src/soc/nvidia/tegra124/include/soc/sor.h | 1 - src/soc/nvidia/tegra124/include/soc/spi.h | 1 - src/soc/nvidia/tegra124/include/soc/sysctr.h | 1 - src/soc/nvidia/tegra124/lp0/Makefile | 1 - src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 2 -- src/soc/nvidia/tegra124/maincpu.S | 1 - src/soc/nvidia/tegra124/monotonic_timer.c | 1 - src/soc/nvidia/tegra124/power.c | 2 -- src/soc/nvidia/tegra124/sdram.c | 1 - src/soc/nvidia/tegra124/sdram_lp0.c | 2 -- src/soc/nvidia/tegra124/soc.c | 3 --- src/soc/nvidia/tegra124/sor.c | 1 - src/soc/nvidia/tegra124/spi.c | 2 -- src/soc/nvidia/tegra124/uart.c | 1 - src/soc/nvidia/tegra124/verstage.c | 1 - src/soc/nvidia/tegra210/addressmap.c | 1 - src/soc/nvidia/tegra210/ape.c | 1 - src/soc/nvidia/tegra210/arm_tf.c | 1 - src/soc/nvidia/tegra210/bootblock.c | 1 - src/soc/nvidia/tegra210/bootblock_asm.S | 8 -------- src/soc/nvidia/tegra210/cbmem.c | 1 - src/soc/nvidia/tegra210/ccplex.c | 1 - src/soc/nvidia/tegra210/chip.h | 1 - src/soc/nvidia/tegra210/clock.c | 2 -- src/soc/nvidia/tegra210/cpu.c | 1 - src/soc/nvidia/tegra210/dc.c | 1 - src/soc/nvidia/tegra210/dma.c | 3 --- src/soc/nvidia/tegra210/dp.c | 2 -- src/soc/nvidia/tegra210/dsi.c | 1 - src/soc/nvidia/tegra210/flow_ctrl.c | 1 - src/soc/nvidia/tegra210/funitcfg.c | 1 - src/soc/nvidia/tegra210/gic.c | 1 - src/soc/nvidia/tegra210/i2c.c | 1 - src/soc/nvidia/tegra210/i2c6.c | 2 -- src/soc/nvidia/tegra210/include/soc/addressmap.h | 4 ---- src/soc/nvidia/tegra210/include/soc/ccplex.h | 1 - src/soc/nvidia/tegra210/include/soc/clk_rst.h | 1 - src/soc/nvidia/tegra210/include/soc/clock.h | 2 -- src/soc/nvidia/tegra210/include/soc/clst_clk.h | 1 - src/soc/nvidia/tegra210/include/soc/console_uart.h | 1 - src/soc/nvidia/tegra210/include/soc/cpu.h | 1 - src/soc/nvidia/tegra210/include/soc/display.h | 1 - src/soc/nvidia/tegra210/include/soc/dma.h | 2 -- src/soc/nvidia/tegra210/include/soc/emc.h | 2 -- src/soc/nvidia/tegra210/include/soc/flow.h | 1 - src/soc/nvidia/tegra210/include/soc/flow_ctrl.h | 1 - src/soc/nvidia/tegra210/include/soc/funitcfg.h | 1 - src/soc/nvidia/tegra210/include/soc/gpio.h | 1 - src/soc/nvidia/tegra210/include/soc/id.h | 1 - src/soc/nvidia/tegra210/include/soc/maincpu.h | 1 - src/soc/nvidia/tegra210/include/soc/mc.h | 2 -- src/soc/nvidia/tegra210/include/soc/memlayout.ld | 1 - src/soc/nvidia/tegra210/include/soc/mipi-phy.h | 1 - src/soc/nvidia/tegra210/include/soc/mipi_display.h | 3 --- src/soc/nvidia/tegra210/include/soc/mipi_dsi.h | 2 -- src/soc/nvidia/tegra210/include/soc/mmu_operations.h | 1 - src/soc/nvidia/tegra210/include/soc/mtc.h | 1 - src/soc/nvidia/tegra210/include/soc/padconfig.h | 1 - src/soc/nvidia/tegra210/include/soc/pinmux.h | 1 - src/soc/nvidia/tegra210/include/soc/pmc.h | 1 - src/soc/nvidia/tegra210/include/soc/power.h | 1 - src/soc/nvidia/tegra210/include/soc/romstage.h | 1 - src/soc/nvidia/tegra210/include/soc/sdram.h | 1 - src/soc/nvidia/tegra210/include/soc/sdram_configs.h | 1 - src/soc/nvidia/tegra210/include/soc/sdram_param.h | 2 -- src/soc/nvidia/tegra210/include/soc/secure_boot.h | 1 - src/soc/nvidia/tegra210/include/soc/sor.h | 1 - src/soc/nvidia/tegra210/include/soc/spi.h | 2 -- src/soc/nvidia/tegra210/include/soc/sysctr.h | 1 - src/soc/nvidia/tegra210/include/soc/tegra_dsi.h | 1 - src/soc/nvidia/tegra210/include/soc/verstage.h | 1 - .../tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c | 1 - .../tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h | 1 - src/soc/nvidia/tegra210/lp0/Makefile | 1 - src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 2 -- src/soc/nvidia/tegra210/mipi-phy.c | 1 - src/soc/nvidia/tegra210/mipi.c | 1 - src/soc/nvidia/tegra210/mipi_dsi.c | 2 -- src/soc/nvidia/tegra210/mmu_operations.c | 1 - src/soc/nvidia/tegra210/monotonic_timer.c | 1 - src/soc/nvidia/tegra210/mtc.c | 1 - src/soc/nvidia/tegra210/padconfig.c | 1 - src/soc/nvidia/tegra210/power.c | 2 -- src/soc/nvidia/tegra210/ram_code.c | 1 - src/soc/nvidia/tegra210/ramstage.c | 1 - src/soc/nvidia/tegra210/romstage.c | 1 - src/soc/nvidia/tegra210/romstage_asm.S | 1 - src/soc/nvidia/tegra210/sdram.c | 1 - src/soc/nvidia/tegra210/sdram_lp0.c | 2 -- src/soc/nvidia/tegra210/soc.c | 2 -- src/soc/nvidia/tegra210/sor.c | 1 - src/soc/nvidia/tegra210/spi.c | 2 -- src/soc/nvidia/tegra210/stack.S | 1 - src/soc/nvidia/tegra210/stage_entry.S | 2 -- src/soc/nvidia/tegra210/uart.c | 1 - src/soc/qualcomm/common/include/soc/mmu_common.h | 1 - src/soc/qualcomm/common/include/soc/qclib_common.h | 1 - src/soc/qualcomm/common/include/soc/symbols_common.h | 1 - src/soc/qualcomm/common/mmu.c | 1 - src/soc/qualcomm/common/qclib.c | 1 - src/soc/qualcomm/ipq40xx/Makefile.inc | 1 - src/soc/qualcomm/ipq40xx/blobs_init.c | 2 -- src/soc/qualcomm/ipq40xx/blsp.c | 1 - src/soc/qualcomm/ipq40xx/cbmem.c | 1 - src/soc/qualcomm/ipq40xx/clock.c | 1 - src/soc/qualcomm/ipq40xx/gpio.c | 1 - src/soc/qualcomm/ipq40xx/i2c.c | 1 - src/soc/qualcomm/ipq40xx/include/soc/blsp.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/cdp.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/clock.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/ebi2.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/gpio.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/iomap.h | 4 ---- src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld | 2 -- src/soc/qualcomm/ipq40xx/include/soc/qup.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/soc_services.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/spi.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/usb.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h | 1 - src/soc/qualcomm/ipq40xx/include/soc/verstage.h | 1 - src/soc/qualcomm/ipq40xx/lcc.c | 1 - src/soc/qualcomm/ipq40xx/mbn_header.h | 1 - src/soc/qualcomm/ipq40xx/qup.c | 1 - src/soc/qualcomm/ipq40xx/soc.c | 3 --- src/soc/qualcomm/ipq40xx/spi.c | 1 - src/soc/qualcomm/ipq40xx/timer.c | 1 - src/soc/qualcomm/ipq40xx/tz_wrapper.S | 1 - src/soc/qualcomm/ipq40xx/uart.c | 1 - src/soc/qualcomm/ipq40xx/usb.c | 1 - src/soc/qualcomm/ipq806x/Makefile.inc | 1 - src/soc/qualcomm/ipq806x/blobs_init.c | 2 -- src/soc/qualcomm/ipq806x/cbmem.c | 1 - src/soc/qualcomm/ipq806x/clock.c | 1 - src/soc/qualcomm/ipq806x/gpio.c | 1 - src/soc/qualcomm/ipq806x/gsbi.c | 1 - src/soc/qualcomm/ipq806x/i2c.c | 1 - src/soc/qualcomm/ipq806x/include/soc/cdp.h | 1 - src/soc/qualcomm/ipq806x/include/soc/clock.h | 2 -- src/soc/qualcomm/ipq806x/include/soc/ebi2.h | 1 - src/soc/qualcomm/ipq806x/include/soc/gpio.h | 2 -- src/soc/qualcomm/ipq806x/include/soc/gsbi.h | 2 -- src/soc/qualcomm/ipq806x/include/soc/iomap.h | 4 ---- src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h | 1 - src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h | 2 -- src/soc/qualcomm/ipq806x/include/soc/lcc-reg.h | 1 - src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 2 -- src/soc/qualcomm/ipq806x/include/soc/qup.h | 1 - src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 1 - src/soc/qualcomm/ipq806x/include/soc/spi.h | 1 - src/soc/qualcomm/ipq806x/include/soc/usb.h | 1 - src/soc/qualcomm/ipq806x/include/soc/usbl_if.h | 1 - src/soc/qualcomm/ipq806x/lcc.c | 1 - src/soc/qualcomm/ipq806x/mbn_header.h | 1 - src/soc/qualcomm/ipq806x/qup.c | 1 - src/soc/qualcomm/ipq806x/soc.c | 3 --- src/soc/qualcomm/ipq806x/spi.c | 1 - src/soc/qualcomm/ipq806x/timer.c | 1 - src/soc/qualcomm/ipq806x/tz_wrapper.S | 1 - src/soc/qualcomm/ipq806x/uart.c | 2 -- src/soc/qualcomm/ipq806x/usb.c | 1 - src/soc/qualcomm/qcs405/blsp.c | 1 - src/soc/qualcomm/qcs405/bootblock.c | 1 - src/soc/qualcomm/qcs405/cbmem.c | 1 - src/soc/qualcomm/qcs405/clock.c | 1 - src/soc/qualcomm/qcs405/gpio.c | 1 - src/soc/qualcomm/qcs405/i2c.c | 1 - src/soc/qualcomm/qcs405/include/soc/addressmap.h | 1 - src/soc/qualcomm/qcs405/include/soc/blsp.h | 1 - src/soc/qualcomm/qcs405/include/soc/cdp.h | 1 - src/soc/qualcomm/qcs405/include/soc/clock.h | 1 - src/soc/qualcomm/qcs405/include/soc/gpio.h | 1 - src/soc/qualcomm/qcs405/include/soc/iomap.h | 6 ------ src/soc/qualcomm/qcs405/include/soc/memlayout.ld | 1 - src/soc/qualcomm/qcs405/include/soc/mmu.h | 1 - src/soc/qualcomm/qcs405/include/soc/qup.h | 1 - src/soc/qualcomm/qcs405/include/soc/spi.h | 1 - src/soc/qualcomm/qcs405/include/soc/symbols.h | 1 - src/soc/qualcomm/qcs405/include/soc/uart.h | 1 - src/soc/qualcomm/qcs405/include/soc/usb.h | 1 - src/soc/qualcomm/qcs405/mmu.c | 1 - src/soc/qualcomm/qcs405/qup.c | 1 - src/soc/qualcomm/qcs405/soc.c | 1 - src/soc/qualcomm/qcs405/spi.c | 1 - src/soc/qualcomm/qcs405/timer.c | 1 - src/soc/qualcomm/qcs405/uart.c | 1 - src/soc/qualcomm/qcs405/usb.c | 1 - src/soc/qualcomm/sc7180/aop_load_reset.c | 1 - src/soc/qualcomm/sc7180/bootblock.c | 1 - src/soc/qualcomm/sc7180/cbmem.c | 1 - src/soc/qualcomm/sc7180/clock.c | 1 - src/soc/qualcomm/sc7180/gpio.c | 1 - src/soc/qualcomm/sc7180/include/soc/addressmap.h | 1 - src/soc/qualcomm/sc7180/include/soc/aop.h | 1 - src/soc/qualcomm/sc7180/include/soc/clock.h | 1 - src/soc/qualcomm/sc7180/include/soc/efuse.h | 1 - src/soc/qualcomm/sc7180/include/soc/gpio.h | 1 - src/soc/qualcomm/sc7180/include/soc/memlayout.ld | 1 - src/soc/qualcomm/sc7180/include/soc/mmu.h | 1 - src/soc/qualcomm/sc7180/include/soc/qspi.h | 1 - src/soc/qualcomm/sc7180/include/soc/symbols.h | 1 - src/soc/qualcomm/sc7180/include/soc/usb.h | 1 - src/soc/qualcomm/sc7180/mmu.c | 1 - src/soc/qualcomm/sc7180/qclib.c | 1 - src/soc/qualcomm/sc7180/qspi.c | 1 - src/soc/qualcomm/sc7180/soc.c | 1 - src/soc/qualcomm/sc7180/spi.c | 1 - src/soc/qualcomm/sc7180/timer.c | 1 - src/soc/qualcomm/sc7180/uart_bitbang.c | 2 -- src/soc/qualcomm/sc7180/usb.c | 1 - src/soc/qualcomm/sdm845/aop_load_reset.c | 1 - src/soc/qualcomm/sdm845/bootblock.c | 1 - src/soc/qualcomm/sdm845/cbmem.c | 1 - src/soc/qualcomm/sdm845/clock.c | 1 - src/soc/qualcomm/sdm845/gpio.c | 1 - src/soc/qualcomm/sdm845/include/soc/addressmap.h | 1 - src/soc/qualcomm/sdm845/include/soc/aop.h | 1 - src/soc/qualcomm/sdm845/include/soc/clock.h | 1 - src/soc/qualcomm/sdm845/include/soc/efuse.h | 1 - src/soc/qualcomm/sdm845/include/soc/gpio.h | 1 - src/soc/qualcomm/sdm845/include/soc/memlayout.ld | 1 - src/soc/qualcomm/sdm845/include/soc/mmu.h | 1 - src/soc/qualcomm/sdm845/include/soc/qspi.h | 1 - src/soc/qualcomm/sdm845/include/soc/symbols.h | 1 - src/soc/qualcomm/sdm845/include/soc/usb.h | 1 - src/soc/qualcomm/sdm845/mmu.c | 1 - src/soc/qualcomm/sdm845/qclib.c | 1 - src/soc/qualcomm/sdm845/qspi.c | 1 - src/soc/qualcomm/sdm845/soc.c | 1 - src/soc/qualcomm/sdm845/spi.c | 1 - src/soc/qualcomm/sdm845/timer.c | 1 - src/soc/qualcomm/sdm845/uart_bitbang.c | 1 - src/soc/qualcomm/sdm845/usb.c | 1 - src/soc/rockchip/common/cbmem.c | 1 - src/soc/rockchip/common/edp.c | 1 - src/soc/rockchip/common/gpio.c | 1 - src/soc/rockchip/common/i2c.c | 1 - src/soc/rockchip/common/include/soc/edp.h | 1 - src/soc/rockchip/common/include/soc/gpio.h | 1 - src/soc/rockchip/common/include/soc/i2c.h | 1 - src/soc/rockchip/common/include/soc/pwm.h | 1 - src/soc/rockchip/common/include/soc/rk808.h | 1 - src/soc/rockchip/common/include/soc/soc.h | 1 - src/soc/rockchip/common/include/soc/spi.h | 1 - src/soc/rockchip/common/include/soc/vop.h | 1 - src/soc/rockchip/common/pwm.c | 1 - src/soc/rockchip/common/rk808.c | 1 - src/soc/rockchip/common/spi.c | 1 - src/soc/rockchip/common/uart.c | 1 - src/soc/rockchip/common/vop.c | 1 - src/soc/rockchip/rk3288/Kconfig | 1 - src/soc/rockchip/rk3288/Makefile.inc | 1 - src/soc/rockchip/rk3288/bootblock.c | 1 - src/soc/rockchip/rk3288/chip.h | 1 - src/soc/rockchip/rk3288/clock.c | 1 - src/soc/rockchip/rk3288/crypto.c | 1 - src/soc/rockchip/rk3288/display.c | 1 - src/soc/rockchip/rk3288/gpio.c | 1 - src/soc/rockchip/rk3288/hdmi.c | 2 -- src/soc/rockchip/rk3288/include/soc/addressmap.h | 1 - src/soc/rockchip/rk3288/include/soc/clock.h | 1 - src/soc/rockchip/rk3288/include/soc/display.h | 1 - src/soc/rockchip/rk3288/include/soc/grf.h | 1 - src/soc/rockchip/rk3288/include/soc/hdmi.h | 2 -- src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3288/include/soc/pmu.h | 1 - src/soc/rockchip/rk3288/include/soc/sdram.h | 1 - src/soc/rockchip/rk3288/include/soc/timer.h | 1 - src/soc/rockchip/rk3288/include/soc/tsadc.h | 1 - src/soc/rockchip/rk3288/sdram.c | 1 - src/soc/rockchip/rk3288/soc.c | 1 - src/soc/rockchip/rk3288/software_i2c.c | 1 - src/soc/rockchip/rk3288/timer.c | 1 - src/soc/rockchip/rk3288/tsadc.c | 1 - src/soc/rockchip/rk3399/Makefile.inc | 1 - src/soc/rockchip/rk3399/bootblock.c | 1 - src/soc/rockchip/rk3399/chip.h | 1 - src/soc/rockchip/rk3399/clock.c | 1 - src/soc/rockchip/rk3399/decompressor.c | 1 - src/soc/rockchip/rk3399/display.c | 1 - src/soc/rockchip/rk3399/gpio.c | 1 - src/soc/rockchip/rk3399/include/soc/addressmap.h | 1 - src/soc/rockchip/rk3399/include/soc/clock.h | 1 - src/soc/rockchip/rk3399/include/soc/display.h | 1 - src/soc/rockchip/rk3399/include/soc/grf.h | 1 - src/soc/rockchip/rk3399/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3399/include/soc/mipi.h | 1 - src/soc/rockchip/rk3399/include/soc/mmu_operations.h | 1 - src/soc/rockchip/rk3399/include/soc/saradc.h | 1 - src/soc/rockchip/rk3399/include/soc/sdram.h | 1 - src/soc/rockchip/rk3399/include/soc/symbols.h | 1 - src/soc/rockchip/rk3399/include/soc/timer.h | 1 - src/soc/rockchip/rk3399/include/soc/tsadc.h | 1 - src/soc/rockchip/rk3399/include/soc/usb.h | 1 - src/soc/rockchip/rk3399/mipi.c | 1 - src/soc/rockchip/rk3399/saradc.c | 1 - src/soc/rockchip/rk3399/sdram.c | 1 - src/soc/rockchip/rk3399/soc.c | 1 - src/soc/rockchip/rk3399/spi_bitbang.c | 1 - src/soc/rockchip/rk3399/timer.c | 1 - src/soc/rockchip/rk3399/tsadc.c | 1 - src/soc/rockchip/rk3399/usb.c | 1 - src/soc/samsung/exynos5250/alternate_cbfs.c | 1 - src/soc/samsung/exynos5250/bootblock.c | 1 - src/soc/samsung/exynos5250/cbmem.c | 1 - src/soc/samsung/exynos5250/chip.h | 1 - src/soc/samsung/exynos5250/clock.c | 1 - src/soc/samsung/exynos5250/clock_init.c | 1 - src/soc/samsung/exynos5250/cpu.c | 2 -- src/soc/samsung/exynos5250/dmc_common.c | 1 - src/soc/samsung/exynos5250/dmc_init_ddr3.c | 1 - src/soc/samsung/exynos5250/dp-reg.c | 1 - src/soc/samsung/exynos5250/fb.c | 2 -- src/soc/samsung/exynos5250/gpio.c | 1 - src/soc/samsung/exynos5250/i2c.c | 1 - src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h | 1 - src/soc/samsung/exynos5250/include/soc/clk.h | 2 -- src/soc/samsung/exynos5250/include/soc/cpu.h | 1 - src/soc/samsung/exynos5250/include/soc/dp-core.h | 2 -- src/soc/samsung/exynos5250/include/soc/dp.h | 2 -- src/soc/samsung/exynos5250/include/soc/dsim.h | 1 - src/soc/samsung/exynos5250/include/soc/fimd.h | 1 - src/soc/samsung/exynos5250/include/soc/gpio.h | 1 - src/soc/samsung/exynos5250/include/soc/i2c.h | 1 - src/soc/samsung/exynos5250/include/soc/i2s-regs.h | 1 - src/soc/samsung/exynos5250/include/soc/memlayout.ld | 1 - src/soc/samsung/exynos5250/include/soc/periph.h | 1 - src/soc/samsung/exynos5250/include/soc/pinmux.h | 1 - src/soc/samsung/exynos5250/include/soc/power.h | 1 - src/soc/samsung/exynos5250/include/soc/setup.h | 1 - src/soc/samsung/exynos5250/include/soc/spi.h | 1 - src/soc/samsung/exynos5250/include/soc/sysreg.h | 1 - src/soc/samsung/exynos5250/include/soc/tmu.h | 1 - src/soc/samsung/exynos5250/include/soc/trustzone.h | 1 - src/soc/samsung/exynos5250/include/soc/uart.h | 2 -- src/soc/samsung/exynos5250/include/soc/usb.h | 1 - src/soc/samsung/exynos5250/include/soc/wakeup.h | 1 - src/soc/samsung/exynos5250/pinmux.c | 1 - src/soc/samsung/exynos5250/power.c | 1 - src/soc/samsung/exynos5250/spi.c | 2 -- src/soc/samsung/exynos5250/timer.c | 1 - src/soc/samsung/exynos5250/tmu.c | 2 -- src/soc/samsung/exynos5250/trustzone.c | 2 -- src/soc/samsung/exynos5250/uart.c | 1 - src/soc/samsung/exynos5250/usb.c | 2 -- src/soc/samsung/exynos5250/wakeup.c | 1 - src/soc/samsung/exynos5420/alternate_cbfs.c | 1 - src/soc/samsung/exynos5420/bootblock.c | 1 - src/soc/samsung/exynos5420/cbmem.c | 1 - src/soc/samsung/exynos5420/chip.h | 1 - src/soc/samsung/exynos5420/clock.c | 1 - src/soc/samsung/exynos5420/clock_init.c | 1 - src/soc/samsung/exynos5420/cpu.c | 2 -- src/soc/samsung/exynos5420/dmc_common.c | 1 - src/soc/samsung/exynos5420/dmc_init_ddr3.c | 1 - src/soc/samsung/exynos5420/dp.c | 1 - src/soc/samsung/exynos5420/dp_lowlevel.c | 1 - src/soc/samsung/exynos5420/fimd.c | 2 -- src/soc/samsung/exynos5420/gpio.c | 1 - src/soc/samsung/exynos5420/i2c.c | 2 -- src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h | 1 - src/soc/samsung/exynos5420/include/soc/clk.h | 2 -- src/soc/samsung/exynos5420/include/soc/cpu.h | 1 - src/soc/samsung/exynos5420/include/soc/dp.h | 2 -- src/soc/samsung/exynos5420/include/soc/dsim.h | 1 - src/soc/samsung/exynos5420/include/soc/fimd.h | 1 - src/soc/samsung/exynos5420/include/soc/gpio.h | 1 - src/soc/samsung/exynos5420/include/soc/i2c.h | 1 - src/soc/samsung/exynos5420/include/soc/i2s-regs.h | 1 - src/soc/samsung/exynos5420/include/soc/memlayout.ld | 1 - src/soc/samsung/exynos5420/include/soc/periph.h | 1 - src/soc/samsung/exynos5420/include/soc/pinmux.h | 1 - src/soc/samsung/exynos5420/include/soc/power.h | 1 - src/soc/samsung/exynos5420/include/soc/setup.h | 1 - src/soc/samsung/exynos5420/include/soc/spi.h | 1 - src/soc/samsung/exynos5420/include/soc/sysreg.h | 1 - src/soc/samsung/exynos5420/include/soc/tmu.h | 1 - src/soc/samsung/exynos5420/include/soc/trustzone.h | 1 - src/soc/samsung/exynos5420/include/soc/uart.h | 2 -- src/soc/samsung/exynos5420/include/soc/usb.h | 1 - src/soc/samsung/exynos5420/include/soc/wakeup.h | 1 - src/soc/samsung/exynos5420/pinmux.c | 1 - src/soc/samsung/exynos5420/power.c | 1 - src/soc/samsung/exynos5420/smp.c | 2 -- src/soc/samsung/exynos5420/spi.c | 2 -- src/soc/samsung/exynos5420/timer.c | 1 - src/soc/samsung/exynos5420/tmu.c | 2 -- src/soc/samsung/exynos5420/trustzone.c | 2 -- src/soc/samsung/exynos5420/uart.c | 1 - src/soc/samsung/exynos5420/usb.c | 2 -- src/soc/samsung/exynos5420/wakeup.c | 1 - src/soc/sifive/fu540/Kconfig | 1 - src/soc/sifive/fu540/Makefile.inc | 1 - src/soc/sifive/fu540/bootblock.c | 1 - src/soc/sifive/fu540/cbmem.c | 1 - src/soc/sifive/fu540/clint.c | 1 - src/soc/sifive/fu540/clock.c | 1 - src/soc/sifive/fu540/ddrregs.h | 1 - src/soc/sifive/fu540/include/soc/addressmap.h | 1 - src/soc/sifive/fu540/include/soc/clock.h | 1 - src/soc/sifive/fu540/include/soc/memlayout.ld | 1 - src/soc/sifive/fu540/include/soc/otp.h | 1 - src/soc/sifive/fu540/include/soc/sdram.h | 1 - src/soc/sifive/fu540/include/soc/spi.h | 1 - src/soc/sifive/fu540/otp.c | 1 - src/soc/sifive/fu540/regconfig-ctl.h | 1 - src/soc/sifive/fu540/regconfig-phy.h | 1 - src/soc/sifive/fu540/sdram.c | 1 - src/soc/sifive/fu540/spi.c | 2 -- src/soc/sifive/fu540/spi_internal.h | 1 - src/soc/sifive/fu540/uart.c | 1 - src/soc/sifive/fu540/ux00ddr.h | 1 - 1698 files changed, 2346 deletions(-) diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 8185c35ac5..f2963104c3 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl index 93b405619d..a2b28d2805 100644 --- a/src/soc/amd/common/acpi/lpc.asl +++ b/src/soc/amd/common/acpi/lpc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index e18933bb81..6f2f7c5ad7 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 202e47ac10..cb5730dbd5 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/alink/alink.c b/src/soc/amd/common/block/alink/alink.c index f80d769037..3a1e2bf842 100644 --- a/src/soc/amd/common/block/alink/alink.c +++ b/src/soc/amd/common/block/alink/alink.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/cpu/car/ap_exit_car.S b/src/soc/amd/common/block/cpu/car/ap_exit_car.S index 5d3e13b1a2..756e31f3ac 100644 --- a/src/soc/amd/common/block/cpu/car/ap_exit_car.S +++ b/src/soc/amd/common/block/cpu/car/ap_exit_car.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 78c672a887..528159df5b 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index 16880e71a5..6eea7fc418 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 76c2021578..a56fe42f9e 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index c24e32d6be..76ce9e370b 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 920549981e..5736ed47d9 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011,2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index cf266ed7d8..44eb903030 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index b4a4b50a29..a2ac5e31fc 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 4d62b39080..3e28c33357 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 04db4242cf..a74a3d6560 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/alink.h b/src/soc/amd/common/block/include/amdblocks/alink.h index a6f748b809..48b3dc2b86 100644 --- a/src/soc/amd/common/block/include/amdblocks/alink.h +++ b/src/soc/amd/common/block/include/amdblocks/alink.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 3a55244bc7..4cf87cb07b 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/car.h b/src/soc/amd/common/block/include/amdblocks/car.h index 6c4049b6bf..57b19380fa 100644 --- a/src/soc/amd/common/block/include/amdblocks/car.h +++ b/src/soc/amd/common/block/include/amdblocks/car.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h index 1ce6d86fa7..6d678afcf0 100644 --- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h +++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 8600e64fcc..6589e7a6cc 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/image.h b/src/soc/amd/common/block/include/amdblocks/image.h index ccfcac5a5d..8b08c72fc4 100644 --- a/src/soc/amd/common/block/include/amdblocks/image.h +++ b/src/soc/amd/common/block/include/amdblocks/image.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Silverback, ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 2f8cd971f1..c7ccc08e1c 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 512b0b8c04..b730293bb5 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index 4f149eadb9..124f2347bf 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 9323baf6aa..1a5f1f4ccd 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h index 2a21436525..cafd343c01 100644 --- a/src/soc/amd/common/block/include/amdblocks/sata.h +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 18c8e665ad..18d9105959 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 628273dd35..ff7d561457 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index cdf36b2988..39f5d265e7 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c index 7a40d262eb..6e7de8d50b 100644 --- a/src/soc/amd/common/block/pci/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 45842168de..7afece26f3 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2018 - 2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index f2b4ed1d0d..cceeaef50c 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c index 363ba83a0f..4561db0e92 100644 --- a/src/soc/amd/common/block/pi/amd_resume_final.c +++ b/src/soc/amd/common/block/pi/amd_resume_final.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index facd5f8c0f..ce615bdf19 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/pi/image.c b/src/soc/amd/common/block/pi/image.c index dca1963666..38a20898cb 100644 --- a/src/soc/amd/common/block/pi/image.c +++ b/src/soc/amd/common/block/pi/image.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Silverback, ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 3ffaf36485..00d249dc02 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 723b279aa3..cf25fd1b51 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index a0de406d38..69be4a6af5 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012-2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 5aa20887dd..90f63728a8 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 6ecf1cd998..e118cb8384 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index 5474c5cd45..c9f065ab94 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 0a629a3213..b298c378f6 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Silverback Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e19375567e..a7423e907a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 89fd5c4c39..48f65078ac 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -1,8 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc. -# 2013 - 2014 Sage Electronic Engineering, LLC -# All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index ad5333a266..b0c7b0fbb3 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 7b70ec6be4..e8bbf57fab 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/acpi_wake_source.asl b/src/soc/amd/picasso/acpi/acpi_wake_source.asl index fa01802618..a5440e8e51 100644 --- a/src/soc/amd/picasso/acpi/acpi_wake_source.asl +++ b/src/soc/amd/picasso/acpi/acpi_wake_source.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 414326ecf1..59ac62e1ec 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index a373a99e7d..6192922ccd 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 208ea261f5..c7712a6c86 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 617b9eb86c..13e195a7f7 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index 925187209c..ba964fd00a 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index ca8d175c61..9276fc78a2 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index bd340dd4bb..46bcc7aae0 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl index c5e979e268..16c8bf24a4 100644 --- a/src/soc/amd/picasso/acpi/sleepstates.asl +++ b/src/soc/amd/picasso/acpi/sleepstates.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index 52c7ee6c00..c5cc419b65 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl index 2af0c1a794..5c5291928e 100644 --- a/src/soc/amd/picasso/acpi/usb.asl +++ b/src/soc/amd/picasso/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index cf02030391..a7b0c26335 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 4e9e18b984..aa27cd382b 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 66dfa6cfa4..403b15b894 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017-2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 5ea52c6eaf..91cc5c26b6 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index ea868ebd02..51cde5b7be 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 408b60b315..5e5db9e8ed 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 25b1d66af1..c3c0933c61 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index fe839e8314..5f4f195edb 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 338e8718e9..2bcffdc320 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 42d255172e..2c2f83de31 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index d129fc1f1f..8bc3254429 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index b1d4bff48c..6eaff8e13f 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Raptor Engineering, LLC - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 9c7419a997..22de453ac0 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 1c02bb7e87..d0ed799b6a 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index acde4558b1..2b72fe7375 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index c0d03d0ead..1669b7582c 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index e7f9da6d9c..e890e1319a 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2019 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index cbf95b9b16..0518b8ac61 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 57fa9c6536..122c751e0b 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index ae5a331259..304b81d311 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 282f9628ea..7be5aef324 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/pmutil.c b/src/soc/amd/picasso/pmutil.c index 59de34890f..e5a5b5cdc4 100644 --- a/src/soc/amd/picasso/pmutil.c +++ b/src/soc/amd/picasso/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 98410387fb..5c62a4990f 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c index d67f5b4a9b..18a5593cf7 100644 --- a/src/soc/amd/picasso/sata.c +++ b/src/soc/amd/picasso/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index b11eda6360..ab8f405e59 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 8759e2acb1..9e0c85a129 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index d987a5056e..55493776dd 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 56fe88de3c..1894bea418 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 6167726955..dd786e3f05 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Advanced Micro Devices * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index c50de464c7..cdeb493711 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index faea3c3af8..fed1c9b64d 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 2ee92786ee..0c5af35ef5 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 7d69a92158..14615888e3 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 0cc49c8568..96b8303a1c 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -1,8 +1,5 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc. -# 2013 - 2014 Sage Electronic Engineering, LLC -# All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 13020ed1da..01849b85a0 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl b/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl index fa01802618..a5440e8e51 100644 --- a/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl +++ b/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 94638b043d..f52d230bf2 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 03d205f8d3..abdee34311 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 208ea261f5..c7712a6c86 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index 617b9eb86c..13e195a7f7 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/pcie.asl b/src/soc/amd/stoneyridge/acpi/pcie.asl index 925187209c..ba964fd00a 100644 --- a/src/soc/amd/stoneyridge/acpi/pcie.asl +++ b/src/soc/amd/stoneyridge/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 897c9ec905..0e30e07676 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 3623814080..e5c6bb6e8e 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index c5e979e268..16c8bf24a4 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index 52c7ee6c00..c5cc419b65 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index f2ee8f6427..f06e04d9bf 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 9920aff082..186f77c646 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. - * Copyright (C) 2017 Advanced Micro Devices * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 7221f955f6..aa3c322813 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index fedb3e9cd0..c78663330a 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index d7823934d6..c2910a28be 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 5e623e8ab0..83d8357549 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 5ea52c6eaf..91cc5c26b6 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index f63a0d93a4..853ff95d8e 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 7f65a4f3f3..e5c2d98736 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 15a41edce6..02a1315aff 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index beef2bcc81..cb2ecb52b7 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index 934a9f2983..cbae3dab01 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index d8774f051a..90447a96db 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 62575d0fb8..68e2ae5b16 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 02997cc777..479964ee20 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Raptor Engineering, LLC - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 5694779fb5..f39bc24209 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 08d46973c0..12f71be192 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 01a0b7cd8b..65a59cf8dd 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 598b409ba5..89f714df72 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 5301dd72a0..aaf767203f 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 0555afbba8..45bad1fb55 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 8a875d9206..8917204764 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index ae5a331259..304b81d311 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/monotonic_timer.c b/src/soc/amd/stoneyridge/monotonic_timer.c index 7ea571f635..2211136ce2 100644 --- a/src/soc/amd/stoneyridge/monotonic_timer.c +++ b/src/soc/amd/stoneyridge/monotonic_timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index cd78ff83a2..afe7cf0420 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index 59de34890f..e5a5b5cdc4 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index ec5ee910d9..0013a63a96 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 25eb4a1ce2..0a209b0260 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index d67f5b4a9b..18a5593cf7 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index b588579e52..a8c20132b5 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index b11eda6360..ab8f405e59 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 8759e2acb1..9e0c85a129 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index aa2a15bf14..98fe94d1b0 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Alexandru Gagniuc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7732fc937a..71b2d90a2c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 29121b955e..aca7c2323a 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Advanced Micro Devices * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index d5d30061bf..268a479c93 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 3c621910e2..10aba3a573 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index ece705fd92..9149075660 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/bl31_plat_params.c b/src/soc/cavium/cn81xx/bl31_plat_params.c index 661f3efb85..b7bf02d5ee 100644 --- a/src/soc/cavium/cn81xx/bl31_plat_params.c +++ b/src/soc/cavium/cn81xx/bl31_plat_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c index 64728daf8f..d65fbe520d 100644 --- a/src/soc/cavium/cn81xx/bootblock.c +++ b/src/soc/cavium/cn81xx/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index 2f503c827b..887831f6af 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -1,8 +1,6 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2016 Cavium, Inc. - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 284608c3a7..44f579182e 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. - * Copyright 2019 9Elements GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/chip.h b/src/soc/cavium/cn81xx/chip.h index 9716a5da6a..2facbfa4d4 100644 --- a/src/soc/cavium/cn81xx/chip.h +++ b/src/soc/cavium/cn81xx/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/clock.c b/src/soc/cavium/cn81xx/clock.c index 452574030a..b7eb9cd748 100644 --- a/src/soc/cavium/cn81xx/clock.c +++ b/src/soc/cavium/cn81xx/clock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index 6c1d006cf1..f422e4c284 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/cpu_secondary.S b/src/soc/cavium/cn81xx/cpu_secondary.S index d4b4d3cd9b..324b96fdc5 100644 --- a/src/soc/cavium/cn81xx/cpu_secondary.S +++ b/src/soc/cavium/cn81xx/cpu_secondary.S @@ -1,8 +1,6 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2016 Cavium, Inc. - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 6659cdf3bc..1f2ba843c6 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/gpio.c b/src/soc/cavium/cn81xx/gpio.c index 676e953a56..356db01372 100644 --- a/src/soc/cavium/cn81xx/gpio.c +++ b/src/soc/cavium/cn81xx/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/atf/plat_params.h b/src/soc/cavium/cn81xx/include/atf/plat_params.h index 93b970b352..e76ae7fa6e 100644 --- a/src/soc/cavium/cn81xx/include/atf/plat_params.h +++ b/src/soc/cavium/cn81xx/include/atf/plat_params.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2018 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index 3fb4c9c3e4..7d6d9bb49a 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h index e47de899e4..2fd886ffd8 100644 --- a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h +++ b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/clock.h b/src/soc/cavium/cn81xx/include/soc/clock.h index d436c121cb..3889d6f8f7 100644 --- a/src/soc/cavium/cn81xx/include/soc/clock.h +++ b/src/soc/cavium/cn81xx/include/soc/clock.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h index 7d3647bda0..4898e31b70 100644 --- a/src/soc/cavium/cn81xx/include/soc/cpu.h +++ b/src/soc/cavium/cn81xx/include/soc/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/ecam0.h b/src/soc/cavium/cn81xx/include/soc/ecam0.h index 1cc249d92d..2244a0a3a2 100644 --- a/src/soc/cavium/cn81xx/include/soc/ecam0.h +++ b/src/soc/cavium/cn81xx/include/soc/ecam0.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/gpio.h b/src/soc/cavium/cn81xx/include/soc/gpio.h index 6986482f79..7d85794a1c 100644 --- a/src/soc/cavium/cn81xx/include/soc/gpio.h +++ b/src/soc/cavium/cn81xx/include/soc/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 1a0eb155b7..74786693db 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/mmu.h b/src/soc/cavium/cn81xx/include/soc/mmu.h index 9b811c3966..d752738faa 100644 --- a/src/soc/cavium/cn81xx/include/soc/mmu.h +++ b/src/soc/cavium/cn81xx/include/soc/mmu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/sdram.h b/src/soc/cavium/cn81xx/include/soc/sdram.h index 5a3e5196b5..199ba6a150 100644 --- a/src/soc/cavium/cn81xx/include/soc/sdram.h +++ b/src/soc/cavium/cn81xx/include/soc/sdram.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/soc.h b/src/soc/cavium/cn81xx/include/soc/soc.h index 582cff3e29..632e38e459 100644 --- a/src/soc/cavium/cn81xx/include/soc/soc.h +++ b/src/soc/cavium/cn81xx/include/soc/soc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/spi.h b/src/soc/cavium/cn81xx/include/soc/spi.h index 33f0f2988b..3d874208d8 100644 --- a/src/soc/cavium/cn81xx/include/soc/spi.h +++ b/src/soc/cavium/cn81xx/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 5e6673e0ea..2f4f7dba1d 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/twsi.h b/src/soc/cavium/cn81xx/include/soc/twsi.h index 6c5211e63b..8365591e9b 100644 --- a/src/soc/cavium/cn81xx/include/soc/twsi.h +++ b/src/soc/cavium/cn81xx/include/soc/twsi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/include/soc/uart.h b/src/soc/cavium/cn81xx/include/soc/uart.h index baa06e1f89..55c760d59d 100644 --- a/src/soc/cavium/cn81xx/include/soc/uart.h +++ b/src/soc/cavium/cn81xx/include/soc/uart.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/mmu.c b/src/soc/cavium/cn81xx/mmu.c index 17b43e77ee..7815b2522c 100644 --- a/src/soc/cavium/cn81xx/mmu.c +++ b/src/soc/cavium/cn81xx/mmu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c index 71d6b48dbd..1d686b9dd3 100644 --- a/src/soc/cavium/cn81xx/sdram.c +++ b/src/soc/cavium/cn81xx/sdram.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. - * Copyright 2019 9elements Agency GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 8abb328ba8..02b7da6140 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 6a5abb131a..09f27a488f 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index be15b9be8e..51b4f393a4 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c index afa98c6adc..a0ff3bb444 100644 --- a/src/soc/cavium/cn81xx/twsi.c +++ b/src/soc/cavium/cn81xx/twsi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c index 8a21f00a70..6e88bd1748 100644 --- a/src/soc/cavium/cn81xx/uart.c +++ b/src/soc/cavium/cn81xx/uart.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc index 766c44db63..71255c33e3 100644 --- a/src/soc/cavium/common/Makefile.inc +++ b/src/soc/cavium/common/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2017-present Facebook, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index 740f8e442f..e58eda3007 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-present Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index 0c3b367891..5be06c4995 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index 89c69dbc2e..0ea7c79464 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Facebook, Inc. - * Copyright 2003-2017 Cavium Inc. - * Copyright 2019 9elements Agency GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h index 1df444fad2..6f966efc97 100644 --- a/src/soc/cavium/common/include/soc/bootblock.h +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/cavium/common/include/soc/ecam.h b/src/soc/cavium/common/include/soc/ecam.h index 16e3d27a62..7628cfae6f 100644 --- a/src/soc/cavium/common/include/soc/ecam.h +++ b/src/soc/cavium/common/include/soc/ecam.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. - * Copyright 2019 9elements Agency GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/common/include/soc/sysreg.h b/src/soc/cavium/common/include/soc/sysreg.h index 655fe09cb6..9bad8cbac4 100644 --- a/src/soc/cavium/common/include/soc/sysreg.h +++ b/src/soc/cavium/common/include/soc/sysreg.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. - * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/cavium/common/pci/chip.h b/src/soc/cavium/common/pci/chip.h index 0d0d33f59d..d84c9277bf 100644 --- a/src/soc/cavium/common/pci/chip.h +++ b/src/soc/cavium/common/pci/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-present Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/cavium/common/pci/uart.c b/src/soc/cavium/common/pci/uart.c index ff002ea5ec..87928713b2 100644 --- a/src/soc/cavium/common/pci/uart.c +++ b/src/soc/cavium/common/pci/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 9Elements GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 46c7b6ce0a..82ef3f1d38 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2020 Intel Corp. - * Copyright (C) 2017-2019 Siemens AG - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/dptf.asl b/src/soc/intel/apollolake/acpi/dptf.asl index f34725f92d..ffbf9137ca 100644 --- a/src/soc/intel/apollolake/acpi/dptf.asl +++ b/src/soc/intel/apollolake/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 1db373d484..8d105c37d0 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2020 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index de556e08d8..c26c04a1c2 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl index 960993a835..a4ab9135c5 100644 --- a/src/soc/intel/apollolake/acpi/gpiolib.asl +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl index ab97374ddb..67774fd507 100644 --- a/src/soc/intel/apollolake/acpi/lpss.asl +++ b/src/soc/intel/apollolake/acpi/lpss.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index ff146ec9db..65eb4d64f9 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2020 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl index 0964448593..c140bf6f12 100644 --- a/src/soc/intel/apollolake/acpi/pch_hda.asl +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. - * Copyright (C) 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index d1402d9651..d91f743d07 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl index 539ae9b71e..d4cb02bf37 100644 --- a/src/soc/intel/apollolake/acpi/pcie.asl +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/pcie_port.asl b/src/soc/intel/apollolake/acpi/pcie_port.asl index d06336cb06..84e256536c 100644 --- a/src/soc/intel/apollolake/acpi/pcie_port.asl +++ b/src/soc/intel/apollolake/acpi/pcie_port.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl index f3202a0c48..e445f01bc9 100644 --- a/src/soc/intel/apollolake/acpi/platform.asl +++ b/src/soc/intel/apollolake/acpi/platform.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2016 Intel Corp * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 5c53af4cd9..12c4c6e985 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index b15d278adb..b3b975a2b3 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 11b5460c19..f8d0876fbd 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 9acb9aeb03..297038f755 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index a7317fe82b..52ef7bf3b5 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl index ebb3e8cd99..2991512653 100644 --- a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl +++ b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC. - * Copyright 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl index e3b045cc2a..64e2d80bd9 100644 --- a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl +++ b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC. - * Copyright 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index a07c4620af..df3eb374fc 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 9f75c7e15c..790f5a7091 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 4eabf8a012..178ccac066 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. - * Copyright (C) 2017 - 2019 Siemens AG - * (Written by Alexandru Gagniuc for Intel Corp.) - * (Written by Andrey Petrov for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 40cd39b46b..c7974a6cd5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 - 2018 Siemens AG - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 0b9466c4c5..cd21fde048 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Intel Corp. - * Copyright (C) 2017-2019 Siemens AG - * (Written by Andrey Petrov for Intel Corp.) - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 2445289385..080b2c277b 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 02afb6c5cc..f019c1ee97 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index 40bacd7ad2..7ec1ebb703 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index 10b7ba635b..b106fc3287 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index 014751905f..2675ed6d41 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index f5136ec103..033b30046d 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c index 5e52548e90..56d8047b72 100644 --- a/src/soc/intel/apollolake/gspi.c +++ b/src/soc/intel/apollolake/gspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/heci.c b/src/soc/intel/apollolake/heci.c index 000fe237bd..bfe7eb5772 100644 --- a/src/soc/intel/apollolake/heci.c +++ b/src/soc/intel/apollolake/heci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/i2c.c b/src/soc/intel/apollolake/i2c.c index bf378bce34..ec5424e798 100644 --- a/src/soc/intel/apollolake/i2c.c +++ b/src/soc/intel/apollolake/i2c.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 4a1a7a438c..359d4b50ab 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 53afb03896..32a9b565ab 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 939c449159..6f71e7fab2 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/gpio_apl.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h index ecd9101e76..9c02b50fff 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_apl.h +++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h @@ -6,8 +6,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h index 54ce952609..d704757346 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_glk.h +++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h @@ -5,7 +5,6 @@ * * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h index 26d0ea9c77..673580fe63 100644 --- a/src/soc/intel/apollolake/include/soc/heci.h +++ b/src/soc/intel/apollolake/include/soc/heci.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index e2fa46299e..b06a9e1bad 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2020 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/itss.h b/src/soc/intel/apollolake/include/soc/itss.h index e61f2d224a..dec6b53104 100644 --- a/src/soc/intel/apollolake/include/soc/itss.h +++ b/src/soc/intel/apollolake/include/soc/itss.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/me.h b/src/soc/intel/apollolake/include/soc/me.h index e1916f622e..529240d0ac 100644 --- a/src/soc/intel/apollolake/include/soc/me.h +++ b/src/soc/intel/apollolake/include/soc/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index d75a4873b0..6c0f36609f 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h index 226fc8a23d..036efa260e 100644 --- a/src/soc/intel/apollolake/include/soc/nhlt.h +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 9cdeee1ad2..79fe1d868a 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2020 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h index 01ba7ffd24..8bd1122a5f 100644 --- a/src/soc/intel/apollolake/include/soc/p2sb.h +++ b/src/soc/intel/apollolake/include/soc/p2sb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index d591c21b58..8821c96fdd 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 510dd03da7..b3ee7a0d49 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/pnpconfig.h b/src/soc/intel/apollolake/include/soc/pnpconfig.h index e592e86ec7..883fed0ef9 100644 --- a/src/soc/intel/apollolake/include/soc/pnpconfig.h +++ b/src/soc/intel/apollolake/include/soc/pnpconfig.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h index 287f2ff945..3fc0639453 100644 --- a/src/soc/intel/apollolake/include/soc/ramstage.h +++ b/src/soc/intel/apollolake/include/soc/ramstage.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * Copyright (C) 2019 9elements Agency GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index 3466abe9ce..486f963856 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 965e8bc264..9288934a11 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/soc_chip.h b/src/soc/intel/apollolake/include/soc/soc_chip.h index fa53a15906..e83f0e71dd 100644 --- a/src/soc/intel/apollolake/include/soc/soc_chip.h +++ b/src/soc/intel/apollolake/include/soc/soc_chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index 46c1d7d9c7..5238b9357c 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 11dec48eb6..6f42e18de6 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. - * (Written by Kane Chen for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 636dd03a3e..20a6ce510a 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 219b661042..2371615681 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index 1dc5ceeb2c..aac34b35c8 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 0fbab0b177..86045792f1 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 611b0a7d4f..b7530576c8 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c index 8a3cfac203..bf19b2feee 100644 --- a/src/soc/intel/apollolake/nhlt.c +++ b/src/soc/intel/apollolake/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/pdpt.c b/src/soc/intel/apollolake/pdpt.c index 38852f1365..674b369c9f 100644 --- a/src/soc/intel/apollolake/pdpt.c +++ b/src/soc/intel/apollolake/pdpt.c @@ -1,5 +1,4 @@ /* - * Copyright 2018 Generated Code * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 286cd8a286..3afb8725ca 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 4a08827c1c..3d0d4593dd 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c index 274f630a71..cb0b9dae11 100644 --- a/src/soc/intel/apollolake/pnpconfig.c +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/pt.c b/src/soc/intel/apollolake/pt.c index bd86f77974..fbbad63aa0 100644 --- a/src/soc/intel/apollolake/pt.c +++ b/src/soc/intel/apollolake/pt.c @@ -1,5 +1,4 @@ /* - * Copyright 2018 Generated Code * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c index 6f4c74ebf5..37501b7efb 100644 --- a/src/soc/intel/apollolake/report_platform.c +++ b/src/soc/intel/apollolake/report_platform.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 36bf77b240..80f1365f36 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 05cd0db401..eff7f04506 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * (Written by Andrey Petrov for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c index e34d53ed21..9626dccb22 100644 --- a/src/soc/intel/apollolake/sd.c +++ b/src/soc/intel/apollolake/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 073d66590d..83cd5e64b4 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index b85d6b134f..4fa8062f6a 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright 2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index fd9108208c..a1b6b4d2a5 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * (Written by Alexandru Gagniuc for Intel Corp.) - * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index f8c4aafec2..ea1c1cbb71 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c index 0a85f2651c..0f5a02eccf 100644 --- a/src/soc/intel/apollolake/xdci.c +++ b/src/soc/intel/apollolake/xdci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c index 131610756f..1b9f932d73 100644 --- a/src/soc/intel/apollolake/xhci.c +++ b/src/soc/intel/apollolake/xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 77cc21bb91..c9ccdbdbf6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl index 54978cd2c0..fb190874a2 100644 --- a/src/soc/intel/baytrail/acpi/device_nvs.asl +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index a8b0f53719..763fa0e66f 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/gpio.asl b/src/soc/intel/baytrail/acpi/gpio.asl index 76e154dc21..d99323d0d4 100644 --- a/src/soc/intel/baytrail/acpi/gpio.asl +++ b/src/soc/intel/baytrail/acpi/gpio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/irq_helper.h b/src/soc/intel/baytrail/acpi/irq_helper.h index 9198833fdf..11b0f0a5db 100644 --- a/src/soc/intel/baytrail/acpi/irq_helper.h +++ b/src/soc/intel/baytrail/acpi/irq_helper.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/acpi/irqlinks.asl b/src/soc/intel/baytrail/acpi/irqlinks.asl index 2d029242d8..0bfdbdedad 100644 --- a/src/soc/intel/baytrail/acpi/irqlinks.asl +++ b/src/soc/intel/baytrail/acpi/irqlinks.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/irqroute.asl b/src/soc/intel/baytrail/acpi/irqroute.asl index ae0058b5a1..2f8e62e977 100644 --- a/src/soc/intel/baytrail/acpi/irqroute.asl +++ b/src/soc/intel/baytrail/acpi/irqroute.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 7cdf1aa5d0..dc2b663f89 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/lpe.asl b/src/soc/intel/baytrail/acpi/lpe.asl index 1f13fe56e9..f75d1b880b 100644 --- a/src/soc/intel/baytrail/acpi/lpe.asl +++ b/src/soc/intel/baytrail/acpi/lpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl index 6473a78419..e8bf01cd60 100644 --- a/src/soc/intel/baytrail/acpi/lpss.asl +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/pcie.asl b/src/soc/intel/baytrail/acpi/pcie.asl index fccbb3eb19..2ae3d965e4 100644 --- a/src/soc/intel/baytrail/acpi/pcie.asl +++ b/src/soc/intel/baytrail/acpi/pcie.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index 885a7d57f2..7b6da44201 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/acpi/scc.asl b/src/soc/intel/baytrail/acpi/scc.asl index c26511c751..2f6dc9accd 100644 --- a/src/soc/intel/baytrail/acpi/scc.asl +++ b/src/soc/intel/baytrail/acpi/scc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 4465c222b0..286826c563 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index d3c0083c2f..4261a57c99 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b5a786bdf5..5a697bc1d6 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 6f0d98acbe..f65d4f251c 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index f153913a0f..0fa7eafe87 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 90e045c718..701a4e6a94 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 3815c34299..e7cd7d8ff1 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 9082feaa16..6b759f2f90 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index d7a0460816..5b4e35f064 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index a99fe5a424..8994e43af8 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index bb83e337c4..417f36e907 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 3460a5f049..0bf9e60c40 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index ff69be5553..e8be1e2327 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index 2851f9201b..fbdf030608 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index 74e312a858..cc9bc658ad 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/efi_wrapper.h b/src/soc/intel/baytrail/include/soc/efi_wrapper.h index d362494638..acff4b4f6f 100644 --- a/src/soc/intel/baytrail/include/soc/efi_wrapper.h +++ b/src/soc/intel/baytrail/include/soc/efi_wrapper.h @@ -1,7 +1,6 @@ /* * PEI EFI entry point * - * Copyright 2013 Google Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/src/soc/intel/baytrail/include/soc/ehci.h b/src/soc/intel/baytrail/include/soc/ehci.h index fe990b7017..56a7705684 100644 --- a/src/soc/intel/baytrail/include/soc/ehci.h +++ b/src/soc/intel/baytrail/include/soc/ehci.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/gfx.h b/src/soc/intel/baytrail/include/soc/gfx.h index f41354bb06..00d709d139 100644 --- a/src/soc/intel/baytrail/include/soc/gfx.h +++ b/src/soc/intel/baytrail/include/soc/gfx.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 2fed005c90..d6be80fde2 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/iomap.h b/src/soc/intel/baytrail/include/soc/iomap.h index 11c01e311d..644c07c746 100644 --- a/src/soc/intel/baytrail/include/soc/iomap.h +++ b/src/soc/intel/baytrail/include/soc/iomap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 436cc33477..29cf26d242 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index 5c64da4b9e..d92b9234c1 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/lpc.h b/src/soc/intel/baytrail/include/soc/lpc.h index b3fa6de98d..2c06bccaec 100644 --- a/src/soc/intel/baytrail/include/soc/lpc.h +++ b/src/soc/intel/baytrail/include/soc/lpc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h index d7f4483820..8651aa4098 100644 --- a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h +++ b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h @@ -1,7 +1,6 @@ /* * MRC wrapper definitions * - * Copyright 2013 Google Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 825e7f2372..474e75a7a7 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 8532728503..49cb03d5e6 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index 7b46345a47..a5c9b16641 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h index 71a0e53ce1..88bedb9642 100644 --- a/src/soc/intel/baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/baytrail/include/soc/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/pcie.h b/src/soc/intel/baytrail/include/soc/pcie.h index 22e17dc358..873af3cb33 100644 --- a/src/soc/intel/baytrail/include/soc/pcie.h +++ b/src/soc/intel/baytrail/include/soc/pcie.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index 6cdf419042..fc30ad10d5 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index f98a79b2ea..199ea06ced 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index ac323058f1..46bd010a56 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/sata.h b/src/soc/intel/baytrail/include/soc/sata.h index ccf1f4c3b4..b9cd6c32f9 100644 --- a/src/soc/intel/baytrail/include/soc/sata.h +++ b/src/soc/intel/baytrail/include/soc/sata.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/smm.h b/src/soc/intel/baytrail/include/soc/smm.h index a2b7ec02d7..c95289b76d 100644 --- a/src/soc/intel/baytrail/include/soc/smm.h +++ b/src/soc/intel/baytrail/include/soc/smm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h index 1ac0b59e56..2a21e90b68 100644 --- a/src/soc/intel/baytrail/include/soc/spi.h +++ b/src/soc/intel/baytrail/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/include/soc/xhci.h b/src/soc/intel/baytrail/include/soc/xhci.h index d509b51a6a..f169acafcd 100644 --- a/src/soc/intel/baytrail/include/soc/xhci.h +++ b/src/soc/intel/baytrail/include/soc/xhci.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index bb5e80cb82..1d51cbb204 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 3fa5459cea..e34af1e2d7 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 4ffdca9d63..71b6dacbb5 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index e0aac9f423..7e8103abf6 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 654d2371e7..d7f17486da 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 6b6c28d731..8cd81a61a7 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 9d92513449..4be6382f1d 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 51174fc130..9e032cebfb 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 769e7ffd2b..6665649a07 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 24469ea3a5..1af829826d 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c index 2d025fc6f1..737beb0ef3 100644 --- a/src/soc/intel/baytrail/romstage/gfx.c +++ b/src/soc/intel/baytrail/romstage/gfx.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 11b3b0f8bc..faa545bd3e 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index c21a0c4acb..df29de762a 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 25cb6617f6..24fff010bf 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 084d7865b4..33fb04316b 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index a6b4fe3f2f..3332fed265 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index dcb20734e3..dd2b61ac7d 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index b8226c29dd..59da24389c 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 9f10f70b61..286cb49082 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index bd61f0821d..746a353051 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index edc31c1e47..df73f80752 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index d9f2c53eaa..ca7ee71e32 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index f68b7ce2da..413b9972d4 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index 0d4bc3cffe..312d2bbe92 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 9625cac5f0..5b91699544 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 7daa36c8d4..397f354d21 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 41f1854d30..caf8648c8c 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl index 05d0cebc7f..5ed5c777c9 100644 --- a/src/soc/intel/braswell/acpi/gpio.asl +++ b/src/soc/intel/braswell/acpi/gpio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/irq_helper.h b/src/soc/intel/braswell/acpi/irq_helper.h index 9198833fdf..11b0f0a5db 100644 --- a/src/soc/intel/braswell/acpi/irq_helper.h +++ b/src/soc/intel/braswell/acpi/irq_helper.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl index a943c88a15..2050695194 100644 --- a/src/soc/intel/braswell/acpi/irqlinks.asl +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl index 2fc9873d49..60c2cc8899 100644 --- a/src/soc/intel/braswell/acpi/irqroute.asl +++ b/src/soc/intel/braswell/acpi/irqroute.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index a8604d6c68..000be38b75 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index 145e6084d9..f4848704d4 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index f9b376ccb3..add7270a5d 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl index fdf27887e5..549bd54abc 100644 --- a/src/soc/intel/braswell/acpi/platform.asl +++ b/src/soc/intel/braswell/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 128edc55d6..1f0f9a42ad 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 4b2deb3ee1..c1807a7c5b 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/acpi/xhci.asl b/src/soc/intel/braswell/acpi/xhci.asl index dbd34474f8..0ace24223f 100644 --- a/src/soc/intel/braswell/acpi/xhci.asl +++ b/src/soc/intel/braswell/acpi/xhci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 53cff31569..11bff97544 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 026b281881..e1918d4e48 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index ae9787b0a8..be95808910 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 4288394808..2d47663e04 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 6efcef1452..b24dff5446 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index aae496a276..23ada25d4b 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 16751fbadd..41b2c6f2a7 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 14f95e1867..2ca023ffe0 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c index 253cfa2674..7dccc7b51b 100644 --- a/src/soc/intel/braswell/gpio_support.c +++ b/src/soc/intel/braswell/gpio_support.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 162f81af15..4999dd7d91 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 1b4f3ba6b2..64bb05e74c 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/ehci.h b/src/soc/intel/braswell/include/soc/ehci.h index 1ae0525023..864bff5817 100644 --- a/src/soc/intel/braswell/include/soc/ehci.h +++ b/src/soc/intel/braswell/include/soc/ehci.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h index c6b802fc42..436b97e065 100644 --- a/src/soc/intel/braswell/include/soc/gfx.h +++ b/src/soc/intel/braswell/include/soc/gfx.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index db8e2a345c..51c8e12ed4 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/gpio_defs.h b/src/soc/intel/braswell/include/soc/gpio_defs.h index c6a3c3be64..b85fc22573 100644 --- a/src/soc/intel/braswell/include/soc/gpio_defs.h +++ b/src/soc/intel/braswell/include/soc/gpio_defs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/hda.h b/src/soc/intel/braswell/include/soc/hda.h index b1b538e2b9..fee65eaf75 100644 --- a/src/soc/intel/braswell/include/soc/hda.h +++ b/src/soc/intel/braswell/include/soc/hda.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h index f49993e6b1..019d5f0a08 100644 --- a/src/soc/intel/braswell/include/soc/iomap.h +++ b/src/soc/intel/braswell/include/soc/iomap.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index f02f07e3a8..5a36d4077d 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index b14d0c06c7..fa51100803 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index 1a56f9e8c1..7945caa893 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index d0bfc8ad4a..90a62d3574 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index f4cd8f2444..67ee369829 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h index d86f9ee98e..76ac54bc29 100644 --- a/src/soc/intel/braswell/include/soc/pattrs.h +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h index 854b858e7f..4bf488e672 100644 --- a/src/soc/intel/braswell/include/soc/pci_devs.h +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/pcie.h b/src/soc/intel/braswell/include/soc/pcie.h index 1515fc25a5..98cf64d02d 100644 --- a/src/soc/intel/braswell/include/soc/pcie.h +++ b/src/soc/intel/braswell/include/soc/pcie.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 744fcf085f..df131538f3 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index 17db2d8f75..aa968b33c1 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index c9b559ac35..cb9b27d825 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/sata.h b/src/soc/intel/braswell/include/soc/sata.h index 9c6cb93f8a..add352c7a7 100644 --- a/src/soc/intel/braswell/include/soc/sata.h +++ b/src/soc/intel/braswell/include/soc/sata.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h index 8bc62f7eec..717c208ddb 100644 --- a/src/soc/intel/braswell/include/soc/smbus.h +++ b/src/soc/intel/braswell/include/soc/smbus.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 68b4cb0025..8e2f3757c2 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 0234021e65..ab4f3202fd 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/include/soc/xhci.h b/src/soc/intel/braswell/include/soc/xhci.h index e05a653186..ef16d242e3 100644 --- a/src/soc/intel/braswell/include/soc/xhci.h +++ b/src/soc/intel/braswell/include/soc/xhci.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 5aa618164c..9d29e8d599 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index 1c89187fd7..bf5807464d 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 58e3492771..12d2858868 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 245fc4ff3f..6bc4065df7 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index e43c5469f6..04e5d7ba03 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index e3e3aa79ff..f8e3391f9e 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 4ae7f3f236..7ab184fd10 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/placeholders.c b/src/soc/intel/braswell/placeholders.c index 503c431620..1175721a2b 100644 --- a/src/soc/intel/braswell/placeholders.c +++ b/src/soc/intel/braswell/placeholders.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 18cb04dd89..f218259b4e 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index f8011fdb73..9b0775e9b7 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 38a0c2e693..1a3100cd02 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index 80031e6907..afd66a0d08 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 5c874e198c..6373cd51f2 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 3816fc46e2..1295ffaddd 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c index a1a0a89598..9ef83a3c39 100644 --- a/src/soc/intel/braswell/smbus.c +++ b/src/soc/intel/braswell/smbus.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * Copyright (C) 2019 3mdeb - * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 31b059c545..584ec88d46 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index c108a3629e..c470f93f6d 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index b2d13d5642..73125309f4 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 923d10cfd5..c822a75eea 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c index 42288f9e18..60d99696fc 100644 --- a/src/soc/intel/braswell/xhci.c +++ b/src/soc/intel/braswell/xhci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index fe65a0113e..61f1008aa1 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/acpi/adsp.asl index 5cc9eef405..d5841b1e10 100644 --- a/src/soc/intel/broadwell/acpi/adsp.asl +++ b/src/soc/intel/broadwell/acpi/adsp.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index e6aad2195d..86ebdd57da 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl index db2a2b97fc..1e64480103 100644 --- a/src/soc/intel/broadwell/acpi/device_nvs.asl +++ b/src/soc/intel/broadwell/acpi/device_nvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/soc/intel/broadwell/acpi/ehci.asl index 4db5aa9df8..d5651e6084 100644 --- a/src/soc/intel/broadwell/acpi/ehci.asl +++ b/src/soc/intel/broadwell/acpi/ehci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 87c053bc2a..53a153b84b 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/acpi/gpio.asl index bf55c9b512..bfdcebf45b 100644 --- a/src/soc/intel/broadwell/acpi/gpio.asl +++ b/src/soc/intel/broadwell/acpi/gpio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/soc/intel/broadwell/acpi/hda.asl index 712b096933..c7ee26dc90 100644 --- a/src/soc/intel/broadwell/acpi/hda.asl +++ b/src/soc/intel/broadwell/acpi/hda.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/acpi/irqlinks.asl index c22c8a69d1..7e554624e5 100644 --- a/src/soc/intel/broadwell/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/acpi/irqlinks.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index ca44c5c90c..c8f81e18e2 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl index ef0eaba476..6d41ae368c 100644 --- a/src/soc/intel/broadwell/acpi/pch.asl +++ b/src/soc/intel/broadwell/acpi/pch.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/acpi/pci_irqs.asl index 44263ea6ab..7534d2c11d 100644 --- a/src/soc/intel/broadwell/acpi/pci_irqs.asl +++ b/src/soc/intel/broadwell/acpi/pci_irqs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/soc/intel/broadwell/acpi/pcie.asl index 3949d80ab7..acdada8031 100644 --- a/src/soc/intel/broadwell/acpi/pcie.asl +++ b/src/soc/intel/broadwell/acpi/pcie.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/soc/intel/broadwell/acpi/pcie_port.asl index 8ad4502d5f..57cd2d42e2 100644 --- a/src/soc/intel/broadwell/acpi/pcie_port.asl +++ b/src/soc/intel/broadwell/acpi/pcie_port.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl index 15a820ff56..d70944d368 100644 --- a/src/soc/intel/broadwell/acpi/platform.asl +++ b/src/soc/intel/broadwell/acpi/platform.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/soc/intel/broadwell/acpi/sata.asl index 18ebbc8487..e5f7fac057 100644 --- a/src/soc/intel/broadwell/acpi/sata.asl +++ b/src/soc/intel/broadwell/acpi/sata.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e9566a..a3bd86680e 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/acpi/smbus.asl index 53452ece55..e6c72d79c7 100644 --- a/src/soc/intel/broadwell/acpi/smbus.asl +++ b/src/soc/intel/broadwell/acpi/smbus.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index 18bf914cf7..9155b4dcce 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl index d638a27d30..0b6ca567d4 100644 --- a/src/soc/intel/broadwell/acpi/xhci.asl +++ b/src/soc/intel/broadwell/acpi/xhci.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index c4023cc84a..198a39adec 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 4c6ab75ef9..d3eb3959d6 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 7ea4a58e1f..671c968f96 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index c9c7d95ca6..2f13080c08 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 2b9f6a1dda..6c5b3a4bfd 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 18a65857a7..fabb95ad00 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 287b5b5532..7e0e6f24ca 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c index 00f3690d89..7a608c1ba0 100644 --- a/src/soc/intel/broadwell/cpu_info.c +++ b/src/soc/intel/broadwell/cpu_info.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index c8a4e7a288..70e62bb243 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index 07425c6e6c..8f4653e7c3 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 442a87014f..ddd6bfd61d 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/gpio.c index 8975f5e913..1920e31f12 100644 --- a/src/soc/intel/broadwell/gpio.c +++ b/src/soc/intel/broadwell/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index d1aee924f4..3cb91fe750 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 924ec61dd4..37f3871483 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index d07546490f..1fd90c517a 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/adsp.h b/src/soc/intel/broadwell/include/soc/adsp.h index 17b5adee4a..8edf19c758 100644 --- a/src/soc/intel/broadwell/include/soc/adsp.h +++ b/src/soc/intel/broadwell/include/soc/adsp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 8b0855227c..8da798f8ee 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h index c37816cfba..724a1c6ee3 100644 --- a/src/soc/intel/broadwell/include/soc/device_nvs.h +++ b/src/soc/intel/broadwell/include/soc/device_nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/ehci.h b/src/soc/intel/broadwell/include/soc/ehci.h index 4a6c56a683..56e26f9c8b 100644 --- a/src/soc/intel/broadwell/include/soc/ehci.h +++ b/src/soc/intel/broadwell/include/soc/ehci.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index 3c7f08ad97..ed34f1aca6 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/soc/intel/broadwell/include/soc/iobp.h index 77346018d2..c4ecff72c6 100644 --- a/src/soc/intel/broadwell/include/soc/iobp.h +++ b/src/soc/intel/broadwell/include/soc/iobp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h index 96b2c1fa45..5dbf30f98f 100644 --- a/src/soc/intel/broadwell/include/soc/iomap.h +++ b/src/soc/intel/broadwell/include/soc/iomap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/soc/intel/broadwell/include/soc/lpc.h index 5cca961bfe..8da9e40ccc 100644 --- a/src/soc/intel/broadwell/include/soc/lpc.h +++ b/src/soc/intel/broadwell/include/soc/lpc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index 69b75b49a0..f5603e79c4 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 9e196c16b5..965512acd8 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index ea64341e58..9776bb880a 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index ef8a87a4db..ffe67f9ce9 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 423f0d6635..0ee5523504 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h index 989ca06733..b73abe6c22 100644 --- a/src/soc/intel/broadwell/include/soc/pei_data.h +++ b/src/soc/intel/broadwell/include/soc/pei_data.h @@ -1,7 +1,6 @@ /* * Broadwell UEFI PEI wrapper * - * Copyright (C) 2014 Google Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/soc/intel/broadwell/include/soc/pei_wrapper.h index 2d9ffdb787..bad3c7b6fd 100644 --- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h +++ b/src/soc/intel/broadwell/include/soc/pei_wrapper.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index c9074d8a0b..d187faf354 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 71c7999e5b..d8da5f92dc 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h index 577815cd7d..cf53b7d172 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/soc/intel/broadwell/include/soc/rcba.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index b32b043b79..b0adefd693 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/soc/intel/broadwell/include/soc/sata.h index 2fe18ecd6d..f84825415f 100644 --- a/src/soc/intel/broadwell/include/soc/sata.h +++ b/src/soc/intel/broadwell/include/soc/sata.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/serialio.h b/src/soc/intel/broadwell/include/soc/serialio.h index 9bdbb8acad..41173ed414 100644 --- a/src/soc/intel/broadwell/include/soc/serialio.h +++ b/src/soc/intel/broadwell/include/soc/serialio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h index ed37373360..e320b0556d 100644 --- a/src/soc/intel/broadwell/include/soc/smbus.h +++ b/src/soc/intel/broadwell/include/soc/smbus.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index 00b8a9542d..303e494e4c 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index f414581c53..33e2861388 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h index 87a59345da..8a1d192500 100644 --- a/src/soc/intel/broadwell/include/soc/xhci.h +++ b/src/soc/intel/broadwell/include/soc/xhci.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index c4f325e368..26e0a710ed 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index e86b5bd46a..15b383c9e5 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 448c5dada9..4b786c81d9 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index d89f108416..e65978f47c 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 48492d3468..6bb434f00e 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 40c257126a..af3cea470b 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index e6c231924a..dc4ff113bf 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 36523411c3..2fc7d09503 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index 7b384c7737..12c9a0299c 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 2445dfacf6..172d8cda20 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index bad9f96135..ed287b8c5c 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 6d192ccdb6..efab8d4163 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index 5a456970c5..5374af71a0 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index e8f4eb89ee..467b83ea51 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 1970c31eb5..0cd1a9d28d 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 3759c1f100..7fe93bdfc5 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index d60ed380e3..98bd94b924 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 4a53c7abe2..f28f9d1636 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c index 4b08b4cbcb..d00a3fc5df 100644 --- a/src/soc/intel/broadwell/romstage/smbus.c +++ b/src/soc/intel/broadwell/romstage/smbus.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c index 5c0224a7b9..471794bab5 100644 --- a/src/soc/intel/broadwell/romstage/systemagent.c +++ b/src/soc/intel/broadwell/romstage/systemagent.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index a1a29b65fd..f8a4b4fc0b 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index f4773e186b..f8e223b7f6 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 1a59829108..518c99da73 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 0ac2ffc388..6a1e85b499 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 2bdeecc943..b26700e267 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 2c388870a0..7df9a341eb 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 7bf351a5ad..e11a66918b 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 8cc6516d2f..1af554a669 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/soc/intel/broadwell/tsc_freq.c index 5bc121795b..77167a9b30 100644 --- a/src/soc/intel/broadwell/tsc_freq.c +++ b/src/soc/intel/broadwell/tsc_freq.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c index 4d2e42b5e1..bd6b31b6f8 100644 --- a/src/soc/intel/broadwell/usb_debug.c +++ b/src/soc/intel/broadwell/usb_debug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 00b8b8ca87..e7b7d0a71a 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 2632ae0a89..67c8c63fd8 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/dptf.asl b/src/soc/intel/cannonlake/acpi/dptf.asl index fb05c5d225..7ae279cdf8 100644 --- a/src/soc/intel/cannonlake/acpi/dptf.asl +++ b/src/soc/intel/cannonlake/acpi/dptf.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl index d2678596c0..cb8ee57013 100644 --- a/src/soc/intel/cannonlake/acpi/gfx.asl +++ b/src/soc/intel/cannonlake/acpi/gfx.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Google LLC * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index e2eb78c48d..060280c882 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index acbd2ea430..d6226356b2 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index b024367181..e25c903479 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl index 1c832b4ea9..65f042055b 100644 --- a/src/soc/intel/cannonlake/acpi/ish.asl +++ b/src/soc/intel/cannonlake/acpi/ish.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index e0e23cac4e..6ae4975ee1 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/cannonlake/acpi/pch_glan.asl index 260dd44962..2d9d960565 100644 --- a/src/soc/intel/cannonlake/acpi/pch_glan.asl +++ b/src/soc/intel/cannonlake/acpi/pch_glan.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2108 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index 97967abd70..0d10d2deb5 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index accfdb93e2..5a993a5668 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 9d4a65c639..b837fe4a87 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/platform.asl b/src/soc/intel/cannonlake/acpi/platform.asl index da61619342..682a7b93d8 100644 --- a/src/soc/intel/cannonlake/acpi/platform.asl +++ b/src/soc/intel/cannonlake/acpi/platform.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 4938081f27..6cdb99fe7a 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/serialio.asl b/src/soc/intel/cannonlake/acpi/serialio.asl index 0a9b15c4c3..2a1cc6b2dd 100644 --- a/src/soc/intel/cannonlake/acpi/serialio.asl +++ b/src/soc/intel/cannonlake/acpi/serialio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/smbus.asl b/src/soc/intel/cannonlake/acpi/smbus.asl index cd5ba2c822..7678d4fff2 100644 --- a/src/soc/intel/cannonlake/acpi/smbus.asl +++ b/src/soc/intel/cannonlake/acpi/smbus.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8dbd850df6..62197f499a 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. - * (Written by Bora Guvendik for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 875cecb5e7..5f11c4849e 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 4cc15fca46..d5d178cc8e 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation.. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index f60f319999..0523aa0dbe 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index eca28b33dd..7cff74b689 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index b89c3b4147..5cc627a8f6 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 2bb1c92612..a53c1a8bef 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b14c3c50dc..7794fd44dd 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index 6c551ad563..eac691e18b 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 3ba0562980..9f3fe1dc8d 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index a2c359fe10..6c26e6a08d 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Intel Corporation. - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index b2fb9f9ec6..e3d33e3aa4 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 9d6ed387d6..46348060ef 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 4036fdc073..ace0d346af 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index dd9f433645..8595b8d7be 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c index 360189a0fd..1a893ec494 100644 --- a/src/soc/intel/cannonlake/gpio_common.c +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index ebe8b0bc6a..84e97762af 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c index c5998b50e2..706eeac854 100644 --- a/src/soc/intel/cannonlake/gspi.c +++ b/src/soc/intel/cannonlake/gspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c index 6983be1c30..df95df924a 100644 --- a/src/soc/intel/cannonlake/i2c.c +++ b/src/soc/intel/cannonlake/i2c.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h index efc837eb80..ec954e6dd6 100644 --- a/src/soc/intel/cannonlake/include/soc/bootblock.h +++ b/src/soc/intel/cannonlake/include/soc/bootblock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index d5f6c39f24..f757fd8968 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index 0e027d3456..d9f4f552a1 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/gpe.h b/src/soc/intel/cannonlake/include/soc/gpe.h index 521d523746..c37750b1c4 100644 --- a/src/soc/intel/cannonlake/include/soc/gpe.h +++ b/src/soc/intel/cannonlake/include/soc/gpe.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index efed88180c..d8879d3608 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h index 6d27f89549..4cae6e54f1 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_common.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 5c12e4cb67..ae59941e15 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index d03723dae1..67396a97a6 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index 698bd2a5c7..c40f4cf447 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index 23953142d7..8e135b0ed3 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index c66cde49a8..b75bbed863 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 61f4025811..898ad2ea2f 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h index 0d8b2ca3c0..84ccc74f5c 100644 --- a/src/soc/intel/cannonlake/include/soc/itss.h +++ b/src/soc/intel/cannonlake/include/soc/itss.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index 260e03cb1d..efa7c8c618 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index ba4a11a64c..cd65d40604 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 63595f353f..858225cfac 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/nhlt.h b/src/soc/intel/cannonlake/include/soc/nhlt.h index bd0da3ae68..f3ac06ea77 100644 --- a/src/soc/intel/cannonlake/include/soc/nhlt.h +++ b/src/soc/intel/cannonlake/include/soc/nhlt.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h index 3bd7bc2bca..cfb189d381 100644 --- a/src/soc/intel/cannonlake/include/soc/nvs.h +++ b/src/soc/intel/cannonlake/include/soc/nvs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/p2sb.h b/src/soc/intel/cannonlake/include/soc/p2sb.h index 73a50537a3..737d11ac1a 100644 --- a/src/soc/intel/cannonlake/include/soc/p2sb.h +++ b/src/soc/intel/cannonlake/include/soc/p2sb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 5253053954..bf80600170 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 88cfe59902..1a1deabea6 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index c4a18e8f90..99c37bca9c 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 77109651f0..65bfa0733e 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index fbd366bb2c..e6d5eb3892 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 486839852c..067f63d682 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index ab20ee7e3f..4fed172a65 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/sata.h b/src/soc/intel/cannonlake/include/soc/sata.h index 17802c3412..dc2822619d 100644 --- a/src/soc/intel/cannonlake/include/soc/sata.h +++ b/src/soc/intel/cannonlake/include/soc/sata.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index c92bd2d67a..d435d3b58f 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index 60d155783e..29bc300312 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/soc_chip.h b/src/soc/intel/cannonlake/include/soc/soc_chip.h index 3d6f232530..5abf328d86 100644 --- a/src/soc/intel/cannonlake/include/soc/soc_chip.h +++ b/src/soc/intel/cannonlake/include/soc/soc_chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h index 3bda9e8d59..a32118535d 100644 --- a/src/soc/intel/cannonlake/include/soc/systemagent.h +++ b/src/soc/intel/cannonlake/include/soc/systemagent.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 722a20251c..33c0bf0bf9 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 456db5b48f..b131f75f8c 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index c556839d18..43ab853121 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 8b9802220e..34fd1aacaf 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index d41b0b8bc8..174261a287 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Google LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c index ffe3f5bf6a..3aa4b8debb 100644 --- a/src/soc/intel/cannonlake/nhlt.c +++ b/src/soc/intel/cannonlake/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/p2sb.c b/src/soc/intel/cannonlake/p2sb.c index 6a7fac4963..328c4d3bab 100644 --- a/src/soc/intel/cannonlake/p2sb.c +++ b/src/soc/intel/cannonlake/p2sb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index c0bb9ae296..7812eeb3ca 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 2d691adbb2..b263892d7d 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 28211e37ef..431a70ccb0 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index ff3d73dee0..dfd596596c 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2017 Intel Corporation # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3c5be301b8..ee05b66839 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c index 8e783da6f9..c05c84820a 100644 --- a/src/soc/intel/cannonlake/romstage/pch.c +++ b/src/soc/intel/cannonlake/romstage/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 2505683479..2be8cc0de5 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c index 61db22e0b8..f30caecfc3 100644 --- a/src/soc/intel/cannonlake/romstage/systemagent.c +++ b/src/soc/intel/cannonlake/romstage/systemagent.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c index b69cd1a32d..9626dccb22 100644 --- a/src/soc/intel/cannonlake/sd.c +++ b/src/soc/intel/cannonlake/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index f68f4c29bf..abf548c203 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index e99a9a27be..fdacff6476 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/spi.c b/src/soc/intel/cannonlake/spi.c index 4989cd49aa..9f3f44a227 100644 --- a/src/soc/intel/cannonlake/spi.c +++ b/src/soc/intel/cannonlake/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 3f01f14dcf..8cfa8d2bc7 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index ae19acc264..50849560ac 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index bd73d15dd7..21a8ae2c46 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/xhci.c b/src/soc/intel/cannonlake/xhci.c index 2741883d88..95d3031e98 100644 --- a/src/soc/intel/cannonlake/xhci.c +++ b/src/soc/intel/cannonlake/xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index 0c0be154e6..c7e3a16594 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/acpi_wake_source.asl b/src/soc/intel/common/acpi/acpi_wake_source.asl index fa01802618..a5440e8e51 100644 --- a/src/soc/intel/common/acpi/acpi_wake_source.asl +++ b/src/soc/intel/common/acpi/acpi_wake_source.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/dptf/charger.asl b/src/soc/intel/common/acpi/dptf/charger.asl index fa54a5f103..ba728b41a3 100644 --- a/src/soc/intel/common/acpi/dptf/charger.asl +++ b/src/soc/intel/common/acpi/dptf/charger.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/dptf/cpu.asl b/src/soc/intel/common/acpi/dptf/cpu.asl index 9414e25024..99dc32a299 100644 --- a/src/soc/intel/common/acpi/dptf/cpu.asl +++ b/src/soc/intel/common/acpi/dptf/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/dptf/dptf.asl b/src/soc/intel/common/acpi/dptf/dptf.asl index 1dd57c04dc..4b7bdd5778 100644 --- a/src/soc/intel/common/acpi/dptf/dptf.asl +++ b/src/soc/intel/common/acpi/dptf/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/dptf/fan.asl b/src/soc/intel/common/acpi/dptf/fan.asl index 8c0e886229..4a15156de5 100644 --- a/src/soc/intel/common/acpi/dptf/fan.asl +++ b/src/soc/intel/common/acpi/dptf/fan.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index 6e361dc496..2dd2c59b7d 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/pci_osc.asl b/src/soc/intel/common/acpi/pci_osc.asl index 4179e94ae7..740cbe9a59 100644 --- a/src/soc/intel/common/acpi/pci_osc.asl +++ b/src/soc/intel/common/acpi/pci_osc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/pcr.asl b/src/soc/intel/common/acpi/pcr.asl index 9dc77e2f03..eac78c4574 100644 --- a/src/soc/intel/common/acpi/pcr.asl +++ b/src/soc/intel/common/acpi/pcr.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index c41ccbe0cb..8984f14657 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2016 Intel Corp * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl index 593821996c..350c319842 100644 --- a/src/soc/intel/common/acpi/sgx.asl +++ b/src/soc/intel/common/acpi/sgx.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi/wifi.asl b/src/soc/intel/common/acpi/wifi.asl index a90b3f23e4..ed19bda103 100644 --- a/src/soc/intel/common/acpi/wifi.asl +++ b/src/soc/intel/common/acpi/wifi.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index 389807e48c..c26c84f189 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 3a34c79304..bed4401b5a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index e94c49f7c8..8e1ea8dfdb 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/acpi/acpi/ipu.asl b/src/soc/intel/common/block/acpi/acpi/ipu.asl index 2c550edcbb..d62a6e46f2 100644 --- a/src/soc/intel/common/block/acpi/acpi/ipu.asl +++ b/src/soc/intel/common/block/acpi/acpi/ipu.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl index e7f6660645..cf48ea5658 100644 --- a/src/soc/intel/common/block/acpi/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index d271ddac3c..7206708a37 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 6551e9182a..810423661b 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0992d85acd..531d65208c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 091fc4a06b..68d3e323ff 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index ab7886cb36..04c8e65369 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S index 4ac580ce6f..f27d6e7d4a 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S +++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 89732f145a..a6ddbe29ff 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 87cebc0a8f..c77035a864 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 648ec6a6f1..b93594aa50 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-2018 Intel Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index f560a37e9d..3f66a92f38 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 Intel Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index dc21b8e116..0660480af7 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * * Copyright (C) 2016 Google Inc. - * * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 49284e9489..5c0b17ba2a 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 2ae56dfa7b..952df222a1 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index f3f4d4fd70..a8afd48c97 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 7ebf05a220..45406dbece 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 29d6c53e42..efbc3e7cc5 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 33f376ee77..148b815ea3 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 632cfcc1b6..d1af348063 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Google Inc. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 57dad62b8b..b5ea15e0c6 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/imc/imc.c b/src/soc/intel/common/block/imc/imc.c index e7f20bef03..27b2beaf3a 100644 --- a/src/soc/intel/common/block/imc/imc.c +++ b/src/soc/intel/common/block/imc/imc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index e615ccd213..502ac6cfac 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. - * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index d90714792e..5a046b5b90 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 84e750e2af..6b4da8059c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 595c7d8d6b..2c813833d0 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index e0e664931b..1fd0793cc2 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 9b351a938f..db0f50324c 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 1f054dbdcf..bd26e82e30 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 6be766125c..8e98228424 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/gspi.h b/src/soc/intel/common/block/include/intelblocks/gspi.h index 516d0ad4e3..48b570e067 100644 --- a/src/soc/intel/common/block/include/intelblocks/gspi.h +++ b/src/soc/intel/common/block/include/intelblocks/gspi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/imc.h b/src/soc/intel/common/block/include/intelblocks/imc.h index fc3c241564..2cfbd3b989 100644 --- a/src/soc/intel/common/block/include/intelblocks/imc.h +++ b/src/soc/intel/common/block/include/intelblocks/imc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Facebook, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h index 11f75980fb..4d1f05dfe8 100644 --- a/src/soc/intel/common/block/include/intelblocks/itss.h +++ b/src/soc/intel/common/block/include/intelblocks/itss.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 25a7370f83..1b5063ca5b 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. - * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index e80f3ddec5..27d13fb7c0 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/mmc.h b/src/soc/intel/common/block/include/intelblocks/mmc.h index a8776ea842..48ab7961b7 100644 --- a/src/soc/intel/common/block/include/intelblocks/mmc.h +++ b/src/soc/intel/common/block/include/intelblocks/mmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 4c528e0f78..dff35d9db9 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 8902d0992f..ebb1c4736b 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 30502f1ccc..054dcce9a8 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 72a3a33774..4ed5847d88 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. - * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/pcr.h b/src/soc/intel/common/block/include/intelblocks/pcr.h index c6554a36e5..8940fb5e3d 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcr.h +++ b/src/soc/intel/common/block/include/intelblocks/pcr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 850cda178b..ee3b96e74d 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index b622a74b9b..0aa209ab45 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h index 0faf0b0ef0..c958eb0fa3 100644 --- a/src/soc/intel/common/block/include/intelblocks/rtc.h +++ b/src/soc/intel/common/block/include/intelblocks/rtc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/sd.h b/src/soc/intel/common/block/include/intelblocks/sd.h index 1dde344572..59b7a043d7 100644 --- a/src/soc/intel/common/block/include/intelblocks/sd.h +++ b/src/soc/intel/common/block/include/intelblocks/sd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 36634d3fa1..52e8d56ef5 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/smbus.h b/src/soc/intel/common/block/include/intelblocks/smbus.h index 262a9e8e65..f465e6c9e9 100644 --- a/src/soc/intel/common/block/include/intelblocks/smbus.h +++ b/src/soc/intel/common/block/include/intelblocks/smbus.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index 06b9e212ad..8a56109aef 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/spi.h b/src/soc/intel/common/block/include/intelblocks/spi.h index 9fdf8ee1c0..a1705f8cc5 100644 --- a/src/soc/intel/common/block/include/intelblocks/spi.h +++ b/src/soc/intel/common/block/include/intelblocks/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/sram.h b/src/soc/intel/common/block/include/intelblocks/sram.h index 5b1d902213..c189d97c7e 100644 --- a/src/soc/intel/common/block/include/intelblocks/sram.h +++ b/src/soc/intel/common/block/include/intelblocks/sram.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index a11bf647d2..73a1efc4fa 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h index 86fa33b61a..0a434fa2ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/tco.h +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/thermal.h b/src/soc/intel/common/block/include/intelblocks/thermal.h index ab18eb6d1d..557f2ebf55 100644 --- a/src/soc/intel/common/block/include/intelblocks/thermal.h +++ b/src/soc/intel/common/block/include/intelblocks/thermal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 1b62421d2b..ba6a873c57 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/xdci.h b/src/soc/intel/common/block/include/intelblocks/xdci.h index 1158056778..2b2532c5e1 100644 --- a/src/soc/intel/common/block/include/intelblocks/xdci.h +++ b/src/soc/intel/common/block/include/intelblocks/xdci.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 0b3aa050e1..2720e01042 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index a8b390b719..00bf492369 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 3524a8f9e6..e65beb4a95 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 9a72580af6..767315a304 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 8edbd2ed7c..6f9ee732f4 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2018 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 1722dcde08..31b8544b61 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 5b72e72fe7..5bf196379c 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index cc20a48d22..153e7f7927 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 96f92f0861..0484bf3836 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Nico Huber * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index f3971c238f..f18092c232 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index ba64063425..e1f2a3508c 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index d022666dd7..d03348adec 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index 5a0d45cc0f..41c7e96607 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 5439767c32..39d8bcd15e 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 80364500b9..593233a693 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index bbdde39ed5..a3d0a2cb18 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 3f036e9847..56af940875 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 6f0cfd8f0e..698c213415 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index d647cf839b..97618b0d26 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index 9ecd7e086d..8842e76b54 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index aad5228178..9c1402b696 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h index adc2d30d70..5436dea5d1 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.h +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 2c0b760481..d5325359ca 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 12c538eb96..af1c633331 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 974c4897a8..538e0c89c1 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index ecea473645..e8ac35b919 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 51ac697eae..a96dc18307 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index bfbacea740..ec3a99ad22 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 487c1d885d..04eb4dd207 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 02a67884dd..fc27046025 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2020 Intel Corporation. - * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index b89a10def2..fa7aaf9f48 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 1273c0f30f..5c7f952d4c 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 8f2fd49da2..5a2b414ac3 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 94e2e65683..73690c3648 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 6f027e7af1..6fe019128e 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index ff4320197b..414fe37aac 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index d8ee29c9ff..a311ec2c88 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index e4f98eb39b..398f093e41 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 03a23dfe0a..c1aa9074e1 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/hda_verb.h b/src/soc/intel/common/hda_verb.h index 6562eab311..b85a04c3fb 100644 --- a/src/soc/intel/common/hda_verb.h +++ b/src/soc/intel/common/hda_verb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 2cd35ea6cd..dbb36de8e5 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/mma.h b/src/soc/intel/common/mma.h index 20dfc158ee..238e6ab371 100644 --- a/src/soc/intel/common/mma.h +++ b/src/soc/intel/common/mma.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index a268ea6c3c..1a74d7d44c 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h index adbf2fe573..01dae8c9d1 100644 --- a/src/soc/intel/common/pch/include/intelpch/lockdown.h +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 3fa6e77042..036cccca7c 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 71a7b0f02b..4d949098a0 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index e1b71ba1f0..6fb2bcfd4b 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 97437eef45..6a013e51f5 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/tpm_tis.c b/src/soc/intel/common/tpm_tis.c index 03089b2528..641bd685a7 100644 --- a/src/soc/intel/common/tpm_tis.c +++ b/src/soc/intel/common/tpm_tis.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 60fe0d861e..2fd3d1571d 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/vbt.h b/src/soc/intel/common/vbt.h index e5a17fb75a..7d7a028d67 100644 --- a/src/soc/intel/common/vbt.h +++ b/src/soc/intel/common/vbt.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 23b84529d2..6ca7f3e61f 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2018 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 635dab8908..2413274723 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 - 2017 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 163f76a4a6..d3e2853c6a 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. - * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index 5ef029e344..c98d50b8a0 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/irqlinks.asl b/src/soc/intel/denverton_ns/acpi/irqlinks.asl index 308ef1e688..f8ef5389e3 100644 --- a/src/soc/intel/denverton_ns/acpi/irqlinks.asl +++ b/src/soc/intel/denverton_ns/acpi/irqlinks.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index 4b6e78698c..f1d2724e55 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index b102f2fdfe..d5065e00e3 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/npk.asl b/src/soc/intel/denverton_ns/acpi/npk.asl index dfb5d9c7f1..d7a2cd1418 100644 --- a/src/soc/intel/denverton_ns/acpi/npk.asl +++ b/src/soc/intel/denverton_ns/acpi/npk.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index bc47b77f09..ddd79f9c4b 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/pcie_port.asl b/src/soc/intel/denverton_ns/acpi/pcie_port.asl index e0132caa7a..083ba303e7 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie_port.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie_port.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/pmc.asl b/src/soc/intel/denverton_ns/acpi/pmc.asl index 1b85ac8e2f..40b6d207fa 100644 --- a/src/soc/intel/denverton_ns/acpi/pmc.asl +++ b/src/soc/intel/denverton_ns/acpi/pmc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/sata.asl b/src/soc/intel/denverton_ns/acpi/sata.asl index a210bcc0ba..28daffafcf 100644 --- a/src/soc/intel/denverton_ns/acpi/sata.asl +++ b/src/soc/intel/denverton_ns/acpi/sata.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/sata2.asl b/src/soc/intel/denverton_ns/acpi/sata2.asl index 46be4e4db2..63043f5e72 100644 --- a/src/soc/intel/denverton_ns/acpi/sata2.asl +++ b/src/soc/intel/denverton_ns/acpi/sata2.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/smbus.asl b/src/soc/intel/denverton_ns/acpi/smbus.asl index ca0e96323b..2f95a739d2 100644 --- a/src/soc/intel/denverton_ns/acpi/smbus.asl +++ b/src/soc/intel/denverton_ns/acpi/smbus.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/smbus2.asl b/src/soc/intel/denverton_ns/acpi/smbus2.asl index 4b315ded1c..039daf7e64 100644 --- a/src/soc/intel/denverton_ns/acpi/smbus2.asl +++ b/src/soc/intel/denverton_ns/acpi/smbus2.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index 674f0435c8..d17f238b15 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/acpi/xhci.asl b/src/soc/intel/denverton_ns/acpi/xhci.asl index 8f29aba145..a7a2f556da 100644 --- a/src/soc/intel/denverton_ns/acpi/xhci.asl +++ b/src/soc/intel/denverton_ns/acpi/xhci.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 47c76b5acd..5b15d498f8 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index baa0878f5e..0f19464fc6 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index c21a2a7a1b..f71b5967e9 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. - * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index 53e86f97b0..d2e4103e8d 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index dd6f00eaf0..e99641330a 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. - * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index be8d991618..73a680e2b9 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/fiamux.c b/src/soc/intel/denverton_ns/fiamux.c index fc18a41312..acc462563b 100644 --- a/src/soc/intel/denverton_ns/fiamux.c +++ b/src/soc/intel/denverton_ns/fiamux.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation - * Copyright (C) 2017 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c index 64099583a3..997c991c0c 100644 --- a/src/soc/intel/denverton_ns/gpio.c +++ b/src/soc/intel/denverton_ns/gpio.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index b083768a54..005a1fe1d9 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/hob_display.c b/src/soc/intel/denverton_ns/hob_display.c index 062aea08a4..9c09ad0d08 100644 --- a/src/soc/intel/denverton_ns/hob_display.c +++ b/src/soc/intel/denverton_ns/hob_display.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index a00a4f498c..ad3d3591a6 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * Copyright (C) 2017-2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 5ab77e0221..e8f9b60ddb 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h index 6efedc36c3..98b82a460a 100644 --- a/src/soc/intel/denverton_ns/include/soc/bootblock.h +++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index 7fd2e94af0..bba20c4da2 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/fiamux.h b/src/soc/intel/denverton_ns/include/soc/fiamux.h index 5f65f53a83..5f3ec54fd5 100644 --- a/src/soc/intel/denverton_ns/include/soc/fiamux.h +++ b/src/soc/intel/denverton_ns/include/soc/fiamux.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h index 082de218fd..2012a47403 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index ae61e6d7c4..06fe26df21 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h index c1c1d65e60..d32b937ca9 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/hob_mem.h b/src/soc/intel/denverton_ns/include/soc/hob_mem.h index 44d73fa428..9d356b8d4e 100644 --- a/src/soc/intel/denverton_ns/include/soc/hob_mem.h +++ b/src/soc/intel/denverton_ns/include/soc/hob_mem.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * Copyright (C) 2017-2018 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index c512d55fd0..011b47d3a2 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/lpc.h b/src/soc/intel/denverton_ns/include/soc/lpc.h index b1b4462c14..18486c2070 100644 --- a/src/soc/intel/denverton_ns/include/soc/lpc.h +++ b/src/soc/intel/denverton_ns/include/soc/lpc.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 0d469c4871..7213c15a36 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index 8d1bc6a703..1dafef76a5 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 - 2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/p2sb.h b/src/soc/intel/denverton_ns/include/soc/p2sb.h index 6d5a41528a..0a98382baa 100644 --- a/src/soc/intel/denverton_ns/include/soc/p2sb.h +++ b/src/soc/intel/denverton_ns/include/soc/p2sb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/pattrs.h b/src/soc/intel/denverton_ns/include/soc/pattrs.h index b558e24afe..7bf794b232 100644 --- a/src/soc/intel/denverton_ns/include/soc/pattrs.h +++ b/src/soc/intel/denverton_ns/include/soc/pattrs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index a300fd4cd3..1345fc8d21 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/pcr.h b/src/soc/intel/denverton_ns/include/soc/pcr.h index 601577640b..d8632182ba 100644 --- a/src/soc/intel/denverton_ns/include/soc/pcr.h +++ b/src/soc/intel/denverton_ns/include/soc/pcr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 13c702cb53..dec1e0d63b 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 62201d97a7..d026c4c969 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/ramstage.h b/src/soc/intel/denverton_ns/include/soc/ramstage.h index 5887b056e8..ecbc5c1d8b 100644 --- a/src/soc/intel/denverton_ns/include/soc/ramstage.h +++ b/src/soc/intel/denverton_ns/include/soc/ramstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/romstage.h b/src/soc/intel/denverton_ns/include/soc/romstage.h index 6ec7cbedc4..96ff779bea 100644 --- a/src/soc/intel/denverton_ns/include/soc/romstage.h +++ b/src/soc/intel/denverton_ns/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/sata.h b/src/soc/intel/denverton_ns/include/soc/sata.h index f38b539353..134e8720ae 100644 --- a/src/soc/intel/denverton_ns/include/soc/sata.h +++ b/src/soc/intel/denverton_ns/include/soc/sata.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/smbus.h b/src/soc/intel/denverton_ns/include/soc/smbus.h index 5668440af3..ebac2766f9 100644 --- a/src/soc/intel/denverton_ns/include/soc/smbus.h +++ b/src/soc/intel/denverton_ns/include/soc/smbus.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index 0444699d3b..0a469618f8 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h index c34894871e..7c8c67a2fe 100644 --- a/src/soc/intel/denverton_ns/include/soc/soc_util.h +++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/systemagent.h b/src/soc/intel/denverton_ns/include/soc/systemagent.h index a02aea34d4..968105c328 100644 --- a/src/soc/intel/denverton_ns/include/soc/systemagent.h +++ b/src/soc/intel/denverton_ns/include/soc/systemagent.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 - 2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/uart.h b/src/soc/intel/denverton_ns/include/soc/uart.h index 662d3e9727..fb8aa13bbe 100644 --- a/src/soc/intel/denverton_ns/include/soc/uart.h +++ b/src/soc/intel/denverton_ns/include/soc/uart.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 8c0a181d0c..bf9263dcd3 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index c30f0e98c9..48e2da7f98 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index 631aac762a..ce57686e01 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index cbb9a4ead8..7027e1ed26 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index ccf0d9586b..9366ec2183 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/reset.c b/src/soc/intel/denverton_ns/reset.c index 577f1c4914..7b7146d057 100644 --- a/src/soc/intel/denverton_ns/reset.c +++ b/src/soc/intel/denverton_ns/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index cb6ba11386..5793aa25ba 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corp. - * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 891d95f934..9097526619 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index b4d81017b9..2d0a256aaf 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 75f179ec67..97ae37c51a 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index ef95f7e562..bb1cdcea5b 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/spi.c b/src/soc/intel/denverton_ns/spi.c index 8d03c07f64..290816104c 100644 --- a/src/soc/intel/denverton_ns/spi.c +++ b/src/soc/intel/denverton_ns/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index d8e42401c1..8af1c4f376 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/tsc_freq.c b/src/soc/intel/denverton_ns/tsc_freq.c index 0e268b3780..8e8565902a 100644 --- a/src/soc/intel/denverton_ns/tsc_freq.c +++ b/src/soc/intel/denverton_ns/tsc_freq.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 3b851ee973..d6babc48dc 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index f7d523ea5e..cc7bc04012 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/upd_display.c b/src/soc/intel/denverton_ns/upd_display.c index 4f4e1bfcf9..4467e30fb9 100644 --- a/src/soc/intel/denverton_ns/upd_display.c +++ b/src/soc/intel/denverton_ns/upd_display.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index a0ed6bae2f..7c6e88951a 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index a2ed8d9d20..057db1ed65 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index c8d4fefdbd..40a1e9ef30 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/pch_glan.asl b/src/soc/intel/icelake/acpi/pch_glan.asl index 260dd44962..2d9d960565 100644 --- a/src/soc/intel/icelake/acpi/pch_glan.asl +++ b/src/soc/intel/icelake/acpi/pch_glan.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2108 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/pch_hda.asl b/src/soc/intel/icelake/acpi/pch_hda.asl index 67223295a7..0d10d2deb5 100644 --- a/src/soc/intel/icelake/acpi/pch_hda.asl +++ b/src/soc/intel/icelake/acpi/pch_hda.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl index 79c99277f5..6dba827e52 100644 --- a/src/soc/intel/icelake/acpi/pci_irqs.asl +++ b/src/soc/intel/icelake/acpi/pci_irqs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. - * (Written by Lance Zhao for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/pcie.asl b/src/soc/intel/icelake/acpi/pcie.asl index 9d4a65c639..b837fe4a87 100644 --- a/src/soc/intel/icelake/acpi/pcie.asl +++ b/src/soc/intel/icelake/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/platform.asl b/src/soc/intel/icelake/acpi/platform.asl index b89fd4685a..682a7b93d8 100644 --- a/src/soc/intel/icelake/acpi/platform.asl +++ b/src/soc/intel/icelake/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/scs.asl b/src/soc/intel/icelake/acpi/scs.asl index 896fd77c19..9471da5b89 100644 --- a/src/soc/intel/icelake/acpi/scs.asl +++ b/src/soc/intel/icelake/acpi/scs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/serialio.asl b/src/soc/intel/icelake/acpi/serialio.asl index 3abf383c8a..2a1cc6b2dd 100644 --- a/src/soc/intel/icelake/acpi/serialio.asl +++ b/src/soc/intel/icelake/acpi/serialio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/smbus.asl b/src/soc/intel/icelake/acpi/smbus.asl index c654fe2087..7678d4fff2 100644 --- a/src/soc/intel/icelake/acpi/smbus.asl +++ b/src/soc/intel/icelake/acpi/smbus.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 389963e79c..3dd4894638 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. - * (Written by Bora Guvendik for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/xhci.asl b/src/soc/intel/icelake/acpi/xhci.asl index 9c624e4f48..3387430c04 100644 --- a/src/soc/intel/icelake/acpi/xhci.asl +++ b/src/soc/intel/icelake/acpi/xhci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index fce3cc424c..1abca127a3 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/bootblock/cpu.c b/src/soc/intel/icelake/bootblock/cpu.c index da7b7ea153..9d3903c5fa 100644 --- a/src/soc/intel/icelake/bootblock/cpu.c +++ b/src/soc/intel/icelake/bootblock/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index f51ecab4af..5f39622dd9 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index 660aab9101..78c3869413 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2bb908c064..d2427b931d 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 56f89db5e7..dd13259368 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 91282d8a66..57719c2d7b 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 2ec6b410df..903259497d 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Intel Corporation. - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index efde625d60..1fb720ac3a 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 6afa61e33d..b3fd6176cb 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 334fac8766..806cb4ded1 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index 96c5c838ad..f25ede023b 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 91f40b9c86..4f5d573c8b 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/gspi.c b/src/soc/intel/icelake/gspi.c index cd5dc8e6bb..706eeac854 100644 --- a/src/soc/intel/icelake/gspi.c +++ b/src/soc/intel/icelake/gspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/i2c.c b/src/soc/intel/icelake/i2c.c index 2820a85e68..df95df924a 100644 --- a/src/soc/intel/icelake/i2c.c +++ b/src/soc/intel/icelake/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h index 22e632fc75..27a2ce691d 100644 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ b/src/soc/intel/icelake/include/soc/bootblock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index 7d17058004..312de72699 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/espi.h b/src/soc/intel/icelake/include/soc/espi.h index 36ee9470ae..4fb762499c 100644 --- a/src/soc/intel/icelake/include/soc/espi.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/gpe.h b/src/soc/intel/icelake/include/soc/gpe.h index d946e2af13..c37750b1c4 100644 --- a/src/soc/intel/icelake/include/soc/gpe.h +++ b/src/soc/intel/icelake/include/soc/gpe.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h index 333dba1a15..9022aa84bf 100644 --- a/src/soc/intel/icelake/include/soc/gpio.h +++ b/src/soc/intel/icelake/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 6ecda855d6..b01e406f97 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h index 887e378e07..5de7960a03 100644 --- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 50ba00561d..81d052c73b 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/irq.h b/src/soc/intel/icelake/include/soc/irq.h index 2f980ff472..898ad2ea2f 100644 --- a/src/soc/intel/icelake/include/soc/irq.h +++ b/src/soc/intel/icelake/include/soc/irq.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/itss.h b/src/soc/intel/icelake/include/soc/itss.h index d846ce099e..92fa026685 100644 --- a/src/soc/intel/icelake/include/soc/itss.h +++ b/src/soc/intel/icelake/include/soc/itss.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h index 1146fdf848..c6df81b93c 100644 --- a/src/soc/intel/icelake/include/soc/me.h +++ b/src/soc/intel/icelake/include/soc/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/msr.h b/src/soc/intel/icelake/include/soc/msr.h index 2aa79af3d7..7925ea76b0 100644 --- a/src/soc/intel/icelake/include/soc/msr.h +++ b/src/soc/intel/icelake/include/soc/msr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h index c855df0305..cfb189d381 100644 --- a/src/soc/intel/icelake/include/soc/nvs.h +++ b/src/soc/intel/icelake/include/soc/nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/p2sb.h b/src/soc/intel/icelake/include/soc/p2sb.h index 253b54ce11..f444c837b4 100644 --- a/src/soc/intel/icelake/include/soc/p2sb.h +++ b/src/soc/intel/icelake/include/soc/p2sb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h index e1560c1657..fa28a4d07a 100644 --- a/src/soc/intel/icelake/include/soc/pch.h +++ b/src/soc/intel/icelake/include/soc/pch.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index e18fdaed99..21feeabfe0 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h index 40d1360ffe..034b622c93 100644 --- a/src/soc/intel/icelake/include/soc/pcr_ids.h +++ b/src/soc/intel/icelake/include/soc/pcr_ids.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 5bdefc9e4a..66b09751e4 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index 448dbb5564..f7a6ccb2b3 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h index 606e2ffb8d..a8c8fdd7b2 100644 --- a/src/soc/intel/icelake/include/soc/ramstage.h +++ b/src/soc/intel/icelake/include/soc/ramstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h index 977c7c057a..1672e8b5ca 100644 --- a/src/soc/intel/icelake/include/soc/romstage.h +++ b/src/soc/intel/icelake/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h index cdf55157ff..0ee6ff1dc3 100644 --- a/src/soc/intel/icelake/include/soc/serialio.h +++ b/src/soc/intel/icelake/include/soc/serialio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index 2277ca914e..8cadd05802 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/soc_chip.h b/src/soc/intel/icelake/include/soc/soc_chip.h index 2d996e9e5b..272e60386c 100644 --- a/src/soc/intel/icelake/include/soc/soc_chip.h +++ b/src/soc/intel/icelake/include/soc/soc_chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 4e78ceb898..013f9ce97c 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/include/soc/usb.h b/src/soc/intel/icelake/include/soc/usb.h index d2e50ef1e8..33c0bf0bf9 100644 --- a/src/soc/intel/icelake/include/soc/usb.h +++ b/src/soc/intel/icelake/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c index b92d1c52f9..43ab853121 100644 --- a/src/soc/intel/icelake/lockdown.c +++ b/src/soc/intel/icelake/lockdown.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/p2sb.c b/src/soc/intel/icelake/p2sb.c index 6a7fac4963..328c4d3bab 100644 --- a/src/soc/intel/icelake/p2sb.c +++ b/src/soc/intel/icelake/p2sb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 6348d28b25..4667f1d905 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 440efd011f..1dbbbc8d7d 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index d79ae455b0..431a70ccb0 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc index b42f3f4b7a..5a8322b055 100644 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ b/src/soc/intel/icelake/romstage/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2018 Intel Corporation # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 5aea2ee8af..0b52abe002 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c index 88a7cc7163..a005ea0b99 100644 --- a/src/soc/intel/icelake/romstage/pch.c +++ b/src/soc/intel/icelake/romstage/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 37fc678cd9..35f97cb654 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/romstage/systemagent.c b/src/soc/intel/icelake/romstage/systemagent.c index fc046a62fa..f30caecfc3 100644 --- a/src/soc/intel/icelake/romstage/systemagent.c +++ b/src/soc/intel/icelake/romstage/systemagent.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c index f7c0eb3fa7..d97b63f498 100644 --- a/src/soc/intel/icelake/sd.c +++ b/src/soc/intel/icelake/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index ec9deb2858..1075b0910a 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 0bedc9e6dd..236b0a85e5 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/spi.c b/src/soc/intel/icelake/spi.c index 8e4f089c2d..9f3f44a227 100644 --- a/src/soc/intel/icelake/spi.c +++ b/src/soc/intel/icelake/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index 930e78ed5e..1e19caf9ac 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index ae19acc264..50849560ac 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 099c7ddc9d..3c3dd35393 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015-2016 Intel Corp. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index bd120abc9f..ba853c0252 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2016 Intel Corporation. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 5006b19d47..da80eea166 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 957b4a0c37..5afcb96c52 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index ca96ceb6e4..24cd57330b 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -1,6 +1,5 @@ /** @file * - * Copyright (C) 2015-2016, Intel Corporation * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 59f8d1b474..677f6b9d7c 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 4e57273ffe..7e295b3f95 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/ehci.c b/src/soc/intel/quark/ehci.c index 12306293a7..d7da9294e6 100644 --- a/src/soc/intel/quark/ehci.c +++ b/src/soc/intel/quark/ehci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/fsp_params.c b/src/soc/intel/quark/fsp_params.c index d96d410f9a..d0cb19b770 100644 --- a/src/soc/intel/quark/fsp_params.c +++ b/src/soc/intel/quark/fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/gpio_i2c.c b/src/soc/intel/quark/gpio_i2c.c index 02b5892946..adb9c2f800 100644 --- a/src/soc/intel/quark/gpio_i2c.c +++ b/src/soc/intel/quark/gpio_i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 6430030e6b..76a6178a3e 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/IntelQNCConfig.h b/src/soc/intel/quark/include/soc/IntelQNCConfig.h index d13f9dca32..36fc33c605 100644 --- a/src/soc/intel/quark/include/soc/IntelQNCConfig.h +++ b/src/soc/intel/quark/include/soc/IntelQNCConfig.h @@ -1,7 +1,6 @@ /** @file Some configuration of QNC Package -Copyright (c) 2013-2017 Intel Corporation. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License. The full text of the license diff --git a/src/soc/intel/quark/include/soc/Ioh.h b/src/soc/intel/quark/include/soc/Ioh.h index 521ae8335c..649bc7c4c7 100644 --- a/src/soc/intel/quark/include/soc/Ioh.h +++ b/src/soc/intel/quark/include/soc/Ioh.h @@ -1,6 +1,5 @@ /** @file * Header file for QuarkSCSocId Ioh. - * Copyright (c) 2013-2017 Intel Corporation. * * This program and the accompanying materials are licensed and made available * under the terms and conditions of the BSD License which accompanies this diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index 21dc7f8aaa..cacc1287a5 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -1,7 +1,6 @@ /** @file QuarkNcSocId Register Definitions -Copyright (c) 2013-2017 Intel Corporation. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License. The full text of the license diff --git a/src/soc/intel/quark/include/soc/acpi.h b/src/soc/intel/quark/include/soc/acpi.h index 9f2ede86a6..39b71ba9b8 100644 --- a/src/soc/intel/quark/include/soc/acpi.h +++ b/src/soc/intel/quark/include/soc/acpi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h index 23c6a24fbf..0098486c9a 100644 --- a/src/soc/intel/quark/include/soc/car.h +++ b/src/soc/intel/quark/include/soc/car.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/cpu.h b/src/soc/intel/quark/include/soc/cpu.h index 238f37089d..34c089f3b1 100644 --- a/src/soc/intel/quark/include/soc/cpu.h +++ b/src/soc/intel/quark/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/i2c.h b/src/soc/intel/quark/include/soc/i2c.h index f3c585f737..9f741d7711 100644 --- a/src/soc/intel/quark/include/soc/i2c.h +++ b/src/soc/intel/quark/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index de81a1a030..dcebb1e59c 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index a24f28f7ff..2585debfbf 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h index c177c86e9a..671bc4204e 100644 --- a/src/soc/intel/quark/include/soc/pei_wrapper.h +++ b/src/soc/intel/quark/include/soc/pei_wrapper.h @@ -1,8 +1,6 @@ /* * UEFI PEI wrapper * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index e02b8a274e..1a87dae444 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index ada8899e9c..e4aae035bb 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 27231f9e11..aa55123046 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 453b4bbc08..6f5cbcca3e 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/sd.h b/src/soc/intel/quark/include/soc/sd.h index d678c95378..8f092d3efe 100644 --- a/src/soc/intel/quark/include/soc/sd.h +++ b/src/soc/intel/quark/include/soc/sd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/include/soc/spi.h b/src/soc/intel/quark/include/soc/spi.h index 95c6b8944c..1b5e70e385 100644 --- a/src/soc/intel/quark/include/soc/spi.h +++ b/src/soc/intel/quark/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h index 1c93f1cdf0..f9eb50c2da 100644 --- a/src/soc/intel/quark/include/soc/storage_test.h +++ b/src/soc/intel/quark/include/soc/storage_test.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c index df5bdcac2a..ad367c806a 100644 --- a/src/soc/intel/quark/lpc.c +++ b/src/soc/intel/quark/lpc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index aeba5182c2..b2726d739e 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c index 0507efcfa3..dda702e827 100644 --- a/src/soc/intel/quark/northcluster.c +++ b/src/soc/intel/quark/northcluster.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 5e5acd8266..ff37fe073d 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c index fe133663a8..2b8e99b1bc 100644 --- a/src/soc/intel/quark/reset.c +++ b/src/soc/intel/quark/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index d90a3af5d4..055f73725f 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2016 Intel Corporation # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c index 8ad87d2f43..47e59e6174 100644 --- a/src/soc/intel/quark/romstage/car.c +++ b/src/soc/intel/quark/romstage/car.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c index e0cf6c8262..94eeebe0d4 100644 --- a/src/soc/intel/quark/romstage/debug.c +++ b/src/soc/intel/quark/romstage/debug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index c31cafb14f..ee6fbfd1a1 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 47bfde4de6..484716c610 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c index 747ac2be6d..5644cc3793 100644 --- a/src/soc/intel/quark/romstage/pcie.c +++ b/src/soc/intel/quark/romstage/pcie.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c index cbbf43f982..abfbdcffe4 100644 --- a/src/soc/intel/quark/romstage/report_platform.c +++ b/src/soc/intel/quark/romstage/report_platform.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ac580eb28..99df27c197 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/sd.c b/src/soc/intel/quark/sd.c index 08db791ffd..5399e36e75 100644 --- a/src/soc/intel/quark/sd.c +++ b/src/soc/intel/quark/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/spi.c b/src/soc/intel/quark/spi.c index 0bd0473db5..9e12d2ad5e 100644 --- a/src/soc/intel/quark/spi.c +++ b/src/soc/intel/quark/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/quark/spi_debug.c b/src/soc/intel/quark/spi_debug.c index d9dfe8e1d3..cadd9fb741 100644 --- a/src/soc/intel/quark/spi_debug.c +++ b/src/soc/intel/quark/spi_debug.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 653466a6d9..a2ec4cda08 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c index fa5bd67efe..4fb7c88bca 100644 --- a/src/soc/intel/quark/tsc_freq.c +++ b/src/soc/intel/quark/tsc_freq.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c index 0037621941..d8db076978 100644 --- a/src/soc/intel/quark/uart.c +++ b/src/soc/intel/quark/uart.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/quark/uart_common.c b/src/soc/intel/quark/uart_common.c index 4408d878f5..4c0a953419 100644 --- a/src/soc/intel/quark/uart_common.c +++ b/src/soc/intel/quark/uart_common.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index bf54854425..10eec8a399 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/dptf/charger.asl b/src/soc/intel/skylake/acpi/dptf/charger.asl index dd4a2103a6..ba728b41a3 100644 --- a/src/soc/intel/skylake/acpi/dptf/charger.asl +++ b/src/soc/intel/skylake/acpi/dptf/charger.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index c614aaf265..9ffe040fea 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index 61f982c4b9..0a2e7ab4f4 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/dptf/fan.asl b/src/soc/intel/skylake/acpi/dptf/fan.asl index 74cdb1bd1e..4a15156de5 100644 --- a/src/soc/intel/skylake/acpi/dptf/fan.asl +++ b/src/soc/intel/skylake/acpi/dptf/fan.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index f73d366e6a..8dda3a84d4 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 8aeb5a37f0..796704f633 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 8788bd3e93..d1b780193e 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/ipu.asl b/src/soc/intel/skylake/acpi/ipu.asl index 66dcd3b8f5..9abc1a4ee8 100644 --- a/src/soc/intel/skylake/acpi/ipu.asl +++ b/src/soc/intel/skylake/acpi/ipu.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index b83c1cb84c..c4a5d71387 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index 7dd0298cb7..f9712f3775 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index ce1619aaea..7487920274 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/pch_hda.asl b/src/soc/intel/skylake/acpi/pch_hda.asl index 22dc21fad6..4b86a92c3b 100644 --- a/src/soc/intel/skylake/acpi/pch_hda.asl +++ b/src/soc/intel/skylake/acpi/pch_hda.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl index 95be7768cf..8c0b62a9b9 100644 --- a/src/soc/intel/skylake/acpi/pci_irqs.asl +++ b/src/soc/intel/skylake/acpi/pci_irqs.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index b039f539ee..b28ea44323 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl index 36c3ae3915..3cfc308b1b 100644 --- a/src/soc/intel/skylake/acpi/platform.asl +++ b/src/soc/intel/skylake/acpi/platform.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/pmc.asl b/src/soc/intel/skylake/acpi/pmc.asl index d097082f99..da58355467 100644 --- a/src/soc/intel/skylake/acpi/pmc.asl +++ b/src/soc/intel/skylake/acpi/pmc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index ad68ef90cf..8fc4f3fb6b 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index d1e0e2b15e..006e7134cc 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl index 46d4672ebb..abeb9ff05e 100644 --- a/src/soc/intel/skylake/acpi/smbus.asl +++ b/src/soc/intel/skylake/acpi/smbus.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index e430b43ca9..92d0d545fc 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index b5aa41292a..5e285c971c 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 26454e4b09..5c0daba596 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 0f3038dabf..3a44ee5421 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index b9a5633026..83224e8125 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 4a519cfdc2..e1620e7c25 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8e86156a07..0ab10ca4c7 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 69b818bab9..178ab03a6b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index d7da56eaf7..965f7495d9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 63f382d222..d32a488f4e 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index e5d32d7b6f..8f980989c2 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae126..c67c0e9e7b 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 - 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c06893edf6..daa6eaa117 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c index 3fb7c5048d..28bf448fca 100644 --- a/src/soc/intel/skylake/gspi.c +++ b/src/soc/intel/skylake/gspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 316c633c4d..21629b087a 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index c39c06627b..447d53c5a0 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 2121821126..63dc8546f6 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 0681f78033..43fc714305 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h index 4dbc99a075..fbfc7de6fe 100644 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ b/src/soc/intel/skylake/include/soc/device_nvs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/gpe.h b/src/soc/intel/skylake/include/soc/gpe.h index d0962b84d8..e643544f5b 100644 --- a/src/soc/intel/skylake/include/soc/gpe.h +++ b/src/soc/intel/skylake/include/soc/gpe.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 13a0a7ab62..4d85e183d5 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c20c3..3568df5535 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h index c6a23db0a7..e5200c21fe 100644 --- a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h index f5633e4ec6..0dca200a72 100644 --- a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/interrupt.h b/src/soc/intel/skylake/include/soc/interrupt.h index bc654981f1..a0c5b06d12 100644 --- a/src/soc/intel/skylake/include/soc/interrupt.h +++ b/src/soc/intel/skylake/include/soc/interrupt.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index b447d79958..efd4ff8a73 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/irq.h b/src/soc/intel/skylake/include/soc/irq.h index cdc620f0e6..30730cab9d 100644 --- a/src/soc/intel/skylake/include/soc/irq.h +++ b/src/soc/intel/skylake/include/soc/irq.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h index e6eb8b0744..5cf96ff874 100644 --- a/src/soc/intel/skylake/include/soc/itss.h +++ b/src/soc/intel/skylake/include/soc/itss.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 2f581fb3b8..ff212a1c2e 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index bd0942ae31..348120a392 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index a25e5acbe2..b33a30faed 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 24e4cf1a2a..e6ae988c45 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index 8d7c11af75..e2f0a5bf4c 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index e2bf5a119c..9a99c823a8 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index ff6b8c1c23..59ee1e2a97 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index 71affd8eea..ee12f4847f 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index faad1efa05..3e26b1669e 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 36c4a13368..9f5ccc97b4 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h index 4157c4e09b..87198f4c45 100644 --- a/src/soc/intel/skylake/include/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index bd98a2bba8..62b0bec377 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/serialio.h b/src/soc/intel/skylake/include/soc/serialio.h index a07f29c9b0..76e5adeaeb 100644 --- a/src/soc/intel/skylake/include/soc/serialio.h +++ b/src/soc/intel/skylake/include/soc/serialio.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index 216e864dbc..72e39441bb 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/soc_chip.h b/src/soc/intel/skylake/include/soc/soc_chip.h index f9e7e4fc64..43807be765 100644 --- a/src/soc/intel/skylake/include/soc/soc_chip.h +++ b/src/soc/intel/skylake/include/soc/soc_chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 91209c8793..477d853ab5 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index d4f7cc5683..947212fc95 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 5bd649cefc..7a0c120889 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 6e6d6555c2..533a4e2529 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 6911744bcb..4db91b66cc 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 71ffb9a23f..0db3c80a3c 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 45a7c485ea..78e2efc8b5 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/da7219.c b/src/soc/intel/skylake/nhlt/da7219.c index 5d872ecff7..323744d33d 100644 --- a/src/soc/intel/skylake/nhlt/da7219.c +++ b/src/soc/intel/skylake/nhlt/da7219.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/dmic.c b/src/soc/intel/skylake/nhlt/dmic.c index a7684bdefd..d3427326da 100644 --- a/src/soc/intel/skylake/nhlt/dmic.c +++ b/src/soc/intel/skylake/nhlt/dmic.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/max98357.c b/src/soc/intel/skylake/nhlt/max98357.c index b2abc26cea..ef106c2e3e 100644 --- a/src/soc/intel/skylake/nhlt/max98357.c +++ b/src/soc/intel/skylake/nhlt/max98357.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a4130b1..10a12b9a0a 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c index bbaf15ded9..53f1d531c6 100644 --- a/src/soc/intel/skylake/nhlt/max98927.c +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c index dd91435acb..b82afbf2a5 100644 --- a/src/soc/intel/skylake/nhlt/nau88l25.c +++ b/src/soc/intel/skylake/nhlt/nau88l25.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c index 9c48c7ba37..bbb2614f9c 100644 --- a/src/soc/intel/skylake/nhlt/rt5514.c +++ b/src/soc/intel/skylake/nhlt/rt5514.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c index c5a3f5393d..c7842aab5e 100644 --- a/src/soc/intel/skylake/nhlt/rt5663.c +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/ssm4567.c b/src/soc/intel/skylake/nhlt/ssm4567.c index 6808bffe3a..2651dcb447 100644 --- a/src/soc/intel/skylake/nhlt/ssm4567.c +++ b/src/soc/intel/skylake/nhlt/ssm4567.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c index c1e9118248..0eb06fd983 100644 --- a/src/soc/intel/skylake/p2sb.c +++ b/src/soc/intel/skylake/p2sb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ab9297fe92..8f4dac47ef 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index afe9b71117..6f837e3b91 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index b16e11c923..9c75228dbb 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c index 8e783da6f9..c05c84820a 100644 --- a/src/soc/intel/skylake/romstage/pch.c +++ b/src/soc/intel/skylake/romstage/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 51428dfe28..d5db8e64cc 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index e1272a1cb1..2525bfcda9 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index a24d03f98d..c431674491 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 213de0ac00..35797e657d 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 62fc7e415d..fe697ccdc3 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c index b2d8de92b6..6d35b2735f 100644 --- a/src/soc/intel/skylake/spi.c +++ b/src/soc/intel/skylake/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 410265f68e..64be7c4349 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 18fcf1b194..61ff00e511 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 9a4ddd899a..98d2513ec5 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c index bca3b861ea..073125da50 100644 --- a/src/soc/intel/skylake/xhci.c +++ b/src/soc/intel/skylake/xhci.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index af4076cf60..23fd970500 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index c9da977c7d..4f08cd78bd 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index 0378b52be3..9bf0c6032f 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl index a16ebf753d..4444c09a5b 100644 --- a/src/soc/intel/tigerlake/acpi/gpio_op.asl +++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/ipu.asl b/src/soc/intel/tigerlake/acpi/ipu.asl index ed964a4165..5711644bcb 100644 --- a/src/soc/intel/tigerlake/acpi/ipu.asl +++ b/src/soc/intel/tigerlake/acpi/ipu.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl index 186a147f44..ee3f1a3fdf 100644 --- a/src/soc/intel/tigerlake/acpi/ish.asl +++ b/src/soc/intel/tigerlake/acpi/ish.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/tigerlake/acpi/pch_glan.asl index 260dd44962..2d9d960565 100644 --- a/src/soc/intel/tigerlake/acpi/pch_glan.asl +++ b/src/soc/intel/tigerlake/acpi/pch_glan.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2108 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pch_hda.asl b/src/soc/intel/tigerlake/acpi/pch_hda.asl index 708d0b56f1..0d10d2deb5 100644 --- a/src/soc/intel/tigerlake/acpi/pch_hda.asl +++ b/src/soc/intel/tigerlake/acpi/pch_hda.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index d3230b4aa9..7048c150f6 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl index 006a5de4a8..086282e733 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl index 8aadf8db6a..7f632ba32e 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index c6cfbce57b..53ae316413 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl index dde9b13186..682a7b93d8 100644 --- a/src/soc/intel/tigerlake/acpi/platform.asl +++ b/src/soc/intel/tigerlake/acpi/platform.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl index 0d62edd926..6dd2d35354 100644 --- a/src/soc/intel/tigerlake/acpi/pmc.asl +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl index a9ff93c2ca..83da7e0f06 100644 --- a/src/soc/intel/tigerlake/acpi/scs.asl +++ b/src/soc/intel/tigerlake/acpi/scs.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl index 95759c2dd0..6fd135b437 100644 --- a/src/soc/intel/tigerlake/acpi/serialio.asl +++ b/src/soc/intel/tigerlake/acpi/serialio.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/smbus.asl b/src/soc/intel/tigerlake/acpi/smbus.asl index 8febe9deef..f273e3669d 100644 --- a/src/soc/intel/tigerlake/acpi/smbus.asl +++ b/src/soc/intel/tigerlake/acpi/smbus.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 1403eb4b13..adb16aa4ba 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl index 9618cf3003..f147a2a83f 100644 --- a/src/soc/intel/tigerlake/acpi/xhci.asl +++ b/src/soc/intel/tigerlake/acpi/xhci.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl index fe17b0d1bf..41be89ace1 100644 --- a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl +++ b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl index 312cc5a88e..b97f52052b 100644 --- a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl +++ b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index a4f965947d..1abca127a3 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/bootblock/cpu.c b/src/soc/intel/tigerlake/bootblock/cpu.c index 1bae4fa804..dddf24352d 100644 --- a/src/soc/intel/tigerlake/bootblock/cpu.c +++ b/src/soc/intel/tigerlake/bootblock/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 090f88f910..b0646018c6 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index c6a62c3deb..d7b2e0db32 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index dc36da34c4..1c7078d6cf 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 87aa8943e4..f82f13d45b 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index cfbfdb3ea4..dfbcd22b94 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 2ec6b410df..903259497d 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Intel Corporation. - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 7efd210cad..da36ea6304 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index aed5cc0e5e..b636ccbec0 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 96aa7ba016..932bd06ff7 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 33abac4411..f3f700f146 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/gpio_jsl.c b/src/soc/intel/tigerlake/gpio_jsl.c index bd0f5004b6..afb9f7b3bc 100644 --- a/src/soc/intel/tigerlake/gpio_jsl.c +++ b/src/soc/intel/tigerlake/gpio_jsl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/gpio_tgl.c b/src/soc/intel/tigerlake/gpio_tgl.c index 54ed5d3f92..cfdd0ac465 100644 --- a/src/soc/intel/tigerlake/gpio_tgl.c +++ b/src/soc/intel/tigerlake/gpio_tgl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index c215384f10..fef17e17e8 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/gspi.c b/src/soc/intel/tigerlake/gspi.c index 2dc738ec97..1381fb2499 100644 --- a/src/soc/intel/tigerlake/gspi.c +++ b/src/soc/intel/tigerlake/gspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/i2c.c b/src/soc/intel/tigerlake/i2c.c index 3d00372d59..46bc726726 100644 --- a/src/soc/intel/tigerlake/i2c.c +++ b/src/soc/intel/tigerlake/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h index 6dbbfecd02..0c8d8c201a 100644 --- a/src/soc/intel/tigerlake/include/soc/bootblock.h +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 210e6993ed..799382498b 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/espi.h b/src/soc/intel/tigerlake/include/soc/espi.h index 03cf8e8b55..3f7e32a717 100644 --- a/src/soc/intel/tigerlake/include/soc/espi.h +++ b/src/soc/intel/tigerlake/include/soc/espi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpe.h b/src/soc/intel/tigerlake/include/soc/gpe.h index d946e2af13..c37750b1c4 100644 --- a/src/soc/intel/tigerlake/include/soc/gpe.h +++ b/src/soc/intel/tigerlake/include/soc/gpe.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index 3a39e3a153..7a6df7c74f 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index db5b3741cd..07835aac2d 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h index c2d686366d..69ed539cae 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h index 7017aa8e87..35a15ded66 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index 145892b7d1..28551ba28a 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h index ce7d0d87e5..6cfb1873cb 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h index 750f589689..ec582c3133 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index d9fc01eaa8..361c296547 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index dec8376033..b87467ad5b 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/irq_jsl.h b/src/soc/intel/tigerlake/include/soc/irq_jsl.h index 2a2d20f671..a6edd23d97 100644 --- a/src/soc/intel/tigerlake/include/soc/irq_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/irq_jsl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h index 0ea6053c2d..6f268c1eae 100644 --- a/src/soc/intel/tigerlake/include/soc/irq_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/itss.h b/src/soc/intel/tigerlake/include/soc/itss.h index 6631ccc27d..39794ead73 100644 --- a/src/soc/intel/tigerlake/include/soc/itss.h +++ b/src/soc/intel/tigerlake/include/soc/itss.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index 9bb41ca57b..94331b4c9e 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h index 588ad5c58d..7f860ede52 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h index dd0541809e..5573fb7110 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h index 2aa79af3d7..7925ea76b0 100644 --- a/src/soc/intel/tigerlake/include/soc/msr.h +++ b/src/soc/intel/tigerlake/include/soc/msr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/nvs.h b/src/soc/intel/tigerlake/include/soc/nvs.h index c855df0305..cfb189d381 100644 --- a/src/soc/intel/tigerlake/include/soc/nvs.h +++ b/src/soc/intel/tigerlake/include/soc/nvs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/p2sb.h b/src/soc/intel/tigerlake/include/soc/p2sb.h index 46fdf47c59..d483ee399b 100644 --- a/src/soc/intel/tigerlake/include/soc/p2sb.h +++ b/src/soc/intel/tigerlake/include/soc/p2sb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h index ae8e310afb..c2f497c1c8 100644 --- a/src/soc/intel/tigerlake/include/soc/pch.h +++ b/src/soc/intel/tigerlake/include/soc/pch.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index af449ba118..8b740cf93b 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index 16162d9ecc..4143892f87 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index 588dfba7ba..14fa5d0c08 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 53076e5885..10693c02a9 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/ramstage.h b/src/soc/intel/tigerlake/include/soc/ramstage.h index 606e2ffb8d..a8c8fdd7b2 100644 --- a/src/soc/intel/tigerlake/include/soc/ramstage.h +++ b/src/soc/intel/tigerlake/include/soc/ramstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index 98ed6bc158..1672e8b5ca 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/serialio.h b/src/soc/intel/tigerlake/include/soc/serialio.h index 04c0efe19b..509f0b0f14 100644 --- a/src/soc/intel/tigerlake/include/soc/serialio.h +++ b/src/soc/intel/tigerlake/include/soc/serialio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h index 0ad565a613..3fb8291698 100644 --- a/src/soc/intel/tigerlake/include/soc/smbus.h +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/soc_chip.h b/src/soc/intel/tigerlake/include/soc/soc_chip.h index 3b02386375..250aa9a0aa 100644 --- a/src/soc/intel/tigerlake/include/soc/soc_chip.h +++ b/src/soc/intel/tigerlake/include/soc/soc_chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 92d70723df..d8c8ad47da 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index d2e50ef1e8..33c0bf0bf9 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c index 08ae4ef455..18d4fa728e 100644 --- a/src/soc/intel/tigerlake/lockdown.c +++ b/src/soc/intel/tigerlake/lockdown.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/meminit_jsl.c b/src/soc/intel/tigerlake/meminit_jsl.c index f977ce2cc3..3247357f1a 100644 --- a/src/soc/intel/tigerlake/meminit_jsl.c +++ b/src/soc/intel/tigerlake/meminit_jsl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/meminit_tgl.c b/src/soc/intel/tigerlake/meminit_tgl.c index 922f66a543..a0e5107998 100644 --- a/src/soc/intel/tigerlake/meminit_tgl.c +++ b/src/soc/intel/tigerlake/meminit_tgl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/soc/intel/tigerlake/p2sb.c b/src/soc/intel/tigerlake/p2sb.c index f5a3e70fce..64f181f634 100644 --- a/src/soc/intel/tigerlake/p2sb.c +++ b/src/soc/intel/tigerlake/p2sb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 65284ec57c..13902b80a6 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index d9eb18665e..ac254020cb 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c index 11e411da48..431a70ccb0 100644 --- a/src/soc/intel/tigerlake/reset.c +++ b/src/soc/intel/tigerlake/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 2bf9812c08..817df541a9 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -1,7 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Intel Corporation # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index a5c4c907e2..39fc445b90 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index b46f3a3f10..e275e59fcc 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c index 88a7cc7163..a005ea0b99 100644 --- a/src/soc/intel/tigerlake/romstage/pch.c +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index f592bb0574..f78ea29ae1 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c index 183089e9fb..9fa498e802 100644 --- a/src/soc/intel/tigerlake/romstage/systemagent.c +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/sd.c b/src/soc/intel/tigerlake/sd.c index bc9dd9b26f..9898734f3d 100644 --- a/src/soc/intel/tigerlake/sd.c +++ b/src/soc/intel/tigerlake/sd.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 1eb56aac8d..67e59a26a0 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 9e21a233a3..44b464441d 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index df4a593368..5270616af6 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 152f8f90d9..fb0ce118aa 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c index b330e7791a..03b4469a98 100644 --- a/src/soc/intel/tigerlake/uart.c +++ b/src/soc/intel/tigerlake/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 94c0ac4a8d..1f015b15a3 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 - 2020 Intel Corporation -## Copyright (C) 2019 - 2020 Facebook Inc ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 9ad3e77b35..3178a4e2bf 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 - 2020 Intel Corporation -## Copyright (C) 2019 - 2020 Facebook Inc ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 37dd420cf7..e10e615cad 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/acpi/globalnvs.asl index c2d5853e06..b719aa98b4 100644 --- a/src/soc/intel/xeon_sp/acpi/globalnvs.asl +++ b/src/soc/intel/xeon_sp/acpi/globalnvs.asl @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index 2d1187f4c3..6750a4c56a 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/acpi/pci_irq.asl index cfa4ad5c7b..613e0848db 100644 --- a/src/soc/intel/xeon_sp/acpi/pci_irq.asl +++ b/src/soc/intel/xeon_sp/acpi/pci_irq.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl index 35fbf98bae..ced1c4fd2b 100644 --- a/src/soc/intel/xeon_sp/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/acpi/uncore.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl index 8492725334..b3278f529c 100644 --- a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 482f5b522b..6b2c48809d 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/chip.c b/src/soc/intel/xeon_sp/chip.c index 832f98e63b..0aa61207de 100644 --- a/src/soc/intel/xeon_sp/chip.c +++ b/src/soc/intel/xeon_sp/chip.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h index 72f2445bba..9388ba5407 100644 --- a/src/soc/intel/xeon_sp/chip.h +++ b/src/soc/intel/xeon_sp/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/cpu.c b/src/soc/intel/xeon_sp/cpu.c index 1d5c5788ab..fcee02faee 100644 --- a/src/soc/intel/xeon_sp/cpu.c +++ b/src/soc/intel/xeon_sp/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/hob_display.c b/src/soc/intel/xeon_sp/hob_display.c index 15080112f0..567fad11c8 100644 --- a/src/soc/intel/xeon_sp/hob_display.c +++ b/src/soc/intel/xeon_sp/hob_display.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 641a3c5dc4..8e1dcb8d0c 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/cpu.h b/src/soc/intel/xeon_sp/include/soc/cpu.h index 82b893c6b3..611fb19715 100644 --- a/src/soc/intel/xeon_sp/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h index 8cb472d515..ac230ef78b 100644 --- a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 7c825a46bd..af6f545037 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h index 06942aeb43..bfb800862f 100644 --- a/src/soc/intel/xeon_sp/include/soc/irq.h +++ b/src/soc/intel/xeon_sp/include/soc/irq.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index 6004490b1a..95057769bb 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h index 00dded3427..613775c759 100644 --- a/src/soc/intel/xeon_sp/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 - 2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * Copyright (C) 2014 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pci_devs.h index db78c824f3..fae7ca0279 100644 --- a/src/soc/intel/xeon_sp/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/include/soc/pci_devs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index c67969237f..8d898e6e4e 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index ea111cdef9..85ad2b0125 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index c080749bf0..5388214907 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h index c012dd6cbd..cf615ff635 100644 --- a/src/soc/intel/xeon_sp/include/soc/ramstage.h +++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 623306ffbe..8337210145 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/soc_util.h b/src/soc/intel/xeon_sp/include/soc/soc_util.h index 8b5e1a2ff7..47e5be3172 100644 --- a/src/soc/intel/xeon_sp/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/include/soc/soc_util.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index b0ba68147b..4dd6f7c657 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/reset.c b/src/soc/intel/xeon_sp/reset.c index 80a452b870..e4ab466d9c 100644 --- a/src/soc/intel/xeon_sp/reset.c +++ b/src/soc/intel/xeon_sp/reset.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index dc94dc6810..a519663134 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/soc_util.c b/src/soc/intel/xeon_sp/soc_util.c index 6310bac8a6..6ba9f8eb85 100644 --- a/src/soc/intel/xeon_sp/soc_util.c +++ b/src/soc/intel/xeon_sp/soc_util.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/spi.c b/src/soc/intel/xeon_sp/spi.c index 18af5e488a..a5bc729d09 100644 --- a/src/soc/intel/xeon_sp/spi.c +++ b/src/soc/intel/xeon_sp/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index adf3e3e40b..34f00d88eb 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/upd_display.c b/src/soc/intel/xeon_sp/upd_display.c index 2ae34ed2b9..6ba46a9237 100644 --- a/src/soc/intel/xeon_sp/upd_display.c +++ b/src/soc/intel/xeon_sp/upd_display.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation - * Copyright (C) 2019 - 2020 Facebook Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index accafeb9c0..0edcd28fd6 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 494f470d10..464b025fc8 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 03e177e569..ff968a23c4 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c index 84ba0e2e99..79dcf2e557 100644 --- a/src/soc/mediatek/common/gpio.c +++ b/src/soc/mediatek/common/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 1ca55ae717..d73a7f07b5 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/ddp_common.h b/src/soc/mediatek/common/include/soc/ddp_common.h index 6d00ea3c75..9849576e91 100644 --- a/src/soc/mediatek/common/include/soc/ddp_common.h +++ b/src/soc/mediatek/common/include/soc/ddp_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 25727b8398..63e0d7f95e 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 374c810313..097cbb50c6 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index c9dade4d82..0229eb56ea 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h index 7fa847fd1d..7c8054416b 100644 --- a/src/soc/mediatek/common/include/soc/mmu_operations.h +++ b/src/soc/mediatek/common/include/soc/mmu_operations.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index 74bdda19ac..0306c8d1f8 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index d0ffa86c48..e4814d785d 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index bf64164948..041742cd5c 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index ff5dd34d89..1ac8a81888 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 1ecb94dab0..4058dfd00d 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/timer.h b/src/soc/mediatek/common/include/soc/timer.h index b58d4d3227..78f810a11a 100644 --- a/src/soc/mediatek/common/include/soc/timer.h +++ b/src/soc/mediatek/common/include/soc/timer.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 22704e77b5..bcb1a0d5a7 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index b24be28e3f..c4d3ec2628 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/memory_test.c b/src/soc/mediatek/common/memory_test.c index 7e2260182b..c930e2feee 100644 --- a/src/soc/mediatek/common/memory_test.c +++ b/src/soc/mediatek/common/memory_test.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 7292487bed..0f9146a911 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index fbc2d7dfe7..1243960e92 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index a63fe8927b..ae9f7c7927 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c index 6785c0a0bd..755672f7e0 100644 --- a/src/soc/mediatek/common/pmic_wrap.c +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/reset.c b/src/soc/mediatek/common/reset.c index 62c8016225..951b91c114 100644 --- a/src/soc/mediatek/common/reset.c +++ b/src/soc/mediatek/common/reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index 080f334c48..89a7d36f53 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index dbbc14dc18..a7f952972c 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c index 6fc2ab2fe9..0ebd3f9643 100644 --- a/src/soc/mediatek/common/timer.c +++ b/src/soc/mediatek/common/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 0d4add8fca..1f6702d779 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index b148093af0..d8d50022f3 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 7d42493f84..1eec587230 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index d0c6ee9302..f8d6ccaaf0 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 MediaTek Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index efccc0bec8..0002cf5805 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index cc20979f50..cc03240853 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 0a57565d94..502a4406d9 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 4fafb049d2..8a57f9d29d 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index f6c866bfdb..70c98fd79f 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 48bfbef1a5..6364f48846 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index 12f08379ea..1c2560863e 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index 9e459834f5..d82eee6641 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index a29c1c14b6..2afd0ba0fa 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index c701034a52..155c09ddf5 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 22702d31b0..1b9e50b9cd 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index 90834a3ca9..3b99a19cc4 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/da9212.h b/src/soc/mediatek/mt8173/include/soc/da9212.h index 118ba85667..24b5eef7ce 100644 --- a/src/soc/mediatek/mt8173/include/soc/da9212.h +++ b/src/soc/mediatek/mt8173/include/soc/da9212.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/ddp.h index dbac5f7fb9..648c0910d8 100644 --- a/src/soc/mediatek/mt8173/include/soc/ddp.h +++ b/src/soc/mediatek/mt8173/include/soc/ddp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_common.h b/src/soc/mediatek/mt8173/include/soc/dramc_common.h index 084e7de555..0782a1a351 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_common.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index 041cfaa76f..aa5334b3ee 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_register.h b/src/soc/mediatek/mt8173/include/soc/dramc_register.h index ce6517376f..73ca7177a4 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_register.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index e7c1d28b1f..f19f0ececa 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/emi.h b/src/soc/mediatek/mt8173/include/soc/emi.h index e3da2e6a1e..2d584ac3bd 100644 --- a/src/soc/mediatek/mt8173/include/soc/emi.h +++ b/src/soc/mediatek/mt8173/include/soc/emi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h index 8d7db8ba50..b92ad89330 100644 --- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8173/include/soc/flash_controller.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index 8a6e13a6f2..482b6a5f86 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/gpio_base.h b/src/soc/mediatek/mt8173/include/soc/gpio_base.h index ac7f46a017..dccea8ff29 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio_base.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio_base.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h index 619893489a..5a9b067ef7 100644 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/infracfg.h b/src/soc/mediatek/mt8173/include/soc/infracfg.h index 60a5209781..3bf8f8b1c6 100644 --- a/src/soc/mediatek/mt8173/include/soc/infracfg.h +++ b/src/soc/mediatek/mt8173/include/soc/infracfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/mcucfg.h b/src/soc/mediatek/mt8173/include/soc/mcucfg.h index 5c011507e6..301adb3909 100644 --- a/src/soc/mediatek/mt8173/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8173/include/soc/mcucfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 2358c3940c..89ee8f4e31 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/mipi.h b/src/soc/mediatek/mt8173/include/soc/mipi.h index aec0b25bda..0a6389a7e6 100644 --- a/src/soc/mediatek/mt8173/include/soc/mipi.h +++ b/src/soc/mediatek/mt8173/include/soc/mipi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/mt6311.h b/src/soc/mediatek/mt8173/include/soc/mt6311.h index 29063d6fe1..eb058167fc 100644 --- a/src/soc/mediatek/mt8173/include/soc/mt6311.h +++ b/src/soc/mediatek/mt8173/include/soc/mt6311.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h index 65b2f7ce8c..4d3f12bc6a 100644 --- a/src/soc/mediatek/mt8173/include/soc/mt6391.h +++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/pericfg.h b/src/soc/mediatek/mt8173/include/soc/pericfg.h index 5aa854287f..ea5b7102b2 100644 --- a/src/soc/mediatek/mt8173/include/soc/pericfg.h +++ b/src/soc/mediatek/mt8173/include/soc/pericfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index 480ffbfb2d..a18431e8db 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index d6c58a5ca0..aa618c203f 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index 709b61105b..8d35938e1b 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index 58bf517f9d..e813f9f3ae 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index 133c8a30f8..ba603d26ce 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h index 85cfd789ff..7fe9ff69b1 100644 --- a/src/soc/mediatek/mt8173/include/soc/symbols.h +++ b/src/soc/mediatek/mt8173/include/soc/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/include/soc/usb.h b/src/soc/mediatek/mt8173/include/soc/usb.h index 8e74436c6f..66a5195c57 100644 --- a/src/soc/mediatek/mt8173/include/soc/usb.h +++ b/src/soc/mediatek/mt8173/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/memory.c b/src/soc/mediatek/mt8173/memory.c index f17f793cae..c87e4975f2 100644 --- a/src/soc/mediatek/mt8173/memory.c +++ b/src/soc/mediatek/mt8173/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index e55c83b634..c76a8568de 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/mt6311.c b/src/soc/mediatek/mt8173/mt6311.c index 8f0b274cfa..76b53f451e 100644 --- a/src/soc/mediatek/mt8173/mt6311.c +++ b/src/soc/mediatek/mt8173/mt6311.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 3f77c8accc..3e0f55615e 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 494fcadbac..0b8a52a4f7 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index a15447c20f..33fbbe2093 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 9ad4caa89c..759eef47c3 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c index b5c805a595..78e4d119e8 100644 --- a/src/soc/mediatek/mt8173/soc.c +++ b/src/soc/mediatek/mt8173/soc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 1b0de79e34..c41a1d58ad 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c index eb2a1424b2..73709319f4 100644 --- a/src/soc/mediatek/mt8173/timer.c +++ b/src/soc/mediatek/mt8173/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8173/usb.c b/src/soc/mediatek/mt8173/usb.c index a61a64bd8c..89674a93c2 100644 --- a/src/soc/mediatek/mt8173/usb.c +++ b/src/soc/mediatek/mt8173/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c index 23ce5570bf..549965bec2 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c index e4c331e524..5aeb5410f6 100644 --- a/src/soc/mediatek/mt8183/bootblock.c +++ b/src/soc/mediatek/mt8183/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index a54b134e6d..0d31dd3b1f 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/decompressor.c b/src/soc/mediatek/mt8183/decompressor.c index d4a55b36c1..87003d0a0d 100644 --- a/src/soc/mediatek/mt8183/decompressor.c +++ b/src/soc/mediatek/mt8183/decompressor.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 74fa0e2f1d..a2615770ed 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c index bf1fee43a2..999126fe74 100644 --- a/src/soc/mediatek/mt8183/dramc_param.c +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index dc3676a9e3..0ee4794d43 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index b9634a8ca8..65f605ec14 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 3710fc652c..ac8200cbd8 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index f1a2e39563..5fc032f30b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 0664678dd9..717a3abfe0 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index a70c5e175d..23f19de94b 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index c267a1473e..dc97a14403 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/auxadc.h b/src/soc/mediatek/mt8183/include/soc/auxadc.h index aafc8a1df4..3e9d3d99d0 100644 --- a/src/soc/mediatek/mt8183/include/soc/auxadc.h +++ b/src/soc/mediatek/mt8183/include/soc/auxadc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h index 479417c77e..16e5238cb8 100644 --- a/src/soc/mediatek/mt8183/include/soc/ddp.h +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index 4da948ec4a..f933268d1f 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index 1f4148bc8d..bf76f7c828 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index c13aa013ee..62f1fc6476 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 8c1f9efa4d..f6fd688a12 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 8813f94982..eaf1cf4a07 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/efuse.h b/src/soc/mediatek/mt8183/include/soc/efuse.h index 32126abc4e..39428346d3 100644 --- a/src/soc/mediatek/mt8183/include/soc/efuse.h +++ b/src/soc/mediatek/mt8183/include/soc/efuse.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 255a323d1a..7d0541f97c 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/flash_controller.h b/src/soc/mediatek/mt8183/include/soc/flash_controller.h index ec3593c9f9..d9ebc745db 100644 --- a/src/soc/mediatek/mt8183/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8183/include/soc/flash_controller.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h index a0d6262abb..2492f0d37f 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/gpio_base.h b/src/soc/mediatek/mt8183/include/soc/gpio_base.h index 60b80bc63f..782f2a141d 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio_base.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio_base.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h index a75b6f002e..9940247705 100644 --- a/src/soc/mediatek/mt8183/include/soc/i2c.h +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/infracfg.h b/src/soc/mediatek/mt8183/include/soc/infracfg.h index 922d977e2b..7a43066c4f 100644 --- a/src/soc/mediatek/mt8183/include/soc/infracfg.h +++ b/src/soc/mediatek/mt8183/include/soc/infracfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/mcucfg.h b/src/soc/mediatek/mt8183/include/soc/mcucfg.h index 0a1232ad5b..9b825b255d 100644 --- a/src/soc/mediatek/mt8183/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8183/include/soc/mcucfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h index 059bf9be2e..3d7dbb7199 100644 --- a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h +++ b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h @@ -1,5 +1,4 @@ /* - * Copyright (C) 2019 MediaTek Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 996d2ecbc8..6e523d8e32 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 1c3e563df8..047311aec8 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/mt8183.h b/src/soc/mediatek/mt8183/include/soc/mt8183.h index 5591ffd5cc..b1b0170274 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/mt8183.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 5a24e75692..23eaf2bceb 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h index da942303a5..32f40a435f 100644 --- a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index bf120e9387..4b18bff857 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/smi.h b/src/soc/mediatek/mt8183/include/soc/smi.h index e9051c2f5e..5264518207 100644 --- a/src/soc/mediatek/mt8183/include/soc/smi.h +++ b/src/soc/mediatek/mt8183/include/soc/smi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index f718081f67..e7b024319d 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index d0a7aa7608..542eb95800 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h index 627088fdc7..89e279fdf7 100644 --- a/src/soc/mediatek/mt8183/include/soc/sspm.h +++ b/src/soc/mediatek/mt8183/include/soc/sspm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/include/soc/usb.h b/src/soc/mediatek/mt8183/include/soc/usb.h index 57d4e7810d..c0af677d0a 100644 --- a/src/soc/mediatek/mt8183/include/soc/usb.h +++ b/src/soc/mediatek/mt8183/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c index a1405dd0e7..d65b426078 100644 --- a/src/soc/mediatek/mt8183/md_ctrl.c +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -1,5 +1,4 @@ /* - * Copyright (C) 2019 MediaTek Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 15ae9cbeea..5603995e71 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/mmu_operations.c b/src/soc/mediatek/mt8183/mmu_operations.c index 45459fe7bf..449b537d2d 100644 --- a/src/soc/mediatek/mt8183/mmu_operations.c +++ b/src/soc/mediatek/mt8183/mmu_operations.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 4ab0e7ed76..c4272260c6 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c index 32da3e0ea5..4159844bdd 100644 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/mtcmos.c b/src/soc/mediatek/mt8183/mtcmos.c index cfe761b4ac..636399bb5c 100644 --- a/src/soc/mediatek/mt8183/mtcmos.c +++ b/src/soc/mediatek/mt8183/mtcmos.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index ff61303337..0eb7dc8d45 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c index 65584ab8a7..8bd580aac8 100644 --- a/src/soc/mediatek/mt8183/pmic_wrap.c +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 6e17a309fe..063f8ae924 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index 21b2f811d6..33e1eb9d51 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index c77d7ef7d3..76a34e894a 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 020da934ab..ca7a5adfaf 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index 857d3dc56d..beec33b9d8 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index 9400ba388f..4d043cb6ed 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h index 87e80990ba..75589a8ea2 100644 --- a/src/soc/nvidia/tegra/apbmisc.h +++ b/src/soc/nvidia/tegra/apbmisc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 56332e433a..927533ee94 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -1,8 +1,4 @@ /* - * Copyright 2013 Google Inc. - * (C) Copyright 2010 - * NVIDIA Corporation - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h index 9d867cddd4..f2479b6270 100644 --- a/src/soc/nvidia/tegra/displayport.h +++ b/src/soc/nvidia/tegra/displayport.h @@ -3,7 +3,6 @@ * * drivers/video/tegra/dc/dpaux_regs.h * - * Copyright (c) 2014, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 6800c5d944..2297145927 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index 22b7fa9126..b748d1a9d5 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 3ca0e13fa4..1feaa21f25 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 440af69387..127e8830d9 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c index 33ae2ba730..38aad4a261 100644 --- a/src/soc/nvidia/tegra/pingroup.c +++ b/src/soc/nvidia/tegra/pingroup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/pingroup.h b/src/soc/nvidia/tegra/pingroup.h index 3cbbb2027d..1d4db24b47 100644 --- a/src/soc/nvidia/tegra/pingroup.h +++ b/src/soc/nvidia/tegra/pingroup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c index 3174714535..63d490c1d9 100644 --- a/src/soc/nvidia/tegra/pinmux.c +++ b/src/soc/nvidia/tegra/pinmux.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/pinmux.h b/src/soc/nvidia/tegra/pinmux.h index 4b9559ec6e..88d36a58d7 100644 --- a/src/soc/nvidia/tegra/pinmux.h +++ b/src/soc/nvidia/tegra/pinmux.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/pwm.h b/src/soc/nvidia/tegra/pwm.h index dba5465470..7e9e81aae3 100644 --- a/src/soc/nvidia/tegra/pwm.h +++ b/src/soc/nvidia/tegra/pwm.h @@ -1,8 +1,4 @@ /* - * Copyright 2014 Google Inc. - * (C) Copyright 2010 - * NVIDIA Corporation - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/soc/nvidia/tegra/software_i2c.c b/src/soc/nvidia/tegra/software_i2c.c index e215c0275d..77ba0d8480 100644 --- a/src/soc/nvidia/tegra/software_i2c.c +++ b/src/soc/nvidia/tegra/software_i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h index 0cbbd5d9d3..9ddab34a7b 100644 --- a/src/soc/nvidia/tegra/types.h +++ b/src/soc/nvidia/tegra/types.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 2b450c5672..528210c8a4 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra/usb.h b/src/soc/nvidia/tegra/usb.h index 7232c96699..1dc06daf0f 100644 --- a/src/soc/nvidia/tegra/usb.h +++ b/src/soc/nvidia/tegra/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 1793aaf3de..80718393dd 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index dca5314dc9..c177585e88 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -4,14 +4,6 @@ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das * U-Boot, which itself got the file from armboot. * - * Copyright (c) 2004 Texas Instruments - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * Copyright (c) 2006-2008 Syed Mohammed Khasim - * Copyright (c) 2013 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/nvidia/tegra124/cache.c b/src/soc/nvidia/tegra124/cache.c index 5c3a43d0a2..bcec52c601 100644 --- a/src/soc/nvidia/tegra124/cache.c +++ b/src/soc/nvidia/tegra124/cache.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index ac2a92e39d..301245cc8c 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index b2b7490560..5f4a63a417 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 04e7d79fef..aab17051fe 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 6fa3bdf0be..c19d36dc40 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 23efd4c084..d053783c42 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index d8a4f22272..708fa57ae5 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -3,8 +3,6 @@ * * drivers/video/tegra/dc/dp.c * - * Copyright (c) 2011-2013, NVIDIA Corporation. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/i2c.c b/src/soc/nvidia/tegra124/i2c.c index e2c5a44ebe..dd38f8597f 100644 --- a/src/soc/nvidia/tegra124/i2c.c +++ b/src/soc/nvidia/tegra124/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index bb950518c9..92195abfb8 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2013 Google Inc. - * - * (C) Copyright 2010,2011 - * NVIDIA Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/cache.h b/src/soc/nvidia/tegra124/include/soc/cache.h index 73d8e42061..59daca1deb 100644 --- a/src/soc/nvidia/tegra124/include/soc/cache.h +++ b/src/soc/nvidia/tegra124/include/soc/cache.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index 07e710a9f3..f64683c4a8 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 712c479caa..86736c3c7f 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h index f781a83e29..3c7ba8b97d 100644 --- a/src/soc/nvidia/tegra124/include/soc/display.h +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/dma.h b/src/soc/nvidia/tegra124/include/soc/dma.h index 3d6d209153..a3d00bcf10 100644 --- a/src/soc/nvidia/tegra124/include/soc/dma.h +++ b/src/soc/nvidia/tegra124/include/soc/dma.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/early_configs.h b/src/soc/nvidia/tegra124/include/soc/early_configs.h index 75cf3750b5..c0b421895a 100644 --- a/src/soc/nvidia/tegra124/include/soc/early_configs.h +++ b/src/soc/nvidia/tegra124/include/soc/early_configs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/emc.h b/src/soc/nvidia/tegra124/include/soc/emc.h index 8e190f9358..7348d63fea 100644 --- a/src/soc/nvidia/tegra124/include/soc/emc.h +++ b/src/soc/nvidia/tegra124/include/soc/emc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/flow.h b/src/soc/nvidia/tegra124/include/soc/flow.h index 84bf705151..fba1b0cbb5 100644 --- a/src/soc/nvidia/tegra124/include/soc/flow.h +++ b/src/soc/nvidia/tegra124/include/soc/flow.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/gpio.h b/src/soc/nvidia/tegra124/include/soc/gpio.h index 2411cd1199..c85c26bbf6 100644 --- a/src/soc/nvidia/tegra124/include/soc/gpio.h +++ b/src/soc/nvidia/tegra124/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/maincpu.h b/src/soc/nvidia/tegra124/include/soc/maincpu.h index f55aa0d97a..6f8d3da44d 100644 --- a/src/soc/nvidia/tegra124/include/soc/maincpu.h +++ b/src/soc/nvidia/tegra124/include/soc/maincpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/mc.h b/src/soc/nvidia/tegra124/include/soc/mc.h index f249ecc03e..ad8b565b2b 100644 --- a/src/soc/nvidia/tegra124/include/soc/mc.h +++ b/src/soc/nvidia/tegra124/include/soc/mc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 7e2cc7ad58..0128a86048 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/pingroup.h b/src/soc/nvidia/tegra124/include/soc/pingroup.h index 28bb4e7cff..93c64c39a5 100644 --- a/src/soc/nvidia/tegra124/include/soc/pingroup.h +++ b/src/soc/nvidia/tegra124/include/soc/pingroup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/pinmux.h b/src/soc/nvidia/tegra124/include/soc/pinmux.h index 22e728935d..45e5815319 100644 --- a/src/soc/nvidia/tegra124/include/soc/pinmux.h +++ b/src/soc/nvidia/tegra124/include/soc/pinmux.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/pmc.h b/src/soc/nvidia/tegra124/include/soc/pmc.h index b6f60e874a..f4f8523907 100644 --- a/src/soc/nvidia/tegra124/include/soc/pmc.h +++ b/src/soc/nvidia/tegra124/include/soc/pmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/power.h b/src/soc/nvidia/tegra124/include/soc/power.h index 39d55030f9..33afbeb08f 100644 --- a/src/soc/nvidia/tegra124/include/soc/power.h +++ b/src/soc/nvidia/tegra124/include/soc/power.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/sdram.h b/src/soc/nvidia/tegra124/include/soc/sdram.h index dbc2a432db..7e570804be 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 938d655cec..5fbedc8677 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/sor.h b/src/soc/nvidia/tegra124/include/soc/sor.h index 4df2cf4fed..c10fe197ef 100644 --- a/src/soc/nvidia/tegra124/include/soc/sor.h +++ b/src/soc/nvidia/tegra124/include/soc/sor.h @@ -3,7 +3,6 @@ * * drivers/video/tegra/dc/sor_regs.h * - * Copyright (c) 2011-2013, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h index 875e88032a..eca2835044 100644 --- a/src/soc/nvidia/tegra124/include/soc/spi.h +++ b/src/soc/nvidia/tegra124/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/sysctr.h b/src/soc/nvidia/tegra124/include/soc/sysctr.h index 5b5e4c69ea..eb620c3d0f 100644 --- a/src/soc/nvidia/tegra124/include/soc/sysctr.h +++ b/src/soc/nvidia/tegra124/include/soc/sysctr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile index a4bbc07172..bbac1dbc3e 100644 --- a/src/soc/nvidia/tegra124/lp0/Makefile +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -1,6 +1,5 @@ ################################################################################ ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 0ebe8e7056..78bb767c30 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/maincpu.S b/src/soc/nvidia/tegra124/maincpu.S index fc32ed2637..14fe0ec05f 100644 --- a/src/soc/nvidia/tegra124/maincpu.S +++ b/src/soc/nvidia/tegra124/maincpu.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/nvidia/tegra124/monotonic_timer.c b/src/soc/nvidia/tegra124/monotonic_timer.c index 603d151be9..5e587478ca 100644 --- a/src/soc/nvidia/tegra124/monotonic_timer.c +++ b/src/soc/nvidia/tegra124/monotonic_timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 3f1ee7ee95..925f139599 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 0057d2a21e..c90528da7a 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index aade07c9b7..e5e15e0ba0 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 9d5e79f8b0..f2e2c0a00c 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 1eac52917d..c95a625c69 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -3,7 +3,6 @@ * * drivers/video/tegra/dc/sor.c * - * Copyright (c) 2011-2013, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 007d189bc9..89ca081ad4 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -1,8 +1,6 @@ /* * NVIDIA Tegra SPI controller (T114 and later) * - * Copyright (c) 2010-2013 NVIDIA Corporation - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 9bebc72afb..23a8775447 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 6564dcb966..4abc931364 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index 60ca16ca4e..ca102d4aca 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/ape.c b/src/soc/nvidia/tegra210/ape.c index 0ada0dba7b..9a9c57f4a5 100644 --- a/src/soc/nvidia/tegra210/ape.c +++ b/src/soc/nvidia/tegra210/ape.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, NVIDIA CORPORATION. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index e0863d21e1..74ea323f12 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 383e578eeb..7ce8ac7777 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/bootblock_asm.S b/src/soc/nvidia/tegra210/bootblock_asm.S index 6ea154abab..a99da87e8e 100644 --- a/src/soc/nvidia/tegra210/bootblock_asm.S +++ b/src/soc/nvidia/tegra210/bootblock_asm.S @@ -4,14 +4,6 @@ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das * U-Boot, which itself got the file from armboot. * - * Copyright (c) 2004 Texas Instruments - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * Copyright (c) 2006-2008 Syed Mohammed Khasim - * Copyright (c) 2013 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 7fdde9e6ea..8c2bfcd1ae 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index fbda37f952..0685a10c26 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/chip.h b/src/soc/nvidia/tegra210/chip.h index 75d2497186..d43e1badeb 100644 --- a/src/soc/nvidia/tegra210/chip.h +++ b/src/soc/nvidia/tegra210/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 574691a362..2fcbb188c1 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index 4f236c09e3..0ebb62dae8 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 46443cfe72..3f9ba25424 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 155d348106..6220210333 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 42845505d2..0b6f64b454 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -3,8 +3,6 @@ * * drivers/video/tegra/dc/dp.c * - * Copyright (c) 2011-2015, NVIDIA Corporation. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 72bf50f3fa..8dcfffca2e 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/flow_ctrl.c b/src/soc/nvidia/tegra210/flow_ctrl.c index b25e270826..e4f95d5849 100644 --- a/src/soc/nvidia/tegra210/flow_ctrl.c +++ b/src/soc/nvidia/tegra210/flow_ctrl.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/funitcfg.c b/src/soc/nvidia/tegra210/funitcfg.c index 887f9f0801..6f3f260d5b 100644 --- a/src/soc/nvidia/tegra210/funitcfg.c +++ b/src/soc/nvidia/tegra210/funitcfg.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/gic.c b/src/soc/nvidia/tegra210/gic.c index 983f39f5bc..258735fefe 100644 --- a/src/soc/nvidia/tegra210/gic.c +++ b/src/soc/nvidia/tegra210/gic.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/i2c.c b/src/soc/nvidia/tegra210/i2c.c index 2fa1123cec..5895a67fc4 100644 --- a/src/soc/nvidia/tegra210/i2c.c +++ b/src/soc/nvidia/tegra210/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c index 483fd5939c..1dfed4b380 100644 --- a/src/soc/nvidia/tegra210/i2c6.c +++ b/src/soc/nvidia/tegra210/i2c6.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index eaac003a2e..1b5a78f1c4 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -1,11 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. * - * (C) Copyright 2010,2011 - * NVIDIA Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/ccplex.h b/src/soc/nvidia/tegra210/include/soc/ccplex.h index 822be5ee11..76c0347f47 100644 --- a/src/soc/nvidia/tegra210/include/soc/ccplex.h +++ b/src/soc/nvidia/tegra210/include/soc/ccplex.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 42eebedbc7..9b85d046d6 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 1e49299e80..27de8e6fa8 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/clst_clk.h b/src/soc/nvidia/tegra210/include/soc/clst_clk.h index 661fd1d849..800315c7d5 100644 --- a/src/soc/nvidia/tegra210/include/soc/clst_clk.h +++ b/src/soc/nvidia/tegra210/include/soc/clst_clk.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/console_uart.h b/src/soc/nvidia/tegra210/include/soc/console_uart.h index e35b582fa2..a2f98b80a8 100644 --- a/src/soc/nvidia/tegra210/include/soc/console_uart.h +++ b/src/soc/nvidia/tegra210/include/soc/console_uart.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Andre Heider * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/cpu.h b/src/soc/nvidia/tegra210/include/soc/cpu.h index 5e34c0b5d4..5ba358584f 100644 --- a/src/soc/nvidia/tegra210/include/soc/cpu.h +++ b/src/soc/nvidia/tegra210/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/display.h b/src/soc/nvidia/tegra210/include/soc/display.h index 74c289e52d..47424733ab 100644 --- a/src/soc/nvidia/tegra210/include/soc/display.h +++ b/src/soc/nvidia/tegra210/include/soc/display.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 6d934191a4..61048ef47b 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2010-2015 NVIDIA Corporation - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h index 289aa72612..0a4cb740c8 100644 --- a/src/soc/nvidia/tegra210/include/soc/emc.h +++ b/src/soc/nvidia/tegra210/include/soc/emc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/flow.h b/src/soc/nvidia/tegra210/include/soc/flow.h index c30175a597..8e3ae4149b 100644 --- a/src/soc/nvidia/tegra210/include/soc/flow.h +++ b/src/soc/nvidia/tegra210/include/soc/flow.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h index 602c75c5fe..071584720c 100644 --- a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h +++ b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/funitcfg.h b/src/soc/nvidia/tegra210/include/soc/funitcfg.h index b2f76d2d67..953578a4b9 100644 --- a/src/soc/nvidia/tegra210/include/soc/funitcfg.h +++ b/src/soc/nvidia/tegra210/include/soc/funitcfg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/gpio.h b/src/soc/nvidia/tegra210/include/soc/gpio.h index a50947d77d..b181de25f8 100644 --- a/src/soc/nvidia/tegra210/include/soc/gpio.h +++ b/src/soc/nvidia/tegra210/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h index 49081db763..12ab2420bc 100644 --- a/src/soc/nvidia/tegra210/include/soc/id.h +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/maincpu.h b/src/soc/nvidia/tegra210/include/soc/maincpu.h index 90edb6624f..8462455686 100644 --- a/src/soc/nvidia/tegra210/include/soc/maincpu.h +++ b/src/soc/nvidia/tegra210/include/soc/maincpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/mc.h b/src/soc/nvidia/tegra210/include/soc/mc.h index b78305a5a8..9be2a8b4fd 100644 --- a/src/soc/nvidia/tegra210/include/soc/mc.h +++ b/src/soc/nvidia/tegra210/include/soc/mc.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index b7268d114b..ff44591e94 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h index e9b579718f..a4e093b09d 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_display.h b/src/soc/nvidia/tegra210/include/soc/mipi_display.h index 6499c43361..1f1ef53902 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi_display.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi_display.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,8 +15,6 @@ * Defines for Mobile Industry Processor Interface (MIPI(R)) * Display Working Group standards: DSI, DCS, DBI, DPI * - * Copyright (C) 2010 Guennadi Liakhovetski - * Copyright (C) 2006 Nokia Corporation * Author: Imre Deak * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h index eed9ed7d03..4a6120009b 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +14,6 @@ /* * MIPI DSI Bus * - * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd. * Andrzej Hajda * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h index d76e76328c..d9905c0dfb 100644 --- a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h +++ b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h index df13cc4f77..041c7f1bfc 100644 --- a/src/soc/nvidia/tegra210/include/soc/mtc.h +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/padconfig.h b/src/soc/nvidia/tegra210/include/soc/padconfig.h index 227fa7ab82..9fe2962583 100644 --- a/src/soc/nvidia/tegra210/include/soc/padconfig.h +++ b/src/soc/nvidia/tegra210/include/soc/padconfig.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/pinmux.h b/src/soc/nvidia/tegra210/include/soc/pinmux.h index 1919cbb347..d39efeff2b 100644 --- a/src/soc/nvidia/tegra210/include/soc/pinmux.h +++ b/src/soc/nvidia/tegra210/include/soc/pinmux.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/pmc.h b/src/soc/nvidia/tegra210/include/soc/pmc.h index ad0d170225..07017f8945 100644 --- a/src/soc/nvidia/tegra210/include/soc/pmc.h +++ b/src/soc/nvidia/tegra210/include/soc/pmc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/power.h b/src/soc/nvidia/tegra210/include/soc/power.h index 6644a76ab5..0fe53b2d3b 100644 --- a/src/soc/nvidia/tegra210/include/soc/power.h +++ b/src/soc/nvidia/tegra210/include/soc/power.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/romstage.h b/src/soc/nvidia/tegra210/include/soc/romstage.h index 699372da26..d193f9e335 100644 --- a/src/soc/nvidia/tegra210/include/soc/romstage.h +++ b/src/soc/nvidia/tegra210/include/soc/romstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/sdram.h b/src/soc/nvidia/tegra210/include/soc/sdram.h index 78fc1caf8d..4dcb55936b 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_configs.h b/src/soc/nvidia/tegra210/include/soc/sdram_configs.h index b3f6ec2713..f1b842b965 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_configs.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_configs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 0b6f7a0a6d..b77aca1275 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/secure_boot.h b/src/soc/nvidia/tegra210/include/soc/secure_boot.h index e21638a2e4..040d920270 100644 --- a/src/soc/nvidia/tegra210/include/soc/secure_boot.h +++ b/src/soc/nvidia/tegra210/include/soc/secure_boot.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/sor.h b/src/soc/nvidia/tegra210/include/soc/sor.h index a128f9f45d..b7051a4daf 100644 --- a/src/soc/nvidia/tegra210/include/soc/sor.h +++ b/src/soc/nvidia/tegra210/include/soc/sor.h @@ -3,7 +3,6 @@ * * drivers/video/tegra/dc/sor_regs.h * - * Copyright (c) 2011-2015, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h index 46c1c3c063..26e66e06de 100644 --- a/src/soc/nvidia/tegra210/include/soc/spi.h +++ b/src/soc/nvidia/tegra210/include/soc/spi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/sysctr.h b/src/soc/nvidia/tegra210/include/soc/sysctr.h index f182c66e79..3f869c9ebe 100644 --- a/src/soc/nvidia/tegra210/include/soc/sysctr.h +++ b/src/soc/nvidia/tegra210/include/soc/sysctr.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h index 00bf65914f..ae91a24cc3 100644 --- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h index 93bfa5c246..686fe93809 100644 --- a/src/soc/nvidia/tegra210/include/soc/verstage.h +++ b/src/soc/nvidia/tegra210/include/soc/verstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c index f95a819448..931f472ac7 100644 --- a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c +++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h index 39db5c45a7..9898e2d7f7 100644 --- a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h +++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/lp0/Makefile b/src/soc/nvidia/tegra210/lp0/Makefile index a4bbc07172..bbac1dbc3e 100644 --- a/src/soc/nvidia/tegra210/lp0/Makefile +++ b/src/soc/nvidia/tegra210/lp0/Makefile @@ -1,6 +1,5 @@ ################################################################################ ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 6ff95b8ac1..a5bc25c5b0 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright 2013-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 72dd57deda..aa6a7285a7 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/mipi.c b/src/soc/nvidia/tegra210/mipi.c index e222048ba9..0dbbc503b7 100644 --- a/src/soc/nvidia/tegra210/mipi.c +++ b/src/soc/nvidia/tegra210/mipi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index 24a61f18d1..dacbc87ee2 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +14,6 @@ /* * MIPI DSI Bus * - * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd. * Andrzej Hajda * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index 73538b1570..65baaf9987 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/monotonic_timer.c b/src/soc/nvidia/tegra210/monotonic_timer.c index ecedd82873..5e587478ca 100644 --- a/src/soc/nvidia/tegra210/monotonic_timer.c +++ b/src/soc/nvidia/tegra210/monotonic_timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c index 2973518441..d63b5d4bf0 100644 --- a/src/soc/nvidia/tegra210/mtc.c +++ b/src/soc/nvidia/tegra210/mtc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/padconfig.c b/src/soc/nvidia/tegra210/padconfig.c index b054f396b3..a89a240c8b 100644 --- a/src/soc/nvidia/tegra210/padconfig.c +++ b/src/soc/nvidia/tegra210/padconfig.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/power.c b/src/soc/nvidia/tegra210/power.c index 51928aec22..8e7838c5a3 100644 --- a/src/soc/nvidia/tegra210/power.c +++ b/src/soc/nvidia/tegra210/power.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/ram_code.c b/src/soc/nvidia/tegra210/ram_code.c index 91f96ae7a0..91cda6d2ce 100644 --- a/src/soc/nvidia/tegra210/ram_code.c +++ b/src/soc/nvidia/tegra210/ram_code.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 2e01523060..41bbf7b279 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 3bd1a5b1da..ee0d442cad 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/romstage_asm.S b/src/soc/nvidia/tegra210/romstage_asm.S index 110149b0d9..089a44c812 100644 --- a/src/soc/nvidia/tegra210/romstage_asm.S +++ b/src/soc/nvidia/tegra210/romstage_asm.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index 8a7f3d955c..2f91321ddc 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 85550516be..9b882728b2 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index a4cea7082d..c29a810ee6 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 8caf05053a..72da889615 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -3,7 +3,6 @@ * * drivers/video/tegra/dc/sor.c * - * Copyright (c) 2011-2015, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index b0142a4bea..84f1a1de75 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -1,8 +1,6 @@ /* * NVIDIA Tegra SPI controller (T114 and later) * - * Copyright (c) 2010-2013 NVIDIA Corporation - * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/stack.S b/src/soc/nvidia/tegra210/stack.S index 416cdb39f9..7905d5fe1a 100644 --- a/src/soc/nvidia/tegra210/stack.S +++ b/src/soc/nvidia/tegra210/stack.S @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/stage_entry.S b/src/soc/nvidia/tegra210/stage_entry.S index 0eeffce2da..1e8ce79c41 100644 --- a/src/soc/nvidia/tegra210/stage_entry.S +++ b/src/soc/nvidia/tegra210/stage_entry.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index b5cf5d5a40..acdbefa6f0 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index ee781224bd..b199a225a0 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index 19ec083bfd..e53e48805d 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index ffa535c493..6cdf249c8f 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index 79d2eb7271..312d4e945e 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index ac80a76c82..be206aa9dd 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 5a0529e119..51ca3d4e3a 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 9d608fa93d..d25bb87b0d 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2014, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/blsp.c b/src/soc/qualcomm/ipq40xx/blsp.c index 099dc6e2c1..bfbf7027bd 100644 --- a/src/soc/qualcomm/ipq40xx/blsp.c +++ b/src/soc/qualcomm/ipq40xx/blsp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2016 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 9970758d91..4fc4aedfd5 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c index bd1345e4ac..9574c21a15 100644 --- a/src/soc/qualcomm/ipq40xx/clock.c +++ b/src/soc/qualcomm/ipq40xx/clock.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/gpio.c b/src/soc/qualcomm/ipq40xx/gpio.c index 41352419d9..ac4bbdc59f 100644 --- a/src/soc/qualcomm/ipq40xx/gpio.c +++ b/src/soc/qualcomm/ipq40xx/gpio.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index 32a6d1c16e..cb69feb34d 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/blsp.h b/src/soc/qualcomm/ipq40xx/include/soc/blsp.h index ce74e56dcc..2308fd26b6 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/blsp.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/blsp.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h index 1e26dcde52..cdc394b80d 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h index c79c50badc..0355598751 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/clock.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. * Source : APQ8064 LK Boot * * Redistribution and use in source and binary forms, with or without diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h b/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h index 83030e4df9..9be3dc29e1 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * Taken from U-Boot. * diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h index 220ea934cc..350a0805a7 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * Source : APQ8064 LK Boot * * Redistribution and use in source and binary forms, with or without diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h index e4b613f7dc..adbc03c5df 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h @@ -1,10 +1,6 @@ /* - * Copyright (c) 2012 - 2013, 2015 The Linux Foundation. All rights reserved. * - * Copyright (c) 2008, Google Inc. - * All rights reserved. * - * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h b/src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h index 0d0f9d2942..aa6112f7e7 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/ipq_timer.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h index 8cb0f25a8c..82c7b6ed1d 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h b/src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h index 9cf375840f..35cbbb9fc7 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/lcc-reg.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index 6ff1018272..f11bcbf764 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/include/soc/qup.h b/src/soc/qualcomm/ipq40xx/include/soc/qup.h index 7b775433b1..093d33a78c 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/qup.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/qup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h index 98147cf656..4beef62644 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/include/soc/spi.h b/src/soc/qualcomm/ipq40xx/include/soc/spi.h index b91e6ca28f..7c110759db 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/spi.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/spi.h @@ -1,7 +1,6 @@ /* * Register definitions for the IPQ BLSP SPI Controller * - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/usb.h b/src/soc/qualcomm/ipq40xx/include/soc/usb.h index 457ead7ec1..3b249563a4 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/usb.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h b/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h index 134b63f19c..8a8499173f 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/verstage.h b/src/soc/qualcomm/ipq40xx/include/soc/verstage.h index be546ee8eb..5decfac672 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/verstage.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/verstage.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/lcc.c b/src/soc/qualcomm/ipq40xx/lcc.c index db534a41c5..44fd3d172e 100644 --- a/src/soc/qualcomm/ipq40xx/lcc.c +++ b/src/soc/qualcomm/ipq40xx/lcc.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/mbn_header.h b/src/soc/qualcomm/ipq40xx/mbn_header.h index a48de1c883..a55559255a 100644 --- a/src/soc/qualcomm/ipq40xx/mbn_header.h +++ b/src/soc/qualcomm/ipq40xx/mbn_header.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index e46e8fd4b0..8810430545 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/soc.c b/src/soc/qualcomm/ipq40xx/soc.c index 4a19544117..742a8ef38a 100644 --- a/src/soc/qualcomm/ipq40xx/soc.c +++ b/src/soc/qualcomm/ipq40xx/soc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index a02ef54ab7..89186296f3 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/timer.c b/src/soc/qualcomm/ipq40xx/timer.c index 1401730558..9048dea551 100644 --- a/src/soc/qualcomm/ipq40xx/timer.c +++ b/src/soc/qualcomm/ipq40xx/timer.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/tz_wrapper.S b/src/soc/qualcomm/ipq40xx/tz_wrapper.S index 70cc170f64..1df9801692 100644 --- a/src/soc/qualcomm/ipq40xx/tz_wrapper.S +++ b/src/soc/qualcomm/ipq40xx/tz_wrapper.S @@ -1,5 +1,4 @@ /* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 2c4a1b0798..9e20776bdb 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * Source : APQ8064 LK boot * * Redistribution and use in source and binary forms, with or without diff --git a/src/soc/qualcomm/ipq40xx/usb.c b/src/soc/qualcomm/ipq40xx/usb.c index 0d0272c9b2..5b27541a6c 100644 --- a/src/soc/qualcomm/ipq40xx/usb.c +++ b/src/soc/qualcomm/ipq40xx/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 67d54d2b98..c2dfa37ed2 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 2da868b892..0f3294745d 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * Copyright (c) 2014, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 32f303e81e..b605ea6a0b 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 5b7469c3fb..6e0d8c7520 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 019635110a..b0384305df 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/gsbi.c b/src/soc/qualcomm/ipq806x/gsbi.c index 18b1876933..c121062c43 100644 --- a/src/soc/qualcomm/ipq806x/gsbi.c +++ b/src/soc/qualcomm/ipq806x/gsbi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index a94b2aee67..50222a131e 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h index 35659a7fcc..62764cbdd4 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index 47d7d49ce7..4f37c0e3ce 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -1,8 +1,6 @@ /* - * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. * Source : APQ8064 LK Boot * - * Copyright (c) 2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h index 5dcd9b858f..fa97d58cea 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/include/soc/gpio.h b/src/soc/qualcomm/ipq806x/include/soc/gpio.h index 35429917ed..f756ad8096 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/gpio.h +++ b/src/soc/qualcomm/ipq806x/include/soc/gpio.h @@ -1,8 +1,6 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* Source : APQ8064 LK Boot - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq806x/include/soc/gsbi.h b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h index 00c257c4b8..6876c215ae 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/gsbi.h +++ b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h @@ -1,6 +1,4 @@ /* -* Copyright (c) 2004-2011 Atheros Communications Inc. -* Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index d501a81b39..58a3fe6d97 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -1,10 +1,6 @@ /* - * Copyright (c) 2012 - 2013, 2015 The Linux Foundation. All rights reserved. * - * Copyright (c) 2008, Google Inc. - * All rights reserved. * - * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h index 7bbce24df0..3861989f4e 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h index f499b9b390..88f45ca11a 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h @@ -1,7 +1,5 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* * - * Copyright (c) 2010, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq806x/include/soc/lcc-reg.h b/src/soc/qualcomm/ipq806x/include/soc/lcc-reg.h index 2827ac94ed..3992cb610e 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/lcc-reg.h +++ b/src/soc/qualcomm/ipq806x/include/soc/lcc-reg.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 595d939d0b..78aee5d32a 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/include/soc/qup.h b/src/soc/qualcomm/ipq806x/include/soc/qup.h index 2b0cff3914..9587e9d9db 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/qup.h +++ b/src/soc/qualcomm/ipq806x/include/soc/qup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index e7a6d683e8..bc78500e9d 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/include/soc/spi.h b/src/soc/qualcomm/ipq806x/include/soc/spi.h index 3005fa2d1f..fd0598acaf 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/spi.h +++ b/src/soc/qualcomm/ipq806x/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/include/soc/usb.h b/src/soc/qualcomm/ipq806x/include/soc/usb.h index 88883a25c2..a4b43c0bc3 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/usb.h +++ b/src/soc/qualcomm/ipq806x/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h b/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h index 3bbf023dfe..ac5e441357 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h +++ b/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h @@ -1,6 +1,5 @@ /* * This file is part of the coreboot project. - * Copyright (C) 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c index 758447d805..efa1d1c369 100644 --- a/src/soc/qualcomm/ipq806x/lcc.c +++ b/src/soc/qualcomm/ipq806x/lcc.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq806x/mbn_header.h b/src/soc/qualcomm/ipq806x/mbn_header.h index c7b38d3a81..2fc594ac4a 100644 --- a/src/soc/qualcomm/ipq806x/mbn_header.h +++ b/src/soc/qualcomm/ipq806x/mbn_header.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index dabc1f1410..55c2151d36 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c index 90773afb97..77c968bd17 100644 --- a/src/soc/qualcomm/ipq806x/soc.c +++ b/src/soc/qualcomm/ipq806x/soc.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index e2467b9ffd..a6c30d7ee4 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 25eebf4eb9..92934671e5 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/tz_wrapper.S b/src/soc/qualcomm/ipq806x/tz_wrapper.S index 70cc170f64..1df9801692 100644 --- a/src/soc/qualcomm/ipq806x/tz_wrapper.S +++ b/src/soc/qualcomm/ipq806x/tz_wrapper.S @@ -1,5 +1,4 @@ /* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 1b559ceba9..a1948863dc 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -1,8 +1,6 @@ /* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. * Source : APQ8064 LK boot * - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index 003bc7bf0b..e5c33a0667 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c index 42dc28d16c..089d9e425b 100644 --- a/src/soc/qualcomm/qcs405/blsp.c +++ b/src/soc/qualcomm/qcs405/blsp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2016, 2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index 15d1c18fe1..2539445a8f 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index a780c6bcf1..ed408b0d9a 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 28f1bc12b9..e2e03c3e32 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -1,6 +1,5 @@ /* This file is part of the coreboot project. * - * Copyright 2018 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index 5eb99648d9..eab29f390f 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-2019 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index 399afa1cca..d762aa14e1 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index 30a30b6cb2..57472f4905 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018-2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/blsp.h b/src/soc/qualcomm/qcs405/include/soc/blsp.h index 6e55d7dd37..2308fd26b6 100644 --- a/src/soc/qualcomm/qcs405/include/soc/blsp.h +++ b/src/soc/qualcomm/qcs405/include/soc/blsp.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/cdp.h b/src/soc/qualcomm/qcs405/include/soc/cdp.h index 8e33f4b960..e2eeb42ca6 100644 --- a/src/soc/qualcomm/qcs405/include/soc/cdp.h +++ b/src/soc/qualcomm/qcs405/include/soc/cdp.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index 55c1aaf7a8..c021c49fa1 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -1,6 +1,5 @@ /* This file is part of the coreboot project. * - * Copyright 2018 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index 232e05e672..0fdb7f79ae 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h index 7d948ec46e..a35179b775 100644 --- a/src/soc/qualcomm/qcs405/include/soc/iomap.h +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -1,11 +1,5 @@ /* - * Copyright (c) 2012 - 2013, 2015, 2019 The Linux Foundation. - * All rights reserved. * - * Copyright (c) 2008, Google Inc. - * All rights reserved. - * - * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index dd013b5e8f..3110fd15cc 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index bc42e7271a..fa3a56577a 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index f8f9c75972..17bdfabaa1 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 - 2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h index 12f7fd97c7..dc7ecd31a7 100644 --- a/src/soc/qualcomm/qcs405/include/soc/spi.h +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -1,7 +1,6 @@ /* * Register definitions for the IPQ BLSP SPI Controller * - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 45e6988683..1084eb974e 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/uart.h b/src/soc/qualcomm/qcs405/include/soc/uart.h index 5c8a361c7b..a99f38f817 100644 --- a/src/soc/qualcomm/qcs405/include/soc/uart.h +++ b/src/soc/qualcomm/qcs405/include/soc/uart.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.* * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/usb.h b/src/soc/qualcomm/qcs405/include/soc/usb.h index 121be4dfe8..0c56183d2b 100644 --- a/src/soc/qualcomm/qcs405/include/soc/usb.h +++ b/src/soc/qualcomm/qcs405/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index a2d626fd35..a4c618cf56 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index 29b28620af..acbbdad565 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index 6735308143..ffa84a3641 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index e60891c899..4c17cd55e7 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c index 5df24301c1..595ff9b7a4 100644 --- a/src/soc/qualcomm/qcs405/timer.c +++ b/src/soc/qualcomm/qcs405/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 43a6daab91..c9c1b3906b 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -1,5 +1,4 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * Source : APQ8064 LK boot * * Redistribution and use in source and binary forms, with or without diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index b91dc87986..d35c081bcb 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 8b69918d32..87c3c38c09 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 4f97d76c9b..29348c2a24 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index fe81309c7a..7f32742581 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 213c37ff3c..b6b6d46061 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index ad89f85011..b258ce66b4 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 60570f0dc0..5ca34a6380 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h index 5573163a5b..46de9d4c0f 100644 --- a/src/soc/qualcomm/sc7180/include/soc/aop.h +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 383e6d7be2..2a8af28858 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/efuse.h b/src/soc/qualcomm/sc7180/include/soc/efuse.h index baaa97179b..bb673e0a56 100644 --- a/src/soc/qualcomm/sc7180/include/soc/efuse.h +++ b/src/soc/qualcomm/sc7180/include/soc/efuse.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index 56ff1ab3ed..d01f479657 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 732311953e..6a830c2cfa 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h index 735ce17936..c8f16ba713 100644 --- a/src/soc/qualcomm/sc7180/include/soc/mmu.h +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/qspi.h b/src/soc/qualcomm/sc7180/include/soc/qspi.h index c3d1f78196..c80a28c110 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qspi.h +++ b/src/soc/qualcomm/sc7180/include/soc/qspi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Qualcomm Technologies. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index d2a53fbf92..0381393173 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h index 3a8816a027..2401dfc1d6 100644 --- a/src/soc/qualcomm/sc7180/include/soc/usb.h +++ b/src/soc/qualcomm/sc7180/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 2eb8c86994..2d43d79ba9 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 9c05452c9e..5b22c73c7a 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index 30dc1c3387..e1d142e994 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index fbcfc6ed8d..67176970ad 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index c6d4cb15cb..8db3bd8e4f 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c index 5b78c1d047..595ff9b7a4 100644 --- a/src/soc/qualcomm/sc7180/timer.c +++ b/src/soc/qualcomm/sc7180/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index fa0eac8fa7..1190353689 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * Copyright 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index 639f40136e..85772da2e3 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 3c73ee60ce..ba4079a954 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c index 589865ef52..7bbc60f712 100644 --- a/src/soc/qualcomm/sdm845/bootblock.c +++ b/src/soc/qualcomm/sdm845/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index b092a1a610..7f32742581 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index f3b34cf68a..efd7a975e2 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/gpio.c b/src/soc/qualcomm/sdm845/gpio.c index faa0133d57..8cd8d579d5 100644 --- a/src/soc/qualcomm/sdm845/gpio.c +++ b/src/soc/qualcomm/sdm845/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h index 70caa169aa..29c7dca920 100644 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/aop.h b/src/soc/qualcomm/sdm845/include/soc/aop.h index cadf21b7bd..e9eac99235 100644 --- a/src/soc/qualcomm/sdm845/include/soc/aop.h +++ b/src/soc/qualcomm/sdm845/include/soc/aop.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index 1f79d95195..7752c55cb9 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h index 309193cf43..d0a26d5610 100644 --- a/src/soc/qualcomm/sdm845/include/soc/efuse.h +++ b/src/soc/qualcomm/sdm845/include/soc/efuse.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h index bb52097635..e6670b0be8 100644 --- a/src/soc/qualcomm/sdm845/include/soc/gpio.h +++ b/src/soc/qualcomm/sdm845/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index c3a3b4c84a..c13baf8801 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h index c9883bc0bf..c6ab2ca3b2 100644 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ b/src/soc/qualcomm/sdm845/include/soc/mmu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/qspi.h b/src/soc/qualcomm/sdm845/include/soc/qspi.h index 3f83421e72..716d0c59f0 100644 --- a/src/soc/qualcomm/sdm845/include/soc/qspi.h +++ b/src/soc/qualcomm/sdm845/include/soc/qspi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Qualcomm Technologies. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index f01f245a92..8f23a2a6fa 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h index b657676763..f540af1fce 100644 --- a/src/soc/qualcomm/sdm845/include/soc/usb.h +++ b/src/soc/qualcomm/sdm845/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index e63bfed690..b3ced55e46 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c index ae7251a12c..7569e99f07 100644 --- a/src/soc/qualcomm/sdm845/qclib.c +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c index cced567a87..838e3cda95 100644 --- a/src/soc/qualcomm/sdm845/qspi.c +++ b/src/soc/qualcomm/sdm845/qspi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index 14394f78c2..417588d6cc 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c index 27aafa7b72..ccdbba37f2 100644 --- a/src/soc/qualcomm/sdm845/spi.c +++ b/src/soc/qualcomm/sdm845/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c index 5df24301c1..595ff9b7a4 100644 --- a/src/soc/qualcomm/sdm845/timer.c +++ b/src/soc/qualcomm/sdm845/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c index f39e0ef1ae..dd58512b47 100644 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ b/src/soc/qualcomm/sdm845/uart_bitbang.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 85b3cbacc5..f6e7d29cb5 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index ccaa62433a..c1afc6c124 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 060099c230..a9661efbe0 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 916ef22bad..a2bc29b225 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index 391a335475..e438f87fe1 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index 58986d123a..24eadd4498 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/gpio.h b/src/soc/rockchip/common/include/soc/gpio.h index 666037464c..b83f2d7299 100644 --- a/src/soc/rockchip/common/include/soc/gpio.h +++ b/src/soc/rockchip/common/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/i2c.h b/src/soc/rockchip/common/include/soc/i2c.h index 56ad73256e..62039d6727 100644 --- a/src/soc/rockchip/common/include/soc/i2c.h +++ b/src/soc/rockchip/common/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/pwm.h b/src/soc/rockchip/common/include/soc/pwm.h index 4b4b2c0914..7f31ae4e83 100644 --- a/src/soc/rockchip/common/include/soc/pwm.h +++ b/src/soc/rockchip/common/include/soc/pwm.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/rk808.h b/src/soc/rockchip/common/include/soc/rk808.h index e9b5ceea7d..8907306e4c 100644 --- a/src/soc/rockchip/common/include/soc/rk808.h +++ b/src/soc/rockchip/common/include/soc/rk808.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/soc.h b/src/soc/rockchip/common/include/soc/soc.h index f4b07a7476..a0e0eb2856 100644 --- a/src/soc/rockchip/common/include/soc/soc.h +++ b/src/soc/rockchip/common/include/soc/soc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index ce5de83c62..8ab9d84d4c 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h index 69d11845c0..2bed9307d0 100644 --- a/src/soc/rockchip/common/include/soc/vop.h +++ b/src/soc/rockchip/common/include/soc/vop.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index 4e6747de4b..9f1b27fdb8 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c index 66a085cefe..d47a4b3b49 100644 --- a/src/soc/rockchip/common/rk808.c +++ b/src/soc/rockchip/common/rk808.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index d91bae0eac..15c8256786 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/uart.c b/src/soc/rockchip/common/uart.c index 9ae6e1e356..55ebff5af3 100644 --- a/src/soc/rockchip/common/uart.c +++ b/src/soc/rockchip/common/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 1e970b1450..44a41593c0 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 6a44ccd2e0..d7514f9c31 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index e7982f7492..91976d2a69 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 8988804931..a30ac2e95f 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/chip.h b/src/soc/rockchip/rk3288/chip.h index ddf0afbc1d..f96963465a 100644 --- a/src/soc/rockchip/rk3288/chip.h +++ b/src/soc/rockchip/rk3288/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 1c490b47a1..6f8e411b96 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index 00885bc11f..b24b8ff6ba 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index a66b2d42e5..9c918eb40e 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 8eeed888c6..4df0227fc0 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 36a08a9000..b333103964 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) Rockchip, Inc. - * Copyright (C) Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/addressmap.h b/src/soc/rockchip/rk3288/include/soc/addressmap.h index 4842ee675b..e8111abf2e 100644 --- a/src/soc/rockchip/rk3288/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3288/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 40152d7e91..96cf775a8d 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/display.h b/src/soc/rockchip/rk3288/include/soc/display.h index 8ffa9222cf..bf2a855e4a 100644 --- a/src/soc/rockchip/rk3288/include/soc/display.h +++ b/src/soc/rockchip/rk3288/include/soc/display.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/grf.h b/src/soc/rockchip/rk3288/include/soc/grf.h index 4a546ea9b8..4f88f0fe10 100644 --- a/src/soc/rockchip/rk3288/include/soc/grf.h +++ b/src/soc/rockchip/rk3288/include/soc/grf.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index 3089949082..3e496d084a 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Rockchip, Inc. - * Copyright (C) 2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index f8e186c9d6..a6ab1e2f66 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/pmu.h b/src/soc/rockchip/rk3288/include/soc/pmu.h index 5ef9544940..7c69ddd565 100644 --- a/src/soc/rockchip/rk3288/include/soc/pmu.h +++ b/src/soc/rockchip/rk3288/include/soc/pmu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/sdram.h b/src/soc/rockchip/rk3288/include/soc/sdram.h index 3ad51b6fa5..2450de5212 100644 --- a/src/soc/rockchip/rk3288/include/soc/sdram.h +++ b/src/soc/rockchip/rk3288/include/soc/sdram.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/timer.h b/src/soc/rockchip/rk3288/include/soc/timer.h index 1d08fcc1e2..7d15faa443 100644 --- a/src/soc/rockchip/rk3288/include/soc/timer.h +++ b/src/soc/rockchip/rk3288/include/soc/timer.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/tsadc.h b/src/soc/rockchip/rk3288/include/soc/tsadc.h index 1159c4bca4..943446ad55 100644 --- a/src/soc/rockchip/rk3288/include/soc/tsadc.h +++ b/src/soc/rockchip/rk3288/include/soc/tsadc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 3305263458..92db012458 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 9fb27cd326..09cd7bcf87 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index 67fca1f624..82ad878368 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index ea235b3e32..5cd96b4832 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 7a1e34d4a3..608d9ef5fe 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 7f6ad8cac1..12d7af255f 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -1,7 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2016 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index f536f7a6e2..ebad1e2b85 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h index b4b3e75605..8111d564df 100644 --- a/src/soc/rockchip/rk3399/chip.h +++ b/src/soc/rockchip/rk3399/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index d2f5b7c6d1..ee04d5637d 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/decompressor.c b/src/soc/rockchip/rk3399/decompressor.c index a64219beea..463dbd497f 100644 --- a/src/soc/rockchip/rk3399/decompressor.c +++ b/src/soc/rockchip/rk3399/decompressor.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 1db7f99c5e..42d5c2d7aa 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 9a01abc038..1be9ceb0b3 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index 5dca6bb84e..df17bc09b0 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index e2aeaeaa7a..55e79c741c 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h index 880ac8ab4f..860c33a9ab 100644 --- a/src/soc/rockchip/rk3399/include/soc/display.h +++ b/src/soc/rockchip/rk3399/include/soc/display.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index 9bda967269..c6d686ed53 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 4e46e2d764..544d7a474d 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index 469a052a95..dc57a5239b 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/mmu_operations.h b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h index 5f06a451c1..d0fb0a30ce 100644 --- a/src/soc/rockchip/rk3399/include/soc/mmu_operations.h +++ b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/saradc.h b/src/soc/rockchip/rk3399/include/soc/saradc.h index 90f743e9f6..58e946d61c 100644 --- a/src/soc/rockchip/rk3399/include/soc/saradc.h +++ b/src/soc/rockchip/rk3399/include/soc/saradc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index 6fdb7076e5..4c2cccbd76 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/symbols.h b/src/soc/rockchip/rk3399/include/soc/symbols.h index a40a7c48d3..258600aa9c 100644 --- a/src/soc/rockchip/rk3399/include/soc/symbols.h +++ b/src/soc/rockchip/rk3399/include/soc/symbols.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/timer.h b/src/soc/rockchip/rk3399/include/soc/timer.h index 46c69e6a2f..93c4c94054 100644 --- a/src/soc/rockchip/rk3399/include/soc/timer.h +++ b/src/soc/rockchip/rk3399/include/soc/timer.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/tsadc.h b/src/soc/rockchip/rk3399/include/soc/tsadc.h index 082a2bc905..690fd275da 100644 --- a/src/soc/rockchip/rk3399/include/soc/tsadc.h +++ b/src/soc/rockchip/rk3399/include/soc/tsadc.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/include/soc/usb.h b/src/soc/rockchip/rk3399/include/soc/usb.h index c2fa1a2af4..38acad2bc8 100644 --- a/src/soc/rockchip/rk3399/include/soc/usb.h +++ b/src/soc/rockchip/rk3399/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Rockchip, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 5df5fdf1e6..65cf6ea93c 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 713acc04ad..5d57024ea1 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 3fe22f2502..928b31e8e3 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 807a7bce35..7c18fca1e4 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/spi_bitbang.c b/src/soc/rockchip/rk3399/spi_bitbang.c index 628cc16764..96ebb6e7a5 100644 --- a/src/soc/rockchip/rk3399/spi_bitbang.c +++ b/src/soc/rockchip/rk3399/spi_bitbang.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/timer.c b/src/soc/rockchip/rk3399/timer.c index be5f20f7c2..faf8b551ae 100644 --- a/src/soc/rockchip/rk3399/timer.c +++ b/src/soc/rockchip/rk3399/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 9f699150fc..d08d0c0e91 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Rockchip Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index 434a99ef11..991c26eb50 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Rockchip, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index 1ff5d85bcb..2d6b08903e 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/bootblock.c b/src/soc/samsung/exynos5250/bootblock.c index 891d640a39..d9c823b119 100644 --- a/src/soc/samsung/exynos5250/bootblock.c +++ b/src/soc/samsung/exynos5250/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 31463b19b5..295ef01c17 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/chip.h b/src/soc/samsung/exynos5250/chip.h index 12f823eefa..d6b0207e37 100644 --- a/src/soc/samsung/exynos5250/chip.h +++ b/src/soc/samsung/exynos5250/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index f1b11b5a69..2b9cc5015c 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index ca3dbd9921..c4d85abfd7 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 5f9989990d..4523964775 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/dmc_common.c b/src/soc/samsung/exynos5250/dmc_common.c index 379a433de6..265a7aa922 100644 --- a/src/soc/samsung/exynos5250/dmc_common.c +++ b/src/soc/samsung/exynos5250/dmc_common.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index 881e79f562..99a3c2c507 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c index fa5e11cf2a..429fb5237d 100644 --- a/src/soc/samsung/exynos5250/dp-reg.c +++ b/src/soc/samsung/exynos5250/dp-reg.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index a29c61985f..7c9fe30397 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c index 0ae2d2a87a..3a982b7e36 100644 --- a/src/soc/samsung/exynos5250/gpio.c +++ b/src/soc/samsung/exynos5250/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index e9aabf81bf..55acbea00a 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2002 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h index 0833934e7b..46468a0be2 100644 --- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/clk.h b/src/soc/samsung/exynos5250/include/soc/clk.h index fab0444e11..f02663cc14 100644 --- a/src/soc/samsung/exynos5250/include/soc/clk.h +++ b/src/soc/samsung/exynos5250/include/soc/clk.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/cpu.h b/src/soc/samsung/exynos5250/include/soc/cpu.h index d7121a9e38..d0d3612540 100644 --- a/src/soc/samsung/exynos5250/include/soc/cpu.h +++ b/src/soc/samsung/exynos5250/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/dp-core.h b/src/soc/samsung/exynos5250/include/soc/dp-core.h index 49f293ee29..25ae5b1672 100644 --- a/src/soc/samsung/exynos5250/include/soc/dp-core.h +++ b/src/soc/samsung/exynos5250/include/soc/dp-core.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/dp.h b/src/soc/samsung/exynos5250/include/soc/dp.h index b5e65fb2d1..179e2df88c 100644 --- a/src/soc/samsung/exynos5250/include/soc/dp.h +++ b/src/soc/samsung/exynos5250/include/soc/dp.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/dsim.h b/src/soc/samsung/exynos5250/include/soc/dsim.h index 301d0a9498..c36965d6b4 100644 --- a/src/soc/samsung/exynos5250/include/soc/dsim.h +++ b/src/soc/samsung/exynos5250/include/soc/dsim.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/fimd.h b/src/soc/samsung/exynos5250/include/soc/fimd.h index e58891e646..b49ed6cc5f 100644 --- a/src/soc/samsung/exynos5250/include/soc/fimd.h +++ b/src/soc/samsung/exynos5250/include/soc/fimd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/gpio.h b/src/soc/samsung/exynos5250/include/soc/gpio.h index a521bea791..533d4d3f3d 100644 --- a/src/soc/samsung/exynos5250/include/soc/gpio.h +++ b/src/soc/samsung/exynos5250/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/i2c.h b/src/soc/samsung/exynos5250/include/soc/i2c.h index aa458838c4..d5b5c8ed50 100644 --- a/src/soc/samsung/exynos5250/include/soc/i2c.h +++ b/src/soc/samsung/exynos5250/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h b/src/soc/samsung/exynos5250/include/soc/i2s-regs.h index a0e0283a17..46976fd0d2 100644 --- a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h +++ b/src/soc/samsung/exynos5250/include/soc/i2s-regs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 7e052f0f31..db637fff28 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/periph.h b/src/soc/samsung/exynos5250/include/soc/periph.h index 6933f198ca..a1b7ae00ca 100644 --- a/src/soc/samsung/exynos5250/include/soc/periph.h +++ b/src/soc/samsung/exynos5250/include/soc/periph.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/pinmux.h b/src/soc/samsung/exynos5250/include/soc/pinmux.h index 3bb49245d3..9f320d2de9 100644 --- a/src/soc/samsung/exynos5250/include/soc/pinmux.h +++ b/src/soc/samsung/exynos5250/include/soc/pinmux.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/power.h b/src/soc/samsung/exynos5250/include/soc/power.h index 297ee19a4c..8c905b9ba2 100644 --- a/src/soc/samsung/exynos5250/include/soc/power.h +++ b/src/soc/samsung/exynos5250/include/soc/power.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/setup.h b/src/soc/samsung/exynos5250/include/soc/setup.h index 3bda94e21d..80f7c2a37e 100644 --- a/src/soc/samsung/exynos5250/include/soc/setup.h +++ b/src/soc/samsung/exynos5250/include/soc/setup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/spi.h b/src/soc/samsung/exynos5250/include/soc/spi.h index 19ee7f85af..0335aa0819 100644 --- a/src/soc/samsung/exynos5250/include/soc/spi.h +++ b/src/soc/samsung/exynos5250/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/sysreg.h b/src/soc/samsung/exynos5250/include/soc/sysreg.h index 397cdb3592..7bff424d5f 100644 --- a/src/soc/samsung/exynos5250/include/soc/sysreg.h +++ b/src/soc/samsung/exynos5250/include/soc/sysreg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/tmu.h b/src/soc/samsung/exynos5250/include/soc/tmu.h index cb92c16e48..42432f2e07 100644 --- a/src/soc/samsung/exynos5250/include/soc/tmu.h +++ b/src/soc/samsung/exynos5250/include/soc/tmu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/trustzone.h b/src/soc/samsung/exynos5250/include/soc/trustzone.h index 9a4afbffb7..64fc5a1d67 100644 --- a/src/soc/samsung/exynos5250/include/soc/trustzone.h +++ b/src/soc/samsung/exynos5250/include/soc/trustzone.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/uart.h b/src/soc/samsung/exynos5250/include/soc/uart.h index 0f63b01d5d..f4e8919de3 100644 --- a/src/soc/samsung/exynos5250/include/soc/uart.h +++ b/src/soc/samsung/exynos5250/include/soc/uart.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/usb.h b/src/soc/samsung/exynos5250/include/soc/usb.h index 4a92f28e61..cad8667331 100644 --- a/src/soc/samsung/exynos5250/include/soc/usb.h +++ b/src/soc/samsung/exynos5250/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/include/soc/wakeup.h b/src/soc/samsung/exynos5250/include/soc/wakeup.h index d6f27f31fb..47dfbe573f 100644 --- a/src/soc/samsung/exynos5250/include/soc/wakeup.h +++ b/src/soc/samsung/exynos5250/include/soc/wakeup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/pinmux.c b/src/soc/samsung/exynos5250/pinmux.c index 9ddbea56b2..0d51140bb6 100644 --- a/src/soc/samsung/exynos5250/pinmux.c +++ b/src/soc/samsung/exynos5250/pinmux.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index 37369b3482..9387f475e7 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index bacd08ca24..d9a4988923 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/timer.c b/src/soc/samsung/exynos5250/timer.c index 47a6f377ee..d287bfdb73 100644 --- a/src/soc/samsung/exynos5250/timer.c +++ b/src/soc/samsung/exynos5250/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/tmu.c b/src/soc/samsung/exynos5250/tmu.c index e10a43b0a0..663f84f3fd 100644 --- a/src/soc/samsung/exynos5250/tmu.c +++ b/src/soc/samsung/exynos5250/tmu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/trustzone.c b/src/soc/samsung/exynos5250/trustzone.c index 2f366ad9e3..8886f5420d 100644 --- a/src/soc/samsung/exynos5250/trustzone.c +++ b/src/soc/samsung/exynos5250/trustzone.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index cc851e5d3c..f13c573a8e 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 12b658aef3..1303519e9b 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5250/wakeup.c b/src/soc/samsung/exynos5250/wakeup.c index f83343bcff..4e6b4b8469 100644 --- a/src/soc/samsung/exynos5250/wakeup.c +++ b/src/soc/samsung/exynos5250/wakeup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index deb4f029a8..48beb10976 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/bootblock.c b/src/soc/samsung/exynos5420/bootblock.c index 8e517741e3..f98a2a2d1e 100644 --- a/src/soc/samsung/exynos5420/bootblock.c +++ b/src/soc/samsung/exynos5420/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index ffed589ee1..6364bd80f9 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/chip.h b/src/soc/samsung/exynos5420/chip.h index 8bad3caec3..bf86839962 100644 --- a/src/soc/samsung/exynos5420/chip.h +++ b/src/soc/samsung/exynos5420/chip.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index acfab976d5..817277aae0 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index 92abf32081..3c0f6c7601 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 375b370a1b..bcc6878de7 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/dmc_common.c b/src/soc/samsung/exynos5420/dmc_common.c index e9b8128bab..d756142d93 100644 --- a/src/soc/samsung/exynos5420/dmc_common.c +++ b/src/soc/samsung/exynos5420/dmc_common.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 88dc18d2f6..198c4c7486 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -3,7 +3,6 @@ * * DDR3 mem setup file for EXYNOS5 based board * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index c48ea8c230..f1d374e1a3 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -1,5 +1,4 @@ /* - * Copyright (C) 2012 Samsung Electronics * * Author: Donghwa Lee * diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index df579b0ad7..33140e2c33 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -1,5 +1,4 @@ /* - * Copyright (C) 2012 Samsung Electronics * * Author: Donghwa Lee * diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 2b3552abdd..66745037fe 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -1,6 +1,4 @@ /* - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * Author: InKi Dae * Author: Donghwa Lee diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c index 97331a0222..e36cf3acef 100644 --- a/src/soc/samsung/exynos5420/gpio.c +++ b/src/soc/samsung/exynos5420/gpio.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 4dd9caa16a..3fd18f167a 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h index 40af40bd2a..874be235a0 100644 --- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/clk.h b/src/soc/samsung/exynos5420/include/soc/clk.h index 08663ff307..25920f3b43 100644 --- a/src/soc/samsung/exynos5420/include/soc/clk.h +++ b/src/soc/samsung/exynos5420/include/soc/clk.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/cpu.h b/src/soc/samsung/exynos5420/include/soc/cpu.h index f61aa2c9ae..956c1f0d39 100644 --- a/src/soc/samsung/exynos5420/include/soc/cpu.h +++ b/src/soc/samsung/exynos5420/include/soc/cpu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/dp.h b/src/soc/samsung/exynos5420/include/soc/dp.h index 6b33a76294..5797f01256 100644 --- a/src/soc/samsung/exynos5420/include/soc/dp.h +++ b/src/soc/samsung/exynos5420/include/soc/dp.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/dsim.h b/src/soc/samsung/exynos5420/include/soc/dsim.h index 2d6a0c57ad..26d671e9d0 100644 --- a/src/soc/samsung/exynos5420/include/soc/dsim.h +++ b/src/soc/samsung/exynos5420/include/soc/dsim.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/fimd.h b/src/soc/samsung/exynos5420/include/soc/fimd.h index 3e9d6a44f5..1c274a0362 100644 --- a/src/soc/samsung/exynos5420/include/soc/fimd.h +++ b/src/soc/samsung/exynos5420/include/soc/fimd.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/gpio.h b/src/soc/samsung/exynos5420/include/soc/gpio.h index 6a40554003..efe8a8afbd 100644 --- a/src/soc/samsung/exynos5420/include/soc/gpio.h +++ b/src/soc/samsung/exynos5420/include/soc/gpio.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/i2c.h b/src/soc/samsung/exynos5420/include/soc/i2c.h index ab936985fe..7732a16161 100644 --- a/src/soc/samsung/exynos5420/include/soc/i2c.h +++ b/src/soc/samsung/exynos5420/include/soc/i2c.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h b/src/soc/samsung/exynos5420/include/soc/i2s-regs.h index 4d68182364..fafd6194be 100644 --- a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h +++ b/src/soc/samsung/exynos5420/include/soc/i2s-regs.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index ff781d2228..c113bf962c 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/periph.h b/src/soc/samsung/exynos5420/include/soc/periph.h index a4d9abdf78..c79ee38667 100644 --- a/src/soc/samsung/exynos5420/include/soc/periph.h +++ b/src/soc/samsung/exynos5420/include/soc/periph.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/pinmux.h b/src/soc/samsung/exynos5420/include/soc/pinmux.h index 66cddc83ce..4962b454b2 100644 --- a/src/soc/samsung/exynos5420/include/soc/pinmux.h +++ b/src/soc/samsung/exynos5420/include/soc/pinmux.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/power.h b/src/soc/samsung/exynos5420/include/soc/power.h index 9b56fe5b1e..957f5a8cbd 100644 --- a/src/soc/samsung/exynos5420/include/soc/power.h +++ b/src/soc/samsung/exynos5420/include/soc/power.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/setup.h b/src/soc/samsung/exynos5420/include/soc/setup.h index 139f5b756a..a4c9e32453 100644 --- a/src/soc/samsung/exynos5420/include/soc/setup.h +++ b/src/soc/samsung/exynos5420/include/soc/setup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/spi.h b/src/soc/samsung/exynos5420/include/soc/spi.h index 9d51914865..dd26100918 100644 --- a/src/soc/samsung/exynos5420/include/soc/spi.h +++ b/src/soc/samsung/exynos5420/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/sysreg.h b/src/soc/samsung/exynos5420/include/soc/sysreg.h index 6417dfb408..423055747b 100644 --- a/src/soc/samsung/exynos5420/include/soc/sysreg.h +++ b/src/soc/samsung/exynos5420/include/soc/sysreg.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/tmu.h b/src/soc/samsung/exynos5420/include/soc/tmu.h index eade11f0ec..0b75bb665e 100644 --- a/src/soc/samsung/exynos5420/include/soc/tmu.h +++ b/src/soc/samsung/exynos5420/include/soc/tmu.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/trustzone.h b/src/soc/samsung/exynos5420/include/soc/trustzone.h index c195cb81c5..2020754cef 100644 --- a/src/soc/samsung/exynos5420/include/soc/trustzone.h +++ b/src/soc/samsung/exynos5420/include/soc/trustzone.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/uart.h b/src/soc/samsung/exynos5420/include/soc/uart.h index 647b1f1c43..3fb49f7fa4 100644 --- a/src/soc/samsung/exynos5420/include/soc/uart.h +++ b/src/soc/samsung/exynos5420/include/soc/uart.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/usb.h b/src/soc/samsung/exynos5420/include/soc/usb.h index d80857c721..29a5d80946 100644 --- a/src/soc/samsung/exynos5420/include/soc/usb.h +++ b/src/soc/samsung/exynos5420/include/soc/usb.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/include/soc/wakeup.h b/src/soc/samsung/exynos5420/include/soc/wakeup.h index f3ccdb7db4..605e0f6bcf 100644 --- a/src/soc/samsung/exynos5420/include/soc/wakeup.h +++ b/src/soc/samsung/exynos5420/include/soc/wakeup.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/pinmux.c b/src/soc/samsung/exynos5420/pinmux.c index 347c6692c9..f4958a81d5 100644 --- a/src/soc/samsung/exynos5420/pinmux.c +++ b/src/soc/samsung/exynos5420/pinmux.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index b59162eccd..d13b9fa653 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 27c0fa60aa..2b7be9df50 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index ec9002399b..7b8b955dc9 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c index 47a6f377ee..d287bfdb73 100644 --- a/src/soc/samsung/exynos5420/timer.c +++ b/src/soc/samsung/exynos5420/timer.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/tmu.c b/src/soc/samsung/exynos5420/tmu.c index 1bac347120..fb57ce500e 100644 --- a/src/soc/samsung/exynos5420/tmu.c +++ b/src/soc/samsung/exynos5420/tmu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/trustzone.c b/src/soc/samsung/exynos5420/trustzone.c index 34c5562f00..0cf25ee4b6 100644 --- a/src/soc/samsung/exynos5420/trustzone.c +++ b/src/soc/samsung/exynos5420/trustzone.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 41fdd0d29c..ccee71364d 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index 2f141c1b67..b8f5ee2518 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/wakeup.c b/src/soc/samsung/exynos5420/wakeup.c index 2bcc6b4b5e..86615f2516 100644 --- a/src/soc/samsung/exynos5420/wakeup.c +++ b/src/soc/samsung/exynos5420/wakeup.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 97c67bf946..b7464ad1fa 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -1,6 +1,5 @@ # This file is part of the coreboot project. # -# Copyright (C) 2018 Jonathan Neuschäfer # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 3c97c08191..8a1eddab9a 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -1,6 +1,5 @@ # This file is part of the coreboot project. # -# Copyright (C) 2018 Jonathan Neuschäfer # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/bootblock.c b/src/soc/sifive/fu540/bootblock.c index 67e2646bfe..a54f084cd6 100644 --- a/src/soc/sifive/fu540/bootblock.c +++ b/src/soc/sifive/fu540/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index b6b568df8d..7fa39eff8f 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c index 699273eb4c..9c430f28e8 100644 --- a/src/soc/sifive/fu540/clint.c +++ b/src/soc/sifive/fu540/clint.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index ad5e06b65e..acbf1d816d 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/ddrregs.h b/src/soc/sifive/fu540/ddrregs.h index 5f6f35dccc..78b6dce801 100644 --- a/src/soc/sifive/fu540/ddrregs.h +++ b/src/soc/sifive/fu540/ddrregs.h @@ -1,4 +1,3 @@ -/* Copyright (c) 2018 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* See the file LICENSE for further information */ diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h index cd611494bb..97370bdf97 100644 --- a/src/soc/sifive/fu540/include/soc/addressmap.h +++ b/src/soc/sifive/fu540/include/soc/addressmap.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/include/soc/clock.h b/src/soc/sifive/fu540/include/soc/clock.h index 706c9c00f7..093abeb6e5 100644 --- a/src/soc/sifive/fu540/include/soc/clock.h +++ b/src/soc/sifive/fu540/include/soc/clock.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index 46c559cba1..bef009b858 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/include/soc/otp.h b/src/soc/sifive/fu540/include/soc/otp.h index a5b4ca8792..81e0afb873 100644 --- a/src/soc/sifive/fu540/include/soc/otp.h +++ b/src/soc/sifive/fu540/include/soc/otp.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/include/soc/sdram.h b/src/soc/sifive/fu540/include/soc/sdram.h index 8610a7e053..2d01b39b94 100644 --- a/src/soc/sifive/fu540/include/soc/sdram.h +++ b/src/soc/sifive/fu540/include/soc/sdram.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h index 543f9b2035..201dcb629a 100644 --- a/src/soc/sifive/fu540/include/soc/spi.h +++ b/src/soc/sifive/fu540/include/soc/spi.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 SiFive, Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c index 10647f4a1a..5437a713f5 100644 --- a/src/soc/sifive/fu540/otp.c +++ b/src/soc/sifive/fu540/otp.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/regconfig-ctl.h b/src/soc/sifive/fu540/regconfig-ctl.h index e76504d33f..75e2ce468f 100644 --- a/src/soc/sifive/fu540/regconfig-ctl.h +++ b/src/soc/sifive/fu540/regconfig-ctl.h @@ -1,4 +1,3 @@ -/* Copyright (c) 2018 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* See the file LICENSE for further information */ diff --git a/src/soc/sifive/fu540/regconfig-phy.h b/src/soc/sifive/fu540/regconfig-phy.h index 3deaa07145..f642d253e6 100644 --- a/src/soc/sifive/fu540/regconfig-phy.h +++ b/src/soc/sifive/fu540/regconfig-phy.h @@ -1,4 +1,3 @@ -/* Copyright (c) 2018 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* See the file LICENSE for further information */ diff --git a/src/soc/sifive/fu540/sdram.c b/src/soc/sifive/fu540/sdram.c index bf549bfa9f..5fadd1dfc5 100644 --- a/src/soc/sifive/fu540/sdram.c +++ b/src/soc/sifive/fu540/sdram.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index ae57cf6ef0..0a736315ea 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 SiFive, Inc - * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/spi_internal.h b/src/soc/sifive/fu540/spi_internal.h index 97094c1d8c..494878d26c 100644 --- a/src/soc/sifive/fu540/spi_internal.h +++ b/src/soc/sifive/fu540/spi_internal.h @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 SiFive, Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index b59b78902a..b3f9107d5e 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index fc5e110421..565103bb9e 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -1,4 +1,3 @@ -/* Copyright (c) 2018 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* See the file LICENSE for further information */ From 223a30ce11b94fa12b610e23cdb88064f652920a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 14 Feb 2020 13:36:13 +0100 Subject: [PATCH 0504/1463] util/autoport: Correct formatting issues There is no need to use hexadecimal values in azalia codec IDs, nor need to print a redundant "LPC bridge PCI-LPC bridge" comment. Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38901 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- util/autoport/azalia.go | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index d94441b6aa..c98b03cdea 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -26,7 +26,7 @@ const u32 cim_verb_data[] = { codec.SubsystemID) fmt.Fprintf(az, "\t%d,\t\t/* Number of 4 dword sets */\n", len(codec.PinConfig)+1) - fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(%d, 0x%08x),\n", codec.CodecNo, codec.SubsystemID) keys := []int{} @@ -37,7 +37,7 @@ const u32 cim_verb_data[] = { sort.Ints(keys) for _, nid := range keys { - fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(%d, 0x%02x, 0x%08x),\n", codec.CodecNo, nid, codec.PinConfig[nid]) } az.WriteString("\n"); From b0b32196660c8866a42cff3445ed16a9429c65c1 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Thu, 12 Mar 2020 21:37:25 +0530 Subject: [PATCH 0505/1463] mb/google/dedede: Support integratred BT enumeration The integrated BT is routed via USB2 port 8, add USB configuration to support integrated BT enumeration. Change-Id: I46d8c92ba57cd72a91ee15ef4d11f07824c29e9a Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39471 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- .../google/dedede/variants/baseboard/devicetree.cb | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 9a8ad66cdd..ece9672ae8 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -31,10 +31,10 @@ chip soc/intel/tigerlake register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 @@ -190,11 +190,17 @@ chip soc/intel/tigerlake device usb 2.3 on end end chip drivers/usb/acpi - register "desc" = ""Bluetooth"" + register "desc" = ""Discrete Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" device usb 2.4 on end end + chip drivers/usb/acpi + register "desc" = ""Integrated Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.7 on end + end chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" From 117a66070add9e16b8dbec6425fa34ea25c0fa5a Mon Sep 17 00:00:00 2001 From: Franklin He Date: Mon, 16 Mar 2020 12:31:01 +1100 Subject: [PATCH 0506/1463] soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake Enables Gaussian Mixture Model (GMM) if the pci device is enabled in the devicetree for Gemini Lake This ports commit 03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b BUG=b:151115705 BRANCH=none TEST=Flashed to Chromebook, PCI device enabled in cbmem, userspace app that uses device still works Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Signed-off-by: Franklin He Reviewed-on: https://review.coreboot.org/c/coreboot/+/39579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/chip.c | 4 +++- src/soc/intel/apollolake/include/soc/pci_devs.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 178ccac066..5a652608eb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -612,6 +612,7 @@ static void glk_fsp_silicon_init_params_cb( { #if CONFIG(SOC_INTEL_GLK) uint8_t port; + struct device *dev; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { if (!cfg->usb2eye[port].Usb20OverrideEn) @@ -627,7 +628,8 @@ static void glk_fsp_silicon_init_params_cb( cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; } - silconfig->Gmm = 0; + dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM); + silconfig->Gmm = dev ? dev->enabled : 0; /* On Geminilake, we need to override the default FSP PCIe de-emphasis * settings using the device tree settings. This is because PCIe diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 6544b7a019..12a4e8db83 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -46,6 +46,10 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_GLK_DEV_SLOT_GMM 0x03 +#define SA_GLK_DEVFN_GMM PCI_DEVFN(SA_GLK_DEV_SLOT_GMM, 0) +#define SA_GLK_DEV_GMM PCI_DEV(0, SA_GLK_DEV_SLOT_GMM, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_NPK 0x00 From 00cc4c9455c0e7d4399676f5e1aa7490e6ea896d Mon Sep 17 00:00:00 2001 From: Franklin He Date: Tue, 17 Mar 2020 16:33:22 +1100 Subject: [PATCH 0507/1463] src/mainboard/g/octopus: Enables GMM in the devicetree for octopus Adds GMM into the baseboard of Octopus For GLK, PCI device 3 is GMM according to Document#: 569262(Glk EDS Vol-1 rev2-7) Related to Gerrit review 39579 BUG=b:151115705 BRANCH=None TEST=Flashed final image on Chromebook Change-Id: I75b4a835c18c5eeb542b7f7b89deea45a31e47bd Signed-off-by: Franklin He Reviewed-on: https://review.coreboot.org/c/coreboot/+/39600 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 8f8507046e..5404531c8f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -111,7 +111,7 @@ chip soc/intel/apollolake device pci 00.1 on end # - DPTF device pci 00.2 off end # - NPK device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit + device pci 03.0 on end # - Gaussian Mixture Model (GMM) chip drivers/intel/wifi register "wake" = "GPE0A_CNVI_PME_STS" device pci 0c.0 on end # - CNVi From c4917775fd310b93681c172d2e6b5a871b3dd36d Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Thu, 5 Mar 2020 16:18:16 +0800 Subject: [PATCH 0508/1463] soc/mediatek/mt8183: Improve the AC timing of DRAMC Set more AC timing items to make the system more stable. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Ibd003582a3ffab1ae91f6378651c2c9e585c4676 Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39314 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/emi.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 5fc032f30b..85a75befdd 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -63,6 +63,8 @@ const u8 phy_mapping[CHANNEL_MAX][16] = { struct optimize_ac_time { u8 rfc; u8 rfc_05t; + u8 rfc_pb; + u8 rfrc_pb05t; u16 tx_ref_cnt; }; @@ -332,19 +334,27 @@ static void dramc_init_pre_settings(void) static void dramc_ac_timing_optimize(u8 freq_group) { struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138}, + [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, + .rfrc_pb05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, + .rfrc_pb05t = 0, .tx_ref_cnt = 91}, + [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, + .rfrc_pb05t = 0, .tx_ref_cnt = 119}, + [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, + .rfrc_pb05t = 1, .tx_ref_cnt = 138}, }; for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], 0xff << 16, rf_cab_opt[freq_group].rfc << 16); - clrbits32(&ch[chn].ao.shu[0].ac_time_05t, - rf_cab_opt[freq_group].rfc_05t << 2); + clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, + 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); clrsetbits32(&ch[chn].ao.shu[0].actim[4], 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + clrsetbits32(&ch[chn].ao.shu[0].actim[3], + 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, + 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); } } From 31b081a48d1cd654624c17b32265bd1e079e3912 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Wed, 18 Mar 2020 13:49:00 +0800 Subject: [PATCH 0509/1463] soc/mediatek/mt8183: Fix wrong setting of DRS config Update setting of DRS config. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39626 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 0ee4794d43..850f2b2ba1 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -485,9 +485,10 @@ void dramc_runtime_config(void) /* DRAM DRS DISABLE */ clrsetbits32(&ch[chn].ao.drsctrl, - (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), - (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | - (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + (0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) | + (0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21), + (0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) | + (0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } dramc_dqs_precalculation_preset(); From 11637452cc093a64e078edebe1d6e18b462c3757 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Thu, 6 Feb 2020 14:20:57 -0800 Subject: [PATCH 0510/1463] soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT FSP needs to know to allow the root ports for USB4/TBT to be enabled This patch may need additional checks for each board as it might not be the right thing to turn them all on for every Tiger Lake board. BUG=b:141609883 BRANCH=NONE TEST=Built image and verified that the root ports were visible with lspci Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/fsp_params_tgl.c | 9 ++++++++ .../intel/tigerlake/romstage/fsp_params_tgl.c | 23 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index f3f700f146..a8be407d23 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -186,6 +186,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable Hybrid storage auto detection */ params->HybridStorageMode = config->HybridStorageMode; + /* USB4/TBT */ + for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { + dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); + if (dev) + params->ITbtPcieRootPortEn[i] = dev->enabled; + else + params->ITbtPcieRootPortEn[i] = 0; + } + mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index e275e59fcc..95f637e4ec 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -120,6 +120,29 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn; + /* USB4/TBT */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + if (dev) + m_cfg->TcssItbtPcie0En = dev->enabled; + else + m_cfg->TcssItbtPcie0En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + if (dev) + m_cfg->TcssItbtPcie1En = dev->enabled; + else + m_cfg->TcssItbtPcie1En = 0; + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + if (dev) + m_cfg->TcssItbtPcie2En = dev->enabled; + else + m_cfg->TcssItbtPcie2En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + if (dev) + m_cfg->TcssItbtPcie3En = dev->enabled; + else + m_cfg->TcssItbtPcie3En = 0; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ From 7eeaeeecc590d22a8f51175ba07cf2cfade19bfc Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Tue, 17 Mar 2020 16:58:02 +0530 Subject: [PATCH 0511/1463] soc/intel/tigerlake: Correct number of gpio group for Jasper Lake Correct number of gpio pad group for Jasper Lake SoC. BUG=None BRANCH=None Test=Code compilation for Jasper Lake RVP Change-Id: I381d0e48430e933569a3b22b66b4e6077383e9e2 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39604 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h index 6cfb1873cb..2ee52b260f 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h @@ -34,7 +34,7 @@ #define GPP_GPD 0xA #define GPP_E 0xD -#define GPIO_NUM_GROUPS 11 +#define GPIO_NUM_GROUPS 12 #define GPIO_MAX_NUM_PER_GROUP 24 /* From b6b8575c0ae97f0b34a2ea08f0b3e7bdf3b805bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 19 Sep 2019 17:02:28 +0200 Subject: [PATCH 0512/1463] util/inteltool: powermgt: make Sunrise Point dumping work MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The existing Sunrise Point ids are assigned to the wrong implementation, which would never work for these chipsets. Assign them to the right dumping implementation, which works for both Sunrise Point PCH-H and PCH-LP. This also adds some missing device ids from doc#332691-003EN and doc#334659-005. Change-Id: Id102ef3809d675dc9a915d2cb3062e093487fa27 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39508 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- util/inteltool/powermgt.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 3f489b88fa..70f8c48f0d 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -745,16 +745,6 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; pm_registers_size = ARRAY_SIZE(pch_pm_registers); @@ -828,15 +818,35 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) pm_registers = i82371xx_pm_registers; pm_registers_size = ARRAY_SIZE(i82371xx_pm_registers); break; - case PCI_DEVICE_ID_INTEL_I63XX: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = i63xx_pm_registers; pm_registers_size = ARRAY_SIZE(i63xx_pm_registers); break; - - case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: + case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_HM175: + case PCI_DEVICE_ID_INTEL_QM175: + case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 2); if (!acpi) { From 55292315988899a371bfa225ed9ce73d36697ed8 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 17 Mar 2020 19:17:11 +0100 Subject: [PATCH 0513/1463] AUTHORS: Add authors from util/ Remove the list of converted trees now that all are in here. Removal can be a separate step, but from now on the expectation is that new authors add themselves to AUTHORS. Change-Id: Ic0bd0f05a38547a139b90d17f3872f31392bd8a3 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39616 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- AUTHORS | 42 ++++++++++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/AUTHORS b/AUTHORS index f3c0aaa986..2534a4625c 100644 --- a/AUTHORS +++ b/AUTHORS @@ -15,14 +15,17 @@ Advanced Computing Lab, LANL Advanced Micro Devices, Inc. AdaCore AG Electronics Ltd. +Alex Thiessen Alex Züpke Alexander Couzens Alexandru Gagniuc Analog Devices Inc. Analogix Semiconductor Andre Heider +Andriy Gapon Andy Fleming Angel Pons +Anton Kochkov ARM Limited and Contributors Arthur Heymans Asami Doi @@ -32,12 +35,14 @@ Atmel Corporation BAP - Bruhnspace Advanced Projects Bill Xie Bitland Tech Inc. +Boris Barbulovski Carl-Daniel Hailfinger Cavium Inc. Christoph Grenz Code Aurora Forum coresystems GmbH Corey Osgood +Curt Brune Damien Zammit Dave Airlie David Brownell @@ -45,8 +50,10 @@ David Greenman David Hendricks David Mosberger-Tang David Mueller +Denis 'GNUtoo' Carikli Denis Dowling DENX Software Engineering +Derek Waldner Digital Design Corporation DMP Electronics Inc. Drew Eckhardt @@ -90,8 +97,10 @@ Isaku Yamahata Ivan Vatlin James Ye Jason Zhao +Joe Pillow Johanna Schander Jonas 'Sortie' Termansen +Jonathan A. Kollasch Jonathan Neuschäfer Jordan Crouse Joseph Smith @@ -102,6 +111,7 @@ Kevin O'Connor Kontron Europe GmbH Kshitij Kyösti Mälkki +Leah Rowe Lei Wen Li-Ta Lo Libra Li @@ -110,6 +120,7 @@ Linaro Limited Linus Torvalds Linux Networx, Inc. LiPPERT ADLINK Technology GmbH +Lubomir Rintel Luc Verhaegen Maciej Matuszczyk Marc Bertens @@ -118,12 +129,14 @@ Marek Vasut Marius Gröger Martin Mares Martin Renters +Martin Roth Marvell International Ltd. Marvell Semiconductor Inc. Matt DeVillier Maxim Polyakov MediaTek Inc. Michael Schroeder +Michael Niewöhner Mika Westerberg Mondrian Nuessle MontaVista Software, Inc. @@ -134,8 +147,11 @@ Nick Barker Nico Huber Nico Rikken Nicola Corna +Nils Jacobs +Nir Tzachar Nokia Corporation NVIDIA Corporation +Olivier Langlois Ollie Lo Omar Pakker Online SAS @@ -149,6 +165,7 @@ PC Engines GmbH Per Odlund Peter Stuge Philipp Degler +Philipp Deppenwiese Philipp Hug Protectli Purism SPC @@ -159,17 +176,24 @@ Reinhard Meyer Renze Nicolai Richard Spiegel Richard Woodruff +Rob Landley Robert Reeves +Robinson P. Tryon Rockchip, Inc. +Romain Lievin +Roman Zippel Ronald G. Minnich Rudolf Marek Russell King +Ruud Schramp Sage Electronic Engineering, LLC +Sam Ravnborg Samsung Electronics Samuel Holland SciTech Software, Inc. Sebastian Grzywna secunet Security Networks AG +Sencore Inc Sergej Ivanov Siemens AG SiFive, Inc @@ -178,12 +202,14 @@ Silverback Ltd. Stefan Reinauer Stefan Tauner Steve Magnani +Steve Shenton ST Microelectronics SUSE LINUX AG Sven Schnelle Syed Mohammed Khasim System76 Texas Instruments +The Android Open Source Project The ChromiumOS Authors The Linux Foundation The Regents of the University of California @@ -197,25 +223,17 @@ ucRobotics Inc. University of Heidelberg Uwe Hermann VIA Technologies, Inc +Vikram Narayanan Vipin Kumar Vladimir Serbinenko Vlado Cibic Wang Qing Pei Ward Vandewege +Wilbert Duijvenvoorde Win Enterprises Wiwynn Corp. Wolfgang Denk +YADRO Yann Collet Yinghai Lu - - - -# Directories transferred -src/acpi -src/arch -src/commonlib -src/console -src/cpu -src/device -src/drivers -src/superio +Zachary Yedidia From dc1c30ac17926415681db6bc27886260071d8256 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 17 Mar 2020 15:24:32 +0100 Subject: [PATCH 0514/1463] util/lint/spelling.txt: Explain the commented-out entries If they were removed instead, it would be too easy to end up adding them back again. They are kept in a comment so that they can be tracked. Also, explain why these two entries have been commented out. Change-Id: I8225944b5e3d1e022af169dda33e0344d4c3bccd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39618 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- util/lint/spelling.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 1263144d9e..58fe30d406 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -7,10 +7,15 @@ # The format of each line is: # mistake||correction # -# Note that "sepc" and "acknowledgement" have been commented out. - +# Some entries may trigger false-positives, and have been commented out: +# +# Reason: Both spellings are correct. #acknowledgement||acknowledgment +# +# Reason: On RISC-V, `SEPC` is the name of a register. #sepc||spec +# + ACII||ASCII Debiab||Debian FTBS||FTBFS From 1cd7d3e664fcf119a2b2f5e3fd8824b5682c6807 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 17 Mar 2020 15:30:46 +0100 Subject: [PATCH 0515/1463] util/lint/spelling.txt: Disable `afe` Uppercase `AFE` is an acronym for `Analog Front-End`. As it is a valid spelling, comment out its entry to prevent false positives. Change-Id: Ib8612d970d33d4955c572838bda217cfdb49dfe6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39619 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- util/lint/spelling.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 58fe30d406..87380779bc 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -12,6 +12,9 @@ # Reason: Both spellings are correct. #acknowledgement||acknowledgment # +# Reason: AFE means `Analog Front-End`, and appears on register names. +#afe||safe +# # Reason: On RISC-V, `SEPC` is the name of a register. #sepc||spec # @@ -343,7 +346,6 @@ advertisment||advertisement adviced||advised afecting||affecting afer||after -afe||safe affortable||affordable afforts||affords affort||afford From 7c49cb8f9ca86e791c392da40e7f0d3cb7ed47f3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 16 Mar 2020 23:17:32 +0100 Subject: [PATCH 0516/1463] nb/intel/sandybridge: Tidy up code and comments - Reformat some lines of code - Move MCHBAR registers and documentation into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) With BUILD_TIMELESS=1, this commit does not change the result of: - Asus P8Z77-V LX2 with native raminit. - Asus P8Z77-M PRO with MRC raminit. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599 Reviewed-by: Felix Held Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/acpi.c | 50 +- src/northbridge/intel/sandybridge/bootblock.c | 18 +- src/northbridge/intel/sandybridge/chip.h | 24 +- .../intel/sandybridge/early_init.c | 132 +- src/northbridge/intel/sandybridge/finalize.c | 46 +- src/northbridge/intel/sandybridge/gma.c | 98 +- src/northbridge/intel/sandybridge/gma.h | 9 +- .../intel/sandybridge/mchbar_regs.h | 430 +++++ src/northbridge/intel/sandybridge/memmap.c | 28 +- .../intel/sandybridge/northbridge.c | 135 +- src/northbridge/intel/sandybridge/pcie.c | 14 +- src/northbridge/intel/sandybridge/pei_data.h | 70 +- src/northbridge/intel/sandybridge/raminit.c | 214 +-- src/northbridge/intel/sandybridge/raminit.h | 2 +- .../intel/sandybridge/raminit_common.c | 1542 ++++++++--------- .../intel/sandybridge/raminit_common.h | 64 +- .../intel/sandybridge/raminit_ivy.c | 425 ++--- .../intel/sandybridge/raminit_mrc.c | 194 +-- .../intel/sandybridge/raminit_native.h | 4 +- .../intel/sandybridge/raminit_sandy.c | 224 ++- src/northbridge/intel/sandybridge/romstage.c | 14 +- .../intel/sandybridge/sandybridge.h | 290 +--- 22 files changed, 2029 insertions(+), 1998 deletions(-) create mode 100644 src/northbridge/intel/sandybridge/mchbar_regs.h diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 074e9413fa..d0434259d4 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -33,38 +33,39 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current; - pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - // MMCFG not supported or not enabled. + /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) return current; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + case 0: /* 256MB */ + pciexbar = pciexbar_reg & (0xffffffffULL << 28); max_buses = 256; break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + case 1: /* 128M */ + pciexbar = pciexbar_reg & (0xffffffffULL << 27); max_buses = 128; break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + case 2: /* 64M */ + pciexbar = pciexbar_reg & (0xffffffffULL << 26); max_buses = 64; break; - default: // RSVD + default: /* RSVD */ return current; } if (!pciexbar) return current; - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, + max_buses - 1); return current; } + static unsigned long acpi_create_igfx_rmrr(const unsigned long current) { const u32 base_mask = ~(u32)(MiB - 1); @@ -73,7 +74,7 @@ static unsigned long acpi_create_igfx_rmrr(const unsigned long current) if (!host) return 0; - const u32 bgsm = pci_read_config32(host, BGSM) & base_mask; + const u32 bgsm = pci_read_config32(host, BGSM) & base_mask; const u32 tolud = pci_read_config32(host, TOLUD) & base_mask; if (!bgsm || !tolud) return 0; @@ -89,7 +90,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) unsigned long tmp; tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -104,34 +105,37 @@ static unsigned long acpi_fill_dmar(unsigned long current) } const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); + + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, - unsigned long current, +unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { - const u32 capid0_a = pci_read_config32(dev, 0xe4); + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); if (capid0_a & (1 << 23)) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); + acpi_add_table(rsdp, dmar); current = acpi_align_current(current); printk(BIOS_DEBUG, "current = %lx\n", current); diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index b6ba395080..9dfeed6a4a 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -20,19 +20,17 @@ void bootblock_early_northbridge_init(void) uint32_t reg; /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the + * The "io" variant of the config access is explicitly used to setup the + * PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to to true. That way, all + * subsequent non-explicit config accesses use MCFG. This code also assumes + * that bootblock_northbridge_init() is the first thing called in the non-asm + * boot block code. The final assumption is that no assembly code is using the * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 5f5bf31f34..83181567a5 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -19,9 +19,9 @@ /* * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse + * 0x04 = Enabled, 2ms short pulse * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse + * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ struct northbridge_intel_sandybridge_config { @@ -48,7 +48,7 @@ struct northbridge_intel_sandybridge_config { struct i915_gpu_controller_info gfx; /* - * Maximum PCI mmio size in MiB. + * Maximum PCI MMIO size in MiB. */ u16 pci_mmio_size; @@ -63,7 +63,8 @@ struct northbridge_intel_sandybridge_config { bool ec_present; bool ddr3lv_support; - /* N mode functionality. Leave this setting at 0. + /* + * N mode functionality. Leave this setting at 0. * 0 Auto * 1 1N * 2 2N @@ -74,12 +75,13 @@ struct northbridge_intel_sandybridge_config { DDR_NMODE_2N, } nmode; - /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows - * for DIMM SPD data to specify whether double-rate is required for - * extended operating temperature range. - * 0 Enable double rate based upon temperature thresholds - * 1 Normal rate - * 2 Always enable double rate + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to + * specify whether double-rate is required for extended operating temperature range. + * + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate */ enum { DDR_REFRESH_RATE_TEMP_THRES = 0, @@ -93,7 +95,7 @@ struct northbridge_intel_sandybridge_config { * [1] = overcurrent pin * [2] = length * - * Ports 0-7 can be mapped to OC0-OC3 + * Ports 0-7 can be mapped to OC0-OC3 * Ports 8-13 can be mapped to OC4-OC7 * * Port Length diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 10ac071f52..390fadca65 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -25,49 +25,49 @@ static void systemagent_vtd_init(void) { - const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); if (capid0_a & (1 << 23)) return; - /* setup BARs */ - MCHBAR32(VTD1_BASE + 4) = IOMMU_BASE1 >> 32; - MCHBAR32(VTD1_BASE) = IOMMU_BASE1 | 1; - MCHBAR32(VTD2_BASE + 4) = IOMMU_BASE2 >> 32; - MCHBAR32(VTD2_BASE) = IOMMU_BASE2 | 1; + /* Setup BARs */ + MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE >> 32; + MCHBAR32(GFXVTBAR) = GFXVT_BASE | 1; + MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE >> 32; + MCHBAR32(VTVC0BAR) = VTVC0_BASE | 1; - /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + /* Lock policies */ + write32((void *)(GFXVT_BASE + 0xff0), 0x80000000); const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + write32((void *)(VTVC0_BASE + 0xff0), 0x20000000); + write32((void *)(VTVC0_BASE + 0xff0), 0xa0000000); } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + write32((void *)(VTVC0_BASE + 0xff0), 0x80000000); } } static void enable_pam_region(void) { - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); } static void sandybridge_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); printk(BIOS_DEBUG, " done\n"); } @@ -76,10 +76,9 @@ static void sandybridge_setup_graphics(void) { u32 reg32; u16 reg16; - u8 reg8; - u8 gfxsize; + u8 reg8, gfxsize; - reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); + reg16 = pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID); switch (reg16) { case 0x0102: /* GT1 Desktop */ case 0x0106: /* GT1 Mobile */ @@ -105,7 +104,7 @@ static void sandybridge_setup_graphics(void) /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ gfxsize = 0; } - reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); + reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; reg16 |= (gfxsize + 1) << 3; /* Program GTT memory by setting GGC[9:8] = 2MB */ @@ -113,7 +112,7 @@ static void sandybridge_setup_graphics(void) reg16 |= 2 << 8; /* Enable VGA decode */ reg16 &= ~0x0002; - pci_write_config16(PCI_DEV(0,0,0), GGC, reg16); + pci_write_config16(HOST_BRIDGE, GGC, reg16); /* Enable 256MB aperture */ reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); @@ -123,7 +122,7 @@ static void sandybridge_setup_graphics(void) /* Erratum workarounds */ reg32 = MCHBAR32(SAPMCTL); - reg32 |= (1 << 9)|(1 << 10); + reg32 |= (1 << 9) | (1 << 10); MCHBAR32(SAPMCTL) = reg32; /* Enable SA Clock Gating */ @@ -131,52 +130,56 @@ static void sandybridge_setup_graphics(void) MCHBAR32(SAPMCTL) = reg32 | 1; /* GPU RC6 workaround for sighting 366252 */ - reg32 = MCHBAR32(0x5d14); + reg32 = MCHBAR32(SSKPD_HI); reg32 |= (1 << 31); - MCHBAR32(0x5d14) = reg32; + MCHBAR32(SSKPD_HI) = reg32; - /* VLW */ + /* VLW (Virtual Legacy Wire?) */ reg32 = MCHBAR32(0x6120); reg32 &= ~(1 << 0); MCHBAR32(0x6120) = reg32; - reg32 = MCHBAR32(PAIR_CTL); + reg32 = MCHBAR32(INTRDIRCTL); reg32 |= (1 << 4) | (1 << 5); - MCHBAR32(PAIR_CTL) = reg32; + MCHBAR32(INTRDIRCTL) = reg32; } static void start_peg_link_training(void) { - u32 tmp; - u32 deven; + u32 tmp, deven; - /* PEG on IvyBridge+ needs a special startup sequence. - * As the MRC has its own initialization code skip it. */ - if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & - BASE_REV_MASK) != BASE_REV_IVB) || - CONFIG(HAVE_MRC)) + const u16 base_rev = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK; + /* + * PEG on IvyBridge+ needs a special startup sequence. + * As the MRC has its own initialization code skip it. + */ + if ((base_rev != BASE_REV_IVB) || CONFIG(HAVE_MRC)) return; - deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + deven = pci_read_config32(HOST_BRIDGE, DEVEN); + /* + * For each PEG device, set bit 5 to use three retries for OC (Offset Calibration). + * We also clear DEFER_OC (bit 16) in order to start PEG training. + */ if (deven & DEVEN_PEG10) { - tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5)); + tmp = pci_read_config32(PCI_DEV(0, 1, 0), AFE_PWRON) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 0), AFE_PWRON, tmp | (1 << 5)); } if (deven & DEVEN_PEG11) { - tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5)); + tmp = pci_read_config32(PCI_DEV(0, 1, 1), AFE_PWRON) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 1), AFE_PWRON, tmp | (1 << 5)); } if (deven & DEVEN_PEG12) { - tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5)); + tmp = pci_read_config32(PCI_DEV(0, 1, 2), AFE_PWRON) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 2), AFE_PWRON, tmp | (1 << 5)); } if (deven & DEVEN_PEG60) { - tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5)); + tmp = pci_read_config32(PCI_DEV(0, 6, 0), AFE_PWRON) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 6, 0), AFE_PWRON, tmp | (1 << 5)); } } @@ -187,17 +190,17 @@ void systemagent_early_init(void) u8 reg8; /* Device ID Override Enable should be done very early */ - capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); if (capid0_a & (1 << 10)) { const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); + reg8 = pci_read_config8(HOST_BRIDGE, DIDOR); reg8 &= ~7; /* Clear 2:0 */ if (is_mobile) reg8 |= 1; /* Set bit 0 */ - pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); + pci_write_config8(HOST_BRIDGE, DIDOR, reg8); } /* Setup all BARs required for early PCIe and raminit */ @@ -210,24 +213,25 @@ void systemagent_early_init(void) systemagent_vtd_init(); /* Device Enable, don't touch PEG bits */ - deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); + deven = pci_read_config32(HOST_BRIDGE, DEVEN) | DEVEN_IGD; + pci_write_config32(HOST_BRIDGE, DEVEN, deven); sandybridge_setup_graphics(); - /* Write magic value to start PEG link training. - * This should be done in PCI device enumeration, but - * the PCIe specification requires to wait at least 100msec - * after reset for devices to come up. - * As we don't want to increase boot time, enable it early and - * assume the PEG is up as soon as PCI enumeration starts. - * TODO: use time stamps to ensure the timings are met */ + /* + * Write magic values to start PEG link training. This should be done in PCI device + * enumeration, but the PCIe specification requires to wait at least 100msec after + * reset for devices to come up. As we don't want to increase boot time, enable it + * early and assume that PEG is up as soon as PCI enumeration starts. + * + * TODO: use timestamps to ensure the timings are met. + */ start_peg_link_training(); } void northbridge_romstage_finalize(int s3resume) { - MCHBAR16(SSKPD) = 0xCAFE; + MCHBAR16(SSKPD_HI) = 0xCAFE; romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 6a3156e4bc..ab2a21c37f 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -16,36 +16,34 @@ #include #include "sandybridge.h" -#define PCI_DEV_SNB PCI_DEV(0, 0, 0) - void intel_sandybridge_finalize_smm(void) { - pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); - pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); - pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, MESEG_MASK, MELCK); - pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); - pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TOUUD, 1 << 0); - pci_or_config32(PCI_DEV_SNB, BDSM, 1 << 0); - pci_or_config32(PCI_DEV_SNB, BGSM, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TSEGMB, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TOLUD, 1 << 0); + pci_or_config16(HOST_BRIDGE, GGC, 1 << 0); + pci_or_config16(HOST_BRIDGE, PAVPC, 1 << 2); + pci_or_config32(HOST_BRIDGE, DPR, 1 << 0); + pci_or_config32(HOST_BRIDGE, MESEG_MASK, MELCK); + pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0); + pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0); + pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); - MCHBAR32_OR(MMIO_PAVP_CTL, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ + MCHBAR32_OR(REQLIM, 1 << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); + MCHBAR32_OR(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); + MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); + MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index e6dfbc4548..f0232e069a 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -57,7 +57,7 @@ static const struct gt_powermeter snb_pm_gt1[] = { { 0xa240, 0x00000000 }, { 0xa244, 0x00000000 }, { 0xa248, 0x8000421e }, - { 0 } + { 0 }, }; static const struct gt_powermeter snb_pm_gt2[] = { @@ -80,7 +80,7 @@ static const struct gt_powermeter snb_pm_gt2[] = { { 0xa240, 0x00000000 }, { 0xa244, 0x00000000 }, { 0xa248, 0x8000421e }, - { 0 } + { 0 }, }; static const struct gt_powermeter ivb_pm_gt1[] = { @@ -136,7 +136,7 @@ static const struct gt_powermeter ivb_pm_gt1[] = { { 0xaa3c, 0x00001c00 }, { 0xaa54, 0x00000004 }, { 0xaa60, 0x00060000 }, - { 0 } + { 0 }, }; static const struct gt_powermeter ivb_pm_gt2_17w[] = { @@ -192,7 +192,7 @@ static const struct gt_powermeter ivb_pm_gt2_17w[] = { { 0xaa3c, 0x00003900 }, { 0xaa54, 0x00000008 }, { 0xaa60, 0x00110000 }, - { 0 } + { 0 }, }; static const struct gt_powermeter ivb_pm_gt2_35w[] = { @@ -248,12 +248,12 @@ static const struct gt_powermeter ivb_pm_gt2_35w[] = { { 0xaa3c, 0x00003900 }, { 0xaa54, 0x00000008 }, { 0xaa60, 0x00110000 }, - { 0 } + { 0 }, }; -/* some vga option roms are used for several chipsets but they only have one - * PCI ID in their header. If we encounter such an option rom, we need to do - * the mapping ourselves +/* + * Some VGA option roms are used for several chipsets but they only have one PCI ID in their + * header. If we encounter such an option rom, we need to do the mapping ourselves. */ u32 map_oprom_vendev(u32 vendev) @@ -262,17 +262,17 @@ u32 map_oprom_vendev(u32 vendev) switch (vendev) { case 0x80860102: /* SNB GT1 Desktop */ - case 0x8086010a: /* SNB GT1 Server */ + case 0x8086010a: /* SNB GT1 Server */ case 0x80860112: /* SNB GT2 Desktop */ - case 0x80860116: /* SNB GT2 Mobile */ + case 0x80860116: /* SNB GT2 Mobile */ case 0x80860122: /* SNB GT2 Desktop >=1.3GHz */ - case 0x80860126: /* SNB GT2 Mobile >=1.3GHz */ + case 0x80860126: /* SNB GT2 Mobile >=1.3GHz */ case 0x80860152: /* IVB GT1 Desktop */ - case 0x80860156: /* IVB GT1 Mobile */ + case 0x80860156: /* IVB GT1 Mobile */ case 0x80860162: /* IVB GT2 Desktop */ - case 0x80860166: /* IVB GT2 Mobile */ - case 0x8086016a: /* IVB GT2 Server */ - new_vendev = 0x80860106;/* SNB GT1 Mobile */ + case 0x80860166: /* IVB GT2 Mobile */ + case 0x8086016a: /* IVB GT2 Server */ + new_vendev = 0x80860106;/* SNB GT1 Mobile */ break; } @@ -385,18 +385,15 @@ static void gma_pm_init_pre_vbios(struct device *dev) if (tdp <= 17) { /* <=17W ULV */ - printk(BIOS_DEBUG, "IVB GT2 17W " - "Power Meter Weights\n"); + printk(BIOS_DEBUG, "IVB GT2 17W Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_17w); } else if ((tdp >= 25) && (tdp <= 35)) { /* 25W-35W */ - printk(BIOS_DEBUG, "IVB GT2 25W-35W " - "Power Meter Weights\n"); + printk(BIOS_DEBUG, "IVB GT2 25W-35W Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } else { /* All others */ - printk(BIOS_DEBUG, "IVB GT2 35W " - "Power Meter Weights\n"); + printk(BIOS_DEBUG, "IVB GT2 35W Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } } @@ -552,7 +549,7 @@ static void gma_pm_init_post_vbios(struct device *dev) /* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030); if (!reg32) { - reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; + reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; gtt_write(0xc4030, reg32); @@ -599,15 +596,15 @@ static void gma_enable_swsci(void) { u16 reg16; - /* clear DMISCI status */ + /* Clear DMISCI status */ reg16 = inw(DEFAULT_PMBASE + TCO1_STS); reg16 &= DMISCI_STS; outw(DEFAULT_PMBASE + TCO1_STS, reg16); - /* clear acpi tco status */ + /* Clear ACPI TCO status */ outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); - /* enable acpi tco scis */ + /* Enable ACPI TCO SCIs */ reg16 = inw(DEFAULT_PMBASE + GPE0_EN); reg16 |= TCOSCI_EN; outw(DEFAULT_PMBASE + GPE0_EN, reg16); @@ -654,10 +651,9 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) +const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { - struct device *dev = pcidev_on_root(0x2, 0); + struct device *dev = pcidev_on_root(2, 0); if (!dev) { return NULL; } @@ -675,10 +671,8 @@ static void gma_ssdt(struct device *device) drivers_intel_gma_displays_ssdt_generate(gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) +static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, + struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; global_nvs_t *gnvs; @@ -706,44 +700,46 @@ static const char *gma_acpi_name(const struct device *dev) return "GFX0"; } -/* called by pci set_vga_bridge function */ +/* Called by PCI set_vga_bridge function */ static void gma_func0_disable(struct device *dev) { u16 reg16; struct device *dev_host = pcidev_on_root(0, 0); reg16 = pci_read_config16(dev_host, GGC); - reg16 |= (1 << 1); /* disable VGA decode */ + reg16 |= (1 << 1); /* Disable VGA decode */ pci_write_config16(dev_host, GGC, reg16); dev->enabled = 0; } static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = gma_ssdt, - .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, - .disable = gma_func0_disable, - .ops_pci = &gma_pci_ops, - .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, + .init = gma_func0_init, + .scan_bus = NULL, + .enable = NULL, + .disable = gma_func0_disable, + .ops_pci = &gma_pci_ops, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; -static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, - 0x0116, 0x0122, 0x0126, 0x0156, - 0x0166, 0x0162, 0x016a, 0x0152, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x0102, 0x0106, 0x010a, 0x0112, + 0x0116, 0x0122, 0x0126, 0x0156, + 0x0166, 0x0162, 0x016a, 0x0152, + 0 +}; static const struct pci_driver gma __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 899edbb1aa..bf04deed5b 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -17,9 +17,10 @@ struct i915_gpu_controller_info; -int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 physbase, u16 pio, u8 *mmio, u32 lfb); -int i915lightup_ivy(const struct i915_gpu_controller_info *info, - u32 physbase, u16 pio, u8 *mmio, u32 lfb); +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, + u8 *mmio, u32 lfb); + +int i915lightup_ivy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, + u8 *mmio, u32 lfb); #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h new file mode 100644 index 0000000000..929392bcd6 --- /dev/null +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -0,0 +1,430 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ +#define __SANDYBRIDGE_MCHBAR_REGS_H__ + +/* + * ### IOSAV command queue notes ### + * + * Intel provides a command queue of depth four. + * Every command is configured by using multiple MCHBAR registers. + * On executing the command queue, you have to specify its depth (number of commands). + * + * The macros for these registers can take some integer parameters, within these bounds: + * channel: [0..1] + * index: [0..3] + * lane: [0..8] + * + * Note that these ranges are 'closed': both endpoints are included. + * + * + * + * ### Register description ### + * + * IOSAV_n_SP_CMD_ADDR_ch(channel, index) + * Sub-sequence command addresses. Controls the address, bank address and slotrank signals. + * + * Bitfields: + * [0..15] Row / Column Address. + * [16..18] The result of (10 + [16..18]) is the number of valid row bits. + * Note: Value 1 is not implemented. Not that it really matters, though. + * Value 7 is reserved, as the hardware does not support it. + * [20..22] Bank Address. + * [24..25] Rank select. Let's call it "ranksel", as it is mentioned later. + * + * IOSAV_n_ADDR_UPDATE_ch(channel, index) + * How the address shall be updated after executing the sub-sequence command. + * + * Bitfields: + * [0] Increment CAS/RAS by 1. + * [1] Increment CAS/RAS by 8. + * [2] Increment bank select by 1. + * [3..4] Increment rank select by 1, 2 or 3. + * [5..9] Known as "addr_wrap". Address bits will wrap around the [addr_wrap..0] range. + * [10..11] LFSR update: + * 00: Do not use the LFSR function. + * 01: Undefined, treat as Reserved. + * 10: Apply LFSR on the [addr_wrap..0] bit range. + * 11: Apply LFSR on the [addr_wrap..3] bit range. + * + * [12..15] Update rate. The number of command runs between address updates. For example: + * 0: Update every command run. + * 1: Update every second command run. That is, half of the command rate. + * N: Update after N command runs without updates. + * + * [16..17] LFSR behavior on the deselect cycles (when no sub-seq command is issued): + * 0: No change w.r.t. the last issued command. + * 1: LFSR XORs with address & command (excluding CS), but does not update. + * 2: LFSR XORs with address & command (excluding CS), and updates. + * + * IOSAV_n_SP_CMD_CTRL_ch(channel, index) + * Special command control register. Controls the DRAM command signals. + * + * Bitfields: + * [0] !RAS signal. + * [1] !CAS signal. + * [2] !WE signal. + * [4..7] CKE, per rank and channel. + * [8..11] ODT, per rank and channel. + * [12] Chip Select mode control. + * [13..16] Chip select, per rank and channel. It works as follows: + * + * entity CS_BLOCK is + * port ( + * MODE : in std_logic; -- Mode select at [12] + * RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value + * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [13..16] + * CS_Q : out std_logic_vector(0 to 3) -- CS signals + * ); + * end entity CS_BLOCK; + * + * architecture RTL of CS_BLOCK is + * begin + * if MODE = '1' then + * CS_Q <= not RANKSEL and CS_CTL; + * else + * CS_Q <= CS_CTL; + * end if; + * end architecture RTL; + * + * [17] Auto Precharge. Only valid when using 10 row bits! + * + * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) + * Sub-sequence parameters. Controls repetititons, delays and data orientation. + * + * Bitfields: + * [0..8] Number of repetitions of the sub-sequence command. + * [10..14] Gap, number of clock-cycles to wait before sending the next command. + * [16..24] Number of clock-cycles to idle between sub-sequence commands. + * [26..27] The direction of the data. + * 00: None, does not handle data + * 01: Read + * 10: Write + * 11: Read & Write + * + * IOSAV_n_ADDRESS_LFSR_ch(channel, index) + * 23-bit LFSR state register. It is written into the LFSR when the sub-sequence is loaded, + * and then read back from the LFSR when the sub-sequence is done. + * + * Bitfields: + * [0..22] LFSR state. + * + * IOSAV_SEQ_CTL_ch(channel) + * Control the sequence level in IOSAV: number of sub-sequences, iterations, maintenance... + * + * Bitfields: + * [0..7] Number of full sequence executions. When this field becomes non-zero, then the + * sequence starts running immediately. This value is decremented after completing + * a full sequence iteration. When it is zero, the sequence is done. No decrement + * is done if this field is set to 0xff. This is the "infinite repeat" mode, and + * it is manually aborted by clearing this field. + * + * [8..16] Number of wait cycles after each sequence iteration. This wait's purpose is to + * allow performing maintenance in infinite loops. When non-zero, RCOMP, refresh + * and ZQXS operations can take place. + * + * [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs. + * [18..19] Number of sub-sequences. The programmed value is the index of the last sub-seq. + * [20] If set, keep refresh disabled until the next sequence execution. + * DANGER: Refresh must be re-enabled within the (9 * tREFI) period! + * + * [22] If set, sequence execution will not prevent refresh. This cannot be set when + * bit [20] is also set, or was set on the previous sequence. This bit exists so + * that the sequence machine can be used as a timer without affecting the memory. + * + * [23] If set, a output pin is asserted on the first detected error. This output can + * be used as a trigger for an oscilloscope or a logic analyzer, which is handy. + * + * IOSAV_DATA_CTL_ch(channel) + * Data-related controls in IOSAV mode. + * + * Bitfields: + * [0..7] WDB (Write Data Buffer) pattern length: [0..7] = (length / 8) - 1; + * [8..15] WDB read pointer. Points at the data used for IOSAV write transactions. + * [16..23] Comparison pointer. Used to compare data from IOSAV read transactions. + * [24] If set, increment pointers only when micro-breakpoint is active. + * + * IOSAV_STATUS_ch(channel) + * State of the IOSAV sequence machine. Should be polled after sending an IOSAV sequence. + * + * Bitfields: + * [0] IDLE: IOSAV is sleeping. + * [1] BUSY: IOSAV is running a sequence. + * [2] DONE: IOSAV has completed a sequence. + * [3] ERROR: IOSAV detected an error and stopped on it, when using Stop-on-error. + * [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted. + * [5] RCOMP: RComp failure. Unused, consider Reserved. + * [6] Cleared with a new sequence, and set when done and refresh counter is drained. + * + */ + +/* Indexed register helper macros */ +#define Gz(r, z) ((r) + ((z) << 8)) +#define Ly(r, y) ((r) + ((y) << 2)) +#define Cx(r, x) ((r) + ((x) << 10)) +#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) +#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) + +/* Byte lane training register base addresses */ +#define LANEBASE_B0 0x0000 +#define LANEBASE_B1 0x0200 +#define LANEBASE_B2 0x0400 +#define LANEBASE_B3 0x0600 +#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ +#define LANEBASE_B4 0x1000 +#define LANEBASE_B5 0x1200 +#define LANEBASE_B6 0x1400 +#define LANEBASE_B7 0x1600 + +/* Byte lane register offsets */ +#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ +#define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ +#define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ +#define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ +#define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ + +/* Register definitions */ +#define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ +#define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ +#define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch) /* PI coding for DDR CLK pins */ +#define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch) /* Logic delay of 1 QCLK in CLK slice */ +#define GDDLLFUSE_ch(ch) Gz(0x0c20, ch) /* Used for fuse download to the DLLs */ +#define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch) /* Debug MUX control */ + +#define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch) /* Debug MUX control */ + +#define CRCOMPOFST1_ch(ch) Gz(0x1810, ch) /* DQ, CTL and CLK Offset values */ + +#define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch) /* Data training mode control */ +#define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch) /* Training results according to PI */ +#define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch) + +#define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch) /* Indicates which rank is populated */ +#define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch) /* COMP values register */ +#define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch) /* COMP values register */ +#define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch) /* Command and control PI coding */ + +#define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ +#define GDCRDATACOMP 0x340c /* COMP values register */ + +#define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ + +/* MC per-channel registers */ +#define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ +#define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ +#define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ +#define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ +#define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ +#define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ +#define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch) /* IO Latency Configuration */ +#define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch) /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LO_ch(ch) Cx(0x4038, ch) /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HI_ch(ch) Cx(0x403c, ch) /* Scrambling seed 2 high */ + +/* IOSAV Bytelane Bit-wise error */ +#define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y) + +/* IOSAV Bytelane Bit-wise compare mask */ +#define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y) + +/* + * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. + * Different counters for transactions that are issued on the ring agents (core or GT) and + * transactions issued in the SA. + */ +#define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch) +#define SC_PCIT_ch(ch) Cx(0x40ac, ch) /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch) /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch) /* ECC error injection count */ +#define ECC_DFT_ch(ch) Cx(0x40b8, ch) /* ECC DFT features (ECC4ANA, error inject) */ +#define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch) /* Extra WR delay to overcome WR-flyby issue */ + +#define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ + +/* IOSAV sub-sequence control registers */ +#define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ +#define IOSAV_n_ADDR_UPDATE_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ +#define IOSAV_n_SP_CMD_CTRL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ +#define IOSAV_n_SUBSEQ_CTRL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ +#define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ + +#define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch) /* Data control in IOSAV mode */ +#define IOSAV_STATUS_ch(ch) Cx(0x428c, ch) /* State of the IOSAV sequence machine */ +#define TC_ZQCAL_ch(ch) Cx(0x4290, ch) /* ZQCAL control register */ +#define TC_RFP_ch(ch) Cx(0x4294, ch) /* Refresh Parameters */ +#define TC_RFTP_ch(ch) Cx(0x4298, ch) /* Refresh Timing Parameters */ +#define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch) /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch) /* IOSAV mode control */ +#define TC_SRFTP_ch(ch) Cx(0x42a4, ch) /* Self-refresh timing parameters */ +#define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch) /* Data vector count of the first error */ +#define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch) /* IOSAV data check masking */ + +#define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y) /* Per-byte 16-bit error count */ +#define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch) /* Global 16-bit error count */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define IOSAV_BYTE_SERROR_ch(ch) Cx(0x4368, ch) /** Byte-Wise Sticky Error */ +#define IOSAV_BYTE_SERROR_C_ch(ch) Cx(0x436c, ch) /** Byte-Wise Sticky Error Clear */ + +#define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch) /* Thermal mode configuration */ +#define PM_CMD_PWR_ch(ch) Cx(0x4384, ch) /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch) /* Bandwidth throttling on overtemp */ +#define SC_WDBWM_ch(ch) Cx(0x438c, ch) /* Watermarks and starvation counter */ + +/* MC Channel Broadcast registers */ +#define TC_DBP 0x4c00 /* Timings: BIN */ +#define TC_RAP 0x4c04 /* Timings: Regular access */ +#define TC_RWP 0x4c08 /* Timings: Read / Write */ +#define TC_OTHP 0x4c0c /* Timings: Other parameters */ +#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ +#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ +#define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ +#define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LO 0x4c38 /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HI 0x4c3c /* Scrambling seed 2 high */ + +#define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ +#define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ + +/* + * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. + * Different counters for transactions that are issued on the ring agents (core or GT) and + * transactions issued in the SA. + */ +#define SC_PR_CNT_CONFIG 0x4ca8 +#define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ +#define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ +#define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ + +/** Opportunistic reads configuration during write-major-mode (WMM) */ +#define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ + +#define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ + +#define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */ +#define IOSAV_n_ADDR_UPDATE(n) Ly(0x4e10, n) /* Address update after command execution */ +#define IOSAV_n_SP_CMD_CTRL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */ +#define IOSAV_n_SUBSEQ_CTRL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */ +#define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */ + +#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ +#define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ +#define TC_ZQCAL 0x4e90 /* ZQCAL control register */ +#define TC_RFP 0x4e94 /* Refresh Parameters */ +#define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ +#define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ +#define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ + +/** + * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this + * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. + */ +#define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ + +#define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ +#define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ + +#define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ +#define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define IOSAV_BYTE_SERROR 0x4f68 /** Byte-Wise Sticky Error */ +#define IOSAV_BYTE_SERROR_C 0x4f6c /** Byte-Wise Sticky Error Clear */ + +#define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ +#define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ +#define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ + +/* No, there's no need to get mad about the Memory Address Decoder */ +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM(ch) Ly(0x5004, ch) /* Channel characteristics */ +#define MAD_DIMM_CH0 MAD_DIMM(0) /* Channel 0 is at 0x5004 */ +#define MAD_DIMM_CH1 MAD_DIMM(1) /* Channel 1 is at 0x5008 */ +#define MAD_DIMM_CH2 MAD_DIMM(2) /* Channel 2 is at 0x500c (unused on SNB) */ + +#define MAD_ZR 0x5014 /* Address Decode Zones */ +#define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ +#define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ + +#define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ + +#define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ +#define MRC_REVISION 0x5034 /* MRC Revision */ +#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ +#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ + +#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ + +#define GFXVTBAR 0x5400 /* Base address for IGD */ +#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ + +/* On Ivy Bridge, this is used to enable Power Aware Interrupt Routing */ +#define INTRDIRCTL 0x5418 /* Interrupt Redirection Control */ + +/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ +#define PAVP_MSG 0x5500 + +#define MEM_TRML_ESTIMATION_CONFIG 0x5880 +#define MEM_TRML_THRESHOLDS_CONFIG 0x5888 +#define MEM_TRML_INTERRUPT 0x58a8 + +/* Some power MSRs are also represented in MCHBAR */ +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 /* Turbo Power Limit 1 parameters */ +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 /* Turbo Power Limit 2 parameters */ + +#define SSKPD 0x5d10 /* 64-bit scratchpad register */ +#define SSKPD_HI 0x5d14 +#define BIOS_RESET_CPL 0x5da8 /* 8-bit */ + +/* PCODE will sample SAPM-related registers at the end of Phase 4. */ +#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ +#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ +#define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ +#define M_COMP 0x5f08 /* Memory COMP control */ +#define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ + +/* WARNING: Only applies to Sandy Bridge! */ +#define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ +#define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ + +/* Finalize registers. The names come from Haswell, as the finalize sequence is the same. */ +#define HDAUDRID 0x6008 +#define UMAGFXCTL 0x6020 +#define VDMBDFBARKVM 0x6030 +#define VDMBDFBARPAVP 0x6034 +#define VTDTRKLCK 0x63fc +#define REQLIM 0x6800 +#define DMIVCLIM 0x7000 +#define PEGCTL 0x7010 /* Bit 0 is PCIPWRGAT (clock gate all PEG controllers) */ +#define CRDTCTL3 0x740c /* Minimum completion credits for PCIe/DMI */ +#define CRDTCTL4 0x7410 /* Read Return Tracker credits */ +#define CRDTLCK 0x77fc + +#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 03e8db6cd7..60b6dcdf31 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -26,18 +26,17 @@ static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - uintptr_t tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB); - return tom; + return pci_read_config32(HOST_BRIDGE, TSEGMB); } void *cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return (void *)smm_region_start(); } static uintptr_t northbridge_get_tseg_base(void) { - return ALIGN_DOWN(smm_region_start(), 1*MiB); + return ALIGN_DOWN(smm_region_start(), 1 * MiB); } static size_t northbridge_get_tseg_size(void) @@ -48,24 +47,27 @@ static size_t northbridge_get_tseg_size(void) void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); - *size = northbridge_get_tseg_size(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - top_of_ram = (uintptr_t)cbmem_top(); - /* Cache 8MiB below the top of ram. On sandybridge systems the top of + /* + * Cache 8MiB below the top of ram. On sandybridge systems the top of * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later - * for ramstage before setting up the entire RAM as cacheable. */ - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + * for ramstage before setting up the entire RAM as cacheable. + */ + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); - /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems + /* + * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM - * handler as well as using the TSEG region for other purposes. */ - postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + * handler as well as using the TSEG region for other purposes. + */ + postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index eb102db933..23c1489acb 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -35,11 +35,9 @@ static uint64_t uma_memory_size = 0; int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( - pcidev_on_root(0, 0), - PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; + uint8_t stepping = cpuid_eax(1) & 0x0f; + uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); + bridge_revision_id = (bridge_id & 0xf0) | stepping; } return bridge_revision_id; } @@ -66,18 +64,19 @@ static int get_pcie_bar(u32 *base) pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + case 0: /* 256MB */ + *base = pciexbar_reg & (0xffffffffULL << 28); return 256; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + case 1: /* 128M */ + *base = pciexbar_reg & (0xffffffffULL << 27); return 128; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + case 2: /* 64M */ + *base = pciexbar_reg & (0xffffffffULL << 26); return 64; } @@ -88,15 +87,14 @@ static void add_fixed_resources(struct device *dev, int index) { mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); - mmio_resource(dev, index++, legacy_hole_base_k, - (0xc0000 >> 10) - legacy_hole_base_k); - reserved_ram_resource(dev, index++, 0xc0000 >> 10, - (0x100000 - 0xc0000) >> 10); + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); + + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); #if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { @@ -106,10 +104,10 @@ static void add_fixed_resources(struct device *dev, int index) } /* Reserve IOMMU BARs */ - const u32 capid0_a = pci_read_config32(dev, 0xe4); + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); if (!(capid0_a & (1 << 23))) { - mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4); - mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4); + mmio_resource(dev, index++, GFXVT_BASE >> 10, 4); + mmio_resource(dev, index++, VTVC0_BASE >> 10, 4); } } @@ -149,7 +147,7 @@ static void pci_domain_set_resources(struct device *dev) struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config32(mch, TOUUD+4); + touud = pci_read_config32(mch, TOUUD + 4); touud <<= 32; touud |= pci_read_config32(mch, TOUUD); @@ -157,17 +155,17 @@ static void pci_domain_set_resources(struct device *dev) tolud = pci_read_config32(mch, TOLUD); /* Top of Memory - does not account for any UMA */ - tom = pci_read_config32(mch, 0xa4); + tom = pci_read_config32(mch, TOM + 4); tom <<= 32; - tom |= pci_read_config32(mch, 0xa0); + tom |= pci_read_config32(mch, TOM); printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); - /* ME UMA needs excluding if total memory <4GB */ - me_base = pci_read_config32(mch, 0x74); + /* ME UMA needs excluding if total memory < 4GB */ + me_base = pci_read_config32(mch, MESEG_BASE + 4); me_base <<= 32; - me_base |= pci_read_config32(mch, 0x70); + me_base |= pci_read_config32(mch, MESEG_BASE); printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); @@ -206,30 +204,28 @@ static void pci_domain_set_resources(struct device *dev) } /* Calculate TSEG size from its base which must be below GTT */ - tseg_base = pci_read_config32(mch, 0xb8); + tseg_base = pci_read_config32(mch, TSEGMB); uma_size = (uma_memory_base - tseg_base) >> 10; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; uma_memory_size += uma_size * 1024ULL; - printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", - tseg_base, uma_size >> 10); + printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); /* Report the memory regions */ ram_resource(dev, 3, 0, legacy_hole_base_k); ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (tomk - (legacy_hole_base_k + legacy_hole_size_k))); + (tomk - (legacy_hole_base_k + legacy_hole_size_k))); /* - * If >= 4GB installed then memory from TOLUD to 4GB - * is remapped above TOM, TOUUD will account for both + * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. + * TOUUD will account for both memory chunks. */ touud >>= 10; /* Convert to KB */ if (touud > 4096 * 1024) { ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096); } add_fixed_resources(dev, 6); @@ -253,17 +249,18 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - */ +/* + * TODO We could determine how many PCIe busses we need in the bar. + * For now, that number is hardcoded to a max of 64. + */ static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_name = northbridge_acpi_name, + .acpi_name = northbridge_acpi_name, }; static void mc_read_resources(struct device *dev) @@ -291,7 +288,7 @@ static void northbridge_dmi_init(struct device *dev) /* Steps prior to DMI ASPM */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { reg32 = DMIBAR32(0x250); - reg32 &= ~((1 << 22)|(1 << 20)); + reg32 &= ~((1 << 22) | (1 << 20)); reg32 |= (1 << 21); DMIBAR32(0x250) = reg32; } @@ -304,6 +301,7 @@ static void northbridge_dmi_init(struct device *dev) reg32 = DMIBAR32(0x1f8); reg32 |= (1 << 16); DMIBAR32(0x1f8) = reg32; + } else if (bridge_silicon_revision() >= SNB_STEP_D1) { reg32 = DMIBAR32(0x1f8); reg32 &= ~(1 << 26); @@ -374,10 +372,15 @@ static void disable_peg(void) dev = pcidev_on_root(0, 0); pci_write_config32(dev, DEVEN, reg); + if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { - /* Set the PEG clock gating bit. - * Disables the IO clock on all PEG devices. */ - MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; + /* + * Set the PEG clock gating bit. Disables the IO clock on all PEG devices. + * + * FIXME: If not clock gating, this register still needs to be written to once, + * to lock it down. Also, never clock gate on Ivy Bridge stepping A0! + */ + MCHBAR32_OR(PEGCTL, 1); printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); } } @@ -394,10 +397,10 @@ static void northbridge_init(struct device *dev) if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { /* Enable Power Aware Interrupt Routing */ - u8 pair = MCHBAR8(PAIR_CTL); - pair &= ~0xf; /* Clear 3:0 */ - pair |= 0x4; /* Fixed Priority */ - MCHBAR8(PAIR_CTL) = pair; + u8 pair = MCHBAR8(INTRDIRCTL); + pair &= ~0x0f; /* Clear 3:0 */ + pair |= 0x04; /* Fixed Priority */ + MCHBAR8(INTRDIRCTL) = pair; /* 30h for IvyBridge */ bridge_type |= 0x30; @@ -407,9 +410,7 @@ static void northbridge_init(struct device *dev) } MCHBAR32(SAPMTIMERS) = bridge_type; - /* Turn off unused devices. Has to be done before - * setting BIOS_RESET_CPL. - */ + /* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */ disable_peg(); /* @@ -426,17 +427,17 @@ static void northbridge_init(struct device *dev) set_power_limits(28); /* - * CPUs with configurable TDP also need power limits set - * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. + * CPUs with configurable TDP also need power limits set in MCHBAR. + * Use the same values from MSR_PKG_POWER_LIMIT. */ if (cpu_config_tdp_levels()) { msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); - MCHBAR32(MC_TURBO_PL1) = msr.lo; - MCHBAR32(MC_TURBO_PL2) = msr.hi; + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = msr.lo; + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = msr.hi; } /* Set here before graphics PM init */ - MCHBAR32(MMIO_PAVP_CTL) = 0x00100001; + MCHBAR32(PAVP_MSG) = 0x00100001; } void northbridge_write_smram(u8 smram) @@ -445,16 +446,16 @@ void northbridge_write_smram(u8 smram) } static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .scan_bus = NULL, + .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, }; @@ -465,8 +466,8 @@ static const unsigned short pci_device_ids[] = { }; static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 258ade2de8..05f05ecc1d 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -54,9 +54,9 @@ static const char *pcie_acpi_name(const struct device *dev) if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && port->bus->secondary == 0 && (port->path.pci.devfn == PCI_DEVFN(1, 0) || - port->path.pci.devfn == PCI_DEVFN(1, 1) || - port->path.pci.devfn == PCI_DEVFN(1, 2) || - port->path.pci.devfn == PCI_DEVFN(6, 0))) + port->path.pci.devfn == PCI_DEVFN(1, 1) || + port->path.pci.devfn == PCI_DEVFN(1, 2) || + port->path.pci.devfn == PCI_DEVFN(6, 0))) return "DEV0"; return NULL; @@ -81,9 +81,11 @@ static struct device_operations device_ops = { #endif }; -static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d, - 0x0151, 0x0155, 0x0159, 0x015d, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x0101, 0x0105, 0x0109, 0x010d, + 0x0151, 0x0155, 0x0159, 0x015d, + 0, +}; static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 8e98becbe3..8114bcc153 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -33,10 +33,10 @@ #include typedef struct { - uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto - uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable - uint16_t preboot_support; // 0: No xHCI preOS driver, 1: xHCI preOS driver - uint16_t xhci_streams; // 0: Disable, 1: Enable + uint16_t mode; /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + uint16_t hs_port_switch_mask; /* 4 bit mask, 1: switchable, 0: not switchable */ + uint16_t preboot_support; /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + uint16_t xhci_streams; /* 0: Disable, 1: Enable */ } pch_usb3_controller_settings; typedef void (*tx_byte_func)(unsigned char byte); @@ -57,17 +57,19 @@ struct pei_data uint32_t pmbase; uint32_t gpiobase; uint32_t thermalbase; - uint32_t system_type; // 0 Mobile, 1 Desktop/Server + uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ uint32_t tseg_size; uint8_t spd_addresses[4]; uint8_t ts_addresses[4]; int boot_mode; int ec_present; int gbe_enable; - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ int dimm_channel0_disabled; int dimm_channel1_disabled; /* Seed values saved in CMOS */ @@ -90,46 +92,50 @@ struct pei_data * [1] = overcurrent pin * [2] = length * - * Ports 0-7 can be mapped to OC0-OC3 + * Ports 0-7 can be mapped to OC0-OC3 * Ports 8-13 can be mapped to OC4-OC7 * * Port Length * MOBILE: - * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) - * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * < 0x050 = Setting 1 (back panel, 1 to 5 in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5 to 14 in, highest tx amplitude) * DESKTOP: - * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) - * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) - * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) + * < 0x080 = Setting 1 (front/back panel, less than 8 in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8 to 13 in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13 to 15 in, highest tx amplitude) */ uint16_t usb_port_config[16][3]; /* See the usb3 struct above for details */ pch_usb3_controller_settings usb3; - /* SPD data array for onboard RAM. - * spd_data [1..3] are ignored, instead the "dimm_channel{0,1}_disabled" - * flag and the spd_addresses are used to determine which DIMMs should - * use the SPD from spd_data[0]. + /* + * SPD data array for onboard RAM. Note that spd_data [1..3] are ignored: instead, + * the "dimm_channel{0,1}_disabled" flag and the spd_addresses are used to determine + * which DIMMs should use the SPD from spd_data[0]. */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; int ddr3lv_support; - /* pcie_init needs to be set to 1 to have the system agent initialize - * PCIe. Note: This should only be required if your system has Gen3 devices - * and it will increase your boot time by at least 100ms. + /* + * pcie_init needs to be set to 1 to have the system agent initialize PCIe. + * Note: This should only be required if your system has Gen3 devices and + * it will increase your boot time by at least 100ms. */ int pcie_init; - /* N mode functionality. Leave this setting at 0. - * 0 Auto - * 1 1N - * 2 2N + /* + * N mode functionality. Leave this setting at 0. + * + * 0: Auto + * 1: 1N + * 2: 2N */ int nmode; - /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows - * for DIMM SPD data to specify whether double-rate is required for - * extended operating temperature range. - * 0 Enable double rate based upon temperature thresholds - * 1 Normal rate - * 2 Always enable double rate + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to + * specify whether double-rate is required for extended operating temperature range. + * + * 0: Enable double rate based upon temperature thresholds + * 1: Normal rate + * 2: Always enable double rate */ int ddr_refresh_rate_config; } __packed; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 60217b4070..ca78eb3a64 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -35,47 +35,48 @@ #define MRC_CACHE_VERSION 1 -/* FIXME: no ECC support. */ -/* FIXME: no support for 3-channel chipsets. */ +/* FIXME: no ECC support */ +/* FIXME: no support for 3-channel chipsets */ static const char *ecc_decoder[] = { "inactive", "active on IO", "disabled on IO", - "active" + "active", }; static void wait_txt_clear(void) { - struct cpuid_result cp; + struct cpuid_result cp = cpuid_ext(1, 0); - cp = cpuid_ext(0x1, 0x0); - /* Check if TXT is supported? */ - if (!(cp.ecx & 0x40)) + /* Check if TXT is supported */ + if (!(cp.ecx & (1 << 6))) return; - /* Some TXT public bit. */ + + /* Some TXT public bit */ if (!(read32((void *)0xfed30010) & 1)) return; - /* Wait for TXT clear. */ - while (!(read8((void *)0xfed40000) & (1 << 7))); + + /* Wait for TXT clear */ + while (!(read8((void *)0xfed40000) & (1 << 7))) + ; } -/* - * Disable a channel in ramctr_timing. - */ -static void disable_channel(ramctr_timing *ctrl, int channel) { +/* Disable a channel in ramctr_timing */ +static void disable_channel(ramctr_timing *ctrl, int channel) +{ ctrl->rankmap[channel] = 0; + memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); + ctrl->channel_size_mb[channel] = 0; - ctrl->cmd_stretch[channel] = 0; - ctrl->mad_dimm[channel] = 0; - memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); + ctrl->cmd_stretch[channel] = 0; + ctrl->mad_dimm[channel] = 0; + memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); } -/* - * Fill cbmem with information for SMBIOS type 17. - */ +/* Fill cbmem with information for SMBIOS type 17 */ static void fill_smbios17(ramctr_timing *ctrl) { int channel, slot; @@ -89,54 +90,50 @@ static void fill_smbios17(ramctr_timing *ctrl) } } -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ +#define ON_OFF(val) (((val) & 1) ? "on" : "off") + +/* Print the memory controller configuration as read from the memory controller registers. */ static void report_memory_config(void) { u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; - int i, refclk; + int i; addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 0) & 3, + (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, - ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); + printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 0) & 0xff) * 256, ((ch_conf >> 19) & 1) ? 16 : 8, ((ch_conf >> 17) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? "" : ", selected"); printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 8) & 0xff) * 256, ((ch_conf >> 20) & 1) ? 16 : 8, ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); } } +#undef ON_OFF -/* - * Return CRC16 match for all SPDs. - */ +/* Return CRC16 match for all SPDs */ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { int channel, slot, spd_slot; @@ -146,7 +143,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; match &= ctrl->spd_crc[channel][slot] == - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); } } return match; @@ -166,7 +163,7 @@ void read_spd(spd_raw_data * spd, u8 addr, bool id_only) static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { - int dimms = 0, dimms_on_channel; + int dimms = 0, ch_dimms; int channel, slot, spd_slot; dimm_info *dimm = &ctrl->info; @@ -178,53 +175,55 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; - dimms_on_channel = 0; - /* count dimms on channel */ + ch_dimms = 0; + /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; - printk(BIOS_DEBUG, - "SPD probe channel%d, slot%d\n", channel, slot); + printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) - dimms_on_channel++; + ch_dimms++; } for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; - printk(BIOS_DEBUG, - "SPD probe channel%d, slot%d\n", channel, slot); + printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); - /* search for XMP profile */ - spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], - spd[spd_slot], + /* Search for XMP profile */ + spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot], DDR3_XMP_PROFILE_1); if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { printram("No valid XMP profile found.\n"); spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); - } else if (dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) { - printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", - dimm->dimm[channel][slot].dimms_per_channel, - dimms_on_channel); + + } else if (ch_dimms > dimm->dimm[channel][slot].dimms_per_channel) { + printram( + "XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", + dimm->dimm[channel][slot].dimms_per_channel, ch_dimms); + if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) - printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n"); + printk(BIOS_WARNING, + "XMP maximum DIMMs will be ignored.\n"); else - spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); + spd_decode_ddr3(&dimm->dimm[channel][slot], + spd[spd_slot]); + } else if (dimm->dimm[channel][slot].voltage != 1500) { - /* TODO: support other DDR3 voltage than 1500mV */ + /* TODO: Support DDR3 voltages other than 1500mV */ printram("XMP profile's requested %u mV is unsupported.\n", dimm->dimm[channel][slot].voltage); spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } - /* fill in CRC16 for MRC cache */ + /* Fill in CRC16 for MRC cache */ ctrl->spd_crc[channel][slot] = - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { - // set dimm invalid - dimm->dimm[channel][slot].ranks = 0; + /* Mark DIMM as invalid */ + dimm->dimm[channel][slot].ranks = 0; dimm->dimm[channel][slot].size_mb = 0; continue; } @@ -232,30 +231,40 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) dram_print_spd_ddr3(&dimm->dimm[channel][slot]); dimms++; ctrl->rank_mirror[channel][slot * 2] = 0; - ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored; + ctrl->rank_mirror[channel][slot * 2 + 1] = + dimm->dimm[channel][slot].flags.pins_mirrored; + ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; - ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; - ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); - printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", - channel, ctrl->rankmap[channel]); + ctrl->extended_temperature_range &= + dimm->dimm[channel][slot].flags.ext_temp_refresh; + + ctrl->rankmap[channel] |= + ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); + + printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, + ctrl->rankmap[channel]); } - if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) - && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { + if ((ctrl->rankmap[channel] & 0x03) && (ctrl->rankmap[channel] & 0x0c) + && dimm->dimm[channel][0].reference_card <= 5 + && dimm->dimm[channel][1].reference_card <= 5) { + const int ref_card_offset_table[6][6] = { - { 0, 0, 0, 0, 2, 2, }, - { 0, 0, 0, 0, 2, 2, }, - { 0, 0, 0, 0, 2, 2, }, - { 0, 0, 0, 0, 1, 1, }, - { 2, 2, 2, 1, 0, 0, }, - { 2, 2, 2, 1, 0, 0, }, + { 0, 0, 0, 0, 2, 2 }, + { 0, 0, 0, 0, 2, 2 }, + { 0, 0, 0, 0, 2, 2 }, + { 0, 0, 0, 0, 1, 1 }, + { 2, 2, 2, 1, 0, 0 }, + { 2, 2, 2, 1, 0, 0 }, }; - ctrl->ref_card_offset[channel] = ref_card_offset_table[dimm->dimm[channel][0].reference_card] - [dimm->dimm[channel][1].reference_card]; - } else + ctrl->ref_card_offset[channel] = ref_card_offset_table + [dimm->dimm[channel][0].reference_card] + [dimm->dimm[channel][1].reference_card]; + } else { ctrl->ref_card_offset[channel] = 0; + } } if (!dimms) @@ -265,29 +274,24 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) static void save_timings(ramctr_timing *ctrl) { /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, - sizeof(*ctrl)); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size) +static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) { if (ctrl->sandybridge) - return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size); + return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size); else - return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size); + return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size); } static void init_dram_ddr3(int min_tck, int s3resume) { - int me_uma_size; - int cbmem_was_inited; + int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; - int fast_boot; spd_raw_data spds[4]; struct region_device rdev; ramctr_timing *ctrl_cached; - int err; u32 cpu; MCHBAR32(SAPMCTL) |= 1; @@ -298,17 +302,14 @@ static void init_dram_ddr3(int min_tck, int s3resume) printk(BIOS_DEBUG, "Starting native Platform init\n"); - u32 reg_5d10; - wait_txt_clear(); wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); - reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000 - if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ - && reg_5d10 && !s3resume) { - MCHBAR32(0x5d10) = 0; - /* Need reset. */ + const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000 + if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { + MCHBAR32(SSKPD) = 0; + /* Need reset */ system_reset(); } @@ -316,10 +317,9 @@ static void init_dram_ddr3(int min_tck, int s3resume) early_init_dmi(); early_thermal_init(); - /* try to find timings in MRC cache */ - int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, - MRC_CACHE_VERSION, &rdev); - if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { + /* Try to find timings in MRC cache */ + err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev); + if (err || (region_device_sz(&rdev) < sizeof(ctrl))) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ system_reset(); @@ -329,7 +329,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) ctrl_cached = rdev_mmap_full(&rdev); } - /* verify MRC cache for fast boot */ + /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { /* Load SPD unique information data. */ memset(spds, 0, sizeof(spds)); @@ -353,8 +353,8 @@ static void init_dram_ddr3(int min_tck, int s3resume) /* Failed S3 resume, reset to come up cleanly */ system_reset(); } - /* no need to erase bad mrc cache here, it gets overwritten on - * successful boot. */ + /* No need to erase bad MRC cache here, it gets overwritten on a + successful boot */ printk(BIOS_ERR, "Stored timings are invalid !\n"); fast_boot = 0; } @@ -377,7 +377,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) } if (err) { - /* fallback: disable failing channel */ + /* Fallback: disable failing channel */ printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); printram("Disable failing channel.\n"); @@ -392,7 +392,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); - /* disable failing channel */ + /* Disable failing channel */ disable_channel(&ctrl, GET_ERR_CHANNEL(err)); err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 1939c83095..6febfa3f61 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -29,4 +29,4 @@ void save_mrc_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); -#endif /* RAMINIT_H */ +#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3c3546a65e..2cb6a8337b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -26,163 +26,8 @@ #include "raminit_common.h" #include "sandybridge.h" -/* FIXME: no ECC support. */ -/* FIXME: no support for 3-channel chipsets. */ - -/* - * ### IOSAV command queue notes ### - * - * Intel provides a command queue of depth four. - * Every command is configured by using multiple MCHBAR registers. - * On executing the command queue, you have to specify its depth (number of commands). - * - * The macros for these registers can take some integer parameters, within these bounds: - * channel: [0..1] - * index: [0..3] - * lane: [0..8] - * - * Note that these ranges are 'closed': both endpoints are included. - * - * - * - * ### Register description ### - * - * IOSAV_n_SP_CMD_ADDR_ch(channel, index) - * Sub-sequence command addresses. Controls the address, bank address and slotrank signals. - * - * Bitfields: - * [0..15] Row / Column Address. - * [16..18] The result of (10 + [16..18]) is the number of valid row bits. - * Note: Value 1 is not implemented. Not that it really matters, though. - * Value 7 is reserved, as the hardware does not support it. - * [20..22] Bank Address. - * [24..25] Rank select. Let's call it "ranksel", as it is mentioned later. - * - * IOSAV_n_ADDR_UPD_ch(channel, index) - * How the address shall be updated after executing the sub-sequence command. - * - * Bitfields: - * [0] Increment CAS/RAS by 1. - * [1] Increment CAS/RAS by 8. - * [2] Increment bank select by 1. - * [3..4] Increment rank select by 1, 2 or 3. - * [5..9] Known as "addr_wrap". Address bits will wrap around the [addr_wrap..0] range. - * [10..11] LFSR update: - * 00: Do not use the LFSR function. - * 01: Undefined, treat as Reserved. - * 10: Apply LFSR on the [addr_wrap..0] bit range. - * 11: Apply LFSR on the [addr_wrap..3] bit range. - * - * [12..15] Update rate. The number of command runs between address updates. For example: - * 0: Update every command run. - * 1: Update every second command run. That is, half of the command rate. - * N: Update after N command runs without updates. - * - * [16..17] LFSR behavior on the deselect cycles (when no sub-seq command is issued): - * 0: No change w.r.t. the last issued command. - * 1: LFSR XORs with address & command (excluding CS), but does not update. - * 2: LFSR XORs with address & command (excluding CS), and updates. - * - * IOSAV_n_SP_CMD_CTL_ch(channel, index) - * Special command control register. Controls the DRAM command signals. - * - * Bitfields: - * [0] !RAS signal. - * [1] !CAS signal. - * [2] !WE signal. - * [4..7] CKE, per rank and channel. - * [8..11] ODT, per rank and channel. - * [12] Chip Select mode control. - * [13..16] Chip select, per rank and channel. It works as follows: - * - * entity CS_BLOCK is - * port ( - * MODE : in std_logic; -- Mode select at [12] - * RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value - * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [13..16] - * CS_Q : out std_logic_vector(0 to 3) -- CS signals - * ); - * end entity CS_BLOCK; - * - * architecture RTL of CS_BLOCK is - * begin - * if MODE = '1' then - * CS_Q <= not RANKSEL and CS_CTL; - * else - * CS_Q <= CS_CTL; - * end if; - * end architecture RTL; - * - * [17] Auto Precharge. Only valid when using 10 row bits! - * - * IOSAV_n_SUBSEQ_CTL_ch(channel, index) - * Sub-sequence parameters. Controls repetititons, delays and data orientation. - * - * Bitfields: - * [0..8] Number of repetitions of the sub-sequence command. - * [10..14] Gap, number of clock-cycles to wait before sending the next command. - * [16..24] Number of clock-cycles to idle between sub-sequence commands. - * [26..27] The direction of the data. - * 00: None, does not handle data - * 01: Read - * 10: Write - * 11: Read & Write - * - * IOSAV_n_ADDRESS_LFSR_ch(channel, index) - * 23-bit LFSR state register. It is written into the LFSR when the sub-sequence is loaded, - * and then read back from the LFSR when the sub-sequence is done. - * - * Bitfields: - * [0..22] LFSR state. - * - * IOSAV_SEQ_CTL_ch(channel) - * Control the sequence level in IOSAV: number of sub-sequences, iterations, maintenance... - * - * Bitfields: - * [0..7] Number of full sequence executions. When this field becomes non-zero, then the - * sequence starts running immediately. This value is decremented after completing - * a full sequence iteration. When it is zero, the sequence is done. No decrement - * is done if this field is set to 0xff. This is the "infinite repeat" mode, and - * it is manually aborted by clearing this field. - * - * [8..16] Number of wait cycles after each sequence iteration. This wait's purpose is to - * allow performing maintenance in infinite loops. When non-zero, RCOMP, refresh - * and ZQXS operations can take place. - * - * [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs. - * [18..19] Number of sub-sequences. The programmed value is the index of the last sub-seq. - * [20] If set, keep refresh disabled until the next sequence execution. - * DANGER: Refresh must be re-enabled within the (9 * tREFI) period! - * - * [22] If set, sequence execution will not prevent refresh. This cannot be set when - * bit [20] is also set, or was set on the previous sequence. This bit exists so - * that the sequence machine can be used as a timer without affecting the memory. - * - * [23] If set, a output pin is asserted on the first detected error. This output can - * be used as a trigger for an oscilloscope or a logic analyzer, which is handy. - * - * IOSAV_DATA_CTL_ch(channel) - * Data-related controls in IOSAV mode. - * - * Bitfields: - * [0..7] WDB (Write Data Buffer) pattern length: [0..7] = (length / 8) - 1; - * [8..15] WDB read pointer. Points at the data used for IOSAV write transactions. - * [16..23] Comparison pointer. Used to compare data from IOSAV read transactions. - * [24] If set, increment pointers only when micro-breakpoint is active. - * - * IOSAV_STATUS_ch(channel) - * State of the IOSAV sequence machine. Should be polled after sending an IOSAV sequence. - * - * Bitfields: - * [0] IDLE: IOSAV is sleeping. - * [1] BUSY: IOSAV is running a sequence. - * [2] DONE: IOSAV has completed a sequence. - * [3] ERROR: IOSAV detected an error and stopped on it, when using Stop-on-error. - * [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted. - * [5] RCOMP: RComp failure. Unused, consider Reserved. - * [6] Cleared with a new sequence, and set when done and refresh counter is drained. - * - */ +/* FIXME: no ECC support */ +/* FIXME: no support for 3-channel chipsets */ /* length: [1..4] */ #define IOSAV_RUN_ONCE(length) ((((length) - 1) << 18) | 1) @@ -192,10 +37,11 @@ static void sfence(void) asm volatile ("sfence"); } -static void toggle_io_reset(void) { - /* toggle IO reset bit */ +/* Toggle IO reset bit */ +static void toggle_io_reset(void) +{ u32 r32 = MCHBAR32(MC_INIT_STATE_G); - MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; + MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; udelay(1); MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; udelay(1); @@ -210,43 +56,49 @@ static u32 get_XOVER_CMD(u8 rankmap) { u32 reg; - // enable xover cmd + /* Enable xover cmd */ reg = 0x4000; - // enable xover ctl - if (rankmap & 0x3) - reg |= 0x20000; + /* Enable xover ctl */ + if (rankmap & 0x03) + reg |= (1 << 17); - if (rankmap & 0xc) - reg |= 0x4000000; + if (rankmap & 0x0c) + reg |= (1 << 26); return reg; } -/* CAS write latency. To be programmed in MR2. - * See DDR3 SPEC for MR2 documentation. */ +/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ u8 get_CWL(u32 tCK) { - /* Get CWL based on tCK using the following rule: */ + /* Get CWL based on tCK using the following rule */ switch (tCK) { case TCK_1333MHZ: return 12; + case TCK_1200MHZ: case TCK_1100MHZ: return 11; + case TCK_1066MHZ: case TCK_1000MHZ: return 10; + case TCK_933MHZ: case TCK_900MHZ: return 9; + case TCK_800MHZ: case TCK_700MHZ: return 8; + case TCK_666MHZ: return 7; + case TCK_533MHZ: return 6; + default: return 5; } @@ -260,22 +112,25 @@ void dram_find_common_params(ramctr_timing *ctrl) ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; valid_dimms = 0; + FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { + const dimm_attr *dimm = &dimms->dimm[channel][slot]; if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) continue; + valid_dimms++; /* Find all possible CAS combinations */ ctrl->cas_supported &= dimm->cas_supported; /* Find the smallest common latencies supported by all DIMMs */ - ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); - ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); - ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); + ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); + ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); + ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); - ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); + ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); @@ -286,8 +141,8 @@ void dram_find_common_params(ramctr_timing *ctrl) } if (!ctrl->cas_supported) - die("Unsupported DIMM combination. " - "DIMMS do not support common CAS latency"); + die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); + if (!valid_dimms) die("No valid DIMMs found"); } @@ -298,12 +153,12 @@ void dram_xover(ramctr_timing *ctrl) int channel; FOR_ALL_CHANNELS { - // enable xover clk + /* Enable xover clk */ reg = get_XOVER_CLK(ctrl->rankmap[channel]); printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; - // enable xover ctl & xover cmd + /* Enable xover ctl & xover cmd */ reg = get_XOVER_CMD(ctrl->rankmap[channel]); printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; @@ -315,22 +170,21 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) u32 addr, cpu, stretch; stretch = ctrl->ref_card_offset[channel]; - /* ODT stretch: Delay ODT signal by stretch value. - * Useful for multi DIMM setups on the same channel. */ + /* + * ODT stretch: + * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. + */ cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; + addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, - (stretch << 12) | (stretch << 10)); - printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, - MCHBAR32(addr)); + MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { - // OTHP addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, - (stretch << 16) | (stretch << 18)); + MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -341,38 +195,39 @@ void dram_timing_regs(ramctr_timing *ctrl) int channel; FOR_ALL_CHANNELS { - // DBP + /* BIN parameters */ reg = 0; - reg |= ctrl->tRCD; - reg |= (ctrl->tRP << 4); - reg |= (ctrl->CAS << 8); - reg |= (ctrl->CWL << 12); + reg |= (ctrl->tRCD << 0); + reg |= (ctrl->tRP << 4); + reg |= (ctrl->CAS << 8); + reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); MCHBAR32(TC_DBP_ch(channel)) = reg; - // RAP + /* Regular access parameters */ reg = 0; - reg |= ctrl->tRRD; - reg |= (ctrl->tRTP << 4); - reg |= (ctrl->tCKE << 8); + reg |= (ctrl->tRRD << 0); + reg |= (ctrl->tRTP << 4); + reg |= (ctrl->tCKE << 8); reg |= (ctrl->tWTR << 12); reg |= (ctrl->tFAW << 16); - reg |= (ctrl->tWR << 24); + reg |= (ctrl->tWR << 24); reg |= (3 << 30); printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); MCHBAR32(TC_RAP_ch(channel)) = reg; - // OTHP + /* Other parameters */ addr = TC_OTHP_ch(channel); reg = 0; - reg |= ctrl->tXPDLL; - reg |= (ctrl->tXP << 5); + reg |= (ctrl->tXPDLL << 0); + reg |= (ctrl->tXP << 5); reg |= (ctrl->tAONPD << 8); reg |= 0xa0000; printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; + /* FIXME: This register might as well not exist */ MCHBAR32(0x4014 + channel * 0x400) = 0; MCHBAR32_OR(addr, 0x00020000); @@ -380,33 +235,31 @@ void dram_timing_regs(ramctr_timing *ctrl) dram_odt_stretch(ctrl, channel); /* - * TC-Refresh timing parameters - * The tREFIx9 field should be programmed to minimum of - * 8.9*tREFI (to allow for possible delays from ZQ or - * isoc) and tRASmax (70us) divided by 1024. + * TC-Refresh timing parameters: + * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow + * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. */ val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); - reg = ((ctrl->tREFI & 0xffff) << 0) | - ((ctrl->tRFC & 0x1ff) << 16) | - (((val32 / 1024) & 0x7f) << 25); + reg = ((ctrl->tREFI & 0xffff) << 0) | + ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); + printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg; MCHBAR32_OR(TC_RFP_ch(channel), 0xff); - // SRFTP + /* Self-refresh timing parameters */ reg = 0; val32 = tDLLK; - reg = (reg & ~0xfff) | val32; + reg = (reg & ~0x00000fff) | (val32 << 0); val32 = ctrl->tXSOffset; - reg = (reg & ~0xf000) | (val32 << 12); + reg = (reg & ~0x0000f000) | (val32 << 12); val32 = tDLLK - ctrl->tXSOffset; - reg = (reg & ~0x3ff0000) | (val32 << 16); + reg = (reg & ~0x03ff0000) | (val32 << 16); val32 = ctrl->tMOD - 8; - reg = (reg & ~0xf0000000) | (val32 << 28); - printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), - reg); + reg = (reg & ~0xf0000000) | (val32 << 28); + printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); MCHBAR32(TC_SRFTP_ch(channel)) = reg; } } @@ -420,34 +273,32 @@ void dram_dimm_mapping(ramctr_timing *ctrl) dimm_attr *dimmA, *dimmB; u32 reg = 0; - if (info->dimm[channel][0].size_mb >= - info->dimm[channel][1].size_mb) { + if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { dimmA = &info->dimm[channel][0]; dimmB = &info->dimm[channel][1]; - reg |= 0 << 16; + reg |= (0 << 16); } else { dimmA = &info->dimm[channel][1]; dimmB = &info->dimm[channel][0]; - reg |= 1 << 16; + reg |= (1 << 16); } if (dimmA && (dimmA->ranks > 0)) { - reg |= dimmA->size_mb / 256; - reg |= (dimmA->ranks - 1) << 17; + reg |= (dimmA->size_mb / 256) << 0; + reg |= (dimmA->ranks - 1) << 17; reg |= (dimmA->width / 8 - 1) << 19; } if (dimmB && (dimmB->ranks > 0)) { - reg |= (dimmB->size_mb / 256) << 8; - reg |= (dimmB->ranks - 1) << 18; + reg |= (dimmB->size_mb / 256) << 8; + reg |= (dimmB->ranks - 1) << 18; reg |= (dimmB->width / 8 - 1) << 20; } - reg |= 1 << 21; /* rank interleave */ - reg |= 1 << 22; /* enhanced interleave */ + reg |= 1 << 21; /* Rank interleave */ + reg |= 1 << 22; /* Enhanced interleave */ - if ((dimmA && (dimmA->ranks > 0)) - || (dimmB && (dimmB->ranks > 0))) { + if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { ctrl->mad_dimm[channel] = reg; } else { ctrl->mad_dimm[channel] = 0; @@ -459,7 +310,7 @@ void dram_dimm_set_mapping(ramctr_timing *ctrl) { int channel; FOR_ALL_CHANNELS { - MCHBAR32(MAD_DIMM_CH0 + channel * 4) = ctrl->mad_dimm[channel]; + MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel]; } } @@ -469,6 +320,7 @@ void dram_zones(ramctr_timing *ctrl, int training) u8 val; reg = 0; val = 0; + if (training) { ch0size = ctrl->channel_size_mb[0] ? 256 : 0; ch1size = ctrl->channel_size_mb[1] ? 256 : 0; @@ -481,14 +333,15 @@ void dram_zones(ramctr_timing *ctrl, int training) reg = MCHBAR32(MAD_ZR); val = ch1size / 256; reg = (reg & ~0xff000000) | val << 24; - reg = (reg & ~0xff0000) | (2 * val) << 16; + reg = (reg & ~0x00ff0000) | (2 * val) << 16; MCHBAR32(MAD_ZR) = reg; MCHBAR32(MAD_CHNL) = 0x24; + } else { reg = MCHBAR32(MAD_ZR); val = ch0size / 256; reg = (reg & ~0xff000000) | val << 24; - reg = (reg & ~0xff0000) | (2 * val) << 16; + reg = (reg & ~0x00ff0000) | (2 * val) << 16; MCHBAR32(MAD_ZR) = reg; MCHBAR32(MAD_CHNL) = 0x21; } @@ -509,13 +362,14 @@ unsigned int get_mem_min_tck(void) /* If this is zero, it just means devicetree.cb didn't set it */ if (!cfg || cfg->max_mem_clock_mhz == 0) { + if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) return TCK_1333MHZ; rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { - /* read Capabilities A Register DMFC bits */ + /* Read Capabilities A Register DMFC bits */ reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); reg32 &= 0x7; @@ -523,12 +377,12 @@ unsigned int get_mem_min_tck(void) case 7: return TCK_533MHZ; case 6: return TCK_666MHZ; case 5: return TCK_800MHZ; - /* reserved: */ + /* Reserved */ default: break; } } else { - /* read Capabilities B Register DMFC bits */ + /* Read Capabilities B Register DMFC bits */ reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); reg32 = (reg32 >> 4) & 0x7; @@ -540,7 +394,7 @@ unsigned int get_mem_min_tck(void) case 3: return TCK_1066MHZ; case 2: return TCK_1200MHZ; case 1: return TCK_1333MHZ; - /* reserved: */ + /* Reserved */ default: break; } @@ -582,11 +436,9 @@ static unsigned int get_mmio_size(void) void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { - u32 reg, val, reclaim; - u32 tom, gfxstolen, gttsize; - size_t tsegsize, mmiosize, toludbase, touudbase, gfxstolenbase, gttbase, - tsegbase, mestolenbase; - size_t tsegbasedelta, remapbase, remaplimit; + u32 reg, val, reclaim, tom, gfxstolen, gttsize; + size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; + size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; uint16_t ggc; mmiosize = get_mmio_size(); @@ -594,10 +446,10 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) ggc = pci_read_config16(HOST_BRIDGE, GGC); if (!(ggc & 2)) { gfxstolen = ((ggc >> 3) & 0x1f) * 32; - gttsize = ((ggc >> 8) & 0x3); + gttsize = ((ggc >> 8) & 0x3); } else { gfxstolen = 0; - gttsize = 0; + gttsize = 0; } tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; @@ -606,14 +458,14 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) mestolenbase = tom - me_uma_size; - toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, - tom - me_uma_size); + toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); + gfxstolenbase = toludbase - gfxstolen; gttbase = gfxstolenbase - gttsize; tsegbase = gttbase - tsegsize; - // Round tsegbase down to nearest address aligned to tsegsize + /* Round tsegbase down to nearest address aligned to tsegsize */ tsegbasedelta = tsegbase & (tsegsize - 1); tsegbase &= ~(tsegsize - 1); @@ -621,24 +473,23 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) gfxstolenbase -= tsegbasedelta; toludbase -= tsegbasedelta; - // Test if it is possible to reclaim a hole in the RAM addressing + /* Test if it is possible to reclaim a hole in the RAM addressing */ if (tom - me_uma_size > toludbase) { - // Reclaim is possible - reclaim = 1; - remapbase = MAX(4096, tom - me_uma_size); - remaplimit = - remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; - touudbase = remaplimit + 1; + /* Reclaim is possible */ + reclaim = 1; + remapbase = MAX(4096, tom - me_uma_size); + remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; + touudbase = remaplimit + 1; } else { // Reclaim not possible - reclaim = 0; + reclaim = 0; touudbase = tom - me_uma_size; } - // Update memory map in pci-e configuration space + /* Update memory map in PCIe configuration space */ printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); - // TOM (top of memory) + /* TOM (top of memory) */ reg = pci_read_config32(HOST_BRIDGE, TOM); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); @@ -651,21 +502,21 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); pci_write_config32(HOST_BRIDGE, TOM + 4, reg); - // TOLUD (top of low used dram) + /* TOLUD (Top Of Low Usable DRAM) */ reg = pci_read_config32(HOST_BRIDGE, TOLUD); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); pci_write_config32(HOST_BRIDGE, TOLUD, reg); - // TOUUD LSB (top of upper usable dram) + /* TOUUD LSB (Top Of Upper Usable DRAM) */ reg = pci_read_config32(HOST_BRIDGE, TOUUD); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); pci_write_config32(HOST_BRIDGE, TOUUD, reg); - // TOUUD MSB + /* TOUUD MSB */ reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); @@ -673,29 +524,29 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); if (reclaim) { - // REMAP BASE - pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); + /* REMAP BASE */ + pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); - // REMAP LIMIT - pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); + /* REMAP LIMIT */ + pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); } - // TSEG + /* TSEG */ reg = pci_read_config32(HOST_BRIDGE, TSEGMB); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); pci_write_config32(HOST_BRIDGE, TSEGMB, reg); - // GFX stolen memory + /* GFX stolen memory */ reg = pci_read_config32(HOST_BRIDGE, BDSM); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); pci_write_config32(HOST_BRIDGE, BDSM, reg); - // GTT stolen memory + /* GTT stolen memory */ reg = pci_read_config32(HOST_BRIDGE, BGSM); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); @@ -709,7 +560,7 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); - // ME base + /* ME base */ reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); @@ -722,12 +573,12 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); - // ME mask + /* ME mask */ reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - reg = reg | ME_STLEN_EN; // set ME memory enable - reg = reg | MELCK; // set lockbit on ME mem + reg = reg | ME_STLEN_EN; /* Set ME memory enable */ + reg = reg | MELCK; /* Set lock bit on ME mem */ printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); } @@ -745,21 +596,25 @@ static void write_reset(ramctr_timing *ctrl) { int channel, slotrank; - /* choose a populated channel. */ + /* Choose a populated channel */ channel = (ctrl->rankmap[0]) ? 0 : 1; wait_for_iosav(channel); - /* choose a populated rank. */ + /* Choose a populated rank */ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x80c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x80c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; - // execute command queue - why is bit 22 set here?! + /* + * Execute command queue - why is bit 22 set here?! + * + * This is actually using the IOSAV state machine as a timer, so refresh is allowed. + */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = (1 << 22) | IOSAV_RUN_ONCE(1); wait_for_iosav(channel); @@ -770,101 +625,99 @@ void dram_jedecreset(ramctr_timing *ctrl) u32 reg; int channel; - while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; do { reg = MCHBAR32(IOSAV_STATUS_ch(0)); } while ((reg & 0x14) == 0); - // Set state of memory controller + /* Set state of memory controller */ reg = 0x112; MCHBAR32(MC_INIT_STATE_G) = reg; MCHBAR32(MC_INIT_STATE) = 0; - reg |= 2; //ddr reset + reg |= 2; /* DDR reset */ MCHBAR32(MC_INIT_STATE_G) = reg; - // Assert dimm reset signal - MCHBAR32_AND(MC_INIT_STATE_G, ~0x2); + /* Assert DIMM reset signal */ + MCHBAR32_AND(MC_INIT_STATE_G, ~2); - // Wait 200us + /* Wait 200us */ udelay(200); - // Deassert dimm reset signal + /* Deassert DIMM reset signal */ MCHBAR32_OR(MC_INIT_STATE_G, 2); - // Wait 500us + /* Wait 500us */ udelay(500); - // Enable DCLK + /* Enable DCLK */ MCHBAR32_OR(MC_INIT_STATE_G, 4); - // XXX Wait 20ns + /* XXX Wait 20ns */ udelay(1); FOR_ALL_CHANNELS { - // Set valid rank CKE + /* Set valid rank CKE */ reg = ctrl->rankmap[channel]; MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; - // Wait 10ns for ranks to settle - //udelay(0.01); + /* Wait 10ns for ranks to settle */ + // udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; - // Write reset using a NOP + /* Write reset using a NOP */ write_reset(ctrl); } } static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) { - /* Get ODT based on rankmap: */ - int dimms_per_ch = (ctrl->rankmap[channel] & 1) - + ((ctrl->rankmap[channel] >> 2) & 1); + /* Get ODT based on rankmap */ + int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); if (dimms_per_ch == 1) { - return (const odtmap){60, 60}; + return (const odtmap){60, 60}; } else { return (const odtmap){120, 30}; } } -static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, - int reg, u32 val) +static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) { wait_for_iosav(channel); if (ctrl->rank_mirror[channel][slotrank]) { /* DDR3 Rank1 Address mirror - * swap the following pins: - * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ + swap the following pins: + A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ reg = ((reg >> 1) & 1) | ((reg << 1) & 2); - val = (val & ~0x1f8) | ((val >> 1) & 0xa8) - | ((val & 0xa8) << 1); + val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); } /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); } @@ -877,7 +730,7 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) /* DLL Reset - self clearing - set after CLK frequency has been changed */ mr0reg = 0x100; - // Convert CAS to MCH register friendly + /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { mch_cas = (u16) ((ctrl->CAS - 4) << 1); } else { @@ -885,15 +738,15 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) mch_cas = ((mch_cas << 1) | 0x1); } - // Convert tWR to MCH register friendly + /* Convert tWR to MCH register friendly */ mch_wr = mch_wr_t[ctrl->tWR - 5]; - mr0reg = (mr0reg & ~0x4) | ((mch_cas & 0x1) << 2); - mr0reg = (mr0reg & ~0x70) | ((mch_cas & 0xe) << 3); - mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9); + mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); + mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); + mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); - // Precharge PD - Fast (desktop) 0x1 or slow (mobile) 0x0 - mostly power-saving feature - mr0reg = (mr0reg & ~0x1000) | (!is_mobile << 12); + /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ + mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); return mr0reg; } @@ -923,7 +776,7 @@ static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) u32 mr1reg; odt = get_ODT(ctrl, rank, channel); - mr1reg = 0x2; + mr1reg = 2; mr1reg |= encode_odt(odt.rttnom); @@ -952,7 +805,7 @@ static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; mr2reg = 0; - mr2reg = (mr2reg & ~0x7) | pasr; + mr2reg = (mr2reg & ~0x07) | pasr; mr2reg = (mr2reg & ~0x38) | (cwl << 3); mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); mr2reg = (mr2reg & ~0x80) | (srt << 7); @@ -973,42 +826,41 @@ void dram_mrscommands(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { FOR_ALL_POPULATED_RANKS { - // MR2 + /* MR2 */ dram_mr2(ctrl, slotrank, channel); - // MR3 + /* MR3 */ dram_mr3(ctrl, slotrank, channel); - // MR1 + /* MR1 */ dram_mr1(ctrl, slotrank, channel); - // MR0 + /* MR0 */ dram_mr0(ctrl, slotrank, channel); } } /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL(0)) = 0x7; - MCHBAR32(IOSAV_n_SUBSEQ_CTL(0)) = 0xf1001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL(0)) = 0x7; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL(0)) = 0xf1001; MCHBAR32(IOSAV_n_SP_CMD_ADDR(0)) = 0x60002; - MCHBAR32(IOSAV_n_ADDR_UPD(0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE(0)) = 0; /* DRAM command ZQCL */ - MCHBAR32(IOSAV_n_SP_CMD_CTL(1)) = 0x1f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL(1)) = 0x1901001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL(1)) = 0x1f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL(1)) = 0x1901001; MCHBAR32(IOSAV_n_SP_CMD_ADDR(1)) = 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD(1)) = 0x288; + MCHBAR32(IOSAV_n_ADDR_UPDATE(1)) = 0x288; - // execute command queue on all channels? Why isn't bit 0 set here? - MCHBAR32(IOSAV_SEQ_CTL) = 0x40004; + /* Execute command queue on all channels. Do it four times. */ + MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4; - // Drain FOR_ALL_CHANNELS { - // Wait for ref drained + /* Wait for ref drained */ wait_for_iosav(channel); } - // Refresh enable + /* Refresh enable */ MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { @@ -1018,20 +870,19 @@ void dram_mrscommands(ramctr_timing *ctrl) slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - // Drain + /* Drain */ wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x659001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); - // Drain + /* Drain */ wait_for_iosav(channel); } } @@ -1063,42 +914,41 @@ void program_timings(ramctr_timing *ctrl, int channel) break; case 1: pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 0].pi_coding + - full_shift; + ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; break; case 2: pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 1].pi_coding + - full_shift; + ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; break; case 3: pi_coding_ctrl[slot] = (ctrl->timings[channel][2 * slot].pi_coding + - ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + - full_shift; + ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; break; } - /* enable CMD XOVER */ + /* Enable CMD XOVER */ reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); - reg32 |= ((pi_coding_ctrl[0] & 0x3f) << 6) | ((pi_coding_ctrl[0] & 0x40) << 9); + reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; + reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; - /* enable CLK XOVER */ + /* Enable CLK XOVER */ reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); reg_logic_delay = 0; FOR_ALL_POPULATED_RANKS { - int shift = - ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; int offset_pi_code; if (shift < 0) shift = 0; + offset_pi_code = ctrl->pi_code_offset + shift; - /* set CLK phase shift */ + + /* Set CLK phase shift */ reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; } @@ -1112,11 +962,10 @@ void program_timings(ramctr_timing *ctrl, int channel) reg_roundtrip_latency = 0; FOR_ALL_POPULATED_RANKS { - int post_timA_min_high = 7, post_timA_max_high = 0; - int pre_timA_min_high = 7, pre_timA_max_high = 0; + int post_timA_min_high = 7, pre_timA_min_high = 7; + int post_timA_max_high = 0, pre_timA_max_high = 0; int shift_402x = 0; - int shift = - ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; if (shift < 0) shift = 0; @@ -1139,6 +988,7 @@ void program_timings(ramctr_timing *ctrl, int channel) if (pre_timA_max_high - pre_timA_min_high < post_timA_max_high - post_timA_min_high) shift_402x = +1; + else if (pre_timA_max_high - pre_timA_min_high > post_timA_max_high - post_timA_min_high) shift_402x = -1; @@ -1146,6 +996,7 @@ void program_timings(ramctr_timing *ctrl, int channel) reg_io_latency |= (ctrl->timings[channel][slotrank].io_latency + shift_402x - post_timA_min_high) << (4 * slotrank); + reg_roundtrip_latency |= (ctrl->timings[channel][slotrank].roundtrip_latency + shift_402x) << (8 * slotrank); @@ -1187,45 +1038,45 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command MRS - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4040c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4040c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS - * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); + write MR3 MPR disable */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); } -static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, - int lane) +static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; - return ((MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> - (timA % 32)) & 1); + + return (MCHBAR32(lane_base[lane] + + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; } struct run { @@ -1253,24 +1104,23 @@ static struct run get_longest_zero_run(int *seq, int sz) } if (bl == 0) { ret.middle = sz / 2; - ret.start = 0; - ret.end = sz; + ret.start = 0; + ret.end = sz; ret.length = sz; - ret.all = 1; + ret.all = 1; return ret; } - ret.start = bs % sz; - ret.end = (bs + bl - 1) % sz; + ret.start = bs % sz; + ret.end = (bs + bl - 1) % sz; ret.middle = (bs + (bl - 1) / 2) % sz; ret.length = bl; - ret.all = 0; + ret.all = 0; return ret; } -static void discover_timA_coarse(ramctr_timing *ctrl, int channel, - int slotrank, int *upperA) +static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA; int statistics[NUM_LANES][128]; @@ -1285,8 +1135,7 @@ static void discover_timA_coarse(ramctr_timing *ctrl, int channel, test_timA(ctrl, channel, slotrank); FOR_ALL_LANES { - statistics[lane][timA] = - !does_lane_work(ctrl, channel, slotrank, lane); + statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); } } FOR_ALL_LANES { @@ -1295,13 +1144,13 @@ static void discover_timA_coarse(ramctr_timing *ctrl, int channel, upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; + printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } } -static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, - int *upperA) +static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA_delta; int statistics[NUM_LANES][51]; @@ -1310,16 +1159,18 @@ static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, memset(statistics, 0, sizeof(statistics)); for (timA_delta = -25; timA_delta <= 25; timA_delta++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. - timA = upperA[lane] + timA_delta + 0x40; + + FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].timA + = upperA[lane] + timA_delta + 0x40; + } program_timings(ctrl, channel); for (i = 0; i < 100; i++) { test_timA(ctrl, channel, slotrank); FOR_ALL_LANES { statistics[lane][timA_delta + 25] += - does_lane_work(ctrl, channel, slotrank, - lane); + does_lane_work(ctrl, channel, slotrank, lane); } } } @@ -1329,18 +1180,19 @@ static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, for (last_zero = -25; last_zero <= 25; last_zero++) if (statistics[lane][last_zero + 25]) break; + last_zero--; for (first_all = -25; first_all <= 25; first_all++) if (statistics[lane][first_all + 25] == 100) break; - printram("lane %d: %d, %d\n", lane, last_zero, - first_all); + printram("lane %d: %d, %d\n", lane, last_zero, first_all); ctrl->timings[channel][slotrank].lanes[lane].timA = - (last_zero + first_all) / 2 + upperA[lane]; + (last_zero + first_all) / 2 + upperA[lane]; + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timA); + lane, ctrl->timings[channel][slotrank].lanes[lane].timA); } } @@ -1348,13 +1200,16 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *up { int works[NUM_LANES]; int lane; + while (1) { int all_works = 1, some_works = 0; + program_timings(ctrl, channel); test_timA(ctrl, channel, slotrank); + FOR_ALL_LANES { - works[lane] = - !does_lane_work(ctrl, channel, slotrank, lane); + works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); + if (works[lane]) some_works = 1; else @@ -1362,6 +1217,7 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *up } if (all_works) return 0; + if (!some_works) { if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", @@ -1374,6 +1230,7 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *up } ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n"); + if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank); @@ -1417,15 +1274,17 @@ static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, struct timA_minmax post; int shift_402x = 0; - /* Get changed maxima. */ + /* Get changed maxima */ pre_timA_change(ctrl, channel, slotrank, &post); if (mnmx->timA_max_high - mnmx->timA_min_high < post.timA_max_high - post.timA_min_high) shift_402x = +1; + else if (mnmx->timA_max_high - mnmx->timA_min_high > post.timA_max_high - post.timA_min_high) shift_402x = -1; + else shift_402x = 0; @@ -1435,17 +1294,21 @@ static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, printram("4028 += %d;\n", shift_402x); } -/* Compensate the skew between DQS and DQs. +/* + * Compensate the skew between DQS and DQs. + * * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. * The controller has to measure and compensate this skew for every byte-lane. By delaying - * either all DQs signals or DQS signal, a full phase shift can be introduced. It is assumed + * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed * that one byte-lane's DQs signals have the same routing delay. * * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates * over all possible values to do a full phase shift and issues read commands. With DQS and - * DQs in phase the data read is expected to alternate on every byte: + * DQ in phase the data being read is expected to alternate on every byte: + * * 0xFF 0x00 0xFF ... + * * Once the controller has detected this pattern a bit in the result register is set for the * current phase shift. */ @@ -1462,12 +1325,12 @@ int read_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; @@ -1519,7 +1382,8 @@ int read_training(ramctr_timing *ctrl) pre_timA_change(ctrl, channel, slotrank, &mnmx); FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; + ctrl->timings[channel][slotrank].lanes[lane].timA -= + mnmx.timA_min_high * 0x40; } ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; printram("4028 -= %d;\n", mnmx.timA_min_high); @@ -1532,8 +1396,7 @@ int read_training(ramctr_timing *ctrl) printram("final results:\n"); FOR_ALL_LANES - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1562,65 +1425,63 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 4 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (6 << 16); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8041001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8041001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x80411f4; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x80411f4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = - 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = + 0x08000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = - (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) - | 8 | (ctrl->CAS << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x244; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -1634,30 +1495,32 @@ static void timC_threshold_process(int *data, const int count) for (i = 1; i < count; i++) { if (min > data[i]) min = data[i]; + if (max < data[i]) max = data[i]; } - int threshold = min/2 + max/2; + int threshold = min / 2 + max / 2; for (i = 0; i < count; i++) data[i] = data[i] > threshold; + printram("threshold=%d min=%d max=%d\n", threshold, min, max); } static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; - int statistics[NUM_LANES][MAX_TIMC + 1]; + int stats[NUM_LANES][MAX_TIMC + 1]; int lane; wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); for (timC = 0; timC <= MAX_TIMC; timC++) { @@ -1667,24 +1530,22 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) test_timC(ctrl, channel, slotrank); FOR_ALL_LANES { - statistics[lane][timC] = - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } FOR_ALL_LANES { - struct run rn = get_longest_zero_run( - statistics[lane], ARRAY_SIZE(statistics[lane])); + struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); + if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", channel, slotrank, lane); - /* With command training not happend yet, the lane can - * be erroneous. Take the avarage as reference and try - * again to find a run. + /* + * With command training not being done yet, the lane can be erroneous. + * Take the average as reference and try again to find a run. */ - timC_threshold_process(statistics[lane], - ARRAY_SIZE(statistics[lane])); - rn = get_longest_zero_run(statistics[lane], - ARRAY_SIZE(statistics[lane])); + timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); + rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); + if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC recovery failed\n"); return MAKE_ERR; @@ -1700,8 +1561,10 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) { int channel, ret = 0; + FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) ret++; + return ret; } @@ -1709,8 +1572,10 @@ static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) { unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; + for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); + sfence(); } @@ -1727,10 +1592,13 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel) unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_step = 0x40 * num_of_channels(ctrl); + for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); + for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); + sfence(); } @@ -1750,40 +1618,40 @@ static void precharge(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command MRS - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -1802,37 +1670,37 @@ static void precharge(ramctr_timing *ctrl) * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -1847,19 +1715,19 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 8 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f107; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f107; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 4; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); wait_for_iosav(channel); @@ -1892,23 +1760,25 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) } FOR_ALL_LANES { struct run rn = get_longest_zero_run(statistics[lane], 128); - /* timC is a direct function of timB's 6 LSBs. - * Some tests increments the value of timB by a small value, - * which might cause the 6bit value to overflow, if it's close - * to 0x3F. Increment the value by a small offset if it's likely - * to overflow, to make sure it won't overflow while running - * tests and bricks the system due to a non matching timC. + /* + * timC is a direct function of timB's 6 LSBs. Some tests increments the value + * of timB by a small value, which might cause the 6-bit value to overflow if + * it's close to 0x3f. Increment the value by a small offset if it's likely + * to overflow, to make sure it won't overflow while running tests and bricks + * the system due to a non matching timC. * - * TODO: find out why some tests (edge write discovery) - * increment timB. */ - if ((rn.start & 0x3F) == 0x3E) + * TODO: find out why some tests (edge write discovery) increment timB. + */ + if ((rn.start & 0x3f) == 0x3e) rn.start += 2; - else if ((rn.start & 0x3F) == 0x3F) + else if ((rn.start & 0x3f) == 0x3f) rn.start += 1; + ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; if (rn.all) { printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", channel, slotrank, lane); + return MAKE_ERR; } printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", @@ -1954,56 +1824,56 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8040c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8040c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x8041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x8041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x3e2; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x3e2; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x3f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x3f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].roundtrip_latency + ctrl->timings[channel][slotrank].io_latency) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60008; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); wait_for_iosav(channel); @@ -2033,28 +1903,28 @@ static void write_op(ramctr_timing *ctrl, int channel) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); } -/* Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. - * DDR3 adopted the fly-by topology. The data and strobes signals reach - * the chips at different times with respect to command, address and - * clock signals. - * By delaying either all DQ/DQs or all CMD/ADDR/CLK signals, a full phase - * shift can be introduced. - * It is assumed that the CLK/ADDR/CMD signals have the same routing delay. +/* + * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. * - * To find the required phase shift the DRAM is placed in "write leveling" mode. - * In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the - * sampled value on the data lanes (DQs). + * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different + * times with respect to command, address and clock signals. By delaying either all DQ/DQS or + * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the + * CLK/ADDR/CMD signals have the same routing delay. + * + * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, + * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data + * lanes (DQ). */ int write_training(ramctr_timing *ctrl) { @@ -2069,42 +1939,40 @@ int write_training(ramctr_timing *ctrl) MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); } - /* refresh disable */ + /* Refresh disable */ MCHBAR32_AND(MC_INIT_STATE_G, ~8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } - /* enable write leveling on all ranks - * disable all DQ outputs - * only NOP is allowed in this mode */ - FOR_ALL_CHANNELS - FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, + /* Enable write leveling on all ranks + Disable all DQ outputs + Only NOP is allowed in this mode */ + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS + write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 0x1080); MCHBAR32(GDCRTRAININGMOD) = 0x108052; toggle_io_reset(); - /* set any valid value for timB, it gets corrected later */ + /* Set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_timB(ctrl, channel, slotrank); if (err) return err; } - /* disable write leveling on all ranks */ + /* Disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, - slotrank, 1, make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); MCHBAR32(GDCRTRAININGMOD) = 0; FOR_ALL_POPULATED_CHANNELS wait_for_iosav(channel); - /* refresh enable */ + /* Refresh enable */ MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { @@ -2113,12 +1981,12 @@ int write_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x659001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); @@ -2182,37 +2050,37 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | ctr | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x20e42; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x20e42; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x20e42; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x20e42; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xf1001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xf1001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2237,8 +2105,8 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) { unsigned int i, j; - unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; - unsigned int channel_step = 0x40 * num_of_channels(ctrl); + unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; + unsigned int step = 0x40 * num_of_channels(ctrl); if (patno) { u8 base8 = 0x80 >> ((patno - 1) % 8); @@ -2246,18 +2114,19 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) for (i = 0; i < 32; i++) { for (j = 0; j < 16; j++) { u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; + if (invert[patno - 1][i] & (1 << (j / 2))) val = ~val; - write32((void *)(0x04000000 + channel_offset + i * channel_step + - j * 4), val); + + write32((void *)((1 << 26) + offset + i * step + j * 4), val); } } - } else { - for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) { - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + i * channel_step + - j * 4), pattern[i][j]); + for (i = 0; i < ARRAY_SIZE(pattern); i++) { + for (j = 0; j < 16; j++) { + const u32 val = pattern[i][j]; + write32((void *)((1 << 26) + offset + i * step + j * 4), val); + } } sfence(); } @@ -2270,16 +2139,16 @@ static void reprogram_320c(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); - /* choose an existing rank. */ + /* Choose an existing rank */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); @@ -2295,20 +2164,21 @@ static void reprogram_320c(ramctr_timing *ctrl) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); } - /* jedec reset */ + /* JEDEC reset */ dram_jedecreset(ctrl); - /* mrs commands. */ + + /* MRS commands */ dram_mrscommands(ctrl); toggle_io_reset(); @@ -2333,12 +2203,12 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) ctrl->cmd_stretch[channel] = cmd_stretch; MCHBAR32(TC_RAP_ch(channel)) = - ctrl->tRRD - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) + (ctrl->tRRD << 0) + | (ctrl->tRTP << 4) + | (ctrl->tCKE << 8) | (ctrl->tWTR << 12) | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) + | (ctrl->tWR << 24) | (ctrl->cmd_stretch[channel] << 30); if (ctrl->cmd_stretch[channel] == 2) @@ -2361,11 +2231,12 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) } } FOR_ALL_POPULATED_RANKS { - struct run rn = - get_longest_zero_run(stat[slotrank], 255); + struct run rn = get_longest_zero_run(stat[slotrank], 255); + ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, rn.start, rn.middle, rn.end); + if (rn.all || rn.length < MIN_C320C_LEN) { FOR_ALL_POPULATED_RANKS { ctrl->timings[channel][slotrank] = @@ -2378,9 +2249,10 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) return 0; } -/* Adjust CMD phase shift and try multiple command rates. - * A command rate of 2T doubles the time needed for address and - * command decode. */ +/* + * Adjust CMD phase shift and try multiple command rates. + * A command rate of 2T doubles the time needed for address and command decode. + */ int command_training(ramctr_timing *ctrl) { int channel; @@ -2395,12 +2267,12 @@ int command_training(ramctr_timing *ctrl) /* * Dual DIMM per channel: - * Issue: While c320c discovery seems to succeed raminit - * will fail in write training. - * Workaround: Skip 1T in dual DIMM mode, that's only - * supported by a few DIMMs. - * Only try 1T mode for XMP DIMMs that request it in dual DIMM - * mode. + * Issue: + * While c320c discovery seems to succeed raminit will fail in write training. + * + * Workaround: + * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. + * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. * * Single DIMM per channel: * Try command rate 1T and 2T @@ -2432,16 +2304,15 @@ int command_training(ramctr_timing *ctrl) return 0; } - static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; - int statistics[NUM_LANES][MAX_EDGE_TIMING + 1]; + int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; int lane; for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = edge; + ctrl->timings[channel][slotrank].lanes[lane].rising = edge; ctrl->timings[channel][slotrank].lanes[lane].falling = edge; } program_timings(ctrl, channel); @@ -2452,54 +2323,55 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i } wait_for_iosav(channel); + /* DRAM command MRS - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x40411f4; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x40411f4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS - * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); + MR3 disable MPR */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); FOR_ALL_LANES { - statistics[lane][edge] = - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } + FOR_ALL_LANES { - struct run rn = get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); + struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); edges[lane] = rn.middle; + if (rn.all) { - printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, + slotrank, lane); return MAKE_ERR; } - printram("eval %d, %d, %d: %02x\n", channel, slotrank, - lane, edges[lane]); + printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); } return 0; } @@ -2537,41 +2409,41 @@ int discover_edges(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command MRS - * MR3 enable MPR - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MR3 enable MPR + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2581,7 +2453,7 @@ int discover_edges(ramctr_timing *ctrl) FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; + ctrl->timings[channel][slotrank].lanes[lane].rising = 48; } program_timings(ctrl, channel); @@ -2590,42 +2462,42 @@ int discover_edges(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command MRS - * MR3 enable MPR - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MR3 enable MPR + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2682,12 +2554,11 @@ int discover_edges(ramctr_timing *ctrl) return 0; } -static int discover_edges_write_real(ramctr_timing *ctrl, int channel, - int slotrank, int *edges) +static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; - u32 raw_statistics[MAX_EDGE_TIMING + 1]; - int statistics[MAX_EDGE_TIMING + 1]; + u32 raw_stats[MAX_EDGE_TIMING + 1]; + int stats[MAX_EDGE_TIMING + 1]; const int reg3000b24[] = { 0, 0xc, 0x2c }; int lane, i; int lower[NUM_LANES]; @@ -2701,12 +2572,13 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, for (i = 0; i < 3; i++) { MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; - printram("[%x] = 0x%08x\n", - GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; printram("using pattern %d\n", pat); + for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -2723,68 +2595,70 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x4 | (ctrl->tRCD << 16) | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8005020 | + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = - IOSAV_RUN_ONCE(4); + /* Execute command queue */ + MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); FOR_ALL_LANES { MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } - raw_statistics[edge] = MCHBAR32(0x436c + channel * 0x400); + /* FIXME: This register only exists on Ivy Bridge */ + raw_stats[edge] = MCHBAR32(0x436c + channel * 0x400); } + FOR_ALL_LANES { struct run rn; for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) - statistics[edge] = - ! !(raw_statistics[edge] & (1 << lane)); - rn = get_longest_zero_run(statistics, - MAX_EDGE_TIMING + 1); - printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", - channel, slotrank, i, rn.start, rn.middle, - rn.end, rn.start + ctrl->edge_offset[i], + stats[edge] = !!(raw_stats[edge] & (1 << lane)); + + rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); + + printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " + "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, + rn.middle, rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); - lower[lane] = - MAX(rn.start + ctrl->edge_offset[i], lower[lane]); - upper[lane] = - MIN(rn.end - ctrl->edge_offset[i], upper[lane]); + + lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); + upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); + edges[lane] = (lower[lane] + upper[lane]) / 2; if (rn.all || (lower[lane] > upper[lane])) { - printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + printk(BIOS_EMERG, "edge write discovery failed: " + "%d, %d, %d\n", channel, slotrank, lane); + return MAKE_ERR; } } @@ -2799,17 +2673,19 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int discover_edges_write(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane; - int err; + int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; + int channel, slotrank, lane, err; - /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ + /* + * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will + * also use a single loop. It would seem that it is a debugging configuration. + */ MCHBAR32(IOSAV_DC_MASK) = 0x300; printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_write_real(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + falling_edges[channel][slotrank]); if (err) return err; } @@ -2819,7 +2695,7 @@ int discover_edges_write(ramctr_timing *ctrl) FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_write_real(ctrl, channel, slotrank, - rising_edges[channel][slotrank]); + rising_edges[channel][slotrank]); if (err) return err; } @@ -2828,9 +2704,10 @@ int discover_edges_write(ramctr_timing *ctrl) FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = - falling_edges[channel][slotrank][lane]; + falling_edges[channel][slotrank][lane]; + ctrl->timings[channel][slotrank].lanes[lane].rising = - rising_edges[channel][slotrank][lane]; + rising_edges[channel][slotrank][lane]; } FOR_ALL_POPULATED_CHANNELS @@ -2845,34 +2722,34 @@ int discover_edges_write(ramctr_timing *ctrl) static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); + /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x0244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2880,7 +2757,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) int discover_timC_write(ramctr_timing *ctrl) { - const u8 rege3c_b24[3] = { 0, 0xf, 0x2f }; + const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; int i, pat; int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2901,53 +2778,65 @@ int discover_timC_write(ramctr_timing *ctrl) for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000, - rege3c_b24[i] << 24); + + /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ + MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), + ~0x3f000000, rege3c_b24[i] << 24); + udelay(2); + for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { int timC; - u32 raw_statistics[MAX_TIMC + 1]; - int statistics[MAX_TIMC + 1]; + u32 raw_stats[MAX_TIMC + 1]; + int stats[MAX_TIMC + 1]; /* Make sure rn.start < rn.end */ - statistics[MAX_TIMC] = 1; + stats[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = - 0x1f; + MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; + for (timC = 0; timC < MAX_TIMC; timC++) { - FOR_ALL_LANES - ctrl->timings[channel][slotrank].lanes[lane].timC = timC; + FOR_ALL_LANES { + ctrl->timings[channel][slotrank] + .lanes[lane].timC = timC; + } program_timings(ctrl, channel); test_timC_write (ctrl, channel, slotrank); - raw_statistics[timC] = + /* FIXME: Another IVB-only register! */ + raw_stats[timC] = MCHBAR32(0x436c + channel * 0x400); } FOR_ALL_LANES { struct run rn; - for (timC = 0; timC < MAX_TIMC; timC++) - statistics[timC] = - !!(raw_statistics[timC] & - (1 << lane)); + for (timC = 0; timC < MAX_TIMC; timC++) { + stats[timC] = !!(raw_stats[timC] + & (1 << lane)); + } - rn = get_longest_zero_run(statistics, - MAX_TIMC + 1); + rn = get_longest_zero_run(stats, MAX_TIMC + 1); if (rn.all) { - printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + printk(BIOS_EMERG, + "timC write discovery failed: " + "%d, %d, %d\n", channel, + slotrank, lane); + return MAKE_ERR; } - printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", - channel, slotrank, i, rn.start, - rn.middle, rn.end, + printram("timC: %d, %d, %d: " + "0x%02x-0x%02x-0x%02x, " + "0x%02x-0x%02x\n", channel, slotrank, + i, rn.start, rn.middle, rn.end, rn.start + ctrl->timC_offset[i], - rn.end - ctrl->timC_offset[i]); + rn.end - ctrl->timC_offset[i]); + lower[channel][slotrank][lane] = MAX(rn.start + ctrl->timC_offset[i], lower[channel][slotrank][lane]); + upper[channel][slotrank][lane] = MIN(rn.end - ctrl->timC_offset[i], upper[channel][slotrank][lane]); @@ -2958,6 +2847,7 @@ int discover_timC_write(ramctr_timing *ctrl) } FOR_ALL_CHANNELS { + /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); udelay(2); } @@ -2971,10 +2861,10 @@ int discover_timC_write(ramctr_timing *ctrl) printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC %d, %d, %d: %x\n", channel, - slotrank, lane, + printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2); + ctrl->timings[channel][slotrank].lanes[lane].timC = (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2; @@ -3049,30 +2939,30 @@ int channel_test(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0001f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x0028a004; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x0028a004; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x00060000 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x00000244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x0001f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x08281064; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x0001f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281064; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x00000242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0001f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x04281064; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0001f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x04281064; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x00000242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x0001f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0x00280c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x0001f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x00280c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = 0x00060400 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x00000240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x00000240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -3090,29 +2980,27 @@ void set_scrambling_seed(ramctr_timing *ctrl) { int channel; - /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? - I don't think so. */ + /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ static u32 seeds[NUM_CHANNELS][3] = { {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, {0x00028bfa, 0x53fe4b49, 0x19ed5483} }; FOR_ALL_POPULATED_CHANNELS { MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; - MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; - MCHBAR32(SCRAMBLING_SEED_2_HIGH_ch(channel)) = seeds[channel][1]; - MCHBAR32(SCRAMBLING_SEED_2_LOW_ch(channel)) = seeds[channel][2]; + MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; + MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; + MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; } } -void set_4f8c(void) +void set_wmm_behavior(void) { - u32 cpu; + u32 cpu = cpu_get_cpuid(); - cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { - MCHBAR32(SC_WDBWM) = 0x141D1519; + MCHBAR32(SC_WDBWM) = 0x141d1519; } else { - MCHBAR32(SC_WDBWM) = 0x551D1519; + MCHBAR32(SC_WDBWM) = 0x551d1519; } } @@ -3121,7 +3009,7 @@ void prepare_training(ramctr_timing *ctrl) int channel; FOR_ALL_POPULATED_CHANNELS { - // Always drive command bus + /* Always drive command bus */ MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); } @@ -3132,7 +3020,7 @@ void prepare_training(ramctr_timing *ctrl) } } -void set_4008c(ramctr_timing *ctrl) +void set_read_write_timings(ramctr_timing *ctrl) { int channel, slotrank; @@ -3146,20 +3034,13 @@ void set_4008c(ramctr_timing *ctrl) min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); } - if (max_pi - min_pi > 51) - b20 = 0; - else - b20 = ctrl->ref_card_offset[channel]; + b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; - if (ctrl->pi_coding_threshold < max_pi - min_pi) - b4_8_12 = 0x3330; - else - b4_8_12 = 0x2220; + b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; dram_odt_stretch(ctrl, channel); - MCHBAR32(TC_RWP_ch(channel)) = - 0x0a000000 | (b20 << 20) | + MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } } @@ -3173,12 +3054,13 @@ void set_normal_operation(ramctr_timing *ctrl) } } -static int encode_5d10(int ns) +/* Encode the watermark latencies in a suitable format for graphics drivers consumption */ +static int encode_wm(int ns) { return (ns + 499) / 500; } -/* FIXME: values in this function should be hardware revision-dependent. */ +/* FIXME: values in this function should be hardware revision-dependent */ void final_registers(ramctr_timing *ctrl) { const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; @@ -3188,17 +3070,17 @@ void final_registers(ramctr_timing *ctrl) int t3_ns; u32 r32; - /* FIXME: This register only exists on Ivy Bridge. */ - MCHBAR32(WMM_READ_CONFIG) = 0x00000046; + /* FIXME: This register only exists on Ivy Bridge */ + MCHBAR32(WMM_READ_CONFIG) = 0x46; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xFFFFCFFF, 0x1000); + MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; else - /* APD - PPD, 64 DCLKs until idle, decision per rank */ + /* APD - PPD, 64 DCLKs until idle, decision per rank */ MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; FOR_ALL_CHANNELS @@ -3209,75 +3091,76 @@ void final_registers(ramctr_timing *ctrl) FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { - /* Unpopulated channel. */ + /* Unpopulated channel */ case 0: MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; break; - /* Only single-ranked dimms. */ + /* Only single-ranked dimms */ case 1: case 4: case 5: - MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x373131; + MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; break; - /* Dual-ranked dimms present. */ + /* Dual-ranked dimms present */ default: - MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x9b6ea1; + MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; break; } } MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0xffffff, 0xe4d5d0); + MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~0x30000, 1 << 16); + MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); MCHBAR32_OR(MC_INIT_STATE_G, 1); MCHBAR32_OR(MC_INIT_STATE_G, 0x80); MCHBAR32(BANDTIMERS_SNB) = 0xfa; - /* Find a populated channel. */ + /* Find a populated channel */ FOR_ALL_POPULATED_CHANNELS break; t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; r32 = MCHBAR32(PM_DLL_CONFIG); - if (r32 & 0x20000) + if (r32 & (1 << 17)) t1_cycles += (r32 & 0xfff); t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; t1_ns = t1_cycles * ctrl->tCK / 256 + 544; - if (!(r32 & 0x20000)) + if (!(r32 & (1 << 17))) t1_ns += 500; t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); if (MCHBAR32(SAPMCTL) & 8) { - t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); + t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); } else { t3_ns = 500; } - printk(BIOS_DEBUG, "t123: %d, %d, %d\n", - t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(0x5d10, 0xC0C0C0C0, - ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | - (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + - encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | 0xc); + + /* The graphics driver will use these watermark values */ + printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); + MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, + ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | + ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); } void restore_timings(ramctr_timing *ctrl) { int channel, slotrank, lane; - FOR_ALL_POPULATED_CHANNELS - MCHBAR32(TC_RAP_ch(channel)) = - ctrl->tRRD - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) - | (ctrl->tWTR << 12) - | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) - | (ctrl->cmd_stretch[channel] << 30); + FOR_ALL_POPULATED_CHANNELS { + MCHBAR32(TC_RAP_ch(channel)) = + (ctrl->tRRD << 0) + | (ctrl->tRTP << 4) + | (ctrl->tCKE << 8) + | (ctrl->tWTR << 12) + | (ctrl->tFAW << 16) + | (ctrl->tWR << 24) + | (ctrl->cmd_stretch[channel] << 30); + } udelay(1); @@ -3290,11 +3173,11 @@ void restore_timings(ramctr_timing *ctrl) } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); FOR_ALL_POPULATED_CHANNELS { - udelay (1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + udelay(1); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); } printram("CPE\n"); @@ -3310,36 +3193,39 @@ void restore_timings(ramctr_timing *ctrl) u32 reg, addr; - while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); + /* Poll for RCOMP */ + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; + do { reg = MCHBAR32(IOSAV_STATUS_ch(0)); } while ((reg & 0x14) == 0); - // Set state of memory controller + /* Set state of memory controller */ MCHBAR32(MC_INIT_STATE_G) = 0x116; - MCHBAR32(MC_INIT_STATE) = 0; + MCHBAR32(MC_INIT_STATE) = 0; - // Wait 500us + /* Wait 500us */ udelay(500); FOR_ALL_CHANNELS { - // Set valid rank CKE + /* Set valid rank CKE */ reg = 0; - reg = (reg & ~0xf) | ctrl->rankmap[channel]; + reg = (reg & ~0x0f) | ctrl->rankmap[channel]; addr = MC_INIT_STATE_ch(channel); MCHBAR32(addr) = reg; - // Wait 10ns for ranks to settle - //udelay(0.01); + /* Wait 10ns for ranks to settle */ + // udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); MCHBAR32(addr) = reg; - // Write reset using a NOP + /* Write reset using a NOP */ write_reset(ctrl); } - /* mrs commands. */ + /* MRS commands */ dram_mrscommands(ctrl); printram("CP5c\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index b1abf5e83a..0735ceaa8f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -17,29 +17,29 @@ #include -#define BASEFREQ 133 -#define tDLLK 512 +#define BASEFREQ 133 +#define tDLLK 512 -#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) -#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) +#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) +#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) -#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) +#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) #define IS_IVY_CPU_C(x) ((x & 0xf) == 4) #define IS_IVY_CPU_K(x) ((x & 0xf) == 5) #define IS_IVY_CPU_D(x) ((x & 0xf) == 6) #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) -#define NUM_CHANNELS 2 -#define NUM_SLOTRANKS 4 -#define NUM_SLOTS 2 -#define NUM_LANES 8 +#define NUM_CHANNELS 2 +#define NUM_SLOTRANKS 4 +#define NUM_SLOTS 2 +#define NUM_LANES 8 /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ -#define NUM_PATTERNS 4 +#define NUM_PATTERNS 4 typedef struct odtmap_st { u16 rttwr; @@ -51,24 +51,24 @@ typedef struct dimm_info_st { } dimm_info; struct ram_rank_timings { - /* ROUNDT_LAT register. One byte per slotrank. */ + /* ROUNDT_LAT register: One byte per slotrank */ u8 roundtrip_latency; - /* IO_LATENCY register. One nibble per slotrank. */ + /* IO_LATENCY register: One nibble per slotrank */ u8 io_latency; - /* Phase interpolator coding for command and control. */ + /* Phase interpolator coding for command and control */ int pi_coding; struct ram_lane_timings { - /* lane register offset 0x10. */ - u16 timA; /* bits 0 - 5, bits 16 - 18 */ - u8 rising; /* bits 8 - 14 */ - u8 falling; /* bits 20 - 26. */ + /* Lane register offset 0x10 */ + u16 timA; /* bits 0 - 5, bits 16 - 18 */ + u8 rising; /* bits 8 - 14 */ + u8 falling; /* bits 20 - 26 */ - /* lane register offset 0x20. */ - int timC; /* bit 0 - 5, 19. */ - u16 timB; /* bits 8 - 13, 15 - 17. */ + /* Lane register offset 0x20 */ + int timC; /* bits 0 - 5, 19 */ + u16 timB; /* bits 8 - 13, 15 - 17 */ } lanes[NUM_LANES]; }; @@ -82,7 +82,7 @@ typedef struct ramctr_timing_st { u8 base_freq; u16 cas_supported; - /* tLatencies are in units of ns, scaled by x256 */ + /* Latencies are in units of ns, scaled by x256 */ u32 tCK; u32 tAA; u32 tWR; @@ -97,8 +97,8 @@ typedef struct ramctr_timing_st { u32 tCWL; u32 tCMD; /* Latencies in terms of clock cycles - * They are saved separately as they are needed for DRAM MRS commands */ - u8 CAS; /* CAS read latency */ + They are saved separately as they are needed for DRAM MRS commands */ + u8 CAS; /* CAS read latency */ u8 CWL; /* CAS write latency */ u32 tREFI; @@ -110,7 +110,7 @@ typedef struct ramctr_timing_st { u32 tXP; u32 tAONPD; - /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer. */ + /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */ u16 mdll_wake_delay; u8 rankmap[NUM_CHANNELS]; @@ -135,7 +135,6 @@ typedef struct ramctr_timing_st { dimm_info info; } ramctr_timing; -#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) #define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++) @@ -149,8 +148,8 @@ typedef struct ramctr_timing_st { #define MAX_CAS 18 #define MIN_CAS 4 -#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) -#define GET_ERR_CHANNEL(x) (x>>16) +#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) +#define GET_ERR_CHANNEL(x) (x >> 16) u8 get_CWL(u32 tCK); void dram_mrscommands(ramctr_timing *ctrl); @@ -174,17 +173,14 @@ void normalize_training(ramctr_timing *ctrl); void write_controller_mr(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); -void set_4f8c(void); +void set_wmm_behavior(void); void prepare_training(ramctr_timing *ctrl); -void set_4008c(ramctr_timing *ctrl); +void set_read_write_timings(ramctr_timing *ctrl); void set_normal_operation(ramctr_timing *ctrl); void final_registers(ramctr_timing *ctrl); void restore_timings(ramctr_timing *ctrl); -int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size); - -int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size); +int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size); +int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size); #endif diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index a992d9c98c..06d23825b6 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -19,12 +19,10 @@ #include "raminit_native.h" #include "raminit_common.h" -/* Frequency multiplier. */ +/* Frequency multiplier */ static u32 get_FRQ(u32 tCK, u8 base_freq) { - u32 FRQ; - - FRQ = 256000 / (tCK * base_freq); + const u32 FRQ = 256000 / (tCK * base_freq); if (base_freq == 100) { if (FRQ > 12) @@ -41,249 +39,181 @@ static u32 get_FRQ(u32 tCK, u8 base_freq) return FRQ; } +/* Get REFI based on MC frequency, tREFI = 7.8usec */ static u32 get_REFI(u32 tCK, u8 base_freq) { - u32 refi; - if (base_freq == 100) { - /* Get REFI based on MCU frequency using the following rule: - * tREFI = 7.8usec - * _________________________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * REFI : | 5460 | 6240 | 7020 | 7800 | 8580 | 9360 | - */ - static const u32 frq_xs_map[] = - { 5460, 6240, 7020, 7800, 8580, 9360 }; - refi = frq_xs_map[get_FRQ(tCK, 100) - 7]; - } else { - /* Get REFI based on MCU frequency using the following rule: - * tREFI = 7.8usec - * ________________________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | 9360 | 10400 | - */ - static const u32 frq_refi_map[] = - { 3120, 4160, 5200, 6240, 7280, 8320, 9360, 10400 }; - refi = frq_refi_map[get_FRQ(tCK, 133) - 3]; - } + static const u32 frq_xs_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 5460, 6240, 7020, 7800, 8580, 9360, + }; + return frq_xs_map[get_FRQ(tCK, 100) - 7]; - return refi; + } else { + static const u32 frq_refi_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 3120, 4160, 5200, 6240, 7280, 8320, 9360, 10400, + }; + return frq_refi_map[get_FRQ(tCK, 133) - 3]; + } } +/* Get XSOffset based on MC frequency, tXS-Offset: tXS = tRFC + 10ns */ static u8 get_XSOffset(u32 tCK, u8 base_freq) { - u8 xsoffset; - if (base_freq == 100) { - /* Get XSOffset based on MCU frequency using the following rule: - * tXS-offset: tXS = tRFC+10ns. - * _____________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * XSOffset : | 7 | 8 | 9 | 10 | 11 | 12 | - */ - static const u8 frq_xs_map[] = { 7, 8, 9, 10, 11, 12 }; - xsoffset = frq_xs_map[get_FRQ(tCK, 100) - 7]; - } else { - /* Get XSOffset based on MCU frequency using the following rule: - * ___________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | 12 | 14 | - */ - static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11, 12, 14 }; - xsoffset = frq_xs_map[get_FRQ(tCK, 133) - 3]; - } + static const u8 frq_xs_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 7, 8, 9, 10, 11, 12, + }; + return frq_xs_map[get_FRQ(tCK, 100) - 7]; - return xsoffset; + } else { + static const u8 frq_xs_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 4, 6, 7, 8, 10, 11, 12, 14, + }; + return frq_xs_map[get_FRQ(tCK, 133) - 3]; + } } +/* Get MOD based on MC frequency */ static u8 get_MOD(u32 tCK, u8 base_freq) { - u8 mod; - if (base_freq == 100) { - /* Get MOD based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * MOD : | 12 | 12 | 14 | 15 | 17 | 18 | - */ + static const u8 frq_mod_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 12, 12, 14, 15, 17, 18, + }; + return frq_mod_map[get_FRQ(tCK, 100) - 7]; - static const u8 frq_mod_map[] = { 12, 12, 14, 15, 17, 18 }; - mod = frq_mod_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get MOD based on MCU frequency using the following rule: - * _______________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | 18 | 20 | - */ - - static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16, 18, 20 }; - mod = frq_mod_map[get_FRQ(tCK, 133) - 3]; + static const u8 frq_mod_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 12, 12, 12, 12, 15, 16, 18, 20, + }; + return frq_mod_map[get_FRQ(tCK, 133) - 3]; } - return mod; } +/* Get Write Leveling Output delay based on MC frequency */ static u8 get_WLO(u32 tCK, u8 base_freq) { - u8 wlo; - if (base_freq == 100) { - /* Get WLO based on MCU frequency using the following rule: - * Write leveling output delay - * _____________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * MOD : | 6 | 6 | 7 | 8 | 9 | 9 | - */ + static const u8 frq_wlo_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 6, 6, 7, 8, 9, 9, + }; + return frq_wlo_map[get_FRQ(tCK, 100) - 7]; - static const u8 frq_wlo_map[] = { 6, 6, 7, 8, 9, 9 }; - wlo = frq_wlo_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get WLO based on MCU frequency using the following rule: - * Write leveling output delay - * ________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | 9 | 10 | - */ - static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8, 9, 10 }; - wlo = frq_wlo_map[get_FRQ(tCK, 133) - 3]; + static const u8 frq_wlo_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 4, 5, 6, 6, 8, 8, 9, 10, + }; + return frq_wlo_map[get_FRQ(tCK, 133) - 3]; } - - return wlo; } +/* Get CKE based on MC frequency */ static u8 get_CKE(u32 tCK, u8 base_freq) { - u8 cke; - if (base_freq == 100) { - /* Get CKE based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * MOD : | 4 | 4 | 5 | 5 | 6 | 6 | - */ + static const u8 frq_cke_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 4, 4, 5, 5, 6, 6, + }; + return frq_cke_map[get_FRQ(tCK, 100) - 7]; - static const u8 frq_cke_map[] = { 4, 4, 5, 5, 6, 6 }; - cke = frq_cke_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get CKE based on MCU frequency using the following rule: - * ________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * WLO : | 3 | 3 | 4 | 4 | 5 | 6 | 6 | 7 | - */ - static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6, 6, 7 }; - cke = frq_cke_map[get_FRQ(tCK, 133) - 3]; + static const u8 frq_cke_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 3, 3, 4, 4, 5, 6, 6, 7, + }; + return frq_cke_map[get_FRQ(tCK, 133) - 3]; } - - return cke; } +/* Get XPDLL based on MC frequency */ static u8 get_XPDLL(u32 tCK, u8 base_freq) { - u8 xpdll; - if (base_freq == 100) { - /* Get XPDLL based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * XPDLL : | 17 | 20 | 22 | 24 | 27 | 32 | - */ + static const u8 frq_xpdll_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 17, 20, 22, 24, 27, 32, + }; + return frq_xpdll_map[get_FRQ(tCK, 100) - 7]; - static const u8 frq_xpdll_map[] = { 17, 20, 22, 24, 27, 32 }; - xpdll = frq_xpdll_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get XPDLL based on MCU frequency using the following rule: - * _______________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | 29 | 32 | - */ - static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26, 29, 32 }; - xpdll = frq_xpdll_map[get_FRQ(tCK, 133) - 3]; + static const u8 frq_xpdll_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 10, 13, 16, 20, 23, 26, 29, 32, + }; + return frq_xpdll_map[get_FRQ(tCK, 133) - 3]; } - - return xpdll; } +/* Get XP based on MC frequency */ static u8 get_XP(u32 tCK, u8 base_freq) { - u8 xp; - if (base_freq == 100) { - /* Get XP based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * XP : | 5 | 5 | 6 | 6 | 7 | 8 | - */ - - static const u8 frq_xp_map[] = { 5, 5, 6, 6, 7, 8 }; - xp = frq_xp_map[get_FRQ(tCK, 100) - 7]; + static const u8 frq_xp_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 5, 5, 6, 6, 7, 8, + }; + return frq_xp_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get XP based on MCU frequency using the following rule: - * _______________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * XP : | 3 | 4 | 4 | 5 | 6 | 7 | 8 | 8 | - */ - static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7, 8, 8 }; - xp = frq_xp_map[get_FRQ(tCK, 133) - 3]; - } - return xp; + static const u8 frq_xp_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 3, 4, 4, 5, 6, 7, 8, 8 + }; + return frq_xp_map[get_FRQ(tCK, 133) - 3]; + } } +/* Get AONPD based on MC frequency */ static u8 get_AONPD(u32 tCK, u8 base_freq) { - u8 aonpd; - if (base_freq == 100) { - /* Get AONPD based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * AONPD : | 6 | 8 | 8 | 9 | 10 | 11 | - */ + static const u8 frq_aonpd_map[] = { + /* FRQ: 7, 8, 9, 10, 11, 12, */ + 6, 8, 8, 9, 10, 11, + }; + return frq_aonpd_map[get_FRQ(tCK, 100) - 7]; - static const u8 frq_aonpd_map[] = { 6, 8, 8, 9, 10, 11 }; - aonpd = frq_aonpd_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get AONPD based on MCU frequency using the following rule: - * _______________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | 11 | 12 | - */ - static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10, 11, 12 }; - aonpd = frq_aonpd_map[get_FRQ(tCK, 133) - 3]; + static const u8 frq_aonpd_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 4, 5, 6, 8, 8, 10, 11, 12, + }; + return frq_aonpd_map[get_FRQ(tCK, 133) - 3]; } - - return aonpd; } +/* Get COMP2 based on MC frequency */ static u32 get_COMP2(u32 tCK, u8 base_freq) { - u32 comp2; - if (base_freq == 100) { - /* Get COMP2 based on MCU frequency using the following rule: - * ______________________________________________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * COMP : | CA8C264 | C6671E4 | C6671E4 | C446964 | C235924 | C235924 | - */ - - static const u32 frq_comp2_map[] = { 0xCA8C264, 0xC6671E4, 0xC6671E4, 0xC446964, 0xC235924, 0xC235924 }; - comp2 = frq_comp2_map[get_FRQ(tCK, 100) - 7]; - } else { - /* Get COMP2 based on MCU frequency using the following rule: - * ________________________________________________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * COMP : | D6FF5E4 | CEBDB64 | CA8C264 | C6671E4 | C446964 | C235924 | C235924 | C235924 | - */ - static const u32 frq_comp2_map[] = { 0xD6FF5E4, 0xCEBDB64, 0xCA8C264, - 0xC6671E4, 0xC446964, 0xC235924, 0xC235924, 0xC235924 + static const u32 frq_comp2_map[] = { + // FRQ: 7, 8, 9, 10, 11, 12, + 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964, 0x0C235924, 0x0C235924, }; - comp2 = frq_comp2_map[get_FRQ(tCK, 133) - 3]; - } + return frq_comp2_map[get_FRQ(tCK, 100) - 7]; - return comp2; + } else { + static const u32 frq_comp2_map[] = { + /* FRQ: 3, 4, 5, 6, */ + 0x0D6FF5E4, 0x0CEBDB64, 0x0CA8C264, 0x0C6671E4, + + /* FRQ: 7, 8, 9, 10, */ + 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924, + }; + return frq_comp2_map[get_FRQ(tCK, 133) - 3]; + } } -static void ivb_normalize_tclk(ramctr_timing *ctrl, - bool ref_100mhz_support) +static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) { if (ctrl->tCK <= TCK_1200MHZ) { ctrl->tCK = TCK_1200MHZ; @@ -324,7 +254,7 @@ static void ivb_normalize_tclk(ramctr_timing *ctrl, } if (!ref_100mhz_support && ctrl->base_freq == 100) { - /* Skip unsupported frequency. */ + /* Skip unsupported frequency */ ctrl->tCK++; ivb_normalize_tclk(ctrl, ref_100mhz_support); } @@ -333,29 +263,31 @@ static void ivb_normalize_tclk(ramctr_timing *ctrl, static void find_cas_tck(ramctr_timing *ctrl) { u8 val; - u32 val32; u32 reg32; u8 ref_100mhz_support; - /* 100 Mhz reference clock supported */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + /* 100 MHz reference clock supported */ + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); ref_100mhz_support = !!((reg32 >> 21) & 0x7); - printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", - ref_100mhz_support ? "yes" : "no"); + printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" + : "no"); /* Find CAS latency */ while (1) { - /* Normalising tCK before computing clock could potentially - * results in lower selected CAS, which is desired. + /* + * Normalising tCK before computing clock could potentially + * result in a lower selected CAS, which is desired. */ ivb_normalize_tclk(ctrl, ref_100mhz_support); if (!(ctrl->tCK)) die("Couldn't find compatible clock / CAS settings\n"); + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); for (; val <= MAX_CAS; val++) if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) break; + if (val == (MAX_CAS + 1)) { ctrl->tCK++; continue; @@ -365,9 +297,7 @@ static void find_cas_tck(ramctr_timing *ctrl) } } - val32 = NS2MHZ_DIV256 / ctrl->tCK; - printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); - + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; } @@ -375,9 +305,10 @@ static void find_cas_tck(ramctr_timing *ctrl) static void dram_timing(ramctr_timing *ctrl) { - /* Maximum supported DDR3 frequency is 1400MHz (DDR3 2800). - * We cap it at 1200Mhz (DDR3 2400). - * Then, align it to the closest JEDEC standard frequency */ + /* + * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800). + * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency. + */ if (ctrl->tCK == TCK_1200MHZ) { ctrl->edge_offset[0] = 18; //XXX: guessed ctrl->edge_offset[1] = 8; @@ -386,6 +317,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 8; ctrl->timC_offset[2] = 8; ctrl->pi_coding_threshold = 10; + } else if (ctrl->tCK == TCK_1100MHZ) { ctrl->edge_offset[0] = 17; //XXX: guessed ctrl->edge_offset[1] = 7; @@ -394,6 +326,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_1066MHZ) { ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; @@ -402,6 +335,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_1000MHZ) { ctrl->edge_offset[0] = 15; //XXX: guessed ctrl->edge_offset[1] = 6; @@ -410,6 +344,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_933MHZ) { ctrl->edge_offset[0] = 14; ctrl->edge_offset[1] = 6; @@ -418,6 +353,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_900MHZ) { ctrl->edge_offset[0] = 14; //XXX: guessed ctrl->edge_offset[1] = 6; @@ -426,6 +362,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 12; + } else if (ctrl->tCK == TCK_800MHZ) { ctrl->edge_offset[0] = 13; ctrl->edge_offset[1] = 5; @@ -434,6 +371,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_700MHZ) { ctrl->edge_offset[0] = 13; //XXX: guessed ctrl->edge_offset[1] = 5; @@ -442,6 +380,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->pi_coding_threshold = 16; + } else if (ctrl->tCK == TCK_666MHZ) { ctrl->edge_offset[0] = 10; ctrl->edge_offset[1] = 4; @@ -450,6 +389,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 4; ctrl->timC_offset[2] = 4; ctrl->pi_coding_threshold = 16; + } else if (ctrl->tCK == TCK_533MHZ) { ctrl->edge_offset[0] = 8; ctrl->edge_offset[1] = 3; @@ -458,6 +398,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 3; ctrl->timC_offset[2] = 3; ctrl->pi_coding_threshold = 17; + } else { /* TCK_400MHZ */ ctrl->edge_offset[0] = 6; ctrl->edge_offset[1] = 2; @@ -478,13 +419,14 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); else ctrl->CWL = get_CWL(ctrl->tCK); + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ @@ -492,7 +434,7 @@ static void dram_timing(ramctr_timing *ctrl) printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ @@ -515,21 +457,22 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); - ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); + ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); + ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); ctrl->tXSOffset = get_XSOffset(ctrl->tCK, ctrl->base_freq); - ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); - ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); - ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); - ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); + ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); + ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); + ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); } static void dram_freq(ramctr_timing *ctrl) { if (ctrl->tCK > TCK_400MHZ) { - printk (BIOS_ERR, "DRAM frequency is under lowest supported " - "frequency (400 MHz). Increasing to 400 MHz as last resort"); + printk(BIOS_ERR, + "DRAM frequency is under lowest supported frequency (400 MHz). " + "Increasing to 400 MHz as last resort"); ctrl->tCK = TCK_400MHZ; } @@ -540,11 +483,12 @@ static void dram_freq(ramctr_timing *ctrl) /* Step 1 - Set target PCU frequency */ find_cas_tck(ctrl); - /* Frequency multiplier. */ - u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + /* Frequency multiplier */ + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); - /* The PLL will never lock if the required frequency is - * already set. Exit early to prevent a system hang. + /* + * The PLL will never lock if the required frequency is already set. + * Exit early to prevent a system hang. */ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; @@ -554,10 +498,11 @@ static void dram_freq(ramctr_timing *ctrl) /* Step 2 - Select frequency in the MCU */ reg1 = FRQ; if (ctrl->base_freq == 100) - reg1 |= 0x100; /* Enable 100Mhz REF clock */ - reg1 |= 0x80000000; // set running bit + reg1 |= 0x100; /* Enable 100Mhz REF clock */ + + reg1 |= 0x80000000; /* set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; - int i=0; + int i = 0; printk(BIOS_DEBUG, "PLL busy... "); while (reg1 & 0x80000000) { udelay(10); @@ -581,61 +526,57 @@ static void dram_freq(ramctr_timing *ctrl) static void dram_ioregs(ramctr_timing *ctrl) { - u32 reg, comp2; + u32 reg; int channel; - // IO clock + /* IO clock */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO command + /* IO command */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO control + /* IO control */ FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - // Rcomp + /* Perform RCOMP */ printram("RCOMP..."); - reg = 0; - while (reg == 0) { - reg = MCHBAR32(RCOMP_TIMER) & 0x10000; - } + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; + printram("done\n"); - // Set comp2 - comp2 = get_COMP2(ctrl->tCK, ctrl->base_freq); - MCHBAR32(CRCOMPOFST2) = comp2; + /* Set COMP2 */ + MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK, ctrl->base_freq); printram("COMP2 done\n"); - // Set comp1 + /* Set COMP1 */ FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(CRCOMPOFST1_ch(channel)); //ch0 - reg = (reg & ~0xe00) | (1 << 9); //odt - reg = (reg & ~0xe00000) | (1 << 21); //clk drive up - reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up + reg = MCHBAR32(CRCOMPOFST1_ch(channel)); + reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ + reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ + reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; } printram("COMP1 done\n"); printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(M_COMP) |= 0x100; + MCHBAR32(M_COMP) |= (1 << 8); udelay(20); printram("done\n"); } -int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size) +int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) { int err; - printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", - fast_boot); + printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", fast_boot); if (!fast_boot) { /* Find fastest common supported parameters */ @@ -644,7 +585,7 @@ int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, dram_dimm_mapping(ctrl); } - /* Set MCU frequency */ + /* Set MC frequency */ dram_freq(ctrl); if (!fast_boot) { @@ -653,7 +594,7 @@ int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, } /* Set version register */ - MCHBAR32(MRC_REVISION) = 0xC04EB002; + MCHBAR32(MRC_REVISION) = 0xc04eb002; /* Enable crossover */ dram_xover(ctrl); @@ -667,11 +608,11 @@ int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, /* Set scheduler chicken bits */ MCHBAR32(SCHED_CBIT) = 0x10100005; - /* Set CPU specific register */ - set_4f8c(); + /* Set up watermarks and starvation counter */ + set_wmm_behavior(); /* Clear IO reset bit */ - MCHBAR32(MC_INIT_STATE_G) &= ~0x20; + MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); /* Set MAD-DIMM registers */ dram_dimm_set_mapping(ctrl); @@ -693,7 +634,7 @@ int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, if (fast_boot) { restore_timings(ctrl); } else { - /* Do jedec ddr3 reset sequence */ + /* Do JEDEC DDR3 reset sequence */ dram_jedecreset(ctrl); printk(BIOS_DEBUG, "Done jedec reset\n"); @@ -737,7 +678,7 @@ int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, normalize_training(ctrl); } - set_4008c(ctrl); + set_read_write_timings(ctrl); write_controller_mr(ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 9e07e2ebaf..5b4b46c583 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -44,8 +44,8 @@ */ #if CONFIG(USE_OPTION_TABLE) #include "option_table.h" -#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) -#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) +#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) +#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) #else #define CMOS_OFFSET_MRC_SEED 152 @@ -60,8 +60,7 @@ void save_mrc_data(struct pei_data *pei_data) u16 c1, c2, checksum; /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - pei_data->mrc_output, + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, pei_data->mrc_output_len); /* Save the MRC seed values to CMOS */ @@ -74,14 +73,12 @@ void save_mrc_data(struct pei_data *pei_data) pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); /* Save a simple checksum of the seed values */ - c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, - sizeof(u32)); - c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, - sizeof(u32)); + c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); + c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); - cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); + cmos_write((checksum >> 0) & 0xff, CMOS_OFFSET_MRC_SEED_CHK); + cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK + 1); } static void prepare_mrc_cache(struct pei_data *pei_data) @@ -89,7 +86,7 @@ static void prepare_mrc_cache(struct pei_data *pei_data) struct region_device rdev; u16 c1, c2, checksum, seed_checksum; - // preset just in case there is an error + /* Preset just in case there is an error */ pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; @@ -103,14 +100,12 @@ static void prepare_mrc_cache(struct pei_data *pei_data) pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); /* Compute seed checksum and compare */ - c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, - sizeof(u32)); - c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, - sizeof(u32)); + c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); + c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); - seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; + seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); + seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; if (checksum != seed_checksum) { printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); @@ -119,68 +114,64 @@ static void prepare_mrc_cache(struct pei_data *pei_data) return; } - if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - &rdev)) { - /* error message printed in find_current_mrc_cache */ + if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) { + /* Error message printed in find_current_mrc_cache */ return; } pei_data->mrc_input = rdev_mmap_full(&rdev); pei_data->mrc_input_len = region_device_sz(&rdev); - printk(BIOS_DEBUG, "%s: at %p, size %x\n", - __func__, pei_data->mrc_input, pei_data->mrc_input_len); + printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input, + pei_data->mrc_input_len); } static const char *ecc_decoder[] = { "inactive", "active on IO", "disabled on IO", - "active" + "active", }; -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ +#define ON_OFF(val) (((val) & 1) ? "on" : "off") + +/* Print the memory controller configuration as read from the memory controller registers. */ static void report_memory_config(void) { u32 addr_decoder_common, addr_decode_ch[2]; int i; addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, + (addr_decoder_common >> 0) & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); + printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 0) & 0xff) * 256, ((ch_conf >> 19) & 1) ? 16 : 8, ((ch_conf >> 17) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? "" : ", selected"); printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 8) & 0xff) * 256, ((ch_conf >> 20) & 1) ? 16 : 8, ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); } } +#undef ON_OFF /** * Find PEI executable in coreboot filesystem and execute it. @@ -190,7 +181,7 @@ static void report_memory_config(void) void sdram_initialize(struct pei_data *pei_data) { struct sys_info sysinfo; - int (*entry) (struct pei_data *pei_data) __attribute__((regparm(1))); + int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); /* Wait for ME to be ready */ intel_early_me_init(); @@ -245,18 +236,17 @@ void sdram_initialize(struct pei_data *pei_data) if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); - /* For reference print the System Agent version - * after executing the UEFI PEI stage. - */ + /* For reference, print the System Agent version after executing the UEFI PEI stage */ u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - version >> 24, (version >> 16) & 0xff, - (version >> 8) & 0xff, version & 0xff); + (version >> 24) & 0xff, (version >> 16) & 0xff, + (version >> 8) & 0xff, (version >> 0) & 0xff); - /* Send ME init done for SandyBridge here. This is done - * inside the SystemAgent binary on IvyBridge. */ - if (BASE_REV_SNB == - (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) + /* + * Send ME init done for SandyBridge here. + * This is done inside the SystemAgent binary on IvyBridge. + */ + if (BASE_REV_SNB == (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); else intel_early_me_status(); @@ -264,31 +254,30 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } -/* These are the location and structure of MRC_VAR data in CAR. - The CAR region looks like this: - +------------------+ -> DCACHE_RAM_BASE - | | - | | - | COREBOOT STACK | - | | - | | - +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE - | | - | MRC HEAP | - | size = 0x5000 | - | | - +------------------+ - | | - | MRC VAR | - | size = 0x4000 | - | | - +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE - + DCACHE_RAM_MRC_VAR_SIZE - +/* + * These are the location and structure of MRC_VAR data in CAR. + * The CAR region looks like this: + * +------------------+ -> DCACHE_RAM_BASE + * | | + * | | + * | COREBOOT STACK | + * | | + * | | + * +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE + * | | + * | MRC HEAP | + * | size = 0x5000 | + * | | + * +------------------+ + * | | + * | MRC VAR | + * | size = 0x4000 | + * | | + * +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE + * + DCACHE_RAM_MRC_VAR_SIZE */ -#define DCACHE_RAM_MRC_VAR_BASE \ - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + \ - CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) +#define DCACHE_RAM_MRC_VAR_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + + CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) struct mrc_var_data { u32 acpi_timer_flag; @@ -300,14 +289,14 @@ struct mrc_var_data { static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; pei_data->hpet_address = CONFIG_HPET_ADDRESS; - pei_data->thermalbase = 0xfed08000; - pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; - pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { const struct device *dev = pcidev_on_root(1, 0); @@ -321,12 +310,12 @@ static void southbridge_fill_pei_data(struct pei_data *pei_data) { const struct device *dev = pcidev_on_root(0x19, 0); - pei_data->smbusbar = SMBUS_IO_BASE; - pei_data->wdbbar = 0x4000000; - pei_data->wdbsize = 0x1000; - pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; - pei_data->pmbase = DEFAULT_PMBASE; - pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x04000000; + pei_data->wdbsize = 0x1000; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; pei_data->gbe_enable = dev && dev->enabled; } @@ -360,13 +349,10 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data) } - memcpy(pei_data->spd_addresses, cfg->spd_addresses, - sizeof(pei_data->spd_addresses)); + memcpy(pei_data->spd_addresses, cfg->spd_addresses, sizeof(pei_data->spd_addresses)); + memcpy(pei_data->ts_addresses, cfg->ts_addresses, sizeof(pei_data->ts_addresses)); - memcpy(pei_data->ts_addresses, cfg->ts_addresses, - sizeof(pei_data->ts_addresses)); - - pei_data->ec_present = cfg->ec_present; + pei_data->ec_present = cfg->ec_present; pei_data->ddr3lv_support = cfg->ddr3lv_support; pei_data->nmode = cfg->nmode; @@ -375,15 +361,15 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data) memcpy(pei_data->usb_port_config, cfg->usb_port_config, sizeof(pei_data->usb_port_config)); - pei_data->usb3.mode = cfg->usb3.mode; + pei_data->usb3.mode = cfg->usb3.mode; pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; - pei_data->usb3.preboot_support = cfg->usb3.preboot_support; - pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; + pei_data->usb3.preboot_support = cfg->usb3.preboot_support; + pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; } static void disable_p2p(void) { - /* Disable PCI-to-PCI bridge early to prevent probing by MRC. */ + /* Disable PCI-to-PCI bridge early to prevent probing by MRC */ const struct device *const p2p = pcidev_on_root(0x1e, 0); if (p2p && p2p->enabled) return; @@ -393,7 +379,6 @@ static void disable_p2p(void) void perform_raminit(int s3resume) { - int cbmem_was_initted; struct pei_data pei_data; struct mrc_var_data *mrc_var; @@ -425,6 +410,7 @@ void perform_raminit(int s3resume) if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { memcpy(pei_data.spd_data[0], pei_data.spd_data[i], sizeof(pei_data.spd_data[0])); + } else if (pei_data.spd_data[i][0] && pei_data.spd_data[0][0]) { if (memcmp(pei_data.spd_data[i], pei_data.spd_data[0], sizeof(pei_data.spd_data[0])) != 0) @@ -438,18 +424,18 @@ void perform_raminit(int s3resume) timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); + /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; - /* Sanity check mrc_var location by verifying a known field. */ if (mrc_var->tx_byte == (uintptr_t)pei_data.tx_byte) { printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", - mrc_var->pool_base, - mrc_var->pool_base + mrc_var->pool_used); + mrc_var->pool_base, mrc_var->pool_base + mrc_var->pool_used); + } else { printk(BIOS_ERR, "Could not parse MRC_VAR data\n"); - hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); + hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var) / sizeof(u32)); } - cbmem_was_initted = !cbmem_recovery(s3resume); + const int cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index ecf13cf1f8..60a5665ba9 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -18,8 +18,8 @@ #include "sandybridge.h" #include -/* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */ +/* The order is: ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB */ void read_spd(spd_raw_data *spd, u8 addr, bool id_only); void mainboard_get_spd(spd_raw_data *spd, bool id_only); -#endif /* RAMINIT_H */ +#endif /* RAMINIT_NATIVE_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index b5169e7525..3b68c22b87 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -18,116 +18,105 @@ #include "raminit_native.h" #include "raminit_common.h" -/* Frequency multiplier. */ +/* Frequency multiplier */ static u32 get_FRQ(u32 tCK) { - u32 FRQ; - FRQ = 256000 / (tCK * BASEFREQ); + const u32 FRQ = 256000 / (tCK * BASEFREQ); + if (FRQ > 8) return 8; if (FRQ < 3) return 3; + return FRQ; } +/* Get REFI based on MC frequency */ static u32 get_REFI(u32 tCK) { - /* Get REFI based on MCU frequency using the following rule: - * _________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | - */ - static const u32 frq_refi_map[] = - { 3120, 4160, 5200, 6240, 7280, 8320 }; + static const u32 frq_refi_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 3120, 4160, 5200, 6240, 7280, 8320, + }; return frq_refi_map[get_FRQ(tCK) - 3]; } +/* Get XSOffset based on MC frequency */ static u8 get_XSOffset(u32 tCK) { - /* Get XSOffset based on MCU frequency using the following rule: - * _________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | - */ - static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11 }; + static const u8 frq_xs_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 4, 6, 7, 8, 10, 11, + }; return frq_xs_map[get_FRQ(tCK) - 3]; } +/* Get MOD based on MC frequency */ static u8 get_MOD(u32 tCK) { - /* Get MOD based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | - */ - static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16 }; + static const u8 frq_mod_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 12, 12, 12, 12, 15, 16, + }; return frq_mod_map[get_FRQ(tCK) - 3]; } +/* Get Write Leveling Output delay based on MC frequency */ static u8 get_WLO(u32 tCK) { - /* Get WLO based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | - */ - static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8 }; + static const u8 frq_wlo_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 4, 5, 6, 6, 8, 8, + }; return frq_wlo_map[get_FRQ(tCK) - 3]; } +/* Get CKE based on MC frequency */ static u8 get_CKE(u32 tCK) { - /* Get CKE based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * CKE : | 3 | 3 | 4 | 4 | 5 | 6 | - */ - static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6 }; + static const u8 frq_cke_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 3, 3, 4, 4, 5, 6, + }; return frq_cke_map[get_FRQ(tCK) - 3]; } +/* Get XPDLL based on MC frequency */ static u8 get_XPDLL(u32 tCK) { - /* Get XPDLL based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | - */ - static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26 }; + static const u8 frq_xpdll_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 10, 13, 16, 20, 23, 26, + }; return frq_xpdll_map[get_FRQ(tCK) - 3]; } +/* Get XP based on MC frequency */ static u8 get_XP(u32 tCK) { - /* Get XP based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XP : | 3 | 4 | 4 | 5 | 6 | 7 | - */ - static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 }; + static const u8 frq_xp_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 3, 4, 4, 5, 6, 7, + }; return frq_xp_map[get_FRQ(tCK) - 3]; } +/* Get AONPD based on MC frequency */ static u8 get_AONPD(u32 tCK) { - /* Get AONPD based on MCU frequency using the following rule: - * ________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | - */ - static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10 }; + static const u8 frq_aonpd_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 4, 5, 6, 8, 8, 10, + }; return frq_aonpd_map[get_FRQ(tCK) - 3]; } +/* Get COMP2 based on MC frequency */ static u32 get_COMP2(u32 tCK) { - /* Get COMP2 based on MCU frequency using the following rule: - * ___________________________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * COMP : | D6BEDCC | CE7C34C | CA57A4C | C6369CC | C42514C | C21410C | - */ - static const u32 frq_comp2_map[] = { 0xD6BEDCC, 0xCE7C34C, 0xCA57A4C, - 0xC6369CC, 0xC42514C, 0xC21410C + static const u32 frq_comp2_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 0x0D6BEDCC, 0x0CE7C34C, 0x0CA57A4C, 0x0C6369CC, 0x0C42514C, 0x0C21410C, }; return frq_comp2_map[get_FRQ(tCK) - 3]; } @@ -154,21 +143,23 @@ static void snb_normalize_tclk(u32 *tclk) static void find_cas_tck(ramctr_timing *ctrl) { u8 val; - u32 val32; /* Find CAS latency */ while (1) { - /* Normalising tCK before computing clock could potentially - * results in lower selected CAS, which is desired. + /* + * Normalising tCK before computing clock could potentially + * result in a lower selected CAS, which is desired. */ snb_normalize_tclk(&(ctrl->tCK)); if (!(ctrl->tCK)) die("Couldn't find compatible clock / CAS settings\n"); + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); for (; val <= MAX_CAS; val++) if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) break; + if (val == (MAX_CAS + 1)) { ctrl->tCK++; continue; @@ -178,18 +169,17 @@ static void find_cas_tck(ramctr_timing *ctrl) } } - val32 = NS2MHZ_DIV256 / ctrl->tCK; - printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); - + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; } static void dram_timing(ramctr_timing *ctrl) { - /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure - * we cap it if we have faster DIMMs. - * Then, align it to the closest JEDEC standard frequency */ + /* + * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). + * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. + */ if (ctrl->tCK == TCK_1066MHZ) { ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; @@ -198,6 +188,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_933MHZ) { ctrl->edge_offset[0] = 14; ctrl->edge_offset[1] = 6; @@ -206,6 +197,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_800MHZ) { ctrl->edge_offset[0] = 13; ctrl->edge_offset[1] = 5; @@ -214,6 +206,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_666MHZ) { ctrl->edge_offset[0] = 10; ctrl->edge_offset[1] = 4; @@ -222,6 +215,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 4; ctrl->timC_offset[2] = 4; ctrl->pi_coding_threshold = 16; + } else if (ctrl->tCK == TCK_533MHZ) { ctrl->edge_offset[0] = 8; ctrl->edge_offset[1] = 3; @@ -230,6 +224,7 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->timC_offset[1] = 3; ctrl->timC_offset[2] = 3; ctrl->pi_coding_threshold = 17; + } else { ctrl->tCK = TCK_400MHZ; ctrl->edge_offset[0] = 6; @@ -251,13 +246,14 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); else ctrl->CWL = get_CWL(ctrl->tCK); + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ @@ -265,7 +261,7 @@ static void dram_timing(ramctr_timing *ctrl) printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ @@ -285,25 +281,25 @@ static void dram_timing(ramctr_timing *ctrl) printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); /* FIXME: Why the -1 ? */ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - ctrl->tREFI = get_REFI(ctrl->tCK); - ctrl->tMOD = get_MOD(ctrl->tCK); + ctrl->tREFI = get_REFI(ctrl->tCK); + ctrl->tMOD = get_MOD(ctrl->tCK); ctrl->tXSOffset = get_XSOffset(ctrl->tCK); - ctrl->tWLO = get_WLO(ctrl->tCK); - ctrl->tCKE = get_CKE(ctrl->tCK); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK); - ctrl->tXP = get_XP(ctrl->tCK); - ctrl->tAONPD = get_AONPD(ctrl->tCK); + ctrl->tWLO = get_WLO(ctrl->tCK); + ctrl->tCKE = get_CKE(ctrl->tCK); + ctrl->tXPDLL = get_XPDLL(ctrl->tCK); + ctrl->tXP = get_XP(ctrl->tCK); + ctrl->tAONPD = get_AONPD(ctrl->tCK); } static void dram_freq(ramctr_timing *ctrl) { - if (ctrl->tCK > TCK_400MHZ) { - printk(BIOS_ERR, "DRAM frequency is under lowest supported " - "frequency (400 MHz). Increasing to 400 MHz as last resort"); + printk(BIOS_ERR, + "DRAM frequency is under lowest supported frequency (400 MHz). " + "Increasing to 400 MHz as last resort"); ctrl->tCK = TCK_400MHZ; } @@ -311,13 +307,15 @@ static void dram_freq(ramctr_timing *ctrl) u8 val2; u32 reg1 = 0; + /* Step 1 - Set target PCU frequency */ find_cas_tck(ctrl); - /* Frequency multiplier. */ - u32 FRQ = get_FRQ(ctrl->tCK); + /* Frequency multiplier */ + const u32 FRQ = get_FRQ(ctrl->tCK); - /* The PLL will never lock if the required frequency is - * already set. Exit early to prevent a system hang. + /* + * The PLL will never lock if the required frequency is already set. + * Exit early to prevent a system hang. */ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; @@ -326,7 +324,7 @@ static void dram_freq(ramctr_timing *ctrl) /* Step 1 - Select frequency in the MCU */ reg1 = FRQ; - reg1 |= 0x80000000; // set running bit + reg1 |= 0x80000000; /* set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; int i=0; printk(BIOS_DEBUG, "PLL busy... "); @@ -352,61 +350,57 @@ static void dram_freq(ramctr_timing *ctrl) static void dram_ioregs(ramctr_timing *ctrl) { - u32 reg, comp2; + u32 reg; int channel; - // IO clock + /* IO clock */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO command + /* IO command */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO control + /* IO control */ FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - // Rcomp + /* Perform RCOMP */ printram("RCOMP..."); - reg = 0; - while (reg == 0) { - reg = MCHBAR32(RCOMP_TIMER) & 0x10000; - } + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; + printram("done\n"); - // Set comp2 - comp2 = get_COMP2(ctrl->tCK); - MCHBAR32(CRCOMPOFST2) = comp2; + /* Set COMP2 */ + MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK); printram("COMP2 done\n"); - // Set comp1 + /* Set COMP1 */ FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(CRCOMPOFST1_ch(channel)); //ch0 - reg = (reg & ~0xe00) | (1 << 9); //odt - reg = (reg & ~0xe00000) | (1 << 21); //clk drive up - reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up + reg = MCHBAR32(CRCOMPOFST1_ch(channel)); + reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ + reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ + reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; } printram("COMP1 done\n"); printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(M_COMP) |= 0x100; + MCHBAR32(M_COMP) |= (1 << 8); udelay(20); printram("done\n"); } -int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size) +int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) { int err; - printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", - fast_boot); + printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", fast_boot); if (!fast_boot) { /* Find fastest common supported parameters */ @@ -415,7 +409,7 @@ int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, dram_dimm_mapping(ctrl); } - /* Set MCU frequency */ + /* Set MC frequency */ dram_freq(ctrl); if (!fast_boot) { @@ -424,7 +418,7 @@ int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, } /* Set version register */ - MCHBAR32(MRC_REVISION) = 0xC04EB002; + MCHBAR32(MRC_REVISION) = 0xc04eb002; /* Enable crossover */ dram_xover(ctrl); @@ -438,11 +432,11 @@ int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, /* Set scheduler chicken bits */ MCHBAR32(SCHED_CBIT) = 0x10100005; - /* Set CPU specific register */ - set_4f8c(); + /* Set up watermarks and starvation counter */ + set_wmm_behavior(); /* Clear IO reset bit */ - MCHBAR32(MC_INIT_STATE_G) &= ~0x20; + MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); /* Set MAD-DIMM registers */ dram_dimm_set_mapping(ctrl); @@ -464,7 +458,7 @@ int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, if (fast_boot) { restore_timings(ctrl); } else { - /* Do jedec ddr3 reset sequence */ + /* Do JEDEC DDR3 reset sequence */ dram_jedecreset(ctrl); printk(BIOS_DEBUG, "Done jedec reset\n"); @@ -508,7 +502,7 @@ int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, normalize_training(ctrl); } - set_4008c(ctrl); + set_read_write_timings(ctrl); write_controller_mr(ctrl); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 81049e55c4..ec44ee2c8a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -39,20 +39,18 @@ static void early_pch_reset_pmcon(void) { u8 reg8; - // reset rtc power status + /* Reset RTC power status */ reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); reg8 &= ~(1 << 2); pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } -/* Platform has no romstage entry point under mainboard directory, - * so this one is named with prefix mainboard. - */ +/* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { int s3resume = 0; - if (MCHBAR16(SSKPD) == 0xCAFE) + if (MCHBAR16(SSKPD_HI) == 0xCAFE) system_reset(); enable_lapic(); @@ -60,14 +58,12 @@ void mainboard_romstage_entry(void) /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); - /* USB is initialized in MRC if MRC is used. */ + /* When using MRC, USB is initialized by MRC */ if (CONFIG(USE_NATIVE_RAMINIT)) { early_usb_init(mainboard_usb_ports); } - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* Perform some early chipset init needed before RAM initialization can work */ systemagent_early_init(); printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 0bbb6fc6d2..07d790430f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -43,8 +43,8 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE ((u8 *)0xfed1c000) -#define IOMMU_BASE1 0xfed90000ULL -#define IOMMU_BASE2 0xfed91000ULL +#define GFXVT_BASE 0xfed90000ULL +#define VTVC0_BASE 0xfed91000ULL /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ @@ -58,31 +58,32 @@ enum platform_type { /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define GGC 0x50 /* GMCH Graphics Control */ - -#define DEVEN 0x54 /* Device Enable */ +#define GGC 0x50 /* GMCH Graphics Control */ +#define DEVEN 0x54 /* Device Enable */ #define DEVEN_D7EN (1 << 14) #define DEVEN_PEG60 (1 << 13) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_IGD (1 << 4) -#define DEVEN_PEG10 (1 << 3) -#define DEVEN_PEG11 (1 << 2) -#define DEVEN_PEG12 (1 << 1) -#define DEVEN_HOST (1 << 0) +#define DEVEN_D4EN (1 << 7) +#define DEVEN_IGD (1 << 4) +#define DEVEN_PEG10 (1 << 3) +#define DEVEN_PEG11 (1 << 2) +#define DEVEN_PEG12 (1 << 1) +#define DEVEN_HOST (1 << 0) #define PAVPC 0x58 /* Protected Audio Video Path Control */ #define DPR 0x5c /* DMA Protected Range */ +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + #define MESEG_BASE 0x70 #define MESEG_MASK 0x78 -#define MELCK (1 << 10) /* ME Range Lock */ -#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ +#define MELCK (1 << 10) /* ME Range Lock */ +#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ #define PAM0 0x80 #define PAM1 0x81 @@ -109,6 +110,13 @@ enum platform_type { #define SKPAD 0xdc /* Scratchpad Data */ +#define DIDOR 0xf3 /* Device ID override, for debug and samples only */ + + +/* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ + +#define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -118,246 +126,27 @@ enum platform_type { * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -/* Indexed register helper macros */ -#define Gz(r, z) ((r) + ((z) << 8)) -#define Ly(r, y) ((r) + ((y) << 2)) -#define Cx(r, x) ((r) + ((x) << 10)) -#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) -#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) - -/* byte lane training register base addresses */ -#define LANEBASE_B0 0x0000 -#define LANEBASE_B1 0x0200 -#define LANEBASE_B2 0x0400 -#define LANEBASE_B3 0x0600 -#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ -#define LANEBASE_B4 0x1000 -#define LANEBASE_B5 0x1200 -#define LANEBASE_B6 0x1400 -#define LANEBASE_B7 0x1600 - -/* byte lane register offsets */ -#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ -#define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ -#define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ -#define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ -#define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ - -/* Register definitions */ -#define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ -#define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ -#define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch) /* PI coding for DDR CLK pins */ -#define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch) /* Logic delay of 1 QCLK in CLK slice */ -#define GDDLLFUSE_ch(ch) Gz(0x0c20, ch) /* Used for fuse download to the DLLs */ -#define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch) /* Debug MUX control */ - -#define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch) /* Debug MUX control */ - -#define CRCOMPOFST1_ch(ch) Gz(0x1810, ch) /* DQ, CTL and CLK Offset values */ - -#define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch) /* Data training mode control */ -#define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch) /* Training results according to PI */ -#define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch) - -#define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch) /* Indicates which rank is populated */ -#define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch) /* COMP values register */ -#define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch) /* COMP values register */ -#define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch) /* Command and control PI coding */ - -#define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ -#define GDCRDATACOMP 0x340c /* COMP values register */ - -#define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ - -/* MC per-channel registers */ -#define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ -#define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ -#define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ -#define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ -#define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ -#define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ -#define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ -#define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch) /* IO Latency Configuration */ -#define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch) /* Scrambling seed 1 */ -#define SCRAMBLING_SEED_2_LOW_ch(ch) Cx(0x4038, ch) /* Scrambling seed 2 low */ -#define SCRAMBLING_SEED_2_HIGH_ch(ch) Cx(0x403c, ch) /* Scrambling seed 2 high */ - -/* IOSAV Bytelane Bit-wise error */ -#define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y) - -/* IOSAV Bytelane Bit-wise compare mask */ -#define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y) - -/* - * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. - * Different counters for transactions that are issued on the ring agents (core or GT) and - * transactions issued in the SA. - */ -#define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch) -#define SC_PCIT_ch(ch) Cx(0x40ac, ch) /* Page-close idle timer setup - 8 bits */ -#define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch) /* Power-down (CKE-off) operation config */ -#define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch) /* ECC error injection count */ -#define ECC_DFT_ch(ch) Cx(0x40b8, ch) /* ECC DFT features (ECC4ANA, error inject) */ -#define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch) /* Extra WR delay to overcome WR-flyby issue */ - -#define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ - -/* IOSAV sub-sequence control registers */ -#define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ -#define IOSAV_n_ADDR_UPD_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ -#define IOSAV_n_SP_CMD_CTL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ -#define IOSAV_n_SUBSEQ_CTL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ -#define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ - -#define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ -#define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ -#define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch) /* Data control in IOSAV mode */ -#define IOSAV_STATUS_ch(ch) Cx(0x428c, ch) /* State of the IOSAV sequence machine */ -#define TC_ZQCAL_ch(ch) Cx(0x4290, ch) /* ZQCAL control register */ -#define TC_RFP_ch(ch) Cx(0x4294, ch) /* Refresh Parameters */ -#define TC_RFTP_ch(ch) Cx(0x4298, ch) /* Refresh Timing Parameters */ -#define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch) /* MR2 shadow - copy of DDR configuration */ -#define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch) /* IOSAV mode control */ -#define TC_SRFTP_ch(ch) Cx(0x42a4, ch) /* Self-refresh timing parameters */ -#define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch) /* Data vector count of the first error */ -#define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch) /* IOSAV data check masking */ - -#define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y) /* Per-byte 16-bit error count */ -#define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch) /* Global 16-bit error count */ - -#define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch) /* Thermal mode configuration */ -#define PM_CMD_PWR_ch(ch) Cx(0x4384, ch) /* Power contribution of commands */ -#define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch) /* Bandwidth throttling on overtemp */ -#define SC_WDBWM_ch(ch) Cx(0x438c, ch) /* Watermarks and starvation counter */ - -/* MC Channel Broadcast registers */ -#define TC_DBP 0x4c00 /* Timings: BIN */ -#define TC_RAP 0x4c04 /* Timings: Regular access */ -#define TC_RWP 0x4c08 /* Timings: Read / Write */ -#define TC_OTHP 0x4c0c /* Timings: Other parameters */ -#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ -#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ -#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ -#define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ -#define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ -#define SCRAMBLING_SEED_2_LOW 0x4c38 /* Scrambling seed 2 low */ -#define SCRAMBLING_SEED_2_HIGH 0x4c3c /* Scrambling seed 2 high */ - -#define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ -#define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ - -/* - * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. - * Different counters for transactions that are issued on the ring agents (core or GT) and - * transactions issued in the SA. - */ -#define SC_PR_CNT_CONFIG 0x4ca8 -#define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ -#define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ -#define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ -#define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ -#define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ - -/* Opportunistic reads configuration during write-major-mode (WMM) */ -#define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ - -#define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ - -#define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */ -#define IOSAV_n_ADDR_UPD(n) Ly(0x4e10, n) /* Address update after command execution */ -#define IOSAV_n_SP_CMD_CTL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */ -#define IOSAV_n_SUBSEQ_CTL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */ -#define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */ - -#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ -#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ -#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ -#define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ -#define TC_ZQCAL 0x4e90 /* ZQCAL control register */ -#define TC_RFP 0x4e94 /* Refresh Parameters */ -#define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ -#define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ -#define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ -#define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ - -/* - * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this - * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. - */ -#define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ - -#define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ -#define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ - -#define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ -#define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ - -#define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ -#define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ -#define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ -#define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ - -#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ -#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ -#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ -#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on SNB) */ -#define MAD_ZR 0x5014 /* Address Decode Zones */ -#define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ -#define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ - -#define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ - -#define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ -#define MRC_REVISION 0x5034 /* MRC Revision */ -#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ -#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ - -#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ - -#define VTD1_BASE 0x5400 /* Base address for IGD */ -#define VTD2_BASE 0x5410 /* Base address for PEG, USB, SATA, etc. */ -#define PAIR_CTL 0x5418 /* Power Aware Interrupt Routing Control */ - -/* PAVP control register, undocumented. Different from PAVPC on PCI config space. */ -#define MMIO_PAVP_CTL 0x5500 /* Bit 0 locks PAVP settings */ - -#define MEM_TRML_ESTIMATION_CONFIG 0x5880 -#define MEM_TRML_THRESHOLDS_CONFIG 0x5888 -#define MEM_TRML_INTERRUPT 0x58a8 - -#define MC_TURBO_PL1 0x59a0 /* Turbo Power Limit 1 parameters */ -#define MC_TURBO_PL2 0x59a4 /* Turbo Power Limit 2 parameters */ - -#define SSKPD_OK 0x5d10 /* 64-bit scratchpad register */ -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ - -/* PCODE will sample SAPM-related registers at the end of Phase 4. */ -#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ -#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ -#define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ -#define M_COMP 0x5f08 /* Memory COMP control */ -#define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ - -/* WARNING: Only applies to Sandy Bridge! */ -#define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ - -/** WARNING: Only applies to Ivy Bridge! */ -#define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ -#define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ +/* As there are many registers, define them on a separate file */ +#include "mchbar_regs.h" /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) @@ -388,7 +177,7 @@ enum platform_type { * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) @@ -436,7 +225,6 @@ enum platform_type { #ifndef __ASSEMBLER__ void intel_sandybridge_finalize_smm(void); - int bridge_silicon_revision(void); void systemagent_early_init(void); void sandybridge_init_iommu(void); @@ -444,8 +232,7 @@ void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void); -/* mainboard_early_init: Optional mainboard callback run after console init - but before raminit. */ +/* mainboard_early_init: Optional callback, run after console init but before raminit. */ void mainboard_early_init(int s3resume); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); @@ -454,7 +241,8 @@ enum platform_type get_platform_type(void); #include struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, + struct acpi_rsdp *rsdp); #endif #endif From 505fe3d73c37e21e378b58cee0c53b835cd5f88d Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 4 Dec 2019 10:26:08 -0700 Subject: [PATCH 0517/1463] soc/amd/picasso: Add CPUID of newer device Add a new device (Family 17h Models 20h-2Fh) to the cpu driver. Change-Id: Id792533e60813b7509bacd6806f78cd8bba56e37 Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/1950713 Reviewed-by: Martin Roth Tested-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/39617 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/amd/picasso/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 403b15b894..c7e847d314 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -129,6 +129,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x810f80 }, { X86_VENDOR_AMD, 0x810f81 }, + { X86_VENDOR_AMD, 0x820f01 }, { 0, 0 }, }; From 9d49598cd6f323d0119d905f9917f526e0c2920f Mon Sep 17 00:00:00 2001 From: Eric Peers Date: Tue, 17 Dec 2019 10:02:15 -0700 Subject: [PATCH 0518/1463] assert.h: add assertions with descriptive failures BUG=None TEST=tested in following patches on Trembyle board Change-Id: Ib30ccd41759e5a2a61d3182cc08ed5eb762eca98 Signed-off-by: Eric Peers Reviewed-on: https://chromium-review.googlesource.com/1971443 Tested-by: Martin Roth Reviewed-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/39620 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Angel Pons Reviewed-by: Raul Rangel Reviewed-by: Paul Menzel --- src/include/assert.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/include/assert.h b/src/include/assert.h index 8f5af1f255..990cee11b5 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -33,6 +33,17 @@ hlt(); \ } \ } + +#define ASSERT_MSG(x, msg) { \ + if (!(x)) { \ + printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ + ", line %d\n", __FILE__, __LINE__); \ + printk(BIOS_EMERG, "%s", msg); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ +} + #define BUG() { \ printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\ ", line %d\n", __FILE__, __LINE__); \ From 5baadba532aec78d76d2ba1efea825b5f9b75efc Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Thu, 20 Feb 2020 14:35:51 -0700 Subject: [PATCH 0519/1463] util/bincfg: Add DDR4 SPD spec MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Additionally provide a simple script for decoding spd hex files using bincfg. BUG=b:148561711 TEST=Decoded spd files in zork BRANCH=None Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499 Signed-off-by: Rob Barnes Reviewed-on: https://chromium-review.googlesource.com/2067697 Reviewed-by: Martin Roth Reviewed-by: Paul Fagerburg Reviewed-on: https://review.coreboot.org/c/coreboot/+/39621 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- util/bincfg/ddr4_registered_spd_512.spec | 362 +++++++++++++++++++++++ util/bincfg/ddr4_unbuffered_spd_512.spec | 335 +++++++++++++++++++++ util/scripts/decode_spd.sh | 76 +++++ util/scripts/description.md | 2 + 4 files changed, 775 insertions(+) create mode 100644 util/bincfg/ddr4_registered_spd_512.spec create mode 100644 util/bincfg/ddr4_unbuffered_spd_512.spec create mode 100755 util/scripts/decode_spd.sh diff --git a/util/bincfg/ddr4_registered_spd_512.spec b/util/bincfg/ddr4_registered_spd_512.spec new file mode 100644 index 0000000000..126091e8f0 --- /dev/null +++ b/util/bincfg/ddr4_registered_spd_512.spec @@ -0,0 +1,362 @@ +# 4_01_02_AnnexL-R25_SPD_for_DDR4_SDRAM_Release_3_Sep2015.pdf +# +# JEDEC Standard No. 21-C +# Page 4.1.2.12.3 – 1 +# Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules +# DDR4 SPD Document Release 3 +# UDIMM Revision 1.1 +# RDIMM Revision 1.1 +# LRDIMM Revision 1.1 +# NVDIMM Revision 1.0 + +{ + # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / + # CRC Coverage + "SPD_Bytes_Used" : 4, + "SPD_Bytes_Total" : 3, + "CRC_Coverage" : 1, + + # Byte 1: SPD Revision + "SPD_Revision" : 8, + + # Byte 2: Key Byte / DRAM Device Type + "DRAM_Device_Type" : 8, + + # Byte 3: Key Byte / Module Type + "Base_Module_Type" : 4, + "Hybrid_Media" : 3, + "Is_Hybrid" : 1, + + # Byte 4: SDRAM Density and Banks + "SDRAM_Capacity" : 4, + "Bank_Address_Bits" : 2, + "Bank_Group_Bits" : 2, + + # Byte 5: SDRAM Addressing + "Column_Address_Bits" : 3, + "Row_Address_Bits" : 3, + "Byte_5_reserved" : 2, + + # Byte 6: SDRAM Package Type + "Signal_Loading" : 2, + "Byte_6_reserved" : 2, + "Die_Count" : 3, + "SDRAM_Package_Type" : 1, + + # Byte 7: SDRAM Optional Features + "Maximum_Activate_Count" : 4, + "Maximum_Activate_Window" : 2, + "Byte_7_reserved" : 2, + + # Byte 8: SDRAM Thermal and Refresh Options + "Byte_8_reserved" : 8, + + # Byte 9: Other SDRAM Optional Features + "Byte_9_reserved" : 5, + "Soft_PPR" : 1, + "Post_Package_Repair" : 2, + + # Byte 10: Secondary SDRAM Package Type + "Secondary_Signal_Loading" : 2, + "Secondary_DRAM_Densityt_Ratio" : 2, + "Secondary_Die_Count" : 3, + "Secondary_SDRAM_Package_Type" : 1, + + # Byte 11: Module Nominal Voltage, VDD + "DRAM_VDD_1_2_V" : 2, + "Byte_11_reserved" : 6, + + # Byte 12: Module Organization + "SDRAM_Device_Width" : 3, + "Number_of_Package_Ranks_per_DIMM" : 3, + "Rank_Mix" : 1, + "Byte_12_reserved" : 1, + + # Byte 13: Module Memory Bus Width + "Primary_bus_width_in_bits" : 3, + "Bus_width_extension_in_bits" : 2, + "Byte_13_reserved" : 3, + + # Byte 14: Module Thermal Sensor + "Byte_14_reserved" : 7, + "Thermal_Sensor" : 1, + + # Byte 15: Extended Module Type + "Extended_Base_Module_Type" : 4, + "Byte_15_reserved" : 4, + + # Byte 16: Reserved + "Byte_16_reserved" : 8, + + # Byte 17: Timebases + "Fine_Timebase" : 2, + "Medium_Timebase" : 2, + "Byte_17_reserved" : 4, + + # Byte 18: SDRAM Minimum Cycle Time (tCKAVGmin) + "tCKAVGmin" : 8, + + # Byte 19: SDRAM Maximum Cycle Time (tCKAVGmax) + "tCKAVGmax" : 8, + + # Bytes 20 - 23: CAS Latencies Supported + "CL_7_Supported" : 1, + "CL_8_Supported" : 1, + "CL_9_Supported" : 1, + "CL_10_Supported" : 1, + "CL_11_Supported" : 1, + "CL_12_Supported" : 1, + "CL_13_Supported" : 1, + "CL_14_Supported" : 1, + + "CL_15_Supported" : 1, + "CL_16_Supported" : 1, + "CL_17_Supported" : 1, + "CL_18_Supported" : 1, + "CL_19_Supported" : 1, + "CL_20_Supported" : 1, + "CL_21_Supported" : 1, + "CL_22_Supported" : 1, + + "CL_23_Supported" : 1, + "CL_24_Supported" : 1, + "CL_25_Supported" : 1, + "CL_26_Supported" : 1, + "CL_27_Supported" : 1, + "CL_28_Supported" : 1, + "CL_29_Supported" : 1, + "CL_30_Supported" : 1, + + "CL_31_Supported" : 1, + "CL_32_Supported" : 1, + "CL_33_Supported" : 1, + "CL_34_Supported" : 1, + "CL_35_Supported" : 1, + "CL_36_Supported" : 1, + "Byte_23_reserved" : 1, + "CL_range" : 1, + + # Byte 24: Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 25: Minimum RAS to CAS Delay Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 26: Minimum Row Precharge Delay Time (tRPmin) + "tRPmin" : 8, + + # Bytes 27 - 29: Minimum Active to Precharge Delay Time (tRASmin) + # / Minimum Active to Active/Refresh Delay Time + # (tRCmin) + "tRASmin_MSN" : 4, + "tRCmin_MSN" : 4, + "tRASmin_LSB" : 8, + "tRCmin_LSB" : 8, + + # Bytes 30 - 31: Minimum Refresh Recovery Delay Time (tRFC1min) + "tRFC1min_LSB" : 8, + "tRFC1min_MSB" : 8, + + # Bytes 32 - 33: Minimum Refresh Recovery Delay Time (tRFC2min) + "tRFC2min_LSB" : 8, + "tRFC2min_MSB" : 8, + + # Bytes 34 - 35: Minimum Refresh Recovery Delay Time (tRFC4min) + "tRFC4min_LSB" : 8, + "tRFC4min_MSB" : 8, + + # Byte 36 - 37: Minimum Four Activate Window Delay Time + # (tFAWmin) + "tFAWmin_MSN" : 4, + "Byte_36_reserved" : 4, + "tFAWmin_LSB" : 8, + + # Bytes 38: Minimum Activate to Activate Delay Time (tRRD_Smin), + # different bank group + "tRRD_Smin" : 8, + + # Byte 39: Minimum Activate to Activate Delay Time (tRRD_Lmin), + # same bank group + "tRRD_Lmin" : 8, + + # Byte 40: Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank + # group + "tCCD_Lmin" : 8, + + # Byte 41 - 42: Minimum Write Recovery Time (tWRmin) + "tWRmin_MSN" : 4, + "Byte_41_reserved" : 4, + "tWRmin_MSB" : 8, + + # Byte 43-45: Minimum Write to Read Time (tWTR_Smin), + # different bank group / Minimum Write to Read Time + # (tWTR_Lmin), same bank group + "tWTR_Smin_MSN" : 4, + "tWTR_Lmin_MSN" : 4, + "tWTR_Smin_LSB" : 8, + "tWTR_Lmin_LSB" : 8, + + # Byte 46~59: Reserved, Base Configuration Section + "Byte_46_59_reserved" [14] : 8, + + # Byte 60: Connector to SDRAM Bit Mapping (DQ0-3) + "DQ0_3" : 8, + # Byte 61: Connector to SDRAM Bit Mapping (DQ4-7) + "DQ4_7" : 8, + + # Byte 62: Connector to SDRAM Bit Mapping (DQ8-11) + "DQ8_11" : 8, + + # Byte 63: Connector to SDRAM Bit Mapping (DQ12-15) + "DQ12_15" : 8, + + # Byte 64: Connector to SDRAM Bit Mapping (DQ16-19) + "DQ16_19" : 8, + + # Byte 65: Connector to SDRAM Bit Mapping (DQ20-23) + "DQ20_23" : 8, + + # Byte 66: Connector to SDRAM Bit Mapping (DQ24-27) + "DQ24_27" : 8, + + # Byte 67: Connector to SDRAM Bit Mapping (DQ28-31) + "DQ28_31" : 8, + + # Byte 68: Connector to SDRAM Bit Mapping (CB0-3) + "CB0_3" : 8, + + # Byte 69: Connector to SDRAM Bit Mapping (CB4-7) + "CB4_7" : 8, + + # Byte 70: Connector to SDRAM Bit Mapping (DQ32-35) + "DQ32_35" : 8, + + # Byte 71: Connector to SDRAM Bit Mapping (DQ36-39) + "DQ36_39" : 8, + + # Byte 72: Connector to SDRAM Bit Mapping (DQ40-43) + "DQ40_43" : 8, + + # Byte 73: Connector to SDRAM Bit Mapping (DQ44-47) + "DQ44_47" : 8, + + # Byte 74: Connector to SDRAM Bit Mapping (DQ48-51) + "DQ48_51" : 8, + + # Byte 75: Connector to SDRAM Bit Mapping (DQ52-55) + "DQ52_55" : 8, + + # Byte 76: Connector to SDRAM Bit Mapping (DQ56-59) + "DQ56_59" : 8, + + # Byte 77: Connector to SDRAM Bit Mapping (DQ60-63) + "DQ60_63" : 8, + + # Bytes 78~116: Reserved, Base Configuration Section + # Must be coded as 0x00 + "Byte_78_116_reserved" [39] : 8, + + # Byte 117: Fine Offset for Minimum CAS to CAS Delay Time + # (tCCD_Lmin), same bank group + "tCCD_Lmin" : 8, + + # Byte 118: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Lmin), same bank group + "tRRD_Lmin" : 8, + + # Byte 119: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Smin), different bank group + "tRRD_Smin" : 8, + + # Byte 120: Fine Offset for Minimum Active to Active/Refresh + # Delay Time (tRCmin) + "tRCmin" : 8, + + # Byte 121: Fine Offset for Minimum Row Precharge Delay + # Time (tRPmin) + "tRPmin" : 8, + + # Byte 122: Fine Offset for Minimum RAS to CAS Delay + # Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 123: Fine Offset for Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 124: Fine Offset for SDRAM Maximum Cycle Time + # (tCKAVGmax) + "tCKAVGmax" : 8, + + # Byte 125: Fine Offset for SDRAM Minimum Cycle Time + # (tCKAVGmin) + "tCKAVGmin" : 8, + + # Byte 126 - 127: Cyclical Redundancy Code (CRC) for + # Base Configuration Section + "CRC_Base_Configuration" : 16, + +# Standard Module Parameters - Overlay Bytes 128~191 +# Module Specific Bytes for Registered Memory Module Types + + # Byte 128: Raw Card Extension, Module Nominal Height + "Module_Nominal_Height_Max" : 5, + "Raw_Card_Extension" : 3, + + # Byte 129: Module Maximum Thickness + "Module_Maximum_Thickness_Front" : 4, + "Module_Maximum_Thickness_Back" : 4, + + # Byte 130: Reference Raw Card Used + "Reference_Raw_Card" : 5, + "Reference_Raw_Card_Revision" : 2, + "Reference_Raw_Card_Extension" : 1, + + # Byte 131: DIMM Attributes + "Number_of_Registers_used_on_RDIMM" : 2, + "Number_of_DRAMS_on_RDIMM" : 2, + "Register_Type" : 4, + + # Byte 132: RDIMM Thermal Heat Spreader Solution + "Heat_Spreader_Thermal_Characteristics" : 7, + "Heat_Spreader_Solution" : 1, + + # Byte 133 - 134: Register Manufacturer ID Code + "Register_Manufacturer_ID_Code" : 16, + + # Byte 135: Register Revision Number + "Register_Revision_Number" : 8, + + # Byte 136: Address Mapping from Register to DRAM + "Rank_1_Mapping" : 1, + "Byte_136_Reserved" : 7, + + # Byte 137: Register Output Drive Strength for + # Control and Command/Address + "Register_Output_Drive_CKE" : 2, + "Register_Output_Drive_ODT" : 2, + "Register_Output_Drive_Command_Address" : 2, + "Register_Output_Drive_Chip_Select" : 2, + + # Byte 138: Register Output Drive Strength for Clock + "Register_Output_Drive_Strength_Clock_Y0_Y2" : 2, + "Register_Output_Drive_Strength_Clock_Y1_Y3" : 2, + "Byte_138_reserved" : 4, + + # Byte 139 - 191: Reserved + "Byte_139_191" [53] : 8, + +# Unused + # Byte 192 - 253: Unused + "Byte_192_255_unused" [62] : 8, + + # Byte 254 - 255: CRC for SPD Block 1 + "CRC_SPD_Block_1" : 16, + +# Reserved + # Byte 256 - 319: Reserved + "Byte_256_319_reserved" [64] : 8, + +# End User Programmable + # Byte 384 - 511 + "End_User_Programmable" [128] : 8 +} diff --git a/util/bincfg/ddr4_unbuffered_spd_512.spec b/util/bincfg/ddr4_unbuffered_spd_512.spec new file mode 100644 index 0000000000..594258e16b --- /dev/null +++ b/util/bincfg/ddr4_unbuffered_spd_512.spec @@ -0,0 +1,335 @@ +# 4_01_02_AnnexL-R25_SPD_for_DDR4_SDRAM_Release_3_Sep2015.pdf +# +# JEDEC Standard No. 21-C +# Page 4.1.2.12.3 – 1 +# Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules +# DDR4 SPD Document Release 3 +# UDIMM Revision 1.1 +# RDIMM Revision 1.1 +# LRDIMM Revision 1.1 +# NVDIMM Revision 1.0 + +{ + # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / + # CRC Coverage + "SPD_Bytes_Used" : 4, + "SPD_Bytes_Total" : 3, + "CRC_Coverage" : 1, + + # Byte 1: SPD Revision + "SPD_Revision" : 8, + + # Byte 2: Key Byte / DRAM Device Type + "DRAM_Device_Type" : 8, + + # Byte 3: Key Byte / Module Type + "Base_Module_Type" : 4, + "Hybrid_Media" : 3, + "Is_Hybrid" : 1, + + # Byte 4: SDRAM Density and Banks + "SDRAM_Capacity" : 4, + "Bank_Address_Bits" : 2, + "Bank_Group_Bits" : 2, + + # Byte 5: SDRAM Addressing + "Column_Address_Bits" : 3, + "Row_Address_Bits" : 3, + "Byte_5_reserved" : 2, + + # Byte 6: SDRAM Package Type + "Signal_Loading" : 2, + "Byte_6_reserved" : 2, + "Die_Count" : 3, + "SDRAM_Package_Type" : 1, + + # Byte 7: SDRAM Optional Features + "Maximum_Activate_Count" : 4, + "Maximum_Activate_Window" : 2, + "Byte_7_reserved" : 2, + + # Byte 8: SDRAM Thermal and Refresh Options + "Byte_8_reserved" : 8, + + # Byte 9: Other SDRAM Optional Features + "Byte_9_reserved" : 5, + "Soft_PPR" : 1, + "Post_Package_Repair" : 2, + + # Byte 10: Secondary SDRAM Package Type + "Secondary_Signal_Loading" : 2, + "Secondary_DRAM_Densityt_Ratio" : 2, + "Secondary_Die_Count" : 3, + "Secondary_SDRAM_Package_Type" : 1, + + # Byte 11: Module Nominal Voltage, VDD + "DRAM_VDD_1_2_V" : 2, + "Byte_11_reserved" : 6, + + # Byte 12: Module Organization + "SDRAM_Device_Width" : 3, + "Number_of_Package_Ranks_per_DIMM" : 3, + "Rank_Mix" : 1, + "Byte_12_reserved" : 1, + + # Byte 13: Module Memory Bus Width + "Primary_bus_width_in_bits" : 3, + "Bus_width_extension_in_bits" : 2, + "Byte_13_reserved" : 3, + + # Byte 14: Module Thermal Sensor + "Byte_14_reserved" : 7, + "Thermal_Sensor" : 1, + + # Byte 15: Extended Module Type + "Extended_Base_Module_Type" : 4, + "Byte_15_reserved" : 4, + + # Byte 16: Reserved + "Byte_16_reserved" : 8, + + # Byte 17: Timebases + "Fine_Timebase" : 2, + "Medium_Timebase" : 2, + "Byte_17_reserved" : 4, + + # Byte 18: SDRAM Minimum Cycle Time (tCKAVGmin) + "tCKAVGmin" : 8, + + # Byte 19: SDRAM Maximum Cycle Time (tCKAVGmax) + "tCKAVGmax" : 8, + + # Bytes 20 - 23: CAS Latencies Supported + "CL_7_Supported" : 1, + "CL_8_Supported" : 1, + "CL_9_Supported" : 1, + "CL_10_Supported" : 1, + "CL_11_Supported" : 1, + "CL_12_Supported" : 1, + "CL_13_Supported" : 1, + "CL_14_Supported" : 1, + + "CL_15_Supported" : 1, + "CL_16_Supported" : 1, + "CL_17_Supported" : 1, + "CL_18_Supported" : 1, + "CL_19_Supported" : 1, + "CL_20_Supported" : 1, + "CL_21_Supported" : 1, + "CL_22_Supported" : 1, + + "CL_23_Supported" : 1, + "CL_24_Supported" : 1, + "CL_25_Supported" : 1, + "CL_26_Supported" : 1, + "CL_27_Supported" : 1, + "CL_28_Supported" : 1, + "CL_29_Supported" : 1, + "CL_30_Supported" : 1, + + "CL_31_Supported" : 1, + "CL_32_Supported" : 1, + "CL_33_Supported" : 1, + "CL_34_Supported" : 1, + "CL_35_Supported" : 1, + "CL_36_Supported" : 1, + "Byte_23_reserved" : 1, + "CL_range" : 1, + + # Byte 24: Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 25: Minimum RAS to CAS Delay Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 26: Minimum Row Precharge Delay Time (tRPmin) + "tRPmin" : 8, + + # Bytes 27 - 29: Minimum Active to Precharge Delay Time (tRASmin) + # / Minimum Active to Active/Refresh Delay Time + # (tRCmin) + "tRASmin_MSN" : 4, + "tRCmin_MSN" : 4, + "tRASmin_LSB" : 8, + "tRCmin_LSB" : 8, + + # Bytes 30 - 31: Minimum Refresh Recovery Delay Time (tRFC1min) + "tRFC1min_LSB" : 8, + "tRFC1min_MSB" : 8, + + # Bytes 32 - 33: Minimum Refresh Recovery Delay Time (tRFC2min) + "tRFC2min_LSB" : 8, + "tRFC2min_MSB" : 8, + + # Bytes 34 - 35: Minimum Refresh Recovery Delay Time (tRFC4min) + "tRFC4min_LSB" : 8, + "tRFC4min_MSB" : 8, + + # Byte 36 - 37: Minimum Four Activate Window Delay Time + # (tFAWmin) + "tFAWmin_MSN" : 4, + "Byte_36_reserved" : 4, + "tFAWmin_LSB" : 8, + + # Bytes 38: Minimum Activate to Activate Delay Time (tRRD_Smin), + # different bank group + "tRRD_Smin" : 8, + + # Byte 39: Minimum Activate to Activate Delay Time (tRRD_Lmin), + # same bank group + "tRRD_Lmin" : 8, + + # Byte 40: Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank + # group + "tCCD_Lmin" : 8, + + # Byte 41 - 42: Minimum Write Recovery Time (tWRmin) + "tWRmin_MSN" : 4, + "Byte_41_reserved" : 4, + "tWRmin_MSB" : 8, + + # Byte 43-45: Minimum Write to Read Time (tWTR_Smin), + # different bank group / Minimum Write to Read Time + # (tWTR_Lmin), same bank group + "tWTR_Smin_MSN" : 4, + "tWTR_Lmin_MSN" : 4, + "tWTR_Smin_LSB" : 8, + "tWTR_Lmin_LSB" : 8, + + # Byte 46~59: Reserved, Base Configuration Section + "Byte_46_59_reserved" [14] : 8, + + # Byte 60: Connector to SDRAM Bit Mapping (DQ0-3) + "DQ0_3" : 8, + # Byte 61: Connector to SDRAM Bit Mapping (DQ4-7) + "DQ4_7" : 8, + + # Byte 62: Connector to SDRAM Bit Mapping (DQ8-11) + "DQ8_11" : 8, + + # Byte 63: Connector to SDRAM Bit Mapping (DQ12-15) + "DQ12_15" : 8, + + # Byte 64: Connector to SDRAM Bit Mapping (DQ16-19) + "DQ16_19" : 8, + + # Byte 65: Connector to SDRAM Bit Mapping (DQ20-23) + "DQ20_23" : 8, + + # Byte 66: Connector to SDRAM Bit Mapping (DQ24-27) + "DQ24_27" : 8, + + # Byte 67: Connector to SDRAM Bit Mapping (DQ28-31) + "DQ28_31" : 8, + + # Byte 68: Connector to SDRAM Bit Mapping (CB0-3) + "CB0_3" : 8, + + # Byte 69: Connector to SDRAM Bit Mapping (CB4-7) + "CB4_7" : 8, + + # Byte 70: Connector to SDRAM Bit Mapping (DQ32-35) + "DQ32_35" : 8, + + # Byte 71: Connector to SDRAM Bit Mapping (DQ36-39) + "DQ36_39" : 8, + + # Byte 72: Connector to SDRAM Bit Mapping (DQ40-43) + "DQ40_43" : 8, + + # Byte 73: Connector to SDRAM Bit Mapping (DQ44-47) + "DQ44_47" : 8, + + # Byte 74: Connector to SDRAM Bit Mapping (DQ48-51) + "DQ48_51" : 8, + + # Byte 75: Connector to SDRAM Bit Mapping (DQ52-55) + "DQ52_55" : 8, + + # Byte 76: Connector to SDRAM Bit Mapping (DQ56-59) + "DQ56_59" : 8, + + # Byte 77: Connector to SDRAM Bit Mapping (DQ60-63) + "DQ60_63" : 8, + + # Bytes 78~116: Reserved, Base Configuration Section + # Must be coded as 0x00 + "Byte_78_116_reserved" [39] : 8, + + # Byte 117: Fine Offset for Minimum CAS to CAS Delay Time + # (tCCD_Lmin), same bank group + "tCCD_Lmin_Fine_Offset" : 8, + + # Byte 118: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Lmin), same bank group + "tRRD_Lmin_Fine_Offset" : 8, + + # Byte 119: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Smin), different bank group + "tRRD_Smin_Fine_Offset" : 8, + + # Byte 120: Fine Offset for Minimum Active to Active/Refresh + # Delay Time (tRCmin) + "tRCmin_Fine_Offset" : 8, + + # Byte 121: Fine Offset for Minimum Row Precharge Delay + # Time (tRPmin) + "tRPmin_Fine_Offset" : 8, + + # Byte 122: Fine Offset for Minimum RAS to CAS Delay + # Time (tRCDmin) + "tRCDmin_Fine_Offset" : 8, + + # Byte 123: Fine Offset for Minimum CAS Latency Time (tAAmin) + "tAAmin_Fine_Offset" : 8, + + # Byte 124: Fine Offset for SDRAM Maximum Cycle Time + # (tCKAVGmax) + "tCKAVGmax_Fine_Offset" : 8, + + # Byte 125: Fine Offset for SDRAM Minimum Cycle Time + # (tCKAVGmin) + "tCKAVGmin_Fine_Offset" : 8, + + # Byte 126 - 127: Cyclical Redundancy Code (CRC) for + # Base Configuration Section + "CRC_Base_Configuration" : 16, + +# Standard Module Parameters - Overlay Bytes 128~191 +# Module Specific Bytes for Unbuffered Memory Module Types + + # Byte 128: Raw Card Extension, Module Nominal Height + "Module_Nominal_Height_Max" : 5, + "Raw_Card_Extension" : 3, + + # Byte 129: Module Maximum Thickness + "Module_Maximum_Thickness_Front" : 4, + "Module_Maximum_Thickness_Back" : 4, + + # Byte 130: Reference Raw Card Used + "Reference_Raw_Card" : 5, + "Reference_Raw_Card_Revision" : 2, + "Reference_Raw_Card_Extension" : 1, + + # Byte 131: Address Mapping from Edge Connector to DRAM + "Rank_1_Mapping" : 1, + "Byte_131_reserved" : 7, + + # Byte 132 - 191: Reserved + "Byte_132_191_reserved" [60] : 8, + +# Unused + # Byte 192 - 253: Unused + "Byte_192_255_unused" [62] : 8, + + # Byte 254 - 255: CRC for SPD Block 1 + "CRC_SPD_Block_1" : 16, + +# Reserved + # Byte 256 - 319: Reserved + "Byte_256_319_reserved" [64] : 8, + +# End User Programmable + # Byte 384 - 511 + "End_User_Programmable" [128] : 8 +} diff --git a/util/scripts/decode_spd.sh b/util/scripts/decode_spd.sh new file mode 100755 index 0000000000..9ab9fa30cf --- /dev/null +++ b/util/scripts/decode_spd.sh @@ -0,0 +1,76 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# +# Parses spd hex files and outputs the contents in various formats +# +# +# Outputs csv, set, and json in same folder as SPD_HEX_FILE +# +# Example: +# decode_spd.sh ../../src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex +# +# Outputs ../../src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.{json|csv|set} +# +# TODO: This script assumes bincfg binary is at ../bincfg/bincfg (which is the +# result of running the bincfg make), and the specs are at +# ../bincfg/*.spec. This dependency should be made more resilliant and +# configurable. + +set -e + +function read8 () { + echo $(( 16#$(xxd -s "${2}" -l 1 -p "${1}") )) +} + +for file in "$@" +do + bintmp=$(mktemp) + outfile="${file%.hex}.set" + + echo "Decoding ${file}, outputting to ${outfile}" + + grep -v '^#' "${file}" | xxd -r -p - "${bintmp}" + dram_type=$(read8 "${bintmp}" 2) + if [ ! "${dram_type}" -eq 12 ] + then + #TODO: Handle other dram types + printf "Error: Expecting dram4 (12), got %d\n" "${dram_type}" + continue + fi + + revision=$(read8 "${bintmp}" 1) + if [ ! "${revision}" -eq $((0x13)) ] + then + printf "Warning: Expecting revision 0x13, got 0x%x.\n" "${revision}" + fi + + module_type=$(read8 "${bintmp}" 3) + case "${module_type}" in + 1) # RDIMM + spec="../bincfg/ddr4_registered_spd_512.spec" + ;; + 2 | 3) #UDIMM | SO-DIMM + spec="../bincfg/ddr4_unbuffered_spd_512.spec" + ;; + * ) + printf "Error: Unhandled module type %d.\n" "${module_type}" + ;; + esac + + ../bincfg/bincfg -d "${spec}" "${bintmp}" "${outfile}" + grep -v '^#' "${outfile}" | sed -e 's/ = \([^,]\+\)/: "\1"/g' \ + > "${file%.hex}.json" + grep -v -e '^#' -e '^{' -e '^}' "${outfile}" | sed -e 's/=/,/g' \ + > "${file%.hex}.csv" +done diff --git a/util/scripts/description.md b/util/scripts/description.md index 1f4e7df042..a08771d48d 100644 --- a/util/scripts/description.md +++ b/util/scripts/description.md @@ -3,6 +3,8 @@ __scripts__ line `Bash` * _cross-repo-cherrypick_ - Pull in patches from another tree from a gerrit repository. `Shell` + * _decode_spd.sh_ - Decodes Serial Presence Detect (SPD) files into + various human readable formats. * _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an fmaptool compatible .fmd format `Bash` * _find-unused-kconfig-symbols.sh_ - Points out Kconfig variables From df248f0c10f77b4de287be7754afadce1abca84c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 12 Nov 2019 10:05:33 +0100 Subject: [PATCH 0520/1463] mb/asrock/b85m_pro4: Add new mainboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a µATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Working: - All four DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI and DVI - Intel GbE - All PCIe ports - Both PCI ports behind the ASM1083 PCI bridge - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - Rear audio output - VBT - SeaBIOS to boot Arch Linux Not working: - PS/2 keyboard (detected as mouse) Untested: - The other audio jacks - S/PDIF - VGA - EHCI debug - Front USB headers - Non-Linux OSes - TPM header - Parallel port Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/36770 Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/asrock/b85m_pro4/Kconfig | 47 +++++ src/mainboard/asrock/b85m_pro4/Kconfig.name | 2 + src/mainboard/asrock/b85m_pro4/Makefile.inc | 5 + src/mainboard/asrock/b85m_pro4/acpi/ec.asl | 0 .../asrock/b85m_pro4/acpi/platform.asl | 23 ++ .../asrock/b85m_pro4/acpi/superio.asl | 26 +++ src/mainboard/asrock/b85m_pro4/acpi_tables.c | 21 ++ src/mainboard/asrock/b85m_pro4/board_info.txt | 7 + src/mainboard/asrock/b85m_pro4/bootblock.c | 43 ++++ src/mainboard/asrock/b85m_pro4/cmos.default | 4 + src/mainboard/asrock/b85m_pro4/cmos.layout | 65 ++++++ src/mainboard/asrock/b85m_pro4/data.vbt | Bin 0 -> 6144 bytes src/mainboard/asrock/b85m_pro4/devicetree.cb | 119 +++++++++++ src/mainboard/asrock/b85m_pro4/dsdt.asl | 40 ++++ .../asrock/b85m_pro4/gma-mainboard.ads | 30 +++ src/mainboard/asrock/b85m_pro4/gpio.c | 196 ++++++++++++++++++ src/mainboard/asrock/b85m_pro4/hda_verb.c | 63 ++++++ src/mainboard/asrock/b85m_pro4/romstage.c | 100 +++++++++ 18 files changed, 791 insertions(+) create mode 100644 src/mainboard/asrock/b85m_pro4/Kconfig create mode 100644 src/mainboard/asrock/b85m_pro4/Kconfig.name create mode 100644 src/mainboard/asrock/b85m_pro4/Makefile.inc create mode 100644 src/mainboard/asrock/b85m_pro4/acpi/ec.asl create mode 100644 src/mainboard/asrock/b85m_pro4/acpi/platform.asl create mode 100644 src/mainboard/asrock/b85m_pro4/acpi/superio.asl create mode 100644 src/mainboard/asrock/b85m_pro4/acpi_tables.c create mode 100644 src/mainboard/asrock/b85m_pro4/board_info.txt create mode 100644 src/mainboard/asrock/b85m_pro4/bootblock.c create mode 100644 src/mainboard/asrock/b85m_pro4/cmos.default create mode 100644 src/mainboard/asrock/b85m_pro4/cmos.layout create mode 100644 src/mainboard/asrock/b85m_pro4/data.vbt create mode 100644 src/mainboard/asrock/b85m_pro4/devicetree.cb create mode 100644 src/mainboard/asrock/b85m_pro4/dsdt.asl create mode 100644 src/mainboard/asrock/b85m_pro4/gma-mainboard.ads create mode 100644 src/mainboard/asrock/b85m_pro4/gpio.c create mode 100644 src/mainboard/asrock/b85m_pro4/hda_verb.c create mode 100644 src/mainboard/asrock/b85m_pro4/romstage.c diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig new file mode 100644 index 0000000000..91ae3a5b24 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASROCK_B85M_PRO4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + +config MAINBOARD_DIR + string + default asrock/b85m_pro4 + +config MAINBOARD_PART_NUMBER + string + default "B85M Pro4" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig.name b/src/mainboard/asrock/b85m_pro4/Kconfig.name new file mode 100644 index 0000000000..4bb4dfd985 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_B85M_PRO4 + bool "B85M Pro4" diff --git a/src/mainboard/asrock/b85m_pro4/Makefile.inc b/src/mainboard/asrock/b85m_pro4/Makefile.inc new file mode 100644 index 0000000000..d9a8d18d0d --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/b85m_pro4/acpi/ec.asl b/src/mainboard/asrock/b85m_pro4/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asrock/b85m_pro4/acpi/platform.asl b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl new file mode 100644 index 0000000000..c70c466720 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl new file mode 100644 index 0000000000..b671e3cb37 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c new file mode 100644 index 0000000000..10e5f944ba --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asrock/b85m_pro4/board_info.txt b/src/mainboard/asrock/b85m_pro4/board_info.txt new file mode 100644 index 0000000000..a9a29cb009 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/B85M%20Pro4/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c new file mode 100644 index 0000000000..6a66121aa6 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select HWM/LED functions instead of floppy functions */ + pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default new file mode 100644 index 0000000000..c51001c03c --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout new file mode 100644 index 0000000000..f9236e10a8 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- + entries +# ----------------------------------------------------------------- +# Offset Size Type Enum Name +# ----------------------------------------------------------------- + 0 120 r 0 reserved_memory + 384 1 e 3 boot_option + 388 4 h 0 reboot_counter + 395 4 e 4 debug_level + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + 984 16 h 0 check_sum +# ----------------------------------------------------------------- + + +# ----------------------------------------------------------------- + enumerations +# ----------------------------------------------------------------- +# ID Value Text +# ----------------------------------------------------------------- + 1 0 Disable + 1 1 Enable +# ----------------------------------------------------------------- + 3 0 Fallback + 3 1 Normal +# ----------------------------------------------------------------- + 4 0 Emergency + 4 1 Alert + 4 2 Critical + 4 3 Error + 4 4 Warning + 4 5 Notice + 4 6 Info + 4 7 Debug + 4 8 Spew +# ----------------------------------------------------------------- + 5 0 Disable + 5 1 Enable + 5 2 Keep +# ----------------------------------------------------------------- + + +# ----------------------------------------------------------------- + checksums +# ----------------------------------------------------------------- +# Start End Store +# ----------------------------------------------------------------- + checksum 392 415 984 +# ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/b85m_pro4/data.vbt b/src/mainboard/asrock/b85m_pro4/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..93b2418f7164587ec8e33f668288c7a3f039822d GIT binary patch literal 6144 zcmeHJU2GIp6h3!mc6WAmX1bkL*sf4dfxx!XcG{BKG&Rn)+qzp8y8WS4g6RUgB3h&r zF!+&56@V0DbJXUh*4Eey+tXvAfm)0XuErHx)^8e1H%8Lip5MM@91~qJ3~$(w9!pQG z+n!G0;P8`Ssj<1OvDs{DA-koW{w-~q z66x;hTak#x!$YyYmDo3ck=S5(aIkwtXZ$Hl4D>}~ow1?rh^7?!(Y0m#rHM@&pWTk3 zu3Bt1O|zajo6v4Dc5Rs$Z@}=_7!L55Z8(tLmY#Sqoodh&&T$H4i2*Pdlrf938_nRA znJP_fP#Z-h5}cX!w`2Eh~LfqoWcGUzi|W$ z#-Hi?6(CYyqX&xotbdM zTMZLp2o8$^92MJOg>(iEdlA0$`r#tsGGWvs!x4`GpAk+Iz9;X~IUrR>CWUHwf<&4iJtIJ|&zad_g!%xJdYs;NAh(b3z6@b}}=}(dBs! zehJ>Ih0H<6f6(!JuhP6AQ5@}awCyb6lFNBKa5Hy40J)s}IB$VP43sJsahRfxj@w!k z6VCk*X`bH^=RTM7Ch4}Be)sRHoQ2}D%;o4qwmhho?=;k8s0YrvLf#qX8lTT~Q8HxR z9w4|T?jBHlvtZoGQ1BP^KMznVpqGk|D0fWGvuRfWII z#Q`jS|6en_uD?W8E*HZMwNNZn(M zc%n~O=K2%OmUXJ&351|^mzYnc+PcdH_O3z}%i6P;EH}**616G>Rqz}Asvye{^1m~* z1Lc29*)1!`Ssp$I7pMSV@LXeiD*m4q?^kJ(%gt+rOWsTtr|0|SD{hH3n2= zt%|!O*xTGr6D!MfzpeYM9jB3UjO-X6^wq_jEl#ew$rx`zJ%4H38-9TNb z(=nkN>vd&J#}9PlBV9SJn?%vMWRxw#d|Z%T-JPb=2s#gZ_dzh z*Ivvl1AJBISMW|(uq1|^*dO#;{$e5F)xa**YH18J3lC?o&!wv6K2bs&W)>=5hwS>P z4!cUp!Q|zWCkjdet$WCE8hmHrX*^K+wKDs_UKk{_xhK>$g$ot zbmG4+*W4Yl^dWewhmski6aOkmKnj+!eQ;T9I03MyC=Z6oC&jGHW?(i0vl*Dpz-$H{ H^bGtCL<9~X literal 0 HcmV?d00001 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb new file mode 100644 index 0000000000..5cf4cf4cc8 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -0,0 +1,119 @@ +chip northbridge/intel/haswell + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1849 0x0c00 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe graphics + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x83" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8b" + register "pirqh_routing" = "0x8a" + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 on end # ME KT + device pci 19.0 on end # Intel GbE through I217-V PHY + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: ASM1083 PCI bridge + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 on end # RP #5: PCIe x16 (electrical x4) + device pci 1d.0 on end # EHCI #1 + device pci 1f.0 on # LPC bridge + + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x3b + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 12 # + Keyboard + irq 0x72 = 12 # + Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfb # + GPIO0 value + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # + GPIO2 direction + end + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe0 = 0x41 # + Enable KBC wakeup + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 + io 0x60 = 0x0290 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl new file mode 100644 index 0000000000..0fa3253a43 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads new file mode 100644 index 0000000000..c595ad4c84 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Angel Pons +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; version 2 of the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI3, -- HDMI + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/b85m_pro4/gpio.c b/src/mainboard/asrock/b85m_pro4/gpio.c new file mode 100644 index 0000000000..4400451568 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gpio.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c new file mode 100644 index 0000000000..bc7c0292c9 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x1849c892, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1849c892), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), + AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), + AZALIA_PIN_CFG(0, 0x1d, 0x598301f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x0221102f), + + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x41c46060), + + 0x80862806, /* Codec Vendor / Device ID: Intel Haswell HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c new file mode 100644 index 0000000000..84b0f62992 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ec_present = 0, + .gbe_enable = 1, + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + }; + + romstage_common(&romstage_params); +} From 81877365d5a7d7f839957714c8fbeb9863d6c564 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Wed, 18 Mar 2020 16:51:04 +0530 Subject: [PATCH 0521/1463] soc/intel/tigerlake: Update header to avoid compilation issue We were including stddefs.h and stdint.h but compilation fails when we use 'bool' type in file. Removing stddef.h and stdint.h and including 'types.h' which includes all data types BUG=None BRANCH=None TEST=Check if compilation passes when bool is used Change-Id: I4c9001f729f3103deba9d1fd631a8942c23276ee Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39630 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Ronak Kanabar Reviewed-by: Patrick Georgi Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/include/soc/meminit_jsl.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h index 7f860ede52..b828ae1cdf 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h @@ -15,8 +15,7 @@ #ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ #define _SOC_JASPERLAKE_MEMCFG_INIT_H_ -#include -#include +#include #include /* Number of dq bits controlled per dqs */ From 44eeed0e5cbb1d449d2398671b29bb36b661ac6f Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 5 Mar 2020 17:37:05 +0530 Subject: [PATCH 0522/1463] soc/intel/tigerlake: add support to read SPD data from SMBus Jasper Lake RVP has DDR4 variant which uses SMBus address to read SPD data. So, add support to read SPD data from SMBUS. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Signed-off-by: Ronak Kanabar Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39401 Reviewed-by: Subrata Banik Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- .../intel/tigerlake/include/soc/meminit_jsl.h | 15 +++++++++---- src/soc/intel/tigerlake/meminit_jsl.c | 21 ++++++++++++------- 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h index b828ae1cdf..421e31d8e4 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h @@ -27,6 +27,9 @@ /* Number of DQ byte mappings */ #define DDR_NUM_BYTE_MAPPINGS 6 +/* Number of memory DIMM slots available on Jasper Lake */ +#define NUM_DIMM_SLOT 4 + /* 64-bit Channel identification */ enum { DDR_CH0, @@ -40,17 +43,21 @@ struct spd_by_pointer { }; enum mem_info_read_type { - READ_SPD_CBFS, /* Find spd file in CBFS. */ - READ_SPD_MEMPTR /* Find spd data from pointer. */ + READ_SPD_CBFS, /* Find SPD file in CBFS. */ + READ_SMBUS, /* Read on-module SPD by SMBUS. */ + READ_SPD_MEMPTR /* Find SPD data from pointer. */ }; struct spd_info { enum mem_info_read_type read_type; union spd_data_by { - /* To identify spd file when read_type is READ_SPD_CBFS. */ + /* To read on-module SPD when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address[NUM_DIMM_SLOT]; + + /* To identify SPD file when read_type is READ_SPD_CBFS. */ int spd_index; - /* To find spd data when read_type is READ_SPD_MEMPTR. */ + /* To find SPD data when read_type is READ_SPD_MEMPTR. */ struct spd_by_pointer spd_data_ptr_info; } spd_spec; }; diff --git a/src/soc/intel/tigerlake/meminit_jsl.c b/src/soc/intel/tigerlake/meminit_jsl.c index 3247357f1a..c68d2100fc 100644 --- a/src/soc/intel/tigerlake/meminit_jsl.c +++ b/src/soc/intel/tigerlake/meminit_jsl.c @@ -102,15 +102,22 @@ static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_c void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, const struct spd_info *spd_info, bool half_populated) { - size_t spd_data_len; - uintptr_t spd_data_ptr; - memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); - get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); - print_spd_info((unsigned char *)spd_data_ptr); + if (spd_info->read_type == READ_SMBUS) { + for (int i = 0; i < NUM_DIMM_SLOT; i++) + mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; - mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); + } else { + uintptr_t spd_data_ptr = 0; + size_t spd_data_len = 0; + memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); + get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + } /* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; From e82b02c004e94c4f6016543088f99120be415ff3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 18 Mar 2020 13:09:39 +0100 Subject: [PATCH 0523/1463] nb/intel/sandybridge: Use loops on DMI register groups The DMI link consists of four lanes, grouped in two bundles. Therefore, some DMI registers may be organized as "per-lane" or "per-bundle". This can be seen in the DMI initialization sequence as series of equidistant offsets being programmed with the same value. Make this more obvious by factoring out the register groups using loops. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39631 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/early_dmi.c | 279 +++++++++--------- 1 file changed, 142 insertions(+), 137 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 99705bb358..dec371fd15 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -20,179 +20,184 @@ void early_init_dmi(void) { int i; - DMIBAR32(0x0914) |= 0x80000000; - DMIBAR32(0x0934) |= 0x80000000; + for (i = 0; i < 2; i++) { + DMIBAR32(0x0914 + (i << 5)) |= (1 << 31); + } for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; - DMIBAR32(0x0a04 + (i << 4)) |= 0x800; + DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000; + DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11); } - DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; + DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30); for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; - DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; + DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000; + DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000; } - DMIBAR32(0x090c) &= 0xfe1fffff; - DMIBAR32(0x092c) &= 0xfe1fffff; - DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x7a1842ec; - DMIBAR32(0x090c); // !!! = 0x00000208 - DMIBAR32(0x090c) = 0x00000128; - DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x7a1842ec; - DMIBAR32(0x092c); // !!! = 0x00000208 - DMIBAR32(0x092c) = 0x00000128; - DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; + for (i = 0; i < 2; i++) { + DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec + DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec; + DMIBAR32(0x090c + (i << 5)); // !!! = 0x00000208 + DMIBAR32(0x090c + (i << 5)) = 0x00000128; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 + DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + } + DMIBAR32(0x0c04); // !!! = 0x2e680008 DMIBAR32(0x0c04) = 0x2e680008; - DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x3a1842ec; - DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x3a1842ec; - DMIBAR32(0x0910); // !!! = 0x00006300 - DMIBAR32(0x0910) = 0x00004300; - DMIBAR32(0x0930); // !!! = 0x00006300 - DMIBAR32(0x0930) = 0x00004300; - DMIBAR32(0x0a00); // !!! = 0x03042010 - DMIBAR32(0x0a00) = 0x03042018; - DMIBAR32(0x0a10); // !!! = 0x03042010 - DMIBAR32(0x0a10) = 0x03042018; - DMIBAR32(0x0a20); // !!! = 0x03042010 - DMIBAR32(0x0a20) = 0x03042018; - DMIBAR32(0x0a30); // !!! = 0x03042010 - DMIBAR32(0x0a30) = 0x03042018; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec + DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0910 + (i << 5)); // !!! = 0x00006300 + DMIBAR32(0x0910 + (i << 5)) = 0x00004300; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042010 + DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + } + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; - DMIBAR32(0x0a04); // !!! = 0x0c0708f0 - DMIBAR32(0x0a04) = 0x0c0718f0; - DMIBAR32(0x0a14); // !!! = 0x0c0708f0 - DMIBAR32(0x0a14) = 0x0c0718f0; - DMIBAR32(0x0a24); // !!! = 0x0c0708f0 - DMIBAR32(0x0a24) = 0x0c0718f0; - DMIBAR32(0x0a34); // !!! = 0x0c0708f0 - DMIBAR32(0x0a34) = 0x0c0718f0; - DMIBAR32(0x0900); // !!! = 0x50000000 - DMIBAR32(0x0900) = 0x50000000; - DMIBAR32(0x0920); // !!! = 0x50000000 - DMIBAR32(0x0920) = 0x50000000; - DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; - DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; - DMIBAR32(0x0904); // !!! = 0x3a1842ec - DMIBAR32(0x0904) = 0x3a1846ec; - DMIBAR32(0x0924); // !!! = 0x3a1842ec - DMIBAR32(0x0924) = 0x3a1846ec; - DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a04 + (i << 4)); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0900 + (i << 5)); // !!! = 0x50000000 + DMIBAR32(0x0900 + (i << 5)) = 0x50000000; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff + DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 + DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 + DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1842ec + DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 + DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff + DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + } + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; + DMIBAR32(0x0c0c); // !!! = 0x16063400 DMIBAR32(0x0c0c) = 0x00063400; - DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46339008; - DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46339008; - DMIBAR32(0x0700); // !!! = 0x46339008 - DMIBAR32(0x0700) = 0x45339008; - DMIBAR32(0x0720); // !!! = 0x46339008 - DMIBAR32(0x0720) = 0x45339008; - DMIBAR32(0x0700); // !!! = 0x45339008 - DMIBAR32(0x0700) = 0x453b9008; - DMIBAR32(0x0720); // !!! = 0x45339008 - DMIBAR32(0x0720) = 0x453b9008; - DMIBAR32(0x0700); // !!! = 0x453b9008 - DMIBAR32(0x0700) = 0x45bb9008; - DMIBAR32(0x0720); // !!! = 0x453b9008 - DMIBAR32(0x0720) = 0x45bb9008; - DMIBAR32(0x0700); // !!! = 0x45bb9008 - DMIBAR32(0x0700) = 0x45fb9008; - DMIBAR32(0x0720); // !!! = 0x45bb9008 - DMIBAR32(0x0720) = 0x45fb9008; - DMIBAR32(0x0914); // !!! = 0x9021a080 - DMIBAR32(0x0914) = 0x9021a280; - DMIBAR32(0x0934); // !!! = 0x9021a080 - DMIBAR32(0x0934) = 0x9021a280; - DMIBAR32(0x0914); // !!! = 0x9021a280 - DMIBAR32(0x0914) = 0x9821a280; - DMIBAR32(0x0934); // !!! = 0x9021a280 - DMIBAR32(0x0934) = 0x9821a280; - DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03242018; - DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03242018; - DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03242018; - DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03242018; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 + DMIBAR32(0x0700 + (i << 5)) = 0x46339008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46339008 + DMIBAR32(0x0700 + (i << 5)) = 0x45339008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45339008 + DMIBAR32(0x0700 + (i << 5)) = 0x453b9008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x453b9008 + DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45bb9008 + DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 + DMIBAR32(0x0914 + (i << 5)) = 0x9021a280; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 + DMIBAR32(0x0914 + (i << 5)) = 0x9821a280; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 + DMIBAR32(0x0a00 + (i << 4)) = 0x03242018; + } + DMIBAR32(0x0258); // !!! = 0x40000600 DMIBAR32(0x0258) = 0x60000600; - DMIBAR32(0x0904); // !!! = 0x3a1846ec - DMIBAR32(0x0904) = 0x2a1846ec; - DMIBAR32(0x0914); // !!! = 0x9821a280 - DMIBAR32(0x0914) = 0x98200280; - DMIBAR32(0x0924); // !!! = 0x3a1846ec - DMIBAR32(0x0924) = 0x2a1846ec; - DMIBAR32(0x0934); // !!! = 0x9821a280 - DMIBAR32(0x0934) = 0x98200280; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1846ec + DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec; + DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9821a280 + DMIBAR32(0x0914 + (i << 5)) = 0x98200280; + } + DMIBAR32(0x022c); // !!! = 0x00c26460 DMIBAR32(0x022c) = 0x00c2403c; early_pch_init_native_dmi_pre(); - /* Write once settings. */ + /* Write once settings */ DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | - (2 << 0) | // 5GT/s - (2 << 12) | // L0s 128 ns to less than 256 ns - (2 << 15); // L1 2 us to less than 4 us + (2 << 0) | // 5GT/s + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us - DMIBAR8(DMILCTL) |= 0x20; // Retrain link + DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link while (DMIBAR16(DMILSTS) & TXTRN) ; - DMIBAR8(DMILCTL) |= 0x20; // Retrain link + DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link while (DMIBAR16(DMILSTS) & TXTRN) ; - const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; - const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; + const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; + const u16 t = (DMIBAR16(DMILSTS) & 0x0f) * 2500; printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); /* * Virtual Channel resources must match settings in RCBA! * - * Channel Vp and Vm are documented in - * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel - * Pentium Processor Family, and Desktop Intel Celeron Processor Family - * Vol. 2" + * Channel Vp and Vm are documented in: + * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium + * Processor Family, and Desktop Intel Celeron Processor Family Vol. 2" */ /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ From 34473ea6c9ee63de46b04b46cc47ef4aa5bae2b7 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Wed, 18 Mar 2020 10:23:26 +0800 Subject: [PATCH 0524/1463] soc/intel/xeon_sp: Modify FSP-T code caching parameters Use CACHE_ROM_BASE and CACHE_ROM_SIZE for code caching parameters. Tested on OCP Tioga Pass. Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/39625 Reviewed-by: Nico Huber Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/bootblock/bootblock.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 6b2c48809d..dc88adc308 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -19,6 +19,7 @@ #include #include #include +#include const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -29,8 +30,8 @@ const FSPT_UPD temp_ram_init_params = { .FsptCoreUpd = { .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, - .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), - .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, + .CodeRegionBase = (UINT32)CACHE_ROM_BASE, + .CodeRegionLength = (UINT32)CACHE_ROM_SIZE, .Reserved1 = {0}, }, .FsptConfig = { From 260ba6b25e6a5611b7ba3b581d343a35fb7bbbff Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 18 Mar 2020 15:40:58 +0100 Subject: [PATCH 0525/1463] util/xcompile: Split $CFLAGS_GCC Split common flags that are not specific to the C language out of $CFLAGS_GCC into $FLAGS_GCC. This way, we can test for C specific flags, too, without adding them to $ADAFLAGS_*. Currently this is done for `-Wno-address-of-packed-member` which only applies to C. Change-Id: Ib793c62656efb07b6e5b3385f1ed1c96a40efd1d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39633 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/xcompile/xcompile | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3203d71899..18e08a0659 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -148,11 +148,11 @@ testas() { [ "$obj_arch" = "$full_arch" ] || return 1 unset ASFLAGS LDFLAGS - unset CFLAGS_GCC CFLAGS_CLANG + unset FLAGS_GCC CFLAGS_GCC CFLAGS_CLANG if [ -n "$use_dash_twidth" ]; then ASFLAGS="--$twidth" - CFLAGS_GCC="-m$twidth" + FLAGS_GCC="-m$twidth" CFLAGS_CLANG="-m$twidth" LDFLAGS="-b $full_arch" @@ -162,7 +162,7 @@ testas() { [ -n "$use_dash_twidth" ] && case "$full_arch" in "elf32-i386" ) LDFLAGS="$LDFLAGS -melf_i386" - CFLAGS_GCC="$CFLAGS_GCC -Wl,-b,elf32-i386 -Wl,-melf_i386" + FLAGS_GCC="$FLAGS_GCC -Wl,-b,elf32-i386 -Wl,-melf_i386" CFLAGS_CLANG="$CFLAGS_CLANG -Wl,-b,elf32-i386 -Wl,-melf_i386" ;; esac @@ -173,19 +173,19 @@ testas() { detect_special_flags() { local architecture="$1" # Check for an operational -m32/-m64 - testcc "$GCC" "$CFLAGS_GCC -m$TWIDTH " && - CFLAGS_GCC="$CFLAGS_GCC -m$TWIDTH " + testcc "$GCC" "$FLAGS_GCC -m$TWIDTH " && + FLAGS_GCC="$FLAGS_GCC -m$TWIDTH " # Use bfd linker instead of gold if available: - testcc "$GCC" "$CFLAGS_GCC -fuse-ld=bfd" && - CFLAGS_GCC="$CFLAGS_GCC -fuse-ld=bfd" && LINKER_SUFFIX='.bfd' + testcc "$GCC" "$FLAGS_GCC -fuse-ld=bfd" && + FLAGS_GCC="$FLAGS_GCC -fuse-ld=bfd" && LINKER_SUFFIX='.bfd' - testcc "$GCC" "$CFLAGS_GCC -fno-stack-protector" && - CFLAGS_GCC="$CFLAGS_GCC -fno-stack-protector" - testcc "$GCC" "$CFLAGS_GCC -Wl,--build-id=none" && - CFLAGS_GCC="$CFLAGS_GCC -Wl,--build-id=none" + testcc "$GCC" "$FLAGS_GCC -fno-stack-protector" && + FLAGS_GCC="$FLAGS_GCC -fno-stack-protector" + testcc "$GCC" "$FLAGS_GCC -Wl,--build-id=none" && + FLAGS_GCC="$FLAGS_GCC -Wl,--build-id=none" - testcc "$GCC" "$CFLAGS_GCC -Wno-address-of-packed-member" && + testcc "$GCC" "$CFLAGS_GCC -Wno-address-of-packed-member $FLAGS_GCC" && CFLAGS_GCC="$CFLAGS_GCC -Wno-address-of-packed-member" case "$architecture" in x86) @@ -193,7 +193,7 @@ detect_special_flags() { x64) ;; arm64) - testld "$GCC" "$CFLAGS_GCC" "${GCCPREFIX}ld${LINKER_SUFFIX}" \ + testld "$GCC" "$FLAGS_GCC" "${GCCPREFIX}ld${LINKER_SUFFIX}" \ "$LDFLAGS --fix-cortex-a53-843419" && \ LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419" ;; @@ -202,7 +202,7 @@ detect_special_flags() { detect_compiler_runtime() { test -z "$GCC" || \ - CC_RT_GCC="$(${GCC} ${CFLAGS_GCC} -print-libgcc-file-name)" + CC_RT_GCC="$(${GCC} ${CFLAGS_GCC} ${FLAGS_GCC} -print-libgcc-file-name)" if [ ${CLANG_RUNTIME} = "libgcc" ]; then CC_RT_CLANG=${CC_RT_GCC} else @@ -219,10 +219,10 @@ SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} # GCC GCC_CC_${TARCH}:=${GCC} -GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} +GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} ${FLAGS_GCC} # Generally available for GCC's cc1: GCC_CFLAGS_${TARCH}+=-fno-delete-null-pointer-checks -Wlogical-op -GCC_ADAFLAGS_${TARCH}:=${CFLAGS_GCC} +GCC_ADAFLAGS_${TARCH}:=${FLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} @@ -425,7 +425,7 @@ test_architecture() { "" "$endian" || testas "$gccprefix" "$TWIDTH" "$TBFDARCH" \ "TRUE" "$endian" ; } && \ - testcc "${gccprefix}gcc" "$CFLAGS_GCC" && \ + testcc "${gccprefix}gcc" "$CFLAGS_GCC" "$FLAGS_GCC" && \ GCCPREFIX="$gccprefix" && \ break 3 done From dc2d07cf42de41f51799b4269b15b8607c97b751 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 18 Mar 2020 09:08:11 +0100 Subject: [PATCH 0526/1463] mb/hp/z220: Fix VGA graphics init The VGA port has the DDC on port B. Select the correct Kconfig and fix graphics init failing on VGA. Tested on HP Z220, libgfxinit reports success and SeaBIOS is displayed on the connected VGA monitor. Change-Id: Ie5ec1a2d4606a21e1dc4217ff6fefe5ee35ac543 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39629 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/mainboard/hp/z220_sff_workstation/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index 8f28baf82d..82a956263c 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_NUVOTON_NPCD378 select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT + select GFX_GMA_ANALOG_I2C_HDMI_B config VBOOT select VBOOT_VBNV_CMOS From 957481c307ac8bb08489b44f52aef9ec6370df93 Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Mon, 23 Dec 2019 17:21:38 -0800 Subject: [PATCH 0527/1463] soc/intel/common: Add ACPI support for PMC core OS driver PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. This patch adds INT33A1 ACPI device to support PMC core OS driver. Any SoC that supports this feature would include this asl file to enable the support. BUG=b:146236297 BRANCH=none TEST="Build and flash volteer and verify it boots to kernel" Change-Id: Ib4edc7b636725177d508b62d15633534e9f44236 Signed-off-by: Venkata Krishna Nimmagadda Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2362512 Reviewed-by: Venkata Krishna Nimmagadda Reviewed-by: Wonkyu Kim Reviewed-by: Caveh Jalali Reviewed-by: Nick Vaccaro Tested-by: Venkata Krishna Nimmagadda Commit-Queue: Alex Levin Reviewed-on: https://review.coreboot.org/c/coreboot/+/39370 Reviewed-by: Venkata Krishna Nimmagadda Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/acpi/pmc.asl | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 src/soc/intel/common/block/acpi/acpi/pmc.asl diff --git a/src/soc/intel/common/block/acpi/acpi/pmc.asl b/src/soc/intel/common/block/acpi/acpi/pmc.asl new file mode 100644 index 0000000000..e534e8b033 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pmc.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEPD) +{ + Name (_HID, "INT33A1" /* Intel Power Engine */) + Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */) + Name (_UID, One) +} From 1fffa4ececa59f9ac11fdffd6ddaa49c693612ee Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Mon, 16 Mar 2020 10:38:50 -0700 Subject: [PATCH 0528/1463] soc/intel/tigerlake: Enable ACPI support for PMC core OS driver PMC core driver in OS provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. This patch adds INT33A1, a required ACPI device, to support that PMC core driver in tigerlake platform. BUG=b:146236297 BRANCH=none TEST="Build and flash volteer and verify it boots to kernel. Checked for valid files under /sys/kernel/debug/pmc_core." Signed-off-by: Venkata Krishna Nimmagadda Change-Id: Ib7e583dc2943461a41d2a7ebde1f16a58a118975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39587 Reviewed-by: Furquan Shaikh Reviewed-by: Venkata Krishna Nimmagadda Reviewed-by: Srinidhi N Kaushik Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi/southbridge.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index adb16aa4ba..6329340392 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -56,3 +56,6 @@ /* PCI _OSC */ #include + +/* PMC Core*/ +#include From 2144bb569df57557404bd186f53599c872e7357e Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Tue, 17 Mar 2020 16:18:27 +0900 Subject: [PATCH 0529/1463] mb/google/nightfury: Update overridetree.cb Updating devicetree to enable ELAN touchpad and ELAN touchscreen on nightfury BUG=none BRANCH=firmware-hatch-12672.B TEST=built and verified touchpad and touchscreen worked Signed-off-by: Seunghwan Kim Change-Id: Ieba6558ce3897ce2f95f51ed667465d84b4ab189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39602 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../hatch/variants/nightfury/overridetree.cb | 59 +++++++------------ 1 file changed, 21 insertions(+), 38 deletions(-) diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 0cf18e7db4..6dc3d9f9e1 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -199,47 +199,30 @@ chip soc/intel/cannonlake end device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" - register "generic.probed" = "1" - register "generic.wake" = "GPE0_DW0_21" - register "hid_desc_reg_offset" = "0x20" - device i2c 0x20 on end - end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "probed" = "1" + register "wake" = "GPE0_DW0_21" + device i2c 0x15 on end + end end # I2C 0 device pci 15.1 on - chip drivers/i2c/generic - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""atmel,maxtouch"" - register "desc" = ""Atmel Touchscreen"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "91" # 90.5 ms - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" - register "enable_delay_ms" = "1" # 90 ns - register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" - register "probed" = "1" - device i2c 4b on end - end - - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" - register "enable_delay_ms" = "10" - register "enable_off_delay_ms" = "100" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "20" - register "reset_off_delay_ms" = "2" - register "has_power_resource" = "1" - device i2c 10 on end - end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN902C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end end # I2C #1 device pci 15.2 off end # I2C #2 From 4130eb5f04ad876e8bf488935861edd6113ee98a Mon Sep 17 00:00:00 2001 From: Julien Viard de Galbert Date: Thu, 8 Mar 2018 16:57:47 +0100 Subject: [PATCH 0530/1463] soc/intel/denverton_ns: Implement AES-NI Lock Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e Signed-off-by: Julien Viard de Galbert Reviewed-on: https://review.coreboot.org/c/coreboot/+/25440 Reviewed-by: Angel Pons Reviewed-by: Steve Mooney Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/cpu.c | 7 +++++++ src/soc/intel/denverton_ns/include/soc/msr.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index e99641330a..036a47a42b 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -74,6 +74,13 @@ static void denverton_core_init(struct device *cpu) msr.lo |= FAST_STRINGS_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) { + msr = rdmsr(MSR_FEATURE_CONFIG); + msr.lo |= FEATURE_CONFIG_LOCK; /* Lock AES-NI */ + wrmsr(MSR_FEATURE_CONFIG, msr); + } + /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 7213c15a36..f7657270de 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -23,6 +23,8 @@ #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff #define IA32_MCG_CAP_CTL_P_BIT 8 From 610b3d7a33e7950e118f92588d08e8ae40cfe7da Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 18 Mar 2020 23:20:17 +0100 Subject: [PATCH 0531/1463] mb/**/gma-mainboard.ads: Remove copyright statements They are already in AUTHORS. Change-Id: I315c0c57babfa239e3d7c501a4183b8996999e6e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39659 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/asrock/b75pro3-m/gma-mainboard.ads | 2 -- src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads | 2 -- .../hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads | 2 -- .../hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads | 2 -- .../hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads | 2 -- .../hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads | 2 -- .../snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads | 2 -- src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads | 2 -- src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads | 2 -- src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads | 2 -- 10 files changed, 20 deletions(-) diff --git a/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads b/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads index e973817e22..f5736d9269 100644 --- a/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads +++ b/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Iru Cai --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads index 6d5680d6a9..c5be10f99f 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads +++ b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2018 Patrick Rudolph --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads index a272d3e0d8..4ca5343954 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Iru Cai --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads index bad712b4de..64899200ea 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Iru Cai --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads index fe4efa2468..0e264d1bd8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Iru Cai --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads index fe4efa2468..0e264d1bd8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Iru Cai --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads index fe4efa2468..0e264d1bd8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Iru Cai --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads b/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads index 6d5680d6a9..c5be10f99f 100644 --- a/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads +++ b/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2018 Patrick Rudolph --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads b/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads index 61793e295a..0e264d1bd8 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Bill XIE persmule@gmail.com --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads b/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads index 4cc7433eaf..c26e55f438 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads @@ -1,6 +1,4 @@ -- --- Copyright (C) 2017 Bill XIE persmule@gmail.com --- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or From c67e4db2dc33642a7c854507968a94eda740e161 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 18 Mar 2020 23:26:07 +0100 Subject: [PATCH 0532/1463] mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-later Change-Id: I78f06b54a6a03d565cf86f1d7bdf37965c3f6ad0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39660 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../apple/macbookair4_2/gma-mainboard.ads | 13 +------------ src/mainboard/asrock/b75pro3-m/gma-mainboard.ads | 13 ++----------- src/mainboard/asrock/g41c-gs/gma-mainboard.ads | 13 +------------ src/mainboard/asrock/h110m/gma-mainboard.ads | 14 +------------- src/mainboard/asrock/h81m-hds/gma-mainboard.ads | 14 +------------- .../asus/maximus_iv_gene-z/gma-mainboard.ads | 14 +------------- src/mainboard/asus/p5ql-em/gma-mainboard.ads | 13 +------------ src/mainboard/asus/p5qpl-am/gma-mainboard.ads | 13 +------------ src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads | 14 +------------- src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads | 14 +------------- src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads | 13 +------------ .../compulab/intense_pc/gma-mainboard.ads | 13 +------------ .../foxconn/g41s-k/variants/g41m/gma-mainboard.ads | 13 +------------ .../g41s-k/variants/g41s-k/gma-mainboard.ads | 13 +------------ .../variants/ga-b75-d3v/gma-mainboard.ads | 14 ++------------ .../variants/ga-b75m-d3v/gma-mainboard.ads | 14 ++------------ .../gigabyte/ga-g41m-es2l/gma-mainboard.ads | 13 +------------ src/mainboard/google/auron/gma-mainboard.ads | 13 +------------ src/mainboard/google/beltino/gma-mainboard.ads | 13 +------------ src/mainboard/google/butterfly/gma-mainboard.ads | 13 +------------ src/mainboard/google/eve/gma-mainboard.ads | 13 +------------ src/mainboard/google/fizz/gma-mainboard.ads | 13 +------------ src/mainboard/google/glados/gma-mainboard.ads | 13 +------------ src/mainboard/google/jecht/gma-mainboard.ads | 13 +------------ src/mainboard/google/link/gma-mainboard.ads | 11 ++--------- src/mainboard/google/parrot/gma-mainboard.ads | 13 +------------ src/mainboard/google/poppy/gma-mainboard.ads | 13 +------------ src/mainboard/google/slippy/gma-mainboard.ads | 14 ++------------ src/mainboard/google/stout/gma-mainboard.ads | 13 +------------ .../hp/compaq_8200_elite_sff/gma-mainboard.ads | 13 ++----------- .../variants/2570p/gma-mainboard.ads | 13 ++----------- .../variants/2760p/gma-mainboard.ads | 13 ++----------- .../variants/8460p/gma-mainboard.ads | 13 ++----------- .../variants/8470p/gma-mainboard.ads | 13 ++----------- .../variants/folio_9470m/gma-mainboard.ads | 13 +------------ .../variants/revolve_810_g1/gma-mainboard.ads | 13 ++----------- .../hp/z220_sff_workstation/gma-mainboard.ads | 13 ++----------- src/mainboard/intel/dg41wv/gma-mainboard.ads | 13 +------------ src/mainboard/intel/dg43gt/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/l520/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/s230u/gma-mainboard.ads | 13 +------------ .../lenovo/t400/variants/r500/gma-mainboard.ads | 13 +------------ .../variants/t400/coronado-5/gma-mainboard.ads | 13 +------------ .../t400/variants/t400/malibu-3/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/t410/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/t420s/gma-mainboard.ads | 13 +------------ .../lenovo/t430s/variants/t430s/gma-mainboard.ads | 13 ++----------- .../lenovo/t430s/variants/t431s/gma-mainboard.ads | 13 ++----------- src/mainboard/lenovo/t440p/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/t520/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/t530/gma-mainboard.ads | 13 +------------ .../lenovo/thinkcentre_a58/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/x200/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/x201/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/x220/gma-mainboard.ads | 13 +------------ src/mainboard/lenovo/x230/gma-mainboard.ads | 13 +------------ src/mainboard/packardbell/ms2290/gma-mainboard.ads | 13 +------------ src/mainboard/purism/librem_bdw/gma-mainboard.ads | 13 +------------ src/mainboard/purism/librem_skl/gma-mainboard.ads | 13 +------------ .../razer/blade_stealth_kbl/gma-mainboard.ads | 13 +------------ .../roda/rv11/variants/rv11/gma-mainboard.ads | 13 +------------ .../roda/rv11/variants/rw11/gma-mainboard.ads | 13 +------------ src/mainboard/samsung/lumpy/gma-mainboard.ads | 13 +------------ src/mainboard/samsung/stumpy/gma-mainboard.ads | 13 +------------ .../sapphire/pureplatinumh61/gma-mainboard.ads | 13 +------------ src/mainboard/up/squared/gma-mainboard.ads | 13 +------------ 66 files changed, 80 insertions(+), 784 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/gma-mainboard.ads b/src/mainboard/apple/macbookair4_2/gma-mainboard.ads index 64f6981b35..66663853e3 100644 --- a/src/mainboard/apple/macbookair4_2/gma-mainboard.ads +++ b/src/mainboard/apple/macbookair4_2/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads b/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads index f5736d9269..2ddf798a54 100644 --- a/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads +++ b/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asrock/g41c-gs/gma-mainboard.ads b/src/mainboard/asrock/g41c-gs/gma-mainboard.ads index bd14b285a9..3d8f69d651 100644 --- a/src/mainboard/asrock/g41c-gs/gma-mainboard.ads +++ b/src/mainboard/asrock/g41c-gs/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asrock/h110m/gma-mainboard.ads b/src/mainboard/asrock/h110m/gma-mainboard.ads index 1af3a93423..d4da142a09 100644 --- a/src/mainboard/asrock/h110m/gma-mainboard.ads +++ b/src/mainboard/asrock/h110m/gma-mainboard.ads @@ -1,17 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asrock/h81m-hds/gma-mainboard.ads b/src/mainboard/asrock/h81m-hds/gma-mainboard.ads index 54f85f2e95..446e94b535 100644 --- a/src/mainboard/asrock/h81m-hds/gma-mainboard.ads +++ b/src/mainboard/asrock/h81m-hds/gma-mainboard.ads @@ -1,17 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads b/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads index 393d1a1822..33eda31b78 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads +++ b/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads @@ -1,17 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asus/p5ql-em/gma-mainboard.ads b/src/mainboard/asus/p5ql-em/gma-mainboard.ads index 43a7d89a3a..f3178a8188 100644 --- a/src/mainboard/asus/p5ql-em/gma-mainboard.ads +++ b/src/mainboard/asus/p5ql-em/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asus/p5qpl-am/gma-mainboard.ads b/src/mainboard/asus/p5qpl-am/gma-mainboard.ads index bd14b285a9..3d8f69d651 100644 --- a/src/mainboard/asus/p5qpl-am/gma-mainboard.ads +++ b/src/mainboard/asus/p5qpl-am/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads index a161d2d22a..3d8f69d651 100644 --- a/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads +++ b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads @@ -1,17 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads index 9e6cb3e51f..d0e08906a7 100644 --- a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads +++ b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads @@ -1,17 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads index 37135f9174..8507ff77cc 100644 --- a/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads +++ b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/compulab/intense_pc/gma-mainboard.ads b/src/mainboard/compulab/intense_pc/gma-mainboard.ads index 816a87d1a2..95a3e3b873 100644 --- a/src/mainboard/compulab/intense_pc/gma-mainboard.ads +++ b/src/mainboard/compulab/intense_pc/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads b/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads index 0bf1021b0a..e737c0889d 100644 --- a/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads +++ b/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads b/src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads index bd14b285a9..3d8f69d651 100644 --- a/src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads +++ b/src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads index 93f8e37f49..2274e989b0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads @@ -1,15 +1,5 @@ --- --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads index 93f8e37f49..2274e989b0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads @@ -1,15 +1,5 @@ --- --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/gma-mainboard.ads b/src/mainboard/gigabyte/ga-g41m-es2l/gma-mainboard.ads index bd14b285a9..3d8f69d651 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-g41m-es2l/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/auron/gma-mainboard.ads b/src/mainboard/google/auron/gma-mainboard.ads index 79ca0075f2..d71ed93690 100644 --- a/src/mainboard/google/auron/gma-mainboard.ads +++ b/src/mainboard/google/auron/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/beltino/gma-mainboard.ads b/src/mainboard/google/beltino/gma-mainboard.ads index 3a92b599ff..43e9edf2eb 100644 --- a/src/mainboard/google/beltino/gma-mainboard.ads +++ b/src/mainboard/google/beltino/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/butterfly/gma-mainboard.ads b/src/mainboard/google/butterfly/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/google/butterfly/gma-mainboard.ads +++ b/src/mainboard/google/butterfly/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/eve/gma-mainboard.ads b/src/mainboard/google/eve/gma-mainboard.ads index 52f6783ddb..45ce538ec4 100644 --- a/src/mainboard/google/eve/gma-mainboard.ads +++ b/src/mainboard/google/eve/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/fizz/gma-mainboard.ads b/src/mainboard/google/fizz/gma-mainboard.ads index e47ea7eab3..12f9d2b4c6 100644 --- a/src/mainboard/google/fizz/gma-mainboard.ads +++ b/src/mainboard/google/fizz/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/glados/gma-mainboard.ads b/src/mainboard/google/glados/gma-mainboard.ads index 52f6783ddb..45ce538ec4 100644 --- a/src/mainboard/google/glados/gma-mainboard.ads +++ b/src/mainboard/google/glados/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/jecht/gma-mainboard.ads b/src/mainboard/google/jecht/gma-mainboard.ads index 3a92b599ff..43e9edf2eb 100644 --- a/src/mainboard/google/jecht/gma-mainboard.ads +++ b/src/mainboard/google/jecht/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/link/gma-mainboard.ads b/src/mainboard/google/link/gma-mainboard.ads index fae0b5b06e..fec522e473 100644 --- a/src/mainboard/google/link/gma-mainboard.ads +++ b/src/mainboard/google/link/gma-mainboard.ads @@ -1,12 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/parrot/gma-mainboard.ads b/src/mainboard/google/parrot/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/google/parrot/gma-mainboard.ads +++ b/src/mainboard/google/parrot/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/poppy/gma-mainboard.ads b/src/mainboard/google/poppy/gma-mainboard.ads index 52f6783ddb..45ce538ec4 100644 --- a/src/mainboard/google/poppy/gma-mainboard.ads +++ b/src/mainboard/google/poppy/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/slippy/gma-mainboard.ads b/src/mainboard/google/slippy/gma-mainboard.ads index 4d1b6c0248..3932e33993 100644 --- a/src/mainboard/google/slippy/gma-mainboard.ads +++ b/src/mainboard/google/slippy/gma-mainboard.ads @@ -1,15 +1,5 @@ --- --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/google/stout/gma-mainboard.ads b/src/mainboard/google/stout/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/google/stout/gma-mainboard.ads +++ b/src/mainboard/google/stout/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads index c5be10f99f..27976ed6dd 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads +++ b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads index 4ca5343954..a7dd834ee9 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads index 64899200ea..ae8d69f3b5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads index 0e264d1bd8..fae354437d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads index 0e264d1bd8..fae354437d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads index 0e264d1bd8..fae354437d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads b/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads index c5be10f99f..27976ed6dd 100644 --- a/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads +++ b/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/intel/dg41wv/gma-mainboard.ads b/src/mainboard/intel/dg41wv/gma-mainboard.ads index bd14b285a9..3d8f69d651 100644 --- a/src/mainboard/intel/dg41wv/gma-mainboard.ads +++ b/src/mainboard/intel/dg41wv/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/intel/dg43gt/gma-mainboard.ads b/src/mainboard/intel/dg43gt/gma-mainboard.ads index 43a7d89a3a..f3178a8188 100644 --- a/src/mainboard/intel/dg43gt/gma-mainboard.ads +++ b/src/mainboard/intel/dg43gt/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/l520/gma-mainboard.ads b/src/mainboard/lenovo/l520/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/lenovo/l520/gma-mainboard.ads +++ b/src/mainboard/lenovo/l520/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/s230u/gma-mainboard.ads b/src/mainboard/lenovo/s230u/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/lenovo/s230u/gma-mainboard.ads +++ b/src/mainboard/lenovo/s230u/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads index 3623d623f4..ae8d69f3b5 100644 --- a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads index 9bf6352f7b..1877ffa24f 100644 --- a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads index 9ab80b59dd..a6985ca419 100644 --- a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t410/gma-mainboard.ads b/src/mainboard/lenovo/t410/gma-mainboard.ads index b75db6c693..cc92af10e4 100644 --- a/src/mainboard/lenovo/t410/gma-mainboard.ads +++ b/src/mainboard/lenovo/t410/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t420s/gma-mainboard.ads b/src/mainboard/lenovo/t420s/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/lenovo/t420s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420s/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads b/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads index 0e264d1bd8..fae354437d 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430s/variants/t430s/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads b/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads index c26e55f438..66663853e3 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430s/variants/t431s/gma-mainboard.ads @@ -1,14 +1,5 @@ --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t440p/gma-mainboard.ads b/src/mainboard/lenovo/t440p/gma-mainboard.ads index 1626f88f5a..2f914ca9f8 100644 --- a/src/mainboard/lenovo/t440p/gma-mainboard.ads +++ b/src/mainboard/lenovo/t440p/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t520/gma-mainboard.ads b/src/mainboard/lenovo/t520/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/lenovo/t520/gma-mainboard.ads +++ b/src/mainboard/lenovo/t520/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t530/gma-mainboard.ads b/src/mainboard/lenovo/t530/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/lenovo/t530/gma-mainboard.ads +++ b/src/mainboard/lenovo/t530/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/thinkcentre_a58/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_a58/gma-mainboard.ads index bd14b285a9..3d8f69d651 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/gma-mainboard.ads +++ b/src/mainboard/lenovo/thinkcentre_a58/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/x200/gma-mainboard.ads b/src/mainboard/lenovo/x200/gma-mainboard.ads index 9ab80b59dd..a6985ca419 100644 --- a/src/mainboard/lenovo/x200/gma-mainboard.ads +++ b/src/mainboard/lenovo/x200/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/x201/gma-mainboard.ads b/src/mainboard/lenovo/x201/gma-mainboard.ads index b75db6c693..cc92af10e4 100644 --- a/src/mainboard/lenovo/x201/gma-mainboard.ads +++ b/src/mainboard/lenovo/x201/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/x220/gma-mainboard.ads b/src/mainboard/lenovo/x220/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/lenovo/x220/gma-mainboard.ads +++ b/src/mainboard/lenovo/x220/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/x230/gma-mainboard.ads b/src/mainboard/lenovo/x230/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/lenovo/x230/gma-mainboard.ads +++ b/src/mainboard/lenovo/x230/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/packardbell/ms2290/gma-mainboard.ads b/src/mainboard/packardbell/ms2290/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/packardbell/ms2290/gma-mainboard.ads +++ b/src/mainboard/packardbell/ms2290/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/purism/librem_bdw/gma-mainboard.ads b/src/mainboard/purism/librem_bdw/gma-mainboard.ads index 750e46ec10..1b814a7caa 100644 --- a/src/mainboard/purism/librem_bdw/gma-mainboard.ads +++ b/src/mainboard/purism/librem_bdw/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/purism/librem_skl/gma-mainboard.ads b/src/mainboard/purism/librem_skl/gma-mainboard.ads index 750e46ec10..1b814a7caa 100644 --- a/src/mainboard/purism/librem_skl/gma-mainboard.ads +++ b/src/mainboard/purism/librem_skl/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads index 82c66e0035..dd5fe18690 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads +++ b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads b/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads index bde759f752..94164a1999 100644 --- a/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads +++ b/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads index fe7487500b..c5b0ec861a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads +++ b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/samsung/lumpy/gma-mainboard.ads b/src/mainboard/samsung/lumpy/gma-mainboard.ads index 105b231e4f..fae354437d 100644 --- a/src/mainboard/samsung/lumpy/gma-mainboard.ads +++ b/src/mainboard/samsung/lumpy/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/samsung/stumpy/gma-mainboard.ads b/src/mainboard/samsung/stumpy/gma-mainboard.ads index 816a87d1a2..95a3e3b873 100644 --- a/src/mainboard/samsung/stumpy/gma-mainboard.ads +++ b/src/mainboard/samsung/stumpy/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads b/src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads index e830f05148..bd4e580fa1 100644 --- a/src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads +++ b/src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/up/squared/gma-mainboard.ads b/src/mainboard/up/squared/gma-mainboard.ads index 6865970e16..bffb310bf0 100644 --- a/src/mainboard/up/squared/gma-mainboard.ads +++ b/src/mainboard/up/squared/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; From 64402bbeb853a180ff84cdfafe45369dfb0d55fa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 18 Mar 2020 23:29:21 +0100 Subject: [PATCH 0533/1463] mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-only Change-Id: I005bf205142d4d8c5e12378f33d2100d278fa174 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39661 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/asus/h61m-cs/gma-mainboard.ads | 13 +------------ src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads | 13 +------------ .../variants/ga-b75m-d3h/gma-mainboard.ads | 12 +----------- .../gigabyte/ga-h61m-s2pv/gma-mainboard.ads | 13 +------------ src/mainboard/intel/dcp847ske/gma-mainboard.ads | 12 +----------- src/mainboard/kontron/ktqm77/gma-mainboard.ads | 12 +----------- src/mainboard/lenovo/t420/gma-mainboard.ads | 12 +----------- src/mainboard/lenovo/t430/gma-mainboard.ads | 12 +----------- src/mainboard/lenovo/x131e/gma-mainboard.ads | 12 +----------- .../lenovo/x1_carbon_gen1/gma-mainboard.ads | 11 +---------- 10 files changed, 10 insertions(+), 112 deletions(-) diff --git a/src/mainboard/asus/h61m-cs/gma-mainboard.ads b/src/mainboard/asus/h61m-cs/gma-mainboard.ads index 8544f77be9..8fed900af9 100644 --- a/src/mainboard/asus/h61m-cs/gma-mainboard.ads +++ b/src/mainboard/asus/h61m-cs/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; version 2 of the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads index 4e89f3af5d..d30ada82c5 100644 --- a/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads +++ b/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; version 2 of the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads index aabf78fa7a..d6140ee457 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads @@ -1,15 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or --- modify it under the terms of the GNU General Public License as --- published by the Free Software Foundation; version 2 of --- the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads index 98b462a2b9..daa6c0f877 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads @@ -1,16 +1,5 @@ --- +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; version 2 of the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/intel/dcp847ske/gma-mainboard.ads b/src/mainboard/intel/dcp847ske/gma-mainboard.ads index 4a7a7ac5b8..76effb1080 100644 --- a/src/mainboard/intel/dcp847ske/gma-mainboard.ads +++ b/src/mainboard/intel/dcp847ske/gma-mainboard.ads @@ -1,15 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- --- This program is free software; you can redistribute it and/or --- modify it under the terms of the GNU General Public License as --- published by the Free Software Foundation; version 2 of --- the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/kontron/ktqm77/gma-mainboard.ads b/src/mainboard/kontron/ktqm77/gma-mainboard.ads index 3ac3cd2769..b47201622a 100644 --- a/src/mainboard/kontron/ktqm77/gma-mainboard.ads +++ b/src/mainboard/kontron/ktqm77/gma-mainboard.ads @@ -1,15 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or --- modify it under the terms of the GNU General Public License as --- published by the Free Software Foundation; version 2 of --- the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index eb0936d810..a26b993127 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -1,15 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or --- modify it under the terms of the GNU General Public License as --- published by the Free Software Foundation; version 2 of --- the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads index eb0936d810..a26b993127 100644 --- a/src/mainboard/lenovo/t430/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430/gma-mainboard.ads @@ -1,15 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or --- modify it under the terms of the GNU General Public License as --- published by the Free Software Foundation; version 2 of --- the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/x131e/gma-mainboard.ads b/src/mainboard/lenovo/x131e/gma-mainboard.ads index cd3b98d01d..7a4edf1d57 100644 --- a/src/mainboard/lenovo/x131e/gma-mainboard.ads +++ b/src/mainboard/lenovo/x131e/gma-mainboard.ads @@ -1,15 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or --- modify it under the terms of the GNU General Public License as --- published by the Free Software Foundation; version 2 of --- the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads b/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads index c9a3d47e8e..229cf6e23d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads +++ b/src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads @@ -1,14 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or --- modify it under the terms of the GNU General Public License as --- published by the Free Software Foundation; version 2 of --- the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; From 3d5d6e8dc7f95d9bcf55ad0c67bd9b6d458c43dd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 18 Mar 2020 23:55:36 +0100 Subject: [PATCH 0534/1463] util/autoport: Emit SPDX license headers Change-Id: I8896b6c92c3126cc611e47b39d596108b90c6bf2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- util/autoport/main.go | 36 +++++------------------------------- 1 file changed, 5 insertions(+), 31 deletions(-) diff --git a/util/autoport/main.go b/util/autoport/main.go index e3c3fdfa06..9e62b565da 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -212,25 +212,10 @@ func Create(ctx Context, name string) *os.File { return mf } -func Add_gpl(fp *os.File) { - fp.WriteString(`/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -`) +func Add_gpl(f *os.File) { + fmt.Fprintln(f, "/* SPDX-License-Identifier: GPL-2.0-only */") + fmt.Fprintln(f, "/* This file is part of the coreboot project. */") + fmt.Fprintln(f) } func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { @@ -900,19 +885,8 @@ DefinitionBlock( gma := Create(ctx, "gma-mainboard.ads") defer gma.Close() - gma.WriteString(`-- + gma.WriteString(`-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; From 78b43c8990a7e3331dd5a0bd2484a53956f546aa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 17 Mar 2020 23:55:18 +0100 Subject: [PATCH 0535/1463] nb/intel/sandybridge: Always write to PEGCTL This register needs to be written to once to lock it down. Do so. Change-Id: I04bd496d064940b51cb9aa1ded6f5b8853ea7334 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39624 Reviewed-by: Arthur Heymans Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/northbridge.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 23c1489acb..abfc1259de 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -377,11 +377,12 @@ static void disable_peg(void) /* * Set the PEG clock gating bit. Disables the IO clock on all PEG devices. * - * FIXME: If not clock gating, this register still needs to be written to once, - * to lock it down. Also, never clock gate on Ivy Bridge stepping A0! + * FIXME: Never clock gate on Ivy Bridge stepping A0! */ MCHBAR32_OR(PEGCTL, 1); printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); + } else { + MCHBAR32_AND(PEGCTL, ~1); } } From 70ea3b9141ee92177c1a1185a7e6a468fd59bc85 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 18 Mar 2020 23:45:32 -0500 Subject: [PATCH 0536/1463] ec/google/chromeec: don't put empty block in SSDT Check that there are actually USB-PD ports for which to add data to SSDT, before actually generating SSDT data. This prevents an empty scope from being generated on devices without any USB-PD ports, which was breaking parsing/decompilation on some older platforms (eg, Braswell). Test: build/boot google/edgar, verify SSDT table able to be parsed via iasl after dumping. Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39665 Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec_acpi.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 4dfd44bf4e..47d60d5b75 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -177,19 +177,14 @@ static void add_usb_port_references(struct acpi_dp *dsd, int port_number) } } -static void fill_ssdt_typec_device(struct device *dev) +static void fill_ssdt_typec_device(int num_ports) { struct usb_pd_port_caps port_caps; char con_name[] = "CONx"; struct acpi_dp *dsd; - int num_ports; int rv; int i; - rv = google_chromeec_get_num_pd_ports(&num_ports); - if (rv) - return; - acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " @@ -220,8 +215,12 @@ static void fill_ssdt_typec_device(struct device *dev) void google_chromeec_fill_ssdt_generator(struct device *dev) { + int num_ports; + if (google_chromeec_get_num_pd_ports(&num_ports)) + return; + /* Reference the existing device's scope */ acpigen_write_scope(acpi_device_path(dev)); - fill_ssdt_typec_device(dev); + fill_ssdt_typec_device(num_ports); acpigen_pop_len(); /* Scope */ } From 12b835050f0af9341b257560b60a8060c8fad328 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 10 Mar 2020 17:50:28 -0700 Subject: [PATCH 0537/1463] soc/intel: Enable GPIO functions in verstage Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 9d8fa6f692..e7169cff42 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -58,6 +58,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +verstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c CPPFLAGS_common += -I$(src)/soc/intel/tigerlake CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include From a1c82c5ebee830fa28a1962618bba4946e68f3ba Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 16 Mar 2020 18:57:48 +0530 Subject: [PATCH 0538/1463] drivers/generic/max98357a: Allow custom _HID from config Add HID field in max98357a_config and allow mainboards to set it. Signed-off-by: Aamir Bohra Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286 Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/drivers/generic/max98357a/chip.h | 4 ++++ src/drivers/generic/max98357a/max98357a.c | 9 +++++++-- src/mainboard/google/fizz/variants/karma/overridetree.cb | 1 + src/mainboard/google/glados/variants/asuka/devicetree.cb | 1 + src/mainboard/google/glados/variants/cave/devicetree.cb | 1 + src/mainboard/google/glados/variants/lars/devicetree.cb | 1 + .../google/glados/variants/sentry/devicetree.cb | 1 + .../google/hatch/variants/akemi/overridetree.cb | 1 + .../google/hatch/variants/dratini/overridetree.cb | 1 + .../google/hatch/variants/hatch/overridetree.cb | 1 + .../hatch/variants/helios_diskswap/overridetree.cb | 1 + .../google/hatch/variants/jinlon/overridetree.cb | 1 + .../google/hatch/variants/kindred/overridetree.cb | 1 + .../google/hatch/variants/kohaku/overridetree.cb | 1 + .../google/hatch/variants/mushu/overridetree.cb | 1 + .../google/hatch/variants/nightfury/overridetree.cb | 1 + .../google/hatch/variants/palkia/overridetree.cb | 1 + .../google/hatch/variants/stryke/overridetree.cb | 1 + .../google/kahlee/variants/aleena/devicetree.cb | 1 + .../google/kahlee/variants/careena/devicetree.cb | 1 + src/mainboard/google/kahlee/variants/grunt/devicetree.cb | 1 + src/mainboard/google/kahlee/variants/liara/devicetree.cb | 1 + .../google/kahlee/variants/nuwani/devicetree.cb | 1 + .../google/kahlee/variants/treeya/devicetree.cb | 1 + .../google/octopus/variants/baseboard/devicetree.cb | 1 + src/mainboard/google/poppy/variants/nami/devicetree.cb | 1 + .../google/poppy/variants/nautilus/devicetree.cb | 1 + .../google/reef/variants/baseboard/devicetree.cb | 1 + src/mainboard/google/reef/variants/coral/devicetree.cb | 1 + src/mainboard/google/reef/variants/pyro/devicetree.cb | 1 + src/mainboard/google/reef/variants/sand/devicetree.cb | 1 + src/mainboard/google/reef/variants/snappy/devicetree.cb | 1 + .../google/volteer/variants/baseboard/devicetree.cb | 1 + .../intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 1 + .../intel/glkrvp/variants/baseboard/devicetree.cb | 1 + src/mainboard/intel/kunimitsu/devicetree.cb | 1 + 36 files changed, 45 insertions(+), 2 deletions(-) diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h index ec4e94f3e6..f956846b60 100644 --- a/src/drivers/generic/max98357a/chip.h +++ b/src/drivers/generic/max98357a/chip.h @@ -14,6 +14,10 @@ #include struct drivers_generic_max98357a_config { + + /* ACPI _HID */ + const char *hid; + /* SDMODE GPIO */ struct acpi_gpio sdmode_gpio; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 2b0ec3ba04..56fd26c3fd 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -23,7 +23,6 @@ #if CONFIG(HAVE_ACPI_TABLES) #define MAX98357A_ACPI_NAME "MAXM" -#define MAX98357A_ACPI_HID "MX98357A" static void max98357a_fill_ssdt(struct device *dev) { @@ -42,7 +41,13 @@ static void max98357a_fill_ssdt(struct device *dev) /* Device */ acpigen_write_scope(scope); acpigen_write_device(name); - acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); + + if (!config->hid) { + printk(BIOS_ERR, "%s: ERROR: _HID required\n", dev_path(dev)); + return; + } + + acpigen_write_name_string("_HID", config->hid); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index 0273f78efd..f978240323 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -58,6 +58,7 @@ chip soc/intel/skylake end # USB xHCI device pci 19.1 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index 27bbebaa57..772584dc3c 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -269,6 +269,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 22ee80f56d..1d04a8e714 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -284,6 +284,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 503cf5a58d..76e614d423 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -267,6 +267,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 4c6bbf817a..3e2137bb58 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -290,6 +290,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" register "device_present_gpio" = "GPP_E3" register "device_present_gpio_invert" = "1" diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index d236cb0c94..27d11ccfb1 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -236,6 +236,7 @@ chip soc/intel/cannonlake device pci 1e.3 off end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 5c30a5a93f..0bd3d8ee93 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -170,6 +170,7 @@ chip soc/intel/cannonlake end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index c623fde5ba..a92ef9b899 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -178,6 +178,7 @@ chip soc/intel/cannonlake end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 22534f32f9..8a3745d174 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -207,6 +207,7 @@ chip soc/intel/cannonlake end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index f7ca7d5c39..7cf434dd91 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -178,6 +178,7 @@ chip soc/intel/cannonlake end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 5067991088..8afae3968b 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -199,6 +199,7 @@ chip soc/intel/cannonlake device pci 1e.3 off end # GSPI #1 unused device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index ce8746932d..6a5ce7c004 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -261,6 +261,7 @@ chip soc/intel/cannonlake end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index f50bab248d..0c8cb5369e 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -193,6 +193,7 @@ chip soc/intel/cannonlake end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 6dc3d9f9e1..a35e99df99 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -255,6 +255,7 @@ chip soc/intel/cannonlake device pci 1e.3 off end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index 0792b9607d..bce58011d3 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -183,6 +183,7 @@ chip soc/intel/cannonlake device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index 796e589070..329efa3b2a 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -212,6 +212,7 @@ chip soc/intel/cannonlake device pci 1e.3 off end # GSPI #1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index cf0978fa5f..864e0cd92a 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -118,6 +118,7 @@ chip soc/amd/stoneyridge device i2c 1a on end end chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" register "sdmode_delay" = "5" device generic 0.1 on end diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index ac07aa1e93..6c28d0ffc0 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -119,6 +119,7 @@ chip soc/amd/stoneyridge device i2c 1a on end end chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" register "sdmode_delay" = "5" device generic 0.1 on end diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 18053d782f..efa4066346 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -118,6 +118,7 @@ chip soc/amd/stoneyridge device i2c 1a on end end chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" register "sdmode_delay" = "5" device generic 0.1 on end diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 7dd34f3465..0983f7955e 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -118,6 +118,7 @@ chip soc/amd/stoneyridge device i2c 1a on end end chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" register "sdmode_delay" = "5" device generic 0.1 on end diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index 6828d363c3..efe92f723e 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -121,6 +121,7 @@ chip soc/amd/stoneyridge device i2c 1a on end end chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" register "sdmode_delay" = "5" device generic 0.1 on end diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index f92767ff27..efc384fea9 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -121,6 +121,7 @@ chip soc/amd/stoneyridge device i2c 1a on end end chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" register "sdmode_delay" = "5" device generic 0.1 on end diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 5404531c8f..9253f11372 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -122,6 +122,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 3d37eda207..1b3fdcc410 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -401,6 +401,7 @@ chip soc/intel/skylake end # I2C #2 device pci 15.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ef5e8ad921..66ceb2d3ac 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -365,6 +365,7 @@ chip soc/intel/skylake device pci 19.0 on end # UART #2 device pci 19.1 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index da842ba6e6..cbc2e22d37 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -131,6 +131,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 1608343d3c..00e63bc94c 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -131,6 +131,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index c2d67aa17e..f62af8a39a 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -140,6 +140,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 68f33ae074..b62704a8f5 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -127,6 +127,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index aaf61de6ae..4edf739805 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -136,6 +136,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 84d121f2b1..6be69fe2ee 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -363,6 +363,7 @@ chip soc/intel/tigerlake device pci 1f.2 on end # PMC 0xA0A1 device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index a6d329be82..53c677b64e 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -166,6 +166,7 @@ chip soc/intel/cannonlake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index c5ad27dca6..361a4a30b8 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -112,6 +112,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_160)" register "sdmode_delay" = "5" device generic 0 on end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ea3578550c..ab306149de 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -289,6 +289,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a + register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" register "device_present_gpio" = "GPP_E3" register "device_present_gpio_invert" = "1" From bf48f6ab1127f3ba6a592f17ec49255f3eea5ffd Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 16 Mar 2020 19:03:46 +0530 Subject: [PATCH 0539/1463] mb/google/dedede Add Audio support for waddledoo 1. Configure Audio GPIOs. 2. Set i2c4 configuration. 3. Update PCH HDA configuration TEST=Verify codecs gets listed with aplay -l command. Signed-off-by: Aamir Bohra Signed-off-by: Yong Zhi Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39285 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/Kconfig.name | 2 ++ .../dedede/variants/baseboard/devicetree.cb | 8 +++++ .../google/dedede/variants/baseboard/gpio.c | 34 ++++++++++--------- .../dedede/variants/waddledoo/overridetree.cb | 33 +++++++++++++++++- 4 files changed, 60 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index d083d2dd8a..36c2467055 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -9,6 +9,8 @@ config BOARD_GOOGLE_WADDLEDOO select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index ece9672ae8..865d4ea73c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -103,6 +103,14 @@ chip soc/intel/tigerlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + # Audio related configurations + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 390910470e..bdc3de4f70 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -178,11 +178,11 @@ static const struct pad_config gpio_table[] = { /* D15 : UCAM_RST_L */ PAD_NC(GPP_D15, NONE), /* D16 : HP_INT_ODL */ - PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), /* D17 : EN_SPK */ - PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D17, 1, PLTRST), /* D18 : I2S_MCLK */ - PAD_NC(GPP_D18, NONE), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* D19 : WWAN_WLAN_COEX1 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : WWAN_WLAN_COEX2 */ @@ -319,7 +319,7 @@ static const struct pad_config gpio_table[] = { /* H14 : GPP_H14/AVS_I2S2_RXD */ PAD_NC(GPP_H14, NONE), /* H15 : I2S_SPK_BCLK */ - PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* H16 : AP_SUB_IO_L */ PAD_NC(GPP_H16, NONE), /* H17 : WWAN_RST_L */ @@ -330,38 +330,40 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H19, 1, DEEP), /* R0 : I2S_HP_BCLK */ - PAD_NC(GPP_R0, NONE), + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* R1 : I2S_HP_LRCK */ - PAD_NC(GPP_R1, NONE), + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* R2 : I2S_HP_AUDIO */ - PAD_NC(GPP_R2, NONE), + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), /* R3 : I2S_HP_MIC */ - PAD_NC(GPP_R3, NONE), + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* R4 : GPP_R04/HDA_RST_N */ PAD_NC(GPP_R4, NONE), /* R5 : GPP_R05/HDA_SDI1/AVS_I2S1_RXD */ PAD_NC(GPP_R5, NONE), /* R6 : I2S_SPK_LRCK */ - PAD_NC(GPP_R6, NONE), - /* R7 : I2S_SPK_AUDIO */ - PAD_NC(GPP_R7, NONE), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), + /* R7 : I2S_SPK_AUDIO */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), + /* S0 : RAM_STRAP_4 */ PAD_NC(GPP_S0, NONE), /* S1 : RSVD_STRAP */ PAD_NC(GPP_S1, NONE), /* S2 : DMIC1_CLK */ - PAD_NC(GPP_S2, NONE), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* S3 : DMIC1_DATA */ - PAD_NC(GPP_S3, NONE), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* S4 : GPP_S04/SNDW1_CLK */ PAD_NC(GPP_S4, NONE), /* S5 : GPP_S05/SNDW1_DATA */ PAD_NC(GPP_S5, NONE), - /* S6 : DMIC0_CLK */ - PAD_NC(GPP_S6, NONE), + /* S6 : DMIC0_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* S7 : DMIC0_DATA */ - PAD_NC(GPP_S7, NONE), + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + /* GPD0 : AP_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 9860e3de46..884199c4c5 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -36,6 +36,12 @@ chip soc/intel/tigerlake }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } }, }" device domain 0 on @@ -49,12 +55,37 @@ chip soc/intel/tigerlake device i2c 15 on end end end #I2C 0 - device pci 1c.7 on chip drivers/intel/wifi register "wake" = "GPE0_DW2_03" device pci 00.0 on end end end # PCI Express Root Port 8 - WLAN + device pci 19.0 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA end end From 59e6f3c6e355a93f7eb7c6f919b62874f97ff3ec Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 9 Mar 2020 10:15:39 +0100 Subject: [PATCH 0540/1463] util/scripts/gerrit-rebase: Fix shell invocation The single apostrophe confuses the shell that's calling the command. Change-Id: I7d3183e9a612de0121b2d208c06a45645b8d67f6 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39397 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- util/scripts/gerrit-rebase | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/scripts/gerrit-rebase b/util/scripts/gerrit-rebase index d051103b60..27ee3c7842 100755 --- a/util/scripts/gerrit-rebase +++ b/util/scripts/gerrit-rebase @@ -71,7 +71,7 @@ to_matches="$(git log ${common_base}..${to} | \ cut -d: -f2-)" # start rebase process, but fail immediately by enforcing an invalid todo -GIT_SEQUENCE_EDITOR="echo Ignore this error, it's intentional>" \ +GIT_SEQUENCE_EDITOR="echo 'Ignore this error, it works around a git-rebase limitation'>" \ git rebase -i --onto ${to} ${from} ${to} 2>/dev/null # write new rebase todo From 903d9a225e3e0b03824daf6718936851c51e0664 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 11 Feb 2020 14:38:18 +0100 Subject: [PATCH 0541/1463] Documentation: Add new GSoC projects Change-Id: I5d67361286da04819def3227b2c6cb41a063fc5b Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38829 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/contributing/project_ideas.md | 63 +++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2c621f410d..141023fd3d 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -184,3 +184,66 @@ build a payload around it. ### Mentors * TODO + +## Fix POST code handling +coreboot supports writing POST codes to I/O port 80. +There are various Kconfigs that deal with POST codes, which don't have +effect on most platforms. +The code to send POST codes is scattered in C and Assembly, some use +functions, some use macros and others simply use the `outb` instruction. +The POST codes are duplicated between stages and aren't documented properly. + + +Tasks: +* Guard Kconfigs with a *depends on* to only show on supported platforms +* Remove duplicated Kconfigs +* Replace `outb(0x80, ...)` with calls to `post_code(...)` +* Update Documentation/POSTCODES +* Use defines from console/post_codes.h where possible +* Drop duplicated POST codes +* Make use of all possible 255 values + +### Requirements +* knowledge in the coreboot build system and the concept of stages +* other knowledge: Little experience with C and x86 Assembly +* hardware requirements: Nothing special + +### Mentors +* Patrick Rudolph +* Christian Walter + +## Board status replacement +The [Board status page](https://coreboot.org/status/board-status.html) allows +to see last working commit of a board. The page is generated by a cron job +that runs on a huge git repository. + +Build an open source replacement written in Golang using existing tools +and libraries, consisting of a backend, a frontend and client side +scripts. The backend should connect to an SQL database with can be +controlled using a RESTful API. The RESTful API should have basic authentication +for managment tasks and new board status uploads. + +At least one older test result should be keept in the database. + +The frontend should use established UI libraries or frameworks (for example +Angular) to display the current board status, that is if it's working or not +and some details provided with the last test. If a board isn't working the last +working commit (if any) should be shown in addition to the broken one. + +Provide a script/tool that allows to: +1. Push mainboard details from coreboot master CI +2. Push mainboard test results from authenticated users containing + * working + * commit hash + * bootlog (if any) + * dmesg (if it's booting) + * timestamps (if it's booting) + * coreboot config + +### Requirements +* coreboot knowledge: Non-technical, needed to perform requirements analysis +* software knowledge: Golang, SQL for the backend, JS for the frontend + +### Mentors +* Patrick Rudolph +* Christian Walter From 064c7999ae5bab4a29d4ee299f6a8c6a97a5da66 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 17 Mar 2020 23:09:16 +0100 Subject: [PATCH 0542/1463] nb/intel/sandybridge: Deduplicate report_memory_config Use the version from native raminit, as it takes the reference clock into account. Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/raminit.c | 50 -------------- .../intel/sandybridge/raminit_mrc.c | 47 ------------- .../intel/sandybridge/raminit_shared.c | 68 +++++++++++++++++++ .../intel/sandybridge/sandybridge.h | 1 + 5 files changed, 70 insertions(+), 97 deletions(-) create mode 100644 src/northbridge/intel/sandybridge/raminit_shared.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 5fb9fdbc9a..7718bf9acd 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -29,6 +29,7 @@ ramstage-y += common.c romstage-y += common.c smm-y += common.c +romstage-y += raminit_shared.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c romstage-y += raminit.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index ca78eb3a64..34fb499599 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -38,13 +38,6 @@ /* FIXME: no ECC support */ /* FIXME: no support for 3-channel chipsets */ -static const char *ecc_decoder[] = { - "inactive", - "active on IO", - "disabled on IO", - "active", -}; - static void wait_txt_clear(void) { struct cpuid_result cp = cpuid_ext(1, 0); @@ -90,49 +83,6 @@ static void fill_smbios17(ramctr_timing *ctrl) } } -#define ON_OFF(val) (((val) & 1) ? "on" : "off") - -/* Print the memory controller configuration as read from the memory controller registers. */ -static void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; - int i; - - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - - const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; - - printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); - - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - (addr_decoder_common >> 0) & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); - printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} -#undef ON_OFF - /* Return CRC16 match for all SPDs */ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 5b4b46c583..6d00afa6cb 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -126,53 +126,6 @@ static void prepare_mrc_cache(struct pei_data *pei_data) pei_data->mrc_input_len); } -static const char *ecc_decoder[] = { - "inactive", - "active on IO", - "disabled on IO", - "active", -}; - -#define ON_OFF(val) (((val) & 1) ? "on" : "off") - -/* Print the memory controller configuration as read from the memory controller registers. */ -static void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); - - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - (addr_decoder_common >> 0) & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); - printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} -#undef ON_OFF - /** * Find PEI executable in coreboot filesystem and execute it. * diff --git a/src/northbridge/intel/sandybridge/raminit_shared.c b/src/northbridge/intel/sandybridge/raminit_shared.c new file mode 100644 index 0000000000..6162544bdc --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_shared.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "sandybridge.h" + +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active", +}; + +#define ON_OFF(val) (((val) & 1) ? "on" : "off") + +/* Print the memory controller configuration as read from the memory controller registers. */ +void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + + const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + + printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); + + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + (addr_decoder_common >> 0) & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); + printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); + printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} +#undef ON_OFF diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 07d790430f..8fb72ccbf8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -236,6 +236,7 @@ void early_init_dmi(void); void mainboard_early_init(int s3resume); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); +void report_memory_config(void); enum platform_type get_platform_type(void); #include From 8ca1ada083e9029defb2d40f33702bd2553d113f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 21:17:21 +0100 Subject: [PATCH 0543/1463] util/inteltool: powermgt: add code for dumping config registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the code required to dump config registers. Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39509 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- util/inteltool/powermgt.c | 43 +++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 70f8c48f0d..125c7396ec 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -670,12 +670,14 @@ static const io_register_t i63xx_pm_registers[] = { int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) { size_t i, pm_registers_size = 0; + size_t pm_cfg_registers_size = 0; uint16_t pmbase; const io_register_t *pm_registers; + const io_register_t *pm_cfg_registers; uint64_t pwrmbase_phys = 0; - struct pci_dev *acpi; + struct pci_dev *acpi = NULL; - printf("\n========== PMBASE/ABASE =========\n\n"); + printf("\n========== ACPI/PMC =========\n\n"); switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_3400: @@ -813,7 +815,6 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) return 1; } pmbase = pci_read_word(acpi, 0x40) & 0xfffc; - pci_free_dev(acpi); pm_registers = i82371xx_pm_registers; pm_registers_size = ARRAY_SIZE(i82371xx_pm_registers); @@ -855,7 +856,6 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) } pmbase = pci_read_word(acpi, 0x40) & ~0xff; pwrmbase_phys = pci_read_long(acpi, 0x48) & ~0xfff; - pci_free_dev(acpi); pm_registers = sunrise_pm_registers; pm_registers_size = ARRAY_SIZE(sunrise_pm_registers); @@ -865,6 +865,41 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) return 1; } + for (i = 0; i < pm_cfg_registers_size; i++) { + switch (pm_cfg_registers[i].size) { + case 8: + printf("0x%04x: 0x%08x (%s)\n" + " 0x%08x\n", + pm_cfg_registers[i].addr, + pci_read_long(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name, + pci_read_long(acpi, pm_cfg_registers[i].addr+4)); + break; + case 4: + printf("0x%04x: 0x%08x (%s)\n", + pm_cfg_registers[i].addr, + pci_read_long(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name); + break; + case 2: + printf("0x%04x: 0x%04x (%s)\n", + pm_cfg_registers[i].addr, + pci_read_word(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name); + break; + case 1: + printf("0x%04x: 0x%02x (%s)\n", + pm_cfg_registers[i].addr, + pci_read_byte(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name); + break; + } + } + + if (acpi) + pci_free_dev(acpi); + + printf("\n========== ABASE/PMBASE =========\n\n"); printf("PMBASE = 0x%04x (IO)\n\n", pmbase); for (i = 0; i < pm_registers_size; i++) { From 838fbc71cf38b441a8a28ba04916c23a0b9dc80c Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Thu, 21 Nov 2019 21:23:32 +0100 Subject: [PATCH 0544/1463] sb/ibexpeak: Use macros instead of hard-coded IDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch replaces hard-coded PCI IDs with macros from pci_ids.h and adds the related IDs to it. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 322170 Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/37116 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner --- src/include/device/pci_ids.h | 13 +++++++++++++ src/southbridge/intel/ibexpeak/azalia.c | 7 ++++++- src/southbridge/intel/ibexpeak/lpc.c | 6 +++++- src/southbridge/intel/ibexpeak/me.c | 7 +++++-- src/southbridge/intel/ibexpeak/sata.c | 7 ++++++- src/southbridge/intel/ibexpeak/smbus.c | 7 ++++++- src/southbridge/intel/ibexpeak/thermal.c | 5 ++++- src/southbridge/intel/ibexpeak/usb_ehci.c | 6 +++++- 8 files changed, 50 insertions(+), 8 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8d634f8106..8b2a273e85 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2715,6 +2715,19 @@ #define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0 #define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1 +/* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */ +#define PCI_DID_INTEL_IBEXPEAK_LPC_QM57 0x3b07 +#define PCI_DID_INTEL_IBEXPEAK_LPC_HM55 0x3b09 +#define PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1 0x3b28 +#define PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI 0x3b29 +#define PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2 0x3b2e +#define PCI_DID_INTEL_IBEXPEAK_EHCI_1 0x3b34 +#define PCI_DID_INTEL_IBEXPEAK_EHCI_2 0x3b3c +#define PCI_DID_INTEL_IBEXPEAK_SMBUS 0x3b30 +#define PCI_DID_INTEL_IBEXPEAK_AUDIO 0x3b56 +#define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64 +#define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 2fceced9b4..fe5cc2ea1d 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -323,7 +323,12 @@ static struct device_operations azalia_ops = { .ops_pci = &azalia_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0x3b56, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c20, + 0x1e20, + PCI_DID_INTEL_IBEXPEAK_AUDIO, + 0 +}; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 5c1b77fe43..0062e0901c 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -777,7 +777,11 @@ static struct device_operations device_ops = { }; -static const unsigned short pci_device_ids[] = { 0x3b07, 0x3b09, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_IBEXPEAK_LPC_QM57, + PCI_DID_INTEL_IBEXPEAK_LPC_HM55, + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 31a0261da6..e8974d8491 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -614,8 +614,11 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c3a, 0x3b64, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c3a, + PCI_DID_INTEL_IBEXPEAK_HECI1, + 0 +}; static const struct pci_driver intel_me __pci_driver = { diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index e4eebcb8a9..33437ef7d6 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -245,7 +245,12 @@ static struct device_operations sata_ops = { .ops_pci = &sata_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b28, 0x3b29, 0x3b2e, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1, + PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI, + PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2, + 0 +}; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index eafb1ee2df..b06b1cd135 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -96,7 +96,12 @@ static struct device_operations smbus_ops = { .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c22, + 0x1e22, + PCI_DID_INTEL_IBEXPEAK_SMBUS, + 0 +}; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index e9a542e692..2664c65ea7 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -56,7 +56,10 @@ static struct device_operations thermal_ops = { .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b32, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_IBEXPEAK_THERMAL, + 0 +}; static const struct pci_driver pch_thermal __pci_driver = { .ops = &thermal_ops, diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index ce169945fc..f4b975a4a0 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -96,7 +96,11 @@ static struct device_operations usb_ehci_ops = { .ops_pci = &lops_pci, }; -static const unsigned short pci_device_ids[] = { 0x3b34, 0x3b3c, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_IBEXPEAK_EHCI_1, + PCI_DID_INTEL_IBEXPEAK_EHCI_2, + 0 +}; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, From dbcb0ce5e90f115435a1e6e17cb9e5bd4a05e1f5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 19 Mar 2020 20:51:09 +0530 Subject: [PATCH 0545/1463] cpu/x86: Fix typo CIRTICAL -> CRITICAL Change-Id: Ie2c1427b197dbfebdc7f0c6ffd85f768845ff1bd Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39671 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes --- src/cpu/x86/mp_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 6082df99d4..704785555d 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -927,7 +927,7 @@ static int run_ap_work(struct mp_callback *val, long expire_us) return 0; } while (expire_us <= 0 || !stopwatch_expired(&sw)); - printk(BIOS_CRIT, "CIRTICAL ERROR: AP call expired. %d/%d CPUs accepted.\n", + printk(BIOS_CRIT, "CRITICAL ERROR: AP call expired. %d/%d CPUs accepted.\n", cpus_accepted, global_num_aps); return -1; } From 96cf680c3d5e4f98ddc05ccb7d50f48452014d0b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 19 Mar 2020 22:52:42 +0530 Subject: [PATCH 0546/1463] soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition proper This patch makes PCH_DEV_UART3 macro referring to _PCH_DEV() rather calling _PCH_DEVFN(). Change-Id: I7bc060c3c5f1e0a0fed194704b4940db73f46985 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39673 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/include/soc/pci_devs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 8b740cf93b..f7ecc3fabd 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -67,7 +67,7 @@ #define PCH_DEV_SLOT_SIO1 0x11 #define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) -#define PCH_DEV_UART3 _PCH_DEVFN(SIO1, 0) +#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) #define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) From 10d522133ef7531c1777c89b1a9ba3cdca5e25ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Mar 2020 19:08:21 +0100 Subject: [PATCH 0547/1463] util/inteltool: use read* macros instead of pointers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch to using read* macros instead of pointers. Change-Id: I1fe54b496a5998597b79cdd7108f3a4075744a78 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39503 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/inteltool/ahci.c | 23 +++++++++++------------ util/inteltool/amb.c | 8 ++++---- util/inteltool/gfx.c | 4 ++-- util/inteltool/inteltool.h | 1 + util/inteltool/memory.c | 4 ++-- util/inteltool/pcie.c | 20 ++++++++++---------- util/inteltool/powermgt.c | 4 ++-- util/inteltool/rootcmplx.c | 4 ++-- util/inteltool/spi.c | 10 +++++----- 9 files changed, 39 insertions(+), 39 deletions(-) diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 90a1617f8f..82f792d0e6 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -84,9 +84,6 @@ static const io_register_t sunrise_ahci_sir_registers[] = { #define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0])) #define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0])) -#define MMIO(offset) (*(uint32_t *)(mmio + offset)) -#define MMIO_PORT(offset) (*(uint32_t *)(mmio_port + offset)) - static void print_port(const uint8_t *const mmio, size_t port) { size_t i; @@ -96,10 +93,11 @@ static void print_port(const uint8_t *const mmio, size_t port) if (i / 4 < NUM_PORTCTL) { printf("0x%03zx: 0x%08x (%s)\n", (size_t)(mmio_port - mmio) + i, - MMIO_PORT(i), port_ctl_regs[i / 4]); - } else if (MMIO_PORT(i)) { + read32(mmio_port + i), port_ctl_regs[i / 4]); + } else if (read32(mmio_port + i)) { printf("0x%03zx: 0x%08x (Reserved)\n", - (size_t)(mmio_port - mmio) + i, MMIO_PORT(i)); + (size_t)(mmio_port - mmio) + i, + read32(mmio_port + i)); } } } @@ -195,22 +193,23 @@ int print_ahci(struct pci_dev *ahci) for (i = 0; i < 0x100; i += 4) { if (i / 4 < NUM_GHC) { printf("0x%03zx: 0x%08x (%s)\n", - i, MMIO(i), ghc_regs[i / 4]); - } else if (MMIO(i)) { - printf("0x%03zx: 0x%08x (Reserved)\n", i, MMIO(i)); + i, read32(mmio + i), ghc_regs[i / 4]); + } else if (read32(mmio + i)) { + printf("0x%03zx: 0x%08x (Reserved)\n", i, + read32(mmio + i)); } } const size_t max_ports = (ahci_registers_size - 0x100) / 0x80; for (i = 0; i < max_ports; i++) { - if (MMIO(0x0c) & 1 << i) + if (read32(mmio + 0x0c) & 1 << i) print_port(mmio, i); } puts("\nOther registers:"); for (i = 0x500; i < ahci_registers_size; i += 4) { - if (MMIO(i)) - printf("0x%03zx: 0x%08x\n", i, MMIO(i)); + if (read32(mmio + i)) + printf("0x%03zx: 0x%08x\n", i, read32(mmio + i)); } unmap_physical((void *)mmio, ahci_registers_size); diff --git a/util/inteltool/amb.c b/util/inteltool/amb.c index 26bece04e3..506ba5fa0f 100644 --- a/util/inteltool/amb.c +++ b/util/inteltool/amb.c @@ -20,11 +20,11 @@ #define AMB_CONFIG_SPACE_SIZE 0x20000 -#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff))) +#define AMB_ADDR(fn, reg) (((fn & 7) << 8) | ((reg & 0xff))) static uint32_t amb_read_config32(volatile void *base, int fn, int reg) { - return *(uint32_t *)(AMB_ADDR((intptr_t)base, fn, reg)); + return read32(base + AMB_ADDR(fn, reg)); } static void amb_printreg32(volatile void *base, int fn, int reg, @@ -38,7 +38,7 @@ static void amb_printreg32(volatile void *base, int fn, int reg, static uint16_t amb_read_config16(volatile void *base, int fn, int reg) { - return *(uint16_t *)(AMB_ADDR((intptr_t)base, fn, reg)); + return read16(base + AMB_ADDR(fn, reg)); } static void amb_printreg16(volatile void *base, int fn, int reg, @@ -53,7 +53,7 @@ static void amb_printreg16(volatile void *base, int fn, int reg, static uint8_t amb_read_config8(volatile void *base, int fn, int reg) { - return *(uint8_t *)(AMB_ADDR((intptr_t)base, fn, reg)); + return read8(base + AMB_ADDR(fn, reg)); } static void amb_printreg8(volatile void *base, int fn, int reg, diff --git a/util/inteltool/gfx.c b/util/inteltool/gfx.c index ffcf75c859..083e6c397d 100644 --- a/util/inteltool/gfx.c +++ b/util/inteltool/gfx.c @@ -39,8 +39,8 @@ int print_gfx(struct pci_dev *gfx) exit(1); } for (i = 0; i < MMIO_SIZE; i += 4) { - if (*(uint32_t *)(mmio + i)) - printf("0x%06x: 0x%08x\n", i, *(uint32_t *)(mmio + i)); + if (read32(mmio + i)) + printf("0x%06x: 0x%08x\n", i, read32(mmio + i)); } unmap_physical((void *)mmio, MMIO_SIZE); return 0; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 85f29fd8f9..0b1b476410 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -17,6 +17,7 @@ #ifndef INTELTOOL_H #define INTELTOOL_H 1 +#include #include #include diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 22de2a9f9d..f5f3f94fd4 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -261,8 +261,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(mchbar + i)) - printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i)); + if (read32(mchbar + i)) + printf("0x%04x: 0x%08"PRIx32"\n", i, read32(mchbar+i)); } switch (nb->device_id) diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 9b13087c5d..38ef61f1d8 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -298,8 +298,8 @@ int print_epbar(struct pci_dev *nb) printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys); for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(epbar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); + if (read32(epbar + i)) + printf("0x%04x: 0x%08x\n", i, read32(epbar+i)); } unmap_physical((void *)epbar, size); @@ -428,27 +428,27 @@ int print_dmibar(struct pci_dev *nb) case 4: printf("dmibase+0x%04x: 0x%08x (%s)\n", dmi_registers[i].addr, - *(uint32_t *)(dmibar+dmi_registers[i].addr), + read32(dmibar+dmi_registers[i].addr), dmi_registers[i].name); break; case 2: printf("dmibase+0x%04x: 0x%04x (%s)\n", dmi_registers[i].addr, - *(uint16_t *)(dmibar+dmi_registers[i].addr), + read16(dmibar+dmi_registers[i].addr), dmi_registers[i].name); break; case 1: printf("dmibase+0x%04x: 0x%02x (%s)\n", dmi_registers[i].addr, - *(uint8_t *)(dmibar+dmi_registers[i].addr), + read8(dmibar+dmi_registers[i].addr), dmi_registers[i].name); break; } } } else { for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(dmibar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); + if (read32(dmibar + i)) + printf("0x%04x: 0x%08x\n", i, read32(dmibar+i)); } } @@ -567,12 +567,12 @@ int print_pciexbar(struct pci_dev *nb) for (fn = 0; fn < 8; fn++) { devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024); - if (*(uint16_t *)(pciexbar + devbase) == 0xffff) + if (read16(pciexbar + devbase) == 0xffff) continue; /* This is a heuristics. Anyone got a better check? */ - if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) && - (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) { + if( (read32(pciexbar + devbase + 256) == 0xffffffff) && + (read32(pciexbar + devbase + 512) == 0xffffffff) ) { #if DEBUG printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn); #endif diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 125c7396ec..0edd3e8d6d 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -946,9 +946,9 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) printf("PWRMBASE = 0x%08" PRIx64 " (MEM)\n\n", pwrmbase_phys); for (i = 0; i < pwrmbase_size; i += 4) { - if (*(uint32_t *)(pwrmbase + i)) + if (read32(pwrmbase + i)) printf("0x%04zx: 0x%08"PRIx32"\n", - i, *(uint32_t *)(pwrmbase + i)); + i, read32(pwrmbase + i)); } unmap_physical((void *)pwrmbase, pwrmbase_size); diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 70d7cbe3ed..8aa959b174 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -147,8 +147,8 @@ int print_rcba(struct pci_dev *sb) printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys); for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(rcba + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i)); + if (read32(rcba + i)) + printf("0x%04x: 0x%08x\n", i, read32(rcba + i)); } unmap_physical((void *)rcba, size); diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index ca29fcc099..3d94c1fc02 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -364,17 +364,17 @@ static int print_spibar(struct pci_dev *sb) { for (i = 0; i < size; i++) { switch(spi_register[i].size) { case 1: - printf("0x%08x = %s\n", *(uint8_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); + printf("0x%08x = %s\n", read8(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); break; case 2: - printf("0x%08x = %s\n", *(uint16_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); + printf("0x%08x = %s\n", read16(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); break; case 4: - printf("0x%08x = %s\n", *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); + printf("0x%08x = %s\n", read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); break; case 8: - printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr + 4), - *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); + printf("0x%08x%08x = %s\n", read32(rcba + spibaroffset + spi_register[i].addr + 4), + read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name); break; } } From 117ee716985fcb531ff5aa189dfac81e84aeb8d0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 19 Mar 2020 22:43:01 +0530 Subject: [PATCH 0548/1463] device/pci_id: Maintain consistent tab in pci_ids.h This patch converts inconsistent white space into tab. Change-Id: Ibc9d614eabbeb819bfff075e66b2277df4c070dc Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39672 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/include/device/pci_ids.h | 355 +++++++++++++++++------------------ 1 file changed, 177 insertions(+), 178 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8b2a273e85..13004dbd54 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -660,7 +660,7 @@ #define PCI_VENDOR_ID_AI 0x1025 #define PCI_DEVICE_ID_AI_M1435 0x1435 -#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_VENDOR_ID_DELL 0x1028 #define PCI_VENDOR_ID_MATROX 0x102B #define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 @@ -690,8 +690,8 @@ #define PCI_VENDOR_ID_NEC 0x1033 #define PCI_DEVICE_ID_NEC_PCX2 0x0046 #define PCI_DEVICE_ID_NEC_NILE4 0x005a -#define PCI_DEVICE_ID_NEC_VRC5476 0x009b -#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 +#define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 #define PCI_VENDOR_ID_FD 0x1036 #define PCI_DEVICE_ID_FD_36C70 0x0000 @@ -791,10 +791,10 @@ #define PCI_DEVICE_ID_SGS_2000 0x0008 #define PCI_DEVICE_ID_SGS_1764 0x0009 -#define PCI_VENDOR_ID_BUSLOGIC 0x104B -#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 -#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 -#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 #define PCI_VENDOR_ID_TI 0x104c #define PCI_DEVICE_ID_TI_TVP4010 0x3d04 @@ -885,10 +885,10 @@ #define PCI_DEVICE_ID_X_AGX016 0x0001 #define PCI_VENDOR_ID_MYLEX 0x1069 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 #define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 #define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 #define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 @@ -1018,7 +1018,7 @@ #define PCI_DEVICE_ID_DATABOOK_87144 0xb106 #define PCI_VENDOR_ID_PLX 0x10b5 -#define PCI_VENDOR_ID_PLX_ROMULUS 0x106a +#define PCI_VENDOR_ID_PLX_ROMULUS 0x106a #define PCI_DEVICE_ID_PLX_R685 0x1030 #define PCI_DEVICE_ID_PLX_ROMULUS 0x106a #define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 @@ -1066,12 +1066,12 @@ #define PCI_DEVICE_ID_AL_M1531 0x1531 #define PCI_DEVICE_ID_AL_M1533 0x1533 #define PCI_DEVICE_ID_AL_M1541 0x1541 -#define PCI_DEVICE_ID_AL_M1621 0x1621 -#define PCI_DEVICE_ID_AL_M1631 0x1631 -#define PCI_DEVICE_ID_AL_M1641 0x1641 -#define PCI_DEVICE_ID_AL_M1644 0x1644 -#define PCI_DEVICE_ID_AL_M1647 0x1647 -#define PCI_DEVICE_ID_AL_M1651 0x1651 +#define PCI_DEVICE_ID_AL_M1621 0x1621 +#define PCI_DEVICE_ID_AL_M1631 0x1631 +#define PCI_DEVICE_ID_AL_M1641 0x1641 +#define PCI_DEVICE_ID_AL_M1644 0x1644 +#define PCI_DEVICE_ID_AL_M1647 0x1647 +#define PCI_DEVICE_ID_AL_M1651 0x1651 #define PCI_DEVICE_ID_AL_M1543 0x1543 #define PCI_DEVICE_ID_AL_M3307 0x3307 #define PCI_DEVICE_ID_AL_M4803 0x5215 @@ -1088,12 +1088,12 @@ #define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 #define PCI_VENDOR_ID_NEOMAGIC 0x10c8 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 #define PCI_VENDOR_ID_ASP 0x10cd #define PCI_DEVICE_ID_ASP_ABP940 0x1200 @@ -1113,46 +1113,46 @@ #define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 #define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 -#define PCI_DEVICE_ID_NVIDIA_CK8S_HT 0x00e1 -#define PCI_DEVICE_ID_NVIDIA_CK8S_LPC 0x00e0 -#define PCI_DEVICE_ID_NVIDIA_CK8S_SM 0x00e4 -#define PCI_DEVICE_ID_NVIDIA_CK8S_USB 0x00e7 -#define PCI_DEVICE_ID_NVIDIA_CK8S_USB2 0x00e8 -#define PCI_DEVICE_ID_NVIDIA_CK8S_NIC 0x00e6 -#define PCI_DEVICE_ID_NVIDIA_CK8S_ACI 0x00ea -#define PCI_DEVICE_ID_NVIDIA_CK8S_MCI 0x00e9 -#define PCI_DEVICE_ID_NVIDIA_CK8S_IDE 0x00e5 -#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA0 0x00ee -#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA1 0x00e3 -#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI 0x00ed -#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI_AGP 0x00e2 +#define PCI_DEVICE_ID_NVIDIA_CK8S_HT 0x00e1 +#define PCI_DEVICE_ID_NVIDIA_CK8S_LPC 0x00e0 +#define PCI_DEVICE_ID_NVIDIA_CK8S_SM 0x00e4 +#define PCI_DEVICE_ID_NVIDIA_CK8S_USB 0x00e7 +#define PCI_DEVICE_ID_NVIDIA_CK8S_USB2 0x00e8 +#define PCI_DEVICE_ID_NVIDIA_CK8S_NIC 0x00e6 +#define PCI_DEVICE_ID_NVIDIA_CK8S_ACI 0x00ea +#define PCI_DEVICE_ID_NVIDIA_CK8S_MCI 0x00e9 +#define PCI_DEVICE_ID_NVIDIA_CK8S_IDE 0x00e5 +#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA0 0x00ee +#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA1 0x00e3 +#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI 0x00ed +#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI_AGP 0x00e2 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360 -#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2 0x0362 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3 0x0363 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4 0x0364 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5 0x0365 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6 0x0366 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO 0x0367 -#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2 0x0368 -#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE 0x036E -#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0 0x037E -#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1 0x037F -#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC 0x0372 -#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE 0x0373 -#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA 0x0371 -#define PCI_DEVICE_ID_NVIDIA_MCP55_USB 0x036C -#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2 0x036D -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI 0x0370 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C 0x0374 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E 0x0375 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A 0x0376 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F 0x0377 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D 0x0378 -#define PCI_DEVICE_ID_NVIDIA_MCP55_HT 0x0369 -#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A -#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360 +#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2 0x0362 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3 0x0363 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4 0x0364 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5 0x0365 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6 0x0366 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO 0x0367 +#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2 0x0368 +#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE 0x036E +#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0 0x037E +#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1 0x037F +#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC 0x0372 +#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE 0x0373 +#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA 0x0371 +#define PCI_DEVICE_ID_NVIDIA_MCP55_USB 0x036C +#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2 0x036D +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI 0x0370 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C 0x0374 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E 0x0375 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A 0x0376 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F 0x0377 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D 0x0378 +#define PCI_DEVICE_ID_NVIDIA_MCP55_HT 0x0369 +#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A +#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B #define PCI_VENDOR_ID_NVIDIA 0x10de #define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 @@ -1160,32 +1160,32 @@ #define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 #define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C #define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D -#define PCI_DEVICE_ID_NVIDIA_CK804_LPC 0x0050 -#define PCI_DEVICE_ID_NVIDIA_CK804_PRO 0x0051 -#define PCI_DEVICE_ID_NVIDIA_CK804_ISA 0x0051 -#define PCI_DEVICE_ID_NVIDIA_CK804_SMB 0x0052 -#define PCI_DEVICE_ID_NVIDIA_CK804_SM 0x0052 -#define PCI_DEVICE_ID_NVIDIA_CK804_ACPI 0x0052 -#define PCI_DEVICE_ID_NVIDIA_CK804_IDE 0x0053 -#define PCI_DEVICE_ID_NVIDIA_CK804_SATA0 0x0054 -#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1 0x0055 -#define PCI_DEVICE_ID_NVIDIA_CK804_ENET 0x0056 -#define PCI_DEVICE_ID_NVIDIA_CK804_NIC 0x0056 -#define PCI_DEVICE_ID_NVIDIA_CK804_ENET2 0x0057 -#define PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE 0x0057 -#define PCI_DEVICE_ID_NVIDIA_CK804_MODEM 0x0058 -#define PCI_DEVICE_ID_NVIDIA_CK804_MCI 0x0058 -#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 -#define PCI_DEVICE_ID_NVIDIA_CK804_ACI 0x0059 -#define PCI_DEVICE_ID_NVIDIA_CK804_USB 0x005A -#define PCI_DEVICE_ID_NVIDIA_CK804_USB2 0x005B -#define PCI_DEVICE_ID_NVIDIA_CK804_PCI 0x005C -#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005D -#define PCI_DEVICE_ID_NVIDIA_CK804_PCI_E 0x005D -#define PCI_DEVICE_ID_NVIDIA_CK804_MEM 0x005E -#define PCI_DEVICE_ID_NVIDIA_CK804_HT 0x005E -#define PCI_DEVICE_ID_NVIDIA_CK804_TRIM 0x005f -#define PCI_DEVICE_ID_NVIDIA_CK804_SLAVE 0x00d3 +#define PCI_DEVICE_ID_NVIDIA_CK804_LPC 0x0050 +#define PCI_DEVICE_ID_NVIDIA_CK804_PRO 0x0051 +#define PCI_DEVICE_ID_NVIDIA_CK804_ISA 0x0051 +#define PCI_DEVICE_ID_NVIDIA_CK804_SMB 0x0052 +#define PCI_DEVICE_ID_NVIDIA_CK804_SM 0x0052 +#define PCI_DEVICE_ID_NVIDIA_CK804_ACPI 0x0052 +#define PCI_DEVICE_ID_NVIDIA_CK804_IDE 0x0053 +#define PCI_DEVICE_ID_NVIDIA_CK804_SATA0 0x0054 +#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1 0x0055 +#define PCI_DEVICE_ID_NVIDIA_CK804_ENET 0x0056 +#define PCI_DEVICE_ID_NVIDIA_CK804_NIC 0x0056 +#define PCI_DEVICE_ID_NVIDIA_CK804_ENET2 0x0057 +#define PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE 0x0057 +#define PCI_DEVICE_ID_NVIDIA_CK804_MODEM 0x0058 +#define PCI_DEVICE_ID_NVIDIA_CK804_MCI 0x0058 +#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 +#define PCI_DEVICE_ID_NVIDIA_CK804_ACI 0x0059 +#define PCI_DEVICE_ID_NVIDIA_CK804_USB 0x005A +#define PCI_DEVICE_ID_NVIDIA_CK804_USB2 0x005B +#define PCI_DEVICE_ID_NVIDIA_CK804_PCI 0x005C +#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005D +#define PCI_DEVICE_ID_NVIDIA_CK804_PCI_E 0x005D +#define PCI_DEVICE_ID_NVIDIA_CK804_MEM 0x005E +#define PCI_DEVICE_ID_NVIDIA_CK804_HT 0x005E +#define PCI_DEVICE_ID_NVIDIA_CK804_TRIM 0x005f +#define PCI_DEVICE_ID_NVIDIA_CK804_SLAVE 0x00d3 #define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 @@ -1204,7 +1204,6 @@ #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 #define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 - #define PCI_VENDOR_ID_IMS 0x10e0 #define PCI_DEVICE_ID_IMS_8849 0x8849 #define PCI_DEVICE_ID_IMS_TT128 0x9128 @@ -1284,7 +1283,7 @@ #define PCI_DEVICE_ID_VIA_82C693_1 0x0698 #define PCI_DEVICE_ID_VIA_82C926 0x0926 #define PCI_DEVICE_ID_VIA_82C576_1 0x1571 -#define PCI_DEVICE_ID_VIA_82C416 0x1571 +#define PCI_DEVICE_ID_VIA_82C416 0x1571 #define PCI_DEVICE_ID_VIA_82C595_97 0x1595 #define PCI_DEVICE_ID_VIA_82C586_2 0x3038 #define PCI_DEVICE_ID_VIA_82C586_3 0x3040 @@ -1419,8 +1418,8 @@ #define PCI_DEVICE_ID_VIA_CN400_BRIDGE 0xB198 #define PCI_DEVICE_ID_VIA_CN400_VGA 0x3118 -#define PCI_VENDOR_ID_SIEMENS 0x110A -#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 +#define PCI_VENDOR_ID_SIEMENS 0x110A +#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 #define PCI_VENDOR_ID_SMC2 0x1113 #define PCI_DEVICE_ID_SMC2_1211TX 0x1211 @@ -1531,43 +1530,43 @@ #define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 #define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 -#define PCI_VENDOR_ID_SERVERWORKS 0x1166 -#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 -#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 -#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010 -#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011 -#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 -#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 -#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 -#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 -#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 -#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 -#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 -#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 -#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB -#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 -#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 -#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 -#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230 +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 +#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 +#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010 +#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011 +#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB +#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB 0x0130 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE 0x0132 -#define PCI_DEVICE_ID_BROADCOM_BCM5780_NIC 0x1668 -#define PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1 0x1669 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB 0x0130 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE 0x0132 +#define PCI_DEVICE_ID_BROADCOM_BCM5780_NIC 0x1668 +#define PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1 0x1669 -#define PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0 0x140 -#define PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1 0x142 -#define PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2 0x144 +#define PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0 0x140 +#define PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1 0x142 +#define PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2 0x144 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_HT_PXB 0x0036 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_PXBX 0x0104 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA 0x024a -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN 0x0205 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE 0x0214 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC 0x0234 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_WDT 0x0238 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_XIOAPIC 0x0235 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB 0x0223 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_HT_PXB 0x0036 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_PXBX 0x0104 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA 0x024a +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN 0x0205 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE 0x0214 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC 0x0234 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_WDT 0x0238 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_XIOAPIC 0x0235 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB 0x0223 #define PCI_VENDOR_ID_SBE 0x1176 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301 @@ -1633,8 +1632,8 @@ #define PCI_VENDOR_ID_V3 0x11b0 #define PCI_DEVICE_ID_V3_V960 0x0001 #define PCI_DEVICE_ID_V3_V350 0x0001 -#define PCI_DEVICE_ID_V3_V960V2 0x0002 -#define PCI_DEVICE_ID_V3_V350V2 0x0002 +#define PCI_DEVICE_ID_V3_V960V2 0x0002 +#define PCI_DEVICE_ID_V3_V350V2 0x0002 #define PCI_DEVICE_ID_V3_V961 0x0002 #define PCI_DEVICE_ID_V3_V351 0x0002 @@ -1767,7 +1766,7 @@ #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 #define PCI_DEVICE_ID_ITE_8872 0x8872 -#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 +#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 /* formerly Platform Tech */ #define PCI_VENDOR_ID_ESS_OLD 0x1285 @@ -1924,7 +1923,7 @@ #define PCI_DEVICE_ID_3WARE_1000 0x1000 #define PCI_VENDOR_ID_ABOCOM 0x13D1 -#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 +#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 #define PCI_VENDOR_ID_CMEDIA 0x13f6 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 @@ -2600,15 +2599,15 @@ #define PCI_DEVICE_ID_INTEL_82801E_LAN2 0x245d #define PCI_DEVICE_ID_INTEL_82801E_PCI 0x245e -#define PCI_DEVICE_ID_INTEL_82870_1E0 0x1461 -#define PCI_DEVICE_ID_INTEL_82870_1F0 0x1460 -#define PCI_DEVICE_ID_INTEL_82820FW_0 0x2440 -#define PCI_DEVICE_ID_INTEL_82820FW_1 0x2442 -#define PCI_DEVICE_ID_INTEL_82820FW_2 0x2443 -#define PCI_DEVICE_ID_INTEL_82820FW_3 0x2444 -#define PCI_DEVICE_ID_INTEL_82820FW_4 0x2449 -#define PCI_DEVICE_ID_INTEL_82820FW_5 0x244b -#define PCI_DEVICE_ID_INTEL_82820FW_6 0x244e +#define PCI_DEVICE_ID_INTEL_82870_1E0 0x1461 +#define PCI_DEVICE_ID_INTEL_82870_1F0 0x1460 +#define PCI_DEVICE_ID_INTEL_82820FW_0 0x2440 +#define PCI_DEVICE_ID_INTEL_82820FW_1 0x2442 +#define PCI_DEVICE_ID_INTEL_82820FW_2 0x2443 +#define PCI_DEVICE_ID_INTEL_82820FW_3 0x2444 +#define PCI_DEVICE_ID_INTEL_82820FW_4 0x2449 +#define PCI_DEVICE_ID_INTEL_82820FW_5 0x244b +#define PCI_DEVICE_ID_INTEL_82820FW_6 0x244e /* Intel 6300ESB */ #define PCI_DEVICE_ID_INTEL_6300ESB_LPC 0x25a1 @@ -2627,32 +2626,32 @@ #define PCI_DEVICE_ID_INTEL_6300ESB_WDT 0x25ab /* Intel 3100 */ -#define PCI_DEVICE_ID_INTEL_3100_LPC 0x2670 -#define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c -#define PCI_DEVICE_ID_INTEL_3100_PCI 0x244e -#define PCI_DEVICE_ID_INTEL_3100_IDE 0x2680 -#define PCI_DEVICE_ID_INTEL_3100_AHCI 0x2681 -#define PCI_DEVICE_ID_INTEL_3100_UHCI 0x2688 -#define PCI_DEVICE_ID_INTEL_3100_UHCI2 0x2689 -#define PCI_DEVICE_ID_INTEL_3100_SMB 0x269b -#define PCI_DEVICE_ID_INTEL_3100_MC 0x35b0 -#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA0 0x35b6 -#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA1 0x35b7 -#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB0 0x2690 -#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB1 0x2692 -#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB2 0x2694 -#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB3 0x2696 +#define PCI_DEVICE_ID_INTEL_3100_LPC 0x2670 +#define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c +#define PCI_DEVICE_ID_INTEL_3100_PCI 0x244e +#define PCI_DEVICE_ID_INTEL_3100_IDE 0x2680 +#define PCI_DEVICE_ID_INTEL_3100_AHCI 0x2681 +#define PCI_DEVICE_ID_INTEL_3100_UHCI 0x2688 +#define PCI_DEVICE_ID_INTEL_3100_UHCI2 0x2689 +#define PCI_DEVICE_ID_INTEL_3100_SMB 0x269b +#define PCI_DEVICE_ID_INTEL_3100_MC 0x35b0 +#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA0 0x35b6 +#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA1 0x35b7 +#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB0 0x2690 +#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB1 0x2692 +#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB2 0x2694 +#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB3 0x2696 /* Intel EP80579 */ -#define PCI_DEVICE_ID_INTEL_EP80579_LPC 0x5031 -#define PCI_DEVICE_ID_INTEL_EP80579_EHCI 0x5035 -#define PCI_DEVICE_ID_INTEL_EP80579_IDE 0x5028 -#define PCI_DEVICE_ID_INTEL_EP80579_AHCI 0x5029 -#define PCI_DEVICE_ID_INTEL_EP80579_UHCI 0x5033 -#define PCI_DEVICE_ID_INTEL_EP80579_SMB 0x5032 -#define PCI_DEVICE_ID_INTEL_EP80579_MC 0x5020 -#define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0 0x5024 -#define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1 0x5025 +#define PCI_DEVICE_ID_INTEL_EP80579_LPC 0x5031 +#define PCI_DEVICE_ID_INTEL_EP80579_EHCI 0x5035 +#define PCI_DEVICE_ID_INTEL_EP80579_IDE 0x5028 +#define PCI_DEVICE_ID_INTEL_EP80579_AHCI 0x5029 +#define PCI_DEVICE_ID_INTEL_EP80579_UHCI 0x5033 +#define PCI_DEVICE_ID_INTEL_EP80579_SMB 0x5032 +#define PCI_DEVICE_ID_INTEL_EP80579_MC 0x5020 +#define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0 0x5024 +#define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1 0x5025 #define PCI_DEVICE_ID_INTEL_80310 0x530d #define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 @@ -2675,7 +2674,7 @@ #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82451NX 0x84ca -#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb +#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb #define PCI_DEVICE_ID_INTEL_PCIE_PA 0x3595 #define PCI_DEVICE_ID_INTEL_PCIE_PA1 0x3596 #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 @@ -3167,10 +3166,10 @@ #define PCI_DEVICE_ID_INTEL_SPT_I2C3 0x9d63 #define PCI_DEVICE_ID_INTEL_SPT_I2C4 0x9d64 #define PCI_DEVICE_ID_INTEL_SPT_I2C5 0x9d65 -#define PCI_DEVICE_ID_INTEL_KBP_H_I2C0 0xa2e0 -#define PCI_DEVICE_ID_INTEL_KBP_H_I2C1 0xa2e1 -#define PCI_DEVICE_ID_INTEL_KBP_H_I2C2 0xa2e2 -#define PCI_DEVICE_ID_INTEL_KBP_H_I2C3 0xa2e3 +#define PCI_DEVICE_ID_INTEL_KBP_H_I2C0 0xa2e0 +#define PCI_DEVICE_ID_INTEL_KBP_H_I2C1 0xa2e1 +#define PCI_DEVICE_ID_INTEL_KBP_H_I2C2 0xa2e2 +#define PCI_DEVICE_ID_INTEL_KBP_H_I2C3 0xa2e3 #define PCI_DEVICE_ID_INTEL_APL_I2C0 0x5aac #define PCI_DEVICE_ID_INTEL_APL_I2C1 0x5aae #define PCI_DEVICE_ID_INTEL_APL_I2C2 0x5ab0 @@ -3425,10 +3424,10 @@ #define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0 0x9BC5 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0 0x3E9B #define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1 0x9BC4 -#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 -#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 -#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 -#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT2 0xFF20 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40 #define PCI_DEVICE_ID_INTEL_TGL_GT0 0x9A7F #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 @@ -3819,12 +3818,12 @@ #define PCI_DEVICE_ID_SIS_SIS968_HD_AUDIO 0x7502 /* DfF0 */ /* OLD USAGE FOR COREBOOT */ -#define PCI_VENDOR_ID_ACER 0x10b9 -#define PCI_DEVICE_ID_ACER_M1535D 0x1533 +#define PCI_VENDOR_ID_ACER 0x10b9 +#define PCI_DEVICE_ID_ACER_M1535D 0x1533 -#define PCI_DEVICE_ID_AMD_761_0 0x700E -#define PCI_DEVICE_ID_AMD_761_1 0x700F -#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412 +#define PCI_DEVICE_ID_AMD_761_0 0x700E +#define PCI_DEVICE_ID_AMD_761_1 0x700F +#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412 /* END OLDER USAGE */ From cf8602b453d4e193ce71a0452fac2b769c881b23 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 19 Mar 2020 09:39:56 +0100 Subject: [PATCH 0549/1463] configs: Fix Intel RVP11 defconfig It wasn't picked up by the builder due to wrong file name. Change-Id: Ia31b5d304a0cabd0d578c5ac6181cb1c8ee1c246 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39666 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- ...el.cfl_rvp11_fsp_car => config.intel_coffeelake_rvp11.fsp_car} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename configs/{config.intel.cfl_rvp11_fsp_car => config.intel_coffeelake_rvp11.fsp_car} (100%) diff --git a/configs/config.intel.cfl_rvp11_fsp_car b/configs/config.intel_coffeelake_rvp11.fsp_car similarity index 100% rename from configs/config.intel.cfl_rvp11_fsp_car rename to configs/config.intel_coffeelake_rvp11.fsp_car From b3884dc59b3f84091136fbff0b8a790e1a4b91f3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 17 Mar 2020 23:46:53 +0100 Subject: [PATCH 0550/1463] nb/intel/sandybridge: Drop spurious register write It does not make sense to disable an optimization that was not enabled before, especially if that optimization only applies to Ivy Bridge. Tested, still boots and can suspend correctly with: - Asus P8Z77-V LX2 with i5-3330 and Windows 10 - Gigabyte GA-H61MA-D3V with i5-2400 and Arch Linux Change-Id: I9f3eb545585824bbdf51e33f0592e7daa1c425af Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39623 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber --- src/northbridge/intel/sandybridge/raminit_common.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2cb6a8337b..e28907086d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3236,11 +3236,4 @@ void restore_timings(ramctr_timing *ctrl) MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); udelay(2); } - - /* - * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. - * FIXME: This must only be done on Ivy Bridge. Moreover, this instance seems to be - * spurious, because nothing else enabled this optimization before. - */ - MCHBAR32(MCMNTS_SPARE) = 0; } From 0beddb5e237f23c59399b1c93f25230a6eab3372 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 9 Mar 2020 10:58:37 +0800 Subject: [PATCH 0551/1463] cbfstool: Build vboot library Currently cbfstool cherry-picks a few files from vboot and hopes these files will work standalone without any dependencies. This is pretty brittle (for example, CL:2084062 will break it), and could be improved by building the whole vboot library and then linking against it. Therefore, this patch creates a new target $(VBOOT_HOSTLIB) and includes it as a dependency for cbfstool and ifittool. To prevent building the vboot lib twice (one for cbfstool and the other for futility) when building coreboot tools together, add the variable 'VBOOT_BUILD' in Makefile to define a shared build path among different tools so that vboot files don't need to be recompiled. Also ignore *.o.d and *.a for vboot library. BRANCH=none BUG=none TEST=make -C util/cbfstool TEST=make -C util/futility TEST=Run 'make tools' and make sure common files such as 2sha1.c are compiled only once TEST=emerge-nami coreboot-utils Change-Id: Ifc826896d895f53d69ea559a88f75672c2ec3146 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/39390 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .gitignore | 2 ++ Makefile | 2 ++ util/cbfstool/Makefile | 2 ++ util/cbfstool/Makefile.inc | 36 +++++++++++++++--------------------- util/futility/Makefile | 1 + util/futility/Makefile.inc | 11 +++++++---- 6 files changed, 29 insertions(+), 25 deletions(-) diff --git a/.gitignore b/.gitignore index 5301a6e7f4..ed667765fb 100644 --- a/.gitignore +++ b/.gitignore @@ -54,11 +54,13 @@ util/crossgcc/xgcc site-local *.\# +*.a *.bin *.debug !Kconfig.debug *.elf *.o +*.o.d *.out *.pyc *.sw[po] diff --git a/Makefile b/Makefile index 3f60493314..98e3eb5796 100644 --- a/Makefile +++ b/Makefile @@ -42,6 +42,8 @@ objutil ?= $(obj)/util objk := $(objutil)/kconfig absobj := $(abspath $(obj)) +VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) + COREBOOT_EXPORTS := COREBOOT_EXPORTS COREBOOT_EXPORTS += top src srck obj objutil objk diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index d5321f6959..5251b2d872 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -10,6 +10,7 @@ INSTALL ?= /usr/bin/env install OBJCOPY ?= objcopy VBOOT_SOURCE ?= $(top)/3rdparty/vboot +VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) .PHONY: all all: cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool @@ -35,6 +36,7 @@ clean: $(RM) $(objutil)/cbfstool/ifwitool $(ifwiobj) $(RM) $(objutil)/cbfstool/ifittool $(ifitobj) $(RM) $(objutil)/cbfstool/cbfs-compression-tool $(cbfscompobj) + $(RM) -r $(VBOOT_HOST_BUILD) linux_trampoline.c: linux_trampoline.S rm -f linux_trampoline.c diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 356b295f4a..f38c8258a6 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -27,11 +27,6 @@ cbfsobj += cbfs.o cbfsobj += fsp_relocate.o cbfsobj += mem_pool.o cbfsobj += region.o -# CRYPTOLIB -cbfsobj += 2sha_utility.o -cbfsobj += 2sha1.o -cbfsobj += 2sha256.o -cbfsobj += 2sha512.o # FMAP cbfsobj += fmap.o cbfsobj += kv_pair.o @@ -81,11 +76,6 @@ ifitobj += rmodule.o ifitobj += cbfs.o ifitobj += mem_pool.o ifitobj += region.o -# CRYPTOLIB -ifitobj += 2sha_utility.o -ifitobj += 2sha1.o -ifitobj += 2sha256.o -ifitobj += 2sha512.o # FMAP ifitobj += fmap.o ifitobj += kv_pair.o @@ -136,6 +126,17 @@ else TOOLCFLAGS+=-std=c11 endif +VBOOT_HOSTLIB = $(VBOOT_HOST_BUILD)/libvboot_host.a + +$(VBOOT_HOSTLIB): + printf " MAKE $(subst $(objutil)/,,$(@))\n" + unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$(VBOOT_HOST_BUILD) \ + CC="$(HOSTCC)" \ + $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ + V=$(V) \ + hostlib + $(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< @@ -156,10 +157,6 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/C/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(VBOOT_SOURCE)/firmware/2lib/%.c - printf " HOSTCC $(subst $(objutil)/,,$(@))\n" - $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< - $(objutil)/cbfstool/%.o: $(top)/src/commonlib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< @@ -172,9 +169,9 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lz4/lib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) +$(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(VBOOT_HOSTLIB) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" - $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) + $(HOSTCC) -v $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(VBOOT_HOSTLIB) $(objutil)/cbfstool/fmaptool: $(addprefix $(objutil)/cbfstool/,$(fmapobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" @@ -188,9 +185,9 @@ $(objutil)/cbfstool/ifwitool: $(addprefix $(objutil)/cbfstool/,$(ifwiobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(ifwiobj)) -$(objutil)/cbfstool/ifittool: $(addprefix $(objutil)/cbfstool/,$(ifitobj)) +$(objutil)/cbfstool/ifittool: $(addprefix $(objutil)/cbfstool/,$(ifitobj)) $(VBOOT_HOSTLIB) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" - $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(ifitobj)) + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(ifitobj)) $(VBOOT_HOSTLIB) $(objutil)/cbfstool/cbfs-compression-tool: $(addprefix $(objutil)/cbfstool/,$(cbfscompobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" @@ -208,9 +205,6 @@ $(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-unused-function # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -# Tolerate vboot warnings -$(objutil)/cbfstool/2sha_utility.o: TOOLCFLAGS += -Wno-sign-compare -$(objutil)/cbfstool/2sha1.o: TOOLCFLAGS += -Wno-cast-qual # Tolerate commonlib warnings $(objutil)/cbfstool/region.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual $(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual diff --git a/util/futility/Makefile b/util/futility/Makefile index cce5da6e9d..2eaab3eaa5 100644 --- a/util/futility/Makefile +++ b/util/futility/Makefile @@ -4,6 +4,7 @@ RM ?= rm HOSTCC ?= $(CC) VBOOT_SOURCE ?= $(top)/3rdparty/vboot +VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) .PHONY: all all: $(objutil)/futility/futility diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index 06e724c15f..ee4ad051e2 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -1,14 +1,17 @@ additional-dirs += $(objutil)/futility -$(objutil)/futility/build/futility/futility: +VBOOT_FUTILITY = $(VBOOT_HOST_BUILD)/futility/futility + +$(VBOOT_FUTILITY): @printf " MAKE $(subst $(objutil)/,,$(@))\n" unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$(abspath $@/../..) \ + BUILD=$(VBOOT_HOST_BUILD) \ CC="$(HOSTCC)" \ $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ V=$(V) \ - $(abspath $@) + $@ -$(objutil)/futility/futility: $(objutil)/futility/build/futility/futility +$(objutil)/futility/futility: $(VBOOT_FUTILITY) + mkdir -p $(dir $@) cp $< $@.tmp mv $@.tmp $@ From 77e0baa6e99761462af4c69c7beda0af9571525e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 3 Feb 2018 11:50:56 +0100 Subject: [PATCH 0552/1463] libpayload/drivers/nvram: Add function to write RTC Add a function to set the RTC to provided struct tm. Change-Id: I17b4c1ee0dcc649738ac6a7400b087d07213eaf0 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/23585 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/nvram.c | 52 ++++++++++++++++++++++++ payloads/libpayload/include/libpayload.h | 1 + 2 files changed, 53 insertions(+) diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index 34ee0331e1..0196bb5c7c 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -160,3 +160,55 @@ void rtc_read_clock(struct tm *time) if (time->tm_year < 80) time->tm_year += 100; } + +/** + * Write the current time and date to the RTC + * + * @param time A pointer to a broken-down time structure + */ +void rtc_write_clock(const struct tm *time) +{ + u16 timeout = 10000; + u8 statusB; + u8 reg8, year; + + while (nvram_updating()) + if (!timeout--) + return; + + statusB = nvram_read(NVRAM_RTC_STATUSB); + + year = time->tm_year; + if (year > 100) + year -= 100; + + if (!(statusB & NVRAM_RTC_FORMAT_BINARY)) { + nvram_write(dec2bcd(time->tm_mon + 1), NVRAM_RTC_MONTH); + nvram_write(dec2bcd(time->tm_sec), NVRAM_RTC_SECONDS); + nvram_write(dec2bcd(time->tm_min), NVRAM_RTC_MINUTES); + nvram_write(dec2bcd(time->tm_mday), NVRAM_RTC_DAY); + if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) { + if (time->tm_hour > 12) + reg8 = dec2bcd(time->tm_hour - 12) | 0x80; + else + reg8 = dec2bcd(time->tm_hour); + } else + reg8 = dec2bcd(time->tm_hour); + nvram_write(reg8, NVRAM_RTC_HOURS); + nvram_write(dec2bcd(year), NVRAM_RTC_YEAR); + } else { + nvram_write(time->tm_mon + 1, NVRAM_RTC_MONTH); + nvram_write(time->tm_sec, NVRAM_RTC_SECONDS); + nvram_write(time->tm_min, NVRAM_RTC_MINUTES); + nvram_write(time->tm_mday, NVRAM_RTC_DAY); + if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) { + if (time->tm_hour > 12) + reg8 = (time->tm_hour - 12) | 0x80; + else + reg8 = time->tm_hour; + } else + reg8 = time->tm_hour; + nvram_write(reg8, NVRAM_RTC_HOURS); + nvram_write(year, NVRAM_RTC_YEAR); + } +} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 74969726bf..e3f8fd363f 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -151,6 +151,7 @@ u8 nvram_read(u8 addr); void nvram_write(u8 val, u8 addr); int nvram_updating(void); void rtc_read_clock(struct tm *tm); +void rtc_write_clock(const struct tm *tm); /** @} */ /** From 0fd179aeb1d63eeab414a47d38ad8dd8514edcb2 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 9 Mar 2020 09:13:09 +0100 Subject: [PATCH 0553/1463] libpayload/drivers/nvram: Fix coding style If one branch has braces all should have them. Change-Id: I94e70c6c6188768d9b37a2d154f4d5b8af31f78c Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39396 Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/nvram.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index 0196bb5c7c..1a80efef24 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -135,8 +135,9 @@ void rtc_read_clock(struct tm *time) time->tm_hour = bcd2dec(reg8 & 0x7f); time->tm_hour += (reg8 & 0x80) ? 12 : 0; time->tm_hour %= 24; - } else + } else { time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS)); + } time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR)); } else { time->tm_mon = nvram_read(NVRAM_RTC_MONTH) - 1; @@ -148,8 +149,9 @@ void rtc_read_clock(struct tm *time) time->tm_hour = reg8 & 0x7f; time->tm_hour += (reg8 & 0x80) ? 12 : 0; time->tm_hour %= 24; - } else + } else { time->tm_hour = nvram_read(NVRAM_RTC_HOURS); + } time->tm_year = nvram_read(NVRAM_RTC_YEAR); } @@ -192,8 +194,9 @@ void rtc_write_clock(const struct tm *time) reg8 = dec2bcd(time->tm_hour - 12) | 0x80; else reg8 = dec2bcd(time->tm_hour); - } else + } else { reg8 = dec2bcd(time->tm_hour); + } nvram_write(reg8, NVRAM_RTC_HOURS); nvram_write(dec2bcd(year), NVRAM_RTC_YEAR); } else { @@ -206,8 +209,9 @@ void rtc_write_clock(const struct tm *time) reg8 = (time->tm_hour - 12) | 0x80; else reg8 = time->tm_hour; - } else + } else { reg8 = time->tm_hour; + } nvram_write(reg8, NVRAM_RTC_HOURS); nvram_write(year, NVRAM_RTC_YEAR); } From e9aef1fe4548da7bf65f11aec48ff3b40e6461fa Mon Sep 17 00:00:00 2001 From: Marcello Sylvester Bauer Date: Mon, 2 Mar 2020 16:04:19 +0100 Subject: [PATCH 0554/1463] Doc/security/vboot: Add a script generated device list Add a script generated list of vboot enabled devices to the documentation. Add a entry to the release checklist. Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93 Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Patrick Georgi --- Documentation/releases/checklist.md | 1 + Documentation/security/vboot/index.md | 2 + Documentation/security/vboot/list_vboot.md | 223 +++++++++++++++++++++ util/vboot_list/description.md | 2 + util/vboot_list/vboot_list.sh | 55 +++++ 5 files changed, 283 insertions(+) create mode 100644 Documentation/security/vboot/list_vboot.md create mode 100644 util/vboot_list/description.md create mode 100755 util/vboot_list/vboot_list.sh diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index 706d08e379..ea05c2036a 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -68,6 +68,7 @@ be more frequent than was needed, so we scaled it back to twice a year. - [ ] Test the commit selected for release. - [ ] Update release notes with actual commit id, push to repo. - [ ] Run release script. +- [ ] Run vboot_list script. - [ ] Test the release from the actual release tarballs. - [ ] Push signed Tag to repo. - [ ] Announce that the release tag is done on IRC. diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index 400c2b5149..997db8be80 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -12,6 +12,8 @@ Google's verified boot support consists of: Google's vboot verifies the firmware and places measurements within the TPM. +- [List of supported Devices](list_vboot.md) + *** ## Root of Trust diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md new file mode 100644 index 0000000000..1bef8234be --- /dev/null +++ b/Documentation/security/vboot/list_vboot.md @@ -0,0 +1,223 @@ +# VBOOT enabled devices + +## Emulation +- QEMU x86 i440fx/piix4 (aka qemu -M pc) +- QEMU x86 q35/ich9 (aka qemu -M q35, since v1.4) + +## Facebook +- Facebook Monolith + +## Google +- Auron_Paine (Acer C740 Chromebook) +- Auron_Yuna (Acer Chromebook 15 (C910/CB5-531)) +- Buddy (Acer Chromebase 24) +- Gandof (Toshiba Chromebook 2 (2015)) +- Lulu (Dell Chromebook 13 7310) +- Samus (Google Chromebook Pixel (2015)) +- Mccloud (Acer Chromebox CXI) +- Monroe (LG Chromebase 22CV241 & 22CB25S) +- Panther (ASUS Chromebox CN60) +- Tricky (Dell Chromebox 3010) +- Zako (HP Chromebox G1) +- Butterfly (HP Pavilion Chromebook 14) +- Cheza +- Banon (Acer Chromebook 15 (CB3-532)) +- Celes (Samsung Chromebook 3) +- Cyan (Acer Chromebook R11 (C738T)) +- Edgar (Acer Chromebook 14 (CB3-431)) +- Kefka (Dell Chromebook 11 3180/3189) +- Reks (Lenovo N22/N42 Chromebook) +- Relm +- Setzer (HP Chromebook 11 G5) +- Terra (ASUS Chromebook C202SA/C300SA/C301SA) +- Ultima (Lenovo Yoga 11e G3) +- Wizpig +- Daisy (Samsung Chromebook (2012)) +- DragonEgg +- Drallion +- Eve (Google Pixelbook) +- Fizz +- Karma +- Endeavour +- Foster +- Gale (Google WiFi) +- Asuka (Dell Chromebook 13 3380) +- Caroline (Samsung Chromebook Pro) +- Cave (Asus Chromebook Flip C302SA) +- Chell (HP Chromebook 13 G1) +- Glados Skylake Reference Board +- Lars (Acer Chromebook 14 for Work (CP5-471)) +- Sentry (Lenovo Thinkpad 13 Chromebook) +- Kevin (Samsung Chromebook Plus) +- Gru +- Bob (Asus Chromebook Flip C101PA) +- Scarlet +- Nefario +- Rainier +- Akemi +- Dratini +- Hatch +- Jinlon +- Kohaku +- Kindred +- Helios +- Mushu +- Palkia +- Nightfury +- Puff +- Helios_Diskswap +- Stryke +- Guado (ASUS Chromebox CN62) +- Jecht +- Rikku (Acer Chromebox CXI2) +- Tidus (Lenovo ThinkCentre Chromebox) +- Aleena +- Careena +- Grunt +- Liara +- Nuwani +- Treeya +- Kukui +- Krane +- Kodama +- Kakadu +- Flapjack +- Jacuzzi +- Juniper +- Kappa +- Damu +- Link (Google Chromebook Pixel (2013)) +- Mistral +- Nyan +- Nyan Big (Acer Chromebook 13 (CB5-311)) +- Nyan Blaze (HP Chromebook 14 G3) +- Oak +- Elm (Acer Chromebook R13) +- Hana (Lenovo N23 Yoga Chromebook) +- Parrot (Acer C7/C710 Chromebook) +- Peach Pit (Samsung Chromebook 2 11\") +- Atlas +- Poppy +- Nami +- Nautilus +- Nocturne +- Rammus +- Soraka +- Banjo (Acer Chromebook 15 (CB3-531)) +- Candy (Dell Chromebook 11 3120) +- Clapper (Lenovo N20 Chromebook) +- Enguarde +- Glimmer (Lenovo ThinkPad 11e Chromebook) +- Gnawty (Acer Chromebook 11 (CB3-111/131,C730/C730E/C735)) +- Heli (Haier Chromebook G2) +- Kip (HP Chromebook 11 G3 / G4 / G4 EE) +- Ninja (AOpen Chromebox Commercial) +- Orco (Lenovo 100S Chromebook) +- Quawks (ASUS Chromebook C300) +- Squawks (ASUS Chromebook C200) +- Rambi +- Sumo (AOpen Chromebase Commercial) +- Swanky (Toshiba Chromebook 2) +- Winky (Samsung Chromebook 2 (XE500C12)) +- Reef/Electro (Acer Chromebook Spin 11 R751T) +- Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook) +- Sand (Acer Chromebook 15 CB515-1HT/1H) +- Snappy (HP Chromebook x360 11 G1 EE) +- Nasher +- Coral +- Arcada +- Sarien +- Falco (HP Chromebook 14) +- Leon (Toshiba Chromebook) +- Peppy (Acer C720/C720P Chromebook) +- Wolf (Dell Chromebook 11) +- Smaug (Google Pixel C) +- Storm (OnHub Router TGR1900) +- Stout (Lenovo Thinkpad X131e Chromebook) +- Trogdor +- Veyron_Jaq (Haier Chromebook 11) +- Veyron_Jerry (Hisense Chromebook 11) +- Veyron_Mighty (Haier Chromebook 11(edu)) +- Veyron_Minnie (ASUS Chromebook Flip C100) +- Veyron_Speedy (ASUS C201 Chromebook) +- Veyron_Mickey (Asus Chromebit CS10) +- Veyron_Rialto + +## HP +- Z220 SFF Workstation + +## Intel +- Basking Ridge CRB +- Cannonlake U LPDDR4 RVP +- Cannonlake Y LPDDR4 RVP +- Coffeelake U SO-DIMM DDR4 RVP +- Coffeelake H SO-DIMM DDR4 RVP11 +- Whiskeylake U DDR4 RVP +- Coffeelake S U-DIMM DDR4 RVP8 +- Cometlake U DDR4 RVP +- Emerald Lake 2 CRB +- Galileo +- Glkrvp +- Icelake U DDR4/LPDDR4 RVP +- Icelake Y LPDDR4 RVP +- Jasperlake DDR4/LPDDR4 RVP +- Jasperlake DDR4/LPDDR4 RVP with Chrome EC +- Kabylake LPDDR3 RVP3 +- Kabylake DDR3L RVP7 +- Kabylake DDR4 RVP8 +- Kabylake DDR4 RVP11 +- Kunimitsu +- Strago +- Tigerlake UP3 RVP +- Tigerlake UP4 RVP +- Whitetip Mountain 2 CRB + +## Lenovo +- ThinkPad T400 +- ThinkPad T500 +- ThinkPad R400 +- ThinkPad R500 +- ThinkPad W500 +- ThinkPad T410 +- ThinkPad T420 +- ThinkPad T420s +- ThinkPad T430 +- ThinkPad T430s +- ThinkPad T431s +- ThinkPad T440p +- ThinkPad T520 +- ThinkPad W520 +- ThinkPad T530 +- ThinkPad W530 +- ThinkPad X131e +- ThinkPad X1 carbon gen 1 +- ThinkPad X200 / X200s / X200t +- ThinkPad X301 +- ThinkPad X201 / X201i / X201s / X201t +- ThinkPad X220 +- ThinkPad X220i +- ThinkPad X1 +- ThinkPad X230 +- ThinkPad X230t + +## OpenCellular +- Elgon (GBCv2) + +## SAMSUNG +- Lumpy +- Stumpy + +## Siemens +- MC APL1 +- MC APL2 +- MC APL3 +- MC APL4 +- MC APL5 +- MC APL6 + +## Supermicro +- X11SSH-TF +- X11SSM-F + +## UP +- Squared diff --git a/util/vboot_list/description.md b/util/vboot_list/description.md new file mode 100644 index 0000000000..b994557f6c --- /dev/null +++ b/util/vboot_list/description.md @@ -0,0 +1,2 @@ +Tools to generate a list of vboot enabled devices to the documentation +`Bash` diff --git a/util/vboot_list/vboot_list.sh b/util/vboot_list/vboot_list.sh new file mode 100755 index 0000000000..f3e8975e96 --- /dev/null +++ b/util/vboot_list/vboot_list.sh @@ -0,0 +1,55 @@ +#!/usr/bin/env bash + +TOP="$( cd "$( dirname "${BASH_SOURCE[0]}" )"/../.. >/dev/null 2>&1 && pwd )" +MAINBOARDS="src/mainboard" +OUTPUT_FILE=${1:-$TOP/Documentation/security/vboot/list_vboot.md} + +function has_vboot +{ + local DIR=$1 + + grep -rq "config VBOOT" $DIR + return $? +} + +function get_vendor_name +{ + local VENDORDIR=$1 + + sed -n '/config VENDOR/{n;s/^[\t[:space:]]\+bool "\(.*\)"/\1/;p;}' \ + $VENDORDIR/Kconfig.name +} + +function get_board_name +{ + local BOARDDIR=$1 + + sed -n '/config BOARD/{n;s/^[\t[:space:]]\+bool "\(->\s\+\)\?\(.*\)"/\2/;p;}' \ + $BOARDDIR/Kconfig.name +} + +function list_vboot_boards +{ + local VENDORDIR=$1 + for BOARD in $(ls -d $VENDORDIR/*/) + do + has_vboot $BOARD || continue + get_board_name $BOARD + done +} + +function generate_vboot_list +{ +for VENDOR in $(ls -d $TOP/$MAINBOARDS/*/) +do + has_vboot $VENDOR || continue + echo -e "\n## $(get_vendor_name $VENDOR)" + IFS=$'\n' + for BOARD in $(list_vboot_boards $VENDOR) + do + echo "- $BOARD" + done +done +} + +(echo "# VBOOT enabled devices"; generate_vboot_list) > $OUTPUT_FILE From a5b0bc4b34a553aa17d087fce4d371ea138c00a9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 20 Feb 2020 20:04:29 +0100 Subject: [PATCH 0555/1463] src: capitalize 'APIC' Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/arch/x86/cpu.c | 2 +- .../emulation/qemu-i440fx/acpi/cpu-hotplug.asl | 6 +++--- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00660F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/soc/intel/baytrail/include/soc/gpio.h | 14 +++++++------- src/soc/intel/broadwell/smi.c | 2 +- src/southbridge/intel/i82801dx/smi.c | 2 +- src/southbridge/intel/i82801ix/smi.c | 2 +- src/southbridge/intel/i82870/82870.h | 2 +- src/southbridge/intel/i82870/ioapic.c | 4 ++-- src/southbridge/intel/lynxpoint/smi.c | 2 +- 14 files changed, 23 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 4c1bce05d6..8f8fdc1fd0 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -211,7 +211,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -/* Keep track of default apic ids for SMM. */ +/* Keep track of default APIC ids for SMM. */ static int cpus_default_apic_id[CONFIG_MAX_CPUS]; /* diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl index 353080194f..e46611d219 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl @@ -22,13 +22,13 @@ Scope(\_SB) { /* Methods called by run-time generated SSDT Processor objects */ Method(CPMA, 1, NotSerialized) { - // _MAT method - create an madt apic buffer + // _MAT method - create an madt APIC buffer // Arg0 = Processor ID = Local APIC ID // Local0 = CPON flag for this cpu Store(DerefOf(Index(CPON, Arg0)), Local0) - // Local1 = Buffer (in madt apic form) to return + // Local1 = Buffer (in madt APIC form) to return Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) - // Update the processor id, lapic id, and enable/disable status + // Update the processor id, Local APIC id, and enable/disable status Store(Arg0, Index(Local1, 2)) Store(Arg0, Index(Local1, 3)) Store(Local0, Index(Local1, 4)) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 3519ab0e5b..642fc150e1 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -859,7 +859,7 @@ static void cpu_bus_scan(struct device *dev) * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 96d71cdc18..fcd7ec1fe6 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -886,7 +886,7 @@ static void cpu_bus_scan(struct device *dev) * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 2df105a4fb..28502b0017 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -864,7 +864,7 @@ static void cpu_bus_scan(struct device *dev) * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 855936af79..0a1b0ba1a4 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -871,7 +871,7 @@ static void cpu_bus_scan(struct device *dev) * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8f23e682e1..05c5142a70 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1130,7 +1130,7 @@ static void cpu_bus_scan(struct device *dev) * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index d6be80fde2..3c1e7f37dd 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -196,49 +196,49 @@ .io_sel = GPIO_DIR_INPUT, \ .is_gpio = 1 } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELHIGH_NO_PULL \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELLOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEHIGH_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEBOTH_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \ diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index b26700e267..b1be1faa69 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -71,7 +71,7 @@ static void __unused southbridge_trigger_smi(void) * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 0de98aca9a..26dfc60e5b 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -305,7 +305,7 @@ static void aseg_smm_relocate(void) * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 25d3515134..6e7463fcd3 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -111,7 +111,7 @@ static void aseg_smm_relocate(void) * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index 1fe40b6e6f..ce76db0682 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -/* for io apic 1461 */ +/* for io APIC 1461 */ #define MBAR 0x10 #define ABAR 0x40 diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 4fbf329342..1f4aa501a8 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -43,8 +43,8 @@ static void p64h2_ioapic_init(struct device *dev) uint32_t memoryBase; int apic_index, apic_id; - volatile uint32_t *pIndexRegister; /* io apic io memory space command address */ - volatile uint32_t *pWindowRegister; /* io apic io memory space data address */ + volatile uint32_t *pIndexRegister; /* io APIC io memory space command address */ + volatile uint32_t *pWindowRegister; /* io APIC io memory space data address */ apic_index = num_p64h2_ioapics; num_p64h2_ioapics++; diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index ed3c6cce7b..6aef493ee1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -76,7 +76,7 @@ static void __unused southbridge_trigger_smi(void) * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so From 97ea709d42eb8c4eb5b2c75d6203034d51946b03 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 20 Mar 2020 12:26:21 -0600 Subject: [PATCH 0556/1463] mb/google/dedede: Update SPD index for waddledee Micron memory part uses SPD Index 0. BUG=b:152005386 TEST=Build the mainboard. Change-Id: I990a95b13d636148f0f922fd5c6d4e489d35ed2c Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/39709 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/variants/waddledee/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index 3e06d73658..b1aba0eeff 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -5,6 +5,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## -SPD_SOURCES = empty #0b0000 -SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 +SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 +SPD_SOURCES += empty #0b0001 SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010 From 79a219813b3e8186f5e89b2e0cd9f8a921fa088f Mon Sep 17 00:00:00 2001 From: Daniel Kang Date: Thu, 19 Mar 2020 14:12:30 -0700 Subject: [PATCH 0557/1463] src/mb/intel/tglrvp: Fix board config flag for TGL-UP4 camera ACPI Camera ACPI had an incorrect board config flag for TGL-UP4. BUG=None BRANCH=None TEST=Build and boot TGLRVP-UP3 or UP4. Start camera app and able to capture images. Signed-off-by: Daniel Kang Change-Id: Ided0e146a9240169d3f1f27a86218ac1a942b899 Signed-off-by: Daniel Kang Reviewed-on: https://review.coreboot.org/c/coreboot/+/39682 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/mainboard/intel/tglrvp/acpi/mipi_camera.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 9cb8817098..de26fd9d05 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -390,10 +390,10 @@ Scope (\_SB.PCI0.I2C5) CTXS(GPP_H12) /* Pull PWREN high */ -#if CONFIG_BOARD_INTEL_TIGERLAKE_RVPY - STXS(GPP_E22) +#if CONFIG(BOARD_INTEL_TGLRVP_UP4) + STXS(GPP_E22) #else - STXS(GPP_R6) + STXS(GPP_R6) #endif Sleep(2) /* reset pulse width */ @@ -416,8 +416,8 @@ Scope (\_SB.PCI0.I2C5) CTXS(GPP_H12) /* Pull PWREN low */ -#if CONFIG_BOARD_INTEL_TIGERLAKE_RVPY - CTXS(GPP_E22) +#if CONFIG(BOARD_INTEL_TGLRVP_UP4) + CTXS(GPP_E22) #else CTXS(GPP_R6) #endif From 6975e07997cedf8a78f0704a461765dfe2a09fe6 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 12 Mar 2020 01:22:01 -0700 Subject: [PATCH 0558/1463] mb/tglrvp: Update Audio AIC settings for Tiger Lake Update Audio AIC UPD settings and gpio pad configs for Tiger Lake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- .../tglrvp/variants/tglrvp_up3/devicetree.cb | 4 ++- .../intel/tglrvp/variants/tglrvp_up3/gpio.c | 25 +++++++++++-------- .../tglrvp/variants/tglrvp_up4/devicetree.cb | 4 ++- .../intel/tglrvp/variants/tglrvp_up4/gpio.c | 24 ++++++++++-------- 4 files changed, 34 insertions(+), 23 deletions(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 41a361c016..23737c3070 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -101,7 +101,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "0" + register "PchHdaAudioLinkSspEnable[2]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T register "PchHdaIDispLinkTmode" = "2" # iDisp-Link Freq 4: 96MHz, 3: 48MHz. diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 4b600e6d0b..758a21c5c9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -60,10 +60,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + /* CNVi */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ - }; /* Early pad configuration in bootblock */ @@ -71,23 +73,24 @@ static const struct pad_config early_gpio_table[] = { /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), /* I2S0_HP_TX */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), /* HDA_RST_L */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SPKR_SCLK */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* I2S2_SPKR_SFRM */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* I2S2_SPKR_TX */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* I2S2_SPKR_RX */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK_A */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK_A */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ /* DP */ PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 586fd26da7..f2e5510147 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -97,7 +97,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "0" + register "PchHdaAudioLinkSspEnable[2]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T register "PchHdaIDispLinkTmode" = "2" # iDisp-Link Freq 4: 96MHz, 3: 48MHz. diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 3ee9ec7022..219786535a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -60,6 +60,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + }; /* Early pad configuration in bootblock */ @@ -67,23 +70,24 @@ static const struct pad_config early_gpio_table[] = { /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), /* I2S0_HP_TX */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), /* HDA_RST_L */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SPKR_SCLK */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* I2S2_SPKR_SFRM */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* I2S2_SPKR_TX */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* I2S2_SPKR_RX */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK_A */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK_A */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ /* DP */ PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ From 12b86b6433a9707580c485067e2ceba83e513417 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 20 Mar 2020 09:30:57 +0100 Subject: [PATCH 0559/1463] soc/intel/cfl/vr_config: Add 8-core desktop CPU support Add 8-core desktop CPU support by adding the corresponding PCI IDs. Tested using "Intel Core(TM) i7-9700E". Change-Id: I7a2e2e5fd1796deff81b032450242fb58031526d Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39691 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/vr_config.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 21a8ae2c46..af3f1ecd0d 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -202,6 +202,7 @@ static uint16_t get_sku_icc_max(int domain) return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8: /* fallthrough */ case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8: { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45); @@ -356,6 +357,7 @@ static uint16_t get_sku_ac_dc_loadline(const int domain) } return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8: /* fallthrough */ case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8: { /* FIXME: Loadline isn't specified for S-series, using H-series default */ const uint16_t loadline[NUM_VR_DOMAINS] = From 6ebb7394f97a387e0503b7b4035647f2d5df331f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 10 Jan 2020 16:33:18 +0100 Subject: [PATCH 0560/1463] mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38343 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/pcengines/apu1/buildOpts.c | 2 +- src/mainboard/pcengines/apu1/mainboard.c | 93 ++++++++++++++++++++++++ 2 files changed, 94 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 2b73fb1dcb..f2e4ab5fe2 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -87,7 +87,7 @@ #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_SLIT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_DMI FALSE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 14eab8b490..d72a8fbcef 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -13,6 +13,8 @@ */ #include +#include +#include #include #include #include @@ -23,6 +25,7 @@ #include #include #include +#include #include #include #include "gpio_ftns.h" @@ -173,6 +176,93 @@ static void config_addon_uart(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, unsigned long *current) +{ + struct smbios_type16 *t; + u32 max_capacity; + int len; + + t = (struct smbios_type16 *)*current; + len = sizeof(struct smbios_type16); + memset(t, 0, len); + max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */ + + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = *handle; + t->length = len - 2; + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->memory_error_correction = agesa_dmi->T16.MemoryErrorCorrection; + t->maximum_capacity = max_capacity * 1024 * 1024; + t->memory_error_information_handle = 0xfffe; + t->number_of_memory_devices = 1; + + *current += len; + + return len; +} + +static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, unsigned long *current) +{ + struct smbios_type17 *t; + int len; + + t = (struct smbios_type17 *)*current; + memset(t, 0, sizeof(struct smbios_type17)); + + t->type = SMBIOS_MEMORY_DEVICE; + t->length = sizeof(struct smbios_type17) - 2; + t->handle = *handle + 1; + t->phys_memory_array_handle = *handle; + t->memory_error_information_handle = 0xfffe; + t->total_width = agesa_dmi->T17[0][0][0].TotalWidth; + t->data_width = agesa_dmi->T17[0][0][0].DataWidth; + t->size = agesa_dmi->T17[0][0][0].MemorySize; + /* AGESA DMI returns form factor = 0, override it with SPD value */ + t->form_factor = MEMORY_FORMFACTOR_SODIMM; + t->device_set = agesa_dmi->T17[0][0][0].DeviceSet; + t->device_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].DeviceLocator); + t->bank_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].BankLocator); + t->memory_type = agesa_dmi->T17[0][0][0].MemoryType; + t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail; + t->speed = agesa_dmi->T17[0][0][0].Speed; + t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode; + t->serial_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].SerialNumber); + t->part_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].PartNumber); + t->attributes = agesa_dmi->T17[0][0][0].Attributes; + t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; + t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed; + t->minimum_voltage = 1500; /* From SPD: 1.5V */ + t->maximum_voltage = 1500; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + + return len; +} + +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + DMI_INFO *agesa_dmi; + int len; + + agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + len = mainboard_smbios_type16(agesa_dmi, handle, current); + len += mainboard_smbios_type17(agesa_dmi, handle, current); + + *handle += 2; + + return len; +} +#endif + static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -194,6 +284,9 @@ static void mainboard_enable(struct device *dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif } /* From 205a5620af30ba3ba31feb2bc91062c0eb13e5c6 Mon Sep 17 00:00:00 2001 From: Prashant Malani Date: Thu, 19 Mar 2020 12:32:00 -0700 Subject: [PATCH 0561/1463] mb/google/volteer: Enable PD_MCU device This is required for PD notifications on the cros_ec driver. BUG=b:150649744 TEST=Boot volteer with this patch and verify that PD notifier events are being generated. Signed-off-by: Prashant Malani Change-Id: I2e72320b025a3dfa7412181586cb142a4503eda5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39675 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/baseboard/include/baseboard/ec.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h index a8ba27c84f..3d89e3c1c9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -71,4 +71,7 @@ /* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ #define EC_ENABLE_SYNC_IRQ +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + #endif /* __MAINBOARD_EC_H__ */ From 140a4ae7bf2960ac7d095ba94847093f4755bf04 Mon Sep 17 00:00:00 2001 From: Daniel Kang Date: Thu, 19 Mar 2020 16:46:38 -0700 Subject: [PATCH 0562/1463] src/mb/google/volteer: Add camera ACPI configuration Add camera ACPI configuration for Ripto/Volteer BUG=None BRANCH=None TEST=Build and boot Ripto or Volteer. Start camera app and able to capture images. Signed-off-by: Daniel Kang Change-Id: I2b47ccd989192273a29f09bf097e12e357929334 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39684 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- .../google/volteer/acpi/mipi_camera.asl | 613 ++++++++++++++++++ src/mainboard/google/volteer/dsdt.asl | 3 + 2 files changed, 616 insertions(+) create mode 100644 src/mainboard/google/volteer/acpi/mipi_camera.asl diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/acpi/mipi_camera.asl new file mode 100644 index 0000000000..7c2ca61198 --- /dev/null +++ b/src/mainboard/google/volteer/acpi/mipi_camera.asl @@ -0,0 +1,613 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 5 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 1 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C2.CAM1, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C3) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(3,1) /* Clock 3, 19.2MHz */ + + /* Pull RST low */ +#if CONFIG(BOARD_GOOGLE_VOLTEER) + CTXS(GPP_F15) +#else + CTXS(GPP_D4) +#endif + + /* Pull PWREN high */ + STXS(GPP_H20) + Sleep(2) /* reset pulse width */ + + /* Pull RST high */ +#if CONFIG(BOARD_GOOGLE_VOLTEER) + STXS(GPP_F15) +#else + STXS(GPP_D4) +#endif + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(3) /* Clock 3 */ + + /* Pull RST low */ +#if CONFIG(BOARD_GOOGLE_VOLTEER) + CTXS(GPP_F15) +#else + CTXS(GPP_D4) +#endif + + /* Pull PWREN low */ + CTXS(GPP_H20) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x02) + { + 0x15752A00, + 0xABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "GT9769 VCM") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "giantec,gt9769-vcm" + } + } + }) + } + Device (NVM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_DDN, "GT9769 EEPROM") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBusV2 (0x0058, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM0 + }) + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x05) + { + Package (0x02) + { + "size", + 0x2800 + }, + Package (0x02) + { + "pagesize", + One + }, + Package (0x02) + { + "read-only", + One + }, + Package (0x02) + { + "address-width", + 0x0D + }, + Package (0x02) + { + "compatible", + "giantec,gt9769-eeprom" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C2) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(2,1) /* Clock 2, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_D4) + + /* Pull SNRPWR_EN high */ + STXS(GPP_D18) + + /* Pull PWREN high */ + STXS(GPP_D17) + Sleep(10) /* t9 */ + + /* Pull RST high */ + STXS(GPP_D4) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(2) /* Clock 2 */ + + /* Pull RST low */ + CTXS(GPP_D4) + + /* Pull PWREN low */ + CTXS(GPP_D17) + + /* Pull SNRPWR_EN low */ + CTXS(GPP_D18) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI2740") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 2740 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0xABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 4533f8937d..d2599260d7 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,4 +47,7 @@ DefinitionBlock( } #include + /* Camera */ + #include + #include "acpi/mipi_camera.asl" } From aee7ab2f6e69b70414f8225cb7a83c3e4cb62d9a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Mar 2020 00:31:58 +0100 Subject: [PATCH 0563/1463] soc/intel/braswell: Clean up Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected. Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/acpi.c | 57 ++- src/soc/intel/braswell/bootblock/bootblock.c | 16 +- src/soc/intel/braswell/chip.c | 462 +++++++++---------- src/soc/intel/braswell/chip.h | 175 ++++--- src/soc/intel/braswell/cpu.c | 42 +- src/soc/intel/braswell/elog.c | 6 +- src/soc/intel/braswell/emmc.c | 3 +- src/soc/intel/braswell/gfx.c | 14 +- src/soc/intel/braswell/gpio.c | 163 +++---- src/soc/intel/braswell/gpio_support.c | 36 +- src/soc/intel/braswell/include/soc/gpio.h | 2 + src/soc/intel/braswell/lpc_init.c | 49 +- src/soc/intel/braswell/lpe.c | 29 +- src/soc/intel/braswell/lpss.c | 31 +- src/soc/intel/braswell/memmap.c | 2 +- src/soc/intel/braswell/pcie.c | 34 +- src/soc/intel/braswell/pmutil.c | 23 +- src/soc/intel/braswell/ramstage.c | 11 +- src/soc/intel/braswell/romstage/romstage.c | 79 ++-- src/soc/intel/braswell/sata.c | 3 +- src/soc/intel/braswell/sd.c | 16 +- src/soc/intel/braswell/smihandler.c | 83 ++-- src/soc/intel/braswell/smm.c | 2 + src/soc/intel/braswell/southcluster.c | 192 ++++---- src/soc/intel/braswell/tsc_freq.c | 23 +- src/soc/intel/braswell/xhci.c | 6 +- 26 files changed, 722 insertions(+), 837 deletions(-) diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 413b9972d4..765be82c40 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -250,13 +250,13 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) static acpi_tstate_t soc_tss_table[] = { { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1e, 0 }, - { 75, 750, 0, 0x1c, 0 }, - { 63, 625, 0, 0x1a, 0 }, - { 50, 500, 0, 0x18, 0 }, - { 38, 375, 0, 0x16, 0 }, - { 25, 250, 0, 0x14, 0 }, - { 13, 125, 0, 0x12, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, }; static void generate_t_state_entries(int core, int cores_per_package) @@ -271,24 +271,23 @@ static void generate_t_state_entries(int core, int cores_per_package) acpigen_write_TPC("\\TLVL"); /* Write TSS table for MSR access */ - acpigen_write_TSS_package( - ARRAY_SIZE(soc_tss_table), soc_tss_table); + acpigen_write_TSS_package(ARRAY_SIZE(soc_tss_table), soc_tss_table); } static int calculate_power(int tdp, int p1_ratio, int ratio) { - u32 m; - u32 power; + u32 m, power; /* * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp */ m = (110000 - ((p1_ratio - ratio) * 625)) / 11; m = (m * m) / 1000; + /* + * Power = (ratio / p1_ratio) * m * TDP + */ power = ((ratio * 100000 / p1_ratio) / 100); power *= (m / 100) * (tdp / 1000); power /= 1000; @@ -387,8 +386,8 @@ static void generate_p_state_entries(int core, int cores_per_package) ratio >= ratio_min; ratio -= ratio_step) { /* Calculate VID for this ratio */ - vid = ((ratio - ratio_min) * vid_range_2) / - ratio_range_2 + vid_min; + vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min; + /* Round up if remainder */ if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) vid++; @@ -424,20 +423,16 @@ void generate_cpu_entries(struct device *device) } /* Generate processor \_PR.CPUx */ - acpigen_write_processor( - core, pcontrol_blk, plen); + acpigen_write_processor(core, pcontrol_blk, plen); /* Generate P-state tables */ - generate_p_state_entries( - core, pattrs->num_cpus); + generate_p_state_entries(core, pattrs->num_cpus); /* Generate C-state tables */ - acpigen_write_CST_package( - cstate_map, ARRAY_SIZE(cstate_map)); + acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - generate_t_state_entries( - core, pattrs->num_cpus); + generate_t_state_entries(core, pattrs->num_cpus); acpigen_pop_len(); } @@ -466,8 +461,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) sci_flags |= MP_IRQ_POLARITY_HIGH; irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); return current; } @@ -480,8 +474,7 @@ static int update_igd_opregion(igd_opregion_t *opregion) return 0; } -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long current, +unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { acpi_header_t *ssdt2; @@ -511,9 +504,9 @@ unsigned long southcluster_write_acpi_tables(struct device *device, if (ssdt2->length) { current += ssdt2->length; acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, - ssdt2->length); + printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, ssdt2->length); current = acpi_align_current(current); + } else { ssdt2 = NULL; printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); @@ -537,15 +530,17 @@ void southcluster_inject_dsdt(struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); - /* Fill in the Wifi Region id */ + + /* Fill in the Wi-Fi Region ID */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) gnvs->cid1 = wifi_regulatory_domain(); else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); - /* Add it to DSDT. */ + /* Add it to DSDT */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_pop_len(); diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 11bff97544..aa8df6ba5e 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -90,11 +90,8 @@ static void soc_rtc_init(void) int rtc_failed = rtc_failure(); if (rtc_failed) { - printk(BIOS_ERR, - "RTC Failure detected. Resetting date to %x/%x/%x%x\n", - COREBOOT_BUILD_MONTH_BCD, - COREBOOT_BUILD_DAY_BCD, - 0x20, + printk(BIOS_ERR, "RTC Failure detected. Resetting date to %x/%x/%x%x\n", + COREBOOT_BUILD_MONTH_BCD, COREBOOT_BUILD_DAY_BCD, 0x20, COREBOOT_BUILD_YEAR_BCD); } @@ -106,10 +103,9 @@ static void setup_mmconfig(void) uint32_t reg; /* - * Set up the MMCONF range. The register lives in the BUNIT. The - * IO variant of the config access needs to be used initially to - * properly configure as the IOSF access registers live in PCI - * config space. + * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the + * config access needs to be used initially to properly configure as the IOSF access + * registers live in PCI config space. */ reg = 0; /* Clear the extended register. */ @@ -124,7 +120,7 @@ static void setup_mmconfig(void) void bootblock_soc_early_init(void) { - /* Allow memory-mapped PCI config access. */ + /* Allow memory-mapped PCI config access */ setup_mmconfig(); /* Early chipset initialization */ diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e1918d4e48..90ee850cd9 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -24,8 +24,7 @@ static void pci_domain_set_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); assign_resources(dev->link_list); } @@ -47,16 +46,15 @@ static struct device_operations cpu_bus_ops = { static void enable_dev(struct device *dev) { - printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", - __FILE__, __func__, + printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", __FILE__, __func__, dev_name(dev), dev->path.type); + printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", pci_read_config16(dev, PCI_VENDOR_ID), pci_read_config16(dev, PCI_DEVICE_ID)); - printk(BIOS_SPEW, "class: 0x%02x %s\n" - "subclass: 0x%02x %s\n" - "prog: 0x%02x\n" - "revision: 0x%02x\n", + + printk(BIOS_SPEW, "class: 0x%02x %s\nsubclass: 0x%02x %s\n" + "prog: 0x%02x\nrevision: 0x%02x\n", pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8, get_pci_class_name(dev), pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff, @@ -67,8 +65,10 @@ static void enable_dev(struct device *dev) /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { /* Handle south cluster enablement. */ if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && @@ -88,9 +88,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) struct soc_intel_braswell_config *config; if (!dev) { - printk(BIOS_ERR, - "Error! Device (%s) not found, " - "soc_silicon_init_params!\n", dev_path(dev)); + printk(BIOS_ERR, "Error! Device (%s) not found, soc_silicon_init_params!\n", + dev_path(dev)); return; } @@ -98,83 +97,81 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) /* Set the parameters for SiliconInit */ printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); - params->PcdSdcardMode = config->PcdSdcardMode; - params->PcdEnableHsuart0 = config->PcdEnableHsuart0; - params->PcdEnableHsuart1 = config->PcdEnableHsuart1; - params->PcdEnableAzalia = config->PcdEnableAzalia; - params->PcdEnableSata = config->PcdEnableSata; - params->PcdEnableXhci = config->PcdEnableXhci; - params->PcdEnableLpe = config->PcdEnableLpe; - params->PcdEnableDma0 = config->PcdEnableDma0; - params->PcdEnableDma1 = config->PcdEnableDma1; - params->PcdEnableI2C0 = config->PcdEnableI2C0; - params->PcdEnableI2C1 = config->PcdEnableI2C1; - params->PcdEnableI2C2 = config->PcdEnableI2C2; - params->PcdEnableI2C3 = config->PcdEnableI2C3; - params->PcdEnableI2C4 = config->PcdEnableI2C4; - params->PcdEnableI2C5 = config->PcdEnableI2C5; - params->PcdEnableI2C6 = config->PcdEnableI2C6; - params->GraphicsConfigPtr = 0; - params->AzaliaConfigPtr = 0; - params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; - params->ChvSvidConfig = config->ChvSvidConfig; - params->DptfDisable = config->DptfDisable; - params->PcdEmmcMode = config->PcdEmmcMode; - params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; - params->PcdDispClkSsc = config->PcdDispClkSsc; - params->PcdSataClkSsc = config->PcdSataClkSsc; - params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; - params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; - params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; - params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; + params->PcdSdcardMode = config->PcdSdcardMode; + params->PcdEnableHsuart0 = config->PcdEnableHsuart0; + params->PcdEnableHsuart1 = config->PcdEnableHsuart1; + params->PcdEnableAzalia = config->PcdEnableAzalia; + params->PcdEnableSata = config->PcdEnableSata; + params->PcdEnableXhci = config->PcdEnableXhci; + params->PcdEnableLpe = config->PcdEnableLpe; + params->PcdEnableDma0 = config->PcdEnableDma0; + params->PcdEnableDma1 = config->PcdEnableDma1; + params->PcdEnableI2C0 = config->PcdEnableI2C0; + params->PcdEnableI2C1 = config->PcdEnableI2C1; + params->PcdEnableI2C2 = config->PcdEnableI2C2; + params->PcdEnableI2C3 = config->PcdEnableI2C3; + params->PcdEnableI2C4 = config->PcdEnableI2C4; + params->PcdEnableI2C5 = config->PcdEnableI2C5; + params->PcdEnableI2C6 = config->PcdEnableI2C6; + params->GraphicsConfigPtr = 0; + params->AzaliaConfigPtr = 0; + params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; + params->ChvSvidConfig = config->ChvSvidConfig; + params->DptfDisable = config->DptfDisable; + params->PcdEmmcMode = config->PcdEmmcMode; + params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; + params->PcdDispClkSsc = config->PcdDispClkSsc; + params->PcdSataClkSsc = config->PcdSataClkSsc; - params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; - params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; - params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; - params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; + params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; + params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; + params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; + params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; - params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; - params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; - params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; - params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; + params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; + params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; + params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; + params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; - params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; - params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; - params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; - params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; + params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; + params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; + params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; + params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; - params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; - params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; - params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; - params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; + params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; + params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; + params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; + params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; - params->Usb3Lane0Ow2tapgen2deemph3p5 = - config->Usb3Lane0Ow2tapgen2deemph3p5; - params->Usb3Lane1Ow2tapgen2deemph3p5 = - config->Usb3Lane1Ow2tapgen2deemph3p5; - params->Usb3Lane2Ow2tapgen2deemph3p5 = - config->Usb3Lane2Ow2tapgen2deemph3p5; - params->Usb3Lane3Ow2tapgen2deemph3p5 = - config->Usb3Lane3Ow2tapgen2deemph3p5; - params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; - params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; - params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; - params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; - params->PcdPchSsicEnable = config->PcdPchSsicEnable; - params->PcdLogoPtr = config->PcdLogoPtr; - params->PcdLogoSize = config->PcdLogoSize; - params->PcdRtcLock = config->PcdRtcLock; - params->PMIC_I2CBus = config->PMIC_I2CBus; - params->ISPEnable = config->ISPEnable; - params->ISPPciDevConfig = config->ISPPciDevConfig; - params->PcdSdDetectChk = config->PcdSdDetectChk; - params->I2C0Frequency = config->I2C0Frequency; - params->I2C1Frequency = config->I2C1Frequency; - params->I2C2Frequency = config->I2C2Frequency; - params->I2C3Frequency = config->I2C3Frequency; - params->I2C4Frequency = config->I2C4Frequency; - params->I2C5Frequency = config->I2C5Frequency; - params->I2C6Frequency = config->I2C6Frequency; + params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; + params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; + params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; + params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; + + params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5; + params->Usb3Lane1Ow2tapgen2deemph3p5 = config->Usb3Lane1Ow2tapgen2deemph3p5; + params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5; + params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5; + + params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; + params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; + params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; + params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; + params->PcdPchSsicEnable = config->PcdPchSsicEnable; + params->PcdLogoPtr = config->PcdLogoPtr; + params->PcdLogoSize = config->PcdLogoSize; + params->PcdRtcLock = config->PcdRtcLock; + params->PMIC_I2CBus = config->PMIC_I2CBus; + params->ISPEnable = config->ISPEnable; + params->ISPPciDevConfig = config->ISPPciDevConfig; + params->PcdSdDetectChk = config->PcdSdDetectChk; + params->I2C0Frequency = config->I2C0Frequency; + params->I2C1Frequency = config->I2C1Frequency; + params->I2C2Frequency = config->I2C2Frequency; + params->I2C3Frequency = config->I2C3Frequency; + params->I2C4Frequency = config->I2C4Frequency; + params->I2C5Frequency = config->I2C5Frequency; + params->I2C6Frequency = config->I2C6Frequency; board_silicon_USB2_override(params); } @@ -184,48 +181,43 @@ const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) return fsp_load_logo(¶ms->PcdLogoPtr, ¶ms->PcdLogoSize); } -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new) +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { /* Display the parameters for SiliconInit */ printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); - fsp_display_upd_value("PcdSdcardMode", 1, old->PcdSdcardMode, - new->PcdSdcardMode); - fsp_display_upd_value("PcdEnableHsuart0", 1, old->PcdEnableHsuart0, - new->PcdEnableHsuart0); - fsp_display_upd_value("PcdEnableHsuart1", 1, old->PcdEnableHsuart1, - new->PcdEnableHsuart1); - fsp_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia, - new->PcdEnableAzalia); + + fsp_display_upd_value("PcdSdcardMode", 1, + old->PcdSdcardMode, + new->PcdSdcardMode); + fsp_display_upd_value("PcdEnableHsuart0", 1, + old->PcdEnableHsuart0, + new->PcdEnableHsuart0); + fsp_display_upd_value("PcdEnableHsuart1", 1, + old->PcdEnableHsuart1, + new->PcdEnableHsuart1); + fsp_display_upd_value("PcdEnableAzalia", 1, + old->PcdEnableAzalia, + new->PcdEnableAzalia); fsp_display_upd_value("AzaliaConfigPtr", 4, - (uint32_t)old->AzaliaConfigPtr, - (uint32_t)new->AzaliaConfigPtr); - fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, - new->PcdEnableSata); - fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, - new->PcdEnableXhci); - fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, - new->PcdEnableLpe); - fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, - new->PcdEnableDma0); - fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, - new->PcdEnableDma1); - fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, - new->PcdEnableI2C0); - fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, - new->PcdEnableI2C1); - fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, - new->PcdEnableI2C2); - fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, - new->PcdEnableI2C3); - fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, - new->PcdEnableI2C4); - fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, - new->PcdEnableI2C5); - fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, - new->PcdEnableI2C6); + (uint32_t)old->AzaliaConfigPtr, + (uint32_t)new->AzaliaConfigPtr); + + fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, new->PcdEnableSata); + fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, new->PcdEnableXhci); + fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, new->PcdEnableLpe); + fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, new->PcdEnableDma0); + fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, new->PcdEnableDma1); + fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, new->PcdEnableI2C0); + fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, new->PcdEnableI2C1); + fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, new->PcdEnableI2C2); + fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, new->PcdEnableI2C3); + fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, new->PcdEnableI2C4); + fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, new->PcdEnableI2C5); + fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, new->PcdEnableI2C6); + fsp_display_upd_value("PcdGraphicsConfigPtr", 4, - old->GraphicsConfigPtr, new->GraphicsConfigPtr); + old->GraphicsConfigPtr, + new->GraphicsConfigPtr); fsp_display_upd_value("GpioFamilyInitTablePtr", 4, (uint32_t)old->GpioFamilyInitTablePtr, (uint32_t)new->GpioFamilyInitTablePtr); @@ -233,117 +225,111 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, (uint32_t)old->GpioPadInitTablePtr, (uint32_t)new->GpioPadInitTablePtr); fsp_display_upd_value("PunitPwrConfigDisable", 1, - old->PunitPwrConfigDisable, - new->PunitPwrConfigDisable); - fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, - new->ChvSvidConfig); - fsp_display_upd_value("DptfDisable", 1, old->DptfDisable, - new->DptfDisable); - fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, - new->PcdEmmcMode); - fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, - new->PcdUsb3ClkSsc); - fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, - new->PcdDispClkSsc); - fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, - new->PcdSataClkSsc); + old->PunitPwrConfigDisable, + new->PunitPwrConfigDisable); + + fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, new->ChvSvidConfig); + fsp_display_upd_value("DptfDisable", 1, old->DptfDisable, new->DptfDisable); + fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, new->PcdEmmcMode); + fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, new->PcdUsb3ClkSsc); + fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, new->PcdDispClkSsc); + fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, new->PcdSataClkSsc); + fsp_display_upd_value("Usb2Port0PerPortPeTxiSet", 1, - old->Usb2Port0PerPortPeTxiSet, - new->Usb2Port0PerPortPeTxiSet); + old->Usb2Port0PerPortPeTxiSet, + new->Usb2Port0PerPortPeTxiSet); fsp_display_upd_value("Usb2Port0PerPortTxiSet", 1, - old->Usb2Port0PerPortTxiSet, - new->Usb2Port0PerPortTxiSet); + old->Usb2Port0PerPortTxiSet, + new->Usb2Port0PerPortTxiSet); fsp_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1, - old->Usb2Port0IUsbTxEmphasisEn, - new->Usb2Port0IUsbTxEmphasisEn); + old->Usb2Port0IUsbTxEmphasisEn, + new->Usb2Port0IUsbTxEmphasisEn); fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, - old->Usb2Port0PerPortTxPeHalf, - new->Usb2Port0PerPortTxPeHalf); + old->Usb2Port0PerPortTxPeHalf, + new->Usb2Port0PerPortTxPeHalf); fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, - old->Usb2Port1PerPortPeTxiSet, - new->Usb2Port1PerPortPeTxiSet); + old->Usb2Port1PerPortPeTxiSet, + new->Usb2Port1PerPortPeTxiSet); fsp_display_upd_value("Usb2Port1PerPortTxiSet", 1, - old->Usb2Port1PerPortTxiSet, - new->Usb2Port1PerPortTxiSet); + old->Usb2Port1PerPortTxiSet, + new->Usb2Port1PerPortTxiSet); fsp_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1, - old->Usb2Port1IUsbTxEmphasisEn, - new->Usb2Port1IUsbTxEmphasisEn); + old->Usb2Port1IUsbTxEmphasisEn, + new->Usb2Port1IUsbTxEmphasisEn); fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, - old->Usb2Port1PerPortTxPeHalf, - new->Usb2Port1PerPortTxPeHalf); + old->Usb2Port1PerPortTxPeHalf, + new->Usb2Port1PerPortTxPeHalf); fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, - old->Usb2Port2PerPortPeTxiSet, - new->Usb2Port2PerPortPeTxiSet); + old->Usb2Port2PerPortPeTxiSet, + new->Usb2Port2PerPortPeTxiSet); fsp_display_upd_value("Usb2Port2PerPortTxiSet", 1, - old->Usb2Port2PerPortTxiSet, - new->Usb2Port2PerPortTxiSet); + old->Usb2Port2PerPortTxiSet, + new->Usb2Port2PerPortTxiSet); fsp_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1, - old->Usb2Port2IUsbTxEmphasisEn, - new->Usb2Port2IUsbTxEmphasisEn); + old->Usb2Port2IUsbTxEmphasisEn, + new->Usb2Port2IUsbTxEmphasisEn); fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, - old->Usb2Port2PerPortTxPeHalf, - new->Usb2Port2PerPortTxPeHalf); + old->Usb2Port2PerPortTxPeHalf, + new->Usb2Port2PerPortTxPeHalf); fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, - old->Usb2Port3PerPortPeTxiSet, - new->Usb2Port3PerPortPeTxiSet); + old->Usb2Port3PerPortPeTxiSet, + new->Usb2Port3PerPortPeTxiSet); fsp_display_upd_value("Usb2Port3PerPortTxiSet", 1, - old->Usb2Port3PerPortTxiSet, - new->Usb2Port3PerPortTxiSet); + old->Usb2Port3PerPortTxiSet, + new->Usb2Port3PerPortTxiSet); fsp_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1, - old->Usb2Port3IUsbTxEmphasisEn, - new->Usb2Port3IUsbTxEmphasisEn); + old->Usb2Port3IUsbTxEmphasisEn, + new->Usb2Port3IUsbTxEmphasisEn); fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, - old->Usb2Port3PerPortTxPeHalf, - new->Usb2Port3PerPortTxPeHalf); + old->Usb2Port3PerPortTxPeHalf, + new->Usb2Port3PerPortTxPeHalf); fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, - old->Usb2Port4PerPortPeTxiSet, - new->Usb2Port4PerPortPeTxiSet); + old->Usb2Port4PerPortPeTxiSet, + new->Usb2Port4PerPortPeTxiSet); fsp_display_upd_value("Usb2Port4PerPortTxiSet", 1, - old->Usb2Port4PerPortTxiSet, - new->Usb2Port4PerPortTxiSet); + old->Usb2Port4PerPortTxiSet, + new->Usb2Port4PerPortTxiSet); fsp_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1, - old->Usb2Port4IUsbTxEmphasisEn, - new->Usb2Port4IUsbTxEmphasisEn); + old->Usb2Port4IUsbTxEmphasisEn, + new->Usb2Port4IUsbTxEmphasisEn); fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, - old->Usb2Port4PerPortTxPeHalf, - new->Usb2Port4PerPortTxPeHalf); + old->Usb2Port4PerPortTxPeHalf, + new->Usb2Port4PerPortTxPeHalf); fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, - old->Usb3Lane0Ow2tapgen2deemph3p5, - new->Usb3Lane0Ow2tapgen2deemph3p5); + old->Usb3Lane0Ow2tapgen2deemph3p5, + new->Usb3Lane0Ow2tapgen2deemph3p5); fsp_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1, - old->Usb3Lane1Ow2tapgen2deemph3p5, - new->Usb3Lane1Ow2tapgen2deemph3p5); + old->Usb3Lane1Ow2tapgen2deemph3p5, + new->Usb3Lane1Ow2tapgen2deemph3p5); fsp_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1, - old->Usb3Lane2Ow2tapgen2deemph3p5, - new->Usb3Lane2Ow2tapgen2deemph3p5); + old->Usb3Lane2Ow2tapgen2deemph3p5, + new->Usb3Lane2Ow2tapgen2deemph3p5); fsp_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1, - old->Usb3Lane3Ow2tapgen2deemph3p5, - new->Usb3Lane3Ow2tapgen2deemph3p5); + old->Usb3Lane3Ow2tapgen2deemph3p5, + new->Usb3Lane3Ow2tapgen2deemph3p5); fsp_display_upd_value("PcdSataInterfaceSpeed", 1, - old->PcdSataInterfaceSpeed, - new->PcdSataInterfaceSpeed); + old->PcdSataInterfaceSpeed, + new->PcdSataInterfaceSpeed); fsp_display_upd_value("PcdPchUsbSsicPort", 1, - old->PcdPchUsbSsicPort, new->PcdPchUsbSsicPort); + old->PcdPchUsbSsicPort, + new->PcdPchUsbSsicPort); fsp_display_upd_value("PcdPchUsbHsicPort", 1, - old->PcdPchUsbHsicPort, new->PcdPchUsbHsicPort); + old->PcdPchUsbHsicPort, + new->PcdPchUsbHsicPort); fsp_display_upd_value("PcdPcieRootPortSpeed", 1, - old->PcdPcieRootPortSpeed, new->PcdPcieRootPortSpeed); - fsp_display_upd_value("PcdPchSsicEnable", 1, old->PcdPchSsicEnable, - new->PcdPchSsicEnable); - fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, - new->PcdLogoPtr); - fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, - new->PcdLogoSize); - fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, - new->PcdRtcLock); - fsp_display_upd_value("PMIC_I2CBus", 1, - old->PMIC_I2CBus, new->PMIC_I2CBus); - fsp_display_upd_value("ISPEnable", 1, - old->ISPEnable, new->ISPEnable); - fsp_display_upd_value("ISPPciDevConfig", 1, - old->ISPPciDevConfig, new->ISPPciDevConfig); - fsp_display_upd_value("PcdSdDetectChk", 1, - old->PcdSdDetectChk, new->PcdSdDetectChk); + old->PcdPcieRootPortSpeed, + new->PcdPcieRootPortSpeed); + fsp_display_upd_value("PcdPchSsicEnable", 1, + old->PcdPchSsicEnable, + new->PcdPchSsicEnable); + + fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, new->PcdLogoPtr); + fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, new->PcdLogoSize); + fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, new->PcdRtcLock); + fsp_display_upd_value("PMIC_I2CBus", 1, old->PMIC_I2CBus, new->PMIC_I2CBus); + fsp_display_upd_value("ISPEnable", 1, old->ISPEnable, new->ISPEnable); + fsp_display_upd_value("ISPPciDevConfig", 1, old->ISPPciDevConfig, new->ISPPciDevConfig); + fsp_display_upd_value("PcdSdDetectChk", 1, old->PcdSdDetectChk, new->PcdSdDetectChk); } /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ @@ -356,7 +342,7 @@ static void soc_init(void *chip_info) struct chip_operations soc_intel_braswell_ops = { CHIP_NAME("Intel Braswell SoC") .enable_dev = enable_dev, - .init = soc_init, + .init = soc_init, }; struct pci_operations soc_pci_ops = { @@ -371,74 +357,74 @@ struct pci_operations soc_pci_ops = { int SocStepping(void) { struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - u8 revid = pci_read_config8(dev, 0x8); + const u8 revid = pci_read_config8(dev, 0x8); switch (revid & B_PCH_LPC_RID_STEPPING_MASK) { case V_PCH_LPC_RID_A0: - return SocA0; + return SocA0; case V_PCH_LPC_RID_A1: - return SocA1; + return SocA1; case V_PCH_LPC_RID_A2: - return SocA2; + return SocA2; case V_PCH_LPC_RID_A3: - return SocA3; + return SocA3; case V_PCH_LPC_RID_A4: - return SocA4; + return SocA4; case V_PCH_LPC_RID_A5: - return SocA5; + return SocA5; case V_PCH_LPC_RID_A6: - return SocA6; + return SocA6; case V_PCH_LPC_RID_A7: - return SocA7; + return SocA7; case V_PCH_LPC_RID_B0: - return SocB0; + return SocB0; case V_PCH_LPC_RID_B1: - return SocB1; + return SocB1; case V_PCH_LPC_RID_B2: - return SocB2; + return SocB2; case V_PCH_LPC_RID_B3: - return SocB3; + return SocB3; case V_PCH_LPC_RID_B4: - return SocB4; + return SocB4; case V_PCH_LPC_RID_B5: - return SocB5; + return SocB5; case V_PCH_LPC_RID_B6: - return SocB6; + return SocB6; case V_PCH_LPC_RID_B7: - return SocB7; + return SocB7; case V_PCH_LPC_RID_C0: - return SocC0; + return SocC0; case V_PCH_LPC_RID_C1: - return SocC1; + return SocC1; case V_PCH_LPC_RID_C2: - return SocC2; + return SocC2; case V_PCH_LPC_RID_C3: - return SocC3; + return SocC3; case V_PCH_LPC_RID_C4: - return SocC4; + return SocC4; case V_PCH_LPC_RID_C5: - return SocC5; + return SocC5; case V_PCH_LPC_RID_C6: - return SocC6; + return SocC6; case V_PCH_LPC_RID_C7: - return SocC7; + return SocC7; case V_PCH_LPC_RID_D0: - return SocD0; + return SocD0; case V_PCH_LPC_RID_D1: - return SocD1; + return SocD1; case V_PCH_LPC_RID_D2: - return SocD2; + return SocD2; case V_PCH_LPC_RID_D3: - return SocD3; + return SocD3; case V_PCH_LPC_RID_D4: - return SocD4; + return SocD4; case V_PCH_LPC_RID_D5: - return SocD5; + return SocD5; case V_PCH_LPC_RID_D6: - return SocD6; + return SocD6; case V_PCH_LPC_RID_D7: - return SocD7; + return SocD7; default: - return SocSteppingMax; + return SocSteppingMax; } } diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index be95808910..026e491006 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -58,13 +58,13 @@ struct soc_intel_braswell_config { enum serirq_mode serirq_mode; - /* Disable SLP_X stretching after SUS power well loss. */ + /* Disable SLP_X stretching after SUS power well loss */ int disable_slp_x_stretch_sus_fail; - /* LPE Audio Clock configuration. */ - enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz */ + /* LPE Audio Clock configuration */ + enum lpe_clk_src lpe_codec_clk_src; /* Both are 19.2MHz */ - /* Native SD Card controller - override controller capabilities. */ + /* Native SD Card controller - override controller capabilities */ uint32_t sdcard_cap_low; uint32_t sdcard_cap_high; @@ -74,7 +74,7 @@ struct soc_intel_braswell_config { int sd_acpi_mode; int lpe_acpi_mode; - /* Allow PCIe devices to wake system from suspend. */ + /* Allow PCIe devices to wake system from suspend */ int pcie_wake_enable; /* Program USB2_COMPBG register. @@ -84,94 +84,91 @@ struct soc_intel_braswell_config { */ enum usb_comp_bg_value usb_comp_bg; + /* + * The following fields come from fsp_vpd.h .aka. VpdHeader.h. + * These are configuration values that are passed to FSP during MemoryInit. + */ + uint16_t PcdMrcInitTsegSize; + uint16_t PcdMrcInitMmioSize; + uint8_t PcdMrcInitSpdAddr1; + uint8_t PcdMrcInitSpdAddr2; + uint8_t PcdIgdDvmt50PreAlloc; + uint8_t PcdApertureSize; + uint8_t PcdGttSize; + uint8_t PcdLegacySegDecode; + uint8_t PcdDvfsEnable; + uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */ /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. - * These are configuration values that are passed to FSP during - * MemoryInit. + * These are configuration values that are passed to FSP during SiliconInit. */ - UINT16 PcdMrcInitTsegSize; - UINT16 PcdMrcInitMmioSize; - UINT8 PcdMrcInitSpdAddr1; - UINT8 PcdMrcInitSpdAddr2; - UINT8 PcdIgdDvmt50PreAlloc; - UINT8 PcdApertureSize; - UINT8 PcdGttSize; - UINT8 PcdLegacySegDecode; - UINT8 PcdDvfsEnable; - UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */ - - /* - * The following fields come from fsp_vpd.h .aka. VpdHeader.h. - * These are configuration values that are passed to FSP during - * SiliconInit. - */ - UINT8 PcdSdcardMode; - UINT8 PcdEnableHsuart0; - UINT8 PcdEnableHsuart1; - UINT8 PcdEnableAzalia; - UINT8 PcdEnableSata; - UINT8 PcdEnableXhci; - UINT8 PcdEnableLpe; - UINT8 PcdEnableDma0; - UINT8 PcdEnableDma1; - UINT8 PcdEnableI2C0; - UINT8 PcdEnableI2C1; - UINT8 PcdEnableI2C2; - UINT8 PcdEnableI2C3; - UINT8 PcdEnableI2C4; - UINT8 PcdEnableI2C5; - UINT8 PcdEnableI2C6; - UINT8 PunitPwrConfigDisable; - UINT8 ChvSvidConfig; - UINT8 DptfDisable; - UINT8 PcdEmmcMode; - UINT8 PcdUsb3ClkSsc; - UINT8 PcdDispClkSsc; - UINT8 PcdSataClkSsc; - UINT8 Usb2Port0PerPortPeTxiSet; - UINT8 Usb2Port0PerPortTxiSet; - UINT8 Usb2Port0IUsbTxEmphasisEn; - UINT8 Usb2Port0PerPortTxPeHalf; - UINT8 Usb2Port1PerPortPeTxiSet; - UINT8 Usb2Port1PerPortTxiSet; - UINT8 Usb2Port1IUsbTxEmphasisEn; - UINT8 Usb2Port1PerPortTxPeHalf; - UINT8 Usb2Port2PerPortPeTxiSet; - UINT8 Usb2Port2PerPortTxiSet; - UINT8 Usb2Port2IUsbTxEmphasisEn; - UINT8 Usb2Port2PerPortTxPeHalf; - UINT8 Usb2Port3PerPortPeTxiSet; - UINT8 Usb2Port3PerPortTxiSet; - UINT8 Usb2Port3IUsbTxEmphasisEn; - UINT8 Usb2Port3PerPortTxPeHalf; - UINT8 Usb2Port4PerPortPeTxiSet; - UINT8 Usb2Port4PerPortTxiSet; - UINT8 Usb2Port4IUsbTxEmphasisEn; - UINT8 Usb2Port4PerPortTxPeHalf; - UINT8 Usb3Lane0Ow2tapgen2deemph3p5; - UINT8 Usb3Lane1Ow2tapgen2deemph3p5; - UINT8 Usb3Lane2Ow2tapgen2deemph3p5; - UINT8 Usb3Lane3Ow2tapgen2deemph3p5; - UINT8 PcdSataInterfaceSpeed; - UINT8 PcdPchUsbSsicPort; - UINT8 PcdPchUsbHsicPort; - UINT8 PcdPcieRootPortSpeed; - UINT8 PcdPchSsicEnable; - UINT32 PcdLogoPtr; - UINT32 PcdLogoSize; - UINT8 PcdRtcLock; - UINT8 PMIC_I2CBus; - UINT8 ISPEnable; - UINT8 ISPPciDevConfig; - UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/ - UINT8 I2C0Frequency; /* 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz */ - UINT8 I2C1Frequency; - UINT8 I2C2Frequency; - UINT8 I2C3Frequency; - UINT8 I2C4Frequency; - UINT8 I2C5Frequency; - UINT8 I2C6Frequency; + uint8_t PcdSdcardMode; + uint8_t PcdEnableHsuart0; + uint8_t PcdEnableHsuart1; + uint8_t PcdEnableAzalia; + uint8_t PcdEnableSata; + uint8_t PcdEnableXhci; + uint8_t PcdEnableLpe; + uint8_t PcdEnableDma0; + uint8_t PcdEnableDma1; + uint8_t PcdEnableI2C0; + uint8_t PcdEnableI2C1; + uint8_t PcdEnableI2C2; + uint8_t PcdEnableI2C3; + uint8_t PcdEnableI2C4; + uint8_t PcdEnableI2C5; + uint8_t PcdEnableI2C6; + uint8_t PunitPwrConfigDisable; + uint8_t ChvSvidConfig; + uint8_t DptfDisable; + uint8_t PcdEmmcMode; + uint8_t PcdUsb3ClkSsc; + uint8_t PcdDispClkSsc; + uint8_t PcdSataClkSsc; + uint8_t Usb2Port0PerPortPeTxiSet; + uint8_t Usb2Port0PerPortTxiSet; + uint8_t Usb2Port0IUsbTxEmphasisEn; + uint8_t Usb2Port0PerPortTxPeHalf; + uint8_t Usb2Port1PerPortPeTxiSet; + uint8_t Usb2Port1PerPortTxiSet; + uint8_t Usb2Port1IUsbTxEmphasisEn; + uint8_t Usb2Port1PerPortTxPeHalf; + uint8_t Usb2Port2PerPortPeTxiSet; + uint8_t Usb2Port2PerPortTxiSet; + uint8_t Usb2Port2IUsbTxEmphasisEn; + uint8_t Usb2Port2PerPortTxPeHalf; + uint8_t Usb2Port3PerPortPeTxiSet; + uint8_t Usb2Port3PerPortTxiSet; + uint8_t Usb2Port3IUsbTxEmphasisEn; + uint8_t Usb2Port3PerPortTxPeHalf; + uint8_t Usb2Port4PerPortPeTxiSet; + uint8_t Usb2Port4PerPortTxiSet; + uint8_t Usb2Port4IUsbTxEmphasisEn; + uint8_t Usb2Port4PerPortTxPeHalf; + uint8_t Usb3Lane0Ow2tapgen2deemph3p5; + uint8_t Usb3Lane1Ow2tapgen2deemph3p5; + uint8_t Usb3Lane2Ow2tapgen2deemph3p5; + uint8_t Usb3Lane3Ow2tapgen2deemph3p5; + uint8_t PcdSataInterfaceSpeed; + uint8_t PcdPchUsbSsicPort; + uint8_t PcdPchUsbHsicPort; + uint8_t PcdPcieRootPortSpeed; + uint8_t PcdPchSsicEnable; + uint32_t PcdLogoPtr; + uint32_t PcdLogoSize; + uint8_t PcdRtcLock; + uint8_t PMIC_I2CBus; + uint8_t ISPEnable; + uint8_t ISPPciDevConfig; + uint8_t PcdSdDetectChk; /* Enable / Disable SD Card Detect Simulation */ + uint8_t I2C0Frequency; /* 0 - 100KHz, 1 - 400KHz, 2 - 1MHz */ + uint8_t I2C1Frequency; + uint8_t I2C2Frequency; + uint8_t I2C3Frequency; + uint8_t I2C4Frequency; + uint8_t I2C5Frequency; + uint8_t I2C6Frequency; }; #endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 2d47663e04..0221478f18 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -35,8 +35,8 @@ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), - REG_MSR_RMW(MSR_POWER_MISC, - ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), + REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), + /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), @@ -53,10 +53,9 @@ static void soc_core_init(struct device *cpu) setup_lapic(); /* - * The turbo disable bit is actually scoped at building - * block level -- not package. For non-bsp cores that are within a - * building block enable turbo. The cores within the BSP's building - * block will just see it already enabled and move on. + * The turbo disable bit is actually scoped at building block level -- not package. + * For non-BSP cores that are within a building block, enable turbo. The cores within + * the BSP's building block will just see it already enabled and move on. */ if (lapicid()) enable_turbo(); @@ -76,9 +75,9 @@ static struct device_operations cpu_dev_ops = { }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x406C4 }, - { X86_VENDOR_INTEL, 0x406C3 }, - { X86_VENDOR_INTEL, 0x406C2 }, + { X86_VENDOR_INTEL, 0x406c4 }, + { X86_VENDOR_INTEL, 0x406c3 }, + { X86_VENDOR_INTEL, 0x406c2 }, { 0, 0 }, }; @@ -115,9 +114,8 @@ static void pre_mp_init(void) x86_mtrr_check(); /* - * Configure the BUNIT to allow dirty cache line evictions in non-SMM - * mode for the lines that were dirtied while in SMM mode. Otherwise - * the writes would be silently dropped. + * Configure the BUNIT to allow dirty cache line evictions in non-SMM mode for lines + * that were dirtied while in SMM mode. Otherwise the writes would be silently dropped. */ bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); @@ -190,8 +188,7 @@ static void per_cpu_smm_trigger(void) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) +static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; @@ -205,22 +202,21 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, } static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_southbridge_clear_state, + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = relocation_handler, - .post_mp_init = smm_southbridge_enable_smi, + .relocation_handler = relocation_handler, + .post_mp_init = smm_southbridge_enable_smi, }; void soc_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index b24dff5446..1eef5fdaac 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -51,9 +51,9 @@ static void log_power_and_resets(const struct chipset_power_state *ps) static void log_wake_events(const struct chipset_power_state *ps) { - const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | - PCIE_WAKE2_STS | PCIE_WAKE1_STS | - PCIE_WAKE0_STS; + const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS | + PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS; + uint32_t gpe0_sts; uint32_t gpio_mask; int i; diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 23ada25d4b..58a3fef1b5 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -33,8 +33,7 @@ static void emmc_init(struct device *dev) { struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 41b2c6f2a7..ff73955d7a 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -32,38 +32,34 @@ static const struct reg_script gpu_pre_vbios_script[] = { static const struct reg_script gfx_post_vbios_script[] = { /* Set Lock bits */ - REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK), + REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK), REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK), REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK), REG_SCRIPT_END }; -static inline void gfx_run_script(struct device *dev, - const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } static void gfx_pre_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } static void gfx_post_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } static void gfx_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (!CONFIG(RUN_FSP_GOP)) { /* Pre VBIOS Init */ diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 2ca023ffe0..a6273f39ea 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -57,39 +57,39 @@ static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = { /* GPIO Community descriptions */ static const struct gpio_bank gpnorth_community = { - .gpio_count = GP_NORTH_COUNT, + .gpio_count = GP_NORTH_COUNT, .gpio_to_pad = gpncommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPNORTH_BASE, - .has_gpe_en = GPE_CAPABLE, + .pad_base = COMMUNITY_GPNORTH_BASE, + .has_gpe_en = GPE_CAPABLE, .has_wake_en = 1, }; static const struct gpio_bank gpsoutheast_community = { - .gpio_count = GP_SOUTHEAST_COUNT, + .gpio_count = GP_SOUTHEAST_COUNT, .gpio_to_pad = gpsecommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPSOUTHEAST_BASE, - .has_gpe_en = GPE_CAPABLE_NONE, + .pad_base = COMMUNITY_GPSOUTHEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, .has_wake_en = 1, }; static const struct gpio_bank gpsouthwest_community = { - .gpio_count = GP_SOUTHWEST_COUNT, + .gpio_count = GP_SOUTHWEST_COUNT, .gpio_to_pad = gpswcommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPSOUTHWEST_BASE, - .has_gpe_en = GPE_CAPABLE, + .pad_base = COMMUNITY_GPSOUTHWEST_BASE, + .has_gpe_en = GPE_CAPABLE, .has_wake_en = 1, }; static const struct gpio_bank gpeast_community = { - .gpio_count = GP_EAST_COUNT, + .gpio_count = GP_EAST_COUNT, .gpio_to_pad = gpecommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPEAST_BASE, - .has_gpe_en = GPE_CAPABLE_NONE, + .pad_base = COMMUNITY_GPEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, .has_wake_en = 1, }; static void setup_gpio_route(const struct soc_gpio_map *sw_gpios, - const struct soc_gpio_map *n_gpios) + const struct soc_gpio_map *n_gpios) { const struct soc_gpio_map *n_config; const struct soc_gpio_map *sw_config; @@ -104,82 +104,72 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios, for (sw_config = sw_gpios, n_config = n_gpios; (!north_done || !south_done); sw_config++, n_config++, gpio++) { - /* when north config is done */ - if ((gpio > GP_NORTH_COUNT) || - (n_config->pad_conf0 == GPIO_LIST_END)) + /* When north config is done */ + if ((gpio > GP_NORTH_COUNT) || (n_config->pad_conf0 == GPIO_LIST_END)) north_done = 1; - /* when sw is done */ - if ((gpio > GP_SOUTHWEST_COUNT) || - (sw_config->pad_conf0 == GPIO_LIST_END)) + /* When southwest config is done */ + if ((gpio > GP_SOUTHWEST_COUNT) || (sw_config->pad_conf0 == GPIO_LIST_END)) south_done = 1; - /* route north gpios */ + /* Route north gpios */ if (!north_done) { /* Int select from 8 to 15 */ int_selection = ((n_config->pad_conf0 >> 28) & 0xf); + if (n_config->gpe == SMI) { - /* - * Set the corresponding bits (01) as - * per the interrupt line - */ + /* Set the corresponding bits (01) as per the interrupt line */ route_reg |= (1 << ((int_selection - 8) * 2)); - /* reset the higher bit */ - route_reg &= - ~(1 << ((int_selection - 8) * 2 + 1)); - alt_gpio_smi |= (1 << (int_selection + 8)); + + /* Reset the higher bit */ + route_reg &= ~(1 << ((int_selection - 8) * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 8)); + } else if (n_config->gpe == SCI) { - /* - * Set the corresponding bits as per the - * interrupt line - */ - route_reg |= - (1 << (((int_selection - 8) * 2) + 1)); - /* reset the bit */ + /* Set the corresponding bits as per the interrupt line */ + route_reg |= (1 << (((int_selection - 8) * 2) + 1)); + + /* Reset the bit */ route_reg &= ~(1 << ((int_selection - 8) * 2)); - gpe0a_en |= (1 << (int_selection + 8)); + gpe0a_en |= (1 << (int_selection + 8)); } } - /* route southwest gpios */ + /* Route southwest gpios */ if (!south_done) { /* Int select from 8 to 15 */ int_selection = ((sw_config->pad_conf0 >> 28) & 0xf); + if (sw_config->gpe == SMI) { - /* - * Set the corresponding bits (10) as - * per the interrupt line - */ - route_reg |= (1 << (int_selection * 2)); - route_reg &= ~(1 << (int_selection * 2 + 1)); - alt_gpio_smi |= (1 << (int_selection + 16)); + /* Set the corresponding bits (10) as per the interrupt line */ + route_reg |= (1 << (int_selection * 2)); + route_reg &= ~(1 << (int_selection * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 16)); + } else if (sw_config->gpe == SCI) { - /* - * Set the corresponding bits as - * per the interrupt line - */ + /* Set the corresponding bits as per the interrupt line */ route_reg |= (1 << ((int_selection * 2) + 1)); - /* reset the bit */ + + /* Reset the bit */ route_reg &= ~(1 << (int_selection * 2)); - gpe0a_en |= (1 << (int_selection + 16)); + gpe0a_en |= (1 << (int_selection + 16)); } } } - /* enable gpe bits in GPE0A_EN_REG */ + /* Enable gpe bits in GPE0A_EN_REG */ outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG); #ifdef GPIO_DEBUG printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n", route_reg, alt_gpio_smi, gpe0a_en); #endif - /* Save as an smm param */ + /* Save as an SMM param */ smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); } -static void setup_gpios(const struct soc_gpio_map *gpios, - const struct gpio_bank *community) +static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank *community) { const struct soc_gpio_map *config; int gpio = 0; @@ -191,38 +181,31 @@ static void setup_gpios(const struct soc_gpio_map *gpios, if (!gpios) return; - for (config = gpios; config->pad_conf0 != GPIO_LIST_END; - config++, gpio++) { + + for (config = gpios; config->pad_conf0 != GPIO_LIST_END; config++, gpio++) { if (gpio > community->gpio_count) break; /* Pad configuration registers */ family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO; - internal_pad_num = community->gpio_to_pad[gpio] % - MAX_FAMILY_PAD_GPIO_NO; + internal_pad_num = community->gpio_to_pad[gpio] % MAX_FAMILY_PAD_GPIO_NO; /* - * Calculate the MMIO Address for specific GPIO pin - * control register pointed by index. - * REG = (IOBASE + COMMUNITY_BASE + (0X04400)) + - * (0X400*FAMILY_NUM) + (8 * PAD_NUM) + * Calculate the MMIO Address for GPIO pin control register pointed by index. + * REG = IOBASE + COMMUNITY_BASE + 0x4400 + (0x400 * FAMILY_NUM) + (8 * PAD_NUM) */ - mmio_addr = FAMILY_PAD_REGS_OFF - + (FAMILY_PAD_REGS_SIZE * family) - + (GPIO_REGS_SIZE * internal_pad_num); + mmio_addr = FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * family) + + (GPIO_REGS_SIZE * internal_pad_num); reg = community->pad_base + mmio_addr; - /* get int selection value */ + /* Get int selection value */ int_selection = ((config->pad_conf0 >> 28) & 0xf); - /* get int mask register value */ + /* Get int mask register value */ gpio_int_mask |= (config->int_mask << int_selection); - /* - * wake capable programming - * some communities have 2 wake regs - */ + /* Wake capable programming, some communities have 2 wake regs */ if (gpio > 31) gpio_wake1 |= config->wake_mask << (gpio % 32); else @@ -235,50 +218,38 @@ static void setup_gpios(const struct soc_gpio_map *gpios, reg, config->pad_conf0, config->pad_conf1, community->gpio_to_pad[gpio], gpio); #endif - /* - * write pad configurations to conf0 and conf1 register - */ - write32((void *)(reg + PAD_CONF0_REG), - config->pad_conf0); - write32((void *)(reg + PAD_CONF1_REG), - config->pad_conf1); + /* Write pad configurations to conf0 and conf1 register */ + write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0); + write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1); } } #ifdef GPIO_DEBUG - printk(BIOS_DEBUG, - "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n", + printk(BIOS_DEBUG, "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n", gpio_wake0, gpio_wake1, gpio_int_mask); #endif /* Wake */ - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), - gpio_wake0); + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0); - /* wake mask config for communities with 2 regs */ + /* Wake mask config for communities with 2 regs */ if (community->gpio_count > 32) - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), - gpio_wake1); + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1); /* Interrupt */ - write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), - gpio_int_mask); - + write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); } void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) { - if (config) { /* - * Write the default value 0xffffff to the SW - * write_access_policy_interrupt_reg to allow the SW interrupt - * mask register to be set + * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg + * to allow the SW interrupt mask register to be set */ - write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), - 0xffffffff); + write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff); printk(BIOS_DEBUG, "north\n"); setup_gpios(config->north, &gpnorth_community); @@ -297,8 +268,8 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) } /* - * Set on die termination feature with pull up value and - * drive the pad high for TAP_TDO and TAP_TMS + * Set on die termination feature with pull up value + * and drive the pad high for TAP_TDO and TAP_TMS */ if (!enable_xdp_tap) printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c index 7dccc7b51b..d2abccc259 100644 --- a/src/soc/intel/braswell/gpio_support.c +++ b/src/soc/intel/braswell/gpio_support.c @@ -24,10 +24,9 @@ uint16_t gpio_family_number(uint8_t community, uint8_t pad) { /* - * Refer to BSW BIOS Writers Guide, Table "Family Number". - * BSW has 4 GPIO communities. Each community has up to 7 families and - * each family contains a range of Pad numbers. The number in the array - * is the maximum no. of that range. + * Refer to BSW BIOS Writers Guide, Table "Family Number". BSW has 4 GPIO communities. + * Each community has up to 7 families and each family contains a range of Pad numbers. + * The number in the array is the maximum no. of that range. * For example: East community, family 0, Pad 0~11. */ static const uint8_t community_base[GPIO_COMMUNITY_COUNT] @@ -57,8 +56,7 @@ uint16_t gpio_family_number(uint8_t community, uint8_t pad) } /* - * Return pad configuration register offset by pad number and which community - * it is in. + * Return pad configuration register offset by pad number and which community it is in. */ uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad) { @@ -69,12 +67,11 @@ uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad) fpad = gpio_family_number(community, pad); /* - * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space - * Registers Addresses" for the Pad configuration register calculation. + * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space Registers Addresses" + * for the Pad configuration register calculation. */ - pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) - + FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * (fpad >> 8)) - + (GPIO_REGS_SIZE * (fpad & 0xff))); + pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + FAMILY_PAD_REGS_OFF + + (FAMILY_PAD_REGS_SIZE * (fpad >> 8)) + (GPIO_REGS_SIZE * (fpad & 0xff))); return pad_config_reg; } @@ -86,17 +83,18 @@ static int gpio_get_community_num(gpio_t gpio_num, int *pad) if (gpio_num >= GP_SW_00 && gpio_num <= GP_SW_97) { comm = GP_SOUTHWEST; *pad = gpio_num % GP_SOUTHWEST_COUNT; + } else if (gpio_num >= GP_NC_00 && gpio_num <= GP_NC_72) { comm = GP_NORTH; *pad = gpio_num % GP_SOUTHWEST_COUNT; + } else if (gpio_num >= GP_E_00 && gpio_num <= GP_E_26) { comm = GP_EAST; - *pad = gpio_num % - (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT); + *pad = gpio_num % (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT); + } else { comm = GP_SOUTHEAST; - *pad = gpio_num % (GP_SOUTHWEST_COUNT + - GP_NORTH_COUNT + GP_EAST_COUNT); + *pad = gpio_num % (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT); } return comm; } @@ -107,10 +105,8 @@ static void gpio_config_pad(gpio_t gpio_num, const struct soc_gpio_map *cfg) int pad_num = 0; uint32_t *pad_config0_reg; uint32_t *pad_config1_reg; - int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT - + GP_SOUTHEAST_COUNT; - if (gpio_num > max_gpio_cnt) + if (gpio_num > MAX_GPIO_CNT) return; /* Get GPIO Community based on GPIO_NUMBER */ comm = gpio_get_community_num(gpio_num, &pad_num); @@ -147,10 +143,8 @@ int gpio_get(gpio_t gpio_num) int pad_num = 0; uint32_t *pad_config0_reg; u32 pad_value; - int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT - + GP_SOUTHEAST_COUNT; - if (gpio_num > max_gpio_cnt) + if (gpio_num > MAX_GPIO_CNT) return -1; /* Get GPIO Community based on GPIO_NUMBER */ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 51c8e12ed4..e40a9517b3 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -133,6 +133,8 @@ #define GP_EAST_COUNT 24 #define GP_SOUTHEAST_COUNT 55 +#define MAX_GPIO_CNT (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT + GP_SOUTHEAST_COUNT) + /* General */ #define GPIO_REGS_SIZE 8 #define NA 0 diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index bf5807464d..8b7c1eab34 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -50,48 +50,47 @@ static void lpc_gpio_config(u32 cycle) { if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_FRAME_MMIO_OFFSET), + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD0_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD1_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD2_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD3_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_CLKRUN_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_PD20K(1)); + } else { /* Resume cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_FRAME_MMIO_OFFSET), + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD0_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD1_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD2_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD3_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_CLKRUN_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); } } /* - * configure LPC GPIO lines for low power + * Configure LPC GPIO lines for low power */ void lpc_set_low_power(void) { diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 12d2858868..85e698c535 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -31,7 +31,6 @@ #include #include "chip.h" - /* * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB * address. Just take 1MiB @ 512MiB. @@ -58,12 +57,12 @@ static void lpe_enable_acpi_mode(struct device *dev) static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - | PCI_COMMAND_INT_DISABLE), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), + /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, - LPE_PCICFGCTR1_PCI_CFG_DIS | - LPE_PCICFGCTR1_ACPI_INT_EN), + LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN), + REG_SCRIPT_END }; global_nvs_t *gnvs; @@ -101,11 +100,13 @@ static void setup_codec_clock(struct device *dev) freq_str = "19.2MHz External Crystal"; reg = CLK_SRC_XTAL; break; + case LPE_CLK_SRC_PLL: /* PLL driven bit2=1 */ freq_str = "19.2MHz PLL"; reg = CLK_SRC_PLL; break; + default: reg = CLK_SRC_XTAL; printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); @@ -118,7 +119,7 @@ static void setup_codec_clock(struct device *dev) printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); - clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); + clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } @@ -136,15 +137,13 @@ static void lpe_stash_firmware_info(struct device *dev) printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base); /* Continue using old way of informing firmware address / size. */ - pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); /* Also put the address in MMIO space like on C0 BTM */ mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), - res->base); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), - res->size); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); } @@ -152,8 +151,7 @@ static void lpe_init(struct device *dev) { struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); lpe_stash_firmware_info(dev); setup_codec_clock(dev); @@ -168,7 +166,7 @@ static void lpe_read_resources(struct device *dev) pci_dev_read_resources(dev); /* - * Allocate the BAR1 resource at index 2 to fulfil the Windows driver + * Allocate the BAR1 resource at index 2 to fulfill the Windows driver * interface requirements even though the PCI device has only one BAR */ res = new_resource(dev, PCI_BASE_ADDRESS_2); @@ -179,8 +177,7 @@ static void lpe_read_resources(struct device *dev) res->align = 12; res->flags = IORESOURCE_MEM; - reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, - FIRMWARE_PHYS_BASE >> 10, + reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10, FIRMWARE_PHYS_LENGTH >> 10); } diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 6bc4065df7..b5c4e3d95c 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -27,16 +27,15 @@ #include "chip.h" -static void dev_enable_acpi_mode(struct device *dev, - int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END }; struct resource *bar; @@ -65,10 +64,6 @@ static void dev_enable_acpi_mode(struct device *dev, reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) -{ - *iosf_reg = -1; - *nvs_index = -1; #define SET_IOSF_REG(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ do { \ @@ -76,6 +71,11 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) *nvs_index = LPSS_NVS_ ## name_; \ } while (0) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) +{ + *iosf_reg = -1; + *nvs_index = -1; + switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); break; @@ -108,6 +108,8 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) } } +#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ @@ -116,9 +118,6 @@ static void i2c_disable_resets(struct device *dev) REG_SCRIPT_END, }; -#define CASE_I2C(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - switch (dev->path.pci.devfn) { CASE_I2C(I2C1) : CASE_I2C(I2C2) : @@ -140,19 +139,15 @@ static void lpss_init(struct device *dev) struct soc_intel_braswell_config *config = config_of(dev); int iosf_reg, nvs_index; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); - printk(BIOS_SPEW, "%s - %s\n", - get_pci_class_name(dev), - get_pci_subclass_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s - %s\n", get_pci_class_name(dev), get_pci_subclass_name(dev)); dev_ctl_reg(dev, &iosf_reg, &nvs_index); if (iosf_reg < 0) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func); return; } diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 04e5d7ba03..28b9e0e5e6 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -19,7 +19,7 @@ static size_t smm_region_size(void) { u32 smm_size; - smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF; + smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF; smm_size -= iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF; smm_size = (smm_size + 1) << 20; return smm_size; diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 7ab184fd10..4745be9be9 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -40,8 +40,7 @@ static inline int is_first_port(struct device *dev) static void pcie_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } static const struct reg_script no_dev_behind_port[] = { @@ -86,14 +85,12 @@ static void check_device_present(struct device *dev) static struct device *port1_dev; /* - * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. - * For each port initial assumption is that, each port will have - * devices connected to it. Later we will scan each PORT and if - * the device is not attached to that port we will update - * rootports_in_use. If none of the root port is in use we will - * disable PORT1 otherwise we will keep PORT1 enabled per spec. - * In future if the Soc has more number of PCIe Root ports then - * change MAX_ROOT_PORTS_BSW value accordingly. + * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. For each port initial + * assumption is that, each port will have devices connected to it. Later we will + * scan each PORT and if the device is not attached to that port we will update + * rootports_in_use. If none of the root port is in use we will disable PORT1 + * otherwise we will keep PORT1 enabled per spec. In future if the SoC has more + * number of PCIe Root ports then change MAX_ROOT_PORTS_BSW value accordingly. */ static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; @@ -109,9 +106,9 @@ static void check_device_present(struct device *dev) printk(BIOS_DEBUG, "No PCIe device present."); /* - * Defer PORT1 disabling for now. When we are at Last port - * we will check rootports_in_use and disable PORT1 if none - * of the port has any device connected + * Defer PORT1 disabling for now. When we are at Last port we will check + * rootports_in_use and disable PORT1 if none of the ports have any device + * connected to it. */ if (!is_first_port(dev)) { reg_script_run_on_dev(dev, no_dev_behind_port); @@ -119,8 +116,8 @@ static void check_device_present(struct device *dev) } else port1_dev = dev; /* - * If none of the ROOT PORT has devices connected then - * disable PORT1 else keep the PORT1 enable + * If none of the ROOT PORT has devices connected then disable PORT1. + * Else, keep the PORT1 enabled. */ if (!rootports_in_use) { reg_script_run_on_dev(port1_dev, no_dev_behind_port); @@ -136,8 +133,8 @@ static void check_device_present(struct device *dev) static void pcie_enable(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + if (is_first_port(dev)) { struct soc_intel_braswell_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); @@ -146,8 +143,7 @@ static void pcie_enable(struct device *dev) strpfusecfg = pci_read_config32(dev, STRPFUSECFG); if (config->pcie_wake_enable) - smm_southcluster_save_param( - SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); + smm_southcluster_save_param(SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } /* Check if device is enabled in strapping. */ diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index f218259b4e..9c5079f8ed 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -53,8 +53,7 @@ uint16_t get_pmbase(void) return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; } -static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) +static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) { int i; @@ -310,16 +309,16 @@ static uint32_t print_alt_sts(uint32_t alt_gpio_smi) { uint32_t alt_gpio_sts; static const char *const alt_gpio_smi_sts_bits[] = { - [0] = "SUS_GPIO_0", - [1] = "SUS_GPIO_1", - [2] = "SUS_GPIO_2", - [3] = "SUS_GPIO_3", - [4] = "SUS_GPIO_4", - [5] = "SUS_GPIO_5", - [6] = "SUS_GPIO_6", - [7] = "SUS_GPIO_7", - [8] = "CORE_GPIO_0", - [9] = "CORE_GPIO_1", + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", [10] = "CORE_GPIO_2", [11] = "CORE_GPIO_3", [12] = "CORE_GPIO_4", diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 9b0775e9b7..3e1625ff60 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -87,12 +87,15 @@ static void fill_in_pattrs(void) if (attrs->revid >= RID_D_STEPPING_START) { attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; attrs->stepping += STEP_D1; + } else if (attrs->revid >= RID_C_STEPPING_START) { attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; attrs->stepping += STEP_C0; + } else if (attrs->revid >= RID_B_STEPPING_START) { attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; attrs->stepping += STEP_B0; + } else { attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; attrs->stepping += STEP_A0; @@ -114,15 +117,15 @@ static void fill_in_pattrs(void) /* Set IA core speed ratio and voltages */ fill_in_msr(&msr, MSR_IACORE_RATIOS); - attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_ratios[IACORE_MIN] = (msr.lo >> 0) & 0x7f; + attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS); attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ fill_in_msr(&msr, MSR_IACORE_VIDS); - attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_vids[IACORE_MIN] = (msr.lo >> 0) & 0x7f; + attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS); attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 1a3100cd02..d8afecd2c3 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -42,13 +42,14 @@ ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); struct chipset_power_state *fill_power_state(void) { - power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); - power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); - power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); + power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + + power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); power_state.gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); @@ -56,10 +57,13 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", power_state.pm1_sts, power_state.pm1_en, power_state.pm1_cnt); + printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", power_state.gpe0_sts, power_state.gpe0_en, power_state.tco_sts); + printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", power_state.prsts, power_state.gen_pmcon1, power_state.gen_pmcon2); + printk(BIOS_DEBUG, "prev_sleep_state %d\n", power_state.prev_sleep_state); return &power_state; } @@ -105,8 +109,7 @@ void soc_after_ram_init(struct romstage_params *params) } /* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) { const struct device *dev; const struct soc_intel_braswell_config *config; @@ -116,24 +119,24 @@ void soc_memory_init_params(struct romstage_params *params, if (!dev) { printk(BIOS_ERR, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_memory_init_params!\n", LPC_DEV, LPC_FUNC); + "Error! Device (PCI:0:%02x.%01x) not found, soc_memory_init_params!\n", + LPC_DEV, LPC_FUNC); return; } config = config_of(dev); printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? - config->PcdMrcInitTsegSize : 0; - upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; - upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; - upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; + + upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; + upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; + upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; - upd->PcdApertureSize = config->PcdApertureSize; - upd->PcdGttSize = config->PcdGttSize; - upd->PcdLegacySegDecode = config->PcdLegacySegDecode; - upd->PcdDvfsEnable = config->PcdDvfsEnable; - upd->PcdCaMirrorEn = config->PcdCaMirrorEn; + upd->PcdApertureSize = config->PcdApertureSize; + upd->PcdGttSize = config->PcdGttSize; + upd->PcdLegacySegDecode = config->PcdLegacySegDecode; + upd->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdCaMirrorEn = config->PcdCaMirrorEn; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -142,27 +145,39 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, /* Display the parameters for MemoryInit */ printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); fsp_display_upd_value("PcdMrcInitTsegSize", 2, - old->PcdMrcInitTsegSize, new->PcdMrcInitTsegSize); + old->PcdMrcInitTsegSize, + new->PcdMrcInitTsegSize); fsp_display_upd_value("PcdMrcInitMmioSize", 2, - old->PcdMrcInitMmioSize, new->PcdMrcInitMmioSize); + old->PcdMrcInitMmioSize, + new->PcdMrcInitMmioSize); fsp_display_upd_value("PcdMrcInitSpdAddr1", 1, - old->PcdMrcInitSpdAddr1, new->PcdMrcInitSpdAddr1); + old->PcdMrcInitSpdAddr1, + new->PcdMrcInitSpdAddr1); fsp_display_upd_value("PcdMrcInitSpdAddr2", 1, - old->PcdMrcInitSpdAddr2, new->PcdMrcInitSpdAddr2); + old->PcdMrcInitSpdAddr2, + new->PcdMrcInitSpdAddr2); fsp_display_upd_value("PcdMemChannel0Config", 1, - old->PcdMemChannel0Config, new->PcdMemChannel0Config); + old->PcdMemChannel0Config, + new->PcdMemChannel0Config); fsp_display_upd_value("PcdMemChannel1Config", 1, - old->PcdMemChannel1Config, new->PcdMemChannel1Config); + old->PcdMemChannel1Config, + new->PcdMemChannel1Config); fsp_display_upd_value("PcdMemorySpdPtr", 4, - old->PcdMemorySpdPtr, new->PcdMemorySpdPtr); + old->PcdMemorySpdPtr, + new->PcdMemorySpdPtr); fsp_display_upd_value("PcdIgdDvmt50PreAlloc", 1, - old->PcdIgdDvmt50PreAlloc, new->PcdIgdDvmt50PreAlloc); + old->PcdIgdDvmt50PreAlloc, + new->PcdIgdDvmt50PreAlloc); fsp_display_upd_value("PcdApertureSize", 1, - old->PcdApertureSize, new->PcdApertureSize); + old->PcdApertureSize, + new->PcdApertureSize); fsp_display_upd_value("PcdGttSize", 1, - old->PcdGttSize, new->PcdGttSize); + old->PcdGttSize, + new->PcdGttSize); fsp_display_upd_value("PcdLegacySegDecode", 1, - old->PcdLegacySegDecode, new->PcdLegacySegDecode); + old->PcdLegacySegDecode, + new->PcdLegacySegDecode); fsp_display_upd_value("PcdDvfsEnable", 1, - old->PcdDvfsEnable, new->PcdDvfsEnable); + old->PcdDvfsEnable, + new->PcdDvfsEnable); } diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index afd66a0d08..4e608194b1 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -26,8 +26,7 @@ typedef struct soc_intel_braswell_config config_t; static void sata_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } static void sata_enable(struct device *dev) diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 1295ffaddd..97983f7494 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -25,23 +25,21 @@ #include #include "chip.h" -#define CAP_OVERRIDE_LOW 0xa0 -#define CAP_OVERRIDE_HIGH 0xa4 -# define USE_CAP_OVERRIDES (1 << 31) +#define CAP_OVERRIDE_LOW 0xa0 +#define CAP_OVERRIDE_HIGH 0xa4 +#define USE_CAP_OVERRIDES (1 << 31) static void sd_init(struct device *dev) { struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); - pci_write_config32(dev, CAP_OVERRIDE_LOW, - config->sdcard_cap_low); - pci_write_config32(dev, CAP_OVERRIDE_HIGH, - config->sdcard_cap_high | USE_CAP_OVERRIDES); + pci_write_config32(dev, CAP_OVERRIDE_LOW, config->sdcard_cap_low); + pci_write_config32(dev, CAP_OVERRIDE_HIGH, config->sdcard_cap_high | + USE_CAP_OVERRIDES); } if (config->sd_acpi_mode) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 584ec88d46..a33c9af96e 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -87,8 +87,7 @@ static void busmaster_disable_on_bus(int bus) /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { + if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int buses; buses = pci_read_config32(dev, PCI_PRIMARY_BUS); busmaster_disable_on_bus((buses >> 8) & 0xff); @@ -100,38 +99,24 @@ static void busmaster_disable_on_bus(int bus) static void tristate_gpios(uint32_t val) { /* Tri-state eMMC */ - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - SDMMC1_CMD_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - SDMMC1_D0_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - SDMMC1_D1_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - SDMMC1_D2_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - SDMMC1_D3_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - MMC1_D4_SD_WE_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - MMC1_D5_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - MMC1_D6_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - MMC1_D7_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHEAST_BASE + - MMC1_RCLK_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val); /* Tri-state HDMI */ - write32((void *)COMMUNITY_GPNORTH_BASE + - HV_DDI2_DDC_SDA_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPNORTH_BASE + - HV_DDI2_DDC_SCL_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val); /* Tri-state CFIO 139 and 140 */ - write32((void *)COMMUNITY_GPSOUTHWEST_BASE + - CFIO_139_MMIO_OFFSET, val); - write32((void *)COMMUNITY_GPSOUTHWEST_BASE + - CFIO_140_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val); } @@ -156,11 +141,10 @@ static void southbridge_smi_sleep(void) if (slp_typ >= ACPI_S3) elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); - /* Clear pending GPE events */ + /* Clear pending GPE events */ clear_gpe_status(); /* Next, do the deed. */ - switch (slp_typ) { case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); @@ -183,25 +167,24 @@ static void southbridge_smi_sleep(void) /* Disable all GPE */ disable_all_gpe(); - /* also iterates over all bridges on bus 0 */ + /* Also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); break; default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } + /* Clear pending wake status bit to avoid immediate wake */ - write32((void *)(0xfed88000 + 0x0200), - read32((void *)(0xfed88000 + 0x0200))); + write32((void *)(0xfed88000 + 0x0200), read32((void *)(0xfed88000 + 0x0200))); /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) tristate_gpios(PAD_CONTROL_REG0_TRISTATE); /* - * Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. + * Write back to the SLP register to cause the originally intended event again. + * We need to set BIT13 (SLP_EN) though to make the sleep happen. */ enable_pm1_control(SLP_EN); @@ -222,9 +205,8 @@ static void southbridge_smi_sleep(void) } /* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. + * Look for Synchronous IO SMI and use save state from that core in case + * we are not running on the same core that initiated the IO transaction. */ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) { @@ -261,8 +243,7 @@ static void southbridge_smi_gsmi(void) { u32 *ret, *param; uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); if (!io_smi) return; @@ -281,8 +262,7 @@ static void southbridge_smi_gsmi(void) static void southbridge_smi_store(void) { u8 sub_command, ret; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); + em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); uint32_t reg_ebx; if (!io_smi) @@ -333,8 +313,7 @@ static void southbridge_smi_apmc(void) break; case APM_CNT_GNVS_UPDATE: if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); + printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } state = smi_apmc_find_state_save(reg8); @@ -362,12 +341,9 @@ static void southbridge_smi_pm1(void) { uint16_t pm1_sts = clear_pm1_status(); - /* - * While OSPM is not active, poweroff immediately - * on a power button event. - */ + /* While OSPM is not active, poweroff immediately on a power button event */ if (pm1_sts & PWRBTN_STS) { - /* power button pressed */ + /* Power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); @@ -463,8 +439,7 @@ void southbridge_smi_handler(void) southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); + "SMI_STS[%d] occurred, but no handler available.\n", i); } } diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index c470f93f6d..ef801bda70 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -75,6 +75,7 @@ static void smm_southcluster_route_gpios(void) for (i = 0; i < 16; i++) { if ((route_reg & ROUTE_MASK) == ROUTE_SMI) alt_gpio_reg |= (1 << i); + route_reg >>= 2; } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); @@ -89,6 +90,7 @@ void smm_southbridge_enable_smi(void) printk(BIOS_DEBUG, "Enabling SMIs.\n"); if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE]) pm1_events |= PCIEXPWAK_DIS; + enable_pm1(pm1_events); disable_gpe(PME_B0_EN); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 73125309f4..be0d910ed8 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -42,15 +42,16 @@ static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) { - u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xf); switch (mode) { case SERIRQ_CONTINUOUS: break; + case SERIRQ_OFF: - write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) & - ~SIRQEN); + write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) & ~SIRQEN); break; + case SERIRQ_QUIET: default: write8(ilb_base + SCNT, read8(ilb_base + SCNT) & ~SCNT_MODE); @@ -58,19 +59,19 @@ static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) } } -static inline void -add_mmio_resource(struct device *dev, int i, unsigned long addr, - unsigned long size) +static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, + unsigned long size) { printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n", __FILE__, __func__, dev_name(dev), addr, size); + mmio_resource(dev, i, addr >> 10, size >> 10); } static void sc_add_mmio_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); @@ -79,9 +80,9 @@ static void sc_add_mmio_resources(struct device *dev) add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); - add_mmio_resource(dev, 0xfff, - 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB*KiB) + 1, - (CONFIG_COREBOOT_ROMSIZE_KB*KiB)); /* BIOS ROM */ + add_mmio_resource(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1, + (CONFIG_COREBOOT_ROMSIZE_KB * KiB)); /* BIOS ROM */ + add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ } @@ -99,17 +100,16 @@ static void sc_enable_serial_irqs(struct device *dev) } /* - * Write PCI config space IRQ assignments. PCI devices have the INT_LINE - * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing - * information to operating systems and drivers. The INT_PIN register is - * generally read only and reports which interrupt pin A - D it uses. The - * INT_LINE register is configurable and reports which IRQ (generally the - * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling - * on devices that are downstream on a PCI bridge into account. + * Write PCI config space IRQ assignments. PCI devices have the INT_LINE (0x3c) and INT_PIN + * (0x3d) registers which report interrupt routing information to operating systems and drivers. + * The INT_PIN register is generally read only and reports which interrupt pin A - D it uses. + * The INT_LINE register is configurable and reports which IRQ (generally the PIC IRQs 1 - 15) + * it will use. This needs to take interrupt pin swizzling on devices that are downstream on + * a PCI bridge into account. * - * This function will loop through all enabled PCI devices and program the - * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it - * uses. It then configures each interrupt in the pic to be level triggered. + * This function will loop through all enabled PCI devices and program the INT_LINE register + * with the correct PIC IRQ number for the INT_PIN that it uses. It then configures each + * interrupt in the PIC to be level triggered. */ static void write_pci_config_irqs(void) { @@ -125,16 +125,14 @@ static void write_pci_config_irqs(void) const struct soc_irq_route *ir = &global_soc_irq_route; if (ir == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments" - " because 'global_braswell_irq_route' structure does" - " not exist\n"); + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments " + "because 'global_braswell_irq_route' structure does not exist\n"); return; } /* - * Loop through all enabled devices and program their - * INT_LINE, INT_PIN registers from values taken from - * the Interrupt Route registers in the ILB + * Loop through all enabled devices and program their INT_LINE, INT_PIN registers from + * values taken from the Interrupt Route registers in the ILB */ printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PIRQ assignments\n"); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { @@ -164,8 +162,8 @@ static void write_pci_config_irqs(void) if (ir->pcidev[device_num] == 0) { printk(BIOS_WARNING, - "Warning: PCI Device %d does not have an IRQ " - "entry, skipping it\n", device_num); + "Warning: PCI Device %d does not have an IRQ entry, " + "skipping it\n", device_num); continue; } @@ -178,28 +176,24 @@ static void write_pci_config_irqs(void) if (int_line != PIRQ_PIC_IRQDISABLE) { /* Set this IRQ to level triggered */ - i8259_configure_irq_trigger(int_line, - IRQ_LEVEL_TRIGGERED); + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + /* Set the Interrupt Line register */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, - int_line); + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); } else { - /* - * Set the Interrupt line register as 'unknown' or - * 'unused' - */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, - PIRQ_PIC_UNKNOWN_UNUSED); + /* Set the Interrupt line register as 'unknown' or 'unused' */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, PIRQ_PIC_UNKNOWN_UNUSED); } - printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", - original_int_pin, pin_to_str(original_int_pin)); + printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", original_int_pin, + pin_to_str(original_int_pin)); + if (parent_bdf != current_bdf) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - new_int_pin, pin_to_str(new_int_pin)); - printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - 'A' + pirq, int_line, int_line); + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", new_int_pin, + pin_to_str(new_int_pin)); + + printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n\tINT_LINE\t: 0x%X (IRQ %d)\n", + 'A' + pirq, int_line, int_line); } printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PIRQ assignments\n"); } @@ -211,11 +205,10 @@ static inline int io_range_in_default(int base, int size) return 0; /* Is it entirely contained? */ - if (base >= LPC_DEFAULT_IO_RANGE_LOWER && - (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) return 1; - /* This will return not in range for partial overlaps. */ + /* This will return not in range for partial overlaps */ return 0; } @@ -223,8 +216,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(struct device *dev, int base, int size, - int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -244,8 +236,7 @@ static void sc_add_io_resources(struct device *dev) { struct resource *res; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); @@ -262,8 +253,7 @@ static void sc_add_io_resources(struct device *dev) static void sc_read_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -278,20 +268,19 @@ static void sc_read_resources(struct device *dev) static void sc_init(struct device *dev) { int i; - const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; - const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; const unsigned long ilb_base = ILB_BASE_ADDRESS; + const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; + const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); /* Use IRQ9 for SCI Interrupt */ write32((void *)(ilb_base + ACTL), 0); @@ -302,13 +291,11 @@ static void sc_init(struct device *dev) /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) - write8((void *)(pr_base + i*sizeof(ir->pic[i])), - ir->pic[i]); + write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); /* Set up the per device PIRQ routing base on static config. */ for (i = 0; i < NUM_IR_DEVS; i++) - write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), - ir->pcidev[i]); + write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); @@ -320,11 +307,10 @@ static void sc_init(struct device *dev) if (config->disable_slp_x_stretch_sus_fail) { printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); - write32(gen_pmcon1, - read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + } else { - write32(gen_pmcon1, - read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); + write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } /* Write IRQ assignments to PCI config space */ @@ -347,17 +333,17 @@ static void sc_init(struct device *dev) /* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(struct device *dev) { - void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); + void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); - uint32_t mask = 0; + uint32_t mask = 0; uint32_t mask2 = 0; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); #define SET_DIS_MASK(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ mask |= name_ ## _DIS + #define SET_DIS_MASK2(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ mask2 |= name_ ## _DIS @@ -423,13 +409,13 @@ static void sc_disable_devfn(struct device *dev) if (mask != 0) { write32(func_dis, read32(func_dis) | mask); - /* Ensure posted write hits. */ + /* Ensure posted write hits */ read32(func_dis); } if (mask2 != 0) { write32(func_dis2, read32(func_dis2) | mask2); - /* Ensure posted write hits. */ + /* Ensure posted write hits */ read32(func_dis2); } } @@ -447,23 +433,21 @@ static inline void set_d3hot_bits(struct device *dev, int offset) } /* - * Parts of the audio subsystem are powered by the HDA device. Therefore, one - * cannot put HDA into D3Hot. Instead perform this workaround to make some of - * the audio paths work for LPE audio. + * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into + * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio. */ static void hda_work_around(struct device *dev) { void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Need to set magic register 0x43 to 0xd7 in config space. */ pci_write_config8(dev, 0x43, 0xd7); /* - * Need to set bit 0 of GCTL to take the device out of reset. However, - * that requires setting up the 64-bit BAR. + * Need to set bit 0 of GCTL to take the device out of reset. + * However, that requires setting up the 64-bit BAR. */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); @@ -477,8 +461,7 @@ static int place_device_in_d3hot(struct device *dev) { unsigned int offset; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* * Parts of the HDA block are used for LPE audio as well. @@ -497,8 +480,8 @@ static int place_device_in_d3hot(struct device *dev) } /* - * For some reason some of the devices don't have the capability - * pointer set correctly. Work around this by hard coding the offset. + * For some reason some of the devices don't have the capability pointer set correctly. + * Work around this by hard coding the offset. */ #define DEV_CASE(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) @@ -556,8 +539,8 @@ void southcluster_enable_dev(struct device *dev) { uint32_t reg32; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); @@ -566,8 +549,7 @@ void southcluster_enable_dev(struct device *dev) /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); /* Place device in D3Hot */ @@ -588,15 +570,15 @@ void southcluster_enable_dev(struct device *dev) } static struct device_operations device_ops = { - .read_resources = sc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = NULL, - .acpi_inject_dsdt_generator = southcluster_inject_dsdt, - .write_acpi_tables = southcluster_write_acpi_tables, - .init = sc_init, - .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, - .ops_pci = &soc_pci_ops, + .read_resources = sc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = NULL, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .write_acpi_tables = southcluster_write_acpi_tables, + .init = sc_init, + .enable = southcluster_enable_dev, + .scan_bus = scan_static_bus, + .ops_pci = &soc_pci_ops, }; static const struct pci_driver southcluster __pci_driver = { @@ -612,21 +594,21 @@ static void finalize_chipset(void *unused) void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); void *etr = (void *)(PMC_BASE_ADDRESS + ETR); uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; + struct vscc_config cfg; - printk(BIOS_SPEW, "%s/%s (%p)\n", - __FILE__, __func__, unused); + printk(BIOS_SPEW, "%s/%s (%p)\n", __FILE__, __func__, unused); - /* Set the lock enable on the BIOS control register. */ + /* Set the lock enable on the BIOS control register */ write32(bcr, read32(bcr) | BCR_LE); - /* Set BIOS lock down bit controlling boot block size and swapping. */ + /* Set BIOS lock down bit controlling boot block size and swapping */ write32(gcs, read32(gcs) | BILD); - /* Lock sleep stretching policy and set SMI lock. */ + /* Lock sleep stretching policy and set SMI lock */ write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); - /* Set the CF9 lock. */ + /* Set the CF9 lock */ write32(etr, read32(etr) | CF9LOCK); spi_finalize_ops(); diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index c822a75eea..13992d46d1 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -32,9 +32,10 @@ static const unsigned int cpu_bus_clk_freq_table[] = { unsigned int cpu_bus_freq_khz(void) { msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - if ((clk_info.lo & 0xF) - < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int))) - return cpu_bus_clk_freq_table[clk_info.lo & 0xF]; + + if ((clk_info.lo & 0xf) < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int))) + return cpu_bus_clk_freq_table[clk_info.lo & 0xf]; + return 0; } @@ -55,7 +56,7 @@ void set_max_freq(void) msr_t perf_ctl; msr_t msr; - /* Enable speed step. */ + /* Enable Intel SpeedStep */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); wrmsr(IA32_MISC_ENABLE, msr); @@ -65,19 +66,13 @@ void set_max_freq(void) msr.hi = 0; wrmsr(IA32_MISC_ENABLE, msr); - /* - * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of - * the PERF_CTL. - */ + /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of the PERF_CTL */ msr = rdmsr(MSR_IACORE_TURBO_RATIOS); - perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; + perf_ctl.lo = (msr.lo & 0x003f0000) >> 8; - /* - * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of - * the PERF_CTL. - */ + /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of the PERF_CTL */ msr = rdmsr(MSR_IACORE_TURBO_VIDS); - perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; + perf_ctl.lo |= (msr.lo & 0x007f0000) >> 16; perf_ctl.hi = 0; wrmsr(IA32_PERF_CTL, perf_ctl); diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c index 60d99696fc..3a2626ffa7 100644 --- a/src/soc/intel/braswell/xhci.c +++ b/src/soc/intel/braswell/xhci.c @@ -35,12 +35,10 @@ static void xhci_init(struct device *dev) if (config->usb_comp_bg) { struct reg_script ops[] = { - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, - config->usb_comp_bg), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, config->usb_comp_bg), REG_SCRIPT_END }; - printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", - config->usb_comp_bg); + printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg); reg_script_run(ops); } } From 8d7afcca3691cda81cd5f21c05d3eb1c014f364c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 22:16:36 +0100 Subject: [PATCH 0564/1463] mb/gigabyte/ga-h61ma-d3v: Correct subsystem ID Linux does not handle either value in any special way, though. Change-Id: I833cb94e65b9ddfb79edbcdd0216c70740aa4a16 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39738 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- .../gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb index 1b10533ef2..ad3a35cf45 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb @@ -27,7 +27,7 @@ chip northbridge/intel/sandybridge end register "pci_mmio_size" = "2048" device domain 0x0 on - subsystemid 0x1458 0x5001 inherit + subsystemid 0x1458 0x5000 inherit device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # Internal graphics From c91b93f22a1e43d066d201e1daeed2ee6067092a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 22:18:28 +0100 Subject: [PATCH 0565/1463] mb/gigabyte/ga-h61m-*/devicetree.cb: Add missing IRQ IRQ 0x70 was not declared for device 2e.7, and coreboot whined about it. Change-Id: If40aa390722cf253169003129b31f20543fde5dd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39739 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb | 1 + .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb | 1 + .../gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb index de9c2131c3..b25bba614a 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb @@ -76,6 +76,7 @@ chip northbridge/intel/sandybridge io 0x60 = 0x0000 io 0x62 = 0x0a00 io 0x64 = 0x0000 + irq 0x70 = 0x00 irq 0x73 = 0x00 irq 0xc1 = 0x37 irq 0xcb = 0x00 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb index c898fad228..08abc3e037 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb @@ -89,6 +89,7 @@ chip northbridge/intel/sandybridge io 0x60 = 0x0000 io 0x62 = 0x0a00 io 0x64 = 0x0000 + irq 0x70 = 0x00 irq 0xcb = 0x00 irq 0xf1 = 0x40 end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb index ad3a35cf45..cbd0ee653d 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb @@ -80,6 +80,7 @@ chip northbridge/intel/sandybridge io 0x60 = 0x0000 io 0x62 = 0x0a00 io 0x64 = 0x0000 + irq 0x70 = 0x00 irq 0x73 = 0x00 irq 0xcb = 0x00 irq 0xf0 = 0x10 From 66671ded2fd28a20d547d6b1410fa1e6c0f308cb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 22:21:25 +0100 Subject: [PATCH 0566/1463] mb/gigabyte/ga-h61ma-d3v: Correct PCIe port setup Coalescing is not needed, as all PCIe ports are used. Change-Id: Icf31f6672e0a54d119a6537da1b52c42f9cee823 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39740 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../variants/ga-h61ma-d3v/devicetree.cb | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb index cbd0ee653d..455e109077 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb @@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "gen1_dec" = "0x003c0a01" - register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" @@ -43,12 +42,14 @@ chip northbridge/intel/sandybridge device pci 16.1 off end # Management Engine Interface 2 device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 + + device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3) + device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) + device pci 1c.2 on end # RP #3: Etron EJ168 USB 3.0 + device pci 1c.3 on end # RP #4: Marvell 88SE9172 SATA + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge From 66f569f4aed42cb1995866a887c9eb780fa7f432 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 22:23:40 +0100 Subject: [PATCH 0567/1463] mb/gigabyte/ga-h61m-ds2v: Fix PCIe port numbers A certain somebody (that would be me) forgot how to count, it seems. Change-Id: Iac0ac5827ca242c465a2e8be92a823c8fc9b2935 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39741 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb index b25bba614a..c5dd15e7dd 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb @@ -48,8 +48,8 @@ chip northbridge/intel/sandybridge device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) device pci 1c.2 off end # RP #3: device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #4: Realtek RTL8111F GbE NIC - device pci 1c.5 on end # RP #5: PCIe x1 Port (PCIEX1_2) + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge From 143309fad45e01c623036c981d568cfb3bd5662f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 21:38:16 +0100 Subject: [PATCH 0568/1463] nb/intel/sandybridge: Remove oddball `- 1` in tRFC Fixes a blunder in commit 50db9c99be7e09aafb7cfd353bd0ac9878b76fca (nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings). Tested on Asus P8Z77-V LX2, still boots fine with an i7-2600. Change-Id: I73436b9f7df9f3a065469fb89bcd0cc6183bb774 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39736 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/sandybridge/raminit_sandy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 3b68c22b87..c554c3aa89 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -281,7 +281,7 @@ static void dram_timing(ramctr_timing *ctrl) printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); /* FIXME: Why the -1 ? */ + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->tCK); From ece6b2fc8a7f22716d47ae4f26742d54d0b655c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 20 Mar 2020 12:07:45 +0100 Subject: [PATCH 0569/1463] nb/amd/agesa/family14: Improve HTC threshold handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to BKDGs HTC temperature limit field indicates the threshold where HTC becomes active. HTC active state means that processor is limiting its power consumption and maximum P-State. Using this threshold as _CRT is incorrect, since HTC active is designed to prevent overheating, not causing immediate shutdown. Change the behavior of temperature limit to act as a passive cooling threshold. Make the passive cooling threshold a reference value for critical and hot temperature with 5 degrees step. TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone temperature using sysctl Signed-off-by: Michał Żygowski Change-Id: Ife64c3aab76f8e125493ecc8183a6e87fb012e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39697 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- .../amd/agesa/family14/acpi/thermal_mixin.asl | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl index 1f877ccc6e..3c692ce859 100644 --- a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl +++ b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl @@ -35,7 +35,7 @@ */ #ifndef K10TEMP_HOT_OFFSET -# define K10TEMP_HOT_OFFSET 100 +# define K10TEMP_HOT_OFFSET 50 #endif #define K10TEMP_KELVIN_OFFSET 2732 @@ -71,7 +71,11 @@ ThermalZone (TZ00) { Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) } - Method (_CRT) { /* Critical temp in tenths degree Kelvin. */ + /* + * TLMT indicates threshold where HTC become active. That is the processor will limit + * P-State and power consumption in order to cool down. + */ + Method (_PSV) { /* Passive temp in tenths degree Kelvin. */ Multiply (TLMT, 10, Local0) ShiftRight (Local0, 1, Local0) Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0) @@ -79,6 +83,10 @@ ThermalZone (TZ00) { } Method (_HOT) { /* Hot temp in tenths degree Kelvin. */ - Return (Subtract (_CRT, K10TEMP_HOT_OFFSET)) + Return (Add (_PSV, K10TEMP_HOT_OFFSET)) + } + + Method (_CRT) { /* Critical temp in tenths degree Kelvin. */ + Return (Add (_HOT, K10TEMP_HOT_OFFSET)) } } From 09eb8d0c9b3b9e7b765520114d148a19926ff886 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 7 Feb 2020 18:39:24 +0100 Subject: [PATCH 0570/1463] nb/amd/{agesa,pi}/acpi: include thermal zone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to BKDGs these northbridges should support the K10 compatible temperature sensors. TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone temperature using sysctl Signed-off-by: Michał Żygowski Change-Id: Icbdf44508085964452d74e084b133f1baa39e1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38755 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl | 5 +++++ src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl | 5 +++++ src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 5 +++++ src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index ce3715e4c1..40df8918b1 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -92,3 +92,8 @@ Device(PBR7) { Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ + +Device(K10M) { + Name (_ADR, 0x00180003) + #include +} diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index cdfab58b04..34bf33a32e 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -92,3 +92,8 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ + +Device(K10M) { + Name (_ADR, 0x00180003) + #include +} diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index 621efb526b..cdb4063d36 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -62,3 +62,8 @@ Device(PBR3) { Return (PS3) /* PIC Mode */ } /* end _PRT */ } /* end PBR3 */ + +Device(K10M) { + Name (_ADR, 0x00180003) + #include +} diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index cdfab58b04..34bf33a32e 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -92,3 +92,8 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ + +Device(K10M) { + Name (_ADR, 0x00180003) + #include +} From be3979c873d23cb0543e635bba59bd85ab67fed0 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Wed, 18 Dec 2019 15:07:59 +0100 Subject: [PATCH 0571/1463] acpi: Change Processor ACPI Name (Intel only) The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- Documentation/acpi/index.md | 5 ++- src/arch/x86/Kconfig | 4 +- src/arch/x86/acpigen.c | 4 +- src/cpu/intel/common/acpi/cpu.asl | 8 ++-- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/intel/speedstep/acpi/cpu.asl | 16 ++++---- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 10 ++--- src/mainboard/getac/p470/acpi/ec.asl | 2 +- src/mainboard/getac/p470/acpi/platform.asl | 10 ++--- src/mainboard/getac/p470/acpi/thermal.asl | 4 +- .../terra/include/variant/acpi/cpu.asl | 38 +++++++++---------- src/mainboard/roda/rk886ex/acpi/thermal.asl | 4 +- src/mainboard/roda/rk9/acpi/thermal.asl | 4 +- .../intel/haswell/acpi/hostbridge.asl | 6 +-- .../intel/ironlake/acpi/hostbridge.asl | 6 +-- .../intel/sandybridge/acpi/hostbridge.asl | 6 +-- src/soc/intel/baytrail/acpi.c | 2 +- src/soc/intel/baytrail/acpi/dptf/cpu.asl | 38 +++++++++---------- src/soc/intel/braswell/acpi.c | 2 +- src/soc/intel/braswell/acpi/dptf/cpu.asl | 38 +++++++++---------- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/acpi/ctdp.asl | 6 +-- src/soc/intel/common/acpi/dptf/cpu.asl | 38 +++++++++---------- src/soc/intel/common/block/acpi/acpi.c | 2 +- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/skylake/acpi/dptf/cpu.asl | 10 ++--- src/southbridge/intel/i82371eb/acpi_tables.c | 2 +- 30 files changed, 140 insertions(+), 137 deletions(-) diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md index c378722018..2f65e29968 100644 --- a/Documentation/acpi/index.md +++ b/Documentation/acpi/index.md @@ -1,6 +1,9 @@ # ACPI-specific documentation -This section contains documentation about coreboot on ACPI. +This section contains documentation about coreboot on ACPI. coreboot dropped +backwards support for ACPI 1.0 and is only compatible to ACPI version 2.0 and +upwards. + - [SSDT UID generation](uid.md) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 810a5bbaab..a4e5314ab5 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -254,11 +254,11 @@ config ACPI_HAVE_PCAT_8259 config ACPI_CPU_STRING string - default "\\_PR.CP%02d" + default "\\_SB.CP%02d" depends on HAVE_ACPI_TABLES help Sets the ACPI name string in the processor scope as written by - the acpigen function. Default is \_PR.CPxx. Note that you need + the acpigen function. Default is \_SB.CPxx. Note that you need the \ escape character in the string. config COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index a599b0ecdb..26fe08fa87 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -340,7 +340,7 @@ void acpigen_write_scope(const char *name) void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* - Processor (\_PR.CPcpuindex, cpuindex, pblock_addr, pblock_len) + Processor (\_SB.CPcpuindex, cpuindex, pblock_addr, pblock_len) { */ char pscope[16]; @@ -376,7 +376,7 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores) { int core_id; - acpigen_write_method("\\_PR.CNOT", 1); + acpigen_write_method("\\_SB.CNOT", 1); for (core_id = 0; core_id < number_of_cores; core_id++) { char buffer[DEVICE_PATH_MAX]; snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl index 14ade7d6ec..153527ba7e 100644 --- a/src/cpu/intel/common/acpi/cpu.asl +++ b/src/cpu/intel/common/acpi/cpu.asl @@ -13,22 +13,22 @@ */ /* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) +External (\_SB.CNOT, MethodObj) /* Notify OS to re-read CPU tables */ Method (PNOT) { - \_PR.CNOT (0x81) + \_SB.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit */ Method (PPCN) { - \_PR.CNOT (0x80) + \_SB.CNOT (0x80) } /* Notify OS to re-read Throttle Limit tables */ Method (TNOT) { - \_PR.CNOT (0x82) + \_SB.CNOT (0x82) } diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 282dd962cc..fe2add772a 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -317,7 +317,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index af2606cf33..54da4e8af2 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -309,7 +309,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 60664213ba..c31bb5eaac 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -312,7 +312,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 47565f44dc..71570b1e40 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -124,7 +124,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx. */ + /* Generate processor \_SB.CPUx. */ acpigen_write_processor( cpuID * cores_per_package + coreID - 1, pcontrol_blk, plen); diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl index 9ff3f76727..2d1a47bc78 100644 --- a/src/cpu/intel/speedstep/acpi/cpu.asl +++ b/src/cpu/intel/speedstep/acpi/cpu.asl @@ -12,20 +12,20 @@ */ /* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) -External (\_PR_.CP00, DeviceObj) -External (\_PR_.CP00._PPC) -External (\_PR_.CP01._PPC) +External (\_SB.CNOT, MethodObj) +External (\_SB_.CP00, DeviceObj) +External (\_SB_.CP00._PPC) +External (\_SB_.CP01._PPC) Method (PNOT) { If (MPEN) { - \_PR.CNOT (0x80) // _PPC + \_SB.CNOT (0x80) // _PPC Sleep(100) - \_PR.CNOT (0x81) // _CST + \_SB.CNOT (0x81) // _CST } Else { // UP - Notify (\_PR_.CP00, 0x80) + Notify (\_SB_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CP00, 0x81) + Notify(\_SB_.CP00, 0x81) } } diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 0f66413e68..9b792db704 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -18,7 +18,7 @@ * re-evaluate their _PPC and _CST tables. */ -External (\_PR.CP00._PPC, IntObj) +External (\_SB.CP00._PPC, IntObj) Device (EC0) { @@ -146,12 +146,12 @@ Device (EC0) And(Local0, Ones, Local0) // Find and program number of P-States - Store (SizeOf (\_PR.CP00._PSS), MPST) + Store (SizeOf (\_SB.CP00._PSS), MPST) Store ("Programming number of P-states: ", Debug) Store (MPST, Debug) // Find and program the current P-State - Store(\_PR.CP00._PPC, NPST) + Store(\_SB.CP00._PPC, NPST) Store ("Programming Current P-state: ", Debug) Store (NPST, Debug) } @@ -190,7 +190,7 @@ Device (EC0) { Store ("Pstate Event 0x0E", Debug) - Store(\_PR.CP00._PPC, Local0) + Store(\_SB.CP00._PPC, Local0) Subtract(PPCM, 0x01, Local1) If(LLess(Local0, Local1)) { @@ -205,7 +205,7 @@ Device (EC0) Method (_Q0F) { Store ("Pstate Event 0x0F", Debug) - Store(\_PR.CP00._PPC, Local0) + Store(\_SB.CP00._PPC, Local0) If(Local0) { Decrement(Local0) diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 618055bed0..1b30e03ec5 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -99,7 +99,7 @@ Device(EC0) // EC Query methods, called upon SCI interrupts. Method (_Q01, 0) { - Notify (\_PR.CP00, 0x80) + Notify (\_SB.CP00, 0x80) If(ADP) { Store(1, \_SB.AC.ACST) TRAP(0xe3) diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 6d1948fe75..b2d9fd0125 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -89,15 +89,15 @@ Method(_WAK,1) // Windows XP SP2 P-State restore If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_PR.CP00._PPC, 0)) { - Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) + If (LGreater(\_SB.CP00._PPC, 0)) { + Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) PNOT() - Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) + Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) PNOT() } Else { - Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) + Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) PNOT() - Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) + Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) PNOT() } } diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 9e83384856..2a4d7a9195 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -73,9 +73,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CP00, \_PR.CP01}) + Return (Package() {\_SB.CP00, \_SB.CP01}) } - Return (Package() {\_PR.CP00}) + Return (Package() {\_SB.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl index bdd9792e8c..49991a8435 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl @@ -41,11 +41,11 @@ #define DPTF_CPU_ACTIVE_AC4 50 #endif -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) +External (\_SB.CP00._TSS, MethodObj) +External (\_SB.CP00._TPC, MethodObj) +External (\_SB.CP00._PTC, PkgObj) +External (\_SB.CP00._TSD, PkgObj) +External (\_SB.CP00._PSS, MethodObj) Device (B0DB) { @@ -66,8 +66,8 @@ Device (B0DB) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_SB.CP00._TSS)) { + Return (\_SB.CP00._TSS) } Else { Return (Package () { @@ -78,8 +78,8 @@ Device (B0DB) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_SB.CP00._TPC)) { + Return (\_SB.CP00._TPC) } Else { Return (0) } @@ -87,8 +87,8 @@ Device (B0DB) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_SB.CP00._PTC)) { + Return (\_SB.CP00._PTC) } Else { Return (Package () { @@ -100,8 +100,8 @@ Device (B0DB) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_SB.CP00._TSD)) { + Return (\_SB.CP00._TSD) } Else { Return (Package () { @@ -112,8 +112,8 @@ Device (B0DB) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) + If (CondRefOf (\_SB.CP00._TSS)) { + Store (SizeOf (\_SB.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -140,8 +140,8 @@ Device (B0DB) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_SB.CP00._PSS)) { + Return (\_SB.CP00._PSS) } Else { Return (Package () { @@ -155,8 +155,8 @@ Device (B0DB) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) + } ElseIf (CondRefOf (\_SB.CP00._PSS)) { + Store (SizeOf (\_SB.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index 405a9e0bb9..f06b273b2b 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -61,9 +61,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CP00, \_PR.CP01}) + Return (Package() {\_SB.CP00, \_SB.CP01}) } - Return (Package() {\_PR.CP00}) + Return (Package() {\_SB.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index de6fd028a3..8eb8195d4c 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -79,9 +79,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CP00, \_PR.CP01}) + Return (Package() {\_SB.CP00, \_SB.CP01}) } - Return (Package() {\_PR.CP00}) + Return (Package() {\_SB.CP00}) } // TC1 value for passive cooling diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 7c33d20605..1a4f33d011 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -151,16 +151,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CP00._PSS) + External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CP00._PSS), Local1) + Store (SizeOf (\_SB.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) + (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index 57d6ba0f82..8d4ec25139 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -102,16 +102,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CP00._PSS) + External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CP00._PSS), Local1) + Store (SizeOf (\_SB.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) + (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 9dd6fc0782..b0e314e1f3 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -141,16 +141,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CP00._PSS) + External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CP00._PSS), Local1) + Store (SizeOf (\_SB.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) + (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index c9ccdbdbf6..1797e48543 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -419,7 +419,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor( core, pcontrol_blk, plen); diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index a351e6c136..289dcd4a7b 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -12,11 +12,11 @@ * GNU General Public License for more details. */ -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) +External (\_SB.CP00._TSS, MethodObj) +External (\_SB.CP00._TPC, MethodObj) +External (\_SB.CP00._PTC, PkgObj) +External (\_SB.CP00._TSD, PkgObj) +External (\_SB.CP00._PSS, MethodObj) Device (TCPU) { @@ -38,8 +38,8 @@ Device (TCPU) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_SB.CP00._TSS)) { + Return (\_SB.CP00._TSS) } Else { Return (Package () { @@ -50,8 +50,8 @@ Device (TCPU) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_SB.CP00._TPC)) { + Return (\_SB.CP00._TPC) } Else { Return (0) } @@ -59,8 +59,8 @@ Device (TCPU) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_SB.CP00._PTC)) { + Return (\_SB.CP00._PTC) } Else { Return (Package () { @@ -72,8 +72,8 @@ Device (TCPU) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_SB.CP00._TSD)) { + Return (\_SB.CP00._TSD) } Else { Return (Package () { @@ -84,8 +84,8 @@ Device (TCPU) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) + If (CondRefOf (\_SB.CP00._TSS)) { + Store (SizeOf (\_SB.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -112,8 +112,8 @@ Device (TCPU) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_SB.CP00._PSS)) { + Return (\_SB.CP00._PSS) } Else { Return (Package () { @@ -127,8 +127,8 @@ Device (TCPU) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) + } ElseIf (CondRefOf (\_SB.CP00._PSS)) { + Store (SizeOf (\_SB.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 765be82c40..8142e1bed6 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -422,7 +422,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor(core, pcontrol_blk, plen); /* Generate P-state tables */ diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 5b91699544..1236c847cb 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -41,11 +41,11 @@ #define DPTF_CPU_ACTIVE_AC4 50 #endif -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) +External (\_SB.CP00._TSS, MethodObj) +External (\_SB.CP00._TPC, MethodObj) +External (\_SB.CP00._PTC, PkgObj) +External (\_SB.CP00._TSD, PkgObj) +External (\_SB.CP00._PSS, MethodObj) Device (B0DB) { @@ -66,8 +66,8 @@ Device (B0DB) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_SB.CP00._TSS)) { + Return (\_SB.CP00._TSS) } Else { Return (Package () { @@ -78,8 +78,8 @@ Device (B0DB) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_SB.CP00._TPC)) { + Return (\_SB.CP00._TPC) } Else { Return (0) } @@ -87,8 +87,8 @@ Device (B0DB) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_SB.CP00._PTC)) { + Return (\_SB.CP00._PTC) } Else { Return (Package () { @@ -100,8 +100,8 @@ Device (B0DB) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_SB.CP00._TSD)) { + Return (\_SB.CP00._TSD) } Else { Return (Package () { @@ -112,8 +112,8 @@ Device (B0DB) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) + If (CondRefOf (\_SB.CP00._TSS)) { + Store (SizeOf (\_SB.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -140,8 +140,8 @@ Device (B0DB) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_SB.CP00._PSS)) { + Return (\_SB.CP00._PSS) } Else { Return (Package () { @@ -155,8 +155,8 @@ Device (B0DB) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) + } ElseIf (CondRefOf (\_SB.CP00._PSS)) { + Store (SizeOf (\_SB.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 61f1008aa1..1664fdffef 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -517,7 +517,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor( (cpuID - 1) * cores_per_package+coreID - 1, pcontrol_blk, plen); diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 86ebdd57da..6f3cad6d85 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -71,16 +71,16 @@ Scope (\_SB.PCI0.MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CP00._PSS) + External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CP00._PSS), Local1) + Store (SizeOf (\_SB.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) + (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/common/acpi/dptf/cpu.asl b/src/soc/intel/common/acpi/dptf/cpu.asl index 99dc32a299..982776f701 100644 --- a/src/soc/intel/common/acpi/dptf/cpu.asl +++ b/src/soc/intel/common/acpi/dptf/cpu.asl @@ -12,11 +12,11 @@ * GNU General Public License for more details. */ -External (\_PR.CP00._PSS, PkgObj) -External (\_PR.CP00._TSS, PkgObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) +External (\_SB.CP00._PSS, PkgObj) +External (\_SB.CP00._TSS, PkgObj) +External (\_SB.CP00._TPC, MethodObj) +External (\_SB.CP00._PTC, PkgObj) +External (\_SB.CP00._TSD, PkgObj) External (\_SB.MPDL, IntObj) Device (DPTF_CPU_DEVICE) @@ -38,8 +38,8 @@ Device (DPTF_CPU_DEVICE) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_SB.CP00._TSS)) { + Return (\_SB.CP00._TSS) } Else { Return (Package () { @@ -50,8 +50,8 @@ Device (DPTF_CPU_DEVICE) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_SB.CP00._TPC)) { + Return (\_SB.CP00._TPC) } Else { Return (0) } @@ -59,8 +59,8 @@ Device (DPTF_CPU_DEVICE) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_SB.CP00._PTC)) { + Return (\_SB.CP00._PTC) } Else { Return (Package () { @@ -72,8 +72,8 @@ Device (DPTF_CPU_DEVICE) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_SB.CP00._TSD)) { + Return (\_SB.CP00._TSD) } Else { Return (Package () { @@ -84,8 +84,8 @@ Device (DPTF_CPU_DEVICE) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS), Local0) + If (CondRefOf (\_SB.CP00._TSS)) { + Store (SizeOf (\_SB.CP00._TSS), Local0) Decrement (Local0) Return (Local0) } Else { @@ -112,8 +112,8 @@ Device (DPTF_CPU_DEVICE) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_SB.CP00._PSS)) { + Return (\_SB.CP00._PSS) } Else { Return (Package () { @@ -128,8 +128,8 @@ Device (DPTF_CPU_DEVICE) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS), Local0) + } ElseIf (CondRefOf (\_SB.CP00._PSS)) { + Store (SizeOf (\_SB.CP00._PSS), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index bed4401b5a..b848db446f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -433,7 +433,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor((cpu_id) * cores_per_package + core_id, pcontrol_blk, plen); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 10eec8a399..e6723aab1c 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -522,7 +522,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx */ + /* Generate processor \_SB.CPUx */ acpigen_write_processor( cpu_id*cores_per_package+core_id, pcontrol_blk, plen); diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index 9ffe040fea..b069919ed3 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -20,7 +20,7 @@ #define DPTF_CPU_CRITICAL 90 #endif -External (\_PR.CP00._PSS, PkgObj) +External (\_SB.CP00._PSS, PkgObj) External (\_SB.MPDL, IntObj) Device (B0D4) @@ -55,8 +55,8 @@ Device (B0D4) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_SB.CP00._PSS)) { + Return (\_SB.CP00._PSS) } Else { Return (Package () { @@ -71,8 +71,8 @@ Device (B0D4) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS), Local0) + } ElseIf (CondRefOf (\_SB.CP00._PSS)) { + Store (SizeOf (\_SB.CP00._PSS), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 8059c2c87a..8a8d99e155 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -44,7 +44,7 @@ void generate_cpu_entries(struct device *device) /* without the outer scope, furhter ssdt addition will end up * within the processor statement */ - acpigen_write_scope("\\_PR"); + acpigen_write_scope("\\_SB"); for (cpu=0; cpu < numcpus; cpu++) { acpigen_write_processor(cpu, pcontrol_blk, plen); acpigen_pop_len(); From 0e47ad6d2cd6322324658757cb345c5758449e18 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 12:07:54 +0100 Subject: [PATCH 0572/1463] nb/intel/sandybridge: Reflow raminit tables Make them fit in 96 characters, so that Jenkins does not complain. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: I4a763f6050593e9d4db9211bfeedb442724e1ace Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39719 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_patterns.h | 1015 +++++++++-------- 1 file changed, 508 insertions(+), 507 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_patterns.h b/src/northbridge/intel/sandybridge/raminit_patterns.h index 01183f1792..aa6c2dcfc7 100644 --- a/src/northbridge/intel/sandybridge/raminit_patterns.h +++ b/src/northbridge/intel/sandybridge/raminit_patterns.h @@ -14,7 +14,7 @@ #ifndef SANDYBRIDGE_RAMINIT_PATTERNS_H #define SANDYBRIDGE_RAMINIT_PATTERNS_H -const u32 pattern[][16] = { +const u32 pattern[32][16] = { {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, @@ -145,513 +145,514 @@ const u32 pattern[][16] = { 0x4cc0c82e, 0x28ccd91e, 0xd7311b5d, 0x50a89860}, }; -static const u8 use_base[63][32] = { - { - 0x0e, 0x9e, 0xa1, 0x39, 0x06, 0x26, 0xc5, 0xe9, 0xed, 0x07, 0x49, 0x3b, 0x34, 0x7f, 0x1c, 0xa8, - 0xdf, 0x7b, 0xb7, 0xb8, 0x28, 0xbe, 0x8a, 0x70, 0x17, 0xe5, 0xc0, 0x44, 0x4a, 0x8e, 0x61, 0x3b, - }, - { - 0x42, 0xe6, 0xe0, 0x6a, 0xb3, 0x08, 0x28, 0xaf, 0xfa, 0xb9, 0xb7, 0x32, 0x83, 0x5c, 0xef, 0x3d, - 0x90, 0x91, 0x64, 0x31, 0xe9, 0x3c, 0x92, 0xe6, 0xa3, 0xd4, 0x6a, 0xc6, 0x01, 0xa6, 0xeb, 0xe6, - }, - { - 0x39, 0x7f, 0x6f, 0x81, 0xb4, 0x33, 0x4a, 0xde, 0x4f, 0x77, 0x28, 0x47, 0x08, 0xf9, 0x3a, 0x55, - 0x21, 0x57, 0x27, 0x59, 0xf5, 0x96, 0xad, 0xc1, 0x10, 0x33, 0xe0, 0xe2, 0xf8, 0xb6, 0x49, 0xbd, - }, - { - 0xdf, 0x57, 0x60, 0x27, 0x95, 0x50, 0x3a, 0x8c, 0x34, 0x8b, 0xae, 0xc5, 0x69, 0x26, 0xca, 0x39, - 0x55, 0x98, 0xfb, 0x05, 0x3c, 0x1c, 0x8d, 0xf8, 0xb9, 0x99, 0x05, 0x40, 0xe5, 0x5e, 0x2f, 0xf6, - }, - { - 0xc1, 0x6a, 0xea, 0xd6, 0x39, 0x56, 0x08, 0x89, 0x83, 0x4c, 0xef, 0xda, 0xb2, 0x69, 0x76, 0xe4, - 0x75, 0x3f, 0x39, 0x13, 0x96, 0xb5, 0x41, 0x84, 0x00, 0x64, 0x79, 0x47, 0xe4, 0xcb, 0xc3, 0xd0, - }, - { - 0xf8, 0xb1, 0x19, 0x76, 0x51, 0x99, 0xd7, 0x45, 0x38, 0x40, 0xbf, 0x10, 0x4c, 0x89, 0x43, 0xa9, - 0x89, 0xe2, 0x85, 0x3f, 0xb4, 0xe8, 0xbf, 0x5e, 0xc2, 0xb4, 0x16, 0x6d, 0x1c, 0x61, 0xca, 0x40, - }, - { - 0x1c, 0xdc, 0xa6, 0xdb, 0x71, 0x8b, 0xf9, 0xbb, 0xee, 0xc2, 0xa5, 0x66, 0xa4, 0xbc, 0xb6, 0x89, - 0x58, 0xb9, 0x6f, 0x57, 0x71, 0x57, 0x5c, 0xf0, 0xed, 0xcf, 0x2c, 0x2e, 0x1d, 0x34, 0xc3, 0x00, - }, - { - 0x1d, 0x30, 0x03, 0xb9, 0x15, 0x8e, 0x47, 0x8c, 0xf2, 0x4e, 0x2d, 0xf1, 0xbf, 0x96, 0xa7, 0xa1, - 0x3f, 0x26, 0xc3, 0xc9, 0x08, 0x0b, 0xa8, 0xdd, 0x9b, 0xeb, 0xbc, 0x77, 0x1c, 0x10, 0x03, 0x77, - }, - { - 0x50, 0x7e, 0x62, 0x26, 0xcb, 0x49, 0x7b, 0x1a, 0xd4, 0x54, 0xf1, 0x25, 0x3d, 0xa2, 0xe6, 0x8a, - 0xb3, 0x62, 0xf1, 0x7e, 0x03, 0xef, 0x1b, 0x27, 0x21, 0xcc, 0xfc, 0x72, 0x30, 0x0c, 0x69, 0xad, - }, - { - 0x11, 0xf5, 0xb2, 0xfa, 0x2d, 0xbc, 0xa1, 0xd9, 0x74, 0x15, 0x59, 0xf2, 0xc6, 0x66, 0x4f, 0xde, - 0x84, 0x82, 0x4f, 0xe8, 0x33, 0xd5, 0xc5, 0xdd, 0xba, 0x0c, 0xc7, 0x51, 0x1f, 0x3c, 0x6d, 0x44, - }, - { - 0xcf, 0xf5, 0x3b, 0xc1, 0xbd, 0x5f, 0x9c, 0xad, 0x57, 0xfb, 0xfc, 0xbe, 0x95, 0xa0, 0x48, 0x58, - 0x8a, 0x68, 0x97, 0x71, 0xf3, 0xc0, 0xd1, 0x31, 0x33, 0xb9, 0x3c, 0xe9, 0x4f, 0xbb, 0x8d, 0xeb, - }, - { - 0x29, 0x0c, 0xa1, 0xc8, 0x04, 0xdc, 0xf9, 0x25, 0x85, 0x7e, 0xea, 0x6d, 0x75, 0x28, 0x69, 0x3f, - 0x3a, 0x83, 0xe4, 0x33, 0x31, 0x77, 0x57, 0x2e, 0xa9, 0xa8, 0x05, 0xfe, 0x19, 0xb7, 0xc4, 0xd1, - }, - { - 0x6d, 0x5d, 0x3f, 0x4f, 0x8a, 0x6a, 0x77, 0x2d, 0xf7, 0x9f, 0x73, 0xab, 0x40, 0xd9, 0x89, 0x57, - 0x69, 0xd7, 0xc8, 0xc3, 0x69, 0x54, 0x93, 0x7c, 0x9f, 0x4a, 0xcc, 0xaf, 0xcc, 0x0e, 0xe0, 0xb8, - }, - { - 0xb6, 0xd5, 0x36, 0x3f, 0x1c, 0x34, 0x54, 0x9b, 0xfc, 0xec, 0x5b, 0xb0, 0x26, 0xa6, 0xc0, 0x61, - 0x6d, 0x4c, 0x4f, 0x86, 0x2a, 0xbd, 0x34, 0x35, 0x52, 0x2c, 0x82, 0x01, 0x66, 0x0e, 0x80, 0x01, - }, - { - 0x48, 0x39, 0x43, 0xb8, 0xf9, 0x2b, 0x25, 0xe8, 0xf7, 0xf0, 0x1a, 0xed, 0x33, 0x1e, 0x30, 0xba, - 0x15, 0x37, 0xeb, 0xae, 0x97, 0xa7, 0x36, 0xa4, 0xc7, 0x1f, 0x91, 0x01, 0x38, 0x80, 0x5a, 0x76, - }, - { - 0x74, 0xbe, 0x15, 0x6b, 0x85, 0x28, 0xe4, 0xc4, 0x13, 0x68, 0x67, 0x03, 0x27, 0x7e, 0x32, 0x08, - 0x87, 0x23, 0xda, 0xf2, 0x47, 0xdd, 0xac, 0x2c, 0xc5, 0x7f, 0x06, 0xc8, 0x17, 0x4c, 0x6c, 0x81, - }, - { - 0x0d, 0x9f, 0x68, 0xbb, 0xa6, 0x6c, 0x7d, 0x3f, 0x81, 0xcf, 0x9a, 0x52, 0x87, 0xce, 0x98, 0x25, - 0x40, 0x2b, 0x1b, 0xdf, 0xd3, 0x6b, 0x53, 0xed, 0x80, 0xd2, 0x3d, 0xca, 0xdf, 0x07, 0x4e, 0x6b, - }, - { - 0xff, 0xf1, 0xd2, 0x1f, 0xbd, 0xd6, 0xa7, 0x3d, 0xb4, 0xc6, 0x88, 0x9d, 0x7b, 0x05, 0x04, 0x0b, - 0x4c, 0x6f, 0x11, 0x7f, 0x19, 0x18, 0x48, 0xf1, 0x26, 0xad, 0xd0, 0x60, 0xfa, 0x40, 0x35, 0xbb, - }, - { - 0xae, 0xec, 0x0e, 0x2e, 0xfd, 0x46, 0xf0, 0x9c, 0x06, 0x1b, 0x62, 0xbf, 0xf0, 0x3e, 0xba, 0xdf, - 0xb2, 0xa2, 0x83, 0x83, 0xda, 0x04, 0x15, 0xec, 0x1e, 0x2e, 0x1a, 0x64, 0x08, 0x8e, 0xd3, 0x87, - }, - { - 0x61, 0x14, 0x05, 0x0b, 0xdb, 0xf4, 0xf0, 0xa3, 0x41, 0x11, 0x7b, 0xd9, 0xa1, 0x40, 0x4f, 0x62, - 0x98, 0x37, 0xa0, 0x90, 0x3d, 0x78, 0x63, 0x24, 0xbc, 0x8e, 0x9e, 0x99, 0x2e, 0xc7, 0xb1, 0x6d, - }, - { - 0x0f, 0xf1, 0x5f, 0xe4, 0x94, 0x3d, 0x24, 0x0d, 0xa2, 0xcf, 0xed, 0xbb, 0x55, 0x8e, 0xdb, 0x07, - 0x12, 0x05, 0x79, 0x82, 0xb1, 0x3a, 0x71, 0x76, 0xbb, 0x8b, 0xcb, 0xcc, 0x00, 0x40, 0x2e, 0xab, - }, - { - 0x48, 0x59, 0xfa, 0x46, 0x15, 0x5e, 0xa2, 0x0d, 0xe8, 0x81, 0x69, 0xe6, 0x2f, 0x5f, 0x6d, 0xaf, - 0xad, 0xc7, 0x30, 0xd6, 0xec, 0x03, 0x1e, 0x19, 0xdd, 0x1d, 0x00, 0x94, 0x0b, 0x93, 0x5a, 0x28, - }, - { - 0xfa, 0x64, 0x62, 0x57, 0x02, 0x7e, 0x37, 0xb8, 0x10, 0xa9, 0x4b, 0xe7, 0xbf, 0x03, 0xdc, 0x1c, - 0xe7, 0x21, 0x68, 0x60, 0x53, 0xec, 0xf0, 0xfc, 0xbf, 0xe5, 0x8e, 0xca, 0x77, 0xdb, 0xa5, 0xae, - }, - { - 0xc1, 0xa9, 0x9f, 0xc2, 0x87, 0x11, 0xad, 0x1c, 0xc5, 0x56, 0x61, 0xc0, 0x20, 0x33, 0xc9, 0x85, - 0xf0, 0x81, 0x36, 0x18, 0xdb, 0xaa, 0x7e, 0x79, 0x36, 0x2d, 0xfc, 0x8f, 0x72, 0x3c, 0x4c, 0xa3, - }, - { - 0xb4, 0xd3, 0x38, 0xed, 0xd3, 0x6c, 0x03, 0x26, 0x0e, 0x1c, 0x8a, 0xa8, 0x72, 0x17, 0xcb, 0xf7, - 0x87, 0xf3, 0x3f, 0x73, 0x5d, 0x12, 0xe8, 0x3b, 0x55, 0xb6, 0xcc, 0xc6, 0x85, 0xad, 0x9f, 0x9e, - }, - { - 0xe9, 0x97, 0xde, 0x7f, 0xe0, 0x9a, 0xc1, 0xdc, 0x96, 0x4c, 0xc3, 0x0d, 0x2d, 0xd4, 0x98, 0x54, - 0x89, 0x1c, 0x57, 0x7d, 0x17, 0x96, 0xe9, 0x2f, 0x02, 0x73, 0x07, 0x5c, 0x8b, 0x44, 0xd7, 0x75, - }, - { - 0xaf, 0xf2, 0x39, 0xc4, 0x23, 0xff, 0xd5, 0x85, 0xf3, 0x11, 0x44, 0x9e, 0xab, 0x59, 0x29, 0x33, - 0xe6, 0xc2, 0x1d, 0xba, 0xa8, 0x5b, 0x70, 0xc3, 0xc0, 0xf8, 0x56, 0x3b, 0x8e, 0x43, 0x4c, 0x4b, - }, - { - 0x46, 0x93, 0xb5, 0x8a, 0x71, 0x67, 0xcb, 0x42, 0x6b, 0x1b, 0x43, 0x58, 0x8b, 0x18, 0xb9, 0xf3, - 0xdc, 0x91, 0x1c, 0x08, 0x83, 0xe3, 0x63, 0xfa, 0xf9, 0x99, 0x99, 0xcb, 0x05, 0x15, 0x7b, 0x85, - }, - { - 0xcf, 0xc6, 0x3c, 0x01, 0xbd, 0xfb, 0x00, 0x8c, 0x8b, 0x07, 0x69, 0xac, 0x61, 0xdb, 0x30, 0xd5, - 0x7c, 0x71, 0x98, 0x69, 0x2e, 0x4a, 0x4a, 0x44, 0xe4, 0x72, 0x6f, 0xf2, 0x9d, 0x58, 0x02, 0x23, - }, - { - 0x29, 0x10, 0xe1, 0xe5, 0x3f, 0xe6, 0x26, 0xaf, 0x30, 0x3c, 0xfe, 0x1f, 0x97, 0x21, 0xdd, 0x8c, - 0xbb, 0x90, 0xdb, 0x2a, 0xb5, 0xb4, 0x46, 0x43, 0x50, 0x0b, 0x6b, 0xa8, 0x8f, 0x55, 0xfb, 0xd2, - }, - { - 0x89, 0x56, 0x19, 0xf9, 0x4a, 0xec, 0x38, 0x99, 0xaa, 0xcc, 0xc5, 0x15, 0xdf, 0x19, 0xee, 0x1a, - 0xc0, 0x94, 0xaf, 0x0f, 0x7b, 0xf4, 0x06, 0xf1, 0x70, 0xa3, 0x79, 0x06, 0xba, 0x4e, 0x09, 0xa6, - }, - { - 0x53, 0x3a, 0x35, 0x98, 0xa9, 0xcb, 0x2c, 0x72, 0x73, 0xb2, 0xb0, 0x63, 0x38, 0xfc, 0xa3, 0xa5, - 0xa3, 0xf1, 0x4d, 0x04, 0x2f, 0x1b, 0x83, 0xbd, 0xed, 0x20, 0x8e, 0xa5, 0x1e, 0x9d, 0xd6, 0x69, - }, - { - 0x78, 0x44, 0xe3, 0x22, 0xa4, 0x7c, 0x53, 0xef, 0x60, 0x8e, 0x39, 0x95, 0x7d, 0x9d, 0x3d, 0x0b, - 0x4a, 0x4f, 0xf4, 0x73, 0xf8, 0xfe, 0xe7, 0x65, 0x86, 0x72, 0x13, 0x0b, 0x4e, 0x8f, 0x4d, 0x7b, - }, - { - 0x46, 0xba, 0xd2, 0x82, 0x46, 0x18, 0x6e, 0x46, 0x96, 0x05, 0x1d, 0xfb, 0xf6, 0xde, 0xba, 0xb5, - 0x6b, 0x73, 0x7a, 0xd5, 0x76, 0x11, 0xb7, 0x7c, 0x0d, 0x61, 0xba, 0xf9, 0x05, 0x12, 0x2b, 0x4e, - }, - { - 0x41, 0x08, 0x8b, 0x63, 0x10, 0xeb, 0x85, 0x10, 0xf3, 0x05, 0x84, 0xc0, 0x81, 0x1f, 0x7f, 0xd3, - 0x9d, 0x01, 0xdc, 0x32, 0xd0, 0xe2, 0xd1, 0xd1, 0x41, 0x8a, 0xa0, 0xf2, 0x64, 0xda, 0x8b, 0x0e, - }, - { - 0x99, 0xf1, 0xf2, 0x88, 0xe8, 0x72, 0x8b, 0x40, 0x17, 0xcc, 0xa7, 0x4c, 0x7d, 0xf1, 0xc4, 0x3f, - 0xbf, 0xf8, 0xbe, 0xc9, 0xce, 0xce, 0x2b, 0xe9, 0x4d, 0x5b, 0xd1, 0xef, 0x76, 0xae, 0x3b, 0xbb, - }, - { - 0x64, 0x69, 0x47, 0x03, 0xe9, 0x3b, 0xc2, 0x2d, 0x2d, 0x1a, 0xdd, 0xa4, 0xac, 0xb6, 0x6e, 0x7a, - 0x41, 0x7d, 0x82, 0xed, 0x54, 0xf7, 0x05, 0xd8, 0xae, 0x07, 0x6c, 0x1c, 0xf6, 0x51, 0xa1, 0xc0, - }, - { - 0x84, 0xaf, 0xe8, 0x59, 0x0c, 0x14, 0x24, 0xec, 0xa0, 0xd2, 0xf3, 0x8f, 0x2f, 0x22, 0xe4, 0x52, - 0xf8, 0xa7, 0x39, 0x74, 0x7f, 0x80, 0x23, 0x3f, 0x30, 0xe3, 0xcb, 0x26, 0x12, 0x5c, 0xa7, 0x93, - }, - { - 0x48, 0xc8, 0x41, 0x42, 0xc5, 0xe7, 0x4d, 0x91, 0x54, 0xa6, 0x5b, 0xba, 0x46, 0x89, 0xd5, 0x42, - 0x46, 0xbc, 0xf2, 0x67, 0x4a, 0xf9, 0x88, 0xe9, 0x02, 0xa5, 0xc2, 0x38, 0x9d, 0x6a, 0x75, 0xcd, - }, - { - 0xab, 0x9b, 0x2c, 0x09, 0xda, 0xaa, 0xe9, 0xe2, 0xd7, 0xf1, 0xa4, 0x86, 0x41, 0x14, 0xcb, 0x4e, - 0x2b, 0xd1, 0x5a, 0x9a, 0x46, 0x47, 0x90, 0xb2, 0x63, 0x16, 0xcb, 0x60, 0x1c, 0x12, 0xe3, 0x2b, - }, - { - 0x54, 0x21, 0xc0, 0xbc, 0xb8, 0x29, 0xce, 0xa4, 0xf2, 0x38, 0xb4, 0x0d, 0x7d, 0xfa, 0xd4, 0x3e, - 0x28, 0xf4, 0xc4, 0xf4, 0x4a, 0x9f, 0x11, 0xf2, 0xe2, 0x31, 0xa3, 0x72, 0x16, 0xbb, 0xd9, 0x05, - }, - { - 0xdc, 0x6e, 0xbe, 0x64, 0xa2, 0xb2, 0x64, 0x46, 0x00, 0xee, 0xd2, 0xa5, 0x81, 0x86, 0x44, 0xa4, - 0x5c, 0xc4, 0xba, 0xc4, 0xa2, 0x44, 0x36, 0x77, 0xb2, 0xec, 0x0d, 0xbe, 0x8f, 0xc0, 0x80, 0x6f, - }, - { - 0x51, 0x51, 0xb2, 0x50, 0x11, 0x0b, 0x60, 0xb8, 0x8e, 0xc2, 0xf7, 0xa8, 0xb4, 0xd2, 0x48, 0xc3, - 0x51, 0x43, 0x52, 0xeb, 0x37, 0xac, 0xd0, 0xf7, 0x61, 0xa1, 0xe9, 0xe3, 0xa7, 0xdf, 0x26, 0xa9, - }, - { - 0x10, 0xd9, 0xf2, 0xfe, 0x71, 0x8e, 0x49, 0x2c, 0x64, 0x53, 0xb0, 0x9e, 0x7a, 0xcc, 0x86, 0xab, - 0x06, 0xd7, 0xc7, 0x13, 0xd1, 0xcb, 0x21, 0x42, 0x97, 0x29, 0x5d, 0xff, 0xaa, 0xec, 0x52, 0x40, - }, - { - 0x7b, 0x35, 0x93, 0xb9, 0xca, 0xbb, 0x7e, 0x09, 0x8f, 0x34, 0x32, 0x02, 0xe7, 0x0c, 0xcf, 0xd1, - 0x6c, 0x2d, 0x11, 0xcd, 0xa5, 0x3b, 0xba, 0x14, 0x47, 0xc5, 0x2c, 0xb8, 0xf6, 0xfb, 0x9d, 0x77, - }, - { - 0x45, 0xce, 0x12, 0x8e, 0xa2, 0x4e, 0x56, 0x58, 0xa7, 0xcf, 0x26, 0x4e, 0x32, 0x21, 0xe0, 0x2b, - 0xed, 0x8d, 0xe2, 0xd9, 0x51, 0x32, 0x9b, 0xdc, 0x7b, 0x0e, 0x14, 0x0a, 0xdb, 0x63, 0x6b, 0x42, - }, - { - 0x9d, 0x49, 0x72, 0xea, 0x89, 0xc7, 0xa2, 0xfd, 0x9a, 0x55, 0xd7, 0x05, 0x16, 0xeb, 0xf7, 0x49, - 0xb6, 0xcf, 0x56, 0xf7, 0x2b, 0xef, 0x6d, 0xbe, 0xdd, 0x0e, 0x90, 0x01, 0xaf, 0x1b, 0xbb, 0xaa, - }, - { - 0x2c, 0xb7, 0x26, 0x43, 0x02, 0xc5, 0x7b, 0xc6, 0x71, 0x1f, 0xf2, 0x28, 0xb4, 0xea, 0x5f, 0x02, - 0xc6, 0xeb, 0xb4, 0xf7, 0x6f, 0x01, 0x7f, 0xfe, 0x3a, 0xb0, 0xe3, 0xf3, 0x31, 0xd3, 0xcb, 0x0f, - }, - { - 0x75, 0x54, 0x90, 0xec, 0xed, 0xcc, 0xbc, 0x5c, 0x9b, 0x44, 0x30, 0x57, 0x57, 0xe0, 0xec, 0x58, - 0x20, 0x54, 0x20, 0xb0, 0x92, 0x3a, 0x06, 0x9f, 0x69, 0xcb, 0x88, 0xee, 0x52, 0x6e, 0x4c, 0xf6, - }, - { - 0x2a, 0x08, 0xd8, 0xdd, 0x2e, 0x07, 0x54, 0x0b, 0x37, 0xc6, 0x09, 0x26, 0x98, 0xf7, 0x45, 0xf6, - 0x05, 0x4f, 0x35, 0xe6, 0xb0, 0x44, 0xff, 0x62, 0x89, 0x47, 0x69, 0x30, 0xea, 0x3b, 0x7b, 0x81, - }, - { - 0x0f, 0x7f, 0x34, 0xbf, 0xf9, 0xce, 0xe7, 0x4c, 0xe1, 0x7a, 0x24, 0x74, 0xeb, 0x8b, 0xb0, 0x65, - 0x18, 0x19, 0xaf, 0x44, 0x45, 0x5e, 0xd9, 0xa4, 0xf0, 0xd8, 0xe8, 0x09, 0x22, 0x58, 0x4e, 0x4d, - }, - { - 0x48, 0x41, 0x7a, 0xd2, 0x26, 0xda, 0x39, 0xb2, 0xba, 0x03, 0x17, 0xe9, 0x80, 0x8e, 0x53, 0x4c, - 0xac, 0x64, 0x6b, 0xa7, 0x5f, 0xed, 0x64, 0x60, 0xb7, 0x5e, 0x7a, 0x68, 0x1a, 0x8a, 0xda, 0x2b, - }, - { - 0x52, 0x01, 0x25, 0xb0, 0x59, 0xcf, 0x61, 0x30, 0x52, 0xe7, 0x77, 0x66, 0xc9, 0x35, 0xac, 0xfe, - 0xc0, 0xa2, 0x18, 0x58, 0xf1, 0xc1, 0x8f, 0x28, 0x72, 0x2f, 0xdc, 0x36, 0x10, 0x5b, 0xd9, 0x6f, - }, - { - 0x05, 0xbf, 0x47, 0x32, 0x0e, 0xa7, 0xc6, 0xd6, 0x13, 0xa1, 0x72, 0x38, 0x8c, 0x1a, 0xbc, 0x6d, - 0x7c, 0xd8, 0x34, 0xac, 0x69, 0x5b, 0x43, 0xc4, 0x00, 0xf8, 0xf2, 0xa7, 0xaf, 0x9f, 0xb0, 0xde, - }, - { - 0x54, 0x67, 0xce, 0xf2, 0xfc, 0x91, 0xd2, 0x4d, 0x73, 0xc6, 0xc9, 0xc3, 0xfe, 0xcf, 0x72, 0xa0, - 0xc7, 0x43, 0xff, 0x87, 0x4b, 0xe3, 0x7f, 0xba, 0xd4, 0xa2, 0xa3, 0x14, 0x8f, 0xa0, 0x39, 0x91, - }, - { - 0xbd, 0x24, 0x35, 0xb5, 0x0e, 0x7a, 0x13, 0xb3, 0x92, 0x83, 0xaa, 0xbd, 0x0c, 0x22, 0x93, 0xbb, - 0x2a, 0xe7, 0x7a, 0x56, 0x2d, 0xae, 0x41, 0x62, 0x52, 0xb2, 0xe9, 0xbd, 0x29, 0x05, 0x51, 0x95, - }, - { - 0x97, 0x8f, 0x21, 0x82, 0x72, 0x4f, 0x65, 0xc8, 0xfc, 0x2e, 0x5e, 0x8a, 0x1a, 0xce, 0x34, 0x39, - 0x12, 0xe6, 0x9b, 0xc3, 0xab, 0x51, 0xa9, 0x40, 0xf7, 0xbe, 0x94, 0xd0, 0x66, 0xda, 0xa5, 0x39, - }, - { - 0x5a, 0x48, 0x43, 0x9a, 0x8e, 0x22, 0x85, 0x9b, 0x28, 0xc9, 0x63, 0xa2, 0x57, 0xa6, 0xe2, 0x16, - 0x64, 0xec, 0x3c, 0x59, 0x13, 0xc4, 0x7b, 0x51, 0xea, 0xfe, 0x2e, 0x70, 0xbd, 0xd9, 0x77, 0x85, - }, - { - 0x2b, 0x74, 0xb6, 0x95, 0x18, 0x94, 0x54, 0x6d, 0xae, 0xdd, 0xe9, 0xb2, 0xf9, 0xbd, 0xce, 0x27, - 0xa9, 0x87, 0x42, 0x13, 0x22, 0x29, 0x87, 0x7a, 0x04, 0xe3, 0xbe, 0x2f, 0x9c, 0x18, 0xbb, 0x13, - }, - { - 0x80, 0x95, 0x43, 0xaa, 0x19, 0x90, 0x03, 0x4f, 0x47, 0xbf, 0xf5, 0x8e, 0x2d, 0x55, 0x23, 0xb7, - 0x7b, 0x5d, 0xaa, 0x34, 0x37, 0xb2, 0x70, 0x86, 0x5e, 0xc4, 0x94, 0xf3, 0x61, 0xfd, 0x87, 0x65, - }, - { - 0xd4, 0xbc, 0x03, 0x65, 0xb0, 0xc5, 0x44, 0x81, 0x7b, 0x06, 0x94, 0x79, 0xca, 0x1f, 0xe2, 0x28, - 0x53, 0xc8, 0xa7, 0x10, 0x13, 0x77, 0xb7, 0x5c, 0x9a, 0x34, 0x1e, 0xd5, 0x78, 0xb1, 0x21, 0x61, - }, - { - 0x90, 0x0e, 0x7f, 0xa3, 0x24, 0x18, 0x12, 0xbf, 0x45, 0xd2, 0x52, 0xa3, 0x99, 0x74, 0x89, 0xd2, - 0x12, 0x8d, 0x32, 0x3c, 0xd0, 0x28, 0x54, 0x98, 0x6c, 0x9e, 0xdd, 0xc0, 0xd5, 0xf1, 0x8a, 0xb1, - }, - { - 0x82, 0xad, 0x7a, 0x5c, 0x4d, 0x81, 0x54, 0x41, 0x79, 0x42, 0x54, 0x5c, 0x49, 0x41, 0xed, 0x49, - 0xc7, 0x06, 0x61, 0xbb, 0x89, 0x2b, 0x90, 0x04, 0x1f, 0x8c, 0x31, 0x3b, 0x39, 0x4f, 0xf8, 0x33, - }, +const u8 use_base[63][32] = { + {0x0e, 0x9e, 0xa1, 0x39, 0x06, 0x26, 0xc5, 0xe9, + 0xed, 0x07, 0x49, 0x3b, 0x34, 0x7f, 0x1c, 0xa8, + 0xdf, 0x7b, 0xb7, 0xb8, 0x28, 0xbe, 0x8a, 0x70, + 0x17, 0xe5, 0xc0, 0x44, 0x4a, 0x8e, 0x61, 0x3b}, + {0x42, 0xe6, 0xe0, 0x6a, 0xb3, 0x08, 0x28, 0xaf, + 0xfa, 0xb9, 0xb7, 0x32, 0x83, 0x5c, 0xef, 0x3d, + 0x90, 0x91, 0x64, 0x31, 0xe9, 0x3c, 0x92, 0xe6, + 0xa3, 0xd4, 0x6a, 0xc6, 0x01, 0xa6, 0xeb, 0xe6}, + {0x39, 0x7f, 0x6f, 0x81, 0xb4, 0x33, 0x4a, 0xde, + 0x4f, 0x77, 0x28, 0x47, 0x08, 0xf9, 0x3a, 0x55, + 0x21, 0x57, 0x27, 0x59, 0xf5, 0x96, 0xad, 0xc1, + 0x10, 0x33, 0xe0, 0xe2, 0xf8, 0xb6, 0x49, 0xbd}, + {0xdf, 0x57, 0x60, 0x27, 0x95, 0x50, 0x3a, 0x8c, + 0x34, 0x8b, 0xae, 0xc5, 0x69, 0x26, 0xca, 0x39, + 0x55, 0x98, 0xfb, 0x05, 0x3c, 0x1c, 0x8d, 0xf8, + 0xb9, 0x99, 0x05, 0x40, 0xe5, 0x5e, 0x2f, 0xf6}, + {0xc1, 0x6a, 0xea, 0xd6, 0x39, 0x56, 0x08, 0x89, + 0x83, 0x4c, 0xef, 0xda, 0xb2, 0x69, 0x76, 0xe4, + 0x75, 0x3f, 0x39, 0x13, 0x96, 0xb5, 0x41, 0x84, + 0x00, 0x64, 0x79, 0x47, 0xe4, 0xcb, 0xc3, 0xd0}, + {0xf8, 0xb1, 0x19, 0x76, 0x51, 0x99, 0xd7, 0x45, + 0x38, 0x40, 0xbf, 0x10, 0x4c, 0x89, 0x43, 0xa9, + 0x89, 0xe2, 0x85, 0x3f, 0xb4, 0xe8, 0xbf, 0x5e, + 0xc2, 0xb4, 0x16, 0x6d, 0x1c, 0x61, 0xca, 0x40}, + {0x1c, 0xdc, 0xa6, 0xdb, 0x71, 0x8b, 0xf9, 0xbb, + 0xee, 0xc2, 0xa5, 0x66, 0xa4, 0xbc, 0xb6, 0x89, + 0x58, 0xb9, 0x6f, 0x57, 0x71, 0x57, 0x5c, 0xf0, + 0xed, 0xcf, 0x2c, 0x2e, 0x1d, 0x34, 0xc3, 0x00}, + {0x1d, 0x30, 0x03, 0xb9, 0x15, 0x8e, 0x47, 0x8c, + 0xf2, 0x4e, 0x2d, 0xf1, 0xbf, 0x96, 0xa7, 0xa1, + 0x3f, 0x26, 0xc3, 0xc9, 0x08, 0x0b, 0xa8, 0xdd, + 0x9b, 0xeb, 0xbc, 0x77, 0x1c, 0x10, 0x03, 0x77}, + {0x50, 0x7e, 0x62, 0x26, 0xcb, 0x49, 0x7b, 0x1a, + 0xd4, 0x54, 0xf1, 0x25, 0x3d, 0xa2, 0xe6, 0x8a, + 0xb3, 0x62, 0xf1, 0x7e, 0x03, 0xef, 0x1b, 0x27, + 0x21, 0xcc, 0xfc, 0x72, 0x30, 0x0c, 0x69, 0xad}, + {0x11, 0xf5, 0xb2, 0xfa, 0x2d, 0xbc, 0xa1, 0xd9, + 0x74, 0x15, 0x59, 0xf2, 0xc6, 0x66, 0x4f, 0xde, + 0x84, 0x82, 0x4f, 0xe8, 0x33, 0xd5, 0xc5, 0xdd, + 0xba, 0x0c, 0xc7, 0x51, 0x1f, 0x3c, 0x6d, 0x44}, + {0xcf, 0xf5, 0x3b, 0xc1, 0xbd, 0x5f, 0x9c, 0xad, + 0x57, 0xfb, 0xfc, 0xbe, 0x95, 0xa0, 0x48, 0x58, + 0x8a, 0x68, 0x97, 0x71, 0xf3, 0xc0, 0xd1, 0x31, + 0x33, 0xb9, 0x3c, 0xe9, 0x4f, 0xbb, 0x8d, 0xeb}, + {0x29, 0x0c, 0xa1, 0xc8, 0x04, 0xdc, 0xf9, 0x25, + 0x85, 0x7e, 0xea, 0x6d, 0x75, 0x28, 0x69, 0x3f, + 0x3a, 0x83, 0xe4, 0x33, 0x31, 0x77, 0x57, 0x2e, + 0xa9, 0xa8, 0x05, 0xfe, 0x19, 0xb7, 0xc4, 0xd1}, + {0x6d, 0x5d, 0x3f, 0x4f, 0x8a, 0x6a, 0x77, 0x2d, + 0xf7, 0x9f, 0x73, 0xab, 0x40, 0xd9, 0x89, 0x57, + 0x69, 0xd7, 0xc8, 0xc3, 0x69, 0x54, 0x93, 0x7c, + 0x9f, 0x4a, 0xcc, 0xaf, 0xcc, 0x0e, 0xe0, 0xb8}, + {0xb6, 0xd5, 0x36, 0x3f, 0x1c, 0x34, 0x54, 0x9b, + 0xfc, 0xec, 0x5b, 0xb0, 0x26, 0xa6, 0xc0, 0x61, + 0x6d, 0x4c, 0x4f, 0x86, 0x2a, 0xbd, 0x34, 0x35, + 0x52, 0x2c, 0x82, 0x01, 0x66, 0x0e, 0x80, 0x01}, + {0x48, 0x39, 0x43, 0xb8, 0xf9, 0x2b, 0x25, 0xe8, + 0xf7, 0xf0, 0x1a, 0xed, 0x33, 0x1e, 0x30, 0xba, + 0x15, 0x37, 0xeb, 0xae, 0x97, 0xa7, 0x36, 0xa4, + 0xc7, 0x1f, 0x91, 0x01, 0x38, 0x80, 0x5a, 0x76}, + {0x74, 0xbe, 0x15, 0x6b, 0x85, 0x28, 0xe4, 0xc4, + 0x13, 0x68, 0x67, 0x03, 0x27, 0x7e, 0x32, 0x08, + 0x87, 0x23, 0xda, 0xf2, 0x47, 0xdd, 0xac, 0x2c, + 0xc5, 0x7f, 0x06, 0xc8, 0x17, 0x4c, 0x6c, 0x81}, + {0x0d, 0x9f, 0x68, 0xbb, 0xa6, 0x6c, 0x7d, 0x3f, + 0x81, 0xcf, 0x9a, 0x52, 0x87, 0xce, 0x98, 0x25, + 0x40, 0x2b, 0x1b, 0xdf, 0xd3, 0x6b, 0x53, 0xed, + 0x80, 0xd2, 0x3d, 0xca, 0xdf, 0x07, 0x4e, 0x6b}, + {0xff, 0xf1, 0xd2, 0x1f, 0xbd, 0xd6, 0xa7, 0x3d, + 0xb4, 0xc6, 0x88, 0x9d, 0x7b, 0x05, 0x04, 0x0b, + 0x4c, 0x6f, 0x11, 0x7f, 0x19, 0x18, 0x48, 0xf1, + 0x26, 0xad, 0xd0, 0x60, 0xfa, 0x40, 0x35, 0xbb}, + {0xae, 0xec, 0x0e, 0x2e, 0xfd, 0x46, 0xf0, 0x9c, + 0x06, 0x1b, 0x62, 0xbf, 0xf0, 0x3e, 0xba, 0xdf, + 0xb2, 0xa2, 0x83, 0x83, 0xda, 0x04, 0x15, 0xec, + 0x1e, 0x2e, 0x1a, 0x64, 0x08, 0x8e, 0xd3, 0x87}, + {0x61, 0x14, 0x05, 0x0b, 0xdb, 0xf4, 0xf0, 0xa3, + 0x41, 0x11, 0x7b, 0xd9, 0xa1, 0x40, 0x4f, 0x62, + 0x98, 0x37, 0xa0, 0x90, 0x3d, 0x78, 0x63, 0x24, + 0xbc, 0x8e, 0x9e, 0x99, 0x2e, 0xc7, 0xb1, 0x6d}, + {0x0f, 0xf1, 0x5f, 0xe4, 0x94, 0x3d, 0x24, 0x0d, + 0xa2, 0xcf, 0xed, 0xbb, 0x55, 0x8e, 0xdb, 0x07, + 0x12, 0x05, 0x79, 0x82, 0xb1, 0x3a, 0x71, 0x76, + 0xbb, 0x8b, 0xcb, 0xcc, 0x00, 0x40, 0x2e, 0xab}, + {0x48, 0x59, 0xfa, 0x46, 0x15, 0x5e, 0xa2, 0x0d, + 0xe8, 0x81, 0x69, 0xe6, 0x2f, 0x5f, 0x6d, 0xaf, + 0xad, 0xc7, 0x30, 0xd6, 0xec, 0x03, 0x1e, 0x19, + 0xdd, 0x1d, 0x00, 0x94, 0x0b, 0x93, 0x5a, 0x28}, + {0xfa, 0x64, 0x62, 0x57, 0x02, 0x7e, 0x37, 0xb8, + 0x10, 0xa9, 0x4b, 0xe7, 0xbf, 0x03, 0xdc, 0x1c, + 0xe7, 0x21, 0x68, 0x60, 0x53, 0xec, 0xf0, 0xfc, + 0xbf, 0xe5, 0x8e, 0xca, 0x77, 0xdb, 0xa5, 0xae}, + {0xc1, 0xa9, 0x9f, 0xc2, 0x87, 0x11, 0xad, 0x1c, + 0xc5, 0x56, 0x61, 0xc0, 0x20, 0x33, 0xc9, 0x85, + 0xf0, 0x81, 0x36, 0x18, 0xdb, 0xaa, 0x7e, 0x79, + 0x36, 0x2d, 0xfc, 0x8f, 0x72, 0x3c, 0x4c, 0xa3}, + {0xb4, 0xd3, 0x38, 0xed, 0xd3, 0x6c, 0x03, 0x26, + 0x0e, 0x1c, 0x8a, 0xa8, 0x72, 0x17, 0xcb, 0xf7, + 0x87, 0xf3, 0x3f, 0x73, 0x5d, 0x12, 0xe8, 0x3b, + 0x55, 0xb6, 0xcc, 0xc6, 0x85, 0xad, 0x9f, 0x9e}, + {0xe9, 0x97, 0xde, 0x7f, 0xe0, 0x9a, 0xc1, 0xdc, + 0x96, 0x4c, 0xc3, 0x0d, 0x2d, 0xd4, 0x98, 0x54, + 0x89, 0x1c, 0x57, 0x7d, 0x17, 0x96, 0xe9, 0x2f, + 0x02, 0x73, 0x07, 0x5c, 0x8b, 0x44, 0xd7, 0x75}, + {0xaf, 0xf2, 0x39, 0xc4, 0x23, 0xff, 0xd5, 0x85, + 0xf3, 0x11, 0x44, 0x9e, 0xab, 0x59, 0x29, 0x33, + 0xe6, 0xc2, 0x1d, 0xba, 0xa8, 0x5b, 0x70, 0xc3, + 0xc0, 0xf8, 0x56, 0x3b, 0x8e, 0x43, 0x4c, 0x4b}, + {0x46, 0x93, 0xb5, 0x8a, 0x71, 0x67, 0xcb, 0x42, + 0x6b, 0x1b, 0x43, 0x58, 0x8b, 0x18, 0xb9, 0xf3, + 0xdc, 0x91, 0x1c, 0x08, 0x83, 0xe3, 0x63, 0xfa, + 0xf9, 0x99, 0x99, 0xcb, 0x05, 0x15, 0x7b, 0x85}, + {0xcf, 0xc6, 0x3c, 0x01, 0xbd, 0xfb, 0x00, 0x8c, + 0x8b, 0x07, 0x69, 0xac, 0x61, 0xdb, 0x30, 0xd5, + 0x7c, 0x71, 0x98, 0x69, 0x2e, 0x4a, 0x4a, 0x44, + 0xe4, 0x72, 0x6f, 0xf2, 0x9d, 0x58, 0x02, 0x23}, + {0x29, 0x10, 0xe1, 0xe5, 0x3f, 0xe6, 0x26, 0xaf, + 0x30, 0x3c, 0xfe, 0x1f, 0x97, 0x21, 0xdd, 0x8c, + 0xbb, 0x90, 0xdb, 0x2a, 0xb5, 0xb4, 0x46, 0x43, + 0x50, 0x0b, 0x6b, 0xa8, 0x8f, 0x55, 0xfb, 0xd2}, + {0x89, 0x56, 0x19, 0xf9, 0x4a, 0xec, 0x38, 0x99, + 0xaa, 0xcc, 0xc5, 0x15, 0xdf, 0x19, 0xee, 0x1a, + 0xc0, 0x94, 0xaf, 0x0f, 0x7b, 0xf4, 0x06, 0xf1, + 0x70, 0xa3, 0x79, 0x06, 0xba, 0x4e, 0x09, 0xa6}, + {0x53, 0x3a, 0x35, 0x98, 0xa9, 0xcb, 0x2c, 0x72, + 0x73, 0xb2, 0xb0, 0x63, 0x38, 0xfc, 0xa3, 0xa5, + 0xa3, 0xf1, 0x4d, 0x04, 0x2f, 0x1b, 0x83, 0xbd, + 0xed, 0x20, 0x8e, 0xa5, 0x1e, 0x9d, 0xd6, 0x69}, + {0x78, 0x44, 0xe3, 0x22, 0xa4, 0x7c, 0x53, 0xef, + 0x60, 0x8e, 0x39, 0x95, 0x7d, 0x9d, 0x3d, 0x0b, + 0x4a, 0x4f, 0xf4, 0x73, 0xf8, 0xfe, 0xe7, 0x65, + 0x86, 0x72, 0x13, 0x0b, 0x4e, 0x8f, 0x4d, 0x7b}, + {0x46, 0xba, 0xd2, 0x82, 0x46, 0x18, 0x6e, 0x46, + 0x96, 0x05, 0x1d, 0xfb, 0xf6, 0xde, 0xba, 0xb5, + 0x6b, 0x73, 0x7a, 0xd5, 0x76, 0x11, 0xb7, 0x7c, + 0x0d, 0x61, 0xba, 0xf9, 0x05, 0x12, 0x2b, 0x4e}, + {0x41, 0x08, 0x8b, 0x63, 0x10, 0xeb, 0x85, 0x10, + 0xf3, 0x05, 0x84, 0xc0, 0x81, 0x1f, 0x7f, 0xd3, + 0x9d, 0x01, 0xdc, 0x32, 0xd0, 0xe2, 0xd1, 0xd1, + 0x41, 0x8a, 0xa0, 0xf2, 0x64, 0xda, 0x8b, 0x0e}, + {0x99, 0xf1, 0xf2, 0x88, 0xe8, 0x72, 0x8b, 0x40, + 0x17, 0xcc, 0xa7, 0x4c, 0x7d, 0xf1, 0xc4, 0x3f, + 0xbf, 0xf8, 0xbe, 0xc9, 0xce, 0xce, 0x2b, 0xe9, + 0x4d, 0x5b, 0xd1, 0xef, 0x76, 0xae, 0x3b, 0xbb}, + {0x64, 0x69, 0x47, 0x03, 0xe9, 0x3b, 0xc2, 0x2d, + 0x2d, 0x1a, 0xdd, 0xa4, 0xac, 0xb6, 0x6e, 0x7a, + 0x41, 0x7d, 0x82, 0xed, 0x54, 0xf7, 0x05, 0xd8, + 0xae, 0x07, 0x6c, 0x1c, 0xf6, 0x51, 0xa1, 0xc0}, + {0x84, 0xaf, 0xe8, 0x59, 0x0c, 0x14, 0x24, 0xec, + 0xa0, 0xd2, 0xf3, 0x8f, 0x2f, 0x22, 0xe4, 0x52, + 0xf8, 0xa7, 0x39, 0x74, 0x7f, 0x80, 0x23, 0x3f, + 0x30, 0xe3, 0xcb, 0x26, 0x12, 0x5c, 0xa7, 0x93}, + {0x48, 0xc8, 0x41, 0x42, 0xc5, 0xe7, 0x4d, 0x91, + 0x54, 0xa6, 0x5b, 0xba, 0x46, 0x89, 0xd5, 0x42, + 0x46, 0xbc, 0xf2, 0x67, 0x4a, 0xf9, 0x88, 0xe9, + 0x02, 0xa5, 0xc2, 0x38, 0x9d, 0x6a, 0x75, 0xcd}, + {0xab, 0x9b, 0x2c, 0x09, 0xda, 0xaa, 0xe9, 0xe2, + 0xd7, 0xf1, 0xa4, 0x86, 0x41, 0x14, 0xcb, 0x4e, + 0x2b, 0xd1, 0x5a, 0x9a, 0x46, 0x47, 0x90, 0xb2, + 0x63, 0x16, 0xcb, 0x60, 0x1c, 0x12, 0xe3, 0x2b}, + {0x54, 0x21, 0xc0, 0xbc, 0xb8, 0x29, 0xce, 0xa4, + 0xf2, 0x38, 0xb4, 0x0d, 0x7d, 0xfa, 0xd4, 0x3e, + 0x28, 0xf4, 0xc4, 0xf4, 0x4a, 0x9f, 0x11, 0xf2, + 0xe2, 0x31, 0xa3, 0x72, 0x16, 0xbb, 0xd9, 0x05}, + {0xdc, 0x6e, 0xbe, 0x64, 0xa2, 0xb2, 0x64, 0x46, + 0x00, 0xee, 0xd2, 0xa5, 0x81, 0x86, 0x44, 0xa4, + 0x5c, 0xc4, 0xba, 0xc4, 0xa2, 0x44, 0x36, 0x77, + 0xb2, 0xec, 0x0d, 0xbe, 0x8f, 0xc0, 0x80, 0x6f}, + {0x51, 0x51, 0xb2, 0x50, 0x11, 0x0b, 0x60, 0xb8, + 0x8e, 0xc2, 0xf7, 0xa8, 0xb4, 0xd2, 0x48, 0xc3, + 0x51, 0x43, 0x52, 0xeb, 0x37, 0xac, 0xd0, 0xf7, + 0x61, 0xa1, 0xe9, 0xe3, 0xa7, 0xdf, 0x26, 0xa9}, + {0x10, 0xd9, 0xf2, 0xfe, 0x71, 0x8e, 0x49, 0x2c, + 0x64, 0x53, 0xb0, 0x9e, 0x7a, 0xcc, 0x86, 0xab, + 0x06, 0xd7, 0xc7, 0x13, 0xd1, 0xcb, 0x21, 0x42, + 0x97, 0x29, 0x5d, 0xff, 0xaa, 0xec, 0x52, 0x40}, + {0x7b, 0x35, 0x93, 0xb9, 0xca, 0xbb, 0x7e, 0x09, + 0x8f, 0x34, 0x32, 0x02, 0xe7, 0x0c, 0xcf, 0xd1, + 0x6c, 0x2d, 0x11, 0xcd, 0xa5, 0x3b, 0xba, 0x14, + 0x47, 0xc5, 0x2c, 0xb8, 0xf6, 0xfb, 0x9d, 0x77}, + {0x45, 0xce, 0x12, 0x8e, 0xa2, 0x4e, 0x56, 0x58, + 0xa7, 0xcf, 0x26, 0x4e, 0x32, 0x21, 0xe0, 0x2b, + 0xed, 0x8d, 0xe2, 0xd9, 0x51, 0x32, 0x9b, 0xdc, + 0x7b, 0x0e, 0x14, 0x0a, 0xdb, 0x63, 0x6b, 0x42}, + {0x9d, 0x49, 0x72, 0xea, 0x89, 0xc7, 0xa2, 0xfd, + 0x9a, 0x55, 0xd7, 0x05, 0x16, 0xeb, 0xf7, 0x49, + 0xb6, 0xcf, 0x56, 0xf7, 0x2b, 0xef, 0x6d, 0xbe, + 0xdd, 0x0e, 0x90, 0x01, 0xaf, 0x1b, 0xbb, 0xaa}, + {0x2c, 0xb7, 0x26, 0x43, 0x02, 0xc5, 0x7b, 0xc6, + 0x71, 0x1f, 0xf2, 0x28, 0xb4, 0xea, 0x5f, 0x02, + 0xc6, 0xeb, 0xb4, 0xf7, 0x6f, 0x01, 0x7f, 0xfe, + 0x3a, 0xb0, 0xe3, 0xf3, 0x31, 0xd3, 0xcb, 0x0f}, + {0x75, 0x54, 0x90, 0xec, 0xed, 0xcc, 0xbc, 0x5c, + 0x9b, 0x44, 0x30, 0x57, 0x57, 0xe0, 0xec, 0x58, + 0x20, 0x54, 0x20, 0xb0, 0x92, 0x3a, 0x06, 0x9f, + 0x69, 0xcb, 0x88, 0xee, 0x52, 0x6e, 0x4c, 0xf6}, + {0x2a, 0x08, 0xd8, 0xdd, 0x2e, 0x07, 0x54, 0x0b, + 0x37, 0xc6, 0x09, 0x26, 0x98, 0xf7, 0x45, 0xf6, + 0x05, 0x4f, 0x35, 0xe6, 0xb0, 0x44, 0xff, 0x62, + 0x89, 0x47, 0x69, 0x30, 0xea, 0x3b, 0x7b, 0x81}, + {0x0f, 0x7f, 0x34, 0xbf, 0xf9, 0xce, 0xe7, 0x4c, + 0xe1, 0x7a, 0x24, 0x74, 0xeb, 0x8b, 0xb0, 0x65, + 0x18, 0x19, 0xaf, 0x44, 0x45, 0x5e, 0xd9, 0xa4, + 0xf0, 0xd8, 0xe8, 0x09, 0x22, 0x58, 0x4e, 0x4d}, + {0x48, 0x41, 0x7a, 0xd2, 0x26, 0xda, 0x39, 0xb2, + 0xba, 0x03, 0x17, 0xe9, 0x80, 0x8e, 0x53, 0x4c, + 0xac, 0x64, 0x6b, 0xa7, 0x5f, 0xed, 0x64, 0x60, + 0xb7, 0x5e, 0x7a, 0x68, 0x1a, 0x8a, 0xda, 0x2b}, + {0x52, 0x01, 0x25, 0xb0, 0x59, 0xcf, 0x61, 0x30, + 0x52, 0xe7, 0x77, 0x66, 0xc9, 0x35, 0xac, 0xfe, + 0xc0, 0xa2, 0x18, 0x58, 0xf1, 0xc1, 0x8f, 0x28, + 0x72, 0x2f, 0xdc, 0x36, 0x10, 0x5b, 0xd9, 0x6f}, + {0x05, 0xbf, 0x47, 0x32, 0x0e, 0xa7, 0xc6, 0xd6, + 0x13, 0xa1, 0x72, 0x38, 0x8c, 0x1a, 0xbc, 0x6d, + 0x7c, 0xd8, 0x34, 0xac, 0x69, 0x5b, 0x43, 0xc4, + 0x00, 0xf8, 0xf2, 0xa7, 0xaf, 0x9f, 0xb0, 0xde}, + {0x54, 0x67, 0xce, 0xf2, 0xfc, 0x91, 0xd2, 0x4d, + 0x73, 0xc6, 0xc9, 0xc3, 0xfe, 0xcf, 0x72, 0xa0, + 0xc7, 0x43, 0xff, 0x87, 0x4b, 0xe3, 0x7f, 0xba, + 0xd4, 0xa2, 0xa3, 0x14, 0x8f, 0xa0, 0x39, 0x91}, + {0xbd, 0x24, 0x35, 0xb5, 0x0e, 0x7a, 0x13, 0xb3, + 0x92, 0x83, 0xaa, 0xbd, 0x0c, 0x22, 0x93, 0xbb, + 0x2a, 0xe7, 0x7a, 0x56, 0x2d, 0xae, 0x41, 0x62, + 0x52, 0xb2, 0xe9, 0xbd, 0x29, 0x05, 0x51, 0x95}, + {0x97, 0x8f, 0x21, 0x82, 0x72, 0x4f, 0x65, 0xc8, + 0xfc, 0x2e, 0x5e, 0x8a, 0x1a, 0xce, 0x34, 0x39, + 0x12, 0xe6, 0x9b, 0xc3, 0xab, 0x51, 0xa9, 0x40, + 0xf7, 0xbe, 0x94, 0xd0, 0x66, 0xda, 0xa5, 0x39}, + {0x5a, 0x48, 0x43, 0x9a, 0x8e, 0x22, 0x85, 0x9b, + 0x28, 0xc9, 0x63, 0xa2, 0x57, 0xa6, 0xe2, 0x16, + 0x64, 0xec, 0x3c, 0x59, 0x13, 0xc4, 0x7b, 0x51, + 0xea, 0xfe, 0x2e, 0x70, 0xbd, 0xd9, 0x77, 0x85}, + {0x2b, 0x74, 0xb6, 0x95, 0x18, 0x94, 0x54, 0x6d, + 0xae, 0xdd, 0xe9, 0xb2, 0xf9, 0xbd, 0xce, 0x27, + 0xa9, 0x87, 0x42, 0x13, 0x22, 0x29, 0x87, 0x7a, + 0x04, 0xe3, 0xbe, 0x2f, 0x9c, 0x18, 0xbb, 0x13}, + {0x80, 0x95, 0x43, 0xaa, 0x19, 0x90, 0x03, 0x4f, + 0x47, 0xbf, 0xf5, 0x8e, 0x2d, 0x55, 0x23, 0xb7, + 0x7b, 0x5d, 0xaa, 0x34, 0x37, 0xb2, 0x70, 0x86, + 0x5e, 0xc4, 0x94, 0xf3, 0x61, 0xfd, 0x87, 0x65}, + {0xd4, 0xbc, 0x03, 0x65, 0xb0, 0xc5, 0x44, 0x81, + 0x7b, 0x06, 0x94, 0x79, 0xca, 0x1f, 0xe2, 0x28, + 0x53, 0xc8, 0xa7, 0x10, 0x13, 0x77, 0xb7, 0x5c, + 0x9a, 0x34, 0x1e, 0xd5, 0x78, 0xb1, 0x21, 0x61}, + {0x90, 0x0e, 0x7f, 0xa3, 0x24, 0x18, 0x12, 0xbf, + 0x45, 0xd2, 0x52, 0xa3, 0x99, 0x74, 0x89, 0xd2, + 0x12, 0x8d, 0x32, 0x3c, 0xd0, 0x28, 0x54, 0x98, + 0x6c, 0x9e, 0xdd, 0xc0, 0xd5, 0xf1, 0x8a, 0xb1}, + {0x82, 0xad, 0x7a, 0x5c, 0x4d, 0x81, 0x54, 0x41, + 0x79, 0x42, 0x54, 0x5c, 0x49, 0x41, 0xed, 0x49, + 0xc7, 0x06, 0x61, 0xbb, 0x89, 0x2b, 0x90, 0x04, + 0x1f, 0x8c, 0x31, 0x3b, 0x39, 0x4f, 0xf8, 0x33}, }; -static const u8 invert[63][32] = { - { - 0x95, 0xb2, 0xa8, 0xe3, 0xac, 0xcf, 0x27, 0x3e, 0x1c, 0xa3, 0xcf, 0x7a, 0x20, 0xb4, 0x52, 0x83, - 0x0e, 0x21, 0x2d, 0xfe, 0x6f, 0x2e, 0x38, 0x13, 0x01, 0x2e, 0xa0, 0x58, 0x58, 0x6d, 0x4a, 0x6f, - }, - { - 0x63, 0x26, 0x5c, 0xd2, 0x9a, 0xc6, 0x8c, 0x5d, 0xc2, 0x0d, 0xba, 0x4f, 0x79, 0x88, 0xd1, 0x15, - 0x64, 0x55, 0x90, 0x7b, 0x76, 0x2d, 0x60, 0x04, 0x92, 0x77, 0x18, 0xd0, 0xba, 0x7f, 0xee, 0x3a, - }, - { - 0x57, 0xc1, 0x0b, 0x23, 0x06, 0x57, 0x0c, 0xde, 0xa1, 0xa5, 0x8d, 0xc6, 0x8e, 0xbd, 0x9e, 0x09, - 0xe5, 0xed, 0xe3, 0xfb, 0xb1, 0xa0, 0xda, 0x73, 0xfc, 0x3e, 0x5e, 0x6d, 0x38, 0x36, 0x26, 0xec, - }, - { - 0x8e, 0xe5, 0x30, 0x36, 0x9e, 0x30, 0x82, 0x02, 0xf6, 0x7c, 0x06, 0x71, 0xbb, 0x6e, 0x09, 0x68, - 0x16, 0xca, 0x10, 0x32, 0x90, 0xcc, 0x7a, 0x99, 0x18, 0x70, 0xe6, 0xe7, 0x3a, 0x78, 0x86, 0xe6, - }, - { - 0x18, 0x98, 0x14, 0xa7, 0xb7, 0x1f, 0x24, 0xed, 0xd0, 0xfc, 0x71, 0xa0, 0x7e, 0xef, 0xdd, 0xe2, - 0xa2, 0xf8, 0x2a, 0xc2, 0x5d, 0x94, 0x03, 0x13, 0x29, 0x39, 0x86, 0xed, 0x08, 0x99, 0x83, 0xab, - }, - { - 0xcd, 0x22, 0xa0, 0xbc, 0xea, 0xe7, 0xde, 0xca, 0x0c, 0x72, 0xbd, 0xf7, 0x40, 0x46, 0x92, 0xc5, - 0xa4, 0xf3, 0x48, 0x9a, 0x8f, 0x52, 0xab, 0x19, 0x07, 0x98, 0xae, 0x9b, 0xe7, 0xfc, 0xbd, 0x05, - }, - { - 0xd2, 0xce, 0x28, 0x79, 0x3f, 0xdd, 0xa1, 0x1c, 0x21, 0xe4, 0xeb, 0x54, 0x85, 0x5c, 0x9d, 0x64, - 0xd5, 0x5b, 0xb6, 0x06, 0x43, 0xcc, 0x80, 0x8b, 0xe3, 0xdb, 0x26, 0xf5, 0x7e, 0x5f, 0x81, 0x9d, - }, - { - 0x54, 0x42, 0xe9, 0x30, 0xd2, 0x2c, 0xba, 0x16, 0xa7, 0x99, 0x28, 0xe7, 0x54, 0x61, 0xee, 0x17, - 0xf0, 0x70, 0x34, 0xe2, 0xe7, 0x66, 0x16, 0x00, 0x95, 0x7b, 0xbd, 0xd8, 0x07, 0xab, 0xa9, 0x5b, - }, - { - 0xe7, 0x58, 0x21, 0x24, 0x0e, 0x32, 0xbd, 0x6b, 0xcb, 0xa6, 0xd9, 0x91, 0xd7, 0xfd, 0xe4, 0x4c, - 0x58, 0xd6, 0x06, 0x11, 0x02, 0x90, 0xe5, 0x1d, 0x91, 0x2f, 0x0f, 0x43, 0xe3, 0xc7, 0x66, 0xd8, - }, - { - 0x45, 0x65, 0x5e, 0x17, 0xe1, 0x00, 0xfd, 0x42, 0x30, 0x25, 0x0e, 0xa5, 0x26, 0x8a, 0x17, 0xfe, - 0xd0, 0xa2, 0xff, 0x7a, 0x09, 0xd3, 0x5a, 0xb4, 0x71, 0x84, 0x29, 0x03, 0x71, 0x70, 0x9b, 0x6e, - }, - { - 0xc7, 0x2d, 0xe6, 0xef, 0xba, 0x0b, 0x97, 0x9a, 0x91, 0xf2, 0xda, 0x26, 0x62, 0xe5, 0xbe, 0x5d, - 0xc5, 0x5d, 0x71, 0xc1, 0xb7, 0x3f, 0xb3, 0xb8, 0x74, 0xd0, 0x0c, 0x03, 0x74, 0xc0, 0x0c, 0xe4, - }, - { - 0x56, 0x38, 0x1e, 0x31, 0xca, 0x3b, 0xb5, 0xc4, 0xff, 0x5a, 0x9e, 0x86, 0xfe, 0x98, 0x0c, 0x27, - 0x23, 0x2c, 0xa0, 0x76, 0x6f, 0xae, 0xf3, 0xde, 0x71, 0x40, 0x0c, 0xdc, 0x41, 0xf9, 0x89, 0x99, - }, - { - 0x2c, 0x27, 0xed, 0x69, 0x50, 0x53, 0xc5, 0x97, 0xf4, 0x88, 0x9a, 0x2b, 0xce, 0x8a, 0xc5, 0xfb, - 0x0d, 0xbc, 0x6f, 0x9c, 0x84, 0x30, 0xf3, 0xcb, 0xc1, 0x30, 0xa4, 0xb5, 0x46, 0xd4, 0xcb, 0xea, - }, - { - 0xb7, 0xf0, 0x86, 0x66, 0xd3, 0x55, 0x64, 0xc9, 0x1b, 0x9b, 0x3d, 0x79, 0x13, 0x0a, 0x3e, 0xa1, - 0xcf, 0x54, 0x17, 0x77, 0xeb, 0x32, 0x1c, 0x47, 0x7d, 0xf0, 0xb4, 0x11, 0x3d, 0xd7, 0xef, 0x04, - }, - { - 0xf7, 0x7e, 0x71, 0xb6, 0x5e, 0xed, 0xf3, 0xfb, 0x56, 0x82, 0x22, 0x61, 0x29, 0xa2, 0x5d, 0xc6, - 0xcd, 0x03, 0x47, 0xc7, 0xcc, 0xe4, 0xf2, 0xa4, 0x3f, 0xed, 0x36, 0xae, 0xa7, 0x30, 0x84, 0x22, - }, - { - 0x13, 0x70, 0xe7, 0x97, 0x14, 0xfa, 0xa9, 0xb7, 0xd5, 0xa1, 0xa4, 0xfd, 0xe8, 0x0c, 0x92, 0xcf, - 0xc4, 0xdc, 0x5d, 0xb9, 0xa4, 0xa2, 0x16, 0xf8, 0x67, 0xdc, 0x12, 0x47, 0xb7, 0x75, 0xfd, 0x3c, - }, - { - 0x29, 0xaa, 0xdd, 0xb5, 0xdc, 0x7f, 0xce, 0xad, 0x02, 0x65, 0x27, 0x5e, 0xa5, 0x5d, 0x23, 0x0f, - 0xa7, 0x51, 0x4d, 0xf2, 0x7d, 0x2a, 0x31, 0xbf, 0x32, 0x3b, 0x80, 0xe3, 0xda, 0x56, 0xdb, 0xfc, - }, - { - 0x70, 0xd0, 0x50, 0x6d, 0xf2, 0xb3, 0x6f, 0xc1, 0x9a, 0x98, 0x02, 0x87, 0xb5, 0x31, 0x3d, 0x19, - 0xaa, 0xf4, 0xd2, 0xd4, 0x48, 0xb1, 0x08, 0x06, 0x98, 0x39, 0x00, 0x06, 0x20, 0xe5, 0x0c, 0xe1, - }, - { - 0xe6, 0xaf, 0x94, 0xa0, 0xdf, 0xc3, 0x6b, 0xb4, 0xcf, 0x78, 0xc0, 0xe8, 0x56, 0xdc, 0xac, 0xbb, - 0x5e, 0x9e, 0xda, 0x90, 0x1e, 0x7f, 0x44, 0x06, 0xe0, 0x00, 0x6a, 0xd9, 0xd1, 0xf9, 0x56, 0xac, - }, - { - 0x15, 0xa2, 0x90, 0x13, 0x4f, 0xa0, 0x9d, 0x0d, 0x9c, 0xf8, 0xc9, 0x20, 0x1c, 0x8e, 0x68, 0xcb, - 0x1f, 0x75, 0xb3, 0xb2, 0x14, 0xff, 0x19, 0x20, 0x5f, 0x30, 0xb1, 0x05, 0x36, 0x7c, 0xa2, 0xed, - }, - { - 0x9a, 0xb2, 0xf5, 0xfd, 0x04, 0x3e, 0x6b, 0x4a, 0x1d, 0x3a, 0x63, 0x96, 0x00, 0xad, 0x6c, 0x7c, - 0x4f, 0xaf, 0x4d, 0xb5, 0x03, 0x4a, 0xf7, 0x28, 0x7f, 0x1f, 0x38, 0xad, 0xfd, 0xc7, 0x4b, 0x7f, - }, - { - 0xf4, 0x5a, 0x9f, 0xf6, 0xd0, 0x1a, 0x23, 0x76, 0xee, 0x15, 0x10, 0x2c, 0x30, 0xbd, 0x45, 0xfc, - 0x65, 0x60, 0x20, 0xc5, 0x9b, 0xb4, 0x42, 0x83, 0xe9, 0x03, 0xd5, 0xec, 0xba, 0xb2, 0x3b, 0xb8, - }, - { - 0xf4, 0x1b, 0xc1, 0x73, 0x1a, 0x6c, 0x88, 0xfd, 0xc2, 0xfb, 0xe8, 0x7e, 0xcb, 0x8a, 0x0e, 0x0e, - 0x6a, 0x13, 0x54, 0xb0, 0x7b, 0xb8, 0x68, 0x90, 0x21, 0x38, 0x4e, 0x1f, 0x86, 0x51, 0x14, 0x2c, - }, - { - 0x6c, 0xd3, 0xc3, 0x8f, 0x06, 0x45, 0xec, 0x65, 0x87, 0x02, 0x3d, 0x89, 0x61, 0xde, 0x80, 0x42, - 0xf6, 0xe0, 0x8d, 0x91, 0xf0, 0x3a, 0x7a, 0x66, 0xba, 0x1c, 0xc7, 0xb6, 0x3d, 0xc4, 0x7f, 0x91, - }, - { - 0x53, 0xf6, 0x90, 0x34, 0x88, 0x3e, 0xb7, 0xef, 0x56, 0x39, 0x6e, 0x1f, 0x48, 0x14, 0xe4, 0x09, - 0xc6, 0xea, 0xc4, 0xd9, 0xed, 0x2e, 0x2e, 0x33, 0x03, 0x00, 0xb9, 0xac, 0x22, 0x65, 0xe9, 0x1b, - }, - { - 0x55, 0x78, 0x89, 0x36, 0xa0, 0x07, 0xa6, 0x99, 0xbf, 0x7c, 0xb5, 0xbd, 0xb6, 0x1e, 0xc3, 0x58, - 0xb3, 0x0f, 0x78, 0x64, 0x74, 0x77, 0x00, 0x50, 0x2e, 0x4c, 0x6a, 0xa1, 0xe8, 0x93, 0x89, 0x5d, - }, - { - 0x09, 0xf8, 0xdd, 0xe0, 0x42, 0xa4, 0x2e, 0x9d, 0xff, 0x0e, 0x70, 0x73, 0x9c, 0x87, 0xa0, 0x81, - 0x4d, 0xb1, 0xc3, 0xf3, 0xff, 0x96, 0x3b, 0x2a, 0xdf, 0x6d, 0x97, 0xba, 0x06, 0xa7, 0x7e, 0x0a, - }, - { - 0x1f, 0x46, 0xb4, 0x72, 0x14, 0x5b, 0x85, 0x01, 0x83, 0xcc, 0x24, 0x17, 0xc2, 0x07, 0xda, 0x60, - 0x6c, 0xab, 0xfa, 0xe5, 0xd9, 0xb4, 0xf0, 0x3f, 0xca, 0xf1, 0x30, 0x8d, 0xd2, 0x4e, 0xe3, 0xb4, - }, - { - 0x4f, 0xb3, 0x0d, 0x98, 0x38, 0x70, 0x28, 0xa2, 0xca, 0x5d, 0x2c, 0xdf, 0x1f, 0xce, 0xff, 0xcc, - 0x75, 0x49, 0xa0, 0xef, 0x54, 0xd9, 0x32, 0x1b, 0x17, 0xb6, 0x7e, 0x7a, 0xa6, 0x5f, 0x7a, 0xff, - }, - { - 0x81, 0x6b, 0x06, 0x73, 0x5b, 0x32, 0x0d, 0x37, 0xb4, 0x50, 0x63, 0x52, 0x25, 0x72, 0x5c, 0xf5, - 0x5d, 0x58, 0xa6, 0xbf, 0x08, 0xcc, 0x1d, 0x70, 0x2d, 0x12, 0x5d, 0xd7, 0xbd, 0xca, 0xe7, 0x10, - }, - { - 0x8f, 0xfc, 0x57, 0x17, 0xce, 0x47, 0x10, 0x79, 0xae, 0x66, 0xa5, 0xcc, 0x98, 0x0b, 0x77, 0xe8, - 0xa2, 0x6e, 0xc1, 0x0d, 0x03, 0xe3, 0x5b, 0xed, 0x38, 0x0e, 0x31, 0x2d, 0x19, 0x4d, 0xd6, 0x2a, - }, - { - 0xc6, 0x9d, 0x2d, 0x0b, 0xad, 0x6d, 0x0c, 0x61, 0x2d, 0x62, 0xe4, 0xce, 0x73, 0x47, 0x72, 0x20, - 0x0c, 0x8e, 0x8f, 0xe9, 0xe7, 0x67, 0x66, 0x2e, 0x17, 0x54, 0xec, 0x15, 0x3e, 0x1b, 0xf3, 0x04, - }, - { - 0xf4, 0xee, 0x03, 0x30, 0x2e, 0x1e, 0xa4, 0xb1, 0x86, 0x6d, 0xc3, 0x54, 0xf3, 0xc5, 0x61, 0xa6, - 0xb9, 0x28, 0x29, 0x11, 0x91, 0xcb, 0xbd, 0xc9, 0x77, 0x62, 0x09, 0x8c, 0xa4, 0x40, 0x84, 0x97, - }, - { - 0xff, 0x98, 0x9b, 0xbc, 0xc2, 0xf0, 0xf8, 0x7f, 0x5c, 0x86, 0x74, 0x33, 0xee, 0x42, 0x6e, 0xab, - 0xd4, 0xd2, 0x1a, 0x0d, 0x41, 0x2d, 0xac, 0xa1, 0x3e, 0x56, 0xed, 0x4b, 0x27, 0x5a, 0x65, 0xe4, - }, - { - 0x2b, 0xb1, 0xe3, 0x64, 0xaa, 0x32, 0x17, 0x57, 0x7c, 0x67, 0xb8, 0x6b, 0x00, 0x53, 0xbe, 0x3e, - 0xec, 0xd1, 0x1b, 0xc4, 0xc3, 0x8d, 0xe6, 0x19, 0xe8, 0x3a, 0x25, 0x98, 0x4e, 0xe9, 0xd4, 0x60, - }, - { - 0xa6, 0x2e, 0xb3, 0xc8, 0xcd, 0xc9, 0xc2, 0x8e, 0xe1, 0xf0, 0x8f, 0x96, 0x8e, 0xc6, 0x37, 0x11, - 0xbc, 0x6c, 0x0c, 0xf6, 0xb6, 0x83, 0x38, 0x96, 0x7a, 0x74, 0x5a, 0xa7, 0xe1, 0x11, 0x8d, 0x8b, - }, - { - 0x90, 0xf2, 0x4d, 0xbd, 0x83, 0x39, 0xe6, 0x54, 0xf6, 0x75, 0xf6, 0x2c, 0x28, 0x3d, 0xd1, 0xcf, - 0xe1, 0xfb, 0x9f, 0x97, 0x19, 0xca, 0x4d, 0x2c, 0x38, 0x3d, 0x36, 0xed, 0x19, 0xe9, 0x4a, 0x0b, - }, - { - 0x1a, 0x61, 0xb8, 0x19, 0x59, 0x16, 0x74, 0xec, 0xdb, 0x7b, 0xeb, 0xd6, 0xae, 0xcd, 0xe9, 0x55, - 0xdb, 0x45, 0xdc, 0xf2, 0x35, 0x84, 0xe9, 0xe6, 0x17, 0x48, 0xac, 0x38, 0x05, 0x21, 0x2c, 0x8e, - }, - { - 0x41, 0xac, 0x17, 0x42, 0xcc, 0x17, 0x10, 0x02, 0x07, 0x7e, 0xfc, 0x4d, 0x77, 0x06, 0x70, 0xcb, - 0x40, 0x8b, 0x47, 0x47, 0x07, 0x29, 0x82, 0xca, 0x93, 0x69, 0x2f, 0x3a, 0x64, 0xc6, 0xcb, 0x23, - }, - { - 0xa2, 0xcb, 0x2d, 0x02, 0x5d, 0x30, 0x9f, 0x32, 0xf5, 0xc5, 0x13, 0xff, 0xfc, 0xe2, 0xfb, 0x26, - 0x3b, 0x3b, 0xaf, 0xa4, 0x37, 0x6d, 0x45, 0xbf, 0xdb, 0xb9, 0xee, 0xec, 0x92, 0xa5, 0x1d, 0x0d, - }, - { - 0xa4, 0xef, 0x08, 0xb7, 0xb4, 0x68, 0x74, 0x93, 0xb2, 0xda, 0xba, 0xe9, 0x05, 0xf5, 0x09, 0xb6, - 0x53, 0xdd, 0x17, 0x60, 0xbb, 0x1e, 0xb0, 0x71, 0xd8, 0x47, 0x85, 0x02, 0x13, 0xbe, 0xa2, 0x67, - }, - { - 0x31, 0x50, 0x90, 0xb0, 0x83, 0x4a, 0xcf, 0x3f, 0xbe, 0x88, 0x90, 0x4b, 0xe1, 0x9f, 0xe6, 0xd0, - 0xfd, 0x01, 0x8e, 0xfc, 0xc0, 0x8c, 0x2f, 0x9b, 0x48, 0x70, 0x9d, 0x4e, 0x22, 0x21, 0x07, 0x09, - }, - { - 0x15, 0x9f, 0x37, 0x45, 0x52, 0x99, 0x6e, 0xe9, 0x1a, 0x25, 0x56, 0x0b, 0x19, 0xf1, 0xca, 0x9f, - 0x29, 0xe5, 0x23, 0xa6, 0x0b, 0x94, 0x0a, 0xe3, 0x74, 0xaa, 0xd5, 0x35, 0xaf, 0x6e, 0xb2, 0x24, - }, - { - 0x68, 0xab, 0xa6, 0x8b, 0x5f, 0xc7, 0x93, 0x1a, 0x06, 0x51, 0x2c, 0x3b, 0xad, 0x44, 0x6b, 0x69, - 0x1a, 0x1d, 0x41, 0xca, 0x8e, 0x59, 0x2c, 0x83, 0x71, 0x48, 0x8c, 0xaf, 0x50, 0x85, 0x00, 0xf3, - }, - { - 0xe2, 0xa6, 0x38, 0x93, 0xca, 0xe3, 0xd0, 0x36, 0xf4, 0xe9, 0x53, 0xfb, 0xa0, 0xd0, 0x13, 0xd3, - 0x2b, 0x7d, 0x46, 0xc8, 0x8b, 0xc7, 0x8c, 0xca, 0x59, 0xec, 0x66, 0x17, 0x70, 0xbb, 0xf9, 0x92, - }, - { - 0x89, 0xca, 0x92, 0x19, 0x01, 0xb8, 0x4b, 0x97, 0x06, 0x1a, 0x12, 0x91, 0x72, 0x11, 0xeb, 0x12, - 0x8b, 0x12, 0xd9, 0xdc, 0xc9, 0xb2, 0x37, 0xf8, 0x3e, 0x02, 0x03, 0xbe, 0x45, 0x45, 0xc9, 0x42, - }, - { - 0x45, 0x2c, 0x80, 0xe1, 0x3a, 0x0a, 0xdf, 0xa3, 0xd2, 0x4a, 0x23, 0x0d, 0x47, 0x0d, 0x49, 0xad, - 0xdf, 0xb0, 0x42, 0xdf, 0x87, 0x85, 0xa6, 0x8f, 0x9f, 0x7e, 0x9b, 0xa4, 0x42, 0x64, 0xcb, 0xfb, - }, - { - 0xc7, 0x39, 0x26, 0xb1, 0x90, 0x4d, 0xc1, 0x7a, 0xea, 0x31, 0x1b, 0xae, 0x1a, 0x5c, 0x1f, 0x4f, - 0x44, 0x2f, 0x87, 0x08, 0x5d, 0xa6, 0x74, 0xfd, 0xab, 0xb2, 0x4b, 0x01, 0xed, 0xd5, 0x4c, 0xe6, - }, - { - 0x2a, 0xef, 0xfa, 0x25, 0x3c, 0xd2, 0xc8, 0x08, 0x9c, 0x33, 0x3c, 0x47, 0xb3, 0xb5, 0x44, 0x34, - 0x97, 0xee, 0xe8, 0x52, 0x1c, 0x15, 0xb3, 0xe0, 0xda, 0xef, 0x77, 0xde, 0x15, 0x39, 0x4b, 0x38, - }, - { - 0x8a, 0x3a, 0x59, 0x61, 0x9d, 0x3e, 0x9b, 0x38, 0xc9, 0x84, 0x80, 0xaf, 0xb4, 0x37, 0x8a, 0x67, - 0x47, 0xc9, 0x6c, 0x72, 0xef, 0x39, 0x50, 0x28, 0x6c, 0x8f, 0xad, 0x09, 0x75, 0x26, 0xc9, 0xa9, - }, - { - 0x27, 0x1e, 0x8b, 0xf6, 0x6b, 0x56, 0x5d, 0x17, 0x58, 0xac, 0xdf, 0x27, 0xd9, 0x3e, 0x5b, 0xdd, - 0xaf, 0xbc, 0xb7, 0xf9, 0x76, 0x3b, 0x40, 0x06, 0xbc, 0x6e, 0xec, 0xaa, 0xb2, 0xdc, 0x9a, 0x0c, - }, - { - 0x09, 0x14, 0xef, 0x19, 0xc7, 0x7d, 0xc8, 0xa3, 0xd0, 0xaa, 0x7f, 0x09, 0x18, 0xaf, 0xd3, 0xde, - 0xbf, 0x05, 0xfc, 0xf9, 0xeb, 0xc0, 0x8e, 0xcf, 0xc7, 0x4c, 0x2f, 0x3f, 0xd4, 0x51, 0x41, 0xb2, - }, - { - 0xb7, 0x33, 0xf3, 0x72, 0x6d, 0x12, 0xc1, 0x5c, 0x5d, 0x81, 0xb3, 0x63, 0x81, 0x50, 0x81, 0xc0, - 0x4a, 0xea, 0x18, 0x7c, 0xa6, 0x2d, 0x23, 0xba, 0x4b, 0xb9, 0x31, 0xd9, 0xab, 0x20, 0x60, 0x77, - }, - { - 0xbb, 0x1c, 0x50, 0x2d, 0xdc, 0x18, 0x27, 0x98, 0x60, 0xde, 0x17, 0xd9, 0x17, 0x3c, 0xd5, 0x98, - 0xc3, 0x12, 0xfd, 0x8b, 0x25, 0x1e, 0xa5, 0xc1, 0xa8, 0xef, 0xec, 0x05, 0x3e, 0xfc, 0xd1, 0xfc, - }, - { - 0xe6, 0x3b, 0x9f, 0x33, 0x85, 0xeb, 0x91, 0xd0, 0xad, 0x2f, 0xc2, 0x96, 0x61, 0x64, 0xbc, 0x12, - 0x15, 0x79, 0x65, 0x93, 0xc2, 0x63, 0xa3, 0x27, 0x88, 0x60, 0x39, 0x35, 0x21, 0x05, 0xe9, 0x49, - }, - { - 0x9b, 0x68, 0xe7, 0xc8, 0xea, 0x0e, 0x5c, 0xa4, 0x03, 0x3a, 0x4e, 0x31, 0xb1, 0x92, 0xad, 0x9d, - 0x7e, 0xb5, 0x93, 0x81, 0xdd, 0x7a, 0xe9, 0xa1, 0x69, 0x28, 0x6a, 0xaf, 0x48, 0x05, 0x94, 0xc0, - }, - { - 0x66, 0x3d, 0x87, 0xc1, 0x48, 0x9d, 0xdf, 0x99, 0x25, 0xd7, 0xb0, 0xfa, 0x03, 0x8b, 0x62, 0x60, - 0xc5, 0x07, 0x3f, 0xa2, 0xc8, 0xbd, 0x70, 0xdb, 0x40, 0x6c, 0x65, 0xbf, 0x15, 0xfc, 0x1e, 0xc9, - }, - { - 0x38, 0x9c, 0x1a, 0x5b, 0x4f, 0x84, 0xca, 0xe1, 0x30, 0x6a, 0xf0, 0xb6, 0xf1, 0x61, 0xd3, 0xb0, - 0xa6, 0x6d, 0x0d, 0x11, 0x03, 0xe0, 0xcb, 0x9f, 0xbe, 0x7e, 0xc2, 0x7a, 0x53, 0x9d, 0x39, 0xcb, - }, - { - 0xf3, 0x47, 0x4a, 0x37, 0xcd, 0x19, 0x27, 0x0f, 0xfb, 0x3f, 0xcb, 0x81, 0x1e, 0x0f, 0xfd, 0x1f, - 0x2e, 0x8d, 0xff, 0xe9, 0x52, 0x8b, 0x8e, 0x52, 0x3c, 0x82, 0xe6, 0x44, 0xf6, 0x92, 0xd4, 0xd4, - }, - { - 0x3a, 0xe8, 0x4d, 0xcc, 0x4a, 0x0e, 0xaa, 0xf6, 0x32, 0x88, 0x4c, 0xee, 0xaa, 0x9c, 0xeb, 0x59, - 0xb5, 0xb8, 0x06, 0x89, 0x49, 0xc9, 0xa6, 0xf7, 0xa6, 0x14, 0x44, 0x55, 0x5e, 0x3e, 0x86, 0x08, - }, - { - 0xca, 0x3d, 0x95, 0x21, 0xf3, 0xbb, 0x78, 0x29, 0x6a, 0x38, 0xd3, 0xe4, 0x48, 0x98, 0x6f, 0x0e, - 0xaf, 0x46, 0xa5, 0x02, 0xdd, 0xfb, 0x52, 0x42, 0x9b, 0x69, 0x97, 0xe6, 0x68, 0x21, 0x0d, 0x69, - }, - { - 0x3a, 0x8a, 0x14, 0x6e, 0xa2, 0x24, 0x8f, 0x89, 0x5e, 0x99, 0x8a, 0x5b, 0x90, 0xb1, 0xf3, 0x64, - 0x4d, 0x10, 0xef, 0x45, 0xa9, 0xfb, 0xbb, 0xc0, 0xf5, 0x66, 0xdf, 0x15, 0xae, 0xd0, 0xd9, 0x56, - }, - { - 0x62, 0x50, 0x52, 0xb5, 0xb9, 0x76, 0xa7, 0xcb, 0xe6, 0xf7, 0x3a, 0x9f, 0xa4, 0x1e, 0x0a, 0x4d, - 0x88, 0xa4, 0x1c, 0xea, 0x11, 0x8c, 0xfb, 0xbe, 0x70, 0x62, 0xec, 0x4e, 0x00, 0x56, 0x0e, 0xa9, - }, + +const u8 invert[63][32] = { + {0x95, 0xb2, 0xa8, 0xe3, 0xac, 0xcf, 0x27, 0x3e, + 0x1c, 0xa3, 0xcf, 0x7a, 0x20, 0xb4, 0x52, 0x83, + 0x0e, 0x21, 0x2d, 0xfe, 0x6f, 0x2e, 0x38, 0x13, + 0x01, 0x2e, 0xa0, 0x58, 0x58, 0x6d, 0x4a, 0x6f}, + {0x63, 0x26, 0x5c, 0xd2, 0x9a, 0xc6, 0x8c, 0x5d, + 0xc2, 0x0d, 0xba, 0x4f, 0x79, 0x88, 0xd1, 0x15, + 0x64, 0x55, 0x90, 0x7b, 0x76, 0x2d, 0x60, 0x04, + 0x92, 0x77, 0x18, 0xd0, 0xba, 0x7f, 0xee, 0x3a}, + {0x57, 0xc1, 0x0b, 0x23, 0x06, 0x57, 0x0c, 0xde, + 0xa1, 0xa5, 0x8d, 0xc6, 0x8e, 0xbd, 0x9e, 0x09, + 0xe5, 0xed, 0xe3, 0xfb, 0xb1, 0xa0, 0xda, 0x73, + 0xfc, 0x3e, 0x5e, 0x6d, 0x38, 0x36, 0x26, 0xec}, + {0x8e, 0xe5, 0x30, 0x36, 0x9e, 0x30, 0x82, 0x02, + 0xf6, 0x7c, 0x06, 0x71, 0xbb, 0x6e, 0x09, 0x68, + 0x16, 0xca, 0x10, 0x32, 0x90, 0xcc, 0x7a, 0x99, + 0x18, 0x70, 0xe6, 0xe7, 0x3a, 0x78, 0x86, 0xe6}, + {0x18, 0x98, 0x14, 0xa7, 0xb7, 0x1f, 0x24, 0xed, + 0xd0, 0xfc, 0x71, 0xa0, 0x7e, 0xef, 0xdd, 0xe2, + 0xa2, 0xf8, 0x2a, 0xc2, 0x5d, 0x94, 0x03, 0x13, + 0x29, 0x39, 0x86, 0xed, 0x08, 0x99, 0x83, 0xab}, + {0xcd, 0x22, 0xa0, 0xbc, 0xea, 0xe7, 0xde, 0xca, + 0x0c, 0x72, 0xbd, 0xf7, 0x40, 0x46, 0x92, 0xc5, + 0xa4, 0xf3, 0x48, 0x9a, 0x8f, 0x52, 0xab, 0x19, + 0x07, 0x98, 0xae, 0x9b, 0xe7, 0xfc, 0xbd, 0x05}, + {0xd2, 0xce, 0x28, 0x79, 0x3f, 0xdd, 0xa1, 0x1c, + 0x21, 0xe4, 0xeb, 0x54, 0x85, 0x5c, 0x9d, 0x64, + 0xd5, 0x5b, 0xb6, 0x06, 0x43, 0xcc, 0x80, 0x8b, + 0xe3, 0xdb, 0x26, 0xf5, 0x7e, 0x5f, 0x81, 0x9d}, + {0x54, 0x42, 0xe9, 0x30, 0xd2, 0x2c, 0xba, 0x16, + 0xa7, 0x99, 0x28, 0xe7, 0x54, 0x61, 0xee, 0x17, + 0xf0, 0x70, 0x34, 0xe2, 0xe7, 0x66, 0x16, 0x00, + 0x95, 0x7b, 0xbd, 0xd8, 0x07, 0xab, 0xa9, 0x5b}, + {0xe7, 0x58, 0x21, 0x24, 0x0e, 0x32, 0xbd, 0x6b, + 0xcb, 0xa6, 0xd9, 0x91, 0xd7, 0xfd, 0xe4, 0x4c, + 0x58, 0xd6, 0x06, 0x11, 0x02, 0x90, 0xe5, 0x1d, + 0x91, 0x2f, 0x0f, 0x43, 0xe3, 0xc7, 0x66, 0xd8}, + {0x45, 0x65, 0x5e, 0x17, 0xe1, 0x00, 0xfd, 0x42, + 0x30, 0x25, 0x0e, 0xa5, 0x26, 0x8a, 0x17, 0xfe, + 0xd0, 0xa2, 0xff, 0x7a, 0x09, 0xd3, 0x5a, 0xb4, + 0x71, 0x84, 0x29, 0x03, 0x71, 0x70, 0x9b, 0x6e}, + {0xc7, 0x2d, 0xe6, 0xef, 0xba, 0x0b, 0x97, 0x9a, + 0x91, 0xf2, 0xda, 0x26, 0x62, 0xe5, 0xbe, 0x5d, + 0xc5, 0x5d, 0x71, 0xc1, 0xb7, 0x3f, 0xb3, 0xb8, + 0x74, 0xd0, 0x0c, 0x03, 0x74, 0xc0, 0x0c, 0xe4}, + {0x56, 0x38, 0x1e, 0x31, 0xca, 0x3b, 0xb5, 0xc4, + 0xff, 0x5a, 0x9e, 0x86, 0xfe, 0x98, 0x0c, 0x27, + 0x23, 0x2c, 0xa0, 0x76, 0x6f, 0xae, 0xf3, 0xde, + 0x71, 0x40, 0x0c, 0xdc, 0x41, 0xf9, 0x89, 0x99}, + {0x2c, 0x27, 0xed, 0x69, 0x50, 0x53, 0xc5, 0x97, + 0xf4, 0x88, 0x9a, 0x2b, 0xce, 0x8a, 0xc5, 0xfb, + 0x0d, 0xbc, 0x6f, 0x9c, 0x84, 0x30, 0xf3, 0xcb, + 0xc1, 0x30, 0xa4, 0xb5, 0x46, 0xd4, 0xcb, 0xea}, + {0xb7, 0xf0, 0x86, 0x66, 0xd3, 0x55, 0x64, 0xc9, + 0x1b, 0x9b, 0x3d, 0x79, 0x13, 0x0a, 0x3e, 0xa1, + 0xcf, 0x54, 0x17, 0x77, 0xeb, 0x32, 0x1c, 0x47, + 0x7d, 0xf0, 0xb4, 0x11, 0x3d, 0xd7, 0xef, 0x04}, + {0xf7, 0x7e, 0x71, 0xb6, 0x5e, 0xed, 0xf3, 0xfb, + 0x56, 0x82, 0x22, 0x61, 0x29, 0xa2, 0x5d, 0xc6, + 0xcd, 0x03, 0x47, 0xc7, 0xcc, 0xe4, 0xf2, 0xa4, + 0x3f, 0xed, 0x36, 0xae, 0xa7, 0x30, 0x84, 0x22}, + {0x13, 0x70, 0xe7, 0x97, 0x14, 0xfa, 0xa9, 0xb7, + 0xd5, 0xa1, 0xa4, 0xfd, 0xe8, 0x0c, 0x92, 0xcf, + 0xc4, 0xdc, 0x5d, 0xb9, 0xa4, 0xa2, 0x16, 0xf8, + 0x67, 0xdc, 0x12, 0x47, 0xb7, 0x75, 0xfd, 0x3c}, + {0x29, 0xaa, 0xdd, 0xb5, 0xdc, 0x7f, 0xce, 0xad, + 0x02, 0x65, 0x27, 0x5e, 0xa5, 0x5d, 0x23, 0x0f, + 0xa7, 0x51, 0x4d, 0xf2, 0x7d, 0x2a, 0x31, 0xbf, + 0x32, 0x3b, 0x80, 0xe3, 0xda, 0x56, 0xdb, 0xfc}, + {0x70, 0xd0, 0x50, 0x6d, 0xf2, 0xb3, 0x6f, 0xc1, + 0x9a, 0x98, 0x02, 0x87, 0xb5, 0x31, 0x3d, 0x19, + 0xaa, 0xf4, 0xd2, 0xd4, 0x48, 0xb1, 0x08, 0x06, + 0x98, 0x39, 0x00, 0x06, 0x20, 0xe5, 0x0c, 0xe1}, + {0xe6, 0xaf, 0x94, 0xa0, 0xdf, 0xc3, 0x6b, 0xb4, + 0xcf, 0x78, 0xc0, 0xe8, 0x56, 0xdc, 0xac, 0xbb, + 0x5e, 0x9e, 0xda, 0x90, 0x1e, 0x7f, 0x44, 0x06, + 0xe0, 0x00, 0x6a, 0xd9, 0xd1, 0xf9, 0x56, 0xac}, + {0x15, 0xa2, 0x90, 0x13, 0x4f, 0xa0, 0x9d, 0x0d, + 0x9c, 0xf8, 0xc9, 0x20, 0x1c, 0x8e, 0x68, 0xcb, + 0x1f, 0x75, 0xb3, 0xb2, 0x14, 0xff, 0x19, 0x20, + 0x5f, 0x30, 0xb1, 0x05, 0x36, 0x7c, 0xa2, 0xed}, + {0x9a, 0xb2, 0xf5, 0xfd, 0x04, 0x3e, 0x6b, 0x4a, + 0x1d, 0x3a, 0x63, 0x96, 0x00, 0xad, 0x6c, 0x7c, + 0x4f, 0xaf, 0x4d, 0xb5, 0x03, 0x4a, 0xf7, 0x28, + 0x7f, 0x1f, 0x38, 0xad, 0xfd, 0xc7, 0x4b, 0x7f}, + {0xf4, 0x5a, 0x9f, 0xf6, 0xd0, 0x1a, 0x23, 0x76, + 0xee, 0x15, 0x10, 0x2c, 0x30, 0xbd, 0x45, 0xfc, + 0x65, 0x60, 0x20, 0xc5, 0x9b, 0xb4, 0x42, 0x83, + 0xe9, 0x03, 0xd5, 0xec, 0xba, 0xb2, 0x3b, 0xb8}, + {0xf4, 0x1b, 0xc1, 0x73, 0x1a, 0x6c, 0x88, 0xfd, + 0xc2, 0xfb, 0xe8, 0x7e, 0xcb, 0x8a, 0x0e, 0x0e, + 0x6a, 0x13, 0x54, 0xb0, 0x7b, 0xb8, 0x68, 0x90, + 0x21, 0x38, 0x4e, 0x1f, 0x86, 0x51, 0x14, 0x2c}, + {0x6c, 0xd3, 0xc3, 0x8f, 0x06, 0x45, 0xec, 0x65, + 0x87, 0x02, 0x3d, 0x89, 0x61, 0xde, 0x80, 0x42, + 0xf6, 0xe0, 0x8d, 0x91, 0xf0, 0x3a, 0x7a, 0x66, + 0xba, 0x1c, 0xc7, 0xb6, 0x3d, 0xc4, 0x7f, 0x91}, + {0x53, 0xf6, 0x90, 0x34, 0x88, 0x3e, 0xb7, 0xef, + 0x56, 0x39, 0x6e, 0x1f, 0x48, 0x14, 0xe4, 0x09, + 0xc6, 0xea, 0xc4, 0xd9, 0xed, 0x2e, 0x2e, 0x33, + 0x03, 0x00, 0xb9, 0xac, 0x22, 0x65, 0xe9, 0x1b}, + {0x55, 0x78, 0x89, 0x36, 0xa0, 0x07, 0xa6, 0x99, + 0xbf, 0x7c, 0xb5, 0xbd, 0xb6, 0x1e, 0xc3, 0x58, + 0xb3, 0x0f, 0x78, 0x64, 0x74, 0x77, 0x00, 0x50, + 0x2e, 0x4c, 0x6a, 0xa1, 0xe8, 0x93, 0x89, 0x5d}, + {0x09, 0xf8, 0xdd, 0xe0, 0x42, 0xa4, 0x2e, 0x9d, + 0xff, 0x0e, 0x70, 0x73, 0x9c, 0x87, 0xa0, 0x81, + 0x4d, 0xb1, 0xc3, 0xf3, 0xff, 0x96, 0x3b, 0x2a, + 0xdf, 0x6d, 0x97, 0xba, 0x06, 0xa7, 0x7e, 0x0a}, + {0x1f, 0x46, 0xb4, 0x72, 0x14, 0x5b, 0x85, 0x01, + 0x83, 0xcc, 0x24, 0x17, 0xc2, 0x07, 0xda, 0x60, + 0x6c, 0xab, 0xfa, 0xe5, 0xd9, 0xb4, 0xf0, 0x3f, + 0xca, 0xf1, 0x30, 0x8d, 0xd2, 0x4e, 0xe3, 0xb4}, + {0x4f, 0xb3, 0x0d, 0x98, 0x38, 0x70, 0x28, 0xa2, + 0xca, 0x5d, 0x2c, 0xdf, 0x1f, 0xce, 0xff, 0xcc, + 0x75, 0x49, 0xa0, 0xef, 0x54, 0xd9, 0x32, 0x1b, + 0x17, 0xb6, 0x7e, 0x7a, 0xa6, 0x5f, 0x7a, 0xff}, + {0x81, 0x6b, 0x06, 0x73, 0x5b, 0x32, 0x0d, 0x37, + 0xb4, 0x50, 0x63, 0x52, 0x25, 0x72, 0x5c, 0xf5, + 0x5d, 0x58, 0xa6, 0xbf, 0x08, 0xcc, 0x1d, 0x70, + 0x2d, 0x12, 0x5d, 0xd7, 0xbd, 0xca, 0xe7, 0x10}, + {0x8f, 0xfc, 0x57, 0x17, 0xce, 0x47, 0x10, 0x79, + 0xae, 0x66, 0xa5, 0xcc, 0x98, 0x0b, 0x77, 0xe8, + 0xa2, 0x6e, 0xc1, 0x0d, 0x03, 0xe3, 0x5b, 0xed, + 0x38, 0x0e, 0x31, 0x2d, 0x19, 0x4d, 0xd6, 0x2a}, + {0xc6, 0x9d, 0x2d, 0x0b, 0xad, 0x6d, 0x0c, 0x61, + 0x2d, 0x62, 0xe4, 0xce, 0x73, 0x47, 0x72, 0x20, + 0x0c, 0x8e, 0x8f, 0xe9, 0xe7, 0x67, 0x66, 0x2e, + 0x17, 0x54, 0xec, 0x15, 0x3e, 0x1b, 0xf3, 0x04}, + {0xf4, 0xee, 0x03, 0x30, 0x2e, 0x1e, 0xa4, 0xb1, + 0x86, 0x6d, 0xc3, 0x54, 0xf3, 0xc5, 0x61, 0xa6, + 0xb9, 0x28, 0x29, 0x11, 0x91, 0xcb, 0xbd, 0xc9, + 0x77, 0x62, 0x09, 0x8c, 0xa4, 0x40, 0x84, 0x97}, + {0xff, 0x98, 0x9b, 0xbc, 0xc2, 0xf0, 0xf8, 0x7f, + 0x5c, 0x86, 0x74, 0x33, 0xee, 0x42, 0x6e, 0xab, + 0xd4, 0xd2, 0x1a, 0x0d, 0x41, 0x2d, 0xac, 0xa1, + 0x3e, 0x56, 0xed, 0x4b, 0x27, 0x5a, 0x65, 0xe4}, + {0x2b, 0xb1, 0xe3, 0x64, 0xaa, 0x32, 0x17, 0x57, + 0x7c, 0x67, 0xb8, 0x6b, 0x00, 0x53, 0xbe, 0x3e, + 0xec, 0xd1, 0x1b, 0xc4, 0xc3, 0x8d, 0xe6, 0x19, + 0xe8, 0x3a, 0x25, 0x98, 0x4e, 0xe9, 0xd4, 0x60}, + {0xa6, 0x2e, 0xb3, 0xc8, 0xcd, 0xc9, 0xc2, 0x8e, + 0xe1, 0xf0, 0x8f, 0x96, 0x8e, 0xc6, 0x37, 0x11, + 0xbc, 0x6c, 0x0c, 0xf6, 0xb6, 0x83, 0x38, 0x96, + 0x7a, 0x74, 0x5a, 0xa7, 0xe1, 0x11, 0x8d, 0x8b}, + {0x90, 0xf2, 0x4d, 0xbd, 0x83, 0x39, 0xe6, 0x54, + 0xf6, 0x75, 0xf6, 0x2c, 0x28, 0x3d, 0xd1, 0xcf, + 0xe1, 0xfb, 0x9f, 0x97, 0x19, 0xca, 0x4d, 0x2c, + 0x38, 0x3d, 0x36, 0xed, 0x19, 0xe9, 0x4a, 0x0b}, + {0x1a, 0x61, 0xb8, 0x19, 0x59, 0x16, 0x74, 0xec, + 0xdb, 0x7b, 0xeb, 0xd6, 0xae, 0xcd, 0xe9, 0x55, + 0xdb, 0x45, 0xdc, 0xf2, 0x35, 0x84, 0xe9, 0xe6, + 0x17, 0x48, 0xac, 0x38, 0x05, 0x21, 0x2c, 0x8e}, + {0x41, 0xac, 0x17, 0x42, 0xcc, 0x17, 0x10, 0x02, + 0x07, 0x7e, 0xfc, 0x4d, 0x77, 0x06, 0x70, 0xcb, + 0x40, 0x8b, 0x47, 0x47, 0x07, 0x29, 0x82, 0xca, + 0x93, 0x69, 0x2f, 0x3a, 0x64, 0xc6, 0xcb, 0x23}, + {0xa2, 0xcb, 0x2d, 0x02, 0x5d, 0x30, 0x9f, 0x32, + 0xf5, 0xc5, 0x13, 0xff, 0xfc, 0xe2, 0xfb, 0x26, + 0x3b, 0x3b, 0xaf, 0xa4, 0x37, 0x6d, 0x45, 0xbf, + 0xdb, 0xb9, 0xee, 0xec, 0x92, 0xa5, 0x1d, 0x0d}, + {0xa4, 0xef, 0x08, 0xb7, 0xb4, 0x68, 0x74, 0x93, + 0xb2, 0xda, 0xba, 0xe9, 0x05, 0xf5, 0x09, 0xb6, + 0x53, 0xdd, 0x17, 0x60, 0xbb, 0x1e, 0xb0, 0x71, + 0xd8, 0x47, 0x85, 0x02, 0x13, 0xbe, 0xa2, 0x67}, + {0x31, 0x50, 0x90, 0xb0, 0x83, 0x4a, 0xcf, 0x3f, + 0xbe, 0x88, 0x90, 0x4b, 0xe1, 0x9f, 0xe6, 0xd0, + 0xfd, 0x01, 0x8e, 0xfc, 0xc0, 0x8c, 0x2f, 0x9b, + 0x48, 0x70, 0x9d, 0x4e, 0x22, 0x21, 0x07, 0x09}, + {0x15, 0x9f, 0x37, 0x45, 0x52, 0x99, 0x6e, 0xe9, + 0x1a, 0x25, 0x56, 0x0b, 0x19, 0xf1, 0xca, 0x9f, + 0x29, 0xe5, 0x23, 0xa6, 0x0b, 0x94, 0x0a, 0xe3, + 0x74, 0xaa, 0xd5, 0x35, 0xaf, 0x6e, 0xb2, 0x24}, + {0x68, 0xab, 0xa6, 0x8b, 0x5f, 0xc7, 0x93, 0x1a, + 0x06, 0x51, 0x2c, 0x3b, 0xad, 0x44, 0x6b, 0x69, + 0x1a, 0x1d, 0x41, 0xca, 0x8e, 0x59, 0x2c, 0x83, + 0x71, 0x48, 0x8c, 0xaf, 0x50, 0x85, 0x00, 0xf3}, + {0xe2, 0xa6, 0x38, 0x93, 0xca, 0xe3, 0xd0, 0x36, + 0xf4, 0xe9, 0x53, 0xfb, 0xa0, 0xd0, 0x13, 0xd3, + 0x2b, 0x7d, 0x46, 0xc8, 0x8b, 0xc7, 0x8c, 0xca, + 0x59, 0xec, 0x66, 0x17, 0x70, 0xbb, 0xf9, 0x92}, + {0x89, 0xca, 0x92, 0x19, 0x01, 0xb8, 0x4b, 0x97, + 0x06, 0x1a, 0x12, 0x91, 0x72, 0x11, 0xeb, 0x12, + 0x8b, 0x12, 0xd9, 0xdc, 0xc9, 0xb2, 0x37, 0xf8, + 0x3e, 0x02, 0x03, 0xbe, 0x45, 0x45, 0xc9, 0x42}, + {0x45, 0x2c, 0x80, 0xe1, 0x3a, 0x0a, 0xdf, 0xa3, + 0xd2, 0x4a, 0x23, 0x0d, 0x47, 0x0d, 0x49, 0xad, + 0xdf, 0xb0, 0x42, 0xdf, 0x87, 0x85, 0xa6, 0x8f, + 0x9f, 0x7e, 0x9b, 0xa4, 0x42, 0x64, 0xcb, 0xfb}, + {0xc7, 0x39, 0x26, 0xb1, 0x90, 0x4d, 0xc1, 0x7a, + 0xea, 0x31, 0x1b, 0xae, 0x1a, 0x5c, 0x1f, 0x4f, + 0x44, 0x2f, 0x87, 0x08, 0x5d, 0xa6, 0x74, 0xfd, + 0xab, 0xb2, 0x4b, 0x01, 0xed, 0xd5, 0x4c, 0xe6}, + {0x2a, 0xef, 0xfa, 0x25, 0x3c, 0xd2, 0xc8, 0x08, + 0x9c, 0x33, 0x3c, 0x47, 0xb3, 0xb5, 0x44, 0x34, + 0x97, 0xee, 0xe8, 0x52, 0x1c, 0x15, 0xb3, 0xe0, + 0xda, 0xef, 0x77, 0xde, 0x15, 0x39, 0x4b, 0x38}, + {0x8a, 0x3a, 0x59, 0x61, 0x9d, 0x3e, 0x9b, 0x38, + 0xc9, 0x84, 0x80, 0xaf, 0xb4, 0x37, 0x8a, 0x67, + 0x47, 0xc9, 0x6c, 0x72, 0xef, 0x39, 0x50, 0x28, + 0x6c, 0x8f, 0xad, 0x09, 0x75, 0x26, 0xc9, 0xa9}, + {0x27, 0x1e, 0x8b, 0xf6, 0x6b, 0x56, 0x5d, 0x17, + 0x58, 0xac, 0xdf, 0x27, 0xd9, 0x3e, 0x5b, 0xdd, + 0xaf, 0xbc, 0xb7, 0xf9, 0x76, 0x3b, 0x40, 0x06, + 0xbc, 0x6e, 0xec, 0xaa, 0xb2, 0xdc, 0x9a, 0x0c}, + {0x09, 0x14, 0xef, 0x19, 0xc7, 0x7d, 0xc8, 0xa3, + 0xd0, 0xaa, 0x7f, 0x09, 0x18, 0xaf, 0xd3, 0xde, + 0xbf, 0x05, 0xfc, 0xf9, 0xeb, 0xc0, 0x8e, 0xcf, + 0xc7, 0x4c, 0x2f, 0x3f, 0xd4, 0x51, 0x41, 0xb2}, + {0xb7, 0x33, 0xf3, 0x72, 0x6d, 0x12, 0xc1, 0x5c, + 0x5d, 0x81, 0xb3, 0x63, 0x81, 0x50, 0x81, 0xc0, + 0x4a, 0xea, 0x18, 0x7c, 0xa6, 0x2d, 0x23, 0xba, + 0x4b, 0xb9, 0x31, 0xd9, 0xab, 0x20, 0x60, 0x77}, + {0xbb, 0x1c, 0x50, 0x2d, 0xdc, 0x18, 0x27, 0x98, + 0x60, 0xde, 0x17, 0xd9, 0x17, 0x3c, 0xd5, 0x98, + 0xc3, 0x12, 0xfd, 0x8b, 0x25, 0x1e, 0xa5, 0xc1, + 0xa8, 0xef, 0xec, 0x05, 0x3e, 0xfc, 0xd1, 0xfc}, + {0xe6, 0x3b, 0x9f, 0x33, 0x85, 0xeb, 0x91, 0xd0, + 0xad, 0x2f, 0xc2, 0x96, 0x61, 0x64, 0xbc, 0x12, + 0x15, 0x79, 0x65, 0x93, 0xc2, 0x63, 0xa3, 0x27, + 0x88, 0x60, 0x39, 0x35, 0x21, 0x05, 0xe9, 0x49}, + {0x9b, 0x68, 0xe7, 0xc8, 0xea, 0x0e, 0x5c, 0xa4, + 0x03, 0x3a, 0x4e, 0x31, 0xb1, 0x92, 0xad, 0x9d, + 0x7e, 0xb5, 0x93, 0x81, 0xdd, 0x7a, 0xe9, 0xa1, + 0x69, 0x28, 0x6a, 0xaf, 0x48, 0x05, 0x94, 0xc0}, + {0x66, 0x3d, 0x87, 0xc1, 0x48, 0x9d, 0xdf, 0x99, + 0x25, 0xd7, 0xb0, 0xfa, 0x03, 0x8b, 0x62, 0x60, + 0xc5, 0x07, 0x3f, 0xa2, 0xc8, 0xbd, 0x70, 0xdb, + 0x40, 0x6c, 0x65, 0xbf, 0x15, 0xfc, 0x1e, 0xc9}, + {0x38, 0x9c, 0x1a, 0x5b, 0x4f, 0x84, 0xca, 0xe1, + 0x30, 0x6a, 0xf0, 0xb6, 0xf1, 0x61, 0xd3, 0xb0, + 0xa6, 0x6d, 0x0d, 0x11, 0x03, 0xe0, 0xcb, 0x9f, + 0xbe, 0x7e, 0xc2, 0x7a, 0x53, 0x9d, 0x39, 0xcb}, + {0xf3, 0x47, 0x4a, 0x37, 0xcd, 0x19, 0x27, 0x0f, + 0xfb, 0x3f, 0xcb, 0x81, 0x1e, 0x0f, 0xfd, 0x1f, + 0x2e, 0x8d, 0xff, 0xe9, 0x52, 0x8b, 0x8e, 0x52, + 0x3c, 0x82, 0xe6, 0x44, 0xf6, 0x92, 0xd4, 0xd4}, + {0x3a, 0xe8, 0x4d, 0xcc, 0x4a, 0x0e, 0xaa, 0xf6, + 0x32, 0x88, 0x4c, 0xee, 0xaa, 0x9c, 0xeb, 0x59, + 0xb5, 0xb8, 0x06, 0x89, 0x49, 0xc9, 0xa6, 0xf7, + 0xa6, 0x14, 0x44, 0x55, 0x5e, 0x3e, 0x86, 0x08}, + {0xca, 0x3d, 0x95, 0x21, 0xf3, 0xbb, 0x78, 0x29, + 0x6a, 0x38, 0xd3, 0xe4, 0x48, 0x98, 0x6f, 0x0e, + 0xaf, 0x46, 0xa5, 0x02, 0xdd, 0xfb, 0x52, 0x42, + 0x9b, 0x69, 0x97, 0xe6, 0x68, 0x21, 0x0d, 0x69}, + {0x3a, 0x8a, 0x14, 0x6e, 0xa2, 0x24, 0x8f, 0x89, + 0x5e, 0x99, 0x8a, 0x5b, 0x90, 0xb1, 0xf3, 0x64, + 0x4d, 0x10, 0xef, 0x45, 0xa9, 0xfb, 0xbb, 0xc0, + 0xf5, 0x66, 0xdf, 0x15, 0xae, 0xd0, 0xd9, 0x56}, + {0x62, 0x50, 0x52, 0xb5, 0xb9, 0x76, 0xa7, 0xcb, + 0xe6, 0xf7, 0x3a, 0x9f, 0xa4, 0x1e, 0x0a, 0x4d, + 0x88, 0xa4, 0x1c, 0xea, 0x11, 0x8c, 0xfb, 0xbe, + 0x70, 0x62, 0xec, 0x4e, 0x00, 0x56, 0x0e, 0xa9}, }; #endif /* SANDYBRIDGE_RAMINIT_PATTERNS_H */ From 7f6586ff782e632902ae9a807b95c97659dd6a9a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 12:45:12 +0100 Subject: [PATCH 0573/1463] nb/intel/sandybridge: Do not define tables in a header Header files are supposed to not make allocations from .bss. Builds fail if said file is included multiple times. To prevent this from happening, move the definitions to a C file. Also, rename raminit_patterns to raminit_tables. This is because more tables that are not patterns will be added here in subsequent changes. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: If8e3a285ecdc4df9e978ae156be915ced6e1750b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39754 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- .../intel/sandybridge/Makefile.inc | 1 + .../intel/sandybridge/raminit_common.c | 3 +-- .../{raminit_patterns.h => raminit_tables.c} | 19 +++---------------- .../intel/sandybridge/raminit_tables.h | 15 +++++++++++++++ 4 files changed, 20 insertions(+), 18 deletions(-) rename src/northbridge/intel/sandybridge/{raminit_patterns.h => raminit_tables.c} (98%) create mode 100644 src/northbridge/intel/sandybridge/raminit_tables.h diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 7718bf9acd..11f1f15656 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -36,6 +36,7 @@ romstage-y += raminit.c romstage-y += raminit_common.c romstage-y += raminit_sandy.c romstage-y += raminit_ivy.c +romstage-y += raminit_tables.c romstage-y += ../../../device/dram/ddr3.c else romstage-y += raminit_mrc.c diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index e28907086d..9eb60c74c9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -24,6 +24,7 @@ #include "raminit_native.h" #include "raminit_common.h" +#include "raminit_tables.h" #include "sandybridge.h" /* FIXME: no ECC support */ @@ -2100,8 +2101,6 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) return lanes_ok != ((1 << NUM_LANES) - 1); } -#include "raminit_patterns.h" - static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) { unsigned int i, j; diff --git a/src/northbridge/intel/sandybridge/raminit_patterns.h b/src/northbridge/intel/sandybridge/raminit_tables.c similarity index 98% rename from src/northbridge/intel/sandybridge/raminit_patterns.h rename to src/northbridge/intel/sandybridge/raminit_tables.c index aa6c2dcfc7..1ecba1b935 100644 --- a/src/northbridge/intel/sandybridge/raminit_patterns.h +++ b/src/northbridge/intel/sandybridge/raminit_tables.c @@ -1,18 +1,7 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ -#ifndef SANDYBRIDGE_RAMINIT_PATTERNS_H -#define SANDYBRIDGE_RAMINIT_PATTERNS_H +#include "raminit_tables.h" const u32 pattern[32][16] = { {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, @@ -654,5 +643,3 @@ const u8 invert[63][32] = { 0x88, 0xa4, 0x1c, 0xea, 0x11, 0x8c, 0xfb, 0xbe, 0x70, 0x62, 0xec, 0x4e, 0x00, 0x56, 0x0e, 0xa9}, }; - -#endif /* SANDYBRIDGE_RAMINIT_PATTERNS_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_tables.h b/src/northbridge/intel/sandybridge/raminit_tables.h new file mode 100644 index 0000000000..4e225552c3 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_tables.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef RAMINIT_TABLES_H +#define RAMINIT_TABLES_H + +#include + +extern const u32 pattern[32][16]; + +extern const u8 use_base[63][32]; + +extern const u8 invert[63][32]; + +#endif /* RAMINIT_TABLES_H */ From 2b5c1e73a57642a3289f19ae061acc0ddbb56d7d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 12:17:47 +0100 Subject: [PATCH 0574/1463] nb/intel/sandybridge: Remove unnecessary declaration Change-Id: If99fd6511fcea474a1398d2b680e0df4bb1a229b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39755 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0735ceaa8f..516d8f5557 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -72,8 +72,6 @@ struct ram_rank_timings { } lanes[NUM_LANES]; }; -struct ramctr_timing_st; - typedef struct ramctr_timing_st { u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int sandybridge; From 5c1baf5bece75de2e396e3f37cfffba310cdf4cd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 12:23:35 +0100 Subject: [PATCH 0575/1463] nb/intel/sandybridge: Add warning to saved structs When changing any of the structures that are cached in non-volatile storage, it is necessary to bump MRC_CACHE_VERSION so that the old information is not misinterpreted. Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39756 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit.c | 2 -- src/northbridge/intel/sandybridge/raminit_common.h | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 34fb499599..dc999138f7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -33,8 +33,6 @@ #include "raminit_common.h" #include "sandybridge.h" -#define MRC_CACHE_VERSION 1 - /* FIXME: no ECC support */ /* FIXME: no support for 3-channel chipsets */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 516d8f5557..18a69af96f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -41,15 +41,22 @@ performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4 +/* + * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! + */ +#define MRC_CACHE_VERSION 1 + typedef struct odtmap_st { u16 rttwr; u16 rttnom; } odtmap; +/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct dimm_info_st { dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; } dimm_info; +/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ struct ram_rank_timings { /* ROUNDT_LAT register: One byte per slotrank */ u8 roundtrip_latency; @@ -72,6 +79,7 @@ struct ram_rank_timings { } lanes[NUM_LANES]; }; +/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct ramctr_timing_st { u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int sandybridge; From 80037f715c9de5a8bb926a0820508d7530e6f429 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 13:12:37 +0100 Subject: [PATCH 0576/1463] nb/intel/sandybridge: Store CPUID in ctrl struct Instead of storing an int with a single bit of information taken from the CPUID, we might as well store the actual CPUID. And since we are changing the definition of the saved data, bump the version number. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: I6ac435fb83900a52890f823e7614055061299e23 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39720 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit.c | 13 +++++-------- src/northbridge/intel/sandybridge/raminit_common.h | 6 ++++-- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index dc999138f7..2a3e4d73e3 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -227,20 +227,19 @@ static void save_timings(ramctr_timing *ctrl) static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) { - if (ctrl->sandybridge) + if (IS_SANDY_CPU(ctrl->cpu)) return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size); else return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size); } -static void init_dram_ddr3(int min_tck, int s3resume) +static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; spd_raw_data spds[4]; struct region_device rdev; ramctr_timing *ctrl_cached; - u32 cpu; MCHBAR32(SAPMCTL) |= 1; @@ -313,8 +312,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) ctrl.tCK = min_tck; /* Get architecture */ - cpu = cpu_get_cpuid(); - ctrl.sandybridge = IS_SANDY_CPU(cpu); + ctrl.cpu = cpuid; /* Get DDR3 SPD data */ memset(spds, 0, sizeof(spds)); @@ -334,8 +332,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) ctrl.tCK = min_tck; /* Get architecture */ - cpu = cpu_get_cpuid(); - ctrl.sandybridge = IS_SANDY_CPU(cpu); + ctrl.cpu = cpuid; /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); @@ -385,5 +382,5 @@ void perform_raminit(int s3resume) timestamp_add_now(TS_BEFORE_INITRAM); - init_dram_ddr3(get_mem_min_tck(), s3resume); + init_dram_ddr3(get_mem_min_tck(), s3resume, cpu_get_cpuid()); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 18a69af96f..0cbac8ae20 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -44,7 +44,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 1 +#define MRC_CACHE_VERSION 2 typedef struct odtmap_st { u16 rttwr; @@ -82,7 +82,9 @@ struct ram_rank_timings { /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct ramctr_timing_st { u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; - int sandybridge; + + /* CPUID value */ + u32 cpu; /* DDR base_freq = 100 Mhz / 133 Mhz */ u8 base_freq; From a6a64183d6c5d535df5e62fad419402cd896f03d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 18:06:03 +0100 Subject: [PATCH 0577/1463] nb/intel/sandybridge: Void MRC cache if CPUID differs Native raminit asserts that the DIMMs haven't been replaced before reusing the saved training data. However, it does not check if the CPU is still the same, so it can end up happily reusing data from an Ivy Bridge CPU onto a Sandy Bridge CPU, which runs the raminit_ivy.c code path. This can make the CPU run in unsupported configurations, which may result in an unstable system, or a failure to boot. To prevent that, ensure that the stored CPUID matches the CPUID of the installed CPU. If they differ, print a message and do not use the saved data. As it does not pose a problem for a regular boot, but precludes resuming from S3, use different loglevels depending on the bootpath. Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, works well. Change-Id: Ib0691f1f849b567579f6afa845c9460e14f8fa27 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39734 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/raminit.c | 27 +++++++++++++++------ 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2a3e4d73e3..9b524a34eb 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -239,7 +239,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) ramctr_timing ctrl; spd_raw_data spds[4]; struct region_device rdev; - ramctr_timing *ctrl_cached; + ramctr_timing *ctrl_cached = NULL; MCHBAR32(SAPMCTL) |= 1; @@ -266,14 +266,25 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) /* Try to find timings in MRC cache */ err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev); - if (err || (region_device_sz(&rdev) < sizeof(ctrl))) { - if (s3resume) { - /* Failed S3 resume, reset to come up cleanly */ - system_reset(); - } - ctrl_cached = NULL; - } else { + + if (!err && !(region_device_sz(&rdev) < sizeof(ctrl))) ctrl_cached = rdev_mmap_full(&rdev); + + /* Before reusing training data, assert that the CPU has not been replaced */ + if (ctrl_cached && cpuid != ctrl_cached->cpu) { + + /* It is not really worrying on a cold boot, but fatal when resuming from S3 */ + printk(s3resume ? BIOS_ALERT : BIOS_NOTICE, + "CPUID %x differs from stored CPUID %x, CPU was replaced!\n", + cpuid, ctrl_cached->cpu); + + /* Invalidate the stored data, it likely does not apply to the current CPU */ + ctrl_cached = NULL; + } + + if (s3resume && !ctrl_cached) { + /* S3 resume is impossible, reset to come up cleanly */ + system_reset(); } /* Verify MRC cache for fast boot */ From 89ae6b8fc2901b56dd1839a2d569493ce668a32c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 13:23:32 +0100 Subject: [PATCH 0578/1463] nb/intel/sandybridge: Use cached CPUID Now that we have it, we might as well pass it around. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.c | 9 +++------ src/northbridge/intel/sandybridge/raminit_common.h | 2 +- src/northbridge/intel/sandybridge/raminit_ivy.c | 2 +- src/northbridge/intel/sandybridge/raminit_sandy.c | 2 +- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9eb60c74c9..41d683b18a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -168,15 +168,14 @@ void dram_xover(ramctr_timing *ctrl) static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { - u32 addr, cpu, stretch; + u32 addr, stretch; stretch = ctrl->ref_card_offset[channel]; /* * ODT stretch: * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. */ - cpu = cpu_get_cpuid(); - if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { + if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { if (stretch == 2) stretch = 3; @@ -2992,10 +2991,8 @@ void set_scrambling_seed(ramctr_timing *ctrl) } } -void set_wmm_behavior(void) +void set_wmm_behavior(const u32 cpu) { - u32 cpu = cpu_get_cpuid(); - if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { MCHBAR32(SC_WDBWM) = 0x141d1519; } else { diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0cbac8ae20..0ff9265052 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -181,7 +181,7 @@ void normalize_training(ramctr_timing *ctrl); void write_controller_mr(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); -void set_wmm_behavior(void); +void set_wmm_behavior(const u32 cpu); void prepare_training(ramctr_timing *ctrl); void set_read_write_timings(ramctr_timing *ctrl); void set_normal_operation(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 06d23825b6..a714e535b4 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -609,7 +609,7 @@ int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in MCHBAR32(SCHED_CBIT) = 0x10100005; /* Set up watermarks and starvation counter */ - set_wmm_behavior(); + set_wmm_behavior(ctrl->cpu); /* Clear IO reset bit */ MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index c554c3aa89..a823d50398 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -433,7 +433,7 @@ int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in MCHBAR32(SCHED_CBIT) = 0x10100005; /* Set up watermarks and starvation counter */ - set_wmm_behavior(); + set_wmm_behavior(ctrl->cpu); /* Clear IO reset bit */ MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); From 208318cdf4069778bdb60f689129e3207098bb82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 20 Mar 2020 15:54:27 +0100 Subject: [PATCH 0579/1463] nb/amd/pi/00730F01: initialize GNB IOAPIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Northbridge IOAPIC was not being initialized which caused its APIC ID to be set to 0 (the same APIC ID as BSP). TEST=boot Debian Linux on PC Engines apu2 Signed-off-by: Michał Żygowski Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39700 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/northbridge/amd/pi/00730F01/northbridge.c | 9 +++++++++ src/northbridge/amd/pi/nb_common.h | 1 + 2 files changed, 10 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 05c5142a70..c87d8fffba 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -290,6 +291,7 @@ static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; + struct resource *res; nodeid = amdfam16_nodeid(dev); for (link = dev->link_list; link; link = link->next) { @@ -304,6 +306,12 @@ static void read_resources(struct device *dev) * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + /* NB IOAPIC2 resource */ + res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res->base = IO_APIC2_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) @@ -410,6 +418,7 @@ static void set_resources(struct device *dev) static void northbridge_init(struct device *dev) { + setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h index 3e78155afd..46a5c1a58e 100644 --- a/src/northbridge/amd/pi/nb_common.h +++ b/src/northbridge/amd/pi/nb_common.h @@ -15,5 +15,6 @@ #define __AMD_NB_COMMON_H__ #define DEV_CDB 0x18 +#define IO_APIC2_ADDR 0xfec20000 #endif From 3fbd2af112bb428e7894a03cd24ffeae9ace1763 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 19 Mar 2020 15:39:12 +0100 Subject: [PATCH 0580/1463] nb/amd/pi/00730F01/state_machine.c: unhardcode IOAPIC2 address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I95964ac6b5939f66c40bd56939bdf532a72d75ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/39701 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/northbridge/amd/pi/00730F01/state_machine.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index 4a049e5cef..d78c575ef3 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -19,6 +19,7 @@ #include #include #include +#include void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { @@ -63,7 +64,7 @@ void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ Mid->GnbMidConfiguration.iGpuVgaMode = 0; - Mid->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; + Mid->GnbMidConfiguration.GnbIoapicAddress = IO_APIC2_ADDR; } void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) From 4629830b73d331d2130e6bf3e49acd24f2bab3f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 19 Mar 2020 16:12:42 +0100 Subject: [PATCH 0581/1463] mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I385339761b3e1b5dcadb67b8ca29b1518c2db408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39702 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/mainboard/pcengines/apu2/mptable.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 36bd340fb0..747e777dca 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -15,6 +15,7 @@ #include #include #include +#include #include static void *smp_write_config_table(void *v) @@ -50,6 +51,11 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24); + ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF); + + smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); From c632bda2f6fe9dad5da4118ea9bb762a8eff1583 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 20 Mar 2020 10:58:51 -0600 Subject: [PATCH 0582/1463] soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). JSL requires 192KiB. Signed-off-by: Tim Wawrzynczak Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8d066f3d45..63bd881b71 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -84,11 +84,13 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x40400 if SOC_INTEL_TIGERLAKE + default 0x30400 if SOC_INTEL_JASPERLAKE help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage + stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex From 4bd69273882c66667590f098f2b9bb916b6c1a44 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 23 Mar 2020 11:01:08 +1100 Subject: [PATCH 0583/1463] mb/google/hatch: Give first NIC in Puff idx 1 for vpd The format for VPD has changed s.t. the first NIC should always have a zero concat to the end. drivers/net supports this with the workaround of setting the idx to 1. The longer term fix is to adjust all the respective boards to shift back by one and adjust drivers/net friends to remove the 'special casing' of idx == 0. Background: https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn BUG=b:152157720 BRANCH=none TEST=none Change-Id: I510428c555b92398a5199b346dffb85d38495d74 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39768 Tested-by: build bot (Jenkins) Reviewed-by: Sam McNally Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index cca2d41ce3..d8df2980ec 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -283,6 +283,7 @@ chip soc/intel/cannonlake register "stop_delay_ms" = "12" # NIC needs time to quiesce register "stop_off_delay_ms" = "1" register "has_power_resource" = "1" + register "device_index" = "1" device pci 00.0 on end end end # FSP requires func0 be enabled. From cc85ce0aa0d6a1e2a254282faf871a8f0a5ffe2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 21 Mar 2020 23:31:31 +0100 Subject: [PATCH 0584/1463] util/inteltool: add inteltool path to include path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the inteltool path to the include path to be able to avoid ugly include hacks like `#include "../inteltool.h"`. Change-Id: Id363fa20fe3b52248a224ca14b2626a8e3ce44a2 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39744 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- util/inteltool/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 0a21c07f53..bc6bcb3e38 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -25,6 +25,7 @@ PREFIX ?= /usr/local CFLAGS ?= -O2 -g -Wall -Wextra -Wmissing-prototypes LDFLAGS += -lpci -lz +CPPFLAGS += -I$(top)/util/inteltool CPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include CPPFLAGS += -I$(top)/src/arch/x86/include From e98f6af77bbd2060f01833559034f28b8b88abfe Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 21 Mar 2020 18:40:03 +0100 Subject: [PATCH 0585/1463] drivers/intel/gma/acpi: Reduce display switching stubs _DCS, _DGS and _DSS are required by specification. However, we never implemented them properly, and no OS driver com- plained yet. So we stub them out and keep the traditional behavior in case an OS driver checks for their existence. The old implementations also only returned static values as there never was any write to their GNVS variables. The TRAP() that was called in one place is actually implemented by some ThinkPad's SMI handler as docking event. However, as the call precedes these SMI handlers in coreboot history, it's most likely an accident. Change-Id: Ib0b9fcdd58df254d3b2290900e3bc206a7abd92d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39726 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/drivers/intel/gma/acpi.c | 41 +++++++++---------- src/drivers/intel/gma/acpi/common.asl | 35 ---------------- src/mainboard/51nb/x210/dsdt.asl | 2 - .../intel/bd82x6x/acpi/globalnvs.asl | 4 -- src/southbridge/intel/bd82x6x/nvs.h | 4 +- src/southbridge/intel/i82801dx/nvs.h | 4 +- .../intel/i82801gx/acpi/globalnvs.asl | 5 +-- src/southbridge/intel/i82801gx/nvs.h | 4 +- .../intel/i82801ix/acpi/globalnvs.asl | 4 -- src/southbridge/intel/i82801ix/nvs.h | 4 +- .../intel/i82801jx/acpi/globalnvs.asl | 4 -- src/southbridge/intel/i82801jx/nvs.h | 4 +- src/southbridge/intel/ibexpeak/nvs.h | 4 +- .../intel/lynxpoint/acpi/globalnvs.asl | 4 -- src/southbridge/intel/lynxpoint/nvs.h | 4 +- 15 files changed, 28 insertions(+), 99 deletions(-) diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index 3f71a5ea84..d3fb69dec8 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -102,39 +102,38 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * } /* - Method(_DCS, 0) - { - Return (^^XDCS()) - } + * _DCS, _DGS and _DSS are required by specification. However, + * we never implemented them properly, and no OS driver com- + * plained yet. So we stub them out and keep the traditional + * behavior in case an OS driver checks for their existence. + */ + + /* + Method(_DCS, 0) + { + Return (0x1d) + } */ acpigen_write_method("_DCS", 0); - acpigen_emit_byte(0xa4); /* ReturnOp. */ - acpigen_emit_namestring("^^XDCS"); - acpigen_write_byte(i); + acpigen_write_return_integer(0x1d); acpigen_pop_len(); /* - Method(_DGS, 0) - { - Return (^^XDGS()) - } + Method(_DGS, 0) + { + Return (0) + } */ acpigen_write_method("_DGS", 0); - acpigen_emit_byte(0xa4); /* ReturnOp. */ - acpigen_emit_namestring("^^XDGS"); - acpigen_write_byte(i); + acpigen_write_return_integer(0); acpigen_pop_len(); /* - Method(_DSS, 1) - { - ^^XDSS(0x5a, Arg0) - } + Method(_DSS, 1) + { + } */ acpigen_write_method("_DSS", 1); - acpigen_emit_namestring("^^XDSS"); - acpigen_write_byte(i); - acpigen_emit_byte(0x68); /* Arg0Op. */ acpigen_pop_len(); acpigen_pop_len(); diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl index 3932a88e87..09d48a20e0 100644 --- a/src/drivers/intel/gma/acpi/common.asl +++ b/src/drivers/intel/gma/acpi/common.asl @@ -35,11 +35,6 @@ /* Display Output Switching */ Method (_DOS, 1) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) } /* @@ -80,33 +75,3 @@ XBCM (DerefOf (Index (BRIG, Local0))) } } - - /* Device Current Status */ - Method(XDCS, 1) - { - TRAP(1) - If (And(CSTE, ShiftLeft (1, Arg0))) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(XDGS, 1) - { - If (And(NSTE, ShiftLeft (1, Arg0))) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(XDSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index 441a80dd4a..b88a56c632 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -12,8 +12,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - Name(\DSEN, 1) - #include "acpi/platform.asl" #include diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 3e7874cfaa..1b23cef6ac 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -16,7 +16,6 @@ /* Global Variables */ Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable /* Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. @@ -89,9 +88,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state Offset (0x46), NDID, 8, // 0x46 - Number of Device IDs DID1, 32, // 0x47 - Device ID 1 diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 326c2ea0d5..93ebed66ec 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -75,9 +75,7 @@ typedef struct global_nvs_t { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ + u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ u8 rsvd5[0x9]; diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index b95f9c95fa..1882fcb26c 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -69,9 +69,7 @@ typedef struct { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ + u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ u8 rsvd5[0x9]; diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 5787cec5c2..4a19de1476 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -16,7 +16,6 @@ /* Global Variables */ Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable /* Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. @@ -88,9 +87,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state + Offset (0x46), NDID, 8, // 0x46 - Number of Device IDs DID1, 32, // 0x47 - Device ID 1 DID2, 32, // 0x4b - Device ID 2 diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index a0f91cda68..6a178d2f3a 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -71,9 +71,7 @@ typedef struct { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ + u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ u8 rsvd5[0x9]; diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index a419fdb685..306260e58e 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -16,7 +16,6 @@ /* Global Variables */ Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable /* Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. @@ -92,9 +91,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state Offset (0x46), NDID, 8, // 0x46 - Number of Device IDs DID1, 32, // 0x47 - Device ID 1 diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index cb4fb45519..815186591f 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -73,9 +73,7 @@ typedef struct { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ + u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ u8 rsvd5[0x9]; diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 3c9dbc3f40..7d05ffbe98 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -16,7 +16,6 @@ /* Global Variables */ Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable /* Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. @@ -92,9 +91,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state Offset (0x46), NDID, 8, // 0x46 - Number of Device IDs DID1, 32, // 0x47 - Device ID 1 diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 26ecda33c8..e9e903711a 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -71,9 +71,7 @@ typedef struct { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ + u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ u8 rsvd5[0x9]; diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index a551fa473c..939b7e4cc8 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -74,9 +74,7 @@ typedef struct global_nvs_t { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ + u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ u8 rsvd5[0x9]; diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 149b75be6e..6dcec0dccc 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -16,7 +16,6 @@ /* Global Variables */ Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable /* Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. @@ -89,9 +88,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state Offset (0x46), NDID, 8, // 0x46 - Number of Device IDs DID1, 32, // 0x47 - Device ID 1 diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 5222db2c45..3f2ce55766 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -75,9 +75,7 @@ typedef struct global_nvs_t { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ + u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ /* TPM support */ From 53c1717dc139e9256294c73b2e8a45dd8de08835 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 21 Mar 2020 18:47:24 +0100 Subject: [PATCH 0586/1463] drivers/intel/gma/acpi: Refine some cosmetics TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: Ie3b00daedc9de05abef0cae9cea99dc7acf1ff62 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39727 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/acpi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index d3fb69dec8..ff4372f610 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -29,39 +29,45 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * acpigen_write_scope("\\_SB.PCI0.GFX0"); /* - Method (_DOD, 0) - { + Method (_DOD, 0) + { Return (Package() { 0x5a5a5a5a, 0x5a5a5a5a, 0x5a5a5a5a }) - } + } */ acpigen_write_method("_DOD", 0); - acpigen_emit_byte(0xa4); /* ReturnOp. */ - acpigen_write_package(conf->ndid); + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(conf->ndid); for (i = 0; i < conf->ndid; i++) { acpigen_write_dword (conf->did[i] | 0x80010000); } acpigen_pop_len(); /* End Package. */ + acpigen_pop_len(); /* End Method. */ for (i = 0; i < conf->ndid; i++) { char name[10]; char *ptr; int kind; + kind = (conf->did[i] >> 8) & 0xf; if (kind >= ARRAY_SIZE(names)) { kind = 0; } + strcpy(name, names[kind]); for (ptr = name; *ptr; ptr++); *ptr++ = counters[kind] + '0'; *ptr++ = '\0'; counters[kind]++; + + /* Device (LCD0) */ acpigen_write_device(name); + /* Name (_ADR, 0x0410) */ acpigen_write_name_dword("_ADR", conf->did[i] & 0xffff); @@ -74,7 +80,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * } */ acpigen_write_method("_BCL", 0); - acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring("^^XBCL"); acpigen_pop_len(); @@ -86,7 +92,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * */ acpigen_write_method("_BCM", 1); acpigen_emit_namestring("^^XBCM"); - acpigen_emit_byte(0x68); /* Arg0Op. */ + acpigen_emit_byte(ARG0_OP); acpigen_pop_len(); /* @@ -96,7 +102,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * } */ acpigen_write_method("_BQC", 0); - acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring("^^XBQC"); acpigen_pop_len(); } @@ -136,8 +142,8 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * acpigen_write_method("_DSS", 1); acpigen_pop_len(); - acpigen_pop_len(); + acpigen_pop_len(); /* End Device. */ } - acpigen_pop_len(); + acpigen_pop_len(); /* End Scope. */ } From c0be4107606c4aeb41fb238a5ef31339b27e5da0 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 21 Mar 2020 18:52:14 +0100 Subject: [PATCH 0587/1463] drivers/intel/gma/acpi: Use snprintf() to construct device name TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: Ieee02f698879ba6b60d863dd63ef9107c0d502b5 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39728 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/acpi.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index ff4372f610..3ec8527e6f 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -50,8 +50,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * acpigen_pop_len(); /* End Method. */ for (i = 0; i < conf->ndid; i++) { - char name[10]; - char *ptr; + char name[5]; int kind; kind = (conf->did[i] >> 8) & 0xf; @@ -59,10 +58,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * kind = 0; } - strcpy(name, names[kind]); - for (ptr = name; *ptr; ptr++); - *ptr++ = counters[kind] + '0'; - *ptr++ = '\0'; + snprintf(name, sizeof(name), "%s%d", names[kind], counters[kind]); counters[kind]++; /* Device (LCD0) */ From bed7ad9cd300b387eb2c92d54cac836a80fd0385 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 21 Mar 2020 19:09:45 +0100 Subject: [PATCH 0588/1463] drivers/intel/gma/acpi: Let the compiler initialize counters[] TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: I8ff3493be4dc8d640a511358a5324eb73eb35db9 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39729 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons --- src/drivers/intel/gma/acpi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index 3ec8527e6f..677414612a 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -22,9 +22,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * { size_t i; const char *names[] = { "UNK", "VGA", "TV", "DVI", "LCD" }; - int counters[ARRAY_SIZE(names)]; - - memset(counters, 0, sizeof(counters)); + int counters[ARRAY_SIZE(names)] = { 0 }; acpigen_write_scope("\\_SB.PCI0.GFX0"); From 53ec8c5722cc50ff9e48a8ff6c6b4011326659de Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 21 Mar 2020 19:50:26 +0100 Subject: [PATCH 0589/1463] drivers/intel/gma/acpi: Use SPDX license identifiers Change-Id: I9012394e553211abe4b225beb9150d997d0c2e38 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39730 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons --- src/drivers/intel/gma/acpi.c | 15 ++------------- src/drivers/intel/gma/acpi/common.asl | 15 ++------------- .../gma/acpi/configure_brightness_levels.asl | 14 ++------------ src/drivers/intel/gma/acpi/non-pch.asl | 15 ++------------- src/drivers/intel/gma/acpi/pch.asl | 15 ++------------- 5 files changed, 10 insertions(+), 64 deletions(-) diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index 677414612a..c0eef880a9 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl index 09d48a20e0..6a26335d8b 100644 --- a/src/drivers/intel/gma/acpi/common.asl +++ b/src/drivers/intel/gma/acpi/common.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ External(LCD0, DeviceObj) diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 21f0b2318e..aa1730cc8b 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Pseudo device that contains methods to modify Opregion diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl index 4a4aad9962..b656d484c9 100644 --- a/src/drivers/intel/gma/acpi/non-pch.asl +++ b/src/drivers/intel/gma/acpi/non-pch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (GFX0) { diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl index 6ec5fbb220..942ccf433c 100644 --- a/src/drivers/intel/gma/acpi/pch.asl +++ b/src/drivers/intel/gma/acpi/pch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (GFX0) { From e47132be6601bfd485076d6520e56a8b8ecb0737 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 23 Mar 2020 01:33:23 +0100 Subject: [PATCH 0590/1463] intel/broadwell: Correct backlight-PWM divider The PWM-granularity chicken bit in the Wildcat Point and Lynx Point PCHs has actually the opposite meaning of the one for Sunrise Point and later. When the bit is set, we get a divider of 16, when it's unset 128. Flip the bit! Change-Id: I1dbde1915d8b269c11643a1636565a560eb07334 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39770 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/broadwell/igd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 37f3871483..ecb5417181 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -348,10 +348,10 @@ static void igd_setup_panel(struct device *dev) south_chicken2 = gtt_read(SOUTH_CHICKEN2); if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { pwm_increment = 16; - south_chicken2 &= ~(1 << 5); + south_chicken2 |= 1 << 5; } else { pwm_increment = 128; - south_chicken2 |= 1 << 5; + south_chicken2 &= ~(1 << 5); } gtt_write(SOUTH_CHICKEN2, south_chicken2); From d07ac8ee13ce7f1af5a9d9a5d2e194ab27b8fb9a Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 22 Mar 2020 20:12:13 +0100 Subject: [PATCH 0591/1463] drivers/intel/gma: Ditch `link_frequency_270_mhz` setting The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons Reviewed-by: Alexander Couzens Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/i915.h | 1 - .../apple/macbookair4_2/devicetree.cb | 1 - src/mainboard/asrock/b75pro3-m/devicetree.cb | 1 - .../compulab/intense_pc/devicetree.cb | 1 - src/mainboard/google/stout/devicetree.cb | 1 - .../hp/compaq_8200_elite_sff/devicetree.cb | 1 - .../hp/snb_ivb_laptops/devicetree.cb | 1 - .../hp/z220_sff_workstation/devicetree.cb | 1 - src/mainboard/lenovo/l520/devicetree.cb | 1 - src/mainboard/lenovo/s230u/devicetree.cb | 1 - src/mainboard/lenovo/t410/devicetree.cb | 1 - src/mainboard/lenovo/t420/devicetree.cb | 1 - src/mainboard/lenovo/t420s/devicetree.cb | 1 - src/mainboard/lenovo/t430/devicetree.cb | 1 - src/mainboard/lenovo/t430s/devicetree.cb | 1 - src/mainboard/lenovo/t520/devicetree.cb | 1 - .../lenovo/t530/variants/t530/devicetree.cb | 1 - .../lenovo/t530/variants/w530/devicetree.cb | 1 - src/mainboard/lenovo/x131e/devicetree.cb | 1 - .../lenovo/x1_carbon_gen1/devicetree.cb | 1 - src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/lenovo/x220/devicetree.cb | 1 - src/mainboard/lenovo/x230/devicetree.cb | 1 - src/mainboard/msi/ms7707/devicetree.cb | 1 - .../packardbell/ms2290/devicetree.cb | 1 - util/autoport/sandybridge.go | 21 ------------------- 26 files changed, 46 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index e02a230854..0ac706275a 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -88,7 +88,6 @@ u32 gtt_read(u32 reg); struct i915_gpu_controller_info { int use_spread_spectrum_clock; - int link_frequency_270_mhz; u32 backlight; int ndid; u32 did[5]; diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 15ec61e717..6e99b63077 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "2" register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x00001312" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 3a2f134a98..50033b3b27 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -14,7 +14,6 @@ # chip northbridge/intel/sandybridge - register "gfx.link_frequency_270_mhz" = "0" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "4" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 4717eca3eb..b333245da6 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -12,7 +12,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index b9ccbf938c..089aea3bc4 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -16,7 +16,6 @@ chip northbridge/intel/sandybridge # For native gfx register "gfx.use_spread_spectrum_clock" = "0" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 0cc4f9db13..ce13e0ae37 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -14,7 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.link_frequency_270_mhz" = "0" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index d4827cffcc..52fd627c5a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x00000129" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 9f184e8c75..2be0ed7b87 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -14,7 +14,6 @@ ## chip northbridge/intel/sandybridge - register "gfx.link_frequency_270_mhz" = "0" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 29b75984fb..897b52a558 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" register "gpu_cpu_backlight" = "0x00000000" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index b03e2f9459..8483a54c7d 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x00000060" diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index c48285e44c..064bc741d2 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -31,7 +31,6 @@ chip northbridge/intel/ironlake register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 53bd16f68a..eaae94c35f 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index c91b04e919..5cf3165e33 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -13,7 +13,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index cfdc3a4189..1cb38599b1 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -13,7 +13,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index ee612cd95c..586e7d9a75 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -13,7 +13,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index e28f6cc552..296a30491f 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 09fb3cdb59..d10371fdba 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 17b0b41a10..095111b3ce 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 2d15d87176..5f19740db3 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -13,7 +13,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "3000" register "gpu_panel_power_backlight_off_delay" = "2000" register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index ded920cb07..c9a83f5e0b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x00001155" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 8b6f1486cd..5bfbebd4be 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -32,7 +32,6 @@ chip northbridge/intel/ironlake register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 5ae14278b4..8749b5cfd5 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index e492dda710..52c5d329dc 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index f520ea49e7..db48656489 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -1,5 +1,4 @@ chip northbridge/intel/sandybridge - register "gfx.link_frequency_270_mhz" = "0" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 231e2cbf3e..52be51bbf1 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -32,7 +32,6 @@ chip northbridge/intel/ironlake register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" register "gfx.use_spread_spectrum_clock" = "0" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index acfda6b8dd..a64ef7a4c2 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -14,26 +14,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); `) - pchLVDS := inteltool.IGD[0xe1180] - dualChannel := pchLVDS&(3<<2) == (3 << 2) - pipe := (pchLVDS >> 30) & 1 - link_m1 := inteltool.IGD[0x60040+0x1000*pipe] - link_n1 := inteltool.IGD[0x60044+0x1000*pipe] - link_factor := float32(link_m1) / float32(link_n1) - fp0 := inteltool.IGD[0xc6040+8*pipe] - dpll := inteltool.IGD[0xc6014+4*pipe] - pixel_m2 := fp0 & 0xff - pixel_m1 := (fp0>>8)&0xff + 2 - pixel_p1 := uint32(1) - for i := dpll & 0x1ffff; i != 0 && i&1 == 0; i >>= 1 { - pixel_p1++ - } - pixel_n := ((fp0 >> 16) & 0xff) + 2 - pixel_frequency := float32(120000*(5*pixel_m1+pixel_m2)) / float32(pixel_n*pixel_p1*7.0) - if !dualChannel { - pixel_frequency /= 2 - } - link_frequency := pixel_frequency / link_factor DevTree = DevTreeNode{ Chip: "northbridge/intel/sandybridge", MissingParent: "northbridge", @@ -51,7 +31,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), "gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0), - "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000), }, Children: []DevTreeNode{ { From c04871a398ca945b42fde0867572094c38f6f92c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 20 Mar 2020 16:14:36 +0100 Subject: [PATCH 0592/1463] mb/pcengines/apu2: add reset logic for PCIe slots MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PC Engines apu2 had many problems with PCIe cards detection. The cards were inconsistently detected when booted from G3, S5 or after a reboot. AGESA can reset PCIe slots using GPIO via callback. Use it to reset the slots that support using GPIO as reset signal. Signed-off-by: Michał Żygowski Change-Id: I8ff7db6ff85cce45b84729be905e6c895a24f6f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39703 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/pcengines/apu2/BiosCallOuts.c | 71 +++++++++++++++++++++ src/mainboard/pcengines/apu2/OemCustomize.c | 19 ++++-- src/mainboard/pcengines/apu2/romstage.c | 9 +++ 3 files changed, 94 insertions(+), 5 deletions(-) diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index d6f8d84300..69af3f9db3 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -24,6 +25,7 @@ #include "hudson.h" static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPciExSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -32,6 +34,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPciExSlotReset }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; @@ -139,3 +142,71 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_SUCCESS; } + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPciExSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + PCIe_SLOT_RESET_INFO *ResetInfo; + uint32_t GpioData; + uint8_t GpioValue; + + ResetInfo = ConfigPtr; + Status = AGESA_UNSUPPORTED; + + switch (ResetInfo->ResetId) { + /* + * ResetID 1 = PCIE_RST# affects all PCIe slots on all boards except + * apu2. ResetID 1 does not need any GPIO. + */ + case 1: + Status = AGESA_SUCCESS; + break; + case 51: /* GPIO51 resets mPCIe1 slot on apu2 */ + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + GpioData = gpio1_read32(0x8); + printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xa); + GpioValue &= ~BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + GpioData = gpio1_read32(0x8); + printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xa); + GpioValue |= BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + } + break; + case 55: /* GPIO51 resets mPCIe2 slot on apu2 */ + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + GpioData = gpio1_read32(0xc); + printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xe); + GpioValue &= ~BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + GpioData = gpio1_read32(0xc); + printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xe); + GpioValue |= BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + } + break; + } + + return Status; +} diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 99b9d518e7..6339e0fc4a 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -15,6 +15,15 @@ #include #include +#define PCIE_NIC_RESET_ID 1 + +#if CONFIG(BOARD_PCENGINES_APU2) +#define PCIE_GFX_RESET_ID 55 +#define PCIE_PORT3_RESET_ID 51 +#else +#define PCIE_GFX_RESET_ID PCIE_NIC_RESET_ID +#define PCIE_PORT3_RESET_ID PCIE_NIC_RESET_ID +#endif static const PCIe_PORT_DESCRIPTOR PortList[] = { { @@ -24,7 +33,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x01, 0) + AspmDisabled, PCIE_PORT3_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -34,7 +43,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x02, 0) + AspmDisabled, PCIE_NIC_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -44,7 +53,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x03, 0) + AspmDisabled, PCIE_NIC_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -54,7 +63,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x04, 0) + AspmDisabled, PCIE_NIC_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -64,7 +73,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x05, 0) + AspmDisabled, PCIE_GFX_RESET_ID, 0) } }; diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 7565bfca1d..34c42b43ff 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -38,6 +38,15 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Release GPIO32/33 for other uses. */ pm_write8(0xea, 1); + + /* + * Assert resets on the PCIe slots, since AGESA calls deassert callout + * only. Only apu2 uses GPIOs to reset PCIe slots. + */ + if (CONFIG(BOARD_PCENGINES_APU2)) { + gpio1_write8(0xa, gpio1_read8(0xa) & ~(1 << 6)); + gpio1_write8(0xe, gpio1_read8(0xe) & ~(1 << 6)); + } } static void early_lpc_init(void) From 8e46d42009f8d8f24787fcaa9785d62ae9260786 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 20 Mar 2020 16:19:55 +0100 Subject: [PATCH 0593/1463] mb/pcengines/apu2: enable PCIe power management features MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable ASPM L0s and L1, Common Clock and Clock Power Management for all PCIe ports. TEST=boot Debian linux and check new PCIe capabilities appear in lspci Signed-off-by: Michał Żygowski Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39704 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/mainboard/pcengines/apu2/Kconfig | 4 ++++ src/mainboard/pcengines/apu2/OemCustomize.c | 20 +++++++++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index b434ddc810..1915cc22d7 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -30,6 +30,10 @@ config BOARD_SPECIFIC_OPTIONS select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6339e0fc4a..e47a2c8317 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -33,7 +33,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_PORT3_RESET_ID, 0) + AspmL0sL1, + PCIE_PORT3_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -43,7 +45,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -53,7 +57,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -63,7 +69,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -73,7 +81,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_GFX_RESET_ID, 0) + AspmL0sL1, + PCIE_GFX_RESET_ID, + ClkPmSupportEnabled) } }; From 4d177e47c3c5e2bc173f81767846ae197a841d1f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 12 Feb 2020 13:20:25 +0100 Subject: [PATCH 0594/1463] mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Nuvoton NCT5104d has no LDN 0xe according to its datasheet. Signed-off-by: Michał Żygowski Change-Id: I0d34218d88b779b08c380d2396ff9ab9253597fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/38851 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/pcengines/apu1/devicetree.cb | 1 - src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb | 1 - src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 1 - src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb | 1 - src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb | 1 - 5 files changed, 5 deletions(-) diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 60509982e9..4974cfbfbb 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family14/root_complex device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end - device pnp 2e.e off end device pnp 2e.f on end end chip drivers/pc80/tpm diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index a8be385a79..3528e86362 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end - device pnp 2e.e off end device pnp 2e.f on end end # SIO NCT5104D chip drivers/pc80/tpm diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index f7593784f6..13643a42c0 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end - device pnp 2e.e off end device pnp 2e.f on end end # SIO NCT5104D end # LPC 0x439d diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index d481004a36..f5082d466f 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end - device pnp 2e.e off end device pnp 2e.f on end end # SIO NCT5104D end # LPC 0x439d diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index 677b171e72..309674bab1 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -69,7 +69,6 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end - device pnp 2e.e off end end # SIO NCT5104D chip drivers/pc80/tpm device pnp 0c31.0 on end From 6e5aabd58aa3d87d81ed39ef7f5219c7bef82e84 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 23:44:42 +0100 Subject: [PATCH 0595/1463] nb/intel/sandybridge: Use SPDX headers Note that pei_data.h uses the BSD 3-Clause license: https://opensource.org/licenses/BSD-3-Clause Change-Id: I904b343283239af4fdee583bcbea757f59a0cca7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39777 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/sandybridge/Kconfig | 14 +-------- .../intel/sandybridge/Makefile.inc | 15 ++-------- src/northbridge/intel/sandybridge/acpi.c | 16 ++-------- .../intel/sandybridge/acpi/hostbridge.asl | 17 ++--------- .../intel/sandybridge/acpi/peg.asl | 16 ++-------- .../intel/sandybridge/acpi/sandybridge.asl | 16 ++-------- src/northbridge/intel/sandybridge/bootblock.c | 14 ++------- src/northbridge/intel/sandybridge/chip.h | 15 ++-------- src/northbridge/intel/sandybridge/common.c | 16 ++-------- src/northbridge/intel/sandybridge/early_dmi.c | 15 ++-------- .../intel/sandybridge/early_init.c | 15 ++-------- src/northbridge/intel/sandybridge/finalize.c | 16 ++-------- src/northbridge/intel/sandybridge/gma.c | 15 ++-------- src/northbridge/intel/sandybridge/gma.h | 15 ++-------- .../intel/sandybridge/mchbar_regs.h | 17 ++--------- src/northbridge/intel/sandybridge/memmap.c | 15 ++-------- .../intel/sandybridge/northbridge.c | 15 ++-------- src/northbridge/intel/sandybridge/pcie.c | 16 ++-------- src/northbridge/intel/sandybridge/pei_data.h | 30 ++----------------- src/northbridge/intel/sandybridge/raminit.c | 15 ++-------- src/northbridge/intel/sandybridge/raminit.h | 15 ++-------- .../intel/sandybridge/raminit_common.c | 15 ++-------- .../intel/sandybridge/raminit_common.h | 15 ++-------- .../intel/sandybridge/raminit_ivy.c | 15 ++-------- .../intel/sandybridge/raminit_mrc.c | 15 ++-------- .../intel/sandybridge/raminit_native.h | 15 ++-------- .../intel/sandybridge/raminit_sandy.c | 15 ++-------- .../intel/sandybridge/raminit_shared.c | 14 ++------- src/northbridge/intel/sandybridge/romstage.c | 15 ++-------- .../intel/sandybridge/sandybridge.h | 15 ++-------- 30 files changed, 59 insertions(+), 413 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7c16632072..a9bbf58ef8 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -1,17 +1,5 @@ -## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - config NORTHBRIDGE_INTEL_SANDYBRIDGE bool diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 11f1f15656..81f3818e62 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -1,16 +1,5 @@ -# -# This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index d0434259d4..9fd13e62b6 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index b0e314e1f3..26df8f2de1 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index 4ebf74389a..e48cbea3b8 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PEGP) { diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 546dac92dd..555058cbe6 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "hostbridge.asl" #include "peg.asl" diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 9dfeed6a4a..39564cf970 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 83181567a5..2e97f31406 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H #define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index 59972dc72d..0533d1ddfa 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index dec371fd15..89bed7403d 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 390fadca65..d63ba1e311 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index ab2a21c37f..e3e1964349 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f0232e069a..1680b1e2a1 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index bf04deed5b..3eaa4845a1 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H #define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 929392bcd6..a8ae9c53a9 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ #define __SANDYBRIDGE_MCHBAR_REGS_H__ diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 60b6dcdf31..52a83e74c0 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index abfc1259de..ef03865905 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 05f05ecc1d..0c3912c0bf 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 8114bcc153..7abc25f8b6 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -1,31 +1,5 @@ -/* - * coreboot UEFI PEI wrapper - * - * Copyright (c) 2011, Google Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* coreboot UEFI PEI wrapper */ #ifndef PEI_DATA_H #define PEI_DATA_H diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 9b524a34eb..93bfd4c540 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 6febfa3f61..efd87d0099 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_H #define RAMINIT_H diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 41d683b18a..90c7164350 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0ff9265052..43bdd340dd 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_COMMON_H #define RAMINIT_COMMON_H diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index a714e535b4..3dcdaba4f9 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 6d00afa6cb..ae95efa81d 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 60a5665ba9..21ba99b49d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_NATIVE_H #define RAMINIT_NATIVE_H diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index a823d50398..2ee91e8a48 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_shared.c b/src/northbridge/intel/sandybridge/raminit_shared.c index 6162544bdc..ab91b05a10 100644 --- a/src/northbridge/intel/sandybridge/raminit_shared.c +++ b/src/northbridge/intel/sandybridge/raminit_shared.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index ec44ee2c8a..8745986416 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8fb72ccbf8..02d2e1384a 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ From 825332d3c9eb4c32b9e2f8eb54bcc838b1c00bb3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 19:31:53 +0100 Subject: [PATCH 0596/1463] nb/intel/sandybridge: Factor out timing tables The timing tables for Sandy Bridge are a subset of Ivy Bridge's tables. Move the latter to a common place, and use it for both generations. Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, both work. Change-Id: Id14227febf4eebb8a2b4d2d4f37759d0f42648c6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39735 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_ivy.c | 157 +++++------------- .../intel/sandybridge/raminit_sandy.c | 55 ++---- .../intel/sandybridge/raminit_tables.c | 105 ++++++++++++ .../intel/sandybridge/raminit_tables.h | 20 +++ 4 files changed, 172 insertions(+), 165 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 3dcdaba4f9..67927ed033 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -7,6 +7,7 @@ #include #include "raminit_native.h" #include "raminit_common.h" +#include "raminit_tables.h" /* Frequency multiplier */ static u32 get_FRQ(u32 tCK, u8 base_freq) @@ -31,175 +32,91 @@ static u32 get_FRQ(u32 tCK, u8 base_freq) /* Get REFI based on MC frequency, tREFI = 7.8usec */ static u32 get_REFI(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u32 frq_xs_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 5460, 6240, 7020, 7800, 8580, 9360, - }; - return frq_xs_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_refi_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u32 frq_refi_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 3120, 4160, 5200, 6240, 7280, 8320, 9360, 10400, - }; - return frq_refi_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_refi_map[0][get_FRQ(tCK, 133) - 3]; } /* Get XSOffset based on MC frequency, tXS-Offset: tXS = tRFC + 10ns */ static u8 get_XSOffset(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u8 frq_xs_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 7, 8, 9, 10, 11, 12, - }; - return frq_xs_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_xs_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u8 frq_xs_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 4, 6, 7, 8, 10, 11, 12, 14, - }; - return frq_xs_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_xs_map[0][get_FRQ(tCK, 133) - 3]; } /* Get MOD based on MC frequency */ static u8 get_MOD(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u8 frq_mod_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 12, 12, 14, 15, 17, 18, - }; - return frq_mod_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_mod_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u8 frq_mod_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 12, 12, 12, 12, 15, 16, 18, 20, - }; - return frq_mod_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_mod_map[0][get_FRQ(tCK, 133) - 3]; } /* Get Write Leveling Output delay based on MC frequency */ static u8 get_WLO(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u8 frq_wlo_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 6, 6, 7, 8, 9, 9, - }; - return frq_wlo_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_wlo_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u8 frq_wlo_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 4, 5, 6, 6, 8, 8, 9, 10, - }; - return frq_wlo_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_wlo_map[0][get_FRQ(tCK, 133) - 3]; } /* Get CKE based on MC frequency */ static u8 get_CKE(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u8 frq_cke_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 4, 4, 5, 5, 6, 6, - }; - return frq_cke_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_cke_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u8 frq_cke_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 3, 3, 4, 4, 5, 6, 6, 7, - }; - return frq_cke_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_cke_map[0][get_FRQ(tCK, 133) - 3]; } /* Get XPDLL based on MC frequency */ static u8 get_XPDLL(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u8 frq_xpdll_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 17, 20, 22, 24, 27, 32, - }; - return frq_xpdll_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_xpdll_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u8 frq_xpdll_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 10, 13, 16, 20, 23, 26, 29, 32, - }; - return frq_xpdll_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_xpdll_map[0][get_FRQ(tCK, 133) - 3]; } /* Get XP based on MC frequency */ static u8 get_XP(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u8 frq_xp_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 5, 5, 6, 6, 7, 8, - }; - return frq_xp_map[get_FRQ(tCK, 100) - 7]; - } else { + if (base_freq == 100) + return frq_xp_map[1][get_FRQ(tCK, 100) - 7]; - static const u8 frq_xp_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 3, 4, 4, 5, 6, 7, 8, 8 - }; - return frq_xp_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_xp_map[0][get_FRQ(tCK, 133) - 3]; } /* Get AONPD based on MC frequency */ static u8 get_AONPD(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u8 frq_aonpd_map[] = { - /* FRQ: 7, 8, 9, 10, 11, 12, */ - 6, 8, 8, 9, 10, 11, - }; - return frq_aonpd_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_aonpd_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u8 frq_aonpd_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ - 4, 5, 6, 8, 8, 10, 11, 12, - }; - return frq_aonpd_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_aonpd_map[0][get_FRQ(tCK, 133) - 3]; } /* Get COMP2 based on MC frequency */ static u32 get_COMP2(u32 tCK, u8 base_freq) { - if (base_freq == 100) { - static const u32 frq_comp2_map[] = { - // FRQ: 7, 8, 9, 10, 11, 12, - 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964, 0x0C235924, 0x0C235924, - }; - return frq_comp2_map[get_FRQ(tCK, 100) - 7]; + if (base_freq == 100) + return frq_comp2_map[1][get_FRQ(tCK, 100) - 7]; - } else { - static const u32 frq_comp2_map[] = { - /* FRQ: 3, 4, 5, 6, */ - 0x0D6FF5E4, 0x0CEBDB64, 0x0CA8C264, 0x0C6671E4, - - /* FRQ: 7, 8, 9, 10, */ - 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924, - }; - return frq_comp2_map[get_FRQ(tCK, 133) - 3]; - } + else + return frq_comp2_map[0][get_FRQ(tCK, 133) - 3]; } static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 2ee91e8a48..29b8a7bfec 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -6,6 +6,7 @@ #include #include "raminit_native.h" #include "raminit_common.h" +#include "raminit_tables.h" /* Frequency multiplier */ static u32 get_FRQ(u32 tCK) @@ -23,91 +24,55 @@ static u32 get_FRQ(u32 tCK) /* Get REFI based on MC frequency */ static u32 get_REFI(u32 tCK) { - static const u32 frq_refi_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 3120, 4160, 5200, 6240, 7280, 8320, - }; - return frq_refi_map[get_FRQ(tCK) - 3]; + return frq_refi_map[0][get_FRQ(tCK) - 3]; } /* Get XSOffset based on MC frequency */ static u8 get_XSOffset(u32 tCK) { - static const u8 frq_xs_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 4, 6, 7, 8, 10, 11, - }; - return frq_xs_map[get_FRQ(tCK) - 3]; + return frq_xs_map[0][get_FRQ(tCK) - 3]; } /* Get MOD based on MC frequency */ static u8 get_MOD(u32 tCK) { - static const u8 frq_mod_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 12, 12, 12, 12, 15, 16, - }; - return frq_mod_map[get_FRQ(tCK) - 3]; + return frq_mod_map[0][get_FRQ(tCK) - 3]; } /* Get Write Leveling Output delay based on MC frequency */ static u8 get_WLO(u32 tCK) { - static const u8 frq_wlo_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 4, 5, 6, 6, 8, 8, - }; - return frq_wlo_map[get_FRQ(tCK) - 3]; + return frq_wlo_map[0][get_FRQ(tCK) - 3]; } /* Get CKE based on MC frequency */ static u8 get_CKE(u32 tCK) { - static const u8 frq_cke_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 3, 3, 4, 4, 5, 6, - }; - return frq_cke_map[get_FRQ(tCK) - 3]; + return frq_cke_map[0][get_FRQ(tCK) - 3]; } /* Get XPDLL based on MC frequency */ static u8 get_XPDLL(u32 tCK) { - static const u8 frq_xpdll_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 10, 13, 16, 20, 23, 26, - }; - return frq_xpdll_map[get_FRQ(tCK) - 3]; + return frq_xpdll_map[0][get_FRQ(tCK) - 3]; } /* Get XP based on MC frequency */ static u8 get_XP(u32 tCK) { - static const u8 frq_xp_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 3, 4, 4, 5, 6, 7, - }; - return frq_xp_map[get_FRQ(tCK) - 3]; + return frq_xp_map[0][get_FRQ(tCK) - 3]; } /* Get AONPD based on MC frequency */ static u8 get_AONPD(u32 tCK) { - static const u8 frq_aonpd_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 4, 5, 6, 8, 8, 10, - }; - return frq_aonpd_map[get_FRQ(tCK) - 3]; + return frq_aonpd_map[0][get_FRQ(tCK) - 3]; } /* Get COMP2 based on MC frequency */ static u32 get_COMP2(u32 tCK) { - static const u32 frq_comp2_map[] = { - /* FRQ: 3, 4, 5, 6, 7, 8, */ - 0x0D6BEDCC, 0x0CE7C34C, 0x0CA57A4C, 0x0C6369CC, 0x0C42514C, 0x0C21410C, - }; - return frq_comp2_map[get_FRQ(tCK) - 3]; + return frq_comp2_map[0][get_FRQ(tCK) - 3]; } static void snb_normalize_tclk(u32 *tclk) diff --git a/src/northbridge/intel/sandybridge/raminit_tables.c b/src/northbridge/intel/sandybridge/raminit_tables.c index 1ecba1b935..67dbd2ba14 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.c +++ b/src/northbridge/intel/sandybridge/raminit_tables.c @@ -3,6 +3,111 @@ #include "raminit_tables.h" +const u32 frq_refi_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 3120, 4160, 5200, 6240, 7280, 8320, 9360, 10400, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, N/A, N/A, */ + 5460, 6240, 7020, 7800, 8580, 9360, 0, 0, + }, +}; + +const u8 frq_xs_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 4, 6, 7, 8, 10, 11, 12, 14, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */ + 7, 8, 9, 10, 11, 12, 0, 0, + }, +}; + +const u8 frq_mod_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 12, 12, 12, 12, 15, 16, 18, 20, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */ + 12, 12, 14, 15, 17, 18, 0, 0, + }, +}; + +const u8 frq_wlo_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 4, 5, 6, 6, 8, 8, 9, 10, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */ + 6, 6, 7, 8, 9, 9, 0, 0, + }, +}; + +const u8 frq_cke_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 3, 3, 4, 4, 5, 6, 6, 7, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */ + 4, 4, 5, 5, 6, 6, 0, 0, + }, +}; + +const u8 frq_xpdll_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 10, 13, 16, 20, 23, 26, 29, 32, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */ + 17, 20, 22, 24, 27, 32, 0, 0, + }, +}; + +const u8 frq_xp_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 3, 4, 4, 5, 6, 7, 8, 8, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */ + 5, 5, 6, 6, 7, 8, 0, 0, + }, +}; + +const u8 frq_aonpd_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */ + 4, 5, 6, 8, 8, 10, 11, 12, + }, + { /* 100 MHz */ + /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */ + 6, 8, 8, 9, 10, 11, 0, 0, + }, +}; + +const u32 frq_comp2_map[2][8] = { + { /* 133 MHz */ + /* FRQ: 7, 8, 9, 10, */ + 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964, + + /* FRQ: 11, 12, N/A, N/A, */ + 0x0C235924, 0x0C235924, 0, 0, + }, + { /* 100 MHz */ + /* FRQ: 3, 4, 5, 6, */ + 0x0D6FF5E4, 0x0CEBDB64, 0x0CA8C264, 0x0C6671E4, + + /* FRQ: 7, 8, 9, 10, */ + 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924, + }, +}; + const u32 pattern[32][16] = { {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, diff --git a/src/northbridge/intel/sandybridge/raminit_tables.h b/src/northbridge/intel/sandybridge/raminit_tables.h index 4e225552c3..e5cf589b70 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.h +++ b/src/northbridge/intel/sandybridge/raminit_tables.h @@ -6,6 +6,26 @@ #include +extern const u32 frq_refi_map[2][8]; + +extern const u8 frq_xs_map[2][8]; + +extern const u8 frq_mod_map[2][8]; + +extern const u8 frq_wlo_map[2][8]; + +extern const u8 frq_cke_map[2][8]; + +extern const u8 frq_xpdll_map[2][8]; + +extern const u8 frq_xp_map[2][8]; + +extern const u8 frq_aonpd_map[2][8]; + +extern const u32 frq_comp2_map[2][8]; + + + extern const u32 pattern[32][16]; extern const u8 use_base[63][32]; From 3180af7fd6a86d202c241b02afa9cc4c0b9d9262 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 19 Mar 2020 15:30:06 -0700 Subject: [PATCH 0597/1463] soc/intel/tigerlake: Configure Hyperthreading Configure Hyperthreading based on devicetree BUG=none TEST= Build and boot with FSP log and check Hyperthread setting Signed-off-by: Wonkyu Kim Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 2 ++ src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f82f13d45b..1d4bd5fa5a 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -292,6 +292,8 @@ struct soc_intel_tigerlake_config { */ uint8_t cpu_ratio_override; + /* HyperThreadingDisable : Yes (1) / No (0) */ + uint8_t HyperThreadingDisable; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 95f637e4ec..32f1b031a9 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -143,8 +143,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, else m_cfg->TcssItbtPcie3En = 0; - /* Enable Hyper Threading */ - m_cfg->HyperThreading = 1; + /* Hyper Threading */ + m_cfg->HyperThreading = !config->HyperThreadingDisable; + /* Disable Lock PCU Thermal Management registers */ m_cfg->LockPTMregs = 0; /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ From ebb7f54b1a107816e4f83bc31f1631acb85700d1 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Wed, 19 Feb 2020 15:52:45 +0800 Subject: [PATCH 0598/1463] soc/intel/xeon_sp: Enable LPC generic IO decode range To use Intel common block LPC function that enables the IO ranges defined in devicetree.cb. Tested on OCP Tioga Pass with BMC LPC working. Signed-off-by: Johnny Lin Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994 Reviewed-by: Patrick Georgi Reviewed-by: Jonathan Zhang Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Makefile.inc | 1 + src/soc/intel/xeon_sp/bootblock/bootblock.c | 2 ++ src/soc/intel/xeon_sp/chip.h | 6 ++++++ src/soc/intel/xeon_sp/include/soc/pcr_ids.h | 1 + src/soc/intel/xeon_sp/lpc.c | 23 +++++++++++++++++++++ 5 files changed, 33 insertions(+) diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 3178a4e2bf..59350bf967 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -24,6 +24,7 @@ subdirs-y += ../../../cpu/x86/cache subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm bootblock-y += bootblock/bootblock.c +bootblock-y += lpc.c bootblock-y += spi.c postcar-y += soc_util.c diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index dc88adc308..453c383897 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include #include #include +#include const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -52,6 +53,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); + pch_enable_lpc(); } void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h index 9388ba5407..94726f35eb 100644 --- a/src/soc/intel/xeon_sp/chip.h +++ b/src/soc/intel/xeon_sp/chip.h @@ -76,6 +76,12 @@ struct soc_intel_xeon_sp_config { uint32_t vtd_support; uint32_t coherency_support; uint32_t ats_support; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; extern struct chip_operations soc_intel_xeon_sp_ops; diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index 8d898e6e4e..8d53ab77e2 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -18,5 +18,6 @@ #define PID_ITSS 0xC4 #define PID_RTC 0xC3 +#define PID_DMI 0xEF #endif /* _PCR_IDS_H_ */ diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 4dd6f7c657..6dc2c41fe0 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -16,8 +16,12 @@ #include #include #include +#include #include #include +#include + +#include "chip.h" static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { { 0, 0 } @@ -28,6 +32,25 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) return xeon_lpc_fixed_mmio_ranges; } +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + void lpc_soc_init(struct device *dev) { printk(BIOS_SPEW, "pch: lpc_init\n"); From a956063e5f9c19179e4bacd145e26e159f1982b2 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Wed, 19 Feb 2020 16:13:15 +0800 Subject: [PATCH 0599/1463] mb/ocp/tiogapass: Enable IPMI KCS A bigger than zero value of bmc_boot_timeout must be set for KCS ipmi_get_bmc_self_test_result() to run, otherwise the self test result will be error and won't write SMBIOS type 38 table. Here we set 60 seconds as the maximal self test timeout. Tested=Check if the BMC IPMI response data and SMBIOS type 38 on OCP Tioga Pass are correct or not. Signed-off-by: Johnny Lin Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38995 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/ocp/tiogapass/Kconfig | 1 + src/mainboard/ocp/tiogapass/devicetree.cb | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index b3b43fb20d..9dbc066f10 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 select FSP_CAR + select IPMI_KCS config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 4a5bb1d3f2..c2eddf270c 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -51,6 +51,8 @@ chip soc/intel/xeon_sp register "coherency_support" = "1" register "ats_support" = "1" + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + device cpu_cluster 0 on device lapic 0 on end end @@ -81,7 +83,13 @@ chip soc/intel/xeon_sp device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode] device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1 device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5 - device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.0 on + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller From 9550e97304ecc1c1b6271d50ea089c82b9a82946 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 20 Mar 2020 13:56:46 +0100 Subject: [PATCH 0600/1463] acpi: correct the processor devices scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/family14/acpi/cpu.asl | 4 +-- src/cpu/amd/agesa/family15tn/acpi/cpu.asl | 4 +-- src/cpu/amd/agesa/family16kb/acpi/cpu.asl | 4 +-- src/cpu/amd/pi/00630F01/acpi/cpu.asl | 4 +-- src/cpu/amd/pi/00660F01/acpi/cpu.asl | 4 +-- src/cpu/amd/pi/00730F01/acpi/cpu.asl | 4 +-- src/mainboard/amd/gardenia/dsdt.asl | 2 +- src/mainboard/amd/olivehill/dsdt.asl | 2 +- src/mainboard/amd/padmelon/dsdt.asl | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/thatcher/acpi/cpstate.asl | 2 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/asrock/imb-a180/dsdt.asl | 2 +- src/mainboard/asus/am1i-a/dsdt.asl | 2 +- src/mainboard/asus/f2a85-m/acpi/cpstate.asl | 2 +- src/mainboard/asus/f2a85-m/dsdt.asl | 2 +- src/mainboard/asus/p2b-ls/dsdt.asl | 2 +- src/mainboard/asus/p2b/dsdt.asl | 2 +- src/mainboard/bap/ode_e20XX/dsdt.asl | 2 +- src/mainboard/bap/ode_e21XX/dsdt.asl | 2 +- src/mainboard/biostar/a68n_5200/dsdt.asl | 2 +- src/mainboard/biostar/am1ml/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo2/dsdt.asl | 2 +- src/mainboard/google/kahlee/dsdt.asl | 2 +- src/mainboard/hp/abm/dsdt.asl | 2 +- src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 2 +- src/mainboard/lenovo/g505s/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 4 +-- src/mainboard/lippert/toucan-af/dsdt.asl | 4 +-- src/mainboard/msi/ms7721/acpi/cpstate.asl | 2 +- src/mainboard/msi/ms7721/dsdt.asl | 2 +- src/mainboard/pcengines/apu2/dsdt.asl | 2 +- .../amd/agesa/family14/northbridge.c | 18 +++++++++++ .../amd/agesa/family15tn/northbridge.c | 16 ++++++++++ .../amd/agesa/family16kb/northbridge.c | 16 ++++++++++ src/northbridge/amd/pi/00630F01/northbridge.c | 16 ++++++++++ src/northbridge/amd/pi/00660F01/northbridge.c | 16 ++++++++++ src/northbridge/amd/pi/00730F01/northbridge.c | 16 ++++++++++ src/soc/amd/picasso/acpi.c | 6 ++-- src/soc/amd/picasso/acpi/cpu.asl | 22 +++++++------- src/soc/amd/picasso/southbridge.c | 2 +- src/soc/amd/stoneyridge/acpi.c | 6 ++-- src/soc/amd/stoneyridge/acpi/cpu.asl | 30 +++++++++---------- src/soc/amd/stoneyridge/northbridge.c | 17 +++++++++++ src/soc/amd/stoneyridge/southbridge.c | 2 +- 45 files changed, 189 insertions(+), 74 deletions(-) diff --git a/src/cpu/amd/agesa/family14/acpi/cpu.asl b/src/cpu/amd/agesa/family14/acpi/cpu.asl index 98b0193c77..b10fd56120 100644 --- a/src/cpu/amd/agesa/family14/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family14/acpi/cpu.asl @@ -15,7 +15,7 @@ * Processor Object * */ -Scope (\_PR) { /* define processor scope */ +Scope (\_SB) { /* define processor scope */ Device (C000) { Name (_HID, "ACPI0007") @@ -26,4 +26,4 @@ Scope (\_PR) { /* define processor scope */ Name (_HID, "ACPI0007") Name (_UID, 1) } -} /* End _PR scope */ +} /* End _SB scope */ diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl index 68e6e97bf3..19ec12b1ec 100644 --- a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl @@ -15,7 +15,7 @@ * Processor Object * */ -Scope (\_PR) { /* define processor scope */ +Scope (\_SB) { /* define processor scope */ Device (P000) { Name(_HID, "ACPI0007") @@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */ Name(_HID, "ACPI0007") Name(_UID, 7) } -} /* End _PR scope */ +} /* End _SB scope */ diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl index 37eb58abc0..48505ebddf 100644 --- a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -15,7 +15,7 @@ * Processor Object * */ -Scope (\_PR) {/* define processor scope */ +Scope (\_SB) {/* define processor scope */ Device (P000) { Name(_HID, "ACPI0007") Name(_UID, 0) @@ -55,4 +55,4 @@ Scope (\_PR) {/* define processor scope */ Name(_HID, "ACPI0007") Name(_UID, 7) } -} /* End _PR scope */ +} /* End _SB scope */ diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl index 68e6e97bf3..19ec12b1ec 100644 --- a/src/cpu/amd/pi/00630F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl @@ -15,7 +15,7 @@ * Processor Object * */ -Scope (\_PR) { /* define processor scope */ +Scope (\_SB) { /* define processor scope */ Device (P000) { Name(_HID, "ACPI0007") @@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */ Name(_HID, "ACPI0007") Name(_UID, 7) } -} /* End _PR scope */ +} /* End _SB scope */ diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl index 68e6e97bf3..19ec12b1ec 100644 --- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00660F01/acpi/cpu.asl @@ -15,7 +15,7 @@ * Processor Object * */ -Scope (\_PR) { /* define processor scope */ +Scope (\_SB) { /* define processor scope */ Device (P000) { Name(_HID, "ACPI0007") @@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */ Name(_HID, "ACPI0007") Name(_UID, 7) } -} /* End _PR scope */ +} /* End _SB scope */ diff --git a/src/cpu/amd/pi/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl index 68e6e97bf3..19ec12b1ec 100644 --- a/src/cpu/amd/pi/00730F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00730F01/acpi/cpu.asl @@ -15,7 +15,7 @@ * Processor Object * */ -Scope (\_PR) { /* define processor scope */ +Scope (\_SB) { /* define processor scope */ Device (P000) { Name(_HID, "ACPI0007") @@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */ Name(_HID, "ACPI0007") Name(_UID, 7) } -} /* End _PR scope */ +} /* End _SB scope */ diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index f1a49ef5c9..6ecea61936 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -39,7 +39,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index a7914191d0..15b241f897 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index e39ce0c836..0e45e0784d 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -37,7 +37,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index 14a38c23bf..459d18f05f 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Describe the supported Sleep States for this Southbridge */ diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl index c88aa64bcf..4a49f6baf2 100644 --- a/src/mainboard/amd/thatcher/acpi/cpstate.asl +++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl @@ -21,7 +21,7 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { + Scope (\_SB) { Device (CPU0) { Name (_HID, "ACPI0007") Name (_UID, 0) diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index 14a38c23bf..459d18f05f 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Describe the supported Sleep States for this Southbridge */ diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index a7914191d0..15b241f897 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index fcae00b660..2d55f7cf58 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl index c88aa64bcf..4a49f6baf2 100644 --- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -21,7 +21,7 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { + Scope (\_SB) { Device (CPU0) { Name (_HID, "ACPI0007") Name (_UID, 0) diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index ad9ce1bc21..f34ccc8244 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Describe the supported Sleep States for this Southbridge */ diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 938caa5a7c..c79b78649f 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -23,7 +23,7 @@ #include DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) { - /* \_PR scope defining the main processor is generated in SSDT. */ + /* \_SB scope defining the main processor is generated in SSDT. */ OperationRegion(X80, SystemIO, 0x80, 1) Field(X80, ByteAcc, NoLock, Preserve) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index c67e50fd79..b52b456983 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -23,7 +23,7 @@ #include DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) { - /* \_PR scope defining the main processor is generated in SSDT. */ + /* \_SB scope defining the main processor is generated in SSDT. */ OperationRegion(X80, SystemIO, 0x80, 1) Field(X80, ByteAcc, NoLock, Preserve) diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index a7914191d0..15b241f897 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl index 4bf4dc8276..8440ecaa0f 100644 --- a/src/mainboard/bap/ode_e21XX/dsdt.asl +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index a7914191d0..15b241f897 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index 907b2d172d..f454732858 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index a7914191d0..15b241f897 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 7e83f06710..574145f4e5 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index a7914191d0..15b241f897 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index 224dd14d18..7b47a7646a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Describe the supported Sleep States for this Southbridge */ diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index b36a1de71d..4eb466f819 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Describe the supported Sleep States for this Southbridge */ diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index bf166c67af..8efa56f816 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -56,7 +56,7 @@ DefinitionBlock ( * Processor Object * */ - Scope (\_PR) { /* define processor scope */ + Scope (\_SB) { /* define processor scope */ Device (C000) { Name (_HID, "ACPI0007") Name (_UID, 0) @@ -73,7 +73,7 @@ DefinitionBlock ( Name (_HID, "ACPI0007") Name (_UID, 3) } - } /* End _PR scope */ + } /* End _SB scope */ /* PIC IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index cc2a48ed5e..c494d7060c 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -56,7 +56,7 @@ DefinitionBlock ( * Processor Object * */ - Scope (\_PR) { /* define processor scope */ + Scope (\_SB) { /* define processor scope */ Device (C000) { Name (_HID, "ACPI0007") Name (_UID, 0) @@ -73,7 +73,7 @@ DefinitionBlock ( Name (_HID, "ACPI0007") Name (_UID, 3) } - } /* End _PR scope */ + } /* End _SB scope */ /* PIC IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) diff --git a/src/mainboard/msi/ms7721/acpi/cpstate.asl b/src/mainboard/msi/ms7721/acpi/cpstate.asl index c88aa64bcf..4a49f6baf2 100644 --- a/src/mainboard/msi/ms7721/acpi/cpstate.asl +++ b/src/mainboard/msi/ms7721/acpi/cpstate.asl @@ -21,7 +21,7 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { + Scope (\_SB) { Device (CPU0) { Name (_HID, "ACPI0007") Name (_UID, 0) diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index d10d953f8e..ceac618519 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Describe the supported Sleep States for this Southbridge */ diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 9d6138a844..cbc7293e80 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include /* Contains the supported sleep states for this chipset */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4086173d7e..1ac5a69cf9 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -710,6 +710,21 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -774,6 +789,9 @@ static unsigned long agesa_write_acpi_tables(struct device *device, printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { + hexdump(ssdt, ssdt->length); + patch_ssdt_processor_scope(ssdt); + hexdump(ssdt, ssdt->length); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 642fc150e1..a62e12e772 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -449,6 +449,21 @@ static void northbridge_fill_ssdt_generator(struct device *device) acpigen_pop_len(); } +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -525,6 +540,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index fcd7ec1fe6..2cdcb58023 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -449,6 +449,21 @@ static void northbridge_fill_ssdt_generator(struct device *device) acpigen_pop_len(); } +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -525,6 +540,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 28502b0017..e90848a36b 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -447,6 +447,21 @@ static void northbridge_fill_ssdt_generator(struct device *device) acpigen_pop_len(); } +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -521,6 +536,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 0a1b0ba1a4..200508617c 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -435,6 +435,21 @@ static void northbridge_fill_ssdt_generator(struct device *device) acpigen_pop_len(); } +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -511,6 +526,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index c87d8fffba..f611bd6e3e 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -671,6 +671,21 @@ static void northbridge_fill_ssdt_generator(struct device *device) acpigen_pop_len(); } +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -741,6 +756,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index e8bbf57fab..8ee7c97b6c 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -236,13 +236,13 @@ void generate_cpu_entries(struct device *device) int cores, cpu; cores = get_cpu_count(); - printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); + printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); - /* Generate BSP \_PR.P000 */ + /* Generate BSP \_SB.P000 */ acpigen_write_processor(0, ACPI_GPE0_BLK, 6); acpigen_pop_len(); - /* Generate AP \_PR.Pxxx */ + /* Generate AP \_SB.Pxxx */ for (cpu = 1; cpu < cores; cpu++) { acpigen_write_processor(cpu, 0, 0); acpigen_pop_len(); diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 59ac62e1ec..587dbea18c 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -21,14 +21,14 @@ Method (PNOT) * Processor Object */ /* These devices are created at runtime */ -External (\_PR.P000, DeviceObj) -External (\_PR.P001, DeviceObj) -External (\_PR.P002, DeviceObj) -External (\_PR.P003, DeviceObj) -External (\_PR.P004, DeviceObj) -External (\_PR.P005, DeviceObj) -External (\_PR.P006, DeviceObj) -External (\_PR.P007, DeviceObj) +External (\_SB.P000, DeviceObj) +External (\_SB.P001, DeviceObj) +External (\_SB.P002, DeviceObj) +External (\_SB.P003, DeviceObj) +External (\_SB.P004, DeviceObj) +External (\_SB.P005, DeviceObj) +External (\_SB.P006, DeviceObj) +External (\_SB.P007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) @@ -36,13 +36,13 @@ Method (PPKG) If (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.P000, - \_PR.P001 + \_SB.P000, + \_SB.P001 }) } Else { Return (Package () { - \_PR.P000 + \_SB.P000 }) } } diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 1894bea418..61c7f36c07 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -367,7 +367,7 @@ static void sb_init_acpi_ports(void) pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CP00, 6 bytes */ + /* CpuControl is in \_SB.CP00, 6 bytes */ cst_addr.hi = 0; cst_addr.lo = ACPI_CPU_CONTROL; wrmsr(CSTATE_BASE_REG, cst_addr); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 01849b85a0..f59aeb504a 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -241,13 +241,13 @@ void generate_cpu_entries(struct device *device) cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK; cores++; /* number of cores is CmpCap+1 */ - printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); + printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); - /* Generate BSP \_PR.P000 */ + /* Generate BSP \_SB.P000 */ acpigen_write_processor(0, ACPI_GPE0_BLK, 6); acpigen_pop_len(); - /* Generate AP \_PR.Pxxx */ + /* Generate AP \_SB.Pxxx */ for (cpu = 1; cpu < cores; cpu++) { acpigen_write_processor(cpu, 0, 0); acpigen_pop_len(); diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index f52d230bf2..1ecde23f7a 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -21,14 +21,14 @@ Method (PNOT) * Processor Object */ /* These devices are created at runtime */ -External (\_PR.P000, DeviceObj) -External (\_PR.P001, DeviceObj) -External (\_PR.P002, DeviceObj) -External (\_PR.P003, DeviceObj) -External (\_PR.P004, DeviceObj) -External (\_PR.P005, DeviceObj) -External (\_PR.P006, DeviceObj) -External (\_PR.P007, DeviceObj) +External (\_SB.P000, DeviceObj) +External (\_SB.P001, DeviceObj) +External (\_SB.P002, DeviceObj) +External (\_SB.P003, DeviceObj) +External (\_SB.P004, DeviceObj) +External (\_SB.P005, DeviceObj) +External (\_SB.P006, DeviceObj) +External (\_SB.P007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) @@ -36,21 +36,21 @@ Method (PPKG) If (LGreaterEqual (\PCNT, 4)) { Return (Package () { - \_PR.P000, - \_PR.P001, - \_PR.P002, - \_PR.P003 + \_SB.P000, + \_SB.P001, + \_SB.P002, + \_SB.P003 }) } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.P000, - \_PR.P001 + \_SB.P000, + \_SB.P001 }) } Else { Return (Package () { - \_PR.P000 + \_SB.P000 }) } } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index afe7cf0420..3707049130 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -227,6 +227,22 @@ static void northbridge_fill_ssdt_generator(struct device *device) acpigen_pop_len(); } +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + + static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -322,6 +338,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *)current; current += ssdt->length; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 71b2d90a2c..b636c26699 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -488,7 +488,7 @@ static void sb_init_acpi_ports(void) pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CP00, 6 bytes */ + /* CpuControl is in \_SB.CP00, 6 bytes */ pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); if (CONFIG(HAVE_SMI_HANDLER)) { From 2e4bc06b49b413d7524d748cc1626b1737dfd7d1 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 19 Mar 2020 14:52:03 -0600 Subject: [PATCH 0601/1463] drivers/usb/acpi: Add needed #include file The chip.h for this driver was updated to add a reset GPIO, but did not add the required #include of . This likely still compiled because other chip.h files included before it may have included it themselves. Signed-off-by: Tim Wawrzynczak Change-Id: I13200f7347fd17739a377e8ad0906ab7e5d6ae1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39677 Reviewed-by: EricR Lai Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/usb/acpi/chip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index bce73c6755..79033bbf4e 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -14,6 +14,7 @@ #ifndef __USB_ACPI_CHIP_H__ #define __USB_ACPI_CHIP_H__ +#include #include #include From ba5062d78b8f3453d918a9096f08bfe393fd5922 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 27 Feb 2020 19:40:32 +0530 Subject: [PATCH 0602/1463] mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39195 Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/board_id.c | 9 +- .../jasperlake_rvp/romstage_fsp_params.c | 34 ++++- .../intel/jasperlake_rvp/spd/Makefile.inc | 4 +- .../intel/jasperlake_rvp/spd/jslrvp.spd.hex | 32 +++++ .../baseboard/include/baseboard/variants.h | 8 ++ .../variants/jslrvp/Makefile.inc | 2 +- .../jasperlake_rvp/variants/jslrvp/memory.c | 118 ++++++++++++++++++ 7 files changed, 197 insertions(+), 10 deletions(-) create mode 100644 src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex create mode 100644 src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.c b/src/mainboard/intel/jasperlake_rvp/board_id.c index 1913d3f0fc..09d73cb9c3 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.c +++ b/src/mainboard/intel/jasperlake_rvp/board_id.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +30,10 @@ static uint32_t get_board_id_via_ext_ec(void) return id; } -/* Get Board ID via EC I/O port write/read */ +/* + * Get Board ID via EC I/O port write/read + * Board id is 5 bit, so mask other bits while returning board id. + */ int get_board_id(void) { MAYBE_STATIC_NONZERO int id = -1; @@ -47,5 +51,6 @@ int get_board_id(void) } } } - return id; + + return (id & 0x1f); } diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index b072a9099d..8858e44616 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,11 +12,36 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include +#include +#include +#include #include +#include "board_id.h" -void mainboard_memory_init_params(FSPM_UPD *mupd) +void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* ToDo : Fill FSP-M memory params */ + static struct spd_info jslrvp_spd_info; + uint8_t board_id = get_board_id(); + const struct mb_cfg *board_cfg = variant_memcfg_config(board_id); + + /* TODO: Read the resistor strap to get number of memory segments */ + bool half_populated = false; + + /* Check board id and fill correct parameters to upd */ + if (board_id == jsl_ddr4) { + /* Initialize spd information for DDR4 board */ + jslrvp_spd_info.read_type = READ_SMBUS; + jslrvp_spd_info.spd_spec.spd_smbus_address[0] = 0xA0; + jslrvp_spd_info.spd_spec.spd_smbus_address[1] = 0xA2; + jslrvp_spd_info.spd_spec.spd_smbus_address[2] = 0xA4; + jslrvp_spd_info.spd_spec.spd_smbus_address[3] = 0xA6; + + } else if (board_id == jsl_lpddr4) { + /* Initialize spd information for LPDDR4 board */ + jslrvp_spd_info.read_type = READ_SPD_CBFS; + jslrvp_spd_info.spd_spec.spd_index = 0x00; + } + + /* Initialize variant specific configurations */ + memcfg_init(&memupd->FspmConfig, board_cfg, &jslrvp_spd_info, half_populated); } diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index 4cde260d52..2909281463 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -12,8 +12,6 @@ ## GNU General Public License for more details. ## -romstage-y += spd_util.c - SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b000 +SPD_SOURCES = jslrvp # 0b000 diff --git a/src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex b/src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex new file mode 100644 index 0000000000..a27c249d33 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B0 08 00 40 00 00 0A 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index 6beef66559..27c645bbde 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,14 +17,21 @@ #define __BASEBOARD_VARIANTS_H__ #include +#include #include #include +enum jsl_board_id { + jsl_ddr4 = 1, + jsl_lpddr4 = 4, +}; + /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +const struct mb_cfg *variant_memcfg_config(uint8_t board_id); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc index 9d44bb02d0..885a1722e3 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc @@ -13,5 +13,5 @@ ## bootblock-y += gpio.c - +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c new file mode 100644 index 0000000000..1915a1e1ff --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {0, 0, 0, 0, 0}, + + /* Disable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg jslrvp_lpddr4_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {0, 3, 2, 1, 7, 5, 4, 6}, + .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 7, 6, 5}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {80, 40, 40, 40, 30}, + + /* Disable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_ULT_ULX, +}; + +const struct mb_cfg *variant_memcfg_config(uint8_t board_id) +{ + if (board_id == jsl_ddr4) + return &jslrvp_ddr4_memcfg_cfg; + else if (board_id == jsl_lpddr4) + return &jslrvp_lpddr4_memcfg_cfg; + + die("unsupported board id : 0x%x\n", board_id); +} From 26dc8f2c4e7634b4298e13e4e26aab3109252d13 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 7 Mar 2020 12:31:17 +0100 Subject: [PATCH 0603/1463] soc/intel/cometlake: Use IntelFSP repo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make use of the publicly-available FSP binaries and headers for Comet Lake. Also, remove the Comet Lake header files from src/vendorcode, since they are no longer necessary. Change-Id: I392cc7ee3bf5aa21753efd6eab4abd643b65ff94 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39372 Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Kconfig | 2 +- src/soc/intel/cannonlake/Kconfig | 3 +- .../fsp2_0/cometlake/FirmwareVersionInfoHob.h | 68 - .../intel/fsp/fsp2_0/cometlake/FspUpd.h | 48 - .../intel/fsp/fsp2_0/cometlake/FspmUpd.h | 3019 -------------- .../intel/fsp/fsp2_0/cometlake/FspsUpd.h | 3666 ----------------- .../intel/fsp/fsp2_0/cometlake/FsptUpd.h | 186 - .../intel/fsp/fsp2_0/cometlake/MemInfoHob.h | 274 -- 8 files changed, 3 insertions(+), 7263 deletions(-) delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/cometlake/FirmwareVersionInfoHob.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/cometlake/MemInfoHob.h diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 2624644fae..cf79201db6 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -56,7 +56,7 @@ config FSP_USE_REPO depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \ - SOC_INTEL_DENVERTON_NS + SOC_INTEL_DENVERTON_NS || SOC_INTEL_COMETLAKE help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7474148db4..1495e2e1bb 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -309,13 +309,14 @@ endchoice config FSP_HEADER_PATH string "Location of FSP headers" default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE - default "src/vendorcode/intel/fsp/fsp2_0/cometlake/" if SOC_INTEL_COMETLAKE + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE config FSP_FD_PATH string depends on FSP_USE_REPO default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FirmwareVersionInfoHob.h deleted file mode 100644 index 98a16d7752..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,68 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
- - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h deleted file mode 100644 index c96f171336..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4D43 /* 'CMLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4D43 /* 'CMLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4D43 /* 'CMLUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h deleted file mode 100644 index 962463e425..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h +++ /dev/null @@ -1,3019 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResistor settings - Indicates RcompResistor settings: CML - 0's means MRC auto configured based on - Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to - provide the appropriate values. -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, - otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - Time Measure - Time Measure: 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0096 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0097 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0098 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0099 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x009C - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x00A0 - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A4 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A6 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A7 - GDXC IOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcIotSize; - -/** Offset 0x00A8 - GDXC MOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcMotSize; - -/** Offset 0x00A9 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00AD - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00AE - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00AF - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 2:512 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00B0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00B1 - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00B2 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, - i.e. divide by 133 or 100 - 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, - 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00B4 - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00B6 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00B7 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00B8 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00B9 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00BA - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x00BB - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00BC - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00BD -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x00BE - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00C0 - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00C1 - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x00C2 - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00C3 - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00C4 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00C5 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00C6 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00C8 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00CA - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00CC - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00CE - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00CF - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00D0 - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00D1 - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00D2 - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00D3 - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00D4 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00D5 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00D6 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00D7 - Margin Limit Check - Margin Limit Check. Choose level of margin check - 0:Disable, 1:L1, 2:L2, 3:Both -**/ - UINT8 MarginLimitCheck; - -/** Offset 0x00D8 - Margin Limit L2 - % of L1 check for margin limit check -**/ - UINT16 MarginLimitL2; - -/** Offset 0x00DA - CPU Trace Hub Mode - Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' - trace hub functionality. - 0: Disable, 1:Target Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x00DB - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x00DC - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x00DD - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message - to disable peci reset on C10 exit. The default value is 0: Disable for CNL, - and 1: Enable for all other CPU's - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x00DE - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x00DF - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x00E0 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x00E4 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x00E8 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x00EC - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x00EE - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x00F0 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x00F3 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x00F4 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x00F5 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x00F6 - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x00F7 - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x00F8 - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x00F9 - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x00FA - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x00FB - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x00FC - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x00FD - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x00FE - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x00FF - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0100 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0101 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0102 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0105 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x010D - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0115 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0122 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x012D -**/ - UINT8 UnusedUpdSpace2[3]; - -/** Offset 0x0130 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0134 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0154 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0155 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0156 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x0158 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x015C - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0160 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3 - Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x01C1 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x01C2 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x01C3 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x01C4 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x01C5 -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x01C6 - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01CA - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01CC - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01CF - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01D0 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01D1 - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01D2 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01D3 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x01D4 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x01DA - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x01DB - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[3]; - -/** Offset 0x01DE - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x01E0 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x01E1 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x01E2 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x01E3 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x01E4 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x01E5 - Program Cache Attributes - Program Cache Attributes; 0: Program; 1: Disable Program. - $EN_DIS -**/ - UINT8 DisableMtrrProgram; - -/** Offset 0x01E6 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x01E7 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x01E8 - CPU ratio value - CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. -**/ - UINT8 CpuRatio; - -/** Offset 0x01E9 - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x01EA - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x01EC - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x01ED - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x01EE - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x01EF - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x01F0 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x01F1 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x01F2 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x01F4 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x01F6 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x01F8 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x01F9 - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x01FA - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x01FC - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x01FE - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x0200 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0201 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x0202 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x0203 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x0204 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x0205 -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0208 - PrmrrSize - 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 -**/ - UINT32 PrmrrSize; - -/** Offset 0x020C - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x0210 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0214 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x0218 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x0220 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0224 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0228 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x022C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0230 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0238 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0240 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0241 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[3]; - -/** Offset 0x0244 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[3]; - -/** Offset 0x0250 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x0251 - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] - have the same setting - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC) -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x0252 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x0253 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x0254 - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x0255 - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x0256 - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x0257 - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x0258 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x0270 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x0288 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x02A0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x02B8 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x02D0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x02E8 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x0300 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x0318 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x0330 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0348 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x0360 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0378 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x0390 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x03A8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x03B0 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x03B8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x03C0 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x03C8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x03D0 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x03D8 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x03E0 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x03E8 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x03F0 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x03F8 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0400 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0408 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0410 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0418 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0420 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0428 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0430 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0438 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0439 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x043A - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x043B - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x043C - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x043E - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x0440 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x0444 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0448 - Enable PCIe IMR - 0:Disable, 1:Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x0449 - Root port number for IMR. - Root port number for IMR. -**/ - UINT8 ImrRpSelection; - -/** Offset 0x044A - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x044B - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x044C - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x044D - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x044E -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0450 - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x0454 - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x0455 - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x0456 - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x0457 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0458 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x045A - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x045B - Enable HD Audio DMIC0 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x045C - Enable HD Audio DMIC1 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x045D - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x045E - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x045F - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x0465 - ReservedPchPreMem - Reserved for Pch Pre-Mem - $EN_DIS -**/ - UINT8 ReservedPchPreMem[2]; - -/** Offset 0x0467 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0468 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0469 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x046A - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x046B - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x046C - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x046D - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x046E - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x046F - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x0470 - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x0471 - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x0472 - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x0473 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x0474 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0475 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0476 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0477 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0478 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x0479 - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x047A - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x047B - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x047C - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x047D - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x047E - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x047F - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x0480 - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x0481 - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x0482 - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x0483 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x0484 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0485 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0486 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0487 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0488 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x0489 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x048A - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x048B - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x048C - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x048D - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x048E - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x048F - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x0490 - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x0491 - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x0492 - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x0493 - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x0494 - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x0495 - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x0496 - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x0497 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x0498 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x0499 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x049A - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x049B - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x049C - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x049D - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x049E - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x049F - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x04A0 - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x04A1 - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x04A2 - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x04A3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x04A4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x04A5 -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x04A6 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6 -**/ - UINT16 ChHashMask; - -/** Offset 0x04A8 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x04AC - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x04AD - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x04AE - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x04B0 - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x04B2 - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x04B3 - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x04B4 - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x04B5 - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x04B6 - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x04B7 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x04B8 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x04B9 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x04BA - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x04BB -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x04BC - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (222= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x04BE - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (0= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x04C0 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x04C1 - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x04C2 - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x04C3 - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x04C4 - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x04C5 - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x04C6 - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x04C7 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x04C8 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x04C9 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x04CA - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x04CB - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x04CC - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x04CD - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x04CE - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x04CF - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x04D0 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x04D1 - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x04D2 - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x04D3 - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x04D4 - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x04D5 - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x04D6 - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x04D7 - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x04D8 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x04D9 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x04DA - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x04DB - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x04DC - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x04DD - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x04DE - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x04DF - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x04E0 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x04E1 - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x04E2 - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x04E3 - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x04E4 - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Default is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x04E5 - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x04E6 - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x04E7 - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x04E8 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x04E9 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x04EA - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x04EB - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x04EC - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x04ED - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x04EE - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x04EF - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x04F0 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x04F1 - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x04F2 - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x04F3 - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x04F4 - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x04F5 - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x04F6 - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x04F7 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x04F8 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x04F9 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x04FA - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x04FB - GDXC MOT enable - GDXC MOT enable. - $EN_DIS -**/ - UINT8 GdxcEnable; - -/** Offset 0x04FC - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x04FD - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x04FE - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x04FF - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x0500 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x0501 - LpDdrDqDqsReTraining - Enables/Disable LpDdrDqDqsReTraining - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x0502 - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x0504 - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x0505 - BER Support - Enable/Disable the Rank Margin Tool interpolation/extrapolation. - 0:Disable, 1:Enable -**/ - UINT8 EnBER; - -/** Offset 0x0506 - Dual Dimm Per-Channel Board Type - Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used - to limit maximum frequency for some SKUs. - 0:1DPC, 1:2DPC -**/ - UINT8 DualDimmPerChannelBoardType; - -/** Offset 0x0507 - DDR4 Mixed U-DIMM 2DPC Limitation - Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. - Disable=0, Enable(Default)=1 - $EN_DIS -**/ - UINT8 Ddr4MixedUDimm2DpcLimit; - -/** Offset 0x0508 - CFL Reserved - Reserved FspmConfig CFL - $EN_DIS -**/ - UINT8 ReservedFspmUpdCfl[2]; - -/** Offset 0x050A - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x050B - Throttler CKEMin Timer - LPDDR - Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + - BYTE_LENGTH (4). Default is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x050C - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x050D - MRC Force training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x050E - Lpddr Dram Odt - Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO) - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 LpddrDramOdt; - -/** Offset 0x050F - DDR4 Skip Refresh Enable - Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled) - 0:Disable, 1:Enable -**/ - UINT8 Ddr4SkipRefreshEn; - -/** Offset 0x0510 - SerialDebugMrcLevel - MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 SerialDebugMrcLevel; - -/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control - deprecated -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x0515 -**/ - UINT8 UnusedUpdSpace8[2]; - -/** Offset 0x0517 -**/ - UINT8 ReservedFspmUpd[1]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0518 -**/ - UINT32 Signature; - -/** Offset 0x051C - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x051D - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x051E - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x051F - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0520 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0521 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x0522 - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x0523 - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x0524 - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x0525 - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x0526 - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x0527 - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0528 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0529 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x052A - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x052B - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x052C - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x052D - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x052E - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x052F - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0530 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0531 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x0532 - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x0533 - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x0534 - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x0535 - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x0549 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x055D - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x0571 -**/ - UINT8 UnusedUpdSpace9; - -/** Offset 0x0572 - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x0574 - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x0576 - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x0578 - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x057A - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x057B - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Margin Tool, 1:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x057C - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x057D -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x057E - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelayPreMem; - -/** Offset 0x0580 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[9]; - -/** Offset 0x0589 -**/ - UINT8 UnusedUpdSpace11; - -/** Offset 0x058A - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x058C - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x058E - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x058F - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[3]; - -/** Offset 0x0592 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x0593 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x0594 - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x0595 - ReservedPchPreMemTest - Reserved for Pch Pre-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPreMemTest[16]; - -/** Offset 0x05A5 - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x05A6 - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x05A7 - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05A8 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05A9 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05AA - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05AB - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05AC - tRd2RdSG - Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdSG; - -/** Offset 0x05AD - tRd2RdDG - Delay between Read-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDG; - -/** Offset 0x05AE - tRd2RdDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDR; - -/** Offset 0x05AF - tRd2RdDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDD; - -/** Offset 0x05B0 - tWr2RdSG - Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. -**/ - UINT8 tWr2RdSG; - -/** Offset 0x05B1 - tWr2RdDG - Delay between Write-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDG; - -/** Offset 0x05B2 - tWr2RdDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDR; - -/** Offset 0x05B3 - tWr2RdDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDD; - -/** Offset 0x05B4 - tWr2WrSG - Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrSG; - -/** Offset 0x05B5 - tWr2WrDG - Delay between Write-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDG; - -/** Offset 0x05B6 - tWr2WrDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDR; - -/** Offset 0x05B7 - tWr2WrDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDD; - -/** Offset 0x05B8 - tRd2WrSG - Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrSG; - -/** Offset 0x05B9 - tRd2WrDG - Delay between Read-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDG; - -/** Offset 0x05BA - tRd2WrDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDR; - -/** Offset 0x05BB - tRd2WrDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDD; - -/** Offset 0x05BC - tRRD_L - Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 -**/ - UINT8 tRRD_L; - -/** Offset 0x05BD - tRRD_S - Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: - AUTO, max: 31 -**/ - UINT8 tRRD_S; - -/** Offset 0x05BE - tWTR_L - Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: - AUTO, max: 60 -**/ - UINT8 tWTR_L; - -/** Offset 0x05BF - tWTR_S - Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. - 0: AUTO, max: 28 -**/ - UINT8 tWTR_S; - -/** Offset 0x05C0 -**/ - UINT8 ReservedFspmTestUpd[8]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0518 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x05C8 -**/ - UINT8 UnusedUpdSpace12[6]; - -/** Offset 0x05CE -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h deleted file mode 100644 index f56cba9b5c..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ /dev/null @@ -1,3666 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0030 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0034 - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0038 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0039 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x003A - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x003B - HECI1 state - Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 Heci1Disabled; - -/** Offset 0x003C - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x003D - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 WatchDogEnabled; - -/** Offset 0x003E - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x003F - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x0040 - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. - Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x0041 -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x0042 - OS Timer - 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x0044 - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x0046 - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0047 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0048 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x0049 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x004A - DMI ASPM - 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 - 0:Disable, 1:L0s, 2:L1, 3:L0sL1 -**/ - UINT8 DmiAspm; - -/** Offset 0x004B - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x004F - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x0053 - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x0057 -**/ - UINT8 UnusedUpdSpace2[1]; - -/** Offset 0x0058 - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x0060 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0061 - CdClock Frequency selection - 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz - 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0063 - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOutDeprecated; - -/** Offset 0x0065 -**/ - UINT8 UnusedUpdSpace3[3]; - -/** Offset 0x0068 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddressDeprecated[3]; - -/** Offset 0x0074 - Enable or disable eDP device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortEdp; - -/** Offset 0x0075 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x0076 - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x0077 - Enable or disable HPD of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDHpd; - -/** Offset 0x0078 - Enable or disable HPD of DDI port F - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortFHpd; - -/** Offset 0x0079 - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x007A - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x007B - Enable or disable DDC of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDDdc; - -/** Offset 0x007C - Enable or disable DDC of DDI port F - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortFDdc; - -/** Offset 0x007D - Enable/Disable SkipS3CdClockInit - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock in S3 resume due to GOP absent - $EN_DIS -**/ - UINT8 SkipS3CdClockInit; - -/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms - DEPRECATED - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelay; - -/** Offset 0x0080 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0084 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x0088 - Program GT Chicken bits - Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] -**/ - UINT8 ProgramGtChickenBits; - -/** Offset 0x0089 - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[34]; - -/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for - Alpine ridge -**/ - UINT8 PcieRootPortGen2PllL1CgDisable[24]; - -/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x00C4 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x00C9 - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x00CE - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x00D3 - Imon offset correction - DEPRECATED -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x00DD - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x00E2 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x00E7 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x00EC - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x00ED - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x00EE - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x00F3 -**/ - UINT8 UnusedUpdSpace4[1]; - -/** Offset 0x00F4 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x00FE - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x0108 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x0112 - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x011C - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x0126 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x0130 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x013A - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x0146 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x0147 - Reserved - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x0148 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization - @deprecated SkipMpInit has been moved to FspmUpd - $EN_DIS -**/ - UINT8 SkipMpInitDeprecated; - -/** Offset 0x014A - McIVR RFI Frequency Prefix - PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: - Minus (-). -**/ - UINT8 McivrRfiFrequencyPrefix; - -/** Offset 0x014B - McIVR RFI Frequency Adjustment - PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in - increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. -**/ - UINT8 McivrRfiFrequencyAdjust; - -/** Offset 0x014C - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x014E - McIVR RFI Spread Spectrum - PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- - 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. -**/ - UINT8 McivrSpreadSpectrum; - -/** Offset 0x014F - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x0152 -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0154 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x0159 -**/ - UINT8 UnusedUpdSpace6[1]; - -/** Offset 0x015A - Imon slope1 correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope1[5]; - -/** Offset 0x0164 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0168 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0169 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x016A - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x016B -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x016C - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x0170 - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0174 - Enable or Disable processor debug features - Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0175 -**/ - UINT8 UnusedUpdSpace8[1]; - -/** Offset 0x0176 - Imon offset 1 correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset1[5]; - -/** Offset 0x0180 - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS -**/ - UINT8 ReservedCpuPostMemProduction[8]; - -/** Offset 0x0188 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0189 - SPI0 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi0CsPolarity[2]; - -/** Offset 0x018B - SPI1 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi1CsPolarity[2]; - -/** Offset 0x018D - SPI2 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi2CsPolarity[2]; - -/** Offset 0x018F - SPI0 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi0CsEnable[2]; - -/** Offset 0x0191 - SPI1 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi1CsEnable[2]; - -/** Offset 0x0193 - SPI2 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi2CsEnable[2]; - -/** Offset 0x0195 - SPIn Device Mode - Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available - modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden -**/ - UINT8 SerialIoSpiMode[3]; - -/** Offset 0x0198 - SPIn Default Chip Select Output - Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available - options: 0:CS0, 1:CS1 -**/ - UINT8 SerialIoSpiDefaultCsOutput[3]; - -/** Offset 0x019B - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 - pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 - for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[6]; - -/** Offset 0x01A1 - I2Cn Device Mode - Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available - modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden -**/ - UINT8 SerialIoI2cMode[6]; - -/** Offset 0x01A7 - UARTn Device Mode - Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available - modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartMode[3]; - -/** Offset 0x01AA -**/ - UINT8 UnusedUpdSpace9[2]; - -/** Offset 0x01AC - Default BaudRate for each Serial IO UART - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 SerialIoUartBaudRate[3]; - -/** Offset 0x01B8 - Default ParityType for each Serial IO UART - Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartParity[3]; - -/** Offset 0x01BB - Default DataBits for each Serial IO UART - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 SerialIoUartDataBits[3]; - -/** Offset 0x01BE - Default StopBits for each Serial IO UART - Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: - TwoStopBits -**/ - UINT8 SerialIoUartStopBits[3]; - -/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode - Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto -**/ - UINT8 SerialIoUartPowerGating[3]; - -/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it - Set DMA/PIO mode. 0: Disabled, 1: Enabled -**/ - UINT8 SerialIoUartDmaEnable[3]; - -/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS lines. -**/ - UINT8 SerialIoUartAutoFlow[3]; - -/** Offset 0x01CA - Serial IO UART Pin Mux - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 SerialIoUartPinMux[3]; - -/** Offset 0x01CD - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x01CE - Serial IO UART DBG2 table - Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; - 1: Enable. -**/ - UINT8 SerialIoUartDbg2[3]; - -/** Offset 0x01D1 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x01D2 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x01D3 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x01D4 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x01D5 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x01D6 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x01DE - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x01E6 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x01F6 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x0200 - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x0201 -**/ - UINT8 UnusedUpdSpace10[3]; - -/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x0208 - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0209 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0211 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0212 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x0213 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x0214 - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x0215 - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x0216 -**/ - UINT8 UnusedUpdSpace11[2]; - -/** Offset 0x0218 - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x021C - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x021D - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x021E - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x021F - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x022F - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x023F - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x0287 - Enable xHCI LTR override - Enables override of recommended LTR values for xHCI - $EN_DIS -**/ - UINT8 PchUsbLtrOverrideEnable; - -/** Offset 0x0288 - xHCI High Idle Time LTR override - Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting -**/ - UINT32 PchUsbLtrHighIdleTimeOverride; - -/** Offset 0x028C - xHCI Medium Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting -**/ - UINT32 PchUsbLtrMediumIdleTimeOverride; - -/** Offset 0x0290 - xHCI Low Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting -**/ - UINT32 PchUsbLtrLowIdleTimeOverride; - -/** Offset 0x0294 - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x0295 - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x0296 - Enable HD Audio DMIC0 Link - Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x0297 - Enable HD Audio DMIC1 Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x0298 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x0299 - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x029A - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x029B - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x029C - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x029D - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x029E - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x02A0 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpPtmMask; - -/** Offset 0x02A4 - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcMask; - -/** Offset 0x02A8 - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcExtensionsMask; - -/** Offset 0x02AC - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x02AD -**/ - UINT8 UnusedUpdSpace12[3]; - -/** Offset 0x02B0 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounce; - -/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x02B5 - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x02B6 -**/ - UINT8 UnusedUpdSpace13[2]; - -/** Offset 0x02B8 - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x02BC - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x02BD -**/ - UINT8 UnusedUpdSpace14[3]; - -/** Offset 0x02C0 - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x02C4 - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x02C8 - Enable Ufs Controller - Enable/disable Ufs 2.0 Controller. - $EN_DIS -**/ - UINT8 ScsUfsEnabled; - -/** Offset 0x02C9 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 CnviMode; - -/** Offset 0x02CA - CNVi BT Core - Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtCore; - -/** Offset 0x02CB - CNVi BT Audio Offload - Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtAudioOffload; - -/** Offset 0x02CC - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x02CD - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PchUsb2PhySusPgEnable; - -/** Offset 0x02CE - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x02CF - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x02D0 - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x02D1 - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x02D2 - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x02D3 - SLP_S0 VM Dynamic Control - SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0VmRuntimeControl; - -/** Offset 0x02D4 - SLP_S0 VM 0.70V Support - SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm070VSupport; - -/** Offset 0x02D5 - SLP_S0 VM 0.75V Support - SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm075VSupport; - -/** Offset 0x02D6 - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[24]; - -/** Offset 0x02EE - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x02FE - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x030E - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[24]; - -/** Offset 0x0326 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x033E - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x036F - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping - CPU and 1 for PCH-H Series. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 SlpS0WithGbeSupport; - -/** Offset 0x0370 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x037B -**/ - UINT8 UnusedUpdSpace15[1]; - -/** Offset 0x037C - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x0386 - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0390 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0391 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0392 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x0393 - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x0394 - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. - 0: 2T, 1: 1T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x0396 - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x0397 - USB LFPS Filter selection - For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, - 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. -**/ - UINT8 PchUsbHsioFilterSel[10]; - -/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x03A2 - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x03B1 - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x03B4 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x03B5 - RTC CMOS MEMORY LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcMemoryLock; - -/** Offset 0x03B6 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x03CE - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03E6 - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x0416 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x042E - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x0446 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x045E - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x0476 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x048E - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x04A6 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x04D6 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04EE - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters - Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for - controlling the input offset -**/ - UINT8 PchUsbHsioRxTuningParameters[10]; - -/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable - Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, - 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable -**/ - UINT8 PchUsbHsioRxTuningEnable[10]; - -/** Offset 0x051A - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x054A - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x0562 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x057A - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x0592 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05AA - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x05C2 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x060A - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, - the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x060F - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the - default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0614 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0615 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0616 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x0617 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x0618 - Teton Glacier Cycle Router - Specify to which cycle router Teton Glacier is connected, it is valid only when - Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system -**/ - UINT8 TetonGlacierCR; - -/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x061A - PCIE IMR - Enables Isolated Memory Region for PCIe. - $EN_DIS -**/ - UINT8 PcieRpImrEnabled; - -/** Offset 0x061B - PCIE IMR port number - Selects PCIE root port number for IMR feature. -**/ - UINT8 PcieRpImrSelection; - -/** Offset 0x061C - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic - Configuration. Default is 0: Disabled - 0: Disabled, 1: Dynamic Configuration -**/ - UINT8 TetonGlacierMode; - -/** Offset 0x061D - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x061F - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0622 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0623 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0624 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0625 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0626 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x0627 - SLP_S0# Override - Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' - will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion - when debug is enabled. \n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:Disabled, 1:Enabled, 2:Auto -**/ - UINT8 SlpS0Override; - -/** Offset 0x0628 - S0ix Override Settings - Select 'Auto', it will be auto-configured according to probe type. 'No Change' will - keep PMC default settings. Or select the desired debug probe type for S0ix Override - settings.\n - Reminder: DCI OOB (aka BSSB) uses CCA probe.\n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto -**/ - UINT8 SlpS0DisQForDebug; - -/** Offset 0x0629 - USB Overcurrent Override for DbC - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x062A - PCH Legacy IO Low Latency Enable - Set to enable low latency of legacy IO. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x062B - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - Default value is Disabled - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x062C - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x062D - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x062E - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0630 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0631 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0632 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x0635 - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x0636 - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0637 - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x0638 - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0639 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x0641 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x0649 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x0651 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x0659 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x0661 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x0669 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x0671 -**/ - UINT8 UnusedUpdSpace16[1]; - -/** Offset 0x0672 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x0682 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x068A - PCH Sata Rst Raid Device Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x068B - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x068C - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x068D - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x068E - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x068F - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x0692 - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x0693 - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x0694 - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x0695 - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x069F - Enable eMMC HS400 Training - Deprecated. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400TuningRequired; - -/** Offset 0x06A0 - Set HS400 Tuning Data Valid - Deprecated - $EN_DIS -**/ - UINT8 PchScsEmmcHs400DllDataValid; - -/** Offset 0x06A1 - Rx Strobe Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400RxStrobeDll1; - -/** Offset 0x06A2 - Tx Data Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400TxDataDll; - -/** Offset 0x06A3 - I/O Driver Strength - Deprecated - 0:33 Ohm, 1:40 Ohm, 2:50 Ohm -**/ - UINT8 PchScsEmmcHs400DriverStrength; - -/** Offset 0x06A4 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x06A5 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x06A6 - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. - 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x06A7 - Reserved - Reserved - $EN_DIS -**/ - UINT8 ReservedForFuture1; - -/** Offset 0x06A8 - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x06A9 -**/ - UINT8 UnusedUpdSpace17; - -/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x06B0 - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x06B1 - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x06B2 - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x06B3 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x06B4 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x06B7 - Thermal Sensor 0 Target Width - DMT thermal sensor suggested representative values. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x06B8 - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x06B9 - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x06BA - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x06BB - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x06BC - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x06BD - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x06BE - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x06BF - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x06C0 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x06C1 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x06C2 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x06C3 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x06C5 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x06C8 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x06C9 - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x06CB - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x06CD - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x06CF -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x06D0 - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x06D2 - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x06D3 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x06E3 - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x06ED - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x06EE - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x06F1 -**/ - UINT8 UnusedUpdSpace19[3]; - -/** Offset 0x06F4 - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x06F8 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x06F9 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x06FB - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTranEnable[10]; - -/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default - = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTran[10]; - -/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTranEnable[10]; - -/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTran[10]; - -/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTranEnable[10]; - -/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTran[10]; - -/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTranEnable[10]; - -/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTran[10]; - -/** Offset 0x074C - Number of Coefficients to be used - The number of coefficients to be used for equalization, default value is 3 -**/ - UINT8 PcieNumOfCoefficients; - -/** Offset 0x074D - GPIO RCOMP Community Clock Gating - 0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock - local clock gating, default value is 1 - $EN_DIS -**/ - UINT8 GpioPmRcompCommunityLocalClockGating; - -/** Offset 0x074E - Enable SD Card Write Protect Pin - Enable/disable SD Card Write Protect Pin. - $EN_DIS -**/ - UINT8 ScsSdCardWpPinEnabled; - -/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config - Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, - 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte - for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlpResetConfig[8]; - -/** Offset 0x0757 - Flash Configuration Lock Down - Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. - $EN_DIS -**/ - UINT8 SpiFlashCfgLockDown; - -/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control - 0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x075C - ReservedPchPostMem - Reserved for Pch Post-Mem - $EN_DIS -**/ - UINT8 ReservedPchPostMem[3]; - -/** Offset 0x075F -**/ - UINT8 UnusedUpdSpace20[1]; - -/** Offset 0x0760 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0780 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x0784 -**/ - UINT8 UnusedUpdSpace21[4]; - -/** Offset 0x0788 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0790 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x0798 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x0799 - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x079A -**/ - UINT8 UnusedUpdSpace22[6]; - -/** Offset 0x07A0 - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x07A8 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x07B0 - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x07B1 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x07B2 -**/ - UINT8 UnusedUpdSpace23[2]; - -/** Offset 0x07B4 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x07B8 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x07BA - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x07BB - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x07BC -**/ - UINT8 UnusedUpdSpace24[3]; - -/** Offset 0x07BF -**/ - UINT8 ReservedFspsUpd[1]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x07C0 -**/ - UINT32 Signature; - -/** Offset 0x07C4 - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x07C5 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x07C6 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x07C7 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x07C8 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x07C9 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x07CD - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x07CE - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x07CF - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x07D0 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisableDeprecated; - -/** Offset 0x07D1 - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x07D2 - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x07D3 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x07DE - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x07DF - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x07E0 - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x07E1 - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07E2 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07E3 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07E4 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. - Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 - , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07E5 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07E6 - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07E7 - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07E8 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07E9 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07EA - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07EB - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For Y SKU, the recommended default for this policy is 15, - For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07ED - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07EE - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07EF - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07F0 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07F1 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07F2 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07F3 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07F4 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07F5 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07F6 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07F7 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07F8 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07F9 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07FA - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07FB - PL1 timewindow - PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) - 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07FC - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0800 - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features - @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0802 - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x0803 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x0804 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x0805 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x0806 -**/ - UINT8 UnusedUpdSpace25[2]; - -/** Offset 0x0808 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x0810 - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x0814 - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0816 - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0818 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x081B - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x081C - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x081D - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x081E - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x081F - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x0820 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x0821 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x0822 - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0824 - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x0825 - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0827 - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0828 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0829 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x082A - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x082B - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x082C - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x082D - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x082E - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x082F - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x0830 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x0831 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x0832 - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x0833 - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x086B -**/ - UINT8 UnusedUpdSpace26; - -/** Offset 0x086C - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x087A -**/ - UINT8 UnusedUpdSpace27[2]; - -/** Offset 0x087C - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0880 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x0884 - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0888 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x088C - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x08A8 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x08AC - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x08B0 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x08B2 - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x08B3 - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x08B4 - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x08B5 - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver - Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x08BA - CpuWakeUpTimer - Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased - to 180 seconds. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CpuWakeUpTimer; - -/** Offset 0x08BB - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x08BC - Minimum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion - Enable or Disable C3 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateAutoDemotion; - -/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion - Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateUnDemotion; - -/** Offset 0x08BF - Ratio Limit Num Core 0 - Ratio Limit Num Core0: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore0; - -/** Offset 0x08C0 - Ratio Limit Num Core 1 - Ratio Limit Num Core1: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore1; - -/** Offset 0x08C1 - Ratio Limit Num Core 2 - Ratio Limit Num Core2: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore2; - -/** Offset 0x08C2 - Ratio Limit Core 3 - Ratio Limit Num Core3: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore3; - -/** Offset 0x08C3 - Ratio Limit Num Core 4 - Ratio Limit Num Core4: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore4; - -/** Offset 0x08C4 - Ratio Limit Num Core 5 - Ratio Limit Num Core5: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore5; - -/** Offset 0x08C5 - Ratio Limit Num Core 6 - Ratio Limit Num Core6: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore6; - -/** Offset 0x08C6 - Ratio Limit Num Core 7 - Ratio Limit Num Core7: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore7; - -/** Offset 0x08C7 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[11]; - -/** Offset 0x08D2 - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x08D3 - End of Post message - Deprecated - 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x08D4 - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x08D5 -**/ - UINT8 UnusedUpdSpace28; - -/** Offset 0x08D6 - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08D8 - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x08DA - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x08DB - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x093C - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x096C - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09FC - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x0A14 - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A75 - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A76 - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A77 - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0A79 - ReservedPchPostMemTest - Reserved for Pch Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPostMemTest[16]; - -/** Offset 0x0A89 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0A8A - Use DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 EmmcUseCustomDlls; - -/** Offset 0x0A8B -**/ - UINT8 UnusedUpdSpace29; - -/** Offset 0x0A8C - Emmc Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 EmmcTxCmdDelayRegValue; - -/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 EmmcTxDataDelay1RegValue; - -/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 EmmcTxDataDelay2RegValue; - -/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay1RegValue; - -/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay2RegValue; - -/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value - Please see Rx Strobe Delay control register definition for help -**/ - UINT32 EmmcRxStrobeDelayRegValue; - -/** Offset 0x0AA4 - Use tuned DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 SdCardUseCustomDlls; - -/** Offset 0x0AA5 -**/ - UINT8 UnusedUpdSpace30[3]; - -/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 SdCardTxCmdDelayRegValue; - -/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 SdCardTxDataDelay1RegValue; - -/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 SdCardTxDataDelay2RegValue; - -/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay1RegValue; - -/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay2RegValue; - -/** Offset 0x0ABC - Enforce Enhanced Debug Mode - Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 EnforceEDebugMode; - -/** Offset 0x0ABD -**/ - UINT8 UnusedUpdSpace31[7]; - -/** Offset 0x0AC4 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x07C0 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0AD0 -**/ - UINT8 UnusedUpdSpace32[6]; - -/** Offset 0x0AD6 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h deleted file mode 100644 index 508705c13f..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h +++ /dev/null @@ -1,186 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUartMode - FSPT - Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 PcdSerialIoUartMode; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 PcdSerialIoUartBaudRate; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 - PcdSerialIoUartParity - FSPT - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 PcdSerialIoUartParity; - -/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 PcdSerialIoUartDataBits; - -/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 PcdSerialIoUartStopBits; - -/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT - Enables UART hardware flow control, CTS and RTS lines. - 0: Disable, 1:Enable -**/ - UINT8 PcdSerialIoUartAutoFlow; - -/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT - Select RX pin muxing for SerialIo UART used for debug -**/ - UINT32 PcdSerialIoUartRxPinMux; - -/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT - Select TX pin muxing for SerialIo UART used for debug -**/ - UINT32 PcdSerialIoUartTxPinMux; - -/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT - Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. -**/ - UINT32 PcdSerialIoUartRtsPinMux; - -/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT - Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. -**/ - UINT32 PcdSerialIoUartCtsPinMux; - -/** Offset 0x0068 -**/ - UINT8 ReservedFsptUpd1[24]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0080 -**/ - UINT8 UnusedUpdSpace1[6]; - -/** Offset 0x0086 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/MemInfoHob.h deleted file mode 100644 index f1ca44fa1b..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/MemInfoHob.h +++ /dev/null @@ -1,274 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.
- This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License that accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php. - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -@par Specification Reference: -**/ -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef CPU_CFL//CNL -#ifndef MRC_DDR_TYPE_LPDDR4 -#define MRC_DDR_TYPE_LPDDR4 3 -#endif -#else//CFL -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif -#endif//CPU_CFL-endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; -#ifdef CPU_CFL - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; -#endif //CPU_CFL -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ From 17a478c85468049771da7d2c51831334942b4d43 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Mon, 16 Mar 2020 22:17:12 +0530 Subject: [PATCH 0604/1463] mb/intel/jasperlake_rvp: Add config check for lid switch We should only define function to get lid switch and recovery mode switches when CHROMEEC_SWITCHES is not available. Correct this to avoid compilation issues BUG=None BRANCH=None TEST=jslrvp code compilation is fine Change-Id: I2445d40da1540c9d8c8c5fc845a4f38a5abf983e Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39585 Reviewed-by: Ronak Kanabar Reviewed-by: V Sowmya Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/chromeos.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 2f2abb5e6b..bee7eba666 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -28,6 +28,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) int get_lid_switch(void) { /* Lid always open */ @@ -39,6 +40,8 @@ int get_recovery_mode_switch(void) return 0; } +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + int get_write_protect_state(void) { /* No write protect */ From 4cc2cacd333de4d77809f1212e879e61ff8e1616 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 6 Dec 2019 19:11:08 -0700 Subject: [PATCH 0605/1463] arch/x86: Add Kconfig option for 2nd VGA BIOS image Picasso and Dali need different video bioses even though they use the same code in most other places. The Kconfig symbol names are changed from the downstream commit to make them more consistent with current coreboot code. BUG=b:145817712 TEST=Build Dali vBIOS into the coreboot image Change-Id: Ide0d061fda0abc78a74ddf97ba81fc3cf2b02e4f Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/1956534 Reviewed-by: Paul Fagerburg Reviewed-by: Raul E Rangel Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/39791 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Raul Rangel --- src/arch/x86/Makefile.inc | 5 +++++ src/device/Kconfig | 29 +++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 873161237e..b28ef78adc 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -34,6 +34,11 @@ cbfs-files-$(CONFIG_VGA_BIOS) += pci$(stripped_vgabios_id).rom pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)) pci$(stripped_vgabios_id).rom-type := optionrom +stripped_second_vbios_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_SECOND_ID)) +cbfs-files-$(CONFIG_VGA_BIOS_SECOND) += pci$(stripped_second_vbios_id).rom +pci$(stripped_second_vbios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_SECOND_FILE)) +pci$(stripped_second_vbios_id).rom-type := optionrom + stripped_vgabios_dgpu_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_ID)) cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE)) diff --git a/src/device/Kconfig b/src/device/Kconfig index 25123ea3e0..66130ccd41 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -680,6 +680,35 @@ config VGA_BIOS_ID Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. +config VGA_BIOS_SECOND + bool "Add a 2nd video BIOS image" + depends on ARCH_X86 && VGA_BIOS + help + Select this option if you have a 2nd video BIOS image that you would + like to add to your ROM. + +config VGA_BIOS_SECOND_FILE + string "2nd video BIOS path and filename" + depends on VGA_BIOS_SECOND + default "vbios2.bin" + help + The path and filename of the file to use as video BIOS. + +config VGA_BIOS_SECOND_ID + string "Graphics device PCI IDs" + depends on VGA_BIOS_SECOND + help + The comma-separated PCI vendor and device ID that would associate + your vBIOS to your video card. + + Example: 1106,3230 + + In the above example 1106 is the PCI vendor ID (in hex, but without + the "0x" prefix) and 3230 specifies the PCI device ID of the + video card (also in hex, without "0x" prefix). + + Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. + config VGA_BIOS_DGPU bool "Add a discrete VGA BIOS image" depends on VGA_BIOS From a616a4be366c6af1f8ccfbfd1f16a4572c7e6c91 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 21 Jan 2020 09:28:40 -0700 Subject: [PATCH 0606/1463] src/device: Add option to look at revision in option roms AMD's Family 17h SOCs have the same vendor and device IDs for their graphics blocks, but need different video BIOSes. The only difference is the revision number. Add a Kconfig option that allows us to add the revision number of the graphics device to the PCI option rom saved in CBFS. Because searching CBFS takes a non-trivial amount of time, only enable the option if it's needed. If it's not used, or if nothing matches, the check will fall through and search for an option rom with no version. BUG=b:145817712 TEST=With surrounding patches, loads dali vbios Change-Id: Icb610a2abe7fcd0f4dc3716382b9853551240a7a Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/2013181 Reviewed-by: Martin Roth Tested-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/39792 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/device/Kconfig | 22 ++++++++++++++-------- src/device/pci_rom.c | 10 ++++++++-- src/include/cbfs.h | 2 ++ src/lib/cbfs.c | 17 +++++++++++++++++ 4 files changed, 41 insertions(+), 10 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 66130ccd41..de33b04773 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -669,14 +669,14 @@ config VGA_BIOS_ID depends on VGA_BIOS default "1106,3230" help - The comma-separated PCI vendor and device ID that would associate - your VGA BIOS to your video card. + The comma-separated PCI vendor and device ID with optional revision if that + feature is enabled that would associate your vBIOS to your video card. - Example: 1106,3230 + Example: 1106,3230 or 1106,3230,a3 In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the - video card (also in hex, without "0x" prefix). + video card (also in hex, without "0x" prefix). a3 specifies the revision. Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. @@ -698,17 +698,23 @@ config VGA_BIOS_SECOND_ID string "Graphics device PCI IDs" depends on VGA_BIOS_SECOND help - The comma-separated PCI vendor and device ID that would associate - your vBIOS to your video card. + The comma-separated PCI vendor and device ID with optional revision if that + feature is enabled that would associate your vBIOS to your video card. - Example: 1106,3230 + Example: 1106,3230 or 1106,3230,a3 In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the - video card (also in hex, without "0x" prefix). + video card (also in hex, without "0x" prefix). a3 specifies the revision. Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. +config CHECK_REV_IN_OPROM_NAME + def_bool n + help + Select this in the platform BIOS or chipset if the option rom has a revision + that needs to be checked when searching CBFS. + config VGA_BIOS_DGPU bool "Add a discrete VGA BIOS image" depends on VGA_BIOS diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 27f2d8dca2..6af20e854e 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -27,11 +27,17 @@ u32 __weak map_oprom_vendev(u32 vendev) { return vendev; } struct rom_header *pci_rom_probe(struct device *dev) { - struct rom_header *rom_header; + struct rom_header *rom_header = NULL; struct pci_data *rom_data; /* If it's in FLASH, then don't check device for ROM. */ - rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); + if (CONFIG(CHECK_REV_IN_OPROM_NAME)) { + uint8_t rev = pci_read_config8(dev, PCI_REVISION_ID); + rom_header = cbfs_boot_map_optionrom_revision(dev->vendor, dev->device, rev); + } + + if (!rom_header) + rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); u32 vendev = (dev->vendor << 16) | dev->device; u32 mapped_vendev; diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 823368644b..feb73a1310 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -24,6 +24,8 @@ /* Return mapping of option ROM found in boot device. NULL on error. */ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); +/* Return mapping of option ROM with revision number. Returns NULL on error. */ +void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev); /* Locate file by name and optional type. Return 0 on success. < 0 on error. */ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); /* Map file into memory leaking the mapping. Only should be used when diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index b8f3d5cb61..4f0b443360 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -159,6 +159,12 @@ static inline int tohex4(unsigned int c) return (c <= 9) ? (c + '0') : (c - 10 + 'a'); } +static void tohex8(unsigned int val, char *dest) +{ + dest[0] = tohex4((val >> 4) & 0xf); + dest[1] = tohex4(val & 0xf); +} + static void tohex16(unsigned int val, char *dest) { dest[0] = tohex4(val >> 12); @@ -177,6 +183,17 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); } +void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev) +{ + char name[20] = "pciXXXX,XXXX,XX.rom"; + + tohex16(vendor, name + 3); + tohex16(device, name + 8); + tohex8(rev, name + 13); + + return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); +} + size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, uint32_t type) { From dafcc7a26dece2cbd73a6a4f761b3fb3963bd260 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 5 Feb 2020 16:46:30 -0700 Subject: [PATCH 0607/1463] Rework map_oprom_vendev to add revision check and mapping AMD's Family 17h SoCs share the same video device ID, but may need different video BIOSes. This adds the common code changes to check the vendor & device IDs along with the revision and select the correct video BIOS to use. Change-Id: I2978a5693c904ddb09d23715cb309c4a356e0370 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/2040455 Reviewed-by: Raul E Rangel Reviewed-by: Matt Papageorge Reviewed-by: Justin Frodsham Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/39793 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/device/pci_rom.c | 27 ++++++++++++++++----------- src/include/device/pci_rom.h | 1 + 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 6af20e854e..7d489615f1 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -23,29 +23,34 @@ #include /* Rmodules don't like weak symbols. */ +void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; } u32 __weak map_oprom_vendev(u32 vendev) { return vendev; } struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header = NULL; struct pci_data *rom_data; + u8 rev = pci_read_config8(dev, PCI_REVISION_ID); + u8 mapped_rev = rev; + u32 vendev = (dev->vendor << 16) | dev->device; + u32 mapped_vendev = vendev; - /* If it's in FLASH, then don't check device for ROM. */ + /* If the ROM is in flash, then don't check the PCI device for it. */ if (CONFIG(CHECK_REV_IN_OPROM_NAME)) { - uint8_t rev = pci_read_config8(dev, PCI_REVISION_ID); rom_header = cbfs_boot_map_optionrom_revision(dev->vendor, dev->device, rev); + map_oprom_vendev_rev(&mapped_vendev, &mapped_rev); + } else { + rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); + mapped_vendev = map_oprom_vendev(vendev); } - if (!rom_header) - rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); - - u32 vendev = (dev->vendor << 16) | dev->device; - u32 mapped_vendev; - - mapped_vendev = map_oprom_vendev(vendev); - if (!rom_header) { - if (vendev != mapped_vendev) { + if (CONFIG(CHECK_REV_IN_OPROM_NAME) && + (vendev != mapped_vendev || rev != mapped_rev)) { + rom_header = cbfs_boot_map_optionrom_revision( + mapped_vendev >> 16, + mapped_vendev & 0xffff, mapped_rev); + } else if (vendev != mapped_vendev) { rom_header = cbfs_boot_map_optionrom( mapped_vendev >> 16, mapped_vendev & 0xffff); diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 82f3c40005..47db52cf19 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -45,6 +45,7 @@ pci_rom_write_acpi_tables(struct device *device, void pci_rom_ssdt(struct device *device); +void map_oprom_vendev_rev(u32 *vendev, u8 *rev); u32 map_oprom_vendev(u32 vendev); int verified_boot_should_run_oprom(struct rom_header *rom_header); From 34d8036333ed1d16d1ef48d3a7c98cc7c7592599 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 24 Oct 2019 15:14:42 +0200 Subject: [PATCH 0608/1463] drivers/secunet: Add driver to read DMI info from I2C EEPROM The EEPROM layout is rather arbitrary and /just happened/. It needs a 256kbit part at least. Change-Id: Iae5c9138e8404acfc3a43dc2c7b55d47d4147060 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36298 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/drivers/secunet/dmi/Kconfig | 3 + src/drivers/secunet/dmi/Makefile.inc | 1 + src/drivers/secunet/dmi/eeprom.h | 62 +++++++++++++++ src/drivers/secunet/dmi/smbios.c | 109 +++++++++++++++++++++++++++ 4 files changed, 175 insertions(+) create mode 100644 src/drivers/secunet/dmi/Kconfig create mode 100644 src/drivers/secunet/dmi/Makefile.inc create mode 100644 src/drivers/secunet/dmi/eeprom.h create mode 100644 src/drivers/secunet/dmi/smbios.c diff --git a/src/drivers/secunet/dmi/Kconfig b/src/drivers/secunet/dmi/Kconfig new file mode 100644 index 0000000000..7e83f9034a --- /dev/null +++ b/src/drivers/secunet/dmi/Kconfig @@ -0,0 +1,3 @@ +config SECUNET_DMI + bool + select SMBIOS_PROVIDED_BY_MOBO diff --git a/src/drivers/secunet/dmi/Makefile.inc b/src/drivers/secunet/dmi/Makefile.inc new file mode 100644 index 0000000000..9c85485d1e --- /dev/null +++ b/src/drivers/secunet/dmi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SECUNET_DMI) += smbios.c diff --git a/src/drivers/secunet/dmi/eeprom.h b/src/drivers/secunet/dmi/eeprom.h new file mode 100644 index 0000000000..c4cdd4142e --- /dev/null +++ b/src/drivers/secunet/dmi/eeprom.h @@ -0,0 +1,62 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SECUNET_DMI_EEPROM_H +#define _SECUNET_DMI_EEPROM_H + +#include + +enum bx26_strings { + BOARD_MATNR, + BOARD_SERIAL_NUMBER, + BOARD_VERSION, + BOARD_MCTRL_FW_VERSION, + BOARD_CCR_FW_VERSION, + BOARD_NIC_FW_VERSION, + BOARD_LP_VERSION, + BOARD_VERSION_ID, + + SYSTEM_PRODUCT_NAME, + SYSTEM_VERSION, + SYSTEM_SERIAL_NUMBER, + SYSTEM_UUID, + SYSTEM_MANUFACTURER, + SYSTEM_PRODUCTION_DATE, + SYSTEM_MLFB, + SYSTEM_MATNR, +}; + +struct bx26_location { + uint16_t offset; + uint16_t length; +}; + +static const struct bx26_location bx26_locations[] = { + [BOARD_MATNR] = { 0x0000, 0x20 }, + [BOARD_SERIAL_NUMBER] = { 0x0020, 0x20 }, + [BOARD_VERSION] = { 0x0040, 0x20 }, + [BOARD_MCTRL_FW_VERSION] = { 0x0060, 0x20 }, + [BOARD_CCR_FW_VERSION] = { 0x0080, 0x20 }, + [BOARD_NIC_FW_VERSION] = { 0x00a0, 0x20 }, + [BOARD_LP_VERSION] = { 0x00c0, 0x20 }, + [BOARD_VERSION_ID] = { 0x0100, 0x20 }, + + [SYSTEM_PRODUCT_NAME] = { 0x4000, 0x20 }, + [SYSTEM_VERSION] = { 0x4040, 0x10 }, + [SYSTEM_SERIAL_NUMBER] = { 0x4060, 0x10 }, + [SYSTEM_UUID] = { 0x4080, 0x24 }, + [SYSTEM_MANUFACTURER] = { 0x40c0, 0x20 }, + [SYSTEM_PRODUCTION_DATE] = { 0x4100, 0x20 }, + [SYSTEM_MLFB] = { 0x4140, 0x20 }, + [SYSTEM_MATNR] = { 0x4180, 0x20 }, +}; + +#endif diff --git a/src/drivers/secunet/dmi/smbios.c b/src/drivers/secunet/dmi/smbios.c new file mode 100644 index 0000000000..5dfbb5d8b7 --- /dev/null +++ b/src/drivers/secunet/dmi/smbios.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "eeprom.h" + +#define MAX_STRING_LENGTH UUID_STRLEN + +static struct device *eeprom; + +static const char *eeprom_read_string(const enum bx26_strings idx) +{ + static char str[MAX_STRING_LENGTH + 1]; + + if (!eeprom) { + printk(BIOS_WARNING, "DMI: Serial EEPROM not found\n"); + str[0] = '\0'; + return str; + } + + const size_t offset = bx26_locations[idx].offset; + const size_t length = MIN(bx26_locations[idx].length, MAX_STRING_LENGTH); + + if (i2c_dev_read_at16(eeprom, (u8 *)str, length, offset) != length) { + printk(BIOS_WARNING, "DMI: Failed to read serial EEPROM\n"); + str[0] = '\0'; + } else { + unsigned int i; + /* Terminate at first non-printable character. */ + for (i = 0; i < length; ++i) { + if (!isprint(str[i])) + break; + } + str[i] = '\0'; + } + + return str; +} + +const char *smbios_system_manufacturer(void) +{ + return eeprom_read_string(SYSTEM_MANUFACTURER); +} + +const char *smbios_system_product_name(void) +{ + return eeprom_read_string(SYSTEM_PRODUCT_NAME); +} + +const char *smbios_system_serial_number(void) +{ + return eeprom_read_string(SYSTEM_SERIAL_NUMBER); +} + +const char *smbios_system_version(void) +{ + return eeprom_read_string(SYSTEM_VERSION); +} + +void smbios_system_set_uuid(u8 *const uuid) +{ + if (parse_uuid(uuid, eeprom_read_string(SYSTEM_UUID))) { + printk(BIOS_WARNING, "DMI: Cannot parse UUID\n"); + memset(uuid, 0x00, UUID_LEN); + } +} + +const char *smbios_mainboard_serial_number(void) +{ + return eeprom_read_string(BOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + return eeprom_read_string(BOARD_VERSION); +} + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_I2C || (dev->path.i2c.device & 0xf0) != 0x50) + return; + eeprom = dev; +} + +struct chip_operations drivers_secunet_dmi_ops = { + CHIP_NAME("secunet DMI") + .enable_dev = enable_dev, +}; From e680caa2988ee1c6b08e1ba3ed85574ca4c4da43 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 24 Mar 2020 13:51:26 +0100 Subject: [PATCH 0609/1463] Makefile.inc: Don't run `ifittool` with CONFIG_UPDATE_IMAGE The dependency for `ifittool` was missing in the CONFIG_UPDATE_IMAGE case. Which led us to the question: Why run `ifittool` in this case? The idea of CONFIG_UPDATE_IMAGE is to update everything _but_ the bootblock. Change-Id: I7fd3bd1b56f495b16beb1e1f4b35b8cfcf25b2ba Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39803 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 43b29c73cc..dbf95d4fb3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1112,6 +1112,7 @@ ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n" $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ @@ -1146,7 +1147,8 @@ endif endif -endif +endif # !CONFIG_UPDATE_IMAGE +endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE mv $@.tmp $@ @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ layout From 9e71fdd506752391b36c518b545cf03f37351ed5 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 23 Mar 2020 22:01:45 -0600 Subject: [PATCH 0610/1463] mb/google/dedede: Update EC_MKBP_INT_L configuration The concerned GPIO is configured as an open drain at the Embedded Controller side without an external pull-up. This causes leakage in the PP3300_A rail. So configure the GPIO to have a weak internal pull-up at the SoC side. BUG=b:151680590 TEST=Build the mainboard. Ensure that there are no leakages in the PP3300_A rail. Change-Id: I5553cf40adb92edc0fecab5c875ec8d72063ba7b Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/39796 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index bdc3de4f70..a0127370c3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -127,7 +127,7 @@ static const struct pad_config gpio_table[] = { /* C14 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* C15 : EC_AP_MKBP_INT_L */ - PAD_CFG_GPI_APIC(GPP_C15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC(GPP_C15, UP_20K, PLTRST, LEVEL, INVERT), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ From b43d74a79827d696866f72da51944a83b5635580 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 8 Jan 2020 21:17:18 +0530 Subject: [PATCH 0611/1463] mb/intel/jasperlake_rvp: Update FMAP for jslrvp Remove unused SMM_STORE space and use it for RW_LEGACY area BUG=None TEST=None Change-Id: I5724b860271025e8cb8b320ecbd33352ef779660 Signed-off-by: Meera Ravindranath Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/38273 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: V Sowmya --- src/mainboard/intel/jasperlake_rvp/chromeos.fmd | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index f4db8b4bc7..827e4484ca 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,10 +1,10 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x3F0000 { + SI_ALL@0x0 0x600000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x36F000 + SI_ME@0x81000 0x57F000 } - SI_BIOS@0x400000 0xC00000 { + SI_BIOS@0x600000 0xA00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x2bffc0 @@ -28,16 +28,15 @@ FLASH@0xff000000 0x1000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - SMMSTORE(PRESERVE)@0x5d0000 0x40000 - RW_LEGACY(CBFS)@0x610000 0x1c0000 - WP_RO@0x7d0000 0x430000 { + RW_LEGACY(CBFS)@0x5d0000 0x100000 + WP_RO@0x6d0000 0x330000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x42c000 { + RO_SECTION@0x4000 0x32c000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x33c000 + COREBOOT(CBFS)@0xf0000 0x23c000 } } } From 4f012694dd3a04fa1166f33656595951eda107b2 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 13 Mar 2020 15:20:13 +0100 Subject: [PATCH 0612/1463] mb/facebook/monolith: Configure COMB to 0x3e8 The 2nd COM port's base address defaults to 0x2f8. Current software for this system expects the port at 0x3e8. Configure COMB to use 0x3e8 instead of 0x2f8. BUG=N/A TEST=tested on facebook monolith Change-Id: Ibb462bad5f0594e0b5c8dea6e02cd42d58d999ab Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/39499 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons --- src/mainboard/facebook/monolith/Kconfig | 1 - src/mainboard/facebook/monolith/acpi/superio.asl | 4 ++-- src/mainboard/facebook/monolith/com_init.c | 3 +++ src/mainboard/facebook/monolith/devicetree.cb | 6 ++++++ 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index b6c9f1939c..b4b6370ae5 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION select INTEL_GMA_HAVE_VBT - select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE select VPD config CBFS_SIZE diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl index a7763b91e0..54d450e710 100644 --- a/src/mainboard/facebook/monolith/acpi/superio.asl +++ b/src/mainboard/facebook/monolith/acpi/superio.asl @@ -52,14 +52,14 @@ Device (COM2) { Name (_CRS, ResourceTemplate () { - FixedIO (0x02F8, 0x08) + FixedIO (0x03E8, 0x08) IRQNoFlags () {3} }) Name (_PRS, ResourceTemplate () { StartDependentFn (0, 0) { - FixedIO (0x02F8, 0x08) + FixedIO (0x03E8, 0x08) IRQNoFlags () {3} } EndDependentFn () diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c index a7ad263bc3..3438a4d471 100644 --- a/src/mainboard/facebook/monolith/com_init.c +++ b/src/mainboard/facebook/monolith/com_init.c @@ -14,6 +14,7 @@ #include #include +#include #include "onboard.h" #define SERIAL_DEV1 PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ @@ -25,5 +26,7 @@ void bootblock_mainboard_early_init(void) pnp_set_logical_device(SERIAL_DEV1); pnp_set_enable(SERIAL_DEV1, 1); pnp_set_logical_device(SERIAL_DEV2); + pnp_set_iobase(SERIAL_DEV2, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(SERIAL_DEV2, PNP_IDX_IRQ0, 3); pnp_set_enable(SERIAL_DEV2, 1); } diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index e9fa2a143c..e65fe3cfc2 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -12,6 +12,12 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" + # Set the fixed lpc ranges + # enable COMA at 3f8 and COMB at 3e8 (instead of the default 2f8) + # enable the embedded controller + register "lpc_iod" = "0x0070" + register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" + # CPLD host command ranges are in 0x280-0x2BF # EC PNP registers are at 0x6e and 0x6f register "gen1_dec" = "0x003c0281" From 612a8676779f873f2f7a3c8011ad0eac61ca38f9 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 19 Feb 2019 19:11:29 +0100 Subject: [PATCH 0613/1463] drivers/intel/gma/acpi: Add Kconfigs for backlight registers Instead of adding more versions of the `*pch.asl`, unify the existing ones and allow to override the register locations via Kconfig. The current defaults should work for Skylake and some newer platforms. TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/31503 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Wim Vervoorn Reviewed-by: Benjamin Doron --- src/drivers/intel/gma/Kconfig | 16 ++++++++++ .../intel/gma/acpi/{non-pch.asl => gma.asl} | 7 +++-- src/drivers/intel/gma/acpi/pch.asl | 30 ------------------- src/northbridge/intel/gm45/Kconfig | 6 ++++ src/northbridge/intel/gm45/acpi/gm45.asl | 2 +- src/northbridge/intel/haswell/Kconfig | 3 ++ .../intel/haswell/acpi/haswell.asl | 2 +- src/northbridge/intel/ironlake/Kconfig | 3 ++ .../intel/ironlake/acpi/ironlake.asl | 2 +- src/northbridge/intel/sandybridge/Kconfig | 3 ++ .../intel/sandybridge/acpi/sandybridge.asl | 2 +- src/northbridge/intel/x4x/acpi/x4x.asl | 2 +- 12 files changed, 40 insertions(+), 38 deletions(-) rename src/drivers/intel/gma/acpi/{non-pch.asl => gma.asl} (76%) delete mode 100644 src/drivers/intel/gma/acpi/pch.asl diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 68d4edce03..acc25fea29 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -29,6 +29,22 @@ config INTEL_GMA_ACPI bool default n +config INTEL_GMA_BCLV_OFFSET + hex + default 0xc8254 + +config INTEL_GMA_BCLV_WIDTH + int + default 16 + +config INTEL_GMA_BCLM_OFFSET + hex + default 0xc8256 + +config INTEL_GMA_BCLM_WIDTH + int + default 16 + config INTEL_GMA_SSC_ALTERNATE_REF bool default n diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/gma.asl similarity index 76% rename from src/drivers/intel/gma/acpi/non-pch.asl rename to src/drivers/intel/gma/acpi/gma.asl index b656d484c9..57563933ce 100644 --- a/src/drivers/intel/gma/acpi/non-pch.asl +++ b/src/drivers/intel/gma/acpi/gma.asl @@ -19,9 +19,10 @@ Device (GFX0) OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) { - Offset (0x61254), - BCLV, 16, - BCLM, 16, + Offset (CONFIG_INTEL_GMA_BCLV_OFFSET), + BCLV, CONFIG_INTEL_GMA_BCLV_WIDTH, + Offset (CONFIG_INTEL_GMA_BCLM_OFFSET), + BCLM, CONFIG_INTEL_GMA_BCLM_WIDTH } #include "configure_brightness_levels.asl" diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl deleted file mode 100644 index 942ccf433c..0000000000 --- a/src/drivers/intel/gma/acpi/pch.asl +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -Device (GFX0) -{ - Name (_ADR, 0x00020000) - - OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) - Field (GFXC, DWordAcc, NoLock, Preserve) - { - Offset (0x10), - BAR0, 64, - Offset (0xe4), - ASLE, 32, - Offset (0xfc), - ASLS, 32, - } - - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) - Field (GFRG, DWordAcc, NoLock, Preserve) - { - Offset (0x48254), - BCLV, 16, - Offset (0xc8256), - BCLM, 16 - } - -#include "configure_brightness_levels.asl" -#include "common.asl" -} diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 752af43ba1..8857bd4f9b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -46,4 +46,10 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config INTEL_GMA_BCLV_OFFSET + default 0x61254 + +config INTEL_GMA_BCLM_OFFSET + default 0x61256 + endif diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 3a7e46487d..8a30212d1d 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -75,4 +75,4 @@ Device (PDRC) #include "peg.asl" // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 5e631cf025..06ce371946 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -107,4 +107,7 @@ config RO_REGION_ONLY depends on VBOOT default "mrc.bin" +config INTEL_GMA_BCLV_OFFSET + default 0x48254 + endif diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index c0de8532fd..900c6c3396 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -48,4 +48,4 @@ Device (PDRC) } // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 638f295dc0..9d937965dd 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -61,4 +61,7 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 +config INTEL_GMA_BCLV_OFFSET + default 0x48254 + endif diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 52fec1e731..2997dea951 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -51,4 +51,4 @@ Device (PDRC) } // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index a9bbf58ef8..29a6db7fb3 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -121,4 +121,7 @@ config MRC_FILE endif # !USE_NATIVE_RAMINIT +config INTEL_GMA_BCLV_OFFSET + default 0x48254 + endif diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 555058cbe6..202671a3e5 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -55,4 +55,4 @@ Device (PDRC) } // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 5f93b3eee3..09849e3b17 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -45,4 +45,4 @@ Device (PDRC) #include "peg.asl" // Integrated graphics 0:2.0 -#include +#include From b84c6167505ca76239b8bd59f4ebb3c115111de5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 23 Mar 2020 14:41:32 +0100 Subject: [PATCH 0614/1463] amd/common/acpi: move thermal zone to common location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Christian Walter Reviewed-by: Angel Pons --- src/northbridge/amd/agesa/family14/acpi/northbridge.asl | 3 +-- src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl | 2 +- src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 2 +- .../thermal_mixin.asl => soc/amd/common/acpi/thermal_zone.asl} | 2 +- 6 files changed, 6 insertions(+), 7 deletions(-) rename src/{northbridge/amd/agesa/family14/acpi/thermal_mixin.asl => soc/amd/common/acpi/thermal_zone.asl} (97%) diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 72efeca1cf..6f51ea1f7a 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -124,7 +124,6 @@ Device(PE23) { /* Northbridge function 3 */ Device(NBF3) { Name(_ADR, 0x00180003) - /* k10temp thermal zone */ - #include "thermal_mixin.asl" + #include } /* end NBF3 */ diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 40df8918b1..217132f8e4 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -95,5 +95,5 @@ Device(PBR7) { Device(K10M) { Name (_ADR, 0x00180003) - #include + #include } diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index 34bf33a32e..34e8ef046d 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -95,5 +95,5 @@ Device(PBR8) { Device(K10M) { Name (_ADR, 0x00180003) - #include + #include } diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index cdb4063d36..ed5db82e79 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -65,5 +65,5 @@ Device(PBR3) { Device(K10M) { Name (_ADR, 0x00180003) - #include + #include } diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index 34bf33a32e..34e8ef046d 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -95,5 +95,5 @@ Device(PBR8) { Device(K10M) { Name (_ADR, 0x00180003) - #include + #include } diff --git a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl b/src/soc/amd/common/acpi/thermal_zone.asl similarity index 97% rename from src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl rename to src/soc/amd/common/acpi/thermal_zone.asl index 3c692ce859..e6ab43235b 100644 --- a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl +++ b/src/soc/amd/common/acpi/thermal_zone.asl @@ -25,7 +25,7 @@ * Scope (\_SB.PCI0) { * Device (K10M) { * Name (_ADR, 0x00180003) - * #include + * #include * } * } * From 527177668910d15a3081e1d1db059a0011b58e81 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 24 Mar 2020 08:44:32 +0100 Subject: [PATCH 0615/1463] Documentation: Add lemp9 to toctree Fix "WARNING: document isn't included in any toctree" by adding the lemp9 to mainboard/index.md. Change-Id: Id6d8f9e2aab6dc7ad4baf1b37d88e531acb757f4 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39800 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/mainboard/index.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index f319edb510..99e5dd0b1d 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -144,6 +144,10 @@ The boards in this section are not real mainboards, but emulators. - [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md) - [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md) +## System76 + +- [Lemur Pro](system76/lemp9.md) + ## UP - [Squared](up/squared/index.md) From df09bdb726e719d2729a55734097e38bdcd7d67b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 16:40:41 +0100 Subject: [PATCH 0616/1463] nb/intel/sandybridge: Rewrite table accessors There is no need to call get_FRQ a dozen times with the same parameters. As SNB will eventually use the same code, only IVB is being refactored. Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330. Change-Id: Idd7c119b2aa291e6396e12fb29effaf3ec73108a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/sandybridge/raminit_ivy.c | 93 ++++++++++--------- 1 file changed, 48 insertions(+), 45 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 67927ed033..fa636565a2 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -29,94 +29,94 @@ static u32 get_FRQ(u32 tCK, u8 base_freq) return FRQ; } -/* Get REFI based on MC frequency, tREFI = 7.8usec */ -static u32 get_REFI(u32 tCK, u8 base_freq) +/* Get REFI based on frequency index, tREFI = 7.8usec */ +static u32 get_REFI(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_refi_map[1][get_FRQ(tCK, 100) - 7]; + return frq_refi_map[1][FRQ - 7]; else - return frq_refi_map[0][get_FRQ(tCK, 133) - 3]; + return frq_refi_map[0][FRQ - 3]; } -/* Get XSOffset based on MC frequency, tXS-Offset: tXS = tRFC + 10ns */ -static u8 get_XSOffset(u32 tCK, u8 base_freq) +/* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ +static u8 get_XSOffset(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_xs_map[1][get_FRQ(tCK, 100) - 7]; + return frq_xs_map[1][FRQ - 7]; else - return frq_xs_map[0][get_FRQ(tCK, 133) - 3]; + return frq_xs_map[0][FRQ - 3]; } -/* Get MOD based on MC frequency */ -static u8 get_MOD(u32 tCK, u8 base_freq) +/* Get MOD based on frequency index */ +static u8 get_MOD(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_mod_map[1][get_FRQ(tCK, 100) - 7]; + return frq_mod_map[1][FRQ - 7]; else - return frq_mod_map[0][get_FRQ(tCK, 133) - 3]; + return frq_mod_map[0][FRQ - 3]; } -/* Get Write Leveling Output delay based on MC frequency */ -static u8 get_WLO(u32 tCK, u8 base_freq) +/* Get Write Leveling Output delay based on frequency index */ +static u8 get_WLO(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_wlo_map[1][get_FRQ(tCK, 100) - 7]; + return frq_wlo_map[1][FRQ - 7]; else - return frq_wlo_map[0][get_FRQ(tCK, 133) - 3]; + return frq_wlo_map[0][FRQ - 3]; } -/* Get CKE based on MC frequency */ -static u8 get_CKE(u32 tCK, u8 base_freq) +/* Get CKE based on frequency index */ +static u8 get_CKE(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_cke_map[1][get_FRQ(tCK, 100) - 7]; + return frq_cke_map[1][FRQ - 7]; else - return frq_cke_map[0][get_FRQ(tCK, 133) - 3]; + return frq_cke_map[0][FRQ - 3]; } -/* Get XPDLL based on MC frequency */ -static u8 get_XPDLL(u32 tCK, u8 base_freq) +/* Get XPDLL based on frequency index */ +static u8 get_XPDLL(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_xpdll_map[1][get_FRQ(tCK, 100) - 7]; + return frq_xpdll_map[1][FRQ - 7]; else - return frq_xpdll_map[0][get_FRQ(tCK, 133) - 3]; + return frq_xpdll_map[0][FRQ - 3]; } -/* Get XP based on MC frequency */ -static u8 get_XP(u32 tCK, u8 base_freq) +/* Get XP based on frequency index */ +static u8 get_XP(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_xp_map[1][get_FRQ(tCK, 100) - 7]; + return frq_xp_map[1][FRQ - 7]; else - return frq_xp_map[0][get_FRQ(tCK, 133) - 3]; + return frq_xp_map[0][FRQ - 3]; } -/* Get AONPD based on MC frequency */ -static u8 get_AONPD(u32 tCK, u8 base_freq) +/* Get AONPD based on frequency index */ +static u8 get_AONPD(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_aonpd_map[1][get_FRQ(tCK, 100) - 7]; + return frq_aonpd_map[1][FRQ - 7]; else - return frq_aonpd_map[0][get_FRQ(tCK, 133) - 3]; + return frq_aonpd_map[0][FRQ - 3]; } -/* Get COMP2 based on MC frequency */ -static u32 get_COMP2(u32 tCK, u8 base_freq) +/* Get COMP2 based on frequency index */ +static u32 get_COMP2(u32 FRQ, u8 base_freq) { if (base_freq == 100) - return frq_comp2_map[1][get_FRQ(tCK, 100) - 7]; + return frq_comp2_map[1][FRQ - 7]; else - return frq_comp2_map[0][get_FRQ(tCK, 133) - 3]; + return frq_comp2_map[0][FRQ - 3]; } static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) @@ -363,14 +363,16 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); - ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); - ctrl->tXSOffset = get_XSOffset(ctrl->tCK, ctrl->base_freq); - ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); - ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); - ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); - ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + + ctrl->tREFI = get_REFI(FRQ, ctrl->base_freq); + ctrl->tMOD = get_MOD(FRQ, ctrl->base_freq); + ctrl->tXSOffset = get_XSOffset(FRQ, ctrl->base_freq); + ctrl->tWLO = get_WLO(FRQ, ctrl->base_freq); + ctrl->tCKE = get_CKE(FRQ, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(FRQ, ctrl->base_freq); + ctrl->tXP = get_XP(FRQ, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(FRQ, ctrl->base_freq); } static void dram_freq(ramctr_timing *ctrl) @@ -432,6 +434,7 @@ static void dram_freq(ramctr_timing *ctrl) static void dram_ioregs(ramctr_timing *ctrl) { + const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); u32 reg; int channel; @@ -459,7 +462,7 @@ static void dram_ioregs(ramctr_timing *ctrl) printram("done\n"); /* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK, ctrl->base_freq); + MCHBAR32(CRCOMPOFST2) = get_COMP2(FRQ, ctrl->base_freq); printram("COMP2 done\n"); /* Set COMP1 */ From 48409b82299ed032e151a67b80b2bb257b463172 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 22:19:29 +0100 Subject: [PATCH 0617/1463] nb/intel/sandybridge: Cache FRQ index It does not change once a frequency has been set, so store it somewhere. Since this changes the saved data definition, update MRC_CACHE_VERSION. As SNB will eventually use the same code, only IVB is being refactored. Change-Id: I25b7c394abab173241fffdf57ac5c929daad8257 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39786 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/sandybridge/raminit_common.h | 5 ++- .../intel/sandybridge/raminit_ivy.c | 31 +++++++++---------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 43bdd340dd..d966c51dfc 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -33,7 +33,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 2 +#define MRC_CACHE_VERSION 3 typedef struct odtmap_st { u16 rttwr; @@ -78,6 +78,9 @@ typedef struct ramctr_timing_st { /* DDR base_freq = 100 Mhz / 133 Mhz */ u8 base_freq; + /* Frequency index */ + u32 FRQ; + u16 cas_supported; /* Latencies are in units of ns, scaled by x256 */ u32 tCK; diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index fa636565a2..6484139a94 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -203,6 +203,9 @@ static void find_cas_tck(ramctr_timing *ctrl) } } + /* Frequency multiplier */ + ctrl->FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; @@ -363,16 +366,14 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); - - ctrl->tREFI = get_REFI(FRQ, ctrl->base_freq); - ctrl->tMOD = get_MOD(FRQ, ctrl->base_freq); - ctrl->tXSOffset = get_XSOffset(FRQ, ctrl->base_freq); - ctrl->tWLO = get_WLO(FRQ, ctrl->base_freq); - ctrl->tCKE = get_CKE(FRQ, ctrl->base_freq); - ctrl->tXPDLL = get_XPDLL(FRQ, ctrl->base_freq); - ctrl->tXP = get_XP(FRQ, ctrl->base_freq); - ctrl->tAONPD = get_AONPD(FRQ, ctrl->base_freq); + ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); + ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); + ctrl->tXSOffset = get_XSOffset(ctrl->FRQ, ctrl->base_freq); + ctrl->tWLO = get_WLO(ctrl->FRQ, ctrl->base_freq); + ctrl->tCKE = get_CKE(ctrl->FRQ, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); + ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); } static void dram_freq(ramctr_timing *ctrl) @@ -391,9 +392,6 @@ static void dram_freq(ramctr_timing *ctrl) /* Step 1 - Set target PCU frequency */ find_cas_tck(ctrl); - /* Frequency multiplier */ - const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); - /* * The PLL will never lock if the required frequency is already set. * Exit early to prevent a system hang. @@ -404,7 +402,7 @@ static void dram_freq(ramctr_timing *ctrl) return; /* Step 2 - Select frequency in the MCU */ - reg1 = FRQ; + reg1 = ctrl->FRQ; if (ctrl->base_freq == 100) reg1 |= 0x100; /* Enable 100Mhz REF clock */ @@ -422,7 +420,7 @@ static void dram_freq(ramctr_timing *ctrl) /* Step 3 - Verify lock frequency */ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; - if (val2 >= FRQ) { + if (val2 >= ctrl->FRQ) { printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", (1000 << 8) / ctrl->tCK); return; @@ -434,7 +432,6 @@ static void dram_freq(ramctr_timing *ctrl) static void dram_ioregs(ramctr_timing *ctrl) { - const u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); u32 reg; int channel; @@ -462,7 +459,7 @@ static void dram_ioregs(ramctr_timing *ctrl) printram("done\n"); /* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(FRQ, ctrl->base_freq); + MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->FRQ, ctrl->base_freq); printram("COMP2 done\n"); /* Set COMP1 */ From 65f05505a6b7e9e1e9b45c9f6aae34fccd7a7f32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 12 Feb 2020 13:10:23 +0100 Subject: [PATCH 0618/1463] superio/nuvoton/nct5104d: add chip config option to reset GPIOs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define a chip option to explicitly soft reset all enabled GPIOs to default state. TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration using nctgpio module and check whether GPIOs are reset after reboot Signed-off-by: Michał Żygowski Change-Id: Iae4205574800138402cbc95f4948167265a80d15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38850 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/pcengines/apu1/devicetree.cb | 1 + .../apu2/variants/apu2/devicetree.cb | 1 + .../apu2/variants/apu3/devicetree.cb | 1 + .../apu2/variants/apu4/devicetree.cb | 1 + src/superio/nuvoton/nct5104d/chip.h | 1 + src/superio/nuvoton/nct5104d/superio.c | 55 ++++++++++--------- 6 files changed, 35 insertions(+), 25 deletions(-) diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 4974cfbfbb..dd851a7133 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -41,6 +41,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 3528e86362..672155b049 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 13643a42c0..d743da6b66 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index f5082d466f..c08e5b24e2 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/superio/nuvoton/nct5104d/chip.h b/src/superio/nuvoton/nct5104d/chip.h index 5b790372ad..ad1c302d21 100644 --- a/src/superio/nuvoton/nct5104d/chip.h +++ b/src/superio/nuvoton/nct5104d/chip.h @@ -6,6 +6,7 @@ struct superio_nuvoton_nct5104d_config { u8 irq_trigger_type; + u8 reset_gpios; }; #endif diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index e49a7cbda5..55700261e1 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -98,42 +99,45 @@ static void route_pins_to_uart(struct device *dev, bool to_uart) static void reset_gpio_default_in(struct device *dev) { pnp_set_logical_device(dev); - - /* Soft reset GPIOs to default state: IN */ - switch (dev->path.pnp.device) { - case NCT5104D_GPIO0: - pnp_write_config(dev, NCT5104D_GPIO0_IO, 0xFF); - break; - case NCT5104D_GPIO1: - pnp_write_config(dev, NCT5104D_GPIO1_IO, 0xFF); - break; - case NCT5104D_GPIO6: - pnp_write_config(dev, NCT5104D_GPIO6_IO, 0xFF); - break; - default: - break; - } + /* + * Soft reset GPIOs to default state: IN. + * The main GPIO LDN holds registers that configure the pins as output + * or input. These registers are located at offset 0xE0 plus the GPIO + * bank number multiplied by 4: 0xE0 for GPIO0, 0xE4 for GPIO1 and + * 0xF8 for GPIO6. + */ + pnp_write_config(dev, NCT5104D_GPIO0_IO + (dev->path.pnp.device >> 8) * 4, 0xFF); } static void reset_gpio_default_od(struct device *dev) { struct device *gpio0, *gpio1, *gpio6; + pnp_set_logical_device(dev); + gpio0 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO0); gpio1 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO1); gpio6 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO6); - pnp_set_logical_device(dev); - - /* Soft reset GPIOs to default state: Open-drain */ + /* + * Soft reset GPIOs to default state: Open-drain. + * The NCT5104D_GPIO_PP_OD LDN holds registers (1 for each GPIO bank) + * that configure each GPIO pin to be open dain or push pull. System + * reset is known to not reset the values in this register. The + * registers are located at offsets begginign from 0xE0 plus GPIO bank + * number, i.e. 0xE0 for GPIO0, 0xE1 for GPIO1 and 0xE6 for GPIO6. + */ if (gpio0 && gpio0->enabled) - pnp_write_config(dev, NCT5104D_GPIO0_PP_OD, 0xFF); + pnp_write_config(dev, + (gpio0->path.pnp.device >> 8) + NCT5104D_GPIO0_PP_OD, 0xFF); if (gpio1 && gpio1->enabled) - pnp_write_config(dev, NCT5104D_GPIO1_PP_OD, 0xFF); + pnp_write_config(dev, + (gpio1->path.pnp.device >> 8) + NCT5104D_GPIO0_PP_OD, 0xFF); if (gpio6 && gpio6->enabled) - pnp_write_config(dev, NCT5104D_GPIO6_PP_OD, 0xFF); + pnp_write_config(dev, + (gpio6->path.pnp.device >> 8) + NCT5104D_GPIO0_PP_OD, 0xFF); } static void disable_gpio_io_port(struct device *dev) @@ -181,13 +185,14 @@ static void nct5104d_init(struct device *dev) case NCT5104D_GPIO0: case NCT5104D_GPIO1: route_pins_to_uart(dev, false); - reset_gpio_default_in(dev); - break; + /* FALLTHROUGH */ case NCT5104D_GPIO6: - reset_gpio_default_in(dev); + if (conf->reset_gpios) + reset_gpio_default_in(dev); break; case NCT5104D_GPIO_PP_OD: - reset_gpio_default_od(dev); + if (conf->reset_gpios) + reset_gpio_default_od(dev); break; case NCT5104D_GPIO_IO: disable_gpio_io_port(dev); From 5e20c1cbc841ca2174cdc025fa4ce95d3d717c29 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 14 Mar 2020 17:36:10 +0100 Subject: [PATCH 0619/1463] util/board-status: Reject logs from dirty images Currently, there are a lot of uploads in the board status repository, where the logs say, that the coreboot image or payload were built from a dirty source tree. Add a check to reject such uploads. Change-Id: I920e26a10f74e1f3b9b4e5f8c9284c59692a519b Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39562 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/board_status/board_status.sh | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 6d6854d071..a990ce505e 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -426,6 +426,13 @@ else echo "Getting coreboot boot log" cmd $LOCAL "$cbmem_cmd -1" "${tmpdir}/${results}/coreboot_console.txt" + if [ $(grep -- -dirty "${tmpdir}/${results}/coreboot_console.txt") ]; then + echo "coreboot or the payload are built from a source tree in a" \ + "dirty state, making it hard to reproduce the result. Please" \ + "check in your source tree with 'git status'." + exit $EXIT_FAILURE + fi + echo "Getting timestamp data" cmd_nonfatal $LOCAL "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" From a1b15172d7f0303e8a1fe147a778d73d4dc26b1a Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Thu, 12 Mar 2020 18:15:34 +0800 Subject: [PATCH 0620/1463] create stdio.h and stdarg.h for {,v}snprintf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sometimes coreboot needs to compile external code (e.g. vboot_reference) using its own set of system header files. When these headers don't line up with C Standard Library, it causes problems. Create stdio.h and stdarg.h header files. Relocate snprintf into stdio.h and vsnprintf into stdarg.h from string.h. Chain include these header files from string.h, since coreboot doesn't care so much about the legacy POSIX location of these functions. Also move va_* definitions from vtxprintf.h into stdarg.h where they belong (in POSIX). Just use our own definitions regardless of GCC or LLVM. Add string.h header to a few C files which should have had it in the first place. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I7223cb96e745e11c82d4012c6671a51ced3297c2 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/39468 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Julius Werner --- src/include/console/vtxprintf.h | 12 ----------- src/include/stdarg.h | 20 +++++++++++++++++++ src/include/stdio.h | 15 ++++++++++++++ src/include/string.h | 8 ++++---- src/mainboard/intel/tglrvp/mainboard.c | 1 + src/soc/intel/xeon_sp/acpi.c | 1 + src/superio/common/ssdt.c | 1 + .../cavium/bdk/libbdk-dram/bdk-dram-test.c | 1 + 8 files changed, 43 insertions(+), 16 deletions(-) create mode 100644 src/include/stdarg.h create mode 100644 src/include/stdio.h diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index f6e985c09d..9babd89322 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -15,19 +15,7 @@ #ifndef __CONSOLE_VTXPRINTF_H #define __CONSOLE_VTXPRINTF_H -/* With GCC we use -nostdinc -ffreestanding to keep out system includes. - * Unfortunately this also gets us rid of the _compiler_ includes, like - * stdarg.h. To work around the issue, we define varargs directly here. - * On LLVM we can still just include stdarg.h. - */ -#ifdef __GNUC__ -#define va_start(v, l) __builtin_va_start(v, l) -#define va_end(v) __builtin_va_end(v) -#define va_arg(v, l) __builtin_va_arg(v, l) -typedef __builtin_va_list va_list; -#else #include -#endif int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data); diff --git a/src/include/stdarg.h b/src/include/stdarg.h new file mode 100644 index 0000000000..c5a8cd8dbe --- /dev/null +++ b/src/include/stdarg.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * Note: This file is only for POSIX compatibility, and is meant to be + * chain-included via string.h. + */ + +#ifndef STDARG_H +#define STDARG_H + +#include + +#define va_start(v, l) __builtin_va_start(v, l) +#define va_end(v) __builtin_va_end(v) +#define va_arg(v, l) __builtin_va_arg(v, l) +typedef __builtin_va_list va_list; + +int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); + +#endif /* STDARG_H */ diff --git a/src/include/stdio.h b/src/include/stdio.h new file mode 100644 index 0000000000..d59b9411ee --- /dev/null +++ b/src/include/stdio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * Note: This file is only for POSIX compatibility, and is meant to be + * chain-included via string.h. + */ + +#ifndef STDIO_H +#define STDIO_H + +#include + +int snprintf(char *buf, size_t size, const char *fmt, ...); + +#endif /* STDIO_H */ diff --git a/src/include/string.h b/src/include/string.h index b55ca5fba6..f923ca5c02 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef STRING_H #define STRING_H +#include #include - -#include +#include /* Stringify a token */ #ifndef STRINGIFY @@ -16,8 +18,6 @@ void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); -int snprintf(char *buf, size_t size, const char *fmt, ...); -int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); size_t strnlen(const char *src, size_t max); diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index e773df5883..1f24e8baa4 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -18,6 +18,7 @@ #include #include #include +#include const char *smbios_system_sku(void) { diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index e10e615cad..4ca406d79e 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "chip.h" static int acpi_sci_irq(void) diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index e31660fad1..f5ad765aa1 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -10,6 +10,7 @@ #include #include #include +#include struct superio_dev { const char *acpi_hid; diff --git a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c index 9c78667116..9304e78d60 100644 --- a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c +++ b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c @@ -37,6 +37,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include +#include #include "libbdk-arch/bdk-csrs-gti.h" #include "libbdk-arch/bdk-csrs-ocx.h" From 662da6cf7b181ea2787ba001d9cbb6d41916abec Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 16 Mar 2020 22:46:57 -0700 Subject: [PATCH 0621/1463] soc/intel/xeon_sp: Refactor code to allow for additional CPUs types Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/Kconfig | 3 +- src/mainboard/ocp/tiogapass/devicetree.cb | 2 +- src/mainboard/ocp/tiogapass/dsdt.asl | 4 +- src/soc/intel/xeon_sp/Kconfig | 37 +++------- src/soc/intel/xeon_sp/Makefile.inc | 42 ++--------- .../intel/xeon_sp/{bootblock => }/bootblock.c | 0 .../include/soc/{soc_util.h => util.h} | 43 ++---------- src/soc/intel/xeon_sp/lpc.c | 3 +- src/soc/intel/xeon_sp/romstage.c | 28 +------- src/soc/intel/xeon_sp/skx/Kconfig | 69 +++++++++++++++++++ src/soc/intel/xeon_sp/skx/Makefile.inc | 36 ++++++++++ src/soc/intel/xeon_sp/{ => skx}/acpi.c | 2 +- .../xeon_sp/{ => skx}/acpi/globalnvs.asl | 0 .../intel/xeon_sp/{ => skx}/acpi/iiostack.asl | 0 .../intel/xeon_sp/{ => skx}/acpi/pci_irq.asl | 0 .../intel/xeon_sp/{ => skx}/acpi/uncore.asl | 0 .../xeon_sp/{ => skx}/acpi/uncore_irq.asl | 0 src/soc/intel/xeon_sp/{ => skx}/chip.c | 4 +- src/soc/intel/xeon_sp/{ => skx}/chip.h | 4 +- src/soc/intel/xeon_sp/{ => skx}/cpu.c | 0 src/soc/intel/xeon_sp/{ => skx}/hob_display.c | 0 .../xeon_sp/{ => skx}/include/soc/acpi.h | 0 .../intel/xeon_sp/{ => skx}/include/soc/cpu.h | 0 .../{ => skx}/include/soc/gpio_soc_defs.h | 0 .../intel/xeon_sp/{ => skx}/include/soc/irq.h | 0 .../intel/xeon_sp/{ => skx}/include/soc/msr.h | 0 .../intel/xeon_sp/{ => skx}/include/soc/nvs.h | 0 .../xeon_sp/{ => skx}/include/soc/pci_devs.h | 0 .../xeon_sp/{ => skx}/include/soc/ramstage.h | 0 .../intel/xeon_sp/skx/include/soc/soc_util.h | 39 +++++++++++ src/soc/intel/xeon_sp/skx/romstage.c | 30 ++++++++ src/soc/intel/xeon_sp/{ => skx}/soc_util.c | 55 +-------------- src/soc/intel/xeon_sp/{ => skx}/upd_display.c | 0 src/soc/intel/xeon_sp/uncore.c | 3 +- src/soc/intel/xeon_sp/util.c | 56 +++++++++++++++ 35 files changed, 269 insertions(+), 191 deletions(-) rename src/soc/intel/xeon_sp/{bootblock => }/bootblock.c (100%) rename src/soc/intel/xeon_sp/include/soc/{soc_util.h => util.h} (60%) create mode 100644 src/soc/intel/xeon_sp/skx/Kconfig create mode 100644 src/soc/intel/xeon_sp/skx/Makefile.inc rename src/soc/intel/xeon_sp/{ => skx}/acpi.c (99%) rename src/soc/intel/xeon_sp/{ => skx}/acpi/globalnvs.asl (100%) rename src/soc/intel/xeon_sp/{ => skx}/acpi/iiostack.asl (100%) rename src/soc/intel/xeon_sp/{ => skx}/acpi/pci_irq.asl (100%) rename src/soc/intel/xeon_sp/{ => skx}/acpi/uncore.asl (100%) rename src/soc/intel/xeon_sp/{ => skx}/acpi/uncore_irq.asl (100%) rename src/soc/intel/xeon_sp/{ => skx}/chip.c (99%) rename src/soc/intel/xeon_sp/{ => skx}/chip.h (95%) rename src/soc/intel/xeon_sp/{ => skx}/cpu.c (100%) rename src/soc/intel/xeon_sp/{ => skx}/hob_display.c (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/acpi.h (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/cpu.h (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/gpio_soc_defs.h (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/irq.h (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/msr.h (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/nvs.h (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/pci_devs.h (100%) rename src/soc/intel/xeon_sp/{ => skx}/include/soc/ramstage.h (100%) create mode 100644 src/soc/intel/xeon_sp/skx/include/soc/soc_util.h create mode 100644 src/soc/intel/xeon_sp/skx/romstage.c rename src/soc/intel/xeon_sp/{ => skx}/soc_util.c (91%) rename src/soc/intel/xeon_sp/{ => skx}/upd_display.c (100%) create mode 100644 src/soc/intel/xeon_sp/util.c diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 9dbc066f10..1d501e6db0 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -19,10 +19,9 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES - select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 - select FSP_CAR select IPMI_KCS + select SOC_INTEL_SKYLAKE_SP config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index c2eddf270c..51e6a62eb1 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -chip soc/intel/xeon_sp +chip soc/intel/xeon_sp/skx register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 41c006bc92..9d33865271 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -28,12 +28,12 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include #include // Xeon-SP ACPI tables Scope (\_SB) { - #include + #include } } diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 1f015b15a3..223329d79d 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -13,14 +13,20 @@ ## GNU General Public License for more details. ## -config SOC_INTEL_XEON_SP +source "src/soc/intel/xeon_sp/skx/Kconfig" + +config XEON_SP_COMMON_BASE bool + +config SOC_INTEL_SKYLAKE_SP + bool + select XEON_SP_COMMON_BASE help - Intel Xeon SP support + Intel Skylake-SP support -if SOC_INTEL_XEON_SP +if XEON_SP_COMMON_BASE -config CPU_SPECIFIC_OPTIONS +config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 @@ -54,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_CAR config MAINBOARD_USES_FSP2_0 bool @@ -67,11 +74,6 @@ config USE_FSP2_0_DRIVER select POSTCAR_CONSOLE select POSTCAR_STAGE -config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" - config MAX_SOCKET int default 2 @@ -88,14 +90,6 @@ config PCR_BASE_ADDRESS help This option allows you to select MMIO Base Address of sideband bus. -config DCACHE_RAM_BASE - hex - default 0xfe800000 - -config DCACHE_RAM_SIZE - hex - default 0x200000 - config DCACHE_BSP_STACK_SIZE hex default 0x10000 @@ -104,14 +98,6 @@ config MMCONF_BASE_ADDRESS hex default 0x80000000 -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - config C_ENV_BOOTBLOCK_SIZE hex default 0xC000 @@ -120,5 +106,4 @@ config HEAP_SIZE hex default 0x80000 - endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 59350bf967..e05fea2448 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -13,46 +13,16 @@ ## GNU General Public License for more details. ## -ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y) +ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx -bootblock-y += bootblock/bootblock.c -bootblock-y += lpc.c -bootblock-y += spi.c - -postcar-y += soc_util.c +bootblock-y += bootblock.c spi.c lpc.c +romstage-y += romstage.c reset.c util.c spi.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c postcar-y += spi.c -romstage-y += soc_util.c -romstage-y += reset.c -romstage-y += romstage.c -romstage-y += soc_util.c -romstage-y += spi.c -romstage-y += hob_display.c -romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c - -ramstage-y += soc_util.c -ramstage-y += uncore.c -ramstage-y += reset.c -ramstage-y += chip.c -ramstage-y += soc_util.c -ramstage-y += lpc.c -ramstage-y += cpu.c -ramstage-y += spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += hob_display.c - CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) -endif ## CONFIG_SOC_INTEL_XEON_SP +endif ## XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c similarity index 100% rename from src/soc/intel/xeon_sp/bootblock/bootblock.c rename to src/soc/intel/xeon_sp/bootblock.c diff --git a/src/soc/intel/xeon_sp/include/soc/soc_util.h b/src/soc/intel/xeon_sp/include/soc/util.h similarity index 60% rename from src/soc/intel/xeon_sp/include/soc/soc_util.h rename to src/soc/intel/xeon_sp/include/soc/util.h index 47e5be3172..6f907f6ff0 100644 --- a/src/soc/intel/xeon_sp/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -13,13 +13,14 @@ * GNU General Public License for more details. */ +#ifndef _XEON_SP_SOC_UTIL_H_ +#define _XEON_SP_SOC_UTIL_H_ -#ifndef _SOC_UTIL_H_ -#define _SOC_UTIL_H_ +#include -#include -#include -#include +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); +void unlock_pam_regions(void); +void get_stack_busnos(uint32_t *bus); #define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ @@ -46,34 +47,4 @@ #define FUNC_EXIT() \ printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) -struct iiostack_resource { - uint8_t no_of_stacks; - STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; -}; - -uintptr_t get_tolm(uint32_t bus); -void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit); -uintptr_t get_cha_mmcfg_base(uint32_t bus); -uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory - -uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); - -void get_stack_busnos(uint32_t *bus); -void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); -void get_iiostack_info(struct iiostack_resource *info); - -int get_threads_per_package(void); -int get_platform_thread_count(void); -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); - -unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem); -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, - uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); - -void unlock_pam_regions(void); -void xeonsp_init_cpu_config(void); -void set_bios_init_completion(void); -void config_reset_cpl3_csrs(void); - -#endif /* _SOC_UTIL_H_ */ +#endif diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 6dc2c41fe0..c2f1f89181 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -17,11 +17,10 @@ #include #include #include -#include #include #include -#include "chip.h" +#include static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { { 0, 0 } diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index a519663134..9d3665c9fe 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -18,9 +18,9 @@ #include #include #include +#include #include -#include -#include "chip.h" +#include asmlinkage void car_stage_entry(void) { @@ -55,27 +55,3 @@ asmlinkage void car_stage_entry(void) run_postcar_phase(&pcf); } - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) -{ -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const config_t *config = config_of_soc(); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - mupd->FspmUpdVersion = FSP_UPD_VERSION; - - // ErrorLevel - 0 (disable) to 8 (verbose) - m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; - m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; - - soc_memory_init_params(m_cfg); - - mainboard_memory_init_params(mupd); - - m_cfg->VTdConfig.VTdSupport = config->vtd_support; - m_cfg->VTdConfig.CoherencySupport = config->coherency_support; - m_cfg->VTdConfig.ATS = config->ats_support; -} diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig new file mode 100644 index 0000000000..e9c3c6b189 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -0,0 +1,69 @@ +## +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. +## + +if SOC_INTEL_SKYLAKE_SP + +config MAINBOARD_USES_FSP2_0 + bool + default y + +config USE_FSP2_0_DRIVER + def_bool y + depends on MAINBOARD_USES_FSP2_0 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_CONSOLE + select POSTCAR_STAGE + +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" + +config MAX_SOCKET + int + default 2 + +# For 2S config, the number of cpus could be as high as +# 2 threads * 20 cores * 2 sockets +config MAX_CPUS + int + default 80 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config DCACHE_RAM_BASE + hex + default 0xfe800000 + +config DCACHE_RAM_SIZE + hex + default 0x200000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x10000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config HEAP_SIZE + hex + default 0x80000 + +endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc new file mode 100644 index 0000000000..ee7ecc4430 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -0,0 +1,36 @@ +## +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. +## + +ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) + +subdirs-y += ../../../../cpu/intel/microcode +subdirs-y += ../../../../cpu/intel/turbo +subdirs-y += ../../../../cpu/x86/lapic +subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/x86/cache +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm + +postcar-y += soc_util.c + +romstage-y += soc_util.c +romstage-y += romstage.c +romstage-y += soc_util.c +romstage-y += hob_display.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c + +ramstage-y += soc_util.c +ramstage-y += chip.c +ramstage-y += soc_util.c +ramstage-y += cpu.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-y += hob_display.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx + +endif ## CONFIG_SOC_INTEL_SKYLAKE_SP diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c similarity index 99% rename from src/soc/intel/xeon_sp/acpi.c rename to src/soc/intel/xeon_sp/skx/acpi.c index 4ca406d79e..2abdf91eaf 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -880,7 +880,7 @@ unsigned long northbridge_write_acpi_tables(struct device *device, acpi_slit_t *slit; acpi_dmar_t *dmar; - const struct soc_intel_xeon_sp_config *const config = config_of(device); + const struct soc_intel_xeon_sp_skx_config *const config = config_of(device); /* SRAT */ current = ALIGN(current, 8); diff --git a/src/soc/intel/xeon_sp/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/globalnvs.asl rename to src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/iiostack.asl rename to src/soc/intel/xeon_sp/skx/acpi/iiostack.asl diff --git a/src/soc/intel/xeon_sp/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/pci_irq.asl rename to src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/uncore.asl rename to src/soc/intel/xeon_sp/skx/acpi/uncore.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/uncore_irq.asl rename to src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl diff --git a/src/soc/intel/xeon_sp/chip.c b/src/soc/intel/xeon_sp/skx/chip.c similarity index 99% rename from src/soc/intel/xeon_sp/chip.c rename to src/soc/intel/xeon_sp/skx/chip.c index 0aa61207de..7a737ac2b4 100644 --- a/src/soc/intel/xeon_sp/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -589,8 +589,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) mainboard_silicon_init_params(silupd); } -struct chip_operations soc_intel_xeon_sp_ops = { - CHIP_NAME("Intel Xeon-SP SOC") +struct chip_operations soc_intel_xeon_sp_skx_ops = { + CHIP_NAME("Intel Skylake-SP") .enable_dev = soc_enable_dev, .init = soc_init, .final = soc_final diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/skx/chip.h similarity index 95% rename from src/soc/intel/xeon_sp/chip.h rename to src/soc/intel/xeon_sp/skx/chip.h index 94726f35eb..7565d6c11a 100644 --- a/src/soc/intel/xeon_sp/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -21,7 +21,7 @@ #include #include -struct soc_intel_xeon_sp_config { +struct soc_intel_xeon_sp_skx_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; @@ -86,6 +86,6 @@ struct soc_intel_xeon_sp_config { extern struct chip_operations soc_intel_xeon_sp_ops; -typedef struct soc_intel_xeon_sp_config config_t; +typedef struct soc_intel_xeon_sp_skx_config config_t; #endif diff --git a/src/soc/intel/xeon_sp/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c similarity index 100% rename from src/soc/intel/xeon_sp/cpu.c rename to src/soc/intel/xeon_sp/skx/cpu.c diff --git a/src/soc/intel/xeon_sp/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c similarity index 100% rename from src/soc/intel/xeon_sp/hob_display.c rename to src/soc/intel/xeon_sp/skx/hob_display.c diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/acpi.h rename to src/soc/intel/xeon_sp/skx/include/soc/acpi.h diff --git a/src/soc/intel/xeon_sp/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/cpu.h rename to src/soc/intel/xeon_sp/skx/include/soc/cpu.h diff --git a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h rename to src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/skx/include/soc/irq.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/irq.h rename to src/soc/intel/xeon_sp/skx/include/soc/irq.h diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/msr.h rename to src/soc/intel/xeon_sp/skx/include/soc/msr.h diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/nvs.h rename to src/soc/intel/xeon_sp/skx/include/soc/nvs.h diff --git a/src/soc/intel/xeon_sp/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pci_devs.h rename to src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/ramstage.h rename to src/soc/intel/xeon_sp/skx/include/soc/ramstage.h diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h new file mode 100644 index 0000000000..8ba4b29688 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_UTIL_H_ +#define _SOC_UTIL_H_ + +#include +#include +#include +#include + +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; +}; + +uintptr_t get_tolm(uint32_t bus); +void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit); +uintptr_t get_cha_mmcfg_base(uint32_t bus); +uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory + +uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); + +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); +void get_iiostack_info(struct iiostack_resource *info); + +int get_threads_per_package(void); +int get_platform_thread_count(void); +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); + +unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem); +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, + uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); + +void xeonsp_init_cpu_config(void); +void set_bios_init_completion(void); +void config_reset_cpl3_csrs(void); + +#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c new file mode 100644 index 0000000000..947930f906 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const config_t *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + mupd->FspmUpdVersion = FSP_UPD_VERSION; + + // ErrorLevel - 0 (disable) to 8 (verbose) + m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; + m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; + + mainboard_memory_init_params(mupd); + + m_cfg->VTdConfig.VTdSupport = config->vtd_support; + m_cfg->VTdConfig.CoherencySupport = config->coherency_support; + m_cfg->VTdConfig.ATS = config->ats_support; +} diff --git a/src/soc/intel/xeon_sp/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c similarity index 91% rename from src/soc/intel/xeon_sp/soc_util.c rename to src/soc/intel/xeon_sp/skx/soc_util.c index 6ba9f8eb85..edacafdcfa 100644 --- a/src/soc/intel/xeon_sp/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -30,6 +30,7 @@ #include #include #include +#include #include /* @@ -69,24 +70,6 @@ uintptr_t get_cha_mmcfg_base(uint32_t bus) return addr; } -/* - * Get Socket 0 CPUBUSNO(0), CPUBUSNO(1) PCI bus numbers UBOX (B0:D8:F2:Offset_CCh) - * TODO: D0h - */ -void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) -{ - uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, - UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); - if (bus0) - *bus0 = (bus & 0xff); - if (bus1) - *bus1 = (bus >> 8) & 0xff; - if (bus2) - *bus2 = (bus >> 16) & 0xff; - if (bus3) - *bus3 = (bus >> 24) & 0xff; -} - uint32_t top_of_32bit_ram(void) { uintptr_t mmcfg, tolm; @@ -153,42 +136,6 @@ uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; } -/* bus needs to be of size 6 (MAX_IIO_STACK) */ -void get_stack_busnos(uint32_t *bus) -{ - uint32_t reg1, reg2; - - reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xcc); - reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xd0); - - for (int i = 0; i < 4; ++i) - bus[i] = ((reg1 >> (i * 8)) & 0xff); - for (int i = 0; i < 2; ++i) - bus[4+i] = ((reg2 >> (i * 8)) & 0xff); -} - -void unlock_pam_regions(void) -{ - uint32_t bus1 = 0; - uint32_t pam0123_unlock_dram = 0x33333330; - uint32_t pam456_unlock_dram = 0x00333333; - - get_cpubusnos(NULL, &bus1, NULL, NULL); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM456_CSR, pam456_unlock_dram); - - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); - printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", - __FILE__, __func__, reg1, reg2); -} - /* return 1 if command timed out else 0 */ static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, uint32_t target) diff --git a/src/soc/intel/xeon_sp/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c similarity index 100% rename from src/soc/intel/xeon_sp/upd_display.c rename to src/soc/intel/xeon_sp/skx/upd_display.c diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 34f00d88eb..c72c6c3ffc 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -21,7 +21,8 @@ #include #include #include -#include +#include +#include struct map_entry { uint32_t reg; diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c new file mode 100644 index 0000000000..cbac1adc4b --- /dev/null +++ b/src/soc/intel/xeon_sp/util.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include + +void get_stack_busnos(uint32_t *bus) +{ + uint32_t reg1, reg2; + + reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xcc); + reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xd0); + + for (int i = 0; i < 4; ++i) + bus[i] = ((reg1 >> (i * 8)) & 0xff); + for (int i = 0; i < 2; ++i) + bus[4+i] = ((reg2 >> (i * 8)) & 0xff); +} + +void unlock_pam_regions(void) +{ + uint32_t bus1 = 0; + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + + get_cpubusnos(NULL, &bus1, NULL, NULL); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) +{ + uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, + UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); + if (bus0) + *bus0 = (bus & 0xff); + if (bus1) + *bus1 = (bus >> 8) & 0xff; + if (bus2) + *bus2 = (bus >> 16) & 0xff; + if (bus3) + *bus3 = (bus >> 24) & 0xff; +} From 403f215cb4e2486d0b89ec97978263948fbc7ce6 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 20 Mar 2020 13:59:45 -0700 Subject: [PATCH 0622/1463] configs: Add builder Tioga Pass config Add config file that can be used to build a fully working Tioga Pass image. Signed-off-by: Andrey Petrov Change-Id: Ifff3591ef9fff40117c60e85900bde9c3729bd94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39715 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- configs/builder/config.ocp.tiogapass | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 configs/builder/config.ocp.tiogapass diff --git a/configs/builder/config.ocp.tiogapass b/configs/builder/config.ocp.tiogapass new file mode 100644 index 0000000000..9121431b5b --- /dev/null +++ b/configs/builder/config.ocp.tiogapass @@ -0,0 +1,17 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass + +CONFIG_VENDOR_OCP=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/tiogapass/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/tiogapass/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/tiogapass/Server_S.fd" +CONFIG_ME_BIN_PATH="site-local/tiogapass/me.bin" +CONFIG_IFD_BIN_PATH="site-local/tiogapass/descriptor.bin" +CONFIG_USE_BLOBS=y From 335384d2b75eb0266c6f13b52e20b2d3bba390ea Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Sun, 22 Mar 2020 22:27:44 -0700 Subject: [PATCH 0623/1463] soc/intel/xeon_sp: Configure P2SB BAR in bootblock In order to use early serial output we need to enable P2SB BAR0, because that allows PCR access to PCH registers. TEST=tested on OCP Tioga Pass Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/bootblock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 453c383897..8e236f2942 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -21,6 +21,7 @@ #include #include #include +#include const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -54,6 +55,11 @@ void bootblock_soc_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); pch_enable_lpc(); + + /* Set up P2SB BAR. This is needed for PCR to work */ + uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); + pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); + pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); } void bootblock_soc_init(void) From 2a82f744d460afee2218e072a3b8a31a4c6efb11 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 25 Mar 2020 12:52:50 +1100 Subject: [PATCH 0624/1463] drivers/net/r8168: Split fetch_mac_string_vpd() logic up Orginally fetch_mac_string_vpd() has been special cased around a device_index of 0/1 that causes a number of edge cases and complexity when attempting to refactor to deal with the revised VPD format. The following change prepares the ground work by splitting up the functional into logical workers where we can deal with each edge case in a more bounded way. The background here is that the format for VPD has changed s.t. the first NIC should always have a zero concat to the end. The details of that can be found here: https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn BUG=b:152157720 BRANCH=none TEST=none Change-Id: Idc886d9b0b3037c91f40b742437e4e50711b5f00 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39811 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/net/r8168.c | 102 +++++++++++++++++++++++----------------- 1 file changed, 59 insertions(+), 43 deletions(-) diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 07069aa88b..fcdac90481 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -92,12 +92,49 @@ static u8 get_hex_digit(const u8 c) #define MACLEN 17 -static enum cb_err fetch_mac_string_vpd(u8 *macstrbuf, const u8 device_index) +/* Returns MAC address based on the key that is passed in. */ +static enum cb_err fetch_mac_vpd_key(u8 *macstrbuf, const char *vpd_key) { struct region_device rdev; void *search_address; size_t search_length; size_t offset; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev)) { + printk(BIOS_ERR, "Error: Couldn't find RO_VPD region."); + return CB_ERR; + } + search_address = rdev_mmap_full(&rdev); + if (search_address == NULL) { + printk(BIOS_ERR, "LAN: VPD not found.\n"); + return CB_ERR; + } + + search_length = region_device_sz(&rdev); + offset = search(vpd_key, search_address, strlen(vpd_key), + search_length); + + if (offset == search_length) { + printk(BIOS_ERR, + "Error: Could not locate '%s' in VPD\n", vpd_key); + return CB_ERR; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", vpd_key); + + offset += strlen(vpd_key) + 1; /* move to next character */ + + if (offset + MACLEN > search_length) { + printk(BIOS_ERR, "Search result too small!\n"); + return CB_ERR; + } + memcpy(macstrbuf, search_address + offset, MACLEN); + + return CB_SUCCESS; +} + +/* Prepares vpd_key by concatenating ethernet_mac with device_index */ +static enum cb_err fetch_mac_vpd_dev_idx(u8 *macstrbuf, u8 device_index) +{ char key[] = "ethernet_mac "; /* Leave a space at tail to stuff an index */ /* @@ -112,35 +149,29 @@ static enum cb_err fetch_mac_string_vpd(u8 *macstrbuf, const u8 device_index) /* Translate index number from integer to ascii */ key[DEVICE_INDEX_BYTE] = (device_index - 1) + '0'; - if (fmap_locate_area_as_rdev("RO_VPD", &rdev)) { - printk(BIOS_ERR, "Error: Couldn't find RO_VPD region."); - return CB_ERR; - } - search_address = rdev_mmap_full(&rdev); - if (search_address == NULL) { - printk(BIOS_ERR, "LAN: VPD not found.\n"); - return CB_ERR; + return fetch_mac_vpd_key(macstrbuf, key); +} + +static void fetch_mac_string_vpd(struct drivers_net_config *config, u8 *macstrbuf) +{ + if (!config) + return; + + /* Current implementation is up to 10 NIC cards */ + if (config->device_index > MAX_DEVICE_SUPPORT) { + printk(BIOS_ERR, "r8168: the maximum device_index should be less then %d\n." + " Using default 00:e0:4c:00:c0:b0\n", MAX_DEVICE_SUPPORT); + return; } - search_length = region_device_sz(&rdev); - offset = search(key, search_address, strlen(key), - search_length); + /* check "ethernet_mac" first when the device index is 1 */ + if (config->device_index == 1 && + fetch_mac_vpd_dev_idx(macstrbuf, 0) == CB_SUCCESS) + return; - if (offset == search_length) { - printk(BIOS_ERR, - "Error: Could not locate '%s' in VPD\n", key); - return CB_ERR; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += strlen(key) + 1; /* move to next character */ - - if (offset + MACLEN > search_length) { - printk(BIOS_ERR, "Search result too small!\n"); - return CB_ERR; - } - memcpy(macstrbuf, search_address + offset, MACLEN); - return CB_SUCCESS; + if (fetch_mac_vpd_dev_idx(macstrbuf, config->device_index) != CB_SUCCESS) + printk(BIOS_ERR, "r8168: mac address not found in VPD," + " using default 00:e0:4c:00:c0:b0\n"); } static enum cb_err fetch_mac_string_cbfs(u8 *macstrbuf) @@ -186,25 +217,10 @@ static void program_mac_address(struct device *dev, u16 io_base) /* Default MAC Address of 00:E0:4C:00:C0:B0 */ u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 }; struct drivers_net_config *config = dev->chip_info; - bool mac_found = false; /* check the VPD for the mac address */ if (CONFIG(RT8168_GET_MAC_FROM_VPD)) { - /* Current implementation is up to 10 NIC cards */ - if (config && config->device_index <= MAX_DEVICE_SUPPORT) { - /* check "ethernet_mac" first when the device index is 1 */ - if (config->device_index == 1 && - fetch_mac_string_vpd(macstrbuf, 0) == CB_SUCCESS) - mac_found = true; - if (!mac_found && fetch_mac_string_vpd(macstrbuf, - config->device_index) != CB_SUCCESS) - printk(BIOS_ERR, "r8168: mac address not found in VPD," - " using default 00:e0:4c:00:c0:b0\n"); - } else { - printk(BIOS_ERR, "r8168: the maximum device_index should be" - " less then %d\n. Using default 00:e0:4c:00:c0:b0\n", - MAX_DEVICE_SUPPORT); - } + fetch_mac_string_vpd(config, macstrbuf); } else { if (fetch_mac_string_cbfs(macstrbuf) != CB_SUCCESS) printk(BIOS_ERR, "r8168: Error reading MAC from CBFS," From d08bc5ad7a83f56e0114b1d01bcab853d0da5cfb Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 26 Mar 2020 14:37:37 +1100 Subject: [PATCH 0625/1463] drivers/net/r8168: Fix leaking memory from mapping BUG=b:152157720,b:152459313 BRANCH=none TEST=none Change-Id: Ie79c3209d0be719ae1394e87efb357b84ce32840 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39855 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/net/r8168.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index fcdac90481..99d472ce8e 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -117,6 +117,7 @@ static enum cb_err fetch_mac_vpd_key(u8 *macstrbuf, const char *vpd_key) if (offset == search_length) { printk(BIOS_ERR, "Error: Could not locate '%s' in VPD\n", vpd_key); + rdev_munmap(&rdev, search_address); return CB_ERR; } printk(BIOS_DEBUG, "Located '%s' in VPD\n", vpd_key); @@ -124,10 +125,12 @@ static enum cb_err fetch_mac_vpd_key(u8 *macstrbuf, const char *vpd_key) offset += strlen(vpd_key) + 1; /* move to next character */ if (offset + MACLEN > search_length) { + rdev_munmap(&rdev, search_address); printk(BIOS_ERR, "Search result too small!\n"); return CB_ERR; } memcpy(macstrbuf, search_address + offset, MACLEN); + rdev_munmap(&rdev, search_address); return CB_SUCCESS; } From 0e1380683fae3fd042ff30274add110a45720aa1 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 23 Mar 2020 13:06:42 +1100 Subject: [PATCH 0626/1463] drivers/net/r8168: Fix ethernet_mac[0-9] format for vpd The format for VPD has changed s.t. the first NIC should always have a zero concat to the end. Adjust all the respective boards to shift back by one and adjust drivers/net friends to remove the 'special casing' of idx == 0. Background: https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn V.2: Fixup a code comment typo while we are here. V.3: Vary special casing semantics for idx==0 => default mac addr is set. V.4: Rework to still support the legacy path. BUG=b:152157720 BRANCH=none TEST=none Change-Id: Idf83cc621a9333186dabb668b22c4b78e211930a Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39771 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/net/Kconfig | 8 +++++++ src/drivers/net/r8168.c | 24 +++++++++---------- src/mainboard/google/fizz/Kconfig | 1 + .../fizz/variants/baseboard/devicetree.cb | 4 ++-- .../hatch/variants/puff/overridetree.cb | 2 +- 5 files changed, 23 insertions(+), 16 deletions(-) diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig index 92de1ed0e7..282075b31d 100644 --- a/src/drivers/net/Kconfig +++ b/src/drivers/net/Kconfig @@ -19,6 +19,14 @@ config RT8168_GET_MAC_FROM_VPD default n select REALTEK_8168_RESET +config RT8168_SUPPORT_LEGACY_VPD_MAC + bool + default n + help + Previously VPD expected that device_indexes set to zero were + special cased. Selecting this Kconfig restores the legacy + VPD format and behaviour. If unsure, you likely do not need this! + config RT8168_SET_LED_MODE bool default n diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 99d472ce8e..eaf33f2978 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -141,16 +141,10 @@ static enum cb_err fetch_mac_vpd_dev_idx(u8 *macstrbuf, u8 device_index) char key[] = "ethernet_mac "; /* Leave a space at tail to stuff an index */ /* - * The device_index 0 is treated as an special case matching to - * "ethernet_mac" with single NIC on DUT. When there are mulitple - * NICs on DUT, they are mapping to "ethernet_macN", where - * N is [0-9]. + * Map each NIC on the DUT to "ethernet_macN", where N is [0-9]. + * Translate index number from integer to ascii by adding '0' char. */ - if (device_index == 0) - key[DEVICE_INDEX_BYTE] = '\0'; - else - /* Translate index number from integer to ascii */ - key[DEVICE_INDEX_BYTE] = (device_index - 1) + '0'; + key[DEVICE_INDEX_BYTE] = device_index + '0'; return fetch_mac_vpd_key(macstrbuf, key); } @@ -167,12 +161,16 @@ static void fetch_mac_string_vpd(struct drivers_net_config *config, u8 *macstrbu return; } - /* check "ethernet_mac" first when the device index is 1 */ - if (config->device_index == 1 && - fetch_mac_vpd_dev_idx(macstrbuf, 0) == CB_SUCCESS) + if (fetch_mac_vpd_dev_idx(macstrbuf, config->device_index) == CB_SUCCESS) return; - if (fetch_mac_vpd_dev_idx(macstrbuf, config->device_index) != CB_SUCCESS) + if (!CONFIG(RT8168_SUPPORT_LEGACY_VPD_MAC)) { + printk(BIOS_ERR, "r8168: mac address not found in VPD," + " using default 00:e0:4c:00:c0:b0\n"); + return; + } + + if (fetch_mac_vpd_key(macstrbuf, "ethernet_mac ") != CB_SUCCESS) printk(BIOS_ERR, "r8168: mac address not found in VPD," " using default 00:e0:4c:00:c0:b0\n"); } diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index fbe98bec3f..b6b34fd8e1 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -24,6 +24,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ select MAINBOARD_HAS_TPM2 select GENERIC_SPD_BIN select RT8168_GET_MAC_FROM_VPD + select RT8168_SUPPORT_LEGACY_VPD_MAC select RT8168_SET_LED_MODE select SPD_READ_BY_WORD diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index c1afe3d439..5da9997d59 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -411,8 +411,8 @@ chip soc/intel/skylake chip drivers/net register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" - register "device_index" = "1" device pci 00.0 on end + register "device_index" = "0" end end # PCI Express Port 3 device pci 1c.3 on @@ -428,7 +428,7 @@ chip soc/intel/skylake device pci 1d.0 on # PCI Express Port 9 for 2nd LAN chip drivers/net register "customized_leds" = "0x0fa5" - register "device_index" = "2" + register "device_index" = "1" device pci 00.0 on end end end # PCI Express Port 9 for BtoB diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d8df2980ec..bf9120adbc 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -283,7 +283,7 @@ chip soc/intel/cannonlake register "stop_delay_ms" = "12" # NIC needs time to quiesce register "stop_off_delay_ms" = "1" register "has_power_resource" = "1" - register "device_index" = "1" + register "device_index" = "0" device pci 00.0 on end end end # FSP requires func0 be enabled. From 2a0a02f98f742ff921ac3a9a8ccbf7fe47690509 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 26 Mar 2020 16:47:55 +1100 Subject: [PATCH 0627/1463] drivers/net/r8168: Fix extraneous space in "ethernet_mac " Unfortunately this was noticed only after commit 0e1380683f merged, credit to Sam McNally for spotting it. Previously the legacy path replaced the space with a null byte and so the expected string here is precisely "ethernet_mac" and not "ethernet_mac ". BUG=b:152157720 BRANCH=none TEST=none Change-Id: I603fad4efd6d6c539137dd714329bcea1877abdd Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/39856 Reviewed-by: Sam McNally Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/net/r8168.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index eaf33f2978..a3e1e1b049 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -170,7 +170,7 @@ static void fetch_mac_string_vpd(struct drivers_net_config *config, u8 *macstrbu return; } - if (fetch_mac_vpd_key(macstrbuf, "ethernet_mac ") != CB_SUCCESS) + if (fetch_mac_vpd_key(macstrbuf, "ethernet_mac") != CB_SUCCESS) printk(BIOS_ERR, "r8168: mac address not found in VPD," " using default 00:e0:4c:00:c0:b0\n"); } From a6c8b4becbd12fe6043557ca1e398c1a7c691007 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 22:38:08 +0100 Subject: [PATCH 0628/1463] nb/intel/sandybridge: Rewrite get_FRQ The code is just clamping the frequency index to a valid range. Do it with a helper function. Also, add a CPUID check, as Sandy Bridge will eventually use this code. Change-Id: I4c7aa5f7615c6edb1ab62fb004abb126df9d284b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39787 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/commonlib/include/commonlib/clamp.h | 22 ++++++++++++ .../intel/sandybridge/raminit_ivy.c | 34 ++++++++++--------- 2 files changed, 40 insertions(+), 16 deletions(-) create mode 100644 src/commonlib/include/commonlib/clamp.h diff --git a/src/commonlib/include/commonlib/clamp.h b/src/commonlib/include/commonlib/clamp.h new file mode 100644 index 0000000000..e01a107ed4 --- /dev/null +++ b/src/commonlib/include/commonlib/clamp.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef COMMONLIB_CLAMP_H +#define COMMONLIB_CLAMP_H + +#include + +/* + * Clamp a value, so that it is between a lower and an upper bound. + */ +static inline u32 clamp_u32(const u32 min, const u32 val, const u32 max) +{ + if (val > max) + return max; + + if (val < min) + return min; + + return val; +} + +#endif /* COMMONLIB_CLAMP_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 6484139a94..6ff82dd011 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -9,24 +10,25 @@ #include "raminit_common.h" #include "raminit_tables.h" -/* Frequency multiplier */ -static u32 get_FRQ(u32 tCK, u8 base_freq) -{ - const u32 FRQ = 256000 / (tCK * base_freq); +#define IVB_MIN_DCLK_133_MULT 3 +#define IVB_MAX_DCLK_133_MULT 10 +#define IVB_MIN_DCLK_100_MULT 7 +#define IVB_MAX_DCLK_100_MULT 12 - if (base_freq == 100) { - if (FRQ > 12) - return 12; - if (FRQ < 7) - return 7; - } else { - if (FRQ > 10) - return 10; - if (FRQ < 3) - return 3; +/* Frequency multiplier */ +static u32 get_FRQ(const ramctr_timing *ctrl) +{ + const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq); + + if (IS_IVY_CPU(ctrl->cpu)) { + if (ctrl->base_freq == 100) + return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT); + + if (ctrl->base_freq == 133) + return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); } - return FRQ; + die("Unsupported CPU or base frequency."); } /* Get REFI based on frequency index, tREFI = 7.8usec */ @@ -204,7 +206,7 @@ static void find_cas_tck(ramctr_timing *ctrl) } /* Frequency multiplier */ - ctrl->FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + ctrl->FRQ = get_FRQ(ctrl); printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); From 29f391ec8f37e3e7d838bf2d16a4ba190062f1dc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 22:51:05 +0100 Subject: [PATCH 0629/1463] nb/intel/sandybridge: Add print for PLL_REF100_CFG This field can take eight different values, depending on the maximum supported speed for the memory when using the 100 MHz reference clock. Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/raminit_ivy.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 6ff82dd011..7d684b2d0e 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -176,10 +176,12 @@ static void find_cas_tck(ramctr_timing *ctrl) /* 100 MHz reference clock supported */ reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); - ref_100mhz_support = !!((reg32 >> 21) & 0x7); + ref_100mhz_support = (reg32 >> 21) & 0x7; printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" : "no"); + printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); + /* Find CAS latency */ while (1) { /* From efbed263dfc1f85b61f1e023682d4e885ed207aa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 23:18:03 +0100 Subject: [PATCH 0630/1463] nb/intel/sandybridge: Unify the code paths The code for Sandy Bridge is a subset of the code for Ivy Bridge. Adapt the Ivy Bridge code so that it also supports Sandy Bridge, and use it. Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330. Change-Id: I7b78ec605aff976b9a5cdbb364a69df4b4947c6e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39737 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit.c | 8 ------- .../intel/sandybridge/raminit_common.h | 2 +- .../intel/sandybridge/raminit_ivy.c | 24 ++++++++++++++----- 3 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 93bfd4c540..b096a11bf2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -214,14 +214,6 @@ static void save_timings(ramctr_timing *ctrl) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) -{ - if (IS_SANDY_CPU(ctrl->cpu)) - return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size); - else - return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size); -} - static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index d966c51dfc..4e23abd956 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -179,8 +179,8 @@ void set_read_write_timings(ramctr_timing *ctrl); void set_normal_operation(ramctr_timing *ctrl); void final_registers(ramctr_timing *ctrl); void restore_timings(ramctr_timing *ctrl); +int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size); int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size); -int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size); #endif diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 7d684b2d0e..d27914a184 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -10,6 +10,8 @@ #include "raminit_common.h" #include "raminit_tables.h" +#define SNB_MIN_DCLK_133_MULT 3 +#define SNB_MAX_DCLK_133_MULT 8 #define IVB_MIN_DCLK_133_MULT 3 #define IVB_MAX_DCLK_133_MULT 10 #define IVB_MIN_DCLK_100_MULT 7 @@ -26,6 +28,10 @@ static u32 get_FRQ(const ramctr_timing *ctrl) if (ctrl->base_freq == 133) return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); + + } else if (IS_SANDY_CPU(ctrl->cpu)) { + if (ctrl->base_freq == 133) + return clamp_u32(SNB_MIN_DCLK_133_MULT, FRQ, SNB_MAX_DCLK_133_MULT); } die("Unsupported CPU or base frequency."); @@ -121,7 +127,7 @@ static u32 get_COMP2(u32 FRQ, u8 base_freq) return frq_comp2_map[0][FRQ - 3]; } -static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) +static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) { if (ctrl->tCK <= TCK_1200MHZ) { ctrl->tCK = TCK_1200MHZ; @@ -164,7 +170,7 @@ static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) if (!ref_100mhz_support && ctrl->base_freq == 100) { /* Skip unsupported frequency */ ctrl->tCK++; - ivb_normalize_tclk(ctrl, ref_100mhz_support); + normalize_tclk(ctrl, ref_100mhz_support); } } @@ -188,7 +194,7 @@ static void find_cas_tck(ramctr_timing *ctrl) * Normalising tCK before computing clock could potentially * result in a lower selected CAS, which is desired. */ - ivb_normalize_tclk(ctrl, ref_100mhz_support); + normalize_tclk(ctrl, ref_100mhz_support); if (!(ctrl->tCK)) die("Couldn't find compatible clock / CAS settings\n"); @@ -218,6 +224,10 @@ static void find_cas_tck(ramctr_timing *ctrl) static void dram_timing(ramctr_timing *ctrl) { + /* + * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). + * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. + */ /* * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800). * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency. @@ -482,11 +492,13 @@ static void dram_ioregs(ramctr_timing *ctrl) printram("done\n"); } -int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) +int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) { int err; - printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", fast_boot); + printk(BIOS_DEBUG, "Starting %s Bridge RAM training (%s).\n", + IS_SANDY_CPU(ctrl->cpu) ? "Sandy" : "Ivy", + fast_boot ? "fast boot" : "full initialization"); if (!fast_boot) { /* Find fastest common supported parameters */ @@ -592,7 +604,7 @@ int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in write_controller_mr(ctrl); - if (!s3_resume) { + if (!s3resume) { err = channel_test(ctrl); if (err) return err; From 07609028ecb4ee1dc52557b9599672a4d62dd60e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 23:34:16 +0100 Subject: [PATCH 0631/1463] nb/intel/sandybridge: Drop dead code Sandy Bridge now uses the same code as Ivy Bridge. Drop the old code. Change-Id: I4f6a71a4223194d83c0ee790d317ecdcafd664fd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39789 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/sandybridge/Makefile.inc | 1 - .../intel/sandybridge/raminit_common.h | 2 - .../intel/sandybridge/raminit_sandy.c | 470 ------------------ 3 files changed, 473 deletions(-) delete mode 100644 src/northbridge/intel/sandybridge/raminit_sandy.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 81f3818e62..9cff82dd3f 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -23,7 +23,6 @@ ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c -romstage-y += raminit_sandy.c romstage-y += raminit_ivy.c romstage-y += raminit_tables.c romstage-y += ../../../device/dram/ddr3.c diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 4e23abd956..090654c848 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -181,6 +181,4 @@ void final_registers(ramctr_timing *ctrl); void restore_timings(ramctr_timing *ctrl); int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size); -int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size); - #endif diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c deleted file mode 100644 index 29b8a7bfec..0000000000 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ /dev/null @@ -1,470 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include -#include -#include -#include "raminit_native.h" -#include "raminit_common.h" -#include "raminit_tables.h" - -/* Frequency multiplier */ -static u32 get_FRQ(u32 tCK) -{ - const u32 FRQ = 256000 / (tCK * BASEFREQ); - - if (FRQ > 8) - return 8; - if (FRQ < 3) - return 3; - - return FRQ; -} - -/* Get REFI based on MC frequency */ -static u32 get_REFI(u32 tCK) -{ - return frq_refi_map[0][get_FRQ(tCK) - 3]; -} - -/* Get XSOffset based on MC frequency */ -static u8 get_XSOffset(u32 tCK) -{ - return frq_xs_map[0][get_FRQ(tCK) - 3]; -} - -/* Get MOD based on MC frequency */ -static u8 get_MOD(u32 tCK) -{ - return frq_mod_map[0][get_FRQ(tCK) - 3]; -} - -/* Get Write Leveling Output delay based on MC frequency */ -static u8 get_WLO(u32 tCK) -{ - return frq_wlo_map[0][get_FRQ(tCK) - 3]; -} - -/* Get CKE based on MC frequency */ -static u8 get_CKE(u32 tCK) -{ - return frq_cke_map[0][get_FRQ(tCK) - 3]; -} - -/* Get XPDLL based on MC frequency */ -static u8 get_XPDLL(u32 tCK) -{ - return frq_xpdll_map[0][get_FRQ(tCK) - 3]; -} - -/* Get XP based on MC frequency */ -static u8 get_XP(u32 tCK) -{ - return frq_xp_map[0][get_FRQ(tCK) - 3]; -} - -/* Get AONPD based on MC frequency */ -static u8 get_AONPD(u32 tCK) -{ - return frq_aonpd_map[0][get_FRQ(tCK) - 3]; -} - -/* Get COMP2 based on MC frequency */ -static u32 get_COMP2(u32 tCK) -{ - return frq_comp2_map[0][get_FRQ(tCK) - 3]; -} - -static void snb_normalize_tclk(u32 *tclk) -{ - if (*tclk <= TCK_1066MHZ) { - *tclk = TCK_1066MHZ; - } else if (*tclk <= TCK_933MHZ) { - *tclk = TCK_933MHZ; - } else if (*tclk <= TCK_800MHZ) { - *tclk = TCK_800MHZ; - } else if (*tclk <= TCK_666MHZ) { - *tclk = TCK_666MHZ; - } else if (*tclk <= TCK_533MHZ) { - *tclk = TCK_533MHZ; - } else if (*tclk <= TCK_400MHZ) { - *tclk = TCK_400MHZ; - } else { - *tclk = 0; - } -} - -static void find_cas_tck(ramctr_timing *ctrl) -{ - u8 val; - - /* Find CAS latency */ - while (1) { - /* - * Normalising tCK before computing clock could potentially - * result in a lower selected CAS, which is desired. - */ - snb_normalize_tclk(&(ctrl->tCK)); - if (!(ctrl->tCK)) - die("Couldn't find compatible clock / CAS settings\n"); - - val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); - printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); - for (; val <= MAX_CAS; val++) - if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) - break; - - if (val == (MAX_CAS + 1)) { - ctrl->tCK++; - continue; - } else { - printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n"); - break; - } - } - - printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); - printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); - ctrl->CAS = val; -} - -static void dram_timing(ramctr_timing *ctrl) -{ - /* - * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). - * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. - */ - if (ctrl->tCK == TCK_1066MHZ) { - ctrl->edge_offset[0] = 16; - ctrl->edge_offset[1] = 7; - ctrl->edge_offset[2] = 7; - ctrl->timC_offset[0] = 18; - ctrl->timC_offset[1] = 7; - ctrl->timC_offset[2] = 7; - ctrl->pi_coding_threshold = 13; - - } else if (ctrl->tCK == TCK_933MHZ) { - ctrl->edge_offset[0] = 14; - ctrl->edge_offset[1] = 6; - ctrl->edge_offset[2] = 6; - ctrl->timC_offset[0] = 15; - ctrl->timC_offset[1] = 6; - ctrl->timC_offset[2] = 6; - ctrl->pi_coding_threshold = 15; - - } else if (ctrl->tCK == TCK_800MHZ) { - ctrl->edge_offset[0] = 13; - ctrl->edge_offset[1] = 5; - ctrl->edge_offset[2] = 5; - ctrl->timC_offset[0] = 14; - ctrl->timC_offset[1] = 5; - ctrl->timC_offset[2] = 5; - ctrl->pi_coding_threshold = 15; - - } else if (ctrl->tCK == TCK_666MHZ) { - ctrl->edge_offset[0] = 10; - ctrl->edge_offset[1] = 4; - ctrl->edge_offset[2] = 4; - ctrl->timC_offset[0] = 11; - ctrl->timC_offset[1] = 4; - ctrl->timC_offset[2] = 4; - ctrl->pi_coding_threshold = 16; - - } else if (ctrl->tCK == TCK_533MHZ) { - ctrl->edge_offset[0] = 8; - ctrl->edge_offset[1] = 3; - ctrl->edge_offset[2] = 3; - ctrl->timC_offset[0] = 9; - ctrl->timC_offset[1] = 3; - ctrl->timC_offset[2] = 3; - ctrl->pi_coding_threshold = 17; - - } else { - ctrl->tCK = TCK_400MHZ; - ctrl->edge_offset[0] = 6; - ctrl->edge_offset[1] = 2; - ctrl->edge_offset[2] = 2; - ctrl->timC_offset[0] = 6; - ctrl->timC_offset[1] = 2; - ctrl->timC_offset[2] = 2; - ctrl->pi_coding_threshold = 17; - } - - /* Initial phase between CLK/CMD pins */ - ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66; - - /* DLL_CONFIG_MDLL_W_TIMER */ - ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3; - - if (ctrl->tCWL) - ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); - else - ctrl->CWL = get_CWL(ctrl->tCK); - - printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); - - /* Find tRCD */ - ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); - - /* Find tRAS */ - ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); - - /* Find tWR */ - ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); - - /* Find tFAW */ - ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); - - /* Find tRRD */ - ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); - - /* Find tRTP */ - ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); - - /* Find tWTR */ - ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); - - /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - - ctrl->tREFI = get_REFI(ctrl->tCK); - ctrl->tMOD = get_MOD(ctrl->tCK); - ctrl->tXSOffset = get_XSOffset(ctrl->tCK); - ctrl->tWLO = get_WLO(ctrl->tCK); - ctrl->tCKE = get_CKE(ctrl->tCK); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK); - ctrl->tXP = get_XP(ctrl->tCK); - ctrl->tAONPD = get_AONPD(ctrl->tCK); -} - -static void dram_freq(ramctr_timing *ctrl) -{ - if (ctrl->tCK > TCK_400MHZ) { - printk(BIOS_ERR, - "DRAM frequency is under lowest supported frequency (400 MHz). " - "Increasing to 400 MHz as last resort"); - ctrl->tCK = TCK_400MHZ; - } - - while (1) { - u8 val2; - u32 reg1 = 0; - - /* Step 1 - Set target PCU frequency */ - find_cas_tck(ctrl); - - /* Frequency multiplier */ - const u32 FRQ = get_FRQ(ctrl->tCK); - - /* - * The PLL will never lock if the required frequency is already set. - * Exit early to prevent a system hang. - */ - reg1 = MCHBAR32(MC_BIOS_DATA); - val2 = (u8) reg1; - if (val2) - return; - - /* Step 1 - Select frequency in the MCU */ - reg1 = FRQ; - reg1 |= 0x80000000; /* set running bit */ - MCHBAR32(MC_BIOS_REQ) = reg1; - int i=0; - printk(BIOS_DEBUG, "PLL busy... "); - while (reg1 & 0x80000000) { - udelay(10); - i++; - reg1 = MCHBAR32(MC_BIOS_REQ); - } - printk(BIOS_DEBUG, "done in %d us\n", i * 10); - - /* Step 2 - Verify lock frequency */ - reg1 = MCHBAR32(MC_BIOS_DATA); - val2 = (u8) reg1; - if (val2 >= FRQ) { - printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", - (1000 << 8) / ctrl->tCK); - return; - } - printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); - ctrl->tCK++; - } -} - -static void dram_ioregs(ramctr_timing *ctrl) -{ - u32 reg; - - int channel; - - /* IO clock */ - FOR_ALL_CHANNELS { - MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; - } - - /* IO command */ - FOR_ALL_CHANNELS { - MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; - } - - /* IO control */ - FOR_ALL_POPULATED_CHANNELS { - program_timings(ctrl, channel); - } - - /* Perform RCOMP */ - printram("RCOMP..."); - while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) - ; - - printram("done\n"); - - /* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK); - printram("COMP2 done\n"); - - /* Set COMP1 */ - FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(CRCOMPOFST1_ch(channel)); - reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ - reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ - reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ - MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; - } - printram("COMP1 done\n"); - - printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(M_COMP) |= (1 << 8); - udelay(20); - printram("done\n"); -} - -int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) -{ - int err; - - printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", fast_boot); - - if (!fast_boot) { - /* Find fastest common supported parameters */ - dram_find_common_params(ctrl); - - dram_dimm_mapping(ctrl); - } - - /* Set MC frequency */ - dram_freq(ctrl); - - if (!fast_boot) { - /* Calculate timings */ - dram_timing(ctrl); - } - - /* Set version register */ - MCHBAR32(MRC_REVISION) = 0xc04eb002; - - /* Enable crossover */ - dram_xover(ctrl); - - /* Set timing and refresh registers */ - dram_timing_regs(ctrl); - - /* Power mode preset */ - MCHBAR32(PM_THML_STAT) = 0x5500; - - /* Set scheduler chicken bits */ - MCHBAR32(SCHED_CBIT) = 0x10100005; - - /* Set up watermarks and starvation counter */ - set_wmm_behavior(ctrl->cpu); - - /* Clear IO reset bit */ - MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); - - /* Set MAD-DIMM registers */ - dram_dimm_set_mapping(ctrl); - printk(BIOS_DEBUG, "Done dimm mapping\n"); - - /* Zone config */ - dram_zones(ctrl, 1); - - /* Set memory map */ - dram_memorymap(ctrl, me_uma_size); - printk(BIOS_DEBUG, "Done memory map\n"); - - /* Set IO registers */ - dram_ioregs(ctrl); - printk(BIOS_DEBUG, "Done io registers\n"); - - udelay(1); - - if (fast_boot) { - restore_timings(ctrl); - } else { - /* Do JEDEC DDR3 reset sequence */ - dram_jedecreset(ctrl); - printk(BIOS_DEBUG, "Done jedec reset\n"); - - /* MRS commands */ - dram_mrscommands(ctrl); - printk(BIOS_DEBUG, "Done MRS commands\n"); - - /* Prepare for memory training */ - prepare_training(ctrl); - - err = read_training(ctrl); - if (err) - return err; - - err = write_training(ctrl); - if (err) - return err; - - printram("CP5a\n"); - - err = discover_edges(ctrl); - if (err) - return err; - - printram("CP5b\n"); - - err = command_training(ctrl); - if (err) - return err; - - printram("CP5c\n"); - - err = discover_edges_write(ctrl); - if (err) - return err; - - err = discover_timC_write(ctrl); - if (err) - return err; - - normalize_training(ctrl); - } - - set_read_write_timings(ctrl); - - write_controller_mr(ctrl); - - if (!s3_resume) { - err = channel_test(ctrl); - if (err) - return err; - } - - return 0; -} From a38fee31b59acd8e3f07ec89d4328e98b6979611 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 23:36:15 +0100 Subject: [PATCH 0632/1463] nb/intel/sandybridge: Rename raminit_ivy.c It is no longer specific to Ivy Bridge. Change-Id: I3684e654a1b1aee308e30db739d41cf18e7ea6bd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39790 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/Makefile.inc | 2 +- .../intel/sandybridge/{raminit_ivy.c => raminit_native.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename src/northbridge/intel/sandybridge/{raminit_ivy.c => raminit_native.c} (100%) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 9cff82dd3f..de52242612 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -23,7 +23,7 @@ ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c -romstage-y += raminit_ivy.c +romstage-y += raminit_native.c romstage-y += raminit_tables.c romstage-y += ../../../device/dram/ddr3.c else diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_native.c similarity index 100% rename from src/northbridge/intel/sandybridge/raminit_ivy.c rename to src/northbridge/intel/sandybridge/raminit_native.c From 0c3936e41b16f11abda5b0f78d5d38caa9f179e3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 12:49:27 +0100 Subject: [PATCH 0633/1463] nb/intel/sandybridge: Update comment Expand a comment with additional information, and split it in two lines. Change-Id: I10389a1a575833c8ecc9a79a374c1816000f5667 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39757 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/raminit_common.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 90c7164350..a8480a7661 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2501,7 +2501,10 @@ int discover_edges(ramctr_timing *ctrl) MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } - /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ + /* + * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will + * also use a single loop. It would seem that it is a debugging configuration. + */ MCHBAR32(IOSAV_DC_MASK) = 0x300; printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); From 098240eb4fd4ef59510d5138538f2a2f7cc5dcdc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 12:55:32 +0100 Subject: [PATCH 0634/1463] nb/intel/sandybridge: Use IOSAV_BYTE_SERROR_C_ch macro This changes the binary because the operations get reordered, but it is otherwise equivalent. Change-Id: I362187b2889e6f7a68bf752a23c1279cebf961f2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39758 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/sandybridge/raminit_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index a8480a7661..d10b859575 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2626,7 +2626,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr } /* FIXME: This register only exists on Ivy Bridge */ - raw_stats[edge] = MCHBAR32(0x436c + channel * 0x400); + raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { @@ -2797,8 +2797,8 @@ int discover_timC_write(ramctr_timing *ctrl) test_timC_write (ctrl, channel, slotrank); /* FIXME: Another IVB-only register! */ - raw_stats[timC] = - MCHBAR32(0x436c + channel * 0x400); + raw_stats[timC] = MCHBAR32( + IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { struct run rn; From 5fd50b6b198d7e086945ca0255ccc0757b31f748 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 13:00:44 +0100 Subject: [PATCH 0635/1463] nb/intel/sandybridge: Add and use TC_DTP definition This register is specific to Ivy Bridge. This changes the binary because the operations get reordered, but it is equivalent. Change-Id: Ibc9127e0fc268466c13f7c5ac8d942543713ca32 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39759 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/mchbar_regs.h | 8 ++++++++ src/northbridge/intel/sandybridge/raminit_common.c | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index a8ae9c53a9..cf29155f35 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -215,6 +215,10 @@ #define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ #define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ #define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define TC_DTP_ch(ch) Cx(0x4014, ch) /** Timings: Debug parameters */ + #define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ #define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ #define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ @@ -280,6 +284,10 @@ #define TC_RAP 0x4c04 /* Timings: Regular access */ #define TC_RWP 0x4c08 /* Timings: Read / Write */ #define TC_OTHP 0x4c0c /* Timings: Other parameters */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define TC_DTP 0x4c14 /** Timings: Debug parameters */ + #define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ #define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ #define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d10b859575..620c57404a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -216,8 +216,8 @@ void dram_timing_regs(ramctr_timing *ctrl) printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; - /* FIXME: This register might as well not exist */ - MCHBAR32(0x4014 + channel * 0x400) = 0; + /* FIXME: This register only exists on Ivy Bridge! */ + MCHBAR32(TC_DTP_ch(channel)) = 0; MCHBAR32_OR(addr, 0x00020000); From ca2f68abedcc2065574a03a4525b1c3cab7280ba Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 13:15:12 +0100 Subject: [PATCH 0636/1463] nb/intel/sandybridge: Correct TC_DTP handling It is only for Ivy Bridge, and needs to be set on certain circumstances. Change-Id: I4093adef44fae787c96fec4b4b8c7c867786d219 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39760 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/sandybridge/raminit_common.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 620c57404a..9e27400942 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -216,8 +216,22 @@ void dram_timing_regs(ramctr_timing *ctrl) printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; - /* FIXME: This register only exists on Ivy Bridge! */ - MCHBAR32(TC_DTP_ch(channel)) = 0; + /* Debug parameters - only applies to Ivy Bridge */ + if (IS_IVY_CPU(ctrl->cpu)) { + reg = 0; + + /* + * If tXP and tXPDLL are very high, we need to increase them by one. + * This can only happen on Ivy Bridge, and when overclocking the RAM. + */ + if (ctrl->tXP >= 8) + reg |= (1 << 12); + + if (ctrl->tXPDLL >= 32) + reg |= (1 << 13); + + MCHBAR32(TC_DTP_ch(channel)) = reg; + } MCHBAR32_OR(addr, 0x00020000); From 394ac5b33ead4233d3527681dc87bd54d1a4d64a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 00:35:14 +0100 Subject: [PATCH 0637/1463] nb/intel/sandybridge: Fix IOSAV register description The four CS control signals are grouped into the same nibble. Change-Id: Iaf8d5216fdca6014be61ae2583fc963d69111571 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39767 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/mchbar_regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index cf29155f35..5f46e706a8 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -67,14 +67,13 @@ * [2] !WE signal. * [4..7] CKE, per rank and channel. * [8..11] ODT, per rank and channel. - * [12] Chip Select mode control. - * [13..16] Chip select, per rank and channel. It works as follows: + * [12..15] Chip select, per rank and channel. It works as follows: * * entity CS_BLOCK is * port ( - * MODE : in std_logic; -- Mode select at [12] + * MODE : in std_logic; -- Mode select at [16] * RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value - * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [13..16] + * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [12..15] * CS_Q : out std_logic_vector(0 to 3) -- CS signals * ); * end entity CS_BLOCK; @@ -88,6 +87,7 @@ * end if; * end architecture RTL; * + * [16] Chip Select mode control. * [17] Auto Precharge. Only valid when using 10 row bits! * * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) From 69e1714dd226b68561b0b03bec3f645c4af48530 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 12:26:29 +0100 Subject: [PATCH 0638/1463] nb/intel/sandybridge: Use macros for JEDEC commands Some commands, like ZQCS and ZQCL, use the same macro. This is because they differ in things outside of the IOSAV_SP_CMD_CTRL registers. Also, correct a comment that does not concur with the actual command in use. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: Id2ff4c85f9d9db7c892b764472423cbf2e6db422 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39776 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/sandybridge/raminit_common.c | 144 +++++++++--------- .../intel/sandybridge/raminit_common.h | 10 ++ 2 files changed, 82 insertions(+), 72 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9e27400942..4ba5b5900f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -608,7 +608,7 @@ static void write_reset(ramctr_timing *ctrl) slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x80c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; @@ -700,21 +700,21 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, } /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (reg << 20) | val | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | (reg << 20) | val | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | (reg << 20) | val | 0x60000; @@ -843,14 +843,14 @@ void dram_mrscommands(ramctr_timing *ctrl) } } - /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL(0)) = 0x7; + /* DRAM command NOP (without ODT nor chip selects) */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL(0)) = IOSAV_NOP & NO_RANKSEL & ~(0xff << 8); MCHBAR32(IOSAV_n_SUBSEQ_CTRL(0)) = 0xf1001; MCHBAR32(IOSAV_n_SP_CMD_ADDR(0)) = 0x60002; MCHBAR32(IOSAV_n_ADDR_UPDATE(0)) = 0; /* DRAM command ZQCL */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL(1)) = 0x1f003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL(1)) = IOSAV_ZQCS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL(1)) = 0x1901001; MCHBAR32(IOSAV_n_SP_CMD_ADDR(1)) = 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE(1)) = 0x288; @@ -877,7 +877,7 @@ void dram_mrscommands(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; @@ -1044,26 +1044,26 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4040c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; @@ -1328,7 +1328,7 @@ int read_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; @@ -1428,26 +1428,26 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (6 << 16); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_NOP; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8041001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 8; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_WR; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x80411f4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_NOP; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x08000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 8; @@ -1459,27 +1459,27 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x244; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; @@ -1518,7 +1518,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; @@ -1624,7 +1624,7 @@ static void precharge(ramctr_timing *ctrl) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = @@ -1632,13 +1632,13 @@ static void precharge(ramctr_timing *ctrl) MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = @@ -1647,7 +1647,7 @@ static void precharge(ramctr_timing *ctrl) /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = @@ -1673,7 +1673,7 @@ static void precharge(ramctr_timing *ctrl) * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = @@ -1681,13 +1681,13 @@ static void precharge(ramctr_timing *ctrl) MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = @@ -1696,7 +1696,7 @@ static void precharge(ramctr_timing *ctrl) /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = @@ -1718,14 +1718,14 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f207; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_NOP; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 8 | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f107; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_NOP_ALT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 4; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; @@ -1827,25 +1827,25 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_NOP; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8040c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x8; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_WR; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x8041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x3e2; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_NOP; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x8; @@ -1857,19 +1857,19 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x3f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD | (3 << 16); MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].roundtrip_latency + ctrl->timings[channel][slotrank].io_latency) << 16); @@ -1905,8 +1905,8 @@ static void write_op(ramctr_timing *ctrl, int channel) /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + /* DRAM command ZQCS */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; @@ -1984,7 +1984,7 @@ int write_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; @@ -2053,7 +2053,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); @@ -2062,7 +2062,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); @@ -2070,7 +2070,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x20e42; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); @@ -2078,7 +2078,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x20e42; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xf1001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; @@ -2144,7 +2144,7 @@ static void reprogram_320c(ramctr_timing *ctrl) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; @@ -2165,7 +2165,7 @@ static void reprogram_320c(ramctr_timing *ctrl) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; @@ -2329,26 +2329,26 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x40411f4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; @@ -2414,7 +2414,7 @@ int discover_edges(ramctr_timing *ctrl) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = @@ -2422,13 +2422,13 @@ int discover_edges(ramctr_timing *ctrl) MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = @@ -2437,7 +2437,7 @@ int discover_edges(ramctr_timing *ctrl) /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = @@ -2467,7 +2467,7 @@ int discover_edges(ramctr_timing *ctrl) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = @@ -2475,14 +2475,14 @@ int discover_edges(ramctr_timing *ctrl) MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = @@ -2491,7 +2491,7 @@ int discover_edges(ramctr_timing *ctrl) /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = @@ -2599,7 +2599,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x4 | (ctrl->tRCD << 16) | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); @@ -2608,7 +2608,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = @@ -2616,7 +2616,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = @@ -2624,7 +2624,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = @@ -2728,27 +2728,27 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x0244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; @@ -2943,25 +2943,25 @@ int channel_test(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x0028a004; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x00060000 | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x0001f201; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281064; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0001f105; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x04281064; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x0001f002; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x00280c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = 0x00060400 | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x00000240; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 090654c848..fef4419ffc 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -26,6 +26,16 @@ #define NUM_SLOTS 2 #define NUM_LANES 8 +#define NO_RANKSEL (~(1 << 16)) +#define IOSAV_MRS (0x1f000) +#define IOSAV_PRE (0x1f002) +#define IOSAV_ZQCS (0x1f003) +#define IOSAV_ACT (0x1f006) +#define IOSAV_RD (0x1f105) +#define IOSAV_NOP_ALT (0x1f107) +#define IOSAV_WR (0x1f201) +#define IOSAV_NOP (0x1f207) + /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4 From 8bf921c32fdf2bef31dafcef6374f7e9d6a819d1 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 24 Mar 2020 16:19:38 +0100 Subject: [PATCH 0639/1463] mb/facebook/monolith: Update GT-Sliced icc_max Update the icc_max for the GT-Sliced VR domain according to the hardware design. BUG=N/A TEST=build Change-Id: Ib9f7d77d144a282214e6bda8a4e836873c395487 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/39804 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/mainboard/facebook/monolith/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index e65fe3cfc2..45829aac1f 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -95,7 +95,7 @@ chip soc/intel/skylake #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 5.1A | 32A | 35A | 35A | + #| IccMax | 5.1A | 32A | 35A | 31A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ @@ -146,7 +146,7 @@ chip soc/intel/skylake .psi4enable = 1, \ .imon_slope = 0, \ .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(35), \ + .icc_max = VR_CFG_AMP(31), \ .voltage_limit = 1520 \ }" From 8a7aff4b0b8bf59e73ad6f45d56c5c7c879dcd48 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 25 Mar 2020 07:53:08 +0100 Subject: [PATCH 0640/1463] mb/google/volteer: Use tabs for indents Change-Id: I7304b06d7bf34fb7126acfdef811481dc5cba598 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39814 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index d2599260d7..640f7cd7fe 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -48,6 +48,6 @@ DefinitionBlock( #include /* Camera */ - #include + #include #include "acpi/mipi_camera.asl" } From bfa8166b71e927d076b64d2c17131056c1577be8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 25 Mar 2020 08:05:28 +0100 Subject: [PATCH 0641/1463] mb/google/hatch/variants/nightfury: Replace unneeded white spaces by tabs Change-Id: Icda241cfac7b428176515d7996a48cb01b1dc976 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39815 Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../hatch/variants/nightfury/overridetree.cb | 54 +++++++++---------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index a35e99df99..a940f8bc19 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -23,19 +23,19 @@ chip soc/intel/cannonlake # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" - register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[7]" = "USB2_PORT_EMPTY" register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_EMPTY" register "usb3_ports[4]" = "USB3_PORT_EMPTY" @@ -72,8 +72,8 @@ chip soc/intel/cannonlake .fall_time_ns = 52, }, .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, + .speed_mhz = 1, + .early_init = 1, }, }" @@ -200,29 +200,29 @@ chip soc/intel/cannonlake device pci 15.0 on chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" - register "probed" = "1" - register "wake" = "GPE0_DW0_21" - device i2c 0x15 on end - end + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "probed" = "1" + register "wake" = "GPE0_DW0_21" + device i2c 0x15 on end + end end # I2C 0 device pci 15.1 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN902C"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "20" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end - end + register "generic.hid" = ""ELAN902C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end end # I2C #1 device pci 15.2 off end # I2C #2 From aa56c11b1911fa49e53a145926b00670f9939f27 Mon Sep 17 00:00:00 2001 From: Dtrain Hsu Date: Wed, 25 Mar 2020 17:25:57 +0800 Subject: [PATCH 0642/1463] mb/google/dedede: Query the EC for board version The board version is part of EC's EEPROM, select Kconfig item to enable requesting the EC for board version. BUG=b:152374066 TEST=Verified the mainboard version is from EC's EEPROM. Signed-off-by: Dtrain Hsu Change-Id: Idd8aceed83439cb500e2b03153e9f8ba93979ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39819 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Karthik Ramasubramanian Reviewed-by: Justin TerAvest Reviewed-by: EricR Lai --- src/mainboard/google/dedede/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index e2afc66a05..1aabd0516e 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID select GENERIC_SPD_BIN + select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE From 9ed5a36e98c33f618a090571c8aed4401625206b Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Mon, 16 Mar 2020 21:10:06 +0530 Subject: [PATCH 0643/1463] mb/intel/jasperlake_rvp: Correct Kconfig options 1.Select CHROMEOS_EC related Kconfig for variant board with external EC support. 2.Select proper CHROMEOS Kconfigs which are required for all variants. 3.Disable Intel EC region in case of external EC. BUG=None BRANCH=None TEST=Compilation is successful for both Jasper Lake RVP variants. Change-Id: I290b3748777e18476651101de71df9080dd3105c Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39584 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/Kconfig | 19 +++++++++++++++---- .../intel/jasperlake_rvp/Kconfig.name | 6 ++++++ 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 97b038e45c..c84beff69e 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -10,9 +10,7 @@ config BOARD_SPECIFIC_OPTIONS select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_USES_IFD_EC_REGION select SOC_INTEL_JASPERLAKE config MAINBOARD_DIR @@ -43,11 +41,24 @@ config DIMM_SPD_SIZE int default 512 +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA + select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2 config UART_FOR_CONSOLE int - default 2 + default 2 if INTEL_LPSS_UART_FOR_CONSOLE + default 0 + endif diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig.name b/src/mainboard/intel/jasperlake_rvp/Kconfig.name index 1a56f05485..5c7a0077d8 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig.name +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig.name @@ -1,5 +1,11 @@ config BOARD_INTEL_JASPERLAKE_RVP bool "Jasperlake DDR4/LPDDR4 RVP" + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC bool "Jasperlake DDR4/LPDDR4 RVP with Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_SWITCHES + select INTEL_LPSS_UART_FOR_CONSOLE From 5e5d9c2d1be190b00fec9e981cbe8bd89a62bb50 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 9 Mar 2020 14:02:51 +0530 Subject: [PATCH 0644/1463] mb/intel/jasperlake_rvp: add display related UPD configs Change-Id: Iad0b394dea017223a5b92fff0cb4c2ed1d5a7bd7 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39402 Reviewed-by: Subrata Banik Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- .../jasperlake_rvp/variants/jslrvp/devicetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 9c40f66210..386936eef8 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -18,6 +18,18 @@ chip soc/intel/tigerlake register "ScsEmmcHs400Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" + # Display related UPDs + # Select eDP for port A (1 = eDP, 2 = MIPI) + register "DdiPortAConfig" = "1" + + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth From b75bcc978af50dc409b5356abd33b064029480bb Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Sun, 22 Mar 2020 22:16:03 -0700 Subject: [PATCH 0645/1463] mb/ocp/tiogapass: Properly configure early serial output Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible. This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible. TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock. Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39782 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/ocp/tiogapass/Kconfig | 1 + src/mainboard/ocp/tiogapass/Makefile.inc | 1 + src/mainboard/ocp/tiogapass/bootblock.c | 59 ++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 src/mainboard/ocp/tiogapass/bootblock.c diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 1d501e6db0..f9b5e7f48a 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_FSP2_0 select IPMI_KCS select SOC_INTEL_SKYLAKE_SP + select SUPERIO_ASPEED_AST2400 config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 7a0a43fb8f..27370fd57a 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000000..d9a86e99f0 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} From 2e410757efb824555191d8afd78cf79ab5ba6049 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 20 Mar 2020 12:08:32 -0700 Subject: [PATCH 0646/1463] soc/intel/xeon_sp: Add basic Cooperlake-SP support This adds barebones support. What works: * Linux kernel boots fine * SIRQ and PCH interupts work fine (only in IOAPIC mode) * PCH devices are usable What doesn't: * MP init is not there yet, only 1 CPU is up * SMM is not supported * GPIO is not available * All IIO and extended bus numbers enumeration is not yet available * Warm reset flow is untested * MRC cache save/load TEST=boots into Linux Signed-off-by: Andrey Petrov Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713 Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Kconfig | 7 + src/soc/intel/xeon_sp/Makefile.inc | 1 + src/soc/intel/xeon_sp/cpx/Kconfig | 78 ++++++ src/soc/intel/xeon_sp/cpx/Makefile.inc | 17 ++ src/soc/intel/xeon_sp/cpx/acpi.c | 182 ++++++++++++++ .../intel/xeon_sp/cpx/acpi/southcluster.asl | 236 ++++++++++++++++++ src/soc/intel/xeon_sp/cpx/chip.c | 98 ++++++++ src/soc/intel/xeon_sp/cpx/chip.h | 25 ++ src/soc/intel/xeon_sp/cpx/include/soc/cpu.h | 4 + src/soc/intel/xeon_sp/cpx/include/soc/gpio.h | 12 + src/soc/intel/xeon_sp/cpx/include/soc/irq.h | 4 + src/soc/intel/xeon_sp/cpx/include/soc/nvs.h | 18 ++ .../intel/xeon_sp/cpx/include/soc/pci_devs.h | 64 +++++ .../intel/xeon_sp/cpx/include/soc/ramstage.h | 6 + src/soc/intel/xeon_sp/cpx/romstage.c | 13 + 15 files changed, 765 insertions(+) create mode 100644 src/soc/intel/xeon_sp/cpx/Kconfig create mode 100644 src/soc/intel/xeon_sp/cpx/Makefile.inc create mode 100644 src/soc/intel/xeon_sp/cpx/acpi.c create mode 100644 src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl create mode 100644 src/soc/intel/xeon_sp/cpx/chip.c create mode 100644 src/soc/intel/xeon_sp/cpx/chip.h create mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/cpu.h create mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/gpio.h create mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/irq.h create mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/nvs.h create mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h create mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h create mode 100644 src/soc/intel/xeon_sp/cpx/romstage.c diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 223329d79d..468cb44c27 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -14,6 +14,7 @@ ## source "src/soc/intel/xeon_sp/skx/Kconfig" +source "src/soc/intel/xeon_sp/cpx/Kconfig" config XEON_SP_COMMON_BASE bool @@ -24,6 +25,12 @@ config SOC_INTEL_SKYLAKE_SP help Intel Skylake-SP support +config SOC_INTEL_COOPERLAKE_SP + bool + select XEON_SP_COMMON_BASE + help + Intel Cooperlake-SP support + if XEON_SP_COMMON_BASE config CPU_SPECIFIC_OPTIONS diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index e05fea2448..1459ee932a 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx +subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c romstage-y += romstage.c reset.c util.c spi.c diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig new file mode 100644 index 0000000000..70703d0c78 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -0,0 +1,78 @@ +## +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. +## + +if SOC_INTEL_COOPERLAKE_SP + +config MAINBOARD_USES_FSP2_0 + bool + default y + +config USE_FSP2_0_DRIVER + def_bool y + depends on MAINBOARD_USES_FSP2_0 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_CONSOLE + select POSTCAR_STAGE + select FSP_USES_CB_STACK + +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp" + +config MAX_SOCKET + int + default 2 + +config MAX_CPUS + int + default 80 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +# currently FSP hardcodes [0fe800000;fe930000] for its heap +config DCACHE_RAM_BASE + hex + default 0xfe930000 + +config DCACHE_RAM_SIZE + hex + default 0xd0000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x10000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config HEAP_SIZE + hex + default 0x80000 + +config FSP_TEMP_RAM_SIZE + hex + depends on FSP_USES_CB_STACK + default 0x70000 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +endif diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc new file mode 100644 index 0000000000..b909a454bd --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -0,0 +1,17 @@ +## +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. +## + +ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) + +subdirs-y += ../../../../cpu/x86/lapic +subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/tsc + +romstage-y += romstage.c +ramstage-y += chip.c acpi.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx + +endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c new file mode 100644 index 0000000000..48ad3747fb --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +#define SCI_INT_NUM 9 + +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, + struct acpi_rsdp *rsdp) +{ + current = acpi_write_hpet(device, current, rsdp); + current = (ALIGN(current, 16)); + printk(BIOS_DEBUG, "current = %lx\n", current); + return current; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); + return current; +} + +void southbridge_inject_dsdt(struct device *device) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, 0x2000); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ + // smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } +} + +void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + config_t *config = config_of_soc(); + (void) config; + /* not implemented yet */ +} + +static unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci = SCI_INT_NUM; + uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + flags |= soc_madt_sci_irq_polarity(sci); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + +int soc_madt_sci_irq_polarity(int sci) +{ + if (sci >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + fadt->header.revision = get_acpi_table_revision(FADT); + fadt->sci_int = SCI_INT_NUM; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + + /* GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + + fadt->flush_size = 0x400; /* twice of cache size */ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->day_alrm = 0xd; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = RST_CNT; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_value = RST_CPU | SYS_RST; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_gpe1_blk.space_id = 1; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0; + fadt->cst_cnt = 0; + } else { + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0; + fadt->cst_cnt = 0; + } + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0; +} diff --git a/src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl b/src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl new file mode 100644 index 0000000000..8dfa0a1b64 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_BBN, 0) + +Name (MCRS, ResourceTemplate() { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfeafffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, + 0x6EB00000,,, PMEM) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, + 0x00100000,,, APIC) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, + 0x00100000,,, PCHR) + + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000380000000000, // Range Minimum + 0x0000383FFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000004000000000, // Length + ,,, AddressRangeMemory, TypeStatic) +}) + +Method (_CRS, 0, Serialized) { + Return (MCRS) +} + +Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} + + +Name (AR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, 0, 47 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, 0, 47 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, 0, 47 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, 0, 47 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, 0, 31 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, 0, 39 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, 0, 31 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, 0, 39 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, 0, 16 }, + Package() { 0x0006FFFF, 1, 0, 17 }, + Package() { 0x0006FFFF, 2, 0, 18 }, + Package() { 0x0006FFFF, 3, 0, 19 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, 0, 20 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, 0, 18 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, 0, 22 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, 0, 19 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, 0, 18 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 0, 0, 20 }, + Package() { 0x0011FFFF, 0, 0, 21 }, +}) + +// Socket 0 Root bridge +Method (_PRT, 0) { + Return (AR00) +} diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c new file mode 100644 index 0000000000..dbbf3b31a5 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* C620 IOAPIC has 120 redirection entries */ +#define C620_IOAPIC_REDIR_ENTRIES 120 + +static void pci_domain_set_resources(struct device *dev) +{ + assign_resources(dev->link_list); +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) +{ + /* not implemented yet */ +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, +}; + +static void init_cpus(struct device *dev) +{ + /* not implemented yet */ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = init_cpus, + .scan_bus = NULL, +}; + +static void chip_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void pch_enable_ioapic(const struct device *dev) +{ + uint32_t reg32; + + set_ioapic_id((void *)IO_APIC_ADDR, 2); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); + + reg32 &= ~0x00ff0000; + reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 1, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 3, 1); +} + +struct pci_operations soc_pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static void chip_final(void *data) +{ + /* nothing implemented yet */ +} + +static void chip_init(void *data) +{ + printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); + fsp_silicon_init(false); + pch_enable_ioapic(NULL); + setup_lapic(); +} + +struct chip_operations soc_intel_xeon_sp_cpx_ops = { + CHIP_NAME("Intel Cooperlake-SP") + .enable_dev = chip_enable_dev, + .init = chip_init, + .final = chip_final +}; diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h new file mode 100644 index 0000000000..d86b8e7efa --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include +#include + +struct soc_intel_xeon_sp_cpx_config { + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; +}; + +extern struct chip_operations soc_intel_xeon_sp_cpx_ops; + +typedef struct soc_intel_xeon_sp_cpx_config config_t; + +#endif diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h new file mode 100644 index 0000000000..f33df89a60 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* nothing here yet */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h b/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h new file mode 100644 index 0000000000..36e1a703f5 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* not implemented, adding defaults just to make common code happy */ + +#ifndef _SOC_GPIO_H_ +#define _SOC_GPIO_H + +#define GPIO_NUM_PAD_CFG_REGS 0 +#define NUM_GPI_STATUS_REGS 0 + +#endif diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/irq.h b/src/soc/intel/xeon_sp/cpx/include/soc/irq.h new file mode 100644 index 0000000000..14dd852b78 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/irq.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* nothing here, please come back later */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h new file mode 100644 index 0000000000..352bc27dad --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include + +/* TODO - this requires xeon sp, server board support */ +/* NOTE: We do not use intelblocks/nvs.h since it includes + mostly client specific attributes */ +typedef struct global_nvs_t { + uint8_t pcnt; /* 0x00 - Processor Count */ + uint32_t cbmc; /* 0x01 - coreboot memconsole */ + uint8_t rsvd3[251]; +} __packed global_nvs_t; + +#endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h new file mode 100644 index 0000000000..1154527e4c --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_PCI_DEVS_H_ +#define _SOC_PCI_DEVS_H_ + +#include + +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#include +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +#define SAD_ALL_DEV 29 +#define SAD_ALL_FUNC 0 +#define SAD_ALL_PAM0123_CSR 0x40 +#define SAD_ALL_PAM456_CSR 0x44 + +#define UBOX_DECS_BUS 0 +#define UBOX_DECS_DEV 8 +#define UBOX_DECS_FUNC 2 +#define UBOX_DECS_CPUBUSNO_CSR 0xcc + +#define VTD_TOLM_CSR 0xd0 +#define VTD_TSEG_BASE_CSR 0xa8 +#define VTD_TSEG_LIMIT_CSR 0xac +#define VTD_EXT_CAP_LOW 0x10 +#define VTD_MMCFG_BASE_CSR 0x90 +#define VTD_MMCFG_LIMIT_CSR 0x98 +#define VTD_TOHM_CSR 0xd4 +#define VTD_MMIOL_CSR 0xdc +#define VTD_ME_BASE_CSR 0xf0 +#define VTD_ME_LIMIT_CSR 0xf8 +#define VTD_VERSION 0x00 +#define VTD_CAP 0x08 +#define VTD_CAP_LOW 0x08 +#define VTD_CAP_HIGH 0x0C +#define VTD_EXT_CAP_HIGH 0x14 + +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 5 +#define VTD_FUNC 0 + + + +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5) + +#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h new file mode 100644 index 0000000000..28e8d1a1dc --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c new file mode 100644 index 0000000000..32ada9f4cb --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include "chip.h" + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + (void)m_cfg; +} From 7b42bba3cf287e13eff6b86326f55ef6bf6ff6e0 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 19 Mar 2020 15:11:59 -0700 Subject: [PATCH 0647/1463] vendorcode: Add fake Cooperlake-SP FSP header files These header files are just placeholders. Currently FSP does not look into any real platform-specific UPD fields anyway, so having padding instead of real thing makes no difference. Signed-off-by: Andrey Petrov Change-Id: Id123f4386124b2ceb7776ab719a9970c9c23a0e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39711 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- .../intel/fsp/fsp2_0/cooperlake_sp/FspEas.h | 24 ++++++++++++++ .../intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h | 18 +++++++++++ .../intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h | 22 +++++++++++++ .../intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h | 20 ++++++++++++ .../intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h | 31 +++++++++++++++++++ 5 files changed, 115 insertions(+) create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h new file mode 100644 index 0000000000..21b84a3069 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h @@ -0,0 +1,24 @@ +/** @file + Intel FSP definition from Intel Firmware Support Package External + Architecture Specification v2.0. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ This file and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FSP_EAS_H_ +#define _FSP_EAS_H_ + +#include +#include +#include +#include + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h new file mode 100644 index 0000000000..086c1181ef --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h @@ -0,0 +1,18 @@ +/* + * These are fake files which only contain padding and some known + * data structures from FSP2.x spec. + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include +#include + +#define FSP_M_CONFIG FSPM_CONFIG + +#define FSPT_UPD_SIGNATURE 0x545F445055434F53ULL /* 'SOCUPD_T' */ +#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53ULL /* 'SOCUPD_M' */ +#define FSPS_UPD_SIGNATURE 0x535F445055434F53ULL /* 'SOCUPD_S' */ + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h new file mode 100644 index 0000000000..bdd80ece7d --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -0,0 +1,22 @@ +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include +#include + +#pragma pack (1) + +typedef struct { +uint8_t padding[208]; +} FSPM_CONFIG; + +typedef struct { + FSP_UPD_HEADER FspUpdHeader; + FSPM_ARCH_UPD FspmArchUpd; + FSPM_CONFIG FspmConfig; + uint16_t UpdTerminator; +} FSPM_UPD; + +#pragma pack(1) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h new file mode 100644 index 0000000000..646c1e2fe6 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h @@ -0,0 +1,20 @@ +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#pragma pack(1) + +#include + +typedef struct { + uint8_t padding[54]; +} FSPS_CONFIG; + +typedef struct { + FSP_UPD_HEADER FspUpdHeader; + FSPS_CONFIG FspsConfig; + uint16_t UpdTerminator; +} FSPS_UPD; + +#pragma pack(1) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h new file mode 100644 index 0000000000..a792e703f3 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h @@ -0,0 +1,31 @@ +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include + +#pragma pack(1) + +typedef struct { + uint32_t MicrocodeRegionBase; + uint32_t MicrocodeRegionLength; + uint32_t CodeRegionBase; + uint32_t CodeRegionLength; + uint8_t Reserved1[16]; +} FSPT_CORE_UPD; + +typedef struct { + uint8_t PcdFsptPort80RouteDisable; + uint8_t ReservedTempRamInitUpd[31]; +} FSPT_CONFIG; + +typedef struct { + FSP_UPD_HEADER FspUpdHeader; + FSPT_CORE_UPD FsptCoreUpd; + FSPT_CONFIG FsptConfig; + uint8_t UnusedUpdSpace0[6]; + uint16_t UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif From 1b325dd971c84d75aa5a53405c11e0ad8f2517b9 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 20 Mar 2020 12:12:12 -0700 Subject: [PATCH 0648/1463] mb/intel/cedarisland_crb: Add Cedar Island CRB Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: Angel Pons --- src/mainboard/intel/cedarisland_crb/Kconfig | 23 ++++++++ .../intel/cedarisland_crb/Kconfig.name | 2 + .../intel/cedarisland_crb/Makefile.inc | 1 + .../intel/cedarisland_crb/acpi/platform.asl | 44 ++++++++++++++ src/mainboard/intel/cedarisland_crb/board.fmd | 11 ++++ .../intel/cedarisland_crb/board_info.txt | 6 ++ .../intel/cedarisland_crb/bootblock.c | 25 ++++++++ .../intel/cedarisland_crb/devicetree.cb | 54 +++++++++++++++++ src/mainboard/intel/cedarisland_crb/dsdt.asl | 59 +++++++++++++++++++ 9 files changed, 225 insertions(+) create mode 100644 src/mainboard/intel/cedarisland_crb/Kconfig create mode 100644 src/mainboard/intel/cedarisland_crb/Kconfig.name create mode 100644 src/mainboard/intel/cedarisland_crb/Makefile.inc create mode 100644 src/mainboard/intel/cedarisland_crb/acpi/platform.asl create mode 100644 src/mainboard/intel/cedarisland_crb/board.fmd create mode 100644 src/mainboard/intel/cedarisland_crb/board_info.txt create mode 100644 src/mainboard/intel/cedarisland_crb/bootblock.c create mode 100644 src/mainboard/intel/cedarisland_crb/devicetree.cb create mode 100644 src/mainboard/intel/cedarisland_crb/dsdt.asl diff --git a/src/mainboard/intel/cedarisland_crb/Kconfig b/src/mainboard/intel/cedarisland_crb/Kconfig new file mode 100644 index 0000000000..9e9e66ee14 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/Kconfig @@ -0,0 +1,23 @@ +if BOARD_INTEL_CEDARISLAND_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default "intel/cedarisland_crb" + +config MAINBOARD_PART_NUMBER + string + default "Cedar Island CRB" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif diff --git a/src/mainboard/intel/cedarisland_crb/Kconfig.name b/src/mainboard/intel/cedarisland_crb/Kconfig.name new file mode 100644 index 0000000000..a060881203 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_CEDARISLAND_CRB + bool "Cedar Island CRB" diff --git a/src/mainboard/intel/cedarisland_crb/Makefile.inc b/src/mainboard/intel/cedarisland_crb/Makefile.inc new file mode 100644 index 0000000000..8501868fbf --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl new file mode 100644 index 0000000000..75c1b92f1e --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/intel/cedarisland_crb/board.fmd b/src/mainboard/intel/cedarisland_crb/board.fmd new file mode 100644 index 0000000000..2002f6e313 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/board.fmd @@ -0,0 +1,11 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x2fe8000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fd5000 + SI_PT@0x2fd8000 0x10000 + } + FMAP@0x03000000 0x800 + RW_MRC_CACHE@0x3000800 0x10000 + COREBOOT(CBFS)@0x3010800 +} diff --git a/src/mainboard/intel/cedarisland_crb/board_info.txt b/src/mainboard/intel/cedarisland_crb/board_info.txt new file mode 100644 index 0000000000..cd4bca4e36 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Cedar Island CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c new file mode 100644 index 0000000000..ea82ecc73f --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void bootblock_mainboard_early_init(void) +{ + /* Enable COM1 only */ + pcr_write32(PID_DMI, 0x2770, 0); + pcr_write32(PID_DMI, 0x2774, 1); + + /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb new file mode 100644 index 0000000000..6eb9557484 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -0,0 +1,54 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + end + + end +end diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl new file mode 100644 index 0000000000..3dc45d5f2c --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include + #include + + } + + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + } + } + +} From d4e9978793f1663db1557f13b81e371dfad0eb96 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Sun, 22 Mar 2020 16:10:25 -0700 Subject: [PATCH 0649/1463] configs: Add builder config to create a working Cedar Island CRB Change-Id: I2a2de7ccb96996211c45da3f9ec9bf6f71cc0c89 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39783 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: David Hendricks --- configs/builder/config.intel.cpx.crb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 configs/builder/config.intel.cpx.crb diff --git a/configs/builder/config.intel.cpx.crb b/configs/builder/config.intel.cpx.crb new file mode 100644 index 0000000000..b825a9239f --- /dev/null +++ b/configs/builder/config.intel.cpx.crb @@ -0,0 +1,17 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.cpx.crb + +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_INTEL_CEDARISLAND_CRB=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="site-local/cedarisland_crb/ucode-05-06-5a" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/cedarisland_crb/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/cedarisland_crb/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/cedarisland_crb/Server_S.fd" +CONFIG_ME_BIN_PATH="site-local/cedarisland_crb/me.bin" +CONFIG_IFD_BIN_PATH="site-local/cedarisland_crb/descriptor.bin" From 90557f4a4ba8ffc027bf16a3a43db4ebb35072f9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 25 Mar 2020 18:40:41 +0530 Subject: [PATCH 0650/1463] drivers/intel/fsp2_0: Avoid iterative print statement This patch moves "Display FSP Version Info HOB" print outside of the loop to avoid getting called multiple times. TEST=Able to see "Display FSP Version Info HOB" only once. Change-Id: I754d5922f4dbef22656ca98c02d9f45791c8433d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39827 Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/hand_off_block.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index d2c2b784cf..3978a1848b 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -233,7 +233,6 @@ static void display_fsp_version_info_hob(const void *hob, size_t size) (fvih->Count * sizeof (FIRMWARE_VERSION_INFO))); size -= sizeof(SMBIOS_STRUCTURE); - printk(BIOS_DEBUG, "Display FSP Version Info HOB\n"); for (index = 0; index < fvih->Count; index++) { cnt = strlen(str_ptr); @@ -282,6 +281,7 @@ void fsp_display_fvi_version_hob(void) if (!hob) return; + printk(BIOS_DEBUG, "Display FSP Version Info HOB\n"); for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_GUID_EXTENSION) From f0619f47c36cbf751e50dcd03b6e695e35ea8d02 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 21 Jan 2020 21:46:51 -0700 Subject: [PATCH 0651/1463] vc/amd/fsp/picasso: Add PCIe and DDI helpers Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP. Signed-off-by: Marshall Dawson Signed-off-by: Felix Held Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38698 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel --- .../amd/fsp/picasso/platform_descriptors.h | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 src/vendorcode/amd/fsp/picasso/platform_descriptors.h diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h new file mode 100644 index 0000000000..58ed4a97ae --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ +#define __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ + +/* Engine descriptor type */ +typedef enum { + UNUSED_ENGINE = 0x00, // Unused descriptor + PCIE_ENGINE = 0x01, // PCIe port + USB_ENGINE = 0x02, // USB port + SATA_ENGINE = 0x03, // SATA + DP_ENGINE = 0x08, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +} dxio_engine_type; + +/* PCIe link capability/speed */ +typedef enum { + GEN_MAX = 0, // Maximum supported + GEN1, + GEN2, + GEN3, + GEN_INVALID // Max Gen for boundary check +} dxio_link_speed_cap; + +/* SATA ChannelType initialization */ +typedef enum { + SATA_CHANNEL_OTHER = 0, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +} dxio_sata_channel_type; + +/* CLKREQ for PCIe type descriptors */ +typedef enum { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4, + CLK_REQ5, + CLK_REQ6, + CLK_REQ7, + CLK_REQ8, + CLK_REQGFX = 0x0c, +} cpm_clk_req; + +/* PCIe link ASPM initialization */ +typedef enum { + ASPM_DISABLED = 0, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +} dxio_aspm_type; + +/* DDI Aux channel */ +typedef enum { + AUX1 = 0, + AUX2, + AUX3, + AUX4, + AUX5, + AUX6, + AUX_MAX // Not valid value, used to verify input +} pcie_aux_type; + +/* DDI Hdp Index */ +typedef enum { + HDP1 = 0, + HDP2, + HDP3, + HDP4, + HDP5, + HDP6, + HDP_MAX // Not valid value, used to verify input +} pcie_hdp_type; + +/* DDI display connector type */ +typedef enum { + DP = 0, // DP + EDP, // eDP + SINGLE_LINK_DVI, // Single Link DVI-D + DUAL_LINK_DVI, // Dual Link DVI-D + HDMI, // HDMI + DP_TO_VGA, // DP-to-VGA + DP_TO_LVDS, // DP-to-LVDS + NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + SINGLE_LINK_DVI_I, // Single Link DVI-I + CRT, // CRT (VGA) + LVDS, // LVDS + EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + AUTO_DETECT, // VBIOS auto detect connector type + UNUSED_PTYPE, // UnusedType + MAX_CONNECTOR_TYPE // Not valid value, used to verify input +} pcie_connector_type; + +/* DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; + uint8_t aux_index; + uint8_t hdp_index; + uint8_t reserved; +} fsp_ddi_descriptor; + +/* PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ +/* Since the code will always be compiled as little endian, using a bitfield struct should be + safe here. */ +typedef struct __packed { + uint8_t engine_type; + uint8_t start_lane; // Start lane of the pci device + uint8_t end_lane; // End lane of the pci device + uint8_t gpio_group_id; // FCH reset number. 0 is global reset + unsigned int port_present :1; // Should be TRUE if train link + unsigned int reserved_3 :7; + unsigned int device_number :5; // Desired root port device number + unsigned int function_number :3; // Desired root port function number + unsigned int link_speed_capability :2; + unsigned int auto_spd_change :2; + unsigned int eq_preset :4; + unsigned int link_aspm :2; + unsigned int link_aspm_L1_1 :1; + unsigned int link_aspm_L1_2 :1; + unsigned int clk_req :4; + uint8_t link_hotplug; + uint8_t slot_power_limit; + unsigned int slot_power_limit_scale :2; + unsigned int reserved_4 :6; + unsigned int link_compliance_mode :1; + unsigned int link_safe_mode :1; + unsigned int sb_link :1; + unsigned int clk_pm_support :1; + unsigned int channel_type :3; + unsigned int turn_off_unused_lanes :1; + uint8_t reserved[4]; +} fsp_pcie_descriptor; + +#endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */ From 18fd26cb088560fe31c3a569eefe2638ed071fc9 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Tue, 3 Mar 2020 10:35:02 -0700 Subject: [PATCH 0652/1463] amdfwtool: Allow for up to 16 APCB entries Increase the number of allowed APCB entries in amdfwtool. BUG=b:150455865 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238 Reviewed-on: https://chromium-review.googlesource.com/2084944 Reviewed-by: Matt Papageorge Reviewed-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861 Reviewed-by: Matt Papageorge Reviewed-by: Angel Pons Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- util/amdfwtool/amdfwtool.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 4f1e8ba0b7..9c50dbd94d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -364,11 +364,33 @@ static amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, @@ -470,7 +492,7 @@ typedef struct _bios_directory_table { bios_directory_entry entries[]; } bios_directory_table; -#define MAX_BIOS_ENTRIES 0x1f +#define MAX_BIOS_ENTRIES 0x22 typedef struct _context { char *rom; /* target buffer, size of flash device */ @@ -1004,7 +1026,8 @@ static void integrate_bios_firmwares(context *ctx, } if (count > MAX_BIOS_ENTRIES) { - printf("Error: BIOS entries exceeds max allowed items\n"); + printf("Error: BIOS entries (%d) exceeds max allowed items " + "(%d)\n", count, MAX_BIOS_ENTRIES); free(ctx->rom); exit(1); } From dd7acaad27e4f99f025df7f06d71dbb49d0e399b Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 25 Mar 2020 11:36:22 +0530 Subject: [PATCH 0653/1463] soc/intel/jasperlake: Add Jasper Lake SoC support This is a copy patch from Tiger Lake SoC code. The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist. Some of the differences are listed below: -> Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE} -> GPIO: GPIO communities have their own differences. This requires conditional checks in gpio.asl, gpio.c, gpio*.h, pmc.h and gpio.asl -> PCI IRQs: Set up differently for JSL and TGL -> PCIe: Number of Root ports differ. -> eMMC/SD: Only supported on JSL. -> USB: Number of USB port are different for JSL and TGL. -> Memory configuration parameters are different for JSL and TGL. -> FSP parameters for JSL and TGL are different. The split of JSL and TGL SoC code is planned as below: 1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds. 2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY. 3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC. 4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC. BUG=b:150217037 Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/jasperlake/Kconfig | 232 +++++++++++ src/soc/intel/jasperlake/Makefile.inc | 66 +++ src/soc/intel/jasperlake/acpi.c | 343 +++++++++++++++ .../jasperlake/acpi/camera_clock_ctl.asl | 76 ++++ src/soc/intel/jasperlake/acpi/gpio.asl | 155 +++++++ src/soc/intel/jasperlake/acpi/gpio_op.asl | 139 ++++++ src/soc/intel/jasperlake/acpi/ipu.asl | 22 + src/soc/intel/jasperlake/acpi/ish.asl | 21 + src/soc/intel/jasperlake/acpi/pch_glan.asl | 26 ++ src/soc/intel/jasperlake/acpi/pch_hda.asl | 82 ++++ src/soc/intel/jasperlake/acpi/pci_irqs.asl | 20 + .../intel/jasperlake/acpi/pci_irqs_jsl.asl | 141 +++++++ .../intel/jasperlake/acpi/pci_irqs_tgl.asl | 167 ++++++++ src/soc/intel/jasperlake/acpi/pcie.asl | 313 ++++++++++++++ src/soc/intel/jasperlake/acpi/platform.asl | 32 ++ src/soc/intel/jasperlake/acpi/pmc.asl | 31 ++ src/soc/intel/jasperlake/acpi/scs.asl | 133 ++++++ src/soc/intel/jasperlake/acpi/serialio.asl | 93 +++++ src/soc/intel/jasperlake/acpi/smbus.asl | 20 + src/soc/intel/jasperlake/acpi/southbridge.asl | 61 +++ src/soc/intel/jasperlake/acpi/xhci.asl | 19 + src/soc/intel/jasperlake/acpi/xhci_jsl.asl | 62 +++ src/soc/intel/jasperlake/acpi/xhci_tgl.asl | 62 +++ .../intel/jasperlake/bootblock/bootblock.c | 43 ++ src/soc/intel/jasperlake/bootblock/cpu.c | 36 ++ src/soc/intel/jasperlake/bootblock/pch.c | 194 +++++++++ .../jasperlake/bootblock/report_platform.c | 246 +++++++++++ src/soc/intel/jasperlake/chip.c | 183 ++++++++ src/soc/intel/jasperlake/chip.h | 299 +++++++++++++ src/soc/intel/jasperlake/cpu.c | 267 ++++++++++++ src/soc/intel/jasperlake/elog.c | 130 ++++++ src/soc/intel/jasperlake/espi.c | 247 +++++++++++ src/soc/intel/jasperlake/finalize.c | 117 ++++++ src/soc/intel/jasperlake/fsp_params_jsl.c | 191 +++++++++ src/soc/intel/jasperlake/fsp_params_tgl.c | 212 ++++++++++ src/soc/intel/jasperlake/gpio_jsl.c | 210 ++++++++++ src/soc/intel/jasperlake/gpio_tgl.c | 197 +++++++++ src/soc/intel/jasperlake/graphics.c | 93 +++++ src/soc/intel/jasperlake/gspi.c | 36 ++ src/soc/intel/jasperlake/i2c.c | 61 +++ .../intel/jasperlake/include/soc/bootblock.h | 27 ++ src/soc/intel/jasperlake/include/soc/cpu.h | 48 +++ src/soc/intel/jasperlake/include/soc/espi.h | 58 +++ src/soc/intel/jasperlake/include/soc/gpe.h | 133 ++++++ src/soc/intel/jasperlake/include/soc/gpio.h | 38 ++ .../intel/jasperlake/include/soc/gpio_defs.h | 23 + .../jasperlake/include/soc/gpio_defs_jsl.h | 272 ++++++++++++ .../jasperlake/include/soc/gpio_defs_tgl.h | 314 ++++++++++++++ .../jasperlake/include/soc/gpio_soc_defs.h | 23 + .../include/soc/gpio_soc_defs_jsl.h | 358 ++++++++++++++++ .../include/soc/gpio_soc_defs_tgl.h | 394 ++++++++++++++++++ src/soc/intel/jasperlake/include/soc/iomap.h | 131 ++++++ src/soc/intel/jasperlake/include/soc/irq.h | 24 ++ .../intel/jasperlake/include/soc/irq_jsl.h | 86 ++++ .../intel/jasperlake/include/soc/irq_tgl.h | 83 ++++ src/soc/intel/jasperlake/include/soc/itss.h | 25 ++ src/soc/intel/jasperlake/include/soc/me.h | 55 +++ .../jasperlake/include/soc/meminit_jsl.h | 124 ++++++ .../jasperlake/include/soc/meminit_tgl.h | 69 +++ src/soc/intel/jasperlake/include/soc/msr.h | 23 + src/soc/intel/jasperlake/include/soc/nvs.h | 20 + src/soc/intel/jasperlake/include/soc/p2sb.h | 29 ++ src/soc/intel/jasperlake/include/soc/pch.h | 28 ++ .../intel/jasperlake/include/soc/pci_devs.h | 209 ++++++++++ .../intel/jasperlake/include/soc/pcr_ids.h | 49 +++ src/soc/intel/jasperlake/include/soc/pm.h | 182 ++++++++ src/soc/intel/jasperlake/include/soc/pmc.h | 168 ++++++++ .../intel/jasperlake/include/soc/ramstage.h | 26 ++ .../intel/jasperlake/include/soc/romstage.h | 32 ++ .../intel/jasperlake/include/soc/serialio.h | 48 +++ src/soc/intel/jasperlake/include/soc/smbus.h | 47 +++ .../intel/jasperlake/include/soc/soc_chip.h | 20 + .../jasperlake/include/soc/systemagent.h | 79 ++++ src/soc/intel/jasperlake/include/soc/usb.h | 151 +++++++ src/soc/intel/jasperlake/lockdown.c | 77 ++++ src/soc/intel/jasperlake/meminit_jsl.c | 126 ++++++ src/soc/intel/jasperlake/meminit_tgl.c | 163 ++++++++ src/soc/intel/jasperlake/p2sb.c | 48 +++ src/soc/intel/jasperlake/pmc.c | 113 +++++ src/soc/intel/jasperlake/pmutil.c | 286 +++++++++++++ src/soc/intel/jasperlake/reset.c | 46 ++ .../intel/jasperlake/romstage/Makefile.inc | 20 + .../jasperlake/romstage/fsp_params_jsl.c | 145 +++++++ .../jasperlake/romstage/fsp_params_tgl.c | 208 +++++++++ src/soc/intel/jasperlake/romstage/pch.c | 26 ++ src/soc/intel/jasperlake/romstage/romstage.c | 134 ++++++ .../intel/jasperlake/romstage/systemagent.c | 47 +++ src/soc/intel/jasperlake/sd.c | 42 ++ src/soc/intel/jasperlake/smihandler.c | 53 +++ src/soc/intel/jasperlake/smmrelocate.c | 261 ++++++++++++ src/soc/intel/jasperlake/spi.c | 38 ++ src/soc/intel/jasperlake/systemagent.c | 80 ++++ src/soc/intel/jasperlake/uart.c | 75 ++++ 93 files changed, 10462 insertions(+) create mode 100644 src/soc/intel/jasperlake/Kconfig create mode 100644 src/soc/intel/jasperlake/Makefile.inc create mode 100644 src/soc/intel/jasperlake/acpi.c create mode 100644 src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl create mode 100644 src/soc/intel/jasperlake/acpi/gpio.asl create mode 100644 src/soc/intel/jasperlake/acpi/gpio_op.asl create mode 100644 src/soc/intel/jasperlake/acpi/ipu.asl create mode 100644 src/soc/intel/jasperlake/acpi/ish.asl create mode 100644 src/soc/intel/jasperlake/acpi/pch_glan.asl create mode 100644 src/soc/intel/jasperlake/acpi/pch_hda.asl create mode 100644 src/soc/intel/jasperlake/acpi/pci_irqs.asl create mode 100644 src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl create mode 100644 src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl create mode 100644 src/soc/intel/jasperlake/acpi/pcie.asl create mode 100644 src/soc/intel/jasperlake/acpi/platform.asl create mode 100644 src/soc/intel/jasperlake/acpi/pmc.asl create mode 100644 src/soc/intel/jasperlake/acpi/scs.asl create mode 100644 src/soc/intel/jasperlake/acpi/serialio.asl create mode 100644 src/soc/intel/jasperlake/acpi/smbus.asl create mode 100644 src/soc/intel/jasperlake/acpi/southbridge.asl create mode 100644 src/soc/intel/jasperlake/acpi/xhci.asl create mode 100644 src/soc/intel/jasperlake/acpi/xhci_jsl.asl create mode 100644 src/soc/intel/jasperlake/acpi/xhci_tgl.asl create mode 100644 src/soc/intel/jasperlake/bootblock/bootblock.c create mode 100644 src/soc/intel/jasperlake/bootblock/cpu.c create mode 100644 src/soc/intel/jasperlake/bootblock/pch.c create mode 100644 src/soc/intel/jasperlake/bootblock/report_platform.c create mode 100644 src/soc/intel/jasperlake/chip.c create mode 100644 src/soc/intel/jasperlake/chip.h create mode 100644 src/soc/intel/jasperlake/cpu.c create mode 100644 src/soc/intel/jasperlake/elog.c create mode 100644 src/soc/intel/jasperlake/espi.c create mode 100644 src/soc/intel/jasperlake/finalize.c create mode 100644 src/soc/intel/jasperlake/fsp_params_jsl.c create mode 100644 src/soc/intel/jasperlake/fsp_params_tgl.c create mode 100644 src/soc/intel/jasperlake/gpio_jsl.c create mode 100644 src/soc/intel/jasperlake/gpio_tgl.c create mode 100644 src/soc/intel/jasperlake/graphics.c create mode 100644 src/soc/intel/jasperlake/gspi.c create mode 100644 src/soc/intel/jasperlake/i2c.c create mode 100644 src/soc/intel/jasperlake/include/soc/bootblock.h create mode 100644 src/soc/intel/jasperlake/include/soc/cpu.h create mode 100644 src/soc/intel/jasperlake/include/soc/espi.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpe.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpio.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpio_defs.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h create mode 100644 src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h create mode 100644 src/soc/intel/jasperlake/include/soc/iomap.h create mode 100644 src/soc/intel/jasperlake/include/soc/irq.h create mode 100644 src/soc/intel/jasperlake/include/soc/irq_jsl.h create mode 100644 src/soc/intel/jasperlake/include/soc/irq_tgl.h create mode 100644 src/soc/intel/jasperlake/include/soc/itss.h create mode 100644 src/soc/intel/jasperlake/include/soc/me.h create mode 100644 src/soc/intel/jasperlake/include/soc/meminit_jsl.h create mode 100644 src/soc/intel/jasperlake/include/soc/meminit_tgl.h create mode 100644 src/soc/intel/jasperlake/include/soc/msr.h create mode 100644 src/soc/intel/jasperlake/include/soc/nvs.h create mode 100644 src/soc/intel/jasperlake/include/soc/p2sb.h create mode 100644 src/soc/intel/jasperlake/include/soc/pch.h create mode 100644 src/soc/intel/jasperlake/include/soc/pci_devs.h create mode 100644 src/soc/intel/jasperlake/include/soc/pcr_ids.h create mode 100644 src/soc/intel/jasperlake/include/soc/pm.h create mode 100644 src/soc/intel/jasperlake/include/soc/pmc.h create mode 100644 src/soc/intel/jasperlake/include/soc/ramstage.h create mode 100644 src/soc/intel/jasperlake/include/soc/romstage.h create mode 100644 src/soc/intel/jasperlake/include/soc/serialio.h create mode 100644 src/soc/intel/jasperlake/include/soc/smbus.h create mode 100644 src/soc/intel/jasperlake/include/soc/soc_chip.h create mode 100644 src/soc/intel/jasperlake/include/soc/systemagent.h create mode 100644 src/soc/intel/jasperlake/include/soc/usb.h create mode 100644 src/soc/intel/jasperlake/lockdown.c create mode 100644 src/soc/intel/jasperlake/meminit_jsl.c create mode 100644 src/soc/intel/jasperlake/meminit_tgl.c create mode 100644 src/soc/intel/jasperlake/p2sb.c create mode 100644 src/soc/intel/jasperlake/pmc.c create mode 100644 src/soc/intel/jasperlake/pmutil.c create mode 100644 src/soc/intel/jasperlake/reset.c create mode 100644 src/soc/intel/jasperlake/romstage/Makefile.inc create mode 100644 src/soc/intel/jasperlake/romstage/fsp_params_jsl.c create mode 100644 src/soc/intel/jasperlake/romstage/fsp_params_tgl.c create mode 100644 src/soc/intel/jasperlake/romstage/pch.c create mode 100644 src/soc/intel/jasperlake/romstage/romstage.c create mode 100644 src/soc/intel/jasperlake/romstage/systemagent.c create mode 100644 src/soc/intel/jasperlake/sd.c create mode 100644 src/soc/intel/jasperlake/smihandler.c create mode 100644 src/soc/intel/jasperlake/smmrelocate.c create mode 100644 src/soc/intel/jasperlake/spi.c create mode 100644 src/soc/intel/jasperlake/systemagent.c create mode 100644 src/soc/intel/jasperlake/uart.c diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig new file mode 100644 index 0000000000..ed2fece152 --- /dev/null +++ b/src/soc/intel/jasperlake/Kconfig @@ -0,0 +1,232 @@ +config SOC_INTEL_TIGERLAKE_BASE_COPY + bool + +config SOC_INTEL_TIGERLAKE_COPY + bool + select SOC_INTEL_TIGERLAKE_BASE_COPY + #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM + help + Intel Tigerlake support + +config SOC_INTEL_JASPERLAKE_COPY + bool + select SOC_INTEL_TIGERLAKE_BASE_COPY + select INTEL_CAR_NEM + help + Intel Jasperlake support + +if SOC_INTEL_TIGERLAKE_BASE_COPY + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select COMMON_FADT + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MRC_SETTINGS_PROTECT + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_1 + select REG_SCRIPT + select SMP + select SOC_AHCI_PORT_IMPLEMENTED_INVERT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select CPU_INTEL_COMMON_SMM + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_CAR + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_2017_BINDING + select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM + +config DCACHE_RAM_BASE + default 0xfef00000 + +config DCACHE_RAM_SIZE + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x40400 if SOC_INTEL_TIGERLAKE_COPY + default 0x30400 if SOC_INTEL_JASPERLAKE_COPY + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage + stack requirement (~1KiB). + +config FSP_TEMP_RAM_SIZE + hex + default 0x20000 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +config IFD_CHIPSET + string + default "jsl" if SOC_INTEL_JASPERLAKE_COPY + default "tgl" if SOC_INTEL_TIGERLAKE_COPY + +config IED_REGION_SIZE + hex + default 0x400000 + +config HEAP_SIZE + hex + default 0x8000 + +config MAX_ROOT_PORTS + int + default 8 if SOC_INTEL_JASPERLAKE_COPY + default 12 if SOC_INTEL_TIGERLAKE_COPY + +config MAX_PCIE_CLOCKS + int + default 7 if SOC_INTEL_TIGERLAKE_COPY + default 6 if SOC_INTEL_JASPERLAKE_COPY + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config SMM_RESERVED_SIZE + hex + default 0x200000 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + +config CPU_BCLK_MHZ + int + default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + default 120 + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 3 if SOC_INTEL_JASPERLAKE_COPY + default 4 if SOC_INTEL_TIGERLAKE_COPY + +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + +config SOC_INTEL_UART_DEV_MAX + int + default 3 + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +# Clock divider parameters for 115200 baud rate +# Baudrate = (UART source clcok * M) /(N *16) +# TGL UART source clock: 120MHz +# JSL UART source clock: 100MHz +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x30 if SOC_INTEL_JASPERLAKE_COPY + default 0x25a if SOC_INTEL_TIGERLAKE_COPY + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0xc35 if SOC_INTEL_JASPERLAKE_COPY + default 0x7fff if SOC_INTEL_TIGERLAKE_COPY + +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config CBFS_SIZE + hex + default 0x200000 + +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE_COPY + default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE_COPY + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE_COPY + default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE_COPY + +config SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT + int "Debug Consent for TGL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual +endif diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc new file mode 100644 index 0000000000..b02dc10250 --- /dev/null +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -0,0 +1,66 @@ +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE_COPY),y) + +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c +bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c +bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +bootblock-y += p2sb.c + +romstage-y += espi.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += meminit_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += meminit_jsl.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +romstage-y += reset.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += espi.c +ramstage-y += finalize.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c +ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c +ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +ramstage-y += graphics.c +ramstage-y += lockdown.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += smmrelocate.c +ramstage-y += systemagent.c +ramstage-y += sd.c + +smm-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c +smm-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +smm-y += p2sb.c +smm-y += pmc.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += uart.c + +verstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c + +CPPFLAGS_common += -I$(src)/soc/intel/tigerlake +CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include + +endif diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c new file mode 100644 index 0000000000..23fd970500 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi.c @@ -0,0 +1,343 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * List of supported C-states in this processor. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C6_SHORT_LAT, /* 3 */ + C_STATE_C6_LONG_LAT, /* 4 */ + C_STATE_C7_SHORT_LAT, /* 5 */ + C_STATE_C7_LONG_LAT, /* 6 */ + C_STATE_C7S_SHORT_LAT, /* 7 */ + C_STATE_C7S_LONG_LAT, /* 8 */ + C_STATE_C8, /* 9 */ + C_STATE_C9, /* 10 */ + C_STATE_C10, /* 11 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static const acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = {}, + [C_STATE_C1] = { + .latency = 0, + .power = C1_POWER, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = C1_POWER, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C6_POWER, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C6_POWER, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C8_POWER, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C9_POWER, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C10_POWER, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_non_s0ix[] = { + C_STATE_C1E, + C_STATE_C6_LONG_LAT, + C_STATE_C7S_LONG_LAT +}; + +static int cstate_set_s0ix[] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), + ARRAY_SIZE(cstate_set_non_s0ix))]; + int *set; + int i; + + config_t *config = config_of_soc(); + + int is_s0ix_enable = config->s0ix_enable; + + if (is_s0ix_enable) { + *entries = ARRAY_SIZE(cstate_set_s0ix); + set = cstate_set_s0ix; + } else { + *entries = ARRAY_SIZE(cstate_set_non_s0ix); + set = cstate_set_non_s0ix; + } + + for (i = 0; i < *entries; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + return map; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ + config_t *config = config_of_soc(); + + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, cores_per_package); +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + config_t *config = config_of_soc(); + + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = 4; + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + if (config->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; +} + +uint32_t soc_read_sci_irq_select(void) +{ + uintptr_t pmc_bar = soc_read_pmc_base(); + return read32((void *)pmc_bar + IRQ_REG); +} + +static unsigned long soc_fill_dmar(unsigned long current) +{ + const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; + bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; + + if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 5, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; + bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; + + if (vtvc0bar && vtvc0en) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* TCSS Thunderbolt root ports */ + for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { + uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK; + bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED; + if (tbtbar && tbten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* + * Create DMAR table only if we have VT-d capability and FSP does not override its + * feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + +void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + config_t *config = config_of_soc(); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + if (CONFIG(CONSOLE_CBMEM)) + /* Update the mem console pointer. */ + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = config->dptf_enable; + + /* Fill in the Wifi Region id */ + gnvs->cid1 = wifi_regulatory_domain(); + + /* Set USB2/USB3 wake enable bitmaps. */ + gnvs->u2we = config->usb2_wake_enable_bitmap; + gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, + const struct chipset_power_state *ps) +{ + /* + * WAK_STS bit is set when the system is in one of the sleep states + * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting + * this bit, the PMC will transition the system to the ON state and + * can only be set by hardware and can only be cleared by writing a one + * to this bit position. + */ + + generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + return generic_pm1_en; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_HIGH; +} diff --git a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl new file mode 100644 index 0000000000..4f08cd78bd --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define R_ICLK_PCR_CAMERA1 0x8000 +#define B_ICLK_PCR_FREQUENCY 0x1 +#define B_ICLK_PCR_REQUEST 0x2 + +/* The clock control registers for each IMGCLK are offset by 0xC */ +#define B_ICLK_PCR_OFFSET 0xC + +Scope (\_SB.PCI0) { + + /* IsCLK PCH base register for clock settings */ + Name (ICKB, 0) + Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) + + /* + * Arg0 : Clock Number + * Return : Offset of register to control the clock in Arg0 + * + */ + Method (OFST, 0x1, NotSerialized) + { + Return (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)) + } + + /* + * Helper function for Read And OR Write + * Arg0 : source and destination + * Arg1 : And data + * Arg2 : Or data + */ + Method (RAOW, 0x3, Serialized) + { + OperationRegion (ICLK, SystemMemory, OFST(Arg0), 4) + Field (ICLK, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 + } + + /* + * Clock control Method + * Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3, + * 4: IMGCLKOUT_4, 5: IMGCLKOUT_5) + * Arg1: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz) + */ + Method (MCON, 0x2, NotSerialized) + { + /* Set Clock Frequency */ + RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) + + /* Enable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST) + } + + Method (MCOF, 0x1, NotSerialized) + { + /* Disable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0) + } +} diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl new file mode 100644 index 0000000000..9bf0c6032f --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include "gpio_op.asl" + +Device (GCM0) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller Community 0") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM1) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 1) + Name (_DDN, "GPIO Controller Community 1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM4) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 4) + Name (_DDN, "GPIO Controller Community 4") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM5) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 5) + Name (_DDN, "GPIO Controller Community 5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl new file mode 100644 index 0000000000..4444c09a5b --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Get GPIO Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (PAD_CFG0_TX_STATE, VAL0, Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (PAD_CFG0_TX_STATE, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0) +} + +/* + * Set Pad mode + * Arg0 - GPIO Number + * Arg1 - Pad mode + * 0 = GPIO control pad + * 1 = Native Function 1 + * 2 = Native Function 2 + * 3 = Native Function 3 + */ +Method (GPMO, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Store (VAL0, Local0) + And (Not (PAD_CFG0_MODE_MASK), Local0, Local0) + And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1) + Or (Local0, Arg1, VAL0) +} + +/* + * Enable/Disable Tx buffer + * Arg0 - GPIO Number + * Arg1 - TxBuffer state + * 0 = Disable Tx Buffer + * 1 = Enable Tx Buffer + */ +Method (GTXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (LEqual (Arg1, 1)) { + And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0) + } ElseIf (LEqual (Arg1, 0)){ + Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0) + } +} + +/* + * Enable/Disable Rx buffer + * Arg0 - GPIO Number + * Arg1 - RxBuffer state + * 0 = Disable Rx Buffer + * 1 = Enable Rx Buffer + */ +Method (GRXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (LEqual (Arg1, 1)) { + And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0) + } ElseIf (LEqual (Arg1, 0)){ + Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0) + } +} diff --git a/src/soc/intel/jasperlake/acpi/ipu.asl b/src/soc/intel/jasperlake/acpi/ipu.asl new file mode 100644 index 0000000000..5711644bcb --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/ipu.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) + Name (_DDN, "Camera and Imaging Subsystem") + } +} diff --git a/src/soc/intel/jasperlake/acpi/ish.asl b/src/soc/intel/jasperlake/acpi/ish.asl new file mode 100644 index 0000000000..ee3f1a3fdf --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/ish.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Integrated Sensor Hub Controller 0:12.0 */ + +Device (ISHB) +{ + Name (_ADR, 0x00120000) + Name (_DDN, "Integrated Sensor Hub Controller") +} diff --git a/src/soc/intel/jasperlake/acpi/pch_glan.asl b/src/soc/intel/jasperlake/acpi/pch_glan.asl new file mode 100644 index 0000000000..2d9d960565 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/pch_glan.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Gigabit Ethernet Controller 0:1f.6 */ + +Device (GLAN) +{ + Name (_ADR, 0x001f0006) + + Name (_S0W, 3) + + Name (_PRW, Package() {GPE0_PME_B0, 4}) + + Method (_DSW, 3) {} +} diff --git a/src/soc/intel/jasperlake/acpi/pch_hda.asl b/src/soc/intel/jasperlake/acpi/pch_hda.asl new file mode 100644 index 0000000000..0d10d2deb5 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/pch_hda.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl new file mode 100644 index 0000000000..474a6d6c1e --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include "pci_irqs_tgl.asl" +#else + #include "pci_irqs_jsl.asl" +#endif diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl new file mode 100644 index 0000000000..086282e733 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Name (PICP, Package () { + /* cAVS, SMBus, GbE, Northpeak */ + Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, + Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ }, + /* SerialIo */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* eMMC */ + Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, + /* SerialIo */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* SATA controller */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 2, 0, IDER_IRQ }, + Package(){0x0016FFFF, 3, 0, KT_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* SerialIo */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ + Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, + Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, + Package(){0x0014FFFF, 5, 0, SD_IRQ }, + /* SerialIo */ + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Northpeak */ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 10 }, + Package () { 0x001FFFFF, 6, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D30: SerialIo */ + Package () {0x001EFFFF, 0, 0, 11 }, + Package () {0x001EFFFF, 1, 0, 10 }, + Package () {0x001EFFFF, 2, 0, 11 }, + Package () {0x001EFFFF, 3, 0, 11 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D26: eMMC */ + Package(){0x001AFFFF, 0, 0, 11 }, + /* D25: SerialIo */ + Package () {0x0019FFFF, 0, 0, 11 }, + Package () {0x0019FFFF, 1, 0, 10 }, + Package () {0x0019FFFF, 2, 0, 11 }, + /* D23: SATA controller */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, 0, 11 }, + Package () { 0x0016FFFF, 1, 0, 10 }, + Package () { 0x0016FFFF, 2, 0, 11 }, + Package () { 0x0016FFFF, 3, 0, 11 }, + Package () { 0x0016FFFF, 4, 0, 11 }, + Package () { 0x0016FFFF, 5, 0, 11 }, + /* D21: SerialIo */ + Package () {0x0015FFFF, 0, 0, 11 }, + Package () {0x0015FFFF, 1, 0, 10 }, + Package () {0x0015FFFF, 2, 0, 11 }, + Package () {0x0015FFFF, 3, 0, 11 }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ + Package () { 0x0014FFFF, 0, 0, 11 }, + Package () { 0x0014FFFF, 1, 0, 10 }, + Package () { 0x0014FFFF, 2, 0, 11 }, + Package () { 0x0014FFFF, 3, 0, 11 }, + Package () { 0x0014FFFF, 5, 0, 11 }, + /* D18: SerialIo */ + Package () {0x0012FFFF, 6, 0, 11 }, + /* SA IGFX Device */ + Package () {0x0002FFFF, 0, 0, 11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, 11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, 11 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl new file mode 100644 index 0000000000..7f632ba32e --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Name (PICP, Package () { + /* D31:HSA, SMBUS, TraceHUB */ + Package(){0x001FFFFF, 3, 0, HDA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* D29: RP9 ~ RP12 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* D28: RP1 ~ RP8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* D23: SATA */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ + Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, + Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, ISH_IRQ }, + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, + Package(){0x0010FFFF, 6, 0, THC0_IRQ }, + Package(){0x0010FFFF, 7, 0, THC1_IRQ }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, + Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, PEG_IRQ }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, +}) + +Name (PICN, Package () { + /* D31:HSA, SMBUS, TraceHUB*/ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package () { 0x001EFFFF, 0, 0, 11 }, + Package () { 0x001EFFFF, 1, 0, 10 }, + Package () { 0x001EFFFF, 2, 0, 11 }, + Package () { 0x001EFFFF, 3, 0, 11 }, + /* D29: RP9 ~ RP12 */ + Package () { 0x001DFFFF, 0, 0, 11 }, + Package () { 0x001DFFFF, 1, 0, 10 }, + Package () { 0x001DFFFF, 2, 0, 11 }, + Package () { 0x001DFFFF, 3, 0, 11 }, + /* D28: RP1 ~ RP8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, 11 }, + Package(){0x0019FFFF, 1, 0, 10 }, + Package(){0x0019FFFF, 2, 0, 11 }, + /* D23: SATA */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, 11 }, + Package(){0x0016FFFF, 1, 0, 10 }, + Package(){0x0016FFFF, 4, 0, 11 }, + Package(){0x0016FFFF, 5, 0, 11 }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, 11 }, + Package(){0x0015FFFF, 1, 0, 10 }, + Package(){0x0015FFFF, 2, 0, 11 }, + Package(){0x0015FFFF, 3, 0, 11 }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, 11 }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, 11 }, + Package(){0x0012FFFF, 6, 0, 11 },, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, 11 }, + Package(){0x0010FFFF, 6, 0, 11 }, + Package(){0x0010FFFF, 7, 0, 10 }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, 11 }, + Package(){0x000DFFFF, 1, 0, 10 }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, 11 }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, 11 }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, 11 }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, 11 }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/jasperlake/acpi/pcie.asl b/src/soc/intel/jasperlake/acpi/pcie.asl new file mode 100644 index 0000000000..53ae316413 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/pcie.asl @@ -0,0 +1,313 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 10 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, 0, 10 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 10 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 10 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/jasperlake/acpi/platform.asl b/src/soc/intel/jasperlake/acpi/platform.asl new file mode 100644 index 0000000000..682a7b93d8 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/platform.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include +/* Generic indicator for sleep state */ +#include + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl new file mode 100644 index 0000000000..6dd2d35354 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/pmc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Scope (\_SB.PCI0) { + + Device (PMC) + { + Name (_HID, "INTC1026") + Name (_DDN, "Intel(R) Tiger Lake IPC Controller") + /* + * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. + * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + }) + } +} diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl new file mode 100644 index 0000000000..83da7e0f06 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Scope (\_SB.PCI0) { + + /* + * Clear register 0x1C20/0x4820 + * Arg0 - PCR Port ID + */ + Method(SCSC, 1, Serialized) + { + PCRA (Arg0, 0x1C20, 0x0) + PCRA (Arg0, 0x4820, 0x0) + } + + /* EMMC */ + Device(PEMC) { + Name(_ADR, 0x001A0000) + Name (_DDN, "eMMC Controller") + Name (TEMP, 0) + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field(SCSR, WordAcc, NoLock, Preserve) { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + } + + Method(_PS0, 0, Serialized) { + Stall (50) // Sleep 50 us + + Store(0, PGEN) // Disable PG + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + + /* Set Power State to D0 */ + And (PMCR, 0xFFFC, PMCR) + Store (PMCR, TEMP) + } + + Method(_PS3, 0, Serialized) { + Store(1, PGEN) // Enable PG + + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, TEMP) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } + + /* SD CARD */ + Device (SDXC) + { + Name (_ADR, 0x00140005) + Name (_DDN, "SD Controller") + Name (TEMP, 0) + + OperationRegion (SDPC, PCI_Config, 0x00, 0x100) + Field (SDPC, WordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) + { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + } + + Method (_PS0, 0, Serialized) + { + Store (0, PGEN) /* Disable PG */ + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + + /* Set Power State to D0 */ + And (PMCR, 0xFFFC, PMCR) + Store (PMCR, TEMP) + } + + Method (_PS3, 0, Serialized) + { + Store (1, PGEN) /* Enable PG */ + + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, TEMP) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } + } /* Device (SDXC) */ +} diff --git a/src/soc/intel/jasperlake/acpi/serialio.asl b/src/soc/intel/jasperlake/acpi/serialio.asl new file mode 100644 index 0000000000..6fd135b437 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/serialio.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (SPI3) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "Serial IO SPI Controller 3") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/jasperlake/acpi/smbus.asl b/src/soc/intel/jasperlake/acpi/smbus.asl new file mode 100644 index 0000000000..f273e3669d --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/smbus.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel SMBus Controller 0:1f.4 */ + +Device (SBUS) +{ + Name (_ADR, 0x001f0004) +} diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl new file mode 100644 index 0000000000..6329340392 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* PCR access */ +#include + +/* PCH clock */ +#include "camera_clock_ctl.asl" + +/* GPIO controller */ +#include "gpio.asl" + +/* ESPI 0:1f.0 */ +#include + +/* PCH HDA */ +#include "pch_hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* pmc 0:1f.2 */ +#include "pmc.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.4 */ +#include "smbus.asl" + +/* ISH 0:12.0 */ +#include "ish.asl" + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include + +/* PMC Core*/ +#include diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl new file mode 100644 index 0000000000..9baf67ac5a --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/xhci.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include "xhci_tgl.asl" +#else + #include "xhci_jsl.asl" +#endif diff --git a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl new file mode 100644 index 0000000000..41be89ace1 --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Jasperlake PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 9) } + Device (SS02) { Name (_ADR, 10) } + Device (SS03) { Name (_ADR, 11) } + Device (SS04) { Name (_ADR, 12) } + Device (SS05) { Name (_ADR, 13) } + Device (SS06) { Name (_ADR, 14) } + } +} diff --git a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl new file mode 100644 index 0000000000..b97f52052b --- /dev/null +++ b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Tigerlake-LP PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + } +} diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c new file mode 100644 index 0000000000..1abca127a3 --- /dev/null +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + bootblock_pch_early_init(); + bootblock_cpu_init(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + pch_init(); +} diff --git a/src/soc/intel/jasperlake/bootblock/cpu.c b/src/soc/intel/jasperlake/bootblock/cpu.c new file mode 100644 index 0000000000..dddf24352d --- /dev/null +++ b/src/soc/intel/jasperlake/bootblock/cpu.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 6 + */ + +#include +#include + +void bootblock_cpu_init(void) +{ + /* + * Tigerlake platform doesn't support booting from any other media + * (like eMMC on APL/GLK platform) than only booting from SPI device + * and on IA platform SPI is memory mapped hence enabling temporarily + * cacheing on memory-mapped spi boot media. + * + * This assumption will not hold good for APL/GLK platform where boot + * from eMMC is also possible options. + */ + fast_spi_cache_bios_region(); +} diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c new file mode 100644 index 0000000000..b0646018c6 --- /dev/null +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 2, 3, 4, 27, 28 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00 +#define PCR_PSFX_TO_SHDW_BAR0 0 +#define PCR_PSFX_TO_SHDW_BAR1 0x4 +#define PCR_PSFX_TO_SHDW_BAR2 0x8 +#define PCR_PSFX_TO_SHDW_BAR3 0xC +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static uint32_t get_pmc_reg_base(void) +{ + uint8_t pch_series; + + pch_series = get_pch_series(); + + if (pch_series == PCH_TGP) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP; + else if (pch_series == PCH_JSP) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP; + else + return 0; +} + +static void soc_config_pwrmbase(void) +{ + uint32_t reg32; + + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MEMORY); + pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); + reg32 |= PCI_COMMAND_MEMORY; + pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + + /* Enable PWRM in PMC */ + reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); + write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); +} + +void bootblock_pch_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + p2sb_enable_bar(); + p2sb_configure_hpet(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + uint32_t pmc_base_reg; + + pmc_base_reg = get_pmc_reg_base(); + if (!pmc_base_reg) + die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n"); + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF3 PMC space BAR4*/ + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +static int pch_check_decode_enable(void) +{ + uint32_t dmi_control; + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); + } + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); +} diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c new file mode 100644 index 0000000000..d7b2e0db32 --- /dev/null +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Platform Stepping and IDs + * Document number: 605534 + * Chapter number: 2, 4, 5, 6 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BIOS_SIGN_ID 0x8B + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, + { CPUID_JASPERLAKE_A0, "Jasperlake A0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, + { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" }, + { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, + { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, + { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, + { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, + { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" }, + { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, + { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, + { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, + { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, + { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" }, +}; + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index, cpu_id, cpu_feature_flag; + const char cpu_not_found[] = "Platform info not available"; + const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ + int vt, txt, aes; + msr_t microcode_ver; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + u32 p[13]; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax >= 0x80000004) { + int j = 0; + + for (i = 2; i <= 4; i++) { + cpuidr = cpuid(index + i); + p[j++] = cpuidr.eax; + p[j++] = cpuidr.ebx; + p[j++] = cpuidr.ecx; + p[j++] = cpuidr.edx; + } + p[12] = 0; + cpu_name = (char *)p; + + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) + cpu_name++; + } + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(BIOS_SIGN_ID, microcode_ver); + cpu_id = cpu_get_cpuid(); + microcode_ver = rdmsr(BIOS_SIGN_ID); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, microcode_ver.hi); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; + txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; + vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + uint8_t mch_revision = get_dev_revision(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c new file mode 100644 index 0000000000..1c7078d6cf --- /dev/null +++ b/src/soc/intel/jasperlake/chip.c @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + return NULL; + } + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_GBE: return "GLAN"; + } + + return NULL; +} +#endif + +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const config_t *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + +void soc_init_pre_device(void *chip_info) +{ + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + /* Perform silicon specific init. */ + fsp_silicon_init(romstage_handoff_is_resume()); + + /* Display FIRMWARE_VERSION_INFO_HOB */ + fsp_display_fvi_version_hob(); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + soc_fill_gpio_pm_configuration(); +} + +static void pci_domain_set_resources(struct device *dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = DEVICE_NOOP, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif +}; + +static void soc_enable(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; +} + +struct chip_operations soc_intel_tigerlake_ops = { + CHIP_NAME("Intel Tigerlake") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +}; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h new file mode 100644 index 0000000000..f82f13d45b --- /dev/null +++ b/src/soc/intel/jasperlake/chip.h @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 + +struct soc_intel_tigerlake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form PMC_GPP_[A:U] or GPD. */ + uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable S0iX support */ + int s0ix_enable; + /* Enable DPTF support */ + int dptf_enable; + + /* Deep SX enable for both AC and DC */ + int deep_s3_enable_ac; + int deep_s3_enable_dc; + int deep_s5_enable_ac; + int deep_s5_enable_dc; + + /* Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ + uint32_t deep_sx_config; + + /* TCC activation offset */ + uint32_t tcc_offset; + + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * When enabled memory will be training at two different frequencies. + * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, + * 4:FixedPoint3, 5:Enabled */ + enum { + SaGv_Disabled, + SaGv_FixedPoint0, + SaGv_FixedPoint1, + SaGv_FixedPoint2, + SaGv_FixedPoint3, + SaGv_Enabled, + } SaGv; + + /* Rank Margin Tool. 1:Enable, 0:Disable */ + uint8_t RMT; + + /* USB related */ + struct usb2_port_config usb2_ports[16]; + struct usb3_port_config usb3_ports[10]; + /* Wake Enable Bitmap for USB2 ports */ + uint16_t usb2_wake_enable_bitmap; + /* Wake Enable Bitmap for USB3 ports */ + uint16_t usb3_wake_enable_bitmap; + + /* SATA related */ + uint8_t SataEnable; + uint8_t SataMode; + uint8_t SataSalpSupport; + uint8_t SataPortsEnable[8]; + uint8_t SataPortsDevSlp[8]; + + /* Audio related */ + uint8_t PchHdaDspEnable; + uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; + uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; + uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispLinkTmode; + uint8_t PchHdaIDispLinkFrequency; + uint8_t PchHdaIDispCodecDisconnect; + + /* PCIe Root Ports */ + uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe output clocks type to PCIe devices. + * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, + * 0xFF: not used */ + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to + * clksrc. */ + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + + /* PCIe RP L1 substate */ + enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, + } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + + /* SMBus */ + uint8_t SmbusEnable; + + /* eMMC and SD */ + uint8_t ScsEmmcHs400Enabled; + + /* Enable if SD Card Power Enable Signal is Active High */ + uint8_t SdCardPowerEnableActiveHigh; + + /* Integrated Sensor */ + uint8_t PchIshEnable; + + /* Heci related */ + uint8_t Heci3Enabled; + + /* Gfx related */ + uint8_t IgdDvmt50PreAlloc; + uint8_t InternalGfx; + uint8_t SkipExtGfxScan; + + uint32_t GraphicsConfigPtr; + uint8_t Device4Enable; + + /* HeciEnabled decides the state of Heci1 at end of boot + * Setting to 0 (default) disables Heci1 and hides the device from OS */ + uint8_t HeciEnabled; + /* PL2 Override value in Watts */ + uint32_t tdp_pl2_override; + /* Intel Speed Shift Technology */ + uint8_t speed_shift_enable; + + /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + uint8_t eist_enable; + + /* Enable C6 DRAM */ + uint8_t enable_c6dram; + /* + * PRMRR size setting with below options + * Disable: 0x0 + * 32MB: 0x2000000 + * 64MB: 0x4000000 + * 128 MB: 0x8000000 + * 256 MB: 0x10000000 + * 512 MB: 0x20000000 + */ + uint32_t PrmrrSize; + uint8_t PmTimerDisabled; + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + /* + * GSPIn Default Chip Select Mode: + * 0:Hardware Mode, + * 1:Software Mode + */ + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * GSPIn Default Chip Select State: + * 0: Low, + * 1: High + */ + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* + * TraceHubMode config + * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode + */ + uint8_t TraceHubMode; + + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = (1 << 0), + DEBUG_INTERFACE_UART = (1 << 1), + DEBUG_INTERFACE_USB3 = (1 << 3), + DEBUG_INTERFACE_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_TRACEHUB = (1 << 5), + } debug_interface_flag; + + /* GPIO SD card detect pin */ + unsigned int sdcard_cd_gpio; + + /* Enable Pch iSCLK */ + uint8_t pch_isclk; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + enum { + FORCE_DISABLE, + FORCE_ENABLE, + } CnviBtAudioOffload; + + /* Tcss */ + uint8_t TcssXhciEn; + uint8_t TcssXdciEn; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* DP config */ + /* + * Port config + * 0:Disabled, 1:eDP, 2:MIPI DSI + */ + uint8_t DdiPortAConfig; + uint8_t DdiPortBConfig; + + /* Enable(1)/Disable(0) HPD */ + uint8_t DdiPortAHpd; + uint8_t DdiPortBHpd; + uint8_t DdiPortCHpd; + uint8_t DdiPort1Hpd; + uint8_t DdiPort2Hpd; + uint8_t DdiPort3Hpd; + uint8_t DdiPort4Hpd; + + /* Enable(1)/Disable(0) DDC */ + uint8_t DdiPortADdc; + uint8_t DdiPortBDdc; + uint8_t DdiPortCDdc; + uint8_t DdiPort1Ddc; + uint8_t DdiPort2Ddc; + uint8_t DdiPort3Ddc; + uint8_t DdiPort4Ddc; + + /* Hybrid storage mode enable (1) / disable (0) + * This mode makes FSP detect Optane and NVME and set PCIe lane mode + * accordingly */ + uint8_t HybridStorageMode; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * Only override CPU flex ratio to not boot with non-turbo max. + */ + uint8_t cpu_ratio_override; + +}; + +typedef struct soc_intel_tigerlake_config config_t; + +#endif diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c new file mode 100644 index 0000000000..dfbcd22b94 --- /dev/null +++ b/src/soc/intel/jasperlake/cpu.c @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor CPU Datasheet + * Document number: 575683 + * Chapter number: 15 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void soc_fsp_load(void) +{ + fsps_load(romstage_handoff_is_resume()); +} + +static void configure_isst(void) +{ + config_t *conf = config_of_soc(); + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + +static void configure_misc(void) +{ + msr_t msr; + + config_t *conf = config_of_soc(); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + /* Enable PROCHOT */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 23); /* Lock it */ + wrmsr(MSR_POWER_CTL, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + uint32_t feature_flag; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + int ecx; + + /* Determine if energy efficient policy is supported. */ + ecx = cpuid_ecx(0x6); + if (!(ecx & (1 << 3))) + return; + + /* Energy Policy is bits 3:0 */ + msr = rdmsr(IA32_ENERGY_PERF_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + wrmsr(IA32_ENERGY_PERF_BIAS, msr); +} + +static void configure_c_states(void) +{ + msr_t msr; + + /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); + + /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); + + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | + C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | + C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | + C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); +} + +/* All CPUs including BSP will run the following function. */ +void soc_core_init(struct device *cpu) +{ + /* Clear out pending MCEs */ + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_configure(); + + /* Enable the local CPU apics */ + enable_lapic_tpr(); + setup_lapic(); + + /* Configure c-state interrupt response time */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Configure Intel Speed Shift */ + configure_isst(); + + /* Enable PM timer emulation */ + enable_pm_timer_emulation(); + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Enable Turbo */ + enable_turbo(); +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + cpu_set_max_ratio(); + + /* + * Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ + smm_southbridge_enable(PWRBTN_EN | GBL_EN); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +static const struct mp_ops mp_ops = { + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = soc_fsp_load, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void soc_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c new file mode 100644 index 0000000000..903259497d --- /dev/null +++ b/src/soc/intel/jasperlake/elog.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* SMBUS Wake */ + if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* Thermal Trip */ + if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) + elog_add_event(ELOG_TYPE_THERM_TRIP); + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon_a & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon_a & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco2_sts & TCO_STS_SECOND_TO) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* RTC reset */ + if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* Host Reset Status */ + if (ps->gen_pmcon_a & HOST_RST_STS) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > ACPI_S0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); + +void elog_gsmi_cb_platform_log_wake_source(void) +{ + struct chipset_power_state ps; + pmc_fill_pm_reg_info(&ps); + pch_log_wake_source(&ps); +} diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c new file mode 100644 index 0000000000..da36ea6304 --- /dev/null +++ b/src/soc/intel/jasperlake/espi.c @@ -0,0 +1,247 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* +* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve +* certain memory range as reserved range for BIOS usage. +* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" +*/ +static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { + { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { 0, 0 } +}; + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +{ + return tgl_lpc_fixed_mmio_ranges; +} + +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + +uint8_t get_pch_series(void) +{ + uint16_t lpc_did_hi_byte; + + /* + * Fetch upper 8 bits on ESPI device ID to determine PCH type + * Adding 1 to the offset to fetch upper 8 bits + */ + lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); + + if (lpc_did_hi_byte == 0xA0) + return PCH_TGP; + else if (lpc_did_hi_byte == 0x4d) + return PCH_JSP; + else + return PCH_UNKNOWN_SERIES; +} + +#if ENV_RAMSTAGE +static void soc_mirror_dmi_pcr_io_dec(void) +{ + struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); + uint32_t io_dec_arr[] = { + pci_read_config32(dev, ESPI_GEN1_DEC), + pci_read_config32(dev, ESPI_GEN2_DEC), + pci_read_config32(dev, ESPI_GEN3_DEC), + pci_read_config32(dev, ESPI_GEN4_DEC), + }; + /* Mirror these same settings in DMI PCR */ + soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); +} + +static void pch_enable_ioapic(const struct device *dev) +{ + u32 reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + +void soc_pch_pirq_init(const struct device *dev) +{ + struct device *irq_dev; + uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; + + pch_interrupt_routing[0] = PCH_IRQ11; + pch_interrupt_routing[1] = PCH_IRQ10; + pch_interrupt_routing[2] = PCH_IRQ11; + pch_interrupt_routing[3] = PCH_IRQ11; + pch_interrupt_routing[4] = PCH_IRQ11; + pch_interrupt_routing[5] = PCH_IRQ11; + pch_interrupt_routing[6] = PCH_IRQ11; + pch_interrupt_routing[7] = PCH_IRQ11; + + itss_irq_init(pch_interrupt_routing); + + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin = 0, int_line = 0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ + int_line = PCH_IRQ11; + break; + case 2: /* INTB# */ + int_line = PCH_IRQ10; + break; + case 3: /* INTC# */ + int_line = PCH_IRQ11; + break; + case 4: /* INTD# */ + int_line = PCH_IRQ11; + break; + } + + if (!int_line) + continue; + + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } +} + +static void pch_misc_init(void) +{ + uint8_t reg8; + + /* Setup NMI on errors, disable SERR */ + reg8 = (inb(0x61)) & 0xf0; + outb((reg8 | (1 << 2)), 0x61); + + /* Disable NMI sources */ + outb((1 << 7), 0x70); +}; + +void lpc_soc_init(struct device *dev) +{ + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + /* Enable CLKRUN_EN for power gating ESPI */ + lpc_enable_pci_clk_cntl(); + + /* Set ESPI Serial IRQ mode */ + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + lpc_set_serirq_mode(SERIRQ_CONTINUOUS); + else + lpc_set_serirq_mode(SERIRQ_QUIET); + + /* Interrupt configuration */ + pch_enable_ioapic(dev); + soc_pch_pirq_init(dev); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); + soc_mirror_dmi_pcr_io_dec(); +} + +/* Fill up ESPI IO resource structure inside SoC directory */ +void pch_lpc_soc_fill_io_resources(struct device *dev) +{ + /* + * PMC pci device gets hidden from PCI bus due to Silicon + * policy hence bind ACPI BASE aka ABASE (offset 0x20) with + * ESPI IO resources to ensure that ABASE falls under PCI reserved + * IO memory range. + * + * Note: Don't add any more resource with same offset 0x20 + * under this device space. + */ + pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, + ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED); +} + +#endif diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c new file mode 100644 index 0000000000..b636ccbec0 --- /dev/null +++ b/src/soc/intel/jasperlake/finalize.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4, 29 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ +#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ +#define CAM_CLK_EN (1 << 1) +#define MIPI_CLK (1 << 0) +#define HDPLL_CLK (0 << 0) + +static void pch_enable_isclk(void) +{ + pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); + pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); +} + +static void pch_handle_sideband(config_t *config) +{ + if (config->pch_isclk) + pch_enable_isclk(); +} + +static void pch_finalize(void) +{ + uint32_t reg32; + uint8_t *pmcbase; + config_t *config; + uint8_t reg8; + + /* TCO Lock down */ + tco_lockdown(); + + /* TODO: Add Thermal Configuration */ + + /* + * Disable ACPI PM timer based on dt policy + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + * + * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is + * just required to get to chip config. PCH_DEV_PMC is hidden by this + * point and hence removed from the root bus. pcidev_path_on_root thus + * returns NULL for PCH_DEV_PMC device. + */ + config = config_of_soc(); + pmcbase = pmc_mmio_regs(); + if (config->PmTimerDisabled) { + reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); + reg8 |= (1 << 1); + write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); + } + + /* Disable XTAL shutdown qualification for low power idle. */ + if (config->s0ix_enable) { + reg32 = read32(pmcbase + CPPMVRIC); + reg32 |= XTALSDQDIS; + write32(pmcbase + CPPMVRIC, reg32); + } + + pch_handle_sideband(config); + + pmc_clear_pmcon_sts(); +} + +static void soc_finalize(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); + + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + outb(APM_CNT_FINALIZE, APM_CNT); + + /* Indicate finalize step with post code */ + post_code(POST_OS_BOOT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); diff --git a/src/soc/intel/jasperlake/fsp_params_jsl.c b/src/soc/intel/jasperlake/fsp_params_jsl.c new file mode 100644 index 0000000000..932bd06ff7 --- /dev/null +++ b/src/soc/intel/jasperlake/fsp_params_jsl.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_tigerlake_config *config = config_of_soc(); + + /* LPSS controllers configuration */ + + /* I2C */ + _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= + ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); + memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, + sizeof(config->SerialIoI2cMode)); + + /* GSPI */ + _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >= + ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, + sizeof(config->SerialIoGSpiMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >= + ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode, + sizeof(config->SerialIoGSpiCsMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >= + ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState, + sizeof(config->SerialIoGSpiCsState)); + + /* UART */ + _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >= + ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!"); + memcpy(params->SerialIoUartMode, config->SerialIoUartMode, + sizeof(config->SerialIoUartMode)); +} + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + unsigned int i; + struct device *dev; + FSP_S_CONFIG *params = &supd->FspsConfig; + struct soc_intel_tigerlake_config *config = config_of_soc(); + + /* Parse device tree and fill in FSP UPDs */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Check if IGD is present and fill Graphics init param accordingly */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + + /* Unlock upper 8 bytes of RTC RAM */ + params->RtcMemoryLock = 0; + + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + + /* disable Legacy PME */ + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + /* USB configuration */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* SDCard related configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (!dev) + params->ScsSdCardEnabled = 0; + else + params->ScsSdCardEnabled = dev->enabled; + + params->Device4Enable = config->Device4Enable; + + /* eMMC configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + if (!dev) { + params->ScsEmmcEnabled = 0; + } else { + params->ScsEmmcEnabled = dev->enabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } + + /* Provide correct UART number for FSP debug logs */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + + /* Override/Fill FSP Silicon Param for mainboard */ + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/jasperlake/fsp_params_tgl.c b/src/soc/intel/jasperlake/fsp_params_tgl.c new file mode 100644 index 0000000000..a8be407d23 --- /dev/null +++ b/src/soc/intel/jasperlake/fsp_params_tgl.c @@ -0,0 +1,212 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Chip config parameter PcieRpL1Substates uses (UPD value + 1) + * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. + * In order to ensure that mainboard setting does not disable L1 substates + * incorrectly, chip config parameter values are offset by 1 with 0 meaning + * use FSP UPD default. get_l1_substate_control() ensures that the right UPD + * value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable L1 substates + * 2: Use L1.1 + * 3: Use L1.2 (FSP UPD default) + */ +static int get_l1_substate_control(enum L1_substates_control ctl) +{ + if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + ctl = L1_SS_L1_2; + return ctl - 1; +} + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_tigerlake_config *config; + config = config_of_soc(); + + for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + + for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { + params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; + params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; + params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; + } + + for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) + params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; +} + +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_GSPI3, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + int i; + FSP_S_CONFIG *params = &supd->FspsConfig; + + struct device *dev; + struct soc_intel_tigerlake_config *config; + config = config_of_soc(); + + /* Parse device tree and enable/disable Serial I/O devices */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + + for (i = 0; i < 8; i++) + params->IomTypeCPortPadCfg[i] = 0x09000000; + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* RP Configs */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + params->PcieRpL1Substates[i] = + get_l1_substate_control(config->PcieRpL1Substates[i]); + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } + + /* PCH UART selection for FSP Debug */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); + params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; + + /* SATA */ + dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + if (!dev) + params->SataEnable = 0; + else { + params->SataEnable = dev->enabled; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + } + + /* LAN */ + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; + + /* CNVi */ + dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); + if (dev) + params->CnviMode = dev->enabled; + else + params->CnviMode = 0; + + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + + /* Enable Hybrid storage auto detection */ + params->HybridStorageMode = config->HybridStorageMode; + + /* USB4/TBT */ + for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { + dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); + if (dev) + params->ITbtPcieRootPortEn[i] = dev->enabled; + else + params->ITbtPcieRootPortEn[i] = 0; + } + + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/jasperlake/gpio_jsl.c b/src/soc/intel/jasperlake/gpio_jsl.c new file mode 100644 index 0000000000..afb9f7b3bc --- /dev/null +++ b/src/soc/intel/jasperlake/gpio_jsl.c @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; + +static const struct reset_mapping rst_map_com0[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO driver for Jasperlake on Windows/Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for JSP at: + * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c + */ +static const struct pad_group jsl_community0_groups[] = { + + INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */ + INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8), + INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ + INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10), + INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ + INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ +}; + +static const struct pad_group jsl_community1_groups[] = { + INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ + INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */ + INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), + INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ + INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group jsl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */ + INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17), +}; + + +static const struct pad_group jsl_community4_groups[] = { + INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23), + INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */ + INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36), +}; + + +static const struct pad_group jsl_community5_groups[] = { + INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */ +}; + +static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { + /* GPP F, B, A, S, R */ + [COMM_0] = { + .port = PID_GPIOCOM0, + .first_pad = GPP_F0, + .last_pad = GPP_R7, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FBASR", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_com0, + .num_reset_vals = ARRAY_SIZE(rst_map_com0), + .groups = jsl_community0_groups, + .num_groups = ARRAY_SIZE(jsl_community0_groups), + }, + /* GPP H, D, VGPIO, C */ + [COMM_1] = { + .port = PID_GPIOCOM1, + .first_pad = GPP_H0, + .last_pad = GPP_C23, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_HDC", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community1_groups, + .num_groups = ARRAY_SIZE(jsl_community1_groups), + }, + /* GPD */ + [COMM_2] = { + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPIO_RSVD_17, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community2_groups, + .num_groups = ARRAY_SIZE(jsl_community2_groups), + }, + /* GPP E */ + [COMM_4] = { + .port = PID_GPIOCOM4, + .first_pad = GPIO_RSVD_18, + .last_pad = GPIO_RSVD_36, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_E", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community4_groups, + .num_groups = ARRAY_SIZE(jsl_community4_groups), + }, + /* GPP G */ + [COMM_5] = { + .port = PID_GPIOCOM5, + .first_pad = GPP_G0, + .last_pad = GPP_G7, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_G", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community5_groups, + .num_groups = ARRAY_SIZE(jsl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(jsl_communities); + return jsl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_A, GPP_A }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPD, GPP_GPD }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_F, GPP_F } + }; + + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/jasperlake/gpio_tgl.c b/src/soc/intel/jasperlake/gpio_tgl.c new file mode 100644 index 0000000000..cfdd0ac465 --- /dev/null +++ b/src/soc/intel/jasperlake/gpio_tgl.c @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 27 + */ + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_com2[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * This layout matches the Linux kernel pinctrl map for TGL-LP at: + * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c + */ +static const struct pad_group tgl_community0_groups[] = { + INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */ + INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */ + INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */ +}; + +static const struct pad_group tgl_community1_groups[] = { + INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */ + INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */ + INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */ + INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */ + INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group tgl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +}; + +static const struct pad_group tgl_community4_groups[] = { + INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ + INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ + INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */ + INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */ +}; + +static const struct pad_group tgl_community5_groups[] = { + INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ +}; + +static const struct pad_community tgl_communities[] = { + [COMM_0] = { /* GPP B, T, A */ + .port = PID_GPIOCOM0, + .first_pad = GPP_B0, + .last_pad = GPP_A24, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BTA", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community0_groups, + .num_groups = ARRAY_SIZE(tgl_community0_groups), + }, + [COMM_1] = { /* GPP S, D, H, U, VGPIO */ + .port = PID_GPIOCOM1, + .first_pad = GPP_S0, + .last_pad = vI2S2_RXD, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SDHU", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community1_groups, + .num_groups = ARRAY_SIZE(tgl_community1_groups), + }, + [COMM_2] = { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPD_DRAM_RESETB, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_com2, + .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .groups = tgl_community2_groups, + .num_groups = ARRAY_SIZE(tgl_community2_groups), + }, + [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */ + .port = PID_GPIOCOM4, + .first_pad = GPP_C0, + .last_pad = GPP_DBG_PMODE, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FCE", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community4_groups, + .num_groups = ARRAY_SIZE(tgl_community4_groups), + }, + [COMM_5] = { /* GPP R, SPI */ + .port = PID_GPIOCOM5, + .first_pad = GPP_R0, + .last_pad = GPP_CLK_LOOPBK, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CPU_VBPIO", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community5_groups, + .num_groups = ARRAY_SIZE(tgl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(tgl_communities); + return tgl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_B, GPP_B }, + { PMC_GPP_T, GPP_T }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_R, GPP_R }, + { PMC_GPD, GPD }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_U, GPP_U }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c new file mode 100644 index 0000000000..fef17e17e8 --- /dev/null +++ b/src/soc/intel/jasperlake/graphics.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 4 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uintptr_t fsp_soc_get_igd_bar(void) +{ + return graphics_get_memory_base(); +} + +void graphics_soc_init(struct device *dev) +{ + uint32_t ddi_buf_ctl; + + /* Skip IGD GT programming */ + if (CONFIG(SKIP_GRAPHICS_ENABLING)) + return; + + /* + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. + * This will allow the kernel to use 4-lane eDP links properly + * if the VBIOS or GOP driver do not execute. + */ + ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { + ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | + DDI_BUF_IS_IDLE); + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); + } + + /* + * GFX PEIM module inside FSP binary is taking care of graphics + * initialization based on RUN_FSP_GOP Kconfig + * option and input VBT file. Hence no need to load/execute legacy VGA + * OpROM in order to initialize GFX. + * + * In case of non-FSP solution, SoC need to select VGA_ROM_RUN + * Kconfig to perform GFX initialization through VGA OpRom. + */ + if (CONFIG(RUN_FSP_GOP)) + return; + + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); +} + +uintptr_t graphics_soc_write_acpi_opregion(struct device *device, + uintptr_t current, struct acpi_rsdp *rsdp) +{ + igd_opregion_t *opregion; + + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + + if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) + return current; + + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); +} diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c new file mode 100644 index 0000000000..1381fb2499 --- /dev/null +++ b/src/soc/intel/jasperlake/gspi.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 11 + */ + +#include +#include + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + switch (gspi_bus) { + case 0: + return PCH_DEVFN_GSPI0; + case 1: + return PCH_DEVFN_GSPI1; + case 2: + return PCH_DEVFN_GSPI2; + } + return -1; +} diff --git a/src/soc/intel/jasperlake/i2c.c b/src/soc/intel/jasperlake/i2c.c new file mode 100644 index 0000000000..46bc726726 --- /dev/null +++ b/src/soc/intel/jasperlake/i2c.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 13 + */ + +#include +#include +#include + +int dw_i2c_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: + return 0; + case PCH_DEVFN_I2C1: + return 1; + case PCH_DEVFN_I2C2: + return 2; + case PCH_DEVFN_I2C3: + return 3; + case PCH_DEVFN_I2C4: + return 4; + case PCH_DEVFN_I2C5: + return 5; + } + return -1; +} + +int dw_i2c_soc_bus_to_devfn(unsigned int bus) +{ + switch (bus) { + case 0: + return PCH_DEVFN_I2C0; + case 1: + return PCH_DEVFN_I2C1; + case 2: + return PCH_DEVFN_I2C2; + case 3: + return PCH_DEVFN_I2C3; + case 4: + return PCH_DEVFN_I2C4; + case 5: + return PCH_DEVFN_I2C5; + } + return -1; +} diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h new file mode 100644 index 0000000000..0c8d8c201a --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/bootblock.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_BOOTBLOCK_H_ +#define _SOC_TIGERLAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h new file mode 100644 index 0000000000..799382498b --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_CPU_H_ +#define _SOC_TIGERLAKE_CPU_H_ + +#include + +/* Latency times in units of 32768ns */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d + +/* Power in units of mW */ +#define C1_POWER 0x3e8 +#define C6_POWER 0x15e +#define C7_POWER 0xc8 +#define C8_POWER 0xc8 +#define C9_POWER 0xc8 +#define C10_POWER 0xc8 + +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/espi.h b/src/soc/intel/jasperlake/include/soc/espi.h new file mode 100644 index 0000000000..3f7e32a717 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/espi.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 2 + */ + +#ifndef _SOC_TIGERLAKE_ESPI_H_ +#define _SOC_TIGERLAKE_ESPI_H_ + +#include + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +/* + * This function will help to differentiate between 2 PCH on single type of soc. + * Since same soc may have LP series pch or H series PCH, we need to + * differentiate by reading upper 8 bits of PCH device ids. + * + * Return: + * Return PCH_LP or PCH_H macro in case of respective device ID found. + * PCH_UNKNOWN_SERIES in case of invalid device ID. + */ +uint8_t get_pch_series(void); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpe.h b/src/soc/intel/jasperlake/include/soc/gpe.h new file mode 100644 index 0000000000..c37750b1c4 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpe.h @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#define GPE_MAX GPE0_WADT +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h new file mode 100644 index 0000000000..fb3f42fd67 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_H_ +#define _SOC_TIGERLAKE_GPIO_H_ + +#include +#include + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + + #define CROS_GPIO_NAME "INT34C5" + #define CROS_GPIO_COMM0_NAME "INT34C5:00" + #define CROS_GPIO_COMM1_NAME "INT34C5:01" + #define CROS_GPIO_COMM4_NAME "INT34C5:02" + #define CROS_GPIO_COMM5_NAME "INT34C5:03" + +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + + #define CROS_GPIO_NAME "INT34C8" + #define CROS_GPIO_COMM0_NAME "INT34C8:00" + #define CROS_GPIO_COMM1_NAME "INT34C8:01" + #define CROS_GPIO_COMM4_NAME "INT34C8:02" + #define CROS_GPIO_COMM5_NAME "INT34C8:03" +#endif + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h new file mode 100644 index 0000000000..2898c12ee0 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_H_ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + #include +#endif +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h new file mode 100644 index 0000000000..69ed539cae --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h @@ -0,0 +1,272 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_ +#define _SOC_JASPERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include +#endif +#include + + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group F */ +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + +/* Group B */ +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + +/* Group D */ +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b +#define GPP_D20_IRQ 0x3c +#define GPP_D21_IRQ 0x3d +#define GPP_D22_IRQ 0x3e +#define GPP_D23_IRQ 0x3f + +/* Group GPD */ +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group R*/ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1a0 +#define PAD_CFG_BASE 0x600 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h new file mode 100644 index 0000000000..35a15ded66 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ + +#ifndef __ACPI__ +#include +#endif +#include + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + + +/* Group D */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + + +/* Group U */ +#define GPP_U0_IRQ 0x40 +#define GPP_U1IRQ 0x41 +#define GPP_U2_IRQ 0x42 +#define GPP_U3_IRQ 0x43 +#define GPP_U4_IRQ 0x44 +#define GPP_U5_IRQ 0x45 +#define GPP_U6_IRQ 0x46 +#define GPP_U7_IRQ 0x47 +#define GPP_U8_IRQ 0x48 +#define GPP_U9_IRQ 0x49 +#define GPP_U10_IRQ 0x4A +#define GPP_U11_IRQ 0x4B +#define GPP_U12_IRQ 0x4C +#define GPP_U13_IRQ 0x4D +#define GPP_U14_IRQ 0x4E +#define GPP_U15_IRQ 0x4F +#define GPP_U16_IRQ 0x50 +#define GPP_U17_IRQ 0x51 +#define GPP_U18_IRQ 0x52 +#define GPP_U19_IRQ 0x53 + + +#define GPP_VGPIO4_IRQ 0x54 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + + + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000000..b3ab9c3b5b --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include "gpio_soc_defs_tgl.h" +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + #include "gpio_soc_defs_jsl.h" +#endif + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h new file mode 100644 index 0000000000..2ee52b260f --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ +#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ + +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_G 0x2 +#define GPP_C 0x3 +#define GPP_R 0x4 +#define GPP_D 0x5 +#define GPP_S 0x6 +#define GPP_H 0x7 +#define GPP_VGPIO 0x8 +#define GPP_F 0x9 +#define GPP_GPD 0xA +#define GPP_E 0xD + +#define GPIO_NUM_GROUPS 12 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group F */ +#define GPP_F0 0 +#define GPP_F1 1 +#define GPP_F2 2 +#define GPP_F3 3 +#define GPP_F4 4 +#define GPP_F5 5 +#define GPP_F6 6 +#define GPP_F7 7 +#define GPP_F8 8 +#define GPP_F9 9 +#define GPP_F10 10 +#define GPP_F11 11 +#define GPP_F12 12 +#define GPP_F13 13 +#define GPP_F14 14 +#define GPP_F15 15 +#define GPP_F16 16 +#define GPP_F17 17 +#define GPP_F18 18 +#define GPP_F19 19 + +/* Group B */ +#define GPIO_RSVD_0 20 +#define GPIO_RSVD_1 21 +#define GPIO_RSVD_2 22 +#define GPIO_RSVD_3 23 +#define GPIO_RSVD_4 24 +#define GPIO_RSVD_5 25 +#define GPIO_RSVD_6 26 +#define GPIO_RSVD_7 27 +#define GPIO_RSVD_8 28 +#define GPP_B0 29 +#define GPP_B1 30 +#define GPP_B2 31 +#define GPP_B3 32 +#define GPP_B4 33 +#define GPP_B5 34 +#define GPP_B6 35 +#define GPP_B7 36 +#define GPP_B8 37 +#define GPP_B9 38 +#define GPP_B10 39 +#define GPP_B11 40 +#define GPP_B12 41 +#define GPP_B13 42 +#define GPP_B14 43 +#define GPP_B15 44 +#define GPP_B16 45 +#define GPP_B17 46 +#define GPP_B18 47 +#define GPP_B19 48 +#define GPP_B20 49 +#define GPP_B21 50 +#define GPP_B22 51 +#define GPP_B23 52 +#define GPIO_RSVD_9 53 +#define GPIO_RSVD_10 54 + +/* Group A */ +#define GPP_A0 55 +#define GPP_A1 56 +#define GPP_A2 57 +#define GPP_A3 58 +#define GPP_A4 59 +#define GPP_A5 60 +#define GPP_A6 61 +#define GPP_A7 62 +#define GPP_A8 63 +#define GPP_A9 64 +#define GPP_A10 65 +#define GPP_A11 66 +#define GPP_A12 67 +#define GPP_A13 68 +#define GPP_A14 69 +#define GPP_A15 70 +#define GPP_A16 71 +#define GPP_A17 72 +#define GPP_A18 73 +#define GPP_A19 74 +#define GPIO_RSVD_11 75 + +/* Group S */ +#define GPP_S0 76 +#define GPP_S1 77 +#define GPP_S2 78 +#define GPP_S3 79 +#define GPP_S4 80 +#define GPP_S5 81 +#define GPP_S6 82 +#define GPP_S7 83 + +/* Group R */ +#define GPP_R0 84 +#define GPP_R1 85 +#define GPP_R2 86 +#define GPP_R3 87 +#define GPP_R4 88 +#define GPP_R5 89 +#define GPP_R6 90 +#define GPP_R7 91 + +#define GPIO_COM0_START GPP_F0 +#define GPIO_COM0_END GPP_R7 +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group H */ +#define GPP_H0 92 +#define GPP_H1 93 +#define GPP_H2 94 +#define GPP_H3 95 +#define GPP_H4 96 +#define GPP_H5 97 +#define GPP_H6 98 +#define GPP_H7 99 +#define GPP_H8 100 +#define GPP_H9 101 +#define GPP_H10 102 +#define GPP_H11 103 +#define GPP_H12 104 +#define GPP_H13 105 +#define GPP_H14 106 +#define GPP_H15 107 +#define GPP_H16 108 +#define GPP_H17 109 +#define GPP_H18 110 +#define GPP_H19 111 +#define GPP_H20 112 +#define GPP_H21 113 +#define GPP_H22 114 +#define GPP_H23 115 + +/* Group D */ +#define GPP_D0 116 +#define GPP_D1 117 +#define GPP_D2 118 +#define GPP_D3 119 +#define GPP_D4 120 +#define GPP_D5 121 +#define GPP_D6 122 +#define GPP_D7 123 +#define GPP_D8 124 +#define GPP_D9 125 +#define GPP_D10 126 +#define GPP_D11 127 +#define GPP_D12 128 +#define GPP_D13 129 +#define GPP_D14 130 +#define GPP_D15 131 +#define GPP_D16 132 +#define GPP_D17 133 +#define GPP_D18 134 +#define GPP_D19 135 +#define GPP_D20 136 +#define GPP_D21 137 +#define GPP_D22 138 +#define GPP_D23 139 +#define GPIO_RSVD_12 140 +#define GPIO_RSVD_13 141 + +/* Group VGPIO */ +#define VGPIO_0 142 +#define VGPIO_3 143 +#define VGPIO_4 144 +#define VGPIO_5 145 +#define VGPIO_6 146 +#define VGPIO_7 147 +#define VGPIO_8 148 +#define VGPIO_9 149 +#define VGPIO_10 150 +#define VGPIO_11 151 +#define VGPIO_12 152 +#define VGPIO_13 153 +#define VGPIO_18 154 +#define VGPIO_19 155 +#define VGPIO_20 156 +#define VGPIO_21 157 +#define VGPIO_22 158 +#define VGPIO_23 159 +#define VGPIO_24 160 +#define VGPIO_25 161 +#define VGPIO_30 162 +#define VGPIO_31 163 +#define VGPIO_32 164 +#define VGPIO_33 165 +#define VGPIO_34 166 +#define VGPIO_35 167 +#define VGPIO_36 168 +#define VGPIO_37 169 +#define VGPIO_39 170 + +/* Group C */ +#define GPP_C0 171 +#define GPP_C1 172 +#define GPP_C2 173 +#define GPP_C3 174 +#define GPP_C4 175 +#define GPP_C5 176 +#define GPP_C6 177 +#define GPP_C7 178 +#define GPP_C8 179 +#define GPP_C9 180 +#define GPP_C10 181 +#define GPP_C11 182 +#define GPP_C12 183 +#define GPP_C13 184 +#define GPP_C14 185 +#define GPP_C15 186 +#define GPP_C16 187 +#define GPP_C17 188 +#define GPP_C18 189 +#define GPP_C19 190 +#define GPP_C20 191 +#define GPP_C21 192 +#define GPP_C22 193 +#define GPP_C23 194 + +#define GPIO_COM1_START GPP_H0 +#define GPIO_COM1_END GPP_C23 +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 195 +#define GPD1 196 +#define GPD2 197 +#define GPD3 198 +#define GPD4 199 +#define GPD5 200 +#define GPD6 201 +#define GPD7 202 +#define GPD8 203 +#define GPD9 204 +#define GPD10 205 +#define GPIO_RSVD_14 206 +#define GPIO_RSVD_15 207 +#define GPIO_RSVD_16 208 +#define GPIO_RSVD_17 209 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPIO_RSVD_17 +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group E */ +#define GPIO_RSVD_18 210 +#define GPIO_RSVD_19 211 +#define GPIO_RSVD_20 212 +#define GPIO_RSVD_21 213 +#define GPIO_RSVD_22 214 +#define GPIO_RSVD_23 215 +#define GPP_E0 216 +#define GPP_E1 217 +#define GPP_E2 218 +#define GPP_E3 219 +#define GPP_E4 220 +#define GPP_E5 221 +#define GPP_E6 222 +#define GPP_E7 223 +#define GPP_E8 224 +#define GPP_E9 225 +#define GPP_E10 226 +#define GPP_E11 227 +#define GPP_E12 228 +#define GPP_E13 229 +#define GPP_E14 230 +#define GPP_E15 231 +#define GPP_E16 232 +#define GPP_E17 233 +#define GPP_E18 234 +#define GPP_E19 235 +#define GPP_E20 236 +#define GPP_E21 237 +#define GPP_E22 238 +#define GPP_E23 239 +#define GPIO_RSVD_24 240 +#define GPIO_RSVD_25 241 +#define GPIO_RSVD_26 242 +#define GPIO_RSVD_27 243 +#define GPIO_RSVD_28 244 +#define GPIO_RSVD_29 245 +#define GPIO_RSVD_30 246 +#define GPIO_RSVD_31 247 +#define GPIO_RSVD_32 248 +#define GPIO_RSVD_33 249 +#define GPIO_RSVD_34 250 +#define GPIO_RSVD_35 251 +#define GPIO_RSVD_36 252 + +#define GPIO_COM4_START GPIO_RSVD_18 +#define GPIO_COM4_END GPIO_RSVD_36 +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group G */ +#define GPP_G0 253 +#define GPP_G1 254 +#define GPP_G2 255 +#define GPP_G3 256 +#define GPP_G4 257 +#define GPP_G5 258 +#define GPP_G6 259 +#define GPP_G7 260 + +#define GPIO_COM5_START GPP_G0 +#define GPIO_COM5_END GPP_G7 +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_PADS 261 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_4 3 +#define COMM_5 4 +#define TOTAL_GPIO_COMM 5 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h new file mode 100644 index 0000000000..ec582c3133 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h @@ -0,0 +1,394 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 +#define GPP_S 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_U 0x8 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC + +#define GPIO_MAX_NUM_PER_GROUP 27 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_A24 +#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +/* Group U */ +#define GPP_U0 120 +#define GPP_U1 121 +#define GPP_U2 122 +#define GPP_U3 123 +#define GPP_U4 124 +#define GPP_U5 125 +#define GPP_U6 126 +#define GPP_U7 127 +#define GPP_U8 128 +#define GPP_U9 129 +#define GPP_U10 130 +#define GPP_U11 131 +#define GPP_U12 132 +#define GPP_U13 133 +#define GPP_U14 134 +#define GPP_U15 135 +#define GPP_U16 136 +#define GPP_U17 137 +#define GPP_U18 138 +#define GPP_U19 139 +#define GPP_GSPI3_CLK_LOOPBK 140 +#define GPP_GSPI4_CLK_LOOPBK 141 +#define GPP_GSPI5_CLK_LOOPBK 142 +#define GPP_GSPI6_CLK_LOOPBK 143 + +/* Group VGPIO */ +#define CNV_BTEN 144 +#define CNV_BT_HOST_WAKEB 145 +#define CNV_BT_IF_SELECT 146 +#define vCNV_BT_UART_TXD 147 +#define vCNV_BT_UART_RXD 148 +#define vCNV_BT_UART_CTS_B 149 +#define vCNV_BT_UART_RTS_B 150 +#define vCNV_MFUART1_TXD 151 +#define vCNV_MFUART1_RXD 152 +#define vCNV_MFUART1_CTS_B 153 +#define vCNV_MFUART1_RTS_B 154 +#define vUART0_TXD 155 +#define vUART0_RXD 156 +#define vUART0_CTS_B 157 +#define vUART0_RTS_B 158 +#define vISH_UART0_TXD 159 +#define vISH_UART0_RXD 160 +#define vISH_UART0_CTS_B 161 +#define vISH_UART0_RTS_B 162 +#define vCNV_BT_I2S_BCLK 163 +#define vCNV_BT_I2S_WS_SYNC 164 +#define vCNV_BT_I2S_SDO 165 +#define vCNV_BT_I2S_SDI 166 +#define vI2S2_SCLK 167 +#define vI2S2_SFRM 168 +#define vI2S2_TXD 169 +#define vI2S2_RXD 170 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END vI2S2_RXD +#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) + +/* Group GPD */ +#define GPD0 171 +#define GPD1 172 +#define GPD2 173 +#define GPD3 174 +#define GPD4 175 +#define GPD5 176 +#define GPD6 177 +#define GPD7 178 +#define GPD8 179 +#define GPD9 180 +#define GPD10 181 +#define GPD11 182 +#define GPD_INPUT3VSEL 183 +#define GPD_SLP_LANB 184 +#define GPD__SLP_SUSB 185 +#define GPD_WAKEB 186 +#define GPD_DRAM_RESETB 187 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) + +/* Group C */ +#define GPP_C0 188 +#define GPP_C1 189 +#define GPP_C2 190 +#define GPP_C3 191 +#define GPP_C4 192 +#define GPP_C5 193 +#define GPP_C6 194 +#define GPP_C7 195 +#define GPP_C8 196 +#define GPP_C9 197 +#define GPP_C10 198 +#define GPP_C11 199 +#define GPP_C12 200 +#define GPP_C13 201 +#define GPP_C14 202 +#define GPP_C15 203 +#define GPP_C16 204 +#define GPP_C17 205 +#define GPP_C18 206 +#define GPP_C19 207 +#define GPP_C20 208 +#define GPP_C21 209 +#define GPP_C22 210 +#define GPP_C23 211 + +/* Group F */ +#define GPP_F0 212 +#define GPP_F1 213 +#define GPP_F2 214 +#define GPP_F3 215 +#define GPP_F4 216 +#define GPP_F5 217 +#define GPP_F6 218 +#define GPP_F7 219 +#define GPP_F8 220 +#define GPP_F9 221 +#define GPP_F10 222 +#define GPP_F11 223 +#define GPP_F12 224 +#define GPP_F13 225 +#define GPP_F14 226 +#define GPP_F15 227 +#define GPP_F16 228 +#define GPP_F17 229 +#define GPP_F18 230 +#define GPP_F19 231 +#define GPP_F20 232 +#define GPP_F21 233 +#define GPP_F22 234 +#define GPP_F23 235 +#define GPP_F_CLK_LOOPBK 236 + +/* Group HVCMOS */ +#define GPP_L_BKLTEN 237 +#define GPP_L_BKLTCTL 238 +#define GPP_L_VDDEN 239 +#define GPP_SYS_PWROK 240 +#define GPP_SYS_RESETB 241 +#define GPP_MLK_RSTB 242 + +/* Group E */ +#define GPP_E0 243 +#define GPP_E1 244 +#define GPP_E2 245 +#define GPP_E3 246 +#define GPP_E4 247 +#define GPP_E5 248 +#define GPP_E6 249 +#define GPP_E7 250 +#define GPP_E8 251 +#define GPP_E9 252 +#define GPP_E10 253 +#define GPP_E11 254 +#define GPP_E12 255 +#define GPP_E13 256 +#define GPP_E14 257 +#define GPP_E15 258 +#define GPP_E16 259 +#define GPP_E17 260 +#define GPP_E18 261 +#define GPP_E19 262 +#define GPP_E20 263 +#define GPP_E21 264 +#define GPP_E22 265 +#define GPP_E23 266 +#define GPP_E_CLK_LOOPBK 267 + +/* Group JTAG */ +#define GPP_JTAG_TDO 268 +#define GPP_JTAG_X 269 +#define GPP_JTAG_PRDYB 270 +#define GPP_JTAG_PREQB 271 +#define GPP_CPU_TRSTB 272 +#define GPP_JTAG_TDI 273 +#define GPP_JTAG_TMS 274 +#define GPP_JTAG_TCK 275 +#define GPP_DBG_PMODE 276 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_DBG_PMODE +#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) + +/* Group R */ +#define GPP_R0 277 +#define GPP_R1 278 +#define GPP_R2 279 +#define GPP_R3 280 +#define GPP_R4 281 +#define GPP_R5 282 +#define GPP_R6 283 +#define GPP_R7 284 + +/* Group SPI */ +#define GPP_SPI_IO_2 285 +#define GPP_SPI_IO_3 286 +#define GPP_SPI_MOSI_IO_0 287 +#define GPP_SPI_MOSI_IO_1 288 +#define GPP_SPI_TPM_CSB 289 +#define GPP_SPI_FLASH_0_CSB 290 +#define GPP_SPI_FLASH_1_CSB 291 +#define GPP_SPI_CLK 292 +#define GPP_CLK_LOOPBK 293 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_CLK_LOOPBK +#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS 294 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h new file mode 100644 index 0000000000..5eda08a132 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Firmware Architecture Specification + * Document number: 608531 + * Chapter number: 4 + */ + +#ifndef _SOC_TIGERLAKE_IOMAP_H_ +#define _SOC_TIGERLAKE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 + +#define UART_BASE_SIZE 0x1000 + +#define UART_BASE_0_ADDRESS 0xfe03e000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define DMI_BASE_ADDRESS 0xfeda0000 +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xfed80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + +#define REG_BASE_ADDRESS 0xfb000000 +#define REG_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define SPI_BASE_ADDRESS 0xfe010000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +#define VTD_BASE_ADDRESS 0xfed90000 +#define VTD_BASE_SIZE 0x00004000 + +#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#else /* CONFIG_SOC_INTEL_JASPERLAKE_COPY */ + +#define MCH_BASE_ADDRESS 0xfea80000 +#define MCH_BASE_SIZE 0x8000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + +#endif + +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h new file mode 100644 index 0000000000..6ca2588a0d --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/irq.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include "irq_tgl.h" +#else + #include "irq_jsl.h" +#endif /* CONFIG_SOC_INTEL_TIGERLAKE_COPY */ + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/irq_jsl.h b/src/soc/intel/jasperlake/include/soc/irq_jsl.h new file mode 100644 index 0000000000..a6edd23d97 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/irq_jsl.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JSL_IRQ_H_ +#define _SOC_JSL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +/* LPSS Devices */ +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 + +/* PCI D:31 F:x */ +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +/* PCI D:28 F:x */ +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 + +/* PCI D:26 F:x */ +#define eMMC_IRQ 16 + +/* PCI D:23 F:x */ +#define SATA_IRQ 16 + +/* PCI D:22 F:x */ +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 +#define IDER_IRQ 18 +#define KT_IRQ 19 + +/* PCI D:20 F:x */ +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define CNViWIFI_IRQ 16 +#define SD_IRQ 19 +#define PMC_SRAM_IRQ 18 + +/* PCI D:18 F:x */ +#define UFS_IRQ 16 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 + +#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/irq_tgl.h b/src/soc/intel/jasperlake/include/soc/irq_tgl.h new file mode 100644 index 0000000000..6f268c1eae --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/irq_tgl.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TGL_IRQ_H_ +#define _SOC_TGL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 18 +#define LPSS_SPI3_IRQ 23 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 + +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 + +#define CNVI_BT_IRQ 18 + +#define THC0_IRQ 16 +#define THC1_IRQ 17 + +#define ISH_IRQ 16 + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 + +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif /* _TGL_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/itss.h b/src/soc/intel/jasperlake/include/soc/itss.h new file mode 100644 index 0000000000..39794ead73 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/itss.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_TGL_ITSS_H +#define SOC_INTEL_TGL_ITSS_H + +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) + +#endif /* SOC_INTEL_TGL_ITSS_H */ diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h new file mode 100644 index 0000000000..94331b4c9e --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/me.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _TIGERLAKE_ME_H_ +#define _TIGERLAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 spi_protection_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 invoke_enhance_dbg_mode: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; +#endif /* _TIGERLAKE_ME_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/meminit_jsl.h b/src/soc/intel/jasperlake/include/soc/meminit_jsl.h new file mode 100644 index 0000000000..421e31d8e4 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/meminit_jsl.h @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ +#define _SOC_JASPERLAKE_MEMCFG_INIT_H_ + +#include +#include + +/* Number of dq bits controlled per dqs */ +#define DQ_BITS_PER_DQS 8 + +/* Number of memory packages, where a "package" represents a 64-bit solution */ +#define DDR_NUM_PACKAGES 2 + +/* Number of DQ byte mappings */ +#define DDR_NUM_BYTE_MAPPINGS 6 + +/* Number of memory DIMM slots available on Jasper Lake */ +#define NUM_DIMM_SLOT 4 + +/* 64-bit Channel identification */ +enum { + DDR_CH0, + DDR_CH1, + DDR_NUM_CHANNELS +}; + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + READ_SPD_CBFS, /* Find SPD file in CBFS. */ + READ_SMBUS, /* Read on-module SPD by SMBUS. */ + READ_SPD_MEMPTR /* Find SPD data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To read on-module SPD when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address[NUM_DIMM_SLOT]; + + /* To identify SPD file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find SPD data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory dq mapping information */ +struct mb_cfg { + + /* + * For each channel, there are 6 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, even though the last 3 sets + * are not used in JSL. + * We let the meminit_dq_dqs_map routine take care of clearing the + * unused fields for the caller. + * Note that dq_map is only used by LPDDR; it does not need to be + * initialized for designs using DDR4. + */ + uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES]; + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + * dqs_map is only used by LPDDR; same comments apply as for dq_map + * above. + */ + uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + uint16_t rcomp_resistor[3]; + + /* + * Rcomp target values. These will typically be the following + * values for Jasper Lake : { 80, 40, 40, 40, 30 } + */ + uint16_t rcomp_targets[5]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; + + /* Board type */ + uint8_t UserBd; +}; + +/* + * Initialize default memory configurations for Jasper Lake. + */ + +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated); + +#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/meminit_tgl.h b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h new file mode 100644 index 0000000000..5573fb7110 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _SOC_MEMINIT_TGL_H_ +#define _SOC_MEMINIT_TGL_H_ + +#include +#include +#include + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 +#define NUM_CHANNELS 8 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this channel */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_lpddr4x_cfg { + /* DQ mapping */ + uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; +}; + +/* Initialize default memory configurations for dimm0-only lpddr4x */ +void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + const struct spd_info *spd, + bool half_populated); + +#endif /* _SOC_MEMINIT_TGL_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/msr.h b/src/soc/intel/jasperlake/include/soc/msr.h new file mode 100644 index 0000000000..7925ea76b0 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/msr.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include + +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/nvs.h b/src/soc/intel/jasperlake/include/soc/nvs.h new file mode 100644 index 0000000000..cfb189d381 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/nvs.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/p2sb.h b/src/soc/intel/jasperlake/include/soc/p2sb.h new file mode 100644 index 0000000000..d483ee399b --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/p2sb.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 3 + */ + +#ifndef _SOC_TIGERLAKE_P2SB_H_ +#define _SOC_TIGERLAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pch.h b/src/soc/intel/jasperlake/include/soc/pch.h new file mode 100644 index 0000000000..c2f497c1c8 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pch.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PCH_H_ +#define _SOC_TIGERLAKE_PCH_H_ + +#include + +#define PCH_TGP 1 +#define PCH_JSP 2 +#define PCH_UNKNOWN_SERIES 0xFF + +#define PCIE_CLK_NOTUSED 0xFF +#define PCIE_CLK_LAN 0x70 +#define PCIE_CLK_FREE 0x80 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h new file mode 100644 index 0000000000..e729864817 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PCI_DEVS_H_ +#define _SOC_TIGERLAKE_PCI_DEVS_H_ + +#include + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ + +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif + +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) + +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) + +#define SA_DEV_SLOT_TBT 0x07 +#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) +#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) +#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) +#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) +#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) +#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) +#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) +#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) + +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + +/* PCH Devices */ +#define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) + +#define PCH_DEV_SLOT_SIO1 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) +#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) + +#define PCH_DEV_SLOT_ISH 0x12 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO2 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) + +#define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) +#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) +#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) + +#if CONFIG(SOC_INTEL_JASPERLAKE_COPY) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) +#endif + +#define PCH_DEV_SLOT_SIO3 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) + +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) + +#define PCH_DEV_SLOT_SIO4 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) + +#if CONFIG(SOC_INTEL_JASPERLAKE_COPY) +#define PCH_DEV_SLOT_STORAGE 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#endif + +#define PCH_DEV_SLOT_PCIE 0x1c +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) + +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) + +#define PCH_DEV_SLOT_SIO5 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) + +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#endif + +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h new file mode 100644 index 0000000000..4143892f87 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 31-35 + */ + +#ifndef SOC_TIGERLAKE_PCR_H +#define SOC_TIGERLAKE_PCR_H +/* + * Port ids + */ +#define PID_EMMC 0x52 +#define PID_SDX 0x53 + +#define PID_GPIOCOM0 0x6e +#define PID_GPIOCOM1 0x6d +#define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM4 0x6a +#define PID_GPIOCOM5 0x69 + +#define PID_DMI 0x88 +#define PID_PSTH 0x89 +#define PID_CSME0 0x90 +#define PID_ISCLK 0xad +#define PID_PSF1 0xba +#define PID_PSF2 0xbb +#define PID_PSF3 0xbc +#define PID_PSF4 0xbd +#define PID_SCS 0xc0 +#define PID_RTC 0xc3 +#define PID_ITSS 0xc4 +#define PID_ESPI 0xc7 +#define PID_SERIALIO 0xcb + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h new file mode 100644 index 0000000000..14fa5d0c08 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include +#include +#include +#include +#include + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h new file mode 100644 index 0000000000..0ec1d36e44 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PMC_H_ +#define _SOC_TIGERLAKE_PMC_H_ + +/* PCI Configuration Space (D31:F2): PMC */ +#define PWRMBASE 0x10 +#define ABASE 0x20 + +/* Memory mapped IO registers in PMC */ +#define GEN_PMCON_A 0x1020 +#define DC_PP_DIS (1 << 30) +#define DSX_PP_DIS (1 << 29) +#define AG3_PP_EN (1 << 28) +#define SX_PP_EN (1 << 27) +#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) +#define GBL_RST_STS (1 << 24) +#define DISB (1 << 23) +#define ALLOW_OPI_PLL_SD_INC0 (1 << 22) +#define MEM_SR (1 << 21) +#define ALLOW_SPXB_CG_INC0 (1 << 20) +#define ALLOW_L1LOW_C0 (1 << 19) +#define MS4V (1 << 18) +#define ALLOW_L1LOW_OPI_ON (1 << 17) +#define SUS_PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define PWR_FLR (1 << 14) +#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) +#define HOST_RST_STS (1 << 9) +#define ESPI_SMI_LOCK (1 << 8) +#define S4MAW_MASK (3 << 4) +#define S4MAW_1S (1 << 4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE (1 << 3) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define GEN_PMCON_B 0x1024 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) +#define PM_DATA_BAR_DIS (1 << 16) +#define WOL_EN_OVRD (1 << 13) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) +#define RTC_BATTERY_DEAD (1 << 2) + +#define ETR 0x1048 +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define SSML 0x104C +#define SSML_SSL_DS (0 << 0) +#define SSML_SSL_EN (1 << 0) + +#define SSMC 0x1050 +#define SSMC_SSMS (1 << 0) + +#define SSMD 0x1054 +#define SSMD_SSD_MASK (0xffff << 0) + +#define PRSTS 0x1810 + +#define S3_PWRGATE_POL 0x1828 +#define S3DC_GATE_SUS (1 << 1) +#define S3AC_GATE_SUS (1 << 0) + +#define S4_PWRGATE_POL 0x182c +#define S4DC_GATE_SUS (1 << 1) +#define S4AC_GATE_SUS (1 << 0) + +#define S5_PWRGATE_POL 0x1830 +#define S5DC_GATE_SUS (1 << 15) +#define S5AC_GATE_SUS (1 << 14) + +#define DSX_CFG 0x1834 +#define REQ_CNV_NOWAKE_DSX (1 << 4) +#define REQ_BATLOW_DSX (1 << 3) +#define DSX_EN_WAKE_PIN (1 << 2) +#define DSX_DIS_AC_PRESENT_PD (1 << 1) +#define DSX_EN_LAN_WAKE_PIN (1 << 0) +#define DSX_CFG_MASK (0x1f << 0) + +#define PMSYNC_TPR_CFG 0x18C4 +#define PCH2CPU_TPR_CFG_LOCK (1 << 31) +#define PCH2CPU_TT_EN (1 << 26) + +#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + + #define PMC_GPP_B 0x0 + #define PMC_GPP_T 0x1 + #define PMC_GPP_A 0x2 + #define PMC_GPP_R 0x3 + #define PMC_GPD 0x4 + #define PMC_GPP_S 0x5 + #define PMC_GPP_H 0x6 + #define PMC_GPP_D 0x7 + #define PMC_GPP_U 0x8 + #define PMC_GPP_F 0xA + #define PMC_GPP_C 0xB + #define PMC_GPP_E 0xC + +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + + #define PMC_GPP_A 0x0 + #define PMC_GPP_B 0x1 + #define PMC_GPP_F 0x2 + #define PMC_GPD 0x3 + #define PMC_GPP_R 0x4 + #define PMC_GPP_S 0x6 + #define PMC_GPP_D 0x7 + #define PMC_GPP_C 0x8 + #define PMC_GPP_H 0xA + #define PMC_GPP_E 0xF + +#endif + +#define GBLRST_CAUSE0 0x1924 +#define GBLRST_CAUSE0_THERMTRIP (1 << 5) +#define GBLRST_CAUSE1 0x1928 + +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS (1 << 22) + +#define IRQ_REG ACTL +#define SCI_IRQ_ADJUST 0 +#define ACTL 0x1BD8 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) + +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#endif diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h new file mode 100644 index 0000000000..a8c8fdd7b2 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/ramstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void soc_init_pre_device(void *chip_info); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h new file mode 100644 index 0000000000..1672e8b5ca --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void pch_init(void); + +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/serialio.h b/src/soc/intel/jasperlake/include/soc/serialio.h new file mode 100644 index 0000000000..509f0b0f14 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/serialio.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; + +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2, + PchSerialIoIndexGSPI3, +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2, +}; + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h new file mode 100644 index 0000000000..3fb8291698 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/smbus.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 6 + */ + +#ifndef _SOC_TIGERLAKE_SMBUS_H_ +#define _SOC_TIGERLAKE_SMBUS_H_ + +/* IO and MMIO registers under primary BAR */ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/soc_chip.h b/src/soc/intel/jasperlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..250aa9a0aa --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/soc_chip.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_ +#define _SOC_TIGERLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h new file mode 100644 index 0000000000..d8c8ad47da --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H +#define SOC_TIGERLAKE_SYSTEMAGENT_H + +#include + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 +#define REGBAR 0x5420 +#define IPUVTBAR 0x7880 +#define TBT0BAR 0x7888 +#define TBT1BAR 0x7890 +#define TBT2BAR 0x7898 +#define TBT3BAR 0x78A0 +#define MAX_TBT_PCIE_PORT 4 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/usb.h b/src/soc/intel/jasperlake/include/soc/usb.h new file mode 100644 index 0000000000..33c0bf0bf9 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/usb.h @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_USB_H_ +#define _SOC_USB_H_ + +#include + +/* Per Port HS Transmitter Emphasis */ +#define USB2_EMP_OFF 0 +#define USB2_DE_EMP_ON 1 +#define USB2_PRE_EMP_ON 2 +#define USB2_DE_EMP_ON_PRE_EMP_ON 3 + +/* Per Port Half Bit Pre-emphasis */ +#define USB2_FULL_BIT_PRE_EMP 0 +#define USB2_HALF_BIT_PRE_EMP 1 + +/* Per Port HS Preemphasis Bias */ +#define USB2_BIAS_0MV 0 +#define USB2_BIAS_11P25MV 1 +#define USB2_BIAS_16P9MV 2 +#define USB2_BIAS_28P15MV 3 +#define USB2_BIAS_39P35MV 5 +#define USB2_BIAS_45MV 6 +#define USB2_BIAS_56P3MV 7 + +struct usb2_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_bias; + uint8_t tx_emp_enable; + uint8_t pre_emp_bias; + uint8_t pre_emp_bit; +}; + +/* USB Overcurrent pins definition */ +enum { + OC0 = 0, + OC1, + OC2, + OC3, + OC4, + OC5, + OC6, + OC7, + OCMAX, + OC_SKIP = 0xff, /* Skip OC programming */ +}; + +/* Standard USB Port based on length: + * - External + * - Back Panel + * - OTG + * - M.2 + * - Internal device down */ + +#define USB2_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_EMP_OFF, \ + .pre_emp_bias = USB2_BIAS_0MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 11.5"-12" */ +#define USB2_PORT_LONG(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 6"-11.49" */ +#define USB2_PORT_MID(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 3"-5.99" */ +#define USB2_PORT_SHORT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_39P35MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + +/* Max TX and Pre-emp settings */ +#define USB2_PORT_MAX(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_56P3MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Type-C Port, no BC1.2 charge detect module / MUX + * Length = 3.0" - 9.00" */ +#define USB2_PORT_TYPE_C(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +struct usb3_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_de_emp; + uint8_t tx_downscale_amp; +}; + +#define USB3_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_de_emp = 0x00, \ + .tx_downscale_amp = 0x00, \ +} + +#define USB3_PORT_DEFAULT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_de_emp = 0x0, \ + .tx_downscale_amp = 0x00, \ +} + +#endif diff --git a/src/soc/intel/jasperlake/lockdown.c b/src/soc/intel/jasperlake/lockdown.c new file mode 100644 index 0000000000..18d4fa728e --- /dev/null +++ b/src/soc/intel/jasperlake/lockdown.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + +#include +#include +#include +#include + +static void pmc_lock_pmsync(void) +{ + uint8_t *pmcbase; + uint32_t pmsyncreg; + + pmcbase = pmc_mmio_regs(); + + pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); + pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; + write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); +} + +static void pmc_lock_abase(void) +{ + uint8_t *pmcbase; + uint32_t reg32; + + pmcbase = pmc_mmio_regs(); + + reg32 = read32(pmcbase + GEN_PMCON_B); + reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + write32(pmcbase + GEN_PMCON_B, reg32); +} + +static void pmc_lock_smi(void) +{ + uint8_t *pmcbase; + uint8_t reg8; + + pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_B); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_B, reg8); +} + +static void pmc_lockdown_cfg(int chipset_lockdown) +{ + /* PMSYNC */ + pmc_lock_pmsync(); + /* Lock down ABASE and sleep stretching policy */ + pmc_lock_abase(); + + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pmc_lock_smi(); +} + +void soc_lockdown_config(int chipset_lockdown) +{ + /* PMC lock down configuration */ + pmc_lockdown_cfg(chipset_lockdown); +} diff --git a/src/soc/intel/jasperlake/meminit_jsl.c b/src/soc/intel/jasperlake/meminit_jsl.c new file mode 100644 index 0000000000..c68d2100fc --- /dev/null +++ b/src/soc/intel/jasperlake/meminit_jsl.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static void spd_read_from_cbfs(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, + size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd_info->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, + size_t *spd_data_len) +{ + if (spd_info->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd_info->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + bool half_populated) +{ + memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, + sizeof(mem_cfg->RcompResistor)); + + memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, + sizeof(mem_cfg->RcompTarget)); + + memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], + sizeof(board_cfg->dq_map[DDR_CH0])); + + memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], + sizeof(board_cfg->dqs_map[DDR_CH0])); + + if (half_populated) + return; + + memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], + sizeof(board_cfg->dq_map[DDR_CH1])); + + memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], + sizeof(board_cfg->dqs_map[DDR_CH1])); +} + +static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + uintptr_t spd_data_ptr, bool half_populated) +{ + /* Channel 0 */ + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + mem_cfg->MemorySpdPtr01 = 0; + + if (half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + spd_data_ptr = 0; + } + + /* Channel 1 */ + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + mem_cfg->MemorySpdPtr11 = 0; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated) +{ + + if (spd_info->read_type == READ_SMBUS) { + for (int i = 0; i < NUM_DIMM_SLOT; i++) + mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); + } else { + uintptr_t spd_data_ptr = 0; + size_t spd_data_len = 0; + memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); + get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + } + + /* Early Command Training Enabled */ + mem_cfg->ECT = board_cfg->ect; + + mem_cfg->UserBd = board_cfg->UserBd; +} diff --git a/src/soc/intel/jasperlake/meminit_tgl.c b/src/soc/intel/jasperlake/meminit_tgl.c new file mode 100644 index 0000000000..a0e5107998 --- /dev/null +++ b/src/soc/intel/jasperlake/meminit_tgl.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +enum dimm_enable_options { + ENABLE_BOTH_DIMMS = 0, + DISABLE_DIMM0 = 1, + DISABLE_DIMM1 = 2, + DISABLE_BOTH_DIMMS = 3 +}; + +#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch) \ + do { \ + memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch, \ + &_b_cfg->dq_map[_ch], \ + sizeof(_b_cfg->dq_map[_ch])); \ + memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch, \ + &_b_cfg->dqs_map[_ch], \ + sizeof(_b_cfg->dqs_map[_ch])); \ + } while (0) + + +static void spd_read_from_cbfs(const struct spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + if (spd->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + bool half_populated) +{ + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3); + + if (half_populated) + return; + + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7); +} + +static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + uintptr_t spd_data_ptr, + bool half_populated) +{ + uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ + + /* Channel 0 */ + mem_cfg->Reserved9[0] = dimm_cfg; + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + mem_cfg->MemorySpdPtr01 = 0; + + /* Channel 1 */ + mem_cfg->Reserved9[1] = dimm_cfg; + mem_cfg->MemorySpdPtr02 = spd_data_ptr; + mem_cfg->MemorySpdPtr03 = 0; + + /* Channel 2 */ + mem_cfg->Reserved9[2] = dimm_cfg; + mem_cfg->MemorySpdPtr04 = spd_data_ptr; + mem_cfg->MemorySpdPtr05 = 0; + + /* Channel 3 */ + mem_cfg->Reserved9[3] = dimm_cfg; + mem_cfg->MemorySpdPtr06 = spd_data_ptr; + mem_cfg->MemorySpdPtr07 = 0; + + if (half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + dimm_cfg = DISABLE_BOTH_DIMMS; + spd_data_ptr = 0; + } + + /* Channel 4 */ + mem_cfg->Reserved9[4] = dimm_cfg; + mem_cfg->MemorySpdPtr08 = spd_data_ptr; + mem_cfg->MemorySpdPtr09 = 0; + + /* Channel 5 */ + mem_cfg->Reserved9[5] = dimm_cfg; + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + mem_cfg->MemorySpdPtr11 = 0; + + /* Channel 6 */ + mem_cfg->Reserved9[6] = dimm_cfg; + mem_cfg->MemorySpdPtr12 = spd_data_ptr; + mem_cfg->MemorySpdPtr13 = 0; + + /* Channel 7 */ + mem_cfg->Reserved9[7] = dimm_cfg; + mem_cfg->MemorySpdPtr14 = spd_data_ptr; + mem_cfg->MemorySpdPtr15 = 0; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + const struct spd_info *spd, + bool half_populated) + +{ + size_t spd_data_len; + uintptr_t spd_data_ptr; + + get_spd_data(spd, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr, + half_populated); + + /* LPDDR4 does not allow interleaved memory */ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->ECT = board_cfg->ect; + mem_cfg->MrcSafeConfig = 0x1; +} diff --git a/src/soc/intel/jasperlake/p2sb.c b/src/soc/intel/jasperlake/p2sb.c new file mode 100644 index 0000000000..64f181f634 --- /dev/null +++ b/src/soc/intel/jasperlake/p2sb.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 3 + */ + +#include +#include + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = (1 << 31) | (1 << 30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c new file mode 100644 index 0000000000..13902b80a6 --- /dev/null +++ b/src/soc/intel/jasperlake/pmc.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; + uint8_t *const pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + write8(pmcbase + GEN_PMCON_A, reg8); +} + +static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + printk(BIOS_DEBUG, "%sabling Deep S%c\n", + enable ? "En" : "Dis", sx + '0'); + reg = read32(pmcbase + offset); + if (enable) + reg |= mask; + else + reg &= ~mask; + write32(pmcbase + offset, reg); +} + +static void config_deep_s5(int on_ac, int on_dc) +{ + /* Treat S4 the same as S5. */ + config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); + config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); + config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); + config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); +} + +static void config_deep_s3(int on_ac, int on_dc) +{ + config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); + config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); +} + +static void config_deep_sx(uint32_t deepsx_config) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg = read32(pmcbase + DSX_CFG); + reg &= ~DSX_CFG_MASK; + reg |= deepsx_config; + write32(pmcbase + DSX_CFG, reg); +} + +static void pmc_init(void *unused) +{ + const config_t *config = config_of_soc(); + + rtc_init(); + + pmc_set_power_failure_state(true); + pmc_gpe_init(); + + pmc_set_acpi_mode(); + + config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); + config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); + config_deep_sx(config->deep_sx_config); +} + +/* +* Initialize PMC controller. +* +* PMC controller gets hidden from PCI bus during FSP-Silicon init call. +* Hence PCI enumeration can't be used to initialize bus device and +* allocate resources. +*/ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c new file mode 100644 index 0000000000..ac254020cb --- /dev/null +++ b/src/soc/intel/jasperlake/pmutil.c @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SMI + */ + +const char *const *soc_smi_sts_array(size_t *a) +{ + static const char *const smi_sts_bits[] = { + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY_USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPE0_STS_BIT] = "GPE0", + [GPIO_STS_BIT] = "GPI", + [MCSMI_STS_BIT] = "MCSMI", + [DEVMON_STS_BIT] = "DEVMON", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [MONITOR_STS_BIT] = "MONITOR", + [SPI_SMI_STS_BIT] = "SPI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", + [ESPI_SMI_STS_BIT] = "ESPI_SMI", + }; + + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} + +/* + * TCO + */ + +const char *const *soc_tco_sts_array(size_t *a) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [18] = "BOOT", + [20] = "SMLINK_SLV" + }; + + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} + +/* + * GPE0 + */ + +const char *const *soc_std_gpe_sts_array(size_t *a) +{ + static const char *const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [12] = "ME", + [13] = "PME_B0", + [14] = "eSPI", + [15] = "GPIO Tier-2", + [16] = "LAN_WAKE", + [18] = "WADT" + }; + + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + uint8_t disb_val; + /* Only care about bits [23:16] of register GEN_PMCON_A */ + uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2); + + disb_val = read8(addr); + disb_val |= (DISB >> 16); + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); + write8(addr, disb_val); +} + +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + +/* + * PMC controller gets hidden from PCI bus + * during FSP-Silicon init call. Hence PWRMBASE + * can't be accessible using PCI configuration space + * read/write. + */ +uint8_t *pmc_mmio_regs(void) +{ + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t)pmc_mmio_regs(); +} + + +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + DEVTREE_CONST struct soc_intel_tigerlake_config *config; + + config = config_of_soc(); + + /* Assign to out variable */ + *dw0 = config->pmc_gpe0_dw0; + *dw1 = config->pmc_gpe0_dw1; + *dw2 = config->pmc_gpe0_dw2; +} + +static int rtc_failed(uint32_t gen_pmcon_b) +{ + return !!(gen_pmcon_b & RTC_BATTERY_DEAD); +} + +int soc_get_rtc_failed(void) +{ + const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (!ps) { + printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + return 1; + } + + return rtc_failed(ps->gen_pmcon_b); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); +} + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_a & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c new file mode 100644 index 0000000000..431a70ccb0 --- /dev/null +++ b/src/soc/intel/jasperlake/reset.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +void do_global_reset(void) +{ + /* Ask CSE to do the global reset */ + if (cse_request_global_reset(GLOBAL_RESET)) + return; + + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + do_full_reset(); +} + +void chipset_handle_reset(uint32_t status) +{ + switch (status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + global_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/jasperlake/romstage/Makefile.inc b/src/soc/intel/jasperlake/romstage/Makefile.inc new file mode 100644 index 0000000000..ff32916433 --- /dev/null +++ b/src/soc/intel/jasperlake/romstage/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c b/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c new file mode 100644 index 0000000000..18253aac9c --- /dev/null +++ b/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_tigerlake_config *config) +{ + unsigned int i; + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint32_t mask = 0; + + if (!dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->RMT = config->RMT; + + /* PCIe root port configuration */ + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + + m_cfg->PcieRpEnableMask = mask; + + _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >= + ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!"); + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + + _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >= + ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!"); + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + + /* Set CPU Ratio */ + m_cfg->CpuRatio = 0; + + /* Set debug interface flags */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT; + + /* VT-d config */ + m_cfg->VtdDisable = 0; + + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + + /* Display */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + + /* Audio */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(config->PchHdaAudioLinkDmicEnable)); + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(config->PchHdaAudioLinkSspEnable)); + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(config->PchHdaAudioLinkSndwEnable)); +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_tigerlake_config *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c b/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c new file mode 100644 index 0000000000..ac1a507270 --- /dev/null +++ b/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_tigerlake_config *config) +{ + unsigned int i; + uint32_t mask = 0; + const struct device *dev; + + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + + /* CpuRatio Settings */ + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + + for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) { + if (config->PcieClkSrcUsage[i] == 0) + m_cfg->PcieClkSrcUsage[i] = 0xff; + } + + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + + /* UART Debug Log */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : + DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; + m_cfg->PcdIsaSerialUartBase = 0x0; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + + /* + * Skip IGD initialization in FSP if device + * is disable in devicetree.cb. + */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) + m_cfg->InternalGfx = 0; + else + m_cfg->InternalGfx = 0x1; + + /* ISH */ + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + if (!dev || !dev->enabled) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = 1; + + /* DP port config */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBConfig = config->DdiPortBConfig; + m_cfg->DdiPortAHpd = config->DdiPortAHpd; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPort1Hpd = config->DdiPort1Hpd; + m_cfg->DdiPort2Hpd = config->DdiPort2Hpd; + m_cfg->DdiPort3Hpd = config->DdiPort3Hpd; + m_cfg->DdiPort4Hpd = config->DdiPort4Hpd; + m_cfg->DdiPortADdc = config->DdiPortADdc; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + m_cfg->DdiPort1Ddc = config->DdiPort1Ddc; + m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; + m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; + m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); + + /* Tcss */ + m_cfg->TcssXhciEn = config->TcssXhciEn; + m_cfg->TcssXdciEn = config->TcssXdciEn; + + /* USB4/TBT */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + if (dev) + m_cfg->TcssItbtPcie0En = dev->enabled; + else + m_cfg->TcssItbtPcie0En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + if (dev) + m_cfg->TcssItbtPcie1En = dev->enabled; + else + m_cfg->TcssItbtPcie1En = 0; + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + if (dev) + m_cfg->TcssItbtPcie2En = dev->enabled; + else + m_cfg->TcssItbtPcie2En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + if (dev) + m_cfg->TcssItbtPcie3En = dev->enabled; + else + m_cfg->TcssItbtPcie3En = 0; + + /* Enable Hyper Threading */ + m_cfg->HyperThreading = 1; + /* Disable Lock PCU Thermal Management registers */ + m_cfg->LockPTMregs = 0; + /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ + m_cfg->ChHashMask = 0x30CC; + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT; + + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + + /* Vt-D config */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdIopEnable = 0x1; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->VtdItbtEnable = 0x1; + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_tigerlake_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + config = config_of_soc(); + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/jasperlake/romstage/pch.c b/src/soc/intel/jasperlake/romstage/pch.c new file mode 100644 index 0000000000..a005ea0b99 --- /dev/null +++ b/src/soc/intel/jasperlake/romstage/pch.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c new file mode 100644 index 0000000000..f78ea29ae1 --- /dev/null +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int node, channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *meminfo_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; + + /* Locate the memory info HOB, presence validated by raminit */ + meminfo_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (meminfo_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Save available DIMM information */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; + channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; + dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; + + u8 memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program PCH init */ + pch_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/jasperlake/romstage/systemagent.c b/src/soc/intel/jasperlake/romstage/systemagent.c new file mode 100644 index 0000000000..9fa498e802 --- /dev/null +++ b/src/soc/intel/jasperlake/romstage/systemagent.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#include +#include +#include +#include + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} diff --git a/src/soc/intel/jasperlake/sd.c b/src/soc/intel/jasperlake/sd.c new file mode 100644 index 0000000000..9898734f3d --- /dev/null +++ b/src/soc/intel/jasperlake/sd.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 26 + */ + +#include +#include + +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) +{ + config_t *config = config_of(dev); + + if (!config->sdcard_cd_gpio) + return -1; + + gpio->type = ACPI_GPIO_TYPE_INTERRUPT; + gpio->pull = ACPI_GPIO_PULL_NONE; + gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; + gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; + gpio->irq.shared = ACPI_IRQ_SHARED; + gpio->irq.wake = ACPI_IRQ_WAKE; + gpio->interrupt_debounce_timeout = 10000; /* 100ms */ + gpio->pin_count = 1; + gpio->pins[0] = config->sdcard_cd_gpio; + + return 0; +} diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c new file mode 100644 index 0000000000..67e59a26a0 --- /dev/null +++ b/src/soc/intel/jasperlake/smihandler.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Specific SOC SMI handler during ramstage finalize phase + * + * BIOS can't make CSME function disable as is due to POSTBOOT_SAI + * restriction in place from TGP chipset. Hence create SMI Handler to + * perform CSME function disabling logic during SMM mode. + */ +void smihandler_soc_at_finalize(void) +{ + const struct soc_intel_tigerlake_config *config; + + config = config_of_soc(); + + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + heci_disable(); +} + +const smi_handler_t southbridge_smi[SMI_STS_BITS] = { + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPE0_STS_BIT] = smihandler_southbridge_gpe0, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, + [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) + [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, + [MONITOR_STS_BIT] = smihandler_southbridge_monitor, +}; diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c new file mode 100644 index 0000000000..44b464441d --- /dev/null +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) +{ + u32 smbase; + u32 iedbase; + + /* + * The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. + */ + smbase = staggered_smbase; + iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", + smbase, iedbase); + + /* + * All threads need to set IEDBASE and SMBASE to the relocated + * handler region. However, the save state location depends on the + * smm_save_state_in_msrs field in the relocation parameters. If + * smm_save_state_in_msrs is non-zero then the CPUs are relocating + * the SMM handler in parallel, and each CPUs save state area is + * located in their respective MSR space. If smm_save_state_in_msrs + * is zero then the SMM relocation is happening serially so the + * save state is at the same default location for all CPUs. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smbase_msr; + msr_t iedbase_msr; + + smbase_msr.lo = smbase; + smbase_msr.hi = 0; + + /* + * According the BWG the IEDBASE MSR is in bits 63:32. It's + * not clear why it differs from the SMBASE MSR. + */ + iedbase_msr.lo = 0; + iedbase_msr.hi = iedbase; + + wrmsr(SMBASE_MSR, smbase_msr); + wrmsr(IEDBASE_MSR, iedbase_msr); + } else { + em64t101_smm_state_save_area_t *save_state; + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); + + save_state->smbase = smbase; + save_state->iedbase = iedbase; + } +} + +/* Returns 1 if SMM MSR save state was set. */ +static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) +{ + msr_t smm_mca_cap; + + smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); + if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.hi = 0; + smm_feature_control.lo |= SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + relo_params->smm_save_state_in_msrs = 1; + } + return relo_params->smm_save_state_in_msrs; +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = &smm_reloc_params; + + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); + + /* + * Determine if the processor supports saving state in MSRs. If so, + * enable it before the non-BSPs run so that SMM relocation can occur + * in parallel in the non-BSP CPUs. + */ + if (cpu == 0) { + /* + * If smm_save_state_in_msrs is 1 then that means this is the + * 2nd time through the relocation handler for the BSP. + * Parallel SMM handler relocation is taking place. However, + * it is desired to access other CPUs save state in the real + * SMM handler. Therefore, disable the SMM save state in MSRs + * feature. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + } else if (bsp_setup_msr_save_state(relo_params)) + /* + * Just return from relocation handler if MSR save + * state is enabled. In that case the BSP will come + * back into the relocation handler to setup the new + * SMBASE as well disabling SMM save state in MSRs. + */ + return; + } + + /* Make appropriate changes to the save state map. */ + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + + /* Write SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); +} + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~(4 * KiB - 1); + + smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + 1 * MiB, 0, 32 * KiB); +} + +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (smm_reloc_params.ied_size) + setup_ied_area(&smm_reloc_params); + + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +void smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ + smm_initiate_relocation(); + + if (smm_reloc_params.smm_save_state_in_msrs) + printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); +} + +void smm_relocate(void) +{ + /* + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation + * shall take place. Run the relocation handler a second time on the + * BSP to do * the final move. For APs, a relocation handler always + * needs to be run. + */ + if (smm_reloc_params.smm_save_state_in_msrs) + smm_initiate_relocation_parallel(); + else if (!boot_cpu()) + smm_initiate_relocation(); +} + +void smm_lock(void) +{ + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + /* + * LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/soc/intel/jasperlake/spi.c b/src/soc/intel/jasperlake/spi.c new file mode 100644 index 0000000000..5270616af6 --- /dev/null +++ b/src/soc/intel/jasperlake/spi.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 7 + */ + +#include +#include + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: + return 0; + case PCH_DEVFN_GSPI0: + return 1; + case PCH_DEVFN_GSPI1: + return 2; + case PCH_DEVFN_GSPI2: + return 3; + } + return -1; +} diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c new file mode 100644 index 0000000000..fb0ce118aa --- /dev/null +++ b/src/soc/intel/jasperlake/systemagent.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#include +#include +#include +#include +#include +#include + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + /* + * PMC pci device gets hidden from PCI bus due to Silicon + * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with + * SA resources to ensure that PMCBAR falls under PCI reserved + * memory range. + * + * Note: Don't add any more resource with same offset 0x10 + * under this device space. + */ + { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, + "PMCBAR" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); +} diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c new file mode 100644 index 0000000000..03b4469a98 --- /dev/null +++ b/src/soc/intel/jasperlake/uart.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 9 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const struct uart_gpio_pad_config uart_gpio_pads[] = { + { + .console_index = 0, + .gpios = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + }, + }, + { + .console_index = 1, + .gpios = { + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ + }, + }, + { + .console_index = 2, + .gpios = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + }, + } +}; + +const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); + +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) +{ + /* + * if index is valid, this function will return corresponding structure + * for uart console else will return NULL. + */ + switch (uart_console) { + case 0: + return pcidev_path_on_root(PCH_DEVFN_UART0); + case 1: + return pcidev_path_on_root(PCH_DEVFN_UART1); + case 2: + return pcidev_path_on_root(PCH_DEVFN_UART2); + default: + printk(BIOS_ERR, "Invalid UART console index\n"); + return NULL; + } +} From 512b77abb582e6c2566d3873b273dd32731e7bae Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 25 Mar 2020 13:20:34 +0530 Subject: [PATCH 0654/1463] soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/Kconfig | 54 +-- src/soc/intel/jasperlake/Makefile.inc | 26 +- src/soc/intel/jasperlake/acpi/pci_irqs.asl | 131 +++++- .../intel/jasperlake/acpi/pci_irqs_jsl.asl | 141 ------- .../intel/jasperlake/acpi/pci_irqs_tgl.asl | 167 -------- src/soc/intel/jasperlake/acpi/pmc.asl | 2 +- src/soc/intel/jasperlake/acpi/xhci.asl | 53 ++- src/soc/intel/jasperlake/acpi/xhci_jsl.asl | 62 --- src/soc/intel/jasperlake/acpi/xhci_tgl.asl | 62 --- src/soc/intel/jasperlake/bootblock/cpu.c | 8 +- src/soc/intel/jasperlake/bootblock/pch.c | 30 +- .../jasperlake/bootblock/report_platform.c | 60 --- src/soc/intel/jasperlake/chip.c | 4 +- src/soc/intel/jasperlake/chip.h | 4 +- src/soc/intel/jasperlake/cpu.c | 6 - src/soc/intel/jasperlake/espi.c | 28 +- src/soc/intel/jasperlake/finalize.c | 6 - .../{fsp_params_jsl.c => fsp_params.c} | 4 +- src/soc/intel/jasperlake/fsp_params_tgl.c | 212 ---------- .../intel/jasperlake/{gpio_jsl.c => gpio.c} | 0 src/soc/intel/jasperlake/gpio_tgl.c | 197 --------- src/soc/intel/jasperlake/graphics.c | 6 - src/soc/intel/jasperlake/gspi.c | 6 - src/soc/intel/jasperlake/i2c.c | 6 - .../intel/jasperlake/include/soc/bootblock.h | 4 +- src/soc/intel/jasperlake/include/soc/cpu.h | 4 +- src/soc/intel/jasperlake/include/soc/espi.h | 21 +- src/soc/intel/jasperlake/include/soc/gpio.h | 24 +- .../intel/jasperlake/include/soc/gpio_defs.h | 261 +++++++++++- .../jasperlake/include/soc/gpio_defs_jsl.h | 272 ------------ .../jasperlake/include/soc/gpio_defs_tgl.h | 314 -------------- .../jasperlake/include/soc/gpio_soc_defs.h | 349 +++++++++++++++- .../include/soc/gpio_soc_defs_jsl.h | 358 ---------------- .../include/soc/gpio_soc_defs_tgl.h | 394 ------------------ src/soc/intel/jasperlake/include/soc/iomap.h | 24 +- src/soc/intel/jasperlake/include/soc/irq.h | 78 +++- .../intel/jasperlake/include/soc/irq_jsl.h | 86 ---- .../intel/jasperlake/include/soc/irq_tgl.h | 83 ---- src/soc/intel/jasperlake/include/soc/itss.h | 6 +- src/soc/intel/jasperlake/include/soc/me.h | 6 +- .../include/soc/{meminit_jsl.h => meminit.h} | 6 +- .../jasperlake/include/soc/meminit_tgl.h | 69 --- src/soc/intel/jasperlake/include/soc/p2sb.h | 10 +- src/soc/intel/jasperlake/include/soc/pch.h | 8 +- .../intel/jasperlake/include/soc/pci_devs.h | 9 +- .../intel/jasperlake/include/soc/pcr_ids.h | 10 +- src/soc/intel/jasperlake/include/soc/pm.h | 6 - src/soc/intel/jasperlake/include/soc/pmc.h | 43 +- src/soc/intel/jasperlake/include/soc/smbus.h | 10 +- .../intel/jasperlake/include/soc/soc_chip.h | 6 +- .../jasperlake/include/soc/systemagent.h | 10 +- src/soc/intel/jasperlake/lockdown.c | 6 - .../jasperlake/{meminit_jsl.c => meminit.c} | 2 +- src/soc/intel/jasperlake/meminit_tgl.c | 163 -------- src/soc/intel/jasperlake/p2sb.c | 6 - src/soc/intel/jasperlake/pmc.c | 6 - src/soc/intel/jasperlake/pmutil.c | 9 +- .../intel/jasperlake/romstage/Makefile.inc | 3 +- .../{fsp_params_jsl.c => fsp_params.c} | 6 +- .../jasperlake/romstage/fsp_params_tgl.c | 208 --------- .../intel/jasperlake/romstage/systemagent.c | 6 - src/soc/intel/jasperlake/sd.c | 6 - src/soc/intel/jasperlake/smihandler.c | 4 +- src/soc/intel/jasperlake/spi.c | 6 - src/soc/intel/jasperlake/systemagent.c | 6 - src/soc/intel/jasperlake/uart.c | 6 - 66 files changed, 939 insertions(+), 3250 deletions(-) delete mode 100644 src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl delete mode 100644 src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl delete mode 100644 src/soc/intel/jasperlake/acpi/xhci_jsl.asl delete mode 100644 src/soc/intel/jasperlake/acpi/xhci_tgl.asl rename src/soc/intel/jasperlake/{fsp_params_jsl.c => fsp_params.c} (97%) delete mode 100644 src/soc/intel/jasperlake/fsp_params_tgl.c rename src/soc/intel/jasperlake/{gpio_jsl.c => gpio.c} (100%) delete mode 100644 src/soc/intel/jasperlake/gpio_tgl.c delete mode 100644 src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h delete mode 100644 src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h delete mode 100644 src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h delete mode 100644 src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h delete mode 100644 src/soc/intel/jasperlake/include/soc/irq_jsl.h delete mode 100644 src/soc/intel/jasperlake/include/soc/irq_tgl.h rename src/soc/intel/jasperlake/include/soc/{meminit_jsl.h => meminit.h} (96%) delete mode 100644 src/soc/intel/jasperlake/include/soc/meminit_tgl.h rename src/soc/intel/jasperlake/{meminit_jsl.c => meminit.c} (99%) delete mode 100644 src/soc/intel/jasperlake/meminit_tgl.c rename src/soc/intel/jasperlake/romstage/{fsp_params_jsl.c => fsp_params.c} (95%) delete mode 100644 src/soc/intel/jasperlake/romstage/fsp_params_tgl.c diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index ed2fece152..01d7294743 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -1,22 +1,9 @@ -config SOC_INTEL_TIGERLAKE_BASE_COPY - bool - -config SOC_INTEL_TIGERLAKE_COPY - bool - select SOC_INTEL_TIGERLAKE_BASE_COPY - #TODO - Enable INTEL_CAR_NEM_ENHANCED - select INTEL_CAR_NEM - help - Intel Tigerlake support - config SOC_INTEL_JASPERLAKE_COPY bool - select SOC_INTEL_TIGERLAKE_BASE_COPY - select INTEL_CAR_NEM help Intel Jasperlake support -if SOC_INTEL_TIGERLAKE_BASE_COPY +if SOC_INTEL_JASPERLAKE_COPY config CPU_SPECIFIC_OPTIONS def_bool y @@ -36,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -84,13 +72,12 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x40400 if SOC_INTEL_TIGERLAKE_COPY - default 0x30400 if SOC_INTEL_JASPERLAKE_COPY + default 0x30400 help The amount of anticipated stack usage in CAR by bootblock and - other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage - stack requirement (~1KiB). + other stages. In the case of FSP_USES_CB_STACK default value + will be sum of FSP-M stack requirement(192 KiB) and CB romstage + stack requirement(~1KiB). config FSP_TEMP_RAM_SIZE hex @@ -102,8 +89,7 @@ config FSP_TEMP_RAM_SIZE config IFD_CHIPSET string - default "jsl" if SOC_INTEL_JASPERLAKE_COPY - default "tgl" if SOC_INTEL_TIGERLAKE_COPY + default "jsl" config IED_REGION_SIZE hex @@ -115,13 +101,11 @@ config HEAP_SIZE config MAX_ROOT_PORTS int - default 8 if SOC_INTEL_JASPERLAKE_COPY - default 12 if SOC_INTEL_TIGERLAKE_COPY + default 8 config MAX_PCIE_CLOCKS int - default 7 if SOC_INTEL_TIGERLAKE_COPY - default 6 if SOC_INTEL_JASPERLAKE_COPY + default 6 config SMM_TSEG_SIZE hex @@ -155,8 +139,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int - default 3 if SOC_INTEL_JASPERLAKE_COPY - default 4 if SOC_INTEL_TIGERLAKE_COPY + default 3 config SOC_INTEL_I2C_DEV_MAX int @@ -173,17 +156,14 @@ config CONSOLE_UART_BASE_ADDRESS # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clcok * M) /(N *16) -# TGL UART source clock: 120MHz # JSL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex - default 0x30 if SOC_INTEL_JASPERLAKE_COPY - default 0x25a if SOC_INTEL_TIGERLAKE_COPY + default 0x30 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex - default 0xc35 if SOC_INTEL_JASPERLAKE_COPY - default 0x7fff if SOC_INTEL_TIGERLAKE_COPY + default 0xc35 config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -205,17 +185,15 @@ config CBFS_SIZE config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE_COPY - default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE_COPY + default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE_COPY - default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE_COPY + default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" -config SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT - int "Debug Consent for TGL" +config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT + int "Debug Consent for JSL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y default 3 if SOC_INTEL_DEBUG_CONSENT diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index b02dc10250..29db4f3d00 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE_COPY),y) +ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode @@ -20,15 +20,12 @@ bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c -bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +bootblock-y += gpio.c bootblock-y += p2sb.c romstage-y += espi.c -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += meminit_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += meminit_jsl.c -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +romstage-y += gpio.c +romstage-y += meminit.c romstage-y += reset.c ramstage-y += acpi.c @@ -37,10 +34,8 @@ ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c -ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c -ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c -ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c -ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c @@ -50,17 +45,16 @@ ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c -smm-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c -smm-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c +smm-y += gpio.c smm-y += p2sb.c smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c -verstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c +verstage-y += gpio.c -CPPFLAGS_common += -I$(src)/soc/intel/tigerlake -CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include +CPPFLAGS_common += -I$(src)/soc/intel/jasperlake +CPPFLAGS_common += -I$(src)/soc/intel/jasperlake/include endif diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl index 474a6d6c1e..086282e733 100644 --- a/src/soc/intel/jasperlake/acpi/pci_irqs.asl +++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl @@ -13,8 +13,129 @@ * GNU General Public License for more details. */ -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - #include "pci_irqs_tgl.asl" -#else - #include "pci_irqs_jsl.asl" -#endif +#include + +Name (PICP, Package () { + /* cAVS, SMBus, GbE, Northpeak */ + Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, + Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ }, + /* SerialIo */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* eMMC */ + Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, + /* SerialIo */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* SATA controller */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 2, 0, IDER_IRQ }, + Package(){0x0016FFFF, 3, 0, KT_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* SerialIo */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ + Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, + Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, + Package(){0x0014FFFF, 5, 0, SD_IRQ }, + /* SerialIo */ + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Northpeak */ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 10 }, + Package () { 0x001FFFFF, 6, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D30: SerialIo */ + Package () {0x001EFFFF, 0, 0, 11 }, + Package () {0x001EFFFF, 1, 0, 10 }, + Package () {0x001EFFFF, 2, 0, 11 }, + Package () {0x001EFFFF, 3, 0, 11 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D26: eMMC */ + Package(){0x001AFFFF, 0, 0, 11 }, + /* D25: SerialIo */ + Package () {0x0019FFFF, 0, 0, 11 }, + Package () {0x0019FFFF, 1, 0, 10 }, + Package () {0x0019FFFF, 2, 0, 11 }, + /* D23: SATA controller */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, 0, 11 }, + Package () { 0x0016FFFF, 1, 0, 10 }, + Package () { 0x0016FFFF, 2, 0, 11 }, + Package () { 0x0016FFFF, 3, 0, 11 }, + Package () { 0x0016FFFF, 4, 0, 11 }, + Package () { 0x0016FFFF, 5, 0, 11 }, + /* D21: SerialIo */ + Package () {0x0015FFFF, 0, 0, 11 }, + Package () {0x0015FFFF, 1, 0, 10 }, + Package () {0x0015FFFF, 2, 0, 11 }, + Package () {0x0015FFFF, 3, 0, 11 }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ + Package () { 0x0014FFFF, 0, 0, 11 }, + Package () { 0x0014FFFF, 1, 0, 10 }, + Package () { 0x0014FFFF, 2, 0, 11 }, + Package () { 0x0014FFFF, 3, 0, 11 }, + Package () { 0x0014FFFF, 5, 0, 11 }, + /* D18: SerialIo */ + Package () {0x0012FFFF, 6, 0, 11 }, + /* SA IGFX Device */ + Package () {0x0002FFFF, 0, 0, 11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, 11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, 11 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl deleted file mode 100644 index 086282e733..0000000000 --- a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -Name (PICP, Package () { - /* cAVS, SMBus, GbE, Northpeak */ - Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ }, - /* SerialIo */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, - /* SerialIo */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* SATA controller */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, IDER_IRQ }, - Package(){0x0016FFFF, 3, 0, KT_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* SerialIo */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, - Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, - Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - Package(){0x0014FFFF, 5, 0, SD_IRQ }, - /* SerialIo */ - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, -}) - -Name (PICN, Package () { - /* D31: cAVS, SMBus, GbE, Northpeak */ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 10 }, - Package () { 0x001FFFFF, 6, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: SerialIo */ - Package () {0x001EFFFF, 0, 0, 11 }, - Package () {0x001EFFFF, 1, 0, 10 }, - Package () {0x001EFFFF, 2, 0, 11 }, - Package () {0x001EFFFF, 3, 0, 11 }, - /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D26: eMMC */ - Package(){0x001AFFFF, 0, 0, 11 }, - /* D25: SerialIo */ - Package () {0x0019FFFF, 0, 0, 11 }, - Package () {0x0019FFFF, 1, 0, 10 }, - Package () {0x0019FFFF, 2, 0, 11 }, - /* D23: SATA controller */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 11 }, - Package () { 0x0016FFFF, 1, 0, 10 }, - Package () { 0x0016FFFF, 2, 0, 11 }, - Package () { 0x0016FFFF, 3, 0, 11 }, - Package () { 0x0016FFFF, 4, 0, 11 }, - Package () { 0x0016FFFF, 5, 0, 11 }, - /* D21: SerialIo */ - Package () {0x0015FFFF, 0, 0, 11 }, - Package () {0x0015FFFF, 1, 0, 10 }, - Package () {0x0015FFFF, 2, 0, 11 }, - Package () {0x0015FFFF, 3, 0, 11 }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ - Package () { 0x0014FFFF, 0, 0, 11 }, - Package () { 0x0014FFFF, 1, 0, 10 }, - Package () { 0x0014FFFF, 2, 0, 11 }, - Package () { 0x0014FFFF, 3, 0, 11 }, - Package () { 0x0014FFFF, 5, 0, 11 }, - /* D18: SerialIo */ - Package () {0x0012FFFF, 6, 0, 11 }, - /* SA IGFX Device */ - Package () {0x0002FFFF, 0, 0, 11 }, - /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, 11 }, - /* SA GNA Device */ - Package () { 0x0008FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl deleted file mode 100644 index 7f632ba32e..0000000000 --- a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ - Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, - Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, ISH_IRQ }, - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, - Package(){0x0010FFFF, 6, 0, THC0_IRQ }, - Package(){0x0010FFFF, 7, 0, THC1_IRQ }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, - Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, PEG_IRQ }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, -}) - -Name (PICN, Package () { - /* D31:HSA, SMBUS, TraceHUB*/ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package () { 0x001EFFFF, 0, 0, 11 }, - Package () { 0x001EFFFF, 1, 0, 10 }, - Package () { 0x001EFFFF, 2, 0, 11 }, - Package () { 0x001EFFFF, 3, 0, 11 }, - /* D29: RP9 ~ RP12 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: RP1 ~ RP8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, 11 }, - Package(){0x0019FFFF, 1, 0, 10 }, - Package(){0x0019FFFF, 2, 0, 11 }, - /* D23: SATA */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, 11 }, - Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 4, 0, 11 }, - Package(){0x0016FFFF, 5, 0, 11 }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, 11 }, - Package(){0x0015FFFF, 1, 0, 10 }, - Package(){0x0015FFFF, 2, 0, 11 }, - Package(){0x0015FFFF, 3, 0, 11 }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, 11 }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 6, 0, 11 },, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, 11 }, - Package(){0x0010FFFF, 6, 0, 11 }, - Package(){0x0010FFFF, 7, 0, 10 }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, 11 }, - Package(){0x000DFFFF, 1, 0, 10 }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, 11 }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, 11 }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, 11 }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl index 6dd2d35354..0e3e24d94e 100644 --- a/src/soc/intel/jasperlake/acpi/pmc.asl +++ b/src/soc/intel/jasperlake/acpi/pmc.asl @@ -19,7 +19,7 @@ Scope (\_SB.PCI0) { Device (PMC) { Name (_HID, "INTC1026") - Name (_DDN, "Intel(R) Tiger Lake IPC Controller") + Name (_DDN, "Intel(R) Jasper Lake IPC Controller") /* * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl index 9baf67ac5a..41be89ace1 100644 --- a/src/soc/intel/jasperlake/acpi/xhci.asl +++ b/src/soc/intel/jasperlake/acpi/xhci.asl @@ -12,8 +12,51 @@ * GNU General Public License for more details. */ -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - #include "xhci_tgl.asl" -#else - #include "xhci_jsl.asl" -#endif +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Jasperlake PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 9) } + Device (SS02) { Name (_ADR, 10) } + Device (SS03) { Name (_ADR, 11) } + Device (SS04) { Name (_ADR, 12) } + Device (SS05) { Name (_ADR, 13) } + Device (SS06) { Name (_ADR, 14) } + } +} diff --git a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl deleted file mode 100644 index 41be89ace1..0000000000 --- a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* XHCI Controller 0:14.0 */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - - Name (_PRW, Package () { GPE0_PME_B0, 3 }) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Method (_PS0, 0, Serialized) - { - - } - - Method (_PS3, 0, Serialized) - { - - } - - /* Root Hub for Jasperlake PCH */ - Device (RHUB) - { - Name (_ADR, Zero) - - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 9) } - Device (SS02) { Name (_ADR, 10) } - Device (SS03) { Name (_ADR, 11) } - Device (SS04) { Name (_ADR, 12) } - Device (SS05) { Name (_ADR, 13) } - Device (SS06) { Name (_ADR, 14) } - } -} diff --git a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl deleted file mode 100644 index b97f52052b..0000000000 --- a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* XHCI Controller 0:14.0 */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - - Name (_PRW, Package () { GPE0_PME_B0, 3 }) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Method (_PS0, 0, Serialized) - { - - } - - Method (_PS3, 0, Serialized) - { - - } - - /* Root Hub for Tigerlake-LP PCH */ - Device (RHUB) - { - Name (_ADR, Zero) - - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - Device (HS09) { Name (_ADR, 9) } - Device (HS10) { Name (_ADR, 10) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 13) } - Device (SS02) { Name (_ADR, 14) } - Device (SS03) { Name (_ADR, 15) } - Device (SS04) { Name (_ADR, 16) } - } -} diff --git a/src/soc/intel/jasperlake/bootblock/cpu.c b/src/soc/intel/jasperlake/bootblock/cpu.c index dddf24352d..561172b2ae 100644 --- a/src/soc/intel/jasperlake/bootblock/cpu.c +++ b/src/soc/intel/jasperlake/bootblock/cpu.c @@ -12,19 +12,13 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 6 - */ - #include #include void bootblock_cpu_init(void) { /* - * Tigerlake platform doesn't support booting from any other media + * Jasperlake platform doesn't support booting from any other media * (like eMMC on APL/GLK platform) than only booting from SPI device * and on IA platform SPI is memory mapped hence enabling temporarily * cacheing on memory-mapped spi boot media. diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index b0646018c6..c98fdc5fb6 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 2, 3, 4, 27, 28 - */ - #include #include #include @@ -39,8 +33,8 @@ #include #include -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100 -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0xA00 + #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -60,20 +54,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -static uint32_t get_pmc_reg_base(void) -{ - uint8_t pch_series; - - pch_series = get_pch_series(); - - if (pch_series == PCH_TGP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP; - else if (pch_series == PCH_JSP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP; - else - return 0; -} - static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -116,11 +96,7 @@ void bootblock_pch_early_init(void) static void soc_config_acpibase(void) { uint32_t pmc_reg_value; - uint32_t pmc_base_reg; - - pmc_base_reg = get_pmc_reg_base(); - if (!pmc_base_reg) - die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n"); + uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index d7b2e0db32..35f2d1aead 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Platform Stepping and IDs - * Document number: 605534 - * Chapter number: 2, 4, 5, 6 - */ - #include #include #include @@ -36,7 +30,6 @@ static struct { u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, { CPUID_JASPERLAKE_A0, "Jasperlake A0" }, }; @@ -44,75 +37,22 @@ static struct { u16 mchid; const char *name; } mch_table[] = { - { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, - { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, - { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; static struct { u16 espiid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" }, - { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, - { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, - { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, - { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, - { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, }; static struct { u16 igdid; const char *name; } igd_table[] = { - { PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" }, - { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, - { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, - { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 1c7078d6cf..b7ed9df3d8 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -176,8 +176,8 @@ static void soc_enable(struct device *dev) dev->ops = &cpu_bus_ops; } -struct chip_operations soc_intel_tigerlake_ops = { - CHIP_NAME("Intel Tigerlake") +struct chip_operations soc_intel_jasperlake_ops = { + CHIP_NAME("Intel Jasperlake") .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index f82f13d45b..8611674332 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -33,7 +33,7 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 -struct soc_intel_tigerlake_config { +struct soc_intel_jasperlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; @@ -294,6 +294,6 @@ struct soc_intel_tigerlake_config { }; -typedef struct soc_intel_tigerlake_config config_t; +typedef struct soc_intel_jasperlake_config config_t; #endif diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index dfbcd22b94..57719c2d7b 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor CPU Datasheet - * Document number: 575683 - * Chapter number: 15 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index da36ea6304..500644e104 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 2 - */ - #include #include #include @@ -41,14 +35,14 @@ * certain memory range as reserved range for BIOS usage. * For this SOC, the range will be from 0FC800000h till FE7FFFFFh" */ -static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { +static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, { 0, 0 } }; const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() { - return tgl_lpc_fixed_mmio_ranges; + return jsl_lpc_fixed_mmio_ranges; } void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) @@ -70,24 +64,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); } -uint8_t get_pch_series(void) -{ - uint16_t lpc_did_hi_byte; - - /* - * Fetch upper 8 bits on ESPI device ID to determine PCH type - * Adding 1 to the offset to fetch upper 8 bits - */ - lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); - - if (lpc_did_hi_byte == 0xA0) - return PCH_TGP; - else if (lpc_did_hi_byte == 0x4d) - return PCH_JSP; - else - return PCH_UNKNOWN_SERIES; -} - #if ENV_RAMSTAGE static void soc_mirror_dmi_pcr_io_dec(void) { diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index b636ccbec0..714cda15e5 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 4, 29 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/fsp_params_jsl.c b/src/soc/intel/jasperlake/fsp_params.c similarity index 97% rename from src/soc/intel/jasperlake/fsp_params_jsl.c rename to src/soc/intel/jasperlake/fsp_params.c index 932bd06ff7..be73ab7319 100644 --- a/src/soc/intel/jasperlake/fsp_params_jsl.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -42,7 +42,7 @@ static const pci_devfn_t serial_io_dev[] = { static void parse_devicetree(FSP_S_CONFIG *params) { - const struct soc_intel_tigerlake_config *config = config_of_soc(); + const struct soc_intel_jasperlake_config *config = config_of_soc(); /* LPSS controllers configuration */ @@ -81,7 +81,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) unsigned int i; struct device *dev; FSP_S_CONFIG *params = &supd->FspsConfig; - struct soc_intel_tigerlake_config *config = config_of_soc(); + struct soc_intel_jasperlake_config *config = config_of_soc(); /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); diff --git a/src/soc/intel/jasperlake/fsp_params_tgl.c b/src/soc/intel/jasperlake/fsp_params_tgl.c deleted file mode 100644 index a8be407d23..0000000000 --- a/src/soc/intel/jasperlake/fsp_params_tgl.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Chip config parameter PcieRpL1Substates uses (UPD value + 1) - * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. - * In order to ensure that mainboard setting does not disable L1 substates - * incorrectly, chip config parameter values are offset by 1 with 0 meaning - * use FSP UPD default. get_l1_substate_control() ensures that the right UPD - * value is set in fsp_params. - * 0: Use FSP UPD default - * 1: Disable L1 substates - * 2: Use L1.1 - * 3: Use L1.2 (FSP UPD default) - */ -static int get_l1_substate_control(enum L1_substates_control ctl) -{ - if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) - ctl = L1_SS_L1_2; - return ctl - 1; -} - -static void parse_devicetree(FSP_S_CONFIG *params) -{ - const struct soc_intel_tigerlake_config *config; - config = config_of_soc(); - - for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) - params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; - - for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { - params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; - params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; - params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; - } - - for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) - params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; -} - -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_GSPI3, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - -/* UPD parameters to be initialized before SiliconInit */ -void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) -{ - int i; - FSP_S_CONFIG *params = &supd->FspsConfig; - - struct device *dev; - struct soc_intel_tigerlake_config *config; - config = config_of_soc(); - - /* Parse device tree and enable/disable Serial I/O devices */ - parse_devicetree(params); - - /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; - - for (i = 0; i < 8; i++) - params->IomTypeCPortPadCfg[i] = 0x09000000; - - /* USB */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; - params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; - params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; - params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; - params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; - } - - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { - params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; - if (config->usb3_ports[i].tx_de_emp) { - params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; - } - if (config->usb3_ports[i].tx_downscale_amp) { - params->Usb3HsioTxDownscaleAmpEnable[i] = 1; - params->Usb3HsioTxDownscaleAmp[i] = - config->usb3_ports[i].tx_downscale_amp; - } - } - - /* RP Configs */ - for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) - params->PcieRpL1Substates[i] = - get_l1_substate_control(config->PcieRpL1Substates[i]); - - /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); - if (dev) { - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; - } else { - params->XdciEnable = 0; - } - - /* PCH UART selection for FSP Debug */ - params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; - ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); - params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; - - /* SATA */ - dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); - if (!dev) - params->SataEnable = 0; - else { - params->SataEnable = dev->enabled; - params->SataMode = config->SataMode; - params->SataSalpSupport = config->SataSalpSupport; - memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); - } - - /* LAN */ - dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); - if (!dev) - params->PchLanEnable = 0; - else - params->PchLanEnable = dev->enabled; - - /* CNVi */ - dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); - if (dev) - params->CnviMode = dev->enabled; - else - params->CnviMode = 0; - - /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; - - /* Enable Hybrid storage auto detection */ - params->HybridStorageMode = config->HybridStorageMode; - - /* USB4/TBT */ - for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { - dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); - if (dev) - params->ITbtPcieRootPortEn[i] = dev->enabled; - else - params->ITbtPcieRootPortEn[i] = 0; - } - - mainboard_silicon_init_params(params); -} - -/* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/jasperlake/gpio_jsl.c b/src/soc/intel/jasperlake/gpio.c similarity index 100% rename from src/soc/intel/jasperlake/gpio_jsl.c rename to src/soc/intel/jasperlake/gpio.c diff --git a/src/soc/intel/jasperlake/gpio_tgl.c b/src/soc/intel/jasperlake/gpio_tgl.c deleted file mode 100644 index cfdd0ac465..0000000000 --- a/src/soc/intel/jasperlake/gpio_tgl.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 27 - */ - -static const struct reset_mapping rst_map[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, -}; -static const struct reset_mapping rst_map_com2[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, -}; - -/* - * This layout matches the Linux kernel pinctrl map for TGL-LP at: - * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c - */ -static const struct pad_group tgl_community0_groups[] = { - INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */ - INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */ - INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */ -}; - -static const struct pad_group tgl_community1_groups[] = { - INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */ - INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */ - INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */ - INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */ - INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */ -}; - -/* This community is not visible to the OS */ -static const struct pad_group tgl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ -}; - -static const struct pad_group tgl_community4_groups[] = { - INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ - INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */ - INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ - INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */ - INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */ -}; - -static const struct pad_group tgl_community5_groups[] = { - INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */ - INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ -}; - -static const struct pad_community tgl_communities[] = { - [COMM_0] = { /* GPP B, T, A */ - .port = PID_GPIOCOM0, - .first_pad = GPP_B0, - .last_pad = GPP_A24, - .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_BTA", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = tgl_community0_groups, - .num_groups = ARRAY_SIZE(tgl_community0_groups), - }, - [COMM_1] = { /* GPP S, D, H, U, VGPIO */ - .port = PID_GPIOCOM1, - .first_pad = GPP_S0, - .last_pad = vI2S2_RXD, - .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_SDHU", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = tgl_community1_groups, - .num_groups = ARRAY_SIZE(tgl_community1_groups), - }, - [COMM_2] = { /* GPD */ - .port = PID_GPIOCOM2, - .first_pad = GPD0, - .last_pad = GPD_DRAM_RESETB, - .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map_com2, - .num_reset_vals = ARRAY_SIZE(rst_map_com2), - .groups = tgl_community2_groups, - .num_groups = ARRAY_SIZE(tgl_community2_groups), - }, - [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */ - .port = PID_GPIOCOM4, - .first_pad = GPP_C0, - .last_pad = GPP_DBG_PMODE, - .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_FCE", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = tgl_community4_groups, - .num_groups = ARRAY_SIZE(tgl_community4_groups), - }, - [COMM_5] = { /* GPP R, SPI */ - .port = PID_GPIOCOM5, - .first_pad = GPP_R0, - .last_pad = GPP_CLK_LOOPBK, - .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_CPU_VBPIO", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = tgl_community5_groups, - .num_groups = ARRAY_SIZE(tgl_community5_groups), - } -}; - -const struct pad_community *soc_gpio_get_community(size_t *num_communities) -{ - *num_communities = ARRAY_SIZE(tgl_communities); - return tgl_communities; -} - -const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) -{ - static const struct pmc_to_gpio_route routes[] = { - { PMC_GPP_B, GPP_B }, - { PMC_GPP_T, GPP_T }, - { PMC_GPP_A, GPP_A }, - { PMC_GPP_R, GPP_R }, - { PMC_GPD, GPD }, - { PMC_GPP_S, GPP_S }, - { PMC_GPP_H, GPP_H }, - { PMC_GPP_D, GPP_D }, - { PMC_GPP_U, GPP_U }, - { PMC_GPP_F, GPP_F }, - { PMC_GPP_C, GPP_C }, - { PMC_GPP_E, GPP_E }, - }; - *num = ARRAY_SIZE(routes); - return routes; -} diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index fef17e17e8..4f5d573c8b 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor SA Datasheet - * Document number: 571131 - * Chapter number: 4 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c index 1381fb2499..706eeac854 100644 --- a/src/soc/intel/jasperlake/gspi.c +++ b/src/soc/intel/jasperlake/gspi.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 11 - */ - #include #include diff --git a/src/soc/intel/jasperlake/i2c.c b/src/soc/intel/jasperlake/i2c.c index 46bc726726..df95df924a 100644 --- a/src/soc/intel/jasperlake/i2c.c +++ b/src/soc/intel/jasperlake/i2c.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 13 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h index 0c8d8c201a..a93cff8dad 100644 --- a/src/soc/intel/jasperlake/include/soc/bootblock.h +++ b/src/soc/intel/jasperlake/include/soc/bootblock.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_BOOTBLOCK_H_ -#define _SOC_TIGERLAKE_BOOTBLOCK_H_ +#ifndef _SOC_JASPERLAKE_BOOTBLOCK_H_ +#define _SOC_JASPERLAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ void bootblock_cpu_init(void); diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index 799382498b..96e29bfcb8 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_CPU_H_ -#define _SOC_TIGERLAKE_CPU_H_ +#ifndef _SOC_JASPERLAKE_CPU_H_ +#define _SOC_JASPERLAKE_CPU_H_ #include diff --git a/src/soc/intel/jasperlake/include/soc/espi.h b/src/soc/intel/jasperlake/include/soc/espi.h index 3f7e32a717..7303a6d981 100644 --- a/src/soc/intel/jasperlake/include/soc/espi.h +++ b/src/soc/intel/jasperlake/include/soc/espi.h @@ -12,14 +12,8 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 2 - */ - -#ifndef _SOC_TIGERLAKE_ESPI_H_ -#define _SOC_TIGERLAKE_ESPI_H_ +#ifndef _SOC_JASPERLAKE_ESPI_H_ +#define _SOC_JASPERLAKE_ESPI_H_ #include @@ -44,15 +38,4 @@ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -/* - * This function will help to differentiate between 2 PCH on single type of soc. - * Since same soc may have LP series pch or H series PCH, we need to - * differentiate by reading upper 8 bits of PCH device ids. - * - * Return: - * Return PCH_LP or PCH_H macro in case of respective device ID found. - * PCH_UNKNOWN_SERIES in case of invalid device ID. - */ -uint8_t get_pch_series(void); - #endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h index fb3f42fd67..b24b467939 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio.h +++ b/src/soc/intel/jasperlake/include/soc/gpio.h @@ -12,27 +12,17 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_GPIO_H_ -#define _SOC_TIGERLAKE_GPIO_H_ +#ifndef _SOC_JASPERLAKE_GPIO_H_ +#define _SOC_JASPERLAKE_GPIO_H_ #include #include -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - #define CROS_GPIO_NAME "INT34C5" - #define CROS_GPIO_COMM0_NAME "INT34C5:00" - #define CROS_GPIO_COMM1_NAME "INT34C5:01" - #define CROS_GPIO_COMM4_NAME "INT34C5:02" - #define CROS_GPIO_COMM5_NAME "INT34C5:03" - -#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) - - #define CROS_GPIO_NAME "INT34C8" - #define CROS_GPIO_COMM0_NAME "INT34C8:00" - #define CROS_GPIO_COMM1_NAME "INT34C8:01" - #define CROS_GPIO_COMM4_NAME "INT34C8:02" - #define CROS_GPIO_COMM5_NAME "INT34C8:03" -#endif +#define CROS_GPIO_NAME "INT34C8" +#define CROS_GPIO_COMM0_NAME "INT34C8:00" +#define CROS_GPIO_COMM1_NAME "INT34C8:01" +#define CROS_GPIO_COMM4_NAME "INT34C8:02" +#define CROS_GPIO_COMM5_NAME "INT34C8:03" #endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h index 2898c12ee0..c030561a2e 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -12,12 +12,261 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ -#define _SOC_TIGERLAKE_GPIO_DEFS_H_ +#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_ +#define _SOC_JASPERLAKE_GPIO_DEFS_H_ -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - #include -#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) - #include +#ifndef __ACPI__ +#include #endif +#include + + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group F */ +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + +/* Group B */ +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + +/* Group D */ +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b +#define GPP_D20_IRQ 0x3c +#define GPP_D21_IRQ 0x3d +#define GPP_D22_IRQ 0x3e +#define GPP_D23_IRQ 0x3f + +/* Group GPD */ +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group R*/ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1a0 +#define PAD_CFG_BASE 0x600 + #endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h deleted file mode 100644 index 69ed539cae..0000000000 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_ -#define _SOC_JASPERLAKE_GPIO_DEFS_H_ - -#ifndef __ACPI__ -#include -#endif -#include - - -#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ - -#define NUM_GPIO_COMx_GPI_REGS(n) \ - (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) - -#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) -#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) -#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) -#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) - -#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS) +\ - (NUM_GPIO_COM5_GPI_REGS)) -/* - * IOxAPIC IRQs for the GPIOs - */ - -/* Group F */ -#define GPP_F0_IRQ 0x40 -#define GPP_F1_IRQ 0x41 -#define GPP_F2_IRQ 0x42 -#define GPP_F3_IRQ 0x43 -#define GPP_F4_IRQ 0x44 -#define GPP_F5_IRQ 0x45 -#define GPP_F6_IRQ 0x46 -#define GPP_F7_IRQ 0x47 -#define GPP_F8_IRQ 0x48 -#define GPP_F9_IRQ 0x49 -#define GPP_F10_IRQ 0x4a -#define GPP_F11_IRQ 0x4b -#define GPP_F12_IRQ 0x4c -#define GPP_F13_IRQ 0x4d -#define GPP_F14_IRQ 0x4e -#define GPP_F15_IRQ 0x4f -#define GPP_F16_IRQ 0x50 -#define GPP_F17_IRQ 0x51 -#define GPP_F18_IRQ 0x52 -#define GPP_F19_IRQ 0x53 - -/* Group G */ -#define GPP_G0_IRQ 0x18 -#define GPP_G1_IRQ 0x19 -#define GPP_G2_IRQ 0x1a -#define GPP_G3_IRQ 0x1b -#define GPP_G4_IRQ 0x1c -#define GPP_G5_IRQ 0x1d -#define GPP_G6_IRQ 0x1e -#define GPP_G7_IRQ 0x1f - -/* Group B */ -#define GPP_B0_IRQ 0x20 -#define GPP_B1_IRQ 0x21 -#define GPP_B2_IRQ 0x22 -#define GPP_B3_IRQ 0x23 -#define GPP_B4_IRQ 0x24 -#define GPP_B5_IRQ 0x25 -#define GPP_B6_IRQ 0x26 -#define GPP_B7_IRQ 0x27 -#define GPP_B8_IRQ 0x28 -#define GPP_B9_IRQ 0x29 -#define GPP_B10_IRQ 0x2a -#define GPP_B11_IRQ 0x2b -#define GPP_B12_IRQ 0x2c -#define GPP_B13_IRQ 0x2d -#define GPP_B14_IRQ 0x2e -#define GPP_B15_IRQ 0x2f -#define GPP_B16_IRQ 0x30 -#define GPP_B17_IRQ 0x31 -#define GPP_B18_IRQ 0x32 -#define GPP_B19_IRQ 0x33 -#define GPP_B20_IRQ 0x34 -#define GPP_B21_IRQ 0x35 -#define GPP_B22_IRQ 0x36 -#define GPP_B23_IRQ 0x37 - -/* Group A */ -#define GPP_A0_IRQ 0x38 -#define GPP_A1_IRQ 0x39 -#define GPP_A2_IRQ 0x3a -#define GPP_A3_IRQ 0x3b -#define GPP_A4_IRQ 0x3c -#define GPP_A5_IRQ 0x3d -#define GPP_A6_IRQ 0x3e -#define GPP_A7_IRQ 0x3f -#define GPP_A8_IRQ 0x40 -#define GPP_A9_IRQ 0x41 -#define GPP_A10_IRQ 0x42 -#define GPP_A11_IRQ 0x43 -#define GPP_A12_IRQ 0x44 -#define GPP_A13_IRQ 0x45 -#define GPP_A14_IRQ 0x46 -#define GPP_A15_IRQ 0x47 -#define GPP_A16_IRQ 0x48 -#define GPP_A17_IRQ 0x49 -#define GPP_A18_IRQ 0x4a -#define GPP_A19_IRQ 0x4b - -/* Group H */ -#define GPP_H0_IRQ 0x70 -#define GPP_H1_IRQ 0x71 -#define GPP_H2_IRQ 0x72 -#define GPP_H3_IRQ 0x73 -#define GPP_H4_IRQ 0x74 -#define GPP_H5_IRQ 0x75 -#define GPP_H6_IRQ 0x76 -#define GPP_H7_IRQ 0x77 -#define GPP_H8_IRQ 0x18 -#define GPP_H9_IRQ 0x19 -#define GPP_H10_IRQ 0x1a -#define GPP_H11_IRQ 0x1b -#define GPP_H12_IRQ 0x1c -#define GPP_H13_IRQ 0x1d -#define GPP_H14_IRQ 0x1e -#define GPP_H15_IRQ 0x1f -#define GPP_H16_IRQ 0x20 -#define GPP_H17_IRQ 0x21 -#define GPP_H18_IRQ 0x22 -#define GPP_H19_IRQ 0x23 -#define GPP_H20_IRQ 0x24 -#define GPP_H21_IRQ 0x25 -#define GPP_H22_IRQ 0x26 -#define GPP_H23_IRQ 0x27 - -/* Group D */ -#define GPP_D0_IRQ 0x28 -#define GPP_D1_IRQ 0x29 -#define GPP_D2_IRQ 0x2a -#define GPP_D3_IRQ 0x2b -#define GPP_D4_IRQ 0x2c -#define GPP_D5_IRQ 0x2d -#define GPP_D6_IRQ 0x2e -#define GPP_D7_IRQ 0x2f -#define GPP_D8_IRQ 0x30 -#define GPP_D9_IRQ 0x31 -#define GPP_D10_IRQ 0x32 -#define GPP_D11_IRQ 0x33 -#define GPP_D12_IRQ 0x34 -#define GPP_D13_IRQ 0x35 -#define GPP_D14_IRQ 0x36 -#define GPP_D15_IRQ 0x37 -#define GPP_D16_IRQ 0x38 -#define GPP_D17_IRQ 0x39 -#define GPP_D18_IRQ 0x3a -#define GPP_D19_IRQ 0x3b -#define GPP_D20_IRQ 0x3c -#define GPP_D21_IRQ 0x3d -#define GPP_D22_IRQ 0x3e -#define GPP_D23_IRQ 0x3f - -/* Group GPD */ -#define GPD0_IRQ 0x64 -#define GPD1_IRQ 0x65 -#define GPD2_IRQ 0x66 -#define GPD3_IRQ 0x67 -#define GPD4_IRQ 0x68 -#define GPD5_IRQ 0x69 -#define GPD6_IRQ 0x6a -#define GPD7_IRQ 0x6b -#define GPD8_IRQ 0x6c -#define GPD9_IRQ 0x6d -#define GPD10_IRQ 0x6e - -/* Group C */ -#define GPP_C0_IRQ 0x5a -#define GPP_C1_IRQ 0x5b -#define GPP_C2_IRQ 0x5c -#define GPP_C3_IRQ 0x5d -#define GPP_C4_IRQ 0x5e -#define GPP_C5_IRQ 0x5f -#define GPP_C6_IRQ 0x60 -#define GPP_C7_IRQ 0x61 -#define GPP_C8_IRQ 0x62 -#define GPP_C9_IRQ 0x63 -#define GPP_C10_IRQ 0x64 -#define GPP_C11_IRQ 0x65 -#define GPP_C12_IRQ 0x66 -#define GPP_C13_IRQ 0x67 -#define GPP_C14_IRQ 0x68 -#define GPP_C15_IRQ 0x69 -#define GPP_C16_IRQ 0x6a -#define GPP_C17_IRQ 0x6b -#define GPP_C18_IRQ 0x6c -#define GPP_C19_IRQ 0x6d -#define GPP_C20_IRQ 0x6e -#define GPP_C21_IRQ 0x6f -#define GPP_C22_IRQ 0x70 -#define GPP_C23_IRQ 0x71 -/* Group E */ -#define GPP_E0_IRQ 0x72 -#define GPP_E1_IRQ 0x73 -#define GPP_E2_IRQ 0x74 -#define GPP_E3_IRQ 0x75 -#define GPP_E4_IRQ 0x76 -#define GPP_E5_IRQ 0x77 -#define GPP_E6_IRQ 0x18 -#define GPP_E7_IRQ 0x19 -#define GPP_E8_IRQ 0x1a -#define GPP_E9_IRQ 0x1b -#define GPP_E10_IRQ 0x1c -#define GPP_E11_IRQ 0x1d -#define GPP_E12_IRQ 0x1e -#define GPP_E13_IRQ 0x1f -#define GPP_E14_IRQ 0x20 -#define GPP_E15_IRQ 0x21 -#define GPP_E16_IRQ 0x22 -#define GPP_E17_IRQ 0x23 -#define GPP_E18_IRQ 0x24 -#define GPP_E19_IRQ 0x25 -#define GPP_E20_IRQ 0x26 -#define GPP_E21_IRQ 0x27 -#define GPP_E22_IRQ 0x28 -#define GPP_E23_IRQ 0x29 - -/* Group R*/ -#define GPP_R0_IRQ 0x50 -#define GPP_R1_IRQ 0x51 -#define GPP_R2_IRQ 0x52 -#define GPP_R3_IRQ 0x53 -#define GPP_R4_IRQ 0x54 -#define GPP_R5_IRQ 0x55 -#define GPP_R6_IRQ 0x56 -#define GPP_R7_IRQ 0x57 - -/* Group S */ -#define GPP_S0_IRQ 0x5c -#define GPP_S1_IRQ 0x5d -#define GPP_S2_IRQ 0x5e -#define GPP_S3_IRQ 0x5f -#define GPP_S4_IRQ 0x60 -#define GPP_S5_IRQ 0x61 -#define GPP_S6_IRQ 0x62 -#define GPP_S7_IRQ 0x63 - -/* Register defines. */ -#define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xc0 -#define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x120 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1a0 -#define PAD_CFG_BASE 0x600 - -#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h deleted file mode 100644 index 35a15ded66..0000000000 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h +++ /dev/null @@ -1,314 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ -#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ - -#ifndef __ACPI__ -#include -#endif -#include - -#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ - -#define NUM_GPIO_COMx_GPI_REGS(n) \ - (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) - -#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) -#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) -#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) -#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) - -#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS) +\ - (NUM_GPIO_COM5_GPI_REGS)) -/* - * IOxAPIC IRQs for the GPIOs - */ - -/* Group B */ -#define GPP_B0_IRQ 0x18 -#define GPP_B1_IRQ 0x19 -#define GPP_B2_IRQ 0x1A -#define GPP_B3_IRQ 0x1B -#define GPP_B4_IRQ 0x1C -#define GPP_B5_IRQ 0x1D -#define GPP_B6_IRQ 0x1E -#define GPP_B7_IRQ 0x1F -#define GPP_B8_IRQ 0x20 -#define GPP_B9_IRQ 0x21 -#define GPP_B10_IRQ 0x22 -#define GPP_B11_IRQ 0x23 -#define GPP_B12_IRQ 0x24 -#define GPP_B13_IRQ 0x25 -#define GPP_B14_IRQ 0x26 -#define GPP_B15_IRQ 0x27 -#define GPP_B16_IRQ 0x28 -#define GPP_B17_IRQ 0x29 -#define GPP_B18_IRQ 0x2A -#define GPP_B19_IRQ 0x2B -#define GPP_B20_IRQ 0x2C -#define GPP_B21_IRQ 0x2D -#define GPP_B22_IRQ 0x2E -#define GPP_B23_IRQ 0x2F - -/* Group T */ -#define GPP_T0_IRQ 0x30 -#define GPP_T1_IRQ 0x31 -#define GPP_T2_IRQ 0x32 -#define GPP_T3_IRQ 0x33 -#define GPP_T4_IRQ 0x34 -#define GPP_T5_IRQ 0x35 -#define GPP_T6_IRQ 0x36 -#define GPP_T7_IRQ 0x37 -#define GPP_T8_IRQ 0x38 -#define GPP_T9_IRQ 0x39 -#define GPP_T10_IRQ 0x3A -#define GPP_T11IRQ 0x3B -#define GPP_T12_IRQ 0x3C -#define GPP_T13_IRQ 0x3D -#define GPP_T14_IRQ 0x3E -#define GPP_T15_IRQ 0x3F - -/* Group A */ -#define GPP_A0_IRQ 0x40 -#define GPP_A1_IRQ 0x41 -#define GPP_A2_IRQ 0x42 -#define GPP_A3_IRQ 0x43 -#define GPP_A4_IRQ 0x44 -#define GPP_A5_IRQ 0x45 -#define GPP_A6_IRQ 0x46 -#define GPP_A7_IRQ 0x47 -#define GPP_A8_IRQ 0x48 -#define GPP_A9_IRQ 0x49 -#define GPP_A10_IRQ 0x4A -#define GPP_A11_IRQ 0x4B -#define GPP_A12_IRQ 0x4C -#define GPP_A13_IRQ 0x4D -#define GPP_A14_IRQ 0x4E -#define GPP_A15_IRQ 0x4F -#define GPP_A16_IRQ 0x50 -#define GPP_A17_IRQ 0x51 -#define GPP_A18_IRQ 0x52 -#define GPP_A19_IRQ 0x53 -#define GPP_A20_IRQ 0x54 -#define GPP_A21_IRQ 0x55 -#define GPP_A22_IRQ 0x56 -#define GPP_A23_IRQ 0x57 - -/* Group R */ -#define GPP_R0_IRQ 0x58 -#define GPP_R1_IRQ 0x59 -#define GPP_R2_IRQ 0x5A -#define GPP_R3_IRQ 0x5B -#define GPP_R4_IRQ 0x5C -#define GPP_R5_IRQ 0x5D -#define GPP_R6_IRQ 0x5E -#define GPP_R7_IRQ 0x5F - - -/* Group D */ -#define GPD0_IRQ 0x60 -#define GPD1_IRQ 0x61 -#define GPD2_IRQ 0x62 -#define GPD3_IRQ 0x63 -#define GPD4_IRQ 0x64 -#define GPD5_IRQ 0x65 -#define GPD6_IRQ 0x66 -#define GPD7_IRQ 0x67 -#define GPD8_IRQ 0x68 -#define GPD9_IRQ 0x69 -#define GPD10_IRQ 0x6A -#define GPD11_IRQ 0x6B - -/* Group S */ -#define GPP_S0_IRQ 0x6C -#define GPP_S1_IRQ 0x6D -#define GPP_S2_IRQ 0x6E -#define GPP_S3_IRQ 0x6F -#define GPP_S4_IRQ 0x70 -#define GPP_S5_IRQ 0x71 -#define GPP_S6_IRQ 0x72 -#define GPP_S7_IRQ 0x73 - -/* Group H */ -#define GPP_H0_IRQ 0x74 -#define GPP_H1_IRQ 0x75 -#define GPP_H2_IRQ 0x76 -#define GPP_H3_IRQ 0x77 -#define GPP_H4_IRQ 0x18 -#define GPP_H5_IRQ 0x19 -#define GPP_H6_IRQ 0x1A -#define GPP_H7_IRQ 0x1B -#define GPP_H8_IRQ 0x1C -#define GPP_H9_IRQ 0x1D -#define GPP_H10_IRQ 0x1E -#define GPP_H11_IRQ 0x1F -#define GPP_H12_IRQ 0x20 -#define GPP_H13_IRQ 0x21 -#define GPP_H14_IRQ 0x22 -#define GPP_H15_IRQ 0x23 -#define GPP_H16_IRQ 0x24 -#define GPP_H17_IRQ 0x25 -#define GPP_H18_IRQ 0x26 -#define GPP_H19_IRQ 0x27 -#define GPP_H20_IRQ 0x28 -#define GPP_H21_IRQ 0x29 -#define GPP_H22_IRQ 0x2A -#define GPP_H23_IRQ 0x2B - -/* Group D */ -#define GPP_D0_IRQ 0x2C -#define GPP_D1_IRQ 0x2D -#define GPP_D2_IRQ 0x2E -#define GPP_D3_IRQ 0x2F -#define GPP_D4_IRQ 0x30 -#define GPP_D5_IRQ 0x31 -#define GPP_D6_IRQ 0x32 -#define GPP_D7_IRQ 0x33 -#define GPP_D8_IRQ 0x34 -#define GPP_D9_IRQ 0x35 -#define GPP_D10_IRQ 0x36 -#define GPP_D11_IRQ 0x37 -#define GPP_D12_IRQ 0x38 -#define GPP_D13_IRQ 0x39 -#define GPP_D14_IRQ 0x3A -#define GPP_D15_IRQ 0x3B -#define GPP_D16_IRQ 0x3C -#define GPP_D17_IRQ 0x3D -#define GPP_D18_IRQ 0x3E -#define GPP_D19_IRQ 0x3F - - -/* Group U */ -#define GPP_U0_IRQ 0x40 -#define GPP_U1IRQ 0x41 -#define GPP_U2_IRQ 0x42 -#define GPP_U3_IRQ 0x43 -#define GPP_U4_IRQ 0x44 -#define GPP_U5_IRQ 0x45 -#define GPP_U6_IRQ 0x46 -#define GPP_U7_IRQ 0x47 -#define GPP_U8_IRQ 0x48 -#define GPP_U9_IRQ 0x49 -#define GPP_U10_IRQ 0x4A -#define GPP_U11_IRQ 0x4B -#define GPP_U12_IRQ 0x4C -#define GPP_U13_IRQ 0x4D -#define GPP_U14_IRQ 0x4E -#define GPP_U15_IRQ 0x4F -#define GPP_U16_IRQ 0x50 -#define GPP_U17_IRQ 0x51 -#define GPP_U18_IRQ 0x52 -#define GPP_U19_IRQ 0x53 - - -#define GPP_VGPIO4_IRQ 0x54 - -/* Group F */ -#define GPP_F0_IRQ 0x56 -#define GPP_F1_IRQ 0x57 -#define GPP_F2_IRQ 0x58 -#define GPP_F3_IRQ 0x59 -#define GPP_F4_IRQ 0x5A -#define GPP_F5_IRQ 0x5B -#define GPP_F6_IRQ 0x5C -#define GPP_F7_IRQ 0x5D -#define GPP_F8_IRQ 0x5E -#define GPP_F9_IRQ 0x5F -#define GPP_F10_IRQ 0x60 -#define GPP_F11_IRQ 0x61 -#define GPP_F12_IRQ 0x62 -#define GPP_F13_IRQ 0x63 -#define GPP_F14_IRQ 0x64 -#define GPP_F15_IRQ 0x65 -#define GPP_F16_IRQ 0x66 -#define GPP_F17_IRQ 0x67 -#define GPP_F18_IRQ 0x68 -#define GPP_F19_IRQ 0x69 -#define GPP_F20_IRQ 0x6A -#define GPP_F21_IRQ 0x6B -#define GPP_F22_IRQ 0x6C -#define GPP_F23_IRQ 0x6D - -/* Group C */ -#define GPP_C0_iIRQ 0x6E -#define GPP_C1_IRQ 0x6F -#define GPP_C2_IRQ 0x70 -#define GPP_C3_IRQ 0x71 -#define GPP_C4_IRQ 0x72 -#define GPP_C5_IRQ 0x73 -#define GPP_C6_IRQ 0x74 -#define GPP_C7_IRQ 0x75 -#define GPP_C8_IRQ 0x76 -#define GPP_C9_IRQ 0x77 -#define GPP_C10_IRQ 0x18 -#define GPP_C11_IRQ 0x19 -#define GPP_C12_IRQ 0x1A -#define GPP_C13_IRQ 0x1B -#define GPP_C14_IRQ 0x1C -#define GPP_C15_IRQ 0x1D -#define GPP_C16_IRQ 0x1E -#define GPP_C17_IRQ 0x1F -#define GPP_C18_IRQ 0x20 -#define GPP_C19_IRQ 0x21 -#define GPP_C20_IRQ 0x22 -#define GPP_C21_IRQ 0x23 -#define GPP_C22_IRQ 0x24 -#define GPP_C23_IRQ 0x25 - - - -/* Group E */ -#define GPP_E0_IRQ 0x26 -#define GPP_E1_IRQ 0x27 -#define GPP_E2_IRQ 0x28 -#define GPP_E3_IRQ 0x29 -#define GPP_E4_IRQ 0x30 -#define GPP_E5_IRQ 0x31 -#define GPP_E6_IRQ 0x32 -#define GPP_E7_IRQ 0x33 -#define GPP_E8_IRQ 0x34 -#define GPP_E9_IRQ 0x35 -#define GPP_E10_IRQ 0x36 -#define GPP_E11_IRQ 0x37 -#define GPP_E12_IRQ 0x38 -#define GPP_E13_IRQ 0x39 -#define GPP_E14_IRQ 0x3A -#define GPP_E15_IRQ 0x3B -#define GPP_E16_IRQ 0x3C -#define GPP_E17_IRQ 0x3D -#define GPP_E18_IRQ 0x3E -#define GPP_E19_IRQ 0x3F -#define GPP_E20_IRQ 0x40 -#define GPP_E21_IRQ 0x41 -#define GPP_E22_IRQ 0x42 -#define GPP_E23_IRQ 0x43 - -/* Register defines. */ -#define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xb0 -#define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x110 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1A0 -#define PAD_CFG_BASE 0x700 - -#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h index b3ab9c3b5b..4570fceac8 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h @@ -11,13 +11,348 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ -#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - #include "gpio_soc_defs_tgl.h" -#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) - #include "gpio_soc_defs_jsl.h" -#endif +#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ + +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_G 0x2 +#define GPP_C 0x3 +#define GPP_R 0x4 +#define GPP_D 0x5 +#define GPP_S 0x6 +#define GPP_H 0x7 +#define GPP_VGPIO 0x8 +#define GPP_F 0x9 +#define GPP_GPD 0xA +#define GPP_E 0xD + +#define GPIO_NUM_GROUPS 12 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group F */ +#define GPP_F0 0 +#define GPP_F1 1 +#define GPP_F2 2 +#define GPP_F3 3 +#define GPP_F4 4 +#define GPP_F5 5 +#define GPP_F6 6 +#define GPP_F7 7 +#define GPP_F8 8 +#define GPP_F9 9 +#define GPP_F10 10 +#define GPP_F11 11 +#define GPP_F12 12 +#define GPP_F13 13 +#define GPP_F14 14 +#define GPP_F15 15 +#define GPP_F16 16 +#define GPP_F17 17 +#define GPP_F18 18 +#define GPP_F19 19 + +/* Group B */ +#define GPIO_RSVD_0 20 +#define GPIO_RSVD_1 21 +#define GPIO_RSVD_2 22 +#define GPIO_RSVD_3 23 +#define GPIO_RSVD_4 24 +#define GPIO_RSVD_5 25 +#define GPIO_RSVD_6 26 +#define GPIO_RSVD_7 27 +#define GPIO_RSVD_8 28 +#define GPP_B0 29 +#define GPP_B1 30 +#define GPP_B2 31 +#define GPP_B3 32 +#define GPP_B4 33 +#define GPP_B5 34 +#define GPP_B6 35 +#define GPP_B7 36 +#define GPP_B8 37 +#define GPP_B9 38 +#define GPP_B10 39 +#define GPP_B11 40 +#define GPP_B12 41 +#define GPP_B13 42 +#define GPP_B14 43 +#define GPP_B15 44 +#define GPP_B16 45 +#define GPP_B17 46 +#define GPP_B18 47 +#define GPP_B19 48 +#define GPP_B20 49 +#define GPP_B21 50 +#define GPP_B22 51 +#define GPP_B23 52 +#define GPIO_RSVD_9 53 +#define GPIO_RSVD_10 54 + +/* Group A */ +#define GPP_A0 55 +#define GPP_A1 56 +#define GPP_A2 57 +#define GPP_A3 58 +#define GPP_A4 59 +#define GPP_A5 60 +#define GPP_A6 61 +#define GPP_A7 62 +#define GPP_A8 63 +#define GPP_A9 64 +#define GPP_A10 65 +#define GPP_A11 66 +#define GPP_A12 67 +#define GPP_A13 68 +#define GPP_A14 69 +#define GPP_A15 70 +#define GPP_A16 71 +#define GPP_A17 72 +#define GPP_A18 73 +#define GPP_A19 74 +#define GPIO_RSVD_11 75 + +/* Group S */ +#define GPP_S0 76 +#define GPP_S1 77 +#define GPP_S2 78 +#define GPP_S3 79 +#define GPP_S4 80 +#define GPP_S5 81 +#define GPP_S6 82 +#define GPP_S7 83 + +/* Group R */ +#define GPP_R0 84 +#define GPP_R1 85 +#define GPP_R2 86 +#define GPP_R3 87 +#define GPP_R4 88 +#define GPP_R5 89 +#define GPP_R6 90 +#define GPP_R7 91 + +#define GPIO_COM0_START GPP_F0 +#define GPIO_COM0_END GPP_R7 +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group H */ +#define GPP_H0 92 +#define GPP_H1 93 +#define GPP_H2 94 +#define GPP_H3 95 +#define GPP_H4 96 +#define GPP_H5 97 +#define GPP_H6 98 +#define GPP_H7 99 +#define GPP_H8 100 +#define GPP_H9 101 +#define GPP_H10 102 +#define GPP_H11 103 +#define GPP_H12 104 +#define GPP_H13 105 +#define GPP_H14 106 +#define GPP_H15 107 +#define GPP_H16 108 +#define GPP_H17 109 +#define GPP_H18 110 +#define GPP_H19 111 +#define GPP_H20 112 +#define GPP_H21 113 +#define GPP_H22 114 +#define GPP_H23 115 + +/* Group D */ +#define GPP_D0 116 +#define GPP_D1 117 +#define GPP_D2 118 +#define GPP_D3 119 +#define GPP_D4 120 +#define GPP_D5 121 +#define GPP_D6 122 +#define GPP_D7 123 +#define GPP_D8 124 +#define GPP_D9 125 +#define GPP_D10 126 +#define GPP_D11 127 +#define GPP_D12 128 +#define GPP_D13 129 +#define GPP_D14 130 +#define GPP_D15 131 +#define GPP_D16 132 +#define GPP_D17 133 +#define GPP_D18 134 +#define GPP_D19 135 +#define GPP_D20 136 +#define GPP_D21 137 +#define GPP_D22 138 +#define GPP_D23 139 +#define GPIO_RSVD_12 140 +#define GPIO_RSVD_13 141 + +/* Group VGPIO */ +#define VGPIO_0 142 +#define VGPIO_3 143 +#define VGPIO_4 144 +#define VGPIO_5 145 +#define VGPIO_6 146 +#define VGPIO_7 147 +#define VGPIO_8 148 +#define VGPIO_9 149 +#define VGPIO_10 150 +#define VGPIO_11 151 +#define VGPIO_12 152 +#define VGPIO_13 153 +#define VGPIO_18 154 +#define VGPIO_19 155 +#define VGPIO_20 156 +#define VGPIO_21 157 +#define VGPIO_22 158 +#define VGPIO_23 159 +#define VGPIO_24 160 +#define VGPIO_25 161 +#define VGPIO_30 162 +#define VGPIO_31 163 +#define VGPIO_32 164 +#define VGPIO_33 165 +#define VGPIO_34 166 +#define VGPIO_35 167 +#define VGPIO_36 168 +#define VGPIO_37 169 +#define VGPIO_39 170 + +/* Group C */ +#define GPP_C0 171 +#define GPP_C1 172 +#define GPP_C2 173 +#define GPP_C3 174 +#define GPP_C4 175 +#define GPP_C5 176 +#define GPP_C6 177 +#define GPP_C7 178 +#define GPP_C8 179 +#define GPP_C9 180 +#define GPP_C10 181 +#define GPP_C11 182 +#define GPP_C12 183 +#define GPP_C13 184 +#define GPP_C14 185 +#define GPP_C15 186 +#define GPP_C16 187 +#define GPP_C17 188 +#define GPP_C18 189 +#define GPP_C19 190 +#define GPP_C20 191 +#define GPP_C21 192 +#define GPP_C22 193 +#define GPP_C23 194 + +#define GPIO_COM1_START GPP_H0 +#define GPIO_COM1_END GPP_C23 +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 195 +#define GPD1 196 +#define GPD2 197 +#define GPD3 198 +#define GPD4 199 +#define GPD5 200 +#define GPD6 201 +#define GPD7 202 +#define GPD8 203 +#define GPD9 204 +#define GPD10 205 +#define GPIO_RSVD_14 206 +#define GPIO_RSVD_15 207 +#define GPIO_RSVD_16 208 +#define GPIO_RSVD_17 209 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPIO_RSVD_17 +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group E */ +#define GPIO_RSVD_18 210 +#define GPIO_RSVD_19 211 +#define GPIO_RSVD_20 212 +#define GPIO_RSVD_21 213 +#define GPIO_RSVD_22 214 +#define GPIO_RSVD_23 215 +#define GPP_E0 216 +#define GPP_E1 217 +#define GPP_E2 218 +#define GPP_E3 219 +#define GPP_E4 220 +#define GPP_E5 221 +#define GPP_E6 222 +#define GPP_E7 223 +#define GPP_E8 224 +#define GPP_E9 225 +#define GPP_E10 226 +#define GPP_E11 227 +#define GPP_E12 228 +#define GPP_E13 229 +#define GPP_E14 230 +#define GPP_E15 231 +#define GPP_E16 232 +#define GPP_E17 233 +#define GPP_E18 234 +#define GPP_E19 235 +#define GPP_E20 236 +#define GPP_E21 237 +#define GPP_E22 238 +#define GPP_E23 239 +#define GPIO_RSVD_24 240 +#define GPIO_RSVD_25 241 +#define GPIO_RSVD_26 242 +#define GPIO_RSVD_27 243 +#define GPIO_RSVD_28 244 +#define GPIO_RSVD_29 245 +#define GPIO_RSVD_30 246 +#define GPIO_RSVD_31 247 +#define GPIO_RSVD_32 248 +#define GPIO_RSVD_33 249 +#define GPIO_RSVD_34 250 +#define GPIO_RSVD_35 251 +#define GPIO_RSVD_36 252 + +#define GPIO_COM4_START GPIO_RSVD_18 +#define GPIO_COM4_END GPIO_RSVD_36 +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group G */ +#define GPP_G0 253 +#define GPP_G1 254 +#define GPP_G2 255 +#define GPP_G3 256 +#define GPP_G4 257 +#define GPP_G5 258 +#define GPP_G6 259 +#define GPP_G7 260 + +#define GPIO_COM5_START GPP_G0 +#define GPIO_COM5_END GPP_G7 +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_PADS 261 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_4 3 +#define COMM_5 4 +#define TOTAL_GPIO_COMM 5 #endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h deleted file mode 100644 index 2ee52b260f..0000000000 --- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ -#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ - -/* - * Most of the fixed numbers and macros are based on the GPP groups. - * The GPIO groups are accessed through register blocks called - * communities. - */ - -#define GPP_A 0x0 -#define GPP_B 0x1 -#define GPP_G 0x2 -#define GPP_C 0x3 -#define GPP_R 0x4 -#define GPP_D 0x5 -#define GPP_S 0x6 -#define GPP_H 0x7 -#define GPP_VGPIO 0x8 -#define GPP_F 0x9 -#define GPP_GPD 0xA -#define GPP_E 0xD - -#define GPIO_NUM_GROUPS 12 -#define GPIO_MAX_NUM_PER_GROUP 24 - -/* - * GPIOs are ordered monotonically increasing to match ACPI/OS driver. - */ - -/* Group F */ -#define GPP_F0 0 -#define GPP_F1 1 -#define GPP_F2 2 -#define GPP_F3 3 -#define GPP_F4 4 -#define GPP_F5 5 -#define GPP_F6 6 -#define GPP_F7 7 -#define GPP_F8 8 -#define GPP_F9 9 -#define GPP_F10 10 -#define GPP_F11 11 -#define GPP_F12 12 -#define GPP_F13 13 -#define GPP_F14 14 -#define GPP_F15 15 -#define GPP_F16 16 -#define GPP_F17 17 -#define GPP_F18 18 -#define GPP_F19 19 - -/* Group B */ -#define GPIO_RSVD_0 20 -#define GPIO_RSVD_1 21 -#define GPIO_RSVD_2 22 -#define GPIO_RSVD_3 23 -#define GPIO_RSVD_4 24 -#define GPIO_RSVD_5 25 -#define GPIO_RSVD_6 26 -#define GPIO_RSVD_7 27 -#define GPIO_RSVD_8 28 -#define GPP_B0 29 -#define GPP_B1 30 -#define GPP_B2 31 -#define GPP_B3 32 -#define GPP_B4 33 -#define GPP_B5 34 -#define GPP_B6 35 -#define GPP_B7 36 -#define GPP_B8 37 -#define GPP_B9 38 -#define GPP_B10 39 -#define GPP_B11 40 -#define GPP_B12 41 -#define GPP_B13 42 -#define GPP_B14 43 -#define GPP_B15 44 -#define GPP_B16 45 -#define GPP_B17 46 -#define GPP_B18 47 -#define GPP_B19 48 -#define GPP_B20 49 -#define GPP_B21 50 -#define GPP_B22 51 -#define GPP_B23 52 -#define GPIO_RSVD_9 53 -#define GPIO_RSVD_10 54 - -/* Group A */ -#define GPP_A0 55 -#define GPP_A1 56 -#define GPP_A2 57 -#define GPP_A3 58 -#define GPP_A4 59 -#define GPP_A5 60 -#define GPP_A6 61 -#define GPP_A7 62 -#define GPP_A8 63 -#define GPP_A9 64 -#define GPP_A10 65 -#define GPP_A11 66 -#define GPP_A12 67 -#define GPP_A13 68 -#define GPP_A14 69 -#define GPP_A15 70 -#define GPP_A16 71 -#define GPP_A17 72 -#define GPP_A18 73 -#define GPP_A19 74 -#define GPIO_RSVD_11 75 - -/* Group S */ -#define GPP_S0 76 -#define GPP_S1 77 -#define GPP_S2 78 -#define GPP_S3 79 -#define GPP_S4 80 -#define GPP_S5 81 -#define GPP_S6 82 -#define GPP_S7 83 - -/* Group R */ -#define GPP_R0 84 -#define GPP_R1 85 -#define GPP_R2 86 -#define GPP_R3 87 -#define GPP_R4 88 -#define GPP_R5 89 -#define GPP_R6 90 -#define GPP_R7 91 - -#define GPIO_COM0_START GPP_F0 -#define GPIO_COM0_END GPP_R7 -#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) - -/* Group H */ -#define GPP_H0 92 -#define GPP_H1 93 -#define GPP_H2 94 -#define GPP_H3 95 -#define GPP_H4 96 -#define GPP_H5 97 -#define GPP_H6 98 -#define GPP_H7 99 -#define GPP_H8 100 -#define GPP_H9 101 -#define GPP_H10 102 -#define GPP_H11 103 -#define GPP_H12 104 -#define GPP_H13 105 -#define GPP_H14 106 -#define GPP_H15 107 -#define GPP_H16 108 -#define GPP_H17 109 -#define GPP_H18 110 -#define GPP_H19 111 -#define GPP_H20 112 -#define GPP_H21 113 -#define GPP_H22 114 -#define GPP_H23 115 - -/* Group D */ -#define GPP_D0 116 -#define GPP_D1 117 -#define GPP_D2 118 -#define GPP_D3 119 -#define GPP_D4 120 -#define GPP_D5 121 -#define GPP_D6 122 -#define GPP_D7 123 -#define GPP_D8 124 -#define GPP_D9 125 -#define GPP_D10 126 -#define GPP_D11 127 -#define GPP_D12 128 -#define GPP_D13 129 -#define GPP_D14 130 -#define GPP_D15 131 -#define GPP_D16 132 -#define GPP_D17 133 -#define GPP_D18 134 -#define GPP_D19 135 -#define GPP_D20 136 -#define GPP_D21 137 -#define GPP_D22 138 -#define GPP_D23 139 -#define GPIO_RSVD_12 140 -#define GPIO_RSVD_13 141 - -/* Group VGPIO */ -#define VGPIO_0 142 -#define VGPIO_3 143 -#define VGPIO_4 144 -#define VGPIO_5 145 -#define VGPIO_6 146 -#define VGPIO_7 147 -#define VGPIO_8 148 -#define VGPIO_9 149 -#define VGPIO_10 150 -#define VGPIO_11 151 -#define VGPIO_12 152 -#define VGPIO_13 153 -#define VGPIO_18 154 -#define VGPIO_19 155 -#define VGPIO_20 156 -#define VGPIO_21 157 -#define VGPIO_22 158 -#define VGPIO_23 159 -#define VGPIO_24 160 -#define VGPIO_25 161 -#define VGPIO_30 162 -#define VGPIO_31 163 -#define VGPIO_32 164 -#define VGPIO_33 165 -#define VGPIO_34 166 -#define VGPIO_35 167 -#define VGPIO_36 168 -#define VGPIO_37 169 -#define VGPIO_39 170 - -/* Group C */ -#define GPP_C0 171 -#define GPP_C1 172 -#define GPP_C2 173 -#define GPP_C3 174 -#define GPP_C4 175 -#define GPP_C5 176 -#define GPP_C6 177 -#define GPP_C7 178 -#define GPP_C8 179 -#define GPP_C9 180 -#define GPP_C10 181 -#define GPP_C11 182 -#define GPP_C12 183 -#define GPP_C13 184 -#define GPP_C14 185 -#define GPP_C15 186 -#define GPP_C16 187 -#define GPP_C17 188 -#define GPP_C18 189 -#define GPP_C19 190 -#define GPP_C20 191 -#define GPP_C21 192 -#define GPP_C22 193 -#define GPP_C23 194 - -#define GPIO_COM1_START GPP_H0 -#define GPIO_COM1_END GPP_C23 -#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) - -/* Group GPD */ -#define GPD0 195 -#define GPD1 196 -#define GPD2 197 -#define GPD3 198 -#define GPD4 199 -#define GPD5 200 -#define GPD6 201 -#define GPD7 202 -#define GPD8 203 -#define GPD9 204 -#define GPD10 205 -#define GPIO_RSVD_14 206 -#define GPIO_RSVD_15 207 -#define GPIO_RSVD_16 208 -#define GPIO_RSVD_17 209 - -#define GPIO_COM2_START GPD0 -#define GPIO_COM2_END GPIO_RSVD_17 -#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) - -/* Group E */ -#define GPIO_RSVD_18 210 -#define GPIO_RSVD_19 211 -#define GPIO_RSVD_20 212 -#define GPIO_RSVD_21 213 -#define GPIO_RSVD_22 214 -#define GPIO_RSVD_23 215 -#define GPP_E0 216 -#define GPP_E1 217 -#define GPP_E2 218 -#define GPP_E3 219 -#define GPP_E4 220 -#define GPP_E5 221 -#define GPP_E6 222 -#define GPP_E7 223 -#define GPP_E8 224 -#define GPP_E9 225 -#define GPP_E10 226 -#define GPP_E11 227 -#define GPP_E12 228 -#define GPP_E13 229 -#define GPP_E14 230 -#define GPP_E15 231 -#define GPP_E16 232 -#define GPP_E17 233 -#define GPP_E18 234 -#define GPP_E19 235 -#define GPP_E20 236 -#define GPP_E21 237 -#define GPP_E22 238 -#define GPP_E23 239 -#define GPIO_RSVD_24 240 -#define GPIO_RSVD_25 241 -#define GPIO_RSVD_26 242 -#define GPIO_RSVD_27 243 -#define GPIO_RSVD_28 244 -#define GPIO_RSVD_29 245 -#define GPIO_RSVD_30 246 -#define GPIO_RSVD_31 247 -#define GPIO_RSVD_32 248 -#define GPIO_RSVD_33 249 -#define GPIO_RSVD_34 250 -#define GPIO_RSVD_35 251 -#define GPIO_RSVD_36 252 - -#define GPIO_COM4_START GPIO_RSVD_18 -#define GPIO_COM4_END GPIO_RSVD_36 -#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) - -/* Group G */ -#define GPP_G0 253 -#define GPP_G1 254 -#define GPP_G2 255 -#define GPP_G3 256 -#define GPP_G4 257 -#define GPP_G5 258 -#define GPP_G6 259 -#define GPP_G7 260 - -#define GPIO_COM5_START GPP_G0 -#define GPIO_COM5_END GPP_G7 -#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) - -#define TOTAL_PADS 261 - -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -#define COMM_4 3 -#define COMM_5 4 -#define TOTAL_GPIO_COMM 5 - -#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h deleted file mode 100644 index ec582c3133..0000000000 --- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ -#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ -/* - * Most of the fixed numbers and macros are based on the GPP groups. - * The GPIO groups are accessed through register blocks called - * communities. - */ -#define GPP_B 0x0 -#define GPP_T 0x1 -#define GPP_A 0x2 -#define GPP_R 0x3 -#define GPD 0x4 -#define GPP_S 0x5 -#define GPP_H 0x6 -#define GPP_D 0x7 -#define GPP_U 0x8 -#define GPP_F 0xA -#define GPP_C 0xB -#define GPP_E 0xC - -#define GPIO_MAX_NUM_PER_GROUP 27 - -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -/* GPIO community 3 is not exposed to be used and hence is skipped. */ -#define COMM_4 3 -#define COMM_5 4 -/* - * GPIOs are ordered monotonically increasing to match ACPI/OS driver. - */ -/* Group B */ -#define GPP_B0 0 -#define GPP_B1 1 -#define GPP_B2 2 -#define GPP_B3 3 -#define GPP_B4 4 -#define GPP_B5 5 -#define GPP_B6 6 -#define GPP_B7 7 -#define GPP_B8 8 -#define GPP_B9 9 -#define GPP_B10 10 -#define GPP_B11 11 -#define GPP_B12 12 -#define GPP_B13 13 -#define GPP_B14 14 -#define GPP_B15 15 -#define GPP_B16 16 -#define GPP_B17 17 -#define GPP_B18 18 -#define GPP_B19 19 -#define GPP_B20 20 -#define GPP_B21 21 -#define GPP_B22 22 -#define GPP_B23 23 -#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ -#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ - -/* Group T */ -#define GPP_T0 26 -#define GPP_T1 27 -#define GPP_T2 28 -#define GPP_T3 29 -#define GPP_T4 30 -#define GPP_T5 31 -#define GPP_T6 32 -#define GPP_T7 33 -#define GPP_T8 34 -#define GPP_T9 35 -#define GPP_T10 36 -#define GPP_T11 37 -#define GPP_T12 38 -#define GPP_T13 39 -#define GPP_T14 40 -#define GPP_T15 41 - -/* Group A */ -#define GPP_A0 42 -#define GPP_A1 43 -#define GPP_A2 44 -#define GPP_A3 45 -#define GPP_A4 46 -#define GPP_A5 47 -#define GPP_A6 48 -#define GPP_A7 49 -#define GPP_A8 50 -#define GPP_A9 51 -#define GPP_A10 52 -#define GPP_A11 53 -#define GPP_A12 54 -#define GPP_A13 55 -#define GPP_A14 56 -#define GPP_A15 57 -#define GPP_A16 58 -#define GPP_A17 59 -#define GPP_A18 60 -#define GPP_A19 61 -#define GPP_A20 62 -#define GPP_A21 63 -#define GPP_A22 64 -#define GPP_A23 65 -#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ - -#define GPIO_COM0_START GPP_B0 -#define GPIO_COM0_END GPP_A24 -#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) - -/* Group S */ -#define GPP_S0 67 -#define GPP_S1 68 -#define GPP_S2 69 -#define GPP_S3 70 -#define GPP_S4 71 -#define GPP_S5 72 -#define GPP_S6 73 -#define GPP_S7 74 - -/* Group H */ -#define GPP_H0 75 -#define GPP_H1 76 -#define GPP_H2 77 -#define GPP_H3 78 -#define GPP_H4 79 -#define GPP_H5 80 -#define GPP_H6 81 -#define GPP_H7 82 -#define GPP_H8 83 -#define GPP_H9 84 -#define GPP_H10 85 -#define GPP_H11 86 -#define GPP_H12 87 -#define GPP_H13 88 -#define GPP_H14 89 -#define GPP_H15 90 -#define GPP_H16 91 -#define GPP_H17 92 -#define GPP_H18 93 -#define GPP_H19 94 -#define GPP_H20 95 -#define GPP_H21 96 -#define GPP_H22 97 -#define GPP_H23 98 - -/* Group D */ -#define GPP_D0 99 -#define GPP_D1 100 -#define GPP_D2 101 -#define GPP_D3 102 -#define GPP_D4 103 -#define GPP_D5 104 -#define GPP_D6 105 -#define GPP_D7 106 -#define GPP_D8 107 -#define GPP_D9 108 -#define GPP_D10 109 -#define GPP_D11 110 -#define GPP_D12 111 -#define GPP_D13 112 -#define GPP_D14 113 -#define GPP_D15 114 -#define GPP_D16 115 -#define GPP_D17 116 -#define GPP_D18 117 -#define GPP_D19 118 -#define GPP_GSPI2_CLK_LOOPBK 119 - -/* Group U */ -#define GPP_U0 120 -#define GPP_U1 121 -#define GPP_U2 122 -#define GPP_U3 123 -#define GPP_U4 124 -#define GPP_U5 125 -#define GPP_U6 126 -#define GPP_U7 127 -#define GPP_U8 128 -#define GPP_U9 129 -#define GPP_U10 130 -#define GPP_U11 131 -#define GPP_U12 132 -#define GPP_U13 133 -#define GPP_U14 134 -#define GPP_U15 135 -#define GPP_U16 136 -#define GPP_U17 137 -#define GPP_U18 138 -#define GPP_U19 139 -#define GPP_GSPI3_CLK_LOOPBK 140 -#define GPP_GSPI4_CLK_LOOPBK 141 -#define GPP_GSPI5_CLK_LOOPBK 142 -#define GPP_GSPI6_CLK_LOOPBK 143 - -/* Group VGPIO */ -#define CNV_BTEN 144 -#define CNV_BT_HOST_WAKEB 145 -#define CNV_BT_IF_SELECT 146 -#define vCNV_BT_UART_TXD 147 -#define vCNV_BT_UART_RXD 148 -#define vCNV_BT_UART_CTS_B 149 -#define vCNV_BT_UART_RTS_B 150 -#define vCNV_MFUART1_TXD 151 -#define vCNV_MFUART1_RXD 152 -#define vCNV_MFUART1_CTS_B 153 -#define vCNV_MFUART1_RTS_B 154 -#define vUART0_TXD 155 -#define vUART0_RXD 156 -#define vUART0_CTS_B 157 -#define vUART0_RTS_B 158 -#define vISH_UART0_TXD 159 -#define vISH_UART0_RXD 160 -#define vISH_UART0_CTS_B 161 -#define vISH_UART0_RTS_B 162 -#define vCNV_BT_I2S_BCLK 163 -#define vCNV_BT_I2S_WS_SYNC 164 -#define vCNV_BT_I2S_SDO 165 -#define vCNV_BT_I2S_SDI 166 -#define vI2S2_SCLK 167 -#define vI2S2_SFRM 168 -#define vI2S2_TXD 169 -#define vI2S2_RXD 170 - -#define GPIO_COM1_START GPP_S0 -#define GPIO_COM1_END vI2S2_RXD -#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) - -/* Group GPD */ -#define GPD0 171 -#define GPD1 172 -#define GPD2 173 -#define GPD3 174 -#define GPD4 175 -#define GPD5 176 -#define GPD6 177 -#define GPD7 178 -#define GPD8 179 -#define GPD9 180 -#define GPD10 181 -#define GPD11 182 -#define GPD_INPUT3VSEL 183 -#define GPD_SLP_LANB 184 -#define GPD__SLP_SUSB 185 -#define GPD_WAKEB 186 -#define GPD_DRAM_RESETB 187 - -#define GPIO_COM2_START GPD0 -#define GPIO_COM2_END GPD_DRAM_RESETB -#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) - -/* Group C */ -#define GPP_C0 188 -#define GPP_C1 189 -#define GPP_C2 190 -#define GPP_C3 191 -#define GPP_C4 192 -#define GPP_C5 193 -#define GPP_C6 194 -#define GPP_C7 195 -#define GPP_C8 196 -#define GPP_C9 197 -#define GPP_C10 198 -#define GPP_C11 199 -#define GPP_C12 200 -#define GPP_C13 201 -#define GPP_C14 202 -#define GPP_C15 203 -#define GPP_C16 204 -#define GPP_C17 205 -#define GPP_C18 206 -#define GPP_C19 207 -#define GPP_C20 208 -#define GPP_C21 209 -#define GPP_C22 210 -#define GPP_C23 211 - -/* Group F */ -#define GPP_F0 212 -#define GPP_F1 213 -#define GPP_F2 214 -#define GPP_F3 215 -#define GPP_F4 216 -#define GPP_F5 217 -#define GPP_F6 218 -#define GPP_F7 219 -#define GPP_F8 220 -#define GPP_F9 221 -#define GPP_F10 222 -#define GPP_F11 223 -#define GPP_F12 224 -#define GPP_F13 225 -#define GPP_F14 226 -#define GPP_F15 227 -#define GPP_F16 228 -#define GPP_F17 229 -#define GPP_F18 230 -#define GPP_F19 231 -#define GPP_F20 232 -#define GPP_F21 233 -#define GPP_F22 234 -#define GPP_F23 235 -#define GPP_F_CLK_LOOPBK 236 - -/* Group HVCMOS */ -#define GPP_L_BKLTEN 237 -#define GPP_L_BKLTCTL 238 -#define GPP_L_VDDEN 239 -#define GPP_SYS_PWROK 240 -#define GPP_SYS_RESETB 241 -#define GPP_MLK_RSTB 242 - -/* Group E */ -#define GPP_E0 243 -#define GPP_E1 244 -#define GPP_E2 245 -#define GPP_E3 246 -#define GPP_E4 247 -#define GPP_E5 248 -#define GPP_E6 249 -#define GPP_E7 250 -#define GPP_E8 251 -#define GPP_E9 252 -#define GPP_E10 253 -#define GPP_E11 254 -#define GPP_E12 255 -#define GPP_E13 256 -#define GPP_E14 257 -#define GPP_E15 258 -#define GPP_E16 259 -#define GPP_E17 260 -#define GPP_E18 261 -#define GPP_E19 262 -#define GPP_E20 263 -#define GPP_E21 264 -#define GPP_E22 265 -#define GPP_E23 266 -#define GPP_E_CLK_LOOPBK 267 - -/* Group JTAG */ -#define GPP_JTAG_TDO 268 -#define GPP_JTAG_X 269 -#define GPP_JTAG_PRDYB 270 -#define GPP_JTAG_PREQB 271 -#define GPP_CPU_TRSTB 272 -#define GPP_JTAG_TDI 273 -#define GPP_JTAG_TMS 274 -#define GPP_JTAG_TCK 275 -#define GPP_DBG_PMODE 276 - -#define GPIO_COM4_START GPP_C0 -#define GPIO_COM4_END GPP_DBG_PMODE -#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) - -/* Group R */ -#define GPP_R0 277 -#define GPP_R1 278 -#define GPP_R2 279 -#define GPP_R3 280 -#define GPP_R4 281 -#define GPP_R5 282 -#define GPP_R6 283 -#define GPP_R7 284 - -/* Group SPI */ -#define GPP_SPI_IO_2 285 -#define GPP_SPI_IO_3 286 -#define GPP_SPI_MOSI_IO_0 287 -#define GPP_SPI_MOSI_IO_1 288 -#define GPP_SPI_TPM_CSB 289 -#define GPP_SPI_FLASH_0_CSB 290 -#define GPP_SPI_FLASH_1_CSB 291 -#define GPP_SPI_CLK 292 -#define GPP_CLK_LOOPBK 293 - -#define GPIO_COM5_START GPP_R0 -#define GPIO_COM5_END GPP_CLK_LOOPBK -#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) - -#define TOTAL_GPIO_COMM (COMM_5 + 1) -#define TOTAL_PADS 294 - -#endif diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index 5eda08a132..ef166382ac 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -12,14 +12,8 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Firmware Architecture Specification - * Document number: 608531 - * Chapter number: 4 - */ - -#ifndef _SOC_TIGERLAKE_IOMAP_H_ -#define _SOC_TIGERLAKE_IOMAP_H_ +#ifndef _SOC_JASPERLAKE_IOMAP_H_ +#define _SOC_JASPERLAKE_IOMAP_H_ /* * Memory-mapped I/O registers. @@ -91,18 +85,6 @@ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - -#define MCH_BASE_ADDRESS 0xfedc0000 -#define MCH_BASE_SIZE 0x20000 - -#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 - -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -#else /* CONFIG_SOC_INTEL_JASPERLAKE_COPY */ - #define MCH_BASE_ADDRESS 0xfea80000 #define MCH_BASE_SIZE 0x8000 @@ -111,8 +93,6 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -#endif - /* * I/O port address space */ diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h index 6ca2588a0d..a6edd23d97 100644 --- a/src/soc/intel/jasperlake/include/soc/irq.h +++ b/src/soc/intel/jasperlake/include/soc/irq.h @@ -12,13 +12,75 @@ * GNU General Public License for more details. */ -#ifndef _SOC_IRQ_H_ -#define _SOC_IRQ_H_ +#ifndef _SOC_JSL_IRQ_H_ +#define _SOC_JSL_IRQ_H_ -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - #include "irq_tgl.h" -#else - #include "irq_jsl.h" -#endif /* CONFIG_SOC_INTEL_TIGERLAKE_COPY */ +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 -#endif /* _SOC_IRQ_H_ */ +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +/* LPSS Devices */ +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 + +/* PCI D:31 F:x */ +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +/* PCI D:28 F:x */ +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 + +/* PCI D:26 F:x */ +#define eMMC_IRQ 16 + +/* PCI D:23 F:x */ +#define SATA_IRQ 16 + +/* PCI D:22 F:x */ +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 +#define IDER_IRQ 18 +#define KT_IRQ 19 + +/* PCI D:20 F:x */ +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define CNViWIFI_IRQ 16 +#define SD_IRQ 19 +#define PMC_SRAM_IRQ 18 + +/* PCI D:18 F:x */ +#define UFS_IRQ 16 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 + +#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/irq_jsl.h b/src/soc/intel/jasperlake/include/soc/irq_jsl.h deleted file mode 100644 index a6edd23d97..0000000000 --- a/src/soc/intel/jasperlake/include/soc/irq_jsl.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_JSL_IRQ_H_ -#define _SOC_JSL_IRQ_H_ - -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 - -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -/* LPSS Devices */ -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 - -/* PCI D:31 F:x */ -#define cAVS_INTA_IRQ 16 -#define SMBUS_INTA_IRQ 16 -#define SMBUS_INTB_IRQ 17 -#define GbE_INTA_IRQ 16 -#define GbE_INTC_IRQ 18 -#define TRACE_HUB_INTA_IRQ 16 -#define TRACE_HUB_INTD_IRQ 19 - -/* PCI D:28 F:x */ -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 - -/* PCI D:26 F:x */ -#define eMMC_IRQ 16 - -/* PCI D:23 F:x */ -#define SATA_IRQ 16 - -/* PCI D:22 F:x */ -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 -#define IDER_IRQ 18 -#define KT_IRQ 19 - -/* PCI D:20 F:x */ -#define XHCI_IRQ 16 -#define OTG_IRQ 17 -#define CNViWIFI_IRQ 16 -#define SD_IRQ 19 -#define PMC_SRAM_IRQ 18 - -/* PCI D:18 F:x */ -#define UFS_IRQ 16 - -#define IGFX_IRQ 16 -#define SA_THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 - -#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/irq_tgl.h b/src/soc/intel/jasperlake/include/soc/irq_tgl.h deleted file mode 100644 index 6f268c1eae..0000000000 --- a/src/soc/intel/jasperlake/include/soc/irq_tgl.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_TGL_IRQ_H_ -#define _SOC_TGL_IRQ_H_ - -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 - -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 28 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 18 -#define LPSS_SPI3_IRQ 23 -#define LPSS_UART0_IRQ 34 -#define LPSS_UART1_IRQ 35 -#define LPSS_UART2_IRQ 33 - -#define HDA_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 - -#define THC0_IRQ 16 -#define THC1_IRQ 17 - -#define ISH_IRQ 16 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 -#endif /* _TGL_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/itss.h b/src/soc/intel/jasperlake/include/soc/itss.h index 39794ead73..97430022f3 100644 --- a/src/soc/intel/jasperlake/include/soc/itss.h +++ b/src/soc/intel/jasperlake/include/soc/itss.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef SOC_INTEL_TGL_ITSS_H -#define SOC_INTEL_TGL_ITSS_H +#ifndef SOC_INTEL_JSL_ITSS_H +#define SOC_INTEL_JSL_ITSS_H #define GPIO_IRQ_START 50 #define GPIO_IRQ_END ITSS_MAX_IRQ @@ -22,4 +22,4 @@ #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) -#endif /* SOC_INTEL_TGL_ITSS_H */ +#endif /* SOC_INTEL_JSL_ITSS_H */ diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h index 94331b4c9e..0fab6d582a 100644 --- a/src/soc/intel/jasperlake/include/soc/me.h +++ b/src/soc/intel/jasperlake/include/soc/me.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef _TIGERLAKE_ME_H_ -#define _TIGERLAKE_ME_H_ +#ifndef _JASPERLAKE_ME_H_ +#define _JASPERLAKE_ME_H_ /* ME Host Firmware Status register 1 */ union me_hfsts1 { @@ -52,4 +52,4 @@ union me_hfsts3 { u32 reserved_30: 2; } __packed fields; }; -#endif /* _TIGERLAKE_ME_H_ */ +#endif /* _JASPERLAKE_ME_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/meminit_jsl.h b/src/soc/intel/jasperlake/include/soc/meminit.h similarity index 96% rename from src/soc/intel/jasperlake/include/soc/meminit_jsl.h rename to src/soc/intel/jasperlake/include/soc/meminit.h index 421e31d8e4..0e2a46c0e5 100644 --- a/src/soc/intel/jasperlake/include/soc/meminit_jsl.h +++ b/src/soc/intel/jasperlake/include/soc/meminit.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ -#define _SOC_JASPERLAKE_MEMCFG_INIT_H_ +#ifndef _SOC_JASPERLAKE_MEMINIT_H_ +#define _SOC_JASPERLAKE_MEMINIT_H_ #include #include @@ -121,4 +121,4 @@ struct mb_cfg { void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, const struct spd_info *spd_info, bool half_populated); -#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */ +#endif /* _SOC_JASPERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/meminit_tgl.h b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h deleted file mode 100644 index 5573fb7110..0000000000 --- a/src/soc/intel/jasperlake/include/soc/meminit_tgl.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#ifndef _SOC_MEMINIT_TGL_H_ -#define _SOC_MEMINIT_TGL_H_ - -#include -#include -#include - -#define BYTES_PER_CHANNEL 2 -#define BITS_PER_BYTE 8 -#define DQS_PER_CHANNEL 2 -#define NUM_CHANNELS 8 - -struct spd_by_pointer { - size_t spd_data_len; - uintptr_t spd_data_ptr; -}; - -enum mem_info_read_type { - NOT_EXISTING, /* No memory in this channel */ - READ_SPD_CBFS, /* Find spd file in CBFS. */ - READ_SPD_MEMPTR /* Find spd data from pointer. */ -}; - -struct spd_info { - enum mem_info_read_type read_type; - union spd_data_by { - /* To identify spd file when read_type is READ_SPD_CBFS. */ - int spd_index; - - /* To find spd data when read_type is READ_SPD_MEMPTR. */ - struct spd_by_pointer spd_data_ptr_info; - } spd_spec; -}; - -/* Board-specific memory configuration information */ -struct mb_lpddr4x_cfg { - /* DQ mapping */ - uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; - - /* - * DQS CPU<>DRAM map. Each array entry represents a - * mapping of a dq bit on the CPU to the bit it's connected to on - * the memory part. The array index represents the dqs bit number - * on the memory part, and the values in the array represent which - * pin on the CPU that DRAM pin connects to. - */ - uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; - - /* - * Early Command Training Enable/Disable Control - * 1 = enable, 0 = disable - */ - uint8_t ect; -}; - -/* Initialize default memory configurations for dimm0-only lpddr4x */ -void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - const struct spd_info *spd, - bool half_populated); - -#endif /* _SOC_MEMINIT_TGL_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/p2sb.h b/src/soc/intel/jasperlake/include/soc/p2sb.h index d483ee399b..2fca70556c 100644 --- a/src/soc/intel/jasperlake/include/soc/p2sb.h +++ b/src/soc/intel/jasperlake/include/soc/p2sb.h @@ -12,14 +12,8 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 3 - */ - -#ifndef _SOC_TIGERLAKE_P2SB_H_ -#define _SOC_TIGERLAKE_P2SB_H_ +#ifndef _SOC_JASPERLAKE_P2SB_H_ +#define _SOC_JASPERLAKE_P2SB_H_ #define HPTC_OFFSET 0x60 #define HPTC_ADDR_ENABLE_BIT (1 << 7) diff --git a/src/soc/intel/jasperlake/include/soc/pch.h b/src/soc/intel/jasperlake/include/soc/pch.h index c2f497c1c8..ccfc44942b 100644 --- a/src/soc/intel/jasperlake/include/soc/pch.h +++ b/src/soc/intel/jasperlake/include/soc/pch.h @@ -12,15 +12,11 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_PCH_H_ -#define _SOC_TIGERLAKE_PCH_H_ +#ifndef _SOC_JASPERLAKE_PCH_H_ +#define _SOC_JASPERLAKE_PCH_H_ #include -#define PCH_TGP 1 -#define PCH_JSP 2 -#define PCH_UNKNOWN_SERIES 0xFF - #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h index e729864817..139d1827f5 100644 --- a/src/soc/intel/jasperlake/include/soc/pci_devs.h +++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_PCI_DEVS_H_ -#define _SOC_TIGERLAKE_PCI_DEVS_H_ +#ifndef _SOC_JASPERLAKE_PCI_DEVS_H_ +#define _SOC_JASPERLAKE_PCI_DEVS_H_ #include @@ -88,11 +88,8 @@ #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) #define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) - -#if CONFIG(SOC_INTEL_JASPERLAKE_COPY) #define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) #define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) -#endif #define PCH_DEV_SLOT_SIO3 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) @@ -130,11 +127,9 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) -#if CONFIG(SOC_INTEL_JASPERLAKE_COPY) #define PCH_DEV_SLOT_STORAGE 0x1a #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) #define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) -#endif #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h index 4143892f87..32ff6ba78a 100644 --- a/src/soc/intel/jasperlake/include/soc/pcr_ids.h +++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h @@ -12,14 +12,8 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 31-35 - */ - -#ifndef SOC_TIGERLAKE_PCR_H -#define SOC_TIGERLAKE_PCR_H +#ifndef SOC_JASPERLAKE_PCR_H +#define SOC_JASPERLAKE_PCR_H /* * Port ids */ diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index 14fa5d0c08..5fb15940ca 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 4 - */ - #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 0ec1d36e44..43c87de45f 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_PMC_H_ -#define _SOC_TIGERLAKE_PMC_H_ +#ifndef _SOC_JASPERLAKE_PMC_H_ +#define _SOC_JASPERLAKE_PMC_H_ /* PCI Configuration Space (D31:F2): PMC */ #define PWRMBASE 0x10 @@ -114,35 +114,16 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - - #define PMC_GPP_B 0x0 - #define PMC_GPP_T 0x1 - #define PMC_GPP_A 0x2 - #define PMC_GPP_R 0x3 - #define PMC_GPD 0x4 - #define PMC_GPP_S 0x5 - #define PMC_GPP_H 0x6 - #define PMC_GPP_D 0x7 - #define PMC_GPP_U 0x8 - #define PMC_GPP_F 0xA - #define PMC_GPP_C 0xB - #define PMC_GPP_E 0xC - -#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) - - #define PMC_GPP_A 0x0 - #define PMC_GPP_B 0x1 - #define PMC_GPP_F 0x2 - #define PMC_GPD 0x3 - #define PMC_GPP_R 0x4 - #define PMC_GPP_S 0x6 - #define PMC_GPP_D 0x7 - #define PMC_GPP_C 0x8 - #define PMC_GPP_H 0xA - #define PMC_GPP_E 0xF - -#endif +#define PMC_GPP_A 0x0 +#define PMC_GPP_B 0x1 +#define PMC_GPP_F 0x2 +#define PMC_GPD 0x3 +#define PMC_GPP_R 0x4 +#define PMC_GPP_S 0x6 +#define PMC_GPP_D 0x7 +#define PMC_GPP_C 0x8 +#define PMC_GPP_H 0xA +#define PMC_GPP_E 0xF #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h index 3fb8291698..fb19772e73 100644 --- a/src/soc/intel/jasperlake/include/soc/smbus.h +++ b/src/soc/intel/jasperlake/include/soc/smbus.h @@ -12,14 +12,8 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 6 - */ - -#ifndef _SOC_TIGERLAKE_SMBUS_H_ -#define _SOC_TIGERLAKE_SMBUS_H_ +#ifndef _SOC_JASPERLAKE_SMBUS_H_ +#define _SOC_JASPERLAKE_SMBUS_H_ /* IO and MMIO registers under primary BAR */ diff --git a/src/soc/intel/jasperlake/include/soc/soc_chip.h b/src/soc/intel/jasperlake/include/soc/soc_chip.h index 250aa9a0aa..d4e9be6d04 100644 --- a/src/soc/intel/jasperlake/include/soc/soc_chip.h +++ b/src/soc/intel/jasperlake/include/soc/soc_chip.h @@ -12,9 +12,9 @@ * GNU General Public License for more details. */ -#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_ -#define _SOC_TIGERLAKE_SOC_CHIP_H_ +#ifndef _SOC_JASPERLAKE_SOC_CHIP_H_ +#define _SOC_JASPERLAKE_SOC_CHIP_H_ #include "../../chip.h" -#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */ +#endif /* _SOC_JASPERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index d8c8ad47da..67ce880988 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -12,14 +12,8 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor SA Datasheet - * Document number: 571131 - * Chapter number: 3 - */ - -#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H -#define SOC_TIGERLAKE_SYSTEMAGENT_H +#ifndef SOC_JASPERLAKE_SYSTEMAGENT_H +#define SOC_JASPERLAKE_SYSTEMAGENT_H #include diff --git a/src/soc/intel/jasperlake/lockdown.c b/src/soc/intel/jasperlake/lockdown.c index 18d4fa728e..7ad5e4aa69 100644 --- a/src/soc/intel/jasperlake/lockdown.c +++ b/src/soc/intel/jasperlake/lockdown.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 4 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/meminit_jsl.c b/src/soc/intel/jasperlake/meminit.c similarity index 99% rename from src/soc/intel/jasperlake/meminit_jsl.c rename to src/soc/intel/jasperlake/meminit.c index c68d2100fc..88b39240bf 100644 --- a/src/soc/intel/jasperlake/meminit_jsl.c +++ b/src/soc/intel/jasperlake/meminit.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/soc/intel/jasperlake/meminit_tgl.c b/src/soc/intel/jasperlake/meminit_tgl.c deleted file mode 100644 index a0e5107998..0000000000 --- a/src/soc/intel/jasperlake/meminit_tgl.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include -#include -#include -#include -#include -#include - -enum dimm_enable_options { - ENABLE_BOTH_DIMMS = 0, - DISABLE_DIMM0 = 1, - DISABLE_DIMM1 = 2, - DISABLE_BOTH_DIMMS = 3 -}; - -#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch) \ - do { \ - memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch, \ - &_b_cfg->dq_map[_ch], \ - sizeof(_b_cfg->dq_map[_ch])); \ - memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch, \ - &_b_cfg->dqs_map[_ch], \ - sizeof(_b_cfg->dqs_map[_ch])); \ - } while (0) - - -static void spd_read_from_cbfs(const struct spd_info *spd, - uintptr_t *spd_data_ptr, size_t *spd_data_len) -{ - struct region_device spd_rdev; - size_t spd_index = spd->spd_spec.spd_index; - - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); - - *spd_data_len = region_device_sz(&spd_rdev); - - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); -} - -static void get_spd_data(const struct spd_info *spd, - uintptr_t *spd_data_ptr, size_t *spd_data_len) -{ - if (spd->read_type == READ_SPD_MEMPTR) { - *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; - *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; - return; - } - - if (spd->read_type == READ_SPD_CBFS) { - spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); - return; - } - - die("no valid way to read SPD info"); -} - -static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - bool half_populated) -{ - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3); - - if (half_populated) - return; - - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7); -} - -static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - uintptr_t spd_data_ptr, - bool half_populated) -{ - uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ - - /* Channel 0 */ - mem_cfg->Reserved9[0] = dimm_cfg; - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - mem_cfg->MemorySpdPtr01 = 0; - - /* Channel 1 */ - mem_cfg->Reserved9[1] = dimm_cfg; - mem_cfg->MemorySpdPtr02 = spd_data_ptr; - mem_cfg->MemorySpdPtr03 = 0; - - /* Channel 2 */ - mem_cfg->Reserved9[2] = dimm_cfg; - mem_cfg->MemorySpdPtr04 = spd_data_ptr; - mem_cfg->MemorySpdPtr05 = 0; - - /* Channel 3 */ - mem_cfg->Reserved9[3] = dimm_cfg; - mem_cfg->MemorySpdPtr06 = spd_data_ptr; - mem_cfg->MemorySpdPtr07 = 0; - - if (half_populated) { - printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); - dimm_cfg = DISABLE_BOTH_DIMMS; - spd_data_ptr = 0; - } - - /* Channel 4 */ - mem_cfg->Reserved9[4] = dimm_cfg; - mem_cfg->MemorySpdPtr08 = spd_data_ptr; - mem_cfg->MemorySpdPtr09 = 0; - - /* Channel 5 */ - mem_cfg->Reserved9[5] = dimm_cfg; - mem_cfg->MemorySpdPtr10 = spd_data_ptr; - mem_cfg->MemorySpdPtr11 = 0; - - /* Channel 6 */ - mem_cfg->Reserved9[6] = dimm_cfg; - mem_cfg->MemorySpdPtr12 = spd_data_ptr; - mem_cfg->MemorySpdPtr13 = 0; - - /* Channel 7 */ - mem_cfg->Reserved9[7] = dimm_cfg; - mem_cfg->MemorySpdPtr14 = spd_data_ptr; - mem_cfg->MemorySpdPtr15 = 0; - - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); -} - -/* Initialize onboard memory configurations for lpddr4x */ -void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - const struct spd_info *spd, - bool half_populated) - -{ - size_t spd_data_len; - uintptr_t spd_data_ptr; - - get_spd_data(spd, &spd_data_ptr, &spd_data_len); - print_spd_info((unsigned char *)spd_data_ptr); - - mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr, - half_populated); - - /* LPDDR4 does not allow interleaved memory */ - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->ECT = board_cfg->ect; - mem_cfg->MrcSafeConfig = 0x1; -} diff --git a/src/soc/intel/jasperlake/p2sb.c b/src/soc/intel/jasperlake/p2sb.c index 64f181f634..328c4d3bab 100644 --- a/src/soc/intel/jasperlake/p2sb.c +++ b/src/soc/intel/jasperlake/p2sb.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 3 - */ - #include #include diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index 13902b80a6..4667f1d905 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 4 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index ac254020cb..4134a2b7fc 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -17,13 +17,6 @@ * and the differences between PCH variants. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 4 - */ - - #define __SIMPLE_DEVICE__ #include @@ -183,7 +176,7 @@ uint32_t *soc_pmc_etr_addr(void) void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { - DEVTREE_CONST struct soc_intel_tigerlake_config *config; + DEVTREE_CONST struct soc_intel_jasperlake_config *config; config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/romstage/Makefile.inc b/src/soc/intel/jasperlake/romstage/Makefile.inc index ff32916433..5a8322b055 100644 --- a/src/soc/intel/jasperlake/romstage/Makefile.inc +++ b/src/soc/intel/jasperlake/romstage/Makefile.inc @@ -12,8 +12,7 @@ # GNU General Public License for more details. # -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c +romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += pch.c diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c b/src/soc/intel/jasperlake/romstage/fsp_params.c similarity index 95% rename from src/soc/intel/jasperlake/romstage/fsp_params_jsl.c rename to src/soc/intel/jasperlake/romstage/fsp_params.c index 18253aac9c..ca7ff26a0e 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -21,7 +21,7 @@ #include static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_tigerlake_config *config) + const struct soc_intel_jasperlake_config *config) { unsigned int i; const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); @@ -89,7 +89,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT; /* VT-d config */ m_cfg->VtdDisable = 0; @@ -131,7 +131,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct soc_intel_tigerlake_config *config = config_of_soc(); + const struct soc_intel_jasperlake_config *config = config_of_soc(); FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c b/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c deleted file mode 100644 index ac1a507270..0000000000 --- a/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_tigerlake_config *config) -{ - unsigned int i; - uint32_t mask = 0; - const struct device *dev; - - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->RMT; - - /* CpuRatio Settings */ - if (config->cpu_ratio_override) { - m_cfg->CpuRatio = config->cpu_ratio_override; - } else { - /* Set CpuRatio to match existing MSR value */ - msr_t flex_ratio; - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; - } - - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - - memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, - sizeof(config->PcieClkSrcUsage)); - - for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) { - if (config->PcieClkSrcUsage[i] == 0) - m_cfg->PcieClkSrcUsage[i] = 0xff; - } - - memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, - sizeof(config->PcieClkSrcClkReq)); - - m_cfg->PrmrrSize = config->PrmrrSize; - m_cfg->EnableC6Dram = config->enable_c6dram; - /* Disable BIOS Guard */ - m_cfg->BiosGuard = 0; - - /* UART Debug Log */ - m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : - DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; - m_cfg->PcdIsaSerialUartBase = 0x0; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; - - /* - * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. - */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) - m_cfg->InternalGfx = 0; - else - m_cfg->InternalGfx = 0x1; - - /* ISH */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (!dev || !dev->enabled) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = 1; - - /* DP port config */ - m_cfg->DdiPortAConfig = config->DdiPortAConfig; - m_cfg->DdiPortBConfig = config->DdiPortBConfig; - m_cfg->DdiPortAHpd = config->DdiPortAHpd; - m_cfg->DdiPortBHpd = config->DdiPortBHpd; - m_cfg->DdiPortCHpd = config->DdiPortCHpd; - m_cfg->DdiPort1Hpd = config->DdiPort1Hpd; - m_cfg->DdiPort2Hpd = config->DdiPort2Hpd; - m_cfg->DdiPort3Hpd = config->DdiPort3Hpd; - m_cfg->DdiPort4Hpd = config->DdiPort4Hpd; - m_cfg->DdiPortADdc = config->DdiPortADdc; - m_cfg->DdiPortBDdc = config->DdiPortBDdc; - m_cfg->DdiPortCDdc = config->DdiPortCDdc; - m_cfg->DdiPort1Ddc = config->DdiPort1Ddc; - m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; - m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; - m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; - - /* Image clock: disable all clocks for bypassing FSP pin mux */ - memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); - - /* Tcss */ - m_cfg->TcssXhciEn = config->TcssXhciEn; - m_cfg->TcssXdciEn = config->TcssXdciEn; - - /* USB4/TBT */ - dev = pcidev_path_on_root(SA_DEVFN_TBT0); - if (dev) - m_cfg->TcssItbtPcie0En = dev->enabled; - else - m_cfg->TcssItbtPcie0En = 0; - dev = pcidev_path_on_root(SA_DEVFN_TBT1); - if (dev) - m_cfg->TcssItbtPcie1En = dev->enabled; - else - m_cfg->TcssItbtPcie1En = 0; - - dev = pcidev_path_on_root(SA_DEVFN_TBT2); - if (dev) - m_cfg->TcssItbtPcie2En = dev->enabled; - else - m_cfg->TcssItbtPcie2En = 0; - dev = pcidev_path_on_root(SA_DEVFN_TBT3); - if (dev) - m_cfg->TcssItbtPcie3En = dev->enabled; - else - m_cfg->TcssItbtPcie3En = 0; - - /* Enable Hyper Threading */ - m_cfg->HyperThreading = 1; - /* Disable Lock PCU Thermal Management registers */ - m_cfg->LockPTMregs = 0; - /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ - m_cfg->ChHashMask = 0x30CC; - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT; - - /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; - - m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; - m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; - memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, - sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); - memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, - sizeof(m_cfg->PchHdaAudioLinkSspEnable)); - memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, - sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); - m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; - m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; - - /* Vt-D config */ - m_cfg->VtdDisable = 0; - m_cfg->VtdIgdEnable = 0x1; - m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; - m_cfg->VtdIpuEnable = 0x1; - m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; - m_cfg->VtdIopEnable = 0x1; - m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; - m_cfg->VtdItbtEnable = 0x1; - m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; - m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; - m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; - m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; - - /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct soc_intel_tigerlake_config *config; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - config = config_of_soc(); - - soc_memory_init_params(m_cfg, config); - mainboard_memory_init_params(mupd); -} - -__weak void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} diff --git a/src/soc/intel/jasperlake/romstage/systemagent.c b/src/soc/intel/jasperlake/romstage/systemagent.c index 9fa498e802..3cf61bd731 100644 --- a/src/soc/intel/jasperlake/romstage/systemagent.c +++ b/src/soc/intel/jasperlake/romstage/systemagent.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor SA Datasheet - * Document number: 571131 - * Chapter number: 3 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/sd.c b/src/soc/intel/jasperlake/sd.c index 9898734f3d..d97b63f498 100644 --- a/src/soc/intel/jasperlake/sd.c +++ b/src/soc/intel/jasperlake/sd.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 26 - */ - #include #include diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 67e59a26a0..3f6cfd2d7f 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -24,12 +24,12 @@ * Specific SOC SMI handler during ramstage finalize phase * * BIOS can't make CSME function disable as is due to POSTBOOT_SAI - * restriction in place from TGP chipset. Hence create SMI Handler to + * restriction in place from JSP chipset. Hence create SMI Handler to * perform CSME function disabling logic during SMM mode. */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_tigerlake_config *config; + const struct soc_intel_jasperlake_config *config; config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/spi.c b/src/soc/intel/jasperlake/spi.c index 5270616af6..9f3f44a227 100644 --- a/src/soc/intel/jasperlake/spi.c +++ b/src/soc/intel/jasperlake/spi.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 7 - */ - #include #include diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index fb0ce118aa..92777bfe5b 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor SA Datasheet - * Document number: 571131 - * Chapter number: 3 - */ - #include #include #include diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c index 03b4469a98..50849560ac 100644 --- a/src/soc/intel/jasperlake/uart.c +++ b/src/soc/intel/jasperlake/uart.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 9 - */ - #include #include #include From 1eea1dd7d78c0c043abb02986cae866cd5ff7ce1 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 2 May 2019 13:30:11 -0700 Subject: [PATCH 0655/1463] soc/intel/common: Hook up GMA ACPI brightness controls Add framework to hook up the generic src/drivers/intel/gma ACPI backlight control for platforms using SOC_INTEL_COMMON_BLOCK_GRAPHICS. Add a weak function to get the struct i915_gpu_controller_info needed to generate the SSDT, defaulting to NULL, which SoC's will override. Each SoC will need to override intel_igd_get_controller_info, and individual boards will need to populate the struct in order for the backlight control methods to be added to the SSDT. Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/32549 Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../intel/common/block/graphics/graphics.c | 30 ++++++++++++++----- .../block/include/intelblocks/graphics.h | 4 +++ 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index efbc3e7cc5..e1eb6fe6fb 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,20 @@ __weak void graphics_soc_init(struct device *dev) pci_dev_init(dev); } +__weak const struct i915_gpu_controller_info * +intel_igd_get_controller_info(struct device *device) +{ + return NULL; +} + +static void gma_generate_ssdt(struct device *device) +{ + const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device); + + if (gfx) + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static int is_graphics_disabled(struct device *dev) { /* Check if Graphics PCI device is disabled */ @@ -111,15 +126,16 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) } static const struct device_operations graphics_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = graphics_soc_init, - .ops_pci = &pci_dev_ops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = graphics_soc_init, + .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = graphics_soc_write_acpi_opregion, + .write_acpi_tables = graphics_soc_write_acpi_opregion, + .acpi_fill_ssdt_generator = gma_generate_ssdt, #endif - .scan_bus = scan_generic_bus, + .scan_bus = scan_generic_bus, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 8e98228424..153f9d8184 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -44,6 +44,10 @@ void graphics_soc_init(struct device *dev); uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, struct acpi_rsdp *rsdp); +/* i915 controller info for ACPI backlight controls */ +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(struct device *device); + /* Graphics MMIO register read/write APIs */ uint32_t graphics_gtt_read(unsigned long reg); void graphics_gtt_write(unsigned long reg, uint32_t data); From ddb4cf08f741dff9bdea708a34301efc0a6061eb Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 27 Mar 2020 14:13:07 -0500 Subject: [PATCH 0656/1463] soc/intel/skylake: Hook up GMA ACPI brightness controls Add struct i915_gpu_controller_info for boards to supply info needed to generate ACPI backlight control SSDT. Hook into soc/common framework by implementing intel_igd_get_controller_info(). Change-Id: I70e280e54d78e69a335f9a382261193c593ce430 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39883 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/skylake/chip.h | 4 ++++ src/soc/intel/skylake/graphics.c | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 178ab03a6b..1170b57704 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -583,6 +584,9 @@ struct soc_intel_skylake_config { /* Enable/Disable Sata test mode */ u8 SataTestMode; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index daa6eaa117..5f2fddfd56 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -185,3 +186,10 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device, printk(BIOS_DEBUG, "current = %lx\n", current); return current; } + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(struct device *device) +{ + struct soc_intel_skylake_config *chip = device->chip_info; + return &chip->gfx; +} From 79dfa909bb4e04b699fb28773855bade922ea50f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 22 Mar 2020 01:17:54 +0100 Subject: [PATCH 0657/1463] superio: Replace D1/D2 power states with D3 Spec says if any object to control the power state exists, at least D0 and D3 must be supported. And it seems Windows complains about the missing D3 support: https://ticket.coreboot.org/issues/257 Windows reported `*** STOP: 0x000000A5` with the first parameter `0x000000000000000D` (refers to a missing ACPI object) and the third parameter `0x000000003353505F` which is the name of the object in ASCII, little-endian (`_PS3`). Change-Id: Ifa28a7c56575848e76e4a1c542866413b4c44d50 Signed-off-by: Nico Huber Closes: https://ticket.coreboot.org/issues/257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39746 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/superio/acpi/pnp.asl | 6 ++-- src/superio/acpi/pnp_generic.asl | 4 +-- src/superio/acpi/pnp_uart.asl | 4 +-- .../winbond/w83627dhg/acpi/superio.asl | 8 ++--- src/superio/winbond/w83627hf/acpi/superio.asl | 32 +++++++++---------- src/superio/winbond/w83977tf/acpi/superio.asl | 4 +-- 6 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl index 1f607ebba4..bb71c9b1c6 100644 --- a/src/superio/acpi/pnp.asl +++ b/src/superio/acpi/pnp.asl @@ -69,7 +69,7 @@ /* * Current power state (returns the chip's state, if it's in - * power saving mode, 1 if this LDN is in power saving mode, + * power saving mode, 3 if this LDN is in power saving mode, * 0 else) * * PM_REG Identifier of a register which powers down the device @@ -82,7 +82,7 @@ ENTER_CONFIG_MODE (PM_LDN)\ Store (PM_REG, Local0)\ EXIT_CONFIG_MODE ()\ - If (LEqual(Local0, PM_VAL)) { Return (1) }\ + If (LEqual(Local0, PM_VAL)) { Return (3) }\ Else { Return (0) }\ /* Disable power saving mode */ @@ -92,7 +92,7 @@ EXIT_CONFIG_MODE () /* Enable power saving mode */ -#define PNP_GENERIC_PS1(PM_REG, PM_VAL, PM_LDN) \ +#define PNP_GENERIC_PS3(PM_REG, PM_VAL, PM_LDN) \ ENTER_CONFIG_MODE (PM_LDN)\ Store (PM_VAL, PM_REG)\ EXIT_CONFIG_MODE () diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index 482d73e40e..cb92a5d9c6 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -74,8 +74,8 @@ Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) { PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN) } - Method (_PS1) { - PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN) + Method (_PS3) { + PNP_GENERIC_PS3(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN) } #else Method (_PSC) { diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index e7278891a1..859430ee9f 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -57,8 +57,8 @@ Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { PNP_GENERIC_PS0(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_VAL, SUPERIO_UART_PM_LDN) } - Method (_PS1) { - PNP_GENERIC_PS1(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_VAL, SUPERIO_UART_PM_LDN) + Method (_PS3) { + PNP_GENERIC_PS3(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_VAL, SUPERIO_UART_PM_LDN) } #else Method (_PSC) { diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index cb6a4a7386..f86f16946e 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -109,12 +109,12 @@ Device(SUPERIO_DEV) { #define PNP_EXIT_MAGIC_1ST 0xaa #include - /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ Method (_PSC) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (IPD, Local0) EXIT_CONFIG_MODE () - If (Local0) { Return (2) } + If (Local0) { Return (3) } Else { Return (0) } } @@ -125,8 +125,8 @@ Device(SUPERIO_DEV) { EXIT_CONFIG_MODE () } - /* PM: Switch to D2 by setting IPD high */ - Method (_PS2) { + /* PM: Switch to D3 by setting IPD high */ + Method (_PS3) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, IPD) EXIT_CONFIG_MODE () diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index c1293ffc93..d5c5ec9026 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -166,12 +166,12 @@ Device(SIO) { Release (CRMX) } - /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ Method (_PSC) { ENCM (0xFF) Store (IPD, Local0) EXCM () - If (Local0) { Return (2) } + If (Local0) { Return (3) } Else { Return (0) } } @@ -182,8 +182,8 @@ Device(SIO) { EXCM () } - /* PM: Switch to D2 by setting IPD high */ - Method (_PS2) { + /* PM: Switch to D3 by setting IPD high */ + Method (_PS3) { ENCM (0xFF) Store (One, IPD) EXCM () @@ -220,7 +220,7 @@ Device(SIO) { ENCM (0xFF) Store (FDPW, Local0) EXCM () - If (Local0) { Return (1) } + If (Local0) { Return (3) } Else { Return (0) } } /* Disable power saving mode */ @@ -230,7 +230,7 @@ Device(SIO) { EXCM () } /* Enable power saving mode */ - Method (_PS1) { + Method (_PS3) { ENCM (0xFF) Store (Zero, FDPW) EXCM () @@ -441,7 +441,7 @@ Device(SIO) { ENCM (0xFF) Store (PRPW, Local0) EXCM () - If (Local0) { Return (1) } + If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { @@ -449,7 +449,7 @@ Device(SIO) { Store (One, PRPW) EXCM () } - Method (_PS1) { + Method (_PS3) { ENCM (0xFF) Store (Zero, PRPW) EXCM () @@ -618,7 +618,7 @@ Device(SIO) { ENCM (0xFF) Store (UAPW, Local0) EXCM () - If (Local0) { Return (1) } + If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { @@ -626,7 +626,7 @@ Device(SIO) { Store (One, UAPW) EXCM () } - Method (_PS1) { + Method (_PS3) { ENCM (0xFF) Store (Zero, UAPW) EXCM () @@ -743,7 +743,7 @@ Device(SIO) { ENCM (0xFF) Store (UBPW, Local0) EXCM () - If (Local0) { Return (1) } + If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { @@ -751,7 +751,7 @@ Device(SIO) { Store (One, UBPW) EXCM () } - Method (_PS1) { + Method (_PS3) { ENCM (0xFF) Store (Zero, UBPW) EXCM () @@ -868,7 +868,7 @@ Device(SIO) { ENCM (0xFF) Store (UBPW, Local0) EXCM () - If (Local0) { Return (1) } + If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { @@ -876,7 +876,7 @@ Device(SIO) { Store (One, UBPW) EXCM () } - Method (_PS1) { + Method (_PS3) { ENCM (0xFF) Store (Zero, UBPW) EXCM () @@ -1391,7 +1391,7 @@ Device(SIO) { ENCM (0xFF) Store (HWPW, Local0) EXCM () - If (Local0) { Return (1) } + If (Local0) { Return (3) } Else { Return (0) } } @@ -1402,7 +1402,7 @@ Device(SIO) { EXCM () } - Method (_PS1) + Method (_PS3) { ENCM (0xFF) Store (Zero, HWPW) diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index e2ff2ef1d6..c7a62cddd1 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -72,12 +72,12 @@ IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) #define PNP_EXIT_MAGIC_1ST 0xaa #include -/* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ +/* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ Method (_PSC) { ENTER_CONFIG_MODE (0xFF) Store (IPD, Local0) EXIT_CONFIG_MODE () - If (Local0) { Return (2) } + If (Local0) { Return (3) } Else { Return (0) } } From 8cb5c30c2a7e4cff1c1f12b0497ff269d3a929da Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 27 Mar 2020 20:04:32 +0100 Subject: [PATCH 0658/1463] soc/amd/picasso: Add Kconfig option for chip footprint Pollock uses the FT5 footprint, so add the Kconfig option to allow us to differentiate the chips. Change-Id: Ia4663d38f1824786f14b6aa000adf27d64e70b5f Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/2051509 Reviewed-by: Martin Roth Reviewed-by: Eric Peers Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/39867 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/amd/picasso/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a7423e907a..d9211b4fb6 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -59,6 +59,16 @@ config HAVE_BOOTBLOCK bool default n +config AMD_FP5 + def_bool y if !AMD_FT5 + help + The FP5 package supports higher-wattage parts and dual channel DDR4 memory. + +config AMD_FT5 + def_bool n + help + The FT5 package supports low-power parts and single-channel DDR4 memory. + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 From eb30e1a9aa08a89c14631e29f8461b9b62b5d4fc Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 10 Dec 2019 21:50:10 -0700 Subject: [PATCH 0659/1463] soc/amd/picasso: Add and use CPUID defines for Picasso and Raven2 Change-Id: I35a1c404ff2f381d3d6bf4f2e4bbbf5429db38c3 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/1961485 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39885 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/soc/amd/picasso/cpu.c | 4 ++-- src/soc/amd/picasso/include/soc/cpu.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c7e847d314..60446882d5 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -128,8 +128,8 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x810f80 }, - { X86_VENDOR_AMD, 0x810f81 }, - { X86_VENDOR_AMD, 0x820f01 }, + { X86_VENDOR_AMD, PICASSO_CPUID }, + { X86_VENDOR_AMD, RAVEN2_CPUID }, { 0, 0 }, }; diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 2bcffdc320..c53829d5c8 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -23,4 +23,7 @@ void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void); +#define PICASSO_CPUID 0x00810f81 +#define RAVEN2_CPUID 0x00820f01 + #endif /* __PICASSO_CPU_H__ */ From 4554942c8c3e85c4f17c18d33d41cb19d64a43c0 Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Thu, 26 Mar 2020 16:14:58 -0600 Subject: [PATCH 0660/1463] hatch: Create sushi variant Create the sushi variant of the hatch reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 3.0.0). BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_SUSHI Signed-off-by: Paul Fagerburg Change-Id: Ie900d09ff55e695527eafe68a5a75cd4a0b6d340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39892 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/hatch/Kconfig | 2 ++ src/mainboard/google/hatch/Kconfig.name | 5 ++++ .../google/hatch/variants/sushi/Makefile.inc | 13 ++++++++++ .../sushi/include/variant/acpi/dptf.asl | 14 ++++++++++ .../hatch/variants/sushi/include/variant/ec.h | 19 ++++++++++++++ .../variants/sushi/include/variant/gpio.h | 26 +++++++++++++++++++ .../hatch/variants/sushi/overridetree.cb | 6 +++++ 7 files changed, 85 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/sushi/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/sushi/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/sushi/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 2bb878491b..04790e0e0a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -103,6 +103,7 @@ config MAINBOARD_PART_NUMBER default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE + default "Sushi" if BOARD_GOOGLE_SUSHI config OVERRIDE_DEVICETREE string @@ -128,6 +129,7 @@ config VARIANT_DIR default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE + default "sushi" if BOARD_GOOGLE_SUSHI config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 207ba2afe5..454561b105 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -75,3 +75,8 @@ config BOARD_GOOGLE_STRYKE bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + +config BOARD_GOOGLE_SUSHI + bool "-> Sushi" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/google/hatch/variants/sushi/Makefile.inc b/src/mainboard/google/hatch/variants/sushi/Makefile.inc new file mode 100644 index 0000000000..38cf728d8f --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..496334daab --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h b/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h new file mode 100644 index 0000000000..25269627bd --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h new file mode 100644 index 0000000000..3b07c1ba20 --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +#endif diff --git a/src/mainboard/google/hatch/variants/sushi/overridetree.cb b/src/mainboard/google/hatch/variants/sushi/overridetree.cb new file mode 100644 index 0000000000..abbcaaa08c --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/cannonlake + + device domain 0 on + end + +end From b49e210984c4e44669e1335f97f32c83ff948a31 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Nov 2019 11:29:33 +0100 Subject: [PATCH 0661/1463] cpu/x86/Makefile.inc: Fix external toolchain build The sipi_vector.S just needs to be linked as relocatable so there is no need to invoke the compiler. TEST: BUILD_TIMELESS=1 has the same hashes Change-Id: I0370f1590a70cffb48c7930f6ae85956b506b09c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37193 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index bbe5545dc3..2f789f7581 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -26,7 +26,7 @@ endif rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S $(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S) - $(CC_rmodules_$(ARCH-$(TARGET_STAGE)-y)) $(CFLAGS_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ + $(LD_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y))) From 6e50849b8cd88e481e5460e4333cb3f198c89d0c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 24 Mar 2020 15:39:34 -0500 Subject: [PATCH 0662/1463] mb/51nb/x210: Fix up USB ports in devicetree Add missing port definition for the mSATA/WWAN mPCIe port, set OC pin for internal ports to OC_SKIP, fix port descrption for mPCIe/WLAN port, remove USB3 definition for right type-A port as it is USB2 only. Test: insert WiFi module into WWAN port, observe BT portion detected and functional. Change-Id: Ie39b99eeb0f605ff07d57c32189fb1f4183713e4 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39808 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/51nb/x210/devicetree.cb | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index ee6e5ffd59..50d217d170 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -107,16 +107,15 @@ chip soc/intel/skylake register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) - register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # M.2-2230 USB (BT) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) # PL1 override 25W register "tdp_pl1_override" = "25" From 044b49c381fddd9c8db4d5472517057b1b70ba29 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 27 Mar 2020 15:41:30 -0500 Subject: [PATCH 0663/1463] mb/google/glados: remove Chrome-EC defaults Chrome-EC/PD images for all glados variants need to be built from the board-specific branch, not master. Including the default board names serves no purpose and requires users to deselect the "use built-in EC firmware" in order for the board to build. Test: build google/chell with defaults Change-Id: Ic10f11337b85035068cdc4fe8147413e6b7f57ac Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39890 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/glados/Kconfig | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index bc0c67ba46..c90b2bd7bd 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -77,18 +77,6 @@ config INCLUDE_NHLT_BLOBS select NHLT_DMIC_2CH select NHLT_NAU88L25 -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "chell" if BOARD_GOOGLE_CHELL - default "glados" if BOARD_GOOGLE_GLADOS - default "" - -config EC_GOOGLE_CHROMEEC_PD_BOARDNAME - string - default "chell_pd" if BOARD_GOOGLE_CHELL - default "glados_pd" if BOARD_GOOGLE_GLADOS - default "" - config UART_FOR_CONSOLE int default 2 From de349ed45c3276f68fe690d711f995bd6db0b752 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 27 Mar 2020 03:13:55 -0500 Subject: [PATCH 0664/1463] mb/google/cyan: Clean up Kconfig Cyan has no VGA BIOS available (at least not publicly), so remove related options. Disable SoC serial output by default, since no production devices have this exposed, but leave it as a user option so it can be selected as needed (eg, for use with a Google debug servo). Change-Id: Ic079a39ca5ad0ac653b52248244b94d4bfbd08a4 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39872 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/google/cyan/Kconfig | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 94ffbc0bad..45610542e4 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -6,7 +6,6 @@ config BOARD_GOOGLE_BASEBOARD_CYAN select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP - select ENABLE_BUILTIN_COM1 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT @@ -73,23 +72,6 @@ config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -config VGA_BIOS_FILE - string - depends on VGA_BIOS - default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" - help - The C0 version of the video BIOS gets computed from this name - so that they can both be added. Only the correct one for the - system will be run. - -config VGA_BIOS_ID - string - depends on VGA_BIOS - default "8086,22b0" - help - The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded - in soc/intel/braswell/Makefile.inc as 8086,22b1 - config CBFS_SIZE hex default 0x200000 @@ -98,4 +80,10 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config CONSOLE_SERIAL + default n + +config ENABLE_BUILTIN_COM1 + default y if CONSOLE_SERIAL + endif # BOARD_GOOGLE_BASEBOARD_CYAN From 8107c81e0791897681a2269a2e324fe434713bf8 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 27 Mar 2020 03:09:21 -0500 Subject: [PATCH 0665/1463] src/device/Kconfig: Adjust Graphics init defaults Adjust the defaults for Graphics Initialization so that the "best" option for a board is selected by default. Net effect is to select RUN_FSP_GOP over VGA_ROM_RUN in cases where the platform supports GOP init and the mainboard has a VBT file included. Test: run 'make menuconfig' and check default Display Init option for google/cyan, observe RUN_FSP_GOP is default. Change-Id: I2184dbdd943d035d1682b3ae7bd8d005221434b1 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39871 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/device/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index de33b04773..64f1693e99 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -67,6 +67,9 @@ choice prompt "Graphics initialization" default NO_GFX_INIT if VGA_BIOS && PAYLOAD_SEABIOS default VGA_ROM_RUN if VGA_BIOS + default MAINBOARD_DO_NATIVE_VGA_INIT + default MAINBOARD_USE_LIBGFXINIT + default RUN_FSP_GOP if INTEL_GMA_ADD_VBT config MAINBOARD_DO_NATIVE_VGA_INIT bool "Use native graphics init" From c2e46420cc934af77391a52e7e5330b5a7e2b1f5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 23 Mar 2020 01:22:49 +0100 Subject: [PATCH 0666/1463] nb/intel/haswell: Implement proper backlight PWM config Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code. We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT. Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/intel/gma/i915_reg.h | 1 + .../slippy/variants/falco/devicetree.cb | 5 +-- .../google/slippy/variants/leon/devicetree.cb | 5 +-- .../slippy/variants/peppy/devicetree.cb | 5 +-- .../google/slippy/variants/wolf/devicetree.cb | 5 +-- src/mainboard/lenovo/t440p/devicetree.cb | 3 +- src/northbridge/intel/haswell/chip.h | 7 +++- src/northbridge/intel/haswell/gma.c | 42 +++++++++++++++---- 8 files changed, 49 insertions(+), 24 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index e0bf1427c5..38ea72a6f9 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -3580,6 +3580,7 @@ #define SOUTH_CHICKEN2 0xc2004 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) +#define LPT_PWM_GRANULARITY (1<<5) #define DPLS_EDP_PPS_FIX_DIS (1<<0) #define _FDI_RXA_CHICKEN 0xc200c diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index f2a952070e..2d076830f3 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -12,9 +12,8 @@ chip northbridge/intel/haswell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index 8951e99e39..4cf1e72d80 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -12,9 +12,8 @@ chip northbridge/intel/haswell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index 6451d95856..7bb18c09d9 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -12,9 +12,8 @@ chip northbridge/intel/haswell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 2cad23b75c..159d51a799 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -12,9 +12,8 @@ chip northbridge/intel/haswell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 1022e7764e..1f84007ec3 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.ndid" = "3" - register "gpu_cpu_backlight" = "0x12ba12ba" register "gpu_ddi_e_connected" = "1" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" @@ -12,7 +11,7 @@ chip northbridge/intel/haswell register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight" = "0x12ba12ba" + register "gpu_pch_backlight_pwm_hz" = "220" device cpu_cluster 0x0 on chip cpu/intel/haswell register "c1_acpower" = "1" diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index cfc28845b2..d7ef27df16 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -36,8 +36,11 @@ struct northbridge_intel_haswell_config { u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ - u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity; bool gpu_ddi_e_connected; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index eed6740bc3..65c5cf3e75 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -347,14 +348,39 @@ static void gma_setup_panel(struct device *dev) gtt_write(PCH_PP_DIVISOR, reg32); } - /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* Enforce the PCH PWM function, as so does Linux. + The CPU PWM controls are disabled after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* Reference clock is either 24MHz or 135MHz. We can choose + either a 16 or a 128 step increment. Use 16 if we would + have less than 100 steps otherwise. */ + const unsigned int refclock = CONFIG(INTEL_LYNXPOINT_LP) ? 24*MHz : 135*MHz; + const unsigned int hz_limit = refclock / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 |= LPT_PWM_GRANULARITY; + } else { + pwm_increment = 128; + south_chicken2 &= ~LPT_PWM_GRANULARITY; + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + printk(BIOS_INFO, + "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", + refclock / MHz, pwm_increment, pwm_period, + DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period)); + + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } /* Get display,pipeline,and DDI registers into a basic sane state */ From 9af0b15e95e074ae6a433598e8ccee5233173c88 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 27 Mar 2020 19:06:26 +0100 Subject: [PATCH 0667/1463] drivers/intel/gma: Drop unused `backlight` field Change-Id: I9d7f8337653f93f40550a3d2886fe7b3845eac69 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39879 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/drivers/intel/gma/i915.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 0ac706275a..ef3aaf5f74 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -88,7 +88,6 @@ u32 gtt_read(u32 reg); struct i915_gpu_controller_info { int use_spread_spectrum_clock; - u32 backlight; int ndid; u32 did[5]; }; From b0b25c8e9cd7950e87167a2558f4645a3479e80c Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 21 Mar 2020 20:35:12 +0100 Subject: [PATCH 0668/1463] drivers/intel/gma/acpi: Provide default definition for displays Use it wherever the standard numbers were copied to. Bit 31 is set at runtime unconditionally, so we don't need it here. Change-Id: I0d853c3b8250a2c7b2d1a91985a555e4b17ad76c Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39731 Reviewed-by: Patrick Rudolph Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/i915.h | 5 +++++ src/mainboard/apple/macbook21/devicetree.cb | 3 +-- src/mainboard/compulab/intense_pc/devicetree.cb | 5 ++--- src/mainboard/emulation/qemu-q35/mainboard.c | 7 +------ src/mainboard/google/butterfly/devicetree.cb | 3 +-- src/mainboard/google/parrot/devicetree.cb | 3 +-- src/mainboard/google/slippy/variants/falco/devicetree.cb | 3 +-- src/mainboard/google/slippy/variants/leon/devicetree.cb | 3 +-- src/mainboard/google/slippy/variants/peppy/devicetree.cb | 3 +-- src/mainboard/google/slippy/variants/wolf/devicetree.cb | 3 +-- src/mainboard/google/stout/devicetree.cb | 4 +--- src/mainboard/ibase/mb899/devicetree.cb | 3 +-- src/mainboard/intel/baskingridge/devicetree.cb | 3 +-- src/mainboard/intel/dcp847ske/devicetree.cb | 3 +-- src/mainboard/intel/emeraldlake2/devicetree.cb | 3 +-- src/mainboard/kontron/986lcd-m/devicetree.cb | 3 +-- src/mainboard/kontron/ktqm77/devicetree.cb | 3 +-- src/mainboard/lenovo/l520/devicetree.cb | 4 +--- src/mainboard/lenovo/s230u/devicetree.cb | 4 +--- src/mainboard/lenovo/t400/devicetree.cb | 4 +--- src/mainboard/lenovo/t410/devicetree.cb | 4 +--- src/mainboard/lenovo/t420/devicetree.cb | 4 +--- src/mainboard/lenovo/t420s/devicetree.cb | 4 +--- src/mainboard/lenovo/t430/devicetree.cb | 4 +--- src/mainboard/lenovo/t430s/devicetree.cb | 4 +--- src/mainboard/lenovo/t440p/devicetree.cb | 3 +-- src/mainboard/lenovo/t520/devicetree.cb | 4 +--- src/mainboard/lenovo/t530/variants/t530/devicetree.cb | 4 +--- src/mainboard/lenovo/t530/variants/w530/devicetree.cb | 4 +--- src/mainboard/lenovo/t60/devicetree.cb | 3 +-- src/mainboard/lenovo/x131e/devicetree.cb | 4 +--- src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb | 4 +--- src/mainboard/lenovo/x200/devicetree.cb | 4 +--- src/mainboard/lenovo/x201/devicetree.cb | 4 +--- src/mainboard/lenovo/x220/devicetree.cb | 4 +--- src/mainboard/lenovo/x230/devicetree.cb | 4 +--- src/mainboard/lenovo/x60/devicetree.cb | 3 +-- src/mainboard/packardbell/ms2290/devicetree.cb | 4 +--- src/mainboard/roda/rk886ex/devicetree.cb | 3 +-- src/mainboard/roda/rk9/devicetree.cb | 3 +-- src/mainboard/samsung/lumpy/devicetree.cb | 3 +-- src/mainboard/samsung/stumpy/devicetree.cb | 3 +-- 42 files changed, 47 insertions(+), 106 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index ef3aaf5f74..fc7b35ab83 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -92,6 +92,11 @@ struct i915_gpu_controller_info u32 did[5]; }; +#define GMA_STATIC_DISPLAYS(ssc) { \ + .use_spread_spectrum_clock = (ssc), \ + .ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \ +} + void drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); const struct i915_gpu_controller_info * diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 8caaa503c5..f5c25c6182 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -15,8 +15,7 @@ chip northbridge/intel/i945 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index b333245da6..20b8bed6c1 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -10,9 +10,8 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.ndid" = "3" +chip northbridge/intel/sandybridge # FIXME: check gfx + register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 1784321da0..aea6d41648 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -25,12 +25,7 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; -struct i915_gpu_controller_info gfx_controller_info = { - .ndid = 3, - .did = { - 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 - } -}; +struct i915_gpu_controller_info gfx_controller_info = GMA_STATIC_DISPLAYS(0); const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 3c08b8bb60..0c63305bf1 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 33d3544264..c39a399f0c 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort B Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index 2d076830f3..887ec4afcb 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index 4cf1e72d80..27ce945dc5 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index 7bb18c09d9..d5e797e88d 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 159d51a799..ee0accaf2e 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 089aea3bc4..a03a0a6dc7 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -15,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms # For native gfx - register "gfx.use_spread_spectrum_clock" = "0" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 78743bd453..12104e4bb0 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/i945 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on chip cpu/intel/socket_m diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index a9cfb49527..157f393454 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index b62c5dffd1..b865d1a49e 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 6da5614d3c..3b4ee6532a 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 741c47b8f9..88cf04db58 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/i945 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on chip cpu/intel/socket_m diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 8928b87988..db0c9e24f9 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on chip cpu/intel/model_206ax diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 897b52a558..93390c9112 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -1,7 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "0" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 8483a54c7d..6f4e6082d5 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -1,7 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "1" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" register "gpu_cpu_backlight" = "0x00000060" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index a61d84eba6..5886aff48c 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -1,14 +1,12 @@ chip northbridge/intel/gm45 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms register "gpu_panel_power_down_delay" = "250" # T3: 25ms register "gpu_panel_power_backlight_on_delay" = "2500" # T5: 250ms register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" device cpu_cluster 0 on chip cpu/intel/socket_p diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 064bc741d2..7f62738d2f 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -15,8 +15,7 @@ chip northbridge/intel/ironlake # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -30,7 +29,6 @@ chip northbridge/intel/ironlake register "gpu_panel_power_backlight_off_delay" = "0" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gfx.use_spread_spectrum_clock" = "1" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index eaae94c35f..5ac9cf5a96 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -13,7 +12,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 5cf3165e33..2fde40ff9d 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -12,7 +11,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 1cb38599b1..95eaa99337 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -12,7 +11,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 586e7d9a75..40c706eb0c 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -12,7 +11,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 1f84007ec3..e18f72b250 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -1,6 +1,5 @@ chip northbridge/intel/haswell - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.ndid" = "3" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_ddi_e_connected" = "1" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 296a30491f..5128d06e4b 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -13,7 +12,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index d10371fdba..cedb478573 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -13,7 +12,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 095111b3ce..be6cc7d9d0 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -13,7 +12,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 08c8fca2c6..c3d96f08de 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -15,8 +15,7 @@ chip northbridge/intel/i945 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 5f19740db3..c84d7ea87d 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" register "gpu_dp_d_hotplug" = "0x04" @@ -12,7 +11,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" register "gpu_panel_power_backlight_on_delay" = "3000" register "gpu_panel_power_backlight_off_delay" = "2000" - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index c9a83f5e0b..b3c11ea450 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -1,7 +1,5 @@ chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "1" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" register "gpu_cpu_backlight" = "0x00001155" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 818eda208d..80288bfcac 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,14 +1,12 @@ chip northbridge/intel/gm45 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms register "gpu_panel_power_down_delay" = "250" # T3: 25ms register "gpu_panel_power_backlight_on_delay" = "2500" # T5: 250ms register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 5bfbebd4be..3401708141 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -15,8 +15,7 @@ chip northbridge/intel/ironlake # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse @@ -31,7 +30,6 @@ chip northbridge/intel/ironlake register "gpu_panel_power_backlight_off_delay" = "2500" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gfx.use_spread_spectrum_clock" = "1" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 8749b5cfd5..bfb9da355d 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -13,7 +12,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 52c5d329dc..e34734c4c3 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -13,7 +12,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gfx.use_spread_spectrum_clock" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2ebd981950..fbe13d8331 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -15,8 +15,7 @@ chip northbridge/intel/i945 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 52be51bbf1..fb26392a14 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -15,8 +15,7 @@ chip northbridge/intel/ironlake # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_dp_b_hotplug" = "0x04" register "gpu_dp_c_hotplug" = "0x04" @@ -31,7 +30,6 @@ chip northbridge/intel/ironlake register "gpu_panel_power_backlight_off_delay" = "3000" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gfx.use_spread_spectrum_clock" = "0" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 5c868b75cd..af250e768d 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -15,8 +15,7 @@ chip northbridge/intel/i945 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on chip cpu/intel/socket_m diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index ddb2ad72a9..39650537db 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/gm45 # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 device lapic 0 on end diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 1a4ecfdd54..15bff4bcc9 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 034e166ca1..8e79b393e2 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" From 5d841e6a176263bd9caa478e6e4ad464d1b9f489 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 26 Mar 2020 13:41:09 -0500 Subject: [PATCH 0669/1463] mb/google/glados: disable serial console by default Glados boards do not have an exposed serial port outside of the servo interface. Set board Kconfig so that a default built image with Tianocore payload is bootable and doesn't hang due to trying to send data over a non-existant serial port. Test: build/boot google/chell with board defaults Change-Id: Ifad6f805e66438e2c436d9fa235d9be2ecf69179 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39863 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/mainboard/google/glados/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index c90b2bd7bd..d0ff3776e0 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -81,4 +81,8 @@ config UART_FOR_CONSOLE int default 2 +config CONSOLE_SERIAL + bool + default n + endif From 1e40a115778865e60a13cb71fdf18eb3ddf1751f Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 25 Mar 2020 13:37:07 +0800 Subject: [PATCH 0670/1463] mb/google/hatch/var/kindred: set wifi sar for kled Enable wifi sar feature and set wifi sar name for kled sku. BUG=b:152277272 TEST=emerge-hatch coreboot chromeos-bootimage and verify wifi SAR load by sku-id Change-Id: I9ee242773fd05cc2bcd7bde07da8176022827677 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/39813 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- src/mainboard/google/hatch/variants/kindred/variant.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 72bed92398..ce9df8a49b 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -16,6 +16,7 @@ #include #include #include +#include void variant_devtree_update(void) { @@ -46,3 +47,13 @@ void variant_devtree_update(void) cfg->satapwroptimize = 0; } } + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id = google_chromeec_get_board_sku(); + + if (sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4) + filename = "wifi_sar-kled.hex"; + return filename; +} From d72cca0c44bc944fdfbdcbc4b264ba0c3727649b Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 25 Mar 2020 11:42:12 -0700 Subject: [PATCH 0671/1463] mb/tglrvp: Add GPE configuration Update the GPE configuration for dw0, dw1 and dw2. BUG=None TEST=build and boot tglrvp Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 8 ++++++++ .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 23737c3070..8fd9087c7f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -4,6 +4,14 @@ chip soc/intel/tigerlake device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index f2e5510147..4ff35cc437 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -4,6 +4,14 @@ chip soc/intel/tigerlake device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" From d47afe90ef438cbeb4f60753d8674db2217d72b2 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 26 Mar 2020 12:29:35 -0600 Subject: [PATCH 0672/1463] util/sconfig: emit NULL sibling fields It's helpful to see the sibling field, even when it's NULL, when debugging the static.c output from a devictree.cb file. Ensure the NULL fields are emitted for fullness. Change-Id: Ib6d5b8164769a6512e762d5a525c7df1f429c866 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/39862 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- util/sconfig/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index d784642ae2..b48f992672 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -832,6 +832,8 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next fprintf(fil, "\t.link_list = NULL,\n"); if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); + else + fprintf(fil, "\t.sibling = NULL,\n"); fprintf(fil, "#if !DEVTREE_EARLY\n"); for (pin = 0; pin < 4; pin++) { if (ptr->pci_irq_info[pin].ioapic_irq_pin > 0) From bc8373830128ff2991c1a8e9ff3e4255deefe746 Mon Sep 17 00:00:00 2001 From: Frank Wu Date: Fri, 13 Mar 2020 16:41:10 +0800 Subject: [PATCH 0673/1463] volteer: Create halvor variant Create the halvor variant of the volteer reference board by copying the template files to a new directory named for the variant. BUG=b:151399850 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_HALVOR Signed-off-by: Frank Wu Change-Id: If4d3417ba55d56af441c99d949a196328d7a1951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39667 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: EricR Lai Reviewed-by: Paul Fagerburg Reviewed-by: Nick Vaccaro --- src/mainboard/google/volteer/Kconfig | 2 + src/mainboard/google/volteer/Kconfig.name | 8 +++- .../volteer/variants/halvor/Makefile.inc | 8 ++++ .../google/volteer/variants/halvor/gpio.c | 37 +++++++++++++++++++ .../variants/halvor/include/variant/ec.h | 9 +++++ .../variants/halvor/include/variant/gpio.h | 11 ++++++ .../volteer/variants/halvor/overridetree.cb | 4 ++ 7 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/volteer/variants/halvor/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/halvor/gpio.c create mode 100644 src/mainboard/google/volteer/variants/halvor/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h create mode 100644 src/mainboard/google/volteer/variants/halvor/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 5bc487686e..54a8fecb4c 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -55,6 +55,7 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string + default "Halvor" if BOARD_GOOGLE_HALVOR default "Ripto" if BOARD_GOOGLE_RIPTO default "Volteer" if BOARD_GOOGLE_VOLTEER @@ -68,6 +69,7 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR string + default "halvor" if BOARD_GOOGLE_HALVOR default "ripto" if BOARD_GOOGLE_RIPTO default "volteer" if BOARD_GOOGLE_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d60dfb4807..596894effb 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,9 +1,13 @@ comment "Volteer" -config BOARD_GOOGLE_VOLTEER - bool "-> Volteer" +config BOARD_GOOGLE_HALVOR + bool "-> Halvor" select BOARD_GOOGLE_BASEBOARD_VOLTEER config BOARD_GOOGLE_RIPTO bool "-> Ripto" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOLTEER + bool "-> Volteer" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc new file mode 100644 index 0000000000..a115fccb1f --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +SPD_SOURCES = + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c new file mode 100644 index 0000000000..6c4fb52f01 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/halvor/include/variant/ec.h b/src/mainboard/google/volteer/variants/halvor/include/variant/ec.h new file mode 100644 index 0000000000..33e79711f6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/include/variant/ec.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h b/src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h new file mode 100644 index 0000000000..55725ad59a --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb new file mode 100644 index 0000000000..75422d80bb --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/tigerlake + device domain 0 on + end +end From fc932374a2860addbdf00dc3bd141b556508b8f3 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Wed, 11 Mar 2020 14:07:23 -0700 Subject: [PATCH 0674/1463] soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3 FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3. Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping. The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports. The TGL EDS describes this setting and what each bit represents. Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-C display should work regardless of Type-C cable orientation. Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459 Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 9 +++++++++ src/soc/intel/tigerlake/fsp_params_tgl.c | 1 + 2 files changed, 10 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 1d4bd5fa5a..64c13ce22e 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -231,6 +231,15 @@ struct soc_intel_tigerlake_config { uint8_t TcssXhciEn; uint8_t TcssXdciEn; + /* + * SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. + * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. + * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines + * on the motherboard. + */ + uint16_t TcssAuxOri; + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index a8be407d23..8e9787b12b 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -104,6 +104,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->PeiGraphicsPeimInit = 0; + params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000; From 91dddd47b3e5a34124e34222ab3f2a1f00ce9246 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Wed, 11 Mar 2020 16:16:16 -0700 Subject: [PATCH 0675/1463] tgl boards: Configure retimer Aux orientation In order to create a working baseline all ports are being set to have retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not misconfigure the ports. Volteer will need some additional changes after this is implemented to account for ports that do not have a retimer. This setting is in the process of being documented in the TGL EDS and we can update once it is fully understood what this setting is changing on the SOC side. BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on Volteer, Connecting Type-c display should work regardless of Type-c cable orientation. Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3 Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460 Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 + src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 +++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 +++ 3 files changed, 7 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 6be69fe2ee..361e563cab 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -127,6 +127,7 @@ chip soc/intel/tigerlake # TCSS USB3 register "TcssXhciEn" = "1" + register "TcssAuxOri" = "0" # DP port register "DdiPortAConfig" = "1" # eDP diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 8fd9087c7f..6cef4f84a6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -103,6 +103,9 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoPci, }" + # TCSS USB3 + register "TcssAuxOri" = "0" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 4ff35cc437..c5cc800224 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -99,6 +99,9 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoPci, }" + # TCSS USB3 + register "TcssAuxOri" = "0" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" From 97bd2a7f33a784b63b8ede4efc23f39d4dfce37b Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 17 Feb 2020 13:17:19 -0700 Subject: [PATCH 0676/1463] soc/amd/picasso: Add helper functions for finding SOC type We're running into more and more situations where we need to tell one SOC type from another, and instead of rewriting them every time, just add some helper functions to the picasso SOC directory. Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/2051514 Reviewed-on: https://chromium-review.googlesource.com/2060904 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Martin Roth Reviewed-by: Eric Peers Reviewed-by: Raul E Rangel Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/soc/amd/picasso/Makefile.inc | 2 ++ src/soc/amd/picasso/include/soc/soc_util.h | 8 ++++++ src/soc/amd/picasso/soc_util.c | 33 ++++++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 src/soc/amd/picasso/include/soc/soc_util.h create mode 100644 src/soc/amd/picasso/soc_util.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 48f65078ac..6b32c6e8e2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -43,6 +43,7 @@ romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += soc_util.c verstage-y += gpio.c verstage-y += i2c.c @@ -74,6 +75,7 @@ ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c +ramstage-y += soc_util.c all-y += cfg_util.c all-y += reset.c diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h new file mode 100644 index 0000000000..be05d9f9af --- /dev/null +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +int soc_is_pollock(void); +int soc_is_dali(void); +int soc_is_picasso(void); +int soc_is_raven2(void); +int soc_is_zen_plus(void); diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c new file mode 100644 index 0000000000..893ff2570f --- /dev/null +++ b/src/soc/amd/picasso/soc_util.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +int soc_is_pollock(void) +{ + return soc_is_zen_plus() && CONFIG(AMD_FT5); +} + +int soc_is_dali(void) +{ + return soc_is_raven2() && CONFIG(AMD_FP5); +} + +int soc_is_picasso(void) +{ + return soc_is_zen_plus() && CONFIG(AMD_FP5); +} + +int soc_is_raven2(void) +{ + /* mask lower model number nibble and stepping */ + return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8; +} + +int soc_is_zen_plus(void) +{ + /* mask lower model number nibble and stepping */ + return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8; +} From 3a1a037231ddb5cdc03d0e147c2335de0f1c8ad6 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Mon, 9 Mar 2020 18:20:07 -0700 Subject: [PATCH 0677/1463] mb/google/deltaur: add deltaur mainboard initial support Created a new Google baseboard using Tiger Lake named deltaur, taking volteer as a starting point. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/deltaur/Kconfig | 83 +++++++++++++ src/mainboard/google/deltaur/Kconfig.name | 9 ++ src/mainboard/google/deltaur/Makefile.inc | 30 +++++ src/mainboard/google/deltaur/board_info.txt | 6 + src/mainboard/google/deltaur/bootblock.c | 26 ++++ src/mainboard/google/deltaur/chromeos.c | 117 ++++++++++++++++++ src/mainboard/google/deltaur/chromeos.fmd | 48 +++++++ src/mainboard/google/deltaur/dsdt.asl | 51 ++++++++ src/mainboard/google/deltaur/ec.c | 14 +++ src/mainboard/google/deltaur/mainboard.c | 35 ++++++ src/mainboard/google/deltaur/smihandler.c | 26 ++++ .../deltaur/variants/baseboard/Makefile.inc | 11 ++ .../deltaur/variants/baseboard/devicetree.cb | 6 + .../google/deltaur/variants/baseboard/gpio.c | 47 +++++++ .../variants/baseboard/include/baseboard/ec.h | 14 +++ .../baseboard/include/baseboard/gpio.h | 13 ++ .../baseboard/include/baseboard/variants.h | 24 ++++ .../deltaur/variants/deltan/Makefile.inc | 9 ++ .../google/deltaur/variants/deltan/gpio.c | 31 +++++ .../variants/deltan/include/variant/ec.h | 15 +++ .../variants/deltan/include/variant/gpio.h | 14 +++ .../deltaur/variants/deltan/overridetree.cb | 6 + .../deltaur/variants/deltaur/Makefile.inc | 9 ++ .../google/deltaur/variants/deltaur/gpio.c | 31 +++++ .../variants/deltaur/include/variant/ec.h | 15 +++ .../variants/deltaur/include/variant/gpio.h | 14 +++ .../deltaur/variants/deltaur/overridetree.cb | 6 + 27 files changed, 710 insertions(+) create mode 100644 src/mainboard/google/deltaur/Kconfig create mode 100644 src/mainboard/google/deltaur/Kconfig.name create mode 100644 src/mainboard/google/deltaur/Makefile.inc create mode 100644 src/mainboard/google/deltaur/board_info.txt create mode 100644 src/mainboard/google/deltaur/bootblock.c create mode 100644 src/mainboard/google/deltaur/chromeos.c create mode 100644 src/mainboard/google/deltaur/chromeos.fmd create mode 100644 src/mainboard/google/deltaur/dsdt.asl create mode 100644 src/mainboard/google/deltaur/ec.c create mode 100644 src/mainboard/google/deltaur/mainboard.c create mode 100644 src/mainboard/google/deltaur/smihandler.c create mode 100644 src/mainboard/google/deltaur/variants/baseboard/Makefile.inc create mode 100644 src/mainboard/google/deltaur/variants/baseboard/devicetree.cb create mode 100644 src/mainboard/google/deltaur/variants/baseboard/gpio.c create mode 100644 src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h create mode 100644 src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h create mode 100644 src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h create mode 100644 src/mainboard/google/deltaur/variants/deltan/Makefile.inc create mode 100644 src/mainboard/google/deltaur/variants/deltan/gpio.c create mode 100644 src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h create mode 100644 src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h create mode 100644 src/mainboard/google/deltaur/variants/deltan/overridetree.cb create mode 100644 src/mainboard/google/deltaur/variants/deltaur/Makefile.inc create mode 100644 src/mainboard/google/deltaur/variants/deltaur/gpio.c create mode 100644 src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h create mode 100644 src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h create mode 100644 src/mainboard/google/deltaur/variants/deltaur/overridetree.cb diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig new file mode 100644 index 0000000000..dcbe5ecbad --- /dev/null +++ b/src/mainboard/google/deltaur/Kconfig @@ -0,0 +1,83 @@ +config BOARD_GOOGLE_BASEBOARD_DELTAUR + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_ISH + select DRIVERS_SPI_ACPI + select EC_GOOGLE_WILCO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_TIGERLAKE + select SYSTEM_TYPE_LAPTOP + +if BOARD_GOOGLE_BASEBOARD_DELTAUR + +config CHROMEOS + bool + default y + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + +config DIMM_SPD_SIZE + int + default 512 + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config DRIVER_TPM_I2C_BUS + hex + default 0x3 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_DIR + string + default "google/deltaur" + +config MAINBOARD_FAMILY + string + default "Google_Deltaur" + +config MAINBOARD_PART_NUMBER + string + default "Deltan" if BOARD_GOOGLE_DELTAN + default "Deltaur" if BOARD_GOOGLE_DELTAUR + +config MAX_CPUS + int + default 8 + +config TPM_TIS_ACPI_INTERRUPT + int + default 23 # GPE0_DW0_23 (GPP_C23) + +config UART_FOR_CONSOLE + int + default 2 + +config VARIANT_DIR + string + default "deltan" if BOARD_GOOGLE_DELTAN + default "deltaur" if BOARD_GOOGLE_DELTAUR + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_DELTAUR diff --git a/src/mainboard/google/deltaur/Kconfig.name b/src/mainboard/google/deltaur/Kconfig.name new file mode 100644 index 0000000000..5c4c12b479 --- /dev/null +++ b/src/mainboard/google/deltaur/Kconfig.name @@ -0,0 +1,9 @@ +comment "Deltaur" + +config BOARD_GOOGLE_DELTAN + bool "-> Deltan" + select BOARD_GOOGLE_BASEBOARD_DELTAUR + +config BOARD_GOOGLE_DELTAUR + bool "-> Deltaur" + select BOARD_GOOGLE_BASEBOARD_DELTAUR diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc new file mode 100644 index 0000000000..a913c75da2 --- /dev/null +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-y += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += ec.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-y += ec.c + +smm-y += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/google/deltaur/board_info.txt b/src/mainboard/google/deltaur/board_info.txt new file mode 100644 index 0000000000..897a63b04b --- /dev/null +++ b/src/mainboard/google/deltaur/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Deltaur +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/deltaur/bootblock.c b/src/mainboard/google/deltaur/bootblock.c new file mode 100644 index 0000000000..c2cffd064f --- /dev/null +++ b/src/mainboard/google/deltaur/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +static void early_config_gpio(void) +{ + const struct pad_config *early_gpio_table; + size_t num_gpios = 0; + + early_gpio_table = variant_early_gpio_table(&num_gpios); + gpio_configure_pads(early_gpio_table, num_gpios); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); + wilco_ec_early_init(); +} diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c new file mode 100644 index 0000000000..128378828a --- /dev/null +++ b/src/mainboard/google/deltaur/chromeos.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +enum rec_mode_state { + REC_MODE_UNINITIALIZED, + REC_MODE_NOT_REQUESTED, + REC_MODE_REQUESTED, +}; + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +static int cros_get_gpio_value(int type) +{ + const struct cros_gpio *cros_gpios; + size_t i, num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + for (i = 0; i < num_gpios; i++) { + const struct cros_gpio *gpio = &cros_gpios[i]; + if (gpio->type == type) { + int state = gpio_get(gpio->gpio_num); + if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) + return !state; + else + return state; + } + } + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *cros_gpios; + size_t num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + chromeos_acpi_gpio_generate(cros_gpios, num_gpios); +} + +int get_write_protect_state(void) +{ + return cros_get_gpio_value(CROS_GPIO_WP); +} + +int get_recovery_mode_switch(void) +{ + static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; + enum rec_mode_state state = REC_MODE_NOT_REQUESTED; + uint8_t cr50_state = 0; + + /* Check cached state, since TPM will only tell us the first time */ + if (saved_rec_mode != REC_MODE_UNINITIALIZED) + return saved_rec_mode == REC_MODE_REQUESTED; + + /* + * Read one-time recovery request from cr50 in verstage only since + * the TPM driver won't be set up in time for other stages like romstage + * and the value from the TPM would be wrong anyway since the verstage + * read would have cleared the value on the TPM. + * + * The TPM recovery request is passed between stages through vboot data + * or cbmem depending on stage. + */ + if (ENV_VERSTAGE && + tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && + cr50_state) + state = REC_MODE_REQUESTED; + + /* Read state from the GPIO controlled by servo. */ + if (cros_get_gpio_value(CROS_GPIO_REC)) + state = REC_MODE_REQUESTED; + + /* Store the state in case this is called again in verstage. */ + saved_rec_mode = state; + + return state == REC_MODE_REQUESTED; +} + +int get_lid_switch(void) +{ + return 1; +} + +void mainboard_prepare_cr50_reset(void) +{ + /* Ensure system powers up after CR50 reset */ + if (ENV_RAMSTAGE) + pmc_soc_set_afterg3_en(true); +} diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd new file mode 100644 index 0000000000..d0cf8e92f8 --- /dev/null +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -0,0 +1,48 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x604000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_ME@0x101000 0x4ff000 + SI_PDR(PRESERVE)@0x600000 0x4000 + } + SI_BIOS@0x604000 0x19fc000 { + RW_DIAG@0x0 0x10cc000 { + RW_LEGACY(CBFS)@0x0 0x10bc000 + DIAG_NVRAM@0x10bc000 0x10000 + } + RW_SECTION_A@0x10cc000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x134c000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x15cc000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + WP_RO@0x15fc000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3ec000 + } + } + } +} diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl new file mode 100644 index 0000000000..b6bc8e4248 --- /dev/null +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include "variant/ec.h" +#include "variant/gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include + + /* global NVS and variables */ + #include + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + /* Chrome OS specific */ + #include + + /* VPD support */ + #include + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } + + #include +} diff --git a/src/mainboard/google/deltaur/ec.c b/src/mainboard/google/deltaur/ec.c new file mode 100644 index 0000000000..5dd7237bdd --- /dev/null +++ b/src/mainboard/google/deltaur/ec.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c new file mode 100644 index 0000000000..eca5ee8e78 --- /dev/null +++ b/src/mainboard/google/deltaur/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *base_pads; + const struct pad_config *override_pads; + size_t base_num, override_num; + + base_pads = variant_base_gpio_table(&base_num); + override_pads = variant_override_gpio_table(&override_num); + + gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/deltaur/smihandler.c b/src/mainboard/google/deltaur/smihandler.c new file mode 100644 index 0000000000..fc68a22a52 --- /dev/null +++ b/src/mainboard/google/deltaur/smihandler.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +void mainboard_smi_espi_handler(void) +{ + wilco_ec_smi_espi(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + wilco_ec_smi_sleep(slp_typ); +} + +int mainboard_smi_apmc(u8 apmc) +{ + wilco_ec_smi_apmc(apmc); + return 0; +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc new file mode 100644 index 0000000000..937cb4628f --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc @@ -0,0 +1,11 @@ +## +## This file is part of the coreboot project. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +bootblock-y += gpio.c + +ramstage-y += gpio.c + +verstage-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..a4031622ef --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device cpu_cluster 0 on + device lapic 0 on end + end +end diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c new file mode 100644 index 0000000000..3951ce0b5d --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *__weak variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..3825cc8824 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + + + + + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..8411900243 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,13 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include + + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..1d8a934ecc --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_base_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_override_gpio_table(size_t *num); + +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc new file mode 100644 index 0000000000..ea0d5f0157 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc @@ -0,0 +1,9 @@ +## +## This file is part of the coreboot project. +## +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/deltan/gpio.c b/src/mainboard/google/deltaur/variants/deltan/gpio.c new file mode 100644 index 0000000000..30315bbc2e --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/gpio.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h new file mode 100644 index 0000000000..7044eebf37 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#endif diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h new file mode 100644 index 0000000000..a1e37894e8 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc new file mode 100644 index 0000000000..ea0d5f0157 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc @@ -0,0 +1,9 @@ +## +## This file is part of the coreboot project. +## +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/deltaur/gpio.c b/src/mainboard/google/deltaur/variants/deltaur/gpio.c new file mode 100644 index 0000000000..30315bbc2e --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/gpio.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h new file mode 100644 index 0000000000..7044eebf37 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#endif diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h new file mode 100644 index 0000000000..a1e37894e8 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/deltaur/variants/deltaur/overridetree.cb b/src/mainboard/google/deltaur/variants/deltaur/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end From d8bff383c2c1ed40a03d664db25020197b67017c Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 19 Mar 2020 12:19:38 -0600 Subject: [PATCH 0678/1463] mb/google/deltaur: Add initial GPIO configuration This configuration sets up all of the GPIO pads for the first rev of the board. BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a Signed-off-by: Tim Wawrzynczak Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/deltaur/chromeos.c | 2 +- .../google/deltaur/variants/baseboard/gpio.c | 459 +++++++++++++++++- .../baseboard/include/baseboard/gpio.h | 29 +- 3 files changed, 468 insertions(+), 22 deletions(-) diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 128378828a..5a0c481b06 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -17,7 +18,6 @@ #include #include - enum rec_mode_state { REC_MODE_UNINITIALIZED, REC_MODE_NOT_REQUESTED, diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 3951ce0b5d..a67dd8cb4c 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -4,18 +4,400 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include -#include +#include +#include +#include -/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { + /* A0 thru A6 are ESPI, configured elsewhere */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : GPP_A7 ==> CNVI_EN# */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : GPP_A8 ==> CNV_RF_RESET# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + /* A9 : GPP_A9 ==> CLKREQ_CNV#_1P8 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + /* A10 : GPP_A10 ==> TOUCH_SCREEN_RST# */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : GPP_A12 ==> M2280_PCIE_SATA# */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A14 : GPP_A14 ==> USB_OC1# */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : GPP_A15 ==> USB_OC2# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : GPP_A16 ==> USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : GPP_A17 ==> NC */ + PAD_NC(GPP_A17, NONE), + /* A18 : GPP_A18 ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : GPP_A19 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : GPP_A20 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : GPP_A21 ==> 3.3V_CAM_EN# */ + PAD_CFG_GPO(GPP_A21, 0, PLTRST), + /* A22 : GPP_A22 ==> KB_DET# */ + PAD_CFG_GPI(GPP_A22, NONE, PLTRST), + /* A23 : GPP_A23 ==> RECOVERY# */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP), -}; + /* B0 : GPP_B0 ==> CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : GPP_B1 ==> CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : GPP_B2 ==> VRALERT_L */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : GPP_B3 ==> TOUCH_SCREEN_PD# */ + PAD_CFG_GPO(GPP_B3, 0, PLTRST), + /* B4 : GPP_B4 ==> TOUCH_SCREEN_DET# */ + PAD_CFG_GPI(GPP_B4, NONE, DEEP), + /* B5 : GPP_B5 ==> ISH_I2C0_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : GPP_B6 ==> ISH_I2C0_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : GPP_B7 ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : GPP_B8 ==> NC */ + PAD_NC(GPP_B8, NONE), + /* B9 : GPP_B9 ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : GPP_B10 ===> NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : GPP_B11 ==> TBT_I2C_INT# */ + PAD_CFG_GPI_APIC(GPP_B11, NONE, PLTRST, LEVEL, INVERT), + /* B12 : GPP_B12 ==> SIO_SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PCH_PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : GPP_B14 ==> SPKR (PIN STRAP, Top Swap Override) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* B15 : GPP_B15 ==> SPK_DET0# */ + PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + /* B16 : GPP_B16 ==> ONE_DIMM# */ + PAD_CFG_GPI(GPP_B16, NONE, PLTRST), + /* B17 : GPP_B17 ==> HOST_SD_WP# */ + PAD_CFG_GPO(GPP_B17, 0, PLTRST), + /* B18 : GPP_B18 ==> NRB_BIT (PIN STRAP, No Reboot) */ + PAD_NC(GPP_B18, NONE), + /* B19 : GPP_B19 ==> D3_RST# */ + PAD_CFG_GPO(GPP_B19, 0, DEEP), + /* B20 : GPP_B20 ==> LCD_CBL_DET# */ + PAD_CFG_GPI(GPP_B20, NONE, PLTRST), + /* B21 : GPP_B21 ==> PCH_TOUCH_SCREEN_EN */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + /* B22 : GPP_B22 ==> NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : GPP_B23 ==> NC (PIN STRAP, CPUNSSC frequency) */ + PAD_NC(GPP_B23, NONE), -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { + /* C0 : GPP_C0 ==> MEM_SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : GPP_C1 ==> MEM_SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2 : GPP_C2 ==> NC (PIN STRAP, TLS Confidentiality) */ + PAD_NC(GPP_C2, NONE), + /* C3 : GPP_C3 ==> SML0_SMBCLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : GPP_C4 ==> SML0_SMBDATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : GPP_C5 ==> NC (PIN STRAP, Boot Strap 0) */ + PAD_NC(GPP_C5, NONE), + /* C6 : GPP_C6 ==> SML1_SMBCLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7 : GPP_C7 ==> SML1_SMBDATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* C8 : GPP_C8 ==> WWAN_FULL_POWER_EN */ + PAD_CFG_GPO(GPP_C8, 1, DEEP), + /* C9 : GPP_C9 ==> SBIOS_TX */ + PAD_CFG_GPO(GPP_C9, 0, PLTRST), + /* C10 : GPP_C10 ==> NC */ + PAD_NC(GPP_C10, NONE), + /* C11 : GPP_C11 ==> NC */ + PAD_NC(GPP_C11, NONE), + /* C12 : GPP_C12 ==> NC */ + PAD_NC(GPP_C12, NONE), + /* C13 : GPP_C13 ==> PCH_SSD_PWR_EN */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C14 : GPP_C14 ==> NC */ + PAD_NC(GPP_C14, NONE), + /* C15 : GPP_C15 ==> NC */ + PAD_NC(GPP_C15, NONE), + /* C16 : GPP_C16 ==> I2C0_SDA_TS */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : GPP_C17 ==> I2C0_SCL_TS */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : GPP_C18 ==> I2C1_SDA_TP */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : GPP_C19 ==> I2C1_SCL_TP */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : GPP_C22 ==> H1_FLASH_WP */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* C23 : GPP_C23 ==> H1_PCH_INT# */ + PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT), + /* D0 : GPP_D0 ==> ISH_ACC1_INT */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + /* D1 : GPP_D1 ==> ISH_ACC2_INT */ + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + /* D2 : GPP_D2 ==> ISH_TABLE_MODE# */ + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + /* D3 : GPP_D3 ==> ISH_ALS_INT# */ + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + /* D4 : GPP_D4 ==> RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D5 : GPP_D5 ==> CLKREQ_PCIE#0 */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : GPP_D6 ==> CLKREQ_PCIE#1 */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : GPP_D7 ==> CLKREQ_PCIE#2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : GPP_D8 ==> CLKREQ_PCIE#3 */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : GPP_D9 ==> TBT_2_LSX_TX */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + /* D10 : GPP_D10 ==> TBT_2_LSX_RX */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + /* D11 : GPP_D11 ==> TBT_3_LSX_TX */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), + /* D12 : GPP_D12 ==> TBT_3_LSX_RX */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF4), + /* D13 : GPP_D13 ==> SML0B_SMLDATA */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* D14 : GPP_D14 ==> SML0B_SMLCLK */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), + /* D15 : GPP_D15 ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : GPP_D16 ==> SML0BALERT# */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* D17 : GPP_D17 ==> ISH_NB_MODE# */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : GPP_D18 ==> ISH_LID_CL#_NB */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* D19 : GPP_D19 ==> NC */ + PAD_NC(GPP_D19, NONE), + + /* E0 : GPP_E0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : GPP_E1 ==> TOUCH_SCREEN_INT# */ + PAD_CFG_GPI_APIC(GPP_E1, NONE, PLTRST, LEVEL, INVERT), + /* E2 : GPP_E2 ==> MEDIACARD_IRQ# */ + PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, LEVEL, INVERT), + /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + /* E4 : GPP_E4 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : GPP_E5 ==> M2280_DEVSLP */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : GPP_E6 ==> (PIN STRAP, Reserved) */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> PCH_TOUCHPAD_INTR# */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E7, NONE, PLTRST, LEVEL, INVERT), + /* E8 : GPP_E8 ==> SECURE_BIO */ + PAD_CFG_GPO(GPP_E8, 0, PLTRST), + /* E9 : GPP_E9 ==> OC0# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : GPP_E10 ==> HDMI_PD# */ + PAD_CFG_GPO(GPP_E10, 1, DEEP), + /* E11 : GPP_E11 ==> VPRO_DET# */ + PAD_CFG_GPI(GPP_E11, NONE, PLTRST), + /* E12 : GPP_E12 ==> RTC_DET# */ + PAD_CFG_GPI(GPP_E12, NONE, PLTRST), + /* E13 : GPP_E13 ==> TBT_DET# */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E14 : GPP_E14 ==> EPD_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : GPP_E15 ==> ISH_LID_CL#_TAB */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + /* E16 : GPP_E16 ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : GPP_E17 ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : GPP_E18 ==> TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : GPP_E19 ==> TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : GPP_E20 ==> TBT_LSX1_TXD */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : GPP_E21 ==> TBT_LSX1_RXD */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : GPP_E22 ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : GPP_E23 ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F0 : GPP_F0 ==> BRI_DT_1P8 */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : GPP_F1 ==> CNV_BRI_RSP_1P8 */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2 : GPP_F2 ==> CNV_RGI_DT_1P8 */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : GPP_F3 ==> CNV_RGI_RSP_1P8 */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4 : GPP_F4 ==> NC */ + PAD_NC(GPP_F4, NONE), + /* F5 : GPP_F5 ==> NC */ + PAD_NC(GPP_F5, NONE), + /* F6 : GPP_F6 ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPP_F7 ==> NC (PIN STRAP, Reserved) */ + PAD_NC(GPP_F7, NONE), + /* F8 : GPP_F8 ==> NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : GPP_F9 ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPP_F10 ==> NC (PIN STRAP, Reserved) */ + PAD_NC(GPP_F10, NONE), + /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ + PAD_CFG_GPI(GPP_F11, NONE, DEEP), + /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ + PAD_CFG_GPI(GPP_F14, NONE, DEEP), + /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */ + PAD_CFG_GPI(GPP_F15, NONE, DEEP), + /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : GPP_F17 ==> WWAN_GPIO_PERST# */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* F18 : GPP_F18 ==> WWAN_GPIO_WAKE# */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : GPP_F19 ==> CAM_MIC_CBL_DET# */ + PAD_CFG_GPI(GPP_F19, NONE, PLTRST), + /* F20 : GPP_F20 ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : GPP_F21 ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), + /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), + /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ + PAD_CFG_GPI(GPP_H5, NONE, DEEP), + /* H6 : GPP_H6 ==> SPK_DET1 */ + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), + /* H7 : GPP_H7 ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* H12 : GPP_H12 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13 ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14 ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : GPP_H15 ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : GPP_H16 ==> CPU_DPB_CTRL_CLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : GPP_H17 ==> CPU_DPB_CTRL_DATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : GPP_H19 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : GPP_H20 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : GPP_H21 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : GPP_H22 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : GPP_H23 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R0 : GPP_R0 ==> HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* R1 : GPP_R1 ==> HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), + /* R2 : GPP_R2 ==> HDA_SDO (PIN STRAP, Flash Descriptor Security Override */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), + /* R3 : GPP_R3 ==> HDA_SDIO */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), + /* R4 : GPP_R4 ==> HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* R5 : GPP_R5 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : GPP_R6 ==> SD_PWR_EN1 */ + PAD_CFG_GPO(GPP_R6, 0, PLTRST), + /* R7 : GPP_R7 ==> SD_PWR_EN2 */ + PAD_CFG_GPO(GPP_R7, 0, PLTRST), + + /* S0 : GPP_S0 ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : GPP_S1 ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : GPP_S2 ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : GPP_S3 ==> NC */ + PAD_NC(GPP_S3, NONE), + /* S4 : GPP_S4 ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : GPP_S5 ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : GPP_S6 ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : GPP_S7 ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD0: GPD0 ==> PCH_BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: GPD1 ==> AC_PRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: GPD2 ==> LAN_WAKE# */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: GPD3 ==> SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + /* GPD4: GPD4 ==> SIO_SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: GPD5 ==> SIO_SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: GPD6 ==> SIO_SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7 ==> PCH_TBT_PERST# (PIN STRAP, Reserved) */ + PAD_CFG_GPO(GPD7, 0, PLTRST), + /* GPD8: GPD8 ==> SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: GPD9 ==> SIO_SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: GPD10 ==> SIO_SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: GPD11 ==> PM_LANPHY_EN */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_base_gpio_table(size_t *num) @@ -24,20 +406,47 @@ const struct pad_config *__weak variant_base_gpio_table(size_t *num) return gpio_table; } -const struct pad_config *__weak variant_override_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} - -const struct pad_config *__weak variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} +/* GPIO pads configured in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A23 : GPP_A23 ==> RECOVERY# */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP), + /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : GPP_C22 ==> H1_FLASH_WP */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* C23 : GPP_C23 ==> H1_PCH_INT# */ + PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT), + /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ + PAD_CFG_GPI(GPP_F11, NONE, DEEP), + /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ + PAD_CFG_GPI(GPP_F14, NONE, DEEP), + /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */ + PAD_CFG_GPI(GPP_F15, NONE, DEEP), + /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), + /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ + PAD_CFG_GPI(GPP_H5, NONE, DEEP), + /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* GPD3: GPD3 ==> SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +}; static const struct cros_gpio cros_gpios[] = { - + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) @@ -45,3 +454,17 @@ const struct cros_gpio *__weak variant_cros_gpios(size_t *num) *num = ARRAY_SIZE(cros_gpios); return cros_gpios; } + +/* Weak implementation of overrides */ +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +/* Weak implementation of early gpio */ +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index 8411900243..e6092b6123 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -4,10 +4,33 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H +#include #include +/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_C22 -#endif /* BASEBOARD_GPIO_H */ +/* Recovery mode */ +#define GPIO_REC_MODE GPP_A23 + +/* DDR channel enable pin */ +#define DDR_CHA_EN GPP_H4 +#define DDR_CHB_EN GPP_H5 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F11 +#define GPIO_MEM_CONFIG_1 GPP_F12 +#define GPIO_MEM_CONFIG_2 GPP_F13 +#define GPIO_MEM_CONFIG_3 GPP_F14 +#define GPIO_MEM_CONFIG_4 GPP_F15 + + +const struct pad_config *override_gpio_table(size_t *num); +const struct pad_config *override_early_gpio_table(size_t *num); +struct cros_gpio; +const struct cros_gpio *override_cros_gpios(size_t *num); + +#endif From 654d9d6b36765408d507a22d49e142b331492891 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 19 Mar 2020 13:56:21 -0600 Subject: [PATCH 0679/1463] mb/google/deltaur: Provide initial devicetree This initial devicetree attempts to correctly configure the status of each PCI device. Not all required drivers are instantiated, nor are all of the SoC options fully selected yet. PCIe root ports are enabled and clocks are assigned. USB ports are assigned. BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a Signed-off-by: Tim Wawrzynczak Change-Id: I911ec08b0db3647d131113a138fb74a55612fd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39678 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/deltaur/Kconfig | 1 + .../deltaur/variants/baseboard/devicetree.cb | 332 ++++++++++++++++++ 2 files changed, 333 insertions(+) diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index dcbe5ecbad..6b4af9b592 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR select DRIVERS_I2C_GENERIC select DRIVERS_INTEL_ISH select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index a4031622ef..a63d66c834 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -3,4 +3,336 @@ chip soc/intel/tigerlake device cpu_cluster 0 on device lapic 0 on end end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + + # TODO: Figure out GPE DW1&2 + register "pmc_gpe0_dw0" = "GPP_C" + #register "pmc_gpe0_dw1" = "??" + #register "pmc_gpe0_dw2" = "??" + + # Wilco EC host command ranges + register "gen1_dec" = "0x00040931" # 0x930-0x937 + register "gen2_dec" = "0x00040941" # 0x940-0x947 + register "gen3_dec" = "0x000c0951" # 0x950-0x95f + + register "s0ix_enable" = "1" + + # TODO: not yet + register "dptf_enable" = "0" + + register "tcc_offset" = "0" + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + + register "SataEnable" = "1" + register "SataMode" = "0" + register "SataSalpSupport" = "1" + register "SmbusEnable" = "1" + + # TODO: the lengths are all MID for right now. + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Ext USB Port 1 (Right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Ext USB Port 2 (Left) + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 3042 (WWAN) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 + + # PCIe root port 6 (WLAN), clock 1 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[1]" = "5" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe root port 7 (Card Reader), clock 4 + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[4]" = "6" + register "PcieClkSrcClkReq[4]" = "4" + + # PCIe port root 8 (LAN), clock 3 + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[3]" = "3" + + # PCIe root port 9 (NVMe), clock 2 + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcUsage[2]" = "8" + register "PcieClkSrcClkReq[2]" = "2" + + # Mark unused SRCCLKREQs as so + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #| I2C2 | ISH ? | + #| I2C3 | cr50 TPM | + #| I2C5 | ISH ? | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + + # TCSS USB3 + register "TcssXhciEn" = "1" + + # DisplayPort + register "DdiPortAConfig" = "1" # eDP + register "DdiPortAHpd" = "1" + + # Disable PM to allow for shorter irq pulses + register "gpio_override_pm" = "1" + register "gpio_pm[0]" = "0" + register "gpio_pm[1]" = "0" + register "gpio_pm[2]" = "0" + register "gpio_pm[3]" = "0" + register "gpio_pm[4]" = "0" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 off end # IPU + device pci 06.0 off end # PEG60 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe0 + device pci 07.2 on end # TBT_PCIe0 + device pci 07.3 on end # TBT_PCIe0 + device pci 08.0 on end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 off end # USB xDCI + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 + device pci 0e.0 off end # VMD + + device pci 10.0 off end # THC #0 + device pci 10.1 off end # THC #1 + device pci 10.2 on end # CNVi Bluetooth + device pci 11.0 off end # UART #3 + device pci 11.1 off end # UART4 + device pci 11.2 off end # UART5 + device pci 11.3 off end # UART6 + + device pci 12.0 on end # ISH + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # GSPI #3 + device pci 13.1 off end # GSPI #4 + device pci 13.2 off end # GSPI #5 + device pci 13.3 off end # GSPI #6 + + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1 (Right)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 2 (Left)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""M.2 3042 (WWAN)"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""M.2 2230 (BT)"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1 (Right)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 2 (Left)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB 3.2 2x1 xHCI HC + + device pci 14.1 off end # USB 3.2 1x1 xDCI HC + device pci 14.2 on end # Shared SRAM + + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi WiFi + end + + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + device i2c 50 on end + end + end # I2C #3 + + device pci 16.0 on end # HECI #1 + device pci 16.1 off end # HECI #2 + device pci 16.2 off end # IDE-R + device pci 16.3 off end # KT-T + device pci 16.4 on end # HECI #3 + device pci 16.5 on end # HECI #4 + device pci 17.0 on end # SATA (AHCI) + device pci 19.0 off end # I2C #4 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # UART #2 + + device pci 1c.0 on end # PCIe Root Port #1 (USB) + device pci 1c.1 on end # PCIe Root Port #2 (USB) + device pci 1c.2 off end # PCIe Root Port #3 () + device pci 1c.3 on end # PCIe Root Port #4 (WWAN) + device pci 1c.4 on end # PCIe Root Port #5 (LTE) + device pci 1c.5 on end # PCIe Root Port #6 (WiFi) + device pci 1c.6 on end # PCIe Root Port #7 (Card reader) + device pci 1c.7 on + chip drivers/net + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end # PCIe Root Port #8 (LAN) + device pci 1d.0 on end # PCIe Root Port #9 (NVMe) + device pci 1d.1 off end # PCIe Root Port #10 (NVMe) + device pci 1d.2 off end # PCIe Root Port #11 (NVMe) + device pci 1d.3 off end # PCIe Root Port #12 (NVMe) + + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + + device pci 1f.0 on + chip ec/google/wilco + device pnp 0c09.0 on end + end + end # eSPI + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # PMC + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI Flash Controller + device pci 1f.6 on end # GbE Controller + device pci 1f.7 off end # Intel Trace Hub + end end From f79f8b4e33a4da257dfacce0eab582b4638791fc Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 27 Mar 2020 10:46:35 -0700 Subject: [PATCH 0680/1463] helpers: Add a helper macro for calculating power of 2 This change adds a helper macro POWER_OF_2 that is useful for calculating the requested power of 2. Change-Id: Ie70f93b6ac175699c11cae7d8f023a52cce01e88 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/39881 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/commonlib/bsd/include/commonlib/bsd/helpers.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/commonlib/bsd/include/commonlib/bsd/helpers.h b/src/commonlib/bsd/include/commonlib/bsd/helpers.h index a305df0cd5..4e6ebeefdd 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/helpers.h +++ b/src/commonlib/bsd/include/commonlib/bsd/helpers.h @@ -52,6 +52,8 @@ (_power_local_x & (_power_local_x - 1)) == 0; \ }) +#define POWER_OF_2(x) (1ULL << (x)) + #define DIV_ROUND_UP(x, y) ({ \ __typeof__(x) _div_local_x = (x); \ __typeof__(y) _div_local_y = (y); \ From 1908340b6903a41750226db90d6dbd39eb527c99 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 24 Mar 2020 14:56:38 -0700 Subject: [PATCH 0681/1463] memranges: Change align attribute to be log2 of required alignment This change updates the align attribute of memranges to be represented as log2 of the required alignment. This makes it consistent with how alignment is stored in struct resource as well. Additionally, since memranges only allow power of 2 alignments, this change allows getting rid of checks at runtime and hence failure cases for non-power of 2 alignments. This change also updates the type of align to be unsigned char. BUG=b:149186922 Signed-off-by: Furquan Shaikh Change-Id: Ie4d3868cdff55b2c7908b9b3ccd5f30a5288e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39810 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/memrange.h | 27 +++++++++++++-------------- src/lib/memrange.c | 29 ++++++++++------------------- 2 files changed, 23 insertions(+), 33 deletions(-) diff --git a/src/include/memrange.h b/src/include/memrange.h index cfd29e7079..dcab791b29 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -24,8 +24,8 @@ struct memranges { /* coreboot doesn't have a free() function. Therefore, keep a cache of * free'd entries. */ struct range_entry *free_list; - /* Alignment for base and end addresses of the range. (Must be power of 2). */ - size_t align; + /* Alignment(log 2) for base and end addresses of the range. */ + unsigned char align; }; /* Each region within a memranges structure is represented by a @@ -96,29 +96,29 @@ static inline bool memranges_is_empty(struct memranges *ranges) /* Initialize memranges structure providing an optional array of range_entry * to use as the free list. Additionally, it accepts an align parameter that - * determines the alignment of addresses. (Alignment must be a power of 2). */ + * represents the required alignment(log 2) of addresses. */ void memranges_init_empty_with_alignment(struct memranges *ranges, struct range_entry *free, - size_t num_free, size_t align); + size_t num_free, unsigned char align); /* Initialize and fill a memranges structure according to the * mask and match type for all memory resources. Tag each entry with the * specified type. Additionally, it accepts an align parameter that - * determines the alignment of addresses. (Alignment must be a power of 2). */ + * represents the required alignment(log 2) of addresses. */ void memranges_init_with_alignment(struct memranges *ranges, unsigned long mask, unsigned long match, - unsigned long tag, size_t align); + unsigned long tag, unsigned char align); /* Initialize memranges structure providing an optional array of range_entry - * to use as the free list. Addresses are default aligned to 4KiB. */ + * to use as the free list. Addresses are default aligned to 4KiB(2^12). */ #define memranges_init_empty(__ranges, __free, __num_free) \ - memranges_init_empty_with_alignment(__ranges, __free, __num_free, 4 * KiB) + memranges_init_empty_with_alignment(__ranges, __free, __num_free, 12); /* Initialize and fill a memranges structure according to the * mask and match type for all memory resources. Tag each entry with the - * specified type. Addresses are default aligned to 4KiB. */ + * specified type. Addresses are default aligned to 4KiB(2^12). */ #define memranges_init(__ranges, __mask, __match, __tag) \ - memranges_init_with_alignment(__ranges, __mask, __match, __tag, 4 * KiB) + memranges_init_with_alignment(__ranges, __mask, __match, __tag, 12); /* Clone a memrange. The new memrange has the same entries as the old one. */ void memranges_clone(struct memranges *newranges, struct memranges *oldranges); @@ -175,14 +175,13 @@ struct range_entry *memranges_next_entry(struct memranges *ranges, /* Steals memory from the available list in given ranges as per the constraints: * limit = Upper bound for the memory range to steal. * size = Requested size for the stolen memory. - * align = Alignment requirements for the starting address of the stolen memory. - * (Alignment must be a power of 2). + * align = Required alignment(log 2) for the starting address of the stolen memory. * tag = Use a range that matches the given tag. * * If the constraints can be satisfied, this function creates a hole in the memrange, * writes the base address of that hole to stolen_base and returns true. Otherwise it returns * false. */ -bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, size_t align, - unsigned long tag, resource_t *stolen_base); +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base); #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 5fb40dfca7..fd7a4d6489 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -230,12 +230,12 @@ static void do_action(struct memranges *ranges, if (size == 0) return; - /* The addresses are aligned to 4096 bytes: the begin address is + /* The addresses are aligned to (1ULL << ranges->align): the begin address is * aligned down while the end address is aligned up to be conservative * about the full range covered. */ - begin = ALIGN_DOWN(base, ranges->align); + begin = ALIGN_DOWN(base, POWER_OF_2(ranges->align)); end = begin + size + (base - begin); - end = ALIGN_UP(end, ranges->align) - 1; + end = ALIGN_UP(end, POWER_OF_2(ranges->align)) - 1; action(ranges, begin, end, tag); } @@ -294,13 +294,10 @@ void memranges_add_resources(struct memranges *ranges, void memranges_init_empty_with_alignment(struct memranges *ranges, struct range_entry *to_free, - size_t num_free, size_t align) + size_t num_free, unsigned char align) { size_t i; - /* Alignment must be a power of 2. */ - assert(IS_POWER_OF_2(align)); - ranges->entries = NULL; ranges->free_list = NULL; ranges->align = align; @@ -311,7 +308,7 @@ void memranges_init_empty_with_alignment(struct memranges *ranges, void memranges_init_with_alignment(struct memranges *ranges, unsigned long mask, unsigned long match, - unsigned long tag, size_t align) + unsigned long tag, unsigned char align) { memranges_init_empty_with_alignment(ranges, NULL, 0, align); memranges_add_resources(ranges, mask, match, tag); @@ -395,7 +392,7 @@ struct range_entry *memranges_next_entry(struct memranges *ranges, * required alignment, is big enough, does not exceed the limit and has a matching tag. */ static const struct range_entry *memranges_find_entry(struct memranges *ranges, resource_t limit, resource_t size, - size_t align, unsigned long tag) + unsigned char align, unsigned long tag) { const struct range_entry *r; resource_t base, end; @@ -403,18 +400,12 @@ static const struct range_entry *memranges_find_entry(struct memranges *ranges, if (size == 0) return NULL; - if (!IS_POWER_OF_2(align)) - return NULL; - - if (!IS_ALIGNED(align, ranges->align)) - return NULL; - memranges_each_entry(r, ranges) { if (r->tag != tag) continue; - base = ALIGN_UP(r->begin, align); + base = ALIGN_UP(r->begin, POWER_OF_2(align)); end = base + size - 1; if (end > r->end) @@ -429,8 +420,8 @@ static const struct range_entry *memranges_find_entry(struct memranges *ranges, return NULL; } -bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, size_t align, - unsigned long tag, resource_t *stolen_base) +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base) { resource_t base; const struct range_entry *r = memranges_find_entry(ranges, limit, size, align, tag); @@ -438,7 +429,7 @@ bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size if (r == NULL) return false; - base = ALIGN_UP(r->begin, align); + base = ALIGN_UP(r->begin, POWER_OF_2(align)); memranges_create_hole(ranges, base, size); *stolen_base = base; From 0a9650c1d4631cd1a3c7f526d34a58bc6eab947e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 22:25:36 +0100 Subject: [PATCH 0682/1463] mb/gigabyte/ga-h61m-s2pv: Correct PCIe port setup Coalescing is not needed, as root port #1 is enabled. Also, update the comments to look more like the other two variants. Note that the Intel H61 PCH only has six root ports, so devices 1c.6 and 1c.7 do not exist. Change-Id: I3f4bf99ceec6c77f6e1eabea9b712245afee7d34 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39742 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../variants/ga-h61m-s2pv/devicetree.cb | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb index 08abc3e037..b76200bd06 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb @@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "gen1_dec" = "0x003c0a01" - register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" @@ -46,14 +45,14 @@ chip northbridge/intel/sandybridge device pci 19.0 off end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe x1 Port (PCIEX1) - device pci 1c.1 off end # Unused PCIe Port - device pci 1c.2 off end # Unused PCIe Port - device pci 1c.3 off end # Unused PCIe Port - device pci 1c.4 on end # Realtek RTL8111F Ethernet Controller - device pci 1c.5 on end # ITE IT8892F PCIe to PCI bridge - device pci 1c.6 off end # Unused PCIe Port - device pci 1c.7 off end # Unused PCIe Port + + device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1) + device pci 1c.1 off end # RP #2: + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: ITE IT8892F PCIe to PCI bridge + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge From bf7d6f1a82926fdb61aec78f7bbd44c97af4437f Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 2 Feb 2020 18:03:22 -0500 Subject: [PATCH 0683/1463] asus/p2b: Transform into variant-enabled structure Get ready to squash all the ASUS i440BX boards together. Change-Id: Ibc9bfa4fc5b582bf658215bda298523e8ee7b36b Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38621 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/asus/p2b/Kconfig | 8 +++- src/mainboard/asus/p2b/Makefile.inc | 1 + src/mainboard/asus/p2b/irq_tables.c | 44 ------------------- .../asus/p2b/variants/p2b/irq_tables.c | 44 +++++++++++++++++++ 4 files changed, 51 insertions(+), 46 deletions(-) create mode 100644 src/mainboard/asus/p2b/Makefile.inc create mode 100644 src/mainboard/asus/p2b/variants/p2b/irq_tables.c diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f55b3a6d46..a9a9b82985 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -29,10 +29,14 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "P2B" + default "P2B" if BOARD_ASUS_P2B + +config VARIANT_DIR + string + default "p2b" if BOARD_ASUS_P2B config IRQ_SLOT_COUNT int default 6 -endif # BOARD_ASUS_P2B +endif diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc new file mode 100644 index 0000000000..640396eea4 --- /dev/null +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c index 4601f0850e..e69de29bb2 100644 --- a/src/mainboard/asus/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/irq_tables.c @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x54, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c new file mode 100644 index 0000000000..4601f0850e --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x54, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} From 7e269ad06c5487c8a0731594167d6840482dfcb7 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 2 Feb 2020 19:23:47 -0500 Subject: [PATCH 0684/1463] asus/p2b-f: Transform into variant TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I56983cabfad574b970aba098a178e691c6b354d1 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/39902 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/asus/p2b-f/Kconfig | 37 ------------------- src/mainboard/asus/p2b-f/Kconfig.name | 2 - src/mainboard/asus/p2b-f/romstage.c | 17 --------- src/mainboard/asus/p2b/Kconfig | 11 +++++- src/mainboard/asus/p2b/Kconfig.name | 3 ++ .../{ => p2b/variants}/p2b-f/board_info.txt | 0 .../{ => p2b/variants}/p2b-f/devicetree.cb | 0 .../{ => p2b/variants}/p2b-f/irq_tables.c | 0 8 files changed, 12 insertions(+), 58 deletions(-) delete mode 100644 src/mainboard/asus/p2b-f/Kconfig delete mode 100644 src/mainboard/asus/p2b-f/Kconfig.name delete mode 100644 src/mainboard/asus/p2b-f/romstage.c rename src/mainboard/asus/{ => p2b/variants}/p2b-f/board_info.txt (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-f/devicetree.cb (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-f/irq_tables.c (100%) diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig deleted file mode 100644 index cb220c9913..0000000000 --- a/src/mainboard/asus/p2b-f/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_F - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default "asus/p2b-f" - -config MAINBOARD_PART_NUMBER - string - default "P2B-F" - -config IRQ_SLOT_COUNT - int - default 7 - -endif # BOARD_ASUS_P2B_F diff --git a/src/mainboard/asus/p2b-f/Kconfig.name b/src/mainboard/asus/p2b-f/Kconfig.name deleted file mode 100644 index a433376ef0..0000000000 --- a/src/mainboard/asus/p2b-f/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_F - bool "P2B-F" diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c deleted file mode 100644 index f91a806b5e..0000000000 --- a/src/mainboard/asus/p2b-f/romstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Shares romstage with the better supported P2B-LS sibling. */ -#include "../p2b-ls/romstage.c" diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index a9a9b82985..503e662661 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -11,7 +11,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B +if BOARD_ASUS_P2B || BOARD_ASUS_P2B_F config BOARD_SPECIFIC_OPTIONS def_bool y @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 - select HAVE_ACPI_TABLES + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B config MAINBOARD_DIR string @@ -30,13 +30,20 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string default "P2B" if BOARD_ASUS_P2B + default "P2B-F" if BOARD_ASUS_P2B_F config VARIANT_DIR string default "p2b" if BOARD_ASUS_P2B + default "p2b-f" if BOARD_ASUS_P2B_F + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" if ! BOARD_ASUS_P2B config IRQ_SLOT_COUNT int + default 7 if BOARD_ASUS_P2B_F default 6 endif diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index 60d6028d74..ee34b16088 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASUS_P2B bool "P2B" + +config BOARD_ASUS_P2B_F + bool "P2B-F" diff --git a/src/mainboard/asus/p2b-f/board_info.txt b/src/mainboard/asus/p2b/variants/p2b-f/board_info.txt similarity index 100% rename from src/mainboard/asus/p2b-f/board_info.txt rename to src/mainboard/asus/p2b/variants/p2b-f/board_info.txt diff --git a/src/mainboard/asus/p2b-f/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-f/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-f/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c From 98b78efabe028761f6c78048395b27f29ca4e290 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Tue, 3 Dec 2019 22:15:49 +0100 Subject: [PATCH 0685/1463] mb/lenovo/t530: Switch to overridetree Change-Id: I3dfa303b6aae2446fa3a1d67a6e31448277cacdb Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37602 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/t530/Kconfig | 4 +- .../t530/{variants/t530 => }/devicetree.cb | 6 +- .../lenovo/t530/variants/t530/overridetree.cb | 13 ++ .../lenovo/t530/variants/w530/devicetree.cb | 185 ------------------ .../lenovo/t530/variants/w530/overridetree.cb | 24 +++ 5 files changed, 40 insertions(+), 192 deletions(-) rename src/mainboard/lenovo/t530/{variants/t530 => }/devicetree.cb (96%) create mode 100644 src/mainboard/lenovo/t530/variants/t530/overridetree.cb delete mode 100644 src/mainboard/lenovo/t530/variants/w530/devicetree.cb create mode 100644 src/mainboard/lenovo/t530/variants/w530/overridetree.cb diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index bef0dee118..0f8d3267f3 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -56,9 +56,9 @@ config MAINBOARD_DIR string default "lenovo/t530" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb similarity index 96% rename from src/mainboard/lenovo/t530/variants/t530/devicetree.cb rename to src/mainboard/lenovo/t530/devicetree.cb index cedb478573..1b16ca3b2c 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -40,7 +40,7 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # PCIe bridge for discrete graphics device pci 02.0 on end # Internal graphics VGA controller - chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -140,10 +140,6 @@ chip northbridge/intel/sandybridge register "has_bdc_detection" = "1" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" - - register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" end chip drivers/lenovo/hybrid_graphics device pnp ff.f on end # dummy diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb new file mode 100644 index 0000000000..e48a702839 --- /dev/null +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end + end + end +end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb deleted file mode 100644 index be6cc7d9d0..0000000000 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ /dev/null @@ -1,185 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(1)" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms - register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms - register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21f6 inherit - - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f5 - end - - chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - register "sata_port_map" = "0x3f" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - - register "xhci_switchable_ports" = "0xf" - register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x04000201" - - register "docking_supported" = "1" - - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 on end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21f3 - end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on # PCIe Port #1 - chip drivers/ricoh/rce822 # Ricoh cardreader - register "disable_mask" = "0x83" - register "sdwppol" = "1" - device pci 00.0 on end # Ricoh SD card reader - end - end - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on # PCIe Port #3 - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # PCI-LPC bridge - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x01" - register "config2" = "0xa0" - register "config3" = "0xe2" - - register "has_keyboard_backlight" = "1" - - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xd0" - register "event5_enable" = "0xfc" - register "event6_enable" = "0x00" - register "event7_enable" = "0x01" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb new file mode 100644 index 0000000000..fc5b31e04b --- /dev/null +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -0,0 +1,24 @@ +chip northbridge/intel/sandybridge + device domain 0 on + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f5 + end + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device pci 16.3 on end # Management Engine KT + device pci 1c.0 on # PCIe Port #1 + chip drivers/ricoh/rce822 # Ricoh cardreader + register "disable_mask" = "0x83" + register "sdwppol" = "1" + device pci 00.0 on end # Ricoh SD card reader + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "config1" = "0x01" + register "config3" = "0xe2" + end + end + device pci 1f.6 off end # Thermal + end + end +end From 95cdd9f21bdf4191f5b0f4c617fb398462d8a647 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 26 Mar 2020 12:20:38 +0100 Subject: [PATCH 0686/1463] nb/intel/i945: Make some cosmetic changes This will make i945GC and i945GM splitting easier. Change-Id: I3acc1f526056248f8fbb1778a3c381d369faf020 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39859 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i945/raminit.c | 52 ++++++++++++++++------------ 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 134d11fbdc..51ee65d7df 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -74,7 +74,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command) PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32); - MCHBAR32(DCC) = reg32; /* This is the actual magic */ + MCHBAR32(DCC) = reg32; /* This is the actual magic */ PRINTK_DEBUG("...done\n"); @@ -205,7 +205,7 @@ static int sdram_capabilities_enhanced_addressing_xor(void) return (!reg8); } -// TODO check if we ever need this function +/* TODO check if we ever need this function */ #if 0 static int sdram_capabilities_MEM4G_disable(void) { @@ -447,7 +447,7 @@ static void gather_common_timing(struct sys_info *sysinfo, sysinfo->package = SYSINFO_PACKAGE_STACKED; if (!dimm_info.flags.bl8) - die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); + die("Only DDR-II RAM with burst length 8 is supported.\n"); if (dimm_info.ranksize_mb < 128) die("DDR-II rank size smaller than 128MB is not supported.\n"); @@ -495,7 +495,7 @@ static void gather_common_timing(struct sys_info *sysinfo, die("No memory installed.\n"); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) - /* Possibly does not boot in this case */ + /* FIXME: Possibly does not boot in this case */ printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); } @@ -809,9 +809,9 @@ static const u32 *slew_group_lookup(int dual_channel, int index) const u8 *slew_group; /* Dual Channel needs different tables. */ if (dual_channel) - slew_group = dual_channel_slew_group_lookup; + slew_group = dual_channel_slew_group_lookup; else - slew_group = single_channel_slew_group_lookup; + slew_group = single_channel_slew_group_lookup; switch (slew_group[index]) { case DQ2030: return dq2030; @@ -950,7 +950,7 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; dual_channel = 1; - idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; + idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; @@ -1202,7 +1202,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) if (sysinfo->interleaved) tolud = (cum0 + cum1) << 1; else - tolud = (cum1 ? cum1 : cum0) << 1; + tolud = (cum1 ? cum1 : cum0) << 1; /* The TOM register has a different format */ tom = tolud >> 3; @@ -1342,7 +1342,7 @@ static void sdram_program_cke_tristate(struct sys_info *sysinfo) reg32 |= (1 << 11); MCHBAR32(C0DRC1) = reg32; - /* Do we have to do this if we're in Single Channel Mode? */ + /* Do we have to do this if we're in Single Channel Mode? */ reg32 = MCHBAR32(C1DRC1); for (i = 4; i < 8; i++) { @@ -1444,12 +1444,16 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) */ tRD_min = sysinfo->cas; switch (sysinfo->fsb_frequency) { - case 533: break; - case 667: tRD_min += 1; + case 533: break; - case 800: tRD_min += 2; + case 667: + tRD_min += 1; break; - case 1066: tRD_min += 3; + case 800: + tRD_min += 2; + break; + case 1066: + tRD_min += 3; break; } @@ -1557,10 +1561,10 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Setting mode of operation for memory channels..."); if (sdram_capabilities_interleave() && - ((sysinfo->banksize[0] + sysinfo->banksize[1] + - sysinfo->banksize[2] + sysinfo->banksize[3]) == - (sysinfo->banksize[4] + sysinfo->banksize[5] + - sysinfo->banksize[6] + sysinfo->banksize[7]))) { + ((sysinfo->banksize[0] + sysinfo->banksize[1] + + sysinfo->banksize[2] + sysinfo->banksize[3]) == + (sysinfo->banksize[4] + sysinfo->banksize[5] + + sysinfo->banksize[6] + sysinfo->banksize[7]))) { /* Both channels equipped with DIMMs of the same size */ sysinfo->interleaved = 1; } else { @@ -1624,9 +1628,9 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo) static void sdram_program_graphics_frequency(struct sys_info *sysinfo) { - u8 reg8; + u8 reg8; u16 reg16; - u8 freq, second_vco, voltage; + u8 freq, second_vco, voltage; #define CRCLK_166MHz 0x00 #define CRCLK_200MHz 0x01 @@ -1699,7 +1703,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) if (voltage == VOLTAGE_1_50) { second_vco = 1; - } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { + } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { u16 mem = sysinfo->memory_frequency; u16 fsb = sysinfo->fsb_frequency; @@ -2507,7 +2511,7 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) } #define RTT_ODT_NONE 0 -#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) +#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) #define RTT_ODT_75_OHM (1 << 5) #define RTT_ODT_150_OHM (1 << 9) @@ -2541,13 +2545,15 @@ static void sdram_jedec_enable(struct sys_info *sysinfo) if (sysinfo->interleaved && nonzero < 4 && i >= 4) { bankaddr = 0x40; } else { - printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero); + printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", + nonzero); bankaddr += sysinfo->banksize[nonzero] << (sysinfo->interleaved ? 26 : 25); } } - /* We have a bank with a non-zero size.. Remember it + /* + * We have a bank with a non-zero size... Remember it * for the next offset we have to calculate */ nonzero = i; From 0c0b16ac9e8ae62533f3029aa1a9f33506222dce Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Mar 2020 10:56:18 +0100 Subject: [PATCH 0687/1463] mb/gigabyte/ga-h61m-*: Use overridetrees Make use of overridetrees, as these mainboards are very similar. Tested on GA-H61MA-D3V, still works fine. Change-Id: I1b587a091da631cb172eb76722958da6c7518893 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39668 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig | 4 +- .../gigabyte/ga-h61m-s2pv/devicetree.cb | 46 ++++++++ .../variants/ga-h61m-ds2v/devicetree.cb | 96 ---------------- .../variants/ga-h61m-ds2v/overridetree.cb | 52 +++++++++ .../variants/ga-h61m-s2pv/devicetree.cb | 104 ------------------ .../variants/ga-h61m-s2pv/overridetree.cb | 58 ++++++++++ .../variants/ga-h61ma-d3v/devicetree.cb | 100 ----------------- .../variants/ga-h61ma-d3v/overridetree.cb | 57 ++++++++++ 8 files changed, 215 insertions(+), 302 deletions(-) create mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb delete mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb create mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb delete mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb create mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb delete mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb create mode 100644 src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index f82ce4a83d..67cefd1c0f 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -46,9 +46,9 @@ config MAINBOARD_PART_NUMBER default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAX_CPUS int diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb new file mode 100644 index 0000000000..14778097e6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -0,0 +1,46 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1458 0x5000 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb deleted file mode 100644 index c5dd15e7dd..0000000000 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb +++ /dev/null @@ -1,96 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - register "pci_mmio_size" = "2048" - device domain 0 on - subsystemid 0x1458 0x5000 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x003c0a01" - register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - - device pci 16.0 on end # MEI #1 - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio - - device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3) - device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC - device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) - - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/ite/it8728f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 off end # COM1 - device pnp 2e.2 off end # COM2 - device pnp 2e.3 off end # Parallel port - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x0a30 - io 0x62 = 0x0a20 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - end - device pnp 2e.6 on end # Mouse - device pnp 2e.7 on # GPIO - irq 0x25 = 0x40 - irq 0x26 = 0xf7 - irq 0x27 = 0x10 - irq 0x2c = 0x80 - io 0x60 = 0x0000 - io 0x62 = 0x0a00 - io 0x64 = 0x0000 - irq 0x70 = 0x00 - irq 0x73 = 0x00 - irq 0xc1 = 0x37 - irq 0xcb = 0x00 - irq 0xf0 = 0x10 - irq 0xf1 = 0x42 - irq 0xf6 = 0x1c - end - device pnp 2e.a off end # CIR - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb new file mode 100644 index 0000000000..4e3b21bfe2 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb @@ -0,0 +1,52 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + device domain 0 on + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + + device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3) + device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) + + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + end + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x70 = 0x00 + irq 0x73 = 0x00 + irq 0xc1 = 0x37 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x42 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb deleted file mode 100644 index b76200bd06..0000000000 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/sandybridge - device cpu_cluster 0x0 on - chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0x0 on end - device lapic 0xacac off end - end - end - register "pci_mmio_size" = "2048" - device domain 0x0 on - subsystemid 0x1458 0x5000 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) - device pci 02.0 on end # Internal graphics VGA controller - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x003c0a01" - register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - - device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC - device pci 1c.5 on end # RP #6: ITE IT8892F PCIe to PCI bridge - - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/ite/it8728f - device pnp 2e.0 off end # Floppy, not routed. - device pnp 2e.1 on # COM1 - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.2 off end # COM2, not routed. - device pnp 2e.3 on # Parallel port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x0a30 - irq 0x70 = 9 - io 0x62 = 0x0a20 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - irq 0x70 = 1 - io 0x62 = 0x64 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - irq 0x25 = 0x40 - irq 0x27 = 0x10 - irq 0x2c = 0x80 - io 0x60 = 0x0000 - io 0x62 = 0x0a00 - io 0x64 = 0x0000 - irq 0x70 = 0x00 - irq 0xcb = 0x00 - irq 0xf1 = 0x40 - end - device pnp 2e.a off end # CIR, not routed. - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb new file mode 100644 index 0000000000..35f5144dec --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + device domain 0 on + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + + device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1) + device pci 1c.1 off end # RP #2: + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: ITE IT8892F PCIe to PCI bridge + + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x70 = 0x00 + irq 0xcb = 0x00 + irq 0xf1 = 0x40 + end + device pnp 2e.a off end # CIR + end + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb deleted file mode 100644 index 455e109077..0000000000 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb +++ /dev/null @@ -1,100 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/sandybridge - device cpu_cluster 0x0 on - chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0x0 on end - device lapic 0xacac off end - end - end - register "pci_mmio_size" = "2048" - device domain 0x0 on - subsystemid 0x1458 0x5000 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x003c0a01" - register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - - device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3) - device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) - device pci 1c.2 on end # RP #3: Etron EJ168 USB 3.0 - device pci 1c.3 on end # RP #4: Marvell 88SE9172 SATA - device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC - device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) - - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/ite/it8728f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 off end # COM1 - device pnp 2e.2 off end # COM2 - device pnp 2e.3 off end # Parallel port - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x0a30 - io 0x62 = 0x0a20 - irq 0x70 = 9 - irq 0xf2 = 0x40 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0xf0 = 0x08 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - irq 0x25 = 0x40 - irq 0x26 = 0xf7 - irq 0x27 = 0x10 - irq 0x2c = 0x80 - io 0x60 = 0x0000 - io 0x62 = 0x0a00 - io 0x64 = 0x0000 - irq 0x70 = 0x00 - irq 0x73 = 0x00 - irq 0xcb = 0x00 - irq 0xf0 = 0x10 - irq 0xf1 = 0x40 - irq 0xf6 = 0x1c - end - device pnp 2e.a off end # CIR - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb new file mode 100644 index 0000000000..3672ba0007 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb @@ -0,0 +1,57 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + device domain 0 on + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + + device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3) + device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) + device pci 1c.2 on end # RP #3: Etron EJ168 USB 3.0 + device pci 1c.3 on end # RP #4: Marvell 88SE9172 SATA + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) + + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + irq 0x70 = 9 + irq 0xf2 = 0x40 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0xf0 = 0x08 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x70 = 0x00 + irq 0x73 = 0x00 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x40 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + end + end +end From 991ee05de9fedc15f178660e0cac0b46e783525e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 22:34:44 +0100 Subject: [PATCH 0688/1463] mb/gigabyte/ga-h61m-s2pv: rename to ga-h61m-series It is not a single mainboard anymore, it's actually three variants. Change-Id: I66f1239abadd8bf93269d6d4617329dc4b925e8d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39743 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../{ga-h61m-s2pv => ga-h61m-series}/Kconfig | 2 +- .../{ga-h61m-s2pv => ga-h61m-series}/Kconfig.name | 0 .../{ga-h61m-s2pv => ga-h61m-series}/Makefile.inc | 0 .../{ga-h61m-s2pv => ga-h61m-series}/acpi/ec.asl | 0 .../acpi/mainboard.asl | 0 .../acpi/platform.asl | 0 .../acpi/superio.asl | 0 .../acpi/thermal.asl | 0 .../{ga-h61m-s2pv => ga-h61m-series}/acpi_tables.c | 0 .../{ga-h61m-s2pv => ga-h61m-series}/board_info.txt | 0 .../{ga-h61m-s2pv => ga-h61m-series}/cmos.default | 0 .../{ga-h61m-s2pv => ga-h61m-series}/cmos.layout | 0 .../{ga-h61m-s2pv => ga-h61m-series}/data.vbt | Bin .../{ga-h61m-s2pv => ga-h61m-series}/devicetree.cb | 0 .../{ga-h61m-s2pv => ga-h61m-series}/dsdt.asl | 0 .../{ga-h61m-s2pv => ga-h61m-series}/early_init.c | 0 .../gma-mainboard.ads | 0 .../{ga-h61m-s2pv => ga-h61m-series}/hda_verb.c | 0 .../{ga-h61m-s2pv => ga-h61m-series}/mainboard.c | 0 .../variants/ga-h61m-ds2v/gpio.c | 0 .../variants/ga-h61m-ds2v/hda_verb.c | 0 .../variants/ga-h61m-ds2v/overridetree.cb | 0 .../variants/ga-h61m-s2pv/gpio.c | 0 .../variants/ga-h61m-s2pv/hda_verb.c | 0 .../variants/ga-h61m-s2pv/overridetree.cb | 0 .../variants/ga-h61ma-d3v/gpio.c | 0 .../variants/ga-h61ma-d3v/hda_verb.c | 0 .../variants/ga-h61ma-d3v/overridetree.cb | 0 28 files changed, 1 insertion(+), 1 deletion(-) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/Kconfig (98%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/Kconfig.name (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/Makefile.inc (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/acpi/ec.asl (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/acpi/mainboard.asl (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/acpi/platform.asl (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/acpi/superio.asl (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/acpi/thermal.asl (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/acpi_tables.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/board_info.txt (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/cmos.default (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/cmos.layout (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/data.vbt (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/devicetree.cb (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/dsdt.asl (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/early_init.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/gma-mainboard.ads (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/hda_verb.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/mainboard.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61m-ds2v/gpio.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61m-ds2v/hda_verb.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61m-ds2v/overridetree.cb (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61m-s2pv/gpio.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61m-s2pv/hda_verb.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61m-s2pv/overridetree.cb (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61ma-d3v/gpio.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61ma-d3v/hda_verb.c (100%) rename src/mainboard/gigabyte/{ga-h61m-s2pv => ga-h61m-series}/variants/ga-h61ma-d3v/overridetree.cb (100%) diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-series/Kconfig similarity index 98% rename from src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig rename to src/mainboard/gigabyte/ga-h61m-series/Kconfig index 67cefd1c0f..a005009c5c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig @@ -32,7 +32,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default "gigabyte/ga-h61m-s2pv" + default "gigabyte/ga-h61m-series" config VARIANT_DIR string diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name rename to src/mainboard/gigabyte/ga-h61m-series/Kconfig.name diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc rename to src/mainboard/gigabyte/ga-h61m-series/Makefile.inc diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/ec.asl similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl rename to src/mainboard/gigabyte/ga-h61m-series/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl rename to src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/platform.asl similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl rename to src/mainboard/gigabyte/ga-h61m-series/acpi/platform.asl diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/superio.asl similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl rename to src/mainboard/gigabyte/ga-h61m-series/acpi/superio.asl diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl rename to src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c rename to src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt b/src/mainboard/gigabyte/ga-h61m-series/board_info.txt similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt rename to src/mainboard/gigabyte/ga-h61m-series/board_info.txt diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default b/src/mainboard/gigabyte/ga-h61m-series/cmos.default similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default rename to src/mainboard/gigabyte/ga-h61m-series/cmos.default diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout rename to src/mainboard/gigabyte/ga-h61m-series/cmos.layout diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt b/src/mainboard/gigabyte/ga-h61m-series/data.vbt similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt rename to src/mainboard/gigabyte/ga-h61m-series/data.vbt diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb rename to src/mainboard/gigabyte/ga-h61m-series/devicetree.cb diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl rename to src/mainboard/gigabyte/ga-h61m-series/dsdt.asl diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c b/src/mainboard/gigabyte/ga-h61m-series/early_init.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c rename to src/mainboard/gigabyte/ga-h61m-series/early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h61m-series/gma-mainboard.ads similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads rename to src/mainboard/gigabyte/ga-h61m-series/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/hda_verb.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c rename to src/mainboard/gigabyte/ga-h61m-series/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c b/src/mainboard/gigabyte/ga-h61m-series/mainboard.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c rename to src/mainboard/gigabyte/ga-h61m-series/mainboard.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/gpio.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/overridetree.cb similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/overridetree.cb diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/gpio.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/overridetree.cb similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/overridetree.cb diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/gpio.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/overridetree.cb similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb rename to src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/overridetree.cb From e5565c45cb71df105bc9ff1dc7572b4e749adaea Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 5 Mar 2020 11:54:47 +0530 Subject: [PATCH 0689/1463] soc/intel/{icelake, tigerlake}: Remove DDI A lane programming For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by default. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A(for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp and tglrvp compilation and boot. Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313 Reviewed-by: Nico Huber Reviewed-by: Aamir Bohra Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/graphics.c | 19 ------------------- src/soc/intel/tigerlake/graphics.c | 19 ------------------- 2 files changed, 38 deletions(-) diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 4f5d573c8b..0ee340ce3b 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -31,24 +30,6 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { - uint32_t ddi_buf_ctl; - - /* Skip IGD GT programming */ - if (CONFIG(SKIP_GRAPHICS_ENABLING)) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index fef17e17e8..4054bd549b 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -37,24 +36,6 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { - uint32_t ddi_buf_ctl; - - /* Skip IGD GT programming */ - if (CONFIG(SKIP_GRAPHICS_ENABLING)) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig From 8a6e036861c87deadc6455f89062c56639acbdc7 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Sun, 8 Dec 2019 15:54:09 +0100 Subject: [PATCH 0690/1463] intel/fsp2_0: Make FSP_USE_REPO a SoC opt-in For quite a bit now we are extending the FSP_USE_REPO option to be available for all Intel SoCs. This results in a list being not only hard to maintain but also prone to errors. To change that behaviour this commit introduces the HAVE_INTEL_FSP_REPO config option for SoCs that are supported from within 3rdparty/fsp. If a SoC selects HAVE_INTEL_FSP_REPO the config option FSP_USE_REPO is selected by default, but can be still deselected by the user in menuconfig. Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc Signed-off-by: Johanna Schander Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/37582 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Kconfig | 6 ++---- src/soc/intel/Kconfig | 6 ++++++ src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/cannonlake/Kconfig | 3 +++ src/soc/intel/denverton_ns/Kconfig | 1 + src/soc/intel/icelake/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + 7 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index cf79201db6..1e1cc194d8 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,10 +53,8 @@ config FSP_M_CBFS config FSP_USE_REPO bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES - depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ - SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \ - SOC_INTEL_DENVERTON_NS || SOC_INTEL_COMETLAKE + depends on HAVE_INTEL_FSP_REPO + default y help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index d5190683ae..75f2f7090e 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -38,3 +38,9 @@ config INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG than the one in non-topswap bootblock. This string will be passed onto ifittool (-A -n option). ifittool will not parse the region for MCU entries, and only locate the region and insert its address into FIT. + +config HAVE_INTEL_FSP_REPO + bool + help + Select this, if the FSP binaries for the platform are public available + in 3rdparty/fsp. diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2bc49c838f..ed35eaac7e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER + select HAVE_INTEL_FSP_REPO select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 1495e2e1bb..baf8756385 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -24,6 +24,7 @@ config SOC_INTEL_COFFEELAKE bool select SOC_INTEL_CANNONLAKE_BASE select FSP_USES_CB_STACK + select HAVE_INTEL_FSP_REPO help Intel Coffeelake support @@ -31,6 +32,7 @@ config SOC_INTEL_WHISKEYLAKE bool select SOC_INTEL_CANNONLAKE_BASE select FSP_USES_CB_STACK + select HAVE_INTEL_FSP_REPO help Intel Whiskeylake support @@ -39,6 +41,7 @@ config SOC_INTEL_COMETLAKE select SOC_INTEL_CANNONLAKE_BASE select MICROCODE_BLOB_UNDISCLOSED select FSP_USES_CB_STACK + select HAVE_INTEL_FSP_REPO help Intel Cometlake support diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 6ca7f3e61f..c628dbd7b5 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 select IOAPIC + select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS select PARALLEL_MP diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 9e97d2ca2c..559ba6c801 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP + select HAVE_INTEL_FSP_REPO select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 4493f9ba9a..2beda43c7c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select HAVE_INTEL_FSP_REPO select IOAPIC select MRC_SETTINGS_PROTECT select PARALLEL_MP From 6b7bbc2b782938685ba08982c83c1694317a16b8 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Fri, 20 Mar 2020 10:37:59 -0700 Subject: [PATCH 0691/1463] mb/google/kohaku: Add enable_delay_ms for wacom pen Add an enable reset delay to avoid messages like this in the kernel: i2c_hid i2c-WCOM50C1:00: failed to change power setting. This gets rid of all the warnings except one on reboot/shutdown. That last case likely isn't fixed because the sleep command is being sent directly from i2c_hid_shutdown(), so no ACPI routines get to run and provide the delay. Since the machine is going down for shutdown/reboot anyway, fixing that last case is a lower priority. BUG=b:145094539 TEST=Run on kohaku, switch to guest mode and log out, no errors Signed-off-by: Evan Green Change-Id: I8fadf497dd09e5b95b1d74443fb0543d3555dbb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39707 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6a5ce7c004..08bbb2a9b0 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -207,6 +207,7 @@ chip soc/intel/cannonlake register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C15)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A19)" register "generic.reset_delay_ms" = "100" + register "generic.enable_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end From c79e96b4eb310db9d44e36e2dff072c01469c380 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Thu, 22 Aug 2019 20:28:36 +0800 Subject: [PATCH 0692/1463] security/vboot: Decouple measured boot from verified boot Currently, those who want to use measured boot implemented within vboot should enable verified boot first, along with sections such as GBB and RW slots defined with manually written fmd files, even if they do not actually want to verify anything. As discussed in CB:34977, measured boot should be decoupled from verified boot and make them two fully independent options. Crypto routines necessary for measurement could be reused, and TPM and CRTM init should be done somewhere other than vboot_logic_executed() if verified boot is not enabled. In this revision, only TCPA log is initialized during bootblock. Before TPM gets set up, digests are not measured into tpm immediately, but cached in TCPA log, and measured into determined PCRs right after TPM is up. This change allows those who do not want to use the verified boot scheme implemented by vboot as well as its requirement of a more complex partition scheme designed for chromeos to make use of the measured boot functionality implemented within vboot library to measure the boot process. TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook(). Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese Reviewed-by: Julius Werner Reviewed-by: Werner Zeh --- src/arch/x86/car.ld | 4 +- src/include/memlayout.h | 6 +- src/include/symbols.h | 5 +- src/lib/cbfs.c | 14 +- .../siemens/mc_apl1/variants/mc_apl2/Kconfig | 2 +- .../siemens/mc_apl1/variants/mc_apl4/Kconfig | 2 +- .../siemens/mc_apl1/variants/mc_apl5/Kconfig | 2 +- .../siemens/mc_apl1/variants/mc_apl6/Kconfig | 2 +- src/security/tpm/Kconfig | 17 ++ src/security/tpm/Makefile.inc | 45 +++-- src/security/tpm/tspi.h | 7 + .../{vboot/vboot_crtm.c => tpm/tspi/crtm.c} | 163 +++++++++--------- .../{vboot/vboot_crtm.h => tpm/tspi/crtm.h} | 19 +- src/security/tpm/tspi/log.c | 12 +- src/security/tpm/tspi/tspi.c | 52 ++++-- src/security/vboot/Kconfig | 16 -- src/security/vboot/Makefile.inc | 8 - src/security/vboot/symbols.h | 2 - src/security/vboot/vboot_logic.c | 16 +- .../cavium/cn81xx/include/soc/memlayout.ld | 2 +- .../mediatek/mt8173/include/soc/memlayout.ld | 2 +- .../mediatek/mt8183/include/soc/memlayout.ld | 2 +- .../nvidia/tegra124/include/soc/memlayout.ld | 2 +- .../nvidia/tegra210/include/soc/memlayout.ld | 2 +- .../exynos5250/include/soc/memlayout.ld | 2 +- 25 files changed, 219 insertions(+), 187 deletions(-) rename src/security/{vboot/vboot_crtm.c => tpm/tspi/crtm.c} (52%) rename src/security/{vboot/vboot_crtm.h => tpm/tspi/crtm.h} (78%) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5e5493a355..92b26a0877 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -20,8 +20,8 @@ /* Vboot measured boot TCPA log measurements. * Needs to be transferred until CBMEM is available */ -#if CONFIG(VBOOT_MEASURED_BOOT) - VBOOT2_TPM_LOG(., 2K) +#if CONFIG(TPM_MEASURED_BOOT) + TPM_TCPA_LOG(., 2K) #endif /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 62c9f7b7aa..bf4b2c5323 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -159,9 +159,9 @@ STR(vboot2 work buffer size must be equivalent to \ VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE! (sz))); -#define VBOOT2_TPM_LOG(addr, size) \ - REGION(vboot2_tpm_log, addr, size, 16) \ - _ = ASSERT(size >= 2K, "vboot2 tpm log buffer must be at least 2K!"); +#define TPM_TCPA_LOG(addr, size) \ + REGION(tpm_tcpa_log, addr, size, 16) \ + _ = ASSERT(size >= 2K, "tpm tcpa log buffer must be at least 2K!"); #if ENV_VERSTAGE #define VERSTAGE(addr, sz) \ diff --git a/src/include/symbols.h b/src/include/symbols.h index 94e4668ecb..e37405d4a1 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -34,8 +34,11 @@ DECLARE_REGION(preram_cbfs_cache) DECLARE_REGION(postram_cbfs_cache) DECLARE_REGION(cbfs_cache) DECLARE_REGION(fmap_cache) -DECLARE_REGION(payload) +DECLARE_REGION(tpm_tcpa_log) +/* Regions for execution units. */ + +DECLARE_REGION(payload) /* "program" always refers to the current execution unit. */ DECLARE_REGION(program) /* __size is always the maximum amount allocated in memlayout, whereas diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 4f0b443360..4392ab7ab0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -13,19 +13,19 @@ */ #include -#include -#include -#include #include #include #include +#include #include +#include #include +#include +#include +#include +#include #include #include -#include -#include -#include #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) @@ -60,7 +60,7 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) } if (!ret) - if (vboot_measure_cbfs_hook(fh, name)) + if (tspi_measure_cbfs_hook(fh, name)) return -1; return ret; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 6adf4e9c41..0f32907da2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -9,12 +9,12 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI + select TPM_MEASURED_BOOT config CBFS_SIZE default 0xb4e000 config VBOOT - select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index b10bdc846b..55fb4b16bb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI select DRIVERS_I2C_PTN3460 + select TPM_MEASURED_BOOT config UART_FOR_CONSOLE default 1 @@ -17,7 +18,6 @@ config CBFS_SIZE default 0xb4e000 config VBOOT - select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index e46a0de6f9..bd0b0d7162 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -12,12 +12,12 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI select DRIVERS_I2C_PTN3460 + select TPM_MEASURED_BOOT config CBFS_SIZE default 0xb4e000 config VBOOT - select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index 864e808f17..852294a01d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -11,9 +11,9 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI + select TPM_MEASURED_BOOT config VBOOT - select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 1766939c4c..d8652b2017 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -100,4 +100,21 @@ config TPM_STARTUP_IGNORE_POSTINIT or VBOOT on the Intel Arrandale processor, which issues a CPU-only reset during the romstage. +config TPM_MEASURED_BOOT + bool "Enable Measured Boot" + default n + select VBOOT_LIB + depends on TPM1 || TPM2 + depends on !VBOOT_RETURN_FROM_VERSTAGE + help + Enables measured boot (experimental) + +config TPM_MEASURED_BOOT_RUNTIME_DATA + string "Runtime data whitelist" + default "" + depends on TPM_MEASURED_BOOT + help + Runtime data whitelist of cbfs filenames. Needs to be a + comma separated list + endmenu # Trusted Platform Module (tpm) diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index a2d32cff89..c36183dd9b 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -6,22 +6,17 @@ ifeq ($(CONFIG_TPM1),y) ramstage-y += tss/tcg-1.2/tss.c romstage-y += tss/tcg-1.2/tss.c - -verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c -postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c +bootblock-y += tss/tcg-1.2/tss.c +verstage-y += tss/tcg-1.2/tss.c +postcar-y += tss/tcg-1.2/tss.c ## TSPI ramstage-y += tspi/tspi.c romstage-y += tspi/tspi.c - -verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c - -ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c -romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c -verstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c -postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c +bootblock-y += tspi/tspi.c +verstage-y += tspi/tspi.c +postcar-y += tspi/tspi.c endif # CONFIG_TPM1 @@ -39,17 +34,31 @@ verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c postcar-y += tss/tcg-2.0/tss_marshaling.c postcar-y += tss/tcg-2.0/tss.c +bootblock-y += tss/tcg-2.0/tss_marshaling.c +bootblock-y += tss/tcg-2.0/tss.c + ## TSPI ramstage-y += tspi/tspi.c romstage-y += tspi/tspi.c - +bootblock-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c - -ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c -romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c -verstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c -postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c +postcar-y += tspi/tspi.c endif # CONFIG_TPM2 + +ifeq ($(CONFIG_TPM_MEASURED_BOOT),y) + +bootblock-y += tspi/crtm.c +verstage-y += tspi/crtm.c +romstage-y += tspi/crtm.c +ramstage-y += tspi/crtm.c +postcar-y += tspi/crtm.c + +ramstage-y += tspi/log.c +romstage-y += tspi/log.c +verstage-y += tspi/log.c +postcar-y += tspi/log.c +bootblock-y += tspi/log.c + +endif # CONFIG_TPM_MEASURED_BOOT diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 6854401d03..7ea90e280e 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -23,6 +23,12 @@ #define TPM_PCR_MAX_LEN 64 #define HASH_DATA_CHUNK_SIZE 1024 +/** + * Get the pointer to the single instance of global + * tcpa log data, and initialize it when necessary + */ +struct tcpa_table *tcpa_log_init(void); + /** * Clears the pre-RAM tcpa log data and initializes * any content with default values @@ -47,6 +53,7 @@ void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, */ void tcpa_log_dump(void *unused); + /** * Ask vboot for a digest and extend a TPM PCR with it. * @param pcr sets the pcr index diff --git a/src/security/vboot/vboot_crtm.c b/src/security/tpm/tspi/crtm.c similarity index 52% rename from src/security/vboot/vboot_crtm.c rename to src/security/tpm/tspi/crtm.c index 40b56ed881..dc7d7d21f0 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -15,12 +15,11 @@ #include #include #include -#include -#include +#include "crtm.h" #include /* - * This functions sets the TCPA log namespace + * This function sets the TCPA log namespace * for the cbfs file (region) lookup. */ static int create_tcpa_metadata(const struct region_device *rdev, @@ -28,11 +27,12 @@ static int create_tcpa_metadata(const struct region_device *rdev, { int i; struct region_device fmap; - static const char *fmap_cbfs_names[] = { - "COREBOOT", - "FW_MAIN_A", - "FW_MAIN_B", - "RW_LEGACY"}; + static const char *const fmap_cbfs_names[] = { + "COREBOOT", + "FW_MAIN_A", + "FW_MAIN_B", + "RW_LEGACY" + }; for (i = 0; i < ARRAY_SIZE(fmap_cbfs_names); i++) { if (fmap_locate_area_as_rdev(fmap_cbfs_names[i], &fmap) == 0) { @@ -49,17 +49,27 @@ static int create_tcpa_metadata(const struct region_device *rdev, return -1; } -uint32_t vboot_init_crtm(void) +static int tcpa_log_initialized; +static inline int tcpa_log_available(void) +{ + if (ENV_BOOTBLOCK) + return tcpa_log_initialized; + + return 1; +} + +uint32_t tspi_init_crtm(void) { struct prog bootblock = PROG_INIT(PROG_BOOTBLOCK, "bootblock"); - struct prog verstage = - PROG_INIT(PROG_VERSTAGE, CONFIG_CBFS_PREFIX "/verstage"); - struct prog romstage = - PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); - char tcpa_metadata[TCPA_PCR_HASH_NAME]; - /* Initialize TCPE PRERAM log. */ - tcpa_preram_log_clear(); + /* Initialize TCPA PRERAM log. */ + if (!tcpa_log_available()) { + tcpa_preram_log_clear(); + tcpa_log_initialized = 1; + } else { + printk(BIOS_WARNING, "TSPI: CRTM already initialized!\n"); + return VB2_SUCCESS; + } /* measure bootblock from RO */ struct cbfsf bootblock_data; @@ -71,66 +81,13 @@ uint32_t vboot_init_crtm(void) return VB2_ERROR_UNKNOWN; } else { if (cbfs_boot_locate(&bootblock_data, - prog_name(&bootblock), NULL) == 0) { - cbfs_file_data(prog_rdev(&bootblock), &bootblock_data); - - if (create_tcpa_metadata(prog_rdev(&bootblock), - prog_name(&bootblock), tcpa_metadata) < 0) - return VB2_ERROR_UNKNOWN; - - if (tpm_measure_region(prog_rdev(&bootblock), - TPM_CRTM_PCR, - tcpa_metadata)) - return VB2_ERROR_UNKNOWN; - } else { + prog_name(&bootblock), NULL)) { + /* + * measurement is done in + * tspi_measure_cbfs_hook() + */ printk(BIOS_INFO, - "VBOOT: Couldn't measure bootblock into CRTM!\n"); - return VB2_ERROR_UNKNOWN; - } - } - - if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { - struct cbfsf romstage_data; - /* measure romstage from RO */ - if (cbfs_boot_locate(&romstage_data, - prog_name(&romstage), NULL) == 0) { - cbfs_file_data(prog_rdev(&romstage), &romstage_data); - - if (create_tcpa_metadata(prog_rdev(&romstage), - prog_name(&romstage), tcpa_metadata) < 0) - return VB2_ERROR_UNKNOWN; - - if (tpm_measure_region(prog_rdev(&romstage), - TPM_CRTM_PCR, - tcpa_metadata)) - return VB2_ERROR_UNKNOWN; - } else { - printk(BIOS_INFO, - "VBOOT: Couldn't measure %s into CRTM!\n", - CONFIG_CBFS_PREFIX "/romstage"); - return VB2_ERROR_UNKNOWN; - } - } - - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) { - struct cbfsf verstage_data; - /* measure verstage from RO */ - if (cbfs_boot_locate(&verstage_data, - prog_name(&verstage), NULL) == 0) { - cbfs_file_data(prog_rdev(&verstage), &verstage_data); - - if (create_tcpa_metadata(prog_rdev(&verstage), - prog_name(&verstage), tcpa_metadata) < 0) - return VB2_ERROR_UNKNOWN; - - if (tpm_measure_region(prog_rdev(&verstage), - TPM_CRTM_PCR, - tcpa_metadata)) - return VB2_ERROR_UNKNOWN; - } else { - printk(BIOS_INFO, - "VBOOT: Couldn't measure %s into CRTM!\n", - CONFIG_CBFS_PREFIX "/verstage"); + "TSPI: Couldn't measure bootblock into CRTM!\n"); return VB2_ERROR_UNKNOWN; } } @@ -140,8 +97,8 @@ uint32_t vboot_init_crtm(void) static bool is_runtime_data(const char *name) { - const char *whitelist = CONFIG_VBOOT_MEASURED_BOOT_RUNTIME_DATA; - size_t whitelist_len = sizeof(CONFIG_VBOOT_MEASURED_BOOT_RUNTIME_DATA) - 1; + const char *whitelist = CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA; + size_t whitelist_len = sizeof(CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA) - 1; size_t name_len = strlen(name); int i; @@ -156,15 +113,21 @@ static bool is_runtime_data(const char *name) return false; } -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name) +uint32_t tspi_measure_cbfs_hook(struct cbfsf *fh, const char *name) { uint32_t pcr_index; uint32_t cbfs_type; struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; - if (!vboot_logic_executed()) - return 0; + if (!tcpa_log_available()) { + if (tspi_init_crtm() != VB2_SUCCESS) { + printk(BIOS_WARNING, + "Initializing CRTM failed!"); + return 0; + } + printk(BIOS_DEBUG, "CRTM initialized."); + } cbfsf_file_type(fh, &cbfs_type); cbfs_file_data(&rdev, fh); @@ -192,3 +155,43 @@ uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name) return tpm_measure_region(&rdev, pcr_index, tcpa_metadata); } + +int tspi_measure_cache_to_pcr(void) +{ + int i; + enum vb2_hash_algorithm hash_alg; + struct tcpa_table *tclt = tcpa_log_init(); + + if (!tclt) { + printk(BIOS_WARNING, "TCPA: Log non-existent!\n"); + return VB2_ERROR_UNKNOWN; + } + if (CONFIG(TPM1)) { + hash_alg = VB2_HASH_SHA1; + } else { /* CONFIG_TPM2 */ + hash_alg = VB2_HASH_SHA256; + } + + + printk(BIOS_DEBUG, "TPM: Write digests cached in TCPA log to PCR\n"); + for (i = 0; i < tclt->num_entries; i++) { + struct tcpa_entry *tce = &tclt->entries[i]; + if (tce) { + printk(BIOS_DEBUG, "TPM: Write digest for" + " %s into PCR %d\n", + tce->name, tce->pcr); + int result = tlcl_extend(tce->pcr, + tce->digest, + NULL); + if (result != TPM_SUCCESS) { + printk(BIOS_ERR, "TPM: Writing digest" + " of %s into PCR failed with error" + " %d\n", + tce->name, result); + return VB2_ERROR_UNKNOWN; + } + } + } + + return VB2_SUCCESS; +} diff --git a/src/security/vboot/vboot_crtm.h b/src/security/tpm/tspi/crtm.h similarity index 78% rename from src/security/vboot/vboot_crtm.h rename to src/security/tpm/tspi/crtm.h index ba3dd45abe..dfd91e1c0e 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#ifndef __SECURITY_VBOOT_CRTM_H__ -#define __SECURITY_VBOOT_CRTM_H__ +#ifndef __SECURITY_TSPI_CRTM_H__ +#define __SECURITY_TSPI_CRTM_H__ #include #include @@ -43,18 +43,23 @@ * Takes the current vboot context as parameter for s3 checks. * returns on success VB2_SUCCESS, else a vboot error. */ -uint32_t vboot_init_crtm(void); +uint32_t tspi_init_crtm(void); -#if CONFIG(VBOOT_MEASURED_BOOT) +/** + * Measure digests cached in TCPA log entries into PCRs + */ +int tspi_measure_cache_to_pcr(void); + +#if CONFIG(TPM_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) * fh is the cbfs file handle to measure * return 0 if successful, else an error */ -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +uint32_t tspi_measure_cbfs_hook(struct cbfsf *fh, const char *name); #else -#define vboot_measure_cbfs_hook(fh, name) 0 +#define tspi_measure_cbfs_hook(fh, name) 0 #endif -#endif /* __VBOOT_VBOOT_CRTM_H__ */ +#endif /* __SECURITY_TSPI_CRTM_H__ */ diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 068d78da19..e43f74d069 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -42,7 +42,7 @@ static struct tcpa_table *tcpa_cbmem_init(void) return tclt; } -static struct tcpa_table *tcpa_log_init(void) +struct tcpa_table *tcpa_log_init(void) { MAYBE_STATIC_BSS struct tcpa_table *tclt = NULL; @@ -50,12 +50,12 @@ static struct tcpa_table *tcpa_log_init(void) * If cbmem isn't available use CAR or SRAM */ if (!cbmem_possibly_online() && !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) - return (struct tcpa_table *)_vboot2_tpm_log; + return (struct tcpa_table *)_tpm_tcpa_log; else if (ENV_ROMSTAGE && !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) { tclt = tcpa_cbmem_init(); if (!tclt) - return (struct tcpa_table *)_vboot2_tpm_log; + return (struct tcpa_table *)_tpm_tcpa_log; } else { tclt = tcpa_cbmem_init(); } @@ -128,7 +128,7 @@ void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, void tcpa_preram_log_clear(void) { printk(BIOS_INFO, "TCPA: Clearing coreboot TCPA log\n"); - struct tcpa_table *tclt = (struct tcpa_table *)_vboot2_tpm_log; + struct tcpa_table *tclt = (struct tcpa_table *)_tpm_tcpa_log; tclt->max_entries = MAX_TCPA_LOG_ENTRIES; tclt->num_entries = 0; } @@ -136,7 +136,7 @@ void tcpa_preram_log_clear(void) #if !CONFIG(VBOOT_RETURN_FROM_VERSTAGE) static void recover_tcpa_log(int is_recovery) { - struct tcpa_table *preram_log = (struct tcpa_table *)_vboot2_tpm_log; + struct tcpa_table *preram_log = (struct tcpa_table *)_tpm_tcpa_log; struct tcpa_table *ram_log = NULL; int i; diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 0095183ca2..4f0cc972a7 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -14,13 +14,14 @@ #include #include +#include #include #include -#if CONFIG(VBOOT) +#include +#include +#include #include #include -#include -#endif #if CONFIG(TPM1) static uint32_t tpm1_invoke_state_machine(void) @@ -100,6 +101,18 @@ static uint32_t tpm_setup_epilogue(uint32_t result) return result; } +static int tpm_is_setup; +static inline int tspi_tpm_is_setup(void) +{ + if (CONFIG(VBOOT)) + return vboot_logic_executed() || tpm_is_setup; + + if (ENV_RAMSTAGE) + return tpm_is_setup; + + return 0; +} + /* * tpm_setup starts the TPM and establishes the root of trust for the * anti-rollback mechanism. tpm_setup can fail for three reasons. 1 A bug. @@ -170,7 +183,10 @@ uint32_t tpm_setup(int s3flag) #if CONFIG(TPM1) result = tpm1_invoke_state_machine(); #endif + if (CONFIG(TPM_MEASURED_BOOT)) + result = tspi_measure_cache_to_pcr(); + tpm_is_setup = 1; return tpm_setup_epilogue(result); } @@ -210,18 +226,27 @@ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, if (!digest) return TPM_E_IOERROR; - result = tlcl_extend(pcr, digest, NULL); - if (result != TPM_SUCCESS) - return result; + if (tspi_tpm_is_setup()) { + result = tlcl_lib_init(); + if (result != TPM_SUCCESS) { + printk(BIOS_ERR, "TPM: Can't initialize library.\n"); + return result; + } - if (CONFIG(VBOOT_MEASURED_BOOT)) + printk(BIOS_DEBUG, "TPM: Extending digest for %s into PCR %d\n", name, pcr); + result = tlcl_extend(pcr, digest, NULL); + if (result != TPM_SUCCESS) + return result; + } + + if (CONFIG(TPM_MEASURED_BOOT)) tcpa_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); return TPM_SUCCESS; } -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_LIB) uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, const char *rname) { @@ -234,11 +259,7 @@ uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, if (!rdev || !rname) return TPM_E_INVALID_ARG; - result = tlcl_lib_init(); - if (result != TPM_SUCCESS) { - printk(BIOS_ERR, "TPM: Can't initialize library.\n"); - return result; - } + if (CONFIG(TPM1)) { hash_alg = VB2_HASH_SHA1; } else { /* CONFIG_TPM2 */ @@ -277,7 +298,8 @@ uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, printk(BIOS_ERR, "TPM: Extending hash into PCR failed.\n"); return result; } - printk(BIOS_DEBUG, "TPM: Measured %s into PCR %d\n", rname, pcr); + printk(BIOS_DEBUG, "TPM: Digest of %s to PCR %d %s\n", + rname, pcr, tspi_tpm_is_setup() ? "measured" : "logged"); return TPM_SUCCESS; } -#endif /* VBOOT */ +#endif /* VBOOT_LIB */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 6e0021d58d..f273265054 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -35,22 +35,6 @@ if VBOOT comment "Anti-Rollback Protection disabled because mocking secdata is enabled." depends on VBOOT_MOCK_SECDATA -config VBOOT_MEASURED_BOOT - bool "Enable Measured Boot" - default n - depends on TPM1 || TPM2 - depends on !VBOOT_RETURN_FROM_VERSTAGE - help - Enables measured boot mode in vboot (experimental) - -config VBOOT_MEASURED_BOOT_RUNTIME_DATA - string "Runtime data whitelist" - default "" - depends on VBOOT_MEASURED_BOOT - help - Runtime data whitelist of cbfs filenames. Needs to be a comma separated - list - config VBOOT_SLOTS_RW_A bool "Firmware RO + RW_A" help diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index e7560dd911..d1cc2da807 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -105,14 +105,6 @@ romstage-y += vboot_common.c ramstage-y += vboot_common.c postcar-y += vboot_common.c -ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) -bootblock-y += vboot_crtm.c -verstage-y += vboot_crtm.c -romstage-y += vboot_crtm.c -ramstage-y += vboot_crtm.c -postcar-y += vboot_crtm.c -endif - bootblock-y += common.c verstage-y += vboot_logic.c verstage-y += common.c diff --git a/src/security/vboot/symbols.h b/src/security/vboot/symbols.h index 778c8ee949..8f6063efac 100644 --- a/src/security/vboot/symbols.h +++ b/src/security/vboot/symbols.h @@ -19,6 +19,4 @@ DECLARE_REGION(vboot2_work) -DECLARE_REGION(vboot2_tpm_log) - #endif /* __VBOOT_SYMBOLS_H__ */ diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index b72df9650b..80f7aaa86b 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -17,13 +17,13 @@ #include #include #include +#include +#include +#include +#include #include #include #include -#include -#include -#include -#include #include "antirollback.h" @@ -283,14 +283,6 @@ void verstage_main(void) antirollback_read_space_firmware(ctx); timestamp_add_now(TS_END_TPMINIT); - /* Enable measured boot mode */ - if (CONFIG(VBOOT_MEASURED_BOOT) && - !(ctx->flags & VB2_CONTEXT_S3_RESUME)) { - if (vboot_init_crtm() != VB2_SUCCESS) - die_with_post_code(POST_INVALID_ROM, - "Initializing measured boot mode failed!"); - } - if (get_recovery_mode_switch()) { ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 74786693db..f3b044235f 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -34,7 +34,7 @@ SECTIONS PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) - VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K) + TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K) VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 89ee8f4e31..2a617b7567 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -38,7 +38,7 @@ SECTIONS SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) - VBOOT2_TPM_LOG(0x00103000, 2K) + TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) PRERAM_CBMEM_CONSOLE(0x00104000, 12K) WATCHDOG_TOMBSTONE(0x00107000, 4) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 6e523d8e32..d2f9a060f8 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -30,7 +30,7 @@ SECTIONS { SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) - VBOOT2_TPM_LOG(0x00103000, 2K) + TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 0128a86048..adb47b1541 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -30,7 +30,7 @@ SECTIONS FMAP_CACHE(0x40005800, 2K) PRERAM_CBFS_CACHE(0x40006000, 14K) VBOOT2_WORK(0x40009800, 12K) - VBOOT2_TPM_LOG(0x4000D800, 2K) + TPM_TCPA_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 30K) VERSTAGE(0x40017800, 72K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index ff44591e94..fdd0e8811f 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -31,7 +31,7 @@ SECTIONS FMAP_CACHE(0x40000800, 2K) PRERAM_CBFS_CACHE(0x40001000, 28K) VBOOT2_WORK(0x40008000, 12K) - VBOOT2_TPM_LOG(0x4000B000, 2K) + TPM_TCPA_LOG(0x4000B000, 2K) #if ENV_ARM64 STACK(0x4000B800, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index db637fff28..d117aac828 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -32,7 +32,7 @@ SECTIONS TTB(0x2058000, 16K) PRERAM_CBFS_CACHE(0x205C000, 76K) FMAP_CACHE(0x206F000, 2K) - VBOOT2_TPM_LOG(0x206F800, 2K) + TPM_TCPA_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 12K) STACK(0x2074000, 16K) SRAM_END(0x2078000) From eff1306ea480c991b7340928f67cbf59e6e11433 Mon Sep 17 00:00:00 2001 From: Marcello Sylvester Bauer Date: Tue, 17 Mar 2020 10:55:04 +0100 Subject: [PATCH 0693/1463] Documentation/mb/lenovo: Test shrunken ME on Ivy Bridge Update the Lenovo Ivy Bridge documentation that no issues could be observed on W530. Tested on Lenovo W530 with stripped ME and found no issues: commit 93b0c7cfc632e7b57f1f4915886bf53397a12f25 * USB * Bluetooth * Wifi * Wifi-kill switch * libgfxinit * SATA * mSATA * Audio * SD-card * Ethernet * Keyboard * Fn-Keys * Display brightness * ACPI S3 resume * CPU temperature reporting * Stress test stable (intel_pstate no_turbo due to W530 overheating bug) * Youtube videos * stress -c 8 -m 1 -t 3600 Change-Id: I46d23d41cc6ade5e641a6ddb3f357a6036002edc Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39603 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- .../mainboard/lenovo/Ivy_Bridge_series.md | 15 +++++++++++++++ .../mainboard/lenovo/Sandy_Bridge_series.md | 4 ++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 2f83ffa8a8..f4f0efff6c 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -76,3 +76,18 @@ region. The update is then written into the EC once. [fl]: flashlayout_Ivy_Bridge.svg +## Reducing Intel Managment Engine firmware size + +It is possible to reduce the Intel ME firmware size to free additional +space for the `bios` region. This is usually referred to as *cleaning the ME* or +*stripping the ME*. +After reducing the Intel ME firmware size you must modify the original IFD, +[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write +each ROM using an [external programmer]. +Have a look at [me_cleaner] for more information. + +Tests on Lenovo W530 showed no issues with a stripped and shrunken ME firmware. + + +[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md +[external programmer]: ../../flash_tutorial/index.md diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index dbbbbeef30..37a75b9799 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -47,11 +47,11 @@ region. The update is then written into the EC once. ## Reducing Intel Managment Engine firmware size It is possible to reduce the Intel ME firmware size to free additional -space for the `bios` region. This is usually refered to as *cleaning the ME* or +space for the `bios` region. This is usually referred to as *cleaning the ME* or *stripping the ME*. After reducing the Intel ME firmware size you must modify the original IFD and then write a full ROM using an [external programmer]. -Have a look at the [me_cleaner] for more information. +Have a look at [me_cleaner] for more information. Tests on Lenovo X220 showed no issues with a stripped ME firmware. From 8602fb7f653ba127a3f6e3f277fc44143174feda Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 30 Mar 2020 12:17:54 +0200 Subject: [PATCH 0694/1463] soc/intel/common/block/cse: Add check for CSE enabled Exit print_me_fw_version if CSE is disabled. BUG=N/A TEST=tested on facebook monolith Change-Id: Ie3f1c2a5a7f96371a0da872efc3308850c382ba7 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/39920 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/common/block/cse/cse.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index b93594aa50..86ed038b06 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -827,6 +827,10 @@ void print_me_fw_version(void *unused) if (!CONFIG(CONSOLE_SERIAL)) return; + /* Ignore if CSE is disabled */ + if (!is_cse_enabled()) + return; + /* * Ignore if ME Firmware SKU type is custom since * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. From cfaf4c7ac88c08165ce4f95a0a20186ea6be7522 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 29 Mar 2020 17:29:48 +0200 Subject: [PATCH 0695/1463] superio/winbond/{w83627hf,w83977tf}: Use macro Change-Id: I3ac8dd2ba089970a18b460769dfc3fabf9395709 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39907 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/superio/winbond/w83627hf/acpi/superio.asl | 272 +++++++++--------- src/superio/winbond/w83977tf/acpi/superio.asl | 2 +- 2 files changed, 138 insertions(+), 136 deletions(-) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index d5c5ec9026..8f1861259a 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -43,6 +43,8 @@ * http://www.itox.com/pages/support/wdt/W83627HF.pdf */ +#include + Device(SIO) { Name (_HID, EisaId("PNP0A05")) Name (_STR, Unicode("Winbond W83627HF SuperIO")) @@ -52,7 +54,7 @@ Device(SIO) { Mutex(CRMX, 1) /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, 0x2E, 0x02) + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, @@ -137,8 +139,8 @@ Device(SIO) { Method (_CRS) { Return (ResourceTemplate () { - IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ - IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ + /* Announce the used I/O ports to the OS */ + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x02, 0x01) }) } @@ -147,7 +149,7 @@ Device(SIO) { Parameter is the LDN which should be accessed. Values >= 0xFF mean no LDN switch should be done. */ - Method (ENCM, 1) + Method (ENTER_CONFIG_MODE, 1) { Acquire (CRMX, 0xFFFF) Store (0x87, ADDR) @@ -160,7 +162,7 @@ Device(SIO) { /* Exit configuration mode (and release mutex) Method must be run after accessing the configuration region. */ - Method (EXCM) + Method (EXIT_CONFIG_MODE) { Store (0xAA, ADDR) Release (CRMX) @@ -168,25 +170,25 @@ Device(SIO) { /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ Method (_PSC) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (IPD, Local0) - EXCM () + EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } } /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, IPD) - EXCM () + EXIT_CONFIG_MODE () } /* PM: Switch to D3 by setting IPD high */ Method (_PS3) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, IPD) - EXCM () + EXIT_CONFIG_MODE () } #ifndef NO_W83627HF_FDC @@ -199,7 +201,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (0) + ENTER_CONFIG_MODE (0) If (ACTR) { Store (0x0F, Local0) } @@ -207,7 +209,7 @@ Device(SIO) { { Store (0x0D, Local0) } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } @@ -217,30 +219,30 @@ Device(SIO) { Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (FDPW, Local0) - EXCM () + EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } } /* Disable power saving mode */ Method (_PS0) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, FDPW) - EXCM () + EXIT_CONFIG_MODE () } /* Enable power saving mode */ Method (_PS3) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, FDPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_DIS) { - ENCM (0) + ENTER_CONFIG_MODE (0) Store (Zero, ACTR) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS) @@ -252,10 +254,10 @@ Device(SIO) { }) /* Get IO port info */ - ENCM (0) + ENTER_CONFIG_MODE (0) Store(IO1L, Local0) Store(IO1H, Local1) - EXCM () + EXIT_CONFIG_MODE () /* Calculate full IO port address */ Or(ShiftLeft(Local1, 8), Local0, Local0) @@ -298,11 +300,11 @@ Device(SIO) { CreateByteField (FDE, 12, FD4) // Get resources from logical device - ENCM (0) + ENTER_CONFIG_MODE (0) Store (ACTR, Local0) Store (IO1H, Local1) Store (IO1L, Local2) - EXCM () + EXIT_CONFIG_MODE () ShiftLeft(Local1, 8, Local1) Or(Local1, Local2, Local1) If (LNot(Local0)) { @@ -380,11 +382,11 @@ Device(SIO) { Divide(IOA0, 256, Local0, Local1) - ENCM (0) + ENTER_CONFIG_MODE (0) Store (Local0, IO1L) Store (Local1, IO1H) Store (One, ACTR) - EXCM () + EXIT_CONFIG_MODE () } } #endif @@ -399,10 +401,10 @@ Device(SIO) { Method (MODE, 1) { And(Arg0, 0x07, Local0) - ENCM (1) + ENTER_CONFIG_MODE (1) And(OPT1, 0x3, Local1) Or(Local1, Local0, OPT1) - EXCM() + EXIT_CONFIG_MODE() } Method (_INI) @@ -410,15 +412,15 @@ Device(SIO) { /* Deactivate DMA, even if set by BIOS. We don't announce it through _CRS and it's only useful in ECP mode which we don't support at the moment. */ - ENCM (1) + ENTER_CONFIG_MODE (1) Store (0x04, DMA0) - EXCM () + EXIT_CONFIG_MODE () } Method (_STA) { Store (0x00, Local0) - ENCM (1) + ENTER_CONFIG_MODE (1) And(OPT1, 0x3, Local1) If (ACTR) { If (LNotEqual(Local1, 2)) { @@ -431,34 +433,34 @@ Device(SIO) { { Store (0x0D, Local0) } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (PRPW, Local0) - EXCM () + EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, PRPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_PS3) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, PRPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_DIS) { - ENCM (1) + ENTER_CONFIG_MODE (1) Store (Zero, ACTR) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS) @@ -475,12 +477,12 @@ Device(SIO) { CreateWordField (CRS, IRQX._INT, IRQW) /* Get device settings */ - ENCM (1) + ENTER_CONFIG_MODE (1) Store (IO1L, Local0) Store (IO1H, Local1) Store (OPT1, Local2) Store (IRQ0, Local5) - EXCM () + EXIT_CONFIG_MODE () /* Calculate IO port and modify template */ Or(ShiftLeft(Local1, 8), Local0, Local0) Store(Local1, IOP0) @@ -571,7 +573,7 @@ Device(SIO) { Divide(IOA0, 256, Local0, Local1) - ENCM (1) + ENTER_CONFIG_MODE (1) /* IO port */ Store (Local0, IO1L) Store (Local1, IO1H) @@ -585,7 +587,7 @@ Device(SIO) { Subtract(FindSetLeftBit (IRQL), 1, IRQ0) /* Activate */ Store (One, ACTR) - EXCM () + EXIT_CONFIG_MODE () } } #endif @@ -600,7 +602,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (2) + ENTER_CONFIG_MODE (2) If (ACTR) { Store (0x0F, Local0) } @@ -608,35 +610,35 @@ Device(SIO) { { Store (0x0D, Local0) } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (UAPW, Local0) - EXCM () + EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, UAPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_PS3) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, UAPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_DIS) { - ENCM (2) + ENTER_CONFIG_MODE (2) Store (Zero, ACTR) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS, 0, Serialized) @@ -645,11 +647,11 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM (2) + ENTER_CONFIG_MODE (2) Store(IO1L, Local0) Store(IO1H, Local1) Store(IRQ0, Local2) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) @@ -702,12 +704,12 @@ Device(SIO) { Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM (2) + ENTER_CONFIG_MODE (2) Store (Local0, IO1L) Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) - EXCM () + EXIT_CONFIG_MODE () } } #endif @@ -722,7 +724,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (3) + ENTER_CONFIG_MODE (3) If (LNot(And(OPT2, 0x30))) { If (ACTR) { @@ -733,35 +735,35 @@ Device(SIO) { Store (0x0D, Local0) } } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (UBPW, Local0) - EXCM () + EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, UBPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_PS3) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, UBPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_DIS) { - ENCM (3) + ENTER_CONFIG_MODE (3) Store (Zero, ACTR) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS) @@ -770,11 +772,11 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM (3) + ENTER_CONFIG_MODE (3) Store(IO1L, Local0) Store(IO1H, Local1) Store(IRQ0, Local2) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) @@ -827,12 +829,12 @@ Device(SIO) { Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM (3) + ENTER_CONFIG_MODE (3) Store (Local0, IO1L) Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) - EXCM () + EXIT_CONFIG_MODE () } } #endif @@ -847,7 +849,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (3) + ENTER_CONFIG_MODE (3) If (And(OPT2, 0x30)) { If (ACTR) { @@ -858,35 +860,35 @@ Device(SIO) { Store (0x0D, Local0) } } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (UBPW, Local0) - EXCM () + EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, UBPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_PS3) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, UBPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_DIS) { - ENCM (3) + ENTER_CONFIG_MODE (3) Store (Zero, ACTR) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS) @@ -895,11 +897,11 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM (3) + ENTER_CONFIG_MODE (3) Store(IO1H, Local1) Store(IO1L, Local0) Store(IRQ0, Local2) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) @@ -952,12 +954,12 @@ Device(SIO) { Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM (3) + ENTER_CONFIG_MODE (3) Store (Local0, IO1L) Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) - EXCM () + EXIT_CONFIG_MODE () } } #endif @@ -973,7 +975,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (6) + ENTER_CONFIG_MODE (6) If (ACTR) { Store (0x0F, Local0) } @@ -981,15 +983,15 @@ Device(SIO) { { Store (0x0D, Local0) } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } Method (_DIS) { - ENCM (6) + ENTER_CONFIG_MODE (6) Store (Zero, ACTR) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS) @@ -998,11 +1000,11 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM (6) + ENTER_CONFIG_MODE (6) Store(IO1L, Local0) Store(IO1H, Local1) Store(IRQ0, Local2) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) @@ -1039,12 +1041,12 @@ Device(SIO) { Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM (6) + ENTER_CONFIG_MODE (6) Store (Local0, IO1L) Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) - EXCM () + EXIT_CONFIG_MODE () } } #endif @@ -1059,7 +1061,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (5) + ENTER_CONFIG_MODE (5) If (ACTR) { Store (0x0F, Local0) } @@ -1071,15 +1073,15 @@ Device(SIO) { Store (0x0D, Local0) #endif } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } Method (_DIS) { - ENCM (5) + ENTER_CONFIG_MODE (5) Store (Zero, ACTR) - EXCM () + EXIT_CONFIG_MODE () Notify(PS2M, 1) } @@ -1090,13 +1092,13 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) }) - ENCM (5) + ENTER_CONFIG_MODE (5) Store(IO1L, Local0) Store(IO1H, Local1) Store(IO2L, Local2) Store(IO2H, Local3) Store(IRQ0, Local4) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) Or(ShiftLeft(Local3, 8), Local2, Local2) @@ -1144,14 +1146,14 @@ Device(SIO) { Subtract(FindSetLeftBit (IRQL), 1, Local4) - ENCM (5) + ENTER_CONFIG_MODE (5) Store (Local0, IO1L) Store (Local1, IO1H) Store (Local2, IO2L) Store (Local3, IO2H) Store (Local4, IRQ0) Store (One, ACTR) - EXCM () + EXIT_CONFIG_MODE () Notify(PS2M, 1) } } @@ -1164,7 +1166,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (5) + ENTER_CONFIG_MODE (5) If (LAnd(ACTR, IRQ1) ) { Store (0x0F, Local0) } @@ -1176,15 +1178,15 @@ Device(SIO) { Store (0x0D, Local0) #endif } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } Method (_DIS) { - ENCM (5) + ENTER_CONFIG_MODE (5) Store (Zero, IRQ1) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS, 0, Serialized) @@ -1192,9 +1194,9 @@ Device(SIO) { Name (CRS, ResourceTemplate () { IRQNoFlags (IRQX) {} }) - ENCM (5) + ENTER_CONFIG_MODE (5) Store(IRQ1, Local4) - EXCM () + EXIT_CONFIG_MODE () CreateWordField (CRS, IRQX._INT, IRQW) Store (One, Local5) @@ -1223,10 +1225,10 @@ Device(SIO) { Subtract(FindSetLeftBit (IRQL), 1, Local0) - ENCM (5) + ENTER_CONFIG_MODE (5) Store (Local0, IRQ1) /* Only activates if KBD is active */ - EXCM () + EXIT_CONFIG_MODE () } } #endif @@ -1242,7 +1244,7 @@ Device(SIO) { Method (_STA) { Store(0, Local0) - ENCM (7) + ENTER_CONFIG_MODE (7) If (LOr(IO1L, IO1H)) { If (LOr(ACTR, ACT1)) { Store (0x0F, Local0) @@ -1251,7 +1253,7 @@ Device(SIO) { Store (0x0D, Local0) } } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } @@ -1261,11 +1263,11 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) IRQNoFlags (IRQX) {} }) - ENCM (7) + ENTER_CONFIG_MODE (7) Store(IO1L, Local0) Store(IO1H, Local1) Store(IRQ0, Local2) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) @@ -1297,7 +1299,7 @@ Device(SIO) { Method (_STA) { Store(0, Local0) - ENCM (7) + ENTER_CONFIG_MODE (7) If (LOr(IO2L, IO2H)) { If (LOr(ACTR, ACT2)) { Store (0x0F, Local0) @@ -1306,7 +1308,7 @@ Device(SIO) { Store (0x0D, Local0) } } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } @@ -1316,11 +1318,11 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) IRQNoFlags (IRQX) {} }) - ENCM (7) + ENTER_CONFIG_MODE (7) Store(IO2L, Local0) Store(IO2H, Local1) Store(IRQ1, Local2) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) @@ -1344,21 +1346,21 @@ Device(SIO) { /* ==== Suspend LED control if it is connected to the SuperIO ==== */ Method (SLED, 1) { - ENCM (9) + ENTER_CONFIG_MODE (9) Store(OPT4, Local0) And(Local0, 63, Local0) Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) - EXCM () + EXIT_CONFIG_MODE () } /* ===== Power LED control if it is connected to the SuperIO ===== */ Method (PLED, 1) { - ENCM (8) + ENTER_CONFIG_MODE (8) Store(OPT4, Local0) And(Local0, 63, Local0) Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) - EXCM () + EXIT_CONFIG_MODE () } #ifndef NO_W83627HF_HWMON @@ -1372,7 +1374,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM (11) + ENTER_CONFIG_MODE (11) If (ACTR) { Store (0x0F, Local0) } @@ -1380,7 +1382,7 @@ Device(SIO) { { Store (0x0D, Local0) } - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } @@ -1388,25 +1390,25 @@ Device(SIO) { { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (HWPW, Local0) - EXCM () + EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } } Method (_PS0) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, HWPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_PS3) { - ENCM (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, HWPW) - EXCM () + EXIT_CONFIG_MODE () } Method (_CRS, 0, Serialized) @@ -1415,11 +1417,11 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) IRQNoFlags (IRQX) {} }) - ENCM (11) + ENTER_CONFIG_MODE (11) Store(IO1L, Local0) Store(IO1H, Local1) Store(IRQ1, Local2) - EXCM () + EXIT_CONFIG_MODE () Or(ShiftLeft(Local1, 8), Local0, Local0) @@ -1449,9 +1451,9 @@ Device(SIO) { */ Method (WAKS) { - ENCM (10) + ENTER_CONFIG_MODE (10) Store (CRE3, Local0) - EXCM () + EXIT_CONFIG_MODE () Return (Local0) } } diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index c7a62cddd1..0a37ac9908 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -74,7 +74,7 @@ IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ Method (_PSC) { - ENTER_CONFIG_MODE (0xFF) + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (IPD, Local0) EXIT_CONFIG_MODE () If (Local0) { Return (3) } From 626963641883519925c98c403eb55ca339ce5b44 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 29 Mar 2020 13:20:59 -0500 Subject: [PATCH 0696/1463] mb/google/link: use default GMA display profile Link's DID data makes no sense, and ACPI backlight controls don't work as a result. Replace them with the default profile used by most/all other boards. Test: build/boot google/link, verify ACPI backlight controls functional Change-Id: Ia7cb3f10bd3c05ebaf414c17a8f94d2e9b40ae26 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39908 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/mainboard/google/link/devicetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index ec7fb201d7..477cd47c32 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "1" - register "gfx.did" = "{ 0x80000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000 }" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" From 98f609aad4b6d6b6a09efaa011a1f02116935acd Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 29 Mar 2020 13:37:07 -0500 Subject: [PATCH 0697/1463] mb/google/link: Use GENERIC_SPD_BIN Clean up Link's mainboard dir by putting the SPD files in a spd subdirectory like all other/newer boards use, and selecting GENERIC_SPD_BIN to include them in the build. Test: build google/link and verify spd.bin unchanged Change-Id: I9c2f9f77dbdd6552c5ae1e7a0df2051b9b85badc Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/link/Makefile.inc | 14 -------------- .../link/{ => spd}/elpida_4Gb_1600_x16.spd.hex | 0 .../{ => spd}/micron_4Gb_1600_1.35v_x16.spd.hex | 0 .../{ => spd}/samsung_4Gb_1600_1.35v_x16.spd.hex | 0 5 files changed, 1 insertion(+), 14 deletions(-) rename src/mainboard/google/link/{ => spd}/elpida_4Gb_1600_x16.spd.hex (100%) rename src/mainboard/google/link/{ => spd}/micron_4Gb_1600_1.35v_x16.spd.hex (100%) rename src/mainboard/google/link/{ => spd}/samsung_4Gb_1600_1.35v_x16.spd.hex (100%) diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 4a32ac2055..2c2a05d37d 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC + select GENERIC_SPD_BIN select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 9152656415..0e720e90ab 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -19,26 +19,12 @@ ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-y += mainboard_smi.c -SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! SPD_SOURCES = elpida_4Gb_1600_x16 SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 SPD_SOURCES += micron_4Gb_1600_1.35v_x16 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c diff --git a/src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex b/src/mainboard/google/link/spd/elpida_4Gb_1600_x16.spd.hex similarity index 100% rename from src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex rename to src/mainboard/google/link/spd/elpida_4Gb_1600_x16.spd.hex diff --git a/src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/google/link/spd/micron_4Gb_1600_1.35v_x16.spd.hex similarity index 100% rename from src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex rename to src/mainboard/google/link/spd/micron_4Gb_1600_1.35v_x16.spd.hex diff --git a/src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/google/link/spd/samsung_4Gb_1600_1.35v_x16.spd.hex similarity index 100% rename from src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex rename to src/mainboard/google/link/spd/samsung_4Gb_1600_1.35v_x16.spd.hex From 61ba3ac92e832259acd831ab6fab2946f57c7035 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 02:11:24 -0500 Subject: [PATCH 0698/1463] mb/google/slippy: Convert variants to use override devicetree Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Test: build all slippy variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/slippy/Kconfig | 4 +- .../slippy/{variants/falco => }/devicetree.cb | 11 -- .../slippy/variants/falco/overridetree.cb | 19 +++ .../google/slippy/variants/leon/devicetree.cb | 158 ------------------ .../slippy/variants/leon/overridetree.cb | 54 ++++++ .../slippy/variants/peppy/devicetree.cb | 130 -------------- .../slippy/variants/peppy/overridetree.cb | 23 +++ .../google/slippy/variants/wolf/devicetree.cb | 131 --------------- .../slippy/variants/wolf/overridetree.cb | 25 +++ 9 files changed, 123 insertions(+), 432 deletions(-) rename src/mainboard/google/slippy/{variants/falco => }/devicetree.cb (87%) create mode 100644 src/mainboard/google/slippy/variants/falco/overridetree.cb delete mode 100644 src/mainboard/google/slippy/variants/leon/devicetree.cb create mode 100644 src/mainboard/google/slippy/variants/leon/overridetree.cb delete mode 100644 src/mainboard/google/slippy/variants/peppy/devicetree.cb create mode 100644 src/mainboard/google/slippy/variants/peppy/overridetree.cb delete mode 100644 src/mainboard/google/slippy/variants/wolf/devicetree.cb create mode 100644 src/mainboard/google/slippy/variants/wolf/overridetree.cb diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 94ade7a546..21659ab675 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -48,9 +48,9 @@ config MAINBOARD_FAMILY string default "Google_Slippy" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAX_CPUS int diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb similarity index 87% rename from src/mainboard/google/slippy/variants/falco/devicetree.cb rename to src/mainboard/google/slippy/devicetree.cb index 887ec4afcb..3d98d745a3 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -14,14 +14,6 @@ chip northbridge/intel/haswell # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) - register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) - register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) - device cpu_cluster 0 on chip cpu/intel/haswell device lapic 0 on end @@ -79,9 +71,6 @@ chip northbridge/intel/haswell # Route all USB ports to XHCI per default register "xhci_default" = "1" - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" - device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb new file mode 100644 index 0000000000..c163202e99 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -0,0 +1,19 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) + register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) + register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) + + device domain 0 on + + chip southbridge/intel/lynxpoint + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013e0000" + end + end +end diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb deleted file mode 100644 index 27ce945dc5..0000000000 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ /dev/null @@ -1,158 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on # SMBus - chip drivers/i2c/rtd2132 - # Panel Power Timings (1 ms units) - # Note: the panel Tx timings are very - # different from the LVDS bridge - # Tx timing settings. Below is a mapping - # for RTD2132 -> Panel timings. - # T1 = T2 - # T2 = T8 + T10 + T12 - # T3 = T14 - # T4 = T15 - # T5 = T9 + T11 + T13 - # T6 = T3 - # T7 = T4 - register "t1" = "0x14" - register "t2" = "0xdc" - register "t3" = "0x0e" - register "t4" = "0x02" - register "t5" = "0xdc" - register "t6" = "0x14" - register "t7" = "0x208" - # LVDS Swap settings are normal. - register "lvds_swap" = "0" - # Enable Spread Sprectrum at 0.5% - register "sscg_percent" = "0x05" - device i2c 35 on end # (8bit address: 0x6A) - end # rtd2132 - end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb new file mode 100644 index 0000000000..f3b5c4a257 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -0,0 +1,54 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 1f.3 on # SMBus + chip drivers/i2c/rtd2132 + # Panel Power Timings (1 ms units) + # Note: the panel Tx timings are very + # different from the LVDS bridge + # Tx timing settings. Below is a mapping + # for RTD2132 -> Panel timings. + # T1 = T2 + # T2 = T8 + T10 + T12 + # T3 = T14 + # T4 = T15 + # T5 = T9 + T11 + T13 + # T6 = T3 + # T7 = T4 + register "t1" = "0x14" + register "t2" = "0xdc" + register "t3" = "0x0e" + register "t4" = "0x02" + register "t5" = "0xdc" + register "t6" = "0x14" + register "t7" = "0x208" + # LVDS Swap settings are normal. + register "lvds_swap" = "0" + # Enable Spread Sprectrum at 0.5% + register "sscg_percent" = "0x05" + device i2c 35 on end # (8bit address: 0x6A) + end # rtd2132 + end # SMBus + end + end +end diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb deleted file mode 100644 index d5e797e88d..0000000000 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ /dev/null @@ -1,130 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb new file mode 100644 index 0000000000..cd6a0df9ad --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -0,0 +1,23 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device domain 0 on + + chip southbridge/intel/lynxpoint + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + end + end +end diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb deleted file mode 100644 index ee0accaf2e..0000000000 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ /dev/null @@ -1,131 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) - register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) - register "gpu_panel_power_down_delay" = "500" # 50ms (T10) - register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb new file mode 100644 index 0000000000..5ccca1d821 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -0,0 +1,25 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) + register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) + register "gpu_panel_power_down_delay" = "500" # 50ms (T10) + register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + end + end +end From ea861ce83118217f1f639cd696dbdb8de87f8ccf Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 12:55:29 -0500 Subject: [PATCH 0699/1463] mb/51nb/x210: restore left USB3 port in devicetree Was accidentially removed in 6e50849 Change-Id: I090b6bc8863d17412cb1e23ac816c39f479290c1 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39937 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 50d217d170..a98dade9b9 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -116,6 +116,7 @@ chip soc/intel/skylake register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) # PL1 override 25W register "tdp_pl1_override" = "25" From bad08c2c29210530e584436a562a1c03a68eb693 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Thu, 13 Feb 2020 11:11:35 +0800 Subject: [PATCH 0700/1463] security/tpm: Include mrc.bin in CRTM if present mrc.bin, on platforms where it is present, is code executed on CPU, so it should be considered a part of CRTM. cbfs_locate_file_in_region() is hooked to measurement here too, since mrc.bin is loaded with it, and CBFS_TYPE_MRC (the type of mrc.bin) is measured to TPM_CRTM_PCR rather than TPM_RUNTIME_DATA_PCR. TODO: I have heard that SMM is too resource-limited to link with vboot library, so currently tspi_measure_cbfs_hook() is masked in SMM. Please correct me if I am wrong. Change-Id: Ib4c3cf47b919864056baf725001ca8a4aaafa110 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/38858 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/lib/cbfs.c | 13 ++++++++++--- src/security/tpm/tspi/crtm.c | 6 +++++- src/security/tpm/tspi/crtm.h | 2 +- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 4392ab7ab0..ccd7e6a7ce 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -56,7 +56,10 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) * Files can be added to the RO_REGION_ONLY config option to use this feature. */ printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); - ret = cbfs_locate_file_in_region(fh, "COREBOOT", name, type); + if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) + ERROR("RO region not found\n"); + else + ret = cbfs_locate(fh, &rdev, name, type); } if (!ret) @@ -86,14 +89,18 @@ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, const char *name, uint32_t *type) { struct region_device rdev; - + int ret = 0; if (fmap_locate_area_as_rdev(region_name, &rdev)) { LOG("%s region not found while looking for %s\n", region_name, name); return -1; } - return cbfs_locate(fh, &rdev, name, type); + ret = cbfs_locate(fh, &rdev, name, type); + if (!ret) + if (tspi_measure_cbfs_hook(fh, name)) + return -1; + return ret; } size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index dc7d7d21f0..304cea38e9 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -133,10 +133,14 @@ uint32_t tspi_measure_cbfs_hook(struct cbfsf *fh, const char *name) cbfs_file_data(&rdev, fh); switch (cbfs_type) { - case CBFS_TYPE_MRC: case CBFS_TYPE_MRC_CACHE: pcr_index = TPM_RUNTIME_DATA_PCR; break; + /* + * mrc.bin is code executed on CPU, so it + * should not be considered runtime data + */ + case CBFS_TYPE_MRC: case CBFS_TYPE_STAGE: case CBFS_TYPE_SELF: case CBFS_TYPE_FIT: diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index dfd91e1c0e..eb624951ca 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -50,7 +50,7 @@ uint32_t tspi_init_crtm(void); */ int tspi_measure_cache_to_pcr(void); -#if CONFIG(TPM_MEASURED_BOOT) +#if !ENV_SMM && CONFIG(TPM_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) * fh is the cbfs file handle to measure From 516c0a53384188f00b5df139b0840567dc8b8298 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 24 Feb 2020 23:08:35 +0800 Subject: [PATCH 0701/1463] security/vboot: relocate and rename vboot_platform_is_resuming() After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/include/bootmode.h | 6 ++++++ src/security/vboot/vboot_common.h | 6 ------ src/security/vboot/vboot_logic.c | 4 ++-- src/soc/amd/common/block/acpi/acpi.c | 14 ++++++++------ src/soc/intel/baytrail/pmutil.c | 4 ++-- src/soc/intel/braswell/pmutil.c | 4 ++-- src/soc/intel/broadwell/pmutil.c | 4 ++-- src/soc/intel/common/block/pmc/pmclib.c | 6 ++++-- src/southbridge/intel/common/pmbase.c | 4 ++-- .../eltan/security/verified_boot/vboot_check.c | 3 ++- 10 files changed, 30 insertions(+), 25 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 258eba1660..89e2c2cc8a 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -29,4 +29,10 @@ int display_init_required(void); int gfx_get_init_done(void); void gfx_set_init_done(int done); +/* + * Determine if the platform is resuming from suspend. Returns 0 when + * not resuming, > 0 if resuming, and < 0 on error. + */ +int platform_is_resuming(void); + #endif /* __BOOTMODE_H__ */ diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index e9221288ad..d825b82f29 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -48,12 +48,6 @@ int vboot_save_hash(void *digest, size_t digest_size); */ int vboot_retrieve_hash(void *digest, size_t digest_size); -/* - * Determine if the platform is resuming from suspend. Returns 0 when - * not resuming, > 0 if resuming, and < 0 on error. - */ -int vboot_platform_is_resuming(void); - /* ============================= VERSTAGE ================================== */ /* * Main logic for verified boot. verstage_main() is just the core vboot logic. diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 80f7aaa86b..ab5b53dc5f 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -113,7 +113,7 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) if (!CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return 0; - is_resume = vboot_platform_is_resuming(); + is_resume = platform_is_resuming(); if (is_resume > 0) { uint8_t saved_hash[VBOOT_MAX_HASH_SIZE]; @@ -272,7 +272,7 @@ void verstage_main(void) * does verification of memory init and thus must ensure it resumes with * the same slot that it booted from. */ if (CONFIG(RESUME_PATH_SAME_AS_BOOT) && - vboot_platform_is_resuming()) + platform_is_resuming()) ctx->flags |= VB2_CONTEXT_S3_RESUME; /* Read secdata from TPM. Initialize TPM if secdata not found. We don't diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 6f2f7c5ad7..4d99f7b535 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -12,15 +12,17 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include #include #include +#include +#include +#include +#include +#include #include #include +#include +#include void poweroff(void) { @@ -136,7 +138,7 @@ int acpi_get_sleep_type(void) return acpi_sleep_from_pm1(acpi_read16(MMIO_ACPI_PM1_CNT_BLK)); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(acpi_read16(MMIO_ACPI_PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 9e032cebfb..f0abcee7d8 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #if defined(__SIMPLE_DEVICE__) @@ -387,7 +387,7 @@ int vbnv_cmos_failed(void) return rtc_failure(); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 9c5079f8ed..016c45cccc 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -26,7 +27,6 @@ #include #include #include -#include #if defined(__SIMPLE_DEVICE__) @@ -380,7 +380,7 @@ int vbnv_cmos_failed(void) return rtc_failure(); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 172d8cda20..b170ff27d7 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -30,7 +31,6 @@ #include #include #include -#include /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -450,7 +450,7 @@ int acpi_sci_irq(void) return sci_irq; } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index d03348adec..47a4ed9f78 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -21,11 +22,12 @@ #include #include #include +#include +#include #include #include #include #include -#include static struct chipset_power_state power_state; @@ -440,7 +442,7 @@ void pmc_global_reset_enable(bool enable) } #endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 5174ed7cfa..2567b287c1 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -15,11 +15,11 @@ #include #include #include +#include #include #include #include #include -#include #include "pmbase.h" #include "pmutil.h" @@ -94,7 +94,7 @@ u8 read_pmbase8(const u8 addr) return inb(lpc_get_pmbase() + addr); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { u16 reg16 = read_pmbase16(PM1_STS); diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index fd0d82b3f7..63e4608553 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -290,7 +291,7 @@ void verified_boot_early_check(void) if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", - mb_measure(vboot_platform_is_resuming())); + mb_measure(platform_is_resuming())); } printk(BIOS_SPEW, "%s: process early verify list\n", __func__); From f02bf35e009e7e4c721bcc3fdf10693e4157dcf9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 17 Mar 2020 18:32:54 -0700 Subject: [PATCH 0702/1463] arch/x86/tables: Move max ACPI table size to Kconfig The maximum ACPI table size is currently hardcoded to 144 KiB. When using QEMU with TPM enabled there is ~200 KiB of ACPI tables returned by the fw_cfg interface, so in order to allow this to be overridden by a mainboard move it to Kconfig. This is seen when using a TPM with qemu as it will hang when processing the fw_cfg tables. qemu-system-x86_64 \ -machine q35 -enable-kvm -vga virtio -serial stdio \ -drive 'id=hd,file=disk.bin' -bios coreboot.rom \ -chardev 'socket,id=swtpm,path=/tmp/swtpm/swtpm-sock' \ -tpmdev 'emulator,id=tpm0,chardev=swtpm' \ -device 'tpm-tis,tpmdev=tpm0' Change-Id: Ib5baa8fe12cb9027a340875f1ccf5fef6f9460bd Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39832 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/arch/x86/Kconfig | 6 ++++++ src/arch/x86/tables.c | 7 +++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a4e5314ab5..21107aa48b 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -322,4 +322,10 @@ config MAX_PIRQ_LINKS table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set. +config MAX_ACPI_TABLE_SIZE_KB + int + default 144 + help + Set the maximum size of all ACPI tables in KiB. + endif diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 066e635675..7e653f7245 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -78,8 +78,7 @@ static unsigned long write_mptable(unsigned long rom_table_end) static unsigned long write_acpi_table(unsigned long rom_table_end) { unsigned long high_table_pointer; - -#define MAX_ACPI_SIZE (144 * 1024) + const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB; post_code(0x9c); @@ -96,7 +95,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end) * how far we get. */ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_ACPI, - MAX_ACPI_SIZE); + max_acpi_size); if (high_table_pointer) { unsigned long acpi_start = high_table_pointer; unsigned long new_high_table_pointer; @@ -104,7 +103,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end) rom_table_end = ALIGN_UP(rom_table_end, 16); new_high_table_pointer = write_acpi_tables(high_table_pointer); if (new_high_table_pointer > (high_table_pointer - + MAX_ACPI_SIZE)) + + max_acpi_size)) printk(BIOS_ERR, "ERROR: Increase ACPI size\n"); printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", new_high_table_pointer - high_table_pointer); From 9f5c8503d10f43b4236439a5a58c3f25a8a6c5e1 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 17 Mar 2020 18:35:21 -0700 Subject: [PATCH 0703/1463] mb/emulation/qemu-q35: Increase max size of ACPI tables When the TPM is enabled in QEMU the fw_cfg interface will return ~200KiB of ACPI tables, so this needs to be increased from the default in order to be able to boot. This is seen when using a TPM with qemu as it will hang when processing the fw_cfg tables. qemu-system-x86_64 \ -machine q35 -enable-kvm -vga virtio -serial stdio \ -drive 'id=hd,file=disk.bin' -bios coreboot.rom \ -chardev 'socket,id=swtpm,path=/tmp/swtpm/swtpm-sock' \ -tpmdev 'emulator,id=tpm0,chardev=swtpm' \ -device 'tpm-tis,tpmdev=tpm0' Change-Id: I21980aace8e86e636f5ae7b55148f4c31404edba Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39833 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/emulation/qemu-q35/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index ee430d0aeb..71841fb591 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -51,6 +51,11 @@ config MMCONF_BASE_ADDRESS hex default 0xb0000000 +# fw_cfg tables can be larger than the default when TPM is enabled +config MAX_ACPI_TABLE_SIZE_KB + int + default 224 + # Skip the first 64KiB as coreboot table pointer is installed # at address 0 config DCACHE_RAM_BASE From ddd4f9a7179ccc0772f1a26cdb70d68c19ae9140 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 17 Mar 2020 18:46:28 -0700 Subject: [PATCH 0704/1463] mb/emulation/qemu-i440fx: Reserve low memory Ensure that the low memory is properly reserved so it does not get marked as normal RAM and get wiped or reused by firmware or the kernel. This ensures that the low RSDP is always available for the kernel. This is only noticed if something wipes the RSDP before the kernel boots, which happens if you use the depthcharge payload and boot in developer mode. Change-Id: I7295018416229bc957ecbf26f77623a57965557e Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39834 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index b30723dd74..355f13cd36 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -129,6 +129,12 @@ static void cpu_pci_domain_read_resources(struct device *dev) "debugcon"); } + /* A segment is legacy VGA region */ + mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); + + /* C segment to 1MB is reserved RAM (low tables) */ + reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB); + if (q35 && ((tomk * 1024) < 0xb0000000)) { /* * Reserve the region between top-of-ram and the From b40e780f8bf8f23337cf5125afdd4c3e04ec5d8c Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 17 Mar 2020 18:47:36 -0700 Subject: [PATCH 0705/1463] mb/emulation/qemu-i440fx: Add acpi_name handler for QEMU QEMU does not have a separate northbridge chip, so the mainboard needs to handle the ACPI name and paths so that devices can get generated into the SSDT properly. This fixes the PIRQ and TPM table generation. This issue can be seen in the coreboot output: ACPI_PIRQ_GEN: Missing LPCB ACPI path Change-Id: Ifc7d4359eea38ac0b55d655e39191ae7f8655fe4 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39835 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- .../emulation/qemu-i440fx/northbridge.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 355f13cd36..74e52de095 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -229,6 +229,20 @@ static int qemu_get_smbios_data(struct device *dev, int *handle, unsigned long * return len; } #endif + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *qemu_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) + return NULL; + + return NULL; +} +#endif + static struct device_operations pci_domain_ops = { .read_resources = cpu_pci_domain_read_resources, .set_resources = cpu_pci_domain_set_resources, @@ -238,6 +252,9 @@ static struct device_operations pci_domain_ops = { #if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = qemu_get_smbios_data, #endif +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = qemu_acpi_name, +#endif }; static void cpu_bus_init(struct device *dev) From 516967c681a1cadfb053d8f4c098826eca743131 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 17 Mar 2020 18:49:39 -0700 Subject: [PATCH 0706/1463] mb/emulation/qemu-q35: Enable option for TPM This enables the mainboard to use a TPM if it is selected in the configuration. By default this does nothing, but it allows the TPM to be enabled and used with the CONFIG_USER_TPM2 Kconfig option. Using a TPM with QEMU requires either a physical TPM backend or the swtpm package with a socket: -chardev socket,id=swtpm,path=/tmp/swtpm/socket -tpmdev emulator,id=tpm0,chardev=swtpm -device tpm-tis,tpmdev=tpm0 Change-Id: I0d79a5a0f590c57998ababb660b52d9e3ed2d484 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39836 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/mainboard/emulation/qemu-q35/Kconfig | 1 + src/mainboard/emulation/qemu-q35/devicetree.cb | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 71841fb591..ee6406049c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_LPC_TPM config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb index c032606e67..ff0589fa60 100644 --- a/src/mainboard/emulation/qemu-q35/devicetree.cb +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -8,7 +8,11 @@ chip mainboard/emulation/qemu-q35 device pci 0.0 mandatory end # northbridge (q35) chip southbridge/intel/i82801ix # present unconditionally - device pci 1f.0 mandatory end # LPC + device pci 1f.0 mandatory + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC device pci 1f.2 on end # SATA device pci 1f.3 on end # SMBus From 14cf3245fe0a3ff362712527492328a9fe055c6f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 17 Mar 2020 18:54:39 -0700 Subject: [PATCH 0707/1463] mb/emulation/qemu-q35: Enable CHROMEOS as an option Allow Chrome OS to be enabled for this QEMU target. By default this does not change anything unless it is selected in the build configuration, but it makes it possible. Native VGA init is not forced when Chrome OS is enabled because the drm-bochs driver does not work with chrome (even the latest upstream kernel driver with drm atomic support) but it does work with virtio. The coreboot graphics init needs to match what is selected with qemu (with -vga std or -vga virtio) which in turn will determine which kernel driver is used. A second FMAP is added with both RW-A and RW-B regions which is required by chromeos. Recovery mode can be entered by supplying a custom fw_cfg option when launching qemu: -fw_cfg name=opt/cros/recovery,string=1 Change-Id: I24b4532ea961e68558663292c99d121f0a30ce3b Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39837 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/emulation/qemu-q35/Kconfig | 8 ++- src/mainboard/emulation/qemu-q35/Makefile.inc | 4 ++ src/mainboard/emulation/qemu-q35/chromeos.c | 58 +++++++++++++++++++ .../emulation/qemu-q35/vboot-rwab-16M.fmd | 28 +++++++++ 4 files changed, 95 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/emulation/qemu-q35/chromeos.c create mode 100644 src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index ee6406049c..31aa3d8723 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,15 +11,16 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_2048 if !VBOOT select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_CHROMEOS config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT + select VBOOT_NO_BOARD_SUPPORT if !CHROMEOS select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC @@ -27,7 +28,8 @@ config VBOOT config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB if VBOOT diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 133a213cc6..e142d4d5c1 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -10,3 +10,7 @@ postcar-y += ../qemu-i440fx/exit_car.S ramstage-y += ../qemu-i440fx/fw_cfg.c ramstage-y += ../qemu-i440fx/memmap.c ramstage-y += ../qemu-i440fx/northbridge.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c new file mode 100644 index 0000000000..50e48caf98 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include "../qemu-i440fx/fw_cfg.h" + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return 0; +} + +/* + * Enable recovery mode with fw_cfg option to qemu: + * -fw_cfg name=opt/cros/recovery,string=1 + */ +int get_recovery_mode_switch(void) +{ + FWCfgFile f; + + if (!fw_cfg_check_file(&f, "opt/cros/recovery")) { + uint8_t rec_mode; + if (f.size != 1) { + printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size); + return 0; + } + fw_cfg_get(f.select, &rec_mode, f.size); + if (rec_mode == '1') { + printk(BIOS_INFO, "Recovery is enabled.\n"); + return 1; + } + } + + return 0; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd new file mode 100644 index 0000000000..fcbfa95b69 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd @@ -0,0 +1,28 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x1c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x1c0000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 + } + RW_VPD(PRESERVE) 0x1000 + RW_LEGACY(CBFS) 0x10000 + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} From 6343cd846a55b228f08843e07c75f48aeadede0a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 27 Mar 2020 12:13:41 -0500 Subject: [PATCH 0708/1463] drivers/intel/gma: fold gma.asl into default_brightness_levels.asl Including gma.asl at the platform level (vs the board level) means that even desktop boards need to include the default brightness levels, which makes no sense. To begin to clean this up, include gma.asl in default_brightness_levels.asl (as well as the handful of board-specific brightness files) and remove it from the various platforms. A follow-on commit will remove default_brightness_levels.asl from all boards which lack an internal display. Change-Id: I8063deeef4ab6d6ab34ed9b0be5b1d541d6e9b6b Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39878 Reviewed-by: Benjamin Doron Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/acpi/default_brightness_levels.asl | 2 ++ .../roda/rv11/variants/rv11/include/acpi/brightness_levels.asl | 2 ++ .../roda/rv11/variants/rw11/include/acpi/brightness_levels.asl | 2 ++ src/northbridge/intel/gm45/acpi/gm45.asl | 3 --- src/northbridge/intel/haswell/acpi/haswell.asl | 3 --- src/northbridge/intel/ironlake/acpi/ironlake.asl | 3 --- src/northbridge/intel/sandybridge/acpi/sandybridge.asl | 3 --- src/northbridge/intel/x4x/acpi/x4x.asl | 3 --- 8 files changed, 6 insertions(+), 15 deletions(-) diff --git a/src/drivers/intel/gma/acpi/default_brightness_levels.asl b/src/drivers/intel/gma/acpi/default_brightness_levels.asl index 6c6f35ee28..b584c0925a 100644 --- a/src/drivers/intel/gma/acpi/default_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/default_brightness_levels.asl @@ -1,3 +1,5 @@ +#include "gma.asl" + Scope (GFX0) { Name (BRIG, Package (0x12) diff --git a/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl b/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl index 70732c8d6e..b92589a075 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl +++ b/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include + Scope (GFX0) { Name (BRIG, Package (13) diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl index 52a456815a..506de019a5 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl +++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include + Scope (GFX0) { Name (BRIG, Package (13) diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 8a30212d1d..576ab96bb6 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -73,6 +73,3 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" - -// Integrated graphics 0:2.0 -#include diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 900c6c3396..03b17ab6da 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -46,6 +46,3 @@ Device (PDRC) Return(PDRS) } } - -// Integrated graphics 0:2.0 -#include diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 2997dea951..61db605698 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -49,6 +49,3 @@ Device (PDRC) Return(PDRS) } } - -// Integrated graphics 0:2.0 -#include diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 202671a3e5..2dd5c00f31 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -53,6 +53,3 @@ Device (PDRC) Return(PDRS) } } - -// Integrated graphics 0:2.0 -#include diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 09849e3b17..947b67865b 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -43,6 +43,3 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" - -// Integrated graphics 0:2.0 -#include From 175ffd827adfb1f3c54ad6070a02538fb6893aa2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 29 Mar 2020 18:20:23 -0500 Subject: [PATCH 0709/1463] device/Kconfig: fix circular dependency for RUN_FSP_GOP Change Graphics Init default for RUN_FSP_GOP to depend on INTEL_GMA_HAVE_VBT rather than INTEL_GMA_ADD_VBT, since RUN_FSP_GOP selects INTEL_GMA_ADD_VBT for several Intel SoC's. Test: create default config for gogle/cyan, RUN_FSP_GOP still default display init selection but no more circular dependency warning from config. Change-Id: I8b978d9938c3d0024d4dd40000b988430664cee7 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39910 Tested-by: build bot (Jenkins) Reviewed-by: Benjamin Doron Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/device/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 64f1693e99..951062c1eb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -69,7 +69,7 @@ choice default VGA_ROM_RUN if VGA_BIOS default MAINBOARD_DO_NATIVE_VGA_INIT default MAINBOARD_USE_LIBGFXINIT - default RUN_FSP_GOP if INTEL_GMA_ADD_VBT + default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT config MAINBOARD_DO_NATIVE_VGA_INIT bool "Use native graphics init" From b8b8ec832360ada5a313f10938bb6cfc310a11eb Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Mon, 30 Mar 2020 16:52:19 +0530 Subject: [PATCH 0710/1463] soc/intel/common/block: Add missing include Include types.h in src/soc/intel/common/block/include/intelblocks/cse.h to use type bool. Without this, there can be a build error like below, src/soc/intel/common/block/include/intelblocks/cse.h:208:1: error: unknown type name 'bool'; did you mean '_Bool'? bool cse_is_hfs1_com_soft_temp_disable(void); ^~~~ _Bool src/soc/intel/common/block/include/intelblocks/cse.h:214:1: error: unknown type name 'bool'; did you mean '_Bool'? bool cse_is_hfs3_fw_sku_custom(void); Signed-off-by: Rizwan Qureshi Change-Id: I92ee533bca7dc255f7a341b2a68bbc09900996a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39922 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/soc/intel/common/block/include/intelblocks/cse.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 2c813833d0..ead5d41e8c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -17,6 +17,7 @@ #define SOC_INTEL_COMMON_CSE_H #include +#include /* MKHI Command groups */ #define MKHI_GROUP_ID_CBM 0x0 From 03a3404d5b9c198c4ac74eb076df108149534b19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 31 Mar 2020 13:36:23 +0200 Subject: [PATCH 0711/1463] mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway. Signed-off-by: Michał Żygowski Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/pcengines/apu2/OemCustomize.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index e47a2c8317..8b6cd038e8 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -35,7 +35,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_PORT3_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -47,7 +47,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -59,7 +59,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -83,7 +83,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_GFX_RESET_ID, - ClkPmSupportEnabled) + 0) } }; From 4c0432ae65e522be43a0c03d8a61e689eea0cc1b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 16:46:57 +0200 Subject: [PATCH 0712/1463] superio/smsc: Improve code formatting Change-Id: Ia9a3f7795178400de39b36471f4169a9f5a3b08b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39931 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/superio/smsc/lpc47m10x/lpc47m10x.h | 16 ++++++++-------- src/superio/smsc/lpc47m15x/lpc47m15x.h | 16 ++++++++-------- src/superio/smsc/sch5147/acpi/superio.asl | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index d096b37848..8f58c7c431 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -7,14 +7,14 @@ #include #include -#define LPC47M10X2_FDC 0 /* Floppy */ -#define LPC47M10X2_PP 3 /* Parallel Port */ -#define LPC47M10X2_SP1 4 /* Com1 */ -#define LPC47M10X2_SP2 5 /* Com2 */ -#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */ -#define LPC47M10X2_GAME 9 /* GAME */ -#define LPC47M10X2_PME 10 /* PME reg*/ -#define LPC47M10X2_MPU 11 /* MPU-401 MIDI */ +#define LPC47M10X2_FDC 0 /* Floppy */ +#define LPC47M10X2_PP 3 /* Parallel Port */ +#define LPC47M10X2_SP1 4 /* Com1 */ +#define LPC47M10X2_SP2 5 /* Com2 */ +#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */ +#define LPC47M10X2_GAME 9 /* GAME */ +#define LPC47M10X2_PME 10 /* PME reg*/ +#define LPC47M10X2_MPU 11 /* MPU-401 MIDI */ #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x.h b/src/superio/smsc/lpc47m15x/lpc47m15x.h index 44fce874ba..0baa21ea9f 100644 --- a/src/superio/smsc/lpc47m15x/lpc47m15x.h +++ b/src/superio/smsc/lpc47m15x/lpc47m15x.h @@ -4,14 +4,14 @@ #ifndef SUPERIO_SMSC_LPC47M15X_H #define SUPERIO_SMSC_LPC47M15X_H -#define LPC47M15X_FDC 0 /* Floppy */ -#define LPC47M15X_PP 3 /* Parallel Port */ -#define LPC47M15X_SP1 4 /* Com1 */ -#define LPC47M15X_SP2 5 /* Com2 */ -#define LPC47M15X_KBC 7 /* Keyboard & Mouse */ -#define LPC47M15X_GAME 9 /* GAME */ -#define LPC47M15X_PME 10 /* PME reg*/ -#define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/ +#define LPC47M15X_FDC 0 /* Floppy */ +#define LPC47M15X_PP 3 /* Parallel Port */ +#define LPC47M15X_SP1 4 /* Com1 */ +#define LPC47M15X_SP2 5 /* Com2 */ +#define LPC47M15X_KBC 7 /* Keyboard & Mouse */ +#define LPC47M15X_GAME 9 /* GAME */ +#define LPC47M15X_PME 10 /* PME reg*/ +#define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/ #define LPC47M15X2_MAX_CONFIG_REGISTER 0x5F diff --git a/src/superio/smsc/sch5147/acpi/superio.asl b/src/superio/smsc/sch5147/acpi/superio.asl index 15467b4c16..ff234c45a5 100644 --- a/src/superio/smsc/sch5147/acpi/superio.asl +++ b/src/superio/smsc/sch5147/acpi/superio.asl @@ -45,7 +45,7 @@ Device(SUPERIO_DEV) { Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_DATA_REG, 8 } IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { From e8fcf1bf8df1e94f84a15815343660360cd12299 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 16:47:28 +0200 Subject: [PATCH 0713/1463] superio/winbond: Improve code formatting Change-Id: Ia63e21b957d89690f36929f9ffbe8a7bf8f0e84c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39932 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- .../winbond/w83627dhg/acpi/superio.asl | 8 +- src/superio/winbond/w83627dhg/w83627dhg.h | 24 +-- src/superio/winbond/w83627ehg/w83627ehg.h | 22 +-- src/superio/winbond/w83627hf/acpi/superio.asl | 160 +++++++++--------- src/superio/winbond/w83977tf/acpi/superio.asl | 18 +- 5 files changed, 116 insertions(+), 116 deletions(-) diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index f86f16946e..ea4aebafd2 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -50,7 +50,7 @@ Device(SUPERIO_DEV) { Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_DATA_REG, 8 } IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { @@ -118,14 +118,14 @@ Device(SUPERIO_DEV) { Else { Return (0) } } - /* PM: Switch to D0 by setting IPD low */ + /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, IPD) EXIT_CONFIG_MODE () } - /* PM: Switch to D3 by setting IPD high */ + /* PM: Switch to D3 by setting IPD high */ Method (_PS3) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, IPD) @@ -133,7 +133,7 @@ Device(SUPERIO_DEV) { } /* Suspend LED: Write given three-bit value into appropriate register. - From the datasheet: + From the datasheet: 000 - drive pin constantly high 001 - drive 0.5Hz pulses 010 - drive pin constantly low diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 889c4f1bed..8d7c4a9651 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -6,20 +6,20 @@ #include -#define W83627DHG_FDC 0 /* Floppy */ -#define W83627DHG_PP 1 /* Parallel port */ -#define W83627DHG_SP1 2 /* Com1 */ -#define W83627DHG_SP2 3 /* Com2 */ -#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ -#define W83627DHG_SPI 6 /* Serial peripheral interface */ -#define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ -#define W83627DHG_ACPI 10 /* ACPI */ -#define W83627DHG_HWM 11 /* Hardware monitor */ -#define W83627DHG_PECI_SST 12 /* PECI, SST */ +#define W83627DHG_FDC 0 /* Floppy */ +#define W83627DHG_PP 1 /* Parallel port */ +#define W83627DHG_SP1 2 /* Com1 */ +#define W83627DHG_SP2 3 /* Com2 */ +#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627DHG_SPI 6 /* Serial peripheral interface */ +#define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ +#define W83627DHG_ACPI 10 /* ACPI */ +#define W83627DHG_HWM 11 /* Hardware monitor */ +#define W83627DHG_PECI_SST 12 /* PECI, SST */ /* The following are handled using "virtual LDNs" (hence the _V suffix). */ -#define W83627DHG_GPIO6_V 7 /* GPIO6 */ -#define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */ +#define W83627DHG_GPIO6_V 7 /* GPIO6 */ +#define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */ /* * Virtual devices sharing the enables are encoded as follows: diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 1dc7376c04..c22c7dbe98 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -4,19 +4,19 @@ #ifndef SUPERIO_WINBOND_W83627EHG_H #define SUPERIO_WINBOND_W83627EHG_H -#define W83627EHG_FDC 0 /* Floppy */ -#define W83627EHG_PP 1 /* Parallel port */ -#define W83627EHG_SP1 2 /* Com1 */ -#define W83627EHG_SP2 3 /* Com2 */ -#define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */ -#define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */ -#define W83627EHG_ACPI 10 /* ACPI */ -#define W83627EHG_HWM 11 /* Hardware monitor */ +#define W83627EHG_FDC 0 /* Floppy */ +#define W83627EHG_PP 1 /* Parallel port */ +#define W83627EHG_SP1 2 /* Com1 */ +#define W83627EHG_SP2 3 /* Com2 */ +#define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */ +#define W83627EHG_ACPI 10 /* ACPI */ +#define W83627EHG_HWM 11 /* Hardware monitor */ /* The following are handled using "virtual LDNs" (hence the _V suffix). */ -#define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */ -#define W83627EHG_GPIO_GAME_MIDI_V 7 /* GPIO1, GPIO6, game port, MIDI */ -#define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */ +#define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */ +#define W83627EHG_GPIO_GAME_MIDI_V 7 /* GPIO1, GPIO6, game port, MIDI */ +#define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */ /* * Virtual devices sharing the enables are encoded as follows: diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 8f1861259a..4d2fd2d5d3 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -57,83 +57,83 @@ Device(SIO) { OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) Field (CREG, ByteAcc, NoLock, Preserve) { - PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 } IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x02), - RST, 1, /* Soft reset */ - , 7, + RST, 1, /* Soft reset */ + , 7, Offset (0x07), - LDN, 8, /* Logical device selector */ + LDN, 8, /* Logical device selector */ Offset (0x20), - DID, 8, /* Device ID */ - DREV, 8, /* Device Revision */ - FDPW, 1, /* FDC Power Down */ - , 2, - PRPW, 1, /* PRT Power Down */ - UAPW, 1, /* UART A Power Down */ - UBPW, 1, /* UART B Power Down */ - HWPW, 1, /* HWM Power Down */ - , 1, - IPD, 1, /* Immediate Chip Power Down */ - , 7, - PNPS, 1, /* PnP Address Select Register Default Value Mode */ - , 1, - KBCR, 1, /* KBC enabled after system reset (read-only) */ - , 3, - CLKS, 1, /* Clock select */ - AQ16, 1, /* 16bit Address Qualification */ - FDCT, 1, /* Tristate FDC (?) */ - , 2, - PRTT, 1, /* Tristate parallel port (?) */ - URAT, 1, /* Tristate UART A (?) */ - URBT, 1, /* Tristate UART B (?) */ - , 2, - URAI, 1, /* UART A Legacy IRQ Select Disable */ - URBI, 1, /* UART B Legacy IRQ Select Disable */ - PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ - FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ - , 1, - LCKC, 1, /* Lock Configuration Registers */ + DID, 8, /* Device ID */ + DREV, 8, /* Device Revision */ + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + HWPW, 1, /* HWM Power Down */ + , 1, + IPD, 1, /* Immediate Chip Power Down */ + , 7, + PNPS, 1, /* PnP Address Select Register Default Value Mode */ + , 1, + KBCR, 1, /* KBC enabled after system reset (read-only) */ + , 3, + CLKS, 1, /* Clock select */ + AQ16, 1, /* 16bit Address Qualification */ + FDCT, 1, /* Tristate FDC (?) */ + , 2, + PRTT, 1, /* Tristate parallel port (?) */ + URAT, 1, /* Tristate UART A (?) */ + URBT, 1, /* Tristate UART B (?) */ + , 2, + URAI, 1, /* UART A Legacy IRQ Select Disable */ + URBI, 1, /* UART B Legacy IRQ Select Disable */ + PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ + FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ + , 1, + LCKC, 1, /* Lock Configuration Registers */ Offset (0x29), - IO3S, 8, /* GPIO3 pin selection register */ + IO3S, 8, /* GPIO3 pin selection register */ Offset (0x30), - ACTR, 1, /* Logical device activation */ - ACT1, 1, /* Logical part activation 1 (mostly unused) */ - ACT2, 1, /* Logical part activation 2 (mostly unused) */ - , 5, + ACTR, 1, /* Logical device activation */ + ACT1, 1, /* Logical part activation 1 (mostly unused) */ + ACT2, 1, /* Logical part activation 2 (mostly unused) */ + , 5, Offset (0x60), - IO1H, 8, /* First I/O port base - high byte */ - IO1L, 8, /* First I/O port base - low byte */ - IO2H, 8, /* Second I/O port base - high byte */ - IO2L, 8, /* Second I/O port base - low byte */ + IO1H, 8, /* First I/O port base - high byte */ + IO1L, 8, /* First I/O port base - low byte */ + IO2H, 8, /* Second I/O port base - high byte */ + IO2L, 8, /* Second I/O port base - low byte */ Offset (0x70), - IRQ0, 8, /* First IRQ */ + IRQ0, 8, /* First IRQ */ Offset (0x72), - IRQ1, 8, /* First IRQ */ + IRQ1, 8, /* First IRQ */ Offset (0x74), - DMA0, 8, /* DMA */ + DMA0, 8, /* DMA */ Offset (0xE0), /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ - CRE0, 8, - CRE1, 8, - CRE2, 8, - CRE3, 8, - CRE4, 8, + CRE0, 8, + CRE1, 8, + CRE2, 8, + CRE3, 8, + CRE4, 8, Offset (0xF0), /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ - OPT1, 8, - OPT2, 8, - OPT3, 8, - OPT4, 8, - OPT5, 8, - OPT6, 8, - OPT7, 8, - OPT8, 8, - OPT9, 8, - OPTA, 8 + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8, + OPT6, 8, + OPT7, 8, + OPT8, 8, + OPT9, 8, + OPTA, 8 } Method (_CRS) @@ -177,14 +177,14 @@ Device(SIO) { Else { Return (0) } } - /* PM: Switch to D0 by setting IPD low */ + /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (Zero, IPD) EXIT_CONFIG_MODE () } - /* PM: Switch to D3 by setting IPD high */ + /* PM: Switch to D3 by setting IPD high */ Method (_PS3) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) Store (One, IPD) @@ -315,23 +315,23 @@ Device(SIO) { Field (FIO1, ByteAcc, NoLock, Preserve) { Offset(0x02), - SELE, 2, - RSTL, 1, - IDMA, 1, - ACT1, 1, - ACT2, 1, - ACT3, 1, - ACT4, 1, + SELE, 2, + RSTL, 1, + IDMA, 1, + ACT1, 1, + ACT2, 1, + ACT3, 1, + ACT4, 1, Offset(0x04), - BSY1, 1, - BSY2, 1, - BSY3, 1, - BSY4, 1, - BUSY, 1, - NDMA, 1, - IODI, 1, - RDY, 1, - DATA, 8, + BSY1, 1, + BSY2, 1, + BSY3, 1, + BSY4, 1, + BUSY, 1, + NDMA, 1, + IODI, 1, + RDY, 1, + DATA, 8, } OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) Field (FIO2, ByteAcc, NoLock, Preserve) @@ -567,7 +567,7 @@ Device(SIO) { If (LEqual(IOAL, 4)) { Store(0x0, Local2) - } else { + } else { Store(0x1, Local2) } diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index 0a37ac9908..918d1e1398 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -67,9 +67,9 @@ IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) OPT1, 8 } -#define PNP_ENTER_MAGIC_1ST 0x87 -#define PNP_ENTER_MAGIC_2ND 0x87 -#define PNP_EXIT_MAGIC_1ST 0xaa +#define PNP_ENTER_MAGIC_1ST 0x87 +#define PNP_ENTER_MAGIC_2ND 0x87 +#define PNP_EXIT_MAGIC_1ST 0xaa #include /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ @@ -84,13 +84,13 @@ Method (_PSC) { #ifdef SUPERIO_SHOW_FDC Device (FDC0) { - Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID - Method (_STA, 0, NotSerialized) // _STA: Status + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status { PNP_GENERIC_STA(W83977TF_FDC) } - Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device { PNP_GENERIC_DIS(W83977TF_FDC) } @@ -300,7 +300,7 @@ Device (ECP) Return (BUF6) } - Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { StartDependentFn (0x01, 0x01) { @@ -326,7 +326,7 @@ Device (ECP) EndDependentFn () }) - Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { CreateByteField (Arg0, 0x02, IOLO) CreateByteField (Arg0, 0x03, IOHI) @@ -366,5 +366,5 @@ Device (ECP) */ #define SUPERIO_KBC_LDN W83977TF_KBC -#define SUPERIO_KBC_PS2M /* Mouse shares same LDN */ +#define SUPERIO_KBC_PS2M /* Mouse shares same LDN */ #include From 7774de53d49b612888603824f24ea5f258feeba1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 16:46:18 +0200 Subject: [PATCH 0714/1463] superio/nuvoton: Improve code formatting Change-Id: I8cdfa5c3e3508ea8ad969df6513401611a066fc5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39930 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/superio/nuvoton/nct5104d/nct5104d.h | 2 +- src/superio/nuvoton/npcd378/npcd378.h | 3 +-- src/superio/nuvoton/npcd378/superio.c | 6 ++---- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index b65e805ddf..679b21af57 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -26,7 +26,7 @@ #define NCT5104D_FDC 0x00 /* FDC - not pinned out */ #define NCT5104D_SP1 0x02 /* UARTA */ #define NCT5104D_SP2 0x03 /* UARTB */ -#define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */ +#define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */ #define NCT5104D_SP3 0x10 /* UARTC */ #define NCT5104D_SP4 0x11 /* UARTD */ #define NCT5104D_PORT80 0x14 /* PORT 80 */ diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h index f2fd87b27e..98d50e53a0 100644 --- a/src/superio/nuvoton/npcd378/npcd378.h +++ b/src/superio/nuvoton/npcd378/npcd378.h @@ -31,8 +31,7 @@ uint8_t npcd378_hwm_read(const uint16_t iobase, const uint16_t reg); * @param reg MSB is page, LSB sets the offset in selected page * @param val The value to write to HWM register */ -void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg, - const uint8_t val); +void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg, const uint8_t val); /* * Notify SuperIO a host-to-device transfer is ongoing. diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index a07afdc79c..95a4babbb7 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -26,8 +26,7 @@ uint8_t npcd378_hwm_read(const uint16_t iobase, const uint16_t reg) return reg8; } -void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg, - const uint8_t val) +void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg, const uint8_t val) { outb((reg >> 8) & 0xf, iobase + 0xff); outb(val, iobase + (reg & 0xff)); @@ -65,8 +64,7 @@ static void npcd378_init(struct device *dev) case NPCD378_HWM: res = find_resource(dev, PNP_IDX_IO0); if (!res || !res->base) { - printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n", - NPCD378_HWM); + printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n", NPCD378_HWM); break; } From 12eef084fda2d02a2ad364ba80dfe5f2cf407d85 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 16:45:35 +0200 Subject: [PATCH 0715/1463] superio/ite: Improve code formatting Change-Id: I014659aaddeb9fa2d5c3c3583e9379be4f9db69b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39929 Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/superio/ite/common/early_serial.c | 12 ++++++------ src/superio/ite/common/env_ctrl.c | 6 ++---- src/superio/ite/it8720f/acpi/superio.asl | 2 +- src/superio/ite/it8721f/acpi/superio.asl | 2 +- src/superio/ite/it8783ef/acpi/superio.asl | 2 +- src/superio/ite/it8786e/acpi/superio.asl | 5 ++--- 6 files changed, 13 insertions(+), 16 deletions(-) diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index fa881a07f6..c143c712e8 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -8,12 +8,12 @@ #include "ite.h" /* Global configuration registers. */ -#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */ -#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ +#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ +#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */ +#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ /* Helper procedure */ static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 23fd87dd9e..1082cf8163 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -81,8 +81,7 @@ static void enable_tmpin(const u16 base, const u8 tmpin, reg |= ITE_EC_ADC_TEMP_RESISTOR_MODE(tmpin); break; default: - printk(BIOS_WARNING, - "Unsupported thermal mode 0x%x on TMPIN%d\n", + printk(BIOS_WARNING, "Unsupported thermal mode 0x%x on TMPIN%d\n", conf->mode, tmpin); return; } @@ -185,8 +184,7 @@ static void enable_fan(const u16 base, const u8 fan, pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, reg); } - if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) - && conf->mode >= FAN_MODE_ON) { + if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { reg = pnp_read_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); pnp_write_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); diff --git a/src/superio/ite/it8720f/acpi/superio.asl b/src/superio/ite/it8720f/acpi/superio.asl index 4f3a8e0b9f..9ad2b87775 100644 --- a/src/superio/ite/it8720f/acpi/superio.asl +++ b/src/superio/ite/it8720f/acpi/superio.asl @@ -50,7 +50,7 @@ Device(SUPERIO_DEV) { Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_DATA_REG, 8 } IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { diff --git a/src/superio/ite/it8721f/acpi/superio.asl b/src/superio/ite/it8721f/acpi/superio.asl index 0679159332..ca876195dc 100644 --- a/src/superio/ite/it8721f/acpi/superio.asl +++ b/src/superio/ite/it8721f/acpi/superio.asl @@ -50,7 +50,7 @@ Device(SUPERIO_DEV) { Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_DATA_REG, 8 } IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { diff --git a/src/superio/ite/it8783ef/acpi/superio.asl b/src/superio/ite/it8783ef/acpi/superio.asl index 67dcf2692c..f3643ece6e 100644 --- a/src/superio/ite/it8783ef/acpi/superio.asl +++ b/src/superio/ite/it8783ef/acpi/superio.asl @@ -56,7 +56,7 @@ Device(SUPERIO_DEV) { Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_DATA_REG, 8 } IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl index ba210bd0dd..dc45b60fd2 100644 --- a/src/superio/ite/it8786e/acpi/superio.asl +++ b/src/superio/ite/it8786e/acpi/superio.asl @@ -55,7 +55,7 @@ Device (SUPERIO_DEV) { Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_DATA_REG, 8 } IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { @@ -83,8 +83,7 @@ Device (SUPERIO_DEV) { { /* Announce the used i/o ports to the OS */ Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, - 0x01, 0x02) + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) }) } From 45808399fc04e7c623af6ee1e7c7686fab09e790 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 16:43:34 +0200 Subject: [PATCH 0716/1463] superio/{acpi,common}: Improve code formatting Change-Id: I879ac7b558781d559a65c97fc8b914ecc4ad3f0d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39927 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/superio/acpi/pnp_generic.asl | 2 +- src/superio/acpi/pnp_uart.asl | 2 +- src/superio/common/generic.c | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index cb92a5d9c6..afec200ab2 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -13,7 +13,7 @@ * SUPERIO_PNP_LDN The logical device number on the Super I/O * chip for this device (required) * SUPERIO_PNP_DDN A string literal that identifies the dos device - * name (DDN) of this device (e.g. "COM1", optional) + * name (DDN) of this device (e.g. "COM1", optional) * SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down * the logical device (optional) * SUPERIO_PNP_PM_VAL The value for SUPERIO_PNP_PM_REG to power the logical diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index 859430ee9f..751f955c4e 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -12,7 +12,7 @@ * SUPERIO_UART_LDN The logical device number on the Super I/O * chip for this UART (required) * SUPERIO_UART_DDN A string literal that identifies the dos device - * name (DDN) of this uart (e.g. "COM1", optional) + * name (DDN) of this uart (e.g. "COM1", optional) * SUPERIO_UART_PM_REG Identifier of a 1-bit register to power down * the UART (optional) * SUPERIO_UART_PM_VAL The value for SUPERIO_UART_PM_REG to power the logical diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index de781999bf..809f8866ca 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -37,8 +37,7 @@ static void generic_ssdt(struct device *dev) const char *name = acpi_device_name(dev); if (!scope || !name) { - printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", - dev_path(dev)); + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); return; } From 3e666898cd99f4e15a39e360bb594d499e738b2d Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 23 Mar 2020 17:17:47 +0530 Subject: [PATCH 0717/1463] vendorcode/intel/fsp: Update FSP header for Tiger Lake Update FSPM header to include DisableDimmCh Upds for Tiger Lake platform version 2457. BUG=b:152000235 BRANCH=none TEST="Build and Boot on Ripto/Volteer" Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797 Tested-by: build bot (Jenkins) Reviewed-by: Srinidhi N Kaushik Reviewed-by: Wonkyu Kim --- .../intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 44 ++++++++++++++++--- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 9bc1a409c7..b27514c644 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -356,9 +356,41 @@ typedef struct { **/ UINT8 RMT; -/** Offset 0x0194 - Reserved +/** Offset 0x0194 - DisableDimmCh0 **/ - UINT8 Reserved8[10]; + UINT8 DisableDimmCh0; + +/** Offset 0x0195 - DisableDimmCh1 +**/ + UINT8 DisableDimmCh1; + +/** Offset 0x0196 - DisableDimmCh2 +**/ + UINT8 DisableDimmCh2; + +/** Offset 0x0197 - DisableDimmCh3 +**/ + UINT8 DisableDimmCh3; + +/** Offset 0x0198 - DisableDimmCh4 +**/ + UINT8 DisableDimmCh4; + +/** Offset 0x0199 - DisableDimmCh5 +**/ + UINT8 DisableDimmCh5; + +/** Offset 0x019A - DisableDimmCh6 +**/ + UINT8 DisableDimmCh6; + +/** Offset 0x019B - DisableDimmCh7 +**/ + UINT8 DisableDimmCh7; + +/** Offset 0x019C - Reserved +**/ + UINT8 Reserved8[2]; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -861,7 +893,7 @@ typedef struct { /** Offset 0x0775 - Reserved **/ - UINT8 Reserved38[355]; + UINT8 Reserved38[315]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -880,11 +912,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x08D8 +/** Offset 0x08B0 **/ - UINT8 UnusedUpdSpace24[6]; + UINT8 UnusedUpdSpace23[6]; -/** Offset 0x08DE +/** Offset 0x08B6 **/ UINT16 UpdTerminator; } FSPM_UPD; From 8dcadc9189d538dfcc0d8247bcd027afd5697244 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 16:44:54 +0200 Subject: [PATCH 0718/1463] superio/fintek: Improve code formatting Change-Id: I5ae2a2da1994fcc587540586d7404ebf18eb2ca0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39928 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/superio/fintek/f71869ad/f71869ad.h | 20 ++++++------- src/superio/fintek/f81216h/f81216h.h | 10 +++---- src/superio/fintek/f81803a/acpi/superio.asl | 4 +-- src/superio/fintek/f81803a/f81803a.h | 2 +- src/superio/fintek/f81803a/fan_control.c | 2 +- src/superio/fintek/f81866d/f81866d_hwm.c | 32 ++++++++++----------- src/superio/fintek/f81866d/f81866d_uart.c | 4 +-- 7 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index d038c3d9e5..e4e2f27f90 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -5,15 +5,15 @@ #define SUPERIO_FINTEK_F71869AD_H /* Logical Device Numbers (LDN). */ -#define F71869AD_FDC 0x00 /* Floppy */ -#define F71869AD_SP1 0x01 /* UART1 */ -#define F71869AD_SP2 0x02 /* UART2 */ -#define F71869AD_PP 0x03 /* Parallel port */ -#define F71869AD_HWM 0x04 /* Hardware monitor */ -#define F71869AD_KBC 0x05 /* PS/2 keyboard and mouse */ -#define F71869AD_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71869AD_WDT 0x07 /* WDT */ -#define F71869AD_CIR 0x08 /* CIR */ -#define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */ +#define F71869AD_FDC 0x00 /* Floppy */ +#define F71869AD_SP1 0x01 /* UART1 */ +#define F71869AD_SP2 0x02 /* UART2 */ +#define F71869AD_PP 0x03 /* Parallel port */ +#define F71869AD_HWM 0x04 /* Hardware monitor */ +#define F71869AD_KBC 0x05 /* PS/2 keyboard and mouse */ +#define F71869AD_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71869AD_WDT 0x07 /* WDT */ +#define F71869AD_CIR 0x08 /* CIR */ +#define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */ #endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h index 865cecbf6a..0c8463e55b 100644 --- a/src/superio/fintek/f81216h/f81216h.h +++ b/src/superio/fintek/f81216h/f81216h.h @@ -7,11 +7,11 @@ #include /* Logical Device Numbers (LDN). */ -#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */ -#define F81216H_SP2 0x01 /* UART2 */ -#define F81216H_SP3 0x02 /* UART3 */ -#define F81216H_SP4 0x03 /* UART4 */ -#define F81216H_WDT 0x08 /* WDT */ +#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */ +#define F81216H_SP2 0x01 /* UART2 */ +#define F81216H_SP3 0x02 /* UART3 */ +#define F81216H_SP4 0x03 /* UART4 */ +#define F81216H_WDT 0x08 /* WDT */ /** * The PNP config entry key is parameterised diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl index 0887d6a9db..30654583a2 100644 --- a/src/superio/fintek/f81803a/acpi/superio.asl +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -237,13 +237,13 @@ Device(SUPERIO_DEV) { { Offset(0x00), /*Control Reg 5 */ , 7, - PSIN, 1 /* PSIN_FLAG */ + PSIN, 1 /* PSIN_FLAG */ } /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ Method(CPSI, 0, Serialized) { - /* DBG0("SIO CPSI")*/ + /* DBG0("SIO CPSI") */ ENTER_CONFIG_MODE(SUPERIO_PME_LDN) Store(1, PSIN) EXIT_CONFIG_MODE() diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h index fdf9ecf504..9cd720f000 100644 --- a/src/superio/fintek/f81803a/f81803a.h +++ b/src/superio/fintek/f81803a/f81803a.h @@ -19,7 +19,7 @@ #define F81803A_WDT 0x07 /* Watch Dog Timer */ #define F81803A_PME 0x0a /* Power Management Events (PME) */ -/* Global Control Registers */ +/* Global Control Registers */ #define CLOCK_SELECT_REG 0x26 #define FUNC_PROG_SELECT (1<<3) #define PORT_SELECT_REG 0x27 diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c index 3b01a64e4f..2143f2e8d0 100644 --- a/src/superio/fintek/f81803a/fan_control.c +++ b/src/superio/fintek/f81803a/fan_control.c @@ -128,7 +128,7 @@ static int check_value_seq(u8 *values, u8 count) u8 current_value, i; for (i = 0; i < count; i++) { current_value = values[i]; - if (current_value > CPU_DAMAGE_TEMP) + if (current_value > CPU_DAMAGE_TEMP) return STATUS_INVALID_VALUE; if (current_value >= last_value) return STATUS_INVALID_ORDER; diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index e6333f5818..3d3a301f8c 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -14,29 +14,29 @@ /* Register addresses */ // Choose between AMD and Intel -#define HWM_AMD_TSI_ADDR 0x08 -#define HWM_AMD_TSI_CONTROL_REG 0x0A +#define HWM_AMD_TSI_ADDR 0x08 +#define HWM_AMD_TSI_CONTROL_REG 0x0A // Set temp sensors type -#define TEMP_SENS_TYPE_REG 0x6B +#define TEMP_SENS_TYPE_REG 0x6B // FAN prog sel -#define HWM_FAN3_CONTROL 0x9A -#define HWM_FAN_SEL 0x94 -#define HWM_FAN_MODE 0x96 -#define HWM_FAN2_TEMP_MAP_SEL 0xBF +#define HWM_FAN3_CONTROL 0x9A +#define HWM_FAN_SEL 0x94 +#define HWM_FAN_MODE 0x96 +#define HWM_FAN2_TEMP_MAP_SEL 0xBF // Fan 2 - 4 Boundaries -#define HWM_FAN2_BOUND1 0xB6 -#define HWM_FAN2_BOUND2 0xB7 -#define HWM_FAN2_BOUND3 0xB8 -#define HWM_FAN2_BOUND4 0xB9 +#define HWM_FAN2_BOUND1 0xB6 +#define HWM_FAN2_BOUND2 0xB7 +#define HWM_FAN2_BOUND3 0xB8 +#define HWM_FAN2_BOUND4 0xB9 // Fan 2 - 5 Segment speeds -#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA -#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB -#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC -#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD -#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE +#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA +#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB +#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC +#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD +#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE void f81866d_hwm_init(struct device *dev) diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c index c6c18890b0..9590dc4e9c 100644 --- a/src/superio/fintek/f81866d/f81866d_uart.c +++ b/src/superio/fintek/f81866d/f81866d_uart.c @@ -36,13 +36,13 @@ void f81866d_uart_init(struct device *dev) pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE); // Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO - if (dev->path.pnp.device == F81866D_SP3) { + if (dev->path.pnp.device == F81866D_SP3) { tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30); } // Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO - if (dev->path.pnp.device == F81866D_SP4) { + if (dev->path.pnp.device == F81866D_SP4) { tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0); } From 00eb7d7bda2c698388edd74ef5bb95441f1e4bcd Mon Sep 17 00:00:00 2001 From: Philipp Deppenwiese Date: Sat, 28 Mar 2020 14:19:44 +0100 Subject: [PATCH 0719/1463] Remove myself from MAINTAINERS file I will pass my responsibilities to Christian Walter. I have hardly any time left for the coreboot project. Change-Id: Ia60e71c5cbd361486dbc924ad954db203e285a5a Signed-off-by: Philipp Deppenwiese Reviewed-on: https://review.coreboot.org/c/coreboot/+/39897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- MAINTAINERS | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3a31847c9b..7ea4aa357e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -223,7 +223,7 @@ F: src/mainboard/google/slippy/ F: src/mainboard/google/stout/ OPENCELLULAR MAINBOARDS -M: Philipp Deppenwiese +M: Christian Walter M: Patrick Rudolph S: Supported F: src/mainboard/opencellular/elgon/ @@ -455,7 +455,7 @@ M: Stefan Reinauer F: util/inteltool/ INTELMETOOL -M: Philipp Deppenwiese +M: Christian Walter F: util/intelmetool/ ME_CLEANER @@ -535,7 +535,7 @@ M: Martin Roth F: payloads/external LINUXBOOT PAYLOAD INTEGRATION -M: Philipp Deppenwiese +M: Christian Walter M: Marcello Sylvester Bauer S: Supported F: payloads/external/LinuxBoot @@ -545,10 +545,9 @@ M: Aaron Durbin F: src/security/vboot/ TPM SUPPORT -M: Philipp Deppenwiese +M: Christian Walter S: Supported F: src/drivers/*/tpm/ -F: src/security/vboot/vboot_crtm.* F: src/security/tpm DOCKER @@ -608,11 +607,11 @@ MISSING: SPI # Backups: # Website -# Owners: Martin, Philipp +# Owners: Martin # Backups: Patrick, Stefan # Documentation Website -# Owners: Patrick, Philipp +# Owners: Patrick # Backups: CODE OF CONDUCT From 5117c27cc18e6a22e71204d911e404f9e27744e8 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Mon, 30 Mar 2020 14:41:52 -0700 Subject: [PATCH 0720/1463] cros_ec: add chrome EC headers to include path This adds the path to chrome EC headers to the depthcharge build. Depthcharge currently includes a manually maintained copy of the EC headers which are perpetually out of sync with the real interface definitions. By adding the include path, we can build depthcharge with the actual EC interface definitions and eliminate the manual maintenance of copies of EC headers. Once the include path is in place, we can remove the copies of the EC headers from depthcharge. BUG=b:152373049 Change-Id: I1ce0ad9dc99ea52f177d4fb034fd23efd95a7864 Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/39947 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Duncan Laurie --- payloads/external/depthcharge/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index c1993e4538..c4dd1bf14b 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -10,6 +10,7 @@ libpayload_dir=$(abspath $(CURDIR)/../../libpayload) libpayload_install_dir=$(output_dir)/lp_$(BOARD) VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot) +EC_HEADERS ?= $(abspath $(CURDIR)/../../../3rdparty/chromeec/include) TAG-$(DEPTHCHARGE_MASTER)=origin/master TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID) @@ -79,13 +80,15 @@ config: $(project_dir)/.version_$(TAG-y) $(libpayload_install_dir) cd $(project_dir) && \ $(MAKE) BOARD=$(BOARD) \ LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ - VB_SOURCE=$(VBOOT_SOURCE) defconfig + VB_SOURCE=$(VBOOT_SOURCE) \ + EC_HEADERS=$(EC_HEADERS) defconfig build: config echo " MAKE $(project_name) $(TAG-y)" $(MAKE) -C $(project_dir) depthcharge BOARD=$(BOARD) \ LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ VB_SOURCE=$(VBOOT_SOURCE) \ + EC_HEADERS=$(EC_HEADERS) \ PATH="$(abspath ../../../build/util/cbfstool):$$PATH" clean: From 51ce41c0e661fd9cb9207463bcbd920e55b44a62 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Sun, 29 Mar 2020 21:40:04 +0800 Subject: [PATCH 0721/1463] drivers/pc80/rtc: Always load cmos.default if measured boot is enabled cmos.default used to be loaded only when cmos is needed to be reset, but conditional loading of CBFS files may change the calculated PCRs if measurement is hooked on each loading. In order to resolve this, loadings should be made less conditional, (if a file might be used, it should be loaded and measured) but the use of loaded data remains conditional. Change-Id: If6ea0d1cbaa7d96f7dea7e77b7548ca2b30efe9e Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/39906 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/pc80/rtc/option.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index bb697dfba1..dc78dbbf30 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -239,25 +239,25 @@ int cmos_lb_cks_valid(void) return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); } -static void cmos_load_defaults(void) -{ - size_t length = 128; - size_t i; - - const unsigned char *cmos_default = - cbfs_boot_map_with_leak("cmos.default", - CBFS_COMPONENT_CMOS_DEFAULT, &length); - if (!cmos_default) - return; - - u8 control_state = cmos_disable_rtc(); - for (i = 14; i < MIN(128, length); i++) - cmos_write_inner(cmos_default[i], i); - cmos_restore_rtc(control_state); -} void sanitize_cmos(void) { - if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE)) - cmos_load_defaults(); + const unsigned char *cmos_default; + const bool cmos_need_reset = + CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid(); + size_t length = 128; + size_t i; + + if (CONFIG(TPM_MEASURED_BOOT) || cmos_need_reset) { + cmos_default = cbfs_boot_map_with_leak("cmos.default", + CBFS_COMPONENT_CMOS_DEFAULT, &length); + + if (!cmos_default || !cmos_need_reset) + return; + + u8 control_state = cmos_disable_rtc(); + for (i = 14; i < MIN(128, length); i++) + cmos_write_inner(cmos_default[i], i); + cmos_restore_rtc(control_state); + } } From a23e0c9d74b7f06738ebf28b068e1bd63f246982 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 25 Mar 2020 15:31:12 +0530 Subject: [PATCH 0722/1463] soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/dsdt.asl | 4 ++-- src/mainboard/google/dedede/romstage.c | 2 +- .../dedede/variants/baseboard/devicetree.cb | 2 +- .../google/dedede/variants/baseboard/memory.c | 2 +- .../dedede/variants/waddledee/overridetree.cb | 2 +- .../dedede/variants/waddledoo/overridetree.cb | 2 +- src/mainboard/intel/jasperlake_rvp/dsdt.asl | 4 ++-- .../intel/jasperlake_rvp/romstage_fsp_params.c | 2 +- .../baseboard/include/baseboard/variants.h | 2 +- .../jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- .../jasperlake_rvp/variants/jslrvp/memory.c | 2 +- src/soc/intel/jasperlake/Kconfig | 6 +++--- src/soc/intel/jasperlake/Makefile.inc | 2 +- src/soc/intel/jasperlake/romstage/fsp_params.c | 2 +- src/soc/intel/tigerlake/Kconfig | 16 ++-------------- src/soc/intel/tigerlake/Makefile.inc | 2 +- 16 files changed, 21 insertions(+), 33 deletions(-) diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 53423b8cb9..98ef6e49cc 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -18,7 +18,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -30,7 +30,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 9c220d4538..f95e7aacc3 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include void mainboard_memory_init_params(FSPM_UPD *memupd) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 865d4ea73c..f030b20cec 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index ff8a4ec661..08c3bde29f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include static const struct mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 23db34e66c..388051afa0 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 884199c4c5..cb21c63b0f 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c996717b0e..ed59af6a96 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -37,7 +37,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 8858e44616..f185628df1 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -14,7 +14,7 @@ */ #include #include -#include +#include #include #include "board_id.h" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index 27c645bbde..2fe7631281 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -17,7 +17,7 @@ #define __BASEBOARD_VARIANTS_H__ #include -#include +#include #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 386936eef8..41921dd46e 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 1915a1e1ff..4de66b3929 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = { diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 01d7294743..844a954996 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -1,9 +1,9 @@ -config SOC_INTEL_JASPERLAKE_COPY +config SOC_INTEL_JASPERLAKE bool help Intel Jasperlake support -if SOC_INTEL_JASPERLAKE_COPY +if SOC_INTEL_JASPERLAKE config CPU_SPECIFIC_OPTIONS def_bool y @@ -192,7 +192,7 @@ config FSP_FD_PATH depends on FSP_USE_REPO default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" -config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT +config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT int "Debug Consent for JSL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 29db4f3d00..4a65adc111 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y) +ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index ca7ff26a0e..d263834576 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -89,7 +89,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_DEBUG_CONSENT; /* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 63bd881b71..e71586d64b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -1,22 +1,9 @@ -config SOC_INTEL_TIGERLAKE_BASE - bool - config SOC_INTEL_TIGERLAKE bool - select SOC_INTEL_TIGERLAKE_BASE - #TODO - Enable INTEL_CAR_NEM_ENHANCED - select INTEL_CAR_NEM help Intel Tigerlake support -config SOC_INTEL_JASPERLAKE - bool - select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM - help - Intel Jasperlake support - -if SOC_INTEL_TIGERLAKE_BASE +if SOC_INTEL_TIGERLAKE config CPU_SPECIFIC_OPTIONS def_bool y @@ -36,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index e7169cff42..12d59b1f93 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode From 555c9b6268febf001e887fbb9e3c3f0901a371ac Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 23 Mar 2020 10:13:10 +0530 Subject: [PATCH 0723/1463] soc/intel/tigerlake: Remove Jasper Lake SoC references This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/romstage.c | 2 +- .../baseboard/include/baseboard/variants.h | 2 +- .../intel/tglrvp/romstage_fsp_params.c | 2 +- .../baseboard/include/baseboard/variants.h | 2 +- src/soc/intel/tigerlake/Kconfig | 32 +- src/soc/intel/tigerlake/Makefile.inc | 20 +- src/soc/intel/tigerlake/acpi/pci_irqs.asl | 157 ++++++- src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl | 141 ------- src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl | 167 -------- src/soc/intel/tigerlake/acpi/xhci.asl | 53 ++- src/soc/intel/tigerlake/acpi/xhci_jsl.asl | 62 --- src/soc/intel/tigerlake/acpi/xhci_tgl.asl | 62 --- src/soc/intel/tigerlake/bootblock/pch.c | 23 +- .../tigerlake/bootblock/report_platform.c | 5 - src/soc/intel/tigerlake/espi.c | 18 - .../{fsp_params_tgl.c => fsp_params.c} | 0 src/soc/intel/tigerlake/fsp_params_jsl.c | 191 --------- .../intel/tigerlake/{gpio_tgl.c => gpio.c} | 0 src/soc/intel/tigerlake/gpio_jsl.c | 210 ---------- src/soc/intel/tigerlake/include/soc/espi.h | 11 - src/soc/intel/tigerlake/include/soc/gpio.h | 21 +- .../intel/tigerlake/include/soc/gpio_defs.h | 299 ++++++++++++- .../tigerlake/include/soc/gpio_defs_jsl.h | 272 ------------ .../tigerlake/include/soc/gpio_defs_tgl.h | 314 -------------- .../tigerlake/include/soc/gpio_soc_defs.h | 381 ++++++++++++++++- .../tigerlake/include/soc/gpio_soc_defs_jsl.h | 358 ---------------- .../tigerlake/include/soc/gpio_soc_defs_tgl.h | 394 ------------------ src/soc/intel/tigerlake/include/soc/iomap.h | 12 - src/soc/intel/tigerlake/include/soc/irq.h | 69 ++- src/soc/intel/tigerlake/include/soc/irq_jsl.h | 86 ---- src/soc/intel/tigerlake/include/soc/irq_tgl.h | 83 ---- .../include/soc/{meminit_tgl.h => meminit.h} | 6 +- .../intel/tigerlake/include/soc/meminit_jsl.h | 124 ------ src/soc/intel/tigerlake/include/soc/pch.h | 4 - .../intel/tigerlake/include/soc/pci_devs.h | 11 - src/soc/intel/tigerlake/include/soc/pmc.h | 41 +- .../tigerlake/{meminit_tgl.c => meminit.c} | 2 +- src/soc/intel/tigerlake/meminit_jsl.c | 126 ------ src/soc/intel/tigerlake/romstage/Makefile.inc | 3 +- .../{fsp_params_tgl.c => fsp_params.c} | 0 .../intel/tigerlake/romstage/fsp_params_jsl.c | 145 ------- 41 files changed, 981 insertions(+), 2930 deletions(-) delete mode 100644 src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl delete mode 100644 src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl delete mode 100644 src/soc/intel/tigerlake/acpi/xhci_jsl.asl delete mode 100644 src/soc/intel/tigerlake/acpi/xhci_tgl.asl rename src/soc/intel/tigerlake/{fsp_params_tgl.c => fsp_params.c} (100%) delete mode 100644 src/soc/intel/tigerlake/fsp_params_jsl.c rename src/soc/intel/tigerlake/{gpio_tgl.c => gpio.c} (100%) delete mode 100644 src/soc/intel/tigerlake/gpio_jsl.c delete mode 100644 src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h delete mode 100644 src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h delete mode 100644 src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h delete mode 100644 src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h delete mode 100644 src/soc/intel/tigerlake/include/soc/irq_jsl.h delete mode 100644 src/soc/intel/tigerlake/include/soc/irq_tgl.h rename src/soc/intel/tigerlake/include/soc/{meminit_tgl.h => meminit.h} (93%) delete mode 100644 src/soc/intel/tigerlake/include/soc/meminit_jsl.h rename src/soc/intel/tigerlake/{meminit_tgl.c => meminit.c} (99%) delete mode 100644 src/soc/intel/tigerlake/meminit_jsl.c rename src/soc/intel/tigerlake/romstage/{fsp_params_tgl.c => fsp_params.c} (100%) delete mode 100644 src/soc/intel/tigerlake/romstage/fsp_params_jsl.c diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 5d588b2d1d..46c5fecd1e 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index f368d886d2..d5bc63a08c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -9,7 +9,7 @@ #define __BASEBOARD_VARIANTS_H__ #include -#include +#include #include #include diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index d636bc89c4..0af394494f 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include "board_id.h" diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index 29f9a7176c..b7b69f29fd 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -16,7 +16,7 @@ #define __BASEBOARD_VARIANTS_H__ #include -#include +#include #include #include diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e71586d64b..77d22ca946 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -72,13 +72,12 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x40400 if SOC_INTEL_TIGERLAKE - default 0x30400 if SOC_INTEL_JASPERLAKE + default 0x40400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage - stack requirement (~1KiB). + sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement + (~1KiB). config FSP_TEMP_RAM_SIZE hex @@ -90,8 +89,7 @@ config FSP_TEMP_RAM_SIZE config IFD_CHIPSET string - default "jsl" if SOC_INTEL_JASPERLAKE - default "tgl" if SOC_INTEL_TIGERLAKE + default "tgl" config IED_REGION_SIZE hex @@ -103,13 +101,11 @@ config HEAP_SIZE config MAX_ROOT_PORTS int - default 8 if SOC_INTEL_JASPERLAKE - default 12 if SOC_INTEL_TIGERLAKE + default 12 config MAX_PCIE_CLOCKS int - default 7 if SOC_INTEL_TIGERLAKE - default 6 if SOC_INTEL_JASPERLAKE + default 7 config SMM_TSEG_SIZE hex @@ -143,8 +139,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int - default 3 if SOC_INTEL_JASPERLAKE - default 4 if SOC_INTEL_TIGERLAKE + default 4 config SOC_INTEL_I2C_DEV_MAX int @@ -162,16 +157,13 @@ config CONSOLE_UART_BASE_ADDRESS # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clcok * M) /(N *16) # TGL UART source clock: 120MHz -# JSL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex - default 0x30 if SOC_INTEL_JASPERLAKE - default 0x25a if SOC_INTEL_TIGERLAKE + default 0x25a config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex - default 0xc35 if SOC_INTEL_JASPERLAKE - default 0x7fff if SOC_INTEL_TIGERLAKE + default 0x7fff config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -193,14 +185,12 @@ config CBFS_SIZE config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE - default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE + default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE - default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE + default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT int "Debug Consent for TGL" diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 12d59b1f93..fd2464d505 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -20,15 +20,12 @@ bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +bootblock-y += gpio.c bootblock-y += p2sb.c romstage-y += espi.c -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += meminit_jsl.c -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +romstage-y += meminit.c +romstage-y += gpio.c romstage-y += reset.c ramstage-y += acpi.c @@ -37,10 +34,8 @@ ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c -ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c -ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c -ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c @@ -50,15 +45,14 @@ ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c -smm-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -smm-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +smm-y += gpio.c smm-y += p2sb.c smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c -verstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c +verstage-y += gpio.c CPPFLAGS_common += -I$(src)/soc/intel/tigerlake CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 7048c150f6..7f632ba32e 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -13,8 +13,155 @@ * GNU General Public License for more details. */ -#if CONFIG(SOC_INTEL_TIGERLAKE) - #include "pci_irqs_tgl.asl" -#else - #include "pci_irqs_jsl.asl" -#endif +#include + +Name (PICP, Package () { + /* D31:HSA, SMBUS, TraceHUB */ + Package(){0x001FFFFF, 3, 0, HDA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* D29: RP9 ~ RP12 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* D28: RP1 ~ RP8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* D23: SATA */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ + Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, + Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, ISH_IRQ }, + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, + Package(){0x0010FFFF, 6, 0, THC0_IRQ }, + Package(){0x0010FFFF, 7, 0, THC1_IRQ }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, + Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, PEG_IRQ }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, +}) + +Name (PICN, Package () { + /* D31:HSA, SMBUS, TraceHUB*/ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package () { 0x001EFFFF, 0, 0, 11 }, + Package () { 0x001EFFFF, 1, 0, 10 }, + Package () { 0x001EFFFF, 2, 0, 11 }, + Package () { 0x001EFFFF, 3, 0, 11 }, + /* D29: RP9 ~ RP12 */ + Package () { 0x001DFFFF, 0, 0, 11 }, + Package () { 0x001DFFFF, 1, 0, 10 }, + Package () { 0x001DFFFF, 2, 0, 11 }, + Package () { 0x001DFFFF, 3, 0, 11 }, + /* D28: RP1 ~ RP8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, 11 }, + Package(){0x0019FFFF, 1, 0, 10 }, + Package(){0x0019FFFF, 2, 0, 11 }, + /* D23: SATA */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, 11 }, + Package(){0x0016FFFF, 1, 0, 10 }, + Package(){0x0016FFFF, 4, 0, 11 }, + Package(){0x0016FFFF, 5, 0, 11 }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, 11 }, + Package(){0x0015FFFF, 1, 0, 10 }, + Package(){0x0015FFFF, 2, 0, 11 }, + Package(){0x0015FFFF, 3, 0, 11 }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, 11 }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, 11 }, + Package(){0x0012FFFF, 6, 0, 11 },, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, 11 }, + Package(){0x0010FFFF, 6, 0, 11 }, + Package(){0x0010FFFF, 7, 0, 10 }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, 11 }, + Package(){0x000DFFFF, 1, 0, 10 }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, 11 }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, 11 }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, 11 }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, 11 }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl deleted file mode 100644 index 086282e733..0000000000 --- a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -Name (PICP, Package () { - /* cAVS, SMBus, GbE, Northpeak */ - Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ }, - /* SerialIo */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, - /* SerialIo */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* SATA controller */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, IDER_IRQ }, - Package(){0x0016FFFF, 3, 0, KT_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* SerialIo */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, - Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, - Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - Package(){0x0014FFFF, 5, 0, SD_IRQ }, - /* SerialIo */ - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, -}) - -Name (PICN, Package () { - /* D31: cAVS, SMBus, GbE, Northpeak */ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 10 }, - Package () { 0x001FFFFF, 6, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: SerialIo */ - Package () {0x001EFFFF, 0, 0, 11 }, - Package () {0x001EFFFF, 1, 0, 10 }, - Package () {0x001EFFFF, 2, 0, 11 }, - Package () {0x001EFFFF, 3, 0, 11 }, - /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D26: eMMC */ - Package(){0x001AFFFF, 0, 0, 11 }, - /* D25: SerialIo */ - Package () {0x0019FFFF, 0, 0, 11 }, - Package () {0x0019FFFF, 1, 0, 10 }, - Package () {0x0019FFFF, 2, 0, 11 }, - /* D23: SATA controller */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 11 }, - Package () { 0x0016FFFF, 1, 0, 10 }, - Package () { 0x0016FFFF, 2, 0, 11 }, - Package () { 0x0016FFFF, 3, 0, 11 }, - Package () { 0x0016FFFF, 4, 0, 11 }, - Package () { 0x0016FFFF, 5, 0, 11 }, - /* D21: SerialIo */ - Package () {0x0015FFFF, 0, 0, 11 }, - Package () {0x0015FFFF, 1, 0, 10 }, - Package () {0x0015FFFF, 2, 0, 11 }, - Package () {0x0015FFFF, 3, 0, 11 }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ - Package () { 0x0014FFFF, 0, 0, 11 }, - Package () { 0x0014FFFF, 1, 0, 10 }, - Package () { 0x0014FFFF, 2, 0, 11 }, - Package () { 0x0014FFFF, 3, 0, 11 }, - Package () { 0x0014FFFF, 5, 0, 11 }, - /* D18: SerialIo */ - Package () {0x0012FFFF, 6, 0, 11 }, - /* SA IGFX Device */ - Package () {0x0002FFFF, 0, 0, 11 }, - /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, 11 }, - /* SA GNA Device */ - Package () { 0x0008FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl deleted file mode 100644 index 7f632ba32e..0000000000 --- a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ - Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, - Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, ISH_IRQ }, - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, - Package(){0x0010FFFF, 6, 0, THC0_IRQ }, - Package(){0x0010FFFF, 7, 0, THC1_IRQ }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, - Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, PEG_IRQ }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, -}) - -Name (PICN, Package () { - /* D31:HSA, SMBUS, TraceHUB*/ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package () { 0x001EFFFF, 0, 0, 11 }, - Package () { 0x001EFFFF, 1, 0, 10 }, - Package () { 0x001EFFFF, 2, 0, 11 }, - Package () { 0x001EFFFF, 3, 0, 11 }, - /* D29: RP9 ~ RP12 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: RP1 ~ RP8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, 11 }, - Package(){0x0019FFFF, 1, 0, 10 }, - Package(){0x0019FFFF, 2, 0, 11 }, - /* D23: SATA */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, 11 }, - Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 4, 0, 11 }, - Package(){0x0016FFFF, 5, 0, 11 }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, 11 }, - Package(){0x0015FFFF, 1, 0, 10 }, - Package(){0x0015FFFF, 2, 0, 11 }, - Package(){0x0015FFFF, 3, 0, 11 }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, 11 }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 6, 0, 11 },, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, 11 }, - Package(){0x0010FFFF, 6, 0, 11 }, - Package(){0x0010FFFF, 7, 0, 10 }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, 11 }, - Package(){0x000DFFFF, 1, 0, 10 }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, 11 }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, 11 }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, 11 }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl index f147a2a83f..b97f52052b 100644 --- a/src/soc/intel/tigerlake/acpi/xhci.asl +++ b/src/soc/intel/tigerlake/acpi/xhci.asl @@ -12,8 +12,51 @@ * GNU General Public License for more details. */ -#if CONFIG(SOC_INTEL_TIGERLAKE) - #include "xhci_tgl.asl" -#else - #include "xhci_jsl.asl" -#endif +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Tigerlake-LP PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + } +} diff --git a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl deleted file mode 100644 index 41be89ace1..0000000000 --- a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* XHCI Controller 0:14.0 */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - - Name (_PRW, Package () { GPE0_PME_B0, 3 }) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Method (_PS0, 0, Serialized) - { - - } - - Method (_PS3, 0, Serialized) - { - - } - - /* Root Hub for Jasperlake PCH */ - Device (RHUB) - { - Name (_ADR, Zero) - - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 9) } - Device (SS02) { Name (_ADR, 10) } - Device (SS03) { Name (_ADR, 11) } - Device (SS04) { Name (_ADR, 12) } - Device (SS05) { Name (_ADR, 13) } - Device (SS06) { Name (_ADR, 14) } - } -} diff --git a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl deleted file mode 100644 index b97f52052b..0000000000 --- a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* XHCI Controller 0:14.0 */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - - Name (_PRW, Package () { GPE0_PME_B0, 3 }) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Method (_PS0, 0, Serialized) - { - - } - - Method (_PS3, 0, Serialized) - { - - } - - /* Root Hub for Tigerlake-LP PCH */ - Device (RHUB) - { - Name (_ADR, Zero) - - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - Device (HS09) { Name (_ADR, 9) } - Device (HS10) { Name (_ADR, 10) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 13) } - Device (SS02) { Name (_ADR, 14) } - Device (SS03) { Name (_ADR, 15) } - Device (SS04) { Name (_ADR, 16) } - } -} diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index b0646018c6..94b70721df 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -39,8 +39,7 @@ #include #include -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100 -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -60,20 +59,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -static uint32_t get_pmc_reg_base(void) -{ - uint8_t pch_series; - - pch_series = get_pch_series(); - - if (pch_series == PCH_TGP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP; - else if (pch_series == PCH_JSP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP; - else - return 0; -} - static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -116,11 +101,7 @@ void bootblock_pch_early_init(void) static void soc_config_acpibase(void) { uint32_t pmc_reg_value; - uint32_t pmc_base_reg; - - pmc_base_reg = get_pmc_reg_base(); - if (!pmc_base_reg) - die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n"); + uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index d7b2e0db32..59091c112f 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -37,7 +37,6 @@ static struct { const char *name; } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, - { CPUID_JASPERLAKE_A0, "Jasperlake A0" }, }; static struct { @@ -48,7 +47,6 @@ static struct { { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, - { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; @@ -89,7 +87,6 @@ static struct { { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, @@ -105,8 +102,6 @@ static struct { { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, - { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, - { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index da36ea6304..0d8f3af956 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -70,24 +70,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); } -uint8_t get_pch_series(void) -{ - uint16_t lpc_did_hi_byte; - - /* - * Fetch upper 8 bits on ESPI device ID to determine PCH type - * Adding 1 to the offset to fetch upper 8 bits - */ - lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); - - if (lpc_did_hi_byte == 0xA0) - return PCH_TGP; - else if (lpc_did_hi_byte == 0x4d) - return PCH_JSP; - else - return PCH_UNKNOWN_SERIES; -} - #if ENV_RAMSTAGE static void soc_mirror_dmi_pcr_io_dec(void) { diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params.c similarity index 100% rename from src/soc/intel/tigerlake/fsp_params_tgl.c rename to src/soc/intel/tigerlake/fsp_params.c diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c deleted file mode 100644 index 932bd06ff7..0000000000 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - -static void parse_devicetree(FSP_S_CONFIG *params) -{ - const struct soc_intel_tigerlake_config *config = config_of_soc(); - - /* LPSS controllers configuration */ - - /* I2C */ - _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= - ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); - memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, - sizeof(config->SerialIoI2cMode)); - - /* GSPI */ - _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >= - ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!"); - memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, - sizeof(config->SerialIoGSpiMode)); - - _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >= - ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!"); - memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode, - sizeof(config->SerialIoGSpiCsMode)); - - _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >= - ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!"); - memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState, - sizeof(config->SerialIoGSpiCsState)); - - /* UART */ - _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >= - ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!"); - memcpy(params->SerialIoUartMode, config->SerialIoUartMode, - sizeof(config->SerialIoUartMode)); -} - -/* UPD parameters to be initialized before SiliconInit */ -void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) -{ - unsigned int i; - struct device *dev; - FSP_S_CONFIG *params = &supd->FspsConfig; - struct soc_intel_tigerlake_config *config = config_of_soc(); - - /* Parse device tree and fill in FSP UPDs */ - parse_devicetree(params); - - /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - - /* Check if IGD is present and fill Graphics init param accordingly */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; - - /* Use coreboot MP PPI services if Kconfig is enabled */ - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - params->SkipMpInit = 0; - } else { - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - } - - /* Unlock upper 8 bytes of RTC RAM */ - params->RtcMemoryLock = 0; - - /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = 1; - - /* disable Legacy PME */ - memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); - - /* USB configuration */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - - params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; - params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; - params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; - params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; - params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; - } - - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { - - params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; - if (config->usb3_ports[i].tx_de_emp) { - params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; - } - if (config->usb3_ports[i].tx_downscale_amp) { - params->Usb3HsioTxDownscaleAmpEnable[i] = 1; - params->Usb3HsioTxDownscaleAmp[i] = - config->usb3_ports[i].tx_downscale_amp; - } - } - - /* SDCard related configuration */ - dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); - if (!dev) - params->ScsSdCardEnabled = 0; - else - params->ScsSdCardEnabled = dev->enabled; - - params->Device4Enable = config->Device4Enable; - - /* eMMC configuration */ - dev = pcidev_path_on_root(PCH_DEVFN_EMMC); - if (!dev) { - params->ScsEmmcEnabled = 0; - } else { - params->ScsEmmcEnabled = dev->enabled; - params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - } - - /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (dev) { - if (!xdci_can_enable()) - dev->enabled = 0; - - params->XdciEnable = dev->enabled; - } else { - params->XdciEnable = 0; - } - - /* Provide correct UART number for FSP debug logs */ - params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; - - /* Override/Fill FSP Silicon Param for mainboard */ - mainboard_silicon_init_params(params); -} - -/* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/tigerlake/gpio_tgl.c b/src/soc/intel/tigerlake/gpio.c similarity index 100% rename from src/soc/intel/tigerlake/gpio_tgl.c rename to src/soc/intel/tigerlake/gpio.c diff --git a/src/soc/intel/tigerlake/gpio_jsl.c b/src/soc/intel/tigerlake/gpio_jsl.c deleted file mode 100644 index afb9f7b3bc..0000000000 --- a/src/soc/intel/tigerlake/gpio_jsl.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static const struct reset_mapping rst_map[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, -}; - -static const struct reset_mapping rst_map_com0[] = { - { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, - { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, -}; - -/* - * The GPIO driver for Jasperlake on Windows/Linux expects 32 GPIOs per pad - * group, regardless of whether or not there is a physical pad for each - * exposed GPIO number. - * - * This results in the OS having a sparse GPIO map, and devices that need - * to export an ACPI GPIO must use the OS expected number. - * - * Not all pins are usable as GPIO and those groups do not have a pad base. - * - * This layout matches the Linux kernel pinctrl map for JSP at: - * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c - */ -static const struct pad_group jsl_community0_groups[] = { - - INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */ - INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8), - INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ - INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10), - INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ - INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ - INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ -}; - -static const struct pad_group jsl_community1_groups[] = { - INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ - INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */ - INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), - INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ - INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ -}; - -/* This community is not visible to the OS */ -static const struct pad_group jsl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */ - INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17), -}; - - -static const struct pad_group jsl_community4_groups[] = { - INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23), - INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */ - INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36), -}; - - -static const struct pad_group jsl_community5_groups[] = { - INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */ -}; - -static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { - /* GPP F, B, A, S, R */ - [COMM_0] = { - .port = PID_GPIOCOM0, - .first_pad = GPP_F0, - .last_pad = GPP_R7, - .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_FBASR", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map_com0, - .num_reset_vals = ARRAY_SIZE(rst_map_com0), - .groups = jsl_community0_groups, - .num_groups = ARRAY_SIZE(jsl_community0_groups), - }, - /* GPP H, D, VGPIO, C */ - [COMM_1] = { - .port = PID_GPIOCOM1, - .first_pad = GPP_H0, - .last_pad = GPP_C23, - .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_HDC", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = jsl_community1_groups, - .num_groups = ARRAY_SIZE(jsl_community1_groups), - }, - /* GPD */ - [COMM_2] = { - .port = PID_GPIOCOM2, - .first_pad = GPD0, - .last_pad = GPIO_RSVD_17, - .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = jsl_community2_groups, - .num_groups = ARRAY_SIZE(jsl_community2_groups), - }, - /* GPP E */ - [COMM_4] = { - .port = PID_GPIOCOM4, - .first_pad = GPIO_RSVD_18, - .last_pad = GPIO_RSVD_36, - .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_E", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = jsl_community4_groups, - .num_groups = ARRAY_SIZE(jsl_community4_groups), - }, - /* GPP G */ - [COMM_5] = { - .port = PID_GPIOCOM5, - .first_pad = GPP_G0, - .last_pad = GPP_G7, - .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, - .pad_cfg_base = PAD_CFG_BASE, - .host_own_reg_0 = HOSTSW_OWN_REG_0, - .gpi_int_sts_reg_0 = GPI_INT_STS_0, - .gpi_int_en_reg_0 = GPI_INT_EN_0, - .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, - .gpi_smi_en_reg_0 = GPI_SMI_EN_0, - .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_G", - .acpi_path = "\\_SB.PCI0.GPIO", - .reset_map = rst_map, - .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = jsl_community5_groups, - .num_groups = ARRAY_SIZE(jsl_community5_groups), - } -}; - -const struct pad_community *soc_gpio_get_community(size_t *num_communities) -{ - *num_communities = ARRAY_SIZE(jsl_communities); - return jsl_communities; -} - -const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) -{ - static const struct pmc_to_gpio_route routes[] = { - { PMC_GPP_A, GPP_A }, - { PMC_GPP_B, GPP_B }, - { PMC_GPP_R, GPP_R }, - { PMC_GPP_D, GPP_D }, - { PMC_GPP_S, GPP_S }, - { PMC_GPP_H, GPP_H }, - { PMC_GPD, GPP_GPD }, - { PMC_GPP_C, GPP_C }, - { PMC_GPP_E, GPP_E }, - { PMC_GPP_F, GPP_F } - }; - - *num = ARRAY_SIZE(routes); - return routes; -} diff --git a/src/soc/intel/tigerlake/include/soc/espi.h b/src/soc/intel/tigerlake/include/soc/espi.h index 3f7e32a717..d323f044f7 100644 --- a/src/soc/intel/tigerlake/include/soc/espi.h +++ b/src/soc/intel/tigerlake/include/soc/espi.h @@ -44,15 +44,4 @@ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -/* - * This function will help to differentiate between 2 PCH on single type of soc. - * Since same soc may have LP series pch or H series PCH, we need to - * differentiate by reading upper 8 bits of PCH device ids. - * - * Return: - * Return PCH_LP or PCH_H macro in case of respective device ID found. - * PCH_UNKNOWN_SERIES in case of invalid device ID. - */ -uint8_t get_pch_series(void); - #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index 7a6df7c74f..1793a3f6fe 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -18,21 +18,10 @@ #include #include -#if CONFIG(SOC_INTEL_TIGERLAKE) - - #define CROS_GPIO_NAME "INT34C5" - #define CROS_GPIO_COMM0_NAME "INT34C5:00" - #define CROS_GPIO_COMM1_NAME "INT34C5:01" - #define CROS_GPIO_COMM4_NAME "INT34C5:02" - #define CROS_GPIO_COMM5_NAME "INT34C5:03" - -#elif CONFIG(SOC_INTEL_JASPERLAKE) - - #define CROS_GPIO_NAME "INT34C8" - #define CROS_GPIO_COMM0_NAME "INT34C8:00" - #define CROS_GPIO_COMM1_NAME "INT34C8:01" - #define CROS_GPIO_COMM4_NAME "INT34C8:02" - #define CROS_GPIO_COMM5_NAME "INT34C8:03" -#endif +#define CROS_GPIO_NAME "INT34C5" +#define CROS_GPIO_COMM0_NAME "INT34C5:00" +#define CROS_GPIO_COMM1_NAME "INT34C5:01" +#define CROS_GPIO_COMM4_NAME "INT34C5:02" +#define CROS_GPIO_COMM5_NAME "INT34C5:03" #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index 07835aac2d..c02da0a4b6 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -15,9 +15,300 @@ #ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_DEFS_H_ -#if CONFIG(SOC_INTEL_TIGERLAKE) - #include -#elif CONFIG(SOC_INTEL_JASPERLAKE) - #include +#ifndef __ACPI__ +#include #endif +#include + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + + +/* Group D */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + + +/* Group U */ +#define GPP_U0_IRQ 0x40 +#define GPP_U1IRQ 0x41 +#define GPP_U2_IRQ 0x42 +#define GPP_U3_IRQ 0x43 +#define GPP_U4_IRQ 0x44 +#define GPP_U5_IRQ 0x45 +#define GPP_U6_IRQ 0x46 +#define GPP_U7_IRQ 0x47 +#define GPP_U8_IRQ 0x48 +#define GPP_U9_IRQ 0x49 +#define GPP_U10_IRQ 0x4A +#define GPP_U11_IRQ 0x4B +#define GPP_U12_IRQ 0x4C +#define GPP_U13_IRQ 0x4D +#define GPP_U14_IRQ 0x4E +#define GPP_U15_IRQ 0x4F +#define GPP_U16_IRQ 0x50 +#define GPP_U17_IRQ 0x51 +#define GPP_U18_IRQ 0x52 +#define GPP_U19_IRQ 0x53 + + +#define GPP_VGPIO4_IRQ 0x54 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + + + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h deleted file mode 100644 index 69ed539cae..0000000000 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_ -#define _SOC_JASPERLAKE_GPIO_DEFS_H_ - -#ifndef __ACPI__ -#include -#endif -#include - - -#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ - -#define NUM_GPIO_COMx_GPI_REGS(n) \ - (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) - -#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) -#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) -#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) -#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) - -#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS) +\ - (NUM_GPIO_COM5_GPI_REGS)) -/* - * IOxAPIC IRQs for the GPIOs - */ - -/* Group F */ -#define GPP_F0_IRQ 0x40 -#define GPP_F1_IRQ 0x41 -#define GPP_F2_IRQ 0x42 -#define GPP_F3_IRQ 0x43 -#define GPP_F4_IRQ 0x44 -#define GPP_F5_IRQ 0x45 -#define GPP_F6_IRQ 0x46 -#define GPP_F7_IRQ 0x47 -#define GPP_F8_IRQ 0x48 -#define GPP_F9_IRQ 0x49 -#define GPP_F10_IRQ 0x4a -#define GPP_F11_IRQ 0x4b -#define GPP_F12_IRQ 0x4c -#define GPP_F13_IRQ 0x4d -#define GPP_F14_IRQ 0x4e -#define GPP_F15_IRQ 0x4f -#define GPP_F16_IRQ 0x50 -#define GPP_F17_IRQ 0x51 -#define GPP_F18_IRQ 0x52 -#define GPP_F19_IRQ 0x53 - -/* Group G */ -#define GPP_G0_IRQ 0x18 -#define GPP_G1_IRQ 0x19 -#define GPP_G2_IRQ 0x1a -#define GPP_G3_IRQ 0x1b -#define GPP_G4_IRQ 0x1c -#define GPP_G5_IRQ 0x1d -#define GPP_G6_IRQ 0x1e -#define GPP_G7_IRQ 0x1f - -/* Group B */ -#define GPP_B0_IRQ 0x20 -#define GPP_B1_IRQ 0x21 -#define GPP_B2_IRQ 0x22 -#define GPP_B3_IRQ 0x23 -#define GPP_B4_IRQ 0x24 -#define GPP_B5_IRQ 0x25 -#define GPP_B6_IRQ 0x26 -#define GPP_B7_IRQ 0x27 -#define GPP_B8_IRQ 0x28 -#define GPP_B9_IRQ 0x29 -#define GPP_B10_IRQ 0x2a -#define GPP_B11_IRQ 0x2b -#define GPP_B12_IRQ 0x2c -#define GPP_B13_IRQ 0x2d -#define GPP_B14_IRQ 0x2e -#define GPP_B15_IRQ 0x2f -#define GPP_B16_IRQ 0x30 -#define GPP_B17_IRQ 0x31 -#define GPP_B18_IRQ 0x32 -#define GPP_B19_IRQ 0x33 -#define GPP_B20_IRQ 0x34 -#define GPP_B21_IRQ 0x35 -#define GPP_B22_IRQ 0x36 -#define GPP_B23_IRQ 0x37 - -/* Group A */ -#define GPP_A0_IRQ 0x38 -#define GPP_A1_IRQ 0x39 -#define GPP_A2_IRQ 0x3a -#define GPP_A3_IRQ 0x3b -#define GPP_A4_IRQ 0x3c -#define GPP_A5_IRQ 0x3d -#define GPP_A6_IRQ 0x3e -#define GPP_A7_IRQ 0x3f -#define GPP_A8_IRQ 0x40 -#define GPP_A9_IRQ 0x41 -#define GPP_A10_IRQ 0x42 -#define GPP_A11_IRQ 0x43 -#define GPP_A12_IRQ 0x44 -#define GPP_A13_IRQ 0x45 -#define GPP_A14_IRQ 0x46 -#define GPP_A15_IRQ 0x47 -#define GPP_A16_IRQ 0x48 -#define GPP_A17_IRQ 0x49 -#define GPP_A18_IRQ 0x4a -#define GPP_A19_IRQ 0x4b - -/* Group H */ -#define GPP_H0_IRQ 0x70 -#define GPP_H1_IRQ 0x71 -#define GPP_H2_IRQ 0x72 -#define GPP_H3_IRQ 0x73 -#define GPP_H4_IRQ 0x74 -#define GPP_H5_IRQ 0x75 -#define GPP_H6_IRQ 0x76 -#define GPP_H7_IRQ 0x77 -#define GPP_H8_IRQ 0x18 -#define GPP_H9_IRQ 0x19 -#define GPP_H10_IRQ 0x1a -#define GPP_H11_IRQ 0x1b -#define GPP_H12_IRQ 0x1c -#define GPP_H13_IRQ 0x1d -#define GPP_H14_IRQ 0x1e -#define GPP_H15_IRQ 0x1f -#define GPP_H16_IRQ 0x20 -#define GPP_H17_IRQ 0x21 -#define GPP_H18_IRQ 0x22 -#define GPP_H19_IRQ 0x23 -#define GPP_H20_IRQ 0x24 -#define GPP_H21_IRQ 0x25 -#define GPP_H22_IRQ 0x26 -#define GPP_H23_IRQ 0x27 - -/* Group D */ -#define GPP_D0_IRQ 0x28 -#define GPP_D1_IRQ 0x29 -#define GPP_D2_IRQ 0x2a -#define GPP_D3_IRQ 0x2b -#define GPP_D4_IRQ 0x2c -#define GPP_D5_IRQ 0x2d -#define GPP_D6_IRQ 0x2e -#define GPP_D7_IRQ 0x2f -#define GPP_D8_IRQ 0x30 -#define GPP_D9_IRQ 0x31 -#define GPP_D10_IRQ 0x32 -#define GPP_D11_IRQ 0x33 -#define GPP_D12_IRQ 0x34 -#define GPP_D13_IRQ 0x35 -#define GPP_D14_IRQ 0x36 -#define GPP_D15_IRQ 0x37 -#define GPP_D16_IRQ 0x38 -#define GPP_D17_IRQ 0x39 -#define GPP_D18_IRQ 0x3a -#define GPP_D19_IRQ 0x3b -#define GPP_D20_IRQ 0x3c -#define GPP_D21_IRQ 0x3d -#define GPP_D22_IRQ 0x3e -#define GPP_D23_IRQ 0x3f - -/* Group GPD */ -#define GPD0_IRQ 0x64 -#define GPD1_IRQ 0x65 -#define GPD2_IRQ 0x66 -#define GPD3_IRQ 0x67 -#define GPD4_IRQ 0x68 -#define GPD5_IRQ 0x69 -#define GPD6_IRQ 0x6a -#define GPD7_IRQ 0x6b -#define GPD8_IRQ 0x6c -#define GPD9_IRQ 0x6d -#define GPD10_IRQ 0x6e - -/* Group C */ -#define GPP_C0_IRQ 0x5a -#define GPP_C1_IRQ 0x5b -#define GPP_C2_IRQ 0x5c -#define GPP_C3_IRQ 0x5d -#define GPP_C4_IRQ 0x5e -#define GPP_C5_IRQ 0x5f -#define GPP_C6_IRQ 0x60 -#define GPP_C7_IRQ 0x61 -#define GPP_C8_IRQ 0x62 -#define GPP_C9_IRQ 0x63 -#define GPP_C10_IRQ 0x64 -#define GPP_C11_IRQ 0x65 -#define GPP_C12_IRQ 0x66 -#define GPP_C13_IRQ 0x67 -#define GPP_C14_IRQ 0x68 -#define GPP_C15_IRQ 0x69 -#define GPP_C16_IRQ 0x6a -#define GPP_C17_IRQ 0x6b -#define GPP_C18_IRQ 0x6c -#define GPP_C19_IRQ 0x6d -#define GPP_C20_IRQ 0x6e -#define GPP_C21_IRQ 0x6f -#define GPP_C22_IRQ 0x70 -#define GPP_C23_IRQ 0x71 -/* Group E */ -#define GPP_E0_IRQ 0x72 -#define GPP_E1_IRQ 0x73 -#define GPP_E2_IRQ 0x74 -#define GPP_E3_IRQ 0x75 -#define GPP_E4_IRQ 0x76 -#define GPP_E5_IRQ 0x77 -#define GPP_E6_IRQ 0x18 -#define GPP_E7_IRQ 0x19 -#define GPP_E8_IRQ 0x1a -#define GPP_E9_IRQ 0x1b -#define GPP_E10_IRQ 0x1c -#define GPP_E11_IRQ 0x1d -#define GPP_E12_IRQ 0x1e -#define GPP_E13_IRQ 0x1f -#define GPP_E14_IRQ 0x20 -#define GPP_E15_IRQ 0x21 -#define GPP_E16_IRQ 0x22 -#define GPP_E17_IRQ 0x23 -#define GPP_E18_IRQ 0x24 -#define GPP_E19_IRQ 0x25 -#define GPP_E20_IRQ 0x26 -#define GPP_E21_IRQ 0x27 -#define GPP_E22_IRQ 0x28 -#define GPP_E23_IRQ 0x29 - -/* Group R*/ -#define GPP_R0_IRQ 0x50 -#define GPP_R1_IRQ 0x51 -#define GPP_R2_IRQ 0x52 -#define GPP_R3_IRQ 0x53 -#define GPP_R4_IRQ 0x54 -#define GPP_R5_IRQ 0x55 -#define GPP_R6_IRQ 0x56 -#define GPP_R7_IRQ 0x57 - -/* Group S */ -#define GPP_S0_IRQ 0x5c -#define GPP_S1_IRQ 0x5d -#define GPP_S2_IRQ 0x5e -#define GPP_S3_IRQ 0x5f -#define GPP_S4_IRQ 0x60 -#define GPP_S5_IRQ 0x61 -#define GPP_S6_IRQ 0x62 -#define GPP_S7_IRQ 0x63 - -/* Register defines. */ -#define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xc0 -#define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x120 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1a0 -#define PAD_CFG_BASE 0x600 - -#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h deleted file mode 100644 index 35a15ded66..0000000000 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h +++ /dev/null @@ -1,314 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ -#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ - -#ifndef __ACPI__ -#include -#endif -#include - -#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ - -#define NUM_GPIO_COMx_GPI_REGS(n) \ - (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) - -#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) -#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) -#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) -#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) - -#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS) +\ - (NUM_GPIO_COM5_GPI_REGS)) -/* - * IOxAPIC IRQs for the GPIOs - */ - -/* Group B */ -#define GPP_B0_IRQ 0x18 -#define GPP_B1_IRQ 0x19 -#define GPP_B2_IRQ 0x1A -#define GPP_B3_IRQ 0x1B -#define GPP_B4_IRQ 0x1C -#define GPP_B5_IRQ 0x1D -#define GPP_B6_IRQ 0x1E -#define GPP_B7_IRQ 0x1F -#define GPP_B8_IRQ 0x20 -#define GPP_B9_IRQ 0x21 -#define GPP_B10_IRQ 0x22 -#define GPP_B11_IRQ 0x23 -#define GPP_B12_IRQ 0x24 -#define GPP_B13_IRQ 0x25 -#define GPP_B14_IRQ 0x26 -#define GPP_B15_IRQ 0x27 -#define GPP_B16_IRQ 0x28 -#define GPP_B17_IRQ 0x29 -#define GPP_B18_IRQ 0x2A -#define GPP_B19_IRQ 0x2B -#define GPP_B20_IRQ 0x2C -#define GPP_B21_IRQ 0x2D -#define GPP_B22_IRQ 0x2E -#define GPP_B23_IRQ 0x2F - -/* Group T */ -#define GPP_T0_IRQ 0x30 -#define GPP_T1_IRQ 0x31 -#define GPP_T2_IRQ 0x32 -#define GPP_T3_IRQ 0x33 -#define GPP_T4_IRQ 0x34 -#define GPP_T5_IRQ 0x35 -#define GPP_T6_IRQ 0x36 -#define GPP_T7_IRQ 0x37 -#define GPP_T8_IRQ 0x38 -#define GPP_T9_IRQ 0x39 -#define GPP_T10_IRQ 0x3A -#define GPP_T11IRQ 0x3B -#define GPP_T12_IRQ 0x3C -#define GPP_T13_IRQ 0x3D -#define GPP_T14_IRQ 0x3E -#define GPP_T15_IRQ 0x3F - -/* Group A */ -#define GPP_A0_IRQ 0x40 -#define GPP_A1_IRQ 0x41 -#define GPP_A2_IRQ 0x42 -#define GPP_A3_IRQ 0x43 -#define GPP_A4_IRQ 0x44 -#define GPP_A5_IRQ 0x45 -#define GPP_A6_IRQ 0x46 -#define GPP_A7_IRQ 0x47 -#define GPP_A8_IRQ 0x48 -#define GPP_A9_IRQ 0x49 -#define GPP_A10_IRQ 0x4A -#define GPP_A11_IRQ 0x4B -#define GPP_A12_IRQ 0x4C -#define GPP_A13_IRQ 0x4D -#define GPP_A14_IRQ 0x4E -#define GPP_A15_IRQ 0x4F -#define GPP_A16_IRQ 0x50 -#define GPP_A17_IRQ 0x51 -#define GPP_A18_IRQ 0x52 -#define GPP_A19_IRQ 0x53 -#define GPP_A20_IRQ 0x54 -#define GPP_A21_IRQ 0x55 -#define GPP_A22_IRQ 0x56 -#define GPP_A23_IRQ 0x57 - -/* Group R */ -#define GPP_R0_IRQ 0x58 -#define GPP_R1_IRQ 0x59 -#define GPP_R2_IRQ 0x5A -#define GPP_R3_IRQ 0x5B -#define GPP_R4_IRQ 0x5C -#define GPP_R5_IRQ 0x5D -#define GPP_R6_IRQ 0x5E -#define GPP_R7_IRQ 0x5F - - -/* Group D */ -#define GPD0_IRQ 0x60 -#define GPD1_IRQ 0x61 -#define GPD2_IRQ 0x62 -#define GPD3_IRQ 0x63 -#define GPD4_IRQ 0x64 -#define GPD5_IRQ 0x65 -#define GPD6_IRQ 0x66 -#define GPD7_IRQ 0x67 -#define GPD8_IRQ 0x68 -#define GPD9_IRQ 0x69 -#define GPD10_IRQ 0x6A -#define GPD11_IRQ 0x6B - -/* Group S */ -#define GPP_S0_IRQ 0x6C -#define GPP_S1_IRQ 0x6D -#define GPP_S2_IRQ 0x6E -#define GPP_S3_IRQ 0x6F -#define GPP_S4_IRQ 0x70 -#define GPP_S5_IRQ 0x71 -#define GPP_S6_IRQ 0x72 -#define GPP_S7_IRQ 0x73 - -/* Group H */ -#define GPP_H0_IRQ 0x74 -#define GPP_H1_IRQ 0x75 -#define GPP_H2_IRQ 0x76 -#define GPP_H3_IRQ 0x77 -#define GPP_H4_IRQ 0x18 -#define GPP_H5_IRQ 0x19 -#define GPP_H6_IRQ 0x1A -#define GPP_H7_IRQ 0x1B -#define GPP_H8_IRQ 0x1C -#define GPP_H9_IRQ 0x1D -#define GPP_H10_IRQ 0x1E -#define GPP_H11_IRQ 0x1F -#define GPP_H12_IRQ 0x20 -#define GPP_H13_IRQ 0x21 -#define GPP_H14_IRQ 0x22 -#define GPP_H15_IRQ 0x23 -#define GPP_H16_IRQ 0x24 -#define GPP_H17_IRQ 0x25 -#define GPP_H18_IRQ 0x26 -#define GPP_H19_IRQ 0x27 -#define GPP_H20_IRQ 0x28 -#define GPP_H21_IRQ 0x29 -#define GPP_H22_IRQ 0x2A -#define GPP_H23_IRQ 0x2B - -/* Group D */ -#define GPP_D0_IRQ 0x2C -#define GPP_D1_IRQ 0x2D -#define GPP_D2_IRQ 0x2E -#define GPP_D3_IRQ 0x2F -#define GPP_D4_IRQ 0x30 -#define GPP_D5_IRQ 0x31 -#define GPP_D6_IRQ 0x32 -#define GPP_D7_IRQ 0x33 -#define GPP_D8_IRQ 0x34 -#define GPP_D9_IRQ 0x35 -#define GPP_D10_IRQ 0x36 -#define GPP_D11_IRQ 0x37 -#define GPP_D12_IRQ 0x38 -#define GPP_D13_IRQ 0x39 -#define GPP_D14_IRQ 0x3A -#define GPP_D15_IRQ 0x3B -#define GPP_D16_IRQ 0x3C -#define GPP_D17_IRQ 0x3D -#define GPP_D18_IRQ 0x3E -#define GPP_D19_IRQ 0x3F - - -/* Group U */ -#define GPP_U0_IRQ 0x40 -#define GPP_U1IRQ 0x41 -#define GPP_U2_IRQ 0x42 -#define GPP_U3_IRQ 0x43 -#define GPP_U4_IRQ 0x44 -#define GPP_U5_IRQ 0x45 -#define GPP_U6_IRQ 0x46 -#define GPP_U7_IRQ 0x47 -#define GPP_U8_IRQ 0x48 -#define GPP_U9_IRQ 0x49 -#define GPP_U10_IRQ 0x4A -#define GPP_U11_IRQ 0x4B -#define GPP_U12_IRQ 0x4C -#define GPP_U13_IRQ 0x4D -#define GPP_U14_IRQ 0x4E -#define GPP_U15_IRQ 0x4F -#define GPP_U16_IRQ 0x50 -#define GPP_U17_IRQ 0x51 -#define GPP_U18_IRQ 0x52 -#define GPP_U19_IRQ 0x53 - - -#define GPP_VGPIO4_IRQ 0x54 - -/* Group F */ -#define GPP_F0_IRQ 0x56 -#define GPP_F1_IRQ 0x57 -#define GPP_F2_IRQ 0x58 -#define GPP_F3_IRQ 0x59 -#define GPP_F4_IRQ 0x5A -#define GPP_F5_IRQ 0x5B -#define GPP_F6_IRQ 0x5C -#define GPP_F7_IRQ 0x5D -#define GPP_F8_IRQ 0x5E -#define GPP_F9_IRQ 0x5F -#define GPP_F10_IRQ 0x60 -#define GPP_F11_IRQ 0x61 -#define GPP_F12_IRQ 0x62 -#define GPP_F13_IRQ 0x63 -#define GPP_F14_IRQ 0x64 -#define GPP_F15_IRQ 0x65 -#define GPP_F16_IRQ 0x66 -#define GPP_F17_IRQ 0x67 -#define GPP_F18_IRQ 0x68 -#define GPP_F19_IRQ 0x69 -#define GPP_F20_IRQ 0x6A -#define GPP_F21_IRQ 0x6B -#define GPP_F22_IRQ 0x6C -#define GPP_F23_IRQ 0x6D - -/* Group C */ -#define GPP_C0_iIRQ 0x6E -#define GPP_C1_IRQ 0x6F -#define GPP_C2_IRQ 0x70 -#define GPP_C3_IRQ 0x71 -#define GPP_C4_IRQ 0x72 -#define GPP_C5_IRQ 0x73 -#define GPP_C6_IRQ 0x74 -#define GPP_C7_IRQ 0x75 -#define GPP_C8_IRQ 0x76 -#define GPP_C9_IRQ 0x77 -#define GPP_C10_IRQ 0x18 -#define GPP_C11_IRQ 0x19 -#define GPP_C12_IRQ 0x1A -#define GPP_C13_IRQ 0x1B -#define GPP_C14_IRQ 0x1C -#define GPP_C15_IRQ 0x1D -#define GPP_C16_IRQ 0x1E -#define GPP_C17_IRQ 0x1F -#define GPP_C18_IRQ 0x20 -#define GPP_C19_IRQ 0x21 -#define GPP_C20_IRQ 0x22 -#define GPP_C21_IRQ 0x23 -#define GPP_C22_IRQ 0x24 -#define GPP_C23_IRQ 0x25 - - - -/* Group E */ -#define GPP_E0_IRQ 0x26 -#define GPP_E1_IRQ 0x27 -#define GPP_E2_IRQ 0x28 -#define GPP_E3_IRQ 0x29 -#define GPP_E4_IRQ 0x30 -#define GPP_E5_IRQ 0x31 -#define GPP_E6_IRQ 0x32 -#define GPP_E7_IRQ 0x33 -#define GPP_E8_IRQ 0x34 -#define GPP_E9_IRQ 0x35 -#define GPP_E10_IRQ 0x36 -#define GPP_E11_IRQ 0x37 -#define GPP_E12_IRQ 0x38 -#define GPP_E13_IRQ 0x39 -#define GPP_E14_IRQ 0x3A -#define GPP_E15_IRQ 0x3B -#define GPP_E16_IRQ 0x3C -#define GPP_E17_IRQ 0x3D -#define GPP_E18_IRQ 0x3E -#define GPP_E19_IRQ 0x3F -#define GPP_E20_IRQ 0x40 -#define GPP_E21_IRQ 0x41 -#define GPP_E22_IRQ 0x42 -#define GPP_E23_IRQ 0x43 - -/* Register defines. */ -#define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xb0 -#define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x110 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1A0 -#define PAD_CFG_BASE 0x700 - -#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index 28551ba28a..a505c73287 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -13,11 +13,382 @@ */ #ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 +#define GPP_S 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_U 0x8 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC -#if CONFIG(SOC_INTEL_TIGERLAKE) - #include "gpio_soc_defs_tgl.h" -#elif CONFIG(SOC_INTEL_JASPERLAKE) - #include "gpio_soc_defs_jsl.h" -#endif +#define GPIO_MAX_NUM_PER_GROUP 27 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_A24 +#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +/* Group U */ +#define GPP_U0 120 +#define GPP_U1 121 +#define GPP_U2 122 +#define GPP_U3 123 +#define GPP_U4 124 +#define GPP_U5 125 +#define GPP_U6 126 +#define GPP_U7 127 +#define GPP_U8 128 +#define GPP_U9 129 +#define GPP_U10 130 +#define GPP_U11 131 +#define GPP_U12 132 +#define GPP_U13 133 +#define GPP_U14 134 +#define GPP_U15 135 +#define GPP_U16 136 +#define GPP_U17 137 +#define GPP_U18 138 +#define GPP_U19 139 +#define GPP_GSPI3_CLK_LOOPBK 140 +#define GPP_GSPI4_CLK_LOOPBK 141 +#define GPP_GSPI5_CLK_LOOPBK 142 +#define GPP_GSPI6_CLK_LOOPBK 143 + +/* Group VGPIO */ +#define CNV_BTEN 144 +#define CNV_BT_HOST_WAKEB 145 +#define CNV_BT_IF_SELECT 146 +#define vCNV_BT_UART_TXD 147 +#define vCNV_BT_UART_RXD 148 +#define vCNV_BT_UART_CTS_B 149 +#define vCNV_BT_UART_RTS_B 150 +#define vCNV_MFUART1_TXD 151 +#define vCNV_MFUART1_RXD 152 +#define vCNV_MFUART1_CTS_B 153 +#define vCNV_MFUART1_RTS_B 154 +#define vUART0_TXD 155 +#define vUART0_RXD 156 +#define vUART0_CTS_B 157 +#define vUART0_RTS_B 158 +#define vISH_UART0_TXD 159 +#define vISH_UART0_RXD 160 +#define vISH_UART0_CTS_B 161 +#define vISH_UART0_RTS_B 162 +#define vCNV_BT_I2S_BCLK 163 +#define vCNV_BT_I2S_WS_SYNC 164 +#define vCNV_BT_I2S_SDO 165 +#define vCNV_BT_I2S_SDI 166 +#define vI2S2_SCLK 167 +#define vI2S2_SFRM 168 +#define vI2S2_TXD 169 +#define vI2S2_RXD 170 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END vI2S2_RXD +#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) + +/* Group GPD */ +#define GPD0 171 +#define GPD1 172 +#define GPD2 173 +#define GPD3 174 +#define GPD4 175 +#define GPD5 176 +#define GPD6 177 +#define GPD7 178 +#define GPD8 179 +#define GPD9 180 +#define GPD10 181 +#define GPD11 182 +#define GPD_INPUT3VSEL 183 +#define GPD_SLP_LANB 184 +#define GPD__SLP_SUSB 185 +#define GPD_WAKEB 186 +#define GPD_DRAM_RESETB 187 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) + +/* Group C */ +#define GPP_C0 188 +#define GPP_C1 189 +#define GPP_C2 190 +#define GPP_C3 191 +#define GPP_C4 192 +#define GPP_C5 193 +#define GPP_C6 194 +#define GPP_C7 195 +#define GPP_C8 196 +#define GPP_C9 197 +#define GPP_C10 198 +#define GPP_C11 199 +#define GPP_C12 200 +#define GPP_C13 201 +#define GPP_C14 202 +#define GPP_C15 203 +#define GPP_C16 204 +#define GPP_C17 205 +#define GPP_C18 206 +#define GPP_C19 207 +#define GPP_C20 208 +#define GPP_C21 209 +#define GPP_C22 210 +#define GPP_C23 211 + +/* Group F */ +#define GPP_F0 212 +#define GPP_F1 213 +#define GPP_F2 214 +#define GPP_F3 215 +#define GPP_F4 216 +#define GPP_F5 217 +#define GPP_F6 218 +#define GPP_F7 219 +#define GPP_F8 220 +#define GPP_F9 221 +#define GPP_F10 222 +#define GPP_F11 223 +#define GPP_F12 224 +#define GPP_F13 225 +#define GPP_F14 226 +#define GPP_F15 227 +#define GPP_F16 228 +#define GPP_F17 229 +#define GPP_F18 230 +#define GPP_F19 231 +#define GPP_F20 232 +#define GPP_F21 233 +#define GPP_F22 234 +#define GPP_F23 235 +#define GPP_F_CLK_LOOPBK 236 + +/* Group HVCMOS */ +#define GPP_L_BKLTEN 237 +#define GPP_L_BKLTCTL 238 +#define GPP_L_VDDEN 239 +#define GPP_SYS_PWROK 240 +#define GPP_SYS_RESETB 241 +#define GPP_MLK_RSTB 242 + +/* Group E */ +#define GPP_E0 243 +#define GPP_E1 244 +#define GPP_E2 245 +#define GPP_E3 246 +#define GPP_E4 247 +#define GPP_E5 248 +#define GPP_E6 249 +#define GPP_E7 250 +#define GPP_E8 251 +#define GPP_E9 252 +#define GPP_E10 253 +#define GPP_E11 254 +#define GPP_E12 255 +#define GPP_E13 256 +#define GPP_E14 257 +#define GPP_E15 258 +#define GPP_E16 259 +#define GPP_E17 260 +#define GPP_E18 261 +#define GPP_E19 262 +#define GPP_E20 263 +#define GPP_E21 264 +#define GPP_E22 265 +#define GPP_E23 266 +#define GPP_E_CLK_LOOPBK 267 + +/* Group JTAG */ +#define GPP_JTAG_TDO 268 +#define GPP_JTAG_X 269 +#define GPP_JTAG_PRDYB 270 +#define GPP_JTAG_PREQB 271 +#define GPP_CPU_TRSTB 272 +#define GPP_JTAG_TDI 273 +#define GPP_JTAG_TMS 274 +#define GPP_JTAG_TCK 275 +#define GPP_DBG_PMODE 276 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_DBG_PMODE +#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) + +/* Group R */ +#define GPP_R0 277 +#define GPP_R1 278 +#define GPP_R2 279 +#define GPP_R3 280 +#define GPP_R4 281 +#define GPP_R5 282 +#define GPP_R6 283 +#define GPP_R7 284 + +/* Group SPI */ +#define GPP_SPI_IO_2 285 +#define GPP_SPI_IO_3 286 +#define GPP_SPI_MOSI_IO_0 287 +#define GPP_SPI_MOSI_IO_1 288 +#define GPP_SPI_TPM_CSB 289 +#define GPP_SPI_FLASH_0_CSB 290 +#define GPP_SPI_FLASH_1_CSB 291 +#define GPP_SPI_CLK 292 +#define GPP_CLK_LOOPBK 293 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_CLK_LOOPBK +#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS 294 #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h deleted file mode 100644 index 2ee52b260f..0000000000 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ -#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ - -/* - * Most of the fixed numbers and macros are based on the GPP groups. - * The GPIO groups are accessed through register blocks called - * communities. - */ - -#define GPP_A 0x0 -#define GPP_B 0x1 -#define GPP_G 0x2 -#define GPP_C 0x3 -#define GPP_R 0x4 -#define GPP_D 0x5 -#define GPP_S 0x6 -#define GPP_H 0x7 -#define GPP_VGPIO 0x8 -#define GPP_F 0x9 -#define GPP_GPD 0xA -#define GPP_E 0xD - -#define GPIO_NUM_GROUPS 12 -#define GPIO_MAX_NUM_PER_GROUP 24 - -/* - * GPIOs are ordered monotonically increasing to match ACPI/OS driver. - */ - -/* Group F */ -#define GPP_F0 0 -#define GPP_F1 1 -#define GPP_F2 2 -#define GPP_F3 3 -#define GPP_F4 4 -#define GPP_F5 5 -#define GPP_F6 6 -#define GPP_F7 7 -#define GPP_F8 8 -#define GPP_F9 9 -#define GPP_F10 10 -#define GPP_F11 11 -#define GPP_F12 12 -#define GPP_F13 13 -#define GPP_F14 14 -#define GPP_F15 15 -#define GPP_F16 16 -#define GPP_F17 17 -#define GPP_F18 18 -#define GPP_F19 19 - -/* Group B */ -#define GPIO_RSVD_0 20 -#define GPIO_RSVD_1 21 -#define GPIO_RSVD_2 22 -#define GPIO_RSVD_3 23 -#define GPIO_RSVD_4 24 -#define GPIO_RSVD_5 25 -#define GPIO_RSVD_6 26 -#define GPIO_RSVD_7 27 -#define GPIO_RSVD_8 28 -#define GPP_B0 29 -#define GPP_B1 30 -#define GPP_B2 31 -#define GPP_B3 32 -#define GPP_B4 33 -#define GPP_B5 34 -#define GPP_B6 35 -#define GPP_B7 36 -#define GPP_B8 37 -#define GPP_B9 38 -#define GPP_B10 39 -#define GPP_B11 40 -#define GPP_B12 41 -#define GPP_B13 42 -#define GPP_B14 43 -#define GPP_B15 44 -#define GPP_B16 45 -#define GPP_B17 46 -#define GPP_B18 47 -#define GPP_B19 48 -#define GPP_B20 49 -#define GPP_B21 50 -#define GPP_B22 51 -#define GPP_B23 52 -#define GPIO_RSVD_9 53 -#define GPIO_RSVD_10 54 - -/* Group A */ -#define GPP_A0 55 -#define GPP_A1 56 -#define GPP_A2 57 -#define GPP_A3 58 -#define GPP_A4 59 -#define GPP_A5 60 -#define GPP_A6 61 -#define GPP_A7 62 -#define GPP_A8 63 -#define GPP_A9 64 -#define GPP_A10 65 -#define GPP_A11 66 -#define GPP_A12 67 -#define GPP_A13 68 -#define GPP_A14 69 -#define GPP_A15 70 -#define GPP_A16 71 -#define GPP_A17 72 -#define GPP_A18 73 -#define GPP_A19 74 -#define GPIO_RSVD_11 75 - -/* Group S */ -#define GPP_S0 76 -#define GPP_S1 77 -#define GPP_S2 78 -#define GPP_S3 79 -#define GPP_S4 80 -#define GPP_S5 81 -#define GPP_S6 82 -#define GPP_S7 83 - -/* Group R */ -#define GPP_R0 84 -#define GPP_R1 85 -#define GPP_R2 86 -#define GPP_R3 87 -#define GPP_R4 88 -#define GPP_R5 89 -#define GPP_R6 90 -#define GPP_R7 91 - -#define GPIO_COM0_START GPP_F0 -#define GPIO_COM0_END GPP_R7 -#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) - -/* Group H */ -#define GPP_H0 92 -#define GPP_H1 93 -#define GPP_H2 94 -#define GPP_H3 95 -#define GPP_H4 96 -#define GPP_H5 97 -#define GPP_H6 98 -#define GPP_H7 99 -#define GPP_H8 100 -#define GPP_H9 101 -#define GPP_H10 102 -#define GPP_H11 103 -#define GPP_H12 104 -#define GPP_H13 105 -#define GPP_H14 106 -#define GPP_H15 107 -#define GPP_H16 108 -#define GPP_H17 109 -#define GPP_H18 110 -#define GPP_H19 111 -#define GPP_H20 112 -#define GPP_H21 113 -#define GPP_H22 114 -#define GPP_H23 115 - -/* Group D */ -#define GPP_D0 116 -#define GPP_D1 117 -#define GPP_D2 118 -#define GPP_D3 119 -#define GPP_D4 120 -#define GPP_D5 121 -#define GPP_D6 122 -#define GPP_D7 123 -#define GPP_D8 124 -#define GPP_D9 125 -#define GPP_D10 126 -#define GPP_D11 127 -#define GPP_D12 128 -#define GPP_D13 129 -#define GPP_D14 130 -#define GPP_D15 131 -#define GPP_D16 132 -#define GPP_D17 133 -#define GPP_D18 134 -#define GPP_D19 135 -#define GPP_D20 136 -#define GPP_D21 137 -#define GPP_D22 138 -#define GPP_D23 139 -#define GPIO_RSVD_12 140 -#define GPIO_RSVD_13 141 - -/* Group VGPIO */ -#define VGPIO_0 142 -#define VGPIO_3 143 -#define VGPIO_4 144 -#define VGPIO_5 145 -#define VGPIO_6 146 -#define VGPIO_7 147 -#define VGPIO_8 148 -#define VGPIO_9 149 -#define VGPIO_10 150 -#define VGPIO_11 151 -#define VGPIO_12 152 -#define VGPIO_13 153 -#define VGPIO_18 154 -#define VGPIO_19 155 -#define VGPIO_20 156 -#define VGPIO_21 157 -#define VGPIO_22 158 -#define VGPIO_23 159 -#define VGPIO_24 160 -#define VGPIO_25 161 -#define VGPIO_30 162 -#define VGPIO_31 163 -#define VGPIO_32 164 -#define VGPIO_33 165 -#define VGPIO_34 166 -#define VGPIO_35 167 -#define VGPIO_36 168 -#define VGPIO_37 169 -#define VGPIO_39 170 - -/* Group C */ -#define GPP_C0 171 -#define GPP_C1 172 -#define GPP_C2 173 -#define GPP_C3 174 -#define GPP_C4 175 -#define GPP_C5 176 -#define GPP_C6 177 -#define GPP_C7 178 -#define GPP_C8 179 -#define GPP_C9 180 -#define GPP_C10 181 -#define GPP_C11 182 -#define GPP_C12 183 -#define GPP_C13 184 -#define GPP_C14 185 -#define GPP_C15 186 -#define GPP_C16 187 -#define GPP_C17 188 -#define GPP_C18 189 -#define GPP_C19 190 -#define GPP_C20 191 -#define GPP_C21 192 -#define GPP_C22 193 -#define GPP_C23 194 - -#define GPIO_COM1_START GPP_H0 -#define GPIO_COM1_END GPP_C23 -#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) - -/* Group GPD */ -#define GPD0 195 -#define GPD1 196 -#define GPD2 197 -#define GPD3 198 -#define GPD4 199 -#define GPD5 200 -#define GPD6 201 -#define GPD7 202 -#define GPD8 203 -#define GPD9 204 -#define GPD10 205 -#define GPIO_RSVD_14 206 -#define GPIO_RSVD_15 207 -#define GPIO_RSVD_16 208 -#define GPIO_RSVD_17 209 - -#define GPIO_COM2_START GPD0 -#define GPIO_COM2_END GPIO_RSVD_17 -#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) - -/* Group E */ -#define GPIO_RSVD_18 210 -#define GPIO_RSVD_19 211 -#define GPIO_RSVD_20 212 -#define GPIO_RSVD_21 213 -#define GPIO_RSVD_22 214 -#define GPIO_RSVD_23 215 -#define GPP_E0 216 -#define GPP_E1 217 -#define GPP_E2 218 -#define GPP_E3 219 -#define GPP_E4 220 -#define GPP_E5 221 -#define GPP_E6 222 -#define GPP_E7 223 -#define GPP_E8 224 -#define GPP_E9 225 -#define GPP_E10 226 -#define GPP_E11 227 -#define GPP_E12 228 -#define GPP_E13 229 -#define GPP_E14 230 -#define GPP_E15 231 -#define GPP_E16 232 -#define GPP_E17 233 -#define GPP_E18 234 -#define GPP_E19 235 -#define GPP_E20 236 -#define GPP_E21 237 -#define GPP_E22 238 -#define GPP_E23 239 -#define GPIO_RSVD_24 240 -#define GPIO_RSVD_25 241 -#define GPIO_RSVD_26 242 -#define GPIO_RSVD_27 243 -#define GPIO_RSVD_28 244 -#define GPIO_RSVD_29 245 -#define GPIO_RSVD_30 246 -#define GPIO_RSVD_31 247 -#define GPIO_RSVD_32 248 -#define GPIO_RSVD_33 249 -#define GPIO_RSVD_34 250 -#define GPIO_RSVD_35 251 -#define GPIO_RSVD_36 252 - -#define GPIO_COM4_START GPIO_RSVD_18 -#define GPIO_COM4_END GPIO_RSVD_36 -#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) - -/* Group G */ -#define GPP_G0 253 -#define GPP_G1 254 -#define GPP_G2 255 -#define GPP_G3 256 -#define GPP_G4 257 -#define GPP_G5 258 -#define GPP_G6 259 -#define GPP_G7 260 - -#define GPIO_COM5_START GPP_G0 -#define GPIO_COM5_END GPP_G7 -#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) - -#define TOTAL_PADS 261 - -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -#define COMM_4 3 -#define COMM_5 4 -#define TOTAL_GPIO_COMM 5 - -#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h deleted file mode 100644 index ec582c3133..0000000000 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ -#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ -/* - * Most of the fixed numbers and macros are based on the GPP groups. - * The GPIO groups are accessed through register blocks called - * communities. - */ -#define GPP_B 0x0 -#define GPP_T 0x1 -#define GPP_A 0x2 -#define GPP_R 0x3 -#define GPD 0x4 -#define GPP_S 0x5 -#define GPP_H 0x6 -#define GPP_D 0x7 -#define GPP_U 0x8 -#define GPP_F 0xA -#define GPP_C 0xB -#define GPP_E 0xC - -#define GPIO_MAX_NUM_PER_GROUP 27 - -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -/* GPIO community 3 is not exposed to be used and hence is skipped. */ -#define COMM_4 3 -#define COMM_5 4 -/* - * GPIOs are ordered monotonically increasing to match ACPI/OS driver. - */ -/* Group B */ -#define GPP_B0 0 -#define GPP_B1 1 -#define GPP_B2 2 -#define GPP_B3 3 -#define GPP_B4 4 -#define GPP_B5 5 -#define GPP_B6 6 -#define GPP_B7 7 -#define GPP_B8 8 -#define GPP_B9 9 -#define GPP_B10 10 -#define GPP_B11 11 -#define GPP_B12 12 -#define GPP_B13 13 -#define GPP_B14 14 -#define GPP_B15 15 -#define GPP_B16 16 -#define GPP_B17 17 -#define GPP_B18 18 -#define GPP_B19 19 -#define GPP_B20 20 -#define GPP_B21 21 -#define GPP_B22 22 -#define GPP_B23 23 -#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ -#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ - -/* Group T */ -#define GPP_T0 26 -#define GPP_T1 27 -#define GPP_T2 28 -#define GPP_T3 29 -#define GPP_T4 30 -#define GPP_T5 31 -#define GPP_T6 32 -#define GPP_T7 33 -#define GPP_T8 34 -#define GPP_T9 35 -#define GPP_T10 36 -#define GPP_T11 37 -#define GPP_T12 38 -#define GPP_T13 39 -#define GPP_T14 40 -#define GPP_T15 41 - -/* Group A */ -#define GPP_A0 42 -#define GPP_A1 43 -#define GPP_A2 44 -#define GPP_A3 45 -#define GPP_A4 46 -#define GPP_A5 47 -#define GPP_A6 48 -#define GPP_A7 49 -#define GPP_A8 50 -#define GPP_A9 51 -#define GPP_A10 52 -#define GPP_A11 53 -#define GPP_A12 54 -#define GPP_A13 55 -#define GPP_A14 56 -#define GPP_A15 57 -#define GPP_A16 58 -#define GPP_A17 59 -#define GPP_A18 60 -#define GPP_A19 61 -#define GPP_A20 62 -#define GPP_A21 63 -#define GPP_A22 64 -#define GPP_A23 65 -#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ - -#define GPIO_COM0_START GPP_B0 -#define GPIO_COM0_END GPP_A24 -#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) - -/* Group S */ -#define GPP_S0 67 -#define GPP_S1 68 -#define GPP_S2 69 -#define GPP_S3 70 -#define GPP_S4 71 -#define GPP_S5 72 -#define GPP_S6 73 -#define GPP_S7 74 - -/* Group H */ -#define GPP_H0 75 -#define GPP_H1 76 -#define GPP_H2 77 -#define GPP_H3 78 -#define GPP_H4 79 -#define GPP_H5 80 -#define GPP_H6 81 -#define GPP_H7 82 -#define GPP_H8 83 -#define GPP_H9 84 -#define GPP_H10 85 -#define GPP_H11 86 -#define GPP_H12 87 -#define GPP_H13 88 -#define GPP_H14 89 -#define GPP_H15 90 -#define GPP_H16 91 -#define GPP_H17 92 -#define GPP_H18 93 -#define GPP_H19 94 -#define GPP_H20 95 -#define GPP_H21 96 -#define GPP_H22 97 -#define GPP_H23 98 - -/* Group D */ -#define GPP_D0 99 -#define GPP_D1 100 -#define GPP_D2 101 -#define GPP_D3 102 -#define GPP_D4 103 -#define GPP_D5 104 -#define GPP_D6 105 -#define GPP_D7 106 -#define GPP_D8 107 -#define GPP_D9 108 -#define GPP_D10 109 -#define GPP_D11 110 -#define GPP_D12 111 -#define GPP_D13 112 -#define GPP_D14 113 -#define GPP_D15 114 -#define GPP_D16 115 -#define GPP_D17 116 -#define GPP_D18 117 -#define GPP_D19 118 -#define GPP_GSPI2_CLK_LOOPBK 119 - -/* Group U */ -#define GPP_U0 120 -#define GPP_U1 121 -#define GPP_U2 122 -#define GPP_U3 123 -#define GPP_U4 124 -#define GPP_U5 125 -#define GPP_U6 126 -#define GPP_U7 127 -#define GPP_U8 128 -#define GPP_U9 129 -#define GPP_U10 130 -#define GPP_U11 131 -#define GPP_U12 132 -#define GPP_U13 133 -#define GPP_U14 134 -#define GPP_U15 135 -#define GPP_U16 136 -#define GPP_U17 137 -#define GPP_U18 138 -#define GPP_U19 139 -#define GPP_GSPI3_CLK_LOOPBK 140 -#define GPP_GSPI4_CLK_LOOPBK 141 -#define GPP_GSPI5_CLK_LOOPBK 142 -#define GPP_GSPI6_CLK_LOOPBK 143 - -/* Group VGPIO */ -#define CNV_BTEN 144 -#define CNV_BT_HOST_WAKEB 145 -#define CNV_BT_IF_SELECT 146 -#define vCNV_BT_UART_TXD 147 -#define vCNV_BT_UART_RXD 148 -#define vCNV_BT_UART_CTS_B 149 -#define vCNV_BT_UART_RTS_B 150 -#define vCNV_MFUART1_TXD 151 -#define vCNV_MFUART1_RXD 152 -#define vCNV_MFUART1_CTS_B 153 -#define vCNV_MFUART1_RTS_B 154 -#define vUART0_TXD 155 -#define vUART0_RXD 156 -#define vUART0_CTS_B 157 -#define vUART0_RTS_B 158 -#define vISH_UART0_TXD 159 -#define vISH_UART0_RXD 160 -#define vISH_UART0_CTS_B 161 -#define vISH_UART0_RTS_B 162 -#define vCNV_BT_I2S_BCLK 163 -#define vCNV_BT_I2S_WS_SYNC 164 -#define vCNV_BT_I2S_SDO 165 -#define vCNV_BT_I2S_SDI 166 -#define vI2S2_SCLK 167 -#define vI2S2_SFRM 168 -#define vI2S2_TXD 169 -#define vI2S2_RXD 170 - -#define GPIO_COM1_START GPP_S0 -#define GPIO_COM1_END vI2S2_RXD -#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) - -/* Group GPD */ -#define GPD0 171 -#define GPD1 172 -#define GPD2 173 -#define GPD3 174 -#define GPD4 175 -#define GPD5 176 -#define GPD6 177 -#define GPD7 178 -#define GPD8 179 -#define GPD9 180 -#define GPD10 181 -#define GPD11 182 -#define GPD_INPUT3VSEL 183 -#define GPD_SLP_LANB 184 -#define GPD__SLP_SUSB 185 -#define GPD_WAKEB 186 -#define GPD_DRAM_RESETB 187 - -#define GPIO_COM2_START GPD0 -#define GPIO_COM2_END GPD_DRAM_RESETB -#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) - -/* Group C */ -#define GPP_C0 188 -#define GPP_C1 189 -#define GPP_C2 190 -#define GPP_C3 191 -#define GPP_C4 192 -#define GPP_C5 193 -#define GPP_C6 194 -#define GPP_C7 195 -#define GPP_C8 196 -#define GPP_C9 197 -#define GPP_C10 198 -#define GPP_C11 199 -#define GPP_C12 200 -#define GPP_C13 201 -#define GPP_C14 202 -#define GPP_C15 203 -#define GPP_C16 204 -#define GPP_C17 205 -#define GPP_C18 206 -#define GPP_C19 207 -#define GPP_C20 208 -#define GPP_C21 209 -#define GPP_C22 210 -#define GPP_C23 211 - -/* Group F */ -#define GPP_F0 212 -#define GPP_F1 213 -#define GPP_F2 214 -#define GPP_F3 215 -#define GPP_F4 216 -#define GPP_F5 217 -#define GPP_F6 218 -#define GPP_F7 219 -#define GPP_F8 220 -#define GPP_F9 221 -#define GPP_F10 222 -#define GPP_F11 223 -#define GPP_F12 224 -#define GPP_F13 225 -#define GPP_F14 226 -#define GPP_F15 227 -#define GPP_F16 228 -#define GPP_F17 229 -#define GPP_F18 230 -#define GPP_F19 231 -#define GPP_F20 232 -#define GPP_F21 233 -#define GPP_F22 234 -#define GPP_F23 235 -#define GPP_F_CLK_LOOPBK 236 - -/* Group HVCMOS */ -#define GPP_L_BKLTEN 237 -#define GPP_L_BKLTCTL 238 -#define GPP_L_VDDEN 239 -#define GPP_SYS_PWROK 240 -#define GPP_SYS_RESETB 241 -#define GPP_MLK_RSTB 242 - -/* Group E */ -#define GPP_E0 243 -#define GPP_E1 244 -#define GPP_E2 245 -#define GPP_E3 246 -#define GPP_E4 247 -#define GPP_E5 248 -#define GPP_E6 249 -#define GPP_E7 250 -#define GPP_E8 251 -#define GPP_E9 252 -#define GPP_E10 253 -#define GPP_E11 254 -#define GPP_E12 255 -#define GPP_E13 256 -#define GPP_E14 257 -#define GPP_E15 258 -#define GPP_E16 259 -#define GPP_E17 260 -#define GPP_E18 261 -#define GPP_E19 262 -#define GPP_E20 263 -#define GPP_E21 264 -#define GPP_E22 265 -#define GPP_E23 266 -#define GPP_E_CLK_LOOPBK 267 - -/* Group JTAG */ -#define GPP_JTAG_TDO 268 -#define GPP_JTAG_X 269 -#define GPP_JTAG_PRDYB 270 -#define GPP_JTAG_PREQB 271 -#define GPP_CPU_TRSTB 272 -#define GPP_JTAG_TDI 273 -#define GPP_JTAG_TMS 274 -#define GPP_JTAG_TCK 275 -#define GPP_DBG_PMODE 276 - -#define GPIO_COM4_START GPP_C0 -#define GPIO_COM4_END GPP_DBG_PMODE -#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) - -/* Group R */ -#define GPP_R0 277 -#define GPP_R1 278 -#define GPP_R2 279 -#define GPP_R3 280 -#define GPP_R4 281 -#define GPP_R5 282 -#define GPP_R6 283 -#define GPP_R7 284 - -/* Group SPI */ -#define GPP_SPI_IO_2 285 -#define GPP_SPI_IO_3 286 -#define GPP_SPI_MOSI_IO_0 287 -#define GPP_SPI_MOSI_IO_1 288 -#define GPP_SPI_TPM_CSB 289 -#define GPP_SPI_FLASH_0_CSB 290 -#define GPP_SPI_FLASH_1_CSB 291 -#define GPP_SPI_CLK 292 -#define GPP_CLK_LOOPBK 293 - -#define GPIO_COM5_START GPP_R0 -#define GPIO_COM5_END GPP_CLK_LOOPBK -#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) - -#define TOTAL_GPIO_COMM (COMM_5 + 1) -#define TOTAL_PADS 294 - -#endif diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 361c296547..554067f28f 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -91,7 +91,6 @@ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) -#if CONFIG(SOC_INTEL_TIGERLAKE) #define MCH_BASE_ADDRESS 0xfedc0000 #define MCH_BASE_SIZE 0x20000 @@ -101,17 +100,6 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) -#else /* CONFIG_SOC_INTEL_JASPERLAKE */ - -#define MCH_BASE_ADDRESS 0xfea80000 -#define MCH_BASE_SIZE 0x8000 - -#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 - -#define EARLY_I2C_BASE_ADDRESS 0xfe040000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) - -#endif /* * I/O port address space diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index b87467ad5b..818cd31be6 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -15,10 +15,69 @@ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ -#if CONFIG(SOC_INTEL_TIGERLAKE) - #include "irq_tgl.h" -#else - #include "irq_jsl.h" -#endif /* CONFIG_SOC_INTEL_TIGERLAKE */ +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 18 +#define LPSS_SPI3_IRQ 23 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 + +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 + +#define CNVI_BT_IRQ 18 + +#define THC0_IRQ 16 +#define THC1_IRQ 17 + +#define ISH_IRQ 16 + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 + +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_jsl.h b/src/soc/intel/tigerlake/include/soc/irq_jsl.h deleted file mode 100644 index a6edd23d97..0000000000 --- a/src/soc/intel/tigerlake/include/soc/irq_jsl.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_JSL_IRQ_H_ -#define _SOC_JSL_IRQ_H_ - -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 - -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -/* LPSS Devices */ -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 - -/* PCI D:31 F:x */ -#define cAVS_INTA_IRQ 16 -#define SMBUS_INTA_IRQ 16 -#define SMBUS_INTB_IRQ 17 -#define GbE_INTA_IRQ 16 -#define GbE_INTC_IRQ 18 -#define TRACE_HUB_INTA_IRQ 16 -#define TRACE_HUB_INTD_IRQ 19 - -/* PCI D:28 F:x */ -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 - -/* PCI D:26 F:x */ -#define eMMC_IRQ 16 - -/* PCI D:23 F:x */ -#define SATA_IRQ 16 - -/* PCI D:22 F:x */ -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 -#define IDER_IRQ 18 -#define KT_IRQ 19 - -/* PCI D:20 F:x */ -#define XHCI_IRQ 16 -#define OTG_IRQ 17 -#define CNViWIFI_IRQ 16 -#define SD_IRQ 19 -#define PMC_SRAM_IRQ 18 - -/* PCI D:18 F:x */ -#define UFS_IRQ 16 - -#define IGFX_IRQ 16 -#define SA_THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 - -#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h deleted file mode 100644 index 6f268c1eae..0000000000 --- a/src/soc/intel/tigerlake/include/soc/irq_tgl.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_TGL_IRQ_H_ -#define _SOC_TGL_IRQ_H_ - -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 - -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 28 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 18 -#define LPSS_SPI3_IRQ 23 -#define LPSS_UART0_IRQ 34 -#define LPSS_UART1_IRQ 35 -#define LPSS_UART2_IRQ 33 - -#define HDA_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 - -#define THC0_IRQ 16 -#define THC1_IRQ 17 - -#define ISH_IRQ 16 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 -#endif /* _TGL_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit.h similarity index 93% rename from src/soc/intel/tigerlake/include/soc/meminit_tgl.h rename to src/soc/intel/tigerlake/include/soc/meminit.h index 5573fb7110..2345b2b12d 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef _SOC_MEMINIT_TGL_H_ -#define _SOC_MEMINIT_TGL_H_ +#ifndef _SOC_TIGERLAKE_MEMINIT_H_ +#define _SOC_TIGERLAKE_MEMINIT_H_ #include #include @@ -66,4 +66,4 @@ void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, const struct spd_info *spd, bool half_populated); -#endif /* _SOC_MEMINIT_TGL_H_ */ +#endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h deleted file mode 100644 index 421e31d8e4..0000000000 --- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ -#define _SOC_JASPERLAKE_MEMCFG_INIT_H_ - -#include -#include - -/* Number of dq bits controlled per dqs */ -#define DQ_BITS_PER_DQS 8 - -/* Number of memory packages, where a "package" represents a 64-bit solution */ -#define DDR_NUM_PACKAGES 2 - -/* Number of DQ byte mappings */ -#define DDR_NUM_BYTE_MAPPINGS 6 - -/* Number of memory DIMM slots available on Jasper Lake */ -#define NUM_DIMM_SLOT 4 - -/* 64-bit Channel identification */ -enum { - DDR_CH0, - DDR_CH1, - DDR_NUM_CHANNELS -}; - -struct spd_by_pointer { - size_t spd_data_len; - uintptr_t spd_data_ptr; -}; - -enum mem_info_read_type { - READ_SPD_CBFS, /* Find SPD file in CBFS. */ - READ_SMBUS, /* Read on-module SPD by SMBUS. */ - READ_SPD_MEMPTR /* Find SPD data from pointer. */ -}; - -struct spd_info { - enum mem_info_read_type read_type; - union spd_data_by { - /* To read on-module SPD when read_type is READ_SMBUS. */ - uint8_t spd_smbus_address[NUM_DIMM_SLOT]; - - /* To identify SPD file when read_type is READ_SPD_CBFS. */ - int spd_index; - - /* To find SPD data when read_type is READ_SPD_MEMPTR. */ - struct spd_by_pointer spd_data_ptr_info; - } spd_spec; -}; - -/* Board-specific memory dq mapping information */ -struct mb_cfg { - - /* - * For each channel, there are 6 sets of DQ byte mappings, - * where each set has a package 0 and a package 1 value (package 0 - * represents the first 64-bit lpddr4 chip combination, and package 1 - * represents the second 64-bit lpddr4 chip combination). - * The first three sets are for CLK, CMD, and CTL. - * The fsp package actually expects 6 sets, even though the last 3 sets - * are not used in JSL. - * We let the meminit_dq_dqs_map routine take care of clearing the - * unused fields for the caller. - * Note that dq_map is only used by LPDDR; it does not need to be - * initialized for designs using DDR4. - */ - uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES]; - - /* - * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a - * mapping of a dq bit on the CPU to the bit it's connected to on - * the memory part. The array index represents the dqs bit number - * on the memory part, and the values in the array represent which - * pin on the CPU that DRAM pin connects to. - * dqs_map is only used by LPDDR; same comments apply as for dq_map - * above. - */ - uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; - - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ - uint16_t rcomp_resistor[3]; - - /* - * Rcomp target values. These will typically be the following - * values for Jasper Lake : { 80, 40, 40, 40, 30 } - */ - uint16_t rcomp_targets[5]; - - /* - * Early Command Training Enable/Disable Control - * 1 = enable, 0 = disable - */ - uint8_t ect; - - /* Board type */ - uint8_t UserBd; -}; - -/* - * Initialize default memory configurations for Jasper Lake. - */ - -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, - const struct spd_info *spd_info, bool half_populated); - -#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h index c2f497c1c8..fc4cd78646 100644 --- a/src/soc/intel/tigerlake/include/soc/pch.h +++ b/src/soc/intel/tigerlake/include/soc/pch.h @@ -17,10 +17,6 @@ #include -#define PCH_TGP 1 -#define PCH_JSP 2 -#define PCH_UNKNOWN_SERIES 0xFF - #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f7ecc3fabd..255081077a 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -89,11 +89,6 @@ #define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) -#if CONFIG(SOC_INTEL_JASPERLAKE) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) -#endif - #define PCH_DEV_SLOT_SIO3 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) @@ -130,12 +125,6 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) -#if CONFIG(SOC_INTEL_JASPERLAKE) -#define PCH_DEV_SLOT_STORAGE 0x1a -#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) -#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) -#endif - #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 10693c02a9..0c1c7a21e4 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -114,35 +114,18 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#if CONFIG(SOC_INTEL_TIGERLAKE) - - #define PMC_GPP_B 0x0 - #define PMC_GPP_T 0x1 - #define PMC_GPP_A 0x2 - #define PMC_GPP_R 0x3 - #define PMC_GPD 0x4 - #define PMC_GPP_S 0x5 - #define PMC_GPP_H 0x6 - #define PMC_GPP_D 0x7 - #define PMC_GPP_U 0x8 - #define PMC_GPP_F 0xA - #define PMC_GPP_C 0xB - #define PMC_GPP_E 0xC - -#elif CONFIG(SOC_INTEL_JASPERLAKE) - - #define PMC_GPP_A 0x0 - #define PMC_GPP_B 0x1 - #define PMC_GPP_F 0x2 - #define PMC_GPD 0x3 - #define PMC_GPP_R 0x4 - #define PMC_GPP_S 0x6 - #define PMC_GPP_D 0x7 - #define PMC_GPP_C 0x8 - #define PMC_GPP_H 0xA - #define PMC_GPP_E 0xF - -#endif +#define PMC_GPP_B 0x0 +#define PMC_GPP_T 0x1 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPD 0x4 +#define PMC_GPP_S 0x5 +#define PMC_GPP_H 0x6 +#define PMC_GPP_D 0x7 +#define PMC_GPP_U 0x8 +#define PMC_GPP_F 0xA +#define PMC_GPP_C 0xB +#define PMC_GPP_E 0xC #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) diff --git a/src/soc/intel/tigerlake/meminit_tgl.c b/src/soc/intel/tigerlake/meminit.c similarity index 99% rename from src/soc/intel/tigerlake/meminit_tgl.c rename to src/soc/intel/tigerlake/meminit.c index a0e5107998..e6cdae0a30 100644 --- a/src/soc/intel/tigerlake/meminit_tgl.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/soc/intel/tigerlake/meminit_jsl.c b/src/soc/intel/tigerlake/meminit_jsl.c deleted file mode 100644 index c68d2100fc..0000000000 --- a/src/soc/intel/tigerlake/meminit_jsl.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static void spd_read_from_cbfs(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, - size_t *spd_data_len) -{ - struct region_device spd_rdev; - size_t spd_index = spd_info->spd_spec.spd_index; - - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); - - *spd_data_len = region_device_sz(&spd_rdev); - - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); -} - -static void get_spd_data(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, - size_t *spd_data_len) -{ - if (spd_info->read_type == READ_SPD_MEMPTR) { - *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr; - *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len; - return; - } - - if (spd_info->read_type == READ_SPD_CBFS) { - spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len); - return; - } - - die("no valid way to read SPD info"); -} - -static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, - bool half_populated) -{ - memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, - sizeof(mem_cfg->RcompResistor)); - - memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, - sizeof(mem_cfg->RcompTarget)); - - memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], - sizeof(board_cfg->dq_map[DDR_CH0])); - - memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], - sizeof(board_cfg->dqs_map[DDR_CH0])); - - if (half_populated) - return; - - memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], - sizeof(board_cfg->dq_map[DDR_CH1])); - - memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], - sizeof(board_cfg->dqs_map[DDR_CH1])); -} - -static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, - uintptr_t spd_data_ptr, bool half_populated) -{ - /* Channel 0 */ - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - mem_cfg->MemorySpdPtr01 = 0; - - if (half_populated) { - printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); - spd_data_ptr = 0; - } - - /* Channel 1 */ - mem_cfg->MemorySpdPtr10 = spd_data_ptr; - mem_cfg->MemorySpdPtr11 = 0; - - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); -} - -/* Initialize onboard memory configurations for lpddr4x */ -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, - const struct spd_info *spd_info, bool half_populated) -{ - - if (spd_info->read_type == READ_SMBUS) { - for (int i = 0; i < NUM_DIMM_SLOT; i++) - mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; - - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); - } else { - uintptr_t spd_data_ptr = 0; - size_t spd_data_len = 0; - memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); - get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); - print_spd_info((unsigned char *)spd_data_ptr); - - mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); - } - - /* Early Command Training Enabled */ - mem_cfg->ECT = board_cfg->ect; - - mem_cfg->UserBd = board_cfg->UserBd; -} diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 817df541a9..5a8322b055 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -12,8 +12,7 @@ # GNU General Public License for more details. # -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c +romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += pch.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params.c similarity index 100% rename from src/soc/intel/tigerlake/romstage/fsp_params_tgl.c rename to src/soc/intel/tigerlake/romstage/fsp_params.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c deleted file mode 100644 index 39fc445b90..0000000000 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_tigerlake_config *config) -{ - unsigned int i; - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - uint32_t mask = 0; - - if (!dev || !dev->enabled) { - /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; - } - - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->SaGv = config->SaGv; - m_cfg->RMT = config->RMT; - - /* PCIe root port configuration */ - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - - m_cfg->PcieRpEnableMask = mask; - - _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >= - ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!"); - memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, - sizeof(config->PcieClkSrcUsage)); - - _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >= - ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!"); - memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, - sizeof(config->PcieClkSrcClkReq)); - - m_cfg->PrmrrSize = config->PrmrrSize; - m_cfg->EnableC6Dram = config->enable_c6dram; - - /* Disable BIOS Guard */ - m_cfg->BiosGuard = 0; - - /* Set CPU Ratio */ - m_cfg->CpuRatio = 0; - - /* Set debug interface flags */ - m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; - - /* TraceHub configuration */ - dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - if (dev && dev->enabled && config->TraceHubMode) { - m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; - m_cfg->PchTraceHubMode = config->TraceHubMode; - m_cfg->CpuTraceHubMode = config->TraceHubMode; - } - - /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - - - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; - - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; - - /* VT-d config */ - m_cfg->VtdDisable = 0; - - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; - - /* Display */ - m_cfg->DdiPortAConfig = config->DdiPortAConfig; - m_cfg->DdiPortBHpd = config->DdiPortBHpd; - m_cfg->DdiPortCHpd = config->DdiPortCHpd; - m_cfg->DdiPortBDdc = config->DdiPortBDdc; - m_cfg->DdiPortCDdc = config->DdiPortCDdc; - - /* Audio */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; - - m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; - m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; - - _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >= - ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!"); - memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, - sizeof(config->PchHdaAudioLinkDmicEnable)); - - _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >= - ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!"); - memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, - sizeof(config->PchHdaAudioLinkSspEnable)); - - _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >= - ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!"); - memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, - sizeof(config->PchHdaAudioLinkSndwEnable)); -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct soc_intel_tigerlake_config *config = config_of_soc(); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - soc_memory_init_params(m_cfg, config); - - mainboard_memory_init_params(mupd); -} - -__weak void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} From 23a82e87ee333c573796de5bd164cd21684fe58c Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 31 Mar 2020 13:32:10 -0700 Subject: [PATCH 0724/1463] security/tpm: Fix compile-time elimination for SEPARATE_VERSTAGE CB:35077 pulled TPM measurement code into the bootblock, with the catch that we'll only cache PCR extensions and not actually write them to the TPM until it gets initialized in a later stage. The goal of this was to keep the heavy TPM driver code out of the size-constrained bootblock. Unfortunately, a small mistake in the tspi_tpm_is_setup() function prevents the compiler from eliminating references to the TPM driver code in the bootblock on platforms with CONFIG_VBOOT and CONFIG_SEPARATE_VERSTAGE. In those cases vboot_logic_executed() is known at compile-time to be 0, but that still makes the final expression `return 0 || tpm_is_setup;`. We know that tpm_is_setup can never be set to 1 in the bootblock, but the compiler doesn't. This patch rewrites the logic slightly to achieve the same effect in a way that the compiler can follow (because we only really need to check tpm_is_setup in the stage that actually runs the vboot code). Signed-off-by: Julius Werner Change-Id: Idc25acf1e6c02d929639e83d529cc14af80e0870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39993 Reviewed-by: Aaron Durbin Reviewed-by: Bill XIE Reviewed-by: Werner Zeh Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- src/security/tpm/tspi/tspi.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4f0cc972a7..b94a0fb029 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -104,8 +104,18 @@ static uint32_t tpm_setup_epilogue(uint32_t result) static int tpm_is_setup; static inline int tspi_tpm_is_setup(void) { - if (CONFIG(VBOOT)) - return vboot_logic_executed() || tpm_is_setup; + /* + * vboot_logic_executed() only starts returning true at the end of + * verstage, but the vboot logic itself already wants to extend PCRs + * before that. So in the stage where verification actually runs, we + * need to check tpm_is_setup. Skip that check in all other stages so + * this whole function can be evaluated at compile time. + */ + if (CONFIG(VBOOT)) { + if (verification_should_run()) + return tpm_is_setup; + return vboot_logic_executed(); + } if (ENV_RAMSTAGE) return tpm_is_setup; From ce482849782715bd048faba89f86bfa0aee75598 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 23 Mar 2020 13:58:12 -0700 Subject: [PATCH 0725/1463] google/trogdor: Add 'Lazor' derivative This patch adds GOOGLE_LAZOR which is just a copy of GOOGLE_TROGDOR for now. Signed-off-by: Julius Werner Change-Id: I0dca8e1c29bdd91625d58b3cb583b530ed925e9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39784 Tested-by: build bot (Jenkins) Reviewed-by: Bob Moragues Reviewed-by: Philip Chen --- src/mainboard/google/trogdor/Kconfig | 1 + src/mainboard/google/trogdor/Kconfig.name | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 27bd023169..d1dbfe0d99 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -42,5 +42,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS config MAINBOARD_PART_NUMBER string default "Trogdor" if BOARD_GOOGLE_TROGDOR + default "Lazor" if BOARD_GOOGLE_LAZOR endif # BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index 425c9bfa95..66636a6ea1 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -2,3 +2,7 @@ config BOARD_GOOGLE_TROGDOR bool "Trogdor" select BOARD_GOOGLE_TROGDOR_COMMON + +config BOARD_GOOGLE_LAZOR + bool "Lazor" + select BOARD_GOOGLE_TROGDOR_COMMON From da1b088885b12e5b20afd5dd99e31acf3c41965b Mon Sep 17 00:00:00 2001 From: William Wei Date: Thu, 26 Mar 2020 14:18:53 +0800 Subject: [PATCH 0726/1463] mb/google/volteer: Create Malefor variant This commit creates a malefor variant for Volteer. The initial settings override the baseboard was copied from variant ripto. Fine tune GPIO and memory DQ based on malefor schematics. BUG=b:150653745 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: William Wei Change-Id: Idbeebb13e537287686344740211143df35b7863a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39857 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 2 + src/mainboard/google/volteer/Kconfig.name | 4 + .../volteer/variants/malefor/Makefile.inc | 11 + .../google/volteer/variants/malefor/gpio.c | 402 ++++++++++++++++++ .../variants/malefor/include/variant/ec.h | 9 + .../variants/malefor/include/variant/gpio.h | 11 + .../google/volteer/variants/malefor/memory.c | 40 ++ .../volteer/variants/malefor/overridetree.cb | 6 + 8 files changed, 485 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/malefor/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/malefor/gpio.c create mode 100644 src/mainboard/google/volteer/variants/malefor/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/malefor/include/variant/gpio.h create mode 100644 src/mainboard/google/volteer/variants/malefor/memory.c create mode 100644 src/mainboard/google/volteer/variants/malefor/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 54a8fecb4c..0870c61ecb 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -56,6 +56,7 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string default "Halvor" if BOARD_GOOGLE_HALVOR + default "Malefor" if BOARD_GOOGLE_MALEFOR default "Ripto" if BOARD_GOOGLE_RIPTO default "Volteer" if BOARD_GOOGLE_VOLTEER @@ -70,6 +71,7 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR string default "halvor" if BOARD_GOOGLE_HALVOR + default "malefor" if BOARD_GOOGLE_MALEFOR default "ripto" if BOARD_GOOGLE_RIPTO default "volteer" if BOARD_GOOGLE_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 596894effb..62aabb1858 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -4,6 +4,10 @@ config BOARD_GOOGLE_HALVOR bool "-> Halvor" select BOARD_GOOGLE_BASEBOARD_VOLTEER +config BOARD_GOOGLE_MALEFOR + bool "-> Malefor" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + config BOARD_GOOGLE_RIPTO bool "-> Ripto" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/malefor/Makefile.inc b/src/mainboard/google/volteer/variants/malefor/Makefile.inc new file mode 100644 index 0000000000..8a7cbec383 --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +## Memory Options +SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c new file mode 100644 index 0000000000..71a03e60dc --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -0,0 +1,402 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> NOT USED */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : ISH_I2C0_CVF_SDA ==> NOT USED*/ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_CVF_SCL ==> NOT USED*/ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> NOT USED */ + PAD_NC(GPP_B7, NONE), + /* B8 : ISH_I2C1_SCL ==> NOT USED */ + PAD_NC(GPP_B8, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> NOT USED */ + PAD_NC(GPP_C1, NONE), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT), + /* C7 : SML1DATA ==> EN_PP5000_PEN */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> NOT USED */ + PAD_NC(GPP_C11, NONE), + /* C12 : UART1_RXD ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> NOT USED */ + PAD_NC(GPP_C13, NONE), + /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> NOT USED */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> NOT USED */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NOT USED */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NOT USED */ + PAD_NC(GPP_D3, NONE), + /* D4 : IMGCLKOUT0 ==> NOT USED */ + PAD_NC(GPP_D4, NONE), + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> NOT USED */ + PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> NOT USED */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_NC(GPP_D10, NONE), + /* D11 : ISH_SPI_MISO ==> NOT USED */ + PAD_NC(GPP_D11, NONE), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_NC(GPP_D12, NONE), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> NOT USED */ + PAD_NC(GPP_D18, NONE), + /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> NOT USED */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NOT USED */ + PAD_NC(GPP_E17, NONE), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT), + /* F9 : Reserved ==> NC */ + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NOT USED */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NOT USED */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> NOT USED */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NOT USED */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NOT USED */ + PAD_NC(GPP_F16, NONE), + /* F17 : NOT USED */ + PAD_NC(GPP_F17, NONE), + /* F18 : THC1_SPI2_INT# ==> NOT USED */ + PAD_NC(GPP_F18, NONE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C3_SDA ==> NOT USED */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NOT USED */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> NOT USED */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> NOT USED */ + PAD_NC(GPP_H13, NONE), + /* H14 : M2_SKT2_CFG2 # ==> NOT SUED */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NOT USED */ + PAD_NC(GPP_H15, NONE), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + /* H21 : IMGCLKOUT2 ==> NOT USED */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NOT USED */ + PAD_NC(GPP_H22, NONE), + /* H23 : IMGCLKOUT4 ==> NOT USED */ + PAD_NC(GPP_H23, NONE), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> HDA_RST_L */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> NOT USED */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NOT USED */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/malefor/include/variant/ec.h b/src/mainboard/google/volteer/variants/malefor/include/variant/ec.h new file mode 100644 index 0000000000..33e79711f6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/include/variant/ec.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/malefor/include/variant/gpio.h b/src/mainboard/google/volteer/variants/malefor/include/variant/gpio.h new file mode 100644 index 0000000000..55725ad59a --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c new file mode 100644 index 0000000000..75ac762a47 --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +static const struct mb_lpddr4x_cfg malefor_memcfg = { + /* DQ byte map */ + .dq_map = { + { 3, 1, 0, 2, 4, 6, 7, 5, /* Byte 0 */ + 12, 13, 14, 15, 8, 9, 10, 11 }, /* Byte 1 */ + { 0, 7, 1, 6, 2, 4, 3, 5, /* Byte 2 */ + 8, 15, 14, 9, 13, 10, 12, 11 }, /* Byte 3 */ + { 3, 2, 0, 1, 4, 5, 6, 7, /* Byte 4 */ + 12, 13, 15, 14, 8, 9, 10, 11 }, /* Byte 5 */ + { 6, 0, 1, 7, 5, 4, 2, 3, /* Byte 6 */ + 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ + { 5, 0, 1, 3, 4, 2, 7, 6, /* Byte 0 */ + 11, 14, 13, 12, 8, 9, 15, 10 }, /* Byte 1 */ + { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ + 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ + { 3, 2, 1, 0, 5, 4, 7, 6, /* Byte 4 */ + 12, 13, 15, 14, 8, 11, 9, 10 }, /* Byte 5 */ + { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ + 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + + .ect = 0, /* Disable Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *variant_memory_params(void) +{ + return &malefor_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end From 5646a648dfc7fcc53ff4dc86ddbc40620ee4a86c Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 19 Jan 2020 16:12:25 -0700 Subject: [PATCH 0727/1463] soc/amd/common/psp: Make common function to print status Consolidate commands' printing of status into one static function. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Id8abe0d1d4ac87f6d4f625593f47bf484729906f Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/2020363 Reviewed-by: Raul E Rangel Reviewed-by: Eric Peers Tested-by: Eric Peers Reviewed-on: https://review.coreboot.org/c/coreboot/+/39998 Reviewed-by: Raul Rangel Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/psp/psp.c | 36 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index cf25fd1b51..0294422c3d 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -225,6 +225,21 @@ static int send_psp_command(u32 command, void *buffer) return 0; } +/* + * Print meaningful status to the console. Caller only passes a pointer to a + * buffer if it's expected to contain its own status. + */ +static void print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer) +{ + if (buffer && rd_resp_sts(buffer)) + printk(BIOS_DEBUG, "buffer status=0x%x ", rd_resp_sts(buffer)); + + if (cmd_status) + printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); + else + printk(BIOS_DEBUG, "OK\n"); +} + /* * Notify the PSP that DRAM is present. Upon receiving this command, the PSP * will load its OS into fenced DRAM that is not accessible to the x86 cores. @@ -243,13 +258,7 @@ int psp_notify_dram(void) cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); /* buffer's status shouldn't change but report it if it does */ - if (rd_resp_sts(&buffer)) - printk(BIOS_DEBUG, "buffer status=0x%x ", - rd_resp_sts(&buffer)); - if (cmd_status) - printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); - else - printk(BIOS_DEBUG, "OK\n"); + print_cmd_status(cmd_status, &buffer); return cmd_status; } @@ -273,13 +282,7 @@ static void psp_notify_boot_done(void *unused) cmd_status = send_psp_command(MBOX_BIOS_CMD_BOOT_DONE, &buffer); /* buffer's status shouldn't change but report it if it does */ - if (rd_resp_sts(&buffer)) - printk(BIOS_DEBUG, "buffer status=0x%x ", - rd_resp_sts(&buffer)); - if (cmd_status) - printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); - else - printk(BIOS_DEBUG, "OK\n"); + print_cmd_status(cmd_status, &buffer); } /* @@ -305,10 +308,7 @@ static int psp_load_blob(int type, void *addr) /* Blob commands use the buffer registers as data, not pointer to buf */ cmd_status = send_psp_command(type, addr); - if (cmd_status) - printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); - else - printk(BIOS_DEBUG, "OK\n"); + print_cmd_status(cmd_status, NULL); return cmd_status; } From 737e56aa56e5dce6c682580f8e89b80a0119107f Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 19 Jan 2020 16:32:08 -0700 Subject: [PATCH 0728/1463] soc/amd/common/psp: Consolidate FW blob load functions The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands. Consolidate the two functions used for interpreting the command and applying the command into a single one. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers Reviewed-by: Raul E Rangel Tested-by: Eric Peers Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Raul Rangel --- .../amd/common/block/include/amdblocks/psp.h | 7 +- src/soc/amd/common/block/psp/psp.c | 65 +++++++++---------- src/soc/amd/stoneyridge/chip.c | 2 +- src/soc/amd/stoneyridge/romstage.c | 2 +- 4 files changed, 40 insertions(+), 36 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index b730293bb5..494f1744f0 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -115,6 +115,11 @@ int psp_notify_dram(void); * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. * name: cbfs file name */ -int psp_load_named_blob(int type, const char *name); +enum psp_blob_type { + BLOB_SMU_FW, + BLOB_SMU_FW2, +}; + +int psp_load_named_blob(enum psp_blob_type type, const char *name); #endif /* __AMD_PSP_H__ */ diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 0294422c3d..9c053c2c39 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -288,53 +288,52 @@ static void psp_notify_boot_done(void *unused) /* * Tell the PSP to load a firmware blob from a location in the BIOS image. */ -static int psp_load_blob(int type, void *addr) +int psp_load_named_blob(enum psp_blob_type type, const char *name) { int cmd_status; - - if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { - printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); - return PSPSTS_UNSUPPORTED; - } - - /* only two types currently supported */ - if (type != MBOX_BIOS_CMD_SMU_FW && type != MBOX_BIOS_CMD_SMU_FW2) { - printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); - return PSPSTS_INVALID_BLOB; - } - - printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, addr); - - /* Blob commands use the buffer registers as data, not pointer to buf */ - cmd_status = send_psp_command(type, addr); - - print_cmd_status(cmd_status, NULL); - - return cmd_status; -} - -int psp_load_named_blob(int type, const char *name) -{ + u32 command; void *blob; struct cbfsf cbfs_file; struct region_device rdev; - int r; + + switch (type) { + case BLOB_SMU_FW: + command = MBOX_BIOS_CMD_SMU_FW; + break; + case BLOB_SMU_FW2: + command = MBOX_BIOS_CMD_SMU_FW2; + break; + default: + printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); + return -PSPSTS_INVALID_BLOB; + } + + /* type can only be BLOB_SMU_FW or BLOB_SMU_FW2 here, so don't re-check for this */ + if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { + printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); + return -PSPSTS_UNSUPPORTED; + } if (cbfs_boot_locate(&cbfs_file, name, NULL)) { printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; } cbfs_file_data(&rdev, &cbfs_file); blob = rdev_mmap_full(&rdev); - if (blob) { - r = psp_load_blob(type, blob); - rdev_munmap(&rdev, blob); - } else { + if (!blob) { printk(BIOS_ERR, "BUG: Cannot map blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; } - return r; + + printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, blob); + + /* Blob commands use the buffer registers as data, not pointer to buf */ + cmd_status = send_psp_command(command, blob); + print_cmd_status(cmd_status, NULL); + + rdev_munmap(&rdev, blob); + return cmd_status; } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index aa3c322813..f08c12f32f 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -160,7 +160,7 @@ static void earliest_ramstage(void *unused) if (!s3_resume) { post_code(0x46); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); + psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); post_code(0x47); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0a209b0260..efe75b72e3 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -61,7 +61,7 @@ static void load_smu_fw1(void) cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); + psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); } static void agesa_call(void) From dba3229b90c7762e9f101cdcd036ca48c76f56bf Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 31 Mar 2020 23:54:44 +0200 Subject: [PATCH 0729/1463] soc/amd/common/psp: Move early init to soc The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Raul Rangel Reviewed-by: Paul Menzel --- .../amd/common/block/include/amdblocks/psp.h | 20 +---- src/soc/amd/common/block/psp/Makefile.inc | 1 + src/soc/amd/common/block/psp/psp.c | 86 +------------------ src/soc/amd/stoneyridge/Makefile.inc | 3 + .../amd/stoneyridge/include/soc/southbridge.h | 7 ++ src/soc/amd/stoneyridge/psp.c | 58 +++++++++++++ src/soc/amd/stoneyridge/romstage.c | 26 +----- 7 files changed, 75 insertions(+), 126 deletions(-) create mode 100644 src/soc/amd/stoneyridge/psp.c diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 494f1744f0..42c802d51b 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -15,24 +15,8 @@ #ifndef __AMD_PSP_H__ #define __AMD_PSP_H__ -#include -#include -#include - -/* Extra, Special Purpose Registers in the PSP PCI Config Space */ - -/* PSP Mirror Features Capabilities and Control Register */ -#define PSP_PCI_MIRRORCTRL1_REG 0x44 /* PSP Mirror Ctrl Reg */ -#define PMNXTPTRW_MASK 0xff /* PCI AFCR pointer mask */ -#define PMNXTPTRW_EXPOSE 0xa4 /* Pointer to expose the AFCR */ - -#define PSP_PCI_EXT_HDR_CTRL 0x48 /* Extra PCI Header Ctrl */ -#define MAGIC_ENABLES 0x34 /* Extra PCI HDR Ctl Enables */ - -#define PSP_MAILBOX_BASE 0x70 /* Mailbox offset from PCIe BAR */ - -#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ -#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ +/* Get the mailbox base address - specific to family of device. */ +struct psp_mbox *soc_get_mbox_address(void); /* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index d5f93869c8..2f5de1df9c 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 9c053c2c39..7ec8d7b0c9 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -33,73 +33,6 @@ static const char *psp_status_init_timeout = "error: PSP init timeout"; static const char *psp_status_cmd_timeout = "error: PSP command timeout"; static const char *psp_status_noerror = ""; -static void psp_bar_init_early(void) -{ - u32 psp_mmio_size; - u32 value32; - u32 base, limit; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: SOC_PSP_DEV device not found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return; - } - - /* Check if PSP BAR has been assigned, and if so, just return */ - if (pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK) - return; - - /* Otherwise, do an early init of the BAR */ - pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4, 0xffffffff); - psp_mmio_size = ~pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) + 1; - printk(BIOS_SPEW, "PSP: BAR size is 0x%x\n", psp_mmio_size); - /* Assign BAR to an initial temporarily defined region */ - pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4, - PSP_MAILBOX_BAR3_BASE); - - /* Route MMIO through the northbridge */ - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, - (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); - limit = ((PSP_MAILBOX_BAR3_BASE + psp_mmio_size - 1) >> 8) & ~0xff; - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(7), limit); - base = (PSP_MAILBOX_BAR3_BASE >> 8) | MMIO_WE | MMIO_RE; - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(7), base); - pci_write_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL, MAGIC_ENABLES); - - /* Update the capability chain */ - value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG); - value32 &= ~PMNXTPTRW_MASK; - value32 |= PMNXTPTRW_EXPOSE; - pci_write_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG, value32); -} - -static uintptr_t get_psp_bar3_addr(void) -{ - uintptr_t psp_mmio; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return 0; - } - - /* D8F0x48[12] is the Bar3Hide flag, check it */ - if (pci_read_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL) & BAR3HIDE) { - psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; - if (psp_mmio == 0xffffffff) { - printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n"); - return 0; - } - return psp_mmio; - } else { - return pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - } -} - static const char *status_to_string(int err) { switch (err) { @@ -120,23 +53,6 @@ static const char *status_to_string(int err) } } -static struct psp_mbox *get_mbox_address(void) -{ - uintptr_t baseptr; - - baseptr = get_psp_bar3_addr(); - if (baseptr == 0) { - psp_bar_init_early(); - baseptr = get_psp_bar3_addr(); - if (baseptr == 0) { - printk(BIOS_WARNING, "PSP: %s(), psp_bar_init_early() failed...\n", - __func__); - return NULL; - } - } - return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE); -} - static u32 rd_mbox_sts(struct psp_mbox *mbox) { return read32(&mbox->mbox_status); @@ -192,7 +108,7 @@ static int wait_command(struct psp_mbox *mbox) static int send_psp_command(u32 command, void *buffer) { - struct psp_mbox *mbox = get_mbox_address(); + struct psp_mbox *mbox = soc_get_mbox_address(); if (!mbox) return -PSPSTS_NOBASE; diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 96b8303a1c..50e53c4c35 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -59,6 +59,7 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += psp.c verstage-y += gpio.c verstage-y += i2c.c @@ -93,6 +94,7 @@ ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c +ramstage-y += psp.c all-y += reset.c @@ -102,6 +104,7 @@ smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c +smm-y += psp.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 45bad1fb55..7384951063 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -290,10 +290,17 @@ #define SPI_RD4DW_EN_HOST BIT(15) /* Platform Security Processor D8F0 */ +void soc_enable_psp_early(void); + #define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ +#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */ + #define PSP_BAR_ENABLES 0x48 #define PSP_MAILBOX_BAR_EN 0x10 +#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ +#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ + /* IO 0xcf9 - Reset control port*/ #define FULL_RST BIT(3) #define RST_CMD BIT(2) diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c new file mode 100644 index 0000000000..bc2d725145 --- /dev/null +++ b/src/soc/amd/stoneyridge/psp.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void soc_enable_psp_early(void) +{ + u32 base, limit, cmd; + + /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ + base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; + limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); + + /* Preload a value into BAR and enable it */ + pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); + pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); + + /* Enable memory access and master */ + cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); +}; + +struct psp_mbox *soc_get_mbox_address(void) +{ + uintptr_t psp_mmio; + + /* Check for presence of the PSP */ + if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { + printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", + PSP_DEV, PSP_FUNC); + return 0; + } + + /* Determine if Bar3Hide has been set, and if hidden get the base from + * the MSR instead. */ + if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { + psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; + if (psp_mmio == 0xffffffff) { + printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n"); + return 0; + } + } else { + psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } + + return (struct psp_mbox *)(psp_mmio + PSP_MAILBOX_OFFSET); +} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index efe75b72e3..fab9a83e04 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -42,28 +43,6 @@ void __weak mainboard_romstage_entry_s3(int s3_resume) /* By default, don't do anything */ } -static void load_smu_fw1(void) -{ - u32 base, limit, cmd; - - /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ - base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); - - /* Preload a value into "BAR3" and enable it */ - pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); - pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); - - /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - - psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); -} - static void agesa_call(void) { post_code(0x37); @@ -92,8 +71,9 @@ asmlinkage void car_stage_entry(void) console_init(); + soc_enable_psp_early(); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - load_smu_fw1(); + psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); From 3c57819005af59064ea0397e8b1ed59fab5a8f7c Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 19 Jan 2020 17:16:01 -0700 Subject: [PATCH 0730/1463] soc/amd/common/psp: Move definitions into a private file Declutter psp.h by removing internal details the caller doesn't need to know. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: I2fb0ed1d2697c313fb8475e3f00482899e729130 Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/2020366 Tested-by: Eric Peers Reviewed-by: Eric Peers Reviewed-on: https://review.coreboot.org/c/coreboot/+/40015 Reviewed-by: Raul Rangel Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../amd/common/block/include/amdblocks/psp.h | 63 +--------------- src/soc/amd/common/block/psp/psp.c | 1 + src/soc/amd/common/block/psp/psp_def.h | 73 +++++++++++++++++++ 3 files changed, 75 insertions(+), 62 deletions(-) create mode 100644 src/soc/amd/common/block/psp/psp_def.h diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 42c802d51b..d7f6169411 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -18,63 +18,7 @@ /* Get the mailbox base address - specific to family of device. */ struct psp_mbox *soc_get_mbox_address(void); -/* x86 to PSP commands */ -#define MBOX_BIOS_CMD_DRAM_INFO 0x01 -#define MBOX_BIOS_CMD_SMM_INFO 0x02 -#define MBOX_BIOS_CMD_SX_INFO 0x03 -#define MBOX_BIOS_CMD_RSM_INFO 0x04 -#define MBOX_BIOS_CMD_PSP_QUERY 0x05 -#define MBOX_BIOS_CMD_BOOT_DONE 0x06 -#define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 -#define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 -#define MBOX_BIOS_CMD_NOP 0x09 -#define MBOX_BIOS_CMD_SMU_FW 0x19 -#define MBOX_BIOS_CMD_SMU_FW2 0x1a -#define MBOX_BIOS_CMD_ABORT 0xfe - -/* generic PSP interface status */ -#define STATUS_INITIALIZED 0x1 -#define STATUS_ERROR 0x2 -#define STATUS_TERMINATED 0x4 -#define STATUS_HALT 0x8 -#define STATUS_RECOVERY 0x10 - -/* psp_mbox consists of hardware registers beginning at PSPx000070 - * mbox_command: BIOS->PSP command, cleared by PSP when complete - * mbox_status: BIOS->PSP interface status - * cmd_response: pointer to command/response buffer - */ -struct psp_mbox { - u32 mbox_command; - u32 mbox_status; - u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ -} __packed; - -/* command/response format, BIOS builds this in memory - * mbox_buffer_header: generic header - * mbox_buffer: command-specific buffer format - * - * AMD reference code aligns and pads all buffers to 32 bytes. - */ -struct mbox_buffer_header { - u32 size; /* total size of buffer */ - u32 status; /* command status, filled by PSP if applicable */ -} __packed; - -/* - * command-specific buffer definitions: see NDA document #54267 - * The following commands need a buffer definition if they are to be used. - * All other commands will work with the default buffer. - * MBOX_BIOS_CMD_SMM_INFO MBOX_BIOS_CMD_PSP_QUERY - * MBOX_BIOS_CMD_SX_INFO MBOX_BIOS_CMD_S3_DATA_INFO - * MBOX_BIOS_CMD_RSM_INFO - */ - -struct mbox_default_buffer { /* command-response buffer unused by command */ - struct mbox_buffer_header header; -} __attribute__((packed, aligned(32))); - -/* send_psp_command() error codes */ +/* BIOS-to-PSP functions return 0 if successful, else negative value */ #define PSPSTS_SUCCESS 0 #define PSPSTS_NOBASE 1 #define PSPSTS_HALTED 2 @@ -87,11 +31,6 @@ struct mbox_default_buffer { /* command-response buffer unused by command */ #define PSPSTS_INVALID_NAME 8 #define PSPSTS_INVALID_BLOB 9 -#define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ -#define PSP_CMD_TIMEOUT 1000 /* 1 second */ - -/* BIOS-to-PSP functions return 0 if successful, else negative value */ - int psp_notify_dram(void); /* diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 7ec8d7b0c9..c580803829 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -24,6 +24,7 @@ #include #include #include +#include "psp_def.h" static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; static const char *psp_status_halted = "error: PSP in halted state"; diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h new file mode 100644 index 0000000000..4b3ca6a352 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMD_PSP_DEF_H__ +#define __AMD_PSP_DEF_H__ + +#include + +/* x86 to PSP commands */ +#define MBOX_BIOS_CMD_DRAM_INFO 0x01 +#define MBOX_BIOS_CMD_SMM_INFO 0x02 +#define MBOX_BIOS_CMD_SX_INFO 0x03 +#define MBOX_BIOS_CMD_RSM_INFO 0x04 +#define MBOX_BIOS_CMD_PSP_QUERY 0x05 +#define MBOX_BIOS_CMD_BOOT_DONE 0x06 +#define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 +#define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 +#define MBOX_BIOS_CMD_NOP 0x09 +#define MBOX_BIOS_CMD_SMU_FW 0x19 +#define MBOX_BIOS_CMD_SMU_FW2 0x1a +#define MBOX_BIOS_CMD_ABORT 0xfe + +/* generic PSP interface status */ +#define STATUS_INITIALIZED 0x1 +#define STATUS_ERROR 0x2 +#define STATUS_TERMINATED 0x4 +#define STATUS_HALT 0x8 +#define STATUS_RECOVERY 0x10 + +/* psp_mbox consists of hardware registers beginning at PSPx000070 + * mbox_command: BIOS->PSP command, cleared by PSP when complete + * mbox_status: BIOS->PSP interface status + * cmd_response: pointer to command/response buffer + */ +struct psp_mbox { + u32 mbox_command; + u32 mbox_status; + u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ +} __packed; + +/* command/response format, BIOS builds this in memory + * mbox_buffer_header: generic header + * mbox_buffer: command-specific buffer format + * + * AMD reference code aligns and pads all buffers to 32 bytes. + */ +struct mbox_buffer_header { + u32 size; /* total size of buffer */ + u32 status; /* command status, filled by PSP if applicable */ +} __packed; + +/* + * command-specific buffer definitions: see NDA document #54267 + * The following commands need a buffer definition if they are to be used. + * All other commands will work with the default buffer. + * MBOX_BIOS_CMD_SMM_INFO MBOX_BIOS_CMD_PSP_QUERY + * MBOX_BIOS_CMD_SX_INFO MBOX_BIOS_CMD_S3_DATA_INFO + * MBOX_BIOS_CMD_RSM_INFO + */ + +struct mbox_default_buffer { /* command-response buffer unused by command */ + struct mbox_buffer_header header; +} __attribute__((packed, aligned(32))); + +struct mbox_cmd_sx_info_buffer { + struct mbox_buffer_header header; + u8 sleep_type; +} __attribute__((packed, aligned(32))); + +#define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ +#define PSP_CMD_TIMEOUT 1000 /* 1 second */ + +#endif /* __AMD_PSP_DEF_H__ */ From 5b1f335ef8aed95e01f040bc7074fb00acc8ab7e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 26 Mar 2020 15:36:19 -0700 Subject: [PATCH 0731/1463] soc/intel/tigerlake: Reorganize memory initialization support This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added. 1. It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. 2. spd_info structure is organized to allow mixed topologies as well. 3. DQ/DQS maps are organized to reflect hardware configuration. TEST=Verified that volteer still boots and memory initialization is successful. Signed-off-by: Furquan Shaikh Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/volteer/romstage.c | 9 +- .../baseboard/include/baseboard/variants.h | 2 +- .../volteer/variants/baseboard/memory.c | 65 ++-- .../google/volteer/variants/malefor/memory.c | 63 ++- .../intel/tglrvp/romstage_fsp_params.c | 9 +- .../baseboard/include/baseboard/variants.h | 2 +- .../intel/tglrvp/variants/tglrvp_up3/memory.c | 63 ++- .../intel/tglrvp/variants/tglrvp_up4/memory.c | 63 ++- src/soc/intel/tigerlake/include/soc/meminit.h | 80 ++-- src/soc/intel/tigerlake/meminit.c | 361 ++++++++++++------ 10 files changed, 473 insertions(+), 244 deletions(-) diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 46c5fecd1e..3e602e6139 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -17,12 +17,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct mb_lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct lpddr4x_cfg *board_cfg = variant_memory_params(); const struct spd_info spd_info = { - .read_type = READ_SPD_CBFS, - .spd_spec.spd_index = variant_memory_sku(), + .topology = MEMORY_DOWN, + .md_spd_loc = SPD_CBFS, + .cbfs_index = variant_memory_sku(), }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - meminit_lpddr4x_dimm0(mem_cfg, board_cfg, &spd_info, half_populated); + meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index d5bc63a08c..a7169fe8c9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -23,7 +23,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct mb_lpddr4x_cfg *variant_memory_params(void); +const struct lpddr4x_cfg *variant_memory_params(void); int variant_memory_sku(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index db2946dd33..f2c5a5a146 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -9,38 +9,59 @@ #include #include -static const struct mb_lpddr4x_cfg baseboard_memcfg = { - /* DQ byte map */ +static const struct lpddr4x_cfg baseboard_memcfg = { + /* DQ CPU<>DRAM map */ .dq_map = { - { 0, 1, 2, 3, 4, 5, 6, 7, /* Byte 0 */ - 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ - { 7, 2, 6, 3, 5, 1, 4, 0, /* Byte 2 */ - 10, 8, 9, 11, 15, 12, 14, 13 }, /* Byte 3 */ - { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 4 */ - 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 5 */ - { 7, 0, 1, 6, 5, 4, 2, 3, /* Byte 6 */ - 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ - { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 0 */ - 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ - { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ - 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ - { 3, 2, 1, 0, 7, 4, 5, 6, /* Byte 4 */ - 15, 14, 13, 12, 8, 9, 10, 11 }, /* Byte 5 */ - { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ - 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + [0] = { + { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ }, .ect = 0, /* Disable Early Command Training */ }; -const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +const struct lpddr4x_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 75ac762a47..4e5313db36 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -3,38 +3,59 @@ #include -static const struct mb_lpddr4x_cfg malefor_memcfg = { +static const struct lpddr4x_cfg malefor_memcfg = { /* DQ byte map */ .dq_map = { - { 3, 1, 0, 2, 4, 6, 7, 5, /* Byte 0 */ - 12, 13, 14, 15, 8, 9, 10, 11 }, /* Byte 1 */ - { 0, 7, 1, 6, 2, 4, 3, 5, /* Byte 2 */ - 8, 15, 14, 9, 13, 10, 12, 11 }, /* Byte 3 */ - { 3, 2, 0, 1, 4, 5, 6, 7, /* Byte 4 */ - 12, 13, 15, 14, 8, 9, 10, 11 }, /* Byte 5 */ - { 6, 0, 1, 7, 5, 4, 2, 3, /* Byte 6 */ - 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ - { 5, 0, 1, 3, 4, 2, 7, 6, /* Byte 0 */ - 11, 14, 13, 12, 8, 9, 15, 10 }, /* Byte 1 */ - { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ - 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ - { 3, 2, 1, 0, 5, 4, 7, 6, /* Byte 4 */ - 12, 13, 15, 14, 8, 11, 9, 10 }, /* Byte 5 */ - { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ - 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ }, .ect = 0, /* Disable Early Command Training */ }; -const struct mb_lpddr4x_cfg *variant_memory_params(void) +const struct lpddr4x_cfg *variant_memory_params(void) { return &malefor_memcfg; } diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 0af394494f..d8057f6564 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -56,13 +56,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct mb_lpddr4x_cfg *mem_config = variant_memory_params(); + const struct lpddr4x_cfg *mem_config = variant_memory_params(); const struct spd_info spd_info = { - .read_type = READ_SPD_CBFS, - .spd_spec.spd_index = mainboard_get_spd_index(), + .topology = MEMORY_DOWN, + .md_spd_loc = SPD_CBFS, + .cbfs_index = mainboard_get_spd_index(), }; bool half_populated = false; - meminit_lpddr4x_dimm0(mem_cfg, mem_config, &spd_info, half_populated); + meminit_lpddr4x(mem_cfg, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index b7b69f29fd..b38daff853 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -28,6 +28,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); size_t variant_memory_sku(void); -const struct mb_lpddr4x_cfg *variant_memory_params(void); +const struct lpddr4x_cfg *variant_memory_params(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index 1cb0df52df..ad2f24f9c1 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -21,38 +21,59 @@ size_t __weak variant_memory_sku(void) return 0; } -static const struct mb_lpddr4x_cfg mem_config = { +static const struct lpddr4x_cfg mem_config = { /* DQ byte map */ .dq_map = { - { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ - 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ - { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ - 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ - { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ - 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ - { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ - 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ - { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ - 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ - { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ - 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ - { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ - 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ - { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ - 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + [0] = { + { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */ + { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */ + }, + [1] = { + { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */ + { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */ + { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */ + { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */ + { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */ + { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */ + { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */ + { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, - { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ }, .ect = 1, /* Early Command Training */ }; -const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +const struct lpddr4x_cfg *__weak variant_memory_params(void) { return &mem_config; } diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index 651550c753..929d0cca89 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -21,38 +21,59 @@ size_t __weak variant_memory_sku(void) return 0; } -static const struct mb_lpddr4x_cfg mem_config = { +static const struct lpddr4x_cfg mem_config = { /* DQ byte map */ .dq_map = { - { 8, 9, 12, 11, 13, 15, 10, 14, /* Byte 0 */ - 4, 6, 0, 2, 5, 7, 1, 3 }, /* Byte 1 */ - { 2, 3, 0, 6, 1, 7, 5, 4, /* Byte 2 */ - 15, 14, 13, 8, 12, 11, 9, 10 }, /* Byte 3 */ - { 1, 0, 3, 2, 5, 4, 7, 6, /* Byte 4 */ - 14, 15, 12, 13, 8, 10, 9, 11 }, /* Byte 5 */ - { 8, 10, 11, 9, 15, 12, 14, 13, /* Byte 6 */ - 4, 7, 6, 5, 2, 0, 1, 3 }, /* Byte 7 */ - { 8, 9, 10, 11, 13, 12, 15, 14, /* Byte 0 */ - 7, 6, 4, 5, 0, 2, 1, 3 }, /* Byte 1 */ - { 1, 3, 0, 2, 6, 4, 5, 7, /* Byte 2 */ - 14, 15, 10, 12, 8, 13, 11, 9 }, /* Byte 3 */ - { 1, 0, 2, 4, 5, 3, 7, 6, /* Byte 4 */ - 12, 14, 15, 13, 9, 10, 8, 11 }, /* Byte 5 */ - { 11, 9, 8, 13, 12, 14, 15, 10, /* Byte 6 */ - 4, 7, 5, 1, 2, 6, 3, 0 } /* Byte 7 */ + [0] = { + { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, - { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ }, .ect = 1, /* Early Command Training */ }; -const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +const struct lpddr4x_cfg *__weak variant_memory_params(void) { return &mem_config; } diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 2345b2b12d..aab155e43c 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -12,46 +12,65 @@ #include #include -#define BYTES_PER_CHANNEL 2 -#define BITS_PER_BYTE 8 -#define DQS_PER_CHANNEL 2 -#define NUM_CHANNELS 8 +#define BITS_PER_BYTE 8 -struct spd_by_pointer { - size_t spd_data_len; - uintptr_t spd_data_ptr; +#define LPDDR4X_CHANNELS 8 +#define LPDDR4X_BYTES_PER_CHANNEL 2 + +enum mem_topology { + MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */ }; -enum mem_info_read_type { - NOT_EXISTING, /* No memory in this channel */ - READ_SPD_CBFS, /* Find spd file in CBFS. */ - READ_SPD_MEMPTR /* Find spd data from pointer. */ +enum md_spd_loc { + /* Read SPD from pointer provided to memory location. */ + SPD_MEMPTR, + /* Read SPD using index into spd.bin in CBFS. */ + SPD_CBFS, }; struct spd_info { - enum mem_info_read_type read_type; - union spd_data_by { - /* To identify spd file when read_type is READ_SPD_CBFS. */ - int spd_index; + enum mem_topology topology; - /* To find spd data when read_type is READ_SPD_MEMPTR. */ - struct spd_by_pointer spd_data_ptr_info; - } spd_spec; + /* SPD info for Memory down topology */ + enum md_spd_loc md_spd_loc; + union { + /* Used for SPD_CBFS */ + uint8_t cbfs_index; + + struct { + /* Used for SPD_MEMPTR */ + uintptr_t data_ptr; + size_t data_len; + }; + }; }; /* Board-specific memory configuration information */ -struct mb_lpddr4x_cfg { - /* DQ mapping */ - uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; +struct lpddr4x_cfg { + /* + * DQ CPU<>DRAM map: + * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits(1 + * byte). Thus, dq_map is represented as DDR[7-0]_DQ[1-0][7:0], where + * DDR[7-0] : LPDDR4x channel # + * DQ[1-0] : DQ # within the channel + * [7:0] : Bits within the DQ + * + * Index of the array represents DQ pin# on the CPU, whereas value in + * the array represents DQ pin# on the memory part. + */ + uint8_t dq_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL][BITS_PER_BYTE]; /* - * DQS CPU<>DRAM map. Each array entry represents a - * mapping of a dq bit on the CPU to the bit it's connected to on - * the memory part. The array index represents the dqs bit number - * on the memory part, and the values in the array represent which - * pin on the CPU that DRAM pin connects to. + * DQS CPU<>DRAM map: + * LPDDR4x memory interface has 2 DQS pairs(P/N) per channel. Thus, dqs_map is + * represented as DDR[7-0]_DQS[1:0], where + * DDR[7-0] : LPDDR4x channel # + * DQS[1-0] : DQS # within the channel + * + * Index of the array represents DQS pin# on the CPU, whereas value in + * the array represents DQ pin# on the memory part. */ - uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + uint8_t dqs_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL]; /* * Early Command Training Enable/Disable Control @@ -60,10 +79,7 @@ struct mb_lpddr4x_cfg { uint8_t ect; }; -/* Initialize default memory configurations for dimm0-only lpddr4x */ -void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - const struct spd_info *spd, - bool half_populated); +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, + const struct spd_info *spd, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index e6cdae0a30..864f0795e4 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -12,6 +12,10 @@ #include #include +/* If memory is half-populated, then upper half of the channels need to be left empty. */ +#define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ + ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2))) + enum dimm_enable_options { ENABLE_BOTH_DIMMS = 0, DISABLE_DIMM0 = 1, @@ -19,145 +23,268 @@ enum dimm_enable_options { DISABLE_BOTH_DIMMS = 3 }; -#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch) \ - do { \ - memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch, \ - &_b_cfg->dq_map[_ch], \ - sizeof(_b_cfg->dq_map[_ch])); \ - memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch, \ - &_b_cfg->dqs_map[_ch], \ - sizeof(_b_cfg->dqs_map[_ch])); \ - } while (0) +static uint8_t get_dimm_cfg(uintptr_t dimm0, uintptr_t dimm1) +{ + if (dimm0 && dimm1) + return ENABLE_BOTH_DIMMS; + if (!dimm0 && !dimm1) + return DISABLE_BOTH_DIMMS; + if (!dimm1) + return DISABLE_DIMM1; + if (!dimm0) + die("Disabling of only dimm0 is not supported!\n"); + return DISABLE_BOTH_DIMMS; +} -static void spd_read_from_cbfs(const struct spd_info *spd, - uintptr_t *spd_data_ptr, size_t *spd_data_len) +static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, + uintptr_t spd_dimm1) +{ + mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1); + + switch (channel) { + case 0: + mem_cfg->MemorySpdPtr00 = spd_dimm0; + mem_cfg->MemorySpdPtr01 = spd_dimm1; + break; + + case 1: + mem_cfg->MemorySpdPtr02 = spd_dimm0; + mem_cfg->MemorySpdPtr03 = spd_dimm1; + break; + + case 2: + mem_cfg->MemorySpdPtr04 = spd_dimm0; + mem_cfg->MemorySpdPtr05 = spd_dimm1; + break; + + case 3: + mem_cfg->MemorySpdPtr06 = spd_dimm0; + mem_cfg->MemorySpdPtr07 = spd_dimm1; + break; + + case 4: + mem_cfg->MemorySpdPtr08 = spd_dimm0; + mem_cfg->MemorySpdPtr09 = spd_dimm1; + break; + + case 5: + mem_cfg->MemorySpdPtr10 = spd_dimm0; + mem_cfg->MemorySpdPtr11 = spd_dimm1; + break; + + case 6: + mem_cfg->MemorySpdPtr12 = spd_dimm0; + mem_cfg->MemorySpdPtr13 = spd_dimm1; + break; + + case 7: + mem_cfg->MemorySpdPtr14 = spd_dimm0; + mem_cfg->MemorySpdPtr15 = spd_dimm1; + break; + + default: + die("Invalid channel: %d\n", channel); + } +} + +static inline void init_spd_upds_empty(FSP_M_CONFIG *mem_cfg, int channel) +{ + init_spd_upds(mem_cfg, channel, 0, 0); +} + +static inline void init_spd_upds_dimm0(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0) +{ + init_spd_upds(mem_cfg, channel, spd_dimm0, 0); +} + +static void init_dq_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, const uint8_t *dq_byte0, + const uint8_t *dq_byte1) +{ + uint8_t *dq_upd; + + switch (byte_pair) { + case 0: + dq_upd = mem_cfg->DqMapCpu2DramCh0; + break; + case 1: + dq_upd = mem_cfg->DqMapCpu2DramCh1; + break; + case 2: + dq_upd = mem_cfg->DqMapCpu2DramCh2; + break; + case 3: + dq_upd = mem_cfg->DqMapCpu2DramCh3; + break; + case 4: + dq_upd = mem_cfg->DqMapCpu2DramCh4; + break; + case 5: + dq_upd = mem_cfg->DqMapCpu2DramCh5; + break; + case 6: + dq_upd = mem_cfg->DqMapCpu2DramCh6; + break; + case 7: + dq_upd = mem_cfg->DqMapCpu2DramCh7; + break; + default: + die("Invalid byte_pair: %d\n", byte_pair); + } + + if (dq_byte0 && dq_byte1) { + memcpy(dq_upd, dq_byte0, BITS_PER_BYTE); + memcpy(dq_upd + BITS_PER_BYTE, dq_byte1, BITS_PER_BYTE); + } else { + memset(dq_upd, 0, BITS_PER_BYTE * 2); + } +} + +static inline void init_dq_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) +{ + init_dq_upds(mem_cfg, byte_pair, NULL, NULL); +} + +static void init_dqs_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, uint8_t dqs_byte0, + uint8_t dqs_byte1) +{ + uint8_t *dqs_upd; + + switch (byte_pair) { + case 0: + dqs_upd = mem_cfg->DqsMapCpu2DramCh0; + break; + case 1: + dqs_upd = mem_cfg->DqsMapCpu2DramCh1; + break; + case 2: + dqs_upd = mem_cfg->DqsMapCpu2DramCh2; + break; + case 3: + dqs_upd = mem_cfg->DqsMapCpu2DramCh3; + break; + case 4: + dqs_upd = mem_cfg->DqsMapCpu2DramCh4; + break; + case 5: + dqs_upd = mem_cfg->DqsMapCpu2DramCh5; + break; + case 6: + dqs_upd = mem_cfg->DqsMapCpu2DramCh6; + break; + case 7: + dqs_upd = mem_cfg->DqsMapCpu2DramCh7; + break; + default: + die("Invalid byte_pair: %d\n", byte_pair); + } + + dqs_upd[0] = dqs_byte0; + dqs_upd[1] = dqs_byte1; +} + +static inline void init_dqs_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) +{ + init_dqs_upds(mem_cfg, byte_pair, 0, 0); +} + +static void read_spd_from_cbfs(uint8_t index, uintptr_t *data, size_t *len) { struct region_device spd_rdev; - size_t spd_index = spd->spd_spec.spd_index; - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + printk(BIOS_DEBUG, "SPD INDEX = %u\n", index); + if (get_spd_cbfs_rdev(&spd_rdev, index) < 0) die("spd.bin not found or incorrect index\n"); - *spd_data_len = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + *len = region_device_sz(&spd_rdev); + *data = (uintptr_t)rdev_mmap_full(&spd_rdev); } -static void get_spd_data(const struct spd_info *spd, - uintptr_t *spd_data_ptr, size_t *spd_data_len) +static void read_md_spd(const struct spd_info *info, uintptr_t *data, size_t *len) { - if (spd->read_type == READ_SPD_MEMPTR) { - *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; - *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; - return; + if (info->md_spd_loc == SPD_MEMPTR) { + *data = info->data_ptr; + *len = info->data_len; + } else if (info->md_spd_loc == SPD_CBFS) { + read_spd_from_cbfs(info->cbfs_index, data, len); + } else { + die("Not a valid location(%d) for Memory-down SPD!\n", info->md_spd_loc); } - if (spd->read_type == READ_SPD_CBFS) { - spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); - return; - } - - die("no valid way to read SPD info"); + print_spd_info((unsigned char *)data); } -static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - bool half_populated) -{ - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3); - - if (half_populated) - return; - - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7); -} - -static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - uintptr_t spd_data_ptr, - bool half_populated) -{ - uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ - - /* Channel 0 */ - mem_cfg->Reserved9[0] = dimm_cfg; - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - mem_cfg->MemorySpdPtr01 = 0; - - /* Channel 1 */ - mem_cfg->Reserved9[1] = dimm_cfg; - mem_cfg->MemorySpdPtr02 = spd_data_ptr; - mem_cfg->MemorySpdPtr03 = 0; - - /* Channel 2 */ - mem_cfg->Reserved9[2] = dimm_cfg; - mem_cfg->MemorySpdPtr04 = spd_data_ptr; - mem_cfg->MemorySpdPtr05 = 0; - - /* Channel 3 */ - mem_cfg->Reserved9[3] = dimm_cfg; - mem_cfg->MemorySpdPtr06 = spd_data_ptr; - mem_cfg->MemorySpdPtr07 = 0; - - if (half_populated) { - printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); - dimm_cfg = DISABLE_BOTH_DIMMS; - spd_data_ptr = 0; - } - - /* Channel 4 */ - mem_cfg->Reserved9[4] = dimm_cfg; - mem_cfg->MemorySpdPtr08 = spd_data_ptr; - mem_cfg->MemorySpdPtr09 = 0; - - /* Channel 5 */ - mem_cfg->Reserved9[5] = dimm_cfg; - mem_cfg->MemorySpdPtr10 = spd_data_ptr; - mem_cfg->MemorySpdPtr11 = 0; - - /* Channel 6 */ - mem_cfg->Reserved9[6] = dimm_cfg; - mem_cfg->MemorySpdPtr12 = spd_data_ptr; - mem_cfg->MemorySpdPtr13 = 0; - - /* Channel 7 */ - mem_cfg->Reserved9[7] = dimm_cfg; - mem_cfg->MemorySpdPtr14 = spd_data_ptr; - mem_cfg->MemorySpdPtr15 = 0; - - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); -} - -/* Initialize onboard memory configurations for lpddr4x */ -void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - const struct spd_info *spd, - bool half_populated) +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, + const struct spd_info *info, bool half_populated) { - size_t spd_data_len; - uintptr_t spd_data_ptr; + size_t spd_len; + uintptr_t spd_data; + int i; - get_spd_data(spd, &spd_data_ptr, &spd_data_len); - print_spd_info((unsigned char *)spd_data_ptr); + if (info->topology != MEMORY_DOWN) + die("LPDDR4x only support memory-down topology.\n"); - mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr, - half_populated); - - /* LPDDR4 does not allow interleaved memory */ + /* LPDDR4x does not allow interleaved memory */ mem_cfg->DqPinsInterleaved = 0; mem_cfg->ECT = board_cfg->ect; mem_cfg->MrcSafeConfig = 0x1; + + read_md_spd(info, &spd_data, &spd_len); + mem_cfg->MemorySpdDataLen = spd_len; + + for (i = 0; i < LPDDR4X_CHANNELS; i++) { + if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) + init_spd_upds_empty(mem_cfg, i); + else + init_spd_upds_dimm0(mem_cfg, i, spd_data); + } + + /* + * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits (1 + * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in + * each UPD. + * + * Thus, init_dq_upds() needs to be called for dq pair of each channel. + * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] + * DqMapCpu2DramCh1 --> dq_map[CHAN=1][0-1] + * DqMapCpu2DramCh2 --> dq_map[CHAN=2][0-1] + * DqMapCpu2DramCh3 --> dq_map[CHAN=3][0-1] + * DqMapCpu2DramCh4 --> dq_map[CHAN=4][0-1] + * DqMapCpu2DramCh5 --> dq_map[CHAN=5][0-1] + * DqMapCpu2DramCh6 --> dq_map[CHAN=6][0-1] + * DqMapCpu2DramCh7 --> dq_map[CHAN=7][0-1] + */ + for (i = 0; i < LPDDR4X_CHANNELS; i++) { + if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) + init_dq_upds_empty(mem_cfg, i); + else + init_dq_upds(mem_cfg, i, board_cfg->dq_map[i][0], + board_cfg->dq_map[i][1]); + } + + /* + * LPDDR4x memory interface has 2 DQS pairs per channel. FSP UPDs for DQS Map expect a + * pair in each UPD. + * + * Thus, init_dqs_upds() needs to be called for dqs pair of each channel. + * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] + * DqsMapCpu2DramCh1 --> dqs_map[CHAN=1][0-1] + * DqsMapCpu2DramCh2 --> dqs_map[CHAN=2][0-1] + * DqsMapCpu2DramCh3 --> dqs_map[CHAN=3][0-1] + * DqsMapCpu2DramCh4 --> dqs_map[CHAN=4][0-1] + * DqsMapCpu2DramCh5 --> dqs_map[CHAN=5][0-1] + * DqsMapCpu2DramCh6 --> dqs_map[CHAN=6][0-1] + * DqsMapCpu2DramCh7 --> dqs_map[CHAN=7][0-1] + */ + for (i = 0; i < LPDDR4X_CHANNELS; i++) { + if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) + init_dqs_upds_empty(mem_cfg, i); + else + init_dqs_upds(mem_cfg, i, board_cfg->dqs_map[i][0], + board_cfg->dqs_map[i][1]); + } } From 35bff432e5456acec8e68adca6b496fda53c6c57 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 26 Mar 2020 15:45:58 -0700 Subject: [PATCH 0732/1463] soc/intel/tigerlake: Add macros and SPD information for DDR4 This change adds new memory topologies (SODIMM, MIXED) that are supported by DDR4 and macros required for DDR4 support. Memory initialization support for DDR4 will be added in a follow-up change. Signed-off-by: Furquan Shaikh Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/soc/intel/tigerlake/include/soc/meminit.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index aab155e43c..a2fb3f4334 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -17,8 +17,13 @@ #define LPDDR4X_CHANNELS 8 #define LPDDR4X_BYTES_PER_CHANNEL 2 +#define DDR4_CHANNELS 2 +#define DDR4_BYTES_PER_CHANNEL 8 + enum mem_topology { MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */ + SODIMM, /* Supports reading SPD using SMBus (only for DDR4). */ + MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ }; enum md_spd_loc { @@ -43,6 +48,17 @@ struct spd_info { size_t data_len; }; }; + + /* + * SPD info for SODIMM topology. + * Leave addr_dimmN as 0 for any DIMMs that are not populated. + */ + struct { + /* SMBus address for DIMM0 within the channel. */ + uint8_t addr_dimm0; + /* SMBus address for DIMM1 within the channel. */ + uint8_t addr_dimm1; + } smbus_info[DDR4_CHANNELS]; }; /* Board-specific memory configuration information */ From 68680dd7cd1a2678406610e99400bd25bf7fa282 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 31 Mar 2020 17:34:52 +0200 Subject: [PATCH 0733/1463] Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator` These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/arch/x86/acpi.c | 8 +++---- src/device/pci_device.c | 2 +- src/drivers/crb/tis.c | 2 +- src/drivers/generic/adau7002/adau7002.c | 10 ++++----- src/drivers/generic/generic/generic.c | 10 ++++----- src/drivers/generic/gpio_keys/gpio_keys.c | 10 ++++----- .../generic/gpio_regulator/gpio_regulator.c | 2 +- src/drivers/generic/max98357a/max98357a.c | 10 ++++----- src/drivers/gfx/generic/generic.c | 4 ++-- src/drivers/i2c/da7219/da7219.c | 10 ++++----- src/drivers/i2c/generic/generic.c | 10 ++++----- src/drivers/i2c/hid/hid.c | 10 ++++----- src/drivers/i2c/max98373/max98373.c | 10 ++++----- src/drivers/i2c/max98927/max98927.c | 10 ++++----- src/drivers/i2c/nau8825/nau8825.c | 10 ++++----- src/drivers/i2c/rt1011/rt1011.c | 2 +- src/drivers/i2c/rt5663/rt5663.c | 10 ++++----- src/drivers/i2c/sx9310/sx9310.c | 10 ++++----- src/drivers/i2c/tpm/chip.c | 10 ++++----- src/drivers/intel/ish/ish.c | 8 +++---- src/drivers/intel/mipi_camera/camera.c | 10 ++++----- src/drivers/intel/wifi/wifi.c | 16 +++++++------- src/drivers/ipmi/ipmi_kcs_ops.c | 2 +- src/drivers/net/r8168.c | 4 ++-- src/drivers/pc80/tpm/tis.c | 4 ++-- src/drivers/spi/acpi/acpi.c | 10 ++++----- src/drivers/usb/acpi/usb_acpi.c | 10 ++++----- src/ec/google/chromeec/ec_lpc.c | 4 ++-- src/ec/google/wilco/chip.c | 12 +++++----- src/ec/lenovo/h8/h8.c | 2 +- src/include/device/device.h | 4 ++-- src/mainboard/google/auron/mainboard.c | 2 +- src/mainboard/google/beltino/mainboard.c | 2 +- src/mainboard/google/butterfly/mainboard.c | 2 +- src/mainboard/google/cyan/mainboard.c | 2 +- src/mainboard/google/dedede/mainboard.c | 2 +- src/mainboard/google/deltaur/mainboard.c | 2 +- src/mainboard/google/dragonegg/mainboard.c | 2 +- src/mainboard/google/drallion/ramstage.c | 2 +- src/mainboard/google/eve/mainboard.c | 2 +- src/mainboard/google/fizz/mainboard.c | 2 +- src/mainboard/google/glados/mainboard.c | 2 +- src/mainboard/google/hatch/ramstage.c | 2 +- src/mainboard/google/jecht/mainboard.c | 2 +- src/mainboard/google/kahlee/mainboard.c | 2 +- src/mainboard/google/link/mainboard.c | 2 +- src/mainboard/google/octopus/mainboard.c | 2 +- src/mainboard/google/parrot/mainboard.c | 2 +- src/mainboard/google/poppy/mainboard.c | 2 +- src/mainboard/google/rambi/mainboard.c | 2 +- src/mainboard/google/reef/mainboard.c | 2 +- src/mainboard/google/sarien/ramstage.c | 2 +- src/mainboard/google/slippy/mainboard.c | 2 +- src/mainboard/google/stout/mainboard.c | 2 +- src/mainboard/google/volteer/mainboard.c | 2 +- src/mainboard/intel/baskingridge/mainboard.c | 2 +- .../intel/cannonlake_rvp/mainboard.c | 2 +- .../intel/coffeelake_rvp/mainboard.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/intel/glkrvp/mainboard.c | 2 +- src/mainboard/intel/icelake_rvp/mainboard.c | 2 +- .../intel/jasperlake_rvp/mainboard.c | 2 +- src/mainboard/intel/kblrvp/mainboard.c | 2 +- src/mainboard/intel/kunimitsu/mainboard.c | 2 +- src/mainboard/intel/strago/mainboard.c | 2 +- src/mainboard/intel/tglrvp/mainboard.c | 2 +- src/mainboard/intel/wtm2/mainboard.c | 2 +- src/mainboard/lenovo/x200/mainboard.c | 2 +- src/mainboard/lenovo/x201/mainboard.c | 2 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 2 +- src/mainboard/samsung/stumpy/mainboard.c | 2 +- .../amd/agesa/family14/northbridge.c | 2 +- .../amd/agesa/family15tn/northbridge.c | 2 +- .../amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00660F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/gm45/northbridge.c | 2 +- src/northbridge/intel/haswell/gma.c | 18 +++++++-------- src/northbridge/intel/haswell/northbridge.c | 14 ++++++------ src/northbridge/intel/i945/gma.c | 2 +- src/northbridge/intel/i945/northbridge.c | 2 +- src/northbridge/intel/ironlake/gma.c | 2 +- src/northbridge/intel/ironlake/northbridge.c | 2 +- src/northbridge/intel/pineview/gma.c | 20 ++++++++--------- src/northbridge/intel/pineview/northbridge.c | 12 +++++----- src/northbridge/intel/sandybridge/gma.c | 22 +++++++++---------- .../intel/sandybridge/northbridge.c | 14 ++++++------ src/northbridge/intel/x4x/gma.c | 2 +- src/northbridge/intel/x4x/northbridge.c | 2 +- src/soc/amd/common/block/lpc/lpc.c | 2 +- src/soc/amd/picasso/chip.c | 2 +- src/soc/amd/picasso/i2c.c | 2 +- src/soc/amd/picasso/northbridge.c | 2 +- src/soc/amd/stoneyridge/chip.c | 2 +- src/soc/amd/stoneyridge/i2c.c | 2 +- src/soc/amd/stoneyridge/northbridge.c | 2 +- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/braswell/northcluster.c | 6 ++--- src/soc/intel/braswell/southcluster.c | 2 +- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/broadwell/systemagent.c | 2 +- src/soc/intel/cannonlake/chip.c | 2 +- .../intel/common/block/graphics/graphics.c | 16 +++++++------- src/soc/intel/common/block/i2c/i2c.c | 16 +++++++------- src/soc/intel/common/block/lpc/lpc.c | 16 +++++++------- src/soc/intel/common/block/scs/sd.c | 10 ++++----- src/soc/intel/denverton_ns/chip.c | 2 +- src/soc/intel/denverton_ns/lpc.c | 2 +- src/soc/intel/icelake/chip.c | 2 +- src/soc/intel/jasperlake/chip.c | 2 +- src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/tigerlake/chip.c | 2 +- src/soc/intel/xeon_sp/skx/chip.c | 2 +- src/soc/intel/xeon_sp/uncore.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- src/southbridge/intel/bd82x6x/sata.c | 3 +-- src/southbridge/intel/i82371eb/isa.c | 4 ++-- src/southbridge/intel/i82801gx/lpc.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 4 ++-- src/southbridge/intel/i82801jx/lpc.c | 4 ++-- src/southbridge/intel/ibexpeak/lpc.c | 4 ++-- src/southbridge/intel/ibexpeak/sata.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 4 ++-- src/superio/aspeed/ast2400/superio.c | 2 +- src/superio/common/generic.c | 4 ++-- src/superio/nuvoton/nct5539d/superio.c | 6 ++--- src/superio/nuvoton/nct6791d/superio.c | 6 ++--- src/superio/nuvoton/npcd378/superio.c | 18 +++++++-------- 133 files changed, 311 insertions(+), 312 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 317cd483a2..6eded1d97a 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -430,8 +430,8 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { struct device *dev; for (dev = all_devices; dev; dev = dev->next) - if (dev->ops && dev->ops->acpi_fill_ssdt_generator) - dev->ops->acpi_fill_ssdt_generator(dev); + if (dev->ops && dev->ops->acpi_fill_ssdt) + dev->ops->acpi_fill_ssdt(dev); current = (unsigned long) acpigen_get_current(); } @@ -1366,8 +1366,8 @@ unsigned long write_acpi_tables(unsigned long start) acpigen_set_current((char *) current); for (dev = all_devices; dev; dev = dev->next) - if (dev->ops && dev->ops->acpi_inject_dsdt_generator) - dev->ops->acpi_inject_dsdt_generator(dev); + if (dev->ops && dev->ops->acpi_inject_dsdt) + dev->ops->acpi_inject_dsdt(dev); current = (unsigned long) acpigen_get_current(); memcpy((char *)current, (char *)dsdt_file + sizeof(acpi_header_t), diff --git a/src/device/pci_device.c b/src/device/pci_device.c index b1e88a6896..0cbb02d60a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -768,7 +768,7 @@ struct device_operations default_pci_ops_dev = { .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = pci_rom_write_acpi_tables, - .acpi_fill_ssdt_generator = pci_rom_ssdt, + .acpi_fill_ssdt = pci_rom_ssdt, #endif .init = pci_dev_init, .scan_bus = 0, diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index b1fbad01eb..32d1550e5b 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -141,7 +141,7 @@ static struct device_operations __unused crb_ops = { .set_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = crb_tpm_acpi_name, - .acpi_fill_ssdt_generator = crb_tpm_fill_ssdt, + .acpi_fill_ssdt = crb_tpm_fill_ssdt, #endif }; diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 7f73cef40d..0a3d62357b 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -65,12 +65,12 @@ static const char *adau7002_acpi_name(const struct device *dev) #endif static struct device_operations adau7002_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = adau7002_acpi_name, - .acpi_fill_ssdt_generator = adau7002_fill_ssdt, + .acpi_name = adau7002_acpi_name, + .acpi_fill_ssdt = adau7002_fill_ssdt, #endif }; diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index c68fa3a0d3..0ba2d53c82 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -78,11 +78,11 @@ static const char *generic_dev_acpi_name(const struct device *dev) } static struct device_operations generic_dev_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = generic_dev_acpi_name, - .acpi_fill_ssdt_generator = generic_dev_fill_ssdt_generator, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = generic_dev_acpi_name, + .acpi_fill_ssdt = generic_dev_fill_ssdt_generator, }; static void generic_dev_enable(struct device *dev) diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 753a555a48..67c591386d 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -112,11 +112,11 @@ static const char *gpio_keys_acpi_name(const struct device *dev) } static struct device_operations gpio_keys_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = gpio_keys_acpi_name, - .acpi_fill_ssdt_generator = gpio_keys_fill_ssdt_generator, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = gpio_keys_acpi_name, + .acpi_fill_ssdt = gpio_keys_fill_ssdt_generator, }; static void gpio_keys_enable(struct device *dev) diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 23c044de2a..b4761262e0 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -73,7 +73,7 @@ static struct device_operations gpio_regulator_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .acpi_name = gpio_regulator_acpi_name, - .acpi_fill_ssdt_generator = gpio_regulator_fill_ssdt_generator, + .acpi_fill_ssdt = gpio_regulator_fill_ssdt_generator, }; static void gpio_regulator_enable(struct device *dev) diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 56fd26c3fd..6f724f8937 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -80,12 +80,12 @@ static const char *max98357a_acpi_name(const struct device *dev) #endif static struct device_operations max98357a_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = max98357a_acpi_name, - .acpi_fill_ssdt_generator = max98357a_fill_ssdt, + .acpi_name = max98357a_acpi_name, + .acpi_fill_ssdt = max98357a_fill_ssdt, #endif }; diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 9e952e8571..a20279f7af 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -151,8 +151,8 @@ static const char *gfx_acpi_name(const struct device *dev) } static struct device_operations gfx_ops = { - .acpi_name = gfx_acpi_name, - .acpi_fill_ssdt_generator = gfx_fill_ssdt_generator, + .acpi_name = gfx_acpi_name, + .acpi_fill_ssdt = gfx_fill_ssdt_generator, }; static void gfx_enable(struct device *dev) diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index f82cd9f6e7..5c67eda2d0 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -108,12 +108,12 @@ static const char *da7219_acpi_name(const struct device *dev) #endif static struct device_operations da7219_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = da7219_acpi_name, - .acpi_fill_ssdt_generator = da7219_fill_ssdt, + .acpi_name = da7219_acpi_name, + .acpi_fill_ssdt = da7219_fill_ssdt, #endif }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 0b36e5f11f..592e791ba9 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -190,12 +190,12 @@ static const char *i2c_generic_acpi_name(const struct device *dev) #endif static struct device_operations i2c_generic_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = i2c_generic_acpi_name, - .acpi_fill_ssdt_generator = i2c_generic_fill_ssdt_generator, + .acpi_name = i2c_generic_acpi_name, + .acpi_fill_ssdt = i2c_generic_fill_ssdt_generator, #endif }; diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index b8185d062b..6e4169ebb9 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -47,12 +47,12 @@ static const char *i2c_hid_acpi_name(const struct device *dev) #endif static struct device_operations i2c_hid_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = i2c_hid_acpi_name, - .acpi_fill_ssdt_generator = i2c_hid_fill_ssdt_generator, + .acpi_name = i2c_hid_acpi_name, + .acpi_fill_ssdt = i2c_hid_fill_ssdt_generator, #endif }; diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 48db3e1be4..71ba75b9fe 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -85,11 +85,11 @@ static const char *max98373_acpi_name(const struct device *dev) } static struct device_operations max98373_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = max98373_acpi_name, - .acpi_fill_ssdt_generator = max98373_fill_ssdt, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = max98373_acpi_name, + .acpi_fill_ssdt = max98373_fill_ssdt, }; static void max98373_enable(struct device *dev) diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index 1cc72d36cf..7979fe32a0 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -81,11 +81,11 @@ static const char *max98927_acpi_name(const struct device *dev) } static struct device_operations max98927_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = max98927_acpi_name, - .acpi_fill_ssdt_generator = max98927_fill_ssdt, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = max98927_acpi_name, + .acpi_fill_ssdt = max98927_fill_ssdt, }; static void max98927_enable(struct device *dev) diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 33b3421318..5d56b243e1 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -96,12 +96,12 @@ static const char *nau8825_acpi_name(const struct device *dev) #endif static struct device_operations nau8825_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = nau8825_acpi_name, - .acpi_fill_ssdt_generator = nau8825_fill_ssdt, + .acpi_name = nau8825_acpi_name, + .acpi_fill_ssdt = nau8825_fill_ssdt, #endif }; diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index 8dc3cd9bb0..cfaeae8517 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -99,7 +99,7 @@ static struct device_operations rt1011_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .acpi_name = rt1011_acpi_name, - .acpi_fill_ssdt_generator = rt1011_fill_ssdt, + .acpi_fill_ssdt = rt1011_fill_ssdt, }; static void rt1011_enable(struct device *dev) diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 6f4e032953..15014cda9e 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -85,11 +85,11 @@ static const char *rt5663_acpi_name(const struct device *dev) } static struct device_operations rt5663_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = rt5663_acpi_name, - .acpi_fill_ssdt_generator = rt5663_fill_ssdt, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = rt5663_acpi_name, + .acpi_fill_ssdt = rt5663_fill_ssdt, }; static void rt5663_enable(struct device *dev) diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 9da687574f..781d09d94d 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -89,11 +89,11 @@ static const char *i2c_sx9310_acpi_name(const struct device *dev) } static struct device_operations i2c_sx9310_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = i2c_sx9310_acpi_name, - .acpi_fill_ssdt_generator = i2c_sx9310_fill_ssdt, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = i2c_sx9310_acpi_name, + .acpi_fill_ssdt = i2c_sx9310_fill_ssdt, }; static void i2c_sx9310_enable(struct device *dev) diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index b13f66675b..d36e4c2932 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -72,11 +72,11 @@ static const char *i2c_tpm_acpi_name(const struct device *dev) } static struct device_operations i2c_tpm_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = i2c_tpm_acpi_name, - .acpi_fill_ssdt_generator = i2c_tpm_fill_ssdt, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = i2c_tpm_acpi_name, + .acpi_fill_ssdt = i2c_tpm_fill_ssdt, }; static void i2c_tpm_enable(struct device *dev) diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index d542bd371a..256b486dc8 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -40,10 +40,10 @@ static void ish_fill_ssdt_generator(struct device *dev) } static struct device_operations intel_ish_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_fill_ssdt_generator = ish_fill_ssdt_generator, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_fill_ssdt = ish_fill_ssdt_generator, }; static void intel_ish_enable(struct device *dev) diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 0cada814e9..92fa00b956 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -78,11 +78,11 @@ static const char *camera_acpi_name(const struct device *dev) } static struct device_operations camera_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = camera_acpi_name, - .acpi_fill_ssdt_generator = camera_fill_ssdt, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = camera_acpi_name, + .acpi_fill_ssdt = camera_fill_ssdt, }; static void camera_enable(struct device *dev) diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index e5efbe15fb..af7407df2f 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -90,17 +90,17 @@ static struct pci_operations pci_ops = { }; struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = wifi_pci_dev_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = wifi_pci_dev_init, #if CONFIG(GENERATE_SMBIOS_TABLES) - .get_smbios_data = smbios_write_wifi, + .get_smbios_data = smbios_write_wifi, #endif - .ops_pci = &pci_ops, + .ops_pci = &pci_ops, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = generic_wifi_acpi_name, - .acpi_fill_ssdt_generator = intel_wifi_fill_ssdt, + .acpi_name = generic_wifi_acpi_name, + .acpi_fill_ssdt = intel_wifi_fill_ssdt, #endif }; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index e0fa1b0120..e5f60fe6b8 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -362,7 +362,7 @@ static struct device_operations ops = { .init = ipmi_kcs_init, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = ipmi_write_acpi_tables, - .acpi_fill_ssdt_generator = ipmi_ssdt, + .acpi_fill_ssdt = ipmi_ssdt, #endif #if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = ipmi_smbios_data, diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index a3e1e1b049..c764b433b6 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -374,8 +374,8 @@ static struct device_operations r8168_ops = { .init = r8168_init, .scan_bus = 0, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = r8168_net_acpi_name, - .acpi_fill_ssdt_generator = r8168_net_fill_ssdt, + .acpi_name = r8168_net_acpi_name, + .acpi_fill_ssdt = r8168_net_fill_ssdt, #endif }; diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index a35ef83d2c..b9fd0cf006 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -988,8 +988,8 @@ static struct device_operations lpc_tpm_ops = { .read_resources = lpc_tpm_read_resources, .set_resources = lpc_tpm_set_resources, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = lpc_tpm_acpi_name, - .acpi_fill_ssdt_generator = lpc_tpm_fill_ssdt, + .acpi_name = lpc_tpm_acpi_name, + .acpi_fill_ssdt = lpc_tpm_fill_ssdt, #endif }; diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 7e107d6f67..30a81262ce 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -200,11 +200,11 @@ static const char *spi_acpi_name(const struct device *dev) } static struct device_operations spi_acpi_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .acpi_name = spi_acpi_name, - .acpi_fill_ssdt_generator = spi_acpi_fill_ssdt_generator, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = spi_acpi_name, + .acpi_fill_ssdt = spi_acpi_fill_ssdt_generator, }; static void spi_acpi_enable(struct device *dev) diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index a312c88b69..2402e8bd12 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -80,11 +80,11 @@ static void usb_acpi_fill_ssdt_generator(struct device *dev) } static struct device_operations usb_acpi_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .scan_bus = scan_static_bus, - .acpi_fill_ssdt_generator = usb_acpi_fill_ssdt_generator, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .scan_bus = scan_static_bus, + .acpi_fill_ssdt = usb_acpi_fill_ssdt_generator, }; static void usb_acpi_enable(struct device *dev) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 4b97ff98d7..c621a39401 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -452,8 +452,8 @@ static struct device_operations ops = { .enable_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = google_chromeec_acpi_name, - .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, + .acpi_name = google_chromeec_acpi_name, + .acpi_fill_ssdt = google_chromeec_fill_ssdt_generator, #endif }; diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index e1181eee87..acbd4871e4 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -228,12 +228,12 @@ static const char *wilco_ec_acpi_name(const struct device *dev) } static struct device_operations ops = { - .init = wilco_ec_init, - .read_resources = wilco_ec_read_resources, - .enable_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .acpi_fill_ssdt_generator = wilco_ec_fill_ssdt_generator, - .acpi_name = wilco_ec_acpi_name, + .init = wilco_ec_init, + .read_resources = wilco_ec_read_resources, + .enable_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .acpi_fill_ssdt = wilco_ec_fill_ssdt_generator, + .acpi_name = wilco_ec_acpi_name, }; static struct pnp_info info[] = { diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index cafbe645b4..3bdb50ddda 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -227,7 +227,7 @@ struct device_operations h8_dev_ops = { .get_smbios_strings = h8_smbios_strings, #endif #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = h8_ssdt_generator, + .acpi_fill_ssdt = h8_ssdt_generator, .acpi_name = h8_acpi_name, #endif .init = h8_init, diff --git a/src/include/device/device.h b/src/include/device/device.h index 333ac5d404..9ba4d3173e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -50,8 +50,8 @@ struct device_operations { #if CONFIG(HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); - void (*acpi_fill_ssdt_generator)(struct device *dev); - void (*acpi_inject_dsdt_generator)(struct device *dev); + void (*acpi_fill_ssdt)(struct device *dev); + void (*acpi_inject_dsdt)(struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index da72d8f430..3cb44f90ad 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -41,7 +41,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 2b42ceb115..43f80103ce 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -40,7 +40,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 37c17ee514..03a1df4d04 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -271,7 +271,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 0d137f1861..2ef44d49d8 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -28,7 +28,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 4df190c2be..aa2de37c06 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -35,7 +35,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index eca5ee8e78..0a906d62ad 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -14,7 +14,7 @@ static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c index 64f7a92525..225b072c2e 100644 --- a/src/mainboard/google/dragonegg/mainboard.c +++ b/src/mainboard/google/dragonegg/mainboard.c @@ -34,7 +34,7 @@ static void mainboard_init(void *chip_info) static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = NULL; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 38dc133382..1c537d53c2 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -69,7 +69,7 @@ static void mainboard_init(void *chip_info) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 37b4b673f3..106d6ac8e6 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -70,7 +70,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6bb298b8d6..ef23dc5c75 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -230,7 +230,7 @@ static void mainboard_enable(struct device *dev) mainboard_set_power_limits(conf); dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 1f5f6a8ea0..4f5859972d 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -108,7 +108,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 005a1a9f70..9b940b46d0 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -48,7 +48,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; variant_mainboard_enable(dev); } diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index 2a8a7fc645..0c621cdbe7 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -34,7 +34,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 9650298d53..968cd7ce69 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -169,7 +169,7 @@ static void kahlee_enable(struct device *dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 4551be8125..23ae30b85a 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -184,7 +184,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; #if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 6dc661dc3f..7b73b9d1be 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -108,7 +108,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 6b242ffda9..98939b400a 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -74,7 +74,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 4c75a10a4d..a375d1f33d 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -59,7 +59,7 @@ static unsigned long mainboard_write_acpi_tables(struct device *device, static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 4ecb08eeae..4a1fd91dce 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -161,7 +161,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; #if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 2ba1e67065..ec09963bb3 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -137,7 +137,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 7df73b0148..6676e911c7 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -81,7 +81,7 @@ static void mainboard_init(void *chip_info) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index b7af3668f8..2a2b13b0b0 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -81,7 +81,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 23d2889f01..b411763c75 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -57,7 +57,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 2d505e1c58..4e9843ceae 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -24,7 +24,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 28dabf0f1c..d60d3bf7d8 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -31,7 +31,7 @@ void mainboard_suspend_resume(void) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c index 7cf4bfaa3f..3f6174deba 100644 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c @@ -58,7 +58,7 @@ static unsigned long mainboard_write_acpi_tables(struct device *device, static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index 6343f885e3..6077cbfbba 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -57,7 +57,7 @@ static unsigned long mainboard_write_acpi_tables(struct device *device, static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index d6141c7aa8..74c365bcaf 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -24,7 +24,7 @@ static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index 139d879def..0670afebad 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -67,7 +67,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 051c6a671f..2f6595f15b 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -30,7 +30,7 @@ static void mainboard_init(void *chip_info) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 2f84d7af1f..b765eecc17 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -29,7 +29,7 @@ static void mainboard_init(void *chip_info) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 46c35cb0db..7e2df109ea 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -33,7 +33,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 40275fd6c6..41453d4939 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -95,7 +95,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 8e7deff412..16c89fcd4e 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -30,7 +30,7 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 1f24e8baa4..680472b71b 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -40,7 +40,7 @@ static void mainboard_init(void *chip_info) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index fbe3981cc5..aa4a707798 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -30,7 +30,7 @@ void mainboard_suspend_resume(void) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 37823bc92f..3406689f0c 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -28,7 +28,7 @@ static void mainboard_enable(struct device *dev) GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + dev->ops->acpi_fill_ssdt = fill_ssdt; if (CONFIG(BOARD_LENOVO_X200)) init_dock(); } diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 212f3a90cf..dbbb75539e 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -29,7 +29,7 @@ static void fill_ssdt(struct device *device) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + dev->ops->acpi_fill_ssdt = fill_ssdt; /* If we're resuming from suspend, blink suspend LED */ if (acpi_is_wakeup_s3()) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 7b399e4478..839fdabd72 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -119,7 +119,7 @@ static void fill_ssdt(struct device *device) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + dev->ops->acpi_fill_ssdt = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 44360ee896..fcf4140b34 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -90,7 +90,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 45a60c670a..757f2fd8c5 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -23,7 +23,7 @@ static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 1ac5a69cf9..a1d345728a 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -807,7 +807,7 @@ static struct device_operations northbridge_operations = { .read_resources = nb_read_resources, .set_resources = nb_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .init = northbridge_init, .enable = 0,.ops_pci = 0, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index a62e12e772..c5f649e91f 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -561,7 +561,7 @@ static struct device_operations northbridge_operations = { .set_resources = nb_set_resources, .enable_resources = pci_dev_enable_resources, .init = DEVICE_NOOP, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, .ops_pci = 0, diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 2cdcb58023..d9c3c36c25 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -560,7 +560,7 @@ static struct device_operations northbridge_operations = { .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = DEVICE_NOOP, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, .ops_pci = 0, diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index e90848a36b..30c68d80fb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -555,7 +555,7 @@ static struct device_operations northbridge_operations = { .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = DEVICE_NOOP, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, .ops_pci = 0, diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 200508617c..44ff37003c 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -545,7 +545,7 @@ static struct device_operations northbridge_operations = { .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, .ops_pci = 0, diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index f611bd6e3e..0a07dfa1d5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -775,7 +775,7 @@ static struct device_operations northbridge_operations = { .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, .ops_pci = 0, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index eed0b92d78..821487ad6f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -279,7 +279,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = gma_ssdt, + .acpi_fill_ssdt = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index a0ff04fa25..9484cd9fab 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -233,7 +233,7 @@ static struct device_operations pci_domain_ops = { .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, .acpi_name = northbridge_acpi_name, }; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 65c5cf3e75..c0eaf6dfdb 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -573,15 +573,15 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gma_func0_init, - .acpi_fill_ssdt_generator = gma_ssdt, - .scan_bus = NULL, - .enable = NULL, - .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .acpi_fill_ssdt = gma_ssdt, + .scan_bus = NULL, + .enable = NULL, + .ops_pci = &gma_pci_ops, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c8273a1e62..4e16ca06e3 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -472,13 +472,13 @@ static struct pci_operations intel_pci_ops = { }; static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .acpi_fill_ssdt_generator = generate_cpu_entries, - .scan_bus = NULL, - .ops_pci = &intel_pci_ops, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .acpi_fill_ssdt = generate_cpu_entries, + .scan_bus = NULL, + .ops_pci = &intel_pci_ops, }; static const unsigned short mc_pci_device_ids[] = { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index f4d6aaf5c6..c26ffb4bf5 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -829,7 +829,7 @@ static struct device_operations gma_func0_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, - .acpi_fill_ssdt_generator = gma_ssdt, + .acpi_fill_ssdt = gma_ssdt, .scan_bus = 0, .enable = 0, .disable = gma_func0_disable, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index a91efbf275..16cf5e6ae2 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -195,7 +195,7 @@ static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index cba25aa64a..b35305b0c1 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -269,7 +269,7 @@ static struct device_operations gma_func0_ops = { .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = gma_ssdt, + .acpi_fill_ssdt = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 1af4a1ce63..4637175ea1 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -255,7 +255,7 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 0b04ade697..307529d60b 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -334,16 +334,16 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = NULL, - .init = gma_func0_init, - .scan_bus = NULL, - .enable = NULL, - .ops_pci = &gma_pci_ops, - .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = NULL, + .init = gma_func0_init, + .scan_bus = NULL, + .enable = NULL, + .ops_pci = &gma_pci_ops, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 727db82b09..87443ca2f9 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -184,12 +184,12 @@ static const char *northbridge_acpi_name(const struct device *dev) } static struct device_operations pci_domain_ops = { - .read_resources = mch_domain_read_resources, - .set_resources = mch_domain_set_resources, - .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, - .acpi_fill_ssdt_generator = generate_cpu_entries, - .acpi_name = northbridge_acpi_name, + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, + .init = mch_domain_init, + .scan_bus = pci_domain_scan_bus, + .acpi_fill_ssdt = generate_cpu_entries, + .acpi_name = northbridge_acpi_name, }; static struct device_operations cpu_bus_ops = { diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 1680b1e2a1..e79277c392 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -707,17 +707,17 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = gma_ssdt, - .init = gma_func0_init, - .scan_bus = NULL, - .enable = NULL, - .disable = gma_func0_disable, - .ops_pci = &gma_pci_ops, - .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = gma_ssdt, + .init = gma_func0_init, + .scan_bus = NULL, + .enable = NULL, + .disable = gma_func0_disable, + .ops_pci = &gma_pci_ops, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ef03865905..ff5d7f27ba 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -440,13 +440,13 @@ static struct pci_operations intel_pci_ops = { }; static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .scan_bus = NULL, - .ops_pci = &intel_pci_ops, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .scan_bus = NULL, + .ops_pci = &intel_pci_ops, + .acpi_fill_ssdt = generate_cpu_entries, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index d43ddf9a36..ff8820cf28 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -149,7 +149,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = gma_ssdt, + .acpi_fill_ssdt = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, .disable = gma_func0_disable, diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 732d97ece3..63243f1a74 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -183,7 +183,7 @@ static struct device_operations pci_domain_ops = { .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, .acpi_name = northbridge_acpi_name, }; diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index ff7d561457..7f9b71554e 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -325,7 +325,7 @@ static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index a7b0c26335..cf9bd5473f 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -34,7 +34,7 @@ struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = picasso_init_cpus, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, }; const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 5e5db9e8ed..e2da961f7d 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -144,7 +144,7 @@ struct device_operations picasso_i2c_mmio_ops = { .enable_resources = DEVICE_NOOP, .scan_bus = scan_smbus, .acpi_name = i2c_acpi_name, - .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, + .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, }; /* diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 7be5aef324..20589a95e3 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -203,7 +203,7 @@ static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, .ops_pci = 0, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index f08c12f32f..caf9c63888 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -39,7 +39,7 @@ struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = stoney_init_cpus, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, }; const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index e5c2d98736..8db263838f 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -141,7 +141,7 @@ struct device_operations stoneyridge_i2c_mmio_ops = { .enable_resources = DEVICE_NOOP, .scan_bus = scan_smbus, .acpi_name = i2c_acpi_name, - .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, + .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, }; /* diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 3707049130..afcd49824b 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -356,7 +356,7 @@ static struct device_operations northbridge_operations = { .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, .enable = 0, .ops_pci = 0, diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 5a652608eb..ee533bb743 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -226,7 +226,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .scan_bus = NULL, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, }; static void enable_dev(struct device *dev) diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index d7f17486da..0b61fe7d05 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -136,7 +136,7 @@ static void nc_read_resources(struct device *dev) static struct device_operations nc_ops = { .read_resources = nc_read_resources, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, .set_resources = NULL, .enable_resources = NULL, .init = NULL, diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 746a353051..be58f42a58 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -521,7 +521,7 @@ static void southcluster_inject_dsdt(struct device *device) static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, - .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .enable_resources = NULL, .init = sc_init, diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index f8e3391f9e..4acef25d45 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -166,9 +166,9 @@ static void nc_read_resources(struct device *dev) } static struct device_operations nc_ops = { - .acpi_fill_ssdt_generator = generate_cpu_entries, - .read_resources = nc_read_resources, - .ops_pci = &soc_pci_ops, + .acpi_fill_ssdt = generate_cpu_entries, + .read_resources = nc_read_resources, + .ops_pci = &soc_pci_ops, }; static const struct pci_driver nc_driver __pci_driver = { diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index be0d910ed8..aa054d6801 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -573,7 +573,7 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, - .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 15b383c9e5..bc6bc6b200 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -623,7 +623,7 @@ static struct device_operations device_ops = { .read_resources = &pch_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, - .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = broadwell_write_acpi_tables, .init = &lpc_init, .scan_bus = &scan_static_bus, diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 1af554a669..fdaa9f6541 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -440,7 +440,7 @@ static void systemagent_init(struct device *dev) static struct device_operations systemagent_ops = { .read_resources = systemagent_read_resources, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = systemagent_init, diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a53c1a8bef..a2a678ba28 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -199,7 +199,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, }; static void soc_enable(struct device *dev) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e1eb6fe6fb..55c181b0bd 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -126,16 +126,16 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) } static const struct device_operations graphics_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = graphics_soc_init, - .ops_pci = &pci_dev_ops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = graphics_soc_init, + .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = graphics_soc_write_acpi_opregion, - .acpi_fill_ssdt_generator = gma_generate_ssdt, + .write_acpi_tables = graphics_soc_write_acpi_opregion, + .acpi_fill_ssdt = gma_generate_ssdt, #endif - .scan_bus = scan_generic_bus, + .scan_bus = scan_generic_bus, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index b5ea15e0c6..6612210a84 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -175,15 +175,15 @@ static void dw_i2c_device_init(struct device *dev) } static struct device_operations i2c_dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, - .ops_i2c_bus = &dw_i2c_bus_ops, - .ops_pci = &pci_dev_ops_pci, - .init = dw_i2c_device_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_smbus, + .ops_i2c_bus = &dw_i2c_bus_ops, + .ops_pci = &pci_dev_ops_pci, + .init = dw_i2c_device_init, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, + .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, #endif }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index e65beb4a95..4cfd6f4839 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -108,16 +108,16 @@ static void pch_lpc_set_resources(struct device *dev) } static struct device_operations device_ops = { - .read_resources = pch_lpc_read_resources, - .set_resources = pch_lpc_set_resources, - .enable_resources = pci_dev_enable_resources, + .read_resources = pch_lpc_read_resources, + .set_resources = pch_lpc_set_resources, + .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = southbridge_write_acpi_tables, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_inject_dsdt = southbridge_inject_dsdt, #endif - .init = lpc_soc_init, - .scan_bus = scan_static_bus, - .ops_pci = &pci_dev_ops_pci, + .init = lpc_soc_init, + .scan_bus = scan_static_bus, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 56af940875..d529faaaca 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -54,13 +54,13 @@ static void sd_fill_ssdt(struct device *dev) #endif static struct device_operations dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = sd_fill_ssdt, + .acpi_fill_ssdt = sd_fill_ssdt, #endif - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index f71b5967e9..c41d857d88 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -48,7 +48,7 @@ static struct device_operations cpu_bus_ops = { .init = denverton_init_cpus, .scan_bus = NULL, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index bf9263dcd3..f695d6123f 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -552,7 +552,7 @@ static struct device_operations device_ops = { .read_resources = lpc_read_resources, .set_resources = pci_dev_set_resources, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = southcluster_write_acpi_tables, #endif .enable_resources = lpc_enable_resources, diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index d2427b931d..304f7e3501 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -155,7 +155,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, }; static void soc_enable(struct device *dev) diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index b7ed9df3d8..2b00f96e1e 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -163,7 +163,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 0ab10ca4c7..40d5b1d66e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -111,7 +111,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 1c7078d6cf..231623ca8d 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -163,7 +163,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 7a737ac2b4..764e70fea6 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -489,7 +489,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, #if CONFIG(HAVE_ACPI_TABLES) /* defined in src/soc/intel/common/block/acpi/acpi.c */ - .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_fill_ssdt = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index c72c6c3ffc..f549eecd85 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -288,7 +288,7 @@ static struct device_operations mmapvtd_ops = { .init = mmapvtd_init, .ops_pci = &soc_pci_ops, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_inject_dsdt_generator = NULL, + .acpi_inject_dsdt = NULL, #endif }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 46ab5fc47a..1f921936d9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -884,8 +884,8 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .write_acpi_tables = acpi_write_hpet, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_inject_dsdt = southbridge_inject_dsdt, + .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, .final = lpc_final, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index ba3630ac3e..4d2ac1c1d9 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -255,8 +255,7 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator - = sata_fill_ssdt, + .acpi_fill_ssdt = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, .scan_bus = 0, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 6e1347d0b3..7fe243f1d5 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -130,8 +130,8 @@ static const struct device_operations isa_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt = southbridge_acpi_fill_ssdt_generator, #endif .init = isa_init, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 743dbba676..db0dc4198a 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -684,9 +684,9 @@ static struct device_operations device_ops = { .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 8b5efd9f2e..626016402e 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -530,9 +530,9 @@ static struct device_operations device_ops = { .read_resources = i82801ix_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e3fdde75e9..5f02d7469f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -688,9 +688,9 @@ static struct device_operations device_ops = { .read_resources = i82801jx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0062e0901c..5f7631322b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -765,8 +765,8 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_inject_dsdt = southbridge_inject_dsdt, + .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 33437ef7d6..555b5ca758 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -240,7 +240,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .acpi_fill_ssdt_generator = sata_fill_ssdt, + .acpi_fill_ssdt = sata_fill_ssdt, .scan_bus = 0, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 745c2315c0..f0b88b2f41 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -963,8 +963,8 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_fill_ssdt = southbridge_fill_ssdt, + .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_name = lpc_acpi_name, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 4867f6ed88..a896b643c6 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -66,7 +66,7 @@ static struct device_operations ops = { .init = ast2400_init, .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_fill_ssdt = superio_common_fill_ssdt_generator, .acpi_name = superio_common_ldn_acpi_name, .acpi_hid = ast2400_acpi_hid, #endif diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 809f8866ca..20ffb3db18 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -300,8 +300,8 @@ static struct device_operations ops = { .enable_resources = DEVICE_NOOP, .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = generic_ssdt, - .acpi_name = generic_acpi_name, + .acpi_fill_ssdt = generic_ssdt, + .acpi_name = generic_acpi_name, #endif }; diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index 5402b2e0fd..9a620c97ee 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -52,9 +52,9 @@ static struct device_operations ops = { .init = nct5539d_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, - .acpi_name = superio_common_ldn_acpi_name, - .acpi_hid = nct5539d_acpi_hid, + .acpi_fill_ssdt = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = nct5539d_acpi_hid, #endif }; diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index a8e267b912..e04a9232ae 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -50,9 +50,9 @@ static struct device_operations ops = { .init = nct6791d_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, - .acpi_name = superio_common_ldn_acpi_name, - .acpi_hid = nct6791d_acpi_hid, + .acpi_fill_ssdt = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = nct6791d_acpi_hid, #endif }; diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 95a4babbb7..94b42a02cf 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -422,16 +422,16 @@ static void npcd378_fill_ssdt_generator(struct device *dev) #endif static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = npcd378_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = npcd378_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = npcd378_fill_ssdt_generator, - .acpi_name = superio_common_ldn_acpi_name, - .acpi_hid = npcd378_acpi_hid, + .acpi_fill_ssdt = npcd378_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = npcd378_acpi_hid, #endif }; From 38641aa8b40ef66e5a5016f6f299a3aa1fb9b0d5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 31 Mar 2020 17:51:18 +0200 Subject: [PATCH 0734/1463] drivers/intel/gma/acpi: Bail out on empty display list Whether the GMA is used depends on the mainboard, so we shouldn't rely on the presence of the static ACPI code around `GFX0`. Change-Id: I4d20b459b8361e43435b535b2b395f51ce1704e6 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39978 Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/acpi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index c0eef880a9..5a10ab4ed7 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -13,6 +13,9 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * const char *names[] = { "UNK", "VGA", "TV", "DVI", "LCD" }; int counters[ARRAY_SIZE(names)] = { 0 }; + if (!conf->ndid) + return; + acpigen_write_scope("\\_SB.PCI0.GFX0"); /* From 53e24468f0b31c82565762e51706da72a92aac29 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 5 Aug 2016 02:20:15 -0500 Subject: [PATCH 0735/1463] soc/intel/broadwell: add ACPI backlight support Add framework to generate ACPI methods in SSDT for screen backlight control. Adjust params for gtt_ methods to match prototypes in i915.h and avoid conflicts. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: If93b7690ef36b5d19ca43957e8a1bef91ec5821d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39941 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/soc/intel/broadwell/chip.h | 3 +++ src/soc/intel/broadwell/igd.c | 18 +++++++++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index fabb95ad00..b68da91c03 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -15,6 +15,7 @@ #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ #define _SOC_INTEL_BROADWELL_CHIP_H_ +#include #include struct soc_intel_broadwell_config { @@ -130,6 +131,8 @@ struct soc_intel_broadwell_config { */ int cdclk; + struct i915_gpu_controller_info gfx; + /* Enable S0iX support */ int s0ix_enable; diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index ecb5417181..77375e4497 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -258,7 +259,7 @@ u32 map_oprom_vendev(u32 vendev) static struct resource *gtt_res = NULL; -static unsigned long gtt_read(unsigned long reg) +u32 gtt_read(u32 reg) { u32 val; val = read32(res2mmio(gtt_res, reg, 0)); @@ -266,7 +267,7 @@ static unsigned long gtt_read(unsigned long reg) } -static void gtt_write(unsigned long reg, unsigned long data) +void gtt_write(u32 reg, u32 data) { write32(res2mmio(gtt_res, reg, 0), data); } @@ -279,9 +280,8 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) gtt_write(reg, val); } -static int gtt_poll(u32 reg, u32 mask, u32 value) -{ - unsigned int try = GT_RETRY; +int gtt_poll(u32 reg, u32 mask, u32 value) +{ unsigned int try = GT_RETRY; u32 data; while (try--) { @@ -627,6 +627,13 @@ gma_write_acpi_tables(struct device *const dev, unsigned long current, return current; } +static void gma_generate_ssdt(struct device *dev) +{ + const struct soc_intel_broadwell_config *chip = dev->chip_info; + + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); +} + static struct device_operations igd_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, @@ -634,6 +641,7 @@ static struct device_operations igd_ops = { .init = &igd_init, .ops_pci = &broadwell_pci_ops, .write_acpi_tables = gma_write_acpi_tables, + .acpi_fill_ssdt = gma_generate_ssdt, }; static const unsigned short pci_device_ids[] = { From 948a5d0310f6a4f7b34cd416b81d0e56fd3ce3d4 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 20:00:38 -0500 Subject: [PATCH 0736/1463] sb/intel/lynxpoint: drop IGD-related NVS variables NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Iec3a18871725fd5f5c4c568c2bd771bb56245bc7 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39951 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 7 ------- src/southbridge/intel/lynxpoint/lpc.c | 8 -------- src/southbridge/intel/lynxpoint/nvs.h | 4 +--- 3 files changed, 1 insertion(+), 18 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 6dcec0dccc..a8de07ce7c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -88,13 +88,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 /* TPM support */ Offset (0x5b), diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f0b88b2f41..bb0d997ad6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -31,7 +31,6 @@ #include "nvs.h" #include "pch.h" #include -#include #include #include #include @@ -724,8 +723,6 @@ static void southbridge_inject_dsdt(struct device *dev) } if (gnvs) { - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - acpi_create_gnvs(gnvs); gnvs->apic = 1; @@ -739,11 +736,6 @@ static void southbridge_inject_dsdt(struct device *dev) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); - if (gfx) { - gnvs->ndid = gfx->ndid; - memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - } - /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 3f2ce55766..b170141204 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -75,9 +75,7 @@ typedef struct global_nvs_t { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 rsvd14[3]; - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ + u8 rsvd14[27]; /* TPM support */ u8 tpmp; /* 0x5b - TPM Present */ u8 tpme; /* 0x5c - TPM Enable */ From c821f00b518c82d20672be844c3a3ef4807112fe Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 20:05:49 -0500 Subject: [PATCH 0737/1463] sb/intel/bd82x6x: drop IGD-related NVS variables NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Ie7491409681d8c2721dd6d6a16a8d5004cd0cf8a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39952 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 7 ------- src/southbridge/intel/bd82x6x/lpc.c | 7 ------- src/southbridge/intel/bd82x6x/nvs.h | 5 +---- 3 files changed, 1 insertion(+), 18 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 1b23cef6ac..ac42c7a327 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -88,13 +88,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 /* Backlight Control */ Offset (0x64), BLCS, 8, // 0x64 - Backlight control possible? diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 1f921936d9..91d710e2a0 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -673,7 +672,6 @@ static void southbridge_inject_dsdt(struct device *dev) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); @@ -682,11 +680,6 @@ static void southbridge_inject_dsdt(struct device *dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); - if (gfx) { - gnvs->ndid = gfx->ndid; - memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - } - #if CONFIG(CHROMEOS) chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 93ebed66ec..08b5ebd8ed 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -75,10 +75,7 @@ typedef struct global_nvs_t { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 rsvd14[3]; - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; + u8 rsvd5[36]; /* Backlight Control */ u8 blcs; /* 0x64 - Backlight Control possible */ u8 brtl; From 28f727b59ba10eec3b3805cc57542643856fbef2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 21:55:21 -0500 Subject: [PATCH 0738/1463] sb/intel/i82801gx: drop IGD-related NVS variables NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: I51a11e7ed6686ab67dac3f02097457ea9c6a7e6a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39953 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 7 ------- src/southbridge/intel/i82801gx/lpc.c | 8 -------- src/southbridge/intel/i82801gx/nvs.h | 5 +---- 3 files changed, 1 insertion(+), 19 deletions(-) diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 4a19de1476..28e79e9f33 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -87,13 +87,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 /* Backlight Control */ Offset (0x64), BLCS, 8, // 0x64 - Backlight control possible? diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index db0dc4198a..ce5d82f3ed 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -642,8 +641,6 @@ static void southbridge_inject_dsdt(struct device *dev) global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - memset(gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; @@ -651,11 +648,6 @@ static void southbridge_inject_dsdt(struct device *dev) acpi_create_gnvs(gnvs); - if (gfx) { - gnvs->ndid = gfx->ndid; - memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - } - /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 6a178d2f3a..0b12d95f00 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -71,10 +71,7 @@ typedef struct { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 rsvd14[3]; - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; + u8 rsvd5[36]; /* Backlight Control */ u8 blcs; /* 0x64 - Backlight Control possible */ u8 brtl; From c19c704c02da663d1def525b07228a843b0962a0 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 21:56:07 -0500 Subject: [PATCH 0739/1463] sb/intel/i82801ix: drop IGD-related NVS variables NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Remove direct setting of gnvs->ndid in qemu-q35 board since build will otherwise break. Change-Id: Ifbf08f43291c1fff7ccbc85272dc97334207983b Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39954 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-q35/acpi_tables.c | 3 --- src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 7 ------- src/southbridge/intel/i82801ix/lpc.c | 7 ------- src/southbridge/intel/i82801ix/nvs.h | 5 +---- 4 files changed, 1 insertion(+), 21 deletions(-) diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 65ff8870fd..793b58e742 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -33,9 +33,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* Enable both COM ports */ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - - /* IGD Displays */ - gnvs->ndid = 0; /* Will use default of 0x00000400. */ } diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 306260e58e..f3a355f71e 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -91,13 +91,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 /* Backlight Control */ Offset (0x64), BLCS, 8, // 0x64 - Backlight control possible? diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 626016402e..f097f50e02 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -33,7 +33,6 @@ #include "i82801ix.h" #include "nvs.h" #include -#include #include #define NMI_OFF 0 @@ -488,15 +487,9 @@ static void southbridge_inject_dsdt(struct device *dev) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - if (gfx) { - gnvs->ndid = gfx->ndid; - memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - } - /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 815186591f..ce2b9a36c7 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -73,10 +73,7 @@ typedef struct { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 rsvd14[3]; - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; + u8 rsvd5[36]; /* Backlight Control */ u8 blcs; /* 0x64 - Backlight Control possible */ u8 brtl; From 93fcf37017d0c4fe39d3f9b52f551c5e1ea907b3 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 21:56:52 -0500 Subject: [PATCH 0740/1463] sb/intel/i82801jx: drop IGD-related NVS variables NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Iecd8559f660cc748c417ec94b7a822e16603cbd8 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39955 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/i82801jx/acpi/globalnvs.asl | 7 ------- src/southbridge/intel/i82801jx/lpc.c | 7 ------- src/southbridge/intel/i82801jx/nvs.h | 5 +---- 3 files changed, 1 insertion(+), 18 deletions(-) diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 7d05ffbe98..8a8b40bb26 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -91,13 +91,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List PADL, 8, // 0x3f - Previously Attached Devices List - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 /* Backlight Control */ Offset (0x64), BLCS, 8, // 0x64 - Backlight control possible? diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 5f02d7469f..652c10db6f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -35,7 +35,6 @@ #include "nvs.h" #include #include -#include #define NMI_OFF 0 @@ -647,15 +646,9 @@ static void southbridge_inject_dsdt(struct device *dev) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - if (gfx) { - gnvs->ndid = gfx->ndid; - memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - } - /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index e9e903711a..0b72113b5d 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -71,10 +71,7 @@ typedef struct { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 rsvd14[3]; - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; + u8 rsvd5[36]; /* Backlight Control */ u8 blcs; /* 0x64 - Backlight Control possible */ u8 brtl; From ae51bb4ba962b6e3a0ae9fea71df530ce4d7999b Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 22:14:07 -0500 Subject: [PATCH 0741/1463] nb/intel/ibexpeak: drop IGD-related NVS variables NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Ibb7898ab4fbbbfcd29b6ba72367cc55a02cd4b1e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39956 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/ibexpeak/lpc.c | 7 ------- src/southbridge/intel/ibexpeak/nvs.h | 5 +---- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 5f7631322b..73f19c7ab7 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -577,7 +576,6 @@ static void southbridge_inject_dsdt(struct device *dev) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); @@ -586,11 +584,6 @@ static void southbridge_inject_dsdt(struct device *dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); - if (gfx) { - gnvs->ndid = gfx->ndid; - memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - } - /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 939b7e4cc8..85d858b025 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -74,10 +74,7 @@ typedef struct global_nvs_t { u8 tlst; /* 0x3d - Display Toggle List Pointer */ u8 cadl; /* 0x3e - currently attached devices */ u8 padl; /* 0x3f - previously attached devices */ - u16 rsvd14[3]; - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; + u8 rsvd5[36]; /* Backlight Control */ u8 blcs; /* 0x64 - Backlight Control possible */ u8 brtl; From 41c4eb5fa686431f9831f337de5e9f3895633d56 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 19:20:54 -0500 Subject: [PATCH 0742/1463] nb/intel/haswell: Simplify GMA SSDT generator Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Icd9caf622dd4c46b13589ebb772138b25888752f Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39948 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/haswell/gma.c | 37 ++++++++++------------------- 1 file changed, 12 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c0eaf6dfdb..4c11bd1c64 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -524,24 +524,11 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) +static void gma_generate_ssdt(struct device *dev) { - struct device *dev = pcidev_on_root(2, 0); - if (!dev) { - return NULL; - } - struct northbridge_intel_haswell_config *chip = dev->chip_info; - return &chip->gfx; -} + const struct northbridge_intel_haswell_config *chip = dev->chip_info; -static void gma_ssdt(struct device *device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) { - return; - } - - drivers_intel_gma_displays_ssdt_generate(gfx); + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, @@ -573,15 +560,15 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gma_func0_init, - .acpi_fill_ssdt = gma_ssdt, - .scan_bus = NULL, - .enable = NULL, - .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .acpi_fill_ssdt = gma_generate_ssdt, + .scan_bus = NULL, + .enable = NULL, + .ops_pci = &gma_pci_ops, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { From 348f9f0ad2e1e8816e78d2931cb50875f15d0276 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 19:30:18 -0500 Subject: [PATCH 0743/1463] nb/intel/sandybridge: Simplify GMA SSDT generator Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: If34ebe0edc46674244c9d5afc7ed165c2ad685ba Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39949 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/gma.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index e79277c392..b68e705b32 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -640,24 +640,11 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) +static void gma_generate_ssdt(struct device *device) { - struct device *dev = pcidev_on_root(2, 0); - if (!dev) { - return NULL; - } - struct northbridge_intel_sandybridge_config *chip = dev->chip_info; - return &chip->gfx; -} + const struct northbridge_intel_sandybridge_config *chip = device->chip_info; -static void gma_ssdt(struct device *device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) { - return; - } - - drivers_intel_gma_displays_ssdt_generate(gfx); + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, @@ -710,7 +697,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = gma_ssdt, + .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, .scan_bus = NULL, .enable = NULL, From 6b059eac5ed0e59cc6f06c1b26413bde67de2658 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 19:31:54 -0500 Subject: [PATCH 0744/1463] nb/intel/ironlake: Simplify GMA SSDT generator Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: I1b6d57c091441aa7431061b1f16135d54cc97b47 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39950 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/ironlake/gma.c | 36 +++++++++------------------- 1 file changed, 11 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index b35305b0c1..6dbc156b98 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -214,25 +214,11 @@ static void gma_read_resources(struct device *dev) res->size = (resource_t) 0x10000000; } -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) +static void gma_generate_ssdt(struct device *device) { - struct device *dev = pcidev_on_root(0x2, 0); - if (!dev) { - return NULL; - } - struct northbridge_intel_ironlake_config *chip = dev->chip_info; - return &chip->gfx; -} + const struct northbridge_intel_ironlake_config *chip = device->chip_info; -static void gma_ssdt(struct device *device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) { - return; - } - - drivers_intel_gma_displays_ssdt_generate(gfx); + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } static unsigned long @@ -266,14 +252,14 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = gma_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = gma_ssdt, - .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = &gma_pci_ops, + .read_resources = gma_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = gma_generate_ssdt, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, .write_acpi_tables = gma_write_acpi_tables, }; From 33f89eea9ff9ebfcdf95b1eaf66daa92edee4969 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 22:16:37 -0500 Subject: [PATCH 0745/1463] nb/intel/x4x: Simplify GMA SSDT generator Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Iacce01ab7d6c220779e84c2b695fbb597b493586 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39957 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/x4x/gma.c | 36 +++++++++++---------------------- 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index ff8820cf28..651b07cf88 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -91,23 +91,11 @@ static void gma_func0_disable(struct device *dev) pci_write_config16(dev_host, D0F0_GGC, ggc); } -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) +static void gma_generate_ssdt(struct device *device) { - struct device *dev = pcidev_on_root(0x2, 0); - if (!dev) - return NULL; - struct northbridge_intel_x4x_config *chip = dev->chip_info; - return &chip->gfx; -} + const struct northbridge_intel_x4x_config *chip = device->chip_info; -static void gma_ssdt(struct device *device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) - return; - - drivers_intel_gma_displays_ssdt_generate(gfx); + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } static unsigned long @@ -146,15 +134,15 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = gma_ssdt, - .init = gma_func0_init, - .ops_pci = &gma_pci_ops, - .disable = gma_func0_disable, - .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = gma_generate_ssdt, + .init = gma_func0_init, + .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { From fd054bc7d46b870a225abffd9f0eb0351dd3c56a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 22:18:45 -0500 Subject: [PATCH 0746/1463] nb/intel/i945: Simplify GMA SSDT generator Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: I68848516fab2058d4aa96ac0342c883fd1df2d6d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39958 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i945/gma.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index c26ffb4bf5..f5a964ab82 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -755,25 +755,11 @@ static void gma_func1_init(struct device *dev) pci_write_config8(dev, 0xf4, 0xff); } -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) +static void gma_generate_ssdt(struct device *device) { - struct device *dev = pcidev_on_root(0x2, 0); - if (!dev) - return NULL; - struct northbridge_intel_i945_config *chip = dev->chip_info; - if (!chip) - return NULL; - return &chip->gfx; -} + const struct northbridge_intel_i945_config *chip = device->chip_info; -static void gma_ssdt(struct device *device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) - return; - - drivers_intel_gma_displays_ssdt_generate(gfx); + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } static void gma_func0_read_resources(struct device *dev) @@ -829,7 +815,7 @@ static struct device_operations gma_func0_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, - .acpi_fill_ssdt = gma_ssdt, + .acpi_fill_ssdt = gma_generate_ssdt, .scan_bus = 0, .enable = 0, .disable = gma_func0_disable, From e91883f5459fa8e8803cb9740bcb5a2cd011a5fb Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 22:20:03 -0500 Subject: [PATCH 0747/1463] nb/intel/gm45: Simplify GMA SSDT generator Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Ideddfc3d327c4421faffb6583e347cd2b094e155 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39959 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/gm45/gma.c | 40 +++++++++++--------------------- 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 821487ad6f..0bbd3d532c 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -219,25 +219,11 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) +static void gma_generate_ssdt(struct device *device) { - struct device *dev = pcidev_on_root(0x2, 0); - if (!dev) { - return NULL; - } - struct northbridge_intel_gm45_config *chip = dev->chip_info; - return &chip->gfx; -} + const struct northbridge_intel_gm45_config *chip = device->chip_info; -static void gma_ssdt(struct device *device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) { - return; - } - - drivers_intel_gma_displays_ssdt_generate(gfx); + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } static unsigned long @@ -276,16 +262,16 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = gma_ssdt, - .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = &gma_pci_ops, - .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = gma_generate_ssdt, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = From affd771ba39772b8ef2cfc44ea2a1a3cac8265a7 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 22:23:07 -0500 Subject: [PATCH 0748/1463] nb/intel/pineview: drop intel_gma_get_controller_info() No longer used by southbridge, no longer needed since pineview doesn't utilize drivers_intel_gma_displays_ssdt_generate() Change-Id: Ia386f8fcd208e201fb8bc2a37cdbecd6f45a044b Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39960 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/gma.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 307529d60b..c0962d78f3 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -289,17 +289,6 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) -{ - struct device *dev = pcidev_on_root(2, 0); - if (!dev) { - printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n"); - return NULL; - } - struct northbridge_intel_pineview_config *chip = dev->chip_info; - return &chip->gfx; -} - static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { From 5bbef4bd1bd0aae84008a2ca6f2cfd205a9e9c8d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 22:25:09 -0500 Subject: [PATCH 0749/1463] mb/emulation/qemu-q35: drop unused intel_gma_get_controller_info() No longer needed anywhere. Change-Id: Ifeea76af44377d917ec46cac0d9d7375d1a68204 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39961 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/emulation/qemu-q35/mainboard.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index aea6d41648..4ccbcd0524 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #define Q35_PAM0 0x90 @@ -25,14 +24,6 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; -struct i915_gpu_controller_info gfx_controller_info = GMA_STATIC_DISPLAYS(0); - -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) -{ - return &gfx_controller_info; -} - static void qemu_nb_init(struct device *dev) { /* Map memory at 0xc0000 - 0xfffff */ From 79b35019a358054d6baf4b5b10b11f3720f78f1e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 22:27:23 -0500 Subject: [PATCH 0750/1463] drivers/intel/gma: drop intel_gma_get_controller_info() Drop function prototype, since all implementations have been removed. Change-Id: I2e7b5ac7352a1434652b5e6d37bb3744c68b2328 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39962 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/intel/gma/i915.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index fc7b35ab83..ff44ac1b60 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -99,8 +99,6 @@ struct i915_gpu_controller_info void drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void); /* vbt.c */ struct device; From 8f42472faaae53b2a271c821b301ba9ed1d2b748 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 27 Nov 2019 22:55:43 -0600 Subject: [PATCH 0751/1463] mb/google/poppy: Add support for ACPI brightness controls Change-Id: Ie7eb4c43178acff2dc5ff7c685e71990d8f353c9 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39945 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/poppy/dsdt.asl | 1 + src/mainboard/google/poppy/variants/atlas/devicetree.cb | 3 +++ src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 3 +++ src/mainboard/google/poppy/variants/nami/devicetree.cb | 3 +++ src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 3 +++ src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 3 +++ src/mainboard/google/poppy/variants/rammus/devicetree.cb | 3 +++ src/mainboard/google/poppy/variants/soraka/devicetree.cb | 3 +++ 8 files changed, 22 insertions(+) diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index dceccc2650..7a21384cfe 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -41,6 +41,7 @@ DefinitionBlock( #include #include #include + #include } } diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 52a2dc765e..b7ab523877 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "200" register "gpu_pp_down_delay_ms" = "50" register "gpu_pp_cycle_delay_ms" = "600" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d9604746dd..77725349e7 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 1b3fdcc410..e4d148c3e2 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 66ceb2d3ac..c3404bf4f8 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 75fcf9c54f..96fcc39e65 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index f44f9ce3ef..65578708ad 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "200" register "gpu_pp_down_delay_ms" = "500" register "gpu_pp_cycle_delay_ms" = "600" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 4711b1f0ae..146d8d2c19 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" From a372f8ae866be5a54f73178a5a1a87daeda378af Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 16:35:41 -0500 Subject: [PATCH 0752/1463] mb/google/beltino: drop ACPI brightness control stub beltino variants are Chromeboxes without built-in displays, so now that default_brightness_levels.asl is no longer required for all boards in a platform, drop it. Change-Id: Ie8147763fc9fdf4f184d3d000bffd6794e134d9e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39946 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/beltino/dsdt.asl | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index f494d2fd79..da11fed342 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -38,8 +38,6 @@ DefinitionBlock( { #include #include - - #include } } From c72f5f74a890ddd20e7849fce7d693a1fdd6da66 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 28 Jan 2018 18:42:10 -0600 Subject: [PATCH 0753/1463] soc/intel/baytrail: add ACPI backlight support Add hook to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0b7fc45bda3aaf89306bedb579fb1e9f8ce07926 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39942 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/baytrail/chip.h | 3 +++ src/soc/intel/baytrail/gfx.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 0fa7eafe87..52b1e33851 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -18,6 +18,7 @@ #ifndef _BAYTRAIL_CHIP_H_ #define _BAYTRAIL_CHIP_H_ +#include #include struct soc_intel_baytrail_config { @@ -84,6 +85,8 @@ struct soc_intel_baytrail_config { uint16_t gpu_pipeb_power_cycle_delay; int gpu_pipeb_pwm_freq_hz; int disable_ddr_2x_refresh_rate; + + struct i915_gpu_controller_info gfx; }; #endif /* _BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 417f36e907..e4ed6f37d5 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -397,6 +397,13 @@ static void gfx_init(struct device *dev) intel_gma_restore_opregion(); } +static void gma_generate_ssdt(struct device *dev) +{ + const struct soc_intel_baytrail_config *chip = dev->chip_info; + + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); +} + static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, @@ -430,6 +437,7 @@ static struct device_operations gfx_device_ops = { .init = gfx_init, .ops_pci = &soc_pci_ops, .write_acpi_tables = gma_write_acpi_tables, + .acpi_fill_ssdt = gma_generate_ssdt, }; static const struct pci_driver gfx_driver __pci_driver = { From 8ff2ecd3448fa47dfad3753bd5a50917e2b86f61 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 29 Mar 2020 16:58:48 -0500 Subject: [PATCH 0754/1463] soc/intel/braswell: add ACPI backlight support Add hook to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0adccc6c8bee71d3c1b7840518308c8dc8ea2d81 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39943 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/braswell/chip.h | 3 +++ src/soc/intel/braswell/gfx.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 026e491006..5f1aaee3be 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -21,6 +21,7 @@ #define _SOC_CHIP_H_ #include +#include #include #include #include @@ -169,6 +170,8 @@ struct soc_intel_braswell_config { uint8_t I2C4Frequency; uint8_t I2C5Frequency; uint8_t I2C6Frequency; + + struct i915_gpu_controller_info gfx; }; #endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index ff73955d7a..12fe6427f0 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -87,12 +88,20 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) gnvs_ptr->aslb = aslb; } +static void gma_generate_ssdt(struct device *dev) +{ + const struct soc_intel_braswell_config *chip = dev->chip_info; + + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); +} + static struct device_operations gfx_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init, .ops_pci = &soc_pci_ops, + .acpi_fill_ssdt = gma_generate_ssdt, }; static const struct pci_driver gfx_driver __pci_driver = { From b54c5168bd1e82deee9f2bb0019490c167a66daf Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 13:20:10 +0200 Subject: [PATCH 0755/1463] Doc/mb/index.md: Fix mainboard vendor order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Oops, Libretrend "stole" all the Thinkpads from Lenovo. Correct that. Change-Id: I15f189dedab98fdbea8c26ceb8ac84486df2519b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40118 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- Documentation/mainboard/index.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 99e5dd0b1d..7637f7bcbe 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -75,10 +75,6 @@ The boards in this section are not real mainboards, but emulators. - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) -## Libretrend - -- [LT1000](libretrend/lt1000.md) - ### Arrandale series - [T410](lenovo/t410.md) @@ -107,6 +103,10 @@ The boards in this section are not real mainboards, but emulators. - [T440p](lenovo/t440p.md) +## Libretrend + +- [LT1000](libretrend/lt1000.md) + ## MSI - [MS-7707](msi/ms7707/ms7707.md) From ae01122b57eed272d6a10013b4686826dbfb95be Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 13:21:45 -0500 Subject: [PATCH 0756/1463] mb/google/auron: Convert variants to use override devicetree Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. As part of the cleanup, drop unused PCIe RP5 for buddy as well. Test: build all auron variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39940 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/auron/Kconfig | 4 +- .../{variants/auron_paine => }/devicetree.cb | 38 +++--- .../variants/auron_paine/overridetree.cb | 16 +++ .../auron/variants/auron_yuna/devicetree.cb | 103 ---------------- .../auron/variants/auron_yuna/overridetree.cb | 16 +++ .../google/auron/variants/buddy/devicetree.cb | 110 ------------------ .../auron/variants/buddy/overridetree.cb | 39 +++++++ .../auron/variants/gandof/devicetree.cb | 103 ---------------- .../auron/variants/gandof/overridetree.cb | 16 +++ .../google/auron/variants/lulu/devicetree.cb | 104 ----------------- .../auron/variants/lulu/overridetree.cb | 16 +++ .../google/auron/variants/samus/devicetree.cb | 107 ----------------- .../auron/variants/samus/overridetree.cb | 40 +++++++ 13 files changed, 158 insertions(+), 554 deletions(-) rename src/mainboard/google/auron/{variants/auron_paine => }/devicetree.cb (67%) create mode 100644 src/mainboard/google/auron/variants/auron_paine/overridetree.cb delete mode 100644 src/mainboard/google/auron/variants/auron_yuna/devicetree.cb create mode 100644 src/mainboard/google/auron/variants/auron_yuna/overridetree.cb delete mode 100644 src/mainboard/google/auron/variants/buddy/devicetree.cb create mode 100644 src/mainboard/google/auron/variants/buddy/overridetree.cb delete mode 100644 src/mainboard/google/auron/variants/gandof/devicetree.cb create mode 100644 src/mainboard/google/auron/variants/gandof/overridetree.cb delete mode 100644 src/mainboard/google/auron/variants/lulu/devicetree.cb create mode 100644 src/mainboard/google/auron/variants/lulu/overridetree.cb delete mode 100644 src/mainboard/google/auron/variants/samus/devicetree.cb create mode 100644 src/mainboard/google/auron/variants/samus/overridetree.cb diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 644104a37e..20d2e440c2 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -48,9 +48,9 @@ config MAINBOARD_PART_NUMBER default "Lulu" if BOARD_GOOGLE_LULU default "Samus" if BOARD_GOOGLE_SAMUS -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config EC_GOOGLE_CHROMEEC_BOARDNAME string diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/devicetree.cb similarity index 67% rename from src/mainboard/google/auron/variants/auron_paine/devicetree.cb rename to src/mainboard/google/auron/devicetree.cb index f6ec15a617..cabcdf0c4b 100644 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -12,14 +12,6 @@ chip soc/intel/broadwell # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x8a" register "pirqc_routing" = "0x8b" @@ -44,10 +36,6 @@ chip soc/intel/broadwell register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - # Force enable ASPM for PCIe Port1 register "pcie_port_force_aspm" = "0x01" @@ -61,32 +49,32 @@ chip soc/intel/broadwell end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 device pci 15.3 off end # GSPI0 device pci 15.4 off end # GSPI1 device pci 15.5 off end # UART0 device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT device pci 17.0 off end # SDIO device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI + device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm @@ -96,8 +84,8 @@ chip soc/intel/broadwell device pnp 0c09.0 on end end end # LPC bridge - device pci 1f.2 on end # SATA Controller + device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal + device pci 1f.6 on end # Thermal end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb new file mode 100644 index 0000000000..70b1ebd552 --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -0,0 +1,16 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "70" # 7ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on end +end diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb deleted file mode 100644 index db02565b27..0000000000 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ /dev/null @@ -1,103 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - register "s0ix_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb new file mode 100644 index 0000000000..67b9131c65 --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -0,0 +1,16 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on end +end diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb deleted file mode 100644 index e12882f413..0000000000 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ /dev/null @@ -1,110 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - - register "s0ix_enable" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 on end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb new file mode 100644 index 0000000000..f814280b15 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -0,0 +1,39 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "70" # 7ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + register "sata_devslp_disable" = "0x1" + + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + register "s0ix_enable" = "0" + + device domain 0 on + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb deleted file mode 100644 index 230f5bd009..0000000000 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ /dev/null @@ -1,103 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "500" # 50ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - register "s0ix_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb new file mode 100644 index 0000000000..e35d3a5529 --- /dev/null +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -0,0 +1,16 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "500" # 50ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on end +end diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb deleted file mode 100644 index 1983045983..0000000000 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - - register "sio_acpi_mode" = "1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - register "s0ix_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb new file mode 100644 index 0000000000..70b1ebd552 --- /dev/null +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -0,0 +1,16 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "70" # 7ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on end +end diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb deleted file mode 100644 index 434ecc80b9..0000000000 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ /dev/null @@ -1,107 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DDI1 Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Enable DDI2 Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_port0_gen3_tx" = "0x72" - register "sio_acpi_mode" = "1" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" - - # Disable S0ix for now - register "s0ix_enable" = "0" - - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 on end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 on end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb new file mode 100644 index 0000000000..93e96cac3f --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -0,0 +1,40 @@ +chip soc/intel/broadwell + + # Enable DDI2 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms + register "gpu_panel_power_up_delay" = "2000" # 200ms + register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + # Disable S0ix for now + register "s0ix_enable" = "0" + + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" + + device domain 0 on + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI + end +end From e4c784bd0d91fe0bf4e0e8e5b0c9fa173235cea6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 31 Mar 2020 00:28:57 +0200 Subject: [PATCH 0757/1463] soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are boards that do not need a specific domain_vr_config because the defaults provided by the soc code are sufficient. Currently, this means that these boards can't benefit from lower power states (PSI 3 and 4) because the settings default to being disabled since at the time the defaults have been defined (2015) there were bugs in FSP in this regard. Set the default values of psiXenable to 1 for boards that do not have a domain_vr_config setting in their devicetree, just like Cannon Lake does. Boards that have a domain_vr_config and set their specific settings are not affected at all. Currently, there are only three boards that have no domain_vr_config: - supermicro/x11-lga1151-series These boards have a MPS MP2955 which we can assume support for PS3 (the MP2965 and MP2935 support it, too). S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and since only C10 makes use of PS4, those CPUs won't ever request PS4. That means we do not need to disable it explicitly for these boards. - 51nb/x210: Needs testing and/or VR datasheet check for PS3/PS4 support Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980 Reviewed-by: Matt DeVillier Reviewed-by: Benjamin Doron Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/vr_config.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 98d2513ec5..57c55eca76 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -21,15 +21,15 @@ #include #include -/* Default values for domain configuration. PSI3 and PSI4 are disabled. */ +/* Default values for domain configuration. */ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { [VR_SYSTEM_AGENT] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, @@ -40,8 +40,8 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, @@ -52,8 +52,8 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, @@ -64,8 +64,8 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, From d957d12e6dbf2eb912904f8cda7f9138a2ac314e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 31 Mar 2020 12:18:44 -0500 Subject: [PATCH 0758/1463] mb/google/glados: clean up variant devicetrees In preparation for conversion to overridetree format, clean up the variant devicetrees in order to minimize the differences across glados variants. This entails: - minor reformatting and reordering of devicetree entries - addition of setting default values on boards which skipped them - disabling unused I2C2 on boards which left it enabled - ensuring TCC offset set for all SKL-Y boards - setting VR mailbox command 1 for caroline - skipping init for UART2 on cave and glados - dropping unused PCIe RP5 for sentry Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39981 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../glados/variants/asuka/devicetree.cb | 15 +++++++-- .../glados/variants/caroline/devicetree.cb | 24 ++++++++++---- .../google/glados/variants/cave/devicetree.cb | 7 ++-- .../glados/variants/chell/devicetree.cb | 13 +++++--- .../glados/variants/glados/devicetree.cb | 12 ++++--- .../google/glados/variants/lars/devicetree.cb | 19 +++++++++-- .../glados/variants/sentry/devicetree.cb | 33 ++++++++++++++----- 7 files changed, 92 insertions(+), 31 deletions(-) diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index 772584dc3c..e1e68caff7 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -34,13 +34,23 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" register "SmbusEnable" = "1" + register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -146,8 +156,6 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -163,6 +171,9 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 25W register "tdp_pl2_override" = "25" diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 6314af8661..00b29b7699 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -61,8 +61,14 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - # TCC offset - register "tcc_offset" = "10" + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" # VR Slew rate setting for improving audible noise register "AcousticNoiseMitigation" = "1" @@ -137,7 +143,7 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -160,7 +166,7 @@ chip soc/intel/skylake register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, @@ -177,9 +183,15 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + + # TCC of 90C + register "tcc_offset" = "10" + # Lock Down register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" device cpu_cluster 0 on @@ -208,7 +220,7 @@ chip soc/intel/skylake device i2c 4a on end end end # I2C #1 - device pci 15.2 on end # I2C #2 + device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 1d04a8e714..41bb82e053 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -167,7 +167,7 @@ chip soc/intel/skylake [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # I2C4 is 1.8V @@ -176,11 +176,12 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" - register "tcc_offset" = "10" # TCC of 90C - # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # TCC of 90C + register "tcc_offset" = "10" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index 89f1c08b75..c0fb07c7ef 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -136,7 +136,7 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -155,7 +155,6 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ @@ -172,17 +171,21 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 15W register "tdp_pl2_override" = "15" - register "tcc_offset" = "10" # TCC of 90C - # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # TCC of 90C + register "tcc_offset" = "10" + # Lock Down register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" device cpu_cluster 0 on diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index 20166253c9..d63d9c12e5 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -136,7 +136,7 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -155,8 +155,6 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2 - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -169,15 +167,21 @@ chip soc/intel/skylake [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 15W register "tdp_pl2_override" = "15" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # TCC of 90C + register "tcc_offset" = "10" + # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 76e614d423..419d14026c 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -9,6 +9,8 @@ chip soc/intel/skylake register "gpu_pch_backlight_pwm_hz" = "1000" # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" @@ -32,13 +34,23 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" register "SmbusEnable" = "1" + register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -124,7 +136,7 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -143,8 +155,6 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -160,6 +170,9 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 25W register "tdp_pl2_override" = "25" diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 3e2137bb58..57586fb38e 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -34,13 +34,23 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" register "SmbusEnable" = "1" + register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" + register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -126,14 +136,18 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - # Enable Root port 1 and 5. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" + + # Enable Root port 5 + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # RP 5 uses SRCCLKREQ2# register "PcieRpClkReqNumber[4]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 @@ -148,9 +162,6 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # I2C0 is 3.3V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -166,6 +177,12 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C0 is 3.3V + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 25W register "tdp_pl2_override" = "25" @@ -263,7 +280,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 From e7dc4f40ef2220649e0c9a9872941a23fba3c18e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 31 Mar 2020 13:10:52 -0500 Subject: [PATCH 0759/1463] mb/google/glados: drop VR configs from devicetree The VR config values used in the variants' devicetrees is identical to the domain defaults in vr_config.c, with the exception of the icc_max value, which is calculated dynamically based on SKU, and again matches the default values for each domain and each varaint. Test: add a print function to dump the VR config values for each domain from the UPDs after setting, verify same output before/after. Change-Id: I4307f6e19ae6f99d4f5e475b181fd66c5b92f28c Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39982 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../glados/variants/asuka/devicetree.cb | 66 ----------------- .../glados/variants/caroline/devicetree.cb | 66 ----------------- .../google/glados/variants/cave/devicetree.cb | 66 ----------------- .../glados/variants/chell/devicetree.cb | 66 ----------------- .../glados/variants/glados/devicetree.cb | 66 ----------------- .../google/glados/variants/lars/devicetree.cb | 66 ----------------- .../glados/variants/sentry/devicetree.cb | 73 ------------------- 7 files changed, 469 deletions(-) diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index e1e68caff7..395b5728b7 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -70,72 +70,6 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 00b29b7699..3e733d6b1c 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -77,72 +77,6 @@ chip soc/intel/skylake register "SlowSlewRateForSa" = "0" # Fast/2 register "FastPkgCRampDisable" = "0" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(4), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 41bb82e053..ccc2302a58 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -70,72 +70,6 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(4), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index c0fb07c7ef..bbc74f8d97 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -70,72 +70,6 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(4), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index d63d9c12e5..9cd5ac986f 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -70,72 +70,6 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 419d14026c..35ce9a0294 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -70,72 +70,6 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 57586fb38e..502aad04ea 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -70,72 +70,6 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - }" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# @@ -143,13 +77,6 @@ chip soc/intel/skylake # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # Enable Root port 5 - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # RP 5 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth From 0d58e64ddfc9bb7f1badaca3930c484a0e16245c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 31 Mar 2020 13:12:22 -0500 Subject: [PATCH 0760/1463] mb/google/glados: convert to overridetree Simplify glados variants by converting to overridetree format. Change-Id: I6dd7a4b1ae7f1d3ce9fadb06ea95e021a1c880a5 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39983 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/glados/Kconfig | 4 +- .../glados/{variants/lars => }/devicetree.cb | 67 +---- .../glados/variants/asuka/devicetree.cb | 227 ---------------- .../glados/variants/asuka/overridetree.cb | 66 +++++ .../glados/variants/caroline/devicetree.cb | 241 ----------------- .../glados/variants/caroline/overridetree.cb | 91 +++++++ .../google/glados/variants/cave/devicetree.cb | 232 ---------------- .../glados/variants/cave/overridetree.cb | 83 ++++++ .../glados/variants/chell/devicetree.cb | 228 ---------------- .../glados/variants/chell/overridetree.cb | 73 +++++ .../glados/variants/glados/devicetree.cb | 234 ---------------- .../glados/variants/glados/overridetree.cb | 84 ++++++ .../glados/variants/lars/overridetree.cb | 67 +++++ .../glados/variants/sentry/devicetree.cb | 249 ------------------ .../glados/variants/sentry/overridetree.cb | 91 +++++++ 15 files changed, 562 insertions(+), 1475 deletions(-) rename src/mainboard/google/glados/{variants/lars => }/devicetree.cb (69%) delete mode 100644 src/mainboard/google/glados/variants/asuka/devicetree.cb create mode 100644 src/mainboard/google/glados/variants/asuka/overridetree.cb delete mode 100644 src/mainboard/google/glados/variants/caroline/devicetree.cb create mode 100644 src/mainboard/google/glados/variants/caroline/overridetree.cb delete mode 100644 src/mainboard/google/glados/variants/cave/devicetree.cb create mode 100644 src/mainboard/google/glados/variants/cave/overridetree.cb delete mode 100644 src/mainboard/google/glados/variants/chell/devicetree.cb create mode 100644 src/mainboard/google/glados/variants/chell/overridetree.cb delete mode 100644 src/mainboard/google/glados/variants/glados/devicetree.cb create mode 100644 src/mainboard/google/glados/variants/glados/overridetree.cb create mode 100644 src/mainboard/google/glados/variants/lars/overridetree.cb delete mode 100644 src/mainboard/google/glados/variants/sentry/devicetree.cb create mode 100644 src/mainboard/google/glados/variants/sentry/overridetree.cb diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index d0ff3776e0..5e3545a85c 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -60,9 +60,9 @@ config VARIANT_DIR default "lars" if BOARD_GOOGLE_LARS default "sentry" if BOARD_GOOGLE_SENTRY -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAX_CPUS int diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/devicetree.cb similarity index 69% rename from src/mainboard/google/glados/variants/lars/devicetree.cb rename to src/mainboard/google/glados/devicetree.cb index 35ce9a0294..e9c1cac69c 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -77,18 +77,6 @@ chip soc/intel/skylake # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # SD - register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -127,23 +115,8 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 @@ -154,30 +127,7 @@ chip soc/intel/skylake device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "1" - register "jkdet_pull_up" = "1" - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x08" - register "sar_threshold[1]" = "0x12" - register "sar_threshold[2]" = "0x26" - register "sar_threshold[3]" = "0x73" - register "sar_hysteresis" = "0" - register "sar_voltage" = "6" - register "sar_compare_time" = "1" # 1us - register "sar_sampling_time" = "1" # 4us - register "short_key_debounce" = "3" # 30ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "0" - device i2c 1a on end - end - end # I2C #4 + device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" @@ -201,7 +151,7 @@ chip soc/intel/skylake device pci 1e.3 off end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard + device pci 1e.6 off end # SDCard device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end @@ -212,14 +162,7 @@ chip soc/intel/skylake end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb deleted file mode 100644 index 395b5728b7..0000000000 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ /dev/null @@ -1,227 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" - - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "4" # 4s - register "PmConfigSlpSusMinAssert" = "3" # 4s - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board) - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU - register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - - # PL2 override 25W - register "tdp_pl2_override" = "25" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "0" # R389 - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x08" - register "sar_threshold[1]" = "0x12" - register "sar_threshold[2]" = "0x26" - register "sar_threshold[3]" = "0x73" - register "sar_hysteresis" = "0" - register "sar_voltage" = "6" - register "sar_compare_time" = "1" # 1us - register "sar_sampling_time" = "1" # 4us - register "short_key_debounce" = "3" # 30ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "0" - device i2c 1a on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/glados/variants/asuka/overridetree.cb b/src/mainboard/google/glados/variants/asuka/overridetree.cb new file mode 100644 index 0000000000..4be1fc6ae3 --- /dev/null +++ b/src/mainboard/google/glados/variants/asuka/overridetree.cb @@ -0,0 +1,66 @@ +chip soc/intel/skylake + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU + register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 10 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" # R389 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" + register "sar_threshold[2]" = "0x26" + register "sar_threshold[3]" = "0x73" + register "sar_hysteresis" = "0" + register "sar_voltage" = "6" + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us + register "short_key_debounce" = "3" # 30ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "0" + device i2c 1a on end + end + end # I2C #4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb deleted file mode 100644 index 3e733d6b1c..0000000000 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ /dev/null @@ -1,241 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" - - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # VR Slew rate setting for improving audible noise - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "3" # Fast/16 - register "SlowSlewRateForGt" = "3" # Fast/16 - register "SlowSlewRateForSa" = "0" # Fast/2 - register "FastPkgCRampDisable" = "0" - - # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main) - register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub) - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - - # PL2 override 15W - register "tdp_pl2_override" = "15" - - # Send an extra VR mailbox command for the supported MPS IMVP8 model - register "SendVrMbxCmd" = "1" - - # TCC of 90C - register "tcc_offset" = "10" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ATML0001"" - register "desc" = ""Atmel Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 4b on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ATML0000"" - register "desc" = ""Atmel Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 4a on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "0" # R389 - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x0c" - register "sar_threshold[1]" = "0x1c" - register "sar_threshold[2]" = "0x38" - register "sar_threshold[3]" = "0x60" - register "sar_hysteresis" = "1" - register "sar_voltage" = "0" # VDDA - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us - register "short_key_debounce" = "2" # 100ms - register "jack_insert_debounce" = "4" # 64ms - register "jack_eject_debounce" = "4" # 64ms - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb new file mode 100644 index 0000000000..ce364801ca --- /dev/null +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -0,0 +1,91 @@ +chip soc/intel/skylake + + register "ScsSdCardEnabled" = "2" + + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + + # VR Slew rate setting for improving audible noise + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "3" # Fast/16 + register "SlowSlewRateForGt" = "3" # Fast/16 + register "SlowSlewRateForSa" = "0" # Fast/2 + register "FastPkgCRampDisable" = "0" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main) + register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub) + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + + # PL2 override 15W + register "tdp_pl2_override" = "15" + + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + + # TCC of 90C + register "tcc_offset" = "10" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ATML0001"" + register "desc" = ""Atmel Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 4b on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ATML0000"" + register "desc" = ""Atmel Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 4a on end + end + end # I2C #1 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" # R389 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "4" # 64ms + register "jack_eject_debounce" = "4" # 64ms + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + device i2c 35 on end + end + end # I2C #4 + device pci 1e.6 on end # SDCard + end +end diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb deleted file mode 100644 index ccc2302a58..0000000000 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ /dev/null @@ -1,232 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" - - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board) - register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Type-A Port 1 - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A Port 2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex) - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2 - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - - # PL2 override 15W - register "tdp_pl2_override" = "15" - - # Send an extra VR mailbox command for the supported MPS IMVP8 model - register "SendVrMbxCmd" = "1" - - # TCC of 90C - register "tcc_offset" = "10" - - # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "0" # R389 - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x0c" - register "sar_threshold[1]" = "0x1e" - register "sar_threshold[2]" = "0x38" - register "sar_threshold[3]" = "0x60" - register "sar_hysteresis" = "1" - register "sar_voltage" = "0" # VDDA - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us - register "short_key_debounce" = "2" # 100ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "7" # 512ms - device i2c 1a on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb new file mode 100644 index 0000000000..ae32b3dabf --- /dev/null +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -0,0 +1,83 @@ +chip soc/intel/skylake + + register "ScsSdCardEnabled" = "2" + + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board) + register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Type-A Port 1 + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A Port 2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex) + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2 + + # PL2 override 15W + register "tdp_pl2_override" = "15" + + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + + # TCC of 90C + register "tcc_offset" = "10" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_A7" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 10 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" # R389 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1e" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + end # I2C #4 + device pci 1e.6 on end # SDCard + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb deleted file mode 100644 index bbc74f8d97..0000000000 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ /dev/null @@ -1,228 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" - - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - - # PL2 override 15W - register "tdp_pl2_override" = "15" - - # Send an extra VR mailbox command for the supported MPS IMVP8 model - register "SendVrMbxCmd" = "1" - - # TCC of 90C - register "tcc_offset" = "10" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "0" # R389 - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x0c" - register "sar_threshold[1]" = "0x1c" - register "sar_threshold[2]" = "0x38" - register "sar_threshold[3]" = "0x60" - register "sar_hysteresis" = "1" - register "sar_voltage" = "0" # VDDA - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us - register "short_key_debounce" = "2" # 100ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "7" # 512ms - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb new file mode 100644 index 0000000000..c6ccd208aa --- /dev/null +++ b/src/mainboard/google/glados/variants/chell/overridetree.cb @@ -0,0 +1,73 @@ +chip soc/intel/skylake + + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD + + # PL2 override 15W + register "tdp_pl2_override" = "15" + + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + + # TCC of 90C + register "tcc_offset" = "10" + + device domain 0 on + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" # R389 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + device i2c 35 on end + end + end # I2C #4 + end +end diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb deleted file mode 100644 index 9cd5ac986f..0000000000 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ /dev/null @@ -1,234 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" - - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port (board) - register "usb2_ports[1]" = "USB2_PORT_MAX(OC3)" # Type-C Port (flex) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port 1 - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC1)" # Type-A Port 2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port (board) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port (flex) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2 - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - - # PL2 override 15W - register "tdp_pl2_override" = "15" - - # Send an extra VR mailbox command for the supported MPS IMVP8 model - register "SendVrMbxCmd" = "1" - - # TCC of 90C - register "tcc_offset" = "10" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "0" # R389 - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x0c" - register "sar_threshold[1]" = "0x1e" - register "sar_threshold[2]" = "0x38" - register "sar_threshold[3]" = "0x60" - register "sar_hysteresis" = "1" - register "sar_voltage" = "0" # VDDA - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us - register "short_key_debounce" = "2" # 100ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "7" # 512ms - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb new file mode 100644 index 0000000000..1bc69abb17 --- /dev/null +++ b/src/mainboard/google/glados/variants/glados/overridetree.cb @@ -0,0 +1,84 @@ +chip soc/intel/skylake + + register "ScsSdCardEnabled" = "2" + + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port (board) + register "usb2_ports[1]" = "USB2_PORT_MAX(OC3)" # Type-C Port (flex) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port 1 + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC1)" # Type-A Port 2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port (board) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port (flex) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2 + + # PL2 override 15W + register "tdp_pl2_override" = "15" + + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + + # TCC of 90C + register "tcc_offset" = "10" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 10 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" # R389 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1e" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + device i2c 35 on end + end + end # I2C #4 + device pci 1e.6 on end # SDCard + end +end diff --git a/src/mainboard/google/glados/variants/lars/overridetree.cb b/src/mainboard/google/glados/variants/lars/overridetree.cb new file mode 100644 index 0000000000..ce32b6b0c9 --- /dev/null +++ b/src/mainboard/google/glados/variants/lars/overridetree.cb @@ -0,0 +1,67 @@ +chip soc/intel/skylake + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # SD + register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 10 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "1" + register "jkdet_pull_up" = "1" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" + register "sar_threshold[2]" = "0x26" + register "sar_threshold[3]" = "0x73" + register "sar_hysteresis" = "0" + register "sar_voltage" = "6" + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us + register "short_key_debounce" = "3" # 30ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "0" + device i2c 1a on end + end + end # I2C #4 + device pci 1e.6 off end # SDCard + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb deleted file mode 100644 index 502aad04ea..0000000000 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ /dev/null @@ -1,249 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" - - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "4" # 4s - register "PmConfigSlpSusMinAssert" = "3" # 4s - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Enable Root port 1 - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # I2C0 is 3.3V - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" - - # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - - # PL2 override 25W - register "tdp_pl2_override" = "25" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - - # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""RAYD0001"" - register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 39 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "1" - register "jkdet_pull_up" = "1" - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x08" - register "sar_threshold[1]" = "0x12" - register "sar_threshold[2]" = "0x26" - register "sar_threshold[3]" = "0x73" - register "sar_hysteresis" = "0" - register "sar_voltage" = "6" - register "sar_compare_time" = "1" # 1us - register "sar_sampling_time" = "1" # 4us - register "short_key_debounce" = "3" # 30ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "0" - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - register "device_present_gpio" = "GPP_E3" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - register "device_present_gpio" = "GPP_E3" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" - register "device_present_gpio" = "GPP_E3" - register "device_present_gpio_invert" = "1" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/glados/variants/sentry/overridetree.cb b/src/mainboard/google/glados/variants/sentry/overridetree.cb new file mode 100644 index 0000000000..08d3dd3aba --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/overridetree.cb @@ -0,0 +1,91 @@ +chip soc/intel/skylake + + register "ScsSdCardEnabled" = "2" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) + + # I2C0 is 3.3V + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_A7" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 39 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "1" + register "jkdet_pull_up" = "1" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" + register "sar_threshold[2]" = "0x26" + register "sar_threshold[3]" = "0x73" + register "sar_hysteresis" = "0" + register "sar_voltage" = "6" + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us + register "short_key_debounce" = "3" # 30ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "0" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + register "device_present_gpio" = "GPP_E3" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + register "device_present_gpio" = "GPP_E3" + device i2c 35 on end + end + end # I2C #4 + device pci 1e.6 on end # SDCard + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" + register "device_present_gpio" = "GPP_E3" + register "device_present_gpio_invert" = "1" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end +end From 8fbfcc3a06d2dde8aa625db123b42cfe29aa0752 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 23:20:32 -0500 Subject: [PATCH 0761/1463] mb/google/cyan: convert to overridetree Simply cyan variants by converting to overridetree format. A few differences were ignored as there appears to be no reason behind them: - cyan had PCIe RP2 enabled, but nothing is attached to it - kefka had the SPI 1 device disabled - reks, relm, and ultima had HSUART 1 disabled - edgar had I2C1 UPD disabled Test: build/boot cyan and edgar variants, verify everything still works Change-Id: I9928cc59adcfda4661ddfdfa95f53a7820053b4a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39964 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/cyan/Kconfig | 4 +- .../cyan/{variants/terra => }/devicetree.cb | 53 +++---- .../google/cyan/variants/banon/devicetree.cb | 146 ----------------- .../cyan/variants/banon/overridetree.cb | 26 ++++ .../google/cyan/variants/celes/devicetree.cb | 140 ----------------- .../cyan/variants/celes/overridetree.cb | 8 + .../google/cyan/variants/cyan/devicetree.cb | 139 ----------------- .../google/cyan/variants/cyan/overridetree.cb | 18 +++ .../google/cyan/variants/edgar/devicetree.cb | 140 ----------------- .../cyan/variants/edgar/overridetree.cb | 32 ++++ .../google/cyan/variants/kefka/devicetree.cb | 146 ----------------- .../cyan/variants/kefka/overridetree.cb | 8 + .../google/cyan/variants/reks/devicetree.cb | 137 ---------------- .../google/cyan/variants/reks/overridetree.cb | 29 ++++ .../google/cyan/variants/relm/devicetree.cb | 146 ----------------- .../google/cyan/variants/relm/overridetree.cb | 8 + .../google/cyan/variants/setzer/devicetree.cb | 146 ----------------- .../cyan/variants/setzer/overridetree.cb | 10 ++ .../cyan/variants/terra/overridetree.cb | 5 + .../google/cyan/variants/ultima/devicetree.cb | 140 ----------------- .../cyan/variants/ultima/overridetree.cb | 11 ++ .../google/cyan/variants/wizpig/devicetree.cb | 147 ------------------ .../cyan/variants/wizpig/overridetree.cb | 32 ++++ 23 files changed, 216 insertions(+), 1455 deletions(-) rename src/mainboard/google/cyan/{variants/terra => }/devicetree.cb (74%) delete mode 100644 src/mainboard/google/cyan/variants/banon/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/banon/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/celes/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/celes/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/cyan/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/cyan/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/edgar/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/edgar/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/kefka/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/kefka/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/reks/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/reks/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/relm/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/relm/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/setzer/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/setzer/overridetree.cb create mode 100644 src/mainboard/google/cyan/variants/terra/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/ultima/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/ultima/overridetree.cb delete mode 100644 src/mainboard/google/cyan/variants/wizpig/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/wizpig/overridetree.cb diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 45610542e4..92bafee514 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -68,9 +68,9 @@ config MAINBOARD_PART_NUMBER default "Ultima" if BOARD_GOOGLE_ULTIMA default "Wizpig" if BOARD_GOOGLE_WIZPIG -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config CBFS_SIZE hex diff --git a/src/mainboard/google/cyan/variants/terra/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb similarity index 74% rename from src/mainboard/google/cyan/variants/terra/devicetree.cb rename to src/mainboard/google/cyan/devicetree.cb index d7d0f1f7e8..328a60817e 100644 --- a/src/mainboard/google/cyan/variants/terra/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -27,12 +27,12 @@ chip soc/intel/braswell register "PcdEnableLpe" = "1" register "PcdEnableDma0" = "1" register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "0" - register "PcdEnableI2C1" = "1" + register "PcdEnableI2C0" = "0" # Touchscreen + register "PcdEnableI2C1" = "1" # PMIC (or Maxim Audio) register "PcdEnableI2C2" = "0" register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" + register "PcdEnableI2C4" = "1" # Realtek Audio + register "PcdEnableI2C5" = "1" # Touchpad register "PcdEnableI2C6" = "0" register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" @@ -67,13 +67,14 @@ chip soc/intel/braswell register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "1" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect + register "I2C0Frequency" = "1" - register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz + register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz register "I2C2Frequency" = "1" register "I2C3Frequency" = "1" register "I2C4Frequency" = "1" @@ -100,37 +101,37 @@ chip soc/intel/braswell end device domain 0 on # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port + device pci 0b.0 on end # 8086 22dc - Signal Processing Controller + device pci 10.0 on end # 8086 2294 - MMC Port device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port + device pci 12.0 on end # 8086 0F16 - SD Port device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 14.0 on end # 8086 22b5 - USB XHCI + device pci 15.0 on end # 8086 22a8 - LP Engine Audio device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 off end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1: Touchscreen + device pci 18.2 on end # 8086 22c2 - I2C Port 2: PMIC device pci 18.3 off end # 8086 22c3 - I2C Port 3 device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.5 on end # 8086 22c5 - I2C Port 5: Realtek Audio + device pci 18.6 on end # 8086 22c6 - I2C Port 6: Touchpad device pci 18.7 off end # 8086 22c7 - I2C Port 7 device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 off end # 8086 22ca - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3: WiFi + device pci 1c.3 off end # 8086 22ce - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA device pci 1e.1 off end # 8086 0F08 - PWM 1 device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.3 on end # 8086 228a - HSUART 1 device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.5 on end # 8086 228e - SPI 1 device pci 1e.6 off end # 8086 2290 - SPI 2 device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge diff --git a/src/mainboard/google/cyan/variants/banon/devicetree.cb b/src/mainboard/google/cyan/variants/banon/devicetree.cb deleted file mode 100644 index 60076c2171..0000000000 --- a/src/mainboard/google/cyan/variants/banon/devicetree.cb +++ /dev/null @@ -1,146 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "0" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "6" - register "Usb2Port0IUsbTxEmphasisEn" = "3" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "6" - register "Usb2Port1IUsbTxEmphasisEn" = "3" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "6" - register "Usb2Port2IUsbTxEmphasisEn" = "3" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "6" - register "Usb2Port3IUsbTxEmphasisEn" = "3" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "6" - register "Usb2Port4IUsbTxEmphasisEn" = "3" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - register "I2C0Frequency" = "1" - register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz - register "I2C2Frequency" = "1" - register "I2C3Frequency" = "1" - register "I2C4Frequency" = "1" - register "I2C5Frequency" = "1" - register "I2C6Frequency" = "1" - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 off end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/banon/overridetree.cb b/src/mainboard/google/cyan/variants/banon/overridetree.cb new file mode 100644 index 0000000000..32f0dc6a5f --- /dev/null +++ b/src/mainboard/google/cyan/variants/banon/overridetree.cb @@ -0,0 +1,26 @@ +chip soc/intel/braswell + + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "6" + register "Usb2Port0IUsbTxEmphasisEn" = "3" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "6" + register "Usb2Port1IUsbTxEmphasisEn" = "3" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "6" + register "Usb2Port2IUsbTxEmphasisEn" = "3" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "6" + register "Usb2Port4IUsbTxEmphasisEn" = "3" + register "Usb2Port4PerPortTxPeHalf" = "1" + + device domain 0 on end + +end diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb deleted file mode 100644 index a1ab510810..0000000000 --- a/src/mainboard/google/cyan/variants/celes/devicetree.cb +++ /dev/null @@ -1,140 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "0" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "0" - register "PcdPchUsbHsicPort" = "0" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 off end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/celes/overridetree.cb b/src/mainboard/google/cyan/variants/celes/overridetree.cb new file mode 100644 index 0000000000..1eabd8e315 --- /dev/null +++ b/src/mainboard/google/cyan/variants/celes/overridetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/braswell + + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbHsicPort" = "0" + + device domain 0 on end + +end diff --git a/src/mainboard/google/cyan/variants/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb deleted file mode 100644 index dd9b05e5f7..0000000000 --- a/src/mainboard/google/cyan/variants/cyan/devicetree.cb +++ /dev/null @@ -1,139 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "0" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "0" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_CONFIG1" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "0" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 off end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 2284 - HD Audio - device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 - device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/cyan/overridetree.cb b/src/mainboard/google/cyan/variants/cyan/overridetree.cb new file mode 100644 index 0000000000..10df7ab023 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/braswell + + register "PcdCaMirrorEn" = "0" + + register "PcdEnableI2C0" = "1" # Touchscreen + register "PcdEnableI2C4" = "0" # No Realtek Audio + + register "ChvSvidConfig" = "SVID_CONFIG1" + + register "PMIC_I2CBus" = "0" + + register "I2C1Frequency" = "1" + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + device pci 18.5 off end # 8086 22c5 - I2C Port 5: Realtek Audio + end +end diff --git a/src/mainboard/google/cyan/variants/edgar/devicetree.cb b/src/mainboard/google/cyan/variants/edgar/devicetree.cb deleted file mode 100644 index 0ba221e3a6..0000000000 --- a/src/mainboard/google/cyan/variants/edgar/devicetree.cb +++ /dev/null @@ -1,140 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_DISABLED" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "0" - register "PcdEnableI2C1" = "0" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "6" - register "Usb2Port3IUsbTxEmphasisEn" = "3" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "0" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "0" - register "PcdPchUsbHsicPort" = "0" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 off end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 off end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/edgar/overridetree.cb b/src/mainboard/google/cyan/variants/edgar/overridetree.cb new file mode 100644 index 0000000000..48b10134f7 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/overridetree.cb @@ -0,0 +1,32 @@ +chip soc/intel/braswell + + register "PcdSdcardMode" = "PCH_DISABLED" + + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "0" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbHsicPort" = "0" + + device domain 0 on + device pci 12.0 off end # 8086 0F16 - SD Port + end +end diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb deleted file mode 100644 index 807dbcb2fe..0000000000 --- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb +++ /dev/null @@ -1,146 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - register "I2C0Frequency" = "1" - register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz - register "I2C2Frequency" = "1" - register "I2C3Frequency" = "1" - register "I2C4Frequency" = "1" - register "I2C5Frequency" = "1" - register "I2C6Frequency" = "1" - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 off end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/kefka/overridetree.cb b/src/mainboard/google/cyan/variants/kefka/overridetree.cb new file mode 100644 index 0000000000..41908e0d4c --- /dev/null +++ b/src/mainboard/google/cyan/variants/kefka/overridetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/braswell + + register "PcdEnableI2C0" = "1" # Touchscreen + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + end +end diff --git a/src/mainboard/google/cyan/variants/reks/devicetree.cb b/src/mainboard/google/cyan/variants/reks/devicetree.cb deleted file mode 100644 index 302f2da620..0000000000 --- a/src/mainboard/google/cyan/variants/reks/devicetree.cb +++ /dev/null @@ -1,137 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "7" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 off end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/reks/overridetree.cb b/src/mainboard/google/cyan/variants/reks/overridetree.cb new file mode 100644 index 0000000000..9b10656b2e --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/overridetree.cb @@ -0,0 +1,29 @@ +chip soc/intel/braswell + + register "PcdEnableI2C0" = "1" # Touchscreen + + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "7" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + end +end diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb deleted file mode 100644 index e1bbb0ac5b..0000000000 --- a/src/mainboard/google/cyan/variants/relm/devicetree.cb +++ /dev/null @@ -1,146 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - register "I2C0Frequency" = "1" - register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz - register "I2C2Frequency" = "1" - register "I2C3Frequency" = "1" - register "I2C4Frequency" = "1" - register "I2C5Frequency" = "1" - register "I2C6Frequency" = "1" - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 off end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/relm/overridetree.cb b/src/mainboard/google/cyan/variants/relm/overridetree.cb new file mode 100644 index 0000000000..41908e0d4c --- /dev/null +++ b/src/mainboard/google/cyan/variants/relm/overridetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/braswell + + register "PcdEnableI2C0" = "1" # Touchscreen + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + end +end diff --git a/src/mainboard/google/cyan/variants/setzer/devicetree.cb b/src/mainboard/google/cyan/variants/setzer/devicetree.cb deleted file mode 100644 index f0b2c6f976..0000000000 --- a/src/mainboard/google/cyan/variants/setzer/devicetree.cb +++ /dev/null @@ -1,146 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "0" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - register "I2C0Frequency" = "1" - register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz - register "I2C2Frequency" = "1" - register "I2C3Frequency" = "1" - register "I2C4Frequency" = "1" - register "I2C5Frequency" = "1" - register "I2C6Frequency" = "1" - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/setzer/overridetree.cb b/src/mainboard/google/cyan/variants/setzer/overridetree.cb new file mode 100644 index 0000000000..d3d7f8dbc7 --- /dev/null +++ b/src/mainboard/google/cyan/variants/setzer/overridetree.cb @@ -0,0 +1,10 @@ +chip soc/intel/braswell + + register "PcdEnableI2C0" = "1" # Touchscreen + + register "PcdPchSsicEnable" = "0" + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + end +end diff --git a/src/mainboard/google/cyan/variants/terra/overridetree.cb b/src/mainboard/google/cyan/variants/terra/overridetree.cb new file mode 100644 index 0000000000..8b6b0078cd --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/braswell + + device domain 0 on end + +end diff --git a/src/mainboard/google/cyan/variants/ultima/devicetree.cb b/src/mainboard/google/cyan/variants/ultima/devicetree.cb deleted file mode 100644 index d4ed38b430..0000000000 --- a/src/mainboard/google/cyan/variants/ultima/devicetree.cb +++ /dev/null @@ -1,140 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "0" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "0" - register "PcdPchUsbHsicPort" = "0" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 2284 - HD Audio - device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 off end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/ultima/overridetree.cb b/src/mainboard/google/cyan/variants/ultima/overridetree.cb new file mode 100644 index 0000000000..b5aa652292 --- /dev/null +++ b/src/mainboard/google/cyan/variants/ultima/overridetree.cb @@ -0,0 +1,11 @@ +chip soc/intel/braswell + + register "PcdEnableI2C0" = "1" # Touchscreen + + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbHsicPort" = "0" + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + end +end diff --git a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb b/src/mainboard/google/cyan/variants/wizpig/devicetree.cb deleted file mode 100644 index 7be7a0f792..0000000000 --- a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb +++ /dev/null @@ -1,147 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "1" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "1" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "0" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "0" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "0" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "0" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "0" - register "PcdPchUsbHsicPort" = "0" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "1" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - register "I2C0Frequency" = "1" - register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz - register "I2C2Frequency" = "1" - register "I2C3Frequency" = "1" - register "I2C4Frequency" = "1" - register "I2C5Frequency" = "1" - register "I2C6Frequency" = "1" - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 on end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 - device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/variants/wizpig/overridetree.cb b/src/mainboard/google/cyan/variants/wizpig/overridetree.cb new file mode 100644 index 0000000000..5923462147 --- /dev/null +++ b/src/mainboard/google/cyan/variants/wizpig/overridetree.cb @@ -0,0 +1,32 @@ +chip soc/intel/braswell + + register "PcdEnableI2C0" = "1" # Touchscreen + + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "0" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "0" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "0" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "0" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbHsicPort" = "0" + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + end +end From a2804781feaa7ba7db198fa03f20be861ccbe4a3 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 21 Jan 2018 18:32:07 -0600 Subject: [PATCH 0762/1463] mb/google/cyan: Switch eMMC and SD from ACPI to PCI mode Braswell boards don't work well with the eMMC and SD controller in ACPI in payloads other than depthcharge - SeaBIOS requires an onerous workaround (manually determining the PCI BAR0 address for each eMMC and SD controller, then adding adding etc/sdcard entries to the CBFS), and Tianocore can't see the devices at all. To make the common use-case work better, switch to PCI mode. Test: build/boot cyan variants with SeaBIOS and Tianocore payloads, verify eMMC and SD card visible and bootable to both payloads and OSes. Change-Id: I71947603e22a37fe2c8ef4eaac8a3aa0d0ed1cec Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40002 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/cyan/devicetree.cb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 328a60817e..b13f3f9e90 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/braswell # Set the parameters for SiliconInit ############################################################ - register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdSdcardMode" = "PCH_PCI_MODE" register "PcdEnableHsuart0" = "0" register "PcdEnableHsuart1" = "1" register "PcdEnableAzalia" = "1" @@ -36,7 +36,7 @@ chip soc/intel/braswell register "PcdEnableI2C6" = "0" register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdEmmcMode" = "PCH_PCI_MODE" register "PcdUsb3ClkSsc" = "1" register "PcdDispClkSsc" = "1" register "PcdSataClkSsc" = "1" @@ -84,10 +84,10 @@ chip soc/intel/braswell # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - # Enable devices in ACPI mode + # Enable LPSS and LPE devices in ACPI mode register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" register "lpe_acpi_mode" = "1" # Disable SLP_X stretching after SUS power well fail. From bf6b7bf60cc6c0cebe28901cd8a623224bfe1f2e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 21 Jan 2018 16:40:21 -0600 Subject: [PATCH 0763/1463] mb/google/cyan: Adjust CID for realtek audio codec Adjust CID to allow for Realtek's Windows drivers to attach without breaking functionality under Linux. Both Linux and Windows use ACPI HID/CID matching for driver attachment. Since the Realtek 5650 isn't used in standard Windows laptops, the '10EC5650' HID/CID isn't contained in the Windows drivers' lookup file (.inf), but a catch-all 'INTCCFFD' entry does exist, so concatenate that to the existing CID to allow the drivers to attach. Test: build/boot google/edgar, verify working audio under both Windows 10 (with Realtek drivers 10.0.10586.4393) and Linux (GalliumOS 3.1 / kernel 4.16.18, Manjaro 18.1 / kernel 5.1.x) Change-Id: Idca5cc86ba1f5ef3978cfba291a0c06e56ef5958 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40003 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/cyan/acpi/codec_realtek.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index 9ebef19065..365f799393 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -19,7 +19,7 @@ Scope (\_SB.PCI0.I2C5) Device (RTEK) /* Audio Codec driver I2C */ { Name (_HID, AUDIO_CODEC_HID) - Name (_CID, AUDIO_CODEC_CID) + Name (_CID, Package() { AUDIO_CODEC_CID, "INTCCFFD" }) Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) From c0b028f205a78ecc748e69d62450b4a804784da9 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 21 Jan 2018 16:40:00 -0600 Subject: [PATCH 0764/1463] mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs The jack detect GPIOs are initialized as dual edge-triggered GPIs, and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or ActiveBoth -- a single interrupt is detected on jack insertion or removal. The Windows drivers on the other hand, will not function unless the codec and LPE ACPI interrupts entries are set as in the Intel Cherry Trail Tianocore platform reference code. So adjust the ACPI interrupt triggers to make Windows happy, since Linux doesn't care either way. Test: boot Linux (GalliumOS 3.1) and Windows 10 on google/edgar, observe functional audio output for both built-in speakers and headphones. Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/24989 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/cyan/acpi/codec_maxim.asl | 6 +++--- src/mainboard/google/cyan/acpi/codec_realtek.asl | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index 4f69daf92d..a33f80a730 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -44,7 +44,7 @@ Scope (\_SB.PCI0.I2C2) "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault,, "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } } ) Return (SBUF) @@ -87,7 +87,7 @@ Scope (\_SB.PCI0.I2C2) "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } } ) @@ -107,7 +107,7 @@ Scope (\_SB.PCI0.LPEA) Name (GBUF, ResourceTemplate () { /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Edge, ActiveBoth, ExclusiveAndWake, PullDefault,, "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } }) } diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index 365f799393..34bf109b89 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -36,7 +36,7 @@ Scope (\_SB.PCI0.I2C5) ) /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } } ) Return (SBUF) @@ -54,7 +54,7 @@ Scope (\_SB.PCI0.LPEA) Name (GBUF, ResourceTemplate () { /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Edge, ActiveBoth, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } }) } From 1d6e07348a6ea52396273d4617cdf0d4020760c4 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 31 Mar 2020 17:37:12 -0500 Subject: [PATCH 0765/1463] mb/google/rambi: Convert to use override devicetree Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Change-Id: I52b71cf12a4e0b67135cfb106c3e89b00205d3bc Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39996 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/rambi/Kconfig | 4 +- .../rambi/{variants/quawks => }/devicetree.cb | 3 +- .../google/rambi/variants/banjo/devicetree.cb | 104 ----------------- .../rambi/variants/banjo/overridetree.cb | 11 ++ .../google/rambi/variants/candy/devicetree.cb | 105 ------------------ .../rambi/variants/candy/overridetree.cb | 11 ++ .../rambi/variants/clapper/devicetree.cb | 101 ----------------- .../rambi/variants/clapper/overridetree.cb | 8 ++ .../rambi/variants/enguarde/devicetree.cb | 104 ----------------- .../rambi/variants/enguarde/overridetree.cb | 9 ++ .../rambi/variants/glimmer/devicetree.cb | 101 ----------------- .../rambi/variants/glimmer/overridetree.cb | 7 ++ .../rambi/variants/gnawty/devicetree.cb | 104 ----------------- .../rambi/variants/gnawty/overridetree.cb | 9 ++ .../google/rambi/variants/heli/devicetree.cb | 105 ------------------ .../rambi/variants/heli/overridetree.cb | 11 ++ .../google/rambi/variants/kip/devicetree.cb | 104 ----------------- .../google/rambi/variants/kip/overridetree.cb | 9 ++ .../google/rambi/variants/ninja/devicetree.cb | 105 ------------------ .../rambi/variants/ninja/overridetree.cb | 12 ++ .../google/rambi/variants/orco/devicetree.cb | 104 ----------------- .../rambi/variants/orco/overridetree.cb | 9 ++ .../rambi/variants/quawks/overridetree.cb | 6 + .../google/rambi/variants/rambi/devicetree.cb | 105 ------------------ .../rambi/variants/rambi/overridetree.cb | 12 ++ .../rambi/variants/squawks/devicetree.cb | 101 ----------------- .../rambi/variants/squawks/overridetree.cb | 6 + .../google/rambi/variants/sumo/devicetree.cb | 105 ------------------ .../rambi/variants/sumo/overridetree.cb | 13 +++ .../rambi/variants/swanky/devicetree.cb | 104 ----------------- .../rambi/variants/swanky/overridetree.cb | 9 ++ .../google/rambi/variants/winky/devicetree.cb | 105 ------------------ .../rambi/variants/winky/overridetree.cb | 13 +++ 33 files changed, 158 insertions(+), 1561 deletions(-) rename src/mainboard/google/rambi/{variants/quawks => }/devicetree.cb (96%) delete mode 100644 src/mainboard/google/rambi/variants/banjo/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/banjo/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/candy/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/candy/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/clapper/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/clapper/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/enguarde/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/enguarde/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/glimmer/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/glimmer/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/gnawty/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/gnawty/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/heli/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/heli/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/kip/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/kip/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/ninja/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/ninja/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/orco/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/orco/overridetree.cb create mode 100644 src/mainboard/google/rambi/variants/quawks/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/rambi/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/rambi/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/squawks/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/squawks/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/sumo/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/sumo/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/swanky/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/swanky/overridetree.cb delete mode 100644 src/mainboard/google/rambi/variants/winky/devicetree.cb create mode 100644 src/mainboard/google/rambi/variants/winky/overridetree.cb diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 7a23a7d09a..d820875718 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -64,9 +64,9 @@ config MAINBOARD_PART_NUMBER default "Swanky" if BOARD_GOOGLE_SWANKY default "Winky" if BOARD_GOOGLE_WINKY -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config EC_GOOGLE_CHROMEEC_BOARDNAME string diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb similarity index 96% rename from src/mainboard/google/rambi/variants/quawks/devicetree.cb rename to src/mainboard/google/rambi/devicetree.cb index ee0f38d498..dc11ec8a91 100644 --- a/src/mainboard/google/rambi/variants/quawks/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -13,7 +13,6 @@ chip soc/intel/baytrail register "usb3_port_disable_mask" = "0x0" # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Quawks board register "usb2_per_port_lane0" = "0x00049a09" register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" register "usb2_per_port_lane1" = "0x00049a09" @@ -74,7 +73,7 @@ chip soc/intel/baytrail device pci 1a.0 off end # TXE device pci 1b.0 on end # HDA device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.1 off end # PCIE_PORT2 device pci 1c.2 off end # PCIE_PORT3 device pci 1c.3 off end # PCIE_PORT4 device pci 1d.0 on end # EHCI diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb deleted file mode 100644 index 55d9873fda..0000000000 --- a/src/mainboard/google/rambi/variants/banjo/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Banjo board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x0" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 off end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 off end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/banjo/overridetree.cb b/src/mainboard/google/rambi/variants/banjo/overridetree.cb new file mode 100644 index 0000000000..bd37ec63bd --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/overridetree.cb @@ -0,0 +1,11 @@ +chip soc/intel/baytrail + + register "sdcard_cap_low" = "0x0" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 12.0 off end # SD + end +end diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb deleted file mode 100644 index e048361b77..0000000000 --- a/src/mainboard/google/rambi/variants/candy/devicetree.cb +++ /dev/null @@ -1,105 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Candy board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - register "usb2_comp_bg" = "0x4700" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 on end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 off end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/candy/overridetree.cb b/src/mainboard/google/rambi/variants/candy/overridetree.cb new file mode 100644 index 0000000000..dcd001b8ae --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/overridetree.cb @@ -0,0 +1,11 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 18.6 on end # I2C6 + end +end diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb deleted file mode 100644 index c010af1e73..0000000000 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ /dev/null @@ -1,101 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Clapper board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 - device pci 18.6 on end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/clapper/overridetree.cb b/src/mainboard/google/rambi/variants/clapper/overridetree.cb new file mode 100644 index 0000000000..ce81c2d48c --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/overridetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/baytrail + + device domain 0 on + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb deleted file mode 100644 index 0db28d5edf..0000000000 --- a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Enguarde board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/enguarde/overridetree.cb b/src/mainboard/google/rambi/variants/enguarde/overridetree.cb new file mode 100644 index 0000000000..5a0589ac43 --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/overridetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/baytrail + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb deleted file mode 100644 index 5e7d6466dd..0000000000 --- a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb +++ /dev/null @@ -1,101 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Glimmer board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 on end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/glimmer/overridetree.cb b/src/mainboard/google/rambi/variants/glimmer/overridetree.cb new file mode 100644 index 0000000000..37b7c539b0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/overridetree.cb @@ -0,0 +1,7 @@ +chip soc/intel/baytrail + + device domain 0 on + device pci 18.6 on end # I2C6 + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb deleted file mode 100644 index 3559d9941a..0000000000 --- a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Gnawty board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/gnawty/overridetree.cb b/src/mainboard/google/rambi/variants/gnawty/overridetree.cb new file mode 100644 index 0000000000..5a0589ac43 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/overridetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/baytrail + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb deleted file mode 100644 index d6536c35a5..0000000000 --- a/src/mainboard/google/rambi/variants/heli/devicetree.cb +++ /dev/null @@ -1,105 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Heli board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - register "usb2_comp_bg" = "0x4700" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/heli/overridetree.cb b/src/mainboard/google/rambi/variants/heli/overridetree.cb new file mode 100644 index 0000000000..fb59964b6a --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/overridetree.cb @@ -0,0 +1,11 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb deleted file mode 100644 index 24facb300d..0000000000 --- a/src/mainboard/google/rambi/variants/kip/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Kip board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/kip/overridetree.cb b/src/mainboard/google/rambi/variants/kip/overridetree.cb new file mode 100644 index 0000000000..5a0589ac43 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/overridetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/baytrail + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/ninja/devicetree.cb b/src/mainboard/google/rambi/variants/ninja/devicetree.cb deleted file mode 100644 index b9e09e07ab..0000000000 --- a/src/mainboard/google/rambi/variants/ninja/devicetree.cb +++ /dev/null @@ -1,105 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Ninja board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - register "usb2_comp_bg" = "0x4700" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 off end # PCIE_PORT2 - device pci 1c.2 on end # PCIE_PORT3 - device pci 1c.3 on end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/ninja/overridetree.cb b/src/mainboard/google/rambi/variants/ninja/overridetree.cb new file mode 100644 index 0000000000..3f67644d79 --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/overridetree.cb @@ -0,0 +1,12 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + end +end diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb deleted file mode 100644 index c6123367f4..0000000000 --- a/src/mainboard/google/rambi/variants/orco/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Orco board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/orco/overridetree.cb b/src/mainboard/google/rambi/variants/orco/overridetree.cb new file mode 100644 index 0000000000..5a0589ac43 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/overridetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/baytrail + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/quawks/overridetree.cb b/src/mainboard/google/rambi/variants/quawks/overridetree.cb new file mode 100644 index 0000000000..76bcf92a21 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/baytrail + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/rambi/devicetree.cb b/src/mainboard/google/rambi/variants/rambi/devicetree.cb deleted file mode 100644 index 0fb7f14930..0000000000 --- a/src/mainboard/google/rambi/variants/rambi/devicetree.cb +++ /dev/null @@ -1,105 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Rambi board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - register "usb2_comp_bg" = "0x4700" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 on end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/rambi/overridetree.cb b/src/mainboard/google/rambi/variants/rambi/overridetree.cb new file mode 100644 index 0000000000..7ba9463447 --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/overridetree.cb @@ -0,0 +1,12 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 18.6 on end # I2C6 + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb deleted file mode 100644 index 4ed27be478..0000000000 --- a/src/mainboard/google/rambi/variants/squawks/devicetree.cb +++ /dev/null @@ -1,101 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Squawks board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/squawks/overridetree.cb b/src/mainboard/google/rambi/variants/squawks/overridetree.cb new file mode 100644 index 0000000000..76bcf92a21 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/baytrail + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb deleted file mode 100644 index 8f093c61e5..0000000000 --- a/src/mainboard/google/rambi/variants/sumo/devicetree.cb +++ /dev/null @@ -1,105 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Sumo board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - register "usb2_comp_bg" = "0x4700" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 on end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 off end # PCIE_PORT2 - device pci 1c.2 on end # PCIE_PORT3 - device pci 1c.3 on end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/sumo/overridetree.cb b/src/mainboard/google/rambi/variants/sumo/overridetree.cb new file mode 100644 index 0000000000..35052dc154 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/overridetree.cb @@ -0,0 +1,13 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 18.6 on end # I2C6 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + end +end diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb deleted file mode 100644 index 57f89109f3..0000000000 --- a/src/mainboard/google/rambi/variants/swanky/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Swanky board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/swanky/overridetree.cb b/src/mainboard/google/rambi/variants/swanky/overridetree.cb new file mode 100644 index 0000000000..5a0589ac43 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/overridetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/baytrail + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb deleted file mode 100644 index ed582ad21b..0000000000 --- a/src/mainboard/google/rambi/variants/winky/devicetree.cb +++ /dev/null @@ -1,105 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Winky board - register "usb2_comp_bg" = "0x4680" - register "usb2_per_port_lane0" = "0x0004C209" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x0004B209" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 off end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/variants/winky/overridetree.cb b/src/mainboard/google/rambi/variants/winky/overridetree.cb new file mode 100644 index 0000000000..d09ecbc48d --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/overridetree.cb @@ -0,0 +1,13 @@ +chip soc/intel/baytrail + + register "usb2_per_port_lane0" = "0x0004C209" + register "usb2_per_port_lane3" = "0x0004B209" + register "usb2_comp_bg" = "0x4680" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device domain 0 on + device pci 1c.1 on end # PCIE_PORT2 + end +end From bb8b23eeaf3e8d6363b8cee44c884db5b9f7fa96 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 31 Mar 2020 17:40:49 -0500 Subject: [PATCH 0766/1463] mb/google/rambi: Disable console output by default Disable SoC serial output by default, since no production devices have this exposed, but leave it as a user option so it can be selected as needed (eg, for use with a Google debug servo). Same change as made for google/cyan in CB:39872 Change-Id: Id6b2c28658aca03d8c5042d719a0f6f504c29288 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39997 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/rambi/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index d820875718..bc4aa6ea7c 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -4,7 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_RAMBI select SOC_INTEL_BAYTRAIL select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC - select ENABLE_BUILTIN_COM1 + select ENABLE_BUILTIN_COM1 if CONSOLE_SERIAL select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -76,4 +76,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config CONSOLE_SERIAL + default n + endif # BOARD_GOOGLE_BASEBOARD_RAMBI From adbb224f5aad822b1cc46481f4fc5e2c1fab5b07 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 5 Aug 2016 02:21:00 -0500 Subject: [PATCH 0767/1463] mb/google/auron: Add support for ACPI backlight controls Test: build/boot lulu and samus variants, verify backlight control functional under Windows 10. Change-Id: I4725fdea5206ae03df14a8b07e51fdf09f1edebd Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39944 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/auron/devicetree.cb | 3 +++ src/mainboard/google/auron/dsdt.asl | 1 + 2 files changed, 4 insertions(+) diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index cabcdf0c4b..a84aa98eeb 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/broadwell + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index f7c5000e9c..a22dedd82f 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -38,6 +38,7 @@ DefinitionBlock( { #include #include + #include } } From d61350c403f90ee11c179fece04f68e6c34e1555 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 1 Apr 2020 17:52:23 -0700 Subject: [PATCH 0768/1463] libpayload: malloc: Change memcpy() to memmove() in realloc Our realloc() works (somewhat suboptimally) by free()ing the existing allocation and then reallocating it wherever it fits. If there was free space before the old location, this means the new allocation may be before the old one, and if the free space block is smaller than the old allocation it may overlap. Thus, we should be moving memmove() instead of memcpy() to move the block over. This is not a problem in practice since all our existing memcpy()s are simple iterate and copy front to back implementations which are safe for overlaps when the destination is in front of the source. but it's still the more correct thing to do (in case we ever change our memcpy()s to do something more advanced or whatever). Signed-off-by: Julius Werner Change-Id: I35f77a94b7a72c01364ee7eecb5c3ff5ecde57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40028 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- payloads/libpayload/libc/malloc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 1fdb59e9b1..f2a54a70c8 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -310,8 +310,9 @@ void *realloc(void *ptr, size_t size) if (ret == NULL || ret == ptr) return ret; - /* Copy the memory to the new location. */ - memcpy(ret, ptr, osize > size ? size : osize); + /* Move the memory to the new location. Might be before the old location + and overlap since the free() above includes a _consolidate(). */ + memmove(ret, ptr, osize > size ? size : osize); return ret; } From b706ab379f808ca9b15d39c0c81a49ecb768c36d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:09 +0200 Subject: [PATCH 0769/1463] src/console: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib8a40e5633faf840e19a35bcdc8edc7e7cdd0ad9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40048 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/console/console.c | 14 ++------------ src/console/die.c | 15 ++------------- src/console/init.c | 15 ++------------- src/console/post.c | 15 ++------------- src/console/printk.c | 14 +++----------- src/console/vsprintf.c | 15 ++------------- src/console/vtxprintf.c | 14 +++----------- 7 files changed, 16 insertions(+), 86 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index a36cb96ed1..e7d74b61b9 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/console/die.c b/src/console/die.c index e57c4e4bf2..0d26dfe0c4 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/console/init.c b/src/console/init.c index 911dbd0546..80bdb24c4b 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/console/post.c b/src/console/post.c index 6265770b37..7d6a8ff028 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/console/printk.c b/src/console/printk.c index 3ef28f32be..bbe028b66e 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * blatantly copied from linux/kernel/printk.c */ diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 78bc09f5a7..bdc7244afb 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 4045543839..6801a970eb 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * vtxprintf.c, originally from linux/lib/vsprintf.c */ From ebda03ea5637cb2dd0b7426cbac72a4738ef7233 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:05 +0200 Subject: [PATCH 0770/1463] src/commonlib: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I29e746115e3b0630238176a0f913a3b5340962eb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40047 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/commonlib/cbfs.c | 14 ++------------ src/commonlib/fsp_relocate.c | 14 ++------------ src/commonlib/include/commonlib/cbfs.h | 14 ++------------ src/commonlib/include/commonlib/cbmem_id.h | 14 ++------------ src/commonlib/include/commonlib/coreboot_tables.h | 14 ++------------ src/commonlib/include/commonlib/endian.h | 14 ++------------ src/commonlib/include/commonlib/fsp.h | 14 ++------------ src/commonlib/include/commonlib/helpers.h | 14 ++------------ src/commonlib/include/commonlib/iobuf.h | 14 ++------------ src/commonlib/include/commonlib/mem_pool.h | 14 ++------------ src/commonlib/include/commonlib/region.h | 14 ++------------ src/commonlib/include/commonlib/rmodule-defs.h | 14 ++------------ src/commonlib/include/commonlib/sort.h | 14 ++------------ .../include/commonlib/tcpa_log_serialized.h | 14 ++------------ .../include/commonlib/timestamp_serialized.h | 14 ++------------ src/commonlib/iobuf.c | 14 ++------------ src/commonlib/mem_pool.c | 14 ++------------ src/commonlib/region.c | 14 ++------------ src/commonlib/sort.c | 14 ++------------ 19 files changed, 38 insertions(+), 228 deletions(-) diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index b03a3dcd3a..caa81ea76c 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index a8b45fa1fa..d9040efaf3 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index f5842d9047..eb74c4c1f3 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_CBFS_H_ #define _COMMONLIB_CBFS_H_ diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 93d1464f1b..1b4b2272ed 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CBMEM_ID_H_ #define _CBMEM_ID_H_ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 213d8210f8..3cba43e07a 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef COMMONLIB_COREBOOT_TABLES_H #define COMMONLIB_COREBOOT_TABLES_H diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h index 3d7ccb112b..78c4613b5e 100644 --- a/src/commonlib/include/commonlib/endian.h +++ b/src/commonlib/include/commonlib/endian.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_ENDIAN_H_ #define _COMMONLIB_ENDIAN_H_ diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h index 2ae7949c8e..c36f64bb7a 100644 --- a/src/commonlib/include/commonlib/fsp.h +++ b/src/commonlib/include/commonlib/fsp.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_FSP_H_ #define _COMMONLIB_FSP_H_ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index a5fe87d42e..eba021a481 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef COMMONLIB_HELPERS_H #define COMMONLIB_HELPERS_H diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h index f114ef8fe5..202226a6ea 100644 --- a/src/commonlib/include/commonlib/iobuf.h +++ b/src/commonlib/include/commonlib/iobuf.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef COMMONLIB_IOBUF_H #define COMMONLIB_IOBUF_H diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index ed473ebdf2..4775eafdf2 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MEM_POOL_H_ #define _MEM_POOL_H_ diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 47df9b63c6..86b9ee39cc 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _REGION_H_ #define _REGION_H_ diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h index de06941fa2..ca049368b8 100644 --- a/src/commonlib/include/commonlib/rmodule-defs.h +++ b/src/commonlib/include/commonlib/rmodule-defs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RMODULE_DEFS_H #define RMODULE_DEFS_H diff --git a/src/commonlib/include/commonlib/sort.h b/src/commonlib/include/commonlib/sort.h index 3d91cd8ec8..3ba00e7a2c 100644 --- a/src/commonlib/include/commonlib/sort.h +++ b/src/commonlib/include/commonlib/sort.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_SORT_H_ #define _COMMONLIB_SORT_H_ diff --git a/src/commonlib/include/commonlib/tcpa_log_serialized.h b/src/commonlib/include/commonlib/tcpa_log_serialized.h index 020eb04eee..84132fa8cb 100644 --- a/src/commonlib/include/commonlib/tcpa_log_serialized.h +++ b/src/commonlib/include/commonlib/tcpa_log_serialized.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TCPA_LOG_SERIALIZED_H__ #define __TCPA_LOG_SERIALIZED_H__ diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index ca72734df4..80a8d0b259 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TIMESTAMP_SERIALIZED_H__ #define __TIMESTAMP_SERIALIZED_H__ diff --git a/src/commonlib/iobuf.c b/src/commonlib/iobuf.c index fc0b2ed809..a05db01cf1 100644 --- a/src/commonlib/iobuf.c +++ b/src/commonlib/iobuf.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index 0aa821b24f..39bfe71cda 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 4a7e285747..b1203bc8e9 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/commonlib/sort.c b/src/commonlib/sort.c index 98d2db264f..cdb94d3c7f 100644 --- a/src/commonlib/sort.c +++ b/src/commonlib/sort.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 8670e829a8f2f6e56c2405333a171c2bc7cd017b Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 30 Mar 2020 12:25:06 -0700 Subject: [PATCH 0771/1463] soc/intel/xeon_sp/cpx: Add multi-core init Add minimal MP init. No SMM, no turbo, not c/p states. TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/soc/intel/xeon_sp/cpx/Makefile.inc | 3 +- src/soc/intel/xeon_sp/cpx/chip.c | 8 +- src/soc/intel/xeon_sp/cpx/cpu.c | 86 +++++++++++++++++++++ src/soc/intel/xeon_sp/cpx/include/soc/cpu.h | 11 ++- 4 files changed, 100 insertions(+), 8 deletions(-) create mode 100644 src/soc/intel/xeon_sp/cpx/cpu.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b909a454bd..e00ae40637 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,9 +8,10 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c -ramstage-y += chip.c acpi.c +ramstage-y += chip.c acpi.c cpu.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index dbbf3b31a5..e4063dc99d 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -29,16 +30,11 @@ static struct device_operations pci_domain_ops = { .scan_bus = &pci_domain_scan_bus, }; -static void init_cpus(struct device *dev) -{ - /* not implemented yet */ -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = init_cpus, + .init = cpx_init_cpus, .scan_bus = NULL, }; diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c new file mode 100644 index 0000000000..8824686674 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const void *microcode_patch; + +void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = intel_mp_current_microcode(); + *parallel = 1; +} + +const void *intel_mp_current_microcode(void) +{ + return microcode_patch; +} + +static void each_cpu_init(struct device *cpu) +{ + printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = each_cpu_init, +}; + +static const struct cpu_device_id cpu_table[] = { + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +/* + * Do essential initialization tasks before APs can be fired up + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_thread_count(void) +{ + unsigned int num_phys = 0, num_virts = 0; + + cpu_read_topology(&num_phys, &num_virts); + printk(BIOS_SPEW, "Detected %u cores and %u threads\n", num_phys, num_virts); + return num_virts; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_thread_count, + .get_microcode_info = get_microcode_info +}; + +void cpx_init_cpus(struct device *dev) +{ + microcode_patch = intel_microcode_find(); + + if (!microcode_patch) + printk(BIOS_ERR, "microcode not found in CBFS!\n"); + + intel_microcode_load_unlocked(microcode_patch); + + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index f33df89a60..563270d135 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -1,4 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* nothing here yet */ +#ifndef _SOC_CPU_H +#define _SOC_CPU_H + +#include + +#define CPUID_COOPERLAKE_SP_A0 0x05065a + +void cpx_init_cpus(struct device *dev); + +#endif From 182dbdeac4b2489f8d03a47a79ab28ad556d9d21 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:49:05 +0200 Subject: [PATCH 0772/1463] src/southbridge: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- .../amd/agesa/hudson/acpi/AmdImc.asl | 15 ++------------ .../amd/agesa/hudson/acpi/audio.asl | 16 ++------------- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 15 ++------------ src/southbridge/amd/agesa/hudson/acpi/lpc.asl | 15 ++------------ .../amd/agesa/hudson/acpi/pci_int.asl | 15 ++------------ .../amd/agesa/hudson/acpi/pcie.asl | 15 ++------------ src/southbridge/amd/agesa/hudson/acpi/usb.asl | 16 ++------------- .../amd/agesa/hudson/amd_pci_int_defs.h | 15 ++------------ .../amd/agesa/hudson/amd_pci_int_types.h | 15 ++------------ src/southbridge/amd/agesa/hudson/bootblock.c | 15 ++------------ src/southbridge/amd/agesa/hudson/chip.h | 15 ++------------ .../amd/agesa/hudson/early_setup.c | 15 ++------------ .../amd/agesa/hudson/enable_usbdebug.c | 15 ++------------ src/southbridge/amd/agesa/hudson/fadt.c | 15 ++------------ src/southbridge/amd/agesa/hudson/hda.c | 15 ++------------ src/southbridge/amd/agesa/hudson/hudson.c | 15 ++------------ src/southbridge/amd/agesa/hudson/hudson.h | 15 ++------------ src/southbridge/amd/agesa/hudson/ide.c | 15 ++------------ src/southbridge/amd/agesa/hudson/imc.c | 15 ++------------ src/southbridge/amd/agesa/hudson/imc.h | 15 ++------------ src/southbridge/amd/agesa/hudson/lpc.c | 15 ++------------ src/southbridge/amd/agesa/hudson/pci.c | 15 ++------------ src/southbridge/amd/agesa/hudson/pci_devs.h | 15 ++------------ src/southbridge/amd/agesa/hudson/pcie.c | 15 ++------------ src/southbridge/amd/agesa/hudson/ramtop.c | 15 ++------------ src/southbridge/amd/agesa/hudson/reset.c | 15 ++------------ src/southbridge/amd/agesa/hudson/resume.c | 15 ++------------ src/southbridge/amd/agesa/hudson/sata.c | 15 ++------------ src/southbridge/amd/agesa/hudson/sd.c | 15 ++------------ src/southbridge/amd/agesa/hudson/sm.c | 15 ++------------ src/southbridge/amd/agesa/hudson/smbus.c | 15 ++------------ src/southbridge/amd/agesa/hudson/smbus.h | 15 ++------------ src/southbridge/amd/agesa/hudson/smbus_spd.c | 15 ++------------ src/southbridge/amd/agesa/hudson/spi.c | 15 ++------------ src/southbridge/amd/agesa/hudson/usb.c | 15 ++------------ src/southbridge/amd/cimx/sb800/Amd.h | 20 ++----------------- src/southbridge/amd/cimx/sb800/AmdSbLib.h | 19 ++---------------- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 19 ++---------------- src/southbridge/amd/cimx/sb800/acpi/audio.asl | 16 ++------------- src/southbridge/amd/cimx/sb800/acpi/fch.asl | 15 ++------------ src/southbridge/amd/cimx/sb800/acpi/lpc.asl | 15 ++------------ src/southbridge/amd/cimx/sb800/acpi/pcie.asl | 15 ++------------ src/southbridge/amd/cimx/sb800/acpi/smbus.asl | 15 ++------------ src/southbridge/amd/cimx/sb800/acpi/usb.asl | 16 ++------------- .../amd/cimx/sb800/amd_pci_int_defs.h | 15 ++------------ .../amd/cimx/sb800/amd_pci_int_types.h | 15 ++------------ src/southbridge/amd/cimx/sb800/bootblock.c | 15 ++------------ src/southbridge/amd/cimx/sb800/cfg.c | 15 ++------------ src/southbridge/amd/cimx/sb800/cfg.h | 15 ++------------ src/southbridge/amd/cimx/sb800/chip.h | 15 ++------------ src/southbridge/amd/cimx/sb800/early.c | 15 ++------------ src/southbridge/amd/cimx/sb800/fadt.c | 15 ++------------ src/southbridge/amd/cimx/sb800/fan.c | 15 ++------------ src/southbridge/amd/cimx/sb800/fan.h | 15 ++------------ src/southbridge/amd/cimx/sb800/gpio_oem.h | 14 ++----------- src/southbridge/amd/cimx/sb800/late.c | 15 ++------------ src/southbridge/amd/cimx/sb800/lpc.c | 15 ++------------ src/southbridge/amd/cimx/sb800/lpc.h | 15 ++------------ src/southbridge/amd/cimx/sb800/pci_devs.h | 15 ++------------ src/southbridge/amd/cimx/sb800/ramtop.c | 15 ++------------ src/southbridge/amd/cimx/sb800/reset.c | 15 ++------------ src/southbridge/amd/cimx/sb800/sb_cimx.h | 15 ++------------ src/southbridge/amd/cimx/sb800/smbus.c | 15 ++------------ src/southbridge/amd/cimx/sb800/smbus.h | 15 ++------------ src/southbridge/amd/cimx/sb800/smbus_spd.c | 15 ++------------ src/southbridge/amd/cimx/sb800/smbus_spd.h | 15 ++------------ src/southbridge/amd/cimx/sb800/spi.c | 15 ++------------ .../amd/common/acpi/sleepstates.asl | 15 ++------------ src/southbridge/amd/common/amd_defs.h | 15 ++------------ src/southbridge/amd/common/amd_pci_util.c | 15 ++------------ src/southbridge/amd/common/amd_pci_util.h | 15 ++------------ src/southbridge/amd/common/reset.h | 15 ++------------ src/southbridge/amd/pi/hudson/acpi/AmdImc.asl | 15 ++------------ src/southbridge/amd/pi/hudson/acpi/audio.asl | 16 ++------------- src/southbridge/amd/pi/hudson/acpi/fch.asl | 15 ++------------ src/southbridge/amd/pi/hudson/acpi/lpc.asl | 15 ++------------ .../amd/pi/hudson/acpi/pci_int.asl | 15 ++------------ src/southbridge/amd/pi/hudson/acpi/pcie.asl | 15 ++------------ src/southbridge/amd/pi/hudson/acpi/usb.asl | 16 ++------------- .../amd/pi/hudson/amd_pci_int_defs.h | 15 ++------------ .../amd/pi/hudson/amd_pci_int_types.h | 15 ++------------ src/southbridge/amd/pi/hudson/bootblock.c | 15 ++------------ src/southbridge/amd/pi/hudson/chip.h | 15 ++------------ src/southbridge/amd/pi/hudson/early_setup.c | 15 ++------------ .../amd/pi/hudson/enable_usbdebug.c | 15 ++------------ src/southbridge/amd/pi/hudson/fadt.c | 15 ++------------ src/southbridge/amd/pi/hudson/fchec.h | 15 ++------------ src/southbridge/amd/pi/hudson/gpio.c | 15 ++------------ src/southbridge/amd/pi/hudson/gpio.h | 15 ++------------ src/southbridge/amd/pi/hudson/hda.c | 15 ++------------ src/southbridge/amd/pi/hudson/hudson.c | 15 ++------------ src/southbridge/amd/pi/hudson/hudson.h | 15 ++------------ src/southbridge/amd/pi/hudson/ide.c | 15 ++------------ src/southbridge/amd/pi/hudson/imc.c | 15 ++------------ src/southbridge/amd/pi/hudson/imc.h | 15 ++------------ src/southbridge/amd/pi/hudson/lpc.c | 15 ++------------ src/southbridge/amd/pi/hudson/pci.c | 15 ++------------ src/southbridge/amd/pi/hudson/pci_devs.h | 15 ++------------ src/southbridge/amd/pi/hudson/pcie.c | 15 ++------------ src/southbridge/amd/pi/hudson/reset.c | 15 ++------------ src/southbridge/amd/pi/hudson/sata.c | 15 ++------------ src/southbridge/amd/pi/hudson/sd.c | 15 ++------------ src/southbridge/amd/pi/hudson/sm.c | 15 ++------------ src/southbridge/amd/pi/hudson/smbus.c | 15 ++------------ src/southbridge/amd/pi/hudson/smbus.h | 15 ++------------ src/southbridge/amd/pi/hudson/smbus_spd.c | 15 ++------------ src/southbridge/amd/pi/hudson/uart.c | 15 ++------------ src/southbridge/amd/pi/hudson/usb.c | 15 ++------------ src/southbridge/intel/bd82x6x/acpi/audio.asl | 16 ++------------- .../intel/bd82x6x/acpi/globalnvs.asl | 16 ++------------- .../intel/bd82x6x/acpi/irqlinks.asl | 16 ++------------- src/southbridge/intel/bd82x6x/acpi/lpc.asl | 16 ++------------- src/southbridge/intel/bd82x6x/acpi/pch.asl | 16 ++------------- src/southbridge/intel/bd82x6x/acpi/sata.asl | 16 ++------------- src/southbridge/intel/bd82x6x/acpi/usb.asl | 16 ++------------- src/southbridge/intel/bd82x6x/azalia.c | 15 ++------------ src/southbridge/intel/bd82x6x/bootblock.c | 15 ++------------ src/southbridge/intel/bd82x6x/chip.h | 15 ++------------ src/southbridge/intel/bd82x6x/early_me.c | 16 ++------------- src/southbridge/intel/bd82x6x/early_me_mrc.c | 16 ++------------- src/southbridge/intel/bd82x6x/early_pch.c | 15 ++------------ src/southbridge/intel/bd82x6x/early_rcba.c | 15 ++------------ src/southbridge/intel/bd82x6x/early_smbus.c | 16 ++------------- src/southbridge/intel/bd82x6x/early_usb.c | 16 ++------------- src/southbridge/intel/bd82x6x/early_usb_mrc.c | 16 ++------------- src/southbridge/intel/bd82x6x/elog.c | 15 ++------------ src/southbridge/intel/bd82x6x/lpc.c | 16 ++------------- src/southbridge/intel/bd82x6x/me.c | 16 ++------------- src/southbridge/intel/bd82x6x/me.h | 16 ++------------- src/southbridge/intel/bd82x6x/me_8.x.c | 16 ++------------- src/southbridge/intel/bd82x6x/me_status.c | 16 ++------------- src/southbridge/intel/bd82x6x/nvs.h | 15 ++------------ src/southbridge/intel/bd82x6x/pch.c | 16 ++------------- src/southbridge/intel/bd82x6x/pch.h | 15 ++------------ src/southbridge/intel/bd82x6x/pci.c | 16 ++------------- src/southbridge/intel/bd82x6x/pcie.c | 16 ++------------- src/southbridge/intel/bd82x6x/sata.c | 16 ++------------- src/southbridge/intel/bd82x6x/smbus.c | 16 ++------------- src/southbridge/intel/bd82x6x/smihandler.c | 16 ++------------- src/southbridge/intel/bd82x6x/usb_ehci.c | 16 ++------------- src/southbridge/intel/bd82x6x/usb_xhci.c | 16 ++------------- src/southbridge/intel/common/acpi/pcie.asl | 16 ++------------- .../intel/common/acpi/pcie_port.asl | 16 ++------------- .../intel/common/acpi/platform.asl | 16 ++------------- .../intel/common/acpi/sleepstates.asl | 16 ++------------- src/southbridge/intel/common/acpi/smbus.asl | 16 ++------------- src/southbridge/intel/common/acpi_pirq_gen.c | 15 ++------------ src/southbridge/intel/common/acpi_pirq_gen.h | 15 ++------------ src/southbridge/intel/common/finalize.c | 16 ++------------- src/southbridge/intel/common/gpio.c | 15 ++------------ src/southbridge/intel/common/gpio.h | 15 ++------------ src/southbridge/intel/common/madt.c | 15 ++------------ src/southbridge/intel/common/pciehp.c | 16 ++------------- src/southbridge/intel/common/pciehp.h | 14 ++----------- src/southbridge/intel/common/pmbase.c | 15 ++------------ src/southbridge/intel/common/pmbase.h | 15 ++------------ src/southbridge/intel/common/pmclib.c | 16 ++------------- src/southbridge/intel/common/pmclib.h | 16 ++------------- src/southbridge/intel/common/pmutil.c | 16 ++------------- src/southbridge/intel/common/pmutil.h | 16 ++------------- src/southbridge/intel/common/rcba.h | 15 ++------------ src/southbridge/intel/common/rcba_pirq.c | 15 ++------------ src/southbridge/intel/common/rcba_pirq.h | 15 ++------------ src/southbridge/intel/common/reset.c | 14 ++----------- src/southbridge/intel/common/rtc.c | 16 ++------------- src/southbridge/intel/common/rtc.h | 16 ++------------- src/southbridge/intel/common/smbus.c | 15 ++------------ src/southbridge/intel/common/smi.c | 16 ++------------- src/southbridge/intel/common/smihandler.c | 16 ++------------- src/southbridge/intel/common/tco.h | 15 ++------------ src/southbridge/intel/common/usb_debug.c | 15 ++------------ src/southbridge/intel/common/watchdog.c | 16 ++------------- .../intel/i82371eb/acpi/i82371eb.asl | 15 ++------------ src/southbridge/intel/i82371eb/acpi/intx.asl | 15 ++------------ .../intel/i82371eb/acpi/isabridge.asl | 15 ++------------ src/southbridge/intel/i82371eb/acpi/pirq.asl | 15 ++------------ src/southbridge/intel/i82371eb/acpi_tables.c | 15 ++------------ src/southbridge/intel/i82801dx/ac97.c | 16 ++------------- src/southbridge/intel/i82801dx/bootblock.c | 14 ++----------- src/southbridge/intel/i82801dx/chip.h | 16 ++------------- src/southbridge/intel/i82801dx/early_smbus.c | 16 ++------------- src/southbridge/intel/i82801dx/i82801dx.c | 16 ++------------- src/southbridge/intel/i82801dx/i82801dx.h | 16 ++------------- src/southbridge/intel/i82801dx/ide.c | 16 ++------------- src/southbridge/intel/i82801dx/lpc.c | 16 ++------------- src/southbridge/intel/i82801dx/nvs.h | 15 ++------------ src/southbridge/intel/i82801dx/pci.c | 15 ++------------ src/southbridge/intel/i82801dx/smi.c | 16 ++------------- src/southbridge/intel/i82801dx/smihandler.c | 16 ++------------- src/southbridge/intel/i82801dx/usb.c | 16 ++------------- src/southbridge/intel/i82801dx/usb2.c | 16 ++------------- src/southbridge/intel/i82801gx/ac97.c | 16 ++------------- src/southbridge/intel/i82801gx/acpi/ac97.asl | 16 ++------------- src/southbridge/intel/i82801gx/acpi/audio.asl | 16 ++------------- .../intel/i82801gx/acpi/globalnvs.asl | 16 ++------------- src/southbridge/intel/i82801gx/acpi/ich7.asl | 16 ++------------- .../intel/i82801gx/acpi/irqlinks.asl | 16 ++------------- src/southbridge/intel/i82801gx/acpi/lpc.asl | 16 ++------------- src/southbridge/intel/i82801gx/acpi/pata.asl | 16 ++------------- src/southbridge/intel/i82801gx/acpi/pci.asl | 16 ++------------- src/southbridge/intel/i82801gx/acpi/sata.asl | 16 ++------------- src/southbridge/intel/i82801gx/acpi/usb.asl | 16 ++------------- src/southbridge/intel/i82801gx/azalia.c | 15 ++------------ src/southbridge/intel/i82801gx/bootblock.c | 15 ++------------ src/southbridge/intel/i82801gx/chip.h | 15 ++------------ src/southbridge/intel/i82801gx/early_cir.c | 14 ++----------- src/southbridge/intel/i82801gx/early_init.c | 14 ++----------- src/southbridge/intel/i82801gx/early_smbus.c | 16 ++------------- src/southbridge/intel/i82801gx/i82801gx.c | 16 ++------------- src/southbridge/intel/i82801gx/i82801gx.h | 15 ++------------ src/southbridge/intel/i82801gx/ide.c | 16 ++------------- src/southbridge/intel/i82801gx/lpc.c | 16 ++------------- src/southbridge/intel/i82801gx/nic.c | 16 ++------------- src/southbridge/intel/i82801gx/nvs.h | 15 ++------------ src/southbridge/intel/i82801gx/pci.c | 16 ++------------- src/southbridge/intel/i82801gx/pcie.c | 16 ++------------- src/southbridge/intel/i82801gx/sata.c | 16 ++------------- src/southbridge/intel/i82801gx/smbus.c | 16 ++------------- src/southbridge/intel/i82801gx/smihandler.c | 16 ++------------- src/southbridge/intel/i82801gx/usb.c | 16 ++------------- src/southbridge/intel/i82801gx/usb_ehci.c | 16 ++------------- src/southbridge/intel/i82801ix/acpi/audio.asl | 16 ++------------- .../intel/i82801ix/acpi/globalnvs.asl | 16 ++------------- src/southbridge/intel/i82801ix/acpi/ich9.asl | 16 ++------------- .../intel/i82801ix/acpi/irqlinks.asl | 16 ++------------- src/southbridge/intel/i82801ix/acpi/lpc.asl | 16 ++------------- src/southbridge/intel/i82801ix/acpi/pci.asl | 16 ++------------- src/southbridge/intel/i82801ix/acpi/sata.asl | 16 ++------------- src/southbridge/intel/i82801ix/acpi/usb.asl | 16 ++------------- src/southbridge/intel/i82801ix/bootblock.c | 15 ++------------ src/southbridge/intel/i82801ix/chip.h | 15 ++------------ src/southbridge/intel/i82801ix/dmi_setup.c | 16 ++------------- src/southbridge/intel/i82801ix/early_init.c | 16 ++------------- src/southbridge/intel/i82801ix/early_smbus.c | 16 ++------------- src/southbridge/intel/i82801ix/hdaudio.c | 15 ++------------ src/southbridge/intel/i82801ix/i82801ix.c | 16 ++------------- src/southbridge/intel/i82801ix/i82801ix.h | 15 ++------------ src/southbridge/intel/i82801ix/lpc.c | 16 ++------------- src/southbridge/intel/i82801ix/nvs.h | 15 ++------------ src/southbridge/intel/i82801ix/pci.c | 16 ++------------- src/southbridge/intel/i82801ix/pcie.c | 16 ++------------- src/southbridge/intel/i82801ix/sata.c | 16 ++------------- src/southbridge/intel/i82801ix/smbus.c | 16 ++------------- src/southbridge/intel/i82801ix/smi.c | 13 +----------- src/southbridge/intel/i82801ix/smihandler.c | 16 ++------------- src/southbridge/intel/i82801ix/thermal.c | 16 ++------------- src/southbridge/intel/i82801ix/usb_ehci.c | 16 ++------------- src/southbridge/intel/i82801jx/acpi/audio.asl | 16 ++------------- .../intel/i82801jx/acpi/globalnvs.asl | 16 ++------------- src/southbridge/intel/i82801jx/acpi/ich10.asl | 16 ++------------- .../intel/i82801jx/acpi/irqlinks.asl | 16 ++------------- src/southbridge/intel/i82801jx/acpi/lpc.asl | 16 ++------------- src/southbridge/intel/i82801jx/acpi/pci.asl | 16 ++------------- src/southbridge/intel/i82801jx/acpi/sata.asl | 16 ++------------- src/southbridge/intel/i82801jx/acpi/usb.asl | 16 ++------------- src/southbridge/intel/i82801jx/bootblock.c | 15 ++------------ src/southbridge/intel/i82801jx/chip.h | 15 ++------------ src/southbridge/intel/i82801jx/early_init.c | 15 ++------------ src/southbridge/intel/i82801jx/early_smbus.c | 16 ++------------- src/southbridge/intel/i82801jx/hdaudio.c | 15 ++------------ src/southbridge/intel/i82801jx/i82801jx.c | 16 ++------------- src/southbridge/intel/i82801jx/i82801jx.h | 15 ++------------ src/southbridge/intel/i82801jx/lpc.c | 16 ++------------- src/southbridge/intel/i82801jx/nvs.h | 15 ++------------ src/southbridge/intel/i82801jx/pci.c | 16 ++------------- src/southbridge/intel/i82801jx/pcie.c | 16 ++------------- src/southbridge/intel/i82801jx/sata.c | 16 ++------------- src/southbridge/intel/i82801jx/smbus.c | 16 ++------------- src/southbridge/intel/i82801jx/smihandler.c | 16 ++------------- src/southbridge/intel/i82801jx/thermal.c | 16 ++------------- src/southbridge/intel/i82801jx/usb_ehci.c | 16 ++------------- src/southbridge/intel/i82870/82870.h | 14 ++----------- src/southbridge/intel/i82870/ioapic.c | 14 ++----------- src/southbridge/intel/i82870/pcibridge.c | 14 ++----------- src/southbridge/intel/ibexpeak/azalia.c | 15 ++------------ src/southbridge/intel/ibexpeak/bootblock.c | 15 ++------------ src/southbridge/intel/ibexpeak/chip.h | 15 ++------------ src/southbridge/intel/ibexpeak/early_cir.c | 14 ++----------- src/southbridge/intel/ibexpeak/early_pch.c | 16 ++------------- src/southbridge/intel/ibexpeak/early_smbus.c | 16 ++------------- src/southbridge/intel/ibexpeak/early_usb.c | 16 ++------------- src/southbridge/intel/ibexpeak/lpc.c | 16 ++------------- src/southbridge/intel/ibexpeak/madt.c | 16 ++------------- src/southbridge/intel/ibexpeak/me.c | 16 ++------------- src/southbridge/intel/ibexpeak/me.h | 16 ++------------- src/southbridge/intel/ibexpeak/nvs.h | 15 ++------------ src/southbridge/intel/ibexpeak/pch.c | 16 ++------------- src/southbridge/intel/ibexpeak/pch.h | 15 ++------------ src/southbridge/intel/ibexpeak/sata.c | 16 ++------------- src/southbridge/intel/ibexpeak/smbus.c | 16 ++------------- src/southbridge/intel/ibexpeak/smihandler.c | 16 ++------------- src/southbridge/intel/ibexpeak/thermal.c | 16 ++------------- src/southbridge/intel/ibexpeak/usb_ehci.c | 16 ++------------- src/southbridge/intel/lynxpoint/acpi.c | 15 ++------------ .../intel/lynxpoint/acpi/audio.asl | 16 ++------------- .../intel/lynxpoint/acpi/globalnvs.asl | 16 ++------------- .../intel/lynxpoint/acpi/irqlinks.asl | 16 ++------------- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 16 ++------------- .../intel/lynxpoint/acpi/lpt_lp.asl | 16 ++------------- src/southbridge/intel/lynxpoint/acpi/pch.asl | 16 ++------------- src/southbridge/intel/lynxpoint/acpi/sata.asl | 16 ++------------- .../intel/lynxpoint/acpi/serialio.asl | 16 ++------------- src/southbridge/intel/lynxpoint/acpi/usb.asl | 16 ++------------- src/southbridge/intel/lynxpoint/azalia.c | 15 ++------------ src/southbridge/intel/lynxpoint/bootblock.c | 15 ++------------ src/southbridge/intel/lynxpoint/chip.h | 15 ++------------ src/southbridge/intel/lynxpoint/early_me.c | 16 ++------------- src/southbridge/intel/lynxpoint/early_pch.c | 15 ++------------ src/southbridge/intel/lynxpoint/early_smbus.c | 16 ++------------- src/southbridge/intel/lynxpoint/early_usb.c | 16 ++------------- src/southbridge/intel/lynxpoint/elog.c | 15 ++------------ src/southbridge/intel/lynxpoint/hda_verb.c | 15 ++------------ src/southbridge/intel/lynxpoint/hda_verb.h | 15 ++------------ src/southbridge/intel/lynxpoint/lp_gpio.c | 15 ++------------ src/southbridge/intel/lynxpoint/lp_gpio.h | 15 ++------------ src/southbridge/intel/lynxpoint/lpc.c | 16 ++------------- src/southbridge/intel/lynxpoint/me.h | 16 ++------------- src/southbridge/intel/lynxpoint/me_9.x.c | 16 ++------------- src/southbridge/intel/lynxpoint/me_status.c | 16 ++------------- src/southbridge/intel/lynxpoint/nvs.h | 15 ++------------ src/southbridge/intel/lynxpoint/pch.c | 16 ++------------- src/southbridge/intel/lynxpoint/pch.h | 15 ++------------ src/southbridge/intel/lynxpoint/pcie.c | 16 ++------------- src/southbridge/intel/lynxpoint/pmutil.c | 16 ++------------- src/southbridge/intel/lynxpoint/rcba.c | 15 ++------------ src/southbridge/intel/lynxpoint/sata.c | 16 ++------------- src/southbridge/intel/lynxpoint/serialio.c | 16 ++------------- src/southbridge/intel/lynxpoint/smbus.c | 16 ++------------- src/southbridge/intel/lynxpoint/smi.c | 16 ++------------- src/southbridge/intel/lynxpoint/smihandler.c | 16 ++------------- src/southbridge/intel/lynxpoint/usb_ehci.c | 16 ++------------- src/southbridge/intel/lynxpoint/usb_xhci.c | 16 ++------------- src/southbridge/ricoh/rl5c476/chip.h | 14 ++----------- src/southbridge/ti/pci1x2x/chip.h | 14 ++----------- src/southbridge/ti/pcixx12/pcixx12.c | 15 ++------------ 335 files changed, 669 insertions(+), 4513 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl index 89189b8de9..4571314c66 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ OperationRegion(IMIO, SystemIO, 0x3E, 0x02) Field(IMIO , ByteAcc, NoLock, Preserve) { diff --git a/src/southbridge/amd/agesa/hudson/acpi/audio.asl b/src/southbridge/amd/agesa/hudson/acpi/audio.asl index bac56b0d50..2c27046353 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/audio.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(AZHD) { /* 0:14.2 - HD Audio */ Name(_ADR, 0x00140002) diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index d77503281e..1c0b0b8084 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* System Bus */ /* _SB.PCI0 */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl index adb98ffc89..a09f166cda 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* 0:14.3 - LPC */ Device(LIBR) { diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl index 17e1deaf57..e326063918 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl index 9faee36194..fb25373a69 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCI IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl index 0e0f982611..51b8afb804 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* 0:12.0 - OHCI */ Device(UOH1) { diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 9385088789..f5e01dd70f 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AMD_PCI_INT_DEFS_H #define AMD_PCI_INT_DEFS_H diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 5fb231610a..32a7d47d69 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index c8605fecd7..e103bc4325 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h index 926f88f620..36c4e86289 100644 --- a/src/southbridge/amd/agesa/hudson/chip.h +++ b/src/southbridge/amd/agesa/hudson/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_CHIP_H #define HUDSON_CHIP_H diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c83fe535b8..a4399c9b2d 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _HUDSON_EARLY_SETUP_C_ #define _HUDSON_EARLY_SETUP_C_ diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 067ba9b880..58c2d05a45 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 4fe7f91458..0baaa9c5c8 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * ACPI - create the Fixed ACPI Description Tables (FADT) diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index 3acbdf0fc4..d03694c2ab 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 99f581f2e2..ca6b46b58a 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index bd9250a42b..9377c97d45 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_H #define HUDSON_H diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c index 69d95912d8..76e5ead8e4 100644 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ b/src/southbridge/amd/agesa/hudson/ide.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 9bc12eba9d..cbad2c969a 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "imc.h" #include diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h index 434bd28226..33c46d6840 100644 --- a/src/southbridge/amd/agesa/hudson/imc.h +++ b/src/southbridge/amd/agesa/hudson/imc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_IMC_H #define HUDSON_IMC_H diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index b6a8494362..0b579842a6 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index e8f316a1dd..cacc59d926 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index 97892db9c9..ff38669195 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AGESA_HUDSON_PCI_DEVS_H_ #define _AGESA_HUDSON_PCI_DEVS_H_ diff --git a/src/southbridge/amd/agesa/hudson/pcie.c b/src/southbridge/amd/agesa/hudson/pcie.c index b4329639ec..ccd687abea 100644 --- a/src/southbridge/amd/agesa/hudson/pcie.c +++ b/src/southbridge/amd/agesa/hudson/pcie.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c index 33ffb9ae4c..46ce0cf07b 100644 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index c1043342d7..2d90ae2aca 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 7f2c06d21d..99c94b6da7 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index 2ca85913f3..fcf27c63c8 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index 0da763172f..3d5eb29f50 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index ec10a41647..f4e2652cdc 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 8a97667c31..1c71c87948 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_ diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 555210410f..5b7621e43f 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_SMBUS_H #define HUDSON_SMBUS_H diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 7adee8a399..14bec8c3ab 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index a2b5a559e5..f6625b944d 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c index c634830064..2657555964 100644 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ b/src/southbridge/amd/agesa/hudson/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index 47afc33889..8f91863e9b 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -8,24 +8,8 @@ * Contains AMD AGESA/CIMx core interface * */ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * *************************************************************************** - * - */ - +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_H_ #define _AMD_H_ diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h index 82485b9b04..30cd71e3c3 100644 --- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h @@ -1,20 +1,5 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * *************************************************************************** - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_SB_LIB_H_ #define _AMD_SB_LIB_H_ diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 596f711d4c..1addeea00c 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -1,20 +1,5 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * *************************************************************************** - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/acpi/audio.asl b/src/southbridge/amd/cimx/sb800/acpi/audio.asl index 79490883f0..bca944cc08 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/audio.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(AZHD) { Name(_ADR, 0x00140002) diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 4c11644fc4..af9d491e31 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* System Bus */ /* _SB.PCI0 */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl index 7d602ba214..41e77646d5 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(LIBR) { Name(_ADR, 0x00140003) diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index c341e2335d..45b2821aef 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\) { /* PCI IRQ mapping registers, C00h-C01h. */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index 206ee05ce5..2d9fd3c29d 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SMBUS Support */ Mutex (SBX0, 0x00) diff --git a/src/southbridge/amd/cimx/sb800/acpi/usb.asl b/src/southbridge/amd/cimx/sb800/acpi/usb.asl index a7a702d09c..1d555d8785 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/usb.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(UOH1) { Name(_ADR, 0x00120000) diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h index e312d1fd6b..6f7393b529 100644 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AMD_PCI_INT_DEFS_H #define AMD_PCI_INT_DEFS_H diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h index d7072dcdd2..db6015e305 100644 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 45a861b297..7a1d05bf17 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 8d815366fa..cf7f3f5fa5 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "SBPLATFORM.h" #include "cfg.h" diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h index b169648bf3..514755c3f6 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.h +++ b/src/southbridge/amd/cimx/sb800/cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SB800_CFG_H_ diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h index 9bd0c54599..bb4b2dbf15 100644 --- a/src/southbridge/amd/cimx/sb800/chip.h +++ b/src/southbridge/amd/cimx/sb800/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CIMX_SB800_CHIP_H_ #define _CIMX_SB800_CHIP_H_ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index d5d0ab04dc..7399b0f595 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 08fbecb554..5cb1695c85 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index 2da6716901..48aeddbae5 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index b2a3556dc3..523d63690b 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SB800_FAN_H_ #define _SB800_FAN_H_ diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h index 9063b2b36b..3313a0fc27 100644 --- a/src/southbridge/amd/cimx/sb800/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CIMX_SB_GPIO_OEM_H_ #define _CIMX_SB_GPIO_OEM_H_ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index f8773fcd10..babc21ef3f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index cb2b266f95..3f0ff7fea3 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index f992e2d60e..bab25b1918 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ diff --git a/src/southbridge/amd/cimx/sb800/pci_devs.h b/src/southbridge/amd/cimx/sb800/pci_devs.h index 38faff6384..5122179b5a 100644 --- a/src/southbridge/amd/cimx/sb800/pci_devs.h +++ b/src/southbridge/amd/cimx/sb800/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CIMX_SB800_PCI_DEVS_H_ #define _CIMX_SB800_PCI_DEVS_H_ diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index 76e5d674e1..25259eeacf 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 7ea6e6f9ab..8c2a2ed58f 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 62d76a7e4d..c1e9808631 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CIMX_H_ diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 4e9f7b68e4..c3183951f7 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h index 6bfb8e9ca4..8db378ca23 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ b/src/southbridge/amd/cimx/sb800/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SB800_SMBUS_H_ #define _SB800_SMBUS_H_ diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c index e1bcb50615..0644b67fb4 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.h b/src/southbridge/amd/cimx/sb800/smbus_spd.h index 20d57c2917..d9e20b91ef 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.h +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SMBUS_SPD_H_ #define _SMBUS_SPD_H_ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 7e30e75ac5..db2cbfbac1 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/common/acpi/sleepstates.asl b/src/southbridge/amd/common/acpi/sleepstates.asl index 8de2108e84..26bf51eec8 100644 --- a/src/southbridge/amd/common/acpi/sleepstates.asl +++ b/src/southbridge/amd/common/acpi/sleepstates.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ #if CONFIG(HAVE_ACPI_RESUME) diff --git a/src/southbridge/amd/common/amd_defs.h b/src/southbridge/amd/common/amd_defs.h index 52f9ad72d6..c5156f6eda 100644 --- a/src/southbridge/amd/common/amd_defs.h +++ b/src/southbridge/amd/common/amd_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_SB_DEFS_H_ diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index 3cd725e74a..33d4033bfe 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index c665ace5d1..7e7e8a93f8 100644 --- a/src/southbridge/amd/common/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AMD_PCI_UTIL_H #define AMD_PCI_UTIL_H diff --git a/src/southbridge/amd/common/reset.h b/src/southbridge/amd/common/reset.h index 006dd8c04d..65badc588d 100644 --- a/src/southbridge/amd/common/reset.h +++ b/src/southbridge/amd/common/reset.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_SB_RESET_H_ #define _AMD_SB_RESET_H_ diff --git a/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl b/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl index 89189b8de9..4571314c66 100644 --- a/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl +++ b/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ OperationRegion(IMIO, SystemIO, 0x3E, 0x02) Field(IMIO , ByteAcc, NoLock, Preserve) { diff --git a/src/southbridge/amd/pi/hudson/acpi/audio.asl b/src/southbridge/amd/pi/hudson/acpi/audio.asl index bac56b0d50..2c27046353 100644 --- a/src/southbridge/amd/pi/hudson/acpi/audio.asl +++ b/src/southbridge/amd/pi/hudson/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(AZHD) { /* 0:14.2 - HD Audio */ Name(_ADR, 0x00140002) diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index f0eb1fd1ec..8051442d34 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* System Bus */ /* _SB.PCI0 */ diff --git a/src/southbridge/amd/pi/hudson/acpi/lpc.asl b/src/southbridge/amd/pi/hudson/acpi/lpc.asl index 001dd766cf..bc6003bc29 100644 --- a/src/southbridge/amd/pi/hudson/acpi/lpc.asl +++ b/src/southbridge/amd/pi/hudson/acpi/lpc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* 0:14.3 - LPC */ Device(LIBR) { diff --git a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl index 17e1deaf57..e326063918 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ diff --git a/src/southbridge/amd/pi/hudson/acpi/pcie.asl b/src/southbridge/amd/pi/hudson/acpi/pcie.asl index bffae17969..e5ccca24ef 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCI IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl index 914d9ae607..6463ec3412 100644 --- a/src/southbridge/amd/pi/hudson/acpi/usb.asl +++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* 0:12.0 - OHCI */ Device(UOH1) { diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index fd630ce13f..8bd67ed103 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AMD_PCI_INT_DEFS_H #define AMD_PCI_INT_DEFS_H diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index 5682e88e29..57e143c3e0 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index 9b71c7d47e..d0c3646fd5 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/chip.h b/src/southbridge/amd/pi/hudson/chip.h index 9de5cd1856..080ffa9dec 100644 --- a/src/southbridge/amd/pi/hudson/chip.h +++ b/src/southbridge/amd/pi/hudson/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_CHIP_H #define HUDSON_CHIP_H diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 9d04d2775d..126a85c5da 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _HUDSON_EARLY_SETUP_C_ #define _HUDSON_EARLY_SETUP_C_ diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index 8d9d7b8b22..c0f1fafa3d 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8573c8bf4c..15fd6bb0c9 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * ACPI - create the Fixed ACPI Description Tables (FADT) diff --git a/src/southbridge/amd/pi/hudson/fchec.h b/src/southbridge/amd/pi/hudson/fchec.h index 04d0610a4b..1378c40e80 100644 --- a/src/southbridge/amd/pi/hudson/fchec.h +++ b/src/southbridge/amd/pi/hudson/fchec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_HUDSON_FCHEC__ #define __AMD_HUDSON_FCHEC__ diff --git a/src/southbridge/amd/pi/hudson/gpio.c b/src/southbridge/amd/pi/hudson/gpio.c index fc8e60bae3..03f63dac37 100644 --- a/src/southbridge/amd/pi/hudson/gpio.c +++ b/src/southbridge/amd/pi/hudson/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "gpio.h" diff --git a/src/southbridge/amd/pi/hudson/gpio.h b/src/southbridge/amd/pi/hudson/gpio.h index 0e3785a872..51dfe12870 100644 --- a/src/southbridge/amd/pi/hudson/gpio.h +++ b/src/southbridge/amd/pi/hudson/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _HUDSON_GPIO_H_ #define _HUDSON_GPIO_H_ diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 49d1ddf9ff..ef2a341ea6 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 74020555a2..3a6b541733 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 7c1044a006..c3d90341e0 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_H #define HUDSON_H diff --git a/src/southbridge/amd/pi/hudson/ide.c b/src/southbridge/amd/pi/hudson/ide.c index 69d95912d8..76e5ead8e4 100644 --- a/src/southbridge/amd/pi/hudson/ide.c +++ b/src/southbridge/amd/pi/hudson/ide.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 8ae0b084ec..461dcb1cd6 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/amd/pi/hudson/imc.h b/src/southbridge/amd/pi/hudson/imc.h index 434bd28226..33c46d6840 100644 --- a/src/southbridge/amd/pi/hudson/imc.h +++ b/src/southbridge/amd/pi/hudson/imc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_IMC_H #define HUDSON_IMC_H diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 239dda8e74..c50758256b 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index eec0180676..af5ebdb61d 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 7069fef55c..0a51a4f253 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PI_HUDSON_PCI_DEVS_H_ #define _PI_HUDSON_PCI_DEVS_H_ diff --git a/src/southbridge/amd/pi/hudson/pcie.c b/src/southbridge/amd/pi/hudson/pcie.c index b4329639ec..ccd687abea 100644 --- a/src/southbridge/amd/pi/hudson/pcie.c +++ b/src/southbridge/amd/pi/hudson/pcie.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index c1043342d7..2d90ae2aca 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 58e0c57e5a..4a210d709d 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index 01a23430ba..0a9baffdda 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index fd36a6fcf1..7564008998 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c index 8a97667c31..1c71c87948 100644 --- a/src/southbridge/amd/pi/hudson/smbus.c +++ b/src/southbridge/amd/pi/hudson/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_ diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index 2a78ef5f2a..e138eff059 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HUDSON_SMBUS_H #define HUDSON_SMBUS_H diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index d8910fd2c0..59dabdcf42 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c index c803852144..b48af69678 100644 --- a/src/southbridge/amd/pi/hudson/uart.c +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index e465c1484e..c882556b75 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/acpi/audio.asl b/src/southbridge/intel/bd82x6x/acpi/audio.asl index b0adf82c87..fbd60c6512 100644 --- a/src/southbridge/intel/bd82x6x/acpi/audio.asl +++ b/src/southbridge/intel/bd82x6x/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH HDA */ diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index ac42c7a327..8e99d49045 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl index 739e6d8915..a711a03b09 100644 --- a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl +++ b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index cd2ea09802..5b16c5e032 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 78db0ba498..c0e223b98a 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Cougar Point PCH support */ #include diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index 3a2f46b482..7355a5494d 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SATA Controller 0:1f.2 diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index 2060065740..458c1cd4c6 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Cougar Point USB support */ diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15178cbf9d..316fafcab4 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 8df42bde81..ef2ee0e55a 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 6d8e1f0848..94715de8dc 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 3bc3836545..184f72ad32 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index eeffd287ca..7e72aa9b74 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index efa6479a48..530f11affa 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 3e3a927c13..915a93599c 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 4d34877a4c..f3151af200 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 7749d5f41a..31aad178fc 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index c106f1eec3..719f94b067 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index ac10a936c4..dc5da793a3 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 91d710e2a0..27f45e359b 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 15cbd7663c..b1f3bfe861 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is a ramstage driver for the Intel Management Engine found in the diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 3131ba24da..2794f9bd62 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTEL_ME_H #define _INTEL_ME_H diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index e4167aeaa3..054c29f565 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is a ramstage driver for the Intel Management Engine found in the diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index f18f8124ac..a19fc01fd9 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "me.h" diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 08b5ebd8ed..25c392d7f1 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 0839ecfb77..cb3188052b 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3af2624662..18383f6bff 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 634371b0aa..459ed4648d 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 84309a4e9a..7baf67d3c7 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 4d2ac1c1d9..e09e07246b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index ba9b9766e6..11568b3096 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 8a9cb86ca1..78ac08bf1c 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 26d2bd1688..1d7120dc09 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 7af3b08f46..8696d59abf 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl index ad33d4b4f9..a3076f988e 100644 --- a/src/southbridge/intel/common/acpi/pcie.asl +++ b/src/southbridge/intel/common/acpi/pcie.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel 6/7 Series PCH PCIe support */ diff --git a/src/southbridge/intel/common/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl index 86cc0bdf87..34ab79b78c 100644 --- a/src/southbridge/intel/common/acpi/pcie_port.asl +++ b/src/southbridge/intel/common/acpi/pcie_port.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Included in each PCIe Root Port device */ diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index 011f708c59..7451e44260 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The APM port can be used for generating software SMIs */ diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl index 89dfc57169..ed8b1b8945 100644 --- a/src/southbridge/intel/common/acpi/sleepstates.asl +++ b/src/southbridge/intel/common/acpi/sleepstates.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) #if !CONFIG(HAVE_ACPI_RESUME) diff --git a/src/southbridge/intel/common/acpi/smbus.asl b/src/southbridge/intel/common/acpi/smbus.asl index 8a1d1f9b64..9fc516fe54 100644 --- a/src/southbridge/intel/common/acpi/smbus.asl +++ b/src/southbridge/intel/common/acpi/smbus.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SMBus Controller 0:1f.3 diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 1df828e0fb..d1e0c8bb70 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h index 3d911c2315..dc2cae9847 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.h +++ b/src/southbridge/intel/common/acpi_pirq_gen.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTEL_COMMON_ACPI_PIRQ_GEN_H #define INTEL_COMMON_ACPI_PIRQ_GEN_H diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index d143e58565..4c6cc63466 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 568806d630..34d8c4839c 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index 60c6e551c2..b0a89f39fb 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTEL_COMMON_GPIO_H #define INTEL_COMMON_GPIO_H diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index 851b3fb4b2..338527091d 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index eb8477af3f..e5bbdab2fb 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h index aa2b444666..bb10d4df08 100644 --- a/src/southbridge/intel/common/pciehp.h +++ b/src/southbridge/intel/common/pciehp.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H #define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2567b287c1..6175302d54 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h index 8738b03599..152eccfbc1 100644 --- a/src/southbridge/intel/common/pmbase.h +++ b/src/southbridge/intel/common/pmbase.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c index 997a053c27..d44d6195ce 100644 --- a/src/southbridge/intel/common/pmclib.c +++ b/src/southbridge/intel/common/pmclib.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h index a74380c5ea..e519360bbb 100644 --- a/src/southbridge/intel/common/pmclib.h +++ b/src/southbridge/intel/common/pmclib.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTEL_COMMON_PMCLIB_H #define INTEL_COMMON_PMCLIB_H diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 0a3bd4b6f7..5de5d41b5d 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index dc9fa1fa9e..f16aed12c7 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTEL_COMMON_PMUTIL_H #define INTEL_COMMON_PMUTIL_H diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 7a8bcea7db..cb3577ee82 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 53274e346d..620d9fae41 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h index c2610c6149..9b33998e7d 100644 --- a/src/southbridge/intel/common/rcba_pirq.h +++ b/src/southbridge/intel/common/rcba_pirq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H #define SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H diff --git a/src/southbridge/intel/common/reset.c b/src/southbridge/intel/common/reset.c index 5a23afa38e..892e3e6b7f 100644 --- a/src/southbridge/intel/common/reset.c +++ b/src/southbridge/intel/common/reset.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index 799d94e56d..f4ac9f0c8b 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/rtc.h b/src/southbridge/intel/common/rtc.h index 2d147286c2..ae472c9f95 100644 --- a/src/southbridge/intel/common/rtc.h +++ b/src/southbridge/intel/common/rtc.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_RTC_H #define SOUTHBRIDGE_INTEL_RTC_H diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 0fb6386d4c..17ac51105f 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index ca2b7a3b1b..8f9544b892 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 3fdee84d8c..7d4066da29 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 62708604c5..31b65428b1 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H #define SOUTHBRIDGE_INTEL_COMMON_TCO_H diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 9f5b0b5840..d6b05787d8 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index ce9bb33df7..b43348eda5 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index bbb56e6c86..57f347e914 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Declares assorted devices that falls under this southbridge. diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl index eb913678e6..c1dc508a96 100644 --- a/src/southbridge/intel/i82371eb/acpi/intx.asl +++ b/src/southbridge/intel/i82371eb/acpi/intx.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(IRQB, ResourceTemplate(){ IRQ(Level,ActiveLow,Shared){} }) diff --git a/src/southbridge/intel/i82371eb/acpi/isabridge.asl b/src/southbridge/intel/i82371eb/acpi/isabridge.asl index 86d6c6707b..55a0ca560e 100644 --- a/src/southbridge/intel/i82371eb/acpi/isabridge.asl +++ b/src/southbridge/intel/i82371eb/acpi/isabridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * ISA portions taken from QEMU acpi-dsdt.dsl. diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl index eaacccb58b..84a71c0c0d 100644 --- a/src/southbridge/intel/i82371eb/acpi/pirq.asl +++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Field (\_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve) { diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 8a8d99e155..9da9c23e53 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index ba17b7e973..b0fda29665 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index 31452a58cf..334eb62ade 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h index b4becce200..734a241d2e 100644 --- a/src/southbridge/intel/i82801dx/chip.h +++ b/src/southbridge/intel/i82801dx/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef I82801DX_CHIP_H #define I82801DX_CHIP_H diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index c447413831..1dd04b9138 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index 303c33b3bf..f01064c049 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 71c2b2fab6..35a0bc249e 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* the problem: we have 82801dbm support in fb1, and 82801er in fb2. * fb1 code is what we want, fb2 structure is needed however. diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c index c94779b0f4..0c8408ca99 100644 --- a/src/southbridge/intel/i82801dx/ide.c +++ b/src/southbridge/intel/i82801dx/ide.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index b7eba17da6..7c9424c97c 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 1882fcb26c..c556573594 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ typedef struct { /* Miscellaneous */ diff --git a/src/southbridge/intel/i82801dx/pci.c b/src/southbridge/intel/i82801dx/pci.c index 837e3401bc..e0f6802ddd 100644 --- a/src/southbridge/intel/i82801dx/pci.c +++ b/src/southbridge/intel/i82801dx/pci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 26dfc60e5b..c81dabe1bc 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 96bf36ceeb..6a3f32bacd 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c index f6cb6e48f4..f02d70808e 100644 --- a/src/southbridge/intel/i82801dx/usb.c +++ b/src/southbridge/intel/i82801dx/usb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c index 9d48b8996a..53fece054a 100644 --- a/src/southbridge/intel/i82801dx/usb2.c +++ b/src/southbridge/intel/i82801dx/usb2.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 606faa4c38..ad7c636312 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/acpi/ac97.asl b/src/southbridge/intel/i82801gx/acpi/ac97.asl index 1ed067f83b..6daf941861 100644 --- a/src/southbridge/intel/i82801gx/acpi/ac97.asl +++ b/src/southbridge/intel/i82801gx/acpi/ac97.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel i82801G AC'97 Audio and Modem */ diff --git a/src/southbridge/intel/i82801gx/acpi/audio.asl b/src/southbridge/intel/i82801gx/acpi/audio.asl index 49b9bc4363..9a3da662c5 100644 --- a/src/southbridge/intel/i82801gx/acpi/audio.asl +++ b/src/southbridge/intel/i82801gx/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel i82801G HDA */ diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 28e79e9f33..d71b1e0e4c 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 6bb06a242f..191797954d 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel 82801Gx support */ diff --git a/src/southbridge/intel/i82801gx/acpi/irqlinks.asl b/src/southbridge/intel/i82801gx/acpi/irqlinks.asl index 0bfdbdedad..ee98996fff 100644 --- a/src/southbridge/intel/i82801gx/acpi/irqlinks.asl +++ b/src/southbridge/intel/i82801gx/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 29014ded85..2940c2ffd2 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 diff --git a/src/southbridge/intel/i82801gx/acpi/pata.asl b/src/southbridge/intel/i82801gx/acpi/pata.asl index 4833dbce92..02e543b086 100644 --- a/src/southbridge/intel/i82801gx/acpi/pata.asl +++ b/src/southbridge/intel/i82801gx/acpi/pata.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel PATA Controller 0:1f.1 diff --git a/src/southbridge/intel/i82801gx/acpi/pci.asl b/src/southbridge/intel/i82801gx/acpi/pci.asl index 4820830c6b..2209a940bd 100644 --- a/src/southbridge/intel/i82801gx/acpi/pci.asl +++ b/src/southbridge/intel/i82801gx/acpi/pci.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel PCI to PCI bridge 0:1e.0 diff --git a/src/southbridge/intel/i82801gx/acpi/sata.asl b/src/southbridge/intel/i82801gx/acpi/sata.asl index 5c22e623ae..2eabdca829 100644 --- a/src/southbridge/intel/i82801gx/acpi/sata.asl +++ b/src/southbridge/intel/i82801gx/acpi/sata.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SATA Controller 0:1f.2 diff --git a/src/southbridge/intel/i82801gx/acpi/usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl index 1ea75a042d..b303fc6624 100644 --- a/src/southbridge/intel/i82801gx/acpi/usb.asl +++ b/src/southbridge/intel/i82801gx/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel i82801G USB support */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index c18eb4b818..737a2db6c1 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 5376234414..9164c585f9 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 48f50c21e0..3a8e6fbf76 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c index 7543a777d5..4143f48594 100644 --- a/src/southbridge/intel/i82801gx/early_cir.c +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index fa578f7cec..29b914f153 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 45844c4cf3..ea639f9fc4 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 0be9e28ee2..5df36ddc81 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index dbc1430128..b42aeb6f68 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 2bb6be4312..16236c1ffb 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ce5d82f3ed..8949e8d7e7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/nic.c b/src/southbridge/intel/i82801gx/nic.c index b7b061fb65..899d1d23d8 100644 --- a/src/southbridge/intel/i82801gx/nic.c +++ b/src/southbridge/intel/i82801gx/nic.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This code should work for all ICH* southbridges with a NIC. */ diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 0b12d95f00..980ab0bce0 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index c8e7346208..432ad3e715 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 8ebbd8118f..7efaca9130 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index a658057e11..95d0482aac 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index fb15ba5825..d533b8776a 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f8c8bec8eb..d19ee1191b 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 21d1a6b491..0e85b1c1eb 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 368eebfffa..399b166c37 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/acpi/audio.asl b/src/southbridge/intel/i82801ix/acpi/audio.asl index 94504af7ec..df069b36d4 100644 --- a/src/southbridge/intel/i82801ix/acpi/audio.asl +++ b/src/southbridge/intel/i82801ix/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel i82801I HDA */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index f3a355f71e..6778fe7f7e 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 9844c3437f..2075326d46 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel 82801Ix support */ diff --git a/src/southbridge/intel/i82801ix/acpi/irqlinks.asl b/src/southbridge/intel/i82801ix/acpi/irqlinks.asl index 0bfdbdedad..ee98996fff 100644 --- a/src/southbridge/intel/i82801ix/acpi/irqlinks.asl +++ b/src/southbridge/intel/i82801ix/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index 1d720f0119..d997fd7950 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 diff --git a/src/southbridge/intel/i82801ix/acpi/pci.asl b/src/southbridge/intel/i82801ix/acpi/pci.asl index 7711e915d6..592c609646 100644 --- a/src/southbridge/intel/i82801ix/acpi/pci.asl +++ b/src/southbridge/intel/i82801ix/acpi/pci.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel PCI to PCI bridge 0:1e.0 diff --git a/src/southbridge/intel/i82801ix/acpi/sata.asl b/src/southbridge/intel/i82801ix/acpi/sata.asl index 19028ed639..bd2f8b474c 100644 --- a/src/southbridge/intel/i82801ix/acpi/sata.asl +++ b/src/southbridge/intel/i82801ix/acpi/sata.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Note: Some BIOSes put the S-ATA code into an SSDT to make it easily // pluggable diff --git a/src/southbridge/intel/i82801ix/acpi/usb.asl b/src/southbridge/intel/i82801ix/acpi/usb.asl index cba9b07b40..a44cb46bd2 100644 --- a/src/southbridge/intel/i82801ix/acpi/usb.asl +++ b/src/southbridge/intel/i82801ix/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel i82801I USB support */ diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 90c542dd73..4251892d25 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 31d99c785c..e7bc5e181b 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index 2f9012398d..45f7dd7562 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 882d725c46..da51c6556f 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 7c4f5b2c79..b118e74644 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 65492d64ce..364ffe4e56 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 7feed34610..f26d584a38 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d155e22836..52a57911f1 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index f097f50e02..923056c7a8 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index ce2b9a36c7..0954daa897 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H #define SOUTHBRIDGE_INTEL_I82801IX_NVS_H diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c index 5b14ab0cc1..351105eca2 100644 --- a/src/southbridge/intel/i82801ix/pci.c +++ b/src/southbridge/intel/i82801ix/pci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index d66a4bd1d1..d170f0de44 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 49d60f285f..b6b72e3c1b 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index fecf71b563..6a98701c6a 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 6e7463fcd3..30be71fedc 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -1,18 +1,7 @@ /* * This file is part of the coreboot project. * - * 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ + * 2012 secunet Security Networks AG SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 1bfe85c502..8a198487e8 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 4d49af4f5b..dce393f042 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 7eb7243147..14996165be 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/acpi/audio.asl b/src/southbridge/intel/i82801jx/acpi/audio.asl index 327e10fa99..d1dd38476c 100644 --- a/src/southbridge/intel/i82801jx/acpi/audio.asl +++ b/src/southbridge/intel/i82801jx/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel i82801L HDA */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 8a8b40bb26..ce810ebaa4 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index e63c23bc43..a8e151ba63 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel 82801Ix support */ diff --git a/src/southbridge/intel/i82801jx/acpi/irqlinks.asl b/src/southbridge/intel/i82801jx/acpi/irqlinks.asl index 0bfdbdedad..ee98996fff 100644 --- a/src/southbridge/intel/i82801jx/acpi/irqlinks.asl +++ b/src/southbridge/intel/i82801jx/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index b903aa7b45..3c74174c6c 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 diff --git a/src/southbridge/intel/i82801jx/acpi/pci.asl b/src/southbridge/intel/i82801jx/acpi/pci.asl index f8a435e159..0a4b0b33cf 100644 --- a/src/southbridge/intel/i82801jx/acpi/pci.asl +++ b/src/southbridge/intel/i82801jx/acpi/pci.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel PCI to PCI bridge 0:1e.0 diff --git a/src/southbridge/intel/i82801jx/acpi/sata.asl b/src/southbridge/intel/i82801jx/acpi/sata.asl index 19028ed639..bd2f8b474c 100644 --- a/src/southbridge/intel/i82801jx/acpi/sata.asl +++ b/src/southbridge/intel/i82801jx/acpi/sata.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Note: Some BIOSes put the S-ATA code into an SSDT to make it easily // pluggable diff --git a/src/southbridge/intel/i82801jx/acpi/usb.asl b/src/southbridge/intel/i82801jx/acpi/usb.asl index 6432ed030e..a299d440c1 100644 --- a/src/southbridge/intel/i82801jx/acpi/usb.asl +++ b/src/southbridge/intel/i82801jx/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel i82801J USB support */ diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 3ed6c32eb9..ae3f1f3e00 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index d82323c682..50882111aa 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index c10c421fe4..43d83acbb6 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 6284c62578..37bae66885 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0a964be2ea..0d93415501 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index 214a263a15..e55735b4a1 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 0139613262..219027985b 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 652c10db6f..91f92859c1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 0b72113b5d..95bfa269db 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c index 718f45ade6..7a30b82118 100644 --- a/src/southbridge/intel/i82801jx/pci.c +++ b/src/southbridge/intel/i82801jx/pci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 08b0e98f52..dba1a6519e 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 69df88c4cb..56ed7708e3 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 413471421d..5951a82913 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 3435287813..5c1edbc307 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index d2744c8bd5..28d4c7b688 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 8290112d63..551aa500df 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index ce76db0682..3be4082a21 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* for io APIC 1461 */ #define MBAR 0x10 diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 1f4aa501a8..c7b189ac77 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index cb6ace8dab..739a38b358 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index fe5cc2ea1d..8a442a1c68 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 82cb29fb35..60bc41a33e 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h index fbbb0a17e8..b1c93dd836 100644 --- a/src/southbridge/intel/ibexpeak/chip.h +++ b/src/southbridge/intel/ibexpeak/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H #define SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c index 9aac07b075..296a042696 100644 --- a/src/southbridge/intel/ibexpeak/early_cir.c +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 00d58221a8..84a0bdedcb 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 4db81bca4b..0c99a2245f 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index 4fdb1e5a4a..0f30c9c989 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 73f19c7ab7..395919e676 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 1baa7df6bb..c582048853 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index e8974d8491..5f6be1d163 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is a ramstage driver for the Intel Management Engine found in the diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 2864c51a91..9c592f3f43 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTEL_ME_H #define _INTEL_ME_H diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 85d858b025..c091b6f5d3 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "vendorcode/google/chromeos/gnvs.h" diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 1b9f51533d..29c3a7635b 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 6ec17a7c47..fc20660e65 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 555b5ca758..e6fcde60c9 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index b06b1cd135..6d95fc6589 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 937078dfb4..a7c1e5feaf 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 2664c65ea7..3f0b7bf07b 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index f4b975a4a0..f513628802 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8bf40f5fbb..48e2a29bc8 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index a953e7daa2..32c4010fd7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH HDA */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index a8de07ce7c..ad7df7f61c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl b/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl index 0bfdbdedad..ee98996fff 100644 --- a/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl +++ b/src/southbridge/intel/lynxpoint/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index e8d8ba85ee..197c087722 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 diff --git a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl index b165cfa5e3..b79a4df1ca 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* LynxPoint-H */ diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 9fcbeca8ff..3a59931ba7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Cougar Point PCH support */ diff --git a/src/southbridge/intel/lynxpoint/acpi/sata.asl b/src/southbridge/intel/lynxpoint/acpi/sata.asl index 49adadc86b..aa964d0cff 100644 --- a/src/southbridge/intel/lynxpoint/acpi/sata.asl +++ b/src/southbridge/intel/lynxpoint/acpi/sata.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SATA Controller 0:1f.2 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 8dd0b1ddc1..52bec4ed1c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LynxPoint Serial IO Devices in ACPI Mode diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 790f2fec19..15155fe1a2 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Cougar Point USB support */ diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index eb505ed42e..b24740bb73 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 0660072790..67b95cdca0 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 517516d120..4876e04633 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index fa5d26c55d..b217eac285 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 6dab182781..5c8324e830 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 4d34877a4c..f3151af200 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 81aceac4b8..2f28369d53 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 3de3532c78..d19250cf6b 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 31618e805f..b5de82bc51 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h index 8c6ccd01cd..e1e55597e2 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ b/src/southbridge/intel/lynxpoint/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LYNXPOINT_HDA_VERB_H #define LYNXPOINT_HDA_VERB_H diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 60b612ca5b..8b394b4f8c 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 84b5690c17..5a0ecea037 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTEL_LYNXPOINT_LP_GPIO_H #define INTEL_LYNXPOINT_LP_GPIO_H diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index bb0d997ad6..21da7d24d7 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 09d12a04dc..46ec6e6d38 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTEL_ME_H #define _INTEL_ME_H diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index fd8d3f5479..c5562c5cfc 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is a ramstage driver for the Intel Management Engine found in the diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index c26d63ad17..6cb187e1b0 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "me.h" diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index b170141204..c35b4b5ce0 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 1413d9441d..a09f28e7a7 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0a62803ca2..d583992ab9 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 83eac8d023..0ca49b802c 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index f7762ac93c..14490a3a6d 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Helper functions for dealing with power management registers diff --git a/src/southbridge/intel/lynxpoint/rcba.c b/src/southbridge/intel/lynxpoint/rcba.c index 71f46fc5b0..7e15641ed2 100644 --- a/src/southbridge/intel/lynxpoint/rcba.c +++ b/src/southbridge/intel/lynxpoint/rcba.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 8570dab197..22be4d169d 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index da2a47a033..4591566e1b 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 3dc8ac4156..ca4ac62735 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 6aef493ee1..05b5bb5c43 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 58729105f1..e156b347c1 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 574b6d17f5..681d098374 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 99e5314e4d..e027f040dc 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/southbridge/ricoh/rl5c476/chip.h b/src/southbridge/ricoh/rl5c476/chip.h index 830661895e..f78e42aa9f 100644 --- a/src/southbridge/ricoh/rl5c476/chip.h +++ b/src/southbridge/ricoh/rl5c476/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOUTHBRIDGE_RICOH_RL5C476 #define _SOUTHBRIDGE_RICOH_RL5C476 diff --git a/src/southbridge/ti/pci1x2x/chip.h b/src/southbridge/ti/pci1x2x/chip.h index f6c8d4110f..3801d99b7f 100644 --- a/src/southbridge/ti/pci1x2x/chip.h +++ b/src/southbridge/ti/pci1x2x/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOUTHBRIDGE_TI_PCI1X2X_H #define SOUTHBRIDGE_TI_PCI1X2X_H diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index 48305215e1..af53d795c8 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 3ef916fa1bdf83e912c01019083137cc41672c3c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:49:13 +0200 Subject: [PATCH 0773/1463] src/vendorcode: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I49dc615178aaef278d6445376842d45152759234 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40060 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/vendorcode/amd/include/cbtypes.h | 16 ++-------------- src/vendorcode/amd/pi/00670F00/agesa_headers.h | 16 ++-------------- .../amd/pi/00670F00/check_for_wrapper.h | 16 ++-------------- .../cavium/include/bdk/bdk-devicetree.h | 17 ++--------------- src/vendorcode/eltan/security/mboot/mboot.c | 15 ++------------- src/vendorcode/eltan/security/mboot/mboot.h | 15 ++------------- .../eltan/security/mboot/mboot_func.c | 15 ++------------- .../eltan/security/verified_boot/vboot_check.c | 15 ++------------- .../eltan/security/verified_boot/vboot_check.h | 15 ++------------- src/vendorcode/google/chromeos/acpi.c | 15 ++------------- src/vendorcode/google/chromeos/acpi/amac.asl | 16 ++-------------- .../google/chromeos/acpi/chromeos.asl | 15 ++------------- src/vendorcode/google/chromeos/acpi/gnvs.asl | 15 ++------------- src/vendorcode/google/chromeos/acpi/ramoops.asl | 16 ++-------------- src/vendorcode/google/chromeos/acpi/vpd.asl | 16 ++-------------- src/vendorcode/google/chromeos/chromeos.h | 15 ++------------- .../google/chromeos/cr50_enable_update.c | 15 ++------------- src/vendorcode/google/chromeos/dsm_calib.c | 15 ++------------- src/vendorcode/google/chromeos/elog.c | 15 ++------------- src/vendorcode/google/chromeos/gnvs.c | 15 ++------------- src/vendorcode/google/chromeos/gnvs.h | 15 ++------------- src/vendorcode/google/chromeos/ramoops.c | 15 ++------------- src/vendorcode/google/chromeos/sar.c | 15 ++------------- src/vendorcode/google/chromeos/symbols.h | 15 ++------------- src/vendorcode/google/chromeos/tpm2.c | 15 ++------------- .../google/chromeos/vpd_calibration.c | 15 ++------------- src/vendorcode/google/chromeos/vpd_mac.c | 15 ++------------- src/vendorcode/google/chromeos/vpd_serialno.c | 15 ++------------- src/vendorcode/google/chromeos/watchdog.c | 15 ++------------- src/vendorcode/google/chromeos/wrdd.c | 15 ++------------- src/vendorcode/google/smbios.c | 15 ++------------- src/vendorcode/siemens/hwilib/hwilib.c | 15 ++------------- src/vendorcode/siemens/hwilib/hwilib.h | 15 ++------------- 33 files changed, 66 insertions(+), 437 deletions(-) diff --git a/src/vendorcode/amd/include/cbtypes.h b/src/vendorcode/amd/include/cbtypes.h index 4a6765d411..99b43d4f53 100644 --- a/src/vendorcode/amd/include/cbtypes.h +++ b/src/vendorcode/amd/include/cbtypes.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CBTYPES_H_ #define _CBTYPES_H_ diff --git a/src/vendorcode/amd/pi/00670F00/agesa_headers.h b/src/vendorcode/amd/pi/00670F00/agesa_headers.h index c9de8b7edc..0f49b7a91c 100644 --- a/src/vendorcode/amd/pi/00670F00/agesa_headers.h +++ b/src/vendorcode/amd/pi/00670F00/agesa_headers.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AGESA_HEADERS_H__ #define __AGESA_HEADERS_H__ diff --git a/src/vendorcode/amd/pi/00670F00/check_for_wrapper.h b/src/vendorcode/amd/pi/00670F00/check_for_wrapper.h index 86d3b3904b..f99965dcc1 100644 --- a/src/vendorcode/amd/pi/00670F00/check_for_wrapper.h +++ b/src/vendorcode/amd/pi/00670F00/check_for_wrapper.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Do not use header guards on this file */ diff --git a/src/vendorcode/cavium/include/bdk/bdk-devicetree.h b/src/vendorcode/cavium/include/bdk/bdk-devicetree.h index 559e4b531f..0716387d7b 100644 --- a/src/vendorcode/cavium/include/bdk/bdk-devicetree.h +++ b/src/vendorcode/cavium/include/bdk/bdk-devicetree.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ struct bdk_devicetree_key_value { const char *key; diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index 47a5280f84..e08c2de759 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 4e4179e1c4..807bc05b41 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MBOOT_H #define MBOOT_H diff --git a/src/vendorcode/eltan/security/mboot/mboot_func.c b/src/vendorcode/eltan/security/mboot/mboot_func.c index b0e4aa0075..b6b3d023a2 100644 --- a/src/vendorcode/eltan/security/mboot/mboot_func.c +++ b/src/vendorcode/eltan/security/mboot/mboot_func.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 63e4608553..174a37824d 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h index 722064da76..9cb11d5384 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.h +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VBOOT_CHECK_H #define VBOOT_CHECK_H diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 39939dcb15..fad1256b0f 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #if CONFIG(GENERIC_GPIO_LIB) diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl index d8661be763..2eb7fa0f22 100644 --- a/src/vendorcode/google/chromeos/acpi/amac.asl +++ b/src/vendorcode/google/chromeos/acpi/amac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The Realtek r8152 driver in the Linux kernel supports a MAC address diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index b1b58315cc..2b7dc4ac4b 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 7f87d7425e..c819daa02c 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is the ChromeOS specific ACPI information needed by * the mainboard's chromeos.asl diff --git a/src/vendorcode/google/chromeos/acpi/ramoops.asl b/src/vendorcode/google/chromeos/acpi/ramoops.asl index 4262d9457d..bbf1a39b27 100644 --- a/src/vendorcode/google/chromeos/acpi/ramoops.asl +++ b/src/vendorcode/google/chromeos/acpi/ramoops.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl index eded65b938..be089d4047 100644 --- a/src/vendorcode/google/chromeos/acpi/vpd.asl +++ b/src/vendorcode/google/chromeos/acpi/vpd.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This device provides an ACPI interface to read VPD keys from either diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 7d610148e0..d53109ca3b 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __CHROMEOS_H__ #define __CHROMEOS_H__ diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index 2fc7158dcf..fa562a2403 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/dsm_calib.c b/src/vendorcode/google/chromeos/dsm_calib.c index 341e428845..c1b6fde7d9 100644 --- a/src/vendorcode/google/chromeos/dsm_calib.c +++ b/src/vendorcode/google/chromeos/dsm_calib.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index a723319d9b..9562e7970b 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 89db0ee20f..f6ea438593 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 66de15f27f..4a2415a63b 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H #define __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 78b5b4d372..fc41989e8a 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index f514928862..1cd4babeec 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/symbols.h b/src/vendorcode/google/chromeos/symbols.h index e1c3770957..377ad118fc 100644 --- a/src/vendorcode/google/chromeos/symbols.h +++ b/src/vendorcode/google/chromeos/symbols.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __CHROMEOS_SYMBOLS_H #define __CHROMEOS_SYMBOLS_H diff --git a/src/vendorcode/google/chromeos/tpm2.c b/src/vendorcode/google/chromeos/tpm2.c index 6feba27f8d..06c3973b9c 100644 --- a/src/vendorcode/google/chromeos/tpm2.c +++ b/src/vendorcode/google/chromeos/tpm2.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/vpd_calibration.c b/src/vendorcode/google/chromeos/vpd_calibration.c index 55da66a04a..ea6294dbac 100644 --- a/src/vendorcode/google/chromeos/vpd_calibration.c +++ b/src/vendorcode/google/chromeos/vpd_calibration.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/vpd_mac.c b/src/vendorcode/google/chromeos/vpd_mac.c index 04b58191d0..87a9c464db 100644 --- a/src/vendorcode/google/chromeos/vpd_mac.c +++ b/src/vendorcode/google/chromeos/vpd_mac.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/vpd_serialno.c b/src/vendorcode/google/chromeos/vpd_serialno.c index a186aefa96..2fe32c3fec 100644 --- a/src/vendorcode/google/chromeos/vpd_serialno.c +++ b/src/vendorcode/google/chromeos/vpd_serialno.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c index f763affcea..11794c999a 100644 --- a/src/vendorcode/google/chromeos/watchdog.c +++ b/src/vendorcode/google/chromeos/watchdog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c index 23fd79ef6f..11e15fe407 100644 --- a/src/vendorcode/google/chromeos/wrdd.c +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/vendorcode/google/smbios.c b/src/vendorcode/google/smbios.c index 2b8f6c23d9..9a061c3ba0 100644 --- a/src/vendorcode/google/smbios.c +++ b/src/vendorcode/google/smbios.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index fde97678bf..ba41a85c30 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index a4c376ed6e..905b4b0d2c 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SIEMENS_HWI_LIB_H_ #define SIEMENS_HWI_LIB_H_ From a019524d35f92725b527ebc10f02d2738b803a61 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 1 Apr 2020 13:34:54 +0200 Subject: [PATCH 0774/1463] sb/intel/bd82x6x: Use SPDX headers Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I08b4f5f53e493371848f588e6976d349e56b0620 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40019 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/Kconfig | 13 +------------ src/southbridge/intel/bd82x6x/Makefile.inc | 13 +------------ src/southbridge/intel/bd82x6x/early_thermal.c | 16 ++-------------- 3 files changed, 4 insertions(+), 38 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 2124d919a9..534d110e70 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -1,16 +1,5 @@ -## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## config SOUTHBRIDGE_INTEL_BD82X6X bool diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 15ff98d386..ca4ac749f7 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -1,16 +1,5 @@ -## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 6cfdb56944..ac7a3a4c90 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include From f23ae0b0f6c449d5925a1d0bf08ce61edd987c68 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:12 +0200 Subject: [PATCH 0775/1463] src/cpu: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/cpu/amd/agesa/family14/acpi/cpu.asl | 14 ++------------ src/cpu/amd/agesa/family14/chip_name.c | 14 ++------------ src/cpu/amd/agesa/family14/fixme.c | 14 ++------------ src/cpu/amd/agesa/family14/model_14_init.c | 14 ++------------ src/cpu/amd/agesa/family15tn/acpi/cpu.asl | 14 ++------------ src/cpu/amd/agesa/family15tn/chip_name.c | 14 ++------------ src/cpu/amd/agesa/family15tn/fixme.c | 14 ++------------ src/cpu/amd/agesa/family15tn/model_15_init.c | 14 ++------------ src/cpu/amd/agesa/family16kb/acpi/cpu.asl | 14 ++------------ src/cpu/amd/agesa/family16kb/chip_name.c | 14 ++------------ src/cpu/amd/agesa/family16kb/fixme.c | 14 ++------------ src/cpu/amd/agesa/family16kb/model_16_init.c | 14 ++------------ src/cpu/amd/mtrr/amd_mtrr.c | 14 ++------------ src/cpu/amd/pi/00630F01/acpi/cpu.asl | 14 ++------------ src/cpu/amd/pi/00630F01/chip_name.c | 14 ++------------ src/cpu/amd/pi/00630F01/fixme.c | 14 ++------------ src/cpu/amd/pi/00630F01/model_15_init.c | 14 ++------------ src/cpu/amd/pi/00660F01/acpi/cpu.asl | 14 ++------------ src/cpu/amd/pi/00660F01/chip_name.c | 14 ++------------ src/cpu/amd/pi/00660F01/fixme.c | 14 ++------------ src/cpu/amd/pi/00660F01/model_15_init.c | 14 ++------------ src/cpu/amd/pi/00730F01/acpi/cpu.asl | 14 ++------------ src/cpu/amd/pi/00730F01/chip_name.c | 14 ++------------ src/cpu/amd/pi/00730F01/fixme.c | 14 ++------------ src/cpu/amd/pi/00730F01/microcode_fam16h.c | 14 ++------------ src/cpu/amd/pi/00730F01/model_16_init.c | 14 ++------------ src/cpu/amd/pi/00730F01/update_microcode.c | 14 ++------------ src/cpu/amd/smm/smm_init.c | 14 ++------------ src/cpu/intel/car/bootblock.c | 14 ++------------ src/cpu/intel/car/core2/cache_as_ram.S | 14 ++------------ src/cpu/intel/car/non-evict/cache_as_ram.S | 14 ++------------ src/cpu/intel/car/non-evict/exit_car.S | 14 ++------------ src/cpu/intel/car/p3/cache_as_ram.S | 14 ++------------ src/cpu/intel/car/p4-netburst/cache_as_ram.S | 14 ++------------ src/cpu/intel/car/p4-netburst/exit_car.S | 14 ++------------ src/cpu/intel/car/romstage.c | 14 ++------------ src/cpu/intel/common/acpi/cpu.asl | 15 ++------------- src/cpu/intel/common/common.h | 15 ++------------- src/cpu/intel/common/common_init.c | 15 ++------------- src/cpu/intel/common/fsb.c | 14 ++------------ src/cpu/intel/common/hyperthreading.c | 14 ++------------ src/cpu/intel/fit/fit.S | 14 ++------------ src/cpu/intel/fit/fit.ld | 14 ++------------ src/cpu/intel/haswell/acpi.c | 15 ++------------- src/cpu/intel/haswell/bootblock.c | 14 ++------------ src/cpu/intel/haswell/chip.h | 14 ++------------ src/cpu/intel/haswell/finalize.c | 15 ++------------- src/cpu/intel/haswell/haswell.h | 15 ++------------- src/cpu/intel/haswell/haswell_init.c | 15 ++------------- src/cpu/intel/haswell/romstage.c | 14 ++------------ src/cpu/intel/haswell/smmrelocate.c | 14 ++------------ src/cpu/intel/hyperthreading/intel_sibling.c | 14 ++------------ src/cpu/intel/microcode/microcode.c | 14 ++------------ src/cpu/intel/microcode/microcode_asm.S | 14 ++------------ src/cpu/intel/model_1067x/chip.h | 14 ++------------ src/cpu/intel/model_1067x/model_1067x_init.c | 15 ++------------- src/cpu/intel/model_1067x/mp_init.c | 15 ++------------- src/cpu/intel/model_106cx/model_106cx_init.c | 14 ++------------ src/cpu/intel/model_2065x/acpi.c | 15 ++------------- src/cpu/intel/model_2065x/chip.h | 14 ++------------ src/cpu/intel/model_2065x/finalize.c | 15 ++------------- src/cpu/intel/model_2065x/model_2065x.h | 15 ++------------- src/cpu/intel/model_2065x/model_2065x_init.c | 15 ++------------- src/cpu/intel/model_206ax/acpi.c | 15 ++------------- src/cpu/intel/model_206ax/bootblock.c | 14 ++------------ src/cpu/intel/model_206ax/chip.h | 14 ++------------ src/cpu/intel/model_206ax/common.c | 15 ++------------- src/cpu/intel/model_206ax/finalize.c | 15 ++------------- src/cpu/intel/model_206ax/model_206ax.h | 15 ++------------- src/cpu/intel/model_206ax/model_206ax_init.c | 15 ++------------- src/cpu/intel/model_65x/model_65x_init.c | 14 ++------------ src/cpu/intel/model_67x/model_67x_init.c | 14 ++------------ src/cpu/intel/model_68x/model_68x_init.c | 15 ++------------- src/cpu/intel/model_6bx/model_6bx_init.c | 15 ++------------- src/cpu/intel/model_6ex/model_6ex_init.c | 15 ++------------- src/cpu/intel/model_6fx/model_6fx_init.c | 15 ++------------- src/cpu/intel/model_6xx/model_6xx_init.c | 14 ++------------ src/cpu/intel/model_f2x/model_f2x_init.c | 14 ++------------ src/cpu/intel/model_f3x/model_f3x_init.c | 14 ++------------ src/cpu/intel/model_f4x/model_f4x_init.c | 14 ++------------ src/cpu/intel/smm/gen1/smmrelocate.c | 14 ++------------ src/cpu/intel/smm/smm_reloc.c | 14 ++------------ src/cpu/intel/speedstep/acpi.c | 15 ++------------- src/cpu/intel/speedstep/acpi/cpu.asl | 14 ++------------ src/cpu/intel/speedstep/speedstep.c | 15 ++------------- src/cpu/intel/turbo/turbo.c | 15 ++------------- src/cpu/qemu-x86/bootblock.c | 14 ++------------ src/cpu/qemu-x86/cache_as_ram_bootblock.S | 14 ++------------ src/cpu/ti/am335x/bootblock.c | 14 ++------------ src/cpu/ti/am335x/bootblock_media.c | 14 ++------------ src/cpu/ti/am335x/cbmem.c | 14 ++------------ src/cpu/ti/am335x/dmtimer.c | 14 ++------------ src/cpu/ti/am335x/dmtimer.h | 14 ++------------ src/cpu/ti/am335x/header.ld | 14 ++------------ src/cpu/ti/am335x/memlayout.ld | 14 ++------------ src/cpu/ti/am335x/monotonic_timer.c | 14 ++------------ src/cpu/ti/am335x/nand.c | 14 ++------------ src/cpu/x86/16bit/entry16.ld | 14 ++------------ src/cpu/x86/16bit/reset16.inc | 14 ++------------ src/cpu/x86/16bit/reset16.ld | 14 ++------------ src/cpu/x86/32bit/entry32.inc | 14 ++------------ src/cpu/x86/64bit/entry64.inc | 15 ++------------- src/cpu/x86/backup_default_smm.c | 15 ++------------- src/cpu/x86/cache/cache.c | 14 ++------------ src/cpu/x86/fpu_enable.inc | 14 ++------------ src/cpu/x86/lapic/apic_timer.c | 14 ++------------ src/cpu/x86/lapic/boot_cpu.c | 14 ++------------ src/cpu/x86/lapic/lapic.c | 14 ++------------ src/cpu/x86/lapic/lapic_cpu_init.c | 14 ++------------ src/cpu/x86/lapic/secondary.S | 14 ++------------ src/cpu/x86/mp_init.c | 15 ++------------- src/cpu/x86/mtrr/debug.c | 14 ++------------ src/cpu/x86/mtrr/earlymtrr.c | 14 ++------------ src/cpu/x86/mtrr/xip_cache.c | 14 ++------------ src/cpu/x86/name/name.c | 14 ++------------ src/cpu/x86/pae/pgtbl.c | 14 ++------------ src/cpu/x86/sipi_vector.S | 15 ++------------- src/cpu/x86/smm/smihandler.c | 15 ++------------- src/cpu/x86/smm/smm.ld | 14 ++------------ src/cpu/x86/smm/smm_module_handler.c | 14 ++------------ src/cpu/x86/smm/smm_module_loader.c | 14 ++------------ src/cpu/x86/smm/smm_stub.S | 15 ++------------- src/cpu/x86/smm/smmhandler.S | 15 ++------------- src/cpu/x86/smm/smmrelocate.S | 15 ++------------- src/cpu/x86/smm/tseg_region.c | 14 ++------------ src/cpu/x86/sse_enable.inc | 14 ++------------ src/cpu/x86/tsc/delay_tsc.c | 14 ++------------ 127 files changed, 254 insertions(+), 1557 deletions(-) diff --git a/src/cpu/amd/agesa/family14/acpi/cpu.asl b/src/cpu/amd/agesa/family14/acpi/cpu.asl index b10fd56120..639b9a0940 100644 --- a/src/cpu/amd/agesa/family14/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family14/acpi/cpu.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Processor Object diff --git a/src/cpu/amd/agesa/family14/chip_name.c b/src/cpu/amd/agesa/family14/chip_name.c index 4b40ec2a16..c2ecd99d73 100644 --- a/src/cpu/amd/agesa/family14/chip_name.c +++ b/src/cpu/amd/agesa/family14/chip_name.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 658434d2c8..207ed98c7c 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 04e6f44df4..c8a5a6298d 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl index 19ec12b1ec..ef47443fec 100644 --- a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Processor Object diff --git a/src/cpu/amd/agesa/family15tn/chip_name.c b/src/cpu/amd/agesa/family15tn/chip_name.c index 876ef3a274..1fb2ef36e7 100644 --- a/src/cpu/amd/agesa/family15tn/chip_name.c +++ b/src/cpu/amd/agesa/family15tn/chip_name.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index 03c6503300..128b732db3 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index be3d58bb1b..7279e8a358 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl index 48505ebddf..d6f1c36b74 100644 --- a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Processor Object diff --git a/src/cpu/amd/agesa/family16kb/chip_name.c b/src/cpu/amd/agesa/family16kb/chip_name.c index caf2c1b2c1..235e9dedfc 100644 --- a/src/cpu/amd/agesa/family16kb/chip_name.c +++ b/src/cpu/amd/agesa/family16kb/chip_name.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 260efc2643..ef59e4eae2 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 3d53b5192b..67ce592523 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 2002dd8fcb..ca2aab57a0 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl index 19ec12b1ec..ef47443fec 100644 --- a/src/cpu/amd/pi/00630F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Processor Object diff --git a/src/cpu/amd/pi/00630F01/chip_name.c b/src/cpu/amd/pi/00630F01/chip_name.c index 68a7cfe62d..ebe06b91f6 100644 --- a/src/cpu/amd/pi/00630F01/chip_name.c +++ b/src/cpu/amd/pi/00630F01/chip_name.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 4699eeac26..5bd6fb670b 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index f1dd58ee5d..b47fd1c806 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl index 19ec12b1ec..ef47443fec 100644 --- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00660F01/acpi/cpu.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Processor Object diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c index f3f2bb52a6..319cb1245d 100644 --- a/src/cpu/amd/pi/00660F01/chip_name.c +++ b/src/cpu/amd/pi/00660F01/chip_name.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 1ce7432fe4..1e66bb9b07 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 78f3ce00ff..ac40a9b470 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl index 19ec12b1ec..ef47443fec 100644 --- a/src/cpu/amd/pi/00730F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00730F01/acpi/cpu.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Processor Object diff --git a/src/cpu/amd/pi/00730F01/chip_name.c b/src/cpu/amd/pi/00730F01/chip_name.c index 3ce3d0cf48..ce52df0026 100644 --- a/src/cpu/amd/pi/00730F01/chip_name.c +++ b/src/cpu/amd/pi/00730F01/chip_name.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 1ce7432fe4..1e66bb9b07 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00730F01/microcode_fam16h.c b/src/cpu/amd/pi/00730F01/microcode_fam16h.c index 1f1dbd90d1..78640707cf 100644 --- a/src/cpu/amd/pi/00730F01/microcode_fam16h.c +++ b/src/cpu/amd/pi/00730F01/microcode_fam16h.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 8edf0d9348..85626ffcc9 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c index 92af1af2a5..8dd2a4308f 100644 --- a/src/cpu/amd/pi/00730F01/update_microcode.c +++ b/src/cpu/amd/pi/00730F01/update_microcode.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 8f859f31e3..5d3aa7542f 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index e60a65a7b2..7caef8fcc2 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 73618d92f6..8fa7056343 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 4dee0a8002..2faa5f4e2c 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 5400ae51ce..a69c978faa 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 5262b1886d..753911e248 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fdeb0af8ec..e99ea81959 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 2d7fdaf8af..d818750f70 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index bd6a5a9b8c..e60ed728fe 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl index 153527ba7e..24c9a24239 100644 --- a/src/cpu/intel/common/acpi/cpu.asl +++ b/src/cpu/intel/common/acpi/cpu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* These come from the dynamically created CPU SSDT */ External (\_SB.CNOT, MethodObj) diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index f6b8e57ffd..8c8f34f207 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 9819ee7d87..0147a01447 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 3dfcd0b0ae..e01434f3ae 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index 4caf49e5b6..77fd59fcb5 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S index aa715eb467..effde79888 100644 --- a/src/cpu/intel/fit/fit.S +++ b/src/cpu/intel/fit/fit.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .section ".fit_pointer", "a", @progbits .code32 diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld index 6e30ea168a..424b8cea48 100644 --- a/src/cpu/intel/fit/fit.ld +++ b/src/cpu/intel/fit/fit.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ SECTIONS { . = 0xffffffc0; diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index fe2add772a..f8f139c8ea 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index e05936f59c..2110ad60c6 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index f3b97572da..4a0e81c052 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index b838f3476d..b160c18378 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 6ffb7e9a58..039e69084c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 66dca28dc5..aab830f1c6 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 34fd7b0458..44abf4bc7d 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index d259460dd7..9ac991353d 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index f602ccded7..d192b52d1b 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 90138be236..42e5140611 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Microcode update for Intel PIII and later CPUs */ diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 647f67c774..590f90a4db 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * input %esp: return address (not pointer to return address!) diff --git a/src/cpu/intel/model_1067x/chip.h b/src/cpu/intel/model_1067x/chip.h index 6cc004d918..83e845188f 100644 --- a/src/cpu/intel/model_1067x/chip.h +++ b/src/cpu/intel/model_1067x/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ struct cpu_intel_model_1067x_config { int c5 : 1; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 94adc8c327..e3ebb48e59 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index dd44582e1c..b4d062535c 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e529ffd595..93fdcae498 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 54da4e8af2..4f49dba410 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h index 50afca0ce1..27747d3887 100644 --- a/src/cpu/intel/model_2065x/chip.h +++ b/src/cpu/intel/model_2065x/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index a0a3fe227b..4bec18a471 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 0a07f3c898..114138f3a6 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CPU_INTEL_MODEL_2065X_H #define _CPU_INTEL_MODEL_2065X_H diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index e35d1e748d..a642afdfd4 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index c31bb5eaac..eba853794f 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index a504480bca..e1d7304b85 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 68cc6e5577..3408088cca 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c index b4017fb17d..05f5b50e82 100644 --- a/src/cpu/intel/model_206ax/common.c +++ b/src/cpu/intel/model_206ax/common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index a7754ae969..b7a67a202c 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 7017c128cb..64fb563015 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CPU_INTEL_MODEL_206AX_H #define _CPU_INTEL_MODEL_206AX_H diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 773940850d..4dfdc349b3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 87a2821d85..6ad3bcf33e 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 0d7afb25e0..8b4ecd9f47 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index fc2cac0db6..5b5f00c93c 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index 777432eddc..c24c0f20d4 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 5f61fb05b5..7897eb308b 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 2aefcc7add..ac61c419ae 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index bf319e45ec..1f2fb43323 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 04710a9e68..41efc69d52 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 48e3872225..0da7f1528e 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 941bee1466..35e5015d55 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 834ec0412e..018a478c1c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SMM relocation for i945-ivybridge. */ diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c index 860c095abf..cbbc2b3ec4 100644 --- a/src/cpu/intel/smm/smm_reloc.c +++ b/src/cpu/intel/smm/smm_reloc.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 71570b1e40..5e8330c76c 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl index 2d1a47bc78..8351fcc869 100644 --- a/src/cpu/intel/speedstep/acpi/cpu.asl +++ b/src/cpu/intel/speedstep/acpi/cpu.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* These come from the dynamically created CPU SSDT */ External (\_SB.CNOT, MethodObj) diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index ea418676e0..0fb115ea23 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index d0b49416d4..4f442fd8c2 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 35a241c32f..a1b3a7626d 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 1fa0018dc8..baf87c8dd8 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c index 93c29c034b..4fbdf9fb49 100644 --- a/src/cpu/ti/am335x/bootblock.c +++ b/src/cpu/ti/am335x/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c index 644665f6b6..e135706b68 100644 --- a/src/cpu/ti/am335x/bootblock_media.c +++ b/src/cpu/ti/am335x/bootblock_media.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index 2ecca65551..d0d9f618fa 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/ti/am335x/dmtimer.c b/src/cpu/ti/am335x/dmtimer.c index 480e8829de..28ca0e96b2 100644 --- a/src/cpu/ti/am335x/dmtimer.c +++ b/src/cpu/ti/am335x/dmtimer.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "dmtimer.h" diff --git a/src/cpu/ti/am335x/dmtimer.h b/src/cpu/ti/am335x/dmtimer.h index 42afa95d47..a99ed3cb98 100644 --- a/src/cpu/ti/am335x/dmtimer.h +++ b/src/cpu/ti/am335x/dmtimer.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __CPU_TI_AM335X_DMTIMER_H__ #define __CPU_TI_AM335X_DMTIMER_H__ diff --git a/src/cpu/ti/am335x/header.ld b/src/cpu/ti/am335x/header.ld index fed7b47c95..13630bf458 100644 --- a/src/cpu/ti/am335x/header.ld +++ b/src/cpu/ti/am335x/header.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index f69a31595a..e5e031b4d1 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/cpu/ti/am335x/monotonic_timer.c index fc8499d924..2177f728ba 100644 --- a/src/cpu/ti/am335x/monotonic_timer.c +++ b/src/cpu/ti/am335x/monotonic_timer.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c index 20f23fec49..e7f0f21c2a 100644 --- a/src/cpu/ti/am335x/nand.c +++ b/src/cpu/ti/am335x/nand.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld index b5c1592691..7d23883c8d 100644 --- a/src/cpu/x86/16bit/entry16.ld +++ b/src/cpu/x86/16bit/entry16.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ gdtptr16_offset = gdtptr16 & 0xffff; nullidt_offset = nullidt & 0xffff; diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc index a9993205c2..1d4c5c69d8 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/16bit/reset16.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .section ".reset", "ax", %progbits .code16 diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index ec01810e73..e6a33b6604 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* _RESET_VECTOR: typically the top of the ROM */ diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 52c07685cf..286f12b2d1 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* For starting coreboot in protected mode */ diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 81a9bab33c..c09b3fe838 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * For starting coreboot in long mode. diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c index 574d87b066..96650d608d 100644 --- a/src/cpu/x86/backup_default_smm.c +++ b/src/cpu/x86/backup_default_smm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c index 2313c4dbc7..c38e10344b 100644 --- a/src/cpu/x86/cache/cache.c +++ b/src/cpu/x86/cache/cache.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/fpu_enable.inc b/src/cpu/x86/fpu_enable.inc index e3dd4c7372..f1256cc95f 100644 --- a/src/cpu/x86/fpu_enable.inc +++ b/src/cpu/x86/fpu_enable.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ __fpu_start: /* Preserve BIST. */ diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index fbe4f08e0b..9efd8ff48c 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index f4c2326a0b..042d2e3f99 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 755fbe220d..91b0fcd5ba 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index be825eccd2..6726f213d4 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 09cd6f7c30..1eece14447 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 704785555d..fa550f137a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index 09ffa9f977..eccf1dd386 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 02dfbdc80d..4d14a8de08 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c index 9968eea78e..2c20f474e6 100644 --- a/src/cpu/x86/mtrr/xip_cache.c +++ b/src/cpu/x86/mtrr/xip_cache.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index b3452763c0..7944b12d2c 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 47d7e1f954..55bceb99a4 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index f75a1c9815..4a391e28ea 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 20417d127e..bfbdfd2ce1 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 17996aff30..929e70b82f 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Maximum number of CPUs/cores */ CPUS = 4; diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index bd4d48c555..3169ace969 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 30f115f121..7c23ef8e8e 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index aa4022389f..7e320362af 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The stub is a generic wrapper for bootstrapping a C-based SMM handler. Its diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index a2be7f2310..3cbcf5c210 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* NOTE: This handler assumes the SMM window goes from 0xa0000 * to 0xaffff. In fact, at least on Intel Core CPUs (i945 chipset) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index f64b36507f..dfd9d85e30 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index 5b5c5729d5..40b226a437 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/cpu/x86/sse_enable.inc b/src/cpu/x86/sse_enable.inc index 7608230e5e..541b83dcb5 100644 --- a/src/cpu/x86/sse_enable.inc +++ b/src/cpu/x86/sse_enable.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Preserve BIST. */ movl %eax, %ebp diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 4a1f5c98be..42689ef0bd 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From c74dae927ac41b90303d12dc6fc85e927e3d72d5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:16 +0200 Subject: [PATCH 0776/1463] src/device: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id5fe26564147ec532850430ea55b19ee94d5c5a5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40050 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/device/azalia_device.c | 14 ++------------ src/device/cardbus_device.c | 14 ++------------ src/device/cpu_device.c | 14 ++------------ src/device/device.c | 14 ++------------ src/device/device_const.c | 14 ++------------ src/device/device_util.c | 14 ++------------ src/device/dram/ddr4.c | 14 ++------------ src/device/dram/ddr_common.c | 14 ++------------ src/device/hypertransport.c | 14 ++------------ src/device/i2c.c | 14 ++------------ src/device/i2c_bus.c | 14 ++------------ src/device/mmio.c | 14 ++------------ src/device/oprom/include/io.h | 14 ++------------ src/device/oprom/realmode/x86.c | 14 ++------------ src/device/oprom/realmode/x86.h | 14 ++------------ src/device/oprom/realmode/x86_asm.S | 14 ++------------ src/device/oprom/realmode/x86_interrupts.c | 14 ++------------ src/device/pci_class.c | 14 ++------------ src/device/pci_device.c | 14 ++------------ src/device/pci_early.c | 14 ++------------ src/device/pci_ops.c | 14 ++------------ src/device/pci_rom.c | 14 ++------------ src/device/pciexp_device.c | 14 ++------------ src/device/pcix_device.c | 14 ++------------ src/device/pnp_device.c | 14 ++------------ src/device/root_device.c | 14 ++------------ src/device/smbus_ops.c | 14 ++------------ src/device/software_i2c.c | 14 ++------------ 28 files changed, 56 insertions(+), 336 deletions(-) diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 519d4612aa..36a70f9ec7 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index f7decb30ee..e56202a1ed 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index a786dc0614..3ab4254874 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/device.c b/src/device/device.c index 236b7684d7..cc1b37df1b 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Originally based on the Linux kernel (arch/i386/kernel/pci-pc.c). diff --git a/src/device/device_const.c b/src/device/device_const.c index c46f283608..c59c5e9b69 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/device_util.c b/src/device/device_util.c index 36bcbe9c4d..25e95cfa67 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 4f7e10928c..b641711df1 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/dram/ddr_common.c b/src/device/dram/ddr_common.c index dcfa18df2a..b5a5803946 100644 --- a/src/device/dram/ddr_common.c +++ b/src/device/dram/ddr_common.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index afa94fbe78..4256550747 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/i2c.c b/src/device/i2c.c index 72e5525df1..dbb355470f 100644 --- a/src/device/i2c.c +++ b/src/device/i2c.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 5d69efb73f..58c3d7349a 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/mmio.c b/src/device/mmio.c index 643ff0429a..ce0514256b 100644 --- a/src/device/mmio.c +++ b/src/device/mmio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/oprom/include/io.h b/src/device/oprom/include/io.h index 09e25f031a..1d16e39fa9 100644 --- a/src/device/oprom/include/io.h +++ b/src/device/oprom/include/io.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __OPROM_IO_H__ #define __OPROM_IO_H__ diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 8ba0241ea4..afc0ee4239 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index a68b50ecbf..46728f316c 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DEVICE_OPROM_REALMODE_X86_H__ #define __DEVICE_OPROM_REALMODE_X86_H__ diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index d68fdc5fca..923a60983b 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define REALMODE_BASE 0x600 #define RELOCATED(x) (x - __realmode_code + REALMODE_BASE) diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index c38da466bd..d08718378c 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/pci_class.c b/src/device/pci_class.c index fcb1966aee..b7f1c4e362 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 0cbb02d60a..0099470160 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Originally based on the Linux kernel (drivers/pci/pci.c). diff --git a/src/device/pci_early.c b/src/device/pci_early.c index b15f4a3370..4904c68bb7 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 431160e5cb..d47a3eb505 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 7d489615f1..2757986938 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index b0ad1450e0..1a4854d381 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index 1db4d4adce..32ad16e51f 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index dc921e777e..15f166d6b7 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/root_device.c b/src/device/root_device.c index 6801b41004..8d587dc42e 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c index 3b7a69eabe..c263d2cae6 100644 --- a/src/device/smbus_ops.c +++ b/src/device/smbus_ops.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/device/software_i2c.c b/src/device/software_i2c.c index 3bb9708bfa..857adf0428 100644 --- a/src/device/software_i2c.c +++ b/src/device/software_i2c.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From b67e979f4871e519ec92a002683c0cfb08cd4996 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:56 +0200 Subject: [PATCH 0777/1463] mainboard/portwell: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id24c3a4fa195ccaafeb1932482c17562213505a7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40092 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks --- src/mainboard/portwell/m107/acpi/superio.asl | 15 ++------------- src/mainboard/portwell/m107/acpi_tables.c | 15 ++------------- src/mainboard/portwell/m107/com_init.c | 15 ++------------- src/mainboard/portwell/m107/dsdt.asl | 15 ++------------- src/mainboard/portwell/m107/fadt.c | 15 ++------------- src/mainboard/portwell/m107/gpio.c | 15 ++------------- src/mainboard/portwell/m107/hda_verb.c | 15 ++------------- src/mainboard/portwell/m107/irqroute.c | 15 ++------------- src/mainboard/portwell/m107/irqroute.h | 15 ++------------- src/mainboard/portwell/m107/mainboard.c | 15 ++------------- src/mainboard/portwell/m107/romstage.c | 15 ++------------- src/mainboard/portwell/m107/w25q64.c | 15 ++------------- 12 files changed, 24 insertions(+), 156 deletions(-) diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl index 7bcd3cc08e..f5d0263c7e 100644 --- a/src/mainboard/portwell/m107/acpi/superio.asl +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (COM1) { Name (_HID, EISAID ("PNP0501")) diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index f831352086..ae5aaf1f0f 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/portwell/m107/com_init.c b/src/mainboard/portwell/m107/com_init.c index e1ddc617af..8c05727ae0 100644 --- a/src/mainboard/portwell/m107/com_init.c +++ b/src/mainboard/portwell/m107/com_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl index 8fa1990e39..cecd8bc606 100644 --- a/src/mainboard/portwell/m107/dsdt.asl +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c index abc1bdd77e..2a13cf6f20 100644 --- a/src/mainboard/portwell/m107/fadt.c +++ b/src/mainboard/portwell/m107/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/portwell/m107/gpio.c b/src/mainboard/portwell/m107/gpio.c index 1cc07c5859..ad683993ab 100644 --- a/src/mainboard/portwell/m107/gpio.c +++ b/src/mainboard/portwell/m107/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/portwell/m107/hda_verb.c b/src/mainboard/portwell/m107/hda_verb.c index 0bdb74d186..0700c48e63 100644 --- a/src/mainboard/portwell/m107/hda_verb.c +++ b/src/mainboard/portwell/m107/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/portwell/m107/irqroute.c b/src/mainboard/portwell/m107/irqroute.c index f0855adbc2..df43ee9c69 100644 --- a/src/mainboard/portwell/m107/irqroute.c +++ b/src/mainboard/portwell/m107/irqroute.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "irqroute.h" diff --git a/src/mainboard/portwell/m107/irqroute.h b/src/mainboard/portwell/m107/irqroute.h index 6e3a083087..6616c07a6a 100644 --- a/src/mainboard/portwell/m107/irqroute.h +++ b/src/mainboard/portwell/m107/irqroute.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/portwell/m107/mainboard.c b/src/mainboard/portwell/m107/mainboard.c index 0c929a2ecc..26cb61a16a 100644 --- a/src/mainboard/portwell/m107/mainboard.c +++ b/src/mainboard/portwell/m107/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index f383d60679..ff90cd6326 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c index 24d69dcee9..ea18f1e4df 100644 --- a/src/mainboard/portwell/m107/w25q64.c +++ b/src/mainboard/portwell/m107/w25q64.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 85bf79d31ff6e1f6a1234618f858076b0dfd38c2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:41 +0200 Subject: [PATCH 0778/1463] mainboard/facebook: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I311c62e8321afa43fdb442e10158973ecdcca793 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40074 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- .../facebook/fbg1701/acpi/mainboard.asl | 16 ++-------------- src/mainboard/facebook/fbg1701/acpi/superio.asl | 15 ++------------- src/mainboard/facebook/fbg1701/acpi_tables.c | 15 ++------------- src/mainboard/facebook/fbg1701/board_mboot.h | 15 ++------------- .../facebook/fbg1701/board_verified_boot.c | 15 ++------------- .../facebook/fbg1701/board_verified_boot.h | 15 ++------------- src/mainboard/facebook/fbg1701/com_init.c | 15 ++------------- src/mainboard/facebook/fbg1701/cpld.c | 15 ++------------- src/mainboard/facebook/fbg1701/cpld.h | 15 ++------------- src/mainboard/facebook/fbg1701/dsdt.asl | 15 ++------------- src/mainboard/facebook/fbg1701/fadt.c | 15 ++------------- src/mainboard/facebook/fbg1701/gpio.c | 15 ++------------- src/mainboard/facebook/fbg1701/hda_verb.c | 15 ++------------- src/mainboard/facebook/fbg1701/irqroute.c | 15 ++------------- src/mainboard/facebook/fbg1701/irqroute.h | 15 ++------------- src/mainboard/facebook/fbg1701/mainboard.c | 15 ++------------- src/mainboard/facebook/fbg1701/manifest.h | 15 ++------------- src/mainboard/facebook/fbg1701/ramstage.c | 15 ++------------- src/mainboard/facebook/fbg1701/romstage.c | 15 ++------------- src/mainboard/facebook/fbg1701/w25q64.c | 15 ++------------- src/mainboard/facebook/monolith/acpi/dptf.asl | 15 ++------------- src/mainboard/facebook/monolith/acpi/ec.asl | 15 ++------------- .../facebook/monolith/acpi/mainboard.asl | 15 ++------------- src/mainboard/facebook/monolith/acpi/superio.asl | 15 ++------------- src/mainboard/facebook/monolith/com_init.c | 15 ++------------- src/mainboard/facebook/monolith/dsdt.asl | 15 ++------------- src/mainboard/facebook/monolith/gpio.h | 15 ++------------- src/mainboard/facebook/monolith/mainboard.c | 15 ++------------- src/mainboard/facebook/monolith/onboard.h | 15 ++------------- src/mainboard/facebook/monolith/ramstage.c | 15 ++------------- src/mainboard/facebook/monolith/romstage.c | 15 ++------------- src/mainboard/facebook/monolith/spd/spd.h | 15 ++------------- src/mainboard/facebook/monolith/spd/spd_util.c | 15 ++------------- 33 files changed, 66 insertions(+), 430 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl index 1f9de2d03c..7dd7445fc9 100644 --- a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl +++ b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Onboard CPLD diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl index 7bcd3cc08e..f5d0263c7e 100644 --- a/src/mainboard/facebook/fbg1701/acpi/superio.asl +++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (COM1) { Name (_HID, EISAID ("PNP0501")) diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index f831352086..ae5aaf1f0f 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 12b35accad..5864d4b549 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "board_verified_boot.h" diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index f869773c56..577a75c6d7 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "board_verified_boot.h" diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.h b/src/mainboard/facebook/fbg1701/board_verified_boot.h index a8734166d5..081db02584 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.h +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BOARD_VERIFIED_BOOT_H #define BOARD_VERIFIED_BOOT_H diff --git a/src/mainboard/facebook/fbg1701/com_init.c b/src/mainboard/facebook/fbg1701/com_init.c index e1ddc617af..8c05727ae0 100644 --- a/src/mainboard/facebook/fbg1701/com_init.c +++ b/src/mainboard/facebook/fbg1701/com_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/fbg1701/cpld.c b/src/mainboard/facebook/fbg1701/cpld.c index 8dbd579a43..25e8f7614e 100644 --- a/src/mainboard/facebook/fbg1701/cpld.c +++ b/src/mainboard/facebook/fbg1701/cpld.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "cpld.h" diff --git a/src/mainboard/facebook/fbg1701/cpld.h b/src/mainboard/facebook/fbg1701/cpld.h index 08a91cb7a2..d21ccc0053 100644 --- a/src/mainboard/facebook/fbg1701/cpld.h +++ b/src/mainboard/facebook/fbg1701/cpld.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPLD_H #define CPLD_H diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index f343f32c05..b0a2af8d93 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/facebook/fbg1701/fadt.c b/src/mainboard/facebook/fbg1701/fadt.c index abc1bdd77e..2a13cf6f20 100644 --- a/src/mainboard/facebook/fbg1701/fadt.c +++ b/src/mainboard/facebook/fbg1701/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/fbg1701/gpio.c b/src/mainboard/facebook/fbg1701/gpio.c index 1cc07c5859..ad683993ab 100644 --- a/src/mainboard/facebook/fbg1701/gpio.c +++ b/src/mainboard/facebook/fbg1701/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/facebook/fbg1701/hda_verb.c b/src/mainboard/facebook/fbg1701/hda_verb.c index f0481cf93d..8427b69394 100644 --- a/src/mainboard/facebook/fbg1701/hda_verb.c +++ b/src/mainboard/facebook/fbg1701/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/facebook/fbg1701/irqroute.c b/src/mainboard/facebook/fbg1701/irqroute.c index f0855adbc2..df43ee9c69 100644 --- a/src/mainboard/facebook/fbg1701/irqroute.c +++ b/src/mainboard/facebook/fbg1701/irqroute.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "irqroute.h" diff --git a/src/mainboard/facebook/fbg1701/irqroute.h b/src/mainboard/facebook/fbg1701/irqroute.h index 6e3a083087..6616c07a6a 100644 --- a/src/mainboard/facebook/fbg1701/irqroute.h +++ b/src/mainboard/facebook/fbg1701/irqroute.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c index 9425c11139..3ab2671a4b 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/facebook/fbg1701/manifest.h b/src/mainboard/facebook/fbg1701/manifest.h index 0a82b22a59..0b5c23f98f 100644 --- a/src/mainboard/facebook/fbg1701/manifest.h +++ b/src/mainboard/facebook/fbg1701/manifest.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MANIFEST_H__ #define __MANIFEST_H__ diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 01af4aca09..f32f5efe71 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index 7f453f535c..36f46f2e26 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c index 24d69dcee9..ea18f1e4df 100644 --- a/src/mainboard/facebook/fbg1701/w25q64.c +++ b/src/mainboard/facebook/fbg1701/w25q64.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/monolith/acpi/dptf.asl b/src/mainboard/facebook/monolith/acpi/dptf.asl index 5eb87cb78b..4dc374762a 100644 --- a/src/mainboard/facebook/monolith/acpi/dptf.asl +++ b/src/mainboard/facebook/monolith/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl index 94012bf0c8..398cf54beb 100644 --- a/src/mainboard/facebook/monolith/acpi/ec.asl +++ b/src/mainboard/facebook/monolith/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * We only use the ERAM region to retrieve the CPU temperature. Otherwise the EC is not enabled diff --git a/src/mainboard/facebook/monolith/acpi/mainboard.asl b/src/mainboard/facebook/monolith/acpi/mainboard.asl index 525126269d..7dd7445fc9 100644 --- a/src/mainboard/facebook/monolith/acpi/mainboard.asl +++ b/src/mainboard/facebook/monolith/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Onboard CPLD diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl index 54d450e710..b40d9c3592 100644 --- a/src/mainboard/facebook/monolith/acpi/superio.asl +++ b/src/mainboard/facebook/monolith/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c index 3438a4d471..49df19890a 100644 --- a/src/mainboard/facebook/monolith/com_init.c +++ b/src/mainboard/facebook/monolith/com_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 892456757c..2cb27ebe8f 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h index a007f37537..ba48dbb11a 100644 --- a/src/mainboard/facebook/monolith/gpio.h +++ b/src/mainboard/facebook/monolith/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/facebook/monolith/mainboard.c b/src/mainboard/facebook/monolith/mainboard.c index 9425c11139..3ab2671a4b 100644 --- a/src/mainboard/facebook/monolith/mainboard.c +++ b/src/mainboard/facebook/monolith/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/facebook/monolith/onboard.h b/src/mainboard/facebook/monolith/onboard.h index 83f51034b3..ddd0b71d9d 100644 --- a/src/mainboard/facebook/monolith/onboard.h +++ b/src/mainboard/facebook/monolith/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c index 0c8273ef58..e15f51df34 100644 --- a/src/mainboard/facebook/monolith/ramstage.c +++ b/src/mainboard/facebook/monolith/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/monolith/romstage.c b/src/mainboard/facebook/monolith/romstage.c index 2674f0c7d9..9238872f8b 100644 --- a/src/mainboard/facebook/monolith/romstage.c +++ b/src/mainboard/facebook/monolith/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/facebook/monolith/spd/spd.h b/src/mainboard/facebook/monolith/spd/spd.h index 5468eba1a7..5f645ab8f3 100644 --- a/src/mainboard/facebook/monolith/spd/spd.h +++ b/src/mainboard/facebook/monolith/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/facebook/monolith/spd/spd_util.c b/src/mainboard/facebook/monolith/spd/spd_util.c index 63c035e6e6..820971c681 100644 --- a/src/mainboard/facebook/monolith/spd/spd_util.c +++ b/src/mainboard/facebook/monolith/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 09481b1b86592201e855e525d96f72c2031c5b06 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:13 +0200 Subject: [PATCH 0779/1463] mainboard/asrock: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I32c5f5e865b5455ddb7034612ecea1383932cef9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40066 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/asrock/b75pro3-m/acpi/pci.asl | 15 ++------------- .../asrock/b75pro3-m/acpi/platform.asl | 15 ++------------- .../asrock/b75pro3-m/acpi/superio.asl | 15 ++------------- src/mainboard/asrock/b75pro3-m/acpi_tables.c | 16 ++-------------- src/mainboard/asrock/b75pro3-m/dsdt.asl | 15 ++------------- src/mainboard/asrock/b75pro3-m/early_init.c | 16 ++-------------- src/mainboard/asrock/b75pro3-m/gpio.c | 16 ++-------------- src/mainboard/asrock/b75pro3-m/hda_verb.c | 16 ++-------------- .../asrock/b85m_pro4/acpi/platform.asl | 16 ++-------------- src/mainboard/asrock/b85m_pro4/acpi_tables.c | 15 ++------------- src/mainboard/asrock/b85m_pro4/bootblock.c | 18 ++---------------- src/mainboard/asrock/b85m_pro4/dsdt.asl | 16 ++-------------- src/mainboard/asrock/b85m_pro4/gpio.c | 15 ++------------- src/mainboard/asrock/b85m_pro4/hda_verb.c | 15 ++------------- src/mainboard/asrock/b85m_pro4/romstage.c | 18 ++---------------- src/mainboard/asrock/e350m1/BiosCallOuts.c | 15 ++------------- src/mainboard/asrock/e350m1/OemCustomize.c | 15 ++------------- src/mainboard/asrock/e350m1/OptionsIds.h | 15 ++------------- src/mainboard/asrock/e350m1/acpi/gpe.asl | 15 ++------------- src/mainboard/asrock/e350m1/acpi/mainboard.asl | 15 ++------------- src/mainboard/asrock/e350m1/acpi/routing.asl | 15 ++------------- src/mainboard/asrock/e350m1/acpi/sata.asl | 15 ++------------- src/mainboard/asrock/e350m1/acpi/sleep.asl | 15 ++------------- src/mainboard/asrock/e350m1/acpi/superio.asl | 14 ++------------ src/mainboard/asrock/e350m1/acpi/usb_oc.asl | 15 ++------------- src/mainboard/asrock/e350m1/acpi_tables.c | 15 ++------------- src/mainboard/asrock/e350m1/bootblock.c | 15 ++------------- src/mainboard/asrock/e350m1/buildOpts.c | 15 ++------------- src/mainboard/asrock/e350m1/dsdt.asl | 15 ++------------- src/mainboard/asrock/e350m1/irq_tables.c | 15 ++------------- src/mainboard/asrock/e350m1/mainboard.c | 15 ++------------- src/mainboard/asrock/e350m1/mptable.c | 15 ++------------- src/mainboard/asrock/e350m1/platform_cfg.h | 15 ++------------- .../asrock/g41c-gs/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/asrock/g41c-gs/acpi_tables.c | 15 ++------------- src/mainboard/asrock/g41c-gs/cstates.c | 15 ++------------- src/mainboard/asrock/g41c-gs/dsdt.asl | 15 ++------------- .../asrock/g41c-gs/variants/g41c-gs-r2/gpio.c | 15 ++------------- .../asrock/g41c-gs/variants/g41c-gs/gpio.c | 15 ++------------- .../asrock/g41c-gs/variants/g41m-gs/gpio.c | 15 ++------------- .../asrock/g41c-gs/variants/g41m-s3/gpio.c | 15 ++------------- .../asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c | 15 ++------------- src/mainboard/asrock/h110m/acpi/dptf.asl | 15 ++------------- src/mainboard/asrock/h110m/bootblock.c | 15 ++------------- src/mainboard/asrock/h110m/dsdt.asl | 15 ++------------- src/mainboard/asrock/h110m/hda_verb.c | 15 ++------------- src/mainboard/asrock/h110m/include/gpio.h | 15 ++------------- src/mainboard/asrock/h110m/ramstage.c | 15 ++------------- src/mainboard/asrock/h110m/romstage.c | 15 ++------------- src/mainboard/asrock/h81m-hds/bootblock.c | 15 ++------------- src/mainboard/asrock/h81m-hds/romstage.c | 15 ++------------- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 15 ++------------- src/mainboard/asrock/imb-a180/OemCustomize.c | 15 ++------------- src/mainboard/asrock/imb-a180/OptionsIds.h | 15 ++------------- src/mainboard/asrock/imb-a180/acpi/gpe.asl | 15 ++------------- src/mainboard/asrock/imb-a180/acpi/ide.asl | 15 ++------------- .../asrock/imb-a180/acpi/mainboard.asl | 15 ++------------- src/mainboard/asrock/imb-a180/acpi/routing.asl | 15 ++------------- src/mainboard/asrock/imb-a180/acpi/sata.asl | 15 ++------------- src/mainboard/asrock/imb-a180/acpi/si.asl | 15 ++------------- src/mainboard/asrock/imb-a180/acpi/sleep.asl | 15 ++------------- src/mainboard/asrock/imb-a180/acpi/usb_oc.asl | 15 ++------------- src/mainboard/asrock/imb-a180/acpi_tables.c | 15 ++------------- src/mainboard/asrock/imb-a180/bootblock.c | 14 ++------------ src/mainboard/asrock/imb-a180/buildOpts.c | 15 ++------------- src/mainboard/asrock/imb-a180/dsdt.asl | 15 ++------------- src/mainboard/asrock/imb-a180/irq_tables.c | 15 ++------------- src/mainboard/asrock/imb-a180/mainboard.c | 15 ++------------- src/mainboard/asrock/imb-a180/mptable.c | 15 ++------------- 69 files changed, 138 insertions(+), 907 deletions(-) diff --git a/src/mainboard/asrock/b75pro3-m/acpi/pci.asl b/src/mainboard/asrock/b75pro3-m/acpi/pci.asl index 5a9cb0cbfc..4930b4ccf4 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi/pci.asl +++ b/src/mainboard/asrock/b75pro3-m/acpi/pci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (P0P1) { diff --git a/src/mainboard/asrock/b75pro3-m/acpi/platform.asl b/src/mainboard/asrock/b75pro3-m/acpi/platform.asl index 8a77c9ba4a..8544109abd 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi/platform.asl +++ b/src/mainboard/asrock/b75pro3-m/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK,1) { diff --git a/src/mainboard/asrock/b75pro3-m/acpi/superio.asl b/src/mainboard/asrock/b75pro3-m/acpi/superio.asl index 5b5095461d..b002c4af32 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi/superio.asl +++ b/src/mainboard/asrock/b75pro3-m/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c index 2b8c10087b..3851d04b22 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi_tables.c +++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index ad1349553e..ff5c708e1d 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index fd82c00ec7..552e6645e7 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/b75pro3-m/gpio.c b/src/mainboard/asrock/b75pro3-m/gpio.c index fa17a2d629..8733027d6e 100644 --- a/src/mainboard/asrock/b75pro3-m/gpio.c +++ b/src/mainboard/asrock/b75pro3-m/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c index 6c63926c73..34ec087bcc 100644 --- a/src/mainboard/asrock/b75pro3-m/hda_verb.c +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/b85m_pro4/acpi/platform.asl b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl index c70c466720..b84cada0a4 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi/platform.asl +++ b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_PTS, 1) { diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c index 10e5f944ba..bf45f4d0eb 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi_tables.c +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index 6a66121aa6..5f91b294dc 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2018 Tristan Corrick - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index 0fa3253a43..8764b2d671 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Angel Pons - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/b85m_pro4/gpio.c b/src/mainboard/asrock/b85m_pro4/gpio.c index 4400451568..190585c980 100644 --- a/src/mainboard/asrock/b85m_pro4/gpio.c +++ b/src/mainboard/asrock/b85m_pro4/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c index bc7c0292c9..5ab920355e 100644 --- a/src/mainboard/asrock/b85m_pro4/hda_verb.c +++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 84b0f62992..f9632ce34d 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2018 Tristan Corrick - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index b80b4ca67a..800bae6fe5 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index bd4a6d2327..de9f55f39f 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h index 610c24096c..d03bf1ae0d 100644 --- a/src/mainboard/asrock/e350m1/OptionsIds.h +++ b/src/mainboard/asrock/e350m1/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl index 4b29c0d8ee..0915af37f5 100644 --- a/src/mainboard/asrock/e350m1/acpi/gpe.asl +++ b/src/mainboard/asrock/e350m1/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/asrock/e350m1/acpi/mainboard.asl b/src/mainboard/asrock/e350m1/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/asrock/e350m1/acpi/mainboard.asl +++ b/src/mainboard/asrock/e350m1/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index dd63e9b63e..2ddb2885a9 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/asrock/e350m1/acpi/sata.asl b/src/mainboard/asrock/e350m1/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/asrock/e350m1/acpi/sata.asl +++ b/src/mainboard/asrock/e350m1/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/asrock/e350m1/acpi/sleep.asl b/src/mainboard/asrock/e350m1/acpi/sleep.asl index 08144ff427..0c973a4a0c 100644 --- a/src/mainboard/asrock/e350m1/acpi/sleep.asl +++ b/src/mainboard/asrock/e350m1/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/asrock/e350m1/acpi/superio.asl b/src/mainboard/asrock/e350m1/acpi/superio.asl index 5047e54c62..1bc1628982 100644 --- a/src/mainboard/asrock/e350m1/acpi/superio.asl +++ b/src/mainboard/asrock/e350m1/acpi/superio.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl index 5b22875dd1..27a737c730 100644 --- a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl +++ b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/e350m1/bootblock.c b/src/mainboard/asrock/e350m1/bootblock.c index 0ee1c39235..1da52c5490 100644 --- a/src/mainboard/asrock/e350m1/bootblock.c +++ b/src/mainboard/asrock/e350m1/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index bac9539320..9e1f21b660 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 95821ec402..e05fee5e28 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 1d49f790c3..e5f03f8732 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 2b0916c586..1d5a6ffacd 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index c7b8a80296..4b0d9751cd 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl index f5427b08fa..3cf760b951 100644 --- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is board specific information: diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c index b0370c1ef4..7f47b3a7e2 100644 --- a/src/mainboard/asrock/g41c-gs/acpi_tables.c +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/g41c-gs/cstates.c b/src/mainboard/asrock/g41c-gs/cstates.c index 2a6d8ad816..10498e1150 100644 --- a/src/mainboard/asrock/g41c-gs/cstates.c +++ b/src/mainboard/asrock/g41c-gs/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index 6120949269..8880ba7076 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c index 17961af1d9..983eb3aa00 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c index f00ab12008..710787afcc 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c index 867fbdac66..24c2331bae 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c index 4ee3e0273e..ca3e87a597 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c index 4ca8d5aef0..c914befb6e 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/h110m/acpi/dptf.asl b/src/mainboard/asrock/h110m/acpi/dptf.asl index 440ef534a8..9e1ceaaa4d 100644 --- a/src/mainboard/asrock/h110m/acpi/dptf.asl +++ b/src/mainboard/asrock/h110m/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 98 #define DPTF_CPU_CRITICAL 125 diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c index e50120ceec..5a6b9ee818 100644 --- a/src/mainboard/asrock/h110m/bootblock.c +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index 06b53b2ee2..568ca39132 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c index 1f8d3f4b95..de169d61bc 100644 --- a/src/mainboard/asrock/h110m/hda_verb.c +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index cfd743679f..8223bfdb29 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PCH_GPIO_H #define _PCH_GPIO_H diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index 37542ec566..d75c8082ce 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "include/gpio.h" diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 62f0e384a5..f3bd487448 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/h81m-hds/bootblock.c b/src/mainboard/asrock/h81m-hds/bootblock.c index 11097fcb0f..f3fb2c2080 100644 --- a/src/mainboard/asrock/h81m-hds/bootblock.c +++ b/src/mainboard/asrock/h81m-hds/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 503bc72a5b..092b417657 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index bbf9d8f239..75b15eef1c 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index e0baf34370..1027fb4013 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/imb-a180/OptionsIds.h b/src/mainboard/asrock/imb-a180/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/asrock/imb-a180/OptionsIds.h +++ b/src/mainboard/asrock/imb-a180/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asrock/imb-a180/acpi/gpe.asl b/src/mainboard/asrock/imb-a180/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/asrock/imb-a180/acpi/gpe.asl +++ b/src/mainboard/asrock/imb-a180/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/asrock/imb-a180/acpi/ide.asl b/src/mainboard/asrock/imb-a180/acpi/ide.asl index e17d93befd..85237670a2 100644 --- a/src/mainboard/asrock/imb-a180/acpi/ide.asl +++ b/src/mainboard/asrock/imb-a180/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No IDE functionality */ diff --git a/src/mainboard/asrock/imb-a180/acpi/mainboard.asl b/src/mainboard/asrock/imb-a180/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/asrock/imb-a180/acpi/mainboard.asl +++ b/src/mainboard/asrock/imb-a180/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/asrock/imb-a180/acpi/routing.asl b/src/mainboard/asrock/imb-a180/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/asrock/imb-a180/acpi/routing.asl +++ b/src/mainboard/asrock/imb-a180/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/asrock/imb-a180/acpi/sata.asl b/src/mainboard/asrock/imb-a180/acpi/sata.asl index 00d855adb0..864eb9e07c 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sata.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No SATA functionality */ diff --git a/src/mainboard/asrock/imb-a180/acpi/si.asl b/src/mainboard/asrock/imb-a180/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/asrock/imb-a180/acpi/si.asl +++ b/src/mainboard/asrock/imb-a180/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/asrock/imb-a180/acpi/sleep.asl b/src/mainboard/asrock/imb-a180/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sleep.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl index 82235e55a4..e44e97001e 100644 --- a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl +++ b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/imb-a180/bootblock.c b/src/mainboard/asrock/imb-a180/bootblock.c index e87dc21f87..7f3938623b 100644 --- a/src/mainboard/asrock/imb-a180/bootblock.c +++ b/src/mainboard/asrock/imb-a180/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 5cdf669a11..13a029dd58 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 15b241f897..1b822e60ba 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index 5f0654ad1e..b8077ff8c1 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index b3e47f8ec3..963f8949f3 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 1901e0e870..65410327c1 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 0fcb1b826cb0abbcb0182128cbb392af26dd31ea Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:20 +0200 Subject: [PATCH 0780/1463] mainboard/bap: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic93a89a2d5cbae851a3ed0d1f04055a182bbb85b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40068 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 15 ++------------- src/mainboard/bap/ode_e20XX/OemCustomize.c | 15 ++------------- src/mainboard/bap/ode_e20XX/OptionsIds.h | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/gpe.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/ide.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/mainboard.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/routing.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/si.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/sleep.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/superio.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/acpi_tables.c | 15 ++------------- src/mainboard/bap/ode_e20XX/bootblock.c | 14 ++------------ src/mainboard/bap/ode_e20XX/buildOpts.c | 15 ++------------- src/mainboard/bap/ode_e20XX/dsdt.asl | 15 ++------------- src/mainboard/bap/ode_e20XX/irq_tables.c | 15 ++------------- src/mainboard/bap/ode_e20XX/mainboard.c | 15 ++------------- src/mainboard/bap/ode_e20XX/mptable.c | 15 ++------------- src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 15 ++------------- src/mainboard/bap/ode_e21XX/OemCustomize.c | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi/gpe.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi/mainboard.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi/routing.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi/si.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi/sleep.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi/superio.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/acpi_tables.c | 15 ++------------- src/mainboard/bap/ode_e21XX/dsdt.asl | 15 ++------------- src/mainboard/bap/ode_e21XX/irq_tables.c | 15 ++------------- src/mainboard/bap/ode_e21XX/mainboard.c | 15 ++------------- src/mainboard/bap/ode_e21XX/mptable.c | 15 ++------------- src/mainboard/bap/ode_e21XX/romstage.c | 15 ++------------- 33 files changed, 66 insertions(+), 428 deletions(-) diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 6b83e16b70..24ce464e86 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index a429a1d8a9..cfe4494a78 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e20XX/OptionsIds.h b/src/mainboard/bap/ode_e20XX/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/bap/ode_e20XX/OptionsIds.h +++ b/src/mainboard/bap/ode_e20XX/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/ide.asl b/src/mainboard/bap/ode_e20XX/acpi/ide.asl index e17d93befd..85237670a2 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/ide.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No IDE functionality */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/routing.asl b/src/mainboard/bap/ode_e20XX/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/routing.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/bap/ode_e20XX/acpi/si.asl b/src/mainboard/bap/ode_e20XX/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/si.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/bap/ode_e20XX/acpi/superio.asl b/src/mainboard/bap/ode_e20XX/acpi/superio.asl index 5c53f116bf..ec74fb72fc 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/superio.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SuperIO support for Windows */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl index bf00545927..db55264f91 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e20XX/bootblock.c b/src/mainboard/bap/ode_e20XX/bootblock.c index 8744547bfc..9554c2b9e2 100644 --- a/src/mainboard/bap/ode_e20XX/bootblock.c +++ b/src/mainboard/bap/ode_e20XX/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 9ec18e9344..34e085a4d1 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index 15b241f897..1b822e60ba 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c index 5f0654ad1e..b8077ff8c1 100644 --- a/src/mainboard/bap/ode_e20XX/irq_tables.c +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index c7d8ee45f3..420c249686 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c index e0a407bb25..e9e1dbe49f 100644 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index c9144449ef..394fd59847 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c index bab757e7b3..789d252dde 100644 --- a/src/mainboard/bap/ode_e21XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/bap/ode_e21XX/acpi/gpe.asl b/src/mainboard/bap/ode_e21XX/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/gpe.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/routing.asl b/src/mainboard/bap/ode_e21XX/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/routing.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/bap/ode_e21XX/acpi/si.asl b/src/mainboard/bap/ode_e21XX/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/si.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/bap/ode_e21XX/acpi/sleep.asl b/src/mainboard/bap/ode_e21XX/acpi/sleep.asl index 19dd289560..5882acb05e 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/sleep.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/bap/ode_e21XX/acpi/superio.asl b/src/mainboard/bap/ode_e21XX/acpi/superio.asl index 5c53f116bf..ec74fb72fc 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/superio.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SuperIO support for Windows */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl index 83cd750b4a..b7757d3950 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/bap/ode_e21XX/acpi_tables.c b/src/mainboard/bap/ode_e21XX/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/bap/ode_e21XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e21XX/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl index 8440ecaa0f..f18550a695 100644 --- a/src/mainboard/bap/ode_e21XX/dsdt.asl +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/bap/ode_e21XX/irq_tables.c b/src/mainboard/bap/ode_e21XX/irq_tables.c index 6133bc8620..9f5d68e7bd 100644 --- a/src/mainboard/bap/ode_e21XX/irq_tables.c +++ b/src/mainboard/bap/ode_e21XX/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index c664be3876..1d21e0e0bf 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c index f942dc9e66..98dfc431be 100644 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 0c017fdf12..6a0ad28324 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From e4cce3fb36ea95259b765a9940599c1160d5de40 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:34 +0200 Subject: [PATCH 0781/1463] mainboard/elmex: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I957a5e19c5ce39203e4afb94cbcb3d2961fdfb43 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40072 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/elmex/pcm205400/BiosCallOuts.c | 15 ++------------- src/mainboard/elmex/pcm205400/OemCustomize.c | 15 ++------------- src/mainboard/elmex/pcm205400/OptionsIds.h | 15 ++------------- src/mainboard/elmex/pcm205400/acpi/gpe.asl | 15 ++------------- src/mainboard/elmex/pcm205400/acpi/ide.asl | 15 ++------------- src/mainboard/elmex/pcm205400/acpi/mainboard.asl | 15 ++------------- src/mainboard/elmex/pcm205400/acpi/routing.asl | 15 ++------------- src/mainboard/elmex/pcm205400/acpi/sata.asl | 15 ++------------- src/mainboard/elmex/pcm205400/acpi/sleep.asl | 15 ++------------- src/mainboard/elmex/pcm205400/acpi/superio.asl | 14 ++------------ src/mainboard/elmex/pcm205400/acpi/usb_oc.asl | 15 ++------------- src/mainboard/elmex/pcm205400/acpi_tables.c | 15 ++------------- src/mainboard/elmex/pcm205400/bootblock.c | 15 ++------------- src/mainboard/elmex/pcm205400/buildOpts.c | 15 ++------------- src/mainboard/elmex/pcm205400/dsdt.asl | 15 ++------------- src/mainboard/elmex/pcm205400/irq_tables.c | 15 ++------------- src/mainboard/elmex/pcm205400/mainboard.c | 15 ++------------- src/mainboard/elmex/pcm205400/mptable.c | 15 ++------------- src/mainboard/elmex/pcm205400/platform_cfg.h | 15 ++------------- 19 files changed, 38 insertions(+), 246 deletions(-) diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 6d195816b4..4960068d06 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index b38ce25b00..51100b5a67 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/elmex/pcm205400/OptionsIds.h b/src/mainboard/elmex/pcm205400/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/elmex/pcm205400/OptionsIds.h +++ b/src/mainboard/elmex/pcm205400/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl index af4e2e48b7..5788140112 100644 --- a/src/mainboard/elmex/pcm205400/acpi/gpe.asl +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl index 6286ade685..c5f09809bd 100644 --- a/src/mainboard/elmex/pcm205400/acpi/ide.asl +++ b/src/mainboard/elmex/pcm205400/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope (_SB) { diff --git a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl +++ b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl index 70c5da5ef0..d7dc69a34d 100644 --- a/src/mainboard/elmex/pcm205400/acpi/routing.asl +++ b/src/mainboard/elmex/pcm205400/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/elmex/pcm205400/acpi/sata.asl +++ b/src/mainboard/elmex/pcm205400/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl index 08144ff427..0c973a4a0c 100644 --- a/src/mainboard/elmex/pcm205400/acpi/sleep.asl +++ b/src/mainboard/elmex/pcm205400/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/elmex/pcm205400/acpi/superio.asl b/src/mainboard/elmex/pcm205400/acpi/superio.asl index daf6e9177b..21fdfe9e95 100644 --- a/src/mainboard/elmex/pcm205400/acpi/superio.asl +++ b/src/mainboard/elmex/pcm205400/acpi/superio.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl index 5b22875dd1..27a737c730 100644 --- a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl +++ b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/elmex/pcm205400/bootblock.c b/src/mainboard/elmex/pcm205400/bootblock.c index 4afb0970c5..b0bb317799 100644 --- a/src/mainboard/elmex/pcm205400/bootblock.c +++ b/src/mainboard/elmex/pcm205400/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index 77551070de..9a7b97ffc5 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index 13df85b261..ca149ba600 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 3da820e067..62849ee712 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 218024134a..c3df3213a3 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index 7b8476db20..e932f93257 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index 2f178292a6..7e8d7b8ed9 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ From 1731d46ddc91748514233029d9e8a91944b2ab4d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:31 +0200 Subject: [PATCH 0782/1463] mainboard/compulab: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Iab4fb613bd33bc29630126a487525087c0fe7177 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40071 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/compulab/intense_pc/acpi/ec.asl | 15 ++------------- .../compulab/intense_pc/acpi/platform.asl | 15 ++------------- .../compulab/intense_pc/acpi/superio.asl | 15 ++------------- src/mainboard/compulab/intense_pc/acpi_tables.c | 15 ++------------- src/mainboard/compulab/intense_pc/dsdt.asl | 15 ++------------- src/mainboard/compulab/intense_pc/early_init.c | 15 ++------------- src/mainboard/compulab/intense_pc/gpio.c | 16 ++-------------- src/mainboard/compulab/intense_pc/hda_verb.c | 15 ++------------- src/mainboard/compulab/intense_pc/mainboard.c | 15 ++------------- 9 files changed, 18 insertions(+), 118 deletions(-) diff --git a/src/mainboard/compulab/intense_pc/acpi/ec.asl b/src/mainboard/compulab/intense_pc/acpi/ec.asl index 95bb1eb7f8..25b989ccbc 100644 --- a/src/mainboard/compulab/intense_pc/acpi/ec.asl +++ b/src/mainboard/compulab/intense_pc/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC) { diff --git a/src/mainboard/compulab/intense_pc/acpi/platform.asl b/src/mainboard/compulab/intense_pc/acpi/platform.asl index 705d5bdce9..e7f5a4a3b6 100644 --- a/src/mainboard/compulab/intense_pc/acpi/platform.asl +++ b/src/mainboard/compulab/intense_pc/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK,1) diff --git a/src/mainboard/compulab/intense_pc/acpi/superio.asl b/src/mainboard/compulab/intense_pc/acpi/superio.asl index 606085fafe..1bc1628982 100644 --- a/src/mainboard/compulab/intense_pc/acpi/superio.asl +++ b/src/mainboard/compulab/intense_pc/acpi/superio.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/compulab/intense_pc/acpi_tables.c b/src/mainboard/compulab/intense_pc/acpi_tables.c index a393cc6ff3..3732afef88 100644 --- a/src/mainboard/compulab/intense_pc/acpi_tables.c +++ b/src/mainboard/compulab/intense_pc/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 4b750174a4..247114ef86 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index cf2306a17f..f135e17a17 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/compulab/intense_pc/gpio.c b/src/mainboard/compulab/intense_pc/gpio.c index cd7e6b7926..859b8b3924 100644 --- a/src/mainboard/compulab/intense_pc/gpio.c +++ b/src/mainboard/compulab/intense_pc/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/compulab/intense_pc/hda_verb.c b/src/mainboard/compulab/intense_pc/hda_verb.c index 7eb7e0c27a..f7595dc692 100644 --- a/src/mainboard/compulab/intense_pc/hda_verb.c +++ b/src/mainboard/compulab/intense_pc/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/compulab/intense_pc/mainboard.c b/src/mainboard/compulab/intense_pc/mainboard.c index 9e41c09292..05cfb6d4dc 100644 --- a/src/mainboard/compulab/intense_pc/mainboard.c +++ b/src/mainboard/compulab/intense_pc/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 5c59680e7a91025bffa016c9a3d2344acd679c87 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:01 +0200 Subject: [PATCH 0783/1463] mainboard/amd: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Iaabbc58a7089b28ebe23df3a04464234ff465486 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40063 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/amd/gardenia/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/gardenia/OemCustomize.c | 15 ++------------- src/mainboard/amd/gardenia/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/gardenia/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/gardenia/acpi/routing.asl | 15 ++------------- src/mainboard/amd/gardenia/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/gardenia/acpi/usb_oc.asl | 15 ++------------- .../amd/gardenia/bootblock/OemCustomize.c | 15 ++------------- src/mainboard/amd/gardenia/bootblock/bootblock.c | 15 ++------------- src/mainboard/amd/gardenia/dsdt.asl | 15 ++------------- src/mainboard/amd/gardenia/gpio.c | 15 ++------------- src/mainboard/amd/gardenia/gpio.h | 15 ++------------- src/mainboard/amd/gardenia/irq_tables.c | 15 ++------------- src/mainboard/amd/gardenia/mainboard.c | 15 ++------------- src/mainboard/amd/gardenia/mptable.c | 15 ++------------- src/mainboard/amd/gardenia/romstage.c | 15 ++------------- src/mainboard/amd/inagua/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/inagua/OemCustomize.c | 15 ++------------- src/mainboard/amd/inagua/OptionsIds.h | 15 ++------------- src/mainboard/amd/inagua/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/inagua/acpi/ide.asl | 15 ++------------- src/mainboard/amd/inagua/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/inagua/acpi/routing.asl | 15 ++------------- src/mainboard/amd/inagua/acpi/sata.asl | 15 ++------------- src/mainboard/amd/inagua/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/inagua/acpi/usb_oc.asl | 15 ++------------- src/mainboard/amd/inagua/acpi_tables.c | 15 ++------------- src/mainboard/amd/inagua/bootblock.c | 15 ++------------- src/mainboard/amd/inagua/buildOpts.c | 15 ++------------- src/mainboard/amd/inagua/dsdt.asl | 15 ++------------- src/mainboard/amd/inagua/irq_tables.c | 15 ++------------- src/mainboard/amd/inagua/mainboard.c | 15 ++------------- src/mainboard/amd/inagua/mptable.c | 15 ++------------- src/mainboard/amd/inagua/platform_cfg.h | 15 ++------------- src/mainboard/amd/olivehill/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/olivehill/OemCustomize.c | 15 ++------------- src/mainboard/amd/olivehill/OptionsIds.h | 15 ++------------- src/mainboard/amd/olivehill/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi/ide.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi/routing.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi/sata.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi/si.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi/usb_oc.asl | 15 ++------------- src/mainboard/amd/olivehill/acpi_tables.c | 15 ++------------- src/mainboard/amd/olivehill/bootblock.c | 14 ++------------ src/mainboard/amd/olivehill/buildOpts.c | 15 ++------------- src/mainboard/amd/olivehill/dsdt.asl | 15 ++------------- src/mainboard/amd/olivehill/irq_tables.c | 15 ++------------- src/mainboard/amd/olivehill/mainboard.c | 15 ++------------- src/mainboard/amd/olivehill/mptable.c | 15 ++------------- src/mainboard/amd/padmelon/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/padmelon/BiosCallOuts.h | 15 ++------------- src/mainboard/amd/padmelon/OemCustomize.c | 15 ++------------- src/mainboard/amd/padmelon/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/padmelon/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/padmelon/acpi/routing.asl | 15 ++------------- src/mainboard/amd/padmelon/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/padmelon/acpi/usb_oc.asl | 15 ++------------- .../amd/padmelon/bootblock/OemCustomize.c | 15 ++------------- src/mainboard/amd/padmelon/bootblock/bootblock.c | 15 ++------------- src/mainboard/amd/padmelon/dsdt.asl | 15 ++------------- src/mainboard/amd/padmelon/fan_init.c | 15 ++------------- src/mainboard/amd/padmelon/gpio.c | 15 ++------------- src/mainboard/amd/padmelon/gpio.h | 15 ++------------- src/mainboard/amd/padmelon/mainboard.c | 15 ++------------- src/mainboard/amd/parmer/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/parmer/OemCustomize.c | 15 ++------------- src/mainboard/amd/parmer/OptionsIds.h | 15 ++------------- src/mainboard/amd/parmer/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/parmer/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/parmer/acpi/routing.asl | 15 ++------------- src/mainboard/amd/parmer/acpi/si.asl | 15 ++------------- src/mainboard/amd/parmer/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/parmer/acpi/usb_oc.asl | 15 ++------------- src/mainboard/amd/parmer/acpi_tables.c | 15 ++------------- src/mainboard/amd/parmer/bootblock.c | 15 ++------------- src/mainboard/amd/parmer/buildOpts.c | 15 ++------------- src/mainboard/amd/parmer/dsdt.asl | 15 ++------------- src/mainboard/amd/parmer/irq_tables.c | 15 ++------------- src/mainboard/amd/parmer/mainboard.c | 15 ++------------- src/mainboard/amd/parmer/mptable.c | 15 ++------------- src/mainboard/amd/persimmon/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/persimmon/OemCustomize.c | 15 ++------------- src/mainboard/amd/persimmon/OptionsIds.h | 15 ++------------- src/mainboard/amd/persimmon/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/persimmon/acpi/ide.asl | 15 ++------------- src/mainboard/amd/persimmon/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/persimmon/acpi/routing.asl | 15 ++------------- src/mainboard/amd/persimmon/acpi/sata.asl | 15 ++------------- src/mainboard/amd/persimmon/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/persimmon/acpi/superio.asl | 14 ++------------ src/mainboard/amd/persimmon/acpi/usb_oc.asl | 15 ++------------- src/mainboard/amd/persimmon/acpi_tables.c | 15 ++------------- src/mainboard/amd/persimmon/bootblock.c | 15 ++------------- src/mainboard/amd/persimmon/buildOpts.c | 15 ++------------- src/mainboard/amd/persimmon/dsdt.asl | 15 ++------------- src/mainboard/amd/persimmon/irq_tables.c | 15 ++------------- src/mainboard/amd/persimmon/mainboard.c | 15 ++------------- src/mainboard/amd/persimmon/mptable.c | 15 ++------------- src/mainboard/amd/persimmon/platform_cfg.h | 15 ++------------- src/mainboard/amd/south_station/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/south_station/OemCustomize.c | 15 ++------------- src/mainboard/amd/south_station/OptionsIds.h | 15 ++------------- src/mainboard/amd/south_station/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/south_station/acpi/ide.asl | 15 ++------------- .../amd/south_station/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/south_station/acpi/routing.asl | 15 ++------------- src/mainboard/amd/south_station/acpi/sata.asl | 15 ++------------- src/mainboard/amd/south_station/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/south_station/acpi/usb_oc.asl | 15 ++------------- src/mainboard/amd/south_station/acpi_tables.c | 15 ++------------- src/mainboard/amd/south_station/bootblock.c | 15 ++------------- src/mainboard/amd/south_station/buildOpts.c | 15 ++------------- src/mainboard/amd/south_station/dsdt.asl | 15 ++------------- src/mainboard/amd/south_station/irq_tables.c | 15 ++------------- src/mainboard/amd/south_station/mainboard.c | 15 ++------------- src/mainboard/amd/south_station/mptable.c | 15 ++------------- src/mainboard/amd/south_station/platform_cfg.h | 15 ++------------- src/mainboard/amd/thatcher/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/thatcher/OemCustomize.c | 15 ++------------- src/mainboard/amd/thatcher/OptionsIds.h | 15 ++------------- src/mainboard/amd/thatcher/acpi/cpstate.asl | 15 ++------------- src/mainboard/amd/thatcher/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/thatcher/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/thatcher/acpi/routing.asl | 15 ++------------- src/mainboard/amd/thatcher/acpi/si.asl | 15 ++------------- src/mainboard/amd/thatcher/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/thatcher/acpi/usb_oc.asl | 15 ++------------- src/mainboard/amd/thatcher/acpi_tables.c | 15 ++------------- src/mainboard/amd/thatcher/bootblock.c | 14 ++------------ src/mainboard/amd/thatcher/buildOpts.c | 15 ++------------- src/mainboard/amd/thatcher/dsdt.asl | 15 ++------------- src/mainboard/amd/thatcher/irq_tables.c | 15 ++------------- src/mainboard/amd/thatcher/mainboard.c | 15 ++------------- src/mainboard/amd/thatcher/mptable.c | 15 ++------------- src/mainboard/amd/union_station/BiosCallOuts.c | 15 ++------------- src/mainboard/amd/union_station/OemCustomize.c | 15 ++------------- src/mainboard/amd/union_station/OptionsIds.h | 15 ++------------- src/mainboard/amd/union_station/acpi/gpe.asl | 15 ++------------- src/mainboard/amd/union_station/acpi/ide.asl | 15 ++------------- .../amd/union_station/acpi/mainboard.asl | 15 ++------------- src/mainboard/amd/union_station/acpi/routing.asl | 15 ++------------- src/mainboard/amd/union_station/acpi/sata.asl | 15 ++------------- src/mainboard/amd/union_station/acpi/sleep.asl | 15 ++------------- src/mainboard/amd/union_station/acpi/usb_oc.asl | 15 ++------------- src/mainboard/amd/union_station/acpi_tables.c | 15 ++------------- src/mainboard/amd/union_station/bootblock.c | 15 ++------------- src/mainboard/amd/union_station/buildOpts.c | 15 ++------------- src/mainboard/amd/union_station/dsdt.asl | 15 ++------------- src/mainboard/amd/union_station/irq_tables.c | 15 ++------------- src/mainboard/amd/union_station/mainboard.c | 15 ++------------- src/mainboard/amd/union_station/mptable.c | 15 ++------------- src/mainboard/amd/union_station/platform_cfg.h | 15 ++------------- 155 files changed, 310 insertions(+), 2012 deletions(-) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 06185ec6bf..9da7a55138 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 0bb9658541..88507a6d91 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl index 63cbd02780..a4aed9a7d9 100644 --- a/src/mainboard/amd/gardenia/acpi/gpe.asl +++ b/src/mainboard/amd/gardenia/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/gardenia/acpi/mainboard.asl b/src/mainboard/amd/gardenia/acpi/mainboard.asl index b74b07c2be..30299db10e 100644 --- a/src/mainboard/amd/gardenia/acpi/mainboard.asl +++ b/src/mainboard/amd/gardenia/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/amd/gardenia/acpi/routing.asl b/src/mainboard/amd/gardenia/acpi/routing.asl index 7c120dde2b..642ef8f8ad 100644 --- a/src/mainboard/amd/gardenia/acpi/routing.asl +++ b/src/mainboard/amd/gardenia/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/amd/gardenia/acpi/sleep.asl b/src/mainboard/amd/gardenia/acpi/sleep.asl index b23f09d779..9b0e09597b 100644 --- a/src/mainboard/amd/gardenia/acpi/sleep.asl +++ b/src/mainboard/amd/gardenia/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/gardenia/acpi/usb_oc.asl b/src/mainboard/amd/gardenia/acpi/usb_oc.asl index 69c42c0af7..8a4df6fbb5 100644 --- a/src/mainboard/amd/gardenia/acpi/usb_oc.asl +++ b/src/mainboard/amd/gardenia/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c index 710ff78275..fdf3956a8a 100644 --- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c +++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index c3833f7aca..27bdc0a384 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 6ecea61936..4f861cbd04 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define MAINBOARD_HAS_SPEAKER 1 diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 1d58a604d1..b1c61064eb 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h index da75c10895..08cf106c9c 100644 --- a/src/mainboard/amd/gardenia/gpio.h +++ b/src/mainboard/amd/gardenia/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c index 761fd060a3..8a8cacf0f4 100644 --- a/src/mainboard/amd/gardenia/irq_tables.c +++ b/src/mainboard/amd/gardenia/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 01c7061607..fcbac2fb9f 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index 130a728483..008639a2cf 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 979facc851..9f66ee0731 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -1,13 +1,2 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index f88929a94c..1efe3621d7 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index 4e02ba0155..ae52246ffd 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ b/src/mainboard/amd/inagua/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index af4e2e48b7..5788140112 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/inagua/acpi/ide.asl b/src/mainboard/amd/inagua/acpi/ide.asl index 6286ade685..c5f09809bd 100644 --- a/src/mainboard/amd/inagua/acpi/ide.asl +++ b/src/mainboard/amd/inagua/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope (_SB) { diff --git a/src/mainboard/amd/inagua/acpi/mainboard.asl b/src/mainboard/amd/inagua/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/amd/inagua/acpi/mainboard.asl +++ b/src/mainboard/amd/inagua/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl index 51215f5de6..88024a73f2 100644 --- a/src/mainboard/amd/inagua/acpi/routing.asl +++ b/src/mainboard/amd/inagua/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/amd/inagua/acpi/sata.asl +++ b/src/mainboard/amd/inagua/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl index 08144ff427..0c973a4a0c 100644 --- a/src/mainboard/amd/inagua/acpi/sleep.asl +++ b/src/mainboard/amd/inagua/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl index 5b22875dd1..27a737c730 100644 --- a/src/mainboard/amd/inagua/acpi/usb_oc.asl +++ b/src/mainboard/amd/inagua/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/inagua/bootblock.c b/src/mainboard/amd/inagua/bootblock.c index 711d075e19..0a18ca9826 100644 --- a/src/mainboard/amd/inagua/bootblock.c +++ b/src/mainboard/amd/inagua/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 6ef93c750d..512c22446b 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 13df85b261..ca149ba600 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 87c26024b2..140528ddd8 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index e49ccf172f..20e249df83 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index f1898e257d..28b8df077c 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index c86a22722c..5202c4360f 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index e207c0303a..e261171cb2 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ b/src/mainboard/amd/olivehill/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ b/src/mainboard/amd/olivehill/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/olivehill/acpi/ide.asl b/src/mainboard/amd/olivehill/acpi/ide.asl index e17d93befd..85237670a2 100644 --- a/src/mainboard/amd/olivehill/acpi/ide.asl +++ b/src/mainboard/amd/olivehill/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No IDE functionality */ diff --git a/src/mainboard/amd/olivehill/acpi/mainboard.asl b/src/mainboard/amd/olivehill/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/amd/olivehill/acpi/mainboard.asl +++ b/src/mainboard/amd/olivehill/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/amd/olivehill/acpi/routing.asl +++ b/src/mainboard/amd/olivehill/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/amd/olivehill/acpi/sata.asl b/src/mainboard/amd/olivehill/acpi/sata.asl index 00d855adb0..864eb9e07c 100644 --- a/src/mainboard/amd/olivehill/acpi/sata.asl +++ b/src/mainboard/amd/olivehill/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No SATA functionality */ diff --git a/src/mainboard/amd/olivehill/acpi/si.asl b/src/mainboard/amd/olivehill/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/amd/olivehill/acpi/si.asl +++ b/src/mainboard/amd/olivehill/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ b/src/mainboard/amd/olivehill/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/olivehill/acpi/usb_oc.asl b/src/mainboard/amd/olivehill/acpi/usb_oc.asl index 7ceb70ce04..4ea18f54b8 100644 --- a/src/mainboard/amd/olivehill/acpi/usb_oc.asl +++ b/src/mainboard/amd/olivehill/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c index d1f8d606e4..8a8a319629 100644 --- a/src/mainboard/amd/olivehill/bootblock.c +++ b/src/mainboard/amd/olivehill/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 0b89298b9d..335d759a13 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index 15b241f897..1b822e60ba 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 5f0654ad1e..b8077ff8c1 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index b3e47f8ec3..963f8949f3 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 6e1d402833..73e6cc4e7d 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index 9ba0a63c8f..c50fefdf17 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.h b/src/mainboard/amd/padmelon/BiosCallOuts.h index 661aa5a7ed..48e42ce85c 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.h +++ b/src/mainboard/amd/padmelon/BiosCallOuts.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define FAN_INPUT_INTERNAL_DIODE 0 #define FAN_INPUT_TEMP0 1 diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c index 099f41f6d6..074fbffa69 100644 --- a/src/mainboard/amd/padmelon/OemCustomize.c +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl index e306202b07..3fd653ed40 100644 --- a/src/mainboard/amd/padmelon/acpi/gpe.asl +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/padmelon/acpi/mainboard.asl b/src/mainboard/amd/padmelon/acpi/mainboard.asl index b74b07c2be..30299db10e 100644 --- a/src/mainboard/amd/padmelon/acpi/mainboard.asl +++ b/src/mainboard/amd/padmelon/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl index b99befab25..fcc65a68b9 100644 --- a/src/mainboard/amd/padmelon/acpi/routing.asl +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl index b23f09d779..9b0e09597b 100644 --- a/src/mainboard/amd/padmelon/acpi/sleep.asl +++ b/src/mainboard/amd/padmelon/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/padmelon/acpi/usb_oc.asl b/src/mainboard/amd/padmelon/acpi/usb_oc.asl index e1dc35d969..fb88faa56b 100644 --- a/src/mainboard/amd/padmelon/acpi/usb_oc.asl +++ b/src/mainboard/amd/padmelon/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* USB overcurrent mapping pins. */ Name(UOM0, 0) diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c index 469b93733c..3a16d56f1d 100644 --- a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index e6bd7d792b..df6e5919ec 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 0e45e0784d..aa8c2c3009 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/padmelon/fan_init.c b/src/mainboard/amd/padmelon/fan_init.c index b6cfd230d3..398057c953 100644 --- a/src/mainboard/amd/padmelon/fan_init.c +++ b/src/mainboard/amd/padmelon/fan_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index ea031bd074..81602313ed 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/padmelon/gpio.h b/src/mainboard/amd/padmelon/gpio.h index d95390c352..774502a96f 100644 --- a/src/mainboard/amd/padmelon/gpio.h +++ b/src/mainboard/amd/padmelon/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index 4aae6c44de..7edd3bef45 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 690dcb294c..7020c6546d 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index 2ca9481a67..208f8b0919 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ b/src/mainboard/amd/parmer/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index f8e34a8995..2e62f8e10c 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/parmer/acpi/mainboard.asl b/src/mainboard/amd/parmer/acpi/mainboard.asl index e97cdecfcc..f4330cd21f 100644 --- a/src/mainboard/amd/parmer/acpi/mainboard.asl +++ b/src/mainboard/amd/parmer/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl index 10b197221a..6c5acf3b04 100644 --- a/src/mainboard/amd/parmer/acpi/routing.asl +++ b/src/mainboard/amd/parmer/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/amd/parmer/acpi/si.asl b/src/mainboard/amd/parmer/acpi/si.asl index cc27e983e1..e46f267284 100644 --- a/src/mainboard/amd/parmer/acpi/si.asl +++ b/src/mainboard/amd/parmer/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { /* DBGO("\\_SI\\_SST\n") */ diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl index d5a1f683a8..c65979df55 100644 --- a/src/mainboard/amd/parmer/acpi/sleep.asl +++ b/src/mainboard/amd/parmer/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/parmer/acpi/usb_oc.asl b/src/mainboard/amd/parmer/acpi/usb_oc.asl index e1dc35d969..fb88faa56b 100644 --- a/src/mainboard/amd/parmer/acpi/usb_oc.asl +++ b/src/mainboard/amd/parmer/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* USB overcurrent mapping pins. */ Name(UOM0, 0) diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index be2669eeb8..3eb63c8920 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/parmer/bootblock.c b/src/mainboard/amd/parmer/bootblock.c index 01587d079c..78141dc9e2 100644 --- a/src/mainboard/amd/parmer/bootblock.c +++ b/src/mainboard/amd/parmer/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 6f74eac801..f3ed24ff75 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index 459d18f05f..20e550f157 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 5f0654ad1e..b8077ff8c1 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 79954aceef..ee8f49f7a7 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 8ffd517fe7..38009d0a50 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 152860fad2..8734bfe625 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 7249a16a56..3ed6e3652f 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ b/src/mainboard/amd/persimmon/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index af4e2e48b7..5788140112 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/persimmon/acpi/ide.asl b/src/mainboard/amd/persimmon/acpi/ide.asl index 6286ade685..c5f09809bd 100644 --- a/src/mainboard/amd/persimmon/acpi/ide.asl +++ b/src/mainboard/amd/persimmon/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope (_SB) { diff --git a/src/mainboard/amd/persimmon/acpi/mainboard.asl b/src/mainboard/amd/persimmon/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/amd/persimmon/acpi/mainboard.asl +++ b/src/mainboard/amd/persimmon/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index 70c5da5ef0..d7dc69a34d 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/amd/persimmon/acpi/sata.asl b/src/mainboard/amd/persimmon/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/amd/persimmon/acpi/sata.asl +++ b/src/mainboard/amd/persimmon/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl index 08144ff427..0c973a4a0c 100644 --- a/src/mainboard/amd/persimmon/acpi/sleep.asl +++ b/src/mainboard/amd/persimmon/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/persimmon/acpi/superio.asl b/src/mainboard/amd/persimmon/acpi/superio.asl index daf6e9177b..21fdfe9e95 100644 --- a/src/mainboard/amd/persimmon/acpi/superio.asl +++ b/src/mainboard/amd/persimmon/acpi/superio.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No Super I/O device or functionality yet */ diff --git a/src/mainboard/amd/persimmon/acpi/usb_oc.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl index 5b22875dd1..27a737c730 100644 --- a/src/mainboard/amd/persimmon/acpi/usb_oc.asl +++ b/src/mainboard/amd/persimmon/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/persimmon/bootblock.c b/src/mainboard/amd/persimmon/bootblock.c index 4afb0970c5..b0bb317799 100644 --- a/src/mainboard/amd/persimmon/bootblock.c +++ b/src/mainboard/amd/persimmon/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index ceb6b8869b..8c97f07cf3 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 13df85b261..ca149ba600 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 218024134a..c3df3213a3 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 7b8476db20..e932f93257 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 212c4bdcae..8e78f480bd 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 751822b682..acdbb62ab9 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 722d74976d..7887402526 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index c8ff6ea30c..fb0db3ab8b 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl index 6286ade685..c5f09809bd 100644 --- a/src/mainboard/amd/south_station/acpi/ide.asl +++ b/src/mainboard/amd/south_station/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope (_SB) { diff --git a/src/mainboard/amd/south_station/acpi/mainboard.asl b/src/mainboard/amd/south_station/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/amd/south_station/acpi/mainboard.asl +++ b/src/mainboard/amd/south_station/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index 51215f5de6..88024a73f2 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/amd/south_station/acpi/sata.asl +++ b/src/mainboard/amd/south_station/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl index f54fe2a9b7..5b059d4cbe 100644 --- a/src/mainboard/amd/south_station/acpi/sleep.asl +++ b/src/mainboard/amd/south_station/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl index 8112d85ee3..b38f7fd2a6 100644 --- a/src/mainboard/amd/south_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/south_station/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/south_station/bootblock.c b/src/mainboard/amd/south_station/bootblock.c index 4afb0970c5..b0bb317799 100644 --- a/src/mainboard/amd/south_station/bootblock.c +++ b/src/mainboard/amd/south_station/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index e6e3e8e9d4..7bcb93b59a 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 13df85b261..ca149ba600 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 0e86c739d7..7fc3a9092e 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 5f1413dc37..87747b76aa 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index f1898e257d..28b8df077c 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 77ae68a2a8..21ffa05395 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 3133c9ef99..69a8528556 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl index 4a49f6baf2..86361521a2 100644 --- a/src/mainboard/amd/thatcher/acpi/cpstate.asl +++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file defines the processor and performance state capability * for each core in the system. It is included into the DSDT for each diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index f8e34a8995..2e62f8e10c 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/thatcher/acpi/mainboard.asl b/src/mainboard/amd/thatcher/acpi/mainboard.asl index e97cdecfcc..f4330cd21f 100644 --- a/src/mainboard/amd/thatcher/acpi/mainboard.asl +++ b/src/mainboard/amd/thatcher/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/amd/thatcher/acpi/routing.asl b/src/mainboard/amd/thatcher/acpi/routing.asl index 10b197221a..6c5acf3b04 100644 --- a/src/mainboard/amd/thatcher/acpi/routing.asl +++ b/src/mainboard/amd/thatcher/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/amd/thatcher/acpi/si.asl b/src/mainboard/amd/thatcher/acpi/si.asl index cc27e983e1..e46f267284 100644 --- a/src/mainboard/amd/thatcher/acpi/si.asl +++ b/src/mainboard/amd/thatcher/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { /* DBGO("\\_SI\\_SST\n") */ diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl index 1d86801d94..46fd0c7e63 100644 --- a/src/mainboard/amd/thatcher/acpi/sleep.asl +++ b/src/mainboard/amd/thatcher/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/thatcher/acpi/usb_oc.asl b/src/mainboard/amd/thatcher/acpi/usb_oc.asl index e1dc35d969..fb88faa56b 100644 --- a/src/mainboard/amd/thatcher/acpi/usb_oc.asl +++ b/src/mainboard/amd/thatcher/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* USB overcurrent mapping pins. */ Name(UOM0, 0) diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index be2669eeb8..3eb63c8920 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index d25102541c..9afafaf6ca 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 417548bf78..23eb0a1716 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index 459d18f05f..20e550f157 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 5f0654ad1e..b8077ff8c1 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 7218afabea..b481c09f07 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index e23b0171da..7d15eb3d80 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 3175f4c3e8..fc31ed023d 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 8192510da4..57004f13b9 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index c8ff6ea30c..fb0db3ab8b 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl index 6286ade685..c5f09809bd 100644 --- a/src/mainboard/amd/union_station/acpi/ide.asl +++ b/src/mainboard/amd/union_station/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope (_SB) { diff --git a/src/mainboard/amd/union_station/acpi/mainboard.asl b/src/mainboard/amd/union_station/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/amd/union_station/acpi/mainboard.asl +++ b/src/mainboard/amd/union_station/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl index 51215f5de6..88024a73f2 100644 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/amd/union_station/acpi/sata.asl +++ b/src/mainboard/amd/union_station/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/amd/union_station/acpi/sleep.asl b/src/mainboard/amd/union_station/acpi/sleep.asl index f54fe2a9b7..5b059d4cbe 100644 --- a/src/mainboard/amd/union_station/acpi/sleep.asl +++ b/src/mainboard/amd/union_station/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl index 8112d85ee3..b38f7fd2a6 100644 --- a/src/mainboard/amd/union_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/union_station/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/union_station/bootblock.c b/src/mainboard/amd/union_station/bootblock.c index ec565a8c7f..fea6a69264 100644 --- a/src/mainboard/amd/union_station/bootblock.c +++ b/src/mainboard/amd/union_station/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index e6e3e8e9d4..7bcb93b59a 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 13df85b261..ca149ba600 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 2c7626a5d1..c649ef6ad2 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 5f1413dc37..87747b76aa 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index f1898e257d..28b8df077c 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ From 1f35dae585ba75b091e5b2d67242c22611bf1b0d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:41 +0200 Subject: [PATCH 0784/1463] mainboard/up: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I4d37fabe34265166019cdbbbe4ccb9772b87bff8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40104 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/up/squared/bootblock.c | 15 ++------------- src/mainboard/up/squared/dsdt.asl | 15 ++------------- src/mainboard/up/squared/gpio.h | 15 ++------------- src/mainboard/up/squared/ramstage.c | 15 ++------------- src/mainboard/up/squared/romstage.c | 15 ++------------- 5 files changed, 10 insertions(+), 65 deletions(-) diff --git a/src/mainboard/up/squared/bootblock.c b/src/mainboard/up/squared/bootblock.c index 3c8d5bd89c..695aaac1f0 100644 --- a/src/mainboard/up/squared/bootblock.c +++ b/src/mainboard/up/squared/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl index f6f274489f..11ad0bb47e 100644 --- a/src/mainboard/up/squared/dsdt.asl +++ b/src/mainboard/up/squared/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index 52a67ee67c..dfe0490f3b 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index dd9bff5294..8295634dcb 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 12c3006627..f2418eb9d0 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 7a400e218573a7dc7d021e0ddc048b8e788b3fec Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:31 +0200 Subject: [PATCH 0785/1463] mainboard/supermicro: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie43c93c371073b4fe071b08522f351d0e20ed561 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40101 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/supermicro/x10slm-f/romstage.c | 15 ++------------- .../supermicro/x11-lga1151-series/bootblock.c | 15 ++------------- .../supermicro/x11-lga1151-series/dsdt.asl | 15 ++------------- .../x11-lga1151-series/include/mainboard.h | 14 ++------------ .../supermicro/x11-lga1151-series/mainboard.c | 15 ++------------- .../supermicro/x11-lga1151-series/ramstage.c | 14 ++------------ .../supermicro/x11-lga1151-series/romstage.c | 14 ++------------ .../variants/x11ssh-tf/include/variant/gpio.h | 15 ++------------- .../variants/x11ssm-f/include/variant/gpio.h | 15 ++------------- .../variants/x11ssm-f/mainboard.c | 14 ++------------ 10 files changed, 20 insertions(+), 126 deletions(-) diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 9885a3d5e1..0c610dd7ac 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 01a75ca65b..015bf9ce1a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index fa047f8d6b..8cff20f84d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h index a2047d4cdf..fc7391c379 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h +++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BASEBOARD_X11_LGA1151_SERIES_H #define _BASEBOARD_X11_LGA1151_SERIES_H diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 92104e3365..3dd3487c35 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index a16678eb33..2b4b8c31d6 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/romstage.c b/src/mainboard/supermicro/x11-lga1151-series/romstage.c index cb1f1059f2..9388354dbe 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/romstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/romstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index 6c8bde224d..f27feeade0 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _GPIO_X11SSH_TF_H #define _GPIO_X11SSH_TF_H diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 153edfea29..51c1c1e682 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _GPIO_X11SSM_F_H #define _GPIO_X11SSM_F_H diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c index 7cf8883dd6..a1d0624d38 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 274a037f085078df8c28d98a55550dd47fc0a92d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:27 +0200 Subject: [PATCH 0786/1463] mainboard/sifive: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8c9d06fd4d369ae18447dadf6ca9107e7bdbc727 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40100 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../sifive/hifive-unleashed/fixup_fdt.c | 15 ++------------- .../sifive/hifive-unleashed/fu540-c000.dtsi | 16 ++-------------- .../hifive-unleashed/hifive-unleashed-a00.dts | 16 ++-------------- .../sifive/hifive-unleashed/mainboard.c | 15 ++------------- src/mainboard/sifive/hifive-unleashed/media.c | 15 ++------------- .../sifive/hifive-unleashed/memlayout.ld | 15 ++------------- src/mainboard/sifive/hifive-unleashed/romstage.c | 15 ++------------- 7 files changed, 14 insertions(+), 93 deletions(-) diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index f5c827b5ab..c270857667 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi index 3dc27c33d6..637ebe7ffb 100644 --- a/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi +++ b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi @@ -1,17 +1,5 @@ -/* - * This file is part of the Linux kernel. - * - * Copyright (c) 2018-2019 SiFive, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the Linux kernel. */ /dts-v1/; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts index 454c3d807c..3d99522b64 100644 --- a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts +++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts @@ -1,17 +1,5 @@ -/* - * This file is part of the Linux kernel. - * - * Copyright (c) 2018-2019 SiFive, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the Linux kernel. */ /include/ "fu540-c000.dtsi" diff --git a/src/mainboard/sifive/hifive-unleashed/mainboard.c b/src/mainboard/sifive/hifive-unleashed/mainboard.c index 86231302b6..b635f269f1 100644 --- a/src/mainboard/sifive/hifive-unleashed/mainboard.c +++ b/src/mainboard/sifive/hifive-unleashed/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index 757b50ac28..097835cc61 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/sifive/hifive-unleashed/memlayout.ld b/src/mainboard/sifive/hifive-unleashed/memlayout.ld index 9572a5ef8f..a6ccf155b6 100644 --- a/src/mainboard/sifive/hifive-unleashed/memlayout.ld +++ b/src/mainboard/sifive/hifive-unleashed/memlayout.ld @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 2c757c6aa5..d0d9a13a4f 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 4f2dacbf7fdc1ad89703e1de9134a6da8a1e2458 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:34 +0200 Subject: [PATCH 0787/1463] mainboard/system76: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2aa745e03e62ff8b9b5c9cb6f91d7f832f599f8d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40102 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/system76/lemp9/acpi/ac.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/battery.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/buttons.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/ec.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/ec_ram.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/gpe.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/hid.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/lid.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/mainboard.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/s76.asl | 15 ++------------- src/mainboard/system76/lemp9/acpi/sleep.asl | 15 ++------------- src/mainboard/system76/lemp9/bootblock.c | 15 ++------------- src/mainboard/system76/lemp9/dsdt.asl | 15 ++------------- src/mainboard/system76/lemp9/gpio.h | 15 ++------------- src/mainboard/system76/lemp9/hda_verb.c | 15 ++------------- src/mainboard/system76/lemp9/ramstage.c | 15 ++------------- src/mainboard/system76/lemp9/romstage.c | 15 ++------------- 17 files changed, 34 insertions(+), 221 deletions(-) diff --git a/src/mainboard/system76/lemp9/acpi/ac.asl b/src/mainboard/system76/lemp9/acpi/ac.asl index 2355ed5fbc..6bd9414ddf 100644 --- a/src/mainboard/system76/lemp9/acpi/ac.asl +++ b/src/mainboard/system76/lemp9/acpi/ac.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (AC) { diff --git a/src/mainboard/system76/lemp9/acpi/battery.asl b/src/mainboard/system76/lemp9/acpi/battery.asl index cf2ce19f4c..e64e25a706 100644 --- a/src/mainboard/system76/lemp9/acpi/battery.asl +++ b/src/mainboard/system76/lemp9/acpi/battery.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (BAT0) { diff --git a/src/mainboard/system76/lemp9/acpi/buttons.asl b/src/mainboard/system76/lemp9/acpi/buttons.asl index f8f2910970..e3bf9ec7ef 100644 --- a/src/mainboard/system76/lemp9/acpi/buttons.asl +++ b/src/mainboard/system76/lemp9/acpi/buttons.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PWRB) { diff --git a/src/mainboard/system76/lemp9/acpi/ec.asl b/src/mainboard/system76/lemp9/acpi/ec.asl index 0e3a68dda5..cca3d27712 100644 --- a/src/mainboard/system76/lemp9/acpi/ec.asl +++ b/src/mainboard/system76/lemp9/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EC0) { diff --git a/src/mainboard/system76/lemp9/acpi/ec_ram.asl b/src/mainboard/system76/lemp9/acpi/ec_ram.asl index ea57291cf4..0d70fa1cf4 100644 --- a/src/mainboard/system76/lemp9/acpi/ec_ram.asl +++ b/src/mainboard/system76/lemp9/acpi/ec_ram.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) Field (ERAM, ByteAcc, Lock, Preserve) diff --git a/src/mainboard/system76/lemp9/acpi/gpe.asl b/src/mainboard/system76/lemp9/acpi/gpe.asl index 99f77f347d..70a6449125 100644 --- a/src/mainboard/system76/lemp9/acpi/gpe.asl +++ b/src/mainboard/system76/lemp9/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // GPP_D9 SCI Method (_L29, 0, Serialized) { diff --git a/src/mainboard/system76/lemp9/acpi/hid.asl b/src/mainboard/system76/lemp9/acpi/hid.asl index f89bc82208..4567bb546b 100644 --- a/src/mainboard/system76/lemp9/acpi/hid.asl +++ b/src/mainboard/system76/lemp9/acpi/hid.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (HIDD) { diff --git a/src/mainboard/system76/lemp9/acpi/lid.asl b/src/mainboard/system76/lemp9/acpi/lid.asl index 3d7dddbc20..ae38f3ec83 100644 --- a/src/mainboard/system76/lemp9/acpi/lid.asl +++ b/src/mainboard/system76/lemp9/acpi/lid.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LID0) { diff --git a/src/mainboard/system76/lemp9/acpi/mainboard.asl b/src/mainboard/system76/lemp9/acpi/mainboard.asl index 1f2b33d2a8..d729c788c6 100644 --- a/src/mainboard/system76/lemp9/acpi/mainboard.asl +++ b/src/mainboard/system76/lemp9/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { #include "ac.asl" diff --git a/src/mainboard/system76/lemp9/acpi/s76.asl b/src/mainboard/system76/lemp9/acpi/s76.asl index 042e7e2431..e4cf619f50 100644 --- a/src/mainboard/system76/lemp9/acpi/s76.asl +++ b/src/mainboard/system76/lemp9/acpi/s76.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Notifications: // 0x80 - hardware backlight toggle diff --git a/src/mainboard/system76/lemp9/acpi/sleep.asl b/src/mainboard/system76/lemp9/acpi/sleep.asl index bb01a96a9b..ac5276041e 100644 --- a/src/mainboard/system76/lemp9/acpi/sleep.asl +++ b/src/mainboard/system76/lemp9/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Method called from _PTS prior to enter sleep state */ Method (MPTS, 1) { diff --git a/src/mainboard/system76/lemp9/bootblock.c b/src/mainboard/system76/lemp9/bootblock.c index 989ea3cc14..b591932150 100644 --- a/src/mainboard/system76/lemp9/bootblock.c +++ b/src/mainboard/system76/lemp9/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl index 7e3fdf503b..64d5399011 100644 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ b/src/mainboard/system76/lemp9/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h index f837ea4c72..1cbbbece81 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/lemp9/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/lemp9/hda_verb.c index 4f8aa2d117..0ba21af4b1 100644 --- a/src/mainboard/system76/lemp9/hda_verb.c +++ b/src/mainboard/system76/lemp9/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/system76/lemp9/ramstage.c b/src/mainboard/system76/lemp9/ramstage.c index e73a892ef3..f0f88c9bd2 100644 --- a/src/mainboard/system76/lemp9/ramstage.c +++ b/src/mainboard/system76/lemp9/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "gpio.h" diff --git a/src/mainboard/system76/lemp9/romstage.c b/src/mainboard/system76/lemp9/romstage.c index e456ffc51f..1921cae663 100644 --- a/src/mainboard/system76/lemp9/romstage.c +++ b/src/mainboard/system76/lemp9/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From f149d4cd64e7aabe93d6e5aa60f36de54692e6e4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:38 +0200 Subject: [PATCH 0788/1463] mainboard/ti: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Idcf639102b041ae46952df28c69dce02e1d3d689 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40103 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/ti/beaglebone/bootblock.c | 15 ++------------- src/mainboard/ti/beaglebone/romstage.c | 15 ++------------- 2 files changed, 4 insertions(+), 26 deletions(-) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index ec5fa4e91b..9f5f2adcb6 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c index 27069005bc..6e6b474b87 100644 --- a/src/mainboard/ti/beaglebone/romstage.c +++ b/src/mainboard/ti/beaglebone/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 2c82fe3a4c9edc8b6fe2968c6c62d39ff907dd2c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:06 +0200 Subject: [PATCH 0789/1463] mainboard/razer: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8fb7bc8056bbd940a2286b6a11a819335aa77ace Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40094 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl | 15 ++------------- .../razer/blade_stealth_kbl/acpi/battery.asl | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl | 15 ++------------- .../razer/blade_stealth_kbl/acpi/mainboard.asl | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/dsdt.asl | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/gpio.h | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/hda_verb.c | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/mainboard.c | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/ramstage.c | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/romstage.c | 15 ++------------- src/mainboard/razer/blade_stealth_kbl/spd/spd.h | 15 ++------------- .../razer/blade_stealth_kbl/spd/spd_util.c | 15 ++------------- 12 files changed, 24 insertions(+), 156 deletions(-) diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl index 08d6b6d47d..a6eb0843a5 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (AC) { diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl index a7a279877f..a33f45bea1 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (BAT) { diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 4b4356c857..112da9d8a7 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EC) { diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl index 7bc42ecb7c..1563f572f0 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index 87ad7c9811..1900877096 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index bee21ce7a0..aa5f50aae7 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c index 5da6d53414..7dcb47876c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c +++ b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/razer/blade_stealth_kbl/mainboard.c b/src/mainboard/razer/blade_stealth_kbl/mainboard.c index 6c0832f214..ff76529985 100644 --- a/src/mainboard/razer/blade_stealth_kbl/mainboard.c +++ b/src/mainboard/razer/blade_stealth_kbl/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/razer/blade_stealth_kbl/ramstage.c b/src/mainboard/razer/blade_stealth_kbl/ramstage.c index 975951ecae..ad70ca0c34 100644 --- a/src/mainboard/razer/blade_stealth_kbl/ramstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "gpio.h" diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index db7027ab4f..f08ffdc338 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h index d02bb3415f..c3bf2261f6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c index cd6596043a..719eab0e4e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 652dce4d1f18c76269dfb19e20e5745835739573 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:17 +0200 Subject: [PATCH 0790/1463] mainboard/sapphire: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I840a776c237a630c0ff6df7d2ee065be51224658 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40097 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../sapphire/pureplatinumh61/acpi/platform.asl | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl index cb4c8835e7..bd55316ef1 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl +++ b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 From 0c58dc6ce3805451dc4bcf93d89c51690f61c145 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:09 +0200 Subject: [PATCH 0791/1463] mainboard/apple: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I6537288b326172d70aac7849b8d9e33c7f5aff9c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40065 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/apple/macbook21/acpi/ec.asl | 14 ++------------ .../apple/macbook21/acpi/ich7_pci_irqs.asl | 16 ++-------------- src/mainboard/apple/macbook21/acpi/platform.asl | 16 ++-------------- src/mainboard/apple/macbook21/acpi_tables.c | 16 ++-------------- src/mainboard/apple/macbook21/dsdt.asl | 16 ++-------------- src/mainboard/apple/macbook21/early_init.c | 16 ++-------------- src/mainboard/apple/macbook21/gpio.c | 15 ++------------- src/mainboard/apple/macbook21/mainboard.c | 16 ++-------------- src/mainboard/apple/macbook21/mptable.c | 16 ++-------------- src/mainboard/apple/macbook21/smihandler.c | 16 ++-------------- src/mainboard/apple/macbookair4_2/acpi/ec.asl | 14 ++------------ .../apple/macbookair4_2/acpi/platform.asl | 14 ++------------ src/mainboard/apple/macbookair4_2/dsdt.asl | 14 ++------------ src/mainboard/apple/macbookair4_2/early_init.c | 14 ++------------ src/mainboard/apple/macbookair4_2/gnvs.c | 14 ++------------ src/mainboard/apple/macbookair4_2/gpio.c | 14 ++------------ src/mainboard/apple/macbookair4_2/hda_verb.c | 14 ++------------ src/mainboard/apple/macbookair4_2/mainboard.c | 14 ++------------ 18 files changed, 36 insertions(+), 233 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index 0a8ebca7a9..ccdf055456 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC) { diff --git a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl index 5a09b686bd..47aeb3d7a3 100644 --- a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl index 4777e19b2d..bd413af1d4 100644 --- a/src/mainboard/apple/macbook21/acpi/platform.asl +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index 0675b4114d..4a4c02ccb4 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index ffd5973f14..f14272d5a7 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define BRIGHTNESS_UP \DSPC.BRTU #define BRIGHTNESS_DOWN \DSPC.BRTD diff --git a/src/mainboard/apple/macbook21/early_init.c b/src/mainboard/apple/macbook21/early_init.c index 3878ec7f2f..4b6c63c758 100644 --- a/src/mainboard/apple/macbook21/early_init.c +++ b/src/mainboard/apple/macbook21/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c index 695c3c9227..b4bfe0e03b 100644 --- a/src/mainboard/apple/macbook21/gpio.c +++ b/src/mainboard/apple/macbook21/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 95bf4ada5d..cb722562c8 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index 059abad075..a48dfb65bc 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 7cf97af155..4492d6b36a 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/apple/macbookair4_2/acpi/ec.asl b/src/mainboard/apple/macbookair4_2/acpi/ec.asl index f70cb3ddcf..25b989ccbc 100644 --- a/src/mainboard/apple/macbookair4_2/acpi/ec.asl +++ b/src/mainboard/apple/macbookair4_2/acpi/ec.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC) { diff --git a/src/mainboard/apple/macbookair4_2/acpi/platform.asl b/src/mainboard/apple/macbookair4_2/acpi/platform.asl index 2d77180e1d..af17b0e388 100644 --- a/src/mainboard/apple/macbookair4_2/acpi/platform.asl +++ b/src/mainboard/apple/macbookair4_2/acpi/platform.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK,1) { diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index f48d0dd239..01656ad269 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index 29a2977444..9aa5ef4cca 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index def9e5fd74..0ae70f7c17 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/apple/macbookair4_2/gpio.c b/src/mainboard/apple/macbookair4_2/gpio.c index 485ca9520d..db095fc561 100644 --- a/src/mainboard/apple/macbookair4_2/gpio.c +++ b/src/mainboard/apple/macbookair4_2/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/apple/macbookair4_2/hda_verb.c b/src/mainboard/apple/macbookair4_2/hda_verb.c index f9267e4a2b..b5fd269e12 100644 --- a/src/mainboard/apple/macbookair4_2/hda_verb.c +++ b/src/mainboard/apple/macbookair4_2/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/apple/macbookair4_2/mainboard.c b/src/mainboard/apple/macbookair4_2/mainboard.c index d942e9b2cc..1369df1834 100644 --- a/src/mainboard/apple/macbookair4_2/mainboard.c +++ b/src/mainboard/apple/macbookair4_2/mainboard.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 08da24e059e9baf6466a8bbe67fc16f9c84f8868 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:24 +0200 Subject: [PATCH 0792/1463] mainboard/biostar: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib697a4b1eb74cced9f22c3c602215f0dcac81f20 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40069 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/biostar/a68n_5200/BiosCallOuts.c | 15 ++------------- src/mainboard/biostar/a68n_5200/OemCustomize.c | 15 ++------------- src/mainboard/biostar/a68n_5200/OptionsIds.h | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/gpe.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/ide.asl | 15 ++------------- .../biostar/a68n_5200/acpi/mainboard.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/routing.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/sata.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/si.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/sleep.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/acpi_tables.c | 15 ++------------- src/mainboard/biostar/a68n_5200/bootblock.c | 15 ++------------- src/mainboard/biostar/a68n_5200/buildOpts.c | 15 ++------------- src/mainboard/biostar/a68n_5200/dsdt.asl | 15 ++------------- src/mainboard/biostar/a68n_5200/irq_tables.c | 15 ++------------- src/mainboard/biostar/a68n_5200/mainboard.c | 15 ++------------- src/mainboard/biostar/a68n_5200/mptable.c | 15 ++------------- src/mainboard/biostar/am1ml/BiosCallOuts.c | 15 ++------------- src/mainboard/biostar/am1ml/OemCustomize.c | 15 ++------------- src/mainboard/biostar/am1ml/OptionsIds.h | 15 ++------------- src/mainboard/biostar/am1ml/acpi/flag0.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/gpe.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/ide.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/mainboard.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/routing.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/sata.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/si.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/sio.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/sleep.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/superio.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi/usb_oc.asl | 15 ++------------- src/mainboard/biostar/am1ml/acpi_tables.c | 15 ++------------- src/mainboard/biostar/am1ml/bootblock.c | 14 ++------------ src/mainboard/biostar/am1ml/buildOpts.c | 15 ++------------- src/mainboard/biostar/am1ml/dsdt.asl | 15 ++------------- src/mainboard/biostar/am1ml/mainboard.c | 15 ++------------- src/mainboard/biostar/am1ml/mptable.c | 15 ++------------- 39 files changed, 78 insertions(+), 506 deletions(-) diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c index ecc7985932..0d91cac89d 100644 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c index e207c0303a..e261171cb2 100644 --- a/src/mainboard/biostar/a68n_5200/OemCustomize.c +++ b/src/mainboard/biostar/a68n_5200/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/a68n_5200/OptionsIds.h b/src/mainboard/biostar/a68n_5200/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/biostar/a68n_5200/OptionsIds.h +++ b/src/mainboard/biostar/a68n_5200/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl index 0910e6a2b6..b41d372d13 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ //BTDC Due to IMC Fan, ACPI control codes OperationRegion(IMIO, SystemIO, 0x3E, 0x02) diff --git a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/ide.asl b/src/mainboard/biostar/a68n_5200/acpi/ide.asl index e17d93befd..85237670a2 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/ide.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No IDE functionality */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/routing.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/biostar/a68n_5200/acpi/sata.asl b/src/mainboard/biostar/a68n_5200/acpi/sata.asl index 00d855adb0..864eb9e07c 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/sata.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No SATA functionality */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/si.asl b/src/mainboard/biostar/a68n_5200/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/si.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl index 7ceb70ce04..4ea18f54b8 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/biostar/a68n_5200/acpi_tables.c +++ b/src/mainboard/biostar/a68n_5200/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/a68n_5200/bootblock.c b/src/mainboard/biostar/a68n_5200/bootblock.c index df033c1ef7..1d1f0f142b 100644 --- a/src/mainboard/biostar/a68n_5200/bootblock.c +++ b/src/mainboard/biostar/a68n_5200/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 0b89298b9d..335d759a13 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index 15b241f897..1b822e60ba 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/biostar/a68n_5200/irq_tables.c b/src/mainboard/biostar/a68n_5200/irq_tables.c index 6fb65c00ba..a3d7c32397 100644 --- a/src/mainboard/biostar/a68n_5200/irq_tables.c +++ b/src/mainboard/biostar/a68n_5200/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c index b3e47f8ec3..963f8949f3 100644 --- a/src/mainboard/biostar/a68n_5200/mainboard.c +++ b/src/mainboard/biostar/a68n_5200/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index 6e1d402833..73e6cc4e7d 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 0ea90d53cf..7a574f66f3 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index 3ea2310181..b5c960157a 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/am1ml/OptionsIds.h b/src/mainboard/biostar/am1ml/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/biostar/am1ml/OptionsIds.h +++ b/src/mainboard/biostar/am1ml/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/biostar/am1ml/acpi/flag0.asl b/src/mainboard/biostar/am1ml/acpi/flag0.asl index 649ff9d582..d79c0efc40 100644 --- a/src/mainboard/biostar/am1ml/acpi/flag0.asl +++ b/src/mainboard/biostar/am1ml/acpi/flag0.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) diff --git a/src/mainboard/biostar/am1ml/acpi/gpe.asl b/src/mainboard/biostar/am1ml/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/biostar/am1ml/acpi/gpe.asl +++ b/src/mainboard/biostar/am1ml/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/biostar/am1ml/acpi/ide.asl b/src/mainboard/biostar/am1ml/acpi/ide.asl index 06fe163a1c..cfe044ef2f 100644 --- a/src/mainboard/biostar/am1ml/acpi/ide.asl +++ b/src/mainboard/biostar/am1ml/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No IDE functionality */ diff --git a/src/mainboard/biostar/am1ml/acpi/mainboard.asl b/src/mainboard/biostar/am1ml/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/biostar/am1ml/acpi/mainboard.asl +++ b/src/mainboard/biostar/am1ml/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/biostar/am1ml/acpi/routing.asl b/src/mainboard/biostar/am1ml/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/biostar/am1ml/acpi/routing.asl +++ b/src/mainboard/biostar/am1ml/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl index dc015dcb5a..59fd57c952 100644 --- a/src/mainboard/biostar/am1ml/acpi/sata.asl +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ diff --git a/src/mainboard/biostar/am1ml/acpi/si.asl b/src/mainboard/biostar/am1ml/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/biostar/am1ml/acpi/si.asl +++ b/src/mainboard/biostar/am1ml/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/biostar/am1ml/acpi/sio.asl b/src/mainboard/biostar/am1ml/acpi/sio.asl index a43f9ac013..29977da44b 100644 --- a/src/mainboard/biostar/am1ml/acpi/sio.asl +++ b/src/mainboard/biostar/am1ml/acpi/sio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ OperationRegion (IOID, SystemIO, 0x2E, 0x02) Field (IOID, ByteAcc, NoLock, Preserve) diff --git a/src/mainboard/biostar/am1ml/acpi/sleep.asl b/src/mainboard/biostar/am1ml/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/biostar/am1ml/acpi/sleep.asl +++ b/src/mainboard/biostar/am1ml/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/biostar/am1ml/acpi/superio.asl b/src/mainboard/biostar/am1ml/acpi/superio.asl index 20c9e94297..2be618f2df 100644 --- a/src/mainboard/biostar/am1ml/acpi/superio.asl +++ b/src/mainboard/biostar/am1ml/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/mainboard/biostar/am1ml/acpi/usb_oc.asl b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl index 20189c94dd..6ebc4bc4c4 100644 --- a/src/mainboard/biostar/am1ml/acpi/usb_oc.asl +++ b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c index 2c7bacf0eb..e6397d3632 100644 --- a/src/mainboard/biostar/am1ml/acpi_tables.c +++ b/src/mainboard/biostar/am1ml/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c index 3eceaa782d..8b3a61dd19 100644 --- a/src/mainboard/biostar/am1ml/bootblock.c +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 1806580d06..eb265d6133 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index f454732858..a2e69b188c 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index bd198ce8eb..71ddfd014b 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index 2eced4e45e..8e418d6241 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 585495e887c61b3a19c369217a85ae9e147ad076 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:38 +0200 Subject: [PATCH 0793/1463] mainboard/emulation: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I68d2a8ac6f201f3c1131252b2b53b2b17ece1db6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40073 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/emulation/qemu-aarch64/bootblock.c | 14 ++------------ src/mainboard/emulation/qemu-armv7/cbmem.c | 14 ++------------ src/mainboard/emulation/qemu-armv7/media.c | 15 ++------------- src/mainboard/emulation/qemu-armv7/memlayout.ld | 15 ++------------- src/mainboard/emulation/qemu-armv7/mmio.c | 14 ++------------ src/mainboard/emulation/qemu-armv7/romstage.c | 15 ++------------- src/mainboard/emulation/qemu-armv7/timer.c | 15 ++------------- .../emulation/qemu-i440fx/acpi/cpu-hotplug.asl | 14 ++------------ .../emulation/qemu-i440fx/acpi/dbug.asl | 14 ++------------ .../emulation/qemu-i440fx/acpi/hpet.asl | 14 ++------------ src/mainboard/emulation/qemu-i440fx/acpi/isa.asl | 14 ++------------ .../emulation/qemu-i440fx/acpi/pci-crs.asl | 14 ++------------ .../emulation/qemu-i440fx/acpi_tables.c | 15 ++------------- src/mainboard/emulation/qemu-i440fx/exit_car.S | 15 ++------------- src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 14 ++------------ src/mainboard/emulation/qemu-i440fx/fw_cfg.h | 14 ++------------ src/mainboard/emulation/qemu-i440fx/irq_tables.c | 14 ++------------ src/mainboard/emulation/qemu-i440fx/mainboard.c | 15 ++------------- src/mainboard/emulation/qemu-i440fx/memmap.c | 15 ++------------- src/mainboard/emulation/qemu-i440fx/memory.h | 15 ++------------- .../emulation/qemu-i440fx/northbridge.c | 14 ++------------ src/mainboard/emulation/qemu-i440fx/romstage.c | 15 ++------------- src/mainboard/emulation/qemu-power8/bootblock.c | 15 ++------------- src/mainboard/emulation/qemu-power8/cbmem.c | 15 ++------------- src/mainboard/emulation/qemu-power8/mainboard.c | 15 ++------------- src/mainboard/emulation/qemu-power8/memlayout.ld | 15 ++------------- src/mainboard/emulation/qemu-power8/romstage.c | 15 ++------------- src/mainboard/emulation/qemu-power8/timer.c | 14 ++------------ src/mainboard/emulation/qemu-power8/uart.c | 15 ++------------- src/mainboard/emulation/qemu-q35/acpi_tables.c | 15 ++------------- src/mainboard/emulation/qemu-q35/bootblock.c | 14 ++------------ src/mainboard/emulation/qemu-q35/hda_verb.c | 14 ++------------ src/mainboard/emulation/qemu-q35/mainboard.c | 15 ++------------- src/mainboard/emulation/qemu-q35/romstage.c | 15 ++------------- src/mainboard/emulation/qemu-riscv/clint.c | 15 ++------------- .../qemu-riscv/include/mainboard/addressmap.h | 15 ++------------- src/mainboard/emulation/qemu-riscv/mainboard.c | 15 ++------------- src/mainboard/emulation/qemu-riscv/memlayout.ld | 15 ++------------- src/mainboard/emulation/qemu-riscv/rom_media.c | 16 ++-------------- src/mainboard/emulation/qemu-riscv/romstage.c | 15 ++------------- src/mainboard/emulation/qemu-riscv/uart.c | 15 ++------------- src/mainboard/emulation/spike-riscv/clint.c | 15 ++------------- src/mainboard/emulation/spike-riscv/mainboard.c | 15 ++------------- src/mainboard/emulation/spike-riscv/memlayout.ld | 15 ++------------- src/mainboard/emulation/spike-riscv/rom_media.c | 16 ++-------------- src/mainboard/emulation/spike-riscv/romstage.c | 15 ++------------- src/mainboard/emulation/spike-riscv/uart.c | 15 ++------------- 47 files changed, 94 insertions(+), 598 deletions(-) diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock.c b/src/mainboard/emulation/qemu-aarch64/bootblock.c index 77d7e532de..9006d65d8f 100644 --- a/src/mainboard/emulation/qemu-aarch64/bootblock.c +++ b/src/mainboard/emulation/qemu-aarch64/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 143e11b88c..b904b44797 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c index d271afef4a..529c7b3c89 100644 --- a/src/mainboard/emulation/qemu-armv7/media.c +++ b/src/mainboard/emulation/qemu-armv7/media.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index aa8588254a..2fee6991f0 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-armv7/mmio.c b/src/mainboard/emulation/qemu-armv7/mmio.c index 4b03e0e552..00c5b45481 100644 --- a/src/mainboard/emulation/qemu-armv7/mmio.c +++ b/src/mainboard/emulation/qemu-armv7/mmio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c index e881ca1a77..3e5803b642 100644 --- a/src/mainboard/emulation/qemu-armv7/romstage.c +++ b/src/mainboard/emulation/qemu-armv7/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-armv7/timer.c b/src/mainboard/emulation/qemu-armv7/timer.c index 5359827e65..aecaae89aa 100644 --- a/src/mainboard/emulation/qemu-armv7/timer.c +++ b/src/mainboard/emulation/qemu-armv7/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ void udelay(unsigned int n); void udelay(unsigned int n) diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl index e46611d219..aaecc8db6f 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /**************************************************************** * CPU hotplug diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl index 052251fbba..bad103ad57 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /**************************************************************** * Debugging diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl index 60b2f00573..421dd2ab90 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /**************************************************************** * HPET diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl b/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl index 51d6ce3746..c14c959ee5 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Common legacy ISA style devices. */ Scope(\_SB.PCI0.ISA) { diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl b/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl index daa0a328f1..81d91929a6 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCI CRS (current resources) definition. */ Scope(\_SB.PCI0) { diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index e4763cdbdd..08df134e59 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/exit_car.S b/src/mainboard/emulation/qemu-i440fx/exit_car.S index 06f1256768..f1dc626ecf 100644 --- a/src/mainboard/emulation/qemu-i440fx/exit_car.S +++ b/src/mainboard/emulation/qemu-i440fx/exit_car.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .text .global chipset_teardown_car chipset_teardown_car: diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 50123f97b4..8afd832aeb 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h index 975801b60e..3824aa35e3 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef FW_CFG_H #define FW_CFG_H #include "fw_cfg_if.h" diff --git a/src/mainboard/emulation/qemu-i440fx/irq_tables.c b/src/mainboard/emulation/qemu-i440fx/irq_tables.c index 001027b8c6..bad8c2b4a3 100644 --- a/src/mainboard/emulation/qemu-i440fx/irq_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/irq_tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 6f0cd18349..5e9b3208c6 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index bc9fc602b3..5f0e149b6a 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/memory.h b/src/mainboard/emulation/qemu-i440fx/memory.h index 33201b6f7f..7e9ee7134e 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.h +++ b/src/mainboard/emulation/qemu-i440fx/memory.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __QEMU_MEMORY_H_ diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 74e52de095..38ab9df71b 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 6c9d946ce6..e44488b897 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index c984039c97..9e56ba9ca4 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 2bacc2b07c..b84d1c8a20 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c index 6bfd0b3867..f4bf42906b 100644 --- a/src/mainboard/emulation/qemu-power8/mainboard.c +++ b/src/mainboard/emulation/qemu-power8/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index fe7070b642..eb26c60b6c 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-power8/romstage.c b/src/mainboard/emulation/qemu-power8/romstage.c index e881ca1a77..3e5803b642 100644 --- a/src/mainboard/emulation/qemu-power8/romstage.c +++ b/src/mainboard/emulation/qemu-power8/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-power8/timer.c b/src/mainboard/emulation/qemu-power8/timer.c index 65b8ecf02f..d7c1575cc9 100644 --- a/src/mainboard/emulation/qemu-power8/timer.c +++ b/src/mainboard/emulation/qemu-power8/timer.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 661b680dcc..400c24988e 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 793b58e742..29dcedf541 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index d5ca7f9ce7..88be6df891 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-q35/hda_verb.c b/src/mainboard/emulation/qemu-q35/hda_verb.c index 5d088790a5..0700c48e63 100644 --- a/src/mainboard/emulation/qemu-q35/hda_verb.c +++ b/src/mainboard/emulation/qemu-q35/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 4ccbcd0524..6bb99cd24d 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 602b981b15..729431ecc4 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index deceb5b804..6b9c5e01fd 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index d0a8f39091..ff95c09b47 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define QEMU_VIRT_CLINT 0x02000000 #define QEMU_VIRT_PLIC 0x0c000000 diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index de7765e5d6..0a548b0df5 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 2fb1b1bb98..571810313e 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 7543ab9ab4..1f2632caa5 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c index 82f1a360db..a5ae5ed35a 100644 --- a/src/mainboard/emulation/qemu-riscv/romstage.c +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 3adc61ecc0..d742c7dfab 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index c3fa3387f0..7f56dcaf65 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv/mainboard.c index 1369a54d70..6b4a96b43b 100644 --- a/src/mainboard/emulation/spike-riscv/mainboard.c +++ b/src/mainboard/emulation/spike-riscv/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 6b647b6e5b..dd7bdbef5a 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv/rom_media.c index 2ee04927e8..676f090ea9 100644 --- a/src/mainboard/emulation/spike-riscv/rom_media.c +++ b/src/mainboard/emulation/spike-riscv/rom_media.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include /* diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv/romstage.c index 118e9562b9..bf71b3214a 100644 --- a/src/mainboard/emulation/spike-riscv/romstage.c +++ b/src/mainboard/emulation/spike-riscv/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index f916f61fb2..1a79c433e0 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From ec9eb64f4c925b3c52578bce94421adf2dc5f821 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:45 +0200 Subject: [PATCH 0794/1463] mainboard/foxconn: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8da7a1a2ae85eb0a5a33c18f233228d81f6938f3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40075 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../foxconn/d41s/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/foxconn/d41s/acpi/superio.asl | 15 ++------------- src/mainboard/foxconn/d41s/acpi_tables.c | 15 ++------------- src/mainboard/foxconn/d41s/cstates.c | 15 ++------------- src/mainboard/foxconn/d41s/dsdt.asl | 15 ++------------- src/mainboard/foxconn/d41s/gpio.c | 16 ++-------------- src/mainboard/foxconn/d41s/hda_verb.c | 15 ++------------- src/mainboard/foxconn/d41s/mainboard.c | 15 ++------------- src/mainboard/foxconn/g41s-k/acpi/superio.asl | 15 ++------------- src/mainboard/foxconn/g41s-k/acpi_tables.c | 15 ++------------- src/mainboard/foxconn/g41s-k/cstates.c | 15 ++------------- src/mainboard/foxconn/g41s-k/dsdt.asl | 15 ++------------- src/mainboard/foxconn/g41s-k/gpio.c | 15 ++------------- .../variants/g41s-k/acpi/ich7_pci_irqs.asl | 15 ++------------- 14 files changed, 28 insertions(+), 183 deletions(-) diff --git a/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl index 6323193c96..3ea2853ac9 100644 --- a/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/foxconn/d41s/acpi/superio.asl b/src/mainboard/foxconn/d41s/acpi/superio.asl index d3d0252932..66009bda86 100644 --- a/src/mainboard/foxconn/d41s/acpi/superio.asl +++ b/src/mainboard/foxconn/d41s/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c index 69787a93ea..f9c941d79e 100644 --- a/src/mainboard/foxconn/d41s/acpi_tables.c +++ b/src/mainboard/foxconn/d41s/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/foxconn/d41s/cstates.c b/src/mainboard/foxconn/d41s/cstates.c index 62b3bd3fba..10498e1150 100644 --- a/src/mainboard/foxconn/d41s/cstates.c +++ b/src/mainboard/foxconn/d41s/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl index 88b4e126e5..75b17df090 100644 --- a/src/mainboard/foxconn/d41s/dsdt.asl +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/foxconn/d41s/gpio.c b/src/mainboard/foxconn/d41s/gpio.c index 5da221d047..9224dbeeff 100644 --- a/src/mainboard/foxconn/d41s/gpio.c +++ b/src/mainboard/foxconn/d41s/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/foxconn/d41s/hda_verb.c b/src/mainboard/foxconn/d41s/hda_verb.c index 93d0144f83..0da12cbc5b 100644 --- a/src/mainboard/foxconn/d41s/hda_verb.c +++ b/src/mainboard/foxconn/d41s/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/foxconn/d41s/mainboard.c b/src/mainboard/foxconn/d41s/mainboard.c index dd930d31ad..4834c625b1 100644 --- a/src/mainboard/foxconn/d41s/mainboard.c +++ b/src/mainboard/foxconn/d41s/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl index 2767faaad8..84f5dd66f5 100644 --- a/src/mainboard/foxconn/g41s-k/acpi/superio.asl +++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c index b0940a0063..0ae4da259c 100644 --- a/src/mainboard/foxconn/g41s-k/acpi_tables.c +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/foxconn/g41s-k/cstates.c b/src/mainboard/foxconn/g41s-k/cstates.c index 2a6d8ad816..10498e1150 100644 --- a/src/mainboard/foxconn/g41s-k/cstates.c +++ b/src/mainboard/foxconn/g41s-k/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index 6120949269..8880ba7076 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/foxconn/g41s-k/gpio.c b/src/mainboard/foxconn/g41s-k/gpio.c index 8d43757fd5..abdae07062 100644 --- a/src/mainboard/foxconn/g41s-k/gpio.c +++ b/src/mainboard/foxconn/g41s-k/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl index 1ecd961916..026922e01a 100644 --- a/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is board specific information: From c80e35008991e6071df20ec03abcdbaef5a0ce88 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:49 +0200 Subject: [PATCH 0795/1463] mainboard/getac: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I9528563399d8f47570a602a378583487f3cacc8c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40076 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/getac/p470/acpi/battery.asl | 16 ++-------------- src/mainboard/getac/p470/acpi/ec.asl | 16 ++-------------- src/mainboard/getac/p470/acpi/gpe.asl | 16 ++-------------- src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl | 16 ++-------------- src/mainboard/getac/p470/acpi/mainboard.asl | 16 ++-------------- src/mainboard/getac/p470/acpi/platform.asl | 16 ++-------------- src/mainboard/getac/p470/acpi/superio.asl | 16 ++-------------- src/mainboard/getac/p470/acpi/thermal.asl | 16 ++-------------- src/mainboard/getac/p470/acpi_tables.c | 16 ++-------------- src/mainboard/getac/p470/cstates.c | 14 ++------------ src/mainboard/getac/p470/dsdt.asl | 16 ++-------------- src/mainboard/getac/p470/early_init.c | 16 ++-------------- src/mainboard/getac/p470/ec_oem.c | 16 ++-------------- src/mainboard/getac/p470/ec_oem.h | 16 ++-------------- src/mainboard/getac/p470/gpio.c | 15 ++------------- src/mainboard/getac/p470/hda_verb.c | 15 ++------------- src/mainboard/getac/p470/irq_tables.c | 16 ++-------------- src/mainboard/getac/p470/mainboard.c | 16 ++-------------- src/mainboard/getac/p470/mainboard.h | 14 ++------------ src/mainboard/getac/p470/mptable.c | 16 ++-------------- src/mainboard/getac/p470/smihandler.c | 16 ++-------------- 21 files changed, 42 insertions(+), 288 deletions(-) diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index 006dbae999..32ed65271c 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SB) { diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 1b30e03ec5..df1cbdfdcc 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC0) { diff --git a/src/mainboard/getac/p470/acpi/gpe.asl b/src/mainboard/getac/p470/acpi/gpe.asl index 95ce678740..0d1e9eeb22 100644 --- a/src/mainboard/getac/p470/acpi/gpe.asl +++ b/src/mainboard/getac/p470/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (_GPE) { diff --git a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl index 94152f4080..8b612e5a50 100644 --- a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/getac/p470/acpi/mainboard.asl b/src/mainboard/getac/p470/acpi/mainboard.asl index 4357fc86e6..412c299d35 100644 --- a/src/mainboard/getac/p470/acpi/mainboard.asl +++ b/src/mainboard/getac/p470/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LID0) { diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index b2d9fd0125..2b2c207e61 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl index 89b63a75fb..7510e113a5 100644 --- a/src/mainboard/getac/p470/acpi/superio.asl +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SMSC SIO10N268 */ diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 2a4d7a9195..f479960a6e 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index c2a0920885..c31d76d585 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c index 81d66a1ca1..69949f519b 100644 --- a/src/mainboard/getac/p470/cstates.c +++ b/src/mainboard/getac/p470/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index 8da962ecb4..dacdbdf936 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ENABLE_TPM #undef ENABLE_FDC // There is no Floppy for this laptop diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index c12cc6f7de..cc126dd3b9 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c index 344374b358..07481f0acc 100644 --- a/src/mainboard/getac/p470/ec_oem.c +++ b/src/mainboard/getac/p470/ec_oem.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h index 5f9616fab0..26e8a169c4 100644 --- a/src/mainboard/getac/p470/ec_oem.h +++ b/src/mainboard/getac/p470/ec_oem.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_EC_OEM_H #define _MAINBOARD_EC_OEM_H diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c index c19e27a29e..1031f92318 100644 --- a/src/mainboard/getac/p470/gpio.c +++ b/src/mainboard/getac/p470/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c index 23e8be686a..9826f05c6d 100644 --- a/src/mainboard/getac/p470/hda_verb.c +++ b/src/mainboard/getac/p470/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c index c279d6b684..eaa9a3c43c 100644 --- a/src/mainboard/getac/p470/irq_tables.c +++ b/src/mainboard/getac/p470/irq_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 6d9e0620ae..7456b7b464 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h index 0e6b24c30c..cc692f07a9 100644 --- a/src/mainboard/getac/p470/mainboard.h +++ b/src/mainboard/getac/p470/mainboard.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ struct acpi_rsdp; diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index b9d7632eb4..935eadf686 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index aaf123b654..108e511b2f 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 8dcc818b40aa7899fa0495dcd9bbff557977e88d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:52 +0200 Subject: [PATCH 0796/1463] mainboard/gigabyte: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I90691355cfc73f0834d45024a2885998b5652f88 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40077 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl | 15 ++------------- .../ga-945gcm-s2l/acpi/ich7_pci_irqs.asl | 15 ++------------- .../gigabyte/ga-945gcm-s2l/acpi/mainboard.asl | 15 ++------------- .../gigabyte/ga-945gcm-s2l/acpi/platform.asl | 15 ++------------- .../gigabyte/ga-945gcm-s2l/acpi_tables.c | 15 ++------------- src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c | 14 ++------------ src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl | 15 ++------------- .../gigabyte/ga-945gcm-s2l/early_init.c | 15 ++------------- src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c | 15 ++------------- src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c | 14 ++------------ .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 16 ++-------------- src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl | 16 ++-------------- .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 15 ++------------- .../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 15 ++------------- src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 15 ++------------- src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 14 ++------------ src/mainboard/gigabyte/ga-b75m-d3h/early_init.c | 15 ++------------- src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 14 ++------------ src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 15 ++------------- src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 15 ++------------- .../ga-b75m-d3h/variants/ga-b75-d3v/gpio.c | 16 ++-------------- .../ga-b75-d3v/include/variant/hda_verb.h | 14 ++------------ .../ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c | 14 ++------------ .../ga-b75m-d3h/include/variant/hda_verb.h | 14 ++------------ .../ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c | 14 ++------------ .../ga-b75m-d3v/include/variant/hda_verb.h | 14 ++------------ .../gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl | 15 ++------------- .../gigabyte/ga-g41m-es2l/acpi_tables.c | 15 ++------------- src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 15 ++------------- src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 15 ++------------- src/mainboard/gigabyte/ga-g41m-es2l/gpio.c | 15 ++------------- .../gigabyte/ga-h61m-series/acpi/mainboard.asl | 16 ++-------------- .../gigabyte/ga-h61m-series/acpi/platform.asl | 15 ++------------- .../gigabyte/ga-h61m-series/acpi/superio.asl | 15 ++------------- .../gigabyte/ga-h61m-series/acpi/thermal.asl | 15 ++------------- .../gigabyte/ga-h61m-series/acpi_tables.c | 15 ++------------- src/mainboard/gigabyte/ga-h61m-series/dsdt.asl | 15 ++------------- .../gigabyte/ga-h61m-series/early_init.c | 15 ++------------- .../gigabyte/ga-h61m-series/mainboard.c | 15 ++------------- .../ga-h61m-series/variants/ga-h61m-ds2v/gpio.c | 15 ++------------- .../variants/ga-h61m-ds2v/hda_verb.c | 16 ++-------------- .../ga-h61m-series/variants/ga-h61m-s2pv/gpio.c | 15 ++------------- .../variants/ga-h61m-s2pv/hda_verb.c | 16 ++-------------- .../ga-h61m-series/variants/ga-h61ma-d3v/gpio.c | 16 ++-------------- .../variants/ga-h61ma-d3v/hda_verb.c | 16 ++-------------- 45 files changed, 90 insertions(+), 584 deletions(-) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl index f42855b182..0cff3760bd 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC0) { diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl index 8d6dfa2867..feb129474e 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl index 5187b2a973..1e31c06ec9 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (SLPB) { diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl index 01c7a94906..64db274094 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c index 69787a93ea..f9c941d79e 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl index c9d81f523d..9e3c03748c 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c index 26ce1790bc..e89088e122 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c b/src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c index 71dd709c8f..c7a72d120b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c index 55cff054c2..d6fefcd666 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl index b7b6195a62..8dc85d9423 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl index 722a5d9f18..9e8dbaf5d1 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel PCI to PCI bridge 0:1e.0 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl index 90db019a82..6fb63456c4 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl index c035abbcce..081c581be9 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c index 9ef2b66097..d0b68b5fdc 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "thermal.h" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 91ed5511d4..ac65961b6d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 9a2b4a3dec..646268399a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c index 34610f09ee..fde4f9cb08 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index 80554a9823..5370fb95d3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h index 31462781e0..8dbf906ff5 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GAB75MD3H_THERMAL_H #define GAB75MD3H_THERMAL_H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c index 012773574a..0bfd7a0cce 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h index 8057a8762e..a6f7dde4c6 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GA_B75_D3V_HDA_VERB_H #define GA_B75_D3V_HDA_VERB_H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c index 3fcf3ad73c..ae77d3ff58 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h index 53e7c65ddb..9234dcbe00 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GA_B75M_D3H_HDA_VERB_H #define GA_B75M_D3H_HDA_VERB_H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c index 3da7f01649..b7efdba154 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h index c84c80df7b..927d584c71 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GA_B75M_D3V_HDA_VERB_H #define GA_B75M_D3V_HDA_VERB_H diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl index 20d7562770..db8b7e3346 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index 02ddd77af4..898bfd5dce 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index 1ba78ac31e..fd5a7f0c44 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index 6120949269..8880ba7076 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c b/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c index bb05851c88..d48517082a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl index 0483c161be..ccde6864f1 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/platform.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/platform.asl index 92c98614d7..b8d04f9ac0 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/superio.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/superio.asl index 606085fafe..1bc1628982 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi/superio.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl index c035abbcce..081c581be9 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c index 5a6a5e4de4..9179d302db 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index 61eb8efeb9..cea8efe111 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 diff --git a/src/mainboard/gigabyte/ga-h61m-series/early_init.c b/src/mainboard/gigabyte/ga-h61m-series/early_init.c index d006745f1b..7c75356977 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/early_init.c +++ b/src/mainboard/gigabyte/ga-h61m-series/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/mainboard.c b/src/mainboard/gigabyte/ga-h61m-series/mainboard.c index e14e31c041..ba9d40217c 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/mainboard.c +++ b/src/mainboard/gigabyte/ga-h61m-series/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/gpio.c index a438cda4fa..fa434d1eb9 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/gpio.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c index 069ba8fade..519dc9d2fe 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/gpio.c index 800298d882..b0d925e253 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/gpio.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c index 069ba8fade..519dc9d2fe 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/gpio.c index d24d16233d..fa434d1eb9 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/gpio.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c index 0baeed019c..a398afb0ed 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From 2dfba3708ee42a233316faead9ac3ac7889590b9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:55 +0200 Subject: [PATCH 0797/1463] mainboard/gizmosphere: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1135a495053b1c1229c94c794664b23f50d50362 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40078 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 15 ++------------- src/mainboard/gizmosphere/gizmo/OemCustomize.c | 15 ++------------- src/mainboard/gizmosphere/gizmo/OptionsIds.h | 15 ++------------- src/mainboard/gizmosphere/gizmo/acpi/gpe.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo/acpi/ide.asl | 15 ++------------- .../gizmosphere/gizmo/acpi/mainboard.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo/acpi/routing.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo/acpi/sata.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo/acpi/sleep.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo/acpi/superio.asl | 14 ++------------ src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo/acpi_tables.c | 15 ++------------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 15 ++------------- src/mainboard/gizmosphere/gizmo/dsdt.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo/irq_tables.c | 15 ++------------- src/mainboard/gizmosphere/gizmo/mainboard.c | 15 ++------------- src/mainboard/gizmosphere/gizmo/mptable.c | 15 ++------------- src/mainboard/gizmosphere/gizmo/platform_cfg.h | 15 ++------------- src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c | 15 ++------------- src/mainboard/gizmosphere/gizmo2/OemCustomize.c | 15 ++------------- src/mainboard/gizmosphere/gizmo2/OptionsIds.h | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi/ide.asl | 15 ++------------- .../gizmosphere/gizmo2/acpi/mainboard.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi/routing.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi/sata.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi/si.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/acpi_tables.c | 15 ++------------- src/mainboard/gizmosphere/gizmo2/bootblock.c | 14 ++------------ src/mainboard/gizmosphere/gizmo2/buildOpts.c | 15 ++------------- src/mainboard/gizmosphere/gizmo2/dsdt.asl | 15 ++------------- src/mainboard/gizmosphere/gizmo2/irq_tables.c | 15 ++------------- src/mainboard/gizmosphere/gizmo2/mainboard.c | 15 ++------------- src/mainboard/gizmosphere/gizmo2/mptable.c | 15 ++------------- 36 files changed, 72 insertions(+), 466 deletions(-) diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 6600c6c47a..5ea1bae875 100644 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index f25d8cf38f..4b6f95980e 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo/OptionsIds.h b/src/mainboard/gizmosphere/gizmo/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/gizmosphere/gizmo/OptionsIds.h +++ b/src/mainboard/gizmosphere/gizmo/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl index af4e2e48b7..5788140112 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/ide.asl b/src/mainboard/gizmosphere/gizmo/acpi/ide.asl index 00c4f8841d..6a289228ee 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/ide.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope (_SB) { diff --git a/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl b/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index dd63e9b63e..2ddb2885a9 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/gizmosphere/gizmo/acpi/sata.asl b/src/mainboard/gizmosphere/gizmo/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/sata.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl b/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl index 08144ff427..0c973a4a0c 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/gizmosphere/gizmo/acpi/superio.asl b/src/mainboard/gizmosphere/gizmo/acpi/superio.asl index daf6e9177b..21fdfe9e95 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/superio.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/superio.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No Super I/O device or functionality yet */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl index 5b22875dd1..27a737c730 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index bec93772b2..86b3f03ee9 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index 47ab7cfe99..a7b28c6985 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 14a60e691a..7a4bdabe39 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index 5746cadec9..10db6fd073 100644 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 7d5396b6cd..78390a6556 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index 6966cff36a..c8a34214b1 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c index d61960528b..16c185451a 100644 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/OptionsIds.h b/src/mainboard/gizmosphere/gizmo2/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/gizmosphere/gizmo2/OptionsIds.h +++ b/src/mainboard/gizmosphere/gizmo2/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl b/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl index e17d93befd..85237670a2 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No IDE functionality */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl b/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl index 00d855adb0..864eb9e07c 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No SATA functionality */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/si.asl b/src/mainboard/gizmosphere/gizmo2/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/si.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl index bf00545927..db55264f91 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/bootblock.c b/src/mainboard/gizmosphere/gizmo2/bootblock.c index 312b5cc0a6..891364d6fd 100644 --- a/src/mainboard/gizmosphere/gizmo2/bootblock.c +++ b/src/mainboard/gizmosphere/gizmo2/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 9ec18e9344..34e085a4d1 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index 15b241f897..1b822e60ba 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/gizmosphere/gizmo2/irq_tables.c b/src/mainboard/gizmosphere/gizmo2/irq_tables.c index 5f0654ad1e..b8077ff8c1 100644 --- a/src/mainboard/gizmosphere/gizmo2/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index 13d185ebb8..da073ecb36 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index e0a407bb25..e9e1dbe49f 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 381c4eb53b3ab8108faf50c13f95d6091c5bd7ca Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:06 +0200 Subject: [PATCH 0798/1463] mainboard/hp: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I42ab3846c75adca1fe74dfa5114c9b697127bb76 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40080 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/hp/abm/BiosCallOuts.c | 15 ++------------- src/mainboard/hp/abm/OemCustomize.c | 15 ++------------- src/mainboard/hp/abm/OptionsIds.h | 15 ++------------- src/mainboard/hp/abm/acpi/gpe.asl | 15 ++------------- src/mainboard/hp/abm/acpi/ide.asl | 15 ++------------- src/mainboard/hp/abm/acpi/mainboard.asl | 15 ++------------- src/mainboard/hp/abm/acpi/routing.asl | 15 ++------------- src/mainboard/hp/abm/acpi/sata.asl | 15 ++------------- src/mainboard/hp/abm/acpi/si.asl | 15 ++------------- src/mainboard/hp/abm/acpi/sleep.asl | 15 ++------------- src/mainboard/hp/abm/acpi/usb_oc.asl | 15 ++------------- src/mainboard/hp/abm/acpi_tables.c | 15 ++------------- src/mainboard/hp/abm/bootblock.c | 14 ++------------ src/mainboard/hp/abm/buildOpts.c | 15 ++------------- src/mainboard/hp/abm/dsdt.asl | 15 ++------------- src/mainboard/hp/abm/irq_tables.c | 15 ++------------- src/mainboard/hp/abm/mainboard.c | 15 ++------------- src/mainboard/hp/abm/mptable.c | 15 ++------------- .../hp/compaq_8200_elite_sff/acpi/platform.asl | 15 ++------------- .../hp/compaq_8200_elite_sff/acpi/superio.asl | 15 ++------------- .../hp/compaq_8200_elite_sff/acpi_tables.c | 16 ++-------------- src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl | 15 ++------------- .../hp/compaq_8200_elite_sff/early_init.c | 16 ++-------------- src/mainboard/hp/compaq_8200_elite_sff/gpio.c | 16 ++-------------- .../hp/compaq_8200_elite_sff/hda_verb.c | 16 ++-------------- .../hp/compaq_8200_elite_sff/mainboard.c | 16 ++-------------- .../hp/pavilion_m6_1035dx/BiosCallOuts.c | 15 ++------------- .../hp/pavilion_m6_1035dx/OemCustomize.c | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 15 ++------------- .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 15 ++------------- .../hp/pavilion_m6_1035dx/acpi/routing.asl | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl | 15 ++------------- .../hp/pavilion_m6_1035dx/acpi/sleep.asl | 15 ++------------- .../hp/pavilion_m6_1035dx/acpi/usb_oc.asl | 15 ++------------- .../hp/pavilion_m6_1035dx/acpi_tables.c | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 15 ++------------- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 15 ++------------- src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl | 15 ++------------- .../hp/snb_ivb_laptops/acpi/platform.asl | 15 ++------------- .../hp/snb_ivb_laptops/acpi/superio.asl | 15 ++------------- src/mainboard/hp/snb_ivb_laptops/acpi_tables.c | 16 ++-------------- src/mainboard/hp/snb_ivb_laptops/dsdt.asl | 15 ++------------- src/mainboard/hp/snb_ivb_laptops/mainboard.c | 15 ++------------- .../snb_ivb_laptops/variants/2570p/early_init.c | 16 ++-------------- .../hp/snb_ivb_laptops/variants/2570p/gpio.c | 16 ++-------------- .../hp/snb_ivb_laptops/variants/2570p/hda_verb.c | 16 ++-------------- .../snb_ivb_laptops/variants/2760p/early_init.c | 15 ++------------- .../hp/snb_ivb_laptops/variants/2760p/gpio.c | 15 ++------------- .../hp/snb_ivb_laptops/variants/2760p/hda_verb.c | 15 ++------------- .../snb_ivb_laptops/variants/8460p/early_init.c | 16 ++-------------- .../hp/snb_ivb_laptops/variants/8460p/gpio.c | 16 ++-------------- .../hp/snb_ivb_laptops/variants/8460p/hda_verb.c | 16 ++-------------- .../snb_ivb_laptops/variants/8470p/early_init.c | 15 ++------------- .../hp/snb_ivb_laptops/variants/8470p/gpio.c | 16 ++-------------- .../hp/snb_ivb_laptops/variants/8470p/hda_verb.c | 15 ++------------- .../snb_ivb_laptops/variants/8770w/early_init.c | 15 ++------------- .../hp/snb_ivb_laptops/variants/8770w/gpio.c | 16 ++-------------- .../hp/snb_ivb_laptops/variants/8770w/hda_verb.c | 15 ++------------- .../variants/folio_9470m/early_init.c | 16 ++-------------- .../snb_ivb_laptops/variants/folio_9470m/gpio.c | 16 ++-------------- .../variants/folio_9470m/hda_verb.c | 16 ++-------------- .../variants/revolve_810_g1/early_init.c | 16 ++-------------- .../variants/revolve_810_g1/gpio.c | 16 ++-------------- .../variants/revolve_810_g1/hda_verb.c | 16 ++-------------- .../hp/z220_sff_workstation/acpi/platform.asl | 15 ++------------- .../hp/z220_sff_workstation/acpi/superio.asl | 15 ++------------- .../hp/z220_sff_workstation/acpi_tables.c | 16 ++-------------- src/mainboard/hp/z220_sff_workstation/dsdt.asl | 15 ++------------- .../hp/z220_sff_workstation/early_init.c | 16 ++-------------- src/mainboard/hp/z220_sff_workstation/gpio.c | 16 ++-------------- src/mainboard/hp/z220_sff_workstation/hda_verb.c | 16 ++-------------- .../hp/z220_sff_workstation/mainboard.c | 16 ++-------------- 76 files changed, 152 insertions(+), 1012 deletions(-) diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 2ee00fc22e..ae332ed7c8 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c index bc311cc457..2054081979 100644 --- a/src/mainboard/hp/abm/OemCustomize.c +++ b/src/mainboard/hp/abm/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h index b796375146..43cfdd75d5 100644 --- a/src/mainboard/hp/abm/OptionsIds.h +++ b/src/mainboard/hp/abm/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/hp/abm/acpi/gpe.asl b/src/mainboard/hp/abm/acpi/gpe.asl index 72bcf765c3..4e66be0e9c 100644 --- a/src/mainboard/hp/abm/acpi/gpe.asl +++ b/src/mainboard/hp/abm/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/hp/abm/acpi/ide.asl b/src/mainboard/hp/abm/acpi/ide.asl index e17d93befd..85237670a2 100644 --- a/src/mainboard/hp/abm/acpi/ide.asl +++ b/src/mainboard/hp/abm/acpi/ide.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No IDE functionality */ diff --git a/src/mainboard/hp/abm/acpi/mainboard.asl b/src/mainboard/hp/abm/acpi/mainboard.asl index 993000d2c6..e15ead22ae 100644 --- a/src/mainboard/hp/abm/acpi/mainboard.asl +++ b/src/mainboard/hp/abm/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/hp/abm/acpi/routing.asl b/src/mainboard/hp/abm/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/hp/abm/acpi/routing.asl +++ b/src/mainboard/hp/abm/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/hp/abm/acpi/sata.asl b/src/mainboard/hp/abm/acpi/sata.asl index 00d855adb0..864eb9e07c 100644 --- a/src/mainboard/hp/abm/acpi/sata.asl +++ b/src/mainboard/hp/abm/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No SATA functionality */ diff --git a/src/mainboard/hp/abm/acpi/si.asl b/src/mainboard/hp/abm/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/hp/abm/acpi/si.asl +++ b/src/mainboard/hp/abm/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/hp/abm/acpi/sleep.asl b/src/mainboard/hp/abm/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/hp/abm/acpi/sleep.asl +++ b/src/mainboard/hp/abm/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl index bf00545927..db55264f91 100644 --- a/src/mainboard/hp/abm/acpi/usb_oc.asl +++ b/src/mainboard/hp/abm/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/hp/abm/acpi_tables.c b/src/mainboard/hp/abm/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/hp/abm/acpi_tables.c +++ b/src/mainboard/hp/abm/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/abm/bootblock.c b/src/mainboard/hp/abm/bootblock.c index a48ba772e1..7a08ae117e 100644 --- a/src/mainboard/hp/abm/bootblock.c +++ b/src/mainboard/hp/abm/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 1b0e853ad6..786d9cb078 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index 15b241f897..1b822e60ba 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index 5f0654ad1e..b8077ff8c1 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index 7a96b6dff1..ed342ab34b 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 6e1d402833..73e6cc4e7d 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl index 440ec7a71f..fab68de5c6 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK, 1, NotSerialized) { diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl index 501cffb566..c937af17a9 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c index 2b8c10087b..3851d04b22 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 2ab4c15802..150bdcf05a 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB diff --git a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c index 66f35dd136..70d055e8b2 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gpio.c b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c index 0fbb24b749..6ea47183ff 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/gpio.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c index 4813fa8cb4..0602fba4d3 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c index 68b60257bc..634270e6f9 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index f51a65ca35..7ebcb99a23 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index da11d010d3..3f0c21618a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 869b6c0ac6..675ceaa851 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 3bbd215f83..fc8fb72d95 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl index 7b9534437e..3c5d592ba6 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl index cc27e983e1..e46f267284 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { /* DBGO("\\_SI\\_SST\n") */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl index d5a1f683a8..c65979df55 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl index e1dc35d969..fb88faa56b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* USB overcurrent mapping pins. */ Name(UOM0, 0) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index be2669eeb8..3eb63c8920 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 09a7825cfe..3e2931af95 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index 7b47a7646a..79f4b3f402 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "mainboard.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c index 7864872b45..3ee0def029 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index bd1a671d50..42af1b8efa 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ec.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index e426b4d0e3..159f26cc98 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl b/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl index 86acea9715..b559de2e4f 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl +++ b/src/mainboard/hp/snb_ivb_laptops/acpi/ec.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl b/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl index f7f8066ecf..68a709e0db 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl +++ b/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK,1) { diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl b/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl index 606085fafe..1bc1628982 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl +++ b/src/mainboard/hp/snb_ivb_laptops/acpi/superio.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c index 831ec53c44..07bc6acbf5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c +++ b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 2ab4c15802..150bdcf05a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB diff --git a/src/mainboard/hp/snb_ivb_laptops/mainboard.c b/src/mainboard/hp/snb_ivb_laptops/mainboard.c index d1aad59d01..97c7e7a333 100644 --- a/src/mainboard/hp/snb_ivb_laptops/mainboard.c +++ b/src/mainboard/hp/snb_ivb_laptops/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c index ef66127101..59048cf123 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c index 971d2fd866..49ca2ab3cb 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c index 0aabe19967..3e329c7aac 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c index b43815ca87..0dab0e0af6 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c index b3a68a49c9..759c667641 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c index 9b32e23c12..1ecdecf829 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c index 7bf19875ca..5fa75ece20 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c index 2a9bb1f402..fd47cf0ee9 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c index e954689f9f..990d8baa89 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c index a89741610d..800e992173 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c index ea8b74983d..ab91d3a7d8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c index 83b14891f5..d8e1fb7a93 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c index 5e33cf1a8a..6b7bbb2312 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c index 8ed54a1419..2f88c94cea 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c index 3eb82daf5d..431b5032ca 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c index 1efdcde355..46ed03ffee 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c index 7e50750dc4..b2f470ac1c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c index c32ea606d6..6528299892 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c index 8b45b009cb..eb62a9f485 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c index 9cfab29848..163e0dc2e4 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c index f353184c97..2f1892e50e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl index 440ec7a71f..fab68de5c6 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl +++ b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK, 1, NotSerialized) { diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl index 501cffb566..c937af17a9 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl +++ b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c index 2b8c10087b..3851d04b22 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c +++ b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 2ab4c15802..150bdcf05a 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB diff --git a/src/mainboard/hp/z220_sff_workstation/early_init.c b/src/mainboard/hp/z220_sff_workstation/early_init.c index d21eed740f..71a2e952a1 100644 --- a/src/mainboard/hp/z220_sff_workstation/early_init.c +++ b/src/mainboard/hp/z220_sff_workstation/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/hp/z220_sff_workstation/gpio.c b/src/mainboard/hp/z220_sff_workstation/gpio.c index c79c285ca6..624226ec7a 100644 --- a/src/mainboard/hp/z220_sff_workstation/gpio.c +++ b/src/mainboard/hp/z220_sff_workstation/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/z220_sff_workstation/hda_verb.c index 40bc9e18b5..32a0f744c2 100644 --- a/src/mainboard/hp/z220_sff_workstation/hda_verb.c +++ b/src/mainboard/hp/z220_sff_workstation/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.c b/src/mainboard/hp/z220_sff_workstation/mainboard.c index 68b60257bc..634270e6f9 100644 --- a/src/mainboard/hp/z220_sff_workstation/mainboard.c +++ b/src/mainboard/hp/z220_sff_workstation/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include From 30a511cea6046b07580a3ab1faddd902654905cb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:09 +0200 Subject: [PATCH 0799/1463] mainboard/ibase: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic2989038a5f11981682443e77d8f639a3ef280f5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40081 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/ibase/mb899/acpi/ec.asl | 15 ++------------- src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/ibase/mb899/acpi/platform.asl | 15 ++------------- src/mainboard/ibase/mb899/acpi/superio.asl | 15 ++------------- src/mainboard/ibase/mb899/acpi_tables.c | 15 ++------------- src/mainboard/ibase/mb899/cstates.c | 14 ++------------ src/mainboard/ibase/mb899/dsdt.asl | 15 ++------------- src/mainboard/ibase/mb899/early_init.c | 15 ++------------- src/mainboard/ibase/mb899/gpio.c | 14 ++------------ src/mainboard/ibase/mb899/hda_verb.c | 14 ++------------ src/mainboard/ibase/mb899/irq_tables.c | 15 ++------------- src/mainboard/ibase/mb899/mainboard.c | 15 ++------------- src/mainboard/ibase/mb899/mptable.c | 15 ++------------- src/mainboard/ibase/mb899/superio_hwm.c | 15 ++------------- src/mainboard/ibase/mb899/superio_hwm.h | 15 ++------------- 15 files changed, 30 insertions(+), 192 deletions(-) diff --git a/src/mainboard/ibase/mb899/acpi/ec.asl b/src/mainboard/ibase/mb899/acpi/ec.asl index 0cd354a09b..35408a9bd5 100644 --- a/src/mainboard/ibase/mb899/acpi/ec.asl +++ b/src/mainboard/ibase/mb899/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC0) { diff --git a/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl b/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl index 953989bfa4..482f538c58 100644 --- a/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/ibase/mb899/acpi/platform.asl b/src/mainboard/ibase/mb899/acpi/platform.asl index 4b161bc565..64db274094 100644 --- a/src/mainboard/ibase/mb899/acpi/platform.asl +++ b/src/mainboard/ibase/mb899/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/ibase/mb899/acpi/superio.asl b/src/mainboard/ibase/mb899/acpi/superio.asl index b49fe477a9..3e9acd3404 100644 --- a/src/mainboard/ibase/mb899/acpi/superio.asl +++ b/src/mainboard/ibase/mb899/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (SIO1) diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index a1f5397852..4a4c02ccb4 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/ibase/mb899/cstates.c b/src/mainboard/ibase/mb899/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/ibase/mb899/cstates.c +++ b/src/mainboard/ibase/mb899/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index ead4771ca5..60b5949159 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index 10b8b33b32..e8537ede95 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/ibase/mb899/gpio.c b/src/mainboard/ibase/mb899/gpio.c index 44ac3b53a5..b5f6552a47 100644 --- a/src/mainboard/ibase/mb899/gpio.c +++ b/src/mainboard/ibase/mb899/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/ibase/mb899/hda_verb.c b/src/mainboard/ibase/mb899/hda_verb.c index 5d088790a5..0700c48e63 100644 --- a/src/mainboard/ibase/mb899/hda_verb.c +++ b/src/mainboard/ibase/mb899/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index d1aa86a57f..1db817d21e 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index ce00fa5400..3167862e6a 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 9a05fa4a50..39afafd008 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 6a2a875c23..aea9f7322d 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/ibase/mb899/superio_hwm.h b/src/mainboard/ibase/mb899/superio_hwm.h index 06b92301e4..deb5e9ed16 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.h +++ b/src/mainboard/ibase/mb899/superio_hwm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_HWM_H #define SUPERIO_HWM_H From a21dff67990ee4d2bbac9f05894336d74d1639db Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:24 +0200 Subject: [PATCH 0800/1463] mainboard/kontron: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5aeaaf267a187105f08f48a010323baa77e06989 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40084 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/kontron/986lcd-m/acpi/ec.asl | 15 ++------------- .../kontron/986lcd-m/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/kontron/986lcd-m/acpi/platform.asl | 15 ++------------- src/mainboard/kontron/986lcd-m/acpi/superio.asl | 15 ++------------- src/mainboard/kontron/986lcd-m/acpi_tables.c | 15 ++------------- src/mainboard/kontron/986lcd-m/cstates.c | 14 ++------------ src/mainboard/kontron/986lcd-m/dsdt.asl | 15 ++------------- src/mainboard/kontron/986lcd-m/early_init.c | 15 ++------------- src/mainboard/kontron/986lcd-m/gpio.c | 15 ++------------- src/mainboard/kontron/986lcd-m/hda_verb.c | 14 ++------------ src/mainboard/kontron/986lcd-m/irq_tables.c | 15 ++------------- src/mainboard/kontron/986lcd-m/mainboard.c | 15 ++------------- src/mainboard/kontron/986lcd-m/mptable.c | 15 ++------------- src/mainboard/kontron/ktqm77/acpi/ec.asl | 14 ++------------ src/mainboard/kontron/ktqm77/acpi/mainboard.asl | 16 ++-------------- src/mainboard/kontron/ktqm77/acpi/platform.asl | 15 ++------------- src/mainboard/kontron/ktqm77/acpi/superio.asl | 14 ++------------ src/mainboard/kontron/ktqm77/acpi/thermal.asl | 15 ++------------- src/mainboard/kontron/ktqm77/acpi_tables.c | 15 ++------------- src/mainboard/kontron/ktqm77/dsdt.asl | 15 ++------------- src/mainboard/kontron/ktqm77/early_init.c | 15 ++------------- src/mainboard/kontron/ktqm77/gpio.c | 15 ++------------- src/mainboard/kontron/ktqm77/hda_verb.c | 15 ++------------- src/mainboard/kontron/ktqm77/mainboard.c | 15 ++------------- src/mainboard/kontron/ktqm77/thermal.h | 15 ++------------- 25 files changed, 50 insertions(+), 322 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/acpi/ec.asl b/src/mainboard/kontron/986lcd-m/acpi/ec.asl index a4510d8de5..87992873be 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/ec.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC0) { diff --git a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl index 953989bfa4..482f538c58 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/kontron/986lcd-m/acpi/platform.asl b/src/mainboard/kontron/986lcd-m/acpi/platform.asl index 4b161bc565..64db274094 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/platform.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/kontron/986lcd-m/acpi/superio.asl b/src/mainboard/kontron/986lcd-m/acpi/superio.asl index b49fe477a9..3e9acd3404 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/superio.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (SIO1) diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index a1f5397852..4a4c02ccb4 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/kontron/986lcd-m/cstates.c b/src/mainboard/kontron/986lcd-m/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/kontron/986lcd-m/cstates.c +++ b/src/mainboard/kontron/986lcd-m/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 64ad9c77f1..1a8513120e 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 2e4ef822bb..08d7a3c73c 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/kontron/986lcd-m/gpio.c b/src/mainboard/kontron/986lcd-m/gpio.c index aa529a5819..e446fe6dad 100644 --- a/src/mainboard/kontron/986lcd-m/gpio.c +++ b/src/mainboard/kontron/986lcd-m/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/kontron/986lcd-m/hda_verb.c b/src/mainboard/kontron/986lcd-m/hda_verb.c index 5d088790a5..0700c48e63 100644 --- a/src/mainboard/kontron/986lcd-m/hda_verb.c +++ b/src/mainboard/kontron/986lcd-m/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index 979863c004..58f109a034 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index b072ba4b95..af1a5feb63 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 103dfbc81a..1068150d14 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/kontron/ktqm77/acpi/ec.asl b/src/mainboard/kontron/ktqm77/acpi/ec.asl index 2f8605700c..4ce9ba42c6 100644 --- a/src/mainboard/kontron/ktqm77/acpi/ec.asl +++ b/src/mainboard/kontron/ktqm77/acpi/ec.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define IT8516E_EC_DEV EC0 #define SUPERIO_PNP_BASE 0x20e diff --git a/src/mainboard/kontron/ktqm77/acpi/mainboard.asl b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl index 53ec05098a..eeb8fbfd9f 100644 --- a/src/mainboard/kontron/ktqm77/acpi/mainboard.asl +++ b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/kontron/ktqm77/acpi/platform.asl b/src/mainboard/kontron/ktqm77/acpi/platform.asl index b345b6d19f..f16eab85f2 100644 --- a/src/mainboard/kontron/ktqm77/acpi/platform.asl +++ b/src/mainboard/kontron/ktqm77/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/kontron/ktqm77/acpi/superio.asl b/src/mainboard/kontron/ktqm77/acpi/superio.asl index 4aa25b6289..936a0e7b9c 100644 --- a/src/mainboard/kontron/ktqm77/acpi/superio.asl +++ b/src/mainboard/kontron/ktqm77/acpi/superio.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/kontron/ktqm77/acpi/thermal.asl b/src/mainboard/kontron/ktqm77/acpi/thermal.asl index 7dfd7ab248..a65da97d77 100644 --- a/src/mainboard/kontron/ktqm77/acpi/thermal.asl +++ b/src/mainboard/kontron/ktqm77/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index 9ef2b66097..d0b68b5fdc 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "thermal.h" diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index d8071f5b74..298f30f782 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index c76acbf63e..565106495d 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/kontron/ktqm77/gpio.c b/src/mainboard/kontron/ktqm77/gpio.c index d64f8d8f13..d839803629 100644 --- a/src/mainboard/kontron/ktqm77/gpio.c +++ b/src/mainboard/kontron/ktqm77/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef KTQM77_GPIO_H #define KTQM77_GPIO_H diff --git a/src/mainboard/kontron/ktqm77/hda_verb.c b/src/mainboard/kontron/ktqm77/hda_verb.c index b485831875..4a0b8408d3 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.c +++ b/src/mainboard/kontron/ktqm77/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 6dffa4cda2..869220133b 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/kontron/ktqm77/thermal.h b/src/mainboard/kontron/ktqm77/thermal.h index a0235c7f18..f6f9c81d3f 100644 --- a/src/mainboard/kontron/ktqm77/thermal.h +++ b/src/mainboard/kontron/ktqm77/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef KTQM77_THERMAL_H #define KTQM77_THERMAL_H From 89ab2503c9ec1528e29f7671bd12ce4a03cedf67 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:28 +0200 Subject: [PATCH 0801/1463] mainboard/lenovo: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7b7670bb541cf4814fd4958d5c0d8c68cbee80c2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40085 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/g505s/BiosCallOuts.c | 15 ++------------- src/mainboard/lenovo/g505s/OemCustomize.c | 15 ++------------- src/mainboard/lenovo/g505s/OptionsIds.h | 15 ++------------- src/mainboard/lenovo/g505s/acpi/gpe.asl | 15 ++------------- src/mainboard/lenovo/g505s/acpi/mainboard.asl | 15 ++------------- src/mainboard/lenovo/g505s/acpi/routing.asl | 15 ++------------- src/mainboard/lenovo/g505s/acpi/si.asl | 15 ++------------- src/mainboard/lenovo/g505s/acpi/sleep.asl | 15 ++------------- src/mainboard/lenovo/g505s/acpi/usb_oc.asl | 15 ++------------- src/mainboard/lenovo/g505s/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/g505s/buildOpts.c | 15 ++------------- src/mainboard/lenovo/g505s/dsdt.asl | 15 ++------------- src/mainboard/lenovo/g505s/irq_tables.c | 15 ++------------- src/mainboard/lenovo/g505s/mainboard.c | 15 ++------------- src/mainboard/lenovo/g505s/mptable.c | 15 ++------------- src/mainboard/lenovo/l520/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/l520/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/l520/acpi/superio.asl | 16 ++-------------- src/mainboard/lenovo/l520/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/l520/dsdt.asl | 14 ++------------ src/mainboard/lenovo/l520/early_init.c | 16 ++-------------- src/mainboard/lenovo/l520/gpio.c | 16 ++-------------- src/mainboard/lenovo/l520/hda_verb.c | 16 ++-------------- src/mainboard/lenovo/l520/mainboard.c | 16 ++-------------- src/mainboard/lenovo/l520/smihandler.c | 16 ++-------------- src/mainboard/lenovo/s230u/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/s230u/acpi/gpe.asl | 16 ++-------------- src/mainboard/lenovo/s230u/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/s230u/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/s230u/dsdt.asl | 14 ++------------ src/mainboard/lenovo/s230u/early_init.c | 15 ++------------- src/mainboard/lenovo/s230u/ec.c | 15 ++------------- src/mainboard/lenovo/s230u/gpio.c | 15 ++------------- src/mainboard/lenovo/s230u/hda_verb.c | 15 ++------------- src/mainboard/lenovo/s230u/mainboard.c | 15 ++------------- src/mainboard/lenovo/s230u/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t400/acpi/dock.asl | 16 ++-------------- src/mainboard/lenovo/t400/acpi/gpe.asl | 16 ++-------------- src/mainboard/lenovo/t400/acpi/graphics.asl | 15 ++------------- src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl | 16 ++-------------- src/mainboard/lenovo/t400/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/t400/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/t400/blc.c | 15 ++------------- src/mainboard/lenovo/t400/bootblock.c | 15 ++------------- src/mainboard/lenovo/t400/cstates.c | 15 ++------------- src/mainboard/lenovo/t400/dock.c | 16 ++-------------- src/mainboard/lenovo/t400/dock.h | 15 ++------------- src/mainboard/lenovo/t400/dsdt.asl | 16 ++-------------- src/mainboard/lenovo/t400/fadt.c | 16 ++-------------- src/mainboard/lenovo/t400/hda_verb.c | 15 ++------------- src/mainboard/lenovo/t400/mainboard.c | 15 ++------------- src/mainboard/lenovo/t400/romstage.c | 16 ++-------------- src/mainboard/lenovo/t400/variants/r500/gpio.c | 14 ++------------ src/mainboard/lenovo/t400/variants/t400/gpio.c | 14 ++------------ src/mainboard/lenovo/t410/acpi/dock.asl | 16 ++-------------- src/mainboard/lenovo/t410/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/t410/acpi/gpe.asl | 16 ++-------------- src/mainboard/lenovo/t410/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/t410/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/t410/dock.c | 16 ++-------------- src/mainboard/lenovo/t410/dock.h | 15 ++------------- src/mainboard/lenovo/t410/dsdt.asl | 16 ++-------------- src/mainboard/lenovo/t410/early_init.c | 16 ++-------------- src/mainboard/lenovo/t410/gpio.c | 15 ++------------- src/mainboard/lenovo/t410/mainboard.c | 16 ++-------------- src/mainboard/lenovo/t410/romstage.c | 16 ++-------------- src/mainboard/lenovo/t410/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t420/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/t420/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/t420/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/t420/dsdt.asl | 15 ++------------- src/mainboard/lenovo/t420/early_init.c | 15 ++------------- src/mainboard/lenovo/t420/gpio.c | 14 ++------------ src/mainboard/lenovo/t420/hda_verb.c | 15 ++------------- src/mainboard/lenovo/t420/mainboard.c | 15 ++------------- src/mainboard/lenovo/t420/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t420s/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/t420s/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/t420s/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/t420s/dsdt.asl | 15 ++------------- src/mainboard/lenovo/t420s/early_init.c | 15 ++------------- src/mainboard/lenovo/t420s/gpio.c | 14 ++------------ src/mainboard/lenovo/t420s/hda_verb.c | 15 ++------------- src/mainboard/lenovo/t420s/mainboard.c | 15 ++------------- src/mainboard/lenovo/t420s/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t430/acpi/ec.asl | 15 ++------------- src/mainboard/lenovo/t430/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/t430/acpi/superio.asl | 15 ++------------- src/mainboard/lenovo/t430/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/t430/dsdt.asl | 15 ++------------- src/mainboard/lenovo/t430/early_init.c | 15 ++------------- src/mainboard/lenovo/t430/gpio.c | 15 ++------------- src/mainboard/lenovo/t430/hda_verb.c | 15 ++------------- src/mainboard/lenovo/t430/mainboard.c | 15 ++------------- src/mainboard/lenovo/t430/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t430s/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/t430s/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/t430s/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/t430s/dsdt.asl | 15 ++------------- src/mainboard/lenovo/t430s/mainboard.c | 15 ++------------- src/mainboard/lenovo/t430s/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t430s/variants/t430s/gpio.c | 14 ++------------ .../lenovo/t430s/variants/t430s/hda_verb.c | 15 ++------------- .../lenovo/t430s/variants/t430s/romstage.c | 15 ++------------- src/mainboard/lenovo/t430s/variants/t431s/gpio.c | 16 ++-------------- .../lenovo/t430s/variants/t431s/hda_verb.c | 16 ++-------------- .../lenovo/t430s/variants/t431s/romstage.c | 15 ++------------- src/mainboard/lenovo/t440p/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/t440p/gpio.c | 16 ++-------------- src/mainboard/lenovo/t440p/hda_verb.c | 16 ++-------------- src/mainboard/lenovo/t440p/romstage.c | 16 ++-------------- src/mainboard/lenovo/t440p/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t520/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/t520/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/t520/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/t520/dsdt.asl | 15 ++------------- src/mainboard/lenovo/t520/early_init.c | 15 ++------------- src/mainboard/lenovo/t520/hda_verb.c | 15 ++------------- src/mainboard/lenovo/t520/mainboard.c | 15 ++------------- src/mainboard/lenovo/t520/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t520/variants/t520/gpio.c | 15 ++------------- .../lenovo/t520/variants/t520/romstage.c | 15 ++------------- src/mainboard/lenovo/t520/variants/w520/gpio.c | 16 ++-------------- .../lenovo/t520/variants/w520/romstage.c | 15 ++------------- src/mainboard/lenovo/t530/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/t530/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/t530/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/t530/dsdt.asl | 15 ++------------- src/mainboard/lenovo/t530/early_init.c | 15 ++------------- src/mainboard/lenovo/t530/hda_verb.c | 15 ++------------- src/mainboard/lenovo/t530/mainboard.c | 15 ++------------- src/mainboard/lenovo/t530/smihandler.c | 16 ++-------------- src/mainboard/lenovo/t530/variants/t530/gpio.c | 14 ++------------ .../lenovo/t530/variants/t530/romstage.c | 15 ++------------- src/mainboard/lenovo/t530/variants/w530/gpio.c | 16 ++-------------- .../lenovo/t530/variants/w530/romstage.c | 15 ++------------- src/mainboard/lenovo/t60/acpi/dock.asl | 16 ++-------------- src/mainboard/lenovo/t60/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/t60/acpi/gpe.asl | 16 ++-------------- src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl | 16 ++-------------- src/mainboard/lenovo/t60/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/t60/acpi/video.asl | 16 ++-------------- src/mainboard/lenovo/t60/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/t60/dock.c | 16 ++-------------- src/mainboard/lenovo/t60/dock.h | 15 ++------------- src/mainboard/lenovo/t60/dsdt.asl | 16 ++-------------- src/mainboard/lenovo/t60/early_init.c | 16 ++-------------- src/mainboard/lenovo/t60/gpio.c | 15 ++------------- src/mainboard/lenovo/t60/hda_verb.c | 14 ++------------ src/mainboard/lenovo/t60/mainboard.c | 16 ++-------------- src/mainboard/lenovo/t60/mptable.c | 16 ++-------------- src/mainboard/lenovo/t60/smi.h | 15 ++------------- src/mainboard/lenovo/t60/smihandler.c | 16 ++-------------- .../thinkcentre_a58/acpi/ich7_pci_irqs.asl | 15 ++------------- .../lenovo/thinkcentre_a58/acpi/superio.asl | 14 ++------------ .../lenovo/thinkcentre_a58/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/thinkcentre_a58/cstates.c | 15 ++------------- src/mainboard/lenovo/thinkcentre_a58/dsdt.asl | 15 ++------------- src/mainboard/lenovo/thinkcentre_a58/gpio.c | 15 ++------------- src/mainboard/lenovo/x131e/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/x131e/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/x131e/acpi/superio.asl | 15 ++------------- src/mainboard/lenovo/x131e/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/x131e/dsdt.asl | 15 ++------------- src/mainboard/lenovo/x131e/early_init.c | 15 ++------------- src/mainboard/lenovo/x131e/gpio.c | 15 ++------------- src/mainboard/lenovo/x131e/hda_verb.c | 15 ++------------- src/mainboard/lenovo/x131e/mainboard.c | 15 ++------------- src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl | 16 ++-------------- .../lenovo/x1_carbon_gen1/acpi/platform.asl | 15 ++------------- .../lenovo/x1_carbon_gen1/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 15 ++------------- src/mainboard/lenovo/x1_carbon_gen1/early_init.c | 15 ++------------- src/mainboard/lenovo/x1_carbon_gen1/gpio.c | 15 ++------------- src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c | 15 ++------------- src/mainboard/lenovo/x1_carbon_gen1/mainboard.c | 15 ++------------- src/mainboard/lenovo/x1_carbon_gen1/smihandler.c | 16 ++-------------- src/mainboard/lenovo/x200/acpi/dock.asl | 16 ++-------------- src/mainboard/lenovo/x200/acpi/gpe.asl | 16 ++-------------- src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl | 16 ++-------------- src/mainboard/lenovo/x200/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/x200/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/x200/blc.c | 15 ++------------- src/mainboard/lenovo/x200/cstates.c | 15 ++------------- src/mainboard/lenovo/x200/dock.h | 15 ++------------- src/mainboard/lenovo/x200/dsdt.asl | 16 ++-------------- src/mainboard/lenovo/x200/fadt.c | 16 ++-------------- src/mainboard/lenovo/x200/hda_verb.c | 15 ++------------- src/mainboard/lenovo/x200/mainboard.c | 15 ++------------- src/mainboard/lenovo/x200/romstage.c | 16 ++-------------- src/mainboard/lenovo/x200/variants/x200/dock.c | 16 ++-------------- src/mainboard/lenovo/x200/variants/x200/gpio.c | 14 ++------------ src/mainboard/lenovo/x200/variants/x301/gpio.c | 14 ++------------ src/mainboard/lenovo/x201/acpi/dock.asl | 16 ++-------------- src/mainboard/lenovo/x201/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/x201/acpi/gpe.asl | 16 ++-------------- src/mainboard/lenovo/x201/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/x201/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/x201/dock.c | 16 ++-------------- src/mainboard/lenovo/x201/dock.h | 15 ++------------- src/mainboard/lenovo/x201/dsdt.asl | 16 ++-------------- src/mainboard/lenovo/x201/early_init.c | 16 ++-------------- src/mainboard/lenovo/x201/gpio.c | 15 ++------------- src/mainboard/lenovo/x201/mainboard.c | 16 ++-------------- src/mainboard/lenovo/x201/romstage.c | 16 ++-------------- src/mainboard/lenovo/x201/smihandler.c | 16 ++-------------- src/mainboard/lenovo/x220/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/x220/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/x220/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/x220/dsdt.asl | 15 ++------------- src/mainboard/lenovo/x220/early_init.c | 15 ++------------- src/mainboard/lenovo/x220/hda_verb.c | 15 ++------------- src/mainboard/lenovo/x220/mainboard.c | 15 ++------------- src/mainboard/lenovo/x220/smihandler.c | 16 ++-------------- src/mainboard/lenovo/x220/variants/x1/gpio.c | 16 ++-------------- src/mainboard/lenovo/x220/variants/x1/romstage.c | 15 ++------------- src/mainboard/lenovo/x220/variants/x220/gpio.c | 14 ++------------ .../lenovo/x220/variants/x220/romstage.c | 15 ++------------- src/mainboard/lenovo/x230/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/x230/acpi/platform.asl | 15 ++------------- src/mainboard/lenovo/x230/acpi_tables.c | 15 ++------------- src/mainboard/lenovo/x230/dsdt.asl | 15 ++------------- src/mainboard/lenovo/x230/early_init.c | 15 ++------------- src/mainboard/lenovo/x230/gpio.c | 15 ++------------- src/mainboard/lenovo/x230/hda_verb.c | 15 ++------------- src/mainboard/lenovo/x230/mainboard.c | 15 ++------------- src/mainboard/lenovo/x230/smihandler.c | 16 ++-------------- src/mainboard/lenovo/x60/acpi/dock.asl | 16 ++-------------- src/mainboard/lenovo/x60/acpi/ec.asl | 16 ++-------------- src/mainboard/lenovo/x60/acpi/gpe.asl | 16 ++-------------- src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl | 16 ++-------------- src/mainboard/lenovo/x60/acpi/platform.asl | 16 ++-------------- src/mainboard/lenovo/x60/acpi_tables.c | 16 ++-------------- src/mainboard/lenovo/x60/dock.c | 16 ++-------------- src/mainboard/lenovo/x60/dock.h | 15 ++------------- src/mainboard/lenovo/x60/dsdt.asl | 16 ++-------------- src/mainboard/lenovo/x60/early_init.c | 16 ++-------------- src/mainboard/lenovo/x60/gpio.c | 15 ++------------- src/mainboard/lenovo/x60/hda_verb.c | 14 ++------------ src/mainboard/lenovo/x60/irq_tables.c | 16 ++-------------- src/mainboard/lenovo/x60/mainboard.c | 16 ++-------------- src/mainboard/lenovo/x60/mptable.c | 16 ++-------------- src/mainboard/lenovo/x60/smi.h | 15 ++------------- src/mainboard/lenovo/x60/smihandler.c | 16 ++-------------- 244 files changed, 488 insertions(+), 3265 deletions(-) diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index f51a65ca35..7ebcb99a23 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 7cf1ab8eac..94bde9e0b6 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/g505s/OptionsIds.h b/src/mainboard/lenovo/g505s/OptionsIds.h index bc9ab3221c..a2fa5c1912 100644 --- a/src/mainboard/lenovo/g505s/OptionsIds.h +++ b/src/mainboard/lenovo/g505s/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index b986afd065..56c0b6cf80 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl index 3bbd215f83..fc8fb72d95 100644 --- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl +++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index 7b9534437e..3c5d592ba6 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/lenovo/g505s/acpi/si.asl b/src/mainboard/lenovo/g505s/acpi/si.asl index cc27e983e1..e46f267284 100644 --- a/src/mainboard/lenovo/g505s/acpi/si.asl +++ b/src/mainboard/lenovo/g505s/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { /* DBGO("\\_SI\\_SST\n") */ diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl index d5a1f683a8..c65979df55 100644 --- a/src/mainboard/lenovo/g505s/acpi/sleep.asl +++ b/src/mainboard/lenovo/g505s/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl index 1f1419d526..c2e4390e61 100644 --- a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl +++ b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* USB overcurrent mapping pins. */ Name(UOM0, 0) diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c index be2669eeb8..3eb63c8920 100644 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ b/src/mainboard/lenovo/g505s/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 1c8e1e6d66..6e5543db56 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index 4eb466f819..bb700e0de1 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "mainboard.h" diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c index 7864872b45..3ee0def029 100644 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ b/src/mainboard/lenovo/g505s/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index b7effa2bcb..c8ce7fdc53 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ec.h" diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index 421253e3b6..034c6208a4 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/l520/acpi/ec.asl b/src/mainboard/lenovo/l520/acpi/ec.asl index 45bafff30d..2477a1022e 100644 --- a/src/mainboard/lenovo/l520/acpi/ec.asl +++ b/src/mainboard/lenovo/l520/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index d63f75aaa8..70cb97ecea 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK,1) { diff --git a/src/mainboard/lenovo/l520/acpi/superio.asl b/src/mainboard/lenovo/l520/acpi/superio.asl index 03ab48a04c..1bc1628982 100644 --- a/src/mainboard/lenovo/l520/acpi/superio.asl +++ b/src/mainboard/lenovo/l520/acpi/superio.asl @@ -1,16 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index 2081a80998..8dcc3a87ff 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index 08b38d2f3a..0ab2c2f7c2 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 22 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c index fdbfa0976c..9d81968c55 100644 --- a/src/mainboard/lenovo/l520/early_init.c +++ b/src/mainboard/lenovo/l520/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/l520/gpio.c b/src/mainboard/lenovo/l520/gpio.c index d5328fbd33..2adc3d9ecf 100644 --- a/src/mainboard/lenovo/l520/gpio.c +++ b/src/mainboard/lenovo/l520/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c index 4f741eec10..0201df364e 100644 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index b2cb5521ff..08901519a4 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c index e15a06bb37..303648a3f7 100644 --- a/src/mainboard/lenovo/l520/smihandler.c +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 87adcb2cc1..c626350ab8 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EC0) { diff --git a/src/mainboard/lenovo/s230u/acpi/gpe.asl b/src/mainboard/lenovo/s230u/acpi/gpe.asl index 747a2aec37..d1ae653e50 100644 --- a/src/mainboard/lenovo/s230u/acpi/gpe.asl +++ b/src/mainboard/lenovo/s230u/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (_GPE) { diff --git a/src/mainboard/lenovo/s230u/acpi/platform.asl b/src/mainboard/lenovo/s230u/acpi/platform.asl index e5008952dc..b714e9c479 100644 --- a/src/mainboard/lenovo/s230u/acpi/platform.asl +++ b/src/mainboard/lenovo/s230u/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK,1) { diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index 01bb91f376..2b9357e818 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 23 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index d3c7a8f51f..3c2b83be3e 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/s230u/ec.c b/src/mainboard/lenovo/s230u/ec.c index dd59cc31d9..593e1cb40f 100644 --- a/src/mainboard/lenovo/s230u/ec.c +++ b/src/mainboard/lenovo/s230u/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ec.h" #include diff --git a/src/mainboard/lenovo/s230u/gpio.c b/src/mainboard/lenovo/s230u/gpio.c index 9cf64e263c..117112ed94 100644 --- a/src/mainboard/lenovo/s230u/gpio.c +++ b/src/mainboard/lenovo/s230u/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c index 15bedc85ae..c36a4cd96f 100644 --- a/src/mainboard/lenovo/s230u/hda_verb.c +++ b/src/mainboard/lenovo/s230u/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c index 42bddf749a..94d192d3e1 100644 --- a/src/mainboard/lenovo/s230u/mainboard.c +++ b/src/mainboard/lenovo/s230u/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c index 58683d6aca..ec1d83efba 100644 --- a/src/mainboard/lenovo/s230u/smihandler.c +++ b/src/mainboard/lenovo/s230u/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t400/acpi/dock.asl b/src/mainboard/lenovo/t400/acpi/dock.asl index 40add6d703..99e171d1af 100644 --- a/src/mainboard/lenovo/t400/acpi/dock.asl +++ b/src/mainboard/lenovo/t400/acpi/dock.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/lenovo/t400/acpi/gpe.asl b/src/mainboard/lenovo/t400/acpi/gpe.asl index a32dacdb85..7f16433948 100644 --- a/src/mainboard/lenovo/t400/acpi/gpe.asl +++ b/src/mainboard/lenovo/t400/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl index 8901bbf93d..5a8361d25a 100644 --- a/src/mainboard/lenovo/t400/acpi/graphics.asl +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* WARNING * Switchable graphics not yet tested! diff --git a/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl index ecc805abcf..be9ecd0820 100644 --- a/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl +++ b/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH9 diff --git a/src/mainboard/lenovo/t400/acpi/platform.asl b/src/mainboard/lenovo/t400/acpi/platform.asl index eca012be8e..2247461874 100644 --- a/src/mainboard/lenovo/t400/acpi/platform.asl +++ b/src/mainboard/lenovo/t400/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 66accb94ce..653365ab2b 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t400/blc.c b/src/mainboard/lenovo/t400/blc.c index b42eee01b8..7f490c1ada 100644 --- a/src/mainboard/lenovo/t400/blc.c +++ b/src/mainboard/lenovo/t400/blc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t400/bootblock.c b/src/mainboard/lenovo/t400/bootblock.c index c9f3cf6b5b..542061b73d 100644 --- a/src/mainboard/lenovo/t400/bootblock.c +++ b/src/mainboard/lenovo/t400/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c index d6143d11b6..81fb3d59ce 100644 --- a/src/mainboard/lenovo/t400/cstates.c +++ b/src/mainboard/lenovo/t400/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 3236117830..2bed449475 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ #include diff --git a/src/mainboard/lenovo/t400/dock.h b/src/mainboard/lenovo/t400/dock.h index cec94e7271..d39303a36e 100644 --- a/src/mainboard/lenovo/t400/dock.h +++ b/src/mainboard/lenovo/t400/dock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THINKPAD_T400_DOCK_H #define THINKPAD_T400_DOCK_H diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 6ea787b7f4..001e91ece2 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index c3c9015ab6..3aeb8bc5c0 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t400/hda_verb.c b/src/mainboard/lenovo/t400/hda_verb.c index 3c42b3c47d..66bdced4f2 100644 --- a/src/mainboard/lenovo/t400/hda_verb.c +++ b/src/mainboard/lenovo/t400/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t400/mainboard.c b/src/mainboard/lenovo/t400/mainboard.c index 26bb537938..d3e2063708 100644 --- a/src/mainboard/lenovo/t400/mainboard.c +++ b/src/mainboard/lenovo/t400/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 75adc5bb52..190b59414c 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t400/variants/r500/gpio.c b/src/mainboard/lenovo/t400/variants/r500/gpio.c index a1cc4586da..a812c415df 100644 --- a/src/mainboard/lenovo/t400/variants/r500/gpio.c +++ b/src/mainboard/lenovo/t400/variants/r500/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t400/variants/t400/gpio.c b/src/mainboard/lenovo/t400/variants/t400/gpio.c index ef340f28bf..1847d7f1e5 100644 --- a/src/mainboard/lenovo/t400/variants/t400/gpio.c +++ b/src/mainboard/lenovo/t400/variants/t400/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t410/acpi/dock.asl b/src/mainboard/lenovo/t410/acpi/dock.asl index d38f03c03c..eafb4236e0 100644 --- a/src/mainboard/lenovo/t410/acpi/dock.asl +++ b/src/mainboard/lenovo/t410/acpi/dock.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/lenovo/t410/acpi/ec.asl b/src/mainboard/lenovo/t410/acpi/ec.asl index 5ca4034f2b..81331d46fc 100644 --- a/src/mainboard/lenovo/t410/acpi/ec.asl +++ b/src/mainboard/lenovo/t410/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t410/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl index a32dacdb85..7f16433948 100644 --- a/src/mainboard/lenovo/t410/acpi/gpe.asl +++ b/src/mainboard/lenovo/t410/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/lenovo/t410/acpi/platform.asl b/src/mainboard/lenovo/t410/acpi/platform.asl index a5c80f2e39..a5c3964499 100644 --- a/src/mainboard/lenovo/t410/acpi/platform.asl +++ b/src/mainboard/lenovo/t410/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c index 3794345dc5..e63f226a41 100644 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c index 8e32b6a758..f06cefe102 100644 --- a/src/mainboard/lenovo/t410/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t410/dock.h b/src/mainboard/lenovo/t410/dock.h index af368b3ddd..b793953a93 100644 --- a/src/mainboard/lenovo/t410/dock.h +++ b/src/mainboard/lenovo/t410/dock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THINKPAD_X201_DOCK_H #define THINKPAD_X201_DOCK_H diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index f3592cac2e..c49c31b2ad 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t410/early_init.c b/src/mainboard/lenovo/t410/early_init.c index 6a6b2e8521..ade98f1aaa 100644 --- a/src/mainboard/lenovo/t410/early_init.c +++ b/src/mainboard/lenovo/t410/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/gpio.c index f5e9a04aad..0af4d4f1df 100644 --- a/src/mainboard/lenovo/t410/gpio.c +++ b/src/mainboard/lenovo/t410/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index cc4eb38d33..63bfaf272f 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 7b87c31d3d..73947cfc91 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index 5ff6125f1e..a106f86ed6 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t420/acpi/ec.asl b/src/mainboard/lenovo/t420/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/t420/acpi/ec.asl +++ b/src/mainboard/lenovo/t420/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/t420/acpi/platform.asl +++ b/src/mainboard/lenovo/t420/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/t420/acpi_tables.c +++ b/src/mainboard/lenovo/t420/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index 7130c6a3ff..a03b252ef5 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 1d267d1db7..6c189f4633 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t420/gpio.c b/src/mainboard/lenovo/t420/gpio.c index 75cb458ae2..5fc8071b55 100644 --- a/src/mainboard/lenovo/t420/gpio.c +++ b/src/mainboard/lenovo/t420/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 62b2eab41d..690c93606d 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index d4be588542..08901519a4 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c index a87e9089fd..443299573a 100644 --- a/src/mainboard/lenovo/t420/smihandler.c +++ b/src/mainboard/lenovo/t420/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/t420s/acpi/ec.asl +++ b/src/mainboard/lenovo/t420s/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ b/src/mainboard/lenovo/t420s/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index 7130c6a3ff..a03b252ef5 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 6c19a5ef4f..212be38fec 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420s/gpio.c index 3058f1a21f..0b64efe268 100644 --- a/src/mainboard/lenovo/t420s/gpio.c +++ b/src/mainboard/lenovo/t420s/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420s/hda_verb.c index c3ac350f0c..991e7e4d9e 100644 --- a/src/mainboard/lenovo/t420s/hda_verb.c +++ b/src/mainboard/lenovo/t420s/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index d4be588542..08901519a4 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index f0ecb0ba1e..84b9c3a732 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl index 2fd8472cdf..515143af04 100644 --- a/src/mainboard/lenovo/t430/acpi/ec.asl +++ b/src/mainboard/lenovo/t430/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl index d7adb54b47..e9d9e6c362 100644 --- a/src/mainboard/lenovo/t430/acpi/platform.asl +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_WAK,1) { diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl index 606085fafe..1bc1628982 100644 --- a/src/mainboard/lenovo/t430/acpi/superio.asl +++ b/src/mainboard/lenovo/t430/acpi/superio.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index 8c10384915..483d81ee32 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 8f68174840..583f9f3b8c 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 5e4c6ac2be..f85a821a08 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c index c266330351..f3131df45d 100644 --- a/src/mainboard/lenovo/t430/gpio.c +++ b/src/mainboard/lenovo/t430/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c index 874e26c47b..e45cf12a8d 100644 --- a/src/mainboard/lenovo/t430/hda_verb.c +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index d4be588542..08901519a4 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c index b3d5ea3676..a402bba935 100644 --- a/src/mainboard/lenovo/t430/smihandler.c +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430s/acpi/ec.asl b/src/mainboard/lenovo/t430s/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/t430s/acpi/ec.asl +++ b/src/mainboard/lenovo/t430s/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/t430s/acpi/platform.asl +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index 7130c6a3ff..a03b252ef5 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index d4be588542..08901519a4 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index a51eddc0e2..c274527bd0 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430s/variants/t430s/gpio.c b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c index 9adc481d62..9fe0bf14d0 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/gpio.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c index ba97d987da..950004d800 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index d939072251..a8c9aa7b6f 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t430s/variants/t431s/gpio.c b/src/mainboard/lenovo/t430s/variants/t431s/gpio.c index f4d147bdcc..863d59f133 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/gpio.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c index 2782d729e7..1a0a78d4fa 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index e3679a46ad..b6be4f239d 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c index 445d4b57a7..06d1dfb453 100644 --- a/src/mainboard/lenovo/t440p/acpi_tables.c +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t440p/gpio.c b/src/mainboard/lenovo/t440p/gpio.c index 36443df7b4..bc02afd1df 100644 --- a/src/mainboard/lenovo/t440p/gpio.c +++ b/src/mainboard/lenovo/t440p/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c index d1843456e2..fb59070e56 100644 --- a/src/mainboard/lenovo/t440p/hda_verb.c +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 1e4f17a797..240aae2392 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index f5dd8a3cec..aae16a3dda 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t520/acpi/ec.asl b/src/mainboard/lenovo/t520/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/t520/acpi/ec.asl +++ b/src/mainboard/lenovo/t520/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 7130c6a3ff..a03b252ef5 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index 22dcb25348..c49a297e7e 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t520/hda_verb.c b/src/mainboard/lenovo/t520/hda_verb.c index e141fde3da..67e3bf5ce4 100644 --- a/src/mainboard/lenovo/t520/hda_verb.c +++ b/src/mainboard/lenovo/t520/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 38ef280bf4..3a1d5b62a1 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index a51eddc0e2..c274527bd0 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t520/variants/t520/gpio.c b/src/mainboard/lenovo/t520/variants/t520/gpio.c index 6b329c69e9..318f84442d 100644 --- a/src/mainboard/lenovo/t520/variants/t520/gpio.c +++ b/src/mainboard/lenovo/t520/variants/t520/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t520/variants/t520/romstage.c b/src/mainboard/lenovo/t520/variants/t520/romstage.c index a77445502a..3e745b88d6 100644 --- a/src/mainboard/lenovo/t520/variants/t520/romstage.c +++ b/src/mainboard/lenovo/t520/variants/t520/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t520/variants/w520/gpio.c b/src/mainboard/lenovo/t520/variants/w520/gpio.c index 2f9c9957f9..334b664035 100644 --- a/src/mainboard/lenovo/t520/variants/w520/gpio.c +++ b/src/mainboard/lenovo/t520/variants/w520/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t520/variants/w520/romstage.c b/src/mainboard/lenovo/t520/variants/w520/romstage.c index 5c37237df0..da8c811548 100644 --- a/src/mainboard/lenovo/t520/variants/w520/romstage.c +++ b/src/mainboard/lenovo/t520/variants/w520/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t530/acpi/ec.asl b/src/mainboard/lenovo/t530/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/t530/acpi/ec.asl +++ b/src/mainboard/lenovo/t530/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 7130c6a3ff..a03b252ef5 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c index 76a5deb5ef..4cacd1040f 100644 --- a/src/mainboard/lenovo/t530/early_init.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index a6b3e6a9ee..5fa4625dd0 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index d6a8ed788c..908a109871 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index a51eddc0e2..c274527bd0 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t530/variants/t530/gpio.c b/src/mainboard/lenovo/t530/variants/t530/gpio.c index cbae7f0d36..778a02a8f6 100644 --- a/src/mainboard/lenovo/t530/variants/t530/gpio.c +++ b/src/mainboard/lenovo/t530/variants/t530/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c index dfe0085eb3..a062b913df 100644 --- a/src/mainboard/lenovo/t530/variants/t530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t530/variants/w530/gpio.c b/src/mainboard/lenovo/t530/variants/w530/gpio.c index 4ed4a528c9..0de022d225 100644 --- a/src/mainboard/lenovo/t530/variants/w530/gpio.c +++ b/src/mainboard/lenovo/t530/variants/w530/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c index 7520bc3b1a..a01ad562ed 100644 --- a/src/mainboard/lenovo/t530/variants/w530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t60/acpi/dock.asl b/src/mainboard/lenovo/t60/acpi/dock.asl index 7801a04ce9..644e93fe40 100644 --- a/src/mainboard/lenovo/t60/acpi/dock.asl +++ b/src/mainboard/lenovo/t60/acpi/dock.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "smi.h" diff --git a/src/mainboard/lenovo/t60/acpi/ec.asl b/src/mainboard/lenovo/t60/acpi/ec.asl index 579f77460f..92bbbec2e0 100644 --- a/src/mainboard/lenovo/t60/acpi/ec.asl +++ b/src/mainboard/lenovo/t60/acpi/ec.asl @@ -1,16 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t60/acpi/gpe.asl b/src/mainboard/lenovo/t60/acpi/gpe.asl index a32dacdb85..7f16433948 100644 --- a/src/mainboard/lenovo/t60/acpi/gpe.asl +++ b/src/mainboard/lenovo/t60/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl index 38cf00dcd3..fe5b1ae329 100644 --- a/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl index bbbc2ff05a..5f6cf0fce6 100644 --- a/src/mainboard/lenovo/t60/acpi/platform.asl +++ b/src/mainboard/lenovo/t60/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl index 62d7132744..294ea2e13b 100644 --- a/src/mainboard/lenovo/t60/acpi/video.asl +++ b/src/mainboard/lenovo/t60/acpi/video.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "smi.h" diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 4bb6b50b56..bb5d03dc65 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 080a9c84ab..e5f0c50739 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h index 219f673fff..7522b32a17 100644 --- a/src/mainboard/lenovo/t60/dock.h +++ b/src/mainboard/lenovo/t60/dock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THINKPAD_X60_DOCK_H #define THINKPAD_X60_DOCK_H diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index e7a7e50c15..51ff3361b2 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \BRTU diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c index 23502c3091..dba4c4cccd 100644 --- a/src/mainboard/lenovo/t60/early_init.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t60/gpio.c b/src/mainboard/lenovo/t60/gpio.c index a316e4eb5e..94a3548207 100644 --- a/src/mainboard/lenovo/t60/gpio.c +++ b/src/mainboard/lenovo/t60/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c index f73e473dfc..28a2b5d828 100644 --- a/src/mainboard/lenovo/t60/hda_verb.c +++ b/src/mainboard/lenovo/t60/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 9a09c7d39f..aba0a9bfe8 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 4f5166393b..6cb76ac308 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/t60/smi.h b/src/mainboard/lenovo/t60/smi.h index a4cb73d3b4..cb0e4d30f7 100644 --- a/src/mainboard/lenovo/t60/smi.h +++ b/src/mainboard/lenovo/t60/smi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_LENOVO_X60_SMI_H #define MAINBOARD_LENOVO_X60_SMI_H diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index c84712fd0b..cb25590f14 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl index 31744e4636..e034437d83 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is board specific information: diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl index 8902579b42..0dbc843196 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c index b0370c1ef4..7f47b3a7e2 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/thinkcentre_a58/cstates.c b/src/mainboard/lenovo/thinkcentre_a58/cstates.c index 2a6d8ad816..10498e1150 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cstates.c +++ b/src/mainboard/lenovo/thinkcentre_a58/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index 6120949269..8880ba7076 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/lenovo/thinkcentre_a58/gpio.c b/src/mainboard/lenovo/thinkcentre_a58/gpio.c index 758198f37c..96c023dcf7 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/gpio.c +++ b/src/mainboard/lenovo/thinkcentre_a58/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x131e/acpi/ec.asl b/src/mainboard/lenovo/x131e/acpi/ec.asl index 579f77460f..92bbbec2e0 100644 --- a/src/mainboard/lenovo/x131e/acpi/ec.asl +++ b/src/mainboard/lenovo/x131e/acpi/ec.asl @@ -1,16 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/x131e/acpi/platform.asl +++ b/src/mainboard/lenovo/x131e/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/x131e/acpi/superio.asl b/src/mainboard/lenovo/x131e/acpi/superio.asl index 606085fafe..1bc1628982 100644 --- a/src/mainboard/lenovo/x131e/acpi/superio.asl +++ b/src/mainboard/lenovo/x131e/acpi/superio.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/x131e/acpi_tables.c +++ b/src/mainboard/lenovo/x131e/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 4aa74c5d2c..1c237fef40 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 22 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c index 8cbcf29b94..ade92aaf26 100644 --- a/src/mainboard/lenovo/x131e/early_init.c +++ b/src/mainboard/lenovo/x131e/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x131e/gpio.c b/src/mainboard/lenovo/x131e/gpio.c index 47aad82e14..78ec1036e6 100644 --- a/src/mainboard/lenovo/x131e/gpio.c +++ b/src/mainboard/lenovo/x131e/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x131e/hda_verb.c b/src/mainboard/lenovo/x131e/hda_verb.c index 3ff0fa4784..2bbccde2b7 100644 --- a/src/mainboard/lenovo/x131e/hda_verb.c +++ b/src/mainboard/lenovo/x131e/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index d4be588542..08901519a4 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 862c869a3a..ce856126cd 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 52c317c30e..39051cd8e3 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c index cc2011bb9c..b0e5887162 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c index b2de7b1ea8..c524f5e7a9 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index d4be588542..08901519a4 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c index b3d5ea3676..a402bba935 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x200/acpi/dock.asl b/src/mainboard/lenovo/x200/acpi/dock.asl index 1edead0af2..ad752db384 100644 --- a/src/mainboard/lenovo/x200/acpi/dock.asl +++ b/src/mainboard/lenovo/x200/acpi/dock.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/lenovo/x200/acpi/gpe.asl b/src/mainboard/lenovo/x200/acpi/gpe.asl index a32dacdb85..7f16433948 100644 --- a/src/mainboard/lenovo/x200/acpi/gpe.asl +++ b/src/mainboard/lenovo/x200/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl index ecc805abcf..be9ecd0820 100644 --- a/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl +++ b/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH9 diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index eca012be8e..2247461874 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 66accb94ce..653365ab2b 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x200/blc.c b/src/mainboard/lenovo/x200/blc.c index cdd39a11b5..016838247f 100644 --- a/src/mainboard/lenovo/x200/blc.c +++ b/src/mainboard/lenovo/x200/blc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c index d6143d11b6..81fb3d59ce 100644 --- a/src/mainboard/lenovo/x200/cstates.c +++ b/src/mainboard/lenovo/x200/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x200/dock.h b/src/mainboard/lenovo/x200/dock.h index c68d4c23bb..614957b6ac 100644 --- a/src/mainboard/lenovo/x200/dock.h +++ b/src/mainboard/lenovo/x200/dock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THINKPAD_X200_DOCK_H #define THINKPAD_X200_DOCK_H diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index e97d47e223..1357a3a9ea 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index c3c9015ab6..3aeb8bc5c0 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x200/hda_verb.c b/src/mainboard/lenovo/x200/hda_verb.c index 001e436f25..169230f5d5 100644 --- a/src/mainboard/lenovo/x200/hda_verb.c +++ b/src/mainboard/lenovo/x200/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 3406689f0c..f3ef0ec59e 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index f90f04b4ff..c44f2c07c2 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x200/variants/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c index d51afec7a6..c9257c7ed2 100644 --- a/src/mainboard/lenovo/x200/variants/x200/dock.c +++ b/src/mainboard/lenovo/x200/variants/x200/dock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x200/variants/x200/gpio.c b/src/mainboard/lenovo/x200/variants/x200/gpio.c index 516a3ae69b..b306ed1143 100644 --- a/src/mainboard/lenovo/x200/variants/x200/gpio.c +++ b/src/mainboard/lenovo/x200/variants/x200/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x200/variants/x301/gpio.c b/src/mainboard/lenovo/x200/variants/x301/gpio.c index 10ad18a855..af580ae409 100644 --- a/src/mainboard/lenovo/x200/variants/x301/gpio.c +++ b/src/mainboard/lenovo/x200/variants/x301/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl index 35e62dfbc0..2badb253a7 100644 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ b/src/mainboard/lenovo/x201/acpi/dock.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl index 6085f18463..4d19b93aa5 100644 --- a/src/mainboard/lenovo/x201/acpi/ec.asl +++ b/src/mainboard/lenovo/x201/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index a32dacdb85..7f16433948 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 4694d9c43e..2f3b215341 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 3794345dc5..e63f226a41 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index d5f122e5e0..a6f6f7c224 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h index af368b3ddd..b793953a93 100644 --- a/src/mainboard/lenovo/x201/dock.h +++ b/src/mainboard/lenovo/x201/dock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THINKPAD_X201_DOCK_H #define THINKPAD_X201_DOCK_H diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index f3592cac2e..c49c31b2ad 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/x201/early_init.c b/src/mainboard/lenovo/x201/early_init.c index 6a6b2e8521..ade98f1aaa 100644 --- a/src/mainboard/lenovo/x201/early_init.c +++ b/src/mainboard/lenovo/x201/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/x201/gpio.c index fd370d8a62..c21d03e950 100644 --- a/src/mainboard/lenovo/x201/gpio.c +++ b/src/mainboard/lenovo/x201/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index dbbb75539e..b29302de0f 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 4b4177a699..16a6487a15 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 5ff6125f1e..a106f86ed6 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x220/acpi/ec.asl b/src/mainboard/lenovo/x220/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/x220/acpi/ec.asl +++ b/src/mainboard/lenovo/x220/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 7130c6a3ff..a03b252ef5 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 9750b8a6bf..4efe15a03f 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x220/hda_verb.c b/src/mainboard/lenovo/x220/hda_verb.c index 8b32616043..f19956743f 100644 --- a/src/mainboard/lenovo/x220/hda_verb.c +++ b/src/mainboard/lenovo/x220/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index d6a8ed788c..908a109871 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index a51eddc0e2..c274527bd0 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x220/variants/x1/gpio.c b/src/mainboard/lenovo/x220/variants/x1/gpio.c index cd68e8c5cf..c1cff882dd 100644 --- a/src/mainboard/lenovo/x220/variants/x1/gpio.c +++ b/src/mainboard/lenovo/x220/variants/x1/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x220/variants/x1/romstage.c b/src/mainboard/lenovo/x220/variants/x1/romstage.c index 41757b26b7..b935458ae2 100644 --- a/src/mainboard/lenovo/x220/variants/x1/romstage.c +++ b/src/mainboard/lenovo/x220/variants/x1/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x220/variants/x220/gpio.c b/src/mainboard/lenovo/x220/variants/x220/gpio.c index b1499d1f83..7416f4db74 100644 --- a/src/mainboard/lenovo/x220/variants/x220/gpio.c +++ b/src/mainboard/lenovo/x220/variants/x220/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/lenovo/x220/variants/x220/romstage.c b/src/mainboard/lenovo/x220/variants/x220/romstage.c index 2b68275ed6..3d7a410feb 100644 --- a/src/mainboard/lenovo/x220/variants/x220/romstage.c +++ b/src/mainboard/lenovo/x220/variants/x220/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x230/acpi/ec.asl b/src/mainboard/lenovo/x230/acpi/ec.asl index 825ff7a6af..2dda5ec4cb 100644 --- a/src/mainboard/lenovo/x230/acpi/ec.asl +++ b/src/mainboard/lenovo/x230/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index f3b0e1ad28..dc46182a33 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index c828ea1bec..65c601972d 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 7130c6a3ff..a03b252ef5 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c index 30e5846579..4e95a72a67 100644 --- a/src/mainboard/lenovo/x230/early_init.c +++ b/src/mainboard/lenovo/x230/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x230/gpio.c b/src/mainboard/lenovo/x230/gpio.c index 47cd5ffc05..05037f73de 100644 --- a/src/mainboard/lenovo/x230/gpio.c +++ b/src/mainboard/lenovo/x230/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index e3faeef4c2..64daa7173b 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index d6a8ed788c..908a109871 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index b3d5ea3676..a402bba935 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index 4f601e386c..a3c6d9d4ca 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "smi.h" diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl index 579f77460f..92bbbec2e0 100644 --- a/src/mainboard/lenovo/x60/acpi/ec.asl +++ b/src/mainboard/lenovo/x60/acpi/ec.asl @@ -1,16 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index a32dacdb85..7f16433948 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl index 38cf00dcd3..fe5b1ae329 100644 --- a/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl index bbbc2ff05a..5f6cf0fce6 100644 --- a/src/mainboard/lenovo/x60/acpi/platform.asl +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 4bb6b50b56..bb5d03dc65 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index d44105e51f..5a5c22e170 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x60/dock.h b/src/mainboard/lenovo/x60/dock.h index 4c41c88fdd..8e5791704f 100644 --- a/src/mainboard/lenovo/x60/dock.h +++ b/src/mainboard/lenovo/x60/dock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THINKPAD_X60_DOCK_H #define THINKPAD_X60_DOCK_H diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 2828e323b7..78a51d3435 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB diff --git a/src/mainboard/lenovo/x60/early_init.c b/src/mainboard/lenovo/x60/early_init.c index 8c4fc1dfd8..ef760fb974 100644 --- a/src/mainboard/lenovo/x60/early_init.c +++ b/src/mainboard/lenovo/x60/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x60/gpio.c b/src/mainboard/lenovo/x60/gpio.c index 74fcfa7483..2243dd16ec 100644 --- a/src/mainboard/lenovo/x60/gpio.c +++ b/src/mainboard/lenovo/x60/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c index 91a071a67c..7fd7809f86 100644 --- a/src/mainboard/lenovo/x60/hda_verb.c +++ b/src/mainboard/lenovo/x60/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x60/irq_tables.c b/src/mainboard/lenovo/x60/irq_tables.c index e5519c7c33..24b97b62c3 100644 --- a/src/mainboard/lenovo/x60/irq_tables.c +++ b/src/mainboard/lenovo/x60/irq_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 839fdabd72..86a2040fcf 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 8abb2a26de..f3d9cfcdea 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lenovo/x60/smi.h b/src/mainboard/lenovo/x60/smi.h index 9ab047eaf3..3a982463d7 100644 --- a/src/mainboard/lenovo/x60/smi.h +++ b/src/mainboard/lenovo/x60/smi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_LENOVO_X60_SMI_H #define MAINBOARD_LENOVO_X60_SMI_H diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index df33133ade..d00b35bf5d 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 08d9f9562e7a74af3377035f5c081746d6308bf1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:39 +0200 Subject: [PATCH 0802/1463] mainboard/msi: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ia5985bd013f68f5510dcad1de5a233f899a63ca0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40087 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/msi/ms7707/acpi_tables.c | 16 ++-------------- src/mainboard/msi/ms7707/early_init.c | 16 ++-------------- src/mainboard/msi/ms7707/gpio.c | 16 ++-------------- src/mainboard/msi/ms7707/hda_verb.c | 16 ++-------------- src/mainboard/msi/ms7721/BiosCallOuts.c | 15 ++------------- src/mainboard/msi/ms7721/OemCustomize.c | 15 ++------------- src/mainboard/msi/ms7721/OptionsIds.h | 15 ++------------- src/mainboard/msi/ms7721/acpi/cpstate.asl | 15 ++------------- src/mainboard/msi/ms7721/acpi/gpe.asl | 15 ++------------- src/mainboard/msi/ms7721/acpi/mainboard.asl | 15 ++------------- src/mainboard/msi/ms7721/acpi/routing.asl | 15 ++------------- src/mainboard/msi/ms7721/acpi/si.asl | 15 ++------------- src/mainboard/msi/ms7721/acpi/sleep.asl | 15 ++------------- src/mainboard/msi/ms7721/acpi_tables.c | 15 ++------------- src/mainboard/msi/ms7721/bootblock.c | 15 ++------------- src/mainboard/msi/ms7721/buildOpts.c | 15 ++------------- src/mainboard/msi/ms7721/dsdt.asl | 15 ++------------- src/mainboard/msi/ms7721/irq_tables.c | 15 ++------------- src/mainboard/msi/ms7721/mainboard.c | 15 ++------------- src/mainboard/msi/ms7721/mptable.c | 15 ++------------- src/mainboard/msi/ms7721/romstage.c | 15 ++------------- 21 files changed, 42 insertions(+), 277 deletions(-) diff --git a/src/mainboard/msi/ms7707/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c index 2b8c10087b..3851d04b22 100644 --- a/src/mainboard/msi/ms7707/acpi_tables.c +++ b/src/mainboard/msi/ms7707/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/msi/ms7707/early_init.c b/src/mainboard/msi/ms7707/early_init.c index 535ac23ff2..828c01ed4c 100644 --- a/src/mainboard/msi/ms7707/early_init.c +++ b/src/mainboard/msi/ms7707/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7707/gpio.c b/src/mainboard/msi/ms7707/gpio.c index 18e55c0c4c..7dad9f9fb1 100644 --- a/src/mainboard/msi/ms7707/gpio.c +++ b/src/mainboard/msi/ms7707/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c index a508c5ebf9..52d0e48898 100644 --- a/src/mainboard/msi/ms7707/hda_verb.c +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c index ed1809d4f6..9a4aa3d1d0 100644 --- a/src/mainboard/msi/ms7721/BiosCallOuts.c +++ b/src/mainboard/msi/ms7721/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 7c81afa37c..01b6fe4c62 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7721/OptionsIds.h b/src/mainboard/msi/ms7721/OptionsIds.h index dc507e8241..4bb2cb38cb 100644 --- a/src/mainboard/msi/ms7721/OptionsIds.h +++ b/src/mainboard/msi/ms7721/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/msi/ms7721/acpi/cpstate.asl b/src/mainboard/msi/ms7721/acpi/cpstate.asl index 4a49f6baf2..86361521a2 100644 --- a/src/mainboard/msi/ms7721/acpi/cpstate.asl +++ b/src/mainboard/msi/ms7721/acpi/cpstate.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file defines the processor and performance state capability * for each core in the system. It is included into the DSDT for each diff --git a/src/mainboard/msi/ms7721/acpi/gpe.asl b/src/mainboard/msi/ms7721/acpi/gpe.asl index be9f9fce2d..15da50c39f 100644 --- a/src/mainboard/msi/ms7721/acpi/gpe.asl +++ b/src/mainboard/msi/ms7721/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/msi/ms7721/acpi/mainboard.asl b/src/mainboard/msi/ms7721/acpi/mainboard.asl index 8cad2d8160..45427738f2 100644 --- a/src/mainboard/msi/ms7721/acpi/mainboard.asl +++ b/src/mainboard/msi/ms7721/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl index e6deee00dc..b7e1aaf41f 100644 --- a/src/mainboard/msi/ms7721/acpi/routing.asl +++ b/src/mainboard/msi/ms7721/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/msi/ms7721/acpi/si.asl b/src/mainboard/msi/ms7721/acpi/si.asl index cc27e983e1..e46f267284 100644 --- a/src/mainboard/msi/ms7721/acpi/si.asl +++ b/src/mainboard/msi/ms7721/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { /* DBGO("\\_SI\\_SST\n") */ diff --git a/src/mainboard/msi/ms7721/acpi/sleep.asl b/src/mainboard/msi/ms7721/acpi/sleep.asl index 1ce04c2336..d3399c9b38 100644 --- a/src/mainboard/msi/ms7721/acpi/sleep.asl +++ b/src/mainboard/msi/ms7721/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/msi/ms7721/acpi_tables.c b/src/mainboard/msi/ms7721/acpi_tables.c index be2669eeb8..3eb63c8920 100644 --- a/src/mainboard/msi/ms7721/acpi_tables.c +++ b/src/mainboard/msi/ms7721/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7721/bootblock.c b/src/mainboard/msi/ms7721/bootblock.c index 23570cd427..6ffaaae4f8 100644 --- a/src/mainboard/msi/ms7721/bootblock.c +++ b/src/mainboard/msi/ms7721/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 436844f324..d44dedadd0 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index ceac618519..5fb15eac9a 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/msi/ms7721/irq_tables.c b/src/mainboard/msi/ms7721/irq_tables.c index 4022ebb513..5d3304d23e 100644 --- a/src/mainboard/msi/ms7721/irq_tables.c +++ b/src/mainboard/msi/ms7721/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c index 32ebebef30..dc65a9451f 100644 --- a/src/mainboard/msi/ms7721/mainboard.c +++ b/src/mainboard/msi/ms7721/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index b9eba0bedb..067238a166 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 637360b05b..70072bb991 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From f4702c297d499bfa5e4f39e085e7791fde40f763 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:49 +0200 Subject: [PATCH 0803/1463] mainboard/packardbell: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ia380dd3faaaf7bdb16c8c877f5488dbbf01a4146 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40090 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/packardbell/ms2290/acpi/ac.asl | 16 ++-------------- .../packardbell/ms2290/acpi/battery.asl | 14 ++------------ src/mainboard/packardbell/ms2290/acpi/ec.asl | 16 ++-------------- src/mainboard/packardbell/ms2290/acpi/gpe.asl | 16 ++-------------- .../packardbell/ms2290/acpi/platform.asl | 16 ++-------------- .../packardbell/ms2290/acpi/thermal.asl | 14 ++------------ src/mainboard/packardbell/ms2290/acpi_tables.c | 16 ++-------------- src/mainboard/packardbell/ms2290/dsdt.asl | 16 ++-------------- src/mainboard/packardbell/ms2290/gpio.c | 14 ++------------ src/mainboard/packardbell/ms2290/mainboard.c | 16 ++-------------- src/mainboard/packardbell/ms2290/romstage.c | 16 ++-------------- src/mainboard/packardbell/ms2290/smihandler.c | 16 ++-------------- 12 files changed, 24 insertions(+), 162 deletions(-) diff --git a/src/mainboard/packardbell/ms2290/acpi/ac.asl b/src/mainboard/packardbell/ms2290/acpi/ac.asl index b3e960c06b..5d1d8bbcdb 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ac.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(AC) { diff --git a/src/mainboard/packardbell/ms2290/acpi/battery.asl b/src/mainboard/packardbell/ms2290/acpi/battery.asl index d341ab4488..1d03783f2e 100644 --- a/src/mainboard/packardbell/ms2290/acpi/battery.asl +++ b/src/mainboard/packardbell/ms2290/acpi/battery.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Arg0: Battery * Arg1: Battery Status Package diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl index 5b214b692b..37a7424180 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ec.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC) { diff --git a/src/mainboard/packardbell/ms2290/acpi/gpe.asl b/src/mainboard/packardbell/ms2290/acpi/gpe.asl index bc2b470fce..b35c5f3c0d 100644 --- a/src/mainboard/packardbell/ms2290/acpi/gpe.asl +++ b/src/mainboard/packardbell/ms2290/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 73ed8e7826..7f6407b032 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/packardbell/ms2290/acpi/thermal.asl b/src/mainboard/packardbell/ms2290/acpi/thermal.asl index 12f8568ad6..f4b25340a9 100644 --- a/src/mainboard/packardbell/ms2290/acpi/thermal.asl +++ b/src/mainboard/packardbell/ms2290/acpi/thermal.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_TZ) { diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index 1a932a6ba9..f315d860af 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index bb96c79bc0..f14a9eeda9 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/packardbell/ms2290/gpio.c b/src/mainboard/packardbell/ms2290/gpio.c index 3aed746af6..75eb9b1e60 100644 --- a/src/mainboard/packardbell/ms2290/gpio.c +++ b/src/mainboard/packardbell/ms2290/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index cc9421526e..8d4bb8e003 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index d502741174..2a9c744491 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index 694cd8c72a..fb52eaf87c 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 53e528a607c1a97433149c68ce61bec2de30eb49 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:03 +0200 Subject: [PATCH 0804/1463] mainboard/purism: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22515873a28333607ad2552c1a417e649cfbaac8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40093 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/purism/librem_bdw/acpi/ec.asl | 15 ++------------- .../purism/librem_bdw/acpi/mainboard.asl | 15 ++------------- src/mainboard/purism/librem_bdw/acpi/superio.asl | 15 ++------------- src/mainboard/purism/librem_bdw/acpi_tables.c | 15 ++------------- src/mainboard/purism/librem_bdw/dsdt.asl | 15 ++------------- src/mainboard/purism/librem_bdw/fadt.c | 15 ++------------- src/mainboard/purism/librem_bdw/gpio.c | 15 ++------------- src/mainboard/purism/librem_bdw/hda_verb.c | 15 ++------------- src/mainboard/purism/librem_bdw/mainboard.c | 15 ++------------- src/mainboard/purism/librem_bdw/romstage.c | 15 ++------------- .../librem_bdw/variants/librem13v1/pei_data.c | 15 ++------------- .../librem_bdw/variants/librem15v2/pei_data.c | 15 ++------------- src/mainboard/purism/librem_skl/acpi/ec.asl | 15 ++------------- .../purism/librem_skl/acpi/mainboard.asl | 15 ++------------- src/mainboard/purism/librem_skl/acpi/superio.asl | 15 ++------------- src/mainboard/purism/librem_skl/dsdt.asl | 15 ++------------- src/mainboard/purism/librem_skl/gpio.h | 15 ++------------- src/mainboard/purism/librem_skl/hda_verb.c | 15 ++------------- src/mainboard/purism/librem_skl/mainboard.c | 15 ++------------- src/mainboard/purism/librem_skl/ramstage.c | 15 ++------------- src/mainboard/purism/librem_skl/romstage.c | 15 ++------------- 21 files changed, 42 insertions(+), 273 deletions(-) diff --git a/src/mainboard/purism/librem_bdw/acpi/ec.asl b/src/mainboard/purism/librem_bdw/acpi/ec.asl index 2d23edc07e..dfd80ce576 100644 --- a/src/mainboard/purism/librem_bdw/acpi/ec.asl +++ b/src/mainboard/purism/librem_bdw/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define EC_SCI_GPI 10 #define PPCM_TURBO Zero diff --git a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl index 1357de19f6..8aaf285821 100644 --- a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/purism/librem_bdw/acpi/superio.asl b/src/mainboard/purism/librem_bdw/acpi/superio.asl index 606085fafe..1bc1628982 100644 --- a/src/mainboard/purism/librem_bdw/acpi/superio.asl +++ b/src/mainboard/purism/librem_bdw/acpi/superio.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 5677e2e735..84263cc397 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index f14a27f9a5..9f4aa03db1 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index 923b3c8e1c..2005ea7a78 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/purism/librem_bdw/gpio.c b/src/mainboard/purism/librem_bdw/gpio.c index d085702b78..57456088f7 100644 --- a/src/mainboard/purism/librem_bdw/gpio.c +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/purism/librem_bdw/hda_verb.c b/src/mainboard/purism/librem_bdw/hda_verb.c index 30c6769808..338b7a45b4 100644 --- a/src/mainboard/purism/librem_bdw/hda_verb.c +++ b/src/mainboard/purism/librem_bdw/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/purism/librem_bdw/mainboard.c b/src/mainboard/purism/librem_bdw/mainboard.c index c5825f93b1..3daa0c2167 100644 --- a/src/mainboard/purism/librem_bdw/mainboard.c +++ b/src/mainboard/purism/librem_bdw/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 00edc575bb..b6f90e318a 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c index 1aa0b29ff9..0cb038403b 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c index 7408a50d0a..fb8d189ebb 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/purism/librem_skl/acpi/ec.asl b/src/mainboard/purism/librem_skl/acpi/ec.asl index dc42606cc3..433ed55a6f 100644 --- a/src/mainboard/purism/librem_skl/acpi/ec.asl +++ b/src/mainboard/purism/librem_skl/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define EC_SCI_GPI 0x50 #define PPCM_TURBO One diff --git a/src/mainboard/purism/librem_skl/acpi/mainboard.asl b/src/mainboard/purism/librem_skl/acpi/mainboard.asl index 1357de19f6..8aaf285821 100644 --- a/src/mainboard/purism/librem_skl/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_skl/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/purism/librem_skl/acpi/superio.asl b/src/mainboard/purism/librem_skl/acpi/superio.asl index 606085fafe..1bc1628982 100644 --- a/src/mainboard/purism/librem_skl/acpi/superio.asl +++ b/src/mainboard/purism/librem_skl/acpi/superio.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 57ed3ab81f..687de930d0 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/purism/librem_skl/gpio.h b/src/mainboard/purism/librem_skl/gpio.h index 73917671d2..4979063903 100644 --- a/src/mainboard/purism/librem_skl/gpio.h +++ b/src/mainboard/purism/librem_skl/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c index 33f471a169..7262f1d916 100644 --- a/src/mainboard/purism/librem_skl/hda_verb.c +++ b/src/mainboard/purism/librem_skl/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/purism/librem_skl/mainboard.c b/src/mainboard/purism/librem_skl/mainboard.c index 2fa8e4c3ef..eb28262eb5 100644 --- a/src/mainboard/purism/librem_skl/mainboard.c +++ b/src/mainboard/purism/librem_skl/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/purism/librem_skl/ramstage.c b/src/mainboard/purism/librem_skl/ramstage.c index 975951ecae..ad70ca0c34 100644 --- a/src/mainboard/purism/librem_skl/ramstage.c +++ b/src/mainboard/purism/librem_skl/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "gpio.h" diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 56dc582cec..5679a7e157 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 7544e2fc2c040f8622a287a4e95b850f157da166 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:10 +0200 Subject: [PATCH 0805/1463] mainboard/roda: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib89ffc86d84550971b2c9a437581f1ad8e5c04ae Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40095 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/roda/rk886ex/acpi/battery.asl | 16 ++-------------- src/mainboard/roda/rk886ex/acpi/ec.asl | 16 ++-------------- src/mainboard/roda/rk886ex/acpi/gpe.asl | 16 ++-------------- .../roda/rk886ex/acpi/ich7_pci_irqs.asl | 16 ++-------------- src/mainboard/roda/rk886ex/acpi/mainboard.asl | 16 ++-------------- src/mainboard/roda/rk886ex/acpi/platform.asl | 16 ++-------------- src/mainboard/roda/rk886ex/acpi/superio.asl | 16 ++-------------- src/mainboard/roda/rk886ex/acpi/thermal.asl | 16 ++-------------- src/mainboard/roda/rk886ex/acpi_tables.c | 16 ++-------------- src/mainboard/roda/rk886ex/cstates.c | 14 ++------------ src/mainboard/roda/rk886ex/dsdt.asl | 16 ++-------------- src/mainboard/roda/rk886ex/early_init.c | 16 ++-------------- src/mainboard/roda/rk886ex/gpio.c | 15 ++------------- src/mainboard/roda/rk886ex/hda_verb.c | 14 ++------------ src/mainboard/roda/rk886ex/irq_tables.c | 16 ++-------------- src/mainboard/roda/rk886ex/m3885.c | 16 ++-------------- src/mainboard/roda/rk886ex/m3885.h | 15 ++------------- src/mainboard/roda/rk886ex/mainboard.c | 16 ++-------------- src/mainboard/roda/rk886ex/mptable.c | 16 ++-------------- src/mainboard/roda/rk9/acpi/battery.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi/ec.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi/gpe.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi/mainboard.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi/platform.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi/superio.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi/thermal.asl | 16 ++-------------- src/mainboard/roda/rk9/acpi_tables.c | 16 ++-------------- src/mainboard/roda/rk9/blc.c | 15 ++------------- src/mainboard/roda/rk9/bootblock.c | 16 ++-------------- src/mainboard/roda/rk9/cstates.c | 15 ++------------- src/mainboard/roda/rk9/dsdt.asl | 16 ++-------------- src/mainboard/roda/rk9/fadt.c | 16 ++-------------- src/mainboard/roda/rk9/gpio.c | 14 ++------------ src/mainboard/roda/rk9/hda_verb.c | 15 ++------------- src/mainboard/roda/rk9/mainboard.c | 15 ++------------- src/mainboard/roda/rk9/romstage.c | 16 ++-------------- src/mainboard/roda/rk9/smihandler.c | 15 ++------------- src/mainboard/roda/rk9/ti_pci7xx1.c | 16 ++-------------- src/mainboard/roda/rv11/acpi/alsd.asl | 15 ++------------- src/mainboard/roda/rv11/acpi/ec.asl | 15 ++------------- src/mainboard/roda/rv11/acpi/mainboard.asl | 15 ++------------- src/mainboard/roda/rv11/acpi/platform.asl | 15 ++------------- src/mainboard/roda/rv11/acpi/thermal.asl | 15 ++------------- src/mainboard/roda/rv11/acpi_tables.c | 15 ++------------- src/mainboard/roda/rv11/dsdt.asl | 15 ++------------- src/mainboard/roda/rv11/early_init.c | 15 ++------------- src/mainboard/roda/rv11/gpio.c | 15 ++------------- src/mainboard/roda/rv11/hda_verb.c | 15 ++------------- .../roda/rv11/variants/rv11/early_init.c | 15 ++------------- .../rv11/include/acpi/brightness_levels.asl | 14 ++------------ .../variants/rv11/include/variant/hda_verb.h | 15 ++------------- .../rv11/variants/rv11/include/variant/thermal.h | 15 ++------------- .../roda/rv11/variants/rw11/early_init.c | 15 ++------------- .../rw11/include/acpi/brightness_levels.asl | 14 ++------------ .../rv11/variants/rw11/include/acpi/superio.asl | 15 ++------------- .../variants/rw11/include/variant/hda_verb.h | 15 ++------------- .../rv11/variants/rw11/include/variant/thermal.h | 15 ++------------- 58 files changed, 116 insertions(+), 778 deletions(-) diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl index 59b17e1a6d..bc40f0fcd1 100644 --- a/src/mainboard/roda/rk886ex/acpi/battery.asl +++ b/src/mainboard/roda/rk886ex/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(\CBA1, 0x60) Name(\CBA2, 0x60) diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index 6839f8e0bf..edb11ce74e 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC0) { diff --git a/src/mainboard/roda/rk886ex/acpi/gpe.asl b/src/mainboard/roda/rk886ex/acpi/gpe.asl index 2e27d9faf7..11665be4ab 100644 --- a/src/mainboard/roda/rk886ex/acpi/gpe.asl +++ b/src/mainboard/roda/rk886ex/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (_GPE) { diff --git a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl index c49624fec9..03a036a8fe 100644 --- a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/roda/rk886ex/acpi/mainboard.asl b/src/mainboard/roda/rk886ex/acpi/mainboard.asl index 460360a9b4..deba6c3eb4 100644 --- a/src/mainboard/roda/rk886ex/acpi/mainboard.asl +++ b/src/mainboard/roda/rk886ex/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LID0) { diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index e873efff56..07541952f4 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index 1d5ef74c9b..4d19281305 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SMSC LPC47N227 */ diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index f06b273b2b..a3e762f454 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index 0675b4114d..4a4c02ccb4 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk886ex/cstates.c b/src/mainboard/roda/rk886ex/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/roda/rk886ex/cstates.c +++ b/src/mainboard/roda/rk886ex/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index 45adb82081..c58f89558c 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index a0ae5fcee5..fe61187f24 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk886ex/gpio.c b/src/mainboard/roda/rk886ex/gpio.c index f1c6af0781..82e0d46435 100644 --- a/src/mainboard/roda/rk886ex/gpio.c +++ b/src/mainboard/roda/rk886ex/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk886ex/hda_verb.c b/src/mainboard/roda/rk886ex/hda_verb.c index 5d088790a5..0700c48e63 100644 --- a/src/mainboard/roda/rk886ex/hda_verb.c +++ b/src/mainboard/roda/rk886ex/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c index bc9fe78db7..9807b6f739 100644 --- a/src/mainboard/roda/rk886ex/irq_tables.c +++ b/src/mainboard/roda/rk886ex/irq_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 5c514dc6c1..f4577be6fa 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk886ex/m3885.h b/src/mainboard/roda/rk886ex/m3885.h index ccf3aca770..80aa6df9ea 100644 --- a/src/mainboard/roda/rk886ex/m3885.h +++ b/src/mainboard/roda/rk886ex/m3885.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_M3885_H #define _MAINBOARD_M3885_H diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index d203716dad..cd10995726 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index 88d2aa29f1..4eef60d84d 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk9/acpi/battery.asl b/src/mainboard/roda/rk9/acpi/battery.asl index c4875786fa..763cfaca81 100644 --- a/src/mainboard/roda/rk9/acpi/battery.asl +++ b/src/mainboard/roda/rk9/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(\CBA1, 0x60) Name(\CBA2, 0x60) diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index dbe7f29ee6..997c4765c5 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC0) { diff --git a/src/mainboard/roda/rk9/acpi/gpe.asl b/src/mainboard/roda/rk9/acpi/gpe.asl index 8d08361b65..2f25534d62 100644 --- a/src/mainboard/roda/rk9/acpi/gpe.asl +++ b/src/mainboard/roda/rk9/acpi/gpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (_GPE) { diff --git a/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl index ecc805abcf..be9ecd0820 100644 --- a/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl +++ b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH9 diff --git a/src/mainboard/roda/rk9/acpi/mainboard.asl b/src/mainboard/roda/rk9/acpi/mainboard.asl index 204f8308aa..842c4d386c 100644 --- a/src/mainboard/roda/rk9/acpi/mainboard.asl +++ b/src/mainboard/roda/rk9/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LID0) { diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl index 451d19785f..cc66bfbc41 100644 --- a/src/mainboard/roda/rk9/acpi/platform.asl +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/roda/rk9/acpi/superio.asl b/src/mainboard/roda/rk9/acpi/superio.asl index 1d5ef74c9b..4d19281305 100644 --- a/src/mainboard/roda/rk9/acpi/superio.asl +++ b/src/mainboard/roda/rk9/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SMSC LPC47N227 */ diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 8eb8195d4c..21aa8cd74b 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index fc9a16ce82..fca8cb7953 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk9/blc.c b/src/mainboard/roda/rk9/blc.c index a8171a26c4..9d657e9b1c 100644 --- a/src/mainboard/roda/rk9/blc.c +++ b/src/mainboard/roda/rk9/blc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk9/bootblock.c b/src/mainboard/roda/rk9/bootblock.c index a7f4b3aaf7..6b2e5447d7 100644 --- a/src/mainboard/roda/rk9/bootblock.c +++ b/src/mainboard/roda/rk9/bootblock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c index a167f91135..6fb09967f0 100644 --- a/src/mainboard/roda/rk9/cstates.c +++ b/src/mainboard/roda/rk9/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index 5a1d21b53e..de5b1dd2b9 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index c3c9015ab6..3aeb8bc5c0 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk9/gpio.c b/src/mainboard/roda/rk9/gpio.c index 4e1ebe3cda..d6e54c765e 100644 --- a/src/mainboard/roda/rk9/gpio.c +++ b/src/mainboard/roda/rk9/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk9/hda_verb.c b/src/mainboard/roda/rk9/hda_verb.c index 088f99a195..f543de6d1a 100644 --- a/src/mainboard/roda/rk9/hda_verb.c +++ b/src/mainboard/roda/rk9/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index a72ae76afd..23f231d6a5 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index beebb70051..717886d134 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c index fc730cbd3b..b473d4930c 100644 --- a/src/mainboard/roda/rk9/smihandler.c +++ b/src/mainboard/roda/rk9/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c index e55542907a..9e2faa2e77 100644 --- a/src/mainboard/roda/rk9/ti_pci7xx1.c +++ b/src/mainboard/roda/rk9/ti_pci7xx1.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rv11/acpi/alsd.asl b/src/mainboard/roda/rv11/acpi/alsd.asl index 3b90d1eefa..95c54e8f8c 100644 --- a/src/mainboard/roda/rv11/acpi/alsd.asl +++ b/src/mainboard/roda/rv11/acpi/alsd.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (ALSD) { diff --git a/src/mainboard/roda/rv11/acpi/ec.asl b/src/mainboard/roda/rv11/acpi/ec.asl index 9a9decaf3e..0e5b1ac01d 100644 --- a/src/mainboard/roda/rv11/acpi/ec.asl +++ b/src/mainboard/roda/rv11/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define EC_SCI_GPI 7 #include diff --git a/src/mainboard/roda/rv11/acpi/mainboard.asl b/src/mainboard/roda/rv11/acpi/mainboard.asl index 4c111e2351..eeb8fbfd9f 100644 --- a/src/mainboard/roda/rv11/acpi/mainboard.asl +++ b/src/mainboard/roda/rv11/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/roda/rv11/acpi/platform.asl b/src/mainboard/roda/rv11/acpi/platform.asl index cb4c8835e7..bd55316ef1 100644 --- a/src/mainboard/roda/rv11/acpi/platform.asl +++ b/src/mainboard/roda/rv11/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/roda/rv11/acpi/thermal.asl b/src/mainboard/roda/rv11/acpi/thermal.asl index 4f56d207d6..8264822f68 100644 --- a/src/mainboard/roda/rv11/acpi/thermal.asl +++ b/src/mainboard/roda/rv11/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/roda/rv11/acpi_tables.c b/src/mainboard/roda/rv11/acpi_tables.c index 7ff962f54c..6d974bfb42 100644 --- a/src/mainboard/roda/rv11/acpi_tables.c +++ b/src/mainboard/roda/rv11/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index f42cef7ee9..ae251a16d1 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/roda/rv11/early_init.c b/src/mainboard/roda/rv11/early_init.c index bb6ff0d0c2..f5bc554ee9 100644 --- a/src/mainboard/roda/rv11/early_init.c +++ b/src/mainboard/roda/rv11/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rv11/gpio.c b/src/mainboard/roda/rv11/gpio.c index 751ccc727e..f00443d5b2 100644 --- a/src/mainboard/roda/rv11/gpio.c +++ b/src/mainboard/roda/rv11/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rv11/hda_verb.c b/src/mainboard/roda/rv11/hda_verb.c index 8ab845deda..b08df8b46a 100644 --- a/src/mainboard/roda/rv11/hda_verb.c +++ b/src/mainboard/roda/rv11/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 1a9c47e328..4bee166053 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl b/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl index b92589a075..68635f2215 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl +++ b/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h index bb92eab2dc..f858e53a69 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h +++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ const u32 cim_verb_data[] = { /* coreboot specific header */ diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h index e742e677dc..0ebb75a381 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h +++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define CRITICAL_TEMPERATURE 106 #define PASSIVE_TEMPERATURE 100 diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index da19839359..bae8b4923a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl index 506de019a5..6bc2292551 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl +++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl index 0ced6ad3a4..8bc20f2506 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl +++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h index d86e335bd2..515751b663 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h +++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ const u32 cim_verb_data[] = { /* coreboot specific header */ diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h index 1da8621eb0..c55aaa45fb 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h +++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define CRITICAL_TEMPERATURE 100 #define PASSIVE_TEMPERATURE 95 From 6ad917606cc6971ebc9835d348aaeebe8ca21352 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:24 +0200 Subject: [PATCH 0806/1463] mainboard/siemens: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7b656f0244774cb174a90d97c5ae1c725802b636 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40099 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/siemens/mc_apl1/bootblock.c | 15 ++------------- src/mainboard/siemens/mc_apl1/dsdt.asl | 15 ++------------- src/mainboard/siemens/mc_apl1/mainboard.c | 15 ++------------- src/mainboard/siemens/mc_apl1/romstage.c | 15 ++------------- .../siemens/mc_apl1/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../siemens/mc_apl1/variants/baseboard/memory.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl1/lcd_panel.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl1/mainboard.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl2/gpio.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl2/mainboard.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl3/gpio.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl3/mainboard.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl4/gpio.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl4/lcd_panel.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl4/memory.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl5/gpio.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl5/lcd_panel.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl5/mainboard.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl6/gpio.c | 15 ++------------- .../siemens/mc_apl1/variants/mc_apl6/mainboard.c | 15 ++------------- 21 files changed, 42 insertions(+), 273 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index 3c8d5bd89c..695aaac1f0 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index b597480330..a13f387a95 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 716f4e0f74..1a134a5d40 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index c967063416..366a139be1 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index eeab878610..c2c28791ef 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h index 1ee4281aca..afbeb33735 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BASEBOARD_VARIANTS_H_ #define _BASEBOARD_VARIANTS_H_ diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c index c90e1e4a94..99481eb3a0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c index 5efced8bd5..0412900e44 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index 9698c2b007..d9a6db07a3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index 4a7255e665..aceab33fc4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index e6aff80055..1aa5fb2745 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index 12f8339fd0..fb1499b8f6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 36c736bd26..a69677be82 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index 8b3e7e2693..f23bc3fe67 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c index 641b7488a6..5fe21f6451 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c index af0bf4672a..6ebaf5fbdc 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index 39e086a39e..68e2ca9b18 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c index 90aade5b45..5576b5606b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 4c696adbb3..023195f859 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c index 38b7c4473e..53f18ca809 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 6ba13fea92..aa96d9bba5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From d32b6dee6bfd609ce44c195abd0410d5f56c8f5f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:13 +0200 Subject: [PATCH 0807/1463] mainboard/samsung: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I588617bad4f4e9213021fb30cb6085273a36e70e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40096 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/samsung/lumpy/acpi/ec.asl | 15 ++------------- src/mainboard/samsung/lumpy/acpi/mainboard.asl | 16 ++-------------- src/mainboard/samsung/lumpy/acpi/platform.asl | 15 ++------------- src/mainboard/samsung/lumpy/acpi/superio.asl | 15 ++------------- src/mainboard/samsung/lumpy/acpi/thermal.asl | 15 ++------------- src/mainboard/samsung/lumpy/acpi/usb.asl | 14 ++------------ src/mainboard/samsung/lumpy/acpi_tables.c | 15 ++------------- src/mainboard/samsung/lumpy/chromeos.c | 15 ++------------- src/mainboard/samsung/lumpy/dsdt.asl | 15 ++------------- src/mainboard/samsung/lumpy/early_init.c | 15 ++------------- src/mainboard/samsung/lumpy/ec.c | 15 ++------------- src/mainboard/samsung/lumpy/ec.h | 15 ++------------- src/mainboard/samsung/lumpy/gpio.c | 15 ++------------- src/mainboard/samsung/lumpy/hda_verb.c | 15 ++------------- src/mainboard/samsung/lumpy/mainboard.c | 15 ++------------- src/mainboard/samsung/lumpy/onboard.h | 15 ++------------- src/mainboard/samsung/lumpy/smihandler.c | 15 ++------------- src/mainboard/samsung/lumpy/thermal.h | 15 ++------------- src/mainboard/samsung/stumpy/acpi/mainboard.asl | 16 ++-------------- src/mainboard/samsung/stumpy/acpi/platform.asl | 15 ++------------- src/mainboard/samsung/stumpy/acpi/superio.asl | 15 ++------------- src/mainboard/samsung/stumpy/acpi/thermal.asl | 15 ++------------- src/mainboard/samsung/stumpy/acpi_tables.c | 15 ++------------- src/mainboard/samsung/stumpy/chromeos.c | 15 ++------------- src/mainboard/samsung/stumpy/dsdt.asl | 15 ++------------- src/mainboard/samsung/stumpy/early_init.c | 15 ++------------- src/mainboard/samsung/stumpy/gpio.c | 15 ++------------- src/mainboard/samsung/stumpy/hda_verb.c | 15 ++------------- src/mainboard/samsung/stumpy/mainboard.c | 15 ++------------- src/mainboard/samsung/stumpy/smihandler.c | 15 ++------------- src/mainboard/samsung/stumpy/thermal.h | 15 ++------------- 31 files changed, 62 insertions(+), 404 deletions(-) diff --git a/src/mainboard/samsung/lumpy/acpi/ec.asl b/src/mainboard/samsung/lumpy/acpi/ec.asl index 9d50a588d9..ada7eb96f1 100644 --- a/src/mainboard/samsung/lumpy/acpi/ec.asl +++ b/src/mainboard/samsung/lumpy/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* EC configuration */ #define EC_GPE 23 // GPE23 -> Runtime SCI diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index 080bff9b79..8e1e8b182c 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl index 11a304e90f..abe8add66d 100644 --- a/src/mainboard/samsung/lumpy/acpi/platform.asl +++ b/src/mainboard/samsung/lumpy/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl index dfd89f751c..8d0ed03514 100644 --- a/src/mainboard/samsung/lumpy/acpi/superio.asl +++ b/src/mainboard/samsung/lumpy/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/samsung/lumpy/acpi/thermal.asl b/src/mainboard/samsung/lumpy/acpi/thermal.asl index b1df43e487..d503d6c9fb 100644 --- a/src/mainboard/samsung/lumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/lumpy/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/samsung/lumpy/acpi/usb.asl b/src/mainboard/samsung/lumpy/acpi/usb.asl index 0dce39eafa..ca52e979a4 100644 --- a/src/mainboard/samsung/lumpy/acpi/usb.asl +++ b/src/mainboard/samsung/lumpy/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.EHC1.HUB7.PRT1) { diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 9ef9d1cc28..7e6e5593d1 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 55dee06e5a..0d5c0f6a07 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index a6f38d9da3..10aa1f7453 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index bfb1b49f8b..817276e904 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index 492e6e9133..9e7e5bba42 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/lumpy/ec.h b/src/mainboard/samsung/lumpy/ec.h index b0114ade6f..8a65d86f99 100644 --- a/src/mainboard/samsung/lumpy/ec.h +++ b/src/mainboard/samsung/lumpy/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LUMPY_EC_H #define LUMPY_EC_H diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c index 565a9facc3..b7722bf776 100644 --- a/src/mainboard/samsung/lumpy/gpio.c +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LUMPY_GPIO_H #define LUMPY_GPIO_H diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c index 12de96ab00..48837509db 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.c +++ b/src/mainboard/samsung/lumpy/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index fcf4140b34..3fe88fb053 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index 63f019061f..d5e0ee312f 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LUMPY_ONBOARD_H #define LUMPY_ONBOARD_H diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index fc10b35111..182946824e 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/lumpy/thermal.h b/src/mainboard/samsung/lumpy/thermal.h index 64145f59f3..cab45943cd 100644 --- a/src/mainboard/samsung/lumpy/thermal.h +++ b/src/mainboard/samsung/lumpy/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LUMPY_THERMAL_H #define LUMPY_THERMAL_H diff --git a/src/mainboard/samsung/stumpy/acpi/mainboard.asl b/src/mainboard/samsung/stumpy/acpi/mainboard.asl index b41486f960..1da38b2dc4 100644 --- a/src/mainboard/samsung/stumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/stumpy/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/samsung/stumpy/acpi/platform.asl b/src/mainboard/samsung/stumpy/acpi/platform.asl index e48bc4367d..5fa04a86ab 100644 --- a/src/mainboard/samsung/stumpy/acpi/platform.asl +++ b/src/mainboard/samsung/stumpy/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/samsung/stumpy/acpi/superio.asl b/src/mainboard/samsung/stumpy/acpi/superio.asl index 73737f3817..42fcd1790c 100644 --- a/src/mainboard/samsung/stumpy/acpi/superio.asl +++ b/src/mainboard/samsung/stumpy/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl index 896d001976..71753c4c07 100644 --- a/src/mainboard/samsung/stumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 637abfabe6..99efad94b0 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index d8e2c87720..ac889ec11c 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 425efa88fe..fa5ad51000 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index d6ace45337..8f5e97d9a6 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/stumpy/gpio.c b/src/mainboard/samsung/stumpy/gpio.c index f4ca4209ce..31f58efc3a 100644 --- a/src/mainboard/samsung/stumpy/gpio.c +++ b/src/mainboard/samsung/stumpy/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef STUMPY_GPIO_H #define STUMPY_GPIO_H diff --git a/src/mainboard/samsung/stumpy/hda_verb.c b/src/mainboard/samsung/stumpy/hda_verb.c index 23063707b8..d98b9c6bd7 100644 --- a/src/mainboard/samsung/stumpy/hda_verb.c +++ b/src/mainboard/samsung/stumpy/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 757f2fd8c5..9b56890403 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 3bcb1dff23..3f511a16c5 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/samsung/stumpy/thermal.h b/src/mainboard/samsung/stumpy/thermal.h index 9b8db33c4a..f49338c8d0 100644 --- a/src/mainboard/samsung/stumpy/thermal.h +++ b/src/mainboard/samsung/stumpy/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef STUMPY_THERMAL_H #define STUMPY_THERMAL_H From 986d50ea47ed9fc6f0177c1ab904ebfd7f39ec02 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:53 +0200 Subject: [PATCH 0808/1463] src/security: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I51f5764b57fb8b62e3a4b3d41bd32e5330a2983c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40057 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/security/memory/memory.c | 15 ++------------- src/security/memory/memory.h | 15 ++------------- src/security/memory/memory_clear.c | 15 ++------------- src/security/tpm/tis.h | 15 ++------------- src/security/tpm/tspi.h | 15 ++------------- src/security/tpm/tspi/crtm.c | 15 ++------------- src/security/tpm/tspi/crtm.h | 15 ++------------- src/security/tpm/tspi/log.c | 15 ++------------- src/security/tpm/tspi/tspi.c | 15 ++------------- src/security/tpm/tss/common/tss_common.h | 15 ++------------- src/security/tpm/tss/tcg-1.2/tss_commands.h | 15 ++------------- src/security/tpm/tss/vendor/cr50/cr50.h | 15 ++------------- src/security/vboot/bootmode.c | 15 ++------------- src/security/vboot/common.c | 15 ++------------- src/security/vboot/ec_sync.c | 14 ++------------ src/security/vboot/misc.h | 15 ++------------- src/security/vboot/mrc_cache_hash_tpm.c | 15 ++------------- src/security/vboot/symbols.h | 15 ++------------- src/security/vboot/tpm_common.c | 14 ++------------ src/security/vboot/tpm_common.h | 14 ++------------ src/security/vboot/vbnv.c | 15 ++------------- src/security/vboot/vbnv.h | 15 ++------------- src/security/vboot/vbnv_cmos.c | 15 ++------------- src/security/vboot/vbnv_ec.c | 15 ++------------- src/security/vboot/vbnv_flash.c | 15 ++------------- src/security/vboot/vbnv_layout.h | 15 ++------------- src/security/vboot/vboot_common.c | 15 ++------------- src/security/vboot/vboot_common.h | 15 ++------------- src/security/vboot/vboot_loader.c | 15 ++------------- src/security/vboot/vboot_logic.c | 15 ++------------- src/security/vboot/verstage.c | 15 ++------------- 31 files changed, 62 insertions(+), 400 deletions(-) diff --git a/src/security/memory/memory.c b/src/security/memory/memory.c index f2c35c0431..416a6c9590 100644 --- a/src/security/memory/memory.c +++ b/src/security/memory/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "memory.h" diff --git a/src/security/memory/memory.h b/src/security/memory/memory.h index 91638f4cc1..73066e9f35 100644 --- a/src/security/memory/memory.h +++ b/src/security/memory/memory.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index d9d053d4b6..75c31abace 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(ARCH_X86) #include diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index c5452e6032..b14ced8221 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef TIS_H_ #define TIS_H_ diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 7ea90e280e..26fabbfabf 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef TSPI_H_ #define TSPI_H_ diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 304cea38e9..b22f3166cf 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index eb624951ca..281c8fc7a9 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SECURITY_TSPI_CRTM_H__ #define __SECURITY_TSPI_CRTM_H__ diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index e43f74d069..619357a0d7 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index b94a0fb029..7a88f8db6d 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/tpm/tss/common/tss_common.h b/src/security/tpm/tss/common/tss_common.h index 5804cc400f..124ec4ad14 100644 --- a/src/security/tpm/tss/common/tss_common.h +++ b/src/security/tpm/tss/common/tss_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef TCG_TSS_COMMON_H_ #define TCG_TSS_COMMON_H_ diff --git a/src/security/tpm/tss/tcg-1.2/tss_commands.h b/src/security/tpm/tss/tcg-1.2/tss_commands.h index 5184ff97c1..2a72a9a619 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_commands.h +++ b/src/security/tpm/tss/tcg-1.2/tss_commands.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 55c3fd2fa0..e3137630de 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CR50_TSS_STRUCTURES_H_ #define CR50_TSS_STRUCTURES_H_ diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 9c4eb2bb36..83a06cef29 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 855406547e..38469f8181 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index e7b64b2398..3a177b16e8 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 7e479678e1..fd422b2ff7 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __VBOOT_MISC_H__ #define __VBOOT_MISC_H__ diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index 0e9b9a865c..d1afe997f4 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/symbols.h b/src/security/vboot/symbols.h index 8f6063efac..53486f3c4f 100644 --- a/src/security/vboot/symbols.h +++ b/src/security/vboot/symbols.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __VBOOT_SYMBOLS_H__ #define __VBOOT_SYMBOLS_H__ diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 0a211c57d4..d763c97811 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/security/vboot/tpm_common.h b/src/security/vboot/tpm_common.h index e1faa0ca45..5cc8fb742b 100644 --- a/src/security/vboot/tpm_common.h +++ b/src/security/vboot/tpm_common.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(TPM1) || CONFIG(TPM2) diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 5c0ff970a6..bd8b882d1c 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index 0a582ff1f1..b4418b511e 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __VBOOT_VBNV_H__ #define __VBOOT_VBNV_H__ diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index 56f207e243..e16c2fb8c7 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/vbnv_ec.c b/src/security/vboot/vbnv_ec.c index 58f7d03f62..8ecb5492df 100644 --- a/src/security/vboot/vbnv_ec.c +++ b/src/security/vboot/vbnv_ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/vbnv_flash.c b/src/security/vboot/vbnv_flash.c index 7e44d62aae..5cdb9aa69d 100644 --- a/src/security/vboot/vbnv_flash.c +++ b/src/security/vboot/vbnv_flash.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index 4c320b1db0..562859db76 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __VBOOT_VBNV_LAYOUT_H__ #define __VBOOT_VBNV_LAYOUT_H__ diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index b5815abf5a..36cd1ade4e 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index d825b82f29..50995e6c04 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __VBOOT_VBOOT_COMMON_H__ #define __VBOOT_VBOOT_COMMON_H__ diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 4cf3eea35d..bee065ab90 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index ab5b53dc5f..9e9e82ac6b 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/security/vboot/verstage.c b/src/security/vboot/verstage.c index 1fa6a90741..e12c4cedef 100644 --- a/src/security/vboot/verstage.c +++ b/src/security/vboot/verstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 118a9c7b0368f79a00b017c799e2562c229269d2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:34 +0200 Subject: [PATCH 0809/1463] src/lib: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id3a0b63272ebda3dad13803700bcff36d36f4815 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40054 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/lib/boot_device.c | 15 ++------------- src/lib/bootblock.c | 16 ++-------------- src/lib/bootmem.c | 15 ++------------- src/lib/bootmode.c | 15 ++------------- src/lib/bootsplash.c | 15 ++------------- src/lib/cbfs.c | 15 ++------------- src/lib/cbmem_common.c | 15 ++------------- src/lib/cbmem_console.c | 15 ++------------- src/lib/cbmem_stage_cache.c | 15 ++------------- src/lib/coreboot_table.c | 16 ++-------------- src/lib/crc_byte.c | 15 ++------------- src/lib/decompressor.c | 16 ++-------------- src/lib/dimm_info_util.c | 15 ++------------- src/lib/ext_stage_cache.c | 15 ++------------- src/lib/fit_payload.c | 15 ++------------- src/lib/fmap.c | 15 ++------------- src/lib/gcc.c | 15 ++------------- src/lib/gcov-glue.c | 15 ++------------- src/lib/gpio.c | 15 ++------------- src/lib/halt.c | 16 ++-------------- src/lib/hardwaremain.c | 15 ++------------- src/lib/imd.c | 15 ++------------- src/lib/imd_cbmem.c | 15 ++------------- src/lib/jpeg.c | 15 ++------------- src/lib/jpeg.h | 15 ++------------- src/lib/libgcc.c | 15 ++------------- src/lib/memrange.c | 15 ++------------- src/lib/nhlt.c | 15 ++------------- src/lib/primitive_memtest.c | 15 ++------------- src/lib/prog_loaders.c | 15 ++------------- src/lib/prog_ops.c | 15 ++------------- src/lib/program.ld | 15 ++------------- src/lib/ramdetect.c | 14 ++------------ src/lib/reg_script.c | 15 ++------------- src/lib/region_file.c | 15 ++------------- src/lib/reset.c | 15 ++------------- src/lib/rmodule.c | 15 ++------------- src/lib/romstage_handoff.c | 15 ++------------- src/lib/selfboot.c | 15 ++------------- src/lib/spd_bin.c | 15 ++------------- src/lib/thread.c | 15 ++------------- src/lib/timer.c | 15 ++------------- src/lib/timer_queue.c | 15 ++------------- src/lib/timestamp.c | 15 ++------------- src/lib/trace.c | 15 ++------------- src/lib/uuid.c | 14 ++------------ src/lib/wrdd.c | 15 ++------------- 47 files changed, 94 insertions(+), 613 deletions(-) diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index dfb4066198..12ca36ba50 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 0731a72069..565d619a3e 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 0fd5be0ac0..aa8087dace 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 1356333b15..f82b1545f2 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index f577e9eff0..a67d54d532 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index ccd7e6a7ce..5e85bb9bde 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 836406cbd6..1f0bb58aaa 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 270bd63dc5..3770642db7 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index f8a725471f..d4dd82ffcc 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 947a33f162..d2615243b2 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/crc_byte.c b/src/lib/crc_byte.c index 55529a2346..d7de1e77a4 100644 --- a/src/lib/crc_byte.c +++ b/src/lib/crc_byte.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index 4b7cb975c5..ab65beb4b5 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/dimm_info_util.c b/src/lib/dimm_info_util.c index 84c0a05ee2..b1a2c4b928 100644 --- a/src/lib/dimm_info_util.c +++ b/src/lib/dimm_info_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 825a7f0439..f28418ab2e 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 9e2cadc24d..9cf154271b 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/fmap.c b/src/lib/fmap.c index d004d8ed11..ecd23f6d32 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/gcc.c b/src/lib/gcc.c index b6208f5288..33dcb2e116 100644 --- a/src/lib/gcc.c +++ b/src/lib/gcc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 48dc46d563..b7d4b7331a 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/gpio.c b/src/lib/gpio.c index a453bc7417..c25b3f9f85 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/halt.c b/src/lib/halt.c index d5db09755e..92795dbc6c 100644 --- a/src/lib/halt.c +++ b/src/lib/halt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 72e3376028..4fdf55446a 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* diff --git a/src/lib/imd.c b/src/lib/imd.c index 2cfd3ec5fc..5a25719032 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index ed98947fcc..13b5483c45 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/jpeg.c b/src/lib/jpeg.c index 47d3fe33c5..23532024e3 100644 --- a/src/lib/jpeg.c +++ b/src/lib/jpeg.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * a tiny jpeg decoder. diff --git a/src/lib/jpeg.h b/src/lib/jpeg.h index de9be5b9e9..e2dc8a886f 100644 --- a/src/lib/jpeg.h +++ b/src/lib/jpeg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * a tiny jpeg decoder. diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index 7fe20a1644..e5ed56dbe6 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/lib/memrange.c b/src/lib/memrange.c index fd7a4d6489..32f053de08 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index d65bfda55c..4ed3c6c13c 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/primitive_memtest.c b/src/lib/primitive_memtest.c index 2e23b45107..6154f221a0 100644 --- a/src/lib/primitive_memtest.c +++ b/src/lib/primitive_memtest.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 8cc8e12edb..c336575434 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index 52ed465c03..55943dc328 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/lib/program.ld b/src/lib/program.ld index 40bbb31e5a..6f096dc360 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 2c83092ebc..cf395bd712 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index baec94e342..2549f2b8fc 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/region_file.c b/src/lib/region_file.c index d847e9872a..dcfc663496 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/reset.c b/src/lib/reset.c index feba3c2306..2b066b2fb8 100644 --- a/src/lib/reset.c +++ b/src/lib/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 88ab06d8a4..e99f10a38b 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index b4b817ed66..963fedf4c6 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index eef857719e..7def7b164a 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index df310f3e56..2f9bb160ce 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/thread.c b/src/lib/thread.c index d61222da63..28eeaf42a1 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/timer.c b/src/lib/timer.c index ef097e68b4..2c4f8eb9a6 100644 --- a/src/lib/timer.c +++ b/src/lib/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index bc5d782407..dd877fb22f 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 4dc6623869..df07bececb 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/trace.c b/src/lib/trace.c index b028bcacd0..54471b0de4 100644 --- a/src/lib/trace.c +++ b/src/lib/trace.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/uuid.c b/src/lib/uuid.c index b5c00d7efb..2d9e90e252 100644 --- a/src/lib/uuid.c +++ b/src/lib/uuid.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c index 859c550db2..adb2b1d5d1 100644 --- a/src/lib/wrdd.c +++ b/src/lib/wrdd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From 37f3d7bb706f4ee93e7a378028fc328ebbe08ca8 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 1 Apr 2020 01:51:07 -0500 Subject: [PATCH 0810/1463] mb/samsung/stumpy: Drop ACPI brightness controls Stumpy is a Chromebox without a built-in display, and now that default_brightness_levels.asl is no longer required for all boards in a platform, drop it and the default panel definition. Test: build/boot stumpy Change-Id: Iaf475f3529dd19330ea46532e9ffd20b44893f7e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40046 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/samsung/stumpy/devicetree.cb | 2 -- src/mainboard/samsung/stumpy/dsdt.asl | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 8e79b393e2..df640b55fd 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -1,6 +1,4 @@ chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index fa5ad51000..b5bb0ef684 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -28,8 +28,6 @@ DefinitionBlock( { #include #include - - #include } } From 7c45c8363d86280d70cb671ea713a06fd462a6e7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 4 Apr 2020 21:00:56 +0200 Subject: [PATCH 0811/1463] assert.h: Add a tag parameter to dead_code() When dead_code() is used in inline functions in a header file, the generated function names (based on the line number) may collide with a dead_code() in the code file. Now that we are hit by such a case, we need a quick solution: Add a tag argument for all invocations in header files. Change-Id: I0c548ce998cf8e28ae9f76b5c0ea5630b4e91ae2 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40140 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/include/assert.h | 10 +++++----- src/security/vboot/misc.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/include/assert.h b/src/include/assert.h index 990cee11b5..fbaf11a4d6 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -65,13 +65,13 @@ * ramstage/lib/bootmode.o: In function `display_init_required': * bootmode.c:42: undefined reference to `dead_code_assertion_failed_at_line_42' */ -#define __dead_code(line) do { \ - extern void dead_code_assertion_failed_at_line_##line(void) \ +#define __dead_code(tag, line) do { \ + extern void dead_code_assertion_failed##tag##_at_line_##line(void) \ __attribute__((noreturn)); \ - dead_code_assertion_failed_at_line_##line(); \ + dead_code_assertion_failed##tag##_at_line_##line(); \ } while (0) -#define _dead_code(line) __dead_code(line) -#define dead_code() _dead_code(__LINE__) +#define _dead_code(tag, line) __dead_code(tag, line) +#define dead_code(tag) _dead_code(tag, __LINE__) /* This can be used in the context of an expression of type 'type'. */ #define dead_code_t(type) ({ \ diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index fd422b2ff7..22cc75052c 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -53,7 +53,7 @@ static inline int verification_should_run(void) else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return ENV_BOOTBLOCK; else - dead_code(); + dead_code(_in_vboot_misc_h); } static inline int verstage_should_load(void) @@ -82,7 +82,7 @@ static inline int vboot_logic_executed(void) /* Post-RAM stages are "after the romstage" */ return !ENV_ROMSTAGE_OR_BEFORE; } else { - dead_code(); + dead_code(_in_vboot_misc_h); } } From deeccbf4e96de1cd4ed136f865b96a90db374886 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 4 Apr 2020 12:26:35 +0200 Subject: [PATCH 0812/1463] Drop explicit NULL initializations from `device_operations` Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/device/azalia_device.c | 1 - src/device/cardbus_device.c | 2 -- src/device/hypertransport.c | 2 -- src/device/pci_device.c | 4 ---- src/device/pciexp_device.c | 2 -- src/device/pcix_device.c | 2 -- src/drivers/aspeed/ast2050/ast2050.c | 1 - src/drivers/dec/21143/21143.c | 1 - src/drivers/emulation/qemu/bochs.c | 1 - src/drivers/emulation/qemu/cirrus.c | 1 - src/drivers/intel/i210/i210.c | 2 -- src/drivers/net/atl1e.c | 1 - src/drivers/net/ne2k.c | 2 -- src/drivers/net/r8168.c | 1 - src/drivers/ricoh/rce822/rce822.c | 1 - src/drivers/siemens/nc_fpga/nc_fpga.c | 2 -- src/drivers/sil/3114/sil_sata.c | 1 - src/drivers/uart/oxpcie.c | 1 - src/drivers/xgi/z9s/z9s.c | 1 - src/mainboard/emulation/qemu-i440fx/mainboard.c | 1 - src/mainboard/emulation/qemu-i440fx/northbridge.c | 2 -- src/mainboard/emulation/qemu-q35/mainboard.c | 1 - src/northbridge/amd/agesa/family15tn/iommu.c | 2 -- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 -- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 -- src/northbridge/amd/pi/00630F01/iommu.c | 2 -- src/northbridge/amd/pi/00630F01/northbridge.c | 3 --- src/northbridge/amd/pi/00660F01/northbridge.c | 3 --- src/northbridge/amd/pi/00730F01/iommu.c | 2 -- src/northbridge/amd/pi/00730F01/northbridge.c | 3 --- src/northbridge/intel/e7505/northbridge.c | 3 --- src/northbridge/intel/gm45/gma.c | 2 -- src/northbridge/intel/gm45/northbridge.c | 2 -- src/northbridge/intel/haswell/gma.c | 2 -- src/northbridge/intel/haswell/minihd.c | 1 - src/northbridge/intel/haswell/northbridge.c | 4 ---- src/northbridge/intel/i440bx/northbridge.c | 5 ----- src/northbridge/intel/i945/gma.c | 4 ---- src/northbridge/intel/i945/northbridge.c | 4 ---- src/northbridge/intel/ironlake/gma.c | 2 -- src/northbridge/intel/ironlake/northbridge.c | 4 ---- src/northbridge/intel/pineview/gma.c | 3 --- src/northbridge/intel/sandybridge/gma.c | 2 -- src/northbridge/intel/sandybridge/northbridge.c | 4 ---- src/soc/amd/picasso/northbridge.c | 2 -- src/soc/amd/stoneyridge/northbridge.c | 2 -- src/soc/cavium/cn81xx/ecam0.c | 2 -- src/soc/cavium/cn81xx/soc.c | 1 - src/soc/intel/apollolake/chip.c | 3 --- src/soc/intel/baytrail/chip.c | 3 --- src/soc/intel/baytrail/emmc.c | 2 -- src/soc/intel/baytrail/hda.c | 2 -- src/soc/intel/baytrail/lpe.c | 2 -- src/soc/intel/baytrail/lpss.c | 2 -- src/soc/intel/baytrail/northcluster.c | 5 ----- src/soc/intel/baytrail/sata.c | 1 - src/soc/intel/baytrail/sd.c | 2 -- src/soc/intel/baytrail/southcluster.c | 1 - src/soc/intel/braswell/chip.c | 2 -- src/soc/intel/braswell/lpe.c | 2 -- src/soc/intel/braswell/lpss.c | 2 -- src/soc/intel/braswell/southcluster.c | 1 - src/soc/intel/denverton_ns/chip.c | 1 - src/soc/intel/denverton_ns/csme_ie_kt.c | 2 -- src/soc/intel/denverton_ns/npk.c | 1 - src/soc/intel/denverton_ns/pmc.c | 1 - src/soc/intel/denverton_ns/sata.c | 1 - src/soc/intel/denverton_ns/xhci.c | 1 - src/soc/intel/xeon_sp/cpx/chip.c | 1 - src/soc/intel/xeon_sp/skx/chip.c | 1 - src/soc/intel/xeon_sp/uncore.c | 3 --- src/soc/nvidia/tegra124/soc.c | 1 - src/soc/nvidia/tegra210/soc.c | 1 - src/soc/rockchip/rk3288/soc.c | 1 - src/soc/samsung/exynos5250/cpu.c | 1 - src/soc/samsung/exynos5420/cpu.c | 1 - src/southbridge/amd/agesa/hudson/hda.c | 1 - src/southbridge/amd/agesa/hudson/ide.c | 1 - src/southbridge/amd/agesa/hudson/sata.c | 1 - src/southbridge/amd/agesa/hudson/sd.c | 1 - src/southbridge/amd/agesa/hudson/usb.c | 1 - src/southbridge/amd/cimx/sb800/late.c | 7 ------- src/southbridge/amd/pi/hudson/hda.c | 1 - src/southbridge/amd/pi/hudson/ide.c | 1 - src/southbridge/amd/pi/hudson/sata.c | 1 - src/southbridge/amd/pi/hudson/sd.c | 1 - src/southbridge/amd/pi/hudson/usb.c | 1 - src/southbridge/intel/bd82x6x/azalia.c | 1 - src/southbridge/intel/bd82x6x/sata.c | 1 - src/southbridge/intel/bd82x6x/usb_ehci.c | 1 - src/southbridge/intel/bd82x6x/usb_xhci.c | 1 - src/southbridge/intel/i82371eb/ide.c | 4 ---- src/southbridge/intel/i82371eb/isa.c | 1 - src/southbridge/intel/i82371eb/smbus.c | 1 - src/southbridge/intel/i82371eb/usb.c | 2 -- src/southbridge/intel/i82801dx/ac97.c | 2 -- src/southbridge/intel/i82801dx/ide.c | 1 - src/southbridge/intel/i82801dx/usb.c | 1 - src/southbridge/intel/i82801dx/usb2.c | 1 - src/southbridge/intel/i82801gx/ac97.c | 2 -- src/southbridge/intel/i82801gx/azalia.c | 1 - src/southbridge/intel/i82801gx/ide.c | 1 - src/southbridge/intel/i82801gx/nic.c | 1 - src/southbridge/intel/i82801gx/sata.c | 1 - src/southbridge/intel/i82801gx/usb.c | 1 - src/southbridge/intel/i82801gx/usb_ehci.c | 1 - src/southbridge/intel/i82801ix/hdaudio.c | 1 - src/southbridge/intel/i82801ix/sata.c | 1 - src/southbridge/intel/i82801ix/thermal.c | 1 - src/southbridge/intel/i82801ix/usb_ehci.c | 1 - src/southbridge/intel/i82801jx/hdaudio.c | 1 - src/southbridge/intel/i82801jx/sata.c | 1 - src/southbridge/intel/i82801jx/thermal.c | 1 - src/southbridge/intel/i82801jx/usb_ehci.c | 1 - src/southbridge/intel/i82870/ioapic.c | 1 - src/southbridge/intel/ibexpeak/azalia.c | 1 - src/southbridge/intel/ibexpeak/sata.c | 1 - src/southbridge/intel/ibexpeak/thermal.c | 1 - src/southbridge/intel/ibexpeak/usb_ehci.c | 1 - src/southbridge/intel/lynxpoint/azalia.c | 1 - src/southbridge/intel/lynxpoint/sata.c | 1 - src/southbridge/intel/lynxpoint/usb_ehci.c | 1 - src/southbridge/ti/pci1x2x/pci1x2x.c | 1 - 123 files changed, 207 deletions(-) diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 36a70f9ec7..152bde4fd4 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -251,6 +251,5 @@ struct device_operations default_azalia_audio_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_audio_init, - .scan_bus = 0, .ops_pci = &azalia_audio_pci_ops, }; diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index e56202a1ed..b3dc669892 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -157,8 +157,6 @@ struct device_operations default_cardbus_ops_bus = { .read_resources = cardbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, - .init = 0, .scan_bus = pci_scan_bridge, - .enable = 0, .reset_bus = pci_bus_reset, }; diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 4256550747..7815415a21 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -495,9 +495,7 @@ struct device_operations default_ht_ops_bus = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, .scan_bus = ht_scan_bridge, - .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &ht_bus_ops_pci, }; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 0099470160..02cb5addfb 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -761,8 +761,6 @@ struct device_operations default_pci_ops_dev = { .acpi_fill_ssdt = pci_rom_ssdt, #endif .init = pci_dev_init, - .scan_bus = 0, - .enable = 0, .ops_pci = &pci_dev_ops_pci, }; @@ -775,9 +773,7 @@ struct device_operations default_pci_ops_bus = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, .scan_bus = pci_scan_bridge, - .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &pci_bus_ops_pci, }; diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 1a4854d381..07d559ac11 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -502,9 +502,7 @@ struct device_operations default_pciexp_ops_bus = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, .scan_bus = pciexp_scan_bridge, - .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &pciexp_bus_ops_pci, }; diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index 32ad16e51f..88f58b4995 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -123,9 +123,7 @@ struct device_operations default_pcix_ops_bus = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, .scan_bus = pcix_scan_bridge, - .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &pcix_bus_ops_pci, }; diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 8bc73078c7..4230146b0c 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -67,7 +67,6 @@ static struct device_operations aspeed_ast2050_ops = { .set_resources = aspeed_ast2050_set_resources, .enable_resources = pci_dev_enable_resources, .init = aspeed_ast2050_init, - .scan_bus = 0, }; static const struct pci_driver aspeed_ast2050_driver __pci_driver = { diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 0230935752..ff64cf3490 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -43,7 +43,6 @@ static struct device_operations dec_21143_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = dec_21143_enable, - .scan_bus = 0, }; static const struct pci_driver dec_21143_driver __pci_driver = { diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index d9e4ce1d6e..8d08ac1b4c 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -140,7 +140,6 @@ static struct device_operations qemu_graph_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = bochs_init, - .scan_bus = 0, }; static const struct pci_driver qemu_stdvga_driver __pci_driver = { diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 6b1968c31d..4f03578438 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -340,7 +340,6 @@ static struct device_operations qemu_cirrus_graph_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = cirrus_init, - .scan_bus = 0, }; static const struct pci_driver qemu_cirrus_driver __pci_driver = { diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 232a826b4c..cb2414f30c 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -228,8 +228,6 @@ static struct device_operations i210_ops = { .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = init, - .scan_bus = 0, - .ops_pci = 0, }; static const unsigned short i210_device_ids[] = { 0x1537, 0x1538, 0x1533, 0 }; diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 51470b0a78..5cc70ceddd 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -162,7 +162,6 @@ static struct device_operations atl1e_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = atl1e_init, - .scan_bus = 0, }; static const struct pci_driver atl1e_driver __pci_driver = { diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index b1d72de084..620dab952e 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -317,8 +317,6 @@ static struct device_operations ne2k_ops = { .read_resources = read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, }; static const struct pci_driver ne2k_driver __pci_driver = { diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index c764b433b6..6e9437005d 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -372,7 +372,6 @@ static struct device_operations r8168_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = r8168_init, - .scan_bus = 0, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = r8168_net_acpi_name, .acpi_fill_ssdt = r8168_net_fill_ssdt, diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index fd425824c0..08e328da72 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -58,7 +58,6 @@ static struct device_operations rce822_ops = { .enable_resources = pci_dev_enable_resources, .init = rce822_init, .enable = rce822_enable, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 355e0f90a8..b305a8c848 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -158,8 +158,6 @@ static struct device_operations nc_fpga_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = nc_fpga_init, - .scan_bus = 0, - .ops_pci = 0, }; static const unsigned short nc_fpga_device_ids[] = { 0x4080, 0x4091, 0 }; diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index c38e642016..a249181ea7 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -38,7 +38,6 @@ static struct device_operations si_sata_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = si_sata_init, - .scan_bus = 0, }; static const struct pci_driver si_sata_driver __pci_driver = { diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 999c6baec9..60b524576e 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -52,7 +52,6 @@ static struct device_operations oxford_oxpcie_ops = { .set_resources = oxford_oxpcie_set_resources, .enable_resources = pci_dev_enable_resources, .init = oxford_oxpcie_enable, - .scan_bus = 0, }; static const struct pci_driver oxford_oxpcie_driver __pci_driver = { diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index 62c80aa271..c0aa3b3d91 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -50,7 +50,6 @@ static struct device_operations xgi_z9s_ops = { .set_resources = xgi_z9s_set_resources, .enable_resources = pci_dev_enable_resources, .init = xgi_z9s_init, - .scan_bus = 0, }; static const struct pci_driver xgi_z9s_driver __pci_driver = { diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 5e9b3208c6..751035ec34 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -36,7 +36,6 @@ static struct device_operations nb_operations = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = qemu_nb_init, - .ops_pci = 0, }; static const struct pci_driver nb_driver __pci_driver = { diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 38ab9df71b..e5df0168c0 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -236,8 +236,6 @@ static const char *qemu_acpi_name(const struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = cpu_pci_domain_read_resources, .set_resources = cpu_pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, #if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = qemu_get_smbios_data, diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 6bb99cd24d..460864aac1 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -55,7 +55,6 @@ static struct device_operations nb_operations = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = qemu_nb_init, - .ops_pci = 0, }; static const struct pci_driver nb_driver __pci_driver = { diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index a7bf958865..8719443c63 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -56,8 +56,6 @@ static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c5f649e91f..eb13e9655b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -563,8 +563,6 @@ static struct device_operations northbridge_operations = { .init = DEVICE_NOOP, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .enable = 0, - .ops_pci = 0, }; static const struct pci_driver family15_northbridge __pci_driver = { diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d9c3c36c25..c9a0b13143 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -562,8 +562,6 @@ static struct device_operations northbridge_operations = { .init = DEVICE_NOOP, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .enable = 0, - .ops_pci = 0, }; static const struct pci_driver family16_northbridge __pci_driver = { diff --git a/src/northbridge/amd/pi/00630F01/iommu.c b/src/northbridge/amd/pi/00630F01/iommu.c index 77eea90769..970e7592bc 100644 --- a/src/northbridge/amd/pi/00630F01/iommu.c +++ b/src/northbridge/amd/pi/00630F01/iommu.c @@ -56,8 +56,6 @@ static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 30c68d80fb..e34cb71149 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -557,8 +557,6 @@ static struct device_operations northbridge_operations = { .init = DEVICE_NOOP, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .enable = 0, - .ops_pci = 0, }; static const struct pci_driver family15_northbridge __pci_driver = { @@ -775,7 +773,6 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, - .init = NULL, .scan_bus = pci_domain_scan_bus, }; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 44ff37003c..74a5553a96 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -547,8 +547,6 @@ static struct device_operations northbridge_operations = { .init = northbridge_init, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .enable = 0, - .ops_pci = 0, }; static const struct pci_driver family15_northbridge __pci_driver = { @@ -784,7 +782,6 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, - .init = NULL, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index a9f6f9772a..99233025b3 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -46,8 +46,6 @@ static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 0a07dfa1d5..9f55596433 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -777,8 +777,6 @@ static struct device_operations northbridge_operations = { .init = northbridge_init, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .enable = 0, - .ops_pci = 0, }; static const struct pci_driver family16_northbridge __pci_driver = { @@ -1048,7 +1046,6 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, - .init = NULL, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 074f63adaf..8dd701b9f2 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -80,8 +80,6 @@ static struct pci_operations intel_pci_ops = { static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci = &intel_pci_ops, }; @@ -96,7 +94,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 0bbd3d532c..436fb9a10a 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -267,8 +267,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, .write_acpi_tables = gma_write_acpi_tables, diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 9484cd9fab..d4a4828ab6 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -229,7 +229,6 @@ void northbridge_write_smram(u8 smram) static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .enable_resources = NULL, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, @@ -242,7 +241,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 4c11bd1c64..8c28c53a3f 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -565,8 +565,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, - .scan_bus = NULL, - .enable = NULL, .ops_pci = &gma_pci_ops, .write_acpi_tables = gma_write_acpi_tables, }; diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 5a1e7a8ef9..9cd7ad4889 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -106,7 +106,6 @@ static struct device_operations minihd_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = minihd_init, - .scan_bus = NULL, .ops_pci = &minihd_pci_ops, }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4e16ca06e3..b764aadb30 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -92,8 +92,6 @@ static const char *northbridge_acpi_name(const struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, .acpi_name = northbridge_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, @@ -477,7 +475,6 @@ static struct device_operations mc_ops = { .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, - .scan_bus = NULL, .ops_pci = &intel_pci_ops, }; @@ -500,7 +497,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = NULL, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index d23a8436f8..1d0251f0ce 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -31,8 +31,6 @@ static struct device_operations northbridge_operations = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = 0, - .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { @@ -82,8 +80,6 @@ static void i440bx_domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = i440bx_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, }; @@ -97,7 +93,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index f5a964ab82..252d984d2b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -816,8 +816,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, - .scan_bus = 0, - .enable = 0, .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, @@ -830,8 +828,6 @@ static struct device_operations gma_func1_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func1_init, - .scan_bus = 0, - .enable = 0, .ops_pci = &gma_pci_ops, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 16cf5e6ae2..17b790740e 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -167,8 +167,6 @@ void northbridge_write_smram(u8 smram) static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, .acpi_name = northbridge_acpi_name, }; @@ -196,7 +194,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = generate_cpu_entries, - .scan_bus = 0, .ops_pci = &intel_pci_ops, }; @@ -216,7 +213,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 6dbc156b98..42bf7f9507 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -257,8 +257,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, .ops_pci = &gma_pci_ops, .write_acpi_tables = gma_write_acpi_tables, }; diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4637175ea1..b04344f17e 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -105,8 +105,6 @@ static const char *northbridge_acpi_name(const struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = northbridge_acpi_name, @@ -256,7 +254,6 @@ static struct device_operations mc_ops = { .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, - .scan_bus = 0, .ops_pci = &intel_pci_ops, }; @@ -271,7 +268,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index c0962d78f3..39ce5e6861 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -326,10 +326,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = NULL, .init = gma_func0_init, - .scan_bus = NULL, - .enable = NULL, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, .write_acpi_tables = gma_write_acpi_tables, diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b68e705b32..5c4f548f99 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -699,8 +699,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .scan_bus = NULL, - .enable = NULL, .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ff5d7f27ba..6ec36f7343 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -245,8 +245,6 @@ static const char *northbridge_acpi_name(const struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_name = northbridge_acpi_name, @@ -444,7 +442,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .scan_bus = NULL, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt = generate_cpu_entries, }; @@ -466,7 +463,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, }; static void enable_dev(struct device *dev) diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 20589a95e3..b6e5d5c8a1 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -205,8 +205,6 @@ static struct device_operations northbridge_operations = { .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .enable = 0, - .ops_pci = 0, }; static const struct pci_driver family15_northbridge __pci_driver = { diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index afcd49824b..b853d5f287 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -358,8 +358,6 @@ static struct device_operations northbridge_operations = { .init = northbridge_init, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .enable = 0, - .ops_pci = 0, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 1f2ba843c6..777cd10967 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -320,8 +320,6 @@ static void ecam0_init(struct device *dev) } struct device_operations pci_domain_ops_ecam0 = { - .set_resources = NULL, - .enable_resources = NULL, .read_resources = ecam0_read_resources, .init = ecam0_init, .scan_bus = pci_domain_scan_bus, diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 02b7da6140..9312593fe6 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -394,7 +394,6 @@ static struct device_operations soc_ops = { .enable_resources = DEVICE_NOOP, .init = soc_init, .final = soc_final, - .scan_bus = NULL, }; static void enable_soc_dev(struct device *dev) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ee533bb743..2c8737f654 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -214,8 +214,6 @@ static void pci_domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, .acpi_name = &soc_acpi_name, }; @@ -225,7 +223,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, - .scan_bus = NULL, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index f65d4f251c..10bb245581 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -28,8 +28,6 @@ static void pci_domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, }; @@ -38,7 +36,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = baytrail_init_cpus, - .scan_bus = NULL, }; diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 8994e43af8..885bc0fbb1 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -59,8 +59,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = emmc_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index e8be1e2327..45430070d2 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -100,8 +100,6 @@ static const struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = hda_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index e34af1e2d7..a2c71e62d8 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -173,8 +173,6 @@ static const struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpe_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 71b6dacbb5..9cc8025957 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -171,8 +171,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpss_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 0b61fe7d05..38bbfc27ad 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -137,11 +137,6 @@ static void nc_read_resources(struct device *dev) static struct device_operations nc_ops = { .read_resources = nc_read_resources, .acpi_fill_ssdt = generate_cpu_entries, - .set_resources = NULL, - .enable_resources = NULL, - .init = NULL, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 33fb04316b..f56975fd39 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -212,7 +212,6 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index dd2b61ac7d..7c587650f9 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -50,8 +50,6 @@ static const struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sd_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index be58f42a58..06cb2619d5 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -523,7 +523,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = acpi_write_hpet, - .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 90ee850cd9..d63bb77dca 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -31,8 +31,6 @@ static void pci_domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, }; diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 85e698c535..cf61120895 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -197,8 +197,6 @@ static const struct device_operations device_ops = { .set_resources = lpe_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpe_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index b5c4e3d95c..24377af311 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -162,8 +162,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpss_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index aa054d6801..c166371091 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -572,7 +572,6 @@ void southcluster_enable_dev(struct device *dev) static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = NULL, .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index c41d857d88..d21f053b41 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -46,7 +46,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = denverton_init_cpus, - .scan_bus = NULL, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 73a680e2b9..a8d081af4c 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -69,8 +69,6 @@ static struct device_operations csme_ie_kt_ops = { .read_resources = pci_csme_ie_kt_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, - .init = 0, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index ce57686e01..c22a5c2d40 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -37,7 +37,6 @@ static struct device_operations pmc_ops = { .read_resources = pci_npk_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, .init = npk_init, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 7027e1ed26..4094b0953a 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -104,7 +104,6 @@ static struct device_operations pmc_ops = { .read_resources = pci_pmc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, .init = pmc_init, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 9097526619..9ee6254424 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -65,7 +65,6 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index 7c6e88951a..be961de332 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -39,7 +39,6 @@ static struct device_operations usb_xhci_ops = { .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, .enable = pci_dev_enable_resources, - .scan_bus = 0, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index e4063dc99d..ef18e45e9b 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -35,7 +35,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpx_init_cpus, - .scan_bus = NULL, }; static void chip_enable_dev(struct device *dev) diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 764e70fea6..90ae0252e2 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -486,7 +486,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = xeon_sp_init_cpus, - .scan_bus = NULL, #if CONFIG(HAVE_ACPI_TABLES) /* defined in src/soc/intel/common/block/acpi/acpi.c */ .acpi_fill_ssdt = generate_cpu_entries, diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index f549eecd85..670d62a5a5 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -287,9 +287,6 @@ static struct device_operations mmapvtd_ops = { .enable_resources = pci_dev_enable_resources, .init = mmapvtd_init, .ops_pci = &soc_pci_ops, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_inject_dsdt = NULL, -#endif }; static const unsigned short mmapvtd_ids[] = { diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index f2e2c0a00c..d291af8ad6 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -57,7 +57,6 @@ static struct device_operations soc_ops = { .set_resources = DEVICE_NOOP, .enable_resources = soc_enable, .init = soc_init, - .scan_bus = 0, }; static void enable_tegra124_dev(struct device *dev) diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index c29a810ee6..22b6dfe497 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -65,7 +65,6 @@ static struct device_operations soc_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = NULL, }; static void enable_tegra210_dev(struct device *dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 09cd7bcf87..84fa691b2b 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -38,7 +38,6 @@ static struct device_operations soc_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .init = soc_init, - .scan_bus = 0, }; static void enable_rk3288_dev(struct device *dev) diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 4523964775..989af5962c 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -127,7 +127,6 @@ static struct device_operations cpu_ops = { .set_resources = DEVICE_NOOP, .enable_resources = cpu_enable, .init = cpu_init, - .scan_bus = 0, }; static void enable_exynos5250_dev(struct device *dev) diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index bcc6878de7..cc6b0480a9 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -157,7 +157,6 @@ static struct device_operations cpu_ops = { .set_resources = DEVICE_NOOP, .enable_resources = cpu_enable, .init = cpu_init, - .scan_bus = 0, }; static void enable_exynos5420_dev(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index d03694c2ab..40f1fa6ef2 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -20,7 +20,6 @@ static struct device_operations hda_audio_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = hda_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c index 76e5ead8e4..f8765c7dd7 100644 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ b/src/southbridge/amd/agesa/hudson/ide.c @@ -19,7 +19,6 @@ static struct device_operations ide_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index fcf27c63c8..af4b2a523c 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -49,7 +49,6 @@ static struct device_operations sata_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index 3d5eb29f50..4bd08a912d 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -43,7 +43,6 @@ static struct device_operations sd_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sd_init, - .scan_bus = 0, }; static const struct pci_driver sd_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c index 2657555964..60716c7222 100644 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ b/src/southbridge/amd/agesa/hudson/usb.c @@ -20,7 +20,6 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index babc21ef3f..e4a1795ab4 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -170,7 +170,6 @@ static struct device_operations sata_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ahci_raid_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -195,8 +194,6 @@ static struct device_operations usb_ops = { .read_resources = pci_ehci_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -226,8 +223,6 @@ static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -242,8 +237,6 @@ static struct device_operations gec_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index ef2a341ea6..f49e5fa6fe 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -26,7 +26,6 @@ static struct device_operations hda_audio_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = hda_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/ide.c b/src/southbridge/amd/pi/hudson/ide.c index 76e5ead8e4..f8765c7dd7 100644 --- a/src/southbridge/amd/pi/hudson/ide.c +++ b/src/southbridge/amd/pi/hudson/ide.c @@ -19,7 +19,6 @@ static struct device_operations ide_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 4a210d709d..ba1c54fe00 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -49,7 +49,6 @@ static struct device_operations sata_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index 0a9baffdda..0dbef81162 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -44,7 +44,6 @@ static struct device_operations sd_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sd_init, - .scan_bus = 0, }; static const struct pci_driver sd_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index c882556b75..12b0754896 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -20,7 +20,6 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 316fafcab4..0466d3109c 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -333,7 +333,6 @@ static struct device_operations azalia_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, .ops_pci = &azalia_pci_ops, .acpi_name = azalia_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index e09e07246b..e04f3bacc9 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -246,7 +246,6 @@ static struct device_operations sata_ops = { .acpi_fill_ssdt = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, .ops_pci = &sata_pci_ops, .acpi_name = sata_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 1d7120dc09..b9069376d7 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -97,7 +97,6 @@ static struct device_operations usb_ehci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, .ops_pci = &lops_pci, .acpi_name = usb_ehci_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 8696d59abf..a562db2e52 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -53,7 +53,6 @@ static struct device_operations usb_xhci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, - .scan_bus = 0, .ops_pci = &xhci_pci_ops, .acpi_name = xhci_acpi_name, }; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index b21887f8d9..40e74e93ab 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -146,8 +146,6 @@ static const struct device_operations ide_ops_fb_sb = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init_i82371fb_sb, - .scan_bus = 0, - .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; @@ -157,8 +155,6 @@ static const struct device_operations ide_ops_ab_eb_mb = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init_i82371ab_eb_mb, - .scan_bus = 0, - .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 7fe243f1d5..bb876115a3 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -135,7 +135,6 @@ static const struct device_operations isa_ops = { #endif .init = isa_init, .scan_bus = scan_static_bus, - .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index f9690c34ad..d74879d0b6 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -113,7 +113,6 @@ static const struct device_operations smbus_ops = { .read_resources = pwrmgt_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, .scan_bus = scan_smbus, .enable = pwrmgt_enable, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index d4fffa4619..4fcd26cc98 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -37,8 +37,6 @@ static const struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, - .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index b0fda29665..9e6d51a500 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -241,7 +241,6 @@ static struct device_operations ac97_audio_ops = { .enable_resources = pci_dev_enable_resources, .enable = i82801dx_enable, .init = ac97_audio_init, - .scan_bus = 0, }; static struct device_operations ac97_modem_ops = { @@ -250,7 +249,6 @@ static struct device_operations ac97_modem_ops = { .enable_resources = pci_dev_enable_resources, .enable = i82801dx_enable, .init = ac97_modem_init, - .scan_bus = 0, }; /* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c index 0c8408ca99..8150de775e 100644 --- a/src/southbridge/intel/i82801dx/ide.c +++ b/src/southbridge/intel/i82801dx/ide.c @@ -47,7 +47,6 @@ static struct device_operations ide_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c index f02d70808e..68dc1a6c3c 100644 --- a/src/southbridge/intel/i82801dx/usb.c +++ b/src/southbridge/intel/i82801dx/usb.c @@ -24,7 +24,6 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c index 53fece054a..cc25d23a98 100644 --- a/src/southbridge/intel/i82801dx/usb2.c +++ b/src/southbridge/intel/i82801dx/usb2.c @@ -25,7 +25,6 @@ static struct device_operations usb2_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb2_init, - .scan_bus = 0, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index ad7c636312..3833e72fdb 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -243,7 +243,6 @@ static struct device_operations ac97_audio_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ac97_audio_init, - .scan_bus = 0, .enable = i82801gx_enable, .ops_pci = &ac97_pci_ops, }; @@ -253,7 +252,6 @@ static struct device_operations ac97_modem_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ac97_modem_init, - .scan_bus = 0, .enable = i82801gx_enable, .ops_pci = &ac97_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 737a2db6c1..a701c47a81 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -300,7 +300,6 @@ static struct device_operations azalia_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, .enable = i82801gx_enable, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 16236c1ffb..b6b30efea9 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -89,7 +89,6 @@ static struct device_operations ide_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, .enable = i82801gx_enable, .ops_pci = &ide_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/nic.c b/src/southbridge/intel/i82801gx/nic.c index 899d1d23d8..498ed3ec27 100644 --- a/src/southbridge/intel/i82801gx/nic.c +++ b/src/southbridge/intel/i82801gx/nic.c @@ -17,7 +17,6 @@ static struct device_operations nic_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = nic_init, - .scan_bus = 0, }; /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 95d0482aac..533cfef9a4 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -227,7 +227,6 @@ static struct device_operations sata_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, - .scan_bus = 0, .enable = i82801gx_enable, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 0e85b1c1eb..8a8b58cb88 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -39,7 +39,6 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, .enable = i82801gx_enable, .ops_pci = &usb_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 399b166c37..0efae6daca 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -71,7 +71,6 @@ static struct device_operations usb_ehci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, .enable = i82801gx_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 364ffe4e56..e5b790619f 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -283,7 +283,6 @@ static struct device_operations azalia_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index b6b72e3c1b..898117304d 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -258,7 +258,6 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index dce393f042..9fd98a12bc 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -46,7 +46,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .scan_bus = 0, .ops_pci = &thermal_pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 14996165be..3ccffd8228 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -52,7 +52,6 @@ static struct device_operations usb_ehci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0d93415501..1711de9ae3 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -283,7 +283,6 @@ static struct device_operations azalia_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 56ed7708e3..9578b9411d 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -252,7 +252,6 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 28d4c7b688..ab5560f69f 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -46,7 +46,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .scan_bus = 0, .ops_pci = &thermal_pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 551aa500df..03b314a10d 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -54,7 +54,6 @@ static struct device_operations usb_ehci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index c7b189ac77..9947cbd5e1 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -87,7 +87,6 @@ static struct device_operations ioapic_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = p64h2_ioapic_init, - .scan_bus = 0, .enable = p64h2_ioapic_enable, }; diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 8a442a1c68..eb75b1200d 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -308,7 +308,6 @@ static struct device_operations azalia_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index e6fcde60c9..3a7bdb605f 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -229,7 +229,6 @@ static struct device_operations sata_ops = { .init = sata_init, .enable = sata_enable, .acpi_fill_ssdt = sata_fill_ssdt, - .scan_bus = 0, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 3f0b7bf07b..298016f39a 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -40,7 +40,6 @@ static struct device_operations thermal_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .scan_bus = 0, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index f513628802..40ba75811d 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -80,7 +80,6 @@ static struct device_operations usb_ehci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index b24740bb73..cbdd3f6ee9 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -149,7 +149,6 @@ static struct device_operations azalia_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 22be4d169d..922aef0c00 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -321,7 +321,6 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 681d098374..ce81f76f44 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -177,7 +177,6 @@ static struct device_operations usb_ehci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index c07e76439b..df9456e1d4 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -58,7 +58,6 @@ struct device_operations southbridge_ti_pci1x2x_pciops = { .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, .init = ti_pci1x2y_init, - .scan_bus = 0, .ops_pci = &ti_pci1x2y_pci_ops, }; From 92646ea3e3456a0a975775a1f5aa5dc011a9b1b6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 4 Apr 2020 13:43:03 +0200 Subject: [PATCH 0813/1463] sb/intel/i82801gx: Improve code formatting This mainly updates the formatting for the new 96 characters text width. Change-Id: Ia75c3ca7136b0291b3ae82e6a281cc76b75965ca Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40127 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/azalia.c | 19 +++++----------- src/southbridge/intel/i82801gx/early_smbus.c | 6 ++--- src/southbridge/intel/i82801gx/i82801gx.c | 3 +-- src/southbridge/intel/i82801gx/lpc.c | 23 ++++++++------------ src/southbridge/intel/i82801gx/pcie.c | 15 +++++-------- src/southbridge/intel/i82801gx/sata.c | 20 ++++++----------- src/southbridge/intel/i82801gx/smbus.c | 9 ++++---- src/southbridge/intel/i82801gx/smihandler.c | 8 ++----- src/southbridge/intel/i82801gx/usb.c | 2 +- src/southbridge/intel/i82801gx/usb_ehci.c | 3 +-- 10 files changed, 38 insertions(+), 70 deletions(-) diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index a701c47a81..4a2b50e4d4 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -30,9 +30,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -100,9 +98,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) static int wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { @@ -116,9 +112,8 @@ static int wait_for_ready(u8 *base) } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) @@ -130,14 +125,12 @@ static int wait_for_valid(u8 *base) reg32 |= (1 << 0) | (1 << 1); write32(base + 0x68, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index ea639f9fc4..3a1369a34b 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -21,8 +21,7 @@ int smbus_enable_iobar(uintptr_t base) return -1; /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -48,8 +47,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); } -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) { return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); } diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 5df36ddc81..1a5366fe87 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -61,8 +61,7 @@ void i82801gx_enable(struct device *dev) /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); /* Hide this device if possible */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 8949e8d7e7..c24460cd81 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -52,8 +52,7 @@ static void i82801gx_enable_ioapic(struct device *dev) static void i82801gx_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); } /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control @@ -129,9 +128,7 @@ static void i82801gx_gpi_routing(struct device *dev) config_t *config = dev->chip_info; u32 reg32 = 0; - /* An array would be much nicer here, or some - * other method of doing this. - */ + /* An array would be much nicer here, or some other method of doing this. */ reg32 |= (config->gpi0_routing & 0x03) << 0; reg32 |= (config->gpi1_routing & 0x03) << 2; reg32 |= (config->gpi2_routing & 0x03) << 4; @@ -411,8 +408,7 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) @@ -675,14 +671,13 @@ static struct device_operations device_ops = { .final = lpc_final, }; -/* 27b0: 82801GH (ICH7 DH) */ -/* 27b8: 82801GB/GR (ICH7/ICH7R) */ -/* 27b9: 82801GBM/GU (ICH7-M/ICH7-U) */ -/* 27bc: 82NM10 (NM10) */ -/* 27bd: 82801GHM (ICH7-M DH) */ - static const unsigned short pci_device_ids[] = { - 0x27b0, 0x27b8, 0x27b9, 0x27bc, 0x27bd, 0 + 0x27b0, /* 82801GH (ICH7 DH) */ + 0x27b8, /* 82801GB/GR (ICH7/ICH7R) */ + 0x27b9, /* 82801GBM/GU (ICH7-M/ICH7-U) */ + 0x27bc, /* 82NM10 (NM10) */ + 0x27bd, /* 82801GHM (ICH7-M DH) */ + 0 }; static const struct pci_driver ich7_lpc __pci_driver = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 7efaca9130..4398ad56b0 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -129,8 +129,7 @@ static void root_port_init_config(struct device *dev) rp = root_port_number(dev); if (rp > rpc.num_ports) { - printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", - rp, rpc.num_ports); + printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", rp, rpc.num_ports); return; } @@ -170,8 +169,7 @@ static void root_port_commit_config(struct device *dev) int coalesce = 0; if (dev->chip_info != NULL) { - struct southbridge_intel_i82801gx_config *config - = dev->chip_info; + struct southbridge_intel_i82801gx_config *config = dev->chip_info; coalesce = config->pcie_port_coalesce; } @@ -184,16 +182,14 @@ static void root_port_commit_config(struct device *dev) pcie_dev = rpc.ports[i]; if (pcie_dev == NULL) { - printk(BIOS_ERR, "Root Port %d device is NULL?\n", - i + 1); + printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1); continue; } if (pcie_dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", - dev_path(pcie_dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(pcie_dev)); /* Disable this device if possible */ i82801gx_enable(pcie_dev); @@ -222,8 +218,7 @@ static void root_port_commit_config(struct device *dev) } } - printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", - rpc.orig_rpfn, rpc.new_rpfn); + printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn); RCBA32(RPFN) = rpc.new_rpfn; } diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 533cfef9a4..4b4511c4d8 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -28,8 +28,7 @@ static u8 get_ich7_sata_ports(void) case 0x27bc: return 0x3; default: - printk(BIOS_ERR, - "i82801gx_sata: error: cannot determine port config\n"); + printk(BIOS_ERR, "i82801gx_sata: error: cannot determine port config\n"); return 0; } } @@ -54,11 +53,9 @@ void sata_enable(struct device *dev) & AHCI_UNSUPPORTED); if (!ahci_supported) { - /* Fallback to IDE PLAIN for sata for the rest of the - initialization */ + /* Fallback to IDE PLAIN for sata for the rest of the initialization */ config->sata_mode = SATA_MODE_IDE_PLAIN; - printk(BIOS_DEBUG, - "AHCI not supported, falling back to plain mode.\n"); + printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n"); } } @@ -66,12 +63,10 @@ void sata_enable(struct device *dev) if (config->sata_mode == SATA_MODE_AHCI) { /* Set map to ahci */ pci_write_config8(dev, SATA_MAP, - (pci_read_config8(dev, SATA_MAP) - & ~0xc3) | 0x40); + (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); } else { /* Set map to ide */ - pci_write_config8(dev, SATA_MAP, - pci_read_config8(dev, SATA_MAP) & ~0xc3); + pci_write_config8(dev, SATA_MAP, pci_read_config8(dev, SATA_MAP) & ~0xc3); } /* At this point, the new pci id will appear on the bus */ } @@ -143,8 +138,7 @@ static void sata_init(struct device *dev) struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); if (ahci_res != NULL) /* write AHCI GHC_PI register */ - write32(res2mmio(ahci_res, 0xc, 0), - config->sata_ports_implemented); + write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented); break; default: case SATA_MODE_IDE_PLAIN: @@ -219,7 +213,7 @@ static void sata_init(struct device *dev) } static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index d533b8776a..b6c669af55 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -34,8 +34,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) return do_smbus_write_byte(res->base, device, address, data); } -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, - const u8 *buf) +static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) { u16 device; struct resource *res; @@ -62,9 +61,9 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, + .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write = lsmbus_block_write, }; static struct pci_operations smbus_pci_ops = { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index d19ee1191b..b5642e7b53 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -18,15 +18,11 @@ #include "nvs.h" -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ +/* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ +/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located by coreboot. */ global_nvs_t *gnvs = (global_nvs_t *)0x0; void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 8a8b58cb88..d4b559a37b 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -31,7 +31,7 @@ static void usb_init(struct device *dev) } static struct pci_operations usb_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 0efae6daca..d127496cd6 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -46,8 +46,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl; From 667d8af08adbd4f2154dfb3032698f961b9cfcdd Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 7 Jan 2017 23:46:41 -0600 Subject: [PATCH 0814/1463] mb/google/rambi: use ACPI backlight controls All variants except NINJA have a built-in display. Enables ACPI brightness controls under Windows. Change-Id: I8dd026608de606fa33f28ccb2967f3beb83b3470 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40119 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/rambi/devicetree.cb | 3 +++ src/mainboard/google/rambi/dsdt.asl | 1 + src/mainboard/google/rambi/variants/ninja/overridetree.cb | 3 +++ 3 files changed, 7 insertions(+) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index dc11ec8a91..c7bc0b66f2 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/baytrail + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # SATA port enable mask (2 ports) register "sata_port_map" = "0x1" register "sata_ahci" = "0x1" diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 3a8d1a1a30..347269fa15 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -36,6 +36,7 @@ DefinitionBlock( { //#include #include + #include } /* Dynamic Platform Thermal Framework */ diff --git a/src/mainboard/google/rambi/variants/ninja/overridetree.cb b/src/mainboard/google/rambi/variants/ninja/overridetree.cb index 3f67644d79..47527da2b3 100644 --- a/src/mainboard/google/rambi/variants/ninja/overridetree.cb +++ b/src/mainboard/google/rambi/variants/ninja/overridetree.cb @@ -1,5 +1,8 @@ chip soc/intel/baytrail + # No Built-in IGD Display + register "gfx.ndid" = "0" + register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend From 11cfcdd7842146c6756ffa85667b6e7ef4958031 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 29 Mar 2020 17:01:44 -0500 Subject: [PATCH 0815/1463] mb/google/cyan: Use ACPI backlight contrls Enables ACPI backlight controls under Windows. Test: boot Win 10 on cyan and edgar variants, verify screen backlight controls available and functional. Change-Id: I8976291b5bafaec934d0bfd91fcdab50b381beec Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40120 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/cyan/devicetree.cb | 3 +++ src/mainboard/google/cyan/dsdt.asl | 1 + 2 files changed, 4 insertions(+) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index b13f3f9e90..91e9795f9b 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/braswell + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + ############################################################ # Set the parameters for MemoryInit ############################################################ diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 90dfa37ff5..f9f494093e 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -33,6 +33,7 @@ DefinitionBlock( Device (PCI0) { #include + #include #if CONFIG(BOARD_GOOGLE_TERRA) #include #else From 338c8d4b375d9c405cee9252568f06f75ff05dac Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 16 Jul 2018 20:29:10 -0500 Subject: [PATCH 0816/1463] mb/google/glados: Use ACPI brightness controls Enables ACPI backlight controls under Windows. Test: build/boot chell variant, verify screen backlight controls available and functional under Windows 10. Change-Id: Ida0102ac828254ae195528a8f1de078abed4a491 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40121 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/glados/devicetree.cb | 3 +++ src/mainboard/google/glados/dsdt.asl | 1 + 2 files changed, 4 insertions(+) diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index e9c1cac69c..4e85e21111 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "200" register "gpu_pp_down_delay_ms" = " 50" register "gpu_pp_cycle_delay_ms" = "500" diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 879e888c4e..7e3a1a2cbf 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -35,6 +35,7 @@ DefinitionBlock( { #include #include + #include } // Dynamic Platform Thermal Framework From 205df70eb230cf52f3e8e4379196dd4fd4694fdb Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 20 Apr 2018 14:24:21 -0700 Subject: [PATCH 0817/1463] mb/google/eve: Use ACPI backlight controls Enables backlight control under Windows. Test: build/boot eve, verify screen backlight controls available and functional under Windows 10. Change-Id: Id4477d2ec71aefb4c9d2ead31cd5fd3bfad51981 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40122 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/eve/devicetree.cb | 3 +++ src/mainboard/google/eve/dsdt.asl | 1 + 2 files changed, 4 insertions(+) diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 50f9114913..564b45dfc6 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "100" register "gpu_pp_down_delay_ms" = "500" register "gpu_pp_cycle_delay_ms" = "500" diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index ea0424a219..8b07dabd53 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -39,6 +39,7 @@ DefinitionBlock( { #include #include + #include } } From 210a00872ec037936e8d983ebef6cc3ff56b90ed Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:24 +0200 Subject: [PATCH 0818/1463] src/ec: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/ec/acpi/ec.asl | 16 ++-------------- src/ec/acpi/ec.c | 16 ++-------------- src/ec/acpi/ec.h | 15 ++------------- src/ec/compal/ene932/acpi/ac.asl | 16 ++-------------- src/ec/compal/ene932/acpi/battery.asl | 16 ++-------------- src/ec/compal/ene932/acpi/ec.asl | 15 ++------------- src/ec/compal/ene932/acpi/superio.asl | 15 ++------------- src/ec/compal/ene932/chip.h | 16 ++-------------- src/ec/compal/ene932/ec.c | 16 ++-------------- src/ec/compal/ene932/ec.h | 15 ++------------- src/ec/ec.h | 15 ++------------- src/ec/google/chromeec/acpi/ac.asl | 15 ++------------- src/ec/google/chromeec/acpi/als.asl | 15 ++------------- src/ec/google/chromeec/acpi/battery.asl | 16 ++-------------- src/ec/google/chromeec/acpi/cros_ec.asl | 15 ++------------- src/ec/google/chromeec/acpi/ec.asl | 15 ++------------- src/ec/google/chromeec/acpi/emem.asl | 15 ++------------- .../google/chromeec/acpi/keyboard_backlight.asl | 15 ++------------- src/ec/google/chromeec/acpi/pd.asl | 15 ++------------- src/ec/google/chromeec/acpi/superio.asl | 15 ++------------- src/ec/google/chromeec/acpi/tbmc.asl | 15 ++------------- src/ec/google/chromeec/chip.h | 15 ++------------- src/ec/google/chromeec/crosec_proto.c | 15 ++------------- src/ec/google/chromeec/ec.c | 15 ++------------- src/ec/google/chromeec/ec.h | 15 +++------------ src/ec/google/chromeec/ec_boardid.c | 15 ++------------- src/ec/google/chromeec/ec_i2c.c | 15 ++------------- src/ec/google/chromeec/ec_lpc.c | 15 ++------------- src/ec/google/chromeec/ec_spi.c | 15 ++------------- src/ec/google/chromeec/smihandler.c | 15 ++------------- src/ec/google/chromeec/smm.h | 15 ++------------- src/ec/google/chromeec/switches.c | 15 ++------------- src/ec/google/chromeec/vboot_storage.c | 15 ++------------- src/ec/google/chromeec/vstore.c | 15 ++------------- src/ec/google/common/mec.c | 15 ++------------- src/ec/google/common/mec.h | 15 ++------------- src/ec/google/wilco/acpi/ac.asl | 16 ++-------------- src/ec/google/wilco/acpi/battery.asl | 16 ++-------------- src/ec/google/wilco/acpi/dptf.asl | 16 ++-------------- src/ec/google/wilco/acpi/ec.asl | 16 ++-------------- src/ec/google/wilco/acpi/ec_dev.asl | 15 ++------------- src/ec/google/wilco/acpi/ec_ram.asl | 16 ++-------------- src/ec/google/wilco/acpi/event.asl | 16 ++-------------- src/ec/google/wilco/acpi/lid.asl | 16 ++-------------- src/ec/google/wilco/acpi/platform.asl | 16 ++-------------- src/ec/google/wilco/acpi/privacy.asl | 16 ++-------------- src/ec/google/wilco/acpi/superio.asl | 16 ++-------------- src/ec/google/wilco/acpi/ucsi.asl | 15 ++------------- src/ec/google/wilco/acpi/vbtn.asl | 16 ++-------------- src/ec/google/wilco/boardid.c | 15 ++------------- src/ec/google/wilco/bootblock.c | 15 ++------------- src/ec/google/wilco/bootblock.h | 15 ++------------- src/ec/google/wilco/chip.c | 15 ++------------- src/ec/google/wilco/chip.h | 15 ++------------- src/ec/google/wilco/commands.c | 15 ++------------- src/ec/google/wilco/commands.h | 15 ++------------- src/ec/google/wilco/ec.h | 15 ++------------- src/ec/google/wilco/mailbox.c | 15 ++------------- src/ec/google/wilco/romstage.c | 15 ++------------- src/ec/google/wilco/romstage.h | 15 ++------------- src/ec/google/wilco/smihandler.c | 15 ++------------- src/ec/google/wilco/smm.h | 15 ++------------- src/ec/hp/kbc1126/acpi/ac.asl | 16 ++-------------- src/ec/hp/kbc1126/acpi/battery.asl | 16 ++-------------- src/ec/hp/kbc1126/acpi/ec.asl | 15 ++------------- src/ec/hp/kbc1126/acpi/lid.asl | 15 ++------------- src/ec/hp/kbc1126/chip.h | 16 ++-------------- src/ec/hp/kbc1126/early_init.c | 15 ++------------- src/ec/hp/kbc1126/ec.c | 16 ++-------------- src/ec/hp/kbc1126/ec.h | 16 ++-------------- src/ec/kontron/it8516e/acpi/ec.asl | 15 ++------------- src/ec/kontron/it8516e/acpi/pm_channels.asl | 15 ++------------- src/ec/kontron/it8516e/chip.h | 16 ++-------------- src/ec/kontron/it8516e/ec.c | 15 ++------------- src/ec/kontron/it8516e/ec.h | 15 ++------------- src/ec/kontron/kempld/chip.h | 16 ++-------------- src/ec/kontron/kempld/early_kempld.c | 15 ++------------- src/ec/kontron/kempld/kempld.c | 15 ++------------- src/ec/kontron/kempld/kempld.h | 15 ++------------- src/ec/kontron/kempld/kempld_internal.h | 15 ++------------- src/ec/lenovo/h8/acpi/ac.asl | 16 ++-------------- src/ec/lenovo/h8/acpi/battery.asl | 16 ++-------------- src/ec/lenovo/h8/acpi/beep.asl | 16 ++-------------- src/ec/lenovo/h8/acpi/ec.asl | 16 ++-------------- src/ec/lenovo/h8/acpi/lid.asl | 16 ++-------------- src/ec/lenovo/h8/acpi/sleepbutton.asl | 16 ++-------------- src/ec/lenovo/h8/acpi/systemstatus.asl | 16 ++-------------- src/ec/lenovo/h8/acpi/thermal.asl | 14 ++------------ src/ec/lenovo/h8/acpi/thinkpad.asl | 16 ++-------------- .../lenovo/h8/acpi/thinkpad_bat_thresholds.asl | 16 ++-------------- .../h8/acpi/thinkpad_bat_thresholds_24.asl | 16 ++-------------- .../h8/acpi/thinkpad_bat_thresholds_b0.asl | 16 ++-------------- src/ec/lenovo/h8/bluetooth.c | 15 ++------------- src/ec/lenovo/h8/chip.h | 15 ++------------- src/ec/lenovo/h8/h8.c | 15 ++------------- src/ec/lenovo/h8/h8.h | 15 ++------------- src/ec/lenovo/h8/panic.c | 15 ++------------- src/ec/lenovo/h8/sense.c | 15 ++------------- src/ec/lenovo/h8/ssdt.c | 15 ++------------- src/ec/lenovo/h8/vboot.c | 15 ++------------- src/ec/lenovo/h8/wwan.c | 15 ++------------- src/ec/lenovo/pmh7/chip.h | 15 ++------------- src/ec/lenovo/pmh7/pmh7.c | 15 ++------------- src/ec/lenovo/pmh7/pmh7.h | 15 ++------------- src/ec/purism/librem/acpi/ac.asl | 15 ++------------- src/ec/purism/librem/acpi/battery.asl | 15 ++------------- src/ec/purism/librem/acpi/ec.asl | 15 ++------------- src/ec/quanta/ene_kb3940q/acpi/ac.asl | 16 ++-------------- src/ec/quanta/ene_kb3940q/acpi/battery.asl | 16 ++-------------- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 15 ++------------- src/ec/quanta/ene_kb3940q/acpi/superio.asl | 15 ++------------- src/ec/quanta/ene_kb3940q/chip.h | 16 ++-------------- src/ec/quanta/ene_kb3940q/ec.c | 16 ++-------------- src/ec/quanta/ene_kb3940q/ec.h | 15 ++------------- src/ec/quanta/it8518/acpi/ac.asl | 16 ++-------------- src/ec/quanta/it8518/acpi/battery.asl | 16 ++-------------- src/ec/quanta/it8518/acpi/ec.asl | 15 ++------------- src/ec/quanta/it8518/acpi/superio.asl | 15 ++------------- src/ec/quanta/it8518/chip.h | 16 ++-------------- src/ec/quanta/it8518/ec.c | 16 ++-------------- src/ec/quanta/it8518/ec.h | 15 ++------------- src/ec/roda/it8518/acpi/ac.asl | 15 ++------------- src/ec/roda/it8518/acpi/battery.asl | 15 ++------------- src/ec/roda/it8518/acpi/ec.asl | 15 ++------------- src/ec/roda/it8518/acpi/lid.asl | 15 ++------------- src/ec/roda/it8518/chip.h | 15 ++------------- src/ec/roda/it8518/ec.c | 15 ++------------- src/ec/smsc/mec1308/acpi/ac.asl | 16 ++-------------- src/ec/smsc/mec1308/acpi/battery.asl | 16 ++-------------- src/ec/smsc/mec1308/acpi/ec.asl | 15 ++------------- src/ec/smsc/mec1308/chip.h | 16 ++-------------- src/ec/smsc/mec1308/ec.c | 16 ++-------------- src/ec/smsc/mec1308/ec.h | 15 +++------------ 133 files changed, 268 insertions(+), 1774 deletions(-) diff --git a/src/ec/acpi/ec.asl b/src/ec/acpi/ec.asl index f5b574b196..edb4c30262 100644 --- a/src/ec/acpi/ec.asl +++ b/src/ec/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * ACPI style embedded controller commands diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 24926a7073..5ad49f9a63 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h index 125ee61a9a..0f7f679ea2 100644 --- a/src/ec/acpi/ec.h +++ b/src/ec/acpi/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_ACPI_H #define _EC_ACPI_H diff --git a/src/ec/compal/ene932/acpi/ac.asl b/src/ec/compal/ene932/acpi/ac.asl index 88330ea8fc..5d96945613 100644 --- a/src/ec/compal/ene932/acpi/ac.asl +++ b/src/ec/compal/ene932/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl index 878bcda0ac..2014decdab 100644 --- a/src/ec/compal/ene932/acpi/battery.asl +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 4db43f6e87..fbf533d3f1 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The mainboard must define a PNOT method to handle power diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index 21d291683e..6cbe94f75f 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/ec/compal/ene932/chip.h b/src/ec/compal/ene932/chip.h index 8dedfee83a..1d11b74c4f 100644 --- a/src/ec/compal/ene932/chip.h +++ b/src/ec/compal/ene932/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_COMPAL_ENE932_CHIP_H #define _EC_COMPAL_ENE932_CHIP_H diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index f6691cd692..8eebfa8c3a 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index ba78cdde24..fa3e3dc6e1 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * EC communication interface for COMPAL ENE932 Embedded Controller. diff --git a/src/ec/ec.h b/src/ec/ec.h index 2787b3a752..5b4858b11c 100644 --- a/src/ec/ec.h +++ b/src/ec/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_EC_H #define EC_EC_H diff --git a/src/ec/google/chromeec/acpi/ac.asl b/src/ec/google/chromeec/acpi/ac.asl index 024d4a8ba6..d2061c64a8 100644 --- a/src/ec/google/chromeec/acpi/ac.asl +++ b/src/ec/google/chromeec/acpi/ac.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/google/chromeec/acpi/als.asl b/src/ec/google/chromeec/acpi/als.asl index 26d682de50..99b0cca030 100644 --- a/src/ec/google/chromeec/acpi/als.asl +++ b/src/ec/google/chromeec/acpi/als.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (ALS) { diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 9cf3abd831..562af13b3c 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 5e86a81c2b..3e9b7733b6 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (CREC) { diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 95494eaba7..1b8e128320 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The mainboard must define a PNOT method to handle power diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index cbc125343c..6e98974b75 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * EMEM data may be accessed through port 62/66 or through LPC at 900h. diff --git a/src/ec/google/chromeec/acpi/keyboard_backlight.asl b/src/ec/google/chromeec/acpi/keyboard_backlight.asl index 7cfbabe0d2..839beb3e0b 100644 --- a/src/ec/google/chromeec/acpi/keyboard_backlight.asl +++ b/src/ec/google/chromeec/acpi/keyboard_backlight.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/ec/google/chromeec/acpi/pd.asl b/src/ec/google/chromeec/acpi/pd.asl index 1509a9eef2..c3189a9e1d 100644 --- a/src/ec/google/chromeec/acpi/pd.asl +++ b/src/ec/google/chromeec/acpi/pd.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (ECPD) { diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index a672c5c24e..649b842a64 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Chrome OS Embedded Controller interface diff --git a/src/ec/google/chromeec/acpi/tbmc.asl b/src/ec/google/chromeec/acpi/tbmc.asl index 639de4a2bc..15fbabd2cb 100644 --- a/src/ec/google/chromeec/acpi/tbmc.asl +++ b/src/ec/google/chromeec/acpi/tbmc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TBMC) { diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 2b7170f00d..78f8f4af11 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 291cd94c49..8f64ebd9d7 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 8f1f86407a..8bb366183a 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 60afb50522..c40172a4ac 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Mailbox EC communication interface for Google Chrome Embedded Controller. */ diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 11b1675c51..52b4fb3e37 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index f5eb3513e7..55f5b2a3eb 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index c621a39401..dd78922d00 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index f90b313d78..8c9d599056 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index 3738f24261..febb457607 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/smm.h b/src/ec/google/chromeec/smm.h index 4fe229203c..865885b010 100644 --- a/src/ec/google/chromeec/smm.h +++ b/src/ec/google/chromeec/smm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_GOOGLE_CHROMEEC_SMM_H #define _EC_GOOGLE_CHROMEEC_SMM_H diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 080b3596e9..f1dda1269b 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c index df9d39256e..571be0f8d4 100644 --- a/src/ec/google/chromeec/vboot_storage.c +++ b/src/ec/google/chromeec/vboot_storage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 1e1a003adf..d973ba96ca 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/common/mec.c b/src/ec/google/common/mec.c index 32bea3617b..c41d6d61b4 100644 --- a/src/ec/google/common/mec.c +++ b/src/ec/google/common/mec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/common/mec.h b/src/ec/google/common/mec.h index 2d3c9b5064..62fa252976 100644 --- a/src/ec/google/common/mec.h +++ b/src/ec/google/common/mec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_COMMON_MEC_H #define EC_GOOGLE_COMMON_MEC_H diff --git a/src/ec/google/wilco/acpi/ac.asl b/src/ec/google/wilco/acpi/ac.asl index a05b7fb9e3..0ff39521f5 100644 --- a/src/ec/google/wilco/acpi/ac.asl +++ b/src/ec/google/wilco/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (AC) { diff --git a/src/ec/google/wilco/acpi/battery.asl b/src/ec/google/wilco/acpi/battery.asl index 5e1e122ba6..c39673a93b 100644 --- a/src/ec/google/wilco/acpi/battery.asl +++ b/src/ec/google/wilco/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Mutex (BATM, 0) diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index b13ea9c2ce..b84e46e715 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Dynamic Platform Thermal Framework support diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index a04def1e52..d2cbc1c367 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EC0) { diff --git a/src/ec/google/wilco/acpi/ec_dev.asl b/src/ec/google/wilco/acpi/ec_dev.asl index 190b36c5d3..2daa9f7f97 100644 --- a/src/ec/google/wilco/acpi/ec_dev.asl +++ b/src/ec/google/wilco/acpi/ec_dev.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (WLCO) { diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 764341a0ac..edfaa533eb 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name (RD, 0) Name (WR, 1) diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 828c554d98..f1ef41dccd 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* ACPI_POWER_RECORD */ Name (ECPR, 0) diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl index 1412b998ee..1724b207d7 100644 --- a/src/ec/google/wilco/acpi/lid.asl +++ b/src/ec/google/wilco/acpi/lid.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LID0) { diff --git a/src/ec/google/wilco/acpi/platform.asl b/src/ec/google/wilco/acpi/platform.asl index fc276cbbe0..9f51f3d84e 100644 --- a/src/ec/google/wilco/acpi/platform.asl +++ b/src/ec/google/wilco/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Call from \_SB._PTS() */ Method (PTS, 1, Serialized) diff --git a/src/ec/google/wilco/acpi/privacy.asl b/src/ec/google/wilco/acpi/privacy.asl index b1a7f2fc88..167bcfbf4e 100644 --- a/src/ec/google/wilco/acpi/privacy.asl +++ b/src/ec/google/wilco/acpi/privacy.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Read Privacy Screen Present */ Method (GPVD, 0, Serialized) diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl index 7567408bc7..c2c3955a6e 100644 --- a/src/ec/google/wilco/acpi/superio.asl +++ b/src/ec/google/wilco/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Scope is \_SB.PCI0.LPCB */ diff --git a/src/ec/google/wilco/acpi/ucsi.asl b/src/ec/google/wilco/acpi/ucsi.asl index 2c5b2473ec..617ffe9479 100644 --- a/src/ec/google/wilco/acpi/ucsi.asl +++ b/src/ec/google/wilco/acpi/ucsi.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (UCSI) { diff --git a/src/ec/google/wilco/acpi/vbtn.asl b/src/ec/google/wilco/acpi/vbtn.asl index 7346455b56..5bdd74a3d6 100644 --- a/src/ec/google/wilco/acpi/vbtn.asl +++ b/src/ec/google/wilco/acpi/vbtn.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Intel Virtual Button driver compatible with the driver found in diff --git a/src/ec/google/wilco/boardid.c b/src/ec/google/wilco/boardid.c index 17412128e6..4c38c1ed90 100644 --- a/src/ec/google/wilco/boardid.c +++ b/src/ec/google/wilco/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "commands.h" diff --git a/src/ec/google/wilco/bootblock.c b/src/ec/google/wilco/bootblock.c index aaa555b69d..cb113a8fd9 100644 --- a/src/ec/google/wilco/bootblock.c +++ b/src/ec/google/wilco/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/wilco/bootblock.h b/src/ec/google/wilco/bootblock.h index 03b475ae15..df59ccba24 100644 --- a/src/ec/google/wilco/bootblock.h +++ b/src/ec/google/wilco/bootblock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_WILCO_BOOTBLOCK_H #define EC_GOOGLE_WILCO_BOOTBLOCK_H diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index acbd4871e4..2ce9bf0ad4 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/wilco/chip.h b/src/ec/google/wilco/chip.h index c79b5a175e..25d5a76195 100644 --- a/src/ec/google/wilco/chip.h +++ b/src/ec/google/wilco/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_WILCO_CHIP_H #define EC_GOOGLE_WILCO_CHIP_H diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index 99cae75035..f462b620ee 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index de95f610a5..313b934315 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_WILCO_COMMANDS_H #define EC_GOOGLE_WILCO_COMMANDS_H diff --git a/src/ec/google/wilco/ec.h b/src/ec/google/wilco/ec.h index ab649b19ec..60523e8bae 100644 --- a/src/ec/google/wilco/ec.h +++ b/src/ec/google/wilco/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_WILCO_EC_H #define EC_GOOGLE_WILCO_EC_H diff --git a/src/ec/google/wilco/mailbox.c b/src/ec/google/wilco/mailbox.c index 54bdc7f2fc..332ad01ad7 100644 --- a/src/ec/google/wilco/mailbox.c +++ b/src/ec/google/wilco/mailbox.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/wilco/romstage.c b/src/ec/google/wilco/romstage.c index 63229dcc04..08a84de0ea 100644 --- a/src/ec/google/wilco/romstage.c +++ b/src/ec/google/wilco/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "commands.h" #include "ec.h" diff --git a/src/ec/google/wilco/romstage.h b/src/ec/google/wilco/romstage.h index bfb9dcd4f2..a31d21f396 100644 --- a/src/ec/google/wilco/romstage.h +++ b/src/ec/google/wilco/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_WILCO_ROMSTAGE_H #define EC_GOOGLE_WILCO_ROMSTAGE_H diff --git a/src/ec/google/wilco/smihandler.c b/src/ec/google/wilco/smihandler.c index b325596397..a9f07fe0c4 100644 --- a/src/ec/google/wilco/smihandler.c +++ b/src/ec/google/wilco/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/google/wilco/smm.h b/src/ec/google/wilco/smm.h index f0bdd7195a..74a4360d43 100644 --- a/src/ec/google/wilco/smm.h +++ b/src/ec/google/wilco/smm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_GOOGLE_WILCO_SMM_H #define EC_GOOGLE_WILCO_SMM_H diff --git a/src/ec/hp/kbc1126/acpi/ac.asl b/src/ec/hp/kbc1126/acpi/ac.asl index 76ff3e0884..02a9ae38a5 100644 --- a/src/ec/hp/kbc1126/acpi/ac.asl +++ b/src/ec/hp/kbc1126/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name (ACST, 0x01) Name (SMAR, 0x00) diff --git a/src/ec/hp/kbc1126/acpi/battery.asl b/src/ec/hp/kbc1126/acpi/battery.asl index 97feeaa5db..2a8e062544 100644 --- a/src/ec/hp/kbc1126/acpi/battery.asl +++ b/src/ec/hp/kbc1126/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Field (ECRM, ByteAcc, NoLock, Preserve) { diff --git a/src/ec/hp/kbc1126/acpi/ec.asl b/src/ec/hp/kbc1126/acpi/ec.asl index 5854470450..8382bc031b 100644 --- a/src/ec/hp/kbc1126/acpi/ec.asl +++ b/src/ec/hp/kbc1126/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EC0) { diff --git a/src/ec/hp/kbc1126/acpi/lid.asl b/src/ec/hp/kbc1126/acpi/lid.asl index 2bdca8917e..ba96f7fd67 100644 --- a/src/ec/hp/kbc1126/acpi/lid.asl +++ b/src/ec/hp/kbc1126/acpi/lid.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LID) { diff --git a/src/ec/hp/kbc1126/chip.h b/src/ec/hp/kbc1126/chip.h index d3c9421ab6..692504c4f4 100644 --- a/src/ec/hp/kbc1126/chip.h +++ b/src/ec/hp/kbc1126/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_HP_KBC1126_CHIP_H #define _EC_HP_KBC1126_CHIP_H diff --git a/src/ec/hp/kbc1126/early_init.c b/src/ec/hp/kbc1126/early_init.c index 2123820598..695cee4ca8 100644 --- a/src/ec/hp/kbc1126/early_init.c +++ b/src/ec/hp/kbc1126/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index 8b8b92c6f3..7be025e2ac 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/hp/kbc1126/ec.h b/src/ec/hp/kbc1126/ec.h index 2a7cc531c6..72ba0b5e10 100644 --- a/src/ec/hp/kbc1126/ec.h +++ b/src/ec/hp/kbc1126/ec.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_HP_KBC1126_EC_H #define _EC_HP_KBC1126_EC_H diff --git a/src/ec/kontron/it8516e/acpi/ec.asl b/src/ec/kontron/it8516e/acpi/ec.asl index 170077be78..cff5255985 100644 --- a/src/ec/kontron/it8516e/acpi/ec.asl +++ b/src/ec/kontron/it8516e/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/ec/kontron/it8516e/acpi/pm_channels.asl b/src/ec/kontron/it8516e/acpi/pm_channels.asl index fc6b4bba06..f12bc13781 100644 --- a/src/ec/kontron/it8516e/acpi/pm_channels.asl +++ b/src/ec/kontron/it8516e/acpi/pm_channels.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifdef IT8516E_FIRST_DATA Device (PM1) { diff --git a/src/ec/kontron/it8516e/chip.h b/src/ec/kontron/it8516e/chip.h index 6034c46585..5e42d31599 100644 --- a/src/ec/kontron/it8516e/chip.h +++ b/src/ec/kontron/it8516e/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_KONTRON_IT8516E_CHIP_H #define EC_KONTRON_IT8516E_CHIP_H diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index cabac234cd..fc852a93d3 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/kontron/it8516e/ec.h b/src/ec/kontron/it8516e/ec.h index 9e6171c2dd..da4fa5338b 100644 --- a/src/ec/kontron/it8516e/ec.h +++ b/src/ec/kontron/it8516e/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_KONTRON_IT8516E_EC_H #define EC_KONTRON_IT8516E_EC_H diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h index 597f281ca1..9d54b380d8 100644 --- a/src/ec/kontron/kempld/chip.h +++ b/src/ec/kontron/kempld/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_KONTRON_KEMPLD_CHIP_H #define EC_KONTRON_KEMPLD_CHIP_H diff --git a/src/ec/kontron/kempld/early_kempld.c b/src/ec/kontron/kempld/early_kempld.c index c47274669f..810faf6e04 100644 --- a/src/ec/kontron/kempld/early_kempld.c +++ b/src/ec/kontron/kempld/early_kempld.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c index 6f2b2689bf..9c209e16c5 100644 --- a/src/ec/kontron/kempld/kempld.c +++ b/src/ec/kontron/kempld/kempld.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/kontron/kempld/kempld.h b/src/ec/kontron/kempld/kempld.h index 6e5000a5b1..c4214173b6 100644 --- a/src/ec/kontron/kempld/kempld.h +++ b/src/ec/kontron/kempld/kempld.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_KONTRON_KEMPLD_H #define EC_KONTRON_KEMPLD_H diff --git a/src/ec/kontron/kempld/kempld_internal.h b/src/ec/kontron/kempld/kempld_internal.h index 4f90f45808..1d0706a7a7 100644 --- a/src/ec/kontron/kempld/kempld_internal.h +++ b/src/ec/kontron/kempld/kempld_internal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_KONTRON_KEMPLD_INTERNAL_H #define EC_KONTRON_KEMPLD_INTERNAL_H diff --git a/src/ec/lenovo/h8/acpi/ac.asl b/src/ec/lenovo/h8/acpi/ac.asl index d67bfbc062..5e9cc30f3d 100644 --- a/src/ec/lenovo/h8/acpi/ac.asl +++ b/src/ec/lenovo/h8/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Field(ERAM, ByteAcc, NoLock, Preserve) { diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 79773c9d80..65a3bcf7da 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Field(ERAM, ByteAcc, NoLock, Preserve) { diff --git a/src/ec/lenovo/h8/acpi/beep.asl b/src/ec/lenovo/h8/acpi/beep.asl index 7f385c6a47..e996240afe 100644 --- a/src/ec/lenovo/h8/acpi/beep.asl +++ b/src/ec/lenovo/h8/acpi/beep.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Field(ERAM, ByteAcc, NoLock, Preserve) { diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 893732f56d..45fa0a8a1b 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC) { diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index 5c21744d3d..93323aa4a9 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Field(ERAM, ByteAcc, NoLock, Preserve) { diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl index 184829d713..82ba030f46 100644 --- a/src/ec/lenovo/h8/acpi/sleepbutton.asl +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Field(ERAM, ByteAcc, NoLock, Preserve) { diff --git a/src/ec/lenovo/h8/acpi/systemstatus.asl b/src/ec/lenovo/h8/acpi/systemstatus.asl index 11b42a86da..3c1bd94998 100644 --- a/src/ec/lenovo/h8/acpi/systemstatus.asl +++ b/src/ec/lenovo/h8/acpi/systemstatus.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SI) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 5ca7a5ab9c..8124a2f4cc 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index eb49511f2e..4f3c622d1f 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (HKEY) { diff --git a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl index 92d4a31f84..67a15faf0a 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This defines the battery charging thresholds setting methods tpacpi-bat can diff --git a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl index 438ac91277..f730765a76 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SB.PCI0.LPCB.EC) diff --git a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl index 260bd8e95f..94faa28291 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SB.PCI0.LPCB.EC) diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c index aba6ec1d6b..0ee0c02195 100644 --- a/src/ec/lenovo/h8/bluetooth.c +++ b/src/ec/lenovo/h8/bluetooth.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 665cbdf38d..a3263c64a1 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_LENOVO_H8EC_CHIP_H #define EC_LENOVO_H8EC_CHIP_H diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3bdb50ddda..e69b242bcb 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 9e2cfa044d..ecc9aabba6 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_LENOVO_H8_H #define EC_LENOVO_H8_H diff --git a/src/ec/lenovo/h8/panic.c b/src/ec/lenovo/h8/panic.c index 23eda97e17..dd0aea07a9 100644 --- a/src/ec/lenovo/h8/panic.c +++ b/src/ec/lenovo/h8/panic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/lenovo/h8/sense.c b/src/ec/lenovo/h8/sense.c index d0f07fd642..e8e356ff5e 100644 --- a/src/ec/lenovo/h8/sense.c +++ b/src/ec/lenovo/h8/sense.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/ec/lenovo/h8/ssdt.c b/src/ec/lenovo/h8/ssdt.c index af041c3683..6b821a40f2 100644 --- a/src/ec/lenovo/h8/ssdt.c +++ b/src/ec/lenovo/h8/ssdt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index 28ce6af617..e397dd8d27 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index 7aa996c772..cb60ce8616 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h index 0bc83dedbf..b67d738945 100644 --- a/src/ec/lenovo/pmh7/chip.h +++ b/src/ec/lenovo/pmh7/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_LENOVO_PMH7_CHIP_H #define EC_LENOVO_PMH7_CHIP_H diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 37a9351dfe..903d1acc9b 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index 141c250c9c..be8db98b6c 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EC_LENOVO_PMH7_H #define EC_LENOVO_PMH7_H diff --git a/src/ec/purism/librem/acpi/ac.asl b/src/ec/purism/librem/acpi/ac.asl index 08d6b6d47d..a6eb0843a5 100644 --- a/src/ec/purism/librem/acpi/ac.asl +++ b/src/ec/purism/librem/acpi/ac.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (AC) { diff --git a/src/ec/purism/librem/acpi/battery.asl b/src/ec/purism/librem/acpi/battery.asl index f2e3881351..8e64dfe0f8 100644 --- a/src/ec/purism/librem/acpi/battery.asl +++ b/src/ec/purism/librem/acpi/battery.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (BAT) { diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index e64770adb9..89af552c97 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TPSD) { diff --git a/src/ec/quanta/ene_kb3940q/acpi/ac.asl b/src/ec/quanta/ene_kb3940q/acpi/ac.asl index 88330ea8fc..5d96945613 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ac.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl index dbfd477024..5c2c29d46b 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/battery.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The mainboard must define strings in the root scope to diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 9b792db704..7bd6160431 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The mainboard must define a PNOT method to handle power diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl index 86950f1e05..0741c44159 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/superio.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/ec/quanta/ene_kb3940q/chip.h b/src/ec/quanta/ene_kb3940q/chip.h index 77357f3223..6e6c1c31da 100644 --- a/src/ec/quanta/ene_kb3940q/chip.h +++ b/src/ec/quanta/ene_kb3940q/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H #define _EC_QUANTA_ENE_KB3940Q_CHIP_H diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index e37b980572..15c04003c3 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h index 5b278c114f..7b7d66a8cc 100644 --- a/src/ec/quanta/ene_kb3940q/ec.h +++ b/src/ec/quanta/ene_kb3940q/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * EC communication interface for QUANTA EnE KB3940Q Embedded Controller. diff --git a/src/ec/quanta/it8518/acpi/ac.asl b/src/ec/quanta/it8518/acpi/ac.asl index 64353295f3..15f369c811 100644 --- a/src/ec/quanta/it8518/acpi/ac.asl +++ b/src/ec/quanta/it8518/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index fcfae755f2..d9c7da9c73 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index 3a61d5d9cc..e9390e4f9d 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The mainboard must define a PNOT method to handle power diff --git a/src/ec/quanta/it8518/acpi/superio.asl b/src/ec/quanta/it8518/acpi/superio.asl index 8363fb9079..2800f3c3f0 100644 --- a/src/ec/quanta/it8518/acpi/superio.asl +++ b/src/ec/quanta/it8518/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/ec/quanta/it8518/chip.h b/src/ec/quanta/it8518/chip.h index 67cf694f61..3b2b8d79fb 100644 --- a/src/ec/quanta/it8518/chip.h +++ b/src/ec/quanta/it8518/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_QUANTA_IT8518_CHIP_H #define _EC_QUANTA_IT8518_CHIP_H diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 593eddc194..fd17097d0c 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 4cc88a3e37..a5617b5bca 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * EC communication interface for QUANTA IT8518 Embedded Controller. diff --git a/src/ec/roda/it8518/acpi/ac.asl b/src/ec/roda/it8518/acpi/ac.asl index 359181c89e..dfddba647b 100644 --- a/src/ec/roda/it8518/acpi/ac.asl +++ b/src/ec/roda/it8518/acpi/ac.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ //SCOPE EC0 diff --git a/src/ec/roda/it8518/acpi/battery.asl b/src/ec/roda/it8518/acpi/battery.asl index c18b9d3bf5..d2196e8ea1 100644 --- a/src/ec/roda/it8518/acpi/battery.asl +++ b/src/ec/roda/it8518/acpi/battery.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ //SCOPE EC0 diff --git a/src/ec/roda/it8518/acpi/ec.asl b/src/ec/roda/it8518/acpi/ec.asl index 084d788cbd..d46485ec0b 100644 --- a/src/ec/roda/it8518/acpi/ec.asl +++ b/src/ec/roda/it8518/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/ec/roda/it8518/acpi/lid.asl b/src/ec/roda/it8518/acpi/lid.asl index e218d76153..1f9b35a336 100644 --- a/src/ec/roda/it8518/acpi/lid.asl +++ b/src/ec/roda/it8518/acpi/lid.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ //SCOPE EC0 diff --git a/src/ec/roda/it8518/chip.h b/src/ec/roda/it8518/chip.h index a18d791795..059485186d 100644 --- a/src/ec/roda/it8518/chip.h +++ b/src/ec/roda/it8518/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_RODA_IT8518_CHIP_H #define _EC_RODA_IT8518_CHIP_H diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c index a9dfb0afae..8f36decd68 100644 --- a/src/ec/roda/it8518/ec.c +++ b/src/ec/roda/it8518/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/smsc/mec1308/acpi/ac.asl b/src/ec/smsc/mec1308/acpi/ac.asl index c7aa5173f1..d2061c64a8 100644 --- a/src/ec/smsc/mec1308/acpi/ac.asl +++ b/src/ec/smsc/mec1308/acpi/ac.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope (EC0) diff --git a/src/ec/smsc/mec1308/acpi/battery.asl b/src/ec/smsc/mec1308/acpi/battery.asl index 4040be8f53..8a61ef1d39 100644 --- a/src/ec/smsc/mec1308/acpi/battery.asl +++ b/src/ec/smsc/mec1308/acpi/battery.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The mainboard must define strings in the root scope to diff --git a/src/ec/smsc/mec1308/acpi/ec.asl b/src/ec/smsc/mec1308/acpi/ec.asl index f2b8f1c5d0..9505dcd02c 100644 --- a/src/ec/smsc/mec1308/acpi/ec.asl +++ b/src/ec/smsc/mec1308/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The mainboard must define a PNOT method to handle power diff --git a/src/ec/smsc/mec1308/chip.h b/src/ec/smsc/mec1308/chip.h index 297e10855d..e9ec4334fa 100644 --- a/src/ec/smsc/mec1308/chip.h +++ b/src/ec/smsc/mec1308/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EC_SMSC_MEC1308_CHIP_H #define _EC_SMSC_MEC1308_CHIP_H diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index 2493f00e58..603f92ec2c 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/ec/smsc/mec1308/ec.h b/src/ec/smsc/mec1308/ec.h index b143c51581..324695db53 100644 --- a/src/ec/smsc/mec1308/ec.h +++ b/src/ec/smsc/mec1308/ec.h @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Mailbox EC communication interface for SMSC MEC1308 Embedded Controller. */ From ae593879f5a589df7c88d0bbce966657891e93c5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:50:57 +0200 Subject: [PATCH 0819/1463] soc/amd: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/common/acpi/gpio_bank_lib.asl | 15 ++------------- src/soc/amd/common/acpi/lpc.asl | 15 ++------------- src/soc/amd/common/acpi/thermal_zone.asl | 14 ++------------ src/soc/amd/common/block/acpi/acpi.c | 15 ++------------- src/soc/amd/common/block/acpimmio/biosram.c | 14 ++------------ src/soc/amd/common/block/acpimmio/mmio_util.c | 15 ++------------- src/soc/amd/common/block/alink/alink.c | 15 ++------------- src/soc/amd/common/block/cpu/car/ap_exit_car.S | 15 ++------------- src/soc/amd/common/block/cpu/car/cache_as_ram.S | 15 ++------------- src/soc/amd/common/block/cpu/car/exit_car.S | 15 ++------------- src/soc/amd/common/block/gpio_banks/gpio.c | 15 ++------------- src/soc/amd/common/block/hda/hda.c | 15 ++------------- .../block/include/amdblocks/BiosCallOuts.h | 15 ++------------- .../amd/common/block/include/amdblocks/acpi.h | 15 ++------------- .../block/include/amdblocks/agesawrapper.h | 15 ++------------- .../block/include/amdblocks/agesawrapper_call.h | 14 ++------------ .../amd/common/block/include/amdblocks/alink.h | 15 ++------------- .../block/include/amdblocks/amd_pci_mmconf.h | 14 ++------------ .../block/include/amdblocks/amd_pci_util.h | 15 ++------------- .../amd/common/block/include/amdblocks/biosram.h | 14 ++------------ src/soc/amd/common/block/include/amdblocks/car.h | 15 ++------------- .../common/block/include/amdblocks/dimm_spd.h | 15 ++------------- .../common/block/include/amdblocks/gpio_banks.h | 15 ++------------- .../amd/common/block/include/amdblocks/image.h | 15 ++------------- src/soc/amd/common/block/include/amdblocks/lpc.h | 15 ++------------- src/soc/amd/common/block/include/amdblocks/psp.h | 15 ++------------- .../amd/common/block/include/amdblocks/reset.h | 15 ++------------- .../common/block/include/amdblocks/s3_resume.h | 15 ++------------- .../amd/common/block/include/amdblocks/sata.h | 15 ++------------- src/soc/amd/common/block/iommu/iommu.c | 15 ++------------- src/soc/amd/common/block/lpc/lpc.c | 15 ++------------- src/soc/amd/common/block/lpc/lpc_util.c | 15 ++------------- src/soc/amd/common/block/pci/amd_pci_mmconf.c | 14 ++------------ src/soc/amd/common/block/pci/amd_pci_util.c | 15 ++------------- src/soc/amd/common/block/pi/agesawrapper.c | 15 ++------------- src/soc/amd/common/block/pi/amd_late_init.c | 15 ++------------- src/soc/amd/common/block/pi/amd_resume_final.c | 15 ++------------- src/soc/amd/common/block/pi/def_callouts.c | 15 ++------------- src/soc/amd/common/block/pi/heapmanager.c | 14 ++------------ src/soc/amd/common/block/pi/image.c | 15 ++------------- src/soc/amd/common/block/pi/refcode_loader.c | 15 ++------------- src/soc/amd/common/block/psp/psp.c | 15 ++------------- src/soc/amd/common/block/s3/s3_resume.c | 15 ++------------- src/soc/amd/common/block/sata/sata.c | 15 ++------------- src/soc/amd/common/block/smbus/sm.c | 15 ++------------- src/soc/amd/common/block/smbus/smbus.c | 15 ++------------- src/soc/amd/common/block/spi/fch_spi_ctrl.c | 15 ++------------- src/soc/amd/picasso/acp.c | 15 ++------------- src/soc/amd/picasso/acpi.c | 15 ++------------- src/soc/amd/picasso/acpi/acpi_wake_source.asl | 15 ++------------- src/soc/amd/picasso/acpi/cpu.asl | 15 ++------------- src/soc/amd/picasso/acpi/northbridge.asl | 15 ++------------- src/soc/amd/picasso/acpi/pci_int.asl | 15 ++------------- src/soc/amd/picasso/acpi/pcie.asl | 15 ++------------- src/soc/amd/picasso/acpi/sb_fch.asl | 15 ++------------- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 15 ++------------- src/soc/amd/picasso/acpi/sleepstates.asl | 15 ++------------- src/soc/amd/picasso/acpi/soc.asl | 15 ++------------- src/soc/amd/picasso/acpi/usb.asl | 16 ++-------------- src/soc/amd/picasso/cfg_util.c | 14 ++------------ src/soc/amd/picasso/chip.c | 15 ++------------- src/soc/amd/picasso/chip.h | 15 ++------------- src/soc/amd/picasso/cpu.c | 15 ++------------- src/soc/amd/picasso/finalize.c | 15 ++------------- src/soc/amd/picasso/gpio.c | 15 ++------------- src/soc/amd/picasso/i2c.c | 15 ++------------- .../amd/picasso/include/soc/amd_pci_int_defs.h | 15 ++------------- src/soc/amd/picasso/include/soc/cpu.h | 15 ++------------- src/soc/amd/picasso/include/soc/gpio.h | 15 ++------------- src/soc/amd/picasso/include/soc/i2c.h | 15 ++------------- src/soc/amd/picasso/include/soc/iomap.h | 15 ++------------- src/soc/amd/picasso/include/soc/northbridge.h | 15 ++------------- src/soc/amd/picasso/include/soc/pci_devs.h | 15 ++------------- src/soc/amd/picasso/include/soc/romstage.h | 15 ++------------- src/soc/amd/picasso/include/soc/southbridge.h | 15 ++------------- src/soc/amd/picasso/mca.c | 15 ++------------- src/soc/amd/picasso/memmap.c | 15 ++------------- src/soc/amd/picasso/northbridge.c | 15 ++------------- src/soc/amd/picasso/pmutil.c | 15 ++------------- src/soc/amd/picasso/reset.c | 15 ++------------- src/soc/amd/picasso/romstage.c | 14 ++------------ src/soc/amd/picasso/sata.c | 15 ++------------- src/soc/amd/picasso/southbridge.c | 15 ++------------- src/soc/amd/picasso/uart.c | 15 ++------------- src/soc/amd/picasso/usb.c | 15 ++------------- src/soc/amd/stoneyridge/BiosCallOuts.c | 15 ++------------- src/soc/amd/stoneyridge/acpi.c | 15 ++------------- .../amd/stoneyridge/acpi/acpi_wake_source.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/cpu.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/northbridge.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/pci_int.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/pcie.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/sb_fch.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/sleepstates.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/soc.asl | 15 ++------------- src/soc/amd/stoneyridge/acpi/usb.asl | 16 ++-------------- src/soc/amd/stoneyridge/bootblock/bootblock.c | 15 ++------------- src/soc/amd/stoneyridge/chip.c | 15 ++------------- src/soc/amd/stoneyridge/chip.h | 15 ++------------- src/soc/amd/stoneyridge/cpu.c | 15 ++------------- src/soc/amd/stoneyridge/enable_usbdebug.c | 15 ++------------- src/soc/amd/stoneyridge/finalize.c | 15 ++------------- src/soc/amd/stoneyridge/gpio.c | 15 ++------------- src/soc/amd/stoneyridge/i2c.c | 15 ++------------- .../stoneyridge/include/soc/amd_pci_int_defs.h | 15 ++------------- src/soc/amd/stoneyridge/include/soc/cpu.h | 15 ++------------- src/soc/amd/stoneyridge/include/soc/gpio.h | 15 ++------------- src/soc/amd/stoneyridge/include/soc/i2c.h | 15 ++------------- src/soc/amd/stoneyridge/include/soc/iomap.h | 15 ++------------- .../amd/stoneyridge/include/soc/northbridge.h | 15 ++------------- src/soc/amd/stoneyridge/include/soc/pci_devs.h | 15 ++------------- src/soc/amd/stoneyridge/include/soc/romstage.h | 15 ++------------- .../amd/stoneyridge/include/soc/southbridge.h | 15 ++------------- src/soc/amd/stoneyridge/mca.c | 15 ++------------- src/soc/amd/stoneyridge/memmap.c | 15 ++------------- src/soc/amd/stoneyridge/northbridge.c | 15 ++------------- src/soc/amd/stoneyridge/pmutil.c | 15 ++------------- src/soc/amd/stoneyridge/reset.c | 15 ++------------- src/soc/amd/stoneyridge/romstage.c | 15 ++------------- src/soc/amd/stoneyridge/sata.c | 15 ++------------- src/soc/amd/stoneyridge/smbus_spd.c | 15 ++------------- src/soc/amd/stoneyridge/southbridge.c | 15 ++------------- src/soc/amd/stoneyridge/uart.c | 15 ++------------- src/soc/amd/stoneyridge/usb.c | 15 ++------------- 125 files changed, 250 insertions(+), 1618 deletions(-) diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index f2963104c3..8ca48e8d65 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl index a2b28d2805..6341135fa9 100644 --- a/src/soc/amd/common/acpi/lpc.asl +++ b/src/soc/amd/common/acpi/lpc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if MAINBOARD_HAS_SPEAKER #define IO61_HID "PNP0800" /* AT style speaker */ diff --git a/src/soc/amd/common/acpi/thermal_zone.asl b/src/soc/amd/common/acpi/thermal_zone.asl index e6ab43235b..5b4721a332 100644 --- a/src/soc/amd/common/acpi/thermal_zone.asl +++ b/src/soc/amd/common/acpi/thermal_zone.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard DSDT inside the PCI device diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 4d99f7b535..9d8da6e4a3 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index 1b1fcadee3..c99de566b0 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index cb5730dbd5..e34b13d238 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/alink/alink.c b/src/soc/amd/common/block/alink/alink.c index 3a1e2bf842..c7485e217b 100644 --- a/src/soc/amd/common/block/alink/alink.c +++ b/src/soc/amd/common/block/alink/alink.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/cpu/car/ap_exit_car.S b/src/soc/amd/common/block/cpu/car/ap_exit_car.S index 756e31f3ac..bcbad39ac6 100644 --- a/src/soc/amd/common/block/cpu/car/ap_exit_car.S +++ b/src/soc/amd/common/block/cpu/car/ap_exit_car.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .code32 diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 528159df5b..89d8df585b 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /****************************************************************************** * $Workfile:: cache_as_ram.S diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index 6eea7fc418..680898ba9a 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index a56fe42f9e..1d3cf08946 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 76ce9e370b..1eaee1e578 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 5736ed47d9..00031a3fd7 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __CALLOUTS_AMD_AGESA_H__ #define __CALLOUTS_AMD_AGESA_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 44eb903030..71e29cdd22 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_ACPI_H__ #define __AMDBLOCKS_ACPI_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index a74a3d6560..7c1ba948b9 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AGESAWRAPPER_H__ #define __AGESAWRAPPER_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h index 86e32aff79..ed649f1b8e 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AGESAWRAPPER_CALL_H__ #define __AGESAWRAPPER_CALL_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/alink.h b/src/soc/amd/common/block/include/amdblocks/alink.h index 48b3dc2b86..2c1ea00e79 100644 --- a/src/soc/amd/common/block/include/amdblocks/alink.h +++ b/src/soc/amd/common/block/include/amdblocks/alink.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_ALINK_H__ #define __AMDBLOCKS_ALINK_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h index 4b65ad0948..a93ce81d16 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_PCI_MMCONF_H__ #define __AMDBLOCKS_PCI_MMCONF_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 4cf87cb07b..737d57e80e 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_PCI_UTIL_H__ #define __AMD_PCI_UTIL_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 4bfd629b59..96e23f6b85 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_BIOSRAM_H__ #define __AMDBLOCKS_BIOSRAM_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/car.h b/src/soc/amd/common/block/include/amdblocks/car.h index 57b19380fa..4e78c6382f 100644 --- a/src/soc/amd/common/block/include/amdblocks/car.h +++ b/src/soc/amd/common/block/include/amdblocks/car.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_CAR_H__ #define __AMD_CAR_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h index 6d678afcf0..f52957f7d1 100644 --- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h +++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DIMMSPD_H__ #define __DIMMSPD_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 6589e7a6cc..9b9b748724 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCK_GPIO_BANKS_H__ #define __AMDBLOCK_GPIO_BANKS_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/image.h b/src/soc/amd/common/block/include/amdblocks/image.h index 8b08c72fc4..12d80ef1ca 100644 --- a/src/soc/amd/common/block/include/amdblocks/image.h +++ b/src/soc/amd/common/block/include/amdblocks/image.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_IMAGE_H__ #define __AMD_IMAGE_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index c7ccc08e1c..dc33073d3e 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_LPC_H__ #define __AMDBLOCKS_LPC_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index d7f6169411..36e110867a 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_PSP_H__ #define __AMD_PSP_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index 124f2347bf..85237d76eb 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_RESET_H__ #define __AMD_RESET_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 1a5f1f4ccd..d6b9e8439e 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_S3_RESUME_H__ #define __AMD_S3_RESUME_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h index cafd343c01..df913118f3 100644 --- a/src/soc/amd/common/block/include/amdblocks/sata.h +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_SATA_H__ #define __AMDBLOCKS_SATA_H__ diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 18d9105959..effdd7ce29 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 7f9b71554e..5346356ad6 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 39f5d265e7..571c6fe8ed 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c index 1aed51bf1b..30cbdcb81a 100644 --- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c index 6e7de8d50b..f2ea73ff1a 100644 --- a/src/soc/amd/common/block/pci/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 7afece26f3..2d7954fba2 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index cceeaef50c..6cdae6b5ab 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c index 4561db0e92..ac64e536b7 100644 --- a/src/soc/amd/common/block/pi/amd_resume_final.c +++ b/src/soc/amd/common/block/pi/amd_resume_final.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index ce615bdf19..b7e5486b7c 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index 3b383ace6f..6359f23541 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/amd/common/block/pi/image.c b/src/soc/amd/common/block/pi/image.c index 38a20898cb..3525a5f8df 100644 --- a/src/soc/amd/common/block/pi/image.c +++ b/src/soc/amd/common/block/pi/image.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 00d249dc02..191e79903e 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index c580803829..c35f41b20c 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 69be4a6af5..44962c6d74 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 90f63728a8..3137672bf6 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index e118cb8384..2863d22326 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index c9f065ab94..8e94422b35 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index b298c378f6..4320d925da 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index b0c7b0fbb3..3dbc9f7a7a 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 8ee7c97b6c..910d3e927e 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * ACPI - create the Fixed ACPI Description Tables (FADT) diff --git a/src/soc/amd/picasso/acpi/acpi_wake_source.asl b/src/soc/amd/picasso/acpi/acpi_wake_source.asl index a5440e8e51..9dadcdaf45 100644 --- a/src/soc/amd/picasso/acpi/acpi_wake_source.asl +++ b/src/soc/amd/picasso/acpi/acpi_wake_source.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 587dbea18c..d8de75b4e0 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Required function by EC, Notify OS to re-read CPU tables */ Method (PNOT) diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index c7712a6c86..c8076015bb 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 13e195a7f7..8f49751fc9 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index ba964fd00a..eaa4563448 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCI IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 9276fc78a2..5dd7159465 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 46bcc7aae0..3e6029e0e0 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ External(\_SB.ALIB, MethodObj) diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl index 16c8bf24a4..9f4d999a41 100644 --- a/src/soc/amd/picasso/acpi/sleepstates.asl +++ b/src/soc/amd/picasso/acpi/sleepstates.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index c5cc419b65..790f89bdd8 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(PCI0) { /* Describe the AMD Northbridge */ diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl index 5c5291928e..2d3f4e24e6 100644 --- a/src/soc/amd/picasso/acpi/usb.asl +++ b/src/soc/amd/picasso/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* 0:12.0 - EHCI */ Device(EHC0) { diff --git a/src/soc/amd/picasso/cfg_util.c b/src/soc/amd/picasso/cfg_util.c index 60555e44c5..b0b06522da 100644 --- a/src/soc/amd/picasso/cfg_util.c +++ b/src/soc/amd/picasso/cfg_util.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index cf9bd5473f..ae3ae32626 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index aa27cd382b..53c03291b7 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PICASSO_CHIP_H__ #define __PICASSO_CHIP_H__ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 60446882d5..2325994a9c 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 91cc5c26b6..09e9b6b4b4 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index 51cde5b7be..e5069243b3 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index e2da961f7d..6bbc7a7adc 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index 5f4f195edb..8186cce172 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_PCI_INT_DEFS_H__ #define __AMD_PCI_INT_DEFS_H__ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index c53829d5c8..dabc73a8f5 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PICASSO_CPU_H__ #define __PICASSO_CPU_H__ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 2c2f83de31..98fbff00d9 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PICASSO_GPIO_H__ #define __PICASSO_GPIO_H__ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 8bc3254429..4cf857eb63 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PICASSO_I2C_H__ #define __PICASSO_I2C_H__ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 6eaff8e13f..1ff3440307 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_PICASSO_IOMAP_H__ #define __SOC_PICASSO_IOMAP_H__ diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 22de453ac0..e7ab290d6c 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PI_PICASSO_NORTHBRIDGE_H__ #define __PI_PICASSO_NORTHBRIDGE_H__ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 2b72fe7375..a7ce3fc430 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PI_PICASSO_PCI_DEVS_H__ #define __PI_PICASSO_PCI_DEVS_H__ diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index 1669b7582c..5d21d0824d 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PICASSO_ROMSTAGE_H__ #define __PICASSO_ROMSTAGE_H__ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 0518b8ac61..a13424536e 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PICASSO_SB_H__ #define __PICASSO_SB_H__ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 122c751e0b..2970b942ef 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 304b81d311..0c8d9c0cdf 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index b6e5d5c8a1..99ae542d91 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/pmutil.c b/src/soc/amd/picasso/pmutil.c index e5a5b5cdc4..a38acf2461 100644 --- a/src/soc/amd/picasso/pmutil.c +++ b/src/soc/amd/picasso/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 5c62a4990f..dda08de544 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 8b8d3297ac..bbbc891c5a 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c index 18a5593cf7..4dbd86c4fb 100644 --- a/src/soc/amd/picasso/sata.c +++ b/src/soc/amd/picasso/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 61c7f36c07..6bedab0629 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index cdeb493711..14a43c18bf 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index fed1c9b64d..67328b8f52 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 0c5af35ef5..105926c5b6 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index f59aeb504a..6a373fbd49 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * ACPI - create the Fixed ACPI Description Tables (FADT) diff --git a/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl b/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl index a5440e8e51..9dadcdaf45 100644 --- a/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl +++ b/src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 1ecde23f7a..fb714f8de6 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Required function by EC, Notify OS to re-read CPU tables */ Method (PNOT) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c7712a6c86..c8076015bb 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index 13e195a7f7..8f49751fc9 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ diff --git a/src/soc/amd/stoneyridge/acpi/pcie.asl b/src/soc/amd/stoneyridge/acpi/pcie.asl index ba964fd00a..eaa4563448 100644 --- a/src/soc/amd/stoneyridge/acpi/pcie.asl +++ b/src/soc/amd/stoneyridge/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCI IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 0e30e07676..3057b8d955 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index e5c6bb6e8e..8cf8da4e24 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ External(\_SB.ALIB, MethodObj) diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index 16c8bf24a4..9f4d999a41 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index c5cc419b65..790f89bdd8 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(PCI0) { /* Describe the AMD Northbridge */ diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index f06e04d9bf..95c607b23c 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* 0:12.0 - EHCI */ Device(EHC0) { diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 186f77c646..a19a3d4f65 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index caf9c63888..8efe64feca 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index c78663330a..22c8cc6547 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __STONEYRIDGE_CHIP_H__ #define __STONEYRIDGE_CHIP_H__ diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index c2910a28be..f134e36edb 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 83d8357549..ab6c95265f 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 91cc5c26b6..09e9b6b4b4 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 853ff95d8e..9a2d32034f 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 8db263838f..bd8fd5b842 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index cb2ecb52b7..a038b85bbc 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_PCI_INT_DEFS_H__ #define __AMD_PCI_INT_DEFS_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index cbae3dab01..73a80830d2 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 90447a96db..dedbc4ff9b 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __STONEYRIDGE_GPIO_H__ #define __STONEYRIDGE_GPIO_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 68e2ae5b16..fb1e7406d3 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __STONEYRIDGE_I2C_H__ #define __STONEYRIDGE_I2C_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 479964ee20..d140124cbe 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_STONEYRIDGE_IOMAP_H__ #define __SOC_STONEYRIDGE_IOMAP_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index f39bc24209..173c798d8f 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ #define __PI_STONEYRIDGE_NORTHBRIDGE_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 65a59cf8dd..9285d8a3ae 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ #define __PI_STONEYRIDGE_PCI_DEVS_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 89f714df72..4086ace6ef 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __STONEYRIDGE_ROMSTAGE_H__ #define __STONEYRIDGE_ROMSTAGE_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 7384951063..69210b78c1 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __STONEYRIDGE_H__ #define __STONEYRIDGE_H__ diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 8917204764..44f43b4717 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 304b81d311..0c8d9c0cdf 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index b853d5f287..ae4b747a02 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index e5a5b5cdc4..a38acf2461 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 0013a63a96..e3587a06bb 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index fab9a83e04..9c3154107a 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index 18a5593cf7..4dbd86c4fb 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index a8c20132b5..e96b1d5383 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b636c26699..614a798651 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 268a479c93..c4ea1aefac 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 10aba3a573..cf3669f8c0 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 4b42983c7a072011499e6a610cfccf3d30689b05 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:50 +0200 Subject: [PATCH 0820/1463] src/northbridge: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/northbridge/amd/agesa/BiosCallOuts.h | 15 ++------------- src/northbridge/amd/agesa/agesa_helper.h | 15 ++------------- src/northbridge/amd/agesa/dimmSpd.h | 15 ++------------- .../amd/agesa/family14/acpi/northbridge.asl | 15 ++------------- src/northbridge/amd/agesa/family14/chip.h | 15 ++------------- src/northbridge/amd/agesa/family14/dimmSpd.c | 15 ++------------- src/northbridge/amd/agesa/family14/northbridge.c | 15 ++------------- src/northbridge/amd/agesa/family14/pci_devs.h | 15 ++------------- .../amd/agesa/family14/state_machine.c | 15 ++------------- .../amd/agesa/family15tn/acpi/northbridge.asl | 15 ++------------- src/northbridge/amd/agesa/family15tn/chip.h | 15 ++------------- src/northbridge/amd/agesa/family15tn/dimmSpd.c | 15 ++------------- src/northbridge/amd/agesa/family15tn/iommu.c | 15 ++------------- .../amd/agesa/family15tn/northbridge.c | 15 ++------------- src/northbridge/amd/agesa/family15tn/pci_devs.h | 15 ++------------- .../amd/agesa/family15tn/state_machine.c | 15 ++------------- .../amd/agesa/family16kb/acpi/northbridge.asl | 15 ++------------- src/northbridge/amd/agesa/family16kb/chip.h | 15 ++------------- src/northbridge/amd/agesa/family16kb/dimmSpd.c | 15 ++------------- .../amd/agesa/family16kb/northbridge.c | 15 ++------------- src/northbridge/amd/agesa/family16kb/pci_devs.h | 15 ++------------- .../amd/agesa/family16kb/state_machine.c | 15 ++------------- src/northbridge/amd/agesa/nb_common.h | 14 ++------------ src/northbridge/amd/agesa/state_machine.h | 15 ++------------- .../amd/pi/00630F01/acpi/northbridge.asl | 15 ++------------- src/northbridge/amd/pi/00630F01/chip.h | 15 ++------------- src/northbridge/amd/pi/00630F01/dimmSpd.c | 15 ++------------- src/northbridge/amd/pi/00630F01/iommu.c | 15 ++------------- src/northbridge/amd/pi/00630F01/northbridge.c | 15 ++------------- src/northbridge/amd/pi/00630F01/pci_devs.h | 15 ++------------- .../amd/pi/00660F01/acpi/northbridge.asl | 15 ++------------- src/northbridge/amd/pi/00660F01/chip.h | 15 ++------------- src/northbridge/amd/pi/00660F01/dimmSpd.c | 15 ++------------- src/northbridge/amd/pi/00660F01/northbridge.c | 15 ++------------- .../amd/pi/00730F01/acpi/northbridge.asl | 15 ++------------- src/northbridge/amd/pi/00730F01/chip.h | 15 ++------------- src/northbridge/amd/pi/00730F01/dimmSpd.c | 15 ++------------- src/northbridge/amd/pi/00730F01/iommu.c | 15 ++------------- src/northbridge/amd/pi/00730F01/northbridge.c | 15 ++------------- src/northbridge/amd/pi/00730F01/pci_devs.h | 15 ++------------- src/northbridge/amd/pi/00730F01/state_machine.c | 15 ++------------- src/northbridge/amd/pi/dimmSpd.h | 15 ++------------- src/northbridge/amd/pi/nb_common.h | 14 ++------------ src/northbridge/intel/e7505/memmap.c | 14 ++------------ src/northbridge/intel/e7505/northbridge.c | 14 ++------------ src/northbridge/intel/e7505/raminit.c | 16 ++-------------- src/northbridge/intel/e7505/raminit.h | 14 ++------------ src/northbridge/intel/e7505/romstage.c | 15 ++------------- src/northbridge/intel/gm45/acpi.c | 16 ++-------------- src/northbridge/intel/gm45/acpi/gm45.asl | 16 ++-------------- src/northbridge/intel/gm45/acpi/hostbridge.asl | 16 ++-------------- src/northbridge/intel/gm45/acpi/peg.asl | 16 ++-------------- src/northbridge/intel/gm45/bootblock.c | 14 ++------------ src/northbridge/intel/gm45/chip.h | 15 ++------------- src/northbridge/intel/gm45/early_init.c | 15 ++------------- src/northbridge/intel/gm45/early_reset.c | 16 ++-------------- src/northbridge/intel/gm45/gm45.h | 15 ++------------- src/northbridge/intel/gm45/gma.c | 15 ++------------- src/northbridge/intel/gm45/igd.c | 16 ++-------------- src/northbridge/intel/gm45/iommu.c | 16 ++-------------- src/northbridge/intel/gm45/memmap.c | 16 ++-------------- src/northbridge/intel/gm45/northbridge.c | 15 ++------------- src/northbridge/intel/gm45/pcie.c | 16 ++-------------- src/northbridge/intel/gm45/pm.c | 16 ++-------------- src/northbridge/intel/gm45/raminit.c | 16 ++-------------- .../intel/gm45/raminit_rcomp_calibration.c | 15 ++------------- .../intel/gm45/raminit_read_write_training.c | 15 ++------------- .../gm45/raminit_receive_enable_calibration.c | 15 ++------------- src/northbridge/intel/gm45/romstage.c | 15 ++------------- src/northbridge/intel/gm45/thermal.c | 16 ++-------------- src/northbridge/intel/haswell/acpi.c | 16 ++-------------- src/northbridge/intel/haswell/acpi/haswell.asl | 16 ++-------------- .../intel/haswell/acpi/hostbridge.asl | 16 ++-------------- src/northbridge/intel/haswell/acpi/peg.asl | 16 ++-------------- src/northbridge/intel/haswell/bootblock.c | 14 ++------------ src/northbridge/intel/haswell/chip.h | 15 ++------------- src/northbridge/intel/haswell/early_init.c | 15 ++------------- src/northbridge/intel/haswell/finalize.c | 16 ++-------------- src/northbridge/intel/haswell/gma.c | 15 ++------------- src/northbridge/intel/haswell/haswell.h | 15 ++------------- src/northbridge/intel/haswell/mchbar_regs.h | 15 ++------------- src/northbridge/intel/haswell/memmap.c | 15 ++------------- src/northbridge/intel/haswell/minihd.c | 15 ++------------- src/northbridge/intel/haswell/northbridge.c | 15 ++------------- src/northbridge/intel/haswell/pcie.c | 16 ++-------------- src/northbridge/intel/haswell/raminit.c | 15 ++------------- src/northbridge/intel/haswell/raminit.h | 15 ++------------- src/northbridge/intel/haswell/report_platform.c | 15 ++------------- .../intel/i440bx/acpi/sb_pci0_crs.asl | 15 ++------------- src/northbridge/intel/i440bx/debug.c | 14 ++------------ src/northbridge/intel/i440bx/memmap.c | 15 ++------------- src/northbridge/intel/i440bx/northbridge.c | 14 ++------------ src/northbridge/intel/i945/acpi.c | 16 ++-------------- src/northbridge/intel/i945/acpi/hostbridge.asl | 16 ++-------------- src/northbridge/intel/i945/acpi/i945.asl | 16 ++-------------- src/northbridge/intel/i945/acpi/igd.asl | 16 ++-------------- src/northbridge/intel/i945/acpi/peg.asl | 16 ++-------------- src/northbridge/intel/i945/bootblock.c | 14 ++------------ src/northbridge/intel/i945/chip.h | 14 ++------------ src/northbridge/intel/i945/debug.c | 16 ++-------------- src/northbridge/intel/i945/early_init.c | 15 ++------------- src/northbridge/intel/i945/errata.c | 15 ++------------- src/northbridge/intel/i945/gma.c | 15 ++------------- src/northbridge/intel/i945/i945.h | 15 ++------------- src/northbridge/intel/i945/memmap.c | 15 ++------------- src/northbridge/intel/i945/northbridge.c | 15 ++------------- src/northbridge/intel/i945/raminit.c | 15 ++------------- src/northbridge/intel/i945/raminit.h | 15 ++------------- src/northbridge/intel/i945/rcven.c | 15 ++------------- src/northbridge/intel/i945/romstage.c | 16 ++-------------- src/northbridge/intel/ironlake/acpi.c | 16 ++-------------- .../intel/ironlake/acpi/hostbridge.asl | 16 ++-------------- src/northbridge/intel/ironlake/acpi/ironlake.asl | 16 ++-------------- src/northbridge/intel/ironlake/bootblock.c | 14 ++------------ src/northbridge/intel/ironlake/chip.h | 15 ++------------- src/northbridge/intel/ironlake/early_init.c | 15 ++------------- src/northbridge/intel/ironlake/finalize.c | 16 ++-------------- src/northbridge/intel/ironlake/gma.c | 15 ++------------- src/northbridge/intel/ironlake/ironlake.h | 15 ++------------- src/northbridge/intel/ironlake/memmap.c | 15 ++------------- src/northbridge/intel/ironlake/northbridge.c | 15 ++------------- src/northbridge/intel/ironlake/raminit.h | 15 ++------------- src/northbridge/intel/ironlake/romstage.c | 15 ++------------- src/northbridge/intel/ironlake/smi.c | 14 ++------------ src/northbridge/intel/pineview/acpi.c | 16 ++-------------- .../intel/pineview/acpi/hostbridge.asl | 16 ++-------------- src/northbridge/intel/pineview/acpi/peg.asl | 16 ++-------------- src/northbridge/intel/pineview/acpi/pineview.asl | 16 ++-------------- src/northbridge/intel/pineview/bootblock.c | 14 ++------------ src/northbridge/intel/pineview/chip.h | 14 ++------------ src/northbridge/intel/pineview/gma.c | 15 ++------------- src/northbridge/intel/pineview/mchbar_regs.h | 15 ++------------- src/northbridge/intel/pineview/memmap.c | 15 ++------------- src/northbridge/intel/pineview/northbridge.c | 15 ++------------- src/northbridge/intel/pineview/romstage.c | 15 ++------------- src/northbridge/intel/x4x/acpi.c | 16 ++-------------- src/northbridge/intel/x4x/acpi/hostbridge.asl | 16 ++-------------- src/northbridge/intel/x4x/acpi/peg.asl | 16 ++-------------- src/northbridge/intel/x4x/acpi/x4x.asl | 16 ++-------------- src/northbridge/intel/x4x/early_init.c | 15 ++------------- src/northbridge/intel/x4x/gma.c | 15 ++------------- src/northbridge/intel/x4x/memmap.c | 16 ++-------------- src/northbridge/intel/x4x/northbridge.c | 15 ++------------- src/northbridge/intel/x4x/x4x.h | 15 ++------------- 144 files changed, 288 insertions(+), 1896 deletions(-) diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h index d48a6c5d51..52fb8bbe97 100644 --- a/src/northbridge/amd/agesa/BiosCallOuts.h +++ b/src/northbridge/amd/agesa/BiosCallOuts.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CALLOUTS_AMD_AGESA_H #define CALLOUTS_AMD_AGESA_H diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index a8b3dcc5f4..833f390b79 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AGESA_HELPER_H_ #define _AGESA_HELPER_H_ diff --git a/src/northbridge/amd/agesa/dimmSpd.h b/src/northbridge/amd/agesa/dimmSpd.h index 05b6ee3aa5..ac0d0140fa 100644 --- a/src/northbridge/amd/agesa/dimmSpd.h +++ b/src/northbridge/amd/agesa/dimmSpd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DIMMSPD_H_ #define _DIMMSPD_H_ diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 6f51ea1f7a..b96e07c9e9 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h index 2f7110f69b..a9f95f4729 100644 --- a/src/northbridge/amd/agesa/family14/chip.h +++ b/src/northbridge/amd/agesa/family14/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _NB_AGESA_CHIP_H_ #define _NB_AGESA_CHIP_H_ diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 778083f2a8..e9eeb49c82 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a1d345728a..714597e088 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family14/pci_devs.h b/src/northbridge/amd/agesa/family14/pci_devs.h index e110831dc6..5600fddfd7 100644 --- a/src/northbridge/amd/agesa/family14/pci_devs.h +++ b/src/northbridge/amd/agesa/family14/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_FAM14_PCI_DEVS_H_ #define _AMD_FAM14_PCI_DEVS_H_ diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 2c57283e54..db923c5ec9 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 217132f8e4..eda3bab8bc 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h index 1aae0bbfe8..ec6d2e267f 100644 --- a/src/northbridge/amd/agesa/family15tn/chip.h +++ b/src/northbridge/amd/agesa/family15tn/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _NB_AGESA_CHIP_H_ #define _NB_AGESA_CHIP_H_ diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index aab815bb67..761b8b86e7 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 8719443c63..6f0be6eb76 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index eb13e9655b..652d8a3532 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h index 501fdcbd52..45c7393208 100644 --- a/src/northbridge/amd/agesa/family15tn/pci_devs.h +++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_FAM15TN_PCI_DEVS_H_ #define _AMD_FAM15TN_PCI_DEVS_H_ diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index 1346660425..85bc2587ed 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index 34e8ef046d..e3093a7041 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/northbridge/amd/agesa/family16kb/chip.h b/src/northbridge/amd/agesa/family16kb/chip.h index d5f4bb1021..84a13d482f 100644 --- a/src/northbridge/amd/agesa/family16kb/chip.h +++ b/src/northbridge/amd/agesa/family16kb/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _NB_AGESA_CHIP_H_ #define _NB_AGESA_CHIP_H_ diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index 51081837a0..6c751f993d 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index c9a0b13143..38f3dad864 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h index 9a1762200a..9e8414eb68 100644 --- a/src/northbridge/amd/agesa/family16kb/pci_devs.h +++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_FAM16KB_PCI_DEVS_H_ #define _AMD_FAM16KB_PCI_DEVS_H_ diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index c10d4e66a1..a27962972a 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/agesa/nb_common.h b/src/northbridge/amd/agesa/nb_common.h index 3e78155afd..e729f10b6d 100644 --- a/src/northbridge/amd/agesa/nb_common.h +++ b/src/northbridge/amd/agesa/nb_common.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_NB_COMMON_H__ #define __AMD_NB_COMMON_H__ diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 057d404d67..20bcf3cb1d 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _STATE_MACHINE_H_ #define _STATE_MACHINE_H_ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index ed5db82e79..cb2c0ad37b 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/northbridge/amd/pi/00630F01/chip.h b/src/northbridge/amd/pi/00630F01/chip.h index 8ec10c6466..0c022ae157 100644 --- a/src/northbridge/amd/pi/00630F01/chip.h +++ b/src/northbridge/amd/pi/00630F01/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AGESA_00630F01_CHIP_H_ #define _AGESA_00630F01_CHIP_H_ diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index 8dfba7b4ab..27f822932e 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00630F01/iommu.c b/src/northbridge/amd/pi/00630F01/iommu.c index 970e7592bc..c1b294526e 100644 --- a/src/northbridge/amd/pi/00630F01/iommu.c +++ b/src/northbridge/amd/pi/00630F01/iommu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index e34cb71149..5107bf7560 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00630F01/pci_devs.h b/src/northbridge/amd/pi/00630F01/pci_devs.h index 74ad44a1ae..5abc39ec40 100644 --- a/src/northbridge/amd/pi/00630F01/pci_devs.h +++ b/src/northbridge/amd/pi/00630F01/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_00630F01_PCI_DEVS_H_ #define _AMD_00630F01_PCI_DEVS_H_ diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 464ecc621c..7e0407af5c 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/northbridge/amd/pi/00660F01/chip.h b/src/northbridge/amd/pi/00660F01/chip.h index 611f692aa4..724c3078f1 100644 --- a/src/northbridge/amd/pi/00660F01/chip.h +++ b/src/northbridge/amd/pi/00660F01/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PI_FAM15CZ_CHIP_H_ #define _PI_FAM15CZ_CHIP_H_ diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index d6a0b4d3c8..2299c15b24 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 74a5553a96..3896ff91f8 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index 34e8ef046d..e3093a7041 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/northbridge/amd/pi/00730F01/chip.h b/src/northbridge/amd/pi/00730F01/chip.h index de11c20d2e..7684005697 100644 --- a/src/northbridge/amd/pi/00730F01/chip.h +++ b/src/northbridge/amd/pi/00730F01/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PI_00730F01_CHIP_H_ #define _PI_00730F01_CHIP_H_ diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index 7b5f011764..ccbf08a3de 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index 99233025b3..442285a223 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 9f55596433..d324689955 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/amd/pi/00730F01/pci_devs.h b/src/northbridge/amd/pi/00730F01/pci_devs.h index 280546d038..be439f8d8c 100644 --- a/src/northbridge/amd/pi/00730F01/pci_devs.h +++ b/src/northbridge/amd/pi/00730F01/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _AMD_00730F01_PCI_DEVS_H_ #define _AMD_00730F01_PCI_DEVS_H_ diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index d78c575ef3..0b96d3aa32 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "Porting.h" #include "AGESA.h" diff --git a/src/northbridge/amd/pi/dimmSpd.h b/src/northbridge/amd/pi/dimmSpd.h index 05b6ee3aa5..ac0d0140fa 100644 --- a/src/northbridge/amd/pi/dimmSpd.h +++ b/src/northbridge/amd/pi/dimmSpd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DIMMSPD_H_ #define _DIMMSPD_H_ diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h index 46a5c1a58e..8ea5e58a10 100644 --- a/src/northbridge/amd/pi/nb_common.h +++ b/src/northbridge/amd/pi/nb_common.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD_NB_COMMON_H__ #define __AMD_NB_COMMON_H__ diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 009db80215..7d0ac3713b 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 8dd701b9f2..e0340da38a 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 72f630d2a3..8ed5007428 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * converted to C 6/2004 yhlu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This was originally for the e7500, modified for e7501 * The primary differences are that 7501 apparently can diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 9aa6eb4b8e..a623e3519a 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_H #define RAMINIT_H diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index 4ce5bdcfda..e2cbf661ac 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 03daf7b9dc..582771298b 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 576ab96bb6..270ad90c32 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "hostbridge.asl" #include "../gm45.h" diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index 4bf47b35bb..d09d44dfb0 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/northbridge/intel/gm45/acpi/peg.asl b/src/northbridge/intel/gm45/acpi/peg.asl index 6b9d47dd1e..7dc67183b2 100644 --- a/src/northbridge/intel/gm45/acpi/peg.asl +++ b/src/northbridge/intel/gm45/acpi/peg.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PEGP) { diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index 58b99ac40b..b10a75d454 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 6527181586..a8a549d72e 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H #define NORTHBRIDGE_INTEL_GM45_CHIP_H diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e54b0f6539..712932aad5 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 5d3278cb12..eff89bfd3d 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 3ee50b0374..ed92a59257 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 436fb9a10a..25f7518ff8 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 6681b2cc7e..173af1bc5c 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 5d9f6ad1fc..4d88e3609d 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 6855835eca..0d03731d47 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index d4a4828ab6..4782bff4b4 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 165336bf0e..0337c55e58 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index 33027bf8aa..5e03a3ca12 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 6370e703e8..e6582ad53c 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c index 4f86fd9e88..ee6544b9d2 100644 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 6d40fd47d1..38a48d96d3 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 4e3b36268c..c6c092ba2a 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b61774f5bb..5b68a7398a 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 7fa245d466..73164946ad 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index ba86abe18e..aa75e20bc1 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 03b17ab6da..27329a435b 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../haswell.h" #include "hostbridge.asl" diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1a4f33d011..8c155b7a86 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(_HID,EISAID("PNP0A08")) // PCIe diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl index bab9d18e8b..894978dff3 100644 --- a/src/northbridge/intel/haswell/acpi/peg.asl +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PEGP) { diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 903c770d9d..b6cfd0b65d 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index d7ef27df16..678afb6831 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H #define NORTHBRIDGE_INTEL_HASWELL_CHIP_H diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index f61d609f8f..150cf27646 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index d067e0dafb..2c69f0b2f5 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "haswell.h" diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 8c28c53a3f..c6b8fab65a 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 695a39c57d..d5f7b32be5 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/mchbar_regs.h index 701e1bf0be..fdd65daeb6 100644 --- a/src/northbridge/intel/haswell/mchbar_regs.h +++ b/src/northbridge/intel/haswell/mchbar_regs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __HASWELL_MCHBAR_REGS_H__ #define __HASWELL_MCHBAR_REGS_H__ diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 14d569b5bb..fd7576c969 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 9cd7ad4889..fffac52d9c 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index b764aadb30..6f892681d7 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index 14fb12b0f9..70f2c19401 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 40cb80f5f2..9fff58eb21 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index b782d8396c..945ee154d2 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_H #define RAMINIT_H diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index f7d77b7e98..2dc05950fd 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 054c8030a3..856b3e83f2 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* i440bx Northbridge */ Device (NB) diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index fe1f9c82b5..57df23fe44 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index c4df33896d..7231ccbf5d 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 1d0251f0ce..eb0d3b1a35 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 97e7129bdf..e1258e04aa 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index d1497a4dda..33d9419291 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 777d03055e..d4dc1a82e3 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "hostbridge.asl" #include "../i945.h" diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index a017df35b4..94f45ef3da 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (GFX0) { diff --git a/src/northbridge/intel/i945/acpi/peg.asl b/src/northbridge/intel/i945/acpi/peg.asl index 6b9d47dd1e..7dc67183b2 100644 --- a/src/northbridge/intel/i945/acpi/peg.asl +++ b/src/northbridge/intel/i945/acpi/peg.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PEGP) { diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 1f20150ebb..d1cf6db17d 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 900400d304..a437028908 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_I945_CHIP_H #define NORTHBRIDGE_INTEL_I945_CHIP_H diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 14d5e35e1a..bb00b1414d 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 3a9766f93b..368ebd2748 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c index ee77d93dc0..ecdb5ea0c7 100644 --- a/src/northbridge/intel/i945/errata.c +++ b/src/northbridge/intel/i945/errata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "i945.h" diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 252d984d2b..8a19b3e8de 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 11ea580291..56d4370e02 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_I945_H #define NORTHBRIDGE_INTEL_I945_H diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index f528ec0af3..ee9f100fee 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 17b790740e..4fdd282858 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 51ee65d7df..db6e3b8e68 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 56f96ce263..08943e795e 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_H #define RAMINIT_H diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index eebd492979..2271904ed5 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 6d83d0fd31..4649c10a45 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 09d024a2b5..9bb3130c77 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index 8d4ec25139..dfef304885 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(_HID,EISAID("PNP0A08")) // PCIe diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 61db605698..227e9a731e 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../ironlake.h" #include "hostbridge.asl" diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 2f9f7da916..f66c9ca8e0 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index 84f8f62a38..087c28aea4 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H #define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index a349dcdc69..7c522e005c 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index 23771adc2d..fe9753dbb6 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ironlake.h" diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 42bf7f9507..c8bbbfd00e 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 12166eb8ce..4b4d736a0f 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index e43fcde824..136d57212b 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index b04344f17e..4144758e9a 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h index b4560373eb..44e2299d66 100644 --- a/src/northbridge/intel/ironlake/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_H #define RAMINIT_H diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index e8e5c56ece..749849e4f4 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/ironlake/smi.c b/src/northbridge/intel/ironlake/smi.c index 73cd06281b..e6219b512e 100644 --- a/src/northbridge/intel/ironlake/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 9501d65801..54c42cf481 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 4de9302802..05ed293dd3 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/northbridge/intel/pineview/acpi/peg.asl b/src/northbridge/intel/pineview/acpi/peg.asl index 6b9d47dd1e..7dc67183b2 100644 --- a/src/northbridge/intel/pineview/acpi/peg.asl +++ b/src/northbridge/intel/pineview/acpi/peg.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PEGP) { diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 89c9fbf19c..ebb6eb9bdd 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "hostbridge.asl" #include "../iomap.h" diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 83917c2332..d8d19380d8 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/pineview/chip.h b/src/northbridge/intel/pineview/chip.h index b4a5ee1dbd..db3aa19707 100644 --- a/src/northbridge/intel/pineview/chip.h +++ b/src/northbridge/intel/pineview/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H #define NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 39ce5e6861..d398b55347 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/pineview/mchbar_regs.h b/src/northbridge/intel/pineview/mchbar_regs.h index dc9a1f7ed6..f331f1d2f2 100644 --- a/src/northbridge/intel/pineview/mchbar_regs.h +++ b/src/northbridge/intel/pineview/mchbar_regs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PINEVIEW_MCHBAR_REGS_H__ #define __PINEVIEW_MCHBAR_REGS_H__ diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 58dea581cd..4717b76a55 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 87443ca2f9..36f39b0fcd 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index f2dab268bb..eddfc668e9 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index ddd26e865f..6da2fd0d54 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index caa490c836..0126aaf0a7 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/northbridge/intel/x4x/acpi/peg.asl b/src/northbridge/intel/x4x/acpi/peg.asl index d93ceb1fa5..07baf85ad6 100644 --- a/src/northbridge/intel/x4x/acpi/peg.asl +++ b/src/northbridge/intel/x4x/acpi/peg.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PEGP) { diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 947b67865b..e9761678ef 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "hostbridge.asl" #include "../iomap.h" diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 8c9918e1ca..4cfc37ae6c 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 651b07cf88..f5335eccb0 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index bcba561f80..233f5ecbd7 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 63243f1a74..6397631c83 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 9b86e74016..d6d72f436d 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NORTHBRIDGE_INTEL_X4X_H__ #define __NORTHBRIDGE_INTEL_X4X_H__ From 32859fccc6e472a2bf669c206f1c39c8af967c46 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:27 +0200 Subject: [PATCH 0821/1463] src/include: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2fa3bad88bb5b068baa1cfc6bbcddaabb09da1c5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40053 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/include/adainit.h | 14 ++------------ src/include/assert.h | 15 ++------------- src/include/base3.h | 15 ++------------- src/include/bcd.h | 15 ++------------- src/include/boardid.h | 15 ++------------- src/include/boot_device.h | 15 ++------------- src/include/bootblock_common.h | 15 ++------------- src/include/bootmem.h | 15 ++------------- src/include/bootmode.h | 15 ++------------- src/include/bootsplash.h | 15 ++------------- src/include/bootstate.h | 15 ++------------- src/include/cbfs.h | 15 ++------------- src/include/cbmem.h | 15 ++------------- src/include/console/cbmem_console.h | 15 ++------------- src/include/console/console.h | 15 ++------------- src/include/console/flash.h | 15 ++------------- src/include/console/ne2k.h | 15 ++------------- src/include/console/spi.h | 15 ++------------- src/include/console/streams.h | 14 ++------------ src/include/console/uart.h | 15 ++------------- src/include/console/usb.h | 15 ++------------- src/include/console/vtxprintf.h | 15 ++------------- src/include/cper.h | 15 ++------------- src/include/cpu/amd/amd64_save_state.h | 14 ++------------ src/include/cpu/amd/msr.h | 15 ++------------- src/include/cpu/intel/em64t100_save_state.h | 14 ++------------ src/include/cpu/intel/em64t101_save_state.h | 14 ++------------ src/include/cpu/intel/fsb.h | 14 ++------------ src/include/cpu/intel/microcode.h | 15 ++------------- src/include/cpu/intel/smm_reloc.h | 14 ++------------ src/include/cpu/intel/speedstep.h | 16 ++-------------- src/include/cpu/intel/turbo.h | 16 ++-------------- src/include/cpu/x86/cache.h | 15 ++------------- src/include/cpu/x86/cr.h | 15 ++------------- src/include/cpu/x86/gdt.h | 14 ++------------ src/include/cpu/x86/legacy_save_state.h | 14 ++------------ src/include/cpu/x86/mp.h | 15 ++------------- src/include/cpu/x86/name.h | 15 ++------------- src/include/cpu/x86/pae.h | 15 ++------------- src/include/cpu/x86/smi_deprecated.h | 14 ++------------ src/include/cpu/x86/smm.h | 15 ++------------- src/include/crc_byte.h | 15 ++------------- src/include/device/azalia.h | 15 ++------------- src/include/device/azalia_device.h | 15 ++------------- src/include/device/dram/ddr4.h | 15 ++------------- src/include/device/i2c.h | 15 ++------------- src/include/device/i2c_bus.h | 14 ++------------ src/include/device/i2c_simple.h | 15 ++------------- src/include/device/mmio.h | 15 ++------------- src/include/device/pci_ehci.h | 15 ++------------- src/include/device/pci_mmio_cfg.h | 15 ++------------- src/include/device/pci_ops.h | 15 ++------------- src/include/device/pci_type.h | 14 ++------------ src/include/device/pnp_ops.h | 15 ++------------- src/include/device/pnp_type.h | 14 ++------------ src/include/device/smbus_host.h | 14 ++------------ src/include/device/spi.h | 15 ++------------- src/include/edid.h | 15 ++------------- src/include/efi/efi_datatype.h | 15 ++------------- src/include/elog.h | 15 ++------------- src/include/fmap.h | 15 ++------------- src/include/gic.h | 15 ++------------- src/include/gpio.h | 15 ++------------- src/include/halt.h | 16 ++-------------- src/include/imd.h | 15 ++------------- src/include/inttypes.h | 14 ++------------ src/include/lib.h | 15 ++------------- src/include/memlayout.h | 15 ++------------- src/include/memrange.h | 15 ++------------- src/include/mrc_cache.h | 15 ++------------- src/include/nhlt.h | 15 ++------------- src/include/option.h | 14 ++------------ src/include/pc80/i8254.h | 15 ++------------- src/include/pc80/i8259.h | 15 ++------------- src/include/program_loading.h | 15 ++------------- src/include/ramdetect.h | 14 ++------------ src/include/random.h | 15 ++------------- src/include/reg_script.h | 15 ++------------- src/include/region_file.h | 15 ++------------- src/include/rmodule.h | 15 ++------------- src/include/romstage_handoff.h | 15 ++------------- src/include/rtc.h | 15 ++------------- src/include/rules.h | 15 ++------------- src/include/sar.h | 15 ++------------- src/include/smbios.h | 15 ++------------- src/include/smmstore.h | 15 ++------------- src/include/spd_bin.h | 15 ++------------- src/include/spd_ddr2.h | 15 ++------------- src/include/spi_sdcard.h | 15 ++------------- src/include/stage_cache.h | 15 ++------------- src/include/stdint.h | 14 ++------------ src/include/superio/conf_mode.h | 15 ++------------- src/include/superio/hwm5_conf.h | 14 ++------------ src/include/symbols.h | 15 ++------------- src/include/thread.h | 15 ++------------- src/include/timer.h | 15 ++------------- src/include/timestamp.h | 15 ++------------- src/include/trace.h | 15 ++------------- src/include/types.h | 15 ++------------- src/include/uuid.h | 15 ++------------- src/include/wrdd.h | 15 ++------------- 101 files changed, 202 insertions(+), 1297 deletions(-) diff --git a/src/include/adainit.h b/src/include/adainit.h index 03671eea56..5042b6b1f7 100644 --- a/src/include/adainit.h +++ b/src/include/adainit.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ADAINIT_H #define _ADAINIT_H diff --git a/src/include/assert.h b/src/include/assert.h index fbaf11a4d6..492629dd30 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __ASSERT_H__ #define __ASSERT_H__ diff --git a/src/include/base3.h b/src/include/base3.h index b14028a8d5..d170fc5d64 100644 --- a/src/include/base3.h +++ b/src/include/base3.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SRC_INCLUDE_BASE3_H__ #define __SRC_INCLUDE_BASE3_H__ diff --git a/src/include/bcd.h b/src/include/bcd.h index 06dfb0349f..ebb6e02d60 100644 --- a/src/include/bcd.h +++ b/src/include/bcd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BCD_H_ #define _BCD_H_ diff --git a/src/include/boardid.h b/src/include/boardid.h index 26725c7a68..6e9b24c544 100644 --- a/src/include/boardid.h +++ b/src/include/boardid.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __INCLUDE_BOARDID_H__ #define __INCLUDE_BOARDID_H__ diff --git a/src/include/boot_device.h b/src/include/boot_device.h index 9f26c161f4..4707331ce6 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BOOT_DEVICE_H_ #define _BOOT_DEVICE_H_ diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 04a22f6543..a3b5e93d56 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BOOTBLOCK_COMMON_H #define __BOOTBLOCK_COMMON_H diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 2763f1aa8b..6c869fafb8 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BOOTMEM_H #define BOOTMEM_H diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 89e2c2cc8a..42cc0920ff 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BOOTMODE_H__ #define __BOOTMODE_H__ diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index ef7b53eb8f..5e860e9950 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BOOTSPLASH_H__ #define __BOOTSPLASH_H__ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index bb2242bd59..b82f95c4ba 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BOOTSTATE_H #define BOOTSTATE_H diff --git a/src/include/cbfs.h b/src/include/cbfs.h index feb73a1310..97539b5b7d 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CBFS_H_ #define _CBFS_H_ diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a67c5b84da..77fff07684 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CBMEM_H_ #define _CBMEM_H_ diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 42e05e75ad..a291db862d 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ diff --git a/src/include/console/console.h b/src/include/console/console.h index 96fc8b5faf..c68caf0e00 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CONSOLE_CONSOLE_H_ #define CONSOLE_CONSOLE_H_ diff --git a/src/include/console/flash.h b/src/include/console/flash.h index 51ac460f1c..b66234d83e 100644 --- a/src/include/console/flash.h +++ b/src/include/console/flash.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CONSOLE_FLASH_H #define CONSOLE_FLASH_H 1 diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index fe9e471d42..f379f558b8 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _NE2K_H__ #define _NE2K_H__ diff --git a/src/include/console/spi.h b/src/include/console/spi.h index 29c500d769..757107571a 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CONSOLE_SPI_H #define CONSOLE_SPI_H 1 diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 6e944a64b3..6d6df0efa4 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CONSOLE_STREAMS_H_ #define _CONSOLE_STREAMS_H_ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 3e38bc8c7f..1bd6ef0f6e 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H diff --git a/src/include/console/usb.h b/src/include/console/usb.h index e7871c404d..b7bc7f4a6e 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CONSOLE_USB_H_ #define _CONSOLE_USB_H_ diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index 9babd89322..9ebc842b3d 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __CONSOLE_VTXPRINTF_H #define __CONSOLE_VTXPRINTF_H diff --git a/src/include/cper.h b/src/include/cper.h index 298fe28b24..e25cada700 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CPER_H_ #define _CPER_H_ diff --git a/src/include/cpu/amd/amd64_save_state.h b/src/include/cpu/amd/amd64_save_state.h index 14149ece37..967e491b6f 100644 --- a/src/include/cpu/amd/amd64_save_state.h +++ b/src/include/cpu/amd/amd64_save_state.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __AMD64_SAVE_STATE_H__ #define __AMD64_SAVE_STATE_H__ diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index d5804d6853..4fe3a6c9e3 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file applies to AMD64 products. * The definitions come from the AMD64 Programmers Manual vol2 diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index 6e8e1d9745..4288ded317 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __EM64T100_SAVE_STATE_H__ #define __EM64T100_SAVE_STATE_H__ diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 5d3f9edf9d..d0b7d251f7 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __EM64T101_SAVE_STATE_H__ #define __EM64T101_SAVE_STATE_H__ diff --git a/src/include/cpu/intel/fsb.h b/src/include/cpu/intel/fsb.h index 825cdd5761..d8476e424c 100644 --- a/src/include/cpu/intel/fsb.h +++ b/src/include/cpu/intel/fsb.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_INTEL_FSB_H #define CPU_INTEL_FSB_H diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index c4e15c5064..bdd0b46d51 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __CPU__INTEL__MICROCODE__ #define __CPU__INTEL__MICROCODE__ diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index bef8d4eed7..26f4bbe64b 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __INTEL_SMM_RELOC_H__ #define __INTEL_SMM_RELOC_H__ diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 26c74655be..58566389da 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_INTEL_SPEEDSTEP_H #define CPU_INTEL_SPEEDSTEP_H diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 191bf2e631..2933b37dde 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CPU_INTEL_TURBO_H #define _CPU_INTEL_TURBO_H diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 2b1418fcb8..7ff5ef5158 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index e790a1bf85..38482832e6 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -1,17 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ #ifndef CPU_X86_CR_H #define CPU_X86_CR_H diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index 07d7b74cab..b4d01035f6 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_X86_GDT #define CPU_X86_GDT diff --git a/src/include/cpu/x86/legacy_save_state.h b/src/include/cpu/x86/legacy_save_state.h index 7803db77de..b1c8510e5b 100644 --- a/src/include/cpu/x86/legacy_save_state.h +++ b/src/include/cpu/x86/legacy_save_state.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __X86_LEGACY_SAVE_STATE_H__ #define __X86_LEGACY_SAVE_STATE_H__ diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 3a22deea76..a0e55d3f0a 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _X86_MP_H_ #define _X86_MP_H_ diff --git a/src/include/cpu/x86/name.h b/src/include/cpu/x86/name.h index 0b8ee92334..bcb2d316d1 100644 --- a/src/include/cpu/x86/name.h +++ b/src/include/cpu/x86/name.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_X86_NAME_H #define CPU_X86_NAME_H diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index b188f63ddb..8889bb24cc 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_X86_PAE_H #define CPU_X86_PAE_H diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h index 2812bb0eab..2b1da751dd 100644 --- a/src/include/cpu/x86/smi_deprecated.h +++ b/src/include/cpu/x86/smi_deprecated.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __X86_SMI_DEPRECATED_H__ #define __X86_SMI_DEPRECATED_H__ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 8abf5d5930..0b76708343 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index dacb8869c5..5d1d0192a4 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CRC_BYTE_H #define CRC_BYTE_H diff --git a/src/include/device/azalia.h b/src/include/device/azalia.h index c85be88077..58f47c39a4 100644 --- a/src/include/device/azalia.h +++ b/src/include/device/azalia.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef AZALIA_H_ #define AZALIA_H_ diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 00899f3c24..6f82e0e5a5 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DEVICE_AZALIA_H #define DEVICE_AZALIA_H diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 4a371b5d67..a5a6ce6eb6 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * JEDEC Standard No. 21-C diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index d3637212f1..3680bf4412 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DEVICE_I2C_H_ #define _DEVICE_I2C_H_ diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 81eae11e2f..89d22a352c 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DEVICE_I2C_BUS_H_ #define _DEVICE_I2C_BUS_H_ diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index 3651d58cf2..c1400035ae 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DEVICE_I2C_SIMPLE_H_ #define _DEVICE_I2C_SIMPLE_H_ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 524284a077..b4f2ab639f 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DEVICE_MMIO_H__ #define __DEVICE_MMIO_H__ diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index a0e0269628..d3dde6e803 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PCI_EHCI_H_ #define _PCI_EHCI_H_ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index e46d45da99..34c68bd84b 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PCI_MMIO_CFG_H #define _PCI_MMIO_CFG_H diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 3757d3073b..e17dc37a65 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PCI_OPS_H #define PCI_OPS_H diff --git a/src/include/device/pci_type.h b/src/include/device/pci_type.h index 4d8c2a3d08..088693c8b2 100644 --- a/src/include/device/pci_type.h +++ b/src/include/device/pci_type.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DEVICE_PCI_TYPE_H #define DEVICE_PCI_TYPE_H diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 61d05a86ad..93a5dc8c47 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DEVICE_PNP_OPS_H__ #define __DEVICE_PNP_OPS_H__ diff --git a/src/include/device/pnp_type.h b/src/include/device/pnp_type.h index dc2d27c84d..14dc40c3d4 100644 --- a/src/include/device/pnp_type.h +++ b/src/include/device/pnp_type.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DEVICE_PNP_TYPE_H__ #define __DEVICE_PNP_TYPE_H__ diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index c12718d195..03b2a5ab65 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DEVICE_SMBUS_HOST_H__ #define __DEVICE_SMBUS_HOST_H__ diff --git a/src/include/device/spi.h b/src/include/device/spi.h index f8ccca1185..cffe721042 100644 --- a/src/include/device/spi.h +++ b/src/include/device/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DEVICE_SPI_H__ #define __DEVICE_SPI_H__ diff --git a/src/include/edid.h b/src/include/edid.h index 4d5839f7a3..acfd2e50bb 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EDID_H #define EDID_H diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index 70bd791855..2d516a9874 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Create EFI equivalent datatype in coreboot based on UEFI specification */ #ifndef __EFI_DATATYPE_H__ diff --git a/src/include/elog.h b/src/include/elog.h index 0b86e09d7a..68a4842feb 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ELOG_H_ #define ELOG_H_ diff --git a/src/include/fmap.h b/src/include/fmap.h index e6f1d05740..beb7957472 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _FMAP_H_ #define _FMAP_H_ diff --git a/src/include/gic.h b/src/include/gic.h index b37c2499b0..d4ec558a7f 100644 --- a/src/include/gic.h +++ b/src/include/gic.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GIC_H #define GIC_H diff --git a/src/include/gpio.h b/src/include/gpio.h index e2de6a18de..0cbcedf5f1 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SRC_INCLUDE_GPIO_H__ #define __SRC_INCLUDE_GPIO_H__ diff --git a/src/include/halt.h b/src/include/halt.h index 1c1cb26b46..3bbca0d192 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __HALT_H__ #define __HALT_H__ diff --git a/src/include/imd.h b/src/include/imd.h index 3d9ca1791f..0bd0f35a51 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _IMD_H_ #define _IMD_H_ diff --git a/src/include/inttypes.h b/src/include/inttypes.h index 4e2476dd03..8b6f6b53ca 100644 --- a/src/include/inttypes.h +++ b/src/include/inttypes.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTTYPES_H #define INTTYPES_H diff --git a/src/include/lib.h b/src/include/lib.h index f57221ca79..168d8cab55 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file is for "nuisance prototypes" that have no other home. */ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index bf4b2c5323..0cd465bda6 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file contains macro definitions for memlayout.ld linker scripts. */ diff --git a/src/include/memrange.h b/src/include/memrange.h index dcab791b29..2579f20c18 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MEMRANGE_H_ #define MEMRANGE_H_ diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 1b4840e04f..1cd0148929 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMON_MRC_CACHE_H_ #define _COMMON_MRC_CACHE_H_ diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 9ef95a6390..75849d5008 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _NHLT_H_ #define _NHLT_H_ diff --git a/src/include/option.h b/src/include/option.h index ba7cd0c1a4..6622a0a1fa 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _OPTION_H_ #define _OPTION_H_ diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index 6936d4bdaf..168b7785cc 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PC80_I8254_H #define PC80_I8254_H diff --git a/src/include/pc80/i8259.h b/src/include/pc80/i8259.h index ef64f214fc..dde86cc11c 100644 --- a/src/include/pc80/i8259.h +++ b/src/include/pc80/i8259.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PC80_I8259_H #define PC80_I8259_H diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 9e9b222993..a69150d39c 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PROGRAM_LOADING_H #define PROGRAM_LOADING_H diff --git a/src/include/ramdetect.h b/src/include/ramdetect.h index e2a7eced67..832d55de8f 100644 --- a/src/include/ramdetect.h +++ b/src/include/ramdetect.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* diff --git a/src/include/random.h b/src/include/random.h index a32a779034..24b1d7ff67 100644 --- a/src/include/random.h +++ b/src/include/random.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _RANDOM_H_ #define _RANDOM_H_ diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 9759167b10..e26ff7997e 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef REG_SCRIPT_H #define REG_SCRIPT_H diff --git a/src/include/region_file.h b/src/include/region_file.h index baae9ea050..a0688fe38c 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef REGION_FILE_H #define REGION_FILE_H diff --git a/src/include/rmodule.h b/src/include/rmodule.h index c066d7b0a8..3d5fe31694 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RMODULE_H #define RMODULE_H diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 481af804a6..6e03195619 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ROMSTAGE_HANDOFF_H #define ROMSTAGE_HANDOFF_H diff --git a/src/include/rtc.h b/src/include/rtc.h index 2c0704ecf6..0421a98613 100644 --- a/src/include/rtc.h +++ b/src/include/rtc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _RTC_H_ #define _RTC_H_ diff --git a/src/include/rules.h b/src/include/rules.h index fa60ede181..92603db4ba 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _RULES_H #define _RULES_H diff --git a/src/include/sar.h b/src/include/sar.h index 3659e76fb1..5040e14fce 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SAR_H_ #define _SAR_H_ diff --git a/src/include/smbios.h b/src/include/smbios.h index 4e94fc45f2..184b2c8fa5 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SMBIOS_H #define SMBIOS_H diff --git a/src/include/smmstore.h b/src/include/smmstore.h index d367c2c767..af07ff0014 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SMMSTORE_H_ #define _SMMSTORE_H_ diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 5027309b40..3b4d7ad671 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SPD_BIN_H #define SPD_BIN_H diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h index 086f3323be..f4eaf2803c 100644 --- a/src/include/spd_ddr2.h +++ b/src/include/spd_ddr2.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SPD_DDR2_H__ #define __SPD_DDR2_H__ diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h index ac91530279..30b9c811c9 100644 --- a/src/include/spi_sdcard.h +++ b/src/include/spi_sdcard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SPI_SDCARD_H_ #define _SPI_SDCARD_H_ diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index f379bc51db..97edf9137b 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _STAGE_CACHE_H_ #define _STAGE_CACHE_H_ diff --git a/src/include/stdint.h b/src/include/stdint.h index b3e4cb31ec..61defd8e33 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef STDINT_H #define STDINT_H diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index 171c38e14b..43199bff58 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DEVICE_PNP_CONF_MODE_H #define DEVICE_PNP_CONF_MODE_H diff --git a/src/include/superio/hwm5_conf.h b/src/include/superio/hwm5_conf.h index bfec0fdef9..d90aa76482 100644 --- a/src/include/superio/hwm5_conf.h +++ b/src/include/superio/hwm5_conf.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DEVICE_PNP_HWM5_CONF_H #define DEVICE_PNP_HWM5_CONF_H diff --git a/src/include/symbols.h b/src/include/symbols.h index e37405d4a1..bdb8a9ae22 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SYMBOLS_H #define __SYMBOLS_H diff --git a/src/include/thread.h b/src/include/thread.h index bd5750b2c2..54d95ff34f 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THREAD_H_ #define THREAD_H_ diff --git a/src/include/timer.h b/src/include/timer.h index 4fa24fb35a..d890c9146f 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef TIMER_H #define TIMER_H diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 7c723698db..b2352b7d11 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TIMESTAMP_H__ #define __TIMESTAMP_H__ diff --git a/src/include/trace.h b/src/include/trace.h index 07b6570326..b90a501660 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TRACE_H #define __TRACE_H diff --git a/src/include/types.h b/src/include/types.h index 40209e0291..7b27273484 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TYPES_H #define __TYPES_H diff --git a/src/include/uuid.h b/src/include/uuid.h index c8604bb3b0..d51bd30155 100644 --- a/src/include/uuid.h +++ b/src/include/uuid.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _UUID_H_ #define _UUID_H_ diff --git a/src/include/wrdd.h b/src/include/wrdd.h index a79046d06f..ee88c94c0a 100644 --- a/src/include/wrdd.h +++ b/src/include/wrdd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _WRDD_H_ #define _WRDD_H_ From fc0af1e18378e1aed8ec6eb5f08305b589d6cc7c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:35 +0200 Subject: [PATCH 0822/1463] mainboard/lippert: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I514d0a10990911e4e1cf731e64f1f8a33af8a7a6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40086 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../lippert/frontrunner-af/BiosCallOuts.c | 15 ++------------- .../lippert/frontrunner-af/OemCustomize.c | 15 ++------------- src/mainboard/lippert/frontrunner-af/OptionsIds.h | 15 ++------------- .../lippert/frontrunner-af/acpi/routing.asl | 15 ++------------- .../lippert/frontrunner-af/acpi/sata.asl | 15 ++------------- .../lippert/frontrunner-af/acpi/superio.asl | 15 +++------------ src/mainboard/lippert/frontrunner-af/acpi/usb.asl | 15 ++------------- .../lippert/frontrunner-af/acpi_tables.c | 15 ++------------- src/mainboard/lippert/frontrunner-af/bootblock.c | 15 ++------------- src/mainboard/lippert/frontrunner-af/buildOpts.c | 15 ++------------- src/mainboard/lippert/frontrunner-af/dsdt.asl | 15 ++------------- src/mainboard/lippert/frontrunner-af/irq_tables.c | 15 ++------------- src/mainboard/lippert/frontrunner-af/mainboard.c | 15 ++------------- src/mainboard/lippert/frontrunner-af/mptable.c | 15 ++------------- .../lippert/frontrunner-af/platform_cfg.h | 15 ++------------- src/mainboard/lippert/frontrunner-af/sema.c | 14 ++------------ src/mainboard/lippert/frontrunner-af/sema.h | 14 ++------------ src/mainboard/lippert/toucan-af/BiosCallOuts.c | 15 ++------------- src/mainboard/lippert/toucan-af/OemCustomize.c | 15 ++------------- src/mainboard/lippert/toucan-af/OptionsIds.h | 15 ++------------- src/mainboard/lippert/toucan-af/acpi/routing.asl | 15 ++------------- src/mainboard/lippert/toucan-af/acpi/sata.asl | 15 ++------------- src/mainboard/lippert/toucan-af/acpi/superio.asl | 15 +++------------ src/mainboard/lippert/toucan-af/acpi/usb.asl | 15 ++------------- src/mainboard/lippert/toucan-af/acpi_tables.c | 15 ++------------- src/mainboard/lippert/toucan-af/bootblock.c | 15 ++------------- src/mainboard/lippert/toucan-af/buildOpts.c | 15 ++------------- src/mainboard/lippert/toucan-af/dsdt.asl | 15 ++------------- src/mainboard/lippert/toucan-af/irq_tables.c | 15 ++------------- src/mainboard/lippert/toucan-af/mainboard.c | 15 ++------------- src/mainboard/lippert/toucan-af/mptable.c | 15 ++------------- src/mainboard/lippert/toucan-af/platform_cfg.h | 15 ++------------- 32 files changed, 66 insertions(+), 412 deletions(-) diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index 536ea44907..f06d94995f 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c index 6f2ba23fc3..486d237931 100644 --- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c +++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/frontrunner-af/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/lippert/frontrunner-af/OptionsIds.h +++ b/src/mainboard/lippert/frontrunner-af/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index b09b7b2eda..5ce62c7cff 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/lippert/frontrunner-af/acpi/sata.asl b/src/mainboard/lippert/frontrunner-af/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/sata.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/lippert/frontrunner-af/acpi/superio.asl b/src/mainboard/lippert/frontrunner-af/acpi/superio.asl index 0ad6829902..83492168da 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/superio.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/superio.asl @@ -1,17 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* * SuperI/O devices - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* PS/2 Keyboard */ diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index 77a4855274..a53490323a 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/bootblock.c index a9a24a91c1..74646a7635 100644 --- a/src/mainboard/lippert/frontrunner-af/bootblock.c +++ b/src/mainboard/lippert/frontrunner-af/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index cbf94e9c3e..0dab7eb079 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 8efa56f816..2c56e08464 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 5285bf48d3..ae33bcbb5d 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 463262dd61..bbd4820896 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 7bd11ded16..63a1536fcb 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index 757d8daa0e..524d90e6b9 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/frontrunner-af/sema.h b/src/mainboard/lippert/frontrunner-af/sema.h index ea8ee31e4e..b444c7b233 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.h +++ b/src/mainboard/lippert/frontrunner-af/sema.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __LIPPERT_SEMA_H__ #define __LIPPERT_SEMA_H__ diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 3f90631448..9b26683069 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c index 7674021e02..5d1e107fa4 100644 --- a/src/mainboard/lippert/toucan-af/OemCustomize.c +++ b/src/mainboard/lippert/toucan-af/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/lippert/toucan-af/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ b/src/mainboard/lippert/toucan-af/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/lippert/toucan-af/acpi/routing.asl b/src/mainboard/lippert/toucan-af/acpi/routing.asl index 4f31f6dc4c..ae3c0008bb 100644 --- a/src/mainboard/lippert/toucan-af/acpi/routing.asl +++ b/src/mainboard/lippert/toucan-af/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/lippert/toucan-af/acpi/sata.asl b/src/mainboard/lippert/toucan-af/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/lippert/toucan-af/acpi/sata.asl +++ b/src/mainboard/lippert/toucan-af/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/lippert/toucan-af/acpi/superio.asl b/src/mainboard/lippert/toucan-af/acpi/superio.asl index 0ad6829902..83492168da 100644 --- a/src/mainboard/lippert/toucan-af/acpi/superio.asl +++ b/src/mainboard/lippert/toucan-af/acpi/superio.asl @@ -1,17 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* * SuperI/O devices - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* PS/2 Keyboard */ diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl index 77a4855274..a53490323a 100644 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ b/src/mainboard/lippert/toucan-af/acpi/usb.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/toucan-af/bootblock.c b/src/mainboard/lippert/toucan-af/bootblock.c index b5625f5008..72400c479d 100644 --- a/src/mainboard/lippert/toucan-af/bootblock.c +++ b/src/mainboard/lippert/toucan-af/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index cbf94e9c3e..0dab7eb079 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index c494d7060c..14aa8654b9 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 0993baaf8a..1af7ea53c5 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 463262dd61..bbd4820896 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index 122191411f..1c443ed8f1 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ From b1c8369c191a88a229c579f95040c92df39e272b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:46 +0200 Subject: [PATCH 0823/1463] mainboard/opencellular: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ia4782dccd8c95e173c7920be06e46a611a48a0cc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40089 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../opencellular/elgon/bdk_devicetree.c | 16 ++-------------- src/mainboard/opencellular/elgon/bootblock.c | 15 ++------------- src/mainboard/opencellular/elgon/death.c | 16 ++-------------- src/mainboard/opencellular/elgon/gbcv2.dts | 15 ++------------- src/mainboard/opencellular/elgon/mainboard.c | 15 +++------------ src/mainboard/opencellular/elgon/mainboard.h | 16 ++-------------- src/mainboard/opencellular/elgon/romstage.c | 16 ++-------------- 7 files changed, 15 insertions(+), 94 deletions(-) diff --git a/src/mainboard/opencellular/elgon/bdk_devicetree.c b/src/mainboard/opencellular/elgon/bdk_devicetree.c index 7836c21485..b3c903ab17 100644 --- a/src/mainboard/opencellular/elgon/bdk_devicetree.c +++ b/src/mainboard/opencellular/elgon/bdk_devicetree.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // This file is automatically generated. // DO NOT EDIT BY HAND. diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c index cce1afa243..110807c21a 100644 --- a/src/mainboard/opencellular/elgon/bootblock.c +++ b/src/mainboard/opencellular/elgon/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/opencellular/elgon/death.c b/src/mainboard/opencellular/elgon/death.c index 72be17dc2a..ecd661b578 100644 --- a/src/mainboard/opencellular/elgon/death.c +++ b/src/mainboard/opencellular/elgon/death.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/opencellular/elgon/gbcv2.dts b/src/mainboard/opencellular/elgon/gbcv2.dts index 04453a2ab1..3cdc7eb4bd 100644 --- a/src/mainboard/opencellular/elgon/gbcv2.dts +++ b/src/mainboard/opencellular/elgon/gbcv2.dts @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /dts-v1/; diff --git a/src/mainboard/opencellular/elgon/mainboard.c b/src/mainboard/opencellular/elgon/mainboard.c index 14411089e5..c18aeebc68 100644 --- a/src/mainboard/opencellular/elgon/mainboard.c +++ b/src/mainboard/opencellular/elgon/mainboard.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/mainboard/opencellular/elgon/mainboard.h b/src/mainboard/opencellular/elgon/mainboard.h index 2e4d01cec4..a29ceb5008 100644 --- a/src/mainboard/opencellular/elgon/mainboard.h +++ b/src/mainboard/opencellular/elgon/mainboard.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ELGON_GPIO_ERROR_LED 11 #define ELGON_GPIO_SPI_MUX 24 diff --git a/src/mainboard/opencellular/elgon/romstage.c b/src/mainboard/opencellular/elgon/romstage.c index 3e4ba490da..54fa97d927 100644 --- a/src/mainboard/opencellular/elgon/romstage.c +++ b/src/mainboard/opencellular/elgon/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 560796c750feb0479e3f5c4b0ad7417e4b6ea2bd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:52 +0200 Subject: [PATCH 0824/1463] mainboard/pcengines: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I64f620205d79b0c4f9a111881b04ac955aecdd91 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40091 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/pcengines/apu1/BiosCallOuts.c | 15 ++------------- src/mainboard/pcengines/apu1/OemCustomize.c | 15 ++------------- src/mainboard/pcengines/apu1/OptionsIds.h | 15 ++------------- src/mainboard/pcengines/apu1/acpi/buttons.asl | 15 +++------------ src/mainboard/pcengines/apu1/acpi/gpe.asl | 15 ++------------- src/mainboard/pcengines/apu1/acpi/gpio.asl | 15 +++------------ src/mainboard/pcengines/apu1/acpi/leds.asl | 15 +++------------ src/mainboard/pcengines/apu1/acpi/mainboard.asl | 15 ++------------- src/mainboard/pcengines/apu1/acpi/routing.asl | 15 ++------------- src/mainboard/pcengines/apu1/acpi/sata.asl | 15 ++------------- src/mainboard/pcengines/apu1/acpi/sleep.asl | 15 ++------------- src/mainboard/pcengines/apu1/acpi/superio.asl | 14 ++------------ src/mainboard/pcengines/apu1/acpi/usb_oc.asl | 15 ++------------- src/mainboard/pcengines/apu1/acpi_tables.c | 15 ++------------- src/mainboard/pcengines/apu1/bootblock.c | 14 ++------------ src/mainboard/pcengines/apu1/buildOpts.c | 15 ++------------- src/mainboard/pcengines/apu1/dsdt.asl | 15 ++------------- src/mainboard/pcengines/apu1/gpio_ftns.c | 15 ++------------- src/mainboard/pcengines/apu1/gpio_ftns.h | 15 ++------------- src/mainboard/pcengines/apu1/irq_tables.c | 15 ++------------- src/mainboard/pcengines/apu1/mainboard.c | 15 ++------------- src/mainboard/pcengines/apu1/mptable.c | 15 ++------------- src/mainboard/pcengines/apu1/platform_cfg.h | 15 ++------------- src/mainboard/pcengines/apu1/romstage.c | 15 ++------------- src/mainboard/pcengines/apu2/BiosCallOuts.c | 15 ++------------- src/mainboard/pcengines/apu2/OemCustomize.c | 15 ++------------- src/mainboard/pcengines/apu2/acpi/gpe.asl | 15 ++------------- src/mainboard/pcengines/apu2/acpi/mainboard.asl | 15 ++------------- src/mainboard/pcengines/apu2/acpi/routing.asl | 15 ++------------- src/mainboard/pcengines/apu2/acpi/si.asl | 15 ++------------- src/mainboard/pcengines/apu2/acpi/sleep.asl | 15 ++------------- src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 15 ++------------- src/mainboard/pcengines/apu2/acpi_tables.c | 15 ++------------- src/mainboard/pcengines/apu2/bootblock.c | 14 ++------------ src/mainboard/pcengines/apu2/dsdt.asl | 15 ++------------- src/mainboard/pcengines/apu2/gpio_ftns.c | 15 ++------------- src/mainboard/pcengines/apu2/gpio_ftns.h | 15 ++------------- src/mainboard/pcengines/apu2/irq_tables.c | 15 ++------------- src/mainboard/pcengines/apu2/mainboard.c | 15 ++------------- src/mainboard/pcengines/apu2/mptable.c | 15 ++------------- src/mainboard/pcengines/apu2/romstage.c | 15 ++------------- 41 files changed, 85 insertions(+), 527 deletions(-) diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index d2a598aae0..7768b81b0d 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 14ee634cc1..766e25b61c 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/pcengines/apu1/OptionsIds.h b/src/mainboard/pcengines/apu1/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/pcengines/apu1/OptionsIds.h +++ b/src/mainboard/pcengines/apu1/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/pcengines/apu1/acpi/buttons.asl b/src/mainboard/pcengines/apu1/acpi/buttons.asl index c5733fa15a..04b852ca9b 100644 --- a/src/mainboard/pcengines/apu1/acpi/buttons.asl +++ b/src/mainboard/pcengines/apu1/acpi/buttons.asl @@ -1,17 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ Scope (\_SB.PCI0.SBUS) diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl index af4e2e48b7..5788140112 100644 --- a/src/mainboard/pcengines/apu1/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu1/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/pcengines/apu1/acpi/gpio.asl b/src/mainboard/pcengines/apu1/acpi/gpio.asl index 570da93ee7..3c7dfe83ed 100644 --- a/src/mainboard/pcengines/apu1/acpi/gpio.asl +++ b/src/mainboard/pcengines/apu1/acpi/gpio.asl @@ -1,17 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ Scope (\_SB.PCI0.SBUS) diff --git a/src/mainboard/pcengines/apu1/acpi/leds.asl b/src/mainboard/pcengines/apu1/acpi/leds.asl index b4ccf188b2..dabae0779c 100644 --- a/src/mainboard/pcengines/apu1/acpi/leds.asl +++ b/src/mainboard/pcengines/apu1/acpi/leds.asl @@ -1,17 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ Scope (\_SB.PCI0.SBUS) diff --git a/src/mainboard/pcengines/apu1/acpi/mainboard.asl b/src/mainboard/pcengines/apu1/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/pcengines/apu1/acpi/mainboard.asl +++ b/src/mainboard/pcengines/apu1/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index befa15d272..d318bfc9d8 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/pcengines/apu1/acpi/sata.asl b/src/mainboard/pcengines/apu1/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/pcengines/apu1/acpi/sata.asl +++ b/src/mainboard/pcengines/apu1/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl index 08144ff427..0c973a4a0c 100644 --- a/src/mainboard/pcengines/apu1/acpi/sleep.asl +++ b/src/mainboard/pcengines/apu1/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/pcengines/apu1/acpi/superio.asl b/src/mainboard/pcengines/apu1/acpi/superio.asl index daf6e9177b..21fdfe9e95 100644 --- a/src/mainboard/pcengines/apu1/acpi/superio.asl +++ b/src/mainboard/pcengines/apu1/acpi/superio.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* No Super I/O device or functionality yet */ diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl index 5b22875dd1..27a737c730 100644 --- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/pcengines/apu1/acpi_tables.c b/src/mainboard/pcengines/apu1/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/pcengines/apu1/acpi_tables.c +++ b/src/mainboard/pcengines/apu1/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c index dc9f87d905..ede1db9f49 100644 --- a/src/mainboard/pcengines/apu1/bootblock.c +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index f2e4ab5fe2..f22dc29b71 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index d461220b0e..97e0e28143 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index bd1342c363..a5a80a1d7c 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h index 551f009817..1d60f441c1 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.h +++ b/src/mainboard/pcengines/apu1/gpio_ftns.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c index f962314546..c9f8f2776b 100644 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ b/src/mainboard/pcengines/apu1/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index d72a8fbcef..f31e256176 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index b6cb9d13b7..c1184f50a0 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index ed1ce3b5cb..0877b1bc88 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 42d85ace80..3eaf9193dc 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 69af3f9db3..d61402b4ac 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 8b6cd038e8..78ff99459c 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl index 573c847f76..256cc82afb 100644 --- a/src/mainboard/pcengines/apu2/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/pcengines/apu2/acpi/mainboard.asl +++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl index 0411c2a6b7..7167de7477 100644 --- a/src/mainboard/pcengines/apu2/acpi/routing.asl +++ b/src/mainboard/pcengines/apu2/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/pcengines/apu2/acpi/si.asl +++ b/src/mainboard/pcengines/apu2/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl index 19dd289560..5882acb05e 100644 --- a/src/mainboard/pcengines/apu2/acpi/sleep.asl +++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl index 83cd750b4a..b7757d3950 100644 --- a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index a40e86fe00..243a4a621d 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c index 8318f39287..3bfb1eb9b4 100644 --- a/src/mainboard/pcengines/apu2/bootblock.c +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index cbc7293e80..cc6c03d08a 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index 5242327354..ea6802fce5 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 3acf2a8654..5d295bd873 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c index 8e6223792a..1a630dabe3 100644 --- a/src/mainboard/pcengines/apu2/irq_tables.c +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 14ed39ffc9..f2663039f5 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 747e777dca..c4959ae865 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 34c42b43ff..6ba5712bd6 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From dd9c09d342fc5d9a09d663cf53adb5cc56c3f516 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:34 +0200 Subject: [PATCH 0825/1463] soc/ucb: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1b7a4fd5c6049230799d9e77903382812bc9768d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40138 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/ucb/riscv/cbmem.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 143e11b88c..b904b44797 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 5de47d0323ebcb8f6f32109879a380e2f65323d4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:30 +0200 Subject: [PATCH 0826/1463] soc/sifive: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I149d06d6241f81b535f64720d61bbd0c198caeda Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40137 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/soc/sifive/fu540/bootblock.c | 15 ++------------- src/soc/sifive/fu540/cbmem.c | 15 ++------------- src/soc/sifive/fu540/clint.c | 15 ++------------- src/soc/sifive/fu540/clock.c | 15 ++------------- src/soc/sifive/fu540/include/soc/addressmap.h | 15 ++------------- src/soc/sifive/fu540/include/soc/clock.h | 15 ++------------- src/soc/sifive/fu540/include/soc/memlayout.ld | 15 ++------------- src/soc/sifive/fu540/include/soc/otp.h | 15 ++------------- src/soc/sifive/fu540/include/soc/sdram.h | 15 ++------------- src/soc/sifive/fu540/include/soc/spi.h | 15 ++------------- src/soc/sifive/fu540/otp.c | 15 ++------------- src/soc/sifive/fu540/sdram.c | 15 ++------------- src/soc/sifive/fu540/spi.c | 15 ++------------- src/soc/sifive/fu540/spi_internal.h | 15 ++------------- src/soc/sifive/fu540/uart.c | 15 ++------------- 15 files changed, 30 insertions(+), 195 deletions(-) diff --git a/src/soc/sifive/fu540/bootblock.c b/src/soc/sifive/fu540/bootblock.c index a54f084cd6..6cdd4abfce 100644 --- a/src/soc/sifive/fu540/bootblock.c +++ b/src/soc/sifive/fu540/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 7fa39eff8f..4ade9ad780 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c index 9c430f28e8..a882fab015 100644 --- a/src/soc/sifive/fu540/clint.c +++ b/src/soc/sifive/fu540/clint.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index acbf1d816d..09bef76ccf 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h index 97370bdf97..7d03b55f70 100644 --- a/src/soc/sifive/fu540/include/soc/addressmap.h +++ b/src/soc/sifive/fu540/include/soc/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define FU540_MSEL 0x00001000 #define FU540_DTIM 0x01000000 diff --git a/src/soc/sifive/fu540/include/soc/clock.h b/src/soc/sifive/fu540/include/soc/clock.h index 093abeb6e5..8284dab06b 100644 --- a/src/soc/sifive/fu540/include/soc/clock.h +++ b/src/soc/sifive/fu540/include/soc/clock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_SIFIVE_HIFIVE_U_CLOCK_H__ #define __SOC_SIFIVE_HIFIVE_U_CLOCK_H__ diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index bef009b858..d024002eee 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/include/soc/otp.h b/src/soc/sifive/fu540/include/soc/otp.h index 81e0afb873..e1aae4cb5e 100644 --- a/src/soc/sifive/fu540/include/soc/otp.h +++ b/src/soc/sifive/fu540/include/soc/otp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_SIFIVE_HIFIVE_U_OTP_H__ #define __SOC_SIFIVE_HIFIVE_U_OTP_H__ diff --git a/src/soc/sifive/fu540/include/soc/sdram.h b/src/soc/sifive/fu540/include/soc/sdram.h index 2d01b39b94..e48ef77384 100644 --- a/src/soc/sifive/fu540/include/soc/sdram.h +++ b/src/soc/sifive/fu540/include/soc/sdram.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_SIFIVE_FU540_SDRAM_H__ #define __SOC_SIFIVE_FU540_SDRAM_H__ diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h index 201dcb629a..e6e57ed1f5 100644 --- a/src/soc/sifive/fu540/include/soc/spi.h +++ b/src/soc/sifive/fu540/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__ #define __SOC_SIFIVE_HIFIVE_U_SPI_H__ diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c index 5437a713f5..ef28fb575a 100644 --- a/src/soc/sifive/fu540/otp.c +++ b/src/soc/sifive/fu540/otp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/sdram.c b/src/soc/sifive/fu540/sdram.c index 5fadd1dfc5..fc31eb726d 100644 --- a/src/soc/sifive/fu540/sdram.c +++ b/src/soc/sifive/fu540/sdram.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index 0a736315ea..fa057be1ec 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/sifive/fu540/spi_internal.h b/src/soc/sifive/fu540/spi_internal.h index 494878d26c..6baee36b4f 100644 --- a/src/soc/sifive/fu540/spi_internal.h +++ b/src/soc/sifive/fu540/spi_internal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ #define __SOC_SIFIVE_HIFIVE_U_SPI_INTERNAL_H__ diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index b3f9107d5e..34a1039b6c 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 7c1d70e8e2ee8932bf6acea603f8e4e4bf9f68c8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:19 +0200 Subject: [PATCH 0827/1463] soc/qualcomm: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie78224f9bedd6ec3f0f10a58bb5dceeb35b73241 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40134 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/qualcomm/ipq40xx/blobs_init.c | 15 ++------------- src/soc/qualcomm/ipq40xx/cbmem.c | 15 ++------------- src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld | 15 ++------------- .../qualcomm/ipq40xx/include/soc/soc_services.h | 15 ++------------- src/soc/qualcomm/ipq40xx/include/soc/usb.h | 15 ++------------- src/soc/qualcomm/ipq40xx/include/soc/verstage.h | 15 ++------------- src/soc/qualcomm/ipq40xx/mbn_header.h | 15 ++------------- src/soc/qualcomm/ipq40xx/soc.c | 15 ++------------- src/soc/qualcomm/ipq40xx/usb.c | 15 ++------------- src/soc/qualcomm/ipq806x/blobs_init.c | 15 ++------------- src/soc/qualcomm/ipq806x/cbmem.c | 15 ++------------- src/soc/qualcomm/ipq806x/clock.c | 15 ++------------- src/soc/qualcomm/ipq806x/include/soc/cdp.h | 15 ++------------- src/soc/qualcomm/ipq806x/include/soc/ebi2.h | 15 ++------------- src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 15 ++------------- .../qualcomm/ipq806x/include/soc/soc_services.h | 15 ++------------- src/soc/qualcomm/ipq806x/include/soc/spi.h | 15 ++------------- src/soc/qualcomm/ipq806x/include/soc/usb.h | 15 ++------------- src/soc/qualcomm/ipq806x/mbn_header.h | 15 ++------------- src/soc/qualcomm/ipq806x/soc.c | 15 ++------------- src/soc/qualcomm/ipq806x/spi.c | 15 ++------------- src/soc/qualcomm/ipq806x/usb.c | 15 ++------------- src/soc/qualcomm/qcs405/gpio.c | 15 ++------------- src/soc/qualcomm/sc7180/gpio.c | 15 ++------------- src/soc/qualcomm/sdm845/gpio.c | 15 ++------------- 25 files changed, 50 insertions(+), 325 deletions(-) diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index d25bb87b0d..5edf615799 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 4fc4aedfd5..551753df1b 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index f11bcbf764..4e99b3a4f0 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h index 4beef62644..946f5f57bf 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_SOC_SERVICES_H__ #define __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_SOC_SERVICES_H__ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/usb.h b/src/soc/qualcomm/ipq40xx/include/soc/usb.h index 3b249563a4..6c0b399764 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/usb.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _IPQ40XX_USB_H_ #define _IPQ40XX_USB_H_ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/verstage.h b/src/soc/qualcomm/ipq40xx/include/soc/verstage.h index 5decfac672..4ba66347e3 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/verstage.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/verstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__ #define __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__ diff --git a/src/soc/qualcomm/ipq40xx/mbn_header.h b/src/soc/qualcomm/ipq40xx/mbn_header.h index a55559255a..a82e31f6e1 100644 --- a/src/soc/qualcomm/ipq40xx/mbn_header.h +++ b/src/soc/qualcomm/ipq40xx/mbn_header.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_QCA_IPQ40XX_MBN_HEADER_H__ #define __SOC_QCA_IPQ40XX_MBN_HEADER_H__ diff --git a/src/soc/qualcomm/ipq40xx/soc.c b/src/soc/qualcomm/ipq40xx/soc.c index 742a8ef38a..68f0b308f1 100644 --- a/src/soc/qualcomm/ipq40xx/soc.c +++ b/src/soc/qualcomm/ipq40xx/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq40xx/usb.c b/src/soc/qualcomm/ipq40xx/usb.c index 5b27541a6c..e61e5d39b9 100644 --- a/src/soc/qualcomm/ipq40xx/usb.c +++ b/src/soc/qualcomm/ipq40xx/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 0f3294745d..73f27839b6 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index b605ea6a0b..f89cfabdf4 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 6e0d8c7520..36084aa86d 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h index 62764cbdd4..89eebd3709 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _IPQ806X_CDP_H_ #define _IPQ806X_CDP_H_ diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h index fa97d58cea..b93e7c7aae 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Taken from U-Boot. diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 78aee5d32a..6bcfb80a53 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index bc78500e9d..f400d67fee 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__ #define __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__ diff --git a/src/soc/qualcomm/ipq806x/include/soc/spi.h b/src/soc/qualcomm/ipq806x/include/soc/spi.h index fd0598acaf..83ad797855 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/spi.h +++ b/src/soc/qualcomm/ipq806x/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Register definitions for the IPQ GSBI Controller diff --git a/src/soc/qualcomm/ipq806x/include/soc/usb.h b/src/soc/qualcomm/ipq806x/include/soc/usb.h index a4b43c0bc3..29c4252483 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/usb.h +++ b/src/soc/qualcomm/ipq806x/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _IPQ806X_USB_H_ #define _IPQ806X_USB_H_ diff --git a/src/soc/qualcomm/ipq806x/mbn_header.h b/src/soc/qualcomm/ipq806x/mbn_header.h index 2fc594ac4a..587211dc78 100644 --- a/src/soc/qualcomm/ipq806x/mbn_header.h +++ b/src/soc/qualcomm/ipq806x/mbn_header.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_QUALCOMM_IPQ806X_MBN_HEADER_H__ #define __SOC_QUALCOMM_IPQ806X_MBN_HEADER_H__ diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c index 77c968bd17..660918155b 100644 --- a/src/soc/qualcomm/ipq806x/soc.c +++ b/src/soc/qualcomm/ipq806x/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index a6c30d7ee4..0e2f10408b 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index e5c33a0667..25c95884ca 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index eab29f390f..cf2d940b16 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index b258ce66b4..38d81f157e 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/qualcomm/sdm845/gpio.c b/src/soc/qualcomm/sdm845/gpio.c index 8cd8d579d5..bfe9e9447e 100644 --- a/src/soc/qualcomm/sdm845/gpio.c +++ b/src/soc/qualcomm/sdm845/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From e67ab180fb856b25f3fbb238438606446a7e3ddb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:11 +0200 Subject: [PATCH 0828/1463] soc/mediatek: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7c3c75eaf2d7a64e7d833541bcf168b93921a142 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40132 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/mediatek/common/cbmem.c | 15 ++------------- src/soc/mediatek/common/ddp.c | 15 ++------------- src/soc/mediatek/common/dsi.c | 15 ++------------- src/soc/mediatek/common/gpio.c | 15 ++------------- src/soc/mediatek/common/i2c.c | 15 ++------------- src/soc/mediatek/common/include/soc/ddp_common.h | 15 ++------------- src/soc/mediatek/common/include/soc/dsi_common.h | 15 ++------------- src/soc/mediatek/common/include/soc/gpio_common.h | 15 ++------------- src/soc/mediatek/common/include/soc/i2c_common.h | 15 ++------------- .../mediatek/common/include/soc/mmu_operations.h | 15 ++------------- src/soc/mediatek/common/include/soc/mtcmos.h | 15 ++------------- src/soc/mediatek/common/include/soc/pll_common.h | 15 ++------------- .../common/include/soc/pmic_wrap_common.h | 15 ++------------- src/soc/mediatek/common/include/soc/rtc_common.h | 15 ++------------- src/soc/mediatek/common/include/soc/spi_common.h | 15 ++------------- src/soc/mediatek/common/include/soc/timer.h | 15 ++------------- src/soc/mediatek/common/include/soc/usb_common.h | 15 ++------------- src/soc/mediatek/common/include/soc/wdt.h | 15 ++------------- src/soc/mediatek/common/memory_test.c | 15 ++------------- src/soc/mediatek/common/mmu_operations.c | 15 ++------------- src/soc/mediatek/common/mtcmos.c | 15 ++------------- src/soc/mediatek/common/pll.c | 15 ++------------- src/soc/mediatek/common/pmic_wrap.c | 15 ++------------- src/soc/mediatek/common/reset.c | 15 ++------------- src/soc/mediatek/common/rtc.c | 15 ++------------- src/soc/mediatek/common/spi.c | 15 ++------------- src/soc/mediatek/common/timer.c | 15 ++------------- src/soc/mediatek/common/uart.c | 15 ++------------- src/soc/mediatek/common/usb.c | 15 ++------------- src/soc/mediatek/common/wdt.c | 15 ++------------- src/soc/mediatek/mt8173/bootblock.c | 15 ++------------- src/soc/mediatek/mt8173/da9212.c | 15 ++------------- src/soc/mediatek/mt8173/ddp.c | 15 ++------------- src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 15 ++------------- .../mediatek/mt8173/dramc_pi_calibration_api.c | 15 ++------------- src/soc/mediatek/mt8173/dsi.c | 15 ++------------- src/soc/mediatek/mt8173/emi.c | 15 ++------------- src/soc/mediatek/mt8173/flash_controller.c | 15 ++------------- src/soc/mediatek/mt8173/gpio.c | 15 ++------------- src/soc/mediatek/mt8173/gpio_init.c | 15 ++------------- src/soc/mediatek/mt8173/i2c.c | 15 ++------------- src/soc/mediatek/mt8173/include/soc/addressmap.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/da9212.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/ddp.h | 15 ++------------- .../mediatek/mt8173/include/soc/dramc_common.h | 15 ++------------- .../mediatek/mt8173/include/soc/dramc_pi_api.h | 15 ++------------- .../mediatek/mt8173/include/soc/dramc_register.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/dsi.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/emi.h | 15 ++------------- .../mt8173/include/soc/flash_controller.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/gpio.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/gpio_base.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/i2c.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/infracfg.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/mcucfg.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/memlayout.ld | 15 ++------------- src/soc/mediatek/mt8173/include/soc/mipi.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/mt6311.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/mt6391.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/pericfg.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/pll.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/pmic_wrap.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/rtc.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/spi.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/spm.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/symbols.h | 15 ++------------- src/soc/mediatek/mt8173/include/soc/usb.h | 15 ++------------- src/soc/mediatek/mt8173/memory.c | 15 ++------------- src/soc/mediatek/mt8173/mmu_operations.c | 15 ++------------- src/soc/mediatek/mt8173/mt6311.c | 15 ++------------- src/soc/mediatek/mt8173/mt6391.c | 15 ++------------- src/soc/mediatek/mt8173/pll.c | 15 ++------------- src/soc/mediatek/mt8173/pmic_wrap.c | 15 ++------------- src/soc/mediatek/mt8173/rtc.c | 15 ++------------- src/soc/mediatek/mt8173/soc.c | 15 ++------------- src/soc/mediatek/mt8173/spi.c | 15 ++------------- src/soc/mediatek/mt8173/timer.c | 15 ++------------- src/soc/mediatek/mt8173/usb.c | 15 ++------------- src/soc/mediatek/mt8183/auxadc.c | 15 ++------------- src/soc/mediatek/mt8183/bootblock.c | 15 ++------------- src/soc/mediatek/mt8183/ddp.c | 15 ++------------- src/soc/mediatek/mt8183/decompressor.c | 15 ++------------- src/soc/mediatek/mt8183/dramc_init_setting.c | 15 ++------------- src/soc/mediatek/mt8183/dramc_param.c | 15 ++------------- src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 15 ++------------- .../mediatek/mt8183/dramc_pi_calibration_api.c | 15 ++------------- src/soc/mediatek/mt8183/dsi.c | 15 ++------------- src/soc/mediatek/mt8183/emi.c | 15 ++------------- src/soc/mediatek/mt8183/gpio.c | 15 ++------------- src/soc/mediatek/mt8183/i2c.c | 15 ++------------- src/soc/mediatek/mt8183/include/soc/addressmap.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/auxadc.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/ddp.h | 15 ++------------- .../mt8183/include/soc/dramc_common_mt8183.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/dramc_param.h | 15 ++------------- .../mediatek/mt8183/include/soc/dramc_pi_api.h | 15 ++------------- .../mediatek/mt8183/include/soc/dramc_register.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/dsi.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/efuse.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/emi.h | 15 ++------------- .../mt8183/include/soc/flash_controller.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/gpio.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/gpio_base.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/i2c.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/infracfg.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/mcucfg.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/memlayout.ld | 15 ++------------- src/soc/mediatek/mt8183/include/soc/mt6358.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/mt8183.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/pll.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/pmic_wrap.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/rtc.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/smi.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/spi.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/spm.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/sspm.h | 15 ++------------- src/soc/mediatek/mt8183/include/soc/usb.h | 15 ++------------- src/soc/mediatek/mt8183/memory.c | 15 ++------------- src/soc/mediatek/mt8183/mmu_operations.c | 15 ++------------- src/soc/mediatek/mt8183/mt6358.c | 15 ++------------- src/soc/mediatek/mt8183/mt8183.c | 15 ++------------- src/soc/mediatek/mt8183/mtcmos.c | 15 ++------------- src/soc/mediatek/mt8183/pll.c | 15 ++------------- src/soc/mediatek/mt8183/pmic_wrap.c | 15 ++------------- src/soc/mediatek/mt8183/rtc.c | 15 ++------------- src/soc/mediatek/mt8183/soc.c | 15 ++------------- src/soc/mediatek/mt8183/spi.c | 15 ++------------- src/soc/mediatek/mt8183/spm.c | 15 ++------------- src/soc/mediatek/mt8183/sspm.c | 15 ++------------- 129 files changed, 258 insertions(+), 1677 deletions(-) diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 0edcd28fd6..5f758f6908 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 464b025fc8..71d859600a 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index ff968a23c4..f241ffe74d 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c index 79dcf2e557..1315f4197e 100644 --- a/src/soc/mediatek/common/gpio.c +++ b/src/soc/mediatek/common/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index d73a7f07b5..7e3ac2e7a0 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/include/soc/ddp_common.h b/src/soc/mediatek/common/include/soc/ddp_common.h index 9849576e91..35a2e2e1bd 100644 --- a/src/soc/mediatek/common/include/soc/ddp_common.h +++ b/src/soc/mediatek/common/include/soc/ddp_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DDP_COMMON_H_ #define _DDP_COMMON_H_ diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 63e0d7f95e..edbc9078a5 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_DSI_COMMON_H #define SOC_MEDIATEK_DSI_COMMON_H diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 097cbb50c6..af3f86a6d8 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_COMMON_GPIO_H #define SOC_MEDIATEK_COMMON_GPIO_H diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 0229eb56ea..c628d29a4d 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MTK_COMMON_I2C_H #define MTK_COMMON_I2C_H diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h index 7c8054416b..46bf41547c 100644 --- a/src/soc/mediatek/common/include/soc/mmu_operations.h +++ b/src/soc/mediatek/common/include/soc/mmu_operations.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__ #define __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__ diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index 0306c8d1f8..7ebbb2e296 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__ #define __SOC_MEDIATEK_COMMON_MTCMOS_H__ diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index e4814d785d..9e32eed514 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_PLL_COMMON_H #define SOC_MEDIATEK_PLL_COMMON_H diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 041742cd5c..29356266f0 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_PMIC_WRAP_COMMON_H #define SOC_MEDIATEK_PMIC_WRAP_COMMON_H diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 1ac8a81888..69f53aeccc 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_RTC_COMMON_H #define SOC_MEDIATEK_RTC_COMMON_H diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 4058dfd00d..b8b9ecac7c 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MTK_COMMON_SPI_H #define MTK_COMMON_SPI_H diff --git a/src/soc/mediatek/common/include/soc/timer.h b/src/soc/mediatek/common/include/soc/timer.h index 78f810a11a..8fa1182d78 100644 --- a/src/soc/mediatek/common/include/soc/timer.h +++ b/src/soc/mediatek/common/include/soc/timer.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_COMMON_TIMER_H #define SOC_MEDIATEK_COMMON_TIMER_H diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index bcb1a0d5a7..1c332ef38b 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_USB_COMMON_H #define SOC_MEDIATEK_USB_COMMON_H diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index c4d3ec2628..2d500d96e2 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_COMMON_WDT_H #define SOC_MEDIATEK_COMMON_WDT_H diff --git a/src/soc/mediatek/common/memory_test.c b/src/soc/mediatek/common/memory_test.c index c930e2feee..3caa113b63 100644 --- a/src/soc/mediatek/common/memory_test.c +++ b/src/soc/mediatek/common/memory_test.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 0f9146a911..5239d1a246 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index 1243960e92..b4bb19288b 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index ae9f7c7927..abd5c81309 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c index 755672f7e0..4a98f6cdf7 100644 --- a/src/soc/mediatek/common/pmic_wrap.c +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/reset.c b/src/soc/mediatek/common/reset.c index 951b91c114..ce15235aca 100644 --- a/src/soc/mediatek/common/reset.c +++ b/src/soc/mediatek/common/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index 89a7d36f53..a21d030626 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index a7f952972c..035fa14fe9 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c index 0ebd3f9643..ea673e656e 100644 --- a/src/soc/mediatek/common/timer.c +++ b/src/soc/mediatek/common/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 1f6702d779..92330a0481 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index d8d50022f3..fb8a5d923e 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 1eec587230..6fc9e4e051 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index 0002cf5805..79ed02900f 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index cc03240853..0fc4ced65a 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 502a4406d9..b247d45c1d 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 8a57f9d29d..f381c93a88 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 70c98fd79f..40500a46e0 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 6364f48846..001d95aa44 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index 1c2560863e..b53cb628b4 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index d82eee6641..9aa1a67432 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */ diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index 2afd0ba0fa..f962769905 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index 155c09ddf5..3b43ec41b1 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 1b9e50b9cd..6e9419e96f 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index 3b99a19cc4..4d353acfe7 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/da9212.h b/src/soc/mediatek/mt8173/include/soc/da9212.h index 24b5eef7ce..54be895043 100644 --- a/src/soc/mediatek/mt8173/include/soc/da9212.h +++ b/src/soc/mediatek/mt8173/include/soc/da9212.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_DA9212_H_ #define __SOC_DA9212_H_ diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/ddp.h index 648c0910d8..bdedb119b5 100644 --- a/src/soc/mediatek/mt8173/include/soc/ddp.h +++ b/src/soc/mediatek/mt8173/include/soc/ddp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MT8173_SOC_DDP_H_ #define _MT8173_SOC_DDP_H_ diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_common.h b/src/soc/mediatek/mt8173/include/soc/dramc_common.h index 0782a1a351..80ce0aa874 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_common.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DRAMC_COMMON_H_ #define _DRAMC_COMMON_H_ diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index aa5334b3ee..12cab1e535 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DRAMC_PI_API_H #define _DRAMC_PI_API_H diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_register.h b/src/soc/mediatek/mt8173/include/soc/dramc_register.h index 73ca7177a4..52b5fe0dc1 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_register.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_ diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index f19f0ececa..50a5c13852 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DSI_REG_H_ #define _DSI_REG_H_ diff --git a/src/soc/mediatek/mt8173/include/soc/emi.h b/src/soc/mediatek/mt8173/include/soc/emi.h index 2d584ac3bd..0346371f2b 100644 --- a/src/soc/mediatek/mt8173/include/soc/emi.h +++ b/src/soc/mediatek/mt8173/include/soc/emi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_EMI_H #define SOC_MEDIATEK_MT8173_EMI_H diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h index b92ad89330..091280be62 100644 --- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8173/include/soc/flash_controller.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ #define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index 482b6a5f86..51e8898c70 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_GPIO_H #define SOC_MEDIATEK_MT8173_GPIO_H diff --git a/src/soc/mediatek/mt8173/include/soc/gpio_base.h b/src/soc/mediatek/mt8173/include/soc/gpio_base.h index dccea8ff29..dc227b6284 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio_base.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio_base.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_GPIO_BASE_H #define SOC_MEDIATEK_MT8173_GPIO_BASE_H diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h index 5a9b067ef7..d09483cecf 100644 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_I2C_H #define SOC_MEDIATEK_MT8173_I2C_H diff --git a/src/soc/mediatek/mt8173/include/soc/infracfg.h b/src/soc/mediatek/mt8173/include/soc/infracfg.h index 3bf8f8b1c6..19c37bd4f9 100644 --- a/src/soc/mediatek/mt8173/include/soc/infracfg.h +++ b/src/soc/mediatek/mt8173/include/soc/infracfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_INFRACFG_H__ #define __SOC_MEDIATEK_MT8173_INFRACFG_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/mcucfg.h b/src/soc/mediatek/mt8173/include/soc/mcucfg.h index 301adb3909..f2a69ed4d0 100644 --- a/src/soc/mediatek/mt8173/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8173/include/soc/mcucfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_MCUCFG_H__ #define __SOC_MEDIATEK_MT8173_MCUCFG_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 2a617b7567..76d774aa59 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/mediatek/mt8173/include/soc/mipi.h b/src/soc/mediatek/mt8173/include/soc/mipi.h index 0a6389a7e6..07c1e063a3 100644 --- a/src/soc/mediatek/mt8173/include/soc/mipi.h +++ b/src/soc/mediatek/mt8173/include/soc/mipi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_MIPI_H__ #define __SOC_MEDIATEK_MT8173_MIPI_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/mt6311.h b/src/soc/mediatek/mt8173/include/soc/mt6311.h index eb058167fc..39fb57c600 100644 --- a/src/soc/mediatek/mt8173/include/soc/mt6311.h +++ b/src/soc/mediatek/mt8173/include/soc/mt6311.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_MT6311_H__ #define __SOC_MEDIATEK_MT8173_MT6311_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h index 4d3f12bc6a..95445a8033 100644 --- a/src/soc/mediatek/mt8173/include/soc/mt6391.h +++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_MT6391_H__ #define __SOC_MEDIATEK_MT8173_MT6391_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/pericfg.h b/src/soc/mediatek/mt8173/include/soc/pericfg.h index ea5b7102b2..470aec7a2f 100644 --- a/src/soc/mediatek/mt8173/include/soc/pericfg.h +++ b/src/soc/mediatek/mt8173/include/soc/pericfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_PERICFG_H__ #define __SOC_MEDIATEK_MT8173_PERICFG_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index a18431e8db..d6164d54db 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_PLL_H #define SOC_MEDIATEK_MT8173_PLL_H diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index aa618c203f..8c9fcbc1df 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_PMIC_WRAP_H #define SOC_MEDIATEK_MT8173_PMIC_WRAP_H diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index 8d35938e1b..61f9994a91 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_RTC_H #define SOC_MEDIATEK_MT8173_RTC_H diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index e813f9f3ae..81c2f2078d 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MTK_MT8173_SPI_H #define MTK_MT8173_SPI_H diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index ba603d26ce..3d4ad712d2 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_SPM_H__ #define __SOC_MEDIATEK_MT8173_SPM_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h index 7fe9ff69b1..05c510bcef 100644 --- a/src/soc/mediatek/mt8173/include/soc/symbols.h +++ b/src/soc/mediatek/mt8173/include/soc/symbols.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ #define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ diff --git a/src/soc/mediatek/mt8173/include/soc/usb.h b/src/soc/mediatek/mt8173/include/soc/usb.h index 66a5195c57..b46f994ac6 100644 --- a/src/soc/mediatek/mt8173/include/soc/usb.h +++ b/src/soc/mediatek/mt8173/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8173_USB_H #define SOC_MEDIATEK_MT8173_USB_H diff --git a/src/soc/mediatek/mt8173/memory.c b/src/soc/mediatek/mt8173/memory.c index c87e4975f2..83a6afae38 100644 --- a/src/soc/mediatek/mt8173/memory.c +++ b/src/soc/mediatek/mt8173/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index c76a8568de..bb2b73da88 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/mt6311.c b/src/soc/mediatek/mt8173/mt6311.c index 76b53f451e..323ff74263 100644 --- a/src/soc/mediatek/mt8173/mt6311.c +++ b/src/soc/mediatek/mt8173/mt6311.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 3e0f55615e..ea4679f025 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 0b8a52a4f7..0749d142a9 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index 33fbbe2093..a2a1ea7c54 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 759eef47c3..ebac96ce68 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c index 78e4d119e8..f47214d4a8 100644 --- a/src/soc/mediatek/mt8173/soc.c +++ b/src/soc/mediatek/mt8173/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index c41a1d58ad..a479f8e22e 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c index 73709319f4..dcd0cebd2b 100644 --- a/src/soc/mediatek/mt8173/timer.c +++ b/src/soc/mediatek/mt8173/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8173/usb.c b/src/soc/mediatek/mt8173/usb.c index 89674a93c2..b47a3a44be 100644 --- a/src/soc/mediatek/mt8173/usb.c +++ b/src/soc/mediatek/mt8173/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c index 549965bec2..1d6e1b0110 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c index 5aeb5410f6..f317844c85 100644 --- a/src/soc/mediatek/mt8183/bootblock.c +++ b/src/soc/mediatek/mt8183/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 0d31dd3b1f..05f4150c16 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/decompressor.c b/src/soc/mediatek/mt8183/decompressor.c index 87003d0a0d..f21300ad18 100644 --- a/src/soc/mediatek/mt8183/decompressor.c +++ b/src/soc/mediatek/mt8183/decompressor.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index a2615770ed..9eebfe8ded 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c index 999126fe74..54d2209917 100644 --- a/src/soc/mediatek/mt8183/dramc_param.c +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "soc/dramc_param.h" diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 850f2b2ba1..5bffc42671 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 65f605ec14..024c039ed5 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index ac8200cbd8..4957f78da3 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 85a75befdd..c03f945052 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 717a3abfe0..96c4e36b94 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index 23f19de94b..918981ee63 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index dc97a14403..00e32ff16a 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__ #define __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__ diff --git a/src/soc/mediatek/mt8183/include/soc/auxadc.h b/src/soc/mediatek/mt8183/include/soc/auxadc.h index 3e9d3d99d0..cc81ed02f4 100644 --- a/src/soc/mediatek/mt8183/include/soc/auxadc.h +++ b/src/soc/mediatek/mt8183/include/soc/auxadc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MTK_ADC_H #define _MTK_ADC_H diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h index 16e5238cb8..eda5fba6a6 100644 --- a/src/soc/mediatek/mt8183/include/soc/ddp.h +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MT8183_SOC_DDP_H_ #define _MT8183_SOC_DDP_H_ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index f933268d1f..11dd8f3724 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DRAMC_COMMON_MT8183_H_ #define _DRAMC_COMMON_MT8183_H_ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index bf76f7c828..7b3ba7ecbe 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H #define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 62f1fc6476..19d92b599d 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DRAMC_PI_API_MT8183_H #define _DRAMC_PI_API_MT8183_H diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index f6fd688a12..d042bfd7c3 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_ diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index eaf1cf4a07..f4ac2bdecb 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_DSI_H #define SOC_MEDIATEK_MT8183_DSI_H diff --git a/src/soc/mediatek/mt8183/include/soc/efuse.h b/src/soc/mediatek/mt8183/include/soc/efuse.h index 39428346d3..01a95d39ab 100644 --- a/src/soc/mediatek/mt8183/include/soc/efuse.h +++ b/src/soc/mediatek/mt8183/include/soc/efuse.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MTK_EFUSE_H #define _MTK_EFUSE_H diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 7d0541f97c..3862d54be0 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_EMI_H #define SOC_MEDIATEK_MT8183_EMI_H diff --git a/src/soc/mediatek/mt8183/include/soc/flash_controller.h b/src/soc/mediatek/mt8183/include/soc/flash_controller.h index d9ebc745db..df61dea4fd 100644 --- a/src/soc/mediatek/mt8183/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8183/include/soc/flash_controller.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8183_FLASH_CONTROLLER_H__ #define __SOC_MEDIATEK_MT8183_FLASH_CONTROLLER_H__ diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h index 2492f0d37f..bcf3fb9f0f 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_GPIO_H #define SOC_MEDIATEK_MT8183_GPIO_H diff --git a/src/soc/mediatek/mt8183/include/soc/gpio_base.h b/src/soc/mediatek/mt8183/include/soc/gpio_base.h index 782f2a141d..9a827252cf 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio_base.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio_base.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_GPIO_BASE_H #define SOC_MEDIATEK_MT8183_GPIO_BASE_H diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h index 9940247705..b737888967 100644 --- a/src/soc/mediatek/mt8183/include/soc/i2c.h +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_I2C_H #define SOC_MEDIATEK_MT8183_I2C_H diff --git a/src/soc/mediatek/mt8183/include/soc/infracfg.h b/src/soc/mediatek/mt8183/include/soc/infracfg.h index 7a43066c4f..12924ec79c 100644 --- a/src/soc/mediatek/mt8183/include/soc/infracfg.h +++ b/src/soc/mediatek/mt8183/include/soc/infracfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_INFRACFG_H #define SOC_MEDIATEK_MT8183_INFRACFG_H diff --git a/src/soc/mediatek/mt8183/include/soc/mcucfg.h b/src/soc/mediatek/mt8183/include/soc/mcucfg.h index 9b825b255d..c63bd85396 100644 --- a/src/soc/mediatek/mt8183/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8183/include/soc/mcucfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_MCUCFG_H #define SOC_MEDIATEK_MT8183_MCUCFG_H diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index d2f9a060f8..072d7e5e5d 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 047311aec8..65005c1d45 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT6358_H__ #define __SOC_MEDIATEK_MT6358_H__ diff --git a/src/soc/mediatek/mt8183/include/soc/mt8183.h b/src/soc/mediatek/mt8183/include/soc/mt8183.h index b1b0170274..d67d00a10a 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/mt8183.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8183_H__ #define __SOC_MEDIATEK_MT8183_H__ diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 23eaf2bceb..bbe13a8982 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_PLL_H #define SOC_MEDIATEK_MT8183_PLL_H diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h index 32f40a435f..5718f92e4c 100644 --- a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ #define __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 4b18bff857..50879c740f 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_RTC_H #define SOC_MEDIATEK_MT8183_RTC_H diff --git a/src/soc/mediatek/mt8183/include/soc/smi.h b/src/soc/mediatek/mt8183/include/soc/smi.h index 5264518207..96901d467e 100644 --- a/src/soc/mediatek/mt8183/include/soc/smi.h +++ b/src/soc/mediatek/mt8183/include/soc/smi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_SMI_H #define SOC_MEDIATEK_MT8183_SMI_H diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index e7b024319d..cef0bdf0e0 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MTK_MT8183_SPI_H #define MTK_MT8183_SPI_H diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 542eb95800..a9663d8296 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_SPM_H #define SOC_MEDIATEK_MT8183_SPM_H diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h index 89e279fdf7..0e5c6ad1df 100644 --- a/src/soc/mediatek/mt8183/include/soc/sspm.h +++ b/src/soc/mediatek/mt8183/include/soc/sspm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_SSPM_H #define SOC_MEDIATEK_MT8183_SSPM_H diff --git a/src/soc/mediatek/mt8183/include/soc/usb.h b/src/soc/mediatek/mt8183/include/soc/usb.h index c0af677d0a..eaf19ace8b 100644 --- a/src/soc/mediatek/mt8183/include/soc/usb.h +++ b/src/soc/mediatek/mt8183/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_MEDIATEK_MT8183_USB_H #define SOC_MEDIATEK_MT8183_USB_H diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 5603995e71..53763fd557 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/mmu_operations.c b/src/soc/mediatek/mt8183/mmu_operations.c index 449b537d2d..e4c4185c1e 100644 --- a/src/soc/mediatek/mt8183/mmu_operations.c +++ b/src/soc/mediatek/mt8183/mmu_operations.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index c4272260c6..959894bcf4 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c index 4159844bdd..60e63ac693 100644 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/mtcmos.c b/src/soc/mediatek/mt8183/mtcmos.c index 636399bb5c..abd95f6d77 100644 --- a/src/soc/mediatek/mt8183/mtcmos.c +++ b/src/soc/mediatek/mt8183/mtcmos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 0eb7dc8d45..df95d90b53 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c index 8bd580aac8..a8a40e353a 100644 --- a/src/soc/mediatek/mt8183/pmic_wrap.c +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 063f8ae924..b408623a74 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index 33e1eb9d51..804a47a448 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 76a34e894a..04d620ce35 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index ca7a5adfaf..70cb54b8bd 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index beec33b9d8..3b72aff6dd 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From a5c27096a41a715efda103b03bf3ce2a61ff1670 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 2 Apr 2020 15:31:21 -0700 Subject: [PATCH 0829/1463] soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD. BUG=b:152000235 BRANCH=none TEST= build volteer and boot to kernel Signed-off-by: Srinidhi N Kaushik Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40061 Reviewed-by: Wonkyu Kim Reviewed-by: Furquan Shaikh Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/meminit.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 864f0795e4..bd9a4ff45d 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -40,45 +40,53 @@ static uint8_t get_dimm_cfg(uintptr_t dimm0, uintptr_t dimm1) static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, uintptr_t spd_dimm1) { - mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1); + uint8_t dimm_cfg = get_dimm_cfg(spd_dimm0, spd_dimm1); switch (channel) { case 0: + mem_cfg->DisableDimmCh0 = dimm_cfg; mem_cfg->MemorySpdPtr00 = spd_dimm0; mem_cfg->MemorySpdPtr01 = spd_dimm1; break; case 1: + mem_cfg->DisableDimmCh1 = dimm_cfg; mem_cfg->MemorySpdPtr02 = spd_dimm0; mem_cfg->MemorySpdPtr03 = spd_dimm1; break; case 2: + mem_cfg->DisableDimmCh2 = dimm_cfg; mem_cfg->MemorySpdPtr04 = spd_dimm0; mem_cfg->MemorySpdPtr05 = spd_dimm1; break; case 3: + mem_cfg->DisableDimmCh3 = dimm_cfg; mem_cfg->MemorySpdPtr06 = spd_dimm0; mem_cfg->MemorySpdPtr07 = spd_dimm1; break; case 4: + mem_cfg->DisableDimmCh4 = dimm_cfg; mem_cfg->MemorySpdPtr08 = spd_dimm0; mem_cfg->MemorySpdPtr09 = spd_dimm1; break; case 5: + mem_cfg->DisableDimmCh5 = dimm_cfg; mem_cfg->MemorySpdPtr10 = spd_dimm0; mem_cfg->MemorySpdPtr11 = spd_dimm1; break; case 6: + mem_cfg->DisableDimmCh6 = dimm_cfg; mem_cfg->MemorySpdPtr12 = spd_dimm0; mem_cfg->MemorySpdPtr13 = spd_dimm1; break; case 7: + mem_cfg->DisableDimmCh7 = dimm_cfg; mem_cfg->MemorySpdPtr14 = spd_dimm0; mem_cfg->MemorySpdPtr15 = spd_dimm1; break; From 52a9599d079896a3a9b379786520208b8ec22269 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 3 Apr 2020 22:47:36 +0200 Subject: [PATCH 0830/1463] soc/intel/apollolake: Don't select repo option for Gemini Lake Change-Id: I70fbc0c2959acba71cbb3b2c7b6c0d6d743c91e5 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40124 Reviewed-by: Mimoja Reviewed-by: Felix Singer Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ed35eaac7e..e5ab28c2fe 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -44,7 +44,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER - select HAVE_INTEL_FSP_REPO + select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GLK select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES From 04da5d72d9f12b066830b82632c4a72c7c50ea5d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 27 Mar 2020 20:34:54 +0100 Subject: [PATCH 0831/1463] fsp2_0: Clean up around `config FSP_USE_REPO` We can make our lifes much easier by removing its dependency on `ADD_FSP_BINARIES`. Instead, we imply the latter if the repository is to be used. We can also hide a lot of unnecessary prompts in this case. Also, remove default overrides and selects for the two that are now unnecessary. Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882 Reviewed-by: Angel Pons Reviewed-by: Felix Singer Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- Documentation/mainboard/asrock/h110m-dvs.md | 2 -- configs/config.intel_coffeelake_rvp11.fsp_car | 2 -- src/drivers/intel/fsp2_0/Kconfig | 34 +++++++++---------- src/mainboard/libretrend/lt1000/Kconfig | 8 ----- src/mainboard/protectli/vault_kbl/Kconfig | 8 ----- src/mainboard/razer/blade_stealth_kbl/Kconfig | 2 -- src/mainboard/system76/lemp9/Kconfig | 1 - src/mainboard/up/squared/Kconfig | 2 -- util/abuild/abuild | 2 +- 9 files changed, 18 insertions(+), 43 deletions(-) diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 66d491d44c..4d26cfd0f8 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -31,8 +31,6 @@ make distclean touch .config ./util/scripts/config --enable VENDOR_ASROCK ./util/scripts/config --enable BOARD_ASROCK_H110M_DVS -./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES -./util/scripts/config --enable CONFIG_FSP_USE_REPO ./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" make olddefconfig ``` diff --git a/configs/config.intel_coffeelake_rvp11.fsp_car b/configs/config.intel_coffeelake_rvp11.fsp_car index 33192c4e1f..689821717e 100644 --- a/configs/config.intel_coffeelake_rvp11.fsp_car +++ b/configs/config.intel_coffeelake_rvp11.fsp_car @@ -2,8 +2,6 @@ CONFIG_USE_BLOBS=y CONFIG_VENDOR_INTEL=y CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin" CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y -CONFIG_ADD_FSP_BINARIES=y CONFIG_USE_CANNONLAKE_FSP_CAR=y CONFIG_RUN_FSP_GOP=y -CONFIG_FSP_USE_REPO=y CONFIG_PAYLOAD_NONE=y diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1e1cc194d8..b3b99bdbe0 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -31,11 +31,19 @@ config PLATFORM_USES_FSP2_1 if PLATFORM_USES_FSP2_0 -config ADD_FSP_BINARIES - bool "Add Intel FSP 2.0 binaries to CBFS" +config FSP_USE_REPO + bool "Use binaries of the Intel FSP repository on GitHub" + depends on HAVE_INTEL_FSP_REPO + default y help - Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not - use the FSP-T binary and it is not added. + When selecting this option, the SoC must set FSP_HEADER_PATH + and FSP_FD_PATH correctly so FSP splitting works. + +config ADD_FSP_BINARIES + bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO + default y if FSP_USE_REPO + help + Add the FSP-M and FSP-S binaries to CBFS. config FSP_T_CBFS string "Name of FSP-T in CBFS" @@ -50,31 +58,23 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" -config FSP_USE_REPO - bool "Use the IntelFSP based binaries" - depends on ADD_FSP_BINARIES - depends on HAVE_INTEL_FSP_REPO - default y - help - When selecting this option, the SoC must set FSP_HEADER_PATH - and FSP_FD_PATH correctly so FSP splitting works. - config FSP_T_FILE - string "Intel FSP-T (temp RAM init) binary path and filename" + string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_USE_REPO + depends on ADD_FSP_BINARIES depends on FSP_CAR default "$(obj)/Fsp_T.fd" if FSP_USE_REPO help - The path and filename of the Intel FSP-M binary for this platform. + The path and filename of the Intel FSP-T binary for this platform. config FSP_M_FILE - string "Intel FSP-M (memory init) binary path and filename" + string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO depends on ADD_FSP_BINARIES default "$(obj)/Fsp_M.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-M binary for this platform. config FSP_S_FILE - string "Intel FSP-S (silicon init) binary path and filename" + string "Intel FSP-S (silicon init) binary path and filename" if !FSP_USE_REPO depends on ADD_FSP_BINARIES default "$(obj)/Fsp_S.fd" if FSP_USE_REPO help diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig index b4a4e49ef7..9c4223ae4b 100644 --- a/src/mainboard/libretrend/lt1000/Kconfig +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -44,12 +44,4 @@ config CBFS_SIZE hex default 0x600000 -config ADD_FSP_BINARIES - bool - default y - -config FSP_USE_REPO - bool - default y - endif diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index bfafc0bce2..8c09a60b6e 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -48,12 +48,4 @@ config CBFS_SIZE hex default 0x600000 -config ADD_FSP_BINARIES - bool - default y - -config FSP_USE_REPO - bool - default y - endif diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 903d7baa4c..532bd76c45 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -14,8 +14,6 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_HID select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select ADD_FSP_BINARIES - select FSP_USE_REPO # For now no way to choose the correct the available RAM config BOARD_RAZER_BLADE_STEALTH_KBL_16GB diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index a612503b6a..d8146332fe 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -2,7 +2,6 @@ if BOARD_SYSTEM76_LEMP9 config BOARD_SPECIFIC_OPTIONS def_bool y - select ADD_FSP_BINARIES select BOARD_ROMSIZE_KB_16384 select EC_ACPI select HAVE_ACPI_RESUME diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index 5db76fd544..542e8c3c20 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -3,8 +3,6 @@ if BOARD_UP_SQUARED config BOARD_SPECIFIC_OPTIONS def_bool y select USE_BLOBS - select ADD_FSP_BINARIES - select FSP_USE_REPO select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select INTEL_GMA_HAVE_VBT diff --git a/util/abuild/abuild b/util/abuild/abuild index 9688c8ce7d..f55dadc71b 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -720,7 +720,7 @@ while true ; do shift;; -B|--blobs) shift customizing="${customizing}, blobs" - configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\nCONFIG_FSP_USE_REPO=y\n" + configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\n" ;; -A|--any-toolchain) shift customizing="${customizing}, any-toolchain" From a0e72c48679ac83fd476af79d26faea07788d402 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 3 Apr 2020 23:38:17 +0200 Subject: [PATCH 0832/1463] fsp2_0: Gather Kconfig declarations Move more Kconfig declarations to drivers/intel/fsp2_0/ and document them properly. This way, we don't have to repeat dependencies and have the prompts in a common place. We can also easily hide the prompt for the header path in case the FSP repository is used. SP platforms were skipped as their Kconfig is too weird but they shouldn't hold other platforms back. Change-Id: Iba5af49bcd15427e9eb9b111e6c4cc9bcb7adcae Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40125 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Singer --- src/drivers/intel/fsp2_0/Kconfig | 27 +++++++++++++++++++++++++-- src/soc/intel/Kconfig | 6 ------ src/soc/intel/apollolake/Kconfig | 3 --- src/soc/intel/cannonlake/Kconfig | 3 --- src/soc/intel/denverton_ns/Kconfig | 3 --- src/soc/intel/icelake/Kconfig | 3 --- src/soc/intel/jasperlake/Kconfig | 3 --- src/soc/intel/skylake/Kconfig | 3 --- src/soc/intel/tigerlake/Kconfig | 3 --- 9 files changed, 25 insertions(+), 29 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index b3b99bdbe0..27c0803ad6 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -31,13 +31,36 @@ config PLATFORM_USES_FSP2_1 if PLATFORM_USES_FSP2_0 +config HAVE_INTEL_FSP_REPO + bool + help + Select this, if the FSP binaries for the platform are public + and available in 3rdparty/fsp/. When selecting this option, the + platform must also set FSP_HEADER_PATH and FSP_FD_PATH correctly. + config FSP_USE_REPO bool "Use binaries of the Intel FSP repository on GitHub" depends on HAVE_INTEL_FSP_REPO default y help - When selecting this option, the SoC must set FSP_HEADER_PATH - and FSP_FD_PATH correctly so FSP splitting works. + Select this option to use the default FSP headers and binaries + found in the IntelFsp GitHub repository at + + https://github.com/IntelFsp/FSP/ + + If unsure, say Y. + +config FSP_HEADER_PATH + string "Location of FSP headers" if !FSP_USE_REPO + help + Include directory with the FSP ABI header files. + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + help + Path to the FSP FD file that contains the individual FSP-T, FSP-M + and FSP-S binaries. config ADD_FSP_BINARIES bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 75f2f7090e..d5190683ae 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -38,9 +38,3 @@ config INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG than the one in non-topswap bootblock. This string will be passed onto ifittool (-A -n option). ifittool will not parse the region for MCU entries, and only locate the region and insert its address into FIT. - -config HAVE_INTEL_FSP_REPO - bool - help - Select this, if the FSP binaries for the platform are public available - in 3rdparty/fsp. diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index e5ab28c2fe..91e5bb64b3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -182,13 +182,10 @@ config VERSTAGE_ADDR The base address (in CAR) where verstage should be linked config FSP_HEADER_PATH - string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GLK default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" config FSP_FD_PATH - string - depends on FSP_USE_REPO default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd" config FSP_M_ADDR diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index baf8756385..889aa00b21 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -310,14 +310,11 @@ config USE_CANNONLAKE_FSP_CAR endchoice config FSP_HEADER_PATH - string "Location of FSP headers" default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE config FSP_FD_PATH - string - depends on FSP_USE_REPO default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index c628dbd7b5..5f2c5aa881 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -81,12 +81,9 @@ config FSP_S_ADDR The memory location of the Intel FSP-S binary for this platform. config FSP_HEADER_PATH - string default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" config FSP_FD_PATH - string - depends on FSP_USE_REPO default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" # CAR memory layout on DENVERTON_NS hardware: diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 559ba6c801..4193128a64 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -179,12 +179,9 @@ config CBFS_SIZE default 0x200000 config FSP_HEADER_PATH - string "Location of FSP headers" default "3rdparty/fsp/IceLakeFspBinPkg/Include" config FSP_FD_PATH - string - depends on FSP_USE_REPO default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" config SOC_INTEL_ICELAKE_DEBUG_CONSENT diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 844a954996..8c2dd779b4 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -184,12 +184,9 @@ config CBFS_SIZE default 0x200000 config FSP_HEADER_PATH - string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" config FSP_FD_PATH - string - depends on FSP_USE_REPO default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2beda43c7c..4df64beb5e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -222,14 +222,11 @@ config NHLT_DA7219 Include DSP firmware settings for DA7219 headset codec. config FSP_HEADER_PATH - string "Location of FSP headers" # Use KabylakeFsp for both Skylake and Kabylake as it supports both. # SkylakeFsp is FSP 1.1 and therefore incompatible. default "3rdparty/fsp/KabylakeFspBinPkg/Include/" config FSP_FD_PATH - string - depends on FSP_USE_REPO default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" config MAX_ROOT_PORTS diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 77d22ca946..a690acf9dc 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -184,12 +184,9 @@ config CBFS_SIZE default 0x200000 config FSP_HEADER_PATH - string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" config FSP_FD_PATH - string - depends on FSP_USE_REPO default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT From e8d483923baed00fbc16de38e6532f4cc27cdc9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 2 Apr 2020 17:55:39 +0200 Subject: [PATCH 0833/1463] arch/x86/acpi: add definitions for IVHD type 11h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add definitions of I/O Virtualization Hardware Definition Block type 11h structures for ACPI I/O Virtualization Reporting Structure generation. Signed-off-by: Michał Żygowski Change-Id: I698ac6f6a2e0bc5736fbb14ef583bbe031baee28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40041 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/acpi.h | 27 ++++++++++++++++++++++ src/arch/x86/include/arch/acpi_ivrs.h | 33 +++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index d5040adb24..644f52f2ce 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -290,6 +290,33 @@ typedef struct acpi_ivrs { struct acpi_ivrs_ivhd ivhd; } __packed acpi_ivrs_t; +/* IVHD Type 11h IOMMU Attributes */ +typedef struct ivhd11_iommu_attr { + uint32_t reserved1 : 13; + uint32_t perf_counters : 4; + uint32_t perf_counter_banks : 6; + uint32_t msi_num_ppr : 5; + uint32_t reserved2 : 4; +} __packed ivhd11_iommu_attr_t; + +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 11h */ +typedef struct acpi_ivrs_ivhd_11 { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_low; + uint32_t iommu_base_high; + uint16_t pci_segment_group; + uint16_t iommu_info; + struct ivhd11_iommu_attr iommu_attributes; + uint32_t efr_reg_image_low; + uint32_t efr_reg_image_high; + uint32_t reserved[2]; + uint8_t entry[0]; +} __packed acpi_ivrs_ivhd11_t; + enum dev_scope_type { SCOPE_PCI_ENDPOINT = 1, SCOPE_PCI_SUB = 2, diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h index d8d62d47b5..83abfb63dc 100644 --- a/src/arch/x86/include/arch/acpi_ivrs.h +++ b/src/arch/x86/include/arch/acpi_ivrs.h @@ -107,4 +107,37 @@ #define IVHD_UID_INT 0x01 #define IVHD_UID_STRING 0x02 +/* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ +typedef struct ivrs_ivhd_generic { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; +} __packed ivrs_ivhd_generic_t; + +/* IVHD (I/O Virtualization Hardware Definition Block) 8-byte entries */ +typedef struct ivrs_ivhd_alias { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint8_t reserved1; + uint16_t source_dev_id; + uint8_t reserved2; +} __packed ivrs_ivhd_alias_t; + +typedef struct ivrs_ivhd_extended { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint32_t extended_dte_setting; +} __packed ivrs_ivhd_extended_t; + +typedef struct ivrs_ivhd_special { + uint8_t type; + uint16_t reserved; + uint8_t dte_setting; + uint8_t handle; + uint16_t source_dev_id; + uint8_t variety; +} __packed ivrs_ivhd_special_t; + #endif From b6a523927d58c13b7a0bf6c8d20ef29a43e1aa95 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 2 Apr 2020 16:03:41 +0530 Subject: [PATCH 0834/1463] soc/intel/jasperlake: Remove DDI A lane programming For newer Intel graphics (>=11), the DDI port max lanes default to 4. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A (for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp compilation and boot. Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/40038 Reviewed-by: Nico Huber Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/graphics.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 4f5d573c8b..0ee340ce3b 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -31,24 +30,6 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { - uint32_t ddi_buf_ctl; - - /* Skip IGD GT programming */ - if (CONFIG(SKIP_GRAPHICS_ENABLING)) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig From 1d5192894f439a85989ff93814d1b8170768f8dc Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 2 Apr 2020 16:06:31 +0530 Subject: [PATCH 0835/1463] soc/intel/common: Remove unused Kconfig SKIP_GRAPHICS_ENABLING It is use to skip GT specific programming in ICL, TGL and JSL. In following patches use of SKIP_GRAPHICS_ENABLING is removed. b6a523927d (soc/intel/jasperlake: Remove DDI A lane programming) e5565c45cb (soc/intel/{icelake, tigerlake}: Remove DDI A lane programming) TEST=checked iclrvp, jslrvp and tglrvp compilation. Change-Id: Ie337fd727d72118c43aa869da1446ea4fceadc5b Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/40039 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Aamir Bohra --- src/soc/intel/common/block/graphics/Kconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index 36cac22ec9..4ab92001c3 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -2,11 +2,3 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS bool help Intel Processor common Graphics support - -config SKIP_GRAPHICS_ENABLING - bool - depends on SOC_INTEL_COMMON_BLOCK_GRAPHICS - default n - help - Skip GT specific programming in coreboot to support - early parts without GT enable. From 93bcf24795a31b6b54095de3d0cc33417f68018d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:17 +0200 Subject: [PATCH 0836/1463] mainboard/jetway: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I101ee19f58180a2181fcdb123b3fedef9a559e39 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40083 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../jetway/nf81-t56n-lf/BiosCallOuts.c | 15 ++------------- .../jetway/nf81-t56n-lf/OemCustomize.c | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl | 15 ++------------- .../jetway/nf81-t56n-lf/acpi/mainboard.asl | 15 ++------------- .../jetway/nf81-t56n-lf/acpi/routing.asl | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl | 15 ++------------- .../jetway/nf81-t56n-lf/acpi/sleep.asl | 15 ++------------- .../jetway/nf81-t56n-lf/acpi/superio.asl | 17 ++--------------- .../jetway/nf81-t56n-lf/acpi/usb_oc.asl | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/bootblock.c | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 15 ++------------- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 15 ++------------- .../jetway/nf81-t56n-lf/platform_cfg.h | 15 ++------------- 18 files changed, 36 insertions(+), 236 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index c27a33d183..bbd36cc25e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index 4fbe3b8a11..9bd0ed46e4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h index b4fe940569..076c1c292d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h +++ b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index af4e2e48b7..5788140112 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl index 3d4abb5d7b..86d8e53910 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl index 70c5da5ef0..d7dc69a34d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl index 9729500d48..04d1b75395 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl index 08144ff427..0c973a4a0c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl index db519899e8..1bc1628982 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl @@ -1,17 +1,4 @@ -/* - * Super I/O devices - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl index 5b22875dd1..27a737c730 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* simple name description */ /* diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 9e3032474e..02afbdbc5a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c index 6a8e578fa7..ade70006fd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c +++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 583dfb2e58..83f20f7c69 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index d190f8c8e8..441f38f619 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index 8239e77015..bce3a2269f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 55dee3314a..dd8064e5cf 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 5ef3850a20..9bfcbda533 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index 666d528ede..81c2ed9c0f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PLATFORM_CFG_H_ From 60ec3656eb1d857caddba81852e3b99551fb1243 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:13 +0200 Subject: [PATCH 0837/1463] mainboard/intel: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../intel/baskingridge/acpi/mainboard.asl | 16 ++-------------- .../intel/baskingridge/acpi/platform.asl | 15 ++------------- .../intel/baskingridge/acpi/superio.asl | 15 ++------------- .../intel/baskingridge/acpi/thermal.asl | 15 ++------------- src/mainboard/intel/baskingridge/acpi_tables.c | 15 ++------------- src/mainboard/intel/baskingridge/chromeos.c | 15 ++------------- src/mainboard/intel/baskingridge/dsdt.asl | 15 ++------------- src/mainboard/intel/baskingridge/gpio.h | 15 ++------------- src/mainboard/intel/baskingridge/hda_verb.c | 15 ++------------- src/mainboard/intel/baskingridge/mainboard.c | 15 ++------------- .../intel/baskingridge/mainboard_smi.c | 15 ++------------- src/mainboard/intel/baskingridge/romstage.c | 15 ++------------- src/mainboard/intel/baskingridge/thermal.h | 15 ++------------- src/mainboard/intel/cannonlake_rvp/bootblock.c | 15 ++------------- src/mainboard/intel/cannonlake_rvp/chromeos.c | 15 ++------------- src/mainboard/intel/cannonlake_rvp/dsdt.asl | 15 ++------------- src/mainboard/intel/cannonlake_rvp/mainboard.c | 15 ++------------- .../intel/cannonlake_rvp/romstage_fsp_params.c | 15 ++------------- src/mainboard/intel/cannonlake_rvp/smihandler.c | 15 ++------------- src/mainboard/intel/cannonlake_rvp/spd/spd.h | 15 ++------------- .../intel/cannonlake_rvp/spd/spd_util.c | 15 ++------------- .../cannonlake_rvp/variants/baseboard/gpio.c | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../cannonlake_rvp/variants/baseboard/nhlt.c | 15 ++------------- .../variants/cnl_u/include/variant/gpio.h | 15 ++------------- .../variants/cnl_y/include/variant/gpio.h | 15 ++------------- src/mainboard/intel/coffeelake_rvp/bootblock.c | 15 ++------------- src/mainboard/intel/coffeelake_rvp/chromeos.c | 15 ++------------- src/mainboard/intel/coffeelake_rvp/dsdt.asl | 15 ++------------- src/mainboard/intel/coffeelake_rvp/hda_verb.c | 15 ++------------- src/mainboard/intel/coffeelake_rvp/mainboard.c | 15 ++------------- src/mainboard/intel/coffeelake_rvp/memory.c | 15 ++------------- src/mainboard/intel/coffeelake_rvp/romstage.c | 15 ++------------- .../coffeelake_rvp/variants/baseboard/gpio.c | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../coffeelake_rvp/variants/baseboard/nhlt.c | 15 ++------------- .../variants/cfl_h/include/variant/hda_verb.h | 15 ++------------- .../variants/cfl_s/include/variant/hda_verb.h | 15 ++------------- .../variants/cml_u/include/variant/gpio.h | 15 ++------------- .../variants/cml_u/include/variant/hda_verb.h | 15 ++------------- .../variants/whl_u/include/variant/gpio.h | 15 ++------------- .../variants/whl_u/include/variant/hda_verb.h | 15 ++------------- .../intel/d510mo/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/intel/d510mo/acpi_tables.c | 15 ++------------- src/mainboard/intel/d510mo/cstates.c | 15 ++------------- src/mainboard/intel/d510mo/dsdt.asl | 15 ++------------- src/mainboard/intel/d510mo/gpio.c | 15 ++------------- src/mainboard/intel/d510mo/hda_verb.c | 15 ++------------- src/mainboard/intel/d510mo/mainboard.c | 15 ++------------- src/mainboard/intel/d945gclf/acpi/ec.asl | 15 ++------------- .../intel/d945gclf/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/intel/d945gclf/acpi/mainboard.asl | 15 ++------------- src/mainboard/intel/d945gclf/acpi/platform.asl | 15 ++------------- src/mainboard/intel/d945gclf/acpi/superio.asl | 15 ++------------- src/mainboard/intel/d945gclf/acpi_tables.c | 15 ++------------- src/mainboard/intel/d945gclf/cstates.c | 14 ++------------ src/mainboard/intel/d945gclf/dsdt.asl | 15 ++------------- src/mainboard/intel/d945gclf/early_init.c | 15 ++------------- src/mainboard/intel/d945gclf/gpio.c | 15 ++------------- src/mainboard/intel/d945gclf/hda_verb.c | 14 ++------------ src/mainboard/intel/d945gclf/irq_tables.c | 15 ++------------- src/mainboard/intel/d945gclf/mptable.c | 15 ++------------- src/mainboard/intel/dcp847ske/acpi/platform.asl | 16 ++-------------- src/mainboard/intel/dcp847ske/acpi/superio.asl | 15 ++------------- src/mainboard/intel/dcp847ske/acpi_tables.c | 16 ++-------------- src/mainboard/intel/dcp847ske/dsdt.asl | 16 ++-------------- .../intel/dcp847ske/early_southbridge.c | 16 ++-------------- src/mainboard/intel/dcp847ske/gpio.c | 16 ++-------------- src/mainboard/intel/dcp847ske/hda_verb.c | 16 ++-------------- src/mainboard/intel/dcp847ske/mainboard.c | 16 ++-------------- src/mainboard/intel/dcp847ske/romstage.c | 16 ++-------------- src/mainboard/intel/dcp847ske/smihandler.c | 16 ++-------------- src/mainboard/intel/dcp847ske/superio.h | 16 ++-------------- src/mainboard/intel/dcp847ske/thermal.h | 15 ++------------- src/mainboard/intel/dcp847ske/usb.h | 16 ++-------------- .../intel/dg41wv/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/intel/dg41wv/acpi/superio.asl | 14 ++------------ src/mainboard/intel/dg41wv/acpi_tables.c | 15 ++------------- src/mainboard/intel/dg41wv/cstates.c | 15 ++------------- src/mainboard/intel/dg41wv/dsdt.asl | 15 ++------------- src/mainboard/intel/dg41wv/gpio.c | 15 ++------------- .../intel/dg43gt/acpi/ich10_pci_irqs.asl | 15 ++------------- src/mainboard/intel/dg43gt/acpi/superio.asl | 14 ++------------ src/mainboard/intel/dg43gt/acpi_tables.c | 15 ++------------- src/mainboard/intel/dg43gt/cstates.c | 14 ++------------ src/mainboard/intel/dg43gt/dsdt.asl | 15 ++------------- src/mainboard/intel/dg43gt/gpio.c | 15 ++------------- .../intel/emeraldlake2/acpi/mainboard.asl | 16 ++-------------- .../intel/emeraldlake2/acpi/platform.asl | 15 ++------------- .../intel/emeraldlake2/acpi/superio.asl | 15 ++------------- .../intel/emeraldlake2/acpi/thermal.asl | 15 ++------------- src/mainboard/intel/emeraldlake2/acpi_tables.c | 15 ++------------- src/mainboard/intel/emeraldlake2/chromeos.c | 15 ++------------- src/mainboard/intel/emeraldlake2/dsdt.asl | 15 ++------------- src/mainboard/intel/emeraldlake2/early_init.c | 15 ++------------- src/mainboard/intel/emeraldlake2/ec.c | 15 ++------------- src/mainboard/intel/emeraldlake2/ec.h | 15 ++------------- src/mainboard/intel/emeraldlake2/gpio.c | 15 ++------------- src/mainboard/intel/emeraldlake2/hda_verb.c | 15 ++------------- src/mainboard/intel/emeraldlake2/mainboard.c | 15 ++------------- src/mainboard/intel/emeraldlake2/smihandler.c | 15 ++------------- src/mainboard/intel/emeraldlake2/thermal.h | 15 ++------------- src/mainboard/intel/galileo/acpi_tables.c | 15 ++------------- src/mainboard/intel/galileo/dsdt.asl | 15 ++------------- src/mainboard/intel/galileo/gen1.h | 15 ++------------- src/mainboard/intel/galileo/gen2.h | 15 ++------------- src/mainboard/intel/galileo/gpio.c | 15 ++------------- src/mainboard/intel/galileo/mainboard.c | 15 ++------------- src/mainboard/intel/galileo/reg_access.c | 15 ++------------- src/mainboard/intel/galileo/reg_access.h | 15 ++------------- src/mainboard/intel/galileo/sd.c | 15 ++------------- src/mainboard/intel/glkrvp/boardid.c | 15 ++------------- src/mainboard/intel/glkrvp/bootblock.c | 15 ++------------- src/mainboard/intel/glkrvp/chromeos.c | 15 ++------------- src/mainboard/intel/glkrvp/dsdt.asl | 15 ++------------- src/mainboard/intel/glkrvp/ec.c | 15 ++------------- src/mainboard/intel/glkrvp/mainboard.c | 15 ++------------- src/mainboard/intel/glkrvp/romstage.c | 15 ++------------- src/mainboard/intel/glkrvp/smihandler.c | 15 ++------------- src/mainboard/intel/glkrvp/touchpad.asl | 15 ++------------- src/mainboard/intel/glkrvp/touchpanel.asl | 15 ++------------- .../intel/glkrvp/variants/baseboard/boardid.c | 15 ++------------- .../intel/glkrvp/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/acpi/dptf.asl | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../intel/glkrvp/variants/baseboard/memory.c | 15 ++------------- .../intel/glkrvp/variants/baseboard/nhlt.c | 15 ++------------- .../glkrvp/include/variant/acpi/dptf.asl | 15 ++------------- .../glkrvp/variants/glkrvp/include/variant/ec.h | 15 ++------------- .../variants/glkrvp/include/variant/gpio.h | 15 ++------------- src/mainboard/intel/harcuvar/acpi/mainboard.asl | 16 ++-------------- .../intel/harcuvar/acpi/mainboard_pci_irqs.asl | 16 ++-------------- src/mainboard/intel/harcuvar/acpi/platform.asl | 16 ++-------------- src/mainboard/intel/harcuvar/acpi/thermal.asl | 16 ++-------------- src/mainboard/intel/harcuvar/acpi_tables.c | 16 ++-------------- src/mainboard/intel/harcuvar/boardid.c | 16 ++-------------- src/mainboard/intel/harcuvar/dsdt.asl | 16 ++-------------- src/mainboard/intel/harcuvar/emmc.h | 16 ++-------------- src/mainboard/intel/harcuvar/fadt.c | 16 ++-------------- src/mainboard/intel/harcuvar/gpio.h | 16 ++-------------- src/mainboard/intel/harcuvar/harcuvar_boardid.h | 16 ++-------------- src/mainboard/intel/harcuvar/hsio.c | 15 ++------------- src/mainboard/intel/harcuvar/hsio.h | 16 ++-------------- src/mainboard/intel/harcuvar/ramstage.c | 16 ++-------------- src/mainboard/intel/harcuvar/spd/spd.c | 16 ++-------------- src/mainboard/intel/harcuvar/spd/spd.h | 16 ++-------------- .../intel/icelake_rvp/acpi/mainboard.asl | 15 ++------------- src/mainboard/intel/icelake_rvp/board_id.c | 15 ++------------- src/mainboard/intel/icelake_rvp/board_id.h | 15 ++------------- src/mainboard/intel/icelake_rvp/bootblock.c | 15 ++------------- src/mainboard/intel/icelake_rvp/chromeos.c | 15 ++------------- src/mainboard/intel/icelake_rvp/dsdt.asl | 15 ++------------- src/mainboard/intel/icelake_rvp/hda_verb.c | 15 ++------------- src/mainboard/intel/icelake_rvp/mainboard.c | 15 ++------------- .../intel/icelake_rvp/romstage_fsp_params.c | 15 ++------------- src/mainboard/intel/icelake_rvp/spd/spd.h | 15 ++------------- src/mainboard/intel/icelake_rvp/spd/spd_util.c | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/hda_verb.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../intel/icelake_rvp/variants/icl_u/gpio.c | 15 ++------------- .../intel/icelake_rvp/variants/icl_y/gpio.c | 15 ++------------- .../intel/jasperlake_rvp/acpi/mainboard.asl | 15 ++------------- src/mainboard/intel/jasperlake_rvp/board_id.c | 16 ++-------------- src/mainboard/intel/jasperlake_rvp/board_id.h | 15 ++------------- src/mainboard/intel/jasperlake_rvp/bootblock.c | 15 ++------------- src/mainboard/intel/jasperlake_rvp/chromeos.c | 15 ++------------- src/mainboard/intel/jasperlake_rvp/dsdt.asl | 15 ++------------- src/mainboard/intel/jasperlake_rvp/mainboard.c | 15 ++------------- .../intel/jasperlake_rvp/romstage_fsp_params.c | 17 +++-------------- src/mainboard/intel/jasperlake_rvp/spd/spd.h | 15 ++------------- .../intel/jasperlake_rvp/spd/spd_util.c | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 16 ++-------------- .../intel/jasperlake_rvp/variants/jslrvp/gpio.c | 15 ++------------- .../jasperlake_rvp/variants/jslrvp/memory.c | 16 ++-------------- src/mainboard/intel/kblrvp/acpi/dptf.asl | 15 ++------------- src/mainboard/intel/kblrvp/acpi/ec.asl | 15 ++------------- .../intel/kblrvp/acpi/ipu_mainboard.asl | 15 ++------------- src/mainboard/intel/kblrvp/acpi/mainboard.asl | 15 ++------------- src/mainboard/intel/kblrvp/acpi/mipi_camera.asl | 15 ++------------- src/mainboard/intel/kblrvp/acpi/superio.asl | 15 ++------------- src/mainboard/intel/kblrvp/board_id.c | 15 ++------------- src/mainboard/intel/kblrvp/board_id.h | 15 ++------------- src/mainboard/intel/kblrvp/bootblock.c | 15 ++------------- src/mainboard/intel/kblrvp/chromeos.c | 15 ++------------- src/mainboard/intel/kblrvp/dsdt.asl | 15 ++------------- src/mainboard/intel/kblrvp/ec.c | 15 ++------------- src/mainboard/intel/kblrvp/ec.h | 15 ++------------- src/mainboard/intel/kblrvp/hda_verb.c | 15 ++------------- src/mainboard/intel/kblrvp/mainboard.c | 15 ++------------- src/mainboard/intel/kblrvp/ramstage.c | 15 ++------------- src/mainboard/intel/kblrvp/romstage.c | 15 ++------------- src/mainboard/intel/kblrvp/smihandler.c | 15 ++------------- src/mainboard/intel/kblrvp/spd/spd.h | 15 ++------------- src/mainboard/intel/kblrvp/spd/spd_util.c | 15 ++------------- .../variants/rvp11/include/variant/gpio.h | 15 ++------------- .../variants/rvp11/include/variant/hda_verb.h | 15 ++------------- .../kblrvp/variants/rvp3/include/variant/gpio.h | 15 ++------------- .../variants/rvp3/include/variant/hda_verb.h | 15 ++------------- .../kblrvp/variants/rvp7/include/variant/gpio.h | 15 ++------------- .../variants/rvp7/include/variant/hda_verb.h | 15 ++------------- .../kblrvp/variants/rvp8/include/variant/gpio.h | 15 ++------------- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 15 ++------------- src/mainboard/intel/kunimitsu/acpi/ec.asl | 15 ++------------- .../intel/kunimitsu/acpi/mainboard.asl | 15 ++------------- src/mainboard/intel/kunimitsu/acpi/superio.asl | 15 ++------------- .../intel/kunimitsu/bootblock_mainboard.c | 15 ++------------- src/mainboard/intel/kunimitsu/chromeos.c | 15 ++------------- src/mainboard/intel/kunimitsu/dsdt.asl | 15 ++------------- src/mainboard/intel/kunimitsu/ec.c | 15 ++------------- src/mainboard/intel/kunimitsu/ec.h | 15 ++------------- src/mainboard/intel/kunimitsu/gpio.h | 15 ++------------- src/mainboard/intel/kunimitsu/mainboard.c | 15 ++------------- src/mainboard/intel/kunimitsu/ramstage.c | 15 ++------------- src/mainboard/intel/kunimitsu/romstage.c | 15 ++------------- src/mainboard/intel/kunimitsu/smihandler.c | 15 ++------------- src/mainboard/intel/kunimitsu/spd/spd.h | 15 ++------------- src/mainboard/intel/kunimitsu/spd/spd_util.c | 15 ++------------- src/mainboard/intel/leafhill/bootblock.c | 15 ++------------- src/mainboard/intel/leafhill/brd_gpio.h | 15 ++------------- src/mainboard/intel/leafhill/dsdt.asl | 15 ++------------- src/mainboard/intel/leafhill/mainboard.c | 15 ++------------- src/mainboard/intel/leafhill/romstage.c | 15 ++------------- src/mainboard/intel/minnow3/bootblock.c | 15 ++------------- src/mainboard/intel/minnow3/dsdt.asl | 15 ++------------- src/mainboard/intel/minnow3/gpio.c | 15 ++------------- src/mainboard/intel/minnow3/gpio.h | 15 ++------------- src/mainboard/intel/minnow3/mainboard.c | 15 ++------------- src/mainboard/intel/minnow3/romstage.c | 15 ++------------- .../intel/saddlebrook/acpi/mainboard.asl | 15 ++------------- src/mainboard/intel/saddlebrook/bootblock.c | 15 ++------------- src/mainboard/intel/saddlebrook/dsdt.asl | 15 ++------------- src/mainboard/intel/saddlebrook/gpio.h | 15 ++------------- src/mainboard/intel/saddlebrook/ramstage.c | 15 ++------------- src/mainboard/intel/saddlebrook/romstage.c | 15 ++------------- src/mainboard/intel/saddlebrook/spd/spd.h | 15 ++------------- src/mainboard/intel/saddlebrook/spd/spd_util.c | 15 ++------------- src/mainboard/intel/strago/acpi/dptf.asl | 15 ++------------- src/mainboard/intel/strago/acpi/ec.asl | 15 ++------------- src/mainboard/intel/strago/acpi/mainboard.asl | 16 ++-------------- src/mainboard/intel/strago/acpi/superio.asl | 15 ++------------- src/mainboard/intel/strago/acpi_tables.c | 15 ++------------- src/mainboard/intel/strago/chromeos.c | 15 ++------------- src/mainboard/intel/strago/com_init.c | 15 ++------------- src/mainboard/intel/strago/dsdt.asl | 15 ++------------- src/mainboard/intel/strago/ec.c | 15 ++------------- src/mainboard/intel/strago/ec.h | 15 ++------------- src/mainboard/intel/strago/fadt.c | 15 ++------------- src/mainboard/intel/strago/gpio.c | 15 ++------------- src/mainboard/intel/strago/irqroute.c | 15 ++------------- src/mainboard/intel/strago/irqroute.h | 15 ++------------- src/mainboard/intel/strago/mainboard.c | 15 ++------------- src/mainboard/intel/strago/onboard.h | 15 ++------------- src/mainboard/intel/strago/ramstage.c | 15 ++------------- src/mainboard/intel/strago/romstage.c | 15 ++------------- src/mainboard/intel/strago/smihandler.c | 15 ++------------- src/mainboard/intel/strago/w25q64.c | 15 ++------------- src/mainboard/intel/tglrvp/acpi/mainboard.asl | 15 ++------------- src/mainboard/intel/tglrvp/acpi/mipi_camera.asl | 15 ++------------- src/mainboard/intel/tglrvp/board_id.c | 15 ++------------- src/mainboard/intel/tglrvp/board_id.h | 15 ++------------- src/mainboard/intel/tglrvp/bootblock.c | 15 ++------------- src/mainboard/intel/tglrvp/chromeos.c | 15 ++------------- src/mainboard/intel/tglrvp/dsdt.asl | 15 ++------------- src/mainboard/intel/tglrvp/mainboard.c | 15 ++------------- .../intel/tglrvp/romstage_fsp_params.c | 15 ++------------- src/mainboard/intel/tglrvp/spd/spd.h | 15 ++------------- src/mainboard/intel/tglrvp/spd/spd_util.c | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../intel/tglrvp/variants/tglrvp_up3/gpio.c | 15 ++------------- .../intel/tglrvp/variants/tglrvp_up3/memory.c | 15 ++------------- .../intel/tglrvp/variants/tglrvp_up4/gpio.c | 15 ++------------- .../intel/tglrvp/variants/tglrvp_up4/memory.c | 15 ++------------- src/mainboard/intel/wtm2/acpi/ec.asl | 14 ++------------ src/mainboard/intel/wtm2/acpi/mainboard.asl | 16 ++-------------- src/mainboard/intel/wtm2/acpi/platform.asl | 15 ++------------- src/mainboard/intel/wtm2/acpi/thermal.asl | 15 ++------------- src/mainboard/intel/wtm2/acpi_tables.c | 15 ++------------- src/mainboard/intel/wtm2/chromeos.c | 15 ++------------- src/mainboard/intel/wtm2/dsdt.asl | 15 ++------------- src/mainboard/intel/wtm2/fadt.c | 15 ++------------- src/mainboard/intel/wtm2/gpio.c | 15 ++------------- src/mainboard/intel/wtm2/hda_verb.c | 15 ++------------- src/mainboard/intel/wtm2/mainboard.c | 15 ++------------- src/mainboard/intel/wtm2/pei_data.c | 15 ++------------- src/mainboard/intel/wtm2/romstage.c | 15 ++------------- src/mainboard/intel/wtm2/thermal.h | 15 ++------------- 296 files changed, 593 insertions(+), 3876 deletions(-) diff --git a/src/mainboard/intel/baskingridge/acpi/mainboard.asl b/src/mainboard/intel/baskingridge/acpi/mainboard.asl index 91bfe1a09d..d551e51be9 100644 --- a/src/mainboard/intel/baskingridge/acpi/mainboard.asl +++ b/src/mainboard/intel/baskingridge/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PWRB) { diff --git a/src/mainboard/intel/baskingridge/acpi/platform.asl b/src/mainboard/intel/baskingridge/acpi/platform.asl index 9a79b56e72..94ee222d51 100644 --- a/src/mainboard/intel/baskingridge/acpi/platform.asl +++ b/src/mainboard/intel/baskingridge/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/baskingridge/acpi/superio.asl b/src/mainboard/intel/baskingridge/acpi/superio.asl index 2d151969d4..f271f7b63b 100644 --- a/src/mainboard/intel/baskingridge/acpi/superio.asl +++ b/src/mainboard/intel/baskingridge/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl index b7864f8599..90e36f6e96 100644 --- a/src/mainboard/intel/baskingridge/acpi/thermal.asl +++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index f688af22f8..935acf17ed 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index a814c94ae6..6a42dc7a45 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index e185335439..8957f752a1 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ENABLE_TPM diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h index 7a18085d83..4ec8dabcc5 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASKING_RIDGE_GPIO_H #define BASKING_RIDGE_GPIO_H diff --git a/src/mainboard/intel/baskingridge/hda_verb.c b/src/mainboard/intel/baskingridge/hda_verb.c index 11041770e4..18eedc23cd 100644 --- a/src/mainboard/intel/baskingridge/hda_verb.c +++ b/src/mainboard/intel/baskingridge/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index d60d3bf7d8..db86877de3 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index cc9b0e7473..5eef5eb31a 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 2f89262c4d..b89d13593c 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/baskingridge/thermal.h b/src/mainboard/intel/baskingridge/thermal.h index e8a93cc01a..af37141d8b 100644 --- a/src/mainboard/intel/baskingridge/thermal.h +++ b/src/mainboard/intel/baskingridge/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASKING_RIDGE_THERMAL_H #define BASKING_RIDGE_THERMAL_H diff --git a/src/mainboard/intel/cannonlake_rvp/bootblock.c b/src/mainboard/intel/cannonlake_rvp/bootblock.c index c43ea9a503..28061399a1 100644 --- a/src/mainboard/intel/cannonlake_rvp/bootblock.c +++ b/src/mainboard/intel/cannonlake_rvp/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index c23c49640b..f4a7b43842 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 6455c123a6..23a3932a6f 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c index 3f6174deba..1fb4997b5d 100644 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c index 91daaaebc8..483270abb8 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/smihandler.c b/src/mainboard/intel/cannonlake_rvp/smihandler.c index e2573d022a..98459b6060 100644 --- a/src/mainboard/intel/cannonlake_rvp/smihandler.c +++ b/src/mainboard/intel/cannonlake_rvp/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h index fc5686004a..9a348af09e 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd.h +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 72439aa0d6..c45491795b 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index 560aab90da..0acae5867c 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h index 84d0c9ec9c..f5c5715c6e 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h index 1f54bf7065..7968ed77b8 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c index 42573712d9..003408e322 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c index bba133f9bd..1a7cd2a1b6 100644 --- a/src/mainboard/intel/coffeelake_rvp/bootblock.c +++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 48db5bcdbb..29d8fcca16 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 03ecf114a3..1aa9020fcb 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/coffeelake_rvp/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/hda_verb.c index 3fbc3a24c3..6a54dbddbe 100644 --- a/src/mainboard/intel/coffeelake_rvp/hda_verb.c +++ b/src/mainboard/intel/coffeelake_rvp/hda_verb.c @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "variant/hda_verb.h" diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index 6077cbfbba..48dbeb48ce 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index 85d089f74a..d7d8b4e6f2 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index e0532db7e3..b10e1bd8d4 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index 62b0b372a8..ced535ee2f 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h index 84d0c9ec9c..f5c5715c6e 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index bbdcedfdf6..6e1b90a24e 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c index d342678c3e..c624fc1234 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h index c285da7644..78ab56654c 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h index c285da7644..78ab56654c 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h index d776f4c1b3..3131debf58 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h index d776f4c1b3..3131debf58 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl index dc58f02077..255abe84b3 100644 --- a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c index 69787a93ea..f9c941d79e 100644 --- a/src/mainboard/intel/d510mo/acpi_tables.c +++ b/src/mainboard/intel/d510mo/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c index 62b3bd3fba..10498e1150 100644 --- a/src/mainboard/intel/d510mo/cstates.c +++ b/src/mainboard/intel/d510mo/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index 88b4e126e5..75b17df090 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/d510mo/gpio.c b/src/mainboard/intel/d510mo/gpio.c index 71e93613f2..006c67542f 100644 --- a/src/mainboard/intel/d510mo/gpio.c +++ b/src/mainboard/intel/d510mo/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c index 6561ddf3a9..6c48e65049 100644 --- a/src/mainboard/intel/d510mo/hda_verb.c +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index dd930d31ad..4834c625b1 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/d945gclf/acpi/ec.asl b/src/mainboard/intel/d945gclf/acpi/ec.asl index f42855b182..0cff3760bd 100644 --- a/src/mainboard/intel/d945gclf/acpi/ec.asl +++ b/src/mainboard/intel/d945gclf/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device(EC0) { diff --git a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl index a079c059e0..209ba8329c 100644 --- a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl index 5187b2a973..1e31c06ec9 100644 --- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl +++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (SLPB) { diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 01c7a94906..64db274094 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/intel/d945gclf/acpi/superio.asl b/src/mainboard/intel/d945gclf/acpi/superio.asl index 23e5fd5d26..eadc3edc84 100644 --- a/src/mainboard/intel/d945gclf/acpi/superio.asl +++ b/src/mainboard/intel/d945gclf/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (SIO1) diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index 69787a93ea..f9c941d79e 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d945gclf/cstates.c b/src/mainboard/intel/d945gclf/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/intel/d945gclf/cstates.c +++ b/src/mainboard/intel/d945gclf/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index c9d81f523d..9e3c03748c 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c index 61fa10ccd9..5f9a78532f 100644 --- a/src/mainboard/intel/d945gclf/early_init.c +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/d945gclf/gpio.c b/src/mainboard/intel/d945gclf/gpio.c index 5c672afd8b..02464f2ffa 100644 --- a/src/mainboard/intel/d945gclf/gpio.c +++ b/src/mainboard/intel/d945gclf/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d945gclf/hda_verb.c b/src/mainboard/intel/d945gclf/hda_verb.c index 5d088790a5..0700c48e63 100644 --- a/src/mainboard/intel/d945gclf/hda_verb.c +++ b/src/mainboard/intel/d945gclf/hda_verb.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d945gclf/irq_tables.c b/src/mainboard/intel/d945gclf/irq_tables.c index 9235d23f22..4820e6dcb9 100644 --- a/src/mainboard/intel/d945gclf/irq_tables.c +++ b/src/mainboard/intel/d945gclf/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index 62d014733f..13ebea4e0c 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/dcp847ske/acpi/platform.asl b/src/mainboard/intel/dcp847ske/acpi/platform.asl index 5cce4b4997..8f429c5b4e 100644 --- a/src/mainboard/intel/dcp847ske/acpi/platform.asl +++ b/src/mainboard/intel/dcp847ske/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index abf7e244e5..519fe3b9b5 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index c546640ba3..cd320ccb60 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "thermal.h" diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index faf012600a..8f318b4817 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index f0b82f02f2..40b7f7ee80 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/dcp847ske/gpio.c b/src/mainboard/intel/dcp847ske/gpio.c index ebfefdf3dc..0f1c52127f 100644 --- a/src/mainboard/intel/dcp847ske/gpio.c +++ b/src/mainboard/intel/dcp847ske/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c index 1282140a25..b5ffb81f94 100644 --- a/src/mainboard/intel/dcp847ske/hda_verb.c +++ b/src/mainboard/intel/dcp847ske/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/dcp847ske/mainboard.c index 8c443682ef..3f7a91e28d 100644 --- a/src/mainboard/intel/dcp847ske/mainboard.c +++ b/src/mainboard/intel/dcp847ske/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 34698f97e2..613e73c367 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/dcp847ske/smihandler.c b/src/mainboard/intel/dcp847ske/smihandler.c index b8f4e765f0..a8b6560a14 100644 --- a/src/mainboard/intel/dcp847ske/smihandler.c +++ b/src/mainboard/intel/dcp847ske/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/dcp847ske/superio.h index 31dc7d91cd..a2c96274e9 100644 --- a/src/mainboard/intel/dcp847ske/superio.h +++ b/src/mainboard/intel/dcp847ske/superio.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DCP847SKE_SUPERIO_H #define DCP847SKE_SUPERIO_H diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h index 1b7e863d9c..f2f11ebdf2 100644 --- a/src/mainboard/intel/dcp847ske/thermal.h +++ b/src/mainboard/intel/dcp847ske/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DCP847SKE_THERMAL_H #define DPC847SKE_THERMAL_H diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h index 10110fc010..d0bc9dc060 100644 --- a/src/mainboard/intel/dcp847ske/usb.h +++ b/src/mainboard/intel/dcp847ske/usb.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DCP847SKE_USB_H #define DPC847SKE_USB_H diff --git a/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl index 3e37d9cd91..dd2803fbc2 100644 --- a/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is board specific information: diff --git a/src/mainboard/intel/dg41wv/acpi/superio.asl b/src/mainboard/intel/dg41wv/acpi/superio.asl index 8b4a3cb0cb..169a739785 100644 --- a/src/mainboard/intel/dg41wv/acpi/superio.asl +++ b/src/mainboard/intel/dg41wv/acpi/superio.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c index b0370c1ef4..7f47b3a7e2 100644 --- a/src/mainboard/intel/dg41wv/acpi_tables.c +++ b/src/mainboard/intel/dg41wv/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/dg41wv/cstates.c b/src/mainboard/intel/dg41wv/cstates.c index 2a6d8ad816..10498e1150 100644 --- a/src/mainboard/intel/dg41wv/cstates.c +++ b/src/mainboard/intel/dg41wv/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index 6120949269..8880ba7076 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/dg41wv/gpio.c b/src/mainboard/intel/dg41wv/gpio.c index 643b6d4d2b..4e972a1354 100644 --- a/src/mainboard/intel/dg41wv/gpio.c +++ b/src/mainboard/intel/dg41wv/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl index 8d12675cff..8697580948 100644 --- a/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl +++ b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 diff --git a/src/mainboard/intel/dg43gt/acpi/superio.asl b/src/mainboard/intel/dg43gt/acpi/superio.asl index 2fc3d8eee8..0866176b19 100644 --- a/src/mainboard/intel/dg43gt/acpi/superio.asl +++ b/src/mainboard/intel/dg43gt/acpi/superio.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 7e45c750c2..faa4021b72 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/dg43gt/cstates.c b/src/mainboard/intel/dg43gt/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/intel/dg43gt/cstates.c +++ b/src/mainboard/intel/dg43gt/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index 87696d5dda..cfc0b23dc2 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/dg43gt/gpio.c b/src/mainboard/intel/dg43gt/gpio.c index fdb25b41aa..4b2044e864 100644 --- a/src/mainboard/intel/dg43gt/gpio.c +++ b/src/mainboard/intel/dg43gt/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl b/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl index 91bfe1a09d..d551e51be9 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PWRB) { diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl index f7f187d66e..a1c9a70d2e 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/platform.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl index 2d151969d4..f271f7b63b 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl index 62b5f5d10c..43dd80e832 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index ebb9ba700b..8d54aa28da 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 1f087cec43..09fd057c9f 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index f7e22a71d3..1533583530 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 23229b83b1..0710871fc1 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index 009e90f973..c1d2046b45 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/emeraldlake2/ec.h b/src/mainboard/intel/emeraldlake2/ec.h index 3e44b584e6..b150fdf7ed 100644 --- a/src/mainboard/intel/emeraldlake2/ec.h +++ b/src/mainboard/intel/emeraldlake2/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LUMPY_EC_H #define LUMPY_EC_H diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c index e8f7b10f0b..a9025edc3d 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.c +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EMERALDLAKE2_GPIO_H #define EMERALDLAKE2_GPIO_H diff --git a/src/mainboard/intel/emeraldlake2/hda_verb.c b/src/mainboard/intel/emeraldlake2/hda_verb.c index 11041770e4..18eedc23cd 100644 --- a/src/mainboard/intel/emeraldlake2/hda_verb.c +++ b/src/mainboard/intel/emeraldlake2/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 74c365bcaf..06e3a65738 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index b267f20a7b..19575351b9 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/emeraldlake2/thermal.h b/src/mainboard/intel/emeraldlake2/thermal.h index 2fa579816e..974c0162e7 100644 --- a/src/mainboard/intel/emeraldlake2/thermal.h +++ b/src/mainboard/intel/emeraldlake2/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef EMERALDLAKE2_THERMAL_H #define EMERALDLAKE2_THERMAL_H diff --git a/src/mainboard/intel/galileo/acpi_tables.c b/src/mainboard/intel/galileo/acpi_tables.c index 80f4222b0e..5f5e1c2262 100644 --- a/src/mainboard/intel/galileo/acpi_tables.c +++ b/src/mainboard/intel/galileo/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl index b69ed78652..2c9e9c656c 100644 --- a/src/mainboard/intel/galileo/dsdt.asl +++ b/src/mainboard/intel/galileo/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index fbe5edece5..f8ceb98bc4 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCIe reset pin */ #define GEN1_PCI_RESET_RESUMEWELL_GPIO 3 diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h index 30abe1ee94..1eed023d0f 100644 --- a/src/mainboard/intel/galileo/gen2.h +++ b/src/mainboard/intel/galileo/gen2.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCIe reset pin */ #define GEN2_PCI_RESET_RESUMEWELL_GPIO 0 diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index c29769e504..f688cfaac0 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/galileo/mainboard.c b/src/mainboard/intel/galileo/mainboard.c index 234a154b58..ef9997abdf 100644 --- a/src/mainboard/intel/galileo/mainboard.c +++ b/src/mainboard/intel/galileo/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index c78ef8e2ac..b20d849223 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/mainboard/intel/galileo/reg_access.h b/src/mainboard/intel/galileo/reg_access.h index 53ffc66265..f8f322716f 100644 --- a/src/mainboard/intel/galileo/reg_access.h +++ b/src/mainboard/intel/galileo/reg_access.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _GALILEO_REG_ACCESS_H_ #define _GALILEO_REG_ACCESS_H_ diff --git a/src/mainboard/intel/galileo/sd.c b/src/mainboard/intel/galileo/sd.c index f832876e2f..694b2a44c5 100644 --- a/src/mainboard/intel/galileo/sd.c +++ b/src/mainboard/intel/galileo/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 3b377f21dd..b9c7cc6c37 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/bootblock.c b/src/mainboard/intel/glkrvp/bootblock.c index fe2513ba05..99d8202e43 100644 --- a/src/mainboard/intel/glkrvp/bootblock.c +++ b/src/mainboard/intel/glkrvp/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 2e8d85af38..f157bbcdd0 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 294e350a71..11313f9336 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c index 9782397526..cdafadb7ca 100644 --- a/src/mainboard/intel/glkrvp/ec.c +++ b/src/mainboard/intel/glkrvp/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index 0670afebad..d8ba962d47 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index 5420a16183..5bf897c7c7 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c index a08e17cdb8..73bf2ba0d3 100644 --- a/src/mainboard/intel/glkrvp/smihandler.c +++ b/src/mainboard/intel/glkrvp/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/touchpad.asl b/src/mainboard/intel/glkrvp/touchpad.asl index fe7e9e5f8b..f39453bd1d 100644 --- a/src/mainboard/intel/glkrvp/touchpad.asl +++ b/src/mainboard/intel/glkrvp/touchpad.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C4) { Device (TPAD) diff --git a/src/mainboard/intel/glkrvp/touchpanel.asl b/src/mainboard/intel/glkrvp/touchpanel.asl index 53b6b68b77..3dc6c030ef 100644 --- a/src/mainboard/intel/glkrvp/touchpanel.asl +++ b/src/mainboard/intel/glkrvp/touchpanel.asl @@ -1,17 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SB.PCI0.I2C7) { // Touch Panels on I2C7 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index e05cd5d5fa..608d791854 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index a08381d8a9..2c0073312f 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl index 8d18f92cec..befca1e2ed 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h index f3c1fb9cba..42261cb766 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_EC_H #define BASEBOARD_EC_H diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index 440b71bb7a..a45f61e29c 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_GPIO_H #define BASEBOARD_GPIO_H diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h index 0641a84555..07f455f6ca 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c index d1403e5005..9218fb2cf9 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c index a5929d3db0..b738a34c75 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl +++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h +++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard.asl b/src/mainboard/intel/harcuvar/acpi/mainboard.asl index 8d3f505cc6..afbadd37a6 100644 --- a/src/mainboard/intel/harcuvar/acpi/mainboard.asl +++ b/src/mainboard/intel/harcuvar/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl index b7254c91ba..2ea7a949c6 100644 --- a/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl +++ b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing */ diff --git a/src/mainboard/intel/harcuvar/acpi/platform.asl b/src/mainboard/intel/harcuvar/acpi/platform.asl index a1a1d214b9..b8d04f9ac0 100644 --- a/src/mainboard/intel/harcuvar/acpi/platform.asl +++ b/src/mainboard/intel/harcuvar/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/intel/harcuvar/acpi/thermal.asl b/src/mainboard/intel/harcuvar/acpi/thermal.asl index 8244266532..784abc33fa 100644 --- a/src/mainboard/intel/harcuvar/acpi/thermal.asl +++ b/src/mainboard/intel/harcuvar/acpi/thermal.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 551d51a47d..813bad943f 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/harcuvar/boardid.c b/src/mainboard/intel/harcuvar/boardid.c index 7ea9f87759..8f91b0c61d 100644 --- a/src/mainboard/intel/harcuvar/boardid.c +++ b/src/mainboard/intel/harcuvar/boardid.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 41e9b5d957..8c6c00d521 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/harcuvar/emmc.h b/src/mainboard/intel/harcuvar/emmc.h index cc51b7c4f8..51c3ee1518 100644 --- a/src/mainboard/intel/harcuvar/emmc.h +++ b/src/mainboard/intel/harcuvar/emmc.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_EMMC_H #define _MAINBOARD_EMMC_H diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index bb4b31eb46..8b38b3434c 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/harcuvar/gpio.h b/src/mainboard/intel/harcuvar/gpio.h index db4cc5c1d5..a973dd164e 100644 --- a/src/mainboard/intel/harcuvar/gpio.h +++ b/src/mainboard/intel/harcuvar/gpio.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_GPIO_H #define _MAINBOARD_GPIO_H diff --git a/src/mainboard/intel/harcuvar/harcuvar_boardid.h b/src/mainboard/intel/harcuvar/harcuvar_boardid.h index d85b6d90c1..28f28d9135 100644 --- a/src/mainboard/intel/harcuvar/harcuvar_boardid.h +++ b/src/mainboard/intel/harcuvar/harcuvar_boardid.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HARCUVAR_MAINBOARD_BOARD_H #define HARCUVAR_MAINBOARD_BOARD_H diff --git a/src/mainboard/intel/harcuvar/hsio.c b/src/mainboard/intel/harcuvar/hsio.c index 0c1861ce1b..d786b8fb2e 100644 --- a/src/mainboard/intel/harcuvar/hsio.c +++ b/src/mainboard/intel/harcuvar/hsio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h index f32fd3fd83..e8bfd2d14d 100644 --- a/src/mainboard/intel/harcuvar/hsio.h +++ b/src/mainboard/intel/harcuvar/hsio.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_HSIO_H #define _MAINBOARD_HSIO_H diff --git a/src/mainboard/intel/harcuvar/ramstage.c b/src/mainboard/intel/harcuvar/ramstage.c index 92fcc7d096..18d53e866c 100644 --- a/src/mainboard/intel/harcuvar/ramstage.c +++ b/src/mainboard/intel/harcuvar/ramstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index ca1cc2b283..81b312fe2b 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/harcuvar/spd/spd.h b/src/mainboard/intel/harcuvar/spd/spd.h index 1de7bed57d..42d902888c 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.h +++ b/src/mainboard/intel/harcuvar/spd/spd.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl index 521dfcb3cf..84b59cb78e 100644 --- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl +++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(EC_GOOGLE_CHROMEEC) Scope (\_SB) diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c index c284df1f77..9f39ff1273 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ b/src/mainboard/intel/icelake_rvp/board_id.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "board_id.h" #include #include diff --git a/src/mainboard/intel/icelake_rvp/board_id.h b/src/mainboard/intel/icelake_rvp/board_id.h index 6629244d92..b7d3d2eef5 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.h +++ b/src/mainboard/intel/icelake_rvp/board_id.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_BOARD_ID_H_ #define _MAINBOARD_BOARD_ID_H_ diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c index 9022af8e8c..8c85b82540 100644 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ b/src/mainboard/intel/icelake_rvp/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index e72333262a..a2181213d9 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 1a425f71d5..b7a012fbba 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c index 2a2a31d7d9..3665bb6dff 100644 --- a/src/mainboard/intel/icelake_rvp/hda_verb.c +++ b/src/mainboard/intel/icelake_rvp/hda_verb.c @@ -1,14 +1,3 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 2f6595f15b..41ef680d79 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index 833dcb9a1a..f336aa7059 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/icelake_rvp/spd/spd.h b/src/mainboard/intel/icelake_rvp/spd/spd.h index fc5686004a..9a348af09e 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd.h +++ b/src/mainboard/intel/icelake_rvp/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index 36ba7d09c5..8f4d178e8a 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h index 60ae713c5d..edf5febcc4 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h index 8d56b32f80..cbe8b0f288 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h index d776f4c1b3..3131debf58 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index 6beef66559..56a151937b 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index be0cf111d9..19ae89ab22 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index be0cf111d9..19ae89ab22 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl b/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl index 521dfcb3cf..84b59cb78e 100644 --- a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl +++ b/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(EC_GOOGLE_CHROMEEC) Scope (\_SB) diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.c b/src/mainboard/intel/jasperlake_rvp/board_id.c index 09d73cb9c3..7444feafb5 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.c +++ b/src/mainboard/intel/jasperlake_rvp/board_id.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2020 The coreboot project Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.h b/src/mainboard/intel/jasperlake_rvp/board_id.h index 86923b9b12..bb4aab7d35 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.h +++ b/src/mainboard/intel/jasperlake_rvp/board_id.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_ diff --git a/src/mainboard/intel/jasperlake_rvp/bootblock.c b/src/mainboard/intel/jasperlake_rvp/bootblock.c index 9022af8e8c..8c85b82540 100644 --- a/src/mainboard/intel/jasperlake_rvp/bootblock.c +++ b/src/mainboard/intel/jasperlake_rvp/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index bee7eba666..52da99cde0 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index ed59af6a96..c40acf29ef 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index b765eecc17..733bc5131f 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index f185628df1..d46c5fa9b6 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -1,17 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2020 The coreboot project Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #include #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd.h b/src/mainboard/intel/jasperlake_rvp/spd/spd.h index dcc0144a0b..9f74620024 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd.h +++ b/src/mainboard/intel/jasperlake_rvp/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c index 92d183dbc9..bc891fbab7 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h index 60ae713c5d..edf5febcc4 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h index 8d56b32f80..cbe8b0f288 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index 2fe7631281..595e9c0c5c 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2020 The coreboot project Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 91292b8c40..e094966ac5 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 4de66b3929..223e98a134 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2020 The coreboot project Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl index 0e19caab6d..ea3b942ce1 100644 --- a/src/mainboard/intel/kblrvp/acpi/dptf.asl +++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index eb9eb0eb7c..8ac51220e0 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl b/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl index a498246e65..1475bf647e 100644 --- a/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/ipu_mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 521dfcb3cf..84b59cb78e 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(EC_GOOGLE_CHROMEEC) Scope (\_SB) diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index c1c9bbb127..23c99a8469 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C2) { diff --git a/src/mainboard/intel/kblrvp/acpi/superio.asl b/src/mainboard/intel/kblrvp/acpi/superio.asl index f5178b3ed0..6e83a0a2bd 100644 --- a/src/mainboard/intel/kblrvp/acpi/superio.asl +++ b/src/mainboard/intel/kblrvp/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/intel/kblrvp/board_id.c b/src/mainboard/intel/kblrvp/board_id.c index 9d87a3eda1..bb770d650f 100644 --- a/src/mainboard/intel/kblrvp/board_id.c +++ b/src/mainboard/intel/kblrvp/board_id.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "board_id.h" #include #include diff --git a/src/mainboard/intel/kblrvp/board_id.h b/src/mainboard/intel/kblrvp/board_id.h index db9d2ba9cf..2dfae5d08e 100644 --- a/src/mainboard/intel/kblrvp/board_id.h +++ b/src/mainboard/intel/kblrvp/board_id.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_BOARD_ID_H_ #define _MAINBOARD_BOARD_ID_H_ diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c index 6d1885ecb4..30e5174945 100644 --- a/src/mainboard/intel/kblrvp/bootblock.c +++ b/src/mainboard/intel/kblrvp/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index c862907170..487efa732d 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 97fe66892b..91a5c2fedc 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/kblrvp/ec.c b/src/mainboard/intel/kblrvp/ec.c index eb5456a231..52819688a1 100644 --- a/src/mainboard/intel/kblrvp/ec.c +++ b/src/mainboard/intel/kblrvp/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/ec.h b/src/mainboard/intel/kblrvp/ec.h index dcdaae404e..0f46319d05 100644 --- a/src/mainboard/intel/kblrvp/ec.h +++ b/src/mainboard/intel/kblrvp/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/intel/kblrvp/hda_verb.c b/src/mainboard/intel/kblrvp/hda_verb.c index 50468cd135..8335c5c570 100644 --- a/src/mainboard/intel/kblrvp/hda_verb.c +++ b/src/mainboard/intel/kblrvp/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if !CONFIG(BOARD_INTEL_KBLRVP8) #include "variant/hda_verb.h" diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 7e2df109ea..639ad0e21b 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index f276913725..cb58897408 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 35ba6ed3d2..f9183d1853 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index 1673cd0df1..6874a4d022 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index de348f5000..80e8c81a6e 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 33970e147f..5314494604 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index 5a26b61d18..566737962a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _GPIORVP11_H #define _GPIORVP11_H diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h index 1b083a3ee6..1ff7e24818 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h index 7265b1affa..6afc1aa44c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h index 725623ae0d..c1f5edcdb8 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index 2c8c1df378..d0d840dfa0 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _GPIORVP7_H #define _GPIORVP7_H diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h index 0a38bed223..baed5dd246 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef HDA_VERB_H #define HDA_VERB_H diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index 320e7a6c20..a8d9108f22 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _GPIORVP8_H #define _GPIORVP8_H diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index b2b702d93b..9559fa827c 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_CRITICAL 99 diff --git a/src/mainboard/intel/kunimitsu/acpi/ec.asl b/src/mainboard/intel/kunimitsu/acpi/ec.asl index 09f5892067..a6dfd35b56 100644 --- a/src/mainboard/intel/kunimitsu/acpi/ec.asl +++ b/src/mainboard/intel/kunimitsu/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index 0e84faab18..8dc85d9423 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/intel/kunimitsu/acpi/superio.asl b/src/mainboard/intel/kunimitsu/acpi/superio.asl index f5178b3ed0..6e83a0a2bd 100644 --- a/src/mainboard/intel/kunimitsu/acpi/superio.asl +++ b/src/mainboard/intel/kunimitsu/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c index 534dad9b3d..40b1a7e6b3 100644 --- a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c +++ b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index c7454b49fa..524a7b724a 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 879e888c4e..046baa74ed 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/kunimitsu/ec.c b/src/mainboard/intel/kunimitsu/ec.c index eb5456a231..52819688a1 100644 --- a/src/mainboard/intel/kunimitsu/ec.c +++ b/src/mainboard/intel/kunimitsu/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kunimitsu/ec.h b/src/mainboard/intel/kunimitsu/ec.h index dcdaae404e..0f46319d05 100644 --- a/src/mainboard/intel/kunimitsu/ec.h +++ b/src/mainboard/intel/kunimitsu/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index fff0fc4e41..6862318d53 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 41453d4939..b645f7cb3c 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 975951ecae..ad70ca0c34 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "gpio.h" diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index ddd3c03565..e526dd80f4 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 35945851cf..17837bb0ca 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 8fbc09a777..4ab0388d7b 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 39a189b0ec..74039a99e2 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c index 3c8d5bd89c..695aaac1f0 100644 --- a/src/mainboard/intel/leafhill/bootblock.c +++ b/src/mainboard/intel/leafhill/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h index 25e1029397..57f2a11896 100644 --- a/src/mainboard/intel/leafhill/brd_gpio.h +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index f6f274489f..11ad0bb47e 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/leafhill/mainboard.c b/src/mainboard/intel/leafhill/mainboard.c index 1bc4152be2..8408a912f7 100644 --- a/src/mainboard/intel/leafhill/mainboard.c +++ b/src/mainboard/intel/leafhill/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c index 154a838e1b..4ea746712e 100644 --- a/src/mainboard/intel/leafhill/romstage.c +++ b/src/mainboard/intel/leafhill/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c index 1f5bddbc0e..e77241d232 100644 --- a/src/mainboard/intel/minnow3/bootblock.c +++ b/src/mainboard/intel/minnow3/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index f6f274489f..11ad0bb47e 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/minnow3/gpio.c b/src/mainboard/intel/minnow3/gpio.c index f8ff0e42cd..56786438bb 100644 --- a/src/mainboard/intel/minnow3/gpio.c +++ b/src/mainboard/intel/minnow3/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "gpio.h" diff --git a/src/mainboard/intel/minnow3/gpio.h b/src/mainboard/intel/minnow3/gpio.h index 57cece9783..8364ac42dc 100644 --- a/src/mainboard/intel/minnow3/gpio.h +++ b/src/mainboard/intel/minnow3/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/minnow3/mainboard.c b/src/mainboard/intel/minnow3/mainboard.c index 574ef039d4..117b84eacd 100644 --- a/src/mainboard/intel/minnow3/mainboard.c +++ b/src/mainboard/intel/minnow3/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "gpio.h" diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c index 66a40a1f0a..d76684d4c7 100644 --- a/src/mainboard/intel/minnow3/romstage.c +++ b/src/mainboard/intel/minnow3/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl index 55d11ab44c..4b79ee19ef 100644 --- a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl +++ b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/saddlebrook/bootblock.c b/src/mainboard/intel/saddlebrook/bootblock.c index 9d0a99b44b..bcc53b1e21 100644 --- a/src/mainboard/intel/saddlebrook/bootblock.c +++ b/src/mainboard/intel/saddlebrook/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index fa047f8d6b..8cff20f84d 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index 4db74cfe88..9a7228a541 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c index 975951ecae..ad70ca0c34 100644 --- a/src/mainboard/intel/saddlebrook/ramstage.c +++ b/src/mainboard/intel/saddlebrook/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "gpio.h" diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index a9447a2218..c034be07af 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index cb38a1b1db..2727a8c6b3 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 2f9fd07527..a1c20e14da 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl index 6ac42aa8cf..356a68a76f 100644 --- a/src/mainboard/intel/strago/acpi/dptf.asl +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl index 0b131615fb..e361a3e78f 100644 --- a/src/mainboard/intel/strago/acpi/ec.asl +++ b/src/mainboard/intel/strago/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "ec.h" diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index b43219e1e3..08eb8a409c 100644 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "onboard.h" diff --git a/src/mainboard/intel/strago/acpi/superio.asl b/src/mainboard/intel/strago/acpi/superio.asl index 35be89e496..756498b978 100644 --- a/src/mainboard/intel/strago/acpi/superio.asl +++ b/src/mainboard/intel/strago/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "ec.h" diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 265d110829..706e107378 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index ef61cadbdf..c77a6297ce 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index 88d8d091b6..81f853f32b 100644 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index 8ce41a99de..7abbcadab9 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index 8ebd096da5..55c3e1ff3c 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/ec.h b/src/mainboard/intel/strago/ec.h index 450d863ba3..b93c53fa33 100644 --- a/src/mainboard/intel/strago/ec.h +++ b/src/mainboard/intel/strago/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index 9e5af024e4..8d746676e9 100644 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 3a2adffb59..0a8c3c7544 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "irqroute.h" #include diff --git a/src/mainboard/intel/strago/irqroute.c b/src/mainboard/intel/strago/irqroute.c index f0855adbc2..df43ee9c69 100644 --- a/src/mainboard/intel/strago/irqroute.c +++ b/src/mainboard/intel/strago/irqroute.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "irqroute.h" diff --git a/src/mainboard/intel/strago/irqroute.h b/src/mainboard/intel/strago/irqroute.h index 85d8a5f93b..cacabfee84 100644 --- a/src/mainboard/intel/strago/irqroute.h +++ b/src/mainboard/intel/strago/irqroute.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 16c89fcd4e..00dccb7fef 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index c483b27c51..7726bb9a85 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index 47f791dc1c..f9ad6a0660 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index b312e53441..307cb2cb48 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "onboard.h" diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index f378eb7bea..4b1a2e2624 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c index 9e0b30a5fb..42a0727336 100644 --- a/src/mainboard/intel/strago/w25q64.c +++ b/src/mainboard/intel/strago/w25q64.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl index 521dfcb3cf..84b59cb78e 100644 --- a/src/mainboard/intel/tglrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/tglrvp/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(EC_GOOGLE_CHROMEEC) Scope (\_SB) diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index de26fd9d05..98189c04c1 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.IPU0) { diff --git a/src/mainboard/intel/tglrvp/board_id.c b/src/mainboard/intel/tglrvp/board_id.c index 1913d3f0fc..5516f63aad 100644 --- a/src/mainboard/intel/tglrvp/board_id.c +++ b/src/mainboard/intel/tglrvp/board_id.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index 748e9d912f..9f835c40b4 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_ diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c index 9022af8e8c..8c85b82540 100644 --- a/src/mainboard/intel/tglrvp/bootblock.c +++ b/src/mainboard/intel/tglrvp/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 2f2abb5e6b..c479c89d78 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index 89104e9ab0..af13d9f5c1 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 680472b71b..d7320c935c 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index d8057f6564..2cf219d61b 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h index f5ba411a50..44c0e26634 100644 --- a/src/mainboard/intel/tglrvp/spd/spd.h +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/intel/tglrvp/spd/spd_util.c b/src/mainboard/intel/tglrvp/spd/spd_util.c index fa1204ec74..9110cb1b1b 100644 --- a/src/mainboard/intel/tglrvp/spd/spd_util.c +++ b/src/mainboard/intel/tglrvp/spd/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index 60ae713c5d..edf5febcc4 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h index 8d56b32f80..cbe8b0f288 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index b38daff853..acb24534e9 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 758a21c5c9..79ffd38f27 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index ad2f24f9c1..4a57a555c5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 219786535a..27d610b48c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index 929d0cca89..2a463d5a87 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/wtm2/acpi/ec.asl b/src/mainboard/intel/wtm2/acpi/ec.asl index d7ef095d9c..f9fa120c13 100644 --- a/src/mainboard/intel/wtm2/acpi/ec.asl +++ b/src/mainboard/intel/wtm2/acpi/ec.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EC0) { diff --git a/src/mainboard/intel/wtm2/acpi/mainboard.asl b/src/mainboard/intel/wtm2/acpi/mainboard.asl index 776b63e2fc..245e9d5ac3 100644 --- a/src/mainboard/intel/wtm2/acpi/mainboard.asl +++ b/src/mainboard/intel/wtm2/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PWRB) { diff --git a/src/mainboard/intel/wtm2/acpi/platform.asl b/src/mainboard/intel/wtm2/acpi/platform.asl index 92c98614d7..b8d04f9ac0 100644 --- a/src/mainboard/intel/wtm2/acpi/platform.asl +++ b/src/mainboard/intel/wtm2/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/intel/wtm2/acpi/thermal.asl b/src/mainboard/intel/wtm2/acpi/thermal.asl index e8af50bf87..3d5fd7cb91 100644 --- a/src/mainboard/intel/wtm2/acpi/thermal.asl +++ b/src/mainboard/intel/wtm2/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Generated by acpigen */ External (\PPKG, MethodObj) diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 727d17572c..e06e42b1cc 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 6926ed08aa..afbd1a2c0f 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index d4de0ca0b1..18609ac9f7 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ENABLE_TPM diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 621beb9655..d580259ba6 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/wtm2/gpio.c b/src/mainboard/intel/wtm2/gpio.c index c2d7bf87d2..a95e21e4df 100644 --- a/src/mainboard/intel/wtm2/gpio.c +++ b/src/mainboard/intel/wtm2/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/wtm2/hda_verb.c b/src/mainboard/intel/wtm2/hda_verb.c index 11041770e4..18eedc23cd 100644 --- a/src/mainboard/intel/wtm2/hda_verb.c +++ b/src/mainboard/intel/wtm2/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index aa4a707798..026a28dc2f 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index c1e3f21d4a..d71e6b239d 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index db2ecf5bcd..b4263446ac 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/intel/wtm2/thermal.h b/src/mainboard/intel/wtm2/thermal.h index e26631fd7b..ec2ae80405 100644 --- a/src/mainboard/intel/wtm2/thermal.h +++ b/src/mainboard/intel/wtm2/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef WTM2_THERMAL_H #define WTM2_THERMAL_H From 5f1bf2f90536e227eafea67c10e1b63e1daa6563 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:16 +0200 Subject: [PATCH 0838/1463] mainboard/asus: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I92d0dc8d93a8b409959d79834ccb5093224285cb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40067 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asus/am1i-a/BiosCallOuts.c | 15 ++------------- src/mainboard/asus/am1i-a/OemCustomize.c | 15 ++------------- src/mainboard/asus/am1i-a/OptionsIds.h | 15 ++------------- src/mainboard/asus/am1i-a/acpi/mainboard.asl | 15 ++------------- src/mainboard/asus/am1i-a/acpi/routing.asl | 15 ++------------- src/mainboard/asus/am1i-a/acpi/sata.asl | 15 ++------------- src/mainboard/asus/am1i-a/acpi/si.asl | 15 ++------------- src/mainboard/asus/am1i-a/acpi/sleep.asl | 15 ++------------- src/mainboard/asus/am1i-a/acpi/superio.asl | 15 ++------------- src/mainboard/asus/am1i-a/acpi_tables.c | 15 ++------------- src/mainboard/asus/am1i-a/bootblock.c | 14 ++------------ src/mainboard/asus/am1i-a/buildOpts.c | 15 ++------------- src/mainboard/asus/am1i-a/dsdt.asl | 15 ++------------- src/mainboard/asus/am1i-a/irq_tables.c | 15 ++------------- src/mainboard/asus/am1i-a/mainboard.c | 17 ++--------------- src/mainboard/asus/am1i-a/mptable.c | 15 ++------------- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 15 ++------------- src/mainboard/asus/f2a85-m/OemCustomize.c | 15 ++------------- src/mainboard/asus/f2a85-m/OptionsIds.h | 15 ++------------- src/mainboard/asus/f2a85-m/acpi/cpstate.asl | 15 ++------------- src/mainboard/asus/f2a85-m/acpi/gpe.asl | 15 ++------------- src/mainboard/asus/f2a85-m/acpi/mainboard.asl | 15 ++------------- src/mainboard/asus/f2a85-m/acpi/routing.asl | 15 ++------------- src/mainboard/asus/f2a85-m/acpi/si.asl | 15 ++------------- src/mainboard/asus/f2a85-m/acpi/sleep.asl | 15 ++------------- src/mainboard/asus/f2a85-m/acpi/usb_oc.asl | 15 ++------------- src/mainboard/asus/f2a85-m/acpi_tables.c | 15 ++------------- src/mainboard/asus/f2a85-m/bootblock.c | 15 ++------------- src/mainboard/asus/f2a85-m/buildOpts.c | 15 ++------------- src/mainboard/asus/f2a85-m/dsdt.asl | 15 ++------------- src/mainboard/asus/f2a85-m/irq_tables.c | 15 ++------------- src/mainboard/asus/f2a85-m/mainboard.c | 15 ++------------- src/mainboard/asus/f2a85-m/mptable.c | 15 ++------------- src/mainboard/asus/f2a85-m/romstage.c | 15 ++------------- src/mainboard/asus/h61m-cs/acpi_tables.c | 16 ++-------------- src/mainboard/asus/h61m-cs/early_init.c | 16 ++-------------- src/mainboard/asus/h61m-cs/gpio.c | 16 ++-------------- src/mainboard/asus/h61m-cs/hda_verb.c | 16 ++-------------- src/mainboard/asus/h61m-cs/mainboard.c | 16 ++-------------- src/mainboard/asus/p2b-ls/acpi_tables.c | 15 ++------------- src/mainboard/asus/p2b-ls/dsdt.asl | 15 ++------------- src/mainboard/asus/p2b/acpi_tables.c | 15 ++------------- src/mainboard/asus/p2b/dsdt.asl | 15 ++------------- .../asus/p5gc-mx/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/asus/p5gc-mx/acpi/mainboard.asl | 15 ++------------- src/mainboard/asus/p5gc-mx/acpi_tables.c | 15 ++------------- src/mainboard/asus/p5gc-mx/cstates.c | 14 ++------------ src/mainboard/asus/p5gc-mx/dsdt.asl | 15 ++------------- src/mainboard/asus/p5gc-mx/early_init.c | 15 ++------------- src/mainboard/asus/p5gc-mx/gpio.c | 15 ++------------- src/mainboard/asus/p5gc-mx/hda_verb.c | 15 ++------------- src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl | 15 ++------------- src/mainboard/asus/p5qc/acpi_tables.c | 15 ++------------- src/mainboard/asus/p5qc/cstates.c | 14 ++------------ src/mainboard/asus/p5qc/dsdt.asl | 15 ++------------- src/mainboard/asus/p5qc/gpio.c | 15 ++------------- .../asus/p5qc/variants/p5ql_pro/gpio.c | 15 ++------------- .../asus/p5ql-em/acpi/ich10_pci_irqs.asl | 14 ++------------ src/mainboard/asus/p5ql-em/acpi_tables.c | 14 ++------------ src/mainboard/asus/p5ql-em/dsdt.asl | 14 ++------------ src/mainboard/asus/p5ql-em/gpio.c | 14 ++------------ .../asus/p5qpl-am/acpi/ich7_pci_irqs.asl | 15 ++------------- src/mainboard/asus/p5qpl-am/acpi/superio.asl | 14 ++------------ src/mainboard/asus/p5qpl-am/acpi_tables.c | 15 ++------------- src/mainboard/asus/p5qpl-am/cstates.c | 15 ++------------- src/mainboard/asus/p5qpl-am/dsdt.asl | 15 ++------------- .../asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c | 15 ++------------- .../asus/p5qpl-am/variants/p5qpl-am/gpio.c | 15 ++------------- .../asus/p8h61-m_pro/acpi/platform.asl | 15 ++------------- src/mainboard/asus/p8h61-m_pro/acpi_tables.c | 15 ++------------- src/mainboard/asus/p8h61-m_pro/dsdt.asl | 15 ++------------- src/mainboard/asus/p8h61-m_pro/early_init.c | 15 ++------------- src/mainboard/asus/p8h61-m_pro/gpio.c | 15 ++------------- src/mainboard/asus/p8h61-m_pro/hda_verb.c | 15 ++------------- src/mainboard/asus/p8z77-m_pro/dsdt.asl | 16 ++-------------- src/mainboard/asus/p8z77-m_pro/early_init.c | 16 ++-------------- src/mainboard/asus/p8z77-m_pro/gpio.c | 16 ++-------------- src/mainboard/asus/p8z77-m_pro/hda_verb.c | 16 ++-------------- src/mainboard/asus/p8z77-m_pro/mainboard.c | 16 ++-------------- .../asus/p8z77-v_lx2/acpi/platform.asl | 14 ++------------ src/mainboard/asus/p8z77-v_lx2/acpi_tables.c | 15 ++------------- src/mainboard/asus/p8z77-v_lx2/dsdt.asl | 15 ++------------- src/mainboard/asus/p8z77-v_lx2/early_init.c | 15 ++------------- src/mainboard/asus/p8z77-v_lx2/gpio.c | 15 ++------------- src/mainboard/asus/p8z77-v_lx2/hda_verb.c | 15 ++------------- 85 files changed, 170 insertions(+), 1108 deletions(-) diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index e081062799..8af7f4f622 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c index 7515afce42..a944f1ac6f 100644 --- a/src/mainboard/asus/am1i-a/OemCustomize.c +++ b/src/mainboard/asus/am1i-a/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/am1i-a/OptionsIds.h b/src/mainboard/asus/am1i-a/OptionsIds.h index bf0588d00f..a7e18bb651 100644 --- a/src/mainboard/asus/am1i-a/OptionsIds.h +++ b/src/mainboard/asus/am1i-a/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asus/am1i-a/acpi/mainboard.asl b/src/mainboard/asus/am1i-a/acpi/mainboard.asl index 837292b76d..e94c9f593c 100644 --- a/src/mainboard/asus/am1i-a/acpi/mainboard.asl +++ b/src/mainboard/asus/am1i-a/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/asus/am1i-a/acpi/routing.asl b/src/mainboard/asus/am1i-a/acpi/routing.asl index 3ddaebff45..da6b061041 100644 --- a/src/mainboard/asus/am1i-a/acpi/routing.asl +++ b/src/mainboard/asus/am1i-a/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/asus/am1i-a/acpi/sata.asl b/src/mainboard/asus/am1i-a/acpi/sata.asl index b25c9d84dc..a7799989af 100644 --- a/src/mainboard/asus/am1i-a/acpi/sata.asl +++ b/src/mainboard/asus/am1i-a/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Name(STTM, Buffer(20) { 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, diff --git a/src/mainboard/asus/am1i-a/acpi/si.asl b/src/mainboard/asus/am1i-a/acpi/si.asl index 0f8d8b1f7f..3a9e84f904 100644 --- a/src/mainboard/asus/am1i-a/acpi/si.asl +++ b/src/mainboard/asus/am1i-a/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { diff --git a/src/mainboard/asus/am1i-a/acpi/sleep.asl b/src/mainboard/asus/am1i-a/acpi/sleep.asl index 9f1f4c72de..118e8b6439 100644 --- a/src/mainboard/asus/am1i-a/acpi/sleep.asl +++ b/src/mainboard/asus/am1i-a/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/asus/am1i-a/acpi/superio.asl b/src/mainboard/asus/am1i-a/acpi/superio.asl index c56e337d0e..1e87feccb3 100644 --- a/src/mainboard/asus/am1i-a/acpi/superio.asl +++ b/src/mainboard/asus/am1i-a/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c index 2c7bacf0eb..e6397d3632 100644 --- a/src/mainboard/asus/am1i-a/acpi_tables.c +++ b/src/mainboard/asus/am1i-a/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/am1i-a/bootblock.c b/src/mainboard/asus/am1i-a/bootblock.c index 2a3aabd7e9..06751a0526 100644 --- a/src/mainboard/asus/am1i-a/bootblock.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index b0ef51d872..46e2a1d87a 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index 2d55f7cf58..f6d028f7c7 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c index 7ef3c8dc9d..551161ae7f 100644 --- a/src/mainboard/asus/am1i-a/irq_tables.c +++ b/src/mainboard/asus/am1i-a/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c index f060899f19..9ac621fc99 100644 --- a/src/mainboard/asus/am1i-a/mainboard.c +++ b/src/mainboard/asus/am1i-a/mainboard.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c index 9828577196..4a4c18bf71 100644 --- a/src/mainboard/asus/am1i-a/mptable.c +++ b/src/mainboard/asus/am1i-a/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 90d9eda654..0c61e0eb58 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 97ea78481e..c5b94400b4 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h index dc507e8241..4bb2cb38cb 100644 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ b/src/mainboard/asus/f2a85-m/OptionsIds.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl index 4a49f6baf2..86361521a2 100644 --- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This file defines the processor and performance state capability * for each core in the system. It is included into the DSDT for each diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl index be9f9fce2d..15da50c39f 100644 --- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl +++ b/src/mainboard/asus/f2a85-m/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_GPE) { /* Start Scope GPE */ diff --git a/src/mainboard/asus/f2a85-m/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m/acpi/mainboard.asl index 8cad2d8160..45427738f2 100644 --- a/src/mainboard/asus/f2a85-m/acpi/mainboard.asl +++ b/src/mainboard/asus/f2a85-m/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index 32cfbd3055..ef953052a4 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Routing is in System Bus scope */ Name(PR0, Package(){ diff --git a/src/mainboard/asus/f2a85-m/acpi/si.asl b/src/mainboard/asus/f2a85-m/acpi/si.asl index cc27e983e1..e46f267284 100644 --- a/src/mainboard/asus/f2a85-m/acpi/si.asl +++ b/src/mainboard/asus/f2a85-m/acpi/si.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SI) { Method(_SST, 1) { /* DBGO("\\_SI\\_SST\n") */ diff --git a/src/mainboard/asus/f2a85-m/acpi/sleep.asl b/src/mainboard/asus/f2a85-m/acpi/sleep.asl index 1ce04c2336..d3399c9b38 100644 --- a/src/mainboard/asus/f2a85-m/acpi/sleep.asl +++ b/src/mainboard/asus/f2a85-m/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name(WKST,Package(){Zero, Zero}) diff --git a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl index e1dc35d969..fb88faa56b 100644 --- a/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl +++ b/src/mainboard/asus/f2a85-m/acpi/usb_oc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* USB overcurrent mapping pins. */ Name(UOM0, 0) diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index be2669eeb8..3eb63c8920 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c index b60cc533a1..c63ab08b71 100644 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index f68aa628e0..4bbc909aab 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * @file diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index f34ccc8244..e43640918c 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ #include diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index 4022ebb513..5d3304d23e 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 32ebebef30..dc65a9451f 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index b9eba0bedb..067238a166 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 7519c2002e..9cd1376dd1 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c index 985d0866bf..9179d302db 100644 --- a/src/mainboard/asus/h61m-cs/acpi_tables.c +++ b/src/mainboard/asus/h61m-cs/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/h61m-cs/early_init.c b/src/mainboard/asus/h61m-cs/early_init.c index 54034d1f3a..1b9adb4a28 100644 --- a/src/mainboard/asus/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61m-cs/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/h61m-cs/gpio.c b/src/mainboard/asus/h61m-cs/gpio.c index e535a90c23..df786d354c 100644 --- a/src/mainboard/asus/h61m-cs/gpio.c +++ b/src/mainboard/asus/h61m-cs/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/h61m-cs/hda_verb.c b/src/mainboard/asus/h61m-cs/hda_verb.c index a92dfec6b4..ea59ca4637 100644 --- a/src/mainboard/asus/h61m-cs/hda_verb.c +++ b/src/mainboard/asus/h61m-cs/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/h61m-cs/mainboard.c b/src/mainboard/asus/h61m-cs/mainboard.c index 36a140bbb9..307966e196 100644 --- a/src/mainboard/asus/h61m-cs/mainboard.c +++ b/src/mainboard/asus/h61m-cs/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c index f1e1994802..9f18039c32 100644 --- a/src/mainboard/asus/p2b-ls/acpi_tables.c +++ b/src/mainboard/asus/p2b-ls/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index c79b78649f..b49e0a1df0 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p2b/acpi_tables.c b/src/mainboard/asus/p2b/acpi_tables.c index f1e1994802..9f18039c32 100644 --- a/src/mainboard/asus/p2b/acpi_tables.c +++ b/src/mainboard/asus/p2b/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index b52b456983..4bfcc319e8 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl index a4a7e1abeb..49cb6bbe58 100644 --- a/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl index 5187b2a973..1e31c06ec9 100644 --- a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl +++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (SLPB) { diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c index 69787a93ea..f9c941d79e 100644 --- a/src/mainboard/asus/p5gc-mx/acpi_tables.c +++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/asus/p5gc-mx/cstates.c +++ b/src/mainboard/asus/p5gc-mx/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl index 21af95c8d6..a27be09a6b 100644 --- a/src/mainboard/asus/p5gc-mx/dsdt.asl +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/asus/p5gc-mx/early_init.c b/src/mainboard/asus/p5gc-mx/early_init.c index dedbaef700..4a17c3705a 100644 --- a/src/mainboard/asus/p5gc-mx/early_init.c +++ b/src/mainboard/asus/p5gc-mx/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/p5gc-mx/gpio.c b/src/mainboard/asus/p5gc-mx/gpio.c index 07f8038abc..682ba13dd8 100644 --- a/src/mainboard/asus/p5gc-mx/gpio.c +++ b/src/mainboard/asus/p5gc-mx/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c index 7edd1710a2..897b1d5d84 100644 --- a/src/mainboard/asus/p5gc-mx/hda_verb.c +++ b/src/mainboard/asus/p5gc-mx/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl index 638a9ba127..7e964359ba 100644 --- a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl +++ b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 7e45c750c2..faa4021b72 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qc/cstates.c b/src/mainboard/asus/p5qc/cstates.c index ab75f495db..10498e1150 100644 --- a/src/mainboard/asus/p5qc/cstates.c +++ b/src/mainboard/asus/p5qc/cstates.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index 5b15298a1e..b72be15736 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/asus/p5qc/gpio.c b/src/mainboard/asus/p5qc/gpio.c index 74ac8ecad7..ef2a44f605 100644 --- a/src/mainboard/asus/p5qc/gpio.c +++ b/src/mainboard/asus/p5qc/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c b/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c index d6325ceada..9cf7af7eb2 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl index 37585da18d..3ee742e2bc 100644 --- a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl +++ b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index 07c9d6caff..a775b6df25 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl index 07f19eca23..2228a1c75e 100644 --- a/src/mainboard/asus/p5ql-em/dsdt.asl +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5ql-em/gpio.c b/src/mainboard/asus/p5ql-em/gpio.c index 7e18c3dd50..0c13d88b7e 100644 --- a/src/mainboard/asus/p5ql-em/gpio.c +++ b/src/mainboard/asus/p5ql-em/gpio.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl index 50e63a81a0..83218bd411 100644 --- a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is board specific information: diff --git a/src/mainboard/asus/p5qpl-am/acpi/superio.asl b/src/mainboard/asus/p5qpl-am/acpi/superio.asl index 2fc3d8eee8..0866176b19 100644 --- a/src/mainboard/asus/p5qpl-am/acpi/superio.asl +++ b/src/mainboard/asus/p5qpl-am/acpi/superio.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef SUPERIO_DEV #undef SUPERIO_PNP_BASE diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c index b0370c1ef4..7f47b3a7e2 100644 --- a/src/mainboard/asus/p5qpl-am/acpi_tables.c +++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qpl-am/cstates.c b/src/mainboard/asus/p5qpl-am/cstates.c index 2a6d8ad816..10498e1150 100644 --- a/src/mainboard/asus/p5qpl-am/cstates.c +++ b/src/mainboard/asus/p5qpl-am/cstates.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index 6120949269..8880ba7076 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c index 1a7739bdde..448d03d1ab 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c index b97804d984..da2de5e7db 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl b/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl index 92c98614d7..b8d04f9ac0 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl +++ b/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c index 2f1c8c0aff..3851d04b22 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index 4080e2facd..7da32d3884 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include diff --git a/src/mainboard/asus/p8h61-m_pro/early_init.c b/src/mainboard/asus/p8h61-m_pro/early_init.c index 7ba8751e8d..582366d9ca 100644 --- a/src/mainboard/asus/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/p8h61-m_pro/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/p8h61-m_pro/gpio.c b/src/mainboard/asus/p8h61-m_pro/gpio.c index ea28bdc50f..a25b8f619b 100644 --- a/src/mainboard/asus/p8h61-m_pro/gpio.c +++ b/src/mainboard/asus/p8h61-m_pro/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/p8h61-m_pro/hda_verb.c index 1a6b2499e7..02eeeafd72 100644 --- a/src/mainboard/asus/p8h61-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_pro/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 663aeb001e..0c024568f4 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 69c79e881b..687cbfd3c5 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/asus/p8z77-m_pro/gpio.c b/src/mainboard/asus/p8z77-m_pro/gpio.c index 30dfb5c37d..9ff2439470 100644 --- a/src/mainboard/asus/p8z77-m_pro/gpio.c +++ b/src/mainboard/asus/p8z77-m_pro/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c index f28a64db7a..ad7a925656 100644 --- a/src/mainboard/asus/p8z77-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8z77-m_pro/hda_verb.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8z77-m_pro/mainboard.c b/src/mainboard/asus/p8z77-m_pro/mainboard.c index 5f2c766a7d..19e14e8acd 100644 --- a/src/mainboard/asus/p8z77-m_pro/mainboard.c +++ b/src/mainboard/asus/p8z77-m_pro/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl index b967f584c4..b84cada0a4 100644 --- a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_PTS, 1) { diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c index 7f695721e0..3851d04b22 100644 --- a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c +++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl index a17d64be99..9481566ce1 100644 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c index c86dab7666..cbbf9dcc97 100644 --- a/src/mainboard/asus/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8z77-v_lx2/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/asus/p8z77-v_lx2/gpio.c b/src/mainboard/asus/p8z77-v_lx2/gpio.c index 634fb2e560..a7aa9717e2 100644 --- a/src/mainboard/asus/p8z77-v_lx2/gpio.c +++ b/src/mainboard/asus/p8z77-v_lx2/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/asus/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c index 01bea72258..645d0fa4f5 100644 --- a/src/mainboard/asus/p8z77-v_lx2/hda_verb.c +++ b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From b04c2f8ea9941a4b9a7146bb4018e2f51d62fdd5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:23:20 +0200 Subject: [PATCH 0839/1463] mainboard/scaleway: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I947c6e3b41fa176cba63064437da0c85834042b1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40098 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/scaleway/tagada/acpi/mainboard.asl | 16 ++-------------- .../scaleway/tagada/acpi/mainboard_pci_irqs.asl | 16 ++-------------- src/mainboard/scaleway/tagada/acpi/platform.asl | 16 ++-------------- src/mainboard/scaleway/tagada/acpi/thermal.asl | 16 ++-------------- src/mainboard/scaleway/tagada/acpi_tables.c | 16 ++-------------- src/mainboard/scaleway/tagada/bmcinfo.c | 16 ++-------------- src/mainboard/scaleway/tagada/bmcinfo.h | 16 ++-------------- src/mainboard/scaleway/tagada/bootblock.c | 16 ++-------------- src/mainboard/scaleway/tagada/dsdt.asl | 16 ++-------------- src/mainboard/scaleway/tagada/fadt.c | 16 ++-------------- src/mainboard/scaleway/tagada/gpio.h | 16 ++-------------- src/mainboard/scaleway/tagada/hsio.c | 15 ++------------- src/mainboard/scaleway/tagada/hsio.h | 16 ++-------------- src/mainboard/scaleway/tagada/ramstage.c | 16 ++-------------- 14 files changed, 28 insertions(+), 195 deletions(-) diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard.asl b/src/mainboard/scaleway/tagada/acpi/mainboard.asl index 8d3f505cc6..afbadd37a6 100644 --- a/src/mainboard/scaleway/tagada/acpi/mainboard.asl +++ b/src/mainboard/scaleway/tagada/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl index b7254c91ba..2ea7a949c6 100644 --- a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl +++ b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* This is board specific information: IRQ routing */ diff --git a/src/mainboard/scaleway/tagada/acpi/platform.asl b/src/mainboard/scaleway/tagada/acpi/platform.asl index a1a1d214b9..b8d04f9ac0 100644 --- a/src/mainboard/scaleway/tagada/acpi/platform.asl +++ b/src/mainboard/scaleway/tagada/acpi/platform.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/scaleway/tagada/acpi/thermal.asl b/src/mainboard/scaleway/tagada/acpi/thermal.asl index 8244266532..784abc33fa 100644 --- a/src/mainboard/scaleway/tagada/acpi/thermal.asl +++ b/src/mainboard/scaleway/tagada/acpi/thermal.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 551d51a47d..813bad943f 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index d07ed3063f..9308f7755c 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/scaleway/tagada/bmcinfo.h b/src/mainboard/scaleway/tagada/bmcinfo.h index e433d037c1..325a57760d 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.h +++ b/src/mainboard/scaleway/tagada/bmcinfo.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_BMCINFO_H #define MAINBOARD_BMCINFO_H diff --git a/src/mainboard/scaleway/tagada/bootblock.c b/src/mainboard/scaleway/tagada/bootblock.c index 301a9b260a..1823dd9c4e 100644 --- a/src/mainboard/scaleway/tagada/bootblock.c +++ b/src/mainboard/scaleway/tagada/bootblock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index 41e9b5d957..8c6c00d521 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index bb4b31eb46..8b38b3434c 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/scaleway/tagada/gpio.h b/src/mainboard/scaleway/tagada/gpio.h index 3edb1baa8d..7d8e0847f0 100644 --- a/src/mainboard/scaleway/tagada/gpio.h +++ b/src/mainboard/scaleway/tagada/gpio.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_GPIO_H #define _MAINBOARD_GPIO_H diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index 94db73d831..7de458a1d5 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index f651855cbf..d293e65da8 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MAINBOARD_HSIO_H #define _MAINBOARD_HSIO_H diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c index f064b74ad9..d0250e9fe7 100644 --- a/src/mainboard/scaleway/tagada/ramstage.c +++ b/src/mainboard/scaleway/tagada/ramstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 3fe302edfe443b2c8b43b339d94f9e60149cc249 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:22:42 +0200 Subject: [PATCH 0840/1463] mainboard/ocp: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I136e19fbba22b71676a0163a88ae341356c31271 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40088 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/acpi_tables.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index 76778a9bed..1da4f8ed82 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 236c637180c93efd15dd4c661671195849e79411 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:05 +0200 Subject: [PATCH 0841/1463] mainboard/aopen: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I9617d289ac09defc337631c4fd6adf6c8df5df66 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40064 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/acpi/p64h2.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/acpi/power.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/acpi/scsi.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/acpi/superio.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/acpi_tables.c | 15 +++------------ src/mainboard/aopen/dxplplusu/bootblock.c | 15 ++------------- src/mainboard/aopen/dxplplusu/dsdt.asl | 15 ++------------- src/mainboard/aopen/dxplplusu/fadt.c | 15 ++------------- 11 files changed, 23 insertions(+), 142 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl index c096e1ce6e..74a19e3071 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (MBRS) { diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 3f57b4d459..b8b65e4939 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index 8d65e56a0a..713a3c20b9 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl index f39e99d37d..ef07f5574e 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Interrupt routing for PCI 03:xx.x */ diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl index 646432ac6f..1b36e3b923 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/power.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/power.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Board powers on with button or PME# from on-board GbE wake-on-lan. diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl index 773b613d63..8da4145818 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W * U320 SCSI dual-channel controller diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl index fec77abc53..20180ee2c5 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/superio.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SuperIO GPIO configuration via logical device 0x0A */ diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index ffa997dd15..e76e525a4d 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -1,18 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * * Ported to Intel XE7501DEVKIT by Agami Aruma * Ported to AOpen DXPL Plus-U by Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c index 95d010318d..408efdb946 100644 --- a/src/mainboard/aopen/dxplplusu/bootblock.c +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index cfde2cb2f8..7fcdad960a 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index f9c81b1918..4f3c2be4fc 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 3e9cd53bbcd6634a360195bc30da6a9d3569c976 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Apr 2020 01:21:27 +0200 Subject: [PATCH 0842/1463] mainboard/cavium: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I268235657b52520ff76556abdf40cdcbd4d7e250 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40070 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../cavium/cn8100_sff_evb/bdk_devicetree.c | 16 ++-------------- src/mainboard/cavium/cn8100_sff_evb/bootblock.c | 15 ++------------- src/mainboard/cavium/cn8100_sff_evb/mainboard.c | 15 +++------------ src/mainboard/cavium/cn8100_sff_evb/romstage.c | 16 ++-------------- 4 files changed, 9 insertions(+), 53 deletions(-) diff --git a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c index 62ea3a6093..557d6e5256 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // This file is automatically generated. // DO NOT EDIT BY HAND. diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c index ff158aecde..52b92322be 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c index dbf71c282e..bd60e96e9c 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c +++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c index 3be4966bcb..afec39433e 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c +++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From a2ee761bfbb4daaf38a990a97f473b98ad357298 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:15 +0200 Subject: [PATCH 0843/1463] soc/nvidia: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id987662ba96ad7e78e76aa5a66a59b313e82f724 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40133 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/nvidia/tegra/apbmisc.c | 15 ++------------- src/soc/nvidia/tegra/apbmisc.h | 15 ++------------- src/soc/nvidia/tegra/displayport.h | 16 +++------------- src/soc/nvidia/tegra/gpio.c | 15 ++------------- src/soc/nvidia/tegra/gpio.h | 15 ++------------- src/soc/nvidia/tegra/i2c.c | 15 ++------------- src/soc/nvidia/tegra/i2c.h | 15 ++------------- src/soc/nvidia/tegra/pingroup.c | 15 ++------------- src/soc/nvidia/tegra/pingroup.h | 15 ++------------- src/soc/nvidia/tegra/pinmux.c | 15 ++------------- src/soc/nvidia/tegra/pinmux.h | 15 ++------------- src/soc/nvidia/tegra/software_i2c.c | 15 ++------------- src/soc/nvidia/tegra/types.h | 15 ++------------- src/soc/nvidia/tegra/usb.c | 15 ++------------- src/soc/nvidia/tegra/usb.h | 15 ++------------- src/soc/nvidia/tegra124/bootblock.c | 15 ++------------- src/soc/nvidia/tegra124/bootblock_asm.S | 13 ++----------- src/soc/nvidia/tegra124/cache.c | 15 ++------------- src/soc/nvidia/tegra124/cbmem.c | 15 ++------------- src/soc/nvidia/tegra124/chip.h | 15 ++------------- src/soc/nvidia/tegra124/clock.c | 16 +++------------- src/soc/nvidia/tegra124/display.c | 15 ++------------- src/soc/nvidia/tegra124/dma.c | 15 ++------------- src/soc/nvidia/tegra124/dp.c | 16 +++------------- src/soc/nvidia/tegra124/i2c.c | 15 ++------------- src/soc/nvidia/tegra124/include/soc/addressmap.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/cache.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/clk_rst.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/clock.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/display.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/dma.h | 15 ++------------- .../nvidia/tegra124/include/soc/early_configs.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/emc.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/flow.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/gpio.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/maincpu.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/mc.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/memlayout.ld | 15 ++------------- src/soc/nvidia/tegra124/include/soc/pingroup.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/pinmux.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/pmc.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/power.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/sdram.h | 15 ++------------- .../nvidia/tegra124/include/soc/sdram_param.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/spi.h | 15 ++------------- src/soc/nvidia/tegra124/include/soc/sysctr.h | 15 ++------------- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 15 ++------------- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld | 13 +------------ src/soc/nvidia/tegra124/monotonic_timer.c | 15 ++------------- src/soc/nvidia/tegra124/power.c | 15 ++------------- src/soc/nvidia/tegra124/sdram.c | 15 ++------------- src/soc/nvidia/tegra124/sdram_lp0.c | 15 ++------------- src/soc/nvidia/tegra124/soc.c | 15 ++------------- src/soc/nvidia/tegra124/sor.c | 16 +++------------- src/soc/nvidia/tegra124/spi.c | 15 ++------------- src/soc/nvidia/tegra124/uart.c | 15 ++------------- src/soc/nvidia/tegra124/verstage.c | 15 ++------------- src/soc/nvidia/tegra210/addressmap.c | 15 ++------------- src/soc/nvidia/tegra210/ape.c | 15 ++------------- src/soc/nvidia/tegra210/arm_tf.c | 15 ++------------- src/soc/nvidia/tegra210/bootblock.c | 15 ++------------- src/soc/nvidia/tegra210/bootblock_asm.S | 13 ++----------- src/soc/nvidia/tegra210/cbmem.c | 15 ++------------- src/soc/nvidia/tegra210/ccplex.c | 15 ++------------- src/soc/nvidia/tegra210/chip.h | 15 ++------------- src/soc/nvidia/tegra210/clock.c | 15 ++------------- src/soc/nvidia/tegra210/cpu.c | 15 ++------------- src/soc/nvidia/tegra210/dc.c | 15 ++------------- src/soc/nvidia/tegra210/dma.c | 15 ++------------- src/soc/nvidia/tegra210/dp.c | 16 +++------------- src/soc/nvidia/tegra210/dsi.c | 15 ++------------- src/soc/nvidia/tegra210/flow_ctrl.c | 15 ++------------- src/soc/nvidia/tegra210/funitcfg.c | 15 ++------------- src/soc/nvidia/tegra210/gic.c | 15 ++------------- src/soc/nvidia/tegra210/i2c.c | 15 ++------------- src/soc/nvidia/tegra210/i2c6.c | 15 ++------------- src/soc/nvidia/tegra210/include/soc/addressmap.h | 16 ++-------------- src/soc/nvidia/tegra210/include/soc/ccplex.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/clk_rst.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/clock.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/clst_clk.h | 15 ++------------- .../nvidia/tegra210/include/soc/console_uart.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/cpu.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/display.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/dma.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/emc.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/flow.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/flow_ctrl.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/funitcfg.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/gpio.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/id.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/maincpu.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/mc.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/memlayout.ld | 15 ++------------- src/soc/nvidia/tegra210/include/soc/mipi-phy.h | 15 ++------------- .../nvidia/tegra210/include/soc/mipi_display.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/mipi_dsi.h | 15 ++------------- .../nvidia/tegra210/include/soc/mmu_operations.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/mtc.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/padconfig.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/pinmux.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/pmc.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/power.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/romstage.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/sdram.h | 15 ++------------- .../nvidia/tegra210/include/soc/sdram_configs.h | 15 ++------------- .../nvidia/tegra210/include/soc/sdram_param.h | 15 ++------------- .../nvidia/tegra210/include/soc/secure_boot.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/spi.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/sysctr.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/tegra_dsi.h | 15 ++------------- src/soc/nvidia/tegra210/include/soc/verstage.h | 15 ++------------- .../jdi_25x18_display/panel-jdi-lpm102a188a.c | 15 ++------------- .../jdi_25x18_display/panel-jdi-lpm102a188a.h | 16 +++------------- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 15 ++------------- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.ld | 13 +------------ src/soc/nvidia/tegra210/mipi-phy.c | 15 ++------------- src/soc/nvidia/tegra210/mipi.c | 15 ++------------- src/soc/nvidia/tegra210/mipi_dsi.c | 15 ++------------- src/soc/nvidia/tegra210/mmu_operations.c | 15 ++------------- src/soc/nvidia/tegra210/monotonic_timer.c | 15 ++------------- src/soc/nvidia/tegra210/mtc.c | 15 ++------------- src/soc/nvidia/tegra210/padconfig.c | 15 ++------------- src/soc/nvidia/tegra210/power.c | 15 ++------------- src/soc/nvidia/tegra210/ram_code.c | 16 ++-------------- src/soc/nvidia/tegra210/ramstage.c | 15 ++------------- src/soc/nvidia/tegra210/romstage.c | 15 ++------------- src/soc/nvidia/tegra210/romstage_asm.S | 15 ++------------- src/soc/nvidia/tegra210/sdram.c | 16 ++-------------- src/soc/nvidia/tegra210/sdram_lp0.c | 15 ++------------- src/soc/nvidia/tegra210/soc.c | 15 ++------------- src/soc/nvidia/tegra210/sor.c | 16 +++------------- src/soc/nvidia/tegra210/spi.c | 15 ++------------- src/soc/nvidia/tegra210/stack.S | 15 ++------------- src/soc/nvidia/tegra210/stage_entry.S | 15 ++------------- src/soc/nvidia/tegra210/uart.c | 15 ++------------- 136 files changed, 277 insertions(+), 1765 deletions(-) diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index 4d043cb6ed..5eeb5e355c 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h index 75589a8ea2..75086eaacd 100644 --- a/src/soc/nvidia/tegra/apbmisc.h +++ b/src/soc/nvidia/tegra/apbmisc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA_APBMISC_H__ #define __SOC_NVIDIA_TEGRA_APBMISC_H__ diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h index f2479b6270..0445e995db 100644 --- a/src/soc/nvidia/tegra/displayport.h +++ b/src/soc/nvidia/tegra/displayport.h @@ -1,18 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * drivers/video/tegra/dc/dpaux_regs.h - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #ifndef __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 2297145927..0dc3ec9852 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index b748d1a9d5..dec5d70e0b 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA_GPIO_H__ #define __SOC_NVIDIA_TEGRA_GPIO_H__ diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 1feaa21f25..134bbf4a5a 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 127e8830d9..fcbe105696 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA_I2C_H__ #define __SOC_NVIDIA_TEGRA_I2C_H__ diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c index 38aad4a261..1e6a22bbe6 100644 --- a/src/soc/nvidia/tegra/pingroup.c +++ b/src/soc/nvidia/tegra/pingroup.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra/pingroup.h b/src/soc/nvidia/tegra/pingroup.h index 1d4db24b47..513a1ad196 100644 --- a/src/soc/nvidia/tegra/pingroup.h +++ b/src/soc/nvidia/tegra/pingroup.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA_PINGROUP_H__ #define __SOC_NVIDIA_TEGRA_PINGROUP_H__ diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c index 63d490c1d9..ee5d80ee57 100644 --- a/src/soc/nvidia/tegra/pinmux.c +++ b/src/soc/nvidia/tegra/pinmux.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra/pinmux.h b/src/soc/nvidia/tegra/pinmux.h index 88d36a58d7..9a4632bebc 100644 --- a/src/soc/nvidia/tegra/pinmux.h +++ b/src/soc/nvidia/tegra/pinmux.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA_PINMUX_H__ #define __SOC_NVIDIA_TEGRA_PINMUX_H__ diff --git a/src/soc/nvidia/tegra/software_i2c.c b/src/soc/nvidia/tegra/software_i2c.c index 77ba0d8480..73e08ee3cf 100644 --- a/src/soc/nvidia/tegra/software_i2c.c +++ b/src/soc/nvidia/tegra/software_i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h index 9ddab34a7b..963f9bb7f5 100644 --- a/src/soc/nvidia/tegra/types.h +++ b/src/soc/nvidia/tegra/types.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TEGRA_MISC_TYPES_H__ #define __TEGRA_MISC_TYPES_H__ diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 528210c8a4..f812398713 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra/usb.h b/src/soc/nvidia/tegra/usb.h index 1dc06daf0f..d41d17fe6a 100644 --- a/src/soc/nvidia/tegra/usb.h +++ b/src/soc/nvidia/tegra/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA_USB_H__ #define __SOC_NVIDIA_TEGRA_USB_H__ diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 80718393dd..54eca5e861 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index c177585e88..b31f896568 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -1,19 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * Early initialization code for ARM architecture. * * This file is based off of the OMAP3530/ARM Cortex start.S file from Das * U-Boot, which itself got the file from armboot. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include diff --git a/src/soc/nvidia/tegra124/cache.c b/src/soc/nvidia/tegra124/cache.c index bcec52c601..381e7763fd 100644 --- a/src/soc/nvidia/tegra124/cache.c +++ b/src/soc/nvidia/tegra124/cache.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 301245cc8c..7ef73153d1 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 5f4a63a417..849f1ebb84 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ #define __SOC_NVIDIA_TEGRA124_CHIP_H__ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index aab17051fe..cd09d7ce30 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #include #include #include diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index c19d36dc40..668bb942af 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index d053783c42..716ef6d6b5 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 708fa57ae5..e7cea03434 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -1,18 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * drivers/video/tegra/dc/dp.c - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include diff --git a/src/soc/nvidia/tegra124/i2c.c b/src/soc/nvidia/tegra124/i2c.c index dd38f8597f..570939461d 100644 --- a/src/soc/nvidia/tegra124/i2c.c +++ b/src/soc/nvidia/tegra124/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index 92195abfb8..8ea8f1bf0a 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/cache.h b/src/soc/nvidia/tegra124/include/soc/cache.h index 59daca1deb..1aa3eafbde 100644 --- a/src/soc/nvidia/tegra124/include/soc/cache.h +++ b/src/soc/nvidia/tegra124/include/soc/cache.h @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ void configure_l2_cache(void); diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index f64683c4a8..32ece18a9e 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA124_CLK_RST_H_ #define _TEGRA124_CLK_RST_H_ diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 86736c3c7f..dc1e763744 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__ #define __SOC_NVIDIA_TEGRA124_CLOCK_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h index 3c7ba8b97d..793d2736c2 100644 --- a/src/soc/nvidia/tegra124/include/soc/display.h +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/dma.h b/src/soc/nvidia/tegra124/include/soc/dma.h index a3d00bcf10..00a96ae4b1 100644 --- a/src/soc/nvidia/tegra124/include/soc/dma.h +++ b/src/soc/nvidia/tegra124/include/soc/dma.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NVIDIA_TEGRA124_DMA_H__ #define __NVIDIA_TEGRA124_DMA_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/early_configs.h b/src/soc/nvidia/tegra124/include/soc/early_configs.h index c0b421895a..25c1bb0a47 100644 --- a/src/soc/nvidia/tegra124/include/soc/early_configs.h +++ b/src/soc/nvidia/tegra124/include/soc/early_configs.h @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ void early_mainboard_init(void); diff --git a/src/soc/nvidia/tegra124/include/soc/emc.h b/src/soc/nvidia/tegra124/include/soc/emc.h index 7348d63fea..75f953e9be 100644 --- a/src/soc/nvidia/tegra124/include/soc/emc.h +++ b/src/soc/nvidia/tegra124/include/soc/emc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_EMC_H__ #define __SOC_NVIDIA_TEGRA124_EMC_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/flow.h b/src/soc/nvidia/tegra124/include/soc/flow.h index fba1b0cbb5..214bf75478 100644 --- a/src/soc/nvidia/tegra124/include/soc/flow.h +++ b/src/soc/nvidia/tegra124/include/soc/flow.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA124_FLOW_H_ #define _TEGRA124_FLOW_H_ diff --git a/src/soc/nvidia/tegra124/include/soc/gpio.h b/src/soc/nvidia/tegra124/include/soc/gpio.h index c85c26bbf6..f0796d5b92 100644 --- a/src/soc/nvidia/tegra124/include/soc/gpio.h +++ b/src/soc/nvidia/tegra124/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_GPIO_H__ #define __SOC_NVIDIA_TEGRA124_GPIO_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/maincpu.h b/src/soc/nvidia/tegra124/include/soc/maincpu.h index 6f8d3da44d..214378806b 100644 --- a/src/soc/nvidia/tegra124/include/soc/maincpu.h +++ b/src/soc/nvidia/tegra124/include/soc/maincpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_MAINCPU_H__ #define __SOC_NVIDIA_TEGRA124_MAINCPU_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/mc.h b/src/soc/nvidia/tegra124/include/soc/mc.h index ad8b565b2b..629c8f5442 100644 --- a/src/soc/nvidia/tegra124/include/soc/mc.h +++ b/src/soc/nvidia/tegra124/include/soc/mc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_MC_H__ #define __SOC_NVIDIA_TEGRA124_MC_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index adb47b1541..f67fbe40ae 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/nvidia/tegra124/include/soc/pingroup.h b/src/soc/nvidia/tegra124/include/soc/pingroup.h index 93c64c39a5..8ea1b86fee 100644 --- a/src/soc/nvidia/tegra124/include/soc/pingroup.h +++ b/src/soc/nvidia/tegra124/include/soc/pingroup.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_PINGROUP_H__ #define __SOC_NVIDIA_TEGRA124_PINGROUP_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/pinmux.h b/src/soc/nvidia/tegra124/include/soc/pinmux.h index 45e5815319..52f7dc1e8c 100644 --- a/src/soc/nvidia/tegra124/include/soc/pinmux.h +++ b/src/soc/nvidia/tegra124/include/soc/pinmux.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_PINMUX_H__ #define __SOC_NVIDIA_TEGRA124_PINMUX_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/pmc.h b/src/soc/nvidia/tegra124/include/soc/pmc.h index f4f8523907..0b6785b45a 100644 --- a/src/soc/nvidia/tegra124/include/soc/pmc.h +++ b/src/soc/nvidia/tegra124/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA124_PMC_H_ #define _TEGRA124_PMC_H_ diff --git a/src/soc/nvidia/tegra124/include/soc/power.h b/src/soc/nvidia/tegra124/include/soc/power.h index 33afbeb08f..027ef1c10e 100644 --- a/src/soc/nvidia/tegra124/include/soc/power.h +++ b/src/soc/nvidia/tegra124/include/soc/power.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_POWER_H__ #define __SOC_NVIDIA_TEGRA124_POWER_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/sdram.h b/src/soc/nvidia/tegra124/include/soc/sdram.h index 7e570804be..50bc548194 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_SDRAM_H__ #define __SOC_NVIDIA_TEGRA124_SDRAM_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 5fbedc8677..41091cfbcb 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * Defines the SDRAM parameter structure. diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h index eca2835044..25ccf4905b 100644 --- a/src/soc/nvidia/tegra124/include/soc/spi.h +++ b/src/soc/nvidia/tegra124/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NVIDIA_TEGRA124_SPI_H__ #define __NVIDIA_TEGRA124_SPI_H__ diff --git a/src/soc/nvidia/tegra124/include/soc/sysctr.h b/src/soc/nvidia/tegra124/include/soc/sysctr.h index eb620c3d0f..1b777f7bab 100644 --- a/src/soc/nvidia/tegra124/include/soc/sysctr.h +++ b/src/soc/nvidia/tegra124/include/soc/sysctr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA124_SYSCTR_H__ #define __SOC_NVIDIA_TEGRA124_SYSCTR_H__ diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 78bb767c30..4d138667c4 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Function unit addresses. */ enum { diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld index 2b6ff38444..81f3e1dffa 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld @@ -1,15 +1,4 @@ -/* - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") diff --git a/src/soc/nvidia/tegra124/monotonic_timer.c b/src/soc/nvidia/tegra124/monotonic_timer.c index 5e587478ca..6ddde1523b 100644 --- a/src/soc/nvidia/tegra124/monotonic_timer.c +++ b/src/soc/nvidia/tegra124/monotonic_timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 925f139599..6abc675aa0 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index c90528da7a..9684c3df05 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index e5e15e0ba0..68b52fd300 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index d291af8ad6..270e5e54e6 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index c95a625c69..a702eaaf4e 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -1,18 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * drivers/video/tegra/dc/sor.c - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 89ca081ad4..75cd9f772a 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -1,16 +1,5 @@ -/* - * NVIDIA Tegra SPI controller (T114 and later) - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* NVIDIA Tegra SPI controller (T114 and later) */ #include #include diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 23a8775447..7683a2b39e 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 4abc931364..dc221cf062 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index ca102d4aca..5c132631eb 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/ape.c b/src/soc/nvidia/tegra210/ape.c index 9a9c57f4a5..d6a13a9fd2 100644 --- a/src/soc/nvidia/tegra210/ape.c +++ b/src/soc/nvidia/tegra210/ape.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index 74ea323f12..1bc957b10c 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 7ce8ac7777..8eeb80d8ec 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/bootblock_asm.S b/src/soc/nvidia/tegra210/bootblock_asm.S index a99da87e8e..d913e1caf5 100644 --- a/src/soc/nvidia/tegra210/bootblock_asm.S +++ b/src/soc/nvidia/tegra210/bootblock_asm.S @@ -1,19 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * Early initialization code for ARM architecture. * * This file is based off of the OMAP3530/ARM Cortex start.S file from Das * U-Boot, which itself got the file from armboot. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 8c2bfcd1ae..bffbeedfd8 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index 0685a10c26..aa484bfcc8 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/chip.h b/src/soc/nvidia/tegra210/chip.h index d43e1badeb..d6afddeed0 100644 --- a/src/soc/nvidia/tegra210/chip.h +++ b/src/soc/nvidia/tegra210/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_CHIP_H__ #define __SOC_NVIDIA_TEGRA210_CHIP_H__ diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 2fcbb188c1..3f2505dd3f 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index 0ebb62dae8..d362ff16d3 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 3f9ba25424..dcfb52f0aa 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 6220210333..d4c464a655 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 0b6f64b454..bf7a4fa8c3 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -1,18 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * drivers/video/tegra/dc/dp.c - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 8dcfffca2e..97bf48e051 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/flow_ctrl.c b/src/soc/nvidia/tegra210/flow_ctrl.c index e4f95d5849..617479cf06 100644 --- a/src/soc/nvidia/tegra210/flow_ctrl.c +++ b/src/soc/nvidia/tegra210/flow_ctrl.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/funitcfg.c b/src/soc/nvidia/tegra210/funitcfg.c index 6f3f260d5b..1220710e9d 100644 --- a/src/soc/nvidia/tegra210/funitcfg.c +++ b/src/soc/nvidia/tegra210/funitcfg.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/gic.c b/src/soc/nvidia/tegra210/gic.c index 258735fefe..4751083f57 100644 --- a/src/soc/nvidia/tegra210/gic.c +++ b/src/soc/nvidia/tegra210/gic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/i2c.c b/src/soc/nvidia/tegra210/i2c.c index 5895a67fc4..79f8ec94fa 100644 --- a/src/soc/nvidia/tegra210/i2c.c +++ b/src/soc/nvidia/tegra210/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c index 1dfed4b380..07ea97beed 100644 --- a/src/soc/nvidia/tegra210/i2c6.c +++ b/src/soc/nvidia/tegra210/i2c6.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 1b5a78f1c4..d46556b57d 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/ccplex.h b/src/soc/nvidia/tegra210/include/soc/ccplex.h index 76c0347f47..8474d47b16 100644 --- a/src/soc/nvidia/tegra210/include/soc/ccplex.h +++ b/src/soc/nvidia/tegra210/include/soc/ccplex.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_CCPLEX_H__ #define __SOC_NVIDIA_TEGRA210_CCPLEX_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 9b85d046d6..bdce60b4f4 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA210_CLK_RST_H_ #define _TEGRA210_CLK_RST_H_ diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 27de8e6fa8..d72de3982f 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_CLOCK_H__ #define __SOC_NVIDIA_TEGRA210_CLOCK_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/clst_clk.h b/src/soc/nvidia/tegra210/include/soc/clst_clk.h index 800315c7d5..e8454b278e 100644 --- a/src/soc/nvidia/tegra210/include/soc/clst_clk.h +++ b/src/soc/nvidia/tegra210/include/soc/clst_clk.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA210_CLST_CLK_H_ #define _TEGRA210_CLST_CLK_H_ diff --git a/src/soc/nvidia/tegra210/include/soc/console_uart.h b/src/soc/nvidia/tegra210/include/soc/console_uart.h index a2f98b80a8..7ea90ab25f 100644 --- a/src/soc/nvidia/tegra210/include/soc/console_uart.h +++ b/src/soc/nvidia/tegra210/include/soc/console_uart.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__ #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/cpu.h b/src/soc/nvidia/tegra210/include/soc/cpu.h index 5ba358584f..df4fbc2faf 100644 --- a/src/soc/nvidia/tegra210/include/soc/cpu.h +++ b/src/soc/nvidia/tegra210/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_CPU_H__ #define __SOC_NVIDIA_TEGRA210_CPU_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/display.h b/src/soc/nvidia/tegra210/include/soc/display.h index 47424733ab..bed0ef84a6 100644 --- a/src/soc/nvidia/tegra210/include/soc/display.h +++ b/src/soc/nvidia/tegra210/include/soc/display.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__ #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 61048ef47b..fd70041233 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NVIDIA_TEGRA210_DMA_H__ #define __NVIDIA_TEGRA210_DMA_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h index 0a4cb740c8..5c4f6ccf5f 100644 --- a/src/soc/nvidia/tegra210/include/soc/emc.h +++ b/src/soc/nvidia/tegra210/include/soc/emc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_EMC_H__ #define __SOC_NVIDIA_TEGRA210_EMC_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/flow.h b/src/soc/nvidia/tegra210/include/soc/flow.h index 8e3ae4149b..8411af0470 100644 --- a/src/soc/nvidia/tegra210/include/soc/flow.h +++ b/src/soc/nvidia/tegra210/include/soc/flow.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA210_FLOW_H_ #define _TEGRA210_FLOW_H_ diff --git a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h index 071584720c..b810a57b85 100644 --- a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h +++ b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA210_FLOW_CTRL_H_ #define _TEGRA210_FLOW_CTRL_H_ diff --git a/src/soc/nvidia/tegra210/include/soc/funitcfg.h b/src/soc/nvidia/tegra210/include/soc/funitcfg.h index 953578a4b9..3764f7aee9 100644 --- a/src/soc/nvidia/tegra210/include/soc/funitcfg.h +++ b/src/soc/nvidia/tegra210/include/soc/funitcfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H #define __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H diff --git a/src/soc/nvidia/tegra210/include/soc/gpio.h b/src/soc/nvidia/tegra210/include/soc/gpio.h index b181de25f8..efd5e940ef 100644 --- a/src/soc/nvidia/tegra210/include/soc/gpio.h +++ b/src/soc/nvidia/tegra210/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_GPIO_H__ #define __SOC_NVIDIA_TEGRA210_GPIO_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h index 12ab2420bc..0905a336c3 100644 --- a/src/soc/nvidia/tegra210/include/soc/id.h +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/maincpu.h b/src/soc/nvidia/tegra210/include/soc/maincpu.h index 8462455686..dbdc81d97e 100644 --- a/src/soc/nvidia/tegra210/include/soc/maincpu.h +++ b/src/soc/nvidia/tegra210/include/soc/maincpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_MAINCPU_H__ #define __SOC_NVIDIA_TEGRA210_MAINCPU_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/mc.h b/src/soc/nvidia/tegra210/include/soc/mc.h index 9be2a8b4fd..99779efca2 100644 --- a/src/soc/nvidia/tegra210/include/soc/mc.h +++ b/src/soc/nvidia/tegra210/include/soc/mc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_MC_H__ #define __SOC_NVIDIA_TEGRA210_MC_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index fdd0e8811f..695f5c749d 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h index a4e093b09d..9a1cfde00c 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA_MIPI_PHY_H #define _TEGRA_MIPI_PHY_H diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_display.h b/src/soc/nvidia/tegra210/include/soc/mipi_display.h index 1f1ef53902..96a6e42bab 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi_display.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi_display.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Defines for Mobile Industry Processor Interface (MIPI(R)) * Display Working Group standards: DSI, DCS, DBI, DPI diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h index 4a6120009b..55fe5d9c40 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * MIPI DSI Bus * diff --git a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h index d9905c0dfb..b9a43878dd 100644 --- a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h +++ b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_MMU_OPERATIONS_H__ #define __SOC_NVIDIA_TEGRA210_MMU_OPERATIONS_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h index 041c7f1bfc..0192ad3619 100644 --- a/src/soc/nvidia/tegra210/include/soc/mtc.h +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_MTC_H__ #define __SOC_NVIDIA_TEGRA210_MTC_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/padconfig.h b/src/soc/nvidia/tegra210/include/soc/padconfig.h index 9fe2962583..bb5e38dfee 100644 --- a/src/soc/nvidia/tegra210/include/soc/padconfig.h +++ b/src/soc/nvidia/tegra210/include/soc/padconfig.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_PAD_CFG_H #define __SOC_NVIDIA_TEGRA210_PAD_CFG_H diff --git a/src/soc/nvidia/tegra210/include/soc/pinmux.h b/src/soc/nvidia/tegra210/include/soc/pinmux.h index d39efeff2b..3d06e24556 100644 --- a/src/soc/nvidia/tegra210/include/soc/pinmux.h +++ b/src/soc/nvidia/tegra210/include/soc/pinmux.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_PINMUX_H__ #define __SOC_NVIDIA_TEGRA210_PINMUX_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/pmc.h b/src/soc/nvidia/tegra210/include/soc/pmc.h index 07017f8945..ba4e91c235 100644 --- a/src/soc/nvidia/tegra210/include/soc/pmc.h +++ b/src/soc/nvidia/tegra210/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA210_PMC_H_ #define _TEGRA210_PMC_H_ diff --git a/src/soc/nvidia/tegra210/include/soc/power.h b/src/soc/nvidia/tegra210/include/soc/power.h index 0fe53b2d3b..171c49afc9 100644 --- a/src/soc/nvidia/tegra210/include/soc/power.h +++ b/src/soc/nvidia/tegra210/include/soc/power.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_POWER_H__ #define __SOC_NVIDIA_TEGRA210_POWER_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/romstage.h b/src/soc/nvidia/tegra210/include/soc/romstage.h index d193f9e335..b74288d4a5 100644 --- a/src/soc/nvidia/tegra210/include/soc/romstage.h +++ b/src/soc/nvidia/tegra210/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_SOC_ROMSTAGE_H__ #define __SOC_NVIDIA_TEGRA210_SOC_ROMSTAGE_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/sdram.h b/src/soc/nvidia/tegra210/include/soc/sdram.h index 4dcb55936b..8ccc9e325d 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_SDRAM_H__ #define __SOC_NVIDIA_TEGRA210_SDRAM_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_configs.h b/src/soc/nvidia/tegra210/include/soc/sdram_configs.h index f1b842b965..984f48d819 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_configs.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_configs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_SDRAM_CONFIGS_H__ #define __SOC_NVIDIA_TEGRA210_SDRAM_CONFIGS_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index b77aca1275..7ef2c838c8 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /** * Defines the SDRAM parameter structure. diff --git a/src/soc/nvidia/tegra210/include/soc/secure_boot.h b/src/soc/nvidia/tegra210/include/soc/secure_boot.h index 040d920270..7b9da1bb0a 100644 --- a/src/soc/nvidia/tegra210/include/soc/secure_boot.h +++ b/src/soc/nvidia/tegra210/include/soc/secure_boot.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TEGRA210_SECURE_BOOT_H_ #define _TEGRA210_SECURE_BOOT_H_ diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h index 26e66e06de..01d9713160 100644 --- a/src/soc/nvidia/tegra210/include/soc/spi.h +++ b/src/soc/nvidia/tegra210/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __NVIDIA_TEGRA210_SPI_H__ #define __NVIDIA_TEGRA210_SPI_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/sysctr.h b/src/soc/nvidia/tegra210/include/soc/sysctr.h index 3f869c9ebe..57018e73f5 100644 --- a/src/soc/nvidia/tegra210/include/soc/sysctr.h +++ b/src/soc/nvidia/tegra210/include/soc/sysctr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_SYSCTR_H__ #define __SOC_NVIDIA_TEGRA210_SYSCTR_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h index ae91a24cc3..db8462786b 100644 --- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TEGRA_DSI_H__ #define __TEGRA_DSI_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h index 686fe93809..9c7a087f5e 100644 --- a/src/soc/nvidia/tegra210/include/soc/verstage.h +++ b/src/soc/nvidia/tegra210/include/soc/verstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ #define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c index 931f472ac7..d4d160b899 100644 --- a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c +++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h index 9898e2d7f7..9516a45df5 100644 --- a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h +++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h @@ -1,16 +1,6 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #ifndef _PANEL_JDI_LPM102A188A_H_ #define _PANEL_JDI_LPM102A188A_H_ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index a5bc25c5b0..937eacf67f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Function unit addresses. */ enum { diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.ld b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.ld index 2b6ff38444..81f3e1dffa 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.ld +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.ld @@ -1,15 +1,4 @@ -/* - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index aa6a7285a7..4f66181342 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/mipi.c b/src/soc/nvidia/tegra210/mipi.c index 0dbbc503b7..752e0d9cb4 100644 --- a/src/soc/nvidia/tegra210/mipi.c +++ b/src/soc/nvidia/tegra210/mipi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index dacbc87ee2..27111aabc2 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * MIPI DSI Bus * diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index 65baaf9987..6b239bf2fe 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/monotonic_timer.c b/src/soc/nvidia/tegra210/monotonic_timer.c index 5e587478ca..6ddde1523b 100644 --- a/src/soc/nvidia/tegra210/monotonic_timer.c +++ b/src/soc/nvidia/tegra210/monotonic_timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c index d63b5d4bf0..5581176ae4 100644 --- a/src/soc/nvidia/tegra210/mtc.c +++ b/src/soc/nvidia/tegra210/mtc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/padconfig.c b/src/soc/nvidia/tegra210/padconfig.c index a89a240c8b..8c05fa76f5 100644 --- a/src/soc/nvidia/tegra210/padconfig.c +++ b/src/soc/nvidia/tegra210/padconfig.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/power.c b/src/soc/nvidia/tegra210/power.c index 8e7838c5a3..b5e5446c26 100644 --- a/src/soc/nvidia/tegra210/power.c +++ b/src/soc/nvidia/tegra210/power.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/ram_code.c b/src/soc/nvidia/tegra210/ram_code.c index 91cda6d2ce..9b70ef10ac 100644 --- a/src/soc/nvidia/tegra210/ram_code.c +++ b/src/soc/nvidia/tegra210/ram_code.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 41bbf7b279..6549d7824e 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index ee0d442cad..9dcc5e0802 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/romstage_asm.S b/src/soc/nvidia/tegra210/romstage_asm.S index 089a44c812..a25ac785d6 100644 --- a/src/soc/nvidia/tegra210/romstage_asm.S +++ b/src/soc/nvidia/tegra210/romstage_asm.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "stack.S" diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index 2f91321ddc..57850e18e7 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 9b882728b2..2e79607300 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 22b6dfe497..b4f51e8587 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 72da889615..72e1eb4bc8 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -1,18 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * * drivers/video/tegra/dc/sor.c - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 84f1a1de75..eae8f39cc9 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -1,16 +1,5 @@ -/* - * NVIDIA Tegra SPI controller (T114 and later) - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* NVIDIA Tegra SPI controller (T114 and later) */ #include #include diff --git a/src/soc/nvidia/tegra210/stack.S b/src/soc/nvidia/tegra210/stack.S index 7905d5fe1a..35dfbf03ce 100644 --- a/src/soc/nvidia/tegra210/stack.S +++ b/src/soc/nvidia/tegra210/stack.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Macro to initialize stack, perform seeding if required and finally call the * function provided diff --git a/src/soc/nvidia/tegra210/stage_entry.S b/src/soc/nvidia/tegra210/stage_entry.S index 1e8ce79c41..9d4e61c80a 100644 --- a/src/soc/nvidia/tegra210/stage_entry.S +++ b/src/soc/nvidia/tegra210/stage_entry.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index acdbefa6f0..97873f5dcd 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From f4a99550e456d7846daa8ace88044c907e85a05c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 20:12:40 +0200 Subject: [PATCH 0844/1463] sb/intel/lynxpoint: Use SPDX headers All the files are GPL-2.0-only. Change-Id: Ibad9b2b81337483435491f8e6b4079011f2356d8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40043 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- src/southbridge/intel/lynxpoint/Kconfig | 13 +------------ src/southbridge/intel/lynxpoint/Makefile.inc | 13 +------------ src/southbridge/intel/lynxpoint/early_pch.c | 1 - 3 files changed, 2 insertions(+), 25 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index fd557577f2..5974a5fca1 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -1,16 +1,5 @@ -## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## config SOUTHBRIDGE_INTEL_LYNXPOINT bool diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 1b6513dd47..cd4858644d 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -1,16 +1,5 @@ -## +## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 5c8324e830..1d7aeba36a 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ - #include #include #include From 5f249e60f95f8aaaff74c72c7e3a728c192e9092 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:01 +0200 Subject: [PATCH 0845/1463] soc/cavium: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3d872f63d56711d39c8320ace2642cea2a23f545 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40130 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/cavium/cn81xx/bl31_plat_params.c | 16 ++-------------- src/soc/cavium/cn81xx/bootblock.c | 15 +++------------ src/soc/cavium/cn81xx/bootblock_custom.S | 16 ++-------------- src/soc/cavium/cn81xx/cbmem.c | 15 ++------------- src/soc/cavium/cn81xx/chip.h | 15 ++------------- src/soc/cavium/cn81xx/clock.c | 15 ++------------- src/soc/cavium/cn81xx/cpu.c | 15 ++------------- src/soc/cavium/cn81xx/cpu_secondary.S | 16 ++-------------- src/soc/cavium/cn81xx/ecam0.c | 15 +++------------ src/soc/cavium/cn81xx/gpio.c | 15 ++------------- src/soc/cavium/cn81xx/include/atf/plat_params.h | 12 +----------- src/soc/cavium/cn81xx/include/soc/addressmap.h | 15 ++------------- .../cavium/cn81xx/include/soc/bl31_plat_params.h | 16 ++-------------- src/soc/cavium/cn81xx/include/soc/clock.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/cpu.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/ecam0.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/gpio.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/memlayout.ld | 15 ++------------- src/soc/cavium/cn81xx/include/soc/mmu.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/sdram.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/soc.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/spi.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/timer.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/twsi.h | 15 ++------------- src/soc/cavium/cn81xx/include/soc/uart.h | 15 ++------------- src/soc/cavium/cn81xx/mmu.c | 15 ++------------- src/soc/cavium/cn81xx/sdram.c | 15 +++------------ src/soc/cavium/cn81xx/soc.c | 15 +++------------ src/soc/cavium/cn81xx/spi.c | 15 +++------------ src/soc/cavium/cn81xx/timer.c | 15 +++------------ src/soc/cavium/cn81xx/twsi.c | 16 ++++------------ src/soc/cavium/cn81xx/uart.c | 15 +++------------ src/soc/cavium/common/bdk-coreboot.c | 15 +++------------ src/soc/cavium/common/bootblock.c | 16 ++-------------- src/soc/cavium/common/ecam.c | 15 +++------------ src/soc/cavium/common/include/soc/bootblock.h | 16 ++-------------- src/soc/cavium/common/include/soc/ecam.h | 15 ++------------- src/soc/cavium/common/include/soc/sysreg.h | 16 ++-------------- src/soc/cavium/common/pci/chip.h | 15 ++------------- src/soc/cavium/common/pci/uart.c | 16 ++-------------- 40 files changed, 90 insertions(+), 516 deletions(-) diff --git a/src/soc/cavium/cn81xx/bl31_plat_params.c b/src/soc/cavium/cn81xx/bl31_plat_params.c index b7bf02d5ee..bfb65b83e2 100644 --- a/src/soc/cavium/cn81xx/bl31_plat_params.c +++ b/src/soc/cavium/cn81xx/bl31_plat_params.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c index d65fbe520d..772c20a327 100644 --- a/src/soc/cavium/cn81xx/bootblock.c +++ b/src/soc/cavium/cn81xx/bootblock.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index 887831f6af..03d91da948 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -1,17 +1,5 @@ -/* - * Early initialization code for aarch64 (a.k.a. armv8) - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Early initialization code for aarch64 (a.k.a. armv8) */ #include #include diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 44f579182e..4760a1d3b6 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/cn81xx/chip.h b/src/soc/cavium/cn81xx/chip.h index 2facbfa4d4..d4701f63fe 100644 --- a/src/soc/cavium/cn81xx/chip.h +++ b/src/soc/cavium/cn81xx/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_CN81XX_CHIP_H #define __SOC_CAVIUM_CN81XX_CHIP_H diff --git a/src/soc/cavium/cn81xx/clock.c b/src/soc/cavium/cn81xx/clock.c index b7eb9cd748..80f74a30ed 100644 --- a/src/soc/cavium/cn81xx/clock.c +++ b/src/soc/cavium/cn81xx/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index f422e4c284..dd8e1de72d 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/cn81xx/cpu_secondary.S b/src/soc/cavium/cn81xx/cpu_secondary.S index 324b96fdc5..a8002e56f9 100644 --- a/src/soc/cavium/cn81xx/cpu_secondary.S +++ b/src/soc/cavium/cn81xx/cpu_secondary.S @@ -1,17 +1,5 @@ -/* - * Early initialization code for aarch64 (a.k.a. armv8) - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Early initialization code for aarch64 (a.k.a. armv8) */ #include #include diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 777cd10967..ef7eb35784 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/cn81xx/gpio.c b/src/soc/cavium/cn81xx/gpio.c index 356db01372..5d7dc82e06 100644 --- a/src/soc/cavium/cn81xx/gpio.c +++ b/src/soc/cavium/cn81xx/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/cn81xx/include/atf/plat_params.h b/src/soc/cavium/cn81xx/include/atf/plat_params.h index e76ae7fa6e..0efe7c7321 100644 --- a/src/soc/cavium/cn81xx/include/atf/plat_params.h +++ b/src/soc/cavium/cn81xx/include/atf/plat_params.h @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __PLAT_PARAMS_H__ #define __PLAT_PARAMS_H__ diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index 7d6d9bb49a..fe1c03444d 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ #define __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ diff --git a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h index 2fd886ffd8..77b9609746 100644 --- a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h +++ b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BL31_PLAT_PARAMS_H__ #define __BL31_PLAT_PARAMS_H__ diff --git a/src/soc/cavium/cn81xx/include/soc/clock.h b/src/soc/cavium/cn81xx/include/soc/clock.h index 3889d6f8f7..29ef7b44b2 100644 --- a/src/soc/cavium/cn81xx/include/soc/clock.h +++ b/src/soc/cavium/cn81xx/include/soc/clock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_ #define SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_ diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h index 4898e31b70..b8fdc2f2eb 100644 --- a/src/soc/cavium/cn81xx/include/soc/cpu.h +++ b/src/soc/cavium/cn81xx/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_CN81XX_CPU_H__ #define __SOC_CAVIUM_CN81XX_CPU_H__ diff --git a/src/soc/cavium/cn81xx/include/soc/ecam0.h b/src/soc/cavium/cn81xx/include/soc/ecam0.h index 2244a0a3a2..d3f4fd9d5f 100644 --- a/src/soc/cavium/cn81xx/include/soc/ecam0.h +++ b/src/soc/cavium/cn81xx/include/soc/ecam0.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM0_H #define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM0_H diff --git a/src/soc/cavium/cn81xx/include/soc/gpio.h b/src/soc/cavium/cn81xx/include/soc/gpio.h index 7d85794a1c..aba89f61b5 100644 --- a/src/soc/cavium/cn81xx/include/soc/gpio.h +++ b/src/soc/cavium/cn81xx/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_GPIO_H #define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_GPIO_H diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index f3b044235f..99a88722d7 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/cn81xx/include/soc/mmu.h b/src/soc/cavium/cn81xx/include/soc/mmu.h index d752738faa..129c0c89fc 100644 --- a/src/soc/cavium/cn81xx/include/soc/mmu.h +++ b/src/soc/cavium/cn81xx/include/soc/mmu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H diff --git a/src/soc/cavium/cn81xx/include/soc/sdram.h b/src/soc/cavium/cn81xx/include/soc/sdram.h index 199ba6a150..cb4499f9dc 100644 --- a/src/soc/cavium/cn81xx/include/soc/sdram.h +++ b/src/soc/cavium/cn81xx/include/soc/sdram.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_CN81XX_SDRAM_H__ #define __SOC_CAVIUM_CN81XX_SDRAM_H__ diff --git a/src/soc/cavium/cn81xx/include/soc/soc.h b/src/soc/cavium/cn81xx/include/soc/soc.h index 632e38e459..0edb0d89c8 100644 --- a/src/soc/cavium/cn81xx/include/soc/soc.h +++ b/src/soc/cavium/cn81xx/include/soc/soc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H diff --git a/src/soc/cavium/cn81xx/include/soc/spi.h b/src/soc/cavium/cn81xx/include/soc/spi.h index 3d874208d8..79bf527827 100644 --- a/src/soc/cavium/cn81xx/include/soc/spi.h +++ b/src/soc/cavium/cn81xx/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_CN81XX_INCLUDE_SOC_SPI_H #define __COREBOOT_SRC_SOC_CN81XX_INCLUDE_SOC_SPI_H diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 2f4f7dba1d..f73fbd9a6c 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_CN81XX_TIMER_H__ #define __SOC_CAVIUM_CN81XX_TIMER_H__ diff --git a/src/soc/cavium/cn81xx/include/soc/twsi.h b/src/soc/cavium/cn81xx/include/soc/twsi.h index 8365591e9b..5c8873aa06 100644 --- a/src/soc/cavium/cn81xx/include/soc/twsi.h +++ b/src/soc/cavium/cn81xx/include/soc/twsi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/cn81xx/include/soc/uart.h b/src/soc/cavium/cn81xx/include/soc/uart.h index 55c760d59d..fbc7457cde 100644 --- a/src/soc/cavium/cn81xx/include/soc/uart.h +++ b/src/soc/cavium/cn81xx/include/soc/uart.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H #define __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H diff --git a/src/soc/cavium/cn81xx/mmu.c b/src/soc/cavium/cn81xx/mmu.c index 7815b2522c..2a1b3d73b6 100644 --- a/src/soc/cavium/cn81xx/mmu.c +++ b/src/soc/cavium/cn81xx/mmu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c index 1d686b9dd3..1a6e759e6e 100644 --- a/src/soc/cavium/cn81xx/sdram.c +++ b/src/soc/cavium/cn81xx/sdram.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 9312593fe6..512a337d7b 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 09f27a488f..d20b90b9e2 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index 51b4f393a4..59a8ea8894 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c index a0ff3bb444..1c61428f63 100644 --- a/src/soc/cavium/cn81xx/twsi.c +++ b/src/soc/cavium/cn81xx/twsi.c @@ -1,18 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ + #include #include #include diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c index 6e88bd1748..c162956b1f 100644 --- a/src/soc/cavium/cn81xx/uart.c +++ b/src/soc/cavium/cn81xx/uart.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index e58eda3007..a2a3025688 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * This file consists of data imported from bdk-config.c */ diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index 5be06c4995..38f7ef6376 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index 0ea7c79464..daa253d438 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h index 6f966efc97..f9ccafbf33 100644 --- a/src/soc/cavium/common/include/soc/bootblock.h +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ #define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ diff --git a/src/soc/cavium/common/include/soc/ecam.h b/src/soc/cavium/common/include/soc/ecam.h index 7628cfae6f..b0f07e746c 100644 --- a/src/soc/cavium/common/include/soc/ecam.h +++ b/src/soc/cavium/common/include/soc/ecam.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H #define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H diff --git a/src/soc/cavium/common/include/soc/sysreg.h b/src/soc/cavium/common/include/soc/sysreg.h index 9bad8cbac4..fb8d2764d2 100644 --- a/src/soc/cavium/common/include/soc/sysreg.h +++ b/src/soc/cavium/common/include/soc/sysreg.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H #define __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H diff --git a/src/soc/cavium/common/pci/chip.h b/src/soc/cavium/common/pci/chip.h index d84c9277bf..1bbeba7172 100644 --- a/src/soc/cavium/common/pci/chip.h +++ b/src/soc/cavium/common/pci/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_CAVIUM_COMMON_PCI_CHIP_H #define __SOC_CAVIUM_COMMON_PCI_CHIP_H diff --git a/src/soc/cavium/common/pci/uart.c b/src/soc/cavium/common/pci/uart.c index 87928713b2..24dae39be3 100644 --- a/src/soc/cavium/common/pci/uart.c +++ b/src/soc/cavium/common/pci/uart.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 1ddb894e69d71c9d1046466cbb58b2e329f92c6d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:26 +0200 Subject: [PATCH 0846/1463] soc/samsung: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I25b9bbe320be891985e5fb42a0c3f1c763a833db Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40136 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/samsung/exynos5250/alternate_cbfs.c | 15 ++------------- src/soc/samsung/exynos5250/bootblock.c | 15 ++------------- src/soc/samsung/exynos5250/cbmem.c | 15 ++------------- src/soc/samsung/exynos5250/chip.h | 15 ++------------- src/soc/samsung/exynos5250/clock.c | 15 ++------------- src/soc/samsung/exynos5250/clock_init.c | 15 ++------------- src/soc/samsung/exynos5250/cpu.c | 15 ++------------- src/soc/samsung/exynos5250/dmc_common.c | 15 ++------------- src/soc/samsung/exynos5250/dmc_init_ddr3.c | 15 ++------------- src/soc/samsung/exynos5250/dp-reg.c | 15 ++------------- src/soc/samsung/exynos5250/fb.c | 15 ++------------- src/soc/samsung/exynos5250/gpio.c | 15 ++------------- src/soc/samsung/exynos5250/i2c.c | 16 ++-------------- .../exynos5250/include/soc/alternate_cbfs.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/clk.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/cpu.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/dmc.h | 14 ++------------ src/soc/samsung/exynos5250/include/soc/dp-core.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/dp.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/dsim.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/fimd.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/gpio.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/i2c.h | 15 ++------------- .../samsung/exynos5250/include/soc/i2s-regs.h | 15 ++------------- .../samsung/exynos5250/include/soc/memlayout.ld | 15 ++------------- src/soc/samsung/exynos5250/include/soc/periph.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/pinmux.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/power.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/setup.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/spi.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/sysreg.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/tmu.h | 15 ++------------- .../samsung/exynos5250/include/soc/trustzone.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/uart.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/usb.h | 15 ++------------- src/soc/samsung/exynos5250/include/soc/wakeup.h | 15 ++------------- src/soc/samsung/exynos5250/pinmux.c | 15 ++------------- src/soc/samsung/exynos5250/power.c | 15 ++------------- src/soc/samsung/exynos5250/spi.c | 15 ++------------- src/soc/samsung/exynos5250/timer.c | 15 ++------------- src/soc/samsung/exynos5250/tmu.c | 15 ++------------- src/soc/samsung/exynos5250/trustzone.c | 15 ++------------- src/soc/samsung/exynos5250/uart.c | 15 ++------------- src/soc/samsung/exynos5250/usb.c | 15 ++------------- src/soc/samsung/exynos5250/wakeup.c | 15 ++------------- src/soc/samsung/exynos5420/alternate_cbfs.c | 15 ++------------- src/soc/samsung/exynos5420/bootblock.c | 15 ++------------- src/soc/samsung/exynos5420/cbmem.c | 15 ++------------- src/soc/samsung/exynos5420/chip.h | 15 ++------------- src/soc/samsung/exynos5420/clock.c | 15 ++------------- src/soc/samsung/exynos5420/clock_init.c | 15 ++------------- src/soc/samsung/exynos5420/cpu.c | 15 ++------------- src/soc/samsung/exynos5420/dmc_common.c | 15 ++------------- src/soc/samsung/exynos5420/gpio.c | 15 ++------------- src/soc/samsung/exynos5420/i2c.c | 15 ++------------- .../exynos5420/include/soc/alternate_cbfs.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/clk.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/cpu.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/dmc.h | 14 ++------------ src/soc/samsung/exynos5420/include/soc/dp.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/dsim.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/fimd.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/gpio.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/i2c.h | 15 ++------------- .../samsung/exynos5420/include/soc/i2s-regs.h | 15 ++------------- .../samsung/exynos5420/include/soc/memlayout.ld | 15 ++------------- src/soc/samsung/exynos5420/include/soc/periph.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/pinmux.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/power.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/setup.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/spi.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/sysreg.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/tmu.h | 15 ++------------- .../samsung/exynos5420/include/soc/trustzone.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/uart.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/usb.h | 15 ++------------- src/soc/samsung/exynos5420/include/soc/wakeup.h | 15 ++------------- src/soc/samsung/exynos5420/pinmux.c | 15 ++------------- src/soc/samsung/exynos5420/power.c | 15 ++------------- src/soc/samsung/exynos5420/smp.c | 15 ++------------- src/soc/samsung/exynos5420/spi.c | 15 ++------------- src/soc/samsung/exynos5420/timer.c | 15 ++------------- src/soc/samsung/exynos5420/tmu.c | 15 ++------------- src/soc/samsung/exynos5420/trustzone.c | 15 ++------------- src/soc/samsung/exynos5420/uart.c | 15 ++------------- src/soc/samsung/exynos5420/usb.c | 15 ++------------- src/soc/samsung/exynos5420/wakeup.c | 15 ++------------- 87 files changed, 174 insertions(+), 1130 deletions(-) diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index 2d6b08903e..8e1271b329 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/bootblock.c b/src/soc/samsung/exynos5250/bootblock.c index d9c823b119..b4af859ccf 100644 --- a/src/soc/samsung/exynos5250/bootblock.c +++ b/src/soc/samsung/exynos5250/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 295ef01c17..b70e2a8f45 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/chip.h b/src/soc/samsung/exynos5250/chip.h index d6b0207e37..fef153fac9 100644 --- a/src/soc/samsung/exynos5250/chip.h +++ b/src/soc/samsung/exynos5250/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_H #define CPU_SAMSUNG_EXYNOS5250_H diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index 2b9cc5015c..94c8e881dd 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index c4d85abfd7..1a228170ff 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Clock setup for SMDK5250 board based on EXYNOS5 */ diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 989af5962c..8b087c9107 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/dmc_common.c b/src/soc/samsung/exynos5250/dmc_common.c index 265a7aa922..f5e1ffd8bb 100644 --- a/src/soc/samsung/exynos5250/dmc_common.c +++ b/src/soc/samsung/exynos5250/dmc_common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Mem setup common file for different types of DDR present on SMDK5250 boards. */ diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index 99a3c2c507..da3c5d36ac 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* DDR3 mem setup file for SMDK5250 board based on EXYNOS5 */ diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c index 429fb5237d..e7823c96dc 100644 --- a/src/soc/samsung/exynos5250/dp-reg.c +++ b/src/soc/samsung/exynos5250/dp-reg.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Samsung DP (Display port) register interface driver. */ diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 7c9fe30397..7b6976ee4a 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* LCD driver for Exynos */ diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c index 3a982b7e36..137c74e89b 100644 --- a/src/soc/samsung/exynos5250/gpio.c +++ b/src/soc/samsung/exynos5250/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index 55acbea00a..269761f708 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h index 46468a0be2..490aaf2dba 100644 --- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H #define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H diff --git a/src/soc/samsung/exynos5250/include/soc/clk.h b/src/soc/samsung/exynos5250/include/soc/clk.h index f02663cc14..145112305a 100644 --- a/src/soc/samsung/exynos5250/include/soc/clk.h +++ b/src/soc/samsung/exynos5250/include/soc/clk.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_CLK_H #define CPU_SAMSUNG_EXYNOS5250_CLK_H diff --git a/src/soc/samsung/exynos5250/include/soc/cpu.h b/src/soc/samsung/exynos5250/include/soc/cpu.h index d0d3612540..c7c8787359 100644 --- a/src/soc/samsung/exynos5250/include/soc/cpu.h +++ b/src/soc/samsung/exynos5250/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_CPU_H #define CPU_SAMSUNG_EXYNOS5250_CPU_H diff --git a/src/soc/samsung/exynos5250/include/soc/dmc.h b/src/soc/samsung/exynos5250/include/soc/dmc.h index 993987f4f1..2ba55aff58 100644 --- a/src/soc/samsung/exynos5250/include/soc/dmc.h +++ b/src/soc/samsung/exynos5250/include/soc/dmc.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_DMC_H #define CPU_SAMSUNG_EXYNOS5250_DMC_H diff --git a/src/soc/samsung/exynos5250/include/soc/dp-core.h b/src/soc/samsung/exynos5250/include/soc/dp-core.h index 25ae5b1672..1651246dbf 100644 --- a/src/soc/samsung/exynos5250/include/soc/dp-core.h +++ b/src/soc/samsung/exynos5250/include/soc/dp-core.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Header file for Samsung DP (Display Port) interface driver. */ diff --git a/src/soc/samsung/exynos5250/include/soc/dp.h b/src/soc/samsung/exynos5250/include/soc/dp.h index 179e2df88c..e68b2a9dc0 100644 --- a/src/soc/samsung/exynos5250/include/soc/dp.h +++ b/src/soc/samsung/exynos5250/include/soc/dp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 DP */ diff --git a/src/soc/samsung/exynos5250/include/soc/dsim.h b/src/soc/samsung/exynos5250/include/soc/dsim.h index c36965d6b4..a122a6bdc3 100644 --- a/src/soc/samsung/exynos5250/include/soc/dsim.h +++ b/src/soc/samsung/exynos5250/include/soc/dsim.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 MIPI-DSIM */ diff --git a/src/soc/samsung/exynos5250/include/soc/fimd.h b/src/soc/samsung/exynos5250/include/soc/fimd.h index b49ed6cc5f..7af4234821 100644 --- a/src/soc/samsung/exynos5250/include/soc/fimd.h +++ b/src/soc/samsung/exynos5250/include/soc/fimd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 FIMD */ diff --git a/src/soc/samsung/exynos5250/include/soc/gpio.h b/src/soc/samsung/exynos5250/include/soc/gpio.h index 533d4d3f3d..c10b3b76f1 100644 --- a/src/soc/samsung/exynos5250/include/soc/gpio.h +++ b/src/soc/samsung/exynos5250/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_GPIO_H #define CPU_SAMSUNG_EXYNOS5250_GPIO_H diff --git a/src/soc/samsung/exynos5250/include/soc/i2c.h b/src/soc/samsung/exynos5250/include/soc/i2c.h index d5b5c8ed50..e4b735a03d 100644 --- a/src/soc/samsung/exynos5250/include/soc/i2c.h +++ b/src/soc/samsung/exynos5250/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_I2C_H #define CPU_SAMSUNG_EXYNOS5250_I2C_H diff --git a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h b/src/soc/samsung/exynos5250/include/soc/i2s-regs.h index 46976fd0d2..3ac4262f6a 100644 --- a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h +++ b/src/soc/samsung/exynos5250/include/soc/i2s-regs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Taken from the kernel code */ diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index d117aac828..9e99a8c3ab 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/samsung/exynos5250/include/soc/periph.h b/src/soc/samsung/exynos5250/include/soc/periph.h index a1b7ae00ca..c2b3496f95 100644 --- a/src/soc/samsung/exynos5250/include/soc/periph.h +++ b/src/soc/samsung/exynos5250/include/soc/periph.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_PERIPH_H #define CPU_SAMSUNG_EXYNOS5250_PERIPH_H diff --git a/src/soc/samsung/exynos5250/include/soc/pinmux.h b/src/soc/samsung/exynos5250/include/soc/pinmux.h index 9f320d2de9..74bc8e7dcc 100644 --- a/src/soc/samsung/exynos5250/include/soc/pinmux.h +++ b/src/soc/samsung/exynos5250/include/soc/pinmux.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_PINMUX_H #define CPU_SAMSUNG_EXYNOS5250_PINMUX_H diff --git a/src/soc/samsung/exynos5250/include/soc/power.h b/src/soc/samsung/exynos5250/include/soc/power.h index 8c905b9ba2..c2058a3278 100644 --- a/src/soc/samsung/exynos5250/include/soc/power.h +++ b/src/soc/samsung/exynos5250/include/soc/power.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 PMU */ diff --git a/src/soc/samsung/exynos5250/include/soc/setup.h b/src/soc/samsung/exynos5250/include/soc/setup.h index 80f7c2a37e..645767a04d 100644 --- a/src/soc/samsung/exynos5250/include/soc/setup.h +++ b/src/soc/samsung/exynos5250/include/soc/setup.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Machine Specific Values for SMDK5250 board based on Exynos5 */ diff --git a/src/soc/samsung/exynos5250/include/soc/spi.h b/src/soc/samsung/exynos5250/include/soc/spi.h index 0335aa0819..4a84f21de1 100644 --- a/src/soc/samsung/exynos5250/include/soc/spi.h +++ b/src/soc/samsung/exynos5250/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_SPI_H #define CPU_SAMSUNG_EXYNOS5250_SPI_H diff --git a/src/soc/samsung/exynos5250/include/soc/sysreg.h b/src/soc/samsung/exynos5250/include/soc/sysreg.h index 7bff424d5f..8f444e053a 100644 --- a/src/soc/samsung/exynos5250/include/soc/sysreg.h +++ b/src/soc/samsung/exynos5250/include/soc/sysreg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 sysreg */ diff --git a/src/soc/samsung/exynos5250/include/soc/tmu.h b/src/soc/samsung/exynos5250/include/soc/tmu.h index 42432f2e07..c88906c408 100644 --- a/src/soc/samsung/exynos5250/include/soc/tmu.h +++ b/src/soc/samsung/exynos5250/include/soc/tmu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* EXYNOS - Thermal Management Unit */ diff --git a/src/soc/samsung/exynos5250/include/soc/trustzone.h b/src/soc/samsung/exynos5250/include/soc/trustzone.h index 64fc5a1d67..c852704b48 100644 --- a/src/soc/samsung/exynos5250/include/soc/trustzone.h +++ b/src/soc/samsung/exynos5250/include/soc/trustzone.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H #define CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H diff --git a/src/soc/samsung/exynos5250/include/soc/uart.h b/src/soc/samsung/exynos5250/include/soc/uart.h index f4e8919de3..76d65eeb17 100644 --- a/src/soc/samsung/exynos5250/include/soc/uart.h +++ b/src/soc/samsung/exynos5250/include/soc/uart.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_UART_H #define CPU_SAMSUNG_EXYNOS5250_UART_H diff --git a/src/soc/samsung/exynos5250/include/soc/usb.h b/src/soc/samsung/exynos5250/include/soc/usb.h index cad8667331..f840b0fefb 100644 --- a/src/soc/samsung/exynos5250/include/soc/usb.h +++ b/src/soc/samsung/exynos5250/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_USB_H #define CPU_SAMSUNG_EXYNOS5250_USB_H diff --git a/src/soc/samsung/exynos5250/include/soc/wakeup.h b/src/soc/samsung/exynos5250/include/soc/wakeup.h index 47dfbe573f..4d2e52f6aa 100644 --- a/src/soc/samsung/exynos5250/include/soc/wakeup.h +++ b/src/soc/samsung/exynos5250/include/soc/wakeup.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5250_WAKEUP_H #define CPU_SAMSUNG_EXYNOS5250_WAKEUP_H diff --git a/src/soc/samsung/exynos5250/pinmux.c b/src/soc/samsung/exynos5250/pinmux.c index 0d51140bb6..0b3241309c 100644 --- a/src/soc/samsung/exynos5250/pinmux.c +++ b/src/soc/samsung/exynos5250/pinmux.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index 9387f475e7..093f164ca3 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Power setup code for EXYNOS5 */ diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index d9a4988923..40a665bd20 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/timer.c b/src/soc/samsung/exynos5250/timer.c index d287bfdb73..e9daa71d50 100644 --- a/src/soc/samsung/exynos5250/timer.c +++ b/src/soc/samsung/exynos5250/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/tmu.c b/src/soc/samsung/exynos5250/tmu.c index 663f84f3fd..efbe67eaef 100644 --- a/src/soc/samsung/exynos5250/tmu.c +++ b/src/soc/samsung/exynos5250/tmu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* EXYNOS - Thermal Management Unit */ diff --git a/src/soc/samsung/exynos5250/trustzone.c b/src/soc/samsung/exynos5250/trustzone.c index 8886f5420d..a6cdde51b1 100644 --- a/src/soc/samsung/exynos5250/trustzone.c +++ b/src/soc/samsung/exynos5250/trustzone.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index f13c573a8e..abdcaf12f5 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 1303519e9b..98c8ab6c57 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5250/wakeup.c b/src/soc/samsung/exynos5250/wakeup.c index 4e6b4b8469..2aa24497f7 100644 --- a/src/soc/samsung/exynos5250/wakeup.c +++ b/src/soc/samsung/exynos5250/wakeup.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index 48beb10976..6cb67cb4de 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/bootblock.c b/src/soc/samsung/exynos5420/bootblock.c index f98a2a2d1e..a39768be7c 100644 --- a/src/soc/samsung/exynos5420/bootblock.c +++ b/src/soc/samsung/exynos5420/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 6364bd80f9..4afe0682bc 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/chip.h b/src/soc/samsung/exynos5420/chip.h index bf86839962..24f5debda7 100644 --- a/src/soc/samsung/exynos5420/chip.h +++ b/src/soc/samsung/exynos5420/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_H #define CPU_SAMSUNG_EXYNOS5420_H diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 817277aae0..cc9947c1a4 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index 3c0f6c7601..8b7e138ccd 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Clock setup for SMDK5420 board based on EXYNOS5 */ diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index cc6b0480a9..dd27730dc1 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/dmc_common.c b/src/soc/samsung/exynos5420/dmc_common.c index d756142d93..d3877296fa 100644 --- a/src/soc/samsung/exynos5420/dmc_common.c +++ b/src/soc/samsung/exynos5420/dmc_common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Mem setup common file for different types of DDR present on SMDK5420 boards. */ diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c index e36cf3acef..70073e618d 100644 --- a/src/soc/samsung/exynos5420/gpio.c +++ b/src/soc/samsung/exynos5420/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 3fd18f167a..50d9248788 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h index 874be235a0..b962f75094 100644 --- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H #define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H diff --git a/src/soc/samsung/exynos5420/include/soc/clk.h b/src/soc/samsung/exynos5420/include/soc/clk.h index 25920f3b43..d2b0a29d0c 100644 --- a/src/soc/samsung/exynos5420/include/soc/clk.h +++ b/src/soc/samsung/exynos5420/include/soc/clk.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_CLK_H #define CPU_SAMSUNG_EXYNOS5420_CLK_H diff --git a/src/soc/samsung/exynos5420/include/soc/cpu.h b/src/soc/samsung/exynos5420/include/soc/cpu.h index 956c1f0d39..0fbb7c9023 100644 --- a/src/soc/samsung/exynos5420/include/soc/cpu.h +++ b/src/soc/samsung/exynos5420/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_CPU_H #define CPU_SAMSUNG_EXYNOS5420_CPU_H diff --git a/src/soc/samsung/exynos5420/include/soc/dmc.h b/src/soc/samsung/exynos5420/include/soc/dmc.h index e068255f96..84bced64d7 100644 --- a/src/soc/samsung/exynos5420/include/soc/dmc.h +++ b/src/soc/samsung/exynos5420/include/soc/dmc.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_DMC_H #define CPU_SAMSUNG_EXYNOS5420_DMC_H diff --git a/src/soc/samsung/exynos5420/include/soc/dp.h b/src/soc/samsung/exynos5420/include/soc/dp.h index 5797f01256..41367dd27a 100644 --- a/src/soc/samsung/exynos5420/include/soc/dp.h +++ b/src/soc/samsung/exynos5420/include/soc/dp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 DP */ diff --git a/src/soc/samsung/exynos5420/include/soc/dsim.h b/src/soc/samsung/exynos5420/include/soc/dsim.h index 26d671e9d0..2c7c8560bd 100644 --- a/src/soc/samsung/exynos5420/include/soc/dsim.h +++ b/src/soc/samsung/exynos5420/include/soc/dsim.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 MIPI-DSIM */ diff --git a/src/soc/samsung/exynos5420/include/soc/fimd.h b/src/soc/samsung/exynos5420/include/soc/fimd.h index 1c274a0362..a695a5d832 100644 --- a/src/soc/samsung/exynos5420/include/soc/fimd.h +++ b/src/soc/samsung/exynos5420/include/soc/fimd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 FIMD */ diff --git a/src/soc/samsung/exynos5420/include/soc/gpio.h b/src/soc/samsung/exynos5420/include/soc/gpio.h index efe8a8afbd..ecd909b771 100644 --- a/src/soc/samsung/exynos5420/include/soc/gpio.h +++ b/src/soc/samsung/exynos5420/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_GPIO_H #define CPU_SAMSUNG_EXYNOS5420_GPIO_H diff --git a/src/soc/samsung/exynos5420/include/soc/i2c.h b/src/soc/samsung/exynos5420/include/soc/i2c.h index 7732a16161..2574c7243e 100644 --- a/src/soc/samsung/exynos5420/include/soc/i2c.h +++ b/src/soc/samsung/exynos5420/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_I2C_H #define CPU_SAMSUNG_EXYNOS5420_I2C_H diff --git a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h b/src/soc/samsung/exynos5420/include/soc/i2s-regs.h index fafd6194be..219e670457 100644 --- a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h +++ b/src/soc/samsung/exynos5420/include/soc/i2s-regs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Taken from the kernel code */ diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index c113bf962c..30440e0da0 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/samsung/exynos5420/include/soc/periph.h b/src/soc/samsung/exynos5420/include/soc/periph.h index c79ee38667..4e8c10211d 100644 --- a/src/soc/samsung/exynos5420/include/soc/periph.h +++ b/src/soc/samsung/exynos5420/include/soc/periph.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_PERIPH_H #define CPU_SAMSUNG_EXYNOS5420_PERIPH_H diff --git a/src/soc/samsung/exynos5420/include/soc/pinmux.h b/src/soc/samsung/exynos5420/include/soc/pinmux.h index 4962b454b2..1121b992e1 100644 --- a/src/soc/samsung/exynos5420/include/soc/pinmux.h +++ b/src/soc/samsung/exynos5420/include/soc/pinmux.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_PINMUX_H #define CPU_SAMSUNG_EXYNOS5420_PINMUX_H diff --git a/src/soc/samsung/exynos5420/include/soc/power.h b/src/soc/samsung/exynos5420/include/soc/power.h index 957f5a8cbd..ae8f7f2cad 100644 --- a/src/soc/samsung/exynos5420/include/soc/power.h +++ b/src/soc/samsung/exynos5420/include/soc/power.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 PMU */ diff --git a/src/soc/samsung/exynos5420/include/soc/setup.h b/src/soc/samsung/exynos5420/include/soc/setup.h index a4c9e32453..3b0bfff057 100644 --- a/src/soc/samsung/exynos5420/include/soc/setup.h +++ b/src/soc/samsung/exynos5420/include/soc/setup.h @@ -1,16 +1,5 @@ - /* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ + /* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Machine Specific Values for SMDK5420 board based on Exynos5 */ diff --git a/src/soc/samsung/exynos5420/include/soc/spi.h b/src/soc/samsung/exynos5420/include/soc/spi.h index dd26100918..a8d8899e57 100644 --- a/src/soc/samsung/exynos5420/include/soc/spi.h +++ b/src/soc/samsung/exynos5420/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_SPI_H #define CPU_SAMSUNG_EXYNOS5420_SPI_H diff --git a/src/soc/samsung/exynos5420/include/soc/sysreg.h b/src/soc/samsung/exynos5420/include/soc/sysreg.h index 423055747b..3c285d12e5 100644 --- a/src/soc/samsung/exynos5420/include/soc/sysreg.h +++ b/src/soc/samsung/exynos5420/include/soc/sysreg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Register map for Exynos5 sysreg */ diff --git a/src/soc/samsung/exynos5420/include/soc/tmu.h b/src/soc/samsung/exynos5420/include/soc/tmu.h index 0b75bb665e..cc46b2ef79 100644 --- a/src/soc/samsung/exynos5420/include/soc/tmu.h +++ b/src/soc/samsung/exynos5420/include/soc/tmu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* EXYNOS - Thermal Management Unit */ diff --git a/src/soc/samsung/exynos5420/include/soc/trustzone.h b/src/soc/samsung/exynos5420/include/soc/trustzone.h index 2020754cef..13deb51f92 100644 --- a/src/soc/samsung/exynos5420/include/soc/trustzone.h +++ b/src/soc/samsung/exynos5420/include/soc/trustzone.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H #define CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H diff --git a/src/soc/samsung/exynos5420/include/soc/uart.h b/src/soc/samsung/exynos5420/include/soc/uart.h index 3fb49f7fa4..097b40559a 100644 --- a/src/soc/samsung/exynos5420/include/soc/uart.h +++ b/src/soc/samsung/exynos5420/include/soc/uart.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_UART_H #define CPU_SAMSUNG_EXYNOS5420_UART_H diff --git a/src/soc/samsung/exynos5420/include/soc/usb.h b/src/soc/samsung/exynos5420/include/soc/usb.h index 29a5d80946..a0abe1cfa1 100644 --- a/src/soc/samsung/exynos5420/include/soc/usb.h +++ b/src/soc/samsung/exynos5420/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_USB_H #define CPU_SAMSUNG_EXYNOS5420_USB_H diff --git a/src/soc/samsung/exynos5420/include/soc/wakeup.h b/src/soc/samsung/exynos5420/include/soc/wakeup.h index 605e0f6bcf..1be91ede3f 100644 --- a/src/soc/samsung/exynos5420/include/soc/wakeup.h +++ b/src/soc/samsung/exynos5420/include/soc/wakeup.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef CPU_SAMSUNG_EXYNOS5420_WAKEUP_H #define CPU_SAMSUNG_EXYNOS5420_WAKEUP_H diff --git a/src/soc/samsung/exynos5420/pinmux.c b/src/soc/samsung/exynos5420/pinmux.c index f4958a81d5..a58303ef50 100644 --- a/src/soc/samsung/exynos5420/pinmux.c +++ b/src/soc/samsung/exynos5420/pinmux.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index d13b9fa653..442689fffa 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Power setup code for EXYNOS5 */ diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 2b7be9df50..2eef2d326a 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 7b8b955dc9..621072129b 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c index d287bfdb73..e9daa71d50 100644 --- a/src/soc/samsung/exynos5420/timer.c +++ b/src/soc/samsung/exynos5420/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/tmu.c b/src/soc/samsung/exynos5420/tmu.c index fb57ce500e..3ed6f5e2bc 100644 --- a/src/soc/samsung/exynos5420/tmu.c +++ b/src/soc/samsung/exynos5420/tmu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* EXYNOS - Thermal Management Unit */ diff --git a/src/soc/samsung/exynos5420/trustzone.c b/src/soc/samsung/exynos5420/trustzone.c index 0cf25ee4b6..f0a79eaa5a 100644 --- a/src/soc/samsung/exynos5420/trustzone.c +++ b/src/soc/samsung/exynos5420/trustzone.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index ccee71364d..d595774a88 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index b8f5ee2518..c0971f94da 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/samsung/exynos5420/wakeup.c b/src/soc/samsung/exynos5420/wakeup.c index 86615f2516..e4179f6086 100644 --- a/src/soc/samsung/exynos5420/wakeup.c +++ b/src/soc/samsung/exynos5420/wakeup.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From bbc99cfe36d1ba25f03115f390a497d3001bdef0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Apr 2020 18:51:23 +0200 Subject: [PATCH 0847/1463] soc/rockchip: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I773cc57197b29fd3f4522aece4c83b3dc9e646e0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40135 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/rockchip/common/cbmem.c | 15 ++------------- src/soc/rockchip/common/edp.c | 15 ++------------- src/soc/rockchip/common/gpio.c | 15 ++------------- src/soc/rockchip/common/i2c.c | 15 ++------------- src/soc/rockchip/common/include/soc/edp.h | 15 ++------------- src/soc/rockchip/common/include/soc/gpio.h | 15 ++------------- src/soc/rockchip/common/include/soc/i2c.h | 15 ++------------- src/soc/rockchip/common/include/soc/pwm.h | 15 ++------------- src/soc/rockchip/common/include/soc/rk808.h | 15 ++------------- src/soc/rockchip/common/include/soc/soc.h | 15 ++------------- src/soc/rockchip/common/include/soc/spi.h | 15 ++------------- src/soc/rockchip/common/include/soc/vop.h | 15 ++------------- src/soc/rockchip/common/pwm.c | 15 ++------------- src/soc/rockchip/common/rk808.c | 15 ++------------- src/soc/rockchip/common/spi.c | 15 ++------------- src/soc/rockchip/common/uart.c | 15 ++------------- src/soc/rockchip/common/vop.c | 15 ++------------- src/soc/rockchip/rk3288/bootblock.c | 15 ++------------- src/soc/rockchip/rk3288/chip.h | 15 ++------------- src/soc/rockchip/rk3288/clock.c | 15 ++------------- src/soc/rockchip/rk3288/crypto.c | 15 ++------------- src/soc/rockchip/rk3288/display.c | 15 ++------------- src/soc/rockchip/rk3288/gpio.c | 15 ++------------- src/soc/rockchip/rk3288/include/soc/addressmap.h | 15 ++------------- src/soc/rockchip/rk3288/include/soc/clock.h | 15 ++------------- src/soc/rockchip/rk3288/include/soc/display.h | 15 ++------------- src/soc/rockchip/rk3288/include/soc/grf.h | 15 ++------------- src/soc/rockchip/rk3288/include/soc/memlayout.ld | 15 ++------------- src/soc/rockchip/rk3288/include/soc/pmu.h | 15 ++------------- src/soc/rockchip/rk3288/include/soc/sdram.h | 15 ++------------- src/soc/rockchip/rk3288/include/soc/timer.h | 15 ++------------- src/soc/rockchip/rk3288/include/soc/tsadc.h | 15 ++------------- src/soc/rockchip/rk3288/sdram.c | 15 ++------------- src/soc/rockchip/rk3288/soc.c | 15 ++------------- src/soc/rockchip/rk3288/software_i2c.c | 15 ++------------- src/soc/rockchip/rk3288/timer.c | 15 ++------------- src/soc/rockchip/rk3288/tsadc.c | 15 ++------------- src/soc/rockchip/rk3399/bootblock.c | 15 ++------------- src/soc/rockchip/rk3399/chip.h | 15 ++------------- src/soc/rockchip/rk3399/clock.c | 15 ++------------- src/soc/rockchip/rk3399/decompressor.c | 16 ++-------------- src/soc/rockchip/rk3399/display.c | 15 ++------------- src/soc/rockchip/rk3399/gpio.c | 15 ++------------- src/soc/rockchip/rk3399/include/soc/addressmap.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/clock.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/display.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/grf.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 15 ++------------- src/soc/rockchip/rk3399/include/soc/mipi.h | 15 ++------------- .../rockchip/rk3399/include/soc/mmu_operations.h | 16 ++-------------- src/soc/rockchip/rk3399/include/soc/saradc.h | 16 ++-------------- src/soc/rockchip/rk3399/include/soc/sdram.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/symbols.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/timer.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/tsadc.h | 15 ++------------- src/soc/rockchip/rk3399/include/soc/usb.h | 15 ++------------- src/soc/rockchip/rk3399/mipi.c | 15 ++------------- src/soc/rockchip/rk3399/saradc.c | 16 ++-------------- src/soc/rockchip/rk3399/sdram.c | 15 ++------------- src/soc/rockchip/rk3399/soc.c | 15 ++------------- src/soc/rockchip/rk3399/spi_bitbang.c | 15 ++------------- src/soc/rockchip/rk3399/timer.c | 15 ++------------- src/soc/rockchip/rk3399/tsadc.c | 15 ++------------- src/soc/rockchip/rk3399/usb.c | 15 ++------------- 64 files changed, 128 insertions(+), 836 deletions(-) diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index c1afc6c124..0d3f100e89 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index a9661efbe0..dd6c0065d8 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index a2bc29b225..15387414b8 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index e438f87fe1..e33f576cad 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index 24eadd4498..77990673b5 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __RK_DP_H #define __RK_DP_H diff --git a/src/soc/rockchip/common/include/soc/gpio.h b/src/soc/rockchip/common/include/soc/gpio.h index b83f2d7299..d4fa2614e8 100644 --- a/src/soc/rockchip/common/include/soc/gpio.h +++ b/src/soc/rockchip/common/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_GPIO_H #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_GPIO_H diff --git a/src/soc/rockchip/common/include/soc/i2c.h b/src/soc/rockchip/common/include/soc/i2c.h index 62039d6727..8fe1e915bf 100644 --- a/src/soc/rockchip/common/include/soc/i2c.h +++ b/src/soc/rockchip/common/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H diff --git a/src/soc/rockchip/common/include/soc/pwm.h b/src/soc/rockchip/common/include/soc/pwm.h index 7f31ae4e83..83473d196f 100644 --- a/src/soc/rockchip/common/include/soc/pwm.h +++ b/src/soc/rockchip/common/include/soc/pwm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H diff --git a/src/soc/rockchip/common/include/soc/rk808.h b/src/soc/rockchip/common/include/soc/rk808.h index 8907306e4c..3aad157993 100644 --- a/src/soc/rockchip/common/include/soc/rk808.h +++ b/src/soc/rockchip/common/include/soc/rk808.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_RK808_H #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_RK808_H diff --git a/src/soc/rockchip/common/include/soc/soc.h b/src/soc/rockchip/common/include/soc/soc.h index a0e0eb2856..33ce459188 100644 --- a/src/soc/rockchip/common/include/soc/soc.h +++ b/src/soc/rockchip/common/include/soc/soc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SOC_H #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SOC_H diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index 8ab9d84d4c..a05b1a757a 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H diff --git a/src/soc/rockchip/common/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h index 2bed9307d0..6fa3325b2d 100644 --- a/src/soc/rockchip/common/include/soc/vop.h +++ b/src/soc/rockchip/common/include/soc/vop.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ROCKCHIP_LCD_H_ #define _ROCKCHIP_LCD_H_ diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index 9f1b27fdb8..69354c08db 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c index d47a4b3b49..4216e33beb 100644 --- a/src/soc/rockchip/common/rk808.c +++ b/src/soc/rockchip/common/rk808.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 15c8256786..f89f084686 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/uart.c b/src/soc/rockchip/common/uart.c index 55ebff5af3..407523443e 100644 --- a/src/soc/rockchip/common/uart.c +++ b/src/soc/rockchip/common/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 44a41593c0..4b1d1e1c57 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index a30ac2e95f..3aeb1116ed 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/chip.h b/src/soc/rockchip/rk3288/chip.h index f96963465a..a73375df3d 100644 --- a/src/soc/rockchip/rk3288/chip.h +++ b/src/soc/rockchip/rk3288/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_CHIP_H__ #define __SOC_ROCKCHIP_RK3288_CHIP_H__ diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 6f8e411b96..3706caed31 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index b24b8ff6ba..a460658599 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 9c918eb40e..0d3a90759e 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 4df0227fc0..7eb0ef054d 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/include/soc/addressmap.h b/src/soc/rockchip/rk3288/include/soc/addressmap.h index e8111abf2e..fbd687df1d 100644 --- a/src/soc/rockchip/rk3288/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3288/include/soc/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ #define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 96cf775a8d..c38d107d01 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_CLOCK_H__ #define __SOC_ROCKCHIP_RK3288_CLOCK_H__ diff --git a/src/soc/rockchip/rk3288/include/soc/display.h b/src/soc/rockchip/rk3288/include/soc/display.h index bf2a855e4a..8df0f515a0 100644 --- a/src/soc/rockchip/rk3288/include/soc/display.h +++ b/src/soc/rockchip/rk3288/include/soc/display.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_DISPLAY_H__ #define __SOC_ROCKCHIP_RK3288_DISPLAY_H__ diff --git a/src/soc/rockchip/rk3288/include/soc/grf.h b/src/soc/rockchip/rk3288/include/soc/grf.h index 4f88f0fe10..83fc9ee585 100644 --- a/src/soc/rockchip/rk3288/include/soc/grf.h +++ b/src/soc/rockchip/rk3288/include/soc/grf.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ #define __SOC_ROCKCHIP_RK3288_GRF_H__ diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index a6ab1e2f66..00966eb229 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/rockchip/rk3288/include/soc/pmu.h b/src/soc/rockchip/rk3288/include/soc/pmu.h index 7c69ddd565..e2d51b9e8c 100644 --- a/src/soc/rockchip/rk3288/include/soc/pmu.h +++ b/src/soc/rockchip/rk3288/include/soc/pmu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_PMU_H__ #define __SOC_ROCKCHIP_RK3288_PMU_H__ diff --git a/src/soc/rockchip/rk3288/include/soc/sdram.h b/src/soc/rockchip/rk3288/include/soc/sdram.h index 2450de5212..680edd1c9d 100644 --- a/src/soc/rockchip/rk3288/include/soc/sdram.h +++ b/src/soc/rockchip/rk3288/include/soc/sdram.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_SDRAM_H__ #define __SOC_ROCKCHIP_RK3288_SDRAM_H__ diff --git a/src/soc/rockchip/rk3288/include/soc/timer.h b/src/soc/rockchip/rk3288/include/soc/timer.h index 7d15faa443..cbf1b55469 100644 --- a/src/soc/rockchip/rk3288/include/soc/timer.h +++ b/src/soc/rockchip/rk3288/include/soc/timer.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__ #define __SOC_ROCKCHIP_RK3288_TIMER_H__ diff --git a/src/soc/rockchip/rk3288/include/soc/tsadc.h b/src/soc/rockchip/rk3288/include/soc/tsadc.h index 943446ad55..1327cf55dc 100644 --- a/src/soc/rockchip/rk3288/include/soc/tsadc.h +++ b/src/soc/rockchip/rk3288/include/soc/tsadc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3288_TSADC_H__ #define __SOC_ROCKCHIP_RK3288_TSADC_H__ diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 92db012458..cda8ff9e3a 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 84fa691b2b..f7f1ec9a88 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index 82ad878368..a486c705e2 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 5cd96b4832..4b676bd8ce 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 608d9ef5fe..7f7fd716a5 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index ebad1e2b85..e6601cc410 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h index 8111d564df..f83d3b88ef 100644 --- a/src/soc/rockchip/rk3399/chip.h +++ b/src/soc/rockchip/rk3399/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_CHIP_H__ #define __SOC_ROCKCHIP_RK3399_CHIP_H__ diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ee04d5637d..5f613f72f1 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/decompressor.c b/src/soc/rockchip/rk3399/decompressor.c index 463dbd497f..4058beb053 100644 --- a/src/soc/rockchip/rk3399/decompressor.c +++ b/src/soc/rockchip/rk3399/decompressor.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 42d5c2d7aa..aed1fd16d7 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 1be9ceb0b3..1993a8863d 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index df17bc09b0..37758f351c 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ #define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 55e79c741c..b3b4fe205a 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_CLOCK_H__ #define __SOC_ROCKCHIP_RK3399_CLOCK_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h index 860c33a9ab..e819ca62ad 100644 --- a/src/soc/rockchip/rk3399/include/soc/display.h +++ b/src/soc/rockchip/rk3399/include/soc/display.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_DISPLAY_H__ #define __SOC_ROCKCHIP_RK3399_DISPLAY_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index c6d686ed53..e6312bbbd3 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ #define __SOC_ROCKCHIP_RK3399_GRF_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 544d7a474d..0a787a1b12 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index dc57a5239b..325a013398 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __RK_MIPI_H #define __RK_MIPI_H diff --git a/src/soc/rockchip/rk3399/include/soc/mmu_operations.h b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h index d0fb0a30ce..1e9f578917 100644 --- a/src/soc/rockchip/rk3399/include/soc/mmu_operations.h +++ b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_MMU_H__ #define __SOC_ROCKCHIP_RK3399_MMU_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/saradc.h b/src/soc/rockchip/rk3399/include/soc/saradc.h index 58e946d61c..7d1b3e0831 100644 --- a/src/soc/rockchip/rk3399/include/soc/saradc.h +++ b/src/soc/rockchip/rk3399/include/soc/saradc.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_SARADC_H__ #define __SOC_ROCKCHIP_RK3399_SARADC_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index 4c2cccbd76..c495bad97c 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__ #define __SOC_ROCKCHIP_RK3399_SDRAM_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/symbols.h b/src/soc/rockchip/rk3399/include/soc/symbols.h index 258600aa9c..c51f02b0cd 100644 --- a/src/soc/rockchip/rk3399/include/soc/symbols.h +++ b/src/soc/rockchip/rk3399/include/soc/symbols.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_SYMBOLS_H__ #define __SOC_SYMBOLS_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/timer.h b/src/soc/rockchip/rk3399/include/soc/timer.h index 93c4c94054..d51d0dd755 100644 --- a/src/soc/rockchip/rk3399/include/soc/timer.h +++ b/src/soc/rockchip/rk3399/include/soc/timer.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_TIMER_H__ #define __SOC_ROCKCHIP_RK3399_TIMER_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/tsadc.h b/src/soc/rockchip/rk3399/include/soc/tsadc.h index 690fd275da..5be07c73a2 100644 --- a/src/soc/rockchip/rk3399/include/soc/tsadc.h +++ b/src/soc/rockchip/rk3399/include/soc/tsadc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_TSADC_H__ #define __SOC_ROCKCHIP_RK3399_TSADC_H__ diff --git a/src/soc/rockchip/rk3399/include/soc/usb.h b/src/soc/rockchip/rk3399/include/soc/usb.h index 38acad2bc8..dbb08e63b5 100644 --- a/src/soc/rockchip/rk3399/include/soc/usb.h +++ b/src/soc/rockchip/rk3399/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_ROCKCHIP_RK3399_USB_H_ #define __SOC_ROCKCHIP_RK3399_USB_H_ diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 65cf6ea93c..c6526700eb 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 5d57024ea1..3b83a82903 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 928b31e8e3..e5afa7160b 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 7c18fca1e4..783b468aff 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/spi_bitbang.c b/src/soc/rockchip/rk3399/spi_bitbang.c index 96ebb6e7a5..32bda53d3c 100644 --- a/src/soc/rockchip/rk3399/spi_bitbang.c +++ b/src/soc/rockchip/rk3399/spi_bitbang.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Compile this driver in place of common/spi.c for bitbang testing. NOTE: Also need to adjust board-specific code for GPIO pinmux! */ diff --git a/src/soc/rockchip/rk3399/timer.c b/src/soc/rockchip/rk3399/timer.c index faf8b551ae..7fe040a709 100644 --- a/src/soc/rockchip/rk3399/timer.c +++ b/src/soc/rockchip/rk3399/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index d08d0c0e91..02732bdeaf 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index 991c26eb50..e33dd7c81a 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 8a3453fc86dcec20bf6cc8a4adb8a16c41621bc3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Apr 2020 23:48:19 +0200 Subject: [PATCH 0848/1463] src/drivers: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I38eaffa391ed5971217ffad74a312b1641e431c9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40051 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/drivers/amd/agesa/acpi_tables.c | 14 ++------------ src/drivers/amd/agesa/bootblock.c | 14 ++------------ src/drivers/amd/agesa/cache_as_ram.S | 14 ++------------ src/drivers/amd/agesa/def_callouts.c | 14 ++------------ src/drivers/amd/agesa/eventlog.c | 14 ++------------ src/drivers/amd/agesa/exit_car.S | 15 ++------------- src/drivers/amd/agesa/heapmanager.c | 14 ++------------ src/drivers/amd/agesa/mtrr_fixme.c | 14 ++------------ src/drivers/amd/agesa/oem_s3.c | 14 ++------------ src/drivers/amd/agesa/romstage.c | 14 ++------------ src/drivers/amd/agesa/s3_mtrr.c | 14 ++------------ src/drivers/amd/agesa/state_machine.c | 14 ++------------ src/drivers/ams/as3722rtc.c | 14 ++------------ src/drivers/analogix/anx7625/anx7625.c | 15 ++------------- src/drivers/asmedia/aspm_blacklist.c | 14 ++------------ src/drivers/aspeed/ast2050/ast2050.c | 14 ++------------ src/drivers/aspeed/common/ast_dp501.c | 14 ++------------ src/drivers/aspeed/common/ast_dram_tables.h | 14 ++------------ src/drivers/broadcom/bcm57xx_aspm_disable.c | 14 ++------------ src/drivers/crb/chip.h | 14 ++------------ src/drivers/crb/tis.c | 14 ++------------ src/drivers/elog/boot_count.c | 14 ++------------ src/drivers/elog/elog.c | 14 ++------------ src/drivers/elog/elog_internal.h | 14 ++------------ src/drivers/elog/gsmi.c | 14 ++------------ src/drivers/emulation/qemu/bochs.c | 14 ++------------ src/drivers/emulation/qemu/qemu_debugcon.c | 14 ++------------ src/drivers/generic/adau7002/adau7002.c | 14 ++------------ src/drivers/generic/adau7002/chip.h | 14 ++------------ src/drivers/generic/bayhub/bh720.c | 14 ++------------ src/drivers/generic/bayhub/bh720.h | 14 ++------------ src/drivers/generic/bayhub/chip.h | 14 ++------------ src/drivers/generic/cbfs-serial/cbfs-serial.c | 14 ++------------ src/drivers/generic/generic/chip.h | 14 ++------------ src/drivers/generic/generic/generic.c | 14 ++------------ src/drivers/generic/gpio_keys/chip.h | 14 ++------------ src/drivers/generic/gpio_keys/gpio_keys.c | 14 ++------------ src/drivers/generic/gpio_regulator/chip.h | 14 ++------------ .../generic/gpio_regulator/gpio_regulator.c | 14 ++------------ src/drivers/generic/ioapic/chip.h | 14 ++------------ src/drivers/generic/ioapic/ioapic.c | 14 ++------------ src/drivers/generic/max98357a/chip.h | 14 ++------------ src/drivers/generic/max98357a/max98357a.c | 14 ++------------ src/drivers/gfx/generic/chip.h | 15 ++------------- src/drivers/gfx/generic/generic.c | 15 ++------------- src/drivers/gic/gic.c | 14 ++------------ src/drivers/gic/gic.h | 14 ++------------ src/drivers/i2c/at24rf08c/at24rf08c.c | 14 ++------------ src/drivers/i2c/at24rf08c/lenovo_serials.c | 14 ++------------ src/drivers/i2c/ck505/chip.h | 15 ++------------- src/drivers/i2c/ck505/ck505.c | 15 ++------------- src/drivers/i2c/da7219/chip.h | 14 ++------------ src/drivers/i2c/da7219/da7219.c | 14 ++------------ src/drivers/i2c/designware/dw_i2c.c | 14 ++------------ src/drivers/i2c/designware/dw_i2c.h | 14 ++------------ src/drivers/i2c/generic/chip.h | 14 ++------------ src/drivers/i2c/generic/generic.c | 14 ++------------ src/drivers/i2c/hid/chip.h | 14 ++------------ src/drivers/i2c/hid/hid.c | 14 ++------------ src/drivers/i2c/lm96000/chip.h | 14 ++------------ src/drivers/i2c/lm96000/lm96000.c | 14 ++------------ src/drivers/i2c/lm96000/lm96000.h | 14 ++------------ src/drivers/i2c/max98373/chip.h | 14 ++------------ src/drivers/i2c/max98373/max98373.c | 14 ++------------ src/drivers/i2c/max98927/chip.h | 14 ++------------ src/drivers/i2c/max98927/max98927.c | 14 ++------------ src/drivers/i2c/nau8825/chip.h | 14 ++------------ src/drivers/i2c/nau8825/nau8825.c | 14 ++------------ src/drivers/i2c/nct7802y/chip.h | 14 ++------------ src/drivers/i2c/nct7802y/nct7802y.c | 14 ++------------ src/drivers/i2c/nct7802y/nct7802y.h | 14 ++------------ src/drivers/i2c/nct7802y/nct7802y_fan.c | 14 ++------------ src/drivers/i2c/nct7802y/nct7802y_peci.c | 14 ++------------ src/drivers/i2c/pca9538/chip.h | 14 ++------------ src/drivers/i2c/pca9538/pca9538.c | 14 ++------------ src/drivers/i2c/pca9538/pca9538.h | 14 ++------------ src/drivers/i2c/pcf8523/chip.h | 14 ++------------ src/drivers/i2c/pcf8523/pcf8523.c | 14 ++------------ src/drivers/i2c/pcf8523/pcf8523.h | 14 ++------------ src/drivers/i2c/ptn3460/ptn3460.c | 15 ++------------- src/drivers/i2c/ptn3460/ptn3460.h | 15 ++------------- src/drivers/i2c/rt1011/chip.h | 15 ++------------- src/drivers/i2c/rt1011/rt1011.c | 15 ++------------- src/drivers/i2c/rt5663/chip.h | 14 ++------------ src/drivers/i2c/rt5663/rt5663.c | 14 ++------------ src/drivers/i2c/rtd2132/chip.h | 14 ++------------ src/drivers/i2c/rtd2132/rtd2132.c | 14 ++------------ src/drivers/i2c/rx6110sa/chip.h | 14 ++------------ src/drivers/i2c/rx6110sa/rx6110sa.c | 14 ++------------ src/drivers/i2c/rx6110sa/rx6110sa.h | 14 ++------------ src/drivers/i2c/sx9310/chip.h | 14 ++------------ src/drivers/i2c/sx9310/registers.h | 14 ++------------ src/drivers/i2c/sx9310/sx9310.c | 14 ++------------ src/drivers/i2c/tpm/chip.c | 14 ++------------ src/drivers/i2c/tpm/chip.h | 14 ++------------ src/drivers/i2c/w83793/chip.h | 14 ++------------ src/drivers/i2c/w83793/w83793.c | 14 ++------------ src/drivers/i2c/w83793/w83793.h | 14 ++------------ src/drivers/intel/fsp1_1/cache_as_ram.S | 14 ++------------ src/drivers/intel/fsp1_1/car.c | 14 ++------------ src/drivers/intel/fsp1_1/exit_car.S | 14 ++------------ src/drivers/intel/fsp1_1/fsp_gop.c | 14 ++------------ src/drivers/intel/fsp1_1/fsp_relocate.c | 14 ++------------ src/drivers/intel/fsp1_1/fsp_util.c | 14 ++------------ src/drivers/intel/fsp1_1/hob.c | 14 ++------------ src/drivers/intel/fsp1_1/include/fsp/api.h | 14 ++------------ src/drivers/intel/fsp1_1/include/fsp/car.h | 14 ++------------ src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 14 ++------------ src/drivers/intel/fsp1_1/include/fsp/romstage.h | 14 ++------------ .../intel/fsp1_1/include/fsp/soc_binding.h | 14 ++------------ src/drivers/intel/fsp1_1/include/fsp/stack.h | 14 ++------------ .../intel/fsp1_1/include/fsp/uefi_binding.h | 14 ++------------ src/drivers/intel/fsp1_1/include/fsp/util.h | 14 ++------------ src/drivers/intel/fsp1_1/logo.c | 14 ++------------ src/drivers/intel/fsp1_1/mma_core.c | 14 ++------------ src/drivers/intel/fsp1_1/raminit.c | 14 ++------------ src/drivers/intel/fsp1_1/ramstage.c | 14 ++------------ src/drivers/intel/fsp1_1/romstage.c | 14 ++------------ src/drivers/intel/fsp1_1/vbt.c | 14 ++------------ src/drivers/intel/fsp1_1/verstage.c | 14 ++------------ src/drivers/intel/fsp2_0/cbmem.c | 14 ++------------ .../intel/fsp2_0/include/fsp/memory_init.h | 14 ++------------ .../fsp2_0/include/fsp/ppi/mp_service_ppi.h | 14 ++------------ .../intel/fsp2_0/include/fsp/soc_binding.h | 14 ++------------ src/drivers/intel/fsp2_0/logo.c | 14 ++------------ src/drivers/intel/fsp2_0/mma_core.c | 14 ++------------ src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c | 14 ++------------ src/drivers/intel/gma/i915.h | 14 ++------------ src/drivers/intel/gma/int15.c | 14 ++------------ src/drivers/intel/gma/libgfxinit.h | 14 ++------------ src/drivers/intel/i210/i210.c | 14 ++------------ src/drivers/intel/i210/i210.h | 14 ++------------ src/drivers/intel/ish/chip.h | 14 ++------------ src/drivers/intel/ish/ish.c | 14 ++------------ src/drivers/intel/mipi_camera/camera.c | 14 ++------------ src/drivers/intel/mipi_camera/chip.h | 14 ++------------ src/drivers/intel/ptt/ptt.c | 14 ++------------ src/drivers/intel/ptt/ptt.h | 14 ++------------ src/drivers/intel/wifi/chip.h | 14 ++------------ src/drivers/ipmi/chip.h | 14 ++------------ src/drivers/ipmi/ipmi_fru.c | 16 ++-------------- src/drivers/ipmi/ipmi_kcs.c | 15 ++------------- src/drivers/ipmi/ipmi_kcs.h | 15 ++------------- src/drivers/ipmi/ipmi_kcs_ops.c | 15 ++------------- src/drivers/ipmi/ipmi_ops.c | 16 ++-------------- src/drivers/ipmi/ipmi_ops.h | 17 +++-------------- src/drivers/lenovo/hybrid_graphics/chip.h | 14 ++------------ .../lenovo/hybrid_graphics/hybrid_graphics.c | 14 ++------------ .../lenovo/hybrid_graphics/hybrid_graphics.h | 14 ++------------ src/drivers/lenovo/hybrid_graphics/romstage.c | 14 ++------------ src/drivers/mrc_cache/mrc_cache.c | 14 ++------------ src/drivers/net/atl1e.c | 14 ++------------ src/drivers/net/chip.h | 14 ++------------ src/drivers/net/r8168.c | 14 ++------------ src/drivers/parade/ps8625/ps8625.c | 14 ++------------ src/drivers/parade/ps8625/ps8625.h | 14 ++------------ src/drivers/parade/ps8640/ps8640.c | 14 ++------------ src/drivers/parade/ps8640/ps8640.h | 14 ++------------ src/drivers/pc80/pc/i8254.c | 14 ++------------ src/drivers/pc80/pc/i8259.c | 14 ++------------ src/drivers/pc80/pc/isa-dma.c | 14 ++------------ src/drivers/pc80/pc/keyboard.c | 14 ++------------ src/drivers/pc80/pc/ps2_controller.asl | 15 ++------------- src/drivers/pc80/rtc/mc146818rtc.c | 14 ++------------ src/drivers/pc80/rtc/mc146818rtc_boot.c | 14 ++------------ src/drivers/pc80/rtc/option.c | 14 ++------------ src/drivers/pc80/rtc/post.c | 15 ++------------- src/drivers/pc80/tpm/chip.h | 14 ++------------ src/drivers/pc80/tpm/tis.c | 14 ++------------ src/drivers/pc80/vga/vga.h | 14 ++------------ src/drivers/ricoh/rce822/chip.h | 15 ++------------- src/drivers/ricoh/rce822/rce822.c | 15 ++------------- src/drivers/secunet/dmi/smbios.c | 16 ++-------------- src/drivers/siemens/nc_fpga/nc_fpga.c | 14 ++------------ src/drivers/siemens/nc_fpga/nc_fpga.h | 14 ++------------ src/drivers/sil/3114/sil_sata.c | 14 ++------------ src/drivers/smmstore/smi.c | 14 ++------------ src/drivers/smmstore/store.c | 14 ++------------ src/drivers/spi/acpi/acpi.c | 14 ++------------ src/drivers/spi/acpi/chip.h | 14 ++------------ src/drivers/spi/bitbang.c | 14 ++------------ src/drivers/spi/boot_device_rw_nommap.c | 14 ++------------ src/drivers/spi/cbfs_spi.c | 14 ++------------ src/drivers/spi/flashconsole.c | 14 ++------------ src/drivers/spi/spi_sdcard.c | 15 ++------------- src/drivers/spi/spi_winbond.h | 14 ++------------ src/drivers/spi/spiconsole.c | 14 ++------------ src/drivers/ti/tps65913/tps65913rtc.c | 14 ++------------ src/drivers/tpm/tpm.c | 14 ++------------ src/drivers/uart/oxpcie.c | 14 ++------------ src/drivers/uart/oxpcie_early.c | 14 ++------------ src/drivers/uart/sifive.c | 14 ++------------ src/drivers/uart/uart8250io.c | 14 ++------------ src/drivers/uart/uart8250mem.c | 14 ++------------ src/drivers/uart/uart8250reg.h | 14 ++------------ src/drivers/uart/util.c | 14 ++------------ src/drivers/usb/acpi/chip.h | 14 ++------------ src/drivers/usb/acpi/usb_acpi.c | 14 ++------------ src/drivers/usb/console.c | 14 ++------------ src/drivers/usb/ehci_debug.c | 14 ++------------ src/drivers/usb/ehci_debug.h | 14 ++------------ src/drivers/usb/gadget.c | 14 ++------------ src/drivers/usb/pci_ehci.c | 14 ++------------ src/drivers/usb/usb_ch9.h | 14 ++------------ src/drivers/vpd/vpd_premem.c | 14 ++------------ src/drivers/wifi/generic_wifi.h | 14 ++------------ src/drivers/xgi/common/XGI_main.c | 14 ++------------ src/drivers/xgi/common/XGI_main.h | 14 ++------------ src/drivers/xgi/common/XGIfb.h | 14 ++------------ src/drivers/xgi/common/vb_def.h | 14 ++------------ src/drivers/xgi/common/vb_init.c | 14 ++------------ src/drivers/xgi/common/vb_init.h | 14 ++------------ src/drivers/xgi/common/vb_setmode.c | 14 ++------------ src/drivers/xgi/common/vb_setmode.h | 14 ++------------ src/drivers/xgi/common/vb_struct.h | 14 ++------------ src/drivers/xgi/common/vb_table.h | 14 ++------------ src/drivers/xgi/common/vb_util.c | 14 ++------------ src/drivers/xgi/common/vb_util.h | 14 ++------------ src/drivers/xgi/common/vgatypes.h | 14 ++------------ src/drivers/xgi/common/xgi_coreboot.c | 14 ++------------ src/drivers/xgi/z9s/z9s.c | 14 ++------------ 221 files changed, 443 insertions(+), 2678 deletions(-) diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c index cb8596fca6..70afcc618b 100644 --- a/src/drivers/amd/agesa/acpi_tables.c +++ b/src/drivers/amd/agesa/acpi_tables.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 7732f27fd5..013fbcf8da 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 1034992e17..f49623577e 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /****************************************************************************** * AMD Generic Encapsulated Software Architecture diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index bce90d90ec..9b0081f0f2 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index aa0ea9b930..5e6d3babc9 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S index 89b0609117..93170b7cb6 100644 --- a/src/drivers/amd/agesa/exit_car.S +++ b/src/drivers/amd/agesa/exit_car.S @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index 513e8049b1..85f203c506 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0440..735f257102 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 3d698ea37e..4f2cbff8d7 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index e8f4da2f28..6c90ac2a12 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index f81485d87a..025571711b 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 1678f841d0..a0d775295c 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/ams/as3722rtc.c b/src/drivers/ams/as3722rtc.c index f76360a117..aa8e79a03f 100644 --- a/src/drivers/ams/as3722rtc.c +++ b/src/drivers/ams/as3722rtc.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index e8e5bf583c..b5e9413b20 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/asmedia/aspm_blacklist.c b/src/drivers/asmedia/aspm_blacklist.c index 6f84d05f48..6ab2beeb5c 100644 --- a/src/drivers/asmedia/aspm_blacklist.c +++ b/src/drivers/asmedia/aspm_blacklist.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 4230146b0c..e8d065b466 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 2954744557..e687e5dc9f 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * File taken from the Linux ast driver (v3.18.5) diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h index 69894fcb17..6aef028a29 100644 --- a/src/drivers/aspeed/common/ast_dram_tables.h +++ b/src/drivers/aspeed/common/ast_dram_tables.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * File taken from the Linux ast driver (v3.18.5) diff --git a/src/drivers/broadcom/bcm57xx_aspm_disable.c b/src/drivers/broadcom/bcm57xx_aspm_disable.c index 427ba623a2..467ed0d980 100644 --- a/src/drivers/broadcom/bcm57xx_aspm_disable.c +++ b/src/drivers/broadcom/bcm57xx_aspm_disable.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/crb/chip.h b/src/drivers/crb/chip.h index 2e34cea88f..9d31d30ff7 100644 --- a/src/drivers/crb/chip.h +++ b/src/drivers/crb/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_CRB_CHIP_H #define DRIVERS_CRB_CHIP_H diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 32d1550e5b..5c1a6df1cf 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index a6efb01465..2afb016875 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 5f11c0c63e..c353d59e9f 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(HAVE_ACPI_RESUME) #include diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h index d16d9a3af2..3c58ee227e 100644 --- a/src/drivers/elog/elog_internal.h +++ b/src/drivers/elog/elog_internal.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ELOG_INTERNAL_H_ #define ELOG_INTERNAL_H_ diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index 0c0a214def..29ce2c335d 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 8d08ac1b4c..b20e5cdec5 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/emulation/qemu/qemu_debugcon.c b/src/drivers/emulation/qemu/qemu_debugcon.c index 00c3aade3a..7bc01afef3 100644 --- a/src/drivers/emulation/qemu/qemu_debugcon.c +++ b/src/drivers/emulation/qemu/qemu_debugcon.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 0a3d62357b..d026ffd344 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/generic/adau7002/chip.h b/src/drivers/generic/adau7002/chip.h index 1b758a242b..a49fe28469 100644 --- a/src/drivers/generic/adau7002/chip.h +++ b/src/drivers/generic/adau7002/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __I2C_GENERIC_ADAU7002_CHIP_H__ #define __I2C_GENERIC_ADAU7002_CHIP_H__ diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index a1c555aacd..43a169b542 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */ diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index 4ee7b6a7f8..c31ee4d0eb 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */ diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h index 820ed1c9ec..3a7b21d3e9 100644 --- a/src/drivers/generic/bayhub/chip.h +++ b/src/drivers/generic/bayhub/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c index ee3e36620c..76bc1cf883 100644 --- a/src/drivers/generic/cbfs-serial/cbfs-serial.c +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/generic/generic/chip.h b/src/drivers/generic/generic/chip.h index 9a59486a71..41b5f461db 100644 --- a/src/drivers/generic/generic/chip.h +++ b/src/drivers/generic/generic/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __GENERIC_GENERIC_CHIP_H__ #define __GENERIC_GENERIC_CHIP_H__ diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index 0ba2d53c82..5666ee4157 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 31ba701518..9836abac60 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DRIVERS_GENERIC_GPIO_KEYS_H__ #define __DRIVERS_GENERIC_GPIO_KEYS_H__ diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 67c591386d..e2310a1c31 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/generic/gpio_regulator/chip.h b/src/drivers/generic/gpio_regulator/chip.h index b5535d22ef..8ae02ae3c2 100644 --- a/src/drivers/generic/gpio_regulator/chip.h +++ b/src/drivers/generic/gpio_regulator/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DRIVERS_GENERIC_GPIO_REGULATOR_H__ #define __DRIVERS_GENERIC_GPIO_REGULATOR_H__ diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index b4761262e0..253a2fa633 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h index b8a20d1898..8c1a51a210 100644 --- a/src/drivers/generic/ioapic/chip.h +++ b/src/drivers/generic/ioapic/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_GENERIC_IOAPIC_CHIP_H #define DRIVERS_GENERIC_IOAPIC_CHIP_H diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index b16f8c6c26..b09e8a6c04 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h index f956846b60..95a58f09d6 100644 --- a/src/drivers/generic/max98357a/chip.h +++ b/src/drivers/generic/max98357a/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 6f724f8937..d1c4978398 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index 258cda9c5c..8e70bc6978 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DRIVERS_GFX_GENERIC_CHIP_H__ #define __DRIVERS_GFX_GENERIC_CHIP_H__ diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index a20279f7af..aa8d7566f6 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/gic/gic.c b/src/drivers/gic/gic.c index 9704b5ec03..ce62f3da4a 100644 --- a/src/drivers/gic/gic.c +++ b/src/drivers/gic/gic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/gic/gic.h b/src/drivers/gic/gic.h index e5b4b11d2e..8c21d24448 100644 --- a/src/drivers/gic/gic.h +++ b/src/drivers/gic/gic.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_GIC_H #define DRIVERS_GIC_H diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 11a6fd2b3d..32f702c497 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index aacdb724c6..2fd5660ef9 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/ck505/chip.h b/src/drivers/i2c/ck505/chip.h index a66a103246..ad9f0f1f00 100644 --- a/src/drivers/i2c/ck505/chip.h +++ b/src/drivers/i2c/ck505/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_CK505_CHIP_H #define DRIVERS_CK505_CHIP_H diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index 4baa1bc94a..23fba474f1 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/da7219/chip.h b/src/drivers/i2c/da7219/chip.h index 89ee21e217..32d04dada1 100644 --- a/src/drivers/i2c/da7219/chip.h +++ b/src/drivers/i2c/da7219/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 5c67eda2d0..eea82ba148 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 5e57e5a5a6..309dfeee0a 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index a4087ef9c7..220d2afc74 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DRIVERS_I2C_DESIGNWARE_I2C_H__ #define __DRIVERS_I2C_DESIGNWARE_I2C_H__ diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index ffaf7e14e5..ae7c0b42ae 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __I2C_GENERIC_CHIP_H__ #define __I2C_GENERIC_CHIP_H__ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 592e791ba9..3e9da75395 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/hid/chip.h b/src/drivers/i2c/hid/chip.h index 06888b63e5..d6180db31e 100644 --- a/src/drivers/i2c/hid/chip.h +++ b/src/drivers/i2c/hid/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DRIVERS_I2C_HID_CHIP_H__ #define __DRIVERS_I2C_HID_CHIP_H__ diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 6e4169ebb9..8a3acf948a 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h index 30cd4e01f8..f15bca398d 100644 --- a/src/drivers/i2c/lm96000/chip.h +++ b/src/drivers/i2c/lm96000/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_I2C_LM96000_CHIP_H #define DRIVERS_I2C_LM96000_CHIP_H diff --git a/src/drivers/i2c/lm96000/lm96000.c b/src/drivers/i2c/lm96000/lm96000.c index 5130630fd1..dcb5b41f9c 100644 --- a/src/drivers/i2c/lm96000/lm96000.c +++ b/src/drivers/i2c/lm96000/lm96000.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/lm96000/lm96000.h b/src/drivers/i2c/lm96000/lm96000.h index a24d8fe68e..9bfb16910b 100644 --- a/src/drivers/i2c/lm96000/lm96000.h +++ b/src/drivers/i2c/lm96000/lm96000.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_I2C_LM96000_H #define DRIVERS_I2C_LM96000_H diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h index 3642ebd349..19337a213d 100644 --- a/src/drivers/i2c/max98373/chip.h +++ b/src/drivers/i2c/max98373/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Maxim MAX98373 audio codec devicetree bindings diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 71ba75b9fe..257156b0f4 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h index 25c0dd7e35..4c90a2f105 100644 --- a/src/drivers/i2c/max98927/chip.h +++ b/src/drivers/i2c/max98927/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Maxim MAX98927 audio codec devicetree bindings diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index 7979fe32a0..f84e8d5197 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/nau8825/chip.h b/src/drivers/i2c/nau8825/chip.h index 9fc8e96ac4..80d950ff71 100644 --- a/src/drivers/i2c/nau8825/chip.h +++ b/src/drivers/i2c/nau8825/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 5d56b243e1..5f5b4d526a 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index adff0f512c..8bd28094b8 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_I2C_NCT7802Y_CHIP_H #define DRIVERS_I2C_NCT7802Y_CHIP_H diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c index d2cce64fc2..da148092d4 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.c +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/nct7802y/nct7802y.h b/src/drivers/i2c/nct7802y/nct7802y.h index 9f3aaef1d0..b7bf458ab7 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.h +++ b/src/drivers/i2c/nct7802y/nct7802y.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_I2C_NCT7802Y_H #define DRIVERS_I2C_NCT7802Y_H diff --git a/src/drivers/i2c/nct7802y/nct7802y_fan.c b/src/drivers/i2c/nct7802y/nct7802y_fan.c index d7cfb908cd..d7872dc6fd 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_fan.c +++ b/src/drivers/i2c/nct7802y/nct7802y_fan.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/nct7802y/nct7802y_peci.c b/src/drivers/i2c/nct7802y/nct7802y_peci.c index 58d7064635..b03fc5c2cb 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_peci.c +++ b/src/drivers/i2c/nct7802y/nct7802y_peci.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/pca9538/chip.h b/src/drivers/i2c/pca9538/chip.h index 40072e1279..598ffb9913 100644 --- a/src/drivers/i2c/pca9538/chip.h +++ b/src/drivers/i2c/pca9538/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ struct drivers_i2c_pca9538_config { diff --git a/src/drivers/i2c/pca9538/pca9538.c b/src/drivers/i2c/pca9538/pca9538.c index d5cd96d9e8..50f634e055 100644 --- a/src/drivers/i2c/pca9538/pca9538.c +++ b/src/drivers/i2c/pca9538/pca9538.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/pca9538/pca9538.h b/src/drivers/i2c/pca9538/pca9538.h index 9519c9a472..4640ab545f 100644 --- a/src/drivers/i2c/pca9538/pca9538.h +++ b/src/drivers/i2c/pca9538/pca9538.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _I2C_PCA9538_H_ #define _I2C_PCA9538_H_ diff --git a/src/drivers/i2c/pcf8523/chip.h b/src/drivers/i2c/pcf8523/chip.h index d40ccd7d06..251e852292 100644 --- a/src/drivers/i2c/pcf8523/chip.h +++ b/src/drivers/i2c/pcf8523/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "pcf8523.h" diff --git a/src/drivers/i2c/pcf8523/pcf8523.c b/src/drivers/i2c/pcf8523/pcf8523.c index 5666042f12..3e6af7541c 100644 --- a/src/drivers/i2c/pcf8523/pcf8523.c +++ b/src/drivers/i2c/pcf8523/pcf8523.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/pcf8523/pcf8523.h b/src/drivers/i2c/pcf8523/pcf8523.h index 02659e2cf6..05f1e6faaa 100644 --- a/src/drivers/i2c/pcf8523/pcf8523.h +++ b/src/drivers/i2c/pcf8523/pcf8523.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _I2C_PCF8523_H_ #define _I2C_PCF8523_H_ diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 2345136108..c4b8f12857 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/drivers/i2c/ptn3460/ptn3460.h b/src/drivers/i2c/ptn3460/ptn3460.h index d91386035d..eaff394708 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.h +++ b/src/drivers/i2c/ptn3460/ptn3460.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _I2C_PTN3460_H_ #define _I2C_PTN3460_H_ diff --git a/src/drivers/i2c/rt1011/chip.h b/src/drivers/i2c/rt1011/chip.h index fa759edc43..edcac72b8a 100644 --- a/src/drivers/i2c/rt1011/chip.h +++ b/src/drivers/i2c/rt1011/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Realtek RT1011 audio codec devicetree bindings diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index cfaeae8517..dc8410fda9 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index 235c253d07..6f7fbd87bb 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Realtek RT5663 audio codec devicetree bindings diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 15014cda9e..f6d023d522 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/rtd2132/chip.h b/src/drivers/i2c/rtd2132/chip.h index a0bb3e6b1b..2387b0c46f 100644 --- a/src/drivers/i2c/rtd2132/chip.h +++ b/src/drivers/i2c/rtd2132/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ struct drivers_i2c_rtd2132_config { /* Panel Power Sequencing. All units in ms. */ diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 22eeaa83be..2cefe6b7da 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index f81f4f4d16..fad18eba13 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "rx6110sa.h" diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 37f306b472..e9abe6266f 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index eb6ca6dfb3..a7d561e57c 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _I2C_RX6110SA_H_ #define _I2C_RX6110SA_H_ diff --git a/src/drivers/i2c/sx9310/chip.h b/src/drivers/i2c/sx9310/chip.h index b1d5a6ebe8..b3820c80fc 100644 --- a/src/drivers/i2c/sx9310/chip.h +++ b/src/drivers/i2c/sx9310/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DRIVERS_I2C_SX9310_CHIP_H__ #define __DRIVERS_I2C_SX9310_CHIP_H__ diff --git a/src/drivers/i2c/sx9310/registers.h b/src/drivers/i2c/sx9310/registers.h index 2c61adbe2e..859a816807 100644 --- a/src/drivers/i2c/sx9310/registers.h +++ b/src/drivers/i2c/sx9310/registers.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef REGISTER #error "define REGISTER(NAME) before including this file" diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 781d09d94d..5524395010 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index d36e4c2932..2373069437 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/tpm/chip.h b/src/drivers/i2c/tpm/chip.h index ebe94e557b..491d0223f8 100644 --- a/src/drivers/i2c/tpm/chip.h +++ b/src/drivers/i2c/tpm/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/w83793/chip.h b/src/drivers/i2c/w83793/chip.h index 9326ed2951..cda659e9fe 100644 --- a/src/drivers/i2c/w83793/chip.h +++ b/src/drivers/i2c/w83793/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ struct drivers_i2c_w83793_config { u8 mfc; diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index dd95e183b5..8cf5d87b20 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/i2c/w83793/w83793.h b/src/drivers/i2c/w83793/w83793.h index 2d149ba71f..3517416fba 100644 --- a/src/drivers/i2c/w83793/w83793.h +++ b/src/drivers/i2c/w83793/w83793.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef W83793_H #define W83793_H diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index fea7acb2e2..c6c5b50a42 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 2039c9c799..b65d0a53ea 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S index a8db68afd8..8c23550e20 100644 --- a/src/drivers/intel/fsp1_1/exit_car.S +++ b/src/drivers/intel/fsp1_1/exit_car.S @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ .text diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index eb641516b4..765bee2786 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c index b78ecad216..66d0b6caaa 100644 --- a/src/drivers/intel/fsp1_1/fsp_relocate.c +++ b/src/drivers/intel/fsp1_1/fsp_relocate.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 891dc0379d..e0f66168d6 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 679cdf8032..f35a83b507 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h index 96fb0d07d9..26b91d94de 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/api.h +++ b/src/drivers/intel/fsp1_1/include/fsp/api.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _FSP1_1_API_H_ #define _FSP1_1_API_H_ diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 461f8463bc..e740a028c5 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef FSP1_1_CAR_H #define FSP1_1_CAR_H diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index e50edd8773..0800345631 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTEL_COMMON_RAMSTAGE_H_ #define _INTEL_COMMON_RAMSTAGE_H_ diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index bee49cf8ad..c062623679 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMON_ROMSTAGE_H_ #define _COMMON_ROMSTAGE_H_ diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h index a4563f448f..3ecaa8fc5a 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _FSP1_1_SOC_BINDING_H_ #define _FSP1_1_SOC_BINDING_H_ diff --git a/src/drivers/intel/fsp1_1/include/fsp/stack.h b/src/drivers/intel/fsp1_1/include/fsp/stack.h index dc4834d106..72708a02d7 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/stack.h +++ b/src/drivers/intel/fsp1_1/include/fsp/stack.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMON_STACK_H_ #define _COMMON_STACK_H_ diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h index b13b99832c..054831436b 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _FSP1_1_UEFI_BINDING_H_ #define _FSP1_1_UEFI_BINDING_H_ diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 73b156fb94..9e2ba27fde 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c index b00406d2bd..406b4bd38a 100644 --- a/src/drivers/intel/fsp1_1/logo.c +++ b/src/drivers/intel/fsp1_1/logo.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c index d62893d344..6edd391413 100644 --- a/src/drivers/intel/fsp1_1/mma_core.c +++ b/src/drivers/intel/fsp1_1/mma_core.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 208ebb5a58..af554f43b4 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 05a29cbf75..8d51244914 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 7773df731e..5f7864412b 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index c84adc50b8..29330efe6c 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp1_1/verstage.c b/src/drivers/intel/fsp1_1/verstage.c index 78866a19f7..c36ac47389 100644 --- a/src/drivers/intel/fsp1_1/verstage.c +++ b/src/drivers/intel/fsp1_1/verstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 7e743dfcdd..f9c680ded9 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h index b2ad0cbfa3..48cd268443 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h +++ b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _FSP2_0_MEMORY_INIT_H_ #define _FSP2_0_MEMORY_INIT_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h index 4b0579bad0..43c549826e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h +++ b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MP_SERVICE_PPI_H #define MP_SERVICE_PPI_H diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 607738d7a4..16bd2412fa 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _FSP2_0_SOC_BINDING_H_ #define _FSP2_0_SOC_BINDING_H_ diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c index 1a9152f97b..ef0dbf1563 100644 --- a/src/drivers/intel/fsp2_0/logo.c +++ b/src/drivers/intel/fsp2_0/logo.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c index b5590a6bc4..0b9b04cb5a 100644 --- a/src/drivers/intel/fsp2_0/mma_core.c +++ b/src/drivers/intel/fsp2_0/mma_core.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 7699ebcd24..fead4f1a98 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index ff44ac1b60..f8721a2fa9 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef INTEL_I915_H #define INTEL_I915_H 1 diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 11efe8c57d..4bba3f4380 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/gma/libgfxinit.h b/src/drivers/intel/gma/libgfxinit.h index 7a00b5cf65..ed6bfd7eb9 100644 --- a/src/drivers/intel/gma/libgfxinit.h +++ b/src/drivers/intel/gma/libgfxinit.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_INTEL_GMA_LIBGFXINIT_H #define DRIVERS_INTEL_GMA_LIBGFXINIT_H diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index cb2414f30c..6bdfda7236 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "i210.h" #include diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h index f4a8faf5fc..6b8328773f 100644 --- a/src/drivers/intel/i210/i210.h +++ b/src/drivers/intel/i210/i210.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTEL_I210_H_ #define _INTEL_I210_H_ diff --git a/src/drivers/intel/ish/chip.h b/src/drivers/intel/ish/chip.h index 69926f09f0..a76e44b4e8 100644 --- a/src/drivers/intel/ish/chip.h +++ b/src/drivers/intel/ish/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Intel Integrated Sensor Hub (ISH) diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 256b486dc8..d7740a4d6f 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 92fa00b956..0d8c10e7ae 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 167c71aa0d..178d394c30 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __INTEL_MIPI_CAMERA_CHIP_H__ #define __INTEL_MIPI_CAMERA_CHIP_H__ diff --git a/src/drivers/intel/ptt/ptt.c b/src/drivers/intel/ptt/ptt.c index 738de50a8f..ef4c7e3095 100644 --- a/src/drivers/intel/ptt/ptt.c +++ b/src/drivers/intel/ptt/ptt.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/intel/ptt/ptt.h b/src/drivers/intel/ptt/ptt.h index e0a901fccf..0d1d3f66f2 100644 --- a/src/drivers/intel/ptt/ptt.h +++ b/src/drivers/intel/ptt/ptt.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This driver checks if the PTT Bit is set correctly within the FWSTS4 diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h index ed25d8f9d1..41366e5341 100644 --- a/src/drivers/intel/wifi/chip.h +++ b/src/drivers/intel/wifi/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTEL_WIFI_CHIP_H_ #define _INTEL_WIFI_CHIP_H_ diff --git a/src/drivers/ipmi/chip.h b/src/drivers/ipmi/chip.h index b3bb5a5d8a..4e9641b7e5 100644 --- a/src/drivers/ipmi/chip.h +++ b/src/drivers/ipmi/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _IMPI_CHIP_H_ #define _IPMI_CHIP_H_ diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 590e606424..7fd3d303b2 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index d3916198a6..2a883d50c0 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index 9a04377a0a..d511edfd4f 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __IPMI_KCS_H #define __IPMI_KCS_H diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index e5f60fe6b8..2ab137e937 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Place in devicetree.cb: diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index ef9319204e..25bf077aef 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "ipmi_ops.h" diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index cbd9657558..f88959544b 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #ifndef __IPMI_OPS_H #define __IPMI_OPS_H -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ #include #include "ipmi_kcs.h" diff --git a/src/drivers/lenovo/hybrid_graphics/chip.h b/src/drivers/lenovo/hybrid_graphics/chip.h index 6926e6f626..13ece974e3 100644 --- a/src/drivers/lenovo/hybrid_graphics/chip.h +++ b/src/drivers/lenovo/hybrid_graphics/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _LENOVO_HYBRID_GRAPHICS_CHIP_H_ #define _LENOVO_HYBRID_GRAPHICS_CHIP_H_ diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index 6cc7a79d30..7f05624c70 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h index 11085d1913..5ca82cb401 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_ #define _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_ diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 6a44000e49..55de375c43 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 2287f27d4b..2b63129435 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 5cc70ceddd..943829af82 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This driver sets the macaddress of a Atheros AR8121/AR8113/AR8114 diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 249b80f740..bc4ae4b6e8 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __DRIVERS_R8168_CHIP_H__ #define __DRIVERS_R8168_CHIP_H__ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 6e9437005d..c547f1776c 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This driver resets the 10ec:8168 NIC then tries to read diff --git a/src/drivers/parade/ps8625/ps8625.c b/src/drivers/parade/ps8625/ps8625.c index 8fd03b8b05..390eda4306 100644 --- a/src/drivers/parade/ps8625/ps8625.c +++ b/src/drivers/parade/ps8625/ps8625.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h index 7eb8b98df2..def2259a4c 100644 --- a/src/drivers/parade/ps8625/ps8625.h +++ b/src/drivers/parade/ps8625/ps8625.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __PS8625_H__ #define __PS8625_H__ diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index 88688ee7ad..ac13eea990 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h index 6fdd46641f..d5e86f682b 100644 --- a/src/drivers/parade/ps8640/ps8640.h +++ b/src/drivers/parade/ps8640/ps8640.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 0b04b393e4..cb5601102c 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/pc/i8259.c b/src/drivers/pc80/pc/i8259.c index b96f1d02f4..3d7ecbbb7e 100644 --- a/src/drivers/pc80/pc/i8259.c +++ b/src/drivers/pc80/pc/i8259.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/pc/isa-dma.c b/src/drivers/pc80/pc/isa-dma.c index c7290e0341..b5bdd0bfc9 100644 --- a/src/drivers/pc80/pc/isa-dma.c +++ b/src/drivers/pc80/pc/isa-dma.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c index cf40e65531..d841f946fb 100644 --- a/src/drivers/pc80/pc/keyboard.c +++ b/src/drivers/pc80/pc/keyboard.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/pc/ps2_controller.asl b/src/drivers/pc80/pc/ps2_controller.asl index 3c0c70d49c..210a687681 100644 --- a/src/drivers/pc80/pc/ps2_controller.asl +++ b/src/drivers/pc80/pc/ps2_controller.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PS2K) // Keyboard { Name(_HID, EISAID("PNP0303")) diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index c197d375fb..419ed6b9fc 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index d345281314..37f1470b9f 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index dc78dbbf30..0f6b7f0d27 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 0d5d0e1ae2..1ac36305a0 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/pc80/tpm/chip.h b/src/drivers/pc80/tpm/chip.h index e79ba16f33..35f66c9bc5 100644 --- a/src/drivers/pc80/tpm/chip.h +++ b/src/drivers/pc80/tpm/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_PC80_TPM_CHIP_H #define DRIVERS_PC80_TPM_CHIP_H diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index b9fd0cf006..98d31c0a82 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The code in this file has been heavily based on the article "Writing a TPM diff --git a/src/drivers/pc80/vga/vga.h b/src/drivers/pc80/vga/vga.h index a1c566204c..0b53de2758 100644 --- a/src/drivers/pc80/vga/vga.h +++ b/src/drivers/pc80/vga/vga.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _VGA_H #define _VGA_H diff --git a/src/drivers/ricoh/rce822/chip.h b/src/drivers/ricoh/rce822/chip.h index d7f8a67c64..2de127f302 100644 --- a/src/drivers/ricoh/rce822/chip.h +++ b/src/drivers/ricoh/rce822/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DRIVERS_RICOH_RC822_CHIP_H #define DRIVERS_RICOH_RC822_CHIP_H diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index 08e328da72..fb714c2406 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/secunet/dmi/smbios.c b/src/drivers/secunet/dmi/smbios.c index 5dfbb5d8b7..fa7309fd27 100644 --- a/src/drivers/secunet/dmi/smbios.c +++ b/src/drivers/secunet/dmi/smbios.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index b305a8c848..406fc8d33e 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index 2cfe1ce243..a4bb8f9c4b 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SIEMENS_NC_FPGA_H_ #define _SIEMENS_NC_FPGA_H_ diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index a249181ea7..50147c2d52 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index 93acbcb675..57f79b8c46 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index e0bfa10e0b..dbad085d7c 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 30a81262ce..fc5feea860 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h index 57c1a5cad1..b74c1776a2 100644 --- a/src/drivers/spi/acpi/chip.h +++ b/src/drivers/spi/acpi/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SPI_ACPI_CHIP_H__ #define __SPI_ACPI_CHIP_H__ diff --git a/src/drivers/spi/bitbang.c b/src/drivers/spi/bitbang.c index d0caa04816..58369b87d1 100644 --- a/src/drivers/spi/bitbang.c +++ b/src/drivers/spi/bitbang.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index 5de9a71ceb..90e492460f 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index c68b9061f8..5b16d18150 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file provides a common CBFS wrapper for SPI storage. SPI driver diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 2216e7df90..54e17c895b 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index 3c70915c6c..03b9be3592 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/drivers/spi/spi_winbond.h b/src/drivers/spi/spi_winbond.h index 73029527ee..57ef51fab5 100644 --- a/src/drivers/spi/spi_winbond.h +++ b/src/drivers/spi/spi_winbond.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Winbond specific function */ /* M25Pxx-specific commands */ diff --git a/src/drivers/spi/spiconsole.c b/src/drivers/spi/spiconsole.c index fffeafaaea..dd73e4b865 100644 --- a/src/drivers/spi/spiconsole.c +++ b/src/drivers/spi/spiconsole.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/ti/tps65913/tps65913rtc.c b/src/drivers/ti/tps65913/tps65913rtc.c index 47f08c5ec3..04fd524ff9 100644 --- a/src/drivers/ti/tps65913/tps65913rtc.c +++ b/src/drivers/ti/tps65913/tps65913rtc.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index b6546667a9..53a0c4b59b 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 60b524576e..2ff7ead756 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index d12b42ace2..0afcb3d8ee 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index b527ecca9d..2caad545e0 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 1b9194ec2d..53c72876ff 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index c519b4d53e..fafb06bdfa 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index 865611d4ae..f84bac5240 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef UART8250REG_H #define UART8250REG_H diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 2f8aa842b3..c5c5a9c3a9 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 79033bbf4e..42a94d5105 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __USB_ACPI_CHIP_H__ #define __USB_ACPI_CHIP_H__ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 2402e8bd12..d6dc46f180 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/usb/console.c b/src/drivers/usb/console.c index 090c9312b7..7c5f75a64b 100644 --- a/src/drivers/usb/console.c +++ b/src/drivers/usb/console.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "ehci_debug.h" diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 364f8c7772..094cd56bbe 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index a6a3e55826..08264d5a35 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _EHCI_DEBUG_H_ #define _EHCI_DEBUG_H_ diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index 61e103160b..aefabf7183 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index dfc78cc666..39c859e9e1 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h index 34f7a6077e..ab718d3f7c 100644 --- a/src/drivers/usb/usb_ch9.h +++ b/src/drivers/usb/usb_ch9.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef USB_CH9_H #define USB_CH9_H diff --git a/src/drivers/vpd/vpd_premem.c b/src/drivers/vpd/vpd_premem.c index 7117288cc8..e5e9db9685 100644 --- a/src/drivers/vpd/vpd_premem.c +++ b/src/drivers/vpd/vpd_premem.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h index f14051b473..1c90bc6d66 100644 --- a/src/drivers/wifi/generic_wifi.h +++ b/src/drivers/wifi/generic_wifi.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _GENERIC_WIFI_H_ #define _GENERIC_WIFI_H_ diff --git a/src/drivers/xgi/common/XGI_main.c b/src/drivers/xgi/common/XGI_main.c index d4650998fc..76bd1847b9 100644 --- a/src/drivers/xgi/common/XGI_main.c +++ b/src/drivers/xgi/common/XGI_main.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Code taken from the Linux xgifb driver (v3.18.5) diff --git a/src/drivers/xgi/common/XGI_main.h b/src/drivers/xgi/common/XGI_main.h index cb758ee082..af1f4a6c0f 100644 --- a/src/drivers/xgi/common/XGI_main.h +++ b/src/drivers/xgi/common/XGI_main.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/XGIfb.h b/src/drivers/xgi/common/XGIfb.h index a528dae4b9..8ca37a1dbd 100644 --- a/src/drivers/xgi/common/XGIfb.h +++ b/src/drivers/xgi/common/XGIfb.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_def.h b/src/drivers/xgi/common/vb_def.h index 4a98d5d714..3e96ac5a17 100644 --- a/src/drivers/xgi/common/vb_def.h +++ b/src/drivers/xgi/common/vb_def.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index ab27439b9b..ee810d6659 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ /* coreboot related includes come indirectly from xgi_coreboot.h */ diff --git a/src/drivers/xgi/common/vb_init.h b/src/drivers/xgi/common/vb_init.h index 8d2e2be019..d8f3bbdca9 100644 --- a/src/drivers/xgi/common/vb_init.h +++ b/src/drivers/xgi/common/vb_init.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index fdb7039013..b5f03ebb3d 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_setmode.h b/src/drivers/xgi/common/vb_setmode.h index 140b3b61d7..9ad475ec05 100644 --- a/src/drivers/xgi/common/vb_setmode.h +++ b/src/drivers/xgi/common/vb_setmode.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_struct.h b/src/drivers/xgi/common/vb_struct.h index 705a1aed59..78b0e6785a 100644 --- a/src/drivers/xgi/common/vb_struct.h +++ b/src/drivers/xgi/common/vb_struct.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_table.h b/src/drivers/xgi/common/vb_table.h index c4d1df06b1..d1ca2587e7 100644 --- a/src/drivers/xgi/common/vb_table.h +++ b/src/drivers/xgi/common/vb_table.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c index dbaaa0c907..0283633ee9 100644 --- a/src/drivers/xgi/common/vb_util.c +++ b/src/drivers/xgi/common/vb_util.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vb_util.h b/src/drivers/xgi/common/vb_util.h index c71b0df5d8..878b7c6d05 100644 --- a/src/drivers/xgi/common/vb_util.h +++ b/src/drivers/xgi/common/vb_util.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/vgatypes.h b/src/drivers/xgi/common/vgatypes.h index db10f4d5af..b39dbcb699 100644 --- a/src/drivers/xgi/common/vgatypes.h +++ b/src/drivers/xgi/common/vgatypes.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* File taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index d65e007a2a..2cdd22aa95 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Code taken from the Linux xgifb driver (v3.18.5) */ diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index c0aa3b3d91..8ce6139b61 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 58c0d32ca8d928186d5c2b5b297e712e6ec9be4b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:20:46 +0200 Subject: [PATCH 0849/1463] mb/google/auron: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I890c2367799196e0b9f986d95bcda1d9090a694d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40143 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/auron/acpi/ec.asl | 15 ++------------- src/mainboard/google/auron/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/auron/acpi/superio.asl | 15 ++------------- src/mainboard/google/auron/acpi/thermal.asl | 15 ++------------- src/mainboard/google/auron/acpi/video.asl | 15 ++------------- src/mainboard/google/auron/acpi_tables.c | 15 ++------------- src/mainboard/google/auron/chromeos.c | 15 ++------------- src/mainboard/google/auron/dsdt.asl | 15 ++------------- src/mainboard/google/auron/ec.c | 15 ++------------- src/mainboard/google/auron/ec.h | 15 ++------------- src/mainboard/google/auron/fadt.c | 15 ++------------- src/mainboard/google/auron/hda_verb.c | 14 ++------------ src/mainboard/google/auron/mainboard.c | 15 ++------------- src/mainboard/google/auron/romstage.c | 15 ++------------- src/mainboard/google/auron/smihandler.c | 15 ++------------- src/mainboard/google/auron/variant.h | 14 ++------------ .../google/auron/variants/auron_paine/gpio.c | 15 ++------------- .../include/variant/acpi/mainboard.asl | 16 ++-------------- .../auron_paine/include/variant/acpi/usb.asl | 14 ++------------ .../auron_paine/include/variant/hda_verb.h | 15 ++------------- .../auron_paine/include/variant/onboard.h | 15 ++------------- .../variants/auron_paine/include/variant/spd.h | 15 ++------------- .../auron_paine/include/variant/thermal.h | 15 ++------------- .../google/auron/variants/auron_paine/pei_data.c | 15 ++------------- .../google/auron/variants/auron_paine/spd/spd.c | 15 ++------------- .../google/auron/variants/auron_paine/variant.c | 14 ++------------ .../google/auron/variants/auron_yuna/gpio.c | 15 ++------------- .../include/variant/acpi/mainboard.asl | 16 ++-------------- .../auron_yuna/include/variant/acpi/usb.asl | 14 ++------------ .../auron_yuna/include/variant/hda_verb.h | 15 ++------------- .../auron_yuna/include/variant/onboard.h | 15 ++------------- .../variants/auron_yuna/include/variant/spd.h | 15 ++------------- .../auron_yuna/include/variant/thermal.h | 15 ++------------- .../google/auron/variants/auron_yuna/pei_data.c | 15 ++------------- .../google/auron/variants/auron_yuna/spd/spd.c | 15 ++------------- .../google/auron/variants/auron_yuna/variant.c | 14 ++------------ src/mainboard/google/auron/variants/buddy/gpio.c | 16 ++-------------- .../buddy/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/buddy/include/variant/hda_verb.h | 16 ++-------------- .../variants/buddy/include/variant/onboard.h | 16 ++-------------- .../auron/variants/buddy/include/variant/spd.h | 16 ++-------------- .../variants/buddy/include/variant/thermal.h | 16 ++-------------- .../google/auron/variants/buddy/pei_data.c | 16 ++-------------- .../google/auron/variants/buddy/spd/spd.c | 16 ++-------------- .../google/auron/variants/buddy/variant.c | 14 ++------------ .../google/auron/variants/gandof/gpio.c | 15 ++------------- .../variants/gandof/include/variant/acpi/ec.asl | 14 ++------------ .../gandof/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/gandof/include/variant/acpi/usb.asl | 14 ++------------ .../variants/gandof/include/variant/hda_verb.h | 15 ++------------- .../variants/gandof/include/variant/onboard.h | 15 ++------------- .../auron/variants/gandof/include/variant/spd.h | 15 ++------------- .../variants/gandof/include/variant/thermal.h | 15 ++------------- .../google/auron/variants/gandof/pei_data.c | 15 ++------------- .../google/auron/variants/gandof/spd/spd.c | 15 ++------------- .../google/auron/variants/gandof/variant.c | 14 ++------------ src/mainboard/google/auron/variants/lulu/gpio.c | 15 ++------------- .../variants/lulu/include/variant/acpi/ec.asl | 14 ++------------ .../lulu/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/lulu/include/variant/acpi/usb.asl | 14 ++------------ .../variants/lulu/include/variant/hda_verb.h | 15 ++------------- .../variants/lulu/include/variant/onboard.h | 15 ++------------- .../auron/variants/lulu/include/variant/spd.h | 15 ++------------- .../variants/lulu/include/variant/thermal.h | 15 ++------------- .../google/auron/variants/lulu/pei_data.c | 15 ++------------- .../google/auron/variants/lulu/spd/spd.c | 15 ++------------- .../google/auron/variants/lulu/variant.c | 14 ++------------ .../google/auron/variants/samus/board_version.c | 15 ++------------- src/mainboard/google/auron/variants/samus/gpio.c | 15 ++------------- .../variants/samus/include/variant/acpi/ec.asl | 14 ++------------ .../samus/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/samus/include/variant/acpi/usb.asl | 14 ++------------ .../samus/include/variant/board_version.h | 15 ++------------- .../variants/samus/include/variant/hda_verb.h | 14 ++------------ .../variants/samus/include/variant/onboard.h | 15 ++------------- .../auron/variants/samus/include/variant/spd.h | 15 ++------------- .../variants/samus/include/variant/thermal.h | 15 ++------------- .../google/auron/variants/samus/pei_data.c | 15 ++------------- .../google/auron/variants/samus/spd/spd.c | 15 ++------------- .../google/auron/variants/samus/variant.c | 14 ++------------ 80 files changed, 160 insertions(+), 1036 deletions(-) diff --git a/src/mainboard/google/auron/acpi/ec.asl b/src/mainboard/google/auron/acpi/ec.asl index d495af4bcd..34e69027fe 100644 --- a/src/mainboard/google/auron/acpi/ec.asl +++ b/src/mainboard/google/auron/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "ec.h" diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index e726fe6dcf..e6ddedc71f 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/acpi/superio.asl b/src/mainboard/google/auron/acpi/superio.asl index a64734771e..aba83438cb 100644 --- a/src/mainboard/google/auron/acpi/superio.asl +++ b/src/mainboard/google/auron/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl index 0e57afae36..bcef1351d2 100644 --- a/src/mainboard/google/auron/acpi/thermal.asl +++ b/src/mainboard/google/auron/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Generated by acpigen */ External (\PPKG, MethodObj) diff --git a/src/mainboard/google/auron/acpi/video.asl b/src/mainboard/google/auron/acpi/video.asl index e4b8b8e2c7..02ce875402 100644 --- a/src/mainboard/google/auron/acpi/video.asl +++ b/src/mainboard/google/auron/acpi/video.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Brightness write Method (BRTW, 1, Serialized) diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 042c1be8c5..1cfdb11742 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index a268f0ab77..7696b9d0ef 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index a22dedd82f..6a9e693a06 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index 089dbeef81..b3a2d61a7b 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/ec.h b/src/mainboard/google/auron/ec.h index 1242c7e3f5..0a8a350d9b 100644 --- a/src/mainboard/google/auron/ec.h +++ b/src/mainboard/google/auron/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index 6afc8e23c0..47d50d28c0 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/hda_verb.c b/src/mainboard/google/auron/hda_verb.c index d1241a085c..6f18171e7c 100644 --- a/src/mainboard/google/auron/hda_verb.c +++ b/src/mainboard/google/auron/hda_verb.c @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 3cb44f90ad..1dac840ce2 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 34749c42fc..4bedd28cb6 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 324227e704..ab32930bee 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index e5f5f0404b..0e4944783b 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/auron/variants/auron_paine/gpio.c b/src/mainboard/google/auron/variants/auron_paine/gpio.c index 59593da4f0..abb1e56a79 100644 --- a/src/mainboard/google/auron/variants/auron_paine/gpio.c +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl index c521937177..168888ab0d 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl index 9227680d53..3538c719ee 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT1) { diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h index 66ff8afbfe..22630e76a3 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h index 4f4dfeb970..a8adf0acea 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h index aaa2ae0f1e..15d9b73a91 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h index cc87da619f..41913441e0 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index f86b8f64a4..83eca9120e 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 2baac7b916..394949127b 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c index 84e26db1b7..2070ea6c85 100644 --- a/src/mainboard/google/auron/variants/auron_paine/variant.c +++ b/src/mainboard/google/auron/variants/auron_paine/variant.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/auron_yuna/gpio.c b/src/mainboard/google/auron/variants/auron_yuna/gpio.c index 59593da4f0..abb1e56a79 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/gpio.c +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl index c521937177..168888ab0d 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl index e3c8659f94..5f71b04e96 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT2) { diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h index 4b37e986d3..0649f01f36 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h index 4f4dfeb970..a8adf0acea 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h index aaa2ae0f1e..15d9b73a91 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h index cc87da619f..41913441e0 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index f86b8f64a4..83eca9120e 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 2baac7b916..394949127b 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c index 84e26db1b7..2070ea6c85 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/variant.c +++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/buddy/gpio.c b/src/mainboard/google/auron/variants/buddy/gpio.c index ec660c526b..28cde64375 100644 --- a/src/mainboard/google/auron/variants/buddy/gpio.c +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index a56deb2202..5e099d5606 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h index 5dec333265..69d2b7d677 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h index 3a1b48f0f0..2b1219c12b 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h index ea0a5c45ab..4a0fbb4ce9 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h b/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h index 1fb6b859dc..41913441e0 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index 5840a9cb14..3be810f991 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index fe0892a807..10d5604d89 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 4e05711970..95d7df52cc 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/gandof/gpio.c b/src/mainboard/google/auron/variants/gandof/gpio.c index b789b87321..9d1fb1cd55 100644 --- a/src/mainboard/google/auron/variants/gandof/gpio.c +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl index 12b59b43c1..1158f2f0e4 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl index c521937177..168888ab0d 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl index e3c8659f94..5f71b04e96 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT2) { diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h index 8b9e76fe82..37eea17bfd 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h b/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h index 4f4dfeb970..a8adf0acea 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h index 4bbf0efa8d..bb0b2c53d6 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h b/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h index 7136afaf3f..d26963adf2 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index f86b8f64a4..83eca9120e 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 2baac7b916..394949127b 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index 29b298839f..d8522a3b27 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/lulu/gpio.c b/src/mainboard/google/auron/variants/lulu/gpio.c index 8aac461477..e84bf326f0 100644 --- a/src/mainboard/google/auron/variants/lulu/gpio.c +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl index 12b59b43c1..1158f2f0e4 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl index a781ea4e6f..2c7de87699 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl index 4f931e26c2..019300f9a7 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT1) { diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h index da4e92c290..7f983c8764 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h index 9e46521d06..5138d3e670 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h index 503b192eb1..d316fa1f21 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h index cc87da619f..41913441e0 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index e547438db1..d03a9e8764 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 30e7fd71bb..869119f04d 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index a76cc858c3..dd93b7a656 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/samus/board_version.c b/src/mainboard/google/auron/variants/samus/board_version.c index 2853d44dcc..f6aab76d1e 100644 --- a/src/mainboard/google/auron/variants/samus/board_version.c +++ b/src/mainboard/google/auron/variants/samus/board_version.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/samus/gpio.c b/src/mainboard/google/auron/variants/samus/gpio.c index f6b6c71d9b..90bca12944 100644 --- a/src/mainboard/google/auron/variants/samus/gpio.c +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl index 12b59b43c1..1158f2f0e4 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 2253fd71a1..60fd3f1fcb 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef ENABLE_TOUCH_WAKE diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl index d36a12267b..a863bb7e13 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT1) { diff --git a/src/mainboard/google/auron/variants/samus/include/variant/board_version.h b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h index 6129ce5591..e99b16d0f1 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/board_version.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SAMUS_BOARD_VERSION_H #define SAMUS_BOARD_VERSION_H diff --git a/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h index 5d088790a5..0700c48e63 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/auron/variants/samus/include/variant/onboard.h b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h index 1e1373a223..fb920fe096 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/onboard.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h index e22a40ecc0..06b750dc9b 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/auron/variants/samus/include/variant/thermal.h b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h index cc87da619f..41913441e0 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/thermal.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index be6b49a101..2f4e819208 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 5a9e2d3ff8..eaa3a64074 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 32a0d29b74..5e16ffd1f8 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 64b5d974d5c6a567728023b776331ca73e2b9df8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:20:50 +0200 Subject: [PATCH 0850/1463] mb/google/beltino: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie7a2074c2319911395234e4ce8ec35b8209bcc01 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40144 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/beltino/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/beltino/acpi/platform.asl | 15 ++------------- src/mainboard/google/beltino/acpi/superio.asl | 15 ++------------- src/mainboard/google/beltino/acpi/thermal.asl | 15 ++------------- src/mainboard/google/beltino/acpi/usb.asl | 15 ++------------- src/mainboard/google/beltino/acpi_tables.c | 15 ++------------- src/mainboard/google/beltino/chromeos.c | 15 ++------------- src/mainboard/google/beltino/dsdt.asl | 15 ++------------- src/mainboard/google/beltino/lan.c | 15 ++------------- src/mainboard/google/beltino/mainboard.c | 15 ++------------- src/mainboard/google/beltino/onboard.h | 14 ++------------ src/mainboard/google/beltino/romstage.c | 15 ++------------- src/mainboard/google/beltino/smihandler.c | 15 ++------------- .../google/beltino/variants/mccloud/hda_verb.c | 15 ++------------- .../variants/mccloud/include/variant/gpio.h | 15 ++------------- .../variants/mccloud/include/variant/thermal.h | 15 ++------------- .../google/beltino/variants/mccloud/led.c | 15 ++------------- .../google/beltino/variants/monroe/hda_verb.c | 15 ++------------- .../variants/monroe/include/variant/gpio.h | 15 ++------------- .../variants/monroe/include/variant/thermal.h | 15 ++------------- .../google/beltino/variants/monroe/led.c | 15 ++------------- .../google/beltino/variants/panther/hda_verb.c | 15 ++------------- .../variants/panther/include/variant/gpio.h | 15 ++------------- .../variants/panther/include/variant/thermal.h | 15 ++------------- .../google/beltino/variants/panther/led.c | 15 ++------------- .../google/beltino/variants/tricky/hda_verb.c | 15 ++------------- .../variants/tricky/include/variant/gpio.h | 15 ++------------- .../variants/tricky/include/variant/thermal.h | 15 ++------------- .../google/beltino/variants/tricky/led.c | 15 ++------------- .../google/beltino/variants/zako/hda_verb.c | 15 ++------------- .../beltino/variants/zako/include/variant/gpio.h | 15 ++------------- .../variants/zako/include/variant/thermal.h | 15 ++------------- src/mainboard/google/beltino/variants/zako/led.c | 15 ++------------- 33 files changed, 66 insertions(+), 429 deletions(-) diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index d73ff8b56a..2f0a4e523f 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/beltino/acpi/platform.asl b/src/mainboard/google/beltino/acpi/platform.asl index c0fac8da72..284c55d8ce 100644 --- a/src/mainboard/google/beltino/acpi/platform.asl +++ b/src/mainboard/google/beltino/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/beltino/acpi/superio.asl b/src/mainboard/google/beltino/acpi/superio.asl index 5bc7fdab46..e6846b2c9d 100644 --- a/src/mainboard/google/beltino/acpi/superio.asl +++ b/src/mainboard/google/beltino/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index 7aed671b9a..bfa5822aff 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ External (\PPKG, MethodObj) diff --git a/src/mainboard/google/beltino/acpi/usb.asl b/src/mainboard/google/beltino/acpi/usb.asl index 92b6dc97d8..d36da136c1 100644 --- a/src/mainboard/google/beltino/acpi/usb.asl +++ b/src/mainboard/google/beltino/acpi/usb.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT2) { diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 9d47b976f8..0445d0dcf5 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 9637c8efa7..f3a112d1c7 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index da11fed342..014483c170 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 0e18e83569..a87ca58e65 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 43f80103ce..a31c5decba 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h index 2e0730912e..35ce16ba85 100644 --- a/src/mainboard/google/beltino/onboard.h +++ b/src/mainboard/google/beltino/onboard.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_ONBOARD_H #define __MAINBOARD_ONBOARD_H diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index c50787eae9..373b488fe9 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index c6677341e5..2f4b86f085 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 9f0671b160..847e7374a9 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h b/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h index 2245ce155b..1a36db4ab6 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MCCLOUD_GPIO_H #define MCCLOUD_GPIO_H diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h index 0920bb3bc7..d787b190bd 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/beltino/variants/mccloud/led.c b/src/mainboard/google/beltino/variants/mccloud/led.c index 00e45d131d..ed1d587442 100644 --- a/src/mainboard/google/beltino/variants/mccloud/led.c +++ b/src/mainboard/google/beltino/variants/mccloud/led.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 5b084ac17a..c3b6be9e29 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h b/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h index 7684956e17..ab94180720 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MONROE_GPIO_H #define MONROE_GPIO_H diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h index 898e029c4b..d7284b8023 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/beltino/variants/monroe/led.c b/src/mainboard/google/beltino/variants/monroe/led.c index 9e2c698be0..bc8a9c47f2 100644 --- a/src/mainboard/google/beltino/variants/monroe/led.c +++ b/src/mainboard/google/beltino/variants/monroe/led.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "../../onboard.h" diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 9f0671b160..847e7374a9 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h b/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h index 6536e52462..2bce5151a8 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PANTHER_GPIO_H #define PANTHER_GPIO_H diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h index 8ea3823bec..3cd6250fb1 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/beltino/variants/panther/led.c b/src/mainboard/google/beltino/variants/panther/led.c index 5c91eb859c..0d9fdf8998 100644 --- a/src/mainboard/google/beltino/variants/panther/led.c +++ b/src/mainboard/google/beltino/variants/panther/led.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "../../onboard.h" diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 9f0671b160..847e7374a9 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h b/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h index 3aefce0544..d2b5c84dd7 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef TRICKY_GPIO_H #define TRICKY_GPIO_H diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h index ff11d7a8db..5bf87d2d92 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/beltino/variants/tricky/led.c b/src/mainboard/google/beltino/variants/tricky/led.c index d22bc9cc7f..6953d15742 100644 --- a/src/mainboard/google/beltino/variants/tricky/led.c +++ b/src/mainboard/google/beltino/variants/tricky/led.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 9f0671b160..847e7374a9 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h b/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h index 606cdb6a9c..3d75ae572a 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ZAKO_GPIO_H #define ZAKO_GPIO_H diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h index 60f86cfd27..e81043566c 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/beltino/variants/zako/led.c b/src/mainboard/google/beltino/variants/zako/led.c index e44aa489ed..02c4489cd1 100644 --- a/src/mainboard/google/beltino/variants/zako/led.c +++ b/src/mainboard/google/beltino/variants/zako/led.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "../../onboard.h" From 54c5472f3f98822fe6560847ec08e123b2ac020c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:20:54 +0200 Subject: [PATCH 0851/1463] mb/google/butterfly: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: If78d4f1715f91671b3fb9557a8c5dfbc46bb07a5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40165 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/butterfly/acpi/ec.asl | 15 ++------------- .../google/butterfly/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/butterfly/acpi/platform.asl | 15 ++------------- src/mainboard/google/butterfly/acpi/superio.asl | 15 ++------------- src/mainboard/google/butterfly/acpi/thermal.asl | 15 ++------------- src/mainboard/google/butterfly/acpi_tables.c | 15 ++------------- src/mainboard/google/butterfly/chromeos.c | 15 ++------------- src/mainboard/google/butterfly/dsdt.asl | 15 ++------------- src/mainboard/google/butterfly/early_init.c | 15 ++------------- src/mainboard/google/butterfly/ec.c | 15 ++------------- src/mainboard/google/butterfly/ec.h | 15 ++------------- src/mainboard/google/butterfly/gpio.c | 15 ++------------- src/mainboard/google/butterfly/hda_verb.c | 15 ++------------- src/mainboard/google/butterfly/mainboard.c | 15 ++------------- src/mainboard/google/butterfly/mainboard_smi.c | 15 ++------------- src/mainboard/google/butterfly/onboard.h | 15 ++------------- src/mainboard/google/butterfly/thermal.h | 15 ++------------- 17 files changed, 34 insertions(+), 222 deletions(-) diff --git a/src/mainboard/google/butterfly/acpi/ec.asl b/src/mainboard/google/butterfly/acpi/ec.asl index faba3ff412..e9a7d61f95 100644 --- a/src/mainboard/google/butterfly/acpi/ec.asl +++ b/src/mainboard/google/butterfly/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index 11b6852b20..77a3aaa2ea 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/butterfly/acpi/platform.asl b/src/mainboard/google/butterfly/acpi/platform.asl index 01e106b13f..a54c5daa25 100644 --- a/src/mainboard/google/butterfly/acpi/platform.asl +++ b/src/mainboard/google/butterfly/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/butterfly/acpi/superio.asl b/src/mainboard/google/butterfly/acpi/superio.asl index cb06a9aec4..9aa9b218a9 100644 --- a/src/mainboard/google/butterfly/acpi/superio.asl +++ b/src/mainboard/google/butterfly/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/butterfly/acpi/thermal.asl b/src/mainboard/google/butterfly/acpi/thermal.asl index f9964e966b..56bc6c7e8d 100644 --- a/src/mainboard/google/butterfly/acpi/thermal.asl +++ b/src/mainboard/google/butterfly/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 0e930aa78e..f9c5e24de6 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 74a3031d6d..a19dc9fa40 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 2596de25ba..f75d858f2f 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index a3cea3f5e2..f0658fea2f 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/butterfly/ec.c b/src/mainboard/google/butterfly/ec.c index 6e1fc349a7..0fdfab3c1e 100644 --- a/src/mainboard/google/butterfly/ec.c +++ b/src/mainboard/google/butterfly/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/butterfly/ec.h b/src/mainboard/google/butterfly/ec.h index 47acc0c4fa..514fb7619f 100644 --- a/src/mainboard/google/butterfly/ec.h +++ b/src/mainboard/google/butterfly/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BUTTERFLY_EC_H #define BUTTERFLY_EC_H diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c index 167731b9c6..c953b8c445 100644 --- a/src/mainboard/google/butterfly/gpio.c +++ b/src/mainboard/google/butterfly/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c index de08867e76..22d0fd4dfd 100644 --- a/src/mainboard/google/butterfly/hda_verb.c +++ b/src/mainboard/google/butterfly/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 03a1df4d04..4c47a6b29a 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index eb069ea758..304e475a19 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index 3aad95924d..926101464c 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BUTTERFLY_ONBOARD_H #define BUTTERFLY_ONBOARD_H diff --git a/src/mainboard/google/butterfly/thermal.h b/src/mainboard/google/butterfly/thermal.h index 9cfc5d77bd..610c9d41fc 100644 --- a/src/mainboard/google/butterfly/thermal.h +++ b/src/mainboard/google/butterfly/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BUTTERFLY_THERMAL_H #define BUTTERFLY_THERMAL_H From 6bc1b92977449f0df35bfde5838773fd321acbb2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:20:57 +0200 Subject: [PATCH 0852/1463] mb/google/cheza: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I90a2643e8d2346cd634266af3d7b2dfc7e20bf2d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40166 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/cheza/boardid.c | 15 ++------------- src/mainboard/google/cheza/reset.c | 15 ++------------- 2 files changed, 4 insertions(+), 26 deletions(-) diff --git a/src/mainboard/google/cheza/boardid.c b/src/mainboard/google/cheza/boardid.c index bca28693bd..227caab59a 100644 --- a/src/mainboard/google/cheza/boardid.c +++ b/src/mainboard/google/cheza/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cheza/reset.c b/src/mainboard/google/cheza/reset.c index c566e127fe..28207cd719 100644 --- a/src/mainboard/google/cheza/reset.c +++ b/src/mainboard/google/cheza/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 2de6bdf8570aad695526f9a79324dd87ad7c917c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:00 +0200 Subject: [PATCH 0853/1463] mb/google/cyan: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1122cdc74a71be6d108998fe7027033394ed6459 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40167 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/cyan/acpi/codec_maxim.asl | 16 ++-------------- src/mainboard/google/cyan/acpi/codec_realtek.asl | 16 ++-------------- src/mainboard/google/cyan/acpi/dptf.asl | 15 ++------------- src/mainboard/google/cyan/acpi/ec.asl | 15 ++------------- src/mainboard/google/cyan/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/cyan/acpi/superio.asl | 15 ++------------- .../google/cyan/acpi/touchscreen_elan.asl | 16 ++-------------- .../google/cyan/acpi/touchscreen_melfas.asl | 16 ++-------------- .../google/cyan/acpi/touchscreen_synaptics.asl | 16 ++-------------- .../google/cyan/acpi/trackpad_atmel.asl | 15 ++------------- src/mainboard/google/cyan/acpi/trackpad_elan.asl | 15 ++------------- src/mainboard/google/cyan/acpi_tables.c | 15 ++------------- src/mainboard/google/cyan/chromeos.c | 15 ++------------- src/mainboard/google/cyan/com_init.c | 15 ++------------- src/mainboard/google/cyan/dsdt.asl | 15 ++------------- src/mainboard/google/cyan/ec.c | 15 ++------------- src/mainboard/google/cyan/ec.h | 15 ++------------- src/mainboard/google/cyan/fadt.c | 15 ++------------- src/mainboard/google/cyan/irqroute.c | 15 ++------------- src/mainboard/google/cyan/irqroute.h | 15 ++------------- src/mainboard/google/cyan/mainboard.c | 15 ++------------- src/mainboard/google/cyan/romstage.c | 15 ++------------- src/mainboard/google/cyan/smihandler.c | 15 ++------------- src/mainboard/google/cyan/spd/spd.c | 15 ++------------- src/mainboard/google/cyan/spd/spd_util.h | 15 ++------------- src/mainboard/google/cyan/variants/banon/gpio.c | 15 ++------------- .../variants/banon/include/variant/acpi/dptf.asl | 15 ++------------- .../banon/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/banon/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/banon/romstage.c | 15 ++------------- .../google/cyan/variants/banon/spd_util.c | 15 ++------------- .../baseboard/include/baseboard/variants.h | 16 ++-------------- src/mainboard/google/cyan/variants/celes/gpio.c | 15 ++------------- .../variants/celes/include/variant/acpi/dptf.asl | 15 ++------------- .../celes/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/celes/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/celes/ramstage.c | 15 ++------------- .../google/cyan/variants/celes/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/cyan/gpio.c | 15 ++------------- .../variants/cyan/include/variant/acpi/dptf.asl | 15 ++------------- .../cyan/include/variant/acpi/mainboard.asl | 16 ++-------------- .../cyan/variants/cyan/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/cyan/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/edgar/gpio.c | 15 ++------------- .../variants/edgar/include/variant/acpi/dptf.asl | 15 ++------------- .../edgar/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/edgar/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/edgar/romstage.c | 15 ++------------- .../google/cyan/variants/edgar/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/kefka/gpio.c | 15 ++------------- .../variants/kefka/include/variant/acpi/dptf.asl | 15 ++------------- .../kefka/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/kefka/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/kefka/ramstage.c | 15 ++------------- .../google/cyan/variants/kefka/romstage.c | 15 ++------------- .../google/cyan/variants/kefka/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/reks/gpio.c | 15 ++------------- .../variants/reks/include/variant/acpi/dptf.asl | 15 ++------------- .../reks/include/variant/acpi/mainboard.asl | 16 ++-------------- .../cyan/variants/reks/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/reks/ramstage.c | 15 ++------------- .../google/cyan/variants/reks/romstage.c | 15 ++------------- .../google/cyan/variants/reks/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/relm/gpio.c | 15 ++------------- .../variants/relm/include/variant/acpi/dptf.asl | 15 ++------------- .../relm/include/variant/acpi/mainboard.asl | 16 ++-------------- .../cyan/variants/relm/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/relm/ramstage.c | 15 ++------------- .../google/cyan/variants/relm/romstage.c | 15 ++------------- .../google/cyan/variants/relm/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/setzer/gpio.c | 15 ++------------- .../setzer/include/variant/acpi/dptf.asl | 15 ++------------- .../setzer/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/setzer/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/setzer/ramstage.c | 15 ++------------- .../google/cyan/variants/setzer/romstage.c | 15 ++------------- .../google/cyan/variants/setzer/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/terra/gpio.c | 15 ++------------- .../terra/include/variant/acpi/charger.asl | 15 ++------------- .../variants/terra/include/variant/acpi/cpu.asl | 16 ++-------------- .../variants/terra/include/variant/acpi/dptf.asl | 15 ++------------- .../terra/include/variant/acpi/mainboard.asl | 16 ++-------------- .../terra/include/variant/acpi/thermal.asl | 15 ++------------- .../variants/terra/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/terra/ramstage.c | 15 ++------------- .../google/cyan/variants/terra/romstage.c | 15 ++------------- .../google/cyan/variants/terra/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/ultima/gpio.c | 15 ++------------- .../ultima/include/variant/acpi/dptf.asl | 15 ++------------- .../ultima/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/ultima/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/ultima/ramstage.c | 15 ++------------- .../google/cyan/variants/ultima/spd_util.c | 15 ++------------- src/mainboard/google/cyan/variants/wizpig/gpio.c | 15 ++------------- .../wizpig/include/variant/acpi/dptf.asl | 15 ++------------- .../wizpig/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/wizpig/include/variant/onboard.h | 15 ++------------- .../google/cyan/variants/wizpig/spd_util.c | 15 ++------------- src/mainboard/google/cyan/w25q64.c | 15 ++------------- 99 files changed, 198 insertions(+), 1305 deletions(-) diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index a33f80a730..2a790b46bd 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C2) { diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index 34bf109b89..c5ca297996 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C5) { diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 97dd96f04d..3271754a9c 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Include Variant DPTF */ #include diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl index da185cbc80..08ab88dd14 100644 --- a/src/mainboard/google/cyan/acpi/ec.asl +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 0fc0d94a15..2c02fbebfd 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index ff98b9053a..251ef26b30 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl index 2b6f148631..cac588a1b2 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C1) { diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl index 9391be7fed..3a059143ca 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C1) { diff --git a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl index 7585cb75f8..4b1695219e 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C1) { diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index a1335d9952..a6b82f287d 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C6) { diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl index 9163cff52a..04e51ded39 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_elan.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C6) { diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index 00b3c08165..20d218df2e 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 2968f8d676..da41162cf0 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c index 8c456d3422..5d82115be0 100644 --- a/src/mainboard/google/cyan/com_init.c +++ b/src/mainboard/google/cyan/com_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index f9f494093e..84544fcc55 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index 8ebd096da5..55c3e1ff3c 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h index 450d863ba3..b93c53fa33 100644 --- a/src/mainboard/google/cyan/ec.h +++ b/src/mainboard/google/cyan/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index 9e5af024e4..8d746676e9 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c index f0855adbc2..df43ee9c69 100644 --- a/src/mainboard/google/cyan/irqroute.c +++ b/src/mainboard/google/cyan/irqroute.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "irqroute.h" diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h index 85d8a5f93b..cacabfee84 100644 --- a/src/mainboard/google/cyan/irqroute.h +++ b/src/mainboard/google/cyan/irqroute.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 2ef44d49d8..a87ca8bbf4 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 7116b71ffc..1501c3b668 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 2871915106..8b1032de63 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index cb65b091db..7ceb27db49 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h index cd65be50a4..5e13ddf724 100644 --- a/src/mainboard/google/cyan/spd/spd_util.h +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SPD_UTIL_H #define SPD_UTIL_H diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index c0a1cb25b6..fa1ef880f0 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl index 9be7ba5dd3..6a7a09450c 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl index e2a50d6161..ba4290c43e 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h b/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h index d8d91af1f8..5a736170ea 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/banon/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c index 22787aae27..d1e1a1cf3d 100644 --- a/src/mainboard/google/cyan/variants/banon/romstage.c +++ b/src/mainboard/google/cyan/variants/banon/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/banon/spd_util.c b/src/mainboard/google/cyan/variants/banon/spd_util.c index 1b31e63d8a..093b06a4f1 100644 --- a/src/mainboard/google/cyan/variants/banon/spd_util.c +++ b/src/mainboard/google/cyan/variants/banon/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h index 3609df5874..305facc481 100644 --- a/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index 5304ed0615..3f5f17de7d 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl index 6c53db92ad..872bc485c3 100644 --- a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "NCP15WB_CPU" diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl index 3ee5394431..5bed5cb097 100644 --- a/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Atmel trackpad */ #include diff --git a/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h index ec45a1eb9a..48d5501332 100644 --- a/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/celes/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index bc8c3a97c7..bb2d1074d8 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/cyan/variants/celes/spd_util.c b/src/mainboard/google/cyan/variants/celes/spd_util.c index 58726c182a..42f3e71e48 100644 --- a/src/mainboard/google/cyan/variants/celes/spd_util.c +++ b/src/mainboard/google/cyan/variants/celes/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 1e8590ed56..c9cd286719 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl index 83ba03035a..a4469a41ef 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl index dd30a68f2f..2a0460de92 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan touchscreen */ #include diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h index 5d5ffbc2f1..6dec60ca0b 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/cyan/spd_util.c b/src/mainboard/google/cyan/variants/cyan/spd_util.c index fc0eebb87b..238021893f 100644 --- a/src/mainboard/google/cyan/variants/cyan/spd_util.c +++ b/src/mainboard/google/cyan/variants/cyan/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index 487046a3f2..f90ca79be2 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl index f76f282f68..919369af5e 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl index 19ec65ae63..ba4290c43e 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h index e676768c23..c55a50f998 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c index 1cfc978680..d5ce6b87bf 100644 --- a/src/mainboard/google/cyan/variants/edgar/romstage.c +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/edgar/spd_util.c b/src/mainboard/google/cyan/variants/edgar/spd_util.c index 5197d1b33c..698f2d9dd0 100644 --- a/src/mainboard/google/cyan/variants/edgar/spd_util.c +++ b/src/mainboard/google/cyan/variants/edgar/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 1fe8f604a0..ccff0821e6 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl index 7fc05e0d33..54f78ff321 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl index 8cee066038..0c5331d62b 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan touchscreen */ #include diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h b/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h index a596f3898e..f16825de38 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c index 9dee808d6a..e0ffcc227f 100644 --- a/src/mainboard/google/cyan/variants/kefka/ramstage.c +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/cyan/variants/kefka/romstage.c b/src/mainboard/google/cyan/variants/kefka/romstage.c index f2bf5a65c6..5b10b755f5 100644 --- a/src/mainboard/google/cyan/variants/kefka/romstage.c +++ b/src/mainboard/google/cyan/variants/kefka/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/kefka/spd_util.c b/src/mainboard/google/cyan/variants/kefka/spd_util.c index f7f387409b..a2e9636fca 100644 --- a/src/mainboard/google/cyan/variants/kefka/spd_util.c +++ b/src/mainboard/google/cyan/variants/kefka/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index 82341e4c5d..6d8cb509ac 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl index e70eae0294..a2147dec9a 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_PMIC" diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl index 4a77209ed3..bc132913db 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Melfas touchscreen */ #include diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h index eead309cf3..26a272d465 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/reks/ramstage.c b/src/mainboard/google/cyan/variants/reks/ramstage.c index e212131773..d49f8f141c 100644 --- a/src/mainboard/google/cyan/variants/reks/ramstage.c +++ b/src/mainboard/google/cyan/variants/reks/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c index 312709b7eb..59a65b3077 100644 --- a/src/mainboard/google/cyan/variants/reks/romstage.c +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/reks/spd_util.c b/src/mainboard/google/cyan/variants/reks/spd_util.c index 00b47deb1b..6276853fd2 100644 --- a/src/mainboard/google/cyan/variants/reks/spd_util.c +++ b/src/mainboard/google/cyan/variants/reks/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index d452622e9d..61ede38d8a 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl index e70eae0294..a2147dec9a 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_PMIC" diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl index 4a77209ed3..bc132913db 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Melfas touchscreen */ #include diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h b/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h index 6d4d682e37..5fe4213207 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c index 0030d9f48c..54e11d27a9 100644 --- a/src/mainboard/google/cyan/variants/relm/ramstage.c +++ b/src/mainboard/google/cyan/variants/relm/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/cyan/variants/relm/romstage.c b/src/mainboard/google/cyan/variants/relm/romstage.c index 312709b7eb..59a65b3077 100644 --- a/src/mainboard/google/cyan/variants/relm/romstage.c +++ b/src/mainboard/google/cyan/variants/relm/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/relm/spd_util.c b/src/mainboard/google/cyan/variants/relm/spd_util.c index 5315c5bae3..b9fd41e5f3 100644 --- a/src/mainboard/google/cyan/variants/relm/spd_util.c +++ b/src/mainboard/google/cyan/variants/relm/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index 70ffeba09d..c2acb2b3f7 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl index 324d8bc351..8807296f55 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl index c976fb96d0..b7a67d3bcd 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Synaptics touchscreen */ #include diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h b/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h index 3f9f4a9b26..5a00f134cf 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/setzer/ramstage.c b/src/mainboard/google/cyan/variants/setzer/ramstage.c index 84d2f43822..b73bb97aac 100644 --- a/src/mainboard/google/cyan/variants/setzer/ramstage.c +++ b/src/mainboard/google/cyan/variants/setzer/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/cyan/variants/setzer/romstage.c b/src/mainboard/google/cyan/variants/setzer/romstage.c index b36f09c0c9..5f400c3a4d 100644 --- a/src/mainboard/google/cyan/variants/setzer/romstage.c +++ b/src/mainboard/google/cyan/variants/setzer/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/setzer/spd_util.c b/src/mainboard/google/cyan/variants/setzer/spd_util.c index 43b57376c3..d9922d8cd1 100644 --- a/src/mainboard/google/cyan/variants/setzer/spd_util.c +++ b/src/mainboard/google/cyan/variants/setzer/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 1f484fe51d..2e16bb88c8 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl index 8c8495f540..9a5cbb94a9 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TCHG) { diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl index 49991a8435..85632bd6e4 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DPTF_CPU_PASSIVE #define DPTF_CPU_PASSIVE 80 diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl index 4ace7195d6..d9dee4ae5c 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_CPU" diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl index ad8f4de332..cf6514d7eb 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl index 09f4b6d7f8..e2c8ddcfe0 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h index 2a8ff9f294..7c53e0e39b 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/terra/ramstage.c b/src/mainboard/google/cyan/variants/terra/ramstage.c index edbe7e06ad..f7414221a7 100644 --- a/src/mainboard/google/cyan/variants/terra/ramstage.c +++ b/src/mainboard/google/cyan/variants/terra/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c index b1850c5491..8640e8c408 100644 --- a/src/mainboard/google/cyan/variants/terra/romstage.c +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/terra/spd_util.c b/src/mainboard/google/cyan/variants/terra/spd_util.c index 1483bab84a..05fbb22421 100644 --- a/src/mainboard/google/cyan/variants/terra/spd_util.c +++ b/src/mainboard/google/cyan/variants/terra/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 78d8a36d97..fc8776a334 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl index 1499545e13..7de355063c 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Charger" diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl index 8cee066038..0c5331d62b 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan touchscreen */ #include diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h index 73121a16c8..e9e73768fa 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/ultima/ramstage.c b/src/mainboard/google/cyan/variants/ultima/ramstage.c index 8ffee5ae75..20159f9972 100644 --- a/src/mainboard/google/cyan/variants/ultima/ramstage.c +++ b/src/mainboard/google/cyan/variants/ultima/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/cyan/variants/ultima/spd_util.c b/src/mainboard/google/cyan/variants/ultima/spd_util.c index ce3cf7fd87..f32b23b8a2 100644 --- a/src/mainboard/google/cyan/variants/ultima/spd_util.c +++ b/src/mainboard/google/cyan/variants/ultima/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index d96c848f6d..603e91d965 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl index 775971ac31..fcf4cf71b3 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl index 8cee066038..0c5331d62b 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan touchscreen */ #include diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h b/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h index 4be300d83e..b0161a8fed 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/cyan/variants/wizpig/spd_util.c b/src/mainboard/google/cyan/variants/wizpig/spd_util.c index f055fee423..04528a8745 100644 --- a/src/mainboard/google/cyan/variants/wizpig/spd_util.c +++ b/src/mainboard/google/cyan/variants/wizpig/spd_util.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c index 9780e0ac1c..c50a38c04d 100644 --- a/src/mainboard/google/cyan/w25q64.c +++ b/src/mainboard/google/cyan/w25q64.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From e3218a2d4ace88060dd62c84168e6165d3a6eb2f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:04 +0200 Subject: [PATCH 0854/1463] mb/google/daisy: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic650486d036d06d5df46e41826d38bb9b8e92ed1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40168 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/daisy/chromeos.c | 15 ++------------- src/mainboard/google/daisy/exynos5250.h | 15 ++------------- src/mainboard/google/daisy/mainboard.c | 15 ++------------- src/mainboard/google/daisy/memlayout.ld | 14 ++------------ src/mainboard/google/daisy/memory.c | 15 ++------------- src/mainboard/google/daisy/romstage.c | 15 ++------------- src/mainboard/google/daisy/wakeup.c | 15 ++------------- 7 files changed, 14 insertions(+), 90 deletions(-) diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index ae4da39e3d..2a91815ffd 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/daisy/exynos5250.h b/src/mainboard/google/daisy/exynos5250.h index 8fb3704751..61880d79bf 100644 --- a/src/mainboard/google/daisy/exynos5250.h +++ b/src/mainboard/google/daisy/exynos5250.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* I2C */ #define I2C_0_SPEED 100000 diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index ae6d866e5a..816e0eecbd 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/daisy/memlayout.ld b/src/mainboard/google/daisy/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/daisy/memlayout.ld +++ b/src/mainboard/google/daisy/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index 3f75fd0fb8..479c0e70aa 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index bb91d07db7..607dae12aa 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/daisy/wakeup.c b/src/mainboard/google/daisy/wakeup.c index b4af25615c..6de742f42e 100644 --- a/src/mainboard/google/daisy/wakeup.c +++ b/src/mainboard/google/daisy/wakeup.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From fb95ff8d50c5853ddd936c34536e60adfc6fc0c6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:14 +0200 Subject: [PATCH 0855/1463] mb/google/dragonegg: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2de1d93070abcfe3ee9926e5798a8a7b187c1351 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40169 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/dragonegg/bootblock.c | 15 ++------------- src/mainboard/google/dragonegg/chromeos.c | 15 ++------------- src/mainboard/google/dragonegg/dsdt.asl | 15 ++------------- src/mainboard/google/dragonegg/ec.c | 15 ++------------- src/mainboard/google/dragonegg/mainboard.c | 15 ++------------- .../google/dragonegg/romstage_fsp_params.c | 15 ++------------- src/mainboard/google/dragonegg/smihandler.c | 15 ++------------- .../google/dragonegg/variants/baseboard/gpio.c | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/dragonegg/variants/baseboard/memory.c | 15 ++------------- .../variants/dragonegg/include/variant/ec.h | 15 ++------------- .../variants/dragonegg/include/variant/gpio.h | 15 ++------------- 14 files changed, 28 insertions(+), 182 deletions(-) diff --git a/src/mainboard/google/dragonegg/bootblock.c b/src/mainboard/google/dragonegg/bootblock.c index c43ea9a503..28061399a1 100644 --- a/src/mainboard/google/dragonegg/bootblock.c +++ b/src/mainboard/google/dragonegg/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index c87b16a3d0..efa0b0d0d7 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 081fcb053a..7765ac922f 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "variant/ec.h" diff --git a/src/mainboard/google/dragonegg/ec.c b/src/mainboard/google/dragonegg/ec.c index a1f272fa16..1b6a5b8896 100644 --- a/src/mainboard/google/dragonegg/ec.c +++ b/src/mainboard/google/dragonegg/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c index 225b072c2e..0bcb7d674a 100644 --- a/src/mainboard/google/dragonegg/mainboard.c +++ b/src/mainboard/google/dragonegg/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index 0cc54d56c1..575e89dbe1 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c index 524dabaf07..5e024d823d 100644 --- a/src/mainboard/google/dragonegg/smihandler.c +++ b/src/mainboard/google/dragonegg/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c index fa27b74997..dca2379245 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c +++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h index b697b6d8bf..56ad578a2d 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h index e083789e3c..2608a3e183 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h index 6dcbd09f5a..496d988105 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c index b383805391..8b3eef52a6 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/memory.c +++ b/src/mainboard/google/dragonegg/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h index bf2a7a65a8..85fba00a43 100644 --- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h +++ b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h +++ b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ From b40546ed4bb6156f786302f2b138415de1969156 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:17 +0200 Subject: [PATCH 0856/1463] mb/google/drallion: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8bd5b9621d85dbb08996653c0f66e528f85ba0b0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40170 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/drallion/bootblock.c | 15 ++------------- src/mainboard/google/drallion/chromeos.c | 15 ++------------- src/mainboard/google/drallion/dsdt.asl | 15 ++------------- src/mainboard/google/drallion/ec.c | 15 ++------------- src/mainboard/google/drallion/hda_verb.c | 15 ++------------- src/mainboard/google/drallion/ramstage.c | 15 ++------------- src/mainboard/google/drallion/romstage.c | 15 ++------------- src/mainboard/google/drallion/smihandler.c | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/drallion/variants/drallion/gpio.c | 15 ++------------- .../drallion/include/variant/acpi/dptf.asl | 15 ++------------- .../drallion/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/drallion/include/variant/ec.h | 15 ++------------- .../variants/drallion/include/variant/gpio.h | 15 ++------------- .../variants/drallion/include/variant/hda_verb.h | 15 ++------------- .../variants/drallion/include/variant/variant.h | 15 ++------------- .../google/drallion/variants/drallion/memory.c | 15 ++------------- .../google/drallion/variants/drallion/sku.c | 15 ++------------- .../google/drallion/variants/drallion/smbios.c | 15 ++------------- 19 files changed, 38 insertions(+), 247 deletions(-) diff --git a/src/mainboard/google/drallion/bootblock.c b/src/mainboard/google/drallion/bootblock.c index 813409433b..db99e8aee7 100644 --- a/src/mainboard/google/drallion/bootblock.c +++ b/src/mainboard/google/drallion/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index b75b63017c..ee3509d01e 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index bc1eb0bd45..10a4af5e30 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/drallion/ec.c b/src/mainboard/google/drallion/ec.c index c0edf680c8..2dd13a8c17 100644 --- a/src/mainboard/google/drallion/ec.c +++ b/src/mainboard/google/drallion/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/hda_verb.c b/src/mainboard/google/drallion/hda_verb.c index 3fbc3a24c3..6a54dbddbe 100644 --- a/src/mainboard/google/drallion/hda_verb.c +++ b/src/mainboard/google/drallion/hda_verb.c @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "variant/hda_verb.h" diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 1c537d53c2..c79a4676dc 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index ef64c3d155..11b54fa062 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/smihandler.c b/src/mainboard/google/drallion/smihandler.c index 0dee122c91..325afb8e42 100644 --- a/src/mainboard/google/drallion/smihandler.c +++ b/src/mainboard/google/drallion/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h index 1058dff22f..7c3fb33b2e 100644 --- a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index fe4fd3be3f..05293f28de 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl index c078b87c04..ecf0b4d2db 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 99 #define DPTF_CPU_CRITICAL 127 diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index 225660be28..cb19926a72 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h index 7063927273..41cd78ac83 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index 98044fd47e..12cd845803 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h index f62f417074..a54faaccc9 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_HDA_VERB_H #define MAINBOARD_HDA_VERB_H diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index 74f6e5de3f..df5641ba8e 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 2509d561bb..f6d20457c2 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/variants/drallion/sku.c b/src/mainboard/google/drallion/variants/drallion/sku.c index 24f4a117ae..66d566a4b8 100644 --- a/src/mainboard/google/drallion/variants/drallion/sku.c +++ b/src/mainboard/google/drallion/variants/drallion/sku.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/drallion/variants/drallion/smbios.c b/src/mainboard/google/drallion/variants/drallion/smbios.c index 6d82af66cb..3e253bbc17 100644 --- a/src/mainboard/google/drallion/variants/drallion/smbios.c +++ b/src/mainboard/google/drallion/variants/drallion/smbios.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 9b10c098ccb0a87be6174c6c4f110f9c1dc3a5fc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:20 +0200 Subject: [PATCH 0857/1463] mb/google/eve: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5dd216564e66ba14207308a4606d53a1dd813076 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40171 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/eve/acpi/dptf.asl | 15 ++------------- src/mainboard/google/eve/bootblock.c | 15 ++------------- src/mainboard/google/eve/chromeos.c | 15 ++------------- src/mainboard/google/eve/dsdt.asl | 15 ++------------- src/mainboard/google/eve/ec.c | 15 ++------------- src/mainboard/google/eve/ec.h | 15 ++------------- src/mainboard/google/eve/gpio.h | 15 ++------------- src/mainboard/google/eve/mainboard.c | 15 ++------------- src/mainboard/google/eve/romstage.c | 15 ++------------- src/mainboard/google/eve/smihandler.c | 15 ++------------- src/mainboard/google/eve/spd/spd.c | 15 ++------------- src/mainboard/google/eve/spd/spd.h | 15 ++------------- 12 files changed, 24 insertions(+), 156 deletions(-) diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl index ecda97f598..3a6de159cf 100644 --- a/src/mainboard/google/eve/acpi/dptf.asl +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100 diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index fc60230926..54843ad3ce 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index c6b8cf37d4..30f92d85fe 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 8b07dabd53..90e8502374 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ec.h" #include "gpio.h" diff --git a/src/mainboard/google/eve/ec.c b/src/mainboard/google/eve/ec.c index 2414475e22..ec0334883a 100644 --- a/src/mainboard/google/eve/ec.c +++ b/src/mainboard/google/eve/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/eve/ec.h b/src/mainboard/google/eve/ec.h index 254a9ae0b5..661188c592 100644 --- a/src/mainboard/google/eve/ec.h +++ b/src/mainboard/google/eve/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index ca6c4152e9..5353562e5e 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 106d6ac8e6..76057b3a5d 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index d3843df2d6..5b676c23a5 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/eve/smihandler.c b/src/mainboard/google/eve/smihandler.c index d5d8a28197..94855f69a7 100644 --- a/src/mainboard/google/eve/smihandler.c +++ b/src/mainboard/google/eve/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index 5b83ce02b5..e7d358bdef 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 8e8f614d0e..5dcab1af6e 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H From 8a7d786b5b2f63f91052ae9c424b64692466099d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:24 +0200 Subject: [PATCH 0858/1463] mb/google/fizz: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I377eb446b42d9427be9884f8bea4de6cbd8addcd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40172 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/fizz/acpi/usb.asl | 15 ++------------- src/mainboard/google/fizz/bootblock.c | 15 ++------------- src/mainboard/google/fizz/chromeos.c | 15 ++------------- src/mainboard/google/fizz/dsdt.asl | 15 ++------------- src/mainboard/google/fizz/ec.c | 15 ++------------- src/mainboard/google/fizz/mainboard.c | 15 ++------------- src/mainboard/google/fizz/romstage.c | 15 ++------------- src/mainboard/google/fizz/smihandler.c | 15 ++------------- .../google/fizz/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/acpi/dptf.asl | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/fizz/variants/baseboard/nhlt.c | 15 ++------------- .../google/fizz/variants/endeavour/gpio.c | 15 ++------------- .../endeavour/include/variant/acpi/dptf.asl | 15 ++------------- .../fizz/variants/endeavour/include/variant/ec.h | 15 ++------------- .../variants/endeavour/include/variant/gpio.h | 15 ++------------- .../google/fizz/variants/endeavour/nhlt.c | 15 ++------------- .../variants/fizz/include/variant/acpi/dptf.asl | 15 ++------------- .../fizz/variants/fizz/include/variant/ec.h | 15 ++------------- .../fizz/variants/fizz/include/variant/gpio.h | 15 ++------------- src/mainboard/google/fizz/variants/karma/gpio.c | 15 ++------------- .../variants/karma/include/variant/acpi/dptf.asl | 15 ++------------- .../fizz/variants/karma/include/variant/ec.h | 15 ++------------- .../fizz/variants/karma/include/variant/gpio.h | 15 ++------------- src/mainboard/google/fizz/variants/karma/nhlt.c | 15 ++------------- .../google/fizz/variants/karma/smihandler.c | 15 ++------------- 28 files changed, 56 insertions(+), 364 deletions(-) diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl index 6712860346..949d0df768 100644 --- a/src/mainboard/google/fizz/acpi/usb.asl +++ b/src/mainboard/google/fizz/acpi/usb.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.RHUB.HS02) { diff --git a/src/mainboard/google/fizz/bootblock.c b/src/mainboard/google/fizz/bootblock.c index fe2262c1d5..00ac265162 100644 --- a/src/mainboard/google/fizz/bootblock.c +++ b/src/mainboard/google/fizz/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 7769ddc3f8..0ce78afbc5 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 0b891ced6d..542c8445dc 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/ec.c b/src/mainboard/google/fizz/ec.c index ec4ef983f2..9a1c2797d3 100644 --- a/src/mainboard/google/fizz/ec.c +++ b/src/mainboard/google/fizz/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index ef23dc5c75..daf9da4388 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 7279ad5d84..adfe040359 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c index ae8b70196a..42b12805b1 100644 --- a/src/mainboard/google/fizz/smihandler.c +++ b/src/mainboard/google/fizz/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index d094e4cb7e..29682bbc49 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl index f98047dfd6..9744525742 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 93 #define DPTF_CPU_CRITICAL 100 diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h index 1fd85b2191..80af043ab9 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h index 1778b81cbc..123f4aa5bc 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h index a1fbb83e8d..5b7d51fa60 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/fizz/variants/baseboard/nhlt.c b/src/mainboard/google/fizz/variants/baseboard/nhlt.c index 1e43c79f9e..d8a1cd524f 100644 --- a/src/mainboard/google/fizz/variants/baseboard/nhlt.c +++ b/src/mainboard/google/fizz/variants/baseboard/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 0cde4f7520..c28f95c944 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl index 7d9006a068..231ff1bb72 100644 --- a/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h index 51dffa5d34..85fba00a43 100644 --- a/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h index e37307225f..785fcaceb1 100644 --- a/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/fizz/variants/endeavour/nhlt.c b/src/mainboard/google/fizz/variants/endeavour/nhlt.c index ede8213f0b..af1ac13fcc 100644 --- a/src/mainboard/google/fizz/variants/endeavour/nhlt.c +++ b/src/mainboard/google/fizz/variants/endeavour/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl index 7d9006a068..231ff1bb72 100644 --- a/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h b/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h index 51dffa5d34..85fba00a43 100644 --- a/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h b/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 5e1ec222c9..2fcb5fb4bb 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl index 7d9006a068..231ff1bb72 100644 --- a/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/fizz/variants/karma/include/variant/ec.h b/src/mainboard/google/fizz/variants/karma/include/variant/ec.h index 51dffa5d34..85fba00a43 100644 --- a/src/mainboard/google/fizz/variants/karma/include/variant/ec.h +++ b/src/mainboard/google/fizz/variants/karma/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h b/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h +++ b/src/mainboard/google/fizz/variants/karma/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/fizz/variants/karma/nhlt.c b/src/mainboard/google/fizz/variants/karma/nhlt.c index 30e353ed71..ac3008b03b 100644 --- a/src/mainboard/google/fizz/variants/karma/nhlt.c +++ b/src/mainboard/google/fizz/variants/karma/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/fizz/variants/karma/smihandler.c b/src/mainboard/google/fizz/variants/karma/smihandler.c index aa7a5bd1c7..369795cb07 100644 --- a/src/mainboard/google/fizz/variants/karma/smihandler.c +++ b/src/mainboard/google/fizz/variants/karma/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 34b707ff6319c27751ba9e7eea79cfbc3af9a489 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:27 +0200 Subject: [PATCH 0859/1463] mb/google/foster: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: If2b94a05ccbb3bead292713719fdc914d96dbd0f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40173 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/foster/boardid.c | 15 ++------------- src/mainboard/google/foster/bootblock.c | 15 ++------------- src/mainboard/google/foster/chromeos.c | 15 ++------------- src/mainboard/google/foster/ec_dummy.c | 14 ++------------ src/mainboard/google/foster/mainboard.c | 15 ++------------- src/mainboard/google/foster/memlayout.ld | 14 ++------------ src/mainboard/google/foster/pmic.c | 15 ++------------- src/mainboard/google/foster/pmic.h | 15 ++------------- src/mainboard/google/foster/reset.c | 15 ++------------- src/mainboard/google/foster/romstage.c | 15 ++------------- src/mainboard/google/foster/sdram_configs.c | 15 ++------------- 11 files changed, 22 insertions(+), 141 deletions(-) diff --git a/src/mainboard/google/foster/boardid.c b/src/mainboard/google/foster/boardid.c index 61c2e93be6..4ae11f7b31 100644 --- a/src/mainboard/google/foster/boardid.c +++ b/src/mainboard/google/foster/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/foster/bootblock.c b/src/mainboard/google/foster/bootblock.c index 1067c91266..4214ff442e 100644 --- a/src/mainboard/google/foster/bootblock.c +++ b/src/mainboard/google/foster/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index aa9647f8aa..7f6fe69e26 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/foster/ec_dummy.c b/src/mainboard/google/foster/ec_dummy.c index d720984415..b0898db78e 100644 --- a/src/mainboard/google/foster/ec_dummy.c +++ b/src/mainboard/google/foster/ec_dummy.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Dummy CHROMEEC file to provide stub functions for vboot compilation */ diff --git a/src/mainboard/google/foster/mainboard.c b/src/mainboard/google/foster/mainboard.c index 324b014fae..20f6550675 100644 --- a/src/mainboard/google/foster/mainboard.c +++ b/src/mainboard/google/foster/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/foster/memlayout.ld b/src/mainboard/google/foster/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/foster/memlayout.ld +++ b/src/mainboard/google/foster/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 29e14ae4f7..54c0d00f6d 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/foster/pmic.h b/src/mainboard/google/foster/pmic.h index 584bb8dcc5..a150023c6a 100644 --- a/src/mainboard/google/foster/pmic.h +++ b/src/mainboard/google/foster/pmic.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ #define __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ diff --git a/src/mainboard/google/foster/reset.c b/src/mainboard/google/foster/reset.c index 305d8a3646..98de1955f3 100644 --- a/src/mainboard/google/foster/reset.c +++ b/src/mainboard/google/foster/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/foster/romstage.c b/src/mainboard/google/foster/romstage.c index e0f9a4317b..5f4fcb1296 100644 --- a/src/mainboard/google/foster/romstage.c +++ b/src/mainboard/google/foster/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/foster/sdram_configs.c b/src/mainboard/google/foster/sdram_configs.c index ca71bb78d6..7fba2caa36 100644 --- a/src/mainboard/google/foster/sdram_configs.c +++ b/src/mainboard/google/foster/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 62079a595eda8b7ad337f4c1e0dd895864881381 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:34 +0200 Subject: [PATCH 0860/1463] mb/google/glados: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3c90ef02041799954aa656924df8c07325b83431 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40175 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/glados/acpi/dptf.asl | 15 ++------------- src/mainboard/google/glados/acpi/ec.asl | 15 ++------------- src/mainboard/google/glados/acpi/mainboard.asl | 15 ++------------- src/mainboard/google/glados/acpi/superio.asl | 15 ++------------- src/mainboard/google/glados/bootblock_mainboard.c | 15 ++------------- src/mainboard/google/glados/chromeos.c | 15 ++------------- src/mainboard/google/glados/dsdt.asl | 15 ++------------- src/mainboard/google/glados/ec.c | 15 ++------------- src/mainboard/google/glados/ec.h | 15 ++------------- src/mainboard/google/glados/mainboard.c | 15 ++------------- src/mainboard/google/glados/romstage.c | 15 ++------------- src/mainboard/google/glados/smihandler.c | 15 ++------------- src/mainboard/google/glados/spd/spd.c | 15 ++------------- src/mainboard/google/glados/spd/spd.h | 15 ++------------- src/mainboard/google/glados/spd/spd_util.h | 14 ++------------ .../variants/asuka/include/variant/acpi/dptf.asl | 15 ++------------- .../glados/variants/asuka/include/variant/gpio.h | 15 ++------------- .../google/glados/variants/asuka/variant.c | 15 ++------------- .../baseboard/include/baseboard/variant.h | 15 ++------------- .../caroline/include/variant/acpi/dptf.asl | 15 ++------------- .../caroline/include/variant/acpi/mainboard.asl | 15 ++------------- .../glados/variants/caroline/include/variant/ec.h | 15 ++------------- .../variants/caroline/include/variant/gpio.h | 15 ++------------- .../google/glados/variants/caroline/variant.c | 15 ++------------- .../variants/cave/include/variant/acpi/dptf.asl | 15 ++------------- .../glados/variants/cave/include/variant/ec.h | 15 ++------------- .../glados/variants/cave/include/variant/gpio.h | 15 ++------------- .../google/glados/variants/cave/variant.c | 15 ++------------- .../variants/chell/include/variant/acpi/dptf.asl | 15 ++------------- .../chell/include/variant/acpi/mainboard.asl | 14 ++------------ .../glados/variants/chell/include/variant/ec.h | 15 ++------------- .../glados/variants/chell/include/variant/gpio.h | 15 ++------------- .../google/glados/variants/chell/variant.c | 15 ++------------- .../variants/glados/include/variant/acpi/dptf.asl | 15 ++------------- .../glados/variants/glados/include/variant/ec.h | 15 ++------------- .../glados/variants/glados/include/variant/gpio.h | 15 ++------------- .../google/glados/variants/glados/variant.c | 15 ++------------- .../variants/lars/include/variant/acpi/dptf.asl | 15 ++------------- .../glados/variants/lars/include/variant/ec.h | 15 ++------------- .../glados/variants/lars/include/variant/gpio.h | 15 ++------------- .../google/glados/variants/lars/variant.c | 15 ++------------- .../variants/sentry/include/variant/acpi/dptf.asl | 15 ++------------- .../glados/variants/sentry/include/variant/ec.h | 15 ++------------- .../glados/variants/sentry/include/variant/gpio.h | 15 ++------------- .../google/glados/variants/sentry/variant.c | 15 ++------------- 45 files changed, 90 insertions(+), 583 deletions(-) diff --git a/src/mainboard/google/glados/acpi/dptf.asl b/src/mainboard/google/glados/acpi/dptf.asl index 9a335098f9..a53368f2b8 100644 --- a/src/mainboard/google/glados/acpi/dptf.asl +++ b/src/mainboard/google/glados/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Include Variant DPTF */ #include diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl index b0dd43af70..ecd32d77f6 100644 --- a/src/mainboard/google/glados/acpi/ec.asl +++ b/src/mainboard/google/glados/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index b3e741a6d0..42a0e089bb 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Variant-specific ACPI, including USB port defs */ #include diff --git a/src/mainboard/google/glados/acpi/superio.asl b/src/mainboard/google/glados/acpi/superio.asl index bd1bbd1e4c..7a4fb6aaec 100644 --- a/src/mainboard/google/glados/acpi/superio.asl +++ b/src/mainboard/google/glados/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources diff --git a/src/mainboard/google/glados/bootblock_mainboard.c b/src/mainboard/google/glados/bootblock_mainboard.c index 6d1885ecb4..30e5174945 100644 --- a/src/mainboard/google/glados/bootblock_mainboard.c +++ b/src/mainboard/google/glados/bootblock_mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 3e9c90bc62..3b710dc4f4 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 7e3a1a2cbf..708950e044 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c index f5329db526..fdc57c5e55 100644 --- a/src/mainboard/google/glados/ec.c +++ b/src/mainboard/google/glados/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h index 21a4ade540..823d7089ae 100644 --- a/src/mainboard/google/glados/ec.h +++ b/src/mainboard/google/glados/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 4f5859972d..53f9f60098 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 4f9022b165..c72f393e41 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index 3d4d119715..1ff4e3c6d2 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 13e1dbb339..ff49cde8c8 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index c28e3caf35..0a02e0b910 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/glados/spd/spd_util.h b/src/mainboard/google/glados/spd/spd_util.h index b1e9a7a8a2..b975806231 100644 --- a/src/mainboard/google/glados/spd/spd_util.h +++ b/src/mainboard/google/glados/spd/spd_util.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SPD_UTIL_H #define SPD_UTIL_H diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl index c57935ab1c..273497902e 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 101 #define DPTF_CPU_CRITICAL 106 diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index ea04abe530..07bec37dbf 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 4312dde3e6..0def99cf77 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h index 45636acad2..27bafece2b 100644 --- a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h +++ b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef GLADOS_VARIANT_H #define GLADOS_VARIANT_H diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl index f6e1400d44..30f0314a66 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100 diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl index d4bc3507b4..72ebfb08bf 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/ec.h b/src/mainboard/google/glados/variants/caroline/include/variant/ec.h index 04894b616e..a1ad66540b 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* EC ENABLE MULTIPLE DPTF PROFILES */ #define EC_ENABLE_MULTIPLE_DPTF_PROFILES diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 1a74445b8f..223a4a5ef3 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index 5757cd15a9..a315f9e3e9 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl index 49321a65a5..924413651c 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 99 diff --git a/src/mainboard/google/glados/variants/cave/include/variant/ec.h b/src/mainboard/google/glados/variants/cave/include/variant/ec.h index dfd09fdd61..2eb7a78837 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index 2961588ec3..c3b44eefb8 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index a3a62bb9a8..00c2b51d76 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl index b3da88984b..eae05b0948 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 99 diff --git a/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl index aa465fae4f..d5f628e31b 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.RHUB.HS01) { diff --git a/src/mainboard/google/glados/variants/chell/include/variant/ec.h b/src/mainboard/google/glados/variants/chell/include/variant/ec.h index 15b68189c4..1158f2f0e4 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index da30cbdfd5..872d912c2b 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 65ad017789..0a4955ef4d 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl index 90af48b68e..50aa06edfb 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/glados/variants/glados/include/variant/ec.h b/src/mainboard/google/glados/variants/glados/include/variant/ec.h index ee4b415c66..1c458e9716 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 2d783ca5b1..a23e422d14 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index a3a62bb9a8..00c2b51d76 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl index ca776edfff..ab57de747a 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_CRITICAL 99 diff --git a/src/mainboard/google/glados/variants/lars/include/variant/ec.h b/src/mainboard/google/glados/variants/lars/include/variant/ec.h index ee4b415c66..1c458e9716 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index 1f390fc911..be03de3bbc 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index 5717484a90..5b7216c407 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl index 2e99dd9da7..bc102ba5af 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 90 #define DPTF_CPU_CRITICAL 98 diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/ec.h b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h index fe31d0e653..aee92b0c45 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/ec.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 5864469f35..399cc920cd 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 126fc1515e..b2405ca892 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 16c851fa9a937ff2190266d29bc366b14d04c169 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:38 +0200 Subject: [PATCH 0861/1463] mb/google/gru: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1d42341e9cf5e35142f9cc8e97a03e442655bc13 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40176 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/gru/board.h | 16 ++-------------- src/mainboard/google/gru/boardid.c | 15 ++------------- src/mainboard/google/gru/bootblock.c | 16 ++-------------- src/mainboard/google/gru/chromeos.c | 16 ++-------------- src/mainboard/google/gru/mainboard.c | 16 ++-------------- src/mainboard/google/gru/memlayout.ld | 15 ++------------- src/mainboard/google/gru/pwm_regulator.c | 15 ++------------- src/mainboard/google/gru/pwm_regulator.h | 15 ++------------- src/mainboard/google/gru/reset.c | 15 ++------------- src/mainboard/google/gru/romstage.c | 16 ++-------------- src/mainboard/google/gru/sdram_configs.c | 15 ++------------- .../sdram_params/sdram-lpddr3-generic-2GB-800.c | 14 ++------------ .../sdram_params/sdram-lpddr3-generic-2GB-928.c | 14 ++------------ .../sdram_params/sdram-lpddr3-generic-4GB-800.c | 14 ++------------ .../sdram_params/sdram-lpddr3-generic-4GB-928.c | 14 ++------------ 15 files changed, 30 insertions(+), 196 deletions(-) diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index c29aa51d50..afb3d21d31 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H #define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index f3cda66604..3dd9e7c3bb 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index b09542e266..0110d339bd 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 3b2711e563..fc8e5f240e 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 7d3c1a79d5..bc3fab2344 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/memlayout.ld b/src/mainboard/google/gru/memlayout.ld index 4b3e957339..eccd0c5fa1 100644 --- a/src/mainboard/google/gru/memlayout.ld +++ b/src/mainboard/google/gru/memlayout.ld @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 7f42f890e8..148ced6268 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/pwm_regulator.h b/src/mainboard/google/gru/pwm_regulator.h index 6e5160b15b..3afb9d7eef 100644 --- a/src/mainboard/google/gru/pwm_regulator.h +++ b/src/mainboard/google/gru/pwm_regulator.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H #define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c index c84e33af93..cd93609291 100644 --- a/src/mainboard/google/gru/reset.c +++ b/src/mainboard/google/gru/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index ba0c7066e4..9505d3fb12 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 176e01c847..94011ff31c 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-800.c index eb0854d59e..d777be6f5e 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-800.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-928.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-928.c index 552ebfc9b5..2795f9c9cf 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-928.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-928.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-800.c index a0b270c696..afa12e768f 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-800.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-928.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-928.c index f75e6b5bd5..2f77a1fe98 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-928.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-928.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From 4d94ae4cfb62e1165953b3966071cb59e29583db Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:31 +0200 Subject: [PATCH 0862/1463] mb/google/gale: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I34bd5147bc1763416f8c875828cd6ee5c2a465ac Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40174 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/gale/boardid.c | 15 ++------------- src/mainboard/google/gale/cdp.c | 15 ++------------- src/mainboard/google/gale/chromeos.c | 15 ++------------- src/mainboard/google/gale/mainboard.c | 15 ++------------- src/mainboard/google/gale/memlayout.ld | 14 ++------------ src/mainboard/google/gale/reset.c | 16 ++-------------- src/mainboard/google/gale/romstage.c | 15 ++------------- src/mainboard/google/gale/verstage.c | 16 ++-------------- 8 files changed, 16 insertions(+), 105 deletions(-) diff --git a/src/mainboard/google/gale/boardid.c b/src/mainboard/google/gale/boardid.c index 027346a562..d6003f6143 100644 --- a/src/mainboard/google/gale/boardid.c +++ b/src/mainboard/google/gale/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index 3f99a679bf..b0d2b0b79e 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 0c0e2ddd51..5bfd86084e 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index 0282c70e99..ff4a7c0732 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gale/memlayout.ld b/src/mainboard/google/gale/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/gale/memlayout.ld +++ b/src/mainboard/google/gale/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c index 5da2f50af9..1229221f3a 100644 --- a/src/mainboard/google/gale/reset.c +++ b/src/mainboard/google/gale/reset.c @@ -1,17 +1,5 @@ -/* - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gale/romstage.c b/src/mainboard/google/gale/romstage.c index cb5a493453..5b29a056d2 100644 --- a/src/mainboard/google/gale/romstage.c +++ b/src/mainboard/google/gale/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index d7622d6efa..cb2e8a7231 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From b6636b0ea812a88a525e6c9ae0603c31837d44c3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:41 +0200 Subject: [PATCH 0863/1463] mb/google/hatch: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: If85e246550abe323d6a2a7c6301e8e91858cbe3a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40177 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/hatch/bootblock.c | 15 ++------------- src/mainboard/google/hatch/chromeos.c | 15 ++------------- src/mainboard/google/hatch/dsdt.asl | 15 ++------------- src/mainboard/google/hatch/ec.c | 15 ++------------- src/mainboard/google/hatch/mainboard.c | 15 ++------------- src/mainboard/google/hatch/ramstage.c | 15 ++------------- src/mainboard/google/hatch/romstage_spd_cbfs.c | 15 ++------------- src/mainboard/google/hatch/romstage_spd_smbus.c | 15 ++------------- src/mainboard/google/hatch/smihandler.c | 15 ++------------- src/mainboard/google/hatch/variants/akemi/gpio.c | 15 ++------------- .../variants/akemi/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/akemi/include/variant/ec.h | 15 ++------------- .../hatch/variants/akemi/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/akemi/variant.c | 15 ++------------- .../google/hatch/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/acpi/dptf.asl | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/hatch/variants/baseboard/memory.c | 15 ++------------- .../google/hatch/variants/dratini/gpio.c | 15 ++------------- .../dratini/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/dratini/include/variant/ec.h | 15 ++------------- .../hatch/variants/dratini/include/variant/gpio.h | 15 ++------------- .../hatch/variants/dratini/include/variant/sku.h | 15 ++------------- .../google/hatch/variants/dratini/ramstage.c | 15 ++------------- .../google/hatch/variants/dratini/variant.c | 15 ++------------- src/mainboard/google/hatch/variants/hatch/gpio.c | 15 ++------------- .../variants/hatch/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/hatch/include/variant/ec.h | 15 ++------------- .../hatch/variants/hatch/include/variant/gpio.h | 15 ++------------- src/mainboard/google/hatch/variants/helios/gpio.c | 15 ++------------- .../variants/helios/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/helios/include/variant/ec.h | 15 ++------------- .../hatch/variants/helios/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/helios/memory.c | 15 ++------------- .../google/hatch/variants/helios/ramstage.c | 15 ++------------- src/mainboard/google/hatch/variants/jinlon/gpio.c | 15 ++------------- .../variants/jinlon/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/jinlon/include/variant/ec.h | 15 ++------------- .../hatch/variants/jinlon/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/jinlon/ramstage.c | 15 ++------------- .../google/hatch/variants/kindred/gpio.c | 15 ++------------- .../kindred/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/kindred/include/variant/ec.h | 15 ++------------- .../hatch/variants/kindred/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/kindred/variant.c | 15 ++------------- src/mainboard/google/hatch/variants/kohaku/gpio.c | 15 ++------------- .../variants/kohaku/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/kohaku/include/variant/ec.h | 15 ++------------- .../hatch/variants/kohaku/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/kohaku/memory.c | 15 ++------------- .../google/hatch/variants/kohaku/ramstage.c | 15 ++------------- src/mainboard/google/hatch/variants/mushu/gpio.c | 15 ++------------- .../variants/mushu/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/mushu/include/variant/ec.h | 15 ++------------- .../hatch/variants/mushu/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/nightfury/gpio.c | 15 ++------------- .../nightfury/include/variant/acpi/dptf.asl | 15 ++------------- .../hatch/variants/nightfury/include/variant/ec.h | 15 ++------------- .../variants/nightfury/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/nightfury/memory.c | 15 ++------------- .../google/hatch/variants/nightfury/ramstage.c | 15 ++------------- src/mainboard/google/hatch/variants/puff/gpio.c | 15 ++------------- .../hatch/variants/puff/include/variant/ec.h | 15 ++------------- .../hatch/variants/puff/include/variant/gpio.h | 15 ++------------- .../google/hatch/variants/puff/mainboard.c | 15 ++------------- src/mainboard/google/hatch/variants/stryke/gpio.c | 15 ++------------- .../variants/stryke/include/variant/acpi/dptf.asl | 14 ++------------ .../hatch/variants/stryke/include/variant/ec.h | 14 ++------------ .../hatch/variants/stryke/include/variant/gpio.h | 14 ++------------ .../variants/sushi/include/variant/acpi/dptf.asl | 14 ++------------ .../hatch/variants/sushi/include/variant/ec.h | 14 ++------------ .../hatch/variants/sushi/include/variant/gpio.h | 14 ++------------ 74 files changed, 148 insertions(+), 956 deletions(-) diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c index be773f260d..102b9b0adf 100644 --- a/src/mainboard/google/hatch/bootblock.c +++ b/src/mainboard/google/hatch/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 8d6cb57666..4825b05885 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 7ca266e2f9..04ce112480 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/ec.c b/src/mainboard/google/hatch/ec.c index 57241e3efd..f32f4fdf66 100644 --- a/src/mainboard/google/hatch/ec.c +++ b/src/mainboard/google/hatch/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index 17f233c7c3..73c3456eec 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 9b940b46d0..08e145cd16 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index b22ad8afb5..fc62fd0e38 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 3f91fd5916..4aa37fa6a4 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c index 51ace6d515..f743a88028 100644 --- a/src/mainboard/google/hatch/smihandler.c +++ b/src/mainboard/google/hatch/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 92041d63ff..346801433a 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl index f05d2c847d..d1e19485b5 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h index e2b5a5a94b..54877da690 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h index 99d3f6d247..ea720899c4 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 93a28042e2..5ed029ffd0 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index f149fe41e0..484057bef6 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index caa47a253d..76b2615b40 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index c904be84f8..48b473f978 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index 14e0108a1b..5fa25c157e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_GPIO_H #define BASEBOARD_GPIO_H diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 34014a30d9..5355ea2b85 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index fb4864e668..4ebff9b885 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 25ba729bb4..6d2da60e9b 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl index aa7aeafc9b..ad1167a5ad 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 90 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h index e2b5a5a94b..54877da690 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h index 99d3f6d247..ea720899c4 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h index 5766b79f12..3b9c51b836 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_SKU_H__ #define __MAINBOARD_SKU_H__ diff --git a/src/mainboard/google/hatch/variants/dratini/ramstage.c b/src/mainboard/google/hatch/variants/dratini/ramstage.c index 20ae7e35cb..8a9361c743 100644 --- a/src/mainboard/google/hatch/variants/dratini/ramstage.c +++ b/src/mainboard/google/hatch/variants/dratini/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/dratini/variant.c b/src/mainboard/google/hatch/variants/dratini/variant.c index 04a305f0eb..a779d21fb4 100644 --- a/src/mainboard/google/hatch/variants/dratini/variant.c +++ b/src/mainboard/google/hatch/variants/dratini/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 6ff3cc7395..2faf7921dc 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl index 7d9006a068..231ff1bb72 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h index e2b5a5a94b..54877da690 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h index 89e64fbe3a..d8f6d14672 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index ac0f88686f..76739c0618 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index e918718650..cf2d999e30 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 0 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/ec.h b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h index e2b5a5a94b..54877da690 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h index 99d3f6d247..ea720899c4 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/helios/memory.c b/src/mainboard/google/hatch/variants/helios/memory.c index 2a8971ecac..2ac088bfa7 100644 --- a/src/mainboard/google/hatch/variants/helios/memory.c +++ b/src/mainboard/google/hatch/variants/helios/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/helios/ramstage.c b/src/mainboard/google/hatch/variants/helios/ramstage.c index 20ae7e35cb..8a9361c743 100644 --- a/src/mainboard/google/hatch/variants/helios/ramstage.c +++ b/src/mainboard/google/hatch/variants/helios/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 2e09488078..4cf2bfd9d2 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl index 4f440e50e1..7824d11776 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 70 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h index e2b5a5a94b..54877da690 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h index 99d3f6d247..ea720899c4 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/jinlon/ramstage.c b/src/mainboard/google/hatch/variants/jinlon/ramstage.c index 20ae7e35cb..8a9361c743 100644 --- a/src/mainboard/google/hatch/variants/jinlon/ramstage.c +++ b/src/mainboard/google/hatch/variants/jinlon/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 7ce62f0daa..588e6ce1be 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl index def0df4c27..76b064ddfd 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 90 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h index e2b5a5a94b..54877da690 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h index 99d3f6d247..ea720899c4 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index ce9df8a49b..583bcff8ae 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index d98a25cdd4..8df69cb89c 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl index 756f8aacb4..894e2f0d2c 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 50 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index f17fbc1dee..7f12e95888 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h index 89e64fbe3a..d8f6d14672 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c index 4d111e2844..087a34d15d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/memory.c +++ b/src/mainboard/google/hatch/variants/kohaku/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c index 20ae7e35cb..8a9361c743 100644 --- a/src/mainboard/google/hatch/variants/kohaku/ramstage.c +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index e01d1b4d48..a7898827d7 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl index 7d9006a068..231ff1bb72 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h index e2b5a5a94b..54877da690 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h index 89e64fbe3a..d8f6d14672 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index 6c9c40e0dd..abcb1d83dd 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl index 756f8aacb4..894e2f0d2c 100644 --- a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 50 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h index f17fbc1dee..7f12e95888 100644 --- a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h index 99d3f6d247..ea720899c4 100644 --- a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/nightfury/memory.c b/src/mainboard/google/hatch/variants/nightfury/memory.c index 358982efff..25cdbb7f97 100644 --- a/src/mainboard/google/hatch/variants/nightfury/memory.c +++ b/src/mainboard/google/hatch/variants/nightfury/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c index 2201efded3..fb28259752 100644 --- a/src/mainboard/google/hatch/variants/nightfury/ramstage.c +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c index d1465fe9fa..8e4f170d4f 100644 --- a/src/mainboard/google/hatch/variants/puff/gpio.c +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 9a3c64e5b0..5e2043fe5c 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h index 40e13ebd77..6c958479fa 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index 7dcd8c756c..e8098b96ac 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 58511cae1e..0249a307d1 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl index 496334daab..231ff1bb72 100644 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h index 25269627bd..54877da690 100644 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h index 132457e5dc..ea720899c4 100644 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl index 496334daab..231ff1bb72 100644 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h b/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h index 25269627bd..54877da690 100644 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h index 3b07c1ba20..6aaeccf763 100644 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H From af4ecc24d4b28c0f4ab19351eba75b8da74628a3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:45 +0200 Subject: [PATCH 0864/1463] mb/google/jecht: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I90a3b2384797a15d5ac7f3cf9df808a5cfb1dc8c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40178 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/jecht/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/jecht/acpi/platform.asl | 15 ++------------- src/mainboard/google/jecht/acpi/superio.asl | 15 ++------------- src/mainboard/google/jecht/acpi_tables.c | 15 ++------------- src/mainboard/google/jecht/bootblock.c | 15 ++------------- src/mainboard/google/jecht/chromeos.c | 15 ++------------- src/mainboard/google/jecht/dsdt.asl | 15 ++------------- src/mainboard/google/jecht/fadt.c | 15 ++------------- src/mainboard/google/jecht/hda_verb.c | 15 ++------------- src/mainboard/google/jecht/lan.c | 15 ++------------- src/mainboard/google/jecht/led.c | 15 ++------------- src/mainboard/google/jecht/mainboard.c | 15 ++------------- src/mainboard/google/jecht/onboard.h | 15 ++------------- src/mainboard/google/jecht/romstage.c | 15 ++------------- src/mainboard/google/jecht/smihandler.c | 15 ++------------- src/mainboard/google/jecht/spd/spd.c | 15 ++------------- src/mainboard/google/jecht/spd/spd.h | 15 ++------------- src/mainboard/google/jecht/variants/guado/gpio.c | 15 ++------------- .../guado/include/variant/acpi/thermal.asl | 15 ++------------- .../variants/guado/include/variant/thermal.h | 15 ++------------- .../google/jecht/variants/guado/pei_data.c | 15 ++------------- src/mainboard/google/jecht/variants/jecht/gpio.c | 15 ++------------- .../jecht/include/variant/acpi/thermal.asl | 15 ++------------- .../variants/jecht/include/variant/thermal.h | 15 ++------------- .../google/jecht/variants/jecht/pei_data.c | 15 ++------------- src/mainboard/google/jecht/variants/rikku/gpio.c | 15 ++------------- .../rikku/include/variant/acpi/thermal.asl | 15 ++------------- .../variants/rikku/include/variant/acpi/usb.asl | 14 ++------------ .../variants/rikku/include/variant/thermal.h | 15 ++------------- .../google/jecht/variants/rikku/pei_data.c | 15 ++------------- src/mainboard/google/jecht/variants/tidus/gpio.c | 15 ++------------- .../tidus/include/variant/acpi/thermal.asl | 15 ++------------- .../variants/tidus/include/variant/thermal.h | 15 ++------------- .../google/jecht/variants/tidus/pei_data.c | 15 ++------------- 34 files changed, 68 insertions(+), 442 deletions(-) diff --git a/src/mainboard/google/jecht/acpi/mainboard.asl b/src/mainboard/google/jecht/acpi/mainboard.asl index e9ba368fde..773aa79ff3 100644 --- a/src/mainboard/google/jecht/acpi/mainboard.asl +++ b/src/mainboard/google/jecht/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/jecht/acpi/platform.asl b/src/mainboard/google/jecht/acpi/platform.asl index 665f79f968..4327e30230 100644 --- a/src/mainboard/google/jecht/acpi/platform.asl +++ b/src/mainboard/google/jecht/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/jecht/acpi/superio.asl b/src/mainboard/google/jecht/acpi/superio.asl index 623f4e63fb..afa75602f2 100644 --- a/src/mainboard/google/jecht/acpi/superio.asl +++ b/src/mainboard/google/jecht/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 937b68de13..c689c2f457 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c index 2bb93f5496..df2da1ed9d 100644 --- a/src/mainboard/google/jecht/bootblock.c +++ b/src/mainboard/google/jecht/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 6f8c7a5212..b58b35a31f 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index fc86907a33..b2ea3eb6d3 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index 6afc8e23c0..47d50d28c0 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index abb798e430..c515f115e0 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 0a9c6eaaa6..a81c3e60a9 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index 5af12b478a..0ceeb54898 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index 0c621cdbe7..2bf7802d81 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index 284ae399af..12097c15bc 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index cf8465bd48..57d36916d8 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 337cf43fff..0d47bf434e 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index c9284b4bd4..3d8758d493 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/spd/spd.h b/src/mainboard/google/jecht/spd/spd.h index d7ba63bce3..4a0fbb4ce9 100644 --- a/src/mainboard/google/jecht/spd/spd.h +++ b/src/mainboard/google/jecht/spd/spd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H diff --git a/src/mainboard/google/jecht/variants/guado/gpio.c b/src/mainboard/google/jecht/variants/guado/gpio.c index e2be9a20d6..e57f5a6f2f 100644 --- a/src/mainboard/google/jecht/variants/guado/gpio.c +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl index 0782df1bcc..7b05fda7fa 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Generated by acpigen */ External (\PPKG, MethodObj) diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h index 58f841399b..b28cae7dac 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 3908969ff7..8a0d0cd83a 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/variants/jecht/gpio.c b/src/mainboard/google/jecht/variants/jecht/gpio.c index 968bb4efb1..38fa7f77ba 100644 --- a/src/mainboard/google/jecht/variants/jecht/gpio.c +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl index 0782df1bcc..7b05fda7fa 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Generated by acpigen */ External (\PPKG, MethodObj) diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h index 350f66e932..22e3dca119 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index 3908969ff7..8a0d0cd83a 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/variants/rikku/gpio.c b/src/mainboard/google/jecht/variants/rikku/gpio.c index e2be9a20d6..e57f5a6f2f 100644 --- a/src/mainboard/google/jecht/variants/rikku/gpio.c +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl index 0782df1bcc..7b05fda7fa 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Generated by acpigen */ External (\PPKG, MethodObj) diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl index 52d7e3e648..426b3f115b 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT2) { diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h index 3266f2d5de..79cc2a2233 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index 3908969ff7..8a0d0cd83a 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/jecht/variants/tidus/gpio.c b/src/mainboard/google/jecht/variants/tidus/gpio.c index 7c4631b24a..a3da3a5a0c 100644 --- a/src/mainboard/google/jecht/variants/tidus/gpio.c +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl index 7793463f27..8c81ff19b7 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Generated by acpigen */ External (\PPKG, MethodObj) diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h index 45a3ffd629..81edc1ccfa 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 03889e5222..f0448c94c2 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 378a955d1b372c51bd2821862ba0ed36e2feecd9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:58 +0200 Subject: [PATCH 0865/1463] mb/google/trogdor: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2ba6f07aa2568c6abf20d6c92ec26bc97f4acdbb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40198 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/google/trogdor/boardid.c | 15 ++------------- src/mainboard/google/trogdor/reset.c | 15 ++------------- 2 files changed, 4 insertions(+), 26 deletions(-) diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index 2036da6b1f..9d92988362 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/trogdor/reset.c b/src/mainboard/google/trogdor/reset.c index c566e127fe..28207cd719 100644 --- a/src/mainboard/google/trogdor/reset.c +++ b/src/mainboard/google/trogdor/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From ef975087cdc8f3a262757bcc7bec7387c24a682c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:04 +0200 Subject: [PATCH 0866/1463] mb/google/mistral: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3be3f10d1f9399796f89071fb35c8e222ef93069 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40182 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/mistral/reset.c | 16 ++-------------- src/mainboard/google/mistral/verstage.c | 16 ++-------------- 2 files changed, 4 insertions(+), 28 deletions(-) diff --git a/src/mainboard/google/mistral/reset.c b/src/mainboard/google/mistral/reset.c index f3deb44306..bd11436f11 100644 --- a/src/mainboard/google/mistral/reset.c +++ b/src/mainboard/google/mistral/reset.c @@ -1,17 +1,5 @@ -/* - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c index 19d9eb3ea3..9cb59177e8 100644 --- a/src/mainboard/google/mistral/verstage.c +++ b/src/mainboard/google/mistral/verstage.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 163030bcd34222ae725e502732c9e02a84c1d168 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:07 +0200 Subject: [PATCH 0867/1463] mb/google/nyan: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Iea5f9af845fda3ffff303aed402edea8b9eb219a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40183 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/google/nyan/boardid.c | 15 ++------------- src/mainboard/google/nyan/bootblock.c | 15 ++------------- src/mainboard/google/nyan/chromeos.c | 15 ++------------- src/mainboard/google/nyan/early_configs.c | 15 ++------------- src/mainboard/google/nyan/mainboard.c | 15 ++------------- src/mainboard/google/nyan/memlayout.ld | 14 ++------------ src/mainboard/google/nyan/pmic.c | 15 ++------------- src/mainboard/google/nyan/pmic.h | 15 ++------------- src/mainboard/google/nyan/reset.c | 15 ++------------- src/mainboard/google/nyan/romstage.c | 15 ++------------- src/mainboard/google/nyan/sdram_configs.c | 15 ++------------- src/mainboard/google/nyan/sdram_configs.h | 15 ++------------- 12 files changed, 24 insertions(+), 155 deletions(-) diff --git a/src/mainboard/google/nyan/boardid.c b/src/mainboard/google/nyan/boardid.c index cf3b28173b..c74718cc36 100644 --- a/src/mainboard/google/nyan/boardid.c +++ b/src/mainboard/google/nyan/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index bb8e60ed88..61bd32664a 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index be43119df1..25022bc770 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/early_configs.c b/src/mainboard/google/nyan/early_configs.c index 61afa28472..b4fdc4e769 100644 --- a/src/mainboard/google/nyan/early_configs.c +++ b/src/mainboard/google/nyan/early_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 1022d3aedf..7bc19071cb 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/memlayout.ld b/src/mainboard/google/nyan/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/nyan/memlayout.ld +++ b/src/mainboard/google/nyan/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index 527aae3223..191b5f4101 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h index 1a95e2a9f1..4c2fd89aee 100644 --- a/src/mainboard/google/nyan/pmic.h +++ b/src/mainboard/google/nyan/pmic.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__ #define __MAINBOARD_GOOGLE_NYAN_PMIC_H__ diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c index d29514e1e7..429c68040e 100644 --- a/src/mainboard/google/nyan/reset.c +++ b/src/mainboard/google/nyan/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index d18eb3d4cf..d38a05fe6c 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c index b4a3954721..13275bf688 100644 --- a/src/mainboard/google/nyan/sdram_configs.c +++ b/src/mainboard/google/nyan/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan/sdram_configs.h b/src/mainboard/google/nyan/sdram_configs.h index 590ff9db54..2c1872c628 100644 --- a/src/mainboard/google/nyan/sdram_configs.h +++ b/src/mainboard/google/nyan/sdram_configs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ #define __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ From 8d0e929efd3b1717280b83e064b6d01c0bdc024c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:48 +0200 Subject: [PATCH 0868/1463] mb/google/smaug: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5e297e7c68d5c2646d1a086ae1a5b64fef7ed730 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40195 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/smaug/boardid.c | 15 ++------------- src/mainboard/google/smaug/bootblock.c | 15 ++------------- src/mainboard/google/smaug/chromeos.c | 15 ++------------- src/mainboard/google/smaug/gpio.h | 15 ++------------- src/mainboard/google/smaug/mainboard.c | 15 ++------------- src/mainboard/google/smaug/memlayout.ld | 14 ++------------ src/mainboard/google/smaug/pmic.c | 15 ++------------- src/mainboard/google/smaug/pmic.h | 15 ++------------- src/mainboard/google/smaug/reset.c | 15 ++------------- src/mainboard/google/smaug/romstage.c | 15 ++------------- src/mainboard/google/smaug/sdram_configs.c | 15 ++------------- 11 files changed, 22 insertions(+), 142 deletions(-) diff --git a/src/mainboard/google/smaug/boardid.c b/src/mainboard/google/smaug/boardid.c index bbff820a40..a60d335545 100644 --- a/src/mainboard/google/smaug/boardid.c +++ b/src/mainboard/google/smaug/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/smaug/bootblock.c b/src/mainboard/google/smaug/bootblock.c index c50e20c70e..ec527e4d6b 100644 --- a/src/mainboard/google/smaug/bootblock.c +++ b/src/mainboard/google/smaug/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 293f41e737..daad11694a 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/smaug/gpio.h b/src/mainboard/google/smaug/gpio.h index 01cf76dcae..332a1332dc 100644 --- a/src/mainboard/google/smaug/gpio.h +++ b/src/mainboard/google/smaug/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ #define __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 5795fda243..226a70aead 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/smaug/memlayout.ld b/src/mainboard/google/smaug/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/smaug/memlayout.ld +++ b/src/mainboard/google/smaug/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 7e128fb23b..948508e5a5 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/smaug/pmic.h b/src/mainboard/google/smaug/pmic.h index 643d714c17..fa6b4f65b9 100644 --- a/src/mainboard/google/smaug/pmic.h +++ b/src/mainboard/google/smaug/pmic.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ #define __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ diff --git a/src/mainboard/google/smaug/reset.c b/src/mainboard/google/smaug/reset.c index 2fe55ee068..dfcfaa46c6 100644 --- a/src/mainboard/google/smaug/reset.c +++ b/src/mainboard/google/smaug/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/smaug/romstage.c b/src/mainboard/google/smaug/romstage.c index 37187d835f..22c8ccc48e 100644 --- a/src/mainboard/google/smaug/romstage.c +++ b/src/mainboard/google/smaug/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/smaug/sdram_configs.c b/src/mainboard/google/smaug/sdram_configs.c index 02c871546f..58fdb008dd 100644 --- a/src/mainboard/google/smaug/sdram_configs.c +++ b/src/mainboard/google/smaug/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 57566307a886a46a2081fa620adf249bd4e499f0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:10 +0200 Subject: [PATCH 0869/1463] mb/google/nyan_big: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie6fb3a47a6ac39a435605ef6aeb30f8001c0a166 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40184 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/nyan_big/boardid.c | 15 ++------------- src/mainboard/google/nyan_big/bootblock.c | 15 ++------------- src/mainboard/google/nyan_big/chromeos.c | 15 ++------------- src/mainboard/google/nyan_big/early_configs.c | 15 ++------------- src/mainboard/google/nyan_big/mainboard.c | 15 ++------------- src/mainboard/google/nyan_big/memlayout.ld | 14 ++------------ src/mainboard/google/nyan_big/pmic.c | 15 ++------------- src/mainboard/google/nyan_big/pmic.h | 15 ++------------- src/mainboard/google/nyan_big/reset.c | 15 ++------------- src/mainboard/google/nyan_big/romstage.c | 15 ++------------- src/mainboard/google/nyan_big/sdram_configs.c | 15 ++------------- src/mainboard/google/nyan_big/sdram_configs.h | 15 ++------------- 12 files changed, 24 insertions(+), 155 deletions(-) diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index d859b3f56e..481d15de4d 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c index bb8e60ed88..61bd32664a 100644 --- a/src/mainboard/google/nyan_big/bootblock.c +++ b/src/mainboard/google/nyan_big/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index be43119df1..25022bc770 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/early_configs.c b/src/mainboard/google/nyan_big/early_configs.c index 61afa28472..b4fdc4e769 100644 --- a/src/mainboard/google/nyan_big/early_configs.c +++ b/src/mainboard/google/nyan_big/early_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 0f42309544..aae9cd5c35 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/memlayout.ld b/src/mainboard/google/nyan_big/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/nyan_big/memlayout.ld +++ b/src/mainboard/google/nyan_big/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index 0faffa5b13..915807840b 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/pmic.h b/src/mainboard/google/nyan_big/pmic.h index 2dd6a627e8..a144ff3019 100644 --- a/src/mainboard/google/nyan_big/pmic.h +++ b/src/mainboard/google/nyan_big/pmic.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__ #define __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__ diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c index d29514e1e7..429c68040e 100644 --- a/src/mainboard/google/nyan_big/reset.c +++ b/src/mainboard/google/nyan_big/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index d18eb3d4cf..d38a05fe6c 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c index e3b6da8d28..e8f547c008 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.c +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_big/sdram_configs.h b/src/mainboard/google/nyan_big/sdram_configs.h index 99e37a14a8..1172f18a1d 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.h +++ b/src/mainboard/google/nyan_big/sdram_configs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ #define __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ From c31c09fe0eb06962518793547661d3465ea98c99 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:23:01 +0200 Subject: [PATCH 0870/1463] mb/google/veyron: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I267f0f989112907f45868c1bdfd3fa117851e586 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40199 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/veyron/board.h | 15 ++------------- src/mainboard/google/veyron/boardid.c | 15 ++------------- src/mainboard/google/veyron/bootblock.c | 15 ++------------- src/mainboard/google/veyron/chromeos.c | 15 ++------------- src/mainboard/google/veyron/mainboard.c | 15 ++------------- src/mainboard/google/veyron/memlayout.ld | 14 ++------------ src/mainboard/google/veyron/reset.c | 15 ++------------- src/mainboard/google/veyron/romstage.c | 15 ++------------- src/mainboard/google/veyron/sdram_configs.c | 15 ++------------- 9 files changed, 18 insertions(+), 116 deletions(-) diff --git a/src/mainboard/google/veyron/board.h b/src/mainboard/google/veyron/board.h index 185bbbe9b7..e59de1a632 100644 --- a/src/mainboard/google/veyron/board.h +++ b/src/mainboard/google/veyron/board.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_VEYRON_BOARD_H #define __MAINBOARD_GOOGLE_VEYRON_BOARD_H diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index 6df66730a7..64c2eae22c 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index a97b5e5300..910ca6f83a 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index 957102ec09..da6d38d8ff 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index b49aedd86c..52d90a5915 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron/memlayout.ld b/src/mainboard/google/veyron/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/veyron/memlayout.ld +++ b/src/mainboard/google/veyron/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c index c84e33af93..cd93609291 100644 --- a/src/mainboard/google/veyron/reset.c +++ b/src/mainboard/google/veyron/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index cc83015006..9b1f3eafea 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 62a69c7ca7..5a274933a2 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include From 141402dfc7209a9e0d379360d00d749d687f2ae2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:16 +0200 Subject: [PATCH 0871/1463] mb/google/oak: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I46f098f38576dee14b34789c24ad5513ed47fac1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40186 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/oak/boardid.c | 15 ++------------- src/mainboard/google/oak/bootblock.c | 15 ++------------- src/mainboard/google/oak/chromeos.c | 15 ++------------- src/mainboard/google/oak/gpio.h | 15 ++------------- src/mainboard/google/oak/mainboard.c | 15 ++------------- src/mainboard/google/oak/memlayout.ld | 14 ++------------ src/mainboard/google/oak/romstage.c | 15 ++------------- src/mainboard/google/oak/sdram_configs.c | 15 ++------------- src/mainboard/google/oak/tpm_tis.c | 15 ++------------- 9 files changed, 18 insertions(+), 116 deletions(-) diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c index dc8678a10d..e36be03877 100644 --- a/src/mainboard/google/oak/boardid.c +++ b/src/mainboard/google/oak/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index a53192f89f..8f06c6c493 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index cdfe5fa545..d2fe769809 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index 6b95c63ddf..308bb37a75 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_OAK_GPIO_H__ #define __MAINBOARD_GOOGLE_OAK_GPIO_H__ diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index ae340ed650..4baa520a0b 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/oak/memlayout.ld b/src/mainboard/google/oak/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/oak/memlayout.ld +++ b/src/mainboard/google/oak/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index c3230b54ba..c429859abe 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index a8ad5d91c9..00967f6b04 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/oak/tpm_tis.c b/src/mainboard/google/oak/tpm_tis.c index 4ab14f2bd9..1eea9f90e0 100644 --- a/src/mainboard/google/oak/tpm_tis.c +++ b/src/mainboard/google/oak/tpm_tis.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From cc98db367c68a889c9b0aa8fff0ac3ffd31449fa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:27 +0200 Subject: [PATCH 0872/1463] mb/google/peach_pit: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie27b19e2a15855def11e366a86e43776ceb71083 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40189 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/peach_pit/chromeos.c | 15 ++------------- src/mainboard/google/peach_pit/mainboard.c | 15 ++------------- src/mainboard/google/peach_pit/memlayout.ld | 14 ++------------ src/mainboard/google/peach_pit/memory.c | 15 ++------------- src/mainboard/google/peach_pit/romstage.c | 15 ++------------- src/mainboard/google/peach_pit/wakeup.c | 15 ++------------- 6 files changed, 12 insertions(+), 77 deletions(-) diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index f063b25bea..bf429eb9be 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 8b1fbabfa2..99b8997121 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/peach_pit/memlayout.ld b/src/mainboard/google/peach_pit/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/peach_pit/memlayout.ld +++ b/src/mainboard/google/peach_pit/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c index d4f0d70d95..8dcce66d3a 100644 --- a/src/mainboard/google/peach_pit/memory.c +++ b/src/mainboard/google/peach_pit/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 98425f33e1..dc95e52f83 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/peach_pit/wakeup.c b/src/mainboard/google/peach_pit/wakeup.c index d8d964bf28..4051aa154d 100644 --- a/src/mainboard/google/peach_pit/wakeup.c +++ b/src/mainboard/google/peach_pit/wakeup.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 94d079ac5d204d7a4d55f1470aa5704d98d88c45 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:23:04 +0200 Subject: [PATCH 0873/1463] mb/google/veyron_mickey: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Icabeae8d5c6c8be8dc284354e1523cec04c9fe30 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40200 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/google/veyron_mickey/board.h | 15 ++------------- src/mainboard/google/veyron_mickey/boardid.c | 15 ++------------- src/mainboard/google/veyron_mickey/bootblock.c | 15 ++------------- src/mainboard/google/veyron_mickey/chromeos.c | 15 ++------------- src/mainboard/google/veyron_mickey/mainboard.c | 15 ++------------- src/mainboard/google/veyron_mickey/memlayout.ld | 14 ++------------ src/mainboard/google/veyron_mickey/reset.c | 15 ++------------- src/mainboard/google/veyron_mickey/romstage.c | 15 ++------------- .../google/veyron_mickey/sdram_configs.c | 15 ++------------- 9 files changed, 18 insertions(+), 116 deletions(-) diff --git a/src/mainboard/google/veyron_mickey/board.h b/src/mainboard/google/veyron_mickey/board.h index 2d6302e4f2..ec642f30ff 100644 --- a/src/mainboard/google/veyron_mickey/board.h +++ b/src/mainboard/google/veyron_mickey/board.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_VEYRON_MICKEY_BOARD_H #define __MAINBOARD_GOOGLE_VEYRON_MICKEY_BOARD_H diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c index 7645952c12..71c52eeb1b 100644 --- a/src/mainboard/google/veyron_mickey/boardid.c +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index 15be677fec..3d01a412fc 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 09ba0f1a85..f5ac928865 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index e081a99e88..82456fda5b 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_mickey/memlayout.ld b/src/mainboard/google/veyron_mickey/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/veyron_mickey/memlayout.ld +++ b/src/mainboard/google/veyron_mickey/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/veyron_mickey/reset.c b/src/mainboard/google/veyron_mickey/reset.c index c84e33af93..cd93609291 100644 --- a/src/mainboard/google/veyron_mickey/reset.c +++ b/src/mainboard/google/veyron_mickey/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index ab9e7e5e38..2b5ddad0d8 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 62a69c7ca7..5a274933a2 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include From 68dd0d53d639c383a717582bfa913dd9a6010502 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:13 +0200 Subject: [PATCH 0874/1463] mb/google/nyan_blaze: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie2f0dac5a0dee26b965616d410e343569588db7e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40185 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/nyan_blaze/boardid.c | 15 ++------------- src/mainboard/google/nyan_blaze/bootblock.c | 15 ++------------- src/mainboard/google/nyan_blaze/chromeos.c | 15 ++------------- src/mainboard/google/nyan_blaze/early_configs.c | 15 ++------------- src/mainboard/google/nyan_blaze/mainboard.c | 15 ++------------- src/mainboard/google/nyan_blaze/memlayout.ld | 14 ++------------ src/mainboard/google/nyan_blaze/pmic.c | 15 ++------------- src/mainboard/google/nyan_blaze/pmic.h | 15 ++------------- src/mainboard/google/nyan_blaze/reset.c | 15 ++------------- src/mainboard/google/nyan_blaze/romstage.c | 15 ++------------- src/mainboard/google/nyan_blaze/sdram_configs.c | 15 ++------------- src/mainboard/google/nyan_blaze/sdram_configs.h | 15 ++------------- 12 files changed, 24 insertions(+), 155 deletions(-) diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index d859b3f56e..481d15de4d 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/bootblock.c b/src/mainboard/google/nyan_blaze/bootblock.c index bb8e60ed88..61bd32664a 100644 --- a/src/mainboard/google/nyan_blaze/bootblock.c +++ b/src/mainboard/google/nyan_blaze/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index be43119df1..25022bc770 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/early_configs.c b/src/mainboard/google/nyan_blaze/early_configs.c index 61afa28472..b4fdc4e769 100644 --- a/src/mainboard/google/nyan_blaze/early_configs.c +++ b/src/mainboard/google/nyan_blaze/early_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index 9e2b65d361..0091a49478 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/memlayout.ld b/src/mainboard/google/nyan_blaze/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/nyan_blaze/memlayout.ld +++ b/src/mainboard/google/nyan_blaze/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index 0faffa5b13..915807840b 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/pmic.h b/src/mainboard/google/nyan_blaze/pmic.h index df8bca0eb1..bdea975b02 100644 --- a/src/mainboard/google/nyan_blaze/pmic.h +++ b/src/mainboard/google/nyan_blaze/pmic.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_NYAN_BLAZE_PMIC_H__ #define __MAINBOARD_GOOGLE_NYAN_BLAZE_PMIC_H__ diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c index d29514e1e7..429c68040e 100644 --- a/src/mainboard/google/nyan_blaze/reset.c +++ b/src/mainboard/google/nyan_blaze/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index bdc4f71b97..0b738c463a 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index 03d6cada99..0fe4dc1fb6 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.h b/src/mainboard/google/nyan_blaze/sdram_configs.h index 0bc402e735..05ade3ae61 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.h +++ b/src/mainboard/google/nyan_blaze/sdram_configs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_NYAN_BLAZE_SDRAM_CONFIG_H__ #define __MAINBOARD_GOOGLE_NYAN_BLAZE_SDRAM_CONFIG_H__ From 7caffce31f9c06ea0d4cbd07e3ea38ff57376588 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:51 +0200 Subject: [PATCH 0875/1463] mb/google/storm: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22232d098d34b9a642da157d07978b8d044926ff Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40196 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/storm/boardid.c | 15 ++------------- src/mainboard/google/storm/cdp.c | 15 ++------------- src/mainboard/google/storm/chromeos.c | 15 ++------------- src/mainboard/google/storm/mainboard.c | 15 ++------------- src/mainboard/google/storm/memlayout.ld | 14 ++------------ src/mainboard/google/storm/reset.c | 16 ++-------------- src/mainboard/google/storm/romstage.c | 15 ++------------- 7 files changed, 14 insertions(+), 91 deletions(-) diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index f2837f9319..f576a4e169 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index e59b393e36..9b5aad04b0 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index f34501cabb..89c4561b64 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0aae56e198..40026d1d71 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/storm/memlayout.ld b/src/mainboard/google/storm/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/storm/memlayout.ld +++ b/src/mainboard/google/storm/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c index f8724cfdb7..a687ca6124 100644 --- a/src/mainboard/google/storm/reset.c +++ b/src/mainboard/google/storm/reset.c @@ -1,17 +1,5 @@ -/* - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index cb5a493453..5b29a056d2 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 2e53038cf97a6383ac94b8514461d29972ec4dad Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:23:08 +0200 Subject: [PATCH 0876/1463] mb/google/veyron_rialto: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib28acdb91c5eb0c06413edfab62d6737932946f2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40201 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/google/veyron_rialto/board.h | 15 ++------------- src/mainboard/google/veyron_rialto/boardid.c | 15 ++------------- src/mainboard/google/veyron_rialto/bootblock.c | 15 ++------------- src/mainboard/google/veyron_rialto/chromeos.c | 15 ++------------- src/mainboard/google/veyron_rialto/mainboard.c | 15 ++------------- src/mainboard/google/veyron_rialto/memlayout.ld | 14 ++------------ src/mainboard/google/veyron_rialto/reset.c | 15 ++------------- src/mainboard/google/veyron_rialto/romstage.c | 15 ++------------- .../google/veyron_rialto/sdram_configs.c | 15 ++------------- .../sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc | 14 ++------------ 10 files changed, 20 insertions(+), 128 deletions(-) diff --git a/src/mainboard/google/veyron_rialto/board.h b/src/mainboard/google/veyron_rialto/board.h index ea557592eb..eafff0af7f 100644 --- a/src/mainboard/google/veyron_rialto/board.h +++ b/src/mainboard/google/veyron_rialto/board.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H #define __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c index 7645952c12..71c52eeb1b 100644 --- a/src/mainboard/google/veyron_rialto/boardid.c +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 44d1a4402d..77cf24f118 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 5d69f90ff6..fae5b4da7d 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 11e90f214b..dfebab7cfe 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_rialto/memlayout.ld b/src/mainboard/google/veyron_rialto/memlayout.ld index 2c3330651d..a6ccf155b6 100644 --- a/src/mainboard/google/veyron_rialto/memlayout.ld +++ b/src/mainboard/google/veyron_rialto/memlayout.ld @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/veyron_rialto/reset.c b/src/mainboard/google/veyron_rialto/reset.c index c84e33af93..cd93609291 100644 --- a/src/mainboard/google/veyron_rialto/reset.c +++ b/src/mainboard/google/veyron_rialto/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 2d6d0f9b67..ff94c30302 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 8393ffb81c..d34abf5832 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc index a0fe689559..5c0efe96e3 100644 --- a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ { { From e816d807b9777bf0cb7966981d744c9a5726d0ab Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:23:11 +0200 Subject: [PATCH 0877/1463] mb/google/volteer: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8e2aaf681ba3543cfcd400d21f8e94454e9b1c98 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40202 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/acpi/mipi_camera.asl | 15 ++------------- .../google/volteer/variants/ripto/gpio.c | 15 ++------------- .../volteer/variants/ripto/include/variant/ec.h | 15 ++------------- .../volteer/variants/ripto/include/variant/gpio.h | 15 ++------------- 4 files changed, 8 insertions(+), 52 deletions(-) diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/acpi/mipi_camera.asl index 7c2ca61198..9d24339c07 100644 --- a/src/mainboard/google/volteer/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/acpi/mipi_camera.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.IPU0) { diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c index 4159cb8d5b..856f7fd23d 100644 --- a/src/mainboard/google/volteer/variants/ripto/gpio.c +++ b/src/mainboard/google/volteer/variants/ripto/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h index 36cdff8e56..33e79711f6 100644 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h index 412796914a..6cd3734d6e 100644 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H From 96d93d142ea128ca52d987f47f99e22a93042c9e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:23 +0200 Subject: [PATCH 0878/1463] mb/google/parrot: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I0f41016ea678f63f386c1ae7006b7221a05f6fd9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40188 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/parrot/acpi/ec.asl | 15 ++------------- src/mainboard/google/parrot/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/parrot/acpi/platform.asl | 15 ++------------- src/mainboard/google/parrot/acpi/superio.asl | 15 ++------------- src/mainboard/google/parrot/acpi/thermal.asl | 15 ++------------- src/mainboard/google/parrot/acpi/usb.asl | 14 ++------------ src/mainboard/google/parrot/acpi_tables.c | 15 ++------------- src/mainboard/google/parrot/chromeos.c | 15 ++------------- src/mainboard/google/parrot/dsdt.asl | 15 ++------------- src/mainboard/google/parrot/early_init.c | 15 ++------------- src/mainboard/google/parrot/ec.c | 15 ++------------- src/mainboard/google/parrot/ec.h | 15 ++------------- src/mainboard/google/parrot/gpio.c | 15 ++------------- src/mainboard/google/parrot/hda_verb.c | 15 ++------------- src/mainboard/google/parrot/mainboard.c | 15 ++------------- src/mainboard/google/parrot/onboard.h | 15 ++------------- src/mainboard/google/parrot/smihandler.c | 15 ++------------- src/mainboard/google/parrot/thermal.h | 15 ++------------- 18 files changed, 36 insertions(+), 234 deletions(-) diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl index 145aeb632a..c50313a7e1 100644 --- a/src/mainboard/google/parrot/acpi/ec.asl +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index aaac6d3dc1..47fbdb9986 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/parrot/acpi/platform.asl b/src/mainboard/google/parrot/acpi/platform.asl index ee04e2fdeb..89b8a231dd 100644 --- a/src/mainboard/google/parrot/acpi/platform.asl +++ b/src/mainboard/google/parrot/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/parrot/acpi/superio.asl b/src/mainboard/google/parrot/acpi/superio.asl index cf409543e4..8257af0afc 100644 --- a/src/mainboard/google/parrot/acpi/superio.asl +++ b/src/mainboard/google/parrot/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/parrot/acpi/thermal.asl b/src/mainboard/google/parrot/acpi/thermal.asl index fa3b79ff6f..310b32de82 100644 --- a/src/mainboard/google/parrot/acpi/thermal.asl +++ b/src/mainboard/google/parrot/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/google/parrot/acpi/usb.asl b/src/mainboard/google/parrot/acpi/usb.asl index fc992db30b..42dedf24c1 100644 --- a/src/mainboard/google/parrot/acpi/usb.asl +++ b/src/mainboard/google/parrot/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.EHC1.HUB7.PRT1) { diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 731b1f432f..ed6c133a32 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index e1619d57d0..818901012b 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 73714ce20a..434a83436b 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f483984373..e42d7933b0 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index fcdfcf44e3..660d41e3f0 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h index 413de1557d..2763977b56 100644 --- a/src/mainboard/google/parrot/ec.h +++ b/src/mainboard/google/parrot/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PARROT_EC_H #define PARROT_EC_H diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c index 854d0aac0b..8ce1677a91 100644 --- a/src/mainboard/google/parrot/gpio.c +++ b/src/mainboard/google/parrot/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PARROT_GPIO_H #define PARROT_GPIO_H diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index 0c21edc51e..47980c29d6 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Parrot audio ports: diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 98939b400a..6851847dd6 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index 1ec86a2ec1..315374795d 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PARROT_ONBOARD_H #define PARROT_ONBOARD_H diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 758399e3a7..3a647b9114 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/parrot/thermal.h b/src/mainboard/google/parrot/thermal.h index f5a057de51..395ced494f 100644 --- a/src/mainboard/google/parrot/thermal.h +++ b/src/mainboard/google/parrot/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PARROT_THERMAL_H #define PARROT_THERMAL_H From feedf23de0ce02eca3f6b6f398cbe3697b89e398 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:01 +0200 Subject: [PATCH 0879/1463] mb/google/link: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Iddcf70e9a0976cfe2e5fb6d557bfcd22ab1f68cf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40181 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/google/link/acpi/ec.asl | 15 ++------------- src/mainboard/google/link/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/link/acpi/platform.asl | 15 ++------------- src/mainboard/google/link/acpi/superio.asl | 15 ++------------- src/mainboard/google/link/acpi/thermal.asl | 15 ++------------- src/mainboard/google/link/acpi_tables.c | 15 ++------------- src/mainboard/google/link/chromeos.c | 15 ++------------- src/mainboard/google/link/dsdt.asl | 15 ++------------- src/mainboard/google/link/early_init.c | 15 ++------------- src/mainboard/google/link/ec.c | 15 ++------------- src/mainboard/google/link/ec.h | 15 ++------------- src/mainboard/google/link/gpio.c | 15 ++------------- src/mainboard/google/link/hda_verb.c | 15 ++------------- src/mainboard/google/link/mainboard.c | 15 ++------------- src/mainboard/google/link/mainboard_smi.c | 15 ++------------- src/mainboard/google/link/onboard.h | 15 ++------------- src/mainboard/google/link/thermal.h | 15 ++------------- 17 files changed, 34 insertions(+), 222 deletions(-) diff --git a/src/mainboard/google/link/acpi/ec.asl b/src/mainboard/google/link/acpi/ec.asl index a8f46ec81a..ada43a6443 100644 --- a/src/mainboard/google/link/acpi/ec.asl +++ b/src/mainboard/google/link/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl index c4fb708e15..3bf243740f 100644 --- a/src/mainboard/google/link/acpi/mainboard.asl +++ b/src/mainboard/google/link/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl index 794d525d81..759f25f6d2 100644 --- a/src/mainboard/google/link/acpi/platform.asl +++ b/src/mainboard/google/link/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/link/acpi/superio.asl b/src/mainboard/google/link/acpi/superio.asl index 98edbd97ea..36d05c3842 100644 --- a/src/mainboard/google/link/acpi/superio.asl +++ b/src/mainboard/google/link/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl index abe72cd4a0..999cc4a6ac 100644 --- a/src/mainboard/google/link/acpi/thermal.asl +++ b/src/mainboard/google/link/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index b7765780cd..4f9c6aa85e 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index b6d00f9bcd..3c60c63c39 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index 2596de25ba..f75d858f2f 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index d3e9a60e0b..cf9c18f947 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 9ee98a845a..48a69ce398 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/link/ec.h b/src/mainboard/google/link/ec.h index a2755327b8..b2a88d17b5 100644 --- a/src/mainboard/google/link/ec.h +++ b/src/mainboard/google/link/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LINK_EC_H #define LINK_EC_H diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c index 212bf5b1d7..8eed084f88 100644 --- a/src/mainboard/google/link/gpio.c +++ b/src/mainboard/google/link/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LINK_GPIO_H #define LINK_GPIO_H diff --git a/src/mainboard/google/link/hda_verb.c b/src/mainboard/google/link/hda_verb.c index 302ee7224e..b4c6b33de3 100644 --- a/src/mainboard/google/link/hda_verb.c +++ b/src/mainboard/google/link/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 23ae30b85a..337807a52a 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 7dce4cbbd2..70b128b48c 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index cd673ec08c..0bd82a361e 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LINK_ONBOARD_H #define LINK_ONBOARD_H diff --git a/src/mainboard/google/link/thermal.h b/src/mainboard/google/link/thermal.h index 2b7b957918..b90d3906c2 100644 --- a/src/mainboard/google/link/thermal.h +++ b/src/mainboard/google/link/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LINK_THERMAL_H #define LINK_THERMAL_H From 952f6b0a77257045c8df12c8f9e0ace20ae1b7a2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:37 +0200 Subject: [PATCH 0880/1463] mb/google/reef: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I57e6790e49032902703ba84b68f285749aab2573 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40192 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/google/reef/bootblock.c | 15 ++------------- src/mainboard/google/reef/chromeos.c | 15 ++------------- src/mainboard/google/reef/dsdt.asl | 15 ++------------- src/mainboard/google/reef/ec.c | 15 ++------------- src/mainboard/google/reef/mainboard.c | 15 ++------------- src/mainboard/google/reef/romstage.c | 15 ++------------- src/mainboard/google/reef/smihandler.c | 15 ++------------- .../google/reef/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/acpi/dptf.asl | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/reef/variants/baseboard/memory.c | 15 ++------------- .../google/reef/variants/baseboard/nhlt.c | 15 ++------------- src/mainboard/google/reef/variants/coral/gpio.c | 15 ++------------- .../variants/coral/include/variant/acpi/dptf.asl | 15 ++------------- .../reef/variants/coral/include/variant/ec.h | 15 ++------------- .../reef/variants/coral/include/variant/gpio.h | 15 ++------------- .../google/reef/variants/coral/mainboard.c | 15 ++------------- .../variants/nasher/include/variant/acpi/dptf.asl | 15 ++------------- .../reef/variants/nasher/include/variant/ec.h | 15 ++------------- .../reef/variants/nasher/include/variant/gpio.h | 15 ++------------- .../variants/pyro/include/variant/acpi/dptf.asl | 15 ++------------- .../reef/variants/pyro/include/variant/ec.h | 15 ++------------- .../reef/variants/pyro/include/variant/gpio.h | 15 ++------------- src/mainboard/google/reef/variants/pyro/memory.c | 15 ++------------- .../variants/reef/include/variant/acpi/dptf.asl | 15 ++------------- .../reef/variants/reef/include/variant/ec.h | 15 ++------------- .../reef/variants/reef/include/variant/gpio.h | 15 ++------------- .../variants/sand/include/variant/acpi/dptf.asl | 15 ++------------- .../reef/variants/sand/include/variant/ec.h | 15 ++------------- .../reef/variants/sand/include/variant/gpio.h | 15 ++------------- .../variants/snappy/include/variant/acpi/dptf.asl | 15 ++------------- .../reef/variants/snappy/include/variant/ec.h | 15 ++------------- .../reef/variants/snappy/include/variant/gpio.h | 15 ++------------- .../google/reef/variants/snappy/mainboard.c | 15 ++------------- 36 files changed, 72 insertions(+), 468 deletions(-) diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index fe2513ba05..99d8202e43 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index c770b8cc6f..79c32e2bd7 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 294e350a71..11313f9336 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c index ddcf6093df..0a86910063 100644 --- a/src/mainboard/google/reef/ec.c +++ b/src/mainboard/google/reef/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index ec09963bb3..b17bf90c2e 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index c99b8cb20c..b6811fb572 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index 2f019cf4c1..bde2e43e5a 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 40aee4db2f..b9cf098824 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index 7e04b5b463..70847fa232 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h index 4bd3103698..77c212b11f 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_EC_H #define BASEBOARD_EC_H diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index 7fb9a7e26d..e380ce703a 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_GPIO_H #define BASEBOARD_GPIO_H diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index b93421fce4..3162892526 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index 21844d5162..4da5cbfc6d 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index f413d01237..7a0dccc1f8 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 25036f770a..3b3839ec9f 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/reef/variants/coral/include/variant/ec.h b/src/mainboard/google/reef/variants/coral/include/variant/ec.h index 4d96aec700..15a685204e 100644 --- a/src/mainboard/google/reef/variants/coral/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/coral/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/reef/variants/coral/include/variant/gpio.h b/src/mainboard/google/reef/variants/coral/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/reef/variants/coral/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/coral/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index 0e21b87c2b..983eed3e42 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl index f3723b0c40..7263428595 100644 --- a/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Use the one from baseboard for now until the real testing is done. */ #include diff --git a/src/mainboard/google/reef/variants/nasher/include/variant/ec.h b/src/mainboard/google/reef/variants/nasher/include/variant/ec.h index 1c26344731..c5bdd63884 100644 --- a/src/mainboard/google/reef/variants/nasher/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/nasher/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Use the one from baseboard for now */ #include diff --git a/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h b/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h index 28a21f0014..b936561735 100644 --- a/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/nasher/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Use the one from baseboard for now */ #include diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl index b8d5bf7454..5b805b8110 100644 --- a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c index fe4b8c5afc..60646d04db 100644 --- a/src/mainboard/google/reef/variants/pyro/memory.c +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/reef/variants/reef/include/variant/ec.h b/src/mainboard/google/reef/variants/reef/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/reef/variants/reef/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/reef/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/reef/variants/reef/include/variant/gpio.h b/src/mainboard/google/reef/variants/reef/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/reef/variants/reef/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/reef/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl index 4af1d3171a..5b97dba510 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 83 #define DPTF_CPU_CRITICAL 99 diff --git a/src/mainboard/google/reef/variants/sand/include/variant/ec.h b/src/mainboard/google/reef/variants/sand/include/variant/ec.h index cb4509f590..966e0f3fe5 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/sand/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_EC_H #define BASEBOARD_EC_H diff --git a/src/mainboard/google/reef/variants/sand/include/variant/gpio.h b/src/mainboard/google/reef/variants/sand/include/variant/gpio.h index 28a21f0014..b936561735 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/sand/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Use the one from baseboard for now */ #include diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl index 81b167955d..0b17ca14b1 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 100 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/ec.h b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h index 4d96aec700..15a685204e 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h +++ b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c index 2ce262b974..dc10d35915 100644 --- a/src/mainboard/google/reef/variants/snappy/mainboard.c +++ b/src/mainboard/google/reef/variants/snappy/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From b5a2a52beea9aa768f58d3d15f51227c008dd064 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:48 +0200 Subject: [PATCH 0881/1463] mb/google/kahlee: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I78f386eb47fc9b91992884e309dbbf33fb3d4e92 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40179 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/BiosCallOuts.c | 15 ++------------- src/mainboard/google/kahlee/OemCustomize.c | 15 ++------------- src/mainboard/google/kahlee/bootblock/bootblock.c | 15 ++------------- src/mainboard/google/kahlee/chromeos.c | 15 ++------------- src/mainboard/google/kahlee/dsdt.asl | 15 ++------------- src/mainboard/google/kahlee/ec.c | 15 ++------------- src/mainboard/google/kahlee/irq_tables.c | 15 ++------------- src/mainboard/google/kahlee/mainboard.c | 15 ++------------- src/mainboard/google/kahlee/mptable.c | 15 ++------------- src/mainboard/google/kahlee/romstage.c | 15 ++------------- src/mainboard/google/kahlee/smihandler.c | 15 ++------------- .../variants/aleena/include/variant/acpi/gpe.asl | 14 ++------------ .../aleena/include/variant/acpi/mainboard.asl | 14 ++------------ .../aleena/include/variant/acpi/routing.asl | 14 ++------------ .../aleena/include/variant/acpi/sleep.asl | 14 ++------------ .../aleena/include/variant/acpi/thermal.asl | 14 ++------------ .../kahlee/variants/aleena/include/variant/ec.h | 14 ++------------ .../kahlee/variants/aleena/include/variant/gpio.h | 15 ++------------- .../variants/aleena/include/variant/thermal.h | 15 ++------------- .../kahlee/variants/baseboard/OemCustomize.c | 15 ++------------- .../google/kahlee/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/acpi/audio.asl | 15 ++------------- .../baseboard/include/baseboard/acpi/gpe.asl | 15 ++------------- .../include/baseboard/acpi/mainboard.asl | 15 ++------------- .../baseboard/include/baseboard/acpi/routing.asl | 15 ++------------- .../baseboard/include/baseboard/acpi/sleep.asl | 15 ++------------- .../baseboard/include/baseboard/acpi/thermal.asl | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/kahlee/variants/baseboard/mainboard.c | 15 ++------------- .../google/kahlee/variants/baseboard/memory.c | 15 ++------------- .../google/kahlee/variants/baseboard/romstage.c | 15 ++------------- .../google/kahlee/variants/baseboard/tpm_tis.c | 15 ++------------- .../variants/careena/include/variant/acpi/gpe.asl | 14 ++------------ .../careena/include/variant/acpi/mainboard.asl | 14 ++------------ .../careena/include/variant/acpi/routing.asl | 14 ++------------ .../careena/include/variant/acpi/sleep.asl | 14 ++------------ .../careena/include/variant/acpi/thermal.asl | 14 ++------------ .../kahlee/variants/careena/include/variant/ec.h | 14 ++------------ .../variants/careena/include/variant/gpio.h | 15 ++------------- .../variants/careena/include/variant/thermal.h | 15 ++------------- .../variants/grunt/include/variant/acpi/gpe.asl | 15 ++------------- .../grunt/include/variant/acpi/mainboard.asl | 15 ++------------- .../grunt/include/variant/acpi/routing.asl | 15 ++------------- .../variants/grunt/include/variant/acpi/sleep.asl | 15 ++------------- .../grunt/include/variant/acpi/thermal.asl | 15 ++------------- .../kahlee/variants/grunt/include/variant/gpio.h | 15 ++------------- .../variants/grunt/include/variant/thermal.h | 15 ++------------- .../variants/liara/include/variant/acpi/gpe.asl | 14 ++------------ .../liara/include/variant/acpi/mainboard.asl | 14 ++------------ .../liara/include/variant/acpi/routing.asl | 14 ++------------ .../variants/liara/include/variant/acpi/sleep.asl | 14 ++------------ .../liara/include/variant/acpi/thermal.asl | 14 ++------------ .../kahlee/variants/liara/include/variant/ec.h | 14 ++------------ .../kahlee/variants/liara/include/variant/gpio.h | 15 ++------------- .../variants/liara/include/variant/thermal.h | 15 ++------------- .../variants/nuwani/include/variant/acpi/gpe.asl | 15 ++------------- .../nuwani/include/variant/acpi/mainboard.asl | 15 ++------------- .../nuwani/include/variant/acpi/routing.asl | 15 ++------------- .../nuwani/include/variant/acpi/sleep.asl | 15 ++------------- .../nuwani/include/variant/acpi/thermal.asl | 15 ++------------- .../kahlee/variants/nuwani/include/variant/ec.h | 15 ++------------- .../kahlee/variants/nuwani/include/variant/gpio.h | 15 ++------------- .../variants/nuwani/include/variant/thermal.h | 15 ++------------- .../google/kahlee/variants/nuwani/mainboard.c | 15 ++------------- .../variants/treeya/include/variant/acpi/gpe.asl | 15 ++------------- .../treeya/include/variant/acpi/mainboard.asl | 15 ++------------- .../treeya/include/variant/acpi/routing.asl | 15 ++------------- .../treeya/include/variant/acpi/sleep.asl | 15 ++------------- .../treeya/include/variant/acpi/thermal.asl | 15 ++------------- .../kahlee/variants/treeya/include/variant/ec.h | 15 ++------------- .../kahlee/variants/treeya/include/variant/gpio.h | 15 ++------------- .../variants/treeya/include/variant/thermal.h | 15 ++------------- .../google/kahlee/variants/treeya/mainboard.c | 15 ++------------- 75 files changed, 150 insertions(+), 957 deletions(-) diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index d9d51c9820..f9dcf26919 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index f39f946714..5715f18013 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 805793d049..613b35b41e 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index f02092883e..06ec2ec6db 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 574145f4e5..56611c5d75 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index cb4723b456..32f3d3532a 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/irq_tables.c b/src/mainboard/google/kahlee/irq_tables.c index b6dfd5d60b..34dfdae52c 100644 --- a/src/mainboard/google/kahlee/irq_tables.c +++ b/src/mainboard/google/kahlee/irq_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 968cd7ce69..24297a3861 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index 130a728483..008639a2cf 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index bfadb5c6f2..aba3ff7994 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c index a13dc6c597..078c9cda4c 100644 --- a/src/mainboard/google/kahlee/smihandler.c +++ b/src/mainboard/google/kahlee/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl index 05cd0b97f5..a6b622df78 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl index d026e9af76..304b4f0678 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl index c1896c37e5..ee9fd82e25 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl index a401b3a24d..998ee6f301 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl index a7e511cbec..597335ec70 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h index 0aa2e213bb..201305df2b 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h index b9f1e45c25..37d619d8cd 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h index b04194fb52..4cc9eb18bb 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index ab128c556b..9fccc6df6b 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index f21a97f845..4fb60b1fcf 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 0084325102..75b61c2d84 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl index c2be6f320e..e7b777df2c 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_GPE) { diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl index c118337c04..168bf566b8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Memory related values */ Name (LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl index fd760f4686..f989bbb6d8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl index 2dbefb9931..9540f3c6f6 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Wake status package */ Name (WKST, Package() { Zero, Zero }) diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl index 54b7d4e4d4..efde141f73 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h index 2d8d348df1..dcc6ac57bf 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h index f1de4abe80..7893a54155 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 348f24f9b1..02d413f6a6 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 95cbd911e0..fab813f08f 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 23d0f7974b..0e54445e67 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/romstage.c b/src/mainboard/google/kahlee/variants/baseboard/romstage.c index cbb4d3054d..0ef0c52547 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/romstage.c +++ b/src/mainboard/google/kahlee/variants/baseboard/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c index b3c6fd5450..df685f3719 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl index 05cd0b97f5..a6b622df78 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl index d026e9af76..304b4f0678 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl index c1896c37e5..ee9fd82e25 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl index a401b3a24d..998ee6f301 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl index a7e511cbec..597335ec70 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/ec.h b/src/mainboard/google/kahlee/variants/careena/include/variant/ec.h index e90724ef52..621ac68c50 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/ec.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h index bc01d14833..4884fc0cbb 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h index b04194fb52..4cc9eb18bb 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl index 750254f4ad..a6b622df78 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl index 01d015c89e..304b4f0678 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl index 95b37951c2..ee9fd82e25 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl index ca791f011e..998ee6f301 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl index cf0aee679f..597335ec70 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h index bc01d14833..4884fc0cbb 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h index b04194fb52..4cc9eb18bb 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl index 05cd0b97f5..a6b622df78 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl index d026e9af76..304b4f0678 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl index c1896c37e5..ee9fd82e25 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl index a401b3a24d..998ee6f301 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl index a7e511cbec..597335ec70 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl @@ -1,14 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/ec.h b/src/mainboard/google/kahlee/variants/liara/include/variant/ec.h index e90724ef52..621ac68c50 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/ec.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h index bc01d14833..4884fc0cbb 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h index b04194fb52..4cc9eb18bb 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl index 750254f4ad..a6b622df78 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl index 01d015c89e..304b4f0678 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl index 95b37951c2..ee9fd82e25 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl index ca791f011e..998ee6f301 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl index cf0aee679f..597335ec70 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h index 89c53be8f1..d6a7fb1200 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h index b9f1e45c25..37d619d8cd 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h index b04194fb52..4cc9eb18bb 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c index cf10d8f2dd..f54b0dbc23 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c +++ b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl index 750254f4ad..a6b622df78 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl index 01d015c89e..304b4f0678 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl index 95b37951c2..ee9fd82e25 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl index ca791f011e..998ee6f301 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl index cf0aee679f..597335ec70 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h index 89c53be8f1..d6a7fb1200 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h index b9f1e45c25..37d619d8cd 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h index b04194fb52..4cc9eb18bb 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c index cf10d8f2dd..f54b0dbc23 100644 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 11ba353806a04c31cd1c638f06c9d4e1c268e213 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:21:58 +0200 Subject: [PATCH 0882/1463] mb/google/kukui: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I377ee2c9dfa3113f88237bd6ea79031a79f18ad5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40180 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/kukui/boardid.c | 15 ++------------- src/mainboard/google/kukui/bootblock.c | 15 ++------------- src/mainboard/google/kukui/chromeos.c | 15 ++------------- src/mainboard/google/kukui/early_init.c | 15 ++------------- src/mainboard/google/kukui/early_init.h | 15 ++------------- src/mainboard/google/kukui/gpio.h | 15 ++------------- src/mainboard/google/kukui/mainboard.c | 15 ++------------- src/mainboard/google/kukui/memlayout.ld | 15 ++------------- src/mainboard/google/kukui/panel.h | 15 ++------------- src/mainboard/google/kukui/panel_anx7625.c | 15 ++------------- src/mainboard/google/kukui/panel_flapjack.c | 15 ++------------- src/mainboard/google/kukui/panel_kakadu.c | 15 ++------------- src/mainboard/google/kukui/panel_kodama.c | 15 ++------------- src/mainboard/google/kukui/panel_krane.c | 15 ++------------- src/mainboard/google/kukui/panel_kukui.c | 15 ++------------- .../kukui/panel_params/panel-AUO_B101UAN08_3.c | 15 ++------------- .../kukui/panel_params/panel-AUO_KD101N80_45NA.c | 15 ++------------- .../kukui/panel_params/panel-AUO_NT51021D8P.c | 15 ++------------- .../kukui/panel_params/panel-BOE_TV080WUM_NG0.c | 15 ++------------- .../kukui/panel_params/panel-BOE_TV101WUM_N53.c | 15 ++------------- .../kukui/panel_params/panel-BOE_TV101WUM_NG0.c | 15 ++------------- .../kukui/panel_params/panel-BOE_TV101WUM_NL6.c | 15 ++------------- .../kukui/panel_params/panel-BOE_TV105WUM_NW0.c | 15 ++------------- .../panel_params/panel-CMN_P097PFG_SSD2858.c | 15 ++------------- .../kukui/panel_params/panel-INX_OTA7290D10P.c | 15 ++------------- src/mainboard/google/kukui/panel_ps8640.c | 15 ++------------- src/mainboard/google/kukui/reset.c | 15 ++------------- src/mainboard/google/kukui/romstage.c | 15 ++------------- src/mainboard/google/kukui/sdram_configs.c | 15 ++------------- .../sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c | 15 ++------------- .../sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c | 15 ++------------- .../sdram-lpddr4x-KMDH6001DA-B422-4GB.c | 15 ++------------- .../sdram-lpddr4x-KMDP6001DA-B425-4GB.c | 15 ++------------- .../sdram-lpddr4x-KMDV6001DA-B620-4GB.c | 15 ++------------- .../sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c | 15 ++------------- .../sdram-lpddr4x-MT53E1G32D4NQ-4GB.c | 15 ++------------- .../sdram-lpddr4x-SDADA4CR-128G-4GB.c | 15 ++------------- src/mainboard/google/kukui/verstage.c | 15 ++------------- 38 files changed, 76 insertions(+), 494 deletions(-) diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 1b610ed333..e619ca5ab9 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 38eb1d757b..0acbfd1272 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 240a0cf571..2883bb035b 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index 4d257f2418..f4a30a4b54 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/early_init.h b/src/mainboard/google/kukui/early_init.h index 3ec00f35d8..0260eeaa95 100644 --- a/src/mainboard/google/kukui/early_init.h +++ b/src/mainboard/google/kukui/early_init.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_KUKUI_EARLY_INIT_H__ #define __MAINBOARD_GOOGLE_KUKUI_EARLY_INIT_H__ diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index 72d72d7022..f03f0f93cb 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_KUKUI_GPIO_H__ #define __MAINBOARD_GOOGLE_KUKUI_GPIO_H__ diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 5bf9121821..bb36d90e3d 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/memlayout.ld b/src/mainboard/google/kukui/memlayout.ld index 9572a5ef8f..a6ccf155b6 100644 --- a/src/mainboard/google/kukui/memlayout.ld +++ b/src/mainboard/google/kukui/memlayout.ld @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/panel.h b/src/mainboard/google/kukui/panel.h index 5f073e7c47..110c474ef0 100644 --- a/src/mainboard/google/kukui/panel.h +++ b/src/mainboard/google/kukui/panel.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ #define __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index 8a7889806f..c75f260e17 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/panel_flapjack.c b/src/mainboard/google/kukui/panel_flapjack.c index ce668e7769..84ef37f563 100644 --- a/src/mainboard/google/kukui/panel_flapjack.c +++ b/src/mainboard/google/kukui/panel_flapjack.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "panel.h" diff --git a/src/mainboard/google/kukui/panel_kakadu.c b/src/mainboard/google/kukui/panel_kakadu.c index 08b9c228e9..03f8db1588 100644 --- a/src/mainboard/google/kukui/panel_kakadu.c +++ b/src/mainboard/google/kukui/panel_kakadu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "panel.h" diff --git a/src/mainboard/google/kukui/panel_kodama.c b/src/mainboard/google/kukui/panel_kodama.c index c18ee74ff0..e2d611e691 100644 --- a/src/mainboard/google/kukui/panel_kodama.c +++ b/src/mainboard/google/kukui/panel_kodama.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "panel.h" diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c index ba30505deb..e4e05a33a1 100644 --- a/src/mainboard/google/kukui/panel_krane.c +++ b/src/mainboard/google/kukui/panel_krane.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "panel.h" diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c index 4162326c75..7acce0bdad 100644 --- a/src/mainboard/google/kukui/panel_kukui.c +++ b/src/mainboard/google/kukui/panel_kukui.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c b/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c index ed9026a52b..cb1d66aaa1 100644 --- a/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c b/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c index 7c8e251b7d..3028fa50d8 100644 --- a/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c b/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c index f9b5b5443f..8d9f9f6016 100644 --- a/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c +++ b/src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c index e096e161ba..240fe4817c 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c index 0ec9534a5e..c6c7965a40 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c index 8a54d07e49..842cdbffd0 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c index dea16ef82a..91d007a1a2 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c index 8d09a9641a..365414acb3 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c b/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c index f17cfbf9f9..a3442cdfaf 100644 --- a/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c +++ b/src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c b/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c index a615481198..235880d979 100644 --- a/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c +++ b/src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../panel.h" diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c index 5d8fe0caec..43ea68e0cf 100644 --- a/src/mainboard/google/kukui/panel_ps8640.c +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/reset.c b/src/mainboard/google/kukui/reset.c index a13007b2ce..ad884ebe30 100644 --- a/src/mainboard/google/kukui/reset.c +++ b/src/mainboard/google/kukui/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index aae4529529..a4b240c99f 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 5ed10958b4..73bd2f83fa 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index 8ff616be0b..6b53bcc952 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 91706de19c..74b642d4e6 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index 8b200546ec..5617ff991f 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 0a239a8cd1..fc31a18ffc 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 2090904365..df37f1aa37 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 1f210e7dfe..a5764d26c3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 49a93c101f..97a8e2d73d 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index 80c5c5188d..2de4be02a7 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/kukui/verstage.c b/src/mainboard/google/kukui/verstage.c index fa46fcab9e..88c3928a6c 100644 --- a/src/mainboard/google/kukui/verstage.c +++ b/src/mainboard/google/kukui/verstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From d9d1d20c9705d5baf0d33393f1278a439b0cd493 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:41 +0200 Subject: [PATCH 0883/1463] mb/google/sarien: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ia64c49aed694eac1f98d176c646a60597c8ae66a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40193 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/sarien/bootblock.c | 15 ++------------- src/mainboard/google/sarien/chromeos.c | 15 ++------------- src/mainboard/google/sarien/dsdt.asl | 15 ++------------- src/mainboard/google/sarien/ec.c | 15 ++------------- src/mainboard/google/sarien/hda_verb.c | 15 ++------------- src/mainboard/google/sarien/ramstage.c | 15 ++------------- src/mainboard/google/sarien/romstage.c | 15 ++------------- src/mainboard/google/sarien/sku.c | 15 ++------------- src/mainboard/google/sarien/smihandler.c | 15 ++------------- .../google/sarien/variants/arcada/gpio.c | 15 ++------------- .../variants/arcada/include/variant/acpi/dptf.asl | 15 ++------------- .../arcada/include/variant/acpi/mainboard.asl | 15 ++------------- .../sarien/variants/arcada/include/variant/ec.h | 15 ++------------- .../sarien/variants/arcada/include/variant/gpio.h | 15 ++------------- .../variants/arcada/include/variant/hda_verb.h | 15 ++------------- .../variants/arcada/include/variant/variant.h | 15 ++------------- .../google/sarien/variants/sarien/gpio.c | 15 ++------------- .../variants/sarien/include/variant/acpi/dptf.asl | 15 ++------------- .../sarien/include/variant/acpi/mainboard.asl | 15 ++------------- .../sarien/variants/sarien/include/variant/ec.h | 15 ++------------- .../sarien/variants/sarien/include/variant/gpio.h | 15 ++------------- .../variants/sarien/include/variant/hda_verb.h | 15 ++------------- .../variants/sarien/include/variant/variant.h | 15 ++------------- 23 files changed, 46 insertions(+), 299 deletions(-) diff --git a/src/mainboard/google/sarien/bootblock.c b/src/mainboard/google/sarien/bootblock.c index 813409433b..db99e8aee7 100644 --- a/src/mainboard/google/sarien/bootblock.c +++ b/src/mainboard/google/sarien/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 2c8dbca844..e64bb73d0b 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 2b35bda27a..25a10d8343 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/sarien/ec.c b/src/mainboard/google/sarien/ec.c index c0edf680c8..2dd13a8c17 100644 --- a/src/mainboard/google/sarien/ec.c +++ b/src/mainboard/google/sarien/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/hda_verb.c b/src/mainboard/google/sarien/hda_verb.c index 3fbc3a24c3..6a54dbddbe 100644 --- a/src/mainboard/google/sarien/hda_verb.c +++ b/src/mainboard/google/sarien/hda_verb.c @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "variant/hda_verb.h" diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 6676e911c7..0b2d51b2af 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index eefe295df2..0b5eb8deb4 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/sku.c b/src/mainboard/google/sarien/sku.c index d47dc82e51..075a9e305d 100644 --- a/src/mainboard/google/sarien/sku.c +++ b/src/mainboard/google/sarien/sku.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/smihandler.c b/src/mainboard/google/sarien/smihandler.c index 0dee122c91..325afb8e42 100644 --- a/src/mainboard/google/sarien/smihandler.c +++ b/src/mainboard/google/sarien/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 2cf52a1fee..5c9d8ce192 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 9be278631c..8ca1b68c17 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 98 #define DPTF_CPU_CRITICAL 108 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index ba3dd00918..bbec2dadc2 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h index 49e455a659..7bec533b46 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h index 97fe7823ff..6c52c733db 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h index f62f417074..a54faaccc9 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_HDA_VERB_H #define MAINBOARD_HDA_VERB_H diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h index 3170a47342..882bec623e 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index aac4055355..60d259d11d 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 7b94a216e4..f0ce46b90c 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 99 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index ba3dd00918..bbec2dadc2 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h index 49e455a659..7bec533b46 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h index 97fe7823ff..6c52c733db 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h index baf7192c62..1281656851 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_HDA_VERB_H #define MAINBOARD_HDA_VERB_H diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h index 42d4b938c6..78826c8847 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H From 2e8a4b04982b27e5fd5066342d65340579b3cba6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:54 +0200 Subject: [PATCH 0884/1463] mb/google/stout: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic3314eb6137a6fc9fa1f90685f37223ca1580cb9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40197 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/stout/acpi/ec.asl | 15 ++------------- src/mainboard/google/stout/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/stout/acpi/platform.asl | 15 ++------------- src/mainboard/google/stout/acpi/superio.asl | 15 ++------------- src/mainboard/google/stout/acpi/thermal.asl | 15 ++------------- src/mainboard/google/stout/acpi_tables.c | 15 ++------------- src/mainboard/google/stout/chromeos.c | 15 ++------------- src/mainboard/google/stout/dsdt.asl | 15 ++------------- src/mainboard/google/stout/early_init.c | 15 ++------------- src/mainboard/google/stout/ec.c | 15 ++------------- src/mainboard/google/stout/ec.h | 15 ++------------- src/mainboard/google/stout/gpio.c | 15 ++------------- src/mainboard/google/stout/hda_verb.c | 15 ++------------- src/mainboard/google/stout/mainboard.c | 15 ++------------- src/mainboard/google/stout/mainboard_smi.c | 15 ++------------- src/mainboard/google/stout/onboard.h | 15 ++------------- src/mainboard/google/stout/thermal.h | 15 ++------------- 17 files changed, 34 insertions(+), 222 deletions(-) diff --git a/src/mainboard/google/stout/acpi/ec.asl b/src/mainboard/google/stout/acpi/ec.asl index c3db9e6aea..2936c34912 100644 --- a/src/mainboard/google/stout/acpi/ec.asl +++ b/src/mainboard/google/stout/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/stout/acpi/mainboard.asl b/src/mainboard/google/stout/acpi/mainboard.asl index ff7ff92852..3d93c3e8d4 100644 --- a/src/mainboard/google/stout/acpi/mainboard.asl +++ b/src/mainboard/google/stout/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/mainboard/google/stout/acpi/platform.asl b/src/mainboard/google/stout/acpi/platform.asl index 757558e1dc..c21557b040 100644 --- a/src/mainboard/google/stout/acpi/platform.asl +++ b/src/mainboard/google/stout/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/stout/acpi/superio.asl b/src/mainboard/google/stout/acpi/superio.asl index b9709a9539..54d60dab29 100644 --- a/src/mainboard/google/stout/acpi/superio.asl +++ b/src/mainboard/google/stout/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/stout/acpi/thermal.asl b/src/mainboard/google/stout/acpi/thermal.asl index 3e826340e1..5091cc1caa 100644 --- a/src/mainboard/google/stout/acpi/thermal.asl +++ b/src/mainboard/google/stout/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 6e28ca3678..94d7803fa0 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 4c39b54ce4..71d7df5685 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 1a91515b24..49891c3470 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 2742ded5ad..bbac23871a 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index ac2fea011f..8a6cf8f6be 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h index f90dd7913c..7212c84a86 100644 --- a/src/mainboard/google/stout/ec.h +++ b/src/mainboard/google/stout/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef STOUT_EC_H #define STOUT_EC_H diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c index 9849fdf4e9..5e7261c835 100644 --- a/src/mainboard/google/stout/gpio.c +++ b/src/mainboard/google/stout/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef STOUT_GPIO_H #define STOUT_GPIO_H diff --git a/src/mainboard/google/stout/hda_verb.c b/src/mainboard/google/stout/hda_verb.c index 485a6dde9f..9b4830cbd6 100644 --- a/src/mainboard/google/stout/hda_verb.c +++ b/src/mainboard/google/stout/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index b411763c75..6f0444f7ba 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 43df830945..9190498913 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index b88d3a452d..06c373687b 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef STOUT_ONBOARD_H #define STOUT_ONBOARD_H diff --git a/src/mainboard/google/stout/thermal.h b/src/mainboard/google/stout/thermal.h index 11336091ad..21879a8245 100644 --- a/src/mainboard/google/stout/thermal.h +++ b/src/mainboard/google/stout/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef STOUT_THERMAL_H #define STOUT_THERMAL_H From 08b5280c9fc59a77357a746de714a6e872a664e9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:20 +0200 Subject: [PATCH 0885/1463] mb/google/octopus: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8076155330100982de82d410b6579ac99ed89e7b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40187 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/bootblock.c | 15 ++------------- src/mainboard/google/octopus/chromeos.c | 15 ++------------- src/mainboard/google/octopus/dsdt.asl | 15 ++------------- src/mainboard/google/octopus/ec.c | 15 ++------------- src/mainboard/google/octopus/mainboard.c | 15 ++------------- src/mainboard/google/octopus/romstage.c | 15 ++------------- src/mainboard/google/octopus/smihandler.c | 15 ++------------- .../google/octopus/variants/ampton/gpio.c | 15 ++------------- .../variants/ampton/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/ampton/include/variant/ec.h | 15 ++------------- .../variants/ampton/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/acpi/dptf.asl | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/octopus/variants/baseboard/memory.c | 15 ++------------- .../google/octopus/variants/baseboard/nhlt.c | 15 ++------------- .../google/octopus/variants/bloog/gpio.c | 15 ++------------- .../variants/bloog/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/bloog/include/variant/ec.h | 15 ++------------- .../octopus/variants/bloog/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/bloog/variant.c | 15 ++------------- .../google/octopus/variants/bobba/gpio.c | 15 ++------------- .../variants/bobba/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/bobba/include/variant/ec.h | 15 ++------------- .../octopus/variants/bobba/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/bobba/variant.c | 15 ++------------- .../google/octopus/variants/casta/gpio.c | 15 ++------------- .../variants/casta/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/casta/include/variant/ec.h | 15 ++------------- .../octopus/variants/casta/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/casta/variant.c | 15 ++------------- src/mainboard/google/octopus/variants/dood/gpio.c | 15 ++------------- .../variants/dood/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/dood/include/variant/ec.h | 15 ++------------- .../octopus/variants/dood/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/dood/variant.c | 15 ++------------- .../google/octopus/variants/fleex/gpio.c | 15 ++------------- .../variants/fleex/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/fleex/include/variant/ec.h | 15 ++------------- .../octopus/variants/fleex/include/variant/gpio.h | 15 ++------------- src/mainboard/google/octopus/variants/foob/gpio.c | 15 ++------------- .../variants/foob/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/foob/include/variant/ec.h | 15 ++------------- .../octopus/variants/foob/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/foob/variant.c | 15 ++------------- src/mainboard/google/octopus/variants/garg/gpio.c | 15 ++------------- .../variants/garg/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/garg/include/variant/ec.h | 15 ++------------- .../octopus/variants/garg/include/variant/gpio.h | 15 ++------------- .../octopus/variants/garg/include/variant/sku.h | 15 ++------------- .../google/octopus/variants/garg/variant.c | 15 ++------------- src/mainboard/google/octopus/variants/lick/gpio.c | 15 ++------------- .../variants/lick/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/lick/include/variant/ec.h | 15 ++------------- .../octopus/variants/lick/include/variant/gpio.h | 15 ++------------- src/mainboard/google/octopus/variants/meep/gpio.c | 15 ++------------- .../variants/meep/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/meep/include/variant/ec.h | 15 ++------------- .../octopus/variants/meep/include/variant/gpio.h | 15 ++------------- .../octopus/variants/meep/include/variant/sku.h | 15 ++------------- .../google/octopus/variants/meep/variant.c | 15 ++------------- .../octopus/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/octopus/include/variant/ec.h | 15 ++------------- .../variants/octopus/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/phaser/gpio.c | 15 ++------------- .../variants/phaser/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/phaser/include/variant/ec.h | 15 ++------------- .../variants/phaser/include/variant/gpio.h | 15 ++------------- .../google/octopus/variants/phaser/mainboard.c | 15 ++------------- .../google/octopus/variants/phaser/variant.c | 15 ++------------- src/mainboard/google/octopus/variants/yorp/gpio.c | 15 ++------------- .../variants/yorp/include/variant/acpi/dptf.asl | 15 ++------------- .../octopus/variants/yorp/include/variant/ec.h | 15 ++------------- .../octopus/variants/yorp/include/variant/gpio.h | 15 ++------------- 76 files changed, 152 insertions(+), 988 deletions(-) diff --git a/src/mainboard/google/octopus/bootblock.c b/src/mainboard/google/octopus/bootblock.c index 5f1b34e829..dd7cf2936f 100644 --- a/src/mainboard/google/octopus/bootblock.c +++ b/src/mainboard/google/octopus/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 9fd0d02ff3..f408bea792 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index 294e350a71..11313f9336 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/ec.c b/src/mainboard/google/octopus/ec.c index 17b7418739..18d6b91c4e 100644 --- a/src/mainboard/google/octopus/ec.c +++ b/src/mainboard/google/octopus/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 7b73b9d1be..e0040f3fb2 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index 4fcfd21764..733a1228c4 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index aa7b04d979..7ab8d2d132 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c index bf02cc6f28..a76086a765 100644 --- a/src/mainboard/google/octopus/variants/ampton/gpio.c +++ b/src/mainboard/google/octopus/variants/ampton/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h index 2183187b61..306b3c52a5 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h index c2f559210c..d20049727a 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 1a40eb531a..228fdbcbeb 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl index 7d504bdc97..d08f8f9cd8 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Below values might change after Thermal Tuning. */ #define DPTF_CPU_PASSIVE 90 diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index 73d7a4ee80..21287b2156 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_EC_H #define BASEBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h index de3e11f253..63dd484b44 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_GPIO_H #define BASEBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 8bcb5a920a..29da19f509 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index 990872ece7..d1244e4730 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index 8d6542bf1c..aafd4ec555 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c index 716344f698..5f6b31413e 100644 --- a/src/mainboard/google/octopus/variants/bloog/gpio.c +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h b/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h index 4d96aec700..15a685204e 100644 --- a/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h b/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 98879504fc..978314b5a1 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 5500d7dd47..3787f28bed 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h index 4d96aec700..15a685204e 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h b/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index d1b66ea5fa..57b706795d 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index c0d6feb05b..0a5922eadd 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/ec.h b/src/mainboard/google/octopus/variants/casta/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/casta/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h b/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/casta/variant.c b/src/mainboard/google/octopus/variants/casta/variant.c index 90a8e524af..5f5c719b4e 100644 --- a/src/mainboard/google/octopus/variants/casta/variant.c +++ b/src/mainboard/google/octopus/variants/casta/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 96050cd293..41195f0412 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/ec.h b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/dood/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e22c2e4657..4501f6c08f 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 6a0e1e8b32..ab35c72ed5 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl index 93b60a3736..05a678cae5 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 100 #define DPTF_CPU_CRITICAL 127 diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h b/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/foob/gpio.c b/src/mainboard/google/octopus/variants/foob/gpio.c index 0fc034a9a6..611898df58 100644 --- a/src/mainboard/google/octopus/variants/foob/gpio.c +++ b/src/mainboard/google/octopus/variants/foob/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/ec.h b/src/mainboard/google/octopus/variants/foob/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/foob/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/foob/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h b/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/foob/variant.c b/src/mainboard/google/octopus/variants/foob/variant.c index e5fd0679e3..c58fec3568 100644 --- a/src/mainboard/google/octopus/variants/foob/variant.c +++ b/src/mainboard/google/octopus/variants/foob/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 9da8ace50d..0fc0487a59 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/ec.h b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h index 4d96aec700..15a685204e 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index 72acceba78..bfe7615195 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_SKU_H__ #define __MAINBOARD_SKU_H__ diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 55dcff7866..29796b76d6 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c index c74a74464a..adacc8f005 100644 --- a/src/mainboard/google/octopus/variants/lick/gpio.c +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 59497e4f42..44a8a4763f 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h index 4d96aec700..15a685204e 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h index 269152d2f3..26a03eeebf 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_SKU_H__ #define __MAINBOARD_SKU_H__ diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index ed46885dc9..2b0bfa8072 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h b/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h b/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 4d1678d2fb..03d8329707 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h b/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/octopus/variants/phaser/mainboard.c b/src/mainboard/google/octopus/variants/phaser/mainboard.c index 2239aa2eb8..4ea96d4ec4 100644 --- a/src/mainboard/google/octopus/variants/phaser/mainboard.c +++ b/src/mainboard/google/octopus/variants/phaser/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/phaser/variant.c b/src/mainboard/google/octopus/variants/phaser/variant.c index ef06106c30..39a4876e61 100644 --- a/src/mainboard/google/octopus/variants/phaser/variant.c +++ b/src/mainboard/google/octopus/variants/phaser/variant.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index ffc7e4a63f..775811ba01 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl index 2e6e9feadf..231ff1bb72 100644 --- a/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h b/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h index 87f03b1ece..52e5f622c1 100644 --- a/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h b/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h index 3777fed07b..e6df66b293 100644 --- a/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H From d28443e5c63c128f0247149f2219b82725283880 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:44 +0200 Subject: [PATCH 0886/1463] mb/google/slippy: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I74fd273aff05e6635d4964f3614c2f1dd5562b4b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40194 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/slippy/acpi/ec.asl | 15 ++------------- src/mainboard/google/slippy/acpi/mainboard.asl | 15 ++------------- src/mainboard/google/slippy/acpi/platform.asl | 15 ++------------- src/mainboard/google/slippy/acpi/superio.asl | 15 ++------------- src/mainboard/google/slippy/acpi/thermal.asl | 15 ++------------- src/mainboard/google/slippy/acpi_tables.c | 15 ++------------- src/mainboard/google/slippy/chromeos.c | 15 ++------------- src/mainboard/google/slippy/dsdt.asl | 15 ++------------- src/mainboard/google/slippy/ec.c | 15 ++------------- src/mainboard/google/slippy/ec.h | 15 ++------------- src/mainboard/google/slippy/mainboard.c | 15 ++------------- src/mainboard/google/slippy/onboard.h | 15 ++------------- src/mainboard/google/slippy/romstage.c | 15 ++------------- src/mainboard/google/slippy/smihandler.c | 15 ++------------- src/mainboard/google/slippy/thermal.h | 15 ++------------- src/mainboard/google/slippy/variant.h | 15 ++------------- .../google/slippy/variants/falco/hda_verb.c | 15 ++------------- .../falco/include/variant/acpi/mainboard.asl | 16 ++-------------- .../slippy/variants/falco/include/variant/gpio.h | 15 ++------------- .../google/slippy/variants/falco/romstage.c | 15 ++------------- .../google/slippy/variants/leon/hda_verb.c | 15 ++------------- .../leon/include/variant/acpi/mainboard.asl | 16 ++-------------- .../slippy/variants/leon/include/variant/gpio.h | 15 ++------------- .../google/slippy/variants/leon/romstage.c | 15 ++------------- .../google/slippy/variants/peppy/hda_verb.c | 15 ++------------- .../peppy/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/peppy/include/variant/acpi/usb.asl | 14 ++------------ .../slippy/variants/peppy/include/variant/gpio.h | 15 ++------------- .../google/slippy/variants/peppy/romstage.c | 15 ++------------- .../google/slippy/variants/wolf/hda_verb.c | 15 ++------------- .../wolf/include/variant/acpi/mainboard.asl | 16 ++-------------- .../variants/wolf/include/variant/acpi/usb.asl | 14 ++------------ .../slippy/variants/wolf/include/variant/gpio.h | 15 ++------------- .../google/slippy/variants/wolf/romstage.c | 15 ++------------- 34 files changed, 68 insertions(+), 444 deletions(-) diff --git a/src/mainboard/google/slippy/acpi/ec.asl b/src/mainboard/google/slippy/acpi/ec.asl index 964ed765bf..d8b3b495a7 100644 --- a/src/mainboard/google/slippy/acpi/ec.asl +++ b/src/mainboard/google/slippy/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/slippy/acpi/mainboard.asl b/src/mainboard/google/slippy/acpi/mainboard.asl index e9ade244cf..b2a869a4cb 100644 --- a/src/mainboard/google/slippy/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl index ddeea8a95d..69b3ded99e 100644 --- a/src/mainboard/google/slippy/acpi/platform.asl +++ b/src/mainboard/google/slippy/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/slippy/acpi/superio.asl b/src/mainboard/google/slippy/acpi/superio.asl index 02c320af60..d5cee3781e 100644 --- a/src/mainboard/google/slippy/acpi/superio.asl +++ b/src/mainboard/google/slippy/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include "../ec.h" diff --git a/src/mainboard/google/slippy/acpi/thermal.asl b/src/mainboard/google/slippy/acpi/thermal.asl index 3ea7aa2f37..b8c2f481e6 100644 --- a/src/mainboard/google/slippy/acpi/thermal.asl +++ b/src/mainboard/google/slippy/acpi/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Thermal Zone diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index ae79d94bad..9666f296f4 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index a92572f4aa..643352d70d 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 373e31a9b9..767401d7ce 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include DefinitionBlock( diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 417dd79f17..484b4acbba 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/ec.h b/src/mainboard/google/slippy/ec.h index 8653c8ad82..f8745fcf21 100644 --- a/src/mainboard/google/slippy/ec.h +++ b/src/mainboard/google/slippy/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 2a2b13b0b0..eea029c7fe 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 5ad47e2835..eff8299bd6 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 7a9715443f..6715ff6942 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "variant.h" diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 41e9d5a2ab..d2d81f8de4 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/thermal.h b/src/mainboard/google/slippy/thermal.h index c01481ab0f..47c1697829 100644 --- a/src/mainboard/google/slippy/thermal.h +++ b/src/mainboard/google/slippy/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef THERMAL_H #define THERMAL_H diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index ab5dc414ea..084431bea8 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/slippy/variants/falco/hda_verb.c b/src/mainboard/google/slippy/variants/falco/hda_verb.c index 30a419e9db..4c57484f40 100644 --- a/src/mainboard/google/slippy/variants/falco/hda_verb.c +++ b/src/mainboard/google/slippy/variants/falco/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl index b8f5f14723..c2d4fc3f6a 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h b/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h index 6419e32b9b..fbc3faae64 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef FALCO_GPIO_H #define FALCO_GPIO_H diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index ee78a705e9..1eb48bfd96 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/variants/leon/hda_verb.c b/src/mainboard/google/slippy/variants/leon/hda_verb.c index 4fe9278639..c5664968ad 100644 --- a/src/mainboard/google/slippy/variants/leon/hda_verb.c +++ b/src/mainboard/google/slippy/variants/leon/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl index 9ac43e8a1e..2254f8ed46 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h b/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h index 798890ac2a..4adfd3e3a7 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef LEON_GPIO_H #define LEON_GPIO_H diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index edf974826f..397c0edebb 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/variants/peppy/hda_verb.c b/src/mainboard/google/slippy/variants/peppy/hda_verb.c index 267e3e9087..7237c09d53 100644 --- a/src/mainboard/google/slippy/variants/peppy/hda_verb.c +++ b/src/mainboard/google/slippy/variants/peppy/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index 536a7a4969..c9be862773 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl index 9227680d53..3538c719ee 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT1) { diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h b/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h index 0da2652446..8697d2ea04 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef PEPPY_GPIO_H #define PEPPY_GPIO_H diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index a9e1812829..d2a92a8789 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c index 63cb8fa171..350ce8ddf3 100644 --- a/src/mainboard/google/slippy/variants/wolf/hda_verb.c +++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl index 9ac43e8a1e..2254f8ed46 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C0) { diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl index 1799640070..fd98b61318 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.HUB7.PRT1) { diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h index c7e65d2305..2a3af00f2b 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef WOLF_GPIO_H #define WOLF_GPIO_H diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index bb61a45e7f..dcd9ac06fd 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 2712398a69a543bdc4d4c687cdfca906837d8bc8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:30 +0200 Subject: [PATCH 0887/1463] mb/google/poppy: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Idfc7a5713e231c4756b5faca8984c6598fe1e65a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40190 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/bootblock.c | 15 ++------------- src/mainboard/google/poppy/chromeos.c | 15 ++------------- src/mainboard/google/poppy/dsdt.asl | 15 ++------------- src/mainboard/google/poppy/ec.c | 15 ++------------- src/mainboard/google/poppy/mainboard.c | 15 ++------------- src/mainboard/google/poppy/ramstage.c | 15 ++------------- src/mainboard/google/poppy/romstage.c | 15 ++------------- src/mainboard/google/poppy/smihandler.c | 15 ++------------- src/mainboard/google/poppy/variants/atlas/gpio.c | 15 ++------------- .../variants/atlas/include/variant/acpi/cam0.asl | 15 ++------------- .../atlas/include/variant/acpi/camera.asl | 15 ++------------- .../variants/atlas/include/variant/acpi/dptf.asl | 15 ++------------- .../atlas/include/variant/acpi/ipu_endpoints.asl | 15 ++------------- .../atlas/include/variant/acpi/ipu_mainboard.asl | 15 ++------------- .../poppy/variants/atlas/include/variant/ec.h | 15 ++------------- .../poppy/variants/atlas/include/variant/gpio.h | 15 ++------------- .../google/poppy/variants/atlas/mainboard.c | 15 ++------------- .../google/poppy/variants/atlas/memory.c | 15 ++------------- src/mainboard/google/poppy/variants/atlas/nhlt.c | 15 ++------------- .../google/poppy/variants/baseboard/gpio.c | 15 ++------------- .../baseboard/include/baseboard/acpi/cam0.asl | 15 ++------------- .../baseboard/include/baseboard/acpi/cam1.asl | 15 ++------------- .../baseboard/include/baseboard/acpi/camera.asl | 15 ++------------- .../include/baseboard/acpi/camera_pmic.asl | 15 ++------------- .../baseboard/include/baseboard/acpi/dptf.asl | 15 ++------------- .../include/baseboard/acpi/ipu_endpoints.asl | 15 ++------------- .../include/baseboard/acpi/ipu_mainboard.asl | 15 ++------------- .../variants/baseboard/include/baseboard/ec.h | 15 ++------------- .../variants/baseboard/include/baseboard/gpio.h | 15 ++------------- .../baseboard/include/baseboard/variants.h | 15 ++------------- .../google/poppy/variants/baseboard/memory.c | 15 ++------------- .../google/poppy/variants/baseboard/nhlt.c | 15 ++------------- src/mainboard/google/poppy/variants/nami/gpio.c | 15 ++------------- .../variants/nami/include/variant/acpi/dptf.asl | 15 ++------------- .../poppy/variants/nami/include/variant/ec.h | 15 ++------------- .../poppy/variants/nami/include/variant/gpio.h | 15 ++------------- .../poppy/variants/nami/include/variant/sku.h | 15 ++------------- .../google/poppy/variants/nami/mainboard.c | 15 ++------------- src/mainboard/google/poppy/variants/nami/memory.c | 15 ++------------- src/mainboard/google/poppy/variants/nami/nhlt.c | 15 ++------------- .../google/poppy/variants/nami/smihandler.c | 15 ++------------- .../google/poppy/variants/nautilus/gpio.c | 15 ++------------- .../nautilus/include/variant/acpi/cam0.asl | 15 ++------------- .../nautilus/include/variant/acpi/camera.asl | 15 ++------------- .../nautilus/include/variant/acpi/dptf.asl | 15 ++------------- .../include/variant/acpi/ipu_endpoints.asl | 15 ++------------- .../include/variant/acpi/ipu_mainboard.asl | 15 ++------------- .../poppy/variants/nautilus/include/variant/ec.h | 15 ++------------- .../variants/nautilus/include/variant/gpio.h | 15 ++------------- .../poppy/variants/nautilus/include/variant/sku.h | 15 ++------------- .../google/poppy/variants/nautilus/mainboard.c | 15 ++------------- .../google/poppy/variants/nautilus/memory.c | 15 ++------------- .../google/poppy/variants/nautilus/nhlt.c | 15 ++------------- .../google/poppy/variants/nautilus/sku.c | 15 ++------------- .../google/poppy/variants/nautilus/smihandler.c | 15 ++------------- src/mainboard/google/poppy/variants/nocturne/ec.c | 15 ++------------- .../google/poppy/variants/nocturne/gpio.c | 15 ++------------- .../nocturne/include/variant/acpi/cam0.asl | 15 ++------------- .../nocturne/include/variant/acpi/cam1.asl | 15 ++------------- .../nocturne/include/variant/acpi/camera.asl | 15 ++------------- .../nocturne/include/variant/acpi/dptf.asl | 15 ++------------- .../include/variant/acpi/ipu_endpoints.asl | 15 ++------------- .../include/variant/acpi/ipu_mainboard.asl | 15 ++------------- .../poppy/variants/nocturne/include/variant/ec.h | 15 ++------------- .../variants/nocturne/include/variant/gpio.h | 15 ++------------- .../google/poppy/variants/nocturne/mainboard.c | 15 ++------------- .../google/poppy/variants/nocturne/memory.c | 15 ++------------- .../google/poppy/variants/nocturne/nhlt.c | 15 ++------------- .../poppy/include/variant/acpi/camera.asl | 15 ++------------- .../variants/poppy/include/variant/acpi/dptf.asl | 15 ++------------- .../poppy/variants/poppy/include/variant/ec.h | 15 ++------------- .../poppy/variants/poppy/include/variant/gpio.h | 15 ++------------- src/mainboard/google/poppy/variants/rammus/gpio.c | 15 ++------------- .../variants/rammus/include/variant/acpi/dptf.asl | 15 ++------------- .../poppy/variants/rammus/include/variant/ec.h | 15 ++------------- .../poppy/variants/rammus/include/variant/gpio.h | 15 ++------------- .../google/poppy/variants/rammus/mainboard.c | 15 ++------------- .../google/poppy/variants/rammus/memory.c | 15 ++------------- src/mainboard/google/poppy/variants/rammus/nhlt.c | 15 ++------------- src/mainboard/google/poppy/variants/soraka/gpio.c | 15 ++------------- .../soraka/include/variant/acpi/camera.asl | 15 ++------------- .../variants/soraka/include/variant/acpi/dptf.asl | 15 ++------------- .../poppy/variants/soraka/include/variant/ec.h | 15 ++------------- .../poppy/variants/soraka/include/variant/gpio.h | 15 ++------------- 84 files changed, 168 insertions(+), 1092 deletions(-) diff --git a/src/mainboard/google/poppy/bootblock.c b/src/mainboard/google/poppy/bootblock.c index fe2262c1d5..00ac265162 100644 --- a/src/mainboard/google/poppy/bootblock.c +++ b/src/mainboard/google/poppy/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 329d53e701..a0bd9b20f3 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 7a21384cfe..9684c043f0 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/ec.c b/src/mainboard/google/poppy/ec.c index 4fbea2e845..77f063d875 100644 --- a/src/mainboard/google/poppy/ec.c +++ b/src/mainboard/google/poppy/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index a375d1f33d..dc50399b88 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c index bdcaa321f3..6a2e551b23 100644 --- a/src/mainboard/google/poppy/ramstage.c +++ b/src/mainboard/google/poppy/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 8c5d3085a3..85260c13de 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c index 21ae5f8216..33a4faff69 100644 --- a/src/mainboard/google/poppy/smihandler.c +++ b/src/mainboard/google/poppy/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index b8ad480cce..3781513900 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl index 0f433eaba9..3b5056d926 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C3) { diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl index 5f0e71214d..9bc56f0939 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ipu_mainboard.asl" #include "ipu_endpoints.asl" diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 5f08a1d2b4..dec5ecef1d 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl index 89396f087c..ce1b7c0639 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl index 03cba8cac2..08d55ef5a3 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h index cb2ca72d81..28740ba163 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h index d439f89765..a94b5d94b8 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 8b475d4928..188962c8ec 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c index 7db8339a8b..3dd2c0c546 100644 --- a/src/mainboard/google/poppy/variants/atlas/memory.c +++ b/src/mainboard/google/poppy/variants/atlas/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/atlas/nhlt.c b/src/mainboard/google/poppy/variants/atlas/nhlt.c index 0d909695b5..03df194e32 100644 --- a/src/mainboard/google/poppy/variants/atlas/nhlt.c +++ b/src/mainboard/google/poppy/variants/atlas/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 7c2d282513..edc555a59a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl index 6bc5a68ce3..76bbfa3998 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C2) { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl index 154a62b6a3..e46d0865bf 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C4) { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl index fafa29f30a..1365ee9f58 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ipu_mainboard.asl" #include "ipu_endpoints.asl" diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 02c18e119a..377f5615f0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C2) { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl index e2c1c01bbc..c63c0ccbe9 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_CRITICAL 99 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl index d96416e279..9d2b5a8f3d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl index a8a7e4ad13..83538daba8 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h index f89808c6a3..11ac7a5139 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h index 4e1506069f..a5239517e9 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index 63cc123b05..23c0c1628c 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/poppy/variants/baseboard/memory.c b/src/mainboard/google/poppy/variants/baseboard/memory.c index ac8e90815c..3f19faca8f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/memory.c +++ b/src/mainboard/google/poppy/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/baseboard/nhlt.c b/src/mainboard/google/poppy/variants/baseboard/nhlt.c index 3d8d29fd70..fd8dd77289 100644 --- a/src/mainboard/google/poppy/variants/baseboard/nhlt.c +++ b/src/mainboard/google/poppy/variants/baseboard/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 93b8e15375..980e9a55c0 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl index ee038fb9c7..ba089dd5b3 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 98 #define DPTF_CPU_CRITICAL 125 diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/ec.h b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h index d7fcf5548e..a4816a2723 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h index ab76d7b498..b535cca69a 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 9b146c76df..79174471c9 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_SKU_H__ #define __MAINBOARD_SKU_H__ diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 9a08597d04..3df1f71a08 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index 5ab78eeb98..1b91ee8f8e 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c index 50bd7eaf21..6a4212d3d3 100644 --- a/src/mainboard/google/poppy/variants/nami/nhlt.c +++ b/src/mainboard/google/poppy/variants/nami/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nami/smihandler.c b/src/mainboard/google/poppy/variants/nami/smihandler.c index 6d9c227d49..0e4c085d9b 100644 --- a/src/mainboard/google/poppy/variants/nami/smihandler.c +++ b/src/mainboard/google/poppy/variants/nami/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 5f83a5f7b6..2652cab0e2 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl index 456bc10d2b..b12dfe3d1c 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C2) { diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl index a265c5d4ae..64ab8a2185 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ipu_mainboard.asl" #include "ipu_endpoints.asl" diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl index 2d09608ed4..eb0b33b4b8 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl index e5eed8eb53..053d8e891d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl index 5626b6c223..ea311ccb22 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h index d6eb4f1649..dce16f180d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h index 97774271b3..0f0ff50584 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h index 1d019c3f82..9e1661ecb1 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_SKU_H__ #define __MAINBOARD_SKU_H__ diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 223ad49fb1..a3c852400e 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/memory.c b/src/mainboard/google/poppy/variants/nautilus/memory.c index dd8608f2d5..92ce85aed8 100644 --- a/src/mainboard/google/poppy/variants/nautilus/memory.c +++ b/src/mainboard/google/poppy/variants/nautilus/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/nhlt.c b/src/mainboard/google/poppy/variants/nautilus/nhlt.c index 08c057a8c1..bbdf9b155d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/nhlt.c +++ b/src/mainboard/google/poppy/variants/nautilus/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/sku.c b/src/mainboard/google/poppy/variants/nautilus/sku.c index 2040f144ca..bbd7a4d18b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/sku.c +++ b/src/mainboard/google/poppy/variants/nautilus/sku.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/smihandler.c b/src/mainboard/google/poppy/variants/nautilus/smihandler.c index 3b6c45aa3c..a65172374b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/smihandler.c +++ b/src/mainboard/google/poppy/variants/nautilus/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nocturne/ec.c b/src/mainboard/google/poppy/variants/nocturne/ec.c index 90f1187a24..7619c7f602 100644 --- a/src/mainboard/google/poppy/variants/nocturne/ec.c +++ b/src/mainboard/google/poppy/variants/nocturne/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 0c8947b15a..ef093838d2 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl index bbf534a2e4..0a66f9abb2 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C3) { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl index 4d87b2910e..bd11758d78 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.I2C5) { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl index 6c74ef1498..fae8e5d1dd 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "ipu_mainboard.asl" #include "ipu_endpoints.asl" diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index 1ca8b55d2a..7d2f3424d9 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl index 0e729a5a56..ecb4738667 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl index f489990a78..e8eaf320c4 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.CIO2) { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h index bb98e65e97..8e27990edc 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h index 7fbd04f3d1..03fd88e117 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index e9cec1e9b1..5df26cd49a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/nocturne/memory.c b/src/mainboard/google/poppy/variants/nocturne/memory.c index 59490bad26..7ce273fd95 100644 --- a/src/mainboard/google/poppy/variants/nocturne/memory.c +++ b/src/mainboard/google/poppy/variants/nocturne/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/poppy/variants/nocturne/nhlt.c b/src/mainboard/google/poppy/variants/nocturne/nhlt.c index 0b0efdc368..93045fa2c6 100644 --- a/src/mainboard/google/poppy/variants/nocturne/nhlt.c +++ b/src/mainboard/google/poppy/variants/nocturne/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl index 14fa2113db..304c0fe611 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl index 7d9006a068..231ff1bb72 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h b/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h index fbae57d7fc..734518f138 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h b/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index 0cae82f404..b276faf5b9 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl index 7d9006a068..231ff1bb72 100644 --- a/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h index 2711481903..daf6d3b8a7 100644 --- a/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h b/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/poppy/variants/rammus/mainboard.c b/src/mainboard/google/poppy/variants/rammus/mainboard.c index c3f5b2af83..07964a3f4e 100644 --- a/src/mainboard/google/poppy/variants/rammus/mainboard.c +++ b/src/mainboard/google/poppy/variants/rammus/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/rammus/memory.c b/src/mainboard/google/poppy/variants/rammus/memory.c index 1a4fe05f20..eec7c1a162 100644 --- a/src/mainboard/google/poppy/variants/rammus/memory.c +++ b/src/mainboard/google/poppy/variants/rammus/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c index c22f672eca..513df50dcd 100644 --- a/src/mainboard/google/poppy/variants/rammus/nhlt.c +++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index c59c572e03..be0c3e9be8 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl index 14fa2113db..304c0fe611 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl index c44e6515b8..1c8abe710d 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 82 #define DPTF_CPU_CRITICAL 100 diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h b/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h index 1bee0bb741..dc0e41c701 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h b/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h index bcb87cb1d7..785fcaceb1 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ From 47f26dbe1572f5b22c9e2ef01b16273395b5ea8e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 13:22:34 +0200 Subject: [PATCH 0888/1463] mb/google/rambi: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I0dea26da28a2879e34593907fef6f984317c347f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40191 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/rambi/acpi/dptf.asl | 14 ++------------ src/mainboard/google/rambi/acpi/ec.asl | 15 ++------------- src/mainboard/google/rambi/acpi/mainboard.asl | 16 ++-------------- src/mainboard/google/rambi/acpi/superio.asl | 15 ++------------- .../google/rambi/acpi/touchscreen_atmel.asl | 15 ++------------- .../google/rambi/acpi/touchscreen_elan.asl | 15 ++------------- .../google/rambi/acpi/touchscreen_wdt.asl | 15 ++------------- .../google/rambi/acpi/trackpad_atmel.asl | 15 ++------------- .../google/rambi/acpi/trackpad_elan.asl | 15 ++------------- src/mainboard/google/rambi/acpi_tables.c | 15 ++------------- src/mainboard/google/rambi/chromeos.c | 15 ++------------- src/mainboard/google/rambi/dsdt.asl | 15 ++------------- src/mainboard/google/rambi/ec.c | 15 ++------------- src/mainboard/google/rambi/ec.h | 15 ++------------- src/mainboard/google/rambi/fadt.c | 15 ++------------- src/mainboard/google/rambi/irqroute.c | 15 ++------------- src/mainboard/google/rambi/irqroute.h | 15 ++------------- src/mainboard/google/rambi/mainboard.c | 15 ++------------- src/mainboard/google/rambi/mainboard_smi.c | 15 ++------------- src/mainboard/google/rambi/romstage.c | 15 ++------------- src/mainboard/google/rambi/variants/banjo/gpio.c | 15 ++------------- .../variants/banjo/include/variant/acpi/dptf.asl | 14 ++------------ .../banjo/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/banjo/include/variant/onboard.h | 15 ++------------- .../variants/banjo/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/candy/gpio.c | 15 ++------------- .../variants/candy/include/variant/acpi/dptf.asl | 14 ++------------ .../candy/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/candy/include/variant/acpi/usb.asl | 14 ++------------ .../variants/candy/include/variant/onboard.h | 15 ++------------- .../variants/candy/include/variant/variant.h | 14 ++------------ .../google/rambi/variants/clapper/gpio.c | 15 ++------------- .../clapper/include/variant/acpi/dptf.asl | 14 ++------------ .../clapper/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/clapper/include/variant/onboard.h | 15 ++------------- .../variants/clapper/include/variant/variant.h | 14 ++------------ .../google/rambi/variants/enguarde/gpio.c | 15 ++------------- .../enguarde/include/variant/acpi/dptf.asl | 14 ++------------ .../enguarde/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/enguarde/include/variant/onboard.h | 15 ++------------- .../variants/enguarde/include/variant/variant.h | 14 ++------------ .../google/rambi/variants/glimmer/gpio.c | 15 ++------------- .../glimmer/include/variant/acpi/dptf.asl | 14 ++------------ .../glimmer/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/glimmer/include/variant/onboard.h | 15 ++------------- .../variants/glimmer/include/variant/variant.h | 14 ++------------ .../google/rambi/variants/gnawty/gpio.c | 15 ++------------- .../gnawty/include/variant/acpi/dptf.asl | 14 ++------------ .../gnawty/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/gnawty/include/variant/onboard.h | 15 ++------------- .../variants/gnawty/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/heli/gpio.c | 15 ++------------- .../variants/heli/include/variant/acpi/dptf.asl | 14 ++------------ .../heli/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/heli/include/variant/onboard.h | 15 ++------------- .../variants/heli/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/kip/gpio.c | 15 ++------------- .../variants/kip/include/variant/acpi/dptf.asl | 14 ++------------ .../kip/include/variant/acpi/mainboard.asl | 15 ++------------- .../rambi/variants/kip/include/variant/onboard.h | 15 ++------------- .../rambi/variants/kip/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/ninja/gpio.c | 15 ++------------- .../variants/ninja/include/variant/acpi/dptf.asl | 15 ++------------- .../variants/ninja/include/variant/onboard.h | 15 ++------------- .../variants/ninja/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/ninja/lan.c | 15 ++------------- src/mainboard/google/rambi/variants/orco/gpio.c | 15 ++------------- .../variants/orco/include/variant/acpi/dptf.asl | 15 ++------------- .../orco/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/orco/include/variant/onboard.h | 15 ++------------- .../variants/orco/include/variant/variant.h | 14 ++------------ .../google/rambi/variants/quawks/gpio.c | 15 ++------------- .../quawks/include/variant/acpi/dptf.asl | 14 ++------------ .../quawks/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/quawks/include/variant/onboard.h | 15 ++------------- .../variants/quawks/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/rambi/gpio.c | 15 ++------------- .../variants/rambi/include/variant/acpi/dptf.asl | 15 ++------------- .../rambi/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/rambi/include/variant/onboard.h | 15 ++------------- .../variants/rambi/include/variant/variant.h | 14 ++------------ .../google/rambi/variants/squawks/gpio.c | 15 ++------------- .../squawks/include/variant/acpi/dptf.asl | 14 ++------------ .../squawks/include/variant/acpi/mainboard.asl | 15 ++------------- .../squawks/include/variant/acpi/usb.asl | 14 ++------------ .../variants/squawks/include/variant/onboard.h | 15 ++------------- .../variants/squawks/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/sumo/gpio.c | 15 ++------------- .../variants/sumo/include/variant/acpi/dptf.asl | 15 ++------------- .../sumo/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/sumo/include/variant/onboard.h | 15 ++------------- .../variants/sumo/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/sumo/lan.c | 15 ++------------- .../google/rambi/variants/swanky/gpio.c | 15 ++------------- .../swanky/include/variant/acpi/dptf.asl | 14 ++------------ .../swanky/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/swanky/include/variant/onboard.h | 15 ++------------- .../variants/swanky/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/variants/winky/gpio.c | 15 ++------------- .../variants/winky/include/variant/acpi/dptf.asl | 15 ++------------- .../winky/include/variant/acpi/mainboard.asl | 15 ++------------- .../variants/winky/include/variant/onboard.h | 15 ++------------- .../variants/winky/include/variant/variant.h | 14 ++------------ src/mainboard/google/rambi/w25q64.c | 15 ++------------- 104 files changed, 208 insertions(+), 1323 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index 673ad1c1ae..904c0b20e3 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Include variant DPTF */ #include diff --git a/src/mainboard/google/rambi/acpi/ec.asl b/src/mainboard/google/rambi/acpi/ec.asl index f66955aa7b..9653cf0718 100644 --- a/src/mainboard/google/rambi/acpi/ec.asl +++ b/src/mainboard/google/rambi/acpi/ec.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* mainboard configuration */ #include diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index a17ecaee19..a928ef3461 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl index 9f3fe50293..39c4c692c2 100644 --- a/src/mainboard/google/rambi/acpi/superio.asl +++ b/src/mainboard/google/rambi/acpi/superio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Baseboard configuration */ #include diff --git a/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl index 80b28e21ef..6215ba8e76 100644 --- a/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl +++ b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/rambi/acpi/touchscreen_elan.asl b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl index feb6c9209d..40804fc359 100644 --- a/src/mainboard/google/rambi/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl index 9732c1002b..a262425c80 100644 --- a/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl +++ b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/rambi/acpi/trackpad_atmel.asl b/src/mainboard/google/rambi/acpi/trackpad_atmel.asl index 20296bddf4..d18f923dcb 100644 --- a/src/mainboard/google/rambi/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/rambi/acpi/trackpad_atmel.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/rambi/acpi/trackpad_elan.asl b/src/mainboard/google/rambi/acpi/trackpad_elan.asl index d1adb138ef..08f1a2e0ba 100644 --- a/src/mainboard/google/rambi/acpi/trackpad_elan.asl +++ b/src/mainboard/google/rambi/acpi/trackpad_elan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 4538bdb29d..ef65930bf3 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index fbb709d42b..3d2bd4592f 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 347269fa15..ce393a312c 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define ENABLE_TPM diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 39d3aac7b0..4e1a192ee4 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/ec.h b/src/mainboard/google/rambi/ec.h index 6dd15badef..a2c738163b 100644 --- a/src/mainboard/google/rambi/ec.h +++ b/src/mainboard/google/rambi/ec.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index 6afc8e23c0..47d50d28c0 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/irqroute.c b/src/mainboard/google/rambi/irqroute.c index f0855adbc2..df43ee9c69 100644 --- a/src/mainboard/google/rambi/irqroute.c +++ b/src/mainboard/google/rambi/irqroute.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "irqroute.h" diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index fd28367235..2d780ed138 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 4a1fd91dce..51da9b8672 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index 9f2098e9aa..fa0e39f999 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index d786ee6711..c9753c02ac 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c index 60d809323e..cf7f33495c 100644 --- a/src/mainboard/google/rambi/variants/banjo/gpio.c +++ b/src/mainboard/google/rambi/variants/banjo/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl index 4276b1cda5..e342d711bd 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl index f64eeff40e..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h index 71ce0e52f9..ddfadee156 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h index 29b707c972..99c427986a 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c index 5f15a15452..28c82e3c4d 100644 --- a/src/mainboard/google/rambi/variants/candy/gpio.c +++ b/src/mainboard/google/rambi/variants/candy/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl index 8dd08851a8..d2c038cbd2 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 85 #define DPTF_CPU_CRITICAL 100 diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl index 33d3209cd4..52c61cb45f 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl index 028a546cf0..c2b8548db2 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.RHUB.PRT1) { diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h index ff737235c2..0e62e05953 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h index 9dac2b9b5c..1db452da0f 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c index 7eacfd1797..7753b636a2 100644 --- a/src/mainboard/google/rambi/variants/clapper/gpio.c +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl index 53dd09c0f3..17344330b0 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl index 82510bd359..021b540be4 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h index 8c135423f9..232e01e7b0 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h index 4e5ba4216e..510adc09b7 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/enguarde/gpio.c b/src/mainboard/google/rambi/variants/enguarde/gpio.c index df15054e97..a2903946f1 100644 --- a/src/mainboard/google/rambi/variants/enguarde/gpio.c +++ b/src/mainboard/google/rambi/variants/enguarde/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl index e9b78a864f..568aefaf9c 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h index a693c71213..31fc27341d 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h index 55c20a2952..72154d60e3 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c index 57b9653ae0..66cd191154 100644 --- a/src/mainboard/google/rambi/variants/glimmer/gpio.c +++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl index 6e2630be3b..a5ee338a1b 100644 --- a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl index 82510bd359..021b540be4 100644 --- a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h index 8c135423f9..232e01e7b0 100644 --- a/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h index 28105518a4..84dbe4363e 100644 --- a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c index 2b4af4a53d..22001fd022 100644 --- a/src/mainboard/google/rambi/variants/gnawty/gpio.c +++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl index 1df96fab95..8033fe39a3 100644 --- a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h index ff737235c2..0e62e05953 100644 --- a/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h index dd76bd31c8..d9b25c46fd 100644 --- a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c index ead1341a0f..95c46d37f6 100644 --- a/src/mainboard/google/rambi/variants/heli/gpio.c +++ b/src/mainboard/google/rambi/variants/heli/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl index adc796d0e6..30941b9269 100644 --- a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h index 71ce0e52f9..ddfadee156 100644 --- a/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h index a240e40fd4..c6d7d9705b 100644 --- a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c index 9180b880f7..280e14d07d 100644 --- a/src/mainboard/google/rambi/variants/kip/gpio.c +++ b/src/mainboard/google/rambi/variants/kip/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl index e88ac7df42..bd1df99bfc 100644 --- a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h index a693c71213..31fc27341d 100644 --- a/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h index 06bcbec82e..984b7939d8 100644 --- a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/ninja/gpio.c b/src/mainboard/google/rambi/variants/ninja/gpio.c index 945182c236..4bff882acf 100644 --- a/src/mainboard/google/rambi/variants/ninja/gpio.c +++ b/src/mainboard/google/rambi/variants/ninja/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl index a460908726..223a5d3027 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h index 2d7594a1f8..217f1bc302 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h index 98f43a0586..cf3915a92f 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index a5e5c4bfe8..6955e644e9 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c index 08cb034d16..18241ae19d 100644 --- a/src/mainboard/google/rambi/variants/orco/gpio.c +++ b/src/mainboard/google/rambi/variants/orco/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl index 3530d7bc6d..568aefaf9c 100644 --- a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h index 71ce0e52f9..ddfadee156 100644 --- a/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h index eeaaf60ca1..f3f4e6ddaf 100644 --- a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c index 9180b880f7..280e14d07d 100644 --- a/src/mainboard/google/rambi/variants/quawks/gpio.c +++ b/src/mainboard/google/rambi/variants/quawks/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl index 7e36946665..c58952b3d3 100644 --- a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h index a693c71213..31fc27341d 100644 --- a/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h index f98beb20c1..2f074178fb 100644 --- a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/rambi/gpio.c b/src/mainboard/google/rambi/variants/rambi/gpio.c index 9180b880f7..280e14d07d 100644 --- a/src/mainboard/google/rambi/variants/rambi/gpio.c +++ b/src/mainboard/google/rambi/variants/rambi/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl index f8409eed13..8984937e6e 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl index f4bc3251cb..833fee76b4 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h b/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h index 62a0884d15..343e7c2a74 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h index 8051f1b7af..45e6657d23 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c index 9180b880f7..280e14d07d 100644 --- a/src/mainboard/google/rambi/variants/squawks/gpio.c +++ b/src/mainboard/google/rambi/variants/squawks/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl index b17f980c8d..6b5825e692 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 90 #define DPTF_CPU_CRITICAL 100 diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl index cacf40f714..2b925e5b92 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.XHCI.RHUB.PRT1) { diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h index a693c71213..31fc27341d 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h index f98beb20c1..2f074178fb 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c index 6dc8851e65..31ab5f8b96 100644 --- a/src/mainboard/google/rambi/variants/sumo/gpio.c +++ b/src/mainboard/google/rambi/variants/sumo/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl index 3530d7bc6d..568aefaf9c 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl index e7f06ee2b7..9990a6bc0d 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* WDT touchscreen */ #include diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h index 601b137461..e3bb0802f0 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h index 98f43a0586..cf3915a92f 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index 97495049ad..d4f7f975c6 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c index 951ee54593..8a47859633 100644 --- a/src/mainboard/google/rambi/variants/swanky/gpio.c +++ b/src/mainboard/google/rambi/variants/swanky/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl index e9b78a864f..568aefaf9c 100644 --- a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl index 3cdd5c0cb2..4e1583d3dd 100644 --- a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Elan trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h index 71ce0e52f9..ddfadee156 100644 --- a/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h index 0beee1cad6..80f88d4cfd 100644 --- a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c index 6924044276..2c6e93546e 100644 --- a/src/mainboard/google/rambi/variants/winky/gpio.c +++ b/src/mainboard/google/rambi/variants/winky/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl index 3530d7bc6d..568aefaf9c 100644 --- a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl index 184ef83482..c28563f486 100644 --- a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Atmel trackpad */ #include diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h index 0f554211d5..f3666de0d1 100644 --- a/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef ONBOARD_H #define ONBOARD_H diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h index 402270fc92..be78c12226 100644 --- a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c index 104414265f..d85a4a66dc 100644 --- a/src/mainboard/google/rambi/w25q64.c +++ b/src/mainboard/google/rambi/w25q64.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 6bc1374e2dd4dceaf4eca6a4f271966206e3e886 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:46:38 +0200 Subject: [PATCH 0889/1463] soc/intel/apollolake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3c6daa484a4aa133ff2ad79eb2b8efa159da3523 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40208 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/intel/apollolake/acpi/dptf.asl | 15 ++------------- src/soc/intel/apollolake/acpi/gpiolib.asl | 15 ++------------- src/soc/intel/apollolake/acpi/pch_hda.asl | 16 ++-------------- src/soc/intel/apollolake/acpi/pcie.asl | 15 ++------------- src/soc/intel/apollolake/acpi/pcie_port.asl | 15 ++------------- src/soc/intel/apollolake/acpi/platform.asl | 15 ++------------- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 16 ++-------------- src/soc/intel/apollolake/acpi/scs.asl | 15 ++------------- src/soc/intel/apollolake/acpi/xhci.asl | 15 ++------------- src/soc/intel/apollolake/cse.c | 15 ++------------- src/soc/intel/apollolake/elog.c | 15 ++------------- src/soc/intel/apollolake/i2c.c | 15 ++------------- src/soc/intel/apollolake/include/soc/gpe.h | 15 ++------------- src/soc/intel/apollolake/include/soc/itss.h | 15 ++------------- src/soc/intel/apollolake/include/soc/me.h | 15 ++------------- src/soc/intel/apollolake/include/soc/meminit.h | 15 ++------------- src/soc/intel/apollolake/include/soc/p2sb.h | 15 ++------------- src/soc/intel/apollolake/include/soc/pcr_ids.h | 15 ++------------- src/soc/intel/apollolake/include/soc/pnpconfig.h | 15 ++------------- src/soc/intel/apollolake/include/soc/smbus.h | 15 ++------------- src/soc/intel/apollolake/include/soc/soc_chip.h | 15 ++------------- src/soc/intel/apollolake/meminit.c | 15 ++------------- src/soc/intel/apollolake/meminit_util_apl.c | 15 ++------------- src/soc/intel/apollolake/meminit_util_glk.c | 15 ++------------- src/soc/intel/apollolake/pnpconfig.c | 15 ++------------- src/soc/intel/apollolake/report_platform.c | 15 ++------------- src/soc/intel/apollolake/reset.c | 15 ++------------- src/soc/intel/apollolake/sd.c | 15 ++------------- src/soc/intel/apollolake/smihandler.c | 15 ++------------- src/soc/intel/apollolake/xdci.c | 15 ++------------- src/soc/intel/apollolake/xhci.c | 15 ++------------- 31 files changed, 62 insertions(+), 405 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/dptf.asl b/src/soc/intel/apollolake/acpi/dptf.asl index ffbf9137ca..98009d7a5a 100644 --- a/src/soc/intel/apollolake/acpi/dptf.asl +++ b/src/soc/intel/apollolake/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_DEVICE TCPU #define DPTF_CPU_ADDR 0x00000001 diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl index a4ab9135c5..aee6026fe4 100644 --- a/src/soc/intel/apollolake/acpi/gpiolib.asl +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl index c140bf6f12..68259c2687 100644 --- a/src/soc/intel/apollolake/acpi/pch_hda.asl +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Audio Controller - Device 14, Function 0 */ diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl index d4cb02bf37..ad0bcb6865 100644 --- a/src/soc/intel/apollolake/acpi/pcie.asl +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCIe Ports */ diff --git a/src/soc/intel/apollolake/acpi/pcie_port.asl b/src/soc/intel/apollolake/acpi/pcie_port.asl index 84e256536c..a9878cc9f2 100644 --- a/src/soc/intel/apollolake/acpi/pcie_port.asl +++ b/src/soc/intel/apollolake/acpi/pcie_port.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Include in each PCIe Root Port device */ diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl index e445f01bc9..da71008a2f 100644 --- a/src/soc/intel/apollolake/acpi/platform.asl +++ b/src/soc/intel/apollolake/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 12c4c6e985..946a1cecc2 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index b3b975a2b3..fcf6b0dcad 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0) { /* 0xD6- is the port address */ diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 52ef7bf3b5..200f18bdf3 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* XHCI Controller 0:15.0 */ Device (XHCI) { diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 080b2c277b..d84af562c5 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index f019c1ee97..2644f5ca8a 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/i2c.c b/src/soc/intel/apollolake/i2c.c index ec5424e798..15b91ea3c5 100644 --- a/src/soc/intel/apollolake/i2c.c +++ b/src/soc/intel/apollolake/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 32a9b565ab..6a7a9bdee4 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ diff --git a/src/soc/intel/apollolake/include/soc/itss.h b/src/soc/intel/apollolake/include/soc/itss.h index dec6b53104..43a915795a 100644 --- a/src/soc/intel/apollolake/include/soc/itss.h +++ b/src/soc/intel/apollolake/include/soc/itss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_APOLLOLAKE_ITSS_H_ #define _SOC_APOLLOLAKE_ITSS_H_ diff --git a/src/soc/intel/apollolake/include/soc/me.h b/src/soc/intel/apollolake/include/soc/me.h index 529240d0ac..88997b0420 100644 --- a/src/soc/intel/apollolake/include/soc/me.h +++ b/src/soc/intel/apollolake/include/soc/me.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _APOLLOLAKE_ME_H_ #define _APOLLOLAKE_ME_H_ diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 6c0f36609f..ed301371fa 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_APOLLOLAKE_MEMINIT_H_ #define _SOC_APOLLOLAKE_MEMINIT_H_ diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h index 8bd1122a5f..cfabf141ab 100644 --- a/src/soc/intel/apollolake/include/soc/p2sb.h +++ b/src/soc/intel/apollolake/include/soc/p2sb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_P2SB_H_ #define _SOC_P2SB_H_ diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 8821c96fdd..46067b60c5 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_APL_PCR_H #define SOC_INTEL_APL_PCR_H diff --git a/src/soc/intel/apollolake/include/soc/pnpconfig.h b/src/soc/intel/apollolake/include/soc/pnpconfig.h index 883fed0ef9..82f6b9552b 100644 --- a/src/soc/intel/apollolake/include/soc/pnpconfig.h +++ b/src/soc/intel/apollolake/include/soc/pnpconfig.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_APOLLOLAKE_PNPCONFIG_H_ #define _SOC_APOLLOLAKE_PNPCONFIG_H_ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 9288934a11..10b36fe436 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_ diff --git a/src/soc/intel/apollolake/include/soc/soc_chip.h b/src/soc/intel/apollolake/include/soc/soc_chip.h index e83f0e71dd..65867546f5 100644 --- a/src/soc/intel/apollolake/include/soc/soc_chip.h +++ b/src/soc/intel/apollolake/include/soc/soc_chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_APOLLOLAKE_SOC_CHIP_H_ #define _SOC_APOLLOLAKE_SOC_CHIP_H_ diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 2371615681..5aeaa16766 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index aac34b35c8..057fdb4207 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 86045792f1..9a819126e3 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c index cb0b9dae11..ca935f4478 100644 --- a/src/soc/intel/apollolake/pnpconfig.c +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c index 37501b7efb..bd0a68fb44 100644 --- a/src/soc/intel/apollolake/report_platform.c +++ b/src/soc/intel/apollolake/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 80f1365f36..c173879cfb 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c index 9626dccb22..68c9bcad2f 100644 --- a/src/soc/intel/apollolake/sd.c +++ b/src/soc/intel/apollolake/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "chip.h" diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 83cd5e64b4..6785688981 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c index 0f5a02eccf..2ad59febdf 100644 --- a/src/soc/intel/apollolake/xdci.c +++ b/src/soc/intel/apollolake/xdci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c index 1b9f932d73..fd08df9cf0 100644 --- a/src/soc/intel/apollolake/xhci.c +++ b/src/soc/intel/apollolake/xhci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From 8559277fc97874becebfb6c07c224851aa8cdabd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:47:25 +0200 Subject: [PATCH 0890/1463] soc/intel/xeon_sp: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I703a656c397345025dab398fb642f3de7bbb61fe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40220 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl | 15 ++------------- src/soc/intel/xeon_sp/skx/include/soc/nvs.h | 16 ++-------------- 2 files changed, 4 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl index 613e0848db..d966db98c6 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h index 613775c759..352bc27dad 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ From 3bd1e3db9c5ba6b156142841efefee55c3985c2e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:47:17 +0200 Subject: [PATCH 0891/1463] soc/intel/skylake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7354edb15ca9cbe181739bc2a148f16bb85ab118 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40218 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/skylake/acpi.c | 15 ++------------- src/soc/intel/skylake/acpi/dptf/charger.asl | 15 ++------------- src/soc/intel/skylake/acpi/dptf/cpu.asl | 15 ++------------- src/soc/intel/skylake/acpi/dptf/dptf.asl | 15 ++------------- src/soc/intel/skylake/acpi/dptf/fan.asl | 15 ++------------- src/soc/intel/skylake/acpi/dptf/thermal.asl | 15 ++------------- src/soc/intel/skylake/acpi/globalnvs.asl | 15 ++------------- src/soc/intel/skylake/acpi/gpio.asl | 15 ++------------- src/soc/intel/skylake/acpi/ipu.asl | 15 ++------------- src/soc/intel/skylake/acpi/irqlinks.asl | 15 ++------------- src/soc/intel/skylake/acpi/lpc.asl | 15 ++------------- src/soc/intel/skylake/acpi/pch.asl | 15 ++------------- src/soc/intel/skylake/acpi/pch_hda.asl | 15 ++------------- src/soc/intel/skylake/acpi/pci_irqs.asl | 15 ++------------- src/soc/intel/skylake/acpi/pcie.asl | 15 ++------------- src/soc/intel/skylake/acpi/platform.asl | 15 ++------------- src/soc/intel/skylake/acpi/pmc.asl | 15 ++------------- src/soc/intel/skylake/acpi/scs.asl | 15 ++------------- src/soc/intel/skylake/acpi/serialio.asl | 15 ++------------- src/soc/intel/skylake/acpi/smbus.asl | 15 ++------------- src/soc/intel/skylake/acpi/systemagent.asl | 15 ++------------- src/soc/intel/skylake/acpi/xhci.asl | 15 ++------------- src/soc/intel/skylake/bootblock/bootblock.c | 15 ++------------- src/soc/intel/skylake/bootblock/cpu.c | 15 ++------------- src/soc/intel/skylake/bootblock/pch.c | 15 ++------------- .../intel/skylake/bootblock/report_platform.c | 15 ++------------- src/soc/intel/skylake/chip.c | 15 ++------------- src/soc/intel/skylake/chip.h | 15 ++------------- src/soc/intel/skylake/cpu.c | 15 ++------------- src/soc/intel/skylake/elog.c | 15 ++------------- src/soc/intel/skylake/finalize.c | 15 ++------------- src/soc/intel/skylake/gpio.c | 15 ++------------- src/soc/intel/skylake/graphics.c | 15 ++------------- src/soc/intel/skylake/i2c.c | 15 ++------------- src/soc/intel/skylake/include/soc/acpi.h | 15 ++------------- src/soc/intel/skylake/include/soc/bootblock.h | 15 ++------------- src/soc/intel/skylake/include/soc/cpu.h | 15 ++------------- src/soc/intel/skylake/include/soc/device_nvs.h | 15 ++------------- src/soc/intel/skylake/include/soc/gpe.h | 15 ++------------- src/soc/intel/skylake/include/soc/gpio.h | 15 ++------------- src/soc/intel/skylake/include/soc/gpio_defs.h | 15 ++------------- .../intel/skylake/include/soc/gpio_pch_h_defs.h | 15 ++------------- .../intel/skylake/include/soc/gpio_soc_defs.h | 15 ++------------- src/soc/intel/skylake/include/soc/interrupt.h | 15 ++------------- src/soc/intel/skylake/include/soc/iomap.h | 15 ++------------- src/soc/intel/skylake/include/soc/irq.h | 15 ++------------- src/soc/intel/skylake/include/soc/itss.h | 15 ++------------- src/soc/intel/skylake/include/soc/me.h | 15 ++------------- src/soc/intel/skylake/include/soc/msr.h | 15 ++------------- src/soc/intel/skylake/include/soc/nhlt.h | 15 ++------------- src/soc/intel/skylake/include/soc/nvs.h | 15 ++------------- src/soc/intel/skylake/include/soc/p2sb.h | 15 ++------------- src/soc/intel/skylake/include/soc/pch.h | 15 ++------------- src/soc/intel/skylake/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/skylake/include/soc/pcr_ids.h | 15 ++------------- src/soc/intel/skylake/include/soc/pm.h | 15 ++------------- src/soc/intel/skylake/include/soc/pmc.h | 15 ++------------- src/soc/intel/skylake/include/soc/ramstage.h | 15 ++------------- src/soc/intel/skylake/include/soc/romstage.h | 15 ++------------- src/soc/intel/skylake/include/soc/serialio.h | 15 ++------------- src/soc/intel/skylake/include/soc/smbus.h | 15 ++------------- src/soc/intel/skylake/include/soc/soc_chip.h | 15 ++------------- src/soc/intel/skylake/include/soc/systemagent.h | 15 ++------------- src/soc/intel/skylake/include/soc/usb.h | 15 ++------------- src/soc/intel/skylake/include/soc/vr_config.h | 15 ++------------- src/soc/intel/skylake/irq.c | 15 ++------------- src/soc/intel/skylake/lockdown.c | 15 ++------------- src/soc/intel/skylake/lpc.c | 15 ++------------- src/soc/intel/skylake/me.c | 15 ++------------- src/soc/intel/skylake/nhlt/dmic.c | 15 ++------------- src/soc/intel/skylake/nhlt/max98357.c | 15 ++------------- src/soc/intel/skylake/nhlt/max98373.c | 15 ++------------- src/soc/intel/skylake/nhlt/max98927.c | 15 ++------------- src/soc/intel/skylake/nhlt/nau88l25.c | 15 ++------------- src/soc/intel/skylake/nhlt/rt5514.c | 15 ++------------- src/soc/intel/skylake/nhlt/rt5663.c | 15 ++------------- src/soc/intel/skylake/nhlt/ssm4567.c | 15 ++------------- src/soc/intel/skylake/p2sb.c | 15 ++------------- src/soc/intel/skylake/pmc.c | 15 ++------------- src/soc/intel/skylake/pmutil.c | 15 ++------------- src/soc/intel/skylake/reset.c | 15 ++------------- src/soc/intel/skylake/romstage/pch.c | 15 ++------------- src/soc/intel/skylake/romstage/romstage.c | 15 ++------------- src/soc/intel/skylake/romstage/systemagent.c | 15 ++------------- src/soc/intel/skylake/sd.c | 15 ++------------- src/soc/intel/skylake/smihandler.c | 15 ++------------- src/soc/intel/skylake/smmrelocate.c | 15 ++------------- src/soc/intel/skylake/systemagent.c | 15 ++------------- src/soc/intel/skylake/uart.c | 15 ++------------- src/soc/intel/skylake/vr_config.c | 16 ++-------------- src/soc/intel/skylake/xhci.c | 15 ++------------- 91 files changed, 182 insertions(+), 1184 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e6723aab1c..dee44b6253 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/acpi/dptf/charger.asl b/src/soc/intel/skylake/acpi/dptf/charger.asl index ba728b41a3..844f287afb 100644 --- a/src/soc/intel/skylake/acpi/dptf/charger.asl +++ b/src/soc/intel/skylake/acpi/dptf/charger.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TCHG) { diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index b069919ed3..b1bc40ed64 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DPTF_CPU_PASSIVE #define DPTF_CPU_PASSIVE 80 diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index 0a2e7ab4f4..2d78190364 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (DPTF) { diff --git a/src/soc/intel/skylake/acpi/dptf/fan.asl b/src/soc/intel/skylake/acpi/dptf/fan.asl index 4a15156de5..bff81ade71 100644 --- a/src/soc/intel/skylake/acpi/dptf/fan.asl +++ b/src/soc/intel/skylake/acpi/dptf/fan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TFN1) { diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 8dda3a84d4..a8c9eac9e7 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 796704f633..7c40630de7 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index d1b780193e..81bff33e74 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #define GPIOTXSTATE_MASK 0x1 diff --git a/src/soc/intel/skylake/acpi/ipu.asl b/src/soc/intel/skylake/acpi/ipu.asl index 9abc1a4ee8..fbb609b48c 100644 --- a/src/soc/intel/skylake/acpi/ipu.asl +++ b/src/soc/intel/skylake/acpi/ipu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index c4a5d71387..1922288f96 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * PIRQ routing control is in PCR ITSS region. diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index f9712f3775..4f237ee522 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 #include diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 7487920274..27ab0826e9 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/acpi/pch_hda.asl b/src/soc/intel/skylake/acpi/pch_hda.asl index 4b86a92c3b..cde4300a2b 100644 --- a/src/soc/intel/skylake/acpi/pch_hda.asl +++ b/src/soc/intel/skylake/acpi/pch_hda.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Audio Controller - Device 31, Function 3 */ diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl index 8c0b62a9b9..0018af6d42 100644 --- a/src/soc/intel/skylake/acpi/pci_irqs.asl +++ b/src/soc/intel/skylake/acpi/pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index b28ea44323..07a475e6d9 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH PCIe support */ diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl index 3cfc308b1b..199300723c 100644 --- a/src/soc/intel/skylake/acpi/platform.asl +++ b/src/soc/intel/skylake/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/skylake/acpi/pmc.asl b/src/soc/intel/skylake/acpi/pmc.asl index da58355467..2057572447 100644 --- a/src/soc/intel/skylake/acpi/pmc.asl +++ b/src/soc/intel/skylake/acpi/pmc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PMC) { diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 8fc4f3fb6b..a8aa360353 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Storage Controllers */ diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index 006e7134cc..ff252f02a8 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Serial IO Devices */ diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl index abeb9ff05e..81bb04f227 100644 --- a/src/soc/intel/skylake/acpi/smbus.asl +++ b/src/soc/intel/skylake/acpi/smbus.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SMBus Controller 0:1f.3 diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 92d0d545fc..ba2a44ff58 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 5e285c971c..b8adf0b23b 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * USB Port Wake Enable (UPWE) on usb attach/detach diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 5c0daba596..15f250ded5 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 3a44ee5421..0ce54258c0 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 83224e8125..1603630910 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index e1620e7c25..46cec8d150 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 40d5b1d66e..c3b22e2e0d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1170b57704..1b9cc4a177 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CHIP_H_ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 965f7495d9..ad26c57958 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index d32a488f4e..484588e325 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8f980989c2..4009fd7c32 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index c67c0e9e7b..028371e7cc 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 5f2fddfd56..c338a674e0 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 21629b087a..f986168be6 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 447d53c5a0..0d3ade0b11 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 63dc8546f6..4b1bae8781 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SKYLAKE_BOOTBLOCK_H_ #define _SOC_SKYLAKE_BOOTBLOCK_H_ diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 43fc714305..f6122a2eb0 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CPU_H_ #define _SOC_CPU_H_ diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h index fbfc7de6fe..79b766f3a8 100644 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ b/src/soc/intel/skylake/include/soc/device_nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_DEVICE_NVS_H_ #define _SOC_DEVICE_NVS_H_ diff --git a/src/soc/intel/skylake/include/soc/gpe.h b/src/soc/intel/skylake/include/soc/gpe.h index e643544f5b..97ffa5d543 100644 --- a/src/soc/intel/skylake/include/soc/gpe.h +++ b/src/soc/intel/skylake/include/soc/gpe.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 4d85e183d5..1ee1e3bf47 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPIO_H_ #define _SOC_GPIO_H_ diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 3568df5535..0ba9d5e3cb 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPIO_DEFS_H_ #define _SOC_GPIO_DEFS_H_ diff --git a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h index e5200c21fe..dc70bd9d50 100644 --- a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPIO_PCH_H_DEFS_H_ #define _SOC_GPIO_PCH_H_DEFS_H_ diff --git a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h index 0dca200a72..7729a1662b 100644 --- a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPIO_SOC_DEFS_H_ #define _SOC_GPIO_SOC_DEFS_H_ diff --git a/src/soc/intel/skylake/include/soc/interrupt.h b/src/soc/intel/skylake/include/soc/interrupt.h index a0c5b06d12..f3d1f6afec 100644 --- a/src/soc/intel/skylake/include/soc/interrupt.h +++ b/src/soc/intel/skylake/include/soc/interrupt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTERRUPT_H_ #define _INTERRUPT_H_ diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index efd4ff8a73..1a61036137 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IOMAP_H_ #define _SOC_IOMAP_H_ diff --git a/src/soc/intel/skylake/include/soc/irq.h b/src/soc/intel/skylake/include/soc/irq.h index 30730cab9d..d5069fee1e 100644 --- a/src/soc/intel/skylake/include/soc/irq.h +++ b/src/soc/intel/skylake/include/soc/irq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h index 5cf96ff874..5536e4d82a 100644 --- a/src/soc/intel/skylake/include/soc/itss.h +++ b/src/soc/intel/skylake/include/soc/itss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_SKL_ITSS_H #define SOC_INTEL_SKL_ITSS_H diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index ff212a1c2e..f80b8cab98 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SKYLAKE_ME_H_ #define _SKYLAKE_ME_H_ diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 348120a392..17cd4946b9 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index b33a30faed..1a4dc70d91 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NHLT_H_ #define _SOC_NHLT_H_ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index e6ae988c45..480805b1fa 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index e2f0a5bf4c..f636451b9d 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_P2SB_H_ #define _SOC_P2SB_H_ diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 9a99c823a8..72150f8323 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PCH_H_ #define _SOC_PCH_H_ diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 59ee1e2a97..96e798bb82 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SKYLAKE_PCI_DEVS_H_ #define _SOC_SKYLAKE_PCI_DEVS_H_ diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index ee12f4847f..1a4909e007 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_SKL_PCR_H #define SOC_INTEL_SKL_PCR_H diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 3e26b1669e..94b8d3e447 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 9f5ccc97b4..3107a92202 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PMC_H_ #define _SOC_PMC_H_ diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h index 87198f4c45..23ef3125a7 100644 --- a/src/soc/intel/skylake/include/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 62b0bec377..5b01625ccd 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ diff --git a/src/soc/intel/skylake/include/soc/serialio.h b/src/soc/intel/skylake/include/soc/serialio.h index 76e5adeaeb..a8b33f03d3 100644 --- a/src/soc/intel/skylake/include/soc/serialio.h +++ b/src/soc/intel/skylake/include/soc/serialio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index 72e39441bb..b9e0c56ece 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SMBUS_H_ #define _SOC_SMBUS_H_ diff --git a/src/soc/intel/skylake/include/soc/soc_chip.h b/src/soc/intel/skylake/include/soc/soc_chip.h index 43807be765..721f555d8b 100644 --- a/src/soc/intel/skylake/include/soc/soc_chip.h +++ b/src/soc/intel/skylake/include/soc/soc_chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SKYLAKE_SOC_CHIP_H_ #define _SOC_SKYLAKE_SOC_CHIP_H_ diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 477d853ab5..7d88c8b0cc 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_SKYLAKE_SYSTEMAGENT_H #define SOC_SKYLAKE_SYSTEMAGENT_H diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index 947212fc95..ac771bfe3f 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_USB_H_ diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 7a0c120889..6779139993 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* VR Settings for each domain */ diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 533a4e2529..5c5a80ceb9 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 4db91b66cc..37fd8175b2 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 0db3c80a3c..75b52c91c3 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 78e2efc8b5..1607e6bc7e 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/nhlt/dmic.c b/src/soc/intel/skylake/nhlt/dmic.c index d3427326da..e9d5045d09 100644 --- a/src/soc/intel/skylake/nhlt/dmic.c +++ b/src/soc/intel/skylake/nhlt/dmic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/nhlt/max98357.c b/src/soc/intel/skylake/nhlt/max98357.c index ef106c2e3e..0c99dbb9e3 100644 --- a/src/soc/intel/skylake/nhlt/max98357.c +++ b/src/soc/intel/skylake/nhlt/max98357.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 10a12b9a0a..ddfe2ae01c 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c index 53f1d531c6..18b4107cfb 100644 --- a/src/soc/intel/skylake/nhlt/max98927.c +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c index b82afbf2a5..d9956e55b8 100644 --- a/src/soc/intel/skylake/nhlt/nau88l25.c +++ b/src/soc/intel/skylake/nhlt/nau88l25.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c index bbb2614f9c..95d39a32f3 100644 --- a/src/soc/intel/skylake/nhlt/rt5514.c +++ b/src/soc/intel/skylake/nhlt/rt5514.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c index c7842aab5e..d8126fdb25 100644 --- a/src/soc/intel/skylake/nhlt/rt5663.c +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/nhlt/ssm4567.c b/src/soc/intel/skylake/nhlt/ssm4567.c index 2651dcb447..918d98baf1 100644 --- a/src/soc/intel/skylake/nhlt/ssm4567.c +++ b/src/soc/intel/skylake/nhlt/ssm4567.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c index 0eb06fd983..09fc90e54c 100644 --- a/src/soc/intel/skylake/p2sb.c +++ b/src/soc/intel/skylake/p2sb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 8f4dac47ef..be0a57ae75 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 6f837e3b91..649cb25b58 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Helper functions for dealing with power management registers diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index 9c75228dbb..b6123e6fd2 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c index c05c84820a..7b9972bcc0 100644 --- a/src/soc/intel/skylake/romstage/pch.c +++ b/src/soc/intel/skylake/romstage/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index d5db8e64cc..2a6b71c75a 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 2525bfcda9..1933be3757 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index c431674491..70fc62fe94 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "chip.h" diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 35797e657d..d619d3eafb 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index fe697ccdc3..3d34616968 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 64be7c4349..9a4c4de287 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 61ff00e511..c74794b93d 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 57c55eca76..c7db74a076 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c index 073125da50..78aadf7388 100644 --- a/src/soc/intel/skylake/xhci.c +++ b/src/soc/intel/skylake/xhci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From ba38f37d185cd2c795e7f0247e815a1c2dd3df98 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:46:45 +0200 Subject: [PATCH 0892/1463] soc/intel/braswell: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I45d746ed374361036d59167293a90d8e557754fa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40210 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/braswell/acpi.c | 15 ++------------- src/soc/intel/braswell/acpi/device_nvs.asl | 16 ++-------------- src/soc/intel/braswell/acpi/dptf/charger.asl | 15 ++------------- src/soc/intel/braswell/acpi/dptf/cpu.asl | 16 ++-------------- src/soc/intel/braswell/acpi/dptf/dptf.asl | 15 ++------------- src/soc/intel/braswell/acpi/dptf/thermal.asl | 16 ++-------------- src/soc/intel/braswell/acpi/dptf/wifi.asl | 15 ++------------- src/soc/intel/braswell/acpi/dptf/wwan.asl | 15 ++------------- src/soc/intel/braswell/acpi/globalnvs.asl | 16 ++-------------- src/soc/intel/braswell/acpi/gpio.asl | 16 ++-------------- src/soc/intel/braswell/acpi/irq_helper.h | 15 ++------------- src/soc/intel/braswell/acpi/irqlinks.asl | 16 ++-------------- src/soc/intel/braswell/acpi/irqroute.asl | 15 ++------------- src/soc/intel/braswell/acpi/lpc.asl | 16 ++-------------- src/soc/intel/braswell/acpi/lpe.asl | 16 ++-------------- src/soc/intel/braswell/acpi/lpss.asl | 16 ++-------------- src/soc/intel/braswell/acpi/platform.asl | 15 ++------------- src/soc/intel/braswell/acpi/scc.asl | 16 ++-------------- src/soc/intel/braswell/acpi/southcluster.asl | 16 ++-------------- src/soc/intel/braswell/acpi/xhci.asl | 16 ++-------------- src/soc/intel/braswell/bootblock/bootblock.c | 15 ++------------- src/soc/intel/braswell/chip.c | 15 ++------------- src/soc/intel/braswell/chip.h | 15 ++------------- src/soc/intel/braswell/cpu.c | 15 ++------------- src/soc/intel/braswell/elog.c | 16 ++-------------- src/soc/intel/braswell/emmc.c | 15 ++------------- src/soc/intel/braswell/gfx.c | 15 ++------------- src/soc/intel/braswell/gpio.c | 15 ++------------- src/soc/intel/braswell/gpio_support.c | 15 ++------------- src/soc/intel/braswell/include/soc/acpi.h | 15 ++------------- src/soc/intel/braswell/include/soc/device_nvs.h | 15 ++------------- src/soc/intel/braswell/include/soc/ehci.h | 15 ++------------- src/soc/intel/braswell/include/soc/gfx.h | 15 ++------------- src/soc/intel/braswell/include/soc/gpio.h | 15 ++------------- src/soc/intel/braswell/include/soc/gpio_defs.h | 15 ++------------- src/soc/intel/braswell/include/soc/hda.h | 15 ++------------- src/soc/intel/braswell/include/soc/iomap.h | 15 ++------------- src/soc/intel/braswell/include/soc/iosf.h | 15 ++------------- src/soc/intel/braswell/include/soc/irq.h | 15 ++------------- src/soc/intel/braswell/include/soc/lpc.h | 15 ++------------- src/soc/intel/braswell/include/soc/msr.h | 15 ++------------- src/soc/intel/braswell/include/soc/nvs.h | 15 ++------------- src/soc/intel/braswell/include/soc/pattrs.h | 15 ++------------- src/soc/intel/braswell/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/braswell/include/soc/pcie.h | 15 ++------------- src/soc/intel/braswell/include/soc/pm.h | 15 ++------------- src/soc/intel/braswell/include/soc/ramstage.h | 15 ++------------- src/soc/intel/braswell/include/soc/romstage.h | 15 ++------------- src/soc/intel/braswell/include/soc/sata.h | 15 ++------------- src/soc/intel/braswell/include/soc/smbus.h | 15 ++------------- src/soc/intel/braswell/include/soc/smm.h | 15 ++------------- src/soc/intel/braswell/include/soc/spi.h | 15 ++------------- src/soc/intel/braswell/include/soc/xhci.h | 15 ++------------- src/soc/intel/braswell/iosf.c | 15 ++------------- src/soc/intel/braswell/lpc_init.c | 15 ++------------- src/soc/intel/braswell/lpe.c | 15 ++------------- src/soc/intel/braswell/lpss.c | 15 ++------------- src/soc/intel/braswell/memmap.c | 15 ++------------- src/soc/intel/braswell/northcluster.c | 15 ++------------- src/soc/intel/braswell/pcie.c | 15 ++------------- src/soc/intel/braswell/placeholders.c | 15 ++------------- src/soc/intel/braswell/pmutil.c | 15 ++------------- src/soc/intel/braswell/ramstage.c | 15 ++------------- src/soc/intel/braswell/romstage/romstage.c | 15 ++------------- src/soc/intel/braswell/sata.c | 15 ++------------- src/soc/intel/braswell/scc.c | 15 ++------------- src/soc/intel/braswell/sd.c | 15 ++------------- src/soc/intel/braswell/smbus.c | 15 ++------------- src/soc/intel/braswell/smihandler.c | 15 ++------------- src/soc/intel/braswell/smm.c | 16 ++-------------- src/soc/intel/braswell/southcluster.c | 15 ++------------- src/soc/intel/braswell/tsc_freq.c | 15 ++------------- src/soc/intel/braswell/xhci.c | 16 ++-------------- 73 files changed, 146 insertions(+), 964 deletions(-) diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 8142e1bed6..b4e4746437 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index 312d2bbe92..0e96a7540e 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Device Enabled in ACPI Mode */ diff --git a/src/soc/intel/braswell/acpi/dptf/charger.asl b/src/soc/intel/braswell/acpi/dptf/charger.asl index 51c0e1df5b..844f287afb 100644 --- a/src/soc/intel/braswell/acpi/dptf/charger.asl +++ b/src/soc/intel/braswell/acpi/dptf/charger.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TCHG) { diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 1236c847cb..0e3b959a87 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef DPTF_CPU_PASSIVE #define DPTF_CPU_PASSIVE 80 diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl index c86ca1128d..6616856ec6 100644 --- a/src/soc/intel/braswell/acpi/dptf/dptf.asl +++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (DPTF) { diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 397f354d21..4a81368b62 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER diff --git a/src/soc/intel/braswell/acpi/dptf/wifi.asl b/src/soc/intel/braswell/acpi/dptf/wifi.asl index e47db9f469..af6ed87a81 100644 --- a/src/soc/intel/braswell/acpi/dptf/wifi.asl +++ b/src/soc/intel/braswell/acpi/dptf/wifi.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (WIFI) { diff --git a/src/soc/intel/braswell/acpi/dptf/wwan.asl b/src/soc/intel/braswell/acpi/dptf/wwan.asl index 3dead66fb3..0a83b1664f 100644 --- a/src/soc/intel/braswell/acpi/dptf/wwan.asl +++ b/src/soc/intel/braswell/acpi/dptf/wwan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (WWAN) { diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index caf8648c8c..860f4d7d80 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl index 5ed5c777c9..31b08f6511 100644 --- a/src/soc/intel/braswell/acpi/gpio.asl +++ b/src/soc/intel/braswell/acpi/gpio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/acpi/irq_helper.h b/src/soc/intel/braswell/acpi/irq_helper.h index 11b0f0a5db..b585972535 100644 --- a/src/soc/intel/braswell/acpi/irq_helper.h +++ b/src/soc/intel/braswell/acpi/irq_helper.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef PCI_DEV_PIRQ_ROUTES #undef ACPI_DEV_APIC_IRQ diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl index 2050695194..7e8f6a6bfa 100644 --- a/src/soc/intel/braswell/acpi/irqlinks.asl +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl index 60c2cc8899..e30b173a9f 100644 --- a/src/soc/intel/braswell/acpi/irqroute.asl +++ b/src/soc/intel/braswell/acpi/irqroute.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* PCI Interrupt Routing */ Method(_PRT) diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 000be38b75..fea1a6c4ad 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel LPC Bus Device - 0:1f.0 */ diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index f4848704d4..90cc1e7b66 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LPEA) { diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index add7270a5d..8feb2cd4eb 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The below definitions are used for customization * Some boards/devices may need different data hold time diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl index 549bd54abc..44e8e0679f 100644 --- a/src/soc/intel/braswell/acpi/platform.asl +++ b/src/soc/intel/braswell/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 1f0f9a42ad..920e1ca685 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EMMC) { diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index c1807a7c5b..a3b4d922ea 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/acpi/xhci.asl b/src/soc/intel/braswell/acpi/xhci.asl index 0ace24223f..2ae1e21605 100644 --- a/src/soc/intel/braswell/acpi/xhci.asl +++ b/src/soc/intel/braswell/acpi/xhci.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (XHCI) { diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index aa8df6ba5e..2426ed95fa 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d63bb77dca..d1540f844c 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 5f1aaee3be..76eb50e493 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * The devicetree parser expects chip.h to reside directly in the path diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 0221478f18..bb77742760 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 1eef5fdaac..615117c613 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 58a3fef1b5..d132a9777b 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 12fe6427f0..d6671f6936 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "chip.h" #include diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index a6273f39ea..08e3510408 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c index d2abccc259..f235540e46 100644 --- a/src/soc/intel/braswell/gpio_support.c +++ b/src/soc/intel/braswell/gpio_support.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 4999dd7d91..6c352b91ad 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 64bb05e74c..9944ccf2f9 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_DEVICE_NVS_H_ #define _SOC_DEVICE_NVS_H_ diff --git a/src/soc/intel/braswell/include/soc/ehci.h b/src/soc/intel/braswell/include/soc/ehci.h index 864bff5817..9eb32cd909 100644 --- a/src/soc/intel/braswell/include/soc/ehci.h +++ b/src/soc/intel/braswell/include/soc/ehci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_EHCI_H_ #define _SOC_EHCI_H_ diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h index 436b97e065..a4b349e5cc 100644 --- a/src/soc/intel/braswell/include/soc/gfx.h +++ b/src/soc/intel/braswell/include/soc/gfx.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GFX_H_ #define _SOC_GFX_H_ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index e40a9517b3..9ce75d2268 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPIO_H_ #define _SOC_GPIO_H_ diff --git a/src/soc/intel/braswell/include/soc/gpio_defs.h b/src/soc/intel/braswell/include/soc/gpio_defs.h index b85fc22573..77183093c0 100644 --- a/src/soc/intel/braswell/include/soc/gpio_defs.h +++ b/src/soc/intel/braswell/include/soc/gpio_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPIO_DEFS_H_ #define _SOC_GPIO_DEFS_H_ diff --git a/src/soc/intel/braswell/include/soc/hda.h b/src/soc/intel/braswell/include/soc/hda.h index fee65eaf75..b98de0f3bb 100644 --- a/src/soc/intel/braswell/include/soc/hda.h +++ b/src/soc/intel/braswell/include/soc/hda.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_HDA_H_ #define _SOC_HDA_H_ diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h index 019d5f0a08..d498c1e938 100644 --- a/src/soc/intel/braswell/include/soc/iomap.h +++ b/src/soc/intel/braswell/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IOMAP_H_ #define _SOC_IOMAP_H_ diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index 5a36d4077d..a95acd48a8 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IOSF_H_ #define _SOC_IOSF_H_ diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index fa51100803..dd4619d10c 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index 7945caa893..ee121a4234 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_LPC_H_ #define _SOC_LPC_H_ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 90a62d3574..09a702ea7a 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 67ee369829..32d6b8ab9f 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h index 76ac54bc29..1a1253318f 100644 --- a/src/soc/intel/braswell/include/soc/pattrs.h +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PATTRS_H_ #define _SOC_PATTRS_H_ diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h index 4bf488e672..b8ee63b43f 100644 --- a/src/soc/intel/braswell/include/soc/pci_devs.h +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ diff --git a/src/soc/intel/braswell/include/soc/pcie.h b/src/soc/intel/braswell/include/soc/pcie.h index 98cf64d02d..6184c6d6a5 100644 --- a/src/soc/intel/braswell/include/soc/pcie.h +++ b/src/soc/intel/braswell/include/soc/pcie.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PCIE_H_ #define _SOC_PCIE_H_ diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index df131538f3..f3397aaa4b 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index aa968b33c1..e14aec71cc 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index cb9b27d825..42ffd32b8d 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ diff --git a/src/soc/intel/braswell/include/soc/sata.h b/src/soc/intel/braswell/include/soc/sata.h index add352c7a7..093422f4dc 100644 --- a/src/soc/intel/braswell/include/soc/sata.h +++ b/src/soc/intel/braswell/include/soc/sata.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SATA_H_ #define _SOC_SATA_H_ diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h index 717c208ddb..2cf09ad2b2 100644 --- a/src/soc/intel/braswell/include/soc/smbus.h +++ b/src/soc/intel/braswell/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SMBUS_H_ #define _SOC_SMBUS_H_ diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 8e2f3757c2..721089d9ea 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SMM_H_ #define _SOC_SMM_H_ diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index ab4f3202fd..699bb542cf 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SPI_H_ #define _SOC_SPI_H_ diff --git a/src/soc/intel/braswell/include/soc/xhci.h b/src/soc/intel/braswell/include/soc/xhci.h index ef16d242e3..d3ca6768a4 100644 --- a/src/soc/intel/braswell/include/soc/xhci.h +++ b/src/soc/intel/braswell/include/soc/xhci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_XHCI_H #define _SOC_XHCI_H diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 9d29e8d599..bb13ca5fee 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index 8b7c1eab34..ce3b030342 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index cf61120895..9c4d2b1819 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 24377af311..582c3237ce 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 28b9e0e5e6..0c5983f3d2 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 4acef25d45..3222faf814 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 4745be9be9..ffa9a49d23 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "chip.h" #include diff --git a/src/soc/intel/braswell/placeholders.c b/src/soc/intel/braswell/placeholders.c index 1175721a2b..71e2a634c8 100644 --- a/src/soc/intel/braswell/placeholders.c +++ b/src/soc/intel/braswell/placeholders.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 016c45cccc..1ca8bdaccc 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 3e1625ff60..e2d9a3b101 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index d8afecd2c3..c358ff7640 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index 4e608194b1..a87b20f349 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 6373cd51f2..0149e2546f 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 97983f7494..9684aaa297 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c index 9ef83a3c39..bceba49070 100644 --- a/src/soc/intel/braswell/smbus.c +++ b/src/soc/intel/braswell/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index a33c9af96e..e96f452341 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index ef801bda70..b900366989 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index c166371091..50ff608cc0 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 13992d46d1..dd53deba9c 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c index 3a2626ffa7..c33ad638c6 100644 --- a/src/soc/intel/braswell/xhci.c +++ b/src/soc/intel/braswell/xhci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 0612b27b9d81338c64cdee51cfd2c792d9e5e092 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:46:56 +0200 Subject: [PATCH 0893/1463] soc/intel/common: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/intel/common/acpi/acpi_debug.asl | 15 ++------------- src/soc/intel/common/acpi/acpi_wake_source.asl | 15 ++------------- src/soc/intel/common/acpi/dptf/charger.asl | 15 ++------------- src/soc/intel/common/acpi/dptf/cpu.asl | 15 ++------------- src/soc/intel/common/acpi/dptf/dptf.asl | 15 ++------------- src/soc/intel/common/acpi/dptf/fan.asl | 15 ++------------- src/soc/intel/common/acpi/dptf/thermal.asl | 15 ++------------- src/soc/intel/common/acpi/pci_osc.asl | 15 ++------------- src/soc/intel/common/acpi/pcr.asl | 15 ++------------- src/soc/intel/common/acpi/platform.asl | 15 ++------------- src/soc/intel/common/acpi/sgx.asl | 15 ++------------- src/soc/intel/common/acpi/wifi.asl | 15 ++------------- src/soc/intel/common/acpi_wake_source.c | 15 ++------------- .../intel/common/block/acpi/acpi/globalnvs.asl | 15 ++------------- src/soc/intel/common/block/acpi/acpi/ipu.asl | 15 ++------------- src/soc/intel/common/block/acpi/acpi/lpc.asl | 15 ++------------- src/soc/intel/common/block/acpi/acpi/pmc.asl | 16 ++-------------- src/soc/intel/common/block/chip/chip.c | 15 ++------------- .../intel/common/block/cpu/car/cache_as_ram.S | 16 ++-------------- src/soc/intel/common/block/cpu/car/exit_car.S | 16 ++-------------- .../intel/common/block/cpu/car/exit_car_fsp.S | 16 ++-------------- src/soc/intel/common/block/cpu/cpulib.c | 15 ++------------- src/soc/intel/common/block/cpu/mp_init.c | 15 ++------------- src/soc/intel/common/block/cse/cse.c | 15 ++------------- src/soc/intel/common/block/cse/disable_heci.c | 15 ++------------- src/soc/intel/common/block/dsp/dsp.c | 15 ++------------- src/soc/intel/common/block/fast_spi/fast_spi.c | 15 ++------------- .../intel/common/block/fast_spi/fast_spi_def.h | 15 ++------------- .../intel/common/block/fast_spi/fast_spi_flash.c | 15 ++------------- src/soc/intel/common/block/hda/hda.c | 15 ++------------- src/soc/intel/common/block/i2c/i2c.c | 15 ++------------- src/soc/intel/common/block/imc/imc.c | 15 ++------------- .../intel/common/block/include/intelblocks/cfg.h | 15 ++------------- .../common/block/include/intelblocks/cpulib.h | 15 ++------------- .../common/block/include/intelblocks/fast_spi.h | 15 ++------------- .../common/block/include/intelblocks/graphics.h | 15 ++------------- .../common/block/include/intelblocks/gspi.h | 15 ++------------- .../intel/common/block/include/intelblocks/imc.h | 15 ++------------- .../common/block/include/intelblocks/itss.h | 15 ++------------- .../common/block/include/intelblocks/lpss.h | 15 ++------------- .../intel/common/block/include/intelblocks/mmc.h | 15 ++------------- .../common/block/include/intelblocks/mp_init.h | 15 ++------------- .../intel/common/block/include/intelblocks/msr.h | 15 ++------------- .../intel/common/block/include/intelblocks/nvs.h | 15 ++------------- .../common/block/include/intelblocks/p2sb.h | 15 ++------------- .../common/block/include/intelblocks/pcie_rp.h | 14 ++------------ .../intel/common/block/include/intelblocks/pcr.h | 15 ++------------- .../intel/common/block/include/intelblocks/pmc.h | 15 ++------------- .../common/block/include/intelblocks/pmclib.h | 15 ++------------- .../intel/common/block/include/intelblocks/rtc.h | 15 ++------------- .../intel/common/block/include/intelblocks/sd.h | 15 ++------------- .../intel/common/block/include/intelblocks/sgx.h | 15 ++------------- .../common/block/include/intelblocks/smbus.h | 15 ++------------- .../block/include/intelblocks/smihandler.h | 15 ++------------- .../intel/common/block/include/intelblocks/spi.h | 15 ++------------- .../common/block/include/intelblocks/sram.h | 15 ++------------- .../block/include/intelblocks/systemagent.h | 15 ++------------- .../intel/common/block/include/intelblocks/tco.h | 15 ++------------- .../common/block/include/intelblocks/thermal.h | 15 ++------------- .../common/block/include/intelblocks/uart.h | 15 ++------------- .../common/block/include/intelblocks/xdci.h | 15 ++------------- .../common/block/include/intelblocks/xhci.h | 15 ++------------- src/soc/intel/common/block/itss/itss.c | 15 ++------------- src/soc/intel/common/block/lpss/lpss.c | 15 ++------------- src/soc/intel/common/block/p2sb/p2sb.c | 15 ++------------- src/soc/intel/common/block/pcie/pcie.c | 15 ++------------- src/soc/intel/common/block/pcie/pcie_rp.c | 15 ++------------- src/soc/intel/common/block/pcr/pcr.c | 15 ++------------- src/soc/intel/common/block/pmc/pmc.c | 15 ++------------- src/soc/intel/common/block/pmc/pmclib.c | 15 ++------------- src/soc/intel/common/block/rtc/rtc.c | 15 ++------------- src/soc/intel/common/block/sata/sata.c | 15 ++------------- src/soc/intel/common/block/scs/early_mmc.c | 15 ++------------- src/soc/intel/common/block/scs/mmc.c | 15 ++------------- src/soc/intel/common/block/scs/sd.c | 15 ++------------- src/soc/intel/common/block/sgx/sgx.c | 15 ++------------- src/soc/intel/common/block/smbus/smbus.c | 15 ++------------- src/soc/intel/common/block/smbus/smbus_early.c | 15 ++------------- src/soc/intel/common/block/smbus/smbuslib.c | 15 ++------------- src/soc/intel/common/block/smbus/smbuslib.h | 15 ++------------- src/soc/intel/common/block/smbus/tco.c | 15 ++------------- src/soc/intel/common/block/smm/smihandler.c | 15 ++------------- src/soc/intel/common/block/smm/smitraphandler.c | 15 ++------------- src/soc/intel/common/block/smm/smm.c | 15 ++------------- src/soc/intel/common/block/systemagent/memmap.c | 15 ++------------- .../intel/common/block/systemagent/systemagent.c | 15 ++------------- .../common/block/systemagent/systemagent_def.h | 15 ++------------- .../common/block/systemagent/systemagent_early.c | 15 ++------------- src/soc/intel/common/block/thermal/thermal.c | 15 ++------------- src/soc/intel/common/block/timer/timer.c | 15 ++------------- src/soc/intel/common/block/uart/uart.c | 15 ++------------- src/soc/intel/common/block/xdci/xdci.c | 15 ++------------- src/soc/intel/common/block/xhci/elog.c | 15 ++------------- src/soc/intel/common/block/xhci/xhci.c | 15 ++------------- src/soc/intel/common/hda_verb.c | 15 ++------------- src/soc/intel/common/hda_verb.h | 15 ++------------- src/soc/intel/common/mma.c | 15 ++------------- src/soc/intel/common/mma.h | 15 ++------------- src/soc/intel/common/nhlt.c | 15 ++------------- .../intel/common/pch/include/intelpch/lockdown.h | 15 ++------------- src/soc/intel/common/pch/lockdown/lockdown.c | 15 ++------------- src/soc/intel/common/reset.c | 15 ++------------- src/soc/intel/common/smbios.c | 15 ++------------- src/soc/intel/common/smbios.h | 15 ++------------- src/soc/intel/common/tpm_tis.c | 15 ++------------- src/soc/intel/common/vbt.c | 15 ++------------- src/soc/intel/common/vbt.h | 15 ++------------- 107 files changed, 214 insertions(+), 1394 deletions(-) diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index c7e3a16594..2e21d51945 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #if CONFIG(ACPI_CONSOLE) diff --git a/src/soc/intel/common/acpi/acpi_wake_source.asl b/src/soc/intel/common/acpi/acpi_wake_source.asl index a5440e8e51..9dadcdaf45 100644 --- a/src/soc/intel/common/acpi/acpi_wake_source.asl +++ b/src/soc/intel/common/acpi/acpi_wake_source.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/soc/intel/common/acpi/dptf/charger.asl b/src/soc/intel/common/acpi/dptf/charger.asl index ba728b41a3..844f287afb 100644 --- a/src/soc/intel/common/acpi/dptf/charger.asl +++ b/src/soc/intel/common/acpi/dptf/charger.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TCHG) { diff --git a/src/soc/intel/common/acpi/dptf/cpu.asl b/src/soc/intel/common/acpi/dptf/cpu.asl index 982776f701..b3af1162eb 100644 --- a/src/soc/intel/common/acpi/dptf/cpu.asl +++ b/src/soc/intel/common/acpi/dptf/cpu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ External (\_SB.CP00._PSS, PkgObj) External (\_SB.CP00._TSS, PkgObj) diff --git a/src/soc/intel/common/acpi/dptf/dptf.asl b/src/soc/intel/common/acpi/dptf/dptf.asl index 4b7bdd5778..0f0c97033f 100644 --- a/src/soc/intel/common/acpi/dptf/dptf.asl +++ b/src/soc/intel/common/acpi/dptf/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (DPTF) { diff --git a/src/soc/intel/common/acpi/dptf/fan.asl b/src/soc/intel/common/acpi/dptf/fan.asl index 4a15156de5..bff81ade71 100644 --- a/src/soc/intel/common/acpi/dptf/fan.asl +++ b/src/soc/intel/common/acpi/dptf/fan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TFN1) { diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index 2dd2c59b7d..44ffc4faba 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER diff --git a/src/soc/intel/common/acpi/pci_osc.asl b/src/soc/intel/common/acpi/pci_osc.asl index 740cbe9a59..229dd35461 100644 --- a/src/soc/intel/common/acpi/pci_osc.asl +++ b/src/soc/intel/common/acpi/pci_osc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766" diff --git a/src/soc/intel/common/acpi/pcr.asl b/src/soc/intel/common/acpi/pcr.asl index eac78c4574..b5095ec077 100644 --- a/src/soc/intel/common/acpi/pcr.asl +++ b/src/soc/intel/common/acpi/pcr.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 8984f14657..6ec2ac9fe3 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl index 350c319842..bfcae3cae3 100644 --- a/src/soc/intel/common/acpi/sgx.asl +++ b/src/soc/intel/common/acpi/sgx.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope(\_SB) { diff --git a/src/soc/intel/common/acpi/wifi.asl b/src/soc/intel/common/acpi/wifi.asl index ed19bda103..699918c5d6 100644 --- a/src/soc/intel/common/acpi/wifi.asl +++ b/src/soc/intel/common/acpi/wifi.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (WIFI) { diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index c26c84f189..9ac03c99ad 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 8e1ea8dfdb..241e59b519 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/soc/intel/common/block/acpi/acpi/ipu.asl b/src/soc/intel/common/block/acpi/acpi/ipu.asl index d62a6e46f2..3a821e5524 100644 --- a/src/soc/intel/common/block/acpi/acpi/ipu.asl +++ b/src/soc/intel/common/block/acpi/acpi/ipu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* IPU3 input system - Device 05, Function 0 */ Device (IMGU) diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl index cf48ea5658..c63ecfec81 100644 --- a/src/soc/intel/common/block/acpi/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel LPC/eSPI Bus Device - 0:1f.0 */ #include diff --git a/src/soc/intel/common/block/acpi/acpi/pmc.asl b/src/soc/intel/common/block/acpi/acpi/pmc.asl index e534e8b033..34dcd43e4d 100644 --- a/src/soc/intel/common/block/acpi/acpi/pmc.asl +++ b/src/soc/intel/common/block/acpi/acpi/pmc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2020 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (PEPD) { diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 810423661b..df858e51f7 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 531d65208c..8b35e5227c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 04c8e65369..7a0bce0a69 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S index f27d6e7d4a..b7fd7e07f5 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S +++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index a6ddbe29ff..4e28b44740 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index c77035a864..35add01c62 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 86ed038b06..8daf6d2db6 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 3f66a92f38..08fca10b60 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 0660480af7..8f78a23733 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5c0b17ba2a..b42030885e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 952df222a1..a41e3ef77e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H #define SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index a8afd48c97..16041322f3 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index d1af348063..d96cfb07c9 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 6612210a84..46f19fb5eb 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/imc/imc.c b/src/soc/intel/common/block/imc/imc.c index 27b2beaf3a..517e62eb75 100644 --- a/src/soc/intel/common/block/imc/imc.c +++ b/src/soc/intel/common/block/imc/imc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Please note: the driver uses MMIO PCIe register access. IO based access will diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index 5a046b5b90..ffb01e1e62 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_CFG_H #define SOC_INTEL_COMMON_BLOCK_CFG_H diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 6b4da8059c..9f1dd411d3 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_CPULIB_H #define SOC_INTEL_COMMON_BLOCK_CPULIB_H diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 1fd0793cc2..8af78afbc3 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_H #define SOC_INTEL_COMMON_BLOCK_FAST_SPI_H diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 153f9d8184..5a68952bfc 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_H #define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H diff --git a/src/soc/intel/common/block/include/intelblocks/gspi.h b/src/soc/intel/common/block/include/intelblocks/gspi.h index 48b570e067..4266f6afff 100644 --- a/src/soc/intel/common/block/include/intelblocks/gspi.h +++ b/src/soc/intel/common/block/include/intelblocks/gspi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_GSPI_H #define SOC_INTEL_COMMON_BLOCK_GSPI_H diff --git a/src/soc/intel/common/block/include/intelblocks/imc.h b/src/soc/intel/common/block/include/intelblocks/imc.h index 2cfbd3b989..7550b2c21c 100644 --- a/src/soc/intel/common/block/include/intelblocks/imc.h +++ b/src/soc/intel/common/block/include/intelblocks/imc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h index 4d1f05dfe8..c79b22fc52 100644 --- a/src/soc/intel/common/block/include/intelblocks/itss.h +++ b/src/soc/intel/common/block/include/intelblocks/itss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H #define SOC_INTEL_COMMON_BLOCK_ITSS_H diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 27d13fb7c0..1e6d51a414 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H #define SOC_INTEL_COMMON_BLOCK_LPSS_H diff --git a/src/soc/intel/common/block/include/intelblocks/mmc.h b/src/soc/intel/common/block/include/intelblocks/mmc.h index 48ab7961b7..b3d9f89dd8 100644 --- a/src/soc/intel/common/block/include/intelblocks/mmc.h +++ b/src/soc/intel/common/block/include/intelblocks/mmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_MMC_H #define SOC_INTEL_COMMON_BLOCK_MMC_H diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index dff35d9db9..96d696b656 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_MP_INIT_H #define SOC_INTEL_COMMON_BLOCK_MP_INIT_H diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index ebb1c4736b..7809857e85 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_MSR_H #define SOC_INTEL_COMMON_MSR_H diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 054dcce9a8..d137e49bb7 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_NVS_H #define SOC_INTEL_COMMON_BLOCK_NVS_H diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 4ed5847d88..b04bfe2b5d 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H #define SOC_INTEL_COMMON_BLOCK_P2SB_H diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 52fde28310..a4e81844d2 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H diff --git a/src/soc/intel/common/block/include/intelblocks/pcr.h b/src/soc/intel/common/block/include/intelblocks/pcr.h index 8940fb5e3d..3f17fbc208 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcr.h +++ b/src/soc/intel/common/block/include/intelblocks/pcr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_PCR_H #define SOC_INTEL_COMMON_BLOCK_PCR_H diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index ee3b96e74d..4d241cc1d6 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_PMC_H #define SOC_INTEL_COMMON_BLOCK_PMC_H diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 0aa209ab45..84c33b1e3f 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_PMCLIB_H #define SOC_INTEL_COMMON_BLOCK_PMCLIB_H diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h index c958eb0fa3..c5af7adb6c 100644 --- a/src/soc/intel/common/block/include/intelblocks/rtc.h +++ b/src/soc/intel/common/block/include/intelblocks/rtc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_RTC_H #define SOC_INTEL_COMMON_BLOCK_RTC_H diff --git a/src/soc/intel/common/block/include/intelblocks/sd.h b/src/soc/intel/common/block/include/intelblocks/sd.h index 59b7a043d7..39ff533112 100644 --- a/src/soc/intel/common/block/include/intelblocks/sd.h +++ b/src/soc/intel/common/block/include/intelblocks/sd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SD_H #define SOC_INTEL_COMMON_BLOCK_SD_H diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 52e8d56ef5..715a6f2c1e 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SGX_H #define SOC_INTEL_COMMON_BLOCK_SGX_H diff --git a/src/soc/intel/common/block/include/intelblocks/smbus.h b/src/soc/intel/common/block/include/intelblocks/smbus.h index f465e6c9e9..6f197685a2 100644 --- a/src/soc/intel/common/block/include/intelblocks/smbus.h +++ b/src/soc/intel/common/block/include/intelblocks/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SMBUS_H #define SOC_INTEL_COMMON_BLOCK_SMBUS_H diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index 8a56109aef..d5a80ee4c6 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SMI_HANDLER_H #define SOC_INTEL_COMMON_BLOCK_SMI_HANDLER_H diff --git a/src/soc/intel/common/block/include/intelblocks/spi.h b/src/soc/intel/common/block/include/intelblocks/spi.h index a1705f8cc5..15ce5aee92 100644 --- a/src/soc/intel/common/block/include/intelblocks/spi.h +++ b/src/soc/intel/common/block/include/intelblocks/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SPI_H #define SOC_INTEL_COMMON_BLOCK_SPI_H diff --git a/src/soc/intel/common/block/include/intelblocks/sram.h b/src/soc/intel/common/block/include/intelblocks/sram.h index c189d97c7e..16c118be66 100644 --- a/src/soc/intel/common/block/include/intelblocks/sram.h +++ b/src/soc/intel/common/block/include/intelblocks/sram.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SRAM_H #define SOC_INTEL_COMMON_BLOCK_SRAM_H diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 73a1efc4fa..c6aa4b4f6f 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SA_H #define SOC_INTEL_COMMON_BLOCK_SA_H diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h index 0a434fa2ea..327945b46a 100644 --- a/src/soc/intel/common/block/include/intelblocks/tco.h +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_TCO_H #define SOC_INTEL_COMMON_BLOCK_TCO_H diff --git a/src/soc/intel/common/block/include/intelblocks/thermal.h b/src/soc/intel/common/block/include/intelblocks/thermal.h index 557f2ebf55..a1c3e7877e 100644 --- a/src/soc/intel/common/block/include/intelblocks/thermal.h +++ b/src/soc/intel/common/block/include/intelblocks/thermal.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ #define _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index ba6a873c57..cc27f0e571 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_UART_H #define SOC_INTEL_COMMON_BLOCK_UART_H diff --git a/src/soc/intel/common/block/include/intelblocks/xdci.h b/src/soc/intel/common/block/include/intelblocks/xdci.h index 2b2532c5e1..f4f730d3b1 100644 --- a/src/soc/intel/common/block/include/intelblocks/xdci.h +++ b/src/soc/intel/common/block/include/intelblocks/xdci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_XDCI_H #define SOC_INTEL_COMMON_BLOCK_XDCI_H diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 2720e01042..930af372c1 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_XHCI_H #define SOC_INTEL_COMMON_BLOCK_XHCI_H diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index 00bf492369..b9638d4a28 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 31b8544b61..f5cf4e5064 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 5bf196379c..050f95868e 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 153e7f7927..ec003e338b 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 0484bf3836..fb95ee5035 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index f18092c232..e851e32578 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index e1f2a3508c..d466e3684b 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 47a4ed9f78..9a0387b493 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index 41c7e96607..830a6aa6d6 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 39d8bcd15e..40b9ac6078 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 593233a693..5980b6b137 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index a3d0a2cb18..ffb72b7e40 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index d529faaaca..d31e33c90a 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 698c213415..89424fa928 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 97618b0d26..dc4c43ee5f 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index 8842e76b54..587f1ab290 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 9c1402b696..4db2c6e7a4 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h index 5436dea5d1..1857ab8fb7 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.h +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H #define SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index d5325359ca..a8babbf295 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index af1c633331..44fe59d2c9 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 538e0c89c1..75746000b8 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index e8ac35b919..ad139ba504 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 04eb4dd207..a9029e1649 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index fc27046025..6c0d5f59a6 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index fa7aaf9f48..03f4de44ba 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 5c7f952d4c..cb0ed34d47 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 5a2b414ac3..b077bbec15 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 73690c3648..95bb21576c 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 6fe019128e..7d75bdd62f 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 414fe37aac..b8800b3186 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index a311ec2c88..1bc32c93ce 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 398f093e41..c293f8ab08 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index c1aa9074e1..d74e50b40a 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/hda_verb.h b/src/soc/intel/common/hda_verb.h index b85a04c3fb..69f7e42cff 100644 --- a/src/soc/intel/common/hda_verb.h +++ b/src/soc/intel/common/hda_verb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMON_HDA_VERB_H_ #define _COMMON_HDA_VERB_H_ diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index dbb36de8e5..2499e436af 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/mma.h b/src/soc/intel/common/mma.h index 238e6ab371..979ab15584 100644 --- a/src/soc/intel/common/mma.h +++ b/src/soc/intel/common/mma.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_MMA_H_ #define _SOC_MMA_H_ diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index 1a74d7d44c..61298de191 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h index 01dae8c9d1..fe0d2a7d4c 100644 --- a/src/soc/intel/common/pch/include/intelpch/lockdown.h +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_COMMON_PCH_LOCKDOWN_H #define SOC_INTEL_COMMON_PCH_LOCKDOWN_H diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 036cccca7c..a00e5c027a 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 4d949098a0..9aa5727c16 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 6fb2bcfd4b..d43a68e133 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "smbios.h" diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 6a013e51f5..c9eb9bc143 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMON_SMBIOS_H_ #define _COMMON_SMBIOS_H_ diff --git a/src/soc/intel/common/tpm_tis.c b/src/soc/intel/common/tpm_tis.c index 641bd685a7..77262b6036 100644 --- a/src/soc/intel/common/tpm_tis.c +++ b/src/soc/intel/common/tpm_tis.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 2fd3d1571d..5b21018b6c 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/common/vbt.h b/src/soc/intel/common/vbt.h index 7d7a028d67..600ba84575 100644 --- a/src/soc/intel/common/vbt.h +++ b/src/soc/intel/common/vbt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _INTEL_COMMON_VBT_H_ #define _INTEL_COMMON_VBT_H_ From c3f58f6aca2139ffa3933e615208a42ca76fd720 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:46:41 +0200 Subject: [PATCH 0894/1463] soc/intel/baytrail: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib41169395ab239e520f6047ac6bd307ec50776d4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40209 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/baytrail/acpi.c | 15 ++------------- src/soc/intel/baytrail/acpi/device_nvs.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/dptf/charger.asl | 15 ++------------- src/soc/intel/baytrail/acpi/dptf/cpu.asl | 15 ++------------- src/soc/intel/baytrail/acpi/dptf/dptf.asl | 15 ++------------- src/soc/intel/baytrail/acpi/dptf/thermal.asl | 15 ++------------- src/soc/intel/baytrail/acpi/globalnvs.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/gpio.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/irq_helper.h | 15 ++------------- src/soc/intel/baytrail/acpi/irqlinks.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/irqroute.asl | 15 ++------------- src/soc/intel/baytrail/acpi/lpc.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/lpe.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/lpss.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/pcie.asl | 15 ++------------- src/soc/intel/baytrail/acpi/platform.asl | 15 ++------------- src/soc/intel/baytrail/acpi/scc.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/southcluster.asl | 16 ++-------------- src/soc/intel/baytrail/acpi/xhci.asl | 16 ++-------------- src/soc/intel/baytrail/bootblock/bootblock.c | 15 ++------------- src/soc/intel/baytrail/chip.c | 15 ++------------- src/soc/intel/baytrail/chip.h | 15 ++------------- src/soc/intel/baytrail/cpu.c | 15 ++------------- src/soc/intel/baytrail/dptf.c | 15 ++------------- src/soc/intel/baytrail/ehci.c | 15 ++------------- src/soc/intel/baytrail/elog.c | 16 ++-------------- src/soc/intel/baytrail/emmc.c | 15 ++------------- src/soc/intel/baytrail/gfx.c | 15 ++------------- src/soc/intel/baytrail/gpio.c | 15 ++------------- src/soc/intel/baytrail/hda.c | 15 ++------------- src/soc/intel/baytrail/include/soc/acpi.h | 15 ++------------- src/soc/intel/baytrail/include/soc/device_nvs.h | 15 ++------------- src/soc/intel/baytrail/include/soc/ehci.h | 15 ++------------- src/soc/intel/baytrail/include/soc/gfx.h | 15 ++------------- src/soc/intel/baytrail/include/soc/gpio.h | 15 ++------------- src/soc/intel/baytrail/include/soc/iomap.h | 15 ++------------- src/soc/intel/baytrail/include/soc/iosf.h | 15 ++------------- src/soc/intel/baytrail/include/soc/irq.h | 15 ++------------- src/soc/intel/baytrail/include/soc/lpc.h | 15 ++------------- src/soc/intel/baytrail/include/soc/msr.h | 15 ++------------- src/soc/intel/baytrail/include/soc/nvs.h | 15 ++------------- src/soc/intel/baytrail/include/soc/pattrs.h | 15 ++------------- src/soc/intel/baytrail/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/baytrail/include/soc/pcie.h | 15 ++------------- src/soc/intel/baytrail/include/soc/pmc.h | 15 ++------------- src/soc/intel/baytrail/include/soc/ramstage.h | 15 ++------------- src/soc/intel/baytrail/include/soc/romstage.h | 15 ++------------- src/soc/intel/baytrail/include/soc/sata.h | 15 ++------------- src/soc/intel/baytrail/include/soc/smm.h | 15 ++------------- src/soc/intel/baytrail/include/soc/spi.h | 15 ++------------- src/soc/intel/baytrail/include/soc/xhci.h | 15 ++------------- src/soc/intel/baytrail/iosf.c | 15 ++------------- src/soc/intel/baytrail/lpe.c | 15 ++------------- src/soc/intel/baytrail/lpss.c | 15 ++------------- src/soc/intel/baytrail/memmap.c | 15 ++------------- src/soc/intel/baytrail/northcluster.c | 15 ++------------- src/soc/intel/baytrail/pcie.c | 15 ++------------- src/soc/intel/baytrail/perf_power.c | 15 ++------------- src/soc/intel/baytrail/placeholders.c | 15 ++------------- src/soc/intel/baytrail/pmutil.c | 15 ++------------- src/soc/intel/baytrail/ramstage.c | 15 ++------------- src/soc/intel/baytrail/refcode.c | 15 ++------------- src/soc/intel/baytrail/romstage/gfx.c | 15 ++------------- src/soc/intel/baytrail/romstage/pmc.c | 15 ++------------- src/soc/intel/baytrail/romstage/raminit.c | 15 ++------------- src/soc/intel/baytrail/romstage/romstage.c | 15 ++------------- src/soc/intel/baytrail/sata.c | 15 ++------------- src/soc/intel/baytrail/scc.c | 15 ++------------- src/soc/intel/baytrail/sd.c | 15 ++------------- src/soc/intel/baytrail/smihandler.c | 15 ++------------- src/soc/intel/baytrail/smm.c | 16 ++-------------- src/soc/intel/baytrail/southcluster.c | 15 ++------------- src/soc/intel/baytrail/tsc_freq.c | 15 ++------------- src/soc/intel/baytrail/xhci.c | 15 ++------------- 74 files changed, 148 insertions(+), 974 deletions(-) diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 1797e48543..ac0e29268b 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl index fb190874a2..159a6158fc 100644 --- a/src/soc/intel/baytrail/acpi/device_nvs.asl +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Device Enabled in ACPI Mode */ diff --git a/src/soc/intel/baytrail/acpi/dptf/charger.asl b/src/soc/intel/baytrail/acpi/dptf/charger.asl index 4af55fb0dc..b07ef29ac2 100644 --- a/src/soc/intel/baytrail/acpi/dptf/charger.asl +++ b/src/soc/intel/baytrail/acpi/dptf/charger.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (TCHG) { diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index 289dcd4a7b..d6f9894551 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ External (\_SB.CP00._TSS, MethodObj) External (\_SB.CP00._TPC, MethodObj) diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl index 1a9e549597..cfec3fe01c 100644 --- a/src/soc/intel/baytrail/acpi/dptf/dptf.asl +++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (DPTF) { diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl index 106cd77015..136142e72a 100644 --- a/src/soc/intel/baytrail/acpi/dptf/thermal.asl +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 763fa0e66f..4aa600f1ca 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/soc/intel/baytrail/acpi/gpio.asl b/src/soc/intel/baytrail/acpi/gpio.asl index d99323d0d4..64aaaa60d6 100644 --- a/src/soc/intel/baytrail/acpi/gpio.asl +++ b/src/soc/intel/baytrail/acpi/gpio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/acpi/irq_helper.h b/src/soc/intel/baytrail/acpi/irq_helper.h index 11b0f0a5db..b585972535 100644 --- a/src/soc/intel/baytrail/acpi/irq_helper.h +++ b/src/soc/intel/baytrail/acpi/irq_helper.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #undef PCI_DEV_PIRQ_ROUTES #undef ACPI_DEV_APIC_IRQ diff --git a/src/soc/intel/baytrail/acpi/irqlinks.asl b/src/soc/intel/baytrail/acpi/irqlinks.asl index 0bfdbdedad..ee98996fff 100644 --- a/src/soc/intel/baytrail/acpi/irqlinks.asl +++ b/src/soc/intel/baytrail/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/soc/intel/baytrail/acpi/irqroute.asl b/src/soc/intel/baytrail/acpi/irqroute.asl index 2f8e62e977..e1adaabf29 100644 --- a/src/soc/intel/baytrail/acpi/irqroute.asl +++ b/src/soc/intel/baytrail/acpi/irqroute.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // PCI Interrupt Routing Method(_PRT) diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index dc2b663f89..cb9a2b89d1 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 diff --git a/src/soc/intel/baytrail/acpi/lpe.asl b/src/soc/intel/baytrail/acpi/lpe.asl index f75d1b880b..e2d11f9972 100644 --- a/src/soc/intel/baytrail/acpi/lpe.asl +++ b/src/soc/intel/baytrail/acpi/lpe.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LPEA) { diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl index e8bf01cd60..ebf23e1acb 100644 --- a/src/soc/intel/baytrail/acpi/lpss.asl +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (SDM1) { diff --git a/src/soc/intel/baytrail/acpi/pcie.asl b/src/soc/intel/baytrail/acpi/pcie.asl index 2ae3d965e4..a4ee4997a6 100644 --- a/src/soc/intel/baytrail/acpi/pcie.asl +++ b/src/soc/intel/baytrail/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel SOC PCIe support */ diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index 7b6da44201..c298b4bade 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/baytrail/acpi/scc.asl b/src/soc/intel/baytrail/acpi/scc.asl index 2f6dc9accd..d1182f6078 100644 --- a/src/soc/intel/baytrail/acpi/scc.asl +++ b/src/soc/intel/baytrail/acpi/scc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (EMMC) { diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 286826c563..a61c1c871c 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index 4261a57c99..fe2401cc7f 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (XHCI) { diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 5a697bc1d6..8d4c82f018 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 10bb245581..39802dcabb 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 52b1e33851..9065854003 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* The devicetree parser expects chip.h to reside directly in the path * specified by the devicetree. */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 701a4e6a94..d2a8e573b8 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index e7cd7d8ff1..09deffa042 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 6b759f2f90..dc9855ddf8 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 5b4e35f064..1401649552 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 885bc0fbb1..347ca16f40 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index e4ed6f37d5..64c906194e 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 0bf9e60c40..7a6da0deff 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index 45430070d2..df23f54974 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index fbdf030608..3da67ebf76 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_ACPI_H_ #define _BAYTRAIL_ACPI_H_ diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index cc9bc658ad..bfc3c681a2 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_DEVICE_NVS_H_ #define _BAYTRAIL_DEVICE_NVS_H_ diff --git a/src/soc/intel/baytrail/include/soc/ehci.h b/src/soc/intel/baytrail/include/soc/ehci.h index 56a7705684..1a1196971b 100644 --- a/src/soc/intel/baytrail/include/soc/ehci.h +++ b/src/soc/intel/baytrail/include/soc/ehci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BAYTRAIL_EHCI_H #define BAYTRAIL_EHCI_H diff --git a/src/soc/intel/baytrail/include/soc/gfx.h b/src/soc/intel/baytrail/include/soc/gfx.h index 00d709d139..38316033cf 100644 --- a/src/soc/intel/baytrail/include/soc/gfx.h +++ b/src/soc/intel/baytrail/include/soc/gfx.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_GFX_H_ #define _BAYTRAIL_GFX_H_ diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 3c1e7f37dd..9013bf537a 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_GPIO_H_ #define _BAYTRAIL_GPIO_H_ diff --git a/src/soc/intel/baytrail/include/soc/iomap.h b/src/soc/intel/baytrail/include/soc/iomap.h index 644c07c746..acbed0df45 100644 --- a/src/soc/intel/baytrail/include/soc/iomap.h +++ b/src/soc/intel/baytrail/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_IOMAP_H_ #define _BAYTRAIL_IOMAP_H_ diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 29cf26d242..e2da8481eb 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_IOSF_H_ #define _BAYTRAIL_IOSF_H_ diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index d92b9234c1..5a11d786dc 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_IRQ_H_ #define _BAYTRAIL_IRQ_H_ diff --git a/src/soc/intel/baytrail/include/soc/lpc.h b/src/soc/intel/baytrail/include/soc/lpc.h index 2c06bccaec..f52ed39499 100644 --- a/src/soc/intel/baytrail/include/soc/lpc.h +++ b/src/soc/intel/baytrail/include/soc/lpc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_ diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 474e75a7a7..ace975c23c 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 49cb03d5e6..df81573016 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_NVS_H_ #define _BAYTRAIL_NVS_H_ diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index a5c9b16641..624c902b90 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _PATTRS_H_ #define _PATTRS_H_ diff --git a/src/soc/intel/baytrail/include/soc/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h index 88bedb9642..4608a7635e 100644 --- a/src/soc/intel/baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/baytrail/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_PCI_DEVS_H_ #define _BAYTRAIL_PCI_DEVS_H_ diff --git a/src/soc/intel/baytrail/include/soc/pcie.h b/src/soc/intel/baytrail/include/soc/pcie.h index 873af3cb33..36df3320a7 100644 --- a/src/soc/intel/baytrail/include/soc/pcie.h +++ b/src/soc/intel/baytrail/include/soc/pcie.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_PCIE_H_ #define _BAYTRAIL_PCIE_H_ diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index fc30ad10d5..0161f67038 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_PMC_H_ #define _BAYTRAIL_PMC_H_ diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index 199ea06ced..5bb82638bf 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_RAMSTAGE_H_ #define _BAYTRAIL_RAMSTAGE_H_ diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 46bd010a56..88eb9ead04 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_ROMSTAGE_H_ #define _BAYTRAIL_ROMSTAGE_H_ diff --git a/src/soc/intel/baytrail/include/soc/sata.h b/src/soc/intel/baytrail/include/soc/sata.h index b9cd6c32f9..62a4e76b65 100644 --- a/src/soc/intel/baytrail/include/soc/sata.h +++ b/src/soc/intel/baytrail/include/soc/sata.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BAYTRAIL_SATA_H #define BAYTRAIL_SATA_H diff --git a/src/soc/intel/baytrail/include/soc/smm.h b/src/soc/intel/baytrail/include/soc/smm.h index c95289b76d..3af36822eb 100644 --- a/src/soc/intel/baytrail/include/soc/smm.h +++ b/src/soc/intel/baytrail/include/soc/smm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_SMM_H_ #define _BAYTRAIL_SMM_H_ diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h index 2a21e90b68..da043e5bc9 100644 --- a/src/soc/intel/baytrail/include/soc/spi.h +++ b/src/soc/intel/baytrail/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BAYTRAIL_SPI_H_ #define _BAYTRAIL_SPI_H_ diff --git a/src/soc/intel/baytrail/include/soc/xhci.h b/src/soc/intel/baytrail/include/soc/xhci.h index f169acafcd..88808a285d 100644 --- a/src/soc/intel/baytrail/include/soc/xhci.h +++ b/src/soc/intel/baytrail/include/soc/xhci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef BAYTRAIL_XHCI_H #define BAYTRAIL_XHCI_H diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 1d51cbb204..f73b97be89 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index a2c71e62d8..e475defb98 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 9cc8025957..a01310e70a 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 7e8103abf6..2ebe57b104 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 38bbfc27ad..d83be9f826 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 8cd81a61a7..8520049b08 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 4be6382f1d..eb16683870 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c index e7b20988b6..71e2a634c8 100644 --- a/src/soc/intel/baytrail/placeholders.c +++ b/src/soc/intel/baytrail/placeholders.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index f0abcee7d8..aa56a2ebb2 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 6665649a07..9036e103fc 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 1af829826d..5f6dce875f 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c index 737beb0ef3..8a87a6b0c1 100644 --- a/src/soc/intel/baytrail/romstage/gfx.c +++ b/src/soc/intel/baytrail/romstage/gfx.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index faa545bd3e..a437d58889 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index df29de762a..f1a3c1798b 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 24fff010bf..5b9a938765 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index f56975fd39..ce8d1b98fe 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 3332fed265..3d5c501038 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 7c587650f9..8709e24c4d 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 59da24389c..da97535ab8 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 286cb49082..85b362ee96 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 06cb2619d5..1b0906f789 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index df73f80752..fb911b4cde 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index ca7ee71e32..473be2fcc3 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From f94ac9ad7dceced2149e59b63380d8eedfba0c08 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:46:48 +0200 Subject: [PATCH 0895/1463] soc/intel/broadwell: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8995372760543e9cf2c845019f7a063046c55e9c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40211 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/broadwell/acpi.c | 15 ++------------- src/soc/intel/broadwell/acpi/adsp.asl | 15 ++------------- src/soc/intel/broadwell/acpi/ctdp.asl | 15 ++------------- src/soc/intel/broadwell/acpi/device_nvs.asl | 15 ++------------- src/soc/intel/broadwell/acpi/ehci.asl | 15 ++------------- src/soc/intel/broadwell/acpi/globalnvs.asl | 15 ++------------- src/soc/intel/broadwell/acpi/gpio.asl | 15 ++------------- src/soc/intel/broadwell/acpi/hda.asl | 15 ++------------- src/soc/intel/broadwell/acpi/irqlinks.asl | 15 ++------------- src/soc/intel/broadwell/acpi/lpc.asl | 15 ++------------- src/soc/intel/broadwell/acpi/pch.asl | 15 ++------------- src/soc/intel/broadwell/acpi/pci_irqs.asl | 15 ++------------- src/soc/intel/broadwell/acpi/pcie.asl | 15 ++------------- src/soc/intel/broadwell/acpi/pcie_port.asl | 15 ++------------- src/soc/intel/broadwell/acpi/platform.asl | 15 ++------------- src/soc/intel/broadwell/acpi/sata.asl | 15 ++------------- src/soc/intel/broadwell/acpi/serialio.asl | 15 ++------------- src/soc/intel/broadwell/acpi/smbus.asl | 15 ++------------- src/soc/intel/broadwell/acpi/systemagent.asl | 15 ++------------- src/soc/intel/broadwell/acpi/xhci.asl | 15 ++------------- src/soc/intel/broadwell/adsp.c | 15 ++------------- src/soc/intel/broadwell/bootblock/cpu.c | 15 ++------------- src/soc/intel/broadwell/bootblock/pch.c | 15 ++------------- src/soc/intel/broadwell/bootblock/systemagent.c | 15 ++------------- src/soc/intel/broadwell/chip.c | 15 ++------------- src/soc/intel/broadwell/chip.h | 15 ++------------- src/soc/intel/broadwell/cpu.c | 15 ++------------- src/soc/intel/broadwell/cpu_info.c | 15 ++------------- src/soc/intel/broadwell/ehci.c | 15 ++------------- src/soc/intel/broadwell/elog.c | 15 ++------------- src/soc/intel/broadwell/finalize.c | 15 ++------------- src/soc/intel/broadwell/gpio.c | 15 ++------------- src/soc/intel/broadwell/hda.c | 15 ++------------- src/soc/intel/broadwell/igd.c | 15 ++------------- src/soc/intel/broadwell/include/soc/acpi.h | 15 ++------------- src/soc/intel/broadwell/include/soc/adsp.h | 15 ++------------- src/soc/intel/broadwell/include/soc/cpu.h | 15 ++------------- src/soc/intel/broadwell/include/soc/device_nvs.h | 15 ++------------- src/soc/intel/broadwell/include/soc/ehci.h | 15 ++------------- src/soc/intel/broadwell/include/soc/gpio.h | 15 ++------------- src/soc/intel/broadwell/include/soc/igd.h | 14 ++------------ src/soc/intel/broadwell/include/soc/iobp.h | 15 ++------------- src/soc/intel/broadwell/include/soc/iomap.h | 15 ++------------- src/soc/intel/broadwell/include/soc/lpc.h | 15 ++------------- src/soc/intel/broadwell/include/soc/me.h | 15 ++------------- src/soc/intel/broadwell/include/soc/msr.h | 15 ++------------- src/soc/intel/broadwell/include/soc/nvs.h | 15 ++------------- src/soc/intel/broadwell/include/soc/pch.h | 15 ++------------- src/soc/intel/broadwell/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/broadwell/include/soc/pei_wrapper.h | 15 ++------------- src/soc/intel/broadwell/include/soc/pm.h | 15 ++------------- src/soc/intel/broadwell/include/soc/ramstage.h | 15 ++------------- src/soc/intel/broadwell/include/soc/rcba.h | 15 ++------------- src/soc/intel/broadwell/include/soc/romstage.h | 15 ++------------- src/soc/intel/broadwell/include/soc/sata.h | 15 ++------------- src/soc/intel/broadwell/include/soc/serialio.h | 15 ++------------- src/soc/intel/broadwell/include/soc/smbus.h | 15 ++------------- src/soc/intel/broadwell/include/soc/spi.h | 15 ++------------- src/soc/intel/broadwell/include/soc/systemagent.h | 15 ++------------- src/soc/intel/broadwell/include/soc/xhci.h | 15 ++------------- src/soc/intel/broadwell/iobp.c | 15 ++------------- src/soc/intel/broadwell/lpc.c | 15 ++------------- src/soc/intel/broadwell/me.c | 15 ++------------- src/soc/intel/broadwell/me_status.c | 15 ++------------- src/soc/intel/broadwell/memmap.c | 15 ++------------- src/soc/intel/broadwell/minihd.c | 15 ++------------- src/soc/intel/broadwell/pch.c | 15 ++------------- src/soc/intel/broadwell/pcie.c | 15 ++------------- src/soc/intel/broadwell/pei_data.c | 15 ++------------- src/soc/intel/broadwell/pmutil.c | 15 ++------------- src/soc/intel/broadwell/ramstage.c | 15 ++------------- src/soc/intel/broadwell/refcode.c | 15 ++------------- src/soc/intel/broadwell/romstage/cpu.c | 15 ++------------- src/soc/intel/broadwell/romstage/pch.c | 15 ++------------- src/soc/intel/broadwell/romstage/power_state.c | 15 ++------------- src/soc/intel/broadwell/romstage/raminit.c | 15 ++------------- .../intel/broadwell/romstage/report_platform.c | 15 ++------------- src/soc/intel/broadwell/romstage/romstage.c | 15 ++------------- src/soc/intel/broadwell/romstage/smbus.c | 15 ++------------- src/soc/intel/broadwell/romstage/systemagent.c | 15 ++------------- src/soc/intel/broadwell/romstage/uart.c | 15 ++------------- src/soc/intel/broadwell/sata.c | 15 ++------------- src/soc/intel/broadwell/serialio.c | 15 ++------------- src/soc/intel/broadwell/smbus.c | 15 ++------------- src/soc/intel/broadwell/smi.c | 15 ++------------- src/soc/intel/broadwell/smihandler.c | 15 ++------------- src/soc/intel/broadwell/smmrelocate.c | 15 ++------------- src/soc/intel/broadwell/systemagent.c | 15 ++------------- src/soc/intel/broadwell/tsc_freq.c | 15 ++------------- src/soc/intel/broadwell/usb_debug.c | 15 ++------------- src/soc/intel/broadwell/xhci.c | 15 ++------------- 91 files changed, 182 insertions(+), 1182 deletions(-) diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 1664fdffef..b93518954f 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/acpi/adsp.asl index d5841b1e10..87b37b442f 100644 --- a/src/soc/intel/broadwell/acpi/adsp.asl +++ b/src/soc/intel/broadwell/acpi/adsp.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (ADSP) { diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 6f3cad6d85..df6e7ec1eb 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0.MCHC) { diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl index 1e64480103..01364113b1 100644 --- a/src/soc/intel/broadwell/acpi/device_nvs.asl +++ b/src/soc/intel/broadwell/acpi/device_nvs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Device Enabled in ACPI Mode */ diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/soc/intel/broadwell/acpi/ehci.asl index d5651e6084..10a0d0d60c 100644 --- a/src/soc/intel/broadwell/acpi/ehci.asl +++ b/src/soc/intel/broadwell/acpi/ehci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // EHCI Controller 0:1d.0 diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 53a153b84b..a28ef4b3cb 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/acpi/gpio.asl index bfdcebf45b..183e0cf77c 100644 --- a/src/soc/intel/broadwell/acpi/gpio.asl +++ b/src/soc/intel/broadwell/acpi/gpio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (GPIO) { diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/soc/intel/broadwell/acpi/hda.asl index c7ee26dc90..e6d410c6f4 100644 --- a/src/soc/intel/broadwell/acpi/hda.asl +++ b/src/soc/intel/broadwell/acpi/hda.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH HDA */ diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/acpi/irqlinks.asl index 7e554624e5..571e9363ab 100644 --- a/src/soc/intel/broadwell/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/acpi/irqlinks.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index c8f81e18e2..7cefc70e1e 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl index 6d41ae368c..8b4ace23cb 100644 --- a/src/soc/intel/broadwell/acpi/pch.asl +++ b/src/soc/intel/broadwell/acpi/pch.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/acpi/pci_irqs.asl index 7534d2c11d..327eb56ce8 100644 --- a/src/soc/intel/broadwell/acpi/pci_irqs.asl +++ b/src/soc/intel/broadwell/acpi/pci_irqs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Method(_PRT) { diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/soc/intel/broadwell/acpi/pcie.asl index acdada8031..ed6217ec90 100644 --- a/src/soc/intel/broadwell/acpi/pcie.asl +++ b/src/soc/intel/broadwell/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH PCIe support */ diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/soc/intel/broadwell/acpi/pcie_port.asl index 57cd2d42e2..93937c4c85 100644 --- a/src/soc/intel/broadwell/acpi/pcie_port.asl +++ b/src/soc/intel/broadwell/acpi/pcie_port.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Included in each PCIe Root Port device */ diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl index d70944d368..341e960d08 100644 --- a/src/soc/intel/broadwell/acpi/platform.asl +++ b/src/soc/intel/broadwell/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/soc/intel/broadwell/acpi/sata.asl index e5f7fac057..5aec8b0347 100644 --- a/src/soc/intel/broadwell/acpi/sata.asl +++ b/src/soc/intel/broadwell/acpi/sata.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SATA Controller 0:1f.2 Device (SATA) diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index a3bd86680e..2caf5b0103 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel Serial IO Devices in ACPI Mode diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/acpi/smbus.asl index e6c72d79c7..9fc516fe54 100644 --- a/src/soc/intel/broadwell/acpi/smbus.asl +++ b/src/soc/intel/broadwell/acpi/smbus.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SMBus Controller 0:1f.3 diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index 9155b4dcce..5e94ae0484 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl index 0b6ca567d4..2d94784ff9 100644 --- a/src/soc/intel/broadwell/acpi/xhci.asl +++ b/src/soc/intel/broadwell/acpi/xhci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // XHCI Controller 0:14.0 diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 198a39adec..82904de39b 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index d3eb3959d6..218232f263 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 671c968f96..6de13065df 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 2f13080c08..e3f3d8e6ac 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 6c5b3a4bfd..1cf5ada530 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index b68da91c03..7351d709c8 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ #define _SOC_INTEL_BROADWELL_CHIP_H_ diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 7e0e6f24ca..b630c0a58f 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c index 7a608c1ba0..0cc65c5bbb 100644 --- a/src/soc/intel/broadwell/cpu_info.c +++ b/src/soc/intel/broadwell/cpu_info.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index 70e62bb243..9eb66cc7b6 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index 8f4653e7c3..66b9360e9a 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index ddd6bfd61d..aa8a51ae45 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/gpio.c index 1920e31f12..fada3ef7e4 100644 --- a/src/soc/intel/broadwell/gpio.c +++ b/src/soc/intel/broadwell/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 3cb91fe750..476d092f19 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 77375e4497..dbb420529f 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 1fd90c517a..7da5b5cb4e 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_ACPI_H_ #define _BROADWELL_ACPI_H_ diff --git a/src/soc/intel/broadwell/include/soc/adsp.h b/src/soc/intel/broadwell/include/soc/adsp.h index 8edf19c758..e1e977691d 100644 --- a/src/soc/intel/broadwell/include/soc/adsp.h +++ b/src/soc/intel/broadwell/include/soc/adsp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_ADSP_H_ #define _BROADWELL_ADSP_H_ diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 8da798f8ee..93d8a0119e 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_CPU_H_ #define _BROADWELL_CPU_H_ diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h index 724a1c6ee3..b9fc0ccb2d 100644 --- a/src/soc/intel/broadwell/include/soc/device_nvs.h +++ b/src/soc/intel/broadwell/include/soc/device_nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_DEVICE_NVS_H_ #define _BROADWELL_DEVICE_NVS_H_ diff --git a/src/soc/intel/broadwell/include/soc/ehci.h b/src/soc/intel/broadwell/include/soc/ehci.h index 56e26f9c8b..778d62d88a 100644 --- a/src/soc/intel/broadwell/include/soc/ehci.h +++ b/src/soc/intel/broadwell/include/soc/ehci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_EHCI_H_ #define _BROADWELL_EHCI_H_ diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index ed34f1aca6..0213b812d9 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_GPIO_H_ #define _BROADWELL_GPIO_H_ diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h index cdbee4ba38..301ae8ea32 100644 --- a/src/soc/intel/broadwell/include/soc/igd.h +++ b/src/soc/intel/broadwell/include/soc/igd.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_BROADWELL_GMA_H #define SOC_INTEL_BROADWELL_GMA_H diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/soc/intel/broadwell/include/soc/iobp.h index c4ecff72c6..1b3f4f6eca 100644 --- a/src/soc/intel/broadwell/include/soc/iobp.h +++ b/src/soc/intel/broadwell/include/soc/iobp.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_IOBP_H_ #define _BROADWELL_IOBP_H_ diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h index 5dbf30f98f..5717f9ef62 100644 --- a/src/soc/intel/broadwell/include/soc/iomap.h +++ b/src/soc/intel/broadwell/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_IOMAP_H_ #define _BROADWELL_IOMAP_H_ diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/soc/intel/broadwell/include/soc/lpc.h index 8da9e40ccc..1f9fa0016c 100644 --- a/src/soc/intel/broadwell/include/soc/lpc.h +++ b/src/soc/intel/broadwell/include/soc/lpc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_LPC_H_ #define _BROADWELL_LPC_H_ diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index f5603e79c4..9f988ffab0 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_ME_H_ #define _BROADWELL_ME_H_ diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 965512acd8..7328f19bbd 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_MSR_H_ #define _BROADWELL_MSR_H_ diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 9776bb880a..b2bc97adcb 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_NVS_H_ #define _BROADWELL_NVS_H_ diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index ffe67f9ce9..8db3767883 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_PCH_H_ #define _BROADWELL_PCH_H_ diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 0ee5523504..dfc0c94676 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_PCI_DEVS_H_ #define _BROADWELL_PCI_DEVS_H_ diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/soc/intel/broadwell/include/soc/pei_wrapper.h index bad3c7b6fd..0706197a80 100644 --- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h +++ b/src/soc/intel/broadwell/include/soc/pei_wrapper.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_PEI_WRAPPER_H_ #define _BROADWELL_PEI_WRAPPER_H_ diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index d187faf354..ea6beb15f1 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_PM_H_ #define _BROADWELL_PM_H_ diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index d8da5f92dc..559eef7c9a 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_RAMSTAGE_H_ #define _BROADWELL_RAMSTAGE_H_ diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h index cf53b7d172..c219834240 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/soc/intel/broadwell/include/soc/rcba.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_RCBA_H_ #define _BROADWELL_RCBA_H_ diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index b0adefd693..ab3260ff57 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_ROMSTAGE_H_ #define _BROADWELL_ROMSTAGE_H_ diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/soc/intel/broadwell/include/soc/sata.h index f84825415f..c1600f95c2 100644 --- a/src/soc/intel/broadwell/include/soc/sata.h +++ b/src/soc/intel/broadwell/include/soc/sata.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_SATA_H_ #define _BROADWELL_SATA_H_ diff --git a/src/soc/intel/broadwell/include/soc/serialio.h b/src/soc/intel/broadwell/include/soc/serialio.h index 41173ed414..5f4135fb59 100644 --- a/src/soc/intel/broadwell/include/soc/serialio.h +++ b/src/soc/intel/broadwell/include/soc/serialio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_SERIALIO_H_ #define _BROADWELL_SERIALIO_H_ diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h index e320b0556d..8e496637a0 100644 --- a/src/soc/intel/broadwell/include/soc/smbus.h +++ b/src/soc/intel/broadwell/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_SMBUS_H_ #define _BROADWELL_SMBUS_H_ diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index 303e494e4c..eba787dbc4 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_SPI_H_ #define _BROADWELL_SPI_H_ diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 33e2861388..ac5b824952 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_SYSTEMAGENT_H_ #define _BROADWELL_SYSTEMAGENT_H_ diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h index 8a1d192500..178bec65b2 100644 --- a/src/soc/intel/broadwell/include/soc/xhci.h +++ b/src/soc/intel/broadwell/include/soc/xhci.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BROADWELL_XHCI_H_ #define _BROADWELL_XHCI_H_ diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index 26e0a710ed..9686269e59 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index bc6bc6b200..a381bb1084 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 4b786c81d9..730d77ed14 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This is a ramstage driver for the Intel Management Engine found in the diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index e65978f47c..c0a927b95e 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 6bb434f00e..8a5771d26e 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index af3cea470b..2dcab97ae9 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index dc4ff113bf..f6f3746d0e 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 2fc7d09503..f81f0429f2 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index 12c9a0299c..d8d1bcc927 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index b170ff27d7..910df61795 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Helper functions for dealing with power management registers diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index ed287b8c5c..a0c6e4f497 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index efab8d4163..f54a4947a2 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index 5374af71a0..37ccf8cb0f 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 467b83ea51..d06619b202 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 0cd1a9d28d..b63343acb4 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 7fe93bdfc5..78081fe54a 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 98bd94b924..af050569c9 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f28f9d1636..4c5dfca853 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c index d00a3fc5df..1815465cfa 100644 --- a/src/soc/intel/broadwell/romstage/smbus.c +++ b/src/soc/intel/broadwell/romstage/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c index 471794bab5..fe508fe268 100644 --- a/src/soc/intel/broadwell/romstage/systemagent.c +++ b/src/soc/intel/broadwell/romstage/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index f8a4b4fc0b..1c6d334b6d 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index f8e223b7f6..d8d14b74c3 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 518c99da73..a4922f7d73 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 6a1e85b499..792fb1052f 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index b1be1faa69..6860f6f58e 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 7df9a341eb..bce157d102 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index e11a66918b..f5f83f6bcb 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index fdaa9f6541..8b5dc0cc60 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/soc/intel/broadwell/tsc_freq.c index 77167a9b30..443350cb62 100644 --- a/src/soc/intel/broadwell/tsc_freq.c +++ b/src/soc/intel/broadwell/tsc_freq.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c index bd6b31b6f8..aef3e6973a 100644 --- a/src/soc/intel/broadwell/usb_debug.c +++ b/src/soc/intel/broadwell/usb_debug.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index e7b7d0a71a..2eb82a20a8 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From f5627e8454aa99d51f85528f761e87e38dc1c634 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:46:52 +0200 Subject: [PATCH 0896/1463] soc/intel/cannonlake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I48422453735d50eb9292f39a3c031073d647a17c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/cannonlake/acpi.c | 15 ++------------- src/soc/intel/cannonlake/acpi/dptf.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/gpio.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/gpio_op.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/ish.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/pch_glan.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/pch_hda.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/pcie.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/platform.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/scs.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/serialio.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/smbus.asl | 15 ++------------- src/soc/intel/cannonlake/acpi/xhci.asl | 15 ++------------- src/soc/intel/cannonlake/bootblock/bootblock.c | 15 ++------------- src/soc/intel/cannonlake/bootblock/cpu.c | 15 ++------------- src/soc/intel/cannonlake/bootblock/pch.c | 15 ++------------- .../intel/cannonlake/bootblock/report_platform.c | 15 ++------------- src/soc/intel/cannonlake/chip.c | 15 ++------------- src/soc/intel/cannonlake/chip.h | 15 ++------------- src/soc/intel/cannonlake/cnl_memcfg_init.c | 15 ++------------- src/soc/intel/cannonlake/cpu.c | 15 ++------------- src/soc/intel/cannonlake/elog.c | 15 ++------------- src/soc/intel/cannonlake/finalize.c | 15 ++------------- src/soc/intel/cannonlake/fsp_params.c | 15 ++------------- src/soc/intel/cannonlake/i2c.c | 15 ++------------- src/soc/intel/cannonlake/include/soc/bootblock.h | 15 ++------------- .../cannonlake/include/soc/cnl_memcfg_init.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/cpu.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/gpe.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/gpio.h | 15 ++------------- .../intel/cannonlake/include/soc/gpio_common.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/gpio_defs.h | 15 ++------------- .../cannonlake/include/soc/gpio_defs_cnp_h.h | 15 ++------------- .../intel/cannonlake/include/soc/gpio_soc_defs.h | 15 ++------------- .../cannonlake/include/soc/gpio_soc_defs_cnp_h.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/iomap.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/irq.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/itss.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/lpc.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/me.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/msr.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/nvs.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/p2sb.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/pch.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/pcr_ids.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/pm.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/pmc.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/ramstage.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/romstage.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/sata.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/serialio.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/smbus.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/soc_chip.h | 15 ++------------- .../intel/cannonlake/include/soc/systemagent.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/usb.h | 15 ++------------- src/soc/intel/cannonlake/include/soc/vr_config.h | 15 ++------------- src/soc/intel/cannonlake/lockdown.c | 15 ++------------- src/soc/intel/cannonlake/lpc.c | 15 ++------------- src/soc/intel/cannonlake/me.c | 15 ++------------- src/soc/intel/cannonlake/p2sb.c | 15 ++------------- src/soc/intel/cannonlake/pmc.c | 15 ++------------- src/soc/intel/cannonlake/pmutil.c | 15 ++------------- src/soc/intel/cannonlake/reset.c | 15 ++------------- src/soc/intel/cannonlake/romstage/fsp_params.c | 15 ++------------- src/soc/intel/cannonlake/romstage/pch.c | 15 ++------------- src/soc/intel/cannonlake/romstage/romstage.c | 15 ++------------- src/soc/intel/cannonlake/romstage/systemagent.c | 15 ++------------- src/soc/intel/cannonlake/sd.c | 15 ++------------- src/soc/intel/cannonlake/smihandler.c | 15 ++------------- src/soc/intel/cannonlake/smmrelocate.c | 15 ++------------- src/soc/intel/cannonlake/systemagent.c | 15 ++------------- src/soc/intel/cannonlake/uart.c | 15 ++------------- src/soc/intel/cannonlake/vr_config.c | 16 ++-------------- src/soc/intel/cannonlake/xhci.c | 15 ++------------- 76 files changed, 152 insertions(+), 989 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 67c8c63fd8..0c806b5d60 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/acpi/dptf.asl b/src/soc/intel/cannonlake/acpi/dptf.asl index 7ae279cdf8..531387ca48 100644 --- a/src/soc/intel/cannonlake/acpi/dptf.asl +++ b/src/soc/intel/cannonlake/acpi/dptf.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define DPTF_CPU_DEVICE TCPU #define DPTF_CPU_ADDR 0x00040000 diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 060280c882..7f41c6bffd 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index d6226356b2..5c9a6596ce 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index e25c903479..f7736b9da1 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Get GPIO Value diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl index 65f042055b..f7ee4e9023 100644 --- a/src/soc/intel/cannonlake/acpi/ish.asl +++ b/src/soc/intel/cannonlake/acpi/ish.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Integrated Sensor Hub Controller 0:13.0 */ diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/cannonlake/acpi/pch_glan.asl index 2d9d960565..174f993ec2 100644 --- a/src/soc/intel/cannonlake/acpi/pch_glan.asl +++ b/src/soc/intel/cannonlake/acpi/pch_glan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Gigabit Ethernet Controller 0:1f.6 */ diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index 0d10d2deb5..78ae2c2b5b 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Audio Controller - Device 31, Function 3 */ diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index b837fe4a87..0fe550870d 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH PCIe support */ diff --git a/src/soc/intel/cannonlake/acpi/platform.asl b/src/soc/intel/cannonlake/acpi/platform.asl index 682a7b93d8..a579b97844 100644 --- a/src/soc/intel/cannonlake/acpi/platform.asl +++ b/src/soc/intel/cannonlake/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 6cdb99fe7a..775c99781a 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/cannonlake/acpi/serialio.asl b/src/soc/intel/cannonlake/acpi/serialio.asl index 2a1cc6b2dd..2785e3d2c2 100644 --- a/src/soc/intel/cannonlake/acpi/serialio.asl +++ b/src/soc/intel/cannonlake/acpi/serialio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Serial IO Devices */ diff --git a/src/soc/intel/cannonlake/acpi/smbus.asl b/src/soc/intel/cannonlake/acpi/smbus.asl index 7678d4fff2..5a8271e9a7 100644 --- a/src/soc/intel/cannonlake/acpi/smbus.asl +++ b/src/soc/intel/cannonlake/acpi/smbus.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SMBus Controller 0:1f.4 diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 5f11c4849e..3019c2f629 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index d5d178cc8e..21b8487ace 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index 0523aa0dbe..bfb23b64e4 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 7cff74b689..d67edea21c 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 5cc627a8f6..ab676fed16 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a2a678ba28..d3918a360b 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 7794fd44dd..578473b79b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index eac691e18b..f9f4256344 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 9f3fe1dc8d..689677ebb7 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 6c26e6a08d..ec411a4551 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index e3d33e3aa4..d777830190 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 46348060ef..434bd2b23b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c index df95df924a..6d9d299c71 100644 --- a/src/soc/intel/cannonlake/i2c.c +++ b/src/soc/intel/cannonlake/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h index ec954e6dd6..72db65db13 100644 --- a/src/soc/intel/cannonlake/include/soc/bootblock.h +++ b/src/soc/intel/cannonlake/include/soc/bootblock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_BOOTBLOCK_H_ #define _SOC_CANNONLAKE_BOOTBLOCK_H_ diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index f757fd8968..eaf1b27485 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_MEMCFG_INIT_H_ #define _SOC_CANNONLAKE_MEMCFG_INIT_H_ diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index d9f4f552a1..8fa6dab586 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_CPU_H_ #define _SOC_CANNONLAKE_CPU_H_ diff --git a/src/soc/intel/cannonlake/include/soc/gpe.h b/src/soc/intel/cannonlake/include/soc/gpe.h index c37750b1c4..cae23a0725 100644 --- a/src/soc/intel/cannonlake/include/soc/gpe.h +++ b/src/soc/intel/cannonlake/include/soc/gpe.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index d8879d3608..b37b8d0216 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_GPIO_H_ #define _SOC_CANNONLAKE_GPIO_H_ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h index 4cae6e54f1..4c21c46010 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_common.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_common.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_ #define _SOC_CANNONLAKE_GPIO_COMMON_H_ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index ae59941e15..5720c9e006 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_GPIO_DEFS_H_ #define _SOC_CANNONLAKE_GPIO_DEFS_H_ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index 67396a97a6..5527e87d08 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_ #define _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index c40f4cf447..3ca14f7bbc 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_ #define _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index 8e135b0ed3..5b9873239b 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_CNP_H_H_ #define _SOC_CANNONLAKE_GPIO_SOC_DEFS_CNP_H_H_ diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index b75bbed863..d420862dd3 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_IOMAP_H_ #define _SOC_CANNONLAKE_IOMAP_H_ diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 898ad2ea2f..f575580864 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h index 84ccc74f5c..ca76d6879d 100644 --- a/src/soc/intel/cannonlake/include/soc/itss.h +++ b/src/soc/intel/cannonlake/include/soc/itss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_CNL_ITSS_H #define SOC_INTEL_CNL_ITSS_H diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index efa7c8c618..60377f2287 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_LPC_H_ #define _SOC_CANNONLAKE_LPC_H_ diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index cd65d40604..55dd1f5d72 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CANNONLAKE_ME_H_ #define _CANNONLAKE_ME_H_ diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 858225cfac..73b4a63784 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h index cfb189d381..d059b00915 100644 --- a/src/soc/intel/cannonlake/include/soc/nvs.h +++ b/src/soc/intel/cannonlake/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ diff --git a/src/soc/intel/cannonlake/include/soc/p2sb.h b/src/soc/intel/cannonlake/include/soc/p2sb.h index 737d11ac1a..0109697eaa 100644 --- a/src/soc/intel/cannonlake/include/soc/p2sb.h +++ b/src/soc/intel/cannonlake/include/soc/p2sb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_P2SB_H_ #define _SOC_CANNONLAKE_P2SB_H_ diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index bf80600170..20ba674c81 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_PCH_H_ #define _SOC_CANNONLAKE_PCH_H_ diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 1a1deabea6..95046fdaf3 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_PCI_DEVS_H_ #define _SOC_CANNONLAKE_PCI_DEVS_H_ diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index 99c37bca9c..d9ebb70b3e 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_CANNONLAKE_PCR_H #define SOC_CANNONLAKE_PCR_H diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 65bfa0733e..7d4fcc39c9 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index e6d5eb3892..90929d5d06 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_PMC_H_ #define _SOC_CANNONLAKE_PMC_H_ diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 067f63d682..7788668b9c 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 4fed172a65..46ab5496f8 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ diff --git a/src/soc/intel/cannonlake/include/soc/sata.h b/src/soc/intel/cannonlake/include/soc/sata.h index dc2822619d..23c674d202 100644 --- a/src/soc/intel/cannonlake/include/soc/sata.h +++ b/src/soc/intel/cannonlake/include/soc/sata.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_SATA_H_ diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index d435d3b58f..ca75376c30 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index 29bc300312..f390020614 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_SMBUS_H_ #define _SOC_CANNONLAKE_SMBUS_H_ diff --git a/src/soc/intel/cannonlake/include/soc/soc_chip.h b/src/soc/intel/cannonlake/include/soc/soc_chip.h index 5abf328d86..944f190554 100644 --- a/src/soc/intel/cannonlake/include/soc/soc_chip.h +++ b/src/soc/intel/cannonlake/include/soc/soc_chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CANNONLAKE_SOC_CHIP_H_ #define _SOC_CANNONLAKE_SOC_CHIP_H_ diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h index a32118535d..cfe1630317 100644 --- a/src/soc/intel/cannonlake/include/soc/systemagent.h +++ b/src/soc/intel/cannonlake/include/soc/systemagent.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_CANNONLAKE_SYSTEMAGENT_H #define SOC_CANNONLAKE_SYSTEMAGENT_H diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 33c0bf0bf9..4caa4022a3 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_USB_H_ diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index b131f75f8c..c43beac092 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* VR Settings for each domain */ diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index 43ab853121..dbf05b5088 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 34fd1aacaf..4fe7bec8d6 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 174261a287..60669e0aa9 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/p2sb.c b/src/soc/intel/cannonlake/p2sb.c index 328c4d3bab..38248a4acb 100644 --- a/src/soc/intel/cannonlake/p2sb.c +++ b/src/soc/intel/cannonlake/p2sb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 7812eeb3ca..9a082577d1 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index b263892d7d..912743e3fc 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Helper functions for dealing with power management registers diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 431a70ccb0..8b9a7fa800 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ee05b66839..c84e3516c0 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c index c05c84820a..7b9972bcc0 100644 --- a/src/soc/intel/cannonlake/romstage/pch.c +++ b/src/soc/intel/cannonlake/romstage/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 2be8cc0de5..836738b335 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c index f30caecfc3..7913a43197 100644 --- a/src/soc/intel/cannonlake/romstage/systemagent.c +++ b/src/soc/intel/cannonlake/romstage/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c index 9626dccb22..68c9bcad2f 100644 --- a/src/soc/intel/cannonlake/sd.c +++ b/src/soc/intel/cannonlake/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "chip.h" diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index abf548c203..1a50fcf86d 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index fdacff6476..782809769c 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 8cfa8d2bc7..1ab365e97a 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 50849560ac..83866c347b 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index af3f1ecd0d..87fb0f0a87 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/cannonlake/xhci.c b/src/soc/intel/cannonlake/xhci.c index 95d3031e98..9ba1d52aff 100644 --- a/src/soc/intel/cannonlake/xhci.c +++ b/src/soc/intel/cannonlake/xhci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include From 80d9238610e979d0208677d06b9bd26656a2ac1e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:47:00 +0200 Subject: [PATCH 0897/1463] soc/intel/denverton_ns: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib1e226e7816efbc5cffc95563b440fb2ad5b1f95 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40214 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/denverton_ns/acpi.c | 16 ++-------------- src/soc/intel/denverton_ns/acpi/globalnvs.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/irqlinks.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/lpc.asl | 16 ++-------------- .../intel/denverton_ns/acpi/northcluster.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/npk.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/pcie.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/pcie_port.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/pmc.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/sata.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/sata2.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/smbus.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/smbus2.asl | 16 ++-------------- .../intel/denverton_ns/acpi/southcluster.asl | 16 ++-------------- src/soc/intel/denverton_ns/acpi/xhci.asl | 16 ++-------------- src/soc/intel/denverton_ns/chip.h | 16 ++-------------- src/soc/intel/denverton_ns/csme_ie_kt.c | 16 ++-------------- src/soc/intel/denverton_ns/fiamux.c | 16 ++-------------- src/soc/intel/denverton_ns/gpio_dnv.c | 16 ++-------------- src/soc/intel/denverton_ns/hob_mem.c | 15 ++------------- src/soc/intel/denverton_ns/include/soc/acpi.h | 16 ++-------------- .../intel/denverton_ns/include/soc/bootblock.h | 15 ++------------- src/soc/intel/denverton_ns/include/soc/cpu.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/fiamux.h | 15 ++------------- src/soc/intel/denverton_ns/include/soc/gpio.h | 16 ++-------------- .../intel/denverton_ns/include/soc/gpio_defs.h | 16 ++-------------- .../intel/denverton_ns/include/soc/gpio_dnv.h | 16 ++-------------- .../intel/denverton_ns/include/soc/hob_mem.h | 15 ++------------- src/soc/intel/denverton_ns/include/soc/iomap.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/lpc.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/msr.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/nvs.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/p2sb.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/pattrs.h | 16 ++-------------- .../intel/denverton_ns/include/soc/pci_devs.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/pcr.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/pm.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/pmc.h | 16 ++-------------- .../intel/denverton_ns/include/soc/ramstage.h | 15 ++------------- src/soc/intel/denverton_ns/include/soc/sata.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/smbus.h | 15 ++------------- src/soc/intel/denverton_ns/include/soc/smm.h | 16 ++-------------- .../intel/denverton_ns/include/soc/soc_util.h | 16 ++-------------- .../denverton_ns/include/soc/systemagent.h | 16 ++-------------- src/soc/intel/denverton_ns/include/soc/uart.h | 16 ++-------------- src/soc/intel/denverton_ns/lpc.c | 16 ++-------------- src/soc/intel/denverton_ns/npk.c | 16 ++-------------- src/soc/intel/denverton_ns/pmc.c | 16 ++-------------- src/soc/intel/denverton_ns/pmutil.c | 16 ++-------------- src/soc/intel/denverton_ns/reset.c | 15 ++------------- src/soc/intel/denverton_ns/romstage.c | 15 ++------------- src/soc/intel/denverton_ns/sata.c | 16 ++-------------- src/soc/intel/denverton_ns/smihandler.c | 16 ++-------------- src/soc/intel/denverton_ns/smm.c | 17 ++--------------- src/soc/intel/denverton_ns/soc_util.c | 16 ++-------------- src/soc/intel/denverton_ns/systemagent.c | 15 ++------------- src/soc/intel/denverton_ns/tsc_freq.c | 16 ++-------------- src/soc/intel/denverton_ns/xhci.c | 16 ++-------------- 58 files changed, 116 insertions(+), 804 deletions(-) diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d3e2853c6a..00c9ba4f85 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index c98d50b8a0..7e4b826ea1 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Global Variables */ diff --git a/src/soc/intel/denverton_ns/acpi/irqlinks.asl b/src/soc/intel/denverton_ns/acpi/irqlinks.asl index f8ef5389e3..e2cc761a2a 100644 --- a/src/soc/intel/denverton_ns/acpi/irqlinks.asl +++ b/src/soc/intel/denverton_ns/acpi/irqlinks.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Device (LNKA) { diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index f1d2724e55..5082c9d2ad 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel LPC Bus Device - 0:1f.0 #include diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index d5065e00e3..352cad76c9 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../include/soc/iomap.h" diff --git a/src/soc/intel/denverton_ns/acpi/npk.asl b/src/soc/intel/denverton_ns/acpi/npk.asl index d7a2cd1418..b2d1e7995f 100644 --- a/src/soc/intel/denverton_ns/acpi/npk.asl +++ b/src/soc/intel/denverton_ns/acpi/npk.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel NPK Controller 0:1f.7 diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index ddd79f9c4b..0f945659d7 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel 6/7 Series PCH PCIe support */ diff --git a/src/soc/intel/denverton_ns/acpi/pcie_port.asl b/src/soc/intel/denverton_ns/acpi/pcie_port.asl index 083ba303e7..93937c4c85 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie_port.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie_port.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Included in each PCIe Root Port device */ diff --git a/src/soc/intel/denverton_ns/acpi/pmc.asl b/src/soc/intel/denverton_ns/acpi/pmc.asl index 40b6d207fa..dddf66be87 100644 --- a/src/soc/intel/denverton_ns/acpi/pmc.asl +++ b/src/soc/intel/denverton_ns/acpi/pmc.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel PMC Controller 0:1f.2 diff --git a/src/soc/intel/denverton_ns/acpi/sata.asl b/src/soc/intel/denverton_ns/acpi/sata.asl index 28daffafcf..4e305e8f17 100644 --- a/src/soc/intel/denverton_ns/acpi/sata.asl +++ b/src/soc/intel/denverton_ns/acpi/sata.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SATA Controller 0:13.0 diff --git a/src/soc/intel/denverton_ns/acpi/sata2.asl b/src/soc/intel/denverton_ns/acpi/sata2.asl index 63043f5e72..e4111519da 100644 --- a/src/soc/intel/denverton_ns/acpi/sata2.asl +++ b/src/soc/intel/denverton_ns/acpi/sata2.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SATA Controller 0:14.0 diff --git a/src/soc/intel/denverton_ns/acpi/smbus.asl b/src/soc/intel/denverton_ns/acpi/smbus.asl index 2f95a739d2..1e8d6f54f1 100644 --- a/src/soc/intel/denverton_ns/acpi/smbus.asl +++ b/src/soc/intel/denverton_ns/acpi/smbus.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SMBus Controller 0:1f.4 diff --git a/src/soc/intel/denverton_ns/acpi/smbus2.asl b/src/soc/intel/denverton_ns/acpi/smbus2.asl index 039daf7e64..4b8973de48 100644 --- a/src/soc/intel/denverton_ns/acpi/smbus2.asl +++ b/src/soc/intel/denverton_ns/acpi/smbus2.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SMBus Controller 0:12.0 diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index d17f238b15..0bc93785b1 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include "../include/soc/iomap.h" diff --git a/src/soc/intel/denverton_ns/acpi/xhci.asl b/src/soc/intel/denverton_ns/acpi/xhci.asl index a7a2f556da..3db600b48e 100644 --- a/src/soc/intel/denverton_ns/acpi/xhci.asl +++ b/src/soc/intel/denverton_ns/acpi/xhci.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // XHCI Controller 0:15.0 diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index d2e4103e8d..bb01ef3fed 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_DENVERTON_NS_CHIP_H #define SOC_INTEL_DENVERTON_NS_CHIP_H diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index a8d081af4c..84ee919bfe 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/fiamux.c b/src/soc/intel/denverton_ns/fiamux.c index acc462563b..db966cc975 100644 --- a/src/soc/intel/denverton_ns/fiamux.c +++ b/src/soc/intel/denverton_ns/fiamux.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 005a1fe1d9..e65638c735 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index ad3d3591a6..f1d9a39c69 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index e8f9b60ddb..d248962ad1 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_ACPI_H_ #define _DENVERTON_NS_ACPI_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h index 98b82a460a..021715393a 100644 --- a/src/soc/intel/denverton_ns/include/soc/bootblock.h +++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_DENVERTON_NS_BOOTBLOCK_H_ #define _SOC_DENVERTON_NS_BOOTBLOCK_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index bba20c4da2..f6869620ca 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CPU_INTEL_DENVERTON_NS_H #define _CPU_INTEL_DENVERTON_NS_H diff --git a/src/soc/intel/denverton_ns/include/soc/fiamux.h b/src/soc/intel/denverton_ns/include/soc/fiamux.h index 5f3ec54fd5..e2e4af8a09 100644 --- a/src/soc/intel/denverton_ns/include/soc/fiamux.h +++ b/src/soc/intel/denverton_ns/include/soc/fiamux.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_FIAMUX_H #define _DENVERTON_NS_FIAMUX_H diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h index 2012a47403..5e43c26a0e 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_DENVERTON_NS_GPIO_H_ #define _SOC_DENVERTON_NS_GPIO_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index 06fe26df21..e7791312d5 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_GPIO_DEFS_H_ #define _DENVERTON_NS_GPIO_DEFS_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h index d32b937ca9..c40d695466 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_GPIO_H_ #define _DENVERTON_NS_GPIO_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/hob_mem.h b/src/soc/intel/denverton_ns/include/soc/hob_mem.h index 9d356b8d4e..fad20fe1cf 100644 --- a/src/soc/intel/denverton_ns/include/soc/hob_mem.h +++ b/src/soc/intel/denverton_ns/include/soc/hob_mem.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_HOB_MEM_H diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 011b47d3a2..73ea43d64f 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_IOMAP_H_ #define _DENVERTON_NS_IOMAP_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/lpc.h b/src/soc/intel/denverton_ns/include/soc/lpc.h index 18486c2070..fd96fa8173 100644 --- a/src/soc/intel/denverton_ns/include/soc/lpc.h +++ b/src/soc/intel/denverton_ns/include/soc/lpc.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_LPC_H_ #define _DENVERTON_NS_LPC_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index f7657270de..3e47b9c86b 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_MSR_H_ #define _DENVERTON_NS_MSR_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index 1dafef76a5..1c82179205 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_NVS_H_ #define _DENVERTON_NS_NVS_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/p2sb.h b/src/soc/intel/denverton_ns/include/soc/p2sb.h index 0a98382baa..3b079324ee 100644 --- a/src/soc/intel/denverton_ns/include/soc/p2sb.h +++ b/src/soc/intel/denverton_ns/include/soc/p2sb.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_P2SB_H_ #define _DENVERTON_NS_P2SB_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/pattrs.h b/src/soc/intel/denverton_ns/include/soc/pattrs.h index 7bf794b232..c56c7a384a 100644 --- a/src/soc/intel/denverton_ns/include/soc/pattrs.h +++ b/src/soc/intel/denverton_ns/include/soc/pattrs.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_PATTRS_H_ #define _DENVERTON_NS_PATTRS_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index 1345fc8d21..198c0696c4 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_PCI_DEVS_H_ #define _DENVERTON_NS_PCI_DEVS_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/pcr.h b/src/soc/intel/denverton_ns/include/soc/pcr.h index d8632182ba..c7da09f46f 100644 --- a/src/soc/intel/denverton_ns/include/soc/pcr.h +++ b/src/soc/intel/denverton_ns/include/soc/pcr.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_PCR_H_ #define _DENVERTON_NS_PCR_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index dec1e0d63b..9e03c03432 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_PM_H_ #define _DENVERTON_NS_PM_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index d026c4c969..be4ec6ffbc 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_PMC_H_ #define _DENVERTON_NS_PMC_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/ramstage.h b/src/soc/intel/denverton_ns/include/soc/ramstage.h index ecbc5c1d8b..34a31b2b60 100644 --- a/src/soc/intel/denverton_ns/include/soc/ramstage.h +++ b/src/soc/intel/denverton_ns/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_SOC_RAMSTAGE_H_ #define _DENVERTON_NS_SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/sata.h b/src/soc/intel/denverton_ns/include/soc/sata.h index 134e8720ae..d02944a481 100644 --- a/src/soc/intel/denverton_ns/include/soc/sata.h +++ b/src/soc/intel/denverton_ns/include/soc/sata.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_SATA_H #define _DENVERTON_NS_SATA_H diff --git a/src/soc/intel/denverton_ns/include/soc/smbus.h b/src/soc/intel/denverton_ns/include/soc/smbus.h index ebac2766f9..4708c79eb6 100644 --- a/src/soc/intel/denverton_ns/include/soc/smbus.h +++ b/src/soc/intel/denverton_ns/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_SMBUS_H_ #define _DENVERTON_NS_SMBUS_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index 0a469618f8..604ff522b5 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_SMM_H_ #define _DENVERTON_NS_SMM_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h index 7c8c67a2fe..5309f15021 100644 --- a/src/soc/intel/denverton_ns/include/soc/soc_util.h +++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_SOC_UTIL_H_ #define _DENVERTON_NS_SOC_UTIL_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/systemagent.h b/src/soc/intel/denverton_ns/include/soc/systemagent.h index 968105c328..f6ebd50e14 100644 --- a/src/soc/intel/denverton_ns/include/soc/systemagent.h +++ b/src/soc/intel/denverton_ns/include/soc/systemagent.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_SYSTEMAGENT_H_ #define _DENVERTON_NS_SYSTEMAGENT_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/uart.h b/src/soc/intel/denverton_ns/include/soc/uart.h index fb8aa13bbe..cf3ee9724b 100644 --- a/src/soc/intel/denverton_ns/include/soc/uart.h +++ b/src/soc/intel/denverton_ns/include/soc/uart.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _DENVERTON_NS_UART_H #define _DENVERTON_NS_UART_H diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index f695d6123f..b1f045a821 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index c22a5c2d40..cf8c7dfc0c 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 4094b0953a..2ba4531deb 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 9366ec2183..b0f8908f99 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/reset.c b/src/soc/intel/denverton_ns/reset.c index 7b7146d057..4b82ff737a 100644 --- a/src/soc/intel/denverton_ns/reset.c +++ b/src/soc/intel/denverton_ns/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 5793aa25ba..95688bcf45 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 9ee6254424..d09054a992 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 2d0a256aaf..276ab096af 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 97ae37c51a..92859824f4 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index bb1cdcea5b..c547e08f1a 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 8af1c4f376..1889b7b164 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/tsc_freq.c b/src/soc/intel/denverton_ns/tsc_freq.c index 8e8565902a..ead10ee12b 100644 --- a/src/soc/intel/denverton_ns/tsc_freq.c +++ b/src/soc/intel/denverton_ns/tsc_freq.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index be961de332..3a43bbd2b7 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 32abdd66a89ba402b56311b827d3e90cec13aaaf Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:47:03 +0200 Subject: [PATCH 0898/1463] soc/intel/icelake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1edbc8bb0efaad033385f29f8a4747bd178296b9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40215 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/icelake/acpi.c | 15 ++------------- src/soc/intel/icelake/acpi/gpio.asl | 15 ++------------- src/soc/intel/icelake/acpi/pch_glan.asl | 15 ++------------- src/soc/intel/icelake/acpi/pch_hda.asl | 15 ++------------- src/soc/intel/icelake/acpi/pcie.asl | 15 ++------------- src/soc/intel/icelake/acpi/platform.asl | 15 ++------------- src/soc/intel/icelake/acpi/scs.asl | 15 ++------------- src/soc/intel/icelake/acpi/serialio.asl | 15 ++------------- src/soc/intel/icelake/acpi/smbus.asl | 15 ++------------- src/soc/intel/icelake/acpi/xhci.asl | 15 ++------------- src/soc/intel/icelake/bootblock/bootblock.c | 15 ++------------- src/soc/intel/icelake/bootblock/cpu.c | 15 ++------------- src/soc/intel/icelake/bootblock/pch.c | 15 ++------------- src/soc/intel/icelake/bootblock/report_platform.c | 15 ++------------- src/soc/intel/icelake/chip.c | 15 ++------------- src/soc/intel/icelake/chip.h | 15 ++------------- src/soc/intel/icelake/cpu.c | 15 ++------------- src/soc/intel/icelake/elog.c | 15 ++------------- src/soc/intel/icelake/espi.c | 15 ++------------- src/soc/intel/icelake/finalize.c | 15 ++------------- src/soc/intel/icelake/fsp_params.c | 15 ++------------- src/soc/intel/icelake/i2c.c | 15 ++------------- src/soc/intel/icelake/include/soc/bootblock.h | 15 ++------------- src/soc/intel/icelake/include/soc/cpu.h | 15 ++------------- src/soc/intel/icelake/include/soc/espi.h | 15 ++------------- src/soc/intel/icelake/include/soc/gpe.h | 15 ++------------- src/soc/intel/icelake/include/soc/gpio.h | 15 ++------------- src/soc/intel/icelake/include/soc/gpio_defs.h | 15 ++------------- src/soc/intel/icelake/include/soc/gpio_soc_defs.h | 15 ++------------- src/soc/intel/icelake/include/soc/iomap.h | 15 ++------------- src/soc/intel/icelake/include/soc/irq.h | 15 ++------------- src/soc/intel/icelake/include/soc/itss.h | 15 ++------------- src/soc/intel/icelake/include/soc/me.h | 15 ++------------- src/soc/intel/icelake/include/soc/msr.h | 15 ++------------- src/soc/intel/icelake/include/soc/nvs.h | 15 ++------------- src/soc/intel/icelake/include/soc/p2sb.h | 15 ++------------- src/soc/intel/icelake/include/soc/pch.h | 15 ++------------- src/soc/intel/icelake/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/icelake/include/soc/pcr_ids.h | 15 ++------------- src/soc/intel/icelake/include/soc/pm.h | 15 ++------------- src/soc/intel/icelake/include/soc/pmc.h | 15 ++------------- src/soc/intel/icelake/include/soc/ramstage.h | 15 ++------------- src/soc/intel/icelake/include/soc/romstage.h | 15 ++------------- src/soc/intel/icelake/include/soc/serialio.h | 15 ++------------- src/soc/intel/icelake/include/soc/smbus.h | 15 ++------------- src/soc/intel/icelake/include/soc/soc_chip.h | 15 ++------------- src/soc/intel/icelake/include/soc/systemagent.h | 15 ++------------- src/soc/intel/icelake/include/soc/usb.h | 15 ++------------- src/soc/intel/icelake/lockdown.c | 15 ++------------- src/soc/intel/icelake/p2sb.c | 15 ++------------- src/soc/intel/icelake/pmc.c | 15 ++------------- src/soc/intel/icelake/pmutil.c | 15 ++------------- src/soc/intel/icelake/reset.c | 15 ++------------- src/soc/intel/icelake/romstage/fsp_params.c | 15 ++------------- src/soc/intel/icelake/romstage/pch.c | 15 ++------------- src/soc/intel/icelake/romstage/romstage.c | 15 ++------------- src/soc/intel/icelake/romstage/systemagent.c | 15 ++------------- src/soc/intel/icelake/sd.c | 15 ++------------- src/soc/intel/icelake/smihandler.c | 15 ++------------- src/soc/intel/icelake/smmrelocate.c | 15 ++------------- src/soc/intel/icelake/systemagent.c | 15 ++------------- src/soc/intel/icelake/uart.c | 15 ++------------- 62 files changed, 124 insertions(+), 806 deletions(-) diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 057db1ed65..327dd112b8 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index 40a1e9ef30..b0efa44c67 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/icelake/acpi/pch_glan.asl b/src/soc/intel/icelake/acpi/pch_glan.asl index 2d9d960565..174f993ec2 100644 --- a/src/soc/intel/icelake/acpi/pch_glan.asl +++ b/src/soc/intel/icelake/acpi/pch_glan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Gigabit Ethernet Controller 0:1f.6 */ diff --git a/src/soc/intel/icelake/acpi/pch_hda.asl b/src/soc/intel/icelake/acpi/pch_hda.asl index 0d10d2deb5..78ae2c2b5b 100644 --- a/src/soc/intel/icelake/acpi/pch_hda.asl +++ b/src/soc/intel/icelake/acpi/pch_hda.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Audio Controller - Device 31, Function 3 */ diff --git a/src/soc/intel/icelake/acpi/pcie.asl b/src/soc/intel/icelake/acpi/pcie.asl index b837fe4a87..0fe550870d 100644 --- a/src/soc/intel/icelake/acpi/pcie.asl +++ b/src/soc/intel/icelake/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH PCIe support */ diff --git a/src/soc/intel/icelake/acpi/platform.asl b/src/soc/intel/icelake/acpi/platform.asl index 682a7b93d8..a579b97844 100644 --- a/src/soc/intel/icelake/acpi/platform.asl +++ b/src/soc/intel/icelake/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/icelake/acpi/scs.asl b/src/soc/intel/icelake/acpi/scs.asl index 9471da5b89..5cd74f6cf7 100644 --- a/src/soc/intel/icelake/acpi/scs.asl +++ b/src/soc/intel/icelake/acpi/scs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/icelake/acpi/serialio.asl b/src/soc/intel/icelake/acpi/serialio.asl index 2a1cc6b2dd..2785e3d2c2 100644 --- a/src/soc/intel/icelake/acpi/serialio.asl +++ b/src/soc/intel/icelake/acpi/serialio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Serial IO Devices */ diff --git a/src/soc/intel/icelake/acpi/smbus.asl b/src/soc/intel/icelake/acpi/smbus.asl index 7678d4fff2..5a8271e9a7 100644 --- a/src/soc/intel/icelake/acpi/smbus.asl +++ b/src/soc/intel/icelake/acpi/smbus.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Intel SMBus Controller 0:1f.4 diff --git a/src/soc/intel/icelake/acpi/xhci.asl b/src/soc/intel/icelake/acpi/xhci.asl index 3387430c04..2023334ee9 100644 --- a/src/soc/intel/icelake/acpi/xhci.asl +++ b/src/soc/intel/icelake/acpi/xhci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index 1abca127a3..6bf1e131d6 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/bootblock/cpu.c b/src/soc/intel/icelake/bootblock/cpu.c index 9d3903c5fa..7f0134e34e 100644 --- a/src/soc/intel/icelake/bootblock/cpu.c +++ b/src/soc/intel/icelake/bootblock/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 5f39622dd9..c240f3b946 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index 78c3869413..00224d94c2 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 304f7e3501..483e0d6e09 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index dd13259368..67d7ff593f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 57719c2d7b..b8ffb27800 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 903259497d..2aceea02ac 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 1fb720ac3a..c473e5469d 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index b3fd6176cb..e192ad37d7 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 806cb4ded1..523f41487f 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/i2c.c b/src/soc/intel/icelake/i2c.c index df95df924a..6d9d299c71 100644 --- a/src/soc/intel/icelake/i2c.c +++ b/src/soc/intel/icelake/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h index 27a2ce691d..34579267d4 100644 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ b/src/soc/intel/icelake/include/soc/bootblock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_BOOTBLOCK_H_ #define _SOC_ICELAKE_BOOTBLOCK_H_ diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index 312de72699..30df00aa7e 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_CPU_H_ #define _SOC_ICELAKE_CPU_H_ diff --git a/src/soc/intel/icelake/include/soc/espi.h b/src/soc/intel/icelake/include/soc/espi.h index 4fb762499c..593b23661b 100644 --- a/src/soc/intel/icelake/include/soc/espi.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_ESPI_H_ #define _SOC_ICELAKE_ESPI_H_ diff --git a/src/soc/intel/icelake/include/soc/gpe.h b/src/soc/intel/icelake/include/soc/gpe.h index c37750b1c4..cae23a0725 100644 --- a/src/soc/intel/icelake/include/soc/gpe.h +++ b/src/soc/intel/icelake/include/soc/gpe.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h index 9022aa84bf..f5228a3bde 100644 --- a/src/soc/intel/icelake/include/soc/gpio.h +++ b/src/soc/intel/icelake/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_GPIO_H_ #define _SOC_ICELAKE_GPIO_H_ diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index b01e406f97..c05e2a5806 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_GPIO_DEFS_H_ #define _SOC_ICELAKE_GPIO_DEFS_H_ diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h index 5de7960a03..3f19b08aaf 100644 --- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_GPIO_SOC_DEFS_H_ #define _SOC_ICELAKE_GPIO_SOC_DEFS_H_ diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 81d052c73b..df86373ce1 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_IOMAP_H_ #define _SOC_ICELAKE_IOMAP_H_ diff --git a/src/soc/intel/icelake/include/soc/irq.h b/src/soc/intel/icelake/include/soc/irq.h index 898ad2ea2f..f575580864 100644 --- a/src/soc/intel/icelake/include/soc/irq.h +++ b/src/soc/intel/icelake/include/soc/irq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ diff --git a/src/soc/intel/icelake/include/soc/itss.h b/src/soc/intel/icelake/include/soc/itss.h index 92fa026685..b345c1a550 100644 --- a/src/soc/intel/icelake/include/soc/itss.h +++ b/src/soc/intel/icelake/include/soc/itss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_ICL_ITSS_H #define SOC_INTEL_ICL_ITSS_H diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h index c6df81b93c..96b5936c8e 100644 --- a/src/soc/intel/icelake/include/soc/me.h +++ b/src/soc/intel/icelake/include/soc/me.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _ICELAKE_ME_H_ #define _ICELAKE_ME_H_ diff --git a/src/soc/intel/icelake/include/soc/msr.h b/src/soc/intel/icelake/include/soc/msr.h index 7925ea76b0..3bbf99d21b 100644 --- a/src/soc/intel/icelake/include/soc/msr.h +++ b/src/soc/intel/icelake/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h index cfb189d381..d059b00915 100644 --- a/src/soc/intel/icelake/include/soc/nvs.h +++ b/src/soc/intel/icelake/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ diff --git a/src/soc/intel/icelake/include/soc/p2sb.h b/src/soc/intel/icelake/include/soc/p2sb.h index f444c837b4..f3890106b1 100644 --- a/src/soc/intel/icelake/include/soc/p2sb.h +++ b/src/soc/intel/icelake/include/soc/p2sb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_P2SB_H_ #define _SOC_ICELAKE_P2SB_H_ diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h index fa28a4d07a..4f0a486ab0 100644 --- a/src/soc/intel/icelake/include/soc/pch.h +++ b/src/soc/intel/icelake/include/soc/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_PCH_H_ #define _SOC_ICELAKE_PCH_H_ diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 21feeabfe0..71dc1da690 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_PCI_DEVS_H_ #define _SOC_ICELAKE_PCI_DEVS_H_ diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h index 034b622c93..89386e10ea 100644 --- a/src/soc/intel/icelake/include/soc/pcr_ids.h +++ b/src/soc/intel/icelake/include/soc/pcr_ids.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_ICELAKE_PCR_H #define SOC_ICELAKE_PCR_H diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 66b09751e4..cb59a21b7b 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index f7a6ccb2b3..95237542b5 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_PMC_H_ #define _SOC_ICELAKE_PMC_H_ diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h index a8c8fdd7b2..1f79b33d93 100644 --- a/src/soc/intel/icelake/include/soc/ramstage.h +++ b/src/soc/intel/icelake/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h index 1672e8b5ca..4a4fbe63b8 100644 --- a/src/soc/intel/icelake/include/soc/romstage.h +++ b/src/soc/intel/icelake/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h index 0ee6ff1dc3..fdc85875e0 100644 --- a/src/soc/intel/icelake/include/soc/serialio.h +++ b/src/soc/intel/icelake/include/soc/serialio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index 8cadd05802..6dc07d445c 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_SMBUS_H_ #define _SOC_ICELAKE_SMBUS_H_ diff --git a/src/soc/intel/icelake/include/soc/soc_chip.h b/src/soc/intel/icelake/include/soc/soc_chip.h index 272e60386c..d11769db95 100644 --- a/src/soc/intel/icelake/include/soc/soc_chip.h +++ b/src/soc/intel/icelake/include/soc/soc_chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ICELAKE_SOC_CHIP_H_ #define _SOC_ICELAKE_SOC_CHIP_H_ diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 013f9ce97c..7b6a680d75 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_ICELAKE_SYSTEMAGENT_H #define SOC_ICELAKE_SYSTEMAGENT_H diff --git a/src/soc/intel/icelake/include/soc/usb.h b/src/soc/intel/icelake/include/soc/usb.h index 33c0bf0bf9..4caa4022a3 100644 --- a/src/soc/intel/icelake/include/soc/usb.h +++ b/src/soc/intel/icelake/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_USB_H_ diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c index 43ab853121..dbf05b5088 100644 --- a/src/soc/intel/icelake/lockdown.c +++ b/src/soc/intel/icelake/lockdown.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/p2sb.c b/src/soc/intel/icelake/p2sb.c index 328c4d3bab..38248a4acb 100644 --- a/src/soc/intel/icelake/p2sb.c +++ b/src/soc/intel/icelake/p2sb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 4667f1d905..fdaec0db65 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 1dbbbc8d7d..75269ccaa6 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Helper functions for dealing with power management registers diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index 431a70ccb0..8b9a7fa800 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 0b52abe002..08fbeca3c3 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c index a005ea0b99..d56a234aba 100644 --- a/src/soc/intel/icelake/romstage/pch.c +++ b/src/soc/intel/icelake/romstage/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 35f97cb654..b97fafe992 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/romstage/systemagent.c b/src/soc/intel/icelake/romstage/systemagent.c index f30caecfc3..7913a43197 100644 --- a/src/soc/intel/icelake/romstage/systemagent.c +++ b/src/soc/intel/icelake/romstage/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c index d97b63f498..db22494208 100644 --- a/src/soc/intel/icelake/sd.c +++ b/src/soc/intel/icelake/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 1075b0910a..25481cc651 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 236b0a85e5..365424e4e0 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index 1e19caf9ac..c07fd0ac84 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 50849560ac..83866c347b 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From fabfe9da7796ab077ddb2100ddce8054b3328a70 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:47:07 +0200 Subject: [PATCH 0899/1463] soc/intel/jasperlake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2efdeb224c478995d393aa3eaac762c876832391 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40216 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/jasperlake/acpi.c | 15 ++------------- src/soc/intel/jasperlake/acpi/gpio.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/gpio_op.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/ipu.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/ish.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/pch_glan.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/pch_hda.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/pcie.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/platform.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/pmc.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/scs.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/serialio.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/smbus.asl | 15 ++------------- src/soc/intel/jasperlake/acpi/xhci.asl | 15 ++------------- src/soc/intel/jasperlake/bootblock/bootblock.c | 15 ++------------- src/soc/intel/jasperlake/bootblock/cpu.c | 15 ++------------- src/soc/intel/jasperlake/bootblock/pch.c | 15 ++------------- .../intel/jasperlake/bootblock/report_platform.c | 15 ++------------- src/soc/intel/jasperlake/chip.c | 15 ++------------- src/soc/intel/jasperlake/chip.h | 15 ++------------- src/soc/intel/jasperlake/cpu.c | 15 ++------------- src/soc/intel/jasperlake/elog.c | 15 ++------------- src/soc/intel/jasperlake/espi.c | 15 ++------------- src/soc/intel/jasperlake/finalize.c | 15 ++------------- src/soc/intel/jasperlake/fsp_params.c | 15 ++------------- src/soc/intel/jasperlake/i2c.c | 15 ++------------- src/soc/intel/jasperlake/include/soc/bootblock.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/cpu.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/espi.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/gpe.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/gpio.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/gpio_defs.h | 15 ++------------- .../intel/jasperlake/include/soc/gpio_soc_defs.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/iomap.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/irq.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/itss.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/me.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/meminit.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/msr.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/nvs.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/p2sb.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/pch.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/pcr_ids.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/pm.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/pmc.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/ramstage.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/romstage.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/serialio.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/smbus.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/soc_chip.h | 15 ++------------- .../intel/jasperlake/include/soc/systemagent.h | 15 ++------------- src/soc/intel/jasperlake/include/soc/usb.h | 15 ++------------- src/soc/intel/jasperlake/lockdown.c | 15 ++------------- src/soc/intel/jasperlake/meminit.c | 15 ++------------- src/soc/intel/jasperlake/p2sb.c | 15 ++------------- src/soc/intel/jasperlake/pmc.c | 15 ++------------- src/soc/intel/jasperlake/pmutil.c | 15 ++------------- src/soc/intel/jasperlake/reset.c | 15 ++------------- src/soc/intel/jasperlake/romstage/fsp_params.c | 15 ++------------- src/soc/intel/jasperlake/romstage/pch.c | 15 ++------------- src/soc/intel/jasperlake/romstage/romstage.c | 15 ++------------- src/soc/intel/jasperlake/romstage/systemagent.c | 15 ++------------- src/soc/intel/jasperlake/sd.c | 15 ++------------- src/soc/intel/jasperlake/smihandler.c | 15 ++------------- src/soc/intel/jasperlake/smmrelocate.c | 15 ++------------- src/soc/intel/jasperlake/systemagent.c | 15 ++------------- src/soc/intel/jasperlake/uart.c | 15 ++------------- 68 files changed, 136 insertions(+), 884 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 23fd970500..29a46195cd 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index 9bf0c6032f..2b4aff09c0 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl index 4444c09a5b..be346ae7e3 100644 --- a/src/soc/intel/jasperlake/acpi/gpio_op.asl +++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Get GPIO Value diff --git a/src/soc/intel/jasperlake/acpi/ipu.asl b/src/soc/intel/jasperlake/acpi/ipu.asl index 5711644bcb..337782d2cc 100644 --- a/src/soc/intel/jasperlake/acpi/ipu.asl +++ b/src/soc/intel/jasperlake/acpi/ipu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0) { diff --git a/src/soc/intel/jasperlake/acpi/ish.asl b/src/soc/intel/jasperlake/acpi/ish.asl index ee3f1a3fdf..bdd3cc74a9 100644 --- a/src/soc/intel/jasperlake/acpi/ish.asl +++ b/src/soc/intel/jasperlake/acpi/ish.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Integrated Sensor Hub Controller 0:12.0 */ diff --git a/src/soc/intel/jasperlake/acpi/pch_glan.asl b/src/soc/intel/jasperlake/acpi/pch_glan.asl index 2d9d960565..174f993ec2 100644 --- a/src/soc/intel/jasperlake/acpi/pch_glan.asl +++ b/src/soc/intel/jasperlake/acpi/pch_glan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Gigabit Ethernet Controller 0:1f.6 */ diff --git a/src/soc/intel/jasperlake/acpi/pch_hda.asl b/src/soc/intel/jasperlake/acpi/pch_hda.asl index 0d10d2deb5..78ae2c2b5b 100644 --- a/src/soc/intel/jasperlake/acpi/pch_hda.asl +++ b/src/soc/intel/jasperlake/acpi/pch_hda.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Audio Controller - Device 31, Function 3 */ diff --git a/src/soc/intel/jasperlake/acpi/pcie.asl b/src/soc/intel/jasperlake/acpi/pcie.asl index 53ae316413..ce9ce7db5c 100644 --- a/src/soc/intel/jasperlake/acpi/pcie.asl +++ b/src/soc/intel/jasperlake/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH PCIe support */ diff --git a/src/soc/intel/jasperlake/acpi/platform.asl b/src/soc/intel/jasperlake/acpi/platform.asl index 682a7b93d8..a579b97844 100644 --- a/src/soc/intel/jasperlake/acpi/platform.asl +++ b/src/soc/intel/jasperlake/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl index 0e3e24d94e..840ec462a6 100644 --- a/src/soc/intel/jasperlake/acpi/pmc.asl +++ b/src/soc/intel/jasperlake/acpi/pmc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl index 83da7e0f06..a2d9414ff0 100644 --- a/src/soc/intel/jasperlake/acpi/scs.asl +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/jasperlake/acpi/serialio.asl b/src/soc/intel/jasperlake/acpi/serialio.asl index 6fd135b437..f7506bb5e4 100644 --- a/src/soc/intel/jasperlake/acpi/serialio.asl +++ b/src/soc/intel/jasperlake/acpi/serialio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Serial IO Devices */ diff --git a/src/soc/intel/jasperlake/acpi/smbus.asl b/src/soc/intel/jasperlake/acpi/smbus.asl index f273e3669d..c0d092ae67 100644 --- a/src/soc/intel/jasperlake/acpi/smbus.asl +++ b/src/soc/intel/jasperlake/acpi/smbus.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel SMBus Controller 0:1f.4 */ diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl index 41be89ace1..87e88c7992 100644 --- a/src/soc/intel/jasperlake/acpi/xhci.asl +++ b/src/soc/intel/jasperlake/acpi/xhci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index 1abca127a3..6bf1e131d6 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/bootblock/cpu.c b/src/soc/intel/jasperlake/bootblock/cpu.c index 561172b2ae..f17cd4ddf1 100644 --- a/src/soc/intel/jasperlake/bootblock/cpu.c +++ b/src/soc/intel/jasperlake/bootblock/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index c98fdc5fb6..9c517feb56 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index 35f2d1aead..663c75818f 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 2b00f96e1e..6a560270e7 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 8611674332..3983d03b84 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 57719c2d7b..b8ffb27800 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 903259497d..2aceea02ac 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 500644e104..dff2f9d9a9 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 714cda15e5..d03c8c755b 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index be73ab7319..19b9300713 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/jasperlake/i2c.c b/src/soc/intel/jasperlake/i2c.c index df95df924a..6d9d299c71 100644 --- a/src/soc/intel/jasperlake/i2c.c +++ b/src/soc/intel/jasperlake/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h index a93cff8dad..69f3bfb480 100644 --- a/src/soc/intel/jasperlake/include/soc/bootblock.h +++ b/src/soc/intel/jasperlake/include/soc/bootblock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_BOOTBLOCK_H_ #define _SOC_JASPERLAKE_BOOTBLOCK_H_ diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index 96e29bfcb8..1ab96e5d05 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_CPU_H_ #define _SOC_JASPERLAKE_CPU_H_ diff --git a/src/soc/intel/jasperlake/include/soc/espi.h b/src/soc/intel/jasperlake/include/soc/espi.h index 7303a6d981..0850b7c829 100644 --- a/src/soc/intel/jasperlake/include/soc/espi.h +++ b/src/soc/intel/jasperlake/include/soc/espi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_ESPI_H_ #define _SOC_JASPERLAKE_ESPI_H_ diff --git a/src/soc/intel/jasperlake/include/soc/gpe.h b/src/soc/intel/jasperlake/include/soc/gpe.h index c37750b1c4..cae23a0725 100644 --- a/src/soc/intel/jasperlake/include/soc/gpe.h +++ b/src/soc/intel/jasperlake/include/soc/gpe.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h index b24b467939..7231682ac8 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio.h +++ b/src/soc/intel/jasperlake/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_GPIO_H_ #define _SOC_JASPERLAKE_GPIO_H_ diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h index c030561a2e..f563bfc30b 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_ #define _SOC_JASPERLAKE_GPIO_DEFS_H_ diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h index 4570fceac8..25aff18603 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_H_ #define _SOC_JASPERLAKE_GPIO_SOC_DEFS_H_ diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index ef166382ac..2d92fc9011 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_IOMAP_H_ #define _SOC_JASPERLAKE_IOMAP_H_ diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h index a6edd23d97..4aca1b7a5e 100644 --- a/src/soc/intel/jasperlake/include/soc/irq.h +++ b/src/soc/intel/jasperlake/include/soc/irq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JSL_IRQ_H_ #define _SOC_JSL_IRQ_H_ diff --git a/src/soc/intel/jasperlake/include/soc/itss.h b/src/soc/intel/jasperlake/include/soc/itss.h index 97430022f3..2065a2b83b 100644 --- a/src/soc/intel/jasperlake/include/soc/itss.h +++ b/src/soc/intel/jasperlake/include/soc/itss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_JSL_ITSS_H #define SOC_INTEL_JSL_ITSS_H diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h index 0fab6d582a..1ca89d211d 100644 --- a/src/soc/intel/jasperlake/include/soc/me.h +++ b/src/soc/intel/jasperlake/include/soc/me.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _JASPERLAKE_ME_H_ #define _JASPERLAKE_ME_H_ diff --git a/src/soc/intel/jasperlake/include/soc/meminit.h b/src/soc/intel/jasperlake/include/soc/meminit.h index 0e2a46c0e5..abcf899f21 100644 --- a/src/soc/intel/jasperlake/include/soc/meminit.h +++ b/src/soc/intel/jasperlake/include/soc/meminit.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_MEMINIT_H_ #define _SOC_JASPERLAKE_MEMINIT_H_ diff --git a/src/soc/intel/jasperlake/include/soc/msr.h b/src/soc/intel/jasperlake/include/soc/msr.h index 7925ea76b0..3bbf99d21b 100644 --- a/src/soc/intel/jasperlake/include/soc/msr.h +++ b/src/soc/intel/jasperlake/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/jasperlake/include/soc/nvs.h b/src/soc/intel/jasperlake/include/soc/nvs.h index cfb189d381..d059b00915 100644 --- a/src/soc/intel/jasperlake/include/soc/nvs.h +++ b/src/soc/intel/jasperlake/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ diff --git a/src/soc/intel/jasperlake/include/soc/p2sb.h b/src/soc/intel/jasperlake/include/soc/p2sb.h index 2fca70556c..ae72b9d650 100644 --- a/src/soc/intel/jasperlake/include/soc/p2sb.h +++ b/src/soc/intel/jasperlake/include/soc/p2sb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_P2SB_H_ #define _SOC_JASPERLAKE_P2SB_H_ diff --git a/src/soc/intel/jasperlake/include/soc/pch.h b/src/soc/intel/jasperlake/include/soc/pch.h index ccfc44942b..9d8df21fea 100644 --- a/src/soc/intel/jasperlake/include/soc/pch.h +++ b/src/soc/intel/jasperlake/include/soc/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_PCH_H_ #define _SOC_JASPERLAKE_PCH_H_ diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h index 139d1827f5..a3b938f118 100644 --- a/src/soc/intel/jasperlake/include/soc/pci_devs.h +++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_PCI_DEVS_H_ #define _SOC_JASPERLAKE_PCI_DEVS_H_ diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h index 32ff6ba78a..411a141ebf 100644 --- a/src/soc/intel/jasperlake/include/soc/pcr_ids.h +++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_JASPERLAKE_PCR_H #define SOC_JASPERLAKE_PCR_H diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index 5fb15940ca..f1da3a81f4 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 43c87de45f..06dcad2ca9 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_PMC_H_ #define _SOC_JASPERLAKE_PMC_H_ diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h index a8c8fdd7b2..1f79b33d93 100644 --- a/src/soc/intel/jasperlake/include/soc/ramstage.h +++ b/src/soc/intel/jasperlake/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h index 1672e8b5ca..4a4fbe63b8 100644 --- a/src/soc/intel/jasperlake/include/soc/romstage.h +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ diff --git a/src/soc/intel/jasperlake/include/soc/serialio.h b/src/soc/intel/jasperlake/include/soc/serialio.h index 509f0b0f14..cd6c8cb624 100644 --- a/src/soc/intel/jasperlake/include/soc/serialio.h +++ b/src/soc/intel/jasperlake/include/soc/serialio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h index fb19772e73..733389112a 100644 --- a/src/soc/intel/jasperlake/include/soc/smbus.h +++ b/src/soc/intel/jasperlake/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_SMBUS_H_ #define _SOC_JASPERLAKE_SMBUS_H_ diff --git a/src/soc/intel/jasperlake/include/soc/soc_chip.h b/src/soc/intel/jasperlake/include/soc/soc_chip.h index d4e9be6d04..d1b88016f5 100644 --- a/src/soc/intel/jasperlake/include/soc/soc_chip.h +++ b/src/soc/intel/jasperlake/include/soc/soc_chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_JASPERLAKE_SOC_CHIP_H_ #define _SOC_JASPERLAKE_SOC_CHIP_H_ diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index 67ce880988..0439979f58 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_JASPERLAKE_SYSTEMAGENT_H #define SOC_JASPERLAKE_SYSTEMAGENT_H diff --git a/src/soc/intel/jasperlake/include/soc/usb.h b/src/soc/intel/jasperlake/include/soc/usb.h index 33c0bf0bf9..4caa4022a3 100644 --- a/src/soc/intel/jasperlake/include/soc/usb.h +++ b/src/soc/intel/jasperlake/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_USB_H_ diff --git a/src/soc/intel/jasperlake/lockdown.c b/src/soc/intel/jasperlake/lockdown.c index 7ad5e4aa69..731d6c7c05 100644 --- a/src/soc/intel/jasperlake/lockdown.c +++ b/src/soc/intel/jasperlake/lockdown.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/meminit.c b/src/soc/intel/jasperlake/meminit.c index 88b39240bf..cca3082b2d 100644 --- a/src/soc/intel/jasperlake/meminit.c +++ b/src/soc/intel/jasperlake/meminit.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/p2sb.c b/src/soc/intel/jasperlake/p2sb.c index 328c4d3bab..38248a4acb 100644 --- a/src/soc/intel/jasperlake/p2sb.c +++ b/src/soc/intel/jasperlake/p2sb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index 4667f1d905..fdaec0db65 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 4134a2b7fc..afcbb71df2 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Helper functions for dealing with power management registers diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c index 431a70ccb0..8b9a7fa800 100644 --- a/src/soc/intel/jasperlake/reset.c +++ b/src/soc/intel/jasperlake/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index d263834576..a841809499 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/romstage/pch.c b/src/soc/intel/jasperlake/romstage/pch.c index a005ea0b99..d56a234aba 100644 --- a/src/soc/intel/jasperlake/romstage/pch.c +++ b/src/soc/intel/jasperlake/romstage/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index f78ea29ae1..fa9db6e29e 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/romstage/systemagent.c b/src/soc/intel/jasperlake/romstage/systemagent.c index 3cf61bd731..067a480ef2 100644 --- a/src/soc/intel/jasperlake/romstage/systemagent.c +++ b/src/soc/intel/jasperlake/romstage/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/sd.c b/src/soc/intel/jasperlake/sd.c index d97b63f498..db22494208 100644 --- a/src/soc/intel/jasperlake/sd.c +++ b/src/soc/intel/jasperlake/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 3f6cfd2d7f..72f83c8bf6 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index 44b464441d..be3abdf4e1 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 92777bfe5b..7be471a096 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c index 50849560ac..83866c347b 100644 --- a/src/soc/intel/jasperlake/uart.c +++ b/src/soc/intel/jasperlake/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 230e4f9df2f92e73c95919fcd9cb400d945dca21 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:47:14 +0200 Subject: [PATCH 0900/1463] soc/intel/quark: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3fdfa159194cccf15c0284700f554d2241dad6cd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40217 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/quark/acpi.c | 15 ++------------- src/soc/intel/quark/bootblock/bootblock.c | 15 ++------------- src/soc/intel/quark/chip.c | 15 ++------------- src/soc/intel/quark/chip.h | 15 ++------------- src/soc/intel/quark/ehci.c | 15 ++------------- src/soc/intel/quark/fsp_params.c | 15 ++------------- src/soc/intel/quark/gpio_i2c.c | 15 ++------------- src/soc/intel/quark/i2c.c | 15 ++------------- src/soc/intel/quark/include/soc/acpi.h | 15 ++------------- src/soc/intel/quark/include/soc/car.h | 15 ++------------- src/soc/intel/quark/include/soc/cpu.h | 15 ++------------- src/soc/intel/quark/include/soc/i2c.h | 15 ++------------- src/soc/intel/quark/include/soc/iomap.h | 15 ++------------- src/soc/intel/quark/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/quark/include/soc/pm.h | 15 ++------------- src/soc/intel/quark/include/soc/ramstage.h | 15 ++------------- src/soc/intel/quark/include/soc/reg_access.h | 15 ++------------- src/soc/intel/quark/include/soc/romstage.h | 15 ++------------- src/soc/intel/quark/include/soc/sd.h | 15 ++------------- src/soc/intel/quark/include/soc/spi.h | 16 ++-------------- src/soc/intel/quark/include/soc/storage_test.h | 15 ++------------- src/soc/intel/quark/lpc.c | 15 ++------------- src/soc/intel/quark/memmap.c | 15 ++------------- src/soc/intel/quark/northcluster.c | 15 ++------------- src/soc/intel/quark/reg_access.c | 15 ++------------- src/soc/intel/quark/reset.c | 15 ++------------- src/soc/intel/quark/romstage/car.c | 15 ++------------- src/soc/intel/quark/romstage/debug.c | 15 ++------------- src/soc/intel/quark/romstage/fsp_params.c | 15 ++------------- src/soc/intel/quark/romstage/mtrr.c | 15 ++------------- src/soc/intel/quark/romstage/pcie.c | 15 ++------------- src/soc/intel/quark/romstage/report_platform.c | 15 ++------------- src/soc/intel/quark/romstage/romstage.c | 15 ++------------- src/soc/intel/quark/sd.c | 15 ++------------- src/soc/intel/quark/spi.c | 16 ++-------------- src/soc/intel/quark/spi_debug.c | 16 ++-------------- src/soc/intel/quark/storage_test.c | 15 ++------------- src/soc/intel/quark/tsc_freq.c | 15 ++------------- src/soc/intel/quark/uart.c | 15 ++------------- src/soc/intel/quark/uart_common.c | 15 ++------------- 40 files changed, 80 insertions(+), 523 deletions(-) diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index da80eea166..ca4d2d6f65 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 5afcb96c52..657bc4a22c 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 677f6b9d7c..68930eb524 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 7e295b3f95..693c36fcde 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ diff --git a/src/soc/intel/quark/ehci.c b/src/soc/intel/quark/ehci.c index d7da9294e6..55ef0b5a8a 100644 --- a/src/soc/intel/quark/ehci.c +++ b/src/soc/intel/quark/ehci.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/fsp_params.c b/src/soc/intel/quark/fsp_params.c index d0cb19b770..9714e0e73f 100644 --- a/src/soc/intel/quark/fsp_params.c +++ b/src/soc/intel/quark/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/gpio_i2c.c b/src/soc/intel/quark/gpio_i2c.c index adb9c2f800..498dd96a2a 100644 --- a/src/soc/intel/quark/gpio_i2c.c +++ b/src/soc/intel/quark/gpio_i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 76a6178a3e..c83325cfb0 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/include/soc/acpi.h b/src/soc/intel/quark/include/soc/acpi.h index 39b71ba9b8..1b8dfa0b3d 100644 --- a/src/soc/intel/quark/include/soc/acpi.h +++ b/src/soc/intel/quark/include/soc/acpi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h index 0098486c9a..30f3c3372d 100644 --- a/src/soc/intel/quark/include/soc/car.h +++ b/src/soc/intel/quark/include/soc/car.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CAR_H_ #define _SOC_CAR_H_ diff --git a/src/soc/intel/quark/include/soc/cpu.h b/src/soc/intel/quark/include/soc/cpu.h index 34c089f3b1..91d6f122fd 100644 --- a/src/soc/intel/quark/include/soc/cpu.h +++ b/src/soc/intel/quark/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _QUARK_CPU_H_ #define _QUARK_CPU_H_ diff --git a/src/soc/intel/quark/include/soc/i2c.h b/src/soc/intel/quark/include/soc/i2c.h index 9f741d7711..bcdf833c5a 100644 --- a/src/soc/intel/quark/include/soc/i2c.h +++ b/src/soc/intel/quark/include/soc/i2c.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _QUARK_I2C_H_ #define _QUARK_I2C_H_ diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index dcebb1e59c..de2c1a5c8f 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _QUARK_IOMAP_H_ #define _QUARK_IOMAP_H_ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 2585debfbf..3d4b23027e 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 1a87dae444..2c0df5eaf4 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index e4aae035bb..243b82154d 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index aa55123046..8d95f22f34 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 6f5cbcca3e..1fa49c2cb3 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _QUARK_ROMSTAGE_H_ #define _QUARK_ROMSTAGE_H_ diff --git a/src/soc/intel/quark/include/soc/sd.h b/src/soc/intel/quark/include/soc/sd.h index 8f092d3efe..32f40092d4 100644 --- a/src/soc/intel/quark/include/soc/sd.h +++ b/src/soc/intel/quark/include/soc/sd.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _QUARK_SD_H_ #define _QUARK_SD_H_ diff --git a/src/soc/intel/quark/include/soc/spi.h b/src/soc/intel/quark/include/soc/spi.h index 1b5e70e385..d1030aa9d0 100644 --- a/src/soc/intel/quark/include/soc/spi.h +++ b/src/soc/intel/quark/include/soc/spi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SOC_SPI_H__ #define __SOC_SPI_H__ diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h index f9eb50c2da..61db77c77a 100644 --- a/src/soc/intel/quark/include/soc/storage_test.h +++ b/src/soc/intel/quark/include/soc/storage_test.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __STORAGE_TEST_H__ #define __STORAGE_TEST_H__ diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c index ad367c806a..96f47b4580 100644 --- a/src/soc/intel/quark/lpc.c +++ b/src/soc/intel/quark/lpc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index b2726d739e..0cde8ef6fa 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c index dda702e827..e0c0f68028 100644 --- a/src/soc/intel/quark/northcluster.c +++ b/src/soc/intel/quark/northcluster.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index ff37fe073d..3fe296503f 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #define __SIMPLE_DEVICE__ diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c index 2b8e99b1bc..af7ff30f7a 100644 --- a/src/soc/intel/quark/reset.c +++ b/src/soc/intel/quark/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c index 47e59e6174..22d9982a86 100644 --- a/src/soc/intel/quark/romstage/car.c +++ b/src/soc/intel/quark/romstage/car.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c index 94eeebe0d4..e56ba5e926 100644 --- a/src/soc/intel/quark/romstage/debug.c +++ b/src/soc/intel/quark/romstage/debug.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index ee6fbfd1a1..ed362ea740 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 484716c610..4c79427885 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c index 5644cc3793..38768379ab 100644 --- a/src/soc/intel/quark/romstage/pcie.c +++ b/src/soc/intel/quark/romstage/pcie.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c index abfbdcffe4..45b1e14afe 100644 --- a/src/soc/intel/quark/romstage/report_platform.c +++ b/src/soc/intel/quark/romstage/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 99df27c197..33c630bcd5 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/sd.c b/src/soc/intel/quark/sd.c index 5399e36e75..08e9ba0bcd 100644 --- a/src/soc/intel/quark/sd.c +++ b/src/soc/intel/quark/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/spi.c b/src/soc/intel/quark/spi.c index 9e12d2ad5e..b0c8f4265a 100644 --- a/src/soc/intel/quark/spi.c +++ b/src/soc/intel/quark/spi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/spi_debug.c b/src/soc/intel/quark/spi_debug.c index cadd9fb741..01e69753e5 100644 --- a/src/soc/intel/quark/spi_debug.c +++ b/src/soc/intel/quark/spi_debug.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index a2ec4cda08..c6c08bb5d9 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c index 4fb7c88bca..0d3e47e16f 100644 --- a/src/soc/intel/quark/tsc_freq.c +++ b/src/soc/intel/quark/tsc_freq.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c index d8db076978..48e106da61 100644 --- a/src/soc/intel/quark/uart.c +++ b/src/soc/intel/quark/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/quark/uart_common.c b/src/soc/intel/quark/uart_common.c index 4c0a953419..61fe34890c 100644 --- a/src/soc/intel/quark/uart_common.c +++ b/src/soc/intel/quark/uart_common.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include From 16f6aa81b6aeacc0b9a80a649eeaea96a192ffa2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 5 Apr 2020 15:47:21 +0200 Subject: [PATCH 0901/1463] soc/intel/tigerlake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I482715c166ccf5d2f3cc25118d25b07dbfd6650a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40219 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/tigerlake/acpi.c | 15 ++------------- src/soc/intel/tigerlake/acpi/gpio.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/gpio_op.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/ipu.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/ish.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/pch_glan.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/pch_hda.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/pcie.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/platform.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/pmc.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/scs.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/serialio.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/smbus.asl | 15 ++------------- src/soc/intel/tigerlake/acpi/xhci.asl | 15 ++------------- src/soc/intel/tigerlake/bootblock/bootblock.c | 15 ++------------- src/soc/intel/tigerlake/bootblock/cpu.c | 15 ++------------- src/soc/intel/tigerlake/bootblock/pch.c | 15 ++------------- .../intel/tigerlake/bootblock/report_platform.c | 15 ++------------- src/soc/intel/tigerlake/chip.c | 15 ++------------- src/soc/intel/tigerlake/chip.h | 15 ++------------- src/soc/intel/tigerlake/cpu.c | 15 ++------------- src/soc/intel/tigerlake/elog.c | 15 ++------------- src/soc/intel/tigerlake/espi.c | 15 ++------------- src/soc/intel/tigerlake/finalize.c | 15 ++------------- src/soc/intel/tigerlake/fsp_params.c | 15 ++------------- src/soc/intel/tigerlake/i2c.c | 15 ++------------- src/soc/intel/tigerlake/include/soc/bootblock.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/cpu.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/espi.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/gpe.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/gpio.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/gpio_defs.h | 15 ++------------- .../intel/tigerlake/include/soc/gpio_soc_defs.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/iomap.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/irq.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/itss.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/me.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/msr.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/nvs.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/p2sb.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/pch.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/pci_devs.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/pcr_ids.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/pm.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/pmc.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/ramstage.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/romstage.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/serialio.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/smbus.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/soc_chip.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/systemagent.h | 15 ++------------- src/soc/intel/tigerlake/include/soc/usb.h | 15 ++------------- src/soc/intel/tigerlake/lockdown.c | 15 ++------------- src/soc/intel/tigerlake/p2sb.c | 15 ++------------- src/soc/intel/tigerlake/pmc.c | 15 ++------------- src/soc/intel/tigerlake/pmutil.c | 15 ++------------- src/soc/intel/tigerlake/reset.c | 15 ++------------- src/soc/intel/tigerlake/romstage/fsp_params.c | 15 ++------------- src/soc/intel/tigerlake/romstage/pch.c | 15 ++------------- src/soc/intel/tigerlake/romstage/romstage.c | 15 ++------------- src/soc/intel/tigerlake/romstage/systemagent.c | 15 ++------------- src/soc/intel/tigerlake/sd.c | 15 ++------------- src/soc/intel/tigerlake/smihandler.c | 15 ++------------- src/soc/intel/tigerlake/smmrelocate.c | 15 ++------------- src/soc/intel/tigerlake/systemagent.c | 15 ++------------- src/soc/intel/tigerlake/uart.c | 15 ++------------- 66 files changed, 132 insertions(+), 858 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 23fd970500..29a46195cd 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index 9bf0c6032f..2b4aff09c0 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include #include diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl index 4444c09a5b..be346ae7e3 100644 --- a/src/soc/intel/tigerlake/acpi/gpio_op.asl +++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Get GPIO Value diff --git a/src/soc/intel/tigerlake/acpi/ipu.asl b/src/soc/intel/tigerlake/acpi/ipu.asl index 5711644bcb..337782d2cc 100644 --- a/src/soc/intel/tigerlake/acpi/ipu.asl +++ b/src/soc/intel/tigerlake/acpi/ipu.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ Scope (\_SB.PCI0) { diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl index ee3f1a3fdf..bdd3cc74a9 100644 --- a/src/soc/intel/tigerlake/acpi/ish.asl +++ b/src/soc/intel/tigerlake/acpi/ish.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Integrated Sensor Hub Controller 0:12.0 */ diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/tigerlake/acpi/pch_glan.asl index 2d9d960565..174f993ec2 100644 --- a/src/soc/intel/tigerlake/acpi/pch_glan.asl +++ b/src/soc/intel/tigerlake/acpi/pch_glan.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Gigabit Ethernet Controller 0:1f.6 */ diff --git a/src/soc/intel/tigerlake/acpi/pch_hda.asl b/src/soc/intel/tigerlake/acpi/pch_hda.asl index 0d10d2deb5..78ae2c2b5b 100644 --- a/src/soc/intel/tigerlake/acpi/pch_hda.asl +++ b/src/soc/intel/tigerlake/acpi/pch_hda.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Audio Controller - Device 31, Function 3 */ diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index 53ae316413..ce9ce7db5c 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel PCH PCIe support */ diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl index 682a7b93d8..a579b97844 100644 --- a/src/soc/intel/tigerlake/acpi/platform.asl +++ b/src/soc/intel/tigerlake/acpi/platform.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Enable ACPI _SWS methods */ #include diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl index 6dd2d35354..2f7fa46d73 100644 --- a/src/soc/intel/tigerlake/acpi/pmc.asl +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl index 83da7e0f06..a2d9414ff0 100644 --- a/src/soc/intel/tigerlake/acpi/scs.asl +++ b/src/soc/intel/tigerlake/acpi/scs.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl index 6fd135b437..f7506bb5e4 100644 --- a/src/soc/intel/tigerlake/acpi/serialio.asl +++ b/src/soc/intel/tigerlake/acpi/serialio.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel Serial IO Devices */ diff --git a/src/soc/intel/tigerlake/acpi/smbus.asl b/src/soc/intel/tigerlake/acpi/smbus.asl index f273e3669d..c0d092ae67 100644 --- a/src/soc/intel/tigerlake/acpi/smbus.asl +++ b/src/soc/intel/tigerlake/acpi/smbus.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Intel SMBus Controller 0:1f.4 */ diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl index b97f52052b..f0b28ce1c2 100644 --- a/src/soc/intel/tigerlake/acpi/xhci.asl +++ b/src/soc/intel/tigerlake/acpi/xhci.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index 1abca127a3..6bf1e131d6 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/bootblock/cpu.c b/src/soc/intel/tigerlake/bootblock/cpu.c index dddf24352d..087c1649cd 100644 --- a/src/soc/intel/tigerlake/bootblock/cpu.c +++ b/src/soc/intel/tigerlake/bootblock/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 94b70721df..a3f38c27a8 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 59091c112f..99c695d419 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Platform Stepping and IDs diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 231623ca8d..f57f51dc7d 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 64c13ce22e..e105061872 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index dfbcd22b94..d33194e4c9 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor CPU Datasheet diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 903259497d..2aceea02ac 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 0d8f3af956..df43d96ba7 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index b636ccbec0..414874ad82 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 8e9787b12b..ff6d3a978a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/i2c.c b/src/soc/intel/tigerlake/i2c.c index 46bc726726..10886b9643 100644 --- a/src/soc/intel/tigerlake/i2c.c +++ b/src/soc/intel/tigerlake/i2c.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h index 0c8d8c201a..66836cb93b 100644 --- a/src/soc/intel/tigerlake/include/soc/bootblock.h +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_BOOTBLOCK_H_ #define _SOC_TIGERLAKE_BOOTBLOCK_H_ diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 799382498b..0d8e17f49b 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_CPU_H_ #define _SOC_TIGERLAKE_CPU_H_ diff --git a/src/soc/intel/tigerlake/include/soc/espi.h b/src/soc/intel/tigerlake/include/soc/espi.h index d323f044f7..fe94748dee 100644 --- a/src/soc/intel/tigerlake/include/soc/espi.h +++ b/src/soc/intel/tigerlake/include/soc/espi.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/include/soc/gpe.h b/src/soc/intel/tigerlake/include/soc/gpe.h index c37750b1c4..cae23a0725 100644 --- a/src/soc/intel/tigerlake/include/soc/gpe.h +++ b/src/soc/intel/tigerlake/include/soc/gpe.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index 1793a3f6fe..ccf6663865 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_GPIO_H_ #define _SOC_TIGERLAKE_GPIO_H_ diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index c02da0a4b6..baa6c00ff4 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_DEFS_H_ diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index a505c73287..bb2188af38 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ /* diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 554067f28f..4514c99283 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Firmware Architecture Specification diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 818cd31be6..01ee10b4f4 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ diff --git a/src/soc/intel/tigerlake/include/soc/itss.h b/src/soc/intel/tigerlake/include/soc/itss.h index 39794ead73..13a22e40d8 100644 --- a/src/soc/intel/tigerlake/include/soc/itss.h +++ b/src/soc/intel/tigerlake/include/soc/itss.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SOC_INTEL_TGL_ITSS_H #define SOC_INTEL_TGL_ITSS_H diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index 94331b4c9e..b102b45a9b 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _TIGERLAKE_ME_H_ #define _TIGERLAKE_ME_H_ diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h index 7925ea76b0..3bbf99d21b 100644 --- a/src/soc/intel/tigerlake/include/soc/msr.h +++ b/src/soc/intel/tigerlake/include/soc/msr.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/tigerlake/include/soc/nvs.h b/src/soc/intel/tigerlake/include/soc/nvs.h index cfb189d381..d059b00915 100644 --- a/src/soc/intel/tigerlake/include/soc/nvs.h +++ b/src/soc/intel/tigerlake/include/soc/nvs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ diff --git a/src/soc/intel/tigerlake/include/soc/p2sb.h b/src/soc/intel/tigerlake/include/soc/p2sb.h index d483ee399b..eb45b6ad1e 100644 --- a/src/soc/intel/tigerlake/include/soc/p2sb.h +++ b/src/soc/intel/tigerlake/include/soc/p2sb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h index fc4cd78646..d24e98b784 100644 --- a/src/soc/intel/tigerlake/include/soc/pch.h +++ b/src/soc/intel/tigerlake/include/soc/pch.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_PCH_H_ #define _SOC_TIGERLAKE_PCH_H_ diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 255081077a..f9d89082c0 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_PCI_DEVS_H_ #define _SOC_TIGERLAKE_PCI_DEVS_H_ diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index 4143892f87..1d54805cb1 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index 14fa5d0c08..3004b4a732 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 0c1c7a21e4..88c6f61d94 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_PMC_H_ #define _SOC_TIGERLAKE_PMC_H_ diff --git a/src/soc/intel/tigerlake/include/soc/ramstage.h b/src/soc/intel/tigerlake/include/soc/ramstage.h index a8c8fdd7b2..1f79b33d93 100644 --- a/src/soc/intel/tigerlake/include/soc/ramstage.h +++ b/src/soc/intel/tigerlake/include/soc/ramstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index 1672e8b5ca..4a4fbe63b8 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ diff --git a/src/soc/intel/tigerlake/include/soc/serialio.h b/src/soc/intel/tigerlake/include/soc/serialio.h index 509f0b0f14..cd6c8cb624 100644 --- a/src/soc/intel/tigerlake/include/soc/serialio.h +++ b/src/soc/intel/tigerlake/include/soc/serialio.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h index 3fb8291698..97b82562e6 100644 --- a/src/soc/intel/tigerlake/include/soc/smbus.h +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/include/soc/soc_chip.h b/src/soc/intel/tigerlake/include/soc/soc_chip.h index 250aa9a0aa..528c25f501 100644 --- a/src/soc/intel/tigerlake/include/soc/soc_chip.h +++ b/src/soc/intel/tigerlake/include/soc/soc_chip.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_TIGERLAKE_SOC_CHIP_H_ #define _SOC_TIGERLAKE_SOC_CHIP_H_ diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index d8c8ad47da..8cb59f8cb4 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor SA Datasheet diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 33c0bf0bf9..4caa4022a3 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _SOC_USB_H_ diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c index 18d4fa728e..0babe8889d 100644 --- a/src/soc/intel/tigerlake/lockdown.c +++ b/src/soc/intel/tigerlake/lockdown.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/p2sb.c b/src/soc/intel/tigerlake/p2sb.c index 64f181f634..3c53519bbc 100644 --- a/src/soc/intel/tigerlake/p2sb.c +++ b/src/soc/intel/tigerlake/p2sb.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 13902b80a6..39644995bb 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index ac254020cb..4482b1ec55 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Helper functions for dealing with power management registers diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c index 431a70ccb0..8b9a7fa800 100644 --- a/src/soc/intel/tigerlake/reset.c +++ b/src/soc/intel/tigerlake/reset.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 32f1b031a9..993320054a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c index a005ea0b99..d56a234aba 100644 --- a/src/soc/intel/tigerlake/romstage/pch.c +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index f78ea29ae1..fa9db6e29e 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c index 9fa498e802..b6850104ac 100644 --- a/src/soc/intel/tigerlake/romstage/systemagent.c +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor SA Datasheet diff --git a/src/soc/intel/tigerlake/sd.c b/src/soc/intel/tigerlake/sd.c index 9898734f3d..857f175f98 100644 --- a/src/soc/intel/tigerlake/sd.c +++ b/src/soc/intel/tigerlake/sd.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 67e59a26a0..59553790e9 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 44b464441d..be3abdf4e1 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index fb0ce118aa..8859386a59 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor SA Datasheet diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c index 03b4469a98..85311c00cf 100644 --- a/src/soc/intel/tigerlake/uart.c +++ b/src/soc/intel/tigerlake/uart.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet From 1b7fc32a54ea962a30da8daee5827003087843ec Mon Sep 17 00:00:00 2001 From: Tommie Date: Tue, 31 Mar 2020 16:24:35 +0800 Subject: [PATCH 0902/1463] mb/google/octopus/variants/phaser: Disable xHCI compliance mode Since the first LFPS timeout causes xHCI to enter compliance mode, the SS hub cannot be enumerated. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:149723583 TEST=Verified USB operation successfully. Signed-off-by: tong.lin Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39968 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Marco Chen --- src/mainboard/google/octopus/variants/phaser/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index 625c2a6a34..b80d0317c8 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -173,4 +173,7 @@ chip soc/intel/apollolake end end # - I2C 7 end + + # Disable xHCI compliance mode + register "DisableComplianceMode" = "1" end From 540af0960217a1d25600d6ef5f0048f4a9b391fd Mon Sep 17 00:00:00 2001 From: Marco Chen Date: Thu, 26 Mar 2020 22:23:17 +0800 Subject: [PATCH 0903/1463] soc/intel/tigerlake: Allow mainboard to override DRAM part number In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on volteer / dedede. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:152019429 Change-Id: If940a76d36a7645a7441ba418aa7aec9af9f6319 Signed-off-by: Marco Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/39860 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- .../intel/tigerlake/include/soc/romstage.h | 2 ++ src/soc/intel/tigerlake/romstage/romstage.c | 25 +++++++++++++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index 4a4fbe63b8..e3c7969127 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -6,6 +6,8 @@ #include +/* Provide a callback to allow mainboard to override the DRAM part number. */ +bool mainboard_get_dram_part_num(const char **part_num, size_t *len); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void pch_init(void); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index fa9db6e29e..dc5dcf1a9b 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -22,6 +22,12 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + /* Default weak implementation, no need to override part number. */ + return false; +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -36,6 +42,9 @@ static void save_dimm_info(void) const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len; + bool is_dram_part_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ meminfo_hob = fsp_find_extension_hob_by_guid( @@ -57,6 +66,10 @@ static void save_dimm_info(void) } memset(mem_info, 0, sizeof(*mem_info)); + /* Allow mainboard to override DRAM part number. */ + is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, + &dram_part_num_len); + /* Save available DIMM information */ index = 0; dimm_max = ARRAY_SIZE(mem_info->dimm); @@ -75,6 +88,14 @@ static void save_dimm_info(void) if (src_dimm->Status != DIMM_PRESENT) continue; + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!is_dram_part_overridden) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + u8 memProfNum = meminfo_hob->MemoryProfile; serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; @@ -87,8 +108,8 @@ static void save_dimm_info(void) src_dimm->RankInDimm, channel_info->ChannelId, src_dimm->DimmId, - (const char *)src_dimm->ModulePartNum, - sizeof(src_dimm->ModulePartNum), + dram_part_num, + dram_part_num_len, serial_num, meminfo_hob->DataWidth, meminfo_hob->VddVoltage[memProfNum], From 2f399b7d5bcfc28a808e61cf203900cfbdacf2b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 2 Apr 2020 19:51:37 +0200 Subject: [PATCH 0904/1463] nb/amd/pi/00730F01/northbridge.c: refactor IVRS generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use defined structures to assemble IVRS and IVHD entries. Additionally assemble IVHD type 11h which supersedes IVHD type 10h. In order to utilize all IOMMU features firmware should also expose IVHD type 11h. The new type is already supported and parsed since Xen 1.13. IVHD type 10h should still be present for backwards compatibility. TEST=boot PC Engines apu2 and disassemble IVRS using newest IASL, boot Xen 1.13 or newer with debug enabled and see IVRS IVHD 11h parsed in xl dmesg Signed-off-by: Michał Żygowski Change-Id: I9a2c24b67adfa8ebd718caeb5eec88687dcbcc9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40042 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/northbridge/amd/pi/00730F01/northbridge.c | 380 +++++++++++------- 1 file changed, 234 insertions(+), 146 deletions(-) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index d324689955..4a24d3550a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include +#include #include #include #include @@ -11,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +25,7 @@ #include #include #include +#include #define MAX_NODE_NUMS MAX_NODES #define PCIE_CAP_AER BIT(5) @@ -428,59 +432,139 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void add_ivhd_dev_entry(struct device *parent, struct device *dev, - unsigned long *current, uint16_t *length, - uint8_t type, uint8_t data) +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { - uint8_t *p; - p = (uint8_t *) *current; + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + current = ALIGN_UP(current, 8); + ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; - if (type == 0x2) { - /* Entry type */ - p[0] = type; - /* Device */ - p[1] = dev->path.pci.devfn; - /* Bus */ - p[2] = dev->bus->secondary; - /* Data */ - p[3] = data; - /* [4:7] Padding */ - p[4] = 0x0; - p[5] = 0x0; - p[6] = 0x0; - p[7] = 0x0; - *length += 8; - *current += 8; - } else if (type == 0x42) { - /* Entry type */ - p[0] = type; - /* Device */ - p[1] = dev->path.pci.devfn; - /* Bus */ - p[2] = dev->bus->secondary; - /* Data */ - p[3] = 0x0; - /* Reserved */ - p[4] = 0x0; - /* Device */ - p[5] = parent->path.pci.devfn; - /* Bus */ - p[6] = parent->bus->secondary; - /* Reserved */ - p[7] = 0x0; - *length += 8; - *current += 8; + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | + IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | + IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; + ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + ivhd_ioapic = (ivrs_ivhd_special_t *)current; + + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = 0x00; + ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_describe_hpet(unsigned long current) +{ + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + current = ALIGN_UP(current, 8); + ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; + + ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_hpet->reserved = 0x0000; + ivhd_hpet->dte_setting = 0x00; + ivhd_hpet->handle = 0x00; + ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, + uint16_t end_devid, uint8_t setting) +{ + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + current = ALIGN_UP(current, 4); + ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; + + /* Create the start range IVHD entry */ + ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; + ivhd_range->dev_id = start_devid; + ivhd_range->dte_setting = setting; + current += sizeof(ivrs_ivhd_generic_t); + + /* Create the end range IVHD entry */ + ivhd_range = (ivrs_ivhd_generic_t *)current; + ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; + ivhd_range->dev_id = end_devid; + ivhd_range->dte_setting = setting; + current += sizeof(ivrs_ivhd_generic_t); + + return current; +} + +static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, + unsigned long *current, uint8_t type, uint8_t data) +{ + if (type == IVHD_DEV_4_BYTE_SELECT) { + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + *current = ALIGN_UP(*current, 4); + ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + *current += sizeof(ivrs_ivhd_generic_t); + } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + *current = ALIGN_UP(*current, 8); + ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + ivhd_entry->reserved1 = 0; + ivhd_entry->reserved2 = 0; + ivhd_entry->source_dev_id = parent->path.pci.devfn | + (parent->bus->secondary << 8); + *current += sizeof(ivrs_ivhd_alias_t); + } + + return *current; +} + +static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, + unsigned long *current, uint16_t *ivhd_length) +{ + unsigned int header_type, is_pcie; + unsigned long current_backup; + + header_type = dev->hdr_type & 0x7f; + is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + if (((header_type == PCI_HEADER_TYPE_NORMAL) || + (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { + /* Device or Bridge is PCIe */ + current_backup = *current; + add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); + *ivhd_length += (*current - current_backup); + } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { + /* Device is legacy PCI or PCI-X */ + current_backup = *current; + add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); + *ivhd_length += (*current - current_backup); } } -static void add_ivrs_device_entries(struct device *parent, struct device *dev, +static void add_ivhd_device_entries(struct device *parent, struct device *dev, unsigned int depth, int linknum, int8_t *root_level, - unsigned long *current, uint16_t *length) + unsigned long *current, uint16_t *ivhd_length) { struct device *sibling; struct bus *link; - unsigned int header_type; - unsigned int is_pcie; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } if (dev->path.type == DEVICE_PATH_PCI) { @@ -489,154 +573,158 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, *root_level = depth; if ((*root_level != -1) && (dev->enabled)) { - if (depth == *root_level) { - if (dev->path.pci.devfn == (0x14 << 3)) { - /* SMBUS controller */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x97); - } else if (dev->path.pci.devfn != 0x2 && - dev->path.pci.devfn < (0x2 << 3)) { - /* FCH control device */ - } else { - /* Other devices */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); - } - } else { - header_type = dev->hdr_type & 0x7f; - is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (((header_type == PCI_HEADER_TYPE_NORMAL) || - (header_type == PCI_HEADER_TYPE_BRIDGE)) - && is_pcie) { - /* Device or Bridge is PCIe */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); - } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && - !is_pcie) { - add_ivhd_dev_entry(parent, dev, current, length, 0x42, 0x0); - /* Device is legacy PCI or PCI-X */ - } - } + if (depth != *root_level) + ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); } } for (link = dev->link_list; link; link = link->next) for (sibling = link->children; sibling; sibling = sibling->sibling) - add_ivrs_device_entries(dev, sibling, depth + 1, depth, - root_level, current, length); + add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, + current, ivhd_length); + + free(root_level); } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) +#define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) +#define EFR_SUPPORT BIT(27) + +static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) { - uint8_t *p; + acpi_ivrs_ivhd11_t *ivhd_11; + unsigned long current_backup; - uint32_t apicid_sb800; - uint32_t apicid_northbridge; + /* + * These devices should be already found by previous function. + * Do not perform NULL checks. + */ + struct device *nb_dev = pcidev_on_root(0, 0); + struct device *iommu_dev = pcidev_on_root(0, 2); - apicid_sb800 = CONFIG_MAX_CPUS; - apicid_northbridge = CONFIG_MAX_CPUS + 1; + /* + * In order to utilize all features, firmware should expose type 11h + * IVHD which supersedes the type 10h. + */ + memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); + ivhd_11 = (acpi_ivrs_ivhd11_t *)current; - /* Describe NB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0x0; /* Data */ - p[4] = apicid_northbridge; /* IOAPIC ID */ - p[5] = 0x0; /* Device 0 Function 0 */ - p[6] = 0x0; /* Northbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; + /* Enable EFR */ + ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; + /* For type 11h bits 6 and 7 are reserved */ + ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; + ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); + /* BDF :00.2 */ + ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + /* PCI Capability block 0x40 (type 0xf, "Secure device") */ + ivhd_11->capability_offset = 0x40; + ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; + ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; + ivhd_11->pci_segment_group = 0x0000; + ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; + ivhd_11->iommu_attributes.perf_counters = + (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; + ivhd_11->iommu_attributes.perf_counter_banks = + (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; + ivhd_11->iommu_attributes.msi_num_ppr = + (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; - /* Describe SB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = apicid_sb800; /* IOAPIC ID */ - p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ - p[6] = 0x0; /* Southbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; + if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { + ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); + ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); + } + + current += sizeof(acpi_ivrs_ivhd11_t); + + /* Now repeat all the device entries from type 10h */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivhd_11->length += (current - current_backup); + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); + + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivhd_11->length += (current - current_backup); + + /* Describe IOAPICs */ + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); + ivhd_11->length += (current - current_backup); return current; } static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) { - uint8_t *p; acpi_ivrs_t *ivrs_agesa; + unsigned long current_backup; - struct device *nb_dev = pcidev_on_root(0x0, 0); + struct device *nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { - printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); return (unsigned long)ivrs; } + struct device *iommu_dev = pcidev_on_root(0, 2); + + if (!iommu_dev) { + printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); + + return (unsigned long)ivrs; + } - /* obtain IOMMU base address */ ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); if (ivrs_agesa != NULL) { - ivrs->iv_info = 0x0; - /* Maximum supported virtual address size */ - ivrs->iv_info |= (0x40 << 15); - /* Maximum supported physical address size */ - ivrs->iv_info |= (0x30 << 8); - /* Guest virtual address width */ - ivrs->iv_info |= (0x2 << 5); - - ivrs->ivhd.type = 0x10; - ivrs->ivhd.flags = 0x0e; - /* Enable ATS support */ - ivrs->ivhd.flags |= 0x10; + ivrs->iv_info = ivrs_agesa->iv_info; + ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; + ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); /* BDF :00.2 */ - ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); - /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); + /* PCI Capability block 0x40 (type 0xf, "Secure device") */ ivrs->ivhd.capability_offset = 0x40; ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; - ivrs->ivhd.pci_segment_group = 0x0; - ivrs->ivhd.iommu_info = 0x0; - ivrs->ivhd.iommu_info |= (0x13 << 8); - /* use only performance counters related bits: - * PNCounters[16:13] and - * PNBanks[22:17], - * otherwise 0 */ - ivrs->ivhd.iommu_feature_info = - ivrs_agesa->ivhd.iommu_feature_info & 0x7fe000; + ivrs->ivhd.pci_segment_group = 0x0000; + ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; + ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; + /* Enable EFR if supported */ + if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) + ivrs->iv_info |= IVINFO_EFR_SUPPORTED; } else { printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); return (unsigned long)ivrs; } - /* Describe HPET */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = 0x0; /* HPET number */ - p[5] = 0x14 << 3; /* HPET device */ - p[6] = nb_dev->bus->secondary; /* HPET bus */ - p[7] = 0x2; /* Variety */ - ivrs->ivhd.length += 8; - current += 8; + /* + * Add all possible PCI devices on bus 0 that can generate transactions + * processed by IOMMU. Start with device 00:01.0 since IOMMU does not + * translate transactions generated by itself. + */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivrs->ivhd.length += (current - current_backup); + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); - /* Describe PCI devices */ - int8_t root_level = -1; - add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, ¤t, - &ivrs->ivhd.length); + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivrs->ivhd.length += (current - current_backup); /* Describe IOAPICs */ - unsigned long prev_current = current; - current = acpi_fill_ivrs_ioapic(ivrs, current); - ivrs->ivhd.length += (current - prev_current); + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); + ivrs->ivhd.length += (current - current_backup); - return current; + /* If EFR is not supported, IVHD type 11h is reserved */ + if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) + return current; + + return acpi_fill_ivrs11(current, ivrs_agesa); } static void northbridge_fill_ssdt_generator(struct device *device) From 7b288012230cdcd381d6e406ebbe2cb9f334f635 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 20 Mar 2020 15:41:44 +0100 Subject: [PATCH 0905/1463] drivers/pc80/tpm/tis.c: change the _HID and _CID for TPM2 device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According TCG PC Client Platform Firmware Profile Specification Revision 1.04 Chapter 8.1 the TPM device object should have the _CID and _HID values set to MSFT0101 for TPM2. FreeBSD also detects TPM2 device using MSFT0101 _HID and _CID only. TEST=boot FreeBSD 12.1 on PC Engines apu2 and check in dmesg that TPM2.0 is detected Signed-off-by: Michał Żygowski Change-Id: I45123f272038e664b834cabd9d8525baca0eb583 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39699 Reviewed-by: Patrick Rudolph Reviewed-by: Philipp Deppenwiese Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/pc80/tpm/tis.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 98d31c0a82..1081410011 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -886,11 +886,16 @@ static void lpc_tpm_fill_ssdt(struct device *dev) acpigen_write_scope(path); acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0C31"); + if (CONFIG(TPM2)) { + acpigen_write_name_string("_HID", "MSFT0101"); + acpigen_write_name_string("_CID", "MSFT0101"); + } else { + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0C31"); - acpigen_write_name("_CID"); - acpigen_emit_eisaid("PNP0C31"); + acpigen_write_name("_CID"); + acpigen_emit_eisaid("PNP0C31"); + } acpi_device_write_uid(dev); From ecaa2d4741696ab0228500fd170e58ee4d268353 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 6 Apr 2020 15:20:47 +0530 Subject: [PATCH 0906/1463] soc/intel/tigerlake/acpi: Fix typo in HDA in comment HSA -> HDA (High Definition Audio) Change-Id: Ic0e6ad7b26105fdd6eca6cd11edcf2236e5c7123 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/40232 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/soc/intel/tigerlake/acpi/pci_irqs.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 7f632ba32e..62520b1f48 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -16,7 +16,7 @@ #include Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ + /* D31:HDA, SMBUS, TraceHUB */ Package(){0x001FFFFF, 3, 0, HDA_IRQ }, Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, @@ -89,7 +89,7 @@ Name (PICP, Package () { }) Name (PICN, Package () { - /* D31:HSA, SMBUS, TraceHUB*/ + /* D31:HDA, SMBUS, TraceHUB*/ Package () { 0x001FFFFF, 3, 0, 11 }, Package () { 0x001FFFFF, 4, 0, 11 }, Package () { 0x001FFFFF, 7, 0, 11 }, From 66579d4e362bb640a9c9e2d960d72c6c37ff67cc Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 6 Apr 2020 10:45:25 +0200 Subject: [PATCH 0907/1463] sb/intel/bd82x6x/sata: Don't hard-code values The interrupt line registers are configured in a central place, pch_pirq_init() in `lpc.c`, according to the PIRQ configuration. Hardcoding values here makes no sense. Change-Id: Ide5f101b2e5bda84f3c2ff8c8ca636b8233bb948 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/40229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- src/southbridge/intel/bd82x6x/pch.h | 1 - src/southbridge/intel/bd82x6x/sata.c | 8 -------- 2 files changed, 9 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 18383f6bff..0a236c6b7e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -167,7 +167,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) -#define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) #define IDE_SITRE (1 << 14) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index e04f3bacc9..310d1a291d 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -58,10 +58,6 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); - /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | @@ -131,10 +127,6 @@ static void sata_init(struct device *dev) */ pci_write_config8(dev, 0x09, 0x8f); - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0xff); - /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | From 192666f352633466158af1974ecb617395705959 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 6 Apr 2020 10:54:42 +0200 Subject: [PATCH 0908/1463] sb/intel/bd82x6x: Drop PCI resource reg override Assignment of PCI resource registers is up to the allocator. Therefore, drop override of the PCI resource register. Change-Id: I184a263c81aa8a434fcd153406b73058914cb2f9 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/40230 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/bd82x6x/sata.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 310d1a291d..2693e2b63a 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -114,10 +114,7 @@ static void sata_init(struct device *dev) /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - - /* And without AHCI BAR no memory decoding */ + /* Without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); From 7daf3cd32e259889c0cb419b4440422649d82266 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 6 Apr 2020 11:01:28 +0200 Subject: [PATCH 0909/1463] sb/intel/bd82x6x/sata: Set values as described in BIOS spec Set some things missed originally because of formatting issues in the BIOS spec. Values were compared with a vendor dump. Change-Id: I27360d6ea5d1f00b1ed350f47ff40a22f19dfb05 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/40231 Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/sata.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 2693e2b63a..c1b61f24c6 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -186,6 +186,11 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); + + pci_update_config32(dev, 0x98, + ~(1 << 16 | 0x3f << 7 | 3 << 5 | 3 << 3), + 1 << 24 | 1 << 22 | 1 << 20 | 1 << 19 | + 1 << 18 | 1 << 14 | 0x04 << 7 | 1 << 3); } static void sata_enable(struct device *dev) From 869ac71483616cd363170cdf2cf5d4ce1965a2a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sat, 4 Apr 2020 08:49:21 +0000 Subject: [PATCH 0910/1463] Revert "mb/pcengines/apu2: add reset logic for PCIe slots" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit c04871a398ca945b42fde0867572094c38f6f92c. Reason for revert: Many apu2 users reported issues with PCIe modules detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught by 3mdeb validation stands and hardware configuration. Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu2/BiosCallOuts.c | 71 --------------------- src/mainboard/pcengines/apu2/OemCustomize.c | 20 ++---- src/mainboard/pcengines/apu2/romstage.c | 9 --- 3 files changed, 5 insertions(+), 95 deletions(-) diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index d61402b4ac..7af4e67542 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */ #include -#include #include #include #include @@ -14,7 +13,6 @@ #include "hudson.h" static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPciExSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -23,7 +21,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPciExSlotReset }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; @@ -131,71 +128,3 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_SUCCESS; } - -/* PCIE slot reset control */ -static AGESA_STATUS board_GnbPciExSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - PCIe_SLOT_RESET_INFO *ResetInfo; - uint32_t GpioData; - uint8_t GpioValue; - - ResetInfo = ConfigPtr; - Status = AGESA_UNSUPPORTED; - - switch (ResetInfo->ResetId) { - /* - * ResetID 1 = PCIE_RST# affects all PCIe slots on all boards except - * apu2. ResetID 1 does not need any GPIO. - */ - case 1: - Status = AGESA_SUCCESS; - break; - case 51: /* GPIO51 resets mPCIe1 slot on apu2 */ - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - GpioData = gpio1_read32(0x8); - printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n", - __func__, ResetInfo->ResetId, GpioData); - GpioValue = gpio1_read8(0xa); - GpioValue &= ~BIT6; - gpio1_write8(0xa, GpioValue); - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - GpioData = gpio1_read32(0x8); - printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n", - __func__, ResetInfo->ResetId, GpioData); - GpioValue = gpio1_read8(0xa); - GpioValue |= BIT6; - gpio1_write8(0xa, GpioValue); - Status = AGESA_SUCCESS; - break; - } - break; - case 55: /* GPIO51 resets mPCIe2 slot on apu2 */ - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - GpioData = gpio1_read32(0xc); - printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n", - __func__, ResetInfo->ResetId, GpioData); - GpioValue = gpio1_read8(0xe); - GpioValue &= ~BIT6; - gpio1_write8(0xa, GpioValue); - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - GpioData = gpio1_read32(0xc); - printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n", - __func__, ResetInfo->ResetId, GpioData); - GpioValue = gpio1_read8(0xe); - GpioValue |= BIT6; - gpio1_write8(0xa, GpioValue); - Status = AGESA_SUCCESS; - break; - } - break; - } - - return Status; -} diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 78ff99459c..7d943c8bdf 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -4,16 +4,6 @@ #include #include -#define PCIE_NIC_RESET_ID 1 - -#if CONFIG(BOARD_PCENGINES_APU2) -#define PCIE_GFX_RESET_ID 55 -#define PCIE_PORT3_RESET_ID 51 -#else -#define PCIE_GFX_RESET_ID PCIE_NIC_RESET_ID -#define PCIE_PORT3_RESET_ID PCIE_NIC_RESET_ID -#endif - static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -23,7 +13,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_PORT3_RESET_ID, + 0x01, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ @@ -35,7 +25,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x02, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ @@ -47,7 +37,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x03, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ @@ -59,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x04, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ @@ -71,7 +61,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_GFX_RESET_ID, + 0x05, 0) } }; diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 6ba5712bd6..e40d95df16 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -27,15 +27,6 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Release GPIO32/33 for other uses. */ pm_write8(0xea, 1); - - /* - * Assert resets on the PCIe slots, since AGESA calls deassert callout - * only. Only apu2 uses GPIOs to reset PCIe slots. - */ - if (CONFIG(BOARD_PCENGINES_APU2)) { - gpio1_write8(0xa, gpio1_read8(0xa) & ~(1 << 6)); - gpio1_write8(0xe, gpio1_read8(0xe) & ~(1 << 6)); - } } static void early_lpc_init(void) From b98c89626e46170b7136d8da7e072bde44fbe77d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 6 Apr 2020 12:08:01 +0530 Subject: [PATCH 0911/1463] drivers/intel/wifi: Add support for Intel Wi-Fi 6 Series Add all Intel WIFI 6 series PCI ids to device/pci_ids.h file. TEST=Harrison Peak (HrP) Wi-Fi module is getting detected during PCI enumeration. Change-Id: Id5452c5c02b58e84d8e5768653b18c9d1246c1bb Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/40224 Reviewed-by: Duncan Laurie Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/drivers/intel/wifi/wifi.c | 8 ++++++++ src/include/device/pci_ids.h | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index af7407df2f..c3e551a7b9 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -145,6 +145,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI, + PCI_DEVICE_ID_HrP_6SERIES_WIFI, + /* Cyclone Peak */ + PCI_DEVICE_ID_CyP_6SERIES_WIFI, + /* Typhoon Peak */ + PCI_DEVICE_ID_TyP_6SERIES_WIFI, + /* Garfiled Peak */ + PCI_DEVICE_ID_GrP_6SERIES_1_WIFI, + PCI_DEVICE_ID_GrP_6SERIES_2_WIFI, 0 }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 13004dbd54..4898a91ce8 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3676,6 +3676,11 @@ #define PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI 0xa0f0 #define PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI 0x02f0 #define PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI 0x06f0 +#define PCI_DEVICE_ID_CyP_6SERIES_WIFI 0x2723 +#define PCI_DEVICE_ID_HrP_6SERIES_WIFI 0x2720 +#define PCI_DEVICE_ID_TyP_6SERIES_WIFI 0x2725 +#define PCI_DEVICE_ID_GrP_6SERIES_1_WIFI 0x51f0 +#define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI 0x7af0 #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 From 182d7bae4769084c56a8206fe0750210c1f44172 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 22 Mar 2020 14:57:36 +0300 Subject: [PATCH 0912/1463] soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver Adds definitions that allow to use the common GPIO driver to configure the Lewisburg PCH pads. Using the GPIO configuration from common/gpio, unlike the FSP-style definitions from Intel RefCode [1] definitions, is more understandable and makes the motherboards code much cleaner. In addition, we can use utilities, such as inteltool, to analyze the configuration of proprietary firmware to add support for new server motherboards with Skylake-SP processors. The pin layout in this patch corresponds to the pinctrl driver in the Linux kernel v4.14 for the Lewisburg PCH GPIO controller [2]. [1] https://designintools.intel.com/product_p/stlgrn45.htm [2] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US. Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39425 Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Makefile.inc | 6 +- src/soc/intel/xeon_sp/gpio.c | 194 +++++ src/soc/intel/xeon_sp/include/soc/gpio.h | 10 + .../include/soc/lewisburg_pch_gpio_defs.h | 668 ++++++++++++++++++ src/soc/intel/xeon_sp/include/soc/pcr_ids.h | 12 +- 5 files changed, 884 insertions(+), 6 deletions(-) create mode 100644 src/soc/intel/xeon_sp/gpio.c create mode 100644 src/soc/intel/xeon_sp/include/soc/gpio.h create mode 100644 src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 1459ee932a..9638c1426c 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -18,9 +18,9 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx -bootblock-y += bootblock.c spi.c lpc.c -romstage-y += romstage.c reset.c util.c spi.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c +bootblock-y += bootblock.c spi.c lpc.c gpio.c +romstage-y += romstage.c reset.c util.c spi.c gpio.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c postcar-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include diff --git a/src/soc/intel/xeon_sp/gpio.c b/src/soc/intel/xeon_sp/gpio.c new file mode 100644 index 0000000000..b8ca4a0b7e --- /dev/null +++ b/src/soc/intel/xeon_sp/gpio.c @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include + +/* + * Reset mapping for Lewisburg PCH. See page 428, Intel Doc #336067-007US + * 00 = RSMRST# + * 01 = Host Deep Reset + * 10 = PLTRST# + * 11 = Reserved + */ +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; + +static const struct pad_group lewisburg_community0_groups[] = { + INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */ + INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */ + INTEL_GPP(GPP_A0, GPP_F0, GPP_F23), /* GPP F */ +}; + +static const struct pad_group lewisburg_community1_groups[] = { + INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */ + INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ + INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ +}; + +static const struct pad_group lewisburg_community3_groups[] = { + INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ +}; + +static const struct pad_group lewisburg_community4_groups[] = { + INTEL_GPP(GPP_J0, GPP_J0, GPP_J23), /* GPP F */ + INTEL_GPP(GPP_J0, GPP_K0, GPP_K10), /* GPP K */ +}; + +static const struct pad_group lewisburg_community5_groups[] = { + INTEL_GPP(GPP_G0, GPP_G0, GPP_G23), /* GPP G */ + INTEL_GPP(GPP_G0, GPP_H0, GPP_H23), /* GPP H */ + INTEL_GPP(GPP_G0, GPP_L0, GPP_L19), /* GPP L */ +}; + +static const struct pad_group lewisburg_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */ +}; + +static const struct pad_community lewisburg_gpio_communities[] = { + [COMM_0] = { /* GPIO Community 0: GPP A, B, F */ + .port = PID_GPIOCOM0, + .first_pad = GPP_A0, + .last_pad = GPP_F23, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM0", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lewisburg_community0_groups, + .num_groups = ARRAY_SIZE(lewisburg_community0_groups), + }, + [COMM_1] = { /* GPIO Community 1: GPP C, D, E */ + .port = PID_GPIOCOM1, + .first_pad = GPP_C0, + .last_pad = GPP_E12, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM1", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lewisburg_community1_groups, + .num_groups = ARRAY_SIZE(lewisburg_community1_groups), + }, + [COMM_3] = { /* GPIO Community 3: GPP I */ + .port = PID_GPIOCOM3, + .first_pad = GPP_I0, + .last_pad = GPP_I10, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM3", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lewisburg_community3_groups, + .num_groups = ARRAY_SIZE(lewisburg_community3_groups), + }, + [COMM_4] = { /* GPIO Community 4: GPP F, G */ + .port = PID_GPIOCOM4, + .first_pad = GPP_J0, + .last_pad = GPP_K10, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lewisburg_community4_groups, + .num_groups = ARRAY_SIZE(lewisburg_community4_groups), + }, + [COMM_5] = { /* GPIO Community 5: GPP G, H, L */ + .port = PID_GPIOCOM5, + .first_pad = GPP_G0, + .last_pad = GPP_L19, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM5", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lewisburg_community5_groups, + .num_groups = ARRAY_SIZE(lewisburg_community5_groups), + }, + [COMM_2] = { /* GPIO Community 2: GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPD11, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM2", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lewisburg_community2_groups, + .num_groups = ARRAY_SIZE(lewisburg_community2_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(lewisburg_gpio_communities); + return lewisburg_gpio_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { GPP_A, GPP_A }, + { GPP_B, GPP_B }, + { GPP_F, GPP_F }, + { GPP_C, GPP_C }, + { GPP_D, GPP_D }, + { GPP_E, GPP_E }, + { GPP_I, GPP_I }, + { GPP_J, GPP_J }, + { GPP_K, GPP_K }, + { GPD, GPD }, + }; + + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/xeon_sp/include/soc/gpio.h b/src/soc/intel/xeon_sp/include/soc/gpio.h new file mode 100644 index 0000000000..f71ddad978 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_GPIO_H_ +#define _SOC_GPIO_H_ + +#include +#include + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h new file mode 100644 index 0000000000..9310096cf3 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h @@ -0,0 +1,668 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef LEWISBURG_GPIO_DEFS_H +#define LEWISBURG_GPIO_DEFS_H + +#ifndef __ACPI__ +#include +#endif + +/* GPIO Community 0 */ +#define COMM_0 0 +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_F 0x2 +/* GPIO Community 1 */ +#define COMM_1 1 +#define GPP_C 0x3 +#define GPP_D 0x4 +#define GPP_E 0x5 +/* GPIO Community 3 */ +#define COMM_3 2 +#define GPP_I 0x6 +/* GPIO Community 4 */ +#define COMM_4 3 +#define GPP_J 0x7 +#define GPP_K 0x8 +/* GPIO Community 5 */ +#define COMM_5 4 +#define GPP_G 0x9 +#define GPP_H 0xA +#define GPP_L 0xB +/* GPIO Community 2 */ +#define COMM_2 5 +#define GPD 0xC + +#define GPIO_NUM_GROUPS 13 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 + +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 + +/* Group F */ +#define GPP_F0 48 +#define GPP_F1 49 +#define GPP_F2 50 +#define GPP_F3 51 +#define GPP_F4 52 +#define GPP_F5 53 +#define GPP_F6 54 +#define GPP_F7 55 +#define GPP_F8 56 +#define GPP_F9 57 +#define GPP_F10 58 +#define GPP_F11 59 +#define GPP_F12 60 +#define GPP_F13 61 +#define GPP_F14 62 +#define GPP_F15 63 +#define GPP_F16 64 +#define GPP_F17 65 +#define GPP_F18 66 +#define GPP_F19 67 +#define GPP_F20 68 +#define GPP_F21 69 +#define GPP_F22 70 +#define GPP_F23 71 + +#define NUM_GPIO_COM0_PADS (GPP_F23 - GPP_A0 + 1) + +/* Community 1 */ +/* Group C */ +#define GPP_C0 72 +#define GPP_C1 73 +#define GPP_C2 74 +#define GPP_C3 75 +#define GPP_C4 76 +#define GPP_C5 77 +#define GPP_C6 78 +#define GPP_C7 79 +#define GPP_C8 80 +#define GPP_C9 81 +#define GPP_C10 82 +#define GPP_C11 83 +#define GPP_C12 84 +#define GPP_C13 85 +#define GPP_C14 86 +#define GPP_C15 87 +#define GPP_C16 88 +#define GPP_C17 89 +#define GPP_C18 90 +#define GPP_C19 91 +#define GPP_C20 92 +#define GPP_C21 93 +#define GPP_C22 94 +#define GPP_C23 95 + +/* Group D */ +#define GPP_D0 96 +#define GPP_D1 97 +#define GPP_D2 98 +#define GPP_D3 99 +#define GPP_D4 100 +#define GPP_D5 101 +#define GPP_D6 102 +#define GPP_D7 103 +#define GPP_D8 104 +#define GPP_D9 105 +#define GPP_D10 106 +#define GPP_D11 107 +#define GPP_D12 108 +#define GPP_D13 109 +#define GPP_D14 110 +#define GPP_D15 111 +#define GPP_D16 112 +#define GPP_D17 113 +#define GPP_D18 114 +#define GPP_D19 115 +#define GPP_D20 116 +#define GPP_D21 117 +#define GPP_D22 118 +#define GPP_D23 119 + +/* Group E */ +#define GPP_E0 120 +#define GPP_E1 121 +#define GPP_E2 122 +#define GPP_E3 123 +#define GPP_E4 124 +#define GPP_E5 125 +#define GPP_E6 126 +#define GPP_E7 127 +#define GPP_E8 128 +#define GPP_E9 129 +#define GPP_E10 130 +#define GPP_E11 131 +#define GPP_E12 132 + +#define NUM_GPIO_COM1_PADS (GPP_E12 - GPP_C0 + 1) + +/* Community 3 */ +/* Group I */ +#define GPP_I0 133 +#define GPP_I1 134 +#define GPP_I2 135 +#define GPP_I3 136 +#define GPP_I4 137 +#define GPP_I5 138 +#define GPP_I6 139 +#define GPP_I7 140 +#define GPP_I8 141 +#define GPP_I9 142 +#define GPP_I10 143 + +#define NUM_GPIO_COM3_PADS (GPP_I10 - GPP_I0 + 1) + +/* Community 4 */ +/* Group J */ +#define GPP_J0 144 +#define GPP_J1 145 +#define GPP_J2 146 +#define GPP_J3 147 +#define GPP_J4 148 +#define GPP_J5 149 +#define GPP_J6 150 +#define GPP_J7 151 +#define GPP_J8 152 +#define GPP_J9 153 +#define GPP_J10 154 +#define GPP_J11 155 +#define GPP_J12 156 +#define GPP_J13 157 +#define GPP_J14 158 +#define GPP_J15 159 +#define GPP_J16 160 +#define GPP_J17 161 +#define GPP_J18 162 +#define GPP_J19 163 +#define GPP_J20 164 +#define GPP_J21 165 +#define GPP_J22 166 +#define GPP_J23 167 + +/* Group K */ +#define GPP_K0 168 +#define GPP_K1 169 +#define GPP_K2 170 +#define GPP_K3 171 +#define GPP_K4 172 +#define GPP_K5 173 +#define GPP_K6 174 +#define GPP_K7 175 +#define GPP_K8 176 +#define GPP_K9 177 +#define GPP_K10 178 + +#define NUM_GPIO_COM4_PADS (GPP_K10 - GPP_J0 + 1) + +/* Community 5 */ +/* Group G */ +#define GPP_G0 179 +#define GPP_G1 180 +#define GPP_G2 181 +#define GPP_G3 182 +#define GPP_G4 183 +#define GPP_G5 184 +#define GPP_G6 185 +#define GPP_G7 186 +#define GPP_G8 187 +#define GPP_G9 188 +#define GPP_G10 189 +#define GPP_G11 190 +#define GPP_G12 191 +#define GPP_G13 192 +#define GPP_G14 193 +#define GPP_G15 194 +#define GPP_G16 195 +#define GPP_G17 196 +#define GPP_G18 197 +#define GPP_G19 198 +#define GPP_G20 199 +#define GPP_G21 200 +#define GPP_G22 201 +#define GPP_G23 202 + +/* Group H */ +#define GPP_H0 203 +#define GPP_H1 204 +#define GPP_H2 205 +#define GPP_H3 206 +#define GPP_H4 207 +#define GPP_H5 208 +#define GPP_H6 209 +#define GPP_H7 210 +#define GPP_H8 211 +#define GPP_H9 212 +#define GPP_H10 213 +#define GPP_H11 214 +#define GPP_H12 215 +#define GPP_H13 216 +#define GPP_H14 217 +#define GPP_H15 218 +#define GPP_H16 219 +#define GPP_H17 220 +#define GPP_H18 221 +#define GPP_H19 222 +#define GPP_H20 223 +#define GPP_H21 224 +#define GPP_H22 225 +#define GPP_H23 226 + +/* Group L */ +#define GPP_L0 227 +#define GPP_L1 228 +#define GPP_L2 229 +#define GPP_L3 230 +#define GPP_L4 231 +#define GPP_L5 232 +#define GPP_L6 233 +#define GPP_L7 234 +#define GPP_L8 235 +#define GPP_L9 236 +#define GPP_L10 237 +#define GPP_L11 238 +#define GPP_L12 239 +#define GPP_L13 240 +#define GPP_L14 241 +#define GPP_L15 242 +#define GPP_L16 243 +#define GPP_L17 244 +#define GPP_L18 245 +#define GPP_L19 246 + +#define NUM_GPIO_COM5_PADS (GPP_L19 - GPP_G0 + 1) + +/* Community 2 */ +/* Group GPD */ +#define GPD0 247 +#define GPD1 248 +#define GPD2 249 +#define GPD3 250 +#define GPD4 251 +#define GPD5 252 +#define GPD6 253 +#define GPD7 254 +#define GPD8 255 +#define GPD9 256 +#define GPD10 257 +#define GPD11 258 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + +#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) + \ + (NUM_GPIO_COM1_GPI_REGS) + \ + (NUM_GPIO_COM3_GPI_REGS) + \ + (NUM_GPIO_COM4_GPI_REGS) + \ + (NUM_GPIO_COM5_GPI_REGS) + \ + (NUM_GPIO_COM2_GPI_REGS)) + +/* + * IOxAPIC IRQs for the GPIOs (This was taken from an intelltool dump) + */ + +/* Community 0 */ +/* Group A */ +#define GPP_A0_IRQ 0x18 +#define GPP_A1_IRQ 0x19 +#define GPP_A2_IRQ 0x1a +#define GPP_A3_IRQ 0x1b +#define GPP_A4_IRQ 0x1c +#define GPP_A5_IRQ 0x1d +#define GPP_A6_IRQ 0x1e +#define GPP_A7_IRQ 0x1f +#define GPP_A8_IRQ 0x20 +#define GPP_A9_IRQ 0x21 +#define GPP_A10_IRQ 0x22 +#define GPP_A11_IRQ 0x23 +#define GPP_A12_IRQ 0x24 +#define GPP_A13_IRQ 0x25 +#define GPP_A14_IRQ 0x26 +#define GPP_A15_IRQ 0x27 +#define GPP_A16_IRQ 0x28 +#define GPP_A17_IRQ 0x29 +#define GPP_A18_IRQ 0x2a +#define GPP_A19_IRQ 0x2b +#define GPP_A20_IRQ 0x2c +#define GPP_A21_IRQ 0x2d +#define GPP_A22_IRQ 0x2e +#define GPP_A23_IRQ 0x2f + +/* Group B */ +#define GPP_B0_IRQ 0x30 +#define GPP_B1_IRQ 0x31 +#define GPP_B2_IRQ 0x32 +#define GPP_B3_IRQ 0x33 +#define GPP_B4_IRQ 0x34 +#define GPP_B5_IRQ 0x35 +#define GPP_B6_IRQ 0x36 +#define GPP_B7_IRQ 0x37 +#define GPP_B8_IRQ 0x38 +#define GPP_B9_IRQ 0x39 +#define GPP_B10_IRQ 0x3a +#define GPP_B11_IRQ 0x3b +#define GPP_B12_IRQ 0x3c +#define GPP_B13_IRQ 0x3d +#define GPP_B14_IRQ 0x3e +#define GPP_B15_IRQ 0x3f +#define GPP_B16_IRQ 0x40 +#define GPP_B17_IRQ 0x41 +#define GPP_B18_IRQ 0x42 +#define GPP_B19_IRQ 0x43 +#define GPP_B20_IRQ 0x44 +#define GPP_B21_IRQ 0x45 +#define GPP_B22_IRQ 0x46 +#define GPP_B23_IRQ 0x47 + +/* Group F */ +#define GPP_F0_IRQ 0x55 +#define GPP_F1_IRQ 0x56 +#define GPP_F2_IRQ 0x57 +#define GPP_F3_IRQ 0x58 +#define GPP_F4_IRQ 0x59 +#define GPP_F5_IRQ 0x5a +#define GPP_F6_IRQ 0x5b +#define GPP_F7_IRQ 0x5c +#define GPP_F8_IRQ 0x5d +#define GPP_F9_IRQ 0x5e +#define GPP_F10_IRQ 0x5f +#define GPP_F11_IRQ 0x60 +#define GPP_F12_IRQ 0x61 +#define GPP_F13_IRQ 0x62 +#define GPP_F14_IRQ 0x63 +#define GPP_F15_IRQ 0x64 +#define GPP_F16_IRQ 0x65 +#define GPP_F17_IRQ 0x66 +#define GPP_F18_IRQ 0x67 +#define GPP_F19_IRQ 0x68 +#define GPP_F20_IRQ 0x69 +#define GPP_F21_IRQ 0x6a +#define GPP_F22_IRQ 0x6b +#define GPP_F23_IRQ 0x6c + +/* Community 1 */ +/* Group C */ +#define GPP_C0_IRQ 0x18 +#define GPP_C1_IRQ 0x19 +#define GPP_C2_IRQ 0x1a +#define GPP_C3_IRQ 0x1b +#define GPP_C4_IRQ 0x1c +#define GPP_C5_IRQ 0x1d +#define GPP_C6_IRQ 0x1e +#define GPP_C7_IRQ 0x1f +#define GPP_C8_IRQ 0x20 +#define GPP_C9_IRQ 0x21 +#define GPP_C10_IRQ 0x22 +#define GPP_C11_IRQ 0x23 +#define GPP_C12_IRQ 0x24 +#define GPP_C13_IRQ 0x25 +#define GPP_C14_IRQ 0x26 +#define GPP_C15_IRQ 0x27 +#define GPP_C16_IRQ 0x28 +#define GPP_C17_IRQ 0x29 +#define GPP_C18_IRQ 0x2a +#define GPP_C19_IRQ 0x2b +#define GPP_C20_IRQ 0x2c +#define GPP_C21_IRQ 0x2d +#define GPP_C22_IRQ 0x2e +#define GPP_C23_IRQ 0x2f + +/* Group D */ +#define GPP_D0_IRQ 0x30 +#define GPP_D1_IRQ 0x31 +#define GPP_D2_IRQ 0x32 +#define GPP_D3_IRQ 0x33 +#define GPP_D4_IRQ 0x34 +#define GPP_D5_IRQ 0x35 +#define GPP_D6_IRQ 0x36 +#define GPP_D7_IRQ 0x37 +#define GPP_D8_IRQ 0x38 +#define GPP_D9_IRQ 0x39 +#define GPP_D10_IRQ 0x3a +#define GPP_D11_IRQ 0x3b +#define GPP_D12_IRQ 0x3c +#define GPP_D13_IRQ 0x3d +#define GPP_D14_IRQ 0x3e +#define GPP_D15_IRQ 0x3f +#define GPP_D16_IRQ 0x40 +#define GPP_D17_IRQ 0x41 +#define GPP_D18_IRQ 0x42 +#define GPP_D19_IRQ 0x43 +#define GPP_D20_IRQ 0x44 +#define GPP_D21_IRQ 0x45 +#define GPP_D22_IRQ 0x46 +#define GPP_D23_IRQ 0x47 + +/* Group E */ +#define GPP_E0_IRQ 0x48 +#define GPP_E1_IRQ 0x49 +#define GPP_E2_IRQ 0x4a +#define GPP_E3_IRQ 0x4b +#define GPP_E4_IRQ 0x4c +#define GPP_E5_IRQ 0x4d +#define GPP_E6_IRQ 0x4e +#define GPP_E7_IRQ 0x4f +#define GPP_E8_IRQ 0x50 +#define GPP_E9_IRQ 0x51 +#define GPP_E10_IRQ 0x52 +#define GPP_E11_IRQ 0x53 +#define GPP_E12_IRQ 0x54 + +/* Community 3 */ +/* Group I */ +#define GPP_I0_IRQ 0x18 +#define GPP_I1_IRQ 0x19 +#define GPP_I2_IRQ 0x1a +#define GPP_I3_IRQ 0x1b +#define GPP_I4_IRQ 0x1c +#define GPP_I5_IRQ 0x1d +#define GPP_I6_IRQ 0x1e +#define GPP_I7_IRQ 0x1f +#define GPP_I8_IRQ 0x20 +#define GPP_I9_IRQ 0x21 +#define GPP_I10_IRQ 0x22 + +/* Community 4 */ +/* Group J */ +#define GPP_J0_IRQ 0x18 +#define GPP_J1_IRQ 0x19 +#define GPP_J2_IRQ 0x1a +#define GPP_J3_IRQ 0x1b +#define GPP_J4_IRQ 0x1c +#define GPP_J5_IRQ 0x1d +#define GPP_J6_IRQ 0x1e +#define GPP_J7_IRQ 0x1f +#define GPP_J8_IRQ 0x20 +#define GPP_J9_IRQ 0x21 +#define GPP_J10_IRQ 0x22 +#define GPP_J11_IRQ 0x23 +#define GPP_J12_IRQ 0x24 +#define GPP_J13_IRQ 0x25 +#define GPP_J14_IRQ 0x26 +#define GPP_J15_IRQ 0x27 +#define GPP_J16_IRQ 0x28 +#define GPP_J17_IRQ 0x29 +#define GPP_J18_IRQ 0x2a +#define GPP_J19_IRQ 0x2b +#define GPP_J20_IRQ 0x2c +#define GPP_J21_IRQ 0x2d +#define GPP_J22_IRQ 0x2e +#define GPP_J23_IRQ 0x2f + +/* Group K */ +#define GPP_K0_IRQ 0x30 +#define GPP_K1_IRQ 0x31 +#define GPP_K2_IRQ 0x32 +#define GPP_K3_IRQ 0x33 +#define GPP_K4_IRQ 0x34 +#define GPP_K5_IRQ 0x35 +#define GPP_K6_IRQ 0x36 +#define GPP_K7_IRQ 0x37 +#define GPP_K8_IRQ 0x38 +#define GPP_K9_IRQ 0x39 +#define GPP_K10_IRQ 0x3a + +/* Community 5 */ +/* Group G */ +#define GPP_G0_IRQ 0x6d +#define GPP_G1_IRQ 0x6e +#define GPP_G2_IRQ 0x6f +#define GPP_G3_IRQ 0x70 +#define GPP_G4_IRQ 0x71 +#define GPP_G5_IRQ 0x72 +#define GPP_G6_IRQ 0x73 +#define GPP_G7_IRQ 0x74 +#define GPP_G8_IRQ 0x75 +#define GPP_G9_IRQ 0x76 +#define GPP_G10_IRQ 0x77 +#define GPP_G11_IRQ 0x2c +#define GPP_G12_IRQ 0x2d +#define GPP_G13_IRQ 0x2e +#define GPP_G14_IRQ 0x2f +#define GPP_G15_IRQ 0x30 +#define GPP_G16_IRQ 0x31 +#define GPP_G17_IRQ 0x32 +#define GPP_G18_IRQ 0x33 +#define GPP_G19_IRQ 0x34 +#define GPP_G20_IRQ 0x35 +#define GPP_G21_IRQ 0x36 +#define GPP_G22_IRQ 0x37 +#define GPP_G23_IRQ 0x38 + +/* Group H */ +#define GPP_H0_IRQ 0x39 +#define GPP_H1_IRQ 0x3a +#define GPP_H2_IRQ 0x3b +#define GPP_H3_IRQ 0x3c +#define GPP_H4_IRQ 0x3d +#define GPP_H5_IRQ 0x3e +#define GPP_H6_IRQ 0x3f +#define GPP_H7_IRQ 0x40 +#define GPP_H8_IRQ 0x41 +#define GPP_H9_IRQ 0x42 +#define GPP_H10_IRQ 0x43 +#define GPP_H11_IRQ 0x44 +#define GPP_H12_IRQ 0x45 +#define GPP_H13_IRQ 0x46 +#define GPP_H14_IRQ 0x47 +#define GPP_H15_IRQ 0x48 +#define GPP_H16_IRQ 0x49 +#define GPP_H17_IRQ 0x4a +#define GPP_H18_IRQ 0x4b +#define GPP_H19_IRQ 0x4c +#define GPP_H20_IRQ 0x4d +#define GPP_H21_IRQ 0x4e +#define GPP_H22_IRQ 0x4f +#define GPP_H23_IRQ 0x50 + +/* Group L */ +#define GPP_L2_IRQ 0x18 +#define GPP_L3_IRQ 0x19 +#define GPP_L4_IRQ 0x1a +#define GPP_L5_IRQ 0x1b +#define GPP_L6_IRQ 0x1c +#define GPP_L7_IRQ 0x1d +#define GPP_L8_IRQ 0x1e +#define GPP_L9_IRQ 0x1f +#define GPP_L10_IRQ 0x20 +#define GPP_L11_IRQ 0x21 +#define GPP_L12_IRQ 0x22 +#define GPP_L13_IRQ 0x23 +#define GPP_L14_IRQ 0x24 +#define GPP_L15_IRQ 0x25 +#define GPP_L16_IRQ 0x26 +#define GPP_L17_IRQ 0x27 +#define GPP_L18_IRQ 0x28 +#define GPP_L19_IRQ 0x29 + +/* Community 2 */ +/* Group GPD */ +#define GPD0_IRQ 0x18 +#define GPD1_IRQ 0x19 +#define GPD2_IRQ 0x1a +#define GPD3_IRQ 0x1b +#define GPD4_IRQ 0x1c +#define GPD5_IRQ 0x1d +#define GPD6_IRQ 0x1e +#define GPD7_IRQ 0x1f +#define GPD8_IRQ 0x20 +#define GPD9_IRQ 0x21 +#define GPD10_IRQ 0x22 +#define GPD11_IRQ 0x23 + +/* Register defines */ +#define GPIO_MISCCFG 0x10 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 + +#define HOSTSW_OWN_REG_0 0xd0 +#define PAD_CFG_BASE 0x400 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1a0 + +#endif /* LEWISBURG_GPIO_DEFS_H */ diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index 8d53ab77e2..ec1e79d4dd 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -16,8 +16,14 @@ #ifndef _PCR_IDS_H_ #define _PCR_IDS_H_ -#define PID_ITSS 0xC4 -#define PID_RTC 0xC3 -#define PID_DMI 0xEF +#define PID_ITSS 0xC4 +#define PID_RTC 0xC3 +#define PID_DMI 0xEF +#define PID_GPIOCOM5 0x11 +#define PID_GPIOCOM4 0xAB +#define PID_GPIOCOM3 0xAC +#define PID_GPIOCOM2 0xAD +#define PID_GPIOCOM1 0xAE +#define PID_GPIOCOM0 0xAF #endif /* _PCR_IDS_H_ */ From ce2399a4461a3e52c992f1cbaf3a66816c2495c0 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Wed, 1 Apr 2020 20:23:38 +0300 Subject: [PATCH 0913/1463] soc/intel/common: gpio: print error if pad is not found Allow to print a debug error message when the GPIO community does not contain the pad number from the motherboard configuration. Change-Id: I21fb389a5d29e11b1fbc24e836d91e17957047f1 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40021 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- src/soc/intel/common/block/gpio/gpio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 45406dbece..dedd36492c 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -89,7 +89,8 @@ static inline size_t gpio_group_index(const struct pad_community *comm, return i; } } - + printk(BIOS_ERR, "%s: pad %d is not found in community %s!\n", + __func__, relative_pad, comm->name); assert(0); return i; From 5b06ffea5691562eb275d4cce809d6419ca75765 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 22 Mar 2020 14:57:36 +0300 Subject: [PATCH 0914/1463] soc/xeon_sp: add configs to use common/gpio diver Allow the use of the common/gpio driver to create Lewisburg PCH pad configurations for server motherboards with Skylake-SP processors. This patch should only be applied after adding Lewisburg PCH definitions to the soc/intel/xeon_sp code [1]. [1] https://review.coreboot.org/c/coreboot/+/39425 Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39428 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 468cb44c27..b10c7bee10 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -61,6 +61,10 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS + select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER select UDELAY_TSC From e0b41fd12eb985a16219deb1baa280fd2a346131 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Fri, 3 Apr 2020 16:38:14 +0900 Subject: [PATCH 0915/1463] mb/google/nightfury: Update DPTF parameters Apply initial DPTF parameters for nightfury from internal thermal team. Will update after further thermal/performance tuning. BUG=b:149226871 BRANCH=firmware-hatch-12672.B TEST=built and verified FAN worked by DPTF active policy Signed-off-by: Seunghwan Kim Change-Id: I712bdd8edc999ef7ee33f4adf21893be12e86bec Reviewed-on: https://review.coreboot.org/c/coreboot/+/40115 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../nightfury/include/variant/acpi/dptf.asl | 70 +++++++++++++------ 1 file changed, 48 insertions(+), 22 deletions(-) diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl index 894e2f0d2c..cdb4258b10 100644 --- a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl @@ -1,38 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define DPTF_CPU_PASSIVE 50 +#define DPTF_CPU_PASSIVE 90 #define DPTF_CPU_CRITICAL 105 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" -#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_PASSIVE 75 #define DPTF_TSR0_CRITICAL 90 -#define DPTF_TSR0_TABLET_PASSIVE 32 -#define DPTF_TSR0_TABLET_CRITICAL 90 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V" -#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_PASSIVE 70 #define DPTF_TSR1_CRITICAL 90 -#define DPTF_TSR1_TABLET_PASSIVE 32 -#define DPTF_TSR1_TABLET_CRITICAL 90 +#define DPTF_TSR1_ACTIVE_AC0 48 +#define DPTF_TSR1_ACTIVE_AC1 46 +#define DPTF_TSR1_ACTIVE_AC2 44 +#define DPTF_TSR1_ACTIVE_AC3 41 +#define DPTF_TSR1_ACTIVE_AC4 39 #define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA" -#define DPTF_TSR2_PASSIVE 45 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - GT" +#define DPTF_TSR2_PASSIVE 75 #define DPTF_TSR2_CRITICAL 90 -#define DPTF_TSR2_TABLET_PASSIVE 32 -#define DPTF_TSR2_TABLET_CRITICAL 90 - -#define DPTF_TSR3_SENSOR_ID 3 -#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT" -#define DPTF_TSR3_PASSIVE 45 -#define DPTF_TSR3_CRITICAL 90 -#define DPTF_TSR3_TABLET_PASSIVE 32 -#define DPTF_TSR3_TABLET_CRITICAL 90 #define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { @@ -42,6 +35,42 @@ Name (CHPS, Package () { Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ }) +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 5900, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5400, 180, 1800}, + Package () {70, 0xFFFFFFFF, 4900, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4500, 115, 1150}, + Package () {50, 0xFFFFFFFF, 4000, 90, 900}, + Package () {40, 0xFFFFFFFF, 3000, 55, 550}, + Package () {30, 0xFFFFFFFF, 2200, 30, 300}, + Package () {20, 0xFFFFFFFF, 1600, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + 0, // Revision + + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, AC7, AC8, AC9 + */ + Package () { + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 70, 63, 54, 48, 44, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } +}) + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, @@ -52,11 +81,8 @@ Name (DTRT, Package () { /* Charger Throttle Effect on Charger (TSR0) */ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 }, - /* CPU Throttle Effect on IA (TSR2) */ + /* CPU Throttle Effect on GT (TSR2) */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on GT (TSR3) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 10, 0, 0, 0, 0 }, }) Name (MPPC, Package () From 72e987d540e9eb8f9b50454be880c3aa4a5bff51 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 7 Apr 2020 15:25:16 +0200 Subject: [PATCH 0916/1463] soc/amd/stoneyridge: replace get_soc_config with config_of_soc get_soc_config was a reimplementation of config_of_soc. Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40257 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/i2c.c | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index bd8fd5b842..3f95be73c3 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -34,19 +35,6 @@ uintptr_t dw_i2c_base_address(unsigned int bus) return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; } -static const struct soc_amd_stoneyridge_config *get_soc_config(void) -{ - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - return dev->chip_info; -} - const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_stoneyridge_config *config; @@ -54,9 +42,8 @@ const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) if (bus >= ARRAY_SIZE(i2c_bus_address)) return NULL; - config = get_soc_config(); - if (config == NULL) - return NULL; + /* config is not NULL; if it was, config_of_soc calls die() internally */ + config = config_of_soc(); return &config->i2c[bus]; } @@ -97,10 +84,8 @@ static void dw_i2c_soc_init(bool is_early_init) size_t i; const struct soc_amd_stoneyridge_config *config; - config = get_soc_config(); - - if (config == NULL) - return; + /* config is not NULL; if it was, config_of_soc calls die() internally */ + config = config_of_soc(); for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { const struct dw_i2c_bus_config *cfg = &config->i2c[i]; From 00058f513e8a5005d566a927eca183d2123d3e19 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 6 Apr 2020 23:36:24 +0200 Subject: [PATCH 0917/1463] soc/amd/picasso: replace get_soc_config with config_of_soc get_soc_config was a reimplementation of config_of_soc, so drop get_soc_config and cfg_util.c. Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons --- src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/picasso/cfg_util.c | 20 -------------------- src/soc/amd/picasso/i2c.c | 12 +++++------- 3 files changed, 5 insertions(+), 28 deletions(-) delete mode 100644 src/soc/amd/picasso/cfg_util.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6b32c6e8e2..2f4f00bc04 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -77,7 +77,6 @@ ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c -all-y += cfg_util.c all-y += reset.c smm-y += smihandler.c diff --git a/src/soc/amd/picasso/cfg_util.c b/src/soc/amd/picasso/cfg_util.c deleted file mode 100644 index b0b06522da..0000000000 --- a/src/soc/amd/picasso/cfg_util.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include -#include -#include -#include "chip.h" - -const config_t *get_soc_config(void) -{ - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - return dev->chip_info; -} diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 6bbc7a7adc..dec409f060 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -37,9 +38,8 @@ const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) return NULL; - config = get_soc_config(); - if (config == NULL) - return NULL; + /* config is not NULL; if it was, config_of_soc calls die() internally */ + config = config_of_soc(); return &config->i2c[bus]; } @@ -80,10 +80,8 @@ static void dw_i2c_soc_init(bool is_early_init) uint32_t pad_ctrl; int misc_reg; - config = get_soc_config(); - - if (config == NULL) - return; + /* config is not NULL; if it was, config_of_soc calls die() internally */ + config = config_of_soc(); for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { const struct dw_i2c_bus_config *cfg = &config->i2c[i]; From dc98bed86928a5b419e6ab7d7e451dd1ca73a95d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 27 Mar 2020 19:43:50 +0100 Subject: [PATCH 0918/1463] mb/intel/d510mo: Add vbt file Add vbt file extracted from the vendor UEFI blob version 0524. Change-Id: Idd39065e9cf5a420317d79695cf032713173eeab Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/39880 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Felix Singer --- src/mainboard/intel/d510mo/Kconfig | 1 + src/mainboard/intel/d510mo/data.vbt | Bin 0 -> 3730 bytes 2 files changed, 1 insertion(+) create mode 100644 src/mainboard/intel/d510mo/data.vbt diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 738eabc4e6..c7d7de0d1c 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select DRIVERS_I2C_CK505 + select INTEL_GMA_HAVE_VBT config MAX_CPUS int diff --git a/src/mainboard/intel/d510mo/data.vbt b/src/mainboard/intel/d510mo/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..7cf261dca6fc76fddd6a9e2c38ca67f3ff79d1f1 GIT binary patch literal 3730 zcmdT`U2GIp6h3!;c4zO-Y^Ot^+f6MOB{;26X4|GAO^vhLA9rzSx7$)zVnTu4NJ)iS zisDbwQR`14k(CF-Lt`4Blm|nM5BfrQFp+3fo`^9d_6ZeC}kg3ENdG! z?aU3C^&FX+Y-Ndw36|qJM_I0Tv^e!_vCyhf?(V#(NCbe$P(y%_MFzc6KnjJZph_Z< zWlau~puAr0lOs~Ul#x=la0UbkV3Pv(>yYWsRzgCV==WJg25?h%S$K2r-YST=H>nY< zwvNsnUEOxFw?DNrlg*8c=J!15y!^_mvoTmagyEpt5=97ujlm}POf=z&D8O}b2gIcd zFcYxg<3JR?M*a!;T2O&Mf(B@c0UMFy$o&e1Eb<=Y0`fD+FCxE&d=fcujQm*^U<_ay zk4ExQM+D-4?T>qXtmATUW>fw+<6{(&%a=}93gVc70~~RN_*m;AaW;8lsB_Vo^XKQh zd9(GK zgRofsCJN=U@-W~H=;#^moYZ+I0#P3uT@*#;k2fQt9+>{PT&7>a(km>NE35xsd*Lr& zla8AZS!E};!L=)lq1Ux7!T!mES_?Zt0#WI9RMZ974WNl|9B3p2`1r=kZ^csQtoW>@1|;(mowB`O5r*NH5k?3QQdnG zh|moppcF)Gn5C<=edE?Kh?fcg{^8o*A#7AyK@r#BI`THy2$Shh8}&XY8K zu>JVLP;85xKV6Ze9sy`&Q9%|k@;N$V2_mCk0SO0{AN+sU_t}@ zj=u&d5eDAx0@(g<^jKA>;KBErrZ;A>(3*ejhRw zYQ!krOwAlM3X~qE<{ULXqV!X0UZKWslnPyEsM4AINU4{OKv%GpKA5H zd#SZFKNf4UE#^OD%qOW7;yzcoJG0xFpFH~jdRmT2F1a5Kb&dIiF^LfNVp>~fx}MyP z-IbU$FD9AY@>&Gt2H`JQP)fIX!B_d+v3g6jdbqWJcUV^WiOZ{b!T4W#awxx^?QkmP zl%G?L=Ly^Dv!L0AF$dO->3S`<_F}?sERy=rJ_rn40LY)YckR~o;HDg3@Mii8+Xmq| literal 0 HcmV?d00001 From ef6eceea562c8f2f5c2c430ae4fb45bd58252acb Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 6 Mar 2020 02:11:53 +0100 Subject: [PATCH 0919/1463] sb/ibexpeak: Use .device for single PCI ID Signed-off-by: Felix Singer Change-Id: I40c4447579cfbf2b9c52dcfaa34f34b22f75c89c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39332 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/intel/ibexpeak/thermal.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 298016f39a..df261de9d7 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -43,13 +43,8 @@ static struct device_operations thermal_ops = { .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_IBEXPEAK_THERMAL, - 0 -}; - static const struct pci_driver pch_thermal __pci_driver = { .ops = &thermal_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .device = PCI_DID_INTEL_IBEXPEAK_THERMAL, }; From 200f02a518600659f0517febc180b27f06533115 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 7 Apr 2020 12:52:55 +1000 Subject: [PATCH 0920/1463] mb/google/hatch: Allow variants to not necessarily be laptops In some cases Hatch variants are not laptop form-factors such as Puff. Ensure that the base configuration does not assume the form factor and allow variants to elect their intended use-case. Note that the issue is that early ec sync needs to be disabled for EFS2 to function correctly, see commit 6daa8c3ba5f from the FIXME line. The relationship is that desktops do not have a battery. BUG=b:152951181 BRANCH=none TEST=none Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40252 Reviewed-by: Angel Pons Reviewed-by: Shelley Chen Reviewed-by: Daniel Kurtz Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 16 ++++++++++++---- src/mainboard/google/hatch/Kconfig.name | 13 +++++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 04790e0e0a..ff3f6a46ec 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -22,10 +22,13 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE - select SYSTEM_TYPE_LAPTOP select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE +config BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select SYSTEM_TYPE_LAPTOP + def_bool n + if BOARD_GOOGLE_BASEBOARD_HATCH config CHROMEOS @@ -134,8 +137,13 @@ config VARIANT_DIR config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - # FIXME: allow kconfig to select on a subset of boards only - select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_PUFF - select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_HATCH + +if BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + +config VBOOT + select VBOOT_EARLY_EC_SYNC + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 454561b105..ac64a9ea9c 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -3,38 +3,45 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI bool "-> Akemi" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_DRATINI bool "-> Dratini" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_JINLON bool "-> Jinlon" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_KINDRED bool "-> Kindred" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 @@ -42,11 +49,13 @@ config BOARD_GOOGLE_HELIOS config BOARD_GOOGLE_MUSHU bool "-> Mushu" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_PALKIA bool "-> Palkia" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 @@ -54,6 +63,7 @@ config BOARD_GOOGLE_PALKIA config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_PUFF @@ -67,6 +77,7 @@ config BOARD_GOOGLE_PUFF config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 @@ -74,9 +85,11 @@ config BOARD_GOOGLE_HELIOS_DISKSWAP config BOARD_GOOGLE_STRYKE bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_SUSHI bool "-> Sushi" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 From 25d20d3332d76cbeda8c38a39ba9af2ef762d417 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 6 Apr 2020 09:12:50 +0200 Subject: [PATCH 0921/1463] sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macro Change-Id: If57d785b92f0f09d9def90b8ac87833321e3cfcf Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40225 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/early_smbus.c | 3 ++- src/southbridge/intel/ibexpeak/early_smbus.c | 3 ++- src/southbridge/intel/lynxpoint/early_smbus.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index f3151af200..0275078129 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -17,7 +18,7 @@ int smbus_enable_iobar(uintptr_t base) pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 0c99a2245f..b87c872012 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -17,7 +18,7 @@ int smbus_enable_iobar(uintptr_t base) pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index f3151af200..0275078129 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -17,7 +18,7 @@ int smbus_enable_iobar(uintptr_t base) pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ From eb00e8722b21da6362f53179d24512d2236f62da Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 6 Apr 2020 09:38:38 +0200 Subject: [PATCH 0922/1463] sb/intel/i82801gx: Use 'const' to set pci_devfn_t statically Change-Id: I4b33b42f41c7e34c5eab70edf2f12862816220d8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40226 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 9164c585f9..44a6846458 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -8,7 +8,7 @@ static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 3a1369a34b..1c0130194c 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -14,7 +14,7 @@ uintptr_t smbus_base(void) int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + const pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ if (pci_read_config16(dev, 0x2) != 0x27da) From 961658f3dc33720ad12371b973b4bf48a53a17b2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 6 Apr 2020 09:42:21 +0200 Subject: [PATCH 0923/1463] nb/intel/i945: Use 'const' to set pci_devfn_t statically Change-Id: I879dd2fc61bc385486b506e2123f32629a67f518 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40227 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/northbridge/intel/i945/early_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 368ebd2748..d7bc1c6205 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -498,10 +498,10 @@ static void i945_setup_pci_express_x16(void) u32 timeout; u32 reg32; u16 reg16; - pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); + const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); u8 tmp_secondary = 0x0a; - pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); + const pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); @@ -761,7 +761,7 @@ disable_pciexpress_x16_link: static void i945_setup_root_complex_topology(void) { u32 reg32; - pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); + const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); /* Egress Port Root Topology */ From af0f410c702bf3468ca9be0a4ea8e21c4f7a67d6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 31 Mar 2020 21:50:35 +0200 Subject: [PATCH 0924/1463] drivers/intel/gma: Remove unneeded white space Change-Id: I816cfe0e3114fe270c6c48014705dbee3b10fd50 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39990 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/intel/gma/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 38ea72a6f9..4ebdc5999f 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -242,9 +242,9 @@ #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) #define MI_BATCH_NON_SECURE (1) /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ -#define MI_BATCH_NON_SECURE_I965 (1<<8) +#define MI_BATCH_NON_SECURE_I965 (1<<8) #define MI_BATCH_PPGTT_HSW (1<<8) -#define MI_BATCH_NON_SECURE_HSW (1<<13) +#define MI_BATCH_NON_SECURE_HSW (1<<13) #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ From a895c32242836c4a6da6c3bbceefc102fdc77636 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 31 Mar 2020 21:55:16 +0200 Subject: [PATCH 0925/1463] soc/intel: Remove unneeded whitespaces Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39991 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/acpi/lpit.asl | 2 +- src/soc/intel/common/acpi/platform.asl | 2 +- src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 6ae4975ee1..0d2d9c39f0 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -78,7 +78,7 @@ scope(\_SB) /* * Save the current PM bits then * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ + */ If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 6ec2ac9fe3..338e681db1 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -32,7 +32,7 @@ Method (_PTS, 1) /* * Save the current PM bits then * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ + */ If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index b3278f529c..ede2208f0d 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -19,7 +19,7 @@ * The mapping fields ae Address, Pin, Source, Source Index. */ -#define GEN_PCIE_LEGACY_IRQ() \ +#define GEN_PCIE_LEGACY_IRQ() \ Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ From e6c04b9255f2ccba03ffa31fea2e9c7c413fb9c1 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 7 Apr 2020 22:01:59 -0700 Subject: [PATCH 0926/1463] ec/google/chromeec: Update ec_commands.h This change copies ec_commands.h directly from Chromium OS EC repo at sha b3c3f6a8f. Signed-off-by: Furquan Shaikh Change-Id: I940f5c7fe8ad4d989a1dfcd6da3ccf9fc151ec56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40266 Tested-by: build bot (Jenkins) Reviewed-by: Rajat Jain Reviewed-by: Karthik Ramasubramanian Reviewed-by: Tim Wawrzynczak --- src/ec/google/chromeec/ec_commands.h | 206 ++++++++++++++++++++++++--- 1 file changed, 183 insertions(+), 23 deletions(-) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 7b5a067114..18be8d30b2 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -39,12 +39,13 @@ extern "C" { #endif +#ifdef CHROMIUM_EC /* * CHROMIUM_EC is defined by the Makefile system of Chromium EC repository. * It is used to not include macros that may cause conflicts in foreign * projects (refer to crbug.com/984623). */ -#ifdef CHROMIUM_EC + /* * Include common.h for CONFIG_HOSTCMD_ALIGNED, if it's defined. This * generates more efficient code for accessing request/response structures on @@ -54,8 +55,18 @@ extern "C" { #include "compile_time_macros.h" #else - #define BUILD_ASSERT(_cond) +#endif /* CHROMIUM_EC */ + +#ifdef __KERNEL__ +#include +#else +/* + * Defines macros that may be needed but are for sure defined by the linux + * kernel. This section is removed when cros_ec_commands.h is generated (by + * util/make_linux_ec_commands_h.sh). + * cros_ec_commands.h looks more integrated to the kernel. + */ #ifndef BIT #define BIT(nr) (1UL << (nr)) @@ -65,7 +76,7 @@ extern "C" { #define BIT_ULL(nr) (1ULL << (nr)) #endif -#endif /* CHROMIUM_EC */ +#endif /* __KERNEL__ */ /* * Current version of this protocol @@ -1073,10 +1084,22 @@ struct ec_response_hello { /* Get version number */ #define EC_CMD_GET_VERSION 0x0002 -enum ec_current_image { +#if !defined(CHROMIUM_EC) && !defined(__KERNEL__) +/* + * enum ec_current_image is deprecated and replaced by enum ec_image. This + * macro exists for backwards compatibility of external projects until they + * have been updated: b/149987779. + */ +#define ec_current_image ec_image +#endif + +enum ec_image { EC_IMAGE_UNKNOWN = 0, EC_IMAGE_RO, - EC_IMAGE_RW + EC_IMAGE_RW, + EC_IMAGE_RW_A = EC_IMAGE_RW, + EC_IMAGE_RO_B, + EC_IMAGE_RW_B }; /** @@ -1084,7 +1107,7 @@ enum ec_current_image { * @version_string_ro: Null-terminated RO firmware version string. * @version_string_rw: Null-terminated RW firmware version string. * @reserved: Unused bytes; was previously RW-B firmware version string. - * @current_image: One of ec_current_image. + * @current_image: One of ec_image. */ struct ec_response_get_version { char version_string_ro[32]; @@ -1390,6 +1413,12 @@ enum ec_feature_code { * MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, + /* + * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. + * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should + * be sent to RO to be precise. + */ + EC_FEATURE_EFS2 = 38, /* The MCU is a System Companion Processor (SCP). */ EC_FEATURE_SCP = 39, /* The MCU is an Integrated Sensor Hub */ @@ -1808,6 +1837,68 @@ struct ec_response_rand_num { BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0); +/** + * Get information about the key used to sign the RW firmware. + * For more details on the fields, see "struct vb21_packed_key". + */ +#define EC_CMD_RWSIG_INFO 0x001B +#define EC_VER_RWSIG_INFO 0 + +#define VBOOT2_KEY_ID_BYTES 20 + +#ifdef CHROMIUM_EC +/* Don't force external projects to depend on the vboot headers. */ +#include "vb21_struct.h" +BUILD_ASSERT(sizeof(struct vb2_id) == VBOOT2_KEY_ID_BYTES); +#endif + +struct ec_response_rwsig_info { + /** + * Signature algorithm used by the key + * (enum vb2_signature_algorithm). + */ + uint16_t sig_alg; + + /** + * Hash digest algorithm used with the key + * (enum vb2_hash_algorithm). + */ + uint16_t hash_alg; + + /** Key version. */ + uint32_t key_version; + + /** Key ID (struct vb2_id). */ + uint8_t key_id[VBOOT2_KEY_ID_BYTES]; + + uint8_t key_is_valid; + + /** Alignment padding. */ + uint8_t reserved[3]; +} __ec_align4; + +BUILD_ASSERT(sizeof(struct ec_response_rwsig_info) == 32); + +/** + * Get information about the system, such as reset flags, locked state, etc. + */ +#define EC_CMD_SYSINFO 0x001C +#define EC_VER_SYSINFO 0 + +enum sysinfo_flags { + SYSTEM_IS_LOCKED = BIT(0), + SYSTEM_IS_FORCE_LOCKED = BIT(1), + SYSTEM_JUMP_ENABLED = BIT(2), + SYSTEM_JUMPED_TO_CURRENT_IMAGE = BIT(3), + SYSTEM_REBOOT_AT_SHUTDOWN = BIT(4) +}; + +struct ec_response_sysinfo { + uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ + uint32_t current_image; /**< enum ec_current_image */ + uint32_t flags; /**< enum sysinfo_flags */ +} __ec_align4; + /*****************************************************************************/ /* PWM commands */ @@ -2412,7 +2503,7 @@ enum motionsense_command { /* * Sensor Offset command is a setter/getter command for the offset - * used for calibration. + * used for factory calibration. * The offsets can be calculated by the host, or via * PERFORM_CALIB command. */ @@ -2457,6 +2548,11 @@ enum motionsense_command { */ MOTIONSENSE_CMD_SENSOR_SCALE = 18, + /* + * Read the current online calibration values (if available). + */ + MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2508,6 +2604,7 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_TCS3400 = 20, MOTIONSENSE_CHIP_LIS2DW12 = 21, MOTIONSENSE_CHIP_LIS2DWL = 22, + MOTIONSENSE_CHIP_LIS2DS = 23, MOTIONSENSE_CHIP_MAX, }; @@ -2540,6 +2637,12 @@ struct ec_response_motion_sensor_data { }; } __ec_todo_packed; +/* Response to AP reporting calibration data for a given sensor. */ +struct ec_response_online_calibration_data { + /** The calibration values. */ + int16_t data[3]; +}; + /* Note: used in ec_response_get_next_data */ struct ec_response_motion_sense_fifo_info { /* Size of the fifo */ @@ -2653,7 +2756,7 @@ struct ec_params_motion_sense { */ struct __ec_todo_unpacked { uint8_t sensor_num; - } info, info_3, data, fifo_flush, list_activities; + } info, info_3, info_4, data, fifo_flush, list_activities; /* * Used for MOTIONSENSE_CMD_PERFORM_CALIB: @@ -2663,6 +2766,7 @@ struct ec_params_motion_sense { uint8_t sensor_num; uint8_t enable; } perform_calib; + /* * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR * and MOTIONSENSE_CMD_SENSOR_RANGE. @@ -2795,6 +2899,15 @@ struct ec_params_motion_sense { */ int16_t hys_degree; } tablet_mode_threshold; + + /* + * Used for MOTIONSENSE_CMD_ONLINE_CALIB_READ: + * Allow reading a single sensor's online calibration value. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } online_calib_read; + }; } __ec_todo_packed; @@ -2915,6 +3028,8 @@ struct ec_response_motion_sense { struct ec_response_motion_sense_fifo_data fifo_read; + struct ec_response_online_calibration_data online_calib_read; + struct __ec_todo_packed { uint16_t reserved; uint32_t enabled; @@ -3572,6 +3687,9 @@ enum ec_mkbp_event { /* We have entered DisplayPort Alternate Mode on a Type-C port. */ EC_MKBP_EVENT_DP_ALT_MODE_ENTERED = 10, + /* New online calibration values are available. */ + EC_MKBP_EVENT_ONLINE_CALIBRATION = 11, + /* Number of MKBP events */ EC_MKBP_EVENT_COUNT, }; @@ -5220,27 +5338,24 @@ enum pd_cc_states { PD_CC_NONE = 0, /* No port partner attached */ /* From DFP perspective */ + PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ /* From UFP perspective */ - PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ + PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ }; -#define USBC_CABLE_TYPE_UNDEF 0 /* Undefined */ -#define USBC_CABLE_TYPE_PASSIVE 3 /* Passive cable attached */ -#define USBC_CABLE_TYPE_ACTIVE 4 /* Active cable attached */ - /* Active/Passive Cable */ -#define USB_PD_MUX_TBT_ACTIVE_CABLE BIT(0) +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) /* Optical/Non-optical cable */ -#define USB_PD_MUX_TBT_CABLE_TYPE BIT(1) +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) /* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */ -#define USB_PD_MUX_TBT_ADAPTER BIT(2) -/* Active Link enabled/disabled */ -#define USB_PD_MUX_TBT_LINK BIT(3) +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) +/* Active Link Uni-Direction */ +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) /* * Underdevelopement : @@ -5253,10 +5368,10 @@ struct ec_response_usb_pd_control_v2 { char state[32]; uint8_t cc_state; /* enum pd_cc_states representing cc state */ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ - uint8_t cable_type; /* USBC_CABLE_TYPE_*cable_type */ - uint8_t control_flags; /* USB_PD_MUX_*flags */ - uint8_t cable_speed; - uint8_t cable_gen; /* rounded_support */ + uint8_t reserved; /* Reserved for future use */ + uint8_t control_flags; /* USB_PD_CTRL_*flags */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; #define EC_CMD_USB_PD_PORTS 0x0102 @@ -5352,7 +5467,7 @@ struct ec_params_usb_pd_rw_hash_entry { * TODO(rspangler) but it's not aligned! * Should have been reserved[2]. */ - uint32_t current_image; /* One of ec_current_image */ + uint32_t current_image; /* One of ec_image */ } __ec_align1; /* Read USB-PD Accessory info */ @@ -5546,6 +5661,10 @@ struct ec_params_usb_pd_mux_info { #define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ #define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ + +/* USB-C Dock connected */ +#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) struct ec_response_usb_pd_mux_info { uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ @@ -5633,6 +5752,7 @@ enum cbi_data_tag { CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ + CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ CBI_TAG_COUNT, }; @@ -5694,6 +5814,9 @@ struct ec_params_set_cbi { #define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ #define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ #define EC_RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset */ +#define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This + * enables PD in RO for Chromebox. + */ struct ec_response_uptime_info { /* @@ -5920,6 +6043,43 @@ struct ec_response_get_pd_port_caps { uint8_t pd_port_location; /* enum ec_pd_port_location */ } __ec_align1; +/*****************************************************************************/ +/* + * Button press simulation + * + * This command is used to simulate a button press. + * Supported commands are vup(volume up) vdown(volume down) & rec(recovery) + * Time duration for which button needs to be pressed is an optional parameter. + * + * NOTE: This is only available on unlocked devices for testing purposes only. + */ +#define EC_CMD_BUTTON 0x0129 + +struct ec_params_button { + /* Button mask aligned to enum keyboard_button_type */ + uint32_t btn_mask; + + /* Duration in milliseconds button needs to be pressed */ + uint32_t press_ms; +} __ec_align1; + +enum keyboard_button_type { + KEYBOARD_BUTTON_POWER = 0, + KEYBOARD_BUTTON_VOLUME_DOWN = 1, + KEYBOARD_BUTTON_VOLUME_UP = 2, + KEYBOARD_BUTTON_RECOVERY = 3, + KEYBOARD_BUTTON_CAPSENSE_1 = 4, + KEYBOARD_BUTTON_CAPSENSE_2 = 5, + KEYBOARD_BUTTON_CAPSENSE_3 = 6, + KEYBOARD_BUTTON_CAPSENSE_4 = 7, + KEYBOARD_BUTTON_CAPSENSE_5 = 8, + KEYBOARD_BUTTON_CAPSENSE_6 = 9, + KEYBOARD_BUTTON_CAPSENSE_7 = 10, + KEYBOARD_BUTTON_CAPSENSE_8 = 11, + + KEYBOARD_BUTTON_COUNT +}; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ From a6cf8d6465f8424862736cb2105de85f80b7c65b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 7 Apr 2020 22:22:22 -0700 Subject: [PATCH 0927/1463] ec/google/chromeec: Replace uses of ec_current_image with ec_image This change replaces all uses of ec_current_image with ec_image since Chromium OS EC has deprecated (sha 78d1ed61d) the use of enum ec_current_image and instead changed it to enum ec_image. BUG=b:149987779 Signed-off-by: Furquan Shaikh Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40267 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Karthik Ramasubramanian Reviewed-by: Tim Wawrzynczak --- src/ec/google/chromeec/ec.c | 4 ++-- src/ec/google/chromeec/ec.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 8bb366183a..8d9c2acb43 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1337,9 +1337,9 @@ static void google_chromeec_log_uptimeinfo(void) } /* Cache and retrieve the EC image type (ro or rw) */ -enum ec_current_image google_chromeec_get_current_image(void) +enum ec_image google_chromeec_get_current_image(void) { - MAYBE_STATIC_BSS enum ec_current_image ec_image_type = EC_IMAGE_UNKNOWN; + MAYBE_STATIC_BSS enum ec_image ec_image_type = EC_IMAGE_UNKNOWN; if (ec_image_type != EC_IMAGE_UNKNOWN) return ec_image_type; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c40172a4ac..f1caeb09fa 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -25,7 +25,7 @@ uint8_t google_chromeec_get_event(void); /* Check if EC supports feature EC_FEATURE_UNIFIED_WAKE_MASKS */ bool google_chromeec_is_uhepi_supported(void); int google_ec_running_ro(void); -enum ec_current_image google_chromeec_get_current_image(void); +enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); int google_chromeec_wait_for_displayport(long timeout); From 6670f44cd0aec048ee881e8c9a38124cb44b2207 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 5 Apr 2020 22:28:15 -0500 Subject: [PATCH 0928/1463] payloads/nvramcui: Select USE_OPTION_TABLE nvramcui requires use of CMOS for NVRAM configuration, so depend on HAVE_OPTION_TABLE and select USE_OPTION_TABLE to ensure that nvramcui is actually functional when included in a build. Change-Id: I0595514f636b8ce67bbc789ecc96a93c99068c50 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40222 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- payloads/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/Kconfig b/payloads/Kconfig index f85dce9175..cfb28d6e81 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -132,7 +132,8 @@ config MEMTEST_SECONDARY_PAYLOAD config NVRAMCUI_SECONDARY_PAYLOAD bool "Load nvramcui as a secondary payload" default n - depends on ARCH_X86 + depends on ARCH_X86 && HAVE_OPTION_TABLE + select USE_OPTION_TABLE help nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads. From b2f8ce7591c80a199d610aad3067e01529c859a1 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Wed, 11 Mar 2020 18:04:58 +0100 Subject: [PATCH 0929/1463] soc/intel/cannonlake: Steal no memory for disabled IGD Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct' to do it like this, otherwise the FSP would always allocate memory for the IGD even if it is disabled. In addition the FSP enables the graphics panel power even if no IGD is present which leads to a crashing FSP. Thus, if no IGD is present we switch off the panel via UPDs. Refer to this issue on IntelFSP for details: https://github.com/IntelFsp/FSP/issues/49 Tested on: * CFL platform with IGD * CFL platform without IGD Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- Documentation/soc/intel/fsp/index.md | 6 +++++ .../intel/cannonlake/romstage/fsp_params.c | 27 +++++++++++++++---- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 769b98b4fc..912c44beea 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -45,6 +45,11 @@ those are fixed. If possible a workaround is described here as well. * Workaround: Disable internal UART manually after calling FSP * Issue on public tracker: [Issue 10] +### CoffeeLakeFsp +* Disabling the internal graphics causes a crash in FSP-M + * 7.0.68.40 and older version + * Workaround: Set "tconfig->PanelPowerEnable = 0" + * Issue on public tracker: [Issue 49] ## Open Source Intel FSP specification @@ -72,4 +77,5 @@ those are fixed. If possible a workaround is described here as well. [Issue 22]: https://github.com/IntelFsp/FSP/issues/22 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35 [Issue 41]: https://github.com/IntelFsp/FSP/issues/41 +[Issue 49]: https://github.com/IntelFsp/FSP/issues/49 diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c84e3516c0..010d152c76 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -2,6 +2,8 @@ /* This file is part of the coreboot project. */ #include +#include +#include #include #include #include @@ -15,14 +17,28 @@ #include "../chip.h" -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) +static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) { + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; + unsigned int i; uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - /* Set IGD stolen size to 64MB. */ - m_cfg->IgdDvmt50PreAlloc = 2; + /* + * Probe for no IGD and disable InternalGfx and panel power to prevent a + * crash in FSP-M. + */ + if (dev && dev->enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { + /* Set IGD stolen size to 64MB. */ + m_cfg->InternalGfx = 1; + m_cfg->IgdDvmt50PreAlloc = 2; + } else { + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + tconfig->PanelPowerEnable = 0; + } m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; @@ -71,6 +87,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } + dev = pcidev_path_on_root(PCH_DEVFN_ISH); /* If ISH is enabled, enable ISH elements */ if (!dev) m_cfg->PchIshEnable = 0; @@ -122,7 +139,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - soc_memory_init_params(m_cfg, config); + soc_memory_init_params(mupd, config); /* Enable SMBus controller based on config */ if (!smbus) From 408fdeba7fc8fdbe99eba6851aec3bedef90de32 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Wed, 8 Apr 2020 15:42:28 +0300 Subject: [PATCH 0930/1463] Doc/mb/lenovo/ivb_internal_flashing: Fix a typo unmount -> umount. My mistake. Change-Id: I5d1b675f6ab7c027f2e646424adb1f255967c753 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/40274 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/mainboard/lenovo/ivb_internal_flashing.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/mainboard/lenovo/ivb_internal_flashing.md b/Documentation/mainboard/lenovo/ivb_internal_flashing.md index e6b597b284..1d02cac5c4 100644 --- a/Documentation/mainboard/lenovo/ivb_internal_flashing.md +++ b/Documentation/mainboard/lenovo/ivb_internal_flashing.md @@ -102,7 +102,7 @@ Replace the last line (`command.com`) with this (change path to the Save the file, then unmount the partition: - sudo unmount /mnt + sudo umount /mnt Write this image to a USB drive (replace `/dev/sdX` with your USB drive device name): From 3408a0ef0c9cc3b2f546b5d6c864ee00d61956f5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 31 Mar 2020 21:10:20 +0200 Subject: [PATCH 0931/1463] mb/intel/d945gclf: Improve code formatting of devicetree Change-Id: I3c8d430a10562edd4404d322e78f603cae191026 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39985 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/d945gclf/devicetree.cb | 94 +++++++++++----------- 1 file changed, 45 insertions(+), 49 deletions(-) diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 3d7e8c632a..9d81e31232 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -14,22 +14,22 @@ chip northbridge/intel/i945 - device cpu_cluster 0 on - chip cpu/intel/socket_441 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_441 + device lapic 0 on end + end + end register "pci_mmio_size" = "768" - device domain 0 on - subsystemid 0x8086 0x464c inherit - device pci 00.0 on end # host bridge + device domain 0 on + subsystemid 0x8086 0x464c inherit + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller + device pci 02.0 on end # vga controller + device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" register "pirqc_routing" = "0x05" @@ -46,60 +46,56 @@ chip northbridge/intel/i945 register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - register "gen1_dec" = "0x0007c0681" # SuperIO Power Management + register "gen1_dec" = "0x0007c0681" # SuperIO Power Management - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe port 1 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 device pci 1c.1 off end # PCIe port 2 - device pci 1c.2 on end # PCIe port 3 - device pci 1c.3 on end # PCIe port 4 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m15x + device pnp 2e.0 off end # Floppy + device pnp 2e.3 off end # Parport + device pnp 2e.4 on + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.5 on + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse + end + device pnp 2e.7 on # Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. + irq 0xf0 = 0x82 # HW accel A20. end - device pnp 2e.8 on # GAME + device pnp 2e.8 on # GAME # all default end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + device pnp 2e.a on end # PME + device pnp 2e.b on end # MPU + end + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end From 17419ff948ad73cbb8d5c98b488eabb18c9ccb1b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 31 Mar 2020 21:24:13 +0200 Subject: [PATCH 0932/1463] mb/intel/icelake_rvp/variants/icl_u: Improve code formatting Change-Id: I2a87e5c0f598d665f1c64ac8cfe235918326d1d5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39988 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- .../icelake_rvp/variants/icl_u/devicetree.cb | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 12accedec4..40f17cebe5 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -169,10 +169,10 @@ chip soc/intel/icelake #| Field | Value | #+-------------------+---------------------------+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI1 | cr50 TPM. Early init is | - #| | required to set up a BAR | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | #| | for TPM communication | - #| | before memory is up | + #| | before memory is up | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -186,8 +186,8 @@ chip soc/intel/icelake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -295,8 +295,8 @@ chip soc/intel/icelake end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -337,7 +337,7 @@ chip soc/intel/icelake device spi 0 on end end end # GSPI #1 - device pci 1f.0 on end # eSPI Interface + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA From db2c8dfecb5086ceb78c59f2108d51ca3129d9c1 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 6 Apr 2020 23:02:12 +0200 Subject: [PATCH 0933/1463] assert.h: Simplify dead_code() It turns out the linker's error message already includes the line number of the dead_code() invocation. If we don't include the line number in the identifier for our undefined reference, we don't need individual identifiers at all and can work with a single, global declaration. Change-Id: Ib63868ce3114c3f839867a3bfb1b03bdb6facf16 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40240 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/include/assert.h | 11 +++-------- src/security/vboot/misc.h | 4 ++-- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/src/include/assert.h b/src/include/assert.h index 492629dd30..7252ab61e2 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -52,15 +52,10 @@ * The error message when this hits will look like this: * * ramstage/lib/bootmode.o: In function `display_init_required': - * bootmode.c:42: undefined reference to `dead_code_assertion_failed_at_line_42' + * bootmode.c:42: undefined reference to `_dead_code_assertion_failed' */ -#define __dead_code(tag, line) do { \ - extern void dead_code_assertion_failed##tag##_at_line_##line(void) \ - __attribute__((noreturn)); \ - dead_code_assertion_failed##tag##_at_line_##line(); \ -} while (0) -#define _dead_code(tag, line) __dead_code(tag, line) -#define dead_code(tag) _dead_code(tag, __LINE__) +extern void _dead_code_assertion_failed(void) __attribute__((noreturn)); +#define dead_code() _dead_code_assertion_failed() /* This can be used in the context of an expression of type 'type'. */ #define dead_code_t(type) ({ \ diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 22cc75052c..fd422b2ff7 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -53,7 +53,7 @@ static inline int verification_should_run(void) else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return ENV_BOOTBLOCK; else - dead_code(_in_vboot_misc_h); + dead_code(); } static inline int verstage_should_load(void) @@ -82,7 +82,7 @@ static inline int vboot_logic_executed(void) /* Post-RAM stages are "after the romstage" */ return !ENV_ROMSTAGE_OR_BEFORE; } else { - dead_code(_in_vboot_misc_h); + dead_code(); } } From c2e796290aa32cb22677cadf467209767cc03f93 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 22:12:52 +0200 Subject: [PATCH 0934/1463] mb/*/*/hda_verb.c: Improve code formatting Change-Id: I294ea867678ad77e454873ecf4948bf2d12c9f80 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39939 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/p5gc-mx/hda_verb.c | 6 +++--- src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c index 897b1d5d84..cd69122e2b 100644 --- a/src/mainboard/asus/p5gc-mx/hda_verb.c +++ b/src/mainboard/asus/p5gc-mx/hda_verb.c @@ -5,9 +5,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0883, /* Vendor ID */ - 0x104382c7, /* Subsystem ID */ - 0x0000000c, /* Number of entries */ + 0x10ec0883, /* Vendor ID */ + 0x104382c7, /* Subsystem ID */ + 0x0000000c, /* Number of entries */ /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c index d6fefcd666..21f8ad834c 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c @@ -5,9 +5,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0662, /* Vendor ID */ - 0x1458a002, /* Subsystem ID */ - 0x00000009, /* Number of entries */ + 0x10ec0662, /* Vendor ID */ + 0x1458a002, /* Subsystem ID */ + 0x00000009, /* Number of entries */ /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), From 9734325f4568c19d1ffc392084aa431a810a0709 Mon Sep 17 00:00:00 2001 From: Varun Joshi Date: Mon, 23 Mar 2020 13:24:36 -0700 Subject: [PATCH 0935/1463] soc/intel/tigerlake: Add support to initialize DDR4 Memory Support to configure DDR4 memory variant. -Add support to read SPD data based on different memory topology. -Initialize FSP UPD's for DQ and DQS mapping. BUG=b:151702387 Signed-off-by: Varun Joshi Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847 Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/include/soc/meminit.h | 41 +++++- src/soc/intel/tigerlake/meminit.c | 132 ++++++++++++++++++ 2 files changed, 172 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index a2fb3f4334..3c4c16b5c2 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -87,7 +87,44 @@ struct lpddr4x_cfg { * the array represents DQ pin# on the memory part. */ uint8_t dqs_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL]; + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; +}; +/* Board-specific memory configuration information for DDR4 memory variant */ +struct mb_ddr4_cfg { + /* + * DQ CPU<>DRAM map: + * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits(1 + * byte). Thus, dq_map is represented as DDR[1-0]_DQ[7-0][7:0], where + * DDR[1-0] : DDR4 channel # + * DQ[7-0] : DQ # within the channel + * [7:0] : Bits within the DQ + * + * Index of the array represents DQ pin# on the CPU, whereas value in + * the array represents DQ pin# on the memory part. + */ + uint8_t dq_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL][BITS_PER_BYTE]; + /* + * DQS CPU<>DRAM map: + * DDR4 memory interface has 8 DQS pairs per channel. Thus, dqs_map is represented as + * DDR[1-0]_DQS[7-0], where + * DDR[1-0] : DDR4 channel # + * DQS[7-0] : DQS # within the channel + * + * Index of the array represents DQS pin# on the CPU, whereas value in + * the array represents DQS pin# on the memory part. + */ + uint8_t dqs_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL]; + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + uint8_t dq_pins_interleaved; /* * Early Command Training Enable/Disable Control * 1 = enable, 0 = disable @@ -97,5 +134,7 @@ struct lpddr4x_cfg { void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, const struct spd_info *spd, bool half_populated); - +/* Initialize DDR4 memory configurations */ +void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, + const struct spd_info *spd, const bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index bd9a4ff45d..7823cfe523 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -296,3 +296,135 @@ void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, board_cfg->dqs_map[i][1]); } } + +static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) +{ + unsigned int i; + + blk->addr_map[0] = info->smbus_info[0].addr_dimm0; + blk->addr_map[1] = info->smbus_info[0].addr_dimm1; + blk->addr_map[2] = info->smbus_info[1].addr_dimm0; + blk->addr_map[3] = info->smbus_info[1].addr_dimm1; + + get_spd_smbus(blk); + + for (i = 0; i < ARRAY_SIZE(blk->addr_map); i++) { + if (blk->addr_map[i]) + print_spd_info((unsigned char *)blk->spd_array[i]); + } +} + +static void ddr4_get_spd(unsigned int channel, const uintptr_t *spd_md_data, + const struct spd_block *spd_sodimm_blk, + const struct spd_info *info, + const bool half_populated, uintptr_t *spd_dimm0, + uintptr_t *spd_dimm1) +{ + if (channel == 0) { + /* For mixed topology, channel 0 can only be Memory_Down */ + if ((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { + *spd_dimm0 = *spd_md_data; + *spd_dimm1 = 0; + } else if (info->topology == SODIMM) { + *spd_dimm0 = (uintptr_t)spd_sodimm_blk->spd_array[0]; + *spd_dimm1 = (uintptr_t)spd_sodimm_blk->spd_array[1]; + } else + die("Undefined memory topology on Channel 0.\n"); + } else if (channel == 1) { + if (half_populated) { + *spd_dimm0 = *spd_dimm1 = 0; + } else if (info->topology == MEMORY_DOWN) { + *spd_dimm0 = *spd_md_data; + *spd_dimm1 = 0; + /* For mixed topology, channel 1 can only be SODIMM */ + } else if ((info->topology == SODIMM) || (info->topology == MIXED)) { + *spd_dimm0 = (uintptr_t)spd_sodimm_blk->spd_array[2]; + *spd_dimm1 = (uintptr_t)spd_sodimm_blk->spd_array[3]; + } else + die("Undefined memory topology on channel 1.\n"); + } else + die("Unsupported channels.\n"); +} + +/* Initialize DDR4 memory configurations */ +void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, + const struct spd_info *info, const bool half_populated) +{ + uintptr_t spd_md_data; + size_t spd_md_len; + uintptr_t spd_dimm0 = 0; + uintptr_t spd_dimm1 = 0; + struct spd_block spd_sodimm_blk; + unsigned int i; + unsigned int index = 0; + + /* Early Command Training Enabled */ + mem_cfg->ECT = board_cfg->ect; + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + + if ((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { + read_md_spd(info, &spd_md_data, &spd_md_len); + mem_cfg->MemorySpdDataLen = spd_md_len; + } + + if ((info->topology == SODIMM) || (info->topology == MIXED)) { + read_sodimm_spd(info, &spd_sodimm_blk); + if ((info->topology == MIXED) && + (mem_cfg->MemorySpdDataLen != spd_sodimm_blk.len)) + die("Mixed topology has incorrect length.\n"); + else + mem_cfg->MemorySpdDataLen = spd_sodimm_blk.len; + } + + for (i = 0; i < DDR4_CHANNELS; i++) { + ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, + half_populated, &spd_dimm0, &spd_dimm1); + init_spd_upds(mem_cfg, i, spd_dimm0, spd_dimm1); + } + + /* + * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits (1 + * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in + * each UPD. + * + * Thus, init_dq_upds() needs to be called for every dq pair of each channel. + * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] + * DqMapCpu2DramCh1 --> dq_map[CHAN=0][2-3] + * DqMapCpu2DramCh2 --> dq_map[CHAN=0][4-5] + * DqMapCpu2DramCh3 --> dq_map[CHAN=0][6-7] + * DqMapCpu2DramCh4 --> dq_map[CHAN=1][0-1] + * DqMapCpu2DramCh5 --> dq_map[CHAN=1][2-3] + * DqMapCpu2DramCh6 --> dq_map[CHAN=1][4-5] + * DqMapCpu2DramCh7 --> dq_map[CHAN=1][6-7] + */ + + /* + * DDR4 memory interface has 8 DQS pairs per channel. FSP UPDs for DQS Map expect a + * pair in each UPD. + * + * Thus, init_dqs_upds() needs to be called for every dqs pair of each channel. + * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] + * DqsMapCpu2DramCh1 --> dqs_map[CHAN=0][2-3] + * DqsMapCpu2DramCh2 --> dqs_map[CHAN=0][4-5] + * DqsMapCpu2DramCh3 --> dqs_map[CHAN=0][6-7] + * DqsMapCpu2DramCh4 --> dqs_map[CHAN=1][0-1] + * DqsMapCpu2DramCh5 --> dqs_map[CHAN=1][2-3] + * DqsMapCpu2DramCh6 --> dqs_map[CHAN=1][4-5] + * DqsMapCpu2DramCh7 --> dqs_map[CHAN=1][6-7] + */ + + for (i = 0; i < DDR4_CHANNELS; i++) { + for (int b = 0; b < DDR4_BYTES_PER_CHANNEL; b += 2) { + if (half_populated && (i == 1)) { + init_dq_upds_empty(mem_cfg, index); + init_dqs_upds_empty(mem_cfg, index); + } else { + init_dq_upds(mem_cfg, index, board_cfg->dq_map[i][b], + board_cfg->dq_map[i][b+1]); + init_dqs_upds(mem_cfg, index, board_cfg->dqs_map[i][b], + board_cfg->dqs_map[i][b+1]); + } + index++; + } + } +} From a461b694a6c0468cd679628aeebf83437027fb45 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 5 Apr 2020 13:55:12 +0200 Subject: [PATCH 0936/1463] Drop unnecessary DEVICE_NOOP entries Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/device/root_device.c | 2 -- src/drivers/generic/adau7002/adau7002.c | 1 - src/drivers/generic/generic/generic.c | 1 - src/drivers/generic/gpio_keys/gpio_keys.c | 1 - src/drivers/generic/gpio_regulator/gpio_regulator.c | 1 - src/drivers/generic/ioapic/ioapic.c | 1 - src/drivers/generic/max98357a/max98357a.c | 1 - src/drivers/i2c/adt7463/adt7463.c | 1 - src/drivers/i2c/at24rf08c/at24rf08c.c | 1 - src/drivers/i2c/ck505/ck505.c | 1 - src/drivers/i2c/da7219/da7219.c | 1 - src/drivers/i2c/generic/generic.c | 1 - src/drivers/i2c/hid/hid.c | 1 - src/drivers/i2c/lm96000/lm96000.c | 1 - src/drivers/i2c/max98373/max98373.c | 1 - src/drivers/i2c/max98927/max98927.c | 1 - src/drivers/i2c/nau8825/nau8825.c | 1 - src/drivers/i2c/nct7802y/nct7802y.c | 1 - src/drivers/i2c/pca9538/pca9538.c | 2 -- src/drivers/i2c/pcf8523/pcf8523.c | 1 - src/drivers/i2c/ptn3460/ptn3460.c | 2 -- src/drivers/i2c/rt1011/rt1011.c | 1 - src/drivers/i2c/rt5663/rt5663.c | 1 - src/drivers/i2c/rtd2132/rtd2132.c | 1 - src/drivers/i2c/rx6110sa/rx6110sa.c | 1 - src/drivers/i2c/sx9310/sx9310.c | 1 - src/drivers/i2c/tpm/chip.c | 1 - src/drivers/i2c/w83793/w83793.c | 1 - src/drivers/intel/ish/ish.c | 1 - src/drivers/intel/mipi_camera/camera.c | 1 - src/drivers/ipmi/ipmi_kcs_ops.c | 1 - src/drivers/spi/acpi/acpi.c | 1 - src/drivers/usb/acpi/usb_acpi.c | 1 - src/ec/compal/ene932/ec.c | 1 - src/ec/google/chromeec/ec_lpc.c | 1 - src/ec/google/wilco/chip.c | 1 - src/ec/quanta/ene_kb3940q/ec.c | 1 - src/ec/quanta/it8518/ec.c | 1 - src/ec/roda/it8518/ec.c | 1 - src/mainboard/emulation/qemu-i440fx/northbridge.c | 1 - src/northbridge/amd/agesa/family14/northbridge.c | 2 -- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 --- src/northbridge/amd/agesa/family16kb/northbridge.c | 3 --- src/northbridge/amd/pi/00630F01/northbridge.c | 2 -- src/northbridge/amd/pi/00660F01/northbridge.c | 1 - src/northbridge/amd/pi/00730F01/northbridge.c | 1 - src/northbridge/intel/e7505/northbridge.c | 1 - src/northbridge/intel/gm45/northbridge.c | 1 - src/northbridge/intel/haswell/northbridge.c | 1 - src/northbridge/intel/i440bx/northbridge.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/ironlake/northbridge.c | 1 - src/northbridge/intel/pineview/northbridge.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 1 - src/northbridge/intel/x4x/northbridge.c | 1 - src/soc/amd/picasso/chip.c | 1 - src/soc/amd/picasso/i2c.c | 1 - src/soc/amd/stoneyridge/chip.c | 1 - src/soc/amd/stoneyridge/i2c.c | 1 - src/soc/cavium/cn81xx/soc.c | 1 - src/soc/intel/apollolake/chip.c | 1 - src/soc/intel/baytrail/chip.c | 1 - src/soc/intel/braswell/chip.c | 1 - src/soc/intel/broadwell/chip.c | 1 - src/soc/intel/cannonlake/chip.c | 2 -- src/soc/intel/denverton_ns/chip.c | 1 - src/soc/intel/denverton_ns/uart.c | 1 - src/soc/intel/icelake/chip.c | 2 -- src/soc/intel/jasperlake/chip.c | 2 -- src/soc/intel/skylake/chip.c | 2 -- src/soc/intel/tigerlake/chip.c | 2 -- src/soc/intel/xeon_sp/cpx/chip.c | 1 - src/soc/intel/xeon_sp/skx/chip.c | 1 - src/soc/nvidia/tegra210/soc.c | 2 -- src/southbridge/amd/agesa/hudson/pci.c | 1 - src/superio/common/generic.c | 1 - src/vendorcode/google/chromeos/chromeos.h | 2 +- 77 files changed, 1 insertion(+), 92 deletions(-) diff --git a/src/device/root_device.c b/src/device/root_device.c index 8d587dc42e..68a7ae668f 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -129,8 +129,6 @@ static const char *root_dev_acpi_name(const struct device *dev) struct device_operations default_dev_ops_root = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, .scan_bus = scan_static_bus, .reset_bus = root_dev_reset, #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index d026ffd344..97bd37d871 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -57,7 +57,6 @@ static const char *adau7002_acpi_name(const struct device *dev) static struct device_operations adau7002_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = adau7002_acpi_name, .acpi_fill_ssdt = adau7002_fill_ssdt, diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index 5666ee4157..d4de6c7583 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -70,7 +70,6 @@ static const char *generic_dev_acpi_name(const struct device *dev) static struct device_operations generic_dev_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = generic_dev_acpi_name, .acpi_fill_ssdt = generic_dev_fill_ssdt_generator, }; diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index e2310a1c31..5a74c6409b 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -104,7 +104,6 @@ static const char *gpio_keys_acpi_name(const struct device *dev) static struct device_operations gpio_keys_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = gpio_keys_acpi_name, .acpi_fill_ssdt = gpio_keys_fill_ssdt_generator, }; diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 253a2fa633..7041aa0e7c 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -61,7 +61,6 @@ static const char *gpio_regulator_acpi_name(const struct device *dev) static struct device_operations gpio_regulator_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = gpio_regulator_acpi_name, .acpi_fill_ssdt = gpio_regulator_fill_ssdt_generator, }; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index b09e8a6c04..b2c4bb60b1 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -96,7 +96,6 @@ static void ioapic_read_resources(struct device *dev) static struct device_operations ioapic_operations = { .read_resources = ioapic_read_resources, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = ioapic_init, }; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index d1c4978398..0a29367498 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -72,7 +72,6 @@ static const char *max98357a_acpi_name(const struct device *dev) static struct device_operations max98357a_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = max98357a_acpi_name, .acpi_fill_ssdt = max98357a_fill_ssdt, diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index d1c5819c21..3e1a3a5859 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -80,7 +80,6 @@ static void adt7463_init(struct device *adt7463) static struct device_operations adt7463_operations = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = adt7463_init, }; diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 32f702c497..3841d64fd6 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -35,7 +35,6 @@ static void at24rf08c_init(struct device *dev) static struct device_operations at24rf08c_operations = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = at24rf08c_init, }; diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index 23fba474f1..fac5208577 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -48,7 +48,6 @@ static void ck505_init(struct device *dev) static struct device_operations ck505_operations = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = ck505_init, }; diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index eea82ba148..43c6f9d41b 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -100,7 +100,6 @@ static const char *da7219_acpi_name(const struct device *dev) static struct device_operations da7219_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = da7219_acpi_name, .acpi_fill_ssdt = da7219_fill_ssdt, diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 3e9da75395..32b984a85f 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -182,7 +182,6 @@ static const char *i2c_generic_acpi_name(const struct device *dev) static struct device_operations i2c_generic_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = i2c_generic_acpi_name, .acpi_fill_ssdt = i2c_generic_fill_ssdt_generator, diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 8a3acf948a..11d9d18298 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -39,7 +39,6 @@ static const char *i2c_hid_acpi_name(const struct device *dev) static struct device_operations i2c_hid_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = i2c_hid_acpi_name, .acpi_fill_ssdt = i2c_hid_fill_ssdt_generator, diff --git a/src/drivers/i2c/lm96000/lm96000.c b/src/drivers/i2c/lm96000/lm96000.c index dcb5b41f9c..54d2b88e7c 100644 --- a/src/drivers/i2c/lm96000/lm96000.c +++ b/src/drivers/i2c/lm96000/lm96000.c @@ -207,7 +207,6 @@ static void lm96000_init(struct device *const dev) static struct device_operations lm96000_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = lm96000_init, }; diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 257156b0f4..c6fa2e48d4 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -77,7 +77,6 @@ static const char *max98373_acpi_name(const struct device *dev) static struct device_operations max98373_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = max98373_acpi_name, .acpi_fill_ssdt = max98373_fill_ssdt, }; diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index f84e8d5197..166a4ef87b 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -73,7 +73,6 @@ static const char *max98927_acpi_name(const struct device *dev) static struct device_operations max98927_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = max98927_acpi_name, .acpi_fill_ssdt = max98927_fill_ssdt, }; diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 5f5b4d526a..0c893a44cb 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -88,7 +88,6 @@ static const char *nau8825_acpi_name(const struct device *dev) static struct device_operations nau8825_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = nau8825_acpi_name, .acpi_fill_ssdt = nau8825_fill_ssdt, diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c index da148092d4..c21b002ba5 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.c +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -22,7 +22,6 @@ static void nct7802y_init(struct device *const dev) static struct device_operations nct7802y_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = nct7802y_init, }; diff --git a/src/drivers/i2c/pca9538/pca9538.c b/src/drivers/i2c/pca9538/pca9538.c index 50f634e055..68283b8006 100644 --- a/src/drivers/i2c/pca9538/pca9538.c +++ b/src/drivers/i2c/pca9538/pca9538.c @@ -41,9 +41,7 @@ static void pca9538_init(struct device *dev) static struct device_operations pca9538_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = pca9538_init, - .final = DEVICE_NOOP }; static void pca9538_enable(struct device *dev) diff --git a/src/drivers/i2c/pcf8523/pcf8523.c b/src/drivers/i2c/pcf8523/pcf8523.c index 3e6af7541c..82945ffe2b 100644 --- a/src/drivers/i2c/pcf8523/pcf8523.c +++ b/src/drivers/i2c/pcf8523/pcf8523.c @@ -120,7 +120,6 @@ static void pcf8523_init(struct device *dev) static struct device_operations pcf8523c_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = pcf8523_init, .final = pcf8523_final }; diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index c4b8f12857..7b3bb56596 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -129,9 +129,7 @@ __weak int mb_adjust_cfg(struct ptn_3460_config *cfg_ptr) static struct device_operations ptn3460_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = ptn3460_init, - .final = DEVICE_NOOP }; static void ptn3460_enable(struct device *dev) diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index dc8410fda9..19ee1f2c22 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -86,7 +86,6 @@ static const char *rt1011_acpi_name(const struct device *dev) static struct device_operations rt1011_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = rt1011_acpi_name, .acpi_fill_ssdt = rt1011_fill_ssdt, }; diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index f6d023d522..0e4bab03cc 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -77,7 +77,6 @@ static const char *rt5663_acpi_name(const struct device *dev) static struct device_operations rt5663_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = rt5663_acpi_name, .acpi_fill_ssdt = rt5663_fill_ssdt, }; diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 2cefe6b7da..5dffdc8000 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -227,7 +227,6 @@ static void rtd2132_init(struct device *dev) static struct device_operations rtd2132_operations = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = rtd2132_init, }; diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index e9abe6266f..c691965f9d 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -167,7 +167,6 @@ static void rx6110sa_init(struct device *dev) static struct device_operations rx6110sa_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = rx6110sa_init, .final = rx6110sa_final }; diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 5524395010..e1fe104fe8 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -81,7 +81,6 @@ static const char *i2c_sx9310_acpi_name(const struct device *dev) static struct device_operations i2c_sx9310_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = i2c_sx9310_acpi_name, .acpi_fill_ssdt = i2c_sx9310_fill_ssdt, }; diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 2373069437..eeccb7d30d 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -64,7 +64,6 @@ static const char *i2c_tpm_acpi_name(const struct device *dev) static struct device_operations i2c_tpm_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = i2c_tpm_acpi_name, .acpi_fill_ssdt = i2c_tpm_fill_ssdt, }; diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 8cf5d87b20..c52cbb24da 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -294,7 +294,6 @@ static void w83793_init(struct device *dev) static struct device_operations w83793_operations = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = w83793_init, }; diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index d7740a4d6f..66e232d51a 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -32,7 +32,6 @@ static void ish_fill_ssdt_generator(struct device *dev) static struct device_operations intel_ish_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_fill_ssdt = ish_fill_ssdt_generator, }; diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 0d8c10e7ae..41a6eb588e 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -70,7 +70,6 @@ static const char *camera_acpi_name(const struct device *dev) static struct device_operations camera_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = camera_acpi_name, .acpi_fill_ssdt = camera_fill_ssdt, }; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 2ab137e937..7f39135d6d 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -347,7 +347,6 @@ static void ipmi_read_resources(struct device *dev) static struct device_operations ops = { .read_resources = ipmi_read_resources, .set_resources = ipmi_set_resources, - .enable_resources = DEVICE_NOOP, .init = ipmi_kcs_init, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = ipmi_write_acpi_tables, diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index fc5feea860..ebdd4099fa 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -192,7 +192,6 @@ static const char *spi_acpi_name(const struct device *dev) static struct device_operations spi_acpi_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .acpi_name = spi_acpi_name, .acpi_fill_ssdt = spi_acpi_fill_ssdt_generator, }; diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index d6dc46f180..13f37fa4e2 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -72,7 +72,6 @@ static void usb_acpi_fill_ssdt_generator(struct device *dev) static struct device_operations usb_acpi_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .scan_bus = scan_static_bus, .acpi_fill_ssdt = usb_acpi_fill_ssdt_generator, }; diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 8eebfa8c3a..a022fa7580 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -123,7 +123,6 @@ static void ene932_init(struct device *dev) static struct device_operations ops = { .init = ene932_init, .read_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index dd78922d00..c34082c56b 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -438,7 +438,6 @@ static void lpc_ec_read_resources(struct device *dev) static struct device_operations ops = { .init = lpc_ec_init, .read_resources = lpc_ec_read_resources, - .enable_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = google_chromeec_acpi_name, diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 2ce9bf0ad4..f4bea48be4 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -219,7 +219,6 @@ static const char *wilco_ec_acpi_name(const struct device *dev) static struct device_operations ops = { .init = wilco_ec_init, .read_resources = wilco_ec_read_resources, - .enable_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .acpi_fill_ssdt = wilco_ec_fill_ssdt_generator, .acpi_name = wilco_ec_acpi_name, diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 15c04003c3..f6acd218a7 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -133,7 +133,6 @@ static void ene_kb3940q_init(struct device *dev) static struct device_operations ops = { .init = ene_kb3940q_init, .read_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index fd17097d0c..19c07c50a0 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -147,7 +147,6 @@ static void it8518_init(struct device *dev) static struct device_operations ops = { .init = it8518_init, .read_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c index 8f36decd68..02f4c9b9db 100644 --- a/src/ec/roda/it8518/ec.c +++ b/src/ec/roda/it8518/ec.c @@ -36,7 +36,6 @@ static void it8518_init(struct device *dev) static struct device_operations ops = { .init = it8518_init, .read_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index e5df0168c0..7eee0f3f35 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -275,7 +275,6 @@ static void cpu_bus_scan(struct device *bus) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 714597e088..85b3172a2f 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -818,7 +818,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = { static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; @@ -826,7 +825,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 652d8a3532..aa0aca3b6b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -549,7 +549,6 @@ static struct device_operations northbridge_operations = { .read_resources = nb_read_resources, .set_resources = nb_set_resources, .enable_resources = pci_dev_enable_resources, - .init = DEVICE_NOOP, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, }; @@ -762,7 +761,6 @@ static void domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, }; @@ -896,7 +894,6 @@ static void cpu_bus_init(struct device *dev) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 38f3dad864..bdf4058476 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -548,7 +548,6 @@ static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, - .init = DEVICE_NOOP, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, }; @@ -788,7 +787,6 @@ static const char *domain_acpi_name(const struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; @@ -923,7 +921,6 @@ static void cpu_bus_init(struct device *dev) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 5107bf7560..583379cf94 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -543,7 +543,6 @@ static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, - .init = DEVICE_NOOP, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, }; @@ -897,7 +896,6 @@ static void cpu_bus_init(struct device *dev) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 3896ff91f8..9b0c490e77 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -904,7 +904,6 @@ static void cpu_bus_init(struct device *dev) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 4a24d3550a..bab5cdceac 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1260,7 +1260,6 @@ static void cpu_bus_init(struct device *dev) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index e0340da38a..fc1496de9c 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -82,7 +82,6 @@ static void cpu_bus_init(struct device *dev) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, }; diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 4782bff4b4..c54e3353b1 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -228,7 +228,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 6f892681d7..0d94dcf6de 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -484,7 +484,6 @@ static const struct pci_driver mc_driver_hsw __pci_driver = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index eb0d3b1a35..f4df62bad1 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -81,7 +81,6 @@ static void cpu_bus_init(struct device *dev) static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 4fdd282858..a82cd0f941 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -200,7 +200,6 @@ static const struct pci_driver mc_driver __pci_driver = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4144758e9a..12592fcc66 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -255,7 +255,6 @@ static const struct pci_driver mc_driver_ard __pci_driver = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 36f39b0fcd..2c6944cf8a 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -184,7 +184,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 6ec36f7343..ff42369b2c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -461,7 +461,6 @@ static const struct pci_driver mc_driver __pci_driver = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 6397631c83..8b49dab356 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -179,7 +179,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, }; diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index ae3ae32626..865dad875a 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -21,7 +21,6 @@ extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = picasso_init_cpus, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index dec409f060..f17eccd487 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -128,7 +128,6 @@ struct device_operations picasso_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .scan_bus = scan_smbus, .acpi_name = i2c_acpi_name, .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 8efe64feca..b27683a6dc 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -26,7 +26,6 @@ extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = stoney_init_cpus, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 3f95be73c3..8ec3555c17 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -112,7 +112,6 @@ struct device_operations stoneyridge_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .scan_bus = scan_smbus, .acpi_name = i2c_acpi_name, .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 512a337d7b..f3adc47a42 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -382,7 +382,6 @@ static void soc_final(struct device *dev) static struct device_operations soc_ops = { .read_resources = soc_read_resources, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = soc_init, .final = soc_final, }; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 2c8737f654..cf4763d67d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -221,7 +221,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 39802dcabb..b51d8c31de 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -23,7 +23,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = baytrail_init_cpus, }; diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d1540f844c..991e30f3de 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -26,7 +26,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = soc_init_cpus }; diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 1cf5ada530..4caa23653d 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -25,7 +25,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = &broadwell_init_cpus, }; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index d3918a360b..e323346a12 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -186,8 +186,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index d21f053b41..dbee2977a2 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -44,7 +44,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = denverton_init_cpus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index d6babc48dc..ce608195f6 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -53,7 +53,6 @@ static struct device_operations uart_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, - .enable = DEVICE_NOOP }; static const struct pci_driver uart_driver __pci_driver = { diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 483e0d6e09..36cd0d15e5 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -142,8 +142,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 6a560270e7..643d8511d4 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -149,8 +149,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c3b22e2e0d..6e471fb2d3 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -97,8 +97,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index f57f51dc7d..b93d1fc2ba 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -149,8 +149,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index ef18e45e9b..5f1dedf497 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -33,7 +33,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = cpx_init_cpus, }; diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 90ae0252e2..fbd13d524c 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -484,7 +484,6 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, .init = xeon_sp_init_cpus, #if CONFIG(HAVE_ACPI_TABLES) /* defined in src/soc/intel/common/block/acpi/acpi.c */ diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index b4f51e8587..5fc1e6a9dd 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -52,8 +52,6 @@ static void soc_read_resources(struct device *dev) static struct device_operations soc_ops = { .read_resources = soc_read_resources, .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, }; static void enable_tegra210_dev(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index cacc59d926..60909fa9df 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -36,7 +36,6 @@ static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = DEVICE_NOOP, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 20ffb3db18..88432ff68d 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -297,7 +297,6 @@ static const char *generic_acpi_name(const struct device *dev) static struct device_operations ops = { .read_resources = generic_read_resources, .set_resources = generic_set_resources, - .enable_resources = DEVICE_NOOP, .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generic_ssdt, diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index d53109ca3b..f7df10f22e 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -72,7 +72,7 @@ void mainboard_chromeos_acpi_generate(void); #if CONFIG(CHROMEOS) void chromeos_dsdt_generator(struct device *dev); #else -#define chromeos_dsdt_generator DEVICE_NOOP +#define chromeos_dsdt_generator NULL #endif enum { From 2f8ba69b0ee5deafa9bad20c2a7b2b4785fcb565 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 5 Apr 2020 14:05:24 +0200 Subject: [PATCH 0937/1463] Replace DEVICE_NOOP with noop_(set|read)_resources `.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/device/root_device.c | 4 ++-- src/drivers/crb/tis.c | 4 ++-- src/drivers/generic/adau7002/adau7002.c | 4 ++-- src/drivers/generic/generic/generic.c | 4 ++-- src/drivers/generic/gpio_keys/gpio_keys.c | 4 ++-- src/drivers/generic/gpio_regulator/gpio_regulator.c | 4 ++-- src/drivers/generic/ioapic/ioapic.c | 2 +- src/drivers/generic/max98357a/max98357a.c | 4 ++-- src/drivers/i2c/adt7463/adt7463.c | 4 ++-- src/drivers/i2c/at24rf08c/at24rf08c.c | 4 ++-- src/drivers/i2c/ck505/ck505.c | 4 ++-- src/drivers/i2c/da7219/da7219.c | 4 ++-- src/drivers/i2c/generic/generic.c | 4 ++-- src/drivers/i2c/hid/hid.c | 4 ++-- src/drivers/i2c/lm96000/lm96000.c | 4 ++-- src/drivers/i2c/max98373/max98373.c | 4 ++-- src/drivers/i2c/max98927/max98927.c | 4 ++-- src/drivers/i2c/nau8825/nau8825.c | 4 ++-- src/drivers/i2c/nct7802y/nct7802y.c | 4 ++-- src/drivers/i2c/pca9538/pca9538.c | 4 ++-- src/drivers/i2c/pcf8523/pcf8523.c | 4 ++-- src/drivers/i2c/ptn3460/ptn3460.c | 4 ++-- src/drivers/i2c/rt1011/rt1011.c | 4 ++-- src/drivers/i2c/rt5663/rt5663.c | 4 ++-- src/drivers/i2c/rtd2132/rtd2132.c | 4 ++-- src/drivers/i2c/rx6110sa/rx6110sa.c | 4 ++-- src/drivers/i2c/sx9310/sx9310.c | 4 ++-- src/drivers/i2c/tpm/chip.c | 4 ++-- src/drivers/i2c/w83793/w83793.c | 4 ++-- src/drivers/intel/ish/ish.c | 4 ++-- src/drivers/intel/mipi_camera/camera.c | 4 ++-- src/drivers/spi/acpi/acpi.c | 4 ++-- src/drivers/usb/acpi/usb_acpi.c | 4 ++-- src/ec/compal/ene932/ec.c | 2 +- src/ec/google/chromeec/ec_lpc.c | 2 +- src/ec/google/wilco/chip.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 2 +- src/ec/quanta/it8518/ec.c | 2 +- src/ec/roda/it8518/ec.c | 2 +- src/include/device/device.h | 4 ++-- src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 4 ++-- src/northbridge/amd/pi/00630F01/northbridge.c | 4 ++-- src/northbridge/amd/pi/00660F01/northbridge.c | 4 ++-- src/northbridge/amd/pi/00730F01/northbridge.c | 4 ++-- src/northbridge/intel/e7505/northbridge.c | 4 ++-- src/northbridge/intel/gm45/northbridge.c | 4 ++-- src/northbridge/intel/haswell/northbridge.c | 4 ++-- src/northbridge/intel/i440bx/northbridge.c | 4 ++-- src/northbridge/intel/i945/northbridge.c | 4 ++-- src/northbridge/intel/ironlake/northbridge.c | 4 ++-- src/northbridge/intel/pineview/northbridge.c | 4 ++-- src/northbridge/intel/sandybridge/northbridge.c | 4 ++-- src/northbridge/intel/x4x/northbridge.c | 4 ++-- src/soc/amd/common/block/smbus/sm.c | 4 ++-- src/soc/amd/picasso/chip.c | 4 ++-- src/soc/amd/picasso/i2c.c | 4 ++-- src/soc/amd/stoneyridge/chip.c | 4 ++-- src/soc/amd/stoneyridge/i2c.c | 4 ++-- src/soc/cavium/cn81xx/soc.c | 2 +- src/soc/intel/apollolake/chip.c | 4 ++-- src/soc/intel/baytrail/chip.c | 4 ++-- src/soc/intel/braswell/chip.c | 4 ++-- src/soc/intel/broadwell/chip.c | 4 ++-- src/soc/intel/cannonlake/chip.c | 4 ++-- src/soc/intel/common/block/p2sb/p2sb.c | 2 +- src/soc/intel/denverton_ns/chip.c | 4 ++-- src/soc/intel/icelake/chip.c | 4 ++-- src/soc/intel/jasperlake/chip.c | 4 ++-- src/soc/intel/skylake/chip.c | 4 ++-- src/soc/intel/tigerlake/chip.c | 4 ++-- src/soc/intel/xeon_sp/cpx/chip.c | 4 ++-- src/soc/intel/xeon_sp/skx/chip.c | 4 ++-- src/soc/nvidia/tegra124/soc.c | 4 ++-- src/soc/nvidia/tegra210/soc.c | 2 +- src/soc/rockchip/rk3288/soc.c | 4 ++-- src/soc/samsung/exynos5250/cpu.c | 4 ++-- src/soc/samsung/exynos5420/cpu.c | 4 ++-- 80 files changed, 150 insertions(+), 150 deletions(-) diff --git a/src/device/root_device.c b/src/device/root_device.c index 68a7ae668f..49aa3d8be5 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -127,8 +127,8 @@ static const char *root_dev_acpi_name(const struct device *dev) * of a motherboard can override this if you want non-default behavior. */ struct device_operations default_dev_ops_root = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .scan_bus = scan_static_bus, .reset_bus = root_dev_reset, #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 5c1a6df1cf..bd54bb6b54 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -127,8 +127,8 @@ static const char *crb_tpm_acpi_name(const struct device *dev) } static struct device_operations __unused crb_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = crb_tpm_acpi_name, .acpi_fill_ssdt = crb_tpm_fill_ssdt, diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 97bd37d871..aa47ae6bb9 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -55,8 +55,8 @@ static const char *adau7002_acpi_name(const struct device *dev) #endif static struct device_operations adau7002_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = adau7002_acpi_name, .acpi_fill_ssdt = adau7002_fill_ssdt, diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index d4de6c7583..cee41a538b 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -68,8 +68,8 @@ static const char *generic_dev_acpi_name(const struct device *dev) } static struct device_operations generic_dev_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = generic_dev_acpi_name, .acpi_fill_ssdt = generic_dev_fill_ssdt_generator, }; diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 5a74c6409b..b8e72bf328 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -102,8 +102,8 @@ static const char *gpio_keys_acpi_name(const struct device *dev) } static struct device_operations gpio_keys_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = gpio_keys_acpi_name, .acpi_fill_ssdt = gpio_keys_fill_ssdt_generator, }; diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 7041aa0e7c..0f39910b85 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -59,8 +59,8 @@ static const char *gpio_regulator_acpi_name(const struct device *dev) } static struct device_operations gpio_regulator_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = gpio_regulator_acpi_name, .acpi_fill_ssdt = gpio_regulator_fill_ssdt_generator, }; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index b2c4bb60b1..c8be606458 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -95,7 +95,7 @@ static void ioapic_read_resources(struct device *dev) static struct device_operations ioapic_operations = { .read_resources = ioapic_read_resources, - .set_resources = DEVICE_NOOP, + .set_resources = noop_set_resources, .init = ioapic_init, }; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 0a29367498..599acb5afe 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -70,8 +70,8 @@ static const char *max98357a_acpi_name(const struct device *dev) #endif static struct device_operations max98357a_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = max98357a_acpi_name, .acpi_fill_ssdt = max98357a_fill_ssdt, diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 3e1a3a5859..2fcd54e647 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -78,8 +78,8 @@ static void adt7463_init(struct device *adt7463) } static struct device_operations adt7463_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = adt7463_init, }; diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 3841d64fd6..3511502b76 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -33,8 +33,8 @@ static void at24rf08c_init(struct device *dev) } static struct device_operations at24rf08c_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = at24rf08c_init, }; diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index fac5208577..147776d3f4 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -46,8 +46,8 @@ static void ck505_init(struct device *dev) } static struct device_operations ck505_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = ck505_init, }; diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 43c6f9d41b..4cfeb9fb72 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -98,8 +98,8 @@ static const char *da7219_acpi_name(const struct device *dev) #endif static struct device_operations da7219_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = da7219_acpi_name, .acpi_fill_ssdt = da7219_fill_ssdt, diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 32b984a85f..0466a6fe31 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -180,8 +180,8 @@ static const char *i2c_generic_acpi_name(const struct device *dev) #endif static struct device_operations i2c_generic_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = i2c_generic_acpi_name, .acpi_fill_ssdt = i2c_generic_fill_ssdt_generator, diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 11d9d18298..de43eb9ba5 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -37,8 +37,8 @@ static const char *i2c_hid_acpi_name(const struct device *dev) #endif static struct device_operations i2c_hid_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = i2c_hid_acpi_name, .acpi_fill_ssdt = i2c_hid_fill_ssdt_generator, diff --git a/src/drivers/i2c/lm96000/lm96000.c b/src/drivers/i2c/lm96000/lm96000.c index 54d2b88e7c..b1cf06eca2 100644 --- a/src/drivers/i2c/lm96000/lm96000.c +++ b/src/drivers/i2c/lm96000/lm96000.c @@ -205,8 +205,8 @@ static void lm96000_init(struct device *const dev) } static struct device_operations lm96000_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = lm96000_init, }; diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index c6fa2e48d4..a7df56baa0 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -75,8 +75,8 @@ static const char *max98373_acpi_name(const struct device *dev) } static struct device_operations max98373_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = max98373_acpi_name, .acpi_fill_ssdt = max98373_fill_ssdt, }; diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index 166a4ef87b..0cb80ae88a 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -71,8 +71,8 @@ static const char *max98927_acpi_name(const struct device *dev) } static struct device_operations max98927_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = max98927_acpi_name, .acpi_fill_ssdt = max98927_fill_ssdt, }; diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 0c893a44cb..c3e95e7506 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -86,8 +86,8 @@ static const char *nau8825_acpi_name(const struct device *dev) #endif static struct device_operations nau8825_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = nau8825_acpi_name, .acpi_fill_ssdt = nau8825_fill_ssdt, diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c index c21b002ba5..dd8c0aabc0 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.c +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -20,8 +20,8 @@ static void nct7802y_init(struct device *const dev) } static struct device_operations nct7802y_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = nct7802y_init, }; diff --git a/src/drivers/i2c/pca9538/pca9538.c b/src/drivers/i2c/pca9538/pca9538.c index 68283b8006..b16ca48544 100644 --- a/src/drivers/i2c/pca9538/pca9538.c +++ b/src/drivers/i2c/pca9538/pca9538.c @@ -39,8 +39,8 @@ static void pca9538_init(struct device *dev) } static struct device_operations pca9538_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = pca9538_init, }; diff --git a/src/drivers/i2c/pcf8523/pcf8523.c b/src/drivers/i2c/pcf8523/pcf8523.c index 82945ffe2b..03b6b2269e 100644 --- a/src/drivers/i2c/pcf8523/pcf8523.c +++ b/src/drivers/i2c/pcf8523/pcf8523.c @@ -118,8 +118,8 @@ static void pcf8523_init(struct device *dev) } static struct device_operations pcf8523c_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = pcf8523_init, .final = pcf8523_final }; diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 7b3bb56596..851156fea0 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -127,8 +127,8 @@ __weak int mb_adjust_cfg(struct ptn_3460_config *cfg_ptr) } static struct device_operations ptn3460_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = ptn3460_init, }; diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index 19ee1f2c22..68681ef846 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -84,8 +84,8 @@ static const char *rt1011_acpi_name(const struct device *dev) } static struct device_operations rt1011_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = rt1011_acpi_name, .acpi_fill_ssdt = rt1011_fill_ssdt, }; diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 0e4bab03cc..70c14efc45 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -75,8 +75,8 @@ static const char *rt5663_acpi_name(const struct device *dev) } static struct device_operations rt5663_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = rt5663_acpi_name, .acpi_fill_ssdt = rt5663_fill_ssdt, }; diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 5dffdc8000..74037ccee0 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -225,8 +225,8 @@ static void rtd2132_init(struct device *dev) } static struct device_operations rtd2132_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = rtd2132_init, }; diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index c691965f9d..028058a7e7 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -165,8 +165,8 @@ static void rx6110sa_init(struct device *dev) } static struct device_operations rx6110sa_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = rx6110sa_init, .final = rx6110sa_final }; diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index e1fe104fe8..a4fac10f60 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -79,8 +79,8 @@ static const char *i2c_sx9310_acpi_name(const struct device *dev) } static struct device_operations i2c_sx9310_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = i2c_sx9310_acpi_name, .acpi_fill_ssdt = i2c_sx9310_fill_ssdt, }; diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index eeccb7d30d..b81b0d17c8 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -62,8 +62,8 @@ static const char *i2c_tpm_acpi_name(const struct device *dev) } static struct device_operations i2c_tpm_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = i2c_tpm_acpi_name, .acpi_fill_ssdt = i2c_tpm_fill_ssdt, }; diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index c52cbb24da..822c2cee21 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -292,8 +292,8 @@ static void w83793_init(struct device *dev) } static struct device_operations w83793_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = w83793_init, }; diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 66e232d51a..3daf4915c6 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -30,8 +30,8 @@ static void ish_fill_ssdt_generator(struct device *dev) } static struct device_operations intel_ish_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_fill_ssdt = ish_fill_ssdt_generator, }; diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 41a6eb588e..aabf2bad2d 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -68,8 +68,8 @@ static const char *camera_acpi_name(const struct device *dev) } static struct device_operations camera_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = camera_acpi_name, .acpi_fill_ssdt = camera_fill_ssdt, }; diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index ebdd4099fa..76bddbdfe5 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -190,8 +190,8 @@ static const char *spi_acpi_name(const struct device *dev) } static struct device_operations spi_acpi_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_name = spi_acpi_name, .acpi_fill_ssdt = spi_acpi_fill_ssdt_generator, }; diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 13f37fa4e2..a6a004f760 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -70,8 +70,8 @@ static void usb_acpi_fill_ssdt_generator(struct device *dev) } static struct device_operations usb_acpi_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .scan_bus = scan_static_bus, .acpi_fill_ssdt = usb_acpi_fill_ssdt_generator, }; diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index a022fa7580..93d9154d83 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -122,7 +122,7 @@ static void ene932_init(struct device *dev) static struct device_operations ops = { .init = ene932_init, - .read_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index c34082c56b..232df8e06a 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -438,7 +438,7 @@ static void lpc_ec_read_resources(struct device *dev) static struct device_operations ops = { .init = lpc_ec_init, .read_resources = lpc_ec_read_resources, - .set_resources = DEVICE_NOOP, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = google_chromeec_acpi_name, .acpi_fill_ssdt = google_chromeec_fill_ssdt_generator, diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index f4bea48be4..7de4e0235e 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -219,7 +219,7 @@ static const char *wilco_ec_acpi_name(const struct device *dev) static struct device_operations ops = { .init = wilco_ec_init, .read_resources = wilco_ec_read_resources, - .set_resources = DEVICE_NOOP, + .set_resources = noop_set_resources, .acpi_fill_ssdt = wilco_ec_fill_ssdt_generator, .acpi_name = wilco_ec_acpi_name, }; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index f6acd218a7..4959db1312 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -132,7 +132,7 @@ static void ene_kb3940q_init(struct device *dev) static struct device_operations ops = { .init = ene_kb3940q_init, - .read_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 19c07c50a0..9cb3755f2f 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -146,7 +146,7 @@ static void it8518_init(struct device *dev) static struct device_operations ops = { .init = it8518_init, - .read_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c index 02f4c9b9db..f4a27588dc 100644 --- a/src/ec/roda/it8518/ec.c +++ b/src/ec/roda/it8518/ec.c @@ -35,7 +35,7 @@ static void it8518_init(struct device *dev) static struct device_operations ops = { .init = it8518_init, - .read_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/include/device/device.h b/src/include/device/device.h index 9ba4d3173e..4e9c594bc0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -66,8 +66,8 @@ struct device_operations { /** * Standard device operations function pointers shims. */ -static inline void device_noop(struct device *dev) {} -#define DEVICE_NOOP device_noop +static inline void noop_read_resources(struct device *dev) {} +static inline void noop_set_resources(struct device *dev) {} struct bus { diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 7eee0f3f35..6312d8e7f7 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -273,8 +273,8 @@ static void cpu_bus_scan(struct device *bus) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 85b3172a2f..5826ee16de 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -823,8 +823,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index aa0aca3b6b..57005c7817 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -892,8 +892,8 @@ static void cpu_bus_init(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index bdf4058476..e6b7db4989 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -919,8 +919,8 @@ static void cpu_bus_init(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 583379cf94..1ee951bd1a 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -894,8 +894,8 @@ static void cpu_bus_init(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 9b0c490e77..7de5b464d5 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -902,8 +902,8 @@ static void cpu_bus_init(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index bab5cdceac..8f8c0944b6 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1258,8 +1258,8 @@ static void cpu_bus_init(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index fc1496de9c..03230a53ae 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -80,8 +80,8 @@ static void cpu_bus_init(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, }; diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index c54e3353b1..5f6c8a1c4f 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -226,8 +226,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0d94dcf6de..f7c6883852 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -482,8 +482,8 @@ static const struct pci_driver mc_driver_hsw __pci_driver = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index f4df62bad1..da0107c962 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -79,8 +79,8 @@ static void cpu_bus_init(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpu_bus_init, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index a82cd0f941..94a5abaefa 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -198,8 +198,8 @@ static const struct pci_driver mc_driver __pci_driver = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 12592fcc66..c1ee207bf1 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -253,8 +253,8 @@ static const struct pci_driver mc_driver_ard __pci_driver = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 2c6944cf8a..b24356361f 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -182,8 +182,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ff42369b2c..ea2a737c2c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -459,8 +459,8 @@ static const struct pci_driver mc_driver __pci_driver = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 8b49dab356..054d2aa2ed 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -177,8 +177,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 2863d22326..cef5bbaa23 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -75,8 +75,8 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations smbus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_smbus, diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 865dad875a..7b3e7fba59 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -19,8 +19,8 @@ extern struct device_operations picasso_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = picasso_init_cpus, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index f17eccd487..22c62161f1 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -126,8 +126,8 @@ void i2c_soc_init(void) struct device_operations picasso_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .scan_bus = scan_smbus, .acpi_name = i2c_acpi_name, .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index b27683a6dc..189f48e8e9 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -24,8 +24,8 @@ extern struct device_operations stoneyridge_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = stoney_init_cpus, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 8ec3555c17..1fdb41691c 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -110,8 +110,8 @@ void i2c_soc_init(void) struct device_operations stoneyridge_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .scan_bus = scan_smbus, .acpi_name = i2c_acpi_name, .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index f3adc47a42..60eb225cf1 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -381,7 +381,7 @@ static void soc_final(struct device *dev) static struct device_operations soc_ops = { .read_resources = soc_read_resources, - .set_resources = DEVICE_NOOP, + .set_resources = noop_set_resources, .init = soc_init, .final = soc_final, }; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cf4763d67d..1075642517 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -219,8 +219,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = apollolake_init_cpus, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index b51d8c31de..912347c325 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -21,8 +21,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = baytrail_init_cpus, }; diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 991e30f3de..cb1c37d934 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -24,8 +24,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = soc_init_cpus }; diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 4caa23653d..e81890e899 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -23,8 +23,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = &broadwell_init_cpus, }; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index e323346a12..df9b908813 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -184,8 +184,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 050f95868e..731ce50d4a 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -124,7 +124,7 @@ static void read_resources(struct device *dev) static const struct device_operations device_ops = { .read_resources = read_resources, - .set_resources = DEVICE_NOOP, + .set_resources = noop_set_resources, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index dbee2977a2..fbe2b8264f 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -42,8 +42,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = denverton_init_cpus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 36cd0d15e5..43216e6cc1 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -140,8 +140,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 643d8511d4..7b53e17bd2 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -147,8 +147,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 6e471fb2d3..9df078bad8 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -95,8 +95,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index b93d1fc2ba..073c8d2c69 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -147,8 +147,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 5f1dedf497..196f3df0d1 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -31,8 +31,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = cpx_init_cpus, }; diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index fbd13d524c..be452a05b6 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -482,8 +482,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = xeon_sp_init_cpus, #if CONFIG(HAVE_ACPI_TABLES) /* defined in src/soc/intel/common/block/acpi/acpi.c */ diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 270e5e54e6..1f9f290226 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -42,8 +42,8 @@ static void soc_init(struct device *dev) } static struct device_operations soc_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .enable_resources = soc_enable, .init = soc_init, }; diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 5fc1e6a9dd..f5eb44f4f3 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -51,7 +51,7 @@ static void soc_read_resources(struct device *dev) static struct device_operations soc_ops = { .read_resources = soc_read_resources, - .set_resources = DEVICE_NOOP, + .set_resources = noop_set_resources, }; static void enable_tegra210_dev(struct device *dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index f7f1ec9a88..08b72ea1b5 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -24,8 +24,8 @@ static void soc_init(struct device *dev) } static struct device_operations soc_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .init = soc_init, }; diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 8b087c9107..8278b1ebfb 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -112,8 +112,8 @@ static void cpu_init(struct device *dev) } static struct device_operations cpu_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .enable_resources = cpu_enable, .init = cpu_init, }; diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index dd27730dc1..4bb03f2549 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -142,8 +142,8 @@ static void cpu_init(struct device *dev) } static struct device_operations cpu_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, .enable_resources = cpu_enable, .init = cpu_init, }; From 7eed98ac88f15b6b81695275858da7cd5c8d7a98 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 Apr 2020 17:46:28 +0200 Subject: [PATCH 0938/1463] util/nvramtool: Remove 2nd initialization 'result' is already defined as 'unsigned long long result = 0;' so no need to re-write 'result = 0;'. Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- util/nvramtool/cmos_lowlevel.c | 1 - 1 file changed, 1 deletion(-) diff --git a/util/nvramtool/cmos_lowlevel.c b/util/nvramtool/cmos_lowlevel.c index eadda62ce8..32406ecd1a 100644 --- a/util/nvramtool/cmos_lowlevel.c +++ b/util/nvramtool/cmos_lowlevel.c @@ -121,7 +121,6 @@ unsigned long long cmos_read(const cmos_entry_t * e) unsigned char value; assert(!verify_cmos_op(bit, length, e->config)); - result = 0; if (e->config == CMOS_ENTRY_STRING) { int strsz = (length + 7) / 8 + 1; From 4d319c3d0965042ae6b225d4cc391e00789d7565 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Apr 2020 13:51:13 +0200 Subject: [PATCH 0939/1463] src/ec: Add missing "set_resources = noop_set_resources" Change-Id: I4acfb9d9911e251a494b6d35d76226c06e7858d6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40256 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/ec/compal/ene932/ec.c | 1 + src/ec/quanta/ene_kb3940q/ec.c | 1 + src/ec/quanta/it8518/ec.c | 1 + src/ec/roda/it8518/ec.c | 1 + 4 files changed, 4 insertions(+) diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 93d9154d83..f0d83a7c28 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -123,6 +123,7 @@ static void ene932_init(struct device *dev) static struct device_operations ops = { .init = ene932_init, .read_resources = noop_read_resources, + .set_resources = noop_set_resources, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 4959db1312..db1a04bf23 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -133,6 +133,7 @@ static void ene_kb3940q_init(struct device *dev) static struct device_operations ops = { .init = ene_kb3940q_init, .read_resources = noop_read_resources, + .set_resources = noop_set_resources, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 9cb3755f2f..bd82ecc5fe 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -147,6 +147,7 @@ static void it8518_init(struct device *dev) static struct device_operations ops = { .init = it8518_init, .read_resources = noop_read_resources, + .set_resources = noop_set_resources, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c index f4a27588dc..07b61f5154 100644 --- a/src/ec/roda/it8518/ec.c +++ b/src/ec/roda/it8518/ec.c @@ -36,6 +36,7 @@ static void it8518_init(struct device *dev) static struct device_operations ops = { .init = it8518_init, .read_resources = noop_read_resources, + .set_resources = noop_set_resources, }; static struct pnp_info pnp_dev_info[] = { From e6d1c7fae87e7bdf869c59a09c16284b6a9dfccb Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Wed, 8 Apr 2020 15:43:03 +0800 Subject: [PATCH 0940/1463] spi: add Winbond W25Q64JW spi rom support BUG=b:153515968 TEST=Able to boot to kernel Signed-off-by: Scott Chao Change-Id: I699f6d7ba3af01436f10c9a59af4a22fc45aa300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40270 Reviewed-by: Yu-Ping Wu Reviewed-by: Hung-Te Lin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/spi/winbond.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index f1aa1c4186..9029dc442d 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -173,6 +173,14 @@ static const struct spi_flash_part_id flash_table[] = { .protection_granularity_shift = 17, .bp_bits = 3, }, + { + /* W25Q64JW */ + .id[0] = 0x8017, + .nr_sectors_shift = 11, + .fast_read_dual_output_support = 1, + .protection_granularity_shift = 17, + .bp_bits = 3, + }, { /* W25Q128_V */ .id[0] = 0x4018, From ea9787a6b29821e95aa382e1df1ba397cf3da9e9 Mon Sep 17 00:00:00 2001 From: Morgan Jang Date: Thu, 9 Apr 2020 13:50:43 +0800 Subject: [PATCH 0941/1463] drivers/ipmi: Implement the function for logging system events into BMC Implemented for functions that need to log system events into BMC, the information of system events can be specific. TEST=Use ipmitool and execute "ipmitool sel list" command to check if SEL is added into BMC. Change-Id: I38f3acb958d12c196d33d34fd5cfa0b784f403b7 Signed-off-by: Morgan Jang Reviewed-on: https://review.coreboot.org/c/coreboot/+/40286 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov Reviewed-by: Paul Menzel --- src/drivers/ipmi/ipmi_kcs.h | 1 + src/drivers/ipmi/ipmi_ops.c | 22 ++++++++++++++++++++ src/drivers/ipmi/ipmi_ops.h | 40 +++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index d511edfd4f..44f668d149 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -21,6 +21,7 @@ #define IPMI_NETFN_FIRMWARE 0x08 #define IPMI_NETFN_STORAGE 0x0a #define IPMI_READ_FRU_DATA 0x11 +#define IPMI_ADD_SEL_ENTRY 0x44 #define IPMI_NETFN_TRANSPORT 0x0c #define IPMI_CMD_ACPI_POWERON 0x06 diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index 25bf077aef..2a52ba0ec3 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -118,3 +118,25 @@ enum cb_err ipmi_get_system_guid(const int port, uint8_t *uuid) memcpy(uuid, rsp.data, 16); return CB_SUCCESS; } + +enum cb_err ipmi_add_sel(const int port, struct sel_event_record *sel) +{ + int ret; + struct ipmi_add_sel_rsp rsp; + + if (sel == NULL) { + printk(BIOS_ERR, "%s failed, system evnt log is not present.\n", __func__); + return CB_ERR; + } + + ret = ipmi_kcs_message(port, IPMI_NETFN_STORAGE, 0x0, + IPMI_ADD_SEL_ENTRY, (const unsigned char *) sel, + 16, (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index f88959544b..e6e6b77548 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -50,6 +50,42 @@ struct ipmi_read_fru_data_rsp { uint8_t data[CONFIG_IPMI_FRU_SINGLE_RW_SZ]; } __packed; +struct standard_spec_sel_rec { + uint32_t timestamp; + uint16_t gen_id; + uint8_t evm_rev; + uint8_t sensor_type; + uint8_t sensor_num; + uint8_t event_dir_type; + uint8_t event_data[3]; +}; + +struct oem_ts_spec_sel_rec { + uint32_t timestamp; + uint8_t manf_id[3]; + uint8_t oem_defined[6]; +}; + +struct oem_nots_spec_sel_rec { + uint8_t oem_defined[13]; +}; + +/* SEL Event Record */ +struct sel_event_record { + uint16_t record_id; + uint8_t record_type; + union{ + struct standard_spec_sel_rec standard_type; + struct oem_ts_spec_sel_rec oem_ts_type; + struct oem_nots_spec_sel_rec oem_nots_type; + } sel_type; +} __packed; + +struct ipmi_add_sel_rsp { + struct ipmi_rsp resp; + uint16_t record_id; +} __packed; + /* Platform Management FRU Information Storage Definition Spec. */ #define PRODUCT_MAN_TYPE_LEN_OFFSET 3 #define BOARD_MAN_TYPE_LEN_OFFSET 6 @@ -123,4 +159,8 @@ void read_fru_areas(const int port, uint8_t id, uint16_t offset, /* Read a particular FRU inventory area into fru_info_str. */ void read_fru_one_area(const int port, uint8_t id, uint16_t offset, struct fru_info_str *fru_info_str, enum fru_area fru_area); + +/* Add a SEL record entry, returns CB_SUCCESS on success and CB_ERR + * if an error occurred */ +enum cb_err ipmi_add_sel(const int port, struct sel_event_record *sel); #endif From e9eb4d5df93d9a1b4ced302160b76d252c78ca6a Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 25 Mar 2020 17:37:34 -0600 Subject: [PATCH 0942/1463] mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up of 20K. Retain it during the GPIO pad configuration. BUG=b:150985246 TEST=Boot the mainboard. Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852 Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index a0127370c3..89683bd754 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -372,7 +372,7 @@ static const struct pad_config gpio_table[] = { /* GPD2 : EC_AP_WAKE_ODL */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3 : EC_AP_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4 : AP_SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5 : AP_SLP_S4_L */ From 30ab312322dba872917a96e82e269065c80556c7 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Thu, 2 Apr 2020 15:53:58 +0530 Subject: [PATCH 0943/1463] soc/intel/jasperlake: Publish single GPIO ACPI device Current pin-ctrl kernel v5.4 driver expects the firmware to publish single GPIO ACPI device. Until kernel pin-ctrl driver implementation is updated to consume community based GPIO ACPI device, update the current ACPI code to comply with pin-ctrl driver requirement. BUG=b:150154277 TEST=Verify intel pin-ctrl driver can successfully load in OS Signed-off-by: Aamir Bohra Change-Id: Ifcc92adaee550182ab405541ea85019f31bb8658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39470 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik --- src/soc/intel/jasperlake/acpi/gpio.asl | 100 ++++++++----------------- 1 file changed, 31 insertions(+), 69 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index 2b4aff09c0..f1e4498092 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -1,107 +1,69 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ + +#include #include #include #include -#include #include "gpio_op.asl" -Device (GCM0) +Device (GPIO) { Name (_HID, CROS_GPIO_NAME) Name (_UID, 0) - Name (_DDN, "GPIO Controller Community 0") + Name (_DDN, "GPIO Controller") Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { GPIO_IRQ14 } }) + Method (_CRS, 0, NotSerialized) { + /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) BAS0 = ^^PCRB (PID_GPIOCOM0) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + LEN0 = GPIO_BASE_SIZE -Device (GCM1) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 1) - Name (_DDN, "GPIO Controller Community 1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) BAS1 = ^^PCRB (PID_GPIOCOM1) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + LEN1 = GPIO_BASE_SIZE -Device (GCM4) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 4) - Name (_DDN, "GPIO Controller Community 4") + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) BAS4 = ^^PCRB (PID_GPIOCOM4) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + LEN4 = GPIO_BASE_SIZE -Device (GCM5) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 5) - Name (_DDN, "GPIO Controller Community 5") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 5 */ CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) BAS5 = ^^PCRB (PID_GPIOCOM5) - Return (^RBUF) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) } - Method (_STA) + + Method (_STA, 0, NotSerialized) { Return (0xF) } } - /* * Get GPIO DW0 Address * Arg0 - GPIO Number From d38108f26fec2441d81bf9183137faede323bcb4 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 8 Apr 2020 11:58:33 -0600 Subject: [PATCH 0944/1463] mb/google/dedede: Add Synaptics Touchpad configuration for waddledee TEST=Build and boot the mainboard. Ensure that the touchpad is operational. Change-Id: I937462cd3992a884194bbd1759a0802a147e925a Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/40277 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Tim Wawrzynczak --- .../dedede/variants/waddledee/overridetree.cb | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 388051afa0..ee1abc9f75 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -36,5 +36,17 @@ chip soc/intel/jasperlake }, }" - device domain 0 on end + device domain 0 on + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + end end From cf0d1c31647cf0c935f206cde36abc473265f93d Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 6 Apr 2020 16:02:10 +0530 Subject: [PATCH 0945/1463] soc/intel/jasperlake: Publish EMMC and SD card ACPI devices BUG=b:150872580 TEST=Build waddledoo board. Verify EMMC and SD card ACPI devices are present in dsdt.asl. Change-Id: I70d47455c48990afe9e79c013c5272d70f4f71e7 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39582 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Maulik V Vaghela Reviewed-by: Subrata Banik --- src/soc/intel/jasperlake/acpi/southbridge.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index 6329340392..c0674a0ed7 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -59,3 +59,6 @@ /* PMC Core*/ #include + +/* EMMC/SD card */ +#include "scs.asl" From a0722870a818bec8693911d836ba1bb703d9c676 Mon Sep 17 00:00:00 2001 From: Jake Mannens Date: Thu, 9 Apr 2020 09:40:57 +1000 Subject: [PATCH 0946/1463] mb/lenovo/t420s/devicetree.cb: Fix PCIe port definitions The NEC uPD720200A USB 3.0 controller on the T420s is actually connected to PCIe root port #5 on the PCH, not #7. Enable RP#5, disable RP#7 and update comments accordingly. Test=USB 3.0 controller shows in `lspci` Change-Id: I21ac72fd5632e552bdcdbd573cf92b433ed545ff Signed-off-by: Jake Mannens Reviewed-on: https://review.coreboot.org/c/coreboot/+/40281 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/mainboard/lenovo/t420s/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 2fde40ff9d..1f794c1b24 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -84,9 +84,9 @@ chip northbridge/intel/sandybridge device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 off end # PCIe Port #5 + device pci 1c.4 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 on end # PCIe Port #7 NEC Corporation uPD720200A USB 3.0 Host Controller + device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge From fd8de1860df9487cffb62bb2b657bd6e55b20596 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 31 Mar 2020 21:42:02 +0200 Subject: [PATCH 0947/1463] src/mb: Remove unneeded spaces before/after tabs Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/devicetree.cb | 6 +++--- src/mainboard/amd/south_station/acpi/gpe.asl | 2 +- src/mainboard/amd/south_station/acpi/sleep.asl | 2 +- src/mainboard/amd/south_station/acpi/usb_oc.asl | 2 +- src/mainboard/amd/union_station/acpi/gpe.asl | 2 +- src/mainboard/amd/union_station/acpi/sleep.asl | 2 +- src/mainboard/amd/union_station/acpi/usb_oc.asl | 2 +- src/mainboard/asus/p5qc/variants/p5q/devicetree.cb | 2 +- .../emulation/qemu-aarch64/bootblock_custom.S | 2 +- src/mainboard/google/volteer/acpi/mipi_camera.asl | 2 +- src/mainboard/intel/tglrvp/acpi/mipi_camera.asl | 2 +- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 ++-- .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 ++-- .../lenovo/t400/variants/r500/overridetree.cb | 12 ++++++------ .../lenovo/t400/variants/t400/overridetree.cb | 8 ++++---- .../variants/x11ssm-f/overridetree.cb | 10 +++++----- src/mainboard/system76/lemp9/devicetree.cb | 8 ++++---- 17 files changed, 36 insertions(+), 36 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a98dade9b9..82bbb1fc74 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -107,9 +107,9 @@ chip soc/intel/skylake register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) - register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index fb0db3ab8b..5788140112 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -51,7 +51,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ /* Contains the GPEs for USB overcurrent */ #include "usb_oc.asl" diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl index 5b059d4cbe..0c973a4a0c 100644 --- a/src/mainboard/amd/south_station/acpi/sleep.asl +++ b/src/mainboard/amd/south_station/acpi/sleep.asl @@ -37,7 +37,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl index b38f7fd2a6..27a737c730 100644 --- a/src/mainboard/amd/south_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/south_station/acpi/usb_oc.asl @@ -25,7 +25,7 @@ Name(UOM9, 6) Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index fb0db3ab8b..5788140112 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -51,7 +51,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ /* Contains the GPEs for USB overcurrent */ #include "usb_oc.asl" diff --git a/src/mainboard/amd/union_station/acpi/sleep.asl b/src/mainboard/amd/union_station/acpi/sleep.asl index 5b059d4cbe..0c973a4a0c 100644 --- a/src/mainboard/amd/union_station/acpi/sleep.asl +++ b/src/mainboard/amd/union_station/acpi/sleep.asl @@ -37,7 +37,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl index b38f7fd2a6..27a737c730 100644 --- a/src/mainboard/amd/union_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/union_station/acpi/usb_oc.asl @@ -25,7 +25,7 @@ Name(UOM9, 6) Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index a33533b15a..9899468212 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/x4x # Northbridge device pci 1d.2 on end # USB device pci 1d.7 on end # USB device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge + device pci 1f.0 on # LPC bridge chip superio/winbond/w83667hg-a # Super I/O device pnp 2e.0 on # FDC # Global registers diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S index 50fb0ae873..eb595b9d59 100644 --- a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S +++ b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S @@ -24,7 +24,7 @@ ENTRY(_start) dmb sy /* Calculate relocation offset between bootblock in flash and in DRAM. */ - ldr x0, =_flash + ldr x0, =_flash ldr x1, =_bootblock sub x1, x1, x0 diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/acpi/mipi_camera.asl index 9d24339c07..83d711bfca 100644 --- a/src/mainboard/google/volteer/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/acpi/mipi_camera.asl @@ -290,7 +290,7 @@ Scope (\_SB.PCI0.I2C3) "endpoint", Zero }, - Package (0x02) + Package (0x02) { "clock-lanes", Zero diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 98189c04c1..24fde85c77 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -281,7 +281,7 @@ Scope (\_SB.PCI0.I2C3) "endpoint", Zero }, - Package (0x02) + Package (0x02) { "clock-lanes", Zero diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 6cef4f84a6..501aa2a160 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -154,7 +154,7 @@ chip soc/intel/tigerlake end device pci 12.6 off end # GSPI2 0x34FB device pci 13.0 off end # GSPI3 0xA0FD - device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF chip drivers/intel/wifi @@ -162,7 +162,7 @@ chip soc/intel/tigerlake device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 end - device pci 15.0 on # I2C0 0xA0E8 + device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/max98373 register "vmon_slot_no" = "4" register "imon_slot_no" = "5" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c5cc800224..81d52a8d3d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -150,7 +150,7 @@ chip soc/intel/tigerlake end device pci 12.6 off end # GSPI2 0x34FB device pci 13.0 off end # GSPI3 0xA0FD - device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF chip drivers/intel/wifi @@ -158,7 +158,7 @@ chip soc/intel/tigerlake device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 end - device pci 15.0 on # I2C0 0xA0E8 + device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/max98373 register "vmon_slot_no" = "4" register "imon_slot_no" = "5" diff --git a/src/mainboard/lenovo/t400/variants/r500/overridetree.cb b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb index 65b9387f59..79fe00c07e 100644 --- a/src/mainboard/lenovo/t400/variants/r500/overridetree.cb +++ b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb @@ -5,8 +5,8 @@ chip northbridge/intel/gm45 register "sata_clock_request" = "1" # Enable PCIe ports 1,2,4,5,6 as slots (Mini * PCIe). register "pcie_slot_implemented" = "0x3b" - # Set power limits to 10 * 10^0 watts. - # Maybe we should set less for Mini PCIe. + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. register "pcie_power_limits" = "{ { 41, 0 }, { 41, 0 }, { 0, 0 }, { 41, 0 }, { 41, 0 }, { 41, 0 } }" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 1, 0, 0 }" device pci 19.0 off end # LAN @@ -29,9 +29,9 @@ chip northbridge/intel/gm45 register "eventb_enable" = "0x00" end end - device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x20f9 - ioapic_irq 2 INTC 0x12 + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x20f9 + ioapic_irq 2 INTC 0x12 # eeprom, 4 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -39,7 +39,7 @@ chip northbridge/intel/gm45 device i2c 56 on end device i2c 57 on end end - end + end end end end diff --git a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb index 64cb6db03f..25a47732fc 100644 --- a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb +++ b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb @@ -23,9 +23,9 @@ chip northbridge/intel/gm45 register "has_thinker1" = "0" end end - device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x20f9 - ioapic_irq 2 INTC 0x12 + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x20f9 + ioapic_irq 2 INTC 0x12 # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -37,7 +37,7 @@ chip northbridge/intel/gm45 device i2c 5e on end device i2c 5f on end end - end + end end end end diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 76e684ce4d..80d2305590 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -12,11 +12,11 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0ca1" # IPMI KCS # PCIe configuration - register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 - register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 - register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 - register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 - register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA + register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 + register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 + register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 + register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 + register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA # USB configuration # USB0/1 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 7a6ba6a959..3fa2c170e3 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -74,11 +74,11 @@ chip soc/intel/cannonlake # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 - register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[4]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth @@ -90,7 +90,7 @@ chip soc/intel/cannonlake register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # NC From 3dff32c8041bb6d1ee4b2c5a8681ec0259b46bf6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 30 Mar 2020 17:16:51 +0200 Subject: [PATCH 0948/1463] nb/i945: Improve code formatting Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i945/acpi/i945.asl | 6 +- src/northbridge/intel/i945/bootblock.c | 15 +- src/northbridge/intel/i945/debug.c | 11 +- src/northbridge/intel/i945/early_init.c | 37 ++-- src/northbridge/intel/i945/northbridge.c | 3 +- src/northbridge/intel/i945/raminit.c | 260 +++++++++++++---------- src/northbridge/intel/i945/rcven.c | 21 +- 7 files changed, 185 insertions(+), 168 deletions(-) diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index d4dc1a82e3..a972939929 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -40,9 +40,9 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index d1cf6db17d..edc2170493 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -10,16 +10,13 @@ void bootblock_early_northbridge_init(void) uint32_t reg; /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true. - * That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit + * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final assumption is that + * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index bb00b1414d..181ef5171a 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -10,9 +10,7 @@ void print_pci_devices(void) { pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0, 0, 1)) { + for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || @@ -30,7 +28,8 @@ void dump_pci_device(unsigned int dev) { int i; - printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); + printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, + (dev >> 12) & 7); for (i = 0; i <= 255; i++) { unsigned char val; @@ -46,9 +45,7 @@ void dump_pci_device(unsigned int dev) void dump_pci_devices(void) { pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0, 0, 1)) { + for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d7bc1c6205..ced635a337 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include +#include #include #include -#include -#include -#include #include -#include -#include +#include +#include #include +#include #include #include "i945.h" @@ -41,8 +41,8 @@ static void i945m_detect_chipset(void) case 6: printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express"); break; - default: - printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */ + default: /* Others reserved. */ + printk(BIOS_INFO, "Unknown (%02x)", reg8); } printk(BIOS_INFO, " Chipset\n"); @@ -75,8 +75,8 @@ static void i945m_detect_chipset(void) case 4: printk(BIOS_DEBUG, "DDR2-400"); break; - default: - printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ + default: /* Others reserved. */ + printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); } printk(BIOS_DEBUG, "\n"); @@ -90,7 +90,8 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "\nIntel(R) "); - reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); + reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) + | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); switch (reg8) { case 0: case 1: @@ -125,8 +126,8 @@ static void i945_detect_chipset(void) case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; - default: - printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ + default: /* Others reserved. */ + printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); } printk(BIOS_DEBUG, "\n"); @@ -403,9 +404,9 @@ static void i945_setup_dmi_rcrb(void) reg32 = DMIBAR32(0x204); reg32 &= ~0x3ff; #if 1 - reg32 |= 0x13f; /* for x4 DMI only */ + reg32 |= 0x13f; /* for x4 DMI only */ #else - reg32 |= 0x1e4; /* for x2 DMI only */ + reg32 |= 0x1e4; /* for x2 DMI only */ #endif DMIBAR32(0x204) = reg32; @@ -543,8 +544,7 @@ static void i945_setup_pci_express_x16(void) pci_write_config16(p2peg, PEG_CAP, reg16); /* Setup SLOTCAP */ - /* TODO: These values are mainboard dependent and should - * be set from devicetree.cb. + /* TODO: These values are mainboard dependent and should be set from devicetree.cb. */ /* NOTE: SLOTCAP becomes RO after the first write! */ reg32 = pci_read_config32(p2peg, SLOTCAP); @@ -701,9 +701,8 @@ static void i945_setup_pci_express_x16(void) if (i945_silicon_revision() >= 3) { static const u32 reglist[] = { - 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, - 0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c, - 0xfb0, 0xfc4, 0xfd8, 0xfec + 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, 0xf38, 0xf4c, + 0xf60, 0xf74, 0xf88, 0xf9c, 0xfb0, 0xfc4, 0xfd8, 0xfec }; int i; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 94a5abaefa..3fd3db69df 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -96,8 +96,7 @@ static void mch_domain_read_resources(struct device *dev) delta_cbmem = tomk_stolen - cbmem_topk; tomk_stolen -= delta_cbmem; - printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", - delta_cbmem); + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem); /* The following needs to be 2 lines, otherwise the second diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index db6e3b8e68..f26fac6207 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -263,8 +263,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ - if (!CONFIG(CHECK_SLFRCS_ON_RESUME) - || sysinfo->boot_path != BOOT_PATH_RESUME) { + if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) { MCHBAR8(SLFRCS) |= 3; } else { /* Validate self refresh config */ @@ -300,8 +299,7 @@ struct timings { /** * @brief loop over dimms and save maximal timings */ -static void gather_common_timing(struct sys_info *sysinfo, - struct timings *saved_timings) +static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings) { int i, j; @@ -310,8 +308,8 @@ static void gather_common_timing(struct sys_info *sysinfo, memset(saved_timings, 0, sizeof(*saved_timings)); saved_timings->max_tRR = UINT32_MAX; - saved_timings->cas_mask = SPD_CAS_LATENCY_DDR2_3 - | SPD_CAS_LATENCY_DDR2_4 | SPD_CAS_LATENCY_DDR2_5; + saved_timings->cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 + | SPD_CAS_LATENCY_DDR2_5; /** * i945 supports two DIMMs, in two configurations: @@ -388,8 +386,7 @@ static void gather_common_timing(struct sys_info *sysinfo, if (spd_dimm_is_registered_ddr2(dimm_info.dimm_type)) die("\nError: Registered memory not supported by this chipset\n"); - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), - (i & 1)); + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); /** * There are 5 different possible populations for a DIMM socket: * 0. x16 double ranked (X16DS) @@ -442,8 +439,7 @@ static void gather_common_timing(struct sys_info *sysinfo, die("DDR-II rank size smaller than 128MB is not supported.\n"); sysinfo->banksize[i * 2] = dimm_info.ranksize_mb / 32; - printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, - sysinfo->banksize[i * 2] * 32); + printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); if (dimm_info.ranks == 2) { sysinfo->banksize[(i * 2) + 1] = dimm_info.ranksize_mb / 32; @@ -457,25 +453,18 @@ static void gather_common_timing(struct sys_info *sysinfo, sysinfo->banks[i] = dimm_info.banks; /* int min_tRAS, min_tRP, min_tRCD, min_tWR, min_tRFC; */ - saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, - dimm_info.tRAS); - saved_timings->min_tRP = MAX(saved_timings->min_tRP, - dimm_info.tRP); - saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, - dimm_info.tRCD); - saved_timings->min_tWR = MAX(saved_timings->min_tWR, - dimm_info.tWR); - saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, - dimm_info.tRFC); - saved_timings->max_tRR = MIN(saved_timings->max_tRR, - dimm_info.tRR); + saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, dimm_info.tRAS); + saved_timings->min_tRP = MAX(saved_timings->min_tRP, dimm_info.tRP); + saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, dimm_info.tRCD); + saved_timings->min_tWR = MAX(saved_timings->min_tWR, dimm_info.tWR); + saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, dimm_info.tRFC); + saved_timings->max_tRR = MIN(saved_timings->max_tRR, dimm_info.tRR); saved_timings->cas_mask &= dimm_info.cas_supported; for (j = 0; j < 8; j++) { if (!(saved_timings->cas_mask & (1 << j))) saved_timings->min_tCLK_cas[j] = 0; else - saved_timings->min_tCLK_cas[j] = - MAX(dimm_info.cycle_time[j], + saved_timings->min_tCLK_cas[j] = MAX(dimm_info.cycle_time[j], saved_timings->min_tCLK_cas[j]); } dimm_mask |= (1 << i); @@ -488,14 +477,12 @@ static void gather_common_timing(struct sys_info *sysinfo, printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); } -static void choose_tclk(struct sys_info *sysinfo, - struct timings *saved_timings) +static void choose_tclk(struct sys_info *sysinfo, struct timings *saved_timings) { u32 ctrl_min_tclk; int try_cas; - ctrl_min_tclk = 2 * 256 * 1000 - / sdram_capabilities_max_supported_memory_frequency(); + ctrl_min_tclk = 2 * 256 * 1000 / sdram_capabilities_max_supported_memory_frequency(); normalize_tck(&ctrl_min_tclk); try_cas = spd_get_msbs(saved_timings->cas_mask); @@ -504,8 +491,8 @@ static void choose_tclk(struct sys_info *sysinfo, sysinfo->cas = try_cas; sysinfo->tclk = saved_timings->min_tCLK_cas[try_cas]; if (sysinfo->tclk >= ctrl_min_tclk && - saved_timings->min_tCLK_cas[try_cas] != - saved_timings->min_tCLK_cas[try_cas - 1]) + saved_timings->min_tCLK_cas[try_cas] != + saved_timings->min_tCLK_cas[try_cas - 1]) break; try_cas--; } @@ -539,8 +526,7 @@ static void choose_tclk(struct sys_info *sysinfo, sysinfo->memory_frequency, sysinfo->cas); } -static void derive_timings(struct sys_info *sysinfo, - struct timings *saved_timings) +static void derive_timings(struct sys_info *sysinfo, struct timings *saved_timings) { sysinfo->tras = DIV_ROUND_UP(saved_timings->min_tRAS, sysinfo->tclk); if (sysinfo->tras > 0x18) @@ -961,7 +947,8 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) /* Channel 0 */ sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0)); sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1)); - if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) + if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && + (sysinfo->package == SYSINFO_PACKAGE_STACKED)) sdram_write_slew_rates(G3SRPUT, ctl3220); else @@ -1005,20 +992,26 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { case 400: - channeldll = 0x26262626; break; + channeldll = 0x26262626; + break; case 533: - channeldll = 0x22222222; break; + channeldll = 0x22222222; + break; case 667: - channeldll = 0x11111111; break; + channeldll = 0x11111111; + break; } } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { case 400: - channeldll = 0x33333333; break; + channeldll = 0x33333333; + break; case 533: - channeldll = 0x24242424; break; + channeldll = 0x24242424; + break; case 667: - channeldll = 0x25252525; break; + channeldll = 0x25252525; + break; } } @@ -1054,7 +1047,6 @@ static void sdram_force_rcomp(void) reg8 = i945_silicon_revision(); if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) { - reg32 = MCHBAR32(GBRCOMPCTL); reg32 |= (3 << 5); MCHBAR32(GBRCOMPCTL) = reg32; @@ -1131,14 +1123,14 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo) /* Is channel 0 populated? */ if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) reg32 |= (1 << 7) | (1 << 5); else reg32 |= (1 << 31); /* Is channel 1 populated? */ if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) reg32 |= (1 << 9) | (1 << 8); else reg32 |= (1 << 30); @@ -1147,13 +1139,13 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo) /* Activate DRAM Channel IO Buffers */ if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { reg32 = MCHBAR32(C0DRC1); reg32 |= (1 << 8); MCHBAR32(C0DRC1) = reg32; } if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) { + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) { reg32 = MCHBAR32(C1DRC1); reg32 |= (1 << 8); MCHBAR32(C1DRC1) = reg32; @@ -1232,20 +1224,24 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - columnsrows = (sysinfo->rows[i] & 0x0f) - | (sysinfo->cols[i] & 0xf) << 4; + columnsrows = (sysinfo->rows[i] & 0x0f) | (sysinfo->cols[i] & 0xf) << 4; switch (columnsrows) { case 0x9d: - dra = 2; break; + dra = 2; + break; case 0xad: - dra = 3; break; + dra = 3; + break; case 0xbd: - dra = 4; break; + dra = 4; + break; case 0xae: - dra = 3; break; + dra = 3; + break; case 0xbe: - dra = 4; break; + dra = 4; + break; default: die("Unsupported Rows/Columns. (DRA)"); } @@ -1388,8 +1384,7 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) reg32 &= ~((1 << 13) | (1 << 12)); MCHBAR32(C1DRC0) = reg32; - if (!sysinfo->dual_channel && sysinfo->dimm[1] != - SYSINFO_DIMM_NOT_POPULATED) { + if (!sysinfo->dual_channel && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { reg32 = MCHBAR32(C0DRC0); reg32 |= (1 << 15); MCHBAR32(C0DRC0) = reg32; @@ -1491,7 +1486,7 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) page_size = 1; /* Default: 1k pagesize */ for (i = 0; i < 2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || - sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) + sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) page_size = 2; /* 2k pagesize */ } @@ -1568,13 +1563,13 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Dual Channel Interleaved.\n"); reg32 |= (1 << 1); } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED && - sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { + sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { /* Channel 1 only */ printk(BIOS_DEBUG, "Single Channel 1 only.\n"); reg32 |= (1 << 2); } else if (sdram_capabilities_dual_channel() && - (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) { + (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) { /* Dual Channel Asymmetric */ printk(BIOS_DEBUG, "Dual Channel Asymmetric.\n"); reg32 |= (1 << 0); @@ -1603,11 +1598,14 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo) /* Only write the lower byte */ switch (sysinfo->fsb_frequency) { case 400: - MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */ + MCHBAR8(CPCTL) = 0x90; + break; case 533: - MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */ + MCHBAR8(CPCTL) = 0x95; + break; case 667: - MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */ + MCHBAR8(CPCTL) = 0x8d; + break; } MCHBAR16(CPCTL) &= ~(1 << 11); @@ -1657,11 +1655,14 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) freq = CRCLK_400MHz; /* 1.5V requires 400MHz */ break; case GFX_FREQUENCY_CAP_250MHZ: - freq = CRCLK_250MHz; break; + freq = CRCLK_250MHz; + break; case GFX_FREQUENCY_CAP_200MHZ: - freq = CRCLK_200MHz; break; + freq = CRCLK_200MHz; + break; case GFX_FREQUENCY_CAP_166MHZ: - freq = CRCLK_166MHz; break; + freq = CRCLK_166MHz; + break; } if (freq != CRCLK_400MHz) { @@ -1674,13 +1675,17 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Render: "); switch (freq) { case CRCLK_166MHz: - printk(BIOS_DEBUG, "166MHz"); break; + printk(BIOS_DEBUG, "166MHz"); + break; case CRCLK_200MHz: - printk(BIOS_DEBUG, "200MHz"); break; + printk(BIOS_DEBUG, "200MHz"); + break; case CRCLK_250MHz: - printk(BIOS_DEBUG, "250MHz"); break; + printk(BIOS_DEBUG, "250MHz"); + break; case CRCLK_400MHz: - printk(BIOS_DEBUG, "400MHz"); break; + printk(BIOS_DEBUG, "400MHz"); + break; } if (i945_silicon_revision() == 0) @@ -1697,8 +1702,8 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) u16 fsb = sysinfo->fsb_frequency; if ((fsb == 667 && mem == 533) || - (fsb == 533 && mem == 533) || - (fsb == 533 && mem == 400)) { + (fsb == 533 && mem == 533) || + (fsb == 533 && mem == 400)) { second_vco = 1; } @@ -1764,17 +1769,19 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) if (sysinfo->clkcfg_bit7) { printk(BIOS_DEBUG, "second VCO, "); - clkcfg |= (1 << 7); } switch (sysinfo->memory_frequency) { case 400: - clkcfg |= ((1 + offset) << 4); break; + clkcfg |= ((1 + offset) << 4); + break; case 533: - clkcfg |= ((2 + offset) << 4); break; + clkcfg |= ((2 + offset) << 4); + break; case 667: - clkcfg |= ((3 + offset) << 4); break; + clkcfg |= ((3 + offset) << 4); + break; default: die("Target Memory Frequency Error"); } @@ -1786,9 +1793,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) MCHBAR32(CLKCFG) = clkcfg; - /* Make sure the following code is in the - * cache before we execute it. - */ + /* Make sure the following code is in the cache before we execute it. */ goto cache_code; vco_update: reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); @@ -1929,29 +1934,47 @@ static void sdram_program_clock_crossing(void) printk(BIOS_DEBUG, "MEM="); switch (memclk()) { case 400: - printk(BIOS_DEBUG, "400"); idx += 0; break; + printk(BIOS_DEBUG, "400"); + idx += 0; + break; case 533: - printk(BIOS_DEBUG, "533"); idx += 2; break; + printk(BIOS_DEBUG, "533"); + idx += 2; + break; case 667: - printk(BIOS_DEBUG, "667"); idx += 4; break; + printk(BIOS_DEBUG, "667"); + idx += 4; + break; default: - printk(BIOS_DEBUG, "RSVD %x", memclk()); return; + printk(BIOS_DEBUG, "RSVD %x", memclk()); + return; } printk(BIOS_DEBUG, " FSB="); switch (fsbclk()) { case 400: - printk(BIOS_DEBUG, "400"); idx += 0; break; + printk(BIOS_DEBUG, "400"); + idx += 0; + break; case 533: - printk(BIOS_DEBUG, "533"); idx += 6; break; + printk(BIOS_DEBUG, "533"); + idx += 6; + break; case 667: - printk(BIOS_DEBUG, "667"); idx += 12; break; + printk(BIOS_DEBUG, "667"); + idx += 12; + break; case 800: - printk(BIOS_DEBUG, "800"); idx += 18; break; + printk(BIOS_DEBUG, "800"); + idx += 18; + break; case 1066: - printk(BIOS_DEBUG, "1066"); idx += 24; break; + printk(BIOS_DEBUG, "1066"); + idx += 24; + break; default: - printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return; + printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); + return; } if (command_clock_crossing[idx] == 0xffffffff) @@ -2021,9 +2044,9 @@ static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo) bool chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]); chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]); @@ -2095,7 +2118,6 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo) /* Enable Channel XORing for Dual Channel Interleave */ if (sysinfo->interleaved) { - reg32 = MCHBAR32(DCC); reg32 &= ~(1 << 10); reg32 |= (1 << 9); @@ -2193,16 +2215,20 @@ static void sdram_power_management(struct sys_info *sysinfo) #endif switch (sysinfo->fsb_frequency) { case 667: - MCHBAR32(HGIPMC2) = 0x0d590d59; break; + MCHBAR32(HGIPMC2) = 0x0d590d59; + break; case 533: - MCHBAR32(HGIPMC2) = 0x155b155b; break; + MCHBAR32(HGIPMC2) = 0x155b155b; + break; } } else { switch (sysinfo->fsb_frequency) { case 667: - MCHBAR32(HGIPMC2) = 0x09c409c4; break; + MCHBAR32(HGIPMC2) = 0x09c409c4; + break; case 533: - MCHBAR32(HGIPMC2) = 0x0fa00fa0; break; + MCHBAR32(HGIPMC2) = 0x0fa00fa0; + break; } } @@ -2212,9 +2238,11 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 &= 0xffff0000; switch (sysinfo->fsb_frequency) { case 667: - reg32 |= 0x0600; break; + reg32 |= 0x0600; + break; case 533: - reg32 |= 0x0480; break; + reg32 |= 0x0480; + break; } MCHBAR32(C2C3TT) = reg32; @@ -2222,9 +2250,11 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 &= 0xffff0000; switch (sysinfo->fsb_frequency) { case 667: - reg32 |= 0x0b80; break; + reg32 |= 0x0b80; + break; case 533: - reg32 |= 0x0980; break; + reg32 |= 0x0980; + break; } MCHBAR32(C3C4TT) = reg32; @@ -2318,9 +2348,7 @@ static void sdram_thermal_management(void) MCHBAR8(TCO1) = 0x00; MCHBAR8(TCO0) = 0x00; - /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr - * 0x30/0x32. - */ + /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr 0x30/0x32. */ /* TODO This is not implemented yet. Volunteers? */ } @@ -2331,9 +2359,8 @@ static void sdram_save_receive_enable(void) u32 reg32; u8 values[4]; - /* The following values are stored to an unused CMOS - * area and restored instead of recalculated in case - * of an S3 resume. + /* The following values are stored to an unused CMOS area and restored instead of + * recalculated in case of an S3 resume. * * C0WL0REOST [7:0] -> 8 bit * C1WL0REOST [7:0] -> 8 bit @@ -2429,7 +2456,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo) MCHBAR32(ODTC) = reg32; if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { + sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { printk(BIOS_DEBUG, "one dimm per channel config..\n"); reg32 = MCHBAR32(C0ODT); @@ -2485,10 +2512,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; #if CONFIG(OVERRIDE_CLOCK_DISABLE) - /* Usually system firmware turns off system memory clock signals - * to unused SO-DIMM slots to reduce EMI and power consumption. - * However, the Kontron 986LCD-M does not like unused clock - * signals to be disabled. + /* Usually system firmware turns off system memory clock signals to unused SO-DIMM slots + * to reduce EMI and power consumption. + * However, the Kontron 986LCD-M does not like unused clock signals to be disabled. */ clocks[0] = 0xf; /* force all clock gate pairs to enable */ @@ -2550,11 +2576,14 @@ static void sdram_jedec_enable(struct sys_info *sysinfo) /* Get CAS latency set up */ switch (sysinfo->cas) { case 5: - mrsaddr = MRS_CAS_5; break; + mrsaddr = MRS_CAS_5; + break; case 4: - mrsaddr = MRS_CAS_4; break; + mrsaddr = MRS_CAS_4; + break; case 3: - mrsaddr = MRS_CAS_3; break; + mrsaddr = MRS_CAS_3; + break; default: die("Jedec Error (CAS).\n"); } @@ -2562,11 +2591,14 @@ static void sdram_jedec_enable(struct sys_info *sysinfo) /* Get tWR set */ switch (sysinfo->twr) { case 5: - mrsaddr |= MRS_TWR_5; break; + mrsaddr |= MRS_TWR_5; + break; case 4: - mrsaddr |= MRS_TWR_4; break; + mrsaddr |= MRS_TWR_4; + break; case 3: - mrsaddr |= MRS_TWR_3; break; + mrsaddr |= MRS_TWR_3; + break; default: die("Jedec Error (tWR).\n"); } diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 2271904ed5..84814f7355 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -100,8 +100,7 @@ static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine) return -1; } - set_receive_enable(channel_offset, *mediumcoarse & 3, - *mediumcoarse >> 2); + set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2); MCHBAR8(C0WL0REOST + channel_offset) = *fine; @@ -123,8 +122,7 @@ static int find_preamble(int channel_offset, u8 *mediumcoarse, } *mediumcoarse -= 4; - set_receive_enable(channel_offset, *mediumcoarse & 3, - *mediumcoarse >> 2); + set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2); reg32 = sample_strobes(channel_offset, sysinfo); @@ -155,8 +153,7 @@ static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine) return -1; } - set_receive_enable(channel_offset, *mediumcoarse & 3, - *mediumcoarse >> 2); + set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2); } else { *fine += 0x80; } @@ -176,8 +173,7 @@ static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine, for (;;) { MCHBAR8(C0WL0REOST + channel_offset) = *fine; - set_receive_enable(channel_offset, *mediumcoarse & 3, - *mediumcoarse >> 2); + set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2); rcvenmt = sample_strobes(channel_offset, sysinfo); @@ -210,8 +206,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine, printk(BIOS_SPEW, " %s()\n", __func__); counter = 8; - set_receive_enable(channel_offset, *mediumcoarse & 3, - *mediumcoarse >> 2); + set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2); for (;;) { MCHBAR8(C0WL0REOST + channel_offset) = *fine; @@ -249,8 +244,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine, *fine -= 7; if (*fine >= 0xf9) { *mediumcoarse -= 2; - set_receive_enable(channel_offset, *mediumcoarse & 3, - *mediumcoarse >> 2); + set_receive_enable(channel_offset, *mediumcoarse & 3, *mediumcoarse >> 2); } *fine &= ~(1 << 3); @@ -265,8 +259,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine, * a lot of if ()s so let's just pass 0 or 0x80 for the channel offset. */ -static int receive_enable_autoconfig(int channel_offset, - struct sys_info *sysinfo) +static int receive_enable_autoconfig(int channel_offset, struct sys_info *sysinfo) { u8 mediumcoarse; u8 fine; From 2a203c50efb68e4ddb1bb657ca9ba3f4d0f6d735 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Thu, 9 Apr 2020 11:26:16 +0800 Subject: [PATCH 0949/1463] mb/google/kukui: correct board name Modify board name from "Kadadu" to "Kakadu" BUG=b:153590144 TEST=CPU log show "Starting depthcharge on Kakadu..." BRANCH=kukui Signed-off-by: Scott Chao Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283 Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/kukui/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 82845a8d0d..69c0374e14 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -53,7 +53,7 @@ config MAINBOARD_PART_NUMBER default "Kukui" if BOARD_GOOGLE_KUKUI default "Krane" if BOARD_GOOGLE_KRANE default "Kodama" if BOARD_GOOGLE_KODAMA - default "Kadadu" if BOARD_GOOGLE_KAKADU + default "Kakadu" if BOARD_GOOGLE_KAKADU default "Flapjack" if BOARD_GOOGLE_FLAPJACK default "Jacuzzi" if BOARD_GOOGLE_JACUZZI default "Juniper" if BOARD_GOOGLE_JUNIPER From 32107dffb7013095f45f363fddcf8a3215790199 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 9 Apr 2020 22:23:39 -0600 Subject: [PATCH 0950/1463] ec/google/chromeec: expose failure and unprovisioned SKU id values Provide CROS_SKU_UNKNOWN and CROS_SKU_UNPROVISIONED defintion so callers can utilize the default and failing value without open coding it. BUG=b:153642124 Change-Id: I447004e9016b6ab3306ea532721494ebbcda741d Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/40299 Reviewed-by: Edward O'Callaghan Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec.h | 3 +++ src/ec/google/chromeec/ec_skuid.c | 8 +++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f1caeb09fa..77ba21169e 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -79,6 +79,9 @@ int google_chromeec_cbi_get_fw_config(uint32_t *fw_config); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); +#define CROS_SKU_UNKNOWN 0xFFFFFFFF +#define CROS_SKU_UNPROVISIONED 0x7FFFFFFF +/* Returns CROS_SKU_UNKNOWN on failure. */ uint32_t google_chromeec_get_board_sku(void); const char *google_chromeec_smbios_system_sku(void); diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index 665d425fac..51229758e6 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -12,17 +12,15 @@ #include #include -#define SKU_UNKNOWN 0xFFFFFFFF - uint32_t google_chromeec_get_board_sku(void) { - MAYBE_STATIC_NONZERO uint32_t sku_id = SKU_UNKNOWN; + MAYBE_STATIC_NONZERO uint32_t sku_id = CROS_SKU_UNKNOWN; - if (sku_id != SKU_UNKNOWN) + if (sku_id != CROS_SKU_UNKNOWN) return sku_id; if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; + sku_id = CROS_SKU_UNKNOWN; return sku_id; } From 083379d0f8a8524c4ffc708350c3e2c9fae683af Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 1 Apr 2020 15:56:11 -0700 Subject: [PATCH 0951/1463] vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527 Update FSP headers for Tiger Lake platform generated based FSP version 2527. Which includes below additional UPDs: FSPM: - PchTraceHubMode - CpuTraceHubMode - CpuPcieRpEnableMask FSPS: - D3HotEnable - D3ColdEnable - RtcMemoryLock - PchLockDownGlobalSmi - PchLockDownBiosInterface - PchUnlockGpioPads - CpuMpPpi - ThcPort0Assignment - ThcPort1Assignment BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026 Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/tigerlake/FspUpd.h | 2 +- .../intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 104 ++++++++------ .../intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 128 ++++++++++++++---- 3 files changed, 168 insertions(+), 66 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h index 0c910f3d93..58f4e39d78 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index b27514c644..cc44a2a96f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -259,7 +259,18 @@ typedef struct { /** Offset 0x014D - Reserved **/ - UINT8 Reserved3[14]; + UINT8 Reserved3[4]; + +/** Offset 0x0151 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x0152 - Reserved +**/ + UINT8 Reserved4[9]; /** Offset 0x015B - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set @@ -269,7 +280,7 @@ typedef struct { /** Offset 0x015C - Reserved **/ - UINT8 Reserved4[4]; + UINT8 Reserved5[4]; /** Offset 0x0160 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -326,7 +337,7 @@ typedef struct { /** Offset 0x018B - Reserved **/ - UINT8 Reserved5; + UINT8 Reserved6; /** Offset 0x018C - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -337,7 +348,7 @@ typedef struct { /** Offset 0x018D - Reserved **/ - UINT8 Reserved6[3]; + UINT8 Reserved7[3]; /** Offset 0x0190 - SA GV System Agent dynamic frequency support and when enabled memory will be training @@ -348,7 +359,7 @@ typedef struct { /** Offset 0x0191 - Reserved **/ - UINT8 Reserved7[2]; + UINT8 Reserved8[2]; /** Offset 0x0193 - Rank Margin Tool Enable/disable Rank Margin Tool. @@ -390,7 +401,7 @@ typedef struct { /** Offset 0x019C - Reserved **/ - UINT8 Reserved8[2]; + UINT8 Reserved9[2]; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -400,7 +411,7 @@ typedef struct { /** Offset 0x019F - Reserved **/ - UINT8 Reserved9[22]; + UINT8 Reserved10[22]; /** Offset 0x01B5 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -414,9 +425,16 @@ typedef struct { **/ UINT8 PchIshEnable; -/** Offset 0x01B7 - Reserved +/** Offset 0x01B7 - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode **/ - UINT8 Reserved10[166]; + UINT8 CpuTraceHubMode; + +/** Offset 0x01B8 - Reserved +**/ + UINT8 Reserved11[165]; /** Offset 0x025D - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;1: Enable. @@ -426,7 +444,17 @@ typedef struct { /** Offset 0x0263 - Reserved **/ - UINT8 Reserved11[6]; + UINT8 Reserved12; + +/** Offset 0x0264 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 CpuPcieRpEnableMask; + +/** Offset 0x0268 - Reserved +**/ + UINT8 Reserved13; /** Offset 0x0269 - RpClockReqMsgEnable **/ @@ -438,7 +466,7 @@ typedef struct { /** Offset 0x026E - Reserved **/ - UINT8 Reserved12[3]; + UINT8 Reserved14[3]; /** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -538,7 +566,7 @@ typedef struct { /** Offset 0x0281 - Reserved **/ - UINT8 Reserved13[126]; + UINT8 Reserved15[126]; /** Offset 0x02FF - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -547,7 +575,7 @@ typedef struct { /** Offset 0x0307 - Reserved **/ - UINT8 Reserved14[22]; + UINT8 Reserved16[22]; /** Offset 0x031D - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM @@ -559,7 +587,7 @@ typedef struct { /** Offset 0x031E - Reserved **/ - UINT8 Reserved15[5]; + UINT8 Reserved17[5]; /** Offset 0x0323 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable @@ -569,7 +597,7 @@ typedef struct { /** Offset 0x0324 - Reserved **/ - UINT8 Reserved16; + UINT8 Reserved18; /** Offset 0x0325 - CPU ratio value CPU ratio value. Valid Range 0 to 63 @@ -578,7 +606,7 @@ typedef struct { /** Offset 0x0326 - Reserved **/ - UINT8 Reserved17[2]; + UINT8 Reserved19[2]; /** Offset 0x0328 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- @@ -589,7 +617,7 @@ typedef struct { /** Offset 0x0329 - Reserved **/ - UINT8 Reserved18; + UINT8 Reserved20; /** Offset 0x032A - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. @@ -599,7 +627,7 @@ typedef struct { /** Offset 0x032B - Reserved **/ - UINT8 Reserved19[31]; + UINT8 Reserved21[31]; /** Offset 0x034A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -613,7 +641,7 @@ typedef struct { /** Offset 0x034C - Reserved **/ - UINT8 Reserved20[4]; + UINT8 Reserved22[4]; /** Offset 0x0350 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -627,7 +655,7 @@ typedef struct { /** Offset 0x0358 - Reserved **/ - UINT8 Reserved21[8]; + UINT8 Reserved23[8]; /** Offset 0x0360 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -641,7 +669,7 @@ typedef struct { /** Offset 0x0368 - Reserved **/ - UINT8 Reserved22[522]; + UINT8 Reserved24[522]; /** Offset 0x0572 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -650,7 +678,7 @@ typedef struct { /** Offset 0x0573 - Reserved **/ - UINT8 Reserved23[4]; + UINT8 Reserved25[4]; /** Offset 0x0577 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -665,7 +693,7 @@ typedef struct { /** Offset 0x0597 - Reserved **/ - UINT8 Reserved24[5]; + UINT8 Reserved26[5]; /** Offset 0x059C - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -688,7 +716,7 @@ typedef struct { /** Offset 0x05A2 - Reserved **/ - UINT8 Reserved25[14]; + UINT8 Reserved27[14]; /** Offset 0x05B0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -698,7 +726,7 @@ typedef struct { /** Offset 0x05B1 - Reserved **/ - UINT8 Reserved26[4]; + UINT8 Reserved28[4]; /** Offset 0x05B5 - MRC Safe Config Enables/Disable MRC Safe Config @@ -744,7 +772,7 @@ typedef struct { /** Offset 0x05BC - Reserved **/ - UINT8 Reserved27[4]; + UINT8 Reserved29[4]; /** Offset 0x05C0 - Early Command Training Enables/Disable Early Command Training @@ -754,7 +782,7 @@ typedef struct { /** Offset 0x05C1 - Reserved **/ - UINT8 Reserved28[109]; + UINT8 Reserved30[109]; /** Offset 0x062E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -764,7 +792,7 @@ typedef struct { /** Offset 0x0630 - Reserved **/ - UINT8 Reserved29[62]; + UINT8 Reserved31[62]; /** Offset 0x066E - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -777,7 +805,7 @@ typedef struct { /** Offset 0x066F - Reserved **/ - UINT8 Reserved30[2]; + UINT8 Reserved32[2]; /** Offset 0x0671 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -787,7 +815,7 @@ typedef struct { /** Offset 0x0672 - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved33[2]; /** Offset 0x0674 - TCSS USB Port Enable Bitmap for per port enabling @@ -796,7 +824,7 @@ typedef struct { /** Offset 0x0675 - Reserved **/ - UINT8 Reserved32[80]; + UINT8 Reserved34[80]; /** Offset 0x06C5 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -807,7 +835,7 @@ typedef struct { /** Offset 0x06C6 - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved35[2]; /** Offset 0x06C8 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -817,7 +845,7 @@ typedef struct { /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved34[122]; + UINT8 Reserved36[122]; /** Offset 0x0743 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -827,7 +855,7 @@ typedef struct { /** Offset 0x0744 - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved37[3]; /** Offset 0x0747 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -836,7 +864,7 @@ typedef struct { /** Offset 0x0749 - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved38[3]; /** Offset 0x074C - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* @@ -856,7 +884,7 @@ typedef struct { /** Offset 0x075D - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved39[3]; /** Offset 0x0760 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -893,7 +921,7 @@ typedef struct { /** Offset 0x0775 - Reserved **/ - UINT8 Reserved38[315]; + UINT8 Reserved40[315]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -914,7 +942,7 @@ typedef struct { /** Offset 0x08B0 **/ - UINT8 UnusedUpdSpace23[6]; + UINT8 UnusedUpdSpace22[6]; /** Offset 0x08B6 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 8ab5878f83..9b8db02fe0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -417,9 +417,15 @@ typedef struct { **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x048E - Reserved +/** Offset 0x048E - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS **/ - UINT8 Reserved16[2]; + UINT8 D3HotEnable; + +/** Offset 0x048F - Reserved +**/ + UINT8 Reserved16; /** Offset 0x0490 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined @@ -430,7 +436,17 @@ typedef struct { /** Offset 0x04B0 - Reserved **/ - UINT8 Reserved17[30]; + UINT8 Reserved17[8]; + +/** Offset 0x04B8 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x04B9 - Reserved +**/ + UINT8 Reserved18[21]; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -444,7 +460,7 @@ typedef struct { /** Offset 0x04D2 - Reserved **/ - UINT8 Reserved18[2]; + UINT8 Reserved19[2]; /** Offset 0x04D4 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable @@ -454,7 +470,7 @@ typedef struct { /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved19[11]; + UINT8 Reserved20[11]; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -464,7 +480,7 @@ typedef struct { /** Offset 0x04E7 - Reserved **/ - UINT8 Reserved20[194]; + UINT8 Reserved21[194]; /** Offset 0x05A9 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -475,7 +491,16 @@ typedef struct { /** Offset 0x05AA - Reserved **/ - UINT8 Reserved21[60]; + UINT8 Reserved22[10]; + +/** Offset 0x05B4 - CpuMpPpi + Pointer for CpuMpPpi +**/ + UINT32 CpuMpPpi; + +/** Offset 0x05B8 - Reserved +**/ + UINT8 Reserved23[46]; /** Offset 0x05E6 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -485,7 +510,7 @@ typedef struct { /** Offset 0x05E7 - Reserved **/ - UINT8 Reserved22[36]; + UINT8 Reserved24[36]; /** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -494,7 +519,7 @@ typedef struct { /** Offset 0x060C - Reserved **/ - UINT8 Reserved23[2]; + UINT8 Reserved25[2]; /** Offset 0x060E - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -518,7 +543,7 @@ typedef struct { /** Offset 0x061C - Reserved **/ - UINT8 Reserved24[2]; + UINT8 Reserved26[2]; /** Offset 0x061E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -529,7 +554,18 @@ typedef struct { /** Offset 0x061F - Reserved **/ - UINT8 Reserved25[75]; + UINT8 Reserved27[2]; + +/** Offset 0x0621 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x0622 - Reserved +**/ + UINT8 Reserved28[72]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -543,16 +579,32 @@ typedef struct { /** Offset 0x069A - Reserved **/ - UINT8 Reserved26[168]; + UINT8 Reserved29[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x075A - Reserved +/** Offset 0x075A - Touch Host Controller Port 0 Assignment + Assign THC Port 0 + 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ - UINT8 Reserved27[86]; + UINT8 ThcPort0Assignment; + +/** Offset 0x075B - Reserved +**/ + UINT8 Reserved30[5]; + +/** Offset 0x0760 - Touch Host Controller Port 1 Assignment + Assign THC Port 1 + 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcPort1Assignment; + +/** Offset 0x0761 - Reserved +**/ + UINT8 Reserved31[79]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -573,7 +625,7 @@ typedef struct { /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved28[98]; + UINT8 Reserved32[98]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -583,7 +635,7 @@ typedef struct { /** Offset 0x085B - Reserved **/ - UINT8 Reserved29[50]; + UINT8 Reserved33[50]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -592,7 +644,7 @@ typedef struct { /** Offset 0x0895 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved34; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -601,7 +653,7 @@ typedef struct { /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved31[72]; + UINT8 Reserved35[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -615,7 +667,7 @@ typedef struct { /** Offset 0x0908 - Reserved **/ - UINT8 Reserved32[16]; + UINT8 Reserved36[16]; /** Offset 0x0918 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time @@ -635,7 +687,7 @@ typedef struct { /** Offset 0x091A - Reserved **/ - UINT8 Reserved33[3]; + UINT8 Reserved37[3]; /** Offset 0x091D - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. @@ -646,7 +698,7 @@ typedef struct { /** Offset 0x091E - Reserved **/ - UINT8 Reserved34[434]; + UINT8 Reserved38[434]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -654,7 +706,7 @@ typedef struct { /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved35[101]; + UINT8 Reserved39[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -672,7 +724,29 @@ typedef struct { /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved36[264]; + UINT8 Reserved40[260]; + +/** Offset 0x0C3E - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x0C3F - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x0C40 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x0C41 - Reserved +**/ + UINT8 Reserved41; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -686,7 +760,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved37[269]; + UINT8 Reserved42[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -694,7 +768,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved38[80]; + UINT8 Reserved43[176]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -709,11 +783,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0E00 +/** Offset 0x0E60 **/ UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0E06 +/** Offset 0x0E66 **/ UINT16 UpdTerminator; } FSPS_UPD; From 9a90a439a2f142ea22ad66584e93b1f309e00dd9 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 2 Apr 2020 19:19:06 -0700 Subject: [PATCH 0952/1463] soc/intel/tigerlake: Disable MrcSafeConfig This change disables MrcSafeConfig option during MRC training. MrcSafeConfig was enabled as part of the early testing. Now with FSP 2527, there is no need to set this config anymore. BUG=b:150357377 BRANCH=master TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106 Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/meminit.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 7823cfe523..86645472aa 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -239,7 +239,6 @@ void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, /* LPDDR4x does not allow interleaved memory */ mem_cfg->DqPinsInterleaved = 0; mem_cfg->ECT = board_cfg->ect; - mem_cfg->MrcSafeConfig = 0x1; read_md_spd(info, &spd_data, &spd_len); mem_cfg->MemorySpdDataLen = spd_len; From 9225fd5040d73f282cc838b716202935ca50a929 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 6 Apr 2020 13:35:18 +0530 Subject: [PATCH 0953/1463] soc/intel/tigerlake: Remove scs.asl Remove EMMC and SD card ACPI devices copied from Ice Lake. Tiger Lake does not support these controllers. BUG=b:151208782 TEST= Build volteer board Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik Reviewed-by: Wonkyu Kim Reviewed-by: Caveh Jalali Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi/scs.asl | 122 --------------------------- 1 file changed, 122 deletions(-) delete mode 100644 src/soc/intel/tigerlake/acpi/scs.asl diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl deleted file mode 100644 index a2d9414ff0..0000000000 --- a/src/soc/intel/tigerlake/acpi/scs.asl +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include - -Scope (\_SB.PCI0) { - - /* - * Clear register 0x1C20/0x4820 - * Arg0 - PCR Port ID - */ - Method(SCSC, 1, Serialized) - { - PCRA (Arg0, 0x1C20, 0x0) - PCRA (Arg0, 0x4820, 0x0) - } - - /* EMMC */ - Device(PEMC) { - Name(_ADR, 0x001A0000) - Name (_DDN, "eMMC Controller") - Name (TEMP, 0) - - OperationRegion(SCSR, PCI_Config, 0x00, 0x100) - Field(SCSR, WordAcc, NoLock, Preserve) { - Offset (0x84), /* PMECTRLSTATUS */ - PMCR, 16, - Offset (0xA2), /* PG_CONFIG */ - , 2, - PGEN, 1, /* PG_ENABLE */ - } - - Method(_INI) { - /* Clear register 0x1C20/0x4820 */ - SCSC (PID_EMMC) - } - - Method(_PS0, 0, Serialized) { - Stall (50) // Sleep 50 us - - Store(0, PGEN) // Disable PG - - /* Clear register 0x1C20/0x4820 */ - SCSC (PID_EMMC) - - /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) - } - - Method(_PS3, 0, Serialized) { - Store(1, PGEN) // Enable PG - - /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) - } - - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0, NotSerialized) - { - Return (0) - } - } - } - - /* SD CARD */ - Device (SDXC) - { - Name (_ADR, 0x00140005) - Name (_DDN, "SD Controller") - Name (TEMP, 0) - - OperationRegion (SDPC, PCI_Config, 0x00, 0x100) - Field (SDPC, WordAcc, NoLock, Preserve) - { - Offset (0x84), /* PMECTRLSTATUS */ - PMCR, 16, - Offset (0xA2), /* PG_CONFIG */ - , 2, - PGEN, 1, /* PG_ENABLE */ - } - - Method(_INI) - { - /* Clear register 0x1C20/0x4820 */ - SCSC (PID_SDX) - } - - Method (_PS0, 0, Serialized) - { - Store (0, PGEN) /* Disable PG */ - - /* Clear register 0x1C20/0x4820 */ - SCSC (PID_SDX) - - /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) - } - - Method (_PS3, 0, Serialized) - { - Store (1, PGEN) /* Enable PG */ - - /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) - } - - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0, NotSerialized) - { - Return (1) - } - } - } /* Device (SDXC) */ -} From d7564dc1b95e0a3a0507ccbc0c7b97e52ec39191 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Fri, 20 Mar 2020 15:44:46 +0530 Subject: [PATCH 0954/1463] mb/intel/jasperlake_rvp: Enable audio Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips connected on I2C0: DA7219 and MAX98373 1. Enable Kconfig to enable I2C drivers for both chips. 2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry for I2C0. 3. Enable audio related GPIO configurations. BUG=None BRANCH=None TEST=Checked that dmic and speaker are functional on Jasper Lake RVP Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695 Reviewed-by: Ronak Kanabar Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/Kconfig | 2 + .../variants/jslrvp/devicetree.cb | 57 ++++++++++++++++--- .../jasperlake_rvp/variants/jslrvp/gpio.c | 52 ++++++++++++++++- 3 files changed, 101 insertions(+), 10 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index c84beff69e..9f0f8cc6ed 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -3,8 +3,10 @@ if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_DA7219 select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_MAX98373 select DRIVERS_USB_ACPI select EC_ACPI select GENERIC_SPD_BIN diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 41921dd46e..76ad831e4c 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -58,7 +58,11 @@ chip soc/intel/jasperlake register "gen3_dec" = "0x00fc0901" register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" # PCIe port 1 for M.2 E-key WLAN register "PcieRpEnable[1]" = "1" @@ -128,6 +132,15 @@ chip soc/intel/jasperlake .speed_mhz = 1, .early_init = 1, }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, }" device domain 0 on @@ -233,14 +246,40 @@ chip soc/intel/jasperlake end device pci 14.5 on end # SDCard device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0000"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C 0 + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # I2C 0 Audio device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index e094966ac5..45ba5efd5b 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -7,7 +7,57 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* ToDo: Fill other gpio configuration */ + + /* Audio related GPIOs */ + /* I2C0_SDA */ + PAD_CFG_NF(GPP_C16, UP_2K, DEEP, NF1), + + /* I2C0_SCL */ + PAD_CFG_NF(GPP_C17, UP_2K, DEEP, NF1), + + /* I2S_MCLK */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* I2S1_SCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* Audio Jack Detection */ + PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, EDGE_BOTH), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S1_RXD */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + + /* I2S1_SFRM */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + + /* I2S1_TXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* DMIC_CLK_1 */ + PAD_CFG_NF(GPP_S2, UP_20K, DEEP, NF2), + + /* DMIC_DATA_1 */ + PAD_CFG_NF(GPP_S3, UP_20K, DEEP, NF2), + + /* DMIC_CLK_0 */ + PAD_CFG_NF(GPP_S6, UP_20K, DEEP, NF2), + + /* DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2), + }; /* Early pad configuration in bootblock */ From da968d5f2eb702aecc8374a36faa7dc583e15f7f Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 6 Apr 2020 16:37:01 +0530 Subject: [PATCH 0955/1463] mb/intel/jasperlake_rvp: Enable S0ix for JSLRVP Enable S0ix from devicetree for JSLRVP TEST= Build, boot JSLRVP and Verified S0ix is working by running "echo freeze > /sys/power/state" from kernel console. Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Paul Menzel Reviewed-by: V Sowmya --- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 76ad831e4c..e8fc451661 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -124,7 +124,7 @@ chip soc/intel/jasperlake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "1" register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, From a67c753d554c730c794726b1b65d07c9c383e264 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sun, 12 Apr 2020 02:17:44 +0200 Subject: [PATCH 0956/1463] soc/amd/picasso/soc_util: add TODO to Dali detection Change-Id: I8ff5a9275d4cdf0049b63cc30b8a1cc376b50f80 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons --- src/soc/amd/picasso/soc_util.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 893ff2570f..7cd050cae6 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -10,6 +10,10 @@ int soc_is_pollock(void) return soc_is_zen_plus() && CONFIG(AMD_FT5); } +/* + * TODO: This detection works for the Dali SKUs used in Chrome-devices, but fails for other + * Dali SKUs, since other Dali SKUs have a Zen+ CPUID and not a Raven2 one. + */ int soc_is_dali(void) { return soc_is_raven2() && CONFIG(AMD_FP5); From d6b7236732d8cc74545849f4b81af1d33e8758e2 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 5 Mar 2020 11:44:24 -0700 Subject: [PATCH 0957/1463] soc/amd/common/psp: Split mailbox support into v1 and v2 Family 17h redefines the PSP command and status, and therefore the steps required to send commands via the mailbox. Convert the existing version into a v1 and add a v2. New Kconfig options allow the soc to choose v1 vs. v2. The v2 PSP begins responding to the mailbox command when the full bit range is written. Define the new mailbox as a union of a u32 and a structure. Additional PSP details may be found in the NDA publication (#55758) AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors Change the existing two soc functions that return pointers to void pointers. BUG=b:153677737 Signed-off-by: Marshall Dawson Signed-off-by: Felix Held Change-Id: I4d358fdae07da471640856f57568059e9487f6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../amd/common/block/include/amdblocks/psp.h | 2 +- src/soc/amd/common/block/psp/Kconfig | 13 ++- src/soc/amd/common/block/psp/Makefile.inc | 11 ++ src/soc/amd/common/block/psp/psp.c | 85 -------------- src/soc/amd/common/block/psp/psp_def.h | 36 ++++-- src/soc/amd/common/block/psp/psp_gen1.c | 93 ++++++++++++++++ src/soc/amd/common/block/psp/psp_gen2.c | 104 ++++++++++++++++++ src/soc/amd/stoneyridge/Kconfig | 2 +- src/soc/amd/stoneyridge/psp.c | 4 +- 9 files changed, 253 insertions(+), 97 deletions(-) create mode 100644 src/soc/amd/common/block/psp/psp_gen1.c create mode 100644 src/soc/amd/common/block/psp/psp_gen2.c diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 36e110867a..53946fb8d2 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -5,7 +5,7 @@ #define __AMD_PSP_H__ /* Get the mailbox base address - specific to family of device. */ -struct psp_mbox *soc_get_mbox_address(void); +void *soc_get_mbox_address(void); /* BIOS-to-PSP functions return 0 if successful, else negative value */ #define PSPSTS_SUCCESS 0 diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 0517a2f33f..9466cc6abd 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -3,7 +3,18 @@ config SOC_AMD_COMMON_BLOCK_PSP default n help This option builds in the Platform Security Processor initialization - functions. + functions. Do not select this directly in SoC code, select + SOC_AMD_COMMON_BLOCK_PSP_GENx instead. + +config SOC_AMD_COMMON_BLOCK_PSP_GEN1 + bool + default n + select SOC_AMD_COMMON_BLOCK_PSP + +config SOC_AMD_COMMON_BLOCK_PSP_GEN2 + bool + default n + select SOC_AMD_COMMON_BLOCK_PSP config SOC_AMD_PSP_SELECTABLE_SMU_FW bool diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 2f5de1df9c..dc9a385e39 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -1,4 +1,15 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c + romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c + ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c + smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index c35f41b20c..22404be6d6 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -6,10 +6,8 @@ #include #include #include -#include #include #include -#include #include #include #include @@ -43,94 +41,11 @@ static const char *status_to_string(int err) } } -static u32 rd_mbox_sts(struct psp_mbox *mbox) -{ - return read32(&mbox->mbox_status); -} - -static void wr_mbox_cmd(struct psp_mbox *mbox, u32 cmd) -{ - write32(&mbox->mbox_command, cmd); -} - -static u32 rd_mbox_cmd(struct psp_mbox *mbox) -{ - return read32(&mbox->mbox_command); -} - -static void wr_mbox_cmd_resp(struct psp_mbox *mbox, void *buffer) -{ - write64(&mbox->cmd_response, (uintptr_t)buffer); -} - static u32 rd_resp_sts(struct mbox_default_buffer *buffer) { return read32(&buffer->header.status); } -static int wait_initialized(struct psp_mbox *mbox) -{ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, PSP_INIT_TIMEOUT); - - do { - if (rd_mbox_sts(mbox) & STATUS_INITIALIZED) - return 0; - } while (!stopwatch_expired(&sw)); - - return -PSPSTS_INIT_TIMEOUT; -} - -static int wait_command(struct psp_mbox *mbox) -{ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); - - do { - if (!rd_mbox_cmd(mbox)) - return 0; - } while (!stopwatch_expired(&sw)); - - return -PSPSTS_CMD_TIMEOUT; -} - -static int send_psp_command(u32 command, void *buffer) -{ - struct psp_mbox *mbox = soc_get_mbox_address(); - if (!mbox) - return -PSPSTS_NOBASE; - - /* check for PSP error conditions */ - if (rd_mbox_sts(mbox) & STATUS_HALT) - return -PSPSTS_HALTED; - - if (rd_mbox_sts(mbox) & STATUS_RECOVERY) - return -PSPSTS_RECOVERY; - - /* PSP must be finished with init and ready to accept a command */ - if (wait_initialized(mbox)) - return -PSPSTS_INIT_TIMEOUT; - - if (wait_command(mbox)) - return -PSPSTS_CMD_TIMEOUT; - - /* set address of command-response buffer and write command register */ - wr_mbox_cmd_resp(mbox, buffer); - wr_mbox_cmd(mbox, command); - - /* PSP clears command register when complete */ - if (wait_command(mbox)) - return -PSPSTS_CMD_TIMEOUT; - - /* check delivery status */ - if (rd_mbox_sts(mbox) & (STATUS_ERROR | STATUS_TERMINATED)) - return -PSPSTS_SEND_ERROR; - - return 0; -} - /* * Print meaningful status to the console. Caller only passes a pointer to a * buffer if it's expected to contain its own status. diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 4b3ca6a352..37755166f0 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -5,6 +5,7 @@ #define __AMD_PSP_DEF_H__ #include +#include /* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 @@ -20,24 +21,42 @@ #define MBOX_BIOS_CMD_SMU_FW2 0x1a #define MBOX_BIOS_CMD_ABORT 0xfe -/* generic PSP interface status */ -#define STATUS_INITIALIZED 0x1 -#define STATUS_ERROR 0x2 -#define STATUS_TERMINATED 0x4 -#define STATUS_HALT 0x8 -#define STATUS_RECOVERY 0x10 +/* generic PSP interface status, v1 */ +#define PSPV1_STATUS_INITIALIZED BIT(0) +#define PSPV1_STATUS_ERROR BIT(1) +#define PSPV1_STATUS_TERMINATED BIT(2) +#define PSPV1_STATUS_HALT BIT(3) +#define PSPV1_STATUS_RECOVERY BIT(4) + +/* generic PSP interface status, v2 */ +#define PSPV2_STATUS_ERROR BIT(30) +#define PSPV2_STATUS_RECOVERY BIT(31) /* psp_mbox consists of hardware registers beginning at PSPx000070 * mbox_command: BIOS->PSP command, cleared by PSP when complete * mbox_status: BIOS->PSP interface status * cmd_response: pointer to command/response buffer */ -struct psp_mbox { +struct pspv1_mbox { u32 mbox_command; u32 mbox_status; u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ } __packed; +struct pspv2_mbox { + union { + u32 val; + struct pspv2_mbox_cmd_fields { + u16 mbox_status; + u8 mbox_command; + u32 reserved:6; + u32 recovery:1; + u32 ready:1; + } __packed fields; + }; + u64 cmd_response; +} __packed; + /* command/response format, BIOS builds this in memory * mbox_buffer_header: generic header * mbox_buffer: command-specific buffer format @@ -70,4 +89,7 @@ struct mbox_cmd_sx_info_buffer { #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */ +/* This command needs to be implemented by the generation specific code. */ +int send_psp_command(u32 command, void *buffer); + #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c new file mode 100644 index 0000000000..0e5aa30154 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include "psp_def.h" + +static u32 rd_mbox_sts(struct pspv1_mbox *mbox) +{ + return read32(&mbox->mbox_status); +} + +static void wr_mbox_cmd(struct pspv1_mbox *mbox, u32 cmd) +{ + write32(&mbox->mbox_command, cmd); +} + +static u32 rd_mbox_cmd(struct pspv1_mbox *mbox) +{ + return read32(&mbox->mbox_command); +} + +static void wr_mbox_cmd_resp(struct pspv1_mbox *mbox, void *buffer) +{ + write64(&mbox->cmd_response, (uintptr_t)buffer); +} + +static int wait_initialized(struct pspv1_mbox *mbox) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, PSP_INIT_TIMEOUT); + + do { + if (rd_mbox_sts(mbox) & PSPV1_STATUS_INITIALIZED) + return 0; + } while (!stopwatch_expired(&sw)); + + return -PSPSTS_INIT_TIMEOUT; +} + +static int wait_command(struct pspv1_mbox *mbox) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); + + do { + if (!rd_mbox_cmd(mbox)) + return 0; + } while (!stopwatch_expired(&sw)); + + return -PSPSTS_CMD_TIMEOUT; +} + +int send_psp_command(u32 command, void *buffer) +{ + struct pspv1_mbox *mbox = soc_get_mbox_address(); + if (!mbox) + return -PSPSTS_NOBASE; + + /* check for PSP error conditions */ + if (rd_mbox_sts(mbox) & PSPV1_STATUS_HALT) + return -PSPSTS_HALTED; + + if (rd_mbox_sts(mbox) & PSPV1_STATUS_RECOVERY) + return -PSPSTS_RECOVERY; + + /* PSP must be finished with init and ready to accept a command */ + if (wait_initialized(mbox)) + return -PSPSTS_INIT_TIMEOUT; + + if (wait_command(mbox)) + return -PSPSTS_CMD_TIMEOUT; + + /* set address of command-response buffer and write command register */ + wr_mbox_cmd_resp(mbox, buffer); + wr_mbox_cmd(mbox, command); + + /* PSP clears command register when complete */ + if (wait_command(mbox)) + return -PSPSTS_CMD_TIMEOUT; + + /* check delivery status */ + if (rd_mbox_sts(mbox) & (PSPV1_STATUS_ERROR | PSPV1_STATUS_TERMINATED)) + return -PSPSTS_SEND_ERROR; + + return 0; +} diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c new file mode 100644 index 0000000000..b70babc14a --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include "psp_def.h" + +static u16 rd_mbox_sts(struct pspv2_mbox *mbox) +{ + union { + u32 val; + struct pspv2_mbox_cmd_fields fields; + } tmp = { 0 }; + + tmp.val = read32(&mbox->val); + return tmp.fields.mbox_status; +} + +static void wr_mbox_cmd(struct pspv2_mbox *mbox, u8 cmd) +{ + union { + u32 val; + struct pspv2_mbox_cmd_fields fields; + } tmp = { 0 }; + + /* Write entire 32-bit area to begin command execution */ + tmp.fields.mbox_command = cmd; + write32(&mbox->val, tmp.val); +} + +static u8 rd_mbox_recovery(struct pspv2_mbox *mbox) +{ + union { + u32 val; + struct pspv2_mbox_cmd_fields fields; + } tmp = { 0 }; + + tmp.val = read32(&mbox->val); + return !!tmp.fields.recovery; +} + +static void wr_mbox_cmd_resp(struct pspv2_mbox *mbox, void *buffer) +{ + write64(&mbox->cmd_response, (uintptr_t)buffer); +} + +static int wait_command(struct pspv2_mbox *mbox, bool wait_for_ready) +{ + struct pspv2_mbox and_mask = { .val = ~0 }; + struct pspv2_mbox expected = { .val = 0 }; + struct stopwatch sw; + u32 tmp; + + /* Zero fields from and_mask that should be kept */ + and_mask.fields.mbox_command = 0; + and_mask.fields.ready = wait_for_ready ? 0 : 1; + + /* Expect mbox_cmd == 0 but ready depends */ + if (wait_for_ready) + expected.fields.ready = 1; + + stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); + + do { + tmp = read32(&mbox->val); + tmp &= ~and_mask.val; + if (tmp == expected.val) + return 0; + } while (!stopwatch_expired(&sw)); + + return -PSPSTS_CMD_TIMEOUT; +} + +int send_psp_command(u32 command, void *buffer) +{ + struct pspv2_mbox *mbox = soc_get_mbox_address(); + if (!mbox) + return -PSPSTS_NOBASE; + + if (rd_mbox_recovery(mbox)) + return -PSPSTS_RECOVERY; + + if (wait_command(mbox, true)) + return -PSPSTS_CMD_TIMEOUT; + + /* set address of command-response buffer and write command register */ + wr_mbox_cmd_resp(mbox, buffer); + wr_mbox_cmd(mbox, command); + + /* PSP clears command register when complete. All commands except + * SxInfo set the Ready bit. */ + if (wait_command(mbox, command != MBOX_BIOS_CMD_SX_INFO)) + return -PSPSTS_CMD_TIMEOUT; + + /* check delivery status */ + if (rd_mbox_sts(mbox)) + return -PSPSTS_SEND_ERROR; + + return 0; +} diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 14615888e3..d73f3153e8 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -47,7 +47,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_PSP + select SOC_AMD_COMMON_BLOCK_PSP_GEN1 select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index bc2d725145..88bd61d4dd 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -30,7 +30,7 @@ void soc_enable_psp_early(void) pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); }; -struct psp_mbox *soc_get_mbox_address(void) +void *soc_get_mbox_address(void) { uintptr_t psp_mmio; @@ -54,5 +54,5 @@ struct psp_mbox *soc_get_mbox_address(void) ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } - return (struct psp_mbox *)(psp_mmio + PSP_MAILBOX_OFFSET); + return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); } From d2d93829bbe121c641973e87da658b2fa8204259 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 16 Mar 2020 20:05:05 -0600 Subject: [PATCH 0958/1463] cpu/x86/smm.h: Add SW SMI for PSP SMM Info Add a definition for a software SMI to allow AMD systems supporting the MboxBiosCmdSmmInfo command to properly initialize the PSP. BUG=b:153677737 Signed-off-by: Marshall Dawson Change-Id: I1d78aabb75cb76178a3606777d6a11f1e8806d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40294 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/cpu/x86/smm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 0b76708343..afa8cf42e8 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -25,6 +25,7 @@ #define APM_CNT_GNVS_UPDATE 0xea #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc +#define APM_CNT_SMMINFO 0xec #define APM_CNT_SMMSTORE 0xed #define APM_CNT_ELOG_GSMI 0xef #define APM_STS 0xb3 From 4ed96f2443f0e15d64df1449ec29af8520d9bfb9 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Sat, 11 Apr 2020 09:14:48 -0600 Subject: [PATCH 0959/1463] ec/google/chromeec: add smbios_mainboard_manufacturer() When EC_GOOGLE_CHROMEEC_SKUID is selected provide an implementation of smbios_mainboard_manufacturer() so the code doesn't need to be duplicated in the mainboards. BUG=b:153767369 Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec_skuid.c | 19 ++++++++++++++++ src/mainboard/google/dedede/board_info.c | 19 ---------------- src/mainboard/google/hatch/mainboard.c | 29 ------------------------ src/mainboard/google/octopus/mainboard.c | 19 ---------------- 4 files changed, 19 insertions(+), 67 deletions(-) delete mode 100644 src/mainboard/google/hatch/mainboard.c diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index 51229758e6..a64d3f9678 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -37,3 +37,22 @@ const char *smbios_system_sku(void) { return google_chromeec_smbios_system_sku(); } + +const char *smbios_mainboard_manufacturer(void) +{ + static char oem_name[32]; + static const char *manuf; + + if (manuf) + return manuf; + + if (google_chromeec_cbi_get_oem_name(&oem_name[0], + ARRAY_SIZE(oem_name)) < 0) { + printk(BIOS_ERR, "Couldn't obtain OEM name from CBI\n"); + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + } else { + manuf = &oem_name[0]; + } + + return manuf; +} diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index d49ae9692a..1d1e069372 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -11,25 +11,6 @@ #include #include -const char *smbios_mainboard_manufacturer(void) -{ - static char oem_name[32]; - static const char *manuf; - - if (manuf) - return manuf; - - if (google_chromeec_cbi_get_oem_name(&oem_name[0], - ARRAY_SIZE(oem_name)) < 0) { - printk(BIOS_ERR, "Couldn't obtain OEM name from CBI\n"); - manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - } else { - manuf = &oem_name[0]; - } - - return manuf; -} - int board_info_get_fw_config(uint32_t *fw_config) { return google_chromeec_cbi_get_fw_config(fw_config); diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c deleted file mode 100644 index 73c3456eec..0000000000 --- a/src/mainboard/google/hatch/mainboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include -#include -#include -#include -#include -#include -#include - -const char *smbios_mainboard_manufacturer(void) -{ - static char oem_name[32]; - static const char *manuf; - - if (manuf) - return manuf; - - if (google_chromeec_cbi_get_oem_name(&oem_name[0], - ARRAY_SIZE(oem_name)) < 0) { - printk(BIOS_INFO, "Couldn't obtain OEM name from CBI\n"); - manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - } else { - manuf = &oem_name[0]; - } - - return manuf; -} diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index e0040f3fb2..00ede2cf60 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -139,25 +139,6 @@ void mainboard_devtree_update(struct device *dev) variant_update_devtree(dev); } -const char *smbios_mainboard_manufacturer(void) -{ - static char oem_name[32]; - static const char *manuf; - - if (manuf) - return manuf; - - if (google_chromeec_cbi_get_oem_name(&oem_name[0], - ARRAY_SIZE(oem_name)) < 0) { - printk(BIOS_ERR, "Couldn't obtain OEM name from CBI\n"); - manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - } else { - manuf = &oem_name[0]; - } - - return manuf; -} - bool __weak variant_ext_usb_status(unsigned int port_type, unsigned int port_id) { /* All externally visible USB ports are present */ From 3907a64a48cb338dfbe85fd2f192ea70d254d3f4 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 1 Apr 2020 12:22:00 -0700 Subject: [PATCH 0960/1463] mb/google/volteer: enable Early Command Training Update memory configuration on Tiger Lake platform to enable Early Command Training. This feature was not supported before FSP v2527. BUG=b:150357377 BRANCH=None TEST= Build and boot volteer Signed-off-by: Srinidhi N Kaushik Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023 Reviewed-by: Dossym Nurmukhanov Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/memory.c | 2 +- src/mainboard/google/volteer/variants/malefor/memory.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index f2c5a5a146..57a2c5e285 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -58,7 +58,7 @@ static const struct lpddr4x_cfg baseboard_memcfg = { [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 0, /* Disable Early Command Training */ + .ect = 1, /* Enable Early Command Training */ }; const struct lpddr4x_cfg *__weak variant_memory_params(void) diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 4e5313db36..e1a4cf0781 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -52,7 +52,7 @@ static const struct lpddr4x_cfg malefor_memcfg = { [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 0, /* Disable Early Command Training */ + .ect = 1, /* Enable Early Command Training */ }; const struct lpddr4x_cfg *variant_memory_params(void) From 999001144f050f1b4b2e8debbbd101e74be215ad Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Fri, 27 Mar 2020 13:12:47 -0700 Subject: [PATCH 0961/1463] util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licenses The Linux kernel UAPI header files are licensed under /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ Allows files with this license to be included in coreboot. For more details about this particular license: https://www.kernel.org/doc/html/v4.17/process/license-rules.html https://spdx.org/licenses/Linux-syscall-note.html Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e Signed-off-by: Rajat Jain Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- util/lint/lint-000-license-headers | 1 + 1 file changed, 1 insertion(+) diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 1382d7fe48..c1110ec75d 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -105,6 +105,7 @@ check_for_license 'SPDX-License-Identifier: Apache-2.0' check_for_license 'SPDX-License-Identifier: BSD-3-Clause' check_for_license 'SPDX-License-Identifier: GPL-2.0-only' check_for_license 'SPDX-License-Identifier: GPL-2.0-or-later' +check_for_license 'SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note' check_for_license 'SPDX-License-Identifier: GPL-3.0-only' check_for_license 'SPDX-License-Identifier: GPL-3.0-or-later' check_for_license 'SPDX-License-Identifier: ISC' From 3639f3817126a04a8cede1b92294b67574b25e18 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 1 Apr 2020 15:57:58 -0700 Subject: [PATCH 0962/1463] include/input-event-codes.h: Add Linux input key codes header file Add header file from keycodes from Linux sources. This is needed so that coreboot can provide scancode to keycode mappings in the ACPI that the linux kernel expects (https://lkml.org/lkml/2020/3/24/588) Signed-off-by: Rajat Jain Change-Id: I40051cb63a6c154728887ac9b0521bc671b2a518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40029 Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/include/input-event-codes.h | 952 ++++++++++++++++++++++++++++++++ 1 file changed, 952 insertions(+) create mode 100644 src/include/input-event-codes.h diff --git a/src/include/input-event-codes.h b/src/include/input-event-codes.h new file mode 100644 index 0000000000..006c2627ad --- /dev/null +++ b/src/include/input-event-codes.h @@ -0,0 +1,952 @@ +/* + * This file is copied as-is from include/uapi/linux/input-event-codes.h + * from input maintainer's tree: + * git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git + * from master branch + * at SHA: fbf66796a0aedbaea248c7ade1459ccd0dd4cb44 + */ + +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Input event codes + * + * *** IMPORTANT *** + * This file is not only included from C-code but also from devicetree source + * files. As such this file MUST only contain comments and defines. + * + * Copyright (c) 1999-2002 Vojtech Pavlik + * Copyright (c) 2015 Hans de Goede + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef _UAPI_INPUT_EVENT_CODES_H +#define _UAPI_INPUT_EVENT_CODES_H + +/* + * Device properties and quirks + */ + +#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ +#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ +#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ +#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ +#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ +#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ +#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ + +#define INPUT_PROP_MAX 0x1f +#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) + +/* + * Event types + */ + +#define EV_SYN 0x00 +#define EV_KEY 0x01 +#define EV_REL 0x02 +#define EV_ABS 0x03 +#define EV_MSC 0x04 +#define EV_SW 0x05 +#define EV_LED 0x11 +#define EV_SND 0x12 +#define EV_REP 0x14 +#define EV_FF 0x15 +#define EV_PWR 0x16 +#define EV_FF_STATUS 0x17 +#define EV_MAX 0x1f +#define EV_CNT (EV_MAX+1) + +/* + * Synchronization events. + */ + +#define SYN_REPORT 0 +#define SYN_CONFIG 1 +#define SYN_MT_REPORT 2 +#define SYN_DROPPED 3 +#define SYN_MAX 0xf +#define SYN_CNT (SYN_MAX+1) + +/* + * Keys and buttons + * + * Most of the keys/buttons are modeled after USB HUT 1.12 + * (see http://www.usb.org/developers/hidpage). + * Abbreviations in the comments: + * AC - Application Control + * AL - Application Launch Button + * SC - System Control + */ + +#define KEY_RESERVED 0 +#define KEY_ESC 1 +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_0 11 +#define KEY_MINUS 12 +#define KEY_EQUAL 13 +#define KEY_BACKSPACE 14 +#define KEY_TAB 15 +#define KEY_Q 16 +#define KEY_W 17 +#define KEY_E 18 +#define KEY_R 19 +#define KEY_T 20 +#define KEY_Y 21 +#define KEY_U 22 +#define KEY_I 23 +#define KEY_O 24 +#define KEY_P 25 +#define KEY_LEFTBRACE 26 +#define KEY_RIGHTBRACE 27 +#define KEY_ENTER 28 +#define KEY_LEFTCTRL 29 +#define KEY_A 30 +#define KEY_S 31 +#define KEY_D 32 +#define KEY_F 33 +#define KEY_G 34 +#define KEY_H 35 +#define KEY_J 36 +#define KEY_K 37 +#define KEY_L 38 +#define KEY_SEMICOLON 39 +#define KEY_APOSTROPHE 40 +#define KEY_GRAVE 41 +#define KEY_LEFTSHIFT 42 +#define KEY_BACKSLASH 43 +#define KEY_Z 44 +#define KEY_X 45 +#define KEY_C 46 +#define KEY_V 47 +#define KEY_B 48 +#define KEY_N 49 +#define KEY_M 50 +#define KEY_COMMA 51 +#define KEY_DOT 52 +#define KEY_SLASH 53 +#define KEY_RIGHTSHIFT 54 +#define KEY_KPASTERISK 55 +#define KEY_LEFTALT 56 +#define KEY_SPACE 57 +#define KEY_CAPSLOCK 58 +#define KEY_F1 59 +#define KEY_F2 60 +#define KEY_F3 61 +#define KEY_F4 62 +#define KEY_F5 63 +#define KEY_F6 64 +#define KEY_F7 65 +#define KEY_F8 66 +#define KEY_F9 67 +#define KEY_F10 68 +#define KEY_NUMLOCK 69 +#define KEY_SCROLLLOCK 70 +#define KEY_KP7 71 +#define KEY_KP8 72 +#define KEY_KP9 73 +#define KEY_KPMINUS 74 +#define KEY_KP4 75 +#define KEY_KP5 76 +#define KEY_KP6 77 +#define KEY_KPPLUS 78 +#define KEY_KP1 79 +#define KEY_KP2 80 +#define KEY_KP3 81 +#define KEY_KP0 82 +#define KEY_KPDOT 83 + +#define KEY_ZENKAKUHANKAKU 85 +#define KEY_102ND 86 +#define KEY_F11 87 +#define KEY_F12 88 +#define KEY_RO 89 +#define KEY_KATAKANA 90 +#define KEY_HIRAGANA 91 +#define KEY_HENKAN 92 +#define KEY_KATAKANAHIRAGANA 93 +#define KEY_MUHENKAN 94 +#define KEY_KPJPCOMMA 95 +#define KEY_KPENTER 96 +#define KEY_RIGHTCTRL 97 +#define KEY_KPSLASH 98 +#define KEY_SYSRQ 99 +#define KEY_RIGHTALT 100 +#define KEY_LINEFEED 101 +#define KEY_HOME 102 +#define KEY_UP 103 +#define KEY_PAGEUP 104 +#define KEY_LEFT 105 +#define KEY_RIGHT 106 +#define KEY_END 107 +#define KEY_DOWN 108 +#define KEY_PAGEDOWN 109 +#define KEY_INSERT 110 +#define KEY_DELETE 111 +#define KEY_MACRO 112 +#define KEY_MUTE 113 +#define KEY_VOLUMEDOWN 114 +#define KEY_VOLUMEUP 115 +#define KEY_POWER 116 /* SC System Power Down */ +#define KEY_KPEQUAL 117 +#define KEY_KPPLUSMINUS 118 +#define KEY_PAUSE 119 +#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ + +#define KEY_KPCOMMA 121 +#define KEY_HANGEUL 122 +#define KEY_HANGUEL KEY_HANGEUL +#define KEY_HANJA 123 +#define KEY_YEN 124 +#define KEY_LEFTMETA 125 +#define KEY_RIGHTMETA 126 +#define KEY_COMPOSE 127 + +#define KEY_STOP 128 /* AC Stop */ +#define KEY_AGAIN 129 +#define KEY_PROPS 130 /* AC Properties */ +#define KEY_UNDO 131 /* AC Undo */ +#define KEY_FRONT 132 +#define KEY_COPY 133 /* AC Copy */ +#define KEY_OPEN 134 /* AC Open */ +#define KEY_PASTE 135 /* AC Paste */ +#define KEY_FIND 136 /* AC Search */ +#define KEY_CUT 137 /* AC Cut */ +#define KEY_HELP 138 /* AL Integrated Help Center */ +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_CALC 140 /* AL Calculator */ +#define KEY_SETUP 141 +#define KEY_SLEEP 142 /* SC System Sleep */ +#define KEY_WAKEUP 143 /* System Wake Up */ +#define KEY_FILE 144 /* AL Local Machine Browser */ +#define KEY_SENDFILE 145 +#define KEY_DELETEFILE 146 +#define KEY_XFER 147 +#define KEY_PROG1 148 +#define KEY_PROG2 149 +#define KEY_WWW 150 /* AL Internet Browser */ +#define KEY_MSDOS 151 +#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +#define KEY_SCREENLOCK KEY_COFFEE +#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ +#define KEY_DIRECTION KEY_ROTATE_DISPLAY +#define KEY_CYCLEWINDOWS 154 +#define KEY_MAIL 155 +#define KEY_BOOKMARKS 156 /* AC Bookmarks */ +#define KEY_COMPUTER 157 +#define KEY_BACK 158 /* AC Back */ +#define KEY_FORWARD 159 /* AC Forward */ +#define KEY_CLOSECD 160 +#define KEY_EJECTCD 161 +#define KEY_EJECTCLOSECD 162 +#define KEY_NEXTSONG 163 +#define KEY_PLAYPAUSE 164 +#define KEY_PREVIOUSSONG 165 +#define KEY_STOPCD 166 +#define KEY_RECORD 167 +#define KEY_REWIND 168 +#define KEY_PHONE 169 /* Media Select Telephone */ +#define KEY_ISO 170 +#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +#define KEY_HOMEPAGE 172 /* AC Home */ +#define KEY_REFRESH 173 /* AC Refresh */ +#define KEY_EXIT 174 /* AC Exit */ +#define KEY_MOVE 175 +#define KEY_EDIT 176 +#define KEY_SCROLLUP 177 +#define KEY_SCROLLDOWN 178 +#define KEY_KPLEFTPAREN 179 +#define KEY_KPRIGHTPAREN 180 +#define KEY_NEW 181 /* AC New */ +#define KEY_REDO 182 /* AC Redo/Repeat */ + +#define KEY_F13 183 +#define KEY_F14 184 +#define KEY_F15 185 +#define KEY_F16 186 +#define KEY_F17 187 +#define KEY_F18 188 +#define KEY_F19 189 +#define KEY_F20 190 +#define KEY_F21 191 +#define KEY_F22 192 +#define KEY_F23 193 +#define KEY_F24 194 + +#define KEY_PLAYCD 200 +#define KEY_PAUSECD 201 +#define KEY_PROG3 202 +#define KEY_PROG4 203 +#define KEY_DASHBOARD 204 /* AL Dashboard */ +#define KEY_SUSPEND 205 +#define KEY_CLOSE 206 /* AC Close */ +#define KEY_PLAY 207 +#define KEY_FASTFORWARD 208 +#define KEY_BASSBOOST 209 +#define KEY_PRINT 210 /* AC Print */ +#define KEY_HP 211 +#define KEY_CAMERA 212 +#define KEY_SOUND 213 +#define KEY_QUESTION 214 +#define KEY_EMAIL 215 +#define KEY_CHAT 216 +#define KEY_SEARCH 217 +#define KEY_CONNECT 218 +#define KEY_FINANCE 219 /* AL Checkbook/Finance */ +#define KEY_SPORT 220 +#define KEY_SHOP 221 +#define KEY_ALTERASE 222 +#define KEY_CANCEL 223 /* AC Cancel */ +#define KEY_BRIGHTNESSDOWN 224 +#define KEY_BRIGHTNESSUP 225 +#define KEY_MEDIA 226 + +#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video + outputs (Monitor/LCD/TV-out/etc) */ +#define KEY_KBDILLUMTOGGLE 228 +#define KEY_KBDILLUMDOWN 229 +#define KEY_KBDILLUMUP 230 + +#define KEY_SEND 231 /* AC Send */ +#define KEY_REPLY 232 /* AC Reply */ +#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +#define KEY_SAVE 234 /* AC Save */ +#define KEY_DOCUMENTS 235 + +#define KEY_BATTERY 236 + +#define KEY_BLUETOOTH 237 +#define KEY_WLAN 238 +#define KEY_UWB 239 + +#define KEY_UNKNOWN 240 + +#define KEY_VIDEO_NEXT 241 /* drive next video source */ +#define KEY_VIDEO_PREV 242 /* drive previous video source */ +#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual + brightness control is off, + rely on ambient */ +#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO +#define KEY_DISPLAY_OFF 245 /* display device to off state */ + +#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ +#define KEY_WIMAX KEY_WWAN +#define KEY_RFKILL 247 /* Key that controls all radios */ + +#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ + +/* Code 255 is reserved for special needs of AT keyboard driver */ + +#define BTN_MISC 0x100 +#define BTN_0 0x100 +#define BTN_1 0x101 +#define BTN_2 0x102 +#define BTN_3 0x103 +#define BTN_4 0x104 +#define BTN_5 0x105 +#define BTN_6 0x106 +#define BTN_7 0x107 +#define BTN_8 0x108 +#define BTN_9 0x109 + +#define BTN_MOUSE 0x110 +#define BTN_LEFT 0x110 +#define BTN_RIGHT 0x111 +#define BTN_MIDDLE 0x112 +#define BTN_SIDE 0x113 +#define BTN_EXTRA 0x114 +#define BTN_FORWARD 0x115 +#define BTN_BACK 0x116 +#define BTN_TASK 0x117 + +#define BTN_JOYSTICK 0x120 +#define BTN_TRIGGER 0x120 +#define BTN_THUMB 0x121 +#define BTN_THUMB2 0x122 +#define BTN_TOP 0x123 +#define BTN_TOP2 0x124 +#define BTN_PINKIE 0x125 +#define BTN_BASE 0x126 +#define BTN_BASE2 0x127 +#define BTN_BASE3 0x128 +#define BTN_BASE4 0x129 +#define BTN_BASE5 0x12a +#define BTN_BASE6 0x12b +#define BTN_DEAD 0x12f + +#define BTN_GAMEPAD 0x130 +#define BTN_SOUTH 0x130 +#define BTN_A BTN_SOUTH +#define BTN_EAST 0x131 +#define BTN_B BTN_EAST +#define BTN_C 0x132 +#define BTN_NORTH 0x133 +#define BTN_X BTN_NORTH +#define BTN_WEST 0x134 +#define BTN_Y BTN_WEST +#define BTN_Z 0x135 +#define BTN_TL 0x136 +#define BTN_TR 0x137 +#define BTN_TL2 0x138 +#define BTN_TR2 0x139 +#define BTN_SELECT 0x13a +#define BTN_START 0x13b +#define BTN_MODE 0x13c +#define BTN_THUMBL 0x13d +#define BTN_THUMBR 0x13e + +#define BTN_DIGI 0x140 +#define BTN_TOOL_PEN 0x140 +#define BTN_TOOL_RUBBER 0x141 +#define BTN_TOOL_BRUSH 0x142 +#define BTN_TOOL_PENCIL 0x143 +#define BTN_TOOL_AIRBRUSH 0x144 +#define BTN_TOOL_FINGER 0x145 +#define BTN_TOOL_MOUSE 0x146 +#define BTN_TOOL_LENS 0x147 +#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +#define BTN_STYLUS3 0x149 +#define BTN_TOUCH 0x14a +#define BTN_STYLUS 0x14b +#define BTN_STYLUS2 0x14c +#define BTN_TOOL_DOUBLETAP 0x14d +#define BTN_TOOL_TRIPLETAP 0x14e +#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ + +#define BTN_WHEEL 0x150 +#define BTN_GEAR_DOWN 0x150 +#define BTN_GEAR_UP 0x151 + +#define KEY_OK 0x160 +#define KEY_SELECT 0x161 +#define KEY_GOTO 0x162 +#define KEY_CLEAR 0x163 +#define KEY_POWER2 0x164 +#define KEY_OPTION 0x165 +#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ +#define KEY_TIME 0x167 +#define KEY_VENDOR 0x168 +#define KEY_ARCHIVE 0x169 +#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ +#define KEY_CHANNEL 0x16b +#define KEY_FAVORITES 0x16c +#define KEY_EPG 0x16d +#define KEY_PVR 0x16e /* Media Select Home */ +#define KEY_MHP 0x16f +#define KEY_LANGUAGE 0x170 +#define KEY_TITLE 0x171 +#define KEY_SUBTITLE 0x172 +#define KEY_ANGLE 0x173 +#define KEY_FULL_SCREEN 0x174 /* AC View Toggle */ +#define KEY_ZOOM KEY_FULL_SCREEN +#define KEY_MODE 0x175 +#define KEY_KEYBOARD 0x176 +#define KEY_ASPECT_RATIO 0x177 /* HUTRR37: Aspect */ +#define KEY_SCREEN KEY_ASPECT_RATIO +#define KEY_PC 0x178 /* Media Select Computer */ +#define KEY_TV 0x179 /* Media Select TV */ +#define KEY_TV2 0x17a /* Media Select Cable */ +#define KEY_VCR 0x17b /* Media Select VCR */ +#define KEY_VCR2 0x17c /* VCR Plus */ +#define KEY_SAT 0x17d /* Media Select Satellite */ +#define KEY_SAT2 0x17e +#define KEY_CD 0x17f /* Media Select CD */ +#define KEY_TAPE 0x180 /* Media Select Tape */ +#define KEY_RADIO 0x181 +#define KEY_TUNER 0x182 /* Media Select Tuner */ +#define KEY_PLAYER 0x183 +#define KEY_TEXT 0x184 +#define KEY_DVD 0x185 /* Media Select DVD */ +#define KEY_AUX 0x186 +#define KEY_MP3 0x187 +#define KEY_AUDIO 0x188 /* AL Audio Browser */ +#define KEY_VIDEO 0x189 /* AL Movie Browser */ +#define KEY_DIRECTORY 0x18a +#define KEY_LIST 0x18b +#define KEY_MEMO 0x18c /* Media Select Messages */ +#define KEY_CALENDAR 0x18d +#define KEY_RED 0x18e +#define KEY_GREEN 0x18f +#define KEY_YELLOW 0x190 +#define KEY_BLUE 0x191 +#define KEY_CHANNELUP 0x192 /* Channel Increment */ +#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ +#define KEY_FIRST 0x194 +#define KEY_LAST 0x195 /* Recall Last */ +#define KEY_AB 0x196 +#define KEY_NEXT 0x197 +#define KEY_RESTART 0x198 +#define KEY_SLOW 0x199 +#define KEY_SHUFFLE 0x19a +#define KEY_BREAK 0x19b +#define KEY_PREVIOUS 0x19c +#define KEY_DIGITS 0x19d +#define KEY_TEEN 0x19e +#define KEY_TWEN 0x19f +#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +#define KEY_GAMES 0x1a1 /* Media Select Games */ +#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +#define KEY_DATABASE 0x1aa /* AL Database App */ +#define KEY_NEWS 0x1ab /* AL Newsreader */ +#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ +#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ +#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE +#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ +#define KEY_LOGOFF 0x1b1 /* AL Logoff */ + +#define KEY_DOLLAR 0x1b2 +#define KEY_EURO 0x1b3 + +#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ +#define KEY_FRAMEFORWARD 0x1b5 +#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ +#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ +#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ +#define KEY_IMAGES 0x1ba /* AL Image Browser */ + +#define KEY_DEL_EOL 0x1c0 +#define KEY_DEL_EOS 0x1c1 +#define KEY_INS_LINE 0x1c2 +#define KEY_DEL_LINE 0x1c3 + +#define KEY_FN 0x1d0 +#define KEY_FN_ESC 0x1d1 +#define KEY_FN_F1 0x1d2 +#define KEY_FN_F2 0x1d3 +#define KEY_FN_F3 0x1d4 +#define KEY_FN_F4 0x1d5 +#define KEY_FN_F5 0x1d6 +#define KEY_FN_F6 0x1d7 +#define KEY_FN_F7 0x1d8 +#define KEY_FN_F8 0x1d9 +#define KEY_FN_F9 0x1da +#define KEY_FN_F10 0x1db +#define KEY_FN_F11 0x1dc +#define KEY_FN_F12 0x1dd +#define KEY_FN_1 0x1de +#define KEY_FN_2 0x1df +#define KEY_FN_D 0x1e0 +#define KEY_FN_E 0x1e1 +#define KEY_FN_F 0x1e2 +#define KEY_FN_S 0x1e3 +#define KEY_FN_B 0x1e4 + +#define KEY_BRL_DOT1 0x1f1 +#define KEY_BRL_DOT2 0x1f2 +#define KEY_BRL_DOT3 0x1f3 +#define KEY_BRL_DOT4 0x1f4 +#define KEY_BRL_DOT5 0x1f5 +#define KEY_BRL_DOT6 0x1f6 +#define KEY_BRL_DOT7 0x1f7 +#define KEY_BRL_DOT8 0x1f8 +#define KEY_BRL_DOT9 0x1f9 +#define KEY_BRL_DOT10 0x1fa + +#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ +#define KEY_NUMERIC_1 0x201 /* and other keypads */ +#define KEY_NUMERIC_2 0x202 +#define KEY_NUMERIC_3 0x203 +#define KEY_NUMERIC_4 0x204 +#define KEY_NUMERIC_5 0x205 +#define KEY_NUMERIC_6 0x206 +#define KEY_NUMERIC_7 0x207 +#define KEY_NUMERIC_8 0x208 +#define KEY_NUMERIC_9 0x209 +#define KEY_NUMERIC_STAR 0x20a +#define KEY_NUMERIC_POUND 0x20b +#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ +#define KEY_NUMERIC_B 0x20d +#define KEY_NUMERIC_C 0x20e +#define KEY_NUMERIC_D 0x20f + +#define KEY_CAMERA_FOCUS 0x210 +#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ + +#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ +#define KEY_TOUCHPAD_ON 0x213 +#define KEY_TOUCHPAD_OFF 0x214 + +#define KEY_CAMERA_ZOOMIN 0x215 +#define KEY_CAMERA_ZOOMOUT 0x216 +#define KEY_CAMERA_UP 0x217 +#define KEY_CAMERA_DOWN 0x218 +#define KEY_CAMERA_LEFT 0x219 +#define KEY_CAMERA_RIGHT 0x21a + +#define KEY_ATTENDANT_ON 0x21b +#define KEY_ATTENDANT_OFF 0x21c +#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ +#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ + +#define BTN_DPAD_UP 0x220 +#define BTN_DPAD_DOWN 0x221 +#define BTN_DPAD_LEFT 0x222 +#define BTN_DPAD_RIGHT 0x223 + +#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ +#define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */ + +#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ +#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ +#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ +#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ +#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ +#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ +#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ +#define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ +#define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */ + +#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ +#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ + +#define KEY_KBDINPUTASSIST_PREV 0x260 +#define KEY_KBDINPUTASSIST_NEXT 0x261 +#define KEY_KBDINPUTASSIST_PREVGROUP 0x262 +#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 +#define KEY_KBDINPUTASSIST_ACCEPT 0x264 +#define KEY_KBDINPUTASSIST_CANCEL 0x265 + +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x277 +#define KEY_ONSCREEN_KEYBOARD 0x278 +/* Electronic privacy screen control */ +#define KEY_PRIVACY_SCREEN_TOGGLE 0x279 + +/* Select an area of screen to be copied */ +#define KEY_SELECTIVE_SCREENSHOT 0x27a + +/* + * Some keyboards have keys which do not have a defined meaning, these keys + * are intended to be programmed / bound to macros by the user. For most + * keyboards with these macro-keys the key-sequence to inject, or action to + * take, is all handled by software on the host side. So from the kernel's + * point of view these are just normal keys. + * + * The KEY_MACRO# codes below are intended for such keys, which may be labeled + * e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys + * where the marking on the key does indicate a defined meaning / purpose. + * + * The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing + * KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO + * define MUST be added. + */ +#define KEY_MACRO1 0x290 +#define KEY_MACRO2 0x291 +#define KEY_MACRO3 0x292 +#define KEY_MACRO4 0x293 +#define KEY_MACRO5 0x294 +#define KEY_MACRO6 0x295 +#define KEY_MACRO7 0x296 +#define KEY_MACRO8 0x297 +#define KEY_MACRO9 0x298 +#define KEY_MACRO10 0x299 +#define KEY_MACRO11 0x29a +#define KEY_MACRO12 0x29b +#define KEY_MACRO13 0x29c +#define KEY_MACRO14 0x29d +#define KEY_MACRO15 0x29e +#define KEY_MACRO16 0x29f +#define KEY_MACRO17 0x2a0 +#define KEY_MACRO18 0x2a1 +#define KEY_MACRO19 0x2a2 +#define KEY_MACRO20 0x2a3 +#define KEY_MACRO21 0x2a4 +#define KEY_MACRO22 0x2a5 +#define KEY_MACRO23 0x2a6 +#define KEY_MACRO24 0x2a7 +#define KEY_MACRO25 0x2a8 +#define KEY_MACRO26 0x2a9 +#define KEY_MACRO27 0x2aa +#define KEY_MACRO28 0x2ab +#define KEY_MACRO29 0x2ac +#define KEY_MACRO30 0x2ad + +/* + * Some keyboards with the macro-keys described above have some extra keys + * for controlling the host-side software responsible for the macro handling: + * -A macro recording start/stop key. Note that not all keyboards which emit + * KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if + * KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START + * should be interpreted as a recording start/stop toggle; + * -Keys for switching between different macro (pre)sets, either a key for + * cycling through the configured presets or keys to directly select a preset. + */ +#define KEY_MACRO_RECORD_START 0x2b0 +#define KEY_MACRO_RECORD_STOP 0x2b1 +#define KEY_MACRO_PRESET_CYCLE 0x2b2 +#define KEY_MACRO_PRESET1 0x2b3 +#define KEY_MACRO_PRESET2 0x2b4 +#define KEY_MACRO_PRESET3 0x2b5 + +/* + * Some keyboards have a buildin LCD panel where the contents are controlled + * by the host. Often these have a number of keys directly below the LCD + * intended for controlling a menu shown on the LCD. These keys often don't + * have any labeling so we just name them KEY_KBD_LCD_MENU# + */ +#define KEY_KBD_LCD_MENU1 0x2b8 +#define KEY_KBD_LCD_MENU2 0x2b9 +#define KEY_KBD_LCD_MENU3 0x2ba +#define KEY_KBD_LCD_MENU4 0x2bb +#define KEY_KBD_LCD_MENU5 0x2bc + +#define BTN_TRIGGER_HAPPY 0x2c0 +#define BTN_TRIGGER_HAPPY1 0x2c0 +#define BTN_TRIGGER_HAPPY2 0x2c1 +#define BTN_TRIGGER_HAPPY3 0x2c2 +#define BTN_TRIGGER_HAPPY4 0x2c3 +#define BTN_TRIGGER_HAPPY5 0x2c4 +#define BTN_TRIGGER_HAPPY6 0x2c5 +#define BTN_TRIGGER_HAPPY7 0x2c6 +#define BTN_TRIGGER_HAPPY8 0x2c7 +#define BTN_TRIGGER_HAPPY9 0x2c8 +#define BTN_TRIGGER_HAPPY10 0x2c9 +#define BTN_TRIGGER_HAPPY11 0x2ca +#define BTN_TRIGGER_HAPPY12 0x2cb +#define BTN_TRIGGER_HAPPY13 0x2cc +#define BTN_TRIGGER_HAPPY14 0x2cd +#define BTN_TRIGGER_HAPPY15 0x2ce +#define BTN_TRIGGER_HAPPY16 0x2cf +#define BTN_TRIGGER_HAPPY17 0x2d0 +#define BTN_TRIGGER_HAPPY18 0x2d1 +#define BTN_TRIGGER_HAPPY19 0x2d2 +#define BTN_TRIGGER_HAPPY20 0x2d3 +#define BTN_TRIGGER_HAPPY21 0x2d4 +#define BTN_TRIGGER_HAPPY22 0x2d5 +#define BTN_TRIGGER_HAPPY23 0x2d6 +#define BTN_TRIGGER_HAPPY24 0x2d7 +#define BTN_TRIGGER_HAPPY25 0x2d8 +#define BTN_TRIGGER_HAPPY26 0x2d9 +#define BTN_TRIGGER_HAPPY27 0x2da +#define BTN_TRIGGER_HAPPY28 0x2db +#define BTN_TRIGGER_HAPPY29 0x2dc +#define BTN_TRIGGER_HAPPY30 0x2dd +#define BTN_TRIGGER_HAPPY31 0x2de +#define BTN_TRIGGER_HAPPY32 0x2df +#define BTN_TRIGGER_HAPPY33 0x2e0 +#define BTN_TRIGGER_HAPPY34 0x2e1 +#define BTN_TRIGGER_HAPPY35 0x2e2 +#define BTN_TRIGGER_HAPPY36 0x2e3 +#define BTN_TRIGGER_HAPPY37 0x2e4 +#define BTN_TRIGGER_HAPPY38 0x2e5 +#define BTN_TRIGGER_HAPPY39 0x2e6 +#define BTN_TRIGGER_HAPPY40 0x2e7 + +/* We avoid low common keys in module aliases so they don't get huge. */ +#define KEY_MIN_INTERESTING KEY_MUTE +#define KEY_MAX 0x2ff +#define KEY_CNT (KEY_MAX+1) + +/* + * Relative axes + */ + +#define REL_X 0x00 +#define REL_Y 0x01 +#define REL_Z 0x02 +#define REL_RX 0x03 +#define REL_RY 0x04 +#define REL_RZ 0x05 +#define REL_HWHEEL 0x06 +#define REL_DIAL 0x07 +#define REL_WHEEL 0x08 +#define REL_MISC 0x09 +/* + * 0x0a is reserved and should not be used in input drivers. + * It was used by HID as REL_MISC+1 and userspace needs to detect if + * the next REL_* event is correct or is just REL_MISC + n. + * We define here REL_RESERVED so userspace can rely on it and detect + * the situation described above. + */ +#define REL_RESERVED 0x0a +#define REL_WHEEL_HI_RES 0x0b +#define REL_HWHEEL_HI_RES 0x0c +#define REL_MAX 0x0f +#define REL_CNT (REL_MAX+1) + +/* + * Absolute axes + */ + +#define ABS_X 0x00 +#define ABS_Y 0x01 +#define ABS_Z 0x02 +#define ABS_RX 0x03 +#define ABS_RY 0x04 +#define ABS_RZ 0x05 +#define ABS_THROTTLE 0x06 +#define ABS_RUDDER 0x07 +#define ABS_WHEEL 0x08 +#define ABS_GAS 0x09 +#define ABS_BRAKE 0x0a +#define ABS_HAT0X 0x10 +#define ABS_HAT0Y 0x11 +#define ABS_HAT1X 0x12 +#define ABS_HAT1Y 0x13 +#define ABS_HAT2X 0x14 +#define ABS_HAT2Y 0x15 +#define ABS_HAT3X 0x16 +#define ABS_HAT3Y 0x17 +#define ABS_PRESSURE 0x18 +#define ABS_DISTANCE 0x19 +#define ABS_TILT_X 0x1a +#define ABS_TILT_Y 0x1b +#define ABS_TOOL_WIDTH 0x1c + +#define ABS_VOLUME 0x20 + +#define ABS_MISC 0x28 + +/* + * 0x2e is reserved and should not be used in input drivers. + * It was used by HID as ABS_MISC+6 and userspace needs to detect if + * the next ABS_* event is correct or is just ABS_MISC + n. + * We define here ABS_RESERVED so userspace can rely on it and detect + * the situation described above. + */ +#define ABS_RESERVED 0x2e + +#define ABS_MT_SLOT 0x2f /* MT slot being modified */ +#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ +#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ +#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ +#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ +#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ +#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ +#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ +#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ +#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ +#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ +#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ +#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ +#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ +#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ + + +#define ABS_MAX 0x3f +#define ABS_CNT (ABS_MAX+1) + +/* + * Switch events + */ + +#define SW_LID 0x00 /* set = lid shut */ +#define SW_TABLET_MODE 0x01 /* set = tablet mode */ +#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ +#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" + set = radio enabled */ +#define SW_RADIO SW_RFKILL_ALL /* deprecated */ +#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ +#define SW_DOCK 0x05 /* set = plugged into dock */ +#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ +#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ +#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ +#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ +#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ +#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ +#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ +#define SW_LINEIN_INSERT 0x0d /* set = inserted */ +#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ +#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ +#define SW_MAX 0x0f +#define SW_CNT (SW_MAX+1) + +/* + * Misc events + */ + +#define MSC_SERIAL 0x00 +#define MSC_PULSELED 0x01 +#define MSC_GESTURE 0x02 +#define MSC_RAW 0x03 +#define MSC_SCAN 0x04 +#define MSC_TIMESTAMP 0x05 +#define MSC_MAX 0x07 +#define MSC_CNT (MSC_MAX+1) + +/* + * LEDs + */ + +#define LED_NUML 0x00 +#define LED_CAPSL 0x01 +#define LED_SCROLLL 0x02 +#define LED_COMPOSE 0x03 +#define LED_KANA 0x04 +#define LED_SLEEP 0x05 +#define LED_SUSPEND 0x06 +#define LED_MUTE 0x07 +#define LED_MISC 0x08 +#define LED_MAIL 0x09 +#define LED_CHARGING 0x0a +#define LED_MAX 0x0f +#define LED_CNT (LED_MAX+1) + +/* + * Autorepeat values + */ + +#define REP_DELAY 0x00 +#define REP_PERIOD 0x01 +#define REP_MAX 0x01 +#define REP_CNT (REP_MAX+1) + +/* + * Sounds + */ + +#define SND_CLICK 0x00 +#define SND_BELL 0x01 +#define SND_TONE 0x02 +#define SND_MAX 0x07 +#define SND_CNT (SND_MAX+1) + +#endif From 06684979f9ebfa2731bc01a5b9cfb61a4e91a2c0 Mon Sep 17 00:00:00 2001 From: Varun Joshi Date: Tue, 17 Mar 2020 22:52:56 -0700 Subject: [PATCH 0963/1463] mb/google/deltaur: Update onboard memory config Update dq, dqs map based on deltan schematics. Configure memory to read SPD. BUG=b:151702387 Signed-off-by: Varun Joshi Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/deltaur/Makefile.inc | 1 + src/mainboard/google/deltaur/romstage.c | 14 +++ .../baseboard/include/baseboard/gpio.h | 2 + .../baseboard/include/baseboard/variants.h | 4 + .../deltaur/variants/deltan/Makefile.inc | 1 + .../google/deltaur/variants/deltan/memory.c | 63 +++++++++++++ .../deltaur/variants/deltaur/Makefile.inc | 1 + .../google/deltaur/variants/deltaur/memory.c | 91 +++++++++++++++++++ 8 files changed, 177 insertions(+) create mode 100644 src/mainboard/google/deltaur/romstage.c create mode 100644 src/mainboard/google/deltaur/variants/deltan/memory.c create mode 100644 src/mainboard/google/deltaur/variants/deltaur/memory.c diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc index a913c75da2..5d758aaa5d 100644 --- a/src/mainboard/google/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += ec.c +romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += ec.c diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c new file mode 100644 index 0000000000..2d7362976f --- /dev/null +++ b/src/mainboard/google/deltaur/romstage.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + variant_memory_init(mem_cfg); +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index e6092b6123..e6b23e645a 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -27,6 +27,8 @@ #define GPIO_MEM_CONFIG_3 GPP_F14 #define GPIO_MEM_CONFIG_4 GPP_F15 +/* DQ Memory Interleaved */ +#define MEMORY_INTERLEAVED GPP_E3 const struct pad_config *override_gpio_table(size_t *num); const struct pad_config *override_early_gpio_table(size_t *num); diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 1d8a934ecc..a1f1b22ec1 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -8,6 +8,7 @@ #define __BASEBOARD_VARIANTS_H__ #include +#include #include #include @@ -21,4 +22,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +const struct lpddr4x_cfg *variant_memory_params(void); +void variant_memory_init(FSP_M_CONFIG *mem_cfg); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc index ea0d5f0157..bad6b247e1 100644 --- a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc @@ -7,3 +7,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +romstage-y += memory.c diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c new file mode 100644 index 0000000000..90fa642c04 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +static const struct mb_ddr4_cfg baseboard_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */ + { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */ + { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ + { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */ + { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ + { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ + { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ + { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ + }, + + [1] = { + { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */ + { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ + { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ + { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ + { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ + { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ + { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ + { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + { 1, 0, 1, 0, 0, 1, 1, 0 }, + { 1, 0, 1, 0, 1, 0, 1, 0 } + }, + + .ect = 0, /* Disable Early Command Training */ +}; + +void variant_memory_init(FSP_M_CONFIG *mem_cfg) +{ + const struct spd_info spd_info = { + .smbus_info[0] = {.addr_dimm0 = 0xa0, + .addr_dimm1 = 0 }, + .smbus_info[1] = {.addr_dimm0 = 0xa4, + .addr_dimm1 = 0 }, + }; + const bool half_populated = false; + struct mb_ddr4_cfg new_board_cfg_ddr4; + + memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg)); + + new_board_cfg_ddr4.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); + + meminit_ddr4(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); +} diff --git a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc index ea0d5f0157..bad6b247e1 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc @@ -7,3 +7,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +romstage-y += memory.c diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c new file mode 100644 index 0000000000..c2df46703c --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +static const struct lpddr4x_cfg baseboard_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 0, /* Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +static int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void variant_memory_init(FSP_M_CONFIG *mem_cfg) +{ + const struct lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct spd_info spd_info = { + .md_spd_loc = SPD_CBFS, + .cbfs_index = variant_memory_sku(), + }; + const bool half_populated = false; + meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); +} From c6f5b05cf383bd66c1f9e168394c7c0d86080a60 Mon Sep 17 00:00:00 2001 From: Anil Kumar Date: Thu, 26 Mar 2020 16:35:23 -0700 Subject: [PATCH 0964/1463] mb/google/deltaur: Return SKU ID info For Deltaur and Deltan variants return proper SKU ID based on EC firmware type and sensor detect GPIO value BUG=b:152544516 TEST=make build successful for deltan Change-Id: I20a497739e5062400b093648c3a634203dec6105 Signed-off-by: Anil Kumar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: EricR Lai --- .../deltaur/variants/baseboard/Makefile.inc | 1 + .../google/deltaur/variants/baseboard/gpio.c | 5 ++++ .../baseboard/include/baseboard/variants.h | 9 +++++++ .../google/deltaur/variants/baseboard/sku.c | 26 +++++++++++++++++++ .../variants/deltan/include/variant/variant.h | 25 ++++++++++++++++++ .../google/deltaur/variants/deltaur/gpio.c | 8 ++++++ .../deltaur/include/variant/variant.h | 26 +++++++++++++++++++ 7 files changed, 100 insertions(+) create mode 100644 src/mainboard/google/deltaur/variants/baseboard/sku.c create mode 100644 src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h create mode 100644 src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h diff --git a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc index 937cb4628f..277b75ab27 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc @@ -7,5 +7,6 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += sku.c verstage-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index a67dd8cb4c..46a5cdd79d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -468,3 +468,8 @@ const struct pad_config *__weak variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +int __weak has_360_sensor_board(void) +{ + return 0; +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index a1f1b22ec1..332a2c6ea3 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -25,4 +25,13 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); const struct lpddr4x_cfg *variant_memory_params(void); void variant_memory_init(FSP_M_CONFIG *mem_cfg); +/* SKU ID structure */ +typedef struct { + int id; + const char *name; +} sku_info; + +/* Check if the device has a 360 sensor board present */ +int has_360_sensor_board(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/deltaur/variants/baseboard/sku.c b/src/mainboard/google/deltaur/variants/baseboard/sku.c new file mode 100644 index 0000000000..8465e64137 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/sku.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +static const uint32_t get_sku_index(void) +{ + return ((!has_360_sensor_board()) | (wilco_ec_signed_fw() << 1)); +} + +const uint32_t sku_id(void) +{ + return skus[get_sku_index()].id; +} + +const char *smbios_system_sku(void) +{ + return skus[get_sku_index()].name; +} diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h new file mode 100644 index 0000000000..be4c970959 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include +#include +#include + +const static sku_info skus[] = { + /* Deltan 360 - invalid configuration */ + { .id = -1, .name = "sku_invalid" }, + /* Deltan */ + { .id = 1, .name = "sku1" }, + /* Deltan 360 signed - invalid configuration */ + { .id = -1, .name = "sku_invalid" }, + /* Deltan signed */ + { .id = 2, .name = "sku2" }, +}; + +#endif diff --git a/src/mainboard/google/deltaur/variants/deltaur/gpio.c b/src/mainboard/google/deltaur/variants/deltaur/gpio.c index 30315bbc2e..02cb127504 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/gpio.c +++ b/src/mainboard/google/deltaur/variants/deltaur/gpio.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { @@ -29,3 +31,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* Check if the device has a 360 sensor board present */ +int has_360_sensor_board(void) +{ + return gpio_get(SENSOR_DET_360) == 0; +} diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h new file mode 100644 index 0000000000..8a5e3a83a8 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include + +/* TODO b/153027724: Sensor detection pin */ +#define SENSOR_DET_360 GPP_C10 + +const static sku_info skus[] = { + /* Deltaur 360 */ + { .id = 1, .name = "sku1" }, + /* Deltaur */ + { .id = 2, .name = "sku2" }, + /* Deltaur 360 signed */ + { .id = 3, .name = "sku3" }, + /* Deltaur signed */ + { .id = 4, .name = "sku4" }, +}; + +#endif From 2255ebaa23d5741e9f6179bfe8b6b3850b143ce8 Mon Sep 17 00:00:00 2001 From: Varun Joshi Date: Tue, 31 Mar 2020 18:02:33 -0700 Subject: [PATCH 0965/1463] mb/google/deltaur: Add support to enable GbE on variant - Configure devicetree for enabling GbE on variant and remove from baseboard. - Configure Kconfig to enable GbE region. - Configure fmd to incorporate GbE. BUG=b:151102809 Cq-Depend: chrome-internal:2843183 Signed-off-by: Varun Joshi Change-Id: I1c36b132546049e3e775585c41164072f4ece73e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Tim Wawrzynczak Reviewed-by: Bora Guvendik --- src/mainboard/google/deltaur/Kconfig | 1 + src/mainboard/google/deltaur/chromeos.fmd | 23 ++++++++++--------- .../deltaur/variants/baseboard/devicetree.cb | 7 +----- .../deltaur/variants/deltan/overridetree.cb | 6 +++++ 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 6b4af9b592..cd4646ccec 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR select MAINBOARD_USES_IFD_EC_REGION select SOC_INTEL_TIGERLAKE select SYSTEM_TYPE_LAPTOP + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DELTAN if BOARD_GOOGLE_BASEBOARD_DELTAUR diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd index d0cf8e92f8..9b6fec3ab2 100644 --- a/src/mainboard/google/deltaur/chromeos.fmd +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -1,26 +1,27 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x604000 { + SI_ALL@0x0 0x606000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_ME@0x101000 0x4ff000 - SI_PDR(PRESERVE)@0x600000 0x4000 + SI_GBE(PRESERVE)@0x101000 0x2000 + SI_ME@0x103000 0x4ff000 + SI_PDR(PRESERVE)@0x602000 0x4000 } - SI_BIOS@0x604000 0x19fc000 { - RW_DIAG@0x0 0x10cc000 { - RW_LEGACY(CBFS)@0x0 0x10bc000 - DIAG_NVRAM@0x10bc000 0x10000 + SI_BIOS@0x606000 0x19fa000 { + RW_DIAG@0x0 0x10ca000 { + RW_LEGACY(CBFS)@0x0 0x10ba000 + DIAG_NVRAM@0x10ba000 0x10000 } - RW_SECTION_A@0x10cc000 0x280000 { + RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x134c000 0x280000 { + RW_SECTION_B@0x134a000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x15cc000 0x30000 { + RW_MISC@0x15ca000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -33,7 +34,7 @@ FLASH@0xfe000000 0x2000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x15fc000 0x400000 { + WP_RO@0x15fa000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index a63d66c834..a30c12d633 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -59,11 +59,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[4]" = "6" register "PcieClkSrcClkReq[4]" = "4" - # PCIe port root 8 (LAN), clock 3 - register "PcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[3]" = "3" - # PCIe root port 9 (NVMe), clock 2 register "PcieRpEnable[8]" = "1" register "PcieClkSrcUsage[2]" = "8" @@ -332,7 +327,7 @@ chip soc/intel/tigerlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller - device pci 1f.6 on end # GbE Controller + device pci 1f.6 off end # GbE Controller device pci 1f.7 off end # Intel Trace Hub end end diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb index 32204c58e7..6a2719b960 100644 --- a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -1,6 +1,12 @@ chip soc/intel/tigerlake + # PCIe Port 8 for LAN + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[3]" = "3" + device domain 0 on + device pci 1f.6 on end # GbE 0x15FC end end From c02bda0f066927744c5d75de14e4c1cf73ce39c9 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 28 Feb 2020 10:19:41 +0100 Subject: [PATCH 0966/1463] acpi: Bump FADT to revision 6 Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/arch/x86/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 9 ++++-- .../emulation/qemu-q35/acpi_tables.c | 10 +++---- src/mainboard/lenovo/t400/fadt.c | 12 ++++---- src/mainboard/lenovo/x200/fadt.c | 12 ++++---- src/mainboard/roda/rk9/fadt.c | 10 +++---- src/soc/amd/picasso/acpi.c | 2 +- src/soc/amd/stoneyridge/acpi.c | 2 +- src/soc/intel/apollolake/acpi.c | 2 +- src/soc/intel/baytrail/acpi.c | 18 ++++++++---- src/soc/intel/braswell/acpi.c | 18 ++++++++---- src/soc/intel/broadwell/acpi.c | 25 +++++++++++------ src/soc/intel/cannonlake/acpi.c | 2 +- src/soc/intel/common/block/acpi/acpi.c | 18 +++++++++++- src/soc/intel/icelake/acpi.c | 2 +- src/soc/intel/quark/acpi.c | 8 +++--- src/soc/intel/skylake/acpi.c | 25 ++++++++++------- src/soc/intel/tigerlake/acpi.c | 2 +- src/soc/intel/xeon_sp/skx/acpi.c | 19 ++++++------- src/southbridge/intel/i82371eb/fadt.c | 14 +++++----- src/southbridge/intel/lynxpoint/lpc.c | 28 +++++++------------ 21 files changed, 138 insertions(+), 102 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6eded1d97a..a5c5c49473 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1554,7 +1554,7 @@ int get_acpi_table_revision(enum acpi_tables table) { switch (table) { case FADT: - return ACPI_FADT_REV_ACPI_3_0; + return ACPI_FADT_REV_ACPI_6_0; case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ return 2; case MCFG: diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 644f52f2ce..f5ec9f1685 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -546,8 +546,8 @@ typedef struct acpi_fadt { u32 flags; acpi_addr_t reset_reg; u8 reset_value; - u16 ARM_boot_arch; - u8 FADT_MinorVersion; + u16 ARM_boot_arch; /* Revision 6 only, Revision 5: Must be zero */ + u8 FADT_MinorVersion; /* Revision 6 only, Revision 5: Must be zero */ u32 x_firmware_ctl_l; u32 x_firmware_ctl_h; u32 x_dsdt_l; @@ -560,6 +560,11 @@ typedef struct acpi_fadt { acpi_addr_t x_pm_tmr_blk; acpi_addr_t x_gpe0_blk; acpi_addr_t x_gpe1_blk; + /* Revision 5 */ + acpi_addr_t sleep_control_reg; + acpi_addr_t sleep_status_reg; + /* Revision 6 */ + u64 hypervisor_vendor_identity; } __packed acpi_fadt_t; /* FADT TABLE Revision values */ diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 29dcedf541..359c562e53 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -85,7 +85,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 0x06; @@ -99,7 +99,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -114,7 +114,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and Linux complains about 32 bit. */ fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -128,14 +128,14 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index 3aeb8bc5c0..840dcd0a42 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -68,7 +68,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 0x06; @@ -82,7 +82,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -97,7 +97,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and Linux complains about 32 bit. */ fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -111,21 +111,21 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 128; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x20; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index 3aeb8bc5c0..840dcd0a42 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -68,7 +68,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 0x06; @@ -82,7 +82,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -97,7 +97,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and Linux complains about 32 bit. */ fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -111,21 +111,21 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 128; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x20; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index 3aeb8bc5c0..edcb3539b1 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -82,7 +82,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -97,7 +97,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and Linux complains about 32 bit. */ fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -111,21 +111,21 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 128; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x20; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 910d3e927e..c9a1179d52 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -171,7 +171,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 6a373fbd49..113d1e6b57 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -173,7 +173,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 82ef3f1d38..fbfe33ff73 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -167,7 +167,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; - + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; if (cfg->lpss_s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index ac0e29268b..3074f1a08f 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -171,7 +171,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 6; @@ -179,7 +179,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -193,7 +193,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -207,21 +207,27 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index b4e4746437..1e6cea298b 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -175,7 +175,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 6; @@ -183,7 +183,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -197,7 +197,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -211,21 +211,27 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index b93518954f..c45bd76731 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -226,7 +226,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 6; @@ -234,7 +234,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -248,7 +248,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -262,24 +262,31 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; + fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 0c806b5d60..306fa1cbee 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -170,7 +170,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index b848db446f..fe127a27e7 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -110,7 +110,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - /* Use ACPI 3.0 revision. */ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); @@ -146,20 +145,37 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.addrl = RST_CNT; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_value = RST_CPU | SYS_RST; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1b_evt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1b_cnt_blk.space_id = 1; + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + fadt->x_gpe1_blk.space_id = 1; soc_fill_fadt(fadt); diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 327dd112b8..ca74ab3b08 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -166,7 +166,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index ca4d2d6f65..624eb7669e 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -35,7 +35,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + R_QNC_PM1BLK_PM1S; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -46,7 +46,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -57,7 +57,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; fadt->x_pm_tmr_blk.addrh = 0x0; @@ -79,7 +79,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index dee44b6253..75f6b691ac 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -223,7 +223,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) const uint16_t pmbase = ACPI_BASE_ADDRESS; config_t *config = config_of_soc(); - /* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); @@ -275,7 +274,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 6; @@ -283,7 +282,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -297,7 +296,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -311,22 +310,28 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; fadt->x_gpe1_blk.space_id = 1; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 29a46195cd..9e7ff56752 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -167,7 +167,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 2abdf91eaf..e9edc9917d 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -355,7 +355,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - /* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); @@ -410,7 +409,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 6; @@ -418,7 +417,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -432,7 +431,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -446,22 +445,22 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; fadt->x_gpe1_blk.space_id = 1; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index b26628d075..db1071a041 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -157,28 +157,28 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; fadt->x_pm1b_evt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; fadt->x_pm1b_cnt_blk.addrh = 0x0; @@ -192,21 +192,21 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; fadt->x_gpe1_blk.addrh = 0x0; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 21da7d24d7..d9ef5cc538 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -852,25 +852,17 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrh = 0x0; /* - * We don't set `fadt->x_gpe0_blk` for Lynx Point LP since the correct - * bit width is 128 * 2, which is too large for an 8 bit unsigned int. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`. + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. */ - if (!pch_is_lp()) { - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 2 * 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; - fadt->x_gpe0_blk.addrh = 0x0; - } else { - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = 0x0; - fadt->x_gpe0_blk.addrh = 0x0; - } + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; From 56a3ef2e7419150e468198ac6c6ae2ebdd9e0afd Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 24 Mar 2020 17:29:49 +0100 Subject: [PATCH 0967/1463] acpi: Bump MADT to revision 3 Add structs and methods for revision 3. Change-Id: Ida75f530551ad2b8b20ce7fdeffb3befc51296bc Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39806 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Matt DeVillier --- src/arch/x86/acpi.c | 37 +++++++++++++++++++++++++++++--- src/arch/x86/include/arch/acpi.h | 24 ++++++++++++++++++++- 2 files changed, 57 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index a5c5c49473..4ff1ad55e1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -127,6 +127,18 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) return lapic->length; } +int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic) +{ + lapic->type = LOCAL_X2APIC; /* Local APIC structure */ + lapic->reserved = 0; + lapic->length = sizeof(acpi_madt_lx2apic_t); + lapic->flags = (1 << 0); /* Processor/LAPIC enabled */ + lapic->processor_id = cpu; + lapic->x2apic_id = apic; + + return lapic->length; +} + unsigned long acpi_create_madt_lapics(unsigned long current) { struct device *cpu; @@ -146,8 +158,12 @@ unsigned long acpi_create_madt_lapics(unsigned long current) if (num_cpus > 1) bubblesort(apic_ids, num_cpus, NUM_ASCENDING); for (index = 0; index < num_cpus; index++) { - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - index, apic_ids[index]); + if (apic_ids[index] < 0xff) + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, + index, apic_ids[index]); + else + current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, + index, apic_ids[index]); } return current; @@ -191,6 +207,21 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, return lapic_nmi->length; } +int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, + u16 flags, u8 lint) +{ + lapic_nmi->type = LOCAL_X2APIC_NMI; /* Local APIC NMI structure */ + lapic_nmi->length = sizeof(acpi_madt_lx2apic_nmi_t); + lapic_nmi->flags = flags; + lapic_nmi->processor_id = cpu; + lapic_nmi->lint = lint; + lapic_nmi->reserved[0] = 0; + lapic_nmi->reserved[1] = 0; + lapic_nmi->reserved[2] = 0; + + return lapic_nmi->length; +} + void acpi_create_madt(acpi_madt_t *madt) { acpi_header_t *header = &(madt->header); @@ -1556,7 +1587,7 @@ int get_acpi_table_revision(enum acpi_tables table) case FADT: return ACPI_FADT_REV_ACPI_6_0; case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ - return 2; + return 3; case MCFG: return 1; case TCPA: diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index f5ec9f1685..0ed89d1b12 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -466,6 +466,26 @@ typedef struct acpi_madt_irqoverride { u16 flags; /* MPS INTI flags */ } __packed acpi_madt_irqoverride_t; +/* MADT: Processor Local x2APIC Structure */ +typedef struct acpi_madt_lx2apic { + u8 type; /* Type (9) */ + u8 length; /* Length in bytes (16) */ + u16 reserved; + u32 x2apic_id; /* Local x2APIC ID */ + u32 flags; /* Same as Local APIC flags */ + u32 processor_id; /* ACPI processor ID */ +} __packed acpi_madt_lx2apic_t; + +/* MADT: Processor Local x2APIC NMI Structure */ +typedef struct acpi_madt_lx2apic_nmi { + u8 type; /* Type (10) */ + u8 length; /* Length in bytes (12) */ + u16 flags; /* Same as MPS INTI flags */ + u32 processor_id; /* ACPI processor ID */ + u8 lint; /* Local APIC LINT# */ + u8 reserved[3]; +} __packed acpi_madt_lx2apic_nmi_t; + #define ACPI_DBG2_PORT_SERIAL 0x8000 #define ACPI_DBG2_PORT_SERIAL_16550 0x0000 #define ACPI_DBG2_PORT_SERIAL_16550_DBGP 0x0001 @@ -871,7 +891,9 @@ void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint); - +int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); +int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, + u16 flags, u8 lint); int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); From bc885c194c0175b7a3ac9442cf9c82a0fa28ac2a Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Wed, 1 Apr 2020 13:30:37 -0700 Subject: [PATCH 0968/1463] google/chromeec: Add USB MUX Interrupt Kernel relies on the USB MUX interrupt to configure USB devices that are connected on the Type-C ports for TGL. Adding in the Q1C Interrupt so the Kernel can properly receive and configure USB devices BUG=b:152902608 TEST=buld_packages for volteer and verified that Proto 1 and Proto 2 are now seeing extcon events Change-Id: Ie3a2f829a295f090a03e72e12f19ecc5bb724952 Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/40024 Tested-by: build bot (Jenkins) Reviewed-by: Prashant Malani Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/acpi/ec.asl | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 1b8e128320..67e5f56d3c 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -355,6 +355,15 @@ Device (EC0) Notify (CREC, 0x80) } +#ifdef EC_ENABLE_PD_MCU_DEVICE + // USB MUX Interrupt + Method (_Q1C, 0, NotSerialized) + { + Store ("EC: USB MUX", Debug) + Notify (\_SB.PCI0.LPCB.EC0.CREC.ECPD, 0x80) + } +#endif + // TABLET mode switch Event Method (_Q1D, 0, NotSerialized) { From 287cf6c7d101d98cdbba8926651d87945534b7d9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 17 Mar 2020 19:32:14 -0700 Subject: [PATCH 0969/1463] lp/drivers/usb: Work around QEMU XHCI register issue The QEMU XHCI controller does not support byte/word reads from the capability register and it expects dword reads only. In order to make this work move the access of the capability register fields to use macros instead of a packed struct bitfield. This issue was filed upstream: https://bugs.launchpad.net/qemu/+bug/1693050 The original fix attempt in 2012 was not effective: https://github.com/qemu/qemu/commit/6ee021d41078844df60a3a466e3829a3e82776f3 With this change the controller is detected properly by the libpayload USB drivers. Change-Id: I048ed14921a4c9c0620c10b315b42476b6e5c512 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39838 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- payloads/libpayload/drivers/usb/xhci.c | 41 ++++--- .../libpayload/drivers/usb/xhci_private.h | 116 +++++++++--------- payloads/libpayload/drivers/usb/xhci_rh.c | 2 +- 3 files changed, 81 insertions(+), 78 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 0a69c5137b..2f61f8658a 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -185,26 +185,27 @@ xhci_init (unsigned long physical_bar) goto _free_xhci; } - xhci->capreg = phys_to_virt(physical_bar); - xhci->opreg = ((void *)xhci->capreg) + xhci->capreg->caplength; - xhci->hcrreg = ((void *)xhci->capreg) + xhci->capreg->rtsoff; - xhci->dbreg = ((void *)xhci->capreg) + xhci->capreg->dboff; + memcpy(&xhci->capreg, phys_to_virt(physical_bar), sizeof(xhci->capreg)); + xhci->opreg = phys_to_virt(physical_bar) + CAP_GET(CAPLEN, xhci->capreg); + xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg.rtsoff; + xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg.dboff; + xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar); - xhci_debug("caplen: 0x%"PRIx32"\n", xhci->capreg->caplength); - xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff); - xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff); + xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg)); + xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg.rtsoff); + xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg.dboff); xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n", - xhci->capreg->hciver_hi, xhci->capreg->hciver_lo); - if ((xhci->capreg->hciversion < 0x96) || - (xhci->capreg->hciversion > 0x110)) { + CAP_GET(CAPVER_HI, xhci->capreg), CAP_GET(CAPVER_LO, xhci->capreg)); + if ((CAP_GET(CAPVER, xhci->capreg) < 0x96) || + (CAP_GET(CAPVER, xhci->capreg) > 0x110)) { xhci_debug("Unsupported xHCI version\n"); goto _free_xhci; } xhci_debug("context size: %dB\n", CTXSIZE(xhci)); - xhci_debug("maxslots: 0x%02lx\n", xhci->capreg->MaxSlots); - xhci_debug("maxports: 0x%02lx\n", xhci->capreg->MaxPorts); + xhci_debug("maxslots: 0x%02lx\n", CAP_GET(MAXSLOTS, xhci->capreg)); + xhci_debug("maxports: 0x%02lx\n", CAP_GET(MAXPORTS, xhci->capreg)); const unsigned pagesize = xhci->opreg->pagesize << 12; xhci_debug("pagesize: 0x%04x\n", pagesize); @@ -213,7 +214,8 @@ xhci_init (unsigned long physical_bar) * structures at first and can still chicken out easily if we run out * of memory. */ - xhci->max_slots_en = xhci->capreg->MaxSlots & CONFIG_LP_MASK_MaxSlotsEn; + xhci->max_slots_en = CAP_GET(MAXSLOTS, xhci->capreg) & + CONFIG_LP_MASK_MaxSlotsEn; xhci->dcbaa = xhci_align(64, (xhci->max_slots_en + 1) * sizeof(u64)); xhci->dev = malloc((xhci->max_slots_en + 1) * sizeof(*xhci->dev)); if (!xhci->dcbaa || !xhci->dev) { @@ -227,8 +229,9 @@ xhci_init (unsigned long physical_bar) * Let dcbaa[0] point to another array of pointers, sp_ptrs. * The pointers therein point to scratchpad buffers (pages). */ - const size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs_Hi << 5 | - xhci->capreg->Max_Scratchpad_Bufs_Lo; + const size_t max_sp_bufs = + CAP_GET(MAX_SCRATCH_BUFS_HI, xhci->capreg) << 5 | + CAP_GET(MAX_SCRATCH_BUFS_LO, xhci->capreg); xhci_debug("max scratchpad bufs: 0x%zx\n", max_sp_bufs); if (max_sp_bufs) { const size_t sp_ptrs_size = max_sp_bufs * sizeof(u64); @@ -376,7 +379,8 @@ xhci_reinit (hci_t *controller) xhci_debug("event ring @%p (0x%08x)\n", xhci->er.ring, virt_to_phys(xhci->er.ring)); xhci_debug("ERST Max: 0x%lx -> 0x%lx entries\n", - xhci->capreg->ERST_Max, 1 << xhci->capreg->ERST_Max); + CAP_GET(ERST_MAX, xhci->capreg), + 1 << CAP_GET(ERST_MAX, xhci->capreg)); memset((void*)xhci->ev_ring_table, 0x00, sizeof(erst_entry_t)); xhci->ev_ring_table[0].seg_base_lo = virt_to_phys(xhci->er.ring); xhci->ev_ring_table[0].seg_base_hi = 0; @@ -432,8 +436,9 @@ xhci_shutdown(hci_t *const controller) #endif if (xhci->sp_ptrs) { - size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs_Hi << 5 | - xhci->capreg->Max_Scratchpad_Bufs_Lo; + const size_t max_sp_bufs = + CAP_GET(MAX_SCRATCH_BUFS_HI, xhci->capreg) << 5 | + CAP_GET(MAX_SCRATCH_BUFS_LO, xhci->capreg); for (i = 0; i < max_sp_bufs; ++i) { if (xhci->sp_ptrs[i]) free(phys_to_virt(xhci->sp_ptrs[i])); diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index ab1dfa98e1..65c3fdd6cc 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -274,7 +274,6 @@ typedef volatile struct epctx { } epctx_t; #define NUM_EPS 32 -#define CTXSIZE(xhci) ((xhci)->capreg->csz ? 64 : 32) typedef union devctx { /* set of pointers, so we can dynamically adjust Slot/EP context size */ @@ -321,66 +320,65 @@ typedef struct erst_entry { u32 rsvd; } erst_entry_t; +#define CAP_CAPLEN_FIELD hciparams +#define CAP_CAPLEN_START 0 +#define CAP_CAPLEN_LEN 8 +#define CAP_CAPVER_FIELD hciparams +#define CAP_CAPVER_START 16 +#define CAP_CAPVER_LEN 16 +#define CAP_CAPVER_HI_FIELD hciparams +#define CAP_CAPVER_HI_START 24 +#define CAP_CAPVER_HI_LEN 8 +#define CAP_CAPVER_LO_FIELD hciparams +#define CAP_CAPVER_LO_START 16 +#define CAP_CAPVER_LO_LEN 8 +#define CAP_MAXSLOTS_FIELD hcsparams1 +#define CAP_MAXSLOTS_START 0 +#define CAP_MAXSLOTS_LEN 7 +#define CAP_MAXINTRS_FIELD hcsparams1 +#define CAP_MAXINTRS_START 7 +#define CAP_MAXINTRS_LEN 11 +#define CAP_MAXPORTS_FIELD hcsparams1 +#define CAP_MAXPORTS_START 24 +#define CAP_MAXPORTS_LEN 8 +#define CAP_IST_FIELD hcsparams2 +#define CAP_IST_START 0 +#define CAP_IST_LEN 4 +#define CAP_ERST_MAX_FIELD hcsparams2 +#define CAP_ERST_MAX_START 4 +#define CAP_ERST_MAX_LEN 4 +#define CAP_MAX_SCRATCH_BUFS_HI_FIELD hcsparams2 +#define CAP_MAX_SCRATCH_BUFS_HI_START 21 +#define CAP_MAX_SCRATCH_BUFS_HI_LEN 5 +#define CAP_MAX_SCRATCH_BUFS_LO_FIELD hcsparams2 +#define CAP_MAX_SCRATCH_BUFS_LO_START 27 +#define CAP_MAX_SCRATCH_BUFS_LO_LEN 5 +#define CAP_U1_LATENCY_FIELD hcsparams3 +#define CAP_U1_LATENCY_START 0 +#define CAP_U1_LATENCY_LEN 8 +#define CAP_U2_LATENCY_FIELD hcsparams3 +#define CAP_U2_LATENCY_START 16 +#define CAP_U2_LATENCY_LEN 16 +#define CAP_CSZ_FIELD hccparams +#define CAP_CSZ_START 2 +#define CAP_CSZ_LEN 1 + +#define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN) +#define CAP_GET(tok, cap) (((cap).CAP_##tok##_FIELD & CAP_MASK(tok)) \ + >> CAP_##tok##_START) + +#define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32) + typedef struct xhci { - /* capreg is read-only, so no need for volatile, - and thus 32bit accesses can be assumed. */ struct capreg { - u8 caplength; /* 0x00 */ - u8 res1; /* 0x01 */ - union { /* 0x02 */ - u16 hciversion; - struct { - u8 hciver_lo; - u8 hciver_hi; - } __packed; - } __packed; - union { /* 0x04 */ - u32 hcsparams1; - struct { - unsigned long MaxSlots:7; - unsigned long MaxIntrs:11; - unsigned long:6; - unsigned long MaxPorts:8; - } __packed; - } __packed; - union { /* 0x08 */ - u32 hcsparams2; - struct { - unsigned long IST:4; - unsigned long ERST_Max:4; - unsigned long:13; - unsigned long Max_Scratchpad_Bufs_Hi:5; - unsigned long SPR:1; - unsigned long Max_Scratchpad_Bufs_Lo:5; - } __packed; - } __packed; - union { /* 0x0C */ - u32 hcsparams3; - struct { - unsigned long u1latency:8; - unsigned long:8; - unsigned long u2latency:16; - } __packed; - } __packed; - union { /* 0x10 */ - u32 hccparams; - struct { - unsigned long ac64:1; - unsigned long bnc:1; - unsigned long csz:1; - unsigned long ppc:1; - unsigned long pind:1; - unsigned long lhrc:1; - unsigned long ltc:1; - unsigned long nss:1; - unsigned long:4; - unsigned long MaxPSASize:4; - unsigned long xECP:16; - } __packed; - } __packed; - u32 dboff; /* 0x14 */ - u32 rtsoff; /* 0x18 */ - } __packed *capreg; + u32 hciparams; + u32 hcsparams1; + u32 hcsparams2; + u32 hcsparams3; + u32 hccparams; + u32 dboff; + u32 rtsoff; + } __packed capreg; /* opreg is R/W is most places, so volatile access is necessary. volatile means that the compiler seeks byte writes if possible, diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index 453fa5b409..865b9ac18b 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -160,7 +160,7 @@ xhci_rh_init (usbdev_t *dev) dev->port = -1; const int num_ports = /* TODO: maybe we need to read extended caps */ - (XHCI_INST(dev->controller)->capreg->hcsparams1 >> 24) & 0xff; + CAP_GET(MAXPORTS, XHCI_INST(dev->controller)->capreg); generic_hub_init(dev, num_ports, &xhci_rh_ops); usb_debug("xHCI: root hub init done\n"); From c68902c210465e31f909618b90c347fbadedb09b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 11 Mar 2020 15:08:31 -0700 Subject: [PATCH 0970/1463] Update vboot submodule pointer Update the pointer for vboot_reference so it can be used to compile depthcharge payload on the master branch. Change-Id: I5fc6e05896d7221a1e48ca86c6b15081488302b5 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39840 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 5059062dd3..46ff62c31c 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 5059062dd352e3864fb68f8a061e87bd7055d12a +Subproject commit 46ff62c31c1d815196fa990e613e1e6e229f8ce2 From 45a354fe787ff2a3f75125edb3b7fa1daad07f34 Mon Sep 17 00:00:00 2001 From: Marcello Sylvester Bauer Date: Wed, 11 Mar 2020 15:47:45 +0100 Subject: [PATCH 0971/1463] mb/lenovo/*: Add vboot RO FMAPs on 12MiB devices Tested on W530 Change-Id: I9be0c5e06fcb8287d32171cb72dabb5fcf047e7a Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39450 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t430/vboot-ro.fmd | 21 +++++++++++++++++++ src/mainboard/lenovo/t430s/vboot-ro.fmd | 21 +++++++++++++++++++ src/mainboard/lenovo/t440p/vboot-ro.fmd | 21 +++++++++++++++++++ src/mainboard/lenovo/t530/vboot-ro.fmd | 21 +++++++++++++++++++ src/mainboard/lenovo/x131e/vboot-ro.fmd | 21 +++++++++++++++++++ .../lenovo/x1_carbon_gen1/vboot-ro.fmd | 21 +++++++++++++++++++ src/mainboard/lenovo/x230/vboot-ro.fmd | 21 +++++++++++++++++++ 7 files changed, 147 insertions(+) create mode 100644 src/mainboard/lenovo/t430/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/t430s/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/t440p/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/t530/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/x131e/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/x230/vboot-ro.fmd diff --git a/src/mainboard/lenovo/t430/vboot-ro.fmd b/src/mainboard/lenovo/t430/vboot-ro.fmd new file mode 100644 index 0000000000..6bdd4cc458 --- /dev/null +++ b/src/mainboard/lenovo/t430/vboot-ro.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x700000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t430s/vboot-ro.fmd b/src/mainboard/lenovo/t430s/vboot-ro.fmd new file mode 100644 index 0000000000..6bdd4cc458 --- /dev/null +++ b/src/mainboard/lenovo/t430s/vboot-ro.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x700000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t440p/vboot-ro.fmd b/src/mainboard/lenovo/t440p/vboot-ro.fmd new file mode 100644 index 0000000000..6bdd4cc458 --- /dev/null +++ b/src/mainboard/lenovo/t440p/vboot-ro.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x700000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t530/vboot-ro.fmd b/src/mainboard/lenovo/t530/vboot-ro.fmd new file mode 100644 index 0000000000..6bdd4cc458 --- /dev/null +++ b/src/mainboard/lenovo/t530/vboot-ro.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x700000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x131e/vboot-ro.fmd b/src/mainboard/lenovo/x131e/vboot-ro.fmd new file mode 100644 index 0000000000..6bdd4cc458 --- /dev/null +++ b/src/mainboard/lenovo/x131e/vboot-ro.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x700000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd new file mode 100644 index 0000000000..6bdd4cc458 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x700000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x230/vboot-ro.fmd b/src/mainboard/lenovo/x230/vboot-ro.fmd new file mode 100644 index 0000000000..6bdd4cc458 --- /dev/null +++ b/src/mainboard/lenovo/x230/vboot-ro.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x700000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} From fc8867c3d8b4560ddcf7c85873601c2516dd67e0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 24 Mar 2020 08:29:08 +0100 Subject: [PATCH 0972/1463] mb/lenovo: Add additional FMAPs for stripped ME Make it easier to use measured boot with stripped ME by providing the corresponding FMAPs. Change-Id: I1763583a42bbc91e6acc06b262deab10d34447a3 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39798 Tested-by: build bot (Jenkins) Reviewed-by: Marcello Sylvester Bauer Reviewed-by: Philipp Deppenwiese --- .../lenovo/t430/vboot-ro-me_clean.fmd | 21 +++++++++++++++++++ .../lenovo/t430s/vboot-ro-me_clean.fmd | 21 +++++++++++++++++++ .../lenovo/t440p/vboot-ro-me_clean.fmd | 21 +++++++++++++++++++ .../lenovo/t530/vboot-ro-me_clean.fmd | 21 +++++++++++++++++++ .../lenovo/x131e/vboot-ro-me_clean.fmd | 21 +++++++++++++++++++ .../x1_carbon_gen1/vboot-ro-me_clean.fmd | 21 +++++++++++++++++++ .../lenovo/x230/vboot-ro-me_clean.fmd | 21 +++++++++++++++++++ 7 files changed, 147 insertions(+) create mode 100644 src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/t440p/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd diff --git a/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..565cacd3a8 --- /dev/null +++ b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0xbe0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..565cacd3a8 --- /dev/null +++ b/src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0xbe0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t440p/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t440p/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..565cacd3a8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/vboot-ro-me_clean.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0xbe0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..565cacd3a8 --- /dev/null +++ b/src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0xbe0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..565cacd3a8 --- /dev/null +++ b/src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0xbe0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..565cacd3a8 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0xbe0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..565cacd3a8 --- /dev/null +++ b/src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd @@ -0,0 +1,21 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0xbe0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} From 65535332db1f94bbe08928f7c0e52f01cb26c1c1 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 2 Apr 2020 14:57:00 +0200 Subject: [PATCH 0973/1463] mb/facebook/monolith: Add fmd files for 6MB BIOS area The current flash layout requires changes to the descriptor area to create the 9MB BIOS region. Add fmd files that allow switching to coreboot by only replacing the BIOS region. BUG=N/A TEST=tested on facebook monolith Change-Id: I2b003018e245693934202505d7e3891c2f545e6c Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/40040 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- .../facebook/monolith/vboot-ro_6mb.fmd | 28 ++++++++++++++++ .../facebook/monolith/vboot-rw_6mb.fmd | 33 +++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 src/mainboard/facebook/monolith/vboot-ro_6mb.fmd create mode 100644 src/mainboard/facebook/monolith/vboot-rw_6mb.fmd diff --git a/src/mainboard/facebook/monolith/vboot-ro_6mb.fmd b/src/mainboard/facebook/monolith/vboot-ro_6mb.fmd new file mode 100644 index 0000000000..1bf6fb9bb4 --- /dev/null +++ b/src/mainboard/facebook/monolith/vboot-ro_6mb.fmd @@ -0,0 +1,28 @@ +FLASH 16M { + SI_ALL@0x0 0xA00000 { + SI_DESC@0x0 0x1000 + UNUSED_1@0x1000 0x2000 + SI_ME@0x3000 0x6fd000 + UNUSED_2@0x700000 0x300000 + } + SI_BIOS@0xA00000 0x600000 { + MISC_RW@0x0 0x20000 { + UNIFIED_MRC_CACHE@0x0 0x10000 { + RW_MRC_CACHE@0x00000 0x10000 + } + RW_VPD(PRESERVE)@0x010000 0x2000 + RW_NVRAM(PRESERVE)@0x012000 0x6000 + } + USED_BY_ORG_BIOS(PRESERVE)@0x20000 0x40000 + WP_RO@0x060000 0x5A0000 { + RO_VPD(PRESERVE)@0x00000 0x1000 + RO_SECTION@0x1000 0x59F000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x59A000 + } + } + } +} diff --git a/src/mainboard/facebook/monolith/vboot-rw_6mb.fmd b/src/mainboard/facebook/monolith/vboot-rw_6mb.fmd new file mode 100644 index 0000000000..e10a5767be --- /dev/null +++ b/src/mainboard/facebook/monolith/vboot-rw_6mb.fmd @@ -0,0 +1,33 @@ +FLASH 16M { + SI_ALL@0x0 0xA00000 { + SI_DESC@0x0 0x1000 + UNUSED_1@0x1000 0x2000 + SI_ME@0x3000 0x6fd000 + UNUSED_2@0x700000 0x300000 + } + SI_BIOS@0xA00000 0x600000 { + MISC_RW@0x0 0x20000 { + UNIFIED_MRC_CACHE@0x0 0x10000 { + RW_MRC_CACHE@0x00000 0x10000 + } + RW_VPD(PRESERVE)@0x010000 0x2000 + RW_NVRAM(PRESERVE)@0x012000 0x6000 + } + USED_BY_ORG_BIOS(PRESERVE)@0x20000 0x40000 + RW_SECTION_A@0x60000 0x520000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x50FFC0 + } + WP_RO@0x580000 0x080000 { + RO_VPD(PRESERVE)@0x00000 0x1000 + RO_SECTION@0x1000 0x7F000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07A000 + } + } + } +} From 56a25a98db1835d02bf6936085073be685a2e10d Mon Sep 17 00:00:00 2001 From: dalao Date: Sun, 27 Oct 2019 17:08:34 +0800 Subject: [PATCH 0974/1463] mainboard/lenovo: Use the original hardware ids for keyboard/pointing Currently coreboot is using the compatible ID PNP0303 for all keyboards and PNP0F13 for all pointing devices, which causes some problems. On Windows, the touchpad driver can't be automatically matched and installed through Windows Update. On Linux, there are some strange issues. So it's better to use the original hardware IDs for each model. The hardware IDs for the following models can be found By searching for dmesg logs on vendor BIOS: T60: https://mail.gnome.org/archives/networkmanager-list/2012-January/msg00110.html Keyboard: PNP0303 Pointing: IBM0057 R60: https://openbenchmarking.org/system/1202279-AR-COMPRESS715/Lenovo%20R60/dmesg Keyboard: PNP0303 Pointing: IBM0057 X60: https://github.com/pavelmachek/missy/blob/master/db/notebook/lenovo/thinkpad/x60/pavel/2018.3648803539788/dmesg.out Keyboard: PNP0303 Pointing: IBM3780 X200: https://ubuntuforums.org/showthread.php?t=1833248&page=2 Keyboard: LEN0010 Pointing: IBM3780 T400: https://github.com/heradon/libreboot-fork/blob/master/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log Keyboard: LEN0010 Pointing: IBM3780 T510: https://bbs.archlinux.org/viewtopic.php?id=120287 Keyboard: PNP0303 Pointing: LEN0015 T410: https://forum.ubuntuusers.de/topic/kein-sound-109/ Keyboard: PNP0303 Pointing: LEN0015 T420: https://linux-hardware.org/index.php?probe=e6a094ade5&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T420s: https://bbs.archlinux.org/viewtopic.php?id=191510 Keyboard: PNP0303 Pointing: LEN0015 T520: https://bbs.archlinux.org/viewtopic.php?id=195636 Keyboard: PNP0303 Pointing: LEN0015 W520: https://linux-hardware.org/index.php?probe=9306cac54c&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/lenovo/g1et73ww-2.09/fwts/20160218_174223/dmesg.log Keyboard: PNP0303 Pointing: LEN0015 T430s: https://linux-hardware.org/index.php?probe=01545dc8fb&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T530: https://forums.fedoraforum.org/showthread.php?316640-Fedora-27-High-CPU Keyboard: LEN0071 Pointing: LEN0015 W530: https://bugs.freedesktop.org/attachment.cgi?id=115557 Keyboard: LEN0071 Pointing: LEN0015 L520: https://pastebin.com/U6MaBAY3 Keyboard: PNP0303 Pointing: LEN0017 X201: https://linux-hardware.org/index.php?probe=d7085ee4c8&log=dmesg.1 Keyboard: PNP0303 Pointing: LEN0018 X220: https://bbs.archlinux.org/viewtopic.php?id=237669 Keyboard: PNP0303 Pointing: LEN0020 X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460 Keyboard: PNP0303 Pointing: LEN0020 X131e: https://linux-hardware.org/index.php?probe=d765880811&log=dmesg Keyboard: MSF0001 Pointing: LEN0026 X1 Carbon Gen 1: https://bugzilla.kernel.org/show_bug.cgi?id=85851 Keyboard: LEN0071 Pointing: LEN0030 s230u: https://launchpadlibrarian.net/147231958/dmesg-reboot.txt Keyboard: PTL0001 Pointing: LEN0031 T540p: https://linux-hardware.org/index.php?probe=da766a30bc&log=dmesg Keyboard: LEN0071 Pointing: LEN0034 X240: https://linux-hardware.org/index.php?probe=fa7155b0e4&log=dmesg Keyboard: LEN0071 Pointing: LEN0035 T440p: https://bugzilla.kernel.org/show_bug.cgi?id=91541 Keyboard: LEN0071 Pointing: LEN0036 T440s: https://bugzilla.kernel.org/show_bug.cgi?id=91541 Keyboard: LEN0071 Pointing: LEN0036 T450: https://gist.github.com/kzar/1c38630eb22e4bf5b976 Keyboard: LEN0071 Pointing: LEN200e Others: https://github.com/torvalds/linux/blob/master/drivers/input/mouse/synaptics.c Test result: This can make Windows automatically install the Lenovo touchpad driver. It also fixes the T440p touchpad issue. Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932 Signed-off-by: dalao Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/36371 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- Documentation/mainboard/lenovo/t440p.md | 2 -- src/drivers/pc80/pc/Kconfig | 12 ++++++++++++ src/drivers/pc80/pc/ps2_controller.asl | 5 +++-- src/mainboard/lenovo/l520/Kconfig | 6 ++++++ src/mainboard/lenovo/s230u/Kconfig | 6 ++++++ src/mainboard/lenovo/t400/Kconfig | 6 ++++++ src/mainboard/lenovo/t410/Kconfig | 6 ++++++ src/mainboard/lenovo/t420/Kconfig | 6 ++++++ src/mainboard/lenovo/t420s/Kconfig | 6 ++++++ src/mainboard/lenovo/t430/Kconfig | 7 +++++++ src/mainboard/lenovo/t430s/Kconfig | 6 ++++++ src/mainboard/lenovo/t440p/Kconfig | 6 ++++++ src/mainboard/lenovo/t520/Kconfig | 6 ++++++ src/mainboard/lenovo/t530/Kconfig | 6 ++++++ src/mainboard/lenovo/t60/Kconfig | 8 ++++++++ src/mainboard/lenovo/x131e/Kconfig | 6 ++++++ src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 6 ++++++ src/mainboard/lenovo/x200/Kconfig | 6 ++++++ src/mainboard/lenovo/x201/Kconfig | 6 ++++++ src/mainboard/lenovo/x220/Kconfig | 6 ++++++ src/mainboard/lenovo/x230/Kconfig | 6 ++++++ src/mainboard/lenovo/x60/Kconfig | 6 ++++++ 22 files changed, 132 insertions(+), 4 deletions(-) diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md index fb0187075c..08df76fdca 100644 --- a/Documentation/mainboard/lenovo/t440p.md +++ b/Documentation/mainboard/lenovo/t440p.md @@ -31,8 +31,6 @@ the laptop able to power on. ## Known Issues - No audio output when using a headphone -- The touchpad is misconfigured, the 3 keys on top are all identified - as left button - Cannot get the mainboard serial number from the mainboard: the OEM UEFI firmware gets the serial number from an "emulated EEPROM" via I/O port 0x1630/0x1634, but it's still unknown how to make it work diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig index 68138575ba..455ac2bee1 100644 --- a/src/drivers/pc80/pc/Kconfig +++ b/src/drivers/pc80/pc/Kconfig @@ -19,3 +19,15 @@ config DRIVERS_PS2_KEYBOARD Otherwise say Y. endif + +config PS2K_EISAID + string + default "PNP0303" + help + Mainboards can override the default to match vendor drivers and quirks. + +config PS2M_EISAID + string + default "PNP0F13" + help + Mainboards can override the default to match vendor drivers and quirks. diff --git a/src/drivers/pc80/pc/ps2_controller.asl b/src/drivers/pc80/pc/ps2_controller.asl index 210a687681..d37ea2e7fd 100644 --- a/src/drivers/pc80/pc/ps2_controller.asl +++ b/src/drivers/pc80/pc/ps2_controller.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ Device (PS2K) // Keyboard { - Name(_HID, EISAID("PNP0303")) + Name(_HID, EISAID(CONFIG_PS2K_EISAID)) Name(_CID, EISAID("PNP030B")) Name(_CRS, ResourceTemplate() @@ -20,7 +20,8 @@ Device (PS2M) // Mouse { - Name(_HID, EISAID("PNP0F13")) + Name(_HID, EISAID(CONFIG_PS2M_EISAID)) + Name(_CID, EISAID("PNP0F13")) Name(_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 6716606ee4..5b9344a437 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -46,4 +46,10 @@ config USBDEBUG_HCD_INDEX int default 2 +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0017" + endif diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 1248906630..64f4b29200 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -52,4 +52,10 @@ config VGA_BIOS_ID string default "8086,0166" +config PS2K_EISAID + default "PTL0001" + +config PS2M_EISAID + default "LEN0031" + endif # BOARD_LENOVO_S230U diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index deb6c8e4bd..e6f56310a8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -79,4 +79,10 @@ config CBFS_SIZE hex default 0x200000 +config PS2K_EISAID + default "LEN0010" + +config PS2M_EISAID + default "IBM3780" + endif # BOARD_LENOVO_T400 diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 86cfce8dfc..ee79f11e61 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -63,4 +63,10 @@ config DRAM_RESET_GATE_GPIO int default 10 +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0015" + endif diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 7c715ed843..dfc8ed1d61 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -75,4 +75,10 @@ config VGA_BIOS_ID string default "8086,0126" +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0015" + endif # BOARD_LENOVO_T420 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 6af93ac887..f29d50fe96 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -74,4 +74,10 @@ config VGA_BIOS_ID string default "8086,0126" +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0015" + endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 009377d78f..45c7ae307a 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -68,4 +68,11 @@ config MAX_CPUS config USBDEBUG_HCD_INDEX int default 2 + +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0015" + endif diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 3ed0d0ecde..15b0912d44 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -84,4 +84,10 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0015" + endif # BOARD_LENOVO_T430S || BOARD_LENOVO_T431S diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 95cb1dc607..e6785488df 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -70,4 +70,10 @@ config DRIVER_LENOVO_SERIALS bool default n +config PS2K_EISAID + default "LEN0071" + +config PS2M_EISAID + default "LEN0036" + endif diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index a628adc646..aebb2dee46 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -84,4 +84,10 @@ config VGA_BIOS_FILE string default "pci8086,0126.rom" +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0015" + endif diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 0f8d3267f3..2a0e3ea039 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -85,4 +85,10 @@ config VGA_BIOS_ID string default "8086,0166" +config PS2K_EISAID + default "LEN0071" + +config PS2M_EISAID + default "LEN0015" + endif diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 58d41a6b57..57172ca25c 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -46,4 +46,12 @@ config MAX_CPUS int default 2 +config PS2K_EISAID + default "PNP0303" if BOARD_LENOVO_T60 + default "PNP0303" if BOARD_LENOVO_R60 + +config PS2M_EISAID + default "IBM0057" if BOARD_LENOVO_T60 + default "IBM0057" if BOARD_LENOVO_R60 + endif # BOARD_LENOVO_T60 || BOARD_LENOVO_Z61T || BOARD_LENOVO_R60 diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 29fda105f2..06c5d83737 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -56,4 +56,10 @@ config USBDEBUG_HCD_INDEX int default 2 +config PS2K_EISAID + default "MSF0001" + +config PS2M_EISAID + default "LEN0026" + endif # BOARD_LENOVO_X131E diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 830ace427d..246e1db5aa 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -73,4 +73,10 @@ config VGA_BIOS_ID string default "8086,0166" +config PS2K_EISAID + default "LEN0071" + +config PS2M_EISAID + default "LEN0030" + endif # BOARD_LENOVO_X1_CARBON_GEN1 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 432c805078..731f4cb142 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -72,4 +72,10 @@ config CBFS_SIZE hex default 0x200000 +config PS2K_EISAID + default "LEN0010" if BOARD_LENOVO_X200 + +config PS2M_EISAID + default "IBM3780" if BOARD_LENOVO_X200 + endif # BOARD_LENOVO_X200 || BOARD_LENOVO_X301 diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 42cf8f956e..d73eac3c7d 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -68,4 +68,10 @@ config ME_CLEANER_ARGS string default "-S -w EFFS" +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0018" + endif diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 7c4754dbbd..33e15a81cc 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -87,4 +87,10 @@ config VGA_BIOS_ID default "8086,0116" if BOARD_LENOVO_X220I default "8086,0126" +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0020" + endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index b25d7cf858..7d563efb2b 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -75,4 +75,10 @@ config VGA_BIOS_ID string default "8086,0166" +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "LEN0020" + endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1815892d4a..994a071fa3 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -42,4 +42,10 @@ config MAX_CPUS int default 2 +config PS2K_EISAID + default "PNP0303" + +config PS2M_EISAID + default "IBM3780" + endif From 5926fb5035aca828711f6b3edb1c4242bb547f7e Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Mon, 6 Apr 2020 18:09:48 -0700 Subject: [PATCH 0975/1463] mb/google/volteer: fix CROS_GPIO_WP_AH export Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community zero instead of community 1. BUG=b:152876091 TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to and log into Volteer kernel, execute "wp enable" in H1 console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in H1 console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/mainboard/google/volteer/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index fff03812d3..1028dfad9f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -460,7 +460,7 @@ const struct pad_config *__weak variant_early_gpio_table(size_t *num) static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM1_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) From ba41ee1f0a74cf6b0ed0c068b6560e60f7d760eb Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Mon, 6 Apr 2020 14:42:07 -0700 Subject: [PATCH 0976/1463] mb/google/volteer: fix incorrect fields in SPDs According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16) This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD). BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel. Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Caveh Jalali --- .../spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 2 +- .../spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex index a94b41a381..94f258e1e9 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 19 95 08 00 00 00 00 02 21 00 00 +23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex index 7ef8220252..90202f983c 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 59431176471beac2e074cf0ebca50c98c1ab50c8 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 7 Apr 2020 20:45:28 -0700 Subject: [PATCH 0977/1463] soc/intel/tigerlake: Configure RP setting Add LTR and AER configuration to the root ports config. BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Nick Vaccaro Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 6 ++++++ src/soc/intel/tigerlake/fsp_params.c | 7 +++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e105061872..bc6c3db726 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -118,6 +118,12 @@ struct soc_intel_tigerlake_config { L1_SS_L1_2, } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR: Enable (1) / Disable (0) */ + uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + + /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ + uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ff6d3a978a..231399c676 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -122,10 +122,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* RP Configs */ - for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpL1Substates[i] = get_l1_substate_control(config->PcieRpL1Substates[i]); - + params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; + params->PcieRpAdvancedErrorReporting[i] = + config->PcieRpAdvancedErrorReporting[i]; + } /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); if (dev) { From e3bf8ba2d812dd027afa8ee8ff368a5295ce1bda Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 7 Apr 2020 23:34:12 -0700 Subject: [PATCH 0978/1463] mb/google/volteer: Enable RP LTR setting BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268 Reviewed-by: Nick Vaccaro Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 361e563cab..ab911d2173 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -43,20 +43,24 @@ chip soc/intel/tigerlake # Enable NVMe PCIE 9 using clk 0 register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "1" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" # Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" From 53ac68e5518472612c1c4b5adf40d068fa3d7dda Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 7 Apr 2020 23:37:11 -0700 Subject: [PATCH 0979/1463] mb/intel/tglrvp : Enable RP LTR BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269 Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 ++++++ .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 501aa2a160..82303c6ddf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,12 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Enable RP LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 81d52a8d3d..043185bfdd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,12 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Enable PR LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1" From d0c0fd736fc28ae94773cc3914faa4fae9940b5d Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Thu, 27 Feb 2020 14:20:13 +0530 Subject: [PATCH 0980/1463] soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE lib Make use of print_me_fw_version() which is defined in the CSE lib to print ME firmware version information for icl,tgl. BUG=None BRANCH=None TEST=Build and boot iclrvp, tglrvp boards. Change-Id: Ief75403c490eee499a84372e54fa38ea3016cc11 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/39147 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Wonkyu Kim Reviewed-by: Sridhar Siricilla Reviewed-by: Subrata Banik --- src/soc/intel/icelake/Makefile.inc | 1 + src/soc/intel/icelake/me.c | 19 +++++++++++++++++++ src/soc/intel/tigerlake/Makefile.inc | 1 + src/soc/intel/tigerlake/me.c | 19 +++++++++++++++++++ 4 files changed, 40 insertions(+) create mode 100644 src/soc/intel/icelake/me.c create mode 100644 src/soc/intel/tigerlake/me.c diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 67a3a7114a..f30816e003 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c +ramstage-y += me.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/icelake/me.c b/src/soc/intel/icelake/me.c new file mode 100644 index 0000000000..d48b32bf6b --- /dev/null +++ b/src/soc/intel/icelake/me.c @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index fd2464d505..4aa1f2f4d1 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c +ramstage-y += me.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c new file mode 100644 index 0000000000..d48b32bf6b --- /dev/null +++ b/src/soc/intel/tigerlake/me.c @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); From 633a36af582f19e86d65b67e4e493d7bcc16acfb Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Wed, 26 Feb 2020 15:42:17 +0530 Subject: [PATCH 0981/1463] soc/intel/tigerlake: Add function to dump ME firmware status information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a function to dump ME Host Firmware Status registers. In tigerlake, Manufacturing mode is “No” if below conditions are satisfied, indicating end of manufacturing. Otherwise, manufacturing mode is "Yes". 1. Intel fuses are programmed (Indicated by HFSTS6[30] bit set) 2. The SPI flash descriptor region is locked. (Indicated by HFSTS1[4] cleared) BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/39127 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Rizwan Qureshi --- src/soc/intel/tigerlake/me.c | 161 +++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index d48b32bf6b..9b61496e65 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -15,5 +15,166 @@ #include #include +#include +#include +#include + +/* Host Firmware Status Register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* Host Firmware Status Register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test : 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t force_boot_guard_acm : 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy : 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; + +static void dump_me_status(void *unused) +{ + union me_hfsts1 hfsts1; + union me_hfsts2 hfsts2; + union me_hfsts3 hfsts3; + union me_hfsts4 hfsts4; + union me_hfsts5 hfsts5; + union me_hfsts6 hfsts6; + + if (!is_cse_enabled()) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); + hfsts2.data = me_read_config32(PCI_ME_HFSTS2); + hfsts3.data = me_read_config32(PCI_ME_HFSTS3); + hfsts4.data = me_read_config32(PCI_ME_HFSTS4); + hfsts5.data = me_read_config32(PCI_ME_HFSTS5); + hfsts6.data = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + + /* + * Lock Descriptor, and Fuses must be programmed on a + * production system to indicate ME Manufacturing mode is disabled. + */ + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + ((hfsts1.fields.spi_protection_mode == 0) && + (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); + /* + * The SPI Protection Mode bit reflects SPI descriptor + * locked(0) or unlocked(1). + */ + printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", + hfsts1.fields.spi_protection_mode ? "NO" : "YES"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: Enhanced Debug Mode : %s\n", + hfsts1.fields.invoke_enhance_dbg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); From 26ea43a5c2fb40e8d1235f8106a99533057f79eb Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Wed, 26 Feb 2020 16:04:57 +0530 Subject: [PATCH 0982/1463] soc/intel/icelake: Add function to dump ME firmware status information Add a function to dump ME Host Firmware Status registers. BUG=None BRANCH=None TEST=Build and boot iclrvp. Change-Id: I9430189665c94decb2e64680d28a7390ee6e912c Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/39128 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Rizwan Qureshi --- src/soc/intel/icelake/me.c | 148 +++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/src/soc/intel/icelake/me.c b/src/soc/intel/icelake/me.c index d48b32bf6b..bbfd166061 100644 --- a/src/soc/intel/icelake/me.c +++ b/src/soc/intel/icelake/me.c @@ -15,5 +15,153 @@ #include #include +#include +#include +#include + +/* Host Firmware Status Register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* Host Firmware Status Register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test : 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t force_boot_guard_acm : 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy : 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; + +static void dump_me_status(void *unused) +{ + union me_hfsts1 hfsts1; + union me_hfsts2 hfsts2; + union me_hfsts3 hfsts3; + union me_hfsts4 hfsts4; + union me_hfsts5 hfsts5; + union me_hfsts6 hfsts6; + + if (!is_cse_enabled()) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); + hfsts2.data = me_read_config32(PCI_ME_HFSTS2); + hfsts3.data = me_read_config32(PCI_ME_HFSTS3); + hfsts4.data = me_read_config32(PCI_ME_HFSTS4); + hfsts5.data = me_read_config32(PCI_ME_HFSTS5); + hfsts6.data = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); From 15161d92842e95f4b8ab10e4b1be118756fde437 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 23:44:25 +0100 Subject: [PATCH 0983/1463] 4.12 release notes: Add some explanation behind deprecations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some features are made mandatory, meaning that some platforms have been dropped from master. This also explains that further development on these popular platforms can happen on the 4.11 branch. TODO is this really the right place or is it too technical for release notes? Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37064 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki Reviewed-by: David Hendricks --- .../releases/coreboot-4.12-relnotes.md | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md index 7943aa7161..b172c4a92e 100644 --- a/Documentation/releases/coreboot-4.12-relnotes.md +++ b/Documentation/releases/coreboot-4.12-relnotes.md @@ -10,6 +10,69 @@ notes. * The chip and board additions and removals will be updated right before the release, so those do not need to be added. +Deprecations +------------ + +For the 4.12 release a few features on x86 became mandatory. These are +relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK. + +### Relocatable ramstage + +Relocatable stages are a feature implemented only on x86, where stages +can be relocated at runtime. This is used to place ramstage in a better +location that does not collide with memory the OS or the payload tends +to use. The rationale behind making this mandatory is that you always +want cbmem to be cached so it's a good location to run ramstage from. +It avoids using lower memory altogether so the OS can make use of it +and no backing up needs to happen on S3 resume. + +### Postcar stage + +With Postcar stage tearing down Cache-as-Ram is done in a separate +stage. This means that romstage has a clean program boundary and +that all variables in romstage can be accessed via their linked +addresses without runtime resolution. There is no need to link +global and static variables via the CAR\_GLOBAL macro and no need +to access them with car\_set/get\_var/ptr functions. + +### C\_ENVIRONMENT\_BOOTBLOCK + +Historically the bootblock on x86 platforms has been compiled with +romcc. This means that the generated code only uses CPU registers +and therefore no stack. This 20K+ LOC compiler is limited and hard +to maintain and so is the code that one has to write in that +environment. A different solution is to set up Cache-as-Ram in the +bootblock and run GCC compiled code in the bootblock. The advantages +are increased flexibility and consistency with other architectures as +well as other stages: e.g. printing to console is possible and +VBOOT can run before romstage, making romstage updatable via RW FMAP +regions. + +### Platforms dropped from master + +The following platforms did not implement those feature are dropped +from master to allow the master branch to move on: +- AMDFAM10 +- all FSP1.0 platforms: BROADWELL_DE, FSP_BAYTRAIL, RANGELEY +- VIA VX900 +- TODO (AMD?) + +In particular on FSP1.0 it is impossible to implement POSTCAR stage. +The reason is that FSP1.0 relocates the CAR region to the HOB before +returning to coreboot. This means that after FSP returns to coreboot +accessing variables via their original address is not possible. One +way of obtaining that behavior would be to set up Cache-as-Ram again +(but with open source code) and copy the relocated data from the HOB +there. This solution is deemed too hacky. Maybe a lesson can be +learned from this: blobs should not interfere with the execution +environment, as this makes proper integration much harder. + +### 4.11_branch + +Given that some platforms supported by FSP1.0 are being produced and +popular, the 4.11 release was made into a branch in which further +development can happen. + Significant changes ------------------- From dd1a0acc4a1a08d3ff446fa84c41307eead91f11 Mon Sep 17 00:00:00 2001 From: Marcello Sylvester Bauer Date: Wed, 19 Feb 2020 10:05:33 +0100 Subject: [PATCH 0984/1463] mb/lenovo: Add additional FMAPs on 8MiB devices * Add FMAP for measured boot only, with a single RO partition. * Add FMAP for measured boot only, with a single RO partition but where the ME has been shrunken. Tested on X220 using VBOOT+measured boot: * Used patched IFD and ME, boots into OS Change-Id: I04c1add13198444638c669deec1e05159b1a09c9 Signed-off-by: Marcello Sylvester Bauer Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39161 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov --- .../lenovo/t420/vboot-ro-me_clean.fmd | 22 +++++++++++++++++++ src/mainboard/lenovo/t420/vboot-ro.fmd | 22 +++++++++++++++++++ .../lenovo/t420s/vboot-ro-me_clean.fmd | 22 +++++++++++++++++++ src/mainboard/lenovo/t420s/vboot-ro.fmd | 22 +++++++++++++++++++ .../lenovo/t520/vboot-ro-me_clean.fmd | 22 +++++++++++++++++++ src/mainboard/lenovo/t520/vboot-ro.fmd | 22 +++++++++++++++++++ .../lenovo/x220/vboot-ro-me_clean.fmd | 22 +++++++++++++++++++ src/mainboard/lenovo/x220/vboot-ro.fmd | 22 +++++++++++++++++++ 8 files changed, 176 insertions(+) create mode 100644 src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/t420/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/t420s/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/t520/vboot-ro.fmd create mode 100644 src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd create mode 100644 src/mainboard/lenovo/x220/vboot-ro.fmd diff --git a/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..d1cbff7a1b --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t420/vboot-ro.fmd b/src/mainboard/lenovo/t420/vboot-ro.fmd new file mode 100644 index 0000000000..51df8a5322 --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..d1cbff7a1b --- /dev/null +++ b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd new file mode 100644 index 0000000000..51df8a5322 --- /dev/null +++ b/src/mainboard/lenovo/t420s/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..d1cbff7a1b --- /dev/null +++ b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t520/vboot-ro.fmd b/src/mainboard/lenovo/t520/vboot-ro.fmd new file mode 100644 index 0000000000..51df8a5322 --- /dev/null +++ b/src/mainboard/lenovo/t520/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..d1cbff7a1b --- /dev/null +++ b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x220/vboot-ro.fmd b/src/mainboard/lenovo/x220/vboot-ro.fmd new file mode 100644 index 0000000000..51df8a5322 --- /dev/null +++ b/src/mainboard/lenovo/x220/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} From 4f771fe98b893f03703e9081a29d08459111c2b2 Mon Sep 17 00:00:00 2001 From: Marco Chen Date: Fri, 10 Apr 2020 14:33:19 +0800 Subject: [PATCH 0985/1463] soc/intel/jasperlake: Allow mainboard to override DRAM part number In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on dedede. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:152019429 Change-Id: I7ba635f5504ba288308d7d7a4935f405f289aa8d Signed-off-by: Marco Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../intel/jasperlake/include/soc/romstage.h | 2 ++ src/soc/intel/jasperlake/romstage/romstage.c | 21 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h index 4a4fbe63b8..e3c7969127 100644 --- a/src/soc/intel/jasperlake/include/soc/romstage.h +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -6,6 +6,8 @@ #include +/* Provide a callback to allow mainboard to override the DRAM part number. */ +bool mainboard_get_dram_part_num(const char **part_num, size_t *len); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void pch_init(void); diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index fa9db6e29e..b8e9032e97 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -22,6 +22,12 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + /* Default weak implementation, no need to override part number. */ + return false; +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -36,6 +42,9 @@ static void save_dimm_info(void) const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len; + bool is_dram_part_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ meminfo_hob = fsp_find_extension_hob_by_guid( @@ -57,6 +66,10 @@ static void save_dimm_info(void) } memset(mem_info, 0, sizeof(*mem_info)); + /* Allow mainboard to override DRAM part number. */ + is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, + &dram_part_num_len); + /* Save available DIMM information */ index = 0; dimm_max = ARRAY_SIZE(mem_info->dimm); @@ -75,6 +88,14 @@ static void save_dimm_info(void) if (src_dimm->Status != DIMM_PRESENT) continue; + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!is_dram_part_overridden) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + u8 memProfNum = meminfo_hob->MemoryProfile; serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; From efc3d04af2f0cbf3d0afeceeadb1d1e09039047d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 8 Apr 2020 12:15:16 +0200 Subject: [PATCH 0986/1463] src/mainboard: Use 'const' to set pnp_devfn_t statically Change-Id: I50ac6914fadc02491df2eccb437eada89fd12b82 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40272 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/mainboard/asus/f2a85-m/bootblock.c | 6 +++--- src/mainboard/getac/p470/early_init.c | 4 +--- src/mainboard/kontron/ktqm77/early_init.c | 2 +- src/mainboard/lenovo/t60/early_init.c | 2 +- src/mainboard/lenovo/x60/early_init.c | 2 +- src/mainboard/roda/rk886ex/early_init.c | 4 +--- 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c index c63ab08b71..4fe0423138 100644 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -24,8 +24,8 @@ static void sbxxx_enable_48mhzout(void) static void superio_init_m(void) { - pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); - pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); ite_kill_watchdog(gpio); ite_enable_serial(uart, CONFIG_TTYS0_BASE); @@ -34,7 +34,7 @@ static void superio_init_m(void) static void superio_init_m_pro(void) { - pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1); + const pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1); nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index cc126dd3b9..04d0c0bf63 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -66,9 +66,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) void bootblock_mainboard_early_init(void) { - pnp_devfn_t dev; - - dev = PNP_DEV(0x4e, 0x00); + const pnp_devfn_t dev = PNP_DEV(0x4e, 0x00); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x02, 0x0e); // UART power diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 565106495d..949eab2a4b 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -35,7 +35,7 @@ void bootblock_mainboard_early_init(void) { int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */ - pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); + const pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_conf_state(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c index dba4c4cccd..3201102ab1 100644 --- a/src/mainboard/lenovo/t60/early_init.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -22,7 +22,7 @@ void mainboard_lpc_decode(void) static void early_superio_config(void) { int timeout = 100000; - pnp_devfn_t dev = PNP_DEV(0x2e, 3); + const pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0xa0); diff --git a/src/mainboard/lenovo/x60/early_init.c b/src/mainboard/lenovo/x60/early_init.c index ef760fb974..5a8fc78d76 100644 --- a/src/mainboard/lenovo/x60/early_init.c +++ b/src/mainboard/lenovo/x60/early_init.c @@ -22,7 +22,7 @@ void mainboard_lpc_decode(void) static void early_superio_config(void) { int timeout = 100000; - pnp_devfn_t dev = PNP_DEV(0x2e, 3); + const pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06); diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index fe61187f24..baa17d174c 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -35,9 +35,7 @@ void mainboard_lpc_decode(void) void bootblock_mainboard_early_init(void) { - pnp_devfn_t dev; - - dev = PNP_DEV(0x2e, 0x00); + const pnp_devfn_t dev = PNP_DEV(0x2e, 0x00); pnp_enter_conf_state(dev); pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ From abc17d10d6feac38cd6c5cdecab04cedfb2bccae Mon Sep 17 00:00:00 2001 From: Marx Wang Date: Tue, 7 Apr 2020 16:58:38 +0800 Subject: [PATCH 0987/1463] soc/intel/apollolake: Disable XHCI LFPS power management Provide the option to disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=None TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Marx Wang Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40255 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/chip.c | 31 +++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 8 ++++++++ 2 files changed, 39 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1075642517..c4e068d41f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -99,6 +99,10 @@ /* IOSF Gasket Backbone Local Clock Gating Enable */ #define IOSFGBLCGE (1 << 0) +#define CFG_XHCPMCTRL 0x80a4 +/* BIT[7:4] LFPS periodic sampling for USB3 Ports */ +#define LFPS_PM_DISABLE_MASK 0xFFFFFF0F + const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -829,6 +833,30 @@ static int check_xdci_enable(void) return !!dev->enabled; } +static void disable_xhci_lfps_pm(void) +{ + struct soc_intel_apollolake_config *cfg; + + cfg = config_of_soc(); + + if (cfg->disable_xhci_lfps_pm) { + void *addr; + const struct resource *res; + uint32_t reg; + struct device *xhci_dev = PCH_DEV_XHCI; + + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL); + reg = read32(addr); + printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg); + if (reg) { + reg &= LFPS_PM_DISABLE_MASK; + write32(addr, reg); + printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n"); + } + } +} + void platform_fsp_notify_status(enum fsp_notify_phase phase) { if (phase == END_OF_FIRMWARE) { @@ -876,6 +904,9 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) IOSFGBLCGE; write32(cfg, reg); } + + /* Disable XHCI LFPS power management if the option in dev tree is set. */ + disable_xhci_lfps_pm(); } } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c7974a6cd5..ac36b702ab 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -184,6 +184,14 @@ struct soc_intel_apollolake_config { * the Upd parameter VtdEnable. */ uint8_t enable_vtd; + + /* Options to disable the LFPS periodic sampling for USB3 Ports. + * Default value of PMCTRL_REG bits[7:4] is 9 which means periodic sampling + * interval is 9ms. + * Set 1 to update XHCI host MMIO BAR + PMCTRL_REG (0x80A4 bits[7:4]) to 0 + * 0:Enable (default), 1:Disable. + */ + uint8_t disable_xhci_lfps_pm; }; typedef struct soc_intel_apollolake_config config_t; From 48d5b8d463ceccf5bf38f0d45490cb9d6185979e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 9 Apr 2020 11:44:37 +0200 Subject: [PATCH 0988/1463] nb/intel/i945: Add vboot support Change-Id: I749be0044be04b044ff82e96aff8093f4b0d295e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/40287 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i945/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 2abc201977..4690a54609 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -27,6 +27,10 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP +config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n config NORTHBRIDGE_INTEL_SUBTYPE_I945GM From 05d4bf7ea76114dcbd21f8302e7152f40d806f18 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 28 Oct 2017 16:36:09 +0200 Subject: [PATCH 0989/1463] nb/intel/sandybridge/raminit: Add ECC detection support Add support for detection ECC capability and forced ECC mode. Print the ECC mode in verbose debugging mode. Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a Signed-off-by: Patrick Rudolph Signed-off-by: Alexander Couzens Signed-off-by: Felix Held Signed-off-by: Jonathan A. Kollasch Reviewed-on: https://review.coreboot.org/c/coreboot/+/22214 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/raminit.c | 30 +++++++++++++------ .../intel/sandybridge/raminit_common.c | 26 ++++++++++++++++ .../intel/sandybridge/raminit_common.h | 7 ++++- 3 files changed, 53 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b096a11bf2..a938a49172 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -214,6 +214,23 @@ static void save_timings(ramctr_timing *ctrl) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); } +static void reinit_ctrl(ramctr_timing *ctrl, int min_tck, const u32 cpuid) +{ + /* Reset internal state */ + memset(ctrl, 0, sizeof(*ctrl)); + ctrl->tCK = min_tck; + + /* Get architecture */ + ctrl->cpu = cpuid; + + /* Get ECC support and mode */ + ctrl->ecc_forced = get_host_ecc_forced(); + ctrl->ecc_supported = ctrl->ecc_forced || get_host_ecc_cap(); + printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n", + ctrl->ecc_supported ? "yes" : "no", + ctrl->ecc_forced ? "yes" : "no"); +} + static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; @@ -300,11 +317,10 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) } if (!fast_boot) { /* Reset internal state */ - memset(&ctrl, 0, sizeof(ctrl)); - ctrl.tCK = min_tck; + reinit_ctrl(&ctrl, min_tck, cpuid); - /* Get architecture */ - ctrl.cpu = cpuid; + printk(BIOS_INFO, "ECC RAM %s.\n", ctrl.ecc_forced ? "required" : + ctrl.ecc_supported ? "supported" : "unsupported"); /* Get DDR3 SPD data */ memset(spds, 0, sizeof(spds)); @@ -320,11 +336,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) printram("Disable failing channel.\n"); /* Reset internal state */ - memset(&ctrl, 0, sizeof(ctrl)); - ctrl.tCK = min_tck; - - /* Get architecture */ - ctrl.cpu = cpuid; + reinit_ctrl(&ctrl, min_tck, cpuid); /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4ba5b5900f..9642a55b31 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -437,6 +437,32 @@ static unsigned int get_mmio_size(void) return cfg->pci_mmio_size; } +/* + * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. + * The ME/PCU/.. has the ability to change this. + * Return 0: ECC is optional + * Return 1: ECC is forced + */ +bool get_host_ecc_forced(void) +{ + /* read Capabilities A Register */ + const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); + return !!(reg32 & (1 << 24)); +} + +/* + * Returns the ECC capability. + * The ME/PCU/.. has the ability to change this. + * Return 0: ECC is disabled + * Return 1: ECC is possible + */ +bool get_host_ecc_cap(void) +{ + /* read Capabilities A Register */ + const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); + return !(reg32 & (1 << 25)); +} + void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { u32 reg, val, reclaim, tom, gfxstolen, gttsize; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index fef4419ffc..ea3d66687e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -43,7 +43,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 3 +#define MRC_CACHE_VERSION 4 typedef struct odtmap_st { u16 rttwr; @@ -132,6 +132,8 @@ typedef struct ramctr_timing_st { int pi_code_offset; int pi_coding_threshold; + bool ecc_supported; + bool ecc_forced; int edge_offset[3]; int timC_offset[3]; @@ -191,4 +193,7 @@ void final_registers(ramctr_timing *ctrl); void restore_timings(ramctr_timing *ctrl); int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size); +bool get_host_ecc_cap(void); +bool get_host_ecc_forced(void); + #endif From dd662870dd9da0be937c593b0b62f3b5c8030cf7 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 28 Oct 2017 18:20:11 +0200 Subject: [PATCH 0990/1463] nb/intel/sandybridge/raminit: Add ECC support Add ECC support for native raminit on SandyBridge/IvyBridge. Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a Signed-off-by: Patrick Rudolph Signed-off-by: Jonathan A. Kollasch Reviewed-on: https://review.coreboot.org/c/coreboot/+/22215 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/Kconfig | 6 ++ src/northbridge/intel/sandybridge/raminit.c | 12 ++++ .../intel/sandybridge/raminit_common.c | 58 +++++++++++++++++-- .../intel/sandybridge/raminit_common.h | 11 ++-- .../intel/sandybridge/raminit_native.c | 8 ++- 5 files changed, 85 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 29a6db7fb3..6b7520f27d 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -100,6 +100,12 @@ config DCACHE_RAM_MRC_VAR_SIZE hex default 0x0 +config RAMINIT_ENABLE_ECC + bool "Enable ECC if supported" + default y + help + Enable ECC if supported by both, host and RAM. + endif # USE_NATIVE_RAMINIT if !USE_NATIVE_RAMINIT diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index a938a49172..e138756d9b 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -102,6 +102,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; int channel, slot, spd_slot; + bool can_use_ecc = ctrl->ecc_supported; dimm_info *dimm = &ctrl->info; memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap)); @@ -173,6 +174,9 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; + if (!dimm->dimm[channel][slot].flags.is_ecc) + can_use_ecc = false; + ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; ctrl->extended_temperature_range &= @@ -204,6 +208,14 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) } } + if (ctrl->ecc_forced || CONFIG(RAMINIT_ENABLE_ECC)) + ctrl->ecc_enabled = can_use_ecc; + if (ctrl->ecc_forced && !ctrl->ecc_enabled) + die("ECC mode forced but non-ECC DIMM installed!"); + printk(BIOS_DEBUG, "ECC is %s\n", ctrl->ecc_enabled ? "enabled" : "disabled"); + + ctrl->lanes = ctrl->ecc_enabled ? 9 : 8; + if (!dimms) die("No DIMMs were found"); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9642a55b31..51f33629f1 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -16,7 +16,6 @@ #include "raminit_tables.h" #include "sandybridge.h" -/* FIXME: no ECC support */ /* FIXME: no support for 3-channel chipsets */ /* length: [1..4] */ @@ -309,12 +308,21 @@ void dram_dimm_mapping(ramctr_timing *ctrl) } } -void dram_dimm_set_mapping(ramctr_timing *ctrl) +void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) { int channel; + u32 ecc; + + if (ctrl->ecc_enabled) + ecc = training ? (1 << 24) : (3 << 24); + else + ecc = 0; + FOR_ALL_CHANNELS { - MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel]; + MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; } + + //udelay(10); /* TODO: Might be needed for ECC configurations; so far works without. */ } void dram_zones(ramctr_timing *ctrl, int training) @@ -2120,13 +2128,13 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) lanes_ok |= 1 << lane; } ctr++; - if (lanes_ok == ((1 << NUM_LANES) - 1)) + if (lanes_ok == ((1 << ctrl->lanes) - 1)) break; } ctrl->timings[channel][slotrank] = saved_rt; - return lanes_ok != ((1 << NUM_LANES) - 1); + return lanes_ok != ((1 << ctrl->lanes) - 1); } static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) @@ -3006,6 +3014,46 @@ int channel_test(ramctr_timing *ctrl) return 0; } +void channel_scrub(ramctr_timing *ctrl) +{ + int channel, slotrank, row, rowsize; + + FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { + rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; + for (row = 0; row < rowsize; row += 16) { + + wait_for_iosav(channel); + + /* DRAM command ACT */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) + | 1 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = + row | 0x00060000 | (slotrank << 24); + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000241; + + /* DRAM command WR */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281081; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = row | (slotrank << 24); + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; + + /* DRAM command PRE */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_PRE; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x00280c01; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = + 0x00060400 | (slotrank << 24); + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000240; + + /* execute command queue */ + MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); + + wait_for_iosav(channel); + } + } +} + void set_scrambling_seed(ramctr_timing *ctrl) { int channel; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ea3d66687e..93541b50fd 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -24,7 +24,7 @@ #define NUM_CHANNELS 2 #define NUM_SLOTRANKS 4 #define NUM_SLOTS 2 -#define NUM_LANES 8 +#define NUM_LANES 9 #define NO_RANKSEL (~(1 << 16)) #define IOSAV_MRS (0x1f000) @@ -43,7 +43,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 4 +#define MRC_CACHE_VERSION 5 typedef struct odtmap_st { u16 rttwr; @@ -134,6 +134,8 @@ typedef struct ramctr_timing_st { bool ecc_supported; bool ecc_forced; + bool ecc_enabled; + int lanes; /* active lanes: 8 or 9 */ int edge_offset[3]; int timC_offset[3]; @@ -149,7 +151,7 @@ typedef struct ramctr_timing_st { #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) -#define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++) +#define FOR_ALL_LANES for (lane = 0; lane < ctrl->lanes; lane++) #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) #define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank)) #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel]) @@ -170,7 +172,7 @@ void dram_find_common_params(ramctr_timing *ctrl); void dram_xover(ramctr_timing *ctrl); void dram_timing_regs(ramctr_timing *ctrl); void dram_dimm_mapping(ramctr_timing *ctrl); -void dram_dimm_set_mapping(ramctr_timing *ctrl); +void dram_dimm_set_mapping(ramctr_timing *ctrl, int training); void dram_zones(ramctr_timing *ctrl, int training); unsigned int get_mem_min_tck(void); void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); @@ -193,6 +195,7 @@ void final_registers(ramctr_timing *ctrl); void restore_timings(ramctr_timing *ctrl); int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size); +void channel_scrub(ramctr_timing *ctrl); bool get_host_ecc_cap(void); bool get_host_ecc_forced(void); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index d27914a184..99c1a4c4ff 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -537,7 +537,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); /* Set MAD-DIMM registers */ - dram_dimm_set_mapping(ctrl); + dram_dimm_set_mapping(ctrl, 1); printk(BIOS_DEBUG, "Done dimm mapping\n"); /* Zone config */ @@ -608,7 +608,13 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ err = channel_test(ctrl); if (err) return err; + + if (ctrl->ecc_enabled) + channel_scrub(ctrl); } + /* Set MAD-DIMM registers */ + dram_dimm_set_mapping(ctrl, 0); + return 0; } From 3e4f7a39f8cbdfc7cd097b5c57c43f52d9b0fb4c Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Fri, 10 Jan 2020 13:23:02 -0600 Subject: [PATCH 0991/1463] mainboard: add Supermicro X9SCL/X9SCM Boots to Linux. Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7 To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants) Signed-off-by: Jonathan A. Kollasch Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/x9scl/Kconfig | 55 ++++++ src/mainboard/supermicro/x9scl/Kconfig.name | 2 + src/mainboard/supermicro/x9scl/Makefile.inc | 4 + src/mainboard/supermicro/x9scl/acpi/ec.asl | 0 .../supermicro/x9scl/acpi/platform.asl | 11 ++ .../supermicro/x9scl/acpi/superio.asl | 12 ++ src/mainboard/supermicro/x9scl/acpi_tables.c | 10 + src/mainboard/supermicro/x9scl/board_info.txt | 7 + src/mainboard/supermicro/x9scl/devicetree.cb | 127 ++++++++++++ src/mainboard/supermicro/x9scl/dsdt.asl | 65 +++++++ src/mainboard/supermicro/x9scl/early_init.c | 158 +++++++++++++++ src/mainboard/supermicro/x9scl/gpio.c | 183 ++++++++++++++++++ src/mainboard/supermicro/x9scl/hda_verb.c | 9 + src/mainboard/supermicro/x9scl/x9scl.h | 13 ++ 14 files changed, 656 insertions(+) create mode 100644 src/mainboard/supermicro/x9scl/Kconfig create mode 100644 src/mainboard/supermicro/x9scl/Kconfig.name create mode 100644 src/mainboard/supermicro/x9scl/Makefile.inc create mode 100644 src/mainboard/supermicro/x9scl/acpi/ec.asl create mode 100644 src/mainboard/supermicro/x9scl/acpi/platform.asl create mode 100644 src/mainboard/supermicro/x9scl/acpi/superio.asl create mode 100644 src/mainboard/supermicro/x9scl/acpi_tables.c create mode 100644 src/mainboard/supermicro/x9scl/board_info.txt create mode 100644 src/mainboard/supermicro/x9scl/devicetree.cb create mode 100644 src/mainboard/supermicro/x9scl/dsdt.asl create mode 100644 src/mainboard/supermicro/x9scl/early_init.c create mode 100644 src/mainboard/supermicro/x9scl/gpio.c create mode 100644 src/mainboard/supermicro/x9scl/hda_verb.c create mode 100644 src/mainboard/supermicro/x9scl/x9scl.h diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig new file mode 100644 index 0000000000..df6308e6ba --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -0,0 +1,55 @@ +if BOARD_SUPERMICRO_X9SCL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select RAMINIT_ENABLE_ECC + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SUPERIO_NUVOTON_WPCM450 + select MAINBOARD_USES_IFD_GBE_REGION + +config MAINBOARD_DIR + string + default supermicro/x9scl + +config MAINBOARD_PART_NUMBER + string + default "X9SCL/X9SCM" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config VGA_BIOS_FILE + string + default "pci102b,0532.rom" + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "102b,0532" + +config PXE_ROM_ID + string + depends on PXE + default "8086:10d3" + +config CBFS_SIZE + hex + default 0x400000 + +#config SUPERMICRO_BOARDID +# string +# default "0624" +# +endif diff --git a/src/mainboard/supermicro/x9scl/Kconfig.name b/src/mainboard/supermicro/x9scl/Kconfig.name new file mode 100644 index 0000000000..e0e91f1dae --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SCL + bool "X9SCL/X9SCM" diff --git a/src/mainboard/supermicro/x9scl/Makefile.inc b/src/mainboard/supermicro/x9scl/Makefile.inc new file mode 100644 index 0000000000..3465dfeca6 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c diff --git a/src/mainboard/supermicro/x9scl/acpi/ec.asl b/src/mainboard/supermicro/x9scl/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/supermicro/x9scl/acpi/platform.asl b/src/mainboard/supermicro/x9scl/acpi/platform.asl new file mode 100644 index 0000000000..4c72ad8884 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Method(_WAK, 1) +{ + Return (Package() { 0, 0 }) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/supermicro/x9scl/acpi/superio.asl b/src/mainboard/supermicro/x9scl/acpi/superio.asl new file mode 100644 index 0000000000..0fffbe8aef --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#undef NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#undef NCT6776_SHOW_GPIO +#define NCT6776_SHOW_HWM + +#include diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c new file mode 100644 index 0000000000..3851d04b22 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi_tables.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/supermicro/x9scl/board_info.txt b/src/mainboard/supermicro/x9scl/board_info.txt new file mode 100644 index 0000000000..a14680e826 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb new file mode 100644 index 0000000000..9236f6f3da --- /dev/null +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -0,0 +1,127 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x15d9 0x0624 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 01.1 on end # PEG + device pci 02.0 off end # iGPU + device pci 06.0 on end # PEG + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) + register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) + register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) + register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F) + subsystemid 0x15d9 0x1502 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + device pci 00.0 on end # primary 574 GigE + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on # PCIe Port #7 + device pci 00.0 on end # secondary 574 GigE on X9SCL+-F + end + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on # PCI bridge + device pci 03.0 on end # Matrox G200e in BMC + end + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + io 0x62 = 0x064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.307 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIOBASE + io 0x60 = 0xa80 + end + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 on # GPIO2 + end + device pnp 2e.309 on # GPIO3 + end + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0xa30 + io 0x62 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + chip drivers/ipmi + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 off end # IPMI KCS + end + chip superio/nuvoton/wpcm450 + device pnp 164e.2 on + io 0x60 = 0x03e8 + irq 0x70 = 10 + end + device pnp 164e.3 off end + device pnp 164e.6 off end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl new file mode 100644 index 0000000000..b6c8930cb6 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT Revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20171231 /* OEM Revision */ +) +{ + #include "acpi/platform.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + Device (PCIB) + { + Name (_ADR, 0x001E0000) + Name (_PRW, Package(){ 13, 4 }) + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0003ffff, 0, 0, 0x17 }, + }) + } + Return (Package() { + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } + } + } + + Scope (\_SB.PCI0.PEGP.DEV0) + { + Name (_SUN, 7) + } + + Scope (\_SB.PCI0.PEG1.DEV0) + { + Name (_SUN, 6) + } + + Scope (\_SB.PCI0.PEG6.DEV0) + { + Name (_SUN, 5) + } + + Scope (\_SB.PCI0.RP01) + { + Device (DEV0) + { + Name (_ADR, 0x00000000) + Name (_SUN, 4) + } + } +} diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c new file mode 100644 index 0000000000..b4a39fe11f --- /dev/null +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* FIXME: Check if all includes are needed. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "x9scl.h" + +#define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1) +#define KCS_DEV PNP_DEV(X9SCL_WPCM450_PNP_BASE, 0x11) + +#define SUPERIO_INITVAL(reg, data) {(reg), (data)} +#define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x)) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ + { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ + { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ + { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ + { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ + { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ + { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ + { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ + { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ + { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ + { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ + { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +static const uint8_t superio_initvals[][2] = { + /* Global config registers */ + SUPERIO_INITVAL(0x1a, 0xc8), + SUPERIO_INITVAL(0x1b, 0x68), + SUPERIO_INITVAL(0x1c, 0x83), + SUPERIO_INITVAL(0x24, 0x24), + //SUPERIO_INITVAL(0x27, 0x00), + SUPERIO_INITVAL(0x2a, 0x00), + SUPERIO_INITVAL(0x2b, 0x42), + SUPERIO_INITVAL(0x2c, 0x80), + + SUPERIO_BANK(0x9), /* GPIO[2345] */ + SUPERIO_INITVAL(0x30, 0x0c), + SUPERIO_INITVAL(0xe0, 0xcf), + SUPERIO_INITVAL(0xe4, 0xbd), + SUPERIO_INITVAL(0xe5, 0x42), + SUPERIO_INITVAL(0xe9, 0x10), + SUPERIO_INITVAL(0xea, 0x40), + SUPERIO_INITVAL(0xf0, 0xff), + SUPERIO_INITVAL(0xf1, 0x02), + + SUPERIO_BANK(0xb), /* HWM & LED */ + SUPERIO_INITVAL(0xf7, 0x07), + SUPERIO_INITVAL(0xf8, 0x40), + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0x60, X9SCL_NCT6776_HWM_BASE >> 8), + SUPERIO_INITVAL(0x61, X9SCL_NCT6776_HWM_BASE & 0xff), + + SUPERIO_BANK(0x5), /* KBC */ + SUPERIO_INITVAL(0xf0, 0x83), + SUPERIO_INITVAL(0x30, 0x01), + + SUPERIO_BANK(0x0), /* FDC */ + SUPERIO_INITVAL(0x30, 0x80), + +#if 0 + SUPERIO_BANK(8), + SUPERIO_INITVAL(0x30, 0x0a), + SUPERIO_INITVAL(0x60, X9SCL_NCT6776_GPIO_BASE >> 8), + SUPERIO_INITVAL(0x61, X9SCL_NCT6776_GPIO_BASE & 0xff), + SUPERIO_INITVAL(0xe1, 0xf9), + + SUPERIO_BANK(0xa), + SUPERIO_INITVAL(0xe4, 0x60), +#endif +}; + + +static void superio_init(void) +{ + const pnp_devfn_t dev = PNP_DEV(X9SCL_NCT6776_PNP_BASE, 0); + + nuvoton_pnp_enter_conf_state(dev); + for (size_t i = 0; i < ARRAY_SIZE(superio_initvals); i++) + pnp_write_config(dev, superio_initvals[i][0], superio_initvals[i][1]); + nuvoton_pnp_exit_conf_state(dev); +} + +static void bmc_init(void) +{ + pnp_devfn_t dev = KCS_DEV; + + pnp_write_config(dev, 0x21, 0x11); + + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, X9SCL_WPCM450_KCS_BASE + 0); + pnp_set_iobase(dev, PNP_IDX_IO1, X9SCL_WPCM450_KCS_BASE + 1); + pnp_set_iobase(dev, PNP_IDX_IRQ0, 0); + pnp_set_enable(dev, 1); + +#if 0 + //wpcm450_enable_dev(WPCM450_SP2, X9SCL_WPCM450_PNP_BASE, 0x03e8); + //wpcm450_enable_dev(WPCM450_SP1, X9SCL_WPCM450_PNP_BASE, 0x02e8); +#endif + +#if 0 + dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x03e8); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x02e8); + pnp_set_enable(dev, 0); +#endif +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + superio_init(); + bmc_init(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_early_init(int s3resume) +{ + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); +} diff --git a/src/mainboard/supermicro/x9scl/gpio.c b/src/mainboard/supermicro/x9scl/gpio.c new file mode 100644 index 0000000000..04ea4825fe --- /dev/null +++ b/src/mainboard/supermicro/x9scl/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio7 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9scl/hda_verb.c b/src/mainboard/supermicro/x9scl/hda_verb.c new file mode 100644 index 0000000000..57c3cff83a --- /dev/null +++ b/src/mainboard/supermicro/x9scl/hda_verb.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9scl/x9scl.h b/src/mainboard/supermicro/x9scl/x9scl.h new file mode 100644 index 0000000000..05723145dc --- /dev/null +++ b/src/mainboard/supermicro/x9scl/x9scl.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef X9SCL_H +#define X9SCL_H + +#define X9SCL_NCT6776_PNP_BASE 0x002e +#define X9SCL_NCT6776_HWM_BASE 0x0a30 +#define X9SCL_NCT6776_GPIO_BASE 0x0a80 +#define X9SCL_WPCM450_KCS_BASE 0x0ca2 +#define X9SCL_WPCM450_PNP_BASE 0x164e + +#endif /* X9SCL_H */ From a6b887e017f2310db79067b18b216036907b2d90 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 28 Dec 2019 19:10:12 +0100 Subject: [PATCH 0992/1463] src/Kconfig: enable USE_BLOBS by default To provide sane defaults for most of the user base, this patch switches on the USE_BLOBS option by default. Since it only changes the default, this behaviour can still be easily disabled. With this abuild doesn't have to select USE_BLOBS any more, so what abuild tests becomes the coreboot default again. Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/37972 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/Kconfig | 1 + util/abuild/abuild | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index da21af1dd1..cf4df18247 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -226,6 +226,7 @@ config TIMESTAMPS_ON_CONSOLE config USE_BLOBS bool "Allow use of binary-only repository" + default y help This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. diff --git a/util/abuild/abuild b/util/abuild/abuild index f55dadc71b..3b8612119f 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -720,7 +720,7 @@ while true ; do shift;; -B|--blobs) shift customizing="${customizing}, blobs" - configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\n" + configoptions="${configoptions}CONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\n" ;; -A|--any-toolchain) shift customizing="${customizing}, any-toolchain" From 895c77f361e9d44849cc00eac5a094371fecfc8c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 22 Nov 2019 17:36:40 +0100 Subject: [PATCH 0993/1463] Documentation/vboot: Drop deprecated options from example 4K keys are now default. Change-Id: I16599d0e8b874f9e8a56100fea06d6e4f94a5c00 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37149 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/security/vboot/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index 997db8be80..ff2261a669 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -231,7 +231,7 @@ More details are available in `3rdparty/vboot/README`. # The keys were made using the following command # # 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \ -# --4k --4k-root --output $PWD/keys +# --output $PWD/keys # # # The "magic" numbers below are derived from the GBB section in From 0fdd9fd2aaaa00e0dd5bd353bb7324a1380d6ca5 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 27 Mar 2020 08:38:51 +0100 Subject: [PATCH 0994/1463] mb/ocp/tiogapass: Add missing spaces around operators Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f Fixes: b75bcc978a ("mb/ocp/tiogapass: Properly configure early serial output") Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Andrey Petrov --- src/mainboard/ocp/tiogapass/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index d9a86e99f0..d507422d30 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -29,7 +29,7 @@ static void enable_espi_lpc_io_windows(void) /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ pci_mmio_write_config32(PCH_DEV_LPC, 0x80, - (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); + (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); } static uint8_t com_to_ast_sio(uint8_t com) From 71e2b2903aaf8a25d6cffda128201b46a6728014 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 10 Apr 2020 11:52:28 +0200 Subject: [PATCH 0995/1463] mb/google/poppy/variants/nami: Use tabs for alignment Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39 Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table") Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../poppy/variants/nami/include/variant/acpi/dptf.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl index ba089dd5b3..b05e236d6f 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl @@ -23,11 +23,11 @@ #define DPTF_TSR1_SENSOR_NAME "Thermal_Sensor_Remote_PMIC" #define DPTF_TSR1_PASSIVE 75 #define DPTF_TSR1_CRITICAL 125 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Thermal_Sensor_Remote_CPU" From aecbe7a988265c0621a118368d7c189b12779dd4 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 10 Apr 2020 11:54:47 +0200 Subject: [PATCH 0996/1463] mb/google/hatch: Use tabs for alignment Change-Id: I38d429245810f64a03253b5076391af843f8d0de Fixes: e2ac5b7a36 ("mb/google/hatch/variants: Add DPTF based Fan control") Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../hatch/variants/akemi/include/variant/acpi/dptf.asl | 6 +++--- .../variants/baseboard/include/baseboard/acpi/dptf.asl | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl index d1e19485b5..65eab2b706 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -25,9 +25,9 @@ #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 38 #define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 42 -#define DPTF_TSR1_ACTIVE_AC1 40 -#define DPTF_TSR1_ACTIVE_AC2 38 +#define DPTF_TSR1_ACTIVE_AC0 42 +#define DPTF_TSR1_ACTIVE_AC1 40 +#define DPTF_TSR1_ACTIVE_AC2 38 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU" diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index 76b2615b40..3a70d1bd79 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -23,11 +23,11 @@ #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL From 3ba64ca3d1b055d8b4f788bc1eff4d4fedc2ec24 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 20 Mar 2020 12:17:14 -0700 Subject: [PATCH 0997/1463] soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters Signed-off-by: Wonkyu Kim Change-Id: I63cec8a718285f424914e426d0399ed821588dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 231399c676..78cfb9f004 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -97,6 +98,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000; + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosInterface = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosInterface = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + } + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; From 53e82f67eabbc64f8344e97a066fbc7c619b5dd6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 10 Apr 2020 15:00:15 +0530 Subject: [PATCH 0998/1463] mb/intel/{jasperlake_rvp, tglrvp}: Remove unused files This patch removes unused "spd_util.c" files from mainboard directory. Change-Id: Ibd011be578fa256afb61796d5ceeea073e852fe9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/40304 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Maulik V Vaghela Reviewed-by: Aamir Bohra --- .../intel/jasperlake_rvp/spd/spd_util.c | 121 ----------------- src/mainboard/intel/tglrvp/spd/spd_util.c | 123 ------------------ 2 files changed, 244 deletions(-) delete mode 100644 src/mainboard/intel/jasperlake_rvp/spd/spd_util.c delete mode 100644 src/mainboard/intel/tglrvp/spd/spd_util.c diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c deleted file mode 100644 index bc891fbab7..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include -#include -#include - -#include "../board_id.h" -#include "spd.h" - -enum jsl_dimm_type { - jsl_u_ddr4 = 0, - jsl_u_lpddr4 = 1, - jsl_u_lpddr4_type_3 = 4, - jsl_y_lpddr4 = 6 -}; - -void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr) -{ - /* DQ byte map Ch0 */ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -static uint8_t get_spd_index(void) -{ - return get_board_id() & 0x7; -} - -void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr) -{ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; - const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; - const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - - switch (get_spd_index()) { - case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case jsl_u_lpddr4: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, - sizeof(dqs_map_u_lpddr_type_3)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; - const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; - - switch (get_spd_index()) { - case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 100, 100, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { - 100, 33, 32, 33, 28 }; - static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { - 80, 40, 40, 40, 30 }; - - switch (get_spd_index()) { - case jsl_u_ddr4: - memcpy(rcomp_strength_ptr, RcompTarget_DDR4, - sizeof(RcompTarget_DDR4)); - break; - case jsl_y_lpddr4: - case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: - memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, - sizeof(RcompTarget_LPDDR4_Ax)); - break; - default: - break; - } -} diff --git a/src/mainboard/intel/tglrvp/spd/spd_util.c b/src/mainboard/intel/tglrvp/spd/spd_util.c deleted file mode 100644 index 9110cb1b1b..0000000000 --- a/src/mainboard/intel/tglrvp/spd/spd_util.c +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include -#include -#include - -#include "../board_id.h" -#include "spd.h" - -enum tgl_dimm_type { - tgl_u_ddr4 = 0, - tgl_u_lpddr4 = 1, - tgl_u_lpddr4_type_3 = 4, - tgl_y_lpddr4 = 6 -}; - -static uint8_t get_spd_index(void) -{ - uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; - - return spd_index; -} - -void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr) -{ - /* DQ byte map Ch0 */ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr) -{ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; - const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; - const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - - switch (get_spd_index()) { - case tgl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case tgl_u_lpddr4: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case tgl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, - sizeof(dqs_map_u_lpddr_type_3)); - break; - case tgl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; - const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; - - switch (get_spd_index()) { - case tgl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case tgl_u_lpddr4: - case tgl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case tgl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 100, 100, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { - 100, 33, 32, 33, 28 }; - static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { - 80, 40, 40, 40, 30 }; - - switch (get_spd_index()) { - case tgl_u_ddr4: - memcpy(rcomp_strength_ptr, RcompTarget_DDR4, - sizeof(RcompTarget_DDR4)); - break; - case tgl_y_lpddr4: - case tgl_u_lpddr4: - case tgl_u_lpddr4_type_3: - memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, - sizeof(RcompTarget_LPDDR4_Ax)); - break; - default: - break; - } -} From 3fe5f2cfa4a091b237562851796d1415451d462f Mon Sep 17 00:00:00 2001 From: Dtrain Hsu Date: Tue, 7 Apr 2020 10:21:59 +0800 Subject: [PATCH 0999/1463] mb/google/dedede: Enable SIS touchscreen for Waddledoo Add SiS9813 USI touchscreen support. BUG=b:152936541 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250 Reviewed-by: Marco Chen Reviewed-by: Karthik Ramasubramanian Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../google/dedede/variants/baseboard/gpio.c | 8 ++++---- .../dedede/variants/waddledoo/overridetree.cb | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 89683bd754..d12d2c464d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -29,7 +29,7 @@ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_NC(GPP_A10, NONE), /* A11 : TOUCH_RPT_EN */ - PAD_NC(GPP_A11, NONE), + PAD_CFG_GPO(GPP_A11, 0, DEEP), /* A12 : USB_OC1_N */ PAD_NC(GPP_A12, NONE), /* A13 : USB_OC2_N */ @@ -154,11 +154,11 @@ static const struct pad_config gpio_table[] = { /* D3 : WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_D3, NONE, DEEP, EDGE_SINGLE), /* D4 : TOUCH_INT_ODL */ - PAD_NC(GPP_D4, NONE), + PAD_CFG_GPI_APIC(GPP_D4, NONE, PLTRST, LEVEL, INVERT), /* D5 : TOUCH_RESET_L */ - PAD_NC(GPP_D5, NONE), + PAD_CFG_GPO(GPP_D5, 0, DEEP), /* D6 : EN_PP3300_TOUCH_S0 */ - PAD_NC(GPP_D6, NONE), + PAD_CFG_GPO(GPP_D6, 0, DEEP), /* D7 : EMR_INT_ODL */ PAD_NC(GPP_D7, NONE), /* D8 : GPP_D8/GSPI2_CS0B/UART0A_RXD */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index cb21c63b0f..cc9e651252 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -55,6 +55,25 @@ chip soc/intel/jasperlake device i2c 15 on end end end #I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""SIS6496"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "100" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end # I2C 2 device pci 1c.7 on chip drivers/intel/wifi register "wake" = "GPE0_DW2_03" From afc593d99cb156b982b24262503a56568b7de614 Mon Sep 17 00:00:00 2001 From: Dtrain Hsu Date: Tue, 7 Apr 2020 10:45:57 +0800 Subject: [PATCH 1000/1463] mb/google/dedede: Enable ELAN touchscreen for Waddledoo Add ELAN EKTH6918 USI touchscreen support. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Karthik Ramasubramanian Reviewed-by: EricR Lai --- .../dedede/variants/waddledoo/overridetree.cb | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index cc9e651252..920c1792fa 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -73,6 +73,26 @@ chip soc/intel/jasperlake register "hid_desc_reg_offset" = "0x00" device i2c 5c on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end end # I2C 2 device pci 1c.7 on chip drivers/intel/wifi From 9e0dd9af47ec73e03c8c36dfe691abd795dc0903 Mon Sep 17 00:00:00 2001 From: Julia Tsai Date: Fri, 27 Mar 2020 15:52:30 +0800 Subject: [PATCH 1001/1463] mb/google/octopus/variants/lick: Disable xHCI compliance mode Since the first LFPS timeout causes xHCI to enter compliance mode, the SS hub cannot be enumerated. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:153782196 TEST=Verified usb operation successfully. Signed-off-by: Julia Tsai Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874 Reviewed-by: Henry Sun Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/lick/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index 3aa369e9b2..3ade35402f 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -112,4 +112,8 @@ chip soc/intel/apollolake end end # - I2C 6 end + + # Disable compliance mode + + register "DisableComplianceMode" = "1" end From 72d93667212b0315a323b073d2f6334462377d2c Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 3 Apr 2020 13:39:24 +0800 Subject: [PATCH 1002/1463] mb/google/deltaur: Enable Melfas touch screen for Deltan Reference Drallion to add device tree for Melfas touch screen. BUG=b:152924290 Signed-off-by: Eric Lai Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../deltaur/variants/deltan/overridetree.cb | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb index 6a2719b960..be1f29f2f2 100644 --- a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -9,4 +9,23 @@ chip soc/intel/tigerlake device pci 1f.6 on end # GbE 0x15FC end + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E1_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "5" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "stop_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" + register "has_power_resource" = "1" + register "device_present_gpio" = "GPP_B4" + register "device_present_gpio_invert" = "1" + device i2c 34 on end + end + end # I2C #0 end From 17277ff6580e054eb7ac33f46c3c58c4bee9e886 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 31 Mar 2020 21:55:35 -0700 Subject: [PATCH 1003/1463] soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT. Fix the scope type to be PCI_SUB. BUG=b:141609884 TEST=Booted to kernel and verified no TBT PCIE root ports scope type mismatch error in kernel log. Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 9e7ff56752..36c488b575 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -235,7 +235,7 @@ static unsigned long soc_fill_dmar(unsigned long current) unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); - current += acpi_create_dmar_ds_pci(current, 0, 7, i); + current += acpi_create_dmar_ds_pci_br(current, 0, 7, i); acpi_dmar_drhd_fixup(tmp, current); } From aee0baf0690681fae85d24e6887d6cbb9209de83 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Sun, 12 Apr 2020 16:00:58 +0900 Subject: [PATCH 1004/1463] mb/google/nightfury: Update tdp_pl1_override value Update tdp_pl1_override value to 15W for CML-U based nightfury platform. BUG=None BRANCH=firmware-hatch-12672.B TEST=Built Signed-off-by: Seunghwan Kim Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Patrick Georgi --- src/mainboard/google/hatch/variants/nightfury/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index a940f8bc19..4b985d933e 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -1,5 +1,5 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "8" + register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "51" register "SerialIoDevMode" = "{ From ef43711aadcaf61ed1234035afc2e0282bb94e97 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 13 Apr 2020 15:24:22 -0700 Subject: [PATCH 1005/1463] trogdor: Add third RAM_CODE pin We decided to add a third RAM_CODE pin to the Trogdor family for devices after rev1. This patch adds support to read it. Since the newly used pin was previously unconnected (not pulled down) on rev1, this will change the RAM_CODE result for previous versions (and actually make it undetermined until we enable tri-state). But since we're not actually using RAM_CODE for anything yet, and since those are development revisions that will eventually be discontinued, this should be fine. Signed-off-by: Julius Werner Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Philip Chen --- src/mainboard/google/trogdor/boardid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index 9d92988362..1b3a269b67 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -20,7 +20,7 @@ uint32_t ram_code(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[1] = GPIO(91), [0] = GPIO(29)}; + const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(91), [0] = GPIO(29)}; if (id == UNDEFINED_STRAPPING_ID) id = gpio_base2_value(pins, ARRAY_SIZE(pins)); From 4f176913c102599c59c98c0729cc198ad19adda4 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 17 Jan 2020 18:47:11 +1100 Subject: [PATCH 1006/1463] mainboard/puff: Tune ALC5682I rise_fall times on i2c Tunes the headphone amp i2c with measured signal shape. BUG=b:147192377 BRANCH=none TEST=builds and measured i2c frequency below 400khz Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Edward O'Callaghan Reviewed-by: Daniel Kurtz Reviewed-by: Paul Menzel --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index bf9120adbc..3507e6d5eb 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -161,8 +161,8 @@ chip soc/intel/cannonlake }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" From b894ad5233c043f7b9c10ca3bff5cd9841c7ad64 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 22 Nov 2019 15:20:59 +0100 Subject: [PATCH 1007/1463] mb/lenovo/x60: Add vboot support It's relatively slow to boot. It takes 1.5s to get to the payload. In timestamps there are entries related to TPM, which are somewhat weird given that the TPM is not enabled on this device (buggy). TESTED: boot X60, with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y you can force the recovery bootpath. Change-Id: Ia9666194e98b7d23b97eaff08e6177684e35eca7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37148 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/x60/Kconfig | 18 ++++++++++++++++++ src/mainboard/lenovo/x60/cmos.layout | 2 ++ src/mainboard/lenovo/x60/vboot-rwa.fmd | 19 +++++++++++++++++++ 3 files changed, 39 insertions(+) create mode 100644 src/mainboard/lenovo/x60/vboot-rwa.fmd diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 994a071fa3..5083fd50fd 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,24 @@ config BOARD_SPECIFIC_OPTIONS select I945_LVDS select INTEL_GMA_HAVE_VBT +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x76 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_DIR string default "lenovo/x60" diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 58fbef590a..a402f05b83 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -93,6 +93,8 @@ entries 1040 8 r 0 RCVENMT 1048 4 r 0 C0DRT1 1052 4 r 0 C1DRT1 + +1056 128 r 0 vbnv # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x60/vboot-rwa.fmd b/src/mainboard/lenovo/x60/vboot-rwa.fmd new file mode 100644 index 0000000000..b21cff3b3a --- /dev/null +++ b/src/mainboard/lenovo/x60/vboot-rwa.fmd @@ -0,0 +1,19 @@ +FLASH@0xffe00000 0x200000 { + BIOS { + RW_SECTION_A 0x100000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + CONSOLE 0x10000 + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} From 609b7fb3034e4cb3d5e75e00b8f6021a0e5c6691 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 2 Apr 2020 10:42:03 +1100 Subject: [PATCH 1008/1463] mb/google/puff: Fix up WLAN_OFF gpio configuration BUG=b:152927525 BRANCH=none TEST=builds Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027 Tested-by: build bot (Jenkins) Reviewed-by: Tim Chen Reviewed-by: Daniel Kurtz --- src/mainboard/google/hatch/variants/puff/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c index 8e4f170d4f..60842a4e54 100644 --- a/src/mainboard/google/hatch/variants/puff/gpio.c +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -28,6 +28,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : PCH_PCON_PDB_ODL */ PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* E2 : EN_PP_MST_OD */ PAD_CFG_GPO(GPP_E2, 1, DEEP), From 1ad73926f2e0c1b0e9d6cdc2064d4555dda1c330 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 14 Apr 2020 02:07:19 +0200 Subject: [PATCH 1009/1463] soc/amd/common/block/psp: move psp_load_named_blob to psp_gen1.c This function is only needed and valid for the 1st generation PSP interface used on stoneyridge. BUG=b:153677737 Change-Id: Ia1be09c32271fe9480a0acbe324c4a45d8620882 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40360 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/soc/amd/common/block/psp/psp.c | 59 ++----------------------- src/soc/amd/common/block/psp/psp_def.h | 2 + src/soc/amd/common/block/psp/psp_gen1.c | 54 ++++++++++++++++++++++ 3 files changed, 59 insertions(+), 56 deletions(-) diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 22404be6d6..479c28bc33 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -3,8 +3,6 @@ #include #include -#include -#include #include #include #include @@ -50,7 +48,7 @@ static u32 rd_resp_sts(struct mbox_default_buffer *buffer) * Print meaningful status to the console. Caller only passes a pointer to a * buffer if it's expected to contain its own status. */ -static void print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer) +void psp_print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer) { if (buffer && rd_resp_sts(buffer)) printk(BIOS_DEBUG, "buffer status=0x%x ", rd_resp_sts(buffer)); @@ -79,7 +77,7 @@ int psp_notify_dram(void) cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); /* buffer's status shouldn't change but report it if it does */ - print_cmd_status(cmd_status, &buffer); + psp_print_cmd_status(cmd_status, &buffer); return cmd_status; } @@ -103,58 +101,7 @@ static void psp_notify_boot_done(void *unused) cmd_status = send_psp_command(MBOX_BIOS_CMD_BOOT_DONE, &buffer); /* buffer's status shouldn't change but report it if it does */ - print_cmd_status(cmd_status, &buffer); -} - -/* - * Tell the PSP to load a firmware blob from a location in the BIOS image. - */ -int psp_load_named_blob(enum psp_blob_type type, const char *name) -{ - int cmd_status; - u32 command; - void *blob; - struct cbfsf cbfs_file; - struct region_device rdev; - - switch (type) { - case BLOB_SMU_FW: - command = MBOX_BIOS_CMD_SMU_FW; - break; - case BLOB_SMU_FW2: - command = MBOX_BIOS_CMD_SMU_FW2; - break; - default: - printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); - return -PSPSTS_INVALID_BLOB; - } - - /* type can only be BLOB_SMU_FW or BLOB_SMU_FW2 here, so don't re-check for this */ - if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { - printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); - return -PSPSTS_UNSUPPORTED; - } - - if (cbfs_boot_locate(&cbfs_file, name, NULL)) { - printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); - return -PSPSTS_INVALID_NAME; - } - - cbfs_file_data(&rdev, &cbfs_file); - blob = rdev_mmap_full(&rdev); - if (!blob) { - printk(BIOS_ERR, "BUG: Cannot map blob for PSP loading\n"); - return -PSPSTS_INVALID_NAME; - } - - printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, blob); - - /* Blob commands use the buffer registers as data, not pointer to buf */ - cmd_status = send_psp_command(command, blob); - print_cmd_status(cmd_status, NULL); - - rdev_munmap(&rdev, blob); - return cmd_status; + psp_print_cmd_status(cmd_status, &buffer); } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 37755166f0..f3ac5c2181 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -89,6 +89,8 @@ struct mbox_cmd_sx_info_buffer { #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */ +void psp_print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer); + /* This command needs to be implemented by the generation specific code. */ int send_psp_command(u32 command, void *buffer); diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 0e5aa30154..b707933553 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -2,8 +2,11 @@ /* This file is part of the coreboot project. */ #include +#include +#include #include #include +#include #include #include #include @@ -91,3 +94,54 @@ int send_psp_command(u32 command, void *buffer) return 0; } + +/* + * Tell the PSP to load a firmware blob from a location in the BIOS image. + */ +int psp_load_named_blob(enum psp_blob_type type, const char *name) +{ + int cmd_status; + u32 command; + void *blob; + struct cbfsf cbfs_file; + struct region_device rdev; + + switch (type) { + case BLOB_SMU_FW: + command = MBOX_BIOS_CMD_SMU_FW; + break; + case BLOB_SMU_FW2: + command = MBOX_BIOS_CMD_SMU_FW2; + break; + default: + printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); + return -PSPSTS_INVALID_BLOB; + } + + /* type can only be BLOB_SMU_FW or BLOB_SMU_FW2 here, so don't re-check for this */ + if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { + printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); + return -PSPSTS_UNSUPPORTED; + } + + if (cbfs_boot_locate(&cbfs_file, name, NULL)) { + printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); + return -PSPSTS_INVALID_NAME; + } + + cbfs_file_data(&rdev, &cbfs_file); + blob = rdev_mmap_full(&rdev); + if (!blob) { + printk(BIOS_ERR, "BUG: Cannot map blob for PSP loading\n"); + return -PSPSTS_INVALID_NAME; + } + + printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, blob); + + /* Blob commands use the buffer registers as data, not pointer to buf */ + cmd_status = send_psp_command(command, blob); + psp_print_cmd_status(cmd_status, NULL); + + rdev_munmap(&rdev, blob); + return cmd_status; +} From 0c70b4ac117fb3e92aec4ffb81723a9c4d9da1e8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 13 Apr 2020 22:38:13 +0200 Subject: [PATCH 1010/1463] soc/amd/common/psp: add Kconfig description to interface version BUG=b:153677737 Change-Id: I5b017dfc92563ec4f0a2edb24416d6b65587d9a3 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40361 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/soc/amd/common/block/psp/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 9466cc6abd..bf0477b5ac 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -10,11 +10,15 @@ config SOC_AMD_COMMON_BLOCK_PSP_GEN1 bool default n select SOC_AMD_COMMON_BLOCK_PSP + help + Used by the PSP in AMD systems before fam17h, e.g. stoneyridge. config SOC_AMD_COMMON_BLOCK_PSP_GEN2 bool default n select SOC_AMD_COMMON_BLOCK_PSP + help + Used by the PSP in AMD fam17h CPUs and possibly newer ones. config SOC_AMD_PSP_SELECTABLE_SMU_FW bool From 5a73fc35e23b15b0a80e2a26553953764907be1d Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 24 Jan 2020 09:42:57 -0700 Subject: [PATCH 1011/1463] soc/amd/picasso: Add common PSP support Add a new psp.c file so the base address can be determined, and select the common/block/psp feature. BUG=b:153677737 Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/2020368 Tested-by: Eric Peers Reviewed-by: Eric Peers Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296 Reviewed-by: Raul Rangel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/Makefile.inc | 3 +++ src/soc/amd/picasso/psp.c | 22 ++++++++++++++++++++++ 3 files changed, 26 insertions(+) create mode 100644 src/soc/amd/picasso/psp.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d9211b4fb6..842ba0cd37 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 2f4f00bc04..b79f6274b3 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -44,6 +44,7 @@ romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += soc_util.c +romstage-y += psp.c verstage-y += gpio.c verstage-y += i2c.c @@ -76,6 +77,7 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c +ramstage-y += psp.c all-y += reset.c @@ -84,6 +86,7 @@ smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c +smm-y += psp.c CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c new file mode 100644 index 0000000000..d6eb7d31a3 --- /dev/null +++ b/src/soc/amd/picasso/psp.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +#define PSP_MAILBOX_OFFSET 0x10570 +#define MSR_CU_CBBCFG 0xc00110a2 + +void *soc_get_mbox_address(void) +{ + uintptr_t psp_mmio; + + psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; + if (psp_mmio == 0xffffffff) { + printk(BIOS_WARNING, "PSP: MSR_CU_CBBCFG uninitialized\n"); + return 0; + } + + return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); +} From 9ff2af2b479e699a77cdb5de3835be25129c37ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 13 Apr 2020 20:37:36 +0200 Subject: [PATCH 1012/1463] sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CLKRUN_EN bit available for mobile is reserved on desktop SKUs. PSEUDO_CLKRUN_EN bit available for desktop is reserved for mobile SKUs. Configure these bits accordign to SKU. Signed-off-by: Michał Żygowski Change-Id: I5295eb2bec27c77f800cc2ade9093e97ede47789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40347 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/bd82x6x/lpc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 27f45e359b..278e90ac00 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -20,6 +20,7 @@ #include "chip.h" #include "pch.h" #include "nvs.h" +#include #include #include #include @@ -373,7 +374,12 @@ static void enable_clock_gating(struct device *dev) RCBA32_AND_OR(DMIC, ~0UL, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 2) | (1 << 11); + reg16 &= ~(3 << 2); /* Clear CLKRUN bits for mobile and desktop */ + if (get_platform_type() == PLATFORM_MOBILE) + reg16 |= (1 << 2); /* CLKRUN_EN for mobile */ + else if (get_platform_type() == PLATFORM_DESKTOP_SERVER) + reg16 |= (1 << 3); /* PSEUDO_CLKRUN_EN for desktop */ + reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); From 63be06008d439cba7cb113df20faf23ed76e4b79 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 13 Feb 2019 15:11:09 +0100 Subject: [PATCH 1013/1463] sb/intel/bd82x6x/sata: Add legacy mode support Legacy mode is supposed to help with IDE controller drivers that don't know Intel's "native" IDE interface. We extend the `sata_mode` NVRAM variable to provide the following choices: * 0 "AHCI" - AHCI interface * 1 "Compatible" - Intel's "native" interface * 2 "Legacy" - Legacy interface Change-Id: I0e7a4befa02772f620602fa2a92c3583895d4d1c Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39828 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/sata.c | 77 +++++++++++++++++++++++++--- 1 file changed, 70 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index c1b61f24c6..6c6e5be598 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -28,6 +28,65 @@ static inline void sir_write(struct device *dev, int idx, u32 value) pci_write_config32(dev, SATA_SIRD, value); } +static void sata_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + /* Assign fixed resources for IDE legacy mode */ + + u8 sata_mode = 0; + get_option(&sata_mode, "sata_mode"); + if (sata_mode != 2) + return; + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + res->base = 0x1f0; + res->size = 8; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + res->base = 0x3f4; + res->size = 4; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res) { + res->base = 0x170; + res->size = 8; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + + res = find_resource(dev, PCI_BASE_ADDRESS_3); + if (res) { + res->base = 0x374; + res->size = 4; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } +} + +static void sata_set_resources(struct device *dev) +{ + /* work around bug in pci_dev_set_resources(), it bails out on FIXED */ + u8 sata_mode = 0; + get_option(&sata_mode, "sata_mode"); + if (sata_mode == 2) { + unsigned int i; + for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) { + struct resource *const res = find_resource(dev, i); + if (res) + res->flags &= ~IORESOURCE_FIXED; + } + } + + pci_dev_set_resources(dev); +} + static void sata_init(struct device *dev) { u32 reg32; @@ -112,17 +171,21 @@ static void sata_init(struct device *dev) write32(abar + 0xa0, reg32); } else { /* IDE */ - printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* Without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - /* Native mode capable on both primary and secondary (0xa) - * or'ed with enabled (0x50) = 0xf - */ - pci_write_config8(dev, 0x09, 0x8f); + if (sata_mode == 1) { + /* Native mode on both primary and secondary. */ + pci_or_config8(dev, 0x09, 0x05); + printk(BIOS_DEBUG, "SATA: Controller in IDE compat mode.\n"); + } else { + /* Legacy mode on both primary and secondary. */ + pci_update_config8(dev, 0x09, ~0x05, 0x00); + printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n"); + } /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | @@ -234,8 +297,8 @@ static struct pci_operations sata_pci_ops = { }; static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = sata_read_resources, + .set_resources = sata_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = sata_fill_ssdt, .init = sata_init, From 6d2a51eb850e7d86da0f7c3269cae606a68cbd78 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 13 Apr 2020 10:17:15 -0600 Subject: [PATCH 1014/1463] cpu/x86/acpi: Add assignments to ACPI_Sn enums Explicitly assign numerical values to the enumerated sleep state values. BUG=b:153854742 Signed-off-by: Marshall Dawson Change-Id: I1de2e7f65a2dc3f8a9a1c5fd83d164871a4a2b96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40338 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/arch/x86/include/arch/acpi.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 0ed89d1b12..fc250d7da0 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -979,13 +979,14 @@ void acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); +/* ACPI_Sn assignments are defined to always equal the sleep state numbers */ enum { - ACPI_S0, - ACPI_S1, - ACPI_S2, - ACPI_S3, - ACPI_S4, - ACPI_S5, + ACPI_S0 = 0, + ACPI_S1 = 1, + ACPI_S2 = 2, + ACPI_S3 = 3, + ACPI_S4 = 4, + ACPI_S5 = 5, }; #if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ From 31fef3f6f8a417c80bdcbebfe99d05adbb197389 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 9 Mar 2020 14:07:28 +0530 Subject: [PATCH 1015/1463] mb/intel/jasperlake_rvp: Update JSLRVP USB configuration Remove extra USB port entry because it came in from copy patch from the previous board and configure USB over-current pins as per JSLRVP. Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403 Reviewed-by: V Sowmya Reviewed-by: Aamir Bohra Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- .../variants/jslrvp/devicetree.cb | 38 +++++++------------ 1 file changed, 13 insertions(+), 25 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index e8fc451661..f5915046ca 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -30,22 +30,20 @@ chip soc/intel/jasperlake register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1" - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # USB2 Type A port1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN + register "usb2_ports[6]" = "USB2_PORT_MID(OC2)" # USB2 Type A port3 + register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # USB3 WWAN + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # UNUSED register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED # Enable Pch iSCLK @@ -195,16 +193,6 @@ chip soc/intel/jasperlake register "type" = "UPC_TYPE_A" device usb 2.7 on end end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.9 on end - end chip drivers/usb/acpi register "desc" = ""USB3/2 Type-A Left Lower"" register "type" = "UPC_TYPE_A" From 68da241ba40f41f4331b3b6df50b0397ace7c562 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Apr 2020 16:30:27 +0200 Subject: [PATCH 1016/1463] soc/intel/apl/report_platform.c: Fix typo "Aplollolake" => "Apollolake" Change-Id: I1881d40b5f71d07d5d217b4380241cc14467fb1a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40407 Reviewed-by: Patrick Rudolph Reviewed-by: Subrata Banik Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/report_platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c index bd0a68fb44..bb20ab506c 100644 --- a/src/soc/intel/apollolake/report_platform.c +++ b/src/soc/intel/apollolake/report_platform.c @@ -46,7 +46,7 @@ static struct { const char *name; } igd_table[] = { { PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, "Apollolake HD 505" }, - { PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, "Aplollolake HD 500" }, + { PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, "Apollolake HD 500" }, { PCI_DEVICE_ID_INTEL_GLK_IGD, "Geminilake" }, { PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, "Geminilake EU12" }, }; From 0b50099c8bd694a67737ff47e56a831e3eeafed9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Apr 2020 16:47:36 +0200 Subject: [PATCH 1017/1463] MAINTAINERS: Fix a comment A space was missing before the asterisks. Change-Id: I1cb62a9efc8e15c09cdebb49956f0edeb032beb3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40410 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Felix Held --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7ea4aa357e..8a49fb3259 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -596,7 +596,7 @@ MISSING: ELOG MISSING: SPI -# *** Infrastructure Owners*** +# *** Infrastructure Owners *** # This is intended to let people know who they should contact for issues with various infrastructure pieces. # Hardware # Owners: Stefan, Patrick From 374d7c2e94ce4bc8520368ee0f0aa9d0e44a56ca Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 27 Mar 2020 20:56:40 +0100 Subject: [PATCH 1018/1463] Do not select USE_BLOBS The `USE_BLOBS` config only exists for idealistic reasons. If we would allow us to use blobs by default, we wouldn't need that option and could just always do it. It's generally debatable for the project as a whole, but not per board/subject. Change-Id: I8591862699aef02e5a4ede32655fc82c44c97555 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39884 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/mainboard/pcengines/apu2/Kconfig | 1 - src/mainboard/system76/lemp9/Kconfig | 1 - src/mainboard/up/squared/Kconfig | 1 - src/security/intel/stm/Kconfig | 1 - 4 files changed, 4 deletions(-) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 1915cc22d7..4321c5cfef 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 - select USE_BLOBS select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index d8146332fe..cc21ca9575 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP - select USE_BLOBS select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB config MAINBOARD_DIR diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index 542e8c3c20..5104713022 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -2,7 +2,6 @@ if BOARD_UP_SQUARED config BOARD_SPECIFIC_OPTIONS def_bool y - select USE_BLOBS select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select INTEL_GMA_HAVE_VBT diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index 618217f686..f7dd363faa 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -3,7 +3,6 @@ config STM default n depends on ENABLE_VMX depends on SMM_TSEG - select USE_BLOBS help Enabling the STM will load a simple hypervisor into SMM that will From 14929253a52cebaedbbe918972ea12568e29dfd9 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Wed, 20 Nov 2019 15:22:29 -0800 Subject: [PATCH 1019/1463] trogdor: add support for Bubs variant Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069 Reviewed-by: Bob Moragues Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- payloads/libpayload/configs/config.bubs | 8 ++++++++ src/mainboard/google/trogdor/Kconfig | 22 +++++++++++++--------- src/mainboard/google/trogdor/Kconfig.name | 5 +++++ src/mainboard/google/trogdor/Makefile.inc | 6 ++++-- 4 files changed, 30 insertions(+), 11 deletions(-) create mode 100644 payloads/libpayload/configs/config.bubs diff --git a/payloads/libpayload/configs/config.bubs b/payloads/libpayload/configs/config.bubs new file mode 100644 index 0000000000..7e162e5ddb --- /dev/null +++ b/payloads/libpayload/configs/config.bubs @@ -0,0 +1,8 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index d1dbfe0d99..76a89fb0db 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -8,20 +8,23 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_RTC - select EC_GOOGLE_CHROMEEC_SPI - select RTC + select EC_GOOGLE_CHROMEEC if !BOARD_GOOGLE_BUBS + select EC_GOOGLE_CHROMEEC_RTC if !BOARD_GOOGLE_BUBS + select EC_GOOGLE_CHROMEEC_SPI if !BOARD_GOOGLE_BUBS + select RTC if !BOARD_GOOGLE_BUBS + select MISSING_BOARD_RESET if BOARD_GOOGLE_BUBS select SOC_QUALCOMM_SC7180 select SPI_FLASH select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_BUBS + select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_BUBS config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES + select EC_GOOGLE_CHROMEEC_SWITCHES if !BOARD_GOOGLE_BUBS select VBOOT_VBNV_FLASH - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT if BOARD_GOOGLE_BUBS + select VBOOT_MOCK_SECDATA if BOARD_GOOGLE_BUBS config MAINBOARD_DIR string @@ -29,11 +32,11 @@ config MAINBOARD_DIR config DRIVER_TPM_SPI_BUS hex - default 0x5 + default 0x6 config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0xa + default 0x0 ########################################################## #### Update below when adding a new derivative board. #### @@ -43,5 +46,6 @@ config MAINBOARD_PART_NUMBER string default "Trogdor" if BOARD_GOOGLE_TROGDOR default "Lazor" if BOARD_GOOGLE_LAZOR + default "Bubs" if BOARD_GOOGLE_BUBS endif # BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index 66636a6ea1..7be1a2d46a 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -1,3 +1,4 @@ +comment "Trogdor" config BOARD_GOOGLE_TROGDOR bool "Trogdor" @@ -6,3 +7,7 @@ config BOARD_GOOGLE_TROGDOR config BOARD_GOOGLE_LAZOR bool "Lazor" select BOARD_GOOGLE_TROGDOR_COMMON + +config BOARD_GOOGLE_BUBS + bool "Bubs" + select BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc index 5c85351a69..3586db5805 100644 --- a/src/mainboard/google/trogdor/Makefile.inc +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -13,24 +13,26 @@ ## bootblock-y += memlayout.ld -bootblock-y += reset.c bootblock-y += boardid.c bootblock-y += chromeos.c bootblock-y += bootblock.c verstage-y += memlayout.ld +ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y) verstage-y += reset.c +endif verstage-y += boardid.c verstage-y += chromeos.c romstage-y += memlayout.ld romstage-y += romstage.c -romstage-y += reset.c romstage-y += boardid.c romstage-y += chromeos.c ramstage-y += memlayout.ld ramstage-y += mainboard.c +ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y) ramstage-y += reset.c +endif ramstage-y += chromeos.c ramstage-y += boardid.c From 56473ca9a7ca96e862897192b2a7dba4f162aa86 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 28 Feb 2019 12:43:21 +0100 Subject: [PATCH 1020/1463] sb/intel/bd82x6x/sata: Clean up IDE modes Don't set legacy timing values that don't affect the hardware but enable the OOB retry mode as already done on the AHCI path. Change-Id: I0b078d7790ca801a89066ef6a161d900be5eb778 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40010 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/sata.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 6c6e5be598..75a1b1a363 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -187,26 +187,14 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n"); } - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_SITRE | IDE_ISP_3_CLOCKS | - IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + /* Enable I/O decoding */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ + /* Port enable + OOB retry mode */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; - reg16 |= config->sata_port_map; + reg16 |= config->sata_port_map | 0x8000; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ From df5b051e6d2a56ed586418d82f3144b5cdf018dc Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 13 Feb 2019 15:16:02 +0100 Subject: [PATCH 1021/1463] mb/kontron/ktqm77: Extend SATA CMOS option with "legacy" mode TEST=Booted Linux 2.6.12 w/o native Intel IDE driver and confirmed working SATA drive. Change-Id: I85f72a172bcbc4c8b4bfb7a2baed7c6739b2d9f8 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39829 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/kontron/ktqm77/cmos.layout | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index f180754492..72117ae5ea 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -54,12 +54,12 @@ entries 400 1 e 2 hyper_threading 401 3 e 12 gfx_uma_size -#404 4 r 0 unused +#404 3 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 11 sata_mode +407 1 e 1 nmi +408 2 e 7 power_on_after_fail +410 2 e 11 sata_mode # coreboot config options: additional mainboard options 412 4 e 10 systemp_type @@ -130,6 +130,7 @@ enumerations 10 4 LM75@9e 11 0 AHCI 11 1 Compatible +11 2 Legacy 12 0 32M 12 1 64M 12 2 96M From 39801329870f16e2e1b56724e9d4e1e3f742bbbc Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 6 Apr 2020 15:06:08 +1000 Subject: [PATCH 1022/1463] mb/google/hatch: Add Duffy variant A verbatim copy of variants/puff. BUG=b:152951181 BRANCH=none TEST=none Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223 Reviewed-by: Daniel Kurtz Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 8 + .../google/hatch/variants/duffy/Makefile.inc | 16 + .../google/hatch/variants/duffy/gpio.c | 116 ++++++ .../duffy/include/variant/acpi/dptf.asl | 1 + .../hatch/variants/duffy/include/variant/ec.h | 60 +++ .../variants/duffy/include/variant/gpio.h | 9 + .../google/hatch/variants/duffy/mainboard.c | 120 ++++++ .../hatch/variants/duffy/overridetree.cb | 371 ++++++++++++++++++ 9 files changed, 703 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/duffy/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/duffy/gpio.c create mode 100644 src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/duffy/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/duffy/mainboard.c create mode 100644 src/mainboard/google/hatch/variants/duffy/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ff3f6a46ec..90c8e38d74 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -95,6 +95,7 @@ config MAINBOARD_PART_NUMBER string default "Akemi" if BOARD_GOOGLE_AKEMI default "Dratini" if BOARD_GOOGLE_DRATINI + default "Duffy" if BOARD_GOOGLE_DUFFY default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP @@ -121,6 +122,7 @@ config VARIANT_DIR string default "akemi" if BOARD_GOOGLE_AKEMI default "dratini" if BOARD_GOOGLE_DRATINI + default "duffy" if BOARD_GOOGLE_DUFFY default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ac64a9ea9c..7eebc2fc18 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -12,6 +12,14 @@ config BOARD_GOOGLE_DRATINI select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 +config BOARD_GOOGLE_DUFFY + bool "-> Duffy" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS + select SPD_READ_BY_WORD + select VBOOT_EC_EFS + config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/hatch/variants/duffy/Makefile.inc new file mode 100644 index 0000000000..8cbad31648 --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +ramstage-y += mainboard.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/duffy/gpio.c b/src/mainboard/google/hatch/variants/duffy/gpio.c new file mode 100644 index 0000000000..60842a4e54 --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/gpio.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..2c44a82365 --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h new file mode 100644 index 0000000000..5e2043fe5c --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS 0 + +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with power button */ +#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* + * Defines EC wake pin route. + * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# + * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. + */ +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* VARIANT_EC_H */ diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h b/src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h new file mode 100644 index 0000000000..6c958479fa --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c new file mode 100644 index 0000000000..e8098b96ac --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +void variant_ramstage_init(void) +{ + static const long display_timeout_ms = 3000; + + /* This is reconfigured back to whatever FSP-S expects by + gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } +} + +/* + * For type-C chargers, set PL2 to 90% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ +#define SET_PSYSPL2(w) (9 * (w) / 10) + +#define PUFF_PL2 (35) + +#define PUFF_PSYSPL2 (58) + +#define PUFF_MAX_TIME_WINDOW 6 +#define PUFF_MIN_DUTYCYCLE 4 + +/* + * mainboard_set_power_limits + * + * Set Pl2 and SysPl2 values based on detected charger. + * Values are defined below but we use U22 value for all SKUs for now. + * definitions: + * x = no value entered. Use default value in parenthesis. + * will set 0 to anything that shouldn't be set. + * n = max value of power adapter. + * +-------------+-----+---------+-----------+-------+ + * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+-----------+-------+ + * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | + * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | + * +-------------+-----+---------+-----------+-------+ + * For USB C charger: + * +-------------+-----+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+---------+-------+ + * | 60 (U42) | 44 | 54 | 54 | 54 | + * | 60 (U22) | 29 | 54 | 54 | x(43) | + * | n (U42) | 44 | .9n | .9n | .9n | + * | n (U22) | 29 | .9n | .9n | x(43) | + * +-------------+-----+---------+---------+-------+ + */ +static void mainboard_set_power_limits(config_t *conf) +{ + enum usb_chg_type type; + u32 watts; + u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 + int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); + + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ + conf->tdp_psyspl3 = 0; + conf->tdp_pl4 = 0; + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + psyspl2 = watts; + conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + /* set max possible time window */ + conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; + /* set minimum duty cycle */ + conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; + conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } + + conf->tdp_pl2_override = PUFF_PL2; + /* set psyspl2 to 90% of max adapter power */ + conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); +} + +void variant_mainboard_enable(struct device *dev) +{ + config_t *conf = config_of_soc(); + mainboard_set_power_limits(conf); +} diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb new file mode 100644 index 0000000000..3507e6d5eb --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -0,0 +1,371 @@ +chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on end # I2C #2, PCON PS175. + device pci 15.3 on end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.0 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # FSP requires func0 be enabled. + device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end From b438dab36757915608fdfb2a4ef7a87c323b43c1 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Wed, 15 Apr 2020 16:10:58 +1000 Subject: [PATCH 1023/1463] mb/google/hatch: Add Kaisa variant A verbatim copy of variants/puff V.2: rebased on duffy. BUG=b:152951180 BRANCH=none TEST=none Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d Signed-off-by: Andrew McRae Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393 Tested-by: build bot (Jenkins) Reviewed-by: Daniel Kurtz --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 8 + .../google/hatch/variants/kaisa/Makefile.inc | 16 + .../google/hatch/variants/kaisa/gpio.c | 116 ++++++ .../kaisa/include/variant/acpi/dptf.asl | 1 + .../hatch/variants/kaisa/include/variant/ec.h | 60 +++ .../variants/kaisa/include/variant/gpio.h | 9 + .../google/hatch/variants/kaisa/mainboard.c | 120 ++++++ .../hatch/variants/kaisa/overridetree.cb | 371 ++++++++++++++++++ 9 files changed, 703 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/kaisa/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/kaisa/gpio.c create mode 100644 src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/kaisa/mainboard.c create mode 100644 src/mainboard/google/hatch/variants/kaisa/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 90c8e38d74..b284ffecdb 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -100,6 +100,7 @@ config MAINBOARD_PART_NUMBER default "Helios" if BOARD_GOOGLE_HELIOS default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP default "Jinlon" if BOARD_GOOGLE_JINLON + default "Kaisa" if BOARD_GOOGLE_KAISA default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU @@ -127,6 +128,7 @@ config VARIANT_DIR default "helios" if BOARD_GOOGLE_HELIOS default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP default "jinlon" if BOARD_GOOGLE_JINLON + default "kaisa" if BOARD_GOOGLE_KAISA default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 7eebc2fc18..0713d13917 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -33,6 +33,14 @@ config BOARD_GOOGLE_JINLON select BOARD_ROMSIZE_KB_16384 select DRIVERS_GFX_GENERIC +config BOARD_GOOGLE_KAISA + bool "-> Kaisa" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS + select SPD_READ_BY_WORD + select VBOOT_EC_EFS + config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc new file mode 100644 index 0000000000..8cbad31648 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +ramstage-y += mainboard.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kaisa/gpio.c b/src/mainboard/google/hatch/variants/kaisa/gpio.c new file mode 100644 index 0000000000..60842a4e54 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kaisa/gpio.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..2c44a82365 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h new file mode 100644 index 0000000000..5e2043fe5c --- /dev/null +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS 0 + +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with power button */ +#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* + * Defines EC wake pin route. + * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# + * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. + */ +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* VARIANT_EC_H */ diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h new file mode 100644 index 0000000000..6c958479fa --- /dev/null +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c new file mode 100644 index 0000000000..e8098b96ac --- /dev/null +++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +void variant_ramstage_init(void) +{ + static const long display_timeout_ms = 3000; + + /* This is reconfigured back to whatever FSP-S expects by + gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } +} + +/* + * For type-C chargers, set PL2 to 90% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ +#define SET_PSYSPL2(w) (9 * (w) / 10) + +#define PUFF_PL2 (35) + +#define PUFF_PSYSPL2 (58) + +#define PUFF_MAX_TIME_WINDOW 6 +#define PUFF_MIN_DUTYCYCLE 4 + +/* + * mainboard_set_power_limits + * + * Set Pl2 and SysPl2 values based on detected charger. + * Values are defined below but we use U22 value for all SKUs for now. + * definitions: + * x = no value entered. Use default value in parenthesis. + * will set 0 to anything that shouldn't be set. + * n = max value of power adapter. + * +-------------+-----+---------+-----------+-------+ + * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+-----------+-------+ + * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | + * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | + * +-------------+-----+---------+-----------+-------+ + * For USB C charger: + * +-------------+-----+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+---------+-------+ + * | 60 (U42) | 44 | 54 | 54 | 54 | + * | 60 (U22) | 29 | 54 | 54 | x(43) | + * | n (U42) | 44 | .9n | .9n | .9n | + * | n (U22) | 29 | .9n | .9n | x(43) | + * +-------------+-----+---------+---------+-------+ + */ +static void mainboard_set_power_limits(config_t *conf) +{ + enum usb_chg_type type; + u32 watts; + u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 + int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); + + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ + conf->tdp_psyspl3 = 0; + conf->tdp_pl4 = 0; + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + psyspl2 = watts; + conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + /* set max possible time window */ + conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; + /* set minimum duty cycle */ + conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; + conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } + + conf->tdp_pl2_override = PUFF_PL2; + /* set psyspl2 to 90% of max adapter power */ + conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); +} + +void variant_mainboard_enable(struct device *dev) +{ + config_t *conf = config_of_soc(); + mainboard_set_power_limits(conf); +} diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb new file mode 100644 index 0000000000..e09d0c4897 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -0,0 +1,371 @@ +chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as kaisa variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on end # I2C #2, PCON PS175. + device pci 15.3 on end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.0 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # FSP requires func0 be enabled. + device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end From e433bccb86aba62759cec88a34dcc0b5c38a3677 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Wed, 8 Apr 2020 14:36:26 +0800 Subject: [PATCH 1024/1463] mb/google/puff: Add variant specific DPTF parameters Modify DPTF parameters for OEM EVT build from thermal team. BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Edward O'Callaghan --- .../puff/include/variant/acpi/dptf.asl | 116 +++++++++++++++++- 1 file changed, 115 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl index 2c44a82365..de12ee133e 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -1 +1,115 @@ -#include +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 80 +#define DPTF_CPU_ACTIVE_AC3 75 +#define DPTF_CPU_ACTIVE_AC4 70 +#define DPTF_CPU_ACTIVE_AC5 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 25000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) From 53525771f0584ea87da78047ceac5682d77a31bf Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 13 Apr 2020 22:24:09 -0600 Subject: [PATCH 1025/1463] ec/google/chromeec: add BOARD_VERSION CBI support Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base. Add the binding for it so it can be used. BUG=b:153640981 Change-Id: Ie2f289631f908014432596448e56b5048a196a10 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec.c | 5 +++++ src/ec/google/chromeec/ec.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 8d9c2acb43..17e110c5c9 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -848,6 +848,11 @@ int google_chromeec_cbi_get_oem_id(uint32_t *id) return cbi_get_uint32(id, CBI_TAG_OEM_ID); } +int google_chromeec_cbi_get_board_version(uint32_t *version) +{ + return cbi_get_uint32(version, CBI_TAG_BOARD_VERSION); +} + static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { struct ec_params_get_cbi params = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 77ba21169e..13e3bd9b7f 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -78,6 +78,9 @@ int google_chromeec_cbi_get_sku_id(uint32_t *id); int google_chromeec_cbi_get_fw_config(uint32_t *fw_config); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); +/* version may be stored in CBI as a smaller integer width, but the EC code + handles it correctly. */ +int google_chromeec_cbi_get_board_version(uint32_t *version); #define CROS_SKU_UNKNOWN 0xFFFFFFFF #define CROS_SKU_UNPROVISIONED 0x7FFFFFFF From 11278dbabeefe33acd8a796359de1e08e655dc8b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 13 Apr 2020 20:15:37 +0200 Subject: [PATCH 1026/1463] SeaBIOS: fix threaded hardware initialization during oprom execution MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since SeaBIOS rel-1.7.5 CONFIG_THREAD_OPTIONROMS is not present in its config. The threaded hardware initialization during optionrom execution is now controlled with a CBFS file. Add appropriate integer to CBFS when threaded hardware initialization is selected in coreboot's Kconfig. Signed-off-by: Michał Żygowski Change-Id: I9b5a532b609c6addf31ccdb6be03ff2e937ad326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40345 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index dbf95d4fb3..39dd6ddf9b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1111,6 +1111,10 @@ ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) @printf " SeaBIOS Add sercon-port file\n" $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif +ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) + @printf " SeaBIOS Thread optionroms\n" + $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads +endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) From b95a1a4ea0fa465c80a411e10bff8735edae050a Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Tue, 5 Mar 2019 15:56:39 +0800 Subject: [PATCH 1027/1463] autoport: Support bigger ACPI tables DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB for an ACPI table and support lines in acpidump.log with address higher than 0x10000. Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/autoport/log_reader.go | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go index d9a687ad42..0aaf6a9db3 100644 --- a/util/autoport/log_reader.go +++ b/util/autoport/log_reader.go @@ -107,12 +107,12 @@ func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { curTable := "" for scanner.Scan() { line := scanner.Text() - /* Only supports ACPI tables up to 0x10000 in size, FIXME if needed */ - is_hexline, _ := regexp.MatchString(" *[0-9A-Fa-f]{4}: ", line) + /* Only supports ACPI tables up to 0x100000 in size, FIXME if needed */ + is_hexline, _ := regexp.MatchString(" *[0-9A-Fa-f]{4,5}: ", line) switch { case len(line) >= 6 && line[5] == '@': curTable = line[0:4] - Tables[curTable] = make([]byte, 0, 100000) + Tables[curTable] = make([]byte, 0, 0x100000) case is_hexline: Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) } From 56360d4f7b3fe2d9ae9f0db86c2869c8c6704624 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Fri, 10 Apr 2020 20:56:07 +0800 Subject: [PATCH 1028/1463] autoport: use GMA_STATIC_DISPLAYS Change-Id: Ie988b2caeb2cdc07a3d6466b7ae3501df469ef41 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/40364 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/autoport/sandybridge.go | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index a64ef7a4c2..6f57847a1d 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -1,5 +1,7 @@ package main +import "fmt" + type sandybridgemc struct { } @@ -30,7 +32,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), - "gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0), + "gfx": fmt.Sprintf("GMA_STATIC_DISPLAYS(%d)", (inteltool.IGD[0xc6200] >> 12) & 1), }, Children: []DevTreeNode{ { From 0b9ed92c40e97c69bc3c111f067c98571a976007 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Apr 2020 17:00:31 +0200 Subject: [PATCH 1029/1463] MAINTAINERS: Drop invalid paths Remove references to directories that no longer exist. Change-Id: Ief45bf4c00c6cbf9b5acef72a76c05a86a7ebedc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40411 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- MAINTAINERS | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8a49fb3259..1026bdb30a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -374,10 +374,6 @@ S: Supported F: src/drivers/aspeed/common/ F: src/drivers/aspeed/ast2050/ -ATI MACH64 Driver -S: Orphan -F: src/drivers/ati/mach64/ - ABUILD M: Patrick Georgi M: Martin Roth @@ -409,13 +405,10 @@ F: util/rockchip/ ORPHANED ARM SOCS S: Orphaned -F: src/cpu/allwinner/ F: src/cpu/armltd/ F: src/cpu/ti/ -F: src/soc/marvell/ F: src/soc/qualcomm/ F: src/soc/samsung/ -F: util/arm_boot_tools/ F: util/exynos/ F: util/ipqheader/ @@ -517,15 +510,11 @@ F: src/drivers/uart/ NVRAM F: util/nvramtool/ -F: util/optionlist/ F: payloads/nvramcui/ LIBPAYLOAD F: payloads/libpayload/ -BAYOU PAYLOAD -F: payloads/bayou/ - COREINFO PAYLOAD F: payloads/coreinfo/ From 77410efebf38f7cd50c80a6c695e83888dabfb9c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Apr 2020 16:36:39 +0200 Subject: [PATCH 1030/1463] MAINTAINERS: Update GA-H61M-S2PV Commit 991ee05 ("mb/gigabyte/ga-h61m-s2pv: rename to ga-h61m-series") renamed the mainboard folder from `ga-h61m-s2pv` to `ga-h61m-series`, but the MAINTAINERS file was not updated accordingly. Correct that. Change-Id: I8119e29912e04ab57bebb96f37a4147afbb4d56e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40409 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 1026bdb30a..bc1e1fc40f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -198,10 +198,10 @@ M: Damien Zammit S: Odd Fixes F: src/mainboard/gigabyte/ga-g41m-es2l -GIGABYTE GA-H61M-S2PV MAINBOARD +GIGABYTE GA-H61M SERIES MAINBOARDS M: Angel Pons S: Maintained -F: src/mainboard/gigabyte/ga-h61m-s2pv +F: src/mainboard/gigabyte/ga-h61m-series GOOGLE PANTHER MAINBOARD M: Stefan Reinauer From ffe26b6c1aa3bd320370693c728161f74a0afc8f Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 14 Apr 2020 11:55:17 +0800 Subject: [PATCH 1031/1463] mb/google/hatch/var/kindred: Override VBT selection for kled Override VBT to fix CRC error issue with psr2 panel for kled. Cq-Depend: chrome-internal:2877637 BUG=b:145963505 BRANCH=hatch TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: If201d449e910f80dc514c142aec4808a44fa31a9 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40356 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg --- src/mainboard/google/hatch/variants/kindred/variant.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 583bcff8ae..27fe170852 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -6,6 +6,7 @@ #include #include #include +#include void variant_devtree_update(void) { @@ -46,3 +47,13 @@ const char *get_wifi_sar_cbfs_filename(void) filename = "wifi_sar-kled.hex"; return filename; } + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id = google_chromeec_get_board_sku(); + + if (sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4) + return "vbt-kled.bin"; + else + return "vbt.bin"; +} From e26da8ba16d4b87669524871b85a211a75f0eec4 Mon Sep 17 00:00:00 2001 From: BryantOu Date: Wed, 15 Apr 2020 00:37:23 -0700 Subject: [PATCH 1032/1463] intel/common/block/lpc: Add new device IDs for Lewisburg PCH Add C621A, C627A and C629A SKU IDs. C621A is used in the Whitley Product. We need to add device ID for setting LPC resources. Refer to Intel C620 series PCH EDS (547817). Change-Id: I19a4024808d5aa72a9e7bd434613b5e7c9284db8 Signed-off-by: BryantOu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40395 Reviewed-by: Paul Menzel Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 6 ++++++ src/soc/intel/common/block/lpc/lpc.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4898a91ce8..3de67ca7dd 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2773,11 +2773,17 @@ #define PCI_DEVICE_ID_INTEL_LWB_C627 0xa1c6 #define PCI_DEVICE_ID_INTEL_LWB_C628 0xa1c7 #define PCI_DEVICE_ID_INTEL_LWB_C629 0xa1ca +#define PCI_DEVICE_ID_INTEL_LWB_C621A 0xa1cb +#define PCI_DEVICE_ID_INTEL_LWB_C627A 0xa1cc +#define PCI_DEVICE_ID_INTEL_LWB_C629A 0xa1cd #define PCI_DEVICE_ID_INTEL_LWB_C624_SUPER 0xa242 #define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1 0xa243 #define PCI_DEVICE_ID_INTEL_LWB_C621_SUPER 0xa244 #define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2 0xa245 #define PCI_DEVICE_ID_INTEL_LWB_C628_SUPER 0xa246 +#define PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER 0xa24a +#define PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER 0xa24b +#define PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER 0xa24c #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 4cfd6f4839..2ce47ed07d 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -147,11 +147,17 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_LWB_C627, PCI_DEVICE_ID_INTEL_LWB_C628, PCI_DEVICE_ID_INTEL_LWB_C629, + PCI_DEVICE_ID_INTEL_LWB_C621A, + PCI_DEVICE_ID_INTEL_LWB_C627A, + PCI_DEVICE_ID_INTEL_LWB_C629A, PCI_DEVICE_ID_INTEL_LWB_C624_SUPER, PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1, PCI_DEVICE_ID_INTEL_LWB_C621_SUPER, PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2, PCI_DEVICE_ID_INTEL_LWB_C628_SUPER, + PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER, + PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER, + PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_Q270, PCI_DEVICE_ID_INTEL_KBP_H_H270, PCI_DEVICE_ID_INTEL_KBP_H_Z270, From e8ffa9ffd3cf5cb9fcade12e1f1e0dea5fc3fcf2 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 16 Mar 2020 19:20:20 -0600 Subject: [PATCH 1033/1463] soc/amd/psp: Add SmmInfo command Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's SMM configuration. Once the BootDone command is sent, the PSP only responds to commands where the buffer is in SMM memory. Set aside a region for the core-to-PSP command buffer and the PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read as non-zero during an SMI. Add calls to soc functions for the soc to populate the trigger info and register info (v2 only). Add functions to set up the structures needed for the SmmInfo function in Picasso support. Issue a SW SMI, and add a new handler to call the new PSP function. BUG=b:153677737 Change-Id: I10088a53e786db788740e4b388650641339dae75 Signed-off-by: Marshall Dawson Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- .../amd/common/block/include/amdblocks/psp.h | 55 ++++++++++--- src/soc/amd/common/block/psp/Makefile.inc | 1 + src/soc/amd/common/block/psp/psp_def.h | 19 +++++ src/soc/amd/common/block/psp/psp_smm.c | 78 +++++++++++++++++++ src/soc/amd/picasso/include/soc/smi.h | 3 + src/soc/amd/picasso/psp.c | 39 ++++++++++ src/soc/amd/picasso/smi.c | 3 + src/soc/amd/picasso/smihandler.c | 4 + 8 files changed, 192 insertions(+), 10 deletions(-) create mode 100644 src/soc/amd/common/block/psp/psp_smm.c diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 53946fb8d2..a1c1152af9 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -7,21 +7,56 @@ /* Get the mailbox base address - specific to family of device. */ void *soc_get_mbox_address(void); +#define SMM_TRIGGER_IO 0 +#define SMM_TRIGGER_MEM 1 + +#define SMM_TRIGGER_BYTE 0 +#define SMM_TRIGGER_WORD 1 +#define SMM_TRIGGER_DWORD 2 + +struct smm_trigger_info { + uint64_t address; /* Memory or IO address */ + uint32_t address_type; /* 0=I/O, 1=memory */ + uint32_t value_width; /* 0=byte, 1=word, 2=qword */ + uint32_t value_and_mask; + uint32_t value_or_mask; +} __packed; + +struct smm_register { + uint64_t address; /* Memory or IO address */ + uint32_t address_type; /* 0=I/O, 1=memory */ + uint32_t value_width; /* 0=byte, 1=word, 2=qword */ + uint32_t reg_bit_mask; + uint32_t expect_value; +} __packed; + +struct smm_register_info { + struct smm_register smi_enb; + struct smm_register eos; + struct smm_register psp_smi_en; + struct smm_register reserved[5]; +} __packed; + +void soc_fill_smm_trig_info(struct smm_trigger_info *trig); +void soc_fill_smm_reg_info(struct smm_register_info *reg); /* v2 only */ + /* BIOS-to-PSP functions return 0 if successful, else negative value */ -#define PSPSTS_SUCCESS 0 -#define PSPSTS_NOBASE 1 -#define PSPSTS_HALTED 2 -#define PSPSTS_RECOVERY 3 -#define PSPSTS_SEND_ERROR 4 -#define PSPSTS_INIT_TIMEOUT 5 -#define PSPSTS_CMD_TIMEOUT 6 +#define PSPSTS_SUCCESS 0 +#define PSPSTS_NOBASE 1 +#define PSPSTS_HALTED 2 +#define PSPSTS_RECOVERY 3 +#define PSPSTS_SEND_ERROR 4 +#define PSPSTS_INIT_TIMEOUT 5 +#define PSPSTS_CMD_TIMEOUT 6 /* other error codes */ -#define PSPSTS_UNSUPPORTED 7 -#define PSPSTS_INVALID_NAME 8 -#define PSPSTS_INVALID_BLOB 9 +#define PSPSTS_UNSUPPORTED 7 +#define PSPSTS_INVALID_NAME 8 +#define PSPSTS_INVALID_BLOB 9 int psp_notify_dram(void); +int psp_notify_smm(void); + /* * type: identical to the corresponding PSP command, e.g. pass * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index dc9a385e39..c2a33354ad 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -11,5 +11,6 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_smm.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index f3ac5c2181..63ca3abb0a 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -6,6 +6,7 @@ #include #include +#include /* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 @@ -81,6 +82,24 @@ struct mbox_default_buffer { /* command-response buffer unused by command */ struct mbox_buffer_header header; } __attribute__((packed, aligned(32))); +struct smm_req_buffer { + uint64_t smm_base; /* TSEG base */ + uint64_t smm_mask; /* TSEG mask */ + uint64_t psp_smm_data_region; /* PSP region in SMM space */ + uint64_t psp_smm_data_length; /* PSP region length in SMM space */ + struct smm_trigger_info smm_trig_info; +#if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) + struct smm_register_info smm_reg_info; +#endif + uint64_t psp_mbox_smm_buffer_address; + uint64_t psp_mbox_smm_flag_address; +} __packed; + +struct mbox_cmd_smm_info_buffer { + struct mbox_buffer_header header; + struct smm_req_buffer req; +} __attribute__((packed, aligned(32))); + struct mbox_cmd_sx_info_buffer { struct mbox_buffer_header header; u8 sleep_type; diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c new file mode 100644 index 0000000000..cc15738881 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "psp_def.h" + +#define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */ +#define P2C_BUFFER_MAXSIZE 0xc00 /* PSP-to-core buffer */ + +struct { + u8 buffer[C2P_BUFFER_MAXSIZE]; +} __attribute__((aligned(32))) c2p_buffer; + +struct { + u8 buffer[P2C_BUFFER_MAXSIZE]; +} __attribute__((aligned(32))) p2c_buffer; + +static uint32_t smm_flag; /* Non-zero for SMM, clear when not */ + +static void set_smm_flag(void) +{ + smm_flag = 1; +} + +static void clear_smm_flag(void) +{ + smm_flag = 0; +} + +int psp_notify_smm(void) +{ + msr_t msr; + int cmd_status; + struct mbox_cmd_smm_info_buffer buffer = { + .header = { + .size = sizeof(buffer) + }, + .req = { + .psp_smm_data_region = (uintptr_t)p2c_buffer.buffer, + .psp_smm_data_length = sizeof(p2c_buffer), + .psp_mbox_smm_buffer_address = (uintptr_t)c2p_buffer.buffer, + .psp_mbox_smm_flag_address = (uintptr_t)&smm_flag, + } + }; + + msr = rdmsr(SMM_ADDR_MSR); + buffer.req.smm_base = ((uint64_t)msr.hi << 32) | msr.lo; + msr = rdmsr(SMM_MASK_MSR); + msr.lo &= 0xffff0000; /* mask SMM_LOCK and SMM_TSEG_VALID and reserved bits */ + buffer.req.smm_mask = ((uint64_t)msr.hi << 32) | msr.lo; + + soc_fill_smm_trig_info(&buffer.req.smm_trig_info); +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2)) + soc_fill_smm_reg_info(&buffer.req.smm_reg_info); +#endif + + printk(BIOS_DEBUG, "PSP: Notify SMM info... "); + + set_smm_flag(); + cmd_status = send_psp_command(MBOX_BIOS_CMD_SMM_INFO, &buffer); + clear_smm_flag(); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, (struct mbox_default_buffer *)&buffer); + + return cmd_status; +} diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index e890e1319a..fb8061ca16 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -86,6 +86,7 @@ #define SMITYPE_NB_GPP_HOT_PLUG 30 /* 31 Reserved */ #define SMITYPE_WAKE_L2 32 +#define SMITYPE_PSP 33 /* 33 - 38 Reserved */ #define SMITYPE_AZPME 39 #define SMITYPE_USB_PD_I2C4 40 @@ -186,6 +187,8 @@ #define SMI_REG_CONTROL8 0xc0 #define SMI_REG_CONTROL9 0xc4 +#define SMI_MODE_MASK 0x03 + enum smi_mode { SMI_MODE_DISABLE = 0, SMI_MODE_SMI = 1, diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c index d6eb7d31a3..88b25b88b0 100644 --- a/src/soc/amd/picasso/psp.c +++ b/src/soc/amd/picasso/psp.c @@ -3,6 +3,8 @@ #include #include +#include +#include #include #define PSP_MAILBOX_OFFSET 0x10570 @@ -20,3 +22,40 @@ void *soc_get_mbox_address(void) return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); } + +void soc_fill_smm_trig_info(struct smm_trigger_info *trig) +{ + if (!trig) + return; + + trig->address = 0xfed802a8; + trig->address_type = SMM_TRIGGER_MEM; + trig->value_width = SMM_TRIGGER_DWORD; + trig->value_and_mask = 0xfdffffff; + trig->value_or_mask = 0x02000000; +} + +void soc_fill_smm_reg_info(struct smm_register_info *reg) +{ + if (!reg) + return; + + reg->smi_enb.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0; + reg->smi_enb.address_type = SMM_TRIGGER_MEM; + reg->smi_enb.value_width = SMM_TRIGGER_DWORD; + reg->smi_enb.reg_bit_mask = SMITRG0_SMIENB; + reg->smi_enb.expect_value = 0; + + reg->eos.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0; + reg->eos.address_type = SMM_TRIGGER_MEM; + reg->eos.value_width = SMM_TRIGGER_DWORD; + reg->eos.reg_bit_mask = SMITRG0_EOS; + reg->eos.expect_value = SMITRG0_EOS; + + reg->psp_smi_en.address = ACPIMMIO_SMI_BASE + SMI_REG_CONTROL0; + reg->psp_smi_en.address += sizeof(uint32_t) * SMITYPE_PSP / 16; + reg->psp_smi_en.address_type = SMM_TRIGGER_MEM; + reg->psp_smi_en.value_width = SMM_TRIGGER_DWORD; + reg->psp_smi_en.reg_bit_mask = SMI_MODE_MASK << (2 * SMITYPE_PSP % 16); + reg->psp_smi_en.expect_value = SMI_MODE_SMI << (2 * SMITYPE_PSP % 16); +} diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index ab8f405e59..273c55b635 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -17,6 +17,7 @@ * Utilities for SMM setup */ +#include #include #include #include @@ -35,4 +36,6 @@ void enable_smi_generation(void) reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); + + outb(APM_CNT_SMMINFO, APM_CNT); } diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 55493776dd..e4d1c86f57 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -26,6 +26,7 @@ #include #include #include +#include #include /* bits in smm_io_trap */ @@ -125,6 +126,9 @@ static void sb_apmc_smi_handler(void) if (CONFIG(SMMSTORE)) southbridge_smi_store(); break; + case APM_CNT_SMMINFO: + psp_notify_smm(); + break; } mainboard_smi_apmc(cmd); From 43126edc3ae246d1dbd293550e29a9e2c378f424 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 1 Apr 2020 22:06:39 +0200 Subject: [PATCH 1034/1463] soc/amd/common/psp: Add notify_sx_info Add the command to tell the PSP the system is going to a sleep state. BUG=b:153677737 Change-Id: I50da358e1f8438b46dbb1bda593becf6dd4549ea Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/2020367 Reviewed-on: https://chromium-review.googlesource.com/2110764 Reviewed-on: https://chromium-review.googlesource.com/2121159 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40016 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- .../amd/common/block/include/amdblocks/psp.h | 6 ++++ src/soc/amd/common/block/psp/psp_def.h | 25 +++++++++-------- src/soc/amd/common/block/psp/psp_smm.c | 28 +++++++++++++++++++ 3 files changed, 47 insertions(+), 12 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index a1c1152af9..91c96e1b0c 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -67,6 +67,12 @@ enum psp_blob_type { BLOB_SMU_FW2, }; +/* + * Notify PSP that the system is entering a sleep state. sleep_state uses the + * same definition as Pm1Cnt[SlpTyp], typically 0, 1, 3, 4, 5. + */ +void psp_notify_sx_info(u8 sleep_type); + int psp_load_named_blob(enum psp_blob_type type, const char *name); #endif /* __AMD_PSP_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 63ca3abb0a..7772ca6bda 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -9,18 +9,19 @@ #include /* x86 to PSP commands */ -#define MBOX_BIOS_CMD_DRAM_INFO 0x01 -#define MBOX_BIOS_CMD_SMM_INFO 0x02 -#define MBOX_BIOS_CMD_SX_INFO 0x03 -#define MBOX_BIOS_CMD_RSM_INFO 0x04 -#define MBOX_BIOS_CMD_PSP_QUERY 0x05 -#define MBOX_BIOS_CMD_BOOT_DONE 0x06 -#define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 -#define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 -#define MBOX_BIOS_CMD_NOP 0x09 -#define MBOX_BIOS_CMD_SMU_FW 0x19 -#define MBOX_BIOS_CMD_SMU_FW2 0x1a -#define MBOX_BIOS_CMD_ABORT 0xfe +#define MBOX_BIOS_CMD_DRAM_INFO 0x01 +#define MBOX_BIOS_CMD_SMM_INFO 0x02 +#define MBOX_BIOS_CMD_SX_INFO 0x03 +#define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07 +#define MBOX_BIOS_CMD_RSM_INFO 0x04 +#define MBOX_BIOS_CMD_PSP_QUERY 0x05 +#define MBOX_BIOS_CMD_BOOT_DONE 0x06 +#define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 +#define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 +#define MBOX_BIOS_CMD_NOP 0x09 +#define MBOX_BIOS_CMD_SMU_FW 0x19 +#define MBOX_BIOS_CMD_SMU_FW2 0x1a +#define MBOX_BIOS_CMD_ABORT 0xfe /* generic PSP interface status, v1 */ #define PSPV1_STATUS_INITIALIZED BIT(0) diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index cc15738881..4ae2277cab 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -76,3 +76,31 @@ int psp_notify_smm(void) return cmd_status; } + +/* Notify PSP the system is going to a sleep state. */ +void psp_notify_sx_info(u8 sleep_type) +{ + int cmd_status; + struct mbox_cmd_sx_info_buffer *buffer; + + /* PSP verifies that this buffer is at the address specified in psp_notify_smm() */ + buffer = (struct mbox_cmd_sx_info_buffer *)c2p_buffer.buffer; + memset(buffer, 0, sizeof(*buffer)); + buffer->header.size = sizeof(*buffer); + + if (sleep_type > MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX) { + printk(BIOS_ERR, "PSP: BUG: invalid sleep type 0x%x requested\n", sleep_type); + return; + } + + printk(BIOS_DEBUG, "PSP: Prepare to enter sleep state %d... ", sleep_type); + + buffer->sleep_type = sleep_type; + + set_smm_flag(); + cmd_status = send_psp_command(MBOX_BIOS_CMD_SX_INFO, buffer); + clear_smm_flag(); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, (struct mbox_default_buffer *)buffer); +} From 90b8339b8d4338c14cfd791bf4d5058aa515da34 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 19 Mar 2020 15:08:01 -0600 Subject: [PATCH 1035/1463] soc/amd/picasso: Notify PSP system is going to sleep state BUG=b:153677737 Signed-off-by: Marshall Dawson Change-Id: Ic72bd5f5710181ca4f282feba5f7531b098c907a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40298 Reviewed-by: Angel Pons Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/smihandler.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index e4d1c86f57..b3a1a30d62 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -220,6 +220,8 @@ static void sb_slp_typ_handler(void) reg32); } /* if (CONFIG(ELOG_GSMI)) */ + psp_notify_sx_info(slp_typ); + /* * An IO cycle is required to trigger the STPCLK/STPGNT * handshake when the Pm1 write is reissued. From 7d304186057cc6c66e5469fadd003e3a62b8eb63 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 15 Apr 2020 17:05:38 +0200 Subject: [PATCH 1036/1463] soc/amd/common/psp: refactor psp_print_cmd_status parameters psp_print_cmd_status only needs data from the mbox buffer header and not the whole buffer. This avoids type casts when the buffer type isn't mbox_default_buffer. BUG=b:153677737 Change-Id: I8688b66fefe89fc4f3ce2207d4360ceb2dbaef12 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40412 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/psp/psp.c | 16 ++++++++-------- src/soc/amd/common/block/psp/psp_def.h | 2 +- src/soc/amd/common/block/psp/psp_smm.c | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 479c28bc33..5f33c82e19 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -39,19 +39,19 @@ static const char *status_to_string(int err) } } -static u32 rd_resp_sts(struct mbox_default_buffer *buffer) +static u32 rd_resp_sts(struct mbox_buffer_header *header) { - return read32(&buffer->header.status); + return read32(&header->status); } /* * Print meaningful status to the console. Caller only passes a pointer to a - * buffer if it's expected to contain its own status. + * buffer header if it's expected to contain its own status. */ -void psp_print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer) +void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header) { - if (buffer && rd_resp_sts(buffer)) - printk(BIOS_DEBUG, "buffer status=0x%x ", rd_resp_sts(buffer)); + if (header && rd_resp_sts(header)) + printk(BIOS_DEBUG, "buffer status=0x%x ", rd_resp_sts(header)); if (cmd_status) printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); @@ -77,7 +77,7 @@ int psp_notify_dram(void) cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer); + psp_print_cmd_status(cmd_status, &buffer.header); return cmd_status; } @@ -101,7 +101,7 @@ static void psp_notify_boot_done(void *unused) cmd_status = send_psp_command(MBOX_BIOS_CMD_BOOT_DONE, &buffer); /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer); + psp_print_cmd_status(cmd_status, &buffer.header); } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 7772ca6bda..7bdec21943 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -109,7 +109,7 @@ struct mbox_cmd_sx_info_buffer { #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */ -void psp_print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer); +void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); /* This command needs to be implemented by the generation specific code. */ int send_psp_command(u32 command, void *buffer); diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 4ae2277cab..7ffa6b6116 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -72,7 +72,7 @@ int psp_notify_smm(void) clear_smm_flag(); /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, (struct mbox_default_buffer *)&buffer); + psp_print_cmd_status(cmd_status, &buffer.header); return cmd_status; } @@ -102,5 +102,5 @@ void psp_notify_sx_info(u8 sleep_type) clear_smm_flag(); /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, (struct mbox_default_buffer *)buffer); + psp_print_cmd_status(cmd_status, &buffer->header); } From 74bee3c8adb70c8987ea1c174d58682bbf05350a Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 3 Feb 2020 16:01:10 -0700 Subject: [PATCH 1037/1463] vc/amd/fsp/picasso: Add file for GUIDs Begin a file for GUIDs used by the FSP. Signed-off-by: Marshall Dawson Change-Id: Ied5c5085ea8ed55439192be8a44fa401aeb559a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38697 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/vendorcode/amd/fsp/picasso/FspGuids.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 src/vendorcode/amd/fsp/picasso/FspGuids.h diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h new file mode 100644 index 0000000000..f50d94240d --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __FSP_GUIDS__ +#define __FSP_GUIDS__ + +#include + +#define AMD_FSP_TSEG_HOB_GUID \ + GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ + 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) + +#endif /* __FSP_GUIDS__ */ From c0495723857792f30b88880fafbe958ce9f700f3 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Thu, 2 Apr 2020 23:58:35 -0700 Subject: [PATCH 1038/1463] ec/google/chromeec: Add host command EC_CMD_GET_KEYBD_CONFIG Add command to query the EC for the keyboard layout. Also add supporting data structures for the exchange. Signed-off-by: Rajat Jain Change-Id: I26aff6dd0e701e0cecb3b66bc54c5a23688f0109 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40030 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/ec/google/chromeec/ec_commands.h | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 18be8d30b2..d642d9eb64 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -6079,6 +6079,83 @@ enum keyboard_button_type { KEYBOARD_BUTTON_COUNT }; +/*****************************************************************************/ +/* + * "Get the Keyboard Config". An EC implementing this command is expected to be + * vivaldi capable, i.e. can send action codes for the top row keys. + * Additionally, capability to send function codes for the same keys is + * optional and acceptable. + * + * Note: If the top row can generate both function and action codes by + * using a dedicated Fn key, it does not matter whether the key sends + * "function" or "action" codes by default. In both cases, the response + * for this command will look the same. + */ +#define EC_CMD_GET_KEYBD_CONFIG 0x012A + +/* Possible values for the top row keys */ +enum action_key { + TK_ABSENT = 0, + TK_BACK = 1, + TK_FORWARD = 2, + TK_REFRESH = 3, + TK_FULLSCREEN = 4, + TK_OVERVIEW = 5, + TK_BRIGHTNESS_DOWN = 6, + TK_BRIGHTNESS_UP = 7, + TK_VOL_MUTE = 8, + TK_VOL_DOWN = 9, + TK_VOL_UP = 10, + TK_SNAPSHOT = 11, + TK_PRIVACY_SCRN_TOGGLE = 12, + TK_KBD_BKLIGHT_DOWN = 13, + TK_KBD_BKLIGHT_UP = 14, + TK_PLAY_PAUSE = 15, + TK_NEXT_TRACK = 16, + TK_PREV_TRACK = 17, +}; + +/* + * Max & Min number of top row keys, excluding Esc and Screenlock keys. + * If this needs to change, please create a new version of the command. + */ +#define MAX_TOP_ROW_KEYS 15 +#define MIN_TOP_ROW_KEYS 10 + +/* + * Is the keyboard capable of sending function keys *in addition to* + * action keys. This is possible for e.g. if the keyboard has a + * dedicated Fn key. + */ +#define KEYBD_CAP_FUNCTION_KEYS BIT(0) +/* + * Whether the keyboard has a dedicated numeric keyboard. + */ +#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1) +/* + * Whether the keyboard has a screenlock key. + */ +#define KEYBD_CAP_SCRNLOCK_KEY BIT(2) + +struct ec_response_keybd_config { + /* + * Number of top row keys, excluding Esc and Screenlock. + * If this is 0, all Vivaldi keyboard code is disabled. + * (i.e. does not expose any tables to the kernel). + */ + uint8_t num_top_row_keys; + + /* + * The action keys in the top row, in order from left to right. + * The values are filled from enum action_key. Esc and Screenlock + * keys are not considered part of top row keys. + */ + uint8_t action_keys[MAX_TOP_ROW_KEYS]; + + /* Capability flags */ + uint8_t capabilities; + +} __ec_align1; /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ From afa71b611312dc897b03e2b4bba44e8a427ac8ea Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 15 Apr 2020 19:23:46 +0200 Subject: [PATCH 1039/1463] configs: Add qemu aarch64 target with FIT support Add a defconfig which allows to place a large uImage/FIT payload in it to boot test the binary on qemu-system-aarch64 using u-root and kexec-tools. Change-Id: I95ca187b68ff883152421bd7612b494cd63e8d02 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/40413 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Reviewed-by: Felix Held --- .../config.emulation_qemu_aarch64_fit_support_timestamps | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 configs/config.emulation_qemu_aarch64_fit_support_timestamps diff --git a/configs/config.emulation_qemu_aarch64_fit_support_timestamps b/configs/config.emulation_qemu_aarch64_fit_support_timestamps new file mode 100644 index 0000000000..7d0054ca6b --- /dev/null +++ b/configs/config.emulation_qemu_aarch64_fit_support_timestamps @@ -0,0 +1,7 @@ +CONFIG_COLLECT_TIMESTAMPS=y +CONFIG_TIMESTAMPS_ON_CONSOLE=y +CONFIG_MAINBOARD_VENDOR="Emulation" +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_BOARD_EMULATION_QEMU_AARCH64=y +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_PAYLOAD_FIT_SUPPORT=y From b2634c1f988668bea665c5fa401d820f86d5dd6b Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Fri, 10 Apr 2020 19:36:42 +0300 Subject: [PATCH 1040/1463] intel/common: add a macro to set ownership for GPI Adds a new macro that allow to set the DRIVER or ACPI as host software ownership for the GPI pad using the parameter own. Thus, this macro can define more variants for pad configuration than others. This is necessary to describe in more detail the configuration for the Tioga Pass OCP server [1] and other boards. In addition, these changes will be used to automatically generate macros [2] and great simplify this task. [1] https://review.coreboot.org/c/coreboot/+/39427 [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I9c191fb6935e94da6e296f8fee0b91a973534e1a Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40276 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/gpio/gpio.c | 2 +- .../block/include/intelblocks/gpio_defs.h | 27 ++++++++++++------- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index dedd36492c..e73c7767c1 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -156,7 +156,7 @@ static void gpio_configure_owner(const struct pad_config *cfg, * needs GPIO driver ownership. Set the bit if GPIO driver ownership * requested, otherwise clear the bit. */ - if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER) + if (cfg->pad_config[1] & PAD_CFG_OWN_GPIO_DRIVER) hostsw_own |= gpio_bitmask_within_group(comm, pin); else hostsw_own &= ~gpio_bitmask_within_group(comm, pin); diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index bd26e82e30..6eaaf0cab7 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -56,11 +56,15 @@ #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) -/* Use the fourth bit in IntSel field to indicate gpio +/* + * Use the fourth bit in IntSel field to indicate gpio * ownership. This field is RO and hence not used during * gpio configuration. */ -#define PAD_CFG1_GPIO_DRIVER (0x1 << 4) +#define PAD_CFG_OWN_GPIO_DRIVER (1 << 4) +#define PAD_CFG_OWN_GPIO_ACPI (0 << 4) +#define PAD_CFG_OWN_GPIO(own) PAD_CFG_OWN_GPIO_##own + #define PAD_CFG1_IRQ_MASK (0xff << 0) #define PAD_CFG1_IOSTERM_MASK (0x3 << 8) #define PAD_CFG1_IOSTERM_SAME (0x0 << 8) @@ -249,7 +253,7 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG_OWN_GPIO(DRIVER)) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ @@ -274,18 +278,24 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) -/* General purpose input. The following macro sets the +/* + * General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ +#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) + #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE)) #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ @@ -295,10 +305,7 @@ /* GPIO Interrupt */ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) /* * No Connect configuration for unused pad. From a95907b0666c764aaddeaffc7a414c49bbb47d7b Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 13 Apr 2020 18:03:29 -0600 Subject: [PATCH 1041/1463] ec/google/chromeec: Update the USBC ACPI device hierarchy Type C connector class driver in kernel (v5.4) expects the Type C ACPI device under ChromeEC ACPI device scope. Currently the Type C ACPI device is populated under ChromeEC device's parent. This leads to incorrect casting of Type C's parent device and hence a crash. Move the Type C device under ChromeEC ACPI device. BUG=b:153518804 TEST=Build and boot the mainboard. Ensure that the USBC ACPI device is populated under ChromeEC ACPI device. Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (USBC) { Name (_HID, "GOOG0014") // _HID: Hardware ID ... } } Change-Id: I628489bc420d7a3db4ad3cb93d085d568c6de507 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/40354 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra Reviewed-by: Tim Wawrzynczak --- src/ec/google/chromeec/ec_acpi.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 47d60d5b75..6bc9693881 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -16,8 +16,9 @@ #include "ec.h" #include "ec_commands.h" -#define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" -#define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" +#define GOOGLE_CHROMEEC_USBC_DEVICE_PARENT "CREC" +#define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" +#define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" const char *google_chromeec_acpi_name(const struct device *dev) { @@ -219,8 +220,8 @@ void google_chromeec_fill_ssdt_generator(struct device *dev) if (google_chromeec_get_num_pd_ports(&num_ports)) return; - /* Reference the existing device's scope */ - acpigen_write_scope(acpi_device_path(dev)); + /* Add TypeC device under the existing device + ".CREC" scope */ + acpigen_write_scope(acpi_device_path_join(dev, GOOGLE_CHROMEEC_USBC_DEVICE_PARENT)); fill_ssdt_typec_device(num_ports); acpigen_pop_len(); /* Scope */ } From 1e066117684997ff44af435854b885b6abf52c3f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 8 Apr 2020 11:35:52 -0700 Subject: [PATCH 1042/1463] soc/intel: Disable config option for SCS by default The eMMC/SD interface is not present in all Intel platforms so this change removes the default enable for the storage controller and instead enables it in the specific SoCs that do provide it. Currently this includes all platforms except Tigerlake. Change-Id: I8b6cab41dbd5080f4a7801f01279f47e80ceaefd Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/40371 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/Kconfig | 1 + src/soc/intel/common/pch/Kconfig | 1 - src/soc/intel/icelake/Kconfig | 1 + src/soc/intel/jasperlake/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + 5 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 889aa00b21..9bd57a353e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -95,6 +95,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 1e8cdcdc23..cca65d6b2a 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -33,7 +33,6 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SATA - select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TCO diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 4193128a64..2a5156b2b9 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_THERMAL diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 8c2dd779b4..41905c5008 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 4df64beb5e..0a5daeaa82 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -62,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY select SOC_INTEL_COMMON_BLOCK_SMM From 3ed55e5da1ea3ed49a20aa3983fc6ac1bc366fb5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 7 Apr 2020 14:33:37 -0700 Subject: [PATCH 1043/1463] soc/intel/tigerlake: Remove eMMC/SD support Tigerlake platform does not have built in eMMC/SD support so all this code is unused and can be removed. Change-Id: I70ff983d175375171d5a649378f32f1062c0876d Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372 Reviewed-by: Angel Pons Reviewed-by: Subrata Banik Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Makefile.inc | 1 - src/soc/intel/tigerlake/chip.h | 9 ------ src/soc/intel/tigerlake/include/soc/pcr_ids.h | 1 - src/soc/intel/tigerlake/sd.c | 31 ------------------- 4 files changed, 42 deletions(-) delete mode 100644 src/soc/intel/tigerlake/sd.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 4aa1f2f4d1..f62bfaf38c 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -43,7 +43,6 @@ ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c -ramstage-y += sd.c ramstage-y += me.c smm-y += gpio.c diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index bc6c3db726..26eab4c8fd 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -127,12 +127,6 @@ struct soc_intel_tigerlake_config { /* SMBus */ uint8_t SmbusEnable; - /* eMMC and SD */ - uint8_t ScsEmmcHs400Enabled; - - /* Enable if SD Card Power Enable Signal is Active High */ - uint8_t SdCardPowerEnableActiveHigh; - /* Integrated Sensor */ uint8_t PchIshEnable; @@ -210,9 +204,6 @@ struct soc_intel_tigerlake_config { DEBUG_INTERFACE_TRACEHUB = (1 << 5), } debug_interface_flag; - /* GPIO SD card detect pin */ - unsigned int sdcard_cd_gpio; - /* Enable Pch iSCLK */ uint8_t pch_isclk; diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index 1d54805cb1..44884beb7a 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -12,7 +12,6 @@ /* * Port ids */ -#define PID_EMMC 0x52 #define PID_SDX 0x53 #define PID_GPIOCOM0 0x6e diff --git a/src/soc/intel/tigerlake/sd.c b/src/soc/intel/tigerlake/sd.c deleted file mode 100644 index 857f175f98..0000000000 --- a/src/soc/intel/tigerlake/sd.c +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 26 - */ - -#include -#include - -int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) -{ - config_t *config = config_of(dev); - - if (!config->sdcard_cd_gpio) - return -1; - - gpio->type = ACPI_GPIO_TYPE_INTERRUPT; - gpio->pull = ACPI_GPIO_PULL_NONE; - gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; - gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; - gpio->irq.shared = ACPI_IRQ_SHARED; - gpio->irq.wake = ACPI_IRQ_WAKE; - gpio->interrupt_debounce_timeout = 10000; /* 100ms */ - gpio->pin_count = 1; - gpio->pins[0] = config->sdcard_cd_gpio; - - return 0; -} From 622c6b84ab029a366dd09740a24d36ae9fad697f Mon Sep 17 00:00:00 2001 From: dnojiri Date: Fri, 3 Apr 2020 10:51:50 -0700 Subject: [PATCH 1044/1463] TPM: Add tlcl_cr50_get_boot_mode tlcl_cr50_get_boot_mode gets the boot mode from Cr50. The boot mode tells coreboot/depthcharge whether booting the kernel is allowed or not. BUG=b:147298634, chromium:1045217, b:148259137 BRANCH=none TEST=Verify software sync succeeds on Puff. Signed-off-by: dnojiri Change-Id: Iadae848c4bf315f2131ff6aebcb35938307b5db4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40388 Reviewed-by: Julius Werner Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- src/security/tpm/tss/tcg-2.0/tss_marshaling.c | 5 ++++ src/security/tpm/tss/tcg-2.0/tss_structures.h | 1 + src/security/tpm/tss/vendor/cr50/cr50.c | 25 +++++++++++++++++++ src/security/tpm/tss/vendor/cr50/cr50.h | 9 +++++++ 4 files changed, 40 insertions(+) diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 45ade1a314..a229dd17ef 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -335,6 +335,9 @@ static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body) */ rc |= obuf_write_be16(ob, *sub_command); break; + case TPM2_CR50_SUB_CMD_GET_BOOT_MODE: + rc |= obuf_write_be16(ob, *sub_command); + break; default: /* Unsupported subcommand. */ printk(BIOS_WARNING, "Unsupported cr50 subcommand: 0x%04x\n", @@ -560,6 +563,8 @@ static int unmarshal_vendor_command(struct ibuf *ib, return ibuf_read_be8(ib, &vcr->recovery_button_state); case TPM2_CR50_SUB_CMD_TPM_MODE: return ibuf_read_be8(ib, &vcr->tpm_mode); + case TPM2_CR50_SUB_CMD_GET_BOOT_MODE: + return ibuf_read_be8(ib, &vcr->boot_mode); default: printk(BIOS_ERR, "%s:%d - unsupported vendor command %#04x!\n", diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index ade9b27873..3f0c6545ab 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -349,6 +349,7 @@ struct vendor_command_response { uint8_t num_restored_headers; uint8_t recovery_button_state; uint8_t tpm_mode; + uint8_t boot_mode; }; }; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index ec69df4ac9..ae2f7c2516 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -107,6 +107,31 @@ uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode) return TPM_SUCCESS; } +uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode) +{ + struct tpm2_response *response; + uint16_t mode_command = TPM2_CR50_SUB_CMD_GET_BOOT_MODE; + + printk(BIOS_DEBUG, "Reading cr50 boot mode\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command); + + if (!response) + return TPM_E_IOERROR; + + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND) + /* Explicitly inform caller when command is not supported */ + return TPM_E_NO_SUCH_COMMAND; + + if (response->hdr.tpm_code) + /* Unexpected return code from Cr50 */ + return TPM_E_IOERROR; + + *boot_mode = response->vcr.boot_mode; + + return TPM_SUCCESS; +} + uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms) { struct tpm2_response *response; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index e3137630de..0f91732856 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -15,6 +15,7 @@ #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24) #define TPM2_CR50_SUB_CMD_GET_REC_BTN (29) #define TPM2_CR50_SUB_CMD_TPM_MODE (40) +#define TPM2_CR50_SUB_CMD_GET_BOOT_MODE (52) /* Cr50 vendor-specific error codes. */ #define VENDOR_RC_ERR 0x00000500 @@ -78,6 +79,14 @@ uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state); */ uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode); +/** + * CR50 specific TPM command sequence to query the current boot mode. + * + * Returns TPM_SUCCESS if boot mode is successfully retrieved. + * Returns TPM_E_* for errors. + */ +uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode); + /** * CR50 specific TPM command sequence to trigger an immediate reset to the Cr50 * device after the specified timeout in milliseconds. A timeout of zero means From dff56a056c7dadf0d970cfe29f0bc9c1fec69e82 Mon Sep 17 00:00:00 2001 From: dnojiri Date: Fri, 3 Apr 2020 10:56:43 -0700 Subject: [PATCH 1045/1463] ec_sync: Run EFS2 in romstage EFS2 allows EC RO to enable PD for special cases. When doing so, it sets NO_BOOT flag to avoid booting the OS. AP needs to get NO_BOOT flag from Cr50 and enforce that. This patch makes verstage get a boot mode and a mirrored hash stored in kernel secdata from Cr50. This patch also makes romstage write an expected EC hash (a.k.a. Hexp) to Cr50 (if there is an update). BUG=b:147298634, chromium:1045217, b:148259137 BRANCH=none TEST=Verify software sync succeeds on Puff. Signed-off-by: dnojiri Change-Id: I1f387b6e920205b9cc4c8536561f2a279c36413d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40389 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/security/vboot/antirollback.h | 6 +++ src/security/vboot/ec_sync.c | 2 +- src/security/vboot/secdata_mock.c | 11 +++++ src/security/vboot/secdata_tpm.c | 25 ++++++++++ src/security/vboot/vboot_common.h | 1 - src/security/vboot/vboot_logic.c | 81 +++++++++++++++++++++++++------ 6 files changed, 109 insertions(+), 17 deletions(-) diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 5af923600d..6bc020d208 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -71,6 +71,12 @@ uint32_t antirollback_read_space_firmware(struct vb2_context *ctx); */ uint32_t antirollback_write_space_firmware(struct vb2_context *ctx); +/** + * Read and write kernel space in TPM. + */ +uint32_t antirollback_read_space_kernel(struct vb2_context *ctx); +uint32_t antirollback_write_space_kernel(struct vb2_context *ctx); + /** * Lock must be called. */ diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 3a177b16e8..580e6c6b8d 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -50,7 +50,7 @@ void vboot_sync_ec(void) ctx->flags |= VB2_CONTEXT_EC_SYNC_SUPPORTED; retval = vb2api_ec_sync(ctx); - vboot_save_nvdata_only(ctx); + vboot_save_data(ctx); switch (retval) { case VB2_SUCCESS: diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index a4957f9575..edb6739653 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -53,6 +53,17 @@ vb2_error_t antirollback_write_space_firmware(struct vb2_context *ctx) return VB2_SUCCESS; } +vb2_error_t antirollback_read_space_kernel(struct vb2_context *ctx) +{ + vb2api_secdata_kernel_create(ctx); + return VB2_SUCCESS; +} + +vb2_error_t antirollback_write_space_kernel(struct vb2_context *ctx) +{ + return VB2_SUCCESS; +} + vb2_error_t antirollback_lock_space_firmware(void) { return VB2_SUCCESS; diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0ae956276c..b60a1bb315 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -80,6 +80,22 @@ static uint32_t read_space_firmware(struct vb2_context *ctx) return TPM_E_CORRUPTED_STATE; } +uint32_t antirollback_read_space_kernel(struct vb2_context *ctx) +{ + uint8_t size = VB2_SECDATA_KERNEL_MIN_SIZE; + + RETURN_ON_FAILURE(tlcl_read(KERNEL_NV_INDEX, ctx->secdata_kernel, + size)); + + if (vb2api_secdata_kernel_check(ctx, &size) + == VB2_ERROR_SECDATA_KERNEL_INCOMPLETE) + /* Re-read. vboot will run the check and handle errors. */ + RETURN_ON_FAILURE(tlcl_read(KERNEL_NV_INDEX, + ctx->secdata_kernel, size)); + + return TPM_SUCCESS; +} + static uint32_t read_space_rec_hash(uint8_t *data) { RETURN_ON_FAILURE(tlcl_read(REC_HASH_NV_INDEX, data, @@ -440,6 +456,15 @@ uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) VB2_SECDATA_FIRMWARE_SIZE); } +uint32_t antirollback_write_space_kernel(struct vb2_context *ctx) +{ + /* Learn the expected size. */ + uint8_t size = VB2_SECDATA_KERNEL_MIN_SIZE; + vb2api_secdata_kernel_check(ctx, &size); + + return write_secdata(KERNEL_NV_INDEX, ctx->secdata_kernel, size); +} + uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) { if (size != REC_HASH_NV_SIZE) { diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 50995e6c04..f25ee46b6f 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -61,7 +61,6 @@ static inline void vboot_run_logic(void) {} static inline int vboot_locate_cbfs(struct region_device *rdev) { return -1; } #endif -void vboot_save_nvdata_only(struct vb2_context *ctx); void vboot_save_data(struct vb2_context *ctx); /* diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 9e9e82ac6b..8e82e40bf0 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -207,10 +208,21 @@ static vb2_error_t hash_body(struct vb2_context *ctx, return VB2_SUCCESS; } -void vboot_save_nvdata_only(struct vb2_context *ctx) +void vboot_save_data(struct vb2_context *ctx) { - assert(!(ctx->flags & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | - VB2_CONTEXT_SECDATA_KERNEL_CHANGED))); + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED && + (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + printk(BIOS_INFO, "Saving secdata firmware\n"); + antirollback_write_space_firmware(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; + } + + if (ctx->flags & VB2_CONTEXT_SECDATA_KERNEL_CHANGED && + (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + printk(BIOS_INFO, "Saving secdata kernel\n"); + antirollback_write_space_kernel(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_KERNEL_CHANGED; + } if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { printk(BIOS_INFO, "Saving nvdata\n"); @@ -219,23 +231,57 @@ void vboot_save_nvdata_only(struct vb2_context *ctx) } } -void vboot_save_data(struct vb2_context *ctx) -{ - if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED) { - printk(BIOS_INFO, "Saving secdata\n"); - antirollback_write_space_firmware(ctx); - ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; - } - - vboot_save_nvdata_only(ctx); -} - static uint32_t extend_pcrs(struct vb2_context *ctx) { return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); } +#define EC_EFS_BOOT_MODE_NORMAL 0x00 +#define EC_EFS_BOOT_MODE_NO_BOOT 0x01 + +static const char *get_boot_mode_string(uint8_t boot_mode) +{ + if (boot_mode == EC_EFS_BOOT_MODE_NORMAL) + return "NORMAL"; + else if (boot_mode == EC_EFS_BOOT_MODE_NO_BOOT) + return "NO_BOOT"; + else + return "UNDEFINED"; +} + +static void check_boot_mode(struct vb2_context *ctx) +{ + uint8_t boot_mode; + int rv; + + rv = tlcl_cr50_get_boot_mode(&boot_mode); + switch (rv) { + case TPM_E_NO_SUCH_COMMAND: + printk(BIOS_WARNING, "Cr50 does not support GET_BOOT_MODE.\n"); + /* Proceed to legacy boot model. */ + return; + case TPM_SUCCESS: + break; + default: + printk(BIOS_ERR, + "Communication error in getting Cr50 boot mode.\n"); + if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) + /* Continue to boot in recovery mode */ + return; + vb2api_fail(ctx, VB2_RECOVERY_CR50_BOOT_MODE, rv); + vboot_save_data(ctx); + vboot_reboot(); + return; + } + + printk(BIOS_INFO, "Cr50 says boot_mode is %s(0x%02x).\n", + get_boot_mode_string(boot_mode), boot_mode); + + if (boot_mode == EC_EFS_BOOT_MODE_NO_BOOT) + ctx->flags |= VB2_CONTEXT_NO_BOOT; +} + /** * Verify and select the firmware in the RW image * @@ -268,8 +314,10 @@ void verstage_main(void) * check the return value here because vb2api_fw_phase1 will catch * invalid secdata and tell us what to do (=reboot). */ timestamp_add_now(TS_START_TPMINIT); - if (vboot_setup_tpm(ctx) == TPM_SUCCESS) + if (vboot_setup_tpm(ctx) == TPM_SUCCESS) { antirollback_read_space_firmware(ctx); + antirollback_read_space_kernel(ctx); + } timestamp_add_now(TS_END_TPMINIT); if (get_recovery_mode_switch()) { @@ -359,6 +407,9 @@ void verstage_main(void) timestamp_add_now(TS_END_TPMPCR); } + if (CONFIG(TPM_CR50)) + check_boot_mode(ctx); + /* Lock TPM */ timestamp_add_now(TS_START_TPMLOCK); From 4fc59af03d0d76caa0b8497ea894f360c15c1a39 Mon Sep 17 00:00:00 2001 From: BryantOu Date: Wed, 15 Apr 2020 23:17:01 -0700 Subject: [PATCH 1046/1463] mb/ocp/tiogapass: Pull POST complete pin Tioga Pass platform use GPIO pin of GPP_B20 for POST complete, BIOS needs to configure this pin for BMC to poll, so it knows when to start to access other components. Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0, the command and result are shown as below, root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value 0 root@bmc-oob:~# Change-Id: I134f80153461c5acd872587038a2207586b658dd Signed-off-by: BryantOu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/ocp/tiogapass/ramstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 8282eb09f4..16b4fd92e3 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -13,7 +13,18 @@ * GNU General Public License for more details. */ #include +#include +#include +#include void mainboard_silicon_init_params(FSPS_UPD *params) { } + +static void pull_post_complete_pin(void *unused) +{ + /* Pull Low post complete pin */ + gpio_output(GPP_B20, 0); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); From 901cb9ca46b334aeb0134fa19cc87b445420c7fa Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 21 Jan 2020 14:53:45 -0700 Subject: [PATCH 1047/1463] soc/amd/picasso: Move BERT region to cbmem Allocate storage for the BERT reserved memory in cbmem, and add it in response to a romstage hook. Add a Kconfig option for adjusting the size reserved. This is different from the Stoney Ridge implementation where it was intentionally oversized to ease MTRR use and to keep TSEG aligned. Signed-off-by: Marshall Dawson Signed-off-by: Felix Held Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 7 +++++++ src/soc/amd/picasso/mca.c | 29 +++++++++++++++++++++++++++++ src/soc/amd/picasso/memmap.c | 25 ++----------------------- 3 files changed, 38 insertions(+), 23 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 842ba0cd37..4759f01ecc 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -199,6 +199,13 @@ config ACPI_BERT ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures. +config ACPI_BERT_SIZE + hex + default 0x4000 + help + Specify the amount of DRAM reserved for gathering the data used to + generate the ACPI table. + config RO_REGION_ONLY string depends on CHROMEOS diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 2970b942ef..cdea0058a8 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -8,6 +8,7 @@ #include #include #include +#include struct mca_bank { int bank; @@ -193,3 +194,31 @@ void check_mca(void) for (i = 0 ; i < num_banks ; i++) wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); } + +void bert_reserved_region(void **start, size_t *size) +{ + const struct cbmem_entry *bert; + + *start = NULL; + *size = 0; + + bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA); + if (!bert) + return; + + *start = cbmem_entry_start(bert); + *size = cbmem_entry_size(bert); +} + +static void alloc_bert_in_cbmem(int unused) +{ + void *p; + + if (CONFIG(ACPI_BERT)) { + p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, CONFIG_ACPI_BERT_SIZE); + if (!p) + printk(BIOS_ERR, "Error: BERT region was not added\n"); + } +} + +ROMSTAGE_CBMEM_INIT_HOOK(alloc_bert_in_cbmem) diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 0c8d9c0cdf..c6fd11874a 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -16,26 +16,6 @@ #include #include -#if CONFIG(ACPI_BERT) - #if CONFIG_SMM_TSEG_SIZE == 0x0 - #define BERT_REGION_MAX_SIZE 0x100000 - #else - /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ - #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE - #endif -#else - #define BERT_REGION_MAX_SIZE 0 -#endif - -void bert_reserved_region(void **start, size_t *size) -{ - if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); - else - start = NULL; - *size = BERT_REGION_MAX_SIZE; -} - void *cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM); @@ -45,13 +25,12 @@ void *cbmem_top_chipset(void) /* 8MB alignment to keep MTRR usage low */ return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); + - CONFIG_SMM_TSEG_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return (uintptr_t)cbmem_top(); } static size_t smm_region_size(void) From 365f52eb1f3692133bae8cc7e0cac5dc81d9de92 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 18 Feb 2020 22:59:23 -0700 Subject: [PATCH 1048/1463] vc/amd/agesa/f14: Fix function return type F14GetNbCofVidUpdate() is declared elsewhere to be of type F_CPU_IS_NBCOF_INIT_NEEDED, which is supposed to return a boolean value (not an AGESA status). This is fixed in the corresponding f15tn and f16kb code, so apply the same change here. This fixes a compiler error when using LTO. Change-Id: Ifc44e2c0467f8bd1f537b5a69c501ba51053d3d9 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39013 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- .../amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c | 4 ++-- .../amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c index e7614a6c17..9f0c4d2399 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c @@ -384,7 +384,7 @@ F14IsNbPstateEnabled ( * * @retval AGESA_SUCCESS Always succeeds. */ -AGESA_STATUS +BOOLEAN F14GetNbCofVidUpdate ( IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PCI_ADDR *PciAddress, @@ -393,7 +393,7 @@ F14GetNbCofVidUpdate ( ) { *NbCofVidUpdateRequired = FALSE; - return (AGESA_SUCCESS); + return FALSE; } /*---------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h index 8bf3dc39ca..8b9f31ca6d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h @@ -99,7 +99,7 @@ F14GetCurrentNbFrequency ( IN AMD_CONFIG_PARAMS *StdHeader ); -AGESA_STATUS +BOOLEAN F14GetNbCofVidUpdate ( IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PCI_ADDR *PciAddress, From 0e2d515b99634e3bee2479a17a9717ca939e5ac1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 16 Apr 2020 23:52:55 +0200 Subject: [PATCH 1049/1463] soc/intel/*/vr_config.c: Use __func__ in error message The error message has been copy-pasted across various functions, so it is nearly impossible to know which function printed it. So, use __func__ to print that information. Change-Id: I55438c2b36cc3b21f3f168bf98b0aca5fd50bbbc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40446 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/vr_config.c | 6 +++--- src/soc/intel/skylake/vr_config.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 87fb0f0a87..455980c64f 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -305,7 +305,7 @@ static uint16_t get_sku_icc_max(int domain) return icc_max[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); } return 0; } @@ -398,7 +398,7 @@ static uint16_t get_sku_ac_dc_loadline(const int domain) return loadline[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); } return 0; } @@ -492,7 +492,7 @@ static uint16_t get_sku_tdc_powerlimit(int domain) return tdc[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); } return 0; diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index c7db74a076..391222e9aa 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -223,7 +223,7 @@ static uint16_t get_sku_icc_max(int domain) return icc_max[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); } return 0; } @@ -293,7 +293,7 @@ static uint16_t get_sku_ac_dc_loadline(const int domain) return loadline[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); } return 0; } From d6d9a4e8c5630e7fb72d9b7d496ada4e8465daa5 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 2 Feb 2020 18:33:52 -0500 Subject: [PATCH 1050/1463] asus/p2b-ls: Transform into variant Boot tested on hardware. Change-Id: I24afd67dada135a8c2597f5ac1c7e91ce43897c9 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/39901 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b-ls/Kconfig | 39 --- src/mainboard/asus/p2b-ls/Kconfig.name | 2 - src/mainboard/asus/p2b-ls/acpi_tables.c | 10 - src/mainboard/asus/p2b-ls/dsdt.asl | 258 ------------------ src/mainboard/asus/p2b-ls/romstage.c | 26 -- src/mainboard/asus/p2b/Kconfig | 8 +- src/mainboard/asus/p2b/Kconfig.name | 3 + src/mainboard/asus/p2b/dsdt.asl | 18 ++ .../{ => p2b/variants}/p2b-ls/board_info.txt | 0 .../{ => p2b/variants}/p2b-ls/devicetree.cb | 0 .../{ => p2b/variants}/p2b-ls/irq_tables.c | 0 11 files changed, 27 insertions(+), 337 deletions(-) delete mode 100644 src/mainboard/asus/p2b-ls/Kconfig delete mode 100644 src/mainboard/asus/p2b-ls/Kconfig.name delete mode 100644 src/mainboard/asus/p2b-ls/acpi_tables.c delete mode 100644 src/mainboard/asus/p2b-ls/dsdt.asl delete mode 100644 src/mainboard/asus/p2b-ls/romstage.c rename src/mainboard/asus/{ => p2b/variants}/p2b-ls/board_info.txt (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-ls/devicetree.cb (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-ls/irq_tables.c (100%) diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig deleted file mode 100644 index 2d12c86045..0000000000 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_LS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - select HAVE_ACPI_TABLES - -config MAINBOARD_DIR - string - default "asus/p2b-ls" - -config MAINBOARD_PART_NUMBER - string - default "P2B-LS" - -config IRQ_SLOT_COUNT - int - default 8 - -endif # BOARD_ASUS_P2B_LS diff --git a/src/mainboard/asus/p2b-ls/Kconfig.name b/src/mainboard/asus/p2b-ls/Kconfig.name deleted file mode 100644 index 0ad0f4744c..0000000000 --- a/src/mainboard/asus/p2b-ls/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_LS - bool "P2B-LS" diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c deleted file mode 100644 index 9f18039c32..0000000000 --- a/src/mainboard/asus/p2b-ls/acpi_tables.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* mainboard has no ioapic */ - return current; -} diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl deleted file mode 100644 index b49e0a1df0..0000000000 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include - -#define SUPERIO_PNP_BASE 0x3F0 -#define SUPERIO_SHOW_UARTA -#define SUPERIO_SHOW_UARTB -#define SUPERIO_SHOW_FDC -#define SUPERIO_SHOW_LPT - -#include -DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) -{ - /* \_SB scope defining the main processor is generated in SSDT. */ - - OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) - { - P80, 8 - } - - /* - * For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - - /* - * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 - * - * 0: soft off/suspend to disk S5 - * 1: suspend to ram S3 - * 2: powered on suspend, context lost S2 - * Note: 'context lost' means the CPU restarts at the reset - * vector - * 3: powered on suspend, CPU context lost S1 - * Note: Looks like 'CPU context lost' does _not_ mean the - * CPU restarts at the reset vector. Most likely only - * caches are lost, so both 0x3 and 0x4 map to ACPI S1 - * 4: powered on suspend, context maintained S1 - * 5: working (clock control) S0 - * 6: reserved - * 7: reserved - */ - Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) - /* - * Kept as a memo of the value needed, but blocked out until - * suspend/resume support is implemented. - */ - /*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/ - /*Name (\_S4, Package () { 0x01, 0x06, 0x00, 0x00 })*/ - Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 }) - - OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10) - Field (GPOB, ByteAcc, NoLock, Preserve) - { - Offset (0x03), - TO12, 1, /* Device trap 12 */ - Offset (0x08), - FANM, 1, /* GPO0, meant for fan */ - Offset (0x09), - PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */ - , 3, /* this goes low when power is cut from its core. */ - , 2, - , 16, - MSG0, 1 /* GPO30, message LED */ - } - - /* Prepare To Sleep, Arg0 is target S-state */ - Method (\_PTS, 1, NotSerialized) - { - /* Disable fan, blink power LED, if not turning off */ - If (LNotEqual (Arg0, 0x05)) - { - Store (Zero, FANM) - Store (Zero, PLED) - } - - /* Arms SMI for device 12 */ - Store (One, TO12) - /* Put out a POST code */ - Or (Arg0, 0xF0, P80) - } - - Method (\_WAK, 1, NotSerialized) - { - /* Re-enable fan, stop power led blinking */ - Store (One, FANM) - Store (One, PLED) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) - } - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - Device (PWRB) - { - /* Power Button Device */ - Name (_HID, EisaId ("PNP0C0C")) - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } - #include - - PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) - PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) - PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3) - PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4) - - /* Top PCI device */ - Device (PCI0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x00) - Name (_BBN, 0x00) - - /* PCI Routing Table */ - Name (_PRT, Package () { - Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, - Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, - Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, - Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, - - Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, - Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, - Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, - Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, - - Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, - Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, - Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, - Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, - - Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, - Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, - Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, - Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, - - Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, - Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, - Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, - Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, - - Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, - Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, - Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, - Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, - - Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, - Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, - Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, - Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, - - Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, - Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, - Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, - Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, - - }) - #include - - /* Begin southbridge block */ - Device (PX40) - { - Name(_ADR, 0x00040000) - OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) - Field (PIRQ, ByteAcc, NoLock, Preserve) - { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8 - } - - /* PNP Motherboard Resources */ - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () - { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) - /* PIIX4E ports */ - /* Aliased DMA ports */ - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) - /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) - /* Aliased timer ports */ - IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) - IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) - IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) - IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) - }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) - Return (BUF1) - } - } - #include - } - Device (PX43) - { - Name (_ADR, 0x00040003) // _ADR: Address - OperationRegion (IPMU, PCI_Config, PMBA, 0x02) - Field (IPMU, ByteAcc, NoLock, Preserve) - { - PM00, 16 - } - - OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) - Field (ISMB, ByteAcc, NoLock, Preserve) - { - SB00, 16 - } - } - - #include - } - } - - /* ACPI Message */ - Scope (\_SI) - { - Method (_MSG, 1, NotSerialized) - { - If (LEqual (Arg0, Zero)) - { - Store (One, MSG0) - } - Else - { - Store (Zero, MSG0) - } - } - } -} diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c deleted file mode 100644 index 546d9ed419..0000000000 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ -#include - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 503e662661..694469dd42 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -11,7 +11,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B || BOARD_ASUS_P2B_F +if BOARD_ASUS_P2B || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS config BOARD_SPECIFIC_OPTIONS def_bool y @@ -21,7 +21,8 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 - select HAVE_ACPI_TABLES if BOARD_ASUS_P2B + select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS config MAINBOARD_DIR string @@ -31,11 +32,13 @@ config MAINBOARD_PART_NUMBER string default "P2B" if BOARD_ASUS_P2B default "P2B-F" if BOARD_ASUS_P2B_F + default "P2B-LS" if BOARD_ASUS_P2B_LS config VARIANT_DIR string default "p2b" if BOARD_ASUS_P2B default "p2b-f" if BOARD_ASUS_P2B_F + default "p2b-ls" if BOARD_ASUS_P2B_LS config DEVICETREE string @@ -43,6 +46,7 @@ config DEVICETREE config IRQ_SLOT_COUNT int + default 8 if BOARD_ASUS_P2B_LS default 7 if BOARD_ASUS_P2B_F default 6 diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index ee34b16088..fd645f07c1 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -3,3 +3,6 @@ config BOARD_ASUS_P2B config BOARD_ASUS_P2B_F bool "P2B-F" + +config BOARD_ASUS_P2B_LS + bool "P2B-LS" diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 4bfcc319e8..05af7202c8 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -44,9 +44,15 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) * 6: reserved * 7: reserved */ + /* Guard these entries for the purpose of variant validation. They will be aligned later. */ Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) +#if CONFIG(BOARD_ASUS_P2B) Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) +#endif +#if CONFIG(BOARD_ASUS_P2B_LS) + Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 }) +#endif OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10) Field (GPOB, ByteAcc, NoLock, Preserve) @@ -126,6 +132,12 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, +#if CONFIG(BOARD_ASUS_P2B_LS) + Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, +#endif Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, @@ -136,6 +148,12 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, +#if CONFIG(BOARD_ASUS_P2B_LS) + Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, + Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, + Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, + Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, +#endif Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, diff --git a/src/mainboard/asus/p2b-ls/board_info.txt b/src/mainboard/asus/p2b/variants/p2b-ls/board_info.txt similarity index 100% rename from src/mainboard/asus/p2b-ls/board_info.txt rename to src/mainboard/asus/p2b/variants/p2b-ls/board_info.txt diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-ls/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb diff --git a/src/mainboard/asus/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-ls/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c From 6f1494b25277af88cf1a7c010c1a75e641f45a08 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 2 Feb 2020 20:23:03 -0500 Subject: [PATCH 1051/1463] asus/p2b-d: Transform into variant TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I1161c726c8c752b5b1e152e1617811989631096e Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/39903 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b-d/Kconfig | 45 ------------------- src/mainboard/asus/p2b-d/Kconfig.name | 2 - src/mainboard/asus/p2b-d/romstage.c | 17 ------- src/mainboard/asus/p2b/Kconfig | 16 ++++++- src/mainboard/asus/p2b/Kconfig.name | 3 ++ src/mainboard/asus/p2b/Makefile.inc | 1 + .../{ => p2b/variants}/p2b-d/board_info.txt | 0 .../{ => p2b/variants}/p2b-d/devicetree.cb | 0 .../{ => p2b/variants}/p2b-d/irq_tables.c | 0 .../asus/{ => p2b/variants}/p2b-d/mptable.c | 0 10 files changed, 19 insertions(+), 65 deletions(-) delete mode 100644 src/mainboard/asus/p2b-d/Kconfig delete mode 100644 src/mainboard/asus/p2b-d/Kconfig.name delete mode 100644 src/mainboard/asus/p2b-d/romstage.c rename src/mainboard/asus/{ => p2b/variants}/p2b-d/board_info.txt (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-d/devicetree.cb (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-d/irq_tables.c (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-d/mptable.c (100%) diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig deleted file mode 100644 index 2b61db7012..0000000000 --- a/src/mainboard/asus/p2b-d/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_D - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select IOAPIC - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - -config MAINBOARD_DIR - string - default "asus/p2b-d" - -config MAINBOARD_PART_NUMBER - string - default "P2B-D" - -config IRQ_SLOT_COUNT - int - default 6 - -config MAX_CPUS - int - default 2 - -endif # BOARD_ASUS_P2B_D diff --git a/src/mainboard/asus/p2b-d/Kconfig.name b/src/mainboard/asus/p2b-d/Kconfig.name deleted file mode 100644 index 23e78088c0..0000000000 --- a/src/mainboard/asus/p2b-d/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_D - bool "P2B-D" diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c deleted file mode 100644 index b996f1ee57..0000000000 --- a/src/mainboard/asus/p2b-d/romstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Shares romstage with P2B-DS */ -#include "../p2b-ds/romstage.c" diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 694469dd42..36d882fe35 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -11,7 +11,14 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS +if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS + +config BASE_ASUS_P2B_D + def_bool n + select SDRAMPWR_4DIMM + select HAVE_MP_TABLE + select IOAPIC + select SMP config BOARD_SPECIFIC_OPTIONS def_bool y @@ -23,6 +30,11 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS + select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D + +config MAX_CPUS + int + default 2 if BASE_ASUS_P2B_D config MAINBOARD_DIR string @@ -31,12 +43,14 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string default "P2B" if BOARD_ASUS_P2B + default "P2B-D" if BOARD_ASUS_P2B_D default "P2B-F" if BOARD_ASUS_P2B_F default "P2B-LS" if BOARD_ASUS_P2B_LS config VARIANT_DIR string default "p2b" if BOARD_ASUS_P2B + default "p2b-d" if BOARD_ASUS_P2B_D default "p2b-f" if BOARD_ASUS_P2B_F default "p2b-ls" if BOARD_ASUS_P2B_LS diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index fd645f07c1..8c42258af8 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -1,6 +1,9 @@ config BOARD_ASUS_P2B bool "P2B" +config BOARD_ASUS_P2B_D + bool "P2B-D" + config BOARD_ASUS_P2B_F bool "P2B-F" diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc index 640396eea4..ca08106480 100644 --- a/src/mainboard/asus/p2b/Makefile.inc +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c +ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c diff --git a/src/mainboard/asus/p2b-d/board_info.txt b/src/mainboard/asus/p2b/variants/p2b-d/board_info.txt similarity index 100% rename from src/mainboard/asus/p2b-d/board_info.txt rename to src/mainboard/asus/p2b/variants/p2b-d/board_info.txt diff --git a/src/mainboard/asus/p2b-d/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-d/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-d/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c similarity index 100% rename from src/mainboard/asus/p2b-d/mptable.c rename to src/mainboard/asus/p2b/variants/p2b-d/mptable.c From b7c11c6953285f64603a6e1a115b2fdc1505d832 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 2 Feb 2020 20:36:26 -0500 Subject: [PATCH 1052/1463] asus/p2b-ds: Transform into variant TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I864f939a84ee9e90013ba9d3fcc8a7e4bf03e4ee Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/39904 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b-ds/Kconfig | 45 ------------------- src/mainboard/asus/p2b-ds/Kconfig.name | 2 - src/mainboard/asus/p2b-ds/romstage.c | 25 ----------- src/mainboard/asus/p2b/Kconfig | 8 ++-- src/mainboard/asus/p2b/Kconfig.name | 3 ++ .../{ => p2b/variants}/p2b-ds/board_info.txt | 0 .../{ => p2b/variants}/p2b-ds/devicetree.cb | 0 .../{ => p2b/variants}/p2b-ds/irq_tables.c | 0 .../asus/{ => p2b/variants}/p2b-ds/mptable.c | 0 9 files changed, 8 insertions(+), 75 deletions(-) delete mode 100644 src/mainboard/asus/p2b-ds/Kconfig delete mode 100644 src/mainboard/asus/p2b-ds/Kconfig.name delete mode 100644 src/mainboard/asus/p2b-ds/romstage.c rename src/mainboard/asus/{ => p2b/variants}/p2b-ds/board_info.txt (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-ds/devicetree.cb (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-ds/irq_tables.c (100%) rename src/mainboard/asus/{ => p2b/variants}/p2b-ds/mptable.c (100%) diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig deleted file mode 100644 index be03d1b44f..0000000000 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_DS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select IOAPIC - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - -config MAINBOARD_DIR - string - default "asus/p2b-ds" - -config MAINBOARD_PART_NUMBER - string - default "P2B-DS" - -config IRQ_SLOT_COUNT - int - default 7 - -config MAX_CPUS - int - default 2 - -endif # BOARD_ASUS_P2B_DS diff --git a/src/mainboard/asus/p2b-ds/Kconfig.name b/src/mainboard/asus/p2b-ds/Kconfig.name deleted file mode 100644 index 0335139821..0000000000 --- a/src/mainboard/asus/p2b-ds/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_DS - bool "P2B-DS" diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c deleted file mode 100644 index 67ba632ece..0000000000 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 36d882fe35..3895990eaa 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -11,7 +11,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS +if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS config BASE_ASUS_P2B_D def_bool n @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS - select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D + select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS config MAX_CPUS int @@ -44,6 +44,7 @@ config MAINBOARD_PART_NUMBER string default "P2B" if BOARD_ASUS_P2B default "P2B-D" if BOARD_ASUS_P2B_D + default "P2B-DS" if BOARD_ASUS_P2B_DS default "P2B-F" if BOARD_ASUS_P2B_F default "P2B-LS" if BOARD_ASUS_P2B_LS @@ -51,6 +52,7 @@ config VARIANT_DIR string default "p2b" if BOARD_ASUS_P2B default "p2b-d" if BOARD_ASUS_P2B_D + default "p2b-ds" if BOARD_ASUS_P2B_DS default "p2b-f" if BOARD_ASUS_P2B_F default "p2b-ls" if BOARD_ASUS_P2B_LS @@ -61,7 +63,7 @@ config DEVICETREE config IRQ_SLOT_COUNT int default 8 if BOARD_ASUS_P2B_LS - default 7 if BOARD_ASUS_P2B_F + default 7 if BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_DS default 6 endif diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index 8c42258af8..106e69445e 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -4,6 +4,9 @@ config BOARD_ASUS_P2B config BOARD_ASUS_P2B_D bool "P2B-D" +config BOARD_ASUS_P2B_DS + bool "P2B-DS" + config BOARD_ASUS_P2B_F bool "P2B-F" diff --git a/src/mainboard/asus/p2b-ds/board_info.txt b/src/mainboard/asus/p2b/variants/p2b-ds/board_info.txt similarity index 100% rename from src/mainboard/asus/p2b-ds/board_info.txt rename to src/mainboard/asus/p2b/variants/p2b-ds/board_info.txt diff --git a/src/mainboard/asus/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-ds/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-ds/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c similarity index 100% rename from src/mainboard/asus/p2b-ds/mptable.c rename to src/mainboard/asus/p2b/variants/p2b-ds/mptable.c From 5d8ad8598bc5043bde2329aa5be561f6a1e308cd Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 2 Feb 2020 00:26:59 -0500 Subject: [PATCH 1053/1463] asus/p2b*: Move serial init into mainboard bootblock With this bootblock messages are transmitted over serial too. TEST=Serial messages transmitted normally on asus/p2b-ls. Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38670 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/p2b/Makefile.inc | 2 ++ src/mainboard/asus/p2b/bootblock.c | 13 +++++++++++++ src/mainboard/asus/p2b/romstage.c | 25 ------------------------- src/northbridge/intel/i440bx/romstage.c | 4 ---- 4 files changed, 15 insertions(+), 29 deletions(-) create mode 100644 src/mainboard/asus/p2b/bootblock.c delete mode 100644 src/mainboard/asus/p2b/romstage.c diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc index ca08106480..cc55c25a20 100644 --- a/src/mainboard/asus/p2b/Makefile.inc +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -1,2 +1,4 @@ +bootblock-y += bootblock.c + ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c diff --git a/src/mainboard/asus/p2b/bootblock.c b/src/mainboard/asus/p2b/bootblock.c new file mode 100644 index 0000000000..18eff07355 --- /dev/null +++ b/src/mainboard/asus/p2b/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c deleted file mode 100644 index 67ba632ece..0000000000 --- a/src/mainboard/asus/p2b/romstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index 1dee03a984..bdcfdc9b85 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -14,15 +14,11 @@ #include #include -#include #include #include void mainboard_romstage_entry(void) { - mainboard_enable_serial(); - console_init(); - i82371eb_early_init(); sdram_initialize(); From 3acf43c336a8ae83200e862aecbc7c2eb3e52893 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 27 Jan 2020 18:08:30 -0500 Subject: [PATCH 1054/1463] i82371eb: Drop KB/Mouse/FDC declarations These are declared by superio. Change-Id: I1db4aca7d682ec298b8f53cfab6ffe661e8ff6e0 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38600 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../intel/i82371eb/acpi/isabridge.asl | 68 ------------------- 1 file changed, 68 deletions(-) diff --git a/src/southbridge/intel/i82371eb/acpi/isabridge.asl b/src/southbridge/intel/i82371eb/acpi/isabridge.asl index 55a0ca560e..1298618649 100644 --- a/src/southbridge/intel/i82371eb/acpi/isabridge.asl +++ b/src/southbridge/intel/i82371eb/acpi/isabridge.asl @@ -1,74 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -// Intel LPC Bus Device - 0:4.0 -Device (LPCB) -{ - Name(_ADR, 0x00040000) - - OperationRegion(PCIC, PCI_Config, 0x00, 0x100) - - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - - /* PS/2 floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) - IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } -} - Device(MBRS) { Name (_HID, EisaId ("PNP0C02")) Name (_UID, 0x01) From 75f4776610c7d24d0c48dc48ff2a236ea914a80c Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 27 Jan 2020 18:17:58 -0500 Subject: [PATCH 1055/1463] asus/p2b*: Declare \_SB.PCI0.MBRS in DSDT sb/intel/i82371eb/isa.c has code that fills this path with CPU info. Because it was not declared in the DSDT, Linux kernel 4.4.18 as used in Slackware 14.2 complains. Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38601 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b/dsdt.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 05af7202c8..5bc5d72db9 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -166,6 +166,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) }) #include + #include /* Begin southbridge block */ Device (PX40) @@ -184,6 +185,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) Device (SYSR) { Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () From 18f888598da2a0cf3458736c3f56b31986f28d29 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 23 Oct 2019 22:07:58 +0200 Subject: [PATCH 1056/1463] mb/lenovo/t420(s): Do minor cosmetic changes Align the whitespace and do some cosmetic changes. This makes it easier to fold these two boards into a variant setup. Change-Id: I53bdd90ae47b52dfdfec27229c6b904487fa2081 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40380 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/mainboard/lenovo/t420/cmos.layout | 4 ++-- src/mainboard/lenovo/t420s/Kconfig | 4 ++-- src/mainboard/lenovo/t420s/devicetree.cb | 2 ++ src/mainboard/lenovo/t420s/early_init.c | 4 ++-- src/mainboard/lenovo/t420s/gpio.c | 7 ++++--- src/mainboard/lenovo/t420s/smihandler.c | 2 +- 6 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index f9b75f293f..26e63005bb 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -74,8 +74,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index f29d50fe96..e2fd824f33 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -16,10 +16,10 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_PANEL_1_ON_LVDS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_PANEL_1_ON_LVDS select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 1f794c1b24..b3399c32a3 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(1)" # Enable DisplayPort Hotplug with 6ms pulse @@ -66,6 +67,7 @@ chip northbridge/intel/sandybridge register "c2_latency" = "101" # c2 not supported + # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 212be38fec..4f5f69d4dc 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -35,8 +35,8 @@ static void hybrid_graphics_init(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0 empty */ - { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ + { 0, 1, -1 }, /* P0: empty */ + { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ { 1, 0, -1 }, /* P3: WWAN, no OC */ { 1, 1, -1 }, /* P4: smartcard, no OC */ diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420s/gpio.c index 0b64efe268..daca020da0 100644 --- a/src/mainboard/lenovo/t420s/gpio.c +++ b/src/mainboard/lenovo/t420s/gpio.c @@ -2,6 +2,7 @@ /* This file is part of the coreboot project. */ #include + static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input @@ -69,7 +70,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio28 = GPIO_DIR_OUTPUT, .gpio29 = GPIO_DIR_OUTPUT, .gpio30 = GPIO_DIR_OUTPUT, - .gpio31 = GPIO_DIR_INPUT + .gpio31 = GPIO_DIR_INPUT, }; static const struct pch_gpio_set1 pch_gpio_set1_level = { @@ -108,8 +109,8 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = { }; static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_INVERT, - .gpio1 = GPIO_INVERT, + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 84b9c3a732..443299573a 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -6,8 +6,8 @@ #include #include #include -#include #include +#include #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 From ab734d8c057d103c7aafd09182c375c3d522e947 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 18 Feb 2020 23:08:07 -0700 Subject: [PATCH 1057/1463] vc/amd/agesa/f14: Fix array length This array is declared to have length MAX_FF_TYPES (aka 6) in several other places, so update it here so the length matches. This fixes a -Wlto-type-mismatch compiler error when using LTO. Extending the length is harmless, since the only code that uses this array will stop once it reaches the NULL pointer. Change-Id: Ie00e969fa8cda88a934bf416c8775f7ae0b2747e Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39014 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h index 231b263312..600ae9b4e8 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h @@ -569,7 +569,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = { + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { PLAT_SP_ON_FF_SDIMM3 PLAT_SP_ON_FF_UDIMM3 NULL From 9e3e49234d30dadd5888b389ed572a2faac1c6af Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 24 Feb 2020 19:06:07 -0700 Subject: [PATCH 1058/1463] vc/amd/agesa/f15tn,f16kb: Fix array types These variables are declared to be arrays of MICROCODE_PATCHES_4K (which is a struct containing a UINT8 array). However, the actual definitions of these arrays ignore the wrapping struct and just use the underlying UINT8 arrays directly, which causes a compiler error when using LTO because of the type mismatch. Fix the type declaration so that it matches. Change-Id: I6bef27507092fe72fe2f836c427ebb2c19009e78 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40436 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- .../f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c | 2 +- .../f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c index c0ca136523..a3e7e5ddce 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c @@ -65,7 +65,7 @@ RDATA_GROUP (G3_DXE) * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ -extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15TnMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[]; extern CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches; /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c index 4790709618..519b4ec1f9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c @@ -65,7 +65,7 @@ RDATA_GROUP (G3_DXE) * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ -extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF16KbMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[]; extern CONST UINT8 ROMDATA CpuF16KbNumberOfMicrocodePatches; /*---------------------------------------------------------------------------------------- From 069cd678546c9b433442e1dbeea46d3a5e923aa5 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 18 Feb 2020 23:29:21 -0700 Subject: [PATCH 1059/1463] mb/intel/harcuvar: Fix board_id() return type The weak definition of board_id() in coreboot_table.c returns a uint32_t, so update this function to match. This fixes a compiler error when using LTO. Change-Id: I6ad03ecedcf4a4d9f0c917cdc760f81ddde06d11 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/39015 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/mainboard/intel/harcuvar/boardid.c | 2 +- src/mainboard/intel/harcuvar/harcuvar_boardid.h | 2 +- src/mainboard/intel/harcuvar/hsio.c | 2 +- src/mainboard/intel/harcuvar/romstage.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/harcuvar/boardid.c b/src/mainboard/intel/harcuvar/boardid.c index 8f91b0c61d..a9d9af630f 100644 --- a/src/mainboard/intel/harcuvar/boardid.c +++ b/src/mainboard/intel/harcuvar/boardid.c @@ -5,7 +5,7 @@ #include "harcuvar_boardid.h" -uint8_t board_id(void) +uint32_t board_id(void) { int id = BoardIdHarcuvar; diff --git a/src/mainboard/intel/harcuvar/harcuvar_boardid.h b/src/mainboard/intel/harcuvar/harcuvar_boardid.h index 28f28d9135..cb05090bc6 100644 --- a/src/mainboard/intel/harcuvar/harcuvar_boardid.h +++ b/src/mainboard/intel/harcuvar/harcuvar_boardid.h @@ -8,6 +8,6 @@ #define BoardIdHarcuvar 0x52 -uint8_t board_id(void); +uint32_t board_id(void); #endif /* MAINBOARD_BOARD_H */ diff --git a/src/mainboard/intel/harcuvar/hsio.c b/src/mainboard/intel/harcuvar/hsio.c index d786b8fb2e..948f3263fc 100644 --- a/src/mainboard/intel/harcuvar/hsio.c +++ b/src/mainboard/intel/harcuvar/hsio.c @@ -7,7 +7,7 @@ size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) { - uint8_t boardid = board_id(); + uint32_t boardid = board_id(); size_t num; switch (boardid) { case BoardIdHarcuvar: diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index a5c13277f1..542f81e005 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -88,7 +88,7 @@ void mainboard_config_gpios(void) { size_t num; const struct dnv_pad_config *table; - uint8_t boardid = board_id(); + uint32_t boardid = board_id(); /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. From e9605bb153b199d2539eb0456144acec6658feb4 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 12 Apr 2020 00:07:26 +0200 Subject: [PATCH 1060/1463] mb/qemu-q35: Select `HAVE_CMOS_DEFAULT` Change-Id: If4c4dc9467154a18168550538fc8e655636e87a0 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40318 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/emulation/qemu-q35/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 31aa3d8723..6a0903d7cf 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82801IX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS + select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES From 3e7633a6fe48c09e08bdea06c93afbf61fb7f7c2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 12 Apr 2020 00:07:49 +0200 Subject: [PATCH 1061/1463] mb/qemu-i440fx,q35: Fix option table Reserve bytes 50 and 55 as they are handled as century bytes by QEMU. Change-Id: I9271253bce560d4ec8a51a24c45473acec469187 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40319 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/emulation/qemu-i440fx/cmos.layout | 12 ++++++++---- src/mainboard/emulation/qemu-q35/cmos.layout | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index 247a6a08a5..9019afb7a3 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -1,11 +1,15 @@ entries 0 384 r 0 reserved_memory + 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level + +400 8 r 0 reserved_century +440 8 r 0 reserved_ibm_ps2_century + +448 1 e 1 power_on_after_fail +452 4 e 6 debug_level 456 1 e 1 ECC_memory # VBOOT @@ -29,4 +33,4 @@ enumerations checksums -checksum 392 463 1008 +checksum 448 463 1008 diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index 247a6a08a5..9019afb7a3 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -1,11 +1,15 @@ entries 0 384 r 0 reserved_memory + 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level + +400 8 r 0 reserved_century +440 8 r 0 reserved_ibm_ps2_century + +448 1 e 1 power_on_after_fail +452 4 e 6 debug_level 456 1 e 1 ECC_memory # VBOOT @@ -29,4 +33,4 @@ enumerations checksums -checksum 392 463 1008 +checksum 448 463 1008 From 64ba44f7fb7a64c5cc1e9155758b57589320b1a5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 12 Apr 2020 00:10:51 +0200 Subject: [PATCH 1062/1463] drivers/pc80/rtc: Turn comment into warning message MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I80786042b1c464268cae8093bd5d3e8d73be5aee Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40320 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/drivers/pc80/rtc/mc146818rtc_boot.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 37f1470b9f..d470d8fcfb 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -2,6 +2,7 @@ /* This file is part of the coreboot project. */ #include +#include #include #include #include @@ -35,9 +36,8 @@ int do_normal_boot(void) unsigned char byte; if (cmos_error() || (CONFIG(USE_OPTION_TABLE) && !cmos_lb_cks_valid())) { - /* Invalid CMOS checksum detected! - * Force fallback boot... - */ + printk(BIOS_WARNING, + "Invalid CMOS checksum detected! Force fallback boot...\n"); byte = cmos_read(RTC_BOOT_BYTE); byte &= boot_set_fallback(byte) & 0x0f; byte |= 0xf << 4; From fc9302465ba1e78f9a99440e1898b3714861290d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 24 Mar 2020 11:12:09 +0100 Subject: [PATCH 1063/1463] nb/intel/sandybridge: Refactor get_mem_min_tck It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit.c | 11 ++- .../intel/sandybridge/raminit_common.c | 69 ----------------- .../intel/sandybridge/raminit_common.h | 1 - .../intel/sandybridge/raminit_native.c | 77 +++++++++++++++++++ 4 files changed, 82 insertions(+), 76 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index e138756d9b..6c8145d13d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -226,11 +226,10 @@ static void save_timings(ramctr_timing *ctrl) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); } -static void reinit_ctrl(ramctr_timing *ctrl, int min_tck, const u32 cpuid) +static void reinit_ctrl(ramctr_timing *ctrl, const u32 cpuid) { /* Reset internal state */ memset(ctrl, 0, sizeof(*ctrl)); - ctrl->tCK = min_tck; /* Get architecture */ ctrl->cpu = cpuid; @@ -243,7 +242,7 @@ static void reinit_ctrl(ramctr_timing *ctrl, int min_tck, const u32 cpuid) ctrl->ecc_forced ? "yes" : "no"); } -static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) +static void init_dram_ddr3(int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; @@ -329,7 +328,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) } if (!fast_boot) { /* Reset internal state */ - reinit_ctrl(&ctrl, min_tck, cpuid); + reinit_ctrl(&ctrl, cpuid); printk(BIOS_INFO, "ECC RAM %s.\n", ctrl.ecc_forced ? "required" : ctrl.ecc_supported ? "supported" : "unsupported"); @@ -348,7 +347,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) printram("Disable failing channel.\n"); /* Reset internal state */ - reinit_ctrl(&ctrl, min_tck, cpuid); + reinit_ctrl(&ctrl, cpuid); /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); @@ -398,5 +397,5 @@ void perform_raminit(int s3resume) timestamp_add_now(TS_BEFORE_INITRAM); - init_dram_ddr3(get_mem_min_tck(), s3resume, cpu_get_cpuid()); + init_dram_ddr3(s3resume, cpu_get_cpuid()); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 51f33629f1..087ba2b550 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -358,75 +358,6 @@ void dram_zones(ramctr_timing *ctrl, int training) } } -#define DEFAULT_TCK TCK_800MHZ - -unsigned int get_mem_min_tck(void) -{ - u32 reg32; - u8 rev; - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->max_mem_clock_mhz == 0) { - - if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) - return TCK_1333MHZ; - - rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); - - if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { - /* Read Capabilities A Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); - reg32 &= 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - /* Reserved */ - default: - break; - } - } else { - /* Read Capabilities B Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); - reg32 = (reg32 >> 4) & 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - case 4: return TCK_933MHZ; - case 3: return TCK_1066MHZ; - case 2: return TCK_1200MHZ; - case 1: return TCK_1333MHZ; - /* Reserved */ - default: - break; - } - } - return DEFAULT_TCK; - } else { - if (cfg->max_mem_clock_mhz >= 1066) - return TCK_1066MHZ; - else if (cfg->max_mem_clock_mhz >= 933) - return TCK_933MHZ; - else if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - else - return TCK_400MHZ; - } -} - #define DEFAULT_PCI_MMIO_SIZE 2048 static unsigned int get_mmio_size(void) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 93541b50fd..314c67de80 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -174,7 +174,6 @@ void dram_timing_regs(ramctr_timing *ctrl); void dram_dimm_mapping(ramctr_timing *ctrl); void dram_dimm_set_mapping(ramctr_timing *ctrl, int training); void dram_zones(ramctr_timing *ctrl, int training); -unsigned int get_mem_min_tck(void); void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); void dram_jedecreset(ramctr_timing *ctrl); int read_training(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 99c1a4c4ff..832391f72e 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -5,7 +5,10 @@ #include #include #include +#include +#include #include +#include #include "raminit_native.h" #include "raminit_common.h" #include "raminit_tables.h" @@ -174,6 +177,78 @@ static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) } } +#define DEFAULT_TCK TCK_800MHZ + +static unsigned int get_mem_min_tck(void) +{ + u32 reg32; + u8 rev; + const struct northbridge_intel_sandybridge_config *cfg = NULL; + + /* Actually, config of MCH or Host Bridge */ + cfg = config_of_soc(); + + /* If non-zero, it was set in the devicetree */ + if (cfg->max_mem_clock_mhz) { + + if (cfg->max_mem_clock_mhz >= 1066) + return TCK_1066MHZ; + + else if (cfg->max_mem_clock_mhz >= 933) + return TCK_933MHZ; + + else if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + + else + return TCK_400MHZ; + } + + if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) + return TCK_1333MHZ; + + rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); + + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { + /* Read Capabilities A Register DMFC bits */ + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); + reg32 &= 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + /* Reserved */ + default: + break; + } + } else { + /* Read Capabilities B Register DMFC bits */ + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); + reg32 = (reg32 >> 4) & 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + case 4: return TCK_933MHZ; + case 3: return TCK_1066MHZ; + case 2: return TCK_1200MHZ; + case 1: return TCK_1333MHZ; + /* Reserved */ + default: + break; + } + } + return DEFAULT_TCK; +} + static void find_cas_tck(ramctr_timing *ctrl) { u8 val; @@ -188,6 +263,8 @@ static void find_cas_tck(ramctr_timing *ctrl) printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); + ctrl->tCK = get_mem_min_tck(); + /* Find CAS latency */ while (1) { /* From d06a6069156b8f1d20f02ded9f0edebcc09ca87e Mon Sep 17 00:00:00 2001 From: John Su Date: Tue, 14 Apr 2020 17:42:03 +0800 Subject: [PATCH 1064/1463] mb/google/drallion: Increase Melfas touchscreen stop delay to 115ms Modify stop_delay as 115ms to waiting for Melfas device I2C interface ready after touch fw auto update and rebind driver. BUG=b:153708773 BRANCH=drallion Signed-off-by: John Su Change-Id: Ib392190d2b4188ee228d8ca4873e03176d2f127f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40357 Reviewed-by: Paul Menzel Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 60be8c9fab..9bb09abd98 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -389,7 +389,7 @@ chip soc/intel/cannonlake register "reset_delay_ms" = "10" register "reset_off_delay_ms" = "5" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "stop_delay_ms" = "10" + register "stop_delay_ms" = "115" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" From cae98879962c7c90e93c373ad6255da099305f35 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 3 Apr 2020 13:48:54 +0800 Subject: [PATCH 1065/1463] mb/google/deltaur: Enable Cirque touchpad for Deltan Reference Arcada to add device tree for Cirque touchpad. BUG=b:152931802 Signed-off-by: Eric Lai Change-Id: Ia354702c8054b5826d45896f7bff268335726028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/deltaur/variants/baseboard/devicetree.cb | 2 +- .../google/deltaur/variants/deltan/overridetree.cb | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index a30c12d633..e0b3d500d9 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -11,7 +11,7 @@ chip soc/intel/tigerlake # TODO: Figure out GPE DW1&2 register "pmc_gpe0_dw0" = "GPP_C" - #register "pmc_gpe0_dw1" = "??" + register "pmc_gpe0_dw1" = "GPP_E" #register "pmc_gpe0_dw2" = "??" # Wilco EC host command ranges diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb index be1f29f2f2..13883d1ac0 100644 --- a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -28,4 +28,16 @@ chip soc/intel/tigerlake device i2c 34 on end end end # I2C #0 + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Cirque Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.wake" = "GPE0_DW1_07" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C #1 end From 5c27182366ac1d699ea2e4cc7b28cb3fadc80f6e Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 3 Apr 2020 00:42:22 -0700 Subject: [PATCH 1066/1463] mb/tglrvp: Configure intel common config Configure lockdown and i2c speed setting. BUG:b:151161585 BRANCH=none TEST=build and boot tglrvp and check FSP logs to lockdown parameters Signed-off-by: Wonkyu Kim Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- .../tglrvp/variants/tglrvp_up3/devicetree.cb | 20 +++++++++++++++++++ .../tglrvp/variants/tglrvp_up4/devicetree.cb | 20 +++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 82303c6ddf..8b4f8f8bbf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -128,6 +128,26 @@ chip soc/intel/tigerlake # Not disconnected/enumerable register "PchHdaIDispCodecDisconnect" = "0" + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 043185bfdd..9b5774bd1c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -124,6 +124,26 @@ chip soc/intel/tigerlake # Not disconnected/enumerable register "PchHdaIDispCodecDisconnect" = "0" + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y From 97e4422a586ca2948106bce2b010113409e43c8a Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Tue, 14 Apr 2020 18:12:58 +0800 Subject: [PATCH 1067/1463] vboot: remove leftover TPM_PCR_GBB constants These constants were left behind after the code using them was relocated in CB:34510. BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: I6ce7c969a9e9bdf6cdce3343ba666a08b3521f27 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/40358 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Julius Werner --- src/security/vboot/secdata_tpm.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index b60a1bb315..c052989ebe 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -56,9 +56,6 @@ } \ } while (0) -#define TPM_PCR_GBB_FLAGS_NAME "GBB flags" -#define TPM_PCR_GBB_HWID_NAME "GBB HWID" - static uint32_t safe_write(uint32_t index, const void *data, uint32_t length); static uint32_t read_space_firmware(struct vb2_context *ctx) From 3814116b42fe7b4f65ea8657b05be7622ba65d9d Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Tue, 14 Apr 2020 18:20:44 +0800 Subject: [PATCH 1068/1463] vboot/secdata: remove retries, readback, and CRC check Depthcharge trusts that our TPM driver is working reliably, and so should we. Also remove CRC check -- the value returned by antirollback_read_space_firmware() is dropped in vboot_logic.c verstage_main(), and vboot handles this check internally. BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: I5d3f3823fca8507fd58087bb0f7b78cfa49417ab Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/40359 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/security/vboot/secdata_tpm.c | 74 +++++++------------------------- 1 file changed, 15 insertions(+), 59 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index c052989ebe..672578a481 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -60,21 +60,10 @@ static uint32_t safe_write(uint32_t index, const void *data, uint32_t length); static uint32_t read_space_firmware(struct vb2_context *ctx) { - int attempts = 3; - - while (attempts--) { - RETURN_ON_FAILURE(tlcl_read(FIRMWARE_NV_INDEX, - ctx->secdata_firmware, - VB2_SECDATA_FIRMWARE_SIZE)); - - if (vb2api_secdata_firmware_check(ctx) == VB2_SUCCESS) - return TPM_SUCCESS; - - VBDEBUG("TPM: %s() - bad CRC\n", __func__); - } - - VBDEBUG("TPM: %s() - too many bad CRCs, giving up\n", __func__); - return TPM_E_CORRUPTED_STATE; + RETURN_ON_FAILURE(tlcl_read(FIRMWARE_NV_INDEX, + ctx->secdata_firmware, + VB2_SECDATA_FIRMWARE_SIZE)); + return TPM_SUCCESS; } uint32_t antirollback_read_space_kernel(struct vb2_context *ctx) @@ -100,39 +89,6 @@ static uint32_t read_space_rec_hash(uint8_t *data) return TPM_SUCCESS; } -static uint32_t write_secdata(uint32_t index, - const uint8_t *secdata, - uint32_t len) -{ - uint8_t sd[MAX(VB2_SECDATA_KERNEL_SIZE, VB2_SECDATA_FIRMWARE_SIZE)]; - uint32_t rv; - int attempts = 3; - - if (len > sizeof(sd)) { - VBDEBUG("TPM: %s() - data is too large\n", __func__); - return TPM_E_WRITE_FAILURE; - } - - while (attempts--) { - rv = safe_write(index, secdata, len); - /* Can't write, not gonna try again */ - if (rv != TPM_SUCCESS) - return rv; - - /* Read it back to be sure it got the right values. */ - rv = tlcl_read(index, sd, len); - if (rv == TPM_SUCCESS && memcmp(secdata, sd, len) == 0) - return rv; - - VBDEBUG("TPM: %s() failed. trying again\n", __func__); - /* Try writing it again. Maybe it was garbled on the way out. */ - } - - VBDEBUG("TPM: %s() - too many failures, giving up\n", __func__); - - return TPM_E_CORRUPTED_STATE; -} - /* * This is used to initialize the TPM space for recovery hash after defining * it. Since there is no data available to calculate hash at the point where TPM @@ -201,7 +157,7 @@ static uint32_t set_space(const char *name, uint32_t index, const void *data, if (rv != TPM_SUCCESS) return rv; - return write_secdata(index, data, length); + return safe_write(index, data, length); } static uint32_t set_firmware_space(const void *firmware_blob) @@ -300,8 +256,8 @@ static uint32_t set_rec_hash_space(const uint8_t *data) TPM_NV_PER_GLOBALLOCK | TPM_NV_PER_PPWRITE, REC_HASH_NV_SIZE)); - RETURN_ON_FAILURE(write_secdata(REC_HASH_NV_INDEX, data, - REC_HASH_NV_SIZE)); + RETURN_ON_FAILURE(safe_write(REC_HASH_NV_INDEX, data, + REC_HASH_NV_SIZE)); return TPM_SUCCESS; } @@ -347,17 +303,17 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) RETURN_ON_FAILURE(safe_define_space(KERNEL_NV_INDEX, TPM_NV_PER_PPWRITE, VB2_SECDATA_KERNEL_SIZE_V02)); - RETURN_ON_FAILURE(write_secdata(KERNEL_NV_INDEX, - ctx->secdata_kernel, - VB2_SECDATA_KERNEL_SIZE_V02)); + RETURN_ON_FAILURE(safe_write(KERNEL_NV_INDEX, + ctx->secdata_kernel, + VB2_SECDATA_KERNEL_SIZE_V02)); /* Define and write secdata_firmware space. */ RETURN_ON_FAILURE(safe_define_space(FIRMWARE_NV_INDEX, TPM_NV_PER_GLOBALLOCK | TPM_NV_PER_PPWRITE, VB2_SECDATA_FIRMWARE_SIZE)); - RETURN_ON_FAILURE(write_secdata(FIRMWARE_NV_INDEX, - ctx->secdata_firmware, + RETURN_ON_FAILURE(safe_write(FIRMWARE_NV_INDEX, + ctx->secdata_firmware, VB2_SECDATA_FIRMWARE_SIZE)); /* Define and set rec hash space, if available. */ @@ -449,8 +405,8 @@ uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) { if (CONFIG(CR50_IMMEDIATELY_COMMIT_FW_SECDATA)) tlcl_cr50_enable_nvcommits(); - return write_secdata(FIRMWARE_NV_INDEX, ctx->secdata_firmware, - VB2_SECDATA_FIRMWARE_SIZE); + return safe_write(FIRMWARE_NV_INDEX, ctx->secdata_firmware, + VB2_SECDATA_FIRMWARE_SIZE); } uint32_t antirollback_write_space_kernel(struct vb2_context *ctx) @@ -498,7 +454,7 @@ uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size) if (rv != TPM_SUCCESS) return rv; - return write_secdata(REC_HASH_NV_INDEX, data, size); + return safe_write(REC_HASH_NV_INDEX, data, size); } vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) From 5e1326a7d60f9a525dfe037eef3d44c87fd8d0ac Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 13 Apr 2020 23:39:44 -0700 Subject: [PATCH 1069/1463] Makefile: Simplify calculation of region base with default fmd files When using default fmd files, base of the fmap region is currently calculated based on the size and base of previous fmap regions. Since the existence of any fmap region is dependent on the selection of certain CONFIG_* parameters, these calculations get complicated. Every time base is calculated for a region, there need to be checks to see which of the previous regions really exist. As the regions in default fmd file are increased, these calculations and the conditional checks get even more complicated. This change introduces a Makefile variable FMAP_CURRENT_BASE which is updated every time a new region is allocated space. This allows using the same steps for determining the base of any fmap region irrespective of the state of previous regions. The way the code is organized it should be possible in the future to also add a macro to perform the same steps (in case that is possible). TEST=Verified that coreboot image generated remains unchanged for x86 and ARM boards using the default fmd files. Signed-off-by: Furquan Shaikh Change-Id: I2a109462928b6e8b7930bbcc1a1ba45fa85de6ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/40373 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- Makefile.inc | 74 +++++++++++++++++++++------------------------------- 1 file changed, 30 insertions(+), 44 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 39dd6ddf9b..8835ec3375 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -896,52 +896,42 @@ FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A # X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled -FMAP_CONSOLE_BASE := 0 + +FMAP_CURRENT_BASE := 0 + ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) +FMAP_CONSOLE_BASE := $(FMAP_CURRENT_BASE) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) -else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_SIZE := 0 +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)) +else FMAP_CONSOLE_ENTRY := -endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) +endif -# -# X86 RW_MRC_CACHE FMAP region -# -# position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ - $(FMAP_CONSOLE_SIZE)), 0x10000) +FMAP_MRC_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000) FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) -else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_MRC_CACHE_BASE := 0 -FMAP_MRC_CACHE_SIZE := 0 +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)) +else FMAP_MRC_CACHE_ENTRY := -endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +endif -# -# X86 SMMSTORE FMAP region -# -# position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_SMMSTORE),y) -FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ - $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000) +FMAP_SMMSTORE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000) FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE) FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE) -else # ifeq ($(CONFIG_SMMSTORE),y) -FMAP_SMMSTORE_BASE := 0 -FMAP_SMMSTORE_SIZE := 0 +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE)) +else FMAP_SMMSTORE_ENTRY := -endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +endif # # X86 FMAP region # # # position, size -FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \ - $(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE)) +FMAP_FMAP_BASE := $(FMAP_CURRENT_BASE) FMAP_FMAP_SIZE := 0x200 # @@ -950,7 +940,9 @@ FMAP_FMAP_SIZE := 0x200 # position and size of CBFS, relative to BIOS_BASE FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) + else # ifeq ($(CONFIG_ARCH_X86),y) + DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd # entire flash FMAP_ROM_ADDR := 0 @@ -963,47 +955,41 @@ FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) FMAP_FMAP_BASE := 0x20000 FMAP_FMAP_SIZE := 0x100 +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) + # # NON-X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) +FMAP_CONSOLE_BASE := $(FMAP_CURRENT_BASE) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) -else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := 0 -FMAP_CONSOLE_SIZE := 0 +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)) +else FMAP_CONSOLE_ENTRY := -endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) +endif # # NON-X86 RW_MRC_CACHE FMAP region # # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ - $(FMAP_CONSOLE_SIZE)), 0x10000) -else -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \ - $(FMAP_FMAP_SIZE)), 0x10000) -endif +FMAP_MRC_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000) FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) -else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_MRC_CACHE_BASE := 0 -FMAP_MRC_CACHE_SIZE := 0 +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)) +else FMAP_MRC_CACHE_ENTRY := -endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +endif # # NON-X86 COREBOOT default cbfs FMAP region # # position and size of CBFS, relative to BIOS_BASE -FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE) $(FMAP_CONSOLE_SIZE) \ - $(FMAP_MRC_CACHE_SIZE)) +FMAP_CBFS_BASE := $(FMAP_CURRENT_BASE) FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) + endif # ifeq ($(CONFIG_ARCH_X86),y) $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h From 8e66b23b350e59601c8e9201c121f484856487bb Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 13 Apr 2020 23:57:08 -0700 Subject: [PATCH 1070/1463] Makefile: Set FMAP size to 0x200 for non-x86 boards with default fmd This change updates FMAP_FMAP_SIZE for non-x86 boards using default fmd file to be 0x200 just like for x86 boards. Signed-off-by: Furquan Shaikh Change-Id: I3f58696b26fbb5363d67bec4056653da83485776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40374 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 8835ec3375..e315732ec9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -953,7 +953,7 @@ FMAP_BIOS_BASE := 0 FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) # position and size of flashmap, relative to BIOS_BASE FMAP_FMAP_BASE := 0x20000 -FMAP_FMAP_SIZE := 0x100 +FMAP_FMAP_SIZE := 0x200 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) From c42cf911ad787364aea359deb7c5a1c24f9bdd35 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 14 Apr 2020 00:14:44 -0700 Subject: [PATCH 1071/1463] util/cbfstool: Allow use of non-ASCII longopt CB:29744 ("util/cbfstool: Add optional argument ibb") added support for non-ASCII characters for long_options. However, there is a check later on which errors out since this character is not one of the commands[i].optstring. This change adds a function valid_opt() which does the following things: 1. Checks if the returned optchar is among the list of optstring supported by the command. 2. Checks if the returned optchar is a valid non-ASCII option. Currently, we do not maintain a list of non-ASCII options supported by each command. So, this function returns true if the optchar returned by getopt_long falls within the allowed range. Signed-off-by: Furquan Shaikh Change-Id: I27a4f9af9850e4c892573202904fa9e5fbb64df6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40375 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Aaron Durbin --- util/cbfstool/cbfstool.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 65c5e08871..f15c65b6e7 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1295,7 +1295,9 @@ static const struct command commands[] = { enum { /* begin after ASCII characters */ - LONGOPT_IBB = 256, + LONGOPT_START = 256, + LONGOPT_IBB = LONGOPT_START, + LONGOPT_END, }; static struct option long_options[] = { @@ -1491,6 +1493,23 @@ static void usage(char *name) ); } +static bool valid_opt(size_t i, int c) +{ + /* Check if it is one of the optstrings supported by the command. */ + if (strchr(commands[i].optstring, c)) + return true; + + /* + * Check if it is one of the non-ASCII characters. Currently, the + * non-ASCII characters are only checked against the valid list + * irrespective of the command. + */ + if (c >= LONGOPT_START && c < LONGOPT_END) + return true; + + return false; +} + int main(int argc, char **argv) { size_t i; @@ -1525,9 +1544,8 @@ int main(int argc, char **argv) } /* Filter out illegal long options */ - if (strchr(commands[i].optstring, c) == NULL) { - /* TODO maybe print actual long option instead */ - ERROR("%s: invalid option -- '%c'\n", + if (!valid_opt(i, c)) { + ERROR("%s: invalid option -- '%d'\n", argv[0], c); c = '?'; } From da4272454981be0eb225bc5786935891181cf0f8 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Fri, 13 Mar 2020 12:13:54 +0530 Subject: [PATCH 1072/1463] mb/intel/jasperlake_rvp: Add SD Card gpio config for JSLRVP Configure write protect and card detect SD Card GPIO for JSLRVP as per schematics. BUG=None BRANCH=None TEST=Build, boot JSLRVP and verified SD Card detection. Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39492 Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 3 +++ .../intel/jasperlake_rvp/variants/jslrvp/gpio.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index f5915046ca..b632b7804c 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -124,6 +124,9 @@ chip soc/intel/jasperlake # Enable S0ix register "s0ix_enable" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "VGPIO_39" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[1] = { diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 45ba5efd5b..726417a8cc 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -19,6 +19,15 @@ static const struct pad_config gpio_table[] = { /* I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* SD_CD# */ + PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), + + /* SD_WP */ + PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), + + /* virtual GPIO for SD card detect */ + PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP), + /* I2S1_SCLK */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), From 8920ee0dcccea100428495220aa53e248f5a210d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 4 Jan 2020 15:30:55 +0200 Subject: [PATCH 1073/1463] drivers/elog,pc80: Move cmos_post_log() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do this to remove elog header dependency from pc80/ and remove some preprocessor guards. Change-Id: I98044a28c29a2b1756fb25fb593f505e914a71c0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38189 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/elog/elog.c | 29 ++++++++++++++++++++++++----- src/drivers/pc80/rtc/post.c | 27 +++++++++++---------------- src/include/console/console.h | 1 + src/include/pc80/mc146818rtc.h | 3 --- 4 files changed, 36 insertions(+), 24 deletions(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index c353d59e9f..ca604dde3a 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -748,16 +748,35 @@ static bool elog_do_add_boot_count(void) #endif } +/* Check and log POST codes from previous boot */ +static void log_last_boot_post(void) +{ +#if CONFIG(ARCH_X86) + u8 code; + u32 extra; + + if (!CONFIG(CMOS_POST)) + return; + + if (cmos_post_previous_boot(&code, &extra) == 0) + return; + + printk(BIOS_WARNING, "POST: Unexpected post code/extra " + "in previous boot: 0x%02x/0x%04x\n", code, extra); + + elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); + /* Always zero with !CMOS_POST_EXTRA. */ + if (extra) + elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); +#endif +} + static void elog_add_boot_count(void) { if (elog_do_add_boot_count()) { elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); -#if CONFIG(ARCH_X86) - /* Check and log POST codes from previous boot */ - if (CONFIG(CMOS_POST)) - cmos_post_log(); -#endif + log_last_boot_post(); } } diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 1ac36305a0..e14367424e 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */ #include -#include #include #include #include @@ -10,45 +9,41 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -void cmos_post_log(void) +int cmos_post_previous_boot(u8 *code, u32 *extra) { - u8 code = 0; - u32 extra = 0; + *code = 0; + *extra = 0; spin_lock(&cmos_post_lock); /* Get post code from other bank */ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: - code = cmos_read(CMOS_POST_BANK_1_OFFSET); + *code = cmos_read(CMOS_POST_BANK_1_OFFSET); if (CONFIG(CMOS_POST_EXTRA)) - extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: - code = cmos_read(CMOS_POST_BANK_0_OFFSET); + *code = cmos_read(CMOS_POST_BANK_0_OFFSET); if (CONFIG(CMOS_POST_EXTRA)) - extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; } spin_unlock(&cmos_post_lock); /* Check last post code in previous boot against normal list */ - switch (code) { + switch (*code) { case POST_OS_BOOT: case POST_OS_RESUME: case POST_ENTER_ELF_BOOT: case 0: break; default: - printk(BIOS_WARNING, "POST: Unexpected post code " - "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) - elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); - if (CONFIG(CMOS_POST_EXTRA) && extra) - elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); -#endif + return -1; } + + return 0; } void cmos_post_init(void) diff --git a/src/include/console/console.h b/src/include/console/console.h index c68caf0e00..f9e9fe24c3 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -19,6 +19,7 @@ void post_code(u8 value); void arch_post_code(u8 value); void cmos_post_code(u8 value); +int cmos_post_previous_boot(u8 *code, u32 *extra); #if CONFIG(CMOS_POST_EXTRA) struct device; void post_log_path(const struct device *dev); diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 20e963909b..edaeb1e4b2 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -210,9 +210,6 @@ void cmos_set_checksum(int range_start, int range_end, int cks_loc); #define CMOS_POST_EXTRA_DEV_PATH 0x01 -void cmos_post_log(void); -#else -static inline void cmos_post_log(void) {} #endif /* CONFIG_CMOS_POST */ #endif /* CONFIG_ARCH_X86 */ From f3dbf4ce6b38b9ebc8e0e537b49ccf1aed456435 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 4 Jan 2020 15:55:16 +0200 Subject: [PATCH 1074/1463] drivers/pc80/rtc: Clean up post_log_path() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I605d39d907e083e73af4c72607216384e7ce166a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38190 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/pc80/rtc/post.c | 26 ++++++++++---------------- src/include/console/console.h | 25 +++++++++++++++++-------- 2 files changed, 27 insertions(+), 24 deletions(-) diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index e14367424e..5bee5be812 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -86,8 +86,11 @@ void cmos_post_code(u8 value) spin_unlock(&cmos_post_lock); } -static void __unused cmos_post_extra(u32 value) +void cmos_post_extra(u32 value) { + if (!CONFIG(CMOS_POST_EXTRA)) + return; + spin_lock(&cmos_post_lock); switch (cmos_read(CMOS_POST_BANK_OFFSET)) { @@ -102,20 +105,11 @@ static void __unused cmos_post_extra(u32 value) spin_unlock(&cmos_post_lock); } -#if CONFIG(CMOS_POST_EXTRA) -void post_log_path(const struct device *dev) +void cmos_post_path(const struct device *dev) { - if (dev) { - /* Encode path into lower 3 bytes */ - u32 path = dev_path_encode(dev); - /* Upper byte contains the log type */ - path |= CMOS_POST_EXTRA_DEV_PATH << 24; - cmos_post_extra(path); - } + /* Encode path into lower 3 bytes */ + u32 path = dev_path_encode(dev); + /* Upper byte contains the log type */ + path |= CMOS_POST_EXTRA_DEV_PATH << 24; + cmos_post_extra(path); } - -void post_log_clear(void) -{ - cmos_post_extra(0); -} -#endif /* CONFIG_CMOS_POST_EXTRA */ diff --git a/src/include/console/console.h b/src/include/console/console.h index f9e9fe24c3..95c0e7fe1a 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -16,18 +16,27 @@ #include +struct device; + void post_code(u8 value); void arch_post_code(u8 value); void cmos_post_code(u8 value); +void cmos_post_extra(u32 value); +void cmos_post_path(const struct device *dev); int cmos_post_previous_boot(u8 *code, u32 *extra); -#if CONFIG(CMOS_POST_EXTRA) -struct device; -void post_log_path(const struct device *dev); -void post_log_clear(void); -#else -#define post_log_path(x) do {} while (0) -#define post_log_clear() do {} while (0) -#endif + +static inline void post_log_path(const struct device *dev) +{ + if (CONFIG(CMOS_POST) && dev) + cmos_post_path(dev); +} + +static inline void post_log_clear(void) +{ + if (CONFIG(CMOS_POST)) + cmos_post_extra(0); +} + /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __noreturn die(const char *fmt, ...); From 101f45459629c545c4a491fcc56b9c8ddd3d7cc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 4 Jan 2020 16:15:50 +0200 Subject: [PATCH 1075/1463] drivers/pc80/rtc: Drop CMOS_POST_EXTRA option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- configs/config.google_meep_cros | 1 - configs/config.google_reef_cros | 1 - src/console/Kconfig | 8 -------- src/drivers/elog/elog.c | 1 - src/drivers/pc80/rtc/post.c | 15 ++++----------- 5 files changed, 4 insertions(+), 22 deletions(-) diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index f87b02b5e9..9911614f16 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -14,7 +14,6 @@ CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y # Event Logging CONFIG_CMOS_POST=y -CONFIG_CMOS_POST_EXTRA=y CONFIG_CMOS_POST_OFFSET=0x70 CONFIG_COLLECT_TIMESTAMPS=y CONFIG_ELOG=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 9bbb3b3f59..6dcda442db 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -10,5 +10,4 @@ CONFIG_SPI_FLASH_SMM=y # CONFIG_CONSOLE_SERIAL is not set CONFIG_CMOS_POST=y CONFIG_CMOS_POST_OFFSET=0x70 -CONFIG_CMOS_POST_EXTRA=y CONFIG_PAYLOAD_NONE=y diff --git a/src/console/Kconfig b/src/console/Kconfig index b893698a20..7c6e9bc5e0 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -392,14 +392,6 @@ config CMOS_POST_OFFSET If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table. -config CMOS_POST_EXTRA - bool "Store extra logging info into CMOS" - depends on CMOS_POST - default n - help - This will enable extra logging of work that happens between post - codes into CMOS for debug. This uses an additional 8 bytes of CMOS. - config CONSOLE_POST bool "Show POST codes on the debug console" depends on !NO_POST diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index ca604dde3a..1d4b1351b5 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -765,7 +765,6 @@ static void log_last_boot_post(void) "in previous boot: 0x%02x/0x%04x\n", code, extra); elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); - /* Always zero with !CMOS_POST_EXTRA. */ if (extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); #endif diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 5bee5be812..41a664e321 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -20,13 +20,11 @@ int cmos_post_previous_boot(u8 *code, u32 *extra) switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: *code = cmos_read(CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: *code = cmos_read(CMOS_POST_BANK_0_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; } @@ -61,10 +59,8 @@ void cmos_post_init(void) /* Initialize to zero */ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) { - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); - } + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); } cmos_write(magic, CMOS_POST_BANK_OFFSET); @@ -88,9 +84,6 @@ void cmos_post_code(u8 value) void cmos_post_extra(u32 value) { - if (!CONFIG(CMOS_POST_EXTRA)) - return; - spin_lock(&cmos_post_lock); switch (cmos_read(CMOS_POST_BANK_OFFSET)) { From 229d5b2f46af0c3c1472311c715c2191dfe7cbbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 4 Jan 2020 16:15:50 +0200 Subject: [PATCH 1076/1463] drivers/pc80/rtc: Move CMOS_POST_BANK_x definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I8b56df6de7529772b0f1a59002f92c4f31486bf0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38196 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/pc80/rtc/post.c | 28 ++++++++++++++++++++++++++++ src/include/pc80/mc146818rtc.h | 31 ------------------------------- 2 files changed, 28 insertions(+), 31 deletions(-) diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 41a664e321..f993b96b2c 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -7,6 +7,34 @@ #include #include +#if CONFIG(USE_OPTION_TABLE) +# include "option_table.h" +# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) +#else +# if (CONFIG_CMOS_POST_OFFSET != 0) +# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET +# else +# error "Must configure CONFIG_CMOS_POST_OFFSET" +# endif +#endif + +/* + * 0 = Bank Select Magic + * 1 = Bank 0 POST + * 2 = Bank 1 POST + * 3-6 = BANK 0 Extra log + * 7-10 = BANK 1 Extra log + */ +#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET) +#define CMOS_POST_BANK_0_MAGIC 0x80 +#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1) +#define CMOS_POST_BANK_0_EXTRA (CMOS_POST_OFFSET + 3) +#define CMOS_POST_BANK_1_MAGIC 0x81 +#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) +#define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7) + +#define CMOS_POST_EXTRA_DEV_PATH 0x01 + DECLARE_SPIN_LOCK(cmos_post_lock) int cmos_post_previous_boot(u8 *code, u32 *extra) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index edaeb1e4b2..353a09b416 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -181,37 +181,6 @@ int cmos_lb_cks_valid(void); int cmos_checksum_valid(int range_start, int range_end, int cks_loc); void cmos_set_checksum(int range_start, int range_end, int cks_loc); -#if CONFIG(CMOS_POST) -#if CONFIG(USE_OPTION_TABLE) -# include "option_table.h" -# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) -#else -# if (CONFIG_CMOS_POST_OFFSET != 0) -# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET -# else -# error "Must configure CONFIG_CMOS_POST_OFFSET" -# endif -#endif - -/* - * 0 = Bank Select Magic - * 1 = Bank 0 POST - * 2 = Bank 1 POST - * 3-6 = BANK 0 Extra log - * 7-10 = BANK 1 Extra log - */ -#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET) -#define CMOS_POST_BANK_0_MAGIC 0x80 -#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1) -#define CMOS_POST_BANK_0_EXTRA (CMOS_POST_OFFSET + 3) -#define CMOS_POST_BANK_1_MAGIC 0x81 -#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) -#define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7) - -#define CMOS_POST_EXTRA_DEV_PATH 0x01 - -#endif /* CONFIG_CMOS_POST */ - #endif /* CONFIG_ARCH_X86 */ void cmos_post_init(void); From ce39ba97bc1906e7fbfec09312fcfec2919cf03e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 4 Jan 2020 16:15:50 +0200 Subject: [PATCH 1077/1463] drivers/pc80/rtc: Reorganize prototypes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38199 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/arch/x86/cpu.c | 1 + src/arch/x86/post.c | 1 + src/device/device.c | 1 + src/drivers/elog/elog.c | 4 +--- src/drivers/pc80/rtc/post.c | 1 + src/include/console/console.h | 26 +++----------------------- src/include/pc80/mc146818rtc.h | 1 - src/include/post.h | 28 ++++++++++++++++++++++++++++ src/lib/bootblock.c | 2 +- src/soc/intel/xeon_sp/skx/chip.c | 1 + 10 files changed, 38 insertions(+), 28 deletions(-) create mode 100644 src/include/post.h diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 8f8fdc1fd0..1ee8fb32c3 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include diff --git a/src/arch/x86/post.c b/src/arch/x86/post.c index 0aaf9b7190..ec185c791e 100644 --- a/src/arch/x86/post.c +++ b/src/arch/x86/post.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include diff --git a/src/device/device.c b/src/device/device.c index cc1b37df1b..a5d223b1c0 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 1d4b1351b5..ab86f387cc 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -7,14 +7,12 @@ #include #include #include -#if CONFIG(ARCH_X86) -#include -#endif #include #include #include #include #include +#include #include #include #include diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index f993b96b2c..842deb71f6 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -2,6 +2,7 @@ /* This file is part of the coreboot project. */ #include +#include #include #include #include diff --git a/src/include/console/console.h b/src/include/console/console.h index 95c0e7fe1a..fdc48da73f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -7,6 +7,7 @@ #include #include #include +#include /* console.h is supposed to provide the log levels defined in here: */ #include @@ -14,31 +15,10 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) -#include - -struct device; - void post_code(u8 value); -void arch_post_code(u8 value); -void cmos_post_code(u8 value); -void cmos_post_extra(u32 value); -void cmos_post_path(const struct device *dev); -int cmos_post_previous_boot(u8 *code, u32 *extra); - -static inline void post_log_path(const struct device *dev) -{ - if (CONFIG(CMOS_POST) && dev) - cmos_post_path(dev); -} - -static inline void post_log_clear(void) -{ - if (CONFIG(CMOS_POST)) - cmos_post_extra(0); -} - -/* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); +void arch_post_code(u8 value); + void __noreturn die(const char *fmt, ...); #define die_with_post_code(value, fmt, ...) \ do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 353a09b416..c9e054b048 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -183,6 +183,5 @@ void cmos_set_checksum(int range_start, int range_end, int cks_loc); #endif /* CONFIG_ARCH_X86 */ -void cmos_post_init(void); #endif /* PC80_MC146818RTC_H */ diff --git a/src/include/post.h b/src/include/post.h new file mode 100644 index 0000000000..5c1e816ea7 --- /dev/null +++ b/src/include/post.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __POST_H__ +#define __POST_H__ + +#include +#include + +void cmos_post_init(void); +void cmos_post_code(u8 value); +void cmos_post_extra(u32 value); +void cmos_post_path(const struct device *dev); +int cmos_post_previous_boot(u8 *code, u32 *extra); + +static inline void post_log_path(const struct device *dev) +{ + if (CONFIG(CMOS_POST) && dev) + cmos_post_path(dev); +} + +static inline void post_log_clear(void) +{ + if (CONFIG(CMOS_POST)) + cmos_post_extra(0); +} + +#endif diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 565d619a3e..b3d48604c3 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index be452a05b6..9a9c45555c 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include From 38e386f2d0255fdc424b0efe73585ea4ab9e8b1b Mon Sep 17 00:00:00 2001 From: Marco Chen Date: Thu, 16 Apr 2020 22:37:26 +0800 Subject: [PATCH 1078/1463] mb/google/dedede: remove samsung-K4U6E3S4AA-MGCL.spd.hex The samsung-K4U6E3S4AA-MGCL.spd.hex is not used and planed by anyone yet. On the other hand, the spd content is not correct based on JSL spec as well. BUG=b:153426401 TEST=build waddledoo and waddledee successfully. Change-Id: If71e3ef2e3385378633549bf8709a1cd6ecc0dd3 Signed-off-by: Marco Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40433 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- .../spd/samsung-K4U6E3S4AA-MGCL.spd.hex | 32 ------------------- .../dedede/variants/waddledee/Makefile.inc | 1 - .../dedede/variants/waddledoo/Makefile.inc | 1 - 3 files changed, 34 deletions(-) delete mode 100644 src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex diff --git a/src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex b/src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex deleted file mode 100644 index e1f27fba56..0000000000 --- a/src/mainboard/google/dedede/spd/samsung-K4U6E3S4AA-MGCL.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 -48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index b1aba0eeff..fb9b4f45fc 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -7,4 +7,3 @@ SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 SPD_SOURCES += empty #0b0001 -SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010 diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 3e06d73658..71042c0340 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -7,4 +7,3 @@ SPD_SOURCES = empty #0b0000 SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 -SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010 From 85ecdb1471dd695997166f447f786ed500d091b9 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Wed, 15 Apr 2020 20:54:14 +0800 Subject: [PATCH 1079/1463] mmio: Fix failure in bit field macro when accessing >30 bits For bit fields with 31 bits (e.g: DEFINE_BITFIELD(MYREG, 30, 0) ), the calculation of mask value will go overflow: "error: integer overflow in expression '-2147483648 - 1' of type 'int' results in '2147483647'". And for bit fields with 32 bits (e.g: DEFINE_BITFIELD(MYREG, 31, 0) ), the error will be: "error: left shift count >= width of type [-Werror=shift-count-overflow]" To fix these issues, the bit field macros should always use unsigned integers, and use 64bit integer when creating mask value. Change-Id: Ie3cddf9df60b83de4e21243bfde6b79729fb06ef Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/40404 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/include/device/mmio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index b4f2ab639f..a725a62953 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -131,10 +131,10 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, #define DEFINE_BIT(name, bit) DEFINE_BITFIELD(name, bit, bit) #define _BF_MASK(name, value) \ - (((1 << name##_BITFIELD_SIZE) - 1) << name##_BITFIELD_SHIFT) + ((u32)((1ULL << name##_BITFIELD_SIZE) - 1) << name##_BITFIELD_SHIFT) #define _BF_VALUE(name, value) \ - ((value) << name##_BITFIELD_SHIFT) + (((u32)(value) << name##_BITFIELD_SHIFT) & _BF_MASK(name, 0)) #define _BF_APPLY1(op, name, value, ...) (op(name, value)) #define _BF_APPLY2(op, name, value, ...) ((op(name, value)) | \ From ab0da17856bc53334f17327e147b941f8cd479af Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 15 Apr 2020 00:15:22 -0700 Subject: [PATCH 1080/1463] mb/google/volteer: Update devicetree based on EDS Update device enable/disable based on PCH EDS#576591 vol1 rev1.2 BRANCH=none BUG=b:154037185 TEST= boot up OS in volteer and check and check lspci Unsupported IP should be visable from lspci result Signed-off-by: Wonkyu Kim Change-Id: I61a328da1014ab7584c3ec789971a106c7a0a403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40394 Reviewed-by: Nick Vaccaro Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- .../volteer/variants/baseboard/devicetree.cb | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ab911d2173..2937bbd516 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -227,24 +227,14 @@ chip soc/intel/tigerlake device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) - device pci 10.0 on end # I2C6 0xA0D8 - device pci 10.1 off end # I2C7 0xA0D9 device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 - device pci 11.0 off end # UART3 0xA0DA - device pci 11.1 off end # UART4 0xA0DB - device pci 11.2 off end # UART5 0xA0DC - device pci 11.3 off end # UART6 0xA0DD - device pci 12.0 off end # SensorHUB 0xA0FC device pci 12.6 off end # GSPI2 0x34FB device pci 13.0 off end # GSPI3 0xA0FD - device pci 13.1 off end # GSPI4 0xA0FE - device pci 13.2 off end # GSPI5 0xA0DE - device pci 13.3 off end # GSPI6 0xA0DF device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 off end # USB3.1 xDCI 0xA0EE @@ -337,10 +327,6 @@ chip soc/intel/tigerlake device pci 1d.1 off end # RP10 0xA0B1 device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 - device pci 1d.4 off end # RP13 0xA0B4 - device pci 1d.5 off end # RP14 0xA0B5 - device pci 1d.6 off end # RP15 0xA0B6 - device pci 1d.7 off end # RP16 0xA0B7 device pci 1e.0 on end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9 From 82e0a81cf1f999c4d4627ff31c594fd4375c6edc Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 13 Apr 2020 13:26:05 -0700 Subject: [PATCH 1081/1463] soc/intel/tigerlake: Merge the recent change from other platforms Merge the recent change from other platform(ICL/JSL). - Update SKpMpInit setting - Update APIs for getting dev info - Update IGD related setting - Update debug interface setting BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Wonkyu Kim Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/40349 Reviewed-by: Caveh Jalali Reviewed-by: Srinidhi N Kaushik Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params.c | 18 ++++++--- src/soc/intel/tigerlake/romstage/fsp_params.c | 38 +++++++++++-------- 2 files changed, 35 insertions(+), 21 deletions(-) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 78cfb9f004..5acad201c6 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -86,14 +87,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - + /* Check if IGD is present and fill Graphics init param accordingly */ dev = pcidev_path_on_root(SA_DEVFN_IGD); if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0; + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000; @@ -144,7 +152,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PcieRpAdvancedErrorReporting[i]; } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -159,7 +167,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; /* SATA */ - dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + dev = pcidev_path_on_root(PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -173,7 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* LAN */ - dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 993320054a..6056b4b0c1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -20,8 +20,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t mask = 0; const struct device *dev; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; @@ -60,22 +69,19 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - /* UART Debug Log */ + /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : - DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; - m_cfg->PcdIsaSerialUartBase = 0x0; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; - /* - * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. - */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) - m_cfg->InternalGfx = 0; - else - m_cfg->InternalGfx = 0x1; + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } + + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); From 4af269171cd2ea2614fdbe5688ffc4214f4b0b03 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sun, 30 Jun 2019 16:32:05 +0300 Subject: [PATCH 1082/1463] mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder lines to make it more similar to buildOpts.c of Lenovo G505S. This improves diff results, which is convenient for debugging. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33913 Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/am1i-a/buildOpts.c | 75 ++++++++++++++------------- 1 file changed, 39 insertions(+), 36 deletions(-) diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 46e2a1d87a..5889592fdb 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -16,7 +16,6 @@ #include #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE #define INSTALL_G34_SOCKET_SUPPORT FALSE @@ -30,7 +29,7 @@ #define INSTALL_FT1_SOCKET_SUPPORT FALSE #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - +#define INSTALL_FT3_SOCKET_SUPPORT TRUE #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE @@ -54,7 +53,7 @@ #define BLDOPT_REMOVE_SRAT FALSE //TRUE #define BLDOPT_REMOVE_SLIT FALSE //TRUE #define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE @@ -74,28 +73,14 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -126,34 +111,52 @@ #define BLDCFG_SCRUB_L3_RATE 0 #define BLDCFG_SCRUB_IC_RATE 0 #define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD FALSE #define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) #endif -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT + +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define OPTION_GFX_INIT_SVIEW FALSE + #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + /* Process the options... * This file include MUST occur AFTER the user option selection settings */ From 116cd21837636a2c151a3c97c805b65eff67e848 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sun, 30 Jun 2019 16:42:21 +0300 Subject: [PATCH 1083/1463] mb/asus/am1i-a/buildOpts.c: Use fully-qualified paths on includes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes it easier to know which files are being included. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33914 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Angel Pons --- src/mainboard/asus/am1i-a/buildOpts.c | 31 ++++++++++++++------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 5889592fdb..28e502e2cd 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -14,7 +14,22 @@ */ #include -#include + +#include + +/* Include the files that instantiate the configuration definitions. */ +#include +#include +#include +#include +#include +#include +#include +#include +/* AGESA nonesense: the next three headers depend on heapManager.h */ +#include +#include +#include #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE @@ -219,20 +234,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} From c84babb8e0ca6d6e2103669e3488e740e3ffdcc4 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sun, 30 Jun 2019 16:51:10 +0300 Subject: [PATCH 1084/1463] mb/asus/am1i-a/buildOpts.c: return the removed comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These comments exist in other buildOpts.c files, but not in this one. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33915 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/asus/am1i-a/buildOpts.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 28e502e2cd..40950f60be 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -31,8 +31,10 @@ #include #include +/* Select the CPU family. */ #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -152,6 +154,10 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +/* + * Specify the default values for the VRM controlling the VDDNB plane. + * If not specified, the values used for the core VRM will be applied + */ #define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 #define BLDCFG_VRM_SLEW_RATE 10000 @@ -331,4 +337,5 @@ GPIO_CONTROL imba180_gpio[] = { #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) +/* AGESA nonsense: this header depends on the definitions above */ #include From 8af30ab576e8f89f10132ef1ab90afb14d340431 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sun, 30 Jun 2019 16:53:50 +0300 Subject: [PATCH 1085/1463] mb/asus/am1i-a/buildOpts.c: guard UMA-related options with CONFIG_GFXUMA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Looks like the guard was dropped by mistake. Signed-off-by: Mike Banon Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33916 Reviewed-by: Michał Żygowski Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/am1i-a/buildOpts.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 40950f60be..71b1815f2a 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -165,9 +165,11 @@ #define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 #define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define OPTION_GFX_INIT_SVIEW FALSE +#endif #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed From 816c5cb9fc431a46368e7b8f3596d92653a831e0 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sun, 30 Jun 2019 17:06:47 +0300 Subject: [PATCH 1086/1463] mb/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one. Signed-off-by: Mike Banon Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/33919 Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/mainboard/asus/am1i-a/buildOpts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 71b1815f2a..71fedaa726 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -99,7 +99,7 @@ #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE From da38715ec3cef00ffa893a2adbee30674bf5f9a4 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 17 Apr 2020 10:16:52 -0600 Subject: [PATCH 1087/1463] mb/google/dedede: Read DRAM population strap Configure DRAM population strap GPIO according to the schematics. Configure an internal pull-up to support the boards in which the strap is not populated. Read the strap and pass that information to FSP for memory initialization. BUG=b:152275658, b:154301008 TEST=Build and boot the mainboard. Ensure that the strap information is read as expected and passed to FSP. Change-Id: I69583f35ffc219bae9ce06bd4ba9898ed0d4d21d Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/39812 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/romstage.c | 6 ++++-- src/mainboard/google/dedede/variants/baseboard/gpio.c | 5 ++++- .../dedede/variants/baseboard/include/baseboard/gpio.h | 3 +++ 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index f95e7aacc3..2efaaf17e7 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,8 +6,10 @@ */ #include +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *memupd) { @@ -16,7 +18,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) .read_type = READ_SPD_CBFS, .spd_spec.spd_index = variant_memory_sku(), }; - /* TODO: Read the resistor strap to get number of memory segments. */ - bool half_populated = 0; + bool half_populated = !gpio_get(GPIO_MEM_CH_SEL); + memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index d12d2c464d..a4ce97d8a5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -348,7 +348,7 @@ static const struct pad_config gpio_table[] = { /* S0 : RAM_STRAP_4 */ - PAD_NC(GPP_S0, NONE), + PAD_CFG_GPI(GPP_S0, UP_5K, DEEP), /* S1 : RSVD_STRAP */ PAD_NC(GPP_S1, NONE), /* S2 : DMIC1_CLK */ @@ -416,6 +416,9 @@ static const struct pad_config early_gpio_table[] = { /* H19 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_H19, 0, DEEP), + + /* S0 : RAM_STRAP_4 */ + PAD_CFG_GPI(GPP_S0, UP_5K, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index dfb2cd1bd7..98e4b277f7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -26,4 +26,7 @@ #define GPIO_MEM_CONFIG_2 GPP_C4 #define GPIO_MEM_CONFIG_3 GPP_C5 +/* Memory channel select strap - 0: half-populated, 1: fully-populated */ +#define GPIO_MEM_CH_SEL GPP_S0 + #endif /* __BASEBOARD_GPIO_H__ */ From c423293d200cfa8ff7162a07fcd365a58347ab7e Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Fri, 17 Apr 2020 16:45:08 +0800 Subject: [PATCH 1088/1463] mb/google/dedede: Disable dynamic clock gating for cr50's GPIO Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:154178408 b:154293730 BRANCH=None TEST=build waddledoo successful and Linux has no TPM IRQ timeout error. Signed-off-by: Ian Feng Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Karthik Ramasubramanian --- .../google/dedede/variants/baseboard/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f030b20cec..cfe221f994 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -118,6 +118,14 @@ chip soc/intel/jasperlake # Select eDP for port A register "DdiPortAConfig" = "1" + # Disable PM to allow for shorter irq pulses + register "gpio_override_pm" = "1" + register "gpio_pm[0]" = "0" + register "gpio_pm[1]" = "0" + register "gpio_pm[2]" = "0" + register "gpio_pm[3]" = "0" + register "gpio_pm[4]" = "0" + # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" From 6f48df1debfefe378f5b59dbbbe65367118f7a80 Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Tue, 7 Apr 2020 15:49:55 -0700 Subject: [PATCH 1089/1463] soc/intel/common: Add _DSM methods for LPIT table This patch adds _DSM Method in LPIT table for entering and exiting S0ix. This method get injected into DSDT table and called from kernel. LPIT table is hardcoded in this patch but the proper way to implement is to use inject_dsdt to make the _DSM methods available for soc's to implement. Calling the LPIT table from mainboard here so that with the current implementation the platforms which do not have lpit support throw compilation error. BUG=b:148892882 BRANCH=none TEST="BUILD" Signed-off-by: Venkata Krishna Nimmagadda Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40259 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Venkata Krishna Nimmagadda --- src/soc/intel/common/acpi/lpit.asl | 104 +++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 src/soc/intel/common/acpi/lpit.asl diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl new file mode 100644 index 0000000000..4f8bd5ece9 --- /dev/null +++ b/src/soc/intel/common/acpi/lpit.asl @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0 +#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 + +#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2 +#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 +#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4 +#define LPID_DSM_ARG2_S0IX_ENTRY 5 +#define LPID_DSM_ARG2_S0IX_EXIT 6 + +External(\_SB.MS0X, MethodObj) +External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) +External(\_SB.PCI0.EGPM, MethodObj) +External(\_SB.PCI0.RGPM, MethodObj) + +Scope(\_SB) +{ + Device(LPID) + { + Name(_ADR, 0x00000000) + Name(_CID, EISAID("PNP0D80")) + Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) + Method(_DSM, 4) + { + If(Arg0 == ^UUID) { + /* + * Enum functions + */ + If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + Return(Buffer(One) {0x60}) + } + /* + * Function 1 - Get Device Constraints + */ + If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + Return(Package(5) {0, Ones, Ones, Ones, Ones}) + } + /* + * Function 2 - Get Crash Dump Device + */ + If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + Return(Buffer(One) {0x0}) + } + /* + * Function 3 - Display Off Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + } + /* + * Function 4 - Display On Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + } + /* + * Function 5 - Low Power S0 Entry Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } + } + /* + * Function 6 - Low Power S0 Exit Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } + } + } + + Return(Buffer(One) {0x00}) + } // Method(_DSM) + } // Device (LPID) +} // End Scope(\_SB) From 4a8cd72c054381125fd2ca14cf47d1c9be79254f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 18 Apr 2020 22:26:39 +0200 Subject: [PATCH 1090/1463] soc/amd: replace remaining license headers with SPDX ones Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../common/block/include/amdblocks/acpimmio.h | 16 ++-------- .../block/include/amdblocks/acpimmio_map.h | 16 ++-------- src/soc/amd/picasso/Kconfig | 15 ++-------- src/soc/amd/picasso/Makefile.inc | 29 ++----------------- src/soc/amd/picasso/acpi/globalnvs.asl | 16 ++-------- src/soc/amd/picasso/include/soc/acpi.h | 16 ++-------- src/soc/amd/picasso/include/soc/nvs.h | 16 ++-------- src/soc/amd/picasso/include/soc/smi.h | 16 ++-------- src/soc/amd/picasso/smi.c | 16 ++-------- src/soc/amd/picasso/smi_util.c | 16 ++-------- src/soc/amd/picasso/smihandler.c | 16 ++-------- src/soc/amd/picasso/tsc_freq.c | 16 ++-------- src/soc/amd/stoneyridge/Kconfig | 15 ++-------- src/soc/amd/stoneyridge/Makefile.inc | 29 ++----------------- src/soc/amd/stoneyridge/acpi/globalnvs.asl | 16 ++-------- src/soc/amd/stoneyridge/include/soc/acpi.h | 16 ++-------- src/soc/amd/stoneyridge/include/soc/nvs.h | 16 ++-------- src/soc/amd/stoneyridge/include/soc/smi.h | 16 ++-------- src/soc/amd/stoneyridge/monotonic_timer.c | 15 ++-------- src/soc/amd/stoneyridge/smi.c | 16 ++-------- src/soc/amd/stoneyridge/smi_util.c | 16 ++-------- src/soc/amd/stoneyridge/smihandler.c | 16 ++-------- src/soc/amd/stoneyridge/tsc_freq.c | 16 ++-------- 23 files changed, 48 insertions(+), 343 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index a2ac5e31fc..2e4064055f 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 3e28c33357..6188c42aea 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_ACPIMMIO_MAP_H__ #define __AMDBLOCKS_ACPIMMIO_MAP_H__ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4759f01ecc..c7e65fa57a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SOC_AMD_PICASSO bool diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b79f6274b3..d31e518edc 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -1,29 +1,6 @@ -#***************************************************************************** -# -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#***************************************************************************** +# SPDX-License-Identifier: BSD-3-Clause +# This file is part of the coreboot project. + ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/amd/mtrr/ diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 6192922ccd..672514bb0c 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * NOTE: The layout of the GNVS structure below must match the layout in diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index c3c0933c61..7d159c0b65 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef __SOC_PICASSO_ACPI_H__ #define __SOC_PICASSO_ACPI_H__ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index d0ed799b6a..396e8a4079 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * NOTE: The layout of the global_nvs_t structure below must match the layout diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index fb8061ca16..4c1e51dcd3 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ #define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index 273c55b635..1411e2ab58 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * Utilities for SMM setup diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 9e0c85a129..6f38ed5ec3 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * SMM utilities used in both SMM and normal mode diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index b3a1a30d62..d399c7d230 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index dd786e3f05..0885f78df4 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index d73f3153e8..39735ac9a6 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SOC_AMD_STONEYRIDGE bool diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 50e53c4c35..5963b14c34 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -1,29 +1,6 @@ -#***************************************************************************** -# -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#***************************************************************************** +# SPDX-License-Identifier: BSD-3-Clause +# This file is part of the coreboot project. + ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index abdee34311..5c4f390680 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * NOTE: The layout of the GNVS structure below must match the layout in diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 02a1315aff..0acbf819d1 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef __SOC_STONEYRIDGE_ACPI_H__ #define __SOC_STONEYRIDGE_ACPI_H__ diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 12f71be192..da4525bb55 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * NOTE: The layout of the global_nvs_t structure below must match the layout diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index aaf767203f..7711b16323 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ #define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ diff --git a/src/soc/amd/stoneyridge/monotonic_timer.c b/src/soc/amd/stoneyridge/monotonic_timer.c index 2211136ce2..71563a9d3e 100644 --- a/src/soc/amd/stoneyridge/monotonic_timer.c +++ b/src/soc/amd/stoneyridge/monotonic_timer.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index ab8f405e59..0bcc221022 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * Utilities for SMM setup diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 9e0c85a129..6f38ed5ec3 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * SMM utilities used in both SMM and normal mode diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 98fe94d1b0..2b8afa7a88 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index aca7c2323a..1edfb3f6e9 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include From 9a3486e018f7ae54563d8be2c11297542e786597 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Fri, 17 Apr 2020 10:14:57 -0700 Subject: [PATCH 1091/1463] mb/google/volteer: add ec device entry to devicetree BUG=b:154279851 TEST=none Change-Id: Ibb56d97d5180ab199c52119135f7eff265908667 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/40494 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/baseboard/devicetree.cb | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2937bbd516..8a6bcf394e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -348,8 +348,11 @@ chip soc/intel/tigerlake device spi 0 on end end # FPMCU end # GSPI1 0xA0AB - - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 device pci 1f.2 on end # PMC 0xA0A1 device pci 1f.3 on From a48e7111209f7257cf40b317dc4df42e7c13ae24 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 17 Apr 2020 19:32:33 +0800 Subject: [PATCH 1092/1463] mb/google/deltaur: Correct H1 I2C gpio pin setting H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7. Previous setting was wrong so correct it. BUG=b:150165131 Signed-off-by: Eric Lai Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487 Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../google/deltaur/variants/baseboard/gpio.c | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 46a5cdd79d..71a07b6d46 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -303,14 +303,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ PAD_CFG_GPI(GPP_H5, NONE, DEEP), - /* H6 : GPP_H6 ==> SPK_DET1 */ - PAD_CFG_GPI(GPP_H6, NONE, PLTRST), - /* H7 : GPP_H7 ==> NC */ - PAD_NC(GPP_H7, NONE), - /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : GPP_H8 ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : GPP_H9 ==> NC */ + PAD_NC(GPP_H9, NONE), /* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */ @@ -436,10 +436,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ PAD_CFG_GPI(GPP_H5, NONE, DEEP), - /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* GPD3: GPD3 ==> SIO_PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), }; From 4ec683d0776c50af3d93d158235b834f5d65b579 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 28 Mar 2020 21:54:17 -0400 Subject: [PATCH 1093/1463] mb/asus/p2b*: Switch to overridetree All variants will use the same lid/thermal-polarity config as a result, which looks the same for all recently boot-tested variants anyway. Change-Id: Iaaae4eae41ab0037e72375b255d9d1c3eca8d383 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/39905 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b/Kconfig | 4 +- src/mainboard/asus/p2b/devicetree.cb | 5 -- .../p2b-d/{devicetree.cb => overridetree.cb} | 32 ---------- .../p2b-ds/{devicetree.cb => overridetree.cb} | 32 ---------- .../asus/p2b/variants/p2b-f/devicetree.cb | 59 ------------------- .../asus/p2b/variants/p2b-f/overridetree.cb | 14 +++++ .../asus/p2b/variants/p2b-ls/devicetree.cb | 58 ------------------ .../asus/p2b/variants/p2b-ls/overridetree.cb | 12 ++++ .../asus/p2b/variants/p2b/overridetree.cb | 15 +++++ 9 files changed, 43 insertions(+), 188 deletions(-) rename src/mainboard/asus/p2b/variants/p2b-d/{devicetree.cb => overridetree.cb} (50%) rename src/mainboard/asus/p2b/variants/p2b-ds/{devicetree.cb => overridetree.cb} (51%) delete mode 100644 src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb create mode 100644 src/mainboard/asus/p2b/variants/p2b-f/overridetree.cb delete mode 100644 src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb create mode 100644 src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb create mode 100644 src/mainboard/asus/p2b/variants/p2b/overridetree.cb diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 3895990eaa..0bee04f994 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -56,9 +56,9 @@ config VARIANT_DIR default "p2b-f" if BOARD_ASUS_P2B_F default "p2b-ls" if BOARD_ASUS_P2B_LS -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" if ! BOARD_ASUS_P2B + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config IRQ_SLOT_COUNT int diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 84f0c2962d..9dcd1da1db 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -37,10 +37,6 @@ chip northbridge/intel/i440bx # Northbridge end device pnp 3f0.8 on # GPIO 2 end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end end end device pci 4.1 on end # IDE @@ -56,7 +52,6 @@ chip northbridge/intel/i440bx # Northbridge register "ide1_drive1_udma33_enable" = "0" register "thrm_polarity" = "1" register "lid_polarity" = "1" - register "gpo" = "0x7fffbbff" end end end diff --git a/src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb similarity index 50% rename from src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb index fe82a0d74d..742414411b 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb @@ -8,47 +8,15 @@ chip northbridge/intel/i440bx # Northbridge end end device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end device pnp 3f0.9 on # GPIO 3 end device pnp 3f0.a on # ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb similarity index 51% rename from src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb index b8e9e8580f..6eabe5897b 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb @@ -8,47 +8,15 @@ chip northbridge/intel/i440bx # Northbridge end end device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end device pnp 3f0.9 on # GPIO 3 end device pnp 3f0.a on # ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI device pci 6.0 on end # Onboard SCSI register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb deleted file mode 100644 index 5bee5ae96a..0000000000 --- a/src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb +++ /dev/null @@ -1,59 +0,0 @@ -chip northbridge/intel/i440bx # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p2b/variants/p2b-f/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-f/overridetree.cb new file mode 100644 index 0000000000..f0fc054568 --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p2b-f/overridetree.cb @@ -0,0 +1,14 @@ +chip northbridge/intel/i440bx # Northbridge + device domain 0 on # PCI domain + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.a on # ACPI + end + end + end + end + end +end diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb deleted file mode 100644 index a9901b4198..0000000000 --- a/src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb +++ /dev/null @@ -1,58 +0,0 @@ -chip northbridge/intel/i440bx # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a off # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - device pci 6.0 on end # Onboard SCSI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb new file mode 100644 index 0000000000..bb252c0b0b --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb @@ -0,0 +1,12 @@ +chip northbridge/intel/i440bx # Northbridge + device domain 0 on # PCI domain + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.a off # ACPI + end + end + end + end + end +end diff --git a/src/mainboard/asus/p2b/variants/p2b/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b/overridetree.cb new file mode 100644 index 0000000000..6d471357e4 --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p2b/overridetree.cb @@ -0,0 +1,15 @@ +chip northbridge/intel/i440bx # Northbridge + device domain 0 on # PCI domain + chip southbridge/intel/i82371eb # Southbridge + register "gpo" = "0x7fffbbff" + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + end + end +end From 1b457f851795a2bae402a0c1e9e190cb5c6add20 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sun, 19 Apr 2020 00:02:01 +0200 Subject: [PATCH 1094/1463] soc/amd/stoneyridge/memmap: fix bug in bert_reserved_region Changing the local pointer "start" has no effect. Changing the value it points to has. Change-Id: I1b689896fcf255b795b27d7a7163849d6dfdb00e Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40506 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/amd/stoneyridge/memmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 0c8d9c0cdf..34ddcb33c9 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -32,7 +32,7 @@ void bert_reserved_region(void **start, size_t *size) if (CONFIG(ACPI_BERT)) *start = cbmem_top(); else - start = NULL; + *start = NULL; *size = BERT_REGION_MAX_SIZE; } From 04a8cfbbc047579b4051793384238228dc38301b Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Tue, 7 Apr 2020 21:02:07 -0700 Subject: [PATCH 1095/1463] soc/intel/tigerlake: Update iDisp Link UPD settings Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings. BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback Signed-off-by: Srinidhi N Kaushik Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263 Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Sathyanarayana Nujella Reviewed-by: Paul Menzel Reviewed-by: Jairaj Arava Tested-by: build bot (Jenkins) --- .../google/volteer/variants/baseboard/devicetree.cb | 7 ------- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 ------ .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 6 ------ src/soc/intel/tigerlake/chip.h | 3 --- src/soc/intel/tigerlake/romstage/fsp_params.c | 3 --- 5 files changed, 25 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8a6bcf394e..28931e486d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -121,13 +121,6 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" register "PchHdaAudioLinkSspEnable[1]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" - # TCSS USB3 register "TcssXhciEn" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 8b4f8f8bbf..82f358e8b6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -121,12 +121,6 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkSspEnable[1]" = "0" register "PchHdaAudioLinkSspEnable[2]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 9b5774bd1c..fec2fefa16 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -117,12 +117,6 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkSspEnable[1]" = "0" register "PchHdaAudioLinkSspEnable[2]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 26eab4c8fd..a3319d4ee4 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -96,9 +96,6 @@ struct soc_intel_tigerlake_config { uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; - uint8_t PchHdaIDispLinkTmode; - uint8_t PchHdaIDispLinkFrequency; - uint8_t PchHdaIDispCodecDisconnect; /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 6056b4b0c1..b4521e2a61 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -165,9 +165,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); - m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; - m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; /* Vt-D config */ m_cfg->VtdDisable = 0; From 52f18df1e361fe9a29a7b75ee514646e640afd50 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Wed, 25 Mar 2020 11:34:25 -0700 Subject: [PATCH 1096/1463] google/chromeec: Revise parameters of EC USB PD API call This patch adds voltage and curent parameters in google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could use the voltage and current information to calculate charger power rating. The reason for this change is, some applications need the voltage information to calculate correct system power eg PsysPmax. BUG=b:151972149 TEST=emerge-puff coreboot; emerge-fizz coreboot Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/ec/google/chromeec/ec.c | 8 ++++---- src/ec/google/chromeec/ec.h | 5 +++-- src/mainboard/google/fizz/mainboard.c | 4 +++- src/mainboard/google/hatch/variants/puff/mainboard.c | 4 +++- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 17e110c5c9..73baec63be 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1120,9 +1120,9 @@ int google_chromeec_set_usb_charge_mode(uint8_t port_id, enum usb_charge_mode mo return google_chromeec_command(&cmd); } -/* Get charger power info in Watts. Also returns type of charger */ +/* Get charger voltage and current. Also returns type of charger */ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, - uint32_t *max_watts) + uint16_t *current_max, uint16_t *voltage_max) { struct ec_params_usb_pd_power_info params = { .port = PD_POWER_CHARGING_PORT, @@ -1147,8 +1147,8 @@ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, /* values are given in milliAmps and milliVolts */ *type = resp.type; m = resp.meas; - *max_watts = (m.current_max * m.voltage_max) / 1000000; - + *voltage_max = m.voltage_max; + *current_max = m.current_max; return 0; } diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 13e3bd9b7f..64d7e52981 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -102,11 +102,12 @@ int google_chromeec_set_usb_pd_role(uint8_t port, enum usb_pd_control_role role) * Retrieve the charger type and max wattage. * * @param type charger type - * @param max_watts charger max wattage + * @param current_max charger max current + * @param voltage_max charger max voltage * @return non-zero for error, otherwise 0. */ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, - uint32_t *max_watts); + uint16_t *current_max, uint16_t *voltage_max); /* * Set max current and voltage of a dedicated charger. diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index daf9da4388..9f35411c24 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -104,8 +104,9 @@ static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; u32 watts; + u16 volts_mv, current_ma; u32 pl2, psyspl2; - int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); + int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); uint8_t sku = board_sku_id(); const uint32_t u42_mask = (1 << FIZZ_SKU_ID_I7_U42) | (1 << FIZZ_SKU_ID_I5_U42) | @@ -126,6 +127,7 @@ static void mainboard_set_power_limits(config_t *conf) psyspl2 = FIZZ_PSYSPL2_U42; } else { /* Detected TypeC. Base on max value of adapter */ + watts = ((u32)volts_mv * current_ma) / 1000000; psyspl2 = watts; conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); /* set max possible time window */ diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index e8098b96ac..3f74c968b1 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -90,8 +90,9 @@ static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; u32 watts; + u16 volts_mv, current_ma; u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); + int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ conf->tdp_psyspl3 = 0; @@ -99,6 +100,7 @@ static void mainboard_set_power_limits(config_t *conf) if (rv == 0 && type == USB_CHG_TYPE_PD) { /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; psyspl2 = watts; conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); /* set max possible time window */ From 7691ebc379bd3d1ca0f92bd25db974ec7dfff4b3 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Sat, 11 Apr 2020 22:05:50 +0800 Subject: [PATCH 1097/1463] Doc/mb/hp: rename the document about HP laptops with KBC1126 Later EliteBooks use different EC chips and have different EC firmware interfaces, so rename the document elitebook_series.md to a more precise name and also do some rewriting. A link to the code review page for 8760w is also added because the port for this laptop is not merged yet. Change-Id: I2f9b8c4e52ed760c16977d16838cca9e490cda05 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/40315 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/mainboard/hp/8760w.md | 6 +++- ...tebook_series.md => hp_kbc1126_laptops.md} | 30 +++++++++---------- Documentation/mainboard/index.md | 2 +- 3 files changed, 20 insertions(+), 18 deletions(-) rename Documentation/mainboard/hp/{elitebook_series.md => hp_kbc1126_laptops.md} (81%) diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md index 714745aa04..071d35e251 100644 --- a/Documentation/mainboard/hp/8760w.md +++ b/Documentation/mainboard/hp/8760w.md @@ -2,6 +2,9 @@ This page describes how to run coreboot on the [HP EliteBook 8760w]. +The coreboot code for this laptop is still not merged, you need to +checkout the [code on gerrit] to build coreboot for the laptop. + ## Flashing coreboot ```eval_rst @@ -29,7 +32,7 @@ This page describes how to run coreboot on the [HP EliteBook 8760w]. ## Required proprietary blobs - Intel Firmware Descriptor, ME and GbE firmware -- EC: please read [EliteBook Series](elitebook_series) +- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops) ## Flashing instructions @@ -80,3 +83,4 @@ clip to read and flash the chip. ``` [HP EliteBook 8760w]: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/5071180 +[code on gerrit]: https://review.coreboot.org/c/coreboot/+/30936 diff --git a/Documentation/mainboard/hp/elitebook_series.md b/Documentation/mainboard/hp/hp_kbc1126_laptops.md similarity index 81% rename from Documentation/mainboard/hp/elitebook_series.md rename to Documentation/mainboard/hp/hp_kbc1126_laptops.md index 6668928008..357af4fb42 100644 --- a/Documentation/mainboard/hp/elitebook_series.md +++ b/Documentation/mainboard/hp/hp_kbc1126_laptops.md @@ -1,13 +1,14 @@ -# HP EliteBook series +# HP Laptops with KBC1126 Embedded Controller This document is about HP EliteBook series laptops up to Ivy Bridge era which use SMSC KBC1126 as embedded controller. -## EC +SMSC KBC1126 (and older similar chips like KBC1098) has been used in +HP EliteBooks for many generations. BIOS and EC firmware share an SPI +flash chip in these laptops, so we need to put firmware blobs for the +EC to the coreboot image. -SMSC KBC1098/KBC1126 has been used in HP EliteBooks for many generations. -They use similar EC firmware that will load other code and data from the -SPI flash chip, so we need to put some firmware blobs to the coreboot image. +## EC firmware extraction and coreboot building The following document takes EliteBook 2760p as an example. @@ -32,18 +33,15 @@ Chipset ---> (2760p-fw2.bin) KBC1126 filename #2 path and filename ``` -## Super I/O +## Porting guide for HP laptops with KBC1126 -EliteBook 8000 series laptops have SMSC LPC47n217 Super I/O to provide -a serial port and a parallel port, you can debug the laptop via this -serial port. - -## porting - -To port coreboot to an HP EliteBook laptop, you need to do the following: +To port coreboot to an HP laptop with KBC1126, you need to do the +following: - select Kconfig option `EC_HP_KBC1126` -- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217 Super I/O +- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217 + Super I/O, usually in EliteBook 8000 series, which can be used for + debugging via serial port - initialize EC and Super I/O in romstage - add EC and Super I/O support to devicetree.cb @@ -51,8 +49,8 @@ To get the related values for EC in devicetree.cb, you need to extract the EFI module EcThermalInit from the vendor UEFI firmware with [UEFITool]. Usually, `ec_data_port`, `ec_cmd_port` and `ec_ctrl_reg` has the following values: -- For xx60 series: 0x60, 0x64, 0xca -- For xx70 series: 0x62, 0x66, 0x81 +- For EliteBook xx60 series: 0x60, 0x64, 0xca +- For EliteBook xx70 series: 0x62, 0x66, 0x81 You can use [radare2] and the following [r2pipe] Python script to find these values from the EcThermalInit EFI module: diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 7637f7bcbe..57df302986 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -58,7 +58,7 @@ The boards in this section are not real mainboards, but emulators. ### EliteBook series -- [EliteBook common](hp/elitebook_series.md) +- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) - [EliteBook 8760w](hp/8760w.md) ## Intel From fb8823ddaa5badd3a7575b48cb8b8aec1016f2a7 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 17 Apr 2020 19:24:00 +0800 Subject: [PATCH 1098/1463] mb/google/deltaur: Add memory topology SODIMM and MEMORYDOWN Update memory topology for spd info. Deltan supports SODIMM and Deltaur supports MEMORYDOWN. BUG=b:151702387 Signed-off-by: Eric Lai Change-Id: If314894325d6f222807030a36f8c4cefecfe5bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40486 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel --- src/mainboard/google/deltaur/variants/deltan/memory.c | 1 + src/mainboard/google/deltaur/variants/deltaur/memory.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index 90fa642c04..d51ba70431 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -47,6 +47,7 @@ static const struct mb_ddr4_cfg baseboard_memcfg = { void variant_memory_init(FSP_M_CONFIG *mem_cfg) { const struct spd_info spd_info = { + .topology = SODIMM, .smbus_info[0] = {.addr_dimm0 = 0xa0, .addr_dimm1 = 0 }, .smbus_info[1] = {.addr_dimm0 = 0xa4, diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c index c2df46703c..c25df392b7 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/memory.c +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -83,6 +83,7 @@ void variant_memory_init(FSP_M_CONFIG *mem_cfg) { const struct lpddr4x_cfg *board_cfg = variant_memory_params(); const struct spd_info spd_info = { + .topology = MEMORY_DOWN, .md_spd_loc = SPD_CBFS, .cbfs_index = variant_memory_sku(), }; From fe7c2b996bbb011f5e0bb66b56c2438776bd0174 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 24 Feb 2020 12:01:26 +0100 Subject: [PATCH 1099/1463] mb/asus/p8h61-m_lx3_r2_0: Add new mainboard This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality. Working: - Both DIMM slots - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - Arch Linux using CorebootPayloadPkg Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39099 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig | 34 +++ .../asus/p8h61-m_lx3_r2_0/Kconfig.name | 2 + .../asus/p8h61-m_lx3_r2_0/Makefile.inc | 7 + .../asus/p8h61-m_lx3_r2_0/acpi/ec.asl | 0 .../asus/p8h61-m_lx3_r2_0/acpi/platform.asl | 11 + .../asus/p8h61-m_lx3_r2_0/acpi/superio.asl | 4 + .../asus/p8h61-m_lx3_r2_0/acpi_tables.c | 10 + .../asus/p8h61-m_lx3_r2_0/board_info.txt | 7 + src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt | Bin 0 -> 7168 bytes .../asus/p8h61-m_lx3_r2_0/devicetree.cb | 89 ++++++++ src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl | 26 +++ .../asus/p8h61-m_lx3_r2_0/early_init.c | 57 +++++ .../asus/p8h61-m_lx3_r2_0/gma-mainboard.ads | 14 ++ src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c | 213 ++++++++++++++++++ .../asus/p8h61-m_lx3_r2_0/hda_verb.c | 26 +++ 15 files changed, 500 insertions(+) create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c create mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig new file mode 100644 index 0000000000..2fc06451b4 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig @@ -0,0 +1,34 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +if BOARD_ASUS_P8H61_M_LX3_R2_0 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NO_UART_ON_SUPERIO + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default asus/p8h61-m_lx3_r2_0 + +config MAINBOARD_PART_NUMBER + string + default "P8H61-M LX3 R2.0" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name new file mode 100644 index 0000000000..6d10dcfc39 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8H61_M_LX3_R2_0 + bool "P8H61-M LX3 R2.0" diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc new file mode 100644 index 0000000000..7167e10123 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl new file mode 100644 index 0000000000..b84cada0a4 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl new file mode 100644 index 0000000000..bbab2af6d0 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c new file mode 100644 index 0000000000..3851d04b22 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt new file mode 100644 index 0000000000..3e3c173aa9 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/us/Motherboards/P8H61M_LX3_R20 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt b/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..e5be40c56b711fa4477da4b57f8d017a89b2ce64 GIT binary patch literal 7168 zcmeHKU1%It6h5;v`*&w1*-T=)S<`S+OS?()GufsghN!bYiP?0UY_i*BEn<^)w?B}k z>Gp>ftQj@fiXf{q_p9FpAlLQe7A|m2LDLzOk(uX2gYS%M&CQaH%I*7#z zdx!6yd(WIXd+&G8IWxO16G_w5aHJ!iiL}M~Q(Mv_$sDNgY_*F0@)n7Yq;|x@>F|z7 zVkEkSo`+RXRekq5Kn}QCIn>#;DL!>LKN%crrm2ak-0_`-eYrjPj`&e)M3d1t4e#2O zpUf8~4(D?;m3cl)4Yx9h9N9OSqr*q`@5~o^so@K)X=hjarY=g=%^jgoM@a1qQQG-* zZ`Y>Y&doB3^+!jxCgX{4IzBQ?N5*I@o(iW@{aYi67ie;9WH26yr~6|vVOxnFm_AqO99qgvjp}`lHf!DZ)%?%t~ z_$^~@G|KuFx<_RoG=LiF>h9_7(;~5f!J$NQES<@2e^Gz+wby3@aHq)Dgsejqr$Uks z!U^61C;1-OD3stgmj^;_1!9N{VlU!^o4`rLJBSYv7Z8^bUn0Ij{D`=QxPkZ`0UiPb zQHN+m1Q8)bA7TKJL~KXo5K{=(5x7%!=t!f{bk34BrUah=Z#RQ}&eET=^xm6z!q|u< zMN2ZJjjmjFyWwv6TR)V`o@a~|Xz0NRgqY=N(2@xzc|K{)(0DuBd5az}DvDnB_qu|IEfvU(75^`M1ez3M;J zZ94O-EpTQOR85_(H8qVFI*wf(4XoF)XBISr&uQw;OCe3WvY_z?p?iim$&|WhoWP1a zj<_O=9UQrg*9d@AAB1|ijaNMsISS@A2by)Ya*LyY;pNG1U>+;sy!#e+s`l|58T+!= z%H@V`_`$0e>D4tp&-hyNsYW}RpdU#+^tV6L{2uV{dg`h6lqLUG9nol=^LVQMkJqzbWT)$63H(jC6dx0 zk@XTyNXknR*(=evC8Z>hixQoelxq^XAyGwE*2$z@rfFH(Et6@Po|cshGPx|vEjI<- zah20+Fg`H~JOv3)G3$_+yv6xYI;%I}J7f9wF>tJ4qI}lza1W(w3Z2;o8r177O1ozq zRuCGs>ERxhXMz#XX7J*tiC}o>TX7f5Gsj2-Gw6>w1GYRIqoV#Fsmn@^lyTZ&a(7ea;wUt#14ZjB{K#aH6Hj!a#+A3Ii1eDhyN@c-$HI3u|k6hyVZp literal 0 HcmV?d00001 diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb new file mode 100644 index 0000000000..6d919592eb --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb @@ -0,0 +1,89 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x1043 0x844d inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4: PCIEX1_1 + device pci 1c.4 on end # RP #5: PCIEX1_2 + device pci 1c.5 on end # RP #6: RTL8111 GbE NIC + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl new file mode 100644 index 0000000000..af0cbad1d1 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c new file mode 100644 index 0000000000..e6f8186743 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Do not enable UART, the header is not populated by default */ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads new file mode 100644 index 0000000000..767f5af2f9 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads @@ -0,0 +1,14 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (Analog, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c new file mode 100644 index 0000000000..096ed43d9e --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c new file mode 100644 index 0000000000..cab7aa5da7 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +const u32 cim_verb_data[] = { + 0x11060397, /* Codec Vendor / Device ID: VIA VT1708S */ + 0x10438415, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438415), + AZALIA_PIN_CFG(0, 0x19, 0x410110f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x585600f0), + AZALIA_PIN_CFG(0, 0x21, 0x474411f0), + AZALIA_PIN_CFG(0, 0x22, 0x410160f0), + AZALIA_PIN_CFG(0, 0x23, 0x410120f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; From 2246216971793ff918ccdf22675ca45bc5d79098 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sat, 18 Apr 2020 13:46:12 -0600 Subject: [PATCH 1100/1463] Doc,util: Update list of utilities Remove entries for old utilities and add entries for new ones. Generated using util/util_readme, with some tweaks to preserve the markdown. Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/util.md | 26 +++++++++++++++----------- util/README.md | 24 +++++++++++++++--------- 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/Documentation/util.md b/Documentation/util.md index feda972e90..27a7c9cab9 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -10,8 +10,6 @@ available targets. `bash` * __amdtools__ - A set of tools to compare extended) K8 memory settings. `Perl` * __archive__ - Concatenate files and create an archive `C` -* __mksunxiboot__ - A simple tool to generate bootable image for sunxi -platform. `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex` @@ -26,11 +24,11 @@ file `Python` * _fmaptool_ - Converts plaintext fmd files into fmap blobs `C` * _rmodtool_ - Creates rmodules `C` * _ifwitool_ - For manipulating IFWI `C` -* __cbmem__ - Cbmem console log reader `C` -* __checklist__ - Board implementation checklist generator `Make` -* __chromeos__ - These scripts can be used to extract System Agent -reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms) -from a Chrome OS recovery image. `C` +* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C` +* __chromeos__ - These scripts can be used to access Chrome OS +resources, for example to extract System Agent reference code and other +blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS +recovery image. `C` * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no libc support) * __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_, @@ -62,8 +60,6 @@ specified base and size `Python` * _mbncat.py_ - Generate ipq8064 uber SBL `Python` * *mbn_tools.py* - Contains all MBN Utilities for image generation `Python` -* __k8resdump__ - This program will dump the IO/memory/PCI resources -from the K8 memory controller `C` * __kbc1126__ - Tools used to dump the two blobs from the factory firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126 embedded controller and insert them to the firmware image. `C` @@ -78,6 +74,8 @@ partial deblobbing of Intel ME/TXE firmware images `Python` * __nvidia__ - nvidia blob parsers * __nvramtool__ - Reads and writes coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM. `C` +* __pgtblgen__ - Generates page tables based on fixed physical address. +`C` * __pmh7tool__ - Dumps, reads and writes PMH7 registers on Lenovo ThinkPads. PMH7 is used for switching on and off the power of some devices on the board such as dGPU. `C` @@ -91,14 +89,14 @@ can be passed to SPIKE, the RISC-V reference emulator.`Bash` * _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for SiFive's bootrom. `Python3` * __rockchip__ - Generate Rockchip idblock bootloader. `Python2` -* __romcc__ - Compile a C source file generating a binary that does not -implicitly use RAM. `C` * __sconfig__ - coreboot device tree compiler `Lex` `Yacc` * __scripts__ * _config_ - Manipulate options in a .config file from the command line `Bash` * _cross-repo-cherrypick_ - Pull in patches from another tree from a gerrit repository. `Shell` + * _decode_spd.sh_ - Decodes Serial Presence Detect (SPD) files +into various human readable formats. * _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an fmaptool compatible .fmd format `Bash` * _find-unused-kconfig-symbols.sh_ - Points out Kconfig @@ -116,15 +114,21 @@ file `Perl` * _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash` * _update_submodules_ - Check all submodules for updates `Bash` * __showdevicetree__ - Compile and dump the device tree `C` +* __spdtool__ - Dumps SPD ROMs from a given blob to separate files +using known patterns and reserved bits. Useful for analysing firmware +that holds SPDs on boards that have soldered down DRAM. `python` * __spkmodem_recv__ - Decode spkmodem signals `C` * __superiotool__ - A user-space utility to detect Super I/O of a mainboard and provide detailed information about the register contents of the Super I/O. `C` +* __smcbiosinfo__ - Generates SMC biosinfo for BMC BIOS updates `C` * __testing__ - coreboot test targets `Make` * __uio_usbdebug__ - Debug coreboot's usbdebug driver inside a running operating system (only Linux at this time). `C` * __util_readme__ - Creates README.md of description files in `./util` subdirectories `Bash` +* __vboot_list__ - Tools to generate a list of vboot enabled devices to +the documentation `Bash` * __vgabios__ - emulated vga driver for qemu `C` * __x86__ - Generates 32-bit PAE page tables based on a CSV input file. `Go` diff --git a/util/README.md b/util/README.md index 4656084ad7..8b05f6f729 100644 --- a/util/README.md +++ b/util/README.md @@ -5,8 +5,6 @@ available targets. `bash` * __amdtools__ - A set of tools to compare extended) K8 memory settings. `Perl` * __archive__ - Concatenate files and create an archive `C` -* __mksunxiboot__ - A simple tool to generate bootable image for sunxi -platform. `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex` @@ -21,11 +19,11 @@ file `Python` * _fmaptool_ - Converts plaintext fmd files into fmap blobs `C` * _rmodtool_ - Creates rmodules `C` * _ifwitool_ - For manipulating IFWI `C` -* __cbmem__ - Cbmem console log reader `C` -* __checklist__ - Board implementation checklist generator `Make` -* __chromeos__ - These scripts can be used to extract System Agent -reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms) -from a Chrome OS recovery image. `C` +* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C` +* __chromeos__ - These scripts can be used to access Chrome OS +resources, for example to extract System Agent reference code and other +blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS +recovery image. `C` * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no libc support) * __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_, @@ -57,8 +55,6 @@ specified base and size `Python` * _mbncat.py_ - Generate ipq8064 uber SBL `Python` * *mbn_tools.py* - Contains all MBN Utilities for image generation `Python` -* __k8resdump__ - This program will dump the IO/memory/PCI resources -from the K8 memory controller `C` * __kbc1126__ - Tools used to dump the two blobs from the factory firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126 embedded controller and insert them to the firmware image. `C` @@ -73,6 +69,8 @@ partial deblobbing of Intel ME/TXE firmware images `Python` * __nvidia__ - nvidia blob parsers * __nvramtool__ - Reads and writes coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM. `C` +* __pgtblgen__ - Generates page tables based on fixed physical address. +`C` * __pmh7tool__ - Dumps, reads and writes PMH7 registers on Lenovo ThinkPads. PMH7 is used for switching on and off the power of some devices on the board such as dGPU. `C` @@ -92,6 +90,8 @@ SiFive's bootrom. `Python3` command line `Bash` * _cross-repo-cherrypick_ - Pull in patches from another tree from a gerrit repository. `Shell` + * _decode_spd.sh_ - Decodes Serial Presence Detect (SPD) files +into various human readable formats. * _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an fmaptool compatible .fmd format `Bash` * _find-unused-kconfig-symbols.sh_ - Points out Kconfig @@ -109,15 +109,21 @@ file `Perl` * _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash` * _update_submodules_ - Check all submodules for updates `Bash` * __showdevicetree__ - Compile and dump the device tree `C` +* __spdtool__ - Dumps SPD ROMs from a given blob to separate files +using known patterns and reserved bits. Useful for analysing firmware +that holds SPDs on boards that have soldered down DRAM. `python` * __spkmodem_recv__ - Decode spkmodem signals `C` * __superiotool__ - A user-space utility to detect Super I/O of a mainboard and provide detailed information about the register contents of the Super I/O. `C` +* __smcbiosinfo__ - Generates SMC biosinfo for BMC BIOS updates `C` * __testing__ - coreboot test targets `Make` * __uio_usbdebug__ - Debug coreboot's usbdebug driver inside a running operating system (only Linux at this time). `C` * __util_readme__ - Creates README.md of description files in `./util` subdirectories `Bash` +* __vboot_list__ - Tools to generate a list of vboot enabled devices to +the documentation `Bash` * __vgabios__ - emulated vga driver for qemu `C` * __x86__ - Generates 32-bit PAE page tables based on a CSV input file. `Go` From 85801f670de57de1e3e4785916d667a190fcb918 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Wed, 25 Mar 2020 13:13:04 -0700 Subject: [PATCH 1101/1463] mb/google/hatch/vr/puff: Add psys_pmax calculation This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Signed-off-by: Gaggery Tsai Change-Id: I8ea01f856411e05a533489280fc2b4a46a1440c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39850 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- .../google/hatch/variants/puff/mainboard.c | 55 +++++++++++++------ 1 file changed, 37 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index 3f74c968b1..ceeb0c5aba 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -31,23 +31,6 @@ static void wait_for_hpd(gpio_t gpio, long timeout) stopwatch_duration_msecs(&sw)); } -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - - /* This is reconfigured back to whatever FSP-S expects by - gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } -} - /* * For type-C chargers, set PL2 to 90% of max power to account for * cable loss and FET Rdson loss in the path from the source. @@ -86,6 +69,24 @@ void variant_ramstage_init(void) * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ + +/* + * Psys_pmax considerations + * + * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A + * instead of real system power. The equation is shown below: + * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) + * Hence, Iinput (Amps) = 9.6A + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W + * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W + * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W + */ +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000 + static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; @@ -108,15 +109,33 @@ static void mainboard_set_power_limits(config_t *conf) /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } else { + /* Input type is barrel jack */ + volts_mv = BJ_VOLTS_MV; } + /* voltage unit is milliVolts and current is in milliAmps */ + conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); conf->tdp_pl2_override = PUFF_PL2; /* set psyspl2 to 90% of max adapter power */ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); } -void variant_mainboard_enable(struct device *dev) +void variant_ramstage_init(void) { + static const long display_timeout_ms = 3000; config_t *conf = config_of_soc(); + + /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + /* Psys_pmax needs to be setup before FSP-S */ mainboard_set_power_limits(conf); } From b81147cb56cb7265d1584491e37accdb2f2f61d7 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 20 Apr 2020 09:25:51 +0200 Subject: [PATCH 1102/1463] security/vboot, mb/google: Fix build errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There have been two cases of incompatibilities between overlapping changes, and they need to be resolved in a single commit to unbreak the tree: 1. CB:40389 introduced a new use of write_secdata while CB:40359 removed that function in favor of safe_write. Follow the refactor of the latter in the code introduced by the former. 2. CB:39849 changed google_chromeec_get_usb_pd_power_info()'s interface and adapted all its users. Except for duffy and kaisa which were only added in CB:40223 and CB:40393 respectively, so reapply the patch to puff's mainboard.c to their mainboard.c files. Change-Id: Ib8dfcd61bb79e0a487eaa60e719bd93561f2d97a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/40518 Tested-by: build bot (Jenkins) Reviewed-by: Christian Walter Reviewed-by: Paul Menzel Reviewed-by: Werner Zeh Reviewed-by: Kyösti Mälkki --- src/mainboard/google/hatch/variants/duffy/mainboard.c | 4 +++- src/mainboard/google/hatch/variants/kaisa/mainboard.c | 4 +++- src/security/vboot/secdata_tpm.c | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c index e8098b96ac..3f74c968b1 100644 --- a/src/mainboard/google/hatch/variants/duffy/mainboard.c +++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c @@ -90,8 +90,9 @@ static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; u32 watts; + u16 volts_mv, current_ma; u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); + int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ conf->tdp_psyspl3 = 0; @@ -99,6 +100,7 @@ static void mainboard_set_power_limits(config_t *conf) if (rv == 0 && type == USB_CHG_TYPE_PD) { /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; psyspl2 = watts; conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); /* set max possible time window */ diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c index e8098b96ac..3f74c968b1 100644 --- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c +++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c @@ -90,8 +90,9 @@ static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; u32 watts; + u16 volts_mv, current_ma; u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); + int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ conf->tdp_psyspl3 = 0; @@ -99,6 +100,7 @@ static void mainboard_set_power_limits(config_t *conf) if (rv == 0 && type == USB_CHG_TYPE_PD) { /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; psyspl2 = watts; conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); /* set max possible time window */ diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 672578a481..d666ae8a5e 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -415,7 +415,7 @@ uint32_t antirollback_write_space_kernel(struct vb2_context *ctx) uint8_t size = VB2_SECDATA_KERNEL_MIN_SIZE; vb2api_secdata_kernel_check(ctx, &size); - return write_secdata(KERNEL_NV_INDEX, ctx->secdata_kernel, size); + return safe_write(KERNEL_NV_INDEX, ctx->secdata_kernel, size); } uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) From e6b0a32cb305f8f201d93ba41215ba9e976c7698 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 5 Dec 2019 13:49:19 +0100 Subject: [PATCH 1103/1463] libpayload: Make 8250 UART driver relocation safe `lib_sysinfo->serial` is a virtual pointer into coreboot tables. It's not valid across relocation. Accessing the wrong value during relocation of FILO resulted in a hang with DEBUG_SEGMENT and UART console enabled. Work around that by caching the whole table entry locally. An alternative would be to revise `sysinfo`, to contain no virtual pointers to anything outside the payload. Change-Id: I03adaf57b83a177316d7778f7e06df8eb6f9158e Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37513 Tested-by: build bot (Jenkins) Reviewed-by: Reto Buerki Reviewed-by: Angel Pons --- payloads/libpayload/drivers/serial/8250.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c index 9502d4b147..4a7cc01a0a 100644 --- a/payloads/libpayload/drivers/serial/8250.c +++ b/payloads/libpayload/drivers/serial/8250.c @@ -31,7 +31,9 @@ #include #include -#define IOBASE lib_sysinfo.serial->baseaddr +static struct cb_serial cb_serial; + +#define IOBASE cb_serial.baseaddr #define MEMBASE (phys_to_virt(IOBASE)) static int serial_hardware_is_present = 0; @@ -39,14 +41,14 @@ static int serial_is_mem_mapped = 0; static uint8_t serial_read_reg(int offset) { - offset *= lib_sysinfo.serial->regwidth; + offset *= cb_serial.regwidth; #if CONFIG(LP_IO_ADDRESS_SPACE) if (!serial_is_mem_mapped) return inb(IOBASE + offset); else #endif - if (lib_sysinfo.serial->regwidth == 4) + if (cb_serial.regwidth == 4) return readl(MEMBASE + offset) & 0xff; else return readb(MEMBASE + offset); @@ -54,14 +56,14 @@ static uint8_t serial_read_reg(int offset) static void serial_write_reg(uint8_t val, int offset) { - offset *= lib_sysinfo.serial->regwidth; + offset *= cb_serial.regwidth; #if CONFIG(LP_IO_ADDRESS_SPACE) if (!serial_is_mem_mapped) outb(val, IOBASE + offset); else #endif - if (lib_sysinfo.serial->regwidth == 4) + if (cb_serial.regwidth == 4) writel(val & 0xff, MEMBASE + offset); else writeb(val, MEMBASE + offset); @@ -108,11 +110,7 @@ static struct console_output_driver consout = { void serial_init(void) { - if (!lib_sysinfo.serial) - return; - - serial_is_mem_mapped = - (lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED); + serial_is_mem_mapped = (cb_serial.type == CB_SERIAL_TYPE_MEMORY_MAPPED); if (!serial_is_mem_mapped) { #if CONFIG(LP_IO_ADDRESS_SPACE) @@ -130,15 +128,16 @@ void serial_init(void) #if CONFIG(LP_SERIAL_SET_SPEED) serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1); #endif + serial_hardware_is_present = 1; } void serial_console_init(void) { if (!lib_sysinfo.serial) return; + cb_serial = *lib_sysinfo.serial; serial_init(); - serial_hardware_is_present = 1; console_add_input_driver(&consin); console_add_output_driver(&consout); From a28e3fb694ecff6efefbbeef1d0882731a6a2bd2 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 1 Apr 2020 17:01:13 -0700 Subject: [PATCH 1104/1463] arch/x86/acpi: Add code to generate ACPI for PS2 keyboards Add new file to generate ACPI _DSD code for PS2 keyboards. The following 2 device properties are generated as needed: function-row-phymap: A list of ordered scancodes for function row. linux,keymap: Symantically, this is an array of "scancode,keycode" tuple entries. Each entry teaches linux the keycode corresponding to a scancode. Signed-off-by: Rajat Jain Change-Id: I5ee05173106a125793e91c263610731543c85472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40031 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/acpigen_ps2_keybd.c | 297 ++++++++++++++++++ src/arch/x86/include/arch/acpigen_ps2_keybd.h | 41 +++ 3 files changed, 339 insertions(+) create mode 100644 src/arch/x86/acpigen_ps2_keybd.c create mode 100644 src/arch/x86/include/arch/acpigen_ps2_keybd.h diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b28ef78adc..2d007094c7 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -235,6 +235,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_ps2_keybd.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += c_start.S diff --git a/src/arch/x86/acpigen_ps2_keybd.c b/src/arch/x86/acpigen_ps2_keybd.c new file mode 100644 index 0000000000..1573de8924 --- /dev/null +++ b/src/arch/x86/acpigen_ps2_keybd.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +#define KEYMAP(scancode, keycode) (((uint32_t)(scancode) << 16) | (keycode & 0xFFFF)) +#define SCANCODE(keymap) ((keymap >> 16) & 0xFFFF) + +/* Possible keymaps for function keys in the top row */ +static const uint32_t function_keymaps[] = { + KEYMAP(0x3b, KEY_F1), + KEYMAP(0x3c, KEY_F2), + KEYMAP(0x3d, KEY_F3), + KEYMAP(0x3e, KEY_F4), + KEYMAP(0x3f, KEY_F5), + KEYMAP(0x40, KEY_F6), + KEYMAP(0x41, KEY_F7), + KEYMAP(0x42, KEY_F8), + KEYMAP(0x43, KEY_F9), + KEYMAP(0x44, KEY_F10), + KEYMAP(0x57, KEY_F11), + KEYMAP(0x58, KEY_F12), + KEYMAP(0x59, KEY_F13), + KEYMAP(0x5a, KEY_F14), + KEYMAP(0x5b, KEY_F15), +}; + +/* + * Possible keymaps for action keys in the top row. This is a superset of + * possible keys. Individual keyboards will have a subset of these keys. + * The scancodes are true / condensed 1 byte scancodes from set-1 + */ +static const uint32_t action_keymaps[] = { + [PS2_KEY_BACK] = KEYMAP(0xea, KEY_BACK), /* e06a */ + [PS2_KEY_FORWARD] = KEYMAP(0xe9, KEY_FORWARD), /* e069 */ + [PS2_KEY_REFRESH] = KEYMAP(0xe7, KEY_REFRESH), /* e067 */ + [PS2_KEY_FULLSCREEN] = KEYMAP(0x91, KEY_FULL_SCREEN), /* e011 */ + [PS2_KEY_OVERVIEW] = KEYMAP(0x92, KEY_SCALE), /* e012 */ + [PS2_KEY_VOL_MUTE] = KEYMAP(0xa0, KEY_MUTE), /* e020 */ + [PS2_KEY_VOL_DOWN] = KEYMAP(0xae, KEY_VOLUMEDOWN), /* e02e */ + [PS2_KEY_VOL_UP] = KEYMAP(0xb0, KEY_VOLUMEUP), /* e030 */ + [PS2_KEY_PLAY_PAUSE] = KEYMAP(0x9a, KEY_PLAYPAUSE), /* e01a */ + [PS2_KEY_NEXT_TRACK] = KEYMAP(0x99, KEY_NEXTSONG), /* e019 */ + [PS2_KEY_PREV_TRACK] = KEYMAP(0x90, KEY_PREVIOUSSONG), /* e010 */ + [PS2_KEY_SNAPSHOT] = KEYMAP(0x93, KEY_SYSRQ), /* e013 */ + [PS2_KEY_BRIGHTNESS_DOWN] = KEYMAP(0x94, KEY_BRIGHTNESSDOWN),/* e014 */ + [PS2_KEY_BRIGHTNESS_UP] = KEYMAP(0x95, KEY_BRIGHTNESSUP), /* e015 */ + [PS2_KEY_KBD_BKLIGHT_DOWN] = KEYMAP(0x97, KEY_KBDILLUMDOWN), /* e017 */ + [PS2_KEY_KBD_BKLIGHT_UP] = KEYMAP(0x98, KEY_KBDILLUMUP), /* e018 */ + [PS2_KEY_PRIVACY_SCRN_TOGGLE] = KEYMAP(0x96, /* e016 */ + KEY_PRIVACY_SCREEN_TOGGLE), +}; + +/* Keymap for numeric keypad keys */ +static uint32_t numeric_keypad_keymaps[] = { + /* Row-0 */ + KEYMAP(0xc9, KEY_PAGEUP), + KEYMAP(0xd1, KEY_PAGEDOWN), + KEYMAP(0xc7, KEY_HOME), + KEYMAP(0xcf, KEY_END), + /* Row-1 */ + KEYMAP(0xd3, KEY_DELETE), + KEYMAP(0xb5, KEY_KPSLASH), + KEYMAP(0x37, KEY_KPASTERISK), + KEYMAP(0x4a, KEY_KPMINUS), + /* Row-2 */ + KEYMAP(0x47, KEY_KP7), + KEYMAP(0x48, KEY_KP8), + KEYMAP(0x49, KEY_KP9), + KEYMAP(0x4e, KEY_KPPLUS), + /* Row-3 */ + KEYMAP(0x4b, KEY_KP4), + KEYMAP(0x4c, KEY_KP5), + KEYMAP(0x4d, KEY_KP6), + /* Row-4 */ + KEYMAP(0x4f, KEY_KP1), + KEYMAP(0x50, KEY_KP2), + KEYMAP(0x51, KEY_KP3), + KEYMAP(0x9c, KEY_KPENTER), + /* Row-5 */ + KEYMAP(0x52, KEY_KP0), + KEYMAP(0x53, KEY_KPDOT), +}; + +/* + * Keymap for rest of non-top-row keys. This is a superset of all the possible + * keys that any chromeos keyboards can have. + */ +static uint32_t rest_of_keymaps[] = { + /* Row-0 */ + KEYMAP(0x01, KEY_ESC), + /* Row-1 */ + KEYMAP(0x29, KEY_GRAVE), + KEYMAP(0x02, KEY_1), + KEYMAP(0x03, KEY_2), + KEYMAP(0x04, KEY_3), + KEYMAP(0x05, KEY_4), + KEYMAP(0x06, KEY_5), + KEYMAP(0x07, KEY_6), + KEYMAP(0x08, KEY_7), + KEYMAP(0x09, KEY_8), + KEYMAP(0x0a, KEY_9), + KEYMAP(0x0b, KEY_0), + KEYMAP(0x0c, KEY_MINUS), + KEYMAP(0x0d, KEY_EQUAL), + KEYMAP(0x0e, KEY_BACKSPACE), + /* Row-2 */ + KEYMAP(0x0f, KEY_TAB), + KEYMAP(0x10, KEY_Q), + KEYMAP(0x11, KEY_W), + KEYMAP(0x12, KEY_E), + KEYMAP(0x13, KEY_R), + KEYMAP(0x14, KEY_T), + KEYMAP(0x15, KEY_Y), + KEYMAP(0x16, KEY_U), + KEYMAP(0x17, KEY_I), + KEYMAP(0x18, KEY_O), + KEYMAP(0x19, KEY_P), + KEYMAP(0x1a, KEY_LEFTBRACE), + KEYMAP(0x1b, KEY_RIGHTBRACE), + KEYMAP(0x2b, KEY_BACKSLASH), + /* Row-3 */ + KEYMAP(0xdb, KEY_LEFTMETA), + KEYMAP(0x1e, KEY_A), + KEYMAP(0x1f, KEY_S), + KEYMAP(0x20, KEY_D), + KEYMAP(0x21, KEY_F), + KEYMAP(0x22, KEY_G), + KEYMAP(0x23, KEY_H), + KEYMAP(0x24, KEY_J), + KEYMAP(0x25, KEY_K), + KEYMAP(0x26, KEY_L), + KEYMAP(0x27, KEY_SEMICOLON), + KEYMAP(0x28, KEY_APOSTROPHE), + KEYMAP(0x1c, KEY_ENTER), + /* Row-4 */ + KEYMAP(0x2a, KEY_LEFTSHIFT), + KEYMAP(0x2c, KEY_Z), + KEYMAP(0x2d, KEY_X), + KEYMAP(0x2e, KEY_C), + KEYMAP(0x2f, KEY_V), + KEYMAP(0x30, KEY_B), + KEYMAP(0x31, KEY_N), + KEYMAP(0x32, KEY_M), + KEYMAP(0x33, KEY_COMMA), + KEYMAP(0x34, KEY_DOT), + KEYMAP(0x35, KEY_SLASH), + KEYMAP(0x36, KEY_RIGHTSHIFT), + /* Row-5 */ + KEYMAP(0x1d, KEY_LEFTCTRL), + KEYMAP(0x38, KEY_LEFTALT), + KEYMAP(0x39, KEY_SPACE), + KEYMAP(0xb8, KEY_RIGHTALT), + KEYMAP(0x9d, KEY_RIGHTCTRL), + /* Arrow keys */ + KEYMAP(0xcb, KEY_LEFT), + KEYMAP(0xd0, KEY_DOWN), + KEYMAP(0xcd, KEY_RIGHT), + KEYMAP(0xc8, KEY_UP), +}; + +static void ssdt_generate_physmap(struct acpi_dp *dp, uint8_t num_top_row_keys, + enum ps2_action_key action_keys[]) +{ + struct acpi_dp *dp_array; + enum ps2_action_key key; + uint32_t keymap, i; + + dp_array = acpi_dp_new_table("function-row-physmap"); + if (!dp_array) { + printk(BIOS_ERR, "PS2K: couldn't write function-row-physmap\n"); + return; + } + + printk(BIOS_INFO, "PS2K: Physmap: ["); + for (i = 0; i < num_top_row_keys; i++) { + key = action_keys[i]; + if (key && key < ARRAY_SIZE(action_keymaps)) { + keymap = action_keymaps[key]; + } else { + keymap = 0; + printk(BIOS_ERR, + "PS2K: invalid top-action-key-%u: %u(skipped)\n", + i, key); + } + acpi_dp_add_integer(dp_array, NULL, SCANCODE(keymap)); + printk(BIOS_INFO, " %X", SCANCODE(keymap)); + } + + printk(BIOS_INFO, " ]\n"); + acpi_dp_add_array(dp, dp_array); +} + +static void ssdt_generate_keymap(struct acpi_dp *dp, uint8_t num_top_row_keys, + enum ps2_action_key action_keys[], + bool can_send_function_keys, + bool has_numeric_keypad, + bool has_scrnlock_key) +{ + struct acpi_dp *dp_array; + enum ps2_action_key key; + uint32_t keymap; + unsigned int i, total = 0; + + dp_array = acpi_dp_new_table("linux,keymap"); + if (!dp_array) { + printk(BIOS_ERR, "PS2K: couldn't write linux,keymap\n"); + return; + } + + /* Write out keymap for top row action keys */ + for (i = 0; i < num_top_row_keys; i++) { + key = action_keys[i]; + if (!key || key >= ARRAY_SIZE(action_keymaps)) { + printk(BIOS_ERR, + "PS2K: invalid top-action-key-%u: %u\n", i, key); + continue; + } + keymap = action_keymaps[key]; + acpi_dp_add_integer(dp_array, NULL, keymap); + total++; + } + + /* Write out keymap for function keys, if keyboard can send them */ + if (can_send_function_keys) { + for (i = 0; i < num_top_row_keys; i++) { + keymap = function_keymaps[i]; + acpi_dp_add_integer(dp_array, NULL, keymap); + } + + total += num_top_row_keys; + } + + /* Write out keymap for numeric keypad, if the keyboard has it */ + if (has_numeric_keypad) { + for (i = 0; i < ARRAY_SIZE(numeric_keypad_keymaps); i++) { + keymap = numeric_keypad_keymaps[i]; + acpi_dp_add_integer(dp_array, NULL, keymap); + } + + total += ARRAY_SIZE(numeric_keypad_keymaps); + } + + /* Provide keymap for screenlock only if it is present */ + if (has_scrnlock_key) { + acpi_dp_add_integer(dp_array, NULL, KEYMAP(0x5d, KEY_SLEEP)); + total++; + } + + /* Write out keymap for rest of keys */ + for (i = 0; i < ARRAY_SIZE(rest_of_keymaps); i++) { + keymap = rest_of_keymaps[i]; + acpi_dp_add_integer(dp_array, NULL, keymap); + } + + total += ARRAY_SIZE(rest_of_keymaps); + printk(BIOS_INFO, "PS2K: Passing %u keymaps to kernel\n", total); + + acpi_dp_add_array(dp, dp_array); +} + +void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, + enum ps2_action_key action_keys[], + bool can_send_function_keys, + bool has_numeric_keypad, + bool has_scrnlock_key) +{ + struct acpi_dp *dsd; + + if (!scope || + num_top_row_keys < PS2_MIN_TOP_ROW_KEYS || + num_top_row_keys > PS2_MAX_TOP_ROW_KEYS) { + printk(BIOS_ERR, "PS2K: %s: invalid args\n", __func__); + return; + } + + dsd = acpi_dp_new_table("_DSD"); + if (!dsd) { + printk(BIOS_ERR, "PS2K: couldn't write _DSD\n"); + return; + } + + acpigen_write_scope(scope); + ssdt_generate_physmap(dsd, num_top_row_keys, action_keys); + ssdt_generate_keymap(dsd, num_top_row_keys, action_keys, + can_send_function_keys, has_numeric_keypad, + has_scrnlock_key); + acpi_dp_write(dsd); + acpigen_pop_len(); /* Scope */ +} diff --git a/src/arch/x86/include/arch/acpigen_ps2_keybd.h b/src/arch/x86/include/arch/acpigen_ps2_keybd.h new file mode 100644 index 0000000000..c0228bca16 --- /dev/null +++ b/src/arch/x86/include/arch/acpigen_ps2_keybd.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __ACPIGEN_PS2_KEYBD_H__ +#define __ACPIGEN_PS2_KEYBD_H__ + +#include + +enum ps2_action_key { + PS2_KEY_ABSENT = 0, + PS2_KEY_BACK, + PS2_KEY_FORWARD, + PS2_KEY_REFRESH, + PS2_KEY_FULLSCREEN, + PS2_KEY_OVERVIEW, + PS2_KEY_BRIGHTNESS_DOWN, + PS2_KEY_BRIGHTNESS_UP, + PS2_KEY_VOL_MUTE, + PS2_KEY_VOL_DOWN, + PS2_KEY_VOL_UP, + PS2_KEY_SNAPSHOT, + PS2_KEY_PRIVACY_SCRN_TOGGLE, + PS2_KEY_KBD_BKLIGHT_DOWN, + PS2_KEY_KBD_BKLIGHT_UP, + PS2_KEY_PLAY_PAUSE, + PS2_KEY_NEXT_TRACK, + PS2_KEY_PREV_TRACK, +}; + +#define PS2_MIN_TOP_ROW_KEYS 10 +#define PS2_MAX_TOP_ROW_KEYS 15 + +void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, + enum ps2_action_key action_keys[], + bool can_send_function_keys, + bool has_numeric_keypad, bool has_scrnlock_key); + +#endif /* __ACPIGEN_PS2_KEYBD_H__ */ From 89eef55718e6eb9164dfedae7ce11d6250a4bc5a Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Fri, 10 Apr 2020 15:48:49 -0700 Subject: [PATCH 1105/1463] google/chromeec: Add wrapper for EC_CMD_GET_KEYBD_CONFIG Add a wrapper command for the subject command Signed-off-by: Rajat Jain Change-Id: I29a4021c2ea0d1cbb4a72f56bf2232d8f9c80ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40313 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/ec/google/chromeec/ec.c | 18 ++++++++++++++++++ src/ec/google/chromeec/ec.h | 8 ++++++++ 2 files changed, 26 insertions(+) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 73baec63be..1c1f42ec62 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1518,3 +1518,21 @@ int google_chromeec_wait_for_displayport(long timeout) return 1; } + +int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) +{ + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_KEYBD_CONFIG, + .cmd_version = 0, + .cmd_data_in = NULL, + .cmd_size_in = 0, + .cmd_data_out = keybd, + .cmd_size_out = sizeof(*keybd), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 64d7e52981..5f84722ac7 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -330,6 +330,14 @@ struct usb_pd_port_caps { int google_chromeec_get_pd_port_caps(int port, struct usb_pd_port_caps *port_caps); +/** + * Get the keyboard configuration / layout information from EC + * + * @param *keybd If successful, this is filled with EC filled parameters + * @return 0 on success, -1 on error + */ +int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT From 962c788861dc4d36d9e3d7a3c238e746e7dc146f Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 1 Apr 2020 17:24:28 -0700 Subject: [PATCH 1106/1463] ec/google/chromeec: Fill up SSDT for EC provided PS2 keyboard Query the EC to get the top row layout, and if it provides one, generate the SSDT for the PS2 keyboard. Signed-off-by: Rajat Jain Change-Id: I75d2eee32c82b9bee73436b08b5f615d1b388148 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40032 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec_acpi.c | 65 ++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 8 deletions(-) diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 6bc9693881..a7e3ae559d 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -178,14 +179,19 @@ static void add_usb_port_references(struct acpi_dp *dsd, int port_number) } } -static void fill_ssdt_typec_device(int num_ports) +static void fill_ssdt_typec_device(struct device *dev) { struct usb_pd_port_caps port_caps; char con_name[] = "CONx"; struct acpi_dp *dsd; int rv; - int i; + int i, num_ports; + if (google_chromeec_get_num_pd_ports(&num_ports)) + return; + + /* Add TypeC device under the existing device + ".CREC" scope */ + acpigen_write_scope(acpi_device_path_join(dev, GOOGLE_CHROMEEC_USBC_DEVICE_PARENT)); acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " @@ -212,16 +218,59 @@ static void fill_ssdt_typec_device(int num_ports) } acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ + acpigen_pop_len(); /* Scope */ +} + +static const enum ps2_action_key ps2_enum_val[] = { + [TK_ABSENT] = PS2_KEY_ABSENT, + [TK_BACK] = PS2_KEY_BACK, + [TK_FORWARD] = PS2_KEY_FORWARD, + [TK_REFRESH] = PS2_KEY_REFRESH, + [TK_FULLSCREEN] = PS2_KEY_FULLSCREEN, + [TK_OVERVIEW] = PS2_KEY_OVERVIEW, + [TK_BRIGHTNESS_DOWN] = PS2_KEY_BRIGHTNESS_DOWN, + [TK_BRIGHTNESS_UP] = PS2_KEY_BRIGHTNESS_UP, + [TK_VOL_MUTE] = PS2_KEY_VOL_MUTE, + [TK_VOL_DOWN] = PS2_KEY_VOL_DOWN, + [TK_VOL_UP] = PS2_KEY_VOL_UP, + [TK_SNAPSHOT] = PS2_KEY_SNAPSHOT, + [TK_PRIVACY_SCRN_TOGGLE] = PS2_KEY_PRIVACY_SCRN_TOGGLE, + [TK_KBD_BKLIGHT_DOWN] = PS2_KEY_KBD_BKLIGHT_DOWN, + [TK_KBD_BKLIGHT_UP] = PS2_KEY_KBD_BKLIGHT_UP, + [TK_PLAY_PAUSE] = PS2_KEY_PLAY_PAUSE, + [TK_NEXT_TRACK] = PS2_KEY_NEXT_TRACK, + [TK_PREV_TRACK] = PS2_KEY_PREV_TRACK, +}; + +static void fill_ssdt_ps2_keyboard(struct device *dev) +{ + uint8_t i; + struct ec_response_keybd_config keybd = {}; + enum ps2_action_key ps2_action_keys[MAX_TOP_ROW_KEYS] = {}; + + if (google_chromeec_get_keybd_config(&keybd) || + !keybd.num_top_row_keys || + keybd.num_top_row_keys > MAX_TOP_ROW_KEYS) { + printk(BIOS_ERR, "PS2K: Bad resp from EC. Vivaldi disabled!\n"); + return; + } + + /* Convert enum action_key values to enum ps2_action_key values */ + for (i = 0; i < keybd.num_top_row_keys; i++) + ps2_action_keys[i] = ps2_enum_val[keybd.action_keys[i]]; + + acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", keybd.num_top_row_keys, + ps2_action_keys, + !!(keybd.capabilities & KEYBD_CAP_FUNCTION_KEYS), + !!(keybd.capabilities & KEYBD_CAP_NUMERIC_KEYPAD), + !!(keybd.capabilities & KEYBD_CAP_SCRNLOCK_KEY)); } void google_chromeec_fill_ssdt_generator(struct device *dev) { - int num_ports; - if (google_chromeec_get_num_pd_ports(&num_ports)) + if (!dev->enabled) return; - /* Add TypeC device under the existing device + ".CREC" scope */ - acpigen_write_scope(acpi_device_path_join(dev, GOOGLE_CHROMEEC_USBC_DEVICE_PARENT)); - fill_ssdt_typec_device(num_ports); - acpigen_pop_len(); /* Scope */ + fill_ssdt_typec_device(dev); + fill_ssdt_ps2_keyboard(dev); } From c5028b2e86fa58c7c7a5e1e47e8654b79a0c0e0c Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Mon, 20 Apr 2020 13:53:47 +1000 Subject: [PATCH 1107/1463] mb/google/puff: configure USB PLD groups Each physical port should have the same group and position for both USB2 and USB3, but puff and its variants use different layout than the baseboard so they must override PLD. Ports are split into two groups for front and back, with positions in each group numbered from left to right. BUG=b:151579409 BRANCH=none TEST=PLD_GroupToken and PLD_GroupPosition are set as expected in SSDT. Change-Id: Ibe19e4faa1fbc7117687d789e9bd5584852a48c0 Signed-off-by: Peter Marheine Reviewed-on: https://review.coreboot.org/c/coreboot/+/40516 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Paul Menzel --- .../google/hatch/variants/duffy/overridetree.cb | 12 ++++++++++++ .../google/hatch/variants/kaisa/overridetree.cb | 12 ++++++++++++ .../google/hatch/variants/puff/overridetree.cb | 12 ++++++++++++ 3 files changed, 36 insertions(+) diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 3507e6d5eb..2f36bc8b62 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -191,31 +191,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 2.0 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 2.1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 2.2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 2.3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Middle"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 2.4 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 2.5 on end end chip drivers/usb/acpi @@ -224,31 +230,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 3.0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 3.1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 3.2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 3.3 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 3.4 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Middle"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.5 on end end end diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index e09d0c4897..db05302278 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -191,31 +191,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 2.0 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 2.1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 2.2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 2.3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Middle"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 2.4 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 2.5 on end end chip drivers/usb/acpi @@ -224,31 +230,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 3.0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 3.1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 3.2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 3.3 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 3.4 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Middle"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.5 on end end end diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 3507e6d5eb..2f36bc8b62 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -191,31 +191,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 2.0 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 2.1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 2.2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Right"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 2.3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Middle"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 2.4 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Left"" register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 2.5 on end end chip drivers/usb/acpi @@ -224,31 +230,37 @@ chip soc/intel/cannonlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" device usb 3.0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" device usb 3.1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Right"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 3.2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Rear"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" device usb 3.3 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Left"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 3.4 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Middle"" register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.5 on end end end From aa832c19b2c3e4f1be6b917abd962a7d664be7a3 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Fri, 27 Mar 2020 17:38:15 +0530 Subject: [PATCH 1108/1463] mb/intel/jasperlake_rvp: Configure WWAN GPIOs M.2 WWAN interface has GPIOs which requires coreboot to configure all related GPIOs as per board schematics. BUG=None BRANCH=None TEST=code compiles and WWAN device is detected in OS Change-Id: I8ad978a619b50e16ad754177f1eb05cf7670b79f Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39877 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik --- .../jasperlake_rvp/variants/jslrvp/gpio.c | 29 +++++++++++++------ 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 726417a8cc..744a299af9 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -9,7 +9,18 @@ static const struct pad_config gpio_table[] = { /* ToDo: Fill other gpio configuration */ - /* Audio related GPIOs */ + /* WWAN_WAKE_N */ + PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT), + + /* M.2_WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_A19, 1, PLTRST), + + /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_C0, 0, PLTRST), + + /* M2_WWAN_SSD_SKT2_CFG2 */ + PAD_CFG_GPI(GPP_C3, NONE, PLTRST), + /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_2K, DEEP, NF1), @@ -19,14 +30,11 @@ static const struct pad_config gpio_table[] = { /* I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), - /* SD_CD# */ - PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), + /* WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), - /* SD_WP */ - PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), - - /* virtual GPIO for SD card detect */ - PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP), + /* WWAN EN GPIO */ + PAD_CFG_GPO(GPP_H7, 1, PLTRST), /* I2S1_SCLK */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), @@ -55,6 +63,9 @@ static const struct pad_config gpio_table[] = { /* I2S1_TXD */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + /* WWAN RST_N */ + PAD_CFG_GPO(GPP_S0, 1, DEEP), + /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_S2, UP_20K, DEEP, NF2), @@ -71,7 +82,7 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* ToDo: Fill early gpio configurations for TPM and WWAN */ + /* ToDo: Fill early gpio configurations for TPM */ }; const struct pad_config *variant_gpio_table(size_t *num) From ef5ff0b49a5d61b8dfc313fdddba3f07e3f7a8fc Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Mon, 30 Mar 2020 20:15:01 +0530 Subject: [PATCH 1109/1463] mb/intel/jasperlake_rvp: Enable Wifi and BT Enable Wifi and Bluetooth for Jasper Lake RVP with following changes: 1. Enable related pci root ports for WLAN and BT 2. Disable unused root ports and clkreq for unused clocks 3. Configure GPIOs properly for M.2 port BUG=None BRANCH=None TEST=Code compiles and able to detect Wifi/BT module on board. Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933 Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik Reviewed-by: Ronak Kanabar Tested-by: build bot (Jenkins) --- .../variants/jslrvp/devicetree.cb | 25 ++++++++----------- .../jasperlake_rvp/variants/jslrvp/gpio.c | 18 +++++++++++++ 2 files changed, 29 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index b632b7804c..7dc45ae520 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -63,22 +63,19 @@ chip soc/intel/jasperlake register "PchHdaAudioLinkDmicEnable[1]" = "1" # PCIe port 1 for M.2 E-key WLAN - register "PcieRpEnable[1]" = "1" - - # RP 1 uses CLK SRC 1 - register "PcieClkSrcUsage[1]" = "0x01" - - # ClkReq-to-ClkSrc mapping for CLK SRC 1 - register "PcieClkSrcClkReq[1]" = "0x01" - # Enable Root Port 4(x4) for NVMe + register "PcieRpEnable[1]" = "1" register "PcieRpEnable[4]" = "1" - # RP 4 uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "0x04" + register "PcieClkSrcUsage[1]" = "0x01" - # ClkReq-to-ClkSrc mapping for CLK SRC 0 register "PcieClkSrcClkReq[0]" = "0x00" + register "PcieClkSrcClkReq[1]" = "0x01" + register "PcieClkSrcClkReq[2]" = "0x02" + register "PcieClkSrcClkReq[3]" = "0x03" + register "PcieClkSrcClkReq[4]" = "0x04" + register "PcieClkSrcClkReq[5]" = "0x05" register "SataEnable" = "0" @@ -285,12 +282,12 @@ chip soc/intel/jasperlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 744a299af9..68f57ffd60 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -15,6 +15,9 @@ static const struct pad_config gpio_table[] = { /* M.2_WWAN_DISABLE_N */ PAD_CFG_GPO(GPP_A19, 1, PLTRST), + /* M.2_WLAN_PERST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + /* WWAN_PERST_N */ PAD_CFG_GPO(GPP_C0, 0, PLTRST), @@ -27,6 +30,12 @@ static const struct pad_config gpio_table[] = { /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_2K, DEEP, NF1), + /* WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_D0, 1, PLTRST), + + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + /* I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), @@ -36,12 +45,21 @@ static const struct pad_config gpio_table[] = { /* WWAN EN GPIO */ PAD_CFG_GPO(GPP_H7, 1, PLTRST), + /* M.2_BT_I2S2_SCLK */ + PAD_CFG_GPI(GPP_H11, NONE, PLTRST), + + /* M.2_BT_I2S2_RXD */ + PAD_CFG_GPI(GPP_H14, NONE, PLTRST), + /* I2S1_SCLK */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* Audio Jack Detection */ PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, EDGE_BOTH), + /* M2_CNVI_EN_N */ + PAD_CFG_GPO(GPP_H19, 0, PLTRST), + /* I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), From 9d25207aaf93cb8052910f11fc1febd7865fb6e9 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 3 Apr 2020 21:37:27 +0530 Subject: [PATCH 1110/1463] sc7180: clock: Define the UART frequency for QUPV3 The frequency to be used by UART client is 7.3728MHz, thus define it in the clock header to be used by the driver. Tested: UART frequency request by client driver. Change-Id: I1ced350fe9826ea05b03ffc11aced2c21fe85c9e Signed-off-by: Taniya Das Reviewed-on: https://review.coreboot.org/c/coreboot/+/40329 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/clock.c | 2 +- src/soc/qualcomm/sc7180/include/soc/clock.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index b6b6d46061..56185eec8a 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -22,7 +22,7 @@ struct clock_config qup_cfg[] = { { - .hz = 7372800, + .hz = QUPV3_UART_SRC_HZ, .src = SRC_GPLL0_EVEN_300MHZ, .div = DIV(1), .m = 384, diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 2a8af28858..25903fb42c 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -32,6 +32,7 @@ #define SRC_XO_HZ (19200 * KHz) #define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_MAIN_HZ (600 * MHz) +#define QUPV3_UART_SRC_HZ 7372800 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1 From cea0d9c0ffc06359b01310c0dd728b4527c0013d Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Wed, 27 Nov 2019 19:28:23 -0800 Subject: [PATCH 1111/1463] sc7180: Add QUPv3 FW load & config UART driver requires firmware loading Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25372/78 https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Signed-off-by: Roja Rani Yarubandi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35499 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/Makefile.inc | 4 + src/soc/qualcomm/sc7180/bootblock.c | 2 + .../qualcomm/sc7180/include/soc/addressmap.h | 21 + .../qualcomm/sc7180/include/soc/qcom_qup_se.h | 467 ++++++++++++++++++ .../sc7180/include/soc/qupv3_config.h | 80 +++ src/soc/qualcomm/sc7180/qcom_qup_se.c | 258 ++++++++++ src/soc/qualcomm/sc7180/qupv3_config.c | 219 ++++++++ 7 files changed, 1051 insertions(+) create mode 100644 src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h create mode 100644 src/soc/qualcomm/sc7180/include/soc/qupv3_config.h create mode 100644 src/soc/qualcomm/sc7180/qcom_qup_se.c create mode 100644 src/soc/qualcomm/sc7180/qupv3_config.c diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 5f4dc1d756..554efd8801 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -10,6 +10,8 @@ bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c bootblock-$(CONFIG_SC7180_QSPI) += qspi.c +bootblock-y += qupv3_config.c +bootblock-y += qcom_qup_se.c ################################################################################ verstage-y += timer.c @@ -43,6 +45,8 @@ ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c ramstage-y += usb.c +ramstage-y += qupv3_config.c +ramstage-y += qcom_qup_se.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 29348c2a24..9cecb4f4f5 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -16,10 +16,12 @@ #include #include #include +#include void bootblock_soc_init(void) { sc7180_mmu_init(); clock_init(); quadspi_init(25 * MHz); + qupv3_fw_init(); } diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 5ca34a6380..6ce7b9b185 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -24,6 +24,27 @@ #define TLMM_SOUTH_TILE_BASE 0x03D00000 #define TLMM_WEST_TILE_BASE 0x03500000 +/* + * QUP SERIAL ENGINE BASE ADDRESSES + */ +/* QUPV3_0 */ +#define QUP_SERIAL0_BASE 0x00880000 +#define QUP_SERIAL1_BASE 0x00884000 +#define QUP_SERIAL2_BASE 0x00888000 +#define QUP_SERIAL3_BASE 0x0088C000 +#define QUP_SERIAL4_BASE 0x00890000 +#define QUP_SERIAL5_BASE 0x00894000 +#define QUP_WRAP0_BASE 0x008C0000 + +/* QUPV3_1 */ +#define QUP_SERIAL6_BASE 0x00A80000 +#define QUP_SERIAL7_BASE 0x00A84000 +#define QUP_SERIAL8_BASE 0x00A88000 +#define QUP_SERIAL9_BASE 0x00A8C000 +#define QUP_SERIAL10_BASE 0x00A90000 +#define QUP_SERIAL11_BASE 0x00A94000 +#define QUP_WRAP1_BASE 0x00AC0000 + /* * USB BASE ADDRESSES */ diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h new file mode 100644 index 0000000000..051af9c0b0 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -0,0 +1,467 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QCOM_QUP_SE_H__ +#define __SOC_QCOM_QUP_SE_H__ + +#include +#include +#include +#include +#include +#include + +#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) + +/* GENI_OUTPUT_CTRL fields */ +#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) + +/* GENI_FORCE_DEFAULT_REG fields */ +#define FORCE_DEFAULT BIT(0) + +#define GENI_FW_REVISION_RO_PROTOCOL_MASK 0x0000FF00 +#define GENI_FW_REVISION_RO_PROTOCOL_SHIFT 0x00000008 + +/* GENI_CGC_CTRL fields */ +#define CFG_AHB_CLK_CGC_ON BIT(0) +#define CFG_AHB_WR_ACLK_CGC_ON BIT(1) +#define DATA_AHB_CLK_CGC_ON BIT(2) +#define SCLK_CGC_ON BIT(3) +#define TX_CLK_CGC_ON BIT(4) +#define RX_CLK_CGC_ON BIT(5) +#define EXT_CLK_CGC_ON BIT(6) +#define PROG_RAM_HCLK_OFF BIT(8) +#define PROG_RAM_SCLK_OFF BIT(9) +#define DEFAULT_CGC_EN (CFG_AHB_CLK_CGC_ON | CFG_AHB_WR_ACLK_CGC_ON \ + | DATA_AHB_CLK_CGC_ON | SCLK_CGC_ON \ + | TX_CLK_CGC_ON | RX_CLK_CGC_ON | EXT_CLK_CGC_ON) + +/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ +#define SER_CLK_EN BIT(0) +#define CLK_DIV_SHFT 4 +#define CLK_DIV_MSK (0xFFF << CLK_DIV_SHFT) + +/* FIFO_IF_DISABLE_RO fields */ +#define FIFO_IF_DISABLE BIT(0) + +/* FW_REVISION_RO fields */ +#define FW_REV_PROTOCOL_MSK GENMASK(15, 8) +#define FW_REV_PROTOCOL_SHFT 8 +#define FW_REV_VERSION_SHFT 0 + +/* GENI_CLK_SEL fields */ +#define CLK_SEL_MSK GENMASK(2, 0) + +/* SE_GENI_DMA_MODE_EN */ +#define GENI_DMA_MODE_EN BIT(0) + +/* GENI_M_CMD0 fields */ +#define M_OPCODE_MSK GENMASK(31, 27) +#define M_OPCODE_SHFT 27 +#define M_PARAMS_MSK GENMASK(26, 0) + +/* GENI_M_CMD_CTRL_REG */ +#define M_GENI_CMD_CANCEL BIT(2) +#define M_GENI_CMD_ABORT BIT(1) +#define M_GENI_DISABLE BIT(0) + +/* GENI_S_CMD0 fields */ +#define S_OPCODE_MSK GENMASK(31, 27) +#define S_OPCODE_SHFT 27 +#define S_PARAMS_MSK GENMASK(26, 0) + +/* GENI_S_CMD_CTRL_REG */ +#define S_GENI_CMD_CANCEL BIT(2) +#define S_GENI_CMD_ABORT BIT(1) +#define S_GENI_DISABLE BIT(0) + +/* GENI_M_IRQ_EN fields */ +#define M_CMD_DONE_EN BIT(0) +#define M_CMD_OVERRUN_EN BIT(1) +#define M_ILLEGAL_CMD_EN BIT(2) +#define M_CMD_FAILURE_EN BIT(3) +#define M_CMD_CANCEL_EN BIT(4) +#define M_CMD_ABORT_EN BIT(5) +#define M_TIMESTAMP_EN BIT(6) +#define M_RX_IRQ_EN BIT(7) +#define M_GP_SYNC_IRQ_0_EN BIT(8) +#define M_GP_IRQ_0_EN BIT(9) +#define M_GP_IRQ_1_EN BIT(10) +#define M_GP_IRQ_2_EN BIT(11) +#define M_GP_IRQ_3_EN BIT(12) +#define M_GP_IRQ_4_EN BIT(13) +#define M_GP_IRQ_5_EN BIT(14) +#define M_IO_DATA_DEASSERT_EN BIT(22) +#define M_IO_DATA_ASSERT_EN BIT(23) +#define M_RX_FIFO_RD_ERR_EN BIT(24) +#define M_RX_FIFO_WR_ERR_EN BIT(25) +#define M_RX_FIFO_WATERMARK_EN BIT(26) +#define M_RX_FIFO_LAST_EN BIT(27) +#define M_TX_FIFO_RD_ERR_EN BIT(28) +#define M_TX_FIFO_WR_ERR_EN BIT(29) +#define M_TX_FIFO_WATERMARK_EN BIT(30) +#define M_SEC_IRQ_EN BIT(31) +#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ + M_IO_DATA_DEASSERT_EN | \ + M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ + M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ + M_TX_FIFO_WR_ERR_EN) + +/* GENI_S_IRQ_EN fields */ +#define S_CMD_DONE_EN BIT(0) +#define S_CMD_OVERRUN_EN BIT(1) +#define S_ILLEGAL_CMD_EN BIT(2) +#define S_CMD_FAILURE_EN BIT(3) +#define S_CMD_CANCEL_EN BIT(4) +#define S_CMD_ABORT_EN BIT(5) +#define S_GP_SYNC_IRQ_0_EN BIT(8) +#define S_GP_IRQ_0_EN BIT(9) +#define S_GP_IRQ_1_EN BIT(10) +#define S_GP_IRQ_2_EN BIT(11) +#define S_GP_IRQ_3_EN BIT(12) +#define S_GP_IRQ_4_EN BIT(13) +#define S_GP_IRQ_5_EN BIT(14) +#define S_IO_DATA_DEASSERT_EN BIT(22) +#define S_IO_DATA_ASSERT_EN BIT(23) +#define S_RX_FIFO_RD_ERR_EN BIT(24) +#define S_RX_FIFO_WR_ERR_EN BIT(25) +#define S_RX_FIFO_WATERMARK_EN BIT(26) +#define S_RX_FIFO_LAST_EN BIT(27) +#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ + S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) + +/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ +#define WATERMARK_MSK GENMASK(5, 0) + +/* GENI_TX_FIFO_STATUS fields */ +#define TX_FIFO_WC GENMASK(27, 0) + +/* GENI_RX_FIFO_STATUS fields */ +#define RX_LAST BIT(31) +#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) +#define RX_LAST_BYTE_VALID_SHFT 28 +#define RX_FIFO_WC_MSK GENMASK(24, 0) + +/* SE_IRQ_EN fields */ +#define DMA_RX_IRQ_EN BIT(0) +#define DMA_TX_IRQ_EN BIT(1) +#define GENI_M_IRQ_EN BIT(2) +#define GENI_S_IRQ_EN BIT(3) + +/* SE_DMA_GENERAL_CFG */ +#define DMA_RX_CLK_CGC_ON BIT(0) +#define DMA_TX_CLK_CGC_ON BIT(1) +#define DMA_AHB_SLV_CFG_ON BIT(2) +#define AHB_SEC_SLV_CLK_CGC_ON BIT(3) +#define DUMMY_RX_NON_BUFFERABLE BIT(4) +#define RX_DMA_ZERO_PADDING_EN BIT(5) +#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) +#define RX_DMA_IRQ_DELAY_SHFT 6 + +#define DEFAULT_SE_CLK (19200 * KHz) +#define GENI_DFS_IF_CFG_DFS_IF_EN_BMSK BIT(0) + +/* FIFO BUFFER PARAMETERS */ +#define BYTES_PER_FIFO_WORD 4 +#define FIFO_WIDTH 32 +#define FIFO_DEPTH 16 +#define BITS_PER_WORD 8 +#define TX_WATERMARK 1 + +/* PACKING CONFIGURATION VECTOR */ + +/* start_idx:x: Bit position to move + * direction:1: MSB to LSB + * len:7: Represents bits-per-word = 8 + * stop:0: Till it's 1, FIFO bit shift continues + */ + +/* Start_idx:7, direction:1, len:7, stop:0 */ +#define PACK_VECTOR0 0x0FE +/* Start_idx:15, direction:1, len:7, stop:0 */ +#define PACK_VECTOR1 0x1FE +/* Start_idx:23, direction:1, len:7, stop:0 */ +#define PACK_VECTOR2 0x2FE +/* Start_idx:31, direction:1, len:7, stop:1 */ +#define PACK_VECTOR3 0x3FF + +enum qup_se { + QUPV3_0_SE0, + QUPV3_0_SE1, + QUPV3_0_SE2, + QUPV3_0_SE3, + QUPV3_0_SE4, + QUPV3_0_SE5, + QUPV3_1_SE0, + QUPV3_1_SE1, + QUPV3_1_SE2, + QUPV3_1_SE3, + QUPV3_1_SE4, + QUPV3_1_SE5, + QUPV3_SE_MAX, +}; + +enum se_protocol { + SE_PROTOCOL_SPI = 1, + SE_PROTOCOL_UART = 2, + SE_PROTOCOL_I2C = 3, + SE_PROTOCOL_I3C = 4, + SE_PROTOCOL_MAX = 5 +}; + +enum se_mode { + NONE, + GSI, + FIFO, + CPU_DMA, + MIXED +}; + +struct qup_regs { + u32 geni_init_cfg_revision; + u32 geni_s_init_cfg_revision; + u8 _reserved1[0x10 - 0x08]; + u32 geni_general_cfg; + u32 geni_rx_fifo_ctrl; + u8 _reserved2[0x20 - 0x18]; + u32 geni_force_default_reg; + u32 geni_output_ctrl; + u32 geni_cgc_ctrl; + u32 geni_char_cfg; + u32 geni_char_data_n; + u8 _reserved3[0x40 - 0x34]; + u32 geni_status; + u32 geni_test_bus_ctrl; + u32 geni_ser_m_clk_cfg; + u32 geni_ser_s_clk_cfg; + u32 geni_prog_rom_ctrl_reg; + u8 _reserved4[0x60 - 0x54]; + u32 geni_clk_ctrl_ro; + u32 fifo_if_disable_ro; + u32 geni_fw_revision_ro; + u32 geni_s_fw_revision_ro; + u32 geni_fw_multilock_protns_ro; + u32 geni_fw_multilock_msa_ro; + u32 geni_fw_multilock_sp_ro; + u32 geni_clk_sel; + u32 geni_dfs_if_cfg; + u8 _reserved5[0x100 - 0x084]; + u32 geni_cfg_reg0; + u32 geni_cfg_reg1; + u32 geni_cfg_reg2; + u32 geni_cfg_reg3; + u32 geni_cfg_reg4; + u32 geni_cfg_reg5; + u32 geni_cfg_reg6; + u32 geni_cfg_reg7; + u32 geni_cfg_reg8; + u32 geni_cfg_reg9; + u32 geni_cfg_reg10; + u32 geni_cfg_reg11; + u32 geni_cfg_reg12; + u32 geni_cfg_reg13; + u32 geni_cfg_reg14; + u32 geni_cfg_reg15; + u32 geni_cfg_reg16; + u32 geni_cfg_reg17; + u32 geni_cfg_reg18; + u8 _reserved6[0x200 - 0x14C]; + u32 geni_cfg_reg64; + u32 geni_cfg_reg65; + u32 geni_cfg_reg66; + u32 geni_cfg_reg67; + u32 geni_cfg_reg68; + u32 geni_cfg_reg69; + u32 geni_cfg_reg70; + u32 geni_cfg_reg71; + u32 geni_cfg_reg72; + u32 spi_cpha; + u32 geni_cfg_reg74; + u32 proto_loopback_cfg; + u32 spi_cpol; + u32 i2c_noise_cancellation_ctl; + u32 i2c_monitor_ctl; + u32 geni_cfg_reg79; + u32 geni_cfg_reg80; + u32 geni_cfg_reg81; + u32 geni_cfg_reg82; + u32 spi_demux_output_inv; + u32 spi_demux_sel; + u32 geni_byte_granularity; + u32 geni_dma_mode_en; + u32 uart_tx_trans_cfg_reg; + u32 geni_tx_packing_cfg0; + u32 geni_tx_packing_cfg1; + union { + u32 uart_tx_word_len; + u32 spi_word_len; + }; + union { + u32 uart_tx_stop_bit_len; + u32 i2c_tx_trans_len; + u32 spi_tx_trans_len; + }; + union { + u32 uart_tx_trans_len; + u32 i2c_rx_trans_len; + u32 spi_rx_trans_len; + }; + u32 spi_pre_post_cmd_dly; + u32 i2c_scl_counters; + u32 geni_cfg_reg95; + u32 uart_rx_trans_cfg; + u32 geni_rx_packing_cfg0; + u32 geni_rx_packing_cfg1; + u32 uart_rx_word_len; + u32 geni_cfg_reg100; + u32 uart_rx_stale_cnt; + u32 geni_cfg_reg102; + u32 geni_cfg_reg103; + u32 geni_cfg_reg104; + u32 uart_tx_parity_cfg; + u32 uart_rx_parity_cfg; + u32 uart_manual_rfr; + u32 geni_cfg_reg108; + u32 geni_cfg_reg109; + u32 geni_cfg_reg110; + u8 _reserved7[0x600 - 0x2BC]; + u32 geni_m_cmd0; + u32 geni_m_cmd_ctrl_reg; + u8 _reserved8[0x10 - 0x08]; + u32 geni_m_irq_status; + u32 geni_m_irq_enable; + u32 geni_m_irq_clear; + u32 geni_m_irq_en_set; + u32 geni_m_irq_en_clear; + u32 geni_m_cmd_err_status; + u32 geni_m_fw_err_status; + u8 _reserved9[0x30 - 0x2C]; + u32 geni_s_cmd0; + u32 geni_s_cmd_ctrl_reg; + u8 _reserved10[0x40 - 0x38]; + u32 geni_s_irq_status; + u32 geni_s_irq_enable; + u32 geni_s_irq_clear; + u32 geni_s_irq_en_set; + u32 geni_s_irq_en_clear; + u8 _reserved11[0x700 - 0x654]; + u32 geni_tx_fifon; + u8 _reserved12[0x780 - 0x704]; + u32 geni_rx_fifon; + u8 _reserved13[0x800 - 0x784]; + u32 geni_tx_fifo_status; + u32 geni_rx_fifo_status; + u32 geni_tx_fifo_threshold; + u32 geni_tx_watermark_reg; + u32 geni_rx_watermark_reg; + u32 geni_rx_rfr_watermark_reg; + u8 _reserved14[0x900 - 0x818]; + u32 geni_gp_output_reg; + u8 _reserved15[0x908 - 0x904]; + u32 geni_ios; + u32 geni_timestamp; + u32 geni_m_gp_length; + u32 geni_s_gp_length; + u8 _reserved16[0x920 - 0x918]; + u32 geni_hw_irq_en; + u32 geni_hw_irq_ignore_on_active; + u8 _reserved17[0x930 - 0x928]; + u32 geni_hw_irq_cmd_param_0; + u8 _reserved18[0xA00 - 0x934]; + u32 geni_i3c_ibi_cfg_tablen; + u8 _reserved19[0xA80 - 0xA04]; + u32 geni_i3c_ibi_status; + u32 geni_i3c_ibi_rd_data; + u32 geni_i3c_ibi_search_pattern; + u32 geni_i3c_ibi_search_data; + u32 geni_i3c_sw_ibi_en; + u32 geni_i3c_sw_ibi_en_recover; + u8 _reserved20[0xC30 - 0xA98]; + u32 dma_tx_ptr_l; + u32 dma_tx_ptr_h; + u32 dma_tx_attr; + u32 dma_tx_length; + u32 dma_tx_irq_stat; + u32 dma_tx_irq_clr; + u32 dma_tx_irq_en; + u32 dma_tx_irq_en_set; + u32 dma_tx_irq_en_clr; + u32 dma_tx_length_in; + u32 dma_tx_fsm_rst; + u32 dma_tx_max_burst_size; + u8 _reserved21[0xD30 - 0xC60]; + u32 dma_rx_ptr_l; + u32 dma_rx_ptr_h; + u32 dma_rx_attr; + u32 dma_rx_length; + u32 dma_rx_irq_stat; + u32 dma_rx_irq_clr; + u32 dma_rx_irq_en; + u32 dma_rx_irq_en_set; + u32 dma_rx_irq_en_clr; + u32 dma_rx_length_in; + u32 dma_rx_fsm_rst; + u32 dma_rx_max_burst_size; + u32 dma_rx_flush; + u8 _reserved22[0xE14 - 0xD64]; + u32 se_irq_high_priority; + u32 se_gsi_event_en; + u32 se_irq_en; + u32 dma_if_en_ro; + u32 se_hw_param_0; + u32 se_hw_param_1; + u32 se_hw_param_2; + u32 dma_general_cfg; + u8 _reserved23[0x40 - 0x34]; + u32 dma_debug_reg0; + u32 dma_test_bus_ctrl; + u32 se_top_test_bus_ctrl; + u8 _reserved24[0x1000 - 0x0E4C]; + u32 se_geni_fw_revision; + u32 se_s_fw_revision; + u8 _reserved25[0x10-0x08]; + u32 se_geni_cfg_ramn; + u8 _reserved26[0x2000 - 0x1014]; + u32 se_geni_clk_ctrl; + u32 se_dma_if_en; + u32 se_fifo_if_disable; + u32 se_geni_fw_multilock_protns; + u32 se_geni_fw_multilock_msa; + u32 se_geni_fw_multilock_sp; +}; +check_member(qup_regs, geni_clk_sel, 0x7C); +check_member(qup_regs, geni_cfg_reg108, 0x2B0); +check_member(qup_regs, geni_dma_mode_en, 0x258); +check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84); +check_member(qup_regs, dma_test_bus_ctrl, 0xE44); +check_member(qup_regs, se_geni_cfg_ramn, 0x1010); +check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014); + +struct qup { + struct qup_regs *regs; + gpio_t pin[6]; + u8 func[6]; +}; + +extern struct qup qup[12]; + +u32 qup_wait_for_m_irq(unsigned int bus); +u32 qup_wait_for_s_irq(unsigned int bus); +void qup_m_cancel_and_abort(unsigned int bus); +void qup_s_cancel_and_abort(unsigned int bus); +int qup_handle_transfer(unsigned int bus, const void *dout, void *din, + int size); + +#endif /* __SOC_QCOM_QUP_SE_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h new file mode 100644 index 0000000000..b2a89a53c0 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SC7180_QUPV3_CONFIG_H_ +#define _SC7180_QUPV3_CONFIG_H_ + +#include +#include +#include +#include + +#define QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK 0x00000001 +#define QUPV3_SE_AHB_M_CFG_AHB_M_CLK_CGC_ON_BMSK 0x00000001 + +#define GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK 0x00000200 +#define GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK 0x00000100 + +#define GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK 0x00000001 + +#define DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008 +#define DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004 +#define DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001 + +#define DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK 0x00000010 +#define DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008 +#define DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004 +#define DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001 + +#define DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK 0x00000008 +#define DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK 0x00000004 +#define DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK 0x00000002 +#define DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK 0x00000001 + +#define GENI_CLK_CTRL_SER_CLK_SEL_BMSK 0x00000001 +#define DMA_IF_EN_DMA_IF_EN_BMSK 0x00000001 +#define SE_GSI_EVENT_EN_BMSK 0x0000000f +#define SE_IRQ_EN_RMSK 0x0000000f + +#define SIZE_GENI_FW_RAM 0x00000200 +#define MAX_OFFSET_CFG_REG 0x000001c0 +#define SEFW_MAGIC_HEADER 0x57464553 + +struct elf_se_hdr { + uint32_t magic; /* = 'SEFW' */ + uint32_t version; /* Structure version number */ + uint32_t core_version; /* QUPV3_HW_VERSION */ + uint16_t serial_protocol; /* Programmed into GENI_FW_REVISION */ + uint16_t fw_version; /* Programmed into GENI_FW_REVISION */ + uint16_t cfg_version; /* Programmed into GENI_INIT_CFG_REVISION */ + uint16_t fw_size_in_items; /* Number of (uint32_t) GENI_FW_RAM words */ + uint16_t fw_offset; /* Byte offset of GENI_FW_RAM array */ + uint16_t cfg_size_in_items;/* Number of GENI_FW_CFG index/value pairs */ + uint16_t cfg_idx_offset; /* Byte offset of GENI_FW_CFG index array */ + uint16_t cfg_val_offset; /* Byte offset of GENI_FW_CFG values array */ +}; + +struct qupv3_common_reg { + u8 reserved_1[0x118]; + u32 qupv3_se_ahb_m_cfg_reg; + u8 reserved_2[0x4]; + u32 qupv3_common_cfg_reg; +}; + +void qupv3_fw_init(void); +void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, + unsigned int mode); + +#endif /* _SC7180_QUPV3_CONFIG_H_ */ diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c new file mode 100644 index 0000000000..b6540a88cf --- /dev/null +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -0,0 +1,258 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +struct qup qup[12] = { + [0] = { .regs = (void *)QUP_SERIAL0_BASE, + .pin = { GPIO(34), GPIO(35), GPIO(36), GPIO(37) }, + .func = { GPIO34_FUNC_QUP0_L0, GPIO35_FUNC_QUP0_L1, + GPIO36_FUNC_QUP0_L2, GPIO37_FUNC_QUP0_L3 } + }, + [1] = { .regs = (void *)QUP_SERIAL1_BASE, + .pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3), + GPIO(12), GPIO(94) }, + .func = { GPIO0_FUNC_QUP0_L0, GPIO1_FUNC_QUP0_L1, + GPIO2_FUNC_QUP0_L2, GPIO3_FUNC_QUP0_L3, + GPIO12_FUNC_QUP0_L4, GPIO94_FUNC_QUP0_L5 } + }, + [2] = { .regs = (void *)QUP_SERIAL2_BASE, + .pin = { GPIO(15), GPIO(16) }, + .func = { GPIO15_FUNC_QUP0_L0, GPIO16_FUNC_QUP0_L1 } + }, + [3] = { .regs = (void *)QUP_SERIAL3_BASE, + .pin = { GPIO(38), GPIO(39), GPIO(40), GPIO(41) }, + .func = { GPIO38_FUNC_QUP0_L0, GPIO39_FUNC_QUP0_L1, + GPIO40_FUNC_QUP0_L2, GPIO41_FUNC_QUP0_L3 } + }, + [4] = { .regs = (void *)QUP_SERIAL4_BASE, + .pin = { GPIO(115), GPIO(116) }, + .func = { GPIO115_FUNC_QUP0_L0, GPIO116_FUNC_QUP0_L1 } + }, + [5] = { .regs = (void *)QUP_SERIAL5_BASE, + .pin = { GPIO(25), GPIO(26), GPIO(27), GPIO(28) }, + .func = { GPIO25_FUNC_QUP0_L0, GPIO26_FUNC_QUP0_L1, + GPIO27_FUNC_QUP0_L2, GPIO28_FUNC_QUP0_L3 } + }, + [6] = { .regs = (void *)QUP_SERIAL6_BASE, + .pin = { GPIO(59), GPIO(60), GPIO(61), GPIO(62), + GPIO(68), GPIO(72) }, + .func = { GPIO59_FUNC_QUP1_L0, GPIO60_FUNC_QUP1_L1, + GPIO61_FUNC_QUP1_L2, GPIO62_FUNC_QUP1_L3, + GPIO68_FUNC_QUP1_L4, GPIO72_FUNC_QUP1_L5 } + }, + [7] = { .regs = (void *)QUP_SERIAL7_BASE, + .pin = { GPIO(6), GPIO(7) }, + .func = { GPIO6_FUNC_QUP1_L0, GPIO7_FUNC_QUP1_L1 } + }, + [8] = { .regs = (void *)QUP_SERIAL8_BASE, + .pin = { GPIO(42), GPIO(43), GPIO(44), GPIO(45) }, + .func = { GPIO42_FUNC_QUP1_L0, GPIO43_FUNC_QUP1_L1, + GPIO44_FUNC_QUP1_L2, GPIO45_FUNC_QUP1_L3 } + }, + [9] = { .regs = (void *)QUP_SERIAL9_BASE, + .pin = { GPIO(46), GPIO(47) }, + .func = { GPIO46_FUNC_QUP1_L0, GPIO47_FUNC_QUP1_L1 } + }, + [10] = { .regs = (void *)QUP_SERIAL10_BASE, + .pin = { GPIO(86), GPIO(87), GPIO(88), GPIO(89), + GPIO(90), GPIO(91) }, + .func = { GPIO86_FUNC_QUP1_L0, GPIO87_FUNC_QUP1_L1, + GPIO88_FUNC_QUP1_L2, GPIO89_FUNC_QUP1_L3, + GPIO90_FUNC_QUP1_L4, GPIO91_FUNC_QUP1_L5 } + }, + [11] = { .regs = (void *)QUP_SERIAL11_BASE, + .pin = { GPIO(53), GPIO(54), GPIO(55), GPIO(56) }, + .func = { GPIO53_FUNC_QUP1_L0, GPIO54_FUNC_QUP1_L1, + GPIO55_FUNC_QUP1_L2, GPIO56_FUNC_QUP1_L3 } + }, +}; + +u32 qup_wait_for_m_irq(unsigned int bus) +{ + struct stopwatch sw; + unsigned int m_irq = 0; + struct qup_regs *regs = qup[bus].regs; + + stopwatch_init_usecs_expire(&sw, 25); + while (!stopwatch_expired(&sw)) { + m_irq = read32(®s->geni_m_irq_status); + if (m_irq) + break; + } + return m_irq; +} + +u32 qup_wait_for_s_irq(unsigned int bus) +{ + struct stopwatch sw; + unsigned int s_irq = 0; + struct qup_regs *regs = qup[bus].regs; + + stopwatch_init_usecs_expire(&sw, 25); + while (!stopwatch_expired(&sw)) { + s_irq = read32(®s->geni_s_irq_status); + if (s_irq) + break; + } + return s_irq; +} + +static int handle_tx(unsigned int bus, const u8 *dout, + unsigned int tx_rem_bytes) +{ + int max_bytes = 0; + struct qup_regs *regs = qup[bus].regs; + + max_bytes = (FIFO_DEPTH - TX_WATERMARK) * BYTES_PER_FIFO_WORD; + max_bytes = MIN(tx_rem_bytes, max_bytes); + + buffer_to_fifo32((void *)dout, max_bytes, ®s->geni_tx_fifon, + 0, BYTES_PER_FIFO_WORD); + + if (tx_rem_bytes == max_bytes) + write32(®s->geni_tx_watermark_reg, 0); + return max_bytes; +} + +static int handle_rx(unsigned int bus, u8 *din, unsigned int rx_rem_bytes) +{ + struct qup_regs *regs = qup[bus].regs; + u32 rx_fifo_status = read32(®s->geni_rx_fifo_status); + int rx_bytes = 0; + + rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * BYTES_PER_FIFO_WORD; + rx_bytes = MIN(rx_rem_bytes, rx_bytes); + + buffer_from_fifo32(din, rx_bytes, ®s->geni_rx_fifon, + 0, BYTES_PER_FIFO_WORD); + return rx_bytes; +} + +void qup_m_cancel_and_abort(unsigned int bus) +{ + struct qup_regs *regs = qup[bus].regs; + struct stopwatch sw; + unsigned int m_irq; + + write32(®s->geni_tx_watermark_reg, 0); + write32(®s->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL); + + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_m_irq(bus); + if (m_irq & M_CMD_CANCEL_EN) { + write32(®s->geni_m_irq_clear, m_irq); + break; + } + write32(®s->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_CANCEL_EN)) { + printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n", + __func__); + + write32(®s->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT); + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_m_irq(bus); + if (m_irq & M_CMD_ABORT_EN) { + write32(®s->geni_m_irq_clear, m_irq); + break; + } + write32(®s->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_ABORT_EN)) + printk(BIOS_INFO, "%s:Abort failed\n", __func__); + } +} + +void qup_s_cancel_and_abort(unsigned int bus) +{ + struct qup_regs *regs = qup[bus].regs; + struct stopwatch sw; + unsigned int s_irq; + u32 rx_fifo_status; + u8 buf[64]; /* FIFO size */ + + write32(®s->geni_tx_watermark_reg, 0); + write32(®s->geni_s_cmd_ctrl_reg, S_GENI_CMD_CANCEL); + + stopwatch_init_msecs_expire(&sw, 100); + do { + s_irq = qup_wait_for_s_irq(bus); + rx_fifo_status = read32(®s->geni_rx_fifo_status); + if (rx_fifo_status & RX_LAST) + handle_rx(bus, buf, 64); /* Read whatever data available in FIFO */ + if (s_irq & S_CMD_CANCEL_EN) { + write32(®s->geni_s_irq_clear, s_irq); + break; + } + write32(®s->geni_s_irq_clear, s_irq); + } while (!stopwatch_expired(&sw)); + + if (!(s_irq & S_CMD_CANCEL_EN)) { + printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n", + __func__); + + write32(®s->geni_s_cmd_ctrl_reg, S_GENI_CMD_ABORT); + stopwatch_init_msecs_expire(&sw, 100); + do { + s_irq = qup_wait_for_s_irq(bus); + if (s_irq & S_CMD_ABORT_EN) { + write32(®s->geni_s_irq_clear, s_irq); + break; + } + write32(®s->geni_s_irq_clear, s_irq); + } while (!stopwatch_expired(&sw)); + + if (!(s_irq & S_CMD_ABORT_EN)) + printk(BIOS_INFO, "%s:Abort failed\n", __func__); + } +} + +int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size) +{ + unsigned int m_irq; + struct stopwatch sw; + unsigned int rx_rem_bytes = din ? size : 0; + unsigned int tx_rem_bytes = dout ? size : 0; + struct qup_regs *regs = qup[bus].regs; + + stopwatch_init_msecs_expire(&sw, 1000); + do { + m_irq = qup_wait_for_m_irq(bus); + if ((m_irq & M_RX_FIFO_WATERMARK_EN) || + (m_irq & M_RX_FIFO_LAST_EN)) + rx_rem_bytes -= handle_rx(bus, din + size + - rx_rem_bytes, rx_rem_bytes); + if (m_irq & M_TX_FIFO_WATERMARK_EN) + tx_rem_bytes -= handle_tx(bus, dout + size + - tx_rem_bytes, tx_rem_bytes); + if (m_irq & M_CMD_DONE_EN) { + write32(®s->geni_m_irq_clear, m_irq); + break; + } + write32(®s->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) { + printk(BIOS_INFO, "%s:Error: Transfer failed\n", __func__); + qup_m_cancel_and_abort(bus); + return -1; + } + return 0; +} diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c new file mode 100644 index 0000000000..14df187886 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static struct elf_se_hdr *fw_list[SE_PROTOCOL_MAX]; + +void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, + unsigned int mode) +{ + uint32_t i; + uint32_t reg_value; + const uint8_t *cfg_idx_arr; + const uint32_t *cfg_val_arr; + const uint32_t *fw_val_arr; + struct elf_se_hdr *hdr; + struct qup_regs *regs = qup[bus].regs; + static const char * const filename[] = { + [SE_PROTOCOL_SPI] = "fallback/spi_fw", + [SE_PROTOCOL_UART] = "fallback/uart_fw", + [SE_PROTOCOL_I2C] = "fallback/i2c_fw", + }; + + if (protocol >= SE_PROTOCOL_MAX || !filename[protocol]) + die("*ERROR* * INVALID PROTOCOL ***\n"); + + if (!fw_list[protocol]) { + fw_list[protocol] = cbfs_boot_map_with_leak(filename[protocol], + CBFS_TYPE_RAW, NULL); + if (!fw_list[protocol]) + die("*ERROR* * cbfs_boot_map_with_leak failed ***\n"); + } + + hdr = fw_list[protocol]; + assert(hdr->magic == SEFW_MAGIC_HEADER) + + cfg_idx_arr = (const uint8_t *)hdr + hdr->cfg_idx_offset; + cfg_val_arr = (const uint32_t *)((uint8_t *)hdr + hdr->cfg_val_offset); + fw_val_arr = (const uint32_t *)((uint8_t *)hdr + hdr->fw_offset); + + /* Unlock SE for FW loading */ + write32(®s->se_geni_fw_multilock_protns, 0x0); + write32(®s->se_geni_fw_multilock_msa, 0x0); + + /* First, ensure GENI FW is disabled */ + write32(®s->geni_output_ctrl, 0x0); + clrbits_le32(®s->geni_dfs_if_cfg, GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); + setbits_le32(®s->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK + | GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK); + write32(®s->se_geni_clk_ctrl, 0x0); + clrbits_le32(®s->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK + | GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK); + + + /* HPG section 3.1.7.1 */ + if (protocol == SE_PROTOCOL_UART) { + /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ + clock_configure_qup(bus, QUPV3_UART_SRC_HZ); + } else { + setbits_le32(®s->geni_dfs_if_cfg, + GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); + /* configure clock dfsr */ + clock_configure_dfsr(bus); + } + + /* HPG section 3.1.7.2 */ + /* No Init Required */ + + /* HPG section 3.1.7.3 */ + write32(®s->dma_general_cfg, + DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK | + DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK | + DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK | + DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK); + write32(®s->geni_cgc_ctrl, DEFAULT_CGC_EN); + + /* HPG section 3.1.7.4 */ + write32(®s->geni_init_cfg_revision, hdr->cfg_version); + write32(®s->geni_s_init_cfg_revision, hdr->cfg_version); + + assert(cfg_idx_arr[hdr->cfg_size_in_items - 1] * sizeof(uint32_t) <= + MAX_OFFSET_CFG_REG); + + for (i = 0; i < hdr->cfg_size_in_items; i++) { + write32(®s->geni_cfg_reg0 + cfg_idx_arr[i], + cfg_val_arr[i]); + } + + /* HPG section 3.1.7.9 */ + /* non-UART configuration, UART driver can configure as desired for UART + */ + write32(®s->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* HPG section 3.1.7.5 */ + /* Don't change any SPI polarity, client driver will handle this */ + setbits_le32(®s->geni_output_ctrl, DEFAULT_IO_OUTPUT_CTRL_MSK); + + /* HPG section 3.1.7.6 */ + reg_value = read32(®s->geni_dma_mode_en); + if (mode == GSI) { + reg_value |= GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK; + write32(®s->geni_dma_mode_en, reg_value); + write32(®s->se_irq_en, 0x0); + write32(®s->se_gsi_event_en, SE_GSI_EVENT_EN_BMSK); + } else if (mode == FIFO) { + reg_value &= ~GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK; + write32(®s->geni_dma_mode_en, reg_value); + write32(®s->se_irq_en, SE_IRQ_EN_RMSK); + write32(®s->se_gsi_event_en, 0x0); + } else if (mode == CPU_DMA) { + reg_value |= GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK; + write32(®s->geni_dma_mode_en, reg_value); + write32(®s->se_irq_en, SE_IRQ_EN_RMSK); + write32(®s->se_gsi_event_en, 0x0); + } + + /* HPG section 3.1.7.7 */ + write32(®s->geni_m_irq_enable, + M_COMMON_GENI_M_IRQ_EN); + reg_value = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN | + S_CMD_CANCEL_EN | S_CMD_ABORT_EN | + S_GP_IRQ_0_EN | S_GP_IRQ_1_EN | + S_GP_IRQ_2_EN | S_GP_IRQ_3_EN | + S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN; + write32(®s->geni_s_irq_enable, reg_value); + + /* HPG section 3.1.7.8 */ + /* GPI/DMA mode */ + reg_value = DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK | + DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK | + DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK; + write32(®s->dma_tx_irq_en_set, reg_value); + + reg_value = DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK | + DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK | + DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK | + DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK; + write32(®s->dma_rx_irq_en_set, reg_value); + + /* HPG section 3.1.7.10 */ + reg_value = (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) | + (hdr->fw_version & 0xFF << + FW_REV_VERSION_SHFT); + write32(®s->se_geni_fw_revision, reg_value); + + reg_value = + (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) | + (hdr->fw_version & 0xFF << + FW_REV_VERSION_SHFT); + write32(®s->se_s_fw_revision, reg_value); + + assert(hdr->fw_size_in_items <= SIZE_GENI_FW_RAM); + + memcpy((®s->se_geni_cfg_ramn), fw_val_arr, + hdr->fw_size_in_items * sizeof(uint32_t)); + + /* HPG section 3.1.7.12 */ + write32(®s->geni_force_default_reg, 0x1); + setbits_le32(®s->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK + |GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK); + setbits_le32(®s->se_geni_clk_ctrl, GENI_CLK_CTRL_SER_CLK_SEL_BMSK); + clrbits_le32(®s->geni_cgc_ctrl, + (GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK | + GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK)); + + /* HPG section 3.1.7.13 */ + /* GSI/DMA mode */ + setbits_le32(®s->se_dma_if_en, DMA_IF_EN_DMA_IF_EN_BMSK); + + /* HPG section 3.1.7.14 */ + reg_value = read32(®s->se_fifo_if_disable); + if ((mode == MIXED) || (mode == FIFO)) + reg_value &= ~FIFO_IF_DISABLE; + else + reg_value |= FIFO_IF_DISABLE; + write32(®s->se_fifo_if_disable, reg_value); + write32(®s->se_geni_clk_ctrl, 0x1); + + /* Lock SE from FW loading */ + write32(®s->se_geni_fw_multilock_protns, 0x1); + write32(®s->se_geni_fw_multilock_msa, 0x1); +} + +static void qup_common_init(int addr) +{ + struct qupv3_common_reg *qupv3_common; + /* HPG section 3.1.2 */ + qupv3_common = (struct qupv3_common_reg *)(uintptr_t) addr; + setbits32(&qupv3_common->qupv3_common_cfg_reg, + QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK); + + /* HPG section 3.1.7.3 */ + setbits32(&qupv3_common->qupv3_se_ahb_m_cfg_reg, + QUPV3_SE_AHB_M_CFG_AHB_M_CLK_CGC_ON_BMSK); +} + +void qupv3_fw_init(void) +{ + uint8_t i; + + /* Turn on all QUP clocks */ + for (i = 0; i < QUPV3_SE_MAX; i++) + clock_enable_qup(i); + + qup_common_init(QUP_WRAP0_BASE); + qup_common_init(QUP_WRAP1_BASE); +} From 7ae833bdaa3778d476f5d8a0a123c3492ceecef8 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Thu, 10 Oct 2019 15:29:16 -0700 Subject: [PATCH 1112/1463] sc7180: Add UART support This implements the UART driver in SoC Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25373/78 Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Signed-off-by: Roja Rani Yarubandi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35500 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sc7180/Kconfig | 6 + src/soc/qualcomm/sc7180/Makefile.inc | 10 +- src/soc/qualcomm/sc7180/qupv3_uart.c | 166 +++++++++++++++++++++++++++ 3 files changed, 179 insertions(+), 3 deletions(-) create mode 100644 src/soc/qualcomm/sc7180/qupv3_uart.c diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index 4093c93213..faf036e62b 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -31,4 +31,10 @@ config BOOT_DEVICE_SPI_FLASH_BUS int default 16 +config UART_FOR_CONSOLE + int + default 8 + help + Select the QUP instance to be used for UART console output. + endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 554efd8801..e49521b4bb 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -17,9 +17,11 @@ bootblock-y += qcom_qup_se.c verstage-y += timer.c verstage-y += spi.c verstage-y += gpio.c -verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c verstage-y += clock.c verstage-$(CONFIG_SC7180_QSPI) += qspi.c +verstage-y += qcom_qup_se.c +verstage-y += qupv3_config.c +verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ################################################################################ romstage-y += cbmem.c @@ -31,22 +33,24 @@ romstage-y += mmu.c romstage-y += usb.c romstage-y += spi.c romstage-y += gpio.c -romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c romstage-y += clock.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c +romstage-y += qcom_qup_se.c +romstage-y += qupv3_config.c +romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ################################################################################ ramstage-y += soc.c ramstage-y += timer.c ramstage-y += spi.c ramstage-y += gpio.c -ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c ramstage-y += usb.c ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c +ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c new file mode 100644 index 0000000000..aba35281c2 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */ + +#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK 0x1 +#define GENI_STATUS_S_GENI_CMD_ACTIVE_MASK 0x1000 + +#define UART_TX_WATERMARK_MARGIN 4 /* Represented in words */ +#define UART_RX_WATERMARK_MARGIN 8 /* Represented in words */ +#define UART_RX_RFR_WATERMARK_MARGIN 4 /* Represented in words */ +#define UART_TX_BITS_PER_WORD 8 +#define UART_RX_BITS_PER_WORD 8 +#define START_UART_TX 0x8000000 +#define START_UART_RX 0x8000000 + +/* UART FIFO Packing Configuration. */ +/* Start_idx:0, direction:0, len:7, stop:0 */ +#define UART_TX_PACK_VECTOR0 0x0E +/* Start_idx:8, direction:0, len:7, stop:0 */ +#define UART_TX_PACK_VECTOR1 0x10E +/* Start_idx:16, direction:0, len:7, stop:0 */ +#define UART_TX_PACK_VECTOR2 0x20E +/* Start_idx:24, direction:0, len:7, stop:1 */ +#define UART_TX_PACK_VECTOR3 0x30F +/* Start_idx:0, direction:0, len:7, stop:1 */ +#define UART_RX_PACK_VECTOR0 0xF +#define UART_RX_PACK_VECTOR2 0x00 + +void uart_tx_flush(int idx) +{ + struct qup_regs *regs = qup[idx].regs; + + while (read32(®s->geni_status) & + GENI_STATUS_M_GENI_CMD_ACTIVE_MASK) + ; +} + +void uart_init(int idx) +{ + struct qup_regs *regs = qup[idx].regs; + unsigned int reg_value; + unsigned int div, baud_rate, uart_freq; + + /* + * If the RX (secondary) sequencer is already active, it means the core + * has been already initialized in the previous stage. Skip + * configuration + */ + if (read32(®s->geni_status) & GENI_STATUS_S_GENI_CMD_ACTIVE_MASK) + return; + + qupv3_se_fw_load_and_init(idx, SE_PROTOCOL_UART, FIFO); + clock_enable_qup(idx); + + reg_value = read32(®s->geni_fw_revision_ro); + reg_value &= GENI_FW_REVISION_RO_PROTOCOL_MASK; + reg_value >>= GENI_FW_REVISION_RO_PROTOCOL_SHIFT; + + assert(reg_value == SE_PROTOCOL_UART); + + baud_rate = get_uart_baudrate(); + + /* sc7180 requires 16 clock pulses to sample 1 bit of data */ + uart_freq = baud_rate * 16; + + div = DIV_ROUND_CLOSEST(QUPV3_UART_SRC_HZ, uart_freq); + write32(®s->geni_ser_m_clk_cfg, (div << 4) | 1); + write32(®s->geni_ser_s_clk_cfg, (div << 4) | 1); + + /* GPIO Configuration */ + gpio_configure(qup[idx].pin[2], qup[idx].func[2], GPIO_PULL_UP, + GPIO_2MA, GPIO_OUTPUT); + gpio_configure(qup[idx].pin[3], qup[idx].func[3], GPIO_PULL_UP, + GPIO_2MA, GPIO_INPUT); + + write32(®s->geni_tx_watermark_reg, UART_TX_WATERMARK_MARGIN); + write32(®s->geni_rx_watermark_reg, FIFO_DEPTH + - UART_RX_WATERMARK_MARGIN); + write32(®s->geni_rx_rfr_watermark_reg, + FIFO_DEPTH - UART_RX_RFR_WATERMARK_MARGIN); + + write32(®s->uart_tx_word_len, UART_TX_BITS_PER_WORD); + write32(®s->uart_rx_word_len, UART_RX_BITS_PER_WORD); + + /* Disable TX parity calculation */ + write32(®s->uart_tx_parity_cfg, 0x0); + /* Ignore CTS line status for TX communication */ + write32(®s->uart_tx_trans_cfg_reg, 0x2); + /* Disable RX parity calculation */ + write32(®s->uart_rx_parity_cfg, 0x0); + /* Disable parity, framing and break check on received word */ + write32(®s->uart_rx_trans_cfg, 0x0); + /* Set UART TX stop bit len to one UART bit length */ + write32(®s->uart_tx_stop_bit_len, 0x0); + write32(®s->uart_rx_stale_cnt, 0x16 * 10); + + write32(®s->geni_tx_packing_cfg0, UART_TX_PACK_VECTOR0 | + (UART_TX_PACK_VECTOR1 << 10)); + write32(®s->geni_tx_packing_cfg1, UART_TX_PACK_VECTOR2 | + (UART_TX_PACK_VECTOR3 << 10)); + write32(®s->geni_rx_packing_cfg0, UART_RX_PACK_VECTOR0); + write32(®s->geni_rx_packing_cfg1, UART_RX_PACK_VECTOR2); + + /* Start RX */ + write32(®s->geni_s_cmd0, START_UART_RX); +} + +unsigned char uart_rx_byte(int idx) +{ + struct qup_regs *regs = qup[idx].regs; + + if (read32(®s->geni_rx_fifo_status) & RX_FIFO_WC_MSK) + return read32(®s->geni_rx_fifon) & 0xFF; + return 0; +} + +void uart_tx_byte(int idx, unsigned char data) +{ + struct qup_regs *regs = qup[idx].regs; + + uart_tx_flush(idx); + + write32(®s->uart_tx_trans_len, 1); + /* Start TX */ + write32(®s->geni_m_cmd0, START_UART_TX); + write32(®s->geni_tx_fifon, data); +} + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)qup[idx].regs; +} + +void uart_fill_lb(void *data) +{ + struct lb_serial serial = {0}; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = get_uart_baudrate(); + serial.regwidth = 4; + serial.input_hertz = QUPV3_UART_SRC_HZ; + + lb_add_serial(&serial, data); +} From 47a0832f821ab0e005f3552d0a6a26624c78a0c0 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Wed, 27 Nov 2019 19:22:45 -0800 Subject: [PATCH 1113/1463] sc7180: Add SPI QUP driver This implements the SPI driver for the QUP core. Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Signed-off-by: Roja Rani Yarubandi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36517 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sc7180/Makefile.inc | 4 + .../qualcomm/sc7180/include/soc/qupv3_spi.h | 27 ++ src/soc/qualcomm/sc7180/qupv3_spi.c | 231 ++++++++++++++++++ src/soc/qualcomm/sc7180/spi.c | 13 + 4 files changed, 275 insertions(+) create mode 100644 src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h create mode 100644 src/soc/qualcomm/sc7180/qupv3_spi.c diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index e49521b4bb..4a931f4b9c 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += bootblock.c bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-y += qupv3_spi.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c @@ -16,6 +17,7 @@ bootblock-y += qcom_qup_se.c ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-y += qupv3_spi.c verstage-y += gpio.c verstage-y += clock.c verstage-$(CONFIG_SC7180_QSPI) += qspi.c @@ -32,6 +34,7 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += usb.c romstage-y += spi.c +romstage-y += qupv3_spi.c romstage-y += gpio.c romstage-y += clock.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c @@ -43,6 +46,7 @@ romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ramstage-y += soc.c ramstage-y += timer.c ramstage-y += spi.c +ramstage-y += qupv3_spi.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h new file mode 100644 index 0000000000..4999422896 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPI_QUP_QCOM_HEADER___ +#define __SPI_QUP_QCOM_HEADER___ + +#include + +int qup_spi_claim_bus(const struct spi_slave *slave); +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in); +void qup_spi_release_bus(const struct spi_slave *slave); +void qup_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif /*__SPI_QUP_QCOM_HEADER___*/ diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c new file mode 100644 index 0000000000..b6999056fb --- /dev/null +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* SE_SPI_LOOPBACK register fields */ +#define LOOPBACK_ENABLE 0x1 + +/* SE_SPI_WORD_LEN register fields */ +#define WORD_LEN_MSK GENMASK(9, 0) +#define MIN_WORD_LEN 4 + +/* SPI_TX/SPI_RX_TRANS_LEN fields */ +#define TRANS_LEN_MSK GENMASK(23, 0) + +/* M_CMD OP codes for SPI */ +#define SPI_TX_ONLY 1 +#define SPI_RX_ONLY 2 +#define SPI_FULL_DUPLEX 3 +#define SPI_TX_RX 7 +#define SPI_CS_ASSERT 8 +#define SPI_CS_DEASSERT 9 +#define SPI_SCK_ONLY 10 + +/* M_CMD params for SPI */ +/* If fragmentation bit is set then CS will not toggle after each transfer */ +#define M_CMD_FRAGMENTATION BIT(2) + +#define BITS_PER_BYTE 8 +#define BITS_PER_WORD 8 +#define TX_WATERMARK 1 + +#define IRQ_TRIGGER (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN | \ + M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN | \ + M_CMD_CANCEL_EN | M_CMD_ABORT_EN) + +static void setup_fifo_params(const struct spi_slave *slave) +{ + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + u32 word_len = 0; + + /* Disable loopback mode */ + write32(®s->proto_loopback_cfg, 0); + + write32(®s->spi_demux_sel, slave->cs); + word_len = ((BITS_PER_WORD - MIN_WORD_LEN) & WORD_LEN_MSK); + write32(®s->spi_word_len, word_len); + + /* FIFO PACKING CONFIGURATION */ + write32(®s->geni_tx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(®s->geni_tx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(®s->geni_rx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(®s->geni_rx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(®s->geni_byte_granularity, (log2(BITS_PER_WORD) - 3)); +} + +static void qup_setup_m_cmd(unsigned int se_bus, u32 cmd, u32 params) +{ + struct qup_regs *regs = qup[se_bus].regs; + u32 m_cmd = (cmd << M_OPCODE_SHFT); + + m_cmd |= (params & M_PARAMS_MSK); + write32(®s->geni_m_cmd0, m_cmd); +} + +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + u32 m_cmd = 0; + u32 m_param = M_CMD_FRAGMENTATION; + int size; + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + + if ((bytes_in == 0) && (bytes_out == 0)) + return 0; + + setup_fifo_params(slave); + + if (!bytes_out) { + size = bytes_in; + m_cmd = SPI_RX_ONLY; + dout = NULL; + } else if (!bytes_in) { + size = bytes_out; + m_cmd = SPI_TX_ONLY; + din = NULL; + } else { + size = MIN(bytes_in, bytes_out); + m_cmd = SPI_FULL_DUPLEX; + } + + /* Check for maximum permissible transfer length */ + assert(!(size & ~TRANS_LEN_MSK)); + + if (bytes_out) { + write32(®s->spi_tx_trans_len, size); + write32(®s->geni_tx_watermark_reg, TX_WATERMARK); + } + if (bytes_in) + write32(®s->spi_rx_trans_len, size); + + qup_setup_m_cmd(se_bus, m_cmd, m_param); + + if (qup_handle_transfer(se_bus, dout, din, size)) + return -1; + + qup_spi_xfer(slave, dout + size, MAX((int)bytes_out - size, 0), + din + size, MAX((int)bytes_in - size, 0)); + + return 0; +} + +static int spi_qup_set_cs(const struct spi_slave *slave, bool enable) +{ + u32 m_cmd = 0; + u32 m_irq = 0; + unsigned int se_bus = slave->bus; + struct stopwatch sw; + + m_cmd = (enable) ? SPI_CS_ASSERT : SPI_CS_DEASSERT; + qup_setup_m_cmd(se_bus, m_cmd, 0); + + stopwatch_init_usecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_m_irq(se_bus); + if (m_irq & M_CMD_DONE_EN) { + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + break; + } + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_DONE_EN)) { + printk(BIOS_INFO, "%s:Failed to %s chip\n", __func__, + (enable) ? "Assert" : "Deassert"); + qup_m_cancel_and_abort(se_bus); + return -1; + } + return 0; +} + +void qup_spi_init(unsigned int bus, unsigned int speed_hz) +{ + u32 m_clk_cfg = 0, div = DEFAULT_SE_CLK / speed_hz; + struct qup_regs *regs = qup[bus].regs; + + /* Make sure div can hit target frequency within +/- 1KHz range */ + assert(((DEFAULT_SE_CLK - speed_hz * div) <= div * KHz) && (div > 0)); + qupv3_se_fw_load_and_init(bus, SE_PROTOCOL_SPI, MIXED); + clock_enable_qup(bus); + m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); + write32(®s->geni_ser_m_clk_cfg, m_clk_cfg); + /* Mode:0, cpha=0, cpol=0 */ + write32(®s->spi_cpha, 0); + write32(®s->spi_cpol, 0); + + /* Serial engine IO initialization */ + write32(®s->geni_cgc_ctrl, DEFAULT_CGC_EN); + write32(®s->dma_general_cfg, + (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON + | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON)); + write32(®s->geni_output_ctrl, + DEFAULT_IO_OUTPUT_CTRL_MSK); + write32(®s->geni_force_default_reg, FORCE_DEFAULT); + + /* Serial engine IO set mode */ + write32(®s->se_irq_en, (GENI_M_IRQ_EN | + GENI_S_IRQ_EN | DMA_TX_IRQ_EN | DMA_RX_IRQ_EN)); + write32(®s->se_gsi_event_en, 0); + + /* Set RX and RFR watermark */ + write32(®s->geni_rx_watermark_reg, 0); + write32(®s->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* GPIO Configuration */ + gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_NO_PULL, + GPIO_6MA, GPIO_INPUT); /* MISO */ + gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* MOSI */ + gpio_configure(qup[bus].pin[2], qup[bus].func[2], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CLK */ + gpio_configure(qup[bus].pin[3], qup[bus].func[3], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CS */ + + /* Select and setup FIFO mode */ + write32(®s->geni_m_irq_clear, 0xFFFFFFFF); + write32(®s->geni_s_irq_clear, 0xFFFFFFFF); + write32(®s->dma_tx_irq_clr, 0xFFFFFFFF); + write32(®s->dma_rx_irq_clr, 0xFFFFFFFF); + write32(®s->geni_m_irq_enable, (M_COMMON_GENI_M_IRQ_EN | + M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | + M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)); + write32(®s->geni_s_irq_enable, (S_COMMON_GENI_S_IRQ_EN + | S_CMD_DONE_EN)); + clrbits32(®s->geni_dma_mode_en, GENI_DMA_MODE_EN); +} + +int qup_spi_claim_bus(const struct spi_slave *slave) +{ + return spi_qup_set_cs(slave, 1); +} + +void qup_spi_release_bus(const struct spi_slave *slave) +{ + spi_qup_set_cs(slave, 0); +} diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index 8db3bd8e4f..10d09268d8 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -15,6 +15,7 @@ #include #include #include +#include static const struct spi_ctrlr qspi_ctrlr = { .claim_bus = sc7180_claim_bus, @@ -24,12 +25,24 @@ static const struct spi_ctrlr qspi_ctrlr = { .max_xfer_size = QSPI_MAX_PACKET_COUNT, }; +const struct spi_ctrlr spi_qup_ctrlr = { + .claim_bus = qup_spi_claim_bus, + .release_bus = qup_spi_release_bus, + .xfer = qup_spi_xfer, + .max_xfer_size = 65535, +}; + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, + { + .ctrlr = &spi_qup_ctrlr, + .bus_start = 0, + .bus_end = 11, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); From 52353d09fc981c48b58ebf8bf44f18ad12e119d2 Mon Sep 17 00:00:00 2001 From: satya priya Date: Thu, 19 Sep 2019 16:45:18 +0530 Subject: [PATCH 1114/1463] sc7180: Add I2C driver Add I2C functionality in coreboot. Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Signed-off-by: Roja Rani Yarubandi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36830 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sc7180/Makefile.inc | 4 + .../qualcomm/sc7180/include/soc/qupv3_i2c.h | 23 +++ src/soc/qualcomm/sc7180/qupv3_i2c.c | 165 ++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h create mode 100644 src/soc/qualcomm/sc7180/qupv3_i2c.c diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 4a931f4b9c..4961d244d0 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += timer.c bootblock-y += spi.c bootblock-y += qupv3_spi.c bootblock-y += gpio.c +bootblock-y += qupv3_i2c.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c bootblock-$(CONFIG_SC7180_QSPI) += qspi.c @@ -19,6 +20,7 @@ verstage-y += timer.c verstage-y += spi.c verstage-y += qupv3_spi.c verstage-y += gpio.c +verstage-y += qupv3_i2c.c verstage-y += clock.c verstage-$(CONFIG_SC7180_QSPI) += qspi.c verstage-y += qcom_qup_se.c @@ -36,6 +38,7 @@ romstage-y += usb.c romstage-y += spi.c romstage-y += qupv3_spi.c romstage-y += gpio.c +romstage-y += qupv3_i2c.c romstage-y += clock.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c romstage-y += qcom_qup_se.c @@ -48,6 +51,7 @@ ramstage-y += timer.c ramstage-y += spi.c ramstage-y += qupv3_spi.c ramstage-y += gpio.c +ramstage-y += qupv3_i2c.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h new file mode 100644 index 0000000000..e69f461ff9 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h @@ -0,0 +1,23 @@ +/* + * This file is part of the depthcharge project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_QCOM_HEADER___ +#define __I2C_QCOM_HEADER___ + +#include + +void i2c_init(unsigned int bus, enum i2c_speed speed); + +#endif /* __I2C_QCOM_HEADER */ diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c new file mode 100644 index 0000000000..b8938e2315 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -0,0 +1,165 @@ +/* + * This file is part of the depthcharge project. + * + * Copyright (C) 2018-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void i2c_clk_configure(unsigned int bus, enum i2c_speed speed) +{ + int clk_div = 0, t_high = 0, t_low = 0, t_cycle = 0; + struct qup_regs *regs = qup[bus].regs; + + switch (speed) { + case I2C_SPEED_STANDARD: + clk_div = 7; + t_high = 10; + t_low = 11; + t_cycle = 26; + break; + case I2C_SPEED_FAST: + clk_div = 2; + t_high = 5; + t_low = 12; + t_cycle = 24; + break; + case I2C_SPEED_FAST_PLUS: + clk_div = 1; + t_high = 3; + t_low = 9; + t_cycle = 18; + break; + default: + die("Unsupported I2C speed"); + } + + write32(®s->geni_ser_m_clk_cfg, (clk_div << 4) | 1); + /* Serial clock frequency is 19.2 MHz */ + write32(®s->i2c_scl_counters, ((t_high << 20) | (t_low << 10) + | t_cycle)); +} + +void i2c_init(unsigned int bus, enum i2c_speed speed) +{ + uint32_t proto; + struct qup_regs *regs = qup[bus].regs; + + qupv3_se_fw_load_and_init(bus, SE_PROTOCOL_I2C, MIXED); + clock_enable_qup(bus); + i2c_clk_configure(bus, speed); + + proto = ((read32(®s->geni_fw_revision_ro) & + GENI_FW_REVISION_RO_PROTOCOL_MASK) >> + GENI_FW_REVISION_RO_PROTOCOL_SHIFT); + + assert(proto == 3); + + /* Serial engine IO initialization */ + write32(®s->geni_cgc_ctrl, DEFAULT_CGC_EN); + write32(®s->dma_general_cfg, + (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON + | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON)); + write32(®s->geni_output_ctrl, + DEFAULT_IO_OUTPUT_CTRL_MSK); + write32(®s->geni_force_default_reg, FORCE_DEFAULT); + + /* Serial engine IO set mode */ + write32(®s->se_irq_en, (GENI_M_IRQ_EN | + GENI_S_IRQ_EN | DMA_TX_IRQ_EN | DMA_RX_IRQ_EN)); + write32(®s->se_gsi_event_en, 0); + + /* Set RX and RFR watermark */ + write32(®s->geni_rx_watermark_reg, 0); + write32(®s->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* FIFO PACKING CONFIGURATION */ + write32(®s->geni_tx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(®s->geni_tx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(®s->geni_rx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(®s->geni_rx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(®s->geni_byte_granularity, (log2(BITS_PER_WORD) - 3)); + + /* GPIO Configuration */ + gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_PULL_UP, + GPIO_2MA, GPIO_OUTPUT_ENABLE); + gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_PULL_UP, + GPIO_2MA, GPIO_OUTPUT_ENABLE); + + /* Select and setup FIFO mode */ + write32(®s->geni_m_irq_clear, 0xFFFFFFFF); + write32(®s->geni_s_irq_clear, 0xFFFFFFFF); + write32(®s->dma_tx_irq_clr, 0xFFFFFFFF); + write32(®s->dma_rx_irq_clr, 0xFFFFFFFF); + write32(®s->geni_m_irq_enable, (M_COMMON_GENI_M_IRQ_EN | + M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | + M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)); + write32(®s->geni_s_irq_enable, (S_COMMON_GENI_S_IRQ_EN + | S_CMD_DONE_EN)); + clrbits32(®s->geni_dma_mode_en, GENI_DMA_MODE_EN); +} + +static int i2c_do_xfer(unsigned int bus, struct i2c_msg segment, + unsigned int prams) +{ + unsigned int cmd = (segment.flags & I2C_M_RD) ? 2 : 1; + unsigned int master_cmd_reg_val = (cmd << M_OPCODE_SHFT); + struct qup_regs *regs = qup[bus].regs; + void *dout = NULL, *din = NULL; + + if (!(segment.flags & I2C_M_RD)) { + write32(®s->i2c_tx_trans_len, segment.len); + write32(®s->geni_tx_watermark_reg, TX_WATERMARK); + dout = segment.buf; + } else { + write32(®s->i2c_rx_trans_len, segment.len); + din = segment.buf; + } + + master_cmd_reg_val |= (prams & M_PARAMS_MSK); + write32(®s->geni_m_cmd0, master_cmd_reg_val); + + return qup_handle_transfer(bus, dout, din, segment.len); +} + +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int seg_count) +{ + struct i2c_msg *seg = segments; + int ret = 0; + + while (!ret && seg_count--) { + /* Stretch means end with repeated start, not stop */ + u32 stretch = (seg_count ? 1 : 0); + u32 m_param = 0; + + m_param |= (stretch << 2); + m_param |= ((seg->slave & 0x7F) << 9); + ret = i2c_do_xfer(bus, *seg, m_param); + seg++; + } + return ret; +} From e8abb5ab8887969498f9953e76b7e0f4c68d3e47 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Apr 2020 15:01:53 +0200 Subject: [PATCH 1115/1463] nb/intel/haswell: Deprecate WDB params in pei_data The WDB (Write Data Buffer) is a data region in CAR, used as a scratchpad in the read and write training algorithms of memory initialization. Both SNB and IVB use this buffer, but HSW does not. Unlike earlier chipsets, Haswell contains much more in-hardware memory training machinery, known as REUT (Robust Electrical Unified Testing). Among other changes, the REUT hardware has a pattern storage buffer, which renders the need for a pattern storage buffer in CAR obsolete. Deprecate the WDB-related parameters in the pei_data structure for Haswell, as they are leftovers from the previous generation's MRC. Remove them from the mainboards, and explain why they are not required. Because the MRC ABI has to remain the same, the layout of pei_data must not be changed, so rename the WDB parameters instead of deleting them. Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf. Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/mainboard/asrock/b85m_pro4/romstage.c | 2 -- src/mainboard/asrock/h81m-hds/romstage.c | 2 -- src/mainboard/google/beltino/romstage.c | 2 -- src/mainboard/google/slippy/variants/falco/romstage.c | 2 -- src/mainboard/google/slippy/variants/leon/romstage.c | 2 -- src/mainboard/google/slippy/variants/peppy/romstage.c | 2 -- src/mainboard/google/slippy/variants/wolf/romstage.c | 2 -- src/mainboard/intel/baskingridge/romstage.c | 2 -- src/mainboard/lenovo/t440p/romstage.c | 2 -- src/mainboard/supermicro/x10slm-f/romstage.c | 2 -- src/northbridge/intel/haswell/pei_data.h | 5 +++-- 11 files changed, 3 insertions(+), 22 deletions(-) diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index f9632ce34d..661942e249 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -34,8 +34,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 092b417657..4e6c8dc867 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -34,8 +34,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 373b488fe9..263ee32675 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -62,8 +62,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 1eb48bfd96..14883cad40 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -101,8 +101,6 @@ void variant_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 397c0edebb..4cd81f46db 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -97,8 +97,6 @@ void variant_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index d2a92a8789..660d7de3aa 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -114,8 +114,6 @@ void variant_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index dcd9ac06fd..866ac16252 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -101,8 +101,6 @@ void variant_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index b89d13593c..dbe5ed9a4d 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -59,8 +59,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 240aae2392..54929b04e9 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -40,8 +40,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 0c610dd7ac..e1eb7b1a61 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -33,8 +33,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 6e537403b3..17b7c182fa 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -73,8 +73,9 @@ struct pei_data uint32_t epbar; uint32_t pciexbar; uint16_t smbusbar; - uint32_t wdbbar; - uint32_t wdbsize; + /* Unused by HSW MRC, but changes to the memory layout of this struct break the ABI */ + uint32_t _unused_wdbbar; + uint32_t _unused_wdbsize; uint32_t hpet_address; uint32_t rcba; uint32_t pmbase; From ca584085d774b47c01bbc32cdb28678f7dc6e652 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 16 Mar 2020 15:33:06 -0700 Subject: [PATCH 1116/1463] soc/intel/tigerlake: Configure TCSS power management Add Type-C subsystem power management support for RTD3. BUG=b:140290596 TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build with the firmware CM. Added acpi debug and booted to kernel. Probed devices PM_STATE transition from D0 to D3 entry/exit while system at S0. TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT. xhci:00:0d.0, offset:0x74, PM_STATE:D0D3. dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST. Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended time tick through /sys/bus/pci/devices/bus:device:func/power. Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/acpi/tcss.asl | 784 +++++++++++++++++++ src/soc/intel/tigerlake/acpi/tcss_dma.asl | 227 ++++++ src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 315 ++++++++ src/soc/intel/tigerlake/acpi/tcss_xhci.asl | 138 ++++ 4 files changed, 1464 insertions(+) create mode 100644 src/soc/intel/tigerlake/acpi/tcss.asl create mode 100644 src/soc/intel/tigerlake/acpi/tcss_dma.asl create mode 100644 src/soc/intel/tigerlake/acpi/tcss_pcierp.asl create mode 100644 src/soc/intel/tigerlake/acpi/tcss_xhci.asl diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl new file mode 100644 index 0000000000..9f03aa94dd --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -0,0 +1,784 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +/* + * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), + * USB device controller(xDCI), Thunderbolt DMA devices and Thunderbolt PCIe controllers. + * PCIe RP0/RP1 is grouped with DMA0 and PCIe RP2/RP3 is grouped with DMA1. + */ +#define TCSS_TBT_PCIE0_RP0 0 +#define TCSS_TBT_PCIE0_RP1 1 +#define TCSS_TBT_PCIE0_RP2 2 +#define TCSS_TBT_PCIE0_RP3 3 +#define TCSS_XHCI 4 +#define TCSS_XDCI 5 +#define TCSS_DMA0 6 +#define TCSS_DMA1 7 + +/* + * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + * Command code 0x15 + * Description: Gateway command for handling TCSS DEVEN clear/restore. + * Field PARAM1[15:8] of the _INTERFACE register is used in this command to select from + * a pre-defined set of subcommands. + */ +#define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015 +#define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */ +#define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */ + +#define TCSS_IOM_ACK_TIMEOUT_IN_MS 100 + +Scope (\_SB) +{ + /* Device base address */ + Method (BASE, 1) + { + Local0 = Arg0 & 0x7 /* Function number */ + Local1 = (Arg0 >> 16) & 0x1F /* Device number */ + Local2 = (Local0 << 12) + (Local1 << 15) + Local3 = \_SB.PCI0.GPCB() + Local2 + Return (Local3) + } + + /* + * Define PCH ACPIBASE I/O as an ACPI operating region. The base address can be + * found in Device 31, Function 2, Offset 40h. + */ + OperationRegion (PMIO, SystemIO, PCH_PWRM_BASE_ADDRESS, 0x80) + Field (PMIO, ByteAcc, NoLock, Preserve) { + Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ + , 19, + CPWS, 1, /* CPU WAKE STATUS */ + Offset(0x7C), /* 0x7C, General Purpose Event 0 Enable [127:96] */ + , 19, + CPWE, 1 /* CPU WAKE EN */ + } + + Name (C2PW, 0) /* Set default value to 0. */ + + /* + * C2PM (CPU to PCH Method) + * + * This object is Enable/Disable GPE_CPU_WAKE_EN. + * Arguments: (4) + * Arg0 - An Integer containing the device wake capability + * Arg1 - An Integer containing the target system state + * Arg2 - An Integer containing the target device state + * Arg3 - An Integer containing the request device type + * Return Value: + * return 0 + */ + Method (C2PM, 4, NotSerialized) + { + Local0 = 0x1 << Arg3 + /* This method is used to enable/disable wake from Tcss Device (WKEN). */ + If (Arg0 && Arg1) + { /* If entering Sx and enabling wake, need to enable WAKE capability. */ + If (CPWE == 0) { /* If CPU WAKE EN is not set, Set it. */ + If (CPWS) { /* If CPU WAKE STATUS is set, Clear it. */ + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { /* If Staying in S0 or Disabling Wake. */ + If (Arg0 || Arg2) { /* Check if Exiting D0 and arming for wake. */ + /* If CPU WAKE EN is not set, Set it. */ + If (CPWE == 0) { + /* If CPU WAKE STATUS is set, Clear it. */ + If (CPWS) { + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { + /* + * Disable runtime PME, either because staying in D0 or + * disabling wake. + */ + If ((C2PW & Local0) != 0) { + /* + * Clear Corresponding Device En BIT in C2PW. + */ + C2PW &= ~Local0 + } + If ((CPWE != 0) && (C2PW == 0)) { + /* + * If CPU WAKE EN is set, Clear it. Clear CPU WAKE EN + * by writing 0. + */ + CPWE = 0 + } + } + } + Return (0) + } +} + +Scope (\_SB.PCI0) +{ + /* + * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset + * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR. + */ + OperationRegion (MBAR, SystemMemory, (GMHB() + 0x7100), 0x1000) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset(0x10), + RBAR, 64 /* RegBar, offset 0x7110 in MCHBAR */ + } + Field (MBAR, DWordAcc, NoLock, Preserve) + { + Offset(0x304), /* PRIMDN_MASK1_0_0_0_MCHBAR_IMPH, offset 0x7404 */ + , 31, + TCD3, 1 /* [31:31] TCSS IN D3 bit */ + } + + /* + * Operation region defined to access the pCode mailbox interface. Get the MCHBAR + * in offset 0x48 in B0:D0:F0. MMIO address is in offset 0x5DA0 of MCHBAR. + */ + OperationRegion (PBAR, SystemMemory, (GMHB() + 0x5DA0), 0x08) + Field (PBAR, DWordAcc, NoLock, Preserve) + { + PMBD, 32, /* pCode MailBox Data, offset 0x5DA0 in MCHBAR */ + PMBC, 8, /* pCode MailBox Command, [7:0] of offset 0x5DA4 in MCHBAR */ + PSCM, 8, /* pCode MailBox Sub-Command, [15:8] of offset 0x5DA4 in MCHBAR */ + , 15, /* Reserved */ + PMBR, 1 /* pCode MailBox RunBit, [31:31] of offset 0x5DA4 in MCHBAR */ + } + + /* + * Poll pCode MailBox Ready + * + * Return 0xFF - Timeout + * 0x00 - Ready + */ + Method (PMBY, 0) + { + Local0 = 0 + While (PMBR && (Local0 < 1000)) { + Local0++ + Stall (1) + } + If (Local0 == 1000) { + Printf("Timeout occurred.") + Return (0xFF) + } + Return (0) + } + + /* + * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS + * + * Result will be updated in DATA[1:0] + * DATA[0:0] TCSS_DEVEN_CURRENT_STATE: + * 0 - TCSS Deven in normal state. + * 1 - TCSS Deven is cleared by BIOS Mailbox request. + * DATA[1:1] TCSS_DEVEN_REQUEST_STATUS: + * 0 - IDLE. TCSS DEVEN has reached its final requested state. + * 1 - In Progress. TCSS DEVEN is currently in progress of switching state + * according to given request (bit 0 reflects source state). + * + * Return 0x00 - TCSS Deven in normal state + * 0x01 - TCSS Deven is cleared by BIOS Mailbox request + * 0x1x - TCSS Deven is in progress of switching state according to given request + * 0xFE - Command timeout + * 0xFF - Command corrupt + */ + Method (DSGS, 0) + { + If ((PMBY () == 0)) { + PMBC = MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + PSCM = TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS + PMBR = 1 + If (PMBY () == 0) { + Local0 = PMBD + Local1 = PMBC + Stall (10) + If ((Local0 != PMBD) || (Local1 != PMBC)) { + Printf("pCode MailBox is corrupt.") + Return (0xFF) + } + Return (Local0) + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } + + /* + * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ + * + * Arg0 : 0 - Restore to previously saved value of TCSS DEVEN + * 1 - Save current TCSS DEVEN value and clear it + * + * Return 0x00 - MAILBOX_BIOS_CMD_CLEAR_TCSS_DEVEN command completed + * 0xFD - Input argument is invalid + * 0xFE - Command timeout + * 0xFF - Command corrupt + */ + Method (DSCR, 1) + { + If (Arg0 > 1) { + Printf("pCode MailBox is corrupt.") + Return (0xFD) + } + If ((PMBY () == 0)) { + PMBC = MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + PSCM = TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ + PMBD = Arg0 + PMBR = 1 + If ((PMBY () == 0)) { + Local0 = PMBD + Local1 = PMBC + Stall (10) + If ((Local0 != PMBD) || (Local1 != PMBC)) { + Printf("pCode MailBox is corrupt.") + Return (0xFF) + } + /* Poll TCSS_DEVEN_REQUEST_STATUS, timeout value is 10ms. */ + Local0 = 0 + While ((DSGS () & 0x10) && (Local0 < 100)) { + Stall (100) + Local0++ + } + If (Local0 == 100) { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } Else { + Return (0x00) + } + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } + + /* + * IOM REG BAR Base address is in offset 0x7110 in MCHBAR. + */ + Method (IOMA, 0) + { + Return (^RBAR & ~0x1) + } + + /* + * From RegBar Base, IOM_TypeC_SW_configuration_1 is in offset 0xC10040, where + * 0x40 is the register offset. + */ + OperationRegion (IOMR, SystemMemory, (IOMA() + 0xC10000), 0x100) + Field (IOMR, DWordAcc, NoLock, Preserve) + { + Offset(0x40), + , 15, + TD3C, 1, /* [15:15] Type C D3 cold bit */ + TACK, 1, /* [16:16] IOM Acknowledge bit */ + DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ + /* display is OFF, clear otherwise */ + Offset(0x70), /* Pyhsical addr is offset 0x70. */ + IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ + IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ + } + + /* + * Below is a variable to store devices connect state for TBT PCIe RP before + * entering D3 cold. + * Value 0 - no device connected before enter D3 cold, no need to send + * CONNECT_TOPOLOGY in D3 cold exit. + * Value 1 - has device connected before enter D3 cold, need to send + * CONNECT_TOPOLOGY in D3 cold exit. + */ + Name (CTP0, 0) /* Variable of device connecet status for TBT0 group. */ + Name (CTP1, 0) /* Variable of device connecet status for TBT1 group. */ + + /* + * TBT Group0 ON method + */ + Method (TG0N, 0) + { + If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { + Printf("TDM0 does not exist.") + } + + If (\_SB.PCI0.TDM0.STAT == 0) { + /* DMA0 is in D3Cold early. */ + \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */ + + Printf("Bring TBT RPs out of D3Code.") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* RP0 D3 cold exit. */ + \_SB.PCI0.TRP0.D3CX() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* RP1 D3 cold exit. */ + \_SB.PCI0.TRP1.D3CX() + } + + /* + * Need to send Connect-Topology command when TBT host + * controller back to D0 from D3. + */ + If (\_SB.PCI0.TDM0.ALCT == 1) { + If (CTP0 == 1) { + /* + * Send Connect-Topology command if there is + * device present on PCIe RP. + */ + \_SB.PCI0.TDM0.CNTP() + + /* Indicate to wait Connect-Topology command. */ + \_SB.PCI0.TDM0.WACT = 1 + + /* Clear the connect states. */ + CTP0 = 0 + } + /* Disallow to send Connect-Topology command. */ + \_SB.PCI0.TDM0.ALCT = 0 + } + } Else { + Printf("Drop TG0N due to it is already exit D3 cold.") + } + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) + } + + /* + * TBT Group0 OFF method + */ + Method (TG0F, 0) + { + If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { + Printf("TDM0 does not exist.") + } + + If (\_SB.PCI0.TDM0.STAT == 1) { + /* DMA0 is not in D3Cold now. */ + \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + + Printf("Push TBT RPs to D3Cold together") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP0.PDSX == 1) { + CTP0 = 1 + } + /* Put RP0 to D3 cold. */ + \_SB.PCI0.TRP0.D3CE() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP1.PDSX == 1) { + CTP0 = 1 + } + /* Put RP1 to D3 cold. */ + \_SB.PCI0.TRP1.D3CE() + } + } + } + + /* + * TBT Group1 ON method + */ + Method (TG1N, 0) + { + If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { + Printf("TDM1 does not exist.") + } + + If (\_SB.PCI0.TDM1.STAT == 0) { + /* DMA1 is in D3Cold early. */ + \_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */ + + Printf("Bring TBT RPs out of D3Code.") + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* RP2 D3 cold exit. */ + \_SB.PCI0.TRP2.D3CX() + } + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + /* RP3 D3 cold exit. */ + \_SB.PCI0.TRP3.D3CX() + } + + /* + * Need to send Connect-Topology command when TBT host + * controller back to D0 from D3. + */ + If (\_SB.PCI0.TDM1.ALCT == 1) { + If (CTP1 == 1) { + /* + * Send Connect-Topology command if there is + * device present on PCIe RP. + */ + \_SB.PCI0.TDM1.CNTP() + + /* Indicate to wait Connect-Topology command. */ + \_SB.PCI0.TDM1.WACT = 1 + + /* Clear the connect states. */ + CTP1 = 0 + } + /* Disallow to send Connect-Topology cmd. */ + \_SB.PCI0.TDM1.ALCT = 0 + } + } Else { + Printf("Drop TG1N due to it is already exit D3 cold.") + } + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) + } + + /* + * TBT Group1 OFF method + */ + Method (TG1F, 0) + { + If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { + Printf("TDM1 does not exist.") + } + + If (\_SB.PCI0.TDM1.STAT == 1) { + /* DMA1 is not in D3Cold now */ + \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + + Printf("Push TBT RPs to D3Cold together") + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP2.PDSX == 1) { + CTP1 = 1 + } + /* Put RP2 to D3 cold. */ + \_SB.PCI0.TRP2.D3CE() + } + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP3.PDSX == 1) { + CTP1 = 1 + } + /* Put RP3 to D3 cold */ + \_SB.PCI0.TRP3.D3CE() + } + } + } + + PowerResource (TBT0, 5, 1) + { + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } + } + + PowerResource (TBT1, 5, 1) + { + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM1.STAT) + } + + Method (_ON, 0) + { + TG1N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM1.SD3C == 0) { + TG1F() + } + } + } + + Method (TCON, 0) + { + /* Reset IOM D3 cold bit if it is in D3 cold now. */ + If (TD3C == 1) /* It was in D3 cold before. */ + { + /* Reset IOM D3 cold bit. */ + TD3C = 0 /* Request IOM for D3 cold exit sequence. */ + Local0 = 0 /* Time check counter variable */ + /* Wait for ack, the maximum wait time for the ack is 100 msec. */ + While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { + /* + * Wait in this loop until TACK becomes 0 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ + Sleep (1) /* Delay of 1ms. */ + Local0++ + } + + If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { + Printf("Error: Error: Timeout occurred.") + } + Else + { + /* + * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and + * acknowledgement by IOM. + */ + TCD3 = 0 + /* + * If the TCSS Deven is cleared by BIOS Mailbox request, then + * restore to previously saved value of TCSS DEVNE. + */ + Local0 = 0 + While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) { + If (DSGS () == 1) { + DSCR (0) + } + Local0++ + If (Local0 == 5) { + Printf("pCode mailbox command failed.") + Break + } + } + } + } + Else { + Printf("Drop TCON due to it is already exit D3 cold.") + } + } + + Method (TCOF, 0) + { + If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0) + || (\_SB.PCI0.TDM1.SD3C != 0)) + { + Printf("Skip D3C entry.") + Return + } + + /* + * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and + * clear it. + */ + Local0 = 0 + While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) { + If (DSGS () == 0) { + DSCR (1) + } + Local0++ + If (Local0 == 5) { + Printf("pCode mailbox command failed.") + Break + } + } + + /* + * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold. + */ + TCD3 = 1 + + /* Request IOM for D3 cold entry sequence. */ + TD3C = 1 + } + + PowerResource (D3C, 5, 0) + { + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } + } + + /* + * TCSS xHCI device + */ + Device (TXHC) + { + Name (_ADR, 0x000D0000) + Name (_DDN, "North XHCI controller") + Name (_STR, Unicode ("North XHCI controller")) + Name (DCPM, TCSS_XHCI) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + #include "tcss_xhci.asl" + } + + /* + * TCSS DMA0 device + */ + Device (TDM0) + { + Name (_ADR, 0x000D0002) + Name (_DDN, "TBT DMA0 controller") + Name (_STR, Unicode ("TBT DMA0 controller")) + Name (DUID, 0) /* TBT DMA number */ + Name (DCPM, TCSS_DMA0) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + #include "tcss_dma.asl" + } + + /* + * TCSS DMA1 device + */ + Device (TDM1) + { + Name (_ADR, 0x000D0003) + Name (_DDN, "TBT DMA1 controller") + Name (_STR, Unicode ("TBT DMA1 controller")) + Name (DUID, 1) /* TBT DMA number */ + Name (DCPM, TCSS_DMA1) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + #include "tcss_dma.asl" + } + + /* + * TCSS PCIE Root Port #00 + */ + Device (TRP0) + { + Name (_ADR, 0x00070000) + Name (TUID, 0) /* TBT PCIE RP Number 0 for RP00 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP0) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #01 + */ + Device (TRP1) + { + Name (_ADR, 0x00070001) + Name (TUID, 1) /* TBT PCIE RP Number 1 for RP01 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP1) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #02 + */ + Device (TRP2) + { + Name (_ADR, 0x00070002) + Name (TUID, 2) /* TBT PCIE RP Number 2 for RP02 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP2) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #03 + */ + Device (TRP3) + { + Name (_ADR, 0x00070003) + Name (TUID, 3) /* TBT PCIE RP Number 3 for RP03 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP3) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } +} diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl new file mode 100644 index 0000000000..a2f86baf09 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +OperationRegion (DPME, SystemMemory, BASE(_ADR), 0x100) +Field (DPME, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x84), /* 0x84, DMA CFG PM CAP */ + PMST, 2, /* 1:0, PM_STATE */ + , 6, + PMEE, 1, /* 8, PME_EN */ + , 6, + PMES, 1, /* 15, PME_STATUS */ + Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ + , 31, + INFR, 1, /* TBT NVM FW Ready */ + Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ + TB2P, 32, /* TBT to PCIe */ + P2TB, 32, /* PCIe to TBT */ + Offset(0xFC), /* 0xFC, DMA RTD3 Force Power */ + DD3E, 1, /* 0:0 DMA RTD3 Enable */ + DFPE, 1, /* 1:1 DMA Force Power */ + , 22, + DMAD, 8 /* 31:24 DMA Active Delay */ +} + +/* + * TBT MailBox Command Method + * Arg0 - MailBox Cmd ID + */ +Method (ITMB, 1, Serialized) +{ + Local0 = Arg0 | 0x1 /* 0x1, PCIE2TBT_VLD_B */ + P2TB = Local0 +} + +/* + * Wait For Command Completed + * Arg0 - TimeOut value (unit is 1 millisecond) + */ +Method (WFCC, 1, Serialized) +{ + WTBS (Arg0) + P2TB = 0 + WTBC (Arg0) +} + +/* + * Wait For Command Set + * Arg0 - TimeOut value + */ +Method (WTBS, 1, Serialized) +{ + Local0 = Arg0 + While (Local0 > 0) { + /* Wait for Bit to Set. */ + If (TB2P & 0x1) { /* 0x1, TBT2PCIE_DON_R */ + Break + } + Local0-- + Sleep (1) + } +} + +/* + * Wait For Command Clear + * Arg0 - TimeOut value + */ +Method (WTBC, 1, Serialized) +{ + Local0 = Arg0 + While (Local0 > 0) { + /* Wait for Bit to Clear. */ + If ((TB2P & 0x1) != 0x0) { /* 0x1, TBT2PCIE_DON_R */ + Break + } + Local0-- + Sleep (1) + } +} + +/* + * TCSS TBT CONNECT_TOPOLOGY MailBox Command Method + */ +Method (CNTP, 0, Serialized) +{ + Local0 = 0 + /* Set Force Power if it is not set */ + If (DFPE == 0) { + DMAD = 0x22 + DFPE = 1 + /* + * Poll the TBT NVM FW Ready bit with timeout(default is 500ms) before + * send the TBT MailBox command. + */ + While ((INFR == 0) && (Local0 < 500)) { + Sleep (1) + Local0++ + } + } + If (Local0 != 100) { + ITMB (0x3E) /* 0x3E, PCIE2TBT_CONNECT_TOPOLOGY_COMMAND */ + } +} + +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ +Name (ALCT, 0x0) /* Connect-Topology cmd can be sent or not 1 - yes, 0 - no */ +/* + * Wait Connect-Topology cmd done + * 0 - no need to wait + * 1 - need to wait + * 2 - wait in progress + */ +Name (WACT, 0x0) + +Method (_PS0, 0, Serialized) +{ + If (WACT == 1) { + /* + * PCIe rp0/rp1 is grouped with DMA0 and PCIe rp2/rp3 is grouped wit DMA1. + * Whenever the Connect-Topology command is in the process, WACT flag is set 1. + * PCIe root ports 0/1/2/3/ and DMA 0/1 _PS0 method set WACT to 2 to indicate + * other thread's _PS0 to wait for the command completion. WACT is cleared to + * be 0 after command is finished. + */ + WACT = 2 + WFCC (100) /* Wait for command complete. */ + WACT = 0 + } ElseIf (WACT == 2) { + While (WACT != 0) { + Sleep (5) + } + } +} + +Method (_PS3, 0, Serialized) +{ +} + +Method (_S0W, 0x0) +{ + Return (0x4) +} + +Method (_PR0) +{ + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +Method (_PR3) +{ + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + DD3E = 0 /* Disable DMA RTD3 */ + STAT = 0x1 +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + DD3E = 1 /* Enable DMA RTD3 */ + STAT = 0 + ALCT = 0x1 /* Allow to send Connect-Topology cmd. */ +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +Method (_DSW, 3) +{ + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +Method (_PRW, 0) +{ + Return (Package() { 0x6D, 4 }) +} + +Method (_DSD, 0) +{ + Return( + Package() + { + /* Thunderbolt GUID for IMR_VALID at ../drivers/acpi/property.c */ + ToUUID("C44D002F-69F9-4E7D-A904-A7BAABDF43F7"), + Package () + { + Package (2) { "IMR_VALID", 1 } + }, + + /* Thunderbolt GUID for WAKE_SUPPORTED at ../drivers/acpi/property.c */ + ToUUID("6C501103-C189-4296-BA72-9BF5A26EBE5D"), + Package () + { + Package (2) { "WAKE_SUPPORTED", 1 } + } + } + ) +} + +Method (_DSM, 4, Serialized) +{ + Return (Buffer() { 0 }) +} diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl new file mode 100644 index 0000000000..653266175d --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -0,0 +1,315 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) +Field (PXCS, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x50), /* LCTL - Link Control Register */ + L0SE, 1, /* 0, L0s Entry Enabled */ + , 3, + LDIS, 1, /* 1, Link Disable */ + , 3, + Offset(0x52), /* LSTS - Link Status Register */ + , 13, + LASX, 1, /* 0, Link Active Status */ + Offset(0x5A), /* SLSTS[7:0] - Slot Status Register */ + ABPX, 1, /* 0, Attention Button Pressed */ + , 2, + PDCX, 1, /* 3, Presence Detect Changed */ + , 2, + PDSX, 1, /* 6, Presence Detect State */ + , 1, + DLSC, 1, /* 8, Data Link Layer State Changed */ + Offset(0x60), /* RSTS - Root Status Register */ + , 16, + PSPX, 1, /* 16, PME Status */ + Offset(0xA4), + D3HT, 2, /* Power State */ + Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */ + , 30, + HPEX, 1, /* 30, Hot Plug SCI Enable */ + PMEX, 1, /* 31, Power Management SCI Enable */ + Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0x420), /* 0x420, PCIEPMECTL (PCIe PM Extension Control) */ + , 30, + DPGE, 1, /* PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane */ + /* Power Gating Enable (DLSULPPGE) */ + Offset(0x5BC), /* 0x5BC, PCIE ADVMCTRL */ + , 3, + RPER, 1, /* RTD3PERST[3] */ + RPFE, 1, /* RTD3PFETDIS[4] */ +} + +Field (PXCS, AnyAcc, NoLock, WriteAsZeros) +{ + Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */ + , 30, + HPSX, 1, /* 30, Hot Plug SCI Status */ + PMSX, 1 /* 31, Power Management SCI Status */ +} + +/* + * _DSM Device Specific Method + * + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ +Method (_DSM, 4, Serialized) +{ + return (Buffer() {0x00}) +} + +Device (PXSX) +{ + Name (_ADR, 0x00000000) + + Method (_PRW, 0) + { + Return (Package() { 0x69, 4 }) + } +} + +Method (_DSW, 3) +{ + C2PM (Arg0, Arg1, Arg2, DCPM) + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + \_SB.PCI0.TDM0.SD3C = Arg1 + \_SB.PCI0.TDM1.SD3C = Arg1 +} + +Method (_PRW, 0) +{ + Return (Package() { 0x69, 4 }) +} + +/* + * Sub-Method of _L61 Hot-Plug event + * _L61 event handler should invoke this method to support HotPlug wake event from TBT RP. + */ +Method (HPEV, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && HPSX) { + If ((PDCX == 1) && (DLSC == 1)) { + /* Clear all status bits first. */ + PDCX = 1 + HPSX = 1 + + /* Perform proper notification to the OS. */ + Notify (^, 0) + } Else { + /* False event. Clear Hot-Plug Status, then exit. */ + HPSX = 1 + } + } +} + +/* + * Power Management routine for D3 + */ +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + If (STAT == 0x1) { + Return + } + + RPFE = 0 /* Set RTD3PFETDIS = 0 */ + RPER = 0 /* Set RTD3PERST = 0 */ + L23R = 1 /* Set L23r2dt = 1 */ + + /* + * Poll for L23r2dt == 0. Wait for transition to Detect. + */ + Local0 = 0 + Local1 = L23R + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23R + } + STAT = 0x1 + + /* Wait for LA = 1 */ + Local0 = 0 + Local1 = LASX + While (Local1 == 0) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = LASX + } +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + If (STAT == 0x0) { + Return + } + + L23E = 1 /* Set L23er = 1 */ + + /* Poll until L23er == 0 */ + Local0 = 0 + Local1 = L23E + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23E + } + + STAT = 0 /* D3Cold */ + RPFE = 1 /* Set RTD3PFETDIS = 1 */ + RPER = 1 /* Set RTD3PERST = 1 */ +} + +Method (_PS0, 0, Serialized) +{ + HPEV () /* Check and handle Hot Plug SCI status. */ + If (HPEX == 1) { + HPEX = 0 /* Disable Hot Plug SCI */ + } + HPME () /* Check and handle PME SCI status */ + If (PMEX == 1) { + PMEX = 0 /* Disable Power Management SCI */ + } + Sleep(100) /* Wait for 100ms before return to OS starts any DS activities. */ + If ((TUID == 0) || (TUID == 1)) { + If (\_SB.PCI0.TDM0.WACT == 1) { + /* + * Indicate other thread's _PS0 to wait the response. + */ + \_SB.PCI0.TDM0.WACT = 2 + \_SB.PCI0.TDM0.WFCC (10) /* Wait for command complete. */ + \_SB.PCI0.TDM0.WACT = 0 + } ElseIf (\_SB.PCI0.TDM0.WACT == 2) { + While (\_SB.PCI0.TDM0.WACT != 0) { + Sleep (5) + } + } + } Else { + If (\_SB.PCI0.TDM1.WACT == 1) { + /* + * Indicate other thread's _PS0 to wait the response. + */ + \_SB.PCI0.TDM1.WACT = 2 + \_SB.PCI0.TDM1.WFCC (10) /* Wait for command complete. */ + \_SB.PCI0.TDM1.WACT = 0 + } ElseIf (\_SB.PCI0.TDM1.WACT == 2) { + While (\_SB.PCI0.TDM1.WACT != 0) { + Sleep (5) + } + } + } +} + +Method (_PS3, 0, Serialized) +{ + /* Check it is hotplug SCI or not, then clear PDC accordingly */ + If (PDCX == 1) { + If (DLSC == 0) { + /* Clear PDC since it is not a hotplug. */ + PDCX = 1 + } + } + + If (HPEX == 0) { + HPEX = 1 /* Enable Hot Plug SCI. */ + HPEV () /* Check and handle Hot Plug SCI status. */ + } + If (PMEX == 0) { + PMEX = 1 /* Enable Power Management SCI. */ + HPME () /* Check and handle PME SCI status. */ + } +} + +Method (_DSD, 0) { + Return ( + Package () { + /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () + { + Package (2) { "HotPlugSupportInD3", 1 }, + }, + + /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ + ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), + Package () { + Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ + /* + * UID of the TBT RP on platform, range is: 0, 1 ..., + * (NumOfTBTRP - 1). + */ + Package (2) { "UID", TUID }, + } + } + ) +} + +Method (_S0W, 0x0, NotSerialized) +{ + Return (0x4) +} + +Method (_PR0) +{ + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +Method (_PR3) +{ + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +/* + * PCI_EXP_STS Handler for PCIE Root Port + */ +Method (HPME, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && (PMSX == 1)) { /* if port exists and PME SCI Status set */ + /* + * Notify child device; this will cause its driver to clear PME_Status from + * device. + */ + Notify (PXSX, 0x2) + PMSX = 1 /* clear rootport's PME SCI status */ + /* + * Consume one pending PME notification to prevent it from blocking the queue. + */ + PSPX = 1 + Return (0x01) + } + Return (0x00) +} diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl new file mode 100644 index 0000000000..e78cc1d482 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +OperationRegion (XPRT, SystemMemory, BASE(_ADR), 0x100) +Field (XPRT, ByteAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x74), /* 0x74, XHCI CFG Power Control And Status */ + D0D3, 2, /* 0x74 BIT[1:0] */ + , 6, + PMEE, 1, /* PME Enable */ + , 6, + PMES, 1, /* PME Status */ +} + +Method (_PS0, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 1) { + /* Clear PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 0 + } +} + +Method (_PS3, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 0) { + /* Set PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 1 + } +} + +Method (_S0W, 0x0, NotSerialized) +{ + Return (0x4) +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +Method (_PR0) +{ + Return (Package () { \_SB.PCI0.D3C }) +} + +Method (_PR3) +{ + Return (Package () { \_SB.PCI0.D3C }) +} + +/* + * XHCI controller _DSM method + */ +Method (_DSM, 4, serialized) +{ + Return (Buffer() { 0 }) +} + +/* + * _SXD and _SXW methods + */ +Method (_S3D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S3W, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4W, 0, NotSerialized) +{ + Return (3) +} + +/* + * Power resource for wake + */ +Method (_PRW, 0) +{ + Return (Package() { 0x6D, 4 }) +} + +/* + * Device sleep wake + */ +Method (_DSW, 3) +{ + C2PM (Arg0, Arg1, Arg2, DCPM) + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +/* + * xHCI Root Hub Device + */ +Device (RHUB) +{ + Name (_ADR, Zero) + + /* High Speed Ports */ + Device (HS01) + { + Name (_ADR, 0x01) + } + + /* Super Speed Ports */ + Device (SS01) + { + Name (_ADR, 0x02) + } + + Device (SS02) + { + Name (_ADR, 0x03) + } + + Device (SS03) + { + Name (_ADR, 0x04) + } + + Device (SS04) + { + Name (_ADR, 0x05) + } +} From f3003657a036cd2193d0dee06815c708f67637ae Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 17 Apr 2020 19:07:26 -0600 Subject: [PATCH 1117/1463] mb/google/deltaur: Remove GbE FMAP region Deltan will be using the integrated Intel GbE for LAN functionality. Deltaur will not have a LAN port, and so does not need the GbE region. This patch adds a new FMAP descriptor file which explicitly supports the GbE region (chromeos-gbe.fmd), and removes the GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd, and Deltaur is assigned chromeos.fmd. BUG=b:150165131 TEST=emerge-deltaur coreboot chromeos-bootimage and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI Signed-off-by: Tim Wawrzynczak Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Angel Pons --- src/mainboard/google/deltaur/Kconfig | 5 ++ src/mainboard/google/deltaur/chromeos-gbe.fmd | 49 +++++++++++++++++++ src/mainboard/google/deltaur/chromeos.fmd | 3 +- 3 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/deltaur/chromeos-gbe.fmd diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index cd4646ccec..74c82010e0 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -43,6 +43,11 @@ config DRIVER_TPM_I2C_ADDR hex default 0x50 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-gbe.fmd" if BOARD_GOOGLE_DELTAN + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_GOOGLE_DELTAUR + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/deltaur/chromeos-gbe.fmd b/src/mainboard/google/deltaur/chromeos-gbe.fmd new file mode 100644 index 0000000000..9b6fec3ab2 --- /dev/null +++ b/src/mainboard/google/deltaur/chromeos-gbe.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x606000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_GBE(PRESERVE)@0x101000 0x2000 + SI_ME@0x103000 0x4ff000 + SI_PDR(PRESERVE)@0x602000 0x4000 + } + SI_BIOS@0x606000 0x19fa000 { + RW_DIAG@0x0 0x10ca000 { + RW_LEGACY(CBFS)@0x0 0x10ba000 + DIAG_NVRAM@0x10ba000 0x10000 + } + RW_SECTION_A@0x10ca000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x134a000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x15ca000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + WP_RO@0x15fa000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3ec000 + } + } + } +} diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd index 9b6fec3ab2..bbec112b78 100644 --- a/src/mainboard/google/deltaur/chromeos.fmd +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -2,8 +2,7 @@ FLASH@0xfe000000 0x2000000 { SI_ALL@0x0 0x606000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_GBE(PRESERVE)@0x101000 0x2000 - SI_ME@0x103000 0x4ff000 + SI_ME@0x101000 0x501000 SI_PDR(PRESERVE)@0x602000 0x4000 } SI_BIOS@0x606000 0x19fa000 { From 9138eee4f7ed304a27fcb0028dd8865d79537374 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 20 Apr 2020 15:20:55 +0800 Subject: [PATCH 1118/1463] mb/google/deltaur: Correct SPD SMBus address SMBus uses 7-bits address, change it from 8-bits to 7-bits. BUG=b:151702387 TEST=Check Memory SPD data is correct in console log. Signed-off-by: Eric Lai Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel --- src/mainboard/google/deltaur/variants/deltan/memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index d51ba70431..0c5873f056 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -48,9 +48,9 @@ void variant_memory_init(FSP_M_CONFIG *mem_cfg) { const struct spd_info spd_info = { .topology = SODIMM, - .smbus_info[0] = {.addr_dimm0 = 0xa0, + .smbus_info[0] = {.addr_dimm0 = 0x50, .addr_dimm1 = 0 }, - .smbus_info[1] = {.addr_dimm0 = 0xa4, + .smbus_info[1] = {.addr_dimm0 = 0x52, .addr_dimm1 = 0 }, }; const bool half_populated = false; From b8d083ec74735b50917adfc2b4da41e3ac698ad3 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Tue, 21 Apr 2020 17:55:53 +1000 Subject: [PATCH 1119/1463] mb/google/puff: comment schematics changes for USB USB routing has changed on reference schematics after Puff rev1 has built. This may confuse people trying to c&p devicetree from the Puff. So add comment to clearly note that there was change, hopefully preventing c&p errors. BUG=b:153682207 BRANCH=None TEST=None Signed-off-by: Kangheui Won Change-Id: I5c43a5c04c81b6708c9eeabc48ef11961d7c8561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40546 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 2f36bc8b62..d869b28a33 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -21,6 +21,9 @@ chip soc/intel/cannonlake }" # USB configuration + # NOTE: This only applies to Puff, + # usb2_ports[1] and usb2_ports[3] were swapped on + # reference schematics after Puff has been built. register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[2]" = "{ From 4ac376a67b0be2a93a05f4fbf6e72ffab30c700f Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Tue, 21 Apr 2020 09:16:18 +0200 Subject: [PATCH 1120/1463] configs/config.facebook_fbg1701: Rename file Jenkins does not build using .config.facebook_fbg1701 on new patches. Rename the config file adding '.mboot_vboot'. Now FACEBOOK_FBG1701 and FACEBOOK_FBG1701_MBOOT_VBOOT are included in Jenkins test result. BUG=N/A TEST=Build and boot Facebook fbg1701 Change-Id: Ib54cc29e7ff34553c19fa3502872d6e7aee5fbe8 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/40557 Reviewed-by: Wim Vervoorn Tested-by: build bot (Jenkins) --- ...onfig.facebook_fbg1701 => config.facebook_fbg1701.mboot_vboot} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename configs/{config.facebook_fbg1701 => config.facebook_fbg1701.mboot_vboot} (100%) diff --git a/configs/config.facebook_fbg1701 b/configs/config.facebook_fbg1701.mboot_vboot similarity index 100% rename from configs/config.facebook_fbg1701 rename to configs/config.facebook_fbg1701.mboot_vboot From e7f176cd61a7ccb78ab9c015bb79b83ae6aaf071 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sun, 19 Jan 2020 21:42:09 +0300 Subject: [PATCH 1121/1463] amd/agesa: Make BottomIo position configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some PCI peripherals, such as discrete VGA adapters, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. 0x80000000 has been successfully boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb). Signed-off-by: Mike Banon Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38472 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/northbridge/amd/agesa/Kconfig | 11 +++++++++++ src/northbridge/amd/agesa/family14/state_machine.c | 2 ++ src/northbridge/amd/agesa/family15tn/state_machine.c | 2 ++ src/northbridge/amd/agesa/family16kb/state_machine.c | 3 +++ 4 files changed, 18 insertions(+) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 19b62f2cd8..1e0153b335 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -19,6 +19,17 @@ config NORTHBRIDGE_AMD_AGESA if NORTHBRIDGE_AMD_AGESA +config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0x80000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocate such devices. + + Declare the beginning of the 128MB-aligned MMIO region. This + option is useful when PCI peripherals requesting large address + ranges are present, for example, graphic cards. + config CONSOLE_VGA_MULTI bool default n diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index db923c5ec9..5b0040899a 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -48,6 +48,8 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { + Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000, + MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8; } void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index 85bc2587ed..439e15d75d 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -18,6 +18,8 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { + Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000, + MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8; } void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index a27962972a..be9adaff4f 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -20,6 +20,9 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { AGESA_STATUS status; + Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000, + MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8; + if (CONFIG(ENABLE_MRC_CACHE)) { status = OemInitResume(&Post->MemConfig.MemContext); if (status == AGESA_SUCCESS) From abaa1de93b36a431e5545f252cddc0e1c2cd3102 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 21 Apr 2020 10:52:48 +0200 Subject: [PATCH 1122/1463] util/scripts/ucode_h_to_bin.sh: Replace whitespace with TABs Newly added code in commit CB:25546 contains spaces instead of TABs for line indent. Replace every 4 spaces by a single TAB to match our coding guides. Change-Id: Ie3633bb42643f4abb5f1a8827a7dc2c9e023d6aa Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40564 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/scripts/ucode_h_to_bin.sh | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh index 436c0fd151..e6f4699c8f 100755 --- a/util/scripts/ucode_h_to_bin.sh +++ b/util/scripts/ucode_h_to_bin.sh @@ -41,23 +41,23 @@ unsigned int microcode[] = { EOF include_file() { - if [ "${1: -4}" == ".inc" ]; then - awk '{gsub( /h.*$/, "", $2 ); print "0x" $2 ","; }' "$1" \ - >> "${TMPFILE}.c" - else - echo "#include \"$1\"" >> "${TMPFILE}.c" - fi + if [ "${1: -4}" == ".inc" ]; then + awk '{gsub( /h.*$/, "", $2 ); print "0x" $2 ","; }' "$1" \ + >> "${TMPFILE}.c" + else + echo "#include \"$1\"" >> "${TMPFILE}.c" + fi } for UCODE in "${@:2}"; do - if [ -d "$UCODE" ]; then - for f in "$UCODE/"*.inc - do - include_file "$f" - done - else - include_file "$UCODE" - fi + if [ -d "$UCODE" ]; then + for f in "$UCODE/"*.inc + do + include_file "$f" + done + else + include_file "$UCODE" + fi done cat >> "${TMPFILE}.c" << EOF From 21530bd421ed286939c32edc8c8cc451ede2e3a7 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 21 Apr 2020 11:03:11 +0200 Subject: [PATCH 1123/1463] util/scripts/ucode_h_to_bin.sh: Drop disruptive quotes The double quotes around the remaining shell parameters '${@:2}' causes that the provided *.h files in $(CONFIG_CPU_MICROCODE_HEADER_FILES), which is a space separated list, cannot be broken down to every single file as needed but stay as a single parameter in the for-loop. Therefore, the called function 'include_file' will get a single parameter with all files which will lead to a broken C code in terms of a wrong #include-syntax. This causes the script to fail. To fix this remove the double quotes which works just fine. Change-Id: Iab7b0dc8d850973d6af764899907d383e9ec7743 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40565 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/scripts/ucode_h_to_bin.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh index e6f4699c8f..2010c48e36 100755 --- a/util/scripts/ucode_h_to_bin.sh +++ b/util/scripts/ucode_h_to_bin.sh @@ -49,7 +49,7 @@ include_file() { fi } -for UCODE in "${@:2}"; do +for UCODE in ${@:2}; do if [ -d "$UCODE" ]; then for f in "$UCODE/"*.inc do From 5171960b2367d8eb34247b9e609a5573f55b8ba1 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 21 Apr 2020 11:16:10 +0200 Subject: [PATCH 1124/1463] util/scripts/ucode_h_to_bin.sh: Fix .inc-lines with just comment There are microcodes in .inc format out in the wild which contains lines with just a comment. So these files look like the following example: ; External header dd 000000001h dd 00000001bh ... ; Data dd 000000000h ... The lines with just a comment starts with a ';' and will break the current awk formatting which is performed to reformat the content into C code style. As we are just interested in the data we can simply drop all lines that start with a ';' which sed can do pretty easy. Change-Id: I9ff5db51667672cffd9d776fb9497962b4a6083a Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40566 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/scripts/ucode_h_to_bin.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh index 2010c48e36..cb403a4978 100755 --- a/util/scripts/ucode_h_to_bin.sh +++ b/util/scripts/ucode_h_to_bin.sh @@ -42,7 +42,7 @@ EOF include_file() { if [ "${1: -4}" == ".inc" ]; then - awk '{gsub( /h.*$/, "", $2 ); print "0x" $2 ","; }' "$1" \ + sed '/^;/d' <"$1" | awk '{gsub( /h.*$/, "", $2 ); print "0x" $2 ","; }' \ >> "${TMPFILE}.c" else echo "#include \"$1\"" >> "${TMPFILE}.c" From 4cd150f5b530a88aa2778b1f1167e1c191186718 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Wed, 15 Apr 2020 16:40:33 +0800 Subject: [PATCH 1125/1463] mb/google/kukui: kakadu: update the EDID and sequence The EDID and command sequence are from BOE, the vendor. BUG=b:148997748 TEST=Boots on Chromebook Kakadu and displayed developer firmware screen successfully. Change-Id: Ieb510cb28882afc5b8023c2a57b31187e4a09fbd Signed-off-by: Scott Chao Reviewed-on: https://review.coreboot.org/c/coreboot/+/40396 Reviewed-by: Hung-Te Lin Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../panel_params/panel-BOE_TV105WUM_NW0.c | 337 +++++++++--------- 1 file changed, 166 insertions(+), 171 deletions(-) diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c index 365414acb3..976d44991a 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c @@ -10,18 +10,18 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { .panel_bits_per_color = 8, .panel_bits_per_pixel = 24, .mode = { - .pixel_clock = 156298, + .pixel_clock = 159916, .lvds_dual_channel = 0, .refresh = 60, - .ha = 1200, .hbl = 140, .hso = 60, .hspw = 24, - .va = 1920, .vbl = 24, .vso = 14, .vspw = 2, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, + .va = 1920, .vbl = 34, .vso = 20, .vspw = 4, .phsync = '-', .pvsync = '-', .x_mm = 147, .y_mm = 236, }, }, + .orientation = LB_FB_ORIENTATION_LEFT_UP, .init = { - INIT_DCS_CMD(0x10), - INIT_DELAY_CMD(34), + INIT_DELAY_CMD(24), INIT_DCS_CMD(0xB0, 0x05), INIT_DCS_CMD(0xB1, 0xE5), INIT_DCS_CMD(0xB3, 0x52), @@ -34,9 +34,9 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { INIT_DCS_CMD(0xBA, 0x87), INIT_DCS_CMD(0xBF, 0x1F), INIT_DCS_CMD(0xC0, 0x0F), - INIT_DCS_CMD(0xC2, 0x0E), + INIT_DCS_CMD(0xC2, 0x0C), INIT_DCS_CMD(0xC3, 0x02), - INIT_DCS_CMD(0xC4, 0x0E), + INIT_DCS_CMD(0xC4, 0x0C), INIT_DCS_CMD(0xC5, 0x02), INIT_DCS_CMD(0xB0, 0x01), INIT_DCS_CMD(0xE0, 0x26), @@ -69,38 +69,38 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { INIT_DCS_CMD(0xDF, 0x08), INIT_DCS_CMD(0xB0, 0x02), INIT_DCS_CMD(0xC0, 0x00), - INIT_DCS_CMD(0xC1, 0x11), - INIT_DCS_CMD(0xC2, 0x1D), - INIT_DCS_CMD(0xC3, 0x2E), - INIT_DCS_CMD(0xC4, 0x3F), - INIT_DCS_CMD(0xC5, 0x3F), - INIT_DCS_CMD(0xC6, 0x3F), - INIT_DCS_CMD(0xC7, 0x3F), - INIT_DCS_CMD(0xC8, 0x3F), - INIT_DCS_CMD(0xC9, 0x3F), - INIT_DCS_CMD(0xCA, 0x3F), - INIT_DCS_CMD(0xCB, 0x3F), - INIT_DCS_CMD(0xCC, 0x3F), - INIT_DCS_CMD(0xCD, 0x33), - INIT_DCS_CMD(0xCE, 0x32), - INIT_DCS_CMD(0xCF, 0x31), + INIT_DCS_CMD(0xC1, 0x0F), + INIT_DCS_CMD(0xC2, 0x1A), + INIT_DCS_CMD(0xC3, 0x2B), + INIT_DCS_CMD(0xC4, 0x38), + INIT_DCS_CMD(0xC5, 0x39), + INIT_DCS_CMD(0xC6, 0x38), + INIT_DCS_CMD(0xC7, 0x38), + INIT_DCS_CMD(0xC8, 0x36), + INIT_DCS_CMD(0xC9, 0x34), + INIT_DCS_CMD(0xCA, 0x35), + INIT_DCS_CMD(0xCB, 0x36), + INIT_DCS_CMD(0xCC, 0x39), + INIT_DCS_CMD(0xCD, 0x2D), + INIT_DCS_CMD(0xCE, 0x2E), + INIT_DCS_CMD(0xCF, 0x2F), INIT_DCS_CMD(0xD0, 0x07), INIT_DCS_CMD(0xD2, 0x00), - INIT_DCS_CMD(0xD3, 0x11), - INIT_DCS_CMD(0xD4, 0x1D), - INIT_DCS_CMD(0xD5, 0x2E), - INIT_DCS_CMD(0xD6, 0x3F), - INIT_DCS_CMD(0xD7, 0x3F), - INIT_DCS_CMD(0xD8, 0x3F), - INIT_DCS_CMD(0xD9, 0x3F), - INIT_DCS_CMD(0xDA, 0x3F), - INIT_DCS_CMD(0xDB, 0x3F), - INIT_DCS_CMD(0xDC, 0x3F), - INIT_DCS_CMD(0xDD, 0x3F), - INIT_DCS_CMD(0xDE, 0x3F), - INIT_DCS_CMD(0xDF, 0x33), - INIT_DCS_CMD(0xE0, 0x32), - INIT_DCS_CMD(0xE1, 0x31), + INIT_DCS_CMD(0xD3, 0x0F), + INIT_DCS_CMD(0xD4, 0x1A), + INIT_DCS_CMD(0xD5, 0x2B), + INIT_DCS_CMD(0xD6, 0x38), + INIT_DCS_CMD(0xD7, 0x39), + INIT_DCS_CMD(0xD8, 0x38), + INIT_DCS_CMD(0xD9, 0x38), + INIT_DCS_CMD(0xDA, 0x36), + INIT_DCS_CMD(0xDB, 0x34), + INIT_DCS_CMD(0xDC, 0x35), + INIT_DCS_CMD(0xDD, 0x36), + INIT_DCS_CMD(0xDE, 0x39), + INIT_DCS_CMD(0xDF, 0x2D), + INIT_DCS_CMD(0xE0, 0x2E), + INIT_DCS_CMD(0xE1, 0x2F), INIT_DCS_CMD(0xE2, 0x07), INIT_DCS_CMD(0xB0, 0x03), INIT_DCS_CMD(0xC8, 0x0B), @@ -122,90 +122,90 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { INIT_DCS_CMD(0xBC, 0x33), INIT_DCS_CMD(0xB0, 0x07), INIT_DCS_CMD(0xB1, 0x00), - INIT_DCS_CMD(0xB2, 0x02), - INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0A), INIT_DCS_CMD(0xB4, 0x1A), INIT_DCS_CMD(0xB5, 0x29), INIT_DCS_CMD(0xB6, 0x38), - INIT_DCS_CMD(0xB7, 0x58), - INIT_DCS_CMD(0xB8, 0x76), - INIT_DCS_CMD(0xB9, 0xB9), - INIT_DCS_CMD(0xBA, 0xF7), - INIT_DCS_CMD(0xBB, 0x6D), - INIT_DCS_CMD(0xBC, 0xE5), - INIT_DCS_CMD(0xBD, 0xE9), - INIT_DCS_CMD(0xBE, 0x5E), - INIT_DCS_CMD(0xBF, 0xD6), - INIT_DCS_CMD(0xC0, 0x15), - INIT_DCS_CMD(0xC1, 0x51), - INIT_DCS_CMD(0xC2, 0x71), - INIT_DCS_CMD(0xC3, 0x90), - INIT_DCS_CMD(0xC4, 0x9C), - INIT_DCS_CMD(0xC5, 0xA8), - INIT_DCS_CMD(0xC6, 0xB5), - INIT_DCS_CMD(0xC7, 0xBC), - INIT_DCS_CMD(0xC8, 0xC0), + INIT_DCS_CMD(0xB7, 0x5A), + INIT_DCS_CMD(0xB8, 0x79), + INIT_DCS_CMD(0xB9, 0xBF), + INIT_DCS_CMD(0xBA, 0x05), + INIT_DCS_CMD(0xBB, 0x88), + INIT_DCS_CMD(0xBC, 0x14), + INIT_DCS_CMD(0xBD, 0x18), + INIT_DCS_CMD(0xBE, 0x97), + INIT_DCS_CMD(0xBF, 0x11), + INIT_DCS_CMD(0xC0, 0x4B), + INIT_DCS_CMD(0xC1, 0x82), + INIT_DCS_CMD(0xC2, 0x9B), + INIT_DCS_CMD(0xC3, 0xB6), + INIT_DCS_CMD(0xC4, 0xC3), + INIT_DCS_CMD(0xC5, 0xD0), + INIT_DCS_CMD(0xC6, 0xDB), + INIT_DCS_CMD(0xC7, 0xE1), + INIT_DCS_CMD(0xC8, 0xE4), INIT_DCS_CMD(0xC9, 0x00), INIT_DCS_CMD(0xCA, 0x00), - INIT_DCS_CMD(0xCB, 0x05), - INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), INIT_DCS_CMD(0xCD, 0xFF), INIT_DCS_CMD(0xCE, 0xFF), INIT_DCS_CMD(0xB0, 0x08), INIT_DCS_CMD(0xB1, 0x00), - INIT_DCS_CMD(0xB2, 0x04), - INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB2, 0x03), + INIT_DCS_CMD(0xB3, 0x0A), INIT_DCS_CMD(0xB4, 0x1A), INIT_DCS_CMD(0xB5, 0x29), INIT_DCS_CMD(0xB6, 0x38), - INIT_DCS_CMD(0xB7, 0x58), - INIT_DCS_CMD(0xB8, 0x76), - INIT_DCS_CMD(0xB9, 0xB8), - INIT_DCS_CMD(0xBA, 0xF7), - INIT_DCS_CMD(0xBB, 0x6C), - INIT_DCS_CMD(0xBC, 0xE3), - INIT_DCS_CMD(0xBD, 0xE7), - INIT_DCS_CMD(0xBE, 0x5C), - INIT_DCS_CMD(0xBF, 0xD3), - INIT_DCS_CMD(0xC0, 0x10), - INIT_DCS_CMD(0xC1, 0x4C), - INIT_DCS_CMD(0xC2, 0x6A), - INIT_DCS_CMD(0xC3, 0x8A), - INIT_DCS_CMD(0xC4, 0x96), - INIT_DCS_CMD(0xC5, 0xA2), - INIT_DCS_CMD(0xC6, 0xAE), - INIT_DCS_CMD(0xC7, 0xB4), - INIT_DCS_CMD(0xC8, 0xB8), + INIT_DCS_CMD(0xB7, 0x5A), + INIT_DCS_CMD(0xB8, 0x7A), + INIT_DCS_CMD(0xB9, 0xC1), + INIT_DCS_CMD(0xBA, 0x07), + INIT_DCS_CMD(0xBB, 0x8B), + INIT_DCS_CMD(0xBC, 0x17), + INIT_DCS_CMD(0xBD, 0x1B), + INIT_DCS_CMD(0xBE, 0x99), + INIT_DCS_CMD(0xBF, 0x13), + INIT_DCS_CMD(0xC0, 0x4C), + INIT_DCS_CMD(0xC1, 0x84), + INIT_DCS_CMD(0xC2, 0x9D), + INIT_DCS_CMD(0xC3, 0xB7), + INIT_DCS_CMD(0xC4, 0xC4), + INIT_DCS_CMD(0xC5, 0xD0), + INIT_DCS_CMD(0xC6, 0xDB), + INIT_DCS_CMD(0xC7, 0xE1), + INIT_DCS_CMD(0xC8, 0xE4), INIT_DCS_CMD(0xC9, 0x00), INIT_DCS_CMD(0xCA, 0x00), - INIT_DCS_CMD(0xCB, 0x05), - INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), INIT_DCS_CMD(0xCD, 0xFF), INIT_DCS_CMD(0xCE, 0xFF), INIT_DCS_CMD(0xB0, 0x09), INIT_DCS_CMD(0xB1, 0x04), INIT_DCS_CMD(0xB2, 0x04), - INIT_DCS_CMD(0xB3, 0x0C), - INIT_DCS_CMD(0xB4, 0x1C), - INIT_DCS_CMD(0xB5, 0x2D), - INIT_DCS_CMD(0xB6, 0x3C), - INIT_DCS_CMD(0xB7, 0x5F), + INIT_DCS_CMD(0xB3, 0x09), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x2B), + INIT_DCS_CMD(0xB6, 0x3A), + INIT_DCS_CMD(0xB7, 0x5D), INIT_DCS_CMD(0xB8, 0x80), - INIT_DCS_CMD(0xB9, 0xC8), - INIT_DCS_CMD(0xBA, 0x0D), - INIT_DCS_CMD(0xBB, 0x8A), - INIT_DCS_CMD(0xBC, 0x10), - INIT_DCS_CMD(0xBD, 0x14), - INIT_DCS_CMD(0xBE, 0x91), - INIT_DCS_CMD(0xBF, 0x13), - INIT_DCS_CMD(0xC0, 0x53), - INIT_DCS_CMD(0xC1, 0x93), - INIT_DCS_CMD(0xC2, 0xAB), - INIT_DCS_CMD(0xC3, 0xC6), - INIT_DCS_CMD(0xC4, 0xD6), - INIT_DCS_CMD(0xC5, 0xE4), - INIT_DCS_CMD(0xC6, 0xF3), - INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xB9, 0xCA), + INIT_DCS_CMD(0xBA, 0x13), + INIT_DCS_CMD(0xBB, 0x9D), + INIT_DCS_CMD(0xBC, 0x30), + INIT_DCS_CMD(0xBD, 0x34), + INIT_DCS_CMD(0xBE, 0xBB), + INIT_DCS_CMD(0xBF, 0x30), + INIT_DCS_CMD(0xC0, 0x6A), + INIT_DCS_CMD(0xC1, 0xA1), + INIT_DCS_CMD(0xC2, 0xBC), + INIT_DCS_CMD(0xC3, 0xD4), + INIT_DCS_CMD(0xC4, 0xE0), + INIT_DCS_CMD(0xC5, 0xEB), + INIT_DCS_CMD(0xC6, 0xF6), + INIT_DCS_CMD(0xC7, 0xFA), INIT_DCS_CMD(0xC8, 0xFC), INIT_DCS_CMD(0xC9, 0x00), INIT_DCS_CMD(0xCA, 0x00), @@ -215,90 +215,90 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { INIT_DCS_CMD(0xCE, 0xFF), INIT_DCS_CMD(0xB0, 0x0A), INIT_DCS_CMD(0xB1, 0x00), - INIT_DCS_CMD(0xB2, 0x02), - INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0A), INIT_DCS_CMD(0xB4, 0x1A), INIT_DCS_CMD(0xB5, 0x29), INIT_DCS_CMD(0xB6, 0x38), - INIT_DCS_CMD(0xB7, 0x58), - INIT_DCS_CMD(0xB8, 0x76), - INIT_DCS_CMD(0xB9, 0xB9), - INIT_DCS_CMD(0xBA, 0xF7), - INIT_DCS_CMD(0xBB, 0x6D), - INIT_DCS_CMD(0xBC, 0xE5), - INIT_DCS_CMD(0xBD, 0xE9), - INIT_DCS_CMD(0xBE, 0x5E), - INIT_DCS_CMD(0xBF, 0xD6), - INIT_DCS_CMD(0xC0, 0x15), - INIT_DCS_CMD(0xC1, 0x51), - INIT_DCS_CMD(0xC2, 0x71), - INIT_DCS_CMD(0xC3, 0x90), - INIT_DCS_CMD(0xC4, 0x9C), - INIT_DCS_CMD(0xC5, 0xA8), - INIT_DCS_CMD(0xC6, 0xB5), - INIT_DCS_CMD(0xC7, 0xBC), - INIT_DCS_CMD(0xC8, 0xC0), + INIT_DCS_CMD(0xB7, 0x5A), + INIT_DCS_CMD(0xB8, 0x79), + INIT_DCS_CMD(0xB9, 0xBF), + INIT_DCS_CMD(0xBA, 0x05), + INIT_DCS_CMD(0xBB, 0x88), + INIT_DCS_CMD(0xBC, 0x14), + INIT_DCS_CMD(0xBD, 0x18), + INIT_DCS_CMD(0xBE, 0x97), + INIT_DCS_CMD(0xBF, 0x11), + INIT_DCS_CMD(0xC0, 0x4B), + INIT_DCS_CMD(0xC1, 0x82), + INIT_DCS_CMD(0xC2, 0x9B), + INIT_DCS_CMD(0xC3, 0xB6), + INIT_DCS_CMD(0xC4, 0xC3), + INIT_DCS_CMD(0xC5, 0xD0), + INIT_DCS_CMD(0xC6, 0xDB), + INIT_DCS_CMD(0xC7, 0xE1), + INIT_DCS_CMD(0xC8, 0xE4), INIT_DCS_CMD(0xC9, 0x00), INIT_DCS_CMD(0xCA, 0x00), - INIT_DCS_CMD(0xCB, 0x05), - INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), INIT_DCS_CMD(0xCD, 0xFF), INIT_DCS_CMD(0xCE, 0xFF), INIT_DCS_CMD(0xB0, 0x0B), INIT_DCS_CMD(0xB1, 0x00), - INIT_DCS_CMD(0xB2, 0x04), - INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB2, 0x03), + INIT_DCS_CMD(0xB3, 0x0A), INIT_DCS_CMD(0xB4, 0x1A), INIT_DCS_CMD(0xB5, 0x29), INIT_DCS_CMD(0xB6, 0x38), - INIT_DCS_CMD(0xB7, 0x58), - INIT_DCS_CMD(0xB8, 0x76), - INIT_DCS_CMD(0xB9, 0xB8), - INIT_DCS_CMD(0xBA, 0xF7), - INIT_DCS_CMD(0xBB, 0x6C), - INIT_DCS_CMD(0xBC, 0xE3), - INIT_DCS_CMD(0xBD, 0xE7), - INIT_DCS_CMD(0xBE, 0x5C), - INIT_DCS_CMD(0xBF, 0xD3), - INIT_DCS_CMD(0xC0, 0x10), - INIT_DCS_CMD(0xC1, 0x4C), - INIT_DCS_CMD(0xC2, 0x6A), - INIT_DCS_CMD(0xC3, 0x8A), - INIT_DCS_CMD(0xC4, 0x96), - INIT_DCS_CMD(0xC5, 0xA2), - INIT_DCS_CMD(0xC6, 0xAE), - INIT_DCS_CMD(0xC7, 0xB4), - INIT_DCS_CMD(0xC8, 0xB8), + INIT_DCS_CMD(0xB7, 0x5A), + INIT_DCS_CMD(0xB8, 0x7A), + INIT_DCS_CMD(0xB9, 0xC1), + INIT_DCS_CMD(0xBA, 0x07), + INIT_DCS_CMD(0xBB, 0x8B), + INIT_DCS_CMD(0xBC, 0x17), + INIT_DCS_CMD(0xBD, 0x1B), + INIT_DCS_CMD(0xBE, 0x99), + INIT_DCS_CMD(0xBF, 0x13), + INIT_DCS_CMD(0xC0, 0x4C), + INIT_DCS_CMD(0xC1, 0x84), + INIT_DCS_CMD(0xC2, 0x9D), + INIT_DCS_CMD(0xC3, 0xB7), + INIT_DCS_CMD(0xC4, 0xC4), + INIT_DCS_CMD(0xC5, 0xD0), + INIT_DCS_CMD(0xC6, 0xDB), + INIT_DCS_CMD(0xC7, 0xE1), + INIT_DCS_CMD(0xC8, 0xE4), INIT_DCS_CMD(0xC9, 0x00), INIT_DCS_CMD(0xCA, 0x00), - INIT_DCS_CMD(0xCB, 0x05), - INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), INIT_DCS_CMD(0xCD, 0xFF), INIT_DCS_CMD(0xCE, 0xFF), INIT_DCS_CMD(0xB0, 0x0C), INIT_DCS_CMD(0xB1, 0x04), INIT_DCS_CMD(0xB2, 0x04), - INIT_DCS_CMD(0xB3, 0x0C), - INIT_DCS_CMD(0xB4, 0x1C), - INIT_DCS_CMD(0xB5, 0x2D), - INIT_DCS_CMD(0xB6, 0x3C), - INIT_DCS_CMD(0xB7, 0x5F), + INIT_DCS_CMD(0xB3, 0x09), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x2B), + INIT_DCS_CMD(0xB6, 0x3A), + INIT_DCS_CMD(0xB7, 0x5D), INIT_DCS_CMD(0xB8, 0x80), - INIT_DCS_CMD(0xB9, 0xC8), - INIT_DCS_CMD(0xBA, 0x0D), - INIT_DCS_CMD(0xBB, 0x8A), - INIT_DCS_CMD(0xBC, 0x10), - INIT_DCS_CMD(0xBD, 0x14), - INIT_DCS_CMD(0xBE, 0x91), - INIT_DCS_CMD(0xBF, 0x13), - INIT_DCS_CMD(0xC0, 0x53), - INIT_DCS_CMD(0xC1, 0x93), - INIT_DCS_CMD(0xC2, 0xAB), - INIT_DCS_CMD(0xC3, 0xC6), - INIT_DCS_CMD(0xC4, 0xD6), - INIT_DCS_CMD(0xC5, 0xE4), - INIT_DCS_CMD(0xC6, 0xF3), - INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xB9, 0xCA), + INIT_DCS_CMD(0xBA, 0x13), + INIT_DCS_CMD(0xBB, 0x9D), + INIT_DCS_CMD(0xBC, 0x30), + INIT_DCS_CMD(0xBD, 0x34), + INIT_DCS_CMD(0xBE, 0xBB), + INIT_DCS_CMD(0xBF, 0x30), + INIT_DCS_CMD(0xC0, 0x6A), + INIT_DCS_CMD(0xC1, 0xA1), + INIT_DCS_CMD(0xC2, 0xBC), + INIT_DCS_CMD(0xC3, 0xD4), + INIT_DCS_CMD(0xC4, 0xE0), + INIT_DCS_CMD(0xC5, 0xEB), + INIT_DCS_CMD(0xC6, 0xF6), + INIT_DCS_CMD(0xC7, 0xFA), INIT_DCS_CMD(0xC8, 0xFC), INIT_DCS_CMD(0xC9, 0x00), INIT_DCS_CMD(0xCA, 0x00), @@ -306,16 +306,11 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { INIT_DCS_CMD(0xCC, 0xAF), INIT_DCS_CMD(0xCD, 0xFF), INIT_DCS_CMD(0xCE, 0xFF), - INIT_DELAY_CMD(100), INIT_DCS_CMD(0xB0, 0x00), INIT_DCS_CMD(0xB3, 0x08), INIT_DCS_CMD(0xB0, 0x04), INIT_DCS_CMD(0xB8, 0x68), - INIT_DELAY_CMD(10), - INIT_DCS_CMD(0x11), - INIT_DELAY_CMD(100), - INIT_DCS_CMD(0x29), - INIT_DELAY_CMD(50), + INIT_DELAY_CMD(150), INIT_END_CMD, }, }; From 86803784d3a459170a1e73dfbd1ecdcfc0d853d5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 16 Apr 2020 23:13:28 -0700 Subject: [PATCH 1126/1463] device: Add checks for NULL in device_const.c functions This change checks to ensure that device/path passed into any of the functions in device_const.c is not NULL. Since NULL is not expected to be passed into these functions, this change adds a die() call in case the assumption is broken. Change-Id: I1ad8d2bcb9d0546104c5e065af1eeff331cdf96d Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40475 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons --- src/device/device_const.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/device/device_const.c b/src/device/device_const.c index c59c5e9b69..2e0ccc4c3b 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -86,6 +87,13 @@ static int path_eq(const struct device_path *path1, { int equal = 0; + if (!path1 || !path2) { + assert(path1); + assert(path2); + /* Return 0 in case assert is considered non-fatal. */ + return 0; + } + if (path1->type != path2->type) return 0; @@ -156,6 +164,13 @@ DEVTREE_CONST struct device *find_dev_path( const struct bus *parent, const struct device_path *path) { DEVTREE_CONST struct device *child; + + if (!parent) { + assert(0); + /* Return NULL in case asserts are considered non-fatal. */ + return NULL; + } + for (child = parent->children; child; child = child->sibling) { if (path_eq(path, &child->path)) break; From 7778e5c55fbf1399a7d80aac38890a8351fcc573 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 16 Apr 2020 08:25:58 -0700 Subject: [PATCH 1127/1463] device: Add a helper to find device behind a PCI-to-PCI bridge device This change adds a helper function to find PCI device with dev# and function# behind a PCI-to-PCI bridge device. BUG=b:153858769 BRANCH=None TEST=None Signed-off-by: Furquan Shaikh Change-Id: Ie5672b35cda66431a0f1977f217bdf61d3012ace Reviewed-on: https://review.coreboot.org/c/coreboot/+/40474 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/device_const.c | 13 +++++++++++++ src/include/device/device.h | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/src/device/device_const.c b/src/device/device_const.c index 2e0ccc4c3b..de404dc0d1 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -232,6 +232,19 @@ DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) return pcidev_path_on_root(PCI_DEVFN(dev, fn)); } +DEVTREE_CONST struct device *pcidev_path_behind_pci2pci_bridge( + const struct device *bridge, + pci_devfn_t devfn) +{ + if (!bridge || (bridge->path.type != DEVICE_PATH_PCI)) { + assert(0); + /* Return NULL in case asserts are non-fatal. */ + return NULL; + } + + return pcidev_path_behind(bridge->link_list, devfn); +} + DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func) { DEVTREE_CONST struct device *dev = pcidev_path_on_root(devfn); diff --git a/src/include/device/device.h b/src/include/device/device.h index 4e9c594bc0..a33702a234 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -293,6 +293,10 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); +/* Find PCI device with given D#:F# sitting behind the given PCI-to-PCI bridge device. */ +DEVTREE_CONST struct device *pcidev_path_behind_pci2pci_bridge( + const struct device *bridge, + pci_devfn_t devfn); /* To be deprecated, avoid using. * From eec30f7beae074c3f80a182cc2950ed8e4f0a640 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 20 Apr 2020 16:38:21 -0700 Subject: [PATCH 1128/1463] ec/google/chromeec: Fix acpi_name() for Chrome EC device In ACPI tables, Chrome EC device (CREC - HID GOOG0004) is a child of EC device (EC0 - HID PNP0C09). However, in coreboot device tree, there is no separate chip/device for EC0. Thus, acpi_name() needs to return EC0.CREC as the ACPI name for the Chrome EC device. By returning the ACPI name as EC0.CREC, all devices that live under Chrome EC device can simply call acpi_device_path()/acpi_device_scope() to emit the right path/scope. In the future, if we ever add a special chip driver for handling EC0 (HID PNP0C09), then the ACPI name for Chrome EC can be fixed to return CREC. BUG=b:154290952 TEST=Verified that acpi_device_path()/acpi_device_scope() return the correct name for Chrome EC device. Signed-off-by: Furquan Shaikh Change-Id: Iec4b0226d1e98ddeb0f8ed8b89477fc4f453d221 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40513 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec_acpi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index a7e3ae559d..79e3f4bfa1 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -17,13 +17,21 @@ #include "ec.h" #include "ec_commands.h" -#define GOOGLE_CHROMEEC_USBC_DEVICE_PARENT "CREC" #define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" const char *google_chromeec_acpi_name(const struct device *dev) { - return "EC0"; + /* + * Chrome EC device (CREC - GOOG0004) is really a child of EC device (EC - PNP0C09) in + * ACPI tables. However, in coreboot device tree, there is no separate chip/device for + * EC0. Thus, Chrome EC device needs to return "EC0.CREC" as the ACPI name so that the + * callers can get the correct acpi device path/scope for this device. + * + * If we ever enable a separate driver for generating AML for EC0 device, then this + * function needs to be updated to return "CREC". + */ + return "EC0.CREC"; } static const char *power_role_to_str(enum ec_pd_power_role_caps power_role) @@ -190,8 +198,7 @@ static void fill_ssdt_typec_device(struct device *dev) if (google_chromeec_get_num_pd_ports(&num_ports)) return; - /* Add TypeC device under the existing device + ".CREC" scope */ - acpigen_write_scope(acpi_device_path_join(dev, GOOGLE_CHROMEEC_USBC_DEVICE_PARENT)); + acpigen_write_scope(acpi_device_path(dev)); acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " From b77963c423dbef18ac06028c275fb4acf4b61ad9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 19 Apr 2020 17:38:20 -0700 Subject: [PATCH 1129/1463] ec/google/chromeec: Add .scan_bus() callback for Chrome EC device This change adds scan_static_bus() as .scan_bus() callback for Chrome EC device which allows scanning of devices sitting behind the EC using the topology provided by mainboard's devicetree.cb. BUG=b:154290952 TEST=Verified with follow-up changes that devices behind EC are scanned correctly. Signed-off-by: Furquan Shaikh Change-Id: Id3630db56774fba1e3fc53bf349588c4c585773b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40514 Reviewed-by: Aaron Durbin Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec_lpc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 232df8e06a..bc8682bce1 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -439,6 +439,7 @@ static struct device_operations ops = { .init = lpc_ec_init, .read_resources = lpc_ec_read_resources, .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = google_chromeec_acpi_name, .acpi_fill_ssdt = google_chromeec_fill_ssdt_generator, From 93193a0f09500e4233b6c8466a1ed48b83000a05 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Mon, 20 Apr 2020 17:56:00 -0700 Subject: [PATCH 1130/1463] arch/x86/acpigen_ps2_keybd: Add JP and UK specific keymaps Add keymaps for keys that are not present in US keyboards. Change-Id: I1ad4c483e81438456533b4c071a4a56cbee88f9c Signed-off-by: Rajat Jain Reviewed-on: https://review.coreboot.org/c/coreboot/+/40542 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/arch/x86/acpigen_ps2_keybd.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/acpigen_ps2_keybd.c b/src/arch/x86/acpigen_ps2_keybd.c index 1573de8924..7943f9a158 100644 --- a/src/arch/x86/acpigen_ps2_keybd.c +++ b/src/arch/x86/acpigen_ps2_keybd.c @@ -110,6 +110,7 @@ static uint32_t rest_of_keymaps[] = { KEYMAP(0x0b, KEY_0), KEYMAP(0x0c, KEY_MINUS), KEYMAP(0x0d, KEY_EQUAL), + KEYMAP(0x7d, KEY_YEN), /* JP keyboards only */ KEYMAP(0x0e, KEY_BACKSPACE), /* Row-2 */ KEYMAP(0x0f, KEY_TAB), @@ -127,7 +128,7 @@ static uint32_t rest_of_keymaps[] = { KEYMAP(0x1b, KEY_RIGHTBRACE), KEYMAP(0x2b, KEY_BACKSLASH), /* Row-3 */ - KEYMAP(0xdb, KEY_LEFTMETA), + KEYMAP(0xdb, KEY_LEFTMETA), /* Search Key */ KEYMAP(0x1e, KEY_A), KEYMAP(0x1f, KEY_S), KEYMAP(0x20, KEY_D), @@ -142,6 +143,7 @@ static uint32_t rest_of_keymaps[] = { KEYMAP(0x1c, KEY_ENTER), /* Row-4 */ KEYMAP(0x2a, KEY_LEFTSHIFT), + KEYMAP(0x56, KEY_102ND), /* UK keyboards only */ KEYMAP(0x2c, KEY_Z), KEYMAP(0x2d, KEY_X), KEYMAP(0x2e, KEY_C), @@ -152,11 +154,14 @@ static uint32_t rest_of_keymaps[] = { KEYMAP(0x33, KEY_COMMA), KEYMAP(0x34, KEY_DOT), KEYMAP(0x35, KEY_SLASH), + KEYMAP(0x73, KEY_RO), /* JP keyboards only */ KEYMAP(0x36, KEY_RIGHTSHIFT), /* Row-5 */ KEYMAP(0x1d, KEY_LEFTCTRL), KEYMAP(0x38, KEY_LEFTALT), + KEYMAP(0x7b, KEY_MUHENKAN), /* JP keyboards only */ KEYMAP(0x39, KEY_SPACE), + KEYMAP(0x79, KEY_HENKAN), /* JP keyboards only */ KEYMAP(0xb8, KEY_RIGHTALT), KEYMAP(0x9d, KEY_RIGHTCTRL), /* Arrow keys */ From 38b349cb35738377cf42b71afa9e5d66e1a8eb4b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 19 Apr 2020 17:40:22 -0700 Subject: [PATCH 1131/1463] ec/google/chromeec: Add driver for i2c_tunnel device under Chrome EC This change enables support for generating ACPI nodes for I2C tunnel for any GOOG0012 device that is sitting behind the Chrome EC. It accepts a config "remote_bus" which allows mainboard to configure the id of the remote bus that is being tunneled. BUG=b:154290952 BRANCH=None TEST=Verified that SSDT node for I2C tunnel behind Chrome EC is generated correctly. Signed-off-by: Furquan Shaikh Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/40515 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Tim Wawrzynczak --- src/ec/google/chromeec/Kconfig | 6 ++ src/ec/google/chromeec/Makefile.inc | 2 + src/ec/google/chromeec/i2c_tunnel/Kconfig | 6 ++ .../google/chromeec/i2c_tunnel/Makefile.inc | 1 + src/ec/google/chromeec/i2c_tunnel/chip.h | 16 +++++ .../google/chromeec/i2c_tunnel/i2c_tunnel.c | 71 +++++++++++++++++++ 6 files changed, 102 insertions(+) create mode 100644 src/ec/google/chromeec/i2c_tunnel/Kconfig create mode 100644 src/ec/google/chromeec/i2c_tunnel/Makefile.inc create mode 100644 src/ec/google/chromeec/i2c_tunnel/chip.h create mode 100644 src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 554677c387..461587800b 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -196,3 +196,9 @@ config EC_GOOGLE_CHROMEEC_SWITCHES help Enable support for Chrome OS mode switches provided by the Chrome OS EC. + +if EC_GOOGLE_CHROMEEC + +source "src/ec/google/chromeec/*/Kconfig" + +endif diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 590b131355..b11f5c8507 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) +subdirs-y += i2c_tunnel + bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c diff --git a/src/ec/google/chromeec/i2c_tunnel/Kconfig b/src/ec/google/chromeec/i2c_tunnel/Kconfig new file mode 100644 index 0000000000..20169fde0f --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/Kconfig @@ -0,0 +1,6 @@ +config EC_GOOGLE_CHROMEEC_I2C_TUNNEL + bool + depends on HAVE_ACPI_TABLES + help + This enables the Cros EC I2C tunnel driver that is required to fill the + SSDT nodes for the I2C tunnel used by the mainboard. diff --git a/src/ec/google/chromeec/i2c_tunnel/Makefile.inc b/src/ec/google/chromeec/i2c_tunnel/Makefile.inc new file mode 100644 index 0000000000..85e0fba127 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C_TUNNEL) += i2c_tunnel.c diff --git a/src/ec/google/chromeec/i2c_tunnel/chip.h b/src/ec/google/chromeec/i2c_tunnel/chip.h new file mode 100644 index 0000000000..01d52bd0b2 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ +#define __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ + +struct ec_google_chromeec_i2c_tunnel_config { + /* ACPI device name */ + const char *name; + /* ACPI _UID */ + unsigned int uid; + /* EC I2C bus number we tunnel to on the other side. */ + unsigned int remote_bus; +}; + +#endif /* __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ */ diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c new file mode 100644 index 0000000000..51375f8f22 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define CROS_EC_I2C_TUNNEL_HID "GOOG0012" +#define CROS_EC_I2C_TUNNEL_DDN "Cros EC I2C Tunnel" + +static void crosec_i2c_tunnel_fill_ssdt(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; + struct acpi_dp *dsd; + + if (!dev->enabled || !scope || !cfg) + return; + + acpigen_write_scope(scope); + + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", CROS_EC_I2C_TUNNEL_HID); + acpigen_write_name_integer("_UID", cfg->uid); + acpigen_write_name_string("_DDN", CROS_EC_I2C_TUNNEL_DDN); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "google,remote-bus", cfg->remote_bus); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), CROS_EC_I2C_TUNNEL_DDN, + dev_path(dev)); +} + +static const char *crosec_i2c_tunnel_acpi_name(const struct device *dev) +{ + struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; + static char name[5]; + + if (cfg->name) + return cfg->name; + + snprintf(name, sizeof(name), "TUN%X", dev->path.generic.id); + return name; +} + +static struct device_operations crosec_i2c_tunnel_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = crosec_i2c_tunnel_acpi_name, + .acpi_fill_ssdt = crosec_i2c_tunnel_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void crosec_i2c_tunnel_enable(struct device *dev) +{ + dev->ops = &crosec_i2c_tunnel_ops; +} + +struct chip_operations ec_google_chromeec_i2c_tunnel_ops = { + CHIP_NAME("CrosEC I2C Tunnel Device") + .enable_dev = crosec_i2c_tunnel_enable +}; From 1f3055aa36655cce731dcc8f33a21b011cec14eb Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 20 Apr 2020 17:59:50 -0700 Subject: [PATCH 1132/1463] device: Add helper function to find matching device on bus This change adds a helper function dev_find_matching_device_on_bus() which scans all the child devices on the given bus and calls a match function provided by the caller. It returns the first device that the match function returns true for, else NULL if no such device is found. Change-Id: I2e3332c0a175ab995c523f078f29a9f498f17931 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40543 Reviewed-by: Aaron Durbin Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/device/device_const.c | 13 +++++++++++++ src/include/device/device.h | 13 +++++++++++++ 2 files changed, 26 insertions(+) diff --git a/src/device/device_const.c b/src/device/device_const.c index de404dc0d1..add253b511 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -70,6 +70,19 @@ DEVTREE_CONST struct device *dev_find_path( return result; } +DEVTREE_CONST struct device *dev_find_matching_device_on_bus(const struct bus *bus, + match_device_fn fn) +{ + DEVTREE_CONST struct device *child = NULL; + + while ((child = dev_bus_each_child(bus, child)) != NULL) { + if (fn(child)) + break; + } + + return child; +} + /** * Given a device pointer, find the next PCI device. * diff --git a/src/include/device/device.h b/src/include/device/device.h index a33702a234..4983b486a4 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -207,6 +207,19 @@ DEVTREE_CONST struct device *dev_find_path( struct device *dev_find_lapic(unsigned int apic_id); int dev_count_cpu(void); +/* + * Signature for matching function that is used by dev_find_matching_device_on_bus() to decide + * if the device being considered is the one that matches the caller's criteria. This function + * is supposed to return true if the provided device matches the criteria, else false. + */ +typedef bool (*match_device_fn)(DEVTREE_CONST struct device *dev); +/* + * Returns the first device on the bus that the match_device_fn returns true for. If no such + * device is found, it returns NULL. + */ +DEVTREE_CONST struct device *dev_find_matching_device_on_bus(const struct bus *bus, + match_device_fn fn); + struct device *add_cpu_device(struct bus *cpu_bus, unsigned int apic_id, int enabled); void set_cpu_topology(struct device *cpu, unsigned int node, From 16a29e53ff63ac2b6431e85552004c49386d50db Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Thu, 5 Mar 2020 10:59:32 -0800 Subject: [PATCH 1133/1463] Update vboot submodule to upstream master Updating from commit id 46ff62c3: vboot: stop reading from ACPI for wpsw_boot to commit id 55154620: vboot: Add screens for recovery using disk This brings in 37 new commits. Signed-off-by: Daisuke Nojiri Change-Id: Ie184cbe6cc18cea540966d5801472ae821ea3e86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40503 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 46ff62c31c..55154620f4 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 46ff62c31c1d815196fa990e613e1e6e229f8ce2 +Subproject commit 55154620f4aa3bba9eaaf09f5186a52a48720025 From 5feef37de8fa2da9ca0b5df48bdf470c248cc0cb Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 14 Apr 2020 17:33:40 -0700 Subject: [PATCH 1134/1463] Puff: Enable VBOOT_EARLY_EC_SYNC Romstage is now where software sync is performed for chromebooks. EFS2 has been ported to romstage from Depthcharge. Puff should follow. This patch enables CONFIG_EARLY_EC_SYNC and disables CONFIG_VBOOT_EC_EFS. EFS2 will be done in romstage. BUG=b:147298634, chromium:1045217 BRANCH=none TEST=Verify software sync succeeds on Puff. Signed-off-by: Daisuke Nojiri Change-Id: I8d7c25f8281496c7adb282f5d4e0fc192d746e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40390 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 2 +- src/mainboard/google/hatch/Kconfig.name | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b284ffecdb..11137bde6e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -141,13 +141,13 @@ config VARIANT_DIR config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_EARLY_EC_SYNC endif # BOARD_GOOGLE_BASEBOARD_HATCH if BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP config VBOOT - select VBOOT_EARLY_EC_SYNC select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 0713d13917..de9bcb53b1 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -88,7 +88,6 @@ config BOARD_GOOGLE_PUFF select BOARD_ROMSIZE_KB_32768 select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD - select VBOOT_EC_EFS config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" From d9f26edfec760ff81f88f164fc0e601fe8e20e3e Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 21 Apr 2020 15:13:07 -0700 Subject: [PATCH 1135/1463] vboot: Add permission check for kernel space This patch restores the permission check for the kernel space which was dropped when read_space_kernel was moved from Depthcharge by CL:2155429. BUG=chromium:1045217, chromium:1020578 BRANCH=none TEST=none Signed-off-by: dnojiri Change-Id: If6d487940f39865cadc0ca9d5de6e055ad3e017d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40579 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/security/tpm/tss.h | 5 +++++ src/security/tpm/tss/tcg-1.2/tss.c | 19 +++++++++++++++++++ src/security/vboot/secdata_tpm.c | 22 ++++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 5237387a74..57f3b24847 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -197,4 +197,9 @@ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, */ uint32_t tlcl_disable_platform_hierarchy(void); +/** + * Get the permission bits for the NVRAM space with |index|. + */ +uint32_t tlcl_get_permissions(uint32_t index, uint32_t *permissions); + #endif /* TSS_H_ */ diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 9bc72d2733..ea3f94d5f8 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -359,3 +359,22 @@ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, kPcrDigestLength); return result; } + +uint32_t tlcl_get_permissions(uint32_t index, uint32_t *permissions) +{ + struct s_tpm_getpermissions_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint8_t *nvdata; + uint32_t result; + uint32_t size; + + memcpy(&cmd, &tpm_getpermissions_cmd, sizeof(cmd)); + to_tpm_uint32(cmd.buffer + tpm_getpermissions_cmd.index, index); + result = tlcl_send_receive(cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; + + nvdata = response + kTpmResponseHeaderLength + sizeof(size); + from_tpm_uint32(nvdata + kNvDataPublicPermissionsOffset, permissions); + return result; +} diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index d666ae8a5e..37665bc23d 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -36,6 +36,8 @@ #include #include #include +#include +#include #include #include @@ -68,6 +70,26 @@ static uint32_t read_space_firmware(struct vb2_context *ctx) uint32_t antirollback_read_space_kernel(struct vb2_context *ctx) { + if (!CONFIG(TPM2)) { + /* + * Before reading the kernel space, verify its permissions. If + * the kernel space has the wrong permission, we give up. This + * will need to be fixed by the recovery kernel. We will have + * to worry about this because at any time (even with PP turned + * off) the TPM owner can remove and redefine a PP-protected + * space (but not write to it). + */ + uint32_t perms; + + RETURN_ON_FAILURE(tlcl_get_permissions(KERNEL_NV_INDEX, + &perms)); + if (perms != TPM_NV_PER_PPWRITE) { + printk(BIOS_ERR, + "TPM: invalid secdata_kernel permissions\n"); + return TPM_E_CORRUPTED_STATE; + } + } + uint8_t size = VB2_SECDATA_KERNEL_MIN_SIZE; RETURN_ON_FAILURE(tlcl_read(KERNEL_NV_INDEX, ctx->secdata_kernel, From 21a4053fde87801b42a0de39d5b6536c1ed4b475 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 21 Apr 2020 16:03:53 -0700 Subject: [PATCH 1136/1463] rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/assembly_entry.S | 2 +- src/arch/x86/memlayout.ld | 2 +- src/commonlib/storage/sdhci.c | 2 +- src/drivers/i2c/tpm/cr50.c | 2 +- src/drivers/spi/tpm/tpm.c | 2 +- src/drivers/usb/ehci_debug.c | 2 +- src/include/cbmem.h | 2 +- src/include/console/cbmem_console.h | 4 +-- src/include/console/console.h | 6 ++--- src/include/console/uart.h | 4 +-- src/include/console/usb.h | 2 +- src/include/memlayout.h | 2 +- src/include/rules.h | 29 ++++++++++++++-------- src/lib/cbfs.c | 8 +++--- src/mainboard/google/deltaur/chromeos.c | 2 +- src/mainboard/google/drallion/chromeos.c | 2 +- src/mainboard/google/sarien/chromeos.c | 2 +- src/security/vboot/misc.h | 2 +- src/soc/mediatek/mt8173/flash_controller.c | 2 +- 19 files changed, 43 insertions(+), 36 deletions(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index d48d28fbb0..f36e7dab4d 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -28,7 +28,7 @@ _start: shrl $2, %ecx rep stosl -#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ +#if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 05efac6db5..5e1ef24655 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -32,7 +32,7 @@ SECTIONS ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) #include EARLY_MEMLAYOUT -#elif ENV_VERSTAGE +#elif ENV_SEPARATE_VERSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M) diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index fd9fc63aea..246b9b9d2d 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -27,7 +27,7 @@ #include #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ - || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \ + || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_SEPARATE_VERSTAGE) \ || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \ || ENV_POSTCAR || ENV_RAMSTAGE) diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 34873dc9e4..3d9ca593e4 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -502,7 +502,7 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) if (cr50_i2c_probe(chip, &did_vid)) return -1; - if (ENV_VERSTAGE || ENV_BOOTBLOCK) + if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK) if (process_reset(chip)) return -1; diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 62d1bbae55..8f93e2a71a 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -454,7 +454,7 @@ int tpm2_init(struct spi_slave *spi_if) printk(BIOS_INFO, " done!\n"); - if (ENV_VERSTAGE || ENV_BOOTBLOCK) + if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK) /* * Claim locality 0, do it only during the first * initialization after reset. diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 094cd56bbe..c26d1db4f7 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -55,7 +55,7 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) { if (glob_dbg_info_p == NULL) { struct ehci_debug_info *info; - if (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) { + if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE || ENV_ROMSTAGE) { /* The message likely does not show if we hit this. */ if (sizeof(*info) > _car_ehci_dbg_info_size) die("BUG: Increase ehci_dbg_info reserve in CAR"); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 77fff07684..dcffbfe035 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -161,7 +161,7 @@ static inline int cbmem_possibly_online(void) if (ENV_BOOTBLOCK) return 0; - if (ENV_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + if (ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return 0; return 1; diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index a291db862d..2996f7c862 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -9,8 +9,8 @@ void cbmemc_init(void); void cbmemc_tx_byte(unsigned char data); #define __CBMEM_CONSOLE_ENABLE__ (CONFIG(CONSOLE_CBMEM) && \ - (ENV_RAMSTAGE || ENV_VERSTAGE || ENV_POSTCAR || ENV_ROMSTAGE || \ - (ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)))) + (ENV_RAMSTAGE || ENV_SEPARATE_VERSTAGE || ENV_POSTCAR || \ + ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } diff --git a/src/include/console/console.h b/src/include/console/console.h index fdc48da73f..be06c66b58 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -31,9 +31,9 @@ void die_notify(void); #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)) || \ - (ENV_POSTCAR && CONFIG(POSTCAR_CONSOLE)) || \ - ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_LIBAGESA || \ - (ENV_SMM && CONFIG(DEBUG_SMI))) + (ENV_POSTCAR && CONFIG(POSTCAR_CONSOLE)) || \ + ENV_SEPARATE_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || \ + ENV_LIBAGESA || (ENV_SMM && CONFIG(DEBUG_SMI))) #if __CONSOLE_ENABLE__ asmlinkage void console_init(void); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 1bd6ef0f6e..d423d9d681 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -51,8 +51,8 @@ static inline void *uart_platform_baseptr(int idx) void oxford_remap(unsigned int new_base); #define __CONSOLE_SERIAL_ENABLE__ (CONFIG(CONSOLE_SERIAL) && \ - (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \ - ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI)))) + (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_SEPARATE_VERSTAGE \ + || ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI)))) #if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_init(void) diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b7bc7f4a6e..e67f125c88 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -18,7 +18,7 @@ int usb_can_rx_byte(int idx); ((ENV_BOOTBLOCK && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ (ENV_ROMSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ (ENV_POSTCAR && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ - (ENV_VERSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ + (ENV_SEPARATE_VERSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ ENV_RAMSTAGE)) #define USB_PIPE_FOR_CONSOLE 0 diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 0cd465bda6..bef3637d1e 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -152,7 +152,7 @@ REGION(tpm_tcpa_log, addr, size, 16) \ _ = ASSERT(size >= 2K, "tpm tcpa log buffer must be at least 2K!"); -#if ENV_VERSTAGE +#if ENV_SEPARATE_VERSTAGE #define VERSTAGE(addr, sz) \ SYMBOL(verstage, addr) \ _everstage = _verstage + sz; \ diff --git a/src/include/rules.h b/src/include/rules.h index 92603db4ba..612f131ecf 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -14,7 +14,7 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 @@ -26,7 +26,7 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 @@ -38,7 +38,7 @@ #define ENV_ROMSTAGE 1 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 @@ -50,19 +50,26 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 1 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 #define ENV_STRING "smm" +/* + * NOTE: "verstage" code may either run as a separate stage or linked into the + * bootblock/romstage, depending on the setting of CONFIG_SEPARATE_VERSTAGE. The + * ENV_SEPARATE_VERSTAGE macro will only return true for "verstage" code when + * CONFIG_SEPARATE_VERSTAGE=y, otherwise that code will have ENV_BOOTBLOCK or + * ENV_ROMSTAGE set (depending on the CONFIG_VBOOT_STARTS_IN_... options). + */ #elif defined(__VERSTAGE__) #define ENV_DECOMPRESSOR 0 #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 1 +#define ENV_SEPARATE_VERSTAGE 1 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 @@ -74,7 +81,7 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 @@ -86,7 +93,7 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 1 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 @@ -98,7 +105,7 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 1 #define ENV_LIBAGESA 0 @@ -110,7 +117,7 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 1 @@ -126,7 +133,7 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_VERSTAGE 0 +#define ENV_SEPARATE_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 @@ -239,7 +246,7 @@ #define ENV_ROMSTAGE_OR_BEFORE \ (ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_ROMSTAGE || \ - (ENV_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))) + (ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))) #if CONFIG(ARCH_X86) /* Indicates memory layout is determined with arch/x86/car.ld. */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 5e85bb9bde..a61bc63fe8 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -106,7 +106,7 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, return in_size; case CBFS_COMPRESS_LZ4: - if ((ENV_BOOTBLOCK || ENV_VERSTAGE) && + if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(COMPRESS_PRERAM_STAGES)) return 0; @@ -125,7 +125,7 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, case CBFS_COMPRESS_LZMA: /* We assume here romstage and postcar are never compressed. */ - if (ENV_BOOTBLOCK || ENV_VERSTAGE) + if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) return 0; if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) return 0; @@ -236,8 +236,8 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ - if ((ENV_BOOTBLOCK || ENV_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && - CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { + if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && + !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { void *mapping = rdev_mmap(fh, foffset, fsize); rdev_munmap(fh, mapping); if (mapping == load) diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 5a0c481b06..2665f463df 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -89,7 +89,7 @@ int get_recovery_mode_switch(void) * The TPM recovery request is passed between stages through vboot data * or cbmem depending on stage. */ - if (ENV_VERSTAGE && + if (ENV_SEPARATE_VERSTAGE && tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && cr50_state) state = REC_MODE_REQUESTED; diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index ee3509d01e..eff43d0042 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -84,7 +84,7 @@ int get_recovery_mode_switch(void) * The TPM recovery request is passed between stages through vboot data * or cbmem depending on stage. */ - if (ENV_VERSTAGE && + if (ENV_SEPARATE_VERSTAGE && tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && cr50_state) state = REC_MODE_REQUESTED; diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index e64bb73d0b..cd59fa9dec 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -82,7 +82,7 @@ int get_recovery_mode_switch(void) * The TPM recovery request is passed between stages through vboot data * or cbmem depending on stage. */ - if (ENV_VERSTAGE && + if (ENV_SEPARATE_VERSTAGE && tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && cr50_state) state = REC_MODE_REQUESTED; diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index fd422b2ff7..d1e60bb2ac 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -47,7 +47,7 @@ int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw); static inline int verification_should_run(void) { if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_VERSTAGE; + return ENV_SEPARATE_VERSTAGE; else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) return ENV_ROMSTAGE; else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index 9aa1a67432..6b222c9d28 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -157,7 +157,7 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, done += next; } - if (ENV_BOOTBLOCK || ENV_VERSTAGE) { + if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) { dma_buf = (uintptr_t)_dma_coherent; dma_buf_len = REGION_SIZE(dma_coherent); } else { From b26f792d7231a6ed16976366a4f58f23077eb5d9 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Mon, 20 Apr 2020 16:26:30 +0800 Subject: [PATCH 1137/1463] mb/google/puff: Switch USB2 port1 and port3 Switch USB2 port1 and port3 for duffy and kaisa due to circuit change. BUG=b:153682207, b:154451230, b:154445635 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: I9c0cbcbefd045085fb70cf4f41869ab9b98103c4 Signed-off-by: Tim Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40301 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Kangheui Won --- .../hatch/variants/duffy/overridetree.cb | 18 +++++++++--------- .../hatch/variants/kaisa/overridetree.cb | 18 +++++++++--------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 2f36bc8b62..ade12c5806 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -22,7 +22,14 @@ chip soc/intel/cannonlake # USB configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -31,14 +38,7 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 3 - register "usb2_ports[3]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[4]" = "{ .enable = 1, .ocpin = OC_SKIP, diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index db05302278..e2380f4460 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -22,7 +22,14 @@ chip soc/intel/cannonlake # USB configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -31,14 +38,7 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 3 - register "usb2_ports[3]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[4]" = "{ .enable = 1, .ocpin = OC_SKIP, From cfdac8266155e7aafdc658e415eb719639670ed8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 17:53:59 +0200 Subject: [PATCH 1138/1463] mb/gigabyte/ga-g41m-es2l: Remove unused variable 'dev' Change-Id: I9ebba0ee9e59cb7d18b5ce89b048f591a4402543 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40613 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/gigabyte/ga-g41m-es2l/early_init.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index fdeb72e558..53652e70cc 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -30,10 +30,6 @@ void bootblock_mainboard_early_init(void) { - pci_devfn_t dev; - - /* Southbridge GPIOs. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); From a4faec3b014b54d4619dad31c6d6ede58700d862 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 16:49:28 +0200 Subject: [PATCH 1139/1463] src/mainboard: Const'ify pci_devfn_t devices Change-Id: I5bb1a819475383719dbda32d9b5fea63da1e6713 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40611 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/biostar/a68n_5200/bootblock.c | 2 +- src/mainboard/emulation/qemu-q35/bootblock.c | 4 +--- src/mainboard/google/beltino/chromeos.c | 6 +++--- src/mainboard/google/jecht/chromeos.c | 6 +++--- src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/stout/chromeos.c | 2 +- src/mainboard/samsung/lumpy/chromeos.c | 8 ++++---- src/mainboard/samsung/stumpy/chromeos.c | 8 ++++---- 8 files changed, 18 insertions(+), 20 deletions(-) diff --git a/src/mainboard/biostar/a68n_5200/bootblock.c b/src/mainboard/biostar/a68n_5200/bootblock.c index 1d1f0f142b..c289c444de 100644 --- a/src/mainboard/biostar/a68n_5200/bootblock.c +++ b/src/mainboard/biostar/a68n_5200/bootblock.c @@ -35,7 +35,7 @@ void bootblock_mainboard_early_init(void) pm_io_write8(0x24, 1); /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); /* enable SIO LPC decode */ diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 88be6df891..d8dc02cdc1 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -41,9 +41,7 @@ static void bootblock_northbridge_init(void) static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); reg8 = pci_read_config8(dev, 0xdc); reg8 &= ~(3 << 2); diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index f3a112d1c7..6c76120813 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -29,20 +29,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index b58b35a31f..90284c564f 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -30,20 +30,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 818901012b..b1bab25b69 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -15,7 +15,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 71d7df5685..03796a6c27 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -60,7 +60,7 @@ int get_recovery_mode_switch(void) if (ec_rec_flag_good) return ec_in_rec_mode; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); u8 ec_status = ec_read(EC_STATUS_REG); diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 0d5c0f6a07..c306e56080 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -21,7 +21,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); u8 lid = ec_read(0x83); @@ -44,20 +44,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ if (get_gpio(GPIO_SPI_WP)) diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index ac889ec11c..38808dbb14 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -17,7 +17,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); struct lb_gpio chromeos_gpios[] = { @@ -40,20 +40,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) From 956f56d645fd620274516a13d538a77f4fc4365d Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 Apr 2020 12:46:02 +0200 Subject: [PATCH 1140/1463] mb/google/smaug: Always add RTC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The device is always there, the Chromium OS config always enables it, so let's mirror that here for a better out of the box experience. Change-Id: Ic43a314aaed635ae2943df02abc5d163cc3c4ffd Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/40658 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/smaug/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index fa2313c154..0d3e879572 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 + select DRIVERS_TI_TPS65913_RTC config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -85,4 +86,12 @@ config EC_GOOGLE_CHROMEEC_I2C_BUS hex default 0x1 +config DRIVERS_TI_TPS65913_RTC_BUS + int + default 4 + +config DRIVERS_TI_TPS65913_RTC_ADDR + hex + default 0x58 + endif # BOARD_GOOGLE_SMAUG From 0b682636f3105952bf561bb064b4664446631d28 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 Apr 2020 12:45:11 +0200 Subject: [PATCH 1141/1463] mb/google/nyan*: Always add RTC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The device is always there, the Chromium OS configs always enable it, so let's mirror that here for a better out of the box experience. Change-Id: Ia2073ee7ecbdb37473e1f1002bc9ae0f7df58e42 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/40657 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/nyan/Kconfig | 9 +++++++++ src/mainboard/google/nyan_big/Kconfig | 9 +++++++++ src/mainboard/google/nyan_blaze/Kconfig | 9 +++++++++ 3 files changed, 27 insertions(+) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 3dc552020e..82577e9eea 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND + select DRIVERS_AS3722_RTC config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -77,4 +78,12 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config DRIVERS_AS3722_RTC_BUS + int + default 4 + +config DRIVERS_AS3722_RTC_ADDR + hex + default 0x40 + endif # BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 14a28cd7b8..099ff7f92d 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH_WINBOND select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 + select DRIVERS_AS3722_RTC config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -79,4 +80,12 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config DRIVERS_AS3722_RTC_BUS + int + default 4 + +config DRIVERS_AS3722_RTC_ADDR + hex + default 0x40 + endif # BOARD_GOOGLE_NYAN_BIG diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 35bd69190a..4c611b986e 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH_WINBOND select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 + select DRIVERS_AS3722_RTC config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -79,4 +80,12 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config DRIVERS_AS3722_RTC_BUS + int + default 4 + +config DRIVERS_AS3722_RTC_ADDR + hex + default 0x40 + endif # BOARD_GOOGLE_NYAN_BLAZE From 5632841c82aa8fc39760ee793d55df7126fb8fa2 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 16 Apr 2020 10:07:39 +1000 Subject: [PATCH 1142/1463] mb/google/hatch: Add Kaisa variant specific DPTF parameters Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: I7270db1283a9c0ee4746da038020e432aeb6dc5e Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40422 Reviewed-by: Sam McNally Reviewed-by: Daniel Kurtz Reviewed-by: Angel Pons Reviewed-by: Tim Chen Tested-by: build bot (Jenkins) --- .../kaisa/include/variant/acpi/dptf.asl | 116 +++++++++++++++++- 1 file changed, 115 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl index 2c44a82365..de12ee133e 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl @@ -1 +1,115 @@ -#include +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 80 +#define DPTF_CPU_ACTIVE_AC3 75 +#define DPTF_CPU_ACTIVE_AC4 70 +#define DPTF_CPU_ACTIVE_AC5 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 25000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) From 9e0b28cbe5dcdfc0c5c512e84c452c300e590691 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 16 Apr 2020 10:09:20 +1000 Subject: [PATCH 1143/1463] mb/google/hatch: Add Duffy variant specific DPTF parameters Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: Ic619826205be06f30055fbbc537f3d302dd039bd Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40423 Reviewed-by: Sam McNally Reviewed-by: Daniel Kurtz Reviewed-by: Angel Pons Reviewed-by: Tim Chen Tested-by: build bot (Jenkins) --- .../duffy/include/variant/acpi/dptf.asl | 116 +++++++++++++++++- 1 file changed, 115 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl index 2c44a82365..de12ee133e 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl @@ -1 +1,115 @@ -#include +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 80 +#define DPTF_CPU_ACTIVE_AC3 75 +#define DPTF_CPU_ACTIVE_AC4 70 +#define DPTF_CPU_ACTIVE_AC5 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 25000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) From 6edfa654d2f1474802ab9f0b787dceb74cd58e16 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 16 Apr 2020 14:36:06 +1000 Subject: [PATCH 1144/1463] mb/google/hatch: Make Kconfig LAPTOP knob transitively select BUG=b:154071868 BRANCH=none TEST=builds Change-Id: I9c602476a80a97438af01e3c48fac385532373a4 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40510 Tested-by: build bot (Jenkins) Reviewed-by: Daniel Kurtz Reviewed-by: Angel Pons --- src/mainboard/google/hatch/Kconfig | 1 + src/mainboard/google/hatch/Kconfig.name | 13 ------------- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 11137bde6e..6168e13140 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select RT8168_SET_LED_MODE config BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select SYSTEM_TYPE_LAPTOP def_bool n diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index de9bcb53b1..6465854104 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -2,13 +2,11 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI bool "-> Akemi" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_DRATINI bool "-> Dratini" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 @@ -22,13 +20,11 @@ config BOARD_GOOGLE_DUFFY config BOARD_GOOGLE_HATCH bool "-> Hatch" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_JINLON bool "-> Jinlon" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select DRIVERS_GFX_GENERIC @@ -43,20 +39,17 @@ config BOARD_GOOGLE_KAISA config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_KINDRED bool "-> Kindred" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS bool "-> Helios" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB @@ -64,13 +57,11 @@ config BOARD_GOOGLE_HELIOS config BOARD_GOOGLE_MUSHU bool "-> Mushu" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_PALKIA bool "-> Palkia" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB @@ -78,7 +69,6 @@ config BOARD_GOOGLE_PALKIA config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 @@ -91,7 +81,6 @@ config BOARD_GOOGLE_PUFF config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB @@ -99,12 +88,10 @@ config BOARD_GOOGLE_HELIOS_DISKSWAP config BOARD_GOOGLE_STRYKE bool "-> Stryke" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_SUSHI bool "-> Sushi" - select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 From 988a273396bcf2d82366a5f6a2a4dc4bed662bfd Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 20 Apr 2020 13:58:07 +0200 Subject: [PATCH 1145/1463] vc/eltan/security/verified_boot/vboot_check.c: Correct code style Remove double space and limit lines to 96 column. BUG=N/A TEST=Build and boot Facebook fbg1701 Signed-off-by: Frans Hendriks Change-Id: Ib6373bbf9b666540304e8a2bdaa9add9914476bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/40528 Reviewed-by: Wim Vervoorn Reviewed-by: Stefan Reinauer Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/vendorcode/eltan/security/verified_boot/vboot_check.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 174a37824d..ac9d73bf9c 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -81,7 +81,7 @@ int verified_boot_check_manifest(void) DIGEST_SIZE; pre->body_signature.sig_offset = sizeof(struct vb2_signature) + pre->body_signature.data_size; - pre->body_signature.sig_size = size - pre->body_signature.data_size; + pre->body_signature.sig_size = size - pre->body_signature.data_size; sd->workbuf_used += size; memcpy((void *)((void *)&pre->body_signature + (long)sizeof(struct vb2_signature)), (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, size); @@ -146,7 +146,8 @@ static void verified_boot_check_buffer(const char *name, void *start, size_t siz if (start && size) { - status = vb2_digest_buffer((const uint8_t *)start, size, HASH_ALG, digest, DIGEST_SIZE); + status = vb2_digest_buffer((const uint8_t *)start, size, HASH_ALG, digest, + DIGEST_SIZE); if ((CONFIG(VENDORCODE_ELTAN_VBOOT) && memcmp((void *)( (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + sizeof(digest) * hash_index), digest, sizeof(digest))) || status) { From 740c29a478c9c2168ce300b547f871c54a68d3de Mon Sep 17 00:00:00 2001 From: Alex Levin Date: Mon, 20 Apr 2020 21:55:02 -0700 Subject: [PATCH 1146/1463] soc/intel/tigerlake: Add ACPI GPIO op Add acpigen methods which generate operations to get/set/clear RX/TX GPIOs. Verify it matches https://doc.coreboot.org/acpi/gpio.html. BUG=b:149588766 TEST=confirmed with touchscreen gpios. Signed-off-by: Alex Levin Change-Id: Id9fe26f14a606ceedb9db02d76fe8d466d3a21af Reviewed-on: https://review.coreboot.org/c/coreboot/+/40550 Reviewed-by: EricR Lai Reviewed-by: Tim Wawrzynczak Reviewed-by: Jes Klinke Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi.c | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 36c488b575..f8d8986d77 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -330,3 +330,40 @@ int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; } + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} From 7e78e56c34896dab31dbaed697fe49dd20111755 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 3 Nov 2019 23:29:02 -0700 Subject: [PATCH 1147/1463] soc/amd/picasso/i2c: don't initialize I2C4 as master and refactor code I2C0&1 are either not available or not functional. Add place holders instead, so that the array index matches the I2C controller number. I2C4 is slave device only, so do not initialize it as I2C host controller. Also do some slight refactoring. BUG=b:153152871 BUG=b:153675916 Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth Signed-off-by: Paul Ma Signed-off-by: Raul E Rangel Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 Reviewed-on: https://chromium-review.googlesource.com/2094855 Reviewed-on: https://chromium-review.googlesource.com/2149870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/lpc/lpc.c | 2 +- src/soc/amd/picasso/chip.h | 5 ++--- src/soc/amd/picasso/i2c.c | 19 +++++++++++------- src/soc/amd/picasso/include/soc/iomap.h | 26 +++++++++++++++++++------ 4 files changed, 35 insertions(+), 17 deletions(-) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 5346356ad6..3df5ad0ae9 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -118,7 +118,7 @@ static void lpc_read_resources(struct device *dev) res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* I2C devices (all 4 devices) */ + /* I2C devices */ res = new_resource(dev, 4); res->base = I2C_BASE_ADDRESS; res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT; diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 53c03291b7..9c756ed616 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -9,10 +9,9 @@ #include #include #include +#include #include -#define PICASSO_I2C_DEV_MAX 4 - struct soc_amd_picasso_config { /* * If sb_reset_i2c_slaves() is called, this devicetree register @@ -23,7 +22,7 @@ struct soc_amd_picasso_config { * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ u8 i2c_scl_reset; - struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; + struct dw_i2c_bus_config i2c[I2C_MASTER_DEV_COUNT]; enum { I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 22c62161f1..8ba05aa9de 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -8,34 +8,39 @@ #include #include #include +#include #include #include #include -#include #include "chip.h" /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev); -static const uintptr_t i2c_bus_address[] = { +/* + * We don't have addresses for I2C0-1. + */ +static const uintptr_t i2c_bus_address[I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT] = { + 0, + 0, APU_I2C2_BASE, APU_I2C3_BASE, - APU_I2C4_BASE, /* slave device only */ + APU_I2C4_BASE, /* Can only be used in slave mode */ }; uintptr_t dw_i2c_base_address(unsigned int bus) { - if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + if (bus >= ARRAY_SIZE(i2c_bus_address)) return 0; - return i2c_bus_address[bus - APU_I2C_MIN_BUS]; + return i2c_bus_address[bus]; } const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; - if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + if (bus >= ARRAY_SIZE(config->i2c)) return NULL; /* config is not NULL; if it was, config_of_soc calls die() internally */ @@ -83,7 +88,7 @@ static void dw_i2c_soc_init(bool is_early_init) /* config is not NULL; if it was, config_of_soc calls die() internally */ config = config_of_soc(); - for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { + for (i = I2C_MASTER_START_INDEX; i < ARRAY_SIZE(config->i2c); i++) { const struct dw_i2c_bus_config *cfg = &config->i2c[i]; if (cfg->early_init != is_early_init) diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 1ff3440307..5e1e6e22b3 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -18,15 +18,29 @@ /* Reserved 0xfecd1000-0xfedc3fff */ +/* + * Picasso/Dali have I2C0 and I2C1 wired to the Sensor Fusion Hub (SFH/MP2). + * The controllers are not directly accessible via the x86. + * + * On Pollock, I2C0 and I2C1 are routed to the x86 domain, but unfortunately the + * interrupts weren't. This effectively makes the I2C controllers useless, so we + * pretend they don't exist. + * + * We want the device tree numbering to match the I2C numbers, so we allocate + * I2C0 and I2C1 even though they are not functional. + */ +#define I2C_MASTER_DEV_COUNT 4 +#define I2C_MASTER_START_INDEX 2 +#define I2C_SLAVE_DEV_COUNT 1 + #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -#define APU_I2C_MIN_BUS 2 -#define APU_I2C_MAX_BUS 4 -#define APU_I2C_BLOCK_SIZE 0x1000 -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 3 + +/* I2C parameters for lpc_read_resources */ +#define I2C_BASE_ADDRESS APU_I2C2_BASE +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 3 #define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC1_BASE 0xfedc8000 From e8ac242e653169a4056b8d8e7252c134c391ed49 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 5 Feb 2020 17:47:33 -0700 Subject: [PATCH 1148/1463] mb/google/hatch: Change baseboard EC wake & SCI masks to match kohaku 1) Allows MKBP events from the EC to wake the system from suspend states. 2) Remove EC_HOST_EVENT_MKBP from the EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:148976961 BRANCH=firmware-hatch-12672.B TEST=Verify MKBP events wake system TEST=Verify MKBP IRQs are run Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/38735 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Shelley Chen --- .../variants/baseboard/include/baseboard/ec.h | 4 +-- .../variants/kohaku/include/variant/ec.h | 25 ------------------- 2 files changed, 2 insertions(+), 27 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index 48b473f978..90785bd795 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -20,8 +20,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) @@ -38,6 +37,7 @@ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS \ diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index 7f12e95888..a6bd201d16 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -8,29 +8,4 @@ #define EC_ENABLE_MULTIPLE_DPTF_PROFILES -/* Add EC_HOST_EVENT_MKBP from baseboard */ -#undef MAINBOARD_EC_S3_WAKE_EVENTS -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -/* Removing EC_HOST_EVENT_MKBP from baseboard mask */ -#undef MAINBOARD_EC_SCI_EVENTS -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - #endif /* VARIANT_EC_H */ From dec73da3c2a1100cf42921015d2b0b3ca792c491 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 Apr 2020 12:46:35 +0200 Subject: [PATCH 1149/1463] drivers/ams: Hide RTC driver from Kconfig menus It's supposed to be selected by default on devices that ship with the device, while there's little need to add it on other devices. Change-Id: I2747c4f825601b2fbffc908821035e4f66c5a3b8 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/40659 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Angel Pons --- src/drivers/ams/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/ams/Kconfig b/src/drivers/ams/Kconfig index 30e86672ae..ed8f3df868 100644 --- a/src/drivers/ams/Kconfig +++ b/src/drivers/ams/Kconfig @@ -1,5 +1,5 @@ config DRIVERS_AS3722_RTC - bool "AS3722 RTC support" + bool default n select RTC From ddb3359754317a536d75c8a234cb7722be515855 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 Apr 2020 12:47:31 +0200 Subject: [PATCH 1150/1463] drivers/ti/tps65913: Hide RTC driver from Kconfig menus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's supposed to be selected by default on devices that ship with the device, while there's little need to add it on other devices. Change-Id: I57badee9ce1e8a3c8df313953aba02cc3489ff97 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/40660 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/ti/tps65913/Kconfig | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/drivers/ti/tps65913/Kconfig b/src/drivers/ti/tps65913/Kconfig index 6d2b58a48f..130bebbd7b 100644 --- a/src/drivers/ti/tps65913/Kconfig +++ b/src/drivers/ti/tps65913/Kconfig @@ -11,14 +11,9 @@ ## GNU General Public License for more details. ## -config DRIVERS_TI_TPS65913 - bool "TI TPS65913 support" - default n - config DRIVERS_TI_TPS65913_RTC - bool "TI TPS65913 RTC support" + bool default n - select DRIVERS_TI_TPS65913 select RTC config DRIVERS_TI_TPS65913_RTC_BUS From 6d9dc243c76dfeef7b5b15e421f4a36e0247faea Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 20 Apr 2020 17:16:53 -0700 Subject: [PATCH 1151/1463] soc/intel/xeon_sp/cpx: Allow motherboards to set FSP-M parameters We need to allow motherboards to configure certain parameters that are specific to it. Hence, invoke this function. Also, provide a weak motherboard implementation that does nothing. Change-Id: Ifa2824811273236a66e742404856fbe17d4cf496 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40552 Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/romstage.c | 3 +++ src/soc/intel/xeon_sp/romstage.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 32ada9f4cb..e909b87ca8 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -3,6 +3,7 @@ #include #include +#include #include "chip.h" void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) @@ -10,4 +11,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; (void)m_cfg; + + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 9d3665c9fe..7881b0adb9 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -55,3 +55,8 @@ asmlinkage void car_stage_entry(void) run_postcar_phase(&pcf); } + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_SPEW, "WARNING: using default FSP-M parameters!\n"); +} From 2f96970e1f4e586a4c5928fefab1bc0f98bc1351 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 20 Apr 2020 23:00:54 -0700 Subject: [PATCH 1152/1463] mb/intel/cedarisland_crb: Add dummy mainboard_memory_init_params() Add a dummy implementation (currently FSP defaults are meant for CRB). It is needed only to prevent build breakage. Change-Id: I67b1a693886a29bdaf23f1f3f249da52ba65451a Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40553 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/intel/cedarisland_crb/Makefile.inc | 1 + src/mainboard/intel/cedarisland_crb/romstage.c | 8 ++++++++ 2 files changed, 9 insertions(+) create mode 100644 src/mainboard/intel/cedarisland_crb/romstage.c diff --git a/src/mainboard/intel/cedarisland_crb/Makefile.inc b/src/mainboard/intel/cedarisland_crb/Makefile.inc index 8501868fbf..9bd017393c 100644 --- a/src/mainboard/intel/cedarisland_crb/Makefile.inc +++ b/src/mainboard/intel/cedarisland_crb/Makefile.inc @@ -1 +1,2 @@ bootblock-y += bootblock.c +romstage-y += romstage.c diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c new file mode 100644 index 0000000000..94af1b6dfe --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ +} From dddb9a85bd1e9810410f14010f20c9ce2dabfee5 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 20 Apr 2020 18:07:08 -0700 Subject: [PATCH 1153/1463] soc/intel/xeon_sp/cpx: Work around FSP-M issues Currently FSP-M does not implement the spec completely, e.g it is unable to use user-provided heap location in CAR. While this is being resolved, this workaround is a stop-gap solution that allows multi-socket usage. TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555 Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Kconfig | 5 ++--- src/soc/intel/xeon_sp/cpx/cpu.c | 2 +- src/soc/intel/xeon_sp/cpx/romstage.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 70703d0c78..88b0d5d651 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -16,7 +16,6 @@ config USE_FSP2_0_DRIVER select UDK_2015_BINDING select POSTCAR_CONSOLE select POSTCAR_STAGE - select FSP_USES_CB_STACK config FSP_HEADER_PATH string "Location of FSP headers" @@ -40,11 +39,11 @@ config PCR_BASE_ADDRESS # currently FSP hardcodes [0fe800000;fe930000] for its heap config DCACHE_RAM_BASE hex - default 0xfe930000 + default 0xfe9a0000 config DCACHE_RAM_SIZE hex - default 0xd0000 + default 0x60000 config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 8824686674..a62c2f0318 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -28,7 +28,7 @@ const void *intel_mp_current_microcode(void) static void each_cpu_init(struct device *cpu) { - printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); setup_lapic(); diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index e909b87ca8..355554a782 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -9,8 +9,19 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; (void)m_cfg; + /* + * Currently FSP for CPX does not implement user-provided StackBase/Size + * properly. When KTI link needs to be trained, inter-socket communication + * library needs quite a bit of memory for its heap usage. However, location + * is hardcoded so this workaround is needed. + */ + if (CONFIG_MAX_SOCKET > 1) { + arch_upd->StackBase = (void *) 0xfe930000; + arch_upd->StackSize = 0x70000; + } mainboard_memory_init_params(mupd); } From e37d1f724a3df9d680ec616f0b13adbc07c4e744 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 20 Apr 2020 21:11:51 -0700 Subject: [PATCH 1154/1463] soc/intel/xeon_sp/cpx: Bump MAX_CPUS Some dual-socket socket systems offer over 100 threads available. Other multi-socket configurations potentially offer even greater numbers of CPUs (over 9000!). Bump MAX_CPUS to 255. Change-Id: I50a181b89f40777a9f7b3881280c7bacf1b947cb Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40556 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/cpx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 88b0d5d651..92681f2767 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -28,7 +28,7 @@ config MAX_SOCKET config MAX_CPUS int - default 80 + default 255 config PCR_BASE_ADDRESS hex From 5d76958de124af3877f9b399a4ec8a6377fe4ffd Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 23 Apr 2020 10:54:18 -0700 Subject: [PATCH 1155/1463] soc/intel/xeon_sp/cpx: Calculate number of threads based on sockets Assuming given system is populated with multiple CPUs of same SKUs, calculate number of threads based on MAX_SOCKET. This is a stop gap solution until proper way of identifying total number of sockets is determined. Change-Id: I7ebad3d57c47b9eeb7d727ffb21bc0a1a84734fd Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40671 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov --- src/soc/intel/xeon_sp/cpx/cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index a62c2f0318..a7a4c54e7f 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -63,7 +63,14 @@ static int get_thread_count(void) cpu_read_topology(&num_phys, &num_virts); printk(BIOS_SPEW, "Detected %u cores and %u threads\n", num_phys, num_virts); - return num_virts; + /* + * Currently we do not know a way to figure out how many CPUs we have total + * on multi-socketed. So we pretend all sockets are populated with CPUs with + * same thread/core fusing. + * TODO: properly figure out number of active sockets OR refactor MPinit code + * to remove requirements of having to know total number of CPUs in advance. + */ + return num_virts * CONFIG_MAX_SOCKET; } static const struct mp_ops mp_ops = { From 8ebbe17b8613c9cf499ab7d5090ed4ee3356c1f9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 21 Apr 2020 23:19:52 -0700 Subject: [PATCH 1156/1463] soc/intel/tigerlake: Fix FSP SPD index for DDR4 For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects. BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful. Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588 Tested-by: build bot (Jenkins) Reviewed-by: Kane Chen Reviewed-by: EricR Lai --- src/soc/intel/tigerlake/meminit.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 86645472aa..d44554af7e 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -16,6 +16,14 @@ #define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2))) +/* + * Translate DDR4 channel # to FSP UPD index # for the channel. + * Channel 0 -> Index 0 + * Channel 1 -> Index 4 + * Index 1-3 and 5-7 are unused. + */ +#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4) + enum dimm_enable_options { ENABLE_BOTH_DIMMS = 0, DISABLE_DIMM0 = 1, @@ -378,7 +386,7 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, for (i = 0; i < DDR4_CHANNELS; i++) { ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, half_populated, &spd_dimm0, &spd_dimm1); - init_spd_upds(mem_cfg, i, spd_dimm0, spd_dimm1); + init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); } /* From 9a521d7125df27d40621c16a2526cfa605e3de5a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 20 Mar 2020 10:07:53 +0100 Subject: [PATCH 1157/1463] include/device/azalia: Add enums and MACROs Instead of only using magic values add enums and defines to allow writing the codec init sequence in human readable form. This will replace the magic numbers in mainboards HDA verb tables. Change-Id: Icad07c2b550657b879ad9328a70ba44629a0c939 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39694 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Angel Pons --- src/include/device/azalia_device.h | 88 ++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 6f82e0e5a5..3c8e76e7ef 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -17,6 +17,94 @@ extern const u32 cim_verb_data_size; extern const u32 pc_beep_verbs[]; extern const u32 pc_beep_verbs_size; +enum azalia_pin_connection { + JACK = 0, + NC, + INTEGRATED, + JACK_AND_INTEGRATED, +}; + +enum azalia_pin_color { + COLOR_UNKNOWN = 0, + BLACK, + GREY, + BLUE, + GREEN, + RED, + ORANGE, + YELLOW, + PURPLE, + PINK, + WHITE = 0xe, + COLOR_OTHER = 0xf, +}; + +enum azalia_pin_type { + TYPE_UNKNOWN = 0, + STEREO_MONO_1_8, + STEREO_MONO_1_4, + ATAPI, + RCA, + OPTIONAL, + OTHER_DIGITAL, + OTHER_ANALOG, + MULTICHANNEL_ANALOG, + XLR, + RJ_11, + COMBINATION, + TYPE_OTHER = 0xf +}; + +enum azalia_pin_device { + LINE_OUT = 0, + SPEAKER, + HP_OUT, + CD, + SPDIF_OUT, + DIGITAL_OTHER_OUT, + MODEM_LINE_SIDE, + MODEM_HANDSET_SIDE, + LINE_IN, + AUX, + MIC_IN, + TELEPHONY, + SPDIF_IN, + DIGITAL_OTHER_IN, + DEVICE_OTHER = 0xf, +}; + +enum azalia_pin_location_1 { + NA = 0, + REAR, + FRONT, + LEFT, + RIGHT, + TOP, + BOTTOM, + SPECIAL7, + SPECIAL8, + SPECIAL9, +}; + +enum azalia_pin_location_2 { + EXTERNAL_PRIMARY_CHASSIS = 0, + INTERNAL, + SEPARATE_CHASSIS, + LOCATION_OTHER +}; + +#define AZALIA_PIN_DESC(conn, location2, location1, dev, type, color, no_presence_detect, \ + association, sequence) \ + (((conn) << 30) | \ + ((location2) << 27) | \ + ((location1) << 24) | \ + ((dev) << 20) | \ + ((type) << 16) | \ + ((color) << 12) | \ + ((no_presence_detect) << 8) | \ + ((sequence) << 4) | \ + ((sequence) << 0)) + #define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ ARRAY_SIZE(pc_beep_verbs); \ const u32 cim_verb_data_size = sizeof(cim_verb_data) From bd2dc2b764ad9f20bfcd71d9c67ef07fe95ab76d Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 11 Jan 2020 03:54:59 -0500 Subject: [PATCH 1158/1463] asus/p2b-ls: Replicate OEM GPO configuration Replicate the GPO configurations from OEM BIOS, obtained via inteltool. Among the GPOs are termination controls for the onboard SCSI buses. TEST=read/write Maxtor Atlas 10k3 18GB HDD connected to Ultra2 LVD port Change-Id: I86183acd8e1a830d7639c21ec179fbdbe937f8ee Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38354 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb index bb252c0b0b..541db02be6 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb @@ -1,6 +1,10 @@ chip northbridge/intel/i440bx # Northbridge device domain 0 on # PCI domain chip southbridge/intel/i82371eb # Southbridge + register "gpo" = "0x7fbfb9ff" + register "gpo22_enable" = "1" # GPO22 controls LVD port termination (0=enabled) + # GPO23 controls SCSI-50 port termination (1=enabled) + # SCSI-68 port is always terminated device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O device pnp 3f0.a off # ACPI From cd23084284d661174c1ebaabc25aba2c52de27c7 Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 1159/1463] mb/lenovo/{x201,t410}: Move ThinkLight code This patch moves the code to control the ThinkLight to the common ACPI folder for h8. This reduces code duplication and allows other ThinkPads to include the same code for ThinkLight support. Change-Id: I57de7516051bdcbb23fc21b4de352f265075893b Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40664 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/ec/lenovo/h8/acpi/thinklight.asl | 17 +++++++++++++++++ src/mainboard/lenovo/t410/acpi/platform.asl | 15 --------------- src/mainboard/lenovo/t410/dsdt.asl | 2 ++ src/mainboard/lenovo/x201/acpi/platform.asl | 15 --------------- src/mainboard/lenovo/x201/dsdt.asl | 2 ++ 5 files changed, 21 insertions(+), 30 deletions(-) create mode 100644 src/ec/lenovo/h8/acpi/thinklight.asl diff --git a/src/ec/lenovo/h8/acpi/thinklight.asl b/src/ec/lenovo/h8/acpi/thinklight.asl new file mode 100644 index 0000000000..d9b1f41b97 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/thinklight.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Method(UCMS, 1, Serialized) +{ + Switch(ToInteger(Arg0)) + { + Case (0x0c) /* Turn on ThinkLight */ + { + \_SB.PCI0.LPCB.EC.LGHT(1) + } + Case (0x0d) /* Turn off ThinkLight */ + { + \_SB.PCI0.LPCB.EC.LGHT(0) + } + } +} diff --git a/src/mainboard/lenovo/t410/acpi/platform.asl b/src/mainboard/lenovo/t410/acpi/platform.asl index a5c3964499..3bea2261f5 100644 --- a/src/mainboard/lenovo/t410/acpi/platform.asl +++ b/src/mainboard/lenovo/t410/acpi/platform.asl @@ -22,18 +22,3 @@ Method(_WAK,1) /* Not implemented. */ Return(Package(){0,0}) } - -Method(UCMS, 1, Serialized) -{ - Switch(ToInteger(Arg0)) - { - Case (0x0c) /* Turn on ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(1) - } - Case (0x0d) /* Turn off ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(0) - } - } -} diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index c49c31b2ad..c2624d4195 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -76,4 +76,6 @@ DefinitionBlock( /* Dock support code */ #include "acpi/dock.asl" + + #include } diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 2f3b215341..2677b846db 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -27,21 +27,6 @@ Method(_WAK,1) Return(Package(){0,0}) } -Method(UCMS, 1, Serialized) -{ - Switch(ToInteger(Arg0)) - { - Case (0x0c) /* Turn on ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(1) - } - Case (0x0d) /* Turn off ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(0) - } - } -} - /* System Bus */ Scope(\_SB) diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index c49c31b2ad..c2624d4195 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -76,4 +76,6 @@ DefinitionBlock( /* Dock support code */ #include "acpi/dock.asl" + + #include } From b45912f453b52bfc01e66dc070fb33fad236d816 Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 1160/1463] mb/lenovo/x200: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad X200 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight I have tested it on an X200 with Kernel 5.4 and it seems to work fine. Change-Id: I14752ab33484122248959517e73f96b6783b1f65 Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40620 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/x200/dsdt.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 1357a3a9ea..abe1c27360 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -41,4 +41,6 @@ DefinitionBlock( /* Dock support code */ #include "acpi/dock.asl" + + #include } From fadd6353dbe72bec79888b37385df7f5877ddc1a Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 24 Apr 2020 19:04:09 +0800 Subject: [PATCH 1161/1463] mb/google/hatch/var/jinlon: Tune i2c frequency under 400 KHz Tuning i2c frequency for jinlon: I2C0: 392.7 KHz I2C1: 390 KHz I2C3: unused I2C4: 388.8 KHz BUG=b:154900217 BRANCH=hatch TEST=emerge-hatch coreboot chromeos-bootimage, and measured with scope Change-Id: I9b186193f34027d03dd349cf1e29bb266b167383 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40688 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak --- .../google/hatch/variants/jinlon/overridetree.cb | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 7cf434dd91..546267011d 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -46,15 +46,18 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 30, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, + .rise_time_ns = 20, + .fall_time_ns = 25, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 40, + .fall_time_ns = 60, }, }" From 184b1ce1714cbdd934494280dfcbf473972c12df Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 21 Apr 2020 17:59:25 +0800 Subject: [PATCH 1162/1463] mb/google/deltaur: Move early gpio table to variants If set variant early gpio table NULL, it will override the baseboard table. Move early gpio table to variant level. BUG=b:154310066 TEST=Check H1 has no I2C error occurs. Signed-off-by: Eric Lai Change-Id: Ie4c4648ccf918446a499019a4f77f64e43a92c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40567 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/deltaur/variants/baseboard/gpio.c | 42 +------------------ .../google/deltaur/variants/deltan/gpio.c | 35 +++++++++++++++- 2 files changed, 36 insertions(+), 41 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 71a07b6d46..a96e702fac 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -406,44 +406,6 @@ const struct pad_config *__weak variant_base_gpio_table(size_t *num) return gpio_table; } -/* GPIO pads configured in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* A23 : GPP_A23 ==> RECOVERY# */ - PAD_CFG_GPI(GPP_A23, NONE, DEEP), - /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - /* C22 : GPP_C22 ==> H1_FLASH_WP */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : GPP_C23 ==> H1_PCH_INT# */ - PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT), - /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ - PAD_CFG_GPI(GPP_E3, NONE, PLTRST), - /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ - PAD_CFG_GPI(GPP_F11, NONE, DEEP), - /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ - PAD_CFG_GPI(GPP_F12, NONE, DEEP), - /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ - PAD_CFG_GPI(GPP_F13, NONE, DEEP), - /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ - PAD_CFG_GPI(GPP_F14, NONE, DEEP), - /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */ - PAD_CFG_GPI(GPP_F15, NONE, DEEP), - /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ - PAD_CFG_GPO(GPP_F16, 0, DEEP), - /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ - PAD_CFG_GPI(GPP_H4, NONE, DEEP), - /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ - PAD_CFG_GPI(GPP_H5, NONE, DEEP), - /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* GPD3: GPD3 ==> SIO_PWRBTN# */ - PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), -}; - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME), @@ -465,8 +427,8 @@ const struct pad_config *__weak variant_override_gpio_table(size_t *num) /* Weak implementation of early gpio */ const struct pad_config *__weak variant_early_gpio_table(size_t *num) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; + *num = 0; + return NULL; } int __weak has_360_sensor_board(void) diff --git a/src/mainboard/google/deltaur/variants/deltan/gpio.c b/src/mainboard/google/deltaur/variants/deltan/gpio.c index 30315bbc2e..f67302f117 100644 --- a/src/mainboard/google/deltaur/variants/deltan/gpio.c +++ b/src/mainboard/google/deltaur/variants/deltan/gpio.c @@ -21,7 +21,40 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - + /* A23 : GPP_A23 ==> RECOVERY# */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP), + /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : GPP_C22 ==> H1_FLASH_WP */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* C23 : GPP_C23 ==> H1_PCH_INT# */ + PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT), + /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ + PAD_CFG_GPI(GPP_F11, NONE, DEEP), + /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ + PAD_CFG_GPI(GPP_F14, NONE, DEEP), + /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */ + PAD_CFG_GPI(GPP_F15, NONE, DEEP), + /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), + /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ + PAD_CFG_GPI(GPP_H5, NONE, DEEP), + /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* GPD3: GPD3 ==> SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), }; const struct pad_config *variant_early_gpio_table(size_t *num) From d6f7ec5f44810a3b7061df1be5c4be456e5852de Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 14 Apr 2020 21:53:43 +0530 Subject: [PATCH 1163/1463] soc/intel/apollolake: Avoid CONFIG_PCIEX_LENGTH_256MB selection This patch removes APL SoC selecting CONFIG_PCIEX_LENGTH_256MB Kconfig as default configuration for CONFIG_SA_PCIEX_LENGTH_MIB is 256MB. TEST=Able to build and boot APL platform. Change-Id: I61249f0adff5e03c07a568556e1ff76b27c6d368 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/40378 Reviewed-by: Angel Pons Reviewed-by: Pratikkumar V Prajapati Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 91e5bb64b3..9118b18af8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -54,7 +54,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select PCIEX_LENGTH_256MB select PMC_INVALID_READ_AFTER_WRITE select PMC_GLOBAL_RESET_ENABLE_LOCK select REG_SCRIPT From 34d9e68ff9026496fb262a2098ccdd2716bd8eb3 Mon Sep 17 00:00:00 2001 From: Alex Levin Date: Mon, 20 Apr 2020 21:55:24 -0700 Subject: [PATCH 1164/1463] mb/google/volteer: add touchscreen entry to Volteer BUG=b:149588766 TEST=ELAN and Goodix touchscreen works. Signed-off-by: Alex Levin Change-Id: I1c3e75eb03a8ab434ee58bf36a155f2255612083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40551 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Nick Vaccaro --- src/mainboard/google/volteer/Kconfig | 1 + .../volteer/variants/baseboard/devicetree.cb | 32 ++++++++++++++++++- .../google/volteer/variants/baseboard/gpio.c | 6 ++-- 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 0870c61ecb..04b2bb0f30 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 28931e486d..12ae87afcd 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -251,7 +251,37 @@ chip soc/intel/tigerlake device i2c 1a on end end end # I2C #0 0xA0E8 - device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 device pci 15.2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 1028dfad9f..37211ff796 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -23,7 +23,7 @@ static const struct pad_config gpio_table[] = { /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_A8, 1, DEEP), + PAD_CFG_GPO(GPP_A8, 0, DEEP), /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_A9, NONE, DEEP), /* A10 : I2S2_RXD ==> EN_SPKR_PA */ @@ -125,7 +125,7 @@ static const struct pad_config gpio_table[] = { /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C10 : UART0_RTS# ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), + PAD_CFG_GPO(GPP_C10, 0, DEEP), /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* C12 : UART1_RXD ==> MEM_STRAP_0 */ @@ -210,7 +210,7 @@ static const struct pad_config gpio_table[] = { /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> USI_INT */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ PAD_CFG_GPO(GPP_E8, 0, DEEP), /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ From fcfca1da5ea4eee266c830948ec117f06a3553cd Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 27 Feb 2020 14:55:50 +0100 Subject: [PATCH 1165/1463] Documentation: Add vboot on Lenovo devices Describe vboot implementation details for retrofitted Lenovo ThinkPad devices. Change-Id: Ibabcc939d9d01f00a93fd42adc48057966ad877e Signed-off-by: Patrick Rudolph Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39151 Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- Documentation/mainboard/index.md | 1 + Documentation/mainboard/lenovo/vboot.md | 39 +++++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 Documentation/mainboard/lenovo/vboot.md diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 57df302986..3426395dfb 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -74,6 +74,7 @@ The boards in this section are not real mainboards, but emulators. - [R60](lenovo/r60.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [VBOOT](lenovo/vboot.md) ### Arrandale series diff --git a/Documentation/mainboard/lenovo/vboot.md b/Documentation/mainboard/lenovo/vboot.md new file mode 100644 index 0000000000..3e4d43bd14 --- /dev/null +++ b/Documentation/mainboard/lenovo/vboot.md @@ -0,0 +1,39 @@ +# Using coreboot's verified boot on Lenovo devices + +By default a single instance of coreboot is present in the firmware flash, +no verification is done and the flash is not write-protected, so as to allow +firmware updates from the OS. +The verified boot mechanism also called [VBOOT] allows secure firmware +updates using an A/B partitioning scheme once enabled. + +## Enabling VBOOT +You can enable [VBOOT] in Kconfig's *Security* section. Besides a verified +boot you can also enable a measured boot by setting +`CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is +present on all recent Lenovo devices. + +## Updating and recovery +As the A/B partition is writeable you can still update them from the OS. +By using the [VBOOT] mechanism you store a copy of coreboot in the `RO` +partition that acts as failsafe in case the regular firmware update, that +goes to the `A` or `B` partition fails. + +**Note:** The `RO` partition isn't write-protected by default. There's a patch +pending on gerrit [CB:32705] that write-protects the `RO` partition. + +On *Lenovo* devices you can enable the *Fn* key as recovery mode switch, by +enabling `CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW`. +Holding the *Fn* at boot will then switch to the recovery image, allowing +to boot and flash a working image to the A/B partition. + +## 8 MiB ROM limitation +*Lenovo* devices with 8 MiB ROM only have a `RO`+`A` partition enabled in the +default FMAP. They are missing the `B` partition, due to size constaints. +You can still provide your own FMAP if you need `RO`+`A`+`B` partitions. + +## CMOS +[VBOOT] on *Lenovo* devices uses the CMOS to store configuration data, like +boot failures and the last successfully booted partition. + +[VBOOT]: ../../security/vboot/index.md +[CB:32705]: https://review.coreboot.org/32705 From 49f63e0aa1fa36dd5d7028955beb63b659de075c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 16:14:26 +0200 Subject: [PATCH 1166/1463] sb/amd/agesa/hudson: Const'ify pci_devfn_t devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5a9078baa2224865d0746b6d41f6053ac3a51e09 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40603 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel --- src/southbridge/amd/agesa/hudson/bootblock.c | 7 ++----- src/southbridge/amd/agesa/hudson/early_setup.c | 6 ++---- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index e103bc4325..e8307b1c07 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -19,9 +19,7 @@ static void hudson_enable_rom(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_s_read_config8(dev, 0x48); @@ -49,7 +47,6 @@ static void hudson_enable_rom(void) void bootblock_early_southbridge_init(void) { - pci_devfn_t dev; u32 data; hudson_enable_rom(); @@ -61,7 +58,7 @@ void bootblock_early_southbridge_init(void) else if (CONFIG(POST_DEVICE_LPC)) hudson_lpc_port80(); - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */ pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a4399c9b2d..ed2b18eaf2 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -60,10 +60,9 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - pci_devfn_t dev; /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); @@ -71,13 +70,12 @@ void hudson_lpc_port80(void) void hudson_lpc_decode(void) { - pci_devfn_t dev; u32 tmp; /* Enable LPC controller */ pm_write8(0xec, pm_read8(0xec) | 0x01); - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* Serial port enumeration on Hudson: * PORT0 - 0x3f8 * PORT1 - 0x2f8 From db4f3bacce835222e53dea91976b15abc2113779 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 16:10:14 +0200 Subject: [PATCH 1167/1463] sb/amd/cimx/sb800: Const'ify pci_devfn_t devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I25a6c3ac2426881c6b3f6390ffdc76f08944b7fa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40602 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel --- src/southbridge/amd/cimx/sb800/bootblock.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 7a1d05bf17..7181243c94 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -9,9 +9,7 @@ static void enable_rom(void) { u16 word; u32 dword; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. * BIT6: Port Enable for serial port 0x3f8-0x3ff * BIT29: Port Enable for KBC port 0x60 and 0x64 @@ -43,7 +41,7 @@ static void enable_rom(void) static void enable_prefetch(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ dword = pci_s_read_config32(dev, 0xb8); @@ -53,7 +51,7 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; From 2f58a007a7528090454d3384bacc973c503b4d20 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 16:07:39 +0200 Subject: [PATCH 1168/1463] sb/pi/hudson: Const'ify pci_devfn_t devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9e63c811c4ac5674b2930304455d828ee516b521 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40601 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel --- src/southbridge/amd/pi/hudson/bootblock.c | 7 ++----- src/southbridge/amd/pi/hudson/early_setup.c | 14 ++++++-------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index d0c3646fd5..021e804b6c 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -19,9 +19,7 @@ static void hudson_enable_rom(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_s_read_config8(dev, 0x48); @@ -49,7 +47,6 @@ static void hudson_enable_rom(void) void bootblock_early_southbridge_init(void) { - pci_devfn_t dev; u32 data; hudson_enable_rom(); @@ -64,7 +61,7 @@ void bootblock_early_southbridge_init(void) else if (CONFIG(POST_DEVICE_LPC)) hudson_lpc_port80(); - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */ pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 126a85c5da..b214ade977 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -92,10 +92,9 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - pci_devfn_t dev; /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); @@ -103,13 +102,12 @@ void hudson_lpc_port80(void) void hudson_lpc_decode(void) { - pci_devfn_t dev; u32 tmp; /* Enable LPC controller */ pm_write8(0xec, pm_read8(0xec) | 0x01); - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 * PORT1 - 0x2f8 @@ -134,7 +132,7 @@ static void enable_wideio(uint8_t port, uint16_t size) LPC_ALT_WIDEIO1_ENABLE, LPC_ALT_WIDEIO2_ENABLE }; - pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + const pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); uint32_t tmp; /* Only allow port 0-2 */ @@ -168,7 +166,7 @@ static void enable_wideio(uint8_t port, uint16_t size) */ static void lpc_wideio_window(uint16_t base, uint16_t size) { - pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + const pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); u32 tmp; /* Support 512 or 16 bytes per range */ @@ -227,7 +225,7 @@ void hudson_clk_output_48Mhz(void) static uintptr_t hudson_spibase(void) { /* Make sure the base address is predictable */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) & 0xfffffff0; @@ -280,7 +278,7 @@ void hudson_read_mode(u32 mode) void hudson_tpm_decode_spi(void) { - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */ + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */ u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase From 2f7f0c62fdacde2b7960c58f8608066f23a8c79b Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Tue, 21 Apr 2020 17:48:10 +0800 Subject: [PATCH 1169/1463] mb/google/hatch/var/jinlon: Update DPTF parameters The change applies the DPTF parameters received from the thermal team. 1. Set PL1 Min to 3W 2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec 3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points for tablet mode. 4. Update trigger points of CPU/TSR0/TSR1 BUG=b:154564062, b:154290855 BRANCH=hatch TEST=build and verified by thermal team. Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../jinlon/include/variant/acpi/dptf.asl | 24 +++++++++++-------- .../variants/jinlon/include/variant/ec.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl index 7824d11776..ddb11efc1a 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define DPTF_CPU_PASSIVE 70 +#define DPTF_CPU_PASSIVE 77 #define DPTF_CPU_CRITICAL 105 #define DPTF_CPU_ACTIVE_AC0 70 #define DPTF_CPU_ACTIVE_AC1 65 @@ -11,13 +11,17 @@ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 62 +#define DPTF_TSR0_PASSIVE 58 #define DPTF_TSR0_CRITICAL 105 +#define DPTF_TSR0_TABLET_PASSIVE 58 +#define DPTF_TSR0_TABLET_CRITICAL 105 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 54 -#define DPTF_TSR1_CRITICAL 105 +#define DPTF_TSR1_PASSIVE 57 +#define DPTF_TSR1_CRITICAL 86 +#define DPTF_TSR1_TABLET_PASSIVE 49 +#define DPTF_TSR1_TABLET_CRITICAL 86 #define DPTF_ENABLE_CHARGER @@ -31,13 +35,13 @@ Name (CHPS, Package () { Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 300, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + /* CPU Throttle Effect on Ambient (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 300, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -45,7 +49,7 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 12000, /* PowerLimitMinimum */ + 3000, /* PowerLimitMinimum */ 15000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h index 54877da690..c947821e2b 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h @@ -5,5 +5,6 @@ #define VARIANT_EC_H #include +#define EC_ENABLE_MULTIPLE_DPTF_PROFILES #endif From 1a82923fd20a500d302c8df73414ce85141a327d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 11:11:05 -0700 Subject: [PATCH 1170/1463] arch/x86/acpigen: Add helpers for generating _ADR This change adds the following helpers: acpigen_write_ADR: Generates _ADR object using provided 64-bit address acpigen_write_ADR_pci_devfn: Generates _ADR object for PCI bus device using devfn as input. acpigen_write_ADR_pci_device: Generates _ADR object for PCI bus device using struct device * as input. BUG=b:153858769 Signed-off-by: Furquan Shaikh Change-Id: I139dfc30aa7db303c1e8bd4a8f9ee0933a60139b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40670 Reviewed-by: Nico Huber Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/arch/x86/acpigen.c | 24 ++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 4 ++++ 2 files changed, 28 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 26fe08fa87..715c38b598 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include static char *gencurrent; @@ -1840,3 +1842,25 @@ void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, acpigen_emit_qword(translation); acpigen_emit_qword(length); } + +void acpigen_write_ADR(uint64_t adr) +{ + acpigen_write_name_qword("_ADR", adr); +} + +void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn) +{ + /* + * _ADR for PCI Bus is encoded as follows: + * [63:32] - unused + * [31:16] - device # + * [15:0] - function # + */ + acpigen_write_ADR(PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn)); +} + +void acpigen_write_ADR_pci_device(const struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_PCI); + acpigen_write_ADR_pci_devfn(dev->path.pci.devfn); +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 4aba5f9024..0eee7ffea7 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -8,6 +8,7 @@ #include #include #include +#include /* Values that can be returned for ACPI Device _STA method */ #define ACPI_STATUS_DEVICE_PRESENT (1 << 0) @@ -369,6 +370,9 @@ void acpigen_write_return_singleton_buffer(uint8_t arg); void acpigen_write_return_byte(uint8_t arg); void acpigen_write_upc(enum acpi_upc_type type); void acpigen_write_pld(const struct acpi_pld *pld); +void acpigen_write_ADR(uint64_t adr); +void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); +void acpigen_write_ADR_pci_device(const struct device *dev); /* * Generate ACPI AML code for _DSM method. * This function takes as input uuid for the device, set of callbacks and From 780639b4ede3beae8708dbc8046d8ae24a450e65 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 23 Apr 2020 17:14:33 +0800 Subject: [PATCH 1171/1463] mb/google/deltaur: Move the code under domain Chip drivers not overrided if out of domain. Only device can get override, so move the code under domain. BUG=b:152924290,b:152931802 TEST=Touch screen and Touch pad can work well. Signed-off-by: Eric Lai Change-Id: Iaaa73e36ec268d26ebd3cafab79179fe22a926a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40655 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../deltaur/variants/deltan/overridetree.cb | 63 +++++++++---------- 1 file changed, 31 insertions(+), 32 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb index 13883d1ac0..01935c549b 100644 --- a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -7,37 +7,36 @@ chip soc/intel/tigerlake device domain 0 on device pci 1f.6 on end # GbE 0x15FC + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E1_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "5" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "stop_delay_ms" = "10" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" + register "has_power_resource" = "1" + register "device_present_gpio" = "GPP_B4" + register "device_present_gpio_invert" = "1" + device i2c 34 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Cirque Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.wake" = "GPE0_DW1_07" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C #1 end - - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""MLFS0000"" - register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E1_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "5" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" - register "stop_delay_ms" = "10" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - register "enable_delay_ms" = "55" - register "has_power_resource" = "1" - register "device_present_gpio" = "GPP_B4" - register "device_present_gpio_invert" = "1" - device i2c 34 on end - end - end # I2C #0 - - device pci 15.1 on - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Cirque Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "generic.wake" = "GPE0_DW1_07" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C #1 end From fd50aea03e57e8efda5bc33f1cbbcd6f2a62e66b Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 23 Apr 2020 17:23:59 +0800 Subject: [PATCH 1172/1463] mb/google/deltaur: Enable DRIVERS_I2C_HID for Touchpad Cirque touchpad uses I2C_HID driver. BUG=b:152931802 TEST=Touch pad can work well in the OS. Signed-off-by: Eric Lai Change-Id: I3f8d5abad2f153f395ba7e3f979ad3d2526e040c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40656 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/deltaur/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 74c82010e0..7395c00ca3 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR def_bool n select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI From 7bcd9a1d91f10c6c58cd4c2b4e0583eec221810c Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 20 Mar 2020 09:55:43 +0100 Subject: [PATCH 1173/1463] drivers/spi/tpm: Add support for non CR50 SPI TPM2 Add support for a STM SPI TPM2 by adding checks for CR50. Tested using ST33HTPH2E32. Change-Id: I015497ca078979a44ba2b84e4995493de1f7247b Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39693 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese Reviewed-by: Julius Werner --- src/drivers/spi/tpm/Kconfig | 7 +++ src/drivers/spi/tpm/tis.c | 1 + src/drivers/spi/tpm/tpm.c | 102 ++++++++++++++++++++++-------------- src/security/tpm/Kconfig | 28 ++++++---- 4 files changed, 89 insertions(+), 49 deletions(-) diff --git a/src/drivers/spi/tpm/Kconfig b/src/drivers/spi/tpm/Kconfig index be43e2314d..8c39a4a44a 100644 --- a/src/drivers/spi/tpm/Kconfig +++ b/src/drivers/spi/tpm/Kconfig @@ -14,6 +14,13 @@ config DRIVER_TPM_SPI_CHIP depends on SPI_TPM config MAINBOARD_HAS_SPI_TPM_CR50 + bool + default n + select MAINBOARD_HAS_SPI_TPM + help + Board has a CR50 SPI TPM + +config MAINBOARD_HAS_SPI_TPM bool default n select SPI_TPM diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 6230751fb1..60dc705bee 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -18,6 +18,7 @@ static const struct { } dev_map[] = { { 0x15d1, 0x001b, "SLB9670" }, { 0x1ae0, 0x0028, "CR50" }, + { 0x104a, 0x0000, "ST33HTPH2E32" }, }; static const char *tis_get_dev_name(struct tpm2_info *info) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 8f93e2a71a..c47aed312c 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -104,47 +104,51 @@ static int tpm_sync(void) */ static int start_transaction(int read_write, size_t bytes, unsigned int addr) { - spi_frame_header header; + spi_frame_header header, header_resp; uint8_t byte; int i; + int ret; struct stopwatch sw; static int tpm_sync_needed; static struct stopwatch wake_up_sw; - /* - * First Cr50 access in each coreboot stage where TPM is used will be - * prepended by a wake up pulse on the CS line. - */ - int wakeup_needed = 1; - /* Wait for TPM to finish previous transaction if needed */ - if (tpm_sync_needed) { - tpm_sync(); + if (CONFIG(TPM_CR50)) { /* - * During the first invocation of this function on each stage - * this if () clause code does not run (as tpm_sync_needed - * value is zero), during all following invocations the - * stopwatch below is guaranteed to be started. + * First Cr50 access in each coreboot stage where TPM is used will be + * prepended by a wake up pulse on the CS line. */ - if (!stopwatch_expired(&wake_up_sw)) - wakeup_needed = 0; - } else { - tpm_sync_needed = 1; - } + int wakeup_needed = 1; - if (wakeup_needed) { - /* Just in case Cr50 is asleep. */ - spi_claim_bus(&spi_slave); - udelay(1); - spi_release_bus(&spi_slave); - udelay(100); - } + /* Wait for TPM to finish previous transaction if needed */ + if (tpm_sync_needed) { + tpm_sync(); + /* + * During the first invocation of this function on each stage + * this if () clause code does not run (as tpm_sync_needed + * value is zero), during all following invocations the + * stopwatch below is guaranteed to be started. + */ + if (!stopwatch_expired(&wake_up_sw)) + wakeup_needed = 0; + } else { + tpm_sync_needed = 1; + } - /* - * The Cr50 on H1 does not go to sleep for 1 second after any - * SPI slave activity, let's be conservative and limit the - * window to 900 ms. - */ - stopwatch_init_msecs_expire(&wake_up_sw, 900); + if (wakeup_needed) { + /* Just in case Cr50 is asleep. */ + spi_claim_bus(&spi_slave); + udelay(1); + spi_release_bus(&spi_slave); + udelay(100); + } + + /* + * The Cr50 on H1 does not go to sleep for 1 second after any + * SPI slave activity, let's be conservative and limit the + * window to 900 ms. + */ + stopwatch_init_msecs_expire(&wake_up_sw, 900); + } /* * The first byte of the frame header encodes the transaction type @@ -181,16 +185,30 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) * transmitted by the TPM during the transaction's last byte. * * We know that cr50 is guaranteed to set the flow control bit to 0 - * during the header transfer, but real TPM2 might be fast enough not - * to require to stall the master, this would present an issue. + * during the header transfer. Real TPM2 are fast enough to not require + * to stall the master. They might still use this feature, so test the + * last bit after shifting in the address bytes. * crosbug.com/p/52132 has been opened to track this. */ - spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0); + + header_resp.body[3] = 0; + if (CONFIG(TPM_CR50)) + ret = spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0); + else + ret = spi_xfer(&spi_slave, header.body, sizeof(header.body), + header_resp.body, sizeof(header_resp.body)); + if (ret) { + printk(BIOS_ERR, "SPI-TPM: transfer error\n"); + spi_release_bus(&spi_slave); + return 0; + } + + if (header_resp.body[3] & 1) + return 1; /* * Now poll the bus until TPM removes the stall bit. Give it up to 100 - * ms to sort it out - it could be saving stuff in nvram at some - * point. + * ms to sort it out - it could be saving stuff in nvram at some point. */ stopwatch_init_msecs_expire(&sw, 100); do { @@ -201,6 +219,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) } spi_xfer(&spi_slave, NULL, 0, &byte, 1); } while (!(byte & 1)); + return 1; } @@ -408,7 +427,8 @@ static int tpm2_claim_locality(void) /* Device/vendor ID values of the TPM devices this driver supports. */ static const uint32_t supported_did_vids[] = { - 0x00281ae0 /* H1 based Cr50 security chip. */ + 0x00281ae0, /* H1 based Cr50 security chip. */ + 0x0000104a /* ST33HTPH2E32 */ }; int tpm2_init(struct spi_slave *spi_if) @@ -454,7 +474,8 @@ int tpm2_init(struct spi_slave *spi_if) printk(BIOS_INFO, " done!\n"); - if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK) + // FIXME: Move this to tpm_setup() + if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT)) /* * Claim locality 0, do it only during the first * initialization after reset. @@ -462,7 +483,10 @@ int tpm2_init(struct spi_slave *spi_if) if (!tpm2_claim_locality()) return -1; - read_tpm_sts(&status); + if (!read_tpm_sts(&status)) { + printk(BIOS_ERR, "Reading status reg failed\n"); + return -1; + } if ((status & TPM_STS_FAMILY_MASK) != TPM_STS_FAMILY_TPM_2_0) { printk(BIOS_ERR, "unexpected TPM family value, status: %#x\n", status); diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index d8652b2017..359b8f11f3 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -18,15 +18,19 @@ menu "Trusted Platform Module" config TPM1 bool default y if MAINBOARD_HAS_TPM1 || USER_TPM1 - depends on MAINBOARD_HAS_LPC_TPM || MAINBOARD_HAS_I2C_TPM_GENERIC \ - || MAINBOARD_HAS_I2C_TPM_ATMEL + depends on MAINBOARD_HAS_LPC_TPM || \ + MAINBOARD_HAS_I2C_TPM_GENERIC || \ + MAINBOARD_HAS_I2C_TPM_ATMEL config TPM2 bool default y if MAINBOARD_HAS_TPM2 || USER_TPM2 - depends on MAINBOARD_HAS_I2C_TPM_GENERIC || MAINBOARD_HAS_LPC_TPM \ - || MAINBOARD_HAS_I2C_TPM_ATMEL || MAINBOARD_HAS_I2C_TPM_CR50 \ - || MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_CRB_TPM + depends on MAINBOARD_HAS_I2C_TPM_GENERIC || \ + MAINBOARD_HAS_LPC_TPM || \ + MAINBOARD_HAS_I2C_TPM_ATMEL || \ + MAINBOARD_HAS_I2C_TPM_CR50 || \ + MAINBOARD_HAS_SPI_TPM || \ + MAINBOARD_HAS_CRB_TPM config MAINBOARD_HAS_TPM1 bool @@ -45,8 +49,9 @@ config USER_NO_TPM config USER_TPM1 bool "1.2" - depends on MAINBOARD_HAS_LPC_TPM || MAINBOARD_HAS_I2C_TPM_GENERIC \ - || MAINBOARD_HAS_I2C_TPM_ATMEL + depends on MAINBOARD_HAS_LPC_TPM || \ + MAINBOARD_HAS_I2C_TPM_GENERIC || \ + MAINBOARD_HAS_I2C_TPM_ATMEL help Enable this option to enable TPM 1.0 - 1.2 support in coreboot. @@ -54,9 +59,12 @@ config USER_TPM1 config USER_TPM2 bool "2.0" - depends on MAINBOARD_HAS_I2C_TPM_GENERIC || MAINBOARD_HAS_LPC_TPM \ - || MAINBOARD_HAS_I2C_TPM_ATMEL || MAINBOARD_HAS_I2C_TPM_CR50 \ - || MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_CRB_TPM + depends on MAINBOARD_HAS_I2C_TPM_GENERIC || \ + MAINBOARD_HAS_LPC_TPM || \ + MAINBOARD_HAS_I2C_TPM_ATMEL || \ + MAINBOARD_HAS_I2C_TPM_CR50 || \ + MAINBOARD_HAS_SPI_TPM || \ + MAINBOARD_HAS_CRB_TPM help Enable this option to enable TPM 2.0 support in coreboot. From 78feacc44057916161365d079ae92aa0baa679f8 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 3 Dec 2019 19:43:06 +0100 Subject: [PATCH 1174/1463] security: Add common boot media write protection Introduce boot media protection settings and use the existing boot_device_wp_region() function to apply settings on all platforms that supports it yet. Also remove the Intel southbridge code, which is now obsolete. Every platform locks the SPIBAR in a different stage. For align up with the common mrc cache driver and lock after it has been written to. Tested on Supermicro X11SSH-TF. The whole address space is write-protected. Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32704 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese Reviewed-by: Julius Werner --- src/include/boot_device.h | 8 ++++ src/security/Kconfig | 1 + src/security/Makefile.inc | 1 + src/security/lockdown/Kconfig | 62 +++++++++++++++++++++++++ src/security/lockdown/Makefile.inc | 6 +++ src/security/lockdown/lockdown.c | 57 +++++++++++++++++++++++ src/southbridge/intel/common/Kconfig | 39 ---------------- src/southbridge/intel/common/finalize.c | 10 ---- 8 files changed, 135 insertions(+), 49 deletions(-) create mode 100644 src/security/lockdown/Kconfig create mode 100644 src/security/lockdown/Makefile.inc create mode 100644 src/security/lockdown/lockdown.c diff --git a/src/include/boot_device.h b/src/include/boot_device.h index 4707331ce6..31464624b9 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -62,4 +62,12 @@ int boot_device_wp_region(const struct region_device *rd, **/ void boot_device_init(void); +/* + * Restrict read/write access to the bootmedia using platform defined rules. + */ +#if CONFIG(BOOTMEDIA_LOCK_NONE) +static inline void boot_device_security_lockdown(void) {} +#else +void boot_device_security_lockdown(void); +#endif #endif /* _BOOT_DEVICE_H_ */ diff --git a/src/security/Kconfig b/src/security/Kconfig index b967311345..65d2defe7d 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -15,3 +15,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" source "src/security/memory/Kconfig" source "src/security/intel/Kconfig" +source "src/security/lockdown/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index fd784385e6..72b87dbe73 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -2,3 +2,4 @@ subdirs-y += vboot subdirs-y += tpm subdirs-y += memory subdirs-y += intel +subdirs-y += lockdown diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig new file mode 100644 index 0000000000..bfdc984b45 --- /dev/null +++ b/src/security/lockdown/Kconfig @@ -0,0 +1,62 @@ + + +choice + prompt "Boot media protection mechanism" + default BOOTMEDIA_LOCK_NONE + +config BOOTMEDIA_LOCK_NONE + bool "Don't lock boot media sections" + +config BOOTMEDIA_LOCK_CONTROLLER + bool "Lock boot media using the controller" + help + Select this if you want the controller to lock specific regions. + This only works on some platforms, please check the code or boot log. + On Intel platforms for e.g. this will make use of the SPIBAR PRRs. + +config BOOTMEDIA_LOCK_CHIP + bool "Lock boot media using the chip" + help + Select this if you want the chip to lock specific regions. + This only works on some chips, please check the code or boot log. + +endchoice + +choice + prompt "Boot media protected regions" + depends on !BOOTMEDIA_LOCK_NONE + default BOOTMEDIA_LOCK_WHOLE_RO + +config BOOTMEDIA_LOCK_WHOLE_RO + bool "Write-protect the whole boot medium" + help + Select this if you want to write-protect the whole firmware boot + medium. + + The locking will take place during the chipset lockdown. + Chipset lockdown is platform specific und might be done unconditionally, + when INTEL_CHIPSET_LOCKDOWN is set or has to be triggered later + (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the whole flash chip using the + internal controller any more. + +config BOOTMEDIA_LOCK_WHOLE_NO_ACCESS + depends on BOOTMEDIA_LOCK_CONTROLLER + bool "Read- and write-protect the whole boot medium" + help + Select this if you want to protect the firmware boot medium against + all further accesses. On platforms that memory map a part of the + boot medium the corresponding region is still readable. + + The locking will take place during the chipset lockdown. + Chipset lockdown is platform specific und might be done unconditionally, + when INTEL_CHIPSET_LOCKDOWN is set or has to be triggered later + (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the whole flash chip using the + internal controller any more. + +endchoice diff --git a/src/security/lockdown/Makefile.inc b/src/security/lockdown/Makefile.inc new file mode 100644 index 0000000000..a51a106ebc --- /dev/null +++ b/src/security/lockdown/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This file is part of the coreboot project. + +ifneq ($(CONFIG_BOOTMEDIA_LOCK_NONE),y) +ramstage-y += lockdown.c +endif diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c new file mode 100644 index 0000000000..a8aad9b5eb --- /dev/null +++ b/src/security/lockdown/lockdown.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include + +/* + * Enables read- /write protection of the bootmedia. + */ +void boot_device_security_lockdown(void) +{ + const struct region_device *rdev; + enum bootdev_prot_type lock_type; + + printk(BIOS_DEBUG, "BM-LOCKDOWN: Enabling boot media protection scheme "); + + if (CONFIG(BOOTMEDIA_LOCK_CONTROLLER)) { + if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { + printk(BIOS_DEBUG, "'readonly'"); + lock_type = CTRLR_WP; + } else if (CONFIG(BOOTMEDIA_LOCK_WHOLE_NO_ACCESS)) { + printk(BIOS_DEBUG, "'no access'"); + lock_type = CTRLR_RWP; + } + printk(BIOS_DEBUG, "using CTRL...\n"); + } else { + if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { + printk(BIOS_DEBUG, "'readonly'"); + lock_type = MEDIA_WP; + } + printk(BIOS_DEBUG, "using flash chip...\n"); + } + + rdev = boot_device_ro(); + + if (boot_device_wp_region(rdev, lock_type) >= 0) + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); + else + printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); +} + +static void lock(void *unused) +{ + boot_device_security_lockdown(); +} + +/* + * Keep in sync with mrc_cache.c + */ + +#if CONFIG(MRC_WRITE_NV_LATE) +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL); +#else +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL); +#endif diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index d1b6bf6024..9356a2be16 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -97,42 +97,3 @@ config INTEL_CHIPSET_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE - -if SOUTHBRIDGE_INTEL_COMMON_FINALIZE - -choice - prompt "Flash locking during chipset lockdown" - default LOCK_SPI_FLASH_NONE - -config LOCK_SPI_FLASH_NONE - bool "Don't lock flash sections" - -config LOCK_SPI_FLASH_RO - bool "Write-protect all flash sections" - help - Select this if you want to write-protect the whole firmware flash - chip. The locking will take place during the chipset lockdown, which - is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) - or has to be triggered later (e.g. by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -config LOCK_SPI_FLASH_NO_ACCESS - bool "Write-protect all flash sections and read-protect non-BIOS sections" - help - Select this if you want to protect the firmware flash against all - further accesses (with the exception of the memory mapped BIOS re- - gion which is always readable). The locking will take place during - the chipset lockdown, which is either triggered by coreboot (when - INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. - by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -endchoice - -endif diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 4c6cc63466..2d66cad89c 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -15,16 +15,6 @@ void intel_pch_finalize_smm(void) { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (CONFIG(LOCK_SPI_FLASH_RO) || - CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { - int i; - u32 lockmask = 1UL << 31; - if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) - lockmask |= 1 << 15; - for (i = 0; i < 20; i += 4) - RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; - } - /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); From 6093c5099f673a2f274acfbd9e6b17a9bf76843d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 8 May 2019 18:36:39 +0200 Subject: [PATCH 1175/1463] security/lockdown: Write-protect WP_RO Allow to write protect only the WP_RO region in case of enabled VBOOT. One can either lock the boot device in VERSTAGE early if VBOOT is enabled, or late in RAMSTAGE. Both options have their downsides as explained below. Lock early if you don't trust the code that's stored in the writeable flash partition. This prevents write-protecting the MRC cache, which is written in ramstage. In case the contents of the MRC cache are corrupted this can lead to system instability or trigger unwanted code flows inside the firmware. Lock late if you trust the code that's stored in the writeable flash partition. This allows write-protecting the MRC cache, but if a vulnerability is found in the code of the writeable partition an attacker might be able to overwrite the whole flash as it hasn't been locked yet. Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Signed-off-by: Patrick Rudolph Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32705 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Philipp Deppenwiese --- src/include/boot_device.h | 2 +- src/security/lockdown/Kconfig | 22 ++++++++++++++++++++++ src/security/lockdown/Makefile.inc | 6 ++++++ src/security/lockdown/lockdown.c | 21 ++++++++++++++++++--- src/security/vboot/vboot_logic.c | 5 +++++ 5 files changed, 52 insertions(+), 4 deletions(-) diff --git a/src/include/boot_device.h b/src/include/boot_device.h index 31464624b9..d5237cd45a 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -65,7 +65,7 @@ void boot_device_init(void); /* * Restrict read/write access to the bootmedia using platform defined rules. */ -#if CONFIG(BOOTMEDIA_LOCK_NONE) +#if CONFIG(BOOTMEDIA_LOCK_NONE) || (CONFIG(BOOTMEDIA_LOCK_IN_VERSTAGE) && ENV_RAMSTAGE) static inline void boot_device_security_lockdown(void) {} #else void boot_device_security_lockdown(void); diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index bfdc984b45..30b5237ffc 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -59,4 +59,26 @@ config BOOTMEDIA_LOCK_WHOLE_NO_ACCESS you won't be able to write to the whole flash chip using the internal controller any more. +config BOOTMEDIA_LOCK_WPRO_VBOOT_RO + bool "Write-protect WP_RO FMAP region in boot medium" + depends on VBOOT + help + Select this if you want to write-protect the WP_RO region as specified + in the VBOOT FMAP. You will be able to write every region outside + of WP_RO using the internal controller (eg. FW_MAIN_A/FW_MAIN_B). + In case of BOOTMEDIA_LOCK_IN_VERSTAGE the locking will take place + early, preventing locking of facilities used in ramstage, like the + MRC cache. If not using BOOTMEDIA_LOCK_IN_VERSTAGE the chipset lockdown + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or + has to be triggered later (e.g. by the payload or the OS). + endchoice + +config BOOTMEDIA_LOCK_IN_VERSTAGE + depends on BOOTMEDIA_LOCK_WPRO_VBOOT_RO + bool "Lock boot media down in verstage" + help + Select this if you want to write-protect the WP_RO region as soon as + possible. This option prevents using write protecting facilities in + ramstage, like the MRC cache for example. + Use this option if you don't trust code running after verstage. diff --git a/src/security/lockdown/Makefile.inc b/src/security/lockdown/Makefile.inc index a51a106ebc..6ccc5571d4 100644 --- a/src/security/lockdown/Makefile.inc +++ b/src/security/lockdown/Makefile.inc @@ -2,5 +2,11 @@ ## This file is part of the coreboot project. ifneq ($(CONFIG_BOOTMEDIA_LOCK_NONE),y) + +ifeq ($(CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE),y) +verstage-y += lockdown.c +else ramstage-y += lockdown.c endif + +endif diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index a8aad9b5eb..62d0a2914a 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -5,13 +5,15 @@ #include #include #include +#include /* * Enables read- /write protection of the bootmedia. */ void boot_device_security_lockdown(void) { - const struct region_device *rdev; + const struct region_device *rdev = NULL; + struct region_device dev; enum bootdev_prot_type lock_type; printk(BIOS_DEBUG, "BM-LOCKDOWN: Enabling boot media protection scheme "); @@ -23,19 +25,32 @@ void boot_device_security_lockdown(void) } else if (CONFIG(BOOTMEDIA_LOCK_WHOLE_NO_ACCESS)) { printk(BIOS_DEBUG, "'no access'"); lock_type = CTRLR_RWP; + } else if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { + printk(BIOS_DEBUG, "'WP_RO only'"); + lock_type = CTRLR_WP; } printk(BIOS_DEBUG, "using CTRL...\n"); } else { if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { printk(BIOS_DEBUG, "'readonly'"); lock_type = MEDIA_WP; + } else if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { + printk(BIOS_DEBUG, "'WP_RO only'"); + lock_type = MEDIA_WP; } printk(BIOS_DEBUG, "using flash chip...\n"); } - rdev = boot_device_ro(); + if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { + if (fmap_locate_area_as_rdev("WP_RO", &dev) < 0) + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); + else + rdev = &dev; + } else { + rdev = boot_device_ro(); + } - if (boot_device_wp_region(rdev, lock_type) >= 0) + if (rdev && boot_device_wp_region(rdev, lock_type) >= 0) printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); else printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 8e82e40bf0..e1c77b6004 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "antirollback.h" @@ -296,6 +297,10 @@ void verstage_main(void) timestamp_add_now(TS_START_VBOOT); + /* Lockdown SPI flash controller if required */ + if (CONFIG(BOOTMEDIA_LOCK_IN_VERSTAGE)) + boot_device_security_lockdown(); + /* Set up context and work buffer */ ctx = vboot_get_context(); From 8c82010c9769ea101e78aac38e17fb09bbf11405 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 24 Mar 2020 08:40:45 +0100 Subject: [PATCH 1176/1463] Documentation: Spell vboot all lowercase Update all occurrences of vboot and spell it lowercase. Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3 Signed-off-by: Patrick Rudolph Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/drivers/smmstore.md | 2 +- Documentation/mainboard/index.md | 2 +- Documentation/mainboard/lenovo/vboot.md | 12 ++++++------ Documentation/releases/coreboot-4.11-relnotes.md | 2 +- Documentation/releases/coreboot-4.5-relnotes.md | 2 +- Documentation/releases/coreboot-4.6-relnotes.md | 2 +- Documentation/releases/coreboot-4.8.1-relnotes.md | 2 +- Documentation/security/vboot/index.md | 2 +- Documentation/security/vboot/list_vboot.md | 2 +- Documentation/security/vboot/measured_boot.md | 4 ++-- util/vboot_list/vboot_list.sh | 2 +- 11 files changed, 17 insertions(+), 17 deletions(-) diff --git a/Documentation/drivers/smmstore.md b/Documentation/drivers/smmstore.md index ecf937b1d0..53bac4dc9e 100644 --- a/Documentation/drivers/smmstore.md +++ b/Documentation/drivers/smmstore.md @@ -22,7 +22,7 @@ The API provides append-only semantics for key/value pairs. By default SMMSTORE will operate on a separate FMAP region called `SMMSTORE`. The default generated FMAP will include such a region. -On systems with a locked FMAP, e.g. in an existing VBOOT setup +On systems with a locked FMAP, e.g. in an existing vboot setup with a locked RO region, the option exists to add a cbfsfile called `smm_store` in the `RW_LEGACY` (if CHROMEOS) or in the `COREBOOT` FMAP regions. It is recommended for new builds using diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3426395dfb..e80ff0b512 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -74,7 +74,7 @@ The boards in this section are not real mainboards, but emulators. - [R60](lenovo/r60.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) -- [VBOOT](lenovo/vboot.md) +- [vboot](lenovo/vboot.md) ### Arrandale series diff --git a/Documentation/mainboard/lenovo/vboot.md b/Documentation/mainboard/lenovo/vboot.md index 3e4d43bd14..4e1b946d08 100644 --- a/Documentation/mainboard/lenovo/vboot.md +++ b/Documentation/mainboard/lenovo/vboot.md @@ -3,18 +3,18 @@ By default a single instance of coreboot is present in the firmware flash, no verification is done and the flash is not write-protected, so as to allow firmware updates from the OS. -The verified boot mechanism also called [VBOOT] allows secure firmware +The verified boot mechanism also called [vboot] allows secure firmware updates using an A/B partitioning scheme once enabled. -## Enabling VBOOT -You can enable [VBOOT] in Kconfig's *Security* section. Besides a verified +## Enabling vboot +You can enable [vboot] in Kconfig's *Security* section. Besides a verified boot you can also enable a measured boot by setting `CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is present on all recent Lenovo devices. ## Updating and recovery As the A/B partition is writeable you can still update them from the OS. -By using the [VBOOT] mechanism you store a copy of coreboot in the `RO` +By using the [vboot] mechanism you store a copy of coreboot in the `RO` partition that acts as failsafe in case the regular firmware update, that goes to the `A` or `B` partition fails. @@ -32,8 +32,8 @@ default FMAP. They are missing the `B` partition, due to size constaints. You can still provide your own FMAP if you need `RO`+`A`+`B` partitions. ## CMOS -[VBOOT] on *Lenovo* devices uses the CMOS to store configuration data, like +[vboot] on *Lenovo* devices uses the CMOS to store configuration data, like boot failures and the last successfully booted partition. -[VBOOT]: ../../security/vboot/index.md [CB:32705]: https://review.coreboot.org/32705 +[vboot]: ../../security/vboot/index.md diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 890c2d7c36..f26de27104 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -175,7 +175,7 @@ of becoming more generally useful. Payload integration has been updated, coreinfo learned to cope with UPPER CASE commands and libpayload knows how to deal with USB3 hubs. -### Added VBOOT support to the following platforms: +### Added vboot support to the following platforms: * intel/gm45 * intel/nehalem diff --git a/Documentation/releases/coreboot-4.5-relnotes.md b/Documentation/releases/coreboot-4.5-relnotes.md index 8b649991a1..12230b298b 100644 --- a/Documentation/releases/coreboot-4.5-relnotes.md +++ b/Documentation/releases/coreboot-4.5-relnotes.md @@ -73,7 +73,7 @@ Areas with significant updates ### Vendorcode * AMD (14 commits) - Cleanup, add libagesa.a builds, remove unused code. -* Google (22 commits) - VBoot2 updates and cleanup +* Google (22 commits) - vboot2 updates and cleanup * Intel (86 commits) - Add Intel FSP 2.0, update Broadwell DE support ### Payloads (37 commits) diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md index 4d19ba7fcf..6151b2c3fd 100644 --- a/Documentation/releases/coreboot-4.6-relnotes.md +++ b/Documentation/releases/coreboot-4.6-relnotes.md @@ -180,7 +180,7 @@ SuperIO (12 commits) * Add 2 new chips * Consolidate code to use common routines -Vboot (23 commits) +vboot (23 commits) * Add support for recovery hash space in TPM RISC-V (25 commits) diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md index e2462365ac..14f1068a34 100644 --- a/Documentation/releases/coreboot-4.8.1-relnotes.md +++ b/Documentation/releases/coreboot-4.8.1-relnotes.md @@ -77,7 +77,7 @@ Security -------- * Start of refactoring the TPM software stack * Introduced coreboot security section in kconfig -* VBoot & TPM code moved into src/security +* vboot & TPM code moved into src/security Intelmetool ----------- diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index ff2261a669..faa8cb8561 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -196,7 +196,7 @@ not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*. **VBOOT_ENABLE_CBFS_FALLBACK** Normally coreboot will use the active read/write coreboot file system for all -of it's file access when VBOOT is active and is not in recovery mode. +of it's file access when vboot is active and is not in recovery mode. When the `VBOOT_ENABLE_CBFS_FALLBACK` option is enabled the cbfs file system will first try to locate a file in the active read/write file system. If the file diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 1bef8234be..6b41597f18 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -1,4 +1,4 @@ -# VBOOT enabled devices +# vboot-enabled devices ## Emulation - QEMU x86 i440fx/piix4 (aka qemu -M pc) diff --git a/Documentation/security/vboot/measured_boot.md b/Documentation/security/vboot/measured_boot.md index 45d66dd2d2..df4cc68008 100644 --- a/Documentation/security/vboot/measured_boot.md +++ b/Documentation/security/vboot/measured_boot.md @@ -120,12 +120,12 @@ PCR-7 are left empty. ### PCR-0 _Hash:_ SHA1 -_Description:_ Google VBoot GBB flags. +_Description:_ Google vboot GBB flags. ### PCR-1 _Hash:_ SHA1/SHA256 -_Description:_ Google VBoot GBB HWID. +_Description:_ Google vboot GBB HWID. ### PCR-2 _Hash:_ SHA1/SHA256 diff --git a/util/vboot_list/vboot_list.sh b/util/vboot_list/vboot_list.sh index f3e8975e96..8c6a1a17aa 100755 --- a/util/vboot_list/vboot_list.sh +++ b/util/vboot_list/vboot_list.sh @@ -52,4 +52,4 @@ do done } -(echo "# VBOOT enabled devices"; generate_vboot_list) > $OUTPUT_FILE +(echo "# vboot-enabled devices"; generate_vboot_list) > $OUTPUT_FILE From ae48b426832f99bdae88a0da4f62e0071025b6af Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 21 Apr 2020 23:54:42 -0500 Subject: [PATCH 1177/1463] payloads/tianocore: Init submodules Recent changes to upstream edk2 necessitate ensuring that Tianocore's submodules exist and are up to date, otherwise building UefiPayloadPkg will fail. Change method used to detect a dirty tree so that initialized submodules do not taint the result. Test: build qemu with Tianocore UefiPayloadPkg option successfully. Change-Id: Ie2541f048966ec0666d8196508ccdb6c5f089de6 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40590 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- payloads/external/tianocore/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 58eb458904..46bc2bdffa 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -70,12 +70,13 @@ update: $(project_dir) echo " $(TAG) is not a valid git reference"; \ exit 1; \ fi; \ - if git describe --all --dirty | grep -qv dirty; then \ + if git status --ignore-submodules=dirty | grep -qv clean; then \ echo " Checking out $(project_name) revision $(TAG)"; \ git checkout --detach $(TAG); \ else \ echo " Working directory not clean; will not overwrite"; \ - fi + fi; \ + git submodule update --init --recursive checktools: echo "Checking uuid-dev..." From b4a0ec52842d28f1dc6e30d37672935501da0fa2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 22 Apr 2020 02:03:30 -0500 Subject: [PATCH 1178/1463] payloads/tianocore: Allow custom boot splash for UefiPayloadPkg Allow a custom boot splash to be used with UefiPayloadPkg: - remove Kconfig guards restricting to CorebootPayloadPkg - set destination path for logo file based on bootloader selected Test: build/boot qemu with UefiPayloadPkg with custom boot logo Change-Id: Ia0a10d1528f516f6b9d3645b83be0fb4e85bc348 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40591 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- payloads/external/tianocore/Kconfig | 2 -- payloads/external/tianocore/Makefile | 8 +++++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 7717917f94..7d5f038ebd 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -83,7 +83,6 @@ config TIANOCORE_USE_8254_TIMER config TIANOCORE_BOOTSPLASH_IMAGE bool "Use a custom bootsplash image" - depends on TIANOCORE_COREBOOTPAYLOAD help Select this option if you have a bootsplash image that you would like to be used. If this option is not selected, the default @@ -92,7 +91,6 @@ config TIANOCORE_BOOTSPLASH_IMAGE config TIANOCORE_BOOTSPLASH_FILE string "Tianocore Bootsplash path and filename" depends on TIANOCORE_BOOTSPLASH_IMAGE - depends on TIANOCORE_COREBOOTPAYLOAD default "bootsplash.bmp" help The path and filename of the file to use as graphical bootsplash diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 46bc2bdffa..1dc368db7e 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -24,10 +24,12 @@ upstream_git_repo=https://github.com/tianocore/edk2 ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y) bootloader=UefiPayloadPkg +logo_pkg=MdeModulePkg build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE TAG=upstream/master else bootloader=CorebootPayloadPkg +logo_pkg=CorebootPayloadPkg # STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch TAG=origin/$(project_git_branch) endif @@ -96,9 +98,9 @@ build: update checktools echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ /*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \ + $(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \ *) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \ + $(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \ esac \ fi; \ cd $(project_dir); \ @@ -111,7 +113,7 @@ build: update checktools fi; \ build $(BUILD_STR); \ mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ - git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 || true + git checkout $(logo_pkg)/Logo/Logo.bmp > /dev/null 2>&1 || true clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 From 168d8a49b60d54ab4692e83de2439f5fd573cd82 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 20 Apr 2020 18:50:17 -0500 Subject: [PATCH 1179/1463] drivers/intel/gma: put controller in separate header Including i915.h just for the GMA/SSDT related functions means dragging along all of i915_reg.h as well, which is problematic since some platforms (like Apollo Lake) use overlapping symbols. To avoid this conflict, break out the GMA/SSDT bits into their own header which can be included without conflict. Change-Id: I73fb7ef01abaafdcdbc44f1e3f5eb1883fc31616 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40592 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/drivers/intel/gma/gma.h | 22 ++++++++++++++++++++++ src/drivers/intel/gma/i915.h | 16 +--------------- 2 files changed, 23 insertions(+), 15 deletions(-) create mode 100644 src/drivers/intel/gma/gma.h diff --git a/src/drivers/intel/gma/gma.h b/src/drivers/intel/gma/gma.h new file mode 100644 index 0000000000..7d20e6beff --- /dev/null +++ b/src/drivers/intel/gma/gma.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include + +struct i915_gpu_controller_info { + int use_spread_spectrum_clock; + int ndid; + u32 did[5]; +}; + +#define GMA_STATIC_DISPLAYS(ssc) { \ + .use_spread_spectrum_clock = (ssc), \ + .ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \ +} + +void drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); + +#endif diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index f8721a2fa9..e18c795672 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -6,6 +6,7 @@ #include #include +#include #include /* port types. We stick with the same defines as the kernel */ @@ -75,21 +76,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value); void gtt_write(u32 reg, u32 data); u32 gtt_read(u32 reg); -struct i915_gpu_controller_info -{ - int use_spread_spectrum_clock; - int ndid; - u32 did[5]; -}; - -#define GMA_STATIC_DISPLAYS(ssc) { \ - .use_spread_spectrum_clock = (ssc), \ - .ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \ -} - -void -drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); - /* vbt.c */ struct device; void From febe5b8a01c78ce8ee5ccb2bd44694666fb4cc70 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 22 Apr 2020 02:35:47 -0500 Subject: [PATCH 1180/1463] mb/google/octopus: Add VBT for ampton variant Add VBT file, extracted from stock Google firmware, and select its use via Kconfig. Change-Id: I256c1c72d1d1e40ea9426fa717bfc4f9c950a91f Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40595 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/mainboard/google/octopus/Kconfig | 1 + .../google/octopus/variants/ampton/data.vbt | Bin 0 -> 5632 bytes 2 files changed, 1 insertion(+) create mode 100644 src/mainboard/google/octopus/variants/ampton/data.vbt diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index e52e994433..01e9f9fba5 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_AMPTON select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_ESPI diff --git a/src/mainboard/google/octopus/variants/ampton/data.vbt b/src/mainboard/google/octopus/variants/ampton/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..88ae386150f0a64ae86b2e5f0b9b1e3e71995bca GIT binary patch literal 5632 zcmeHLYitx%6h5=F&$~0*?UYAZYPmct+XC&hKqkf^_m5r3#8L~Rov;g==E1PLT0V)O?vo;x$$U0O;P5EbQY z&OPUzIrH6n?mhQ0yP~bCm2RqO2sMW416yh+qbSJm+WaM0&ZMePQ%gs6pf%7@Ro@ic zLcfCruzmiu^8itf^9jYWTpZdp6zlaj=hKG1?w;OQQFUzasiD4p8V-hNVB5A>Z)~7z zC>EtHZJPp=;fbVbPfu@@HtyNk9UCa82qL35EnZi+b{(Z98;az$MJ00adVEq|Tw1<< zqe!Z2f=vx!>~m|VsgX7{)9O%5prxgzp{o8d8g6c?3sr?$YpO+ZT?oOx{=EY|Pwp6^ z{$M^W!FJZ@xO$gquy3HhkOq2tX*2T~q|LFx*uc}VXrV|L&>5?!{KDu?#hKtydQ>m3mo9f zV43wKI9(K0xxDZQas>I5jllQFKOz5u{44TRWQUzVCh}tB2a$`AHzEg-8;~DG?n1Wj zfh(FtWmABpa;D5QBzUdxQa-3hP5V*P?z)7NjYLf8Hl=P%qtG;m1FmV`WP_$TA7(vJ z5COyHs!gOiQ`YN}=fh^b6(t+1cC)T&u1>64^whXpB{>C&1*d6K@!hMMkOiA@dGpSS zksLjitpM6vA`inrGR?Jyc1f5@O5JJRn_%}Dp*t!JIkWsHpZM73u=s*y+(BU6ahV&< zO4SZoXWDM$clT{GM{PEXre&Hmo5y|o|9b>->fi^L8mE&Fc%7ZgjIqeQJQ^YXptZV1hPe-y9McxKwcE+hl2ElK)w~|Z-V3yNv23Q zh*C%-Eh613N-v1y6_I`-N?(iQN0D9?r3?>QKQ(jzs0`h;bie zec&;f7{YDlq>dmO2sWBV6z6>~7N!ejK@PIF^l{+hxE`?&s-sNL2bScsXSJnV&E8$M zMrmJ@oC}_P46!Kii)QY1k*`3f3R#_AZzg-o=mYMjNJ4#WxFg)PE7sfCwKMh~sIZ`J zPOF{=`{t8)M?Yqk=lGhqiJNBMynUVg<9-p2ygCNAq-Ji&Akfec& Date: Tue, 21 Apr 2020 11:52:58 -0500 Subject: [PATCH 1181/1463] mb/google/octopus: add default non-ChromeOS FMAP Add a FMAP which supports SMMSTORE and non-ChromeOS payloads, since GeminiLake-based devices like Octopus cannot use an automatically-generated FMAP due to strict layout requirements. Change-Id: Iebacbea5b3a782b2abf1d6e28acd21b87dc9402b Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40596 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/Kconfig | 3 +++ src/mainboard/google/octopus/default.fmd | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 src/mainboard/google/octopus/default.fmd diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 01e9f9fba5..7d9e1e8efa 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -137,4 +137,7 @@ config DRAM_PART_IN_CBI_BOARD_ID_MIN default 1 if BOARD_GOOGLE_MEEP default 255 if BOARD_GOOGLE_OCTOPUS +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS + endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/default.fmd b/src/mainboard/google/octopus/default.fmd new file mode 100644 index 0000000000..6e6b64fd0b --- /dev/null +++ b/src/mainboard/google/octopus/default.fmd @@ -0,0 +1,24 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xf6f000 { + IFWI@0x0 0x1ff000 + # SMMSTORE requires 64k alignment + SMMSTORE@0xa5e000 0x40000 + RW_MRC_CACHE 0x10000 + FMAP 0x300 + COREBOOT(CBFS) + BIOS_UNUSABLE 0x4f000 + } + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} From 8536072346efa0919f82c7355a1cf03147dda8b9 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 23 Apr 2020 00:46:56 -0500 Subject: [PATCH 1182/1463] soc/baytrail/raminit: Populate SMBIOS type 17 tables Populate SMBIOS type 17 tables using data from SPD and read via IOSF. Refactor print_dram_info() to pass thru SPD data and channel/speed info. Move call to print_dram_info() after cbmem initialization so the SMBIOS data has somewhere to go. Test: build/boot google/swanky, verify via dmidecode. Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/baytrail/romstage/raminit.c | 25 ++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index f1a3c1798b..3ebf8fff2a 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -55,7 +56,23 @@ static void ABI_X86 send_to_console(unsigned char b) do_putchar(b); } -static void print_dram_info(void) +static void populate_smbios_tables(void *dram_data, int speed, int num_channels) +{ + dimm_attr dimm; + enum spd_status status; + + /* Decode into dimm_attr struct */ + status = spd_decode_ddr3(&dimm, *(spd_raw_data *)dram_data); + + /* Some SPDs have bad CRCs, nothing we can do about it */ + if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) { + /* Add table 17 entry for each channel */ + for (int i = 0; i < num_channels; i++) + spd_add_smbios17(i, 0, speed, &dimm); + } +} + +static void print_dram_info(void *dram_data) { const int mrc_ver_reg = 0xf0; const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); @@ -95,6 +112,8 @@ static void print_dram_info(void) speed = 1600; break; } printk(BIOS_INFO, "%dMHz\n", speed); + + populate_smbios_tables(dram_data, speed, num_channels); } void raminit(struct mrc_params *mp, int prev_sleep_state) @@ -147,8 +166,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) ret = mrc_entry(mp); - print_dram_info(); - if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { @@ -159,6 +176,8 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) #endif } + print_dram_info(mp->mainboard.dram_data[0]); + printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, mp->data_to_save_size); From 8745a2743c046352725957c1657514b0d49309a6 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Wed, 22 Apr 2020 12:13:40 +0530 Subject: [PATCH 1183/1463] soc/intel/jasperlake: Add new MCH device ids Add new MCH device-ids for jasperlake. Reference is taken from jasperlake EDS volume 1 chapter 13.3. BUG=None BRANCH=None TEST=code compiles and able to boot the platform. Change-Id: I38e09579c9a3681e9168c66085cbb3a092dc30cc Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/40589 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Reviewed-by: Aamir Bohra --- src/include/device/pci_ids.h | 3 +++ src/soc/intel/common/block/systemagent/systemagent.c | 3 +++ src/soc/intel/jasperlake/bootblock/report_platform.c | 5 ++++- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3de67ca7dd..2ef3aa37d3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3508,6 +3508,9 @@ #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 +#define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26 +#define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 +#define PCI_DEVICE_ID_INTEL_JSL_ID_4 0x4e14 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 6c0d5f59a6..d78f86f5e0 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -390,6 +390,9 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_JSL_EHL, PCI_DEVICE_ID_INTEL_EHL_ID_1, PCI_DEVICE_ID_INTEL_JSL_ID_1, + PCI_DEVICE_ID_INTEL_JSL_ID_2, + PCI_DEVICE_ID_INTEL_JSL_ID_3, + PCI_DEVICE_ID_INTEL_JSL_ID_4, 0 }; diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index 663c75818f..9cd3c580f6 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -26,7 +26,10 @@ static struct { u16 mchid; const char *name; } mch_table[] = { - { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake SKU4-1" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_2, "Jasperlake SKU4-2" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_3, "Jasperlake SKU2-1" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_4, "Jasperlake SKU2-2" }, }; static struct { From 979c8c7caefdb0a41d18ddd3f1e3473edf6b7861 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 1 Apr 2020 16:04:39 +0530 Subject: [PATCH 1184/1463] mb/intel/jasperlake_rvp: Update SMBIOS data for Jslrvp 1)Change Mainboard Part Number to jslrvp 2)Change Mainboard Family to Intel_jslrvp 3)Generate SMBIOS table and fill sku id information in SMBIOS BUG=None BRANCH=None TEST=Mosys works on jslrvp and Sku ID info is generated Change-Id: Iad0b394fea017223a5b98fff0cb4c2bd1d5a7bd7 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/40011 Reviewed-by: Frans Hendriks Reviewed-by: Maulik V Vaghela Reviewed-by: Subrata Banik Reviewed-by: Ronak Kanabar Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/Kconfig | 4 ++-- src/mainboard/intel/jasperlake_rvp/mainboard.c | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 9f0f8cc6ed..82e57490e5 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -25,11 +25,11 @@ config VARIANT_DIR config MAINBOARD_PART_NUMBER string - default "blackwall" + default "jslrvp" config MAINBOARD_FAMILY string - default "Intel_jasperlake_rvp" + default "Intel_jslrvp" config MAX_CPUS int diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 733bc5131f..e18f9f4637 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -5,6 +5,7 @@ #include #include #include +#include #include static void mainboard_init(void *chip_info) @@ -21,6 +22,12 @@ static void mainboard_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } +const char *smbios_system_sku(void) +{ + static const char *sku_str = "sku2147483647"; /* sku{0-1} */ + return sku_str; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, From d31c150f819f8cd9441cb4a104d91df8eef0294d Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Tue, 14 Apr 2020 18:00:04 +0530 Subject: [PATCH 1185/1463] mb/intel/jasperlake_rvp: Configure GPIO for JSLRVP We need to configure GSPI related gpios for external EC and TPM. Along with GSPI configuring gpios for LAN (power down), FSP_INT and PCH_INT. BUG=None BRANCH=None TEST=External EC card works and LAN is powered down. Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362 Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/Kconfig | 3 ++ .../variants/jslrvp/devicetree.cb | 4 +- .../jasperlake_rvp/variants/jslrvp/gpio.c | 43 ++++++++++++++++++- 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 82e57490e5..a1283bda48 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -63,4 +63,7 @@ config UART_FOR_CONSOLE default 2 if INTEL_LPSS_UART_FOR_CONSOLE default 0 +config TPM_TIS_ACPI_INTERRUPT + int + default 45 # GPE0_DW1_13 (GPP_H13) endif diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 7dc45ae520..cb3d1f3598 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -9,7 +9,7 @@ chip soc/intel/jasperlake # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw1" = "GPP_H" register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration @@ -297,7 +297,7 @@ chip soc/intel/jasperlake chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)" device spi 0 on end end end # GSPI #1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 68f57ffd60..9b86839119 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -18,12 +18,30 @@ static const struct pad_config gpio_table[] = { /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST), + /* GSPI1_CS# */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + + /* GSPI1_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + + /* GSPI1_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* GSPI1_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /*PCH_INT_ODL*/ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), + /* WWAN_PERST_N */ PAD_CFG_GPO(GPP_C0, 0, PLTRST), /* M2_WWAN_SSD_SKT2_CFG2 */ PAD_CFG_GPI(GPP_C3, NONE, PLTRST), + /*SLP_LAN_N*/ + PAD_CFG_GPO(GPP_C7, 0, PLTRST), + /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_2K, DEEP, NF1), @@ -36,18 +54,27 @@ static const struct pad_config gpio_table[] = { /* BT_RF_KILL_N */ PAD_CFG_GPO(GPP_D1, 1, PLTRST), + /*LAN_RST_N*/ + PAD_CFG_GPO(GPP_D6, 1, PLTRST), + /* I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* WWAN_FCP_OFF_N */ PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /*FPS_INT*/ + PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT), + /* WWAN EN GPIO */ PAD_CFG_GPO(GPP_H7, 1, PLTRST), /* M.2_BT_I2S2_SCLK */ PAD_CFG_GPI(GPP_H11, NONE, PLTRST), + /*PCH_INT_ODL*/ + PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT), + /* M.2_BT_I2S2_RXD */ PAD_CFG_GPI(GPP_H14, NONE, PLTRST), @@ -100,7 +127,21 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configurations for TPM */ + + /* GSPI1_CS# */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + + /* GSPI1_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + + /* GSPI1_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* GSPI1_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /*PCH_INT_ODL*/ + PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT), }; const struct pad_config *variant_gpio_table(size_t *num) From d1e0a466d387dc97aae53282c3b4827264993225 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 22 Apr 2020 10:36:34 +0200 Subject: [PATCH 1186/1463] 3rdparty/intel-microcode: Update submodule pointer to 20191115 release Update submodule pointer to 20191115 release to include the microcode update for CML-U62, and others. Signed-off-by: Felix Singer Change-Id: I4765a70be0b1182acd340a3c31a5d71fd0ab500f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40597 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- 3rdparty/intel-microcode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 1dd14da6d1..33b7b2f381 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 1dd14da6d1ea5cfbd95923653f31c04aac3aa655 +Subproject commit 33b7b2f3817e362111cd91910026ab8907f21710 From 007faee9486bcc24e1bc7011717ae88d7eb5e62b Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 22 Apr 2020 00:14:44 +0200 Subject: [PATCH 1187/1463] soc/intel/cometlake: Add ucode from repo On Comet Lake, add the following microcode updates from the 3rdparty repository: - 06-8e-0c (CPUID signature: 0x806ec) - 06-a6-00 (CPUID signature: 0xa0660) Tested with Clevo N141CU. Signed-off-by: Felix Singer Change-Id: Id10b013df8ce98a4e9830782570e20fbcfad05c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40580 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/cannonlake/Makefile.inc | 6 +++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9bd57a353e..6a86576c2b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -39,7 +39,6 @@ config SOC_INTEL_WHISKEYLAKE config SOC_INTEL_COMETLAKE bool select SOC_INTEL_CANNONLAKE_BASE - select MICROCODE_BLOB_UNDISCLOSED select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO help diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c744e9953d..e0605817ae 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -108,7 +108,11 @@ else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y) -# TODO +ifneq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) +# Missing 06-a6-01 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a6-00 +endif endif CPPFLAGS_common += -I$(src)/soc/intel/cannonlake From d2b2be39296d910178173273017800a1b054a1ba Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Mon, 13 Apr 2020 20:48:54 +0800 Subject: [PATCH 1188/1463] soc/intel/cannonlake: Report driver strength by _DSM in eMMC ACPI device According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD. This commit provides _DSM method for driver to query driving strength. TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4 BUG=b:154159888 Signed-off-by: Kane Chen Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/acpi/scs.asl | 56 +++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 775c99781a..8dd3003053 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -20,9 +20,12 @@ Scope (\_SB.PCI0) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name (TEMP, 0) + Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61")) OperationRegion(SCSR, PCI_Config, 0x00, 0x100) Field(SCSR, WordAcc, NoLock, Preserve) { + Offset (0x0), /* PCI VID DID */ + VDID, 32, Offset (0x84), /* PMECTRLSTATUS */ PMCR, 16, Offset (0xA2), /* PG_CONFIG */ @@ -64,6 +67,59 @@ Scope (\_SB.PCI0) { Return (0) } } + /* _DSM x86 Device Specific Method + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^DSUU)) { + /* Check the revision */ + If (LGreaterEqual (Arg1, Zero)) { + /* + * Function Index 0 the return value is a buffer + * containing one bit for each function index, starting + * with zero. + * Bit 0 - Indicates whether there is support for any + * functions other than function 0 + * Bit 1 - Indicates support to clear power control + * register + * Bit 2 - Indicates support to set power control + * register + * Bit 3 - Indicates support to set 1.8V signalling + * Bit 4 - Indicates support to set 3.3V signalling + * Bit 5 - Indicates support for HS200 mode + * Bit 6 - Indicates support for HS400 mode + * Bit 9 - Indicates eMMC I/O Driver Strength + */ + If (LEqual (Arg2, Zero)) { + If (Lequal (VDID, 0x02c48086) ) { + /* + * Set bit 9 for CML eMMC to indicate + * eMMC I/O driver strength is supported + */ + Return(Buffer() {0x0, 0x02}) + } + + } + /* + * Function Index 9, the return value is preferred eMMC + * driver strength + * 0 - 50 ohm + * 1 - 33 ohm + * 2 - 66 ohm + * 3 - 100 ohm + * 4 - 40 ohm + */ + If (LEqual (Arg2, 9)) { + Return(Buffer() {0x4}) + } + } + } + Return(Buffer() { 0x0 }) + } } /* SD CARD */ From 0ee9b14c09c4dfeb59ad94315051ae423b26384d Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 21 Apr 2020 15:32:20 +0800 Subject: [PATCH 1189/1463] soc/intel/common/block/smbus: Set SPD array NULL if no DIMM present Set SPD array NULL if no DIMM present. do_smbus_read_byte returns negative value if SMBus transaction fails. BUG=b:154445630,b:151702387 TEST=Check SPD is NULL if no DIMM in the slot. Signed-off-by: Eric Lai Change-Id: Ie81adbfab5bb1d5c557fe549a158cb68e26b1162 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40558 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/smbus/smbuslib.c | 23 ++++++++++++++------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 4db2c6e7a4..5f60ddcab3 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -38,14 +38,14 @@ static void smbus_read_spd(u8 *spd, u8 addr) } } -static void get_spd(u8 *spd, u8 addr) +/* return -1 if SMBus errors otherwise return 0 */ +static int get_spd(u8 *spd, u8 addr) { - if (do_smbus_read_byte(SMBUS_IO_BASE, addr, 0) == 0xff) { + /* If address is not 0, it will return CB_ERR(-1) if no dimm */ + if (do_smbus_read_byte(SMBUS_IO_BASE, addr, 0) < 0) { printk(BIOS_INFO, "No memory dimm at address %02X\n", addr << 1); - /* Make sure spd is zeroed if dimm doesn't exist. */ - memset(spd, 0, CONFIG_DIMM_SPD_SIZE); - return; + return -1; } smbus_read_spd(spd, addr); @@ -58,6 +58,7 @@ static void get_spd(u8 *spd, u8 addr) /* Restore to page 0 */ do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_0, 0, 0); } + return 0; } static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE]; @@ -66,9 +67,15 @@ void get_spd_smbus(struct spd_block *blk) { u8 i; for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { - get_spd(&spd_data[i * CONFIG_DIMM_SPD_SIZE], - blk->addr_map[i]); - blk->spd_array[i] = &spd_data[i * CONFIG_DIMM_SPD_SIZE]; + if (blk->addr_map[i] == 0) { + blk->spd_array[i] = NULL; + continue; + } + + if (get_spd(&spd_data[i * CONFIG_DIMM_SPD_SIZE], blk->addr_map[i]) == 0) + blk->spd_array[i] = &spd_data[i * CONFIG_DIMM_SPD_SIZE]; + else + blk->spd_array[i] = NULL; } update_spd_len(blk); From c486c78020fc426d8ddb2a74fac5f7c402e4af29 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 27 Apr 2020 15:17:56 +0800 Subject: [PATCH 1190/1463] mb/google/deltaur: Enable PS/2 keyboard By default, the ACPI status method _STA returns false for the PS/2 keyboard and mouse device of the Wilco EC, so the OS does not enable it. Enable these devices, by defining the macro SIO_EC_ENABLE_PS2K. BUG=b:154790509 TEST=Check Keyboard is functional under OS. Signed-off-by: Eric Lai Change-Id: I31c74ddb3608589e5a4753c7e487f250b112bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40745 Reviewed-by: Ivy Jian Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../google/deltaur/variants/baseboard/include/baseboard/ec.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h index 3825cc8824..9f688ae963 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h @@ -7,8 +7,7 @@ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ - - - +/* Enable PS/2 keyboard */ +#define SIO_EC_ENABLE_PS2K #endif /* __MAINBOARD_EC_H__ */ From 5b574e1c859a095ecdf2728a1a6db2d854bbb668 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 23 Apr 2020 13:52:54 +0800 Subject: [PATCH 1191/1463] mb/google/deltaur: Change H1 I2C speed to STANDARD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, Deltaur’s I2C speed has not been tuned yet, so slow down the H1 I2C to avoid I2C error for short term. Error logs: Reading cr50 TPM mode I2C receive timeout I2C read failed: bus 3 addr 0x50 BUG=b:154310066 TEST=Check H1 has no I2C error occurring and can be updated by gsctool. Signed-off-by: Eric Lai Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index e0b3d500d9..498266efdd 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -92,7 +92,7 @@ chip soc/intel/tigerlake .speed = I2C_SPEED_FAST, }, .i2c[3] = { - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_STANDARD, .early_init = 1, }, .i2c[5] = { From ef0cb90ae3a5849f17366338ec5f9f77c1fd3850 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 23 Apr 2020 21:08:44 +0800 Subject: [PATCH 1192/1463] mb/google/deltaur: Disable POWER_OFF_ON_CR50_UPDATE This is missing configuration of Wiloc projects. Following Wilco projects configuration. CB:32436 The power architecture on this platform is different than most of our other x86 devices and needs some special handling to ensure it powers up again after an EC reset. BUG=b:150165131 Signed-off-by: Eric Lai Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 7395c00ca3..a9197f0f42 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -53,6 +53,10 @@ config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" +config POWER_OFF_ON_CR50_UPDATE + bool + default n + config MAINBOARD_DIR string default "google/deltaur" From d1130af40e5570f9b74e0cf44c05fe1c6a4e46b2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 12:51:42 -0700 Subject: [PATCH 1193/1463] arch/x86/acpi_device: Add a helper function to write PCI device This change adds a helper function to write a PCI device with _ADR and _STA defined for it. BUG=b:153858769 Signed-off-by: Furquan Shaikh Change-Id: I932af917d91198876fe8e90af9bb7a2531bd8960 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40674 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/arch/x86/acpi_device.c | 32 +++++++++++++++++++++++++ src/arch/x86/include/arch/acpi_device.h | 9 +++++++ 2 files changed, 41 insertions(+) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 9f1710e35f..2c461558a2 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -927,3 +928,34 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, return gpio; } + +/* + * This function writes a PCI device with _ADR object: + * Example: + * Scope (\_SB.PCI0) + * { + * Device (IGFX) + * { + * Name (_ADR, 0x0000000000000000) + * Method (_STA, 0, NotSerialized) { Return (status) } + * } + * } + */ +void acpi_device_write_pci_dev(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + assert(dev->path.type == DEVICE_PATH_PCI); + assert(name); + assert(scope); + + acpigen_write_scope(scope); + acpigen_write_device(name); + + acpigen_write_ADR_pci_device(dev); + acpigen_write_STA(acpi_device_status(dev)); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index e9c5cd4de2..362efc4a62 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -501,4 +501,13 @@ size_t acpi_dp_add_property_list(struct acpi_dp *dp, /* Write Device Property hierarchy and clean up resources */ void acpi_dp_write(struct acpi_dp *table); +/* + * Helper function to write a PCI device with _ADR object defined. + * + * IMPORTANT: Scope of a device created in SSDT cannot be used to add ACPI nodes under that + * scope in DSDT. So, if there are any references to this PCI device scope required from static + * asl files, do not use this function and instead add the device to DSDT as well. + */ +void acpi_device_write_pci_dev(struct device *dev); + #endif From 590bdc649e6ffc8dcb421e69e26e783b5d145d04 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 15 Apr 2020 23:00:44 -0700 Subject: [PATCH 1194/1463] soc/amd: Update macro name for IOMMU on AMD Family 17h IOMMU for AMD Family 17h Model 10-20h uses the same PCI device ID 0x15D1. This change updates the name to indicate that the PCI device ID is supported for FP5(Model 18h) and FT5(Model 20h). BUG=b:153858769 BRANCH=None TEST=Trembyle and dalboz still build. Signed-off-by: Furquan Shaikh Change-Id: I17c782000ed525075a3e438ed820a22d9af61a26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40672 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/include/device/pci_ids.h | 2 +- src/soc/amd/common/block/iommu/iommu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 2ef3aa37d3..76b214abef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -305,7 +305,7 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 -#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU 0x15d1 +#define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index effdd7ce29..d9517c814c 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -36,7 +36,7 @@ static struct device_operations iommu_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, - PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU, + PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU, 0 }; From a1cd7eb93ed2b2f9a2351399a2036f84d9dfb9ff Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 15 Apr 2020 23:58:22 -0700 Subject: [PATCH 1195/1463] amd/family17h: Add PCI device IDs for all controllers in AMD Family17h This change adds all the missing PCI device IDs for AMD Family 17h. IDs that were already present are updated to include _FAM17H_ in the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs match the family and models as per the PPR. In cases where the controller is present only on certain models, _MODEL##H_ is also included in the name. BUG=b:153858769 BRANCH=None TEST=Verified that trembyle and dalboz still build. Signed-off-by: Furquan Shaikh Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Raul Rangel --- src/include/device/pci_ids.h | 33 +++++++++++++++++++++++------- src/soc/amd/common/block/hda/hda.c | 3 ++- src/soc/amd/common/block/lpc/lpc.c | 2 +- src/soc/amd/picasso/acp.c | 2 +- src/soc/amd/picasso/usb.c | 6 +++--- 5 files changed, 33 insertions(+), 13 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 76b214abef..cfdcab350c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -453,13 +453,32 @@ #define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_PCO_LPC 0x790e -#define PCI_DEVICE_ID_AMD_PCO_HDA0 0x15de -#define PCI_DEVICE_ID_AMD_PCO_HDA1 0x15e3 -#define PCI_DEVICD_ID_AMD_PCO_ACP 0x15e2 -#define PCI_DEVICE_ID_AMD_PCO_XHCI0 0x15e0 -#define PCI_DEVICE_ID_AMD_PCO_XHCI1 0x15e1 -#define PCI_DEVICE_ID_AMD_DALI_XHCI 0x15e5 +#define PCI_DEVICE_ID_AMD_FAM17H_GNB 0x15D0 +#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP 0x15D3 +#define PCI_DEVICE_ID_AMD_FAM17H_GPU 0x15D8 +#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA 0x15DB +#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB 0x15DC +#define PCI_DEVICE_ID_AMD_FAM17H_HDA0 0x15DE +#define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 +#define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 +#define PCI_DEVICE_ID_AMD_FAM17H_DF0 0x15E8 +#define PCI_DEVICE_ID_AMD_FAM17H_DF1 0x15E9 +#define PCI_DEVICE_ID_AMD_FAM17H_DF2 0x15EA +#define PCI_DEVICE_ID_AMD_FAM17H_DF3 0x15EB +#define PCI_DEVICE_ID_AMD_FAM17H_DF4 0x15EC +#define PCI_DEVICE_ID_AMD_FAM17H_DF5 0x15ED +#define PCI_DEVICE_ID_AMD_FAM17H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1 0x7917 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 +#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B +#define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E +#define PCI_DEVICE_ID_AMD_FAM17H_GBE 0x1458 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 1eaee1e578..e4f86df192 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -10,7 +10,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, PCI_DEVICE_ID_AMD_CZ_HDA, - PCI_DEVICE_ID_AMD_PCO_HDA1, + PCI_DEVICE_ID_AMD_FAM17H_HDA0, + PCI_DEVICE_ID_AMD_FAM17H_HDA1, 0 }; diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 3df5ad0ae9..0c98fcbc6b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -324,7 +324,7 @@ static struct device_operations lpc_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_LPC, PCI_DEVICE_ID_AMD_CZ_LPC, - PCI_DEVICE_ID_AMD_PCO_LPC, + PCI_DEVICE_ID_AMD_FAM17H_LPC, 0 }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 3dbc9f7a7a..ce5ced3031 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -56,5 +56,5 @@ static struct device_operations acp_ops = { static const struct pci_driver acp_driver __pci_driver = { .ops = &acp_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICD_ID_AMD_PCO_ACP, + .device = PCI_DEVICE_ID_AMD_FAM17H_ACP, }; diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 67328b8f52..6faf28f2c2 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -34,9 +34,9 @@ static struct device_operations usb_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_PCO_XHCI0, - PCI_DEVICE_ID_AMD_PCO_XHCI1, - PCI_DEVICE_ID_AMD_DALI_XHCI, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1, + PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0, 0 }; From c82aabca0122c5a118f6ab988768bd05eefc3a05 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 13:59:00 -0700 Subject: [PATCH 1196/1463] soc/amd/common: Add a common graphics block device driver for AMD SoCs This change adds a common graphics block device driver for AMD SoCs. In follow-up CLs, this driver will be utilized for Picasso. This driver is added to enable ACPI name and SSDT generation for graphics controller. BUG=b:153858769 Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40675 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/graphics/Kconfig | 5 +++ .../amd/common/block/graphics/Makefile.inc | 1 + src/soc/amd/common/block/graphics/graphics.c | 31 +++++++++++++++++++ 3 files changed, 37 insertions(+) create mode 100644 src/soc/amd/common/block/graphics/Kconfig create mode 100644 src/soc/amd/common/block/graphics/Makefile.inc create mode 100644 src/soc/amd/common/block/graphics/graphics.c diff --git a/src/soc/amd/common/block/graphics/Kconfig b/src/soc/amd/common/block/graphics/Kconfig new file mode 100644 index 0000000000..8aa2a20a3c --- /dev/null +++ b/src/soc/amd/common/block/graphics/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_GRAPHICS + bool + default n + help + Select this option to use AMD common graphics driver support. diff --git a/src/soc/amd/common/block/graphics/Makefile.inc b/src/soc/amd/common/block/graphics/Makefile.inc new file mode 100644 index 0000000000..3f21aafe7d --- /dev/null +++ b/src/soc/amd/common/block/graphics/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c new file mode 100644 index 0000000000..6d40f7c757 --- /dev/null +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include + +static const char *graphics_acpi_name(const struct device *dev) +{ + return "IGFX"; +} + +static const struct device_operations graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .ops_pci = &pci_dev_ops_pci, + .write_acpi_tables = pci_rom_write_acpi_tables, + .acpi_fill_ssdt = pci_rom_ssdt, + .acpi_name = graphics_acpi_name, +}; + +static const unsigned short pci_device_ids[] = { + 0, +}; + +static const struct pci_driver graphics_driver __pci_driver = { + .ops = &graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids, +}; From 9e1a49cea530f389c0255dc4555590fbb1abaa26 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 14:01:12 -0700 Subject: [PATCH 1197/1463] soc/amd/picasso: Use common block graphics driver This change selects common block graphics driver for Picasso and also adds PCI ID for Family 17h graphics controller to the graphics driver. Since the common driver provides .acpi_name() callback for graphics device, soc_acpi_name() no longer needs to provide the ACPI name for graphics device. BUG=b:153858769 Change-Id: Id3ffcb05d8f8a253a0b27407d52d7907c507cabb Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40676 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons --- src/soc/amd/common/block/graphics/graphics.c | 1 + src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/chip.c | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 6d40f7c757..880573b11f 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -21,6 +21,7 @@ static const struct device_operations graphics_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_GPU, 0, }; diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index c7e65fa57a..3113b27783 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 7b3e7fba59..4b25b888d6 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -51,8 +51,6 @@ const char *soc_acpi_name(const struct device *dev) return NULL; switch (dev->path.pci.devfn) { - case GFX_DEVFN: - return "IGFX"; case PCIE0_DEVFN: return "PBR4"; case PCIE1_DEVFN: From f939df7a959b645cc79872623d72bed475c21157 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 14:13:02 -0700 Subject: [PATCH 1198/1463] soc/amd/{common,picasso}: Move GFX device from static ASL to SSDT This change: 1. Adds PCI device for graphics controller in ACPI SSDT tables using acpi_device_write_pci_dev(). 2. Gets rid of IGFX device from picasso acpi/northbridge.asl. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I3a967cdc43b74f786e645d3fb666506070851a99 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40677 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/soc/amd/common/block/graphics/graphics.c | 9 ++++++++- src/soc/amd/picasso/acpi/northbridge.asl | 5 ----- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 880573b11f..a40aadd256 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -1,9 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ +#include #include #include +static void graphics_fill_ssdt(struct device *dev) +{ + acpi_device_write_pci_dev(dev); + pci_rom_ssdt(dev); +} + static const char *graphics_acpi_name(const struct device *dev) { return "IGFX"; @@ -16,7 +23,7 @@ static const struct device_operations graphics_ops = { .init = pci_dev_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = pci_rom_write_acpi_tables, - .acpi_fill_ssdt = pci_rom_ssdt, + .acpi_fill_ssdt = graphics_fill_ssdt, .acpi_name = graphics_acpi_name, }; diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index c8076015bb..6b6bd7cd86 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -32,11 +32,6 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ -/* Internal Graphics */ -Device(IGFX) { - Name(_ADR, 0x00010000) -} - /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) From 0f007d8ceb7e5c852c645cf773df5c5c37cbf411 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 06:41:18 -0700 Subject: [PATCH 1199/1463] device: Constify struct device * parameter to write_acpi_tables .write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/arch/x86/acpi.c | 8 ++++---- src/arch/x86/include/arch/acpi.h | 8 ++++---- src/device/pci_rom.c | 8 ++++---- src/drivers/ipmi/ipmi_kcs_ops.c | 2 +- src/include/device/device.h | 2 +- src/include/device/pci_rom.h | 4 ++-- src/mainboard/getac/p470/acpi_tables.c | 2 +- src/mainboard/getac/p470/mainboard.h | 2 +- src/mainboard/google/dedede/mainboard.c | 2 +- src/mainboard/google/eve/mainboard.c | 2 +- src/mainboard/google/fizz/mainboard.c | 2 +- src/mainboard/google/glados/mainboard.c | 2 +- src/mainboard/google/octopus/mainboard.c | 2 +- src/mainboard/google/poppy/mainboard.c | 2 +- src/mainboard/google/reef/mainboard.c | 2 +- src/mainboard/intel/cannonlake_rvp/mainboard.c | 2 +- src/mainboard/intel/coffeelake_rvp/mainboard.c | 2 +- src/mainboard/intel/glkrvp/mainboard.c | 2 +- src/mainboard/intel/kunimitsu/mainboard.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00660F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/gm45/acpi.c | 2 +- src/northbridge/intel/gm45/gm45.h | 3 ++- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/acpi.c | 3 ++- src/northbridge/intel/haswell/gma.c | 3 ++- src/northbridge/intel/haswell/haswell.h | 2 +- src/northbridge/intel/i945/gma.c | 2 +- src/northbridge/intel/ironlake/gma.c | 2 +- src/northbridge/intel/pineview/gma.c | 3 ++- src/northbridge/intel/sandybridge/acpi.c | 3 ++- src/northbridge/intel/sandybridge/gma.c | 3 ++- src/northbridge/intel/sandybridge/sandybridge.h | 2 +- src/northbridge/intel/x4x/acpi.c | 2 +- src/northbridge/intel/x4x/gma.c | 2 +- src/northbridge/intel/x4x/x4x.h | 2 +- src/soc/amd/picasso/acpi.c | 2 +- src/soc/amd/picasso/include/soc/acpi.h | 2 +- src/soc/amd/picasso/northbridge.c | 2 +- src/soc/amd/stoneyridge/acpi.c | 2 +- src/soc/amd/stoneyridge/include/soc/acpi.h | 2 +- src/soc/amd/stoneyridge/northbridge.c | 2 +- src/soc/intel/apollolake/acpi.c | 2 +- src/soc/intel/apollolake/graphics.c | 2 +- src/soc/intel/baytrail/gfx.c | 2 +- src/soc/intel/braswell/acpi.c | 2 +- src/soc/intel/braswell/include/soc/acpi.h | 2 +- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/igd.c | 2 +- src/soc/intel/broadwell/include/soc/acpi.h | 2 +- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/cannonlake/acpi.c | 2 +- src/soc/intel/cannonlake/graphics.c | 2 +- src/soc/intel/common/block/acpi/acpi.c | 2 +- src/soc/intel/common/block/include/intelblocks/acpi.h | 4 ++-- src/soc/intel/common/block/include/intelblocks/graphics.h | 2 +- src/soc/intel/common/block/systemagent/systemagent.c | 2 +- src/soc/intel/denverton_ns/acpi.c | 2 +- src/soc/intel/denverton_ns/include/soc/acpi.h | 2 +- src/soc/intel/icelake/graphics.c | 2 +- src/soc/intel/jasperlake/acpi.c | 2 +- src/soc/intel/jasperlake/graphics.c | 2 +- src/soc/intel/skylake/acpi.c | 4 ++-- src/soc/intel/skylake/graphics.c | 2 +- src/soc/intel/skylake/include/soc/acpi.h | 4 ++-- src/soc/intel/tigerlake/acpi.c | 2 +- src/soc/intel/tigerlake/graphics.c | 2 +- src/soc/intel/xeon_sp/cpx/acpi.c | 2 +- src/soc/intel/xeon_sp/skx/acpi.c | 4 ++-- src/soc/intel/xeon_sp/skx/include/soc/acpi.h | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 75 files changed, 95 insertions(+), 89 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 4ff1ad55e1..5c15a5e6af 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -758,9 +758,9 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } -void acpi_create_vfct(struct device *device, +void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, - unsigned long (*acpi_fill_vfct)(struct device *device, + unsigned long (*acpi_fill_vfct)(const struct device *device, acpi_vfct_t *vfct_struct, unsigned long current)) { acpi_header_t *header = &(vfct->header); @@ -791,7 +791,7 @@ void acpi_create_vfct(struct device *device, header->checksum = acpi_checksum((void *)vfct, header->length); } -void acpi_create_ipmi(struct device *device, +void acpi_create_ipmi(const struct device *device, struct acpi_spmi *spmi, const u16 ipmi_revision, const acpi_addr_t *addr, @@ -871,7 +871,7 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, header->checksum = acpi_checksum((void *)ivrs, header->length); } -unsigned long acpi_write_hpet(struct device *device, unsigned long current, +unsigned long acpi_write_hpet(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { acpi_hpet_t *hpet; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index fc250d7da0..9fb6f6fcec 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -906,13 +906,13 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); -void acpi_create_vfct(struct device *device, +void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, - unsigned long (*acpi_fill_vfct)(struct device *device, + unsigned long (*acpi_fill_vfct)(const struct device *device, acpi_vfct_t *vfct_struct, unsigned long current)); -void acpi_create_ipmi(struct device *device, +void acpi_create_ipmi(const struct device *device, struct acpi_spmi *spmi, const u16 ipmi_revision, const acpi_addr_t *addr, @@ -926,7 +926,7 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long current)); void acpi_create_hpet(acpi_hpet_t *hpet); -unsigned long acpi_write_hpet(struct device *device, unsigned long start, +unsigned long acpi_write_hpet(const struct device *device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 2757986938..cfd16e804d 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -16,7 +16,7 @@ void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; } u32 __weak map_oprom_vendev(u32 vendev) { return vendev; } -struct rom_header *pci_rom_probe(struct device *dev) +struct rom_header *pci_rom_probe(const struct device *dev) { struct rom_header *rom_header = NULL; struct pci_data *rom_data; @@ -174,7 +174,7 @@ struct rom_header *pci_rom_load(struct device *dev, #if CONFIG(HAVE_ACPI_TABLES) /* VBIOS may be modified after oprom init so use the copy if present. */ -static struct rom_header *check_initialized(struct device *dev) +static struct rom_header *check_initialized(const struct device *dev) { struct rom_header *run_rom; struct pci_data *rom_data; @@ -198,7 +198,7 @@ static struct rom_header *check_initialized(struct device *dev) } static unsigned long -pci_rom_acpi_fill_vfct(struct device *device, acpi_vfct_t *vfct_struct, +pci_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct, unsigned long current) { acpi_vfct_image_hdr_t *header = &vfct_struct->image_hdr; @@ -233,7 +233,7 @@ pci_rom_acpi_fill_vfct(struct device *device, acpi_vfct_t *vfct_struct, } unsigned long -pci_rom_write_acpi_tables(struct device *device, unsigned long current, +pci_rom_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { /* Only handle VGA devices */ diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7f39135d6d..043616afae 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -165,7 +165,7 @@ static void ipmi_kcs_init(struct device *dev) static uint32_t uid_cnt = 0; static unsigned long -ipmi_write_acpi_tables(struct device *dev, unsigned long current, +ipmi_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) { struct drivers_ipmi_config *conf = NULL; diff --git a/src/include/device/device.h b/src/include/device/device.h index 4983b486a4..295415aa7f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -48,7 +48,7 @@ struct device_operations { void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t); #endif #if CONFIG(HAVE_ACPI_TABLES) - unsigned long (*write_acpi_tables)(struct device *dev, + unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(struct device *dev); void (*acpi_inject_dsdt)(struct device *dev); diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 47db52cf19..d16daf8a86 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -34,12 +34,12 @@ struct pci_data { uint16_t reserved_2; }; -struct rom_header *pci_rom_probe(struct device *dev); +struct rom_header *pci_rom_probe(const struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); unsigned long -pci_rom_write_acpi_tables(struct device *device, +pci_rom_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index c31d76d585..72c18060f0 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -63,7 +63,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt) return header->length; } -unsigned long mainboard_write_acpi_tables(struct device *device, +unsigned long mainboard_write_acpi_tables(const struct device *device, unsigned long start, acpi_rsdp_t *rsdp) { diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h index cc692f07a9..d340c7d3cd 100644 --- a/src/mainboard/getac/p470/mainboard.h +++ b/src/mainboard/getac/p470/mainboard.h @@ -3,6 +3,6 @@ struct acpi_rsdp; -unsigned long mainboard_write_acpi_tables(struct device *device, +unsigned long mainboard_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index aa2de37c06..ba7ba655f0 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -26,7 +26,7 @@ static void mainboard_dev_init(struct device *dev) } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { return current; } diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 76057b3a5d..ab7a5a8b28 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -21,7 +21,7 @@ static void mainboard_init(struct device *dev) } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; uintptr_t end_addr; diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 9f35411c24..4377af3f6c 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -187,7 +187,7 @@ static void mainboard_init(struct device *dev) } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { const char *oem_id = NULL; const char *oem_table_id = NULL; diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 53f9f60098..0d6ba32d0c 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -38,7 +38,7 @@ static uint8_t max_codec_enable(void) } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; uintptr_t end_addr; diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 00ede2cf60..dd4d40de91 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -71,7 +71,7 @@ static void mainboard_init(void *chip_info) } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; uintptr_t end_addr; diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index dc50399b88..e24d6bcaea 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -16,7 +16,7 @@ static void mainboard_init(struct device *dev) mainboard_ec_init(); } -static unsigned long mainboard_write_acpi_tables(struct device *device, +static unsigned long mainboard_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index b17bf90c2e..66cf9c1b68 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -95,7 +95,7 @@ void __weak variant_nhlt_oem_overrides(const char **oem_id, } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; uintptr_t end_addr; diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c index 1fb4997b5d..bde45b110c 100644 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c @@ -19,7 +19,7 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(pads, num); } -static unsigned long mainboard_write_acpi_tables(struct device *device, +static unsigned long mainboard_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index 48dbeb48ce..1759bb95b7 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -18,7 +18,7 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(pads, num); } -static unsigned long mainboard_write_acpi_tables(struct device *device, +static unsigned long mainboard_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index d8ba962d47..f6015a1b7d 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -30,7 +30,7 @@ static void mainboard_init(void *chip_info) } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; uintptr_t end_addr; diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index b645f7cb3c..6166a33f78 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -26,7 +26,7 @@ static uint8_t select_audio_codec(void) } static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; uintptr_t end_addr; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 5826ee16de..32d1ad8655 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -714,7 +714,7 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 57005c7817..e400d106fb 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -453,7 +453,7 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index e6b7db4989..b63dec9a87 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -453,7 +453,7 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 1ee951bd1a..f07a60af60 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -451,7 +451,7 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 7de5b464d5..2742f0673d 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -439,7 +439,7 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8f8c0944b6..d5a6865003 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -763,7 +763,7 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 582771298b..bdd0ed0822 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -96,7 +96,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(struct device *device, +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp) { diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ed92a59257..423a8f25eb 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -438,7 +438,8 @@ u16 get_blc_pwm_freq_value(const char *edid_ascii_string); #include struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, + struct acpi_rsdp *rsdp); #endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 25f7518ff8..93191148e8 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -216,7 +216,7 @@ static void gma_generate_ssdt(struct device *device) } static unsigned long -gma_write_acpi_tables(struct device *const dev, +gma_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index aa75e20bc1..f4d9d65421 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -93,7 +93,8 @@ static unsigned long acpi_fill_dmar(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, +unsigned long northbridge_write_acpi_tables(const struct device *const dev, + unsigned long current, struct acpi_rsdp *const rsdp) { /* Create DMAR table only if we have VT-d capability. */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c6b8fab65a..1014ce527c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -520,7 +520,8 @@ static void gma_generate_ssdt(struct device *dev) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, +static unsigned long gma_write_acpi_tables(const struct device *const dev, + unsigned long current, struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index d5f7b32be5..32ac7c3db4 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -200,7 +200,7 @@ void report_platform_info(void); #include struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); #endif /* __ASSEMBLER__ */ diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 8a19b3e8de..98b8e8a45a 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -765,7 +765,7 @@ static void gma_func0_read_resources(struct device *dev) } static unsigned long -gma_write_acpi_tables(struct device *const dev, +gma_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index c8bbbfd00e..d0f6bde948 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -211,7 +211,7 @@ static void gma_generate_ssdt(struct device *device) } static unsigned long -gma_write_acpi_tables(struct device *const dev, +gma_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index d398b55347..7d6b51d93a 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -278,7 +278,8 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, +static unsigned long gma_write_acpi_tables(const struct device *const dev, + unsigned long current, struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 9fd13e62b6..77aa8149da 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -108,7 +108,8 @@ static unsigned long acpi_fill_dmar(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, +unsigned long northbridge_write_acpi_tables(const struct device *const dev, + unsigned long current, struct acpi_rsdp *const rsdp) { const u32 capid0_a = pci_read_config32(dev, CAPID0_A); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 5c4f548f99..ad94e067c4 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -647,7 +647,8 @@ static void gma_generate_ssdt(struct device *device) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, +static unsigned long gma_write_acpi_tables(const struct device *const dev, + unsigned long current, struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 02d2e1384a..0b29e1705e 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -231,7 +231,7 @@ enum platform_type get_platform_type(void); #include struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); #endif diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 6da2fd0d54..fb1ebab753 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -22,7 +22,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(struct device *device, +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp) { diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index f5335eccb0..c1b7837f0d 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -88,7 +88,7 @@ static void gma_generate_ssdt(struct device *device) } static unsigned long -gma_write_acpi_tables(struct device *const dev, +gma_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index d6d72f436d..23db61bf76 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -403,7 +403,7 @@ extern const u16 ddr3_c2_x23c[3][6]; #include struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); #endif /* __NORTHBRIDGE_INTEL_X4X_H__ */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index c9a1179d52..c3dec352f9 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -238,7 +238,7 @@ void generate_cpu_entries(struct device *device) } } -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 7d159c0b65..bf1651830d 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -10,7 +10,7 @@ #define FADT_PM_PROFILE PM_UNSPECIFIED #endif -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void southbridge_inject_dsdt(struct device *device); diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 99ae542d91..d6409c9653 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -180,7 +180,7 @@ static void northbridge_fill_ssdt_generator(struct device *device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 113d1e6b57..325b59403f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -243,7 +243,7 @@ void generate_cpu_entries(struct device *device) } } -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 0acbf819d1..d6f9bed406 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -16,7 +16,7 @@ #define FADT_PM_PROFILE PM_UNSPECIFIED #endif -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void southbridge_inject_dsdt(struct device *device); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index ae4b747a02..2911c898dd 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -232,7 +232,7 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) } -static unsigned long agesa_write_acpi_tables(struct device *device, +static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index fbfe33ff73..93c8792c3e 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -225,7 +225,7 @@ static unsigned long soc_fill_dmar(unsigned long current) return current; } -unsigned long sa_write_acpi_tables(struct device *const dev, +unsigned long sa_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 033b30046d..e375f409f5 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -52,7 +52,7 @@ void graphics_soc_init(struct device *const dev) } } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, +uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 64c906194e..7e65c966c1 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -394,7 +394,7 @@ static void gma_generate_ssdt(struct device *dev) } static unsigned long -gma_write_acpi_tables(struct device *const dev, +gma_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1e6cea298b..7cabb3a418 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -469,7 +469,7 @@ static int update_igd_opregion(igd_opregion_t *opregion) return 0; } -unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current, +unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { acpi_header_t *ssdt2; diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 6c352b91ad..7a58bec8d8 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -12,7 +12,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); void southcluster_inject_dsdt(struct device *device); -unsigned long southcluster_write_acpi_tables(struct device *device, +unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index c45bd76731..feec61f3a0 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -586,7 +586,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, +unsigned long northbridge_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dbb420529f..6ab9b199a0 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -592,7 +592,7 @@ static void igd_init(struct device *dev) } static unsigned long -gma_write_acpi_tables(struct device *const dev, unsigned long current, +gma_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 7da5b5cb4e..2d39707f78 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -16,6 +16,6 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long northbridge_write_acpi_tables(struct device *dev, +unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); #endif diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index a381bb1084..22547fc4bc 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -596,7 +596,7 @@ static void southcluster_inject_dsdt(struct device *device) } } -static unsigned long broadwell_write_acpi_tables(struct device *device, +static unsigned long broadwell_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 306fa1cbee..39f3fe1de6 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -335,7 +335,7 @@ static unsigned long soc_fill_dmar(unsigned long current) return current; } -unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) { acpi_dmar_t *const dmar = (acpi_dmar_t *)current; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 84e97762af..c2f99570b7 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -74,7 +74,7 @@ void graphics_soc_init(struct device *dev) } } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, +uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fe127a27e7..f1c7b8a5a7 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -181,7 +181,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) soc_fill_fadt(fadt); } -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 502ac6cfac..e1f9bf82b1 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -40,7 +40,7 @@ void soc_write_sci_irq_select(uint32_t scis); * Calls acpi_write_hpet which creates and fills HPET table and * adds it to the RSDT (and XSDT) structure. */ -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); @@ -80,7 +80,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, void soc_fill_fadt(acpi_fadt_t *fadt); /* Chipset specific settings for filling up dmar table */ -unsigned long sa_write_acpi_tables(struct device *dev, +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 5a68952bfc..4187ca10cc 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -30,7 +30,7 @@ void graphics_soc_init(struct device *dev); * End address of graphics opregion so that the called * can use the same for future calls to write_acpi_tables */ -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, +uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp); /* i915 controller info for ACPI backlight controls */ diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index d78f86f5e0..d0e171dcf1 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -34,7 +34,7 @@ __weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, return -1; } -__weak unsigned long sa_write_acpi_tables(struct device *dev, +__weak unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 00c9ba4f85..d425879249 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -264,7 +264,7 @@ int soc_madt_sci_irq_polarity(int sci) return MP_IRQ_POLARITY_HIGH; } -unsigned long southcluster_write_acpi_tables(struct device *device, +unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index d248962ad1..9f7e0c3765 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -10,7 +10,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long southcluster_write_acpi_tables(struct device *device, +unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(struct device *device); diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 0ee340ce3b..b8192c95b6 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -51,7 +51,7 @@ void graphics_soc_init(struct device *dev) pci_dev_init(dev); } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, +uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 29a46195cd..4acd8a6131 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -251,7 +251,7 @@ static unsigned long soc_fill_dmar(unsigned long current) return current; } -unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) { acpi_dmar_t *const dmar = (acpi_dmar_t *)current; diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 0ee340ce3b..b8192c95b6 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -51,7 +51,7 @@ void graphics_soc_init(struct device *dev) pci_dev_init(dev); } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, +uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 75f6b691ac..487916886b 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -588,7 +588,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, +unsigned long northbridge_write_acpi_tables(const struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { @@ -630,7 +630,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c338a674e0..5be398c717 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -147,7 +147,7 @@ static void update_igd_opregion(igd_opregion_t *opregion) /* FIXME: Add platform specific mailbox initialization */ } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, +uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 0d3ade0b11..924d9cb20e 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -17,9 +17,9 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_mainboard_gnvs(global_nvs_t *gnvs); void southbridge_inject_dsdt(struct device *device); -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -unsigned long northbridge_write_acpi_tables(struct device *, +unsigned long northbridge_write_acpi_tables(const struct device *, unsigned long current, struct acpi_rsdp *); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index f8d8986d77..a331b722a7 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -251,7 +251,7 @@ static unsigned long soc_fill_dmar(unsigned long current) return current; } -unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) { acpi_dmar_t *const dmar = (acpi_dmar_t *)current; diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index 4054bd549b..eaa07c394a 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -57,7 +57,7 @@ void graphics_soc_init(struct device *dev) pci_dev_init(dev); } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, +uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 48ad3747fb..0ba0069172 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -18,7 +18,7 @@ #define SCI_INT_NUM 9 -unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { current = acpi_write_hpet(device, current, rsdp); diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index e9edc9917d..589ee856a2 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -498,7 +498,7 @@ int soc_madt_sci_irq_polarity(int sci) return MP_IRQ_POLARITY_HIGH; } -unsigned long southbridge_write_acpi_tables(struct device *device, +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { @@ -871,7 +871,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(struct device *device, +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h index 8e1dcb8d0c..a34cd39698 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h @@ -28,7 +28,7 @@ typedef struct { void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long northbridge_write_acpi_tables(struct device *device, +unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void uncore_inject_dsdt(void); void motherboard_fill_fadt(acpi_fadt_t *fadt); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d9ef5cc538..42469ba3c1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -882,7 +882,7 @@ static void southbridge_fill_ssdt(struct device *dev) intel_acpi_gen_def_acpi_pirq(dev); } -static unsigned long southbridge_write_acpi_tables(struct device *device, +static unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp) { From d14d03a6a8518ac3b4e24e8e35d60ce5e9d726aa Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:27:29 -0700 Subject: [PATCH 1200/1463] arch/x86/acpi_device: Constify struct device * parameter to UID functions acpi_device_uid() and acpi_device_write_uid() do not need to make changes to the device structure. Thus, this change marks struct device * parameter to these functions as const. Change-Id: I3755223766c78f93c57ac80caf392985cfd5c5e5 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40702 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/arch/x86/acpi_device.c | 4 ++-- src/arch/x86/include/arch/acpi_device.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 2c461558a2..1dc471c54f 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -95,7 +95,7 @@ const char *acpi_device_hid(const struct device *dev) * Generate unique ID based on the ACPI path. * Collisions on the same _HID are possible but very unlikely. */ -uint32_t acpi_device_uid(struct device *dev) +uint32_t acpi_device_uid(const struct device *dev) { const char *path = acpi_device_path(dev); if (!path) @@ -200,7 +200,7 @@ int acpi_device_status(const struct device *dev) /* Write the unique _UID based on ACPI device path. */ -void acpi_device_write_uid(struct device *dev) +void acpi_device_write_uid(const struct device *dev) { acpigen_write_name_integer("_UID", acpi_device_uid(dev)); } diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 362efc4a62..80dab0b1ba 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -52,12 +52,12 @@ struct acpi_dp { struct device; const char *acpi_device_name(const struct device *dev); const char *acpi_device_hid(const struct device *dev); -uint32_t acpi_device_uid(struct device *dev); +uint32_t acpi_device_uid(const struct device *dev); const char *acpi_device_path(const struct device *dev); const char *acpi_device_scope(const struct device *dev); const char *acpi_device_path_join(const struct device *dev, const char *name); int acpi_device_status(const struct device *dev); -void acpi_device_write_uid(struct device *dev); +void acpi_device_write_uid(const struct device *dev); /* * ACPI Descriptor for extended Interrupt() From 5b5c233e909b67482908b0f32452c7cbcd6fae0e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:31:35 -0700 Subject: [PATCH 1201/1463] device: Constify struct device * parameter to dev_name dev_name() does not need to modify the device structure. Hence, this change makes the struct device * parameter to dev_name() as const. Change-Id: I6a94394385e45fd76f68218bf57914bddd2e2121 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40703 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/device_util.c | 2 +- src/include/device/device.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 25e95cfa67..aa2f06a332 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -225,7 +225,7 @@ const char *dev_path(const struct device *dev) return buffer; } -const char *dev_name(struct device *dev) +const char *dev_name(const struct device *dev) { if (dev->name) return dev->name; diff --git a/src/include/device/device.h b/src/include/device/device.h index 295415aa7f..40aa2d0419 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -182,7 +182,7 @@ void dev_finalize_chips(void); int reset_bus(struct bus *bus); void scan_bridges(struct bus *bus); void assign_resources(struct bus *bus); -const char *dev_name(struct device *dev); +const char *dev_name(const struct device *dev); const char *dev_path(const struct device *dev); u32 dev_path_encode(const struct device *dev); const char *bus_path(struct bus *bus); From 00296ea96f469c0ed35b813a9810272b7530df58 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:33:02 -0700 Subject: [PATCH 1202/1463] i2c/designware: Constify struct device * parameter to dw_i2c_soc_dev_to_bus dw_i2c_soc_dev_to_bus() does not need to modify the device structure. Thus, this change makes the struct device * parameter to dw_i2c_soc_dev_to_bus as const. Change-Id: Ibf5c8d8127dff2ab2ccbd1f6b4f553e98e81955f Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40704 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/i2c/designware/dw_i2c.h | 2 +- src/soc/amd/picasso/i2c.c | 2 +- src/soc/amd/stoneyridge/i2c.c | 2 +- src/soc/intel/common/block/i2c/i2c.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 220d2afc74..e309bc12a2 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -129,7 +129,7 @@ int dw_i2c_transfer(unsigned int bus, * -1 = failure * >=0 = logical bus number */ -int dw_i2c_soc_dev_to_bus(struct device *dev); +int dw_i2c_soc_dev_to_bus(const struct device *dev); /* * Common device_operations implementation to initialize the i2c host diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 8ba05aa9de..25dab397c0 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -63,7 +63,7 @@ const char *i2c_acpi_name(const struct device *dev) } } -int dw_i2c_soc_dev_to_bus(struct device *dev) +int dw_i2c_soc_dev_to_bus(const struct device *dev) { switch (dev->path.mmio.addr) { case APU_I2C2_BASE: diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 1fdb41691c..852930a88d 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -64,7 +64,7 @@ const char *i2c_acpi_name(const struct device *dev) } } -int dw_i2c_soc_dev_to_bus(struct device *dev) +int dw_i2c_soc_dev_to_bus(const struct device *dev) { switch (dev->path.mmio.addr) { case I2CA_BASE_ADDRESS: diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 46f19fb5eb..b9638fe242 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -14,7 +14,7 @@ #include #include -int dw_i2c_soc_dev_to_bus(struct device *dev) +int dw_i2c_soc_dev_to_bus(const struct device *dev) { pci_devfn_t devfn = dev->path.pci.devfn; return dw_i2c_soc_devfn_to_bus(devfn); From 0f6e652f397672efcb920cf97a77f488bd82ad97 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:35:23 -0700 Subject: [PATCH 1203/1463] drivers/ipmi: Add uid parameter to struct drivers_ipmi_config This change adds uid parameter to drivers_ipmi_config that can be used by ipmi_ssdt() to store the uid value to be used by ipmi_write_acpi_tables. This allows to remove the requirement in ipmi_ssdt() to update dev->command. This is being done in preparation to make the struct device * parameter to fill_ssdt as const. Change-Id: Ieb41771c75aae902191bba5d220796e6c343f8e0 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40705 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/ipmi/chip.h | 1 + src/drivers/ipmi/ipmi_kcs_ops.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/drivers/ipmi/chip.h b/src/drivers/ipmi/chip.h index 4e9641b7e5..ede9af693e 100644 --- a/src/drivers/ipmi/chip.h +++ b/src/drivers/ipmi/chip.h @@ -23,6 +23,7 @@ struct drivers_ipmi_config { * Will be used if wait_for_bmc is true. */ u16 bmc_boot_timeout; + unsigned int uid; /* Auto-filled by ipmi_ssdt() */ }; #endif /* _IMPI_CHIP_H_ */ diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 043616afae..349abbce3f 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -212,7 +212,7 @@ ipmi_write_acpi_tables(const struct device *dev, unsigned long current, acpi_create_ipmi(dev, spmi, (ipmi_revision_major << 8) | (ipmi_revision_minor << 4), &addr, IPMI_INTERFACE_KCS, gpe_interrupt, apic_interrupt, - dev->command); + conf->uid); acpi_add_table(rsdp, spmi); @@ -236,14 +236,14 @@ static void ipmi_ssdt(struct device *dev) conf = dev->chip_info; /* Use command to pass UID to ipmi_write_acpi_tables */ - dev->command = uid_cnt++; + conf->uid = uid_cnt++; /* write SPMI device */ acpigen_write_scope(scope); acpigen_write_device("SPMI"); acpigen_write_name_string("_HID", "IPI0001"); acpigen_write_name_unicode("_STR", "IPMI_KCS"); - acpigen_write_name_byte("_UID", dev->command); + acpigen_write_name_byte("_UID", conf->uid); acpigen_write_STA(0xf); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); From 4fc17b47a42e7e530a0921d62f399008541c0908 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:39:08 -0700 Subject: [PATCH 1204/1463] ec/lenovo/h8: Constify struct device * parameter to h8_has_* functions h8_has_bdc() and h8_has_wwan() do not need to modify the device structure. Hence, this change makes the struct device * parameter to these functions as const. This is being done in preparation to make struct device * parameter to fill_ssdt as const. Change-Id: Id3d65d2de7b5161b0e7cff26055c00d5dae967dc Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40706 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/ec/lenovo/h8/bluetooth.c | 2 +- src/ec/lenovo/h8/h8.h | 4 ++-- src/ec/lenovo/h8/wwan.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c index 0ee0c02195..561072ff1e 100644 --- a/src/ec/lenovo/h8/bluetooth.c +++ b/src/ec/lenovo/h8/bluetooth.c @@ -25,7 +25,7 @@ void h8_bluetooth_enable(int on) /* * Detect BDC on supported MBs. */ -bool h8_has_bdc(struct device *dev) +bool h8_has_bdc(const struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index ecc9aabba6..8999cc377a 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -29,11 +29,11 @@ int h8_get_sense_ready(void); void h8_bluetooth_enable(int on); bool h8_bluetooth_nv_enable(void); -bool h8_has_bdc(struct device *dev); +bool h8_has_bdc(const struct device *dev); void h8_wwan_enable(int on); bool h8_wwan_nv_enable(void); -bool h8_has_wwan(struct device *dev); +bool h8_has_wwan(const struct device *dev); void h8_ssdt_generator(struct device *dev); diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index cb60ce8616..4a07604133 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -23,7 +23,7 @@ void h8_wwan_enable(int on) /* * Detect WWAN on supported MBs. */ -bool h8_has_wwan(struct device *dev) +bool h8_has_wwan(const struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; From 8220c4b7789769c529f506113b198367e09e6e58 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:44:27 -0700 Subject: [PATCH 1205/1463] drivers/i2c: Constify struct device * param to i2c fill ssdt callback This change makes the struct device * param to callback function called by i2c_generic_fill_ssdt() as const. This is in preparation to make struct device * param to fill_ssdt as const. Change-Id: I7556b672a7b0172ded44747af394f5b32b6209aa Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40707 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/i2c/generic/chip.h | 2 +- src/drivers/i2c/generic/generic.c | 2 +- src/drivers/i2c/hid/hid.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index ae7c0b42ae..b167b71bed 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -77,7 +77,7 @@ struct drivers_i2c_generic_config { * config: Pointer to drivers_i2c_generic_config structure */ void i2c_generic_fill_ssdt(struct device *dev, - void (*callback)(struct device *dev), + void (*callback)(const struct device *dev), struct drivers_i2c_generic_config *config); #endif /* __I2C_GENERIC_CHIP_H__ */ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 0466a6fe31..38fcfdc160 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -44,7 +44,7 @@ static int i2c_generic_write_gpio(struct acpi_gpio *gpio, int *curr_index) } void i2c_generic_fill_ssdt(struct device *dev, - void (*callback)(struct device *dev), + void (*callback)(const struct device *dev), struct drivers_i2c_generic_config *config) { const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index de43eb9ba5..0cb28bba65 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -10,7 +10,7 @@ #include #if CONFIG(HAVE_ACPI_TABLES) -static void i2c_hid_fill_dsm(struct device *dev) +static void i2c_hid_fill_dsm(const struct device *dev) { struct drivers_i2c_hid_config *config = dev->chip_info; struct dsm_i2c_hid_config dsm_config = { From 3b54fdf282797ca2950341cdba32bb6f451ef53d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:52:27 -0700 Subject: [PATCH 1206/1463] soc/intel: Constify struct device *param to sd_fill_soc_gpio_info sd_fill_soc_gpio_info() does not need to modify device structure. Hence, this change makes the struct device * parameter to this function as const. Change-Id: I237ee9640ec64061aa9ed7c65ea21740c40b6ae2 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40708 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/sd.c | 2 +- src/soc/intel/cannonlake/sd.c | 2 +- src/soc/intel/common/block/include/intelblocks/sd.h | 2 +- src/soc/intel/icelake/sd.c | 2 +- src/soc/intel/jasperlake/sd.c | 2 +- src/soc/intel/skylake/sd.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c index 68c9bcad2f..1007eb129e 100644 --- a/src/soc/intel/apollolake/sd.c +++ b/src/soc/intel/apollolake/sd.c @@ -4,7 +4,7 @@ #include #include "chip.h" -int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev) { config_t *config = config_of(dev); diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c index 68c9bcad2f..1007eb129e 100644 --- a/src/soc/intel/cannonlake/sd.c +++ b/src/soc/intel/cannonlake/sd.c @@ -4,7 +4,7 @@ #include #include "chip.h" -int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev) { config_t *config = config_of(dev); diff --git a/src/soc/intel/common/block/include/intelblocks/sd.h b/src/soc/intel/common/block/include/intelblocks/sd.h index 39ff533112..d0a160de29 100644 --- a/src/soc/intel/common/block/include/intelblocks/sd.h +++ b/src/soc/intel/common/block/include/intelblocks/sd.h @@ -10,6 +10,6 @@ * Fill the GPIO Interrupt or I/O information that will be used for the * GPIO Connection Descriptor. */ -int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev); +int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev); #endif /* SOC_INTEL_COMMON_BLOCK_SD_H */ diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c index db22494208..f3c25e4cc3 100644 --- a/src/soc/intel/icelake/sd.c +++ b/src/soc/intel/icelake/sd.c @@ -4,7 +4,7 @@ #include #include -int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev) { config_t *config = config_of(dev); diff --git a/src/soc/intel/jasperlake/sd.c b/src/soc/intel/jasperlake/sd.c index db22494208..f3c25e4cc3 100644 --- a/src/soc/intel/jasperlake/sd.c +++ b/src/soc/intel/jasperlake/sd.c @@ -4,7 +4,7 @@ #include #include -int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev) { config_t *config = config_of(dev); diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index 70fc62fe94..c98f870d1e 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -4,7 +4,7 @@ #include #include "chip.h" -int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev) { config_t *config = config_of(dev); From ec3dafd97ccdc4cd4b08476724f3f53a47fbdb7a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:53:42 -0700 Subject: [PATCH 1207/1463] soc/intel: Constify struct device * parameter to intel_igd_get_controller_info intel_igd_get_controller_info() does not need to modify the device structure. Hence, this change makes the struct device * parameter to intel_igd_get_controller_info() as const. Change-Id: Ic044a80e3e2c45af6824a23f3cd0b08b94c0f279 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40709 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/graphics/graphics.c | 2 +- src/soc/intel/common/block/include/intelblocks/graphics.h | 2 +- src/soc/intel/skylake/graphics.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 55c181b0bd..a6d45c66e1 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -34,7 +34,7 @@ __weak void graphics_soc_init(struct device *dev) } __weak const struct i915_gpu_controller_info * -intel_igd_get_controller_info(struct device *device) +intel_igd_get_controller_info(const struct device *device) { return NULL; } diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 4187ca10cc..378fdd0567 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -35,7 +35,7 @@ uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, /* i915 controller info for ACPI backlight controls */ const struct i915_gpu_controller_info * -intel_igd_get_controller_info(struct device *device); +intel_igd_get_controller_info(const struct device *device); /* Graphics MMIO register read/write APIs */ uint32_t graphics_gtt_read(unsigned long reg); diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 5be398c717..e1f8fbd3c4 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -177,7 +177,7 @@ uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, } const struct i915_gpu_controller_info * -intel_igd_get_controller_info(struct device *device) +intel_igd_get_controller_info(const struct device *device) { struct soc_intel_skylake_config *chip = device->chip_info; return &chip->gfx; From 7536a398e978aa8ddb0e5f2ae12bae73a708b68f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 21:59:21 -0700 Subject: [PATCH 1208/1463] device: Constify struct device * parameter to acpi_fill_ssdt() .acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/x86/acpi_device.c | 2 +- src/arch/x86/include/arch/acpi.h | 2 +- src/arch/x86/include/arch/acpi_device.h | 2 +- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/device/pci_rom.c | 2 +- src/drivers/crb/tis.c | 2 +- src/drivers/generic/adau7002/adau7002.c | 2 +- src/drivers/generic/generic/generic.c | 2 +- src/drivers/generic/gpio_keys/gpio_keys.c | 2 +- src/drivers/generic/gpio_regulator/gpio_regulator.c | 2 +- src/drivers/generic/max98357a/max98357a.c | 2 +- src/drivers/gfx/generic/generic.c | 2 +- src/drivers/i2c/da7219/da7219.c | 2 +- src/drivers/i2c/designware/dw_i2c.c | 2 +- src/drivers/i2c/designware/dw_i2c.h | 2 +- src/drivers/i2c/generic/chip.h | 2 +- src/drivers/i2c/generic/generic.c | 4 ++-- src/drivers/i2c/hid/hid.c | 2 +- src/drivers/i2c/max98373/max98373.c | 2 +- src/drivers/i2c/max98927/max98927.c | 2 +- src/drivers/i2c/nau8825/nau8825.c | 2 +- src/drivers/i2c/rt1011/rt1011.c | 2 +- src/drivers/i2c/rt5663/rt5663.c | 2 +- src/drivers/i2c/sx9310/sx9310.c | 2 +- src/drivers/i2c/tpm/chip.c | 2 +- src/drivers/intel/ish/ish.c | 2 +- src/drivers/intel/mipi_camera/camera.c | 2 +- src/drivers/intel/wifi/wifi.c | 2 +- src/drivers/ipmi/ipmi_kcs_ops.c | 2 +- src/drivers/net/r8168.c | 2 +- src/drivers/pc80/tpm/tis.c | 2 +- src/drivers/spi/acpi/acpi.c | 2 +- src/drivers/usb/acpi/usb_acpi.c | 2 +- src/drivers/wifi/generic.c | 2 +- src/drivers/wifi/generic_wifi.h | 2 +- src/ec/google/chromeec/ec.h | 2 +- src/ec/google/chromeec/ec_acpi.c | 6 +++--- src/ec/google/wilco/chip.c | 2 +- src/ec/lenovo/h8/h8.h | 2 +- src/ec/lenovo/h8/ssdt.c | 4 ++-- src/include/device/device.h | 2 +- src/include/device/pci_rom.h | 2 +- src/mainboard/lenovo/x200/mainboard.c | 2 +- src/mainboard/lenovo/x201/mainboard.c | 2 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00660F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/gma.c | 2 +- src/northbridge/intel/i945/gma.c | 2 +- src/northbridge/intel/ironlake/gma.c | 2 +- src/northbridge/intel/sandybridge/gma.c | 2 +- src/northbridge/intel/x4x/gma.c | 2 +- src/soc/amd/picasso/acpi.c | 2 +- src/soc/amd/picasso/northbridge.c | 2 +- src/soc/amd/stoneyridge/acpi.c | 2 +- src/soc/amd/stoneyridge/northbridge.c | 2 +- src/soc/intel/baytrail/acpi.c | 2 +- src/soc/intel/baytrail/gfx.c | 2 +- src/soc/intel/braswell/acpi.c | 2 +- src/soc/intel/braswell/gfx.c | 2 +- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/igd.c | 2 +- src/soc/intel/common/block/acpi/acpi.c | 2 +- src/soc/intel/common/block/graphics/graphics.c | 2 +- src/soc/intel/common/block/scs/sd.c | 2 +- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/xeon_sp/skx/acpi.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/sata.c | 2 +- src/southbridge/intel/common/acpi_pirq_gen.c | 2 +- src/southbridge/intel/common/acpi_pirq_gen.h | 2 +- src/southbridge/intel/i82371eb/acpi_tables.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801jx/lpc.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/sata.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/superio/common/generic.c | 2 +- src/superio/common/ssdt.c | 10 +++++----- src/superio/common/ssdt.h | 2 +- src/superio/nuvoton/npcd378/superio.c | 8 ++++---- 91 files changed, 102 insertions(+), 102 deletions(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 1dc471c54f..b4016ef5db 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -941,7 +941,7 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, * } * } */ -void acpi_device_write_pci_dev(struct device *dev) +void acpi_device_write_pci_dev(const struct device *dev) { const char *scope = acpi_device_scope(dev); const char *name = acpi_device_name(dev); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 9fb6f6fcec..86b3932f89 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -930,7 +930,7 @@ unsigned long acpi_write_hpet(const struct device *device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(struct device *device); +void generate_cpu_entries(const struct device *device); void acpi_create_mcfg(acpi_mcfg_t *mcfg); diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 80dab0b1ba..ed64cd8a27 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -508,6 +508,6 @@ void acpi_dp_write(struct acpi_dp *table); * scope in DSDT. So, if there are any references to this PCI device scope required from static * asl files, do not use this function and instead add the device to DSDT as well. */ -void acpi_device_write_pci_dev(struct device *dev); +void acpi_device_write_pci_dev(const struct device *dev); #endif diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index f8f139c8ea..b3cc1e0d5b 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -289,7 +289,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 4f49dba410..a45f021ccb 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -281,7 +281,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index eba853794f..d668f45f23 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -284,7 +284,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 5e8330c76c..1d33640c8b 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -81,7 +81,7 @@ static void gen_pstate_entries(const sst_table_t *const pstates, /** * @brief Generate ACPI entries for Speedstep for each cpu */ -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = determine_total_number_of_cores(); diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index cfd16e804d..4fec2906d6 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -261,7 +261,7 @@ pci_rom_write_acpi_tables(const struct device *device, unsigned long current, return current; } -void pci_rom_ssdt(struct device *device) +void pci_rom_ssdt(const struct device *device) { static size_t ngfx; diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index bd54bb6b54..0e97a07848 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -93,7 +93,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, siz return 0; } -static void crb_tpm_fill_ssdt(struct device *dev) +static void crb_tpm_fill_ssdt(const struct device *dev) { const char *path = acpi_device_path(dev); if (!path) { diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index aa47ae6bb9..bf2f03de04 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -14,7 +14,7 @@ #define ADAU7002_ACPI_NAME "ADAU" #define ADAU7002_ACPI_HID "ADAU7002" -static void adau7002_fill_ssdt(struct device *dev) +static void adau7002_fill_ssdt(const struct device *dev) { struct drivers_generic_adau7002_config *config; struct acpi_dp *dp; diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index cee41a538b..eed824d375 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -10,7 +10,7 @@ #include #include "chip.h" -static void generic_dev_fill_ssdt_generator(struct device *dev) +static void generic_dev_fill_ssdt_generator(const struct device *dev) { struct acpi_dp *dsd; struct drivers_generic_generic_config *config = dev->chip_info; diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index b8e72bf328..1017f7a69f 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -46,7 +46,7 @@ static struct acpi_dp *gpio_keys_add_child_node( return dsd; } -static void gpio_keys_fill_ssdt_generator(struct device *dev) +static void gpio_keys_fill_ssdt_generator(const struct device *dev) { struct drivers_generic_gpio_keys_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 0f39910b85..0ec1626da8 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -9,7 +9,7 @@ #include "chip.h" -static void gpio_regulator_fill_ssdt_generator(struct device *dev) +static void gpio_regulator_fill_ssdt_generator(const struct device *dev) { struct drivers_generic_gpio_regulator_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 599acb5afe..b9c270b0c5 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -14,7 +14,7 @@ #define MAX98357A_ACPI_NAME "MAXM" -static void max98357a_fill_ssdt(struct device *dev) +static void max98357a_fill_ssdt(const struct device *dev) { struct drivers_generic_max98357a_config *config = dev->chip_info; const char *path; diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index aa8d7566f6..4670b4d65f 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -101,7 +101,7 @@ static void gfx_fill_privacy_screen_dsm( privacy); } -static void gfx_fill_ssdt_generator(struct device *dev) +static void gfx_fill_ssdt_generator(const struct device *dev) { size_t i; struct drivers_gfx_generic_config *config = dev->chip_info; diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 4cfeb9fb72..931c437546 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -17,7 +17,7 @@ #define DA7219_ACPI_NAME "DLG7" #define DA7219_ACPI_HID "DLGS7219" -static void da7219_fill_ssdt(struct device *dev) +static void da7219_fill_ssdt(const struct device *dev) { struct drivers_i2c_da7219_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 309dfeee0a..74e24c7a53 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -805,7 +805,7 @@ void dw_i2c_dev_init(struct device *dev) * Generate I2C timing information into the SSDT for the OS driver to consume, * optionally applying override values provided by the caller. */ -void dw_i2c_acpi_fill_ssdt(struct device *dev) +void dw_i2c_acpi_fill_ssdt(const struct device *dev) { const struct dw_i2c_bus_config *bcfg; uintptr_t dw_i2c_addr; diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index e309bc12a2..75df47592e 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -141,7 +141,7 @@ void dw_i2c_dev_init(struct device *dev); * Common device_operations implementation to fill ACPI SSDT table for i2c * host controller. */ -void dw_i2c_acpi_fill_ssdt(struct device *dev); +void dw_i2c_acpi_fill_ssdt(const struct device *dev); /* * Common device_operations implementation for i2c host controller ops. diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index b167b71bed..e1f4472a44 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -76,7 +76,7 @@ struct drivers_i2c_generic_config { * callback: Callback to fill in device-specific information * config: Pointer to drivers_i2c_generic_config structure */ -void i2c_generic_fill_ssdt(struct device *dev, +void i2c_generic_fill_ssdt(const struct device *dev, void (*callback)(const struct device *dev), struct drivers_i2c_generic_config *config); diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 38fcfdc160..7e709d6cc7 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -43,7 +43,7 @@ static int i2c_generic_write_gpio(struct acpi_gpio *gpio, int *curr_index) return ret; } -void i2c_generic_fill_ssdt(struct device *dev, +void i2c_generic_fill_ssdt(const struct device *dev, void (*callback)(const struct device *dev), struct drivers_i2c_generic_config *config) { @@ -159,7 +159,7 @@ void i2c_generic_fill_ssdt(struct device *dev, config->desc ? : dev->chip_ops->name, dev_path(dev)); } -static void i2c_generic_fill_ssdt_generator(struct device *dev) +static void i2c_generic_fill_ssdt_generator(const struct device *dev) { i2c_generic_fill_ssdt(dev, NULL, dev->chip_info); } diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 0cb28bba65..4fac85874d 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -20,7 +20,7 @@ static void i2c_hid_fill_dsm(const struct device *dev) acpigen_write_dsm_i2c_hid(&dsm_config); } -static void i2c_hid_fill_ssdt_generator(struct device *dev) +static void i2c_hid_fill_ssdt_generator(const struct device *dev) { struct drivers_i2c_hid_config *config = dev->chip_info; config->generic.cid = I2C_HID_CID; diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index a7df56baa0..067563868c 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -14,7 +14,7 @@ #define MAX98373_ACPI_NAME "MAXI" #define MAX98373_ACPI_HID "MX98373" -static void max98373_fill_ssdt(struct device *dev) +static void max98373_fill_ssdt(const struct device *dev) { struct drivers_i2c_max98373_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index 0cb80ae88a..ddd9d152b0 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -14,7 +14,7 @@ #define MAX98927_ACPI_NAME "MAXI" #define MAX98927_ACPI_HID "MX98927" -static void max98927_fill_ssdt(struct device *dev) +static void max98927_fill_ssdt(const struct device *dev) { struct drivers_i2c_max98927_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index c3e95e7506..fd9cfc9679 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -19,7 +19,7 @@ #define NAU8825_DP_INT(key,val) \ acpi_dp_add_integer(dp, "nuvoton," key, (val)) -static void nau8825_fill_ssdt(struct device *dev) +static void nau8825_fill_ssdt(const struct device *dev) { struct drivers_i2c_nau8825_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index 68681ef846..ec018cc38f 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -16,7 +16,7 @@ #define RT1011_DP_INT(key, val) acpi_dp_add_integer(dp, "realtek," key, (val)) -static void rt1011_fill_ssdt(struct device *dev) +static void rt1011_fill_ssdt(const struct device *dev) { struct drivers_i2c_rt1011_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 70c14efc45..67d8dea562 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -17,7 +17,7 @@ #define RT5663_DP_INT(key, val) \ acpi_dp_add_integer(dp, "realtek," key, (val)) -static void rt5663_fill_ssdt(struct device *dev) +static void rt5663_fill_ssdt(const struct device *dev) { struct drivers_i2c_rt5663_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index a4fac10f60..44cb883478 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -18,7 +18,7 @@ I2C_SX9310_ACPI_ID "," #NAME, \ config->NAME) -static void i2c_sx9310_fill_ssdt(struct device *dev) +static void i2c_sx9310_fill_ssdt(const struct device *dev) { struct drivers_i2c_sx9310_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index b81b0d17c8..fbf9ffa667 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -11,7 +11,7 @@ #include "tpm.h" #include "chip.h" -static void i2c_tpm_fill_ssdt(struct device *dev) +static void i2c_tpm_fill_ssdt(const struct device *dev) { struct drivers_i2c_tpm_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 3daf4915c6..58402869f4 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -8,7 +8,7 @@ #include #include "chip.h" -static void ish_fill_ssdt_generator(struct device *dev) +static void ish_fill_ssdt_generator(const struct device *dev) { struct drivers_intel_ish_config *config = dev->chip_info; struct device *root = dev->bus->dev; diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index aabf2bad2d..b8e1076346 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -10,7 +10,7 @@ #include #include "chip.h" -static void camera_fill_ssdt(struct device *dev) +static void camera_fill_ssdt(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index c3e551a7b9..ffbab4de79 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -59,7 +59,7 @@ static int smbios_write_wifi(struct device *dev, int *handle, #endif #if CONFIG(HAVE_ACPI_TABLES) -static void intel_wifi_fill_ssdt(struct device *dev) +static void intel_wifi_fill_ssdt(const struct device *dev) { struct drivers_intel_wifi_config *config = dev->chip_info; struct generic_wifi_config generic_config; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 349abbce3f..145313a599 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -221,7 +221,7 @@ ipmi_write_acpi_tables(const struct device *dev, unsigned long current, return current; } -static void ipmi_ssdt(struct device *dev) +static void ipmi_ssdt(const struct device *dev) { const char *scope = acpi_device_scope(dev); struct drivers_ipmi_config *conf = NULL; diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index c547f1776c..b904586dd5 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -306,7 +306,7 @@ static void r8168_init(struct device *dev) #if CONFIG(HAVE_ACPI_TABLES) #define R8168_ACPI_HID "R8168" -static void r8168_net_fill_ssdt(struct device *dev) +static void r8168_net_fill_ssdt(const struct device *dev) { struct drivers_net_config *config = dev->chip_info; const char *path = acpi_device_path(dev->bus->dev); diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 1081410011..3d4c6b6d98 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -872,7 +872,7 @@ static void (*tpm_mci_callbacks[])(void *) = { tpm_mci_func1_cb, }; -static void lpc_tpm_fill_ssdt(struct device *dev) +static void lpc_tpm_fill_ssdt(const struct device *dev) { const char *path = acpi_device_path(dev->bus->dev); u32 arg; diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 76bddbdfe5..0eeaffbddd 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -59,7 +59,7 @@ static int spi_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index) return ret; } -static void spi_acpi_fill_ssdt_generator(struct device *dev) +static void spi_acpi_fill_ssdt_generator(const struct device *dev) { struct drivers_spi_acpi_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index a6a004f760..916d3733ec 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -21,7 +21,7 @@ static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) return true; } -static void usb_acpi_fill_ssdt_generator(struct device *dev) +static void usb_acpi_fill_ssdt_generator(const struct device *dev) { struct drivers_usb_acpi_config *config = dev->chip_info; const char *path = acpi_device_path(dev); diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index fe2e39d29d..b864094499 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -171,7 +171,7 @@ static void emit_sar_acpi_structures(void) acpigen_pop_len(); } -void generic_wifi_fill_ssdt(struct device *dev, +void generic_wifi_fill_ssdt(const struct device *dev, const struct generic_wifi_config *config) { const char *path; diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h index 1c90bc6d66..b863ef4565 100644 --- a/src/drivers/wifi/generic_wifi.h +++ b/src/drivers/wifi/generic_wifi.h @@ -22,7 +22,7 @@ struct generic_wifi_config { * This function implements common device operation to help fill ACPI SSDT * table for WiFi controller. */ -void generic_wifi_fill_ssdt(struct device *dev, +void generic_wifi_fill_ssdt(const struct device *dev, const struct generic_wifi_config *config); /** diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 5f84722ac7..6014143b9d 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -344,7 +344,7 @@ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd); * * @param dev EC device */ -void google_chromeec_fill_ssdt_generator(struct device *dev); +void google_chromeec_fill_ssdt_generator(const struct device *dev); /** * Returns the ACPI name for the EC device. diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 79e3f4bfa1..2331c7a492 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -187,7 +187,7 @@ static void add_usb_port_references(struct acpi_dp *dsd, int port_number) } } -static void fill_ssdt_typec_device(struct device *dev) +static void fill_ssdt_typec_device(const struct device *dev) { struct usb_pd_port_caps port_caps; char con_name[] = "CONx"; @@ -249,7 +249,7 @@ static const enum ps2_action_key ps2_enum_val[] = { [TK_PREV_TRACK] = PS2_KEY_PREV_TRACK, }; -static void fill_ssdt_ps2_keyboard(struct device *dev) +static void fill_ssdt_ps2_keyboard(const struct device *dev) { uint8_t i; struct ec_response_keybd_config keybd = {}; @@ -273,7 +273,7 @@ static void fill_ssdt_ps2_keyboard(struct device *dev) !!(keybd.capabilities & KEYBD_CAP_SCRNLOCK_KEY)); } -void google_chromeec_fill_ssdt_generator(struct device *dev) +void google_chromeec_fill_ssdt_generator(const struct device *dev) { if (!dev->enabled) return; diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 7de4e0235e..0d0f987da3 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -179,7 +179,7 @@ static void wilco_ec_read_resources(struct device *dev) wilco_ec_resource(dev, 2, CONFIG_EC_BASE_PACKET, 16); } -static void wilco_ec_fill_ssdt_generator(struct device *dev) +static void wilco_ec_fill_ssdt_generator(const struct device *dev) { struct opregion opreg; void *region_ptr; diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 8999cc377a..5b2ae1ead9 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -35,7 +35,7 @@ void h8_wwan_enable(int on); bool h8_wwan_nv_enable(void); bool h8_has_wwan(const struct device *dev); -void h8_ssdt_generator(struct device *dev); +void h8_ssdt_generator(const struct device *dev); /* EC registers */ #define H8_CONFIG0 0x00 diff --git a/src/ec/lenovo/h8/ssdt.c b/src/ec/lenovo/h8/ssdt.c index 6b821a40f2..56e305a787 100644 --- a/src/ec/lenovo/h8/ssdt.c +++ b/src/ec/lenovo/h8/ssdt.c @@ -8,7 +8,7 @@ #include "h8.h" #include "chip.h" -static char *h8_dsdt_scope(struct device *dev, const char *scope) +static char *h8_dsdt_scope(const struct device *dev, const char *scope) { static char buf[DEVICE_PATH_MAX] = {}; const char *path = acpi_device_path(dev); @@ -22,7 +22,7 @@ static char *h8_dsdt_scope(struct device *dev, const char *scope) /* * Generates EC SSDT. */ -void h8_ssdt_generator(struct device *dev) +void h8_ssdt_generator(const struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; diff --git a/src/include/device/device.h b/src/include/device/device.h index 40aa2d0419..efa9e8bc58 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -50,7 +50,7 @@ struct device_operations { #if CONFIG(HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); - void (*acpi_fill_ssdt)(struct device *dev); + void (*acpi_fill_ssdt)(const struct device *dev); void (*acpi_inject_dsdt)(struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index d16daf8a86..6b6fee2c44 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -43,7 +43,7 @@ pci_rom_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void pci_rom_ssdt(struct device *device); +void pci_rom_ssdt(const struct device *device); void map_oprom_vendev_rev(u32 *vendev, u8 *rev); u32 map_oprom_vendev(u32 vendev); diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index f3ef0ec59e..86afcfdf72 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -6,7 +6,7 @@ #include #include "dock.h" -static void fill_ssdt(struct device *device) +static void fill_ssdt(const struct device *device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index b29302de0f..785cde6242 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -10,7 +10,7 @@ #include #include -static void fill_ssdt(struct device *device) +static void fill_ssdt(const struct device *device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 86a2040fcf..14080f5f05 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -99,7 +99,7 @@ static void mainboard_init(struct device *dev) } } -static void fill_ssdt(struct device *device) +static void fill_ssdt(const struct device *device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 32d1ad8655..9700ff727d 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -658,7 +658,7 @@ static void cpu_bus_init(struct device *dev) /* North Bridge Structures */ -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index e400d106fb..e861b9804d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -417,7 +417,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b63dec9a87..7852b5eb3a 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -417,7 +417,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f07a60af60..1ead42c92e 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -415,7 +415,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 2742f0673d..e3d753a93d 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -403,7 +403,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index d5a6865003..fa49fc934e 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -727,7 +727,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) return acpi_fill_ivrs11(current, ivrs_agesa); } -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 93191148e8..8a38bdf4ea 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -208,7 +208,7 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -static void gma_generate_ssdt(struct device *device) +static void gma_generate_ssdt(const struct device *device) { const struct northbridge_intel_gm45_config *chip = device->chip_info; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 1014ce527c..4d70d1a001 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -513,7 +513,7 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -static void gma_generate_ssdt(struct device *dev) +static void gma_generate_ssdt(const struct device *dev) { const struct northbridge_intel_haswell_config *chip = dev->chip_info; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 98b8e8a45a..3259ac4dad 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -744,7 +744,7 @@ static void gma_func1_init(struct device *dev) pci_write_config8(dev, 0xf4, 0xff); } -static void gma_generate_ssdt(struct device *device) +static void gma_generate_ssdt(const struct device *device) { const struct northbridge_intel_i945_config *chip = device->chip_info; diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index d0f6bde948..2521105920 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -203,7 +203,7 @@ static void gma_read_resources(struct device *dev) res->size = (resource_t) 0x10000000; } -static void gma_generate_ssdt(struct device *device) +static void gma_generate_ssdt(const struct device *device) { const struct northbridge_intel_ironlake_config *chip = device->chip_info; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index ad94e067c4..bb099f0663 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -640,7 +640,7 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -static void gma_generate_ssdt(struct device *device) +static void gma_generate_ssdt(const struct device *device) { const struct northbridge_intel_sandybridge_config *chip = device->chip_info; diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index c1b7837f0d..03d72649aa 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -80,7 +80,7 @@ static void gma_func0_disable(struct device *dev) pci_write_config16(dev_host, D0F0_GGC, ggc); } -static void gma_generate_ssdt(struct device *device) +static void gma_generate_ssdt(const struct device *device) { const struct northbridge_intel_x4x_config *chip = device->chip_info; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index c3dec352f9..85b40ac8a5 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -220,7 +220,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int cores, cpu; diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index d6409c9653..35d46bcfb6 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -159,7 +159,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 325b59403f..e486c9c59a 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -222,7 +222,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int cores, cpu; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 2911c898dd..db715091cf 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -195,7 +195,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(struct device *device) +static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 3074f1a08f..426c2de95a 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -402,7 +402,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 7e65c966c1..fe842ac266 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -386,7 +386,7 @@ static void gfx_init(struct device *dev) intel_gma_restore_opregion(); } -static void gma_generate_ssdt(struct device *dev) +static void gma_generate_ssdt(const struct device *dev) { const struct soc_intel_baytrail_config *chip = dev->chip_info; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 7cabb3a418..0b68e09316 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -405,7 +405,7 @@ static void generate_p_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index d6671f6936..163acb4fd9 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -77,7 +77,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) gnvs_ptr->aslb = aslb; } -static void gma_generate_ssdt(struct device *dev) +static void gma_generate_ssdt(const struct device *dev) { const struct soc_intel_braswell_config *chip = dev->chip_info; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index feec61f3a0..503e1799b5 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -496,7 +496,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 6ab9b199a0..b030d44c39 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -616,7 +616,7 @@ gma_write_acpi_tables(const struct device *const dev, unsigned long current, return current; } -static void gma_generate_ssdt(struct device *dev) +static void gma_generate_ssdt(const struct device *dev) { const struct soc_intel_broadwell_config *chip = dev->chip_info; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f1c7b8a5a7..995a51da0b 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -431,7 +431,7 @@ __weak void soc_power_states_generation(int core_id, { } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; int plen = 6; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index a6d45c66e1..5392958b42 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -39,7 +39,7 @@ intel_igd_get_controller_info(const struct device *device) return NULL; } -static void gma_generate_ssdt(struct device *device) +static void gma_generate_ssdt(const struct device *device) { const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device); diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index d31e33c90a..8e44738da5 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -7,7 +7,7 @@ #include #if CONFIG(HAVE_ACPI_TABLES) -static void sd_fill_ssdt(struct device *dev) +static void sd_fill_ssdt(const struct device *dev) { const char *path; struct acpi_gpio default_gpio = { 0 }; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 487916886b..aac90c3fd5 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -491,7 +491,7 @@ static void generate_p_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 589ee856a2..8a806be888 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -200,7 +200,7 @@ void generate_p_state_entries(int core, int cores_per_package) { } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; int plen = 6; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 278e90ac00..215965e6f2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -823,7 +823,7 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(struct device *device) +static void southbridge_fill_ssdt(const struct device *device) { struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 75a1b1a363..e65fd6ecae 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -274,7 +274,7 @@ static const char *sata_acpi_name(const struct device *dev) return "SATA"; } -static void sata_fill_ssdt(struct device *dev) +static void sata_fill_ssdt(const struct device *dev) { config_t *config = dev->chip_info; generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index d1e0c8bb70..20dafdfd38 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -71,7 +71,7 @@ static void gen_pirq_route(const enum emit_type emit, const char *lpcb_path, } } -void intel_acpi_gen_def_acpi_pirq(struct device *dev) +void intel_acpi_gen_def_acpi_pirq(const struct device *dev) { const char *lpcb_path = acpi_device_path(dev); char pci_int_mapping[32][4]; diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h index dc2cae9847..acb1bcb1ac 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.h +++ b/src/southbridge/intel/common/acpi_pirq_gen.h @@ -24,7 +24,7 @@ enum pirq { PIRQ_H, }; -void intel_acpi_gen_def_acpi_pirq(struct device *dev); +void intel_acpi_gen_def_acpi_pirq(const struct device *dev); enum pirq intel_common_map_pirq(const struct device *dev, const enum pci_pin pci_pin); diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 9da9c23e53..96fcefcebb 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -25,7 +25,7 @@ static int determine_total_number_of_cores(void) return count; } -void generate_cpu_entries(struct device *device) +void generate_cpu_entries(const struct device *device) { int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; int numcpus = determine_total_number_of_cores(); diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bb876115a3..bc492df15a 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -118,7 +118,7 @@ static void sb_read_resources(struct device *dev) } #if CONFIG(HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(struct device *device) +static void southbridge_acpi_fill_ssdt_generator(const struct device *device) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); generate_cpu_entries(device); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c24460cd81..9b5f5457fc 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -647,7 +647,7 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(struct device *device) +static void southbridge_fill_ssdt(const struct device *device) { intel_acpi_gen_def_acpi_pirq(device); } diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 923056c7a8..a177c6cc64 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -494,7 +494,7 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(struct device *device) +static void southbridge_fill_ssdt(const struct device *device) { struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 91f92859c1..380dca4c30 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -652,7 +652,7 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(struct device *device) +static void southbridge_fill_ssdt(const struct device *device) { struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 395919e676..242d274932 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -716,7 +716,7 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(struct device *device) +static void southbridge_fill_ssdt(const struct device *device) { struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 3a7bdb605f..11ac078c83 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -212,7 +212,7 @@ static void sata_enable(struct device *dev) pci_write_config16(dev, 0x90, map); } -static void sata_fill_ssdt(struct device *dev) +static void sata_fill_ssdt(const struct device *dev) { config_t *config = dev->chip_info; generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 42469ba3c1..d44009b00f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -877,7 +877,7 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(struct device *dev) +static void southbridge_fill_ssdt(const struct device *dev) { intel_acpi_gen_def_acpi_pirq(dev); } diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 88432ff68d..cffe0c3476 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -31,7 +31,7 @@ static void generic_read_resources(struct device *dev) } #if CONFIG(HAVE_ACPI_TABLES) -static void generic_ssdt(struct device *dev) +static void generic_ssdt(const struct device *dev) { const char *scope = acpi_device_scope(dev); const char *name = acpi_device_name(dev); diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index f5ad765aa1..9ff02fb3af 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -29,7 +29,7 @@ static const struct superio_dev superio_devs[] = { static const u8 io_idx[] = {PNP_IDX_IO0, PNP_IDX_IO1, PNP_IDX_IO2, PNP_IDX_IO3}; static const u8 irq_idx[] = {PNP_IDX_IRQ0, PNP_IDX_IRQ1}; -static const struct superio_dev *superio_guess_function(struct device *dev) +static const struct superio_dev *superio_guess_function(const struct device *dev) { for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { struct resource *res = probe_resource(dev, io_idx[i]); @@ -62,7 +62,7 @@ static const struct superio_dev *superio_guess_function(struct device *dev) } /* Return true if there are resources to report */ -static bool has_resources(struct device *dev) +static bool has_resources(const struct device *dev) { for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { struct resource *res = probe_resource(dev, io_idx[i]); @@ -80,7 +80,7 @@ static bool has_resources(struct device *dev) } /* Add IO and IRQ resources for _CRS or _PRS */ -static void ldn_gen_resources(struct device *dev) +static void ldn_gen_resources(const struct device *dev) { uint16_t irq = 0; for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { @@ -109,7 +109,7 @@ static void ldn_gen_resources(struct device *dev) } /* Add resource base and size for additional SuperIO code */ -static void ldn_gen_resources_use(struct device *dev) +static void ldn_gen_resources_use(const struct device *dev) { char name[5]; for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { @@ -161,7 +161,7 @@ static const char *name_from_hid(const char *hid) return "Generic device"; } -void superio_common_fill_ssdt_generator(struct device *dev) +void superio_common_fill_ssdt_generator(const struct device *dev) { if (!dev || !dev->bus || !dev->bus->dev) { printk(BIOS_CRIT, "BUG: Invalid argument in %s!\n", __func__); diff --git a/src/superio/common/ssdt.h b/src/superio/common/ssdt.h index 1f9918950f..5b1efcf8ac 100644 --- a/src/superio/common/ssdt.h +++ b/src/superio/common/ssdt.h @@ -7,6 +7,6 @@ #include const char *superio_common_ldn_acpi_name(const struct device *dev); -void superio_common_fill_ssdt_generator(struct device *dev); +void superio_common_fill_ssdt_generator(const struct device *dev); #endif /* __SUPERIO_COMMON_SSDT_H__ */ diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 94b42a02cf..8f5975ba26 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -115,7 +115,7 @@ static const char *npcd378_acpi_hid(const struct device *dev) } } -static void npcd378_ssdt_aux(struct device *dev) +static void npcd378_ssdt_aux(const struct device *dev) { /* Scope */ acpigen_write_scope(acpi_device_path(dev)); @@ -131,7 +131,7 @@ static void npcd378_ssdt_aux(struct device *dev) acpigen_pop_len(); /* Pop Scope */ } -static void npcd378_ssdt_kbc(struct device *dev) +static void npcd378_ssdt_kbc(const struct device *dev) { /* Scope */ acpigen_write_scope(acpi_device_path(dev)); @@ -147,7 +147,7 @@ static void npcd378_ssdt_kbc(struct device *dev) acpigen_pop_len(); /* Pop Scope */ } -static void npcd378_ssdt_pwr(struct device *dev) +static void npcd378_ssdt_pwr(const struct device *dev) { const char *name = acpi_device_path(dev); const char *scope = acpi_device_scope(dev); @@ -403,7 +403,7 @@ static void npcd378_ssdt_pwr(struct device *dev) acpigen_pop_len(); /* Scope */ } -static void npcd378_fill_ssdt_generator(struct device *dev) +static void npcd378_fill_ssdt_generator(const struct device *dev) { superio_common_fill_ssdt_generator(dev); From 338fd9ad305fa9a27d39b344aa458e677b64df50 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 22:57:05 -0700 Subject: [PATCH 1209/1463] device: Constify struct device * parameter to acpi_inject_dsdt .acpi_inject_dsdt() does not need to modify the device structure. Hence, this change makes the struct device * parameter to acpi_inject_dsdt as const. Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/device/device.h | 2 +- src/soc/amd/picasso/acpi.c | 2 +- src/soc/amd/picasso/include/soc/acpi.h | 2 +- src/soc/amd/stoneyridge/acpi.c | 2 +- src/soc/amd/stoneyridge/include/soc/acpi.h | 2 +- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/braswell/acpi.c | 2 +- src/soc/intel/braswell/include/soc/acpi.h | 2 +- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/common/block/acpi/acpi.c | 2 +- src/soc/intel/common/block/include/intelblocks/acpi.h | 2 +- src/soc/intel/denverton_ns/acpi.c | 2 +- src/soc/intel/denverton_ns/include/soc/acpi.h | 2 +- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/skylake/include/soc/acpi.h | 2 +- src/soc/intel/xeon_sp/cpx/acpi.c | 2 +- src/soc/intel/xeon_sp/skx/acpi.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801jx/lpc.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/vendorcode/google/chromeos/acpi.c | 2 +- src/vendorcode/google/chromeos/chromeos.h | 2 +- 25 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index efa9e8bc58..c21067deeb 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -51,7 +51,7 @@ struct device_operations { unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(const struct device *dev); - void (*acpi_inject_dsdt)(struct device *dev); + void (*acpi_inject_dsdt)(const struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 85b40ac8a5..8e34c85f52 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -267,7 +267,7 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { struct global_nvs_t *gnvs; diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index bf1651830d..68321fffae 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -13,7 +13,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); const char *soc_acpi_name(const struct device *dev); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e486c9c59a..cc9f634959 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -272,7 +272,7 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { struct global_nvs_t *gnvs; diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index d6f9bed406..6a74f22f58 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -19,7 +19,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); const char *soc_acpi_name(const struct device *dev); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 1b0906f789..b40609674f 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -483,7 +483,7 @@ void southcluster_enable_dev(struct device *dev) } } -static void southcluster_inject_dsdt(struct device *device) +static void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 0b68e09316..1c9d6b3e9b 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -512,7 +512,7 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, unsign return current; } -void southcluster_inject_dsdt(struct device *device) +void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 7a58bec8d8..997b7e920c 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -11,7 +11,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -void southcluster_inject_dsdt(struct device *device); +void southcluster_inject_dsdt(const struct device *device); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 22547fc4bc..af3be9e132 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -573,7 +573,7 @@ static void pch_lpc_read_resources(struct device *dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void southcluster_inject_dsdt(struct device *device) +static void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 995a51da0b..e426fae95e 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -243,7 +243,7 @@ __weak void acpi_create_gnvs(struct global_nvs_t *gnvs) { } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { struct global_nvs_t *gnvs; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index e1f9bf82b1..cb10f1f10d 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -48,7 +48,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, * Creates acpi gnvs and adds it to the DSDT table. * GNVS creation is chipset specific and is done in soc specific acpi.c file. */ -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); /* * This function populates the gnvs structure in acpi table. diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d425879249..6f43288457 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -292,7 +292,7 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, return current; } -void southcluster_inject_dsdt(struct device *device) +void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 9f7e0c3765..ae184e92b0 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -13,7 +13,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southcluster_inject_dsdt(struct device *device); +void southcluster_inject_dsdt(const struct device *device); void motherboard_fill_fadt(acpi_fadt_t *fadt); #endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index aac90c3fd5..5ba683f47b 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -641,7 +641,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return acpi_align_current(current); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 924d9cb20e..f63220e13b 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -16,7 +16,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_mainboard_gnvs(global_nvs_t *gnvs); -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); unsigned long northbridge_write_acpi_tables(const struct device *, diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 0ba0069172..0fe471c558 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -34,7 +34,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 8a806be888..9c5c7495f2 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -987,7 +987,7 @@ void uncore_inject_dsdt(void) acpigen_pop_len(); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 215965e6f2..35d71a4d07 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -661,7 +661,7 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9b5f5457fc..e54f2bd80f 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -620,7 +620,7 @@ static void lpc_final(struct device *dev) outb(POST_OS_BOOT, 0x80); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index a177c6cc64..8765cc1584 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -470,7 +470,7 @@ static void i82801ix_lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 380dca4c30..77a8f7772b 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -629,7 +629,7 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 242d274932..4edf87e7c5 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -559,7 +559,7 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d44009b00f..b5fb674a26 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -699,7 +699,7 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs; diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index fad1256b0f..abd5b67095 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -35,7 +35,7 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) acpigen_pop_len(); } -void chromeos_dsdt_generator(struct device *dev) +void chromeos_dsdt_generator(const struct device *dev) { mainboard_chromeos_acpi_generate(); } diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index f7df10f22e..d2d0a7ace3 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -70,7 +70,7 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); */ void mainboard_chromeos_acpi_generate(void); #if CONFIG(CHROMEOS) -void chromeos_dsdt_generator(struct device *dev); +void chromeos_dsdt_generator(const struct device *dev); #else #define chromeos_dsdt_generator NULL #endif From f0ebaf22600e60a84c313840f5718bb123a683e4 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 27 Apr 2020 13:57:05 -0700 Subject: [PATCH 1210/1463] vboot: Always build secdata functions for romstage Since CB:40389, all platforms with CONFIG_VBOOT_EARLY_EC_SYNC need to write back secdata in romstage. Those platforms currently all happen to have CONFIG_VBOOT_SEPARATE_VERSTAGE set as well, but there's no official dependency between those options. Change the Makefile to unconditionally build the secdata access routines for romstage so that this would work on other platforms as well. Signed-off-by: Julius Werner Change-Id: I0b3c79e9bb8af9d09ef91f5749953ca109dd2a40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40760 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri Reviewed-by: Aaron Durbin --- src/security/vboot/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d1cc2da807..67ee0f5786 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -111,10 +111,10 @@ verstage-y += common.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c ifeq (${CONFIG_VBOOT_MOCK_SECDATA},y) verstage-y += secdata_mock.c -romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_mock.c +romstage-y += secdata_mock.c else verstage-y += secdata_tpm.c -romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c +romstage-y += secdata_tpm.c endif ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) From 029b5432a1a5db1b2c985eef5c01586c841cdda9 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Fri, 17 Apr 2020 13:38:10 -0700 Subject: [PATCH 1211/1463] soc/intel/tigerlake: fix call to print_spd_info() Pointer passed to print_spd_info() from meminit.c needs to be dereferenced first, so this change dereferences it. BUG=b:154352883 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, login to kernel and execute the following cbmem command: localhost ~ # cbmem -c | grep LPDDR4X and verify it returns "SPD: module type is LPDDR4X" Change-Id: I5ff64121f0d50947c4946e9e02460dfb7319d01a Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/40496 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/meminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index d44554af7e..ebadcffe84 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -230,7 +230,7 @@ static void read_md_spd(const struct spd_info *info, uintptr_t *data, size_t *le die("Not a valid location(%d) for Memory-down SPD!\n", info->md_spd_loc); } - print_spd_info((unsigned char *)data); + print_spd_info((uint8_t *) *data); } void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, @@ -317,7 +317,7 @@ static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) for (i = 0; i < ARRAY_SIZE(blk->addr_map); i++) { if (blk->addr_map[i]) - print_spd_info((unsigned char *)blk->spd_array[i]); + print_spd_info((uint8_t *)blk->spd_array[i]); } } From 1463c5613984d1146a951c85e3ea3b419c09274b Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Thu, 16 Apr 2020 22:38:07 -0700 Subject: [PATCH 1212/1463] mb/google/volteer: implement mainboard_get_dram_part_num() Implements mainboard_get_dram_part_num() to override dram part number with a part number read from CBI. BUG=b:146464098 TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer, boot and log into kernel, execute "mosys memory spd print id" and verify that the memory part number from the cbi gets displayed properly. Change-Id: I3a20691f601cb513ee0936c8d141233c3d06db3d Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/40472 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/volteer/romstage.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 3e602e6139..d46b73181a 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -6,13 +6,15 @@ */ #include +#include +#include #include +#include #include #include #include #include -#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -27,3 +29,17 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); } + +bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + + if (google_chromeec_cbi_get_dram_part_num(part_num_store, + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); + return false; + } + *part_num = part_num_store; + *len = strlen(part_num_store); + return true; +} From c97bb64aadee241189f3c3ffae91115cbe33e58d Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 21 Apr 2020 12:51:37 -0700 Subject: [PATCH 1213/1463] mb/google/volteer: move mipi_camera.asl to variants folders Moves mipi_camera.asl from mb/google/volteer/acpi/ to mb/google/volteer/variant/baseboard/include/baseboard/acpi/. Adds mipi_camera.asl to variant/[volteer|ripto]/include/acpi/. Adds new VARIANT_HAS_MIPI_CAMERA Kconfig option. Adds VARIANT_HAS_MIPI_CAMERA for volteer and ripto variants. BUG=b:154648941, b:154646959 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Ripto and Volteer to kernel. Change-Id: I2f28243dfb945857d26f27f07968a15a3eeb7a4f Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/40578 Reviewed-by: William Wei Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 4 ++++ src/mainboard/google/volteer/Kconfig.name | 2 ++ src/mainboard/google/volteer/dsdt.asl | 5 ++++- .../baseboard/include/baseboard}/acpi/mipi_camera.asl | 0 .../variants/ripto/include/variant/acpi/mipi_camera.asl | 4 ++++ .../variants/volteer/include/variant/acpi/mipi_camera.asl | 4 ++++ 6 files changed, 18 insertions(+), 1 deletion(-) rename src/mainboard/google/volteer/{ => variants/baseboard/include/baseboard}/acpi/mipi_camera.asl (100%) create mode 100644 src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl create mode 100644 src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 04b2bb0f30..641ece1253 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -76,4 +76,8 @@ config VARIANT_DIR default "ripto" if BOARD_GOOGLE_RIPTO default "volteer" if BOARD_GOOGLE_VOLTEER +config VARIANT_HAS_MIPI_CAMERA + bool + default n + endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 62aabb1858..f7d0909583 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -11,7 +11,9 @@ config BOARD_GOOGLE_MALEFOR config BOARD_GOOGLE_RIPTO bool "-> Ripto" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 640f7cd7fe..af881ae859 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,7 +47,10 @@ DefinitionBlock( } #include + +#if CONFIG(VARIANT_HAS_MIPI_CAMERA) /* Camera */ #include - #include "acpi/mipi_camera.asl" + #include +#endif /* VARIANT_HAS_MIPI_CAMERA */ } diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl similarity index 100% rename from src/mainboard/google/volteer/acpi/mipi_camera.asl rename to src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000000..6df508198f --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000000..6df508198f --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include From a57240687f56dcadecc318bba3e89ab8108596bc Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 21 Jan 2020 20:57:44 -0700 Subject: [PATCH 1214/1463] vc/amd/fsp/picasso: Update UPD files to version 0.0.1-r38 Include a more recent set of files from a current FSP build. These are automatically generated. BUG=b:153675909 TEST=Trembyle builds and boots to payload Signed-off-by: Marshall Dawson Change-Id: I6428f618afc2a1cf1c35e93e00f905f90b2cd86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38696 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/vendorcode/amd/fsp/picasso/FspmUpd.h | 42 ++++++++++++++++++++- src/vendorcode/amd/fsp/picasso/FspsUpd.h | 48 ++++++++++++++++-------- 2 files changed, 73 insertions(+), 17 deletions(-) diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index aa85adc766..a2da917e08 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -21,7 +21,47 @@ typedef struct { /** Offset 0x004C**/ uint32_t serial_port_stride; /** Offset 0x0050**/ uint32_t serial_port_baudrate; /** Offset 0x0054**/ uint32_t serial_port_refclk; - /** Offset 0x0058**/ uint8_t UnusedUpdSpace0[168]; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5; + /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope; + /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; + /** Offset 0x0078**/ uint8_t aa_mode_en; + /** Offset 0x0079**/ uint8_t unused2; + /** Offset 0x007A**/ uint8_t unused3; + /** Offset 0x007B**/ uint8_t unused4; + /** Offset 0x007C**/ uint32_t fast_ppt_limit; + /** Offset 0x0080**/ uint32_t slow_ppt_limit; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant; + /** Offset 0x0088**/ uint32_t psi0_current_limit; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit; + /** Offset 0x0090**/ uint32_t thermctl_limit; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit; + /** Offset 0x009C**/ uint32_t sustained_power_limit; + /** Offset 0x00A0**/ uint32_t stapm_time_constant; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time; + /** Offset 0x00A8**/ uint32_t vrm_current_limit; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin; + /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; + /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; + /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; + /** Offset 0x00C1**/ uint8_t system_config; + /** Offset 0x00C2**/ uint8_t core_dldo_bypass; + /** Offset 0x00C3**/ uint8_t min_soc_vid_offset; + /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; + /** Offset 0x00C5**/ uint8_t unused5; + /** Offset 0x00C6**/ uint8_t unused6; + /** Offset 0x00C7**/ uint8_t unused7; + /** Offset 0x00C8**/ uint32_t tseg_size; + /** Offset 0x00CC**/ uint8_t pspp_policy; + /** Offset 0x00CD**/ uint8_t audio_soundwire; + /** Offset 0x00CE**/ uint8_t UnusedUpdSpace0[50]; /** Offset 0x0100**/ uint16_t Reserved100; /** Offset 0x0102**/ uint16_t UpdTerminator; } FSP_M_CONFIG; diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 5a154358d9..66ea60bb7b 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -13,22 +13,38 @@ typedef struct { - /** Offset 0x0020**/ uint32_t pcie_port0_topology; - /** Offset 0x0024**/ uint32_t pcie_port1_topology; - /** Offset 0x0028**/ uint32_t pcie_port2_topology; - /** Offset 0x002C**/ uint32_t pcie_port3_topology; - /** Offset 0x0030**/ uint32_t pcie_port4_topology; - /** Offset 0x0034**/ uint32_t pcie_port5_topology; - /** Offset 0x0038**/ uint32_t pcie_port6_topology; - /** Offset 0x003C**/ uint32_t pcie_sata_topology; - /** Offset 0x0040**/ uint32_t pcie_xgbe1_topology; - /** Offset 0x0044**/ uint32_t pcie_xgbe2_topology; - /** Offset 0x0048**/ uint32_t dp0_connector_type; - /** Offset 0x004C**/ uint32_t dp1_connector_type; - /** Offset 0x0050**/ uint32_t dp2_connector_type; - /** Offset 0x0054**/ uint32_t dp3_connector_type; - /** Offset 0x0058**/ uint32_t emmc0_mode; - /** Offset 0x005C**/ uint8_t UnusedUpdSpace0[196]; + /** Offset 0x0020**/ uint32_t emmc0_mode; + /** Offset 0x0024**/ uint8_t unused0[12]; + /** Offset 0x0030**/ uint8_t dxio_descriptor0[16]; + /** Offset 0x0040**/ uint8_t dxio_descriptor1[16]; + /** Offset 0x0050**/ uint8_t dxio_descriptor2[16]; + /** Offset 0x0060**/ uint8_t dxio_descriptor3[16]; + /** Offset 0x0070**/ uint8_t dxio_descriptor4[16]; + /** Offset 0x0080**/ uint8_t dxio_descriptor5[16]; + /** Offset 0x0090**/ uint32_t ddi_descriptor0; + /** Offset 0x0094**/ uint32_t ddi_descriptor1; + /** Offset 0x0098**/ uint32_t ddi_descriptor2; + /** Offset 0x009C**/ uint32_t ddi_descriptor3; + /** Offset 0x00A0**/ uint32_t unused1; + /** Offset 0x00A4**/ uint32_t unused2; + /** Offset 0x00A8**/ uint32_t unused3; + /** Offset 0x00AC**/ uint32_t unused4; + /** Offset 0x00B0**/ uint8_t fch_usb_version_major; + /** Offset 0x00B1**/ uint8_t fch_usb_version_minor; + /** Offset 0x00B2**/ uint8_t fch_usb_2_port0_phy_tune[9]; + /** Offset 0x00BB**/ uint8_t fch_usb_2_port1_phy_tune[9]; + /** Offset 0x00C4**/ uint8_t fch_usb_2_port2_phy_tune[9]; + /** Offset 0x00CD**/ uint8_t fch_usb_2_port3_phy_tune[9]; + /** Offset 0x00D6**/ uint8_t fch_usb_2_port4_phy_tune[9]; + /** Offset 0x00DF**/ uint8_t fch_usb_2_port5_phy_tune[9]; + /** Offset 0x00E8**/ uint8_t fch_usb_device_removable; + /** Offset 0x00E9**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x00EA**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x00EB**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x00EC**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x00ED**/ uint8_t unused8; + /** Offset 0x00EE**/ uint32_t xhci_oc_pin_select; + /** Offset 0x00F2**/ uint8_t UnusedUpdSpace0[46]; /** Offset 0x0120**/ uint16_t UpdTerminator; } FSP_S_CONFIG; From 8df012775dba24cd8a443bfc422aeddff8387860 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 21 Jan 2020 22:06:57 -0700 Subject: [PATCH 1215/1463] soc/amd/picasso: Add UPD settings to chip.h Add values that align with UPD settings. BUG=b:153675909 TEST=Trembyle builds and boots to payload Signed-off-by: Marshall Dawson Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38699 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/chip.h | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9c756ed616..4cc10ef945 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -31,6 +31,45 @@ struct soc_amd_picasso_config { I2S_PINS_I2S_TDM = 4, I2S_PINS_UNCONF = 7, /* All pads will be input mode */ } acp_pin_cfg; + + /* Options for these are in src/arch/x86/include/arch/acpi.h */ + uint8_t fadt_pm_profile; + uint16_t fadt_boot_arch; + uint32_t fadt_flags; + + /* System config index */ + uint8_t system_config; + + /* STAPM Configuration */ + uint32_t fast_ppt_limit; + uint32_t slow_ppt_limit; + uint32_t slow_ppt_time_constant; + uint32_t stapm_time_constant; + uint32_t sustained_power_limit; + + /* PROCHOT_L de-assertion Ramp Time */ + uint32_t prochot_l_deassertion_ramp_time; + + /* Lower die temperature limit */ + uint32_t thermctl_limit; + + /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */ + uint32_t psi0_current_limit; + uint32_t psi0_soc_current_limit; + uint32_t vddcr_soc_voltage_margin; + uint32_t vddcr_vdd_voltage_margin; + + /* VRM Limits. 0 indicates use SOC default */ + uint32_t vrm_maximum_current_limit; + uint32_t vrm_soc_maximum_current_limit; + uint32_t vrm_current_limit; + uint32_t vrm_soc_current_limit; + + /* Misc SMU settings */ + uint8_t sb_tsi_alert_comparator_mode_en; + uint8_t core_dldo_bypass; + uint8_t min_soc_vid_offset; + uint8_t aclk_dpm0_freq_400MHz; }; typedef struct soc_amd_picasso_config config_t; From 80b464af1830711cf97f16c504517518d0dcbdde Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 15:26:29 -0700 Subject: [PATCH 1216/1463] soc/amd/common/block/sata: Fix the condition to include sata.c sata.c was being added to ramstage based on the selection of CONFIG_SOC_AMD_COMMON_BLOCK_HDA which is not correct. This change fixes the error by including sata.c based on selection of CONFIG_SOC_AMD_COMMON_BLOCK_SATA. BUG=b:153858769 Change-Id: I5d23e5817872ddbb3d8d4f7dcabbaafcee4d51f4 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40766 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/sata/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/sata/Makefile.inc b/src/soc/amd/common/block/sata/Makefile.inc index 59b99eb9b4..3ca2a890e2 100644 --- a/src/soc/amd/common/block/sata/Makefile.inc +++ b/src/soc/amd/common/block/sata/Makefile.inc @@ -1 +1 @@ -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_HDA) += sata.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SATA) += sata.c From d7d22a4a530695cda9343cf0b6708e41fc1a6db6 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 15:30:04 -0700 Subject: [PATCH 1217/1463] soc/amd/common/block/sata: Use tabs instead of spaces in sata.c This is a cosmetic change to use tabs to align sata_ops and sata0_driver entries. Change-Id: Ia9eabd0cd64ecc9cbff0d4c3e3c6b71bbf29e3a9 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40767 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/sata/sata.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 3137672bf6..e95587eafc 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -9,10 +9,10 @@ void __weak soc_enable_sata_features(struct device *dev) { } static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = soc_enable_sata_features, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = soc_enable_sata_features, }; static const unsigned short pci_device_ids[] = { @@ -22,7 +22,7 @@ static const unsigned short pci_device_ids[] = { }; static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, }; From 69c0469bb94662f0fff523fe6eeb84911b397a47 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 15:34:47 -0700 Subject: [PATCH 1218/1463] soc/amd/sata: Add .acpi_name() callback to SATA driver This change adds .acpi_name() callback to SATA driver that returns "STCR" as the ACPI device name for SATA. Since this is now done by the common SATA driver, this change also removes the SATA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I5e0998be3016febbb3b0e91940750a38edb6a9e7 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40768 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/sata/sata.c | 6 ++++++ src/soc/amd/stoneyridge/chip.c | 2 -- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index e95587eafc..f9b6549494 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -8,11 +8,17 @@ void __weak soc_enable_sata_features(struct device *dev) { } +static const char *sata_acpi_name(const struct device *dev) +{ + return "STCR"; +} + static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = soc_enable_sata_features, + .acpi_name = sata_acpi_name, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 189f48e8e9..b063c7287f 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -87,8 +87,6 @@ const char *soc_acpi_name(const struct device *dev) return "EHC0"; case LPC_DEVFN: return "LPCB"; - case SATA_DEVFN: - return "STCR"; case SD_DEVFN: return "SDCN"; case SMBUS_DEVFN: From 088b9e337cfa0bce05ddbdbc643c29676e842f8f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 15:41:35 -0700 Subject: [PATCH 1219/1463] soc/amd/sata: Move SATA PCI device from DSDT to SSDT This change adds support in common block SATA driver to add a PCI device for SATA in SSDT and removes the SATA device from DSDT. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I16ac36d997496ff33c5b44ec9bd2731b2b8799eb Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40769 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/sata/sata.c | 2 ++ src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index f9b6549494..2dd0d425a1 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -19,6 +20,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = soc_enable_sata_features, .acpi_name = sata_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 8cf8da4e24..cfd2f1df7b 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -23,11 +23,6 @@ Method(_OSC,4) /* Describe the Southbridge devices */ -/* 0:11.0 - SATA */ -Device(STCR) { - Name(_ADR, 0x00110000) -} /* end STCR */ - /* 0:14.0 - SMBUS */ Device(SBUS) { Name(_ADR, 0x00140000) From 52f8926159917d87cc33c33183225be7eb470e0d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 15:45:20 -0700 Subject: [PATCH 1220/1463] soc/amd/picasso: Use AMD common SATA driver This change enables the use of AMD common block SATA driver for Picasso. Since the common driver provides ACPI device name and PCI device for SATA in SSDT, these are removed from picasso chip.c and sb_pci0_fch.asl. BUG=b:153858769 TEST=Verified that "STCR" device is correctly reported on trembyle in SSDT. Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/sata/sata.c | 4 ++++ src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 5 ----- src/soc/amd/picasso/chip.c | 2 -- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 2dd0d425a1..4db00b1d6e 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -26,6 +26,10 @@ static struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1, 0 }; diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 3e6029e0e0..04e72c0a45 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -23,11 +23,6 @@ Method(_OSC,4) /* Describe the Southbridge devices */ -/* 0:11.0 - SATA */ -Device(STCR) { - Name(_ADR, 0x00110000) -} /* end STCR */ - /* 0:14.0 - SMBUS */ Device(SBUS) { Name(_ADR, 0x00140000) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 4b25b888d6..201afb40dd 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -65,8 +65,6 @@ const char *soc_acpi_name(const struct device *dev) return "AZHD"; case LPC_DEVFN: return "LPCB"; - case SATA_DEVFN: - return "STCR"; case SMBUS_DEVFN: return "SBUS"; case XHCI0_DEVFN: From 64f477b401ecc885ba678c77d01757118c84bd55 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 17:57:03 -0700 Subject: [PATCH 1221/1463] soc/amd/common/block/sata: Add missing .ops_pci member This change sets .ops_pci for sata device_operations to default pci_dev_ops_pci. It is required to set the subsystem IDs making the behavior consistent with default_pci_ops_dev. BUG=b:153858769 Change-Id: I695ac8961c92a3061beca890f5d47413b251e22b Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40777 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/sata/sata.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 4db00b1d6e..1959d3d860 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -19,6 +19,7 @@ static struct device_operations sata_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = soc_enable_sata_features, + .ops_pci = &pci_dev_ops_pci, .acpi_name = sata_acpi_name, .acpi_fill_ssdt = acpi_device_write_pci_dev, }; From f98bbda5fb145287c75e944b7c8d91e7c57a672e Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Tue, 7 Apr 2020 16:16:38 -0700 Subject: [PATCH 1222/1463] soc/intel/common: Add method to modify GPIO community PM config This patch adds CGPM, a helper method to configure GPIO power management bits that are part of miscellaneous config. This is needed for configuration of these bits on S0ix entry and exit. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260 Reviewed-by: Venkata Krishna Nimmagadda Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/common/acpi/gpio.asl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 src/soc/intel/common/acpi/gpio.asl diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl new file mode 100644 index 0000000000..364ac73843 --- /dev/null +++ b/src/soc/intel/common/acpi/gpio.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * Configure GPIO Power Management bits + * + * Arg0: GPIO community (0-5) + * Arg1: PM bits in MISCCFG + */ +Method (CGPM, 2, Serialized) +{ + Local0 = GPID (Arg0) + If (Local0 != 0) { + /* Mask off current PM bits */ + PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG) + /* Mask in requested bits */ + PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG) + } +} From cd41fa378d03eb2509d5757c441f242bc3f98a6f Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Fri, 17 Apr 2020 00:21:22 -0700 Subject: [PATCH 1223/1463] soc/intel/tigerlake: Add method to look up GPIO com ID for an index This patch adds GPID, a helper method to look up GPIO community ID for an index. This patch also includes Intel's common GPIO ASL code. CGPM method in the common code uses the GPID method introduced in this patch. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478 Reviewed-by: Venkata Krishna Nimmagadda Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi/gpio.asl | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index 2b4aff09c0..9b8a175659 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -4,6 +4,7 @@ #include #include #include +#include #include "gpio_op.asl" Device (GCM0) @@ -142,3 +143,35 @@ Method (GADD, 1, NotSerialized) Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) Return (Local2) } + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (0) { + Local0 = PID_GPIOCOM0 + } + Case (1) { + Local0 = PID_GPIOCOM1 + } + Case (2) { + Local0 = PID_GPIOCOM2 + } + Case (4) { + Local0 = PID_GPIOCOM4 + } + Case (5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} From eb148d88d1af5b4fb409794e974f89cf2705741a Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Tue, 7 Apr 2020 16:33:33 -0700 Subject: [PATCH 1224/1463] mb/google/volteer: Work around TPM issue by enabling GPIO PM in S0ix Setting the default values for GPIO community power management, causes issues in detecting TPM interrupts. So to avoid that GPIO PM has to be disabled in devicetree. But for S0ix it is needed. This patch implements a workaround in ASL code to enable GPIO PM on S0ix entry and disable it on S0ix exit. This patch adds the following three platform specific methods. 1. MS0X to enable power management features for GPIO communities on entry and on exit, it disables them. 2. MPTS to enable power management features for GPIO communities when preparing to sleep. 3. MWAK to disable power management features for GPIO communities on waking up. BUG=b:148892882 BRANCH=none TEST="Boot with this change on volteer proto1 and check for GPIO community config with debugger" Signed-off-by: Venkata Krishna Nimmagadda Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40261 Reviewed-by: Nick Vaccaro Reviewed-by: Venkata Krishna Nimmagadda Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/dsdt.asl | 6 +++ src/mainboard/google/volteer/mainboard.asl | 48 ++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 src/mainboard/google/volteer/mainboard.asl diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index af881ae859..450835db03 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -32,11 +32,17 @@ DefinitionBlock( #include #include } + /* Mainboard hooks */ + #include "mainboard.asl" } // Chrome OS specific #include + /* Include Low power idle table for a short term workaround to enable + S0ix. Once cr50 pulse width is fixed, this can be removed. */ + #include + // Chrome OS Embedded Controller Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl new file mode 100644 index 0000000000..d58822d719 --- /dev/null +++ b/src/mainboard/google/volteer/mainboard.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.LPID._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) + } Else { + /* S0ix Exit */ + PGPM (0) + } +} From fa52f31e114d7d15b49dca448832138c884138cd Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 24 Apr 2020 13:57:26 -0600 Subject: [PATCH 1225/1463] cpu/x86/16bit/entry16.inc: Fix typos in comment Signed-off-by: Raul E Rangel Change-Id: I89d4d9d3a4a8a7545921dabb50f33035a090ecda Reviewed-on: https://review.coreboot.org/c/coreboot/+/40696 Reviewed-by: Aaron Durbin Reviewed-by: Marshall Dawson Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/x86/16bit/entry16.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index f7fd416d42..c71acb0bff 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -71,13 +71,13 @@ _start16bit: * * One way to work around this is to have the linker do the * math instead of the assembler. This solves the very - * pratical problem of being able to write code that can + * practical problem of being able to write code that can * be relocated. * * An lgdt call before we have memory enabled cannot be * position independent, as we cannot execute a call * instruction to get our current instruction pointer. - * So while this code is relocateable it isn't arbitrarily + * So while this code is relocatable it isn't arbitrarily * relocatable. * * The criteria for relocation have been relaxed to their From 3ae3ff28286f1e752f01ccf9480414ff1d82615f Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 27 Apr 2020 15:47:18 -0600 Subject: [PATCH 1226/1463] src/cpu/x86/mtrr/earlymtrr: Add clear_all_var_mtrr Picasso does not define the state of variable MTRRs on boot. Add a helper function to clear all MTRRs. BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel Change-Id: I21b887ce12849a95ddd8f1698028fb6bbfb4a7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40764 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/cpu/x86/mtrr/earlymtrr.c | 14 ++++++++++++++ src/include/cpu/x86/mtrr.h | 1 + 2 files changed, 15 insertions(+) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 4d14a8de08..e4003591f9 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -42,3 +42,17 @@ void set_var_mtrr( maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); } + +void clear_all_var_mtrr(void) +{ + msr_t mtrr = {0, 0}; + int vcnt; + int i; + + vcnt = get_var_mtrr_count(); + + for (i = 0; i < vcnt; i++) { + wrmsr(MTRR_PHYS_MASK(i), mtrr); + wrmsr(MTRR_PHYS_BASE(i), mtrr); + } +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 07db3cb606..50148ffd35 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -107,6 +107,7 @@ static inline int get_var_mtrr_count(void) void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, unsigned int type); int get_free_var_mtrr(void); +void clear_all_var_mtrr(void); asmlinkage void display_mtrrs(void); From ca928c6768ba143f619a99cca44f9f8153511270 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 4 Apr 2020 01:47:37 +0200 Subject: [PATCH 1227/1463] arch/x86: Implement RESET_VECTOR_IN_RAM Add support for devices with the reset vector pointing into DRAM. This is a specific implementation that assumes a paradigm of AMD Family 17h (a.k.a. "Zen"). Until the first ljmpl for protected mode, the core's state appears to software like other designs, and then the actual physical addressing becomes recognizable. These systems cannot implement cache-as-RAM as in more traditional x86 products. Therefore instead of reusing CAR names and variables, a substitute called "earlyram" is introduced. This change makes adjustments to CAR-aware files accordingly. Enable NO_XIP_EARLY_STAGES. The first stage is already in DRAM, and running subsequent stages as XIP in the boot device would reduce performance. Finally, add a new early_ram.ld linker file. Because all stages run in DRAM, they can be linked with their .data and .bss as normal, i.e. they don't need to rely on storage available only at a fixed location like CAR systems. The primary purpose of the early_ram.ld is to provide consistent locations for PRERAM_CBMEM_CONSOLE, TIMESTAMP regions, etc. across stages until cbmem is brought online. BUG=b:147042464 TEST=Build for trembyle, and boot to ramstage. $ objdump -h cbfs/fallback/bootblock.debug Idx ,Name ,Size ,VMA ,LMA ,File off Algn 0 ,.text ,000074d0 ,08076000 ,08076000 ,00001000 2**12 1 ,.data ,00000038 ,0807d4d0 ,0807d4d0 ,000084d0 2**2 2 ,.bss ,00000048 ,0807d508 ,0807d508 ,00008508 2**2 3 ,.stack ,00000800 ,0807daf0 ,0807daf0 ,00000000 2**0 4 ,.persistent ,00001cfa ,0807e2f0 ,0807e2f0 ,00000000 2**0 5 ,.reset ,00000010 ,0807fff0 ,0807fff0 ,0000aff0 2**0 6 ,.debug_info ,0002659c ,00000000 ,00000000 ,0000b000 2**0 7 ,.debug_abbrev ,000074a2 ,00000000 ,00000000 ,0003159c 2**0 8 ,.debug_aranges,00000dd0 ,00000000 ,00000000 ,00038a40 2**3 9 ,.debug_line ,0000ad65 ,00000000 ,00000000 ,00039810 2**0 10 ,.debug_str ,00009655 ,00000000 ,00000000 ,00044575 2**0 11 ,.debug_loc ,0000b7ce ,00000000 ,00000000 ,0004dbca 2**0 12 ,.debug_ranges ,000029c0 ,00000000 ,00000000 ,00059398 2**3 Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/35035 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 6 ++-- src/arch/x86/assembly_entry.S | 11 +++++-- src/arch/x86/early_ram.ld | 43 +++++++++++++++++++++++++++ src/arch/x86/include/arch/memlayout.h | 3 ++ src/arch/x86/memlayout.ld | 4 ++- src/cpu/Kconfig | 4 +++ src/include/memlayout.h | 3 ++ 7 files changed, 69 insertions(+), 5 deletions(-) create mode 100644 src/arch/x86/early_ram.ld diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 21107aa48b..11733bd05e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -89,9 +89,10 @@ config X86_RESET_VECTOR config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 + select NO_XIP_EARLY_STAGES help - Select this option if the x86 soc implements custom code to handle the - reset vector in RAM instead of the traditional 0xfffffff0 location. + Select this option if the x86 processor's reset vector is in + preinitialized DRAM instead of the traditional 0xfffffff0 location. # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. @@ -206,6 +207,7 @@ config VERSTAGE_ADDR config POSTCAR_STAGE def_bool y depends on ARCH_X86 + depends on !RESET_VECTOR_IN_RAM config VERSTAGE_DEBUG_SPINLOOP bool diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index f36e7dab4d..59b34c8713 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -9,6 +9,13 @@ * continue with C code execution one needs to set stack pointer and * clear .bss variables that are stage specific. */ + +#if CONFIG(RESET_VECTOR_IN_RAM) + #define _STACK_TOP _eearlyram_stack +#else + #define _STACK_TOP _ecar_stack +#endif + .section ".text._start", "ax", @progbits .global _start _start: @@ -16,8 +23,8 @@ _start: /* Migrate GDT to this text segment */ call gdt_init - /* reset stack pointer to CAR stack */ - mov $_ecar_stack, %esp + /* reset stack pointer to CAR/EARLYRAM stack */ + mov $_STACK_TOP, %esp /* clear .bss section as it is not shared */ cld diff --git a/src/arch/x86/early_ram.ld b/src/arch/x86/early_ram.ld new file mode 100644 index 0000000000..941c385b04 --- /dev/null +++ b/src/arch/x86/early_ram.ld @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* This file is included inside a SECTIONS block */ + +_STACK_SIZE = CONFIG_EARLYRAM_BSP_STACK_SIZE; +_ = ASSERT(_STACK_SIZE > 0x0, "EARLYRAM_BSP_STACK_SIZE is not configured"); + +_CONSOLE_SIZE = CONFIG_PRERAM_CBMEM_CONSOLE_SIZE; +_ = ASSERT(_CONSOLE_SIZE > 0x0, "PRERAM_CBMEM_CONSOLE_SIZE is not configured"); + +_TIMESTAMPS_SIZE = 0x200; +#if !CONFIG(NO_FMAP_CACHE) +_FMAP_SIZE = FMAP_SIZE; +#else +_FMAP_SIZE = 0; +#endif + +/* + * The PRERAM_CBMEM_CONSOLE, TIMESTAMP, and FMAP_CACHE regions are shared + * between the pre-ram stages (bootblock, romstage, etc). We need to assign a + * fixed size and consistent link address so they can be shared between stages. + * + * The stack area is not shared between stages, but is defined here for + * convenience. + */ +. = CONFIG_X86_RESET_VECTOR - ARCH_STACK_ALIGN_SIZE - _STACK_SIZE - _CONSOLE_SIZE - _TIMESTAMPS_SIZE - _FMAP_SIZE; + +_ = ASSERT(. > _eprogram, "Not enough room for .earlyram.data. Try increasing C_ENV_BOOTBLOCK_SIZE, or decreasing either EARLYRAM_BSP_STACK_SIZE or PRERAM_CBMEM_CONSOLE_SIZE."); + +.stack ALIGN(ARCH_STACK_ALIGN_SIZE) (NOLOAD) : { + EARLYRAM_STACK(., _STACK_SIZE) +} + +.persistent ALIGN(ARCH_POINTER_ALIGN_SIZE) (NOLOAD) : { + PRERAM_CBMEM_CONSOLE(., _CONSOLE_SIZE) + TIMESTAMP(., _TIMESTAMPS_SIZE) + #if !CONFIG(NO_FMAP_CACHE) + FMAP_CACHE(., FMAP_SIZE) + #endif +} + +_ = ASSERT(. <= CONFIG_X86_RESET_VECTOR, "Earlyram data regions don't fit below the reset vector!"); diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 2eea83faaf..34d1bd2567 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -8,4 +8,7 @@ # error "CONFIG_RAMTOP not configured" #endif +/* Intel386 psABI requires a 16 byte aligned stack. */ +#define ARCH_STACK_ALIGN_SIZE 16 + #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 5e1ef24655..31767b3c31 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -9,7 +9,7 @@ #if ENV_CACHE_AS_RAM #define EARLY_MEMLAYOUT "car.ld" #else -#error "Early DRAM environment for x86 is work-in-progress. */ +#define EARLY_MEMLAYOUT "early_ram.ld" #endif #endif @@ -53,7 +53,9 @@ SECTIONS /* Bootblock specific scripts which provide more SECTION directives. */ #include #include +#if !CONFIG(RESET_VECTOR_IN_RAM) #include +#endif #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include #endif diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c1b84f9d44..933e50f227 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -15,6 +15,10 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex +config EARLYRAM_BSP_STACK_SIZE + depends on RESET_VECTOR_IN_RAM + hex + config SMP bool default y if MAX_CPUS != 1 diff --git a/src/include/memlayout.h b/src/include/memlayout.h index bef3637d1e..af277eaf20 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -58,6 +58,9 @@ #define PRERAM_CBMEM_CONSOLE(addr, size) \ REGION(preram_cbmem_console, addr, size, 4) +#define EARLYRAM_STACK(addr, size) \ + REGION(earlyram_stack, addr, size, ARCH_STACK_ALIGN_SIZE) + /* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */ #define CBFS_CACHE(addr, size) \ REGION(cbfs_cache, addr, size, 4) \ From 466732262817aadb1d9464883912112fd5d03fba Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 4 Apr 2020 02:37:04 +0200 Subject: [PATCH 1228/1463] soc/amd/picasso: Add bootblock support The original plan for Picasso was to combine the features of bootblock with romstage due to its unique way of coming out of reset. Early in development, all bootblock support was removed from the directory. All Picasso designs will now use a bootblock as their first stage. The reason being that it requires less invasive changes than using a hybrid romstage. Add a basic bootblock back to the directory, and compatible with the design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM and add appropriate settings in Kconfig. Make Makefile.inc calculates the size and base of bootblock from known parameters. * Future work may attempt to streamline this further, in conjunction with changes in amdfwtool. See b/154957411. BUG=b:147042464, b:153675909 Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c Signed-off-by: Marshall Dawson Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 13 ++++++--- src/soc/amd/picasso/Makefile.inc | 28 +++++++++++------- src/soc/amd/picasso/bootblock/bootblock.c | 31 ++++++++++++++++++++ src/soc/amd/picasso/bootblock/pre_c.S | 35 +++++++++++++++++++++++ 4 files changed, 92 insertions(+), 15 deletions(-) create mode 100644 src/soc/amd/picasso/bootblock/bootblock.c create mode 100644 src/soc/amd/picasso/bootblock/pre_c.S diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3113b27783..afa18bc64c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES @@ -46,10 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select RTC -config HAVE_BOOTBLOCK - bool - default n - config AMD_FP5 def_bool y if !AMD_FT5 help @@ -219,6 +216,14 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. +config X86_RESET_VECTOR + hex + default 0x807fff0 + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x800 + menu "PSP Configuration Options" config AMDFW_OUTSIDE_CBFS diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d31e518edc..b04e1e9217 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,6 +11,15 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm +bootblock-y += bootblock/pre_c.S +bootblock-y += bootblock/bootblock.c +bootblock-y += southbridge.c +bootblock-y += i2c.c +bootblock-$(CONFIG_PICASSO_UART) += uart.c +bootblock-y += tsc_freq.c +bootblock-y += gpio.c +bootblock-y += smi_util.c + romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c @@ -29,12 +38,6 @@ verstage-y += pmutil.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c -postcar-y += monotonic_timer.c -postcar-$(CONFIG_PICASSO_UART) += uart.c -postcar-y += memmap.c -postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c -postcar-y += tsc_freq.c - ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c @@ -179,8 +182,12 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR) -PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE) +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +# TODO(b/154957411): Refactor amdfwtool to extract the address and size from +# the elf file. +PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE) +# This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld. +PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE))) # type = 0x63 ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) @@ -368,11 +375,10 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ -USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf -$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS) +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \ + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ --maxsize $(PSP_BIOSBIN_SIZE) ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c new file mode 100644 index 0000000000..8ae4db3178 --- /dev/null +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + enable_pci_mmconf(); + + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + sb_reset_i2c_slaves(); + fch_pre_init(); +} + +void bootblock_soc_init(void) +{ + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + fch_early_init(); + i2c_soc_early_init(); +} diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S new file mode 100644 index 0000000000..c478ef80bb --- /dev/null +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */ + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + post_code(0xa0) + + movl $_eearlyram_stack, %esp + + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $8, %esp + + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ + + post_code(0xa2) + + call bootblock_c_entry + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever From 10757897c0714d3c7c1f4b5d67b64a7e92a5cc9e Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 29 Apr 2020 14:05:52 +1000 Subject: [PATCH 1229/1463] mb/google/hatch/romstage_spd_smbus.c: Fix missing DIMM issue Since `commit 0ee9b14c09c` the SPD array is set to NULL if no DIMM is present. This causes failure due to an unconditional use of `blk.spd_array[i]`, : i={0,1}. This validates the spd_array is non-NULL before use otherwise it sets the DIMM as not present. Puff fails boot with the following log: ``` ... SPD: banks 16, ranks 2, rows 16, columns 10, density 8192 Mb SPD: device width 8 bits, bus width 64 bits SPD: module size is 16384 MB (per channel) ASSERTION ERROR: file 'src/soc/intel/cannonlake/cnl_memcfg_init.c', line 47 ``` BUG=b:155220125 BRANCH=none TEST=none Change-Id: I5f47c849344951d53fa8c67e779b7c46d632d124 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40820 Reviewed-by: Jamie Chen Reviewed-by: Sam McNally Reviewed-by: Furquan Shaikh Reviewed-by: Daniel Kurtz Tested-by: build bot (Jenkins) --- .../google/hatch/romstage_spd_smbus.c | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 4aa37fa6a4..bac5d588ea 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -18,15 +18,24 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* Access memory info through SMBUS. */ get_spd_smbus(&blk); - memcfg.spd[0].read_type = READ_SPD_MEMPTR; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; + + if (blk.spd_array[0] == NULL) { + memcfg.spd[0].read_type = NOT_EXISTING; + } else { + memcfg.spd[0].read_type = READ_SPD_MEMPTR; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; + } memcfg.spd[1].read_type = NOT_EXISTING; - memcfg.spd[2].read_type = READ_SPD_MEMPTR; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; + if (blk.spd_array[1] == NULL) { + memcfg.spd[2].read_type = NOT_EXISTING; + } else { + memcfg.spd[2].read_type = READ_SPD_MEMPTR; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; + } memcfg.spd[3].read_type = NOT_EXISTING; dump_spd_info(&blk); From f9c4a8dd3f784e050520a78c9a2c49bfd802fa11 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 17:53:18 -0700 Subject: [PATCH 1230/1463] soc/amd/common/block/hda: Drop PCI_DEVICE_ID_AMD_FAM17H_HDA0 PCI device PCI_DEVICE_ID_AMD_FAM17H_HDA0 does not really use the same vendor ID as PCI_VENDOR_ID_AMD. Thus, drop this device from the list of pci_device_ids[] that are supported by the common hda driver. BUG=b:153858769 Change-Id: If41dc7179e1e5b476878ee24c8a355b1cde762eb Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40778 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/hda/hda.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index e4f86df192..1f41478108 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -10,7 +10,6 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, PCI_DEVICE_ID_AMD_CZ_HDA, - PCI_DEVICE_ID_AMD_FAM17H_HDA0, PCI_DEVICE_ID_AMD_FAM17H_HDA1, 0 }; From f9e6d3e0508b1f9494e996b9aef4fd7fe23dcc05 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 17:59:25 -0700 Subject: [PATCH 1231/1463] soc/amd/common/block/hda: Use default pci_dev_ops_pci This change sets ops_pci for hda_audio_ops to default pci_dev_ops_pci and removes the custom lops_pci since the driver does not really need a custom ops_pci. BUG=b:153858769 Change-Id: I4b46e22ef556c0f49152c41a07f3c54c513ae37a Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40779 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/hda/hda.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 1f41478108..90e533918c 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -14,15 +14,11 @@ static const unsigned short pci_device_ids[] = { 0 }; -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver hdaaudio_driver __pci_driver = { From 45f06c56ca0ab071e2780c89e7011d2268f588c7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 18:02:21 -0700 Subject: [PATCH 1232/1463] soc/amd/common/block/hda: Use tabs instead of spaces in hda.c This is a cosmetic change to use tabs to align hda_audio_ops and hdaaudio_driver entries. Change-Id: I8e398706cbe7087d0178b2433606f8984651c0d6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40780 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/hda/hda.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 90e533918c..c53291d815 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -15,15 +15,15 @@ static const unsigned short pci_device_ids[] = { }; static struct device_operations hda_audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .ops_pci = &pci_dev_ops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = CONFIG(AZALIA_PLUGIN_SUPPORT) ? - &default_azalia_audio_ops : &hda_audio_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, + .ops = CONFIG(AZALIA_PLUGIN_SUPPORT) ? + &default_azalia_audio_ops : &hda_audio_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, }; From edfc5a9df5444cfa6746b0aa78361e4dfa1ed15b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 18:04:46 -0700 Subject: [PATCH 1233/1463] soc/amd/hda: Add .acpi_name() callback to HDA driver This change adds .acpi_name() callback to HDA driver that returns "AZHD" as the ACPI device name for HDA controller. Since this is now done by the common HDA driver, this change also removes the HDA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I89eaa799518572f3c46c7ce9ef8dd3f85daa12bb Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40781 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/hda/hda.c | 6 ++++++ src/soc/amd/stoneyridge/chip.c | 2 -- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index c53291d815..ea42b84216 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -14,11 +14,17 @@ static const unsigned short pci_device_ids[] = { 0 }; +static const char *hda_acpi_name(const struct device *dev) +{ + return "AZHD"; +} + static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, + .acpi_name = hda_acpi_name, }; static const struct pci_driver hdaaudio_driver __pci_driver = { diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index b063c7287f..3c32bf5183 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -81,8 +81,6 @@ const char *soc_acpi_name(const struct device *dev) return "PBR7"; case PCIE4_DEVFN: return "PBR8"; - case HDA1_DEVFN: - return "AZHD"; case EHCI1_DEVFN: return "EHC0"; case LPC_DEVFN: From f510c75d649ba7e4f8a441174b8d9c0b7e0c7c9b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 18:46:52 -0700 Subject: [PATCH 1234/1463] soc/amd/picasso: Drop _INI method and OperationRegion for AZHD device _INI method for AZHD device for Picasso family was just copied from Stoneyridge as part of initial change. There is no evidence that this is required for Picasso. Also, removing the _INI method works perfectly fine. Thus, this change drops the _INI method for AZHD device on Picasso. Since the _INI method was the only entity using the OperationRegion fields, this change also drops the operation region. BUG=b:155132752 TEST=Verified that audio still works on Trembyle Change-Id: If42abf91ee5cd47a881b0a3b4ca1916ea5169261 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40782 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/acpi/northbridge.asl | 33 ------------------------ 1 file changed, 33 deletions(-) diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 6b6bd7cd86..386556c9d0 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -79,37 +79,4 @@ Device(PBR8) { Device(AZHD) { /* 0:9.2 - HD Audio */ Name(_ADR, 0x00090002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6c), - MMDT, 16, - } - - Method (_INI, 0, NotSerialized) - { - If (LEqual (OSVR, 0x03)) - { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) - } - } } /* end AZHD */ From 2c213d35b0cdcc6def4431c736c5bc64abe160fb Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 23:06:30 -0700 Subject: [PATCH 1235/1463] arch/x86/acpigen: Add helpers for Store() and If (Lequal (...)) This change adds the following acpigen helpers: a. acpigen_write_store_op_to_namestr: This generates ACPI code for storing an ACPI OP to name string b. acpigen_write_if_lequal_namestr_int: This generates ACPI code for checking if operand1 and operand2 are equal where operand1 is namestring and operand2 is an integer. Change-Id: I84c158361c0725c2927f06be35391e61f627a453 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40783 Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/x86/acpigen.c | 22 ++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 715c38b598..82654e18dd 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1186,6 +1186,14 @@ void acpigen_write_store_ops(uint8_t src, uint8_t dst) acpigen_emit_byte(dst); } +/* Store (src, "namestr") */ +void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst) +{ + acpigen_write_store(); + acpigen_emit_byte(src); + acpigen_emit_namestring(dst); +} + /* Or (arg1, arg2, res) */ void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res) { @@ -1274,6 +1282,20 @@ void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val) acpigen_write_integer(val); } +/* + * Generates ACPI code for checking if operand1 and operand2 are equal, where, + * operand1 is namestring and operand2 is an integer. + * + * If (Lequal ("namestr", val)) + */ +void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val) +{ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring(namestr); + acpigen_write_integer(val); +} + void acpigen_write_else(void) { acpigen_emit_byte(ELSE_OP); diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 0eee7ffea7..3a74db11e9 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -351,6 +351,7 @@ void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, void acpigen_write_sleep(uint64_t sleep_ms); void acpigen_write_store(void); void acpigen_write_store_ops(uint8_t src, uint8_t dst); +void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); @@ -361,6 +362,7 @@ void acpigen_write_debug_op(uint8_t op); void acpigen_write_if(void); void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); +void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); void acpigen_write_else(void); void acpigen_write_to_buffer(uint8_t src, uint8_t dst); void acpigen_write_to_integer(uint8_t src, uint8_t dst); From f9392990d5f8d3c1b7d6f8531c62b5a6b2f3545c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 23:18:12 -0700 Subject: [PATCH 1236/1463] arch/x86/acpigen: Constify fieldlist parameter to acpigen_write_field acpigen_write_field() does not need to modify the fieldlist parameter. Thus, this change makes this parameter as const. Change-Id: I94688913cee8948f42ae5e184f2d24264876648d Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40784 Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/x86/acpigen.c | 2 +- src/arch/x86/include/arch/acpigen.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 82654e18dd..34de2bab18 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -514,7 +514,7 @@ static void acpigen_write_field_name(const char *name, uint32_t size) * PMCS, 2 * } */ -void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, +void acpigen_write_field(const char *name, const struct fieldlist *l, size_t count, uint8_t flags) { uint16_t i; diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 3a74db11e9..3339ce4d92 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -426,7 +426,7 @@ void acpigen_write_release(const char *name); * Generate ACPI AML code for Field * This function takes input region name, fieldlist, count & flags. */ -void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, +void acpigen_write_field(const char *name, const struct fieldlist *l, size_t count, uint8_t flags); /* * Generate ACPI AML code for IndexField From 91a7abf25c72145b974002ca295ce60b0a8f405c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 18:48:48 -0700 Subject: [PATCH 1237/1463] soc/amd/hda: Move HDA PCI device from DSDT to SSDT This change adds support in common block HDA driver to add a PCI device for HDA in SSDT and removes the HDA device from DSDT for Stoneyridge and Picasso. _INI method is still retained in stoneyridge since I am unsure why it was added. In order to support the _INI method, HDA driver makes a callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks required for the HDA device. This callback is implemented by Stoneyridge to provide the _INI method which retains the same functionality for HDA device. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769,b:155132752 TEST=Verified that audio still works fine on Trembyle. Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40785 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/amd/gardenia/acpi/gpe.asl | 2 + src/mainboard/amd/padmelon/acpi/gpe.asl | 2 + src/soc/amd/common/block/hda/hda.c | 13 +++++ .../amd/common/block/include/amdblocks/hda.h | 12 +++++ src/soc/amd/picasso/acpi/northbridge.asl | 4 -- src/soc/amd/stoneyridge/acpi/northbridge.asl | 37 ------------- src/soc/amd/stoneyridge/northbridge.c | 54 +++++++++++++++++++ 7 files changed, 83 insertions(+), 41 deletions(-) create mode 100644 src/soc/amd/common/block/include/amdblocks/hda.h diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl index a4aed9a7d9..7756729d3b 100644 --- a/src/mainboard/amd/gardenia/acpi/gpe.asl +++ b/src/mainboard/amd/gardenia/acpi/gpe.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +External (\_SB.PCI0.AZHD, DeviceObj) + Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl index 3fd653ed40..545ba14658 100644 --- a/src/mainboard/amd/padmelon/acpi/gpe.asl +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +External (\_SB.PCI0.AZHD, DeviceObj) + Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index ea42b84216..2028f09335 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include +#include #include #include #include @@ -19,12 +21,23 @@ static const char *hda_acpi_name(const struct device *dev) return "AZHD"; } +__weak void hda_soc_ssdt_quirks(const struct device *dev) +{ +} + +static void hda_fill_ssdt(const struct device *dev) +{ + acpi_device_write_pci_dev(dev); + hda_soc_ssdt_quirks(dev); +} + static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, .acpi_name = hda_acpi_name, + .acpi_fill_ssdt = hda_fill_ssdt, }; static const struct pci_driver hdaaudio_driver __pci_driver = { diff --git a/src/soc/amd/common/block/include/amdblocks/hda.h b/src/soc/amd/common/block/include/amdblocks/hda.h new file mode 100644 index 0000000000..b59a7b0e02 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/hda.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_HDA_H__ +#define __AMDBLOCKS_HDA_H__ + +#include + +/* SoC callback to add any quirks to HDA device node in SSDT. */ +void hda_soc_ssdt_quirks(const struct device *dev); + +#endif /* __AMDBLOCKS_HDA_H__ */ diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 386556c9d0..67ae6f2bbe 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -76,7 +76,3 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) -} /* end AZHD */ diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c8076015bb..91e43aa5d6 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -81,40 +81,3 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6c), - MMDT, 16, - } - - Method (_INI, 0, NotSerialized) - { - If (LEqual (OSVR, 0x03)) - { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) - } - } -} /* end AZHD */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index db715091cf..2aa16b6853 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include +#include #include #include #include @@ -501,3 +503,55 @@ void SetNbMidParams(GNB_MID_CONFIGURATION *params) params->iGpuVgaMode = 0; params->GnbIoapicAddress = IO_APIC2_ADDR; } + +void hda_soc_ssdt_quirks(const struct device *dev) +{ + const char *scope = acpi_device_path(dev); + static const struct fieldlist list[] = { + FIELDLIST_OFFSET(0x42), + FIELDLIST_NAMESTR("NSDI", 1), + FIELDLIST_NAMESTR("NSDO", 1), + FIELDLIST_NAMESTR("NSEN", 1), + }; + struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100); + + assert(scope); + + acpigen_write_scope(scope); + + /* + * OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + * Field (AZPD, AnyAcc, NoLock, Preserve) { + * Offset (0x42), + * NSDI, 1, + * NSDO, 1, + * NSEN, 1, + * } + */ + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* + * Method (_INI, 0, NotSerialized) { + * If (LEqual (OSVR, 0x03)) { + * Store (Zero, NSEN) + * Store (One, NSDO) + * Store (One, NSDI) + * } + * } + */ + acpigen_write_method("_INI", 0); + + acpigen_write_if_lequal_namestr_int("OSVR", 0x03); + + acpigen_write_store_op_to_namestr(ONE_OP, "NSEN"); + acpigen_write_store_op_to_namestr(ZERO_OP, "NSDO"); + acpigen_write_store_op_to_namestr(ZERO_OP, "NSDI"); + + acpigen_pop_len(); /* If */ + + acpigen_pop_len(); /* Method _INI */ + + acpigen_pop_len(); /* Scope */ +} From 47cdf430e4c17864f45e18559846efce0e641c1d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 18:01:34 -0700 Subject: [PATCH 1238/1463] soc/amd/picasso: Disable MP2 FW inclusion by default Inclusion of MP2 firmware is optional and dependent on mainboard. Set default option for including MP2 firmware in PSP directory to 'n'. BUG=b:154880818 Signed-off-by: Furquan Shaikh Change-Id: I1ff7527a409d8ac7f4d30e69eafc53975b63e49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40680 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index afa18bc64c..c9f45f16f8 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -330,11 +330,11 @@ config USE_PSPSCUREOS config PSP_LOAD_MP2_FW bool "Include MP2 blobs in PSP build" - default y + default n help Include the MP2 firmwares and configuration into the PSP build. - If unsure, answer 'y' + If unsure, answer 'n' config PSP_LOAD_S0I3_FW bool "Include S0I3 blob in PSP build" From 30bc5b3131d8fcaa7ae637c061916a99f1b1aad9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 18:02:53 -0700 Subject: [PATCH 1239/1463] soc/amd/picasso: Disable inclusion of S0i3 firmware by default Enabling of S0i3 is a mainboard decision. This change sets the option to include S0i3 firmware by default to 'n'. BUG=b:154880818 Signed-off-by: Furquan Shaikh Change-Id: I5d533e317535b01efe9dd32272483296bf4fafab Reviewed-on: https://review.coreboot.org/c/coreboot/+/40681 Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index c9f45f16f8..384e8a80b4 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -338,6 +338,7 @@ config PSP_LOAD_MP2_FW config PSP_LOAD_S0I3_FW bool "Include S0I3 blob in PSP build" + default n help Select this item to include the S0i3 file into the PSP build. From 39288038f6aa8770aa3100597f50f275cf6a404a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 19:11:23 -0700 Subject: [PATCH 1240/1463] soc/amd/picasso: Drop addition of PUBSIGNEDKEY_FILE This change drops the addition of PUBSIGNEDKEY_FILE to PSP directory. This file is used to add OEM key for BIOS, however this is currently unused for upcoming zork board. In the future, if any mainboard needs this, it can be added based on some Kconfig selection. BUG=b:154880818 TEST=Verified that trembyle still boots up fine. Signed-off-by: Furquan Shaikh Change-Id: Icd97856a94a100898678702d99bbe29b82956004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40682 Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b04e1e9217..4991315c1c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -103,9 +103,6 @@ else PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin endif -# type = 0x5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSignedRV.key - # types = 0x8 and 0x18 PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin @@ -220,7 +217,6 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) OPT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) @@ -272,7 +268,6 @@ OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --uc OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ - $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ @@ -320,7 +315,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(AMDFWTOOL) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ $(OPT_PSPSCUREOS_FILE) \ $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ From 2bfce48b6efe20a9adbea3cbed794ca2fae9b99b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 19:44:31 -0700 Subject: [PATCH 1241/1463] soc/amd/picasso: Drop unused OPT_PSPNVRAM_FILE This change drops unused option OPT_PSPNVRAM_FILE from picasso Makefile. BUG=b:154880818 TEST=Verified that trembyle still boots to OS. Signed-off-by: Furquan Shaikh Change-Id: I64b328a92f5ee76e198a2ad3ec72d2cc4aeb9e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40684 Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 4991315c1c..b428b5df89 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -216,7 +216,6 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) OPT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) From 4e8b63970382d18498216ee84f3c9ee3bf3ec67d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 19:48:28 -0700 Subject: [PATCH 1242/1463] soc/amd/picasso: Drop addition of PSPTRUSTLETS_FILE PSPTRUSTLETS_FILE was including a binary for fTPM which according to BIOS architecture design guide is the firmware enabled TPM. Chrome OS does not really use firmware enabled TPM. Also, this is an option which is mainboard dependent. This change drops the addition of PSPTRUSTLETS_FILE to PSP directory. If this is something that is required by any mainboard, there should be a separate Kconfig to include the required files. BUG=b:154880818 TEST=Verified that trembyle still boots Signed-off-by: Furquan Shaikh Change-Id: Iaa2126c879986d00c921c85fb5cb5257c7065006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40685 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Makefile.inc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b428b5df89..6fd1524f5b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -116,9 +116,8 @@ PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin PSP_SOFTFUSE="0x0000000010000001" ifeq ($(CONFIG_USE_PSPSCUREOS),y) -# types = 0x2, 0xc +# types = 0x2 PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_ftpm_prod_RV.csbin endif # type = 0x13 @@ -223,7 +222,6 @@ OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogra OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) -OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) @@ -270,7 +268,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ - $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ $(call strip_quotes, $(PSP_APCB0_FILE)) \ $(call strip_quotes, $(PSP_APCB1_FILE)) \ $(call strip_quotes, $(PSP_APCB2_FILE)) \ @@ -316,7 +313,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_PSPSCUREOS_FILE) \ $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ $(OPT_SMUFW1_SUB2_FILE) \ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ From 90944101585f739092b983a46ef6fc9e91e4e5e3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 23 Apr 2020 23:34:17 -0700 Subject: [PATCH 1243/1463] soc/amd/picasso: Fix comment about SMU firmware2 type SMU firmware2 has type 0x12 i.e. decimal 18 and not 0x18. This change updates the comment for SMU firmware2 type. Change-Id: Ia2e35aff3e460a3423f90d6ecdbe2362331391f3 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40698 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6fd1524f5b..224202f4a1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -103,7 +103,7 @@ else PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin endif -# types = 0x8 and 0x18 +# types = 0x8 and 0x12 PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin From d4ef9a44857cde949dff3ba2bb468eb5910f75ac Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 11:49:32 -0700 Subject: [PATCH 1244/1463] soc/amd/picasso: Drop prompts from some Kconfig options Some of the PSP Kconfig options that are prompted to the user should really be selected by mainboard. This change updates such options to not make them user-visible any more. BUG=b:154880818 Change-Id: Iaff02fb1e720e0562b740799593322e59b022212 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40699 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/amd/picasso/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 384e8a80b4..a37f5430ed 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -227,7 +227,7 @@ config EARLYRAM_BSP_STACK_SIZE menu "PSP Configuration Options" config AMDFW_OUTSIDE_CBFS - bool "The AMD firmware is outside CBFS" + bool default n help The AMDFW (PSP) is typically locatable in cbfs. Select this @@ -268,11 +268,11 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 config AMD_PUBKEY_FILE - string "AMD public Key" + string default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" config PSP_APCB_FILE - string "APCB file" + string help The name of the AGESA Parameter Customization Block. This image is instance ID 0 in the PSP's BIOS Directory Table. @@ -321,7 +321,7 @@ config PSP_APOB_NV_SIZE size the flash device can erase. config USE_PSPSCUREOS - bool "Include PSP SecureOS blobs in PSP build" + bool default y help Include the PspSecureOs and PspTrustlet binaries in the PSP build. @@ -329,7 +329,7 @@ config USE_PSPSCUREOS If unsure, answer 'y' config PSP_LOAD_MP2_FW - bool "Include MP2 blobs in PSP build" + bool default n help Include the MP2 firmwares and configuration into the PSP build. @@ -337,7 +337,7 @@ config PSP_LOAD_MP2_FW If unsure, answer 'n' config PSP_LOAD_S0I3_FW - bool "Include S0I3 blob in PSP build" + bool default n help Select this item to include the S0i3 file into the PSP build. From 318e5830dbed98e6ae7574812b4d8b5b6496341c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 14:04:07 -0700 Subject: [PATCH 1245/1463] soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSE This change updates Makefile.inc to use a helper function set-bit to set a bit for the soft fuses. It gets rid of the different checks that were done to set soft fuses to magic values in different places. This is still not the best way to handle the fuses and instead this logic should be embedded within the amdfwtool by making it aware of specific platforms. But until that happens, we want to avoid having to add PSP_SOFTFUSE setting in various places with different values. BUG=b:154880818 TEST=Verified that the softfuse values are same with and without this change. Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40700 Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 224202f4a1..d7cf9c052c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -111,9 +111,8 @@ PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin # type = 0x9 PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin - -# type = 0xb - See #55758 (NDA) for bit definitions. -PSP_SOFTFUSE="0x0000000010000001" +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 ifeq ($(CONFIG_USE_PSPSCUREOS),y) # types = 0x2 @@ -137,7 +136,8 @@ PSP_MP2FW2_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin # BIOS type = 0x6a PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin else -PSP_SOFTFUSE="0x0000000030000001" +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 endif # type = 0x28 @@ -206,6 +206,14 @@ PSP_UCODE_FILE1=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin PSP_UCODE_FILE2=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin PSP_UCODE_FILE3=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +# type = 0xb - See #55758 (NDA) for bit definitions. +PSP_SOFTFUSE_BITS += 28 + +# Helper function to return a value with given bit set +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + # # Build the arguments to amdfwtool (order is unimportant). Missing file names # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. From 60e0dc3919324ae7a5c3f2766790b0c76c39f25c Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 22 Nov 2019 16:36:56 +0100 Subject: [PATCH 1246/1463] util/kconfig: Remove miniconfig script It replicates the functionality of savedefconfig because back when the script was added, savedefconfig didn't work for us. It now does, is the official way of doing things, is recommended in our documentation and is also a fair bit faster. Change-Id: Ia8e0377537ff7cd638c564037ea6a77b01a87243 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37150 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Angel Pons --- util/kconfig/miniconfig | 87 ----------------------------------------- 1 file changed, 87 deletions(-) delete mode 100755 util/kconfig/miniconfig diff --git a/util/kconfig/miniconfig b/util/kconfig/miniconfig deleted file mode 100755 index 29a40353d7..0000000000 --- a/util/kconfig/miniconfig +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/env bash -# -# miniconfig - utility to minimize your coreboot config files -# -# Copyright 2015 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -CONFIG=$1 -NEWCONFIG=$2 - -CONF=build/util/kconfig/conf -KCONFIG=src/Kconfig -DOTCONFIG=.config -PREVCONFIG=.config.prev -TMPCONFIG=.config.mini - -recreate_config() -{ - $CONF --olddefconfig $KCONFIG &> /dev/null -} - -if [ "$CONFIG" == "" ]; then - printf "usage: util/miniconfig/miniconfig [path to config file] \n" - exit 0 -fi - -if [ ! -r "$CONFIG" ]; then - printf "Can't read $CONFIG.\n" - exit 1 -fi - -if [ "$CONFIG" == .config ]; then - printf "Can't use .config, it's overwritten. Make a backup.\n" - exit 1 -fi - -if [ ! -x "$CONF" ]; then - printf "conf utility at $CONF not available.\n" - exit 1 -fi - -# Start out by creating a default config file for a mainboard -VENDOR=$( grep ^CONFIG_VENDOR "$CONFIG" ) -BOARD=$( grep ^CONFIG_BOARD "$CONFIG" | grep -v ROMSIZE | grep -v SPECIFIC_OPTIONS ) - -printf "$VENDOR\n$BOARD\n" > "$TMPCONFIG" -cp "$TMPCONFIG" "$DOTCONFIG" -recreate_config - -LINES=$( cat "$CONFIG" | wc -l ) -CUR=1 - -# Now go through each line of the existing, large config file, add it to our -# new minimal config file, and see if it makes a difference when running "make -# olddefconfig". If it does, keep the line, otherwise discard it. - -cat "$CONFIG" | while read L; do - printf "\rProcessing $CONFIG - $CUR / $LINES (%d%%)" $(( $CUR * 100 / $LINES)) - mv "$DOTCONFIG" "$PREVCONFIG" - cp "$TMPCONFIG" "$DOTCONFIG" - echo "$L" >> "$DOTCONFIG" - recreate_config - - if ! diff -q "$DOTCONFIG" "$PREVCONFIG" > /dev/null; then - echo "$L" >> "$TMPCONFIG" - fi - CUR=$(( $CUR + 1 )) -done - -echo - -if [ "$NEWCONFIG" != "" ]; then - printf "Writing new, minimized config to $NEWCONFIG\n" - mv "$TMPCONFIG" "$NEWCONFIG" -else - printf "Overwriting $CONFIG with new, minimized config.\n" - mv "$TMPCONFIG" "$CONFIG" -fi From ab90782e7220d188e916680da21b49a011208f3f Mon Sep 17 00:00:00 2001 From: BryantOu Date: Fri, 17 Apr 2020 02:15:17 -0700 Subject: [PATCH 1247/1463] superio/aspeed/common: Add early configure functions Add LPC read/write functions for access aspeed's memory, also create config data table to config memory and SIO. These functions are used at early stages to configure devices. Signed-off-by: Bryant Ou Change-Id: Ib59c29a042b2c7bf196b8a5bd5218704d8075855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40483 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/superio/aspeed/Makefile.inc | 2 + src/superio/aspeed/common/aspeed.h | 488 +++++++++++++++++++ src/superio/aspeed/common/early_config.c | 575 +++++++++++++++++++++++ src/superio/aspeed/common/early_serial.c | 3 - 4 files changed, 1065 insertions(+), 3 deletions(-) create mode 100644 src/superio/aspeed/common/early_config.c diff --git a/src/superio/aspeed/Makefile.inc b/src/superio/aspeed/Makefile.inc index 769334e8d8..2810c077c9 100644 --- a/src/superio/aspeed/Makefile.inc +++ b/src/superio/aspeed/Makefile.inc @@ -4,6 +4,8 @@ ## include generic fintek pre-ram stage driver romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c bootblock-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c +bootblock-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_config.c + subdirs-y += ast2400 subdirs-y += common diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h index f77258912d..3094f1a91a 100644 --- a/src/superio/aspeed/common/aspeed.h +++ b/src/superio/aspeed/common/aspeed.h @@ -7,9 +7,497 @@ #include #include +/* AST2300/2400/2500/2600 use the same memory base */ +#define ASPEED_MEM_BASE1 0x1E6E0000 +#define ASPEED_MMC_BASE (ASPEED_MEM_BASE1) +#define ASPEED_USB_BASE (ASPEED_MEM_BASE1 + 0x1000) +#define ASPEED_SCU_BASE (ASPEED_MEM_BASE1 + 0x2000) +#define ASPEED_HACE_BASE (ASPEED_MEM_BASE1 + 0x3000) +#define ASPEED_JTAG_BASE (ASPEED_MEM_BASE1 + 0x4000) +#define ASPEED_GFX_BASE (ASPEED_MEM_BASE1 + 0x6000) +#define ASPEED_X_DMA_BASE (ASPEED_MEM_BASE1 + 0x7000) +#define ASPEED_MCTP_BASE (ASPEED_MEM_BASE1 + 0x8000) +#define ASPEED_ADC_BASE (ASPEED_MEM_BASE1 + 0x9000) +#define ASPEED_LPC_PLUS_BASE (ASPEED_MEM_BASE1 + 0xC000) +#define ASPEED_PCIE_BASE (ASPEED_MEM_BASE1 + 0xD000) +#define ASPEED_ESPI_BASE (ASPEED_MEM_BASE1 + 0xE000) +#define ASPEED_BAT_BASE (ASPEED_MEM_BASE1 + 0xF000) +#define ASPEED_MEM_BASE2 0x1E780000 +#define ASPEED_GPIO_BASE (ASPEED_MEM_BASE2) +#define ASPEED_RTC_BASE (ASPEED_MEM_BASE2 + 0x1000) +#define ASPEED_TIMER_BASE (ASPEED_MEM_BASE2 + 0x2000) +#define ASPEED_UART1_BASE (ASPEED_MEM_BASE2 + 0x3000) +#define ASPEED_UART5_BASE (ASPEED_MEM_BASE2 + 0x4000) +#define ASPEED_WDT_BASE (ASPEED_MEM_BASE2 + 0x5000) +#define ASPEED_PWM_FAN_BASE (ASPEED_MEM_BASE2 + 0x6000) +#define ASPEED_VUART_BASE (ASPEED_MEM_BASE2 + 0x7000) +#define ASPEED_PUART_BASE (ASPEED_MEM_BASE2 + 0x8000) +#define ASPEED_LPC_BASE (ASPEED_MEM_BASE2 + 0x9000) +#define ASPEED_I2C_BASE (ASPEED_MEM_BASE2 + 0xA000) +#define ASPEED_PECI_BASE (ASPEED_MEM_BASE2 + 0xB000) +#define ASPEED_APB2PCI_BASE (ASPEED_MEM_BASE2 + 0xC000) +#define ASPEED_UART2_BASE (ASPEED_MEM_BASE2 + 0xD000) +#define ASPEED_UART3_BASE (ASPEED_MEM_BASE2 + 0xE000) +#define ASPEED_UART4_BASE (ASPEED_MEM_BASE2 + 0xF000) + +/* System Control Unit */ +#define PRO_KEY_REG 0x00 +#define PRO_KEY_PASSWORD 0x1688A8A8 +#define SYS_RESET_CTL_REG 0x04 +#define CLK_SEL_REG 0x08 +#define CLK_STOP_CTL_REG 0x0C +#define FRQ_CNT_CTL_REG 0x10 +#define FRQ_CNT_CMP_REG 0x14 +#define INT_CTL_STS_REG 0x18 +#define D2_PLL_PARM_REG 0x1C +#define M_PLL_PARM_REG 0x20 +#define H_PLL_PARM_REG 0x24 +#define D_PLL_PARM_REG 0x28 +#define MISC_CTL_REG 0x2C +#define PCI_CFG_SET_REG1 0x30 +#define PCI_CFG_SET_REG2 0x34 +#define PCI_CFG_SET_REG3 0x38 +#define SYS_RESET_CTL_STS_REG 0x3C +#define VGA_FUNC_HANDSHAKE_REG1 0x40 +#define VGA_FUNC_HANDSHAKE_REG2 0x44 +#define MAC_CLK_DELAY_SET_REG 0x48 +#define MISC_2_CTL_REG 0x4C +#define VGA_SCRATCH_REG1 0x50 +#define VGA_SCRATCH_REG2 0x54 +#define VGA_SCRATCH_REG3 0x58 +#define VGA_SCRATCH_REG4 0x5C +#define VGA_SCRATCH_REG5 0x60 +#define VGA_SCRATCH_REG6 0x64 +#define VGA_SCRATCH_REG7 0x68 +#define VGA_SCRATCH_REG8 0x6C +#define HW_STRAP_REG 0x70 +#define RAN_NUM_GEN_CTL_REG 0x74 +#define RAN_NUM_GEN_DATA_OUT_REG 0x78 +#define SILICON_REV_ID_REG 0x7C +#define MUL_FUNC_PIN_CTL1_REG 0x80 +#define UART3_TXD3_EN_BIT 22 +#define UART3_RXD3_EN_BIT 23 +#define UART4_TXD4_EN_BIT 30 +#define UART4_RXD4_EN_BIT 31 +#define MUL_FUNC_PIN_CTL2_REG 0x84 +#define UART1_TXD1_EN_BIT 22 +#define UART1_RXD1_EN_BIT 23 +#define UART2_TXD2_EN_BIT 30 +#define UART2_RXD2_EN_BIT 31 +#define MUL_FUNC_PIN_CTL3_REG 0x88 +#define MUL_FUNC_PIN_CTL4_REG 0x8C +#define MUL_FUNC_PIN_CTL5_REG 0x90 +#define MUL_FUNC_PIN_CTL6_REG 0x94 +#define DIGI_VIDEO_OUT_PINS_DIS 0 +#define DIGI_VIDEO_OUT_PINS_EN 1 +#define EXTRST_RESET_SEL_REG 0x9C +#define MUL_FUNC_PIN_CTL7_REG 0xA0 +#define MUL_FUNC_PIN_CTL8_REG 0xA4 +#define MUL_FUNC_PIN_CTL9_REG 0xA8 +#define MUL_FUNC_PIN_CTL10_REG 0xAC +#define MAC_CLK_DELAY_100M_REG 0xB8 +#define MAC_CLK_DELAY_10M_REG 0xBC +#define PWR_SAVE_WAKEUP_EN_REG 0xC0 +#define PWR_SAVE_WAKEUP_CTL_REG 0xC4 +#define SYS_RESET_CTL_SET2_REG 0xD4 +#define CLK_SEL_SET2_REG 0xD8 +#define CLK_STOP_CTL_SET2_REG 0xDC +#define SCU_FREE_RUN_CNT_READ_BACK_REG 0xE0 +#define SCU_FREE_RUN_CNT_EXT_READ_BACK_REG 0xE4 +#define CLK_DUTY_MEASURE_CTL_REG 0xE8 +#define CLK_DUTY_MEASURE_RESULT_REG 0xEC +#define CPU2_CTL_REG 0x100 +#define CPU2_BASE_ADDR_SEG_REG1 0x104 +#define CPU2_BASE_ADDR_SEG_REG2 0x108 +#define CPU2_BASE_ADDR_SEG_REG3 0x10C +#define CPU2_BASE_ADDR_SEG_REG4 0x110 +#define CPU2_BASE_ADDR_SEG_REG5 0x114 +#define CPU2_BASE_ADDR_SEG_REG6 0x118 +#define CPU2_BASE_ADDR_SEG_REG7 0x11C +#define CPU2_BASE_ADDR_SEG_REG8 0x120 +#define CPU2_BASE_ADDR_SEG_REG9 0x124 +#define CPU2_CACHE_FUNC_CTL_REG 0x128 +#define D_PLL_EXT_PARM_REG1 0x130 +#define D_PLL_EXT_PARM_REG2 0x134 +#define D_PLL_EXT_PARM_REG3 0x138 +#define D2_PLL_EXT_PARM_REG1 0x13C +#define D2_PLL_EXT_PARM_REG2 0x140 +#define D2_PLL_EXT_PARM_REG3 0x144 +#define EXT_PARM_M_H_PLL_REG 0x148 +#define CHIP_UNIQ_ID_L_REG 0x150 +#define CHIP_UNIQ_ID_H_REG 0x154 +#define GEN_UART_24M_H_PLL_REG 0x160 +#define PCIE_CFG_SET_CTL_REG 0x180 +#define BMC_MMIO_DECODE_SET_REG 0x184 +#define FIRST_RELO_CTL_DECODE_AREA_LOCA_REG 0x188 +#define SECOND_RELO_CTL_DECODE_AREA_LOCA_REG 0x18C +#define MAILBOX_DECODE_AREA_LOCA_REG 0x190 +#define SHARED_SRAM_AREA_DECODE_LOCA_REG1 0x194 +#define SHARED_SRAM_AREA_DECODE_LOCA_REG2 0x198 +#define BMC_DEV_CLASS_CODE_REV_ID_REG 0x19C +#define BMC_DEV_ID_REG 0x1A4 +#define CLK_DUTY_SEL_REG 0x1DC + +/* LPC Controller */ +#define HICR0_REG 0x00 +#define HICR1_REG 0x04 +#define HICR2_REG 0x08 +#define HICR3_REG 0x0C +#define HICR4_REG 0x10 +#define LADR3H_REG 0x14 +#define LADR3L_REG 0x18 +#define LADR12H_REG 0x1C +#define LADR12L_REG 0x20 +#define IDR1_REG 0x24 +#define IDR2_REG 0x28 +#define IDR3_REG 0x2C +#define ODR1_REG 0x30 +#define ODR2_REG 0x34 +#define ODR3_REG 0x38 +#define STR1_REG 0x3C +#define STR2_REG 0x40 +#define STR3_REG 0x44 +#define BTR0_REG 0x48 +#define BRT1_REG 0x4C +#define BTCSR0_REG 0x50 +#define BTCSR1_REG 0x54 +#define BTCR_REG 0x58 +#define BTDTR_REG 0x5C +#define BTIMSR_REG 0x60 +#define BTFVSR0_REG 0x64 +#define BTFVSR1_REG 0x68 +#define SIRQCR0_REG 0x70 +#define SIRQCR1_REG 0x74 +#define SIRQCR2_REG 0x78 +#define SIRQCR3_REG 0x7C +#define HICR5_REG 0x80 +#define SNOOP_ADDR_EN 0 +#define HICR6_REG 0x84 +#define HICR7_REG 0x88 +#define HICR8_REG 0x8C +#define SNPWADR_REG 0x90 +#define SNOOP_ADDR_PORT80 0x80 +#define SNPWDR_REG 0x94 +#define HICR9_REG 0x98 +#define HICRA_REG 0x9C +#define LHCR0_REG 0xA0 +#define LHCR1_REG 0xA4 +#define LHCR2_REG 0xA8 +#define LHCR3_REG 0xAC +#define LHCR4_REG 0xB0 +#define LHCR5_REG 0xB4 +#define LHCR6_REG 0xB8 +#define LHCR7_REG 0xBC +#define LHCR8_REG 0xC0 +#define PCCR6_REG 0xC4 +#define LHCRA_REG 0xC8 +#define LHCRB_REG 0xCC +#define PCCR4_REG 0xD0 +#define PCCR5_REG 0xD4 +#define HICRB_REG 0x100 +#define HICRC_REG 0x104 +#define HISR0_REG 0x108 +#define HISR1_REG 0x10C +#define LADR4_REG 0x110 +#define IDR4_REG 0x114 +#define ODR4_REG 0x118 +#define STR4_REG 0x11C +#define LSADR12_REG 0x120 +#define IDR5_REG 0x124 +#define ODR5_REG 0x12C +#define PCCR0_REG 0x130 +#define PCCR1_REG 0x134 +#define PCCR2_REG 0x138 +#define PCCR3_REG 0x13C +#define IBTCR0_REG 0x140 +#define IBTCR1_REG 0x144 +#define IBTCR2_REG 0x148 +#define IBTCR3_REG 0x14C +#define IBTCR4_REG 0x150 +#define IBTCR5_REG 0x154 +#define IBTCR6_REG 0x158 +#define SRUART1_REG 0x160 +#define SRUART2_REG 0x164 +#define SRUART3_REG 0x168 +#define SRUART4_REG 0x16C +#define SCR0SIO_REG 0x170 +#define SCR1SIO_REG 0x174 +#define SCR2SIO_REG 0x178 +#define SCR3SIO_REG 0x17C +#define SWCR_03_00_REG 0x180 +#define SWCR_07_04_REG 0x184 +#define SWCR_0B_08_REG 0x188 +#define SWCR_0F_0C_REG 0x18C +#define SWCR_13_10_REG 0x190 +#define SWCR_17_14_REG 0x194 +#define SWCR_1B_18_REG 0x198 +#define SWCR_1F_1C_REG 0x19C +#define ACPI_E3_E0_REG 0x1A0 +#define ACPI_C1_C0_REG 0x1A4 +#define ACPI_B3_B0_REG 0x1A8 +#define ACPI_B7_B4_REG 0x1AC +#define MBXDAT_0_REG 0x200 +#define MBXDAT_1_REG 0x204 +#define MBXDAT_2_REG 0x208 +#define MBXDAT_3_REG 0x20C +#define MBXDAT_4_REG 0x210 +#define MBXDAT_5_REG 0x214 +#define MBXDAT_6_REG 0x218 +#define MBXDAT_7_REG 0x21C +#define MBXDAT_8_REG 0x220 +#define MBXDAT_9_REG 0x224 +#define MBXDAT_A_REG 0x228 +#define MBXDAT_B_REG 0x22C +#define MBXDAT_C_REG 0x230 +#define MBXDAT_D_REG 0x234 +#define MBXDAT_E_REG 0x238 +#define MBXDAT_F_REG 0x23C +#define MBXSTS_0_REG 0x240 +#define MBXSTS_1_REG 0x244 +#define MBXBCR_REG 0x248 +#define MBXHCR_REG 0x24C +#define MBXBIE_0_REG 0x250 +#define MBXBIE_1_REG 0x254 +#define MBXHIE_0_REG 0x258 +#define MBXHIE_1_REG 0x25C + +/* GPIO Controller */ +#define A_B_C_D_DATA_VALUE_REG 0x00 +#define A_B_C_D_DIRECTION_REG 0x04 +#define A_B_C_D_INT_EN_REG 0x08 +#define A_B_C_D_INT_SEN_T0_REG 0x0C +#define A_B_C_D_INT_SEN_T1_REG 0x10 +#define A_B_C_D_INT_SEN_T2_REG 0x14 +#define A_B_C_D_INT_STS_REG 0x18 +#define A_B_C_D_RESET_TOLE_REG 0x1C +#define E_F_G_H_DATA_VALUE_REG 0x20 +#define E_F_G_H_DIRECTION_REG 0x24 +#define E_F_G_H_INT_EN_REG 0x28 +#define E_F_G_H_INT_SEN_T0_REG 0x2C +#define E_F_G_H_INT_SEN_T1_REG 0x30 +#define E_F_G_H_INT_SEN_T2_REG 0x34 +#define E_F_G_H_INT_STS_REG 0x38 +#define E_F_G_H_RESET_TOLE_REG 0x3C +#define A_B_C_D_DEBOUNCE_SET_REG1 0x40 +#define A_B_C_D_DEBOUNCE_SET_REG2 0x44 +#define E_F_G_H_DEBOUNCE_SET_REG1 0x48 +#define E_F_G_H_DEBOUNCE_SET_REG2 0x4C +#define DEBOUNCE_TIMER_SET_REG1 0x50 +#define DEBOUNCE_TIMER_SET_REG2 0x54 +#define DEBOUNCE_TIMER_SET_REG3 0x58 +#define A_B_C_D_CMD_SOURCE0_REG 0x60 +#define A_B_C_D_CMD_SOURCE1_REG 0x64 +#define E_F_G_H_CMD_SOURCE0_REG 0x68 +#define E_F_G_H_CMD_SOURCE1_REG 0x6C +#define I_J_K_L_DATA_VALUE_REG 0x70 +#define I_J_K_L_DIRECTION_REG 0x74 +#define M_N_O_P_DATA_VALUE_REG 0x78 +#define M_N_O_P_DIRECTION_REG 0x7C +#define Q_R_S_T_DATA_VALUE_REG 0x80 +#define Q_R_S_T_DIRECTION_REG 0x84 +#define U_V_W_X_DATA_VALUE_REG 0x88 +#define U_V_W_X_DIRECTION_REG 0x8C +#define I_J_K_L_CMD_SOURCE0_REG 0x90 +#define I_J_K_L_CMD_SOURCE1_REG 0x94 +#define I_J_K_L_INT_EN_REG 0x98 +#define I_J_K_L_INT_SEN_T0_REG 0x9C +#define I_J_K_L_INT_SEN_T1_REG 0xA0 +#define I_J_K_L_INT_SEN_T2_REG 0xA4 +#define I_J_K_L_INT_STS_REG 0xA8 +#define I_J_K_L_RESET_TOLE_REG 0xAC +#define I_J_K_L_DEBOUNCE_SET_REG1 0xB0 +#define I_J_K_L_DEBOUNCE_SET_REG2 0xB4 +#define I_J_K_L_INPUT_MASK 0xB8 +#define A_B_C_D_DATA_READ_REG 0xC0 +#define E_F_G_H_DATA_READ_REG 0xC4 +#define I_J_K_L_DATA_READ_REG 0xC8 +#define M_N_O_P_DATA_READ_REG 0xCC +#define Q_R_S_T_DATA_READ_REG 0xD0 +#define U_V_W_X_DATA_READ_REG 0xD4 +#define Y_Z_AA_AB_DATA_READ_REG 0xD8 +#define AC_DATA_READ_REG 0xDC +#define M_N_O_P_CMD_SOURCE0_REG 0xE0 +#define M_N_O_P_CMD_SOURCE1_REG 0xE4 +#define M_N_O_P_INT_EN_REG 0xE8 +#define M_N_O_P_INT_SEN_T0_REG 0xEC +#define M_N_O_P_INT_SEN_T1_REG 0xF0 +#define M_N_O_P_INT_SEN_T2_REG 0xF4 +#define M_N_O_P_INT_STS_REG 0xF8 +#define M_N_O_P_RESET_TOLE_REG 0xFC +#define M_N_O_P_DEBOUNCE_SET_REG1 0x100 +#define M_N_O_P_DEBOUNCE_SET_REG2 0x104 +#define M_N_O_P_INPUT_MASK 0x108 +#define Q_R_S_T_CMD_SOURCE0_REG 0x110 +#define Q_R_S_T_CMD_SOURCE1_REG 0x114 +#define Q_R_S_T_INT_EN_REG 0x118 +#define Q_R_S_T_INT_SEN_T0_REG 0x11C +#define Q_R_S_T_INT_SEN_T1_REG 0x120 +#define Q_R_S_T_INT_SEN_T2_REG 0x124 +#define Q_R_S_T_INT_STS_REG 0x128 +#define Q_R_S_T_RESET_TOLE_REG 0x12C +#define Q_R_S_T_DEBOUNCE_SET_REG1 0x130 +#define Q_R_S_T_DEBOUNCE_SET_REG2 0x134 +#define Q_R_S_T_INPUT_MASK 0x138 +#define U_V_W_X_CMD_SOURCE0_REG 0x140 +#define U_V_W_X_CMD_SOURCE1_REG 0x144 +#define U_V_W_X_INT_EN_REG 0x148 +#define U_V_W_X_INT_SEN_T0_REG 0x14C +#define U_V_W_X_INT_SEN_T1_REG 0x150 +#define U_V_W_X_INT_SEN_T2_REG 0x154 +#define U_V_W_X_INT_STS_REG 0x158 +#define U_V_W_X_RESET_TOLE_REG 0x15C +#define U_V_W_X_DEBOUNCE_SET_REG1 0x160 +#define U_V_W_X_DEBOUNCE_SET_REG2 0x164 +#define U_V_W_X_INPUT_MASK 0x168 +#define Y_Z_AA_AB_CMD_SOURCE0_REG 0x170 +#define Y_Z_AA_AB_CMD_SOURCE1_REG 0x174 +#define Y_Z_AA_AB_INT_EN_REG 0x178 +#define Y_Z_AA_AB_INT_SEN_T0_REG 0x17C +#define Y_Z_AA_AB_INT_SEN_T1_REG 0x180 +#define Y_Z_AA_AB_INT_SEN_T2_REG 0x184 +#define Y_Z_AA_AB_INT_STS_REG 0x188 +#define Y_Z_AA_AB_RESET_TOLE_REG 0x18C +#define Y_Z_AA_AB_DEBOUNCE_SET_REG1 0x190 +#define Y_Z_AA_AB_DEBOUNCE_SET_REG2 0x194 +#define Y_Z_AA_AB_INPUT_MASK 0x198 +#define AC_CMD_SOURCE0_REG 0x1A0 +#define AC_CMD_SOURCE1_REG 0x1A4 +#define AC_INT_EN_REG 0x1A8 +#define AC_INT_SEN_T0_REG 0x1AC +#define AC_INT_SEN_T1_REG 0x1B0 +#define AC_INT_SEN_T2_REG 0x1B4 +#define AC_INT_STS_REG 0x1B8 +#define AC_RESET_TOLE_REG 0x1BC +#define AC_DEBOUNCE_SET_REG1 0x1C0 +#define AC_DEBOUNCE_SET_REG2 0x1C4 +#define AC_INPUT_MASK 0x1C8 +#define A_B_C_D_INPUT_MASK 0x1D0 +#define E_F_G_H_INPUT_MASK 0x1D4 +#define Y_Z_AA_AB_DATA_VALUE_REG 0x1E0 +#define Y_Z_AA_AB_DIRECTION_REG 0x1E4 +#define AC_DATA_VALUE_REG 0x1E8 +#define AC_DIRECTION_REG 0x1EC + +/* SuperIO Controller */ +#define LDN_ILPC2AHB 0xD +#define LDN_SUART1 0x02 +#define LDN_SUART2 0x03 +#define LDN_SUART3 0x0B +#define LDN_SUART4 0x0C +#define LDN_SEL_REG 0x07 +#define ACT_REG 0x30 +#define ACTIVATE_VALUE 0x01 +#define DEACTIVATE_VALUE 0x00 +#define PORT80_GPIO_EN 0x80 +#define PORT80_GPIO_SEL_REG 0x38 +#define INV_GPIO_EN 0x80 +#define LPC2AHB_ADD0_REG 0xF0 +#define LPC2AHB_ADD1_REG 0xF1 +#define LPC2AHB_ADD2_REG 0xF2 +#define LPC2AHB_ADD3_REG 0xF3 +#define LPC2AHB_DAT0_REG 0xF4 +#define LPC2AHB_DAT1_REG 0xF5 +#define LPC2AHB_DAT2_REG 0xF6 +#define LPC2AHB_DAT3_REG 0xF7 +#define LPC2AHB_LEN_REG 0xF8 +#define LPC2AHB_1_BYTE 0x00 +#define LPC2AHB_2_BYTE 0x01 +#define LPC2AHB_4_BYTE 0x02 +#define LPC2AHB_RW_REG 0xFE + +#define ASPEED_ENTRY_KEY 0xA5 +#define ASPEED_EXIT_KEY 0xAA + +#define TO_BE_UPDATE 0 +#define AndMask32(HighBit, LowBit) ~((((uint32_t) 1 << (HighBit - LowBit + 1)) - 1) << LowBit) + +typedef enum { + GPIOA = 0, + GPIOB, + GPIOC, + GPIOD, + GPIOE, + GPIOF, + GPIOG, + GPIOH, + GPIOI, + GPIOJ, + GPIOK, + GPIOL, + GPIOM, + GPION, + GPIOO, + GPIOP, + GPIOQ, + GPIOR, + GPIOS, + GPIOT, + GPIOU, + GPIOV, + GPIOW, + GPIOX, + GPIOY, + GPIOZ, + GPIOAA, + GPIOAB, +} gpio_group_sel; + +enum { + Step1 = 0, + Step2, + Step3, + Step4, + Step5, + Step6, + Step7, + Step8, + Step9, + Step10, + Step11, + Step12, + Step13, + Step14, + Step15, + Step16, + Step17, + Step18, + Step19, + Step20, +}; + +enum { + ARM = 0, + LPC, + CoprocessorCPU, + Reserved, +}; + +typedef enum { + SIO = 0, + MEM, + NOP, +} config_type; + +typedef struct config_data { + config_type type; + uint32_t base; + uint16_t reg; + uint32_t and; + uint32_t or; +} config_data; + void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase); +void aspeed_early_config(pnp_devfn_t dev, config_data *table, uint8_t count); + +/* Enable SuperIO feature which is described in ASPEED datasheet */ +void aspeed_enable_port80_direct_gpio(pnp_devfn_t dev, gpio_group_sel g); + +/* Enable UART multi-function pins which is described in ASPEED datasheet */ +void aspeed_enable_uart_pin(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); +void lpc_read(uint8_t port, uint32_t addr, uint32_t *value); +void lpc_write(uint8_t port, uint32_t addr, uint32_t data); #endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */ diff --git a/src/superio/aspeed/common/early_config.c b/src/superio/aspeed/common/early_config.c new file mode 100644 index 0000000000..8d425a0779 --- /dev/null +++ b/src/superio/aspeed/common/early_config.c @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include "aspeed.h" + +void lpc_read(uint8_t port, uint32_t addr, uint32_t *value) +{ + uint32_t data = 0; + uint8_t tmp; + pnp_devfn_t dev = PNP_DEV(port, LDN_ILPC2AHB); + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + /* Write Address */ + pnp_write_config(dev, LPC2AHB_ADD0_REG, ((addr & 0xff000000) >> 24)); + pnp_write_config(dev, LPC2AHB_ADD1_REG, ((addr & 0x00ff0000) >> 16)); + pnp_write_config(dev, LPC2AHB_ADD2_REG, ((addr & 0x0000ff00) >> 8)); + pnp_write_config(dev, LPC2AHB_ADD3_REG, (addr & 0x000000ff)); + + /* Write Mode */ + tmp = pnp_read_config(dev, LPC2AHB_LEN_REG); + pnp_write_config(dev, LPC2AHB_LEN_REG, (tmp & 0xfc) | LPC2AHB_4_BYTE); + + /* Fire the command */ + outb(LPC2AHB_RW_REG, port); + tmp = inb(port + 1); + + /* Get Data */ + data |= (pnp_read_config(dev, LPC2AHB_DAT0_REG) << 24) | + (pnp_read_config(dev, LPC2AHB_DAT1_REG) << 16) | + (pnp_read_config(dev, LPC2AHB_DAT2_REG) << 8) | + pnp_read_config(dev, LPC2AHB_DAT3_REG); + *value = data; + + pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +void lpc_write(uint8_t port, uint32_t addr, uint32_t data) +{ + uint8_t tmp; + pnp_devfn_t dev = PNP_DEV(port, LDN_ILPC2AHB); + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + /* Write Address */ + pnp_write_config(dev, LPC2AHB_ADD0_REG, ((addr & 0xFF000000) >> 24)); + pnp_write_config(dev, LPC2AHB_ADD1_REG, ((addr & 0x00FF0000) >> 16)); + pnp_write_config(dev, LPC2AHB_ADD2_REG, ((addr & 0x0000FF00) >> 8)); + pnp_write_config(dev, LPC2AHB_ADD3_REG, (addr & 0x000000FF)); + + /* Write Data */ + pnp_write_config(dev, LPC2AHB_DAT0_REG, ((data & 0xFF000000) >> 24)); + pnp_write_config(dev, LPC2AHB_DAT1_REG, ((data & 0x00FF0000) >> 16)); + pnp_write_config(dev, LPC2AHB_DAT2_REG, ((data & 0x0000FF00) >> 8)); + pnp_write_config(dev, LPC2AHB_DAT3_REG, (data & 0x000000FF)); + + /* Write Mode */ + tmp = pnp_read_config(dev, LPC2AHB_LEN_REG); + pnp_write_config(dev, LPC2AHB_LEN_REG, (tmp & 0xfc) | LPC2AHB_4_BYTE); + + /* Fire */ + pnp_write_config(dev, LPC2AHB_RW_REG, 0xcf); + + pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +void aspeed_early_config(pnp_devfn_t dev, config_data *table, uint8_t count) +{ + uint8_t i, t, port; + uint32_t v, addr; + port = dev >> 8; + for (i = 0; i < count; i++) { + if (table[i].type == MEM) { + addr = (u32)(table[i].base | table[i].reg); + lpc_read(port, addr, &v); + v &= table[i].and; + v |= table[i].or; + lpc_write(port, addr, v); + } else if (table[i].type == SIO) { + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + t = pnp_read_config(dev, ACT_REG) | ACTIVATE_VALUE; + pnp_write_config(dev, ACT_REG, t); + t = pnp_read_config(dev, (uint8_t)(table[i].reg)); + t &= (uint8_t)(table[i].and); + t |= (uint8_t)(table[i].or); + pnp_write_config(dev, (uint8_t)(table[i].reg), t); + pnp_set_logical_device(dev); + t = pnp_read_config(dev, ACT_REG) & ~ACTIVATE_VALUE; + pnp_write_config(dev, ACT_REG, t); + pnp_exit_conf_state(dev); + } + } +} + +void aspeed_enable_port80_direct_gpio(pnp_devfn_t dev, gpio_group_sel g) +{ + struct config_data port80[] = { + /* Set command source 0 */ + [Step1] = { + .type = MEM, + .base = ASPEED_GPIO_BASE, + .reg = TO_BE_UPDATE, + .and = AndMask32((g % 4) * 8, (g % 4) * 8), + .or = (LPC & 0x01) << ((g % 4) * 8) + }, + /* Set command source 1 */ + [Step2] = { + .type = MEM, + .base = ASPEED_GPIO_BASE, + .reg = TO_BE_UPDATE, + .and = AndMask32((g % 4) * 8, (g % 4) * 8), + .or = (LPC & 0x02) << ((g % 4) * 8) + }, + /* Unlock SCU registers */ + [Step3] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = PRO_KEY_REG, + .and = 0, + .or = PRO_KEY_PASSWORD + }, + /* Program multi-function to GPIO */ + [Step4] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = TO_BE_UPDATE, + .and = TO_BE_UPDATE, + .or = TO_BE_UPDATE + }, + [Step5] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = TO_BE_UPDATE, + .and = TO_BE_UPDATE, + .or = TO_BE_UPDATE + }, + [Step6] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = TO_BE_UPDATE, + .and = TO_BE_UPDATE, + .or = TO_BE_UPDATE + }, + [Step7] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = TO_BE_UPDATE, + .and = TO_BE_UPDATE, + .or = TO_BE_UPDATE + }, + /* Program GPIO as output */ + [Step8] = { + .type = MEM, + .base = ASPEED_GPIO_BASE, + .reg = TO_BE_UPDATE, + .and = AndMask32((((g % 4) + 1) * 8) - 1, (g % 4) * 8), + .or = 0xFF << ((g % 4) * 8) + }, + /* Set snooping address#0 as 80h */ + [Step9] = { + .type = MEM, + .base = ASPEED_LPC_BASE, + .reg = SNPWADR_REG, + .and = AndMask32(15, 0), + .or = SNOOP_ADDR_PORT80 + }, + /* Enable snooping address#0 */ + [Step10] = { + .type = MEM, + .base = ASPEED_LPC_BASE, + .reg = HICR5_REG, + .and = AndMask32(0, 0), + .or = 1 << SNOOP_ADDR_EN + }, + /* Lock SCU registers */ + [Step11] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = PRO_KEY_REG, + .and = 0, + .or = 0 + }, + /* Select group for port80 GPIO */ + [Step12] = { + .type = SIO, + .base = 0, + .reg = PORT80_GPIO_SEL_REG, + .and = AndMask32(4, 0), + .or = g + }, + /* Enable port80 GPIO */ + [Step13] = { + .type = SIO, + .base = 0, + .reg = ACT_REG, + .and = AndMask32(8, 8), + .or = PORT80_GPIO_EN + }, + }; + + switch (g) { + case GPIOA: + case GPIOB: + case GPIOC: + case GPIOD: + port80[Step1].reg = A_B_C_D_CMD_SOURCE0_REG; + port80[Step2].reg = A_B_C_D_CMD_SOURCE1_REG; + port80[Step8].reg = A_B_C_D_DIRECTION_REG; + break; + case GPIOE: + case GPIOF: + case GPIOG: + case GPIOH: + port80[Step1].reg = E_F_G_H_CMD_SOURCE0_REG; + port80[Step2].reg = E_F_G_H_CMD_SOURCE1_REG; + port80[Step8].reg = E_F_G_H_DIRECTION_REG; + break; + case GPIOI: + case GPIOJ: + case GPIOK: + case GPIOL: + port80[Step1].reg = I_J_K_L_CMD_SOURCE0_REG; + port80[Step2].reg = I_J_K_L_CMD_SOURCE1_REG; + port80[Step8].reg = I_J_K_L_DIRECTION_REG; + break; + case GPIOM: + case GPION: + case GPIOO: + case GPIOP: + port80[Step1].reg = M_N_O_P_CMD_SOURCE0_REG; + port80[Step2].reg = M_N_O_P_CMD_SOURCE1_REG; + port80[Step8].reg = M_N_O_P_DIRECTION_REG; + break; + case GPIOQ: + case GPIOR: + case GPIOS: + case GPIOT: + port80[Step1].reg = Q_R_S_T_CMD_SOURCE0_REG; + port80[Step2].reg = Q_R_S_T_CMD_SOURCE1_REG; + port80[Step8].reg = Q_R_S_T_DIRECTION_REG; + break; + case GPIOU: + case GPIOV: + case GPIOW: + case GPIOX: + port80[Step1].reg = U_V_W_X_CMD_SOURCE0_REG; + port80[Step2].reg = U_V_W_X_CMD_SOURCE1_REG; + port80[Step8].reg = U_V_W_X_DIRECTION_REG; + break; + case GPIOY: + case GPIOZ: + case GPIOAA: + case GPIOAB: + port80[Step1].reg = Y_Z_AA_AB_CMD_SOURCE0_REG; + port80[Step2].reg = Y_Z_AA_AB_CMD_SOURCE1_REG; + port80[Step8].reg = Y_Z_AA_AB_DIRECTION_REG; + break; + } + + switch (g) { + case GPIOA: + port80[Step4].reg = MUL_FUNC_PIN_CTL1_REG; + port80[Step4].and = AndMask32(7, 0) & AndMask32(15, 15); + port80[Step5].reg = MUL_FUNC_PIN_CTL4_REG; + port80[Step5].and = AndMask32(6, 6) & AndMask32(2, 2) & AndMask32(22, 22); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOB: + port80[Step4].reg = HW_STRAP_REG; + port80[Step4].and = AndMask32(23, 23); + port80[Step5].reg = MUL_FUNC_PIN_CTL1_REG; + port80[Step5].and = AndMask32(14, 13); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOC: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(0, 0); + port80[Step5].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step5].and = AndMask32(26, 23); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOD: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(1, 1); + port80[Step5].reg = MUL_FUNC_PIN_CTL4_REG; + port80[Step5].and = AndMask32(11, 8); + port80[Step6].reg = HW_STRAP_REG; + port80[Step6].and = AndMask32(21, 21); + port80[Step7].type = NOP; + break; + case GPIOE: + port80[Step4].reg = MUL_FUNC_PIN_CTL1_REG; + port80[Step4].and = AndMask32(23, 16); + port80[Step5].reg = MUL_FUNC_PIN_CTL4_REG; + port80[Step5].and = AndMask32(15, 12); + port80[Step6].reg = HW_STRAP_REG; + port80[Step6].and = AndMask32(22, 22); + port80[Step7].type = NOP; + break; + case GPIOF: + port80[Step4].base = ASPEED_LPC_BASE; + port80[Step4].reg = LHCR0_REG; + port80[Step4].and = AndMask32(0, 0); + port80[Step5].reg = MUL_FUNC_PIN_CTL1_REG; + port80[Step5].and = AndMask32(31, 24); + port80[Step6].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step6].and = AndMask32(30, 30); + port80[Step7].type = NOP; + break; + case GPIOG: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(6, 6); + port80[Step5].reg = MUL_FUNC_PIN_CTL2_REG; + port80[Step5].and = AndMask32(7, 0); + port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG; + port80[Step6].and = AndMask32(12, 12); + port80[Step7].type = NOP; + break; + case GPIOH: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(7, 6); + port80[Step5].reg = FRQ_CNT_CTL_REG; + port80[Step5].and = AndMask32(8, 8); + port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG; + port80[Step6].and = AndMask32(7, 5); + port80[Step7].type = NOP; + break; + case GPIOI: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(6, 6); + port80[Step5].reg = HW_STRAP_REG; + port80[Step5].and = AndMask32(13, 12) & AndMask32(5, 5); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOJ: + port80[Step4].reg = FRQ_CNT_CTL_REG; + port80[Step4].and = AndMask32(8, 8); + port80[Step5].reg = MUL_FUNC_PIN_CTL2_REG; + port80[Step5].and = AndMask32(15, 8); + port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG; + port80[Step6].and = AndMask32(8, 8); + port80[Step7].type = NOP; + break; + case GPIOK: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(21, 18); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOL: + port80[Step4].reg = MUL_FUNC_PIN_CTL2_REG; + port80[Step4].and = AndMask32(23, 16); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOM: + port80[Step4].reg = MUL_FUNC_PIN_CTL2_REG; + port80[Step4].and = AndMask32(31, 24); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPION: + port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG; + port80[Step4].and = AndMask32(7, 0); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOO: + port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG; + port80[Step4].and = AndMask32(15, 8); + port80[Step5].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step5].and = AndMask32(5, 5) & AndMask32(5, 4); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOP: + port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG; + port80[Step4].and = AndMask32(23, 16); + port80[Step5].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step5].and = AndMask32(5, 5) & AndMask32(5, 4) & AndMask32(28, 28); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOQ: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(17, 16) & AndMask32(27, 27); + port80[Step5].reg = MISC_CTL_REG; + port80[Step5].and = AndMask32(1, 1) & AndMask32(29, 29); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOR: + port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG; + port80[Step4].and = AndMask32(31, 24); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOS: + port80[Step4].reg = MUL_FUNC_PIN_CTL4_REG; + port80[Step4].and = AndMask32(7, 0); + port80[Step5].reg = MUL_FUNC_PIN_CTL6_REG; + port80[Step5].and = AndMask32(1, 0); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOT: + port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG; + port80[Step4].and = AndMask32(7, 0); + port80[Step4].or = ~AndMask32(7, 0); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOU: + port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG; + port80[Step4].and = AndMask32(15, 8); + port80[Step4].or = ~AndMask32(15, 8); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOV: + port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG; + port80[Step4].and = AndMask32(23, 16); + port80[Step4].or = ~AndMask32(23, 16); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOW: + port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG; + port80[Step4].and = AndMask32(31, 24); + port80[Step4].or = ~AndMask32(31, 24); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOX: + port80[Step4].reg = MUL_FUNC_PIN_CTL8_REG; + port80[Step4].and = AndMask32(7, 0); + port80[Step4].or = ~AndMask32(7, 0); + port80[Step5].type = NOP; + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOY: + port80[Step4].reg = HW_STRAP_REG; + port80[Step4].and = AndMask32(19, 19); + port80[Step5].reg = MUL_FUNC_PIN_CTL8_REG; + port80[Step5].and = AndMask32(15, 8); + port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG; + port80[Step6].and = AndMask32(11, 10); + port80[Step7].type = NOP; + break; + case GPIOZ: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(31, 31); + port80[Step5].reg = MUL_FUNC_PIN_CTL8_REG; + port80[Step5].and = AndMask32(23, 16); + port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG; + port80[Step6].and = AndMask32(1, 0); + port80[Step6].reg = HW_STRAP_REG; + port80[Step6].and = AndMask32(19, 19); + break; + case GPIOAA: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(31, 31); + port80[Step5].reg = MUL_FUNC_PIN_CTL8_REG; + port80[Step5].and = AndMask32(31, 24); + port80[Step6].type = NOP; + port80[Step7].type = NOP; + break; + case GPIOAB: + port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG; + port80[Step4].and = AndMask32(31, 31); + port80[Step5].reg = MUL_FUNC_PIN_CTL9_REG; + port80[Step5].and = AndMask32(3, 0); + port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG; + port80[Step6].and = AndMask32(1, 0); + port80[Step7].type = NOP; + break; + default: + return; + } + + aspeed_early_config(dev, port80, ARRAY_SIZE(port80)); +} + +void aspeed_enable_uart_pin(pnp_devfn_t dev) +{ + struct config_data uart[] = { + /* Unlock SCU registers */ + [Step1] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = PRO_KEY_REG, + .and = 0, + .or = PRO_KEY_PASSWORD + }, + /* Enable UART function pin */ + [Step2] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = TO_BE_UPDATE, + .and = TO_BE_UPDATE, + .or = TO_BE_UPDATE + }, + [Step3] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = MUL_FUNC_PIN_CTL6_REG, + .and = AndMask32(1, 0), + .or = DIGI_VIDEO_OUT_PINS_DIS + }, + /* Lock SCU registers */ + [Step4] = { + .type = MEM, + .base = ASPEED_SCU_BASE, + .reg = PRO_KEY_REG, + .and = 0, + .or = 0 + }, + }; + + switch (dev & 0xff) { + case LDN_SUART1: + uart[Step2].reg = MUL_FUNC_PIN_CTL2_REG; + uart[Step2].and = AndMask32(23, 22); + uart[Step2].or = (1 << UART1_TXD1_EN_BIT) | (1 << UART1_RXD1_EN_BIT); + break; + case LDN_SUART2: + uart[Step2].reg = MUL_FUNC_PIN_CTL2_REG; + uart[Step2].and = AndMask32(31, 30); + uart[Step2].or = (1 << UART2_TXD2_EN_BIT) | (1 << UART2_RXD2_EN_BIT); + break; + case LDN_SUART3: + uart[Step2].reg = MUL_FUNC_PIN_CTL1_REG; + uart[Step2].and = AndMask32(23, 22); + uart[Step2].or = (1 << UART3_TXD3_EN_BIT) | (1 << UART3_RXD3_EN_BIT); + uart[Step3].type = NOP; + break; + case LDN_SUART4: + uart[Step2].reg = MUL_FUNC_PIN_CTL1_REG; + uart[Step2].and = AndMask32(31, 30); + uart[Step2].or = (1 << UART4_TXD4_EN_BIT) | (1 << UART4_RXD4_EN_BIT); + uart[Step3].type = NOP; + break; + default: + return; + } + + aspeed_early_config(dev, uart, ARRAY_SIZE(uart)); +} diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c index 086e9ddf1a..4051fd522a 100644 --- a/src/superio/aspeed/common/early_serial.c +++ b/src/superio/aspeed/common/early_serial.c @@ -27,9 +27,6 @@ #include #include "aspeed.h" -#define ASPEED_ENTRY_KEY 0xA5 -#define ASPEED_EXIT_KEY 0xAA - /* Enable configuration: pass entry key '0xA5' into index port dev. */ void pnp_enter_conf_state(pnp_devfn_t dev) { From c2af6097c26ad002dfbba6f079c0ec449f87afd7 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Wed, 22 Apr 2020 13:32:07 +0800 Subject: [PATCH 1248/1463] mb/google/octopus/variants/garg: update Garfour SKU ID SKUID: 49 - Garfour EVT (touch, TypeA DB) 50 - Garfour EVT (non-touch, HDMI DB) BUG=b:152861752 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I656a2bb2404efded6da6697664748b6c8d2ca4e0 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/40586 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Marco Chen --- src/mainboard/google/octopus/variants/garg/gpio.c | 1 + .../google/octopus/variants/garg/include/variant/sku.h | 2 ++ src/mainboard/google/octopus/variants/garg/variant.c | 1 + 3 files changed, 4 insertions(+) diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 0fc0487a59..21f7903e92 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -66,6 +66,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) switch (sku_id) { case SKU_9_HDMI: case SKU_19_HDMI_TS: + case SKU_50_HDMI: *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; case SKU_17_LTE: diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index bfe7615195..1946a77425 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -13,6 +13,8 @@ enum { SKU_20_2A2C_TS = 20, SKU_37_2A2C_360 = 37, SKU_38_2A2C_360_TS_NO_STYLUES = 38, + SKU_49_2A2C_TS = 49, + SKU_50_HDMI = 50, }; #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 29796b76d6..5c92035c42 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -47,6 +47,7 @@ const char *mainboard_vbt_filename(void) switch (sku_id) { case SKU_9_HDMI: case SKU_19_HDMI_TS: + case SKU_50_HDMI: return "vbt_garg_hdmi.bin"; default: return "vbt.bin"; From 8939d28f16fc57b109a3172bfd277c411be1ebfd Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 22 Apr 2020 09:43:58 -0700 Subject: [PATCH 1249/1463] mb/google/volteer: Include TCSS power management Include TCSS RTD3 into ACPI DSDT table. BUG=b:140290596 TEST=Booted to kernel and verified tcss xhci/pcierp/dma power state D3 entry/exit. Change-Id: Iae31a29eb23f7370737d097dd401f4056b8b7052 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/40616 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/volteer/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 450835db03..e2dcaef3f1 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -31,6 +31,7 @@ DefinitionBlock( { #include #include + #include } /* Mainboard hooks */ #include "mainboard.asl" From 4e300cc780aada423b58af4aaeae457fa34ff741 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 22 Apr 2020 09:23:48 -0700 Subject: [PATCH 1250/1463] mb/intel/tigerlake: Include TCSS power management Include TCSS RTD3 into ACPI DSDT table. BUG=b:140290596 TEST=Booted to kernel and verified tcss xhci/pcierp/dma power state D3 entry/exit. Change-Id: I8cc5cfb572e15121059eb1fba41f931c59afbdf6 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/40615 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/intel/tglrvp/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index af13d9f5c1..080072d4e0 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -27,6 +27,7 @@ DefinitionBlock( { #include #include + #include } } From d7a6d61d51ebf4025484e567a20b2b50fda5a6f9 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 24 Apr 2020 10:24:04 -0700 Subject: [PATCH 1251/1463] device/pci_id: Add Tiger Lake TCSS device ID Add Tiger Lake TCSS USB xHCI, xDCI and Thunderbolt DMA device ID. BUG=None TEST=Built and booted image sucessfully. Change-Id: Idef3850666c9f393181e0a13974b9ad79ba258ad Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/40693 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Nick Vaccaro --- src/include/device/pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index cfdcab350c..4b17567a30 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3559,6 +3559,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI 0x9a13 #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded @@ -3644,6 +3645,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee #define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI 0x9a15 #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e #define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee @@ -3669,6 +3671,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 From 577db029a02306fcdcb873f7a01f78b19d47da91 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 24 Apr 2020 15:52:04 -0700 Subject: [PATCH 1252/1463] soc/amd/picasso: Enable secure debug unlock conditionally This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which when enabled includes secure debug unlock blobs and sets the required softfuses and options for amdfwtool. By default this is set to 'N'. BUG=b:154880818 Signed-off-by: Furquan Shaikh Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Kconfig | 6 ++++++ src/soc/amd/picasso/Makefile.inc | 11 +++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a37f5430ed..fa053f98cc 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -357,6 +357,12 @@ config PSP_WHITELIST_FILE depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin" +config PSP_UNLOCK_SECURE_DEBUG + bool "Unlock secure debug" + default n + help + Select this item to enable secure debug options in PSP. + endmenu endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d7cf9c052c..4790ecb502 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -109,19 +109,21 @@ PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # type = 0x9 PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin +# type = 0x13 +PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin # Enable secure debug unlock PSP_SOFTFUSE_BITS += 0 +PSP_TOKEN_UNLOCK="--token-unlock" +endif ifeq ($(CONFIG_USE_PSPSCUREOS),y) # types = 0x2 PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin endif -# type = 0x13 -PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin - # type = 0x21 PSP_IKEK_FILE=$(top)/$(FIRMWARE_LOCATE)/PspIkekRV.bin @@ -228,6 +230,7 @@ OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogra OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) +OPT_TOKEN_UNLOCK=$(call add_opt_prefix, $(PSP_TOKEN_UNLOCK), "") OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) @@ -367,7 +370,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ --combo-capable \ - --token-unlock \ + $(OPT_TOKEN_UNLOCK) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ From 6ba3a0758f7162834378e5845ea3a65fe327012c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 24 Apr 2020 17:42:19 +0200 Subject: [PATCH 1253/1463] nb/intel/haswell/pei_data.h: Add ULT system type Looks like 5 is a valid system type, as Google Beltino and Slippy are using it. According to comments on these mainboards' code, this value corresponds to ULT systems. So, add it to the comment on the pei_data struct, which was likely copied from Sandy Bridge and was not updated. Change-Id: I3654bb6022839dba3e1499cf43e8beaa97d1def1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40692 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/northbridge/intel/haswell/pei_data.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 17b7c182fa..643b830c24 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -81,7 +81,8 @@ struct pei_data uint32_t pmbase; uint32_t gpiobase; uint32_t temp_mmio_base; - uint32_t system_type; // 0 Mobile, 1 Desktop/Server + /* System type: 0 => Mobile, 1 => Desktop/Server, 5 => ULT, Others => Reserved */ + uint32_t system_type; uint32_t tseg_size; uint8_t spd_addresses[4]; int boot_mode; From 26afd648a1969df55a5786a2c877eec5144400ae Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 21 Apr 2020 15:50:04 +0800 Subject: [PATCH 1254/1463] soc/intel/tigerlake: Check SPD is not NULL before print Check SPD is not NULL before print. This can prevent the system from hanging up. BUG=b:154445630 TEST=Check NULL SPD is not print. Signed-off-by: Eric Lai Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40560 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/meminit.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index ebadcffe84..231e261968 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -315,8 +315,13 @@ static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) get_spd_smbus(blk); + /* + * SPD gets printed only if: + * a) mainboard provides a non-zero SMBus address and + * b) SPD is successfully read using the SMBus address + */ for (i = 0; i < ARRAY_SIZE(blk->addr_map); i++) { - if (blk->addr_map[i]) + if (blk->spd_array[i] != NULL) print_spd_info((uint8_t *)blk->spd_array[i]); } } From 6f028e7993aaca3a7557f096fa36c0b848e42016 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 29 Apr 2020 15:35:17 -0700 Subject: [PATCH 1255/1463] sc7180: Increase SPI flash frequency to 37.5MHz It seems that all SC7180 boards we have can well handle 37.5MHz of SPI flash speed, so bump that up from the current 25MHz so that we don't leave boot speed on the table. (The next step would be 50MHz which currently doesn't work on all boards so we're not going there yet.) BUG=b:117440651 Signed-off-by: Julius Werner Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40874 Tested-by: build bot (Jenkins) Reviewed-by: Philip Chen --- src/soc/qualcomm/sc7180/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 9cecb4f4f5..d860c4a5fd 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -22,6 +22,6 @@ void bootblock_soc_init(void) { sc7180_mmu_init(); clock_init(); - quadspi_init(25 * MHz); + quadspi_init(37500 * KHz); qupv3_fw_init(); } From 6c1a669b444fc7e6d7542ff910deca1a606d4c29 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 29 Apr 2020 17:36:12 -0700 Subject: [PATCH 1256/1463] libpayload: xhci: Do not memcpy registers memcpy() is meant to be used on normal memory and often implemented with architecture-specific optimizations to make that as performant as possible. MMIO registers often have special access restrictions that may be incompatible with whatever memcpy() does. For example, on arm64 it uses the LDP (load pair) to load 16 bytes at a time, which makes 4-byte MMIO registers unhappy. This patch removes the caching of the XHCI capreg registers and changes it back to a pointer. The CAP_GET() macro is still accessing a full (non-bitfield) uint32_t at the end so this should still generate a 4-byte access (which was the goal of the original change in CB:39838). Signed-off-by: Julius Werner Change-Id: Id058c8813087a8e8cb85f570399e07fb8a597108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40895 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- payloads/libpayload/drivers/usb/xhci.c | 10 +++++----- payloads/libpayload/drivers/usb/xhci_private.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 2f61f8658a..ef1d73ff68 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -185,15 +185,15 @@ xhci_init (unsigned long physical_bar) goto _free_xhci; } - memcpy(&xhci->capreg, phys_to_virt(physical_bar), sizeof(xhci->capreg)); + xhci->capreg = phys_to_virt(physical_bar) + sizeof(xhci->capreg); xhci->opreg = phys_to_virt(physical_bar) + CAP_GET(CAPLEN, xhci->capreg); - xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg.rtsoff; - xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg.dboff; + xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg->rtsoff; + xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg->dboff; xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar); xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg)); - xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg.rtsoff); - xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg.dboff); + xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff); + xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff); xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n", CAP_GET(CAPVER_HI, xhci->capreg), CAP_GET(CAPVER_LO, xhci->capreg)); diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 65c3fdd6cc..0264f1f218 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -364,7 +364,7 @@ typedef struct erst_entry { #define CAP_CSZ_LEN 1 #define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN) -#define CAP_GET(tok, cap) (((cap).CAP_##tok##_FIELD & CAP_MASK(tok)) \ +#define CAP_GET(tok, cap) (((cap)->CAP_##tok##_FIELD & CAP_MASK(tok)) \ >> CAP_##tok##_START) #define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32) @@ -378,7 +378,7 @@ typedef struct xhci { u32 hccparams; u32 dboff; u32 rtsoff; - } __packed capreg; + } __packed *capreg; /* opreg is R/W is most places, so volatile access is necessary. volatile means that the compiler seeks byte writes if possible, From a932f6e507e1e77755c9670f0ee6aaf77ca5d83c Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Thu, 23 Apr 2020 15:48:17 +0800 Subject: [PATCH 1257/1463] mb/google/puff: update USB2 strength Based on USB SI report to fine tune the strength for USB2 port0. BRANCH=none BUG=b:153590143 TEST=build and test USB2 port0 function works fine. Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4 Signed-off-by: Tim Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Edward O'Callaghan --- .../google/hatch/variants/duffy/overridetree.cb | 9 ++++++++- .../google/hatch/variants/kaisa/overridetree.cb | 9 ++++++++- src/mainboard/google/hatch/variants/puff/overridetree.cb | 9 ++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index ade12c5806..d7acbd71e7 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -21,7 +21,14 @@ chip soc/intel/cannonlake }" # USB configuration - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "{ .enable = 1, .ocpin = OC1, diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index e2380f4460..f5e85bde23 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -21,7 +21,14 @@ chip soc/intel/cannonlake }" # USB configuration - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "{ .enable = 1, .ocpin = OC1, diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d869b28a33..31efc4a1d9 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -24,7 +24,14 @@ chip soc/intel/cannonlake # NOTE: This only applies to Puff, # usb2_ports[1] and usb2_ports[3] were swapped on # reference schematics after Puff has been built. - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[2]" = "{ .enable = 1, From c7f473642a35a18a014e57290e462e23d3771056 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 25 Jan 2019 03:44:20 +0100 Subject: [PATCH 1258/1463] payloads/ipxe: Enable HTTPS support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Signed-off-by: Felix Singer Signed-off-by: Piotr Król Signed-off-by: Krystian Hebel Reviewed-on: https://review.coreboot.org/c/coreboot/+/31086 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- payloads/external/Makefile.inc | 1 + payloads/external/iPXE/Kconfig | 8 ++++++++ payloads/external/iPXE/Makefile | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 0a96aff90b..7319a11a6d 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -263,6 +263,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT) CONFIG_SCRIPT=$(PXE_CONFIG_SCRIPT) \ CONFIG_HAS_SCRIPT=$(CONFIG_PXE_ADD_SCRIPT) \ CONFIG_PXE_NO_PROMT=$(CONFIG_PXE_NO_PROMT) \ + CONFIG_PXE_HAS_HTTPS=$(CONFIG_PXE_HAS_HTTPS) \ MFLAGS= MAKEFLAGS= # LinuxBoot diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index 7cb0d1e249..1636138039 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -113,5 +113,13 @@ config PXE_SCRIPT Uses the ipxe script instead showing the prompt: "Press Ctrl-B to start iPXE..." +config PXE_HAS_HTTPS + bool "Enable HTTPS protocol" + default y + depends on BUILD_IPXE + help + Enable HTTPS protocol, which allows you to encrypt all communication + with a web server and to verify the server's identity + endmenu endif diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 0c071fa13b..489bcfae9c 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -65,6 +65,10 @@ ifeq ($(CONFIG_PXE_NO_PROMT),y) sed 's|#define\s*BANNER_TIMEOUT.*|#define BANNER_TIMEOUT 0|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h" endif +ifeq ($(CONFIG_PXE_HAS_HTTPS),y) + sed 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" + mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h" +endif build: config $(CONFIG_SCRIPT) ifeq ($(CONFIG_HAS_SCRIPT),y) From 4cea00a64f6e2080556a63863d1b792654c01cd8 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 24 Apr 2020 16:13:07 +0800 Subject: [PATCH 1259/1463] mb/google/volteer: Create trondo variant Create the trondo variant of the volteer reference board by copying the template files to a new directory named for the variant. BUG=b:154678884 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TRONDO Change-Id: Ie4f9bfe4798e14f91c6cb439f5c5ab2b9ea52b51 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40686 Reviewed-by: Caveh Jalali Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 2 + src/mainboard/google/volteer/Kconfig.name | 4 ++ .../volteer/variants/trondo/Makefile.inc | 8 ++++ .../google/volteer/variants/trondo/gpio.c | 37 +++++++++++++++++++ .../variants/trondo/include/variant/ec.h | 9 +++++ .../variants/trondo/include/variant/gpio.h | 11 ++++++ .../volteer/variants/trondo/overridetree.cb | 4 ++ 7 files changed, 75 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/trondo/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/trondo/gpio.c create mode 100644 src/mainboard/google/volteer/variants/trondo/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h create mode 100644 src/mainboard/google/volteer/variants/trondo/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 641ece1253..de77633153 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -59,6 +59,7 @@ config MAINBOARD_PART_NUMBER default "Halvor" if BOARD_GOOGLE_HALVOR default "Malefor" if BOARD_GOOGLE_MALEFOR default "Ripto" if BOARD_GOOGLE_RIPTO + default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER config MAX_CPUS @@ -74,6 +75,7 @@ config VARIANT_DIR default "halvor" if BOARD_GOOGLE_HALVOR default "malefor" if BOARD_GOOGLE_MALEFOR default "ripto" if BOARD_GOOGLE_RIPTO + default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER config VARIANT_HAS_MIPI_CAMERA diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f7d0909583..5c674d85fd 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -13,6 +13,10 @@ config BOARD_GOOGLE_RIPTO select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA +config BOARD_GOOGLE_TRONDO + bool "-> Trondo" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/trondo/Makefile.inc b/src/mainboard/google/volteer/variants/trondo/Makefile.inc new file mode 100644 index 0000000000..a115fccb1f --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +SPD_SOURCES = + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/trondo/gpio.c b/src/mainboard/google/volteer/variants/trondo/gpio.c new file mode 100644 index 0000000000..6c4fb52f01 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/gpio.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/trondo/include/variant/ec.h b/src/mainboard/google/volteer/variants/trondo/include/variant/ec.h new file mode 100644 index 0000000000..33e79711f6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/include/variant/ec.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h b/src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h new file mode 100644 index 0000000000..55725ad59a --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb new file mode 100644 index 0000000000..75422d80bb --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/tigerlake + device domain 0 on + end +end From b8bfe142c6bbaf3674e9d0ff70b42ca32bcb4df4 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 21 Apr 2020 17:07:57 -0700 Subject: [PATCH 1260/1463] mb/google/voteer: Enable DevSlp for SATA port1 BUG=b:152893285 BRANCH=none TEST=Build and boot to OS volteer with Intel SATA and reboot from OS console Signed-off-by: Wonkyu Kim Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 12ae87afcd..b68966331c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -77,6 +77,7 @@ chip soc/intel/tigerlake register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, From 4e06c6eeb1179cf553c99eff6f2ae9888376fd67 Mon Sep 17 00:00:00 2001 From: BryantOu Date: Fri, 17 Apr 2020 01:41:35 -0700 Subject: [PATCH 1261/1463] mb/ocp/tiogapass: Implement port 80h direct to GPIO and init UART pins Enable aspeed's function that port 80h direct to GPIO for LED display, refer to section 9.4 Port 80h Direct to GPIO Guide of aspeed's Application Design Guide, also configure GPIO to UART for output serial console messages. Tested=Check if port 80h LED debug card can display POST codes at early stage, and serial console can see the related messages. Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7 Signed-off-by: BryantOu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40481 Reviewed-by: Patrick Rudolph Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/bootblock.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index d507422d30..67808ef72a 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -13,6 +14,8 @@ /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F static void enable_espi_lpc_io_windows(void) { @@ -54,6 +57,14 @@ void bootblock_mainboard_early_init(void) enable_espi_lpc_io_windows(); /* Configure appropriate physical port of SuperIO chip off BMC */ - const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); + aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH); + + /* Enable UART function pin */ + aspeed_enable_uart_pin(serial_dev); } From 00961676fd399252e6ef1178dcda8391085694e2 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 22 Apr 2020 22:31:36 +0000 Subject: [PATCH 1262/1463] Revert "soc/mediatek/mt8183: Force retraining memory if requested" This reverts commit 285975dbba8c7f3bbb9f9950e79a30bb983d5123. Reason for revert: VB2_RECOVERY_TRAIN_AND_REBOOT was never meant to have any special effect on memory training behavior. It was just supposed to be a "reboot automatically after reaching kernel verification" recovery reason. On x86 devices this was used to prime the separate recovery MRC cache in the factory (make sure it is initialized before shipping). This isn't used on Kukui anyway, but in order to make sure nobody copies this code and keep the behavior consistent between platforms, let's remove it. Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/40623 Reviewed-by: Furquan Shaikh Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/memory.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 53763fd557..aa8f7d201d 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -163,8 +163,7 @@ static void mt_mem_init_run(struct dramc_param_ops *dparam_ops) /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); - if (get_recovery_mode_retrain_switch() || - vboot_check_recovery_request() == VB2_RECOVERY_TRAIN_AND_REBOOT) { + if (get_recovery_mode_retrain_switch()) { printk(BIOS_WARNING, "Retrain memory in next boot\n"); /* Use 0xFF as erased flash data. */ memset(dparam, 0xff, sizeof(*dparam)); From 38206886e6bce457789c4ec93956e27a235fd862 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 28 Apr 2020 21:04:54 -0700 Subject: [PATCH 1263/1463] soc/amd/common/block/smbus: Include acpimmio_map.h in sm.c sm.c requires acpimmio_map.h for ACPIMMIO_* macros. This change includes acpimmio_map.h in sm.c Signed-off-by: Furquan Shaikh Change-Id: Ia049254fa389a76bcf6538c0449229b4d856086e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40821 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/smbus/sm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index cef5bbaa23..99b24ec6d3 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include From 73716d0e924080ea32274a265a8de04e009c3676 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 28 Apr 2020 21:06:17 -0700 Subject: [PATCH 1264/1463] soc/amd/picasso: Get rid of chip.h inclusion from southbridge.h southbridge.h does not really need chip.h. So, this change removes the inclusion of chip.h from it. Signed-off-by: Furquan Shaikh Change-Id: I09c87b975ecd5f7798da8dd858be0c729aef42de Reviewed-on: https://review.coreboot.org/c/coreboot/+/40822 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/southbridge.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a13424536e..cf1d124744 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -8,7 +8,6 @@ #include #include #include -#include "chip.h" /* * AcpiMmio Region From a0284db08df3e0150202fd1cfc8c2c675c19f4de Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 28 Apr 2020 18:45:20 -0700 Subject: [PATCH 1265/1463] soc/amd/picasso: Introduce enums for SPI read mode and speed This change adds enums for spi_read_mode and spi100_speed in preparation for adding these to chip.h in follow-up CLs. This makes it easier to reference what the mainboard is expected to set for these SPI configs. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that SPI configuration is correct for trembyle. Signed-off-by: Furquan Shaikh Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/southbridge.h | 54 ++++++++++++------- src/soc/amd/picasso/southbridge.c | 13 ++--- 2 files changed, 41 insertions(+), 26 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index cf1d124744..1ce7019526 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -243,15 +243,25 @@ #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) +enum spi_read_mode { + SPI_READ_MODE_NORMAL33M = 0, + /* 1 is reserved. */ + SPI_READ_MODE_DUAL112 = 2, + SPI_READ_MODE_QUAD114 = 3, + SPI_READ_MODE_DUAL122 = 4, + SPI_READ_MODE_QUAD144 = 5, + SPI_READ_MODE_NORMAL66M = 6, + SPI_READ_MODE_FAST_READ = 7, +}; +/* + * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for + * SpiReadMode. + */ #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -/* Nominal is 16.7MHz on older devices, 33MHz on newer */ -#define SPI_READ_MODE_NOM 0x00000000 -#define SPI_READ_MODE_DUAL112 ( BIT(29) ) -#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) -#define SPI_READ_MODE_DUAL122 (BIT(30) ) -#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) -#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) -#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) +#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) +#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ + SPI_READ_MODE_LOWER_BITS(x)) #define SPI_ACCESS_MAC_ROM_EN BIT(22) #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) @@ -264,16 +274,24 @@ /* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ #define SPI100_SPEED_CONFIG 0x22 -#define SPI_SPEED_66M (0x0) -#define SPI_SPEED_33M ( BIT(0)) -#define SPI_SPEED_22M ( BIT(1) ) -#define SPI_SPEED_16M ( BIT(1) | BIT(0)) -#define SPI_SPEED_100M (BIT(2) ) -#define SPI_SPEED_800K (BIT(2) | BIT(0)) -#define SPI_NORM_SPEED_NEW_SH 12 -#define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 -#define SPI_TPM_SPEED_NEW_SH 0 +enum spi100_speed { + SPI_SPEED_66M = 0, + SPI_SPEED_33M = 1, + SPI_SPEED_22M = 2, + SPI_SPEED_16M = 3, + SPI_SPEED_100M = 4, + SPI_SPEED_800K = 5, +}; + +#define SPI_SPEED_MASK 0xf +#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << (shift)) +#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) +#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) +#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) +#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) + +#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ + SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 6bedab0629..caf7171c94 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -214,11 +214,8 @@ static uintptr_t sb_init_spi_base(void) void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { uintptr_t base = sb_init_spi_base(); - write16((void *)(base + SPI100_SPEED_CONFIG), - (norm << SPI_NORM_SPEED_NEW_SH) | - (fast << SPI_FAST_SPEED_NEW_SH) | - (alt << SPI_ALT_SPEED_NEW_SH) | - (tpm << SPI_TPM_SPEED_NEW_SH)); + + write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); } @@ -233,9 +230,9 @@ void sb_disable_4dw_burst(void) void sb_read_mode(u32 mode) { uintptr_t base = sb_init_spi_base(); - write32((void *)(base + SPI_CNTRL0), - (read32((void *)(base + SPI_CNTRL0)) - & ~SPI_READ_MODE_MASK) | mode); + uint32_t val = (read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK); + + write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); } static void fch_smbus_init(void) From 173c7c459473d35ff10c2d99daa54cec940402a8 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 28 Apr 2020 18:55:59 -0700 Subject: [PATCH 1266/1463] soc/amd/picasso: Move SPI init calls into sb_spi_init() This change adds a helper sb_spi_init() that makes all the required calls for configuring SPI to ROM. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that SPI configuration is correct for trembyle. Signed-off-by: Furquan Shaikh Change-Id: Ic5b395a8d3bdab449c24b05d1b6b8777e128b5e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40824 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/southbridge.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index caf7171c94..c38f373a36 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -235,6 +235,20 @@ void sb_read_mode(u32 mode) write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); } +static void sb_spi_config_modes(void) +{ + sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, + SPI_SPEED_16M, SPI_SPEED_16M); +} + +static void sb_spi_init(void) +{ + lpc_enable_spi_prefetch(); + sb_init_spi_base(); + sb_disable_4dw_burst(); + sb_spi_config_modes(); +} + static void fch_smbus_init(void) { /* 400 kHz smbus speed. */ @@ -260,11 +274,7 @@ void fch_pre_init(void) if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80) && CONFIG(PICASSO_LPC_IOMUX)) lpc_enable_port80(); - lpc_enable_spi_prefetch(); - sb_init_spi_base(); - sb_disable_4dw_burst(); - sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, - SPI_SPEED_16M, SPI_SPEED_16M); + sb_spi_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); sb_enable_cf9_io(); From 69c2811acc685f1d46aff081583af039388f7aab Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 28 Apr 2020 18:57:52 -0700 Subject: [PATCH 1267/1463] soc/amd/picasso: Allow mainboard to configure SPI settings This change adds options to allow mainboard to configure SPI speed for different modes as well as the SPI read mode. BUG=b:153675510,b:147758054 BRANCH=trembyle-bringup TEST=Verified that SPI settings are configured correctly for trembyle. Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951 Signed-off-by: Furquan Shaikh Signed-off-by: Rob Barnes Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/chip.h | 16 ++++++++++++++++ src/soc/amd/picasso/southbridge.c | 8 ++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 4cc10ef945..edb1b69bb0 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -10,6 +10,7 @@ #include #include #include +#include #include struct soc_amd_picasso_config { @@ -70,6 +71,21 @@ struct soc_amd_picasso_config { uint8_t core_dldo_bypass; uint8_t min_soc_vid_offset; uint8_t aclk_dpm0_freq_400MHz; + + /* + * SPI config + * Default values if not overridden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + enum spi_read_mode spi_read_mode; + enum spi100_speed spi_normal_speed; + enum spi100_speed spi_fast_speed; + enum spi100_speed spi_altio_speed; + enum spi100_speed spi_tpm_speed; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index c38f373a36..4f25802141 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -23,6 +23,7 @@ #include #include #include +#include "chip.h" #define FCH_AOAC_UART_FOR_CONSOLE \ (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ @@ -237,8 +238,11 @@ void sb_read_mode(u32 mode) static void sb_spi_config_modes(void) { - sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, - SPI_SPEED_16M, SPI_SPEED_16M); + const struct soc_amd_picasso_config *cfg = config_of_soc(); + + sb_read_mode(cfg->spi_read_mode); + sb_set_spi100(cfg->spi_normal_speed, cfg->spi_fast_speed, cfg->spi_altio_speed, + cfg->spi_tpm_speed); } static void sb_spi_init(void) From 0eabe139e55e94bbd7c49f81248dd7eabdcf2a4b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 28 Apr 2020 21:57:07 -0700 Subject: [PATCH 1268/1463] soc/amd/picasso: Add support for em100 This change enables support for em100 for Picasso platform. Since em100 requires lower SPI speed, this change configures speed in all modes as 16MHz. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that em100 works fine on trembyle. Signed-off-by: Furquan Shaikh Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/southbridge.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fa053f98cc..5996cc632e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB select IOAPIC + select HAVE_EM100_SUPPORT select HAVE_USBDEBUG_OPTIONS select TSC_MONOTONIC_TIMER select SOC_AMD_COMMON_BLOCK_SPI diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 4f25802141..d37f143313 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -236,7 +236,7 @@ void sb_read_mode(u32 mode) write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); } -static void sb_spi_config_modes(void) +static void sb_spi_config_mb_modes(void) { const struct soc_amd_picasso_config *cfg = config_of_soc(); @@ -245,6 +245,20 @@ static void sb_spi_config_modes(void) cfg->spi_tpm_speed); } +static void sb_spi_config_em100_modes(void) +{ + sb_read_mode(SPI_READ_MODE_NORMAL33M); + sb_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +static void sb_spi_config_modes(void) +{ + if (CONFIG(EM100)) + sb_spi_config_em100_modes(); + else + sb_spi_config_mb_modes(); +} + static void sb_spi_init(void) { lpc_enable_spi_prefetch(); From fa0e8b5e92052a04d5d5e78c1db139ecdaf01d4e Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 27 Apr 2020 13:03:15 +0200 Subject: [PATCH 1269/1463] mb/purism/librem_bdw: Remove PS/2 keyboard driver selection Most payloads, like GRUB, SeaBIOS and Linux, are able to initialize the PS/2 keyboard themselves, so coreboot does not need to initialize it. Therefore, this option should not be hard-coded for the mainboard, and be left for the user to select. Change-Id: Iac835d2e7a3232f8e5c76f10984ae3f172f9c0ca Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/40750 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons --- src/mainboard/purism/librem_bdw/Kconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 7a8bc22459..d9747f52e0 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -21,11 +21,6 @@ config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -config DRIVERS_PS2_KEYBOARD - def_bool y - help - Default PS/2 Keyboard to enabled on this board. - config DRIVERS_UART_8250IO def_bool n help From 7fb6a6a6c9dff985d271d1a84d93081ab147f296 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 27 Apr 2020 13:07:09 +0200 Subject: [PATCH 1270/1463] mb/pcengines/apu1: Remove PS/2 keyboard driver configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 6aa8c5bc (drivers/pc80: Do not initialize PS2 keyboard by default), the Kconfig option `DRIVERS_PS2_KEYBOARD` already defaults to `n`. So, remove it here, as this option should be user selectable anyway depending on the payload. Change-Id: I3d08fb6bbb3e9d53fd2fed96f26679e8b1e73f8c Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/40751 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/pcengines/apu1/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index d25825eb38..bf58575b49 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -72,10 +72,6 @@ config SB800_AHCI_ROM bool default n -config DRIVERS_PS2_KEYBOARD - bool - default n - choice prompt "J19 pins 1-10" default APU1_PINMUX_OFF_C From 247d027a4fecb74385c4ddd91035d190d1a1b204 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 27 Apr 2020 13:12:23 +0200 Subject: [PATCH 1271/1463] mb/amd/padmelon: Remove PS/2 keyboard driver selection Most payloads, like GRUB, SeaBIOS and Linux, are able to initialize the PS/2 keyboard themselves, so coreboot does not need to initialize it. Therefore, this option should not be hard-coded for the mainboard, and be left for the user to select. Change-Id: Ibfb7efa22c525e60399afc198af6632330faaac3 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/40752 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/mainboard/amd/padmelon/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 98753cff6b..300a3006c0 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMD_APU_PKG_FP4 select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC - select DRIVERS_PS2_KEYBOARD select HAVE_ACPI_TABLES select GFXUMA select STONEYRIDGE_LEGACY_FREE From 98a47ac9b52cad2ec94204e6839e0bb8fdfb30f3 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 29 Apr 2020 15:29:27 -0500 Subject: [PATCH 1272/1463] payloads/tianocore: Fix check for custom bootsplash -n needs to check against a string, but if CONFIG_TIANOCORE_BOOTSPLASH_FILE is unset, then $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) evaluates to nothing and the check fails, leading the Makefile to try and copy a non- existant file/path. Change-Id: Iff717dd48748cff16f485bafaa91c7a225fb5bdb Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40860 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- payloads/external/tianocore/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 1dc368db7e..21bae758da 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -94,7 +94,7 @@ checktools: build: update checktools unset CC; $(MAKE) -C $(project_dir)/BaseTools echo " build $(project_name) $(TAG)" - if [ -n $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) ]; then \ + if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \ echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ /*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ From 04a2edf689f79ffeb540c3e39e8893e75d5efd7a Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 21:08:20 +0300 Subject: [PATCH 1273/1463] mb/intel/cedarisland_crb: use common driver to configure GPIO According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with vendors firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- .../intel/cedarisland_crb/bootblock.c | 4 + .../intel/cedarisland_crb/include/gpio.h | 543 ++++++++++++++++++ 2 files changed, 547 insertions(+) create mode 100644 src/mainboard/intel/cedarisland_crb/include/gpio.h diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c index ea82ecc73f..3be0f8bc10 100644 --- a/src/mainboard/intel/cedarisland_crb/bootblock.c +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -10,9 +10,13 @@ #include #include #include +#include "include/gpio.h" void bootblock_mainboard_early_init(void) { + /* Configure Lewisburg PCH GPIOs */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + /* Enable COM1 only */ pcr_write32(PID_DMI, 0x2770, 0); pcr_write32(PID_DMI, 0x2774, 1); diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h new file mode 100644 index 0000000000..6aca58d2eb --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -0,0 +1,543 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef CFG_PCH_GPIO_H +#define CFG_PCH_GPIO_H + +#include + +/* GPIO configuration table for C627 Lewisburg PCH */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - ESPI_ALERT1# */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010), + /* GPP_A1 - ESPI_IO0 */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000c00, 0x00003010), + /* GPP_A2 - ESPI_IO1 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000c02, 0x00003010), + /* GPP_A3 - ESPI_IO2 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000c00, 0x00003010), + /* GPP_A4 - ESPI_IO3 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000c00, 0x00003010), + /* GPP_A5 - ESPI_CS0# */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000e00, 0x00003010), + /* GPP_A6 - ESPI_CS1# */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000e00, 0x00000010), + /* GPP_A7 - ESPI_ALERT0# */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000d02, 0x00000010), + /* GPP_A8 - CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000400, 0x00000010), + /* GPP_A9 - ESPI_CLK */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000e00, 0x00001010), + /* GPP_A10 - CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000010), + /* GPP_A11 - GPIO */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + /* GPP_A12 - GPIO */ + _PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000), + /* GPP_A13 - GPIO */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x00000010), + /* GPP_A14 - ESPI_RESET# */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000e00, 0x00000010), + /* GPP_A15 - GPIO */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000100, 0x00000010), + /* GPP_A16 - GPIO */ + _PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x00000010), + /* GPP_A17 - GPIO */ + _PAD_CFG_STRUCT(GPP_A17, 0x04000100, 0x00000000), + /* GPP_A18 - GPIO */ + _PAD_CFG_STRUCT(GPP_A18, 0x04000100, 0x00000000), + /* GPP_A19 - RESERVED */ + /* GPP_A20 - GPIO */ + _PAD_CFG_STRUCT(GPP_A20, 0x04000100, 0x00000000), + /* GPP_A21 - GPIO */ + _PAD_CFG_STRUCT(GPP_A21, 0x04000100, 0x00000000), + /* GPP_A22 - GPIO */ + _PAD_CFG_STRUCT(GPP_A22, 0x04000100, 0x00000000), + /* GPP_A23 - GPIO */ + _PAD_CFG_STRUCT(GPP_A23, 0x04000100, 0x00000000), + + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - CORE_VID0 */ + _PAD_CFG_STRUCT(GPP_B0, 0x04000600, 0x00000000), + /* GPP_B1 - CORE_VID1 */ + _PAD_CFG_STRUCT(GPP_B1, 0x04000600, 0x00000000), + /* GPP_B2 - GPIO */ + _PAD_CFG_STRUCT(GPP_B2, 0x04000102, 0x00000000), + /* GPP_B3 - GPIO */ + _PAD_CFG_STRUCT(GPP_B3, 0x04000102, 0x00000000), + /* GPP_B4 - GPIO */ + _PAD_CFG_STRUCT(GPP_B4, 0x04000102, 0x00000000), + /* GPP_B5 - GPIO */ + _PAD_CFG_STRUCT(GPP_B5, 0x04000102, 0x00000000), + /* GPP_B6 - GPIO */ + _PAD_CFG_STRUCT(GPP_B6, 0x04000102, 0x00000000), + /* GPP_B7 - GPIO */ + _PAD_CFG_STRUCT(GPP_B7, 0x04000100, 0x00000000), + /* GPP_B8 - GPIO */ + _PAD_CFG_STRUCT(GPP_B8, 0x04000102, 0x00000000), + /* GPP_B9 - GPIO */ + _PAD_CFG_STRUCT(GPP_B9, 0x04000100, 0x00000000), + /* GPP_B10 - GPIO */ + _PAD_CFG_STRUCT(GPP_B10, 0x04000102, 0x00000000), + /* GPP_B11 - RESERVED */ + /* GPP_B12 - GPIO */ + _PAD_CFG_STRUCT(GPP_B12, 0x04000102, 0x00000000), + /* GPP_B13 - PLTRST# */ + _PAD_CFG_STRUCT(GPP_B13, 0x04000600, 0x00000000), + /* GPP_B14 - SPKR */ + _PAD_CFG_STRUCT(GPP_B14, 0x04000500, 0x00000000), + /* GPP_B15 - GPIO */ + _PAD_CFG_STRUCT(GPP_B15, 0x04000102, 0x00000000), + /* GPP_B16 - GPIO */ + _PAD_CFG_STRUCT(GPP_B16, 0x04000102, 0x00000000), + /* GPP_B17 - GPIO */ + _PAD_CFG_STRUCT(GPP_B17, 0x04000102, 0x00000000), + /* GPP_B18 - GPIO */ + _PAD_CFG_STRUCT(GPP_B18, 0x04000102, 0x00000000), + /* GPP_B19 - GPIO */ + _PAD_CFG_STRUCT(GPP_B19, 0x04000100, 0x00000000), + /* GPP_B20 - GPIO */ + _PAD_CFG_STRUCT(GPP_B20, 0x04000200, 0x00000000), + /* GPP_B21 - GPIO */ + _PAD_CFG_STRUCT(GPP_B21, 0x04000102, 0x00000000), + /* GPP_B22 - GPIO */ + _PAD_CFG_STRUCT(GPP_B22, 0x04000100, 0x00000000), + /* GPP_B23 - PCHHOT# */ + _PAD_CFG_STRUCT(GPP_B23, 0x04000a00, 0x00000000), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - SATAXPCIE3 */ + _PAD_CFG_STRUCT(GPP_F0, 0x04000502, 0x00000000), + /* GPP_F1 - SATAXPCIE4 */ + _PAD_CFG_STRUCT(GPP_F1, 0x04000502, 0x00000000), + /* GPP_F2 - SATAXPCIE5 */ + _PAD_CFG_STRUCT(GPP_F2, 0x04000502, 0x00000000), + /* GPP_F3 - SATAXPCIE6 */ + _PAD_CFG_STRUCT(GPP_F3, 0x04000502, 0x00000000), + /* GPP_F4 - SATAXPCIE7 */ + _PAD_CFG_STRUCT(GPP_F4, 0x04000502, 0x00000000), + /* GPP_F5 - GPIO */ + _PAD_CFG_STRUCT(GPP_F5, 0x04000102, 0x00000000), + /* GPP_F6 - GPIO */ + _PAD_CFG_STRUCT(GPP_F6, 0x04000200, 0x00000000), + /* GPP_F7 - GPIO */ + _PAD_CFG_STRUCT(GPP_F7, 0x04000200, 0x00000000), + /* GPP_F8 - GPIO */ + _PAD_CFG_STRUCT(GPP_F8, 0x04000200, 0x00000000), + /* GPP_F9 - GPIO */ + _PAD_CFG_STRUCT(GPP_F9, 0x04000102, 0x00000000), + /* GPP_F10 - SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F10, 0x04000600, 0x00000000), + /* GPP_F11 - SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F11, 0x04000600, 0x00000000), + /* GPP_F12 - SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F12, 0x04000600, 0x00000000), + /* GPP_F13 - SATA_SDATAOUT2 */ + _PAD_CFG_STRUCT(GPP_F13, 0x04000600, 0x00000000), + /* GPP_F14 - SSATA_LED# */ + _PAD_CFG_STRUCT(GPP_F14, 0x04000e00, 0x00000000), + /* GPP_F15 - USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F15, 0x04000502, 0x00000000), + /* GPP_F16 - USB_OC5# */ + _PAD_CFG_STRUCT(GPP_F16, 0x04000502, 0x00000000), + /* GPP_F17 - USB_OC6# */ + _PAD_CFG_STRUCT(GPP_F17, 0x04000502, 0x00000000), + /* GPP_F18 - USB_OC7# */ + _PAD_CFG_STRUCT(GPP_F18, 0x04000502, 0x00000000), + /* GPP_F19 - LAN_SMBCLK */ + _PAD_CFG_STRUCT(GPP_F19, 0x04000402, 0x00000000), + /* GPP_F20 - LAN_SMBDATA */ + _PAD_CFG_STRUCT(GPP_F20, 0x04000402, 0x00000000), + /* GPP_F21 - GPIO */ + _PAD_CFG_STRUCT(GPP_F21, 0x04000102, 0x00000000), + /* GPP_F22 - SSATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F22, 0x04000e00, 0x00000000), + /* GPP_F23 - SSATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F23, 0x04000e00, 0x00000000), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + /* GPP_C2 - GPIO */ + _PAD_CFG_STRUCT(GPP_C2, 0x00000102, 0x00000000), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + /* GPP_C5 - SML0ALERT# */ + _PAD_CFG_STRUCT(GPP_C5, 0x04000602, 0x00000000), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + /* GPP_C8 - GPIO */ + _PAD_CFG_STRUCT(GPP_C8, 0x04000102, 0x00000000), + /* GPP_C9 - GPIO */ + _PAD_CFG_STRUCT(GPP_C9, 0x04000100, 0x00000010), + /* GPP_C10 - GPIO */ + _PAD_CFG_STRUCT(GPP_C10, 0x04000000, 0x00000000), + /* GPP_C11 - GPIO */ + _PAD_CFG_STRUCT(GPP_C11, 0x04000102, 0x00000000), + /* GPP_C12 - GPIO */ + _PAD_CFG_STRUCT(GPP_C12, 0x04000102, 0x00000000), + /* GPP_C13 - GPIO */ + _PAD_CFG_STRUCT(GPP_C13, 0x04000100, 0x00000000), + /* GPP_C14 - GPIO */ + _PAD_CFG_STRUCT(GPP_C14, 0x04000102, 0x00000000), + /* GPP_C15 - GPIO */ + _PAD_CFG_STRUCT(GPP_C15, 0x04000102, 0x00000000), + /* GPP_C16 - GPIO */ + _PAD_CFG_STRUCT(GPP_C16, 0x04000102, 0x00000000), + /* GPP_C17 - GPIO */ + _PAD_CFG_STRUCT(GPP_C17, 0x04000102, 0x00000000), + /* GPP_C18 - GPIO */ + _PAD_CFG_STRUCT(GPP_C18, 0x04000102, 0x00000000), + /* GPP_C19 - GPIO */ + _PAD_CFG_STRUCT(GPP_C19, 0x04000200, 0x00000000), + /* GPP_C20 - RESERVED */ + /* GPP_C21 - GPIO */ + _PAD_CFG_STRUCT(GPP_C21, 0x04000200, 0x00000000), + /* GPP_C22 - GPIO */ + _PAD_CFG_STRUCT(GPP_C22, 0x04000102, 0x00000000), + /* GPP_C23 - GPIO */ + _PAD_CFG_STRUCT(GPP_C23, 0x04000102, 0x00000000), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + _PAD_CFG_STRUCT(GPP_D0, 0x04000100, 0x00000000), + /* GPP_D1 - GPIO */ + _PAD_CFG_STRUCT(GPP_D1, 0x04000200, 0x00000000), + /* GPP_D2 - GPIO */ + _PAD_CFG_STRUCT(GPP_D2, 0x04000200, 0x00000000), + /* GPP_D3 - GPIO */ + _PAD_CFG_STRUCT(GPP_D3, 0x04000100, 0x00000000), + /* GPP_D4 - GPIO */ + _PAD_CFG_STRUCT(GPP_D4, 0x04000201, 0x00000000), + /* GPP_D5 - GPIO */ + _PAD_CFG_STRUCT(GPP_D5, 0x04000102, 0x00000000), + /* GPP_D6 - GPIO */ + _PAD_CFG_STRUCT(GPP_D6, 0x04000100, 0x00000010), + /* GPP_D7 - GPIO */ + _PAD_CFG_STRUCT(GPP_D7, 0x04000100, 0x00000000), + /* GPP_D8 - GPIO */ + _PAD_CFG_STRUCT(GPP_D8, 0x04000100, 0x00000000), + /* GPP_D9 - GPIO */ + _PAD_CFG_STRUCT(GPP_D9, 0x04000102, 0x00000000), + /* GPP_D10 - SSATA_DEVSLP4 */ + _PAD_CFG_STRUCT(GPP_D10, 0x04000e00, 0x00000000), + /* GPP_D11 - GPIO */ + _PAD_CFG_STRUCT(GPP_D11, 0x04000102, 0x00000000), + /* GPP_D12 - SSATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_D12, 0x04000e00, 0x00000000), + /* GPP_D13 - SML0BCLK_IE */ + _PAD_CFG_STRUCT(GPP_D13, 0x04000c02, 0x00000000), + /* GPP_D14 - SML0BDATA_IE */ + _PAD_CFG_STRUCT(GPP_D14, 0x04000c02, 0x00000000), + /* GPP_D15 - SSATA_SDATAOUT0 */ + _PAD_CFG_STRUCT(GPP_D15, 0x04000e00, 0x00000000), + /* GPP_D16 - GPIO */ + _PAD_CFG_STRUCT(GPP_D16, 0x04000200, 0x00000000), + /* GPP_D17 - GPIO */ + _PAD_CFG_STRUCT(GPP_D17, 0x04000200, 0x00000000), + /* GPP_D18 - GPIO */ + _PAD_CFG_STRUCT(GPP_D18, 0x04000102, 0x00000000), + /* GPP_D19 - GPIO */ + _PAD_CFG_STRUCT(GPP_D19, 0x04000200, 0x00000000), + /* GPP_D20 - GPIO */ + _PAD_CFG_STRUCT(GPP_D20, 0x04000102, 0x00000000), + /* GPP_D21 - GPIO */ + _PAD_CFG_STRUCT(GPP_D21, 0x04000102, 0x00000000), + /* GPP_D22 - GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), + /* GPP_D23 - GPIO */ + _PAD_CFG_STRUCT(GPP_D23, 0x04000102, 0x00000000), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - SATAXPCIE0 */ + _PAD_CFG_STRUCT(GPP_E0, 0x04000502, 0x00000000), + /* GPP_E1 - SATAXPCIE1 */ + _PAD_CFG_STRUCT(GPP_E1, 0x04000502, 0x00000000), + /* GPP_E2 - SATAXPCIE2 */ + _PAD_CFG_STRUCT(GPP_E2, 0x04000502, 0x00000000), + /* GPP_E3 - CPU_GP0 */ + _PAD_CFG_STRUCT(GPP_E3, 0x04000502, 0x00000000), + /* GPP_E4 - GPIO */ + _PAD_CFG_STRUCT(GPP_E4, 0x04000102, 0x00000000), + /* GPP_E5 - GPIO */ + _PAD_CFG_STRUCT(GPP_E5, 0x04000102, 0x00000000), + /* GPP_E6 - GPIO */ + _PAD_CFG_STRUCT(GPP_E6, 0x04000100, 0x00000000), + /* GPP_E7 - GPIO */ + _PAD_CFG_STRUCT(GPP_E7, 0x40840102, 0x00000000), + /* GPP_E8 - SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E8, 0x04000600, 0x00000000), + /* GPP_E9 - USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E9, 0x04000502, 0x00000000), + /* GPP_E10 - USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E10, 0x04000502, 0x00000000), + /* GPP_E11 - USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E11, 0x04000502, 0x00000000), + /* GPP_E12 - USB_OC3# */ + _PAD_CFG_STRUCT(GPP_E12, 0x04000502, 0x00000000), + + /* ------- GPIO Community 2 ------- */ + /* -------- GPIO Group GPD -------- */ + /* GPD0 - RESERVED */ + /* GPD1 - ACPRESENT */ + _PAD_CFG_STRUCT(GPD1, 0x04000502, 0x00000000), + /* GPD2 - GBE_WAKE# */ + _PAD_CFG_STRUCT(GPD2, 0x04000502, 0x00000000), + /* GPD3 - PWRBTN# */ + _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + /* GPD4 - SLP_S3# */ + _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + /* GPD5 - SLP_S4# */ + _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + /* GPD6 - SLP_A# */ + _PAD_CFG_STRUCT(GPD6, 0x04000600, 0x00000000), + /* GPD7 - GPIO */ + _PAD_CFG_STRUCT(GPD7, 0x04000102, 0x00000000), + /* GPD8 - GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + /* GPD9 - GPIO */ + _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + /* GPD10 - SLP_S5# */ + _PAD_CFG_STRUCT(GPD10, 0x04000600, 0x00000000), + /* GPD11 - GBEPHY */ + _PAD_CFG_STRUCT(GPD11, 0x04000600, 0x00000000), + + /* ------- GPIO Community 3 ------- */ + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - LAN_TDO */ + _PAD_CFG_STRUCT(GPP_I0, 0x04000a00, 0x00000000), + /* GPP_I1 - LAN_TCK */ + _PAD_CFG_STRUCT(GPP_I1, 0x04000902, 0x00000000), + /* GPP_I2 - LAN_TMS */ + _PAD_CFG_STRUCT(GPP_I2, 0x04000902, 0x00000000), + /* GPP_I3 - LAN_TDI */ + _PAD_CFG_STRUCT(GPP_I3, 0x04000902, 0x00000000), + /* GPP_I4 - GPIO */ + _PAD_CFG_STRUCT(GPP_I4, 0x04000000, 0x00000000), + /* GPP_I5 - GPIO */ + _PAD_CFG_STRUCT(GPP_I5, 0x04000200, 0x00000000), + /* GPP_I6 - GPIO */ + _PAD_CFG_STRUCT(GPP_I6, 0x04000102, 0x00000000), + /* GPP_I7 - LAN_TRST_IN */ + _PAD_CFG_STRUCT(GPP_I7, 0x04000902, 0x00000000), + /* GPP_I8 - PCI_DIS */ + _PAD_CFG_STRUCT(GPP_I8, 0x04000900, 0x00000000), + /* GPP_I9 - LAN_DIS */ + _PAD_CFG_STRUCT(GPP_I9, 0x04000900, 0x00000000), + /* GPP_I10 - GPIO */ + _PAD_CFG_STRUCT(GPP_I10, 0x04000102, 0x00000000), + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_J ------- */ + /* GPP_J0 - GPIO */ + _PAD_CFG_STRUCT(GPP_J0, 0x04000200, 0x00000000), + /* GPP_J1 - GPIO */ + _PAD_CFG_STRUCT(GPP_J1, 0x04000200, 0x00000000), + /* GPP_J2 - GPIO */ + _PAD_CFG_STRUCT(GPP_J2, 0x04000200, 0x00000000), + /* GPP_J3 - GPIO */ + _PAD_CFG_STRUCT(GPP_J3, 0x04000200, 0x00000000), + /* GPP_J4 - GPIO */ + _PAD_CFG_STRUCT(GPP_J4, 0x04000200, 0x00000000), + /* GPP_J5 - GPIO */ + _PAD_CFG_STRUCT(GPP_J5, 0x04000200, 0x00000000), + /* GPP_J6 - GPIO */ + _PAD_CFG_STRUCT(GPP_J6, 0x04000200, 0x00000000), + /* GPP_J7 - GPIO */ + _PAD_CFG_STRUCT(GPP_J7, 0x04000200, 0x00000000), + /* GPP_J8 - GPIO */ + _PAD_CFG_STRUCT(GPP_J8, 0x04000200, 0x00000000), + /* GPP_J9 - GPIO */ + _PAD_CFG_STRUCT(GPP_J9, 0x04000200, 0x00000000), + /* GPP_J10 - GPIO */ + _PAD_CFG_STRUCT(GPP_J10, 0x04000200, 0x00000000), + /* GPP_J11 - GPIO */ + _PAD_CFG_STRUCT(GPP_J11, 0x04000200, 0x00000000), + /* GPP_J12 - GPIO */ + _PAD_CFG_STRUCT(GPP_J12, 0x04000200, 0x00000000), + /* GPP_J13 - GPIO */ + _PAD_CFG_STRUCT(GPP_J13, 0x04000000, 0x00000000), + /* GPP_J14 - GPIO */ + _PAD_CFG_STRUCT(GPP_J14, 0x04000200, 0x00000000), + /* GPP_J15 - GPIO */ + _PAD_CFG_STRUCT(GPP_J15, 0x04000000, 0x00000000), + /* GPP_J16 - GPIO */ + _PAD_CFG_STRUCT(GPP_J16, 0x04000200, 0x00000000), + /* GPP_J17 - GPIO */ + _PAD_CFG_STRUCT(GPP_J17, 0x04000102, 0x00000000), + /* GPP_J18 - GPIO */ + _PAD_CFG_STRUCT(GPP_J18, 0x04000200, 0x00000000), + /* GPP_J19 - GPIO */ + _PAD_CFG_STRUCT(GPP_J19, 0x04000102, 0x00000000), + /* GPP_J20 - GPIO */ + _PAD_CFG_STRUCT(GPP_J20, 0x04000200, 0x00000000), + /* GPP_J21 - GPIO */ + _PAD_CFG_STRUCT(GPP_J21, 0x04000102, 0x00000000), + /* GPP_J22 - GPIO */ + _PAD_CFG_STRUCT(GPP_J22, 0x04000200, 0x00000000), + /* GPP_J23 - GPIO */ + _PAD_CFG_STRUCT(GPP_J23, 0x04000102, 0x00000000), + + /* ------- GPIO Group GPP_K ------- */ + /* GPP_K0 - LAN_NCSI_CLK_IN */ + _PAD_CFG_STRUCT(GPP_K0, 0x04000402, 0x00000000), + /* GPP_K1 - LAN_NCSI_TXD0 */ + _PAD_CFG_STRUCT(GPP_K1, 0x04000502, 0x00000000), + /* GPP_K2 - LAN_NCSI_TXD1 */ + _PAD_CFG_STRUCT(GPP_K2, 0x04000502, 0x00000000), + /* GPP_K3 - LAN_NCSI_TX_EN */ + _PAD_CFG_STRUCT(GPP_K3, 0x04000502, 0x00000000), + /* GPP_K4 - LAN_NCSI_CRS_DV */ + _PAD_CFG_STRUCT(GPP_K4, 0x04000600, 0x00000000), + /* GPP_K5 - LAN_NCSI_RXD0 */ + _PAD_CFG_STRUCT(GPP_K5, 0x04000500, 0x00000000), + /* GPP_K6 - LAN_NCSI_RXD1 */ + _PAD_CFG_STRUCT(GPP_K6, 0x04000500, 0x00000000), + /* GPP_K7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_K7, 0x04000402, 0x00000000), + /* GPP_K8 - LAN_NCSI_ARB_IN */ + _PAD_CFG_STRUCT(GPP_K8, 0x04000500, 0x00000000), + /* GPP_K9 - LAN_NCSI_ARB_OUT */ + _PAD_CFG_STRUCT(GPP_K9, 0x04000602, 0x00000000), + /* GPP_K10 - PE_RST# */ + _PAD_CFG_STRUCT(GPP_K10, 0x04000502, 0x00000000), + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_G ------- */ + /* GPP_G0 - GPIO */ + _PAD_CFG_STRUCT(GPP_G0, 0x04000102, 0x00000000), + /* GPP_G1 - GPIO */ + _PAD_CFG_STRUCT(GPP_G1, 0x04000102, 0x00000000), + /* GPP_G2 - GPIO */ + _PAD_CFG_STRUCT(GPP_G2, 0x04000102, 0x00000000), + /* GPP_G3 - GPIO */ + _PAD_CFG_STRUCT(GPP_G3, 0x04000102, 0x00000000), + /* GPP_G4 - GPIO */ + _PAD_CFG_STRUCT(GPP_G4, 0x04000102, 0x00000000), + /* GPP_G5 - GPIO */ + _PAD_CFG_STRUCT(GPP_G5, 0x04000102, 0x00000000), + /* GPP_G6 - GPIO */ + _PAD_CFG_STRUCT(GPP_G6, 0x04000102, 0x00000000), + /* GPP_G7 - GPIO */ + _PAD_CFG_STRUCT(GPP_G7, 0x04000102, 0x00000000), + /* GPP_G8 - GPIO */ + _PAD_CFG_STRUCT(GPP_G8, 0x04000102, 0x00000000), + /* GPP_G9 - GPIO */ + _PAD_CFG_STRUCT(GPP_G9, 0x04000102, 0x00000000), + /* GPP_G10 - GPIO */ + _PAD_CFG_STRUCT(GPP_G10, 0x04000102, 0x00000000), + /* GPP_G11 - GPIO */ + _PAD_CFG_STRUCT(GPP_G11, 0x04000102, 0x00000000), + /* GPP_G12 - GPIO */ + _PAD_CFG_STRUCT(GPP_G12, 0x04000102, 0x00000000), + /* GPP_G13 - GPIO */ + _PAD_CFG_STRUCT(GPP_G13, 0x04000102, 0x00000000), + /* GPP_G14 - GPIO */ + _PAD_CFG_STRUCT(GPP_G14, 0x04000102, 0x00000000), + /* GPP_G15 - GPIO */ + _PAD_CFG_STRUCT(GPP_G15, 0x04000100, 0x00000000), + /* GPP_G16 - GPIO */ + _PAD_CFG_STRUCT(GPP_G16, 0x04000102, 0x00000000), + /* GPP_G17 - ADR_COMPLETE */ + _PAD_CFG_STRUCT(GPP_G17, 0x04000600, 0x00000000), + /* GPP_G18 - NMI# */ + _PAD_CFG_STRUCT(GPP_G18, 0x04000600, 0x00000000), + /* GPP_G19 - SMI# */ + _PAD_CFG_STRUCT(GPP_G19, 0x04000600, 0x00000000), + /* GPP_G20 - RESERVED */ + /* GPP_G21 - GPIO */ + _PAD_CFG_STRUCT(GPP_G21, 0x04000102, 0x00000000), + /* GPP_G22 - n/a */ + _PAD_CFG_STRUCT(GPP_G22, 0x04000e00, 0x00000000), + /* GPP_G23 - GPIO */ + _PAD_CFG_STRUCT(GPP_G23, 0x04000102, 0x00000000), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + _PAD_CFG_STRUCT(GPP_H0, 0x04000000, 0x00000000), + /* GPP_H1 - GPIO */ + _PAD_CFG_STRUCT(GPP_H1, 0x04000102, 0x00000000), + /* GPP_H2 - GPIO */ + _PAD_CFG_STRUCT(GPP_H2, 0x04000000, 0x00000000), + /* GPP_H3 - GPIO */ + _PAD_CFG_STRUCT(GPP_H3, 0x04000000, 0x00000000), + /* GPP_H4 - GPIO */ + _PAD_CFG_STRUCT(GPP_H4, 0x04000000, 0x00000000), + /* GPP_H5 - RESERVED */ + /* GPP_H6 - SRCCLKREQ12# */ + _PAD_CFG_STRUCT(GPP_H6, 0x04000502, 0x00000000), + /* GPP_H7 - GPIO */ + _PAD_CFG_STRUCT(GPP_H7, 0x04000000, 0x00000000), + /* GPP_H8 - SRCCLKREQ14# */ + _PAD_CFG_STRUCT(GPP_H8, 0x04000500, 0x00000000), + /* GPP_H9 - GPIO */ + _PAD_CFG_STRUCT(GPP_H9, 0x04000000, 0x00000000), + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + /* GPP_H12 - GPIO */ + _PAD_CFG_STRUCT(GPP_H12, 0x04000102, 0x00000000), + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + /* GPP_H15 - GPIO */ + _PAD_CFG_STRUCT(GPP_H15, 0x04000102, 0x00000000), + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + /* GPP_H18 - GPIO */ + _PAD_CFG_STRUCT(GPP_H18, 0x04000102, 0x00000000), + /* GPP_H19 - GPIO */ + _PAD_CFG_STRUCT(GPP_H19, 0x04000200, 0x00000000), + /* GPP_H20 - SSATAXPCIE2 */ + _PAD_CFG_STRUCT(GPP_H20, 0x04000902, 0x00000000), + /* GPP_H21 - GPIO */ + _PAD_CFG_STRUCT(GPP_H21, 0x04000200, 0x00000000), + /* GPP_H22 - SSATAXPCIE4 */ + _PAD_CFG_STRUCT(GPP_H22, 0x04000902, 0x00000000), + /* GPP_H23 - GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x04000102, 0x00000000), + + /* ------- GPIO Group GPP_L ------- */ + /* GPP_L0 - RESERVED */ + /* GPP_L1 - CSME_INTR_OUT */ + _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + /* GPP_L2 - TESTCH0_D0 */ + _PAD_CFG_STRUCT(GPP_L2, 0x04000600, 0x00000000), + /* GPP_L3 - TESTCH0_D1 */ + _PAD_CFG_STRUCT(GPP_L3, 0x04000600, 0x00000000), + /* GPP_L4 - TESTCH0_D2 */ + _PAD_CFG_STRUCT(GPP_L4, 0x04000600, 0x00000000), + /* GPP_L5 - TESTCH0_D3 */ + _PAD_CFG_STRUCT(GPP_L5, 0x04000600, 0x00000000), + /* GPP_L6 - TESTCH0_D4 */ + _PAD_CFG_STRUCT(GPP_L6, 0x04000600, 0x00000000), + /* GPP_L7 - TESTCH0_D5 */ + _PAD_CFG_STRUCT(GPP_L7, 0x04000600, 0x00000000), + /* GPP_L8 - TESTCH0_D6 */ + _PAD_CFG_STRUCT(GPP_L8, 0x04000600, 0x00000000), + /* GPP_L9 - TESTCH0_D7 */ + _PAD_CFG_STRUCT(GPP_L9, 0x04000600, 0x00000000), + /* GPP_L10 - TESTCH0_CLK */ + _PAD_CFG_STRUCT(GPP_L10, 0x04000600, 0x00000000), + /* GPP_L11 - TESTCH1_D0 */ + _PAD_CFG_STRUCT(GPP_L11, 0x04000600, 0x00000000), + /* GPP_L12 - TESTCH1_D1 */ + _PAD_CFG_STRUCT(GPP_L12, 0x04000600, 0x00000000), + /* GPP_L13 - TESTCH1_D2 */ + _PAD_CFG_STRUCT(GPP_L13, 0x04000600, 0x00000000), + /* GPP_L14 - TESTCH1_D3 */ + _PAD_CFG_STRUCT(GPP_L14, 0x04000600, 0x00000000), + /* GPP_L15 - TESTCH1_D4 */ + _PAD_CFG_STRUCT(GPP_L15, 0x04000600, 0x00000000), + /* GPP_L16 - TESTCH1_D5 */ + _PAD_CFG_STRUCT(GPP_L16, 0x04000600, 0x00000000), + /* GPP_L17 - TESTCH1_D6 */ + _PAD_CFG_STRUCT(GPP_L17, 0x04000600, 0x00000000), + /* GPP_L18 - TESTCH1_D7 */ + _PAD_CFG_STRUCT(GPP_L18, 0x04000600, 0x00000000), + /* GPP_L19 - TESTCH1_CLK */ + _PAD_CFG_STRUCT(GPP_L19, 0x04000600, 0x00000000), +}; + +#endif /* CFG_PCH_GPIO_H */ From c00f74a82c7b6eb42c0e4c3ca7604f0947cf0691 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 21:14:21 +0300 Subject: [PATCH 1274/1463] mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M We should be sure that after romstage the pads will be configured according to the config from gpio.h only. This patch sets the GPIO configuration from gpio.h using the soc/intel/common/gpio.c driver again in ramstage. [1] https://review.coreboot.org/c/coreboot/+/40730 Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- src/mainboard/intel/cedarisland_crb/ramstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 src/mainboard/intel/cedarisland_crb/ramstage.c diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c new file mode 100644 index 0000000000..f4c716eda2 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* configure Lewisburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} From 5fcfbe14818e4a4cb1111c759e183195607e0a91 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 21:30:18 +0300 Subject: [PATCH 1275/1463] mb/cedarisland_crb: rework GPIOs configuration using macros This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736 Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- .../intel/cedarisland_crb/include/gpio.h | 510 +++++++++--------- 1 file changed, 270 insertions(+), 240 deletions(-) diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index 6aca58d2eb..f9a9825f24 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -11,533 +11,563 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - ESPI_ALERT1# */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF3, TX_DISABLE, OFF), /* GPP_A1 - ESPI_IO0 */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A2 - ESPI_IO1 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000c02, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A3 - ESPI_IO2 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A4 - ESPI_IO3 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A5 - ESPI_CS0# */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000e00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A5, 20K_PU, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A6 - ESPI_CS1# */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A7 - ESPI_ALERT0# */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000d02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF3, TX_DISABLE, OFF), /* GPP_A8 - CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000400, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A9 - ESPI_CLK */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000e00, 0x00001010), + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A10 - CLKOUT_LPC1 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A11 - GPIO */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ - _PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000), + PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), /* GPP_A13 - GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* GPP_A14 - ESPI_RESET# */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A15 - GPIO */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_A16, 1, DEEP), /* GPP_A17 - GPIO */ - _PAD_CFG_STRUCT(GPP_A17, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, RSMRST, OFF, ACPI), /* GPP_A18 - GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, RSMRST, OFF, ACPI), /* GPP_A19 - RESERVED */ /* GPP_A20 - GPIO */ - _PAD_CFG_STRUCT(GPP_A20, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, RSMRST, OFF, ACPI), /* GPP_A21 - GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, RSMRST, OFF, ACPI), /* GPP_A22 - GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, RSMRST, OFF, ACPI), /* GPP_A23 - GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B0, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B1 - CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B1, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B2 - GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI), /* GPP_B3 - GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, RSMRST, OFF, ACPI), /* GPP_B4 - GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, RSMRST, OFF, ACPI), /* GPP_B5 - GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, RSMRST, OFF, ACPI), /* GPP_B6 - GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, RSMRST, OFF, ACPI), /* GPP_B7 - GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, RSMRST, OFF, ACPI), /* GPP_B8 - GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, RSMRST, OFF, ACPI), /* GPP_B9 - GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, RSMRST, OFF, ACPI), /* GPP_B10 - GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, RSMRST, OFF, ACPI), /* GPP_B11 - RESERVED */ /* GPP_B12 - GPIO */ - _PAD_CFG_STRUCT(GPP_B12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, RSMRST, OFF, ACPI), /* GPP_B13 - PLTRST# */ - _PAD_CFG_STRUCT(GPP_B13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B14 - SPKR */ - _PAD_CFG_STRUCT(GPP_B14, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_B15 - GPIO */ - _PAD_CFG_STRUCT(GPP_B15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI), /* GPP_B16 - GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, RSMRST, OFF, ACPI), /* GPP_B17 - GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, RSMRST, OFF, ACPI), /* GPP_B18 - GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, RSMRST, OFF, ACPI), /* GPP_B19 - GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, RSMRST, OFF, ACPI), /* GPP_B20 - GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_B20, 0, RSMRST), /* GPP_B21 - GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, RSMRST, OFF, ACPI), /* GPP_B22 - GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, 0x04000a00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, OFF), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - SATAXPCIE3 */ - _PAD_CFG_STRUCT(GPP_F0, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F0, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F1 - SATAXPCIE4 */ - _PAD_CFG_STRUCT(GPP_F1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F2 - SATAXPCIE5 */ - _PAD_CFG_STRUCT(GPP_F2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F3 - SATAXPCIE6 */ - _PAD_CFG_STRUCT(GPP_F3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F4 - SATAXPCIE7 */ - _PAD_CFG_STRUCT(GPP_F4, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F4, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPP_F6 - GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F6, 0, RSMRST), /* GPP_F7 - GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* GPP_F8 - GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F8, 0, RSMRST), /* GPP_F9 - GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI), /* GPP_F10 - SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F11 - SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F12 - SATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_F12, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F13 - SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F14 - SSATA_LED# */ - _PAD_CFG_STRUCT(GPP_F14, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_F15 - USB_OC4# */ - _PAD_CFG_STRUCT(GPP_F15, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F16 - USB_OC5# */ - _PAD_CFG_STRUCT(GPP_F16, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F17 - USB_OC6# */ - _PAD_CFG_STRUCT(GPP_F17, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F18 - USB_OC7# */ - _PAD_CFG_STRUCT(GPP_F18, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F18, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F19 - LAN_SMBCLK */ - _PAD_CFG_STRUCT(GPP_F19, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_F20 - LAN_SMBDATA */ - _PAD_CFG_STRUCT(GPP_F20, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_F21 - GPIO */ - _PAD_CFG_STRUCT(GPP_F21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, RSMRST, OFF, ACPI), /* GPP_F22 - SSATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F22, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_F23 - SSATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F23, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - GPIO */ - _PAD_CFG_STRUCT(GPP_C2, 0x00000102, 0x00000000), + PAD_CFG_GPI(GPP_C2, NONE, RSMRST), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - SML0ALERT# */ - _PAD_CFG_STRUCT(GPP_C5, 0x04000602, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_C5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - _PAD_CFG_STRUCT(GPP_C8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, RSMRST, OFF, ACPI), /* GPP_C9 - GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x04000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, DRIVER), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_C11 - GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, RSMRST, OFF, ACPI), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, RSMRST, OFF, ACPI), /* GPP_C14 - GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, RSMRST, OFF, ACPI), /* GPP_C15 - GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, RSMRST, OFF, ACPI), /* GPP_C16 - GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, RSMRST, OFF, ACPI), /* GPP_C17 - GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, RSMRST, OFF, ACPI), /* GPP_C18 - GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, RSMRST, OFF, ACPI), /* GPP_C19 - GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_C19, 0, RSMRST), /* GPP_C20 - RESERVED */ /* GPP_C21 - GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_C21, 0, RSMRST), /* GPP_C22 - GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, RSMRST, OFF, ACPI), /* GPP_C23 - GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - _PAD_CFG_STRUCT(GPP_D0, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, RSMRST, OFF, ACPI), /* GPP_D1 - GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D1, 0, RSMRST), /* GPP_D2 - GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D2, 0, RSMRST), /* GPP_D3 - GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, RSMRST, OFF, ACPI), /* GPP_D4 - GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x04000201, 0x00000000), + PAD_CFG_GPO(GPP_D4, 1, RSMRST), /* GPP_D5 - GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, RSMRST, OFF, ACPI), /* GPP_D6 - GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x04000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, DRIVER), /* GPP_D7 - GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI), /* GPP_D8 - GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, RSMRST, OFF, ACPI), /* GPP_D9 - GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI), /* GPP_D10 - SSATA_DEVSLP4 */ - _PAD_CFG_STRUCT(GPP_D10, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D10, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D11 - GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, RSMRST, OFF, ACPI), /* GPP_D12 - SSATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_D12, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D12, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D13 - SML0BCLK_IE */ - _PAD_CFG_STRUCT(GPP_D13, 0x04000c02, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D13, NONE, RSMRST, NF3, NO_DISABLE, OFF), /* GPP_D14 - SML0BDATA_IE */ - _PAD_CFG_STRUCT(GPP_D14, 0x04000c02, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D14, NONE, RSMRST, NF3, NO_DISABLE, OFF), /* GPP_D15 - SSATA_SDATAOUT0 */ - _PAD_CFG_STRUCT(GPP_D15, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D16 - GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPP_D17 - GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D17, 0, RSMRST), /* GPP_D18 - GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, RSMRST, OFF, ACPI), /* GPP_D19 - GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D19, 0, RSMRST), /* GPP_D20 - GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, RSMRST, OFF, ACPI), /* GPP_D21 - GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, RSMRST, OFF, ACPI), /* GPP_D22 - GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), /* GPP_D23 - GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - _PAD_CFG_STRUCT(GPP_E0, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E1 - SATAXPCIE1 */ - _PAD_CFG_STRUCT(GPP_E1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E2 - SATAXPCIE2 */ - _PAD_CFG_STRUCT(GPP_E2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E3 - CPU_GP0 */ - _PAD_CFG_STRUCT(GPP_E3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E4 - GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, RSMRST, OFF, ACPI), /* GPP_E5 - GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, RSMRST, OFF, ACPI), /* GPP_E6 - GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, RSMRST, OFF, ACPI), /* GPP_E7 - GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x40840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT), /* GPP_E8 - SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E8, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_E9 - USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E9, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E10 - USB_OC1# */ - _PAD_CFG_STRUCT(GPP_E10, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E11 - USB_OC2# */ - _PAD_CFG_STRUCT(GPP_E11, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E12 - USB_OC3# */ - _PAD_CFG_STRUCT(GPP_E12, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - ACPRESENT */ - _PAD_CFG_STRUCT(GPD1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD2 - GBE_WAKE# */ - _PAD_CFG_STRUCT(GPD2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD3 - PWRBTN# */ - _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD4 - SLP_S3# */ - _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD5 - SLP_S4# */ - _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD6 - SLP_A# */ - _PAD_CFG_STRUCT(GPD6, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD6, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ - _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - SLP_S5# */ - _PAD_CFG_STRUCT(GPD10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD11 - GBEPHY */ - _PAD_CFG_STRUCT(GPD11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - _PAD_CFG_STRUCT(GPP_I0, 0x04000a00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, RSMRST, NF2, RX_DISABLE, OFF), /* GPP_I1 - LAN_TCK */ - _PAD_CFG_STRUCT(GPP_I1, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I2 - LAN_TMS */ - _PAD_CFG_STRUCT(GPP_I2, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I3 - LAN_TDI */ - _PAD_CFG_STRUCT(GPP_I3, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_I5 - GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_I5, 0, RSMRST), /* GPP_I6 - GPIO */ - _PAD_CFG_STRUCT(GPP_I6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI), /* GPP_I7 - LAN_TRST_IN */ - _PAD_CFG_STRUCT(GPP_I7, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I8 - PCI_DIS */ - _PAD_CFG_STRUCT(GPP_I8, 0x04000900, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I9 - LAN_DIS */ - _PAD_CFG_STRUCT(GPP_I9, 0x04000900, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I10 - GPIO */ - _PAD_CFG_STRUCT(GPP_I10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - GPIO */ - _PAD_CFG_STRUCT(GPP_J0, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J0, 0, RSMRST), /* GPP_J1 - GPIO */ - _PAD_CFG_STRUCT(GPP_J1, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J1, 0, RSMRST), /* GPP_J2 - GPIO */ - _PAD_CFG_STRUCT(GPP_J2, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J2, 0, RSMRST), /* GPP_J3 - GPIO */ - _PAD_CFG_STRUCT(GPP_J3, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J3, 0, RSMRST), /* GPP_J4 - GPIO */ - _PAD_CFG_STRUCT(GPP_J4, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J4, 0, RSMRST), /* GPP_J5 - GPIO */ - _PAD_CFG_STRUCT(GPP_J5, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J5, 0, RSMRST), /* GPP_J6 - GPIO */ - _PAD_CFG_STRUCT(GPP_J6, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J6, 0, RSMRST), /* GPP_J7 - GPIO */ - _PAD_CFG_STRUCT(GPP_J7, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J7, 0, RSMRST), /* GPP_J8 - GPIO */ - _PAD_CFG_STRUCT(GPP_J8, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J8, 0, RSMRST), /* GPP_J9 - GPIO */ - _PAD_CFG_STRUCT(GPP_J9, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J9, 0, RSMRST), /* GPP_J10 - GPIO */ - _PAD_CFG_STRUCT(GPP_J10, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J10, 0, RSMRST), /* GPP_J11 - GPIO */ - _PAD_CFG_STRUCT(GPP_J11, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J11, 0, RSMRST), /* GPP_J12 - GPIO */ - _PAD_CFG_STRUCT(GPP_J12, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J12, 0, RSMRST), /* GPP_J13 - GPIO */ - _PAD_CFG_STRUCT(GPP_J13, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_J13, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_J14 - GPIO */ - _PAD_CFG_STRUCT(GPP_J14, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J14, 0, RSMRST), /* GPP_J15 - GPIO */ - _PAD_CFG_STRUCT(GPP_J15, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_J15, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_J16 - GPIO */ - _PAD_CFG_STRUCT(GPP_J16, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J16, 0, RSMRST), /* GPP_J17 - GPIO */ - _PAD_CFG_STRUCT(GPP_J17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, RSMRST, OFF, ACPI), /* GPP_J18 - GPIO */ - _PAD_CFG_STRUCT(GPP_J18, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J18, 0, RSMRST), /* GPP_J19 - GPIO */ - _PAD_CFG_STRUCT(GPP_J19, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, RSMRST, OFF, ACPI), /* GPP_J20 - GPIO */ - _PAD_CFG_STRUCT(GPP_J20, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J20, 0, RSMRST), /* GPP_J21 - GPIO */ - _PAD_CFG_STRUCT(GPP_J21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, RSMRST, OFF, ACPI), /* GPP_J22 - GPIO */ - _PAD_CFG_STRUCT(GPP_J22, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J22, 0, RSMRST), /* GPP_J23 - GPIO */ - _PAD_CFG_STRUCT(GPP_J23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - LAN_NCSI_CLK_IN */ - _PAD_CFG_STRUCT(GPP_K0, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K0, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_K1 - LAN_NCSI_TXD0 */ - _PAD_CFG_STRUCT(GPP_K1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K2 - LAN_NCSI_TXD1 */ - _PAD_CFG_STRUCT(GPP_K2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K3 - LAN_NCSI_TX_EN */ - _PAD_CFG_STRUCT(GPP_K3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K4 - LAN_NCSI_CRS_DV */ - _PAD_CFG_STRUCT(GPP_K4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_K5 - LAN_NCSI_RXD0 */ - _PAD_CFG_STRUCT(GPP_K5, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K5, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K6 - LAN_NCSI_RXD1 */ - _PAD_CFG_STRUCT(GPP_K6, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K6, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K7 - RESERVED */ - _PAD_CFG_STRUCT(GPP_K7, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_K8 - LAN_NCSI_ARB_IN */ - _PAD_CFG_STRUCT(GPP_K8, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - _PAD_CFG_STRUCT(GPP_K9, 0x04000602, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_K10 - PE_RST# */ - _PAD_CFG_STRUCT(GPP_K10, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - _PAD_CFG_STRUCT(GPP_G0, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, RSMRST, OFF, ACPI), /* GPP_G1 - GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, RSMRST, OFF, ACPI), /* GPP_G2 - GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, RSMRST, OFF, ACPI), /* GPP_G3 - GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, RSMRST, OFF, ACPI), /* GPP_G4 - GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, RSMRST, OFF, ACPI), /* GPP_G5 - GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, RSMRST, OFF, ACPI), /* GPP_G6 - GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, RSMRST, OFF, ACPI), /* GPP_G7 - GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, RSMRST, OFF, ACPI), /* GPP_G8 - GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, RSMRST, OFF, ACPI), /* GPP_G9 - GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, RSMRST, OFF, ACPI), /* GPP_G10 - GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, RSMRST, OFF, ACPI), /* GPP_G11 - GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, RSMRST, OFF, ACPI), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, RSMRST, OFF, ACPI), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, RSMRST, OFF, ACPI), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, RSMRST, OFF, ACPI), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, RSMRST, OFF, ACPI), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI), /* GPP_G17 - ADR_COMPLETE */ - _PAD_CFG_STRUCT(GPP_G17, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ - _PAD_CFG_STRUCT(GPP_G18, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G19 - SMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI), /* GPP_G22 - n/a */ - _PAD_CFG_STRUCT(GPP_G22, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G22, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_G23 - GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H0, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H1 - GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H2, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ - _PAD_CFG_STRUCT(GPP_H6, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H6, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H7, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H8 - SRCCLKREQ14# */ - _PAD_CFG_STRUCT(GPP_H8, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H8, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H9, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ - _PAD_CFG_STRUCT(GPP_H12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, RSMRST, OFF, ACPI), /* GPP_H13 - RESERVED */ /* GPP_H14 - RESERVED */ /* GPP_H15 - GPIO */ - _PAD_CFG_STRUCT(GPP_H15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, RSMRST, OFF, ACPI), /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ /* GPP_H18 - GPIO */ - _PAD_CFG_STRUCT(GPP_H18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, RSMRST, OFF, ACPI), /* GPP_H19 - GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_H19, 0, RSMRST), /* GPP_H20 - SSATAXPCIE2 */ - _PAD_CFG_STRUCT(GPP_H20, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H20, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_H21 - GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_H21, 0, RSMRST), /* GPP_H22 - SSATAXPCIE4 */ - _PAD_CFG_STRUCT(GPP_H22, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H22, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_H23 - GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* GPP_L2 - TESTCH0_D0 */ - _PAD_CFG_STRUCT(GPP_L2, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L2, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L3 - TESTCH0_D1 */ - _PAD_CFG_STRUCT(GPP_L3, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L3, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L4 - TESTCH0_D2 */ - _PAD_CFG_STRUCT(GPP_L4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L5 - TESTCH0_D3 */ - _PAD_CFG_STRUCT(GPP_L5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L6 - TESTCH0_D4 */ - _PAD_CFG_STRUCT(GPP_L6, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L6, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L7 - TESTCH0_D5 */ - _PAD_CFG_STRUCT(GPP_L7, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L7, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L8 - TESTCH0_D6 */ - _PAD_CFG_STRUCT(GPP_L8, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L8, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L9 - TESTCH0_D7 */ - _PAD_CFG_STRUCT(GPP_L9, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L9, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L10 - TESTCH0_CLK */ - _PAD_CFG_STRUCT(GPP_L10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L11 - TESTCH1_D0 */ - _PAD_CFG_STRUCT(GPP_L11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L11, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L12 - TESTCH1_D1 */ - _PAD_CFG_STRUCT(GPP_L12, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L12, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L13 - TESTCH1_D2 */ - _PAD_CFG_STRUCT(GPP_L13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L14 - TESTCH1_D3 */ - _PAD_CFG_STRUCT(GPP_L14, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L14, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L15 - TESTCH1_D4 */ - _PAD_CFG_STRUCT(GPP_L15, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L15, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L16 - TESTCH1_D5 */ - _PAD_CFG_STRUCT(GPP_L16, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L16, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L17 - TESTCH1_D6 */ - _PAD_CFG_STRUCT(GPP_L17, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L17, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L18 - TESTCH1_D7 */ - _PAD_CFG_STRUCT(GPP_L18, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L18, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L19 - TESTCH1_CLK */ - _PAD_CFG_STRUCT(GPP_L19, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L19, NONE, RSMRST, NF1, RX_DISABLE, OFF), }; #endif /* CFG_PCH_GPIO_H */ From 3b9d995ecb99063adc2c79bb3c2e73de72499e01 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Fri, 27 Mar 2020 22:06:30 +0800 Subject: [PATCH 1276/1463] mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time Update UPD IIO bifurcation at run-time according to different Riser cards. For detail please reference Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types. With the engineering build FSP, it can only configure IIO for one socket so my local test needs to remove all socket1 elements from tp_iio_bifur_table. This change relies on [1] and need to add GPP_C15 and GPP_C16 to early_gpio_table for gpio configuration in bootblock. [1] https://review.coreboot.org/c/coreboot/+/39427/ Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/ocp/tiogapass/romstage.c | 23 +++++++++++++++++++++- src/mainboard/ocp/tiogapass/skxsp_tp_iio.h | 13 ++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 8f9806f250..e4a188d35d 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -16,10 +16,29 @@ #include #include #include +#include +#include +#include #include "skxsp_tp_gpio.h" #include "skxsp_tp_iio.h" +static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; + +static void oem_update_iio(FSPM_UPD *mupd) +{ + /* Read GPIO to decide IIO bifurcation at run-time. */ + int slot_config0 = gpio_get(GPP_C15); + int slot_config1 = gpio_get(GPP_C16); + + /* It's a single side 3 slots riser card, to tell which AICs are on each slot requires + reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation + accordingly is left for future work. */ + if (!slot_config0 && slot_config1) + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation + = IIO_BIFURCATE_xxx8xxx8; +} + /* * Configure GPIO depend on platform */ @@ -32,8 +51,9 @@ static void mainboard_config_gpios(FSPM_UPD *mupd) static void mainboard_config_iio(FSPM_UPD *mupd) { + memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table; + (UPD_IIO_BIFURCATION_DATA_ENTRY *) iio_table_buf; mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_bifur_table); @@ -49,6 +69,7 @@ static void mainboard_config_iio(FSPM_UPD *mupd) mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; + oem_update_iio(mupd); } void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h index 403702035c..d436e885a4 100644 --- a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h @@ -19,6 +19,19 @@ #include #include +enum tp_iio_bifur_table_index { + Skt0_Iou0 = 0, + Skt0_Iou1, + Skt0_Iou2, + Skt0_Mcp0, + Skt0_Mcp1, + Skt1_Iou0, + Skt1_Iou1, + Skt1_Iou2, + Skt1_Mcp0, + Skt1_Mcp1 +}; + /* * Standard Tioga Pass Iio Bifurcation Table * This is SS 2x16 config. As documented in OCP TP spec, there are From e0b7a88f586d746c72da1fedfbeda3156faf4d73 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 20 Apr 2020 13:43:29 -0600 Subject: [PATCH 1277/1463] soc/intel/jasperlake: Add support to generate ACPI GPIO operations Add support to generate ACPI operations to get/set/clear RX/TX GPIOs. BUG=b:152936541 TEST=Build and boot the mainboard. Ensure that there are no errors in the coreboot logs regarding unsupported ACPI GPIO operations. Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/jasperlake/acpi.c | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 4acd8a6131..b390968708 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -330,3 +330,40 @@ int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; } + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} From 24a65f8019e7b9b000bc8b7eb2947a07e6424293 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Thu, 23 Apr 2020 14:04:38 +0900 Subject: [PATCH 1278/1463] mb/google/nightfury: Tune the usb2_port[0] strength Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/nightfury/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 4b985d933e..2c759bc4bb 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -23,7 +23,7 @@ chip soc/intel/cannonlake # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" From fdbdca2ec3a3a28142791cd331fcf42da59e9d38 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Wed, 22 Apr 2020 13:50:46 +0800 Subject: [PATCH 1279/1463] mb/google/dedede: add new variant for wheelie Add initial support for wheelie variant board. BUG=b:154664137 BRANCH=None TEST=build Change-Id: Id638e987f45c247dae824f221a38ccf32626572f Signed-off-by: peichao.wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/40587 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/Kconfig | 2 + src/mainboard/google/dedede/Kconfig.name | 6 +++ .../dedede/variants/wheelie/Makefile.inc | 8 ++++ .../variants/wheelie/include/variant/ec.h | 13 +++++++ .../variants/wheelie/include/variant/gpio.h | 13 +++++++ .../dedede/variants/wheelie/overridetree.cb | 39 +++++++++++++++++++ 6 files changed, 81 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/wheelie/Makefile.inc create mode 100644 src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h create mode 100644 src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h create mode 100644 src/mainboard/google/dedede/variants/wheelie/overridetree.cb diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 1aabd0516e..37439084c0 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -55,6 +55,7 @@ config MAINBOARD_PART_NUMBER default "Dedede" if BOARD_GOOGLE_DEDEDE default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO default "Waddledee" if BOARD_GOOGLE_WADDLEDEE + default "Wheelie" if BOARD_GOOGLE_WHEELIE config MAX_CPUS int @@ -77,5 +78,6 @@ config VARIANT_DIR default "dedede" if BOARD_GOOGLE_DEDEDE default "waddledoo" if BOARD_GOOGLE_WADDLEDOO default "waddledee" if BOARD_GOOGLE_WADDLEDEE + default "wheelie" if BOARD_GOOGLE_WHEELIE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 36c2467055..cf9298cc96 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -17,3 +17,9 @@ config BOARD_GOOGLE_WADDLEDEE select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + +config BOARD_GOOGLE_WHEELIE + bool "Wheelie" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/dedede/variants/wheelie/Makefile.inc b/src/mainboard/google/dedede/variants/wheelie/Makefile.inc new file mode 100644 index 0000000000..13afb36de9 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/Makefile.inc @@ -0,0 +1,8 @@ +## +## This file is part of the coreboot project. +## +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h new file mode 100644 index 0000000000..70bd8e7785 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h @@ -0,0 +1,13 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h new file mode 100644 index 0000000000..fd92743190 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/wheelie/overridetree.cb b/src/mainboard/google/dedede/variants/wheelie/overridetree.cb new file mode 100644 index 0000000000..1e75864922 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/overridetree.cb @@ -0,0 +1,39 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on end +end From 2d7173d462c66cbbca6a5354c1ac719941e117d9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 23 Apr 2020 16:32:27 +0200 Subject: [PATCH 1280/1463] src: Remove unused 'include ' Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell_init.c | 1 - src/cpu/intel/haswell/smmrelocate.c | 1 - src/cpu/intel/smm/gen1/smmrelocate.c | 1 - src/cpu/qemu-x86/cache_as_ram_bootblock.S | 1 - src/cpu/x86/mtrr/earlymtrr.c | 1 - src/cpu/x86/smm/smihandler.c | 1 - src/cpu/x86/smm/smm_module_loader.c | 1 - src/drivers/amd/agesa/mtrr_fixme.c | 1 - src/drivers/intel/gma/intel_ddi.c | 1 - src/northbridge/intel/e7505/raminit.c | 1 - src/northbridge/intel/pineview/raminit.c | 1 - src/northbridge/intel/x4x/raminit.c | 1 - src/soc/intel/apollolake/cpu.c | 1 - src/soc/intel/baytrail/cpu.c | 1 - src/soc/intel/braswell/cpu.c | 1 - src/soc/intel/broadwell/bootblock/cpu.c | 1 - src/soc/intel/broadwell/cpu.c | 1 - src/soc/intel/broadwell/smi.c | 1 - src/soc/intel/broadwell/smmrelocate.c | 1 - src/soc/intel/cannonlake/smmrelocate.c | 1 - src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 1 - src/soc/intel/denverton_ns/cpu.c | 1 - src/soc/intel/icelake/smmrelocate.c | 1 - src/soc/intel/jasperlake/smmrelocate.c | 1 - src/soc/intel/quark/romstage/fsp_params.c | 1 - src/soc/intel/skylake/cpu.c | 1 - src/soc/intel/skylake/smmrelocate.c | 1 - src/soc/intel/tigerlake/smmrelocate.c | 1 - src/southbridge/intel/bd82x6x/smihandler.c | 1 - src/southbridge/intel/common/pmutil.c | 1 - src/southbridge/intel/common/smi.c | 1 - src/southbridge/intel/i82801ix/smihandler.c | 1 - src/southbridge/intel/i82801jx/smihandler.c | 1 - src/southbridge/intel/ibexpeak/smihandler.c | 1 - src/southbridge/intel/lynxpoint/smi.c | 1 - 35 files changed, 35 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index aab830f1c6..82c28bfc22 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 9ac991353d..cf3a8732b9 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 018a478c1c..d52bcbc485 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index baf87c8dd8..46ccc3d837 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include #include .global bootblock_pre_c_entry diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index e4003591f9..e8608fd9cc 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */ #include -#include #include #include diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bfbdfd2ce1..2e929d114f 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -3,7 +3,6 @@ #include #include -#include #include #include #include diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 7c23ef8e8e..bdcf2834ed 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 735f257102..7055233fcf 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index d52b2933c6..3a8fe50c32 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 8ed5007428..fd88193b91 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 18e1faa490..aea699e3a8 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include "pineview.h" diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index f1dc8817e6..797bc5a378 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index cd21fde048..73f5614852 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -18,7 +18,6 @@ #include #include "chip.h" #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d2a8e573b8..06728036bc 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index bb77742760..e3c1f1bd82 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 218232f263..9e6841093b 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index b630c0a58f..35df1b5960 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 6860f6f58e..95d45ea523 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index f5f83f6bcb..4adc28144b 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 782809769c..ce42767398 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 68d3e323ff..26c938b2b0 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 036a47a42b..ab90123dfa 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 365424e4e0..874ba32872 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index be3abdf4e1..78b0375806 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index ed362ea740..d555b344f6 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -6,7 +6,6 @@ #include #include #include "../chip.h" -#include #include #include #include diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index ad26c57958..5f2938c1e5 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 3d34616968..7db79a6c12 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index be3abdf4e1..78b0375806 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 78ac08bf1c..b2b635fcbc 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 5de5d41b5d..a471eefcb8 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -3,7 +3,6 @@ #include #include -#include #include #include #include diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 8f9544b892..f303ef4e93 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8a198487e8..928202103b 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -3,7 +3,6 @@ #include #include -#include #include #include #include diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 5c1edbc307..de9148e9ae 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -3,7 +3,6 @@ #include #include -#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a7c1e5feaf..05cd20fd88 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 05b5bb5c43..4c8ccfa0d1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "pch.h" From 7724f1142ee5c71c3df6c3a45af6d9da3f0798b5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 18 Mar 2020 12:19:14 -0700 Subject: [PATCH 1281/1463] lp/drivers/usb: Add quirk for QEMU XHCI root hub The QEMU XHCI driver does not implement the Port Change Detect bit in the USBSTS register. As a result no devices are attached without looking at each port individually. Detect this as a quirk based on the QEMU XHCI controller PCI ID, and apply it to the root hub quirk list so it can get used by the generic hub driver to skip this check. With this change an attached USB mass storage device is detected and able to boot when supplied to qemu: -drive if=none,id=usbmsc,format=raw,file=/tmp/disk.img -device qemu-xhci,id-xhci -device usb-storage,bus=xhci.0,drive=usbmsc Change-Id: I6689cb1dbb24c93d45f5c5ef040b713925d07588 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/39839 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/usb/generic_hub.c | 6 +++-- payloads/libpayload/drivers/usb/quirks.c | 24 +++++++++++++++++++ payloads/libpayload/drivers/usb/xhci.c | 4 ++++ payloads/libpayload/include/usb/usb.h | 2 ++ 4 files changed, 34 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/generic_hub.c b/payloads/libpayload/drivers/usb/generic_hub.c index 9d444ee792..7263400840 100644 --- a/payloads/libpayload/drivers/usb/generic_hub.c +++ b/payloads/libpayload/drivers/usb/generic_hub.c @@ -218,9 +218,11 @@ generic_hub_poll(usbdev_t *const dev) if (!hub) return; - if (hub->ops->hub_status_changed && - hub->ops->hub_status_changed(dev) != 1) + if (!(dev->quirks & USB_QUIRK_HUB_NO_USBSTS_PCD) && + hub->ops->hub_status_changed && + hub->ops->hub_status_changed(dev) != 1) { return; + } int port; for (port = 1; port <= hub->num_ports; ++port) { diff --git a/payloads/libpayload/drivers/usb/quirks.c b/payloads/libpayload/drivers/usb/quirks.c index 0a3514933c..d5be0e6cda 100644 --- a/payloads/libpayload/drivers/usb/quirks.c +++ b/payloads/libpayload/drivers/usb/quirks.c @@ -59,6 +59,30 @@ usb_quirks_t usb_quirks[] = { */ }; +#if CONFIG(LP_USB_PCI) +usb_quirks_t pci_quirks[] = { + /* QEMU XHCI root hub does not implement port change detect */ + { 0x1b36, 0x000d, USB_QUIRK_HUB_NO_USBSTS_PCD, 0 }, +}; + +u32 pci_quirk_check(pcidev_t controller) +{ + int i; + u16 vendor = pci_read_config16(controller, REG_VENDOR_ID); + u16 device = pci_read_config16(controller, REG_DEVICE_ID); + + for (i = 0; i < ARRAY_SIZE(pci_quirks); i++) { + if ((pci_quirks[i].vendor == vendor) && + (pci_quirks[i].device == device)) { + printf("PCI quirks enabled: %08x\n", pci_quirks[i].quirks); + return pci_quirks[i].quirks; + } + } + + return USB_QUIRK_NONE; +} +#endif + u32 usb_quirk_check(u16 vendor, u16 device) { int i; diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index ef1d73ff68..21af579f4c 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -314,9 +314,13 @@ xhci_pci_init (pcidev_t addr) controller = xhci_init((unsigned long)reg_addr); if (controller) { + xhci_t *xhci = controller->instance; controller->pcidev = addr; xhci_switch_ppt_ports(addr); + + /* Set up any quirks for controller root hub */ + xhci->roothub->quirks = pci_quirk_check(addr); } return controller; diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index 5d27f7cbc6..328e8839fc 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -318,6 +318,7 @@ void usb_detach_device(hci_t *controller, int devno); int usb_attach_device(hci_t *controller, int hubaddress, int port, usb_speed speed); +u32 pci_quirk_check(pcidev_t controller); u32 usb_quirk_check(u16 vendor, u16 device); int usb_interface_check(u16 vendor, u16 device); @@ -330,6 +331,7 @@ int usb_interface_check(u16 vendor, u16 device); #define USB_QUIRK_MSC_FORCE_TRANS_CBI_I (1 << 6) #define USB_QUIRK_MSC_NO_TEST_UNIT_READY (1 << 7) #define USB_QUIRK_MSC_SHORT_INQUIRY (1 << 8) +#define USB_QUIRK_HUB_NO_USBSTS_PCD (1 << 9) #define USB_QUIRK_TEST (1 << 31) #define USB_QUIRK_NONE 0 From c98f2eacfcf05cdf9d98f4b62733108a0a36cdbb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Apr 2020 16:38:32 +0200 Subject: [PATCH 1282/1463] sb/intel/common/{madt,rcba_pirq}.c: Convert to 96 characters line length Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40258 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/common/madt.c | 3 +-- src/southbridge/intel/common/rcba_pirq.c | 6 ++---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index 338527091d..d425a74366 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -11,8 +11,7 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 620d9fae41..e1da606cf5 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -16,8 +16,7 @@ static const u32 pirq_dir_route_reg[MAX_SLOT - MIN_SLOT + 1] = { D26IR, D27IR, D28IR, D29IR, D30IR, D31IR, }; -enum pirq intel_common_map_pirq(const struct device *dev, - const enum pci_pin pci_pin) +enum pirq intel_common_map_pirq(const struct device *dev, const enum pci_pin pci_pin) { u8 slot = PCI_SLOT(dev->path.pci.devfn); u8 shift = 4 * (pci_pin - PCI_INT_A); @@ -25,8 +24,7 @@ enum pirq intel_common_map_pirq(const struct device *dev, u16 reg; if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) { - printk(BIOS_ERR, - "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n", + printk(BIOS_ERR, "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n", slot, pci_pin); return PIRQ_NONE; } From 3c3a760513ac1b324051ab943f89d982a3105816 Mon Sep 17 00:00:00 2001 From: "Pandya, Varshit B" Date: Sat, 7 Mar 2020 00:36:30 +0530 Subject: [PATCH 1283/1463] mb/google/dedede: Add ACPI support for camera 1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI8856 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1 Signed-off-by: Pandya, Varshit B Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39360 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Karthik Ramasubramanian --- .../baseboard/include/baseboard/acpi/cam0.asl | 173 +++++++++++++++++ .../baseboard/include/baseboard/acpi/cam1.asl | 176 ++++++++++++++++++ .../include/baseboard/acpi/camera.asl | 7 + .../include/baseboard/acpi/ipu_endpoints.asl | 85 +++++++++ .../include/baseboard/acpi/ipu_mainboard.asl | 80 ++++++++ 5 files changed, 521 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl create mode 100644 src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl create mode 100644 src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl create mode 100644 src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl create mode 100644 src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl new file mode 100644 index 0000000000..ca40e91c67 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA0, Zero) + + /* Method to turn off Power Rails */ + Method (POFF, 0) + { + /* Disable PP1200 lane */ + CTXS(GPP_D14) + /* Disable PP2800 lane */ + CTXS(GPP_D13) + } + + Method (PON, 0) + { + /* Enable PP2800 lane */ + STXS(GPP_D13) + /* Enable PP1200 lane */ + STXS(GPP_D14) + } + + PowerResource (FCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(0, 1) /* Clock 0, 19.2MHz */ + IF(!STA1) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D15) + Sleep(5) /* 5 us */ + /* Deassert Reset */ + STXS(GPP_D15) + Sleep(5) /* 5 us */ + STA0 = 1 + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(0) /* Clock 0 */ + /* Assert Reset */ + CTXS(GPP_D15) + IF(!STA1) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA0 = 0 + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA0) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI9734") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 9734 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl new file mode 100644 index 0000000000..7cc9034e82 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA1, Zero) + + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(1, 1) /* Clock 1, 19.2MHz */ + /* Check if another sensor is ON */ + IF(!STA0) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D12) + Sleep(5) /* 5 us */ + /* DeAssert Reset */ + STXS(GPP_D12) + Sleep(5) /* 5 us */ + STA1 = 1 + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(1) /* Clock 1 */ + /* Assert Reset */ + CTXS(GPP_D12) + IF(!STA0) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA1 = 0 + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA1) + } + } + + Device(CAM1) + { + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x02) + { + 0x15752A00, + 0xABA9500 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl new file mode 100644 index 0000000000..fae8e5d1dd --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl new file mode 100644 index 0000000000..cff20e4688 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x01) + { + One, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl new file mode 100644 index 0000000000..9d294991de --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) /* _ADR: Address */ + + Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} From a02bf7468a5bb22f47be2aaf6186f2c835710fbc Mon Sep 17 00:00:00 2001 From: "Pandya, Varshit B" Date: Fri, 17 Apr 2020 12:12:34 +0530 Subject: [PATCH 1284/1463] mb/google/dedede: Enable camera support for waddledoo BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Signed-off-by: Pandya, Varshit B Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/Kconfig | 6 ++++++ src/mainboard/google/dedede/Kconfig.name | 1 + src/mainboard/google/dedede/dsdt.asl | 5 +++++ .../google/dedede/variants/baseboard/gpio.c | 12 ++++++------ .../waddledoo/include/variant/acpi/camera.asl | 4 ++++ 5 files changed, 22 insertions(+), 6 deletions(-) create mode 100644 src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 37439084c0..85dbc38ea4 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -80,4 +80,10 @@ config VARIANT_DIR default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE +config VARIANT_HAS_CAMERA_ACPI + bool + default n + help + Select this option to enable camera ACPI support on the variant. + endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index cf9298cc96..25ad61f6d8 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -11,6 +11,7 @@ config BOARD_GOOGLE_WADDLEDOO select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 98ef6e49cc..f7bb6b9090 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -34,6 +34,11 @@ DefinitionBlock( } } +#if CONFIG(VARIANT_HAS_CAMERA_ACPI) + /* Camera */ + #include +#endif + /* Chrome OS specific */ #include diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index a4ce97d8a5..b09d6c1abb 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -170,13 +170,13 @@ static const struct pad_config gpio_table[] = { /* D11 : GPP_D11/GSPI2_MOSI/UART0A_CTSB */ PAD_NC(GPP_D11, NONE), /* D12 : WCAM_RST_L */ - PAD_NC(GPP_D12, NONE), + PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* D13 : EN_PP2800_CAMERA */ - PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* D14 : EN_PP1200_CAMERA */ - PAD_NC(GPP_D14, NONE), + PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* D15 : UCAM_RST_L */ - PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* D16 : HP_INT_ODL */ PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), /* D17 : EN_SPK */ @@ -195,11 +195,11 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D23, NONE), /* E0 : CLK_24M_UCAM */ - PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), /* E1 : EMR_RESET_L */ PAD_NC(GPP_E1, NONE), /* E2 : CLK_24M_WCAM */ - PAD_NC(GPP_E2, NONE), + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* E3 : GPP_E3/SATA_0_DEVSLP */ PAD_NC(GPP_E3, NONE), /* E4 : IMGCLKOUT_2 */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl new file mode 100644 index 0000000000..304c0fe611 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include From f60a8f02c5d6eed7249a4e60c1d6df373d047eb0 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Mon, 20 Apr 2020 21:37:39 +0530 Subject: [PATCH 1285/1463] Helios: Update DPTF settings for smooth fan speed control Update DPTF settings for smooth fan speed control. BRANCH=firmware-hatch-12672.B BUG=b:154074920 TEST=Built and test on Helios system Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/40530 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../variants/helios/include/variant/acpi/dptf.asl | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index cf2d999e30..39d50c30d6 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -13,9 +13,12 @@ #define DPTF_TSR1_SENSOR_NAME "5V Regulator" #define DPTF_TSR1_PASSIVE 0 #define DPTF_TSR1_CRITICAL 70 -#define DPTF_TSR1_ACTIVE_AC0 42 -#define DPTF_TSR1_ACTIVE_AC1 41 -#define DPTF_TSR1_ACTIVE_AC2 39 +#define DPTF_TSR1_ACTIVE_AC0 43 +#define DPTF_TSR1_ACTIVE_AC1 42 +#define DPTF_TSR1_ACTIVE_AC2 41 +#define DPTF_TSR1_ACTIVE_AC3 40 +#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC5 38 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Ambient" @@ -73,7 +76,7 @@ Name (DART, Package () { 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 60, 50, 40, 30, 0, 0, 0, 0 }, Package () { From 8d09cf61860e743b35a9158163654c8d2bd3c189 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 20 Apr 2020 11:37:52 -0600 Subject: [PATCH 1286/1463] mb/google/dedede: Remove pad termination for RAM_STRAP_4 The stuffed resistor straps are weaker compared to the internal pull-up. This can cause the GPIO to read '1' always. Remove the internal pull-up. Also read the GPIO only on the boards where the board version is populated. BUG=b:154301008 TEST=Build and boot the mainboard. Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/romstage.c | 2 +- .../google/dedede/variants/baseboard/gpio.c | 4 ++-- .../baseboard/include/baseboard/variants.h | 7 ++++++ .../google/dedede/variants/baseboard/memory.c | 5 +++++ .../dedede/variants/waddledee/Makefile.inc | 2 ++ .../google/dedede/variants/waddledee/memory.c | 22 +++++++++++++++++++ .../dedede/variants/waddledoo/Makefile.inc | 2 ++ .../google/dedede/variants/waddledoo/memory.c | 22 +++++++++++++++++++ 8 files changed, 63 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/google/dedede/variants/waddledee/memory.c create mode 100644 src/mainboard/google/dedede/variants/waddledoo/memory.c diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 2efaaf17e7..7a700f4ff4 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -18,7 +18,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) .read_type = READ_SPD_CBFS, .spd_spec.spd_index = variant_memory_sku(), }; - bool half_populated = !gpio_get(GPIO_MEM_CH_SEL); + bool half_populated = variant_mem_is_half_populated(); memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index b09d6c1abb..6adb35ba9d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -348,7 +348,7 @@ static const struct pad_config gpio_table[] = { /* S0 : RAM_STRAP_4 */ - PAD_CFG_GPI(GPP_S0, UP_5K, DEEP), + PAD_CFG_GPI(GPP_S0, NONE, DEEP), /* S1 : RSVD_STRAP */ PAD_NC(GPP_S1, NONE), /* S2 : DMIC1_CLK */ @@ -418,7 +418,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_H19, 0, DEEP), /* S0 : RAM_STRAP_4 */ - PAD_CFG_GPI(GPP_S0, UP_5K, DEEP), + PAD_CFG_GPI(GPP_S0, NONE, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 8fd5119bd4..48c1419617 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -33,4 +33,11 @@ const struct mb_cfg *variant_memcfg_config(void); /* Return memory SKU for the variant */ int variant_memory_sku(void); +/** + * Get data whether memory channel is half-populated or not + * + * @return false on boards where memory channel is half-populated, true otherwise. + */ +bool variant_mem_is_half_populated(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index 08c3bde29f..120cb4e43e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -70,3 +70,8 @@ int __weak variant_memory_sku(void) return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } + +bool __weak variant_mem_is_half_populated(void) +{ + return !gpio_get(GPIO_MEM_CH_SEL); +} diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index fb9b4f45fc..d3d6452743 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -7,3 +7,5 @@ SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 SPD_SOURCES += empty #0b0001 + +romstage-y += memory.c diff --git a/src/mainboard/google/dedede/variants/waddledee/memory.c b/src/mainboard/google/dedede/variants/waddledee/memory.c new file mode 100644 index 0000000000..d1e8af2c59 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/memory.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +bool variant_mem_is_half_populated(void) +{ + uint32_t board_ver; + + /* On boards where board version is populated, ram strap is also populated */ + if (!google_chromeec_get_board_version(&board_ver)) + return !gpio_get(GPIO_MEM_CH_SEL); + + return false; +} diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 71042c0340..75cbb6a36d 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -7,3 +7,5 @@ SPD_SOURCES = empty #0b0000 SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 + +romstage-y += memory.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory.c b/src/mainboard/google/dedede/variants/waddledoo/memory.c new file mode 100644 index 0000000000..d1e8af2c59 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +bool variant_mem_is_half_populated(void) +{ + uint32_t board_ver; + + /* On boards where board version is populated, ram strap is also populated */ + if (!google_chromeec_get_board_version(&board_ver)) + return !gpio_get(GPIO_MEM_CH_SEL); + + return false; +} From c712144124764627644280e6341268e3dd7f67ab Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 10 Apr 2020 18:04:59 +0200 Subject: [PATCH 1287/1463] include/device/device.h: Include smbios_slot_{type,data_width,length,designation} used for smbios_type_9 needs "smbios.h" Also use already defined 'smbios_type11' in "smbios.h". This will also include in "static.c" file, this we can remove indirect includes of in "chip.h" Change-Id: Id412a504da2fd75648636febd150356569e07935 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40310 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/include/device/device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index c21067deeb..72df751054 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -5,6 +5,7 @@ #include #include #include +#include #include struct device; @@ -29,7 +30,6 @@ struct chip_operations { struct bus; -struct smbios_type11; struct acpi_rsdp; struct device_operations { From b8a0cd11c6cc509c122b09bafd911ce9c169d9c8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 25 Mar 2020 08:35:26 +0100 Subject: [PATCH 1288/1463] src: Remove not used 'include ' Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/drivers/i2c/at24rf08c/at24rf08c.c | 1 - src/drivers/intel/gma/intel_ddi.c | 1 - src/mainboard/google/volteer/mainboard.c | 1 - src/mainboard/packardbell/ms2290/mainboard.c | 1 - src/soc/intel/braswell/chip.h | 1 - src/soc/intel/cannonlake/chip.h | 1 - src/soc/intel/skylake/chip.h | 1 - 7 files changed, 7 deletions(-) diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 3511502b76..3890638b3d 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -4,7 +4,6 @@ #include #include #include -#include #include static void at24rf08c_init(struct device *dev) diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 3a8fe50c32..59d3010be1 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 4e9843ceae..0db43d1bed 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 8d4bb8e003..184401a0f7 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -9,7 +9,6 @@ #include #include #include -#include static void mainboard_enable(struct device *dev) { diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 76eb50e493..04c017ecc3 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -14,7 +14,6 @@ #include #include #include -#include #define SVID_CONFIG1 1 #define SVID_CONFIG3 3 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 578473b79b..b74291ebb3 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1b9cc4a177..892f26212b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -21,7 +21,6 @@ #include #include #include -#include #define MAX_PEG_PORTS 3 From 798fd4b69fb8102d66ac58b6f6bec7f8cd5ea9de Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Mon, 27 Apr 2020 22:40:03 +0530 Subject: [PATCH 1289/1463] soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar --- src/soc/intel/jasperlake/chip.h | 3 +++ src/soc/intel/jasperlake/fsp_params.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3983d03b84..a6932bc52c 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -110,6 +110,9 @@ struct soc_intel_jasperlake_config { * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ + uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 19b9300713..f525fd8af1 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -104,6 +104,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Enable ClkReqDetect for enabled port */ + memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, + sizeof(config->PcieRpClkReqDetect)); + /* USB configuration */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { From a15eaec1e6975d78687aaea06996464b5a67f14c Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Mon, 27 Apr 2020 22:53:40 +0530 Subject: [PATCH 1290/1463] mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree This CL selects the PcieRpClkReqDetect for the required root ports which is needed to allow proper clksrc gpio configuration. Also, sets the unused PcieClkSrcUsage to 0xFF. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Reviewed-by: Ronak Kanabar Reviewed-by: Maulik V Vaghela --- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index cb3d1f3598..1b5e256de7 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -67,8 +67,17 @@ chip soc/intel/jasperlake register "PcieRpEnable[1]" = "1" register "PcieRpEnable[4]" = "1" + # Enable ClkReqDetect 1 for WLAN + # Enable ClkReqDetect 4 for NVMe + register "PcieRpClkReqDetect[1]" = "1" + register "PcieRpClkReqDetect[4]" = "1" + register "PcieClkSrcUsage[0]" = "0x04" register "PcieClkSrcUsage[1]" = "0x01" + register "PcieClkSrcUsage[2]" = "0xFF" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcClkReq[0]" = "0x00" register "PcieClkSrcClkReq[1]" = "0x01" From b30d0545843b6ba3e8c0976a1fc0f1413be1608b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 09:42:47 +0200 Subject: [PATCH 1291/1463] soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/psp.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index 88bd61d4dd..5a4cd4dbab 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -12,7 +12,8 @@ void soc_enable_psp_early(void) { - u32 base, limit, cmd; + u32 base, limit; + u16 cmd; /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; @@ -25,9 +26,9 @@ void soc_enable_psp_early(void) pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND); cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); }; void *soc_get_mbox_address(void) From 7b2646536a773f181f766fe755403a242e9f3e8e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 09:46:42 +0200 Subject: [PATCH 1292/1463] util/intelmetool: Fix 16-bit read/write PCI_COMMAND register Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40790 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/intelmetool/me.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index ee2b46a317..e9aa510a10 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -574,7 +574,7 @@ int mkhi_debug_me_memory(void *physaddr) uint32_t intel_mei_setup(struct pci_dev *dev) { struct mei_csr host; - uint32_t reg32; + uint16_t reg16; uint32_t pagerounded; mei_base_address = dev->base_addr[0] & ~0xf; @@ -588,9 +588,9 @@ uint32_t intel_mei_setup(struct pci_dev *dev) } /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_long(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_long(dev, PCI_COMMAND, reg32); + reg16 = pci_read_word(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_word(dev, PCI_COMMAND, reg16); /* Clean up status for next message */ read_host_csr(&host); From 8b6dfdeb203c5e10c804398b822f85df2b4b6d26 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 09:58:21 +0200 Subject: [PATCH 1293/1463] sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register Change-Id: I212ef304a03d068232f50a71c318e2b468336339 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40791 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/ibexpeak/azalia.c | 3 +-- src/southbridge/intel/ibexpeak/me.c | 15 ++++++++------- src/southbridge/intel/ibexpeak/pch.c | 12 +++++------- src/southbridge/intel/ibexpeak/usb_ehci.c | 5 +---- 4 files changed, 15 insertions(+), 20 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index eb75b1200d..c57bd9a4da 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -262,8 +262,7 @@ static void azalia_init(struct device *dev) pci_write_config32(dev, 0xd0, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 5f6be1d163..ea641ee5fc 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -358,6 +358,7 @@ static void intel_me7_finalize_smm(void) { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -380,10 +381,10 @@ static void intel_me7_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -475,7 +476,7 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; - u32 reg32; + u16 reg16; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -486,9 +487,9 @@ static int intel_mei_setup(struct device *dev) mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 29c3a7635b..5a15e3d968 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -66,24 +66,22 @@ static void pch_disable_devfn(struct device *dev) void pch_enable(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 40ba75811d..dee25f64fb 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -30,10 +30,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xfc, 0x301b1728); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); access_cntl = pci_read_config8(dev, 0x80); From 73ae076e954ea6acd2fd22386616cd4ce839c830 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 10:13:05 +0200 Subject: [PATCH 1294/1463] sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND register Change-Id: I81b740e0cfcf0e1bf096427b45ffba06d357fee6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/lynxpoint/azalia.c | 4 +--- src/southbridge/intel/lynxpoint/early_usb.c | 5 +---- src/southbridge/intel/lynxpoint/me_9.x.c | 13 +++++-------- src/southbridge/intel/lynxpoint/pch.c | 13 +++++-------- src/southbridge/intel/lynxpoint/pcie.c | 18 ++++++------------ src/southbridge/intel/lynxpoint/serialio.c | 5 +---- src/southbridge/intel/lynxpoint/smihandler.c | 8 ++++---- src/southbridge/intel/lynxpoint/usb_ehci.c | 9 ++++----- 8 files changed, 27 insertions(+), 48 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index cbdd3f6ee9..cc77956b54 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -116,7 +116,6 @@ static void azalia_init(struct device *dev) u8 *base; struct resource *res; u32 codec_mask; - u32 reg32; /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -127,8 +126,7 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); azalia_pch_init(dev, base); diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 2f28369d53..075892b580 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -25,11 +25,8 @@ */ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { - u32 cmd; pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); - cmd = pci_read_config32(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } void enable_usb_bar(void) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index c5562c5cfc..4599c26cff 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -568,6 +568,7 @@ void intel_me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -595,10 +596,9 @@ void intel_me_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -726,7 +726,6 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; - u32 reg32; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -737,9 +736,7 @@ static int intel_mei_setup(struct device *dev) mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index a09f28e7a7..b8060a22dd 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -286,7 +286,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) void pch_enable(struct device *dev) { - u32 reg32; + u16 reg16; /* PCH PCIe Root Ports are handled in PCIe driver. */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) @@ -296,18 +296,15 @@ void pch_enable(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 0ca49b802c..3daf1826a5 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -277,7 +277,7 @@ static void root_port_commit_config(void) for (i = 0; i < rpc.num_ports; i++) { struct device *dev; - u32 reg32; + u16 reg16; dev = rpc.ports[i]; @@ -292,10 +292,9 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -654,19 +653,14 @@ static void pch_pcie_early(struct device *dev) static void pci_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 4591566e1b..f789e7c784 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -134,14 +134,11 @@ static void serialio_init(struct device *dev) struct southbridge_intel_lynxpoint_config *config = dev->chip_info; struct resource *bar0, *bar1; int sio_index = -1; - u32 reg32; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index e156b347c1..427c4fb337 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -64,7 +64,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -74,9 +74,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index ce81f76f44..1fde466eb7 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -16,7 +16,6 @@ void usb_ehci_disable(pci_devfn_t dev) { u16 reg16; - u32 reg32; /* Set 0xDC[0]=1 */ pci_or_config32(dev, 0xdc, (1 << 0)); @@ -29,9 +28,9 @@ void usb_ehci_disable(pci_devfn_t dev) /* Clear memory and bus master */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable device */ switch (dev) { @@ -56,7 +55,7 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff) return; - pci_cmd = pci_read_config32(dev, PCI_COMMAND); + pci_cmd = pci_read_config16(dev, PCI_COMMAND); switch (slp_typ) { case ACPI_S4: From b9d2e228b63c898383f1f6e6bd5e02b018ff31af Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 10:25:12 +0200 Subject: [PATCH 1295/1463] sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40794 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82801ix/hdaudio.c | 3 +-- src/southbridge/intel/i82801ix/i82801ix.c | 6 +----- src/southbridge/intel/i82801ix/pcie.c | 4 +--- src/southbridge/intel/i82801ix/usb_ehci.c | 6 +----- 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index e5b790619f..434d0aa2fd 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -247,8 +247,7 @@ static void azalia_init(struct device *dev) pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 &= ~(1 << 7); // Docking not supported diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index f26d584a38..b76116d80f 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -13,12 +13,8 @@ typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_device(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static void i82801ix_early_settings(const config_t *const info) diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index d170f0de44..5471e6979f 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -20,9 +20,7 @@ static void pci_init(struct device *dev) printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 3ccffd8228..9759186ca3 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -11,12 +11,8 @@ static void usb_ehci_init(struct device *dev) { - u32 reg32; - printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); } From ca4ff25290c099152ee9b2b53df6eb0d71ef0823 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 10:29:11 +0200 Subject: [PATCH 1296/1463] sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40795 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82801jx/hdaudio.c | 3 +-- src/southbridge/intel/i82801jx/i82801jx.c | 6 +----- src/southbridge/intel/i82801jx/pcie.c | 4 +--- src/southbridge/intel/i82801jx/usb_ehci.c | 6 +----- 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 1711de9ae3..5da7ce547f 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -247,8 +247,7 @@ static void azalia_init(struct device *dev) pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 &= ~(1 << 7); // Docking not supported diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index e55735b4a1..f3c899cad5 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -13,12 +13,8 @@ typedef struct southbridge_intel_i82801jx_config config_t; static void i82801jx_enable_device(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static void i82801jx_early_settings(const config_t *const info) diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index dba1a6519e..df3140a543 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -20,9 +20,7 @@ static void pci_init(struct device *dev) printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 03b314a10d..45737a535e 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -11,12 +11,8 @@ static void usb_ehci_init(struct device *dev) { - u32 reg32; - printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); } From d82faa8ea3f81087af76f9599e04258006dec222 Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Tue, 28 Apr 2020 11:48:26 +0800 Subject: [PATCH 1297/1463] mb/google/dedede: Enable USB port for camera support Support USB Chicony user facing camera. BUG=b:155109736 BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using user facing camera. Signed-off-by: Ian Feng Change-Id: I7580a58086977e239dca49c1def4f03583831662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Karthik Ramasubramanian --- .../dedede/variants/waddledoo/overridetree.cb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 920c1792fa..b9346af1fa 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,5 +1,8 @@ chip soc/intel/jasperlake + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -45,6 +48,17 @@ chip soc/intel/jasperlake }, }" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" From 804a34022cbd020e1b1f461ee3a45a68f14684f0 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 27 Apr 2020 05:25:06 +0200 Subject: [PATCH 1298/1463] sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40742 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/southbridge/intel/common/smihandler.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066da29..7b27ce0cd5 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -61,7 +61,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -71,9 +71,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); From 52e56e84796d8b4def9341f2302b355f059added Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 27 Apr 2020 05:34:05 +0200 Subject: [PATCH 1299/1463] libpayload: Fix 16-bit read/write to PCI_COMMAND register Change-Id: I34facbe0cbbdc91066799b586d96abca1599c509 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40743 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/usb/ehci.c | 4 ++-- payloads/libpayload/drivers/usb/usbinit.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index bf8a5eaa81..7969febce9 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -860,9 +860,9 @@ ehci_pci_init (pcidev_t addr) hci_t *controller; u32 reg_base; - u32 pci_command = pci_read_config32(addr, PCI_COMMAND); + u16 pci_command = pci_read_config16(addr, PCI_COMMAND); pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ; - pci_write_config32(addr, PCI_COMMAND, pci_command); + pci_write_config16(addr, PCI_COMMAND, pci_command); reg_base = pci_read_config32 (addr, USBBASE); diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 0ac27e4456..49634c6c06 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -62,11 +62,11 @@ static int usb_controller_initialize(int bus, int dev, int func) /* enable busmaster */ if (devclass == 0xc03) { - u32 pci_command; + u16 pci_command; - pci_command = pci_read_config32(pci_device, PCI_COMMAND); + pci_command = pci_read_config16(pci_device, PCI_COMMAND); pci_command |= PCI_COMMAND_MASTER; - pci_write_config32(pci_device, PCI_COMMAND, pci_command); + pci_write_config16(pci_device, PCI_COMMAND, pci_command); usb_debug("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, pciid >> 16, pciid & 0xFFFF, func); From 4c7bc8db749ffaf0bb3a54b43b0a56652285cde9 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Wed, 29 Apr 2020 13:56:37 +0800 Subject: [PATCH 1300/1463] mb/google/hatch/vr/puff: Add psys_pmax calculation This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Signed-off-by: Tim Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- .../google/hatch/variants/duffy/mainboard.c | 55 +++++++++++++------ .../google/hatch/variants/kaisa/mainboard.c | 55 +++++++++++++------ 2 files changed, 74 insertions(+), 36 deletions(-) diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c index 3f74c968b1..ceeb0c5aba 100644 --- a/src/mainboard/google/hatch/variants/duffy/mainboard.c +++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c @@ -31,23 +31,6 @@ static void wait_for_hpd(gpio_t gpio, long timeout) stopwatch_duration_msecs(&sw)); } -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - - /* This is reconfigured back to whatever FSP-S expects by - gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } -} - /* * For type-C chargers, set PL2 to 90% of max power to account for * cable loss and FET Rdson loss in the path from the source. @@ -86,6 +69,24 @@ void variant_ramstage_init(void) * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ + +/* + * Psys_pmax considerations + * + * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A + * instead of real system power. The equation is shown below: + * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) + * Hence, Iinput (Amps) = 9.6A + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W + * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W + * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W + */ +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000 + static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; @@ -108,15 +109,33 @@ static void mainboard_set_power_limits(config_t *conf) /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } else { + /* Input type is barrel jack */ + volts_mv = BJ_VOLTS_MV; } + /* voltage unit is milliVolts and current is in milliAmps */ + conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); conf->tdp_pl2_override = PUFF_PL2; /* set psyspl2 to 90% of max adapter power */ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); } -void variant_mainboard_enable(struct device *dev) +void variant_ramstage_init(void) { + static const long display_timeout_ms = 3000; config_t *conf = config_of_soc(); + + /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + /* Psys_pmax needs to be setup before FSP-S */ mainboard_set_power_limits(conf); } diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c index 3f74c968b1..ceeb0c5aba 100644 --- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c +++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c @@ -31,23 +31,6 @@ static void wait_for_hpd(gpio_t gpio, long timeout) stopwatch_duration_msecs(&sw)); } -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - - /* This is reconfigured back to whatever FSP-S expects by - gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } -} - /* * For type-C chargers, set PL2 to 90% of max power to account for * cable loss and FET Rdson loss in the path from the source. @@ -86,6 +69,24 @@ void variant_ramstage_init(void) * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ + +/* + * Psys_pmax considerations + * + * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A + * instead of real system power. The equation is shown below: + * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) + * Hence, Iinput (Amps) = 9.6A + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W + * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W + * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W + */ +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000 + static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; @@ -108,15 +109,33 @@ static void mainboard_set_power_limits(config_t *conf) /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } else { + /* Input type is barrel jack */ + volts_mv = BJ_VOLTS_MV; } + /* voltage unit is milliVolts and current is in milliAmps */ + conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); conf->tdp_pl2_override = PUFF_PL2; /* set psyspl2 to 90% of max adapter power */ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); } -void variant_mainboard_enable(struct device *dev) +void variant_ramstage_init(void) { + static const long display_timeout_ms = 3000; config_t *conf = config_of_soc(); + + /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + /* Psys_pmax needs to be setup before FSP-S */ mainboard_set_power_limits(conf); } From 0d6cc2201713fef102d7229f24e97428679aec68 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 29 Apr 2020 12:19:33 +0530 Subject: [PATCH 1301/1463] soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/chip.h | 3 +++ src/soc/intel/tigerlake/fsp_params.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a3319d4ee4..fe338352fb 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -107,6 +107,9 @@ struct soc_intel_tigerlake_config { * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ + uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 5acad201c6..fc2a3c026a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -151,6 +151,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; } + + /* Enable ClkReqDetect for enabled port */ + memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, + sizeof(config->PcieRpClkReqDetect)); + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { From a4f8e406633810c12b836d2d0fdbcca576840d41 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 29 Apr 2020 16:08:48 +0800 Subject: [PATCH 1302/1463] Update vboot submodule to upstream master Updating from commit id 55154620: vboot: Add screens for recovery using disk to commit id 3aab3014: vboot: Convert reboot-related errors to vboot2-style This brings in 3 new commits. Change-Id: I75be535e0b0f8080366b98e5ae2007452ad51738 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40845 Reviewed-by: Joel Kitching Tested-by: build bot (Jenkins) --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 55154620f4..3aab301473 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 55154620f4aa3bba9eaaf09f5186a52a48720025 +Subproject commit 3aab301473ec0b95f109a245efeadc20c3b7d57d From 30322785c446a20bce98e0591eb8fcf0023dcb53 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Fri, 17 Apr 2020 18:39:01 +0800 Subject: [PATCH 1303/1463] security/vboot: Convert reboot-related errors to vboot2-style Error codes are renamed as follows: VBERROR_SHUTDOWN_REQUESTED --> VB2_REQUEST_SHUTDOWN VBERROR_REBOOT_REQUIRED --> VB2_REQUEST_REBOOT VBERROR_EC_REBOOT_TO_SWITCH_RW --> VB2_REQUEST_REBOOT_EC_SWITCH_RW VBERROR_EC_REBOOT_TO_RO_REQUIRED --> VB2_REQUEST_REBOOT_EC_TO_RO BRANCH=none BUG=b:124141368, chromium:988410 TEST=emerge-nami coreboot Cq-Depend: chromium:2143030 Change-Id: Id82cf85f49dfb63a9c3d41aacd3969786bffcac7 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40749 Reviewed-by: Joel Kitching Tested-by: build bot (Jenkins) --- src/security/vboot/ec_sync.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 580e6c6b8d..39950a8452 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -56,7 +56,7 @@ void vboot_sync_ec(void) case VB2_SUCCESS: break; - case VBERROR_EC_REBOOT_TO_RO_REQUIRED: + case VB2_REQUEST_REBOOT_EC_TO_RO: printk(BIOS_INFO, "EC Reboot requested. Doing cold reboot\n"); if (google_chromeec_reboot(0, EC_REBOOT_COLD, 0)) printk(BIOS_EMERG, "Failed to get EC to cold reboot\n"); @@ -65,7 +65,7 @@ void vboot_sync_ec(void) break; /* Only for EC-EFS */ - case VBERROR_EC_REBOOT_TO_SWITCH_RW: + case VB2_REQUEST_REBOOT_EC_SWITCH_RW: printk(BIOS_INFO, "Switch EC slot requested. Doing cold reboot\n"); if (google_chromeec_reboot(0, EC_REBOOT_COLD, EC_REBOOT_FLAG_SWITCH_RW_SLOT)) @@ -74,7 +74,7 @@ void vboot_sync_ec(void) halt(); break; - case VBERROR_REBOOT_REQUIRED: + case VB2_REQUEST_REBOOT: printk(BIOS_INFO, "Reboot requested. Doing warm reboot\n"); vboot_reboot(); break; @@ -203,7 +203,7 @@ static vb2_error_t ec_protect_flash(enum vb2_firmware_selection select, int enab if (!enable) { /* If protection is still enabled, need reboot */ if (resp.flags & protected_region) - return VBERROR_EC_REBOOT_TO_RO_REQUIRED; + return VB2_REQUEST_REBOOT_EC_TO_RO; return VB2_SUCCESS; } @@ -222,7 +222,7 @@ static vb2_error_t ec_protect_flash(enum vb2_firmware_selection select, int enab /* If RW will be protected at boot but not now, need a reboot */ if (resp.flags & EC_FLASH_PROTECT_ALL_AT_BOOT) - return VBERROR_EC_REBOOT_TO_RO_REQUIRED; + return VB2_REQUEST_REBOOT_EC_TO_RO; /* Otherwise, it's an error */ return VB2_ERROR_UNKNOWN; @@ -479,7 +479,7 @@ vb2_error_t vb2ex_ec_vboot_done(struct vb2_context *ctx) if (limit_power) { printk(BIOS_INFO, "EC requests limited power usage. Request shutdown.\n"); - return VBERROR_SHUTDOWN_REQUESTED; + return VB2_REQUEST_SHUTDOWN; } else { printk(BIOS_INFO, "Waited %luus to clear limit power flag.\n", stopwatch_duration_usecs(&sw)); From d149f1db69c9ddde793889931ce8fef931d13cd8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 4 Apr 2020 02:48:03 +0200 Subject: [PATCH 1304/1463] soc/amd/picasso: Enable cache in bootblock Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM setup code to properly enable MTRRs. Add that capability to the bootblock_c_entry() function. In addition, enable an MTRR to cache (WP) the flash boot device and another for WB of the non-XIP bootblock running in DRAM. BUG=b:147042464 TEST=Boot trembyle to payload and make sure bootblock isn't abnormally slow. Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/bootblock/bootblock.c | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 8ae4db3178..6a0fd85078 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -2,14 +2,47 @@ /* This file is part of the coreboot project. */ #include +#include #include #include +#include +#include +#include +#include +#include #include #include #include +static void set_caching(void) +{ + msr_t deftype = {0, 0}; + int mtrr; + + /* Disable fixed and variable MTRRs while we setup */ + wrmsr(MTRR_DEF_TYPE_MSR, deftype); + + clear_all_var_mtrr(); + + mtrr = get_free_var_mtrr(); + if (mtrr >= 0) + set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + mtrr = get_free_var_mtrr(); + if (mtrr >= 0) + set_var_mtrr(mtrr, (unsigned int)_bootblock, REGION_SIZE(bootblock), + MTRR_TYPE_WRBACK); + + /* Enable variable MTRRs. Fixed MTRRs are left disabled since they are not used. */ + deftype.lo |= MTRR_DEF_TYPE_EN | MTRR_TYPE_UNCACHEABLE; + wrmsr(MTRR_DEF_TYPE_MSR, deftype); + + enable_cache(); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + set_caching(); enable_pci_mmconf(); bootblock_main_with_basetime(base_timestamp); From ac08c818369b8dcd21e7529ac50aebe5f4c4608a Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Sat, 4 Apr 2020 05:58:54 +0000 Subject: [PATCH 1305/1463] mb/purism/librem_skl: Use ACPI backlight controls Enables ACPI backlight controls. Change-Id: Iccf50f427b7555ee1a3ef9cc11a89d532789ac54 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/40145 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks Reviewed-by: Matt DeVillier --- src/mainboard/purism/librem_skl/dsdt.asl | 1 + .../purism/librem_skl/variants/librem13v2/devicetree.cb | 3 +++ .../purism/librem_skl/variants/librem15v3/devicetree.cb | 3 +++ 3 files changed, 7 insertions(+) diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 687de930d0..5ef19e12f6 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -24,6 +24,7 @@ DefinitionBlock( { #include #include + #include } } diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index f69c4822bb..6c55af66cc 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -8,6 +8,9 @@ chip soc/intel/skylake register "gpu_pch_backlight_pwm_hz" = "200" + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f5b8b99885..f48135297e 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -8,6 +8,9 @@ chip soc/intel/skylake register "gpu_pch_backlight_pwm_hz" = "200" + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0" From da5e07e6c7a88282e884cd6d2af726196e66cc21 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 29 Apr 2020 15:55:33 -0600 Subject: [PATCH 1306/1463] soc/amd/common/block/graphics/graphics: Add missing const to fill_ssdt BUG=none TEST=Made sure trembyle builds Signed-off-by: Raul E Rangel Change-Id: I9df70fd5c41a9a68edc7be3c2e920c4dc94d5af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40871 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/graphics/graphics.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index a40aadd256..6715a43296 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -5,7 +5,7 @@ #include #include -static void graphics_fill_ssdt(struct device *dev) +static void graphics_fill_ssdt(const struct device *dev) { acpi_device_write_pci_dev(dev); pci_rom_ssdt(dev); From 6449b674275812da9b7d69da99bedf0debfaa17f Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Sat, 28 Mar 2020 00:05:18 +0100 Subject: [PATCH 1307/1463] Documentation: Add proposal for firmware unit testing Signed-off-by: Jan Dabros Change-Id: I552d6c3373219978b8e5fd4304f993d920425431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39893 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Julius Werner --- .../2020-03-unit-testing-coreboot.md | 319 ++++++++++++++++++ Documentation/technotes/index.md | 1 + 2 files changed, 320 insertions(+) create mode 100644 Documentation/technotes/2020-03-unit-testing-coreboot.md diff --git a/Documentation/technotes/2020-03-unit-testing-coreboot.md b/Documentation/technotes/2020-03-unit-testing-coreboot.md new file mode 100644 index 0000000000..0d1d8ece49 --- /dev/null +++ b/Documentation/technotes/2020-03-unit-testing-coreboot.md @@ -0,0 +1,319 @@ +# Unit testing coreboot + +## Preface +First part of this document, Introduction, comprises disambiguation for what +unit testing is and what is not. This definition will be a basis for the whole +paper. + +Next, Rationale, explains why to use unit testing and how coreboot specifically +may benefit from it. + +This is followed by evaluation of different available free C unit test +frameworks. Firstly, collection of requirements is provided. Secondly, there is +a description of a few selected candidates. Finally, requirements are applied to +candidates to see if they might be a good fit. + +Fourth part is a summary of evaluation, with proposal of unit test framework +for coreboot to be used. + +Finally, Implementation proposal paragraph touches how build system and coreboot +codebase in general should be organized, in order to support unit testing. This +comprises couple of design considerations which need to be addressed. + +## Introduction +A unit test is supposed to test a single unit of code in isolation. In C +language (in contrary to OOP) unit usually means a function. One may also +consider unit under test to be a single compilation unit which exposes some +API (set of functions). A function, talking to some external component can be +tested if this component can be mocked out. + +In other words (looking from C compilation angle), there should be no extra +dependencies (executables) required beside unit under test and test harness in +order to compile unit test binary. Test harness, beside code examining a +routines, may comprise test framework implementation. + +It is hard to apply this strict definition of unit test to firmware code in +practice, mostly due to constraints on speed of execution and size of final +executable. coreboot codebase often cannot be adjusted to be testable. Because +of this, coreboot unit testing subsystem should allow to include some additional +source object files beside unit under test. That being said, the default and +goal wherever possible, should be to isolate unit under test from other parts. + +Unit testing is not an integration testing and it doesn't replace it. First of +all, integration tests cover larger set of components and interactions between +them. Positive integration test result gives more confidence than a positive +unit test does. Furthermore, unit tests are running on the build machine, while +integration tests usually are executed on the target (or simulator). + +## Rationale +Considering above, what is the benefit of unit testing, especially keeping in +mind that coreboot is low-level firmware? Unit tests should be quick, thus may +be executed frequently during development process. It is much easier to build +and run a unit test on a build machine, than any integration test. This in turn +may be used by dev to gather extra confidence early during code development +process. Actually developer may even write unit tests earlier than the code - +see [TDD](https://en.wikipedia.org/wiki/Test-driven_development) concept. + +That being said, unit testing embedded C code is a difficult task, due to +significant amount of dependencies on underlying hardware. Mocking can handle +some hardware dependencies. However, complex mocks make the unit test +susceptible to failing and can require significant development effort. + +Writing unit tests for a code (both new and currently existing) may be favorable +for the code quality. It is not only about finding bugs, but in general - easily +testable code is a good code. + +coreboot benefits the most from testing common libraries (lib/, commonlib/, +payloads/libpayload) and coreboot infrastructure (console/, device/, security/). + +## Evaluation of unit testing frameworks + +### Requirements +Requirements for unit testing frameworks: + +* Easy to use +* Few dependencies + + Standard C library is all we should need + +* Isolation between tests +* Support for mocking +* Support for some machine parsable output +* Compiler similarity + + Compiler for the host _must_ support the same language standards as the target + compiler. Ideally the same toolchain should be used for building firmware + executables and test binaries, however the host complier will be used to build + unit tests, whereas the coreboot toolchain will be used for building the + firmware executables. For some targets, the host compiler and the target + compiler could be the same, but this is not a requirement. + +* Same language for tests and code + + Unit tests will be written in C, because coreboot code is also written in C + +### Desirables + +* Easy to integrate with build system/build tools + + Ideally JUnit-like XML output format for Jenkins + +* Popularity is a plus + + We want a larger community for a couple of reasons. Firstly, easier access to + people with knowledge and tutorials. Secondly, bug fixes for the top of tree + are more frequent and known issues are usually shorter in the pending state. + Last but not least, larger reviewer pool means better and easier upstream + improvements that we would like to submit. + +* Extra features may be a plus +* Compatible license + + This should not be a blocker, since test binaries are not distributed. + However ideally compatible with GPL. + +* IDE integration + +### Candidates +There is a lot of frameworks which allow unit testing C code +([list](https://en.wikipedia.org/wiki/List_of_unit_testing_frameworks#C) from +Wikipedia). While not all of them were evaluated, because that would take an +excessive amount of time, couple of them were selected based on the good +opinions among C devs, popularity and fitting above criteria. + +* [SputUnit](https://www.use-strict.de/sput-unit-testing/) +* [GoogleTest](https://github.com/google/googletest) +* [Cmocka](https://cmocka.org/) +* [Unity](http://www.throwtheswitch.org/unity) (CMock, Ceedling) + +We looked at several other test frameworks, but decided not to do a full evaluation +for various reasons such as functionality, size of the developer community, or +compatibility. + +### Evaluation +* [SputUnit](https://www.use-strict.de/sput-unit-testing/) + * Pros + * No dependencies, one header file to include - that’s all + * Pure C + * Very easy to use + * BSD license + * Cons + * Main repo doesn’t have support for generating JUnit XML reports for + Jenkins to consume - this feature is available only on the fork from + SputUnit called “Sput_report”. It makes it niche in a niche, so there are + some reservations whether support for this will be satisfactory + * No support for mocks + * Not too popular + * No automatic test registration +* [GoogleTest](https://github.com/google/googletest) + * Pros + * Automatic test registration + * Support for different output formats (including XML for Jenkins) + * Good support, widely used, the biggest and the most active community out + of all frameworks that were investigated + * Available as a package in the most common distributions + * Test fixtures easily available + * Well documented + * Easy to integrate with an IDE + * BSD license + * Cons + * Requires C++11 compiler + * To make most out of it (use GMock) C++ knowledge is required +* [Cmocka](https://cmocka.org/) + * Pros + * Self-contained, autonomous framework + * Pure C + * API is well documented + * Multiple output formats (including XML for Jenkins) + * Available as a package in the most common distributions + * Used in some popular open source projects (libssh, OpenVPN, Samba) + * Test fixtures available + * Support for exception handling + * Cons + * No automatic test registration + * It will require some effort to make it work from within an IDE + * Apache 2.0 license (not compatible with GPLv2) +* [Unity](http://www.throwtheswitch.org/unity) (CMock, Ceedling) + * Pros + * Pure C (Unity testing framework itself, not test runner) + * Support for different output formats (including XML for Jenkins) + * There are some (rather easy) hints how to use this from an IDE (e.g. Eclipse) + * MIT license + * Cons + * Test runner (Ceedling) is not written in C - uses Ruby + * Mocking/Exception handling functionalities are actually separate tools + * No automatic test registration + * Not too popular + +### Summary & framework proposal +After research, we propose using the Cmocka unit test framework. Cmocka fulfills +all stated evaluation criteria. It is rather easy to use, doesn’t have extra +dependencies, written fully in C, allows for tests fixtures and some popular +open source projects already are using it. Cmocka also includes support for +mocks. + +Cmocka's limitations, such as the lack of automatic test registration, are +considered minor issues that will require only minimal additional work from a +developer. At the same time, it may be worth to propose improvement to Cmocka +community or simply apply some extra wrapper with demanded functionality. + +## Implementation + +### Framework as a submodule or external package +Unit test frameworks may be either compiled from source (from a git submodule +under 3rdparty/) or pre-compiled as a package. The second option seems to be +easier to maintain, while at the same time may bring some unwanted consequences +(different version across distributions, frequent changes in API). It makes sense +to initially experiment with packages and check how it works. If this will +cause any issues, then it is always possible to switch to submodule approach. + +### Integration with build system +To get the most out of unit testing framework, it should be integrated with +Jenkins automation server. Verification of all unit tests for new changes may +improve code reliability to some extent. + +### Build configuration (Kconfig) +While building unit under test object file, it is necessary to apply some +configuration (config) just like when building usual firmware. For simplicity, +there will be one default tests .config `qemu_x86_i440fx` for all unit tests. At +the same time, some tests may require running with different values of particular +config. This should be handled by adding extra header, included after config.h. +This header will comprise #undef of old CONFIG values and #define of the +required value. When unit testing will be integrated with Jenkins, it may be +preferred to use every available config for periodic builds. + +### Directory structure +Tests should be kept separate from the code, while at the same time it must be +easy to match code with test harness. + +We create new directory for test files ($(toplevel)/tests/) and mimic the +structure of src/ directory. + +Test object files (test harness, unit under tests and any additional executables +are stored under build/tests/ directory. + +Below example shows how directory structure is organized for the two test cases: +tests/lib/string-test and tests/device/i2c-test: + +```bash +├── src +│ ├── lib +│ │ ├── string.c <- unit under test +│ │ +│ ├── device +│ ├── i2c.c +│ +├── tests +│ ├── include +│ │ ├── mocks <- mock headers, which replace original headers +│ │ +│ ├── Makefile.inc <- top Makefile for unit tests subsystem +│ ├── lib +│ │ ├── Makefile.inc +│ │ ├── string-test.c <- test code for src/lib/string.c +│ │ │ +│ ├── device +│ │ ├── Makefile.inc +│ ├── i2c-test.c +│ +├── build +│ ├── tests <-all test-related executables + ├── config.h <- default config used for tests builds + ├── lib + │ ├── string-test <- all string-test executables + │ │ ├── run <- final test binary + │ │ ├── tests <- all test harness executables + │ │ ├── lib + │ │ ├── string-test.o <-test harness executable + │ │ ├── src <- unit under test and other src executables + │ │ ├── lib + │ │ ├── string.o <- unit under test executable + ├── device + ├── i2c-test + ├── run + ├── tests + │ ├── device + │ ├── i2c-test.o + ├── src + ├── device + ├── i2c.o +``` + +### Adding new tests +For purpose of this description, let's assume that we want to add a new unit test +for src/device/i2c.c module. Since this module is rather simple, it will be enough +to have only one test module. + +Firstly (assuming there is no tests/device/Makefile.inc file) we need to create +Makefile.inc in main unit test module directory. Inside this Makefile.inc, one +need to register new test and can specify multiple different attributes for it. + +```bash +# Register new test, by adding its name to tests variable +tests-y += i2c-test + +# All attributes are defined by - variables +# -srcs is used to register all input files (test harness, unit under +# test and others) for this particular test. Remember to add relative paths. +i2c-test-srcs += tests/device/i2c-test.c +i2c-test-srcs += src/device/i2c.c + +# We can define extra cflags for this particular test +i2c-test-cflags += -DSOME_DEFINE=1 + +# For mocking out external dependencies (functions which cannot be resolved by +# linker), it is possible to register a mock function. To register new mock, it +# is enough to add function-to-be-mocked name to -mocks variable. +i2c-test-mocks += platform_i2c_transfer + +# Similar to coreboot concept, unit tests also runs in the context of stages. +# By default all unit tests are compiled to be ramstage executables. If one want +# to overwrite this setting, there is -stage variable available. +i2c-test-stage:= bootblock +``` + +### Writing new tests +Full description of how to write unit tests and Cmocka API description is out of +the scope of this document. There are other documents related to this +[Cmocka API](https://api.cmocka.org/) and +[Mocks](https://lwn.net/Articles/558106/). diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index 7c231fc672..5367e69aa2 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -2,3 +2,4 @@ * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) +* [Unit testing coreboot](2020-03-unit-testing-coreboot.md) From ef1c968374ab9eb599ec18523700e0dacbeef351 Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Sat, 28 Mar 2020 00:15:03 +0100 Subject: [PATCH 1308/1463] tests: Add build subsystem for unit testing coreboot Add a subsystem which will be used for writing, building and running unit tests for different coreboot's modules. This work is built using Cmocka unit testing framework. Description of what unit testing means (for the author) and how unit testing framework evaluation was performed may be found in Documentation/technotes/2020-03-unit-testing-coreboot.md Makefiles structure is very similar to this used for building coreboot images. Every directory has its own Makefile.inc were tests' names, sources, subdirs and multiple other test-related attributes are defined in form of variables. Signed-off-by: Jan Dabros Change-Id: I9b0220b84b9a6e448476ca3eb3ccccc5fb829ad1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39894 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Julius Werner --- Makefile | 19 +++++++ tests/Makefile.inc | 136 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 tests/Makefile.inc diff --git a/Makefile b/Makefile index 98e3eb5796..55d3db1e88 100644 --- a/Makefile +++ b/Makefile @@ -141,6 +141,14 @@ NOMKDIR:=1 endif endif +ifneq ($(filter %-test %-tests,$(MAKECMDGOALS)),) +ifneq ($(filter-out %-test %-tests, $(MAKECMDGOALS)),) +$(error Cannot mix unit-tests targets with other targets) +endif +UNIT_TEST:=1 +NOCOMPILE:= +endif + .xcompile: util/xcompile/xcompile rm -f $@ $< $(XGCCPATH) > $@.tmp @@ -159,7 +167,9 @@ real-all: @exit 1 else +ifneq ($(UNIT_TEST),1) include $(DOTCONFIG) +endif # in addition to the dependency below, create the file if it doesn't exist # to silence stupid warnings about a file that would be generated anyway. @@ -177,7 +187,9 @@ ifneq ($(CONFIG_MMX),y) CFLAGS_x86_32 += -mno-mmx endif +ifneq ($(UNIT_TEST),1) include toolchain.inc +endif strip_quotes = $(strip $(subst ",,$(subst \",,$(1)))) # fix makefile syntax highlighting after strip macro \" ")) @@ -276,7 +288,14 @@ evaluate_subdirs= \ # collect all object files eligible for building subdirs:=$(TOPLEVEL) postinclude-hooks := + +# Don't iterate through Makefile.incs under src/ when building tests +ifneq ($(UNIT_TEST),1) $(eval $(call evaluate_subdirs)) +else +include $(TOPLEVEL)/tests/Makefile.inc +endif + ifeq ($(FAILBUILD),1) $(error cannot continue build) endif diff --git a/tests/Makefile.inc b/tests/Makefile.inc new file mode 100644 index 0000000000..82f724e69a --- /dev/null +++ b/tests/Makefile.inc @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +testobj = $(obj)/tests + +TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx +TEST_DOTCONFIG = $(testobj)/.config +TEST_KCONFIG_AUTOHEADER := $(testobj)/config.h +TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf +TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd +TEST_KCONFIG_SPLITCONFIG := $(testobj)/config +TEST_KCONFIG_TRISTATE := $(testobj)/tristate.conf + +TEST_CFLAGS = -include$(src)/include/kconfig.h \ + -include$(src)/commonlib/bsd/include/commonlib/bsd/compiler.h \ + -include $(src)/include/rules.h \ + +# Include generic test mock headers, before original ones +TEST_CFLAGS += -Itests/include/mocks + +TEST_CFLAGS += -I$(src)/include -I$(src)/commonlib/include \ + -I$(src)/commonlib/bsd/include -I$(src)/arch/x86/include \ + +# Path for Kconfig autoheader +TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) + +TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections \ + -Wl,--gc-sections -fno-builtin + +# Link against Cmocka +TEST_LDFLAGS = -lcmocka + +# Extra attributes for unit tests, declared per test +attributes:= srcs cflags mocks stage + +stages:= decompressor bootblock romstage smm verstage +stages+= ramstage rmodule postcar libagesa + +alltests:= +subdirs:= tests/arch tests/commonlib tests/console tests/cpu tests/device +subdirs+= tests/drivers tests/ec tests/lib tests/mainboard +subdirs+= tests/northbridge tests/security tests/soc tests/southbridge +subdirs+= tests/superio tests/vendorcode + +define tests-handler +alltests += $(1)$(2) +$(foreach attribute,$(attributes), + $(eval $(1)$(2)-$(attribute) += $($(2)-$(attribute)))) +$(foreach attribute,$(attributes), + $(eval $(2)-$(attribute):=)) + +# Sanity check for stage attribute value +$(eval $(1)$(2)-stage:=$(if $($(1)$(2)-stage),$($(1)$(2)-stage),ramstage)) +$(if $(findstring $($(1)$(2)-stage), $(stages)),, + $(error Wrong $(1)$(2)-stage value $($(1)$(2)-stage). \ + Check your $(dir $(1)$(2))Makefile.inc)) +endef + +$(call add-special-class, tests) +$(call evaluate_subdirs) + +# Create actual targets for unit test binaries +# $1 - test name +define TEST_CC_template +$($(1)-objs): TEST_CFLAGS+= \ + -D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__ +$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $(TEST_KCONFIG_AUTOHEADER) + mkdir -p $$(dir $$@) + $(HOSTCC) $(HOSTCFLAGS) $$(TEST_CFLAGS) $($(1)-cflags) -MMD \ + -MT $$@ -c $$< -o $$@ + +$($(1)-bin): TEST_LDFLAGS+= $$(foreach mock,$$($(1)-mocks),-Wl,--wrap=$$(mock)) +$($(1)-bin): $($(1)-objs) + $(HOSTCC) $$^ $($(1)-cflags) $$(TEST_LDFLAGS) -o $$@ + +endef + +$(foreach test, $(alltests), \ + $(eval $(test)-objs:=$(addprefix $(obj)/$(test)/, \ + $(patsubst %.c,%.o,$($(test)-srcs))))) +$(foreach test, $(alltests), \ + $(eval $(test)-bin:=$(obj)/$(test)/run)) +$(foreach test, $(alltests), \ + $(eval $(call TEST_CC_template,$(test)))) + +$(foreach test, $(alltests), \ + $(eval all-test-objs+=$($(test)-objs))) +$(foreach test, $(alltests), \ + $(eval test-bins+=$($(test)-bin))) + +DEPENDENCIES += $(addsuffix .d,$(basename $(all-test-objs))) +-include $(DEPENDENCIES) + +# Kconfig targets +$(TEST_DOTCONFIG): + mkdir -p $(dir $@) + cp $(TEST_DEFAULT_CONFIG) $(TEST_DOTCONFIG) + +# Don't override default Kconfig variables, since this will affect all +# Kconfig targets. Change them only when calling sub-make instead. +$(TEST_KCONFIG_AUTOHEADER): TEST_KCONFIG_FLAGS:= DOTCONFIG=$(TEST_DOTCONFIG) \ + KCONFIG_AUTOHEADER=$(TEST_KCONFIG_AUTOHEADER) \ + KCONFIG_AUTOCONFIG=$(TEST_KCONFIG_AUTOCONFIG) \ + KCONFIG_DEPENDENCIES=$(TEST_KCONFIG_DEPENDENCIES) \ + KCONFIG_SPLITCONFIG=$(TEST_KCONFIG_SPLITCONFIG) \ + KCONFIG_TRISTATE=$(TEST_KCONFIG_TRISTATE) \ + KBUILD_DEFCONFIG=$(TEST_DEFAULT_CONFIG) + +$(TEST_KCONFIG_AUTOHEADER): $(TEST_DOTCONFIG) $(objutil)/kconfig/conf + mkdir -p $(dir $@) + +$(MAKE) $(TEST_KCONFIG_FLAGS) olddefconfig + +$(MAKE) $(TEST_KCONFIG_FLAGS) silentoldconfig + +$(TEST_KCONFIG_AUTOCONFIG): $(TEST_KCONFIG_AUTOHEADER) + true + +.PHONY: $(alltests) $(addprefix clean-,$(alltests)) +.PHONY: unit-tests build-unit-tests run-unit-tests clean-unit-tests + +$(alltests): $$($$(@)-bin) + ./$^ + +unit-tests: build-unit-tests run-unit-tests + +build-unit-tests: $(test-bins) + +run-unit-tests: $(alltests) + echo "**********************" + echo " ALL TESTS PASSED" + echo "**********************" + +$(addprefix clean-,$(alltests)): clean-%: + rm -rf $(obj)/$* + +clean-unit-tests: + rm -rf $(testobj) From 2d0ee36913a5e0f6c74beb5cdb9f25ea36ea9290 Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Mon, 20 Apr 2020 15:19:45 +0200 Subject: [PATCH 1309/1463] tests: Add lib/string-test test case Show a basic example of how unit testing can be applied for the coreboot project. Add a test harness for lib/string.c module. TEST=Install cmocka via appropriate command: sudo apt-get install -y libcmocka-dev sudo emerge dev-util/cmocka yum install libcmocka-devel * Build and run unit tests via `make unit-tests` * Check the output to see that tests passed. Signed-off-by: Jan Dabros Change-Id: Ibf5554d1e99a393721a66bdd35af0122c2e412c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40538 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Fagerburg --- tests/lib/Makefile.inc | 20 ++++++++++++++++ tests/lib/string-test.c | 53 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 tests/lib/Makefile.inc create mode 100644 tests/lib/string-test.c diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc new file mode 100644 index 0000000000..86ac323ab8 --- /dev/null +++ b/tests/lib/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# object filest should be under build/tests/ build/test/src/ build/test/run/ +# two examples - first should be simply string.c, second should use -wrap + +tests-y += string-test + +string-test-srcs += tests/lib/string-test.c +string-test-srcs += src/lib/string.c diff --git a/tests/lib/string-test.c b/tests/lib/string-test.c new file mode 100644 index 0000000000..210aabae4a --- /dev/null +++ b/tests/lib/string-test.c @@ -0,0 +1,53 @@ +#include +#include +#include +#include + +#include + +/* + * Important note: In every particular test, don't use any string-related + * functions other than function under test. We are linking against + * src/lib/string.c not the standard library. This is important for proper test + * isolation. One can use __builtin_xxx for many of the most simple str*() + * functions, when non-coreboot one is required. + */ + +struct strings_t { + char *str; + size_t size; +} strings[] = { + {"coreboot", 8}, + {"is\0very", 2}, /* strlen should be 2 because of the embedded \0 */ + {"nice\n", 5} +}; + +static void test_strlen_strings(void **state) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(strings); i++) + assert_int_equal(strings[i].size, strlen(strings[i].str)); +} + +static void test_strdup(void **state) +{ + char str[] = "Hello coreboot\n"; + char *duplicate; + + duplicate = strdup(str); + + /* There is a more suitable Cmocka's function 'assert_string_equal()', but it + is using strcmp() internally. */ + assert_int_equal(0, memcmp(str, duplicate, __builtin_strlen(str))); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_strlen_strings), + cmocka_unit_test(test_strdup), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} From a67cc5f5e8d11cd1004faf112193cf368af25f4b Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Mon, 20 Apr 2020 14:34:16 +0200 Subject: [PATCH 1310/1463] tests: Add device/i2c-test test case Add unit test for src/device/i2c.c module. This patch is also used as an example for incorporating Cmocka mocking feature (-wrap linker flag). Signed-off-by: Jan Dabros Change-Id: I2eeb565aacc724ae3b9f5c76ef4b98ef695416d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40539 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Fagerburg --- tests/device/Makefile.inc | 18 ++++ tests/device/i2c-test.c | 183 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 tests/device/Makefile.inc create mode 100644 tests/device/i2c-test.c diff --git a/tests/device/Makefile.inc b/tests/device/Makefile.inc new file mode 100644 index 0000000000..f23e72fa32 --- /dev/null +++ b/tests/device/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +tests-y += i2c-test + +i2c-test-srcs += tests/device/i2c-test.c +i2c-test-srcs += src/device/i2c.c +i2c-test-mocks += platform_i2c_transfer diff --git a/tests/device/i2c-test.c b/tests/device/i2c-test.c new file mode 100644 index 0000000000..16e4d0d1ed --- /dev/null +++ b/tests/device/i2c-test.c @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include + +/* Simulate two i2c devices, both on bus 0, each with three uint8_t regs + implemented. */ +typedef struct { + uint8_t reg; + uint8_t data; +} i2c_ex_regs_t; + +typedef struct { + unsigned int bus; + uint8_t slave; + i2c_ex_regs_t regs[3]; +} i2c_ex_devs_t; + +i2c_ex_devs_t i2c_ex_devs[] = { + {.bus = 0, .slave = 0xA, .regs = { + {.reg = 0x0, .data = 0xB}, + {.reg = 0x1, .data = 0x6}, + {.reg = 0x2, .data = 0xF}, + } }, + {.bus = 0, .slave = 0x3, .regs = { + {.reg = 0x0, .data = 0xDE}, + {.reg = 0x1, .data = 0xAD}, + {.reg = 0x2, .data = 0xBE}, + } }, +}; + +int __wrap_platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int count) +{ + int i; + int reg; + struct i2c_msg *tmp = segments; + i2c_ex_devs_t *i2c_dev = NULL; + + check_expected(count); + + for (i = 0; i < count; i++, segments++) { + check_expected_ptr(segments->buf); + check_expected(segments->flags); + } + + reg = tmp->buf[0]; + + /* Find object for requested device */ + for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++, i2c_dev++) + if (i2c_ex_devs[i].slave == tmp->slave) { + i2c_dev = &i2c_ex_devs[i]; + break; + } + + if (i2c_dev == NULL) + return -1; + + /* Write commands */ + if (tmp->len > 1) { + i2c_dev->regs[reg].data = tmp->buf[1]; + }; + + /* Read commands */ + for (i = 0; i < count; i++, tmp++) + if (tmp->flags & I2C_M_RD) { + *(tmp->buf) = i2c_dev->regs[reg].data; + }; +} + +static void mock_expect_params_platform_i2c_transfer(void) +{ + unsigned long int expected_flags[] = {0, I2C_M_RD, I2C_M_TEN, + I2C_M_RECV_LEN, I2C_M_NOSTART}; + + /* Flags should always be only within supported range */ + expect_in_set_count(__wrap_platform_i2c_transfer, segments->flags, + expected_flags, -1); + + expect_not_value_count(__wrap_platform_i2c_transfer, segments->buf, + NULL, -1); + + expect_in_range_count(__wrap_platform_i2c_transfer, count, 1, INT_MAX, + -1); +} + +#define MASK 0x3 +#define SHIFT 0x1 + +static void i2c_read_field_test(void **state) +{ + int bus, slave, reg; + int i, j; + uint8_t buf; + + mock_expect_params_platform_i2c_transfer(); + + /* Read particular bits in all registers in all devices, then compare + with expected value. */ + for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) + for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { + i2c_read_field(i2c_ex_devs[i].bus, + i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, + &buf, MASK, SHIFT); + assert_int_equal((i2c_ex_devs[i].regs[j].data & + (MASK << SHIFT)) >> SHIFT, buf); + }; + + /* Read whole registers */ + for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) + for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { + i2c_read_field(i2c_ex_devs[i].bus, + i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, + &buf, 0xFF, 0); + assert_int_equal(i2c_ex_devs[i].regs[j].data, buf); + }; +} + +static void i2c_write_field_test(void **state) +{ + int bus, slave, reg; + int i, j; + uint8_t buf, tmp; + + mock_expect_params_platform_i2c_transfer(); + + /* Clear particular bits in all registers in all devices, then compare + with expected value. */ + for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) + for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { + buf = 0x0; + tmp = i2c_ex_devs[i].regs[j].data; + i2c_write_field(i2c_ex_devs[i].bus, + i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, + buf, MASK, SHIFT); + assert_int_equal(i2c_ex_devs[i].regs[j].data, + (tmp & ~(MASK << SHIFT)) | (buf << SHIFT)); + }; + + /* Set all bits in all registers, this time verify using + i2c_read_field() accessor. */ + for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) + for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { + i2c_write_field(i2c_ex_devs[i].bus, + i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, + 0xFF, 0xFF, 0); + i2c_read_field(i2c_ex_devs[i].bus, + i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, + &buf, 0xFF, 0); + assert_int_equal(buf, 0xFF); + }; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(i2c_read_field_test), + cmocka_unit_test(i2c_write_field_test) + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} From 7023174b88a2eca3f4eb541a2dc9cb7239617282 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 20 Apr 2020 13:37:00 +0200 Subject: [PATCH 1311/1463] vc/eltan/security/verified_boot/vboot_check.c: Increase wb_buffer size Running commit aee0baf0690681fae85d24e6887d6cbb9209de83 on Facebook fbg1701 results in an error: VB2:vb2_rsa_verify_digest() ERROR - vboot2 work buffer too small! ERROR: HASH table verification failed! The actual vboot structures require more space. Workbuffer size needs to be increased. We didn't determine the commit causing the issue because this change fixes the issue. BUG=N/A TEST=Build and boot Facebook fbg1701 Change-Id: I5caebc643eb493f4285c2f2fc164ff3a5d35e24e Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/40526 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn --- src/vendorcode/eltan/security/verified_boot/vboot_check.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index ac9d73bf9c..a07b470e03 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -26,7 +26,7 @@ int verified_boot_check_manifest(void) struct vb2_kernel_preamble *pre; static struct vb2_shared_data *sd; size_t size; - uint8_t wb_buffer[2800]; + uint8_t wb_buffer[3000]; if (vb2api_init(&wb_buffer, sizeof(wb_buffer), &ctx)) { goto fail; From e11072e6c77f3e6d137fb328f9b8e14729cfc749 Mon Sep 17 00:00:00 2001 From: William Wei Date: Wed, 22 Apr 2020 16:23:16 +0800 Subject: [PATCH 1312/1463] mb/google/volteer/malefor: Enable touch screen Enable Goodix touch screen and ensure it works properly. BUG=b:154191288 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the Goodix touch screen function. Signed-off-by: William Wei Change-Id: I236ac56dd0a1817092151bae93e699115ba88e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40598 Reviewed-by: Alex Levin Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../google/volteer/variants/malefor/gpio.c | 6 +++--- .../volteer/variants/malefor/overridetree.cb | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index 71a03e60dc..2804859abf 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -19,7 +19,7 @@ static const struct pad_config gpio_table[] = { /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_A8, 1, DEEP), + PAD_CFG_GPO(GPP_A8, 0, DEEP), /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_A9, NONE, DEEP), /* A10 : I2S2_RXD ==> EN_SPKR_PA */ @@ -121,7 +121,7 @@ static const struct pad_config gpio_table[] = { /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C10 : UART0_RTS# ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), + PAD_CFG_GPO(GPP_C10, 0, DEEP), /* C11 : UART0_CTS# ==> NOT USED */ PAD_NC(GPP_C11, NONE), /* C12 : UART1_RXD ==> MEM_STRAP_0 */ @@ -205,7 +205,7 @@ static const struct pad_config gpio_table[] = { /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> USI_INT */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ PAD_CFG_GPO(GPP_E8, 0, DEEP), /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 32204c58e7..8d4c6ea029 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -1,6 +1,24 @@ chip soc/intel/tigerlake device domain 0 on + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + end # I2C1 end end From f86c3265e8014b085de08094d7a30847fa49c165 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Fri, 10 Apr 2020 15:25:01 +0800 Subject: [PATCH 1313/1463] mb/google/octopus/variants/bobba: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Henry Sun Reviewed-by: Justin TerAvest --- .../octopus/variants/bobba/overridetree.cb | 1 + .../google/octopus/variants/bobba/variant.c | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 6cd4c61796..c786a5d2b6 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -214,4 +214,5 @@ chip soc/intel/apollolake # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 57b706795d..089337ab4c 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -8,6 +8,7 @@ #include #include #include +#include enum { SKU_37_DROID = 37, /* LTE */ @@ -74,3 +75,24 @@ void variant_smi_sleep(u8 slp_typ) return; } } + + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case 37: + case 38: + case 39: + case 40: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} From d991bf1fb43f977e46bd63a815dd0c8ec2cc3a8e Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Thu, 19 Mar 2020 18:05:15 +0300 Subject: [PATCH 1314/1463] Doc/mb/51nb/x210: Do minor fixes Fix code blocks, add a newline, use inline code blocks for commands. Change-Id: Iecf04b00ed12323c124517f2557cc8b60640b618 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/39670 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- Documentation/mainboard/51nb/x210.md | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/Documentation/mainboard/51nb/x210.md b/Documentation/mainboard/51nb/x210.md index 645c3ba816..2c41fd8a31 100644 --- a/Documentation/mainboard/51nb/x210.md +++ b/Documentation/mainboard/51nb/x210.md @@ -4,20 +4,21 @@ EC firmware is included in the SPI image. To extract it, run: -`` +``` dd bs=64K skip=32 count=1 if=bios.rom of=ec.bin -`` +``` -and ensure that you have a file that includes the string "Insyde Software Corp" +and ensure that you have a file that includes the string "Insyde Software Corp". ## Flashing instructions This can be performed using the internal SPI controller, even when flashing -from stock firmware. Use flashrom -p internal and follow the appropriate +from stock firmware. Use `flashrom -p internal` and follow the appropriate flashrom instructions to force it. Alternatively, external flashing has been tested with Dediprog SF100 and SF600 and using a Beaglebone Black. The flash is located on the upper side of the motherboard, below the keyboard connector. It is circled in red here: + ![](x210.jpg) ## Flashing a subset of the ROM @@ -32,14 +33,14 @@ create a layout file with the following content: 00210000:007fffff main ``` -and run flashrom with the "--layout rom.layout --image main" arguments. This +and run flashrom with the `--layout rom.layout --image main` arguments. This will flash the main firmware without overwriting the existing EC or ME firmware. ## Working All hardware features are believed to be working, although the SD reader is -untested. Note that certain hotkeys don't work (including the Thinkvantage +untested. Note that certain hotkeys don't work (including the ThinkVantage button) - this is a limitation of the EC firmware, and these keys also generate no events under the stock vendor firmware. From 09a106907ea7e53e206ea1db3d1639d0941a39fe Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 13 Mar 2020 07:48:55 +0100 Subject: [PATCH 1315/1463] soc/intel/cannonlake/bootblock: Fix FSP CAR Fix FSP CAR on platforms that have ROM_SIZE of 32MiB. CodeRegionSize must be smaller than or equal to 16MiB to not overlap with LAPIC or the CAR area at 0xfef00000. Tested on Intel CFL, the new code allows to boot using FSP-T. Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/bootblock/bootblock.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 21b8487ace..73bd81a334 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -2,6 +2,7 @@ /* This file is part of the coreboot project. */ #include +#include #include #include #include @@ -28,12 +29,14 @@ const FSPT_UPD temp_ram_init_params = { * even before hitting CPU reset vector. Hence skipping FSP-T loading * microcode after CPU reset by passing '0' value to * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. + * + * Note: CodeRegionSize must be smaller than or equal to 16MiB to not + * overlap with LAPIC or the CAR area at 0xfef00000. */ .MicrocodeRegionBase = 0, .MicrocodeRegionSize = 0, - .CodeRegionBase = - (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), - .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, + .CodeRegionBase = (uint32_t)0x100000000ULL - CACHE_ROM_SIZE, + .CodeRegionSize = (uint32_t)CACHE_ROM_SIZE, }, }; #endif From 0025f777ed3e231e93e06fdebf520496804a6097 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Tue, 28 Apr 2020 17:00:41 +0800 Subject: [PATCH 1316/1463] mainboard/google/kahlee: move specific setting to variant Separate specific setting to variant from baseboard. baseboard/romstage.c in current release is only utilized by careena, we could remove it from the rest of variant build. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I658526e44aadc47bdc5538f506a1bfe2e5f20f63 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40796 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../kahlee/variants/aleena/Makefile.inc | 2 - .../kahlee/variants/baseboard/romstage.c | 35 ----------------- .../kahlee/variants/careena/Makefile.inc | 2 +- .../variants/careena/include/variant/sku.h | 24 ++++++++++++ .../google/kahlee/variants/careena/variant.c | 38 +++++++++++++++++++ .../google/kahlee/variants/grunt/Makefile.inc | 2 - .../google/kahlee/variants/liara/Makefile.inc | 2 - .../kahlee/variants/nuwani/Makefile.inc | 2 - .../kahlee/variants/treeya/Makefile.inc | 2 - 9 files changed, 63 insertions(+), 46 deletions(-) delete mode 100644 src/mainboard/google/kahlee/variants/baseboard/romstage.c create mode 100644 src/mainboard/google/kahlee/variants/careena/include/variant/sku.h create mode 100644 src/mainboard/google/kahlee/variants/careena/variant.c diff --git a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc index 0346f39c5a..ba3228d6c3 100644 --- a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc @@ -14,6 +14,4 @@ subdirs-y += ../baseboard/spd -romstage-y += ../baseboard/romstage.c - ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/baseboard/romstage.c b/src/mainboard/google/kahlee/variants/baseboard/romstage.c deleted file mode 100644 index 0ef0c52547..0000000000 --- a/src/mainboard/google/kahlee/variants/baseboard/romstage.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include -#include - -/* SKU ID enumeration */ -enum careena_sku { - SKU_UNKNOWN = -1, - SKU_CAREENA_KB_NO_BACKLIGHT16 = 16, - SKU_CAREENA_KB_BACKLIGHT18 = 18, - SKU_CAREENA_KB_BACKLIGHT19 = 19, - SKU_CAREENA_KB_BACKLIGHT22 = 22, - SKU_CAREENA_KB_BACKLIGHT23 = 23, -}; - -void variant_romstage_entry(int s3_resume) -{ - uint32_t sku = google_chromeec_get_sku_id(); - - if (!s3_resume) { - /* Based on SKU, turn on keyboard backlight */ - switch (sku) { - default: - google_chromeec_kbbacklight(75); - break; - case SKU_CAREENA_KB_BACKLIGHT18: - case SKU_CAREENA_KB_BACKLIGHT19: - case SKU_CAREENA_KB_BACKLIGHT22: - case SKU_CAREENA_KB_BACKLIGHT23: - google_chromeec_kbbacklight(10); - break; - } - } -} diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index 3dfc57c491..dd9ff4eded 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -14,6 +14,6 @@ subdirs-y += ./spd -romstage-y += ../baseboard/romstage.c +romstage-y += variant.c ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/sku.h b/src/mainboard/google/kahlee/variants/careena/include/variant/sku.h new file mode 100644 index 0000000000..a31c99eba2 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/sku.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SKU ID enumeration */ +enum careena_sku { + SKU_UNKNOWN = -1, + SKU_CAREENA_KB_NO_BACKLIGHT16 = 16, + SKU_CAREENA_KB_BACKLIGHT18 = 18, + SKU_CAREENA_KB_BACKLIGHT19 = 19, + SKU_CAREENA_KB_BACKLIGHT22 = 22, + SKU_CAREENA_KB_BACKLIGHT23 = 23, +}; diff --git a/src/mainboard/google/kahlee/variants/careena/variant.c b/src/mainboard/google/kahlee/variants/careena/variant.c new file mode 100644 index 0000000000..d35ec488df --- /dev/null +++ b/src/mainboard/google/kahlee/variants/careena/variant.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void variant_romstage_entry(int s3_resume) +{ + uint32_t sku = google_chromeec_get_sku_id(); + + if (!s3_resume) { + /* Based on SKU, turn on keyboard backlight */ + switch (sku) { + default: + google_chromeec_kbbacklight(75); + break; + case SKU_CAREENA_KB_BACKLIGHT18: + case SKU_CAREENA_KB_BACKLIGHT19: + case SKU_CAREENA_KB_BACKLIGHT22: + case SKU_CAREENA_KB_BACKLIGHT23: + google_chromeec_kbbacklight(10); + break; + } + } +} diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc index 0346f39c5a..ba3228d6c3 100644 --- a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc @@ -14,6 +14,4 @@ subdirs-y += ../baseboard/spd -romstage-y += ../baseboard/romstage.c - ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/liara/Makefile.inc b/src/mainboard/google/kahlee/variants/liara/Makefile.inc index 0346f39c5a..ba3228d6c3 100644 --- a/src/mainboard/google/kahlee/variants/liara/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/liara/Makefile.inc @@ -14,6 +14,4 @@ subdirs-y += ../baseboard/spd -romstage-y += ../baseboard/romstage.c - ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc index 8823259bd7..89458dec87 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc @@ -14,6 +14,4 @@ subdirs-y += ./spd -romstage-y += ../baseboard/romstage.c - ramstage-y += mainboard.c diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index 8823259bd7..89458dec87 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -14,6 +14,4 @@ subdirs-y += ./spd -romstage-y += ../baseboard/romstage.c - ramstage-y += mainboard.c From 7d18f88c6da0333848ca9ff86fedb1e9e7c4338c Mon Sep 17 00:00:00 2001 From: Marco Chen Date: Wed, 29 Apr 2020 14:32:54 +0800 Subject: [PATCH 1317/1463] soc/intel/jasperlake: fix args of dimm_info_fill() for dram_part_num BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. modify mainboard - dedede to report DRAM part number from CBI 3. check DRAM part number is correct in SMBIOS for memory device Change-Id: I509d06a81bd005c5afe6e74a2da2ca408dee7b29 Signed-off-by: Marco Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40833 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/jasperlake/romstage/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index b8e9032e97..dc5dcf1a9b 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -108,8 +108,8 @@ static void save_dimm_info(void) src_dimm->RankInDimm, channel_info->ChannelId, src_dimm->DimmId, - (const char *)src_dimm->ModulePartNum, - sizeof(src_dimm->ModulePartNum), + dram_part_num, + dram_part_num_len, serial_num, meminfo_hob->DataWidth, meminfo_hob->VddVoltage[memProfNum], From c1adeb68a0228a514f68baec89994ec77a1311fe Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 00:04:14 -0700 Subject: [PATCH 1318/1463] arch/x86/acpi_device: Allow empty child references Currently if a child table is created and added to a property list without adding any properties to that child it will generate an empty package. For example: struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); struct acpi_dp *prop = acpi_dp_new_table("PROP"); acpi_dp_add_child(dsd, "dsd-prop", prop); acpi_dp_write(dsd); Results in an empty PROP package: Name (_DSD, Package (2) { ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") Package (1) { Package (2) { "dsd-prop", "PROP" } } } Name (PROP, Package (0) { } Empty packages don't seem to be explicitly forbidden, but they don't serve a purpose with device properties. Instead, if packages without any properties or children are skipped then this empty package is not written and the added child property can refer to another property that is already defined. This allows creating property references to existing tables, which can save duplication and namespace collision issues with nested properties. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40880 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/arch/x86/acpi_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index b4016ef5db..f3ee1e7ec4 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -665,7 +665,7 @@ void acpi_dp_write(struct acpi_dp *table) char *dp_count, *prop_count = NULL; int child_count = 0; - if (!table || table->type != ACPI_DP_TYPE_TABLE) + if (!table || table->type != ACPI_DP_TYPE_TABLE || !table->next) return; /* Name (name) */ From de13519ca58c12845b1bdc525654f5da5365b7bf Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 00:11:19 -0700 Subject: [PATCH 1319/1463] arch/x86/acpi: Add define for generic container HID The generic container HID is defined in ACPI specification as PNP0A05. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I3632e77533a47f22b92259b469b03e63f51687e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40881 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/arch/x86/include/arch/acpi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 86b3932f89..5314d78197 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -118,6 +118,7 @@ typedef struct acpi_gen_regaddr { #define ACPI_HID_COM "PNP0501" #define ACPI_HID_LPT "PNP0400" #define ACPI_HID_PNP "PNP0C02" +#define ACPI_HID_CONTAINER "PNP0A05" /* Generic ACPI header, provided by (almost) all tables */ typedef struct acpi_table_header { From ed6eb2713a738c45ab876941d6b5805fd00bf13c Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 11:39:08 -0700 Subject: [PATCH 1320/1463] acpi_device: Make integer array input variable const An array of 64bit integers is passed to acpi_dp_add_integer_array() but it is not const so can't take a const array without a compiler error. The function does not modify the array so it can be made const without breaking anything and allowing a const array to be passed in the future. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I98ecdaef5ddfa2026390e2812f5ea841ee51f073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40882 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/arch/x86/acpi_device.c | 2 +- src/arch/x86/include/arch/acpi_device.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index f3ee1e7ec4..bef1a5db73 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -879,7 +879,7 @@ struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array) } struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, - uint64_t *array, int len) + const uint64_t *array, int len) { struct acpi_dp *dp_array; int i; diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index ed64cd8a27..bc71e0264d 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -482,7 +482,7 @@ struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array); /* Add an array of integers Device Property */ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, - uint64_t *array, int len); + const uint64_t *array, int len); /* Add a GPIO binding Device Property */ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, From 1d17529954fda73460ef2441706139967e3a6b78 Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Thu, 30 Apr 2020 10:05:47 +0800 Subject: [PATCH 1321/1463] mb/google/deltaur: Update USB/WWAN config Update USB3 ports configuration as schematics design. BUG=b:155026295 TEST=Boot into OS and check WWAN device detected by lsusb. Signed-off-by: Ivy Jian Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../deltaur/variants/baseboard/devicetree.cb | 26 ++++++------------- 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 498266efdd..e31c89b468 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -48,6 +48,8 @@ chip soc/intel/tigerlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN # PCIe root port 6 (WLAN), clock 1 register "PcieRpEnable[5]" = "1" @@ -232,33 +234,21 @@ chip soc/intel/tigerlake device usb 2.9 on end end chip drivers/usb/acpi - register "desc" = ""Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.0 on end end chip drivers/usb/acpi - register "desc" = ""Type-C Port 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.1 on end end - chip drivers/usb/acpi - register "desc" = ""Type-A Port 1 (Right)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Type-A Port 2 (Left)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.3 on end - end chip drivers/usb/acpi register "desc" = ""WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end + device usb 3.2 on end end end end @@ -297,7 +287,7 @@ chip soc/intel/tigerlake device pci 1c.0 on end # PCIe Root Port #1 (USB) device pci 1c.1 on end # PCIe Root Port #2 (USB) device pci 1c.2 off end # PCIe Root Port #3 () - device pci 1c.3 on end # PCIe Root Port #4 (WWAN) + device pci 1c.3 off end # PCIe Root Port #4 (WWAN) device pci 1c.4 on end # PCIe Root Port #5 (LTE) device pci 1c.5 on end # PCIe Root Port #6 (WiFi) device pci 1c.6 on end # PCIe Root Port #7 (Card reader) From 7be0df8dd354d87c2482ac2d2cca29628297bd03 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 Apr 2020 12:23:16 +0530 Subject: [PATCH 1322/1463] soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding BIT 1 -> DEBUG_INTERFACE_UART_8250IO BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/soc/intel/jasperlake/chip.h | 4 ++-- src/soc/intel/jasperlake/romstage/fsp_params.c | 2 +- src/soc/intel/tigerlake/chip.h | 4 ++-- src/soc/intel/tigerlake/romstage/fsp_params.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index a6932bc52c..886f823711 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -201,9 +201,9 @@ struct soc_intel_jasperlake_config { /* Debug interface selection */ enum { DEBUG_INTERFACE_RAM = (1 << 0), - DEBUG_INTERFACE_UART = (1 << 1), + DEBUG_INTERFACE_UART_8250IO = (1 << 1), DEBUG_INTERFACE_USB3 = (1 << 3), - DEBUG_INTERFACE_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), DEBUG_INTERFACE_TRACEHUB = (1 << 5), } debug_interface_flag; diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index a841809499..bb7db65dd7 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -60,7 +60,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fe338352fb..9f12dae1d9 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -198,9 +198,9 @@ struct soc_intel_tigerlake_config { /* Debug interface selection */ enum { DEBUG_INTERFACE_RAM = (1 << 0), - DEBUG_INTERFACE_UART = (1 << 1), + DEBUG_INTERFACE_UART_8250IO = (1 << 1), DEBUG_INTERFACE_USB3 = (1 << 3), - DEBUG_INTERFACE_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), DEBUG_INTERFACE_TRACEHUB = (1 << 5), } debug_interface_flag; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index b4521e2a61..022cd830c9 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -71,7 +71,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); From 5874c7831cc5b14bbd97510009529af16108e23e Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Wed, 29 Apr 2020 14:23:21 +0800 Subject: [PATCH 1323/1463] mb/google/deltaur: Add BT reset gpio Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence. BUG=b:155248677 TEST=Boot into OS and check BT is functional. Signed-off-by: Eric Lai Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel --- src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 1 + src/mainboard/google/deltaur/variants/baseboard/gpio.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index e31c89b468..028b022a1b 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -231,6 +231,7 @@ chip soc/intel/tigerlake chip drivers/usb/acpi register "desc" = ""M.2 2230 (BT)"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device usb 2.9 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index a96e702fac..62b6559e46 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -32,7 +32,7 @@ static const struct pad_config gpio_table[] = { /* A12 : GPP_A12 ==> M2280_PCIE_SATA# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */ - PAD_CFG_GPO(GPP_A13, 0, DEEP), + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* A14 : GPP_A14 ==> USB_OC1# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : GPP_A15 ==> USB_OC2# */ From b468f9b9ea03edc33ff959aa1f42fc06a124c1b6 Mon Sep 17 00:00:00 2001 From: Victor Ding Date: Thu, 30 Apr 2020 13:23:42 +1000 Subject: [PATCH 1324/1463] ec/google/chromeec: Fix incorrect diag message The expected error code observed in clear_pending_events() should be EC_RES_UNAVAILABLE(9), not EC_RES_INVALID_COMMAND(1). BUG=b:153896701 Change-Id: I609490ceef675267760d34b5e9775211da93347c Signed-off-by: Victor Ding Reviewed-on: https://review.coreboot.org/c/coreboot/+/40900 Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/smihandler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index febb457607..5e192a51da 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -41,7 +41,7 @@ static void clear_pending_events(void) while (google_chromeec_get_event() != 0) ; - printk(BIOS_DEBUG,"Clearing pending EC events. Error code 1 is expected.\n"); + printk(BIOS_DEBUG, "Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.\n"); while (google_chromeec_get_mkbp_event(&mkbp_event) == 0) ; } From 89e51e6178186bce7f602007232980adc28ca510 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 9 Apr 2020 14:16:55 -0600 Subject: [PATCH 1325/1463] soc/amd/picasso: Allow mainboard to provide pci ddi descriptors Mainboards must provide their DDI descriptors. BUG=b:153502861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454 Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/fsp_params.c | 55 +++++++++++++++++++ .../include/soc/platform_descriptors.h | 16 ++++++ 3 files changed, 72 insertions(+) create mode 100644 src/soc/amd/picasso/fsp_params.c create mode 100644 src/soc/amd/picasso/include/soc/platform_descriptors.h diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 4790ecb502..c7b6fb8bc9 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c +ramstage-y += fsp_params.c all-y += reset.c diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c new file mode 100644 index 0000000000..0dbda093f3 --- /dev/null +++ b/src/soc/amd/picasso/fsp_params.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include "chip.h" + +static void fill_pcie_descriptors(FSP_S_CONFIG *scfg, + const picasso_fsp_pcie_descriptor *descs, size_t num) +{ + size_t i; + picasso_fsp_pcie_descriptor *fsp_pcie; + + /* FIXME: this violates C rules. */ + fsp_pcie = (picasso_fsp_pcie_descriptor *)(scfg->dxio_descriptor0); + + for (i = 0; i < num; i++) { + fsp_pcie[i] = descs[i]; + } +} + +static void fill_ddi_descriptors(FSP_S_CONFIG *scfg, + const picasso_fsp_ddi_descriptor *descs, size_t num) +{ + size_t i; + picasso_fsp_ddi_descriptor *fsp_ddi; + + /* FIXME: this violates C rules. */ + fsp_ddi = (picasso_fsp_ddi_descriptor *)&(scfg->ddi_descriptor0); + + for (i = 0; i < num; i++) { + fsp_ddi[i] = descs[i]; + } +} +static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) +{ + const picasso_fsp_pcie_descriptor *fsp_pcie; + const picasso_fsp_ddi_descriptor *fsp_ddi; + size_t num_pcie; + size_t num_ddi; + + mainboard_get_pcie_ddi_descriptors(&fsp_pcie, &num_pcie, + &fsp_ddi, &num_ddi); + fill_pcie_descriptors(scfg, fsp_pcie, num_pcie); + fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + FSP_S_CONFIG *scfg = &supd->FspsConfig; + + fsp_fill_pcie_ddi_descriptors(scfg); +} diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h new file mode 100644 index 0000000000..bc67550fd0 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__ +#define __PICASSO_PLATFORM_DESCRIPTORS_H__ + +#include +#include +#include + +/* Mainboard callback to obtain PCIe and DDI descriptors. */ +void mainboard_get_pcie_ddi_descriptors( + const picasso_fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); + +#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ From f771b1669bd860858ca89ef389940779d1baadb0 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 29 Apr 2020 13:41:36 -0600 Subject: [PATCH 1326/1463] soc/amd/picasso/bootblock/bootblock: Remove duplicate i2c init fch_early_init already calls i2c_soc_early_init(). BUG=b:153675916 TEST=Boot trembyle and only see 1 i2c initialization message Signed-off-by: Raul E Rangel Change-Id: I689616fb617904df1781be3abe9d1dc580608173 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40866 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/bootblock/bootblock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 6a0fd85078..56cdbd96c5 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -60,5 +60,4 @@ void bootblock_soc_init(void) printk(BIOS_DEBUG, "Family_Model: %08x\n", val); fch_early_init(); - i2c_soc_early_init(); } From 4cf3af49cadafb00fe6370fd3057ea6b2c25608a Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 29 Apr 2020 13:55:38 -0600 Subject: [PATCH 1327/1463] soc/amd/picasso/bootblock: Remove duplicate sb_reset_i2c_slaves sb_reset_i2c_slaves is called in fch_pre_init. BUG=b:153675916 TEST=Builds on trembyle Signed-off-by: Raul E Rangel Change-Id: I157e473984257d633ceb3ef9df45c71a31c5c00b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40867 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/bootblock/bootblock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 56cdbd96c5..b1f43c2c5c 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -50,7 +50,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { - sb_reset_i2c_slaves(); fch_pre_init(); } From 09f60ff0e259664c174070a6ed444bd3e11883c5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 9 Apr 2020 15:24:50 -0600 Subject: [PATCH 1328/1463] soc/amd/picasso: initialize i2c controllers in SoC flow BUG=b:153642124 TEST=Saw I2C communication Change-Id: I31f8b97d1ff7b687d7e078d5b594d1ad73c815e7 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145457 Commit-Queue: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40868 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/southbridge.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index d37f143313..0d54294543 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -467,6 +467,7 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); void southbridge_init(void *chip_info) { + i2c_soc_init(); sb_init_acpi_ports(); acpi_clear_pm1_status(); } From 38df060abad3ac105d73fc7425c89571650b40f1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 27 Apr 2020 12:12:54 +0530 Subject: [PATCH 1329/1463] mb/google/dedede: Fix crossystem wpsw_cur error Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community zero. TEST=Build coreboot, flash, boot to and log into kernel, execute "wp enable" in console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744 Reviewed-by: Usha P Reviewed-by: Maulik V Vaghela Reviewed-by: Angel Pons Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/chromeos.c | 3 +-- src/mainboard/google/dedede/variants/baseboard/gpio.c | 4 +++- .../google/dedede/variants/baseboard/include/baseboard/gpio.h | 2 ++ 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index a9cc602e8d..3f0cad5a99 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -23,8 +23,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - /* No write protect */ - return 0; + return gpio_get(GPIO_PCH_WP); } void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 6adb35ba9d..1b3e015c78 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = { /* C10 : GPP_C10/UART0_RTSB */ PAD_NC(GPP_C10, NONE), /* C11 : AP_WP_OD */ - PAD_NC(GPP_C11, NONE), + PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* C12 : AP_PEN_DET_ODL */ PAD_NC(GPP_C12, NONE), /* C13 : GPP_C13/UART1_TXD */ @@ -444,6 +444,8 @@ const struct pad_config *__weak variant_sleep_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index 98e4b277f7..fac834288d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -14,6 +14,8 @@ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI +#define GPIO_PCH_WP GPP_C11 + /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK From 1234925ad77aa888fb28034251b950e1bc2fd480 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 27 Apr 2020 05:08:26 +0200 Subject: [PATCH 1330/1463] sb/intel/i82801gx: Fix 16-bit read/write PCI_COMMAND register Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40741 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801gx/azalia.c | 3 +-- src/southbridge/intel/i82801gx/i82801gx.c | 12 +++++------- src/southbridge/intel/i82801gx/ide.c | 3 +-- src/southbridge/intel/i82801gx/pcie.c | 4 +--- src/southbridge/intel/i82801gx/usb.c | 4 +--- src/southbridge/intel/i82801gx/usb_ehci.c | 5 +---- 6 files changed, 10 insertions(+), 21 deletions(-) diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 4a2b50e4d4..775326cccf 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -230,8 +230,7 @@ static void azalia_init(struct device *dev) pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 1a5366fe87..eae16db3d3 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -54,23 +54,21 @@ static void ich_hide_devfn(unsigned int devfn) void i82801gx_enable(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide this device if possible */ ich_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) { printk(BIOS_DEBUG, "Set SATA mode early\n"); diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index b6b30efea9..cc3e7409d4 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -30,8 +30,7 @@ static void ide_init(struct device *dev) enable_secondary = config->ide_enable_secondary; } - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); /* Native Capable, but not enabled. */ pci_write_config8(dev, 0x09, 0x8a); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 4398ad56b0..4de62e256d 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -47,9 +47,7 @@ static void pci_init(struct device *dev) printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index d4b559a37b..d8c55e0981 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -10,14 +10,12 @@ static void usb_init(struct device *dev) { - u32 reg32; u8 reg8; /* USB Specification says the device must be Bus Master */ printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); // Erratum pci_write_config8(dev, 0xca, 0x00); diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index d127496cd6..08211c2f9e 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -18,10 +18,7 @@ static void usb_ehci_init(struct device *dev) u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR); reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 31) | (1 << 27); From e4c81bcca59e94c71f7acf48c060da827afeb15a Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Thu, 23 Apr 2020 13:17:00 +0200 Subject: [PATCH 1331/1463] documentation: Add documentation ideas for season of docs Let's gather some documentation ideas for the season of docs. I reused the project ideas style (thanks Patrick). Feel free to add yourself as a mentor here. Also if you have more ideas, please add them to the document. Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/40662 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- .../contributing/documentation_ideas.md | 173 ++++++++++++++++++ Documentation/index.md | 1 + 2 files changed, 174 insertions(+) create mode 100644 Documentation/contributing/documentation_ideas.md diff --git a/Documentation/contributing/documentation_ideas.md b/Documentation/contributing/documentation_ideas.md new file mode 100644 index 0000000000..54b3efa5bc --- /dev/null +++ b/Documentation/contributing/documentation_ideas.md @@ -0,0 +1,173 @@ +# Documentation Ideas + +This section collects ideas to improve the coreboot documentation and +should serve as a pool of ideas for people who want to improve the current +documentation status of coreboot. + +The main purpose of this document is to gather documentation ideas for technical +writers of the seasons of docs. Nevertheless anyone who wants to help improving +the current documentation situation can take one of the projects. + +Each entry should outline what would be done, the benefit it brings +to the project, the pre-requisites, both in knowledge and parts. They +should also list people interested in supporting people who want to work +on them. + +## Restructure Existing Documentation + +The goal is to improve the user experience and structure the documentation more +logically. The current situation makes it very hard for beginners, but also for +experienced developers to find anything in the coreboot documentation. + +One possible approach to restructure the documentation is to split it up such +that we divide the group of users into: + +* (End-)users +Most probably users which _just_ want to use coreboot as fast as possible. This +section should include guidelines on how to build coreboot, how to flash coreboot +and also which hardware is currently supported. + +* Developers +This section should more focus on the developer side-of-view. This section would +include how to get started developing coreboot, explaining the basic concepts of +coreboot and also give guideance on how to proceed after the first steps. + +* Knowledge area +This section is very tighlight coupled to the developer section and might be merged +into it. The _Knowledge area_ can give a technical deep dive on various drivers, +technologies, etc. + +* Community area +This section gives some room for the community: Youtube channels, conferences, +meetups, forums, chat, etc. + +A [first approach](https://review.coreboot.org/c/coreboot/+/40327) has already been made here and might be a basis for the work. +Most of the documentation is already there, but scattered around the documentation +folder. + +### Requirements +* Understanding on how a different groups of users might use the documentation area +* Basic understanding of how coreboot works (Can be worked out _on-the-fly_) + +### Mentors +* christian.walter@9elements.com +* TBD + +## Update Howto/Guides + +An important part to involve new people in the project, either as developer or +as enduser, are guides and how-to's. There are already some guides which need +to be updated to work, and could also be extended to multiple platforms, like +Fedora or Arch-Linux. Also guidance for setting up coreboot with a Windows +environment would be helpful. + +In addition, the vboot guidance needs an update/extensions, that the security +features within coreboot can be used by non-technical people. + +For developers, how to debug coreboot and various debugging techniques need +documentation. + +### Requirements +* Knowledge of virtual machines, how to install different OSs and set up the + toolchain on different operating systems +* Knowledge of debugging tools like gdb + +### Mentors +* christian.walter@9elements.com +* TBD + +## How to Support a New Board + +coreboot benefits from running on as many platforms as possible. Therefore we +want to encourage new developers on porting existing hardware to coreboot. +Guidance for those new developers need to be made such that they are able to +take the first steps supporting new mainboards, when the SoC support already +exists. There should be a 'how-to' guide for this. Also what are common problems +and how to solve those. + +### Requirements +* Knowledge of how to add support for a new mainboard in coreboot + +### Mentors +* christian.walter@9elements.com +* TBD + +## Payloads + +The current documentation of the payloads is not very effective. There should be +more detailed documentation on the payloads that can be selected via the make +menuconfig within coreboot. Also the use-cases should be described in more +detail: When to use which payload? What are the benefits of using payload X over +Y in a specific use-case ? + +In addition it should be made clear how additional functionality e.g. extend +LinuxBoot with more commands, can be achieved. + +### Requirements +* Basic knowledge of the supported payloads like SeaBIOS, TinanoCore, LinuxBoot, + GRUB, Linux, ... + + +### Mentors +* christian.walter@9elements.com +* TBD + + +## coreboot Util Documentation + +coreboot inherits a variaty of utilities. The current documentation only +provides a "one-liner" as an explanation. The list of util should be updated +with a more detailed explanation where possible. Also more "in-depths" +explanations should be added with examples if possible. + +### Requirements +* coreboot utilities + +### Mentors +* christian.walter@9elements.com +* TBD + + +## CBMEM Developer Guide + +CBMEM is the API that provides memory buffers for the use at OS runtime. It's a +core component and thus should be documented. Dos, don'ts and pitfalls when +using CBMEM. This "in-depth" guide is clearly for developers. + +### Requirements +* Deep understanding of coreboot's internals + +### Mentors +* TBD +* TBD + + +## CBFS Developer Guide + +CBFS is the in-flash filesystem that is used by coreboot. It's a core component +and thus should be documented. Update the existing CBFS.txt that still shows +version 1 of the implementation. A [first approach](https://review.coreboot.org/c/coreboot/+/33663/2) +has been made here. +This "in-depth" guide is clearly for developers. + +### Requirements +* Deep understanding of coreboot's internals + +### Mentors +* TBD +* TBD + + +## Region API Developer Guide + +The region API is used by coreboot when dealing with memory mapped objects that +can be split into chunks. It's a core component and thus should be documented. +This "in-depth" guide is clearly for developers. + +### Requirements +* Deep understanding of coreboot's internals + +### Mentors +* TBD +* TBD + diff --git a/Documentation/index.md b/Documentation/index.md index b636b61911..a7c4869db2 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -164,6 +164,7 @@ Contents: * [Tutorial](tutorial/index.md) * [Coding Style](coding_style.md) * [Project Ideas](contributing/project_ideas.md) +* [Documentation Ideas](contributing/documentation_ideas.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) * [Project services](community/services.md) From 3e42ee05d86c1de3ed23dddf08fd8e6451bdea92 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 27 Apr 2020 15:38:58 -0600 Subject: [PATCH 1332/1463] cpu/x86/mtrr/earlymtrr: Validate MTRR arguments The AMD64 Architecture Programmer's Manual, Volume 2: Systems Programming says the following about variable MTRRs: Variable Range Size and Alignment. The size and alignment of variable memory-ranges (MTRRs) and I/O ranges (IORRs) are restricted as follows: * The boundary on which a variable range is aligned must be equal to the range size. For example, a memory range of 16 Mbytes must be aligned on a 16-Mbyte boundary (i.e., naturally aligned). * The range size must be a power of 2 (2^n , 52 > n > 11), with a minimum allowable size of 4 Kbytes. For example, 4 Mbytes and 8 Mbytes are allowable memory range sizes, but 6 Mbytes is not allowable. Print out errors if these conditions are violated. I didn't assert since `set_var_mtrr` can be used in boot block before the serial console is enabled. BUG=b:147042464 TEST=Boot trembyle and see MTRR errors: MTRR Error: base 0xcc800000 must be aligned to size 0x1000000 Signed-off-by: Raul E Rangel Change-Id: I8b8c734c7599bd89cf9f212ed43c2dd5b2c8ba7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40762 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/cpu/x86/mtrr/earlymtrr.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index e8608fd9cc..f96b05061f 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -4,6 +4,8 @@ #include #include #include +#include +#include /* Get first available variable MTRR. * Returns var# if available, else returns -1. @@ -34,6 +36,15 @@ void set_var_mtrr( /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ /* FIXME: It only support 4G less range */ msr_t basem, maskm; + + if (!IS_POWER_OF_2(size)) + printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); + if (size < 4 * KiB) + printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size); + if (base % size != 0) + printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base, + size); + basem.lo = base | type; basem.hi = 0; wrmsr(MTRR_PHYS_BASE(reg), basem); From b887adf7a56f2877c41e808002f30841a6679eb6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:42:34 +0200 Subject: [PATCH 1333/1463] soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/broadwell/adsp.c | 4 +--- src/soc/intel/broadwell/hda.c | 12 +++++------- src/soc/intel/broadwell/me.c | 13 +++++-------- src/soc/intel/broadwell/minihd.c | 3 +-- src/soc/intel/broadwell/pch.c | 12 +++++------- src/soc/intel/broadwell/pcie.c | 10 +++------- src/soc/intel/broadwell/serialio.c | 5 +---- src/soc/intel/broadwell/smihandler.c | 8 ++++---- 8 files changed, 25 insertions(+), 42 deletions(-) diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 82904de39b..64b7d5e639 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -24,9 +24,7 @@ static void adsp_init(struct device *dev) u32 tmp32; /* Ensure memory and bus master are enabled */ - tmp32 = pci_read_config32(dev, PCI_COMMAND); - tmp32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, tmp32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 476d092f19..c5ce2e4989 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -84,7 +84,6 @@ static void hda_init(struct device *dev) u8 *base; struct resource *res; u32 codec_mask; - u32 reg32; /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -95,8 +94,7 @@ static void hda_init(struct device *dev) printk(BIOS_DEBUG, "HDA: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); hda_pch_init(dev, base); @@ -110,7 +108,7 @@ static void hda_init(struct device *dev) static void hda_enable(struct device *dev) { - u32 reg32; + u16 reg16; u8 reg8; reg8 = pci_read_config8(dev, 0x43); @@ -126,10 +124,10 @@ static void hda_enable(struct device *dev) printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n"); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device */ pch_disable_devfn(dev); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 730d77ed14..afe9c82705 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -600,17 +600,17 @@ static int mkhi_hmrfpo_lock_noack(void) static void intel_me_finalize(struct device *dev) { - u32 reg32; + u16 reg16; /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0) return; /* Make sure IO is disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -712,7 +712,6 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; - u32 reg32; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -723,9 +722,7 @@ static int intel_mei_setup(struct device *dev) mei_base_address = res2mmio(res, 0, 0); /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 2dcab97ae9..da0b42a47e 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -62,8 +62,7 @@ static void minihd_init(struct device *dev) printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index f6f3746d0e..ac6ac2ad7f 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -171,7 +171,7 @@ void pch_disable_devfn(struct device *dev) void broadwell_pch_enable_dev(struct device *dev) { - u32 reg32; + u16 reg16; /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { @@ -185,18 +185,16 @@ void broadwell_pch_enable_dev(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f81f0429f2..d506057d61 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -574,19 +574,14 @@ static void pch_pcie_early(struct device *dev) static void pch_pcie_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); @@ -597,6 +592,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG + u32 reg32; reg32 = pci_read_config32(dev, 0x20); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index a4922f7d73..9e6cf32a9c 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -160,14 +160,11 @@ static void serialio_init(struct device *dev) config_t *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; - u32 reg32; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index bce157d102..1d92c127cd 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -69,7 +69,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -79,9 +79,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); From 2ec1c13ac4a9724095ce71783fd52f70a0b1536d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 09:57:05 +0200 Subject: [PATCH 1334/1463] soc/intel/common: Fix 16-bit read/write PCI_COMMAND register Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/common/block/cse/cse.c | 10 ++++------ src/soc/intel/common/block/fast_spi/fast_spi.c | 10 ++++------ src/soc/intel/common/block/i2c/i2c.c | 2 +- src/soc/intel/common/block/p2sb/p2sb.c | 2 +- src/soc/intel/common/block/sata/sata.c | 3 +-- src/soc/intel/common/block/scs/early_mmc.c | 4 ++-- src/soc/intel/common/block/smm/smihandler.c | 8 ++++---- src/soc/intel/common/block/uart/uart.c | 4 ++-- 8 files changed, 19 insertions(+), 24 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 8daf6d2db6..fd6cb45dbb 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -75,7 +75,7 @@ void heci_init(uintptr_t tempbar) #else struct device *dev = PCH_DEV_CSE; #endif - u8 pcireg; + u16 pcireg; /* Assume it is already initialized, nothing else to do */ if (cse.sec_bar) @@ -87,18 +87,16 @@ void heci_init(uintptr_t tempbar) /* Assign Resources to HECI1 */ /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg = pci_read_config16(dev, PCI_COMMAND); pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_write_config16(dev, PCI_COMMAND, pcireg); /* Program Temporary BAR for HECI1 */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); cse.sec_bar = tempbar; } diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index b42030885e..e97bc2ee6a 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -260,22 +260,20 @@ void fast_spi_early_init(uintptr_t spi_base_address) #else struct device *dev = PCH_DEV_SPI; #endif - uint8_t pcireg; + uint16_t pcireg; /* Assign Resources to SPI Controller */ /* Clear BIT 1-2 SPI Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg = pci_read_config16(dev, PCI_COMMAND); pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_write_config16(dev, PCI_COMMAND, pcireg); /* Program Temporary BAR for SPI */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY); /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Initialize SPI to allow BIOS to write/erase on flash. */ fast_spi_init(); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index b9638fe242..38e96ee09b 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -69,7 +69,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus) /* Prepare early base address for access before memory */ base = dw_i2c_get_soc_early_base(bus); pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Take device out of reset */ diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 731ce50d4a..ff6c9dc26b 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -23,7 +23,7 @@ void p2sb_enable_bar(void) pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, + pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 40b9ac6078..93ba867889 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -34,8 +34,7 @@ static void sata_final(struct device *dev) u8 port_impl, temp; /* Set Bus Master */ - temp = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Read Ports Implemented (GHC_PI) */ port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 5980b6b137..00946b304d 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -32,14 +32,14 @@ static void enable_mmc_controller_bar(void) { pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, PRERAM_MMC_BASE_ADDRESS); - pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } static void disable_mmc_controller_bar(void) { pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, 0); - pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 44fe59d2c9..d8127a8c67 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -139,7 +139,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); @@ -152,9 +152,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If it's not a bridge, move on. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7d75bdd62f..9498060c5e 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -68,7 +68,7 @@ void uart_common_init(const struct device *device, uintptr_t baseaddr) pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); /* Enable memory access and bus master */ - pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); + pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); uart_lpss_init(device, baseaddr); } @@ -109,7 +109,7 @@ bool uart_is_controller_initialized(void) if (!base) return false; - if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE) + if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) != UART_PCI_ENABLE) return false; From ad87d1c8b9285cfed47b3ec060be520a467189ff Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:04:57 +0200 Subject: [PATCH 1335/1463] soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/cannonlake/bootblock/pch.c | 11 +++++------ src/soc/intel/cannonlake/graphics.c | 5 ++--- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index d67edea21c..516359daec 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -61,22 +61,21 @@ static uint32_t get_pmc_reg_base(void) static void soc_config_pwrmbase(void) { uint32_t reg32; + uint16_t reg16; /* * Assign Resources to PWRMBASE * Clear BIT 1-2 Command Register */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MEMORY); - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Enable PWRM in PMC */ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index c2f99570b7..1ecbb67098 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -48,9 +48,8 @@ void graphics_soc_init(struct device *dev) } /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); /* * GFX PEIM module inside FSP binary is taking care of graphics From 066e61f3ea1f65012b14467412e6b17351c87dc6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:28:20 +0200 Subject: [PATCH 1336/1463] soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/lpe.c | 2 +- src/soc/intel/braswell/smihandler.c | 8 ++++---- src/soc/intel/braswell/southcluster.c | 16 +++++++--------- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 9c4d2b1819..363b57ffa5 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -45,7 +45,7 @@ static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index e96f452341..188c14ee42 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -59,7 +59,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -69,9 +69,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 50ff608cc0..9b5784c2b5 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -440,9 +440,9 @@ static void hda_work_around(struct device *dev) */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); write32(gctl, read32(gctl) | 0x1); - pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config16(dev, PCI_COMMAND, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } @@ -526,7 +526,7 @@ static int place_device_in_d3hot(struct device *dev) /* Common PCI device function disable. */ void southcluster_enable_dev(struct device *dev) { - uint32_t reg32; + uint16_t reg16; printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); @@ -537,9 +537,9 @@ void southcluster_enable_dev(struct device *dev) dev_path(dev), slot, func); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Place device in D3Hot */ if (place_device_in_d3hot(dev) < 0) { @@ -552,9 +552,7 @@ void southcluster_enable_dev(struct device *dev) sc_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } From d2bbc68fa32ec60f8aa83870559beadbef0d1c9f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:12:33 +0200 Subject: [PATCH 1337/1463] soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register Change-Id: I353daf35c843521b089ff8411a9ba8c801605ff9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40846 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/lpe.c | 2 +- src/soc/intel/baytrail/lpss.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index e475defb98..e5b0e8788c 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -43,7 +43,7 @@ static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index a01310e70a..247bb18f90 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -21,7 +21,7 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 3d5c501038..552d27d1f4 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -74,7 +74,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, From f87ad9225c5dfafc266071bb4757065bca50966f Mon Sep 17 00:00:00 2001 From: Ryback Hung Date: Thu, 16 Apr 2020 19:34:03 -0700 Subject: [PATCH 1338/1463] mb/ocp/sonorapass: Add Sonora Pass Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: Andrey Petrov --- src/mainboard/ocp/sonorapass/Kconfig | 31 +++++++++ src/mainboard/ocp/sonorapass/Kconfig.name | 2 + src/mainboard/ocp/sonorapass/Makefile.inc | 1 + .../ocp/sonorapass/acpi/platform.asl | 44 ++++++++++++ src/mainboard/ocp/sonorapass/board.fmd | 10 +++ src/mainboard/ocp/sonorapass/board_info.txt | 5 ++ src/mainboard/ocp/sonorapass/bootblock.c | 68 +++++++++++++++++++ src/mainboard/ocp/sonorapass/devicetree.cb | 39 +++++++++++ src/mainboard/ocp/sonorapass/dsdt.asl | 59 ++++++++++++++++ 9 files changed, 259 insertions(+) create mode 100644 src/mainboard/ocp/sonorapass/Kconfig create mode 100644 src/mainboard/ocp/sonorapass/Kconfig.name create mode 100644 src/mainboard/ocp/sonorapass/Makefile.inc create mode 100644 src/mainboard/ocp/sonorapass/acpi/platform.asl create mode 100644 src/mainboard/ocp/sonorapass/board.fmd create mode 100644 src/mainboard/ocp/sonorapass/board_info.txt create mode 100644 src/mainboard/ocp/sonorapass/bootblock.c create mode 100644 src/mainboard/ocp/sonorapass/devicetree.cb create mode 100644 src/mainboard/ocp/sonorapass/dsdt.asl diff --git a/src/mainboard/ocp/sonorapass/Kconfig b/src/mainboard/ocp/sonorapass/Kconfig new file mode 100644 index 0000000000..7e8e20ee7c --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +if BOARD_OCP_SONORAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select IPMI_KCS + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default "ocp/sonorapass" + +config MAINBOARD_PART_NUMBER + string + default "SonoraPass" + +config MAINBOARD_FAMILY + string + default "SonoraPass" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif diff --git a/src/mainboard/ocp/sonorapass/Kconfig.name b/src/mainboard/ocp/sonorapass/Kconfig.name new file mode 100644 index 0000000000..90e7f3dfdf --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_SONORAPASS + bool "SonoraPass" diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc new file mode 100644 index 0000000000..8501868fbf --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/ocp/sonorapass/acpi/platform.asl b/src/mainboard/ocp/sonorapass/acpi/platform.asl new file mode 100644 index 0000000000..75c1b92f1e --- /dev/null +++ b/src/mainboard/ocp/sonorapass/acpi/platform.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ocp/sonorapass/board.fmd b/src/mainboard/ocp/sonorapass/board.fmd new file mode 100644 index 0000000000..e28bcf08c0 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board.fmd @@ -0,0 +1,10 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x2fd8000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fc5000 + } + FMAP@0x03000000 0x800 + RW_MRC_CACHE@0x3000800 0x10000 + COREBOOT(CBFS)@0x3010800 +} diff --git a/src/mainboard/ocp/sonorapass/board_info.txt b/src/mainboard/ocp/sonorapass/board_info.txt new file mode 100644 index 0000000000..bbf3ee9b9d --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: SonoraPass +Category: server +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/ocp/sonorapass/bootblock.c b/src/mainboard/ocp/sonorapass/bootblock.c new file mode 100644 index 0000000000..ba02208cab --- /dev/null +++ b/src/mainboard/ocp/sonorapass/bootblock.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); + aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH); + + /* Enable UART function pin*/ + aspeed_enable_uart_pin(serial_dev); +} diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb new file mode 100644 index 0000000000..05dac455e3 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/devicetree.cb @@ -0,0 +1,39 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + end + + end +end diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl new file mode 100644 index 0000000000..3dc45d5f2c --- /dev/null +++ b/src/mainboard/ocp/sonorapass/dsdt.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include + #include + + } + + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + } + } + +} From 6468d87dded4be460707533d3de938f709c7d460 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:22:42 +0200 Subject: [PATCH 1339/1463] soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register Change-Id: I9b15b5458bb8140fa9bb6b0ffb6b9c78e8d8a93b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40848 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/smihandler.c | 8 ++++---- src/soc/intel/baytrail/southcluster.c | 16 +++++++--------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index da97535ab8..6ca4e6478b 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -58,7 +58,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -68,9 +68,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index b40609674f..3f83e08a4c 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -328,9 +328,9 @@ static void hda_work_around(struct device *dev) * that requires setting up the 64-bit BAR. */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); write32(gctl, read32(gctl) | 0x1); - pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config16(dev, PCI_COMMAND, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } @@ -452,7 +452,7 @@ static int place_device_in_d3hot(struct device *dev) /* Common PCI device function disable. */ void southcluster_enable_dev(struct device *dev) { - uint32_t reg32; + uint16_t reg16; if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); @@ -461,10 +461,10 @@ void southcluster_enable_dev(struct device *dev) dev_path(dev), slot, func); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Place device in D3Hot */ if (place_device_in_d3hot(dev) < 0) { @@ -477,9 +477,7 @@ void southcluster_enable_dev(struct device *dev) sc_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } From ed7d91d2579ea9a8eb6b62972ad7beeb2f136d8a Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 20 Apr 2020 17:20:23 -0700 Subject: [PATCH 1340/1463] mb/ocp/sonorapass: Populate FSP-M parameters Since CPX FSP headers are not released yet, populate certain settings with hard-coded offsets. Provided values are probably not correct and I do not understand what they mean and there is no documentation available yet. However they were found to work to a certain degree. TEST=tested on OCP Sonora Pass EVT Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554 Reviewed-by: Andrey Petrov Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/mainboard/ocp/sonorapass/Makefile.inc | 1 + src/mainboard/ocp/sonorapass/romstage.c | 28 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 src/mainboard/ocp/sonorapass/romstage.c diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc index 8501868fbf..9bd017393c 100644 --- a/src/mainboard/ocp/sonorapass/Makefile.inc +++ b/src/mainboard/ocp/sonorapass/Makefile.inc @@ -1 +1,2 @@ bootblock-y += bootblock.c +romstage-y += romstage.c diff --git a/src/mainboard/ocp/sonorapass/romstage.c b/src/mainboard/ocp/sonorapass/romstage.c new file mode 100644 index 0000000000..1acd8c3964 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *start = (void *) m_cfg; + + // BoardId + *((uint8_t *) (start + 140)) = 0x1d; + // BoardTypeBitmask + *((uint32_t *) (start + 104)) = 0x11111111; + // DebugPrintLevel + *((uint8_t *) (start + 45)) = 8; + // KtiLinkSpeedMode + *((uint8_t *) (start + 64)) = 0; + // mmiolSize + *((uint32_t *) (start + 88)) = 0; + // mmiohBase + *((uint32_t *) (start + 92)) = 0x2000; + // KtiPrefetchEn + *((uint8_t *) (start + 53)) = 2; + // KtiFpgaEnable + *((uint8_t *) (start + 55)) = 0; + *((uint8_t *) (start + 56)) = 0; +} From 89d2aa0cdc43a85258ff6b6ca2c781339081025a Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 20:56:50 +0300 Subject: [PATCH 1341/1463] mb/tiogapass: use common driver to configure GPIO According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with AMI firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39427 Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/bootblock.c | 4 + src/mainboard/ocp/tiogapass/gpio.h | 544 ++++++++++++++++++++++++ src/mainboard/ocp/tiogapass/romstage.c | 16 +- 3 files changed, 552 insertions(+), 12 deletions(-) create mode 100644 src/mainboard/ocp/tiogapass/gpio.h diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index 67808ef72a..dbb3b6a93f 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -10,6 +10,7 @@ #include #include #include +#include "gpio.h" /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ #define PCR_DMI_LPCIOD 0x2770 @@ -53,6 +54,9 @@ static uint8_t com_to_ast_sio(uint8_t com) void bootblock_mainboard_early_init(void) { + /* pre-configure Lewisburg PCH GPIO pads */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + /* Open IO windows */ enable_espi_lpc_io_windows(); diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h new file mode 100644 index 0000000000..823f7972fb --- /dev/null +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -0,0 +1,544 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef CFG_PCH_GPIO_H +#define CFG_PCH_GPIO_H + +#include + +/* Pad configuration */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - GPIO */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), + /* GPP_A1 - LAD0 */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), + /* GPP_A2 - LAD1 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), + /* GPP_A3 - LAD2 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), + /* GPP_A4 - LAD3 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), + /* GPP_A5 - LFRAME# */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), + /* GPP_A6 - SERIRQ */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), + /* GPP_A7 - PIRQA# */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010), + /* GPP_A8 - CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000500, 0x00000010), + /* GPP_A9 - CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x00000010), + /* GPP_A10 - GPIO */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000102, 0x00000010), + /* GPP_A11 - GPIO */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + /* GPP_A12 - GPIO */ + _PAD_CFG_STRUCT(GPP_A12, 0x84000102, 0x00000010), + /* GPP_A13 - GPIO */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000102, 0x00000010), + /* GPP_A14 - GPIO */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000102, 0x00000010), + /* GPP_A15 - GPIO */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000102, 0x00000010), + /* GPP_A16 - GPIO */ + _PAD_CFG_STRUCT(GPP_A16, 0x44000102, 0x00000010), + /* GPP_A17 - GPIO */ + _PAD_CFG_STRUCT(GPP_A17, 0x44000102, 0x00000010), + /* GPP_A18 - GPIO */ + _PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x00000010), + /* GPP_A19 - RESERVED */ + /* GPP_A20 - GPIO */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000102, 0x00000010), + /* GPP_A21 - GPIO */ + _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x00000010), + /* GPP_A22 - GPIO */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000102, 0x00000010), + /* GPP_A23 - GPIO */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x00000010), + + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - CORE_VID0 */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000600, 0x00000010), + /* GPP_B1 - CORE_VID1 */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000600, 0x00000010), + /* GPP_B2 - GPIO */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000102, 0x00000010), + /* GPP_B3 - GPIO */ + _PAD_CFG_STRUCT(GPP_B3, 0x44000102, 0x00000010), + /* GPP_B4 - GPIO */ + _PAD_CFG_STRUCT(GPP_B4, 0x44000102, 0x00000010), + /* GPP_B5 - GPIO */ + _PAD_CFG_STRUCT(GPP_B5, 0x44000102, 0x00000010), + /* GPP_B6 - GPIO */ + _PAD_CFG_STRUCT(GPP_B6, 0x84000102, 0x00000010), + /* GPP_B7 - GPIO */ + _PAD_CFG_STRUCT(GPP_B7, 0x84000102, 0x00000010), + /* GPP_B8 - GPIO */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000102, 0x00000010), + /* GPP_B9 - GPIO */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000102, 0x00000010), + /* GPP_B10 - GPIO */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x00000010), + /* GPP_B11 - GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x00000010), + /* GPP_B12 - GLB_RST_WARN_N# */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000600, 0x00000010), + /* GPP_B13 - PLTRST# */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000600, 0x00000010), + /* GPP_B14 - SPKR */ + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x00000010), + /* GPP_B15 - GPIO */ + _PAD_CFG_STRUCT(GPP_B15, 0x44000102, 0x00000010), + /* GPP_B16 - GPIO */ + _PAD_CFG_STRUCT(GPP_B16, 0x44000102, 0x00000010), + /* GPP_B17 - GPIO */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000102, 0x00000010), + /* GPP_B18 - GPIO */ + _PAD_CFG_STRUCT(GPP_B18, 0x44000102, 0x00000010), + /* GPP_B19 - GPIO */ + _PAD_CFG_STRUCT(GPP_B19, 0x44000201, 0x00000010), + /* GPP_B20 - GPIO */ + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x00000010), + /* GPP_B21 - GPIO */ + _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x00000010), + /* GPP_B22 - GPIO */ + _PAD_CFG_STRUCT(GPP_B22, 0x44000200, 0x00000010), + /* GPP_B23 - PCHHOT# */ + _PAD_CFG_STRUCT(GPP_B23, 0x00000a00, 0x00000010), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - GPIO */ + _PAD_CFG_STRUCT(GPP_F0, 0x44000102, 0x00000010), + /* GPP_F1 - GPIO */ + _PAD_CFG_STRUCT(GPP_F1, 0x44000102, 0x00000010), + /* GPP_F2 - GPIO */ + _PAD_CFG_STRUCT(GPP_F2, 0x44000102, 0x00000010), + /* GPP_F3 - GPIO */ + _PAD_CFG_STRUCT(GPP_F3, 0x44000102, 0x00000010), + /* GPP_F4 - GPIO */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x00000010), + /* GPP_F5 - GPIO */ + _PAD_CFG_STRUCT(GPP_F5, 0x44000101, 0x00000010), + /* GPP_F6 - GPIO */ + _PAD_CFG_STRUCT(GPP_F6, 0x84000200, 0x00000010), + /* GPP_F7 - GPIO */ + _PAD_CFG_STRUCT(GPP_F7, 0x84000200, 0x00000010), + /* GPP_F8 - GPIO */ + _PAD_CFG_STRUCT(GPP_F8, 0x84000200, 0x00000010), + /* GPP_F9 - GPIO */ + _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000010), + /* GPP_F10 - SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F10, 0x44000600, 0x00000010), + /* GPP_F11 - SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F11, 0x44000600, 0x00000010), + /* GPP_F12 - GPIO */ + _PAD_CFG_STRUCT(GPP_F12, 0x44000102, 0x00000010), + /* GPP_F13 - SATA_SDATAOUT2 */ + _PAD_CFG_STRUCT(GPP_F13, 0x44000600, 0x00000010), + /* GPP_F14 - SSATA_LED# */ + _PAD_CFG_STRUCT(GPP_F14, 0x44000e00, 0x00000010), + /* GPP_F15 - GPIO */ + _PAD_CFG_STRUCT(GPP_F15, 0x44000102, 0x00000010), + /* GPP_F16 - GPIO */ + _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x00000010), + /* GPP_F17 - GPIO */ + _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x00000010), + /* GPP_F18 - GPIO */ + _PAD_CFG_STRUCT(GPP_F18, 0x44000102, 0x00000010), + /* GPP_F19 - LAN_SMBCLK */ + _PAD_CFG_STRUCT(GPP_F19, 0x44000502, 0x00000010), + /* GPP_F20 - LAN_SMBDATA */ + _PAD_CFG_STRUCT(GPP_F20, 0x44000502, 0x00000010), + /* GPP_F21 - LAN_SMBALRT# */ + _PAD_CFG_STRUCT(GPP_F21, 0x44000602, 0x00000010), + /* GPP_F22 - SSATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F22, 0x44000e00, 0x00000010), + /* GPP_F23 - SSATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F23, 0x44000e00, 0x00000010), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + /* GPP_C2 - SMBALERT# */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000502, 0x00000010), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + /* GPP_C5 - GPIO */ + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x00000000), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + /* GPP_C8 - GPIO */ + _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x00000010), + /* GPP_C9 - GPIO */ + _PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x00000010), + /* GPP_C10 - GPIO */ + _PAD_CFG_STRUCT(GPP_C10, 0x86000103, 0x00000000), + /* GPP_C11 - GPIO */ + _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x00000010), + /* GPP_C12 - GPIO */ + _PAD_CFG_STRUCT(GPP_C12, 0x44000103, 0x00000010), + /* GPP_C13 - GPIO */ + _PAD_CFG_STRUCT(GPP_C13, 0x44000103, 0x00000010), + /* GPP_C14 - GPIO */ + _PAD_CFG_STRUCT(GPP_C14, 0x80080102, 0x00000000), + /* GPP_C15 - GPIO */ + _PAD_CFG_STRUCT(GPP_C15, 0x44000102, 0x00000010), + /* GPP_C16 - GPIO */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000102, 0x00000010), + /* GPP_C17 - GPIO */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000102, 0x00000010), + /* GPP_C18 - GPIO */ + _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x00000010), + /* GPP_C19 - GPIO */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x00000010), + /* GPP_C20 - RESERVED */ + /* GPP_C21 - GPIO */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x00000010), + /* GPP_C22 - GPIO */ + _PAD_CFG_STRUCT(GPP_C22, 0x80040102, 0x00000000), + /* GPP_C23 - GPIO */ + _PAD_CFG_STRUCT(GPP_C23, 0x40840102, 0x00000000), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + _PAD_CFG_STRUCT(GPP_D0, 0x80840102, 0x00000000), + /* GPP_D1 - GPIO */ + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x00000010), + /* GPP_D2 - GPIO */ + _PAD_CFG_STRUCT(GPP_D2, 0x84000102, 0x00000010), + /* GPP_D3 - GPIO */ + _PAD_CFG_STRUCT(GPP_D3, 0x84000102, 0x00000010), + /* GPP_D4 - GPIO */ + _PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x00000010), + /* GPP_D5 - GPIO */ + _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x00000010), + /* GPP_D6 - GPIO */ + _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x00000010), + /* GPP_D7 - GPIO */ + _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x00000010), + /* GPP_D8 - GPIO */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x00000010), + /* GPP_D9 - GPIO */ + _PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x00000010), + /* GPP_D10 - GPIO */ + _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x00000010), + /* GPP_D11 - GPIO */ + _PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x00000010), + /* GPP_D12 - GPIO */ + _PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x00000010), + /* GPP_D13 - GPIO */ + _PAD_CFG_STRUCT(GPP_D13, 0x44000102, 0x00000010), + /* GPP_D14 - GPIO */ + _PAD_CFG_STRUCT(GPP_D14, 0x44000102, 0x00000010), + /* GPP_D15 - SSATA_SDATAOUT0 */ + _PAD_CFG_STRUCT(GPP_D15, 0x44000e00, 0x00000010), + /* GPP_D16 - GPIO */ + _PAD_CFG_STRUCT(GPP_D16, 0x44000102, 0x00000010), + /* GPP_D17 - GPIO */ + _PAD_CFG_STRUCT(GPP_D17, 0x44000102, 0x00000010), + /* GPP_D18 - GPIO */ + _PAD_CFG_STRUCT(GPP_D18, 0x44000102, 0x00000010), + /* GPP_D19 - GPIO */ + _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x00000010), + /* GPP_D20 - GPIO */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000102, 0x00000010), + /* GPP_D21 - GPIO */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x00000010), + /* GPP_D22 - GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0x44000102, 0x00000010), + /* GPP_D23 - GPIO */ + _PAD_CFG_STRUCT(GPP_D23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - GPIO */ + _PAD_CFG_STRUCT(GPP_E0, 0x40040102, 0x00000010), + /* GPP_E1 - GPIO */ + _PAD_CFG_STRUCT(GPP_E1, 0x40040102, 0x00000010), + /* GPP_E2 - GPIO */ + _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x00000010), + /* GPP_E3 - CPU_GP0 */ + _PAD_CFG_STRUCT(GPP_E3, 0x44000502, 0x00000010), + /* GPP_E4 - GPIO */ + _PAD_CFG_STRUCT(GPP_E4, 0x44000102, 0x00000010), + /* GPP_E5 - GPIO */ + _PAD_CFG_STRUCT(GPP_E5, 0x44000102, 0x00000010), + /* GPP_E6 - GPIO */ + _PAD_CFG_STRUCT(GPP_E6, 0x44000102, 0x00000010), + /* GPP_E7 - GPIO */ + _PAD_CFG_STRUCT(GPP_E7, 0x44000102, 0x00000010), + /* GPP_E8 - SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000600, 0x00000010), + /* GPP_E9 - USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E9, 0x44000502, 0x00000010), + /* GPP_E10 - GPIO */ + _PAD_CFG_STRUCT(GPP_E10, 0x44000102, 0x00000010), + /* GPP_E11 - GPIO */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000102, 0x00000010), + /* GPP_E12 - GPIO */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000102, 0x00000010), + + /* ------- GPIO Community 2 ------- */ + /* -------- GPIO Group GPD -------- */ + /* GPD0 - RESERVED */ + /* GPD1 - GPIO */ + _PAD_CFG_STRUCT(GPD1, 0x04000102, 0x00000000), + /* GPD2 - GPIO */ + _PAD_CFG_STRUCT(GPD2, 0x04000102, 0x00000000), + /* GPD3 - PWRBTN# */ + _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + /* GPD4 - SLP_S3# */ + _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + /* GPD5 - SLP_S4# */ + _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + /* GPD6 - GPIO */ + _PAD_CFG_STRUCT(GPD6, 0x04000100, 0x00000000), + /* GPD7 - GPIO */ + _PAD_CFG_STRUCT(GPD7, 0x04000103, 0x00000000), + /* GPD8 - GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + /* GPD9 - GPIO */ + _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + /* GPD10 - GPIO */ + _PAD_CFG_STRUCT(GPD10, 0x04000102, 0x00000000), + /* GPD11 - GBEPHY */ + _PAD_CFG_STRUCT(GPD11, 0x04000500, 0x00000000), + + /* ------- GPIO Community 3 ------- */ + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - LAN_TDO */ + _PAD_CFG_STRUCT(GPP_I0, 0x44000900, 0x00000010), + /* GPP_I1 - LAN_TCK */ + _PAD_CFG_STRUCT(GPP_I1, 0x44000a02, 0x00000010), + /* GPP_I2 - LAN_TMS */ + _PAD_CFG_STRUCT(GPP_I2, 0x44000a02, 0x00000010), + /* GPP_I3 - LAN_TDI */ + _PAD_CFG_STRUCT(GPP_I3, 0x44000a02, 0x00000010), + /* GPP_I4 - GPIO */ + _PAD_CFG_STRUCT(GPP_I4, 0x44000102, 0x00000010), + /* GPP_I5 - GPIO */ + _PAD_CFG_STRUCT(GPP_I5, 0x44000102, 0x00000010), + /* GPP_I6 - GPIO */ + _PAD_CFG_STRUCT(GPP_I6, 0x44000102, 0x00000010), + /* GPP_I7 - LAN_TRST_IN */ + _PAD_CFG_STRUCT(GPP_I7, 0x44000902, 0x00000010), + /* GPP_I8 - GPIO */ + _PAD_CFG_STRUCT(GPP_I8, 0x44000102, 0x00000010), + /* GPP_I9 - GPIO */ + _PAD_CFG_STRUCT(GPP_I9, 0x44000102, 0x00000010), + /* GPP_I10 - GPIO */ + _PAD_CFG_STRUCT(GPP_I10, 0x44000102, 0x00000010), + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_J ------- */ + /* GPP_J0 - LAN_LED_P0_0 */ + _PAD_CFG_STRUCT(GPP_J0, 0x44000600, 0x00000010), + /* GPP_J1 - LAN_LED_P0_1 */ + _PAD_CFG_STRUCT(GPP_J1, 0x44000600, 0x00000010), + /* GPP_J2 - LAN_LED_P1_0 */ + _PAD_CFG_STRUCT(GPP_J2, 0x44000600, 0x00000010), + /* GPP_J3 - LAN_LED_P1_1 */ + _PAD_CFG_STRUCT(GPP_J3, 0x44000600, 0x00000010), + /* GPP_J4 - LAN_LED_P2_0 */ + _PAD_CFG_STRUCT(GPP_J4, 0x44000600, 0x00000010), + /* GPP_J5 - LAN_LED_P2_1 */ + _PAD_CFG_STRUCT(GPP_J5, 0x44000600, 0x00000010), + /* GPP_J6 - LAN_LED_P3_0 */ + _PAD_CFG_STRUCT(GPP_J6, 0x44000600, 0x00000010), + /* GPP_J7 - LAN_LED_P3_1 */ + _PAD_CFG_STRUCT(GPP_J7, 0x44000600, 0x00000010), + /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ + _PAD_CFG_STRUCT(GPP_J8, 0x44000602, 0x00000010), + /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ + _PAD_CFG_STRUCT(GPP_J9, 0x44000402, 0x00000010), + /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ + _PAD_CFG_STRUCT(GPP_J10, 0x44000602, 0x00000010), + /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ + _PAD_CFG_STRUCT(GPP_J11, 0x44000402, 0x00000010), + /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ + _PAD_CFG_STRUCT(GPP_J12, 0x44000602, 0x00000010), + /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ + _PAD_CFG_STRUCT(GPP_J13, 0x44000402, 0x00000010), + /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ + _PAD_CFG_STRUCT(GPP_J14, 0x44000602, 0x00000010), + /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ + _PAD_CFG_STRUCT(GPP_J15, 0x44000402, 0x00000010), + /* GPP_J16 - LAN_SDP_P0_0 */ + _PAD_CFG_STRUCT(GPP_J16, 0x44000502, 0x00000010), + /* GPP_J17 - GPIO */ + _PAD_CFG_STRUCT(GPP_J17, 0x44000102, 0x00000010), + /* GPP_J18 - LAN_SDP_P1_0 */ + _PAD_CFG_STRUCT(GPP_J18, 0x44000502, 0x00000010), + /* GPP_J19 - GPIO */ + _PAD_CFG_STRUCT(GPP_J19, 0x44000102, 0x00000010), + /* GPP_J20 - LAN_SDP_P2_0 */ + _PAD_CFG_STRUCT(GPP_J20, 0x44000502, 0x00000010), + /* GPP_J21 - GPIO */ + _PAD_CFG_STRUCT(GPP_J21, 0x44000102, 0x00000010), + /* GPP_J22 - LAN_SDP_P3_0 */ + _PAD_CFG_STRUCT(GPP_J22, 0x44000502, 0x00000010), + /* GPP_J23 - GPIO */ + _PAD_CFG_STRUCT(GPP_J23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_K ------- */ + /* GPP_K0 - GPIO */ + _PAD_CFG_STRUCT(GPP_K0, 0x44000100, 0x00000010), + /* GPP_K1 - GPIO */ + _PAD_CFG_STRUCT(GPP_K1, 0x44000100, 0x00000010), + /* GPP_K2 - GPIO */ + _PAD_CFG_STRUCT(GPP_K2, 0x44000100, 0x00000010), + /* GPP_K3 - GPIO */ + _PAD_CFG_STRUCT(GPP_K3, 0x44000100, 0x00000010), + /* GPP_K4 - GPIO */ + _PAD_CFG_STRUCT(GPP_K4, 0x44000100, 0x00000010), + /* GPP_K5 - GPIO */ + _PAD_CFG_STRUCT(GPP_K5, 0x44000102, 0x00000010), + /* GPP_K6 - GPIO */ + _PAD_CFG_STRUCT(GPP_K6, 0x44000102, 0x00000010), + /* GPP_K7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_K7, 0x44000600, 0x00000010), + /* GPP_K8 - LAN_NCSI_ARB_IN */ + _PAD_CFG_STRUCT(GPP_K8, 0x44000502, 0x00000010), + /* GPP_K9 - LAN_NCSI_ARB_OUT */ + _PAD_CFG_STRUCT(GPP_K9, 0x44000602, 0x00000010), + /* GPP_K10 - PE_RST# */ + _PAD_CFG_STRUCT(GPP_K10, 0x44000502, 0x00000010), + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_G ------- */ + /* GPP_G0 - GPIO */ + _PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x00000010), + /* GPP_G1 - GPIO */ + _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x00000010), + /* GPP_G2 - GPIO */ + _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000010), + /* GPP_G3 - GPIO */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000010), + /* GPP_G4 - GPIO */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000102, 0x00000010), + /* GPP_G5 - GPIO */ + _PAD_CFG_STRUCT(GPP_G5, 0x44000102, 0x00000010), + /* GPP_G6 - GPIO */ + _PAD_CFG_STRUCT(GPP_G6, 0x44000102, 0x00000010), + /* GPP_G7 - GPIO */ + _PAD_CFG_STRUCT(GPP_G7, 0x44000102, 0x00000010), + /* GPP_G8 - GPIO */ + _PAD_CFG_STRUCT(GPP_G8, 0x44000102, 0x00000010), + /* GPP_G9 - GPIO */ + _PAD_CFG_STRUCT(GPP_G9, 0x44000102, 0x00000010), + /* GPP_G10 - GPIO */ + _PAD_CFG_STRUCT(GPP_G10, 0x44000102, 0x00000010), + /* GPP_G11 - GPIO */ + _PAD_CFG_STRUCT(GPP_G11, 0x44000102, 0x00000010), + /* GPP_G12 - GPIO */ + _PAD_CFG_STRUCT(GPP_G12, 0x44000103, 0x00000010), + /* GPP_G13 - GPIO */ + _PAD_CFG_STRUCT(GPP_G13, 0x44000103, 0x00000010), + /* GPP_G14 - GPIO */ + _PAD_CFG_STRUCT(GPP_G14, 0x44000101, 0x00000010), + /* GPP_G15 - GPIO */ + _PAD_CFG_STRUCT(GPP_G15, 0x44000101, 0x00000010), + /* GPP_G16 - GPIO */ + _PAD_CFG_STRUCT(GPP_G16, 0x44000101, 0x00000010), + /* GPP_G17 - ADR_COMPLETE */ + _PAD_CFG_STRUCT(GPP_G17, 0x44000600, 0x00000010), + /* GPP_G18 - NMI# */ + _PAD_CFG_STRUCT(GPP_G18, 0x44000600, 0x00000010), + /* GPP_G19 - SMI# */ + _PAD_CFG_STRUCT(GPP_G19, 0x44000600, 0x00000010), + /* GPP_G20 - RESERVED */ + /* GPP_G21 - GPIO */ + _PAD_CFG_STRUCT(GPP_G21, 0x44000100, 0x00000010), + /* GPP_G22 - GPIO */ + _PAD_CFG_STRUCT(GPP_G22, 0x44000201, 0x00000010), + /* GPP_G23 - GPIO */ + _PAD_CFG_STRUCT(GPP_G23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + _PAD_CFG_STRUCT(GPP_H0, 0x44000102, 0x00000010), + /* GPP_H1 - GPIO */ + _PAD_CFG_STRUCT(GPP_H1, 0x44000102, 0x00000010), + /* GPP_H2 - GPIO */ + _PAD_CFG_STRUCT(GPP_H2, 0x44000102, 0x00000010), + /* GPP_H3 - GPIO */ + _PAD_CFG_STRUCT(GPP_H3, 0x44000102, 0x00000010), + /* GPP_H4 - GPIO */ + _PAD_CFG_STRUCT(GPP_H4, 0x44000102, 0x00000010), + /* GPP_H5 - RESERVED */ + /* GPP_H6 - GPIO */ + _PAD_CFG_STRUCT(GPP_H6, 0x44000102, 0x00000010), + /* GPP_H7 - GPIO */ + _PAD_CFG_STRUCT(GPP_H7, 0x44000102, 0x00000010), + /* GPP_H8 - GPIO */ + _PAD_CFG_STRUCT(GPP_H8, 0x44000102, 0x00000010), + /* GPP_H9 - GPIO */ + _PAD_CFG_STRUCT(GPP_H9, 0x44000102, 0x00000010), + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + /* GPP_H12 - GPIO */ + _PAD_CFG_STRUCT(GPP_H12, 0x44000102, 0x00000010), + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + /* GPP_H15 - GPIO */ + _PAD_CFG_STRUCT(GPP_H15, 0x84000102, 0x00000010), + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + /* GPP_H18 - GPIO */ + _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x00000010), + /* GPP_H19 - GPIO */ + _PAD_CFG_STRUCT(GPP_H19, 0x84000102, 0x00000010), + /* GPP_H20 - GPIO */ + _PAD_CFG_STRUCT(GPP_H20, 0x44000102, 0x00000010), + /* GPP_H21 - GPIO */ + _PAD_CFG_STRUCT(GPP_H21, 0x44000102, 0x00000010), + /* GPP_H22 - GPIO */ + _PAD_CFG_STRUCT(GPP_H22, 0x44000102, 0x00000010), + /* GPP_H23 - GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_L ------- */ + /* GPP_L0 - RESERVED */ + /* GPP_L1 - CSME_INTR_OUT */ + _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + /* GPP_L2 - GPIO */ + _PAD_CFG_STRUCT(GPP_L2, 0x44000100, 0x00000010), + /* GPP_L3 - GPIO */ + _PAD_CFG_STRUCT(GPP_L3, 0x44000100, 0x00000010), + /* GPP_L4 - GPIO */ + _PAD_CFG_STRUCT(GPP_L4, 0x44000100, 0x00000010), + /* GPP_L5 - GPIO */ + _PAD_CFG_STRUCT(GPP_L5, 0x44000100, 0x00000010), + /* GPP_L6 - GPIO */ + _PAD_CFG_STRUCT(GPP_L6, 0x44000102, 0x00000010), + /* GPP_L7 - GPIO */ + _PAD_CFG_STRUCT(GPP_L7, 0x44000102, 0x00000010), + /* GPP_L8 - GPIO */ + _PAD_CFG_STRUCT(GPP_L8, 0x44000102, 0x00000010), + /* GPP_L9 - GPIO */ + _PAD_CFG_STRUCT(GPP_L9, 0x44000102, 0x00000010), + /* GPP_L10 - GPIO */ + _PAD_CFG_STRUCT(GPP_L10, 0x44000100, 0x00000010), + /* GPP_L11 - GPIO */ + _PAD_CFG_STRUCT(GPP_L11, 0x44000100, 0x00000010), + /* GPP_L12 - GPIO */ + _PAD_CFG_STRUCT(GPP_L12, 0x44000100, 0x00000010), + /* GPP_L13 - GPIO */ + _PAD_CFG_STRUCT(GPP_L13, 0x44000100, 0x00000010), + /* GPP_L14 - GPIO */ + _PAD_CFG_STRUCT(GPP_L14, 0x44000100, 0x00000010), + /* GPP_L15 - GPIO */ + _PAD_CFG_STRUCT(GPP_L15, 0x44000100, 0x00000010), + /* GPP_L16 - GPIO */ + _PAD_CFG_STRUCT(GPP_L16, 0x44000100, 0x00000010), + /* GPP_L17 - GPIO */ + _PAD_CFG_STRUCT(GPP_L17, 0x44000100, 0x00000010), + /* GPP_L18 - GPIO */ + _PAD_CFG_STRUCT(GPP_L18, 0x44000100, 0x00000010), + /* GPP_L19 - GPIO */ + _PAD_CFG_STRUCT(GPP_L19, 0x44000100, 0x00000010), +}; + +#endif /* CFG_PCH_GPIO_H */ diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index e4a188d35d..41f785638a 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -20,7 +20,6 @@ #include #include -#include "skxsp_tp_gpio.h" #include "skxsp_tp_iio.h" static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; @@ -39,16 +38,6 @@ static void oem_update_iio(FSPM_UPD *mupd) = IIO_BIFURCATE_xxx8xxx8; } -/* -* Configure GPIO depend on platform -*/ -static void mainboard_config_gpios(FSPM_UPD *mupd) -{ - mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table; - mupd->FspmConfig.GpioConfig.NumberOfEntries = - sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG); -} - static void mainboard_config_iio(FSPM_UPD *mupd) { memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); @@ -74,6 +63,9 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { - mainboard_config_gpios(mupd); mainboard_config_iio(mupd); + + /* do not configure GPIO controller inside FSP-M */ + mupd->FspmConfig.GpioConfig.GpioTable = NULL; + mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; } From 2bb3e7806673b6d806bc43aa4b68d0ea36badbad Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 20:56:50 +0300 Subject: [PATCH 1342/1463] mb/ocp/tiogapass: rework GPIOs configuration using macros This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input (GPI). The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731 Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/gpio.h | 484 ++++++++++++++--------------- 1 file changed, 242 insertions(+), 242 deletions(-) diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h index 823f7972fb..b05f53692b 100644 --- a/src/mainboard/ocp/tiogapass/gpio.h +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -6,539 +6,539 @@ #include -/* Pad configuration */ +/* Pad configuration table for C621 Lewisburg PCH */ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - GPIO */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A2 - LAD1 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A3 - LAD2 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A4 - LAD3 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A5 - LFRAME# */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A6 - SERIRQ */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A7 - PIRQA# */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A8 - CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000500, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A9 - CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A10 - GPIO */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ - _PAD_CFG_STRUCT(GPP_A12, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, DRIVER), /* GPP_A13 - GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, DEEP, OFF, DRIVER), /* GPP_A14 - GPIO */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, DRIVER), /* GPP_A15 - GPIO */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A16, NONE, DEEP, OFF, DRIVER), /* GPP_A17 - GPIO */ - _PAD_CFG_STRUCT(GPP_A17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, DRIVER), /* GPP_A18 - GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, DRIVER), /* GPP_A19 - RESERVED */ /* GPP_A20 - GPIO */ - _PAD_CFG_STRUCT(GPP_A20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, DRIVER), /* GPP_A21 - GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_A21, 1, DEEP), /* GPP_A22 - GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, DRIVER), /* GPP_A23 - GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B1 - CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B2 - GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, DRIVER), /* GPP_B4 - GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, DRIVER), /* GPP_B5 - GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, DRIVER), /* GPP_B6 - GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, DRIVER), /* GPP_B7 - GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, DRIVER), /* GPP_B8 - GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, DRIVER), /* GPP_B9 - GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, DRIVER), /* GPP_B10 - GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, DRIVER), /* GPP_B11 - GPIO */ - _PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPP_B12 - GLB_RST_WARN_N# */ - _PAD_CFG_STRUCT(GPP_B12, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B13 - PLTRST# */ - _PAD_CFG_STRUCT(GPP_B13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B14 - SPKR */ - _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B15 - GPIO */ - _PAD_CFG_STRUCT(GPP_B15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, DEEP, OFF, DRIVER), /* GPP_B17 - GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, DEEP, OFF, DRIVER), /* GPP_B18 - GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, DRIVER), /* GPP_B19 - GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPP_B20 - GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_B20, 0, DEEP), /* GPP_B21 - GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), /* GPP_B22 - GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, 0x00000a00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ - _PAD_CFG_STRUCT(GPP_F0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, DRIVER), /* GPP_F1 - GPIO */ - _PAD_CFG_STRUCT(GPP_F1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, DRIVER), /* GPP_F2 - GPIO */ - _PAD_CFG_STRUCT(GPP_F2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, DRIVER), /* GPP_F3 - GPIO */ - _PAD_CFG_STRUCT(GPP_F3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, DRIVER), /* GPP_F4 - GPIO */ - _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_F6 - GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x84000200, 0x00000010), + PAD_CFG_GPO(GPP_F6, 0, PLTRST), /* GPP_F7 - GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x84000200, 0x00000010), + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* GPP_F8 - GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x84000200, 0x00000010), + PAD_CFG_GPO(GPP_F8, 0, PLTRST), /* GPP_F9 - GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F10, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F11 - SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F11, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F12 - GPIO */ - _PAD_CFG_STRUCT(GPP_F12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F14 - SSATA_LED# */ - _PAD_CFG_STRUCT(GPP_F14, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F15 - GPIO */ - _PAD_CFG_STRUCT(GPP_F15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ - _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, DRIVER), /* GPP_F17 - GPIO */ - _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, DEEP, OFF, DRIVER), /* GPP_F18 - GPIO */ - _PAD_CFG_STRUCT(GPP_F18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - _PAD_CFG_STRUCT(GPP_F19, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F20 - LAN_SMBDATA */ - _PAD_CFG_STRUCT(GPP_F20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F21 - LAN_SMBALRT# */ - _PAD_CFG_STRUCT(GPP_F21, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F22 - SSATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F22, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F23 - SSATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F23, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF), /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - _PAD_CFG_STRUCT(GPP_C2, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ - _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x00000000), + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, DEEP, OFF, DRIVER), /* GPP_C9 - GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_C9, 1, DEEP), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x86000103, 0x00000000), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_C11 - GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C14 - GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x80080102, 0x00000000), + PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), /* GPP_C15 - GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, DRIVER), /* GPP_C16 - GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, DEEP, OFF, DRIVER), /* GPP_C17 - GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, DEEP, OFF, DRIVER), /* GPP_C18 - GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, DEEP, OFF, DRIVER), /* GPP_C19 - GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, DEEP, OFF, DRIVER), /* GPP_C20 - RESERVED */ /* GPP_C21 - GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, DEEP, OFF, DRIVER), /* GPP_C22 - GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x80040102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), /* GPP_C23 - GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x40840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - _PAD_CFG_STRUCT(GPP_D0, 0x80840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), /* GPP_D1 - GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_D1, 0, DEEP), /* GPP_D2 - GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, DRIVER), /* GPP_D3 - GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, DRIVER), /* GPP_D4 - GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_D4, 1, DEEP), /* GPP_D5 - GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, DRIVER), /* GPP_D6 - GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, DRIVER), /* GPP_D7 - GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, DRIVER), /* GPP_D8 - GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, DRIVER), /* GPP_D9 - GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, DRIVER), /* GPP_D10 - GPIO */ - _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, DRIVER), /* GPP_D11 - GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, OFF, DRIVER), /* GPP_D12 - GPIO */ - _PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, OFF, DRIVER), /* GPP_D13 - GPIO */ - _PAD_CFG_STRUCT(GPP_D13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, DRIVER), /* GPP_D14 - GPIO */ - _PAD_CFG_STRUCT(GPP_D14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - _PAD_CFG_STRUCT(GPP_D15, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_D16 - GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, DRIVER), /* GPP_D18 - GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, DRIVER), /* GPP_D19 - GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_D19, 1, DEEP), /* GPP_D20 - GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, DRIVER), /* GPP_D21 - GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, DEEP, OFF, DRIVER), /* GPP_D22 - GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, DRIVER), /* GPP_D23 - GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - GPIO */ - _PAD_CFG_STRUCT(GPP_E0, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E0, NONE, DEEP, LEVEL, NONE), /* GPP_E1 - GPIO */ - _PAD_CFG_STRUCT(GPP_E1, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E1, NONE, DEEP, LEVEL, NONE), /* GPP_E2 - GPIO */ - _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - _PAD_CFG_STRUCT(GPP_E3, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E4 - GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, DRIVER), /* GPP_E6 - GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, DRIVER), /* GPP_E7 - GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E8, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_E9 - USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E9, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E10 - GPIO */ - _PAD_CFG_STRUCT(GPP_E10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ - _PAD_CFG_STRUCT(GPP_E11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, DRIVER), /* GPP_E12 - GPIO */ - _PAD_CFG_STRUCT(GPP_E12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - GPIO */ - _PAD_CFG_STRUCT(GPD1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, RSMRST, OFF, ACPI), /* GPD2 - GPIO */ - _PAD_CFG_STRUCT(GPD2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD4 - SLP_S3# */ - _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD5 - SLP_S4# */ - _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD6 - GPIO */ - _PAD_CFG_STRUCT(GPD6, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, 0x04000103, 0x00000000), + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPD8 - GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ - _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - GPIO */ - _PAD_CFG_STRUCT(GPD10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - _PAD_CFG_STRUCT(GPD11, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - _PAD_CFG_STRUCT(GPP_I0, 0x44000900, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I1 - LAN_TCK */ - _PAD_CFG_STRUCT(GPP_I1, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I2 - LAN_TMS */ - _PAD_CFG_STRUCT(GPP_I2, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I3 - LAN_TDI */ - _PAD_CFG_STRUCT(GPP_I3, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, DEEP, OFF, DRIVER), /* GPP_I6 - GPIO */ - _PAD_CFG_STRUCT(GPP_I6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - _PAD_CFG_STRUCT(GPP_I7, 0x44000902, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I8 - GPIO */ - _PAD_CFG_STRUCT(GPP_I8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ - _PAD_CFG_STRUCT(GPP_I9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, DEEP, OFF, DRIVER), /* GPP_I10 - GPIO */ - _PAD_CFG_STRUCT(GPP_I10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - _PAD_CFG_STRUCT(GPP_J0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J1 - LAN_LED_P0_1 */ - _PAD_CFG_STRUCT(GPP_J1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J2 - LAN_LED_P1_0 */ - _PAD_CFG_STRUCT(GPP_J2, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J3 - LAN_LED_P1_1 */ - _PAD_CFG_STRUCT(GPP_J3, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J4 - LAN_LED_P2_0 */ - _PAD_CFG_STRUCT(GPP_J4, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J5 - LAN_LED_P2_1 */ - _PAD_CFG_STRUCT(GPP_J5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J6 - LAN_LED_P3_0 */ - _PAD_CFG_STRUCT(GPP_J6, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J7 - LAN_LED_P3_1 */ - _PAD_CFG_STRUCT(GPP_J7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - _PAD_CFG_STRUCT(GPP_J8, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - _PAD_CFG_STRUCT(GPP_J9, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - _PAD_CFG_STRUCT(GPP_J10, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - _PAD_CFG_STRUCT(GPP_J11, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - _PAD_CFG_STRUCT(GPP_J12, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - _PAD_CFG_STRUCT(GPP_J13, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - _PAD_CFG_STRUCT(GPP_J14, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - _PAD_CFG_STRUCT(GPP_J15, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J16 - LAN_SDP_P0_0 */ - _PAD_CFG_STRUCT(GPP_J16, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J17 - GPIO */ - _PAD_CFG_STRUCT(GPP_J17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - _PAD_CFG_STRUCT(GPP_J18, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J19 - GPIO */ - _PAD_CFG_STRUCT(GPP_J19, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - _PAD_CFG_STRUCT(GPP_J20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J21 - GPIO */ - _PAD_CFG_STRUCT(GPP_J21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - _PAD_CFG_STRUCT(GPP_J22, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J23 - GPIO */ - _PAD_CFG_STRUCT(GPP_J23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - GPIO */ - _PAD_CFG_STRUCT(GPP_K0, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, DEEP, OFF, DRIVER), /* GPP_K1 - GPIO */ - _PAD_CFG_STRUCT(GPP_K1, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, DEEP, OFF, DRIVER), /* GPP_K2 - GPIO */ - _PAD_CFG_STRUCT(GPP_K2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, DEEP, OFF, DRIVER), /* GPP_K3 - GPIO */ - _PAD_CFG_STRUCT(GPP_K3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, DEEP, OFF, DRIVER), /* GPP_K4 - GPIO */ - _PAD_CFG_STRUCT(GPP_K4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, DRIVER), /* GPP_K5 - GPIO */ - _PAD_CFG_STRUCT(GPP_K5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, DRIVER), /* GPP_K6 - GPIO */ - _PAD_CFG_STRUCT(GPP_K6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - _PAD_CFG_STRUCT(GPP_K7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K8 - LAN_NCSI_ARB_IN */ - _PAD_CFG_STRUCT(GPP_K8, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - _PAD_CFG_STRUCT(GPP_K9, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K10 - PE_RST# */ - _PAD_CFG_STRUCT(GPP_K10, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF), /* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - _PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), /* GPP_G1 - GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), /* GPP_G2 - GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), /* GPP_G3 - GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), /* GPP_G4 - GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, DEEP, OFF, DRIVER), /* GPP_G5 - GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, DEEP, OFF, DRIVER), /* GPP_G6 - GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, DEEP, OFF, DRIVER), /* GPP_G7 - GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, DRIVER), /* GPP_G8 - GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, DEEP, OFF, DRIVER), /* GPP_G9 - GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, DEEP, OFF, DRIVER), /* GPP_G10 - GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, DRIVER), /* GPP_G11 - GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G17 - ADR_COMPLETE */ - _PAD_CFG_STRUCT(GPP_G17, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ - _PAD_CFG_STRUCT(GPP_G18, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G19 - SMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), /* GPP_G22 - GPIO */ - _PAD_CFG_STRUCT(GPP_G22, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_G22, 1, DEEP), /* GPP_G23 - GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, DEEP, OFF, DRIVER), /* GPP_H1 - GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, DRIVER), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, DRIVER), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, DRIVER), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, DEEP, OFF, DRIVER), /* GPP_H5 - RESERVED */ /* GPP_H6 - GPIO */ - _PAD_CFG_STRUCT(GPP_H6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, DEEP, OFF, DRIVER), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, DEEP, OFF, DRIVER), /* GPP_H8 - GPIO */ - _PAD_CFG_STRUCT(GPP_H8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, DEEP, OFF, DRIVER), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, DEEP, OFF, DRIVER), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ - _PAD_CFG_STRUCT(GPP_H12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, DEEP, OFF, DRIVER), /* GPP_H13 - RESERVED */ /* GPP_H14 - RESERVED */ /* GPP_H15 - GPIO */ - _PAD_CFG_STRUCT(GPP_H15, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, DRIVER), /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ /* GPP_H18 - GPIO */ - _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, DEEP, OFF, DRIVER), /* GPP_H19 - GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, DRIVER), /* GPP_H20 - GPIO */ - _PAD_CFG_STRUCT(GPP_H20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, DRIVER), /* GPP_H21 - GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, DRIVER), /* GPP_H22 - GPIO */ - _PAD_CFG_STRUCT(GPP_H22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, DRIVER), /* GPP_H23 - GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* GPP_L2 - GPIO */ - _PAD_CFG_STRUCT(GPP_L2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */ - _PAD_CFG_STRUCT(GPP_L3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, DRIVER), /* GPP_L4 - GPIO */ - _PAD_CFG_STRUCT(GPP_L4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, DRIVER), /* GPP_L5 - GPIO */ - _PAD_CFG_STRUCT(GPP_L5, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, DRIVER), /* GPP_L6 - GPIO */ - _PAD_CFG_STRUCT(GPP_L6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER), /* GPP_L7 - GPIO */ - _PAD_CFG_STRUCT(GPP_L7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, DRIVER), /* GPP_L8 - GPIO */ - _PAD_CFG_STRUCT(GPP_L8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, DEEP, OFF, DRIVER), /* GPP_L9 - GPIO */ - _PAD_CFG_STRUCT(GPP_L9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L9, NONE, DEEP, OFF, DRIVER), /* GPP_L10 - GPIO */ - _PAD_CFG_STRUCT(GPP_L10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L10, NONE, DEEP, OFF, DRIVER), /* GPP_L11 - GPIO */ - _PAD_CFG_STRUCT(GPP_L11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L11, NONE, DEEP, OFF, DRIVER), /* GPP_L12 - GPIO */ - _PAD_CFG_STRUCT(GPP_L12, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L12, NONE, DEEP, OFF, DRIVER), /* GPP_L13 - GPIO */ - _PAD_CFG_STRUCT(GPP_L13, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L13, NONE, DEEP, OFF, DRIVER), /* GPP_L14 - GPIO */ - _PAD_CFG_STRUCT(GPP_L14, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L14, NONE, DEEP, OFF, DRIVER), /* GPP_L15 - GPIO */ - _PAD_CFG_STRUCT(GPP_L15, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L15, NONE, DEEP, OFF, DRIVER), /* GPP_L16 - GPIO */ - _PAD_CFG_STRUCT(GPP_L16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L16, NONE, DEEP, OFF, DRIVER), /* GPP_L17 - GPIO */ - _PAD_CFG_STRUCT(GPP_L17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L17, NONE, DEEP, OFF, DRIVER), /* GPP_L18 - GPIO */ - _PAD_CFG_STRUCT(GPP_L18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L18, NONE, DEEP, OFF, DRIVER), /* GPP_L19 - GPIO */ - _PAD_CFG_STRUCT(GPP_L19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L19, NONE, DEEP, OFF, DRIVER), }; #endif /* CFG_PCH_GPIO_H */ From d2b418bd337ec9904fc7e85c2a2e46a7f9508b36 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 20:56:50 +0300 Subject: [PATCH 1343/1463] mb/ocp/tiogapass: fix advanced _PAD_CFG_STRUCT macros in config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the current pad configuration can not be defined using standard macros from the gpio_defs.h [1], then the intelp2m utility generates "advanced" _PAD_CFG_STRUCT() macros. However, often this configuration in the vendor’s firmware is erroneous. Change the extended macros to standard ones taking into account the information based on the schematic diagram and the previous GPIO configuration for FSP-M [2]. [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40732 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- src/mainboard/ocp/tiogapass/gpio.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h index b05f53692b..f37ffd5eb5 100644 --- a/src/mainboard/ocp/tiogapass/gpio.h +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = { /* GPP_F4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, DEEP, OFF, DRIVER), /* GPP_F6 - GPIO */ PAD_CFG_GPO(GPP_F6, 0, PLTRST), /* GPP_F7 - GPIO */ @@ -175,13 +175,13 @@ static const struct pad_config gpio_table[] = { /* GPP_C9 - GPIO */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, EDGE_BOTH, ACPI), /* GPP_C11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, DEEP, OFF, DRIVER), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, DEEP, OFF, DRIVER), /* GPP_C14 - GPIO */ PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), /* GPP_C15 - GPIO */ @@ -296,7 +296,7 @@ static const struct pad_config gpio_table[] = { /* GPD6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ @@ -433,15 +433,15 @@ static const struct pad_config gpio_table[] = { /* GPP_G11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, DEEP, OFF, DRIVER), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, DRIVER), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, DEEP, OFF, DRIVER), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, DEEP, OFF, DRIVER), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), /* GPP_G17 - ADR_COMPLETE */ PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ From d2b3e81095bccee157c8daa0db2d045fe33ea9cd Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 20:56:50 +0300 Subject: [PATCH 1344/1463] xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h | 1017 ----------------- .../xeon_sp/skx/include/soc/gpio_soc_defs.h | 298 ----- 2 files changed, 1315 deletions(-) delete mode 100644 src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h delete mode 100644 src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h deleted file mode 100644 index 44098b1290..0000000000 --- a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h +++ /dev/null @@ -1,1017 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SKXSP_TP_GPIO_H_ -#define _SKXSP_TP_GPIO_H_ - -#include -#include - -/* - * OCP TiogaPass Gpio Pad Configuration - */ -static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = { - {GPIO_SKL_H_GPP_A0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N - {GPIO_SKL_H_GPP_A1, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_1_LAD_0_ESPI_IO_0 - {GPIO_SKL_H_GPP_A2, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_2_LAD_1_ESPI_IO_1 - {GPIO_SKL_H_GPP_A3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_3_LAD_2_ESPI_IO_2 - {GPIO_SKL_H_GPP_A4, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_4_LAD_3_ESPI_IO_3 - {GPIO_SKL_H_GPP_A5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N - {GPIO_SKL_H_GPP_A6, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N - {GPIO_SKL_H_GPP_A7, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N - {GPIO_SKL_H_GPP_A8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_8_FM_LPC_CLKRUN_N - {GPIO_SKL_H_GPP_A9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK - {GPIO_SKL_H_GPP_A10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_10_CLKOUT_LPC1 - {GPIO_SKL_H_GPP_A11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_11_FM_LPC_PME_N - {GPIO_SKL_H_GPP_A12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N - {GPIO_SKL_H_GPP_A13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK - {GPIO_SKL_H_GPP_A14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_14_ESPI_RESET_N - {GPIO_SKL_H_GPP_A15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_15_SUSACK_N - {GPIO_SKL_H_GPP_A16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_16_CLKOUT_LPC2 - {GPIO_SKL_H_GPP_A17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_17 - {GPIO_SKL_H_GPP_A18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_18 - // {GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME - {GPIO_SKL_H_GPP_A20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } },//GPP_A_20 - {GPIO_SKL_H_GPP_A21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_21 - {GPIO_SKL_H_GPP_A22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_22 - {GPIO_SKL_H_GPP_A23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_23 - - {GPIO_SKL_H_GPP_B0, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_0_CORE_VID_0 - {GPIO_SKL_H_GPP_B1, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_1_CORE_VID_1 - {GPIO_SKL_H_GPP_B2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_2_VRALERT_N - {GPIO_SKL_H_GPP_B3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_3_CPU_GP2 - {GPIO_SKL_H_GPP_B4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_4_CPU_GP3 - {GPIO_SKL_H_GPP_B5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_5_SRCCLKREQ0_N - {GPIO_SKL_H_GPP_B6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_6_SRCCLKREQ1_N - {GPIO_SKL_H_GPP_B7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_7_SRCCLKREQ2_N - {GPIO_SKL_H_GPP_B8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_8_SRCCLKREQ3_N - {GPIO_SKL_H_GPP_B9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_9_SRCCLKREQ4_N - {GPIO_SKL_H_GPP_B10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_10_SRCCLKREQ5_N - {GPIO_SKL_H_GPP_B11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_11 - {GPIO_SKL_H_GPP_B12, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_12_GLB_RST_WARN_N - {GPIO_SKL_H_GPP_B13, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_13_RST_PLTRST_N - {GPIO_SKL_H_GPP_B14, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR - {GPIO_SKL_H_GPP_B15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_15 - {GPIO_SKL_H_GPP_B16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_16 - {GPIO_SKL_H_GPP_B17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_17 - {GPIO_SKL_H_GPP_B18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_18 - {GPIO_SKL_H_GPP_B19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_19 - {GPIO_SKL_H_GPP_B20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_20 - {GPIO_SKL_H_GPP_B21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_21 - {GPIO_SKL_H_GPP_B22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_22 - {GPIO_SKL_H_GPP_B23, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N - -// {GPIO_SKL_H_GPP_C0, {} }, //GPP_C_0_SMBCLK, controlled by ME -// {GPIO_SKL_H_GPP_C1, {} }, //GPP_C_1_SMBDATA, controlled by ME - {GPIO_SKL_H_GPP_C2, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_2_SMBALERT_N -// {GPIO_SKL_H_GPP_C3, {} }, //GPP_C_3_SML0CLK_IE, controlled by ME -// {GPIO_SKL_H_GPP_C4, {} }, //GPP_C_4_SML0DATA_IE, controlled by ME - {GPIO_SKL_H_GPP_C5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_5_SML0ALERT_IE_N -// {GPIO_SKL_H_GPP_C6, {} }, //GPP_C_6_SML1CLK_IE, controlled by ME -// {GPIO_SKL_H_GPP_C7, {} }, //GPP_C_7_SML1DATA_IE, controlled by ME - {GPIO_SKL_H_GPP_C8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_8 - {GPIO_SKL_H_GPP_C9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_9 - {GPIO_SKL_H_GPP_C10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_10 - {GPIO_SKL_H_GPP_C11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_11 - {GPIO_SKL_H_GPP_C12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_12 - {GPIO_SKL_H_GPP_C13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_13 - {GPIO_SKL_H_GPP_C14, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_14 - {GPIO_SKL_H_GPP_C15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_15 - {GPIO_SKL_H_GPP_C16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_16 - {GPIO_SKL_H_GPP_C17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_17 - {GPIO_SKL_H_GPP_C18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_18 - {GPIO_SKL_H_GPP_C19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_19 -// {GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME - {GPIO_SKL_H_GPP_C21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_21 - {GPIO_SKL_H_GPP_C22, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_22 - {GPIO_SKL_H_GPP_C23, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_23 - - {GPIO_SKL_H_GPP_D0, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_0 - {GPIO_SKL_H_GPP_D1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_1 - {GPIO_SKL_H_GPP_D2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_2 - {GPIO_SKL_H_GPP_D3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_3 - {GPIO_SKL_H_GPP_D4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_4 - {GPIO_SKL_H_GPP_D5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_5 - {GPIO_SKL_H_GPP_D6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_6 - {GPIO_SKL_H_GPP_D7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_7 - {GPIO_SKL_H_GPP_D8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_8 - {GPIO_SKL_H_GPP_D9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_9_SSATA_DEVSLP3 - {GPIO_SKL_H_GPP_D10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_10_SSATA_DEVSLP4 - {GPIO_SKL_H_GPP_D11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_11_SSATA_DEVSLP5 - {GPIO_SKL_H_GPP_D12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_12_SSATA_SDATAOUT1 - {GPIO_SKL_H_GPP_D13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_13_SML0BLCK_IE - {GPIO_SKL_H_GPP_D14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_14_SML0BDATA_IE - {GPIO_SKL_H_GPP_D15, { - GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_15_SSATA_SDATAOUT0 - {GPIO_SKL_H_GPP_D16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_16_SML0BALERT_IE_N - {GPIO_SKL_H_GPP_D17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_17 - {GPIO_SKL_H_GPP_D18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_18 - {GPIO_SKL_H_GPP_D19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock - } }, //GPP_D_19 - {GPIO_SKL_H_GPP_D20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_20_TP_PCH_GPP_D_20 - {GPIO_SKL_H_GPP_D21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_21_IE_URAT_RX - {GPIO_SKL_H_GPP_D22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_22_IE_URAT_TX - {GPIO_SKL_H_GPP_D23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_23 - - {GPIO_SKL_H_GPP_E0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_0_SATAXPCIE0_SATAGP0 - {GPIO_SKL_H_GPP_E1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_1_SATAXPCIE1_SATAGP1 - {GPIO_SKL_H_GPP_E2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_2_SATAXPCIE2_SATAGP2 - {GPIO_SKL_H_GPP_E3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_3_CPU_GP0 - {GPIO_SKL_H_GPP_E4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_4_SATA_DEVSLP0 - {GPIO_SKL_H_GPP_E5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_5_SATA_DEVSLP1 - {GPIO_SKL_H_GPP_E6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_6_SATA_DEVSLP2 - {GPIO_SKL_H_GPP_E7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_7_CPU_GP1 - {GPIO_SKL_H_GPP_E8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_8_SATA_LED_N - {GPIO_SKL_H_GPP_E9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_9_USB2_OC0_N - {GPIO_SKL_H_GPP_E10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_10_USB2_OC1_N - {GPIO_SKL_H_GPP_E11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_11_USB2_OC2_N - {GPIO_SKL_H_GPP_E12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_12_USB2_OC3_N - - {GPIO_SKL_H_GPP_F0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_0_SATAXPCIE3_SATAGP3 - {GPIO_SKL_H_GPP_F1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_1_SATAXPCIE4_SATAGP4 - {GPIO_SKL_H_GPP_F2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_2_SATAXPCIE5_SATAGP5 - {GPIO_SKL_H_GPP_F3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_3_SATAXPCIE6_SATAGP6 - {GPIO_SKL_H_GPP_F4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_4_SATAXPCIE7_SATAGP7 - {GPIO_SKL_H_GPP_F5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_5_SATA_DEVSLP3 - {GPIO_SKL_H_GPP_F6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_6_SATA_DEVSLP4 - {GPIO_SKL_H_GPP_F7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_7_SATA_DEVSLP5 - {GPIO_SKL_H_GPP_F8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_8_SATA_DEVSLP6 - {GPIO_SKL_H_GPP_F9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_9_SATA_DEVSLP7 - {GPIO_SKL_H_GPP_F10, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_10_SATA_SCLOCK - {GPIO_SKL_H_GPP_F11, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_11_SATA_SLOAD - {GPIO_SKL_H_GPP_F12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_12_SATA_SDATAOUT1 - {GPIO_SKL_H_GPP_F13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_13_SATA_SDATAOUT0 - {GPIO_SKL_H_GPP_F14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_14_SSATA_LED_N - {GPIO_SKL_H_GPP_F15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_15_USB2_OC4_N - {GPIO_SKL_H_GPP_F16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_16_USB2_OC5_N - {GPIO_SKL_H_GPP_F17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_17_USB2_OC6_N - {GPIO_SKL_H_GPP_F18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_18_USB2_OC7_N - {GPIO_SKL_H_GPP_F19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_19_LAN_SMBCLK - {GPIO_SKL_H_GPP_F20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_20_LAN_SMBDATA - {GPIO_SKL_H_GPP_F21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_21_LAN_SMBALERT_N - {GPIO_SKL_H_GPP_F22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_22_SSATA_SCLOCK - {GPIO_SKL_H_GPP_F23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_23_SSATA_SLOAD - - {GPIO_SKL_H_GPP_G0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_0_FANTACH0_FANTACH0IE - {GPIO_SKL_H_GPP_G1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_1_FANTACH1_FANTACH1IE - {GPIO_SKL_H_GPP_G2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_2_FANTACH2_FANTACH2IE - {GPIO_SKL_H_GPP_G3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_3_FANTACH3_FANTACH3IE - {GPIO_SKL_H_GPP_G4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_4_FANTACH4_FANTACH4IE - {GPIO_SKL_H_GPP_G5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_5_FANTACH5_FANTACH5IE - {GPIO_SKL_H_GPP_G6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_6_FANTACH6_FANTACH6IE - {GPIO_SKL_H_GPP_G7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_7_FANTACH7_FANTACH7IE - {GPIO_SKL_H_GPP_G8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_8_FANPWM0_FANPWM0IE - {GPIO_SKL_H_GPP_G9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_9_FANPWM1_FANPWM1IE - {GPIO_SKL_H_GPP_G10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_10_FANPWM2_FANPWM2IE - {GPIO_SKL_H_GPP_G11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_11_FANPWM3_FANPWM3IE - {GPIO_SKL_H_GPP_G12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_12 - {GPIO_SKL_H_GPP_G13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_13 - {GPIO_SKL_H_GPP_G14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_14 - {GPIO_SKL_H_GPP_G15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_15 - {GPIO_SKL_H_GPP_G16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_16 - {GPIO_SKL_H_GPP_G17, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_17_ADR_COMPLETE - {GPIO_SKL_H_GPP_G18, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_18_FM_NMI_EVENT_N - {GPIO_SKL_H_GPP_G19, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_19_FM_SMI_ACTIVE_N -// {GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME - {GPIO_SKL_H_GPP_G21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_21_SSATA_DEVSLP1 - {GPIO_SKL_H_GPP_G22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_22_SSATA_DEVSLP2 - {GPIO_SKL_H_GPP_G23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_23_SSATAXPCIE0_SSATAGP0 - - {GPIO_SKL_H_GPP_H0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_0_SRCCLKREQ6_N - {GPIO_SKL_H_GPP_H1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_1_SRCCLKREQ7_N - {GPIO_SKL_H_GPP_H2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_2_SRCCLKREQ8_N - {GPIO_SKL_H_GPP_H3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_3_SRCCLKREQ9_N - {GPIO_SKL_H_GPP_H4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_4_SRCCLKREQ10_N -// {GPIO_SKL_H_GPP_H5, {} }, //GPP_H_5_SRCCLKREQ11_N - {GPIO_SKL_H_GPP_H6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_6_SRCCLKREQ12_N - {GPIO_SKL_H_GPP_H7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_7_SRCCLKREQ13_N - {GPIO_SKL_H_GPP_H8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_8_SRCCLKREQ14_N - {GPIO_SKL_H_GPP_H9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_9_SRCCLKREQ15_N -// {GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE -// {GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE - {GPIO_SKL_H_GPP_H12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_12_SML2ALERT_N_IE -// {GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE -// {GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE - {GPIO_SKL_H_GPP_H15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_15_SML3ALERT_N_IE -// {GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE -// {GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE - {GPIO_SKL_H_GPP_H18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_18_SML4ALERT_N_IE - {GPIO_SKL_H_GPP_H19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_19_SSATAXPCIE1_SSATAGP1 - {GPIO_SKL_H_GPP_H20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_20_SSATAXPCIE2_SSATAGP2 - {GPIO_SKL_H_GPP_H21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_21_SSATAXPCIE3_SSATAGP3 - {GPIO_SKL_H_GPP_H22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_22_SSATAXPCIE4_SSATAGP4 - {GPIO_SKL_H_GPP_H23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_23_SSATAXPCIE5_SSATAGP5 - - {GPIO_SKL_H_GPP_I0, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_0_GBE_TDO - {GPIO_SKL_H_GPP_I1, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_1_GBE_TCK - {GPIO_SKL_H_GPP_I2, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_2_GBE_TMS - {GPIO_SKL_H_GPP_I3, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_3_GBE_TDI - {GPIO_SKL_H_GPP_I4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_4_DO_RESET_IN_N - {GPIO_SKL_H_GPP_I5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_5_DO_RESET_OUT_N - {GPIO_SKL_H_GPP_I6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_6_RESET_DONE - {GPIO_SKL_H_GPP_I7, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_7_JTAG_GBE_TRST_N - {GPIO_SKL_H_GPP_I8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_8_GBE_PCI_DIS - {GPIO_SKL_H_GPP_I9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_9_GBE_LAN_DIS - {GPIO_SKL_H_GPP_I10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_10 - - {GPIO_SKL_H_GPP_J0, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_0_LAN_LED_P0_0 - {GPIO_SKL_H_GPP_J1, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_1_LAN_LED_P0_1 - {GPIO_SKL_H_GPP_J2, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_2_LAN_LED_P1_0 - {GPIO_SKL_H_GPP_J3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_3_LAN_LED_P1_1 - {GPIO_SKL_H_GPP_J4, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_4_LAN_LED_P2_0 - {GPIO_SKL_H_GPP_J5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_5_LAN_LED_P2_1 - {GPIO_SKL_H_GPP_J6, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_6_LAN_LED_P3_0 - {GPIO_SKL_H_GPP_J7, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_7_LAN_LED_P3_1 - {GPIO_SKL_H_GPP_J8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_8_LAN_I2C_SCL_MDC_P0 - {GPIO_SKL_H_GPP_J9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0 - {GPIO_SKL_H_GPP_J10, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_10_LAN_I2C_SCL_MDC_P1 - {GPIO_SKL_H_GPP_J11, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1 - {GPIO_SKL_H_GPP_J12, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_12_LAN_I2C_SCL_MDC_P2 - {GPIO_SKL_H_GPP_J13, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2 - {GPIO_SKL_H_GPP_J14, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_14_LAN_I2C_SCL_MDC_P3 - {GPIO_SKL_H_GPP_J15, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3 - {GPIO_SKL_H_GPP_J16, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_16_LAN_SDP_P0_0 - {GPIO_SKL_H_GPP_J17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_17_LAN_SDP_P0_1 - {GPIO_SKL_H_GPP_J18, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_18_LAN_SDP_P1_0 - {GPIO_SKL_H_GPP_J19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_19_LAN_SDP_P1_1 - {GPIO_SKL_H_GPP_J20, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_20_LAN_SDP_P2_0 - {GPIO_SKL_H_GPP_J21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_21_LAN_SDP_P2_1 - {GPIO_SKL_H_GPP_J22, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_22_LAN_SDP_P3_0 - {GPIO_SKL_H_GPP_J23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_23_LAN_SDP_P3_1 - - {GPIO_SKL_H_GPP_K0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_0_LAN_NCSI_CLK_IN - {GPIO_SKL_H_GPP_K1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_1_LAN_NCSI_TXD0 - {GPIO_SKL_H_GPP_K2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_2_LAN_NCSI_TXD1 - {GPIO_SKL_H_GPP_K3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_3_LAN_NCSI_TX_EN - {GPIO_SKL_H_GPP_K4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_4_LAN_NCSI_CRS_DV - {GPIO_SKL_H_GPP_K5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_5_LAN_NCSI_RXD0 - {GPIO_SKL_H_GPP_K6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_6_LAN_NCSI_RXD1 - {GPIO_SKL_H_GPP_K7, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_7 - {GPIO_SKL_H_GPP_K8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_8_LAN_NCSI_ARB_IN - {GPIO_SKL_H_GPP_K9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_9_LAN_NCSI_ARB_OUT - {GPIO_SKL_H_GPP_K10, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_10_PE_RST_N - - {GPIO_SKL_H_GPP_L2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_2_TESTCH0_D0 - {GPIO_SKL_H_GPP_L3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_3_TESTCH0_D1 - {GPIO_SKL_H_GPP_L4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_4_TESTCH0_D2 - {GPIO_SKL_H_GPP_L5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_5_TESTCH0_D3 - {GPIO_SKL_H_GPP_L6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_6_TESTCH0_D4 - {GPIO_SKL_H_GPP_L7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_7_TESTCH0_D5 - {GPIO_SKL_H_GPP_L8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_8_TESTCH0_D6 - {GPIO_SKL_H_GPP_L9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_9_TESTCH0_D7 - {GPIO_SKL_H_GPP_L10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_10_TESTCH0_CLK - {GPIO_SKL_H_GPP_L11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_11_TESTCH1_D0 - {GPIO_SKL_H_GPP_L12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_12_TESTCH1_D1 - {GPIO_SKL_H_GPP_L13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_13_TESTCH1_D2 - {GPIO_SKL_H_GPP_L14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_14_TESTCH1_D3 - {GPIO_SKL_H_GPP_L15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_15_TESTCH1_D4 - {GPIO_SKL_H_GPP_L16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_16_TESTCH1_D5 - {GPIO_SKL_H_GPP_L17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_17_TESTCH1_D6 - {GPIO_SKL_H_GPP_L18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_18_TESTCH1_D7 - {GPIO_SKL_H_GPP_L19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_19_TESTCH1_CLK - - {GPIO_SKL_H_GPD0, {} }, //GPD_0, controlled by ME - {GPIO_SKL_H_GPD1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_1_ACPRESENT - {GPIO_SKL_H_GPD2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_2_GBE_WAKE_N - {GPIO_SKL_H_GPD3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_3_PWRBTNB_N - {GPIO_SKL_H_GPD4, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_4_SLP_S3B - {GPIO_SKL_H_GPD5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_5_SLP_S4B - {GPIO_SKL_H_GPD6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_6_SLPA_N - {GPIO_SKL_H_GPD7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_7 - {GPIO_SKL_H_GPD8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD - {GPIO_SKL_H_GPD9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_9 - {GPIO_SKL_H_GPD10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_10_FM_SLPS5_N - {GPIO_SKL_H_GPD11, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_11_GBEPHY -}; - -#endif /* _SKXSP_TP_GPIO_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h deleted file mode 100644 index ac230ef78b..0000000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _GPIO_SOC_DEFS_H_ -#define _GPIO_SOC_DEFS_H_ - -/// -/// Skylake-SP chipset GPIO Groups -/// -#define GPIO_SKL_H_GROUP_GPP_A 0x0100 -#define GPIO_SKL_H_GROUP_GPP_B 0x0101 -#define GPIO_SKL_H_GROUP_GPP_C 0x0102 -#define GPIO_SKL_H_GROUP_GPP_D 0x0103 -#define GPIO_SKL_H_GROUP_GPP_E 0x0104 -#define GPIO_SKL_H_GROUP_GPP_F 0x0105 -#define GPIO_SKL_H_GROUP_GPP_G 0x0106 -#define GPIO_SKL_H_GROUP_GPP_H 0x0107 -#define GPIO_SKL_H_GROUP_GPP_I 0x0108 -#define GPIO_SKL_H_GROUP_GPP_J 0x0109 -#define GPIO_SKL_H_GROUP_GPP_K 0x010A -#define GPIO_SKL_H_GROUP_GPP_L 0x010B -#define GPIO_SKL_H_GROUP_GPD 0x010C - -/// -/// SKL H GPIO pins -/// -#define GPIO_SKL_H_GPP_A0 0x01000000 -#define GPIO_SKL_H_GPP_A1 0x01000001 -#define GPIO_SKL_H_GPP_A2 0x01000002 -#define GPIO_SKL_H_GPP_A3 0x01000003 -#define GPIO_SKL_H_GPP_A4 0x01000004 -#define GPIO_SKL_H_GPP_A5 0x01000005 -#define GPIO_SKL_H_GPP_A6 0x01000006 -#define GPIO_SKL_H_GPP_A7 0x01000007 -#define GPIO_SKL_H_GPP_A8 0x01000008 -#define GPIO_SKL_H_GPP_A9 0x01000009 -#define GPIO_SKL_H_GPP_A10 0x0100000A -#define GPIO_SKL_H_GPP_A11 0x0100000B -#define GPIO_SKL_H_GPP_A12 0x0100000C -#define GPIO_SKL_H_GPP_A13 0x0100000D -#define GPIO_SKL_H_GPP_A14 0x0100000E -#define GPIO_SKL_H_GPP_A15 0x0100000F -#define GPIO_SKL_H_GPP_A16 0x01000010 -#define GPIO_SKL_H_GPP_A17 0x01000011 -#define GPIO_SKL_H_GPP_A18 0x01000012 -#define GPIO_SKL_H_GPP_A19 0x01000013 -#define GPIO_SKL_H_GPP_A20 0x01000014 -#define GPIO_SKL_H_GPP_A21 0x01000015 -#define GPIO_SKL_H_GPP_A22 0x01000016 -#define GPIO_SKL_H_GPP_A23 0x01000017 -#define GPIO_SKL_H_GPP_B0 0x01010000 -#define GPIO_SKL_H_GPP_B1 0x01010001 -#define GPIO_SKL_H_GPP_B2 0x01010002 -#define GPIO_SKL_H_GPP_B3 0x01010003 -#define GPIO_SKL_H_GPP_B4 0x01010004 -#define GPIO_SKL_H_GPP_B5 0x01010005 -#define GPIO_SKL_H_GPP_B6 0x01010006 -#define GPIO_SKL_H_GPP_B7 0x01010007 -#define GPIO_SKL_H_GPP_B8 0x01010008 -#define GPIO_SKL_H_GPP_B9 0x01010009 -#define GPIO_SKL_H_GPP_B10 0x0101000A -#define GPIO_SKL_H_GPP_B11 0x0101000B -#define GPIO_SKL_H_GPP_B12 0x0101000C -#define GPIO_SKL_H_GPP_B13 0x0101000D -#define GPIO_SKL_H_GPP_B14 0x0101000E -#define GPIO_SKL_H_GPP_B15 0x0101000F -#define GPIO_SKL_H_GPP_B16 0x01010010 -#define GPIO_SKL_H_GPP_B17 0x01010011 -#define GPIO_SKL_H_GPP_B18 0x01010012 -#define GPIO_SKL_H_GPP_B19 0x01010013 -#define GPIO_SKL_H_GPP_B20 0x01010014 -#define GPIO_SKL_H_GPP_B21 0x01010015 -#define GPIO_SKL_H_GPP_B22 0x01010016 -#define GPIO_SKL_H_GPP_B23 0x01010017 -#define GPIO_SKL_H_GPP_C0 0x01020000 -#define GPIO_SKL_H_GPP_C1 0x01020001 -#define GPIO_SKL_H_GPP_C2 0x01020002 -#define GPIO_SKL_H_GPP_C3 0x01020003 -#define GPIO_SKL_H_GPP_C4 0x01020004 -#define GPIO_SKL_H_GPP_C5 0x01020005 -#define GPIO_SKL_H_GPP_C6 0x01020006 -#define GPIO_SKL_H_GPP_C7 0x01020007 -#define GPIO_SKL_H_GPP_C8 0x01020008 -#define GPIO_SKL_H_GPP_C9 0x01020009 -#define GPIO_SKL_H_GPP_C10 0x0102000A -#define GPIO_SKL_H_GPP_C11 0x0102000B -#define GPIO_SKL_H_GPP_C12 0x0102000C -#define GPIO_SKL_H_GPP_C13 0x0102000D -#define GPIO_SKL_H_GPP_C14 0x0102000E -#define GPIO_SKL_H_GPP_C15 0x0102000F -#define GPIO_SKL_H_GPP_C16 0x01020010 -#define GPIO_SKL_H_GPP_C17 0x01020011 -#define GPIO_SKL_H_GPP_C18 0x01020012 -#define GPIO_SKL_H_GPP_C19 0x01020013 -#define GPIO_SKL_H_GPP_C20 0x01020014 -#define GPIO_SKL_H_GPP_C21 0x01020015 -#define GPIO_SKL_H_GPP_C22 0x01020016 -#define GPIO_SKL_H_GPP_C23 0x01020017 -#define GPIO_SKL_H_GPP_D0 0x01030000 -#define GPIO_SKL_H_GPP_D1 0x01030001 -#define GPIO_SKL_H_GPP_D2 0x01030002 -#define GPIO_SKL_H_GPP_D3 0x01030003 -#define GPIO_SKL_H_GPP_D4 0x01030004 -#define GPIO_SKL_H_GPP_D5 0x01030005 -#define GPIO_SKL_H_GPP_D6 0x01030006 -#define GPIO_SKL_H_GPP_D7 0x01030007 -#define GPIO_SKL_H_GPP_D8 0x01030008 -#define GPIO_SKL_H_GPP_D9 0x01030009 -#define GPIO_SKL_H_GPP_D10 0x0103000A -#define GPIO_SKL_H_GPP_D11 0x0103000B -#define GPIO_SKL_H_GPP_D12 0x0103000C -#define GPIO_SKL_H_GPP_D13 0x0103000D -#define GPIO_SKL_H_GPP_D14 0x0103000E -#define GPIO_SKL_H_GPP_D15 0x0103000F -#define GPIO_SKL_H_GPP_D16 0x01030010 -#define GPIO_SKL_H_GPP_D17 0x01030011 -#define GPIO_SKL_H_GPP_D18 0x01030012 -#define GPIO_SKL_H_GPP_D19 0x01030013 -#define GPIO_SKL_H_GPP_D20 0x01030014 -#define GPIO_SKL_H_GPP_D21 0x01030015 -#define GPIO_SKL_H_GPP_D22 0x01030016 -#define GPIO_SKL_H_GPP_D23 0x01030017 -#define GPIO_SKL_H_GPP_E0 0x01040000 -#define GPIO_SKL_H_GPP_E1 0x01040001 -#define GPIO_SKL_H_GPP_E2 0x01040002 -#define GPIO_SKL_H_GPP_E3 0x01040003 -#define GPIO_SKL_H_GPP_E4 0x01040004 -#define GPIO_SKL_H_GPP_E5 0x01040005 -#define GPIO_SKL_H_GPP_E6 0x01040006 -#define GPIO_SKL_H_GPP_E7 0x01040007 -#define GPIO_SKL_H_GPP_E8 0x01040008 -#define GPIO_SKL_H_GPP_E9 0x01040009 -#define GPIO_SKL_H_GPP_E10 0x0104000A -#define GPIO_SKL_H_GPP_E11 0x0104000B -#define GPIO_SKL_H_GPP_E12 0x0104000C -#define GPIO_SKL_H_GPP_F0 0x01050000 -#define GPIO_SKL_H_GPP_F1 0x01050001 -#define GPIO_SKL_H_GPP_F2 0x01050002 -#define GPIO_SKL_H_GPP_F3 0x01050003 -#define GPIO_SKL_H_GPP_F4 0x01050004 -#define GPIO_SKL_H_GPP_F5 0x01050005 -#define GPIO_SKL_H_GPP_F6 0x01050006 -#define GPIO_SKL_H_GPP_F7 0x01050007 -#define GPIO_SKL_H_GPP_F8 0x01050008 -#define GPIO_SKL_H_GPP_F9 0x01050009 -#define GPIO_SKL_H_GPP_F10 0x0105000A -#define GPIO_SKL_H_GPP_F11 0x0105000B -#define GPIO_SKL_H_GPP_F12 0x0105000C -#define GPIO_SKL_H_GPP_F13 0x0105000D -#define GPIO_SKL_H_GPP_F14 0x0105000E -#define GPIO_SKL_H_GPP_F15 0x0105000F -#define GPIO_SKL_H_GPP_F16 0x01050010 -#define GPIO_SKL_H_GPP_F17 0x01050011 -#define GPIO_SKL_H_GPP_F18 0x01050012 -#define GPIO_SKL_H_GPP_F19 0x01050013 -#define GPIO_SKL_H_GPP_F20 0x01050014 -#define GPIO_SKL_H_GPP_F21 0x01050015 -#define GPIO_SKL_H_GPP_F22 0x01050016 -#define GPIO_SKL_H_GPP_F23 0x01050017 -#define GPIO_SKL_H_GPP_G0 0x01060000 -#define GPIO_SKL_H_GPP_G1 0x01060001 -#define GPIO_SKL_H_GPP_G2 0x01060002 -#define GPIO_SKL_H_GPP_G3 0x01060003 -#define GPIO_SKL_H_GPP_G4 0x01060004 -#define GPIO_SKL_H_GPP_G5 0x01060005 -#define GPIO_SKL_H_GPP_G6 0x01060006 -#define GPIO_SKL_H_GPP_G7 0x01060007 -#define GPIO_SKL_H_GPP_G8 0x01060008 -#define GPIO_SKL_H_GPP_G9 0x01060009 -#define GPIO_SKL_H_GPP_G10 0x0106000A -#define GPIO_SKL_H_GPP_G11 0x0106000B -#define GPIO_SKL_H_GPP_G12 0x0106000C -#define GPIO_SKL_H_GPP_G13 0x0106000D -#define GPIO_SKL_H_GPP_G14 0x0106000E -#define GPIO_SKL_H_GPP_G15 0x0106000F -#define GPIO_SKL_H_GPP_G16 0x01060010 -#define GPIO_SKL_H_GPP_G17 0x01060011 -#define GPIO_SKL_H_GPP_G18 0x01060012 -#define GPIO_SKL_H_GPP_G19 0x01060013 -#define GPIO_SKL_H_GPP_G20 0x01060014 -#define GPIO_SKL_H_GPP_G21 0x01060015 -#define GPIO_SKL_H_GPP_G22 0x01060016 -#define GPIO_SKL_H_GPP_G23 0x01060017 -#define GPIO_SKL_H_GPP_H0 0x01070000 -#define GPIO_SKL_H_GPP_H1 0x01070001 -#define GPIO_SKL_H_GPP_H2 0x01070002 -#define GPIO_SKL_H_GPP_H3 0x01070003 -#define GPIO_SKL_H_GPP_H4 0x01070004 -#define GPIO_SKL_H_GPP_H5 0x01070005 -#define GPIO_SKL_H_GPP_H6 0x01070006 -#define GPIO_SKL_H_GPP_H7 0x01070007 -#define GPIO_SKL_H_GPP_H8 0x01070008 -#define GPIO_SKL_H_GPP_H9 0x01070009 -#define GPIO_SKL_H_GPP_H10 0x0107000A -#define GPIO_SKL_H_GPP_H11 0x0107000B -#define GPIO_SKL_H_GPP_H12 0x0107000C -#define GPIO_SKL_H_GPP_H13 0x0107000D -#define GPIO_SKL_H_GPP_H14 0x0107000E -#define GPIO_SKL_H_GPP_H15 0x0107000F -#define GPIO_SKL_H_GPP_H16 0x01070010 -#define GPIO_SKL_H_GPP_H17 0x01070011 -#define GPIO_SKL_H_GPP_H18 0x01070012 -#define GPIO_SKL_H_GPP_H19 0x01070013 -#define GPIO_SKL_H_GPP_H20 0x01070014 -#define GPIO_SKL_H_GPP_H21 0x01070015 -#define GPIO_SKL_H_GPP_H22 0x01070016 -#define GPIO_SKL_H_GPP_H23 0x01070017 -#define GPIO_SKL_H_GPP_I0 0x01080000 -#define GPIO_SKL_H_GPP_I1 0x01080001 -#define GPIO_SKL_H_GPP_I2 0x01080002 -#define GPIO_SKL_H_GPP_I3 0x01080003 -#define GPIO_SKL_H_GPP_I4 0x01080004 -#define GPIO_SKL_H_GPP_I5 0x01080005 -#define GPIO_SKL_H_GPP_I6 0x01080006 -#define GPIO_SKL_H_GPP_I7 0x01080007 -#define GPIO_SKL_H_GPP_I8 0x01080008 -#define GPIO_SKL_H_GPP_I9 0x01080009 -#define GPIO_SKL_H_GPP_I10 0x0108000A - -#define GPIO_SKL_H_GPP_J0 0x01090000 -#define GPIO_SKL_H_GPP_J1 0x01090001 -#define GPIO_SKL_H_GPP_J2 0x01090002 -#define GPIO_SKL_H_GPP_J3 0x01090003 -#define GPIO_SKL_H_GPP_J4 0x01090004 -#define GPIO_SKL_H_GPP_J5 0x01090005 -#define GPIO_SKL_H_GPP_J6 0x01090006 -#define GPIO_SKL_H_GPP_J7 0x01090007 -#define GPIO_SKL_H_GPP_J8 0x01090008 -#define GPIO_SKL_H_GPP_J9 0x01090009 -#define GPIO_SKL_H_GPP_J10 0x0109000A -#define GPIO_SKL_H_GPP_J11 0x0109000B -#define GPIO_SKL_H_GPP_J12 0x0109000C -#define GPIO_SKL_H_GPP_J13 0x0109000D -#define GPIO_SKL_H_GPP_J14 0x0109000E -#define GPIO_SKL_H_GPP_J15 0x0109000F -#define GPIO_SKL_H_GPP_J16 0x01090010 -#define GPIO_SKL_H_GPP_J17 0x01090011 -#define GPIO_SKL_H_GPP_J18 0x01090012 -#define GPIO_SKL_H_GPP_J19 0x01090013 -#define GPIO_SKL_H_GPP_J20 0x01090014 -#define GPIO_SKL_H_GPP_J21 0x01090015 -#define GPIO_SKL_H_GPP_J22 0x01090016 -#define GPIO_SKL_H_GPP_J23 0x01090017 -#define GPIO_SKL_H_GPP_K0 0x010A0000 -#define GPIO_SKL_H_GPP_K1 0x010A0001 -#define GPIO_SKL_H_GPP_K2 0x010A0002 -#define GPIO_SKL_H_GPP_K3 0x010A0003 -#define GPIO_SKL_H_GPP_K4 0x010A0004 -#define GPIO_SKL_H_GPP_K5 0x010A0005 -#define GPIO_SKL_H_GPP_K6 0x010A0006 -#define GPIO_SKL_H_GPP_K7 0x010A0007 -#define GPIO_SKL_H_GPP_K8 0x010A0008 -#define GPIO_SKL_H_GPP_K9 0x010A0009 -#define GPIO_SKL_H_GPP_K10 0x010A000A -#define GPIO_SKL_H_GPP_L2 0x010B0002 -#define GPIO_SKL_H_GPP_L3 0x010B0003 -#define GPIO_SKL_H_GPP_L4 0x010B0004 -#define GPIO_SKL_H_GPP_L5 0x010B0005 -#define GPIO_SKL_H_GPP_L6 0x010B0006 -#define GPIO_SKL_H_GPP_L7 0x010B0007 -#define GPIO_SKL_H_GPP_L8 0x010B0008 -#define GPIO_SKL_H_GPP_L9 0x010B0009 -#define GPIO_SKL_H_GPP_L10 0x010B000A -#define GPIO_SKL_H_GPP_L11 0x010B000B -#define GPIO_SKL_H_GPP_L12 0x010B000C -#define GPIO_SKL_H_GPP_L13 0x010B000D -#define GPIO_SKL_H_GPP_L14 0x010B000E -#define GPIO_SKL_H_GPP_L15 0x010B000F -#define GPIO_SKL_H_GPP_L16 0x010B0010 -#define GPIO_SKL_H_GPP_L17 0x010B0011 -#define GPIO_SKL_H_GPP_L18 0x010B0012 -#define GPIO_SKL_H_GPP_L19 0x010B0013 -#define GPIO_SKL_H_GPD0 0x010C0000 -#define GPIO_SKL_H_GPD1 0x010C0001 -#define GPIO_SKL_H_GPD2 0x010C0002 -#define GPIO_SKL_H_GPD3 0x010C0003 -#define GPIO_SKL_H_GPD4 0x010C0004 -#define GPIO_SKL_H_GPD5 0x010C0005 -#define GPIO_SKL_H_GPD6 0x010C0006 -#define GPIO_SKL_H_GPD7 0x010C0007 -#define GPIO_SKL_H_GPD8 0x010C0008 -#define GPIO_SKL_H_GPD9 0x010C0009 -#define GPIO_SKL_H_GPD10 0x010C000A -#define GPIO_SKL_H_GPD11 0x010C000B - -#endif From 8fb221dbd5ce11d27616a36eb6d5dc38bec7fd45 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 20:56:50 +0300 Subject: [PATCH 1345/1463] md/tiogapass: move all *.h to dir and make them global It is necessary to rename the file gpio.h so that there are no conflict with another file (src/include/gpio.h) Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40733 Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/Makefile.inc | 2 +- src/mainboard/ocp/tiogapass/bootblock.c | 2 +- src/mainboard/ocp/tiogapass/{ => include}/skxsp_tp_iio.h | 0 src/mainboard/ocp/tiogapass/{gpio.h => include/tp_pch_gpio.h} | 0 src/mainboard/ocp/tiogapass/romstage.c | 3 +-- 5 files changed, 3 insertions(+), 4 deletions(-) rename src/mainboard/ocp/tiogapass/{ => include}/skxsp_tp_iio.h (100%) rename src/mainboard/ocp/tiogapass/{gpio.h => include/tp_pch_gpio.h} (100%) diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 27370fd57a..e80a5940e5 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -17,5 +17,5 @@ bootblock-y += bootblock.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index dbb3b6a93f..4ca4ca5612 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -10,7 +10,7 @@ #include #include #include -#include "gpio.h" +#include /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ #define PCR_DMI_LPCIOD 0x2770 diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h similarity index 100% rename from src/mainboard/ocp/tiogapass/skxsp_tp_iio.h rename to src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h similarity index 100% rename from src/mainboard/ocp/tiogapass/gpio.h rename to src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 41f785638a..dcd198de70 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -19,8 +19,7 @@ #include #include #include - -#include "skxsp_tp_iio.h" +#include static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; From f8f9b282b4f7ce2f6b83005db0f9aa5cf3f810ec Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 30 Apr 2020 12:47:25 -0700 Subject: [PATCH 1346/1463] mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21. Signed-off-by: Andrey Petrov Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: Angel Pons --- src/mainboard/intel/cedarisland_crb/romstage.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index 94af1b6dfe..0d1ccabfea 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,8 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *start = (void *) m_cfg; + + // BoardId + write8(start + 140, 0x1d); + + // BoardTypeBitmask + write32(start + 104, 0x11111111); + + // DebugPrintLevel + write8(start + 45, 8); + + // KtiLinkSpeedMode + write8(start + 64, 0); + + // KtiPrefetchEn + write8(start + 53, 2); } From 26679699cddaccdc1539e5c0c4b82e49e7ec2900 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 30 Apr 2020 14:39:37 -0700 Subject: [PATCH 1347/1463] mb/intel/cedarisland_crb: Enable P2SB device Enable P2SB in static device tree so that hide/unhide trick works. Change-Id: I7dc20b001605b715155d333a07580e21a5f24136 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40918 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: Angel Pons --- src/mainboard/intel/cedarisland_crb/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index 6eb9557484..a82f022c0b 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -28,10 +28,10 @@ chip soc/intel/xeon_sp/cpx device pci 17.0 on end device pci 1c.0 on end device pci 1c.4 on end + device pci 1f.1 on end device pci 1f.2 on end device pci 1f.4 on end device pci 1f.5 on end - device pci 1f.0 on # LPC/eSPI Interface chip superio/common device pnp 2e.0 on From 15070e7ea86eefc211718b967e50fe44281bd879 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 30 Apr 2020 13:37:12 -0700 Subject: [PATCH 1348/1463] soc/intel/xeon_sp: Add C620 p2sb.h Add p2sb.h that is shared by all currently supported Xeon SP CPUs. Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40919 Reviewed-by: Maxim Polyakov Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/include/soc/p2sb.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 src/soc/intel/xeon_sp/include/soc/p2sb.h diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h new file mode 100644 index 0000000000..b90bc73cc1 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +/* + * Currently all known xeon-sp CPUs use C620 PCH. These definitions + * come from C620 datasheet (Intel Doc #336067-007US) + */ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) +#define PCH_P2SB_EPMASK0 0xb0 +#define P2SB_SIZE (16 * MiB) From cf270f0d62dbe2647a8e4b80d6c986a6922d47f9 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 30 Apr 2020 13:36:38 -0700 Subject: [PATCH 1349/1463] soc/intel/xeon_sp/cpx: Enable common P2SB Use common P2SB driver. This is needed to address a problem when enumerator does not see p2sb device (since it is hidden) but it is active and BAR is decoded. Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920 Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 92681f2767..15669d1827 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -74,4 +74,7 @@ config FSP_TEMP_RAM_SIZE Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config SOC_INTEL_COMMON_BLOCK_P2SB + def_bool y + endif From 4e48ac04da0cb4dd71edd039b55e04942b80ab75 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 30 Apr 2020 14:08:19 -0700 Subject: [PATCH 1350/1463] soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance Perform the P2SB hide/unhide trick. This is needed so that BAR0 (0xfd000000) is not reclaimed by resource allocator, since it can not deal with a device that does not exist (hidden). Signed-off-by: Andrey Petrov Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40921 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov --- src/soc/intel/xeon_sp/cpx/chip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 196f3df0d1..0a4cea6207 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -73,7 +74,7 @@ struct pci_operations soc_pci_ops = { static void chip_final(void *data) { - /* nothing implemented yet */ + p2sb_hide(); } static void chip_init(void *data) @@ -82,6 +83,7 @@ static void chip_init(void *data) fsp_silicon_init(false); pch_enable_ioapic(NULL); setup_lapic(); + p2sb_unhide(); } struct chip_operations soc_intel_xeon_sp_cpx_ops = { From e04c2c4527d07583201003aa95f1ebc596c11e00 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 30 Apr 2020 16:26:30 -0600 Subject: [PATCH 1351/1463] src/soc/amd/picasso: Add methods to save and restore MTRRs FSP AGESA overrides the MTRRs that coreboot set up. Until this is fixed we need to save and restore the MTRRs to undo what AGESA did. Once AGESA is fixed, we can delete these files. BUG=b:155426691, b:147042464 TEST=Boot trembyle and see MTRRs being modified Saving Variable MTRR 0: Base: 0x00000000 0xff000005, Mask: 0x0000ffff 0xff000800 Saving Variable MTRR 1: Base: 0x00000000 0x08070006, Mask: 0x0000ffff 0xffff0800 Saving Variable MTRR 2: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 3: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 4: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 5: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 6: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 7: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Fixed MTRR 0: 0x00000000 0x00000000 Saving Fixed MTRR 1: 0x00000000 0x00000000 Saving Fixed MTRR 2: 0x00000000 0x00000000 Saving Fixed MTRR 3: 0x00000000 0x00000000 Saving Fixed MTRR 4: 0x00000000 0x00000000 Saving Fixed MTRR 5: 0x00000000 0x00000000 Saving Fixed MTRR 6: 0x00000000 0x00000000 Saving Fixed MTRR 7: 0x00000000 0x00000000 Saving Fixed MTRR 8: 0x00000000 0x00000000 Saving Fixed MTRR 9: 0x00000000 0x00000000 Saving Fixed MTRR 10: 0x00000000 0x00000000 Saving Default Type MTRR: 0x00000000 0x00000800 Saving SYS_CFG: 0x00000000 0x00000800 ... MSR 0x200 was modified: 0x00000000 0x00000006 MSR 0x201 was modified: 0x0000ffff 0x80000800 MSR 0x202 was modified: 0x00000000 0x80000006 MSR 0x203 was modified: 0x0000ffff 0xc0000800 MSR 0x204 was modified: 0x00000000 0xc0000006 MSR 0x205 was modified: 0x0000ffff 0xf0000800 MSR 0x250 was modified: 0x06060606 0x06060606 MSR 0x258 was modified: 0x06060606 0x06060606 SYS_CFG was modified: 0x00000000 0x00740000 Signed-off-by: Raul E Rangel Change-Id: I6048b25bd8a32904031ca23953f9726754b5a294 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40922 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/include/soc/mtrr.h | 10 +++ src/soc/amd/picasso/mtrr.c | 112 +++++++++++++++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 src/soc/amd/picasso/include/soc/mtrr.h create mode 100644 src/soc/amd/picasso/mtrr.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index c7b6fb8bc9..40275ee4bc 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -31,6 +31,7 @@ romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += soc_util.c romstage-y += psp.c +romstage-y += mtrr.c verstage-y += gpio.c verstage-y += i2c.c diff --git a/src/soc/amd/picasso/include/soc/mtrr.h b/src/soc/amd/picasso/include/soc/mtrr.h new file mode 100644 index 0000000000..4372ca4f5d --- /dev/null +++ b/src/soc/amd/picasso/include/soc/mtrr.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __PICASSO_MTRR_H__ +#define __PICASSO_MTRR_H__ + +void picasso_save_mtrrs(void); +void picasso_restore_mtrrs(void); + +#endif /* __PICASSO_MTRR_H__ */ diff --git a/src/soc/amd/picasso/mtrr.c b/src/soc/amd/picasso/mtrr.c new file mode 100644 index 0000000000..fe142f8fc1 --- /dev/null +++ b/src/soc/amd/picasso/mtrr.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include + +/* Picasso defines 8 Variable MTRRs */ +#define MAX_VARIABLE_MTRRS 8 +#define SYS_CFG_MTRR_BITS ( \ +SYSCFG_MSR_TOM2WB | \ +SYSCFG_MSR_TOM2En | \ +SYSCFG_MSR_MtrrVarDramEn | \ +SYSCFG_MSR_MtrrFixDramModEn | \ +SYSCFG_MSR_MtrrFixDramEn \ +) + +static const unsigned int fixed_mtrr_offsets[] = { + MTRR_FIX_64K_00000, + MTRR_FIX_16K_80000, + MTRR_FIX_16K_A0000, + MTRR_FIX_4K_C0000, + MTRR_FIX_4K_C8000, + MTRR_FIX_4K_D0000, + MTRR_FIX_4K_D8000, + MTRR_FIX_4K_E0000, + MTRR_FIX_4K_E8000, + MTRR_FIX_4K_F0000, + MTRR_FIX_4K_F8000, +}; + +static int mtrrs_saved; +static msr_t sys_cfg; +static msr_t mtrr_def; +static msr_t mtrr_base[MAX_VARIABLE_MTRRS]; +static msr_t mtrr_mask[MAX_VARIABLE_MTRRS]; +static msr_t fixed_mtrrs[ARRAY_SIZE(fixed_mtrr_offsets)]; + +void picasso_save_mtrrs(void) +{ + unsigned int i; + int mtrrs; + + mtrrs = get_var_mtrr_count(); + + ASSERT_MSG(mtrrs == MAX_VARIABLE_MTRRS, "Unexpected number of MTRRs\n"); + + for (i = 0; i < MAX_VARIABLE_MTRRS; ++i) { + mtrr_base[i] = rdmsr(MTRR_PHYS_BASE(i)); + mtrr_mask[i] = rdmsr(MTRR_PHYS_MASK(i)); + printk(BIOS_DEBUG, + "Saving Variable MTRR %d: Base: 0x%08x 0x%08x, Mask: 0x%08x 0x%08x\n", i, + mtrr_base[i].hi, mtrr_base[i].lo, mtrr_mask[i].hi, mtrr_mask[i].lo); + } + + for (i = 0; i < ARRAY_SIZE(fixed_mtrr_offsets); ++i) { + fixed_mtrrs[i] = rdmsr(fixed_mtrr_offsets[i]); + printk(BIOS_DEBUG, "Saving Fixed MTRR %u: 0x%08x 0x%08x\n", i, + fixed_mtrrs[i].hi, fixed_mtrrs[i].lo); + } + + mtrr_def = rdmsr(MTRR_DEF_TYPE_MSR); + printk(BIOS_DEBUG, "Saving Default Type MTRR: 0x%08x 0x%08x\n", mtrr_def.hi, + mtrr_def.lo); + + sys_cfg = rdmsr(SYSCFG_MSR); + printk(BIOS_DEBUG, "Saving SYS_CFG: 0x%08x 0x%08x\n", mtrr_def.hi, mtrr_def.lo); + + mtrrs_saved = 1; +} + +static void update_if_changed(unsigned int offset, msr_t expected) +{ + msr_t tmp = rdmsr(offset); + if (tmp.lo == expected.lo && tmp.hi == expected.hi) + return; + + printk(BIOS_INFO, "MSR %#x was modified: 0x%08x 0x%08x\n", offset, tmp.hi, tmp.lo); + wrmsr(offset, expected); +} + +void picasso_restore_mtrrs(void) +{ + unsigned int i; + msr_t tmp_sys_cfg; + + ASSERT_MSG(mtrrs_saved, "Must save MTRRs before restoring.\n"); + + for (i = 0; i < MAX_VARIABLE_MTRRS; ++i) { + update_if_changed(MTRR_PHYS_BASE(i), mtrr_base[i]); + update_if_changed(MTRR_PHYS_MASK(i), mtrr_mask[i]); + } + + for (i = 0; i < ARRAY_SIZE(fixed_mtrr_offsets); ++i) + update_if_changed(fixed_mtrr_offsets[i], fixed_mtrrs[i]); + + update_if_changed(MTRR_DEF_TYPE_MSR, mtrr_def); + + tmp_sys_cfg = rdmsr(SYSCFG_MSR); + + /* We only care about the MTRR bits in the SYSCFG register */ + if ((tmp_sys_cfg.lo & SYS_CFG_MTRR_BITS) != (sys_cfg.lo & SYS_CFG_MTRR_BITS)) { + printk(BIOS_INFO, "SYS_CFG was modified: 0x%08x 0x%08x\n", tmp_sys_cfg.hi, + tmp_sys_cfg.lo); + tmp_sys_cfg.lo &= ~SYS_CFG_MTRR_BITS; + tmp_sys_cfg.lo |= (sys_cfg.lo & SYS_CFG_MTRR_BITS); + wrmsr(SYSCFG_MSR, tmp_sys_cfg); + } +} From 00a220877c8fc27f161017e68b67fce23117c0ad Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 20 Jan 2020 23:05:31 -0700 Subject: [PATCH 1352/1463] soc/amd/picasso: Add FSP support for including AGESA AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI build environments. Therefore, unlike the previous Arch2008 (a.k.a. v5), it can't be built without additional source, e.g. by combining with EDK II, and it has no entry points for easily building it into a legacy BIOS. AGESA in coreboot now relies on the FSP 2.0 framework published by Intel and uses the existing fsp2_0 driver. * Add fsp_memory_init() to romstage.c. Although Picasso comes out of reset with DRAM alive, this call is added to maximize compatibility and facilitate internal development. Future work may look at removing it. AGESA reports the memory map to coreboot via HOBs returned from fsp_memory_init(). * AGESA currently sets up MTRRs, as in most older generations. Take ownership back immediately before running ramstage. * Remove cbmem initialization, as the FSP driver handles this. * Add chipset_handle_reset() for compatibility. * Top of memory is determined by the FSP driver checking the HOBs passed from AGESA. Note that relying on the TOM register happens to be misleading when UMA is below 4GB. BUG=b:147042464 TEST=Boot trembyle to payload Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 11 +++++ src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/chip.c | 3 ++ src/soc/amd/picasso/memmap.c | 48 ++++++++-------------- src/soc/amd/picasso/reset.c | 10 +++++ src/soc/amd/picasso/romstage.c | 69 ++++++++++++++++++++++++++++---- 6 files changed, 104 insertions(+), 38 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5996cc632e..c807ad4c7d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -47,6 +47,10 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select SSE2 select RTC + select PLATFORM_USES_FSP2_0 + select FSP_USES_CB_STACK + select UDK_2017_BINDING + select HAVE_CF9_RESET config AMD_FP5 def_bool y if !AMD_FT5 @@ -225,6 +229,13 @@ config EARLYRAM_BSP_STACK_SIZE hex default 0x800 +config FSP_TEMP_RAM_SIZE + hex + depends on FSP_USES_CB_STACK + default 0x40000 + help + The amount of coreboot-allocated heap and stack usage by the FSP. + menu "PSP Configuration Options" config AMDFW_OUTSIDE_CBFS diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 40275ee4bc..71604d1bca 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -73,6 +73,7 @@ smm-y += psp.c CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 201afb40dd..2ab946236b 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -13,6 +13,7 @@ #include #include #include "chip.h" +#include /* Supplied by i2c.c */ extern struct device_operations picasso_i2c_mmio_ops; @@ -99,6 +100,8 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { + fsp_silicon_init(acpi_is_wakeup_s3()); + southbridge_init(chip_info); setup_bsp_ramtop(); } diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index c6fd11874a..7b504afc75 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -6,37 +6,11 @@ #include #include #include -#include #include #include -#include -#include -#include -#include -#include -#include - -void *cbmem_top_chipset(void) -{ - msr_t tom = rdmsr(TOP_MEM); - - if (!tom.lo) - return 0; - - /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE, 8*MiB); -} - -static uintptr_t smm_region_start(void) -{ - return (uintptr_t)cbmem_top(); -} - -static size_t smm_region_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} +#include +#include +#include /* * For data stored in TSEG, ensure TValid is clear so R/W access can reach @@ -63,9 +37,21 @@ static void clear_tvalid(void) void smm_region(uintptr_t *start, size_t *size) { static int once; + struct range_entry tseg; + int status; - *start = smm_region_start(); - *size = smm_region_size(); + *start = 0; + *size = 0; + + status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b); + + if (status < 0) { + printk(BIOS_ERR, "Error: unable to find TSEG HOB\n"); + return; + } + + *start = (uintptr_t)range_entry_base(&tseg); + *size = range_entry_size(&tseg); if (!once) { clear_tvalid(); diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index dda08de544..81a4cabc8e 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include void set_warm_reset_flag(void) { @@ -43,3 +45,11 @@ void do_board_reset(void) /* TODO: Would a warm_reset() suffice? */ do_cold_reset(); } + +void chipset_handle_reset(uint32_t status) +{ + printk(BIOS_ERR, "Error: unexpected call to %s(0x%08x). Doing cold reset.\n", + __func__, status); + assert(0); + do_cold_reset(); +} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index bbbc891c5a..329429ef48 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -4,8 +4,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -13,15 +15,69 @@ #include #include #include +#include +#include "chip.h" +#include void __weak mainboard_romstage_entry_s3(int s3_resume) { /* By default, don't do anything */ } +/* TODO(b/155426691): Make FSP AGESA leave MTRRs alone */ +static void clear_agesa_mtrrs(void) +{ + disable_cache(); + + picasso_restore_mtrrs(); + + enable_cache(); +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + const config_t *config = config_of_soc(); + + mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; + mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); + mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; + mcfg->serial_port_baudrate = get_uart_baudrate(); + mcfg->serial_port_refclk = uart_platform_refclk(); + + mcfg->system_config = config->system_config; + + if ((config->slow_ppt_limit) && + (config->fast_ppt_limit) && + (config->slow_ppt_time_constant) && + (config->stapm_time_constant)) { + mcfg->slow_ppt_limit = config->slow_ppt_limit; + mcfg->fast_ppt_limit = config->fast_ppt_limit; + mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant; + mcfg->stapm_time_constant = config->stapm_time_constant; + } + + mcfg->sustained_power_limit = config->sustained_power_limit; + mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time; + mcfg->thermctl_limit = config->thermctl_limit; + mcfg->psi0_current_limit = config->psi0_current_limit; + mcfg->psi0_soc_current_limit = config->psi0_soc_current_limit; + mcfg->vddcr_soc_voltage_margin = config->vddcr_soc_voltage_margin; + mcfg->vddcr_vdd_voltage_margin = config->vddcr_vdd_voltage_margin; + mcfg->vrm_maximum_current_limit = config->vrm_maximum_current_limit; + mcfg->vrm_soc_maximum_current_limit = config->vrm_soc_maximum_current_limit; + mcfg->vrm_current_limit = config->vrm_current_limit; + mcfg->vrm_soc_current_limit = config->vrm_soc_current_limit; + mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en; + mcfg->core_dldo_bypass = config->core_dldo_bypass; + mcfg->min_soc_vid_offset = config->min_soc_vid_offset; + mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz; +} + asmlinkage void car_stage_entry(void) { - uintptr_t top_of_mem; int s3_resume; post_code(0x40); @@ -37,16 +93,15 @@ asmlinkage void car_stage_entry(void) printk(BIOS_DEBUG, "Family_Model: %08x\n", val); post_code(0x43); - top_of_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 8 * MiB); - backup_top_of_low_cacheable(top_of_mem); + picasso_save_mtrrs(); post_code(0x44); - if (cbmem_recovery(s3_resume)) - printk(BIOS_CRIT, "Failed to recover cbmem\n"); - if (romstage_handoff_init(s3_resume)) - printk(BIOS_ERR, "Failed to set romstage handoff data\n"); + fsp_memory_init(s3_resume); post_code(0x45); + clear_agesa_mtrrs(); + + post_code(0x46); run_ramstage(); post_code(0x50); /* Should never see this post code. */ From 806ea463dbc20c9a577923af51e9976baaf6790a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Sat, 11 Apr 2020 10:06:37 -0600 Subject: [PATCH 1353/1463] soc/amd/picasso: add sd/emmc0 configuration to chip.h In order to isolate mainboard code from direct FSPS manipulation allow sd/emmc0 configuration to be supplied by devicetree.cb. BUG=b:153502861 Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Commit-Queue: Aaron Durbin Tested-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/chip.h | 15 ++++++ src/soc/amd/picasso/fsp_params.c | 52 +++++++++++++++++++ .../include/soc/platform_descriptors.h | 15 ++++++ 3 files changed, 82 insertions(+) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index edb1b69bb0..7c6823239c 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -86,6 +86,21 @@ struct soc_amd_picasso_config { enum spi100_speed spi_fast_speed; enum spi100_speed spi_altio_speed; enum spi100_speed spi_tpm_speed; + + enum { + SD_EMMC_DISABLE, + SD_EMMC_SD_LOW_SPEED, + SD_EMMC_SD_HIGH_SPEED, + SD_EMMC_SD_UHS_I_SDR_50, + SD_EMMC_SD_UHS_I_DDR_50, + SD_EMMC_SD_UHS_I_SDR_104, + SD_EMMC_EMMC_SDR_26, + SD_EMMC_EMMC_SDR_52, + SD_EMMC_EMMC_DDR_52, + SD_EMMC_EMMC_HS200, + SD_EMMC_EMMC_HS400, + SD_EMMC_EMMC_HS300, + } sd_emmc_config; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 0dbda093f3..d11dae201c 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -7,6 +7,55 @@ #include #include "chip.h" +static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + int val = SD_DISABLE; + + switch (cfg->sd_emmc_config) { + case SD_EMMC_DISABLE: + val = SD_DISABLE; + break; + case SD_EMMC_SD_LOW_SPEED: + val = SD_LOW_SPEED; + break; + case SD_EMMC_SD_HIGH_SPEED: + val = SD_HIGH_SPEED; + break; + case SD_EMMC_SD_UHS_I_SDR_50: + val = SD_UHS_I_SDR_50; + break; + case SD_EMMC_SD_UHS_I_DDR_50: + val = SD_UHS_I_DDR_50; + break; + case SD_EMMC_SD_UHS_I_SDR_104: + val = SD_UHS_I_SDR_104; + break; + case SD_EMMC_EMMC_SDR_26: + val = EMMC_SDR_26; + break; + case SD_EMMC_EMMC_SDR_52: + val = EMMC_SDR_52; + break; + case SD_EMMC_EMMC_DDR_52: + val = EMMC_DDR_52; + break; + case SD_EMMC_EMMC_HS200: + val = EMMC_HS200; + break; + case SD_EMMC_EMMC_HS400: + val = EMMC_HS400; + break; + case SD_EMMC_EMMC_HS300: + val = EMMC_HS300; + break; + default: + break; + } + + scfg->emmc0_mode = val; +} + static void fill_pcie_descriptors(FSP_S_CONFIG *scfg, const picasso_fsp_pcie_descriptor *descs, size_t num) { @@ -49,7 +98,10 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { + const struct soc_amd_picasso_config *cfg; FSP_S_CONFIG *scfg = &supd->FspsConfig; + cfg = config_of_soc(); + fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); } diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index bc67550fd0..7a8444b062 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -8,6 +8,21 @@ #include #include +/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG. + * TODO: Remove when official definitions arrive. */ +#define SD_DISABLE 0 +#define SD_LOW_SPEED 1 +#define SD_HIGH_SPEED 2 +#define SD_UHS_I_SDR_50 3 +#define SD_UHS_I_DDR_50 4 +#define SD_UHS_I_SDR_104 5 +#define EMMC_SDR_26 6 +#define EMMC_SDR_52 7 +#define EMMC_DDR_52 8 +#define EMMC_HS200 9 +#define EMMC_HS400 10 +#define EMMC_HS300 11 + /* Mainboard callback to obtain PCIe and DDI descriptors. */ void mainboard_get_pcie_ddi_descriptors( const picasso_fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, From 50c1f27069535beedc6ee36232a3ebab35b5c625 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 1 May 2020 14:56:49 -0700 Subject: [PATCH 1354/1463] libpayload: xhci: Fix CAPREG address calculation I rushed CB:40895 in to fix a bug only to introduce another. xhci_init() no longer crashes, but it doesn't correctly initialize the XHCI controller either, and unfortunately the error messages are all hidden behind USB_DEBUG. This patch fixes the incorrect address calculation to what it was before CB:39838. Signed-off-by: Julius Werner Change-Id: I14293e2135108db30ba6fd2efea0573fe266fa37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40956 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Nico Huber --- payloads/libpayload/drivers/usb/xhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 21af579f4c..08a81ef5d5 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -185,7 +185,7 @@ xhci_init (unsigned long physical_bar) goto _free_xhci; } - xhci->capreg = phys_to_virt(physical_bar) + sizeof(xhci->capreg); + xhci->capreg = phys_to_virt(physical_bar); xhci->opreg = phys_to_virt(physical_bar) + CAP_GET(CAPLEN, xhci->capreg); xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg->rtsoff; xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg->dboff; From a268aac9e5b79dcd96ab3411413f4385bfecfe5e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 14:30:31 -0700 Subject: [PATCH 1355/1463] src/acpi: Drop Kconfig option ACPI_SATA_GENERATOR ACPI_SATA_GENERATOR is currently used to include sata.c in ramstage. However, there is no need to guard this inclusion using a separate Kconfig. All other files that deal with ACPI tables are included based on the state of HAVE_ACPI_TABLES. This change includes sata.c in ramstage if HAVE_ACPI_TABLES is selected. If the ACPI function isn't used, linker will optimize it out. BUG=b:155428745 Change-Id: I9a319cfe7c3f973b15ccbd0f13bd1ed07571a398 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40928 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Duncan Laurie Reviewed-by: Aaron Durbin --- src/acpi/Kconfig | 6 ------ src/acpi/Makefile.inc | 2 +- src/southbridge/intel/bd82x6x/Kconfig | 1 - src/southbridge/intel/ibexpeak/Kconfig | 1 - 4 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 3c6aeb1a18..8c8bb87884 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -1,12 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. -config ACPI_SATA_GENERATOR - bool - default n - help - Use ACPI SATA port generator. - config ACPI_INTEL_HARDWARE_SLEEP_VALUES def_bool n help diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 7c2092d5f5..e99110ec24 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. -ramstage-$(CONFIG_ACPI_SATA_GENERATOR) += sata.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sata.c diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 534d110e70..b6478aedca 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -27,7 +27,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select COMMON_FADT - select ACPI_SATA_GENERATOR select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON_GPIO select RTC diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 2b59134ae2..856dc61487 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -36,7 +36,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG_OPTIONS select COMMON_FADT - select ACPI_SATA_GENERATOR select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON_GPIO select HAVE_INTEL_CHIPSET_LOCKDOWN From b1859a6687553900337c9ace092517e921e95e3b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 21:27:47 -0700 Subject: [PATCH 1356/1463] cpu: Add a helper function cpu_get_lapic_addr This change adds a helper function cpu_get_lapic_addr() that returns LOCAL_APIC_ADDR for x86. It also adds a weak default implementation which returns 0 if platform does not support LAPIC. This is being done in preparation to move all ACPI table support in coreboot out of arch/x86. BUG=b:155428745 Change-Id: I4d9c50ee46804164712aaa22be1b434f800871ec Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40929 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie --- src/arch/x86/acpi.c | 12 ++++++++++-- src/arch/x86/cpu.c | 5 +++++ src/include/cpu/cpu.h | 1 + 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 5c15a5e6af..8e7b51d79d 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -222,6 +221,15 @@ int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, return lapic_nmi->length; } +__weak uintptr_t cpu_get_lapic_addr(void) +{ + /* + * If an architecture does not support LAPIC, this weak implementation returns LAPIC + * addr as 0. + */ + return 0; +} + void acpi_create_madt(acpi_madt_t *madt) { acpi_header_t *header = &(madt->header); @@ -242,7 +250,7 @@ void acpi_create_madt(acpi_madt_t *madt) header->length = sizeof(acpi_madt_t); header->revision = get_acpi_table_revision(MADT); - madt->lapic_addr = LOCAL_APIC_ADDR; + madt->lapic_addr = cpu_get_lapic_addr(); if (CONFIG(ACPI_HAVE_PCAT_8259)) madt->flags |= 1; diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 1ee8fb32c3..b52376885f 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -354,3 +354,8 @@ int cpu_index(void) } return -1; } + +uintptr_t cpu_get_lapic_addr(void) +{ + return LOCAL_APIC_ADDR; +} diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cdb681729e..db324b6da9 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -6,6 +6,7 @@ void cpu_initialize(unsigned int cpu_index); /* Returns default APIC id based on logical_cpu number or < 0 on failure. */ int cpu_get_apic_id(int logical_cpu); +uintptr_t cpu_get_lapic_addr(void); /* Function to keep track of cpu default apic_id */ void cpu_add_map_entry(unsigned int index); struct bus; From dc78275993acfc0ff4d58452e4829d65bc3a963a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 22:49:39 -0700 Subject: [PATCH 1357/1463] arch/x86: Change power_res_dev_states[] to be static const * const This change makes power_res_dev_states[] to be static const * const as complained by Jenkins. BUG=b:155428745 Change-Id: Ice2fff6ab3bcd72a059bc905b7462a681f2e6aaf Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40935 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/acpi_device.c | 2 +- src/arch/x86/acpigen.c | 2 +- src/arch/x86/include/arch/acpigen.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index bef1a5db73..9f63200121 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -527,7 +527,7 @@ void acpi_device_write_spi(const struct acpi_spi *spi) /* PowerResource() with Enable and/or Reset control */ void acpi_device_add_power_res(const struct acpi_power_res_params *params) { - static const char *power_res_dev_states[] = { "_PR0", "_PR3" }; + static const char * const power_res_dev_states[] = { "_PR0", "_PR3" }; unsigned int reset_gpio = params->reset_gpio ? params->reset_gpio->pins[0] : 0; unsigned int enable_gpio = params->enable_gpio ? params->enable_gpio->pins[0] : 0; unsigned int stop_gpio = params->stop_gpio ? params->stop_gpio->pins[0] : 0; diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 34de2bab18..dfc2a5adf4 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1147,7 +1147,7 @@ void acpigen_write_uuid(const char *uuid) * PowerResource (name, level, order) */ void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, - const char *dev_states[], size_t dev_states_count) + const char * const dev_states[], size_t dev_states_count) { size_t i; for (i = 0; i < dev_states_count; i++) { diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 3339ce4d92..a3c4777afb 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -347,7 +347,7 @@ void acpigen_write_mainboard_resources(const char *scope, const char *name); void acpigen_write_irq(u16 mask); void acpigen_write_uuid(const char *uuid); void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, - const char *dev_states[], size_t dev_states_count); + const char * const dev_states[], size_t dev_states_count); void acpigen_write_sleep(uint64_t sleep_ms); void acpigen_write_store(void); void acpigen_write_store_ops(uint8_t src, uint8_t dst); From 8bd784eba5376eed3ad07c147096dc379ffbd187 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 5 Apr 2020 14:54:22 -0400 Subject: [PATCH 1358/1463] nb/intel/i440bx: Clean up register_values table The table of initial i440BX register values has a bitmask that allows preserving certain bits as they are programmed. This feature has been unused since day one and probably will never be used. So drop it. Drop DRB, RPS, PGPOL registers from the table as they will be programmed during RAM init. These two reductions combined saved ~104 bytes. Drop unneeded SDRAMC "+0". Slightly compact a comment block. TEST=Boot tested on asus/p2b-ls, i440bx config did not change Change-Id: I020f616455bb671fe284993a488beb6386a03d0d Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40391 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/i440bx/raminit.c | 101 ++++++++++--------------- 1 file changed, 42 insertions(+), 59 deletions(-) diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index e2db5e70ea..dddcc217f4 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -60,7 +60,7 @@ static const uint32_t refresh_rate_map[] = { 1, 5, 5, 2, 3, 4 }; -/* Table format: register, bitmask, value. */ +/* Table format: register, value. */ static const u8 register_values[] = { /* NBXCFG - NBX Configuration Register * 0x50 - 0x53 @@ -122,11 +122,11 @@ static const u8 register_values[] = { * 0 = A7# is sampled asserted (i.e., 0) * [01:00] Reserved */ - NBXCFG + 0, 0x00, 0x0c, + NBXCFG + 0, 0x0c, // TODO: Bit 15 should be 0 for multiprocessor boards - NBXCFG + 1, 0x00, 0x80, - NBXCFG + 2, 0x00, 0x00, - NBXCFG + 3, 0x00, 0xff, + NBXCFG + 1, 0x80, + NBXCFG + 2, 0x00, + NBXCFG + 3, 0xff, /* DRAMC - DRAM Control Register * 0x57 @@ -156,7 +156,7 @@ static const u8 register_values[] = { * 111 = Reserved */ /* Choose SDRAM (not registered), and disable refresh for now. */ - DRAMC, 0x00, 0x08, + DRAMC, 0x08, /* * PAM[6:0] - Programmable Attribute Map Registers @@ -190,13 +190,13 @@ static const u8 register_values[] = { * registers are not set here appropriately, the RAM in that region * will not be accessible, thus a RAM check of it will also fail. */ - PAM0, 0x00, 0x30, - PAM1, 0x00, 0x33, - PAM2, 0x00, 0x33, - PAM3, 0x00, 0x33, - PAM4, 0x00, 0x33, - PAM5, 0x00, 0x33, - PAM6, 0x00, 0x33, + PAM0, 0x30, + PAM1, 0x33, + PAM2, 0x33, + PAM3, 0x33, + PAM4, 0x33, + PAM5, 0x33, + PAM6, 0x33, /* DRB[0:7] - DRAM Row Boundary Registers * 0x60 - 0x67 @@ -214,14 +214,6 @@ static const u8 register_values[] = { * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) */ /* DRBs will be set later. */ - DRB0, 0x00, 0x00, - DRB1, 0x00, 0x00, - DRB2, 0x00, 0x00, - DRB3, 0x00, 0x00, - DRB4, 0x00, 0x00, - DRB5, 0x00, 0x00, - DRB6, 0x00, 0x00, - DRB7, 0x00, 0x00, /* FDHC - Fixed DRAM Hole Control Register * 0x68 @@ -236,7 +228,7 @@ static const u8 register_values[] = { * [5:0] Reserved */ /* No memory holes. */ - FDHC, 0x00, 0x00, + FDHC, 0x00, /* RPS - SDRAM Row Page Size Register * 0x74 - 0x75 @@ -261,8 +253,6 @@ static const u8 register_values[] = { * [15:14] DRB[7], row 7 */ /* Power on defaults to 2KB. Will be set later. */ - // RPS + 0, 0x00, 0x00, - // RPS + 1, 0x00, 0x00, /* SDRAMC - SDRAM Control Register * 0x76 - 0x77 @@ -298,9 +288,9 @@ static const u8 register_values[] = { * 1 = 2 clocks of RAS# precharge */ #if CONFIG(SDRAMPWR_4DIMM) - SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ + SDRAMC, 0x10, /* The board has 4 DIMM slots. */ #else - SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */ + SDRAMC, 0x00, /* The board has 3 DIMM slots. */ #endif /* PGPOL - Paging Policy Register @@ -325,40 +315,38 @@ static const u8 register_values[] = { * 0111 = 32 clocks * 1xxx = Infinite (pages are not closed for idle condition) */ - PGPOL + 0, 0x00, 0x00, - PGPOL + 1, 0x00, 0xff, + /* PGPOL will be set later. */ /* PMCR - Power Management Control Register * 0x7a * - * [07:07] Power Down SDRAM Enable (PDSE) - * 1 = Enable - * 0 = Disable - * [06:06] ACPI Control Register Enable (SCRE) - * 1 = Enable - * 0 = Disable (default) - * [05:05] Suspend Refresh Type (SRT) - * 1 = Self refresh mode - * 0 = CBR fresh mode - * [04:04] Normal Refresh Enable (NREF_EN) - * 1 = Enable - * 0 = Disable - * [03:03] Quick Start Mode (QSTART) - * 1 = Quick start mode for the processor is enabled - * [02:02] Gated Clock Enable (GCLKEN) - * 1 = Enable - * 0 = Disable - * [01:01] AGP Disable (AGP_DIS) - * 1 = Disable - * 0 = Enable - * [00:00] CPU reset without PCIRST enable (CRst_En) - * 1 = Enable - * 0 = Disable + * [7] Power Down SDRAM Enable (PDSE) + * 1 = Enable + * 0 = Disable + * [6] ACPI Control Register Enable (SCRE) + * 1 = Enable + * 0 = Disable (default) + * [5] Suspend Refresh Type (SRT) + * 1 = Self refresh mode + * 0 = CBR fresh mode + * [4] Normal Refresh Enable (NREF_EN) + * 1 = Enable + * 0 = Disable + * [3] Quick Start Mode (QSTART) + * 1 = Quick start mode for the processor is enabled + * [2] Gated Clock Enable (GCLKEN) + * 1 = Enable + * 0 = Disable + * [1] AGP Disable (AGP_DIS) + * 1 = AGP disabled (Hardware strap) + * [0] CPU reset without PCIRST enable (CRst_En) + * 1 = Enable + * 0 = Disable */ /* PMCR will be set later. */ /* Enable SCRR.SRRAEN and let BX choose the SRR. */ - SCRR + 1, 0x00, 0x10, + SCRR + 1, 0x10, }; /*----------------------------------------------------------------------------- @@ -666,7 +654,6 @@ Public interface. static void sdram_set_registers(void) { int i, max; - uint8_t reg; PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); @@ -674,12 +661,8 @@ static void sdram_set_registers(void) max = ARRAY_SIZE(register_values); /* Set registers as specified in the register_values[] array. */ - for (i = 0; i < max; i += 3) { - reg = pci_read_config8(NB, register_values[i]); - reg &= register_values[i + 1]; - reg |= register_values[i + 2] & ~(register_values[i + 1]); - pci_write_config8(NB, register_values[i], reg); - } + for (i = 0; i < max; i += 2) + pci_write_config8(NB, register_values[i], register_values[i + 1]); } struct dimm_size { From 5687c98f756bfb8621e8297c3d1eee1d7be515cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 29 Apr 2020 14:50:49 +0200 Subject: [PATCH 1359/1463] mb/supermicro/x11: drop DeepSx config from devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the DeepSx config as it's unsupported and disabled for the boards. Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/40858 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons --- src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 998f3dd366..0dd37eeafa 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -2,7 +2,6 @@ chip soc/intel/skylake register "deep_s5_enable_ac" = "0" register "deep_s5_enable_dc" = "0" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" From 7bab4c90a72a0e3599d6dbda0a72e8d470fd3fbf Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2020 10:34:37 -0500 Subject: [PATCH 1360/1463] mb/google/reef: add default non-ChromeOS FMAP Add a FMAP which supports SMMSTORE and non-ChromeOS payloads, since Apollo Lake-based devices like Reef cannot use an automatically-generated FMAP due to strict layout requirements. Change-Id: If570f92f4f81c0e29777c87756fc5e45af549064 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40907 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/default.fmd | 28 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 src/mainboard/google/reef/default.fmd diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5d782b1cef..6b970b28ac 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -100,4 +100,7 @@ config PRERAM_CBMEM_CONSOLE_SIZE default 0xe00 if CHROMEOS default 0xc00 +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS + endif # BOARD_GOOGLE_REEF diff --git a/src/mainboard/google/reef/default.fmd b/src/mainboard/google/reef/default.fmd new file mode 100644 index 0000000000..d6433137ab --- /dev/null +++ b/src/mainboard/google/reef/default.fmd @@ -0,0 +1,28 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xf6f000 { + IFWI@0x0 0x1ff000 + # SMMSTORE requires 64k alignment + SMMSTORE@0xa5e000 0x40000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 + } + FMAP 0x300 + COREBOOT(CBFS) + BIOS_UNUSABLE 0x4f000 + } + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} From 076605bc92730553e9adae543713f0d356a94709 Mon Sep 17 00:00:00 2001 From: Eugene D Myers Date: Wed, 15 Apr 2020 18:28:10 -0400 Subject: [PATCH 1361/1463] intel/stm: Place resource list right below MSEG Suggested by Nico Huber in CB:38765. This placement makes the address calculation simpler and makes its location indepedent of the number of CPUs. As part of the change in the BIOS resource list address calculation, the `size` variable was factored out of the conditional in line 361, thus eliminating the else. Change-Id: I9ee2747474df02b0306530048bdec75e95413b5d Signed-off-by: Eugene D Myers Reviewed-on: https://review.coreboot.org/c/coreboot/+/40437 Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/x86/smm/smm_module_loader.c | 18 +++++++----------- src/security/intel/stm/StmPlatformSmm.c | 7 +------ 2 files changed, 8 insertions(+), 17 deletions(-) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index bdcf2834ed..c08e83369e 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -307,13 +307,13 @@ int smm_setup_relocation_handler(struct smm_loader_params *params) /* The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size - * | stacks | - * +-----------------+ <- smram + size - total_stack_size - * | fxsave area | - * +-----------------+ <- smram + size - total_stack_size - fxsave_size * | BIOS resource | * | list (STM) | - * +-----------------+ <- .. - CONFIG_BIOS_RESOURCE_LIST_SIZE + * +-----------------+ <- smram + size - CONFIG_BIOS_RESOURCE_LIST_SIZE + * | stacks | + * +-----------------+ <- .. - total_stack_size + * | fxsave area | + * +-----------------+ <- .. - total_stack_size - fxsave_size * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE * | handler | @@ -354,11 +354,10 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Stacks start at the top of the region. */ base = smram; + base += size; if (CONFIG(STM)) - base += size - CONFIG_MSEG_SIZE; // take out the mseg - else - base += size; + base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; params->stack_top = base; @@ -388,9 +387,6 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - /* Account for the BIOS resource list */ - if (CONFIG(STM)) - total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; if (total_size > size) return -1; diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 45db0e069f..248ccc028a 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -177,12 +177,7 @@ void stm_setup(uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, // need to create the BIOS resource list once // first calculate the location in SMRAM - addr_calc = (mseg - (CONFIG_SMM_MODULE_STACK_SIZE * num_cpus)); - - if (CONFIG(SSE)) - addr_calc -= FXSAVE_SIZE * num_cpus; - - addr_calc -= CONFIG_BIOS_RESOURCE_LIST_SIZE; + addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); From f213f1799244ccfe4acab99c22df3dd183a3965b Mon Sep 17 00:00:00 2001 From: Eugene D Myers Date: Wed, 15 Apr 2020 19:11:52 -0400 Subject: [PATCH 1362/1463] intel/stm: Drop now unneeded `num_cpus` param Suggested by Nico Huber in CB:38766 Change-Id: Ib8a340f17a12951bc6bc67e3093046575e7b0e46 Signed-off-by: Eugene D Myers Reviewed-on: https://review.coreboot.org/c/coreboot/+/40438 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/x86/mp_init.c | 2 +- src/security/intel/stm/SmmStm.h | 2 +- src/security/intel/stm/StmPlatformSmm.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index fa550f137a..44a29151b5 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -741,7 +741,7 @@ static void asmlinkage smm_do_relocation(void *arg) mseg = mp_state.perm_smbase + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); - stm_setup(mseg, p->cpu, runtime->num_cpus, + stm_setup(mseg, p->cpu, perm_smbase, mp_state.perm_smbase, runtime->start32_offset); diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h index 4f72816cae..169025553a 100644 --- a/src/security/intel/stm/SmmStm.h +++ b/src/security/intel/stm/SmmStm.h @@ -28,7 +28,7 @@ int load_stm_image(uintptr_t mseg); void stm_setup( - uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, + uintptr_t mseg, int cpu, uintptr_t smbase, uintptr_t smbase_base, uint32_t offset32); /* diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 248ccc028a..b9d2686f35 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -154,7 +154,7 @@ extern uint8_t *stm_resource_heap; static int stm_load_status = 0; -void stm_setup(uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, +void stm_setup(uintptr_t mseg, int cpu, uintptr_t smbase, uintptr_t base_smbase, uint32_t offset32) { msr_t InitMseg; @@ -163,7 +163,7 @@ void stm_setup(uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, uintptr_t addr_calc; // used to calculate the stm resource heap area - printk(BIOS_DEBUG, "STM: set up for cpu %d/%d\n", cpu, num_cpus); + printk(BIOS_DEBUG, "STM: set up for cpu %d\n", cpu); vmx_basic = rdmsr(IA32_VMX_BASIC_MSR); From 9d821fa1d12ccdb8e7816cab14ef5abdc8143f7a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 26 Mar 2020 21:13:24 -0500 Subject: [PATCH 1363/1463] payloads/seabios: Add Hardware IRQ Kconfig Certain boards require SeaBIOS' HARDWARE_IRQ option to be deselected in order for the platform to boot. Add a Kconfig to allow selection of HARDWARE_IRQ enablement, and write to SeaBIOS' .config file in cases where it needs to be disabled. Deselect the option for google/rambi variants so they boot with boards defaults. Test: build/boot google/clapper, verify board boots vs hanging at boot menu prompt. Change-Id: I23e9b30d2d1042c86bd10f134d6fe361edaf8cb2 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39869 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- payloads/external/SeaBIOS/Kconfig | 10 ++++++++++ payloads/external/SeaBIOS/Makefile | 3 +++ src/mainboard/google/rambi/Kconfig | 5 +++++ 3 files changed, 18 insertions(+) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index e816775f28..21e47206f4 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -51,6 +51,16 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_HARDWARE_IRQ + prompt "Hardware Interrupts" + default y + bool + help + Program and support hardware interrupts using the i8259 + programmable interrupt controller (PIC). Deselected by + boards which would otherwise hang at the boot menu (eg, + google/rambi). + config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" default y if !VENDOR_EMULATION diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 0086775b8d..cd646d9d73 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -72,6 +72,9 @@ endif ifneq ($(CONFIG_SEABIOS_DEBUG_LEVEL),-1) echo "CONFIG_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL)" >> seabios/.config endif +ifneq ($(CONFIG_SEABIOS_HARDWARE_IRQ),y) + echo "# CONFIG_HARDWARE_IRQ is not set" >> seabios/.config +endif # This shows how to force a previously set .config option *off* # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index bc4aa6ea7c..3cb5e26277 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -77,6 +77,11 @@ config MAINBOARD_SMBIOS_MANUFACTURER default "GOOGLE" config CONSOLE_SERIAL + bool + default n + +config SEABIOS_HARDWARE_IRQ + bool default n endif # BOARD_GOOGLE_BASEBOARD_RAMBI From 8c4ad5b4a56769327c3da80c57091f23c24016d7 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Fri, 1 May 2020 20:59:28 +0800 Subject: [PATCH 1364/1463] mainboard/google/kahlee: Add hook for early wlan rst gpio init Base on the grunt board schematic, gpio70 is an alternative way for wlan rst. Add hook for variants to override default state. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chiu Change-Id: Ic3f1c016357dd5090e6adedf96e7593abff29a0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40944 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/kahlee/bootblock/bootblock.c | 3 +++ .../google/kahlee/variants/baseboard/gpio.c | 15 ++++++++++++--- .../baseboard/include/baseboard/variants.h | 1 + 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 613b35b41e..338edfd62c 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -17,6 +17,9 @@ void bootblock_mainboard_early_init(void) /* Enable the EC as soon as we have visibility */ mainboard_ec_init(); + gpios = variant_wlan_rst_early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + gpios = variant_early_gpio_table(&num_gpios); program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 4fb60b1fcf..fe0744a62a 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -42,9 +42,6 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* GPIO_40 - EMMC_BRIDGE_RST */ PAD_GPO(GPIO_40, LOW), - /* GPIO_70 - WLAN_PE_RST_L */ - PAD_GPO(GPIO_70, HIGH), - /* GPIO_74 - LPC_CLK0_EC_R */ PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN), @@ -77,6 +74,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { PAD_GPI(GPIO_142, PULL_NONE), }; +static const struct soc_amd_gpio gpio_wlan_rst_early_reset[] = { + /* GPIO_70 - WLAN_PE_RST_L */ + PAD_GPO(GPIO_70, HIGH), +}; + static const struct soc_amd_gpio gpio_set_stage_rom[] = { /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */ PAD_GPO(GPIO_133, HIGH), @@ -247,6 +249,13 @@ struct soc_amd_gpio *variant_early_gpio_table(size_t *size) return gpio_set_stage_reset; } +const __weak +struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_wlan_rst_early_reset); + return gpio_wlan_rst_early_reset; +} + const __weak struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) { diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 02d413f6a6..8b789929f8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,7 @@ int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size); const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size); const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); From eba32d217a7979dc1fa860c325351f86b98feb13 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2020 16:06:37 -0500 Subject: [PATCH 1365/1463] mb/purism/librem_bdw: Clean up 15v2 devicetree The Librem 15v2 only uses SATA ports 0/1, so the DTLE settings for ports 2/3 have no consequence. Drop them to make overridetree conversion cleaner. Signed-off-by: Matt DeVillier Change-Id: I4145feecb389be90f317249426e58752c03aef76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40914 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../purism/librem_bdw/variants/librem15v2/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb index 32c3ed166f..cbd59bec8e 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb @@ -28,8 +28,6 @@ chip soc/intel/broadwell # Port tuning for link stability register "sata_port0_gen3_dtle" = "7" register "sata_port1_gen3_dtle" = "9" - register "sata_port2_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "7" device cpu_cluster 0 on device lapic 0 on end From 819005332b37a424cbeeb7cc75fc9a154b55fcfb Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2020 16:12:05 -0500 Subject: [PATCH 1366/1463] mb/purism/librem_bdw: Convert to use override devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier Change-Id: I07fb5a09e578bf299081b26e010317385a6c5f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40915 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons --- src/mainboard/purism/librem_bdw/Kconfig | 4 +- .../{variants/librem15v2 => }/devicetree.cb | 10 +-- .../variants/librem13v1/devicetree.cb | 72 ------------------- .../variants/librem13v1/overridetree.cb | 14 ++++ .../variants/librem15v2/overridetree.cb | 14 ++++ 5 files changed, 31 insertions(+), 83 deletions(-) rename src/mainboard/purism/librem_bdw/{variants/librem15v2 => }/devicetree.cb (90%) delete mode 100644 src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb create mode 100644 src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb create mode 100644 src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index d9747f52e0..27ae21f8aa 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -17,9 +17,9 @@ config VARIANT_DIR default "librem13v1" if BOARD_PURISM_LIBREM13_V1 default "librem15v2" if BOARD_PURISM_LIBREM15_V2 -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config DRIVERS_UART_8250IO def_bool n diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb similarity index 90% rename from src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb rename to src/mainboard/purism/librem_bdw/devicetree.cb index cbd59bec8e..13b9e5e729 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -21,14 +21,6 @@ chip soc/intel/broadwell register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" - # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device cpu_cluster 0 on device lapic 0 on end end @@ -58,7 +50,7 @@ chip soc/intel/broadwell device pci 1c.3 on end # PCIe Port #4 - WiFi device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 on end # USB2 EHCI + device pci 1d.0 off end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip ec/purism/librem diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb deleted file mode 100644 index 98b5163b5f..0000000000 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DDI1 Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - - # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port 0 tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal - end -end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb new file mode 100644 index 0000000000..d3d0ae72d0 --- /dev/null +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -0,0 +1,14 @@ +chip soc/intel/broadwell + + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device domain 0 on + device pci 1c.2 on end # PCIe Port #3 - LAN + end +end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb new file mode 100644 index 0000000000..c0c8d0360f --- /dev/null +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -0,0 +1,14 @@ +chip soc/intel/broadwell + + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device domain 0 on + device pci 1d.0 on end # USB2 EHCI + end +end From bc26e771708b6cf20b77eb3427c09c093448cb8a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2020 19:01:51 -0500 Subject: [PATCH 1367/1463] mb/google/reef: Add and use VBT Add VBT file, and override use via Kconfig since all Reef variants use the same VBT file. VBT extracted from firmware in ChromeOS recovery image. Test: built/boot google/reef w/FSP display init Change-Id: I31156ec7371c0443719fdd9ddac6ed4960c83767 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40926 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/google/reef/Kconfig | 5 +++++ src/mainboard/google/reef/data.vbt | Bin 0 -> 6656 bytes 2 files changed, 5 insertions(+) create mode 100644 src/mainboard/google/reef/data.vbt diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 6b970b28ac..25d02cdc94 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -12,6 +12,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 @@ -103,4 +104,8 @@ config PRERAM_CBMEM_CONSOLE_SIZE config FMDFILE default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS +# Override the default behavior, since the data.vbt is the same for all variants +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + endif # BOARD_GOOGLE_REEF diff --git a/src/mainboard/google/reef/data.vbt b/src/mainboard/google/reef/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..d9a55d2bb24ddc370a06fda07ddad061b45134c4 GIT binary patch literal 6656 zcmeHLZ%iCT6o0$R{hQrAjs-2fBAxz`9<+spwpWTMdmK=%g>nZJF`DqFceO-XC{U%= zmNn9Z#MImeHPtkVF-B9rkf@)Gv3^jSG+Owerk|u~Olo73Cf4YOw&$DOg#%i`wbnni zyvy77=FOYm%)FV|d3&o{Dw}C#V?%3m!wzau6jUJDS@^t}DnkuTZB>EhKwD*9LvTAi z3lGA%B{wbsL^*D$RIIASp?w3fZeL?Qt?%jV>W&pv#rmHa=;@{5V2B2G?TU5B`Z@+; zQQFk9H9#4jOezm_bw}xr1A9ATePt9uRP?6B8w)pVq_kvnk-DL%L@nNgHD$&AvQ1lL zQdJ#ns1Jwg0?i>Dctazt3N;0qnyTw7>z<(D#)jHZWvIEjN+z?W5bWta*w^*+o&o9$ z=F<}FXT5=I44DRd`g#j#pu3wkGM|3h80(MqJsXP_%7g)(0%sZrz}X;O0}ig205}2C z05kwPtDpG_9^f}|JhsSlf<1f6i?u~~0fh&#Ska<1_-YS$JkCql4@H{;dqzd_-g2y@!(3xHoO^n_ax23><0as9uRV|b8`EZjV}#S; zRM_pxg{^`Q1_U0C2&J$x?KC)D6xO;t@ECFg`HYRgcgQ~?|BU=A@^xf~oj?ZiGUSJm zi;%Y<2a)TMA4l#$wjY3N30`MQfTVMl%rGT*(%_YR&`((Q6PDd|1s5BMSW>j4VNBtX zNH`pDBk^rEBofX?*$6a5z-e<;7E-Mx>kKIfVXNGXlEtdkDkl=Ib}aJ7*7&=ghog9{j(}gS_F{)DhQ7d+Ch|lLJkx9E>S)q0tb}CJB-4Yk^0G``lj*0j@{LS>km+?1gy>Sx0+6R>kN8c5Z2yp8KL4)f%k=F1 zrR%lU^~tpmAl*Q~mzaIwbCIt>yAGM{9!~~qWsU*gr$|y=O}H)Gu`kxWqhoLEe^6kP znoVn81pBtrn3JEho)?9rKGXge^pEEdKZn*m0LN-@SRu^RcS0DVu#S5jE((QX03*|M zPpBJ=w}2Vqjegv@aokA8nVKDTyj3cY*>^K0@W|uVM;kkf=|jsavM?4bCi78wIXFwY z@@o7Xtm@iVf~(W!D+m1iXCI+Pqs5++v0IGx-QQtXIrBG?dHY&&WoB!3gZvyGoJCrU zzs(Z8B>;_%-li;N5l6Rdgq*X~OHQ=Ki!`zZo{ E0vr8OE&u=k literal 0 HcmV?d00001 From a298668b99d0c8ac3b2d801e5ddce936062f0e9b Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Fri, 1 May 2020 17:23:28 -0400 Subject: [PATCH 1368/1463] mb/asus/p2b*: Get rid of power button device These boards have the same issue as [27272]: Currently, two power buttons are exposed in ACPI, and detected by the operating system. > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. > > [i440BX] mainboards implemented the generic hardware power button in > a broken manner i.e. power button object with HID PNP0C0C is added to > ACPI however none of the boards set POWER_BUTTON flag in FADT. This > results in Linux kernel adding both fixed hardware power button as > well as generic hardware power button to the list of devices present > on the system. Though this is mostly harmless, it is logically > incorrect and can confuse any userspace utilities scanning the ACPI > devices. Hardware tests on the P2B-LS shows the generic hardware power button is not working anyway - with FADT power button flag set, the board could not power off with the button. This change removes the generic hardware power button from all P2B mainboards and relies completely on the fixed hardware power button. TEST=Booted on P2B-LS, Linux detects only fixed hardware power button, button still powers off. [27272]: https://review.coreboot.org/27272 Change-Id: I0f5b7aaf32366360de3cce58cd742651a2bb46ba Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40007 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/p2b/dsdt.asl | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 5bc5d72db9..e119871ed6 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -97,15 +97,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) /* Root of the bus hierarchy */ Scope (\_SB) { - Device (PWRB) - { - /* Power Button Device */ - Name (_HID, EisaId ("PNP0C0C")) - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } #include PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) From 6cc1e9e81efe794eb4ef0d0586fa7b8351577aba Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 19:13:47 -0700 Subject: [PATCH 1369/1463] acpi: Move ACPI table support out of arch/x86 (1/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 1/5 which moves .c files from arch/x86 to acpi/. The only acpi files that are still retained under arch/x86 are: a. acpi_s3.c: This doesn't really deal with ACPI tables. Also, there are some assumptions in there about SMM which will have to be resolved if this file needs to be moved to common code. b. acpi_bert_storage.c/bert_storage.h: This file is currently written specifically with x86 in mind. So, not moving the file for now. Motivation for this change: Not all stages on Picasso SoC are targeted for the same architecture. For example, verstage (if runs before bootblock) will be targeted for non-x86. This makes it difficult to add device tree to verstage which would be required to get to SoC configs from the tree. This is because the device tree on x86 platforms currently contains a lot of devices that require ACPI related enums and structs (like acpi_gpio, acpi_pld, acpi_dp and so on). Hence, this change removes all ACPI table support out of arch/x86. BUG=b:155428745 Change-Id: Icc6b793c52c86483a8c52e0555619e36869a869e Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40930 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/acpi/Makefile.inc | 13 ++++++++++++- src/{arch/x86 => acpi}/acpi.c | 0 src/{arch/x86 => acpi}/acpi_device.c | 0 src/{arch/x86 => acpi}/acpi_pld.c | 0 src/{arch/x86 => acpi}/acpigen.c | 0 src/{arch/x86 => acpi}/acpigen_dsm.c | 0 src/{arch/x86 => acpi}/acpigen_ps2_keybd.c | 0 src/arch/x86/Makefile.inc | 6 ------ 8 files changed, 12 insertions(+), 7 deletions(-) rename src/{arch/x86 => acpi}/acpi.c (100%) rename src/{arch/x86 => acpi}/acpi_device.c (100%) rename src/{arch/x86 => acpi}/acpi_pld.c (100%) rename src/{arch/x86 => acpi}/acpigen.c (100%) rename src/{arch/x86 => acpi}/acpigen_dsm.c (100%) rename src/{arch/x86 => acpi}/acpigen_ps2_keybd.c (100%) diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index e99110ec24..068c592db7 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -1,4 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sata.c +ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) + +ramstage-y += acpi.c +ramstage-y += acpi_device.c +ramstage-y += acpi_pld.c +ramstage-y += acpigen.c +ramstage-y += acpigen_dsm.c +ramstage-y += acpigen_ps2_keybd.c + +ramstage-y += sata.c + +endif # CONFIG_GENERATE_ACPI_TABLES diff --git a/src/arch/x86/acpi.c b/src/acpi/acpi.c similarity index 100% rename from src/arch/x86/acpi.c rename to src/acpi/acpi.c diff --git a/src/arch/x86/acpi_device.c b/src/acpi/acpi_device.c similarity index 100% rename from src/arch/x86/acpi_device.c rename to src/acpi/acpi_device.c diff --git a/src/arch/x86/acpi_pld.c b/src/acpi/acpi_pld.c similarity index 100% rename from src/arch/x86/acpi_pld.c rename to src/acpi/acpi_pld.c diff --git a/src/arch/x86/acpigen.c b/src/acpi/acpigen.c similarity index 100% rename from src/arch/x86/acpigen.c rename to src/acpi/acpigen.c diff --git a/src/arch/x86/acpigen_dsm.c b/src/acpi/acpigen_dsm.c similarity index 100% rename from src/arch/x86/acpigen_dsm.c rename to src/acpi/acpigen_dsm.c diff --git a/src/arch/x86/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c similarity index 100% rename from src/arch/x86/acpigen_ps2_keybd.c rename to src/acpi/acpigen_ps2_keybd.c diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2d007094c7..aa1f5fef5f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -230,12 +230,6 @@ $(CONFIG_CBFS_PREFIX)/postcar-compression := none ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_ps2_keybd.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += c_start.S From e0844636aca974449c7257e846ec816db683d0b9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 2 May 2020 10:23:37 -0700 Subject: [PATCH 1370/1463] acpi: Move ACPI table support out of arch/x86 (2/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 2/5 which moves the contents of arch/x86/include/arch/acpi*.h files into include/acpi/acpi*.h and updates the arch header files to include acpi header files. These are just temporary placeholders and will be removed later in the series. BUG=b:155428745 Change-Id: I9acb787770b7f09fd2cbd99cb8d0a6499b9c64b3 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40937 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/arch/x86/include/arch/acpi.h | 1050 +--------------- src/arch/x86/include/arch/acpi_device.h | 511 +------- src/arch/x86/include/arch/acpi_ivrs.h | 141 +-- src/arch/x86/include/arch/acpi_pld.h | 117 +- src/arch/x86/include/arch/acpigen.h | 488 +------- src/arch/x86/include/arch/acpigen_dsm.h | 13 +- src/arch/x86/include/arch/acpigen_ps2_keybd.h | 36 +- src/include/acpi/acpi.h | 1052 +++++++++++++++++ src/include/acpi/acpi_device.h | 513 ++++++++ src/include/acpi/acpi_ivrs.h | 143 +++ src/include/acpi/acpi_pld.h | 119 ++ src/include/acpi/acpigen.h | 490 ++++++++ src/include/acpi/acpigen_dsm.h | 15 + src/include/acpi/acpigen_ps2_keybd.h | 41 + 14 files changed, 2380 insertions(+), 2349 deletions(-) create mode 100644 src/include/acpi/acpi.h create mode 100644 src/include/acpi/acpi_device.h create mode 100644 src/include/acpi/acpi_ivrs.h create mode 100644 src/include/acpi/acpi_pld.h create mode 100644 src/include/acpi/acpigen.h create mode 100644 src/include/acpi/acpigen_dsm.h create mode 100644 src/include/acpi/acpigen_ps2_keybd.h diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 5314d78197..35cf6c6b06 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -1,1052 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* - * coreboot ACPI support - headers and defines. - */ - -#ifndef __ASM_ACPI_H -#define __ASM_ACPI_H - -/* - * The type and enable fields are common in ACPI, but the - * values themselves are hardware implementation defined. - */ -#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) - #define SLP_EN (1 << 13) - #define SLP_TYP_SHIFT 10 - #define SLP_TYP (7 << SLP_TYP_SHIFT) - #define SLP_TYP_S0 0 - #define SLP_TYP_S1 1 - #define SLP_TYP_S3 5 - #define SLP_TYP_S4 6 - #define SLP_TYP_S5 7 -#elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) - #define SLP_EN (1 << 13) - #define SLP_TYP_SHIFT 10 - #define SLP_TYP (7 << SLP_TYP_SHIFT) - #define SLP_TYP_S0 0 - #define SLP_TYP_S1 1 - #define SLP_TYP_S3 3 - #define SLP_TYP_S4 4 - #define SLP_TYP_S5 5 -#endif - -#define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ -#define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#include -#include -#include -#include -#include - -#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ -#define ASLC "CORE" /* Must be exactly 4 bytes long! */ - -/* - * The assigned ACPI ID for the coreboot project is 'BOOT' - * http://www.uefi.org/acpi_id_list - */ -#define COREBOOT_ACPI_ID "BOOT" /* ACPI ID for coreboot HIDs */ - -/* List of ACPI HID that use the coreboot ACPI ID */ -enum coreboot_acpi_ids { - COREBOOT_ACPI_ID_CBTABLE = 0x0000, /* BOOT0000 */ - COREBOOT_ACPI_ID_MAX = 0xFFFF, /* BOOTFFFF */ -}; - -enum acpi_tables { - /* Tables defined by ACPI and used by coreboot */ - BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, - RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, - /* Additional proprietary tables used by coreboot */ - VFCT, NHLT, SPMI -}; - -/* RSDP (Root System Description Pointer) */ -typedef struct acpi_rsdp { - char signature[8]; /* RSDP signature */ - u8 checksum; /* Checksum of the first 20 bytes */ - char oem_id[6]; /* OEM ID */ - u8 revision; /* RSDP revision */ - u32 rsdt_address; /* Physical address of RSDT (32 bits) */ - u32 length; /* Total RSDP length (incl. extended part) */ - u64 xsdt_address; /* Physical address of XSDT (64 bits) */ - u8 ext_checksum; /* Checksum of the whole table */ - u8 reserved[3]; -} __packed acpi_rsdp_t; - -/* GAS (Generic Address Structure) */ -typedef struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size since ACPI 2.0c */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ -} __packed acpi_addr_t; - -#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ -#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ -#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ -#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ -#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ -#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ -#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ -#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ -#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ -#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ -#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ -#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ -/* 0x80-0xbf: Reserved */ -/* 0xc0-0xff: OEM defined */ - -/* Access size definitions for Generic address structure */ -#define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */ -#define ACPI_ACCESS_SIZE_BYTE_ACCESS 1 -#define ACPI_ACCESS_SIZE_WORD_ACCESS 2 -#define ACPI_ACCESS_SIZE_DWORD_ACCESS 3 -#define ACPI_ACCESS_SIZE_QWORD_ACCESS 4 - -/* Common ACPI HIDs */ -#define ACPI_HID_FDC "PNP0700" -#define ACPI_HID_KEYBOARD "PNP0303" -#define ACPI_HID_MOUSE "PNP0F03" -#define ACPI_HID_COM "PNP0501" -#define ACPI_HID_LPT "PNP0400" -#define ACPI_HID_PNP "PNP0C02" -#define ACPI_HID_CONTAINER "PNP0A05" - -/* Generic ACPI header, provided by (almost) all tables */ -typedef struct acpi_table_header { - char signature[4]; /* ACPI signature (4 ASCII characters) */ - u32 length; /* Table length in bytes (incl. header) */ - u8 revision; /* Table version (not ACPI version!) */ - u8 checksum; /* To make sum of entire table == 0 */ - char oem_id[6]; /* OEM identification */ - char oem_table_id[8]; /* OEM table identification */ - u32 oem_revision; /* OEM revision number */ - char asl_compiler_id[4]; /* ASL compiler vendor ID */ - u32 asl_compiler_revision; /* ASL compiler revision number */ -} __packed acpi_header_t; - -/* A maximum number of 32 ACPI tables ought to be enough for now. */ -#define MAX_ACPI_TABLES 32 - -/* RSDT (Root System Description Table) */ -typedef struct acpi_rsdt { - acpi_header_t header; - u32 entry[MAX_ACPI_TABLES]; -} __packed acpi_rsdt_t; - -/* XSDT (Extended System Description Table) */ -typedef struct acpi_xsdt { - acpi_header_t header; - u64 entry[MAX_ACPI_TABLES]; -} __packed acpi_xsdt_t; - -/* HPET timers */ -typedef struct acpi_hpet { - acpi_header_t header; - u32 id; - acpi_addr_t addr; - u8 number; - u16 min_tick; - u8 attributes; -} __packed acpi_hpet_t; - -/* MCFG (PCI Express MMIO config space BAR description table) */ -typedef struct acpi_mcfg { - acpi_header_t header; - u8 reserved[8]; -} __packed acpi_mcfg_t; - -typedef struct acpi_tcpa { - acpi_header_t header; - u16 platform_class; - u32 laml; - u64 lasa; -} __packed acpi_tcpa_t; - -typedef struct acpi_tpm2 { - acpi_header_t header; - u16 platform_class; - u8 reserved[2]; - u64 control_area; - u32 start_method; - u8 msp[12]; - u32 laml; - u64 lasa; -} __packed acpi_tpm2_t; - -typedef struct acpi_mcfg_mmconfig { - u32 base_address; - u32 base_reserved; - u16 pci_segment_group_number; - u8 start_bus_number; - u8 end_bus_number; - u8 reserved[4]; -} __packed acpi_mcfg_mmconfig_t; - -/* SRAT (System Resource Affinity Table) */ -typedef struct acpi_srat { - acpi_header_t header; - u32 resv; - u64 resv1; - /* Followed by static resource allocation structure[n] */ -} __packed acpi_srat_t; - -/* SRAT: Processor Local APIC/SAPIC Affinity Structure */ -typedef struct acpi_srat_lapic { - u8 type; /* Type (0) */ - u8 length; /* Length in bytes (16) */ - u8 proximity_domain_7_0; /* Proximity domain bits[7:0] */ - u8 apic_id; /* Local APIC ID */ - u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */ - u8 local_sapic_eid; /* Local SAPIC EID */ - u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */ - u32 clock_domain; /* _CDM Clock Domain */ -} __packed acpi_srat_lapic_t; - -/* SRAT: Memory Affinity Structure */ -typedef struct acpi_srat_mem { - u8 type; /* Type (1) */ - u8 length; /* Length in bytes (40) */ - u32 proximity_domain; /* Proximity domain */ - u16 resv; - u32 base_address_low; /* Mem range base address, low */ - u32 base_address_high; /* Mem range base address, high */ - u32 length_low; /* Mem range length, low */ - u32 length_high; /* Mem range length, high */ - u32 resv1; - u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2, - * other bits reserved to 0 - */ - u32 resv2[2]; -} __packed acpi_srat_mem_t; - -/* SLIT (System Locality Distance Information Table) */ -typedef struct acpi_slit { - acpi_header_t header; - /* Followed by static resource allocation 8+byte[num*num] */ -} __packed acpi_slit_t; - -/* MADT (Multiple APIC Description Table) */ -typedef struct acpi_madt { - acpi_header_t header; - u32 lapic_addr; /* Local APIC address */ - u32 flags; /* Multiple APIC flags */ -} __packed acpi_madt_t; - -/* VFCT image header */ -typedef struct acpi_vfct_image_hdr { - u32 PCIBus; - u32 PCIDevice; - u32 PCIFunction; - u16 VendorID; - u16 DeviceID; - u16 SSVID; - u16 SSID; - u32 Revision; - u32 ImageLength; - u8 VbiosContent; // dummy - copy VBIOS here -} __packed acpi_vfct_image_hdr_t; - -/* VFCT (VBIOS Fetch Table) */ -typedef struct acpi_vfct { - acpi_header_t header; - u8 TableUUID[16]; - u32 VBIOSImageOffset; - u32 Lib1ImageOffset; - u32 Reserved[4]; - acpi_vfct_image_hdr_t image_hdr; -} __packed acpi_vfct_t; - -typedef struct acpi_ivrs_info { -} __packed acpi_ivrs_info_t; - -/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 10h */ -typedef struct acpi_ivrs_ivhd { - uint8_t type; - uint8_t flags; - uint16_t length; - uint16_t device_id; - uint16_t capability_offset; - uint32_t iommu_base_low; - uint32_t iommu_base_high; - uint16_t pci_segment_group; - uint16_t iommu_info; - uint32_t iommu_feature_info; - uint8_t entry[0]; -} __packed acpi_ivrs_ivhd_t; - -/* IVRS (I/O Virtualization Reporting Structure) Type 10h */ -typedef struct acpi_ivrs { - acpi_header_t header; - uint32_t iv_info; - uint32_t reserved[2]; - struct acpi_ivrs_ivhd ivhd; -} __packed acpi_ivrs_t; - -/* IVHD Type 11h IOMMU Attributes */ -typedef struct ivhd11_iommu_attr { - uint32_t reserved1 : 13; - uint32_t perf_counters : 4; - uint32_t perf_counter_banks : 6; - uint32_t msi_num_ppr : 5; - uint32_t reserved2 : 4; -} __packed ivhd11_iommu_attr_t; - -/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 11h */ -typedef struct acpi_ivrs_ivhd_11 { - uint8_t type; - uint8_t flags; - uint16_t length; - uint16_t device_id; - uint16_t capability_offset; - uint32_t iommu_base_low; - uint32_t iommu_base_high; - uint16_t pci_segment_group; - uint16_t iommu_info; - struct ivhd11_iommu_attr iommu_attributes; - uint32_t efr_reg_image_low; - uint32_t efr_reg_image_high; - uint32_t reserved[2]; - uint8_t entry[0]; -} __packed acpi_ivrs_ivhd11_t; - -enum dev_scope_type { - SCOPE_PCI_ENDPOINT = 1, - SCOPE_PCI_SUB = 2, - SCOPE_IOAPIC = 3, - SCOPE_MSI_HPET = 4, - SCOPE_ACPI_NAMESPACE_DEVICE = 5 -}; - -typedef struct dev_scope { - u8 type; - u8 length; - u8 reserved[2]; - u8 enumeration; - u8 start_bus; - struct { - u8 dev; - u8 fn; - } __packed path[0]; -} __packed dev_scope_t; - -enum dmar_type { - DMAR_DRHD = 0, - DMAR_RMRR = 1, - DMAR_ATSR = 2, - DMAR_RHSA = 3, - DMAR_ANDD = 4 -}; - -enum { - DRHD_INCLUDE_PCI_ALL = 1 -}; - -enum dmar_flags { - DMAR_INTR_REMAP = 1 << 0, - DMAR_X2APIC_OPT_OUT = 1 << 1, - DMA_CTRL_PLATFORM_OPT_IN_FLAG = 1 << 2, -}; - -typedef struct dmar_entry { - u16 type; - u16 length; - u8 flags; - u8 reserved; - u16 segment; - u64 bar; -} __packed dmar_entry_t; - -typedef struct dmar_rmrr_entry { - u16 type; - u16 length; - u16 reserved; - u16 segment; - u64 bar; - u64 limit; -} __packed dmar_rmrr_entry_t; - -typedef struct dmar_atsr_entry { - u16 type; - u16 length; - u8 flags; - u8 reserved; - u16 segment; -} __packed dmar_atsr_entry_t; - -typedef struct dmar_rhsa_entry { - u16 type; - u16 length; - u32 reserved; - u64 base_address; - u32 proximity_domain; -} __packed dmar_rhsa_entry_t; - -typedef struct dmar_andd_entry { - u16 type; - u16 length; - u8 reserved[3]; - u8 device_number; - u8 device_name[]; -} __packed dmar_andd_entry_t; - -/* DMAR (DMA Remapping Reporting Structure) */ -typedef struct acpi_dmar { - acpi_header_t header; - u8 host_address_width; - u8 flags; - u8 reserved[10]; - dmar_entry_t structure[0]; -} __packed acpi_dmar_t; - -/* MADT: APIC Structure Types */ -enum acpi_apic_types { - LOCAL_APIC, /* Processor local APIC */ - IO_APIC, /* I/O APIC */ - IRQ_SOURCE_OVERRIDE, /* Interrupt source override */ - NMI_TYPE, /* NMI source */ - LOCAL_APIC_NMI, /* Local APIC NMI */ - LAPIC_ADDRESS_OVERRIDE, /* Local APIC address override */ - IO_SAPIC, /* I/O SAPIC */ - LOCAL_SAPIC, /* Local SAPIC */ - PLATFORM_IRQ_SOURCES, /* Platform interrupt sources */ - LOCAL_X2APIC, /* Processor local x2APIC */ - LOCAL_X2APIC_NMI, /* Local x2APIC NMI */ - GICC, /* GIC CPU Interface */ - GICD, /* GIC Distributor */ - GIC_MSI_FRAME, /* GIC MSI Frame */ - GICR, /* GIC Redistributor */ - GIC_ITS, /* Interrupt Translation Service */ - /* 0x10-0x7f: Reserved */ - /* 0x80-0xff: Reserved for OEM use */ -}; - -/* MADT: Processor Local APIC Structure */ -typedef struct acpi_madt_lapic { - u8 type; /* Type (0) */ - u8 length; /* Length in bytes (8) */ - u8 processor_id; /* ACPI processor ID */ - u8 apic_id; /* Local APIC ID */ - u32 flags; /* Local APIC flags */ -} __packed acpi_madt_lapic_t; - -/* MADT: Local APIC NMI Structure */ -typedef struct acpi_madt_lapic_nmi { - u8 type; /* Type (4) */ - u8 length; /* Length in bytes (6) */ - u8 processor_id; /* ACPI processor ID */ - u16 flags; /* MPS INTI flags */ - u8 lint; /* Local APIC LINT# */ -} __packed acpi_madt_lapic_nmi_t; - -/* MADT: I/O APIC Structure */ -typedef struct acpi_madt_ioapic { - u8 type; /* Type (1) */ - u8 length; /* Length in bytes (12) */ - u8 ioapic_id; /* I/O APIC ID */ - u8 reserved; - u32 ioapic_addr; /* I/O APIC address */ - u32 gsi_base; /* Global system interrupt base */ -} __packed acpi_madt_ioapic_t; - -/* MADT: Interrupt Source Override Structure */ -typedef struct acpi_madt_irqoverride { - u8 type; /* Type (2) */ - u8 length; /* Length in bytes (10) */ - u8 bus; /* ISA (0) */ - u8 source; /* Bus-relative int. source (IRQ) */ - u32 gsirq; /* Global system interrupt */ - u16 flags; /* MPS INTI flags */ -} __packed acpi_madt_irqoverride_t; - -/* MADT: Processor Local x2APIC Structure */ -typedef struct acpi_madt_lx2apic { - u8 type; /* Type (9) */ - u8 length; /* Length in bytes (16) */ - u16 reserved; - u32 x2apic_id; /* Local x2APIC ID */ - u32 flags; /* Same as Local APIC flags */ - u32 processor_id; /* ACPI processor ID */ -} __packed acpi_madt_lx2apic_t; - -/* MADT: Processor Local x2APIC NMI Structure */ -typedef struct acpi_madt_lx2apic_nmi { - u8 type; /* Type (10) */ - u8 length; /* Length in bytes (12) */ - u16 flags; /* Same as MPS INTI flags */ - u32 processor_id; /* ACPI processor ID */ - u8 lint; /* Local APIC LINT# */ - u8 reserved[3]; -} __packed acpi_madt_lx2apic_nmi_t; - -#define ACPI_DBG2_PORT_SERIAL 0x8000 -#define ACPI_DBG2_PORT_SERIAL_16550 0x0000 -#define ACPI_DBG2_PORT_SERIAL_16550_DBGP 0x0001 -#define ACPI_DBG2_PORT_SERIAL_ARM_PL011 0x0003 -#define ACPI_DBG2_PORT_SERIAL_ARM_SBSA 0x000e -#define ACPI_DBG2_PORT_SERIAL_ARM_DDC 0x000f -#define ACPI_DBG2_PORT_SERIAL_BCM2835 0x0010 -#define ACPI_DBG2_PORT_IEEE1394 0x8001 -#define ACPI_DBG2_PORT_IEEE1394_STANDARD 0x0000 -#define ACPI_DBG2_PORT_USB 0x8002 -#define ACPI_DBG2_PORT_USB_XHCI 0x0000 -#define ACPI_DBG2_PORT_USB_EHCI 0x0001 -#define ACPI_DBG2_PORT_NET 0x8003 - -/* DBG2: Microsoft Debug Port Table 2 header */ -typedef struct acpi_dbg2_header { - acpi_header_t header; - uint32_t devices_offset; - uint32_t devices_count; -} __attribute__((packed)) acpi_dbg2_header_t; - -/* DBG2: Microsoft Debug Port Table 2 device entry */ -typedef struct acpi_dbg2_device { - uint8_t revision; - uint16_t length; - uint8_t address_count; - uint16_t namespace_string_length; - uint16_t namespace_string_offset; - uint16_t oem_data_length; - uint16_t oem_data_offset; - uint16_t port_type; - uint16_t port_subtype; - uint8_t reserved[2]; - uint16_t base_address_offset; - uint16_t address_size_offset; -} __attribute__((packed)) acpi_dbg2_device_t; - -/* FADT (Fixed ACPI Description Table) */ -typedef struct acpi_fadt { - acpi_header_t header; - u32 firmware_ctrl; - u32 dsdt; - u8 reserved; /* Should be 0 */ - u8 preferred_pm_profile; - u16 sci_int; - u32 smi_cmd; - u8 acpi_enable; - u8 acpi_disable; - u8 s4bios_req; - u8 pstate_cnt; - u32 pm1a_evt_blk; - u32 pm1b_evt_blk; - u32 pm1a_cnt_blk; - u32 pm1b_cnt_blk; - u32 pm2_cnt_blk; - u32 pm_tmr_blk; - u32 gpe0_blk; - u32 gpe1_blk; - u8 pm1_evt_len; - u8 pm1_cnt_len; - u8 pm2_cnt_len; - u8 pm_tmr_len; - u8 gpe0_blk_len; - u8 gpe1_blk_len; - u8 gpe1_base; - u8 cst_cnt; - u16 p_lvl2_lat; - u16 p_lvl3_lat; - u16 flush_size; - u16 flush_stride; - u8 duty_offset; - u8 duty_width; - u8 day_alrm; - u8 mon_alrm; - u8 century; - u16 iapc_boot_arch; - u8 res2; - u32 flags; - acpi_addr_t reset_reg; - u8 reset_value; - u16 ARM_boot_arch; /* Revision 6 only, Revision 5: Must be zero */ - u8 FADT_MinorVersion; /* Revision 6 only, Revision 5: Must be zero */ - u32 x_firmware_ctl_l; - u32 x_firmware_ctl_h; - u32 x_dsdt_l; - u32 x_dsdt_h; - acpi_addr_t x_pm1a_evt_blk; - acpi_addr_t x_pm1b_evt_blk; - acpi_addr_t x_pm1a_cnt_blk; - acpi_addr_t x_pm1b_cnt_blk; - acpi_addr_t x_pm2_cnt_blk; - acpi_addr_t x_pm_tmr_blk; - acpi_addr_t x_gpe0_blk; - acpi_addr_t x_gpe1_blk; - /* Revision 5 */ - acpi_addr_t sleep_control_reg; - acpi_addr_t sleep_status_reg; - /* Revision 6 */ - u64 hypervisor_vendor_identity; -} __packed acpi_fadt_t; - -/* FADT TABLE Revision values */ -#define ACPI_FADT_REV_ACPI_1_0 1 -#define ACPI_FADT_REV_ACPI_2_0 3 -#define ACPI_FADT_REV_ACPI_3_0 4 -#define ACPI_FADT_REV_ACPI_4_0 4 -#define ACPI_FADT_REV_ACPI_5_0 5 -#define ACPI_FADT_REV_ACPI_6_0 6 - -/* Flags for p_lvl2_lat and p_lvl3_lat */ -#define ACPI_FADT_C2_NOT_SUPPORTED 101 -#define ACPI_FADT_C3_NOT_SUPPORTED 1001 - -/* FADT Feature Flags */ -#define ACPI_FADT_WBINVD (1 << 0) -#define ACPI_FADT_WBINVD_FLUSH (1 << 1) -#define ACPI_FADT_C1_SUPPORTED (1 << 2) -#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) -#define ACPI_FADT_POWER_BUTTON (1 << 4) -#define ACPI_FADT_SLEEP_BUTTON (1 << 5) -#define ACPI_FADT_FIXED_RTC (1 << 6) -#define ACPI_FADT_S4_RTC_WAKE (1 << 7) -#define ACPI_FADT_32BIT_TIMER (1 << 8) -#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) -#define ACPI_FADT_RESET_REGISTER (1 << 10) -#define ACPI_FADT_SEALED_CASE (1 << 11) -#define ACPI_FADT_HEADLESS (1 << 12) -#define ACPI_FADT_SLEEP_TYPE (1 << 13) -#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) -#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) -#define ACPI_FADT_S4_RTC_VALID (1 << 16) -#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) -#define ACPI_FADT_APIC_CLUSTER (1 << 18) -#define ACPI_FADT_APIC_PHYSICAL (1 << 19) -/* Bits 20-31: reserved ACPI 3.0 & 4.0 */ -#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) -#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) -/* bits 22-31: reserved since ACPI 5.0 */ - -/* FADT Boot Architecture Flags */ -#define ACPI_FADT_LEGACY_DEVICES (1 << 0) -#define ACPI_FADT_8042 (1 << 1) -#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) -#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) -#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) -#define ACPI_FADT_NO_CMOS_RTC (1 << 5) -#define ACPI_FADT_LEGACY_FREE 0x00 /* No legacy devices (including 8042) */ - -/* FADT ARM Boot Architecture Flags */ -#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) -#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) -/* bits 2-16: reserved since ACPI 5.1 */ - -/* FADT Preferred Power Management Profile */ -enum acpi_preferred_pm_profiles { - PM_UNSPECIFIED = 0, - PM_DESKTOP = 1, - PM_MOBILE = 2, - PM_WORKSTATION = 3, - PM_ENTERPRISE_SERVER = 4, - PM_SOHO_SERVER = 5, - PM_APPLIANCE_PC = 6, - PM_PERFORMANCE_SERVER = 7, - PM_TABLET = 8, /* ACPI 5.0 & greater */ -}; - -/* FACS (Firmware ACPI Control Structure) */ -typedef struct acpi_facs { - char signature[4]; /* "FACS" */ - u32 length; /* Length in bytes (>= 64) */ - u32 hardware_signature; /* Hardware signature */ - u32 firmware_waking_vector; /* Firmware waking vector */ - u32 global_lock; /* Global lock */ - u32 flags; /* FACS flags */ - u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ - u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* FACS version */ - u8 resv1[3]; /* This value is 0 */ - u32 ospm_flags; /* 64BIT_WAKE_F */ - u8 resv2[24]; /* This value is 0 */ -} __packed acpi_facs_t; - -/* FACS flags */ -#define ACPI_FACS_S4BIOS_F (1 << 0) -#define ACPI_FACS_64BIT_WAKE_F (1 << 1) -/* Bits 31..2: reserved */ - -/* ECDT (Embedded Controller Boot Resources Table) */ -typedef struct acpi_ecdt { - acpi_header_t header; - acpi_addr_t ec_control; /* EC control register */ - acpi_addr_t ec_data; /* EC data register */ - u32 uid; /* UID */ - u8 gpe_bit; /* GPE bit */ - u8 ec_id[]; /* EC ID */ -} __packed acpi_ecdt_t; - -/* HEST (Hardware Error Source Table) */ -typedef struct acpi_hest { - acpi_header_t header; - u32 error_source_count; - /* error_source_struct(s) */ -} __packed acpi_hest_t; - -/* Error Source Descriptors */ -typedef struct acpi_hest_esd { - u16 type; - u16 source_id; - u16 resv; - u8 flags; - u8 enabled; - u32 prealloc_erecords; /* The number of error records to - * pre-allocate for this error source. - */ - u32 max_section_per_record; -} __packed acpi_hest_esd_t; - -/* Hardware Error Notification */ -typedef struct acpi_hest_hen { - u8 type; - u8 length; - u16 conf_we; /* Configuration Write Enable */ - u32 poll_interval; - u32 vector; - u32 sw2poll_threshold_val; - u32 sw2poll_threshold_win; - u32 error_threshold_val; - u32 error_threshold_win; -} __packed acpi_hest_hen_t; - -/* BERT (Boot Error Record Table) */ -typedef struct acpi_bert { - acpi_header_t header; - u32 region_length; - u64 error_region; -} __packed acpi_bert_t; - -/* Generic Error Data Entry */ -typedef struct acpi_hest_generic_data { - guid_t section_type; - u32 error_severity; - u16 revision; - u8 validation_bits; - u8 flags; - u32 data_length; - guid_t fru_id; - u8 fru_text[20]; - /* error data */ -} __packed acpi_hest_generic_data_t; - -/* Generic Error Data Entry v300 */ -typedef struct acpi_hest_generic_data_v300 { - guid_t section_type; - u32 error_severity; - u16 revision; - u8 validation_bits; - u8 flags; /* see CPER Section Descriptor, Flags field */ - u32 data_length; - guid_t fru_id; - u8 fru_text[20]; - cper_timestamp_t timestamp; - /* error data */ -} __packed acpi_hest_generic_data_v300_t; -#define HEST_GENERIC_ENTRY_V300 0x300 - -/* Both Generic Error Status & Generic Error Data Entry, Error Severity field */ -#define ACPI_GENERROR_SEV_RECOVERABLE 0 -#define ACPI_GENERROR_SEV_FATAL 1 -#define ACPI_GENERROR_SEV_CORRECTED 2 -#define ACPI_GENERROR_SEV_NONE 3 - -/* Generic Error Data Entry, Validation Bits field */ -#define ACPI_GENERROR_VALID_FRUID BIT(0) -#define ACPI_GENERROR_VALID_FRUID_TEXT BIT(1) -#define ACPI_GENERROR_VALID_TIMESTAMP BIT(2) - -/* Generic Error Status Block */ -typedef struct acpi_generic_error_status { - u32 block_status; - u32 raw_data_offset; /* must follow any generic entries */ - u32 raw_data_length; - u32 data_length; /* generic data */ - u32 error_severity; - /* Generic Error Data structures, zero or more entries */ -} __packed acpi_generic_error_status_t; - -/* Generic Status Block, Block Status values */ -#define GENERIC_ERR_STS_UNCORRECTABLE_VALID BIT(0) -#define GENERIC_ERR_STS_CORRECTABLE_VALID BIT(1) -#define GENERIC_ERR_STS_MULT_UNCORRECTABLE BIT(2) -#define GENERIC_ERR_STS_MULT_CORRECTABLE BIT(3) -#define GENERIC_ERR_STS_ENTRY_COUNT_SHIFT 4 -#define GENERIC_ERR_STS_ENTRY_COUNT_MAX 0x3ff -#define GENERIC_ERR_STS_ENTRY_COUNT_MASK \ - (GENERIC_ERR_STS_ENTRY_COUNT_MAX \ - << GENERIC_ERR_STS_ENTRY_COUNT_SHIFT) - -typedef struct acpi_cstate { - u8 ctype; - u16 latency; - u32 power; - acpi_addr_t resource; -} __packed acpi_cstate_t; - -typedef struct acpi_tstate { - u32 percent; - u32 power; - u32 latency; - u32 control; - u32 status; -} __packed acpi_tstate_t; - -/* Port types for ACPI _UPC object */ -enum acpi_upc_type { - UPC_TYPE_A, - UPC_TYPE_MINI_AB, - UPC_TYPE_EXPRESSCARD, - UPC_TYPE_USB3_A, - UPC_TYPE_USB3_B, - UPC_TYPE_USB3_MICRO_B, - UPC_TYPE_USB3_MICRO_AB, - UPC_TYPE_USB3_POWER_B, - UPC_TYPE_C_USB2_ONLY, - UPC_TYPE_C_USB2_SS_SWITCH, - UPC_TYPE_C_USB2_SS, - UPC_TYPE_PROPRIETARY = 0xff, - /* - * The following types are not directly defined in the ACPI - * spec but are used by coreboot to identify a USB device type. - */ - UPC_TYPE_INTERNAL = 0xff, - UPC_TYPE_UNUSED, - UPC_TYPE_HUB -}; - -enum acpi_ipmi_interface_type { - IPMI_INTERFACE_RESERVED = 0, - IPMI_INTERFACE_KCS, - IPMI_INTERFACE_SMIC, - IPMI_INTERFACE_BT, - IPMI_INTERFACE_SSIF, -}; - -#define ACPI_IPMI_PCI_DEVICE_FLAG (1 << 0) -#define ACPI_IPMI_INT_TYPE_SCI (1 << 0) -#define ACPI_IPMI_INT_TYPE_APIC (1 << 1) - -/* ACPI IPMI 2.0 */ -struct acpi_spmi { - acpi_header_t header; - u8 interface_type; - u8 reserved; - u16 specification_revision; - u8 interrupt_type; - u8 gpe; - u8 reserved2; - u8 pci_device_flag; - - u32 global_system_interrupt; - acpi_addr_t base_address; - union { - struct { - u8 pci_segment_group; - u8 pci_bus; - u8 pci_device; - u8 pci_function; - }; - u8 uid[4]; - }; - u8 reserved3; -} __packed; - -unsigned long fw_cfg_acpi_tables(unsigned long start); - -/* These are implemented by the target port or north/southbridge. */ -unsigned long write_acpi_tables(unsigned long addr); -unsigned long acpi_fill_madt(unsigned long current); -unsigned long acpi_fill_mcfg(unsigned long current); -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); -void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); -void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length); -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); -#if CONFIG(COMMON_FADT) -void acpi_fill_fadt(acpi_fadt_t *fadt); -#endif - -void update_ssdt(void *ssdt); -void update_ssdtx(void *ssdtx, int i); - -/* These can be used by the target port. */ -u8 acpi_checksum(u8 *table, u32 length); - -void acpi_add_table(acpi_rsdp_t *rsdp, void *table); - -int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, - u32 gsi_base); -int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags); -int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint); -void acpi_create_madt(acpi_madt_t *madt); -unsigned long acpi_create_madt_lapics(unsigned long current); -unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, - u8 lint); -int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); -int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, - u16 flags, u8 lint); -int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); -int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, - u32 flags); -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); -unsigned long acpi_create_srat_lapics(unsigned long current); -void acpi_create_srat(acpi_srat_t *srat, - unsigned long (*acpi_fill_srat)(unsigned long current)); - -void acpi_create_slit(acpi_slit_t *slit, - unsigned long (*acpi_fill_slit)(unsigned long current)); - -void acpi_create_vfct(const struct device *device, - acpi_vfct_t *vfct, - unsigned long (*acpi_fill_vfct)(const struct device *device, - acpi_vfct_t *vfct_struct, - unsigned long current)); - -void acpi_create_ipmi(const struct device *device, - struct acpi_spmi *spmi, - const u16 ipmi_revision, - const acpi_addr_t *addr, - const enum acpi_ipmi_interface_type type, - const s8 gpe_interrupt, - const u32 apic_interrupt, - const u32 uid); - -void acpi_create_ivrs(acpi_ivrs_t *ivrs, - unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, - unsigned long current)); - -void acpi_create_hpet(acpi_hpet_t *hpet); -unsigned long acpi_write_hpet(const struct device *device, unsigned long start, - acpi_rsdp_t *rsdp); - -/* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(const struct device *device); - -void acpi_create_mcfg(acpi_mcfg_t *mcfg); - -void acpi_create_facs(acpi_facs_t *facs); - -void acpi_create_dbg2(acpi_dbg2_header_t *dbg2_header, - int port_type, int port_subtype, - acpi_addr_t *address, uint32_t address_size, - const char *device_path); - -unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, - const struct device *dev, uint8_t access_size); -void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, - unsigned long (*acpi_fill_dmar)(unsigned long)); -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u64 bar); -unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, - u64 bar, u64 limit); -unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, - u16 segment); -unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, - u32 proximity_domain); -unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, - const char *device_name); -void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); -void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current); -void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); -unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, - u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_ds_pci(unsigned long current, - u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, - u8 enumeration_id, - u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, - u8 enumeration_id, - u8 bus, u8 dev, u8 fn); -void acpi_write_hest(acpi_hest_t *hest, - unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)); - -unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, - acpi_hest_esd_t *esd, u16 type, void *data, u16 len); - -/* For ACPI S3 support. */ -void acpi_resume(void *wake_vec); -void mainboard_suspend_resume(void); -void *acpi_find_wakeup_vector(void); - -/* ACPI_Sn assignments are defined to always equal the sleep state numbers */ -enum { - ACPI_S0 = 0, - ACPI_S1 = 1, - ACPI_S2 = 2, - ACPI_S3 = 3, - ACPI_S4 = 4, - ACPI_S5 = 5, -}; - -#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ - || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) -/* Given the provided PM1 control register return the ACPI sleep type. */ -static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt) -{ - switch (((pm1_cnt) & SLP_TYP) >> SLP_TYP_SHIFT) { - case SLP_TYP_S0: return ACPI_S0; - case SLP_TYP_S1: return ACPI_S1; - case SLP_TYP_S3: return ACPI_S3; - case SLP_TYP_S4: return ACPI_S4; - case SLP_TYP_S5: return ACPI_S5; - } - return -1; -} -#endif - -/* Returns ACPI_Sx values. */ -int acpi_get_sleep_type(void); - -/* Read and clear GPE status */ -int acpi_get_gpe(int gpe); - -static inline int acpi_s3_resume_allowed(void) -{ - return CONFIG(HAVE_ACPI_RESUME); -} - -#if CONFIG(HAVE_ACPI_RESUME) - -#if ENV_ROMSTAGE_OR_BEFORE -static inline int acpi_is_wakeup_s3(void) -{ - return (acpi_get_sleep_type() == ACPI_S3); -} -#else -int acpi_is_wakeup(void); -int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_s4(void); -#endif - -#else -static inline int acpi_is_wakeup(void) { return 0; } -static inline int acpi_is_wakeup_s3(void) { return 0; } -static inline int acpi_is_wakeup_s4(void) { return 0; } -#endif - -static inline uintptr_t acpi_align_current(uintptr_t current) -{ - return ALIGN_UP(current, 16); -} - -/* ACPI table revisions should match the revision of the ACPI spec - * supported. This function keeps the table versions synced. This could - * be made into a weak function if there is ever a need to override the - * coreboot default ACPI spec version supported. */ -int get_acpi_table_revision(enum acpi_tables table); - -#endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMC__) - -#endif /* __ASM_ACPI_H */ +#include diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index bc71e0264d..5c3199e7b7 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -1,513 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef __ACPI_DEVICE_H -#define __ACPI_DEVICE_H - -#include -#include -#include - -enum acpi_dp_type { - ACPI_DP_TYPE_UNKNOWN, - ACPI_DP_TYPE_INTEGER, - ACPI_DP_TYPE_STRING, - ACPI_DP_TYPE_REFERENCE, - ACPI_DP_TYPE_TABLE, - ACPI_DP_TYPE_ARRAY, - ACPI_DP_TYPE_CHILD, -}; - -struct acpi_dp { - enum acpi_dp_type type; - const char *name; - struct acpi_dp *next; - union { - struct acpi_dp *child; - struct acpi_dp *array; - }; - union { - uint64_t integer; - const char *string; - }; -}; - -#define ACPI_DESCRIPTOR_LARGE (1 << 7) -#define ACPI_DESCRIPTOR_INTERRUPT (ACPI_DESCRIPTOR_LARGE | 9) -#define ACPI_DESCRIPTOR_GPIO (ACPI_DESCRIPTOR_LARGE | 12) -#define ACPI_DESCRIPTOR_SERIAL_BUS (ACPI_DESCRIPTOR_LARGE | 14) - -/* - * PRP0001 is a special DT namespace link device ID. It provides a means to use - * existing DT-compatible device identification in ACPI. When this _HID is used - * by an ACPI device, the ACPI subsystem in OS looks up "compatible" property in - * device object's _DSD and will use the value of that property to identify the - * corresponding device in analogy with the original DT device identification - * algorithm. - * More details can be found in Linux kernel documentation: - * Documentation/acpi/enumeration.txt - */ -#define ACPI_DT_NAMESPACE_HID "PRP0001" - -struct device; -const char *acpi_device_name(const struct device *dev); -const char *acpi_device_hid(const struct device *dev); -uint32_t acpi_device_uid(const struct device *dev); -const char *acpi_device_path(const struct device *dev); -const char *acpi_device_scope(const struct device *dev); -const char *acpi_device_path_join(const struct device *dev, const char *name); -int acpi_device_status(const struct device *dev); -void acpi_device_write_uid(const struct device *dev); - -/* - * ACPI Descriptor for extended Interrupt() - */ - -enum acpi_irq_mode { - ACPI_IRQ_EDGE_TRIGGERED, - ACPI_IRQ_LEVEL_TRIGGERED -}; - -enum acpi_irq_polarity { - ACPI_IRQ_ACTIVE_LOW, - ACPI_IRQ_ACTIVE_HIGH, - ACPI_IRQ_ACTIVE_BOTH -}; - -enum acpi_irq_shared { - ACPI_IRQ_EXCLUSIVE, - ACPI_IRQ_SHARED -}; - -enum acpi_irq_wake { - ACPI_IRQ_NO_WAKE, - ACPI_IRQ_WAKE -}; - -struct acpi_irq { - unsigned int pin; - enum acpi_irq_mode mode; - enum acpi_irq_polarity polarity; - enum acpi_irq_shared shared; - enum acpi_irq_wake wake; -}; - -#define ACPI_IRQ_CFG(_pin, _mode, _pol, _shared, _wake) { \ - .pin = (_pin), \ - .mode = (_mode), \ - .polarity = (_pol), \ - .shared = (_shared), \ - .wake = (_wake) } - -#define ACPI_IRQ_EDGE_LOW(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ - ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_NO_WAKE) - -#define ACPI_IRQ_EDGE_HIGH(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ - ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_NO_WAKE) - -#define ACPI_IRQ_LEVEL_LOW(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ - ACPI_IRQ_SHARED, ACPI_IRQ_NO_WAKE) - -#define ACPI_IRQ_LEVEL_HIGH(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ - ACPI_IRQ_SHARED, ACPI_IRQ_NO_WAKE) - -#define ACPI_IRQ_WAKE_EDGE_LOW(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ - ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_WAKE) - -#define ACPI_IRQ_WAKE_EDGE_HIGH(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ - ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_WAKE) - -#define ACPI_IRQ_WAKE_LEVEL_LOW(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ - ACPI_IRQ_SHARED, ACPI_IRQ_WAKE) - -#define ACPI_IRQ_WAKE_LEVEL_HIGH(x) \ - ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ - ACPI_IRQ_SHARED, ACPI_IRQ_WAKE) - -/* Write extended Interrupt() descriptor to SSDT AML output */ -void acpi_device_write_interrupt(const struct acpi_irq *irq); - -/* - * ACPI Descriptors for GpioIo() and GpioInterrupt() - */ - -enum acpi_gpio_type { - ACPI_GPIO_TYPE_INTERRUPT, - ACPI_GPIO_TYPE_IO -}; - -enum acpi_gpio_pull { - ACPI_GPIO_PULL_DEFAULT, - ACPI_GPIO_PULL_UP, - ACPI_GPIO_PULL_DOWN, - ACPI_GPIO_PULL_NONE -}; - -enum acpi_gpio_io_restrict { - ACPI_GPIO_IO_RESTRICT_NONE, - ACPI_GPIO_IO_RESTRICT_INPUT, - ACPI_GPIO_IO_RESTRICT_OUTPUT, - ACPI_GPIO_IO_RESTRICT_PRESERVE -}; - -enum acpi_gpio_polarity { - ACPI_GPIO_ACTIVE_HIGH = 0, - ACPI_GPIO_ACTIVE_LOW = 1, -}; - -#define ACPI_GPIO_REVISION_ID 1 -#define ACPI_GPIO_MAX_PINS 8 - -struct acpi_gpio { - int pin_count; - uint16_t pins[ACPI_GPIO_MAX_PINS]; - - enum acpi_gpio_type type; - enum acpi_gpio_pull pull; - const char *resource; - - /* GpioInt */ - uint16_t interrupt_debounce_timeout; /* 1/100 ms */ - struct acpi_irq irq; - - /* GpioIo */ - uint16_t output_drive_strength; /* 1/100 mA */ - int io_shared; - enum acpi_gpio_io_restrict io_restrict; - enum acpi_gpio_polarity polarity; -}; - -/* Basic output GPIO with default pull settings */ -#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) { \ - .type = ACPI_GPIO_TYPE_IO, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ - .polarity = ACPI_GPIO_ACTIVE_HIGH, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_IO, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ - .polarity = ACPI_GPIO_ACTIVE_LOW, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Basic input GPIO with default pull settings */ -#define ACPI_GPIO_INPUT_ACTIVE_HIGH(gpio) { \ - .type = ACPI_GPIO_TYPE_IO, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_INPUT, \ - .polarity = ACPI_GPIO_ACTIVE_HIGH, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -#define ACPI_GPIO_INPUT_ACTIVE_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_IO, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_INPUT, \ - .polarity = ACPI_GPIO_ACTIVE_LOW, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Edge Triggered Active High GPIO interrupt */ -#define ACPI_GPIO_IRQ_EDGE_HIGH(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Edge Triggered Active Low GPIO interrupt */ -#define ACPI_GPIO_IRQ_EDGE_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Edge Triggered Active Both GPIO interrupt */ -#define ACPI_GPIO_IRQ_EDGE_BOTH(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_BOTH, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Edge Triggered Active High GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_EDGE_HIGH_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Edge Triggered Active Low GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_EDGE_LOW_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Edge Triggered Active Both GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_EDGE_BOTH_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_BOTH, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Level Triggered Active High GPIO interrupt */ -#define ACPI_GPIO_IRQ_LEVEL_HIGH(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Level Triggered Active Low GPIO interrupt */ -#define ACPI_GPIO_IRQ_LEVEL_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Level Triggered Active High GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_LEVEL_HIGH_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Level Triggered Active Low GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } - -/* Write GpioIo() or GpioInt() descriptor to SSDT AML output */ -void acpi_device_write_gpio(const struct acpi_gpio *gpio); - -/* - * ACPI Descriptors for Serial Bus interfaces - */ - -#define ACPI_SERIAL_BUS_TYPE_I2C 1 -#define ACPI_SERIAL_BUS_TYPE_SPI 2 -#define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */ -#define ACPI_I2C_TYPE_SPECIFIC_REVISION_ID 1 -#define ACPI_SPI_SERIAL_BUS_REVISION_ID 1 -#define ACPI_SPI_TYPE_SPECIFIC_REVISION_ID 1 - -/* - * ACPI I2C Bus - */ - -struct acpi_i2c { - /* I2C Address */ - uint16_t address; - /* 7 or 10 bit Address Mode */ - enum i2c_address_mode mode_10bit; - /* I2C Bus Speed in Hz */ - enum i2c_speed speed; - /* Reference to I2C controller */ - const char *resource; -}; - -/* Write I2cSerialBus() descriptor to SSDT AML output */ -void acpi_device_write_i2c(const struct acpi_i2c *i2c); - -/* - * ACPI SPI Bus - */ - -struct acpi_spi { - /* Device selection */ - uint16_t device_select; - /* Device selection line is active high or low */ - enum spi_polarity device_select_polarity; - /* 3 or 4 wire SPI connection */ - enum spi_wire_mode wire_mode; - /* Connection speed in HZ */ - unsigned int speed; - /* Size in bits of smallest transfer unit */ - u8 data_bit_length; - /* Phase of clock pulse on which to capture data */ - enum spi_clock_phase clock_phase; - /* Indicate if clock is high or low during first phase */ - enum spi_polarity clock_polarity; - /* Reference to SPI controller */ - const char *resource; -}; - -/* Write SPI Bus descriptor to SSDT AML output */ -void acpi_device_write_spi(const struct acpi_spi *spi); - -/* GPIO/timing information for the power on/off sequences */ -struct acpi_power_res_params { - /* GPIO used to take device out of reset or to put it into reset. */ - struct acpi_gpio *reset_gpio; - /* Delay to be inserted after device is taken out of reset. - * (_ON method delay) - */ - unsigned int reset_delay_ms; - /* Delay to be inserted after device is put into reset. - * (_OFF method delay) - */ - unsigned int reset_off_delay_ms; - /* GPIO used to enable device. */ - struct acpi_gpio *enable_gpio; - /* Delay to be inserted after device is enabled. - * (_ON method delay) - */ - unsigned int enable_delay_ms; - /* Delay to be inserted after device is disabled. - * (_OFF method delay) - */ - unsigned int enable_off_delay_ms; - /* GPIO used to stop operation of device. */ - struct acpi_gpio *stop_gpio; - /* Delay to be inserted after disabling stop. - * (_ON method delay) - */ - unsigned int stop_delay_ms; - /* Delay to be inserted after enabling stop. - * (_OFF method delay) - */ - unsigned int stop_off_delay_ms; -}; - -/* - * Add a basic PowerResource block for a device that includes - * GPIOs to control enable, reset and stop operation of the device. Each - * GPIO is optional, but at least one must be provided. - * - * Reset - Put the device into / take the device out of reset. - * Enable - Enable / disable power to device. - * Stop - Stop / start operation of device. - */ -void acpi_device_add_power_res(const struct acpi_power_res_params *params); - -/* - * Writing Device Properties objects via _DSD - * - * http://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf - * http://uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.pdf - * - * The Device Property Hierarchy can be multiple levels deep with multiple - * children possible in each level. In order to support this flexibility - * the device property hierarchy must be built up before being written out. - * - * For example: - * - * // Child table with string and integer - * struct acpi_dp *child = acpi_dp_new_table("CHLD"); - * acpi_dp_add_string(child, "childstring", "CHILD"); - * acpi_dp_add_integer(child, "childint", 100); - * - * // _DSD table with integer and gpio and child pointer - * struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); - * acpi_dp_add_integer(dsd, "number1", 1); - * acpi_dp_add_gpio(dsd, "gpio", "\_SB.PCI0.GPIO", 0, 0, 1); - * acpi_dp_add_child(dsd, "child", child); - * - * // Write entries into SSDT and clean up resources - * acpi_dp_write(dsd); - * - * Name(_DSD, Package() { - * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") - * Package() { - * Package() { "gpio", Package() { \_SB.PCI0.GPIO, 0, 0, 0 } } - * Package() { "number1", 1 } - * } - * ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") - * Package() { - * Package() { "child", CHLD } - * } - * } - * Name(CHLD, Package() { - * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") - * Package() { - * Package() { "childstring", "CHILD" } - * Package() { "childint", 100 } - * } - * } - */ - -/* Start a new Device Property table with provided ACPI reference */ -struct acpi_dp *acpi_dp_new_table(const char *ref); - -/* Add integer Device Property */ -struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, - uint64_t value); - -/* Add string Device Property */ -struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, - const char *string); - -/* Add ACPI reference Device Property */ -struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, - const char *reference); - -/* Add an array of Device Properties */ -struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array); - -/* Add an array of integers Device Property */ -struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, - const uint64_t *array, int len); - -/* Add a GPIO binding Device Property */ -struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, - const char *ref, int index, int pin, - int active_low); - -/* Add a child table of Device Properties */ -struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, - struct acpi_dp *child); - -/* Add a list of Device Properties, returns the number of properties added */ -size_t acpi_dp_add_property_list(struct acpi_dp *dp, - const struct acpi_dp *property_list, - size_t property_count); - -/* Write Device Property hierarchy and clean up resources */ -void acpi_dp_write(struct acpi_dp *table); - -/* - * Helper function to write a PCI device with _ADR object defined. - * - * IMPORTANT: Scope of a device created in SSDT cannot be used to add ACPI nodes under that - * scope in DSDT. So, if there are any references to this PCI device scope required from static - * asl files, do not use this function and instead add the device to DSDT as well. - */ -void acpi_device_write_pci_dev(const struct device *dev); - -#endif +#include diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h index 83abfb63dc..032d253f08 100644 --- a/src/arch/x86/include/arch/acpi_ivrs.h +++ b/src/arch/x86/include/arch/acpi_ivrs.h @@ -1,143 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* - * AMD I/O Virtualization Technology (IOMMU) - * Specification 48882-Rev 2.62-February 2015 - * - * from http://www.uefi.org/acpi - * I/O Virtualization Reporting Structure (IVRS) - */ - -#ifndef __ARCH_ACPI_IVRS_H -#define __ARCH_ACPI_IVRS_H - -/* I/O Virtualization Reporting Structure (IVRS) */ -#define IVHD_BLOCK_TYPE_LEGACY__FIXED 0x10 -#define IVHD_BLOCK_TYPE_FULL__FIXED 0x11 -#define IVHD_BLOCK_TYPE_FULL__ACPI_HID 0x40 - -/* IVRS Revision Field */ -#define IVRS_FORMAT_FIXED 0x01 /* Type 10h & 11h only */ -#define IVRS_FORMAT_MIXED 0x02 /* Type 10h, 11h, & 40h */ - -/* IVRS IVinfo Field */ -/* ATS response address range reserved */ -#define IVINFO_HT_ATS_RESERVED (1 << 22) - -/* Virtual Address size - All other values are reserved */ -#define IVINFO_VA_SIZE_32_BITS (0x20 << 15) -#define IVINFO_VA_SIZE_40_BITS (0x28 << 15) -#define IVINFO_VA_SIZE_48_BITS (0x30 << 15) -#define IVINFO_VA_SIZE_64_BITS (0x40 << 15) - -/* Physical Address size - All other values are reserved */ -#define IVINFO_PA_SIZE_40_BITS (0x28 << 8) -#define IVINFO_PA_SIZE_48_BITS (0x30 << 8) -#define IVINFO_PA_SIZE_52_BITS (0x34 << 8) - -/* Guest Virtual Address size - All other values are reserved */ -#define IVINFO_GVA_SIZE_48_BITS (0x02 << 5) - -/* Extended Feature Support */ -#define IVINFO_EFR_SUPPORTED 0x01 - -/* IVHD Flags Field */ -#define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */ -#define IVHD_FLAG_PREF_SUP (1 << 6) /* Type 10h only */ -#define IVHD_FLAG_COHERENT (1 << 5) -#define IVHD_FLAG_IOTLB_SUP (1 << 4) -#define IVHD_FLAG_ISOC (1 << 3) -#define IVHD_FLAG_RES_PASS_PW (1 << 2) -#define IVHD_FLAG_PASS_PW (1 << 1) -#define IVHD_FLAG_HT_TUN_EN (1 << 0) - -/* IVHD IOMMU Info Field */ -#define IOMMU_INFO_UNIT_ID_SHIFT 8 - -/* IVHD IOMMU Feature Reporting Field */ -#define IOMMU_FEATURE_HATS_SHIFT 30 /* Type 10h only */ -#define IOMMU_FEATURE_GATS_SHIFT 28 /* Type 10h only */ -#define IOMMU_FEATURE_MSI_NUM_PPR_SHIFT 23 -#define IOMMU_FEATURE_PN_BANKS_SHIFT 17 -#define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13 -#define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */ - -#define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */ -#define IOMMU_FEATURE_GA_SUP (1 << 6) /* Type 10h only */ -#define IOMMU_FEATURE_IA_SUP (1 << 5) /* Type 10h only */ -#define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */ -#define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */ -#define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */ -#define IOMMU_FEATURE_GT_SUP (1 << 1) /* Type 10h only */ -#define IOMMU_FEATURE_NX_SUP (1 << 0) /* Type 10h only */ - -/* IVHD Device Entry Type Codes */ -#define IVHD_DEV_4_BYTE_ALL 0x01 -#define IVHD_DEV_4_BYTE_SELECT 0x02 -#define IVHD_DEV_4_BYTE_START_RANGE 0x03 -#define IVHD_DEV_4_BYTE_END_RANGE 0x04 -#define IVHD_DEV_8_BYTE_ALIAS_SELECT 0x42 -#define IVHD_DEV_8_BYTE_ALIAS_START_RANGE 0x43 -#define IVHD_DEV_8_BYTE_EXT_SELECT 0x46 -#define IVHD_DEV_8_BYTE_EXT_START_RANGE 0x47 -#define IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV 0x48 -#define IVHD_DEV_VARIABLE 0xF0 - -/* IVHD Device Table Entry (DTE) Settings */ -#define IVHD_DTE_LINT_1_PASS (1 << 7) -#define IVHD_DTE_LINT_0_PASS (1 << 6) -#define IVHD_DTE_SYS_MGT_TGT_ABT (0 << 4) -#define IVHD_DTE_SYS_MGT_NO_TRANS (1 << 4) -#define IVHD_DTE_SYS_MGT_INTX_NO_TRANS (2 << 4) -#define IVHD_DTE_SYS_MGT_TRANS (3 << 4) -#define IVHD_DTE_NMI_PASS (1 << 2) -#define IVHD_DTE_EXT_INT_PASS (1 << 1) -#define IVHD_DTE_INIT_PASS (1 << 0) - -/* IVHD Device Entry Extended DTE Setting Field */ -#define IVHD_DEV_EXT_ATS_DISABLE (1 << 31) - -/* IVHD Special Device Entry Variety Field */ -#define IVHD_SPECIAL_DEV_IOAPIC 0x01 -#define IVHD_SPECIAL_DEV_HPET 0x02 - -/* Device EntryType F0h UID Format */ -#define IVHD_UID_NOT_PRESENT 0x00 -#define IVHD_UID_INT 0x01 -#define IVHD_UID_STRING 0x02 - -/* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ -typedef struct ivrs_ivhd_generic { - uint8_t type; - uint16_t dev_id; - uint8_t dte_setting; -} __packed ivrs_ivhd_generic_t; - -/* IVHD (I/O Virtualization Hardware Definition Block) 8-byte entries */ -typedef struct ivrs_ivhd_alias { - uint8_t type; - uint16_t dev_id; - uint8_t dte_setting; - uint8_t reserved1; - uint16_t source_dev_id; - uint8_t reserved2; -} __packed ivrs_ivhd_alias_t; - -typedef struct ivrs_ivhd_extended { - uint8_t type; - uint16_t dev_id; - uint8_t dte_setting; - uint32_t extended_dte_setting; -} __packed ivrs_ivhd_extended_t; - -typedef struct ivrs_ivhd_special { - uint8_t type; - uint16_t reserved; - uint8_t dte_setting; - uint8_t handle; - uint16_t source_dev_id; - uint8_t variety; -} __packed ivrs_ivhd_special_t; - -#endif +#include diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h index 944eb3154a..5076e39a71 100644 --- a/src/arch/x86/include/arch/acpi_pld.h +++ b/src/arch/x86/include/arch/acpi_pld.h @@ -1,119 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef __ACPI_PLD_H -#define __ACPI_PLD_H - -#include -#include - -enum acpi_pld_panel { - PLD_PANEL_TOP, - PLD_PANEL_BOTTOM, - PLD_PANEL_LEFT, - PLD_PANEL_RIGHT, - PLD_PANEL_FRONT, - PLD_PANEL_BACK, - PLD_PANEL_UNKNOWN -}; - -enum acpi_pld_vertical_position { - PLD_VERTICAL_POSITION_UPPER, - PLD_VERTICAL_POSITION_CENTER, - PLD_VERTICAL_POSITION_LOWER -}; - -/* - * The ACPI spec 6.2A does not define the horizontal position field. - * These values are taken from the IASL compiler: - * https://github.com/acpica/acpica/blob/master/source/components/utilities/utglobal.c#L321 - */ - -enum acpi_pld_horizontal_position { - PLD_HORIZONTAL_POSITION_LEFT, - PLD_HORIZONTAL_POSITION_CENTER, - PLD_HORIZONTAL_POSITION_RIGHT -}; - -enum acpi_pld_shape { - PLD_SHAPE_ROUND, - PLD_SHAPE_OVAL, - PLD_SHAPE_SQUARE, - PLD_SHAPE_VERTICAL_RECTANGLE, - PLD_SHAPE_HORIZONTAL_RECTANGLE, - PLD_SHAPE_VERTICAL_TRAPEZOID, - PLD_SHAPE_HORIZONTAL_TRAPEZOID, - PLD_SHAPE_UNKNOWN, - PLD_SHAPE_CHAMFERED -}; - -enum acpi_pld_orientation { - PLD_ORIENTATION_HORIZONTAL, - PLD_ORIENTATION_VERTICAL, -}; - -enum acpi_pld_rotate { - PLD_ROTATE_0, - PLD_ROTATE_45, - PLD_ROTATE_90, - PLD_ROTATE_135, - PLD_ROTATE_180, - PLD_ROTATE_225, - PLD_ROTATE_270, - PLD_ROTATE_315 -}; - -#define ACPI_PLD_GROUP(__token, __position) \ - { \ - .token = __token, \ - .position = __position, \ - } - -struct acpi_pld_group { - uint8_t token; - uint8_t position; -}; - -struct acpi_pld { - /* Color field can be explicitly ignored */ - bool ignore_color; - uint8_t color_red; - uint8_t color_blue; - uint8_t color_green; - - /* Port characteristics */ - bool visible; /* Can be seen by the user */ - bool lid; /* Port is on lid of device */ - bool dock; /* Port is in a docking station */ - bool bay; /* Port is in a bay */ - bool ejectable; /* Device is ejectable, has _EJx objects */ - bool ejectable_ospm; /* Device needs OSPM to eject */ - uint16_t width; /* Width in mm */ - uint16_t height; /* Height in mm */ - uint16_t vertical_offset; - uint16_t horizontal_offset; - enum acpi_pld_panel panel; - enum acpi_pld_horizontal_position horizontal_position; - enum acpi_pld_vertical_position vertical_position; - enum acpi_pld_shape shape; - enum acpi_pld_rotate rotation; - - /* Port grouping */ - enum acpi_pld_orientation orientation; - struct acpi_pld_group group; - uint8_t draw_order; - uint8_t cabinet_number; - uint8_t card_cage_number; - - /* Set if this PLD defines a reference shape */ - bool reference_shape; -}; - -/* Fill out PLD structure with defaults based on USB port type */ -int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, - struct acpi_pld_group *group); - -/* Turn PLD structure into a 20 byte ACPI buffer */ -int acpi_pld_to_buffer(const struct acpi_pld *pld, uint8_t *buf, int buf_len); - -#endif +#include diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index a3c4777afb..cdac49fc1b 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -1,490 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef LIBACPI_H -#define LIBACPI_H - -#include -#include -#include -#include -#include - -/* Values that can be returned for ACPI Device _STA method */ -#define ACPI_STATUS_DEVICE_PRESENT (1 << 0) -#define ACPI_STATUS_DEVICE_ENABLED (1 << 1) -#define ACPI_STATUS_DEVICE_SHOW_IN_UI (1 << 2) -#define ACPI_STATUS_DEVICE_STATE_OK (1 << 3) - -#define ACPI_STATUS_DEVICE_ALL_OFF 0 -#define ACPI_STATUS_DEVICE_ALL_ON (ACPI_STATUS_DEVICE_PRESENT |\ - ACPI_STATUS_DEVICE_ENABLED |\ - ACPI_STATUS_DEVICE_SHOW_IN_UI |\ - ACPI_STATUS_DEVICE_STATE_OK) -#define ACPI_STATUS_DEVICE_HIDDEN_ON (ACPI_STATUS_DEVICE_PRESENT |\ - ACPI_STATUS_DEVICE_ENABLED |\ - ACPI_STATUS_DEVICE_STATE_OK) - -/* ACPI Op/Prefix Codes */ -enum { - ZERO_OP = 0x00, - ONE_OP = 0x01, - ALIAS_OP = 0x06, - NAME_OP = 0x08, - BYTE_PREFIX = 0x0A, - WORD_PREFIX = 0x0B, - DWORD_PREFIX = 0x0C, - STRING_PREFIX = 0x0D, - QWORD_PREFIX = 0x0E, - SCOPE_OP = 0x10, - BUFFER_OP = 0x11, - PACKAGE_OP = 0x12, - VARIABLE_PACKAGE_OP = 0x13, - METHOD_OP = 0x14, - EXTERNAL_OP = 0x15, - DUAL_NAME_PREFIX = 0x2E, - MULTI_NAME_PREFIX = 0x2F, - EXT_OP_PREFIX = 0x5B, - MUTEX_OP = 0x01, - EVENT_OP = 0x01, - SF_RIGHT_OP = 0x10, - SF_LEFT_OP = 0x11, - COND_REFOF_OP = 0x12, - CREATEFIELD_OP = 0x13, - LOAD_TABLE_OP = 0x1f, - LOAD_OP = 0x20, - STALL_OP = 0x21, - SLEEP_OP = 0x22, - ACQUIRE_OP = 0x23, - SIGNAL_OP = 0x24, - WAIT_OP = 0x25, - RST_OP = 0x26, - RELEASE_OP = 0x27, - FROM_BCD_OP = 0x28, - TO_BCD_OP = 0x29, - UNLOAD_OP = 0x2A, - REVISON_OP = 0x30, - DEBUG_OP = 0x31, - FATAL_OP = 0x32, - TIMER_OP = 0x33, - OPREGION_OP = 0x80, - FIELD_OP = 0x81, - DEVICE_OP = 0x82, - PROCESSOR_OP = 0x83, - POWER_RES_OP = 0x84, - THERMAL_ZONE_OP = 0x85, - INDEX_FIELD_OP = 0x86, - BANK_FIELD_OP = 0x87, - DATA_REGION_OP = 0x88, - ROOT_PREFIX = 0x5C, - PARENT_PREFIX = 0x5E, - LOCAL0_OP = 0x60, - LOCAL1_OP = 0x61, - LOCAL2_OP = 0x62, - LOCAL3_OP = 0x63, - LOCAL4_OP = 0x64, - LOCAL5_OP = 0x65, - LOCAL6_OP = 0x66, - LOCAL7_OP = 0x67, - ARG0_OP = 0x68, - ARG1_OP = 0x69, - ARG2_OP = 0x6A, - ARG3_OP = 0x6B, - ARG4_OP = 0x6C, - ARG5_OP = 0x6D, - ARG6_OP = 0x6E, - STORE_OP = 0x70, - REF_OF_OP = 0x71, - ADD_OP = 0x72, - CONCATENATE_OP = 0x73, - SUBTRACT_OP = 0x74, - INCREMENT_OP = 0x75, - DECREMENT_OP = 0x76, - MULTIPLY_OP = 0x77, - DIVIDE_OP = 0x78, - SHIFT_LEFT_OP = 0x79, - SHIFT_RIGHT_OP = 0x7A, - AND_OP = 0x7B, - NAND_OP = 0x7C, - OR_OP = 0x7D, - NOR_OP = 0x7E, - XOR_OP = 0x7F, - NOT_OP = 0x80, - FD_SHIFT_LEFT_BIT_OR = 0x81, - FD_SHIFT_RIGHT_BIT_OR = 0x82, - DEREF_OP = 0x83, - CONCATENATE_TEMP_OP = 0x84, - MOD_OP = 0x85, - NOTIFY_OP = 0x86, - SIZEOF_OP = 0x87, - INDEX_OP = 0x88, - MATCH_OP = 0x89, - CREATE_DWORD_OP = 0x8A, - CREATE_WORD_OP = 0x8B, - CREATE_BYTE_OP = 0x8C, - CREATE_BIT_OP = 0x8D, - OBJ_TYPE_OP = 0x8E, - CREATE_QWORD_OP = 0x8F, - LAND_OP = 0x90, - LOR_OP = 0x91, - LNOT_OP = 0x92, - LEQUAL_OP = 0x93, - LGREATER_OP = 0x94, - LLESS_OP = 0x95, - TO_BUFFER_OP = 0x96, - TO_DEC_STRING_OP = 0x97, - TO_HEX_STRING_OP = 0x98, - TO_INTEGER_OP = 0x99, - TO_STRING_OP = 0x9C, - CP_OBJ_OP = 0x9D, - MID_OP = 0x9E, - CONTINUE_OP = 0x9F, - IF_OP = 0xA0, - ELSE_OP = 0xA1, - WHILE_OP = 0xA2, - NOOP_OP = 0xA3, - RETURN_OP = 0xA4, - BREAK_OP = 0xA5, - COMMENT_OP = 0xA9, - BREAKPIONT_OP = 0xCC, - ONES_OP = 0xFF, -}; - -#define FIELDLIST_OFFSET(X) { .type = OFFSET, \ - .name = "",\ - .bits = X * 8, \ - } -#define FIELDLIST_NAMESTR(X, Y) { .type = NAME_STRING, \ - .name = X, \ - .bits = Y, \ - } - -#define FIELD_ANYACC 0 -#define FIELD_BYTEACC 1 -#define FIELD_WORDACC 2 -#define FIELD_DWORDACC 3 -#define FIELD_QWORDACC 4 -#define FIELD_BUFFERACC 5 -#define FIELD_NOLOCK (0<<4) -#define FIELD_LOCK (1<<4) -#define FIELD_PRESERVE (0<<5) -#define FIELD_WRITEASONES (1<<5) -#define FIELD_WRITEASZEROS (2<<5) - -enum field_type { - OFFSET, - NAME_STRING, - FIELD_TYPE_MAX, -}; - -struct fieldlist { - enum field_type type; - const char *name; - u32 bits; -}; - -#define OPREGION(rname, space, offset, len) {.name = rname, \ - .regionspace = space, \ - .regionoffset = offset, \ - .regionlen = len, \ - } - -enum region_space { - SYSTEMMEMORY, - SYSTEMIO, - PCI_CONFIG, - EMBEDDEDCONTROL, - SMBUS, - CMOS, - PCIBARTARGET, - IPMI, - GPIO_REGION, - GPSERIALBUS, - PCC, - FIXED_HARDWARE = 0x7F, - REGION_SPACE_MAX, -}; - -struct opregion { - const char *name; - enum region_space regionspace; - unsigned long regionoffset; - unsigned long regionlen; -}; - -#define DSM_UUID(DSM_UUID, DSM_CALLBACKS, DSM_COUNT, DSM_ARG) \ - { .uuid = DSM_UUID, \ - .callbacks = DSM_CALLBACKS, \ - .count = DSM_COUNT, \ - .arg = DSM_ARG, \ - } - -struct dsm_uuid { - const char *uuid; - void (**callbacks)(void *); - size_t count; - void *arg; -}; - -/*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ -enum cppc_fields { - CPPC_HIGHEST_PERF, /* can be DWORD */ - CPPC_NOMINAL_PERF, /* can be DWORD */ - CPPC_LOWEST_NONL_PERF, /* can be DWORD */ - CPPC_LOWEST_PERF, /* can be DWORD */ - CPPC_GUARANTEED_PERF, - CPPC_DESIRED_PERF, - CPPC_MIN_PERF, - CPPC_MAX_PERF, - CPPC_PERF_REDUCE_TOLERANCE, - CPPC_TIME_WINDOW, - CPPC_COUNTER_WRAP, /* can be DWORD */ - CPPC_REF_PERF_COUNTER, - CPPC_DELIVERED_PERF_COUNTER, - CPPC_PERF_LIMITED, - CPPC_ENABLE, /* can be System I/O */ - CPPC_MAX_FIELDS_VER_1, - CPPC_AUTO_SELECT = /* can be DWORD */ - CPPC_MAX_FIELDS_VER_1, - CPPC_AUTO_ACTIVITY_WINDOW, - CPPC_PERF_PREF, - CPPC_REF_PERF, /* can be DWORD */ - CPPC_MAX_FIELDS_VER_2, - CPPC_LOWEST_FREQ = /* can be DWORD */ - CPPC_MAX_FIELDS_VER_2, - CPPC_NOMINAL_FREQ, /* can be DWORD */ - CPPC_MAX_FIELDS_VER_3, -}; - -struct cppc_config { - u32 version; /* must be 1, 2, or 3 */ - /* - * The generic acpi_addr_t structure is being used, though - * anything besides PPC or FFIXED generally requires checking - * if the OS has advertised support for it (via _OSC). - * - * NOTE: some fields permit DWORDs to be used. If you - * provide a System Memory register with all zeros (which - * represents unsupported) then this will be used as-is. - * Otherwise, a System Memory register with a 32-bit - * width will be converted into a DWORD field (the value - * of which will be the value of 'addrl'. Any other use - * of System Memory register is currently undefined. - * (i.e., if you have an actual need for System Memory - * then you'll need to adjust this kludge). - */ - acpi_addr_t regs[CPPC_MAX_FIELDS_VER_3]; -}; - -void acpigen_write_return_integer(uint64_t arg); -void acpigen_write_return_string(const char *arg); -void acpigen_write_len_f(void); -void acpigen_pop_len(void); -void acpigen_set_current(char *curr); -char *acpigen_get_current(void); -char *acpigen_write_package(int nr_el); -void acpigen_write_zero(void); -void acpigen_write_one(void); -void acpigen_write_ones(void); -void acpigen_write_byte(unsigned int data); -void acpigen_emit_byte(unsigned char data); -void acpigen_emit_ext_op(uint8_t op); -void acpigen_emit_word(unsigned int data); -void acpigen_emit_dword(unsigned int data); -void acpigen_emit_stream(const char *data, int size); -void acpigen_emit_string(const char *string); -void acpigen_emit_namestring(const char *namepath); -void acpigen_emit_eisaid(const char *eisaid); -void acpigen_write_word(unsigned int data); -void acpigen_write_dword(unsigned int data); -void acpigen_write_qword(uint64_t data); -void acpigen_write_integer(uint64_t data); -void acpigen_write_string(const char *string); -void acpigen_write_name_unicode(const char *name, const char *string); -void acpigen_write_name(const char *name); -void acpigen_write_name_zero(const char *name); -void acpigen_write_name_one(const char *name); -void acpigen_write_name_string(const char *name, const char *string); -void acpigen_write_name_dword(const char *name, uint32_t val); -void acpigen_write_name_qword(const char *name, uint64_t val); -void acpigen_write_name_byte(const char *name, uint8_t val); -void acpigen_write_name_integer(const char *name, uint64_t val); -void acpigen_write_coreboot_hid(enum coreboot_acpi_ids id); -void acpigen_write_scope(const char *name); -void acpigen_write_method(const char *name, int nargs); -void acpigen_write_method_serialized(const char *name, int nargs); -void acpigen_write_device(const char *name); -void acpigen_write_PPC(u8 nr); -void acpigen_write_PPC_NVS(void); -void acpigen_write_empty_PCT(void); -void acpigen_write_empty_PTC(void); -void acpigen_write_PRW(u32 wake, u32 level); -void acpigen_write_STA(uint8_t status); -void acpigen_write_TPC(const char *gnvs_tpc_limit); -void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, - u32 busmLat, u32 control, u32 status); -typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord; -void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); -void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); -typedef enum { CSD_HW_ALL = 0xfe } CSD_coord; -void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, - u32 index); -void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); -void acpigen_write_processor_package(const char *name, - unsigned int first_core, - unsigned int core_count); -void acpigen_write_processor_cnot(const unsigned int number_of_cores); -void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); -void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); -void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); -void acpigen_write_register_resource(const acpi_addr_t *addr); -void acpigen_write_resourcetemplate_header(void); -void acpigen_write_resourcetemplate_footer(void); -void acpigen_write_mainboard_resource_template(void); -void acpigen_write_mainboard_resources(const char *scope, const char *name); -void acpigen_write_irq(u16 mask); -void acpigen_write_uuid(const char *uuid); -void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, - const char * const dev_states[], size_t dev_states_count); -void acpigen_write_sleep(uint64_t sleep_ms); -void acpigen_write_store(void); -void acpigen_write_store_ops(uint8_t src, uint8_t dst); -void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst); -void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); -void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); -void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); -void acpigen_write_not(uint8_t arg, uint8_t res); -void acpigen_write_debug_string(const char *str); -void acpigen_write_debug_integer(uint64_t val); -void acpigen_write_debug_op(uint8_t op); -void acpigen_write_if(void); -void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); -void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); -void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); -void acpigen_write_else(void); -void acpigen_write_to_buffer(uint8_t src, uint8_t dst); -void acpigen_write_to_integer(uint8_t src, uint8_t dst); -void acpigen_write_byte_buffer(uint8_t *arr, size_t size); -void acpigen_write_return_byte_buffer(uint8_t *arr, size_t size); -void acpigen_write_return_singleton_buffer(uint8_t arg); -void acpigen_write_return_byte(uint8_t arg); -void acpigen_write_upc(enum acpi_upc_type type); -void acpigen_write_pld(const struct acpi_pld *pld); -void acpigen_write_ADR(uint64_t adr); -void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); -void acpigen_write_ADR_pci_device(const struct device *dev); -/* - * Generate ACPI AML code for _DSM method. - * This function takes as input uuid for the device, set of callbacks and - * argument to pass into the callbacks. Callbacks should ensure that Local0 and - * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. - */ -void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *), - size_t count, void *arg); -void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count); - -/* - * Generate ACPI AML code for _CPC (Continuous Performance Control). - * Execute the package function once to create a global table, then - * execute the method function within each processor object to - * create a method that points to the global table. - */ -void acpigen_write_CPPC_package(const struct cppc_config *config); -void acpigen_write_CPPC_method(void); - -/* - * Generate ACPI AML code for _ROM method. - * This function takes as input ROM data and ROM length. - * The ROM length has to be multiple of 4096 and has to be less - * than the current implementation limit of 0x40000. - */ -void acpigen_write_rom(void *bios, const size_t length); -/* - * Generate ACPI AML code for OperationRegion - * This function takes input region name, region space, region offset & region - * length. - */ -void acpigen_write_opregion(struct opregion *opreg); -/* - * Generate ACPI AML code for Mutex - * This function takes mutex name and initial value. - */ -void acpigen_write_mutex(const char *name, const uint8_t flags); -/* - * Generate ACPI AML code for Acquire - * This function takes mutex name and privilege value. - */ -void acpigen_write_acquire(const char *name, const uint16_t val); -/* - * Generate ACPI AML code for Release - * This function takes mutex name. - */ -void acpigen_write_release(const char *name); -/* - * Generate ACPI AML code for Field - * This function takes input region name, fieldlist, count & flags. - */ -void acpigen_write_field(const char *name, const struct fieldlist *l, size_t count, - uint8_t flags); -/* - * Generate ACPI AML code for IndexField - * This function takes input index name, data name, fieldlist, count & flags. - */ -void acpigen_write_indexfield(const char *idx, const char *data, - struct fieldlist *l, size_t count, uint8_t flags); - -int get_cst_entries(acpi_cstate_t **); - -/* - * Soc-implemented functions for generating ACPI AML code for GPIO handling. All - * these functions are expected to use only Local5, Local6 and Local7 - * variables. If the functions call into another ACPI method, then there is no - * restriction on the use of Local variables. In case of get/read functions, - * return value is expected to be stored in Local0 variable. - * - * All functions return 0 on success and -1 on error. - */ - -/* Generate ACPI AML code to return Rx value of GPIO in Local0. */ -int acpigen_soc_read_rx_gpio(unsigned int gpio_num); - -/* Generate ACPI AML code to return Tx value of GPIO in Local0. */ -int acpigen_soc_get_tx_gpio(unsigned int gpio_num); - -/* Generate ACPI AML code to set Tx value of GPIO to 1. */ -int acpigen_soc_set_tx_gpio(unsigned int gpio_num); - -/* Generate ACPI AML code to set Tx value of GPIO to 0. */ -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num); - -/* - * Helper functions for enabling/disabling Tx GPIOs based on the GPIO - * polarity. These functions end up calling acpigen_soc_{set,clear}_tx_gpio to - * make callbacks into SoC acpigen code. - * - * Returns 0 on success and -1 on error. - */ -int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); -int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); - -/* - * Helper function for getting a RX GPIO value based on the GPIO polarity. - * The return value is stored in Local0 variable. - * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks - * into SoC acpigen code - */ -void acpigen_get_rx_gpio(struct acpi_gpio *gpio); - -/* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ -void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, - u16 range_min, u16 range_max, u16 translation, u16 length); -/* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */ -void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, - u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length); -/* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ -void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, - u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); - -#endif +#include diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h index c51c12b6e3..0804ab975a 100644 --- a/src/arch/x86/include/arch/acpigen_dsm.h +++ b/src/arch/x86/include/arch/acpigen_dsm.h @@ -1,15 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef __ARCH_ACPIGEN_DSM_H__ -#define __ARCH_ACPIGEN_DSM_H__ - -#include - -struct dsm_i2c_hid_config { - uint8_t hid_desc_reg_offset; -}; - -void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config); - -#endif /* __ARCH_ACPIGEN_DSM_H__ */ +#include diff --git a/src/arch/x86/include/arch/acpigen_ps2_keybd.h b/src/arch/x86/include/arch/acpigen_ps2_keybd.h index c0228bca16..894524a6ac 100644 --- a/src/arch/x86/include/arch/acpigen_ps2_keybd.h +++ b/src/arch/x86/include/arch/acpigen_ps2_keybd.h @@ -4,38 +4,4 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __ACPIGEN_PS2_KEYBD_H__ -#define __ACPIGEN_PS2_KEYBD_H__ - -#include - -enum ps2_action_key { - PS2_KEY_ABSENT = 0, - PS2_KEY_BACK, - PS2_KEY_FORWARD, - PS2_KEY_REFRESH, - PS2_KEY_FULLSCREEN, - PS2_KEY_OVERVIEW, - PS2_KEY_BRIGHTNESS_DOWN, - PS2_KEY_BRIGHTNESS_UP, - PS2_KEY_VOL_MUTE, - PS2_KEY_VOL_DOWN, - PS2_KEY_VOL_UP, - PS2_KEY_SNAPSHOT, - PS2_KEY_PRIVACY_SCRN_TOGGLE, - PS2_KEY_KBD_BKLIGHT_DOWN, - PS2_KEY_KBD_BKLIGHT_UP, - PS2_KEY_PLAY_PAUSE, - PS2_KEY_NEXT_TRACK, - PS2_KEY_PREV_TRACK, -}; - -#define PS2_MIN_TOP_ROW_KEYS 10 -#define PS2_MAX_TOP_ROW_KEYS 15 - -void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, - enum ps2_action_key action_keys[], - bool can_send_function_keys, - bool has_numeric_keypad, bool has_scrnlock_key); - -#endif /* __ACPIGEN_PS2_KEYBD_H__ */ +#include diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h new file mode 100644 index 0000000000..5314d78197 --- /dev/null +++ b/src/include/acpi/acpi.h @@ -0,0 +1,1052 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * coreboot ACPI support - headers and defines. + */ + +#ifndef __ASM_ACPI_H +#define __ASM_ACPI_H + +/* + * The type and enable fields are common in ACPI, but the + * values themselves are hardware implementation defined. + */ +#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) + #define SLP_EN (1 << 13) + #define SLP_TYP_SHIFT 10 + #define SLP_TYP (7 << SLP_TYP_SHIFT) + #define SLP_TYP_S0 0 + #define SLP_TYP_S1 1 + #define SLP_TYP_S3 5 + #define SLP_TYP_S4 6 + #define SLP_TYP_S5 7 +#elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) + #define SLP_EN (1 << 13) + #define SLP_TYP_SHIFT 10 + #define SLP_TYP (7 << SLP_TYP_SHIFT) + #define SLP_TYP_S0 0 + #define SLP_TYP_S1 1 + #define SLP_TYP_S3 3 + #define SLP_TYP_S4 4 + #define SLP_TYP_S5 5 +#endif + +#define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ +#define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include +#include +#include +#include +#include + +#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ +#define ASLC "CORE" /* Must be exactly 4 bytes long! */ + +/* + * The assigned ACPI ID for the coreboot project is 'BOOT' + * http://www.uefi.org/acpi_id_list + */ +#define COREBOOT_ACPI_ID "BOOT" /* ACPI ID for coreboot HIDs */ + +/* List of ACPI HID that use the coreboot ACPI ID */ +enum coreboot_acpi_ids { + COREBOOT_ACPI_ID_CBTABLE = 0x0000, /* BOOT0000 */ + COREBOOT_ACPI_ID_MAX = 0xFFFF, /* BOOTFFFF */ +}; + +enum acpi_tables { + /* Tables defined by ACPI and used by coreboot */ + BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, + RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, + /* Additional proprietary tables used by coreboot */ + VFCT, NHLT, SPMI +}; + +/* RSDP (Root System Description Pointer) */ +typedef struct acpi_rsdp { + char signature[8]; /* RSDP signature */ + u8 checksum; /* Checksum of the first 20 bytes */ + char oem_id[6]; /* OEM ID */ + u8 revision; /* RSDP revision */ + u32 rsdt_address; /* Physical address of RSDT (32 bits) */ + u32 length; /* Total RSDP length (incl. extended part) */ + u64 xsdt_address; /* Physical address of XSDT (64 bits) */ + u8 ext_checksum; /* Checksum of the whole table */ + u8 reserved[3]; +} __packed acpi_rsdp_t; + +/* GAS (Generic Address Structure) */ +typedef struct acpi_gen_regaddr { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size since ACPI 2.0c */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ +} __packed acpi_addr_t; + +#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ +#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ +#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ +#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ +#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ +#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ +#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ +#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ +#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ +#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ +#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ +/* 0x80-0xbf: Reserved */ +/* 0xc0-0xff: OEM defined */ + +/* Access size definitions for Generic address structure */ +#define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */ +#define ACPI_ACCESS_SIZE_BYTE_ACCESS 1 +#define ACPI_ACCESS_SIZE_WORD_ACCESS 2 +#define ACPI_ACCESS_SIZE_DWORD_ACCESS 3 +#define ACPI_ACCESS_SIZE_QWORD_ACCESS 4 + +/* Common ACPI HIDs */ +#define ACPI_HID_FDC "PNP0700" +#define ACPI_HID_KEYBOARD "PNP0303" +#define ACPI_HID_MOUSE "PNP0F03" +#define ACPI_HID_COM "PNP0501" +#define ACPI_HID_LPT "PNP0400" +#define ACPI_HID_PNP "PNP0C02" +#define ACPI_HID_CONTAINER "PNP0A05" + +/* Generic ACPI header, provided by (almost) all tables */ +typedef struct acpi_table_header { + char signature[4]; /* ACPI signature (4 ASCII characters) */ + u32 length; /* Table length in bytes (incl. header) */ + u8 revision; /* Table version (not ACPI version!) */ + u8 checksum; /* To make sum of entire table == 0 */ + char oem_id[6]; /* OEM identification */ + char oem_table_id[8]; /* OEM table identification */ + u32 oem_revision; /* OEM revision number */ + char asl_compiler_id[4]; /* ASL compiler vendor ID */ + u32 asl_compiler_revision; /* ASL compiler revision number */ +} __packed acpi_header_t; + +/* A maximum number of 32 ACPI tables ought to be enough for now. */ +#define MAX_ACPI_TABLES 32 + +/* RSDT (Root System Description Table) */ +typedef struct acpi_rsdt { + acpi_header_t header; + u32 entry[MAX_ACPI_TABLES]; +} __packed acpi_rsdt_t; + +/* XSDT (Extended System Description Table) */ +typedef struct acpi_xsdt { + acpi_header_t header; + u64 entry[MAX_ACPI_TABLES]; +} __packed acpi_xsdt_t; + +/* HPET timers */ +typedef struct acpi_hpet { + acpi_header_t header; + u32 id; + acpi_addr_t addr; + u8 number; + u16 min_tick; + u8 attributes; +} __packed acpi_hpet_t; + +/* MCFG (PCI Express MMIO config space BAR description table) */ +typedef struct acpi_mcfg { + acpi_header_t header; + u8 reserved[8]; +} __packed acpi_mcfg_t; + +typedef struct acpi_tcpa { + acpi_header_t header; + u16 platform_class; + u32 laml; + u64 lasa; +} __packed acpi_tcpa_t; + +typedef struct acpi_tpm2 { + acpi_header_t header; + u16 platform_class; + u8 reserved[2]; + u64 control_area; + u32 start_method; + u8 msp[12]; + u32 laml; + u64 lasa; +} __packed acpi_tpm2_t; + +typedef struct acpi_mcfg_mmconfig { + u32 base_address; + u32 base_reserved; + u16 pci_segment_group_number; + u8 start_bus_number; + u8 end_bus_number; + u8 reserved[4]; +} __packed acpi_mcfg_mmconfig_t; + +/* SRAT (System Resource Affinity Table) */ +typedef struct acpi_srat { + acpi_header_t header; + u32 resv; + u64 resv1; + /* Followed by static resource allocation structure[n] */ +} __packed acpi_srat_t; + +/* SRAT: Processor Local APIC/SAPIC Affinity Structure */ +typedef struct acpi_srat_lapic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (16) */ + u8 proximity_domain_7_0; /* Proximity domain bits[7:0] */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */ + u8 local_sapic_eid; /* Local SAPIC EID */ + u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */ + u32 clock_domain; /* _CDM Clock Domain */ +} __packed acpi_srat_lapic_t; + +/* SRAT: Memory Affinity Structure */ +typedef struct acpi_srat_mem { + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (40) */ + u32 proximity_domain; /* Proximity domain */ + u16 resv; + u32 base_address_low; /* Mem range base address, low */ + u32 base_address_high; /* Mem range base address, high */ + u32 length_low; /* Mem range length, low */ + u32 length_high; /* Mem range length, high */ + u32 resv1; + u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2, + * other bits reserved to 0 + */ + u32 resv2[2]; +} __packed acpi_srat_mem_t; + +/* SLIT (System Locality Distance Information Table) */ +typedef struct acpi_slit { + acpi_header_t header; + /* Followed by static resource allocation 8+byte[num*num] */ +} __packed acpi_slit_t; + +/* MADT (Multiple APIC Description Table) */ +typedef struct acpi_madt { + acpi_header_t header; + u32 lapic_addr; /* Local APIC address */ + u32 flags; /* Multiple APIC flags */ +} __packed acpi_madt_t; + +/* VFCT image header */ +typedef struct acpi_vfct_image_hdr { + u32 PCIBus; + u32 PCIDevice; + u32 PCIFunction; + u16 VendorID; + u16 DeviceID; + u16 SSVID; + u16 SSID; + u32 Revision; + u32 ImageLength; + u8 VbiosContent; // dummy - copy VBIOS here +} __packed acpi_vfct_image_hdr_t; + +/* VFCT (VBIOS Fetch Table) */ +typedef struct acpi_vfct { + acpi_header_t header; + u8 TableUUID[16]; + u32 VBIOSImageOffset; + u32 Lib1ImageOffset; + u32 Reserved[4]; + acpi_vfct_image_hdr_t image_hdr; +} __packed acpi_vfct_t; + +typedef struct acpi_ivrs_info { +} __packed acpi_ivrs_info_t; + +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 10h */ +typedef struct acpi_ivrs_ivhd { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_low; + uint32_t iommu_base_high; + uint16_t pci_segment_group; + uint16_t iommu_info; + uint32_t iommu_feature_info; + uint8_t entry[0]; +} __packed acpi_ivrs_ivhd_t; + +/* IVRS (I/O Virtualization Reporting Structure) Type 10h */ +typedef struct acpi_ivrs { + acpi_header_t header; + uint32_t iv_info; + uint32_t reserved[2]; + struct acpi_ivrs_ivhd ivhd; +} __packed acpi_ivrs_t; + +/* IVHD Type 11h IOMMU Attributes */ +typedef struct ivhd11_iommu_attr { + uint32_t reserved1 : 13; + uint32_t perf_counters : 4; + uint32_t perf_counter_banks : 6; + uint32_t msi_num_ppr : 5; + uint32_t reserved2 : 4; +} __packed ivhd11_iommu_attr_t; + +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 11h */ +typedef struct acpi_ivrs_ivhd_11 { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_low; + uint32_t iommu_base_high; + uint16_t pci_segment_group; + uint16_t iommu_info; + struct ivhd11_iommu_attr iommu_attributes; + uint32_t efr_reg_image_low; + uint32_t efr_reg_image_high; + uint32_t reserved[2]; + uint8_t entry[0]; +} __packed acpi_ivrs_ivhd11_t; + +enum dev_scope_type { + SCOPE_PCI_ENDPOINT = 1, + SCOPE_PCI_SUB = 2, + SCOPE_IOAPIC = 3, + SCOPE_MSI_HPET = 4, + SCOPE_ACPI_NAMESPACE_DEVICE = 5 +}; + +typedef struct dev_scope { + u8 type; + u8 length; + u8 reserved[2]; + u8 enumeration; + u8 start_bus; + struct { + u8 dev; + u8 fn; + } __packed path[0]; +} __packed dev_scope_t; + +enum dmar_type { + DMAR_DRHD = 0, + DMAR_RMRR = 1, + DMAR_ATSR = 2, + DMAR_RHSA = 3, + DMAR_ANDD = 4 +}; + +enum { + DRHD_INCLUDE_PCI_ALL = 1 +}; + +enum dmar_flags { + DMAR_INTR_REMAP = 1 << 0, + DMAR_X2APIC_OPT_OUT = 1 << 1, + DMA_CTRL_PLATFORM_OPT_IN_FLAG = 1 << 2, +}; + +typedef struct dmar_entry { + u16 type; + u16 length; + u8 flags; + u8 reserved; + u16 segment; + u64 bar; +} __packed dmar_entry_t; + +typedef struct dmar_rmrr_entry { + u16 type; + u16 length; + u16 reserved; + u16 segment; + u64 bar; + u64 limit; +} __packed dmar_rmrr_entry_t; + +typedef struct dmar_atsr_entry { + u16 type; + u16 length; + u8 flags; + u8 reserved; + u16 segment; +} __packed dmar_atsr_entry_t; + +typedef struct dmar_rhsa_entry { + u16 type; + u16 length; + u32 reserved; + u64 base_address; + u32 proximity_domain; +} __packed dmar_rhsa_entry_t; + +typedef struct dmar_andd_entry { + u16 type; + u16 length; + u8 reserved[3]; + u8 device_number; + u8 device_name[]; +} __packed dmar_andd_entry_t; + +/* DMAR (DMA Remapping Reporting Structure) */ +typedef struct acpi_dmar { + acpi_header_t header; + u8 host_address_width; + u8 flags; + u8 reserved[10]; + dmar_entry_t structure[0]; +} __packed acpi_dmar_t; + +/* MADT: APIC Structure Types */ +enum acpi_apic_types { + LOCAL_APIC, /* Processor local APIC */ + IO_APIC, /* I/O APIC */ + IRQ_SOURCE_OVERRIDE, /* Interrupt source override */ + NMI_TYPE, /* NMI source */ + LOCAL_APIC_NMI, /* Local APIC NMI */ + LAPIC_ADDRESS_OVERRIDE, /* Local APIC address override */ + IO_SAPIC, /* I/O SAPIC */ + LOCAL_SAPIC, /* Local SAPIC */ + PLATFORM_IRQ_SOURCES, /* Platform interrupt sources */ + LOCAL_X2APIC, /* Processor local x2APIC */ + LOCAL_X2APIC_NMI, /* Local x2APIC NMI */ + GICC, /* GIC CPU Interface */ + GICD, /* GIC Distributor */ + GIC_MSI_FRAME, /* GIC MSI Frame */ + GICR, /* GIC Redistributor */ + GIC_ITS, /* Interrupt Translation Service */ + /* 0x10-0x7f: Reserved */ + /* 0x80-0xff: Reserved for OEM use */ +}; + +/* MADT: Processor Local APIC Structure */ +typedef struct acpi_madt_lapic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (8) */ + u8 processor_id; /* ACPI processor ID */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Local APIC flags */ +} __packed acpi_madt_lapic_t; + +/* MADT: Local APIC NMI Structure */ +typedef struct acpi_madt_lapic_nmi { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (6) */ + u8 processor_id; /* ACPI processor ID */ + u16 flags; /* MPS INTI flags */ + u8 lint; /* Local APIC LINT# */ +} __packed acpi_madt_lapic_nmi_t; + +/* MADT: I/O APIC Structure */ +typedef struct acpi_madt_ioapic { + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (12) */ + u8 ioapic_id; /* I/O APIC ID */ + u8 reserved; + u32 ioapic_addr; /* I/O APIC address */ + u32 gsi_base; /* Global system interrupt base */ +} __packed acpi_madt_ioapic_t; + +/* MADT: Interrupt Source Override Structure */ +typedef struct acpi_madt_irqoverride { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (10) */ + u8 bus; /* ISA (0) */ + u8 source; /* Bus-relative int. source (IRQ) */ + u32 gsirq; /* Global system interrupt */ + u16 flags; /* MPS INTI flags */ +} __packed acpi_madt_irqoverride_t; + +/* MADT: Processor Local x2APIC Structure */ +typedef struct acpi_madt_lx2apic { + u8 type; /* Type (9) */ + u8 length; /* Length in bytes (16) */ + u16 reserved; + u32 x2apic_id; /* Local x2APIC ID */ + u32 flags; /* Same as Local APIC flags */ + u32 processor_id; /* ACPI processor ID */ +} __packed acpi_madt_lx2apic_t; + +/* MADT: Processor Local x2APIC NMI Structure */ +typedef struct acpi_madt_lx2apic_nmi { + u8 type; /* Type (10) */ + u8 length; /* Length in bytes (12) */ + u16 flags; /* Same as MPS INTI flags */ + u32 processor_id; /* ACPI processor ID */ + u8 lint; /* Local APIC LINT# */ + u8 reserved[3]; +} __packed acpi_madt_lx2apic_nmi_t; + +#define ACPI_DBG2_PORT_SERIAL 0x8000 +#define ACPI_DBG2_PORT_SERIAL_16550 0x0000 +#define ACPI_DBG2_PORT_SERIAL_16550_DBGP 0x0001 +#define ACPI_DBG2_PORT_SERIAL_ARM_PL011 0x0003 +#define ACPI_DBG2_PORT_SERIAL_ARM_SBSA 0x000e +#define ACPI_DBG2_PORT_SERIAL_ARM_DDC 0x000f +#define ACPI_DBG2_PORT_SERIAL_BCM2835 0x0010 +#define ACPI_DBG2_PORT_IEEE1394 0x8001 +#define ACPI_DBG2_PORT_IEEE1394_STANDARD 0x0000 +#define ACPI_DBG2_PORT_USB 0x8002 +#define ACPI_DBG2_PORT_USB_XHCI 0x0000 +#define ACPI_DBG2_PORT_USB_EHCI 0x0001 +#define ACPI_DBG2_PORT_NET 0x8003 + +/* DBG2: Microsoft Debug Port Table 2 header */ +typedef struct acpi_dbg2_header { + acpi_header_t header; + uint32_t devices_offset; + uint32_t devices_count; +} __attribute__((packed)) acpi_dbg2_header_t; + +/* DBG2: Microsoft Debug Port Table 2 device entry */ +typedef struct acpi_dbg2_device { + uint8_t revision; + uint16_t length; + uint8_t address_count; + uint16_t namespace_string_length; + uint16_t namespace_string_offset; + uint16_t oem_data_length; + uint16_t oem_data_offset; + uint16_t port_type; + uint16_t port_subtype; + uint8_t reserved[2]; + uint16_t base_address_offset; + uint16_t address_size_offset; +} __attribute__((packed)) acpi_dbg2_device_t; + +/* FADT (Fixed ACPI Description Table) */ +typedef struct acpi_fadt { + acpi_header_t header; + u32 firmware_ctrl; + u32 dsdt; + u8 reserved; /* Should be 0 */ + u8 preferred_pm_profile; + u16 sci_int; + u32 smi_cmd; + u8 acpi_enable; + u8 acpi_disable; + u8 s4bios_req; + u8 pstate_cnt; + u32 pm1a_evt_blk; + u32 pm1b_evt_blk; + u32 pm1a_cnt_blk; + u32 pm1b_cnt_blk; + u32 pm2_cnt_blk; + u32 pm_tmr_blk; + u32 gpe0_blk; + u32 gpe1_blk; + u8 pm1_evt_len; + u8 pm1_cnt_len; + u8 pm2_cnt_len; + u8 pm_tmr_len; + u8 gpe0_blk_len; + u8 gpe1_blk_len; + u8 gpe1_base; + u8 cst_cnt; + u16 p_lvl2_lat; + u16 p_lvl3_lat; + u16 flush_size; + u16 flush_stride; + u8 duty_offset; + u8 duty_width; + u8 day_alrm; + u8 mon_alrm; + u8 century; + u16 iapc_boot_arch; + u8 res2; + u32 flags; + acpi_addr_t reset_reg; + u8 reset_value; + u16 ARM_boot_arch; /* Revision 6 only, Revision 5: Must be zero */ + u8 FADT_MinorVersion; /* Revision 6 only, Revision 5: Must be zero */ + u32 x_firmware_ctl_l; + u32 x_firmware_ctl_h; + u32 x_dsdt_l; + u32 x_dsdt_h; + acpi_addr_t x_pm1a_evt_blk; + acpi_addr_t x_pm1b_evt_blk; + acpi_addr_t x_pm1a_cnt_blk; + acpi_addr_t x_pm1b_cnt_blk; + acpi_addr_t x_pm2_cnt_blk; + acpi_addr_t x_pm_tmr_blk; + acpi_addr_t x_gpe0_blk; + acpi_addr_t x_gpe1_blk; + /* Revision 5 */ + acpi_addr_t sleep_control_reg; + acpi_addr_t sleep_status_reg; + /* Revision 6 */ + u64 hypervisor_vendor_identity; +} __packed acpi_fadt_t; + +/* FADT TABLE Revision values */ +#define ACPI_FADT_REV_ACPI_1_0 1 +#define ACPI_FADT_REV_ACPI_2_0 3 +#define ACPI_FADT_REV_ACPI_3_0 4 +#define ACPI_FADT_REV_ACPI_4_0 4 +#define ACPI_FADT_REV_ACPI_5_0 5 +#define ACPI_FADT_REV_ACPI_6_0 6 + +/* Flags for p_lvl2_lat and p_lvl3_lat */ +#define ACPI_FADT_C2_NOT_SUPPORTED 101 +#define ACPI_FADT_C3_NOT_SUPPORTED 1001 + +/* FADT Feature Flags */ +#define ACPI_FADT_WBINVD (1 << 0) +#define ACPI_FADT_WBINVD_FLUSH (1 << 1) +#define ACPI_FADT_C1_SUPPORTED (1 << 2) +#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) +#define ACPI_FADT_POWER_BUTTON (1 << 4) +#define ACPI_FADT_SLEEP_BUTTON (1 << 5) +#define ACPI_FADT_FIXED_RTC (1 << 6) +#define ACPI_FADT_S4_RTC_WAKE (1 << 7) +#define ACPI_FADT_32BIT_TIMER (1 << 8) +#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) +#define ACPI_FADT_RESET_REGISTER (1 << 10) +#define ACPI_FADT_SEALED_CASE (1 << 11) +#define ACPI_FADT_HEADLESS (1 << 12) +#define ACPI_FADT_SLEEP_TYPE (1 << 13) +#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) +#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) +#define ACPI_FADT_S4_RTC_VALID (1 << 16) +#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) +#define ACPI_FADT_APIC_CLUSTER (1 << 18) +#define ACPI_FADT_APIC_PHYSICAL (1 << 19) +/* Bits 20-31: reserved ACPI 3.0 & 4.0 */ +#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) +#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) +/* bits 22-31: reserved since ACPI 5.0 */ + +/* FADT Boot Architecture Flags */ +#define ACPI_FADT_LEGACY_DEVICES (1 << 0) +#define ACPI_FADT_8042 (1 << 1) +#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) +#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) +#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) +#define ACPI_FADT_NO_CMOS_RTC (1 << 5) +#define ACPI_FADT_LEGACY_FREE 0x00 /* No legacy devices (including 8042) */ + +/* FADT ARM Boot Architecture Flags */ +#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) +#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) +/* bits 2-16: reserved since ACPI 5.1 */ + +/* FADT Preferred Power Management Profile */ +enum acpi_preferred_pm_profiles { + PM_UNSPECIFIED = 0, + PM_DESKTOP = 1, + PM_MOBILE = 2, + PM_WORKSTATION = 3, + PM_ENTERPRISE_SERVER = 4, + PM_SOHO_SERVER = 5, + PM_APPLIANCE_PC = 6, + PM_PERFORMANCE_SERVER = 7, + PM_TABLET = 8, /* ACPI 5.0 & greater */ +}; + +/* FACS (Firmware ACPI Control Structure) */ +typedef struct acpi_facs { + char signature[4]; /* "FACS" */ + u32 length; /* Length in bytes (>= 64) */ + u32 hardware_signature; /* Hardware signature */ + u32 firmware_waking_vector; /* Firmware waking vector */ + u32 global_lock; /* Global lock */ + u32 flags; /* FACS flags */ + u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ + u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ + u8 version; /* FACS version */ + u8 resv1[3]; /* This value is 0 */ + u32 ospm_flags; /* 64BIT_WAKE_F */ + u8 resv2[24]; /* This value is 0 */ +} __packed acpi_facs_t; + +/* FACS flags */ +#define ACPI_FACS_S4BIOS_F (1 << 0) +#define ACPI_FACS_64BIT_WAKE_F (1 << 1) +/* Bits 31..2: reserved */ + +/* ECDT (Embedded Controller Boot Resources Table) */ +typedef struct acpi_ecdt { + acpi_header_t header; + acpi_addr_t ec_control; /* EC control register */ + acpi_addr_t ec_data; /* EC data register */ + u32 uid; /* UID */ + u8 gpe_bit; /* GPE bit */ + u8 ec_id[]; /* EC ID */ +} __packed acpi_ecdt_t; + +/* HEST (Hardware Error Source Table) */ +typedef struct acpi_hest { + acpi_header_t header; + u32 error_source_count; + /* error_source_struct(s) */ +} __packed acpi_hest_t; + +/* Error Source Descriptors */ +typedef struct acpi_hest_esd { + u16 type; + u16 source_id; + u16 resv; + u8 flags; + u8 enabled; + u32 prealloc_erecords; /* The number of error records to + * pre-allocate for this error source. + */ + u32 max_section_per_record; +} __packed acpi_hest_esd_t; + +/* Hardware Error Notification */ +typedef struct acpi_hest_hen { + u8 type; + u8 length; + u16 conf_we; /* Configuration Write Enable */ + u32 poll_interval; + u32 vector; + u32 sw2poll_threshold_val; + u32 sw2poll_threshold_win; + u32 error_threshold_val; + u32 error_threshold_win; +} __packed acpi_hest_hen_t; + +/* BERT (Boot Error Record Table) */ +typedef struct acpi_bert { + acpi_header_t header; + u32 region_length; + u64 error_region; +} __packed acpi_bert_t; + +/* Generic Error Data Entry */ +typedef struct acpi_hest_generic_data { + guid_t section_type; + u32 error_severity; + u16 revision; + u8 validation_bits; + u8 flags; + u32 data_length; + guid_t fru_id; + u8 fru_text[20]; + /* error data */ +} __packed acpi_hest_generic_data_t; + +/* Generic Error Data Entry v300 */ +typedef struct acpi_hest_generic_data_v300 { + guid_t section_type; + u32 error_severity; + u16 revision; + u8 validation_bits; + u8 flags; /* see CPER Section Descriptor, Flags field */ + u32 data_length; + guid_t fru_id; + u8 fru_text[20]; + cper_timestamp_t timestamp; + /* error data */ +} __packed acpi_hest_generic_data_v300_t; +#define HEST_GENERIC_ENTRY_V300 0x300 + +/* Both Generic Error Status & Generic Error Data Entry, Error Severity field */ +#define ACPI_GENERROR_SEV_RECOVERABLE 0 +#define ACPI_GENERROR_SEV_FATAL 1 +#define ACPI_GENERROR_SEV_CORRECTED 2 +#define ACPI_GENERROR_SEV_NONE 3 + +/* Generic Error Data Entry, Validation Bits field */ +#define ACPI_GENERROR_VALID_FRUID BIT(0) +#define ACPI_GENERROR_VALID_FRUID_TEXT BIT(1) +#define ACPI_GENERROR_VALID_TIMESTAMP BIT(2) + +/* Generic Error Status Block */ +typedef struct acpi_generic_error_status { + u32 block_status; + u32 raw_data_offset; /* must follow any generic entries */ + u32 raw_data_length; + u32 data_length; /* generic data */ + u32 error_severity; + /* Generic Error Data structures, zero or more entries */ +} __packed acpi_generic_error_status_t; + +/* Generic Status Block, Block Status values */ +#define GENERIC_ERR_STS_UNCORRECTABLE_VALID BIT(0) +#define GENERIC_ERR_STS_CORRECTABLE_VALID BIT(1) +#define GENERIC_ERR_STS_MULT_UNCORRECTABLE BIT(2) +#define GENERIC_ERR_STS_MULT_CORRECTABLE BIT(3) +#define GENERIC_ERR_STS_ENTRY_COUNT_SHIFT 4 +#define GENERIC_ERR_STS_ENTRY_COUNT_MAX 0x3ff +#define GENERIC_ERR_STS_ENTRY_COUNT_MASK \ + (GENERIC_ERR_STS_ENTRY_COUNT_MAX \ + << GENERIC_ERR_STS_ENTRY_COUNT_SHIFT) + +typedef struct acpi_cstate { + u8 ctype; + u16 latency; + u32 power; + acpi_addr_t resource; +} __packed acpi_cstate_t; + +typedef struct acpi_tstate { + u32 percent; + u32 power; + u32 latency; + u32 control; + u32 status; +} __packed acpi_tstate_t; + +/* Port types for ACPI _UPC object */ +enum acpi_upc_type { + UPC_TYPE_A, + UPC_TYPE_MINI_AB, + UPC_TYPE_EXPRESSCARD, + UPC_TYPE_USB3_A, + UPC_TYPE_USB3_B, + UPC_TYPE_USB3_MICRO_B, + UPC_TYPE_USB3_MICRO_AB, + UPC_TYPE_USB3_POWER_B, + UPC_TYPE_C_USB2_ONLY, + UPC_TYPE_C_USB2_SS_SWITCH, + UPC_TYPE_C_USB2_SS, + UPC_TYPE_PROPRIETARY = 0xff, + /* + * The following types are not directly defined in the ACPI + * spec but are used by coreboot to identify a USB device type. + */ + UPC_TYPE_INTERNAL = 0xff, + UPC_TYPE_UNUSED, + UPC_TYPE_HUB +}; + +enum acpi_ipmi_interface_type { + IPMI_INTERFACE_RESERVED = 0, + IPMI_INTERFACE_KCS, + IPMI_INTERFACE_SMIC, + IPMI_INTERFACE_BT, + IPMI_INTERFACE_SSIF, +}; + +#define ACPI_IPMI_PCI_DEVICE_FLAG (1 << 0) +#define ACPI_IPMI_INT_TYPE_SCI (1 << 0) +#define ACPI_IPMI_INT_TYPE_APIC (1 << 1) + +/* ACPI IPMI 2.0 */ +struct acpi_spmi { + acpi_header_t header; + u8 interface_type; + u8 reserved; + u16 specification_revision; + u8 interrupt_type; + u8 gpe; + u8 reserved2; + u8 pci_device_flag; + + u32 global_system_interrupt; + acpi_addr_t base_address; + union { + struct { + u8 pci_segment_group; + u8 pci_bus; + u8 pci_device; + u8 pci_function; + }; + u8 uid[4]; + }; + u8 reserved3; +} __packed; + +unsigned long fw_cfg_acpi_tables(unsigned long start); + +/* These are implemented by the target port or north/southbridge. */ +unsigned long write_acpi_tables(unsigned long addr); +unsigned long acpi_fill_madt(unsigned long current); +unsigned long acpi_fill_mcfg(unsigned long current); +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); +void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); +void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length); +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); +#if CONFIG(COMMON_FADT) +void acpi_fill_fadt(acpi_fadt_t *fadt); +#endif + +void update_ssdt(void *ssdt); +void update_ssdtx(void *ssdtx, int i); + +/* These can be used by the target port. */ +u8 acpi_checksum(u8 *table, u32 length); + +void acpi_add_table(acpi_rsdp_t *rsdp, void *table); + +int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); +int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, + u32 gsi_base); +int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, + u8 bus, u8 source, u32 gsirq, u16 flags); +int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, + u16 flags, u8 lint); +void acpi_create_madt(acpi_madt_t *madt); +unsigned long acpi_create_madt_lapics(unsigned long current); +unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, + u8 lint); +int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); +int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, + u16 flags, u8 lint); +int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); +int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, + u32 flags); +int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, + u16 seg_nr, u8 start, u8 end); +unsigned long acpi_create_srat_lapics(unsigned long current); +void acpi_create_srat(acpi_srat_t *srat, + unsigned long (*acpi_fill_srat)(unsigned long current)); + +void acpi_create_slit(acpi_slit_t *slit, + unsigned long (*acpi_fill_slit)(unsigned long current)); + +void acpi_create_vfct(const struct device *device, + acpi_vfct_t *vfct, + unsigned long (*acpi_fill_vfct)(const struct device *device, + acpi_vfct_t *vfct_struct, + unsigned long current)); + +void acpi_create_ipmi(const struct device *device, + struct acpi_spmi *spmi, + const u16 ipmi_revision, + const acpi_addr_t *addr, + const enum acpi_ipmi_interface_type type, + const s8 gpe_interrupt, + const u32 apic_interrupt, + const u32 uid); + +void acpi_create_ivrs(acpi_ivrs_t *ivrs, + unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, + unsigned long current)); + +void acpi_create_hpet(acpi_hpet_t *hpet); +unsigned long acpi_write_hpet(const struct device *device, unsigned long start, + acpi_rsdp_t *rsdp); + +/* cpu/intel/speedstep/acpi.c */ +void generate_cpu_entries(const struct device *device); + +void acpi_create_mcfg(acpi_mcfg_t *mcfg); + +void acpi_create_facs(acpi_facs_t *facs); + +void acpi_create_dbg2(acpi_dbg2_header_t *dbg2_header, + int port_type, int port_subtype, + acpi_addr_t *address, uint32_t address_size, + const char *device_path); + +unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, + const struct device *dev, uint8_t access_size); +void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, + unsigned long (*acpi_fill_dmar)(unsigned long)); +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, + u16 segment, u64 bar); +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, + u64 bar, u64 limit); +unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, + u16 segment); +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, + u32 proximity_domain); +unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, + const char *device_name); +void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); +void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current); +void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); +unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, + u8 bus, u8 dev, u8 fn); +unsigned long acpi_create_dmar_ds_pci(unsigned long current, + u8 bus, u8 dev, u8 fn); +unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, + u8 enumeration_id, + u8 bus, u8 dev, u8 fn); +unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, + u8 enumeration_id, + u8 bus, u8 dev, u8 fn); +void acpi_write_hest(acpi_hest_t *hest, + unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)); + +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, + acpi_hest_esd_t *esd, u16 type, void *data, u16 len); + +/* For ACPI S3 support. */ +void acpi_resume(void *wake_vec); +void mainboard_suspend_resume(void); +void *acpi_find_wakeup_vector(void); + +/* ACPI_Sn assignments are defined to always equal the sleep state numbers */ +enum { + ACPI_S0 = 0, + ACPI_S1 = 1, + ACPI_S2 = 2, + ACPI_S3 = 3, + ACPI_S4 = 4, + ACPI_S5 = 5, +}; + +#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ + || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) +/* Given the provided PM1 control register return the ACPI sleep type. */ +static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt) +{ + switch (((pm1_cnt) & SLP_TYP) >> SLP_TYP_SHIFT) { + case SLP_TYP_S0: return ACPI_S0; + case SLP_TYP_S1: return ACPI_S1; + case SLP_TYP_S3: return ACPI_S3; + case SLP_TYP_S4: return ACPI_S4; + case SLP_TYP_S5: return ACPI_S5; + } + return -1; +} +#endif + +/* Returns ACPI_Sx values. */ +int acpi_get_sleep_type(void); + +/* Read and clear GPE status */ +int acpi_get_gpe(int gpe); + +static inline int acpi_s3_resume_allowed(void) +{ + return CONFIG(HAVE_ACPI_RESUME); +} + +#if CONFIG(HAVE_ACPI_RESUME) + +#if ENV_ROMSTAGE_OR_BEFORE +static inline int acpi_is_wakeup_s3(void) +{ + return (acpi_get_sleep_type() == ACPI_S3); +} +#else +int acpi_is_wakeup(void); +int acpi_is_wakeup_s3(void); +int acpi_is_wakeup_s4(void); +#endif + +#else +static inline int acpi_is_wakeup(void) { return 0; } +static inline int acpi_is_wakeup_s3(void) { return 0; } +static inline int acpi_is_wakeup_s4(void) { return 0; } +#endif + +static inline uintptr_t acpi_align_current(uintptr_t current) +{ + return ALIGN_UP(current, 16); +} + +/* ACPI table revisions should match the revision of the ACPI spec + * supported. This function keeps the table versions synced. This could + * be made into a weak function if there is ever a need to override the + * coreboot default ACPI spec version supported. */ +int get_acpi_table_revision(enum acpi_tables table); + +#endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMC__) + +#endif /* __ASM_ACPI_H */ diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h new file mode 100644 index 0000000000..bc71e0264d --- /dev/null +++ b/src/include/acpi/acpi_device.h @@ -0,0 +1,513 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __ACPI_DEVICE_H +#define __ACPI_DEVICE_H + +#include +#include +#include + +enum acpi_dp_type { + ACPI_DP_TYPE_UNKNOWN, + ACPI_DP_TYPE_INTEGER, + ACPI_DP_TYPE_STRING, + ACPI_DP_TYPE_REFERENCE, + ACPI_DP_TYPE_TABLE, + ACPI_DP_TYPE_ARRAY, + ACPI_DP_TYPE_CHILD, +}; + +struct acpi_dp { + enum acpi_dp_type type; + const char *name; + struct acpi_dp *next; + union { + struct acpi_dp *child; + struct acpi_dp *array; + }; + union { + uint64_t integer; + const char *string; + }; +}; + +#define ACPI_DESCRIPTOR_LARGE (1 << 7) +#define ACPI_DESCRIPTOR_INTERRUPT (ACPI_DESCRIPTOR_LARGE | 9) +#define ACPI_DESCRIPTOR_GPIO (ACPI_DESCRIPTOR_LARGE | 12) +#define ACPI_DESCRIPTOR_SERIAL_BUS (ACPI_DESCRIPTOR_LARGE | 14) + +/* + * PRP0001 is a special DT namespace link device ID. It provides a means to use + * existing DT-compatible device identification in ACPI. When this _HID is used + * by an ACPI device, the ACPI subsystem in OS looks up "compatible" property in + * device object's _DSD and will use the value of that property to identify the + * corresponding device in analogy with the original DT device identification + * algorithm. + * More details can be found in Linux kernel documentation: + * Documentation/acpi/enumeration.txt + */ +#define ACPI_DT_NAMESPACE_HID "PRP0001" + +struct device; +const char *acpi_device_name(const struct device *dev); +const char *acpi_device_hid(const struct device *dev); +uint32_t acpi_device_uid(const struct device *dev); +const char *acpi_device_path(const struct device *dev); +const char *acpi_device_scope(const struct device *dev); +const char *acpi_device_path_join(const struct device *dev, const char *name); +int acpi_device_status(const struct device *dev); +void acpi_device_write_uid(const struct device *dev); + +/* + * ACPI Descriptor for extended Interrupt() + */ + +enum acpi_irq_mode { + ACPI_IRQ_EDGE_TRIGGERED, + ACPI_IRQ_LEVEL_TRIGGERED +}; + +enum acpi_irq_polarity { + ACPI_IRQ_ACTIVE_LOW, + ACPI_IRQ_ACTIVE_HIGH, + ACPI_IRQ_ACTIVE_BOTH +}; + +enum acpi_irq_shared { + ACPI_IRQ_EXCLUSIVE, + ACPI_IRQ_SHARED +}; + +enum acpi_irq_wake { + ACPI_IRQ_NO_WAKE, + ACPI_IRQ_WAKE +}; + +struct acpi_irq { + unsigned int pin; + enum acpi_irq_mode mode; + enum acpi_irq_polarity polarity; + enum acpi_irq_shared shared; + enum acpi_irq_wake wake; +}; + +#define ACPI_IRQ_CFG(_pin, _mode, _pol, _shared, _wake) { \ + .pin = (_pin), \ + .mode = (_mode), \ + .polarity = (_pol), \ + .shared = (_shared), \ + .wake = (_wake) } + +#define ACPI_IRQ_EDGE_LOW(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ + ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_NO_WAKE) + +#define ACPI_IRQ_EDGE_HIGH(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ + ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_NO_WAKE) + +#define ACPI_IRQ_LEVEL_LOW(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ + ACPI_IRQ_SHARED, ACPI_IRQ_NO_WAKE) + +#define ACPI_IRQ_LEVEL_HIGH(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ + ACPI_IRQ_SHARED, ACPI_IRQ_NO_WAKE) + +#define ACPI_IRQ_WAKE_EDGE_LOW(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ + ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_WAKE) + +#define ACPI_IRQ_WAKE_EDGE_HIGH(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_EDGE_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ + ACPI_IRQ_EXCLUSIVE, ACPI_IRQ_WAKE) + +#define ACPI_IRQ_WAKE_LEVEL_LOW(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_LOW, \ + ACPI_IRQ_SHARED, ACPI_IRQ_WAKE) + +#define ACPI_IRQ_WAKE_LEVEL_HIGH(x) \ + ACPI_IRQ_CFG((x), ACPI_IRQ_LEVEL_TRIGGERED, ACPI_IRQ_ACTIVE_HIGH, \ + ACPI_IRQ_SHARED, ACPI_IRQ_WAKE) + +/* Write extended Interrupt() descriptor to SSDT AML output */ +void acpi_device_write_interrupt(const struct acpi_irq *irq); + +/* + * ACPI Descriptors for GpioIo() and GpioInterrupt() + */ + +enum acpi_gpio_type { + ACPI_GPIO_TYPE_INTERRUPT, + ACPI_GPIO_TYPE_IO +}; + +enum acpi_gpio_pull { + ACPI_GPIO_PULL_DEFAULT, + ACPI_GPIO_PULL_UP, + ACPI_GPIO_PULL_DOWN, + ACPI_GPIO_PULL_NONE +}; + +enum acpi_gpio_io_restrict { + ACPI_GPIO_IO_RESTRICT_NONE, + ACPI_GPIO_IO_RESTRICT_INPUT, + ACPI_GPIO_IO_RESTRICT_OUTPUT, + ACPI_GPIO_IO_RESTRICT_PRESERVE +}; + +enum acpi_gpio_polarity { + ACPI_GPIO_ACTIVE_HIGH = 0, + ACPI_GPIO_ACTIVE_LOW = 1, +}; + +#define ACPI_GPIO_REVISION_ID 1 +#define ACPI_GPIO_MAX_PINS 8 + +struct acpi_gpio { + int pin_count; + uint16_t pins[ACPI_GPIO_MAX_PINS]; + + enum acpi_gpio_type type; + enum acpi_gpio_pull pull; + const char *resource; + + /* GpioInt */ + uint16_t interrupt_debounce_timeout; /* 1/100 ms */ + struct acpi_irq irq; + + /* GpioIo */ + uint16_t output_drive_strength; /* 1/100 mA */ + int io_shared; + enum acpi_gpio_io_restrict io_restrict; + enum acpi_gpio_polarity polarity; +}; + +/* Basic output GPIO with default pull settings */ +#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) { \ + .type = ACPI_GPIO_TYPE_IO, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ + .polarity = ACPI_GPIO_ACTIVE_HIGH, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) { \ + .type = ACPI_GPIO_TYPE_IO, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ + .polarity = ACPI_GPIO_ACTIVE_LOW, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Basic input GPIO with default pull settings */ +#define ACPI_GPIO_INPUT_ACTIVE_HIGH(gpio) { \ + .type = ACPI_GPIO_TYPE_IO, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .io_restrict = ACPI_GPIO_IO_RESTRICT_INPUT, \ + .polarity = ACPI_GPIO_ACTIVE_HIGH, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +#define ACPI_GPIO_INPUT_ACTIVE_LOW(gpio) { \ + .type = ACPI_GPIO_TYPE_IO, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .io_restrict = ACPI_GPIO_IO_RESTRICT_INPUT, \ + .polarity = ACPI_GPIO_ACTIVE_LOW, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Edge Triggered Active High GPIO interrupt */ +#define ACPI_GPIO_IRQ_EDGE_HIGH(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Edge Triggered Active Low GPIO interrupt */ +#define ACPI_GPIO_IRQ_EDGE_LOW(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Edge Triggered Active Both GPIO interrupt */ +#define ACPI_GPIO_IRQ_EDGE_BOTH(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_BOTH, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Edge Triggered Active High GPIO interrupt with wake */ +#define ACPI_GPIO_IRQ_EDGE_HIGH_WAKE(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ + .irq.wake = ACPI_IRQ_WAKE, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Edge Triggered Active Low GPIO interrupt with wake */ +#define ACPI_GPIO_IRQ_EDGE_LOW_WAKE(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ + .irq.wake = ACPI_IRQ_WAKE, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Edge Triggered Active Both GPIO interrupt with wake */ +#define ACPI_GPIO_IRQ_EDGE_BOTH_WAKE(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_BOTH, \ + .irq.wake = ACPI_IRQ_WAKE, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Level Triggered Active High GPIO interrupt */ +#define ACPI_GPIO_IRQ_LEVEL_HIGH(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Level Triggered Active Low GPIO interrupt */ +#define ACPI_GPIO_IRQ_LEVEL_LOW(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Level Triggered Active High GPIO interrupt with wake */ +#define ACPI_GPIO_IRQ_LEVEL_HIGH_WAKE(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ + .irq.wake = ACPI_IRQ_WAKE, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Level Triggered Active Low GPIO interrupt with wake */ +#define ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(gpio) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ + .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ + .irq.wake = ACPI_IRQ_WAKE, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +/* Write GpioIo() or GpioInt() descriptor to SSDT AML output */ +void acpi_device_write_gpio(const struct acpi_gpio *gpio); + +/* + * ACPI Descriptors for Serial Bus interfaces + */ + +#define ACPI_SERIAL_BUS_TYPE_I2C 1 +#define ACPI_SERIAL_BUS_TYPE_SPI 2 +#define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */ +#define ACPI_I2C_TYPE_SPECIFIC_REVISION_ID 1 +#define ACPI_SPI_SERIAL_BUS_REVISION_ID 1 +#define ACPI_SPI_TYPE_SPECIFIC_REVISION_ID 1 + +/* + * ACPI I2C Bus + */ + +struct acpi_i2c { + /* I2C Address */ + uint16_t address; + /* 7 or 10 bit Address Mode */ + enum i2c_address_mode mode_10bit; + /* I2C Bus Speed in Hz */ + enum i2c_speed speed; + /* Reference to I2C controller */ + const char *resource; +}; + +/* Write I2cSerialBus() descriptor to SSDT AML output */ +void acpi_device_write_i2c(const struct acpi_i2c *i2c); + +/* + * ACPI SPI Bus + */ + +struct acpi_spi { + /* Device selection */ + uint16_t device_select; + /* Device selection line is active high or low */ + enum spi_polarity device_select_polarity; + /* 3 or 4 wire SPI connection */ + enum spi_wire_mode wire_mode; + /* Connection speed in HZ */ + unsigned int speed; + /* Size in bits of smallest transfer unit */ + u8 data_bit_length; + /* Phase of clock pulse on which to capture data */ + enum spi_clock_phase clock_phase; + /* Indicate if clock is high or low during first phase */ + enum spi_polarity clock_polarity; + /* Reference to SPI controller */ + const char *resource; +}; + +/* Write SPI Bus descriptor to SSDT AML output */ +void acpi_device_write_spi(const struct acpi_spi *spi); + +/* GPIO/timing information for the power on/off sequences */ +struct acpi_power_res_params { + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio *reset_gpio; + /* Delay to be inserted after device is taken out of reset. + * (_ON method delay) + */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. + * (_OFF method delay) + */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio *enable_gpio; + /* Delay to be inserted after device is enabled. + * (_ON method delay) + */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. + * (_OFF method delay) + */ + unsigned int enable_off_delay_ms; + /* GPIO used to stop operation of device. */ + struct acpi_gpio *stop_gpio; + /* Delay to be inserted after disabling stop. + * (_ON method delay) + */ + unsigned int stop_delay_ms; + /* Delay to be inserted after enabling stop. + * (_OFF method delay) + */ + unsigned int stop_off_delay_ms; +}; + +/* + * Add a basic PowerResource block for a device that includes + * GPIOs to control enable, reset and stop operation of the device. Each + * GPIO is optional, but at least one must be provided. + * + * Reset - Put the device into / take the device out of reset. + * Enable - Enable / disable power to device. + * Stop - Stop / start operation of device. + */ +void acpi_device_add_power_res(const struct acpi_power_res_params *params); + +/* + * Writing Device Properties objects via _DSD + * + * http://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf + * http://uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.pdf + * + * The Device Property Hierarchy can be multiple levels deep with multiple + * children possible in each level. In order to support this flexibility + * the device property hierarchy must be built up before being written out. + * + * For example: + * + * // Child table with string and integer + * struct acpi_dp *child = acpi_dp_new_table("CHLD"); + * acpi_dp_add_string(child, "childstring", "CHILD"); + * acpi_dp_add_integer(child, "childint", 100); + * + * // _DSD table with integer and gpio and child pointer + * struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + * acpi_dp_add_integer(dsd, "number1", 1); + * acpi_dp_add_gpio(dsd, "gpio", "\_SB.PCI0.GPIO", 0, 0, 1); + * acpi_dp_add_child(dsd, "child", child); + * + * // Write entries into SSDT and clean up resources + * acpi_dp_write(dsd); + * + * Name(_DSD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "gpio", Package() { \_SB.PCI0.GPIO, 0, 0, 0 } } + * Package() { "number1", 1 } + * } + * ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") + * Package() { + * Package() { "child", CHLD } + * } + * } + * Name(CHLD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "childstring", "CHILD" } + * Package() { "childint", 100 } + * } + * } + */ + +/* Start a new Device Property table with provided ACPI reference */ +struct acpi_dp *acpi_dp_new_table(const char *ref); + +/* Add integer Device Property */ +struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, + uint64_t value); + +/* Add string Device Property */ +struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, + const char *string); + +/* Add ACPI reference Device Property */ +struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, + const char *reference); + +/* Add an array of Device Properties */ +struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array); + +/* Add an array of integers Device Property */ +struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, + const uint64_t *array, int len); + +/* Add a GPIO binding Device Property */ +struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + int active_low); + +/* Add a child table of Device Properties */ +struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, + struct acpi_dp *child); + +/* Add a list of Device Properties, returns the number of properties added */ +size_t acpi_dp_add_property_list(struct acpi_dp *dp, + const struct acpi_dp *property_list, + size_t property_count); + +/* Write Device Property hierarchy and clean up resources */ +void acpi_dp_write(struct acpi_dp *table); + +/* + * Helper function to write a PCI device with _ADR object defined. + * + * IMPORTANT: Scope of a device created in SSDT cannot be used to add ACPI nodes under that + * scope in DSDT. So, if there are any references to this PCI device scope required from static + * asl files, do not use this function and instead add the device to DSDT as well. + */ +void acpi_device_write_pci_dev(const struct device *dev); + +#endif diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h new file mode 100644 index 0000000000..83abfb63dc --- /dev/null +++ b/src/include/acpi/acpi_ivrs.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * AMD I/O Virtualization Technology (IOMMU) + * Specification 48882-Rev 2.62-February 2015 + * + * from http://www.uefi.org/acpi + * I/O Virtualization Reporting Structure (IVRS) + */ + +#ifndef __ARCH_ACPI_IVRS_H +#define __ARCH_ACPI_IVRS_H + +/* I/O Virtualization Reporting Structure (IVRS) */ +#define IVHD_BLOCK_TYPE_LEGACY__FIXED 0x10 +#define IVHD_BLOCK_TYPE_FULL__FIXED 0x11 +#define IVHD_BLOCK_TYPE_FULL__ACPI_HID 0x40 + +/* IVRS Revision Field */ +#define IVRS_FORMAT_FIXED 0x01 /* Type 10h & 11h only */ +#define IVRS_FORMAT_MIXED 0x02 /* Type 10h, 11h, & 40h */ + +/* IVRS IVinfo Field */ +/* ATS response address range reserved */ +#define IVINFO_HT_ATS_RESERVED (1 << 22) + +/* Virtual Address size - All other values are reserved */ +#define IVINFO_VA_SIZE_32_BITS (0x20 << 15) +#define IVINFO_VA_SIZE_40_BITS (0x28 << 15) +#define IVINFO_VA_SIZE_48_BITS (0x30 << 15) +#define IVINFO_VA_SIZE_64_BITS (0x40 << 15) + +/* Physical Address size - All other values are reserved */ +#define IVINFO_PA_SIZE_40_BITS (0x28 << 8) +#define IVINFO_PA_SIZE_48_BITS (0x30 << 8) +#define IVINFO_PA_SIZE_52_BITS (0x34 << 8) + +/* Guest Virtual Address size - All other values are reserved */ +#define IVINFO_GVA_SIZE_48_BITS (0x02 << 5) + +/* Extended Feature Support */ +#define IVINFO_EFR_SUPPORTED 0x01 + +/* IVHD Flags Field */ +#define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */ +#define IVHD_FLAG_PREF_SUP (1 << 6) /* Type 10h only */ +#define IVHD_FLAG_COHERENT (1 << 5) +#define IVHD_FLAG_IOTLB_SUP (1 << 4) +#define IVHD_FLAG_ISOC (1 << 3) +#define IVHD_FLAG_RES_PASS_PW (1 << 2) +#define IVHD_FLAG_PASS_PW (1 << 1) +#define IVHD_FLAG_HT_TUN_EN (1 << 0) + +/* IVHD IOMMU Info Field */ +#define IOMMU_INFO_UNIT_ID_SHIFT 8 + +/* IVHD IOMMU Feature Reporting Field */ +#define IOMMU_FEATURE_HATS_SHIFT 30 /* Type 10h only */ +#define IOMMU_FEATURE_GATS_SHIFT 28 /* Type 10h only */ +#define IOMMU_FEATURE_MSI_NUM_PPR_SHIFT 23 +#define IOMMU_FEATURE_PN_BANKS_SHIFT 17 +#define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13 +#define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */ + +#define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */ +#define IOMMU_FEATURE_GA_SUP (1 << 6) /* Type 10h only */ +#define IOMMU_FEATURE_IA_SUP (1 << 5) /* Type 10h only */ +#define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */ +#define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */ +#define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */ +#define IOMMU_FEATURE_GT_SUP (1 << 1) /* Type 10h only */ +#define IOMMU_FEATURE_NX_SUP (1 << 0) /* Type 10h only */ + +/* IVHD Device Entry Type Codes */ +#define IVHD_DEV_4_BYTE_ALL 0x01 +#define IVHD_DEV_4_BYTE_SELECT 0x02 +#define IVHD_DEV_4_BYTE_START_RANGE 0x03 +#define IVHD_DEV_4_BYTE_END_RANGE 0x04 +#define IVHD_DEV_8_BYTE_ALIAS_SELECT 0x42 +#define IVHD_DEV_8_BYTE_ALIAS_START_RANGE 0x43 +#define IVHD_DEV_8_BYTE_EXT_SELECT 0x46 +#define IVHD_DEV_8_BYTE_EXT_START_RANGE 0x47 +#define IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV 0x48 +#define IVHD_DEV_VARIABLE 0xF0 + +/* IVHD Device Table Entry (DTE) Settings */ +#define IVHD_DTE_LINT_1_PASS (1 << 7) +#define IVHD_DTE_LINT_0_PASS (1 << 6) +#define IVHD_DTE_SYS_MGT_TGT_ABT (0 << 4) +#define IVHD_DTE_SYS_MGT_NO_TRANS (1 << 4) +#define IVHD_DTE_SYS_MGT_INTX_NO_TRANS (2 << 4) +#define IVHD_DTE_SYS_MGT_TRANS (3 << 4) +#define IVHD_DTE_NMI_PASS (1 << 2) +#define IVHD_DTE_EXT_INT_PASS (1 << 1) +#define IVHD_DTE_INIT_PASS (1 << 0) + +/* IVHD Device Entry Extended DTE Setting Field */ +#define IVHD_DEV_EXT_ATS_DISABLE (1 << 31) + +/* IVHD Special Device Entry Variety Field */ +#define IVHD_SPECIAL_DEV_IOAPIC 0x01 +#define IVHD_SPECIAL_DEV_HPET 0x02 + +/* Device EntryType F0h UID Format */ +#define IVHD_UID_NOT_PRESENT 0x00 +#define IVHD_UID_INT 0x01 +#define IVHD_UID_STRING 0x02 + +/* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ +typedef struct ivrs_ivhd_generic { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; +} __packed ivrs_ivhd_generic_t; + +/* IVHD (I/O Virtualization Hardware Definition Block) 8-byte entries */ +typedef struct ivrs_ivhd_alias { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint8_t reserved1; + uint16_t source_dev_id; + uint8_t reserved2; +} __packed ivrs_ivhd_alias_t; + +typedef struct ivrs_ivhd_extended { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint32_t extended_dte_setting; +} __packed ivrs_ivhd_extended_t; + +typedef struct ivrs_ivhd_special { + uint8_t type; + uint16_t reserved; + uint8_t dte_setting; + uint8_t handle; + uint16_t source_dev_id; + uint8_t variety; +} __packed ivrs_ivhd_special_t; + +#endif diff --git a/src/include/acpi/acpi_pld.h b/src/include/acpi/acpi_pld.h new file mode 100644 index 0000000000..944eb3154a --- /dev/null +++ b/src/include/acpi/acpi_pld.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __ACPI_PLD_H +#define __ACPI_PLD_H + +#include +#include + +enum acpi_pld_panel { + PLD_PANEL_TOP, + PLD_PANEL_BOTTOM, + PLD_PANEL_LEFT, + PLD_PANEL_RIGHT, + PLD_PANEL_FRONT, + PLD_PANEL_BACK, + PLD_PANEL_UNKNOWN +}; + +enum acpi_pld_vertical_position { + PLD_VERTICAL_POSITION_UPPER, + PLD_VERTICAL_POSITION_CENTER, + PLD_VERTICAL_POSITION_LOWER +}; + +/* + * The ACPI spec 6.2A does not define the horizontal position field. + * These values are taken from the IASL compiler: + * https://github.com/acpica/acpica/blob/master/source/components/utilities/utglobal.c#L321 + */ + +enum acpi_pld_horizontal_position { + PLD_HORIZONTAL_POSITION_LEFT, + PLD_HORIZONTAL_POSITION_CENTER, + PLD_HORIZONTAL_POSITION_RIGHT +}; + +enum acpi_pld_shape { + PLD_SHAPE_ROUND, + PLD_SHAPE_OVAL, + PLD_SHAPE_SQUARE, + PLD_SHAPE_VERTICAL_RECTANGLE, + PLD_SHAPE_HORIZONTAL_RECTANGLE, + PLD_SHAPE_VERTICAL_TRAPEZOID, + PLD_SHAPE_HORIZONTAL_TRAPEZOID, + PLD_SHAPE_UNKNOWN, + PLD_SHAPE_CHAMFERED +}; + +enum acpi_pld_orientation { + PLD_ORIENTATION_HORIZONTAL, + PLD_ORIENTATION_VERTICAL, +}; + +enum acpi_pld_rotate { + PLD_ROTATE_0, + PLD_ROTATE_45, + PLD_ROTATE_90, + PLD_ROTATE_135, + PLD_ROTATE_180, + PLD_ROTATE_225, + PLD_ROTATE_270, + PLD_ROTATE_315 +}; + +#define ACPI_PLD_GROUP(__token, __position) \ + { \ + .token = __token, \ + .position = __position, \ + } + +struct acpi_pld_group { + uint8_t token; + uint8_t position; +}; + +struct acpi_pld { + /* Color field can be explicitly ignored */ + bool ignore_color; + uint8_t color_red; + uint8_t color_blue; + uint8_t color_green; + + /* Port characteristics */ + bool visible; /* Can be seen by the user */ + bool lid; /* Port is on lid of device */ + bool dock; /* Port is in a docking station */ + bool bay; /* Port is in a bay */ + bool ejectable; /* Device is ejectable, has _EJx objects */ + bool ejectable_ospm; /* Device needs OSPM to eject */ + uint16_t width; /* Width in mm */ + uint16_t height; /* Height in mm */ + uint16_t vertical_offset; + uint16_t horizontal_offset; + enum acpi_pld_panel panel; + enum acpi_pld_horizontal_position horizontal_position; + enum acpi_pld_vertical_position vertical_position; + enum acpi_pld_shape shape; + enum acpi_pld_rotate rotation; + + /* Port grouping */ + enum acpi_pld_orientation orientation; + struct acpi_pld_group group; + uint8_t draw_order; + uint8_t cabinet_number; + uint8_t card_cage_number; + + /* Set if this PLD defines a reference shape */ + bool reference_shape; +}; + +/* Fill out PLD structure with defaults based on USB port type */ +int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, + struct acpi_pld_group *group); + +/* Turn PLD structure into a 20 byte ACPI buffer */ +int acpi_pld_to_buffer(const struct acpi_pld *pld, uint8_t *buf, int buf_len); + +#endif diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h new file mode 100644 index 0000000000..a3c4777afb --- /dev/null +++ b/src/include/acpi/acpigen.h @@ -0,0 +1,490 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef LIBACPI_H +#define LIBACPI_H + +#include +#include +#include +#include +#include + +/* Values that can be returned for ACPI Device _STA method */ +#define ACPI_STATUS_DEVICE_PRESENT (1 << 0) +#define ACPI_STATUS_DEVICE_ENABLED (1 << 1) +#define ACPI_STATUS_DEVICE_SHOW_IN_UI (1 << 2) +#define ACPI_STATUS_DEVICE_STATE_OK (1 << 3) + +#define ACPI_STATUS_DEVICE_ALL_OFF 0 +#define ACPI_STATUS_DEVICE_ALL_ON (ACPI_STATUS_DEVICE_PRESENT |\ + ACPI_STATUS_DEVICE_ENABLED |\ + ACPI_STATUS_DEVICE_SHOW_IN_UI |\ + ACPI_STATUS_DEVICE_STATE_OK) +#define ACPI_STATUS_DEVICE_HIDDEN_ON (ACPI_STATUS_DEVICE_PRESENT |\ + ACPI_STATUS_DEVICE_ENABLED |\ + ACPI_STATUS_DEVICE_STATE_OK) + +/* ACPI Op/Prefix Codes */ +enum { + ZERO_OP = 0x00, + ONE_OP = 0x01, + ALIAS_OP = 0x06, + NAME_OP = 0x08, + BYTE_PREFIX = 0x0A, + WORD_PREFIX = 0x0B, + DWORD_PREFIX = 0x0C, + STRING_PREFIX = 0x0D, + QWORD_PREFIX = 0x0E, + SCOPE_OP = 0x10, + BUFFER_OP = 0x11, + PACKAGE_OP = 0x12, + VARIABLE_PACKAGE_OP = 0x13, + METHOD_OP = 0x14, + EXTERNAL_OP = 0x15, + DUAL_NAME_PREFIX = 0x2E, + MULTI_NAME_PREFIX = 0x2F, + EXT_OP_PREFIX = 0x5B, + MUTEX_OP = 0x01, + EVENT_OP = 0x01, + SF_RIGHT_OP = 0x10, + SF_LEFT_OP = 0x11, + COND_REFOF_OP = 0x12, + CREATEFIELD_OP = 0x13, + LOAD_TABLE_OP = 0x1f, + LOAD_OP = 0x20, + STALL_OP = 0x21, + SLEEP_OP = 0x22, + ACQUIRE_OP = 0x23, + SIGNAL_OP = 0x24, + WAIT_OP = 0x25, + RST_OP = 0x26, + RELEASE_OP = 0x27, + FROM_BCD_OP = 0x28, + TO_BCD_OP = 0x29, + UNLOAD_OP = 0x2A, + REVISON_OP = 0x30, + DEBUG_OP = 0x31, + FATAL_OP = 0x32, + TIMER_OP = 0x33, + OPREGION_OP = 0x80, + FIELD_OP = 0x81, + DEVICE_OP = 0x82, + PROCESSOR_OP = 0x83, + POWER_RES_OP = 0x84, + THERMAL_ZONE_OP = 0x85, + INDEX_FIELD_OP = 0x86, + BANK_FIELD_OP = 0x87, + DATA_REGION_OP = 0x88, + ROOT_PREFIX = 0x5C, + PARENT_PREFIX = 0x5E, + LOCAL0_OP = 0x60, + LOCAL1_OP = 0x61, + LOCAL2_OP = 0x62, + LOCAL3_OP = 0x63, + LOCAL4_OP = 0x64, + LOCAL5_OP = 0x65, + LOCAL6_OP = 0x66, + LOCAL7_OP = 0x67, + ARG0_OP = 0x68, + ARG1_OP = 0x69, + ARG2_OP = 0x6A, + ARG3_OP = 0x6B, + ARG4_OP = 0x6C, + ARG5_OP = 0x6D, + ARG6_OP = 0x6E, + STORE_OP = 0x70, + REF_OF_OP = 0x71, + ADD_OP = 0x72, + CONCATENATE_OP = 0x73, + SUBTRACT_OP = 0x74, + INCREMENT_OP = 0x75, + DECREMENT_OP = 0x76, + MULTIPLY_OP = 0x77, + DIVIDE_OP = 0x78, + SHIFT_LEFT_OP = 0x79, + SHIFT_RIGHT_OP = 0x7A, + AND_OP = 0x7B, + NAND_OP = 0x7C, + OR_OP = 0x7D, + NOR_OP = 0x7E, + XOR_OP = 0x7F, + NOT_OP = 0x80, + FD_SHIFT_LEFT_BIT_OR = 0x81, + FD_SHIFT_RIGHT_BIT_OR = 0x82, + DEREF_OP = 0x83, + CONCATENATE_TEMP_OP = 0x84, + MOD_OP = 0x85, + NOTIFY_OP = 0x86, + SIZEOF_OP = 0x87, + INDEX_OP = 0x88, + MATCH_OP = 0x89, + CREATE_DWORD_OP = 0x8A, + CREATE_WORD_OP = 0x8B, + CREATE_BYTE_OP = 0x8C, + CREATE_BIT_OP = 0x8D, + OBJ_TYPE_OP = 0x8E, + CREATE_QWORD_OP = 0x8F, + LAND_OP = 0x90, + LOR_OP = 0x91, + LNOT_OP = 0x92, + LEQUAL_OP = 0x93, + LGREATER_OP = 0x94, + LLESS_OP = 0x95, + TO_BUFFER_OP = 0x96, + TO_DEC_STRING_OP = 0x97, + TO_HEX_STRING_OP = 0x98, + TO_INTEGER_OP = 0x99, + TO_STRING_OP = 0x9C, + CP_OBJ_OP = 0x9D, + MID_OP = 0x9E, + CONTINUE_OP = 0x9F, + IF_OP = 0xA0, + ELSE_OP = 0xA1, + WHILE_OP = 0xA2, + NOOP_OP = 0xA3, + RETURN_OP = 0xA4, + BREAK_OP = 0xA5, + COMMENT_OP = 0xA9, + BREAKPIONT_OP = 0xCC, + ONES_OP = 0xFF, +}; + +#define FIELDLIST_OFFSET(X) { .type = OFFSET, \ + .name = "",\ + .bits = X * 8, \ + } +#define FIELDLIST_NAMESTR(X, Y) { .type = NAME_STRING, \ + .name = X, \ + .bits = Y, \ + } + +#define FIELD_ANYACC 0 +#define FIELD_BYTEACC 1 +#define FIELD_WORDACC 2 +#define FIELD_DWORDACC 3 +#define FIELD_QWORDACC 4 +#define FIELD_BUFFERACC 5 +#define FIELD_NOLOCK (0<<4) +#define FIELD_LOCK (1<<4) +#define FIELD_PRESERVE (0<<5) +#define FIELD_WRITEASONES (1<<5) +#define FIELD_WRITEASZEROS (2<<5) + +enum field_type { + OFFSET, + NAME_STRING, + FIELD_TYPE_MAX, +}; + +struct fieldlist { + enum field_type type; + const char *name; + u32 bits; +}; + +#define OPREGION(rname, space, offset, len) {.name = rname, \ + .regionspace = space, \ + .regionoffset = offset, \ + .regionlen = len, \ + } + +enum region_space { + SYSTEMMEMORY, + SYSTEMIO, + PCI_CONFIG, + EMBEDDEDCONTROL, + SMBUS, + CMOS, + PCIBARTARGET, + IPMI, + GPIO_REGION, + GPSERIALBUS, + PCC, + FIXED_HARDWARE = 0x7F, + REGION_SPACE_MAX, +}; + +struct opregion { + const char *name; + enum region_space regionspace; + unsigned long regionoffset; + unsigned long regionlen; +}; + +#define DSM_UUID(DSM_UUID, DSM_CALLBACKS, DSM_COUNT, DSM_ARG) \ + { .uuid = DSM_UUID, \ + .callbacks = DSM_CALLBACKS, \ + .count = DSM_COUNT, \ + .arg = DSM_ARG, \ + } + +struct dsm_uuid { + const char *uuid; + void (**callbacks)(void *); + size_t count; + void *arg; +}; + +/*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ +enum cppc_fields { + CPPC_HIGHEST_PERF, /* can be DWORD */ + CPPC_NOMINAL_PERF, /* can be DWORD */ + CPPC_LOWEST_NONL_PERF, /* can be DWORD */ + CPPC_LOWEST_PERF, /* can be DWORD */ + CPPC_GUARANTEED_PERF, + CPPC_DESIRED_PERF, + CPPC_MIN_PERF, + CPPC_MAX_PERF, + CPPC_PERF_REDUCE_TOLERANCE, + CPPC_TIME_WINDOW, + CPPC_COUNTER_WRAP, /* can be DWORD */ + CPPC_REF_PERF_COUNTER, + CPPC_DELIVERED_PERF_COUNTER, + CPPC_PERF_LIMITED, + CPPC_ENABLE, /* can be System I/O */ + CPPC_MAX_FIELDS_VER_1, + CPPC_AUTO_SELECT = /* can be DWORD */ + CPPC_MAX_FIELDS_VER_1, + CPPC_AUTO_ACTIVITY_WINDOW, + CPPC_PERF_PREF, + CPPC_REF_PERF, /* can be DWORD */ + CPPC_MAX_FIELDS_VER_2, + CPPC_LOWEST_FREQ = /* can be DWORD */ + CPPC_MAX_FIELDS_VER_2, + CPPC_NOMINAL_FREQ, /* can be DWORD */ + CPPC_MAX_FIELDS_VER_3, +}; + +struct cppc_config { + u32 version; /* must be 1, 2, or 3 */ + /* + * The generic acpi_addr_t structure is being used, though + * anything besides PPC or FFIXED generally requires checking + * if the OS has advertised support for it (via _OSC). + * + * NOTE: some fields permit DWORDs to be used. If you + * provide a System Memory register with all zeros (which + * represents unsupported) then this will be used as-is. + * Otherwise, a System Memory register with a 32-bit + * width will be converted into a DWORD field (the value + * of which will be the value of 'addrl'. Any other use + * of System Memory register is currently undefined. + * (i.e., if you have an actual need for System Memory + * then you'll need to adjust this kludge). + */ + acpi_addr_t regs[CPPC_MAX_FIELDS_VER_3]; +}; + +void acpigen_write_return_integer(uint64_t arg); +void acpigen_write_return_string(const char *arg); +void acpigen_write_len_f(void); +void acpigen_pop_len(void); +void acpigen_set_current(char *curr); +char *acpigen_get_current(void); +char *acpigen_write_package(int nr_el); +void acpigen_write_zero(void); +void acpigen_write_one(void); +void acpigen_write_ones(void); +void acpigen_write_byte(unsigned int data); +void acpigen_emit_byte(unsigned char data); +void acpigen_emit_ext_op(uint8_t op); +void acpigen_emit_word(unsigned int data); +void acpigen_emit_dword(unsigned int data); +void acpigen_emit_stream(const char *data, int size); +void acpigen_emit_string(const char *string); +void acpigen_emit_namestring(const char *namepath); +void acpigen_emit_eisaid(const char *eisaid); +void acpigen_write_word(unsigned int data); +void acpigen_write_dword(unsigned int data); +void acpigen_write_qword(uint64_t data); +void acpigen_write_integer(uint64_t data); +void acpigen_write_string(const char *string); +void acpigen_write_name_unicode(const char *name, const char *string); +void acpigen_write_name(const char *name); +void acpigen_write_name_zero(const char *name); +void acpigen_write_name_one(const char *name); +void acpigen_write_name_string(const char *name, const char *string); +void acpigen_write_name_dword(const char *name, uint32_t val); +void acpigen_write_name_qword(const char *name, uint64_t val); +void acpigen_write_name_byte(const char *name, uint8_t val); +void acpigen_write_name_integer(const char *name, uint64_t val); +void acpigen_write_coreboot_hid(enum coreboot_acpi_ids id); +void acpigen_write_scope(const char *name); +void acpigen_write_method(const char *name, int nargs); +void acpigen_write_method_serialized(const char *name, int nargs); +void acpigen_write_device(const char *name); +void acpigen_write_PPC(u8 nr); +void acpigen_write_PPC_NVS(void); +void acpigen_write_empty_PCT(void); +void acpigen_write_empty_PTC(void); +void acpigen_write_PRW(u32 wake, u32 level); +void acpigen_write_STA(uint8_t status); +void acpigen_write_TPC(const char *gnvs_tpc_limit); +void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, + u32 busmLat, u32 control, u32 status); +typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord; +void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); +void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); +void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); +typedef enum { CSD_HW_ALL = 0xfe } CSD_coord; +void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, + u32 index); +void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +void acpigen_write_processor_package(const char *name, + unsigned int first_core, + unsigned int core_count); +void acpigen_write_processor_cnot(const unsigned int number_of_cores); +void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); +void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); +void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); +void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); +void acpigen_write_register_resource(const acpi_addr_t *addr); +void acpigen_write_resourcetemplate_header(void); +void acpigen_write_resourcetemplate_footer(void); +void acpigen_write_mainboard_resource_template(void); +void acpigen_write_mainboard_resources(const char *scope, const char *name); +void acpigen_write_irq(u16 mask); +void acpigen_write_uuid(const char *uuid); +void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, + const char * const dev_states[], size_t dev_states_count); +void acpigen_write_sleep(uint64_t sleep_ms); +void acpigen_write_store(void); +void acpigen_write_store_ops(uint8_t src, uint8_t dst); +void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst); +void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_not(uint8_t arg, uint8_t res); +void acpigen_write_debug_string(const char *str); +void acpigen_write_debug_integer(uint64_t val); +void acpigen_write_debug_op(uint8_t op); +void acpigen_write_if(void); +void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); +void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); +void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); +void acpigen_write_else(void); +void acpigen_write_to_buffer(uint8_t src, uint8_t dst); +void acpigen_write_to_integer(uint8_t src, uint8_t dst); +void acpigen_write_byte_buffer(uint8_t *arr, size_t size); +void acpigen_write_return_byte_buffer(uint8_t *arr, size_t size); +void acpigen_write_return_singleton_buffer(uint8_t arg); +void acpigen_write_return_byte(uint8_t arg); +void acpigen_write_upc(enum acpi_upc_type type); +void acpigen_write_pld(const struct acpi_pld *pld); +void acpigen_write_ADR(uint64_t adr); +void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); +void acpigen_write_ADR_pci_device(const struct device *dev); +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + */ +void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *), + size_t count, void *arg); +void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count); + +/* + * Generate ACPI AML code for _CPC (Continuous Performance Control). + * Execute the package function once to create a global table, then + * execute the method function within each processor object to + * create a method that points to the global table. + */ +void acpigen_write_CPPC_package(const struct cppc_config *config); +void acpigen_write_CPPC_method(void); + +/* + * Generate ACPI AML code for _ROM method. + * This function takes as input ROM data and ROM length. + * The ROM length has to be multiple of 4096 and has to be less + * than the current implementation limit of 0x40000. + */ +void acpigen_write_rom(void *bios, const size_t length); +/* + * Generate ACPI AML code for OperationRegion + * This function takes input region name, region space, region offset & region + * length. + */ +void acpigen_write_opregion(struct opregion *opreg); +/* + * Generate ACPI AML code for Mutex + * This function takes mutex name and initial value. + */ +void acpigen_write_mutex(const char *name, const uint8_t flags); +/* + * Generate ACPI AML code for Acquire + * This function takes mutex name and privilege value. + */ +void acpigen_write_acquire(const char *name, const uint16_t val); +/* + * Generate ACPI AML code for Release + * This function takes mutex name. + */ +void acpigen_write_release(const char *name); +/* + * Generate ACPI AML code for Field + * This function takes input region name, fieldlist, count & flags. + */ +void acpigen_write_field(const char *name, const struct fieldlist *l, size_t count, + uint8_t flags); +/* + * Generate ACPI AML code for IndexField + * This function takes input index name, data name, fieldlist, count & flags. + */ +void acpigen_write_indexfield(const char *idx, const char *data, + struct fieldlist *l, size_t count, uint8_t flags); + +int get_cst_entries(acpi_cstate_t **); + +/* + * Soc-implemented functions for generating ACPI AML code for GPIO handling. All + * these functions are expected to use only Local5, Local6 and Local7 + * variables. If the functions call into another ACPI method, then there is no + * restriction on the use of Local variables. In case of get/read functions, + * return value is expected to be stored in Local0 variable. + * + * All functions return 0 on success and -1 on error. + */ + +/* Generate ACPI AML code to return Rx value of GPIO in Local0. */ +int acpigen_soc_read_rx_gpio(unsigned int gpio_num); + +/* Generate ACPI AML code to return Tx value of GPIO in Local0. */ +int acpigen_soc_get_tx_gpio(unsigned int gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 1. */ +int acpigen_soc_set_tx_gpio(unsigned int gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 0. */ +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num); + +/* + * Helper functions for enabling/disabling Tx GPIOs based on the GPIO + * polarity. These functions end up calling acpigen_soc_{set,clear}_tx_gpio to + * make callbacks into SoC acpigen code. + * + * Returns 0 on success and -1 on error. + */ +int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); +int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); + +/* + * Helper function for getting a RX GPIO value based on the GPIO polarity. + * The return value is stored in Local0 variable. + * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks + * into SoC acpigen code + */ +void acpigen_get_rx_gpio(struct acpi_gpio *gpio); + +/* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ +void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, + u16 range_min, u16 range_max, u16 translation, u16 length); +/* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */ +void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, + u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length); +/* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ +void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, + u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); + +#endif diff --git a/src/include/acpi/acpigen_dsm.h b/src/include/acpi/acpigen_dsm.h new file mode 100644 index 0000000000..c51c12b6e3 --- /dev/null +++ b/src/include/acpi/acpigen_dsm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __ARCH_ACPIGEN_DSM_H__ +#define __ARCH_ACPIGEN_DSM_H__ + +#include + +struct dsm_i2c_hid_config { + uint8_t hid_desc_reg_offset; +}; + +void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config); + +#endif /* __ARCH_ACPIGEN_DSM_H__ */ diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h new file mode 100644 index 0000000000..c0228bca16 --- /dev/null +++ b/src/include/acpi/acpigen_ps2_keybd.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __ACPIGEN_PS2_KEYBD_H__ +#define __ACPIGEN_PS2_KEYBD_H__ + +#include + +enum ps2_action_key { + PS2_KEY_ABSENT = 0, + PS2_KEY_BACK, + PS2_KEY_FORWARD, + PS2_KEY_REFRESH, + PS2_KEY_FULLSCREEN, + PS2_KEY_OVERVIEW, + PS2_KEY_BRIGHTNESS_DOWN, + PS2_KEY_BRIGHTNESS_UP, + PS2_KEY_VOL_MUTE, + PS2_KEY_VOL_DOWN, + PS2_KEY_VOL_UP, + PS2_KEY_SNAPSHOT, + PS2_KEY_PRIVACY_SCRN_TOGGLE, + PS2_KEY_KBD_BKLIGHT_DOWN, + PS2_KEY_KBD_BKLIGHT_UP, + PS2_KEY_PLAY_PAUSE, + PS2_KEY_NEXT_TRACK, + PS2_KEY_PREV_TRACK, +}; + +#define PS2_MIN_TOP_ROW_KEYS 10 +#define PS2_MAX_TOP_ROW_KEYS 15 + +void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, + enum ps2_action_key action_keys[], + bool can_send_function_keys, + bool has_numeric_keypad, bool has_scrnlock_key); + +#endif /* __ACPIGEN_PS2_KEYBD_H__ */ From 76cedd2c292352d7dbd45fab70ec272e476d0910 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 2 May 2020 10:24:23 -0700 Subject: [PATCH 1371/1463] acpi: Move ACPI table support out of arch/x86 (3/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- Documentation/Intel/SoC/soc.html | 2 +- Documentation/acpi/devicetree.md | 2 +- src/acpi/acpi.c | 6 +++--- src/acpi/acpi_device.c | 6 +++--- src/acpi/acpi_pld.c | 4 ++-- src/acpi/acpigen.c | 2 +- src/acpi/acpigen_dsm.c | 4 ++-- src/acpi/acpigen_ps2_keybd.c | 6 +++--- src/acpi/sata.c | 4 ++-- src/arch/x86/acpi/debug.asl | 2 +- src/arch/x86/acpi_bert_storage.c | 2 +- src/arch/x86/acpi_s3.c | 2 +- src/arch/x86/ebda.c | 2 +- src/arch/x86/include/arch/bert_storage.h | 2 +- src/arch/x86/tables.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/intel/common/common_init.c | 2 +- src/cpu/intel/haswell/acpi.c | 4 ++-- src/cpu/intel/haswell/haswell_init.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 2 +- src/cpu/intel/model_206ax/acpi.c | 4 ++-- src/cpu/intel/model_206ax/model_206ax_init.c | 2 +- src/cpu/intel/speedstep/acpi.c | 4 ++-- src/cpu/x86/backup_default_smm.c | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 2 +- src/device/pci_device.c | 2 +- src/device/pci_rom.c | 2 +- src/drivers/amd/agesa/heapmanager.c | 2 +- src/drivers/amd/agesa/romstage.c | 2 +- src/drivers/amd/agesa/state_machine.c | 2 +- src/drivers/crb/tis.c | 2 +- src/drivers/elog/elog.c | 2 +- src/drivers/generic/adau7002/adau7002.c | 4 ++-- src/drivers/generic/bayhub/chip.h | 2 +- src/drivers/generic/generic/chip.h | 2 +- src/drivers/generic/generic/generic.c | 4 ++-- src/drivers/generic/gpio_keys/chip.h | 2 +- src/drivers/generic/gpio_keys/gpio_keys.c | 4 ++-- src/drivers/generic/gpio_regulator/chip.h | 2 +- src/drivers/generic/gpio_regulator/gpio_regulator.c | 4 ++-- src/drivers/generic/max98357a/chip.h | 2 +- src/drivers/generic/max98357a/max98357a.c | 4 ++-- src/drivers/gfx/generic/chip.h | 2 +- src/drivers/gfx/generic/generic.c | 2 +- src/drivers/i2c/da7219/chip.h | 2 +- src/drivers/i2c/da7219/da7219.c | 6 +++--- src/drivers/i2c/designware/dw_i2c.c | 2 +- src/drivers/i2c/generic/chip.h | 2 +- src/drivers/i2c/generic/generic.c | 4 ++-- src/drivers/i2c/hid/hid.c | 2 +- src/drivers/i2c/max98373/max98373.c | 6 +++--- src/drivers/i2c/max98927/max98927.c | 6 +++--- src/drivers/i2c/nau8825/chip.h | 2 +- src/drivers/i2c/nau8825/nau8825.c | 6 +++--- src/drivers/i2c/rt1011/rt1011.c | 6 +++--- src/drivers/i2c/rt5663/chip.h | 2 +- src/drivers/i2c/rt5663/rt5663.c | 6 +++--- src/drivers/i2c/sx9310/chip.h | 2 +- src/drivers/i2c/sx9310/sx9310.c | 4 ++-- src/drivers/i2c/tpm/chip.c | 4 ++-- src/drivers/i2c/tpm/chip.h | 2 +- src/drivers/intel/fsp1_1/raminit.c | 2 +- src/drivers/intel/fsp1_1/ramstage.c | 2 +- src/drivers/intel/fsp1_1/romstage.c | 2 +- src/drivers/intel/gma/acpi.c | 4 ++-- src/drivers/intel/gma/intel_ddi.c | 2 +- src/drivers/intel/gma/opregion.c | 2 +- src/drivers/intel/ish/ish.c | 4 ++-- src/drivers/intel/mipi_camera/camera.c | 6 +++--- src/drivers/ipmi/ipmi_kcs_ops.c | 4 ++-- src/drivers/lenovo/wacom.c | 4 ++-- src/drivers/net/chip.h | 2 +- src/drivers/net/r8168.c | 4 ++-- src/drivers/pc80/pc/keyboard.c | 2 +- src/drivers/pc80/rtc/mc146818rtc.c | 2 +- src/drivers/pc80/tpm/tis.c | 6 +++--- src/drivers/spi/acpi/acpi.c | 4 ++-- src/drivers/spi/acpi/chip.h | 2 +- src/drivers/tpm/tpm.c | 2 +- src/drivers/usb/acpi/chip.h | 6 +++--- src/drivers/usb/acpi/usb_acpi.c | 6 +++--- src/drivers/wifi/generic.c | 4 ++-- src/ec/google/chromeec/ec_acpi.c | 8 ++++---- src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c | 4 ++-- src/ec/google/chromeec/smihandler.c | 2 +- src/ec/google/wilco/chip.c | 6 +++--- src/ec/google/wilco/smihandler.c | 2 +- src/ec/lenovo/h8/h8.c | 2 +- src/ec/lenovo/h8/ssdt.c | 2 +- src/include/acpi/acpi_pld.h | 2 +- src/include/acpi/acpigen.h | 6 +++--- src/include/device/azalia_device.h | 2 +- src/include/device/pci_rom.h | 2 +- src/lib/coreboot_table.c | 2 +- src/lib/hardwaremain.c | 2 +- src/lib/nhlt.c | 2 +- src/mainboard/51nb/x210/dsdt.asl | 2 +- src/mainboard/amd/gardenia/acpi/routing.asl | 2 +- src/mainboard/amd/gardenia/acpi/usb_oc.asl | 2 +- src/mainboard/amd/gardenia/dsdt.asl | 2 +- src/mainboard/amd/inagua/acpi/routing.asl | 2 +- src/mainboard/amd/inagua/acpi/usb_oc.asl | 2 +- src/mainboard/amd/inagua/acpi_tables.c | 2 +- src/mainboard/amd/inagua/dsdt.asl | 2 +- src/mainboard/amd/olivehill/acpi/routing.asl | 2 +- src/mainboard/amd/olivehill/acpi/usb_oc.asl | 2 +- src/mainboard/amd/olivehill/acpi_tables.c | 2 +- src/mainboard/amd/olivehill/dsdt.asl | 2 +- src/mainboard/amd/padmelon/dsdt.asl | 2 +- src/mainboard/amd/padmelon/mainboard.c | 2 +- src/mainboard/amd/parmer/acpi_tables.c | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/persimmon/acpi/routing.asl | 2 +- src/mainboard/amd/persimmon/acpi/usb_oc.asl | 2 +- src/mainboard/amd/persimmon/acpi_tables.c | 2 +- src/mainboard/amd/persimmon/dsdt.asl | 2 +- src/mainboard/amd/south_station/acpi/routing.asl | 2 +- src/mainboard/amd/south_station/acpi/usb_oc.asl | 2 +- src/mainboard/amd/south_station/acpi_tables.c | 2 +- src/mainboard/amd/south_station/dsdt.asl | 2 +- src/mainboard/amd/thatcher/acpi/cpstate.asl | 2 +- src/mainboard/amd/thatcher/acpi_tables.c | 2 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/amd/union_station/acpi/routing.asl | 2 +- src/mainboard/amd/union_station/acpi/usb_oc.asl | 2 +- src/mainboard/amd/union_station/acpi_tables.c | 2 +- src/mainboard/amd/union_station/dsdt.asl | 2 +- src/mainboard/aopen/dxplplusu/acpi_tables.c | 2 +- src/mainboard/aopen/dxplplusu/dsdt.asl | 2 +- src/mainboard/aopen/dxplplusu/fadt.c | 2 +- src/mainboard/apple/macbook21/dsdt.asl | 2 +- src/mainboard/apple/macbook21/mainboard.c | 2 +- src/mainboard/apple/macbookair4_2/dsdt.asl | 2 +- src/mainboard/asrock/b75pro3-m/dsdt.asl | 2 +- src/mainboard/asrock/b85m_pro4/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/acpi/routing.asl | 2 +- src/mainboard/asrock/e350m1/acpi/usb_oc.asl | 2 +- src/mainboard/asrock/e350m1/acpi_tables.c | 2 +- src/mainboard/asrock/e350m1/dsdt.asl | 2 +- src/mainboard/asrock/g41c-gs/cstates.c | 2 +- src/mainboard/asrock/g41c-gs/dsdt.asl | 2 +- src/mainboard/asrock/h110m/dsdt.asl | 2 +- src/mainboard/asrock/h81m-hds/dsdt.asl | 2 +- src/mainboard/asrock/imb-a180/acpi/routing.asl | 2 +- src/mainboard/asrock/imb-a180/acpi/usb_oc.asl | 2 +- src/mainboard/asrock/imb-a180/acpi_tables.c | 2 +- src/mainboard/asrock/imb-a180/dsdt.asl | 2 +- src/mainboard/asus/am1i-a/acpi_tables.c | 2 +- src/mainboard/asus/am1i-a/dsdt.asl | 2 +- src/mainboard/asus/f2a85-m/acpi/cpstate.asl | 2 +- src/mainboard/asus/f2a85-m/acpi_tables.c | 2 +- src/mainboard/asus/f2a85-m/dsdt.asl | 2 +- src/mainboard/asus/h61m-cs/dsdt.asl | 2 +- src/mainboard/asus/maximus_iv_gene-z/dsdt.asl | 2 +- src/mainboard/asus/p2b/acpi_tables.c | 2 +- src/mainboard/asus/p2b/dsdt.asl | 2 +- src/mainboard/asus/p5gc-mx/cstates.c | 2 +- src/mainboard/asus/p5gc-mx/dsdt.asl | 2 +- src/mainboard/asus/p5qc/cstates.c | 2 +- src/mainboard/asus/p5qc/dsdt.asl | 2 +- src/mainboard/asus/p5ql-em/acpi_tables.c | 2 +- src/mainboard/asus/p5ql-em/dsdt.asl | 2 +- src/mainboard/asus/p5qpl-am/cstates.c | 2 +- src/mainboard/asus/p5qpl-am/dsdt.asl | 2 +- src/mainboard/asus/p8h61-m_lx/dsdt.asl | 2 +- src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl | 2 +- src/mainboard/asus/p8h61-m_pro/dsdt.asl | 2 +- src/mainboard/asus/p8z77-m_pro/dsdt.asl | 2 +- src/mainboard/asus/p8z77-v_lx2/dsdt.asl | 2 +- src/mainboard/bap/ode_e20XX/acpi/routing.asl | 2 +- src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl | 2 +- src/mainboard/bap/ode_e20XX/acpi_tables.c | 2 +- src/mainboard/bap/ode_e20XX/dsdt.asl | 2 +- src/mainboard/bap/ode_e21XX/acpi/routing.asl | 2 +- src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl | 2 +- src/mainboard/bap/ode_e21XX/acpi_tables.c | 2 +- src/mainboard/bap/ode_e21XX/dsdt.asl | 2 +- src/mainboard/biostar/a68n_5200/acpi/routing.asl | 2 +- src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl | 2 +- src/mainboard/biostar/a68n_5200/acpi_tables.c | 2 +- src/mainboard/biostar/a68n_5200/dsdt.asl | 2 +- src/mainboard/biostar/am1ml/acpi/routing.asl | 2 +- src/mainboard/biostar/am1ml/acpi/usb_oc.asl | 2 +- src/mainboard/biostar/am1ml/acpi_tables.c | 2 +- src/mainboard/biostar/am1ml/dsdt.asl | 2 +- src/mainboard/compulab/intense_pc/dsdt.asl | 2 +- src/mainboard/elmex/pcm205400/acpi/routing.asl | 2 +- src/mainboard/elmex/pcm205400/acpi/usb_oc.asl | 2 +- src/mainboard/elmex/pcm205400/acpi_tables.c | 2 +- src/mainboard/elmex/pcm205400/dsdt.asl | 2 +- src/mainboard/emulation/qemu-i440fx/acpi_tables.c | 2 +- src/mainboard/emulation/qemu-i440fx/dsdt.asl | 2 +- src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 2 +- src/mainboard/emulation/qemu-q35/acpi_tables.c | 2 +- src/mainboard/emulation/qemu-q35/dsdt.asl | 2 +- src/mainboard/facebook/fbg1701/acpi_tables.c | 2 +- src/mainboard/facebook/fbg1701/dsdt.asl | 2 +- src/mainboard/facebook/monolith/dsdt.asl | 2 +- src/mainboard/foxconn/d41s/cstates.c | 2 +- src/mainboard/foxconn/d41s/dsdt.asl | 2 +- src/mainboard/foxconn/g41s-k/cstates.c | 2 +- src/mainboard/foxconn/g41s-k/dsdt.asl | 2 +- src/mainboard/getac/p470/acpi_tables.c | 2 +- src/mainboard/getac/p470/cstates.c | 2 +- src/mainboard/getac/p470/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c | 2 +- src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 2 +- src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-h61m-series/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo/acpi/routing.asl | 2 +- src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl | 2 +- src/mainboard/gizmosphere/gizmo/acpi_tables.c | 2 +- src/mainboard/gizmosphere/gizmo/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo2/acpi/routing.asl | 2 +- src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl | 2 +- src/mainboard/gizmosphere/gizmo2/acpi_tables.c | 2 +- src/mainboard/gizmosphere/gizmo2/dsdt.asl | 2 +- src/mainboard/google/auron/acpi_tables.c | 2 +- src/mainboard/google/auron/dsdt.asl | 2 +- src/mainboard/google/auron/ec.c | 2 +- src/mainboard/google/auron/smihandler.c | 2 +- src/mainboard/google/beltino/acpi_tables.c | 2 +- src/mainboard/google/beltino/dsdt.asl | 2 +- src/mainboard/google/beltino/mainboard.c | 2 +- src/mainboard/google/beltino/smihandler.c | 2 +- src/mainboard/google/butterfly/dsdt.asl | 2 +- src/mainboard/google/butterfly/early_init.c | 2 +- src/mainboard/google/butterfly/mainboard.c | 2 +- src/mainboard/google/cyan/acpi_tables.c | 2 +- src/mainboard/google/cyan/dsdt.asl | 2 +- src/mainboard/google/cyan/ec.c | 2 +- src/mainboard/google/cyan/smihandler.c | 2 +- src/mainboard/google/dedede/dsdt.asl | 2 +- src/mainboard/google/dedede/ec.c | 2 +- src/mainboard/google/dedede/mainboard.c | 2 +- src/mainboard/google/deltaur/chromeos.c | 2 +- src/mainboard/google/deltaur/dsdt.asl | 2 +- src/mainboard/google/deltaur/mainboard.c | 2 +- src/mainboard/google/deltaur/variants/baseboard/gpio.c | 2 +- src/mainboard/google/dragonegg/chromeos.c | 2 +- src/mainboard/google/dragonegg/dsdt.asl | 2 +- src/mainboard/google/dragonegg/ec.c | 2 +- src/mainboard/google/dragonegg/mainboard.c | 2 +- src/mainboard/google/drallion/chromeos.c | 2 +- src/mainboard/google/drallion/dsdt.asl | 2 +- src/mainboard/google/drallion/ramstage.c | 2 +- src/mainboard/google/eve/dsdt.asl | 2 +- src/mainboard/google/eve/ec.c | 2 +- src/mainboard/google/eve/mainboard.c | 2 +- src/mainboard/google/fizz/dsdt.asl | 2 +- src/mainboard/google/fizz/ec.c | 2 +- src/mainboard/google/fizz/mainboard.c | 2 +- src/mainboard/google/fizz/variants/karma/smihandler.c | 2 +- src/mainboard/google/glados/dsdt.asl | 2 +- src/mainboard/google/glados/ec.c | 2 +- src/mainboard/google/glados/mainboard.c | 2 +- src/mainboard/google/glados/smihandler.c | 2 +- src/mainboard/google/hatch/chromeos.c | 2 +- src/mainboard/google/hatch/dsdt.asl | 2 +- src/mainboard/google/hatch/ec.c | 2 +- src/mainboard/google/hatch/ramstage.c | 2 +- src/mainboard/google/hatch/variants/akemi/gpio.c | 2 +- src/mainboard/google/hatch/variants/baseboard/gpio.c | 2 +- src/mainboard/google/hatch/variants/dratini/gpio.c | 2 +- src/mainboard/google/hatch/variants/hatch/gpio.c | 2 +- src/mainboard/google/hatch/variants/helios/gpio.c | 2 +- src/mainboard/google/hatch/variants/jinlon/gpio.c | 2 +- src/mainboard/google/hatch/variants/kindred/gpio.c | 2 +- src/mainboard/google/hatch/variants/kohaku/gpio.c | 2 +- src/mainboard/google/hatch/variants/mushu/gpio.c | 2 +- src/mainboard/google/hatch/variants/nightfury/gpio.c | 2 +- src/mainboard/google/hatch/variants/palkia/gpio.c | 2 +- src/mainboard/google/hatch/variants/stryke/gpio.c | 2 +- src/mainboard/google/jecht/acpi_tables.c | 2 +- src/mainboard/google/jecht/dsdt.asl | 2 +- src/mainboard/google/jecht/mainboard.c | 2 +- src/mainboard/google/jecht/smihandler.c | 2 +- src/mainboard/google/kahlee/dsdt.asl | 2 +- src/mainboard/google/kahlee/ec.c | 2 +- src/mainboard/google/kahlee/mainboard.c | 2 +- src/mainboard/google/kahlee/smihandler.c | 2 +- .../variants/baseboard/include/baseboard/acpi/routing.asl | 2 +- src/mainboard/google/link/dsdt.asl | 2 +- src/mainboard/google/link/early_init.c | 2 +- src/mainboard/google/link/ec.c | 2 +- src/mainboard/google/link/mainboard.c | 2 +- src/mainboard/google/link/mainboard_smi.c | 2 +- src/mainboard/google/octopus/dsdt.asl | 2 +- src/mainboard/google/octopus/ec.c | 2 +- src/mainboard/google/octopus/mainboard.c | 2 +- src/mainboard/google/octopus/smihandler.c | 2 +- src/mainboard/google/octopus/variants/baseboard/gpio.c | 2 +- src/mainboard/google/octopus/variants/bobba/variant.c | 2 +- src/mainboard/google/octopus/variants/dood/variant.c | 2 +- src/mainboard/google/octopus/variants/garg/variant.c | 2 +- src/mainboard/google/parrot/acpi_tables.c | 2 +- src/mainboard/google/parrot/dsdt.asl | 2 +- src/mainboard/google/parrot/early_init.c | 2 +- src/mainboard/google/parrot/ec.c | 2 +- src/mainboard/google/parrot/mainboard.c | 2 +- src/mainboard/google/poppy/chromeos.c | 2 +- src/mainboard/google/poppy/dsdt.asl | 2 +- src/mainboard/google/poppy/ec.c | 2 +- src/mainboard/google/poppy/mainboard.c | 2 +- src/mainboard/google/poppy/variants/nami/smihandler.c | 2 +- src/mainboard/google/poppy/variants/nautilus/smihandler.c | 2 +- src/mainboard/google/poppy/variants/nocturne/ec.c | 2 +- src/mainboard/google/rambi/acpi_tables.c | 2 +- src/mainboard/google/rambi/dsdt.asl | 2 +- src/mainboard/google/rambi/ec.c | 2 +- src/mainboard/google/rambi/mainboard.c | 2 +- src/mainboard/google/rambi/mainboard_smi.c | 2 +- src/mainboard/google/reef/dsdt.asl | 2 +- src/mainboard/google/reef/ec.c | 2 +- src/mainboard/google/reef/mainboard.c | 2 +- src/mainboard/google/reef/smihandler.c | 2 +- src/mainboard/google/reef/variants/coral/gpio.c | 2 +- src/mainboard/google/sarien/chromeos.c | 2 +- src/mainboard/google/sarien/dsdt.asl | 2 +- src/mainboard/google/sarien/ramstage.c | 2 +- src/mainboard/google/slippy/acpi_tables.c | 2 +- src/mainboard/google/slippy/dsdt.asl | 2 +- src/mainboard/google/slippy/ec.c | 2 +- src/mainboard/google/slippy/mainboard.c | 2 +- src/mainboard/google/slippy/smihandler.c | 2 +- src/mainboard/google/stout/acpi_tables.c | 2 +- src/mainboard/google/stout/dsdt.asl | 4 ++-- src/mainboard/google/stout/early_init.c | 2 +- src/mainboard/google/stout/ec.c | 2 +- src/mainboard/google/stout/mainboard.c | 2 +- src/mainboard/google/volteer/dsdt.asl | 2 +- src/mainboard/google/volteer/ec.c | 2 +- src/mainboard/google/volteer/mainboard.c | 2 +- src/mainboard/hp/abm/acpi/routing.asl | 2 +- src/mainboard/hp/abm/acpi/usb_oc.asl | 2 +- src/mainboard/hp/abm/acpi_tables.c | 2 +- src/mainboard/hp/abm/dsdt.asl | 2 +- src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl | 2 +- src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 2 +- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/mainboard/hp/snb_ivb_laptops/dsdt.asl | 2 +- src/mainboard/hp/z220_sff_workstation/dsdt.asl | 2 +- src/mainboard/ibase/mb899/cstates.c | 2 +- src/mainboard/ibase/mb899/dsdt.asl | 2 +- src/mainboard/intel/apollolake_rvp/dsdt.asl | 2 +- src/mainboard/intel/baskingridge/acpi_tables.c | 2 +- src/mainboard/intel/baskingridge/dsdt.asl | 2 +- src/mainboard/intel/baskingridge/mainboard.c | 2 +- src/mainboard/intel/baskingridge/mainboard_smi.c | 2 +- src/mainboard/intel/cannonlake_rvp/chromeos.c | 2 +- src/mainboard/intel/cannonlake_rvp/dsdt.asl | 2 +- src/mainboard/intel/cannonlake_rvp/mainboard.c | 2 +- src/mainboard/intel/cannonlake_rvp/smihandler.c | 2 +- src/mainboard/intel/cedarisland_crb/dsdt.asl | 2 +- src/mainboard/intel/coffeelake_rvp/chromeos.c | 2 +- src/mainboard/intel/coffeelake_rvp/dsdt.asl | 2 +- src/mainboard/intel/coffeelake_rvp/mainboard.c | 2 +- src/mainboard/intel/d510mo/cstates.c | 2 +- src/mainboard/intel/d510mo/dsdt.asl | 2 +- src/mainboard/intel/d945gclf/cstates.c | 2 +- src/mainboard/intel/d945gclf/dsdt.asl | 2 +- src/mainboard/intel/dcp847ske/dsdt.asl | 2 +- src/mainboard/intel/dg41wv/cstates.c | 2 +- src/mainboard/intel/dg41wv/dsdt.asl | 2 +- src/mainboard/intel/dg43gt/cstates.c | 2 +- src/mainboard/intel/dg43gt/dsdt.asl | 2 +- src/mainboard/intel/emeraldlake2/acpi_tables.c | 2 +- src/mainboard/intel/emeraldlake2/dsdt.asl | 2 +- src/mainboard/intel/emeraldlake2/ec.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/intel/emeraldlake2/smihandler.c | 2 +- src/mainboard/intel/galileo/dsdt.asl | 2 +- src/mainboard/intel/glkrvp/dsdt.asl | 2 +- src/mainboard/intel/glkrvp/ec.c | 2 +- src/mainboard/intel/glkrvp/mainboard.c | 2 +- src/mainboard/intel/glkrvp/smihandler.c | 2 +- src/mainboard/intel/harcuvar/acpi_tables.c | 2 +- src/mainboard/intel/harcuvar/dsdt.asl | 2 +- src/mainboard/intel/harcuvar/fadt.c | 2 +- src/mainboard/intel/icelake_rvp/chromeos.c | 2 +- src/mainboard/intel/icelake_rvp/dsdt.asl | 2 +- src/mainboard/intel/icelake_rvp/mainboard.c | 2 +- src/mainboard/intel/jasperlake_rvp/dsdt.asl | 2 +- src/mainboard/intel/kblrvp/dsdt.asl | 2 +- src/mainboard/intel/kblrvp/ec.c | 2 +- src/mainboard/intel/kblrvp/mainboard.c | 2 +- src/mainboard/intel/kunimitsu/dsdt.asl | 2 +- src/mainboard/intel/kunimitsu/ec.c | 2 +- src/mainboard/intel/kunimitsu/mainboard.c | 2 +- src/mainboard/intel/kunimitsu/smihandler.c | 2 +- src/mainboard/intel/leafhill/dsdt.asl | 2 +- src/mainboard/intel/minnow3/dsdt.asl | 2 +- src/mainboard/intel/saddlebrook/dsdt.asl | 2 +- src/mainboard/intel/strago/acpi_tables.c | 2 +- src/mainboard/intel/strago/dsdt.asl | 2 +- src/mainboard/intel/strago/ec.c | 2 +- src/mainboard/intel/strago/smihandler.c | 2 +- src/mainboard/intel/tglrvp/dsdt.asl | 2 +- src/mainboard/intel/wtm2/acpi_tables.c | 2 +- src/mainboard/intel/wtm2/dsdt.asl | 2 +- src/mainboard/intel/wtm2/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl | 2 +- src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl | 2 +- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 2 +- src/mainboard/kontron/986lcd-m/cstates.c | 2 +- src/mainboard/kontron/986lcd-m/dsdt.asl | 2 +- src/mainboard/kontron/ktqm77/dsdt.asl | 2 +- src/mainboard/lenovo/g505s/acpi_tables.c | 2 +- src/mainboard/lenovo/g505s/dsdt.asl | 2 +- src/mainboard/lenovo/g505s/mainboard.c | 2 +- src/mainboard/lenovo/l520/dsdt.asl | 2 +- src/mainboard/lenovo/s230u/dsdt.asl | 2 +- src/mainboard/lenovo/s230u/mainboard.c | 2 +- src/mainboard/lenovo/t400/acpi_tables.c | 2 +- src/mainboard/lenovo/t400/cstates.c | 2 +- src/mainboard/lenovo/t400/dsdt.asl | 2 +- src/mainboard/lenovo/t400/fadt.c | 2 +- src/mainboard/lenovo/t410/dsdt.asl | 2 +- src/mainboard/lenovo/t410/mainboard.c | 2 +- src/mainboard/lenovo/t420/dsdt.asl | 2 +- src/mainboard/lenovo/t420s/dsdt.asl | 2 +- src/mainboard/lenovo/t430/dsdt.asl | 2 +- src/mainboard/lenovo/t430s/dsdt.asl | 2 +- src/mainboard/lenovo/t440p/dsdt.asl | 2 +- src/mainboard/lenovo/t520/dsdt.asl | 2 +- src/mainboard/lenovo/t530/dsdt.asl | 2 +- src/mainboard/lenovo/t60/dsdt.asl | 2 +- src/mainboard/lenovo/t60/mainboard.c | 2 +- src/mainboard/lenovo/thinkcentre_a58/cstates.c | 2 +- src/mainboard/lenovo/thinkcentre_a58/dsdt.asl | 2 +- src/mainboard/lenovo/x131e/dsdt.asl | 2 +- src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 2 +- src/mainboard/lenovo/x200/acpi_tables.c | 2 +- src/mainboard/lenovo/x200/cstates.c | 2 +- src/mainboard/lenovo/x200/dsdt.asl | 2 +- src/mainboard/lenovo/x200/fadt.c | 2 +- src/mainboard/lenovo/x201/dsdt.asl | 2 +- src/mainboard/lenovo/x220/dsdt.asl | 2 +- src/mainboard/lenovo/x220/early_init.c | 2 +- src/mainboard/lenovo/x230/dsdt.asl | 2 +- src/mainboard/lenovo/x60/dsdt.asl | 2 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/mainboard/libretrend/lt1000/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/acpi/routing.asl | 2 +- src/mainboard/lippert/frontrunner-af/acpi/usb.asl | 2 +- src/mainboard/lippert/frontrunner-af/acpi_tables.c | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/lippert/toucan-af/acpi/routing.asl | 2 +- src/mainboard/lippert/toucan-af/acpi/usb.asl | 2 +- src/mainboard/lippert/toucan-af/acpi_tables.c | 2 +- src/mainboard/lippert/toucan-af/dsdt.asl | 2 +- src/mainboard/msi/ms7707/dsdt.asl | 2 +- src/mainboard/msi/ms7721/acpi/cpstate.asl | 2 +- src/mainboard/msi/ms7721/acpi_tables.c | 2 +- src/mainboard/msi/ms7721/dsdt.asl | 2 +- src/mainboard/ocp/sonorapass/dsdt.asl | 2 +- src/mainboard/ocp/tiogapass/dsdt.asl | 2 +- src/mainboard/ocp/tiogapass/fadt.c | 2 +- src/mainboard/packardbell/ms2290/dsdt.asl | 2 +- src/mainboard/pcengines/apu1/acpi/routing.asl | 2 +- src/mainboard/pcengines/apu1/acpi/usb_oc.asl | 2 +- src/mainboard/pcengines/apu1/acpi_tables.c | 2 +- src/mainboard/pcengines/apu1/dsdt.asl | 2 +- src/mainboard/pcengines/apu2/acpi/routing.asl | 2 +- src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 2 +- src/mainboard/pcengines/apu2/acpi_tables.c | 2 +- src/mainboard/pcengines/apu2/dsdt.asl | 2 +- src/mainboard/portwell/m107/acpi_tables.c | 2 +- src/mainboard/portwell/m107/dsdt.asl | 2 +- src/mainboard/protectli/vault_bsw/dsdt.asl | 2 +- src/mainboard/protectli/vault_kbl/dsdt.asl | 2 +- src/mainboard/purism/librem_bdw/acpi_tables.c | 2 +- src/mainboard/purism/librem_bdw/dsdt.asl | 2 +- src/mainboard/purism/librem_skl/dsdt.asl | 2 +- src/mainboard/razer/blade_stealth_kbl/dsdt.asl | 2 +- src/mainboard/roda/rk886ex/cstates.c | 2 +- src/mainboard/roda/rk886ex/dsdt.asl | 2 +- src/mainboard/roda/rk9/acpi_tables.c | 2 +- src/mainboard/roda/rk9/cstates.c | 2 +- src/mainboard/roda/rk9/dsdt.asl | 2 +- src/mainboard/roda/rk9/fadt.c | 2 +- src/mainboard/roda/rv11/dsdt.asl | 2 +- src/mainboard/samsung/lumpy/acpi_tables.c | 2 +- src/mainboard/samsung/lumpy/dsdt.asl | 2 +- src/mainboard/samsung/lumpy/ec.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 2 +- src/mainboard/samsung/stumpy/acpi_tables.c | 2 +- src/mainboard/samsung/stumpy/dsdt.asl | 2 +- src/mainboard/samsung/stumpy/mainboard.c | 2 +- src/mainboard/samsung/stumpy/smihandler.c | 2 +- src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 2 +- src/mainboard/scaleway/tagada/acpi_tables.c | 2 +- src/mainboard/scaleway/tagada/dsdt.asl | 2 +- src/mainboard/scaleway/tagada/fadt.c | 2 +- src/mainboard/siemens/mc_apl1/dsdt.asl | 2 +- src/mainboard/supermicro/x10slm-f/dsdt.asl | 2 +- src/mainboard/supermicro/x11-lga1151-series/dsdt.asl | 2 +- src/mainboard/supermicro/x9scl/dsdt.asl | 2 +- src/mainboard/system76/lemp9/dsdt.asl | 2 +- src/mainboard/up/squared/dsdt.asl | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 4 ++-- src/northbridge/amd/pi/00630F01/northbridge.c | 4 ++-- src/northbridge/amd/pi/00660F01/northbridge.c | 4 ++-- src/northbridge/amd/pi/00730F01/northbridge.c | 6 +++--- src/northbridge/intel/e7505/northbridge.c | 2 +- src/northbridge/intel/gm45/acpi.c | 4 ++-- src/northbridge/intel/gm45/northbridge.c | 2 +- src/northbridge/intel/gm45/romstage.c | 2 +- src/northbridge/intel/haswell/acpi.c | 2 +- src/northbridge/intel/haswell/northbridge.c | 2 +- src/northbridge/intel/i945/acpi.c | 4 ++-- src/northbridge/intel/i945/northbridge.c | 2 +- src/northbridge/intel/ironlake/northbridge.c | 2 +- src/northbridge/intel/pineview/acpi.c | 4 ++-- src/northbridge/intel/pineview/northbridge.c | 2 +- src/northbridge/intel/sandybridge/acpi.c | 2 +- src/northbridge/intel/sandybridge/northbridge.c | 2 +- src/northbridge/intel/x4x/acpi.c | 4 ++-- src/northbridge/intel/x4x/northbridge.c | 2 +- src/security/memory/memory_clear.c | 2 +- src/soc/amd/common/block/acpi/acpi.c | 2 +- src/soc/amd/common/block/graphics/graphics.c | 2 +- src/soc/amd/common/block/hda/hda.c | 2 +- src/soc/amd/common/block/include/amdblocks/acpi.h | 2 +- src/soc/amd/common/block/pi/agesawrapper.c | 2 +- src/soc/amd/common/block/pi/amd_late_init.c | 2 +- src/soc/amd/common/block/pi/refcode_loader.c | 2 +- src/soc/amd/common/block/sata/sata.c | 2 +- src/soc/amd/picasso/acpi.c | 4 ++-- src/soc/amd/picasso/chip.h | 4 ++-- src/soc/amd/picasso/finalize.c | 2 +- src/soc/amd/picasso/i2c.c | 2 +- src/soc/amd/picasso/include/soc/acpi.h | 2 +- src/soc/amd/picasso/mca.c | 2 +- src/soc/amd/picasso/northbridge.c | 4 ++-- src/soc/amd/picasso/pmutil.c | 2 +- src/soc/amd/picasso/romstage.c | 2 +- src/soc/amd/picasso/smihandler.c | 2 +- src/soc/amd/stoneyridge/acpi.c | 4 ++-- src/soc/amd/stoneyridge/chip.h | 2 +- src/soc/amd/stoneyridge/finalize.c | 2 +- src/soc/amd/stoneyridge/i2c.c | 2 +- src/soc/amd/stoneyridge/include/soc/acpi.h | 2 +- src/soc/amd/stoneyridge/mca.c | 2 +- src/soc/amd/stoneyridge/northbridge.c | 4 ++-- src/soc/amd/stoneyridge/pmutil.c | 2 +- src/soc/amd/stoneyridge/romstage.c | 2 +- src/soc/amd/stoneyridge/smihandler.c | 2 +- src/soc/intel/apollolake/acpi.c | 4 ++-- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/cpu.c | 2 +- src/soc/intel/apollolake/graphics.c | 2 +- src/soc/intel/apollolake/include/soc/pm.h | 2 +- src/soc/intel/apollolake/pmutil.c | 2 +- src/soc/intel/baytrail/acpi.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 2 +- src/soc/intel/baytrail/elog.c | 2 +- src/soc/intel/baytrail/include/soc/acpi.h | 2 +- src/soc/intel/baytrail/include/soc/pmc.h | 2 +- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pmutil.c | 2 +- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/refcode.c | 2 +- src/soc/intel/baytrail/romstage/raminit.c | 2 +- src/soc/intel/baytrail/southcluster.c | 4 ++-- src/soc/intel/baytrail/xhci.c | 2 +- src/soc/intel/braswell/acpi.c | 4 ++-- src/soc/intel/braswell/elog.c | 2 +- src/soc/intel/braswell/include/soc/acpi.h | 2 +- src/soc/intel/braswell/include/soc/pm.h | 2 +- src/soc/intel/braswell/northcluster.c | 2 +- src/soc/intel/braswell/pmutil.c | 2 +- src/soc/intel/braswell/ramstage.c | 2 +- src/soc/intel/braswell/southcluster.c | 2 +- src/soc/intel/broadwell/acpi.c | 4 ++-- src/soc/intel/broadwell/igd.c | 2 +- src/soc/intel/broadwell/include/soc/acpi.h | 2 +- src/soc/intel/broadwell/include/soc/pm.h | 2 +- src/soc/intel/broadwell/lpc.c | 4 ++-- src/soc/intel/broadwell/me.c | 2 +- src/soc/intel/broadwell/pmutil.c | 2 +- src/soc/intel/broadwell/ramstage.c | 2 +- src/soc/intel/broadwell/refcode.c | 2 +- src/soc/intel/broadwell/systemagent.c | 2 +- src/soc/intel/broadwell/xhci.c | 2 +- src/soc/intel/cannonlake/acpi.c | 4 ++-- src/soc/intel/cannonlake/graphics.c | 2 +- src/soc/intel/cannonlake/include/soc/pm.h | 2 +- src/soc/intel/common/acpi_wake_source.c | 2 +- src/soc/intel/common/block/acpi/acpi.c | 2 +- src/soc/intel/common/block/cpu/cpulib.c | 2 +- src/soc/intel/common/block/include/intelblocks/acpi.h | 2 +- src/soc/intel/common/block/include/intelblocks/sd.h | 2 +- src/soc/intel/common/block/pmc/pmc.c | 2 +- src/soc/intel/common/block/pmc/pmclib.c | 2 +- src/soc/intel/common/block/scs/early_mmc.c | 2 +- src/soc/intel/common/block/scs/sd.c | 2 +- src/soc/intel/common/block/uart/uart.c | 2 +- src/soc/intel/common/block/xhci/xhci.c | 2 +- src/soc/intel/common/tpm_tis.c | 2 +- src/soc/intel/common/vbt.c | 2 +- src/soc/intel/denverton_ns/acpi.c | 4 ++-- src/soc/intel/denverton_ns/chip.c | 2 +- src/soc/intel/denverton_ns/include/soc/acpi.h | 2 +- src/soc/intel/denverton_ns/include/soc/pm.h | 2 +- src/soc/intel/denverton_ns/lpc.c | 2 +- src/soc/intel/denverton_ns/pmc.c | 2 +- src/soc/intel/icelake/acpi.c | 4 ++-- src/soc/intel/icelake/graphics.c | 2 +- src/soc/intel/icelake/include/soc/pm.h | 2 +- src/soc/intel/jasperlake/acpi.c | 4 ++-- src/soc/intel/jasperlake/graphics.c | 2 +- src/soc/intel/jasperlake/include/soc/pm.h | 2 +- src/soc/intel/quark/include/soc/acpi.h | 4 ++-- src/soc/intel/quark/include/soc/pm.h | 2 +- src/soc/intel/skylake/acpi.c | 4 ++-- src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/skylake/chip.h | 2 +- src/soc/intel/skylake/include/soc/acpi.h | 2 +- src/soc/intel/skylake/include/soc/pm.h | 2 +- src/soc/intel/skylake/pmutil.c | 2 +- src/soc/intel/tigerlake/acpi.c | 4 ++-- src/soc/intel/tigerlake/graphics.c | 2 +- src/soc/intel/tigerlake/include/soc/pm.h | 2 +- src/soc/intel/xeon_sp/cpx/acpi.c | 2 +- src/soc/intel/xeon_sp/cpx/cpu.c | 4 ++-- src/soc/intel/xeon_sp/skx/acpi.c | 2 +- src/soc/intel/xeon_sp/skx/include/soc/acpi.h | 2 +- src/soc/intel/xeon_sp/skx/include/soc/soc_util.h | 2 +- src/southbridge/amd/agesa/hudson/fadt.c | 2 +- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/agesa/hudson/ramtop.c | 2 +- src/southbridge/amd/cimx/sb800/cfg.c | 2 +- src/southbridge/amd/cimx/sb800/fadt.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/cimx/sb800/ramtop.c | 2 +- src/southbridge/amd/pi/hudson/fadt.c | 2 +- src/southbridge/amd/pi/hudson/hudson.c | 2 +- src/southbridge/amd/pi/hudson/lpc.c | 2 +- src/southbridge/intel/bd82x6x/elog.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/pch.h | 2 +- src/southbridge/intel/common/acpi_pirq_gen.c | 2 +- src/southbridge/intel/common/madt.c | 2 +- src/southbridge/intel/common/pciehp.c | 4 ++-- src/southbridge/intel/common/pmbase.c | 2 +- src/southbridge/intel/common/pmclib.c | 2 +- src/southbridge/intel/common/smihandler.c | 2 +- src/southbridge/intel/i82371eb/acpi_tables.c | 4 ++-- src/southbridge/intel/i82371eb/fadt.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 4 ++-- src/southbridge/intel/i82371eb/wakeup.c | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 2 +- src/southbridge/intel/i82801dx/smi.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 4 ++-- src/southbridge/intel/i82801ix/smi.c | 2 +- src/southbridge/intel/i82801jx/lpc.c | 4 ++-- src/southbridge/intel/ibexpeak/lpc.c | 4 ++-- src/southbridge/intel/ibexpeak/madt.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 2 +- src/southbridge/intel/ibexpeak/pch.h | 2 +- src/southbridge/intel/lynxpoint/acpi.c | 4 ++-- src/southbridge/intel/lynxpoint/elog.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 4 ++-- src/southbridge/intel/lynxpoint/me_9.x.c | 2 +- src/southbridge/intel/lynxpoint/pch.h | 2 +- src/superio/aspeed/ast2400/superio.c | 2 +- src/superio/common/conf_mode.c | 2 +- src/superio/common/generic.c | 2 +- src/superio/common/ssdt.c | 4 ++-- src/superio/nuvoton/nct5539d/superio.c | 2 +- src/superio/nuvoton/nct5572d/superio.c | 2 +- src/superio/nuvoton/nct6791d/superio.c | 2 +- src/superio/nuvoton/npcd378/superio.c | 4 ++-- src/superio/winbond/w83667hg-a/superio.c | 2 +- src/vendorcode/eltan/security/mboot/mboot.h | 2 +- src/vendorcode/google/chromeos/acpi.c | 2 +- src/vendorcode/google/chromeos/elog.c | 2 +- util/autoport/main.go | 2 +- 691 files changed, 790 insertions(+), 790 deletions(-) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 6b1bb30740..53131c6e6f 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -657,7 +657,7 @@ Use the following steps to debug the call to TempRamInit: The EDK2 data structure is defined in MdeModulePkg/Include/IndustryStandard/Acpi61.h The coreboot data structure is defined in - src/arch/x86/include/arch/acpi.h + src/arch/x86/include/arch/acpi.h

    diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md index 556c9668f6..c3c4c2e402 100644 --- a/Documentation/acpi/devicetree.md +++ b/Documentation/acpi/devicetree.md @@ -157,7 +157,7 @@ Note that the ACPI_IRQ_WAKE_EDGE_LOW macro informs the platform that the GPIO will be routed through SCI (ACPI's System Control Interrupt) for use as a wake source. Also note that the IRQ names are SoC-specific, and you will need to find the names in your SoC's header file. The ACPI_* macros are defined in -``src/arch/x86/include/arch/acpi_device.h``. +``src/arch/x86/include/acpi/acpi_device.h``. Using a GPIO as an IRQ requires that it is configured in coreboot correctly. This is often done in a mainboard-specific file named ``gpio.c``. diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 8e7b51d79d..d5b2c6b274 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -16,9 +16,9 @@ #include #include -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/acpi/acpi_device.c b/src/acpi/acpi_device.c index 9f63200121..6b067f3a0f 100644 --- a/src/acpi/acpi_device.c +++ b/src/acpi/acpi_device.c @@ -3,9 +3,9 @@ #include #include -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/acpi/acpi_pld.c b/src/acpi/acpi_pld.c index 135009a243..a2d0dd7fe7 100644 --- a/src/acpi/acpi_pld.c +++ b/src/acpi/acpi_pld.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, struct acpi_pld_group *group) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index dfc2a5adf4..a2dc84f799 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/acpi/acpigen_dsm.c b/src/acpi/acpigen_dsm.c index ecac3fefb8..b7b2a0bf18 100644 --- a/src/acpi/acpigen_dsm.c +++ b/src/acpi/acpigen_dsm.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include /* ------------------- I2C HID DSM ---------------------------- */ diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 7943f9a158..be8d2eb999 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -4,9 +4,9 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include -#include -#include +#include +#include +#include #include #include diff --git a/src/acpi/sata.c b/src/acpi/sata.c index f2b381124e..f2f53e6f64 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -3,8 +3,8 @@ #include "sata.h" -#include -#include +#include +#include /* e.g. * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index cde807c17f..2c1d2ce471 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* - #include + #include DefinitionBlock ( "DSDT.AML", "DSDT", diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index a7061fa7c5..c5f98f7ea8 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index bf17980020..39e3a056cd 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index 4ac1359faa..99aa2d3f16 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 3e7b0b560c..d088f02ee9 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -5,7 +5,7 @@ #define _BERT_STORAGE_H_ #include -#include +#include /* Items in the BERT region * diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 7e653f7245..3affd75761 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index c8a5a6298d..4bee724f16 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include static void model_14_init(struct device *dev) diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 7279e8a358..f731990bed 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include static void model_15_init(struct device *dev) diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 67ce592523..e92e870d3a 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include static void model_16_init(struct device *dev) diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 0147a01447..c4ef6263f2 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index b3cc1e0d5b..423146176e 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 82c28bfc22..c89bb830b3 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index a45f021ccb..692cc8036f 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index a642afdfd4..d856b3bac7 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index d668f45f23..043e7facfe 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4dfdc349b3..fabb6ba18b 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 1d33640c8b..eead460460 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c index 96650d608d..1875c3dc37 100644 --- a/src/cpu/x86/backup_default_smm.c +++ b/src/cpu/x86/backup_default_smm.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 6726f213d4..2c6960d9b6 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 02cb5addfb..6fce761a72 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -6,7 +6,7 @@ * PCI Bus Services, see include/linux/pci.h for further explanation. */ -#include +#include #include #include #include diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 4fec2906d6..08bfec8178 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include /* Rmodules don't like weak symbols. */ void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; } diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index 85f203c506..ea8abb52a5 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 6c90ac2a12..3652f8f80d 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index a0d775295c..f9bf1fe2a9 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 0e97a07848..d34091121b 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index ab86f387cc..3bc52dd70d 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #if CONFIG(HAVE_ACPI_RESUME) -#include +#include #endif #include #include diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index bf2f03de04..ddf6b7a93e 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h index 3a7b21d3e9..e4535b24c2 100644 --- a/src/drivers/generic/bayhub/chip.h +++ b/src/drivers/generic/bayhub/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include /* * Bayhub BG720 PCI to eMMC bridge diff --git a/src/drivers/generic/generic/chip.h b/src/drivers/generic/generic/chip.h index 41b5f461db..47b83a740e 100644 --- a/src/drivers/generic/generic/chip.h +++ b/src/drivers/generic/generic/chip.h @@ -6,7 +6,7 @@ #if CONFIG(HAVE_ACPI_TABLES) -#include +#include #define MAX_GENERIC_PROPERTY_LIST 10 diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index eed824d375..00b9dda02c 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 9836abac60..e0ba3752d9 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -4,7 +4,7 @@ #ifndef __DRIVERS_GENERIC_GPIO_KEYS_H__ #define __DRIVERS_GENERIC_GPIO_KEYS_H__ -#include +#include #include /* Linux input type */ diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 1017f7a69f..732f02ad28 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/generic/gpio_regulator/chip.h b/src/drivers/generic/gpio_regulator/chip.h index 8ae02ae3c2..f3d1d0f86a 100644 --- a/src/drivers/generic/gpio_regulator/chip.h +++ b/src/drivers/generic/gpio_regulator/chip.h @@ -4,7 +4,7 @@ #ifndef __DRIVERS_GENERIC_GPIO_REGULATOR_H__ #define __DRIVERS_GENERIC_GPIO_REGULATOR_H__ -#include +#include struct drivers_generic_gpio_regulator_config { const char *name; diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 0ec1626da8..4eedb8bd7b 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h index 95a58f09d6..248311cc38 100644 --- a/src/drivers/generic/max98357a/chip.h +++ b/src/drivers/generic/max98357a/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include struct drivers_generic_max98357a_config { diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index b9c270b0c5..52f08c69f7 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index 8e70bc6978..67843fdb42 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -4,7 +4,7 @@ #ifndef __DRIVERS_GFX_GENERIC_CHIP_H__ #define __DRIVERS_GFX_GENERIC_CHIP_H__ -#include +#include /* Config for electronic privacy screen */ struct drivers_gfx_generic_privacy_screen_config { diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 4670b4d65f..2cbb17a06c 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/drivers/i2c/da7219/chip.h b/src/drivers/i2c/da7219/chip.h index 32d04dada1..9afce952c8 100644 --- a/src/drivers/i2c/da7219/chip.h +++ b/src/drivers/i2c/da7219/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include /* * Dialog Semiconductor DA7219 Audio Codec devicetree bindings diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 931c437546..3b122026a3 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 74e24c7a53..dd5c17ce5a 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index e1f4472a44..a9a7082b12 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -4,7 +4,7 @@ #ifndef __I2C_GENERIC_CHIP_H__ #define __I2C_GENERIC_CHIP_H__ -#include +#include #include #define MAX_GENERIC_PROPERTY_LIST 10 diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 7e709d6cc7..38fa3ebeb9 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 4fac85874d..b588115275 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 067563868c..542dc98fb7 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index ddd9d152b0..0ea33d5f2b 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/nau8825/chip.h b/src/drivers/i2c/nau8825/chip.h index 80d950ff71..3f17a5674b 100644 --- a/src/drivers/i2c/nau8825/chip.h +++ b/src/drivers/i2c/nau8825/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #define NAU8825_MAX_BUTTONS 8 diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index fd9cfc9679..1d31f302f8 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index ec018cc38f..da8ad4eaf0 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index 6f7fbd87bb..ef498dba15 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -5,7 +5,7 @@ * Realtek RT5663 audio codec devicetree bindings */ -#include +#include #include struct drivers_i2c_rt5663_config { diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 67d8dea562..0573454b7d 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/sx9310/chip.h b/src/drivers/i2c/sx9310/chip.h index b3820c80fc..bf4945b143 100644 --- a/src/drivers/i2c/sx9310/chip.h +++ b/src/drivers/i2c/sx9310/chip.h @@ -4,7 +4,7 @@ #ifndef __DRIVERS_I2C_SX9310_CHIP_H__ #define __DRIVERS_I2C_SX9310_CHIP_H__ -#include +#include #include #define REGISTER(NAME) uint8_t NAME diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 44cb883478..39299295cf 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index fbf9ffa667..e471652ef9 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/i2c/tpm/chip.h b/src/drivers/i2c/tpm/chip.h index 491d0223f8..fadd1ec849 100644 --- a/src/drivers/i2c/tpm/chip.h +++ b/src/drivers/i2c/tpm/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include struct drivers_i2c_tpm_config { diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index af554f43b4..a090a1fce5 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 8d51244914..11eee04e88 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 5f7864412b..90760970a5 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index 5a10ab4ed7..b7f4847ce5 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include "i915.h" diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 59d3010be1..aac330415b 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0a11..cd42337d07 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 58402869f4..adfa4f1800 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index b8e1076346..16e139eb52 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 145313a599..c3b2b4ee2e 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -13,8 +13,8 @@ #include #include #if CONFIG(HAVE_ACPI_TABLES) -#include -#include +#include +#include #endif #if CONFIG(GENERATE_SMBIOS_TABLES) #include diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 442089814c..1da5ddc989 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -14,8 +14,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index bc4ae4b6e8..df22db2107 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -5,7 +5,7 @@ #define __DRIVERS_R8168_CHIP_H__ #include -#include +#include struct drivers_net_config { uint16_t customized_leds; diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index b904586dd5..92cb9b54f2 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -9,8 +9,8 @@ */ #include -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c index d841f946fb..64deacaea1 100644 --- a/src/drivers/pc80/pc/keyboard.c +++ b/src/drivers/pc80/pc/keyboard.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 419ed6b9fc..d34fbb13cf 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 3d4c6b6d98..5994cefd86 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -15,9 +15,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 0eeaffbddd..39e887bfd9 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h index b74c1776a2..ea369b308f 100644 --- a/src/drivers/spi/acpi/chip.h +++ b/src/drivers/spi/acpi/chip.h @@ -4,7 +4,7 @@ #ifndef __SPI_ACPI_CHIP_H__ #define __SPI_ACPI_CHIP_H__ -#include +#include struct drivers_spi_acpi_config { const char *hid; /* ACPI _HID (required) */ diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index 53a0c4b59b..a38e18185a 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -7,7 +7,7 @@ #include #if CONFIG(HAVE_ACPI_RESUME) -#include +#include #endif static void init_tpm_dev(void *unused) diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 42a94d5105..3bca91cf75 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -4,9 +4,9 @@ #ifndef __USB_ACPI_CHIP_H__ #define __USB_ACPI_CHIP_H__ -#include -#include -#include +#include +#include +#include struct drivers_usb_acpi_config { const char *desc; diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 916d3733ec..6720e2c394 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index b864094499..ca16686ce6 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -12,8 +12,8 @@ * GNU General Public License for more details. */ -#include -#include +#include +#include #include #include #include diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 2331c7a492..b29c32f3e1 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -5,10 +5,10 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include -#include -#include -#include +#include +#include +#include +#include #include #include #include diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c index 51375f8f22..7a110cba26 100644 --- a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index 5e192a51da..fb8bb7e04c 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 0d0f987da3..7516b2a879 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/src/ec/google/wilco/smihandler.c b/src/ec/google/wilco/smihandler.c index a9f07fe0c4..f3ed90b5a4 100644 --- a/src/ec/google/wilco/smihandler.c +++ b/src/ec/google/wilco/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index e69b242bcb..69a43a9826 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/ec/lenovo/h8/ssdt.c b/src/ec/lenovo/h8/ssdt.c index 56e305a787..92522cd8fe 100644 --- a/src/ec/lenovo/h8/ssdt.c +++ b/src/ec/lenovo/h8/ssdt.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include "h8.h" diff --git a/src/include/acpi/acpi_pld.h b/src/include/acpi/acpi_pld.h index 944eb3154a..c518077597 100644 --- a/src/include/acpi/acpi_pld.h +++ b/src/include/acpi/acpi_pld.h @@ -4,7 +4,7 @@ #ifndef __ACPI_PLD_H #define __ACPI_PLD_H -#include +#include #include enum acpi_pld_panel { diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index a3c4777afb..005ec6b096 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -5,9 +5,9 @@ #define LIBACPI_H #include -#include -#include -#include +#include +#include +#include #include /* Values that can be returned for ACPI Device _STA method */ diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 3c8e76e7ef..a787efe889 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -5,7 +5,7 @@ #define DEVICE_AZALIA_H #include -#include +#include #include #include diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 6b6fee2c44..c49389f396 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,7 +2,7 @@ #define PCI_ROM_H #include #include -#include +#include #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR ((uint32_t) (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d2615243b2..075bd04082 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -26,7 +26,7 @@ #endif #if CONFIG(CHROMEOS) #if CONFIG(HAVE_ACPI_TABLES) -#include +#include #endif #include #include diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 4fdf55446a..73632fc512 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -21,7 +21,7 @@ #include #include #if CONFIG(HAVE_ACPI_RESUME) -#include +#include #endif #include #include diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 4ed3c6c13c..462a9ce57d 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index b88a56c632..277a96b076 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/amd/gardenia/acpi/routing.asl b/src/mainboard/amd/gardenia/acpi/routing.asl index 642ef8f8ad..dd0a48d5eb 100644 --- a/src/mainboard/amd/gardenia/acpi/routing.asl +++ b/src/mainboard/amd/gardenia/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/gardenia/acpi/usb_oc.asl b/src/mainboard/amd/gardenia/acpi/usb_oc.asl index 8a4df6fbb5..49d7744c4f 100644 --- a/src/mainboard/amd/gardenia/acpi/usb_oc.asl +++ b/src/mainboard/amd/gardenia/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 4f861cbd04..e2a3dcd11e 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -4,7 +4,7 @@ #define MAINBOARD_HAS_SPEAKER 1 /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl index 88024a73f2..c7d9861738 100644 --- a/src/mainboard/amd/inagua/acpi/routing.asl +++ b/src/mainboard/amd/inagua/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/amd/inagua/acpi/usb_oc.asl +++ b/src/mainboard/amd/inagua/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index ca149ba600..09ea5b0b34 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/amd/olivehill/acpi/routing.asl +++ b/src/mainboard/amd/olivehill/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/olivehill/acpi/usb_oc.asl b/src/mainboard/amd/olivehill/acpi/usb_oc.asl index 4ea18f54b8..e95ec3f6c3 100644 --- a/src/mainboard/amd/olivehill/acpi/usb_oc.asl +++ b/src/mainboard/amd/olivehill/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index 1b822e60ba..4fdefdc1a8 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index aa8c2c3009..30d43c3eaa 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index 7edd3bef45..7be4ebab5c 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index 3eb63c8920..a311f72b80 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index 20e550f157..85ec272659 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index d7dc69a34d..eea2b4d55d 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/persimmon/acpi/usb_oc.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/amd/persimmon/acpi/usb_oc.asl +++ b/src/mainboard/amd/persimmon/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index ca149ba600..09ea5b0b34 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index 88024a73f2..c7d9861738 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/amd/south_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/south_station/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index ca149ba600..09ea5b0b34 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl index 86361521a2..9e7fdcf706 100644 --- a/src/mainboard/amd/thatcher/acpi/cpstate.asl +++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl @@ -7,7 +7,7 @@ * characteristics. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { Scope (\_SB) { diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index 3eb63c8920..a311f72b80 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index 20e550f157..85ec272659 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl index 88024a73f2..c7d9861738 100644 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/amd/union_station/acpi/usb_oc.asl +++ b/src/mainboard/amd/union_station/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index ca149ba600..09ea5b0b34 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index e76e525a4d..778455a1ff 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -6,7 +6,7 @@ * Ported to AOpen DXPL Plus-U by Kyösti Mälkki */ -#include +#include #include #define IOAPIC_ICH4 2 diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 7fcdad960a..d43e7b63f3 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index 4f3c2be4fc..6460dbd79b 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include /* FIXME: This needs to go into a separate .h file diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index f14272d5a7..77d6daf19f 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -5,7 +5,7 @@ #define BRIGHTNESS_DOWN \DSPC.BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index cb722562c8..a537fd31cc 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 01656ad269..315fd4df1d 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -4,7 +4,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index ff5c708e1d..6d9866e1b6 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -4,7 +4,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index 8764b2d671..f9664fc4f4 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 2ddb2885a9..d77d22df0c 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl +++ b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index e05fee5e28..60a5d84340 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/asrock/g41c-gs/cstates.c b/src/mainboard/asrock/g41c-gs/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/asrock/g41c-gs/cstates.c +++ b/src/mainboard/asrock/g41c-gs/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index 8880ba7076..8e1656b224 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index 568ca39132..14350c9cce 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 1b1ec6eaef..3e7d798855 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asrock/imb-a180/acpi/routing.asl b/src/mainboard/asrock/imb-a180/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/asrock/imb-a180/acpi/routing.asl +++ b/src/mainboard/asrock/imb-a180/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl index e44e97001e..d80cc35552 100644 --- a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl +++ b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 1b822e60ba..4fdefdc1a8 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c index e6397d3632..047a3a015e 100644 --- a/src/mainboard/asus/am1i-a/acpi_tables.c +++ b/src/mainboard/asus/am1i-a/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index f6d028f7c7..c9e6be0dff 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl index 86361521a2..9e7fdcf706 100644 --- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -7,7 +7,7 @@ * characteristics. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { Scope (\_SB) { diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index 3eb63c8920..a311f72b80 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index e43640918c..bcde29de93 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 42fc8abb15..28cf2fed82 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index a9b0faa5b4..8708809fee 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p2b/acpi_tables.c b/src/mainboard/asus/p2b/acpi_tables.c index 9f18039c32..39a9719202 100644 --- a/src/mainboard/asus/p2b/acpi_tables.c +++ b/src/mainboard/asus/p2b/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index e119871ed6..c3a279d672 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -9,7 +9,7 @@ #define SUPERIO_SHOW_FDC #define SUPERIO_SHOW_LPT -#include +#include DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) { /* \_SB scope defining the main processor is generated in SSDT. */ diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/asus/p5gc-mx/cstates.c +++ b/src/mainboard/asus/p5gc-mx/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl index a27be09a6b..c3f5e4b8ef 100644 --- a/src/mainboard/asus/p5gc-mx/dsdt.asl +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p5qc/cstates.c b/src/mainboard/asus/p5qc/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/asus/p5qc/cstates.c +++ b/src/mainboard/asus/p5qc/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index b72be15736..1b6651eb33 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index a775b6df25..e34767bf8e 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl index 2228a1c75e..e8ded2937f 100644 --- a/src/mainboard/asus/p5ql-em/dsdt.asl +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -3,7 +3,7 @@ #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p5qpl-am/cstates.c b/src/mainboard/asus/p5qpl-am/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/asus/p5qpl-am/cstates.c +++ b/src/mainboard/asus/p5qpl-am/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index 8880ba7076..8e1656b224 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index a9b0faa5b4..8708809fee 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl index af0cbad1d1..21538247fa 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index 7da32d3884..b77c2bac03 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 0c024568f4..ce1d905b6c 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -3,7 +3,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl index 9481566ce1..10b8ec7f97 100644 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/bap/ode_e20XX/acpi/routing.asl b/src/mainboard/bap/ode_e20XX/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/routing.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl index db55264f91..52b5606013 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index 1b822e60ba..4fdefdc1a8 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/bap/ode_e21XX/acpi/routing.asl b/src/mainboard/bap/ode_e21XX/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/routing.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl index b7757d3950..f6d8c9226b 100644 --- a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl +++ b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/bap/ode_e21XX/acpi_tables.c b/src/mainboard/bap/ode_e21XX/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/bap/ode_e21XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e21XX/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl index f18550a695..370e6b312f 100644 --- a/src/mainboard/bap/ode_e21XX/dsdt.asl +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/routing.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl index 4ea18f54b8..e95ec3f6c3 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/biostar/a68n_5200/acpi_tables.c +++ b/src/mainboard/biostar/a68n_5200/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index 1b822e60ba..4fdefdc1a8 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/biostar/am1ml/acpi/routing.asl b/src/mainboard/biostar/am1ml/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/biostar/am1ml/acpi/routing.asl +++ b/src/mainboard/biostar/am1ml/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/biostar/am1ml/acpi/usb_oc.asl b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl index 6ebc4bc4c4..9bb27eaa70 100644 --- a/src/mainboard/biostar/am1ml/acpi/usb_oc.asl +++ b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c index e6397d3632..047a3a015e 100644 --- a/src/mainboard/biostar/am1ml/acpi_tables.c +++ b/src/mainboard/biostar/am1ml/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index a2e69b188c..e2ac8926ef 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 247114ef86..f6d5d4a0b1 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -5,7 +5,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl index d7dc69a34d..eea2b4d55d 100644 --- a/src/mainboard/elmex/pcm205400/acpi/routing.asl +++ b/src/mainboard/elmex/pcm205400/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl +++ b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index ca149ba600..09ea5b0b34 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index 08df134e59..39143e42bb 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 9bef7d9c18..ad9243b9cb 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -13,7 +13,7 @@ * Lesser General Public License for more details. */ -#include +#include DefinitionBlock ( "dsdt.aml", // Output Filename "DSDT", // Signature diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 8afd832aeb..ccd12312ea 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include "fw_cfg.h" diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 359c562e53..2be4ed07cb 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index ea17df21e2..5e4769da56 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -19,7 +19,7 @@ * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset. */ -#include +#include DefinitionBlock ( "dsdt.aml", // Output Filename "DSDT", // Signature diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index ae5aaf1f0f..45fb909057 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index b0a2af8d93..98e261550d 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #define SDCARD_CD 81 /* Not used */ diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 2cb27ebe8f..b9d961d25e 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/foxconn/d41s/cstates.c b/src/mainboard/foxconn/d41s/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/foxconn/d41s/cstates.c +++ b/src/mainboard/foxconn/d41s/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl index 75b17df090..8746132dbe 100644 --- a/src/mainboard/foxconn/d41s/dsdt.asl +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/foxconn/g41s-k/cstates.c b/src/mainboard/foxconn/g41s-k/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/foxconn/g41s-k/cstates.c +++ b/src/mainboard/foxconn/g41s-k/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index 8880ba7076..8e1656b224 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 72c18060f0..3d211de16c 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c index 69949f519b..b343e97f21 100644 --- a/src/mainboard/getac/p470/cstates.c +++ b/src/mainboard/getac/p470/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include static acpi_cstate_t cst_entries[] = { diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index dacdbdf936..6809c42ece 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -4,7 +4,7 @@ #define ENABLE_TPM #undef ENABLE_FDC // There is no Floppy for this laptop -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl index 9e3c03748c..62aa924f7f 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index ac65961b6d..a34bb6baba 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index fd5a7f0c44..0506c29496 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include static acpi_cstate_t cst_entries[] = {}; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index 8880ba7076..8e1656b224 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index cea8efe111..1b7bf223bb 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -3,7 +3,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index 2ddb2885a9..d77d22df0c 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index a7b28c6985..8227f47e44 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl index db55264f91..52b5606013 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index 1b822e60ba..4fdefdc1a8 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 1cfdb11742..19b75fd11e 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 6a9e693a06..5df7e077e3 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index b3a2d61a7b..a84d9643b3 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index ab32930bee..153a07169b 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 0445d0dcf5..abc5844ecb 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 014483c170..99dcb7e1f9 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index a31c5decba..bf52510b3d 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index 2f4b86f085..c7f6c50927 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index f75d858f2f..4758afb09e 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index f0658fea2f..102460d2e9 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 4c47a6b29a..a5e08bc932 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index 20d218df2e..ef644b1996 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 84544fcc55..0b444a3edd 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index 55c3e1ff3c..e009bf0927 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include "ec.h" diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 8b1032de63..1acac464a3 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index f7bb6b9090..47110f6987 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include diff --git a/src/mainboard/google/dedede/ec.c b/src/mainboard/google/dedede/ec.c index 98509c3b53..991dcf9160 100644 --- a/src/mainboard/google/dedede/ec.c +++ b/src/mainboard/google/dedede/ec.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include #include diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index ba7ba655f0..a58c5ac3b2 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include #include diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 2665f463df..0e199ca318 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include #include diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index b6bc8e4248..631ec5e9dd 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include "variant/ec.h" #include "variant/gpio.h" diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index 0a906d62ad..ba545409f6 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include #include diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 62b6559e46..c56fff818b 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include #include diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index efa0b0d0d7..1a16444e0f 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 7765ac922f..b00babb398 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include "variant/ec.h" #include "variant/gpio.h" diff --git a/src/mainboard/google/dragonegg/ec.c b/src/mainboard/google/dragonegg/ec.c index 1b6a5b8896..5ab8c580be 100644 --- a/src/mainboard/google/dragonegg/ec.c +++ b/src/mainboard/google/dragonegg/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c index 0bcb7d674a..a1a545a68c 100644 --- a/src/mainboard/google/dragonegg/mainboard.c +++ b/src/mainboard/google/dragonegg/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index eff43d0042..279b2f5641 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 10a4af5e30..04cf009222 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -3,7 +3,7 @@ #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index c79a4676dc..9c0c454669 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 90e8502374..db00f7fb2b 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -4,7 +4,7 @@ #include "ec.h" #include "gpio.h" -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/eve/ec.c b/src/mainboard/google/eve/ec.c index ec0334883a..006c7ee470 100644 --- a/src/mainboard/google/eve/ec.c +++ b/src/mainboard/google/eve/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include "ec.h" diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index ab7a5a8b28..564e76c90e 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 542c8445dc..4741513f35 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -4,7 +4,7 @@ #include #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/fizz/ec.c b/src/mainboard/google/fizz/ec.c index 9a1c2797d3..0ae46adc1a 100644 --- a/src/mainboard/google/fizz/ec.c +++ b/src/mainboard/google/fizz/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 4377af3f6c..aaae6f9d3e 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/fizz/variants/karma/smihandler.c b/src/mainboard/google/fizz/variants/karma/smihandler.c index 369795cb07..a0412b7842 100644 --- a/src/mainboard/google/fizz/variants/karma/smihandler.c +++ b/src/mainboard/google/fizz/variants/karma/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 708950e044..7d29008127 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c index fdc57c5e55..029b4fa7b6 100644 --- a/src/mainboard/google/glados/ec.c +++ b/src/mainboard/google/glados/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include "ec.h" diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 0d6ba32d0c..1db450a7ef 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index 1ff4e3c6d2..552f9d8a47 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 4825b05885..8e423eb515 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 04ce112480..e8b9b89399 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/google/hatch/ec.c b/src/mainboard/google/hatch/ec.c index f32f4fdf66..fcf4d533fa 100644 --- a/src/mainboard/google/hatch/ec.c +++ b/src/mainboard/google/hatch/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 08e145cd16..66140d169e 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 346801433a..efd3d47c2e 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 484057bef6..305f3500af 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 6d2da60e9b..ecb13cb078 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 2faf7921dc..bac4eb7334 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 76739c0618..92264bbbce 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 4cf2bfd9d2..9c1b4b5158 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 588e6ce1be..1b86d85fae 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 8df69cb89c..1df24ee258 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index a7898827d7..358d980c1b 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index abcb1d83dd..f5154320d9 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index 67d070a537..2fed318ddd 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 0249a307d1..3ad8fcff40 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index c689c2f457..5dd0c7c7d2 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index b2ea3eb6d3..fd287c5fe3 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index 2bf7802d81..bef6f3a24c 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include "onboard.h" diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 0d47bf434e..2d8bfc821b 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 56611c5d75..08288f83d7 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -4,7 +4,7 @@ #include /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 32f3d3532a..fcec0dc9aa 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 24297a3861..04791a47c5 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c index 078c9cda4c..afe80b92ba 100644 --- a/src/mainboard/google/kahlee/smihandler.c +++ b/src/mainboard/google/kahlee/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl index f989bbb6d8..9a51ff3d44 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* - * #include + * #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) *{ * #include "routing.asl" diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index f75d858f2f..4758afb09e 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index cf9c18f947..28fe3f4f0e 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 48a69ce398..3948022998 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 337807a52a..ab096134f1 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -8,7 +8,7 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include +#include #include #include #include "onboard.h" diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 70b128b48c..12c1b97e87 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index 11313f9336..ec70c31028 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -4,7 +4,7 @@ #include #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/octopus/ec.c b/src/mainboard/google/octopus/ec.c index 18d6b91c4e..3fe1e2f933 100644 --- a/src/mainboard/google/octopus/ec.c +++ b/src/mainboard/google/octopus/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index dd4d40de91..55404db500 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index 7ab8d2d132..74ff64d0a1 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 228fdbcbeb..fcd44577a0 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 089337ab4c..aa183cb6a7 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 4501f6c08f..e728fe3a08 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 5c92035c42..48263700da 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index ed6c133a32..ff9680b26d 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 434a83436b..9bb5467fd8 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index e42d7933b0..21e6fc671b 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index 660d41e3f0..b7f3786bfc 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 6851847dd6..620ca648a6 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index a0bd9b20f3..c67108bd47 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 9684c043f0..43d78354e7 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -4,7 +4,7 @@ #include #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/poppy/ec.c b/src/mainboard/google/poppy/ec.c index 77f063d875..fc2d5b5fbd 100644 --- a/src/mainboard/google/poppy/ec.c +++ b/src/mainboard/google/poppy/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index e24d6bcaea..5a1bfedf52 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/poppy/variants/nami/smihandler.c b/src/mainboard/google/poppy/variants/nami/smihandler.c index 0e4c085d9b..8f04f3baa1 100644 --- a/src/mainboard/google/poppy/variants/nami/smihandler.c +++ b/src/mainboard/google/poppy/variants/nami/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/smihandler.c b/src/mainboard/google/poppy/variants/nautilus/smihandler.c index a65172374b..44b7c9e782 100644 --- a/src/mainboard/google/poppy/variants/nautilus/smihandler.c +++ b/src/mainboard/google/poppy/variants/nautilus/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/poppy/variants/nocturne/ec.c b/src/mainboard/google/poppy/variants/nocturne/ec.c index 7619c7f602..b303984665 100644 --- a/src/mainboard/google/poppy/variants/nocturne/ec.c +++ b/src/mainboard/google/poppy/variants/nocturne/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index ef65930bf3..2120e23b34 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index ce393a312c..1471e2a899 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -3,7 +3,7 @@ #define ENABLE_TPM -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 4e1a192ee4..1187078b13 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 51da9b8672..ec0ce4a73f 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -7,7 +7,7 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include +#include #include #include #include "ec.h" diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index fa0e39f999..5ac4ada2b5 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 11313f9336..ec70c31028 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -4,7 +4,7 @@ #include #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c index 0a86910063..65334a00fb 100644 --- a/src/mainboard/google/reef/ec.c +++ b/src/mainboard/google/reef/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 66cf9c1b68..759bd2ece2 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index bde2e43e5a..ca5e277b47 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 3b3839ec9f..52d4a9182a 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index cd59fa9dec..471174eddc 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 25a10d8343..a019dc5277 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -3,7 +3,7 @@ #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 0b2d51b2af..7f129615ec 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 9666f296f4..2ecea5108f 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 767401d7ce..bb362c33bd 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 484b4acbba..4b937138b3 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index eea029c7fe..6ba83eeed6 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index d2d81f8de4..b587353132 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 94d7803fa0..ac74f1822b 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 49891c3470..12368d6932 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index bbac23871a..c5ba372cb3 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 8a6cf8f6be..2ae581feb3 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 6f0444f7ba..86985203c2 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index e2dcaef3f1..a87c743488 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include "variant/ec.h" #include "variant/gpio.h" diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c index d36c1e33af..10ed955ee0 100644 --- a/src/mainboard/google/volteer/ec.c +++ b/src/mainboard/google/volteer/ec.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include #include #include #include diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 0db43d1bed..22a6c77c1d 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/mainboard/hp/abm/acpi/routing.asl b/src/mainboard/hp/abm/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/hp/abm/acpi/routing.asl +++ b/src/mainboard/hp/abm/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl index db55264f91..52b5606013 100644 --- a/src/mainboard/hp/abm/acpi/usb_oc.asl +++ b/src/mainboard/hp/abm/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/hp/abm/acpi_tables.c b/src/mainboard/hp/abm/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/hp/abm/acpi_tables.c +++ b/src/mainboard/hp/abm/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index 1b822e60ba..4fdefdc1a8 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 150bdcf05a..5fc8201391 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -4,7 +4,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index 3eb63c8920..a311f72b80 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index 79f4b3f402..2df49f797d 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -4,7 +4,7 @@ #include "mainboard.h" /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 42af1b8efa..db19d56a96 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -3,7 +3,7 @@ #include "ec.h" -#include +#include #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 150bdcf05a..5fc8201391 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -4,7 +4,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 150bdcf05a..5fc8201391 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -4,7 +4,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/ibase/mb899/cstates.c b/src/mainboard/ibase/mb899/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/ibase/mb899/cstates.c +++ b/src/mainboard/ibase/mb899/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index 60b5949159..8897e0464a 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index e4e121bf36..05fdd237b9 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 935acf17ed..b09c7146cf 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 8957f752a1..0eae213c0d 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -3,7 +3,7 @@ #define ENABLE_TPM -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index db86877de3..3717dd041e 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index 5eef5eb31a..d3b1576953 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index f4a7b43842..bb88dbe80a 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 23a3932a6f..0a4c4d3b34 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c index bde45b110c..984e7e0ef1 100644 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/smihandler.c b/src/mainboard/intel/cannonlake_rvp/smihandler.c index 98459b6060..eec94cc446 100644 --- a/src/mainboard/intel/cannonlake_rvp/smihandler.c +++ b/src/mainboard/intel/cannonlake_rvp/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 3dc45d5f2c..6013bfb2ad 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include DefinitionBlock( diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 29d8fcca16..2fe308c676 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 1aa9020fcb..1fc731b520 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index 1759bb95b7..0bd071572b 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/intel/d510mo/cstates.c +++ b/src/mainboard/intel/d510mo/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index 75b17df090..8746132dbe 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/d945gclf/cstates.c b/src/mainboard/intel/d945gclf/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/intel/d945gclf/cstates.c +++ b/src/mainboard/intel/d945gclf/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 9e3c03748c..62aa924f7f 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 8f318b4817..0febac1817 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/dg41wv/cstates.c b/src/mainboard/intel/dg41wv/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/intel/dg41wv/cstates.c +++ b/src/mainboard/intel/dg41wv/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index 8880ba7076..8e1656b224 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/dg43gt/cstates.c b/src/mainboard/intel/dg43gt/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/intel/dg43gt/cstates.c +++ b/src/mainboard/intel/dg43gt/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index cfc0b23dc2..bdc73094d3 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 8d54aa28da..6253596926 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 1533583530..d72e1f9eb3 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index c1d2046b45..3ec74414b5 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 06e3a65738..9f65b8ad7f 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index 19575351b9..d74c98c0e1 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl index 2c9e9c656c..786aa3692b 100644 --- a/src/mainboard/intel/galileo/dsdt.asl +++ b/src/mainboard/intel/galileo/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 11313f9336..ec70c31028 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -4,7 +4,7 @@ #include #include -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c index cdafadb7ca..3a41f5d7d3 100644 --- a/src/mainboard/intel/glkrvp/ec.c +++ b/src/mainboard/intel/glkrvp/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index f6015a1b7d..43486fe33e 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c index 73bf2ba0d3..42561fe099 100644 --- a/src/mainboard/intel/glkrvp/smihandler.c +++ b/src/mainboard/intel/glkrvp/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 813bad943f..f9408f1b9d 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 8c6c00d521..cf26e32905 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index 8b38b3434c..370dfd4663 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index a2181213d9..632d10f15a 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index b7a012fbba..440d6995cd 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 41ef680d79..11c26f93ab 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c40acf29ef..8a956038b2 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 91a5c2fedc..690a705999 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/kblrvp/ec.c b/src/mainboard/intel/kblrvp/ec.c index 52819688a1..c060bef8f2 100644 --- a/src/mainboard/intel/kblrvp/ec.c +++ b/src/mainboard/intel/kblrvp/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include "ec.h" diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 639ad0e21b..fb2ae9b64b 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 046baa74ed..d93dc31f20 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/kunimitsu/ec.c b/src/mainboard/intel/kunimitsu/ec.c index 52819688a1..c060bef8f2 100644 --- a/src/mainboard/intel/kunimitsu/ec.c +++ b/src/mainboard/intel/kunimitsu/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include "ec.h" diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 6166a33f78..833929d58b 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 17837bb0ca..4c7287b136 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index 11ad0bb47e..7363974716 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index 11ad0bb47e..7363974716 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index 8cff20f84d..52f3d775f0 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 706e107378..a3ed8d8d83 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index 7abbcadab9..5333193c09 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index 55c3e1ff3c..e009bf0927 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include "ec.h" diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 4b1a2e2624..389a8822ae 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index 080072d4e0..c66e972639 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index e06e42b1cc..9458a29c0a 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 18609ac9f7..528f365784 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -3,7 +3,7 @@ #define ENABLE_TPM -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 026a28dc2f..5b0e36717a 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl index d7dc69a34d..eea2b4d55d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index 441f38f619..244ee5f786 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/kontron/986lcd-m/cstates.c b/src/mainboard/kontron/986lcd-m/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/kontron/986lcd-m/cstates.c +++ b/src/mainboard/kontron/986lcd-m/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 1a8513120e..ee74281d2f 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index 298f30f782..de21e4249f 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c index 3eb63c8920..a311f72b80 100644 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ b/src/mainboard/lenovo/g505s/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index bb700e0de1..a9715d10a3 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -4,7 +4,7 @@ #include "mainboard.h" /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index c8ce7fdc53..312a621f19 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -3,7 +3,7 @@ #include "ec.h" -#include +#include #include #include diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index 0ab2c2f7c2..ab26ba784f 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index 2b9357e818..37ad7b8b79 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c index 94d192d3e1..10f72a61f9 100644 --- a/src/mainboard/lenovo/s230u/mainboard.c +++ b/src/mainboard/lenovo/s230u/mainboard.c @@ -10,7 +10,7 @@ #include #include "ec.h" -#include +#include static u8 mainboard_fill_ec_version(char *buf, u8 buf_len) { diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 653365ab2b..de7c9f97c4 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c index 81fb3d59ce..cbcf739430 100644 --- a/src/mainboard/lenovo/t400/cstates.c +++ b/src/mainboard/lenovo/t400/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include static acpi_cstate_t cst_entries[] = { { diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 001e91ece2..9144ad200d 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index 840dcd0a42..f2d70fcbba 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index c2624d4195..cecb4bde40 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index 63bfaf272f..bf45672aca 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include "dock.h" diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index a03b252ef5..0eedf51163 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index a03b252ef5..0eedf51163 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 583f9f3b8c..48a26e1c00 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index a03b252ef5..0eedf51163 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 94e70433df..3be8bda159 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -19,7 +19,7 @@ #define EC_LENOVO_H8_ME_WORKAROUND 1 #define THINKPAD_EC_GPE 17 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index a03b252ef5..0eedf51163 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index a03b252ef5..0eedf51163 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 51ff3361b2..222a5f9243 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -6,7 +6,7 @@ #define BRIGHTNESS_DOWN \BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index aba0a9bfe8..846aa07d36 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT diff --git a/src/mainboard/lenovo/thinkcentre_a58/cstates.c b/src/mainboard/lenovo/thinkcentre_a58/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cstates.c +++ b/src/mainboard/lenovo/thinkcentre_a58/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index 8880ba7076..8e1656b224 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 1c237fef40..bdacd20b5b 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index ce856126cd..de195e6aca 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -8,7 +8,7 @@ #define EC_LENOVO_H8_ME_WORKAROUND 1 #define EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 653365ab2b..de7c9f97c4 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c index 81fb3d59ce..cbcf739430 100644 --- a/src/mainboard/lenovo/x200/cstates.c +++ b/src/mainboard/lenovo/x200/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include static acpi_cstate_t cst_entries[] = { { diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index abe1c27360..9f6f22de33 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -6,7 +6,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index 840dcd0a42..f2d70fcbba 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index c2624d4195..cecb4bde40 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index a03b252ef5..0eedf51163 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 4efe15a03f..a7716a507f 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index a03b252ef5..0eedf51163 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -7,7 +7,7 @@ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 78a51d3435..42a8d91a93 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -6,7 +6,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 14080f5f05..5d129bb360 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -12,7 +12,7 @@ #include "dock.h" #include #include -#include +#include #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl index 624806ca04..77b1afe7f9 100644 --- a/src/mainboard/libretrend/lt1000/dsdt.asl +++ b/src/mainboard/libretrend/lt1000/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index 5ce62c7cff..aa7864832f 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index a53490323a..495f7a8647 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 2c56e08464..4c4f0a8725 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/lippert/toucan-af/acpi/routing.asl b/src/mainboard/lippert/toucan-af/acpi/routing.asl index ae3c0008bb..62180ea2f7 100644 --- a/src/mainboard/lippert/toucan-af/acpi/routing.asl +++ b/src/mainboard/lippert/toucan-af/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl index a53490323a..495f7a8647 100644 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ b/src/mainboard/lippert/toucan-af/acpi/usb.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 14aa8654b9..3422ee0a92 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index ca6f5a0d3a..e46f606b6a 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/msi/ms7721/acpi/cpstate.asl b/src/mainboard/msi/ms7721/acpi/cpstate.asl index 86361521a2..9e7fdcf706 100644 --- a/src/mainboard/msi/ms7721/acpi/cpstate.asl +++ b/src/mainboard/msi/ms7721/acpi/cpstate.asl @@ -7,7 +7,7 @@ * characteristics. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { Scope (\_SB) { diff --git a/src/mainboard/msi/ms7721/acpi_tables.c b/src/mainboard/msi/ms7721/acpi_tables.c index 3eb63c8920..a311f72b80 100644 --- a/src/mainboard/msi/ms7721/acpi_tables.c +++ b/src/mainboard/msi/ms7721/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index 5fb15eac9a..d14091792e 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl index 3dc45d5f2c..6013bfb2ad 100644 --- a/src/mainboard/ocp/sonorapass/dsdt.asl +++ b/src/mainboard/ocp/sonorapass/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include DefinitionBlock( diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 9d33865271..717597c379 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -14,7 +14,7 @@ */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c index 00a54db816..f6fb273747 100644 --- a/src/mainboard/ocp/tiogapass/fadt.c +++ b/src/mainboard/ocp/tiogapass/fadt.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include void motherboard_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index f14a9eeda9..db71348823 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index d318bfc9d8..a6f72e4b46 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl index 27a737c730..734f821bba 100644 --- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/pcengines/apu1/acpi_tables.c b/src/mainboard/pcengines/apu1/acpi_tables.c index 02afbdbc5a..de2336efad 100644 --- a/src/mainboard/pcengines/apu1/acpi_tables.c +++ b/src/mainboard/pcengines/apu1/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index 97e0e28143..e5a4ecef5e 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl index 7167de7477..cf0961af68 100644 --- a/src/mainboard/pcengines/apu2/acpi/routing.asl +++ b/src/mainboard/pcengines/apu2/acpi/routing.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl index b7757d3950..f6d8c9226b 100644 --- a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl @@ -3,7 +3,7 @@ /* simple name description */ /* -#include +#include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 ) { diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index 243a4a621d..16df3ea104 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index cc6c03d08a..8827a3727f 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ /* DefinitionBlock Statement */ -#include +#include DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index ae5aaf1f0f..45fb909057 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl index cecd8bc606..d00b1b1a8f 100644 --- a/src/mainboard/portwell/m107/dsdt.asl +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #define SDCARD_CD 81 /* Not used */ diff --git a/src/mainboard/protectli/vault_bsw/dsdt.asl b/src/mainboard/protectli/vault_bsw/dsdt.asl index 34f93fa229..8e0c7a9cc1 100644 --- a/src/mainboard/protectli/vault_bsw/dsdt.asl +++ b/src/mainboard/protectli/vault_bsw/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl index 624806ca04..77b1afe7f9 100644 --- a/src/mainboard/protectli/vault_kbl/dsdt.asl +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 84263cc397..cc3b003e52 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 9f4aa03db1..be2b3066ff 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 5ef19e12f6..43c6983f30 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index 1900877096..1d97b24450 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/roda/rk886ex/cstates.c b/src/mainboard/roda/rk886ex/cstates.c index 10498e1150..f52dae852a 100644 --- a/src/mainboard/roda/rk886ex/cstates.c +++ b/src/mainboard/roda/rk886ex/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index c58f89558c..a7ae9e83af 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index fca8cb7953..04b9632a69 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c index 6fb09967f0..f994143884 100644 --- a/src/mainboard/roda/rk9/cstates.c +++ b/src/mainboard/roda/rk9/cstates.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include static acpi_cstate_t cst_entries[] = { { diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index de5b1dd2b9..a1cb6e35b3 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index edcb3539b1..5f4bf1b2e0 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index ae251a16d1..eba6d32ed2 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 7e6e5593d1..ca2f560bf5 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index 10aa1f7453..9d5c7c654e 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index 9e7e5bba42..c3bce8a490 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 3fe88fb053..2fb012d391 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include "ec.h" #include "onboard.h" diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 99efad94b0..74e044d71f 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index b5bb0ef684..3585db1ab3 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 9b56890403..dede546349 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 3f511a16c5..1f9c748b3b 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 8b23ee7b85..72204e089d 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -16,7 +16,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 813bad943f..f9408f1b9d 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index 8c6c00d521..cf26e32905 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index 8b38b3434c..370dfd4663 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index a13f387a95..6a824dfd74 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 9b4cb92bfb..deed223366 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include DefinitionBlock("dsdt.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181220) { diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index 8cff20f84d..52f3d775f0 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl index b6c8930cb6..e1dc9db971 100644 --- a/src/mainboard/supermicro/x9scl/dsdt.asl +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl index 64d5399011..818b05a5cb 100644 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ b/src/mainboard/system76/lemp9/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl index 11ad0bb47e..7363974716 100644 --- a/src/mainboard/up/squared/dsdt.asl +++ b/src/mainboard/up/squared/dsdt.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 9700ff727d..30755d13bc 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index e861b9804d..5a2f266fde 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 7852b5eb3a..dd07aa5463 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 1ead42c92e..5d832eaf4b 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index e3d753a93d..8bb64b761a 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index fa49fc934e..74fd8c61b1 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -4,8 +4,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 03230a53ae..e8944669a3 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index bdd0ed0822..c81d21f0d0 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 5f6c8a1c4f..d566120827 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include "chip.h" diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 5b68a7398a..9bfb4e99bb 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index f4d9d65421..a66847d6a9 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include "haswell.h" diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index f7c6883852..552f032de5 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index e1258e04aa..1c7eabcb57 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -2,8 +2,8 @@ /* This file is part of the coreboot project. */ #include -#include -#include +#include +#include #include #include #include "i945.h" diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 3fd3db69df..c080d0cbd5 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include "i945.h" diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index c1ee207bf1..7384223c0d 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 54c42cf481..cf91f1ea65 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index b24356361f..af4bfb8ef5 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 77aa8149da..3ae44b8b36 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ea2a737c2c..e947bc5613 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index fb1ebab753..67fc93334b 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -3,8 +3,8 @@ #include #include -#include -#include +#include +#include #include #include "x4x.h" diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 054d2aa2ed..8aab1f63bd 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 75c31abace..4504780f48 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include /* Helper to find free space for memset_pae. */ static uintptr_t get_free_memory_range(struct memranges *mem, diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 9d8da6e4a3..105d77b0f6 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 6715a43296..a3f8a969e6 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 2028f09335..00a5aea977 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 71e29cdd22..3304f93e7f 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -10,7 +10,7 @@ #define MMIO_ACPI_PM1_STS 0x00 #define MMIO_ACPI_PM1_EN 0x02 #define MMIO_ACPI_PM1_CNT_BLK 0x04 - /* sleep types defined in arch/x86/include/arch/acpi.h */ + /* sleep types defined in arch/x86/include/acpi/acpi.h */ #define ACPI_PM1_CNT_SCIEN BIT(0) #define MMIO_ACPI_PM_TMR_BLK 0x08 #define MMIO_ACPI_CPU_CONTROL 0x0c diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 2d7954fba2..8d4ff6c449 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 6cdae6b5ab..663f1e7629 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 191e79903e..5221b7486a 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 1959d3d860..b4954c8818 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 8e34c85f52..357dbcacb8 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -7,8 +7,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 7c6823239c..c206b2e054 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -11,7 +11,7 @@ #include #include #include -#include +#include struct soc_amd_picasso_config { /* @@ -33,7 +33,7 @@ struct soc_amd_picasso_config { I2S_PINS_UNCONF = 7, /* All pads will be input mode */ } acp_pin_cfg; - /* Options for these are in src/arch/x86/include/arch/acpi.h */ + /* Options for these are in src/arch/x86/include/acpi/acpi.h */ uint8_t fadt_pm_profile; uint16_t fadt_boot_arch; uint32_t fadt_flags; diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 09e9b6b4b4..15af741ea1 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 25dab397c0..454d0c2283 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 68321fffae..c90ce468f1 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -4,7 +4,7 @@ #ifndef __SOC_PICASSO_ACPI_H__ #define __SOC_PICASSO_ACPI_H__ -#include +#include #ifndef FADT_PM_PROFILE #define FADT_PM_PROFILE PM_UNSPECIFIED diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index cdea0058a8..64e61c04e8 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 35d46bcfb6..0f484d22b6 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -4,8 +4,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/soc/amd/picasso/pmutil.c b/src/soc/amd/picasso/pmutil.c index a38acf2461..1db9d00a5d 100644 --- a/src/soc/amd/picasso/pmutil.c +++ b/src/soc/amd/picasso/pmutil.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 329429ef48..8af5821ef2 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index d399c7d230..cf04c2eace 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index cc9f634959..15b48583fe 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -7,8 +7,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 22c8cc6547..ad89df437f 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -9,7 +9,7 @@ #include #include #include -#include +#include #define MAX_NODES 1 #if CONFIG(AMD_APU_MERLINFALCON) diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 09e9b6b4b4..15af741ea1 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 852930a88d..5206b40537 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 6a74f22f58..95477489b6 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -4,7 +4,7 @@ #ifndef __SOC_STONEYRIDGE_ACPI_H__ #define __SOC_STONEYRIDGE_ACPI_H__ -#include +#include #if CONFIG(STONEYRIDGE_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 44f43b4717..14559b9b99 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 2aa16b6853..135abefe91 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -6,8 +6,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index a38acf2461..1db9d00a5d 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9c3154107a..131a268993 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 2b8afa7a88..6e5e79bded 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 93c8792c3e..944d853646 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c4e068d41f..0b2de52fbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 73f5614852..1e60683b37 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include "chip.h" diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index e375f409f5..3b41d73a18 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index b3ee7a0d49..207d1ef6d8 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -17,7 +17,7 @@ #define _SOC_APOLLOLAKE_PM_H_ #include -#include +#include #include #include diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 3d0d4593dd..4a33b6c63e 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -15,7 +15,7 @@ #define __SIMPLE_DEVICE__ -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 426c2de95a..eb94d39f59 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index dc9855ddf8..06534d06ab 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 1401649552..6ce90a4b5a 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index 3da67ebf76..842049a283 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -4,7 +4,7 @@ #ifndef _BAYTRAIL_ACPI_H_ #define _BAYTRAIL_ACPI_H_ -#include +#include #include void acpi_fill_in_fadt(acpi_fadt_t *fadt); diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index 0161f67038..274e7a75b6 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -4,7 +4,7 @@ #ifndef _BAYTRAIL_PMC_H_ #define _BAYTRAIL_PMC_H_ -#include +#include #define IOCOM1 0x3f8 diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index d83be9f826..64d528f1cb 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aa56a2ebb2..e815a9730d 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9036e103fc..7147f18449 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 5f6dce875f..39803dea4e 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 3ebf8fff2a..68b8c0e0bb 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 3f83e08a4c..7f651b30ee 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include @@ -26,7 +26,7 @@ #include #include #include "chip.h" -#include +#include static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 473be2fcc3..347c796414 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1c9d6b3e9b..0954e58c95 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 615117c613..6f35d064dd 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 997b7e920c..ef476456af 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -4,7 +4,7 @@ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ -#include +#include #include void acpi_create_serialio_ssdt(acpi_header_t *ssdt); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index f3397aaa4b..2ca2b5d1b1 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -4,7 +4,7 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ -#include +#include #define IOCOM1 0x3f8 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 3222faf814..5dca249e0b 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 1ca8bdaccc..aaa6e480f9 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index e2d9a3b101..5d6ecab8c4 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 9b5784c2b5..14c42022dc 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include "chip.h" diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 503e1799b5..8afdba158a 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index b030d44c39..294fbdef9d 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 2d39707f78..049393c9a5 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -4,7 +4,7 @@ #ifndef _BROADWELL_ACPI_H_ #define _BROADWELL_ACPI_H_ -#include +#include #include /* P-state configuration */ diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index ea6beb15f1..5f512b8d4e 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -4,7 +4,7 @@ #ifndef _BROADWELL_PM_H_ #define _BROADWELL_PM_H_ -#include +#include /* ACPI_BASE_ADDRESS / PMBASE */ diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index af3be9e132..4b4969ccb4 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include static void pch_enable_ioapic(struct device *dev) diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index afe9c82705..e6f3849f03 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -9,7 +9,7 @@ * not used unless the console loglevel is high enough. */ -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 910df61795..cecac7fe4b 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -6,7 +6,7 @@ * and the differences between PCH variants. */ -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index a0c6e4f497..2849d3c254 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index f54a4947a2..8c0b726bd3 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 8b5dc0cc60..ac1008b2b1 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 2eb82a20a8..10fa9214b9 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 39f3fe1de6..5604186c11 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 1ecbb67098..57270b428b 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 7d4fcc39c9..4068ea10e9 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -127,7 +127,7 @@ #if !defined(__ACPI__) -#include +#include #include #include #include diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index 9ac03c99ad..eac68ab9c2 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index e426fae95e..905032fa77 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 4e28b44740..d3e109f936 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index cb10f1f10d..2d0fecf3b0 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -16,7 +16,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_ACPI_H #define SOC_INTEL_COMMON_BLOCK_ACPI_H -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/include/intelblocks/sd.h b/src/soc/intel/common/block/include/intelblocks/sd.h index d0a160de29..25ce242354 100644 --- a/src/soc/intel/common/block/include/intelblocks/sd.h +++ b/src/soc/intel/common/block/include/intelblocks/sd.h @@ -4,7 +4,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SD_H #define SOC_INTEL_COMMON_BLOCK_SD_H -#include +#include /* * Fill the GPIO Interrupt or I/O information that will be used for the diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index d466e3684b..c7a70e6fc7 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 9a0387b493..731c50b195 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -439,7 +439,7 @@ int platform_is_resuming(void) return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; } -/* Read and clear GPE status (defined in arch/acpi.h) */ +/* Read and clear GPE status (defined in acpi/acpi.h) */ int acpi_get_gpe(int gpe) { int bank; diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 00946b304d..57f39f02e3 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 8e44738da5..be7fd2033f 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 9498060c5e..3c607e5ab6 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index c293f8ab08..bab2c0f436 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/common/tpm_tis.c b/src/soc/intel/common/tpm_tis.c index 77262b6036..bb0aea0c98 100644 --- a/src/soc/intel/common/tpm_tis.c +++ b/src/soc/intel/common/tpm_tis.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include int tis_plat_irq_status(void) diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 5b21018b6c..845a8ce0cd 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 6f43288457..1d4bcfc520 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index fbe2b8264f..16175e7317 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index ae184e92b0..b9edfea63c 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -4,7 +4,7 @@ #ifndef _DENVERTON_NS_ACPI_H_ #define _DENVERTON_NS_ACPI_H_ -#include +#include #include void acpi_create_serialio_ssdt(acpi_header_t *ssdt); diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 9e03c03432..04d0fccf0e 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -5,7 +5,7 @@ #define _DENVERTON_NS_PM_H_ #include -#include +#include #define GPE_MAX 127 diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index b1f045a821..e976b8d772 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 2ba4531deb..d868d3eef2 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index ca74ab3b08..5bc4ff21a6 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index b8192c95b6..175b3ceefa 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index cb59a21b7b..be7198fdfa 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -127,7 +127,7 @@ #if !defined(__ACPI__) -#include +#include #include #include #include diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index b390968708..6db6ec8440 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index b8192c95b6..175b3ceefa 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index f1da3a81f4..10a658658d 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -127,7 +127,7 @@ #if !defined(__ACPI__) -#include +#include #include #include #include diff --git a/src/soc/intel/quark/include/soc/acpi.h b/src/soc/intel/quark/include/soc/acpi.h index 1b8dfa0b3d..6dccc3044a 100644 --- a/src/soc/intel/quark/include/soc/acpi.h +++ b/src/soc/intel/quark/include/soc/acpi.h @@ -4,8 +4,8 @@ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ -#include -#include +#include +#include void acpi_fill_in_fadt(acpi_fadt_t *fadt); diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 2c0df5eaf4..4ce4cb5058 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -5,7 +5,7 @@ #define _SOC_PM_H_ #include -#include +#include struct chipset_power_state { uint32_t prev_sleep_state; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 5ba683f47b..789af1d9e6 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9df078bad8..b731baff8d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 892f26212b..387bd6fe3d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -5,7 +5,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index f63220e13b..9b0369773d 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -4,7 +4,7 @@ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ -#include +#include #include /* P-state configuration */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 94b8d3e447..083783f346 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -4,7 +4,7 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 649cb25b58..f9dfa8b2b5 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -6,7 +6,7 @@ * and the differences between PCH variants. */ -#include +#include #include #include #include diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index a331b722a7..58c8e9ccf1 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index eaa07c394a..bbf36ca6a3 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -19,7 +19,7 @@ * Chapter number: 4 */ -#include +#include #include #include #include diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index 3004b4a732..c42e280ed1 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -133,7 +133,7 @@ #if !defined(__ACPI__) -#include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 0fe471c558..6260c73eb1 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index a7a4c54e7f..f0b7ddf110 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 9c5c7495f2..98cdd99545 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h index a34cd39698..3d32cd104a 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h @@ -17,7 +17,7 @@ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ -#include +#include #include #define MEM_BLK_COUNT 0x140 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 8ba4b29688..a27550c90c 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -6,7 +6,7 @@ #include #include -#include +#include #include struct iiostack_resource { diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 0baaa9c5c8..be724434cb 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 0b579842a6..56879a3418 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c index 46ce0cf07b..eeb37809fc 100644 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include "hudson.h" int acpi_get_sleep_type(void) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index cf7f3f5fa5..256a9c5b7b 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -5,7 +5,7 @@ #include "cfg.h" #include -#include +#include /** * @brief South Bridge CIMx configuration diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 5cb1695c85..67de34829c 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index e4a1795ab4..b0ee037ae2 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -14,7 +14,7 @@ #include #include #include /* printk */ -#include +#include #include #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platform Specific Definitions */ diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index 25259eeacf..d25f391b13 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include #include "SBPLATFORM.h" diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 15fd6bb0c9..23239dd213 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 3a6b541733..00c8900550 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index c50758256b..c8f37a470a 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index dc5da793a3..241c1a0d83 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 35d71a4d07..1100544707 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b1f3bfe861..ae62638f1b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -9,7 +9,7 @@ * not used unless the console loglevel is high enough. */ -#include +#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 054c29f565..d240bf65d5 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -9,7 +9,7 @@ * not used unless the console loglevel is high enough. */ -#include +#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 0a236c6b7e..a452263645 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -4,7 +4,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H -#include +#include /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 20dafdfd38..d1a00f4498 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include #include diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index d425a74366..fe65afaea2 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #include #include diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index e5bbdab2fb..4f77bb0086 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -2,8 +2,8 @@ /* This file is part of the coreboot project. */ #include -#include -#include +#include +#include #include #include diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 6175302d54..d78e9cd2e8 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c index d44d6195ce..72df0ff86a 100644 --- a/src/southbridge/intel/common/pmclib.c +++ b/src/southbridge/intel/common/pmclib.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include "pmclib.h" diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7b27ce0cd5..3e3dca94f8 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 96fcefcebb..4b29e0fe4d 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -2,8 +2,8 @@ /* This file is part of the coreboot project. */ #include -#include -#include +#include +#include #include #include #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index db1071a041..03bbdccb76 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -16,7 +16,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bc492df15a..d1918657c8 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -23,8 +23,8 @@ #include #include #if CONFIG(HAVE_ACPI_TABLES) -#include -#include +#include +#include #endif #include "i82371eb.h" #include "chip.h" diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index 253433368e..45f0182edf 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include "i82371eb.h" diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 35a0bc249e..0b54fe7ec9 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -12,7 +12,7 @@ #ifndef I82801DX_H #define I82801DX_H -#include +#include #if !defined(__ASSEMBLER__) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index c81dabe1bc..c437cc8620 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index e54f2bd80f..3e9493fdbc 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -12,9 +12,9 @@ #include #include #include -#include +#include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 8765cc1584..072f60b106 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -12,9 +12,9 @@ #include #include #include -#include +#include #include -#include +#include #include #include #include "chip.h" diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 30be71fedc..6cf0c52611 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 77a8f7772b..e2658b32f9 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,9 +12,9 @@ #include #include #include -#include +#include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 4edf87e7c5..0b0a9f2d39 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -13,9 +13,9 @@ #include #include #include -#include +#include #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index c582048853..1b2e0162f6 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index ea641ee5fc..bcdb17a9bb 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -9,7 +9,7 @@ * not used unless the console loglevel is high enough. */ -#include +#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index fc20660e65..7e8306cce3 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -4,7 +4,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H -#include +#include /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 48e2a29bc8..315fb65f17 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include -#include +#include +#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index d19250cf6b..85d89501eb 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b5fb674a26..6db647c6bf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -11,14 +11,14 @@ #include #include #include -#include +#include #include #include #include #include "chip.h" #include "nvs.h" #include "pch.h" -#include +#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 4599c26cff..2c2c6ea3c9 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -9,7 +9,7 @@ * not used unless the console loglevel is high enough. */ -#include +#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d583992ab9..8707349242 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -4,7 +4,7 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H -#include +#include #define CROS_GPIO_DEVICE_NAME "LynxPoint" diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index a896b643c6..4b5d51dc2b 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include "ast2400.h" #include "chip.h" diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index 83cf074fe1..ca6b1bdf2c 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include /* Common enter/exit implementations */ diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index cffe0c3476..d992830621 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include static void generic_set_resources(struct device *dev) diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index 9ff02fb3af..90d4461960 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -5,8 +5,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index 9a620c97ee..95e2e27836 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -9,7 +9,7 @@ #if CONFIG(HAVE_ACPI_TABLES) #include -#include +#include #endif static void nct5539d_init(struct device *dev) diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index fe1da65db2..4f83d1029f 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include "nct5572d.h" diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index e04a9232ae..7d4e90cc74 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include "nct6791d.h" static void nct6791d_init(struct device *dev) diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 8f5975ba26..6feee5e9da 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 685062170d..54f88551e4 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include "w83667hg-a.h" diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 807bc05b41..1cc5dec404 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -5,7 +5,7 @@ #define MBOOT_H #include -#include +#include #include #include #include diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index abd5b67095..89bca785ab 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include +#include #if CONFIG(GENERIC_GPIO_LIB) #include #endif diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index 9562e7970b..297df1ee4a 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -7,7 +7,7 @@ #include #if CONFIG(HAVE_ACPI_RESUME) -#include +#include #endif static void elog_add_boot_reason(void *unused) diff --git a/util/autoport/main.go b/util/autoport/main.go index 9e62b565da..d0201de2c1 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -845,7 +845,7 @@ func main() { dsdt.WriteString( ` -#include +#include DefinitionBlock( "dsdt.aml", From fada3e56c4d896bcbf41280f0d20ed7c72000890 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 27 Apr 2020 00:14:05 +0200 Subject: [PATCH 1372/1463] mb/asus/p8h61-m_pro: Fix function of pin 70 The board uses the pin for Deep S5, but the code was setting 3VSBSW. Change-Id: I81c865358002e6af500658efea851ab8c8202950 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40737 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 0ad35776a9..ce6acadb8e 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -90,7 +90,7 @@ chip northbridge/intel/sandybridge irq 0xe5 = 0x06 irq 0xe6 = 0x0c irq 0xe7 = 0x11 - irq 0xf0 = 0x20 + irq 0xf0 = 0x00 irq 0xf2 = 0x5d end device pnp 2e.b on # HWM, LED From 3a3fb365a912d34d2cb3afdb5bd704ae4eaa0a59 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 27 Apr 2020 00:16:59 +0200 Subject: [PATCH 1373/1463] mb/asus/p8h61-m_pro: Disable SB-TSI base address SB-TSI is specific to AMD platforms, but this is an Intel board. Change-Id: I5eb7e3bc920103279dfca3a9ec14a41666404993 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40738 Reviewed-by: Paul Menzel Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index ce6acadb8e..2d1550da3c 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -95,7 +95,7 @@ chip northbridge/intel/sandybridge end device pnp 2e.b on # HWM, LED io 0x60 = 0x0290 - io 0x62 = 0x0200 + io 0x62 = 0x0000 end device pnp 2e.d on end # VID device pnp 2e.e off end # CIR WAKE-UP From 6099aa308b4f7984728b6be2f452b474c642ed6b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 27 Apr 2020 00:19:12 +0200 Subject: [PATCH 1374/1463] mb/asus/p8h61-m_pro: Disable SVID LDN The SVID functionality is not used on this mainboard. Turn it off. Change-Id: Iea891975b32d24f54edec9d8c36391ec60a37d0c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40739 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 2d1550da3c..71f2b41436 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -102,7 +102,7 @@ chip northbridge/intel/sandybridge device pnp 2e.f on # GPIO Push-Pull or Open-drain irq 0xf0 = 0x9d end - device pnp 2e.14 on end # SVID + device pnp 2e.14 off end # SVID device pnp 2e.16 on # Deep Sleep io 0x30 = 0x20 end From 00367b2243064268062cd094f43e1271fca09c5e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 23:00:41 -0700 Subject: [PATCH 1375/1463] acpi: Move ACPI table support out of arch/x86 (4/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 4/5 which gets rid of the placeholder header files that were added to temporarily include acpi/ header files from arch/header files. BUG=b:155428745 Change-Id: If6e8580c3c6433f9239e06a1dc7ba661b3f597e5 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40939 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Frans Hendriks Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Reviewed-by: Duncan Laurie --- src/arch/x86/include/arch/acpi.h | 4 ---- src/arch/x86/include/arch/acpi_device.h | 4 ---- src/arch/x86/include/arch/acpi_ivrs.h | 4 ---- src/arch/x86/include/arch/acpi_pld.h | 4 ---- src/arch/x86/include/arch/acpigen.h | 4 ---- src/arch/x86/include/arch/acpigen_dsm.h | 4 ---- src/arch/x86/include/arch/acpigen_ps2_keybd.h | 7 ------- 7 files changed, 31 deletions(-) delete mode 100644 src/arch/x86/include/arch/acpi.h delete mode 100644 src/arch/x86/include/arch/acpi_device.h delete mode 100644 src/arch/x86/include/arch/acpi_ivrs.h delete mode 100644 src/arch/x86/include/arch/acpi_pld.h delete mode 100644 src/arch/x86/include/arch/acpigen.h delete mode 100644 src/arch/x86/include/arch/acpigen_dsm.h delete mode 100644 src/arch/x86/include/arch/acpigen_ps2_keybd.h diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h deleted file mode 100644 index 35cf6c6b06..0000000000 --- a/src/arch/x86/include/arch/acpi.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h deleted file mode 100644 index 5c3199e7b7..0000000000 --- a/src/arch/x86/include/arch/acpi_device.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h deleted file mode 100644 index 032d253f08..0000000000 --- a/src/arch/x86/include/arch/acpi_ivrs.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h deleted file mode 100644 index 5076e39a71..0000000000 --- a/src/arch/x86/include/arch/acpi_pld.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h deleted file mode 100644 index cdac49fc1b..0000000000 --- a/src/arch/x86/include/arch/acpigen.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h deleted file mode 100644 index 0804ab975a..0000000000 --- a/src/arch/x86/include/arch/acpigen_dsm.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include diff --git a/src/arch/x86/include/arch/acpigen_ps2_keybd.h b/src/arch/x86/include/arch/acpigen_ps2_keybd.h deleted file mode 100644 index 894524a6ac..0000000000 --- a/src/arch/x86/include/arch/acpigen_ps2_keybd.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include From e5bcc72049aa59a41cbf3ec8aaaa8994c62a227b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 23:05:11 -0700 Subject: [PATCH 1376/1463] acpi: Move ACPI table support out of arch/x86 (5/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 5/5 which moves the addition of ACPI table related files from arch/x86/Makefile.inc to acpi/Makefile.inc. BUG=b:155428745 Change-Id: I8143fd37357aeb0561516450adddc6714d539ada Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40940 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Frans Hendriks Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Reviewed-by: Duncan Laurie --- src/acpi/Makefile.inc | 8 ++++++++ src/arch/x86/Makefile.inc | 9 --------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 068c592db7..09ff9f1e58 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -12,4 +12,12 @@ ramstage-y += acpigen_ps2_keybd.c ramstage-y += sata.c +ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c +endif +$(eval $(call asl_template,dsdt)) +ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c +endif + endif # CONFIG_GENERATE_ACPI_TABLES diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index aa1f5fef5f..c29d5edf23 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -281,15 +281,6 @@ endif ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/reset.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif -ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c -endif -$(eval $(call asl_template,dsdt)) -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c -endif -endif # CONFIG_GENERATE_ACPI_TABLES ramstage-libs ?= From 56eafbbc3ac6ea01a03daf4b54a989d3d44260ae Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 18:38:55 -0700 Subject: [PATCH 1377/1463] acpi: Make header #ifdefs consistent Now that all ACPI header files are moved to src/include/acpi, this change updates the #ifdef to __ACPI_${FILENAME}__. BUG=b:155428745 Change-Id: Id24ee35bac318278871a26f98be7092604de01c0 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40931 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/include/acpi/acpi.h | 6 +++--- src/include/acpi/acpi_device.h | 6 +++--- src/include/acpi/acpi_ivrs.h | 6 +++--- src/include/acpi/acpi_pld.h | 6 +++--- src/include/acpi/acpigen.h | 6 +++--- src/include/acpi/acpigen_dsm.h | 6 +++--- src/include/acpi/acpigen_ps2_keybd.h | 6 +++--- 7 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 5314d78197..95080b29c3 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -5,8 +5,8 @@ * coreboot ACPI support - headers and defines. */ -#ifndef __ASM_ACPI_H -#define __ASM_ACPI_H +#ifndef __ACPI_ACPI_H__ +#define __ACPI_ACPI_H__ /* * The type and enable fields are common in ACPI, but the @@ -1049,4 +1049,4 @@ int get_acpi_table_revision(enum acpi_tables table); #endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMC__) -#endif /* __ASM_ACPI_H */ +#endif /* __ACPI_ACPI_H__ */ diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index bc71e0264d..ede6a2a140 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef __ACPI_DEVICE_H -#define __ACPI_DEVICE_H +#ifndef __ACPI_ACPI_DEVICE_H__ +#define __ACPI_ACPI_DEVICE_H__ #include #include @@ -510,4 +510,4 @@ void acpi_dp_write(struct acpi_dp *table); */ void acpi_device_write_pci_dev(const struct device *dev); -#endif +#endif /* __ACPI_ACPI_DEVICE_H__ */ diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h index 83abfb63dc..c46fec95e6 100644 --- a/src/include/acpi/acpi_ivrs.h +++ b/src/include/acpi/acpi_ivrs.h @@ -9,8 +9,8 @@ * I/O Virtualization Reporting Structure (IVRS) */ -#ifndef __ARCH_ACPI_IVRS_H -#define __ARCH_ACPI_IVRS_H +#ifndef __ACPI_ACPI_IVRS_H__ +#define __ACPI_ACPI_IVRS_H__ /* I/O Virtualization Reporting Structure (IVRS) */ #define IVHD_BLOCK_TYPE_LEGACY__FIXED 0x10 @@ -140,4 +140,4 @@ typedef struct ivrs_ivhd_special { uint8_t variety; } __packed ivrs_ivhd_special_t; -#endif +#endif /* __ACPI_ACPI_IVRS_H__ */ diff --git a/src/include/acpi/acpi_pld.h b/src/include/acpi/acpi_pld.h index c518077597..26e3475836 100644 --- a/src/include/acpi/acpi_pld.h +++ b/src/include/acpi/acpi_pld.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef __ACPI_PLD_H -#define __ACPI_PLD_H +#ifndef __ACPI_ACPI_PLD_H__ +#define __ACPI_ACPI_PLD_H__ #include #include @@ -116,4 +116,4 @@ int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, /* Turn PLD structure into a 20 byte ACPI buffer */ int acpi_pld_to_buffer(const struct acpi_pld *pld, uint8_t *buf, int buf_len); -#endif +#endif /* __ACPI_ACPI_PLD_H__ */ diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 005ec6b096..37c2318a95 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef LIBACPI_H -#define LIBACPI_H +#ifndef __ACPI_ACPIGEN_H__ +#define __ACPI_ACPIGEN_H__ #include #include @@ -487,4 +487,4 @@ void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); -#endif +#endif /* __ACPI_ACPIGEN_H__ */ diff --git a/src/include/acpi/acpigen_dsm.h b/src/include/acpi/acpigen_dsm.h index c51c12b6e3..28b89746a7 100644 --- a/src/include/acpi/acpigen_dsm.h +++ b/src/include/acpi/acpigen_dsm.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#ifndef __ARCH_ACPIGEN_DSM_H__ -#define __ARCH_ACPIGEN_DSM_H__ +#ifndef __ACPI_ACPIGEN_DSM_H__ +#define __ACPI_ACPIGEN_DSM_H__ #include @@ -12,4 +12,4 @@ struct dsm_i2c_hid_config { void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config); -#endif /* __ARCH_ACPIGEN_DSM_H__ */ +#endif /* __ACPI_ACPIGEN_DSM_H__ */ diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h index c0228bca16..aeeacae700 100644 --- a/src/include/acpi/acpigen_ps2_keybd.h +++ b/src/include/acpi/acpigen_ps2_keybd.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __ACPIGEN_PS2_KEYBD_H__ -#define __ACPIGEN_PS2_KEYBD_H__ +#ifndef __ACPI_ACPIGEN_PS2_KEYBD_H__ +#define __ACPI_ACPIGEN_PS2_KEYBD_H__ #include @@ -38,4 +38,4 @@ void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, bool can_send_function_keys, bool has_numeric_keypad, bool has_scrnlock_key); -#endif /* __ACPIGEN_PS2_KEYBD_H__ */ +#endif /* __ACPI_ACPIGEN_PS2_KEYBD_H__ */ From bf4b7b057737884fe4ac3a92e8ccbee370165e80 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 18:08:16 -0700 Subject: [PATCH 1378/1463] acpi: Reorganize ACPI configs In order to the Kconfigs in the same directory where the corresponding code lives, this change moves ACPI_BERT to arch/x86/Kconfig and following configs to acpi/Kconfig: ACPI_CPU_STRING ACPI_HAVE_PCAT_8259 ACPI_NO_PCAT_8259 HAVE_ACPI_TABLES BUG=b:155428745 Change-Id: I289565f38e46bd106ff89685aaf8f57e53d9827a Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40932 Reviewed-by: HAOUAS Elyes Reviewed-by: Duncan Laurie Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/Kconfig | 12 ------------ src/acpi/Kconfig | 31 +++++++++++++++++++++++++++---- src/arch/x86/Kconfig | 15 ++------------- 3 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index cf4df18247..65404995c9 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -624,12 +624,6 @@ config GFXUMA help Enable Unified Memory Architecture for graphics. -config HAVE_ACPI_TABLES - bool - help - This variable specifies whether a given board has ACPI table support. - It is usually set in mainboard/*/Kconfig. - config HAVE_MP_TABLE bool help @@ -656,12 +650,6 @@ config ACPI_NHLT help Build support for NHLT (non HD Audio) ACPI table generation. -config ACPI_BERT - bool - depends on HAVE_ACPI_TABLES - help - Build an ACPI Boot Error Record Table. - #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 8c8bb87884..22e0323c52 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -1,14 +1,37 @@ # SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. +config ACPI_AMD_HARDWARE_SLEEP_VALUES + def_bool n + help + Provide common definitions for AMD hardware PM1_CNT register sleep + values. + +config ACPI_CPU_STRING + string + default "\\_SB.CP%02d" + depends on HAVE_ACPI_TABLES + help + Sets the ACPI name string in the processor scope as written by + the acpigen function. Default is \_SB.CPxx. Note that you need + the \ escape character in the string. + +config ACPI_HAVE_PCAT_8259 + def_bool y if !ACPI_NO_PCAT_8259 + config ACPI_INTEL_HARDWARE_SLEEP_VALUES def_bool n help Provide common definitions for Intel hardware PM1_CNT register sleep values. -config ACPI_AMD_HARDWARE_SLEEP_VALUES - def_bool n +config ACPI_NO_PCAT_8259 + bool help - Provide common definitions for AMD hardware PM1_CNT register sleep - values. + Selected by platforms that don't expose a PC/AT 8259 PIC pair. + +config HAVE_ACPI_TABLES + bool + help + This variable specifies whether a given board has ACPI table support. + It is usually set in mainboard/*/Kconfig. diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 11733bd05e..7e10f60c0e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -246,22 +246,11 @@ config SKIP_MAX_REBOOT_CNT_CLEAR Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successful boot. -config ACPI_NO_PCAT_8259 +config ACPI_BERT bool - help - Selected by platforms that don't expose a PC/AT 8259 PIC pair. - -config ACPI_HAVE_PCAT_8259 - def_bool y if !ACPI_NO_PCAT_8259 - -config ACPI_CPU_STRING - string - default "\\_SB.CP%02d" depends on HAVE_ACPI_TABLES help - Sets the ACPI name string in the processor scope as written by - the acpigen function. Default is \_SB.CPxx. Note that you need - the \ escape character in the string. + Build an ACPI Boot Error Record Table. config COLLECT_TIMESTAMPS_NO_TSC bool From 56a5ebf48d648f0df4bf338c441a79968734e5a5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 23:56:20 -0700 Subject: [PATCH 1379/1463] acpi: Remove acpi_ from filenames This change drops acpi_ prefix from filenames under src/acpi/. BUG=b:155428745 Change-Id: Iadda2b848701367e51f4f74706154f7e36a87df6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40941 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/acpi/Makefile.inc | 5 ++--- src/acpi/{acpi_device.c => device.c} | 0 src/acpi/{acpi_pld.c => pld.c} | 0 3 files changed, 2 insertions(+), 3 deletions(-) rename src/acpi/{acpi_device.c => device.c} (100%) rename src/acpi/{acpi_pld.c => pld.c} (100%) diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 09ff9f1e58..09b990603f 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -4,12 +4,11 @@ ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-y += acpi.c -ramstage-y += acpi_device.c -ramstage-y += acpi_pld.c ramstage-y += acpigen.c ramstage-y += acpigen_dsm.c ramstage-y += acpigen_ps2_keybd.c - +ramstage-y += device.c +ramstage-y += pld.c ramstage-y += sata.c ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) diff --git a/src/acpi/acpi_device.c b/src/acpi/device.c similarity index 100% rename from src/acpi/acpi_device.c rename to src/acpi/device.c diff --git a/src/acpi/acpi_pld.c b/src/acpi/pld.c similarity index 100% rename from src/acpi/acpi_pld.c rename to src/acpi/pld.c From c0bff9755f12a6de9b15faf1498a096cf699d310 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 19:19:33 -0700 Subject: [PATCH 1380/1463] acpi: Update sata files to be more aligned with rest of acpi files This change moves sata.h to include/acpi/acpi_sata.h to align with the rest of the acpi header files in include/acpi. BUG=b:155428745 Change-Id: I3f97e5c12535a331d7347c0ecad00b07b5f13f37 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40933 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie --- src/acpi/sata.c | 3 +-- src/{acpi/sata.h => include/acpi/acpi_sata.h} | 0 src/southbridge/intel/bd82x6x/sata.c | 2 +- src/southbridge/intel/ibexpeak/sata.c | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) rename src/{acpi/sata.h => include/acpi/acpi_sata.h} (100%) diff --git a/src/acpi/sata.c b/src/acpi/sata.c index f2f53e6f64..110742e84c 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include "sata.h" - #include #include +#include /* e.g. * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); diff --git a/src/acpi/sata.h b/src/include/acpi/acpi_sata.h similarity index 100% rename from src/acpi/sata.h rename to src/include/acpi/acpi_sata.h diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index e65fd6ecae..57eb7e75a1 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include "chip.h" diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 11ac078c83..df13989f4a 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include "chip.h" From 40a3888128f6cd967666eaaf158c40185368baf9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 1 May 2020 10:43:48 -0700 Subject: [PATCH 1381/1463] soc/amd/picasso: Select CHROMEOS_RAMOOPS_DYNAMIC For boards that select CHROMEOS, select CHROMEOS_RAMOOPS_DYNAMIC by default. BUG=b:155345589 Change-Id: Id215f3a2c8d1e9e713a628283af9586a1f117ef4 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40949 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index c807ad4c7d..3d699667fe 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -198,6 +198,9 @@ config ACPI_BERT_SIZE Specify the amount of DRAM reserved for gathering the data used to generate the ACPI table. +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + config RO_REGION_ONLY string depends on CHROMEOS From 336d9a214843c4312eea9f00f2ce7c74ca87500b Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Wed, 29 Apr 2020 16:16:26 -0400 Subject: [PATCH 1382/1463] sb/intel/i82371eb: Move wakeup code to romstage This code is needed in romstage, not ramstage. Change-Id: Ic38c3c50fb135fba582864a242348ec29cec2991 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40965 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/i82371eb/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 1a1a0a10ea..327c424433 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -24,8 +24,8 @@ ramstage-y += usb.c ramstage-y += smbus.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c romstage-y += early_smbus.c From 67c73110e96ec6f1ec90c12f1ed6aac95107e896 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Thu, 16 Apr 2020 20:45:30 -0400 Subject: [PATCH 1383/1463] nb/intel/i440bx: Resolve a SMP-raminit TODO Change-Id: I0087294bccee079368c93ba8986873a5e65593b0 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40957 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/northbridge/intel/i440bx/raminit.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index dddcc217f4..ee1e75902e 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -123,8 +123,11 @@ static const u8 register_values[] = { * [01:00] Reserved */ NBXCFG + 0, 0x0c, - // TODO: Bit 15 should be 0 for multiprocessor boards +#if CONFIG(SMP) + NBXCFG + 1, 0x00, +#else NBXCFG + 1, 0x80, +#endif NBXCFG + 2, 0x00, NBXCFG + 3, 0xff, From 095f927016b64adcfb35800725389cf87409e30e Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Fri, 24 Apr 2020 16:05:02 -0400 Subject: [PATCH 1384/1463] nb/intel/i440bx: Drop northbridge.h It declares a function that was either never or no longer implemented. Change-Id: I714d39374519bff1afb94870d0e84f57db619a1f Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40958 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/northbridge/intel/i440bx/northbridge.c | 1 - src/northbridge/intel/i440bx/northbridge.h | 21 --------------------- 2 files changed, 22 deletions(-) delete mode 100644 src/northbridge/intel/i440bx/northbridge.h diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index da0107c962..d0c93fd35d 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -8,7 +8,6 @@ #include #include #include -#include "northbridge.h" #include "i440bx.h" static void northbridge_init(struct device *dev) diff --git a/src/northbridge/intel/i440bx/northbridge.h b/src/northbridge/intel/i440bx/northbridge.h deleted file mode 100644 index f42211e66a..0000000000 --- a/src/northbridge/intel/i440bx/northbridge.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_440BX_H -#define NORTHBRIDGE_INTEL_440BX_H - -extern unsigned int i440bx_scan_root_bus(struct device *root, unsigned int max); - -#endif /* NORTHBRIDGE_INTEL_440BX_H */ From 11bce2059bd79199003b2c3a4fbe1d7a89492e34 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Fri, 17 Apr 2020 12:49:49 -0400 Subject: [PATCH 1385/1463] nb/intel/i440bx: Use SPDX for remaining files Change-Id: I0d28f1fc835fc05b4fc3ab891e9e6e340848aa49 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40959 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/northbridge/intel/i440bx/Makefile.inc | 14 +------------- src/northbridge/intel/i440bx/i440bx.h | 16 ++-------------- src/northbridge/intel/i440bx/raminit.c | 16 ++-------------- src/northbridge/intel/i440bx/raminit.h | 16 ++-------------- src/northbridge/intel/i440bx/romstage.c | 15 ++------------- 5 files changed, 9 insertions(+), 68 deletions(-) diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 708a41f6e8..6270811469 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -1,17 +1,5 @@ -## +## SPDX-License-Identifier: GPL-2.0-or-later ## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 3a2b3f4f4b..1b58003478 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_I440BX_I440BX_H #define NORTHBRIDGE_INTEL_I440BX_I440BX_H diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index ee1e75902e..18997c52ea 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index dcc800713f..534bc447a3 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_H #define RAMINIT_H diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index bdcfdc9b85..69cfa7fb38 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include From 0e0fdbef1cc7753b836321aa72f4bb71613d124e Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Wed, 29 Apr 2020 12:47:41 -0400 Subject: [PATCH 1386/1463] nb/intel/i440bx: Ready raminit for S3 resume path Change-Id: I77e95850af82a5684ba10841260db021f5de1e8b Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40960 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i440bx/raminit.c | 2 +- src/northbridge/intel/i440bx/raminit.h | 2 +- src/northbridge/intel/i440bx/romstage.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 18997c52ea..d1e0f40ac1 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1004,7 +1004,7 @@ static void sdram_enable(void) void __weak enable_spd(void) { } void __weak disable_spd(void) { } -void sdram_initialize(void) +void sdram_initialize(int s3resume) { timestamp_add_now(TS_BEFORE_INITRAM); enable_spd(); diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 534bc447a3..e9099de2e9 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -9,7 +9,7 @@ void enable_spd(void); void disable_spd(void); -void sdram_initialize(void); +void sdram_initialize(int s3resume); void mainboard_enable_serial(void); /* Debug */ diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index 69cfa7fb38..199cf5cf0c 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -10,6 +10,6 @@ void mainboard_romstage_entry(void) { i82371eb_early_init(); - sdram_initialize(); + sdram_initialize(0); cbmem_initialize_empty(); } From 576315e1bec889a76ec14875a4e8037495cc173e Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Thu, 30 Apr 2020 21:30:36 -0400 Subject: [PATCH 1387/1463] asus/p2b: Enable IDE and UDMA for all variants There's no reason not to. Change-Id: I12c9e0f66c437d8add5c4096fd2a5e747d082799 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40961 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/asus/p2b/devicetree.cb | 8 ++++---- src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb | 8 -------- src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb | 8 -------- 3 files changed, 4 insertions(+), 20 deletions(-) diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 9dcd1da1db..9f7f63e5f3 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -46,10 +46,10 @@ chip northbridge/intel/i440bx # Northbridge register "ide1_enable" = "1" register "ide_legacy_enable" = "1" # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" register "thrm_polarity" = "1" register "lid_polarity" = "1" end diff --git a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb index 742414411b..ce36ce60d0 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb @@ -17,14 +17,6 @@ chip northbridge/intel/i440bx # Northbridge end end end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" end end end diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb index 6eabe5897b..b261a3514f 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb @@ -18,14 +18,6 @@ chip northbridge/intel/i440bx # Northbridge end end device pci 6.0 on end # Onboard SCSI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" end end end From f49f4d48ba12bea159a30ae2d2e761ca15c04a5e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 16:33:55 +0200 Subject: [PATCH 1388/1463] nb/intel/i945/memmap: Convert to 96 characters line length Also remove an extra star in comment. Change-Id: I2ef938573e75022dcb31c935dde7d3055e7a53f0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40802 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/i945/memmap.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index ee9f100fee..0183ea2b3f 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -65,11 +65,10 @@ void *cbmem_top_chipset(void) return (void *) top_of_ram; } -/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +/* Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) { - static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, - 48, 64 }; + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64 }; if (gms >= ARRAY_SIZE(ggc2uma)) die("Bad Graphics Mode Select (GMS) setting.\n"); @@ -91,9 +90,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - } From fbcfefe5f3f85daff84a454f822fe6c8ca4c02af Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 29 Apr 2020 22:51:31 +0200 Subject: [PATCH 1389/1463] mb/**/dsdt.asl: Drop unused ACPI_VIDEO_DEVICE It is only used with the Lenovo-specific H8 EC code. Change-Id: I596d4d19277555894ab728e32a44e34a5a21e21d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40863 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/apple/macbook21/dsdt.asl | 1 - src/mainboard/apple/macbookair4_2/dsdt.asl | 2 +- src/mainboard/asrock/b75pro3-m/dsdt.asl | 2 +- src/mainboard/asus/p8h61-m_pro/dsdt.asl | 1 - src/mainboard/asus/p8z77-m_pro/dsdt.asl | 2 -- src/mainboard/compulab/intense_pc/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-h61m-series/dsdt.asl | 2 -- src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl | 2 +- src/mainboard/hp/snb_ivb_laptops/dsdt.asl | 2 +- src/mainboard/hp/z220_sff_workstation/dsdt.asl | 2 +- src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 2 +- 11 files changed, 7 insertions(+), 13 deletions(-) diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 77d6daf19f..eabb7a2429 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -3,7 +3,6 @@ #define BRIGHTNESS_UP \DSPC.BRTU #define BRIGHTNESS_DOWN \DSPC.BRTD -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include DefinitionBlock( diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 315fd4df1d..7913816b6b 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 6d9866e1b6..b83703cc4a 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index b77c2bac03..66608b061f 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index ce1d905b6c..21b3954774 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index f6d5d4a0b1..947e0535f8 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -4,7 +4,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index 1b7bf223bb..ce93c599b5 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 - #include DefinitionBlock( diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 5fc8201391..f093207a50 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 5fc8201391..f093207a50 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 5fc8201391..f093207a50 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 72204e089d..0b75683937 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -15,7 +15,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include DefinitionBlock( "dsdt.aml", From 822148c5e737b5c69758148ebc68f1a9faf8bfd3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 29 Apr 2020 22:58:39 +0200 Subject: [PATCH 1390/1463] treewide: Drop ACPI_VIDEO_DEVICE macro It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864 Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/ec/lenovo/h8/acpi/ec.asl | 5 ++--- src/mainboard/lenovo/l520/dsdt.asl | 1 - src/mainboard/lenovo/s230u/acpi/ec.asl | 2 +- src/mainboard/lenovo/s230u/dsdt.asl | 1 - src/mainboard/lenovo/t400/dsdt.asl | 1 - src/mainboard/lenovo/t410/dsdt.asl | 1 - src/mainboard/lenovo/t420/dsdt.asl | 1 - src/mainboard/lenovo/t420s/dsdt.asl | 1 - src/mainboard/lenovo/t430/dsdt.asl | 1 - src/mainboard/lenovo/t430s/dsdt.asl | 1 - src/mainboard/lenovo/t440p/dsdt.asl | 1 - src/mainboard/lenovo/t520/dsdt.asl | 1 - src/mainboard/lenovo/t530/dsdt.asl | 1 - src/mainboard/lenovo/t60/dsdt.asl | 1 - src/mainboard/lenovo/x131e/dsdt.asl | 1 - src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 1 - src/mainboard/lenovo/x200/dsdt.asl | 1 - src/mainboard/lenovo/x201/dsdt.asl | 1 - src/mainboard/lenovo/x220/dsdt.asl | 1 - src/mainboard/lenovo/x230/dsdt.asl | 1 - src/mainboard/lenovo/x60/dsdt.asl | 1 - util/autoport/bd82x6x.go | 4 ---- 22 files changed, 3 insertions(+), 27 deletions(-) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 45fa0a8a1b..366fd09f8e 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -141,13 +141,12 @@ Device(EC) BRIGHTNESS_DOWN() } -#ifdef ACPI_VIDEO_DEVICE /* Next display GPE */ Method(_Q16, 0, NotSerialized) { - Notify (ACPI_VIDEO_DEVICE, 0x82) + Notify (\_SB.PCI0.GFX0, 0x82) } -#endif + /* AC status change: present */ Method(_Q26, 0, NotSerialized) { diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index ab26ba784f..eb530ff5fc 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 22 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index c626350ab8..3db858f89f 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -117,7 +117,7 @@ Device (EC0) /* Video output switch hotkey */ Method (_Q16, 0, NotSerialized) { - Notify (ACPI_VIDEO_DEVICE, 0x82) + Notify (\_SB.PCI0.GFX0, 0x82) ^HKEY.MHKQ (0x1007) } diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index 37ad7b8b79..651cb749bb 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 23 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 9144ad200d..a44f8c32d4 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index cecb4bde40..d31b4597f2 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index 0eedf51163..dfa567c459 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index 0eedf51163..dfa567c459 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 48a26e1c00..a996e1d779 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index 0eedf51163..dfa567c459 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 3be8bda159..04fd79392f 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -15,7 +15,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define THINKPAD_EC_GPE 17 diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 0eedf51163..dfa567c459 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 0eedf51163..dfa567c459 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 222a5f9243..89bb39cd2b 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \BRTU #define BRIGHTNESS_DOWN \BRTD -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include DefinitionBlock( diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index bdacd20b5b..f82ef1987d 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 22 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index de195e6aca..52fe1cc7e5 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT 1 diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 9f6f22de33..f892267205 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include DefinitionBlock( diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index cecb4bde40..d31b4597f2 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 0eedf51163..dfa567c459 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 0eedf51163..dfa567c459 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 42a8d91a93..8cf6ca81fb 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include DefinitionBlock( diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 87e7584743..9f37aeef4f 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -192,10 +192,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { DSDTDefine{ Key: "BRIGHTNESS_DOWN", Value: "\\_SB.PCI0.GFX0.DECB", - }, - DSDTDefine{ - Key: "ACPI_VIDEO_DEVICE", - Value: "\\_SB.PCI0.GFX0", }) /* SPI init */ From bf59fac286653dc60f2279cd01194de729d3e789 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 29 Apr 2020 23:05:39 +0200 Subject: [PATCH 1391/1463] mb/**/dsdt.asl: Drop unused BRIGHTNESS_{UP,DOWN} It is only used with the Lenovo-specific H8 EC code. Change-Id: If3b209a9ab82a07ce7b4450d8a0b62a1ca86a95c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40865 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/apple/macbook21/dsdt.asl | 3 --- src/mainboard/apple/macbookair4_2/dsdt.asl | 3 --- src/mainboard/asrock/b75pro3-m/dsdt.asl | 3 --- src/mainboard/compulab/intense_pc/dsdt.asl | 4 ---- src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl | 3 --- src/mainboard/hp/snb_ivb_laptops/dsdt.asl | 3 --- src/mainboard/hp/z220_sff_workstation/dsdt.asl | 3 --- src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 3 --- 8 files changed, 25 deletions(-) diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index eabb7a2429..ee74281d2f 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \DSPC.BRTU -#define BRIGHTNESS_DOWN \DSPC.BRTD - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 7913816b6b..cdc0815f57 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index b83703cc4a..d6c4f5164b 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 947e0535f8..0febac1817 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ - -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index f093207a50..0febac1817 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index f093207a50..0febac1817 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index f093207a50..0febac1817 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 0b75683937..109e37204c 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -13,9 +13,6 @@ * GNU General Public License for more details. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include DefinitionBlock( "dsdt.aml", From 44e304abe11d87ba3bda7b566fe972aee96b159b Mon Sep 17 00:00:00 2001 From: Marco Chen Date: Wed, 29 Apr 2020 14:47:28 +0800 Subject: [PATCH 1392/1463] mb/google/dedede: Read DRAM part number from CBI The index of MEM_STRAPS will be migrated from per DRAM part number to per DRAM characteristic therefore one index mapped to a single SPD binary can represent to multiple DRAM part numbers as long as their characteristic is the same for DRAM controller to support. In this case, the real DRAM part number would be provisioned in the CBI instead of SPD in the factory flow. As a result, we need to extract DRAM part number from CBI. BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. check DRAM part number is correct in SMBIOS for memory device Change-Id: I40780a35e04efb279591e9db179cb86b5e907c0d Signed-off-by: Marco Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40836 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 7a700f4ff4..3155f70763 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,9 +6,13 @@ */ #include +#include +#include #include +#include #include #include +#include #include void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -22,3 +26,19 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } + +bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + + if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "No DRAM part number in CBI!\n"); + return false; + } + + + *part_num = &part_num_store[0]; + *len = strlen(part_num_store); + return true; +} From 7ba4ada8af425c3db4af212e7970bf2df0338633 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 1 May 2020 22:55:44 +0200 Subject: [PATCH 1393/1463] payloads/external/GRUB2: Makefile: fix check for changed files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The check for changed files, introduced in cb:36343 does not work (anymore?) due to the quotes. Thus, drop them. Signed-off-by: Michael Niewöhner Change-Id: Ie126e3d604990b2346f1f004f912080104e2789d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40953 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- payloads/external/GRUB2/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index f13c12892a..4dfedbe96e 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -17,8 +17,8 @@ checkout: echo " GIT GRUB2 $(NAME-y)" test -d $(project_dir) || git clone $(project_git_repo) $(project_dir) git -C $(project_dir) fetch -ifeq ("$(shell test -d $(project_dir) && \ - (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain))",) +ifeq ($(shell test -d $(project_dir) && \ + (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain),) git -C $(project_dir) checkout -f $(TAG-y) else echo "WARNING: index/tree not clean, skipping update / force checkout." From 7f9c064263811700329812e16828b5b97cf916e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 1 May 2020 23:01:28 +0200 Subject: [PATCH 1394/1463] payloads/external/GRUB2: Makefile: fix checkout hint MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The git checkout hint introduced in cb:36343 does not get printed but executed instead. Escape the single-quotes to fix this. Signed-off-by: Michael Niewöhner Change-Id: I1277c3788a141b25cd9f22ec0476ee56b64aea4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40954 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- payloads/external/GRUB2/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 4dfedbe96e..bb7b5f8457 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -22,7 +22,8 @@ ifeq ($(shell test -d $(project_dir) && \ git -C $(project_dir) checkout -f $(TAG-y) else echo "WARNING: index/tree not clean, skipping update / force checkout." - echo " Checkout manually with `git -C $(project_dir) checkout -f`." + echo " Checkout manually with "\ + "\`git -C payloads/external/GRUB2/$(project_dir) checkout -f\`." endif grub2/build/config.h: $(CONFIG_DEP) | checkout From 89ac87a976e2ace9a3637c99209adec492566d30 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Mon, 20 Apr 2020 18:45:22 +0530 Subject: [PATCH 1395/1463] security/vboot: Limit vboot verification code access to only verstage Make vboot verification code accessible in only verstage. Vboot verification code in vboot_logic.c is being used in verstage. Due to support function vboot_save_data(), so core functionality in vboot_logic.c is made available in romstage. The patch decouples the support function frm vboot_logic.c to limit itself to verstage. BUG=b:155544643 TEST=Verified on hatch Signed-off-by: Sridhar Siricilla Change-Id: Id1ede45c4dffe90afcef210eabaa657cf92a9335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40562 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Rizwan Qureshi --- src/security/vboot/Makefile.inc | 3 ++- src/security/vboot/vboot_common.c | 25 +++++++++++++++++++++++++ src/security/vboot/vboot_logic.c | 22 ---------------------- 3 files changed, 27 insertions(+), 23 deletions(-) diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 67ee0f5786..b452e937c9 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -112,16 +112,17 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c ifeq (${CONFIG_VBOOT_MOCK_SECDATA},y) verstage-y += secdata_mock.c romstage-y += secdata_mock.c +ramstage-y += secdata_mock.c else verstage-y += secdata_tpm.c romstage-y += secdata_tpm.c +ramstage-y += secdata_tpm.c endif ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) verstage-y += tpm_common.c endif -romstage-y += vboot_logic.c romstage-y += common.c ramstage-y += common.c diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 36cd1ade4e..049b4a9558 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -12,6 +12,31 @@ #include #include +#include "antirollback.h" + +void vboot_save_data(struct vb2_context *ctx) +{ + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED && + (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + printk(BIOS_INFO, "Saving secdata firmware\n"); + antirollback_write_space_firmware(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; + } + + if (ctx->flags & VB2_CONTEXT_SECDATA_KERNEL_CHANGED && + (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + printk(BIOS_INFO, "Saving secdata kernel\n"); + antirollback_write_space_kernel(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_KERNEL_CHANGED; + } + + if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { + printk(BIOS_INFO, "Saving nvdata\n"); + save_vbnv(ctx->nvdata); + ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; + } +} + /* Check if it is okay to enable USB Device Controller (UDC). */ int vboot_can_enable_udc(void) { diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index e1c77b6004..a8a7be55e7 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -209,28 +209,6 @@ static vb2_error_t hash_body(struct vb2_context *ctx, return VB2_SUCCESS; } -void vboot_save_data(struct vb2_context *ctx) -{ - if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED && - (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { - printk(BIOS_INFO, "Saving secdata firmware\n"); - antirollback_write_space_firmware(ctx); - ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; - } - - if (ctx->flags & VB2_CONTEXT_SECDATA_KERNEL_CHANGED && - (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { - printk(BIOS_INFO, "Saving secdata kernel\n"); - antirollback_write_space_kernel(ctx); - ctx->flags &= ~VB2_CONTEXT_SECDATA_KERNEL_CHANGED; - } - - if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { - printk(BIOS_INFO, "Saving nvdata\n"); - save_vbnv(ctx->nvdata); - ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; - } -} static uint32_t extend_pcrs(struct vb2_context *ctx) { From f87ff33a898e93012112bf9a446182ac7e024bc8 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 12 Sep 2019 17:18:20 +0530 Subject: [PATCH 1396/1463] soc/intel/common/block/cse: Add boot partition related APIs In CSE Firmware Custom SKU, CSE region is logically divided into 2 boot partitions. These boot partitions are represented by BP1(RO), BP2(RW). With CSE Firmware Custom SKU, CSE can boot from either RO(BP1) or RW(BP2). The CSE Firmware Custom SKU layout appears as below: ------------- -------------------- --------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA | ------------- -------------------- --------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either RO(BP1) or RW(BP2)). GET_BOOT_PARTITION_INFO - Provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets CSE's next boot partition to boot from. With the HECI API, firmware can notify CSE to boot from RO(BP1) or RW(BP2) on next boot. As system having CSE Firmware Custom SKU, boots from RO(BP1) after G3, so coreboot sets CSE to boot from RW(BP2) in normal mode and further, coreboot ensure CSE to boot from whichever is selected boot partition if system is in recovery mode. BUG=b:145809764 TEST=Verified on hatch Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/35402 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/cse/Kconfig | 7 + src/soc/intel/common/block/cse/Makefile.inc | 1 + src/soc/intel/common/block/cse/custom_bp.c | 329 ++++++++++++++++++ .../common/block/include/intelblocks/cse.h | 14 + 4 files changed, 351 insertions(+) create mode 100644 src/soc/intel/common/block/cse/custom_bp.c diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 15de0b0536..e566dddcce 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -12,3 +12,10 @@ config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM help Use this config to include common CSE block to make HECI function disable in SMM mode + +config SOC_INTEL_CSE_CUSTOM_SKU + bool + default n + depends on CHROMEOS + help + Enables CSE Custom SKU diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 90f76d59b0..418b7a2efa 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +ramstage-$(CONFIG_SOC_INTEL_CSE_CUSTOM_SKU) += custom_bp.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c diff --git a/src/soc/intel/common/block/cse/custom_bp.c b/src/soc/intel/common/block/cse/custom_bp.c new file mode 100644 index 0000000000..653684a7bd --- /dev/null +++ b/src/soc/intel/common/block/cse/custom_bp.c @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +#include +#include +#include +#include +#include +#include + +/* Converts bp index to boot partition string */ +#define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") + +/* + * CSE Firmware supports 3 boot partitions. For CSE Custom SKU, only 2 boot partitions are + * used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT. + * CSE Custom SKU Image Layout: + * ------------- ------------------- --------------------- + * |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA | + * ------------- ------------------- --------------------- + */ +#define CSE_MAX_BOOT_PARTITIONS 3 + +/* CSE Custom SKU's valid bootable partition identifiers */ +enum boot_partition_id { + /* RO(BP1) contains recovery/minimal boot FW */ + RO = 0, + + /* RW(BP2) contains fully functional CSE Firmware */ + RW = 1 +}; + +/* + * Boot partition status. + * The status is returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd. + */ +enum bp_status { + /* This value is returned when a partition has no errors */ + BP_STATUS_SUCCESS = 0, + + /* + * This value is returned when a partition should be present based on layout, but it is + * not valid. + */ + BP_STATUS_GENERAL_FAILURE = 1, + + /* This value is returned when a partition is not present per initial image layout */ + BP_STATUS_PARTITION_NOT_PRESENT = 2, + +}; + +/* + * Boot Partition Info Flags + * The flags are returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd. + */ +enum bp_info_flags { + + /* Redundancy Enabled: It indicates CSE supports RO(BP1) and RW(BP2) regions */ + BP_INFO_REDUNDANCY_EN = 1 << 0, + + /* It indicates RO(BP1) supports Minimal Recovery Mode */ + BP_INFO_MIN_RECOV_MODE_EN = 1 << 1, + + /* + * Read-only Config Enabled: It indicates HW protection to CSE RO region is enabled. + * The option is relevant only if the BP_INFO_MIN_RECOV_MODE_EN flag is enabled. + */ + BP_INFO_READ_ONLY_CFG = 1 << 2, +}; + +/* Boot Partition FW Version */ +struct fw_version { + uint16_t major; + uint16_t minor; + uint16_t hotfix; + uint16_t build; +} __packed; + +/* CSE boot partition entry info */ +struct cse_bp_entry { + /* Boot partition version */ + struct fw_version fw_ver; + + /* Boot partition status */ + uint32_t status; + + /* Starting offset of the partition within CSE region */ + uint32_t start_offset; + + /* Ending offset of the partition within CSE region */ + uint32_t end_offset; + uint8_t reserved[12]; +} __packed; + +/* CSE boot partition info */ +struct cse_bp_info { + /* Number of boot partitions */ + uint8_t total_number_of_bp; + + /* Current boot partition */ + uint8_t current_bp; + + /* Next boot partition */ + uint8_t next_bp; + + /* Boot Partition Info Flags */ + uint8_t flags; + + /* Boot Partition Entry Info */ + struct cse_bp_entry bp_entries[CSE_MAX_BOOT_PARTITIONS]; +} __packed; + +struct get_bp_info_rsp { + struct mkhi_hdr hdr; + struct cse_bp_info bp_info; +} __packed; + +static uint8_t cse_get_current_bp(const struct cse_bp_info *cse_bp_info) +{ + return cse_bp_info->current_bp; +} + +static const struct cse_bp_entry *cse_get_bp_entry(enum boot_partition_id bp, + const struct cse_bp_info *cse_bp_info) +{ + return &cse_bp_info->bp_entries[bp]; +} + +static void cse_print_boot_partition_info(const struct cse_bp_info *cse_bp_info) +{ + const struct cse_bp_entry *cse_bp; + + printk(BIOS_DEBUG, "ME: Number of partitions = %d\n", cse_bp_info->total_number_of_bp); + printk(BIOS_DEBUG, "ME: Current partition = %s\n", GET_BP_STR(cse_bp_info->current_bp)); + printk(BIOS_DEBUG, "ME: Next partition = %s\n", GET_BP_STR(cse_bp_info->next_bp)); + printk(BIOS_DEBUG, "ME: Flags = 0x%x\n", cse_bp_info->flags); + + /* Log version info of RO & RW partitions */ + cse_bp = cse_get_bp_entry(RO, cse_bp_info); + printk(BIOS_DEBUG, "ME: %s version = %d.%d.%d.%d (Status=0x%x, Start=0x%x, End=0x%x)\n", + GET_BP_STR(RO), cse_bp->fw_ver.major, cse_bp->fw_ver.minor, + cse_bp->fw_ver.hotfix, cse_bp->fw_ver.build, + cse_bp->status, cse_bp->start_offset, + cse_bp->end_offset); + + cse_bp = cse_get_bp_entry(RW, cse_bp_info); + printk(BIOS_DEBUG, "ME: %s version = %d.%d.%d.%d (Status=0x%x, Start=0x%x, End=0x%x)\n", + GET_BP_STR(RW), cse_bp->fw_ver.major, cse_bp->fw_ver.minor, + cse_bp->fw_ver.hotfix, cse_bp->fw_ver.build, + cse_bp->status, cse_bp->start_offset, + cse_bp->end_offset); +} + +/* + * Checks prerequisites for MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO and + * MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO HECI commands. + * It allows execution of the Boot Partition commands in below scenarios: + * - When CSE boots from RW partition (COM: Normal and CWS: Normal) + * - When CSE boots from RO partition (COM: Soft Temp Disable and CWS: Normal) + * - After HMRFPO_ENABLE command is issued to CSE (COM: SECOVER_MEI_MSG and CWS: Normal) + */ +static bool cse_is_bp_cmd_info_possible(void) +{ + if (cse_is_hfs1_cws_normal()) { + if (cse_is_hfs1_com_normal()) + return true; + if (cse_is_hfs1_com_secover_mei_msg()) + return true; + if (cse_is_hfs1_com_soft_temp_disable()) + return true; + } + return false; +} + +static bool cse_get_bp_info(struct get_bp_info_rsp *bp_info_rsp) +{ + struct get_bp_info_req { + struct mkhi_hdr hdr; + uint8_t reserved[4]; + } __packed; + + struct get_bp_info_req info_req = { + .hdr.group_id = MKHI_GROUP_ID_BUP_COMMON, + .hdr.command = MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO, + .reserved = {0}, + }; + + if (!cse_is_bp_cmd_info_possible()) { + printk(BIOS_ERR, "cse_bp: CSE does not meet prerequisites\n"); + return false; + } + + size_t resp_size = sizeof(struct get_bp_info_rsp); + + if (!heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size)) { + printk(BIOS_ERR, "cse_bp: Could not get partition info\n"); + return false; + } + + if (bp_info_rsp->hdr.result) { + printk(BIOS_ERR, "cse_bp: Get partition info resp failed: %d\n", + bp_info_rsp->hdr.result); + return false; + } + + cse_print_boot_partition_info(&bp_info_rsp->bp_info); + + return true; +} +/* + * It sends HECI command to notify CSE about its next boot partition. When coreboot wants + * CSE to boot from certain partition (BP1 or BP2 ), then this command can be used. + * The CSE's valid bootable partitions are BP1(RO) and BP2(RW). + * This function must be used before EOP. + * Returns false on failure and true on success. + */ +static bool cse_set_next_boot_partition(enum boot_partition_id bp) +{ + struct set_boot_partition_info_req { + struct mkhi_hdr hdr; + uint8_t next_bp; + uint8_t reserved[3]; + } __packed; + + struct set_boot_partition_info_req switch_req = { + .hdr.group_id = MKHI_GROUP_ID_BUP_COMMON, + .hdr.command = MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO, + .next_bp = bp, + .reserved = {0}, + }; + + if (bp != RO && bp != RW) { + printk(BIOS_ERR, "cse_bp: Incorrect partition id(%d) is provided", bp); + return false; + } + + printk(BIOS_INFO, "cse_bp: Set Boot Partition Info Command (%s)\n", GET_BP_STR(bp)); + + if (!cse_is_bp_cmd_info_possible()) { + printk(BIOS_ERR, "cse_bp: CSE does not meet prerequisites\n"); + return false; + } + + struct mkhi_hdr switch_resp; + size_t sw_resp_sz = sizeof(struct mkhi_hdr); + + if (!heci_send_receive(&switch_req, sizeof(switch_req), &switch_resp, &sw_resp_sz)) + return false; + + if (switch_resp.result) { + printk(BIOS_ERR, "cse_bp: Set Boot Partition Info Response Failed: %d\n", + switch_resp.result); + return false; + } + + return true; +} + +static bool cse_boot_to_rw(const struct cse_bp_info *cse_bp_info) +{ + if (cse_get_current_bp(cse_bp_info) == RW) + return true; + + if (!cse_set_next_boot_partition(RW)) + return false; + + do_global_reset(); + + die("cse_bp: Failed to reset system\n"); + + /* Control never reaches here */ + return false; +} + +static bool cse_is_rw_status_valid(const struct cse_bp_info *cse_bp_info) +{ + const struct cse_bp_entry *rw_bp; + + /* RW(BP2) alone represents RW partition */ + rw_bp = cse_get_bp_entry(RW, cse_bp_info); + + if (rw_bp->status == BP_STATUS_PARTITION_NOT_PRESENT || + rw_bp->status == BP_STATUS_GENERAL_FAILURE) { + printk(BIOS_ERR, "cse_bp: RW BP (status:%u) is not valid\n", rw_bp->status); + return false; + } + return true; +} + +static bool cse_is_rw_info_valid(struct cse_bp_info *cse_bp_info) +{ + return cse_is_rw_status_valid(cse_bp_info); +} + +void cse_fw_sync(void *unused) +{ + static struct get_bp_info_rsp cse_bp_info; + + if (vboot_recovery_mode_enabled()) { + printk(BIOS_DEBUG, "cse_bp: Skip switching to RW in the recovery path\n"); + return; + } + + /* If CSE SKU type is not Custom, skip enabling CSE Custom SKU */ + if (!cse_is_hfs3_fw_sku_custom()) { + printk(BIOS_ERR, "cse_bp: Not a CSE Custom SKU\n"); + return; + } + + if (!cse_get_bp_info(&cse_bp_info)) { + printk(BIOS_ERR, "cse_bp: Failed to get CSE boot partition info\n"); + goto failed; + } + + + if (!cse_is_rw_info_valid(&cse_bp_info.bp_info)) { + printk(BIOS_ERR, "cse_bp: CSE RW partition is not valid\n"); + goto failed; + } + + if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { + printk(BIOS_ERR, "cse_bp: Failed to switch to RW\n"); + goto failed; + } + return; +failed: + do_global_reset(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index ead5d41e8c..5cad63c47f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -23,6 +23,7 @@ #define MKHI_GROUP_ID_CBM 0x0 #define MKHI_GROUP_ID_HMRFPO 0x5 #define MKHI_GROUP_ID_GEN 0xff +#define MKHI_GROUP_ID_BUP_COMMON 0xf0 /* Global Reset Command ID */ #define MKHI_CBM_GLOBAL_RESET_REQ 0xb @@ -37,6 +38,10 @@ /* Get Firmware Version Command Id */ #define MKHI_GEN_GET_FW_VERSION 0x2 +/* Boot partition info and set boot partition info command ids */ +#define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c +#define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d + /* ME Current Working States */ #define ME_HFS1_CWS_NORMAL 0x5 @@ -219,4 +224,13 @@ bool cse_is_hfs3_fw_sku_custom(void); * Returns 0 on failure and 1 on success. */ uint8_t cse_wait_com_soft_temp_disable(void); + +/* + * The CSE Custom SKU supports notion of RO and RW boot partitions. The function will set + * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to + * boot from RW and triggers recovery mode if CSE fails to jump to RW. + * In software triggered recovery mode, the function allows CSE to boot from whatever is + * currently selected partition. + */ +void cse_fw_sync(void *unused); #endif // SOC_INTEL_COMMON_CSE_H From 066007590f5b904962f9965ace5485ddab7a89c3 Mon Sep 17 00:00:00 2001 From: Patrik Tesarik Date: Wed, 15 Apr 2020 14:11:54 +0200 Subject: [PATCH 1397/1463] mb/up/squared: Fix eMMC speed for UP2 with EDK2 Since commit 402fe20e (mb/up/squared: Add mainboard) the UP2's eMMC maximum host speed was reduced to DDR50, because HS200 showed I/O errors in the host kernel. We found out that with EDK2 master the correct Host Speed could not be set properly during EDK2 platform init. Therefore eMMC would not show up for boot device selection. This commit sets the eMMC MaxHostSpeed to the designed max value of the used eMMC on the UP2 board and furthermore drops the override from the ramstage.c. It's already set in the devicetree.cb. Though CRC errors are still visible in EDK II debug logs, no other negative effects have been observed. Signed-off-by: Patrik Tesarik Change-Id: I8d53204d8a776efd560fbdea918f83e180813179 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40403 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/up/squared/devicetree.cb | 4 ++++ src/mainboard/up/squared/ramstage.c | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index d7281a6cd8..da2ff06f6a 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -16,6 +16,10 @@ chip soc/intel/apollolake register "enable_vtd" = "1" + # Override eMMC MaxHostSpeed + # 0:HS400 (Default) 1:HS200 2:DDR50 + register "emmc_host_max_speed" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index 8295634dcb..a5cc5d465b 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -30,7 +30,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) silconfig->IoApicBdfValid = 0x1; // 0x0 silconfig->IoApicDeviceNumber = 0x1F; // 0xf silconfig->LPSS_S0ixEnable = 0x1; // 0x0 - silconfig->eMMCHostMaxSpeed = 0x2; // 0x0 silconfig->Usb30Mode = 0x1; // 0x0 silconfig->HdAudioDspUaaCompliance = 0x1; // 0x0 silconfig->InitS3Cpu = 0x1; // 0x0 From e01054d86eecfff846764e640eaafe58b5d5fb5d Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Mon, 27 Apr 2020 18:11:51 +0200 Subject: [PATCH 1398/1463] soc/intel/cannonlake: Add DisableHeciRetry to config Add DisableHeciRetry to the chip config and parse it in romstage. Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/soc/intel/cannonlake/chip.h | 1 + src/soc/intel/cannonlake/romstage/fsp_params.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b74291ebb3..d4d76cdb61 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -194,6 +194,7 @@ struct soc_intel_cannonlake_config { /* Heci related */ uint8_t Heci3Enabled; + uint8_t DisableHeciRetry; /* Gfx related */ uint8_t IgdDvmt50PreAlloc; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 010d152c76..7af90a73ed 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -128,6 +128,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) config->sata_port[i].TxGen3DeEmph; } } +#if !CONFIG(SOC_INTEL_COMETLAKE) + if (config->DisableHeciRetry) + tconfig->DisableHeciRetry = config->DisableHeciRetry; +#endif } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) From 13dee2a9113bfbcce9ae8b302a759af062ecf486 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 30 Apr 2020 00:44:04 +0200 Subject: [PATCH 1399/1463] soc/intel/skl: always enable SataPwrOptEnable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default in coreboot and FSP. Even if FSP's default was 1, coreboot would reset it. This can lead to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "unaligned write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable statically. There is no valid reason to disable it, which might break SATA, anyway. Currently, there are no reported issues on CML and CNL, so a change there could not be tested reliably. SKL/KBL was tested successfully without any noticable downsides. Thus, only SKL gets changed for now. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877 Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/devicetree.cb | 1 - .../google/fizz/variants/baseboard/devicetree.cb | 1 - src/mainboard/protectli/vault_kbl/devicetree.cb | 1 - src/soc/intel/skylake/chip.c | 8 +++++++- src/soc/intel/skylake/chip.h | 3 --- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 82bbb1fc74..e453aa432f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -48,7 +48,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "SataPwrOptEnable" = "1" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 5da9997d59..f02accec71 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -72,7 +72,6 @@ chip soc/intel/skylake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" - register "SataPwrOptEnable" = "1" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d53e43eba3..d3e8b2305c 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "SataPwrOptEnable" = "1" register "EnableAzalia" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b731baff8d..b24ec4fdc0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -258,9 +258,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; - params->SataPwrOptEnable = config->SataPwrOptEnable; params->EnableTcoTimer = !config->PmTimerDisabled; + /* + * For unknown reasons FSP skips writing some essential SATA init registers (SIR) when + * SataPwrOptEnable=0. This results in link errors, "unaligned write" errors and others. + * Enabling this option solves these problems. + */ + params->SataPwrOptEnable = 1; + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 387bd6fe3d..d268eebd66 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -567,9 +567,6 @@ struct soc_intel_skylake_config { */ u8 IslVrCmd; - /* Enable/Disable Sata power optimization */ - u8 SataPwrOptEnable; - /* Enable/Disable Sata test mode */ u8 SataTestMode; From 939cabfae43661b75fb109bd8f280aee0a99ec7e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 29 Apr 2020 17:45:57 -0500 Subject: [PATCH 1400/1463] mb/purism/librem_skl: drop SataSpeedLimit restriction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40909 Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../purism/librem_skl/variants/librem13v2/devicetree.cb | 1 - .../purism/librem_skl/variants/librem15v3/devicetree.cb | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 6c55af66cc..b15dc2df2e 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -54,7 +54,6 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f48135297e..d273462c97 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -54,7 +54,6 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" From 5086ccef19a21bb836c6c11bb3f4fb8f993d3bc2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 1 May 2020 12:48:54 -0500 Subject: [PATCH 1401/1463] mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per the schematics, SRCCLKREQ2# is used for the NVMe and should be enabled. Enable CLKREQ for PCIe RP9, and adjust comments to indicate correct value used per schematic. Test: build/boot Librem 15v3 with NVMe drive, verify drive identified properly and no errors in boot log. Signed-off-by: Matt DeVillier Change-Id: I159cb7ce1f5195d95c0229490c3bbde26edbd375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40950 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- .../purism/librem_skl/variants/librem15v3/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index d273462c97..ceeeb431a7 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -167,8 +167,8 @@ chip soc/intel/skylake register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" # Enable CLKREQ# for RP9 - register "PcieRpClkReqSupport[8]" = "0" - # ClkReq for NVMe - Bruteforced (no other value works) + register "PcieRpClkReqSupport[8]" = "1" + # SRCCLKREQ2# for NVMe per schematic register "PcieRpClkReqNumber[8]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port From 0f4977705d64a50cf823a38227b45c7b4d4eb950 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 28 Apr 2020 08:06:34 +0200 Subject: [PATCH 1402/1463] Documentation: Update vboot on lenovo Update the documentation now that CB:32705 is merged. Change-Id: I9845c0750ec4016188478154610400d1b8556793 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/40775 Reviewed-by: Marcello Sylvester Bauer Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/mainboard/lenovo/vboot.md | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/mainboard/lenovo/vboot.md b/Documentation/mainboard/lenovo/vboot.md index 4e1b946d08..3f1536018f 100644 --- a/Documentation/mainboard/lenovo/vboot.md +++ b/Documentation/mainboard/lenovo/vboot.md @@ -18,8 +18,8 @@ By using the [vboot] mechanism you store a copy of coreboot in the `RO` partition that acts as failsafe in case the regular firmware update, that goes to the `A` or `B` partition fails. -**Note:** The `RO` partition isn't write-protected by default. There's a patch -pending on gerrit [CB:32705] that write-protects the `RO` partition. +**Note:** The `RO` partition isn't write-protected by default, therefore you +have to enable the protection in the security Kconfig menu by yourself. On *Lenovo* devices you can enable the *Fn* key as recovery mode switch, by enabling `CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW`. @@ -35,5 +35,4 @@ You can still provide your own FMAP if you need `RO`+`A`+`B` partitions. [vboot] on *Lenovo* devices uses the CMOS to store configuration data, like boot failures and the last successfully booted partition. -[CB:32705]: https://review.coreboot.org/32705 [vboot]: ../../security/vboot/index.md From fcd9f36b6e7ee9172c950d3e0873d5c926b9be13 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 May 2020 20:14:37 +0200 Subject: [PATCH 1403/1463] payloads/external/GRUB2: Makefile: fix check for changed files again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the missing closing brace introduced in CB:40953. Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/41036 Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- payloads/external/GRUB2/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index bb7b5f8457..31b0f53b18 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -18,7 +18,7 @@ checkout: test -d $(project_dir) || git clone $(project_git_repo) $(project_dir) git -C $(project_dir) fetch ifeq ($(shell test -d $(project_dir) && \ - (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain),) + (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)),) git -C $(project_dir) checkout -f $(TAG-y) else echo "WARNING: index/tree not clean, skipping update / force checkout." From 57e37c58639f01b5249628425323f69770606fbf Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 1 May 2020 12:53:31 -0500 Subject: [PATCH 1404/1463] mb/purism/librem_skl: Convert to use override devicetree Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier Change-Id: I3dac62a649e12ea2498d3ecafe03fd0d62af5f2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40911 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/purism/librem_skl/Kconfig | 4 +- .../{variants/librem13v2 => }/devicetree.cb | 13 - .../variants/librem13v2/overridetree.cb | 17 ++ .../variants/librem15v3/devicetree.cb | 243 ------------------ .../variants/librem15v3/overridetree.cb | 27 ++ 5 files changed, 46 insertions(+), 258 deletions(-) rename src/mainboard/purism/librem_skl/{variants/librem13v2 => }/devicetree.cb (90%) create mode 100644 src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb delete mode 100644 src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb create mode 100644 src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ca1582a50c..be4c391e60 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -39,9 +39,9 @@ config MAINBOARD_DIR string default "purism/librem_skl" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAX_CPUS int diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb similarity index 90% rename from src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb rename to src/mainboard/purism/librem_skl/devicetree.cb index b15dc2df2e..854f5db48a 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -167,19 +167,6 @@ chip soc/intel/skylake register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD - - # OC1 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - # PL2 override 25W register "tdp_pl2_override" = "25" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb new file mode 100644 index 0000000000..18ce220753 --- /dev/null +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb @@ -0,0 +1,17 @@ +chip soc/intel/skylake + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD + + # OC1 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + + device domain 0 on end +end diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb deleted file mode 100644 index ceeeb431a7..0000000000 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ /dev/null @@ -1,243 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" - - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - register "eist_enable" = "1" - - # Set the Thermal Control Circuit (TCC) activaction value to 95C - # even though FSP integration guide says to set it to 100C for SKL-U - # (offset at 0), because when the TCC activates at 100C, the CPU - # will have already shut itself down from overheating protection. - register "tcc_offset" = "5" # TCC of 95C - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_C" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Disable DPTF - register "dptf_enable" = "0" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "0" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "0" - register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "0" - - # EC/KBC requires continuous mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | - #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), - .voltage_limit = 1520, - .ac_loadline = 1500, - .dc_loadline = 1430, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - .ac_loadline = 570, - .dc_loadline = 483, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - .ac_loadline = 520, - .dc_loadline = 420, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - .ac_loadline = 520, - .dc_loadline = 420, - }" - - # Enable Root Ports 5 and 9 - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# for RP9 - register "PcieRpClkReqSupport[8]" = "1" - # SRCCLKREQ2# for NVMe per schematic - register "PcieRpClkReqNumber[8]" = "2" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD - - # OC0 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - - # PL2 override 25W - register "tdp_pl2_override" = "25" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 on end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb new file mode 100644 index 0000000000..ab46cd3cd1 --- /dev/null +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb @@ -0,0 +1,27 @@ +chip soc/intel/skylake + + # Enable CLKREQ# for RP9 + register "PcieRpClkReqSupport[8]" = "1" + # SRCCLKREQ2# for NVMe per schematic + register "PcieRpClkReqNumber[8]" = "2" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + + device domain 0 on + device pci 1c.4 on end # PCI Express Port 5 + end +end From 2b2f67fb7e3e6e7dd6360540c16a2cf8e52b7175 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2020 14:47:26 -0500 Subject: [PATCH 1405/1463] mb/purism/librem_skl: rename variant directories MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the same variant dirs are used by multiple versions of the same board, drop the v2/v3 labels. Signed-off-by: Matt DeVillier Change-Id: Id913e31ab52043e49769be9d3ebf6e71ecb0c856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40912 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/purism/librem_skl/Kconfig | 4 ++-- .../variants/{librem13v2 => librem13}/board_info.txt | 0 .../variants/{librem13v2 => librem13}/overridetree.cb | 0 .../variants/{librem15v3 => librem15}/board_info.txt | 0 .../variants/{librem15v3 => librem15}/overridetree.cb | 0 5 files changed, 2 insertions(+), 2 deletions(-) rename src/mainboard/purism/librem_skl/variants/{librem13v2 => librem13}/board_info.txt (100%) rename src/mainboard/purism/librem_skl/variants/{librem13v2 => librem13}/overridetree.cb (100%) rename src/mainboard/purism/librem_skl/variants/{librem15v3 => librem15}/board_info.txt (100%) rename src/mainboard/purism/librem_skl/variants/{librem15v3 => librem15}/overridetree.cb (100%) diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index be4c391e60..08fa4c7d43 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -20,8 +20,8 @@ config IRQ_SLOT_COUNT config VARIANT_DIR string - default "librem13v2" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 - default "librem15v3" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 + default "librem13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 + default "librem15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 config MAINBOARD_FAMILY string diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/board_info.txt b/src/mainboard/purism/librem_skl/variants/librem13/board_info.txt similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem13v2/board_info.txt rename to src/mainboard/purism/librem_skl/variants/librem13/board_info.txt diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb rename to src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt b/src/mainboard/purism/librem_skl/variants/librem15/board_info.txt similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt rename to src/mainboard/purism/librem_skl/variants/librem15/board_info.txt diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb rename to src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb From b651032ea77e7a959b61dd49bbdfcbbdc56c6f71 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2020 14:52:18 -0500 Subject: [PATCH 1406/1463] mb/purism/librem_skl: Clean up Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder Kconfig selects alphabetically, and select the correct SoC for each variant (even though it currently makes no difference). Signed-off-by: Matt DeVillier Change-Id: I46f651a530ef0ed617dd1f3eee077e84279a40f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40913 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/Kconfig | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 08fa4c7d43..11bb08da00 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -1,16 +1,17 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL def_bool n - select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_GMA_HAVE_VBT - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_SKYLAKE - select SPD_READ_BY_WORD select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 + select SOC_INTEL_SKYLAKE if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP if BOARD_PURISM_BASEBOARD_LIBREM_SKL From df134c187370e15d1cdf964be8bf124b9449293c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 29 Apr 2020 17:33:36 -0500 Subject: [PATCH 1407/1463] mb/purism/librem_skl: disable serial console output MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Librem SKL/KBL boards do not have an exposed serial port interface. Set board Kconfig so that a default built image with Tianocore payload is bootable and doesn't hang due to trying to send data over a non-existant serial port. Test: build/boot librem 13v4 with board defaults + Tianocore Signed-off-by: Matt DeVillier Change-Id: I4c3f8a3c1726f804957b06b437b399291854a3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40873 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel --- src/mainboard/purism/librem_skl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 11bb08da00..7a73823f15 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -3,10 +3,10 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM + select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_KABYLAKE if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 select SOC_INTEL_SKYLAKE if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 From 4eadcb053795514ad6fdd61b0b9a95729dee8bd0 Mon Sep 17 00:00:00 2001 From: Dossym Nurmukhanov Date: Mon, 4 May 2020 12:45:06 -0700 Subject: [PATCH 1408/1463] libpayload/drivers/usb/xhci: Allow xHCI v1.2 in libpayload The latest Intel FSP advertises xHCI v1.2 chipset support, so update libpayload to include that version. No critical changes were identified in review of the xHCI v1.2 spec, and booting from USB works with the included change as expected. BUG=b:155315876 TEST=booting from multiple USB sticks/hubs with the latest Intel FSP that advertises xHCI v1.2 Change-Id: I236fed9beef86ff5e1bf7962d882fdae5817a1ff Signed-off-by: Dossym Nurmukhanov Reviewed-on: https://review.coreboot.org/c/coreboot/+/41039 Reviewed-by: Wonkyu Kim Reviewed-by: Julius Werner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/usb/xhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 08a81ef5d5..53dd782c84 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -198,7 +198,7 @@ xhci_init (unsigned long physical_bar) xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n", CAP_GET(CAPVER_HI, xhci->capreg), CAP_GET(CAPVER_LO, xhci->capreg)); if ((CAP_GET(CAPVER, xhci->capreg) < 0x96) || - (CAP_GET(CAPVER, xhci->capreg) > 0x110)) { + (CAP_GET(CAPVER, xhci->capreg) > 0x120)) { xhci_debug("Unsupported xHCI version\n"); goto _free_xhci; } From e7a083ec3dc0d7696cf6a0eda03dac67d6936834 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 29 Apr 2020 19:25:07 -0700 Subject: [PATCH 1409/1463] vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163 Update FSP headers for Tiger Lake platform generated based FSP version 3163. Which includes below additional UPDs: FSPM: -BootFrequency -SerialIoUartDebugMode FSPS: -PcieRpPmSci -PchPmWoWlanEnable -PchPmWoWlanDeepSxEnable -PchPmLanWakeFromDeepSx BUG=b:155315876 BRANCH=none TEST=build and boot ripto/volteer Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik Change-Id: Ida87ac7dd7f5fd7ee0459ae1037a8df816976083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40898 Reviewed-by: Wonkyu Kim Reviewed-by: Dossym Nurmukhanov Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 32 ++++++-- .../intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 79 +++++++++++++------ 2 files changed, 82 insertions(+), 29 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index cc44a2a96f..aa59bbf11d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -219,7 +219,7 @@ typedef struct { UINT8 Reserved1[7]; /** Offset 0x0130 - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + DEPRECATED 0 : Disable, 0x400000 : Enable **/ UINT32 IedSize; @@ -604,9 +604,16 @@ typedef struct { **/ UINT8 CpuRatio; -/** Offset 0x0326 - Reserved +/** Offset 0x0326 - Boot frequency + Sets the boot frequency starting from reset vector.- 0: Maximum battery performance. + 1: Maximum non-turbo performance. 2: Turbo performance + 0:0, 1:1, 2:2 **/ - UINT8 Reserved19[2]; + UINT8 BootFrequency; + +/** Offset 0x0327 - Reserved +**/ + UINT8 Reserved19; /** Offset 0x0328 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- @@ -921,7 +928,18 @@ typedef struct { /** Offset 0x0775 - Reserved **/ - UINT8 Reserved40[315]; + UINT8 Reserved40[297]; + +/** Offset 0x089E - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x089F - Reserved +**/ + UINT8 Reserved41[121]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -940,11 +958,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x08B0 +/** Offset 0x0918 **/ - UINT8 UnusedUpdSpace22[6]; + UINT8 UnusedUpdSpace24[6]; -/** Offset 0x08B6 +/** Offset 0x091E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 9b8db02fe0..6b1217e63a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -394,7 +394,7 @@ typedef struct { /** Offset 0x03FE - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable + DEPRECATED 0: disable, 1: enable $EN_DIS **/ UINT8 Heci3Enabled; @@ -412,7 +412,8 @@ typedef struct { UINT8 CdClock; /** Offset 0x048D - Enable/Disable PeiGraphicsPeimInit - Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; @@ -494,7 +495,9 @@ typedef struct { UINT8 Reserved22[10]; /** Offset 0x05B4 - CpuMpPpi - Pointer for CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; @@ -565,7 +568,16 @@ typedef struct { /** Offset 0x0622 - Reserved **/ - UINT8 Reserved28[72]; + UINT8 Reserved28[24]; + +/** Offset 0x063A - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[24]; + +/** Offset 0x0652 - Reserved +**/ + UINT8 Reserved29[24]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -579,7 +591,7 @@ typedef struct { /** Offset 0x069A - Reserved **/ - UINT8 Reserved29[168]; + UINT8 Reserved30[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. @@ -594,7 +606,7 @@ typedef struct { /** Offset 0x075B - Reserved **/ - UINT8 Reserved30[5]; + UINT8 Reserved31[5]; /** Offset 0x0760 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -604,7 +616,7 @@ typedef struct { /** Offset 0x0761 - Reserved **/ - UINT8 Reserved31[79]; + UINT8 Reserved32[79]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -625,7 +637,30 @@ typedef struct { /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved32[98]; + UINT8 Reserved33[79]; + +/** Offset 0x0847 - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x0848 - PCH Pm WoW lan DeepSx Enable + Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the + PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanDeepSxEnable; + +/** Offset 0x0849 - PCH Pm Lan Wake From DeepSx + Determine if enable LAN to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmLanWakeFromDeepSx; + +/** Offset 0x084A - Reserved +**/ + UINT8 Reserved34[16]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -635,7 +670,7 @@ typedef struct { /** Offset 0x085B - Reserved **/ - UINT8 Reserved33[50]; + UINT8 Reserved35[50]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -644,7 +679,7 @@ typedef struct { /** Offset 0x0895 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved36; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -653,7 +688,7 @@ typedef struct { /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved35[72]; + UINT8 Reserved37[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -667,7 +702,7 @@ typedef struct { /** Offset 0x0908 - Reserved **/ - UINT8 Reserved36[16]; + UINT8 Reserved38[16]; /** Offset 0x0918 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time @@ -687,7 +722,7 @@ typedef struct { /** Offset 0x091A - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved39[3]; /** Offset 0x091D - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. @@ -698,7 +733,7 @@ typedef struct { /** Offset 0x091E - Reserved **/ - UINT8 Reserved38[434]; + UINT8 Reserved40[434]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -706,7 +741,7 @@ typedef struct { /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved39[101]; + UINT8 Reserved41[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -724,7 +759,7 @@ typedef struct { /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved40[260]; + UINT8 Reserved42[260]; /** Offset 0x0C3E - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. @@ -746,7 +781,7 @@ typedef struct { /** Offset 0x0C41 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved43; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -760,7 +795,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved42[269]; + UINT8 Reserved44[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -768,7 +803,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved43[176]; + UINT8 Reserved45[224]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -783,11 +818,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0E60 +/** Offset 0x0E90 **/ - UINT8 UnusedUpdSpace34[6]; + UINT8 UnusedUpdSpace36[6]; -/** Offset 0x0E66 +/** Offset 0x0E96 **/ UINT16 UpdTerminator; } FSPS_UPD; From 6ad8352a3de78e2f6869cc7fbc4274057fcffd4a Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 29 Apr 2020 19:49:25 -0700 Subject: [PATCH 1410/1463] src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M Due to refactoring of Serial IO code in FSP v3163 onwards we need to set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart initialization is skipped in FSP. This makes sure that SerialIo initialization in coreboot is not changed by FSP. BUG=b:155315876 BRANCH=none TEST=build and boot tglrvp/ripto/volteer and check UART debug logs Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899 Reviewed-by: Dossym Nurmukhanov Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 022cd830c9..e4f6e824c1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -82,6 +82,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, } m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); From 65cc80f740a736d3b947268c157d3331a7cec922 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 24 Apr 2020 17:42:49 -0700 Subject: [PATCH 1411/1463] soc/intel/tigerlake: Update interrupt setting Update interrupt setting based on latest FSP(3163.01) Reference: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/ ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/ PeiItssPolicyLibVer2.c BUG=b:155315876 BRANCH=none TEST=Build with new FSP(3163.01) and boot OS and login OS console in ripto/volteer. Without this change, we can't login due to mismatch interrupt setting between asl and fsp setting. Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Wonkyu Kim Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872 Reviewed-by: Dossym Nurmukhanov Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi/pci_irqs.asl | 4 ++-- src/soc/intel/tigerlake/include/soc/irq.h | 15 ++++++++------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1f48..116b9a3fd0 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -19,6 +19,7 @@ Name (PICP, Package () { /* D31:HDA, SMBUS, TraceHUB */ Package(){0x001FFFFF, 3, 0, HDA_IRQ }, Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, + Package(){0x001FFFFF, 6, 0, GBE_IRQ }, Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, /* D30: UART0, UART1, SPI0, SPI1 */ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, @@ -64,8 +65,7 @@ Name (PICP, Package () { /* D18: ISH, SPI2 */ Package(){0x0012FFFF, 0, 0, ISH_IRQ }, Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, + /* D16: TCH0, TCH1 */ Package(){0x0010FFFF, 6, 0, THC0_IRQ }, Package(){0x0010FFFF, 7, 0, THC1_IRQ }, /* D13: xHCI, xDCI */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b4f4..8763abb903 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -11,20 +11,21 @@ #define PCH_IRQ11 11 #define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C1_IRQ 40 #define LPSS_I2C2_IRQ 29 #define LPSS_I2C3_IRQ 30 #define LPSS_I2C4_IRQ 31 #define LPSS_I2C5_IRQ 32 #define LPSS_SPI0_IRQ 36 #define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 18 -#define LPSS_SPI3_IRQ 23 -#define LPSS_UART0_IRQ 34 -#define LPSS_UART1_IRQ 35 +#define LPSS_SPI2_IRQ 34 +#define LPSS_SPI3_IRQ 43 +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 #define LPSS_UART2_IRQ 33 #define HDA_IRQ 16 +#define GBE_IRQ 16 #define SMBUS_IRQ 16 #define TRACEHUB_IRQ 16 @@ -49,8 +50,8 @@ #define CNVI_BT_IRQ 18 -#define THC0_IRQ 16 -#define THC1_IRQ 17 +#define THC0_IRQ 23 +#define THC1_IRQ 22 #define ISH_IRQ 16 From 314c716aff9895221f1f5b8bef4d3889a7749c0a Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 1 May 2020 14:04:08 -0600 Subject: [PATCH 1412/1463] soc/amd/common/block/lpc: Add lpc_disable_spi_rom_sharing If a Picasso platform wants to use GPIO 67 it must disable ROM sharing. Otherwise ROM access is incredibly slow. BUG=b:153502861 TEST=Build trembyle Signed-off-by: Raul E Rangel Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/soc/amd/common/block/include/amdblocks/lpc.h | 3 +++ src/soc/amd/common/block/lpc/Kconfig | 6 ++++++ src/soc/amd/common/block/lpc/lpc_util.c | 14 ++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index dc33073d3e..1d74823542 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -10,6 +10,8 @@ /* PCI registers for D14F3 */ #define LPC_PCI_CONTROL 0x40 #define LEGACY_DMA_EN BIT(2) +#define VW_ROM_SHARING_EN BIT(3) +#define EXT_ROM_SHARING_EN BIT(4) #define LPC_IO_PORT_DECODE_ENABLE 0x44 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) @@ -148,6 +150,7 @@ void lpc_tpm_decode(void); void lpc_tpm_decode_spi(void); void lpc_enable_rom(void); void lpc_enable_spi_prefetch(void); +void lpc_disable_spi_rom_sharing(void); /** * @brief Find the size of a particular wide IO diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index b0d59a55f4..3cfbfe5dcd 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -3,3 +3,9 @@ config SOC_AMD_COMMON_BLOCK_LPC default n help Select this option to use the traditional LPC-ISA bridge at D14F3. + +config PROVIDES_ROM_SHARING + bool + default n + help + Select this option if the LPC bridge supports ROM sharing. diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 571c6fe8ed..45b252f99b 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include #include #include @@ -300,6 +301,19 @@ void lpc_enable_spi_prefetch(void) pci_write_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); } +void lpc_disable_spi_rom_sharing(void) +{ + u8 byte; + + if (!CONFIG(PROVIDES_ROM_SHARING)) + dead_code(); + + byte = pci_read_config8(_LPCB_DEV, LPC_PCI_CONTROL); + byte &= ~VW_ROM_SHARING_EN; + byte &= ~EXT_ROM_SHARING_EN; + pci_write_config8(_LPCB_DEV, LPC_PCI_CONTROL, byte); +} + uintptr_t lpc_get_spibase(void) { u32 base; From 1d0b99ba1df910677b3ac238a16b88bcec2d49f8 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Sat, 11 Apr 2020 11:58:57 -0600 Subject: [PATCH 1413/1463] soc/amd/picasso: add Kconfig option to disable rom sharing Add a knob for mainboards to request disablement of the SPI flash ROM sharing in the chipset. The chipset allows the board to share the SPI flash bus and needs a pin to perform the request. If the board design does not employ SPI flash ROM sharing then it's imperative to ensure this option is selected, especially if the pin is being utilized by something else in the board design. BUG=b:153502861 Change-Id: I60ba852070dd218c4ac071b6c1cfcde2df8e5dce Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146445 Reviewed-by: Furquan Shaikh Commit-Queue: Aaron Durbin Tested-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/40869 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/Kconfig | 9 +++++++++ src/soc/amd/picasso/southbridge.c | 3 +++ 2 files changed, 12 insertions(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3d699667fe..a42629bdff 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -216,6 +217,14 @@ config PICASSO_LPC_IOMUX Picasso's LPC bus signals are MUXed with some of the EMMC signals. Select this option if LPC signals are required. +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0d54294543..d742038183 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -360,6 +360,9 @@ void fch_early_init(void) { sb_print_pmxc0_status(); i2c_soc_early_init(); + + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) + lpc_disable_spi_rom_sharing(); } void sb_enable(struct device *dev) From 07171b480cfdfdc0e14060ff93bf94a74161b0e6 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 7 Feb 2020 14:09:15 -0800 Subject: [PATCH 1414/1463] soc/intel/tigerlake: Add PMC mux control PMC supports messages that can be used for configuring the USB Type-C Multiplexer/Demultiplexer. BUG=b:151646486 TEST=Booted to kernel on volteer board and verified PMC and Mux agent devices identification. Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/38777 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/acpi/pmc.asl | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl index 2f7fa46d73..8e4e306651 100644 --- a/src/soc/intel/tigerlake/acpi/pmc.asl +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -14,7 +14,14 @@ Scope (\_SB.PCI0) { * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. */ Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE) }) + + /* The OS mux driver will be bound to this device node. */ + Device (MUX) + { + Name (_HID, "INTC105C") + Name (_DDN, "Intel(R) Tiger Lake North Mux-Agent") + } } } From 296ce46bcc84a6c10716bb807f317ca9f451ed39 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 2 May 2020 19:19:04 -0400 Subject: [PATCH 1415/1463] superio/fintek/f81216h: Drop support No mainboards use this anymore. Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/40967 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/superio/fintek/f81216h/Kconfig | 6 -- src/superio/fintek/f81216h/Makefile.inc | 6 -- src/superio/fintek/f81216h/chip.h | 23 ------ src/superio/fintek/f81216h/early_serial.c | 52 ------------ src/superio/fintek/f81216h/f81216h.h | 31 ------- src/superio/fintek/f81216h/superio.c | 98 ----------------------- 6 files changed, 216 deletions(-) delete mode 100644 src/superio/fintek/f81216h/Kconfig delete mode 100644 src/superio/fintek/f81216h/Makefile.inc delete mode 100644 src/superio/fintek/f81216h/chip.h delete mode 100644 src/superio/fintek/f81216h/early_serial.c delete mode 100644 src/superio/fintek/f81216h/f81216h.h delete mode 100644 src/superio/fintek/f81216h/superio.c diff --git a/src/superio/fintek/f81216h/Kconfig b/src/superio/fintek/f81216h/Kconfig deleted file mode 100644 index 17da818414..0000000000 --- a/src/superio/fintek/f81216h/Kconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# This file is part of the coreboot project. - -config SUPERIO_FINTEK_F81216H - bool -# N.B. 'special romstage' diff --git a/src/superio/fintek/f81216h/Makefile.inc b/src/superio/fintek/f81216h/Makefile.inc deleted file mode 100644 index 6dd48a1198..0000000000 --- a/src/superio/fintek/f81216h/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This file is part of the coreboot project. - -bootblock-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c -romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c -ramstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += superio.c diff --git a/src/superio/fintek/f81216h/chip.h b/src/superio/fintek/f81216h/chip.h deleted file mode 100644 index f5f7575f43..0000000000 --- a/src/superio/fintek/f81216h/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* This file is part of the coreboot project. */ - -#ifndef SUPERIO_FINTEK_F81216H_CHIP_H -#define SUPERIO_FINTEK_F81216H_CHIP_H - -#include - -/* Member variables are defined in devicetree.cb. */ -struct superio_fintek_f81216h_config { - /** - * KEY1 KEY0 Enter key - * 0 0 0x77 (default) - * 0 1 0xA0 - * 1 0 0x87 - * 1 1 0x67 - * - * See page 17 of data sheet. - */ - uint8_t conf_key_mode; -}; - -#endif /* SUPERIO_FINTEK_F81216H_CHIP_H */ diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c deleted file mode 100644 index d2fa0fe9ec..0000000000 --- a/src/superio/fintek/f81216h/early_serial.c +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* This file is part of the coreboot project. */ - -#include -#include -#include -#include -#include "f81216h.h" - -#define FINTEK_EXIT_KEY 0xAA - -static void pnp_enter_conf_state(pnp_devfn_t dev, u8 f81216h_entry_key) -{ - u16 port = dev >> 8; - outb(f81216h_entry_key, port); - outb(f81216h_entry_key, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(FINTEK_EXIT_KEY, port); -} - -/* Bring up early serial debugging output before the RAM is initialized. */ -void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, mode_key k) -{ - u8 key; - switch (k) { - case MODE_6767: - key = 0x67; - break; - case MODE_7777: - key = 0x77; - break; - case MODE_8787: - key = 0x87; - break; - case MODE_A0A0: - key = 0xA0; - break; - default: - key = 0x77; /* try the hw default */ - break; - } - pnp_enter_conf_state(dev, key); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h deleted file mode 100644 index 0c8463e55b..0000000000 --- a/src/superio/fintek/f81216h/f81216h.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* This file is part of the coreboot project. */ - -#ifndef SUPERIO_FINTEK_F81216H_H -#define SUPERIO_FINTEK_F81216H_H - -#include - -/* Logical Device Numbers (LDN). */ -#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */ -#define F81216H_SP2 0x01 /* UART2 */ -#define F81216H_SP3 0x02 /* UART3 */ -#define F81216H_SP4 0x03 /* UART4 */ -#define F81216H_WDT 0x08 /* WDT */ - -/** - * The PNP config entry key is parameterised - * by two bits on this Super I/O with 0x77 as - * the default key. - * See page 17 of data sheet for details. - */ -typedef enum { - MODE_6767 = 0x67, - MODE_7777 = 0x77, - MODE_8787 = 0x87, - MODE_A0A0 = 0xA0, -} mode_key; - -void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, mode_key k); - -#endif /* SUPERIO_FINTEK_F81216H_H */ diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c deleted file mode 100644 index 52eedd6fc8..0000000000 --- a/src/superio/fintek/f81216h/superio.c +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* This file is part of the coreboot project. */ - -#include -#include -#include -#include -#include - -#include "chip.h" -#include "f81216h.h" - - -static void pnp_enter_ext_func_mode(struct device *dev) -{ - const struct superio_fintek_f81216h_config *conf = dev->chip_info; - - u8 key; - - /** - * KEY1 KEY0 Enter key - * 0 0 0x77 (default) - * 0 1 0xA0 - * 1 0 0x87 - * 1 1 0x67 - * - * See page 17 of data sheet. - */ - switch (conf->conf_key_mode) { - case MODE_6767: - case MODE_7777: - case MODE_8787: - case MODE_A0A0: - key = conf->conf_key_mode; - break; - default: - printk(BIOS_WARNING, "Warning: Undefined F81216 unlock key assignment!\n"); - printk(BIOS_WARNING, "Setting conf_key_mode to default\n"); - key = MODE_7777; /* try the hw default */ - break; - } - - outb(key, dev->path.pnp.port); - outb(key, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - outb(0xaa, dev->path.pnp.port); -} - -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - - -static void f81216h_init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case F81216H_SP1: - case F81216H_SP2: - case F81216H_SP3: - case F81216H_SP4: - case F81216H_WDT: - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f81216h_init, - .ops_pnp_mode = &pnp_conf_mode_ops, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, F81216H_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F81216H_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F81216H_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F81216H_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F81216H_WDT, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_fintek_f81216h_ops = { - CHIP_NAME("Fintek F81216H/D/DG/F/FG Super I/O") - .enable_dev = enable_dev -}; From a4412d68d50f27fea65ef4c83e43ab89aa27bf95 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 4 May 2020 17:08:03 +0530 Subject: [PATCH 1416/1463] soc/intel/jasperlake: Allow SD card power enable polarity configuration SdCardPowerEnableActiveHigh is a UPD which controls polarity of SD card power enable pin. Setting it 1 will set polarity of this pin as Active high. This patch will allow to control it from devicetree so that it can be set as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD value from FSP log Signed-off-by: Ronak Kanabar Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41027 Reviewed-by: Aamir Bohra Reviewed-by: Karthik Ramasubramanian Reviewed-by: V Sowmya Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/fsp_params.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index f525fd8af1..28dccabb10 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -136,10 +136,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); - if (!dev) + if (!dev) { params->ScsSdCardEnabled = 0; - else + } else { params->ScsSdCardEnabled = dev->enabled; + params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; + } params->Device4Enable = config->Device4Enable; From d4ad3f537f2fc478d5904c34d1f06234c30de1c9 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 4 May 2020 17:28:39 +0530 Subject: [PATCH 1417/1463] soc/intel/jasperlake: Correct the EMMC PCR Port ID Updating EMMC PCR PID from 0x52 to 0x51 for Jasperlake BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP from emmc Signed-off-by: Ronak Kanabar Change-Id: I17d4e7b7e0fe5e0b18867b6481b5bc9227ae19e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41028 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: V Sowmya Reviewed-by: Aamir Bohra Reviewed-by: Maulik V Vaghela --- src/soc/intel/jasperlake/include/soc/pcr_ids.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h index 411a141ebf..a423134de5 100644 --- a/src/soc/intel/jasperlake/include/soc/pcr_ids.h +++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h @@ -4,9 +4,9 @@ #ifndef SOC_JASPERLAKE_PCR_H #define SOC_JASPERLAKE_PCR_H /* - * Port ids + * Port IDs */ -#define PID_EMMC 0x52 +#define PID_EMMC 0x51 #define PID_SDX 0x53 #define PID_GPIOCOM0 0x6e From 733ef79424f0260aeaf949386db11121f18d92fb Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Tue, 21 Apr 2020 20:21:34 +0530 Subject: [PATCH 1418/1463] mb/intel/jasperlake_rvp: Configure IP specific GPIOs This patch configures all IP related GPIOs as per mainboard schematics. Till now, we were relying on FSP to do IP specific GPIO programming but now we'll program all GPIOs from mainboard. This will remove ambiguity of GPIO programming done by FSP and coreboot will do full GPIO programming Programming GPIOs of following IPs - I2C - Emmc - Display - CPU specific gpio (SLP lines) - Cnvi - SD BUG=None BRANCH=None TEST=compile coreboot and checked that all IP functionality working. Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Reviewed-by: Ronak Kanabar --- .../jasperlake_rvp/variants/jslrvp/gpio.c | 192 ++++++++++++++++-- 1 file changed, 173 insertions(+), 19 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 9b86839119..39c14704af 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -7,18 +7,35 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill other gpio configuration */ /* WWAN_WAKE_N */ PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT), + /* DDI1_HPD */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* DDI0_HPD */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* M.2_WWAN_DISABLE_N */ PAD_CFG_GPO(GPP_A19, 1, PLTRST), + /* PMC_CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* PMC_CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* PMC_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* PMC_PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST), - /* GSPI1_CS# */ + /* GSPI1_CS0_N */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* GSPI1_CLK */ @@ -30,7 +47,7 @@ static const struct pad_config gpio_table[] = { /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), - /*PCH_INT_ODL*/ + /* DDI2_HPD */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* WWAN_PERST_N */ @@ -39,7 +56,7 @@ static const struct pad_config gpio_table[] = { /* M2_WWAN_SSD_SKT2_CFG2 */ PAD_CFG_GPI(GPP_C3, NONE, PLTRST), - /*SLP_LAN_N*/ + /* SLP_LAN_N */ PAD_CFG_GPO(GPP_C7, 0, PLTRST), /* I2C0_SDA */ @@ -54,31 +71,145 @@ static const struct pad_config gpio_table[] = { /* BT_RF_KILL_N */ PAD_CFG_GPO(GPP_D1, 1, PLTRST), - /*LAN_RST_N*/ + /* LAN_RST_N */ PAD_CFG_GPO(GPP_D6, 1, PLTRST), - /* I2S_MCLK */ + /* AVS_I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* WWAN_FCP_OFF_N */ PAD_CFG_GPO(GPP_E3, 1, PLTRST), - /*FPS_INT*/ + /* DDI0_DDC_SCL */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* DDI0_DDC_SDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + + /* DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), + + /* DDI2_DDC_SCL */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + + /* DDI2_DDC_SDA */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + + /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + + /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + + /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* CNV_RF_RESET_B */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* EMMC_CMD */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + + /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + + /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + + /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + + /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + + /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + + /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + + /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + + /* EMMC_RCLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + + /* EMMC_CLK */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + + /* EMMC_RESET_N */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + + /* SD_SDIO_CMD */ + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + + /* SD_SDIO_D0 */ + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + + /* SD_SDIO_D1 */ + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + + /* SD_SDIO_D2 */ + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + + /* SD_SDIO_D3 */ + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + + /* SD_SDIO_CD_N */ + PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), + + /* SD_SDIO_CLK */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + + /* SD_SDIO_WP */ + PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), + + /* FPS_INT */ PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT), + /* SD_SDIO_PWR_EN_N */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), + + /* MODEM_CLKREQ0 */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* WWAN EN GPIO */ PAD_CFG_GPO(GPP_H7, 1, PLTRST), + /* CPU_C10_GATE_N */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* M.2_BT_I2S2_SCLK */ PAD_CFG_GPI(GPP_H11, NONE, PLTRST), - /*PCH_INT_ODL*/ + /* CNV_RF_RESET_N */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2), + + /* PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT), /* M.2_BT_I2S2_RXD */ PAD_CFG_GPI(GPP_H14, NONE, PLTRST), - /* I2S1_SCLK */ + /* AVS_I2S1_SCLK */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* Audio Jack Detection */ @@ -87,26 +218,26 @@ static const struct pad_config gpio_table[] = { /* M2_CNVI_EN_N */ PAD_CFG_GPO(GPP_H19, 0, PLTRST), - /* I2S0_SCLK */ + /* AVS_I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* I2S0_SFRM */ + /* AVS_I2S0_SFRM */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* I2S0_TXD */ + /* AVS_I2S0_TXD */ PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), - /* I2S0_RXD */ + /* AVS_I2S0_RXD */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* I2S1_RXD */ + /* AVS_I2S1_RXD */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* I2S1_SFRM */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* AVS_I2S1_SFRM */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), - /* I2S1_TXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + /* AVS_I2S1_TXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), /* WWAN RST_N */ PAD_CFG_GPO(GPP_S0, 1, DEEP), @@ -123,6 +254,29 @@ static const struct pad_config gpio_table[] = { /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2), + /* PMC_BATLOW_N */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + + /* PMC_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + + /* LAN_WAKE_N */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* PMC_PWR_BTN_N */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + + /* PMC_SLP_S3_N */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + + /* PMC_SLP_S4_N */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + + /* PMC_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + + /* virtual GPIO for SD card detect */ + PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP), }; /* Early pad configuration in bootblock */ @@ -140,7 +294,7 @@ static const struct pad_config early_gpio_table[] = { /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), - /*PCH_INT_ODL*/ + /* PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT), }; From d9b2f7971a2a7ae7c43f778ceaf3d385154bd22f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 28 Apr 2020 16:28:03 +0200 Subject: [PATCH 1419/1463] sconfig: Allow `register` entries below devices, too Every device belongs to a chip. And we already keep that relation by inheriting the `.chip_info` pointer if downstream devices don't have another chip specified. So we can also allow to specify `register` settings at the device level. Change-Id: I44e6b95d0cd708fef69b152ebc46b869b2bb9205 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40803 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- util/sconfig/sconfig.tab.c_shipped | 626 ++++++++++++++++------------- util/sconfig/sconfig.tab.h_shipped | 17 +- util/sconfig/sconfig.y | 2 +- 3 files changed, 357 insertions(+), 288 deletions(-) diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index f4335c79ad..1831e91147 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,8 +1,9 @@ -/* A Bison parser, made by GNU Bison 3.0.4. */ +/* A Bison parser, made by GNU Bison 3.5.4. */ /* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2020 Free Software Foundation, + Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -40,11 +41,14 @@ define necessary library symbols; they are noted "INFRINGES ON USER NAME SPACE" below. */ +/* Undocumented macros, especially those whose name start with YY_, + are private implementation details. Do not rely on them. */ + /* Identify Bison output. */ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.0.4" +#define YYBISON_VERSION "3.5.4" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -61,8 +65,7 @@ -/* Copy the first part of user declarations. */ - +/* First part of user prologue. */ /* * sconfig, coreboot device tree compiler @@ -90,12 +93,24 @@ static struct chip_instance *cur_chip_instance; - -# ifndef YY_NULLPTR -# if defined __cplusplus && 201103L <= __cplusplus -# define YY_NULLPTR nullptr +# ifndef YY_CAST +# ifdef __cplusplus +# define YY_CAST(Type, Val) static_cast (Val) +# define YY_REINTERPRET_CAST(Type, Val) reinterpret_cast (Val) # else -# define YY_NULLPTR 0 +# define YY_CAST(Type, Val) ((Type) (Val)) +# define YY_REINTERPRET_CAST(Type, Val) ((Type) (Val)) +# endif +# endif +# ifndef YY_NULLPTR +# if defined __cplusplus +# if 201103L <= __cplusplus +# define YY_NULLPTR nullptr +# else +# define YY_NULLPTR 0 +# endif +# else +# define YY_NULLPTR ((void*)0) # endif # endif @@ -107,10 +122,10 @@ static struct chip_instance *cur_chip_instance; # define YYERROR_VERBOSE 0 #endif -/* In a future release of Bison, this section will be replaced - by #include "sconfig.tab.h_shipped". */ -#ifndef YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +/* Use api.header.include to #include this header + instead of duplicating it here. */ +#ifndef YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -162,11 +177,9 @@ extern int yydebug; /* Value type. */ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED - union YYSTYPE { - struct device *dev; struct chip_instance *chip_instance; char *string; @@ -174,7 +187,6 @@ union YYSTYPE }; - typedef union YYSTYPE YYSTYPE; # define YYSTYPE_IS_TRIVIAL 1 # define YYSTYPE_IS_DECLARED 1 @@ -185,9 +197,7 @@ extern YYSTYPE yylval; int yyparse (void); -#endif /* !YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ - -/* Copy the second part of user declarations. */ +#endif /* !YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ @@ -195,28 +205,75 @@ int yyparse (void); # undef short #endif -#ifdef YYTYPE_UINT8 -typedef YYTYPE_UINT8 yytype_uint8; -#else -typedef unsigned char yytype_uint8; +/* On compilers that do not define __PTRDIFF_MAX__ etc., make sure + and (if available) are included + so that the code can choose integer types of a good width. */ + +#ifndef __PTRDIFF_MAX__ +# include /* INFRINGES ON USER NAME SPACE */ +# if defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__ +# include /* INFRINGES ON USER NAME SPACE */ +# define YY_STDINT_H +# endif #endif -#ifdef YYTYPE_INT8 -typedef YYTYPE_INT8 yytype_int8; +/* Narrow types that promote to a signed type and that can represent a + signed or unsigned integer of at least N bits. In tables they can + save space and decrease cache pressure. Promoting to a signed type + helps avoid bugs in integer arithmetic. */ + +#ifdef __INT_LEAST8_MAX__ +typedef __INT_LEAST8_TYPE__ yytype_int8; +#elif defined YY_STDINT_H +typedef int_least8_t yytype_int8; #else typedef signed char yytype_int8; #endif -#ifdef YYTYPE_UINT16 -typedef YYTYPE_UINT16 yytype_uint16; +#ifdef __INT_LEAST16_MAX__ +typedef __INT_LEAST16_TYPE__ yytype_int16; +#elif defined YY_STDINT_H +typedef int_least16_t yytype_int16; #else -typedef unsigned short int yytype_uint16; +typedef short yytype_int16; #endif -#ifdef YYTYPE_INT16 -typedef YYTYPE_INT16 yytype_int16; +#if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__ +typedef __UINT_LEAST8_TYPE__ yytype_uint8; +#elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \ + && UINT_LEAST8_MAX <= INT_MAX) +typedef uint_least8_t yytype_uint8; +#elif !defined __UINT_LEAST8_MAX__ && UCHAR_MAX <= INT_MAX +typedef unsigned char yytype_uint8; #else -typedef short int yytype_int16; +typedef short yytype_uint8; +#endif + +#if defined __UINT_LEAST16_MAX__ && __UINT_LEAST16_MAX__ <= __INT_MAX__ +typedef __UINT_LEAST16_TYPE__ yytype_uint16; +#elif (!defined __UINT_LEAST16_MAX__ && defined YY_STDINT_H \ + && UINT_LEAST16_MAX <= INT_MAX) +typedef uint_least16_t yytype_uint16; +#elif !defined __UINT_LEAST16_MAX__ && USHRT_MAX <= INT_MAX +typedef unsigned short yytype_uint16; +#else +typedef int yytype_uint16; +#endif + +#ifndef YYPTRDIFF_T +# if defined __PTRDIFF_TYPE__ && defined __PTRDIFF_MAX__ +# define YYPTRDIFF_T __PTRDIFF_TYPE__ +# define YYPTRDIFF_MAXIMUM __PTRDIFF_MAX__ +# elif defined PTRDIFF_MAX +# ifndef ptrdiff_t +# include /* INFRINGES ON USER NAME SPACE */ +# endif +# define YYPTRDIFF_T ptrdiff_t +# define YYPTRDIFF_MAXIMUM PTRDIFF_MAX +# else +# define YYPTRDIFF_T long +# define YYPTRDIFF_MAXIMUM LONG_MAX +# endif #endif #ifndef YYSIZE_T @@ -224,15 +281,27 @@ typedef short int yytype_int16; # define YYSIZE_T __SIZE_TYPE__ # elif defined size_t # define YYSIZE_T size_t -# elif ! defined YYSIZE_T +# elif defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__ # include /* INFRINGES ON USER NAME SPACE */ # define YYSIZE_T size_t # else -# define YYSIZE_T unsigned int +# define YYSIZE_T unsigned # endif #endif -#define YYSIZE_MAXIMUM ((YYSIZE_T) -1) +#define YYSIZE_MAXIMUM \ + YY_CAST (YYPTRDIFF_T, \ + (YYPTRDIFF_MAXIMUM < YY_CAST (YYSIZE_T, -1) \ + ? YYPTRDIFF_MAXIMUM \ + : YY_CAST (YYSIZE_T, -1))) + +#define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X)) + +/* Stored state numbers (used for stacks). */ +typedef yytype_int8 yy_state_t; + +/* State numbers in computations. */ +typedef int yy_state_fast_t; #ifndef YY_ # if defined YYENABLE_NLS && YYENABLE_NLS @@ -246,30 +315,19 @@ typedef short int yytype_int16; # endif #endif -#ifndef YY_ATTRIBUTE -# if (defined __GNUC__ \ - && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \ - || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C -# define YY_ATTRIBUTE(Spec) __attribute__(Spec) +#ifndef YY_ATTRIBUTE_PURE +# if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__) +# define YY_ATTRIBUTE_PURE __attribute__ ((__pure__)) # else -# define YY_ATTRIBUTE(Spec) /* empty */ +# define YY_ATTRIBUTE_PURE # endif #endif -#ifndef YY_ATTRIBUTE_PURE -# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__)) -#endif - #ifndef YY_ATTRIBUTE_UNUSED -# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__)) -#endif - -#if !defined _Noreturn \ - && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112) -# if defined _MSC_VER && 1200 <= _MSC_VER -# define _Noreturn __declspec (noreturn) +# if defined __GNUC__ && 2 < __GNUC__ + (7 <= __GNUC_MINOR__) +# define YY_ATTRIBUTE_UNUSED __attribute__ ((__unused__)) # else -# define _Noreturn YY_ATTRIBUTE ((__noreturn__)) +# define YY_ATTRIBUTE_UNUSED # endif #endif @@ -280,13 +338,13 @@ typedef short int yytype_int16; # define YYUSE(E) /* empty */ #endif -#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ +#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ /* Suppress an incorrect diagnostic about yylval being uninitialized. */ -# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ - _Pragma ("GCC diagnostic push") \ - _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\ +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ + _Pragma ("GCC diagnostic push") \ + _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") \ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") -# define YY_IGNORE_MAYBE_UNINITIALIZED_END \ +# define YY_IGNORE_MAYBE_UNINITIALIZED_END \ _Pragma ("GCC diagnostic pop") #else # define YY_INITIAL_VALUE(Value) Value @@ -299,6 +357,20 @@ typedef short int yytype_int16; # define YY_INITIAL_VALUE(Value) /* Nothing. */ #endif +#if defined __cplusplus && defined __GNUC__ && ! defined __ICC && 6 <= __GNUC__ +# define YY_IGNORE_USELESS_CAST_BEGIN \ + _Pragma ("GCC diagnostic push") \ + _Pragma ("GCC diagnostic ignored \"-Wuseless-cast\"") +# define YY_IGNORE_USELESS_CAST_END \ + _Pragma ("GCC diagnostic pop") +#endif +#ifndef YY_IGNORE_USELESS_CAST_BEGIN +# define YY_IGNORE_USELESS_CAST_BEGIN +# define YY_IGNORE_USELESS_CAST_END +#endif + + +#define YY_ASSERT(E) ((void) (0 && (E))) #if ! defined yyoverflow || YYERROR_VERBOSE @@ -375,17 +447,17 @@ void free (void *); /* INFRINGES ON USER NAME SPACE */ /* A type that is properly aligned for any stack member. */ union yyalloc { - yytype_int16 yyss_alloc; + yy_state_t yyss_alloc; YYSTYPE yyvs_alloc; }; /* The size of the maximum gap between one aligned stack and the next. */ -# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1) +# define YYSTACK_GAP_MAXIMUM (YYSIZEOF (union yyalloc) - 1) /* The size of an array large to enough to hold all stacks, each with N elements. */ # define YYSTACK_BYTES(N) \ - ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \ + ((N) * (YYSIZEOF (yy_state_t) + YYSIZEOF (YYSTYPE)) \ + YYSTACK_GAP_MAXIMUM) # define YYCOPY_NEEDED 1 @@ -398,11 +470,11 @@ union yyalloc # define YYSTACK_RELOCATE(Stack_alloc, Stack) \ do \ { \ - YYSIZE_T yynewbytes; \ + YYPTRDIFF_T yynewbytes; \ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ Stack = &yyptr->Stack_alloc; \ - yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ - yyptr += yynewbytes / sizeof (*yyptr); \ + yynewbytes = yystacksize * YYSIZEOF (*Stack) + YYSTACK_GAP_MAXIMUM; \ + yyptr += yynewbytes / YYSIZEOF (*yyptr); \ } \ while (0) @@ -414,12 +486,12 @@ union yyalloc # ifndef YYCOPY # if defined __GNUC__ && 1 < __GNUC__ # define YYCOPY(Dst, Src, Count) \ - __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src))) + __builtin_memcpy (Dst, Src, YY_CAST (YYSIZE_T, (Count)) * sizeof (*(Src))) # else # define YYCOPY(Dst, Src, Count) \ do \ { \ - YYSIZE_T yyi; \ + YYPTRDIFF_T yyi; \ for (yyi = 0; yyi < (Count); yyi++) \ (Dst)[yyi] = (Src)[yyi]; \ } \ @@ -431,28 +503,29 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 40 +#define YYLAST 45 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 36 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 15 /* YYNRULES -- Number of rules. */ -#define YYNRULES 28 +#define YYNRULES 29 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 49 +#define YYNSTATES 50 -/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned - by yylex, with out-of-bounds checking. */ #define YYUNDEFTOK 2 #define YYMAXUTOK 290 + +/* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM + as returned by yylex, with out-of-bounds checking. */ #define YYTRANSLATE(YYX) \ - ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) + (0 <= (YYX) && (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) /* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM - as returned by yylex, without out-of-bounds checking. */ -static const yytype_uint8 yytranslate[] = + as returned by yylex. */ +static const yytype_int8 yytranslate[] = { 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -488,11 +561,11 @@ static const yytype_uint8 yytranslate[] = #if YYDEBUG /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ -static const yytype_uint8 yyrline[] = +static const yytype_int8 yyrline[] = { 0, 36, 36, 36, 38, 38, 38, 38, 40, 40, - 40, 40, 40, 40, 40, 42, 42, 51, 51, 59, - 59, 61, 64, 67, 70, 73, 76, 79, 82 + 40, 40, 40, 40, 40, 40, 42, 42, 51, 51, + 59, 59, 61, 64, 67, 70, 73, 76, 79, 82 }; #endif @@ -515,7 +588,7 @@ static const char *const yytname[] = # ifdef YYPRINT /* YYTOKNUM[NUM] -- (External) token number corresponding to the (internal) symbol number NUM (which must be that of a token). */ -static const yytype_uint16 yytoknum[] = +static const yytype_int16 yytoknum[] = { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, @@ -524,99 +597,99 @@ static const yytype_uint16 yytoknum[] = }; # endif -#define YYPACT_NINF -12 +#define YYPACT_NINF (-10) -#define yypact_value_is_default(Yystate) \ - (!!((Yystate) == (-12))) +#define yypact_value_is_default(Yyn) \ + ((Yyn) == YYPACT_NINF) -#define YYTABLE_NINF -1 +#define YYTABLE_NINF (-1) -#define yytable_value_is_error(Yytable_value) \ +#define yytable_value_is_error(Yyn) \ 0 /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ static const yytype_int8 yypact[] = { - -12, 6, 9, -12, -1, -12, -12, -12, 0, 5, - 1, -12, -12, -12, -12, -10, 7, 3, 8, -12, - -12, -12, -12, -12, -3, -9, -12, 11, 2, 4, - -12, -12, -12, -12, -12, -12, 15, 17, 10, -11, - 12, 18, -5, 13, -12, 19, -12, -12, -12 + -10, 11, 10, -10, 0, -10, -10, -10, 1, 6, + 2, -10, -10, -10, -10, -9, 8, 3, 4, -10, + -10, -10, -10, -10, -3, -4, -10, 9, -1, 5, + -10, -10, -10, -10, -10, -10, -10, 15, 14, 7, + -2, 12, 16, 13, 17, -10, 18, -10, -10, -10 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. Performed when YYTABLE does not specify something else to do. Zero means the default is an error. */ -static const yytype_uint8 yydefact[] = +static const yytype_int8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 15, 7, 0, 0, - 0, 16, 5, 4, 6, 0, 0, 0, 0, 19, - 20, 17, 22, 14, 0, 0, 18, 0, 0, 0, - 9, 8, 10, 11, 12, 13, 0, 0, 0, 0, - 0, 28, 23, 0, 21, 27, 24, 25, 26 + 2, 0, 0, 1, 0, 3, 16, 7, 0, 0, + 0, 17, 5, 4, 6, 0, 0, 0, 0, 20, + 21, 18, 23, 15, 0, 0, 19, 0, 0, 0, + 9, 8, 10, 14, 11, 12, 13, 0, 0, 0, + 0, 0, 29, 24, 0, 22, 28, 25, 26, 27 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -12, -12, -12, -12, -12, -6, -12, 16, -12, -12, - -12, -12, -12, -12, -12 + -10, -10, -10, -10, -10, -5, -10, 20, -10, -10, + -10, 21, -10, -10, -10 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { -1, 1, 2, 8, 24, 5, 7, 13, 23, 21, - 32, 14, 33, 34, 35 + 32, 14, 34, 35, 36 }; /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If positive, shift that token. If negative, reduce the rule whose number is the opposite. If YYTABLE_NINF, syntax error. */ -static const yytype_uint8 yytable[] = +static const yytype_int8 yytable[] = { - 4, 9, 12, 4, 9, 10, 3, 25, 26, 19, - 20, 11, 4, 6, 15, 16, 17, 36, 30, 18, - 43, 27, 22, 46, 28, 37, 29, 40, 38, 0, - 39, 41, 45, 48, 0, 0, 42, 0, 44, 47, - 31 + 4, 9, 10, 12, 4, 9, 10, 25, 26, 19, + 20, 3, 11, 4, 6, 15, 16, 17, 22, 30, + 18, 27, 37, 38, 28, 39, 29, 41, 42, 44, + 46, 40, 49, 43, 0, 0, 0, 0, 45, 0, + 0, 47, 0, 48, 31, 33 }; static const yytype_int8 yycheck[] = { - 3, 4, 8, 3, 4, 5, 0, 10, 11, 6, - 7, 11, 3, 14, 9, 14, 26, 26, 24, 12, - 31, 24, 14, 28, 27, 14, 29, 12, 26, -1, - 26, 14, 14, 14, -1, -1, 26, -1, 26, 26, - 24 + 3, 4, 5, 8, 3, 4, 5, 10, 11, 6, + 7, 0, 11, 3, 14, 9, 14, 26, 14, 24, + 12, 24, 26, 14, 27, 26, 29, 12, 14, 31, + 14, 26, 14, 26, -1, -1, -1, -1, 26, -1, + -1, 28, -1, 26, 24, 24 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ -static const yytype_uint8 yystos[] = +static const yytype_int8 yystos[] = { 0, 37, 38, 0, 3, 41, 14, 42, 39, 4, 5, 11, 41, 43, 47, 9, 14, 26, 12, 6, 7, 45, 14, 44, 40, 10, 11, 24, 27, 29, - 41, 43, 46, 48, 49, 50, 26, 14, 26, 26, - 12, 14, 26, 31, 26, 14, 28, 26, 14 + 41, 43, 46, 47, 48, 49, 50, 26, 14, 26, + 26, 12, 14, 26, 31, 26, 14, 28, 26, 14 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ -static const yytype_uint8 yyr1[] = +static const yytype_int8 yyr1[] = { 0, 36, 38, 37, 39, 39, 39, 39, 40, 40, - 40, 40, 40, 40, 40, 42, 41, 44, 43, 45, - 45, 46, 47, 48, 48, 49, 50, 50, 50 + 40, 40, 40, 40, 40, 40, 42, 41, 44, 43, + 45, 45, 46, 47, 48, 48, 49, 50, 50, 50 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ -static const yytype_uint8 yyr2[] = +static const yytype_int8 yyr2[] = { 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 2, 0, 0, 5, 0, 7, 1, - 1, 4, 4, 3, 4, 4, 5, 4, 3 + 2, 2, 2, 2, 2, 0, 0, 5, 0, 7, + 1, 1, 4, 4, 3, 4, 4, 5, 4, 3 }; @@ -632,22 +705,22 @@ static const yytype_uint8 yyr2[] = #define YYRECOVERING() (!!yyerrstatus) -#define YYBACKUP(Token, Value) \ -do \ - if (yychar == YYEMPTY) \ - { \ - yychar = (Token); \ - yylval = (Value); \ - YYPOPSTACK (yylen); \ - yystate = *yyssp; \ - goto yybackup; \ - } \ - else \ - { \ - yyerror (YY_("syntax error: cannot back up")); \ - YYERROR; \ - } \ -while (0) +#define YYBACKUP(Token, Value) \ + do \ + if (yychar == YYEMPTY) \ + { \ + yychar = (Token); \ + yylval = (Value); \ + YYPOPSTACK (yylen); \ + yystate = *yyssp; \ + goto yybackup; \ + } \ + else \ + { \ + yyerror (YY_("syntax error: cannot back up")); \ + YYERROR; \ + } \ + while (0) /* Error token number */ #define YYTERROR 1 @@ -687,37 +760,39 @@ do { \ } while (0) -/*----------------------------------------. -| Print this symbol's value on YYOUTPUT. | -`----------------------------------------*/ +/*-----------------------------------. +| Print this symbol's value on YYO. | +`-----------------------------------*/ static void -yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) { - FILE *yyo = yyoutput; - YYUSE (yyo); + FILE *yyoutput = yyo; + YYUSE (yyoutput); if (!yyvaluep) return; # ifdef YYPRINT if (yytype < YYNTOKENS) - YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep); + YYPRINT (yyo, yytoknum[yytype], *yyvaluep); # endif + YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN YYUSE (yytype); + YY_IGNORE_MAYBE_UNINITIALIZED_END } -/*--------------------------------. -| Print this symbol on YYOUTPUT. | -`--------------------------------*/ +/*---------------------------. +| Print this symbol on YYO. | +`---------------------------*/ static void -yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) { - YYFPRINTF (yyoutput, "%s %s (", + YYFPRINTF (yyo, "%s %s (", yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); - yy_symbol_value_print (yyoutput, yytype, yyvaluep); - YYFPRINTF (yyoutput, ")"); + yy_symbol_value_print (yyo, yytype, yyvaluep); + YYFPRINTF (yyo, ")"); } /*------------------------------------------------------------------. @@ -726,7 +801,7 @@ yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) `------------------------------------------------------------------*/ static void -yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop) +yy_stack_print (yy_state_t *yybottom, yy_state_t *yytop) { YYFPRINTF (stderr, "Stack now"); for (; yybottom <= yytop; yybottom++) @@ -749,20 +824,20 @@ do { \ `------------------------------------------------*/ static void -yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule) +yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) { - unsigned long int yylno = yyrline[yyrule]; + int yylno = yyrline[yyrule]; int yynrhs = yyr2[yyrule]; int yyi; - YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n", + YYFPRINTF (stderr, "Reducing stack by rule %d (line %d):\n", yyrule - 1, yylno); /* The symbols being reduced. */ for (yyi = 0; yyi < yynrhs; yyi++) { YYFPRINTF (stderr, " $%d = ", yyi + 1); yy_symbol_print (stderr, - yystos[yyssp[yyi + 1 - yynrhs]], - &(yyvsp[(yyi + 1) - (yynrhs)]) + yystos[+yyssp[yyi + 1 - yynrhs]], + &yyvsp[(yyi + 1) - (yynrhs)] ); YYFPRINTF (stderr, "\n"); } @@ -806,13 +881,13 @@ int yydebug; # ifndef yystrlen # if defined __GLIBC__ && defined _STRING_H -# define yystrlen strlen +# define yystrlen(S) (YY_CAST (YYPTRDIFF_T, strlen (S))) # else /* Return the length of YYSTR. */ -static YYSIZE_T +static YYPTRDIFF_T yystrlen (const char *yystr) { - YYSIZE_T yylen; + YYPTRDIFF_T yylen; for (yylen = 0; yystr[yylen]; yylen++) continue; return yylen; @@ -848,12 +923,12 @@ yystpcpy (char *yydest, const char *yysrc) backslash-backslash). YYSTR is taken from yytname. If YYRES is null, do not copy; instead, return the length of what the result would have been. */ -static YYSIZE_T +static YYPTRDIFF_T yytnamerr (char *yyres, const char *yystr) { if (*yystr == '"') { - YYSIZE_T yyn = 0; + YYPTRDIFF_T yyn = 0; char const *yyp = yystr; for (;;) @@ -866,7 +941,10 @@ yytnamerr (char *yyres, const char *yystr) case '\\': if (*++yyp != '\\') goto do_not_strip_quotes; - /* Fall through. */ + else + goto append; + + append: default: if (yyres) yyres[yyn] = *yyp; @@ -881,10 +959,10 @@ yytnamerr (char *yyres, const char *yystr) do_not_strip_quotes: ; } - if (! yyres) + if (yyres) + return yystpcpy (yyres, yystr) - yyres; + else return yystrlen (yystr); - - return yystpcpy (yyres, yystr) - yyres; } # endif @@ -897,19 +975,19 @@ yytnamerr (char *yyres, const char *yystr) *YYMSG_ALLOC to the required number of bytes. Return 2 if the required number of bytes is too large to store. */ static int -yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, - yytype_int16 *yyssp, int yytoken) +yysyntax_error (YYPTRDIFF_T *yymsg_alloc, char **yymsg, + yy_state_t *yyssp, int yytoken) { - YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); - YYSIZE_T yysize = yysize0; enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; /* Internationalized format string. */ const char *yyformat = YY_NULLPTR; - /* Arguments of yyformat. */ + /* Arguments of yyformat: reported tokens (one for the "unexpected", + one per "expected"). */ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; - /* Number of reported tokens (one for the "unexpected", one per - "expected"). */ + /* Actual size of YYARG. */ int yycount = 0; + /* Cumulated lengths of YYARG. */ + YYPTRDIFF_T yysize = 0; /* There are many possibilities here to consider: - If this state is a consistent state with a default action, then @@ -936,7 +1014,9 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, */ if (yytoken != YYEMPTY) { - int yyn = yypact[*yyssp]; + int yyn = yypact[+*yyssp]; + YYPTRDIFF_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); + yysize = yysize0; yyarg[yycount++] = yytname[yytoken]; if (!yypact_value_is_default (yyn)) { @@ -961,11 +1041,12 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, } yyarg[yycount++] = yytname[yyx]; { - YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); - if (! (yysize <= yysize1 - && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + YYPTRDIFF_T yysize1 + = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); + if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) + yysize = yysize1; + else return 2; - yysize = yysize1; } } } @@ -977,6 +1058,7 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, case N: \ yyformat = S; \ break + default: /* Avoid compiler warnings. */ YYCASE_(0, YY_("syntax error")); YYCASE_(1, YY_("syntax error, unexpected %s")); YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); @@ -987,10 +1069,13 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, } { - YYSIZE_T yysize1 = yysize + yystrlen (yyformat); - if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + /* Don't count the "%s"s in the final size, but reserve room for + the terminator. */ + YYPTRDIFF_T yysize1 = yysize + (yystrlen (yyformat) - 2 * yycount) + 1; + if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) + yysize = yysize1; + else return 2; - yysize = yysize1; } if (*yymsg_alloc < yysize) @@ -1016,8 +1101,8 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, } else { - yyp++; - yyformat++; + ++yyp; + ++yyformat; } } return 0; @@ -1060,7 +1145,7 @@ int yynerrs; int yyparse (void) { - int yystate; + yy_state_fast_t yystate; /* Number of tokens to shift before error messages enabled. */ int yyerrstatus; @@ -1072,16 +1157,16 @@ yyparse (void) to reallocate them elsewhere. */ /* The state stack. */ - yytype_int16 yyssa[YYINITDEPTH]; - yytype_int16 *yyss; - yytype_int16 *yyssp; + yy_state_t yyssa[YYINITDEPTH]; + yy_state_t *yyss; + yy_state_t *yyssp; /* The semantic value stack. */ YYSTYPE yyvsa[YYINITDEPTH]; YYSTYPE *yyvs; YYSTYPE *yyvsp; - YYSIZE_T yystacksize; + YYPTRDIFF_T yystacksize; int yyn; int yyresult; @@ -1095,7 +1180,7 @@ yyparse (void) /* Buffer for error messages, and its allocated size. */ char yymsgbuf[128]; char *yymsg = yymsgbuf; - YYSIZE_T yymsg_alloc = sizeof yymsgbuf; + YYPTRDIFF_T yymsg_alloc = sizeof yymsgbuf; #endif #define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) @@ -1116,46 +1201,54 @@ yyparse (void) yychar = YYEMPTY; /* Cause a token to be read. */ goto yysetstate; + /*------------------------------------------------------------. -| yynewstate -- Push a new state, which is found in yystate. | +| yynewstate -- push a new state, which is found in yystate. | `------------------------------------------------------------*/ - yynewstate: +yynewstate: /* In all cases, when you get here, the value and location stacks have just been pushed. So pushing a state here evens the stacks. */ yyssp++; - yysetstate: - *yyssp = yystate; + +/*--------------------------------------------------------------------. +| yysetstate -- set current state (the top of the stack) to yystate. | +`--------------------------------------------------------------------*/ +yysetstate: + YYDPRINTF ((stderr, "Entering state %d\n", yystate)); + YY_ASSERT (0 <= yystate && yystate < YYNSTATES); + YY_IGNORE_USELESS_CAST_BEGIN + *yyssp = YY_CAST (yy_state_t, yystate); + YY_IGNORE_USELESS_CAST_END if (yyss + yystacksize - 1 <= yyssp) +#if !defined yyoverflow && !defined YYSTACK_RELOCATE + goto yyexhaustedlab; +#else { /* Get the current used size of the three stacks, in elements. */ - YYSIZE_T yysize = yyssp - yyss + 1; + YYPTRDIFF_T yysize = yyssp - yyss + 1; -#ifdef yyoverflow +# if defined yyoverflow { /* Give user a chance to reallocate the stack. Use copies of these so that the &'s don't force the real ones into memory. */ + yy_state_t *yyss1 = yyss; YYSTYPE *yyvs1 = yyvs; - yytype_int16 *yyss1 = yyss; /* Each stack pointer address is followed by the size of the data in use in that stack, in bytes. This used to be a conditional around just the two extra args, but that might be undefined if yyoverflow is a macro. */ yyoverflow (YY_("memory exhausted"), - &yyss1, yysize * sizeof (*yyssp), - &yyvs1, yysize * sizeof (*yyvsp), + &yyss1, yysize * YYSIZEOF (*yyssp), + &yyvs1, yysize * YYSIZEOF (*yyvsp), &yystacksize); - yyss = yyss1; yyvs = yyvs1; } -#else /* no yyoverflow */ -# ifndef YYSTACK_RELOCATE - goto yyexhaustedlab; -# else +# else /* defined YYSTACK_RELOCATE */ /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) goto yyexhaustedlab; @@ -1164,42 +1257,43 @@ yyparse (void) yystacksize = YYMAXDEPTH; { - yytype_int16 *yyss1 = yyss; + yy_state_t *yyss1 = yyss; union yyalloc *yyptr = - (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); + YY_CAST (union yyalloc *, + YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize)))); if (! yyptr) goto yyexhaustedlab; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); -# undef YYSTACK_RELOCATE +# undef YYSTACK_RELOCATE if (yyss1 != yyssa) YYSTACK_FREE (yyss1); } # endif -#endif /* no yyoverflow */ yyssp = yyss + yysize - 1; yyvsp = yyvs + yysize - 1; - YYDPRINTF ((stderr, "Stack size increased to %lu\n", - (unsigned long int) yystacksize)); + YY_IGNORE_USELESS_CAST_BEGIN + YYDPRINTF ((stderr, "Stack size increased to %ld\n", + YY_CAST (long, yystacksize))); + YY_IGNORE_USELESS_CAST_END if (yyss + yystacksize - 1 <= yyssp) YYABORT; } - - YYDPRINTF ((stderr, "Entering state %d\n", yystate)); +#endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */ if (yystate == YYFINAL) YYACCEPT; goto yybackup; + /*-----------. | yybackup. | `-----------*/ yybackup: - /* Do appropriate processing given the current state. Read a lookahead token if we need one and don't already have one. */ @@ -1249,15 +1343,13 @@ yybackup: /* Shift the lookahead token. */ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc); - - /* Discard the shifted token. */ - yychar = YYEMPTY; - yystate = yyn; YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN *++yyvsp = yylval; YY_IGNORE_MAYBE_UNINITIALIZED_END + /* Discard the shifted token. */ + yychar = YYEMPTY; goto yynewstate; @@ -1272,7 +1364,7 @@ yydefault: /*-----------------------------. -| yyreduce -- Do a reduction. | +| yyreduce -- do a reduction. | `-----------------------------*/ yyreduce: /* yyn is the number of a rule to reduce with. */ @@ -1292,93 +1384,67 @@ yyreduce: YY_REDUCE_PRINT (yyn); switch (yyn) { - case 2: - - { cur_parent = root_parent; } - + case 2: + { cur_parent = root_parent; } break; - case 15: - - { + case 16: + { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); chip_enqueue_tail(cur_chip_instance); cur_chip_instance = (yyval.chip_instance); } - - break; - - case 16: - - { - cur_chip_instance = chip_dequeue_tail(); -} - break; case 17: - - { - (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); - cur_parent = (yyval.dev)->last_bus; + { + cur_chip_instance = chip_dequeue_tail(); } - break; case 18: - - { - cur_parent = (yyvsp[-2].dev)->parent; + { + (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); + cur_parent = (yyval.dev)->last_bus; } - break; - case 21: - - { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } - + case 19: + { + cur_parent = (yyvsp[-2].dev)->parent; +} break; case 22: - - { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } - + { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; case 23: - - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } - + { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; case 24: - - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } - + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; case 25: - - { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } - + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; case 26: - - { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } - + { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; case 27: - - { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } - + { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } break; case 28: + { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } + break; - { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } - + case 29: + { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } break; @@ -1407,14 +1473,13 @@ yyreduce: /* Now 'shift' the result of the reduction. Determine what state that goes to, based on the state we popped back to and the rule number reduced by. */ - - yyn = yyr1[yyn]; - - yystate = yypgoto[yyn - YYNTOKENS] + *yyssp; - if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp) - yystate = yytable[yystate]; - else - yystate = yydefgoto[yyn - YYNTOKENS]; + { + const int yylhs = yyr1[yyn] - YYNTOKENS; + const int yyi = yypgoto[yylhs] + *yyssp; + yystate = (0 <= yyi && yyi <= YYLAST && yycheck[yyi] == *yyssp + ? yytable[yyi] + : yydefgoto[yylhs]); + } goto yynewstate; @@ -1446,7 +1511,7 @@ yyerrlab: { if (yymsg != yymsgbuf) YYSTACK_FREE (yymsg); - yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc); + yymsg = YY_CAST (char *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, yymsg_alloc))); if (!yymsg) { yymsg = yymsgbuf; @@ -1497,12 +1562,10 @@ yyerrlab: | yyerrorlab -- error raised explicitly by YYERROR. | `---------------------------------------------------*/ yyerrorlab: - - /* Pacify compilers like GCC when the user code never invokes - YYERROR and the label yyerrorlab therefore never appears in user - code. */ - if (/*CONSTCOND*/ 0) - goto yyerrorlab; + /* Pacify compilers when the user code never invokes YYERROR and the + label yyerrorlab therefore never appears in user code. */ + if (0) + YYERROR; /* Do not reclaim the symbols of the rule whose action triggered this YYERROR. */ @@ -1564,6 +1627,7 @@ yyacceptlab: yyresult = 0; goto yyreturn; + /*-----------------------------------. | yyabortlab -- YYABORT comes here. | `-----------------------------------*/ @@ -1571,6 +1635,7 @@ yyabortlab: yyresult = 1; goto yyreturn; + #if !defined yyoverflow || YYERROR_VERBOSE /*-------------------------------------------------. | yyexhaustedlab -- memory exhaustion comes here. | @@ -1581,6 +1646,10 @@ yyexhaustedlab: /* Fall through. */ #endif + +/*-----------------------------------------------------. +| yyreturn -- parsing is finished, return the result. | +`-----------------------------------------------------*/ yyreturn: if (yychar != YYEMPTY) { @@ -1597,7 +1666,7 @@ yyreturn: while (yyssp != yyss) { yydestruct ("Cleanup: popping", - yystos[*yyssp], yyvsp); + yystos[+*yyssp], yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow @@ -1611,4 +1680,3 @@ yyreturn: return yyresult; } - diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index 272f651222..f93daea392 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,8 +1,9 @@ -/* A Bison parser, made by GNU Bison 3.0.4. */ +/* A Bison parser, made by GNU Bison 3.5.4. */ /* Bison interface for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2020 Free Software Foundation, + Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -30,8 +31,11 @@ This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ -#ifndef YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +/* Undocumented macros, especially those whose name start with YY_, + are private implementation details. Do not rely on them. */ + +#ifndef YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -83,11 +87,9 @@ extern int yydebug; /* Value type. */ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED - union YYSTYPE { - struct device *dev; struct chip_instance *chip_instance; char *string; @@ -95,7 +97,6 @@ union YYSTYPE }; - typedef union YYSTYPE YYSTYPE; # define YYSTYPE_IS_TRIVIAL 1 # define YYSTYPE_IS_DECLARED 1 @@ -106,4 +107,4 @@ extern YYSTYPE yylval; int yyparse (void); -#endif /* !YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index d55b18bda9..4af6e1835a 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -37,7 +37,7 @@ devtree: { cur_parent = root_parent; } chip; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren registers | /* empty */ ; chip: CHIP STRING /* == path */ { $$ = new_chip_instance($2); From 8c2872964abeaa32221a04785f7eeac4d1835663 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 4 May 2020 14:46:25 -0500 Subject: [PATCH 1420/1463] mb/purism/librem_{bdw,skl}: select MAINBOARD_HAS_TPM1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Current model Librems all have a TPM 1.2 module, so select it at the board level to avoid having to do so in .config. Signed-off-by: Matt DeVillier Change-Id: Iab8b39c39aef2a3fc182f1a50091f84f2151a394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41038 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel --- src/mainboard/purism/librem_bdw/Kconfig | 1 + src/mainboard/purism/librem_skl/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 27ae21f8aa..dcfe78e752 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -8,6 +8,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM1 select SOC_INTEL_BROADWELL if BOARD_PURISM_BASEBOARD_LIBREM_BDW diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 7a73823f15..c1a9aecda7 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -6,6 +6,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_KABYLAKE if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 From 4a36cfb625653a1849edd7651ed81a0c7007a612 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 4 May 2020 16:11:42 -0500 Subject: [PATCH 1421/1463] mb/purism/librem_skl: select DRIVERS_GENERIC_CBFS_SERIAL This driver was previously added for another out-of-tree Librem device, but forgot to switch over the librem_skl boards to use it. Remove duplicate functionality from mainboard.c and delete the empty file. Test: build/boot Librem 13v2 and verify serial number read from CBFS via dmidecode. Signed-off-by: Matt DeVillier Change-Id: Ide952197335c6bfbad846c6d6f62be5c4c57e2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/mainboard/purism/librem_skl/Kconfig | 1 + src/mainboard/purism/librem_skl/mainboard.c | 38 --------------------- 2 files changed, 1 insertion(+), 38 deletions(-) delete mode 100644 src/mainboard/purism/librem_skl/mainboard.c diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index c1a9aecda7..9760a2f9e7 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -1,6 +1,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL def_bool n select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_CBFS_SERIAL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/purism/librem_skl/mainboard.c b/src/mainboard/purism/librem_skl/mainboard.c deleted file mode 100644 index eb28262eb5..0000000000 --- a/src/mainboard/purism/librem_skl/mainboard.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include -#include -#include - -#define MAX_SERIAL_LENGTH 0x100 - -const char *smbios_mainboard_serial_number(void) -{ - static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; - struct cbfsf file; - - if (serial_number[0] != 0) - return serial_number; - - if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { - struct region_device cbfs_region; - size_t serial_len; - - cbfs_file_data(&cbfs_region, &file); - - serial_len = region_device_sz(&cbfs_region); - if (serial_len <= MAX_SERIAL_LENGTH) { - if (rdev_readat(&cbfs_region, serial_number, 0, - serial_len) == serial_len) { - serial_number[serial_len] = 0; - return serial_number; - } - } - } - - strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, - MAX_SERIAL_LENGTH); - - return serial_number; -} From 0985fba3705607ecf571082b241018c0d1bd962d Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 4 May 2020 13:36:23 -0600 Subject: [PATCH 1422/1463] mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree BUG=None TEST=Build and boot the mainboard. Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037 Reviewed-by: Tim Wawrzynczak Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- .../google/dedede/variants/baseboard/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cfe221f994..c891e6e376 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -289,11 +289,11 @@ chip soc/intel/jasperlake device pnp 0c09.0 on end end end # eSPI Interface - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI + device pci 1f.5 on end # PCH SPI device pci 1f.7 off end # Intel Trace Hub end end From 18e632f8b33b8c764db124e65b9ccab16044f108 Mon Sep 17 00:00:00 2001 From: "derek.huang" Date: Fri, 24 Apr 2020 17:35:59 +0800 Subject: [PATCH 1423/1463] elog: Add new elog types for CSME-initiated host reset Change-Id: Iddae1c7cbc71ce10b126a1e05abf9269e8187a38 Signed-off-by: derek.huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/40687 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/include/elog.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index 68a4842feb..7df1bfb38c 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -195,6 +195,12 @@ struct elog_event_mem_cache_update { /* Cr50 reset to enable TPM */ #define ELOG_TYPE_CR50_NEED_RESET 0xb2 +/* CSME-Initiated Host Reset */ +#define ELOG_TYPE_MI_HRPD 0xb3 +#define ELOG_TYPE_MI_HRPC 0xb4 +#define ELOG_TYPE_MI_HR 0xb5 + + struct elog_event_extended_event { u8 event_type; u32 event_complement; From e685107dd61461f91d3fdbf722cf378e121e2551 Mon Sep 17 00:00:00 2001 From: "derek.huang" Date: Thu, 23 Apr 2020 14:55:24 +0800 Subject: [PATCH 1424/1463] soc/intel/tigerlake: Print HPR_CAUSE0 register In addition to GBLRST_CAUSE0 and GBLRST_CAUSE1, print the value of HPR_CAUSE0. Change-Id: Idc57c3cd6a8d156c5544640898e8e7147d34c535 Signed-off-by: derek.huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/40648 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/include/soc/pm.h | 1 + src/soc/intel/tigerlake/include/soc/pmc.h | 4 ++++ src/soc/intel/tigerlake/pmutil.c | 3 +++ 3 files changed, 8 insertions(+) diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index c42e280ed1..c69fe3edb8 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -150,6 +150,7 @@ struct chipset_power_state { uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; uint32_t prev_sleep_state; } __packed; diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 88c6f61d94..9ad3391348 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -119,6 +119,10 @@ #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define HPR_CAUSE0 0x192C +#define HPR_CAUSE0_MI_HRPD (1 << 10) +#define HPR_CAUSE0_MI_HRPC (1 << 9) +#define HPR_CAUSE0_MI_HR (1 << 8) #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 4482b1ec55..554932bd72 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -260,12 +260,15 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + ps->hpr_cause0 = read32(pmc + HPR_CAUSE0); printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b); printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); + + printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } /* STM Support */ From 56e3df459abafdd9d00fcd0a8ddca7db4730874a Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 24 Mar 2020 00:24:59 -0700 Subject: [PATCH 1425/1463] soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel Kernel pinctrl driver changed for Tiger Lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BUG=b:151683980 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Cq-Depend:chromium:2116670 Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/deltaur/variants/baseboard/gpio.c | 4 +- .../google/volteer/variants/baseboard/gpio.c | 4 +- .../google/volteer/variants/ripto/gpio.c | 4 +- .../intel/tglrvp/variants/tglrvp_up3/gpio.c | 2 +- .../intel/tglrvp/variants/tglrvp_up4/gpio.c | 2 +- src/soc/intel/tigerlake/acpi/gpio.asl | 96 +++++-------------- src/soc/intel/tigerlake/gpio.c | 35 ++++--- src/soc/intel/tigerlake/include/soc/gpio.h | 7 +- 8 files changed, 57 insertions(+), 97 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index c56fff818b..905a6d22f7 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -407,8 +407,8 @@ const struct pad_config *__weak variant_base_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 37211ff796..31ff3fc2f2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -459,8 +459,8 @@ const struct pad_config *__weak variant_early_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c index 856f7fd23d..fcc1848f25 100644 --- a/src/mainboard/google/volteer/variants/ripto/gpio.c +++ b/src/mainboard/google/volteer/variants/ripto/gpio.c @@ -444,8 +444,8 @@ const struct pad_config *variant_early_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *variant_cros_gpios(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 79ffd38f27..5f36b0b66b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -105,7 +105,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *variant_cros_gpios(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 27d610b48c..743d593984 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -102,7 +102,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *variant_cros_gpios(size_t *num) diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index 9b8a175659..d1e4955e4a 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -1,103 +1,57 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include +#include #include #include -#include -#include #include "gpio_op.asl" -Device (GCM0) +Device (GPIO) { - Name (_HID, CROS_GPIO_NAME) + Name (_HID, "INT34C5") Name (_UID, 0) - Name (_DDN, "GPIO Controller Community 0") + Name (_DDN, "GPIO Controller") Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { GPIO_IRQ14 } }) Method (_CRS, 0, NotSerialized) { + /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) BAS0 = ^^PCRB (PID_GPIOCOM0) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + LEN0 = GPIO_BASE_SIZE -Device (GCM1) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 1) - Name (_DDN, "GPIO Controller Community 1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) BAS1 = ^^PCRB (PID_GPIOCOM1) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + LEN1 = GPIO_BASE_SIZE -Device (GCM4) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 4) - Name (_DDN, "GPIO Controller Community 4") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) BAS4 = ^^PCRB (PID_GPIOCOM4) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} + LEN4 = GPIO_BASE_SIZE -Device (GCM5) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 5) - Name (_DDN, "GPIO Controller Community 5") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { + /* GPIO Community 5 */ CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) BAS5 = ^^PCRB (PID_GPIOCOM5) - Return (^RBUF) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) } - Method (_STA) + + Method (_STA, 0, NotSerialized) { Return (0xF) } diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c index cfdd0ac465..f96262a74e 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio.c @@ -37,21 +37,30 @@ static const struct reset_mapping rst_map_com2[] = { }; /* - * This layout matches the Linux kernel pinctrl map for TGL-LP at: + * The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for TGL at: * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c */ static const struct pad_group tgl_community0_groups[] = { - INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */ - INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */ - INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */ + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64), /* GPP_A */ }; static const struct pad_group tgl_community1_groups[] = { - INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */ - INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */ - INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */ - INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */ - INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */ + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ + INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192), /* GPP_U */ + INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224), /* GPP_VGPIO */ }; /* This community is not visible to the OS */ @@ -60,15 +69,15 @@ static const struct pad_group tgl_community2_groups[] = { }; static const struct pad_group tgl_community4_groups[] = { - INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ - INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */ + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ - INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */ }; static const struct pad_group tgl_community5_groups[] = { - INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */ + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ }; diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index ccf6663865..0ac0033eff 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -7,10 +7,7 @@ #include #include -#define CROS_GPIO_NAME "INT34C5" -#define CROS_GPIO_COMM0_NAME "INT34C5:00" -#define CROS_GPIO_COMM1_NAME "INT34C5:01" -#define CROS_GPIO_COMM4_NAME "INT34C5:02" -#define CROS_GPIO_COMM5_NAME "INT34C5:03" + +#define CROS_GPIO_DEVICE_NAME "INT34C5:00" #endif From 02363b5e464e729366ca21421edcebad33f1237e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 5 May 2020 20:48:50 +0200 Subject: [PATCH 1426/1463] treewide: Move "is part of the coreboot project" line in its own comment That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/commonlib/include/commonlib/loglevel.h | 3 +-- src/commonlib/include/commonlib/sd_mmc_ctrlr.h | 3 +-- src/commonlib/include/commonlib/sdhci.h | 3 +-- src/commonlib/include/commonlib/storage.h | 3 +-- src/commonlib/storage/bouncebuf.c | 3 +-- src/commonlib/storage/bouncebuf.h | 3 +-- src/commonlib/storage/mmc.c | 3 +-- src/commonlib/storage/mmc.h | 3 +-- src/commonlib/storage/pci_sdhci.c | 3 +-- src/commonlib/storage/sd.c | 3 +-- src/commonlib/storage/sd_mmc.c | 3 +-- src/commonlib/storage/sd_mmc.h | 3 +-- src/commonlib/storage/sdhci.c | 3 +-- src/commonlib/storage/sdhci.h | 3 +-- src/commonlib/storage/sdhci_adma.c | 3 +-- src/commonlib/storage/sdhci_display.c | 3 +-- src/commonlib/storage/storage.c | 3 +-- src/commonlib/storage/storage.h | 3 +-- src/commonlib/storage/storage_erase.c | 3 +-- src/commonlib/storage/storage_write.c | 3 +-- src/cpu/amd/agesa/family15tn/udelay.c | 3 +-- src/cpu/amd/pi/00630F01/udelay.c | 3 +-- src/cpu/intel/slot_1/l2_cache.c | 3 +-- src/cpu/intel/slot_1/slot_1.c | 3 +-- src/cpu/qemu-power8/qemu.c | 3 +-- src/cpu/qemu-x86/qemu.c | 3 +-- src/cpu/ti/am335x/clock.h | 3 +-- src/cpu/ti/am335x/gpio.c | 3 +-- src/cpu/ti/am335x/gpio.h | 3 +-- src/cpu/ti/am335x/header.c | 3 +-- src/cpu/ti/am335x/header.h | 3 +-- src/cpu/ti/am335x/pinmux.c | 3 +-- src/cpu/ti/am335x/pinmux.h | 3 +-- src/cpu/ti/am335x/uart.c | 3 +-- src/cpu/ti/am335x/uart.h | 3 +-- src/cpu/x86/early_reset.S | 3 +-- src/cpu/x86/mtrr/mtrr.c | 3 +-- src/device/dram/ddr2.c | 3 +-- src/device/dram/ddr3.c | 3 +-- src/drivers/aspeed/common/aspeed_coreboot.h | 3 +-- src/drivers/aspeed/common/ast_drv.h | 3 +-- src/drivers/aspeed/common/ast_main.c | 3 +-- src/drivers/aspeed/common/ast_post.c | 3 +-- src/drivers/aspeed/common/ast_tables.h | 3 +-- src/drivers/dec/21143/21143.c | 3 +-- src/drivers/emulation/qemu/cirrus.c | 3 +-- src/drivers/i2c/adt7463/adt7463.c | 3 +-- src/drivers/i2c/tpm/cr50.c | 3 +-- src/drivers/i2c/tpm/tis.c | 3 +-- src/drivers/i2c/tpm/tis_atmel.c | 3 +-- src/drivers/i2c/tpm/tpm.c | 3 +-- src/drivers/i2c/tpm/tpm.h | 3 +-- src/drivers/i2c/ww_ring/ww_ring.c | 3 +-- src/drivers/i2c/ww_ring/ww_ring.h | 3 +-- src/drivers/i2c/ww_ring/ww_ring_programs.c | 3 +-- src/drivers/i2c/ww_ring/ww_ring_programs.h | 3 +-- src/drivers/intel/fsp1_1/temp_ram_exit.c | 3 +-- src/drivers/intel/fsp2_0/debug.c | 3 +-- src/drivers/intel/fsp2_0/graphics.c | 3 +-- src/drivers/intel/fsp2_0/hand_off_block.c | 3 +-- src/drivers/intel/fsp2_0/header_display.c | 3 +-- src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch | 3 +-- src/drivers/intel/fsp2_0/hob_display.c | 3 +-- src/drivers/intel/fsp2_0/hob_verify.c | 3 +-- src/drivers/intel/fsp2_0/include/fsp/api.h | 3 +-- src/drivers/intel/fsp2_0/include/fsp/debug.h | 3 +-- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 3 +-- src/drivers/intel/fsp2_0/include/fsp/upd.h | 3 +-- src/drivers/intel/fsp2_0/include/fsp/util.h | 3 +-- src/drivers/intel/fsp2_0/memory_init.c | 3 +-- src/drivers/intel/fsp2_0/notify.c | 3 +-- src/drivers/intel/fsp2_0/silicon_init.c | 3 +-- src/drivers/intel/fsp2_0/temp_ram_exit.c | 3 +-- src/drivers/intel/fsp2_0/upd_display.c | 3 +-- src/drivers/intel/fsp2_0/util.c | 3 +-- src/drivers/intel/gma/edid.c | 3 +-- src/drivers/intel/gma/opregion.c | 3 +-- src/drivers/intel/gma/opregion.h | 3 +-- src/drivers/intel/gma/vbt.c | 3 +-- src/drivers/intel/wifi/wifi.c | 3 +-- src/drivers/lenovo/lenovo.h | 3 +-- src/drivers/lenovo/wacom.c | 3 +-- src/drivers/maxim/max77686/max77686.c | 3 +-- src/drivers/maxim/max77686/max77686.h | 3 +-- src/drivers/maxim/max77802/max77802.h | 3 +-- src/drivers/pc80/pc/spkmodem.c | 3 +-- src/drivers/pc80/vga/vga.c | 3 +-- src/drivers/pc80/vga/vga_font_8x16.c | 3 +-- src/drivers/pc80/vga/vga_io.c | 3 +-- src/drivers/pc80/vga/vga_palette.c | 3 +-- src/drivers/spi/adesto.c | 3 +-- src/drivers/spi/amic.c | 3 +-- src/drivers/spi/atmel.c | 3 +-- src/drivers/spi/eon.c | 3 +-- src/drivers/spi/gigadevice.c | 3 +-- src/drivers/spi/macronix.c | 3 +-- src/drivers/spi/spansion.c | 3 +-- src/drivers/spi/spi-generic.c | 3 +-- src/drivers/spi/spi_flash.c | 3 +-- src/drivers/spi/spi_flash_internal.h | 3 +-- src/drivers/spi/sst.c | 3 +-- src/drivers/spi/stmicro.c | 3 +-- src/drivers/spi/winbond.c | 3 +-- src/drivers/uart/pl011.c | 3 +-- src/drivers/usb/ehci.h | 3 +-- src/drivers/wifi/generic.c | 3 +-- src/drivers/xgi/common/xgi_coreboot.h | 3 +-- src/include/console/post_codes.h | 3 +-- src/include/cpu/intel/l2_cache.h | 3 +-- src/include/device/dram/common.h | 3 +-- src/include/device/dram/ddr2.h | 3 +-- src/include/device/dram/ddr3.h | 3 +-- src/include/dimm_info_util.h | 3 +-- src/include/pc80/vga.h | 3 +-- src/include/pc80/vga_io.h | 3 +-- src/include/sdram_mode.h | 3 +-- src/include/spd.h | 3 +-- src/include/spi_bitbang.h | 3 +-- src/lib/rtc.c | 3 +-- src/mainboard/amd/padmelon/hda_verb.c | 3 +-- src/mainboard/apple/macbook21/hda_verb.c | 3 +-- src/mainboard/asrock/b75pro3-m/mainboard.c | 3 +-- src/mainboard/asrock/b85m_pro4/acpi/superio.asl | 3 +-- src/mainboard/asrock/g41c-gs/early_init.c | 3 +-- src/mainboard/asrock/g41c-gs/hda_verb.c | 3 +-- src/mainboard/asrock/h110m/mainboard.c | 3 +-- src/mainboard/asrock/h81m-hds/acpi/platform.asl | 3 +-- src/mainboard/asrock/h81m-hds/acpi/superio.asl | 3 +-- src/mainboard/asrock/h81m-hds/acpi_tables.c | 3 +-- src/mainboard/asrock/h81m-hds/dsdt.asl | 3 +-- src/mainboard/asrock/h81m-hds/gpio.c | 3 +-- src/mainboard/asrock/h81m-hds/hda_verb.c | 3 +-- src/mainboard/asrock/h81m-hds/mainboard.c | 3 +-- src/mainboard/asus/h61m-cs/acpi/platform.asl | 3 +-- src/mainboard/asus/h61m-cs/dsdt.asl | 3 +-- src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl | 3 +-- src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl | 3 +-- src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c | 3 +-- src/mainboard/asus/maximus_iv_gene-z/dsdt.asl | 3 +-- src/mainboard/asus/maximus_iv_gene-z/early_init.c | 3 +-- src/mainboard/asus/maximus_iv_gene-z/gpio.c | 3 +-- src/mainboard/asus/maximus_iv_gene-z/hda_verb.c | 3 +-- src/mainboard/asus/maximus_iv_gene-z/mainboard.c | 3 +-- src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c | 3 +-- src/mainboard/asus/p2b/variants/p2b-d/mptable.c | 3 +-- src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c | 3 +-- src/mainboard/asus/p2b/variants/p2b-ds/mptable.c | 3 +-- src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c | 3 +-- src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c | 3 +-- src/mainboard/asus/p2b/variants/p2b/irq_tables.c | 3 +-- src/mainboard/asus/p3b-f/irq_tables.c | 3 +-- src/mainboard/asus/p3b-f/romstage.c | 3 +-- src/mainboard/asus/p5qc/early_init.c | 3 +-- src/mainboard/asus/p5qc/hda_verb.c | 3 +-- src/mainboard/asus/p5ql-em/early_init.c | 3 +-- src/mainboard/asus/p5ql-em/hda_verb.c | 3 +-- src/mainboard/asus/p5qpl-am/early_init.c | 3 +-- src/mainboard/asus/p5qpl-am/hda_verb.c | 3 +-- src/mainboard/asus/p8h61-m_lx/acpi/platform.asl | 3 +-- src/mainboard/asus/p8h61-m_lx/acpi/superio.asl | 3 +-- src/mainboard/asus/p8h61-m_lx/acpi_tables.c | 3 +-- src/mainboard/asus/p8h61-m_lx/dsdt.asl | 3 +-- src/mainboard/asus/p8h61-m_lx/early_init.c | 3 +-- src/mainboard/asus/p8h61-m_lx/gpio.c | 3 +-- src/mainboard/asus/p8h61-m_lx/hda_verb.c | 3 +-- src/mainboard/asus/p8h61-m_lx/mainboard.c | 3 +-- src/mainboard/asus/p8h61-m_pro/acpi/superio.asl | 3 +-- src/mainboard/asus/p8z77-m_pro/acpi/platform.asl | 3 +-- src/mainboard/asus/p8z77-m_pro/acpi/superio.asl | 3 +-- src/mainboard/asus/p8z77-m_pro/acpi_tables.c | 3 +-- src/mainboard/biostar/am1ml/irq_tables.c | 3 +-- src/mainboard/emulation/qemu-armv7/mainboard.c | 3 +-- src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h | 3 +-- src/mainboard/foxconn/d41s/early_init.c | 3 +-- src/mainboard/foxconn/g41s-k/early_init.c | 3 +-- src/mainboard/foxconn/g41s-k/hda_verb.c | 3 +-- .../foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl | 3 +-- src/mainboard/gigabyte/ga-g41m-es2l/early_init.c | 3 +-- src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 3 +-- src/mainboard/google/cheza/board.h | 3 +-- src/mainboard/google/cheza/bootblock.c | 3 +-- src/mainboard/google/cheza/chromeos.c | 3 +-- src/mainboard/google/cheza/mainboard.c | 3 +-- src/mainboard/google/cheza/memlayout.ld | 3 +-- src/mainboard/google/cheza/romstage.c | 3 +-- .../google/kahlee/variants/careena/include/variant/sku.h | 3 +-- src/mainboard/google/kahlee/variants/careena/variant.c | 3 +-- src/mainboard/google/mistral/bootblock.c | 3 +-- src/mainboard/google/mistral/chromeos.c | 3 +-- src/mainboard/google/mistral/mainboard.c | 3 +-- src/mainboard/google/mistral/memlayout.ld | 3 +-- src/mainboard/google/mistral/romstage.c | 3 +-- src/mainboard/google/trogdor/board.h | 3 +-- src/mainboard/google/trogdor/bootblock.c | 3 +-- src/mainboard/google/trogdor/chromeos.c | 3 +-- src/mainboard/google/trogdor/mainboard.c | 3 +-- src/mainboard/google/trogdor/memlayout.ld | 3 +-- src/mainboard/google/trogdor/romstage.c | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/ec.c | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/ec.h | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/mainboard.h | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c | 3 +-- src/mainboard/intel/apollolake_rvp/dsdt.asl | 3 +-- src/mainboard/intel/apollolake_rvp/romstage.c | 3 +-- src/mainboard/intel/d510mo/early_init.c | 3 +-- src/mainboard/intel/dg41wv/early_init.c | 3 +-- src/mainboard/intel/dg41wv/hda_verb.c | 3 +-- src/mainboard/intel/dg43gt/early_init.c | 3 +-- src/mainboard/intel/dg43gt/hda_verb.c | 3 +-- src/mainboard/intel/harcuvar/romstage.c | 3 +-- src/mainboard/lenovo/g505s/acpi/ec.asl | 3 +-- src/mainboard/lenovo/g505s/acpi/superio.asl | 3 +-- src/mainboard/lenovo/g505s/ec.c | 3 +-- src/mainboard/lenovo/g505s/ec.h | 3 +-- src/mainboard/lenovo/g505s/mainboard.h | 3 +-- src/mainboard/lenovo/g505s/mainboard_smi.c | 3 +-- src/mainboard/lenovo/s230u/ec.h | 3 +-- src/mainboard/lenovo/t410/hda_verb.c | 3 +-- src/mainboard/lenovo/t440p/acpi/ec.asl | 3 +-- src/mainboard/lenovo/t440p/acpi/platform.asl | 3 +-- src/mainboard/lenovo/t440p/acpi/superio.asl | 3 +-- src/mainboard/lenovo/t440p/dsdt.asl | 3 +-- src/mainboard/lenovo/t440p/mainboard.c | 3 +-- src/mainboard/lenovo/thinkcentre_a58/early_init.c | 3 +-- src/mainboard/lenovo/thinkcentre_a58/hda_verb.c | 3 +-- src/mainboard/lenovo/x201/hda_verb.c | 3 +-- src/mainboard/msi/ms7707/acpi/platform.asl | 3 +-- src/mainboard/msi/ms7707/dsdt.asl | 3 +-- src/mainboard/ocp/tiogapass/acpi/platform.asl | 3 +-- src/mainboard/ocp/tiogapass/dsdt.asl | 3 +-- src/mainboard/ocp/tiogapass/fadt.c | 3 +-- src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h | 3 +-- src/mainboard/ocp/tiogapass/ramstage.c | 3 +-- src/mainboard/ocp/tiogapass/romstage.c | 3 +-- src/mainboard/packardbell/ms2290/hda_verb.c | 3 +-- src/mainboard/sapphire/pureplatinumh61/acpi_tables.c | 3 +-- src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 3 +-- src/mainboard/sapphire/pureplatinumh61/early_init.c | 3 +-- src/mainboard/sapphire/pureplatinumh61/gpio.c | 3 +-- src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 3 +-- src/mainboard/sapphire/pureplatinumh61/mainboard.c | 3 +-- src/mainboard/scaleway/tagada/romstage.c | 3 +-- src/mainboard/supermicro/x10slm-f/acpi/platform.asl | 3 +-- src/mainboard/supermicro/x10slm-f/acpi/superio.asl | 3 +-- src/mainboard/supermicro/x10slm-f/acpi_tables.c | 3 +-- src/mainboard/supermicro/x10slm-f/bootblock.c | 3 +-- src/mainboard/supermicro/x10slm-f/dsdt.asl | 3 +-- src/mainboard/supermicro/x10slm-f/gpio.c | 3 +-- src/mainboard/supermicro/x10slm-f/hda_verb.c | 3 +-- src/mainboard/supermicro/x10slm-f/mainboard.c | 3 +-- src/northbridge/intel/e7505/e7505.h | 3 +-- src/northbridge/intel/ironlake/raminit.c | 3 +-- src/northbridge/intel/ironlake/raminit_tables.c | 3 +-- src/northbridge/intel/ironlake/raminit_tables.h | 3 +-- src/northbridge/intel/pineview/early_init.c | 3 +-- src/northbridge/intel/pineview/iomap.h | 3 +-- src/northbridge/intel/pineview/pineview.h | 3 +-- src/northbridge/intel/pineview/raminit.c | 3 +-- src/northbridge/intel/pineview/raminit.h | 3 +-- src/northbridge/intel/x4x/bootblock.c | 3 +-- src/northbridge/intel/x4x/chip.h | 3 +-- src/northbridge/intel/x4x/dq_dqs.c | 3 +-- src/northbridge/intel/x4x/iomap.h | 3 +-- src/northbridge/intel/x4x/raminit.c | 3 +-- src/northbridge/intel/x4x/raminit_ddr23.c | 3 +-- src/northbridge/intel/x4x/raminit_tables.c | 3 +-- src/northbridge/intel/x4x/rcven.c | 3 +-- src/northbridge/intel/x4x/romstage.c | 3 +-- src/soc/intel/apollolake/acpi.c | 3 +-- src/soc/intel/apollolake/acpi/globalnvs.asl | 3 +-- src/soc/intel/apollolake/acpi/gpio.asl | 3 +-- src/soc/intel/apollolake/acpi/lpss.asl | 3 +-- src/soc/intel/apollolake/acpi/northbridge.asl | 3 +-- src/soc/intel/apollolake/acpi/pci_irqs.asl | 3 +-- src/soc/intel/apollolake/acpi/soc_int.asl | 3 +-- src/soc/intel/apollolake/acpi/southbridge.asl | 3 +-- src/soc/intel/apollolake/acpi/xhci_apl_ports.asl | 3 +-- src/soc/intel/apollolake/acpi/xhci_glk_ports.asl | 3 +-- src/soc/intel/apollolake/bootblock/bootblock.c | 3 +-- src/soc/intel/apollolake/car.c | 3 +-- src/soc/intel/apollolake/chip.c | 3 +-- src/soc/intel/apollolake/chip.h | 3 +-- src/soc/intel/apollolake/cpu.c | 3 +-- src/soc/intel/apollolake/fspcar.c | 3 +-- src/soc/intel/apollolake/gpio_apl.c | 3 +-- src/soc/intel/apollolake/gpio_glk.c | 3 +-- src/soc/intel/apollolake/graphics.c | 3 +-- src/soc/intel/apollolake/gspi.c | 3 +-- src/soc/intel/apollolake/heci.c | 3 +-- src/soc/intel/apollolake/include/soc/cpu.h | 3 +-- src/soc/intel/apollolake/include/soc/gpio.h | 3 +-- src/soc/intel/apollolake/include/soc/heci.h | 3 +-- src/soc/intel/apollolake/include/soc/iomap.h | 3 +-- src/soc/intel/apollolake/include/soc/nhlt.h | 3 +-- src/soc/intel/apollolake/include/soc/nvs.h | 3 +-- src/soc/intel/apollolake/include/soc/pci_devs.h | 3 +-- src/soc/intel/apollolake/include/soc/pm.h | 3 +-- src/soc/intel/apollolake/include/soc/ramstage.h | 3 +-- src/soc/intel/apollolake/include/soc/romstage.h | 3 +-- src/soc/intel/apollolake/include/soc/systemagent.h | 3 +-- src/soc/intel/apollolake/include/soc/usb.h | 3 +-- src/soc/intel/apollolake/lpc.c | 3 +-- src/soc/intel/apollolake/mmap_boot.c | 3 +-- src/soc/intel/apollolake/nhlt.c | 3 +-- src/soc/intel/apollolake/pmc.c | 3 +-- src/soc/intel/apollolake/pmutil.c | 3 +-- src/soc/intel/apollolake/romstage.c | 3 +-- src/soc/intel/apollolake/spi.c | 3 +-- src/soc/intel/apollolake/systemagent.c | 3 +-- src/soc/intel/apollolake/uart.c | 3 +-- src/soc/intel/cannonlake/acpi/gfx.asl | 3 +-- src/soc/intel/cannonlake/acpi/lpit.asl | 3 +-- src/soc/intel/cannonlake/acpi/pci_irqs.asl | 3 +-- src/soc/intel/cannonlake/acpi/southbridge.asl | 3 +-- src/soc/intel/cannonlake/gpio.c | 3 +-- src/soc/intel/cannonlake/gpio_cnp_h.c | 3 +-- src/soc/intel/cannonlake/gpio_common.c | 3 +-- src/soc/intel/cannonlake/graphics.c | 3 +-- src/soc/intel/cannonlake/gspi.c | 3 +-- src/soc/intel/cannonlake/include/soc/nhlt.h | 3 +-- src/soc/intel/cannonlake/nhlt.c | 3 +-- src/soc/intel/cannonlake/spi.c | 3 +-- src/soc/intel/common/block/acpi/acpi.c | 3 +-- src/soc/intel/common/block/acpi/acpi/northbridge.asl | 3 +-- src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 3 +-- src/soc/intel/common/block/gpio/gpio.c | 3 +-- src/soc/intel/common/block/graphics/graphics.c | 3 +-- src/soc/intel/common/block/gspi/gspi.c | 3 +-- src/soc/intel/common/block/include/intelblocks/acpi.h | 3 +-- src/soc/intel/common/block/include/intelblocks/cse.h | 3 +-- src/soc/intel/common/block/include/intelblocks/gpio.h | 3 +-- src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 3 +-- src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 3 +-- src/soc/intel/common/block/lpc/lpc.c | 3 +-- src/soc/intel/common/block/lpc/lpc_def.h | 3 +-- src/soc/intel/common/block/lpc/lpc_lib.c | 3 +-- src/soc/intel/common/block/spi/spi.c | 3 +-- src/soc/intel/common/block/sram/sram.c | 3 +-- src/soc/intel/common/reset.h | 3 +-- src/soc/intel/denverton_ns/bootblock/bootblock.c | 3 +-- src/soc/intel/denverton_ns/bootblock/uart.c | 3 +-- src/soc/intel/denverton_ns/chip.c | 3 +-- src/soc/intel/denverton_ns/cpu.c | 3 +-- src/soc/intel/denverton_ns/gpio.c | 3 +-- src/soc/intel/denverton_ns/hob_display.c | 3 +-- src/soc/intel/denverton_ns/include/soc/romstage.h | 3 +-- src/soc/intel/denverton_ns/memmap.c | 3 +-- src/soc/intel/denverton_ns/spi.c | 3 +-- src/soc/intel/denverton_ns/uart.c | 3 +-- src/soc/intel/denverton_ns/uart_debug.c | 3 +-- src/soc/intel/denverton_ns/upd_display.c | 3 +-- src/soc/intel/icelake/acpi/pci_irqs.asl | 3 +-- src/soc/intel/icelake/acpi/southbridge.asl | 3 +-- src/soc/intel/icelake/gpio.c | 3 +-- src/soc/intel/icelake/graphics.c | 3 +-- src/soc/intel/icelake/gspi.c | 3 +-- src/soc/intel/icelake/me.c | 3 +-- src/soc/intel/icelake/spi.c | 3 +-- src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl | 3 +-- src/soc/intel/jasperlake/acpi/pci_irqs.asl | 3 +-- src/soc/intel/jasperlake/acpi/southbridge.asl | 3 +-- src/soc/intel/jasperlake/gpio.c | 3 +-- src/soc/intel/jasperlake/graphics.c | 3 +-- src/soc/intel/jasperlake/gspi.c | 3 +-- src/soc/intel/jasperlake/spi.c | 3 +-- src/soc/intel/skylake/gspi.c | 3 +-- src/soc/intel/skylake/nhlt/da7219.c | 3 +-- src/soc/intel/skylake/spi.c | 3 +-- src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl | 3 +-- src/soc/intel/tigerlake/acpi/pci_irqs.asl | 3 +-- src/soc/intel/tigerlake/acpi/southbridge.asl | 3 +-- src/soc/intel/tigerlake/gpio.c | 3 +-- src/soc/intel/tigerlake/graphics.c | 3 +-- src/soc/intel/tigerlake/gspi.c | 3 +-- src/soc/intel/tigerlake/me.c | 3 +-- src/soc/intel/tigerlake/spi.c | 3 +-- src/soc/intel/xeon_sp/bootblock.c | 3 +-- src/soc/intel/xeon_sp/include/soc/iomap.h | 3 +-- src/soc/intel/xeon_sp/include/soc/pcr_ids.h | 3 +-- src/soc/intel/xeon_sp/include/soc/pm.h | 3 +-- src/soc/intel/xeon_sp/include/soc/pmc.h | 3 +-- src/soc/intel/xeon_sp/include/soc/romstage.h | 3 +-- src/soc/intel/xeon_sp/include/soc/util.h | 3 +-- src/soc/intel/xeon_sp/lpc.c | 3 +-- src/soc/intel/xeon_sp/reset.c | 3 +-- src/soc/intel/xeon_sp/romstage.c | 3 +-- src/soc/intel/xeon_sp/skx/acpi.c | 3 +-- src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl | 3 +-- src/soc/intel/xeon_sp/skx/acpi/iiostack.asl | 3 +-- src/soc/intel/xeon_sp/skx/acpi/uncore.asl | 3 +-- src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl | 3 +-- src/soc/intel/xeon_sp/skx/chip.c | 3 +-- src/soc/intel/xeon_sp/skx/chip.h | 3 +-- src/soc/intel/xeon_sp/skx/cpu.c | 3 +-- src/soc/intel/xeon_sp/skx/hob_display.c | 3 +-- src/soc/intel/xeon_sp/skx/include/soc/acpi.h | 3 +-- src/soc/intel/xeon_sp/skx/include/soc/cpu.h | 3 +-- src/soc/intel/xeon_sp/skx/include/soc/irq.h | 3 +-- src/soc/intel/xeon_sp/skx/include/soc/msr.h | 3 +-- src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h | 3 +-- src/soc/intel/xeon_sp/skx/include/soc/ramstage.h | 3 +-- src/soc/intel/xeon_sp/skx/soc_util.c | 3 +-- src/soc/intel/xeon_sp/skx/upd_display.c | 3 +-- src/soc/intel/xeon_sp/spi.c | 3 +-- src/soc/intel/xeon_sp/uncore.c | 3 +-- src/soc/nvidia/tegra124/include/soc/sor.h | 3 +-- src/soc/nvidia/tegra124/maincpu.S | 3 +-- src/soc/nvidia/tegra210/include/soc/sor.h | 3 +-- src/soc/qualcomm/common/include/soc/mmu_common.h | 3 +-- src/soc/qualcomm/common/include/soc/qclib_common.h | 3 +-- src/soc/qualcomm/common/include/soc/symbols_common.h | 3 +-- src/soc/qualcomm/common/mmu.c | 3 +-- src/soc/qualcomm/common/qclib.c | 3 +-- src/soc/qualcomm/ipq40xx/blsp.c | 3 +-- src/soc/qualcomm/ipq40xx/i2c.c | 3 +-- src/soc/qualcomm/ipq40xx/include/soc/qup.h | 3 +-- src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h | 3 +-- src/soc/qualcomm/ipq40xx/qup.c | 3 +-- src/soc/qualcomm/ipq806x/gsbi.c | 3 +-- src/soc/qualcomm/ipq806x/i2c.c | 3 +-- src/soc/qualcomm/ipq806x/include/soc/qup.h | 3 +-- src/soc/qualcomm/ipq806x/include/soc/usbl_if.h | 3 +-- src/soc/qualcomm/ipq806x/qup.c | 3 +-- src/soc/qualcomm/qcs405/blsp.c | 3 +-- src/soc/qualcomm/qcs405/bootblock.c | 3 +-- src/soc/qualcomm/qcs405/cbmem.c | 3 +-- src/soc/qualcomm/qcs405/i2c.c | 3 +-- src/soc/qualcomm/qcs405/include/soc/addressmap.h | 3 +-- src/soc/qualcomm/qcs405/include/soc/gpio.h | 3 +-- src/soc/qualcomm/qcs405/include/soc/memlayout.ld | 3 +-- src/soc/qualcomm/qcs405/include/soc/mmu.h | 3 +-- src/soc/qualcomm/qcs405/include/soc/qup.h | 3 +-- src/soc/qualcomm/qcs405/include/soc/symbols.h | 3 +-- src/soc/qualcomm/qcs405/include/soc/usb.h | 3 +-- src/soc/qualcomm/qcs405/mmu.c | 3 +-- src/soc/qualcomm/qcs405/qup.c | 3 +-- src/soc/qualcomm/qcs405/soc.c | 3 +-- src/soc/qualcomm/qcs405/timer.c | 3 +-- src/soc/qualcomm/qcs405/usb.c | 3 +-- src/soc/qualcomm/sc7180/aop_load_reset.c | 3 +-- src/soc/qualcomm/sc7180/bootblock.c | 3 +-- src/soc/qualcomm/sc7180/cbmem.c | 3 +-- src/soc/qualcomm/sc7180/clock.c | 3 +-- src/soc/qualcomm/sc7180/include/soc/addressmap.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/aop.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/clock.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/efuse.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/gpio.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/memlayout.ld | 3 +-- src/soc/qualcomm/sc7180/include/soc/mmu.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/qspi.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/symbols.h | 3 +-- src/soc/qualcomm/sc7180/include/soc/usb.h | 3 +-- src/soc/qualcomm/sc7180/mmu.c | 3 +-- src/soc/qualcomm/sc7180/qclib.c | 3 +-- src/soc/qualcomm/sc7180/qcom_qup_se.c | 3 +-- src/soc/qualcomm/sc7180/qspi.c | 3 +-- src/soc/qualcomm/sc7180/qupv3_spi.c | 3 +-- src/soc/qualcomm/sc7180/qupv3_uart.c | 3 +-- src/soc/qualcomm/sc7180/soc.c | 3 +-- src/soc/qualcomm/sc7180/spi.c | 3 +-- src/soc/qualcomm/sc7180/timer.c | 3 +-- src/soc/qualcomm/sc7180/uart_bitbang.c | 3 +-- src/soc/qualcomm/sc7180/usb.c | 3 +-- src/soc/qualcomm/sdm845/aop_load_reset.c | 3 +-- src/soc/qualcomm/sdm845/bootblock.c | 3 +-- src/soc/qualcomm/sdm845/cbmem.c | 3 +-- src/soc/qualcomm/sdm845/clock.c | 3 +-- src/soc/qualcomm/sdm845/include/soc/addressmap.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/aop.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/clock.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/efuse.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/gpio.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/memlayout.ld | 3 +-- src/soc/qualcomm/sdm845/include/soc/mmu.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/qspi.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/symbols.h | 3 +-- src/soc/qualcomm/sdm845/include/soc/usb.h | 3 +-- src/soc/qualcomm/sdm845/mmu.c | 3 +-- src/soc/qualcomm/sdm845/qclib.c | 3 +-- src/soc/qualcomm/sdm845/qspi.c | 3 +-- src/soc/qualcomm/sdm845/soc.c | 3 +-- src/soc/qualcomm/sdm845/spi.c | 3 +-- src/soc/qualcomm/sdm845/timer.c | 3 +-- src/soc/qualcomm/sdm845/uart_bitbang.c | 3 +-- src/soc/qualcomm/sdm845/usb.c | 3 +-- src/soc/rockchip/rk3288/hdmi.c | 3 +-- src/soc/rockchip/rk3288/include/soc/hdmi.h | 3 +-- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 3 +-- src/southbridge/amd/agesa/hudson/smi.c | 3 +-- src/southbridge/amd/agesa/hudson/smi.h | 3 +-- src/southbridge/amd/agesa/hudson/smi_util.c | 3 +-- src/southbridge/amd/agesa/hudson/smihandler.c | 3 +-- src/southbridge/amd/pi/hudson/smi.c | 3 +-- src/southbridge/amd/pi/hudson/smi.h | 3 +-- src/southbridge/amd/pi/hudson/smi_util.c | 3 +-- src/southbridge/amd/pi/hudson/smihandler.c | 3 +-- src/southbridge/intel/common/finalize.h | 3 +-- src/southbridge/intel/i82371eb/bootblock.c | 3 +-- src/southbridge/intel/i82371eb/chip.h | 3 +-- src/southbridge/intel/i82371eb/early_pm.c | 3 +-- src/southbridge/intel/i82371eb/early_smbus.c | 3 +-- src/southbridge/intel/i82371eb/fadt.c | 3 +-- src/southbridge/intel/i82371eb/i82371eb.c | 3 +-- src/southbridge/intel/i82371eb/i82371eb.h | 3 +-- src/southbridge/intel/i82371eb/ide.c | 3 +-- src/southbridge/intel/i82371eb/isa.c | 3 +-- src/southbridge/intel/i82371eb/smbus.c | 3 +-- src/southbridge/intel/i82371eb/usb.c | 3 +-- src/southbridge/intel/i82371eb/wakeup.c | 3 +-- src/southbridge/intel/i82801gx/sata.h | 3 +-- src/southbridge/intel/ibexpeak/early_thermal.c | 3 +-- src/southbridge/ricoh/rl5c476/rl5c476.c | 3 +-- src/southbridge/ricoh/rl5c476/rl5c476.h | 3 +-- src/southbridge/ti/pci1x2x/pci1x2x.c | 3 +-- src/southbridge/ti/pci7420/cardbus.c | 3 +-- src/southbridge/ti/pci7420/chip.h | 3 +-- src/southbridge/ti/pci7420/firewire.c | 3 +-- src/southbridge/ti/pci7420/pci7420.h | 3 +-- util/amdfwtool/amdfwtool.c | 3 +-- util/cbfstool/coff.h | 3 +-- util/cbfstool/console/console.h | 3 +-- util/cbfstool/fv.h | 3 +-- util/cbmem/cbmem.c | 3 +-- util/fuzz-tests/jpeg-test.c | 3 +-- util/intelmetool/me.c | 3 +-- util/intelmetool/me.h | 3 +-- util/intelmetool/me_status.c | 3 +-- util/kbc1126/kbc1126_ec_dump.c | 3 +-- util/kbc1126/kbc1126_ec_insert.c | 3 +-- .../google/hatch/template/include/variant/acpi/dptf.asl | 3 +-- util/mainboard/google/hatch/template/include/variant/ec.h | 3 +-- util/mainboard/google/hatch/template/include/variant/gpio.h | 3 +-- util/nvramtool/cbfs.c | 3 +-- util/nvramtool/cbfs.h | 3 +-- util/pmh7tool/pmh7tool.c | 3 +-- util/pmh7tool/pmh7tool.h | 3 +-- util/supermicro/smcbiosinfo/smcbiosinfo.c | 3 +-- util/vgabios/include/arch/byteorder.h | 3 +-- util/vgabios/include/console/console.h | 3 +-- util/vgabios/include/stdtypes.h | 3 +-- util/vgabios/include/swab.h | 3 +-- util/vgabios/pci-userspace.c | 3 +-- util/vgabios/pci-userspace.h | 3 +-- util/vgabios/testbios.c | 3 +-- util/vgabios/testbios.h | 3 +-- util/x86/x86_page_tables.go | 3 +-- 550 files changed, 550 insertions(+), 1100 deletions(-) diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h index 7a1654179d..30209092fd 100644 --- a/src/commonlib/include/commonlib/loglevel.h +++ b/src/commonlib/include/commonlib/loglevel.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h index d4a7d54ff5..0807d2e2c5 100644 --- a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h +++ b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/include/commonlib/sdhci.h b/src/commonlib/include/commonlib/sdhci.h index 015fd0c6f9..126ef0176b 100644 --- a/src/commonlib/include/commonlib/sdhci.h +++ b/src/commonlib/include/commonlib/sdhci.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/include/commonlib/storage.h b/src/commonlib/include/commonlib/storage.h index faba2fe5a9..ce5f93acaa 100644 --- a/src/commonlib/include/commonlib/storage.h +++ b/src/commonlib/include/commonlib/storage.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 99287b6270..6bc5cf4103 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h index 3e702fad29..6a2e759614 100644 --- a/src/commonlib/storage/bouncebuf.h +++ b/src/commonlib/storage/bouncebuf.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index 8eaa2ee611..6346c432ba 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/mmc.h b/src/commonlib/storage/mmc.h index 2441d5d7e8..621c5414b1 100644 --- a/src/commonlib/storage/mmc.h +++ b/src/commonlib/storage/mmc.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index 380f2db557..fbc73a8825 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 30af81088d..1b4bee0b47 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index c5fa76c730..c8df33595a 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/sd_mmc.h b/src/commonlib/storage/sd_mmc.h index b1ae0f3f06..9ad2a9e52a 100644 --- a/src/commonlib/storage/sd_mmc.h +++ b/src/commonlib/storage/sd_mmc.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 246b9b9d2d..47286c54d2 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/sdhci.h b/src/commonlib/storage/sdhci.h index c745b8cc09..ff0af13f19 100644 --- a/src/commonlib/storage/sdhci.h +++ b/src/commonlib/storage/sdhci.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 2ca4b5557c..843497116c 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/sdhci_display.c b/src/commonlib/storage/sdhci_display.c index 1bb0bcf8d8..4169f7ec98 100644 --- a/src/commonlib/storage/sdhci_display.c +++ b/src/commonlib/storage/sdhci_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index df040cae21..8f5a72f248 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/storage.h b/src/commonlib/storage/storage.h index f03ed554fc..67e21a40af 100644 --- a/src/commonlib/storage/storage.h +++ b/src/commonlib/storage/storage.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/storage_erase.c b/src/commonlib/storage/storage_erase.c index a8da366438..b01388077e 100644 --- a/src/commonlib/storage/storage_erase.c +++ b/src/commonlib/storage/storage_erase.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/commonlib/storage/storage_write.c b/src/commonlib/storage/storage_write.c index ec19dd2182..edf13fc0a3 100644 --- a/src/commonlib/storage/storage_write.c +++ b/src/commonlib/storage/storage_write.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c index 898f6c1fef..f168356531 100644 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ b/src/cpu/amd/agesa/family15tn/udelay.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c index d4bf45f7d2..c70a8c180e 100644 --- a/src/cpu/amd/pi/00630F01/udelay.c +++ b/src/cpu/amd/pi/00630F01/udelay.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License or (at your option) diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 2602527d5f..ab783760a3 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c index 9a03f6bf68..e95b722172 100644 --- a/src/cpu/intel/slot_1/slot_1.c +++ b/src/cpu/intel/slot_1/slot_1.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/qemu-power8/qemu.c b/src/cpu/qemu-power8/qemu.c index 826624a386..e617b86785 100644 --- a/src/cpu/qemu-power8/qemu.c +++ b/src/cpu/qemu-power8/qemu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index f250698c89..12b7c7911b 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/ti/am335x/clock.h b/src/cpu/ti/am335x/clock.h index 4a2b4018e8..f43fbe2447 100644 --- a/src/cpu/ti/am335x/clock.h +++ b/src/cpu/ti/am335x/clock.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c index 5e3b62a34f..5906a98d5d 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/cpu/ti/am335x/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h index b6e2a997dc..84df942db4 100644 --- a/src/cpu/ti/am335x/gpio.h +++ b/src/cpu/ti/am335x/gpio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index bef1e5607f..80cb88f134 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/ti/am335x/header.h b/src/cpu/ti/am335x/header.h index 9b40f4b7ce..814b27383f 100644 --- a/src/cpu/ti/am335x/header.h +++ b/src/cpu/ti/am335x/header.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c index 58e0fffb51..e1cc41980c 100644 --- a/src/cpu/ti/am335x/pinmux.c +++ b/src/cpu/ti/am335x/pinmux.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index 714ba22c19..94f189f370 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 24aa7df53b..e7e9141ff9 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index 3ad84dc6a2..686040f29a 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index ec015abe22..93c1b49e4c 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index b26e31a1d4..2698708516 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 5319806ae6..12200f7f08 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index bef3c78497..7eaf960285 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h index d3b6981708..72ef4e7ae7 100644 --- a/src/drivers/aspeed/common/aspeed_coreboot.h +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index eb52da0783..c71637fb1b 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index d84678d05a..7a99afb504 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index d9c2d2db27..6842ba7d52 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 9b91b2b981..1b1158c442 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index ff64cf3490..d718597696 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 4f03578438..a58d7610bd 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 2fcd54e647..199b6a829a 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 3d9ca593e4..72431e2fd5 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation, version 2 of the diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 8b07bb78dd..de4116774d 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 74b4830b6a..82f21ca800 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 009227eb36..2917b45cb9 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation, version 2 of the diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h index 2d7c3855c0..c1ed3f0afb 100644 --- a/src/drivers/i2c/tpm/tpm.h +++ b/src/drivers/i2c/tpm/tpm.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation, version 2 of the diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index 9957584d28..a7b20bf24f 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/drivers/i2c/ww_ring/ww_ring.h b/src/drivers/i2c/ww_ring/ww_ring.h index a3c3372c1c..f17f5e39b8 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.h +++ b/src/drivers/i2c/ww_ring/ww_ring.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index e739f9851a..2283fb94dd 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 02c2e9bcd8..ea0e241f5c 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/drivers/intel/fsp1_1/temp_ram_exit.c b/src/drivers/intel/fsp1_1/temp_ram_exit.c index eff157bc0e..12fdff8172 100644 --- a/src/drivers/intel/fsp1_1/temp_ram_exit.c +++ b/src/drivers/intel/fsp1_1/temp_ram_exit.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 5fc3b6fc16..e7a163f315 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index be7afdb084..d05b09f7f2 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 3978a1848b..183487ddd6 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index 926b2ae540..abb99c1c5c 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch index dd8f05f935..502db14189 100644 --- a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index ce6937d123..69eaed2aa4 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index bdfb64d81a..36a4eea16c 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 60adb98513..239d387f5d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index fa859556b6..0409bbfc27 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index fd09f41305..3b737309de 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 46a930d2f8..34c3d958a3 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 303bafe458..c8dfd8e6d5 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index ad95dce12a..5af3842095 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index dea3de5313..d18d7378b0 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 33d15afad6..07b202468b 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index a2171b07ca..c4f60b113c 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index 6ac52dd8b8..4afc7f9f87 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 5239f9be94..1d845be374 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index ca3ab322b6..796f4df4dd 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your option) diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index cd42337d07..bc1b296c16 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your option) diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 496769134b..dd1beabb98 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 603044a4c8..a4b1c289a7 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 or (at your option) diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index ffbab4de79..dffb207129 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 or (at your option) diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index cf8c71f13f..390df3706f 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 1da5ddc989..5a07d27ed7 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index cfbf912937..5b24187c6e 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h index a5f46b3bf8..74e03f8230 100644 --- a/src/drivers/maxim/max77686/max77686.h +++ b/src/drivers/maxim/max77686/max77686.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/maxim/max77802/max77802.h b/src/drivers/maxim/max77802/max77802.h index a19d85f197..85e385e7bf 100644 --- a/src/drivers/maxim/max77802/max77802.h +++ b/src/drivers/maxim/max77802/max77802.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/pc80/pc/spkmodem.c b/src/drivers/pc80/pc/spkmodem.c index d7db44c475..4dd5972c4b 100644 --- a/src/drivers/pc80/pc/spkmodem.c +++ b/src/drivers/pc80/pc/spkmodem.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index 6d0b674833..20e148b55d 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free * Software Foundation; either version 2 of the License, or (at your option) diff --git a/src/drivers/pc80/vga/vga_font_8x16.c b/src/drivers/pc80/vga/vga_font_8x16.c index b267c4a59f..2d8e2ca581 100644 --- a/src/drivers/pc80/vga/vga_font_8x16.c +++ b/src/drivers/pc80/vga/vga_font_8x16.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free * Software Foundation; either version 2 of the License, or (at your option) diff --git a/src/drivers/pc80/vga/vga_io.c b/src/drivers/pc80/vga/vga_io.c index 842419e0fd..3d76df1512 100644 --- a/src/drivers/pc80/vga/vga_io.c +++ b/src/drivers/pc80/vga/vga_io.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free * Software Foundation; either version 2 of the License, or (at your option) diff --git a/src/drivers/pc80/vga/vga_palette.c b/src/drivers/pc80/vga/vga_palette.c index 748a7c9159..2e58a55a9f 100644 --- a/src/drivers/pc80/vga/vga_palette.c +++ b/src/drivers/pc80/vga/vga_palette.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index fe4106afd0..eb09fe52e4 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index cb4ada01ce..b0198b3a48 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 491a7ab04e..6feda6ecc3 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 706115a18c..f5923c3354 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 717b01613f..ccc8eba72f 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 0c5bf14814..12f8679e97 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 29b7027b65..9d5f559e92 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index bc4fb086cd..4ce29ed33d 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 51498296d6..eb19860c76 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 0842961be7..e5884a474e 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 4b25b902f1..f48d107a15 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index e867d71450..464d366fa0 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 9029dc442d..b146984bb5 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index d2c7c4b597..682a334889 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index efda0a22b5..d2129016ce 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index ca16686ce6..e4b6f330e8 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 or (at your option) diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index a850087260..bfc5dd594e 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index a9094929c6..416d487eef 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 74d5acc64a..c253f880da 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index 5dc15e3e4c..32cdc79de1 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 1da9681169..f83965971b 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 51207e9999..2ded8a8fdb 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/dimm_info_util.h b/src/include/dimm_info_util.h index d6603ed60f..48fff6ceb2 100644 --- a/src/include/dimm_info_util.h +++ b/src/include/dimm_info_util.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License version diff --git a/src/include/pc80/vga.h b/src/include/pc80/vga.h index 0e3d5f5895..ea47368936 100644 --- a/src/include/pc80/vga.h +++ b/src/include/pc80/vga.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/pc80/vga_io.h b/src/include/pc80/vga_io.h index 1f258c4f15..3cfba1b2fb 100644 --- a/src/include/pc80/vga_io.h +++ b/src/include/pc80/vga_io.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/sdram_mode.h b/src/include/sdram_mode.h index 763dd562b3..5dadaee3a0 100644 --- a/src/include/sdram_mode.h +++ b/src/include/sdram_mode.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/spd.h b/src/include/spd.h index 80d14c1685..cacb20517c 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/spi_bitbang.h b/src/include/spi_bitbang.h index ac6924e223..4691fd21ec 100644 --- a/src/include/spi_bitbang.h +++ b/src/include/spi_bitbang.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/src/lib/rtc.c b/src/lib/rtc.c index 8a807cef82..018897b505 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/amd/padmelon/hda_verb.c b/src/mainboard/amd/padmelon/hda_verb.c index b4d80beaa5..4e1418c0a6 100644 --- a/src/mainboard/amd/padmelon/hda_verb.c +++ b/src/mainboard/amd/padmelon/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index 76bae0c1a3..cfd6e0bef3 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/b75pro3-m/mainboard.c b/src/mainboard/asrock/b75pro3-m/mainboard.c index a3d8b3409a..ef929669f3 100644 --- a/src/mainboard/asrock/b75pro3-m/mainboard.c +++ b/src/mainboard/asrock/b75pro3-m/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl index b671e3cb37..37926305a2 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2018 Tristan Corrick * * This program is free software: you can redistribute it and/or modify diff --git a/src/mainboard/asrock/g41c-gs/early_init.c b/src/mainboard/asrock/g41c-gs/early_init.c index d35bb5dcc2..88fe3fb090 100644 --- a/src/mainboard/asrock/g41c-gs/early_init.c +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c index 11fd3edf80..661f6c45ef 100644 --- a/src/mainboard/asrock/g41c-gs/hda_verb.c +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asrock/h110m/mainboard.c b/src/mainboard/asrock/h110m/mainboard.c index 01f0575226..01b70e0fad 100644 --- a/src/mainboard/asrock/h110m/mainboard.c +++ b/src/mainboard/asrock/h110m/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/acpi/platform.asl b/src/mainboard/asrock/h81m-hds/acpi/platform.asl index 26a10c57b4..81591d6ece 100644 --- a/src/mainboard/asrock/h81m-hds/acpi/platform.asl +++ b/src/mainboard/asrock/h81m-hds/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/acpi/superio.asl b/src/mainboard/asrock/h81m-hds/acpi/superio.asl index 25a0c5cbfa..43ab19a9e1 100644 --- a/src/mainboard/asrock/h81m-hds/acpi/superio.asl +++ b/src/mainboard/asrock/h81m-hds/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c index 54796d54eb..4c600616b4 100644 --- a/src/mainboard/asrock/h81m-hds/acpi_tables.c +++ b/src/mainboard/asrock/h81m-hds/acpi_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 3e7d798855..9e40cfc043 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/gpio.c b/src/mainboard/asrock/h81m-hds/gpio.c index 4474f79d92..6610ab1dfa 100644 --- a/src/mainboard/asrock/h81m-hds/gpio.c +++ b/src/mainboard/asrock/h81m-hds/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/hda_verb.c b/src/mainboard/asrock/h81m-hds/hda_verb.c index 9de7845a95..a07ca8c5dc 100644 --- a/src/mainboard/asrock/h81m-hds/hda_verb.c +++ b/src/mainboard/asrock/h81m-hds/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asrock/h81m-hds/mainboard.c b/src/mainboard/asrock/h81m-hds/mainboard.c index 01f0575226..01b70e0fad 100644 --- a/src/mainboard/asrock/h81m-hds/mainboard.c +++ b/src/mainboard/asrock/h81m-hds/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/acpi/platform.asl b/src/mainboard/asus/h61m-cs/acpi/platform.asl index d356d9b52b..89f8f7362a 100644 --- a/src/mainboard/asus/h61m-cs/acpi/platform.asl +++ b/src/mainboard/asus/h61m-cs/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 28cf2fed82..b8e4df30f3 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl index 26a10c57b4..81591d6ece 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl index bef9a0325e..a6fe5a788c 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c index 9c02dd5485..f97249d9e4 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index 8708809fee..eec65b8bf5 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index f5757c9482..aae5ee60e3 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/gpio.c b/src/mainboard/asus/maximus_iv_gene-z/gpio.c index b0dcee2942..4b8462ddad 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/gpio.c +++ b/src/mainboard/asus/maximus_iv_gene-z/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c index 9859c8d86f..0fd8d7862d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c +++ b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/maximus_iv_gene-z/mainboard.c b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c index 01f0575226..01b70e0fad 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/mainboard.c +++ b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c index 0bc944060f..8822035ce2 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c index 6c238f1da2..2c7ac6023e 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c index 2da3346988..84cd1373a0 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c index a180194b30..0c09233e87 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c index 368c0e56e7..eab90868f5 100644 --- a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c index b7536eb397..d4b9272d68 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c index 4601f0850e..d0360d9c90 100644 --- a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index 483b4eecde..5c10ec4be8 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e3a78978c0..56f5253905 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/early_init.c b/src/mainboard/asus/p5qc/early_init.c index 6a7ac89e00..5b0539d4a2 100644 --- a/src/mainboard/asus/p5qc/early_init.c +++ b/src/mainboard/asus/p5qc/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c index 8a56a75973..b7607499b0 100644 --- a/src/mainboard/asus/p5qc/hda_verb.c +++ b/src/mainboard/asus/p5qc/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p5ql-em/early_init.c b/src/mainboard/asus/p5ql-em/early_init.c index 38038012f7..4585a98456 100644 --- a/src/mainboard/asus/p5ql-em/early_init.c +++ b/src/mainboard/asus/p5ql-em/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c index 3be50bb3b2..8dbf431f13 100644 --- a/src/mainboard/asus/p5ql-em/hda_verb.c +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/mainboard/asus/p5qpl-am/early_init.c b/src/mainboard/asus/p5qpl-am/early_init.c index afcd531ed4..5556536e6b 100644 --- a/src/mainboard/asus/p5qpl-am/early_init.c +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c index 76b249b2ba..cca113c8a9 100644 --- a/src/mainboard/asus/p5qpl-am/hda_verb.c +++ b/src/mainboard/asus/p5qpl-am/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl index 26a10c57b4..81591d6ece 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl +++ b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl index 25a0c5cbfa..43ab19a9e1 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl +++ b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c index 9c02dd5485..f97249d9e4 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index 8708809fee..eec65b8bf5 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/early_init.c b/src/mainboard/asus/p8h61-m_lx/early_init.c index 0d4f227e5a..4021781d10 100644 --- a/src/mainboard/asus/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/p8h61-m_lx/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/gpio.c b/src/mainboard/asus/p8h61-m_lx/gpio.c index 3b46845764..e02359f1d2 100644 --- a/src/mainboard/asus/p8h61-m_lx/gpio.c +++ b/src/mainboard/asus/p8h61-m_lx/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/p8h61-m_lx/hda_verb.c index 17e2e8d9b5..417ae1b720 100644 --- a/src/mainboard/asus/p8h61-m_lx/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_lx/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_lx/mainboard.c b/src/mainboard/asus/p8h61-m_lx/mainboard.c index 01f0575226..01b70e0fad 100644 --- a/src/mainboard/asus/p8h61-m_lx/mainboard.c +++ b/src/mainboard/asus/p8h61-m_lx/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl b/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl index bef9a0325e..a6fe5a788c 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl +++ b/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl index d356d9b52b..89f8f7362a 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl +++ b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl index bef9a0325e..a6fe5a788c 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl +++ b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c index da96b49f40..3f69f12f9a 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c index 0044ab7bd0..b4f09f971a 100644 --- a/src/mainboard/biostar/am1ml/irq_tables.c +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index d3e14c1fb0..b7d339725b 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index dad6ca9e7f..d089898f5d 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License, or (at your diff --git a/src/mainboard/foxconn/d41s/early_init.c b/src/mainboard/foxconn/d41s/early_init.c index e37cc82265..c31860db80 100644 --- a/src/mainboard/foxconn/d41s/early_init.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/early_init.c b/src/mainboard/foxconn/g41s-k/early_init.c index c2d7c1b331..731f622dc7 100644 --- a/src/mainboard/foxconn/g41s-k/early_init.c +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c index f92d75164c..98bce49e6b 100644 --- a/src/mainboard/foxconn/g41s-k/hda_verb.c +++ b/src/mainboard/foxconn/g41s-k/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl index b5d41b2e67..ac6fcbe3f6 100644 --- a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index 53652e70cc..476a1aa7a4 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c index ad0642b965..bea28ed05a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h index bf53a44c03..528096f59e 100644 --- a/src/mainboard/google/cheza/board.h +++ b/src/mainboard/google/cheza/board.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c index 05da53ed6c..b6f99126c1 100644 --- a/src/mainboard/google/cheza/bootblock.c +++ b/src/mainboard/google/cheza/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 4abe1f13de..227370cbdd 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 1e46167c90..1e3803443e 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld index 9f22755be0..6bb1739fe6 100644 --- a/src/mainboard/google/cheza/memlayout.ld +++ b/src/mainboard/google/cheza/memlayout.ld @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index fd54e9e186..bcb65d5d08 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/sku.h b/src/mainboard/google/kahlee/variants/careena/include/variant/sku.h index a31c99eba2..bbe3eaaab4 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/sku.h +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/sku.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/google/kahlee/variants/careena/variant.c b/src/mainboard/google/kahlee/variants/careena/variant.c index d35ec488df..7eda9337ba 100644 --- a/src/mainboard/google/kahlee/variants/careena/variant.c +++ b/src/mainboard/google/kahlee/variants/careena/variant.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright 2020 Google LLC * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index d4446864b2..bbf5d68a99 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index c92be26fdb..34354ae05f 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 13c9cb27e1..63095dede3 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/memlayout.ld b/src/mainboard/google/mistral/memlayout.ld index 174ae545fa..6cd2717891 100644 --- a/src/mainboard/google/mistral/memlayout.ld +++ b/src/mainboard/google/mistral/memlayout.ld @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index ccba032223..1dc7c6c14c 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index acaf02288c..aef11d603a 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c index 05da53ed6c..b6f99126c1 100644 --- a/src/mainboard/google/trogdor/bootblock.c +++ b/src/mainboard/google/trogdor/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 4abe1f13de..227370cbdd 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index a2cee53fc5..61fb19093e 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/memlayout.ld b/src/mainboard/google/trogdor/memlayout.ld index 174ae545fa..6cd2717891 100644 --- a/src/mainboard/google/trogdor/memlayout.ld +++ b/src/mainboard/google/trogdor/memlayout.ld @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 1e87c4d305..226546ad68 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl index d49c26b118..3dc2ef2cdd 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.c b/src/mainboard/hp/pavilion_m6_1035dx/ec.c index d5928aa258..3dd7f9aad3 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 6a375bfb06..aab96f4cd1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h index 8b55c50665..6ff3c1e225 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index a0c35a33e9..0e23b1db70 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 05fdd237b9..648e9f9e05 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index ce38130106..7d625c15de 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/d510mo/early_init.c b/src/mainboard/intel/d510mo/early_init.c index 68e1141abc..29f00b35de 100644 --- a/src/mainboard/intel/d510mo/early_init.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/early_init.c b/src/mainboard/intel/dg41wv/early_init.c index 584b936eca..035ad9b435 100644 --- a/src/mainboard/intel/dg41wv/early_init.c +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg41wv/hda_verb.c b/src/mainboard/intel/dg41wv/hda_verb.c index b4d80beaa5..4e1418c0a6 100644 --- a/src/mainboard/intel/dg41wv/hda_verb.c +++ b/src/mainboard/intel/dg41wv/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/dg43gt/early_init.c b/src/mainboard/intel/dg43gt/early_init.c index 3c1c7d178a..fbec787342 100644 --- a/src/mainboard/intel/dg43gt/early_init.c +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/intel/dg43gt/hda_verb.c b/src/mainboard/intel/dg43gt/hda_verb.c index fbc3eebf93..a7bd2799ba 100644 --- a/src/mainboard/intel/dg43gt/hda_verb.c +++ b/src/mainboard/intel/dg43gt/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index 542f81e005..4331805749 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/ec.asl b/src/mainboard/lenovo/g505s/acpi/ec.asl index d49c26b118..3dc2ef2cdd 100644 --- a/src/mainboard/lenovo/g505s/acpi/ec.asl +++ b/src/mainboard/lenovo/g505s/acpi/ec.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl index e5182fc4c8..85a0894fdd 100644 --- a/src/mainboard/lenovo/g505s/acpi/superio.asl +++ b/src/mainboard/lenovo/g505s/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/ec.c b/src/mainboard/lenovo/g505s/ec.c index 8471167c5a..9ddccb839d 100644 --- a/src/mainboard/lenovo/g505s/ec.c +++ b/src/mainboard/lenovo/g505s/ec.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index 2826494353..f615fccf69 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h index 06abb1151b..02ddb279c6 100644 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/mainboard_smi.c index a0c35a33e9..0e23b1db70 100644 --- a/src/mainboard/lenovo/g505s/mainboard_smi.c +++ b/src/mainboard/lenovo/g505s/mainboard_smi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index ddb4280786..836b2d8234 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 523ff73599..828a13ff41 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t440p/acpi/ec.asl b/src/mainboard/lenovo/t440p/acpi/ec.asl index e3a00aac2c..3dbe6fe882 100644 --- a/src/mainboard/lenovo/t440p/acpi/ec.asl +++ b/src/mainboard/lenovo/t440p/acpi/ec.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/acpi/platform.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl index 567d302031..a2c2e002f9 100644 --- a/src/mainboard/lenovo/t440p/acpi/platform.asl +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/acpi/superio.asl b/src/mainboard/lenovo/t440p/acpi/superio.asl index bef9a0325e..a6fe5a788c 100644 --- a/src/mainboard/lenovo/t440p/acpi/superio.asl +++ b/src/mainboard/lenovo/t440p/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 04fd79392f..718cad1dab 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t440p/mainboard.c b/src/mainboard/lenovo/t440p/mainboard.c index 6f3b5b89d9..31552b8407 100644 --- a/src/mainboard/lenovo/t440p/mainboard.c +++ b/src/mainboard/lenovo/t440p/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/early_init.c b/src/mainboard/lenovo/thinkcentre_a58/early_init.c index 483e22a666..70d70f7880 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/early_init.c +++ b/src/mainboard/lenovo/thinkcentre_a58/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c index 57c632457b..6074f5f350 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c +++ b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c index d521321e24..fa01ebf8e8 100644 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ b/src/mainboard/lenovo/x201/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/msi/ms7707/acpi/platform.asl b/src/mainboard/msi/ms7707/acpi/platform.asl index d356d9b52b..89f8f7362a 100644 --- a/src/mainboard/msi/ms7707/acpi/platform.asl +++ b/src/mainboard/msi/ms7707/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index e46f606b6a..7432de8311 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl index a10c4068f7..312ae70ff8 100644 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 717597c379..fe52ea1e9b 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c index f6fb273747..1036b02008 100644 --- a/src/mainboard/ocp/tiogapass/fadt.c +++ b/src/mainboard/ocp/tiogapass/fadt.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h index d436e885a4..b43260fc27 100644 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 16b4fd92e3..27d2a17509 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index dcd198de70..3af6a2e9ed 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/packardbell/ms2290/hda_verb.c b/src/mainboard/packardbell/ms2290/hda_verb.c index 68646d7661..8121f874cb 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.c +++ b/src/mainboard/packardbell/ms2290/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c index f8bbf887d3..436930a83b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 109e37204c..9e704c870f 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index a13e580b4c..39ca7e781a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c index 33dd607a45..c4d456d308 100644 --- a/src/mainboard/sapphire/pureplatinumh61/gpio.c +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c index f0ed031328..c0467950f6 100644 --- a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c index e142ee20ea..290c55fb25 100644 --- a/src/mainboard/sapphire/pureplatinumh61/mainboard.c +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c index 5d024c8780..c02a7b9bb9 100644 --- a/src/mainboard/scaleway/tagada/romstage.c +++ b/src/mainboard/scaleway/tagada/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl index 26a10c57b4..81591d6ece 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl +++ b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl index 3f2ac82c92..0c9f46b78c 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl +++ b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c index 54796d54eb..4c600616b4 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi_tables.c +++ b/src/mainboard/supermicro/x10slm-f/acpi_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm-f/bootblock.c index c0d4502664..ff09a11726 100644 --- a/src/mainboard/supermicro/x10slm-f/bootblock.c +++ b/src/mainboard/supermicro/x10slm-f/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index deed223366..96e6227ce7 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/gpio.c b/src/mainboard/supermicro/x10slm-f/gpio.c index 53d15699e1..8758fab19f 100644 --- a/src/mainboard/supermicro/x10slm-f/gpio.c +++ b/src/mainboard/supermicro/x10slm-f/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm-f/hda_verb.c index 2a293190da..35c420ca68 100644 --- a/src/mainboard/supermicro/x10slm-f/hda_verb.c +++ b/src/mainboard/supermicro/x10slm-f/hda_verb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index 249659492a..27d9ec7594 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 47add723cf..574801c15f 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 2f1ce066d3..daaa96a9cc 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/raminit_tables.c b/src/northbridge/intel/ironlake/raminit_tables.c index f06918c961..3abd4c0a01 100644 --- a/src/northbridge/intel/ironlake/raminit_tables.c +++ b/src/northbridge/intel/ironlake/raminit_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/ironlake/raminit_tables.h b/src/northbridge/intel/ironlake/raminit_tables.h index 160c90b2fb..05a8c35f6c 100644 --- a/src/northbridge/intel/ironlake/raminit_tables.h +++ b/src/northbridge/intel/ironlake/raminit_tables.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 4a50b1328f..588f0fac86 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h index fadd097f8b..310a575d9c 100644 --- a/src/northbridge/intel/pineview/iomap.h +++ b/src/northbridge/intel/pineview/iomap.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 42f9d0fd9e..92bca75fdf 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index aea699e3a8..081d1ee86d 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h index 0bde7d8194..2662d1905e 100644 --- a/src/northbridge/intel/pineview/raminit.h +++ b/src/northbridge/intel/pineview/raminit.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index ab5ddfd320..7ee3fdb284 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/chip.h b/src/northbridge/intel/x4x/chip.h index 28a95f5163..4b853b6943 100644 --- a/src/northbridge/intel/x4x/chip.h +++ b/src/northbridge/intel/x4x/chip.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 614fd05e64..bd4a4d6ff0 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h index 3dc01b64b7..c2d48a73da 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/iomap.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 797bc5a378..817b789036 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 237060ad48..81e6395846 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index 5f23994355..f9ab7dfc57 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index ea5762188c..e466eeb4cf 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 26d336bfd2..e35606617a 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 944d853646..eb8040c3ab 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 8d105c37d0..5b4a82a216 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index c26c04a1c2..422bf2d021 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl index 67774fd507..f46941795b 100644 --- a/src/soc/intel/apollolake/acpi/lpss.asl +++ b/src/soc/intel/apollolake/acpi/lpss.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 65eb4d64f9..3148ac6e13 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index d91f743d07..0373e97f45 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index f8d0876fbd..e608aa87a9 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 297038f755..7d0c94c34a 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl index 2991512653..c8bd339c6b 100644 --- a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl +++ b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl index 64e2d80bd9..6692b17af7 100644 --- a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl +++ b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index df3eb374fc..b389813519 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 790f5a7091..c213461c55 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 0b2de52fbb..7e303c712a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ac36b702ab..3efd97004a 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 1e60683b37..4484413e61 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index 7ec1ebb703..a9e4ed2646 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index b106fc3287..4a377820de 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index 2675ed6d41..d895018409 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 3b41d73a18..aff4c38fba 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c index 56d8047b72..80934f97b6 100644 --- a/src/soc/intel/apollolake/gspi.c +++ b/src/soc/intel/apollolake/gspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/heci.c b/src/soc/intel/apollolake/heci.c index bfe7eb5772..8dad3a3d54 100644 --- a/src/soc/intel/apollolake/heci.c +++ b/src/soc/intel/apollolake/heci.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 359d4b50ab..332d26a0f4 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 6f71e7fab2..06fc29ecba 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h index 673580fe63..41f4dabece 100644 --- a/src/soc/intel/apollolake/include/soc/heci.h +++ b/src/soc/intel/apollolake/include/soc/heci.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index b06a9e1bad..f254f01f05 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h index 036efa260e..c578c588ad 100644 --- a/src/soc/intel/apollolake/include/soc/nhlt.h +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 79fe1d868a..cc97bb15ce 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 12a4e8db83..8cb56b64cd 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 207d1ef6d8..72a149652d 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h index 3fc0639453..38839f3342 100644 --- a/src/soc/intel/apollolake/include/soc/ramstage.h +++ b/src/soc/intel/apollolake/include/soc/ramstage.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index 486f963856..8c4d1ed405 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index 5238b9357c..0ac82930a7 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 6f42e18de6..060d5bd1b8 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 20a6ce510a..541df007f7 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index b7530576c8..f84821c7b3 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c index bf19b2feee..d5ce4ae271 100644 --- a/src/soc/intel/apollolake/nhlt.c +++ b/src/soc/intel/apollolake/nhlt.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 3afb8725ca..60cc9aa927 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 4a33b6c63e..58d34d1dbf 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index eff7f04506..338aac9b63 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 4fa8062f6a..2a3c500451 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index a1b6b4d2a5..b5ae6f36ff 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index ea1c1cbb71..965e4eeb3d 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl index cb8ee57013..d9f265ad80 100644 --- a/src/soc/intel/cannonlake/acpi/gfx.asl +++ b/src/soc/intel/cannonlake/acpi/gfx.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 0d2d9c39f0..83a64cadae 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index 5a993a5668..d765ee3353 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 62197f499a..458c1aa671 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index ace0d346af..f6419854fd 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index 8595b8d7be..50ecb462e7 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c index 1a893ec494..07dfbea43b 100644 --- a/src/soc/intel/cannonlake/gpio_common.c +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 57270b428b..65dd621f66 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c index 706eeac854..43825d8bbb 100644 --- a/src/soc/intel/cannonlake/gspi.c +++ b/src/soc/intel/cannonlake/gspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/include/soc/nhlt.h b/src/soc/intel/cannonlake/include/soc/nhlt.h index f3ac06ea77..3b8a35383f 100644 --- a/src/soc/intel/cannonlake/include/soc/nhlt.h +++ b/src/soc/intel/cannonlake/include/soc/nhlt.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c index 3aa4b8debb..56ad12a2ec 100644 --- a/src/soc/intel/cannonlake/nhlt.c +++ b/src/soc/intel/cannonlake/nhlt.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/cannonlake/spi.c b/src/soc/intel/cannonlake/spi.c index 9f3f44a227..8a14d244bb 100644 --- a/src/soc/intel/cannonlake/spi.c +++ b/src/soc/intel/cannonlake/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 905032fa77..fd6e48c310 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 7206708a37..91265be799 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 26c938b2b0..07aebd5ea4 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index e73c7767c1..a9304ba48b 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5392958b42..702b9a1431 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 148b815ea3..939d2e0146 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 2d0fecf3b0..e8759ffa76 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 5cad63c47f..a0998e1e88 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index db0f50324c..dd107a74b2 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 6eaaf0cab7..5327dba195 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 1b5063ca5b..9100f2af21 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 2ce47ed07d..072963bb0d 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 767315a304..2d18838a13 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 6f9ee732f4..f8b467a849 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index a96dc18307..ef8515c5bf 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index ec3a99ad22..6dee8792dc 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index 0e605d6c61..e881b5417a 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 5b15d498f8..28f312179e 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index 0f19464fc6..4b9fbe1b49 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 16175e7317..986459eeb3 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index ab90123dfa..19dddbed82 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c index 997c991c0c..77053292ca 100644 --- a/src/soc/intel/denverton_ns/gpio.c +++ b/src/soc/intel/denverton_ns/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/hob_display.c b/src/soc/intel/denverton_ns/hob_display.c index 9c09ad0d08..b046b308c7 100644 --- a/src/soc/intel/denverton_ns/hob_display.c +++ b/src/soc/intel/denverton_ns/hob_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/include/soc/romstage.h b/src/soc/intel/denverton_ns/include/soc/romstage.h index 96ff779bea..66f86ee0cc 100644 --- a/src/soc/intel/denverton_ns/include/soc/romstage.h +++ b/src/soc/intel/denverton_ns/include/soc/romstage.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 48e2da7f98..790275a3ae 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/spi.c b/src/soc/intel/denverton_ns/spi.c index 290816104c..4fefd361b0 100644 --- a/src/soc/intel/denverton_ns/spi.c +++ b/src/soc/intel/denverton_ns/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index ce608195f6..44ba0335d7 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index cc7bc04012..60ff4d9c7d 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/denverton_ns/upd_display.c b/src/soc/intel/denverton_ns/upd_display.c index 4467e30fb9..58e0ad5d68 100644 --- a/src/soc/intel/denverton_ns/upd_display.c +++ b/src/soc/intel/denverton_ns/upd_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl index 6dba827e52..a6aa0abacc 100644 --- a/src/soc/intel/icelake/acpi/pci_irqs.asl +++ b/src/soc/intel/icelake/acpi/pci_irqs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 3dd4894638..b98f4ef843 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index f25ede023b..f8452ea9a1 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 175b3ceefa..33e6227f9a 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/gspi.c b/src/soc/intel/icelake/gspi.c index 706eeac854..43825d8bbb 100644 --- a/src/soc/intel/icelake/gspi.c +++ b/src/soc/intel/icelake/gspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/icelake/me.c b/src/soc/intel/icelake/me.c index bbfd166061..05ed199bd7 100644 --- a/src/soc/intel/icelake/me.c +++ b/src/soc/intel/icelake/me.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2020 Google LLC. * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/intel/icelake/spi.c b/src/soc/intel/icelake/spi.c index 9f3f44a227..8a14d244bb 100644 --- a/src/soc/intel/icelake/spi.c +++ b/src/soc/intel/icelake/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl index 4f08cd78bd..cc832e41fc 100644 --- a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl index 086282e733..aa5048ee52 100644 --- a/src/soc/intel/jasperlake/acpi/pci_irqs.asl +++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index c0674a0ed7..549ee96051 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index afb9f7b3bc..7850c64f33 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 175b3ceefa..33e6227f9a 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c index 706eeac854..43825d8bbb 100644 --- a/src/soc/intel/jasperlake/gspi.c +++ b/src/soc/intel/jasperlake/gspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/jasperlake/spi.c b/src/soc/intel/jasperlake/spi.c index 9f3f44a227..8a14d244bb 100644 --- a/src/soc/intel/jasperlake/spi.c +++ b/src/soc/intel/jasperlake/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c index 28bf448fca..13e329dd61 100644 --- a/src/soc/intel/skylake/gspi.c +++ b/src/soc/intel/skylake/gspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/nhlt/da7219.c b/src/soc/intel/skylake/nhlt/da7219.c index 323744d33d..5ce3e357b3 100644 --- a/src/soc/intel/skylake/nhlt/da7219.c +++ b/src/soc/intel/skylake/nhlt/da7219.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c index 6d35b2735f..bebf6c4186 100644 --- a/src/soc/intel/skylake/spi.c +++ b/src/soc/intel/skylake/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index 4f08cd78bd..cc832e41fc 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 116b9a3fd0..a021d368a3 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 6329340392..2c99978f33 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c index f96262a74e..ca02cd965d 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index bbf36ca6a3..f8d1125d08 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/gspi.c b/src/soc/intel/tigerlake/gspi.c index 1381fb2499..9385ec1043 100644 --- a/src/soc/intel/tigerlake/gspi.c +++ b/src/soc/intel/tigerlake/gspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index 9b61496e65..a6ebcc317a 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2020 Google LLC. * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index 5270616af6..765a24d079 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 8e236f2942..d89143bf48 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index af6f545037..134d0e6c25 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index ec1e79d4dd..3f3b3f1538 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index 85ad2b0125..c4091d1255 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 5388214907..bcd476cdf3 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 8337210145..80101f5797 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 6f907f6ff0..e41b771c79 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index c2f1f89181..696734e5ae 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/reset.c b/src/soc/intel/xeon_sp/reset.c index e4ab466d9c..259fbc3089 100644 --- a/src/soc/intel/xeon_sp/reset.c +++ b/src/soc/intel/xeon_sp/reset.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 7881b0adb9..c0177bd9bd 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 98cdd99545..6d95d51ce8 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl index b719aa98b4..3e19165b29 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl index 6750a4c56a..6347c2ba19 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl index ced1c4fd2b..4ed1c1dd25 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index ede2208f0d..2bb1e4adaf 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 9a9c45555c..3f9db8215c 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index 7565d6c11a..8b48eb7e80 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index fcee02faee..d19921bc2e 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c index 567fad11c8..2cc39e6870 100644 --- a/src/soc/intel/xeon_sp/skx/hob_display.c +++ b/src/soc/intel/xeon_sp/skx/hob_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h index 3d32cd104a..e7f176ae7a 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index 611fb19715..08ce4edd94 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/include/soc/irq.h b/src/soc/intel/xeon_sp/skx/include/soc/irq.h index bfb800862f..92bcdc8f0f 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/irq.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/irq.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h index 95057769bb..31c1c026b4 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/msr.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index fae7ca0279..07edad25e7 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h index cf615ff635..ffd67b16d9 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index edacafdcfa..9beddcc4d0 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c index 6ba46a9237..fcea838917 100644 --- a/src/soc/intel/xeon_sp/skx/upd_display.c +++ b/src/soc/intel/xeon_sp/skx/upd_display.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/spi.c b/src/soc/intel/xeon_sp/spi.c index a5bc729d09..fbb60e8b0b 100644 --- a/src/soc/intel/xeon_sp/spi.c +++ b/src/soc/intel/xeon_sp/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 670d62a5a5..a578efe8e2 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/nvidia/tegra124/include/soc/sor.h b/src/soc/nvidia/tegra124/include/soc/sor.h index c10fe197ef..d998f8425c 100644 --- a/src/soc/nvidia/tegra124/include/soc/sor.h +++ b/src/soc/nvidia/tegra124/include/soc/sor.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * drivers/video/tegra/dc/sor_regs.h * * diff --git a/src/soc/nvidia/tegra124/maincpu.S b/src/soc/nvidia/tegra124/maincpu.S index 14fe0ec05f..f6514396df 100644 --- a/src/soc/nvidia/tegra124/maincpu.S +++ b/src/soc/nvidia/tegra124/maincpu.S @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/nvidia/tegra210/include/soc/sor.h b/src/soc/nvidia/tegra210/include/soc/sor.h index b7051a4daf..bb25c46833 100644 --- a/src/soc/nvidia/tegra210/include/soc/sor.h +++ b/src/soc/nvidia/tegra210/include/soc/sor.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * drivers/video/tegra/dc/sor_regs.h * * diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index b199a225a0..22cb71f9bb 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index e53e48805d..18a4a32821 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 6cdf249c8f..68a9b69982 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index 312d4e945e..c9967a79fe 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index be206aa9dd..93472e5014 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/ipq40xx/blsp.c b/src/soc/qualcomm/ipq40xx/blsp.c index bfbf7027bd..6acd9a3267 100644 --- a/src/soc/qualcomm/ipq40xx/blsp.c +++ b/src/soc/qualcomm/ipq40xx/blsp.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index cb69feb34d..394724008e 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/qup.h b/src/soc/qualcomm/ipq40xx/include/soc/qup.h index 093d33a78c..0566857738 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/qup.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/qup.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h b/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h index 8a8499173f..d2c9c6e0b8 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/usbl_if.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 8810430545..d02f9a8d4f 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/ipq806x/gsbi.c b/src/soc/qualcomm/ipq806x/gsbi.c index c121062c43..6a31f91f86 100644 --- a/src/soc/qualcomm/ipq806x/gsbi.c +++ b/src/soc/qualcomm/ipq806x/gsbi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index 50222a131e..ddd42e4272 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/include/soc/qup.h b/src/soc/qualcomm/ipq806x/include/soc/qup.h index 9587e9d9db..2645af52f4 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/qup.h +++ b/src/soc/qualcomm/ipq806x/include/soc/qup.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h b/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h index ac5e441357..1a3ee8d4fa 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h +++ b/src/soc/qualcomm/ipq806x/include/soc/usbl_if.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index 55c2151d36..283d85799a 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c index 089d9e425b..93f232b590 100644 --- a/src/soc/qualcomm/qcs405/blsp.c +++ b/src/soc/qualcomm/qcs405/blsp.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index 2539445a8f..dcfc84676b 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index ed408b0d9a..6a0fe9d2db 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index d762aa14e1..bc88bd6cee 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index 57472f4905..98f4467472 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index 0fdb7f79ae..9e665edea5 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 3110fd15cc..f138fb75d1 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index fa3a56577a..a6a9fea26e 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 17bdfabaa1..55f478dc1b 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 1084eb974e..90f72969cd 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/include/soc/usb.h b/src/soc/qualcomm/qcs405/include/soc/usb.h index 0c56183d2b..04ab3b6cd3 100644 --- a/src/soc/qualcomm/qcs405/include/soc/usb.h +++ b/src/soc/qualcomm/qcs405/include/soc/usb.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index a4c618cf56..e6b70c078e 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index acbbdad565..cb9bad17da 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index ffa84a3641..5f11f73378 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c index 595ff9b7a4..085344c331 100644 --- a/src/soc/qualcomm/qcs405/timer.c +++ b/src/soc/qualcomm/qcs405/timer.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index d35c081bcb..1723fac438 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 87c3c38c09..784101a3cf 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index d860c4a5fd..29d5d896a3 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 7f32742581..3f654fdffb 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 56185eec8a..b7fe201ff2 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 6ce7b9b185..0b9f4396e1 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h index 46de9d4c0f..1fd026180e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/aop.h +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 25903fb42c..a2a7a802d4 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/efuse.h b/src/soc/qualcomm/sc7180/include/soc/efuse.h index bb673e0a56..fd14d89bc9 100644 --- a/src/soc/qualcomm/sc7180/include/soc/efuse.h +++ b/src/soc/qualcomm/sc7180/include/soc/efuse.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index d01f479657..b7f4fdef8d 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 6a830c2cfa..5c2736ea16 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h index c8f16ba713..34ff5d72fa 100644 --- a/src/soc/qualcomm/sc7180/include/soc/mmu.h +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h index 051af9c0b0..307ea6ab54 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (c) 2018-2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/qualcomm/sc7180/include/soc/qspi.h b/src/soc/qualcomm/sc7180/include/soc/qspi.h index c80a28c110..0d6fbcb09f 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qspi.h +++ b/src/soc/qualcomm/sc7180/include/soc/qspi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h index 4999422896..a147070fe0 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (c) 2018-2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 0381393173..9082f3eea7 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h index 2401dfc1d6..846b0d1a70 100644 --- a/src/soc/qualcomm/sc7180/include/soc/usb.h +++ b/src/soc/qualcomm/sc7180/include/soc/usb.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 2d43d79ba9..5eb9b27cde 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 5b22c73c7a..80cc7558b2 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index b6540a88cf..e0a7d4ca7b 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (c) 2018-2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index e1d142e994..f670f6d9b3 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index b6999056fb..756d6efb82 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2018-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index aba35281c2..ac3032f491 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 67176970ad..775f4e597e 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index 10d09268d8..5e6292394f 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c index 595ff9b7a4..085344c331 100644 --- a/src/soc/qualcomm/sc7180/timer.c +++ b/src/soc/qualcomm/sc7180/timer.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index 1190353689..645e6a4384 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index 85772da2e3..bf3e64a213 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index ba4079a954..b984780b1e 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c index 7bbc60f712..bdc37c17ae 100644 --- a/src/soc/qualcomm/sdm845/bootblock.c +++ b/src/soc/qualcomm/sdm845/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 7f32742581..3f654fdffb 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index efd7a975e2..38168602b6 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h index 29c7dca920..e8b00a23f6 100644 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/aop.h b/src/soc/qualcomm/sdm845/include/soc/aop.h index e9eac99235..72b97b7946 100644 --- a/src/soc/qualcomm/sdm845/include/soc/aop.h +++ b/src/soc/qualcomm/sdm845/include/soc/aop.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index 7752c55cb9..a6e451c471 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h index d0a26d5610..0b1adf6ddb 100644 --- a/src/soc/qualcomm/sdm845/include/soc/efuse.h +++ b/src/soc/qualcomm/sdm845/include/soc/efuse.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h index e6670b0be8..8cb74763d0 100644 --- a/src/soc/qualcomm/sdm845/include/soc/gpio.h +++ b/src/soc/qualcomm/sdm845/include/soc/gpio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index c13baf8801..5c04f49e64 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h index c6ab2ca3b2..62e9ac2e0b 100644 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ b/src/soc/qualcomm/sdm845/include/soc/mmu.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/qspi.h b/src/soc/qualcomm/sdm845/include/soc/qspi.h index 716d0c59f0..2359c10eab 100644 --- a/src/soc/qualcomm/sdm845/include/soc/qspi.h +++ b/src/soc/qualcomm/sdm845/include/soc/qspi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index 8f23a2a6fa..fa5c1a710b 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h index f540af1fce..bb65899ccb 100644 --- a/src/soc/qualcomm/sdm845/include/soc/usb.h +++ b/src/soc/qualcomm/sdm845/include/soc/usb.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index b3ced55e46..906c0921cf 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c index 7569e99f07..8be4c9aebb 100644 --- a/src/soc/qualcomm/sdm845/qclib.c +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c index 838e3cda95..f0a52f6de0 100644 --- a/src/soc/qualcomm/sdm845/qspi.c +++ b/src/soc/qualcomm/sdm845/qspi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index 417588d6cc..1f076c903a 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c index ccdbba37f2..ec068f5ec0 100644 --- a/src/soc/qualcomm/sdm845/spi.c +++ b/src/soc/qualcomm/sdm845/spi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c index 595ff9b7a4..085344c331 100644 --- a/src/soc/qualcomm/sdm845/timer.c +++ b/src/soc/qualcomm/sdm845/timer.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c index dd58512b47..71913d1cbf 100644 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ b/src/soc/qualcomm/sdm845/uart_bitbang.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index f6e7d29cb5..6aa0015fd1 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index b333103964..20b8752e82 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index 3e496d084a..eee1743163 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 198c4c7486..8ba1eab9e5 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * DDR3 mem setup file for EXYNOS5 based board * * diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index d59b03d003..081728af92 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 381391424b..4e109e4da7 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c index d92f0b4b4e..e53bb70ada 100644 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index 3f350ba5d1..478107c5f5 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index d59b03d003..081728af92 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index dde0fb928d..19358a2bcc 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index d92f0b4b4e..e53bb70ada 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 3f350ba5d1..478107c5f5 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/common/finalize.h b/src/southbridge/intel/common/finalize.h index c071690637..2e70f849a7 100644 --- a/src/southbridge/intel/common/finalize.h +++ b/src/southbridge/intel/common/finalize.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 4e48fca6d5..6faaa3597f 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h index 87a91add93..6d42cc1e3f 100644 --- a/src/southbridge/intel/i82371eb/chip.h +++ b/src/southbridge/intel/i82371eb/chip.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 1e0bf8752f..168d3b2c1d 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 46f973df23..a7ef1eb9c0 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 03bbdccb76..3240221eff 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Based on src/southbridge/via/vt8237r/vt8237_fadt.c * * diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 4c33f93947..ec8745a286 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 5fcc484439..3433561fef 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 40e74e93ab..d2e8614c55 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index d1918657c8..4e32c1dab7 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index d74879d0b6..4c1594b4ff 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 4fcd26cc98..80c46b2a23 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index 45f0182edf..9d219b06e3 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801gx/sata.h b/src/southbridge/intel/i82801gx/sata.h index 2515470885..a4fc6dc88b 100644 --- a/src/southbridge/intel/i82801gx/sata.h +++ b/src/southbridge/intel/i82801gx/sata.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index 2838db1e98..f92269801f 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 67173a2f87..3ff08b2b95 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index cfaf3c80bd..89220eaa6b 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index df9456e1d4..8a16653eaf 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 5964aa97f5..211b5bc31c 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/chip.h b/src/southbridge/ti/pci7420/chip.h index 266c121c10..a5349d055a 100644 --- a/src/southbridge/ti/pci7420/chip.h +++ b/src/southbridge/ti/pci7420/chip.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index 126a8cf40d..037355e9c3 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index 2c7449ef23..8b02a5079d 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 9c50dbd94d..1ff86e6c88 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify diff --git a/util/cbfstool/coff.h b/util/cbfstool/coff.h index e814379c1b..3ee1b6a0f3 100644 --- a/util/cbfstool/coff.h +++ b/util/cbfstool/coff.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify diff --git a/util/cbfstool/console/console.h b/util/cbfstool/console/console.h index 40c1436ace..daf0458e93 100644 --- a/util/cbfstool/console/console.h +++ b/util/cbfstool/console/console.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify diff --git a/util/cbfstool/fv.h b/util/cbfstool/fv.h index 04a34e3108..996508d186 100644 --- a/util/cbfstool/fv.h +++ b/util/cbfstool/fv.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f8da7daa7e..24a9b5416a 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright 2012 Google Inc. * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * diff --git a/util/fuzz-tests/jpeg-test.c b/util/fuzz-tests/jpeg-test.c index 82967ddb4e..0f9a925d06 100644 --- a/util/fuzz-tests/jpeg-test.c +++ b/util/fuzz-tests/jpeg-test.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index e9aa510a10..0cb162707c 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or diff --git a/util/intelmetool/me.h b/util/intelmetool/me.h index 6a208070ba..dca9a20f7c 100644 --- a/util/intelmetool/me.h +++ b/util/intelmetool/me.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or diff --git a/util/intelmetool/me_status.c b/util/intelmetool/me_status.c index ede3e3ac48..3f654f3916 100644 --- a/util/intelmetool/me_status.c +++ b/util/intelmetool/me_status.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or diff --git a/util/kbc1126/kbc1126_ec_dump.c b/util/kbc1126/kbc1126_ec_dump.c index 124a475a28..6122449fef 100644 --- a/util/kbc1126/kbc1126_ec_dump.c +++ b/util/kbc1126/kbc1126_ec_dump.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify diff --git a/util/kbc1126/kbc1126_ec_insert.c b/util/kbc1126/kbc1126_ec_insert.c index 64d1295c96..f582954c0d 100644 --- a/util/kbc1126/kbc1126_ec_insert.c +++ b/util/kbc1126/kbc1126_ec_insert.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2017 Iru Cai * * This program is free software; you can redistribute it and/or modify diff --git a/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl b/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl index 496334daab..3cc78aebd0 100644 --- a/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl +++ b/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/util/mainboard/google/hatch/template/include/variant/ec.h b/util/mainboard/google/hatch/template/include/variant/ec.h index 25269627bd..bbcd4a3b99 100644 --- a/util/mainboard/google/hatch/template/include/variant/ec.h +++ b/util/mainboard/google/hatch/template/include/variant/ec.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/util/mainboard/google/hatch/template/include/variant/gpio.h b/util/mainboard/google/hatch/template/include/variant/gpio.h index 3b07c1ba20..063c0f53a4 100644 --- a/util/mainboard/google/hatch/template/include/variant/gpio.h +++ b/util/mainboard/google/hatch/template/include/variant/gpio.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/util/nvramtool/cbfs.c b/util/nvramtool/cbfs.c index 3ce50c5524..67568fa7e9 100644 --- a/util/nvramtool/cbfs.c +++ b/util/nvramtool/cbfs.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2008 Jordan Crouse * Copyright (C) 2011 secunet Security Networks AG * (Written by Patrick Georgi ) diff --git a/util/nvramtool/cbfs.h b/util/nvramtool/cbfs.h index 47c9ad8d3d..679f5e43ba 100644 --- a/util/nvramtool/cbfs.h +++ b/util/nvramtool/cbfs.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2008 Jordan Crouse * * This file is dual-licensed. You can choose between: diff --git a/util/pmh7tool/pmh7tool.c b/util/pmh7tool/pmh7tool.c index f03d97e254..9f2dc64b69 100644 --- a/util/pmh7tool/pmh7tool.c +++ b/util/pmh7tool/pmh7tool.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2018 Evgeny Zinoviev * * This program is free software; you can redistribute it and/or modify diff --git a/util/pmh7tool/pmh7tool.h b/util/pmh7tool/pmh7tool.h index 37d5027a50..9549bbdd08 100644 --- a/util/pmh7tool/pmh7tool.h +++ b/util/pmh7tool/pmh7tool.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2018 Evgeny Zinoviev * * This program is free software; you can redistribute it and/or modify diff --git a/util/supermicro/smcbiosinfo/smcbiosinfo.c b/util/supermicro/smcbiosinfo/smcbiosinfo.c index ae2a17b469..de81debd75 100644 --- a/util/supermicro/smcbiosinfo/smcbiosinfo.c +++ b/util/supermicro/smcbiosinfo/smcbiosinfo.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2019 9elements Agency GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/util/vgabios/include/arch/byteorder.h b/util/vgabios/include/arch/byteorder.h index fd29071b9d..33a5e16637 100644 --- a/util/vgabios/include/arch/byteorder.h +++ b/util/vgabios/include/arch/byteorder.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2016 Google Inc * * This program is free software; you can redistribute it and/or modify diff --git a/util/vgabios/include/console/console.h b/util/vgabios/include/console/console.h index 443e3e8bb7..90f42e7e05 100644 --- a/util/vgabios/include/console/console.h +++ b/util/vgabios/include/console/console.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2016 Google Inc * * This program is free software; you can redistribute it and/or modify diff --git a/util/vgabios/include/stdtypes.h b/util/vgabios/include/stdtypes.h index 05f37a5a8a..4212f4898c 100644 --- a/util/vgabios/include/stdtypes.h +++ b/util/vgabios/include/stdtypes.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2016 Google Inc * * This program is free software; you can redistribute it and/or modify diff --git a/util/vgabios/include/swab.h b/util/vgabios/include/swab.h index 28d0b8abb2..4b82b6293c 100644 --- a/util/vgabios/include/swab.h +++ b/util/vgabios/include/swab.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/util/vgabios/pci-userspace.c b/util/vgabios/pci-userspace.c index 0390f7a494..1b02cf4dc1 100644 --- a/util/vgabios/pci-userspace.c +++ b/util/vgabios/pci-userspace.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2016 Google Inc * * This program is free software; you can redistribute it and/or modify diff --git a/util/vgabios/pci-userspace.h b/util/vgabios/pci-userspace.h index 2dbdbbe6a3..f1da2312e9 100644 --- a/util/vgabios/pci-userspace.h +++ b/util/vgabios/pci-userspace.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2016 Google Inc * * This program is free software; you can redistribute it and/or modify diff --git a/util/vgabios/testbios.c b/util/vgabios/testbios.c index de537b8fcd..189df24411 100644 --- a/util/vgabios/testbios.c +++ b/util/vgabios/testbios.c @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2016 Google Inc * * This program is free software; you can redistribute it and/or modify diff --git a/util/vgabios/testbios.h b/util/vgabios/testbios.h index a028bf0fa1..c7501ec773 100644 --- a/util/vgabios/testbios.h +++ b/util/vgabios/testbios.h @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright 1999 Egbert Eich * * This program is free software; you can redistribute it and/or modify diff --git a/util/x86/x86_page_tables.go b/util/x86/x86_page_tables.go index e477b54c5e..b447ea9fce 100644 --- a/util/x86/x86_page_tables.go +++ b/util/x86/x86_page_tables.go @@ -1,6 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify From afd4c876a9b4b1040673e94b7aa1561bf4ad4bc6 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 5 May 2020 23:43:18 +0200 Subject: [PATCH 1427/1463] treewide: move copyrights and authors to AUTHORS Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: HAOUAS Elyes --- AUTHORS | 6 ++++++ src/commonlib/include/commonlib/sd_mmc_ctrlr.h | 3 ++- src/commonlib/include/commonlib/sdhci.h | 3 ++- src/commonlib/storage/bouncebuf.c | 3 ++- src/commonlib/storage/bouncebuf.h | 3 ++- src/commonlib/storage/mmc.c | 3 ++- src/commonlib/storage/sd.c | 3 ++- src/commonlib/storage/sd_mmc.c | 3 ++- src/commonlib/storage/sdhci.c | 3 ++- src/commonlib/storage/sdhci_adma.c | 3 ++- src/commonlib/storage/sdhci_display.c | 3 ++- src/commonlib/storage/storage.c | 3 ++- src/commonlib/storage/storage_erase.c | 3 ++- src/commonlib/storage/storage_write.c | 3 ++- src/ec/google/chromeec/ec_message.h | 5 ++--- src/ec/kontron/kempld/kempld_i2c.c | 12 +++--------- src/include/b64_decode.h | 2 -- src/include/device_tree.h | 6 +----- src/include/endian.h | 2 -- src/include/fit.h | 6 +----- src/include/fit_payload.h | 5 ----- src/include/list.h | 6 +----- src/include/memory_info.h | 5 +---- src/include/spi-generic.h | 3 --- src/include/spi_flash.h | 5 +---- src/lib/b64_decode.c | 2 -- src/lib/device_tree.c | 6 +----- src/lib/fit.c | 6 +----- src/lib/hexdump.c | 2 -- src/lib/list.c | 6 +----- src/mainboard/emulation/qemu-i440fx/dsdt.asl | 5 +---- src/mainboard/emulation/qemu-q35/dsdt.asl | 7 +------ src/mainboard/intel/galileo/vboot.c | 2 -- src/mainboard/intel/galileo/vboot.fmd | 2 -- src/mainboard/ti/beaglebone/leds.c | 2 -- src/mainboard/ti/beaglebone/leds.h | 2 -- src/soc/nvidia/tegra210/include/soc/mipi_display.h | 4 ---- src/soc/nvidia/tegra210/include/soc/mipi_dsi.h | 4 ---- src/soc/qualcomm/qcs405/clock.c | 5 ++--- src/soc/qualcomm/qcs405/include/soc/clock.h | 5 ++--- src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h | 2 -- src/soc/qualcomm/sc7180/include/soc/qupv3_config.h | 5 +---- src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h | 5 +---- src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h | 2 -- src/soc/qualcomm/sc7180/qcom_qup_se.c | 2 -- src/soc/qualcomm/sc7180/qupv3_config.c | 5 +---- src/soc/qualcomm/sc7180/qupv3_i2c.c | 5 +---- src/soc/qualcomm/sc7180/qupv3_spi.c | 2 -- src/soc/qualcomm/sc7180/qupv3_uart.c | 2 -- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 3 +-- src/soc/samsung/exynos5420/dp.c | 2 -- src/soc/samsung/exynos5420/dp_lowlevel.c | 2 -- src/soc/samsung/exynos5420/fimd.c | 3 --- src/southbridge/intel/common/spi.h | 5 ++--- util/cbfstool/fdt.h | 6 +----- util/ectool/ec.c | 5 +---- util/ectool/ec.h | 4 +--- util/ectool/ectool.c | 4 +--- util/intelmetool/me.c | 1 - util/intelmetool/me.h | 1 - util/intelmetool/me_status.c | 1 - util/intelmetool/mmap.c | 6 ++---- util/intelmetool/mmap.h | 5 ++--- util/intelmetool/msr.c | 7 ++----- util/intelmetool/msr.h | 6 ++---- util/intelmetool/rcba.c | 2 -- util/intelmetool/rcba.h | 1 - util/inteltool/ahci.c | 5 +---- util/msrtool/Makefile.in | 2 -- util/msrtool/configure | 2 -- util/msrtool/cs5536.c | 5 +---- util/msrtool/darwin.c | 4 +--- util/msrtool/freebsd.c | 5 +---- util/msrtool/geodegx2.c | 5 +---- util/msrtool/geodelx.c | 4 +--- util/msrtool/intel_atom.c | 4 +--- util/msrtool/intel_core1.c | 4 +--- util/msrtool/intel_core2_early.c | 4 +--- util/msrtool/intel_core2_later.c | 4 +--- util/msrtool/intel_nehalem.c | 4 +--- util/msrtool/intel_pentium3.c | 4 +--- util/msrtool/intel_pentium3_early.c | 4 +--- util/msrtool/intel_pentium4_early.c | 4 +--- util/msrtool/intel_pentium4_later.c | 4 +--- util/msrtool/intel_pentium_d.c | 4 +--- util/msrtool/k8.c | 4 +--- util/msrtool/linux.c | 4 +--- util/msrtool/msrtool.c | 4 +--- util/msrtool/msrtool.h | 5 +---- util/msrtool/msrutils.c | 4 +--- util/msrtool/sys.c | 5 +---- util/msrtool/via_c7.c | 5 +---- util/pgtblgen/pgtblgen.c | 4 +--- util/qualcomm/scripts/cmm/debug_cb_405.cmm | 2 -- util/qualcomm/scripts/cmm/debug_cb_845.cmm | 2 -- util/qualcomm/scripts/cmm/debug_cb_common.cmm | 2 -- util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm | 2 -- util/qualcomm/scripts/cmm/debug_chroot_common.cmm | 2 -- util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm | 2 -- 99 files changed, 94 insertions(+), 281 deletions(-) diff --git a/AUTHORS b/AUTHORS index 2534a4625c..4bc62a7b63 100644 --- a/AUTHORS +++ b/AUTHORS @@ -43,6 +43,7 @@ Code Aurora Forum coresystems GmbH Corey Osgood Curt Brune +Custom Ideas Damien Zammit Dave Airlie David Brownell @@ -56,6 +57,7 @@ DENX Software Engineering Derek Waldner Digital Design Corporation DMP Electronics Inc. +Donghwa Lee Drew Eckhardt Dynon Avionics Edward O'Callaghan @@ -76,6 +78,7 @@ Free Software Foundation, Inc. Freescale Semiconductor, Inc. Gary Jennejohn George Trudeau +Gerald Van Baren Gerd Hoffmann Gergely Kiss Google LLC @@ -91,6 +94,7 @@ Idwer Vollering Igor Pavlov Imagination Technologies Infineon Technologies +InKi Dae Intel Corporation Iru Cai Isaku Yamahata @@ -135,6 +139,7 @@ Marvell Semiconductor Inc. Matt DeVillier Maxim Polyakov MediaTek Inc. +Michael Brunner Michael Schroeder Michael Niewöhner Mika Westerberg @@ -163,6 +168,7 @@ Paulo Alcantara Pavel Sayekat PC Engines GmbH Per Odlund +Peter Korsgaard Peter Stuge Philipp Degler Philipp Deppenwiese diff --git a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h index 0807d2e2c5..d681d2ecb2 100644 --- a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h +++ b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * Controller independent definitions */ #ifndef __COMMONLIB_SD_MMC_CTRLR_H__ diff --git a/src/commonlib/include/commonlib/sdhci.h b/src/commonlib/include/commonlib/sdhci.h index 126ef0176b..2ce3e8a39f 100644 --- a/src/commonlib/include/commonlib/sdhci.h +++ b/src/commonlib/include/commonlib/sdhci.h @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * SD host controller specific definitions */ #ifndef __COMMONLIB_SDHCI_H__ diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 6bc5cf4103..722a6c8d0b 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * Generic bounce buffer implementation */ diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h index 6a2e759614..615f73e2f6 100644 --- a/src/commonlib/storage/bouncebuf.h +++ b/src/commonlib/storage/bouncebuf.h @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * Generic bounce buffer implementation */ diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index 6346c432ba..d822865053 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * MultiMediaCard (MMC) and eMMC specific support code * This code is controller independent */ diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 1b4bee0b47..a925088afa 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * Secure Digital (SD) card specific support code * This code is controller independent */ diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index c8df33595a..8c0c1f7e1d 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common initialization * code which brings the card into the standby state. This code is controller * independent. diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 47286c54d2..231224c556 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * Secure Digital (SD) Host Controller interface specific code */ diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 843497116c..285ac0f1ec 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * Secure Digital (SD) Host Controller interface DMA support code */ diff --git a/src/commonlib/storage/sdhci_display.c b/src/commonlib/storage/sdhci_display.c index 4169f7ec98..6dad33c36e 100644 --- a/src/commonlib/storage/sdhci_display.c +++ b/src/commonlib/storage/sdhci_display.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * Secure Digital (SD) Host Controller interface specific code */ diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index 8f5a72f248..050d8bfb60 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common code which * transitions the card from the standby state to the transfer state. The * common code supports read operations, erase and write operations are in diff --git a/src/commonlib/storage/storage_erase.c b/src/commonlib/storage/storage_erase.c index b01388077e..2425b765d6 100644 --- a/src/commonlib/storage/storage_erase.c +++ b/src/commonlib/storage/storage_erase.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) erase support code. * This code is controller independent. */ diff --git a/src/commonlib/storage/storage_write.c b/src/commonlib/storage/storage_write.c index edf13fc0a3..f5af6dc663 100644 --- a/src/commonlib/storage/storage_write.c +++ b/src/commonlib/storage/storage_write.c @@ -9,7 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ +/* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) write support code. * This code is controller independent. */ diff --git a/src/ec/google/chromeec/ec_message.h b/src/ec/google/chromeec/ec_message.h index be0b08ab03..f0eab2f185 100644 --- a/src/ec/google/chromeec/ec_message.h +++ b/src/ec/google/chromeec/ec_message.h @@ -1,8 +1,7 @@ /* * Chromium OS Matrix Keyboard Message Protocol definitions - * - * Copyright (c) 2012 The Chromium OS Authors. - * + */ +/* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index ab41097782..56283eacc4 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -1,15 +1,9 @@ /* * I2C bus driver for Kontron COM modules * - * Copyright (C) 2017 secunet Security Networks AG - * - * Based on the similar driver in Linux: - * - * Copyright (c) 2010-2013 Kontron Europe GmbH - * Author: Michael Brunner - * - * The driver is based on the i2c-ocores driver by Peter Korsgaard. - * + * Based on the similar driver in Linux. + */ +/* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License 2 as published * by the Free Software Foundation. diff --git a/src/include/b64_decode.h b/src/include/b64_decode.h index 4d0970e1a5..0deb7aae31 100644 --- a/src/include/b64_decode.h +++ b/src/include/b64_decode.h @@ -1,6 +1,4 @@ /* - * Copyright (C) 2015 Google, Inc. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 30da803b63..0de9dba21a 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -1,9 +1,5 @@ +/* Taken from depthcharge: src/base/device_tree.h */ /* - * Copyright 2013 Google Inc. - * Copyright 2018-present Facebook, Inc. - * - * Taken from depthcharge: src/base/device_tree.h - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/include/endian.h b/src/include/endian.h index 0f32b7484a..a1c7f6a89b 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -1,6 +1,4 @@ /* - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/include/fit.h b/src/include/fit.h index 1c90aca1ff..beec38ae6a 100644 --- a/src/include/fit.h +++ b/src/include/fit.h @@ -1,9 +1,5 @@ +/* Taken from depthcharge: src/boot/fit.h */ /* - * Copyright 2013 Google Inc. - * Copyright 2018-present Facebook, Inc. - * - * Taken from depthcharge: src/boot/fit.h - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/include/fit_payload.h b/src/include/fit_payload.h index dd66289853..657c7d57f3 100644 --- a/src/include/fit_payload.h +++ b/src/include/fit_payload.h @@ -1,9 +1,4 @@ /* - * Copyright 2013 Google Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/include/list.h b/src/include/list.h index 201a8d39a8..9706080713 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -1,9 +1,5 @@ +/* Taken from depthcharge: src/base/list.h */ /* - * Copyright 2012 Google Inc. - * Copyright 2018-present Facebook, Inc. - * - * Taken from depthcharge: src/base/list.h - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/include/memory_info.h b/src/include/memory_info.h index ad3c1775f9..03b4fdc738 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -1,8 +1,5 @@ +/* Memory information */ /* - * Memory information - * - * Copyright (C) 2014, Intel Corporation. All rights reserved. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License version * 2 as published by the Free Software Foundation. diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 30228867fc..a57ec907d5 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -1,7 +1,4 @@ /* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index c74ceaeed4..5dce7206ab 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -1,8 +1,5 @@ +/* Interface to SPI flash */ /* - * Interface to SPI flash - * - * Copyright (C) 2008 Atmel Corporation - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. diff --git a/src/lib/b64_decode.c b/src/lib/b64_decode.c index 9efa465c25..57c883870e 100644 --- a/src/lib/b64_decode.c +++ b/src/lib/b64_decode.c @@ -1,6 +1,4 @@ /* - * Copyright (C) 2015 Google, Inc. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index b8faab53b8..2124edd582 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -1,9 +1,5 @@ +/* Taken from depthcharge: src/base/device_tree.c */ /* - * Copyright 2013 Google Inc. - * Copyright 2018-present Facebook, Inc. - * - * Taken from depthcharge: src/base/device_tree.c - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/lib/fit.c b/src/lib/fit.c index edac1927e7..be6c87a936 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -1,9 +1,5 @@ +/* Taken from depthcharge: src/boot/fit.c */ /* - * Copyright 2013 Google Inc. - * Copyright 2018-present Facebook, Inc. - * - * Taken from depthcharge: src/boot/fit.c - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 8ecba6d512..95f3b93f91 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -1,6 +1,4 @@ /* - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/lib/list.c b/src/lib/list.c index 06d422d30e..9138ab30cd 100644 --- a/src/lib/list.c +++ b/src/lib/list.c @@ -1,9 +1,5 @@ +/* Taken from depthcharge: src/base/list.c */ /* - * Copyright 2012 Google Inc. - * Copyright 2018-present Facebook, Inc. - * - * Taken from depthcharge: src/base/list.c - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index ad9243b9cb..c4ca0b3013 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -1,8 +1,5 @@ +/* Bochs/QEMU ACPI DSDT ASL definition */ /* - * Bochs/QEMU ACPI DSDT ASL definition - * - * Copyright (c) 2006 Fabrice Bellard - * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License version 2 as published by the Free Software Foundation. diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index 5e4769da56..31a26603c2 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -1,10 +1,5 @@ +/* Bochs/QEMU ACPI DSDT ASL definition */ /* - * Bochs/QEMU ACPI DSDT ASL definition - * - * Copyright (c) 2006 Fabrice Bellard - * Copyright (c) 2010 Isaku Yamahata - * yamahata at valinux co jp - * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License version 2 as published by the Free Software Foundation. diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 3ec5bb3b44..b0f8ae207b 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -1,6 +1,4 @@ /* - * Copyright (C) 2016-2017 Intel Corporation - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bdf19..3a64387636 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -1,6 +1,4 @@ # -# Copyright (C) 2016-2017 Intel Corporation -# # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index dd1471d06b..abad71867a 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -1,6 +1,4 @@ /* - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/mainboard/ti/beaglebone/leds.h b/src/mainboard/ti/beaglebone/leds.h index a4a6001f40..6a2d3ecb76 100644 --- a/src/mainboard/ti/beaglebone/leds.h +++ b/src/mainboard/ti/beaglebone/leds.h @@ -1,6 +1,4 @@ /* - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_display.h b/src/soc/nvidia/tegra210/include/soc/mipi_display.h index 96a6e42bab..38e4f9d186 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi_display.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi_display.h @@ -5,10 +5,6 @@ * Display Working Group standards: DSI, DCS, DBI, DPI * * Author: Imre Deak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef MIPI_DISPLAY_H #define MIPI_DISPLAY_H diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h index 55fe5d9c40..1c86c8da28 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h @@ -4,10 +4,6 @@ * MIPI DSI Bus * * Andrzej Hajda - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __MIPI_DSI_H__ diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index e2e03c3e32..cbc16a9614 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -1,6 +1,5 @@ - /* This file is part of the coreboot project. - * - * + /* This file is part of the coreboot project. */ + /* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index c021c49fa1..1778214d47 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -1,6 +1,5 @@ - /* This file is part of the coreboot project. - * - * + /* This file is part of the coreboot project. */ + /* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h index 307ea6ab54..221e44af33 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -1,7 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (c) 2018-2019 Qualcomm Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h index b2a89a53c0..941f6565c3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h @@ -1,8 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright (C) 2019, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h index e69f461ff9..3eaf0ce190 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h @@ -1,8 +1,5 @@ +/* This file is part of the depthcharge project. */ /* - * This file is part of the depthcharge project. - * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h index a147070fe0..172d937bd1 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h @@ -1,7 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (c) 2018-2019 Qualcomm Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index e0a7d4ca7b..58a1b36606 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,7 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (c) 2018-2019 Qualcomm Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 14df187886..15b6b4dbe9 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -1,8 +1,5 @@ +/* This file is part of the coreboot project. */ /* - * This file is part of the coreboot project. - * - * Copyright (C) 2020, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index b8938e2315..02f92b4aa0 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -1,8 +1,5 @@ +/* This file is part of the depthcharge project. */ /* - * This file is part of the depthcharge project. - * - * Copyright (C) 2018-2020, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index 756d6efb82..4d26a2933b 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,7 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (C) 2018-2020, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index ac3032f491..916d4aa4d4 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -1,7 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 8ba1eab9e5..90ad93298a 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -1,7 +1,6 @@ /* This file is part of the coreboot project. */ +/* DDR3 mem setup file for EXYNOS5 based board */ /* - * DDR3 mem setup file for EXYNOS5 based board - * * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index f1d374e1a3..101630dab4 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -1,6 +1,4 @@ /* - * - * Author: Donghwa Lee * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 33140e2c33..6bb73512ab 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -1,6 +1,4 @@ /* - * - * Author: Donghwa Lee * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 66745037fe..20480f4251 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -1,7 +1,4 @@ /* - * - * Author: InKi Dae - * Author: Donghwa Lee * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3b8410cd9f..3c997f8e60 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -1,7 +1,6 @@ -/* - * This file is part of the coreboot project. +/* This file is part of the coreboot project. */ - * This program is free software; you can redistribute it and/or +/* This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of * the License. diff --git a/util/cbfstool/fdt.h b/util/cbfstool/fdt.h index 387cd328ed..126ca95200 100644 --- a/util/cbfstool/fdt.h +++ b/util/cbfstool/fdt.h @@ -1,9 +1,5 @@ +/* Taken from depthcharge: src/base/device_tree.h */ /* - * Copyright 2013 Google Inc. - * Copyright 2018-present Facebook, Inc. - * - * Taken from depthcharge: src/base/device_tree.h - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/util/ectool/ec.c b/util/ectool/ec.c index d6c20001d8..17a08dcbf9 100644 --- a/util/ectool/ec.c +++ b/util/ectool/ec.c @@ -1,8 +1,5 @@ +/* This file is part of the ectool project. */ /* - * This file is part of the ectool project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of the License. diff --git a/util/ectool/ec.h b/util/ectool/ec.h index fd062356d0..b7bc6b938f 100644 --- a/util/ectool/ec.h +++ b/util/ectool/ec.h @@ -1,7 +1,5 @@ +/* This file is part of the ectool project. */ /* - * This file is part of the ectool project. - * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index 2af45c30f2..21e1023b34 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -1,7 +1,5 @@ +/* This file is part of the ectool project. */ /* - * This file is part of the ectool project. - * - * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index 0cb162707c..e3df257272 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -1,6 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/intelmetool/me.h b/util/intelmetool/me.h index dca9a20f7c..4e0036e2d3 100644 --- a/util/intelmetool/me.h +++ b/util/intelmetool/me.h @@ -1,6 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/intelmetool/me_status.c b/util/intelmetool/me_status.c index 3f654f3916..77c3ba6644 100644 --- a/util/intelmetool/me_status.c +++ b/util/intelmetool/me_status.c @@ -1,6 +1,5 @@ /* This file is part of the coreboot project. */ /* - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/intelmetool/mmap.c b/util/intelmetool/mmap.c index e3075a8121..70bc42244d 100644 --- a/util/intelmetool/mmap.c +++ b/util/intelmetool/mmap.c @@ -1,7 +1,5 @@ -/* intelmetool - * - * Copyright (C) 2013-2015 Damien Zammit - * +/* intelmetool */ +/* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/util/intelmetool/mmap.h b/util/intelmetool/mmap.h index 31d8313bf3..ecc327a535 100644 --- a/util/intelmetool/mmap.h +++ b/util/intelmetool/mmap.h @@ -1,6 +1,5 @@ -/* intelmetool - * - * Copyright (C) 2013-2015 Damien Zammit +/* intelmetool */ +/* * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/intelmetool/msr.c b/util/intelmetool/msr.c index 5c84f2b582..d8735a7c0b 100644 --- a/util/intelmetool/msr.c +++ b/util/intelmetool/msr.c @@ -1,8 +1,5 @@ -/* intelmetool - * - * Copyright (C) 2013-2016 Philipp Deppenwiese , - * Copyright (C) 2013-2016 Alexander Couzens - * +/* intelmetool */ +/* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/util/intelmetool/msr.h b/util/intelmetool/msr.h index 1f6a1175af..c40700f248 100644 --- a/util/intelmetool/msr.h +++ b/util/intelmetool/msr.h @@ -1,7 +1,5 @@ -/* intelmetool - * - * Copyright (C) 2013-2016 Philipp Deppenwiese - * Copyright (C) 2013-2016 Alexander Couzens +/* intelmetool */ +/* * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/intelmetool/rcba.c b/util/intelmetool/rcba.c index ebc2d9ca48..d1aaa671a8 100644 --- a/util/intelmetool/rcba.c +++ b/util/intelmetool/rcba.c @@ -1,6 +1,4 @@ /* - * Copyright (C) 2014 Damien Zammit - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/intelmetool/rcba.h b/util/intelmetool/rcba.h index d40dcb9262..a87fe49180 100644 --- a/util/intelmetool/rcba.h +++ b/util/intelmetool/rcba.h @@ -1,5 +1,4 @@ /* - * Copyright (C) 2017 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 82f792d0e6..4be40ff38a 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -1,8 +1,5 @@ +/* ahci.c: dump AHCI registers */ /* - * ahci.c: dump AHCI registers - * - * Copyright (C) 2016 Iru Cai - * Copyright (C) 2017 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/util/msrtool/Makefile.in b/util/msrtool/Makefile.in index f50adc240d..45b4ba280a 100644 --- a/util/msrtool/Makefile.in +++ b/util/msrtool/Makefile.in @@ -2,8 +2,6 @@ # # This file is part of msrtool. # -# Copyright (c) 2008 Peter Stuge -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License version 2 as # published by the Free Software Foundation. diff --git a/util/msrtool/configure b/util/msrtool/configure index 0606f4b8b9..5f55056c9d 100755 --- a/util/msrtool/configure +++ b/util/msrtool/configure @@ -2,8 +2,6 @@ # # This file is part of msrtool. # -# Copyright (c) 2008, 2009 Peter Stuge -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License version 2 as # published by the Free Software Foundation. diff --git a/util/msrtool/cs5536.c b/util/msrtool/cs5536.c index d9c66d2c88..3d035000a3 100644 --- a/util/msrtool/cs5536.c +++ b/util/msrtool/cs5536.c @@ -1,8 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2009 Peter Stuge - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/util/msrtool/darwin.c b/util/msrtool/darwin.c index 1423fbd74d..efa37fce79 100644 --- a/util/msrtool/darwin.c +++ b/util/msrtool/darwin.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/freebsd.c b/util/msrtool/freebsd.c index 84988c748b..40cd9a16d7 100644 --- a/util/msrtool/freebsd.c +++ b/util/msrtool/freebsd.c @@ -1,8 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2009 Andriy Gapon - * Copyright (c) 2009 Peter Stuge * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/geodegx2.c b/util/msrtool/geodegx2.c index 9b6f221591..d6a845fc12 100644 --- a/util/msrtool/geodegx2.c +++ b/util/msrtool/geodegx2.c @@ -1,8 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2008 Peter Stuge - * Copyright (c) 2009 Nils Jacobs * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/geodelx.c b/util/msrtool/geodelx.c index b7e8917118..bac8ec1a82 100644 --- a/util/msrtool/geodelx.c +++ b/util/msrtool/geodelx.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2008 Peter Stuge * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index 8a73d94966..ac63a2615f 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2013 Olivier Langlois * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c index fdf4005cc8..fcb3a91659 100644 --- a/util/msrtool/intel_core1.c +++ b/util/msrtool/intel_core1.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c index a3c7ad26cc..ea35ac4b04 100644 --- a/util/msrtool/intel_core2_early.c +++ b/util/msrtool/intel_core2_early.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index fda85327bd..7e1cdfd9c6 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2013 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index c5c30826f1..3f472e8f6f 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2012 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c index e541e00e95..aedc4402cf 100644 --- a/util/msrtool/intel_pentium3.c +++ b/util/msrtool/intel_pentium3.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c index dbbc985b4d..676f134c41 100644 --- a/util/msrtool/intel_pentium3_early.c +++ b/util/msrtool/intel_pentium3_early.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c index 088a68ddcc..249cac8136 100644 --- a/util/msrtool/intel_pentium4_early.c +++ b/util/msrtool/intel_pentium4_early.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c index a23a99e606..0b51707d19 100644 --- a/util/msrtool/intel_pentium4_later.c +++ b/util/msrtool/intel_pentium4_later.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/intel_pentium_d.c b/util/msrtool/intel_pentium_d.c index f3675614f8..28b544bb01 100644 --- a/util/msrtool/intel_pentium_d.c +++ b/util/msrtool/intel_pentium_d.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/k8.c b/util/msrtool/k8.c index 16f626f55a..96aa6c5dfe 100644 --- a/util/msrtool/k8.c +++ b/util/msrtool/k8.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2009 Marc Jones * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/linux.c b/util/msrtool/linux.c index 64b4af212f..ccf8dbd0e0 100644 --- a/util/msrtool/linux.c +++ b/util/msrtool/linux.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2008 Peter Stuge * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 540ff53961..13586d8c78 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2008 Peter Stuge * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 8cba4c7483..f6ba66829b 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -1,8 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2008 Peter Stuge - * Copyright (c) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/msrutils.c b/util/msrtool/msrutils.c index 1c6707e4c2..82199a8f80 100644 --- a/util/msrtool/msrutils.c +++ b/util/msrtool/msrutils.c @@ -1,7 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2008 Peter Stuge * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/sys.c b/util/msrtool/sys.c index 7ff1131b63..f79391d434 100644 --- a/util/msrtool/sys.c +++ b/util/msrtool/sys.c @@ -1,8 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (c) 2008 Peter Stuge - * Copyright (c) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/msrtool/via_c7.c b/util/msrtool/via_c7.c index 07ed1756e7..9939798151 100644 --- a/util/msrtool/via_c7.c +++ b/util/msrtool/via_c7.c @@ -1,8 +1,5 @@ +/* This file is part of msrtool. */ /* - * This file is part of msrtool. - * - * Copyright (C) 2011 Anton Kochkov - * Copyright (C) 2017 Lubomir Rintel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index 234fd72a0e..b8bd0ed787 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -1,7 +1,5 @@ +/* This file is part of pgtblgen. */ /* - * This file is part of pgtblgen. - * - * Copyright (c) 2019 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/util/qualcomm/scripts/cmm/debug_cb_405.cmm b/util/qualcomm/scripts/cmm/debug_cb_405.cmm index 166d2aa308..bc677e9e62 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_405.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_405.cmm @@ -2,8 +2,6 @@ ;## ;## This file is part of the coreboot project. ;## -;## Copyright (C) 2018, The Linux Foundation. All rights reserved. -;## ;## This program is free software; you can redistribute it and/or modify ;## it under the terms of the GNU General Public License version 2 and ;## only version 2 as published by the Free Software Foundation. diff --git a/util/qualcomm/scripts/cmm/debug_cb_845.cmm b/util/qualcomm/scripts/cmm/debug_cb_845.cmm index c0a9cca74e..f99ff26216 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_845.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_845.cmm @@ -2,8 +2,6 @@ ;## ;## This file is part of the coreboot project. ;## -;## Copyright (C) 2018, The Linux Foundation. All rights reserved. -;## ;## This program is free software; you can redistribute it and/or modify ;## it under the terms of the GNU General Public License version 2 and ;## only version 2 as published by the Free Software Foundation. diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index bf90575823..f81d92b7ff 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -2,8 +2,6 @@ ;## ;## This file is part of the coreboot project. ;## -;## Copyright (C) 2018, The Linux Foundation. All rights reserved. -;## ;## This program is free software; you can redistribute it and/or modify ;## it under the terms of the GNU General Public License version 2 and ;## only version 2 as published by the Free Software Foundation. diff --git a/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm index 5d72ff792e..fd12041e4c 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm @@ -2,8 +2,6 @@ ;## ;## This file is part of the coreboot project. ;## -;## Copyright (C) 2019, The Linux Foundation. All rights reserved. -;## ;## This program is free software; you can redistribute it and/or modify ;## it under the terms of the GNU General Public License version 2 and ;## only version 2 as published by the Free Software Foundation. diff --git a/util/qualcomm/scripts/cmm/debug_chroot_common.cmm b/util/qualcomm/scripts/cmm/debug_chroot_common.cmm index 0e1d58baf5..93c2418a81 100644 --- a/util/qualcomm/scripts/cmm/debug_chroot_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_chroot_common.cmm @@ -2,8 +2,6 @@ ;## ;## This file is part of the coreboot project. ;## -;## Copyright (C) 2018, The Linux Foundation. All rights reserved. -;## ;## This program is free software; you can redistribute it and/or modify ;## it under the terms of the GNU General Public License version 2 and ;## only version 2 as published by the Free Software Foundation. diff --git a/util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm b/util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm index d93a4c0374..e84e54d35d 100644 --- a/util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm +++ b/util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm @@ -2,8 +2,6 @@ ;## ;## This file is part of the coreboot project. ;## -;## Copyright (C) 2019, The Linux Foundation. All rights reserved. -;## ;## This program is free software; you can redistribute it and/or modify ;## it under the terms of the GNU General Public License version 2 and ;## only version 2 as published by the Free Software Foundation. From ac9590395e0404e1fa1199643a1b28b228f992e5 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 5 May 2020 22:49:26 +0200 Subject: [PATCH 1428/1463] treewide: replace GPLv2 long form headers with SPDX header This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: HAOUAS Elyes --- src/commonlib/include/commonlib/loglevel.h | 12 +----------- src/commonlib/include/commonlib/sd_mmc_ctrlr.h | 12 +----------- src/commonlib/include/commonlib/sdhci.h | 12 +----------- src/commonlib/include/commonlib/storage.h | 12 +----------- src/commonlib/storage/bouncebuf.c | 12 +----------- src/commonlib/storage/bouncebuf.h | 12 +----------- src/commonlib/storage/mmc.c | 12 +----------- src/commonlib/storage/mmc.h | 12 +----------- src/commonlib/storage/pci_sdhci.c | 12 +----------- src/commonlib/storage/sd.c | 12 +----------- src/commonlib/storage/sd_mmc.c | 12 +----------- src/commonlib/storage/sd_mmc.h | 12 +----------- src/commonlib/storage/sdhci.c | 12 +----------- src/commonlib/storage/sdhci.h | 12 +----------- src/commonlib/storage/sdhci_adma.c | 12 +----------- src/commonlib/storage/sdhci_display.c | 12 +----------- src/commonlib/storage/storage.c | 12 +----------- src/commonlib/storage/storage.h | 12 +----------- src/commonlib/storage/storage_erase.c | 12 +----------- src/commonlib/storage/storage_write.c | 12 +----------- src/cpu/amd/agesa/family15tn/udelay.c | 12 +----------- src/cpu/amd/pi/00630F01/udelay.c | 12 +----------- src/cpu/intel/slot_1/l2_cache.c | 12 +----------- src/cpu/intel/slot_1/slot_1.c | 12 +----------- src/cpu/qemu-power8/qemu.c | 12 +----------- src/cpu/qemu-x86/qemu.c | 12 +----------- src/cpu/ti/am335x/clock.h | 12 +----------- src/cpu/ti/am335x/gpio.c | 12 +----------- src/cpu/ti/am335x/gpio.h | 12 +----------- src/cpu/ti/am335x/header.c | 12 +----------- src/cpu/ti/am335x/header.h | 12 +----------- src/cpu/ti/am335x/pinmux.c | 12 +----------- src/cpu/ti/am335x/pinmux.h | 12 +----------- src/cpu/ti/am335x/uart.c | 12 +----------- src/cpu/ti/am335x/uart.h | 12 +----------- src/cpu/x86/early_reset.S | 12 +----------- src/device/dram/ddr2.c | 12 +----------- src/device/dram/ddr3.c | 12 +----------- src/drivers/aspeed/common/aspeed_coreboot.h | 12 +----------- src/drivers/dec/21143/21143.c | 12 +----------- src/drivers/emulation/qemu/cirrus.c | 12 +----------- src/drivers/i2c/adt7463/adt7463.c | 12 +----------- src/drivers/i2c/tpm/cr50.c | 12 +----------- src/drivers/i2c/tpm/tis.c | 12 +----------- src/drivers/i2c/tpm/tis_atmel.c | 12 +----------- src/drivers/i2c/tpm/tpm.c | 12 +----------- src/drivers/i2c/tpm/tpm.h | 12 +----------- src/drivers/i2c/ww_ring/ww_ring.c | 11 +---------- src/drivers/i2c/ww_ring/ww_ring.h | 11 +---------- src/drivers/i2c/ww_ring/ww_ring_programs.c | 11 +---------- src/drivers/i2c/ww_ring/ww_ring_programs.h | 11 +---------- src/drivers/intel/fsp2_0/debug.c | 12 +----------- src/drivers/intel/fsp2_0/graphics.c | 12 +----------- src/drivers/intel/fsp2_0/hand_off_block.c | 12 +----------- src/drivers/intel/fsp2_0/header_display.c | 12 +----------- src/drivers/intel/fsp2_0/hob_display.c | 12 +----------- src/drivers/intel/fsp2_0/hob_verify.c | 12 +----------- src/drivers/intel/fsp2_0/include/fsp/api.h | 12 +----------- src/drivers/intel/fsp2_0/include/fsp/debug.h | 12 +----------- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 12 +----------- src/drivers/intel/fsp2_0/include/fsp/upd.h | 12 +----------- src/drivers/intel/fsp2_0/include/fsp/util.h | 12 +----------- src/drivers/intel/fsp2_0/memory_init.c | 12 +----------- src/drivers/intel/fsp2_0/notify.c | 12 +----------- src/drivers/intel/fsp2_0/silicon_init.c | 12 +----------- src/drivers/intel/fsp2_0/temp_ram_exit.c | 12 +----------- src/drivers/intel/fsp2_0/upd_display.c | 12 +----------- src/drivers/intel/fsp2_0/util.c | 12 +----------- src/drivers/intel/gma/edid.c | 12 +----------- src/drivers/intel/gma/opregion.c | 12 +----------- src/drivers/intel/gma/opregion.h | 12 +----------- src/drivers/intel/gma/vbt.c | 12 +----------- src/drivers/intel/wifi/wifi.c | 12 +----------- src/drivers/lenovo/lenovo.h | 12 +----------- src/drivers/lenovo/wacom.c | 12 +----------- src/drivers/maxim/max77686/max77686.c | 12 +----------- src/drivers/maxim/max77686/max77686.h | 12 +----------- src/drivers/maxim/max77802/max77802.h | 12 +----------- src/drivers/pc80/pc/spkmodem.c | 12 +----------- src/drivers/pc80/vga/vga_palette.c | 12 +----------- src/drivers/secunet/dmi/eeprom.h | 11 +---------- src/drivers/spi/adesto.c | 12 +----------- src/drivers/spi/amic.c | 12 +----------- src/drivers/spi/atmel.c | 12 +----------- src/drivers/spi/eon.c | 12 +----------- src/drivers/spi/gigadevice.c | 12 +----------- src/drivers/spi/macronix.c | 12 +----------- src/drivers/spi/spansion.c | 12 +----------- src/drivers/spi/spi-generic.c | 12 +----------- src/drivers/spi/spi_flash.c | 12 +----------- src/drivers/spi/spi_flash_internal.h | 12 +----------- src/drivers/spi/sst.c | 12 +----------- src/drivers/spi/stmicro.c | 12 +----------- src/drivers/spi/winbond.c | 12 +----------- src/drivers/uart/pl011.c | 11 +---------- src/drivers/wifi/generic.c | 12 +----------- src/drivers/xgi/common/xgi_coreboot.h | 12 +----------- src/ec/google/chromeec/ec_message.h | 12 +----------- src/include/b64_decode.h | 11 +---------- src/include/console/post_codes.h | 13 +------------ src/include/cpu/intel/l2_cache.h | 13 +------------ src/include/device/dram/common.h | 13 +------------ src/include/device/dram/ddr2.h | 13 +------------ src/include/device/dram/ddr3.h | 13 +------------ src/include/device_tree.h | 12 +----------- src/include/dimm_info_util.h | 12 +----------- src/include/endian.h | 12 +----------- src/include/fit.h | 12 +----------- src/include/fit_payload.h | 12 +----------- src/include/list.h | 12 +----------- src/include/memory_info.h | 11 +---------- src/include/pc80/vga.h | 13 +------------ src/include/pc80/vga_io.h | 13 +------------ src/include/sdram_mode.h | 13 +------------ src/include/spd.h | 13 +------------ src/include/spi-generic.h | 12 +----------- src/include/spi_bitbang.h | 12 +----------- src/include/spi_flash.h | 11 +---------- src/lib/b64_decode.c | 11 +---------- src/lib/device_tree.c | 12 +----------- src/lib/fit.c | 12 +----------- src/lib/hexdump.c | 12 +----------- src/lib/list.c | 12 +----------- src/mainboard/amd/padmelon/hda_verb.c | 13 +------------ src/mainboard/apple/macbook21/hda_verb.c | 13 +------------ src/mainboard/asrock/b75pro3-m/mainboard.c | 13 +------------ src/mainboard/asrock/g41c-gs/early_init.c | 13 +------------ src/mainboard/asrock/g41c-gs/hda_verb.c | 13 +------------ src/mainboard/asrock/h110m/mainboard.c | 13 +------------ src/mainboard/asrock/h81m-hds/acpi/platform.asl | 13 +------------ src/mainboard/asrock/h81m-hds/acpi/superio.asl | 13 +------------ src/mainboard/asrock/h81m-hds/acpi_tables.c | 13 +------------ src/mainboard/asrock/h81m-hds/dsdt.asl | 13 +------------ src/mainboard/asrock/h81m-hds/gpio.c | 13 +------------ src/mainboard/asrock/h81m-hds/hda_verb.c | 13 +------------ src/mainboard/asrock/h81m-hds/mainboard.c | 13 +------------ src/mainboard/asus/h61m-cs/acpi/platform.asl | 13 +------------ src/mainboard/asus/h61m-cs/dsdt.asl | 13 +------------ .../asus/maximus_iv_gene-z/acpi/platform.asl | 13 +------------ .../asus/maximus_iv_gene-z/acpi/superio.asl | 13 +------------ src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c | 13 +------------ src/mainboard/asus/maximus_iv_gene-z/dsdt.asl | 13 +------------ src/mainboard/asus/maximus_iv_gene-z/early_init.c | 13 +------------ src/mainboard/asus/maximus_iv_gene-z/gpio.c | 13 +------------ src/mainboard/asus/maximus_iv_gene-z/hda_verb.c | 13 +------------ src/mainboard/asus/maximus_iv_gene-z/mainboard.c | 13 +------------ src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c | 13 +------------ src/mainboard/asus/p2b/variants/p2b-d/mptable.c | 13 +------------ src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c | 13 +------------ src/mainboard/asus/p2b/variants/p2b-ds/mptable.c | 13 +------------ src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c | 13 +------------ src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c | 13 +------------ src/mainboard/asus/p2b/variants/p2b/irq_tables.c | 13 +------------ src/mainboard/asus/p3b-f/irq_tables.c | 13 +------------ src/mainboard/asus/p3b-f/romstage.c | 13 +------------ src/mainboard/asus/p5qc/early_init.c | 13 +------------ src/mainboard/asus/p5qc/hda_verb.c | 13 +------------ src/mainboard/asus/p5ql-em/early_init.c | 12 +----------- src/mainboard/asus/p5ql-em/hda_verb.c | 12 +----------- src/mainboard/asus/p5qpl-am/early_init.c | 13 +------------ src/mainboard/asus/p5qpl-am/hda_verb.c | 13 +------------ src/mainboard/asus/p8h61-m_lx/acpi/platform.asl | 13 +------------ src/mainboard/asus/p8h61-m_lx/acpi/superio.asl | 13 +------------ src/mainboard/asus/p8h61-m_lx/acpi_tables.c | 13 +------------ src/mainboard/asus/p8h61-m_lx/dsdt.asl | 13 +------------ src/mainboard/asus/p8h61-m_lx/early_init.c | 13 +------------ src/mainboard/asus/p8h61-m_lx/gpio.c | 13 +------------ src/mainboard/asus/p8h61-m_lx/hda_verb.c | 13 +------------ src/mainboard/asus/p8h61-m_lx/mainboard.c | 13 +------------ src/mainboard/asus/p8h61-m_pro/acpi/superio.asl | 13 +------------ src/mainboard/asus/p8z77-m_pro/acpi/platform.asl | 13 +------------ src/mainboard/asus/p8z77-m_pro/acpi/superio.asl | 13 +------------ src/mainboard/asus/p8z77-m_pro/acpi_tables.c | 13 +------------ src/mainboard/biostar/am1ml/irq_tables.c | 13 +------------ src/mainboard/emulation/qemu-armv7/mainboard.c | 13 +------------ src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h | 12 +----------- src/mainboard/foxconn/d41s/early_init.c | 13 +------------ src/mainboard/foxconn/g41s-k/early_init.c | 13 +------------ src/mainboard/foxconn/g41s-k/hda_verb.c | 13 +------------ .../g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl | 12 +----------- src/mainboard/gigabyte/ga-g41m-es2l/early_init.c | 13 +------------ src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 13 +------------ src/mainboard/google/cheza/board.h | 12 +----------- src/mainboard/google/cheza/bootblock.c | 12 +----------- src/mainboard/google/cheza/chromeos.c | 12 +----------- src/mainboard/google/cheza/mainboard.c | 12 +----------- src/mainboard/google/cheza/memlayout.ld | 12 +----------- src/mainboard/google/cheza/romstage.c | 12 +----------- src/mainboard/google/gale/bootblock.c | 12 +----------- src/mainboard/google/gale/mmu.c | 12 +----------- src/mainboard/google/gale/mmu.h | 12 +----------- src/mainboard/google/mistral/bootblock.c | 12 +----------- src/mainboard/google/mistral/chromeos.c | 12 +----------- src/mainboard/google/mistral/mainboard.c | 12 +----------- src/mainboard/google/mistral/memlayout.ld | 12 +----------- src/mainboard/google/mistral/romstage.c | 12 +----------- src/mainboard/google/storm/bootblock.c | 12 +----------- src/mainboard/google/storm/mmu.c | 12 +----------- src/mainboard/google/storm/mmu.h | 12 +----------- src/mainboard/google/trogdor/board.h | 12 +----------- src/mainboard/google/trogdor/bootblock.c | 12 +----------- src/mainboard/google/trogdor/chromeos.c | 12 +----------- src/mainboard/google/trogdor/mainboard.c | 12 +----------- src/mainboard/google/trogdor/memlayout.ld | 12 +----------- src/mainboard/google/trogdor/romstage.c | 12 +----------- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 13 +------------ src/mainboard/hp/pavilion_m6_1035dx/ec.c | 13 +------------ src/mainboard/hp/pavilion_m6_1035dx/ec.h | 13 +------------ src/mainboard/hp/pavilion_m6_1035dx/mainboard.h | 13 +------------ src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c | 13 +------------ src/mainboard/intel/apollolake_rvp/dsdt.asl | 13 +------------ src/mainboard/intel/apollolake_rvp/romstage.c | 13 +------------ src/mainboard/intel/d510mo/early_init.c | 13 +------------ src/mainboard/intel/dg41wv/early_init.c | 13 +------------ src/mainboard/intel/dg41wv/hda_verb.c | 13 +------------ src/mainboard/intel/dg43gt/early_init.c | 13 +------------ src/mainboard/intel/dg43gt/hda_verb.c | 13 +------------ src/mainboard/intel/galileo/vboot.c | 12 +----------- src/mainboard/intel/harcuvar/romstage.c | 13 +------------ src/mainboard/lenovo/g505s/acpi/ec.asl | 13 +------------ src/mainboard/lenovo/g505s/acpi/superio.asl | 13 +------------ src/mainboard/lenovo/g505s/ec.c | 13 +------------ src/mainboard/lenovo/g505s/ec.h | 13 +------------ src/mainboard/lenovo/g505s/mainboard.h | 13 +------------ src/mainboard/lenovo/g505s/mainboard_smi.c | 13 +------------ src/mainboard/lenovo/s230u/ec.h | 13 +------------ src/mainboard/lenovo/t410/hda_verb.c | 13 +------------ src/mainboard/lenovo/t440p/acpi/ec.asl | 13 +------------ src/mainboard/lenovo/t440p/acpi/platform.asl | 13 +------------ src/mainboard/lenovo/t440p/acpi/superio.asl | 13 +------------ src/mainboard/lenovo/t440p/dsdt.asl | 13 +------------ src/mainboard/lenovo/t440p/mainboard.c | 13 +------------ src/mainboard/lenovo/thinkcentre_a58/early_init.c | 13 +------------ src/mainboard/lenovo/thinkcentre_a58/hda_verb.c | 13 +------------ src/mainboard/lenovo/x201/hda_verb.c | 13 +------------ src/mainboard/msi/ms7707/acpi/platform.asl | 13 +------------ src/mainboard/msi/ms7707/dsdt.asl | 13 +------------ src/mainboard/ocp/tiogapass/acpi/platform.asl | 13 +------------ src/mainboard/ocp/tiogapass/dsdt.asl | 13 +------------ src/mainboard/ocp/tiogapass/fadt.c | 13 +------------ src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h | 13 +------------ src/mainboard/ocp/tiogapass/ramstage.c | 13 +------------ src/mainboard/ocp/tiogapass/romstage.c | 13 +------------ src/mainboard/packardbell/ms2290/hda_verb.c | 13 +------------ .../sapphire/pureplatinumh61/acpi_tables.c | 13 +------------ src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 13 +------------ src/mainboard/sapphire/pureplatinumh61/early_init.c | 13 +------------ src/mainboard/sapphire/pureplatinumh61/gpio.c | 13 +------------ src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 13 +------------ src/mainboard/sapphire/pureplatinumh61/mainboard.c | 13 +------------ src/mainboard/scaleway/tagada/romstage.c | 13 +------------ src/mainboard/supermicro/x10slm-f/acpi/platform.asl | 13 +------------ src/mainboard/supermicro/x10slm-f/acpi/superio.asl | 13 +------------ src/mainboard/supermicro/x10slm-f/acpi_tables.c | 13 +------------ src/mainboard/supermicro/x10slm-f/bootblock.c | 13 +------------ src/mainboard/supermicro/x10slm-f/dsdt.asl | 13 +------------ src/mainboard/supermicro/x10slm-f/gpio.c | 13 +------------ src/mainboard/supermicro/x10slm-f/hda_verb.c | 13 +------------ src/mainboard/supermicro/x10slm-f/mainboard.c | 13 +------------ src/mainboard/ti/beaglebone/leds.c | 12 +----------- src/mainboard/ti/beaglebone/leds.h | 12 +----------- src/northbridge/intel/e7505/e7505.h | 13 +------------ src/northbridge/intel/ironlake/raminit.c | 13 +------------ src/northbridge/intel/ironlake/raminit_tables.c | 13 +------------ src/northbridge/intel/ironlake/raminit_tables.h | 13 +------------ src/northbridge/intel/pineview/early_init.c | 13 +------------ src/northbridge/intel/pineview/iomap.h | 13 +------------ src/northbridge/intel/pineview/pineview.h | 13 +------------ src/northbridge/intel/pineview/raminit.c | 13 +------------ src/northbridge/intel/pineview/raminit.h | 13 +------------ src/northbridge/intel/x4x/bootblock.c | 13 +------------ src/northbridge/intel/x4x/chip.h | 13 +------------ src/northbridge/intel/x4x/dq_dqs.c | 13 +------------ src/northbridge/intel/x4x/iomap.h | 13 +------------ src/northbridge/intel/x4x/raminit.c | 13 +------------ src/northbridge/intel/x4x/raminit_ddr23.c | 13 +------------ src/northbridge/intel/x4x/raminit_tables.c | 13 +------------ src/northbridge/intel/x4x/rcven.c | 13 +------------ src/northbridge/intel/x4x/romstage.c | 12 +----------- src/soc/intel/apollolake/acpi.c | 13 +------------ src/soc/intel/apollolake/acpi/globalnvs.asl | 13 +------------ src/soc/intel/apollolake/acpi/gpio.asl | 13 +------------ src/soc/intel/apollolake/acpi/lpss.asl | 13 +------------ src/soc/intel/apollolake/acpi/northbridge.asl | 13 +------------ src/soc/intel/apollolake/acpi/pci_irqs.asl | 13 +------------ src/soc/intel/apollolake/acpi/soc_int.asl | 13 +------------ src/soc/intel/apollolake/acpi/southbridge.asl | 13 +------------ src/soc/intel/apollolake/acpi/xhci_apl_ports.asl | 13 +------------ src/soc/intel/apollolake/acpi/xhci_glk_ports.asl | 13 +------------ src/soc/intel/apollolake/bootblock/bootblock.c | 13 +------------ src/soc/intel/apollolake/car.c | 13 +------------ src/soc/intel/apollolake/chip.c | 13 +------------ src/soc/intel/apollolake/chip.h | 13 +------------ src/soc/intel/apollolake/cpu.c | 13 +------------ src/soc/intel/apollolake/fspcar.c | 13 +------------ src/soc/intel/apollolake/gpio_apl.c | 13 +------------ src/soc/intel/apollolake/gpio_glk.c | 13 +------------ src/soc/intel/apollolake/graphics.c | 13 +------------ src/soc/intel/apollolake/gspi.c | 13 +------------ src/soc/intel/apollolake/heci.c | 13 +------------ src/soc/intel/apollolake/include/soc/cpu.h | 13 +------------ src/soc/intel/apollolake/include/soc/gpio.h | 13 +------------ src/soc/intel/apollolake/include/soc/heci.h | 13 +------------ src/soc/intel/apollolake/include/soc/iomap.h | 13 +------------ src/soc/intel/apollolake/include/soc/nhlt.h | 13 +------------ src/soc/intel/apollolake/include/soc/nvs.h | 13 +------------ src/soc/intel/apollolake/include/soc/pci_devs.h | 12 +----------- src/soc/intel/apollolake/include/soc/pm.h | 13 +------------ src/soc/intel/apollolake/include/soc/ramstage.h | 13 +------------ src/soc/intel/apollolake/include/soc/romstage.h | 13 +------------ src/soc/intel/apollolake/include/soc/systemagent.h | 13 +------------ src/soc/intel/apollolake/include/soc/usb.h | 13 +------------ src/soc/intel/apollolake/lpc.c | 13 +------------ src/soc/intel/apollolake/mmap_boot.c | 13 +------------ src/soc/intel/apollolake/nhlt.c | 13 +------------ src/soc/intel/apollolake/pmc.c | 13 +------------ src/soc/intel/apollolake/pmutil.c | 13 +------------ src/soc/intel/apollolake/romstage.c | 13 +------------ src/soc/intel/apollolake/spi.c | 13 +------------ src/soc/intel/apollolake/systemagent.c | 13 +------------ src/soc/intel/apollolake/uart.c | 13 +------------ src/soc/intel/cannonlake/acpi/gfx.asl | 13 +------------ src/soc/intel/cannonlake/acpi/lpit.asl | 13 +------------ src/soc/intel/cannonlake/acpi/pci_irqs.asl | 13 +------------ src/soc/intel/cannonlake/acpi/southbridge.asl | 13 +------------ src/soc/intel/cannonlake/gpio.c | 13 +------------ src/soc/intel/cannonlake/gpio_cnp_h.c | 13 +------------ src/soc/intel/cannonlake/gpio_common.c | 13 +------------ src/soc/intel/cannonlake/graphics.c | 13 +------------ src/soc/intel/cannonlake/gspi.c | 13 +------------ src/soc/intel/cannonlake/include/soc/nhlt.h | 13 +------------ src/soc/intel/cannonlake/nhlt.c | 13 +------------ src/soc/intel/cannonlake/spi.c | 13 +------------ src/soc/intel/common/acpi.h | 11 +---------- src/soc/intel/common/block/acpi/acpi.c | 13 +------------ .../intel/common/block/acpi/acpi/northbridge.asl | 13 +------------ .../intel/common/block/cpu/car/cache_as_ram_fsp.S | 13 +------------ src/soc/intel/common/block/gpio/gpio.c | 13 +------------ src/soc/intel/common/block/graphics/graphics.c | 13 +------------ src/soc/intel/common/block/gspi/gspi.c | 13 +------------ .../intel/common/block/include/intelblocks/acpi.h | 13 +------------ .../intel/common/block/include/intelblocks/cse.h | 13 +------------ .../intel/common/block/include/intelblocks/gpio.h | 13 +------------ .../common/block/include/intelblocks/gpio_defs.h | 13 +------------ .../common/block/include/intelblocks/lpc_lib.h | 13 +------------ src/soc/intel/common/block/lpc/lpc.c | 13 +------------ src/soc/intel/common/block/lpc/lpc_def.h | 13 +------------ src/soc/intel/common/block/lpc/lpc_lib.c | 13 +------------ src/soc/intel/common/block/spi/spi.c | 13 +------------ src/soc/intel/common/block/sram/sram.c | 13 +------------ src/soc/intel/common/reset.h | 12 +----------- src/soc/intel/denverton_ns/bootblock/bootblock.c | 13 +------------ src/soc/intel/denverton_ns/bootblock/uart.c | 13 +------------ src/soc/intel/denverton_ns/chip.c | 13 +------------ src/soc/intel/denverton_ns/cpu.c | 13 +------------ src/soc/intel/denverton_ns/gpio.c | 13 +------------ src/soc/intel/denverton_ns/hob_display.c | 13 +------------ src/soc/intel/denverton_ns/memmap.c | 13 +------------ src/soc/intel/denverton_ns/spi.c | 13 +------------ src/soc/intel/denverton_ns/uart.c | 13 +------------ src/soc/intel/denverton_ns/uart_debug.c | 13 +------------ src/soc/intel/denverton_ns/upd_display.c | 13 +------------ src/soc/intel/icelake/acpi/pci_irqs.asl | 13 +------------ src/soc/intel/icelake/acpi/southbridge.asl | 13 +------------ src/soc/intel/icelake/gpio.c | 13 +------------ src/soc/intel/icelake/graphics.c | 13 +------------ src/soc/intel/icelake/gspi.c | 13 +------------ src/soc/intel/icelake/spi.c | 13 +------------ src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl | 13 +------------ src/soc/intel/jasperlake/acpi/pci_irqs.asl | 13 +------------ src/soc/intel/jasperlake/acpi/southbridge.asl | 13 +------------ src/soc/intel/jasperlake/gpio.c | 13 +------------ src/soc/intel/jasperlake/graphics.c | 13 +------------ src/soc/intel/jasperlake/gspi.c | 13 +------------ src/soc/intel/jasperlake/spi.c | 13 +------------ src/soc/intel/skylake/gspi.c | 13 +------------ src/soc/intel/skylake/nhlt/da7219.c | 13 +------------ src/soc/intel/skylake/spi.c | 13 +------------ src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl | 13 +------------ src/soc/intel/tigerlake/acpi/pci_irqs.asl | 13 +------------ src/soc/intel/tigerlake/acpi/southbridge.asl | 13 +------------ src/soc/intel/tigerlake/gpio.c | 13 +------------ src/soc/intel/tigerlake/graphics.c | 13 +------------ src/soc/intel/tigerlake/gspi.c | 13 +------------ src/soc/intel/tigerlake/spi.c | 13 +------------ src/soc/intel/xeon_sp/bootblock.c | 13 +------------ src/soc/intel/xeon_sp/include/soc/iomap.h | 13 +------------ src/soc/intel/xeon_sp/include/soc/pcr_ids.h | 13 +------------ src/soc/intel/xeon_sp/include/soc/pm.h | 13 +------------ src/soc/intel/xeon_sp/include/soc/pmc.h | 13 +------------ src/soc/intel/xeon_sp/include/soc/romstage.h | 13 +------------ src/soc/intel/xeon_sp/include/soc/util.h | 13 +------------ src/soc/intel/xeon_sp/lpc.c | 13 +------------ src/soc/intel/xeon_sp/reset.c | 13 +------------ src/soc/intel/xeon_sp/romstage.c | 13 +------------ src/soc/intel/xeon_sp/skx/acpi.c | 13 +------------ src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl | 13 +------------ src/soc/intel/xeon_sp/skx/acpi/iiostack.asl | 13 +------------ src/soc/intel/xeon_sp/skx/acpi/uncore.asl | 13 +------------ src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl | 13 +------------ src/soc/intel/xeon_sp/skx/chip.c | 13 +------------ src/soc/intel/xeon_sp/skx/chip.h | 13 +------------ src/soc/intel/xeon_sp/skx/cpu.c | 13 +------------ src/soc/intel/xeon_sp/skx/hob_display.c | 13 +------------ src/soc/intel/xeon_sp/skx/include/soc/acpi.h | 13 +------------ src/soc/intel/xeon_sp/skx/include/soc/cpu.h | 13 +------------ src/soc/intel/xeon_sp/skx/include/soc/irq.h | 13 +------------ src/soc/intel/xeon_sp/skx/include/soc/msr.h | 13 +------------ src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h | 13 +------------ src/soc/intel/xeon_sp/skx/include/soc/ramstage.h | 13 +------------ src/soc/intel/xeon_sp/skx/soc_util.c | 13 +------------ src/soc/intel/xeon_sp/skx/upd_display.c | 13 +------------ src/soc/intel/xeon_sp/spi.c | 13 +------------ src/soc/intel/xeon_sp/uncore.c | 13 +------------ src/soc/mediatek/mt8183/include/soc/md_ctrl.h | 12 +----------- src/soc/mediatek/mt8183/md_ctrl.c | 12 +----------- src/soc/nvidia/tegra/dc.h | 12 +----------- src/soc/nvidia/tegra/pwm.h | 12 +----------- src/soc/qualcomm/common/include/soc/mmu_common.h | 12 +----------- src/soc/qualcomm/common/include/soc/qclib_common.h | 12 +----------- .../qualcomm/common/include/soc/symbols_common.h | 12 +----------- src/soc/qualcomm/common/mmu.c | 12 +----------- src/soc/qualcomm/common/qclib.c | 12 +----------- src/soc/qualcomm/ipq40xx/tz_wrapper.S | 12 +----------- src/soc/qualcomm/ipq806x/tz_wrapper.S | 12 +----------- src/soc/qualcomm/qcs405/bootblock.c | 12 +----------- src/soc/qualcomm/qcs405/cbmem.c | 12 +----------- src/soc/qualcomm/qcs405/clock.c | 11 +---------- src/soc/qualcomm/qcs405/include/soc/addressmap.h | 12 +----------- src/soc/qualcomm/qcs405/include/soc/clock.h | 11 +---------- src/soc/qualcomm/qcs405/include/soc/gpio.h | 12 +----------- src/soc/qualcomm/qcs405/include/soc/memlayout.ld | 12 +----------- src/soc/qualcomm/qcs405/include/soc/mmu.h | 12 +----------- src/soc/qualcomm/qcs405/include/soc/symbols.h | 12 +----------- src/soc/qualcomm/qcs405/include/soc/usb.h | 12 +----------- src/soc/qualcomm/qcs405/mmu.c | 12 +----------- src/soc/qualcomm/qcs405/soc.c | 12 +----------- src/soc/qualcomm/qcs405/timer.c | 12 +----------- src/soc/qualcomm/qcs405/usb.c | 12 +----------- src/soc/qualcomm/sc7180/aop_load_reset.c | 12 +----------- src/soc/qualcomm/sc7180/bootblock.c | 12 +----------- src/soc/qualcomm/sc7180/cbmem.c | 12 +----------- src/soc/qualcomm/sc7180/clock.c | 12 +----------- src/soc/qualcomm/sc7180/include/soc/addressmap.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/aop.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/clock.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/efuse.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/gpio.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/memlayout.ld | 12 +----------- src/soc/qualcomm/sc7180/include/soc/mmu.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h | 11 +---------- src/soc/qualcomm/sc7180/include/soc/qspi.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h | 11 +---------- src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h | 11 +---------- src/soc/qualcomm/sc7180/include/soc/symbols.h | 12 +----------- src/soc/qualcomm/sc7180/include/soc/usb.h | 12 +----------- src/soc/qualcomm/sc7180/mmu.c | 12 +----------- src/soc/qualcomm/sc7180/qclib.c | 12 +----------- src/soc/qualcomm/sc7180/qcom_qup_se.c | 11 +---------- src/soc/qualcomm/sc7180/qspi.c | 12 +----------- src/soc/qualcomm/sc7180/qupv3_i2c.c | 11 +---------- src/soc/qualcomm/sc7180/qupv3_spi.c | 11 +---------- src/soc/qualcomm/sc7180/qupv3_uart.c | 11 +---------- src/soc/qualcomm/sc7180/soc.c | 12 +----------- src/soc/qualcomm/sc7180/spi.c | 12 +----------- src/soc/qualcomm/sc7180/timer.c | 12 +----------- src/soc/qualcomm/sc7180/uart_bitbang.c | 12 +----------- src/soc/qualcomm/sc7180/usb.c | 12 +----------- src/soc/qualcomm/sdm845/aop_load_reset.c | 12 +----------- src/soc/qualcomm/sdm845/bootblock.c | 12 +----------- src/soc/qualcomm/sdm845/cbmem.c | 12 +----------- src/soc/qualcomm/sdm845/clock.c | 12 +----------- src/soc/qualcomm/sdm845/include/soc/addressmap.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/aop.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/clock.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/efuse.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/gpio.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/memlayout.ld | 12 +----------- src/soc/qualcomm/sdm845/include/soc/mmu.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/qspi.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/symbols.h | 12 +----------- src/soc/qualcomm/sdm845/include/soc/usb.h | 12 +----------- src/soc/qualcomm/sdm845/mmu.c | 12 +----------- src/soc/qualcomm/sdm845/qclib.c | 12 +----------- src/soc/qualcomm/sdm845/qspi.c | 12 +----------- src/soc/qualcomm/sdm845/soc.c | 12 +----------- src/soc/qualcomm/sdm845/spi.c | 12 +----------- src/soc/qualcomm/sdm845/timer.c | 12 +----------- src/soc/qualcomm/sdm845/uart_bitbang.c | 12 +----------- src/soc/qualcomm/sdm845/usb.c | 12 +----------- src/soc/rockchip/rk3288/hdmi.c | 13 +------------ src/soc/rockchip/rk3288/include/soc/hdmi.h | 13 +------------ src/soc/samsung/exynos5420/dmc_init_ddr3.c | 13 +------------ src/soc/samsung/exynos5420/dp.c | 13 +------------ src/soc/samsung/exynos5420/dp_lowlevel.c | 13 +------------ src/soc/samsung/exynos5420/fimd.c | 13 +------------ src/southbridge/amd/agesa/hudson/smi.c | 13 +------------ src/southbridge/amd/agesa/hudson/smi.h | 13 +------------ src/southbridge/amd/agesa/hudson/smi_util.c | 13 +------------ src/southbridge/amd/agesa/hudson/smihandler.c | 13 +------------ src/southbridge/amd/pi/hudson/smi.c | 13 +------------ src/southbridge/amd/pi/hudson/smi.h | 13 +------------ src/southbridge/amd/pi/hudson/smi_util.c | 13 +------------ src/southbridge/amd/pi/hudson/smihandler.c | 13 +------------ src/southbridge/intel/common/finalize.h | 13 +------------ src/southbridge/intel/common/spi.c | 13 +------------ src/southbridge/intel/common/spi.h | 11 +---------- src/southbridge/intel/i82371eb/bootblock.c | 13 +------------ src/southbridge/intel/i82371eb/chip.h | 13 +------------ src/southbridge/intel/i82371eb/early_pm.c | 13 +------------ src/southbridge/intel/i82371eb/early_smbus.c | 13 +------------ src/southbridge/intel/i82371eb/i82371eb.c | 13 +------------ src/southbridge/intel/i82371eb/i82371eb.h | 13 +------------ src/southbridge/intel/i82371eb/ide.c | 13 +------------ src/southbridge/intel/i82371eb/isa.c | 13 +------------ src/southbridge/intel/i82371eb/smbus.c | 13 +------------ src/southbridge/intel/i82371eb/usb.c | 13 +------------ src/southbridge/intel/i82371eb/wakeup.c | 13 +------------ src/southbridge/intel/i82801gx/sata.h | 13 +------------ src/southbridge/intel/ibexpeak/early_thermal.c | 13 +------------ src/southbridge/ricoh/rl5c476/rl5c476.c | 13 +------------ src/southbridge/ricoh/rl5c476/rl5c476.h | 13 +------------ src/southbridge/ti/pci1x2x/pci1x2x.c | 13 +------------ src/southbridge/ti/pci7420/cardbus.c | 13 +------------ src/southbridge/ti/pci7420/chip.h | 13 +------------ src/southbridge/ti/pci7420/firewire.c | 13 +------------ src/southbridge/ti/pci7420/pci7420.h | 13 +------------ util/cbfstool/fdt.h | 12 +----------- util/ectool/ec.c | 11 +---------- util/ectool/ec.h | 12 +----------- util/ectool/ectool.c | 12 +----------- util/intelmetool/me.c | 13 +------------ util/intelmetool/me.h | 13 +------------ util/intelmetool/me_status.c | 13 +------------ util/intelmetool/mmap.c | 12 +----------- util/intelmetool/mmap.h | 13 +------------ util/intelmetool/msr.c | 12 +----------- util/intelmetool/msr.h | 13 +------------ util/intelmetool/rcba.c | 13 +------------ util/intelmetool/rcba.h | 13 +------------ util/inteltool/ahci.c | 13 +------------ .../hatch/template/include/variant/acpi/dptf.asl | 11 +---------- .../google/hatch/template/include/variant/ec.h | 11 +---------- .../google/hatch/template/include/variant/gpio.h | 11 +---------- util/msrtool/cs5536.c | 11 +---------- util/msrtool/darwin.c | 12 +----------- util/msrtool/freebsd.c | 12 +----------- util/msrtool/geodegx2.c | 12 +----------- util/msrtool/geodelx.c | 12 +----------- util/msrtool/intel_atom.c | 12 +----------- util/msrtool/intel_core1.c | 12 +----------- util/msrtool/intel_core2_early.c | 12 +----------- util/msrtool/intel_core2_later.c | 12 +----------- util/msrtool/intel_nehalem.c | 12 +----------- util/msrtool/intel_pentium3.c | 12 +----------- util/msrtool/intel_pentium3_early.c | 12 +----------- util/msrtool/intel_pentium4_early.c | 12 +----------- util/msrtool/intel_pentium4_later.c | 12 +----------- util/msrtool/intel_pentium_d.c | 12 +----------- util/msrtool/k8.c | 12 +----------- util/msrtool/linux.c | 12 +----------- util/msrtool/msrtool.c | 12 +----------- util/msrtool/msrtool.h | 12 +----------- util/msrtool/msrutils.c | 12 +----------- util/msrtool/sys.c | 12 +----------- util/msrtool/via_c7.c | 12 +----------- util/pgtblgen/pgtblgen.c | 12 +----------- util/vgabios/include/swab.h | 11 +---------- 568 files changed, 568 insertions(+), 6531 deletions(-) diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h index 30209092fd..7992178e98 100644 --- a/src/commonlib/include/commonlib/loglevel.h +++ b/src/commonlib/include/commonlib/loglevel.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef LOGLEVEL_H #define LOGLEVEL_H diff --git a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h index d681d2ecb2..a0b2e2b218 100644 --- a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h +++ b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Controller independent definitions */ diff --git a/src/commonlib/include/commonlib/sdhci.h b/src/commonlib/include/commonlib/sdhci.h index 2ce3e8a39f..cd76634360 100644 --- a/src/commonlib/include/commonlib/sdhci.h +++ b/src/commonlib/include/commonlib/sdhci.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SD host controller specific definitions */ diff --git a/src/commonlib/include/commonlib/storage.h b/src/commonlib/include/commonlib/storage.h index ce5f93acaa..673ae9f613 100644 --- a/src/commonlib/include/commonlib/storage.h +++ b/src/commonlib/include/commonlib/storage.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __COMMONLIB_STORAGE_H__ #define __COMMONLIB_STORAGE_H__ diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 722a6c8d0b..506c723089 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Generic bounce buffer implementation */ diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h index 615f73e2f6..bdfb9f8366 100644 --- a/src/commonlib/storage/bouncebuf.h +++ b/src/commonlib/storage/bouncebuf.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Generic bounce buffer implementation */ diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index d822865053..391b45c341 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * MultiMediaCard (MMC) and eMMC specific support code * This code is controller independent diff --git a/src/commonlib/storage/mmc.h b/src/commonlib/storage/mmc.h index 621c5414b1..aa1af0af33 100644 --- a/src/commonlib/storage/mmc.h +++ b/src/commonlib/storage/mmc.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __COMMONLIB_STORAGE_MMC_H__ #define __COMMONLIB_STORAGE_MMC_H__ diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index fbc73a8825..839fb34a01 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index a925088afa..5e74cd2e80 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Secure Digital (SD) card specific support code * This code is controller independent diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index 8c0c1f7e1d..07e8af8af8 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common initialization * code which brings the card into the standby state. This code is controller diff --git a/src/commonlib/storage/sd_mmc.h b/src/commonlib/storage/sd_mmc.h index 9ad2a9e52a..72e3ec313a 100644 --- a/src/commonlib/storage/sd_mmc.h +++ b/src/commonlib/storage/sd_mmc.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __COMMONLIB_STORAGE_SD_MMC_H__ #define __COMMONLIB_STORAGE_SD_MMC_H__ diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 231224c556..feef228497 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Secure Digital (SD) Host Controller interface specific code */ diff --git a/src/commonlib/storage/sdhci.h b/src/commonlib/storage/sdhci.h index ff0af13f19..61b2e013a6 100644 --- a/src/commonlib/storage/sdhci.h +++ b/src/commonlib/storage/sdhci.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __COMMONLIB_STORAGE_SDHCI_H__ #define __COMMONLIB_STORAGE_SDHCI_H__ diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 285ac0f1ec..786a57c512 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Secure Digital (SD) Host Controller interface DMA support code */ diff --git a/src/commonlib/storage/sdhci_display.c b/src/commonlib/storage/sdhci_display.c index 6dad33c36e..4d0300e53f 100644 --- a/src/commonlib/storage/sdhci_display.c +++ b/src/commonlib/storage/sdhci_display.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Secure Digital (SD) Host Controller interface specific code */ diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index 050d8bfb60..f5d1517cbf 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) common code which * transitions the card from the standby state to the transfer state. The diff --git a/src/commonlib/storage/storage.h b/src/commonlib/storage/storage.h index 67e21a40af..28f684de55 100644 --- a/src/commonlib/storage/storage.h +++ b/src/commonlib/storage/storage.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __COMMONLIB_STORAGE_STORAGE_H__ #define __COMMONLIB_STORAGE_STORAGE_H__ diff --git a/src/commonlib/storage/storage_erase.c b/src/commonlib/storage/storage_erase.c index 2425b765d6..4410687ea6 100644 --- a/src/commonlib/storage/storage_erase.c +++ b/src/commonlib/storage/storage_erase.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) erase support code. * This code is controller independent. diff --git a/src/commonlib/storage/storage_write.c b/src/commonlib/storage/storage_write.c index f5af6dc663..216c217202 100644 --- a/src/commonlib/storage/storage_write.c +++ b/src/commonlib/storage/storage_write.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * MultiMediaCard (MMC), eMMC and Secure Digital (SD) write support code. * This code is controller independent. diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c index f168356531..c11d1e69e9 100644 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ b/src/cpu/amd/agesa/family15tn/udelay.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * udelay() implementation for SMI handlers diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c index c70a8c180e..3a92dfe22c 100644 --- a/src/cpu/amd/pi/00630F01/udelay.c +++ b/src/cpu/amd/pi/00630F01/udelay.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * udelay() implementation for SMI handlers diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index ab783760a3..518d5813a0 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Intel Pentium L2 Cache initialization. diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c index e95b722172..e540548206 100644 --- a/src/cpu/intel/slot_1/slot_1.c +++ b/src/cpu/intel/slot_1/slot_1.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/cpu/qemu-power8/qemu.c b/src/cpu/qemu-power8/qemu.c index e617b86785..f3a2845eea 100644 --- a/src/cpu/qemu-power8/qemu.c +++ b/src/cpu/qemu-power8/qemu.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index 12b7c7911b..fb8cd6b71a 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/cpu/ti/am335x/clock.h b/src/cpu/ti/am335x/clock.h index f43fbe2447..cc9c5c3eaf 100644 --- a/src/cpu/ti/am335x/clock.h +++ b/src/cpu/ti/am335x/clock.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __CPU_TI_AM335X_CLOCK_H__ #define __CPU_TI_AM335X_CLOCK_H__ diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c index 5906a98d5d..b1bf782cbe 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/cpu/ti/am335x/gpio.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h index 84df942db4..a792e714de 100644 --- a/src/cpu/ti/am335x/gpio.h +++ b/src/cpu/ti/am335x/gpio.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __CPU_TI_AM335X_GPIO_H__ #define __CPU_TI_AM335X_GPIO_H__ diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 80cb88f134..3edf8b0415 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/cpu/ti/am335x/header.h b/src/cpu/ti/am335x/header.h index 814b27383f..a8e2599533 100644 --- a/src/cpu/ti/am335x/header.h +++ b/src/cpu/ti/am335x/header.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __CPU_TI_AM335X_HEADER_H #define __CPU_TI_AM335X_HEADER_H diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c index e1cc41980c..81ee5f9244 100644 --- a/src/cpu/ti/am335x/pinmux.c +++ b/src/cpu/ti/am335x/pinmux.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "pinmux.h" diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index 94f189f370..9c905d4131 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __CPU_TI_AM335X_PINMUX_H #define __CPU_TI_AM335X_PINMUX_H diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index e7e9141ff9..9b7e2aaee3 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index 686040f29a..ce6ebdea7a 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef AM335X_UART_H #define AM335X_UART_H diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 93c1b49e4c..cbf4de7479 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * input %esp: return address (not pointer to return address!) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 12200f7f08..db108d792a 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file ddr2.c diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 7eaf960285..a2fc617799 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file ddr3.c diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h index 72ef4e7ae7..1d8bdb9834 100644 --- a/src/drivers/aspeed/common/aspeed_coreboot.h +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _ASPEED_COREBOOT_ #define _ASPEED_COREBOOT_ diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index d718597696..0721d86d40 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index a58d7610bd..99f41b15f9 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 199b6a829a..fd8732efeb 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 72431e2fd5..c1b5cb5e76 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation, version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* Based on Linux Kernel TPM driver */ diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index de4116774d..a7004a82e3 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 82f21ca800..161cb4501e 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 2917b45cb9..0f097fffa4 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation, version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Description: diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h index c1ed3f0afb..55792a5547 100644 --- a/src/drivers/i2c/tpm/tpm.h +++ b/src/drivers/i2c/tpm/tpm.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation, version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Description: diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index a7b20bf24f..ed01f93842 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This is a driver for the Whirlwind LED ring, which is equipped with two LED diff --git a/src/drivers/i2c/ww_ring/ww_ring.h b/src/drivers/i2c/ww_ring/ww_ring.h index f17f5e39b8..8e1b312310 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.h +++ b/src/drivers/i2c/ww_ring/ww_ring.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SRC_DRIVERS_VIDEO_WW_RING__H__ #define __SRC_DRIVERS_VIDEO_WW_RING__H__ diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 2283fb94dd..5cb371c56f 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This is a driver for the Whirlwind LED ring, which is equipped with two LED diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index ea0e241f5c..b5562cc46d 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This is a driver for the Whirlwind LED ring, which is equipped with two LED diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index e7a163f315..7fcbda1a46 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index d05b09f7f2..f4c9996f7f 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 183487ddd6..0391b861db 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index abb99c1c5c..19f4998777 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 69eaed2aa4..d962a84894 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 36a4eea16c..b0adbfea7d 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 239d387f5d..126dc701ab 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _FSP2_0_API_H_ #define _FSP2_0_API_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 0409bbfc27..9dde8c654f 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _FSP2_0_DEBUG_H_ #define _FSP2_0_DEBUG_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 3b737309de..2fff273e1b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _FSP2_0_INFO_HEADER_H_ #define _FSP2_0_INFO_HEADER_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 34c3d958a3..bf0a9681ad 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _FSP2_0_UPD_H_ #define _FSP2_0_UPD_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index c8dfd8e6d5..e98aaf6697 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _FSP2_0_UTIL_H_ #define _FSP2_0_UTIL_H_ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 5af3842095..71441c28fd 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index d18d7378b0..9473772032 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 07b202468b..32e7fa2d8e 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index c4f60b113c..d9e4fa8ad8 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index 4afc7f9f87..4f97490865 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 1d845be374..6e4bb2a53b 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 796f4df4dd..39f4e5d7cc 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2, or (at your option) - * any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index bc1b296c16..cc68ab9336 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2, or (at your option) - * any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index dd1beabb98..0c5d30a058 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _COMMON_GMA_H_ #define _COMMON_GMA_H_ diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index a4b1c289a7..3dfe282818 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or (at your option) - * any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index dffb207129..9aeda87aad 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or (at your option) - * any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 390df3706f..71c171e34a 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ int drivers_lenovo_is_wacom_present(void); void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 5a07d27ed7..238f754281 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2, or (at your - * option) any later version, of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index 5b24187c6e..9acb459207 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h index 74e03f8230..25b7f49cb3 100644 --- a/src/drivers/maxim/max77686/max77686.h +++ b/src/drivers/maxim/max77686/max77686.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAX77686_H_ #define __MAX77686_H_ diff --git a/src/drivers/maxim/max77802/max77802.h b/src/drivers/maxim/max77802/max77802.h index 85e385e7bf..f8bb631d71 100644 --- a/src/drivers/maxim/max77802/max77802.h +++ b/src/drivers/maxim/max77802/max77802.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAX77802_H_ #define __MAX77802_H_ diff --git a/src/drivers/pc80/pc/spkmodem.c b/src/drivers/pc80/pc/spkmodem.c index 4dd5972c4b..ee3175767f 100644 --- a/src/drivers/pc80/pc/spkmodem.c +++ b/src/drivers/pc80/pc/spkmodem.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/pc80/vga/vga_palette.c b/src/drivers/pc80/vga/vga_palette.c index 2e58a55a9f..19e76511a0 100644 --- a/src/drivers/pc80/vga/vga_palette.c +++ b/src/drivers/pc80/vga/vga_palette.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "vga.h" diff --git a/src/drivers/secunet/dmi/eeprom.h b/src/drivers/secunet/dmi/eeprom.h index c4cdd4142e..602af40882 100644 --- a/src/drivers/secunet/dmi/eeprom.h +++ b/src/drivers/secunet/dmi/eeprom.h @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SECUNET_DMI_EEPROM_H #define _SECUNET_DMI_EEPROM_H diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index eb09fe52e4..958d2ddd42 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Driver for Adesto Technologies SPI flash diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index b0198b3a48..5de89ab7c6 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 6feda6ecc3..70a4635fce 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index f5923c3354..f2f16271ad 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index ccc8eba72f..6924c18ab8 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 12f8679e97..69e3e080f8 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 9d5f559e92..7818ec7813 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 4ce29ed33d..90e97b8764 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index eb19860c76..d9362190fe 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index e5884a474e..a53ca7bd8a 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SPI flash internal definitions diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index f48d107a15..b02061c06d 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Driver for SST serial flashes diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 464d366fa0..0482972d1b 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index b146984bb5..278e64d8b0 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 682a334889..936114a2eb 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index e4b6f330e8..d3b0a529bc 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or (at your option) - * any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index bfc5dd594e..e12bd78bdf 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Portions marked below taken from XGI/SiS Linux kernel drivers */ diff --git a/src/ec/google/chromeec/ec_message.h b/src/ec/google/chromeec/ec_message.h index f0eab2f185..f074ae8a27 100644 --- a/src/ec/google/chromeec/ec_message.h +++ b/src/ec/google/chromeec/ec_message.h @@ -1,17 +1,7 @@ /* * Chromium OS Matrix Keyboard Message Protocol definitions */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _CROS_MESSAGE_H #define _CROS_MESSAGE_H diff --git a/src/include/b64_decode.h b/src/include/b64_decode.h index 0deb7aae31..34e0e5ac85 100644 --- a/src/include/b64_decode.h +++ b/src/include/b64_decode.h @@ -1,13 +1,4 @@ -/* - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __INCLUDE_B64_DECODE_H__ #define __INCLUDE_B64_DECODE_H__ diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 416d487eef..77f3b0ae4e 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file post_codes.h diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index c253f880da..8322a86f85 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* The L2 cache definitions here only apply to SECC/SECC2 P6 family CPUs * with Klamath (63x), Deschutes (65x) and Katmai (67x) cores. diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index 32cdc79de1..67d968bd91 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef DEVICE_DRAM_COMMON_H #define DEVICE_DRAM_COMMON_H diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index f83965971b..408075f14c 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * JEDEC Standard No. 21-C diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 2ded8a8fdb..2eba3f35d3 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * JEDEC Standard No. 21-C diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 0de9dba21a..bd0d151508 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -1,15 +1,5 @@ /* Taken from depthcharge: src/base/device_tree.h */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __DEVICE_TREE_H__ #define __DEVICE_TREE_H__ diff --git a/src/include/dimm_info_util.h b/src/include/dimm_info_util.h index 48fff6ceb2..4622c1f81f 100644 --- a/src/include/dimm_info_util.h +++ b/src/include/dimm_info_util.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version - * 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _DIMM_INFO_UTIL_H_ #define _DIMM_INFO_UTIL_H_ diff --git a/src/include/endian.h b/src/include/endian.h index a1c7f6a89b..552ce0025e 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _ENDIAN_H_ #define _ENDIAN_H_ diff --git a/src/include/fit.h b/src/include/fit.h index beec38ae6a..a1e970d502 100644 --- a/src/include/fit.h +++ b/src/include/fit.h @@ -1,15 +1,5 @@ /* Taken from depthcharge: src/boot/fit.h */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __LIB_FIT_H__ #define __LIB_FIT_H__ diff --git a/src/include/fit_payload.h b/src/include/fit_payload.h index 657c7d57f3..8632b05b82 100644 --- a/src/include/fit_payload.h +++ b/src/include/fit_payload.h @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __FIT_PAYLOAD_H_ #define __FIT_PAYLOAD_H_ diff --git a/src/include/list.h b/src/include/list.h index 9706080713..a8990354d7 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -1,15 +1,5 @@ /* Taken from depthcharge: src/base/list.h */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __LIST_H__ #define __LIST_H__ diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 03b4fdc738..a9891189d2 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -1,14 +1,5 @@ /* Memory information */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version - * 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _MEMORY_INFO_H_ #define _MEMORY_INFO_H_ diff --git a/src/include/pc80/vga.h b/src/include/pc80/vga.h index ea47368936..e6aed868db 100644 --- a/src/include/pc80/vga.h +++ b/src/include/pc80/vga.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VGA_H #define VGA_H diff --git a/src/include/pc80/vga_io.h b/src/include/pc80/vga_io.h index 3cfba1b2fb..79cc58118f 100644 --- a/src/include/pc80/vga_io.h +++ b/src/include/pc80/vga_io.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VGA_IO_H #define VGA_IO_H diff --git a/src/include/sdram_mode.h b/src/include/sdram_mode.h index 5dadaee3a0..31c62624a1 100644 --- a/src/include/sdram_mode.h +++ b/src/include/sdram_mode.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register diff --git a/src/include/spd.h b/src/include/spd.h index cacb20517c..0d67502144 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Serial Presence Detect (SPD) data stored on SDRAM modules. diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index a57ec907d5..77a3c09a79 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SPI_GENERIC_H_ #define _SPI_GENERIC_H_ diff --git a/src/include/spi_bitbang.h b/src/include/spi_bitbang.h index 4691fd21ec..4dd560eb33 100644 --- a/src/include/spi_bitbang.h +++ b/src/include/spi_bitbang.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SPI_BITBANG_H_ #define _SPI_BITBANG_H_ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 5dce7206ab..9d0e3ad08c 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -1,14 +1,5 @@ /* Interface to SPI flash */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SPI_FLASH_H_ #define _SPI_FLASH_H_ diff --git a/src/lib/b64_decode.c b/src/lib/b64_decode.c index 57c883870e..b4dd3f8c0a 100644 --- a/src/lib/b64_decode.c +++ b/src/lib/b64_decode.c @@ -1,13 +1,4 @@ -/* - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 2124edd582..cb81d3248c 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -1,15 +1,5 @@ /* Taken from depthcharge: src/base/device_tree.c */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/lib/fit.c b/src/lib/fit.c index be6c87a936..90cbfcacee 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -1,15 +1,5 @@ /* Taken from depthcharge: src/boot/fit.c */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 95f3b93f91..90446c1481 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/lib/list.c b/src/lib/list.c index 9138ab30cd..01d5c8914e 100644 --- a/src/lib/list.c +++ b/src/lib/list.c @@ -1,15 +1,5 @@ /* Taken from depthcharge: src/base/list.c */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/amd/padmelon/hda_verb.c b/src/mainboard/amd/padmelon/hda_verb.c index 4e1418c0a6..de192a393a 100644 --- a/src/mainboard/amd/padmelon/hda_verb.c +++ b/src/mainboard/amd/padmelon/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index cfd6e0bef3..a7e1138931 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License, - * or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asrock/b75pro3-m/mainboard.c b/src/mainboard/asrock/b75pro3-m/mainboard.c index ef929669f3..53ca822c09 100644 --- a/src/mainboard/asrock/b75pro3-m/mainboard.c +++ b/src/mainboard/asrock/b75pro3-m/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asrock/g41c-gs/early_init.c b/src/mainboard/asrock/g41c-gs/early_init.c index 88fe3fb090..9f811a430e 100644 --- a/src/mainboard/asrock/g41c-gs/early_init.c +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c index 661f6c45ef..33b1027ab7 100644 --- a/src/mainboard/asrock/g41c-gs/hda_verb.c +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asrock/h110m/mainboard.c b/src/mainboard/asrock/h110m/mainboard.c index 01b70e0fad..fe670efe47 100644 --- a/src/mainboard/asrock/h110m/mainboard.c +++ b/src/mainboard/asrock/h110m/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asrock/h81m-hds/acpi/platform.asl b/src/mainboard/asrock/h81m-hds/acpi/platform.asl index 81591d6ece..2238209f21 100644 --- a/src/mainboard/asrock/h81m-hds/acpi/platform.asl +++ b/src/mainboard/asrock/h81m-hds/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK, 1) { diff --git a/src/mainboard/asrock/h81m-hds/acpi/superio.asl b/src/mainboard/asrock/h81m-hds/acpi/superio.asl index 43ab19a9e1..8cb29eacad 100644 --- a/src/mainboard/asrock/h81m-hds/acpi/superio.asl +++ b/src/mainboard/asrock/h81m-hds/acpi/superio.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x2e diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c index 4c600616b4..b40bb95725 100644 --- a/src/mainboard/asrock/h81m-hds/acpi_tables.c +++ b/src/mainboard/asrock/h81m-hds/acpi_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 9e40cfc043..e8335d54a9 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( diff --git a/src/mainboard/asrock/h81m-hds/gpio.c b/src/mainboard/asrock/h81m-hds/gpio.c index 6610ab1dfa..85277661ef 100644 --- a/src/mainboard/asrock/h81m-hds/gpio.c +++ b/src/mainboard/asrock/h81m-hds/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asrock/h81m-hds/hda_verb.c b/src/mainboard/asrock/h81m-hds/hda_verb.c index a07ca8c5dc..8ac0e7e651 100644 --- a/src/mainboard/asrock/h81m-hds/hda_verb.c +++ b/src/mainboard/asrock/h81m-hds/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asrock/h81m-hds/mainboard.c b/src/mainboard/asrock/h81m-hds/mainboard.c index 01b70e0fad..fe670efe47 100644 --- a/src/mainboard/asrock/h81m-hds/mainboard.c +++ b/src/mainboard/asrock/h81m-hds/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/h61m-cs/acpi/platform.asl b/src/mainboard/asus/h61m-cs/acpi/platform.asl index 89f8f7362a..17460c7082 100644 --- a/src/mainboard/asus/h61m-cs/acpi/platform.asl +++ b/src/mainboard/asus/h61m-cs/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK,1) { diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index b8e4df30f3..cabf179029 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl index 81591d6ece..2238209f21 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK, 1) { diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl index a6fe5a788c..490e449e89 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl @@ -1,15 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c index f97249d9e4..66cd5fcdd4 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index eec65b8bf5..9e787cedb8 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index aae5ee60e3..e71f2336f4 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/maximus_iv_gene-z/gpio.c b/src/mainboard/asus/maximus_iv_gene-z/gpio.c index 4b8462ddad..ad567baf47 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/gpio.c +++ b/src/mainboard/asus/maximus_iv_gene-z/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c index 0fd8d7862d..c41035acc9 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c +++ b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/maximus_iv_gene-z/mainboard.c b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c index 01b70e0fad..fe670efe47 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/mainboard.c +++ b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c index 8822035ce2..29442c845a 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c index 2c7ac6023e..463ca6cc00 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c index 84cd1373a0..7d2c567ae1 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c index 0c09233e87..bd1891defa 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c index eab90868f5..4bd2c982cd 100644 --- a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c index d4b9272d68..04b6ed2a6d 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c index d0360d9c90..578ee093e1 100644 --- a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index 5c10ec4be8..c0c5aa25da 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 56f5253905..475da286d0 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p5qc/early_init.c b/src/mainboard/asus/p5qc/early_init.c index 5b0539d4a2..bab5b1c16a 100644 --- a/src/mainboard/asus/p5qc/early_init.c +++ b/src/mainboard/asus/p5qc/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c index b7607499b0..cec9bd5eb2 100644 --- a/src/mainboard/asus/p5qc/hda_verb.c +++ b/src/mainboard/asus/p5qc/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p5ql-em/early_init.c b/src/mainboard/asus/p5ql-em/early_init.c index 4585a98456..99a0f6ecc1 100644 --- a/src/mainboard/asus/p5ql-em/early_init.c +++ b/src/mainboard/asus/p5ql-em/early_init.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c index 8dbf431f13..5178d3fd1c 100644 --- a/src/mainboard/asus/p5ql-em/hda_verb.c +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p5qpl-am/early_init.c b/src/mainboard/asus/p5qpl-am/early_init.c index 5556536e6b..66efd527e4 100644 --- a/src/mainboard/asus/p5qpl-am/early_init.c +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c index cca113c8a9..126c5560b5 100644 --- a/src/mainboard/asus/p5qpl-am/hda_verb.c +++ b/src/mainboard/asus/p5qpl-am/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl index 81591d6ece..2238209f21 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl +++ b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK, 1) { diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl index 43ab19a9e1..8cb29eacad 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl +++ b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x2e diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c index f97249d9e4..66cd5fcdd4 100644 --- a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index eec65b8bf5..9e787cedb8 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( diff --git a/src/mainboard/asus/p8h61-m_lx/early_init.c b/src/mainboard/asus/p8h61-m_lx/early_init.c index 4021781d10..970b8e96aa 100644 --- a/src/mainboard/asus/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/p8h61-m_lx/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p8h61-m_lx/gpio.c b/src/mainboard/asus/p8h61-m_lx/gpio.c index e02359f1d2..6bcab020b6 100644 --- a/src/mainboard/asus/p8h61-m_lx/gpio.c +++ b/src/mainboard/asus/p8h61-m_lx/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/p8h61-m_lx/hda_verb.c index 417ae1b720..d99291e427 100644 --- a/src/mainboard/asus/p8h61-m_lx/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_lx/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p8h61-m_lx/mainboard.c b/src/mainboard/asus/p8h61-m_lx/mainboard.c index 01b70e0fad..fe670efe47 100644 --- a/src/mainboard/asus/p8h61-m_lx/mainboard.c +++ b/src/mainboard/asus/p8h61-m_lx/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl b/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl index a6fe5a788c..490e449e89 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl +++ b/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl @@ -1,15 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl index 89f8f7362a..17460c7082 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl +++ b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK,1) { diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl index a6fe5a788c..490e449e89 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl +++ b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl @@ -1,15 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c index 3f69f12f9a..65b59e8fda 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c index b4f09f971a..29c79a98c8 100644 --- a/src/mainboard/biostar/am1ml/irq_tables.c +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index b7d339725b..f591410f41 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or, at your option, any later - * version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index d089898f5d..d4aae59943 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * These are the qemu firmware config interface defines and structs. diff --git a/src/mainboard/foxconn/d41s/early_init.c b/src/mainboard/foxconn/d41s/early_init.c index c31860db80..ba0b7ee994 100644 --- a/src/mainboard/foxconn/d41s/early_init.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/foxconn/g41s-k/early_init.c b/src/mainboard/foxconn/g41s-k/early_init.c index 731f622dc7..3b412322b7 100644 --- a/src/mainboard/foxconn/g41s-k/early_init.c +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c index 98bce49e6b..08cff2ff3c 100644 --- a/src/mainboard/foxconn/g41s-k/hda_verb.c +++ b/src/mainboard/foxconn/g41s-k/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl index ac6fcbe3f6..9410dd737c 100644 --- a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. -m * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This is board specific information: diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index 476a1aa7a4..f343bb7bca 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c index bea28ed05a..86339d38fd 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h index 528096f59e..62d176e52f 100644 --- a/src/mainboard/google/cheza/board.h +++ b/src/mainboard/google/cheza/board.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H #define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c index b6f99126c1..f056fc4877 100644 --- a/src/mainboard/google/cheza/bootblock.c +++ b/src/mainboard/google/cheza/bootblock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include "board.h" diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 227370cbdd..12ee07f04c 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 1e3803443e..601cff1597 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld index 6bb1739fe6..24c698faff 100644 --- a/src/mainboard/google/cheza/memlayout.ld +++ b/src/mainboard/google/cheza/memlayout.ld @@ -1,14 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index bcb65d5d08..0ca987c285 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/gale/bootblock.c b/src/mainboard/google/gale/bootblock.c index d919839401..343fe65784 100644 --- a/src/mainboard/google/gale/bootblock.c +++ b/src/mainboard/google/gale/bootblock.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index 94c5fa6e86..3b9917c9a9 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/gale/mmu.h b/src/mainboard/google/gale/mmu.h index a07e4bc784..8f6b547f19 100644 --- a/src/mainboard/google/gale/mmu.h +++ b/src/mainboard/google/gale/mmu.h @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index bbf5d68a99..302ef4f6a8 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 34354ae05f..ce0d0c3fb8 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 63095dede3..f85353086a 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/mistral/memlayout.ld b/src/mainboard/google/mistral/memlayout.ld index 6cd2717891..e2e5f15929 100644 --- a/src/mainboard/google/mistral/memlayout.ld +++ b/src/mainboard/google/mistral/memlayout.ld @@ -1,14 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 1dc7c6c14c..1da791b483 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/storm/bootblock.c b/src/mainboard/google/storm/bootblock.c index 186673c4af..e7ff6a3ee3 100644 --- a/src/mainboard/google/storm/bootblock.c +++ b/src/mainboard/google/storm/bootblock.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 8d0a166cd3..37b4654b1b 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/storm/mmu.h b/src/mainboard/google/storm/mmu.h index 1bf7e4f5fa..49f3b48e48 100644 --- a/src/mainboard/google/storm/mmu.h +++ b/src/mainboard/google/storm/mmu.h @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index aef11d603a..8d03551c4a 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ #define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c index b6f99126c1..f056fc4877 100644 --- a/src/mainboard/google/trogdor/bootblock.c +++ b/src/mainboard/google/trogdor/bootblock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include "board.h" diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 227370cbdd..12ee07f04c 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 61fb19093e..9da62bba84 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/google/trogdor/memlayout.ld b/src/mainboard/google/trogdor/memlayout.ld index 6cd2717891..e2e5f15929 100644 --- a/src/mainboard/google/trogdor/memlayout.ld +++ b/src/mainboard/google/trogdor/memlayout.ld @@ -1,14 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 226546ad68..cf3e08a031 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl index 3dc2ef2cdd..0c112614a2 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Defines EC bits specific to the mainboard, needed by EC ASL */ #include "mainboard.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.c b/src/mainboard/hp/pavilion_m6_1035dx/ec.c index 3dd7f9aad3..50f5dd384a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "ec.h" #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index aab96f4cd1..b8920be1c4 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H #define _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h index 6ff3c1e225..07074e6380 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * "The way things are connected" and a few setup options diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index 0e23b1db70..5a79d36867 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SMI handler -- mostly takes care of SMIs from the EC diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 648e9f9e05..e63de17d65 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index 7d625c15de..328087440b 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/intel/d510mo/early_init.c b/src/mainboard/intel/d510mo/early_init.c index 29f00b35de..2f07a7033e 100644 --- a/src/mainboard/intel/d510mo/early_init.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/intel/dg41wv/early_init.c b/src/mainboard/intel/dg41wv/early_init.c index 035ad9b435..342adf4aac 100644 --- a/src/mainboard/intel/dg41wv/early_init.c +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/intel/dg41wv/hda_verb.c b/src/mainboard/intel/dg41wv/hda_verb.c index 4e1418c0a6..de192a393a 100644 --- a/src/mainboard/intel/dg41wv/hda_verb.c +++ b/src/mainboard/intel/dg41wv/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/intel/dg43gt/early_init.c b/src/mainboard/intel/dg43gt/early_init.c index fbec787342..cb93ed8af1 100644 --- a/src/mainboard/intel/dg43gt/early_init.c +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/intel/dg43gt/hda_verb.c b/src/mainboard/intel/dg43gt/hda_verb.c index a7bd2799ba..ba95df7b15 100644 --- a/src/mainboard/intel/dg43gt/hda_verb.c +++ b/src/mainboard/intel/dg43gt/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index b0f8ae207b..4a7f424cd2 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index 4331805749..f01e2c8268 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "harcuvar_boardid.h" #include "gpio.h" diff --git a/src/mainboard/lenovo/g505s/acpi/ec.asl b/src/mainboard/lenovo/g505s/acpi/ec.asl index 3dc2ef2cdd..0c112614a2 100644 --- a/src/mainboard/lenovo/g505s/acpi/ec.asl +++ b/src/mainboard/lenovo/g505s/acpi/ec.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Defines EC bits specific to the mainboard, needed by EC ASL */ #include "mainboard.h" diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl index 85a0894fdd..264c0932d8 100644 --- a/src/mainboard/lenovo/g505s/acpi/superio.asl +++ b/src/mainboard/lenovo/g505s/acpi/superio.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Defines EC bits specific to the mainboard, needed by EC ASL */ #include "mainboard.h" diff --git a/src/mainboard/lenovo/g505s/ec.c b/src/mainboard/lenovo/g505s/ec.c index 9ddccb839d..2a723901d9 100644 --- a/src/mainboard/lenovo/g505s/ec.c +++ b/src/mainboard/lenovo/g505s/ec.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "ec.h" #include diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index f615fccf69..dadb971fd2 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _MAINBOARD_LENOVO_G505S_EC_H #define _MAINBOARD_LENOVO_G505S_EC_H diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h index 02ddb279c6..6646b6219b 100644 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * "The way things are connected" and a few setup options diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/mainboard_smi.c index 0e23b1db70..5a79d36867 100644 --- a/src/mainboard/lenovo/g505s/mainboard_smi.c +++ b/src/mainboard/lenovo/g505s/mainboard_smi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SMI handler -- mostly takes care of SMIs from the EC diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index 836b2d8234..dfb7e8f39e 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _MAINBOARD_LENOVO_S230U_EC_H #define _MAINBOARD_LENOVO_S230U_EC_H diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 828a13ff41..d1d3654bf0 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License, - * or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/t440p/acpi/ec.asl b/src/mainboard/lenovo/t440p/acpi/ec.asl index 3dbe6fe882..8b7af641af 100644 --- a/src/mainboard/lenovo/t440p/acpi/ec.asl +++ b/src/mainboard/lenovo/t440p/acpi/ec.asl @@ -1,15 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/t440p/acpi/platform.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl index a2c2e002f9..79be356051 100644 --- a/src/mainboard/lenovo/t440p/acpi/platform.asl +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK,1) { diff --git a/src/mainboard/lenovo/t440p/acpi/superio.asl b/src/mainboard/lenovo/t440p/acpi/superio.asl index a6fe5a788c..490e449e89 100644 --- a/src/mainboard/lenovo/t440p/acpi/superio.asl +++ b/src/mainboard/lenovo/t440p/acpi/superio.asl @@ -1,15 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 718cad1dab..c59c119e56 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB diff --git a/src/mainboard/lenovo/t440p/mainboard.c b/src/mainboard/lenovo/t440p/mainboard.c index 31552b8407..27d4abb527 100644 --- a/src/mainboard/lenovo/t440p/mainboard.c +++ b/src/mainboard/lenovo/t440p/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/lenovo/thinkcentre_a58/early_init.c b/src/mainboard/lenovo/thinkcentre_a58/early_init.c index 70d70f7880..1ab26859a6 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/early_init.c +++ b/src/mainboard/lenovo/thinkcentre_a58/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c index 6074f5f350..357de1e192 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c +++ b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c index fa01ebf8e8..a8e9b3890b 100644 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ b/src/mainboard/lenovo/x201/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License, - * or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/msi/ms7707/acpi/platform.asl b/src/mainboard/msi/ms7707/acpi/platform.asl index 89f8f7362a..17460c7082 100644 --- a/src/mainboard/msi/ms7707/acpi/platform.asl +++ b/src/mainboard/msi/ms7707/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK,1) { diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 7432de8311..7a4e8c5eee 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl index 312ae70ff8..ec6772b322 100644 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Enable ACPI _SWS methods */ #include diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index fe52ea1e9b..f2386acaca 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c index 1036b02008..a440e0df20 100644 --- a/src/mainboard/ocp/tiogapass/fadt.c +++ b/src/mainboard/ocp/tiogapass/fadt.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h index b43260fc27..b81a8f8a15 100644 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SKXSP_TP_IIO_H_ #define _SKXSP_TP_IIO_H_ diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 27d2a17509..0a32b722e2 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 3af6a2e9ed..597475d1a3 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/packardbell/ms2290/hda_verb.c b/src/mainboard/packardbell/ms2290/hda_verb.c index 8121f874cb..1697cded54 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.c +++ b/src/mainboard/packardbell/ms2290/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License, - * or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c index 436930a83b..cdc3d9962a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 9e704c870f..0a05ca28a7 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index 39ca7e781a..5f6e266c0c 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c index c4d456d308..9841c38f04 100644 --- a/src/mainboard/sapphire/pureplatinumh61/gpio.c +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c index c0467950f6..2e851d96f0 100644 --- a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c index 290c55fb25..371c525b5b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/mainboard.c +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c index c02a7b9bb9..9fbbc3821e 100644 --- a/src/mainboard/scaleway/tagada/romstage.c +++ b/src/mainboard/scaleway/tagada/romstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "gpio.h" #include diff --git a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl index 81591d6ece..2238209f21 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl +++ b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Method(_WAK, 1) { diff --git a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl index 0c9f46b78c..318b6bf73a 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl +++ b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x2e diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c index 4c600616b4..b40bb95725 100644 --- a/src/mainboard/supermicro/x10slm-f/acpi_tables.c +++ b/src/mainboard/supermicro/x10slm-f/acpi_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm-f/bootblock.c index ff09a11726..8019ecb2b0 100644 --- a/src/mainboard/supermicro/x10slm-f/bootblock.c +++ b/src/mainboard/supermicro/x10slm-f/bootblock.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 96e6227ce7..f3a3bebffc 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/supermicro/x10slm-f/gpio.c b/src/mainboard/supermicro/x10slm-f/gpio.c index 8758fab19f..deaad67f03 100644 --- a/src/mainboard/supermicro/x10slm-f/gpio.c +++ b/src/mainboard/supermicro/x10slm-f/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm-f/hda_verb.c index 35c420ca68..72b34e3a59 100644 --- a/src/mainboard/supermicro/x10slm-f/hda_verb.c +++ b/src/mainboard/supermicro/x10slm-f/hda_verb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index 27d9ec7594..1380cd16cf 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index abad71867a..99ae6d934a 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/ti/beaglebone/leds.h b/src/mainboard/ti/beaglebone/leds.h index 6a2d3ecb76..49404f66d6 100644 --- a/src/mainboard/ti/beaglebone/leds.h +++ b/src/mainboard/ti/beaglebone/leds.h @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ #define __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 574801c15f..fe80bfd87c 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * e7505.h: PCI configuration space for the Intel E7501 memory controller diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index daaa96a9cc..33b225659e 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/ironlake/raminit_tables.c b/src/northbridge/intel/ironlake/raminit_tables.c index 3abd4c0a01..721e00b916 100644 --- a/src/northbridge/intel/ironlake/raminit_tables.c +++ b/src/northbridge/intel/ironlake/raminit_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "raminit_tables.h" diff --git a/src/northbridge/intel/ironlake/raminit_tables.h b/src/northbridge/intel/ironlake/raminit_tables.h index 05a8c35f6c..822cb198f2 100644 --- a/src/northbridge/intel/ironlake/raminit_tables.h +++ b/src/northbridge/intel/ironlake/raminit_tables.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef RAMINIT_TABLES_H #define RAMINIT_TABLES_H diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 588f0fac86..9c0b46e2b6 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h index 310a575d9c..e7472b43a9 100644 --- a/src/northbridge/intel/pineview/iomap.h +++ b/src/northbridge/intel/pineview/iomap.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef PINEVIEW_IOMAP_H #define PINEVIEW_IOMAP_H diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 92bca75fdf..df4232a759 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H #define NORTHBRIDGE_INTEL_PINEVIEW_H diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 081d1ee86d..1e1170d4f3 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h index 2662d1905e..3d52117913 100644 --- a/src/northbridge/intel/pineview/raminit.h +++ b/src/northbridge/intel/pineview/raminit.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef PINEVIEW_RAMINIT_H #define PINEVIEW_RAMINIT_H diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 7ee3fdb284..61d987b338 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/x4x/chip.h b/src/northbridge/intel/x4x/chip.h index 4b853b6943..7d40d209a1 100644 --- a/src/northbridge/intel/x4x/chip.h +++ b/src/northbridge/intel/x4x/chip.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef NORTHBRIDGE_INTEL_X4X_CHIP_H #define NORTHBRIDGE_INTEL_X4X_CHIP_H diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index bd4a4d6ff0..82f4acd4b6 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h index c2d48a73da..06eb7462c3 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/iomap.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef X4X_IOMAP_H #define X4X_IOMAP_H diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 817b789036..90d8a449bf 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 81e6395846..e0ce3404df 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index f9ab7dfc57..1f8e97fba9 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include "x4x.h" diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index e466eeb4cf..3b59df2038 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index e35606617a..aebec25bdb 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index eb8040c3ab..342ca6f97f 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 5b4a82a216..43258d8693 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * NOTE: The layout of the GNVS structure below must match the layout in diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 422bf2d021..d1af398f82 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl index f46941795b..04fa3135d5 100644 --- a/src/soc/intel/apollolake/acpi/lpss.asl +++ b/src/soc/intel/apollolake/acpi/lpss.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ scope (\_SB.PCI0) { diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 3148ac6e13..2cedbd389c 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Name(_HID, EISAID("PNP0A08")) /* PCIe */ diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index 0373e97f45..28c751109d 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "soc_int.asl" diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index e608aa87a9..cf937aa189 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_INT_DEFINE_ASL_ #define _SOC_INT_DEFINE_ASL_ diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 7d0c94c34a..abb89ed70a 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl index c8bd339c6b..cb4caf0910 100644 --- a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl +++ b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* USB2 */ Device (HS01) { Name (_ADR, 1) } diff --git a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl index 6692b17af7..8806b41d94 100644 --- a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl +++ b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* USB2 */ Device (HS01) { Name (_ADR, 1) } diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index b389813519..a75d2e1bb9 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index c213461c55..384b441635 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 7e303c712a..1048bf915c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 3efd97004a..a6a4a002bb 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 4484413e61..739990d8d8 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index a9e4ed2646..08b4ffd87c 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index 4a377820de..d70f3e2ebf 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index d895018409..c6fd8cc269 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index aff4c38fba..cf815e1444 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c index 80934f97b6..c62be58866 100644 --- a/src/soc/intel/apollolake/gspi.c +++ b/src/soc/intel/apollolake/gspi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/heci.c b/src/soc/intel/apollolake/heci.c index 8dad3a3d54..e500d318bc 100644 --- a/src/soc/intel/apollolake/heci.c +++ b/src/soc/intel/apollolake/heci.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 332d26a0f4..50a3413b0a 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 06fc29ecba..2ce615dfd3 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APL_GPIO_H_ #define _SOC_APL_GPIO_H_ diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h index 41f4dabece..845128fd08 100644 --- a/src/soc/intel/apollolake/include/soc/heci.h +++ b/src/soc/intel/apollolake/include/soc/heci.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_HECI_H_ #define _SOC_APOLLOLAKE_HECI_H_ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index f254f01f05..3426d8b541 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_IOMAP_H_ #define _SOC_APOLLOLAKE_IOMAP_H_ diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h index c578c588ad..1d4caa2c1a 100644 --- a/src/soc/intel/apollolake/include/soc/nhlt.h +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_NHLT_H_ #define _SOC_APOLLOLAKE_NHLT_H_ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index cc97bb15ce..78c82ebd80 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * NOTE: The layout of the global_nvs_t structure below must match the layout diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 8cb56b64cd..c908212128 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_ #define _SOC_APOLLOLAKE_PCI_DEVS_H_ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 72a149652d..42d599e7cc 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_PM_H_ #define _SOC_APOLLOLAKE_PM_H_ diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h index 38839f3342..f4c3def31f 100644 --- a/src/soc/intel/apollolake/include/soc/ramstage.h +++ b/src/soc/intel/apollolake/include/soc/ramstage.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_RAMSTAGE_H_ #define _SOC_APOLLOLAKE_RAMSTAGE_H_ diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index 8c4d1ed405..0581f5e210 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_ROMSTAGE_H_ #define _SOC_APOLLOLAKE_ROMSTAGE_H_ diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index 0ac82930a7..75e4f9bd8b 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef SOC_APOLLOLAKE_SYSTEMAGENT_H #define SOC_APOLLOLAKE_SYSTEMAGENT_H diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 060d5bd1b8..b2dc65dd62 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_APOLLOLAKE_USB_H_ #define _SOC_APOLLOLAKE_USB_H_ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 541df007f7..217eb2c9a8 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index f84821c7b3..98cc242706 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c index d5ce4ae271..4ff541b138 100644 --- a/src/soc/intel/apollolake/nhlt.c +++ b/src/soc/intel/apollolake/nhlt.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 60cc9aa927..4ed8ea9fcf 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "chip.h" #include diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 58d34d1dbf..cb5c353080 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define __SIMPLE_DEVICE__ diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 338aac9b63..34428e446d 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 2a3c500451..68ea1b1609 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index b5ae6f36ff..cc3639cb54 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 965e4eeb3d..7b9450cff0 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * The sole purpose of this driver is to avoid BAR to be changed during diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl index d9f265ad80..542d73df64 100644 --- a/src/soc/intel/cannonlake/acpi/gfx.asl +++ b/src/soc/intel/cannonlake/acpi/gfx.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ Device (GFX0) { diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 83a64cadae..3eb2e8f699 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ External(\_SB.MS0X, MethodObj) External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index d765ee3353..f8fada36f7 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 458c1aa671..53558ef48f 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* PCI IRQ assignment */ #include "pci_irqs.asl" diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index f6419854fd..d71f9b3086 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index 50ecb462e7..119b89dea2 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c index 07dfbea43b..742213eb79 100644 --- a/src/soc/intel/cannonlake/gpio_common.c +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 65dd621f66..05af993a24 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c index 43825d8bbb..09adc47e29 100644 --- a/src/soc/intel/cannonlake/gspi.c +++ b/src/soc/intel/cannonlake/gspi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/cannonlake/include/soc/nhlt.h b/src/soc/intel/cannonlake/include/soc/nhlt.h index 3b8a35383f..e8eac69a62 100644 --- a/src/soc/intel/cannonlake/include/soc/nhlt.h +++ b/src/soc/intel/cannonlake/include/soc/nhlt.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_CANNONLAKE_NHLT_H_ #define _SOC_CANNONLAKE_NHLT_H_ diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c index 56ad12a2ec..a63502aac9 100644 --- a/src/soc/intel/cannonlake/nhlt.c +++ b/src/soc/intel/cannonlake/nhlt.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/cannonlake/spi.c b/src/soc/intel/cannonlake/spi.c index 8a14d244bb..29dcdbec6c 100644 --- a/src/soc/intel/cannonlake/spi.c +++ b/src/soc/intel/cannonlake/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index 4547204894..5e38c4b502 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _INTEL_COMMON_ACPI_H_ #define _INTEL_COMMON_ACPI_H_ diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fd6e48c310..eaf1e2918a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 91265be799..348f94a40b 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 07aebd5ea4..ce5dc81986 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index a9304ba48b..b56ec6d9a2 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 702b9a1431..1be3238e60 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 939d2e0146..ae57b31572 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index e8759ffa76..b2cbbf51a9 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef SOC_INTEL_COMMON_BLOCK_ACPI_H #define SOC_INTEL_COMMON_BLOCK_ACPI_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index a0998e1e88..308268d949 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef SOC_INTEL_COMMON_CSE_H #define SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index dd107a74b2..7e61da4382 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_INTELBLOCKS_GPIO_H_ #define _SOC_INTELBLOCKS_GPIO_H_ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 5327dba195..266d093868 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_BLOCK_GPIO_DEFS_H_ #define _SOC_BLOCK_GPIO_DEFS_H_ diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 9100f2af21..f92ebcbfdb 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_COMMON_BLOCK_LPC_LIB_H_ #define _SOC_COMMON_BLOCK_LPC_LIB_H_ diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 072963bb0d..789470a204 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 2d18838a13..14387d90cc 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_COMMON_BLOCK_LPC_DEF_H_ #define _SOC_COMMON_BLOCK_LPC_DEF_H_ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index f8b467a849..160e8cfe9a 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define __SIMPLE_DEVICE__ diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index ef8515c5bf..59b876a4b4 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 6dee8792dc..ead3d9a057 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index e881b5417a..c34546489b 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _INTEL_COMMON_RESET_H_ #define _INTEL_COMMON_RESET_H_ diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 28f312179e..0f72471c08 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index 4b9fbe1b49..b834e8a74b 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 986459eeb3..42d63ee399 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 19dddbed82..7142f324ca 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c index 77053292ca..7bf4a349cc 100644 --- a/src/soc/intel/denverton_ns/gpio.c +++ b/src/soc/intel/denverton_ns/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/hob_display.c b/src/soc/intel/denverton_ns/hob_display.c index b046b308c7..a61e6fa621 100644 --- a/src/soc/intel/denverton_ns/hob_display.c +++ b/src/soc/intel/denverton_ns/hob_display.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 790275a3ae..270007824a 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/spi.c b/src/soc/intel/denverton_ns/spi.c index 4fefd361b0..bedba3f7b4 100644 --- a/src/soc/intel/denverton_ns/spi.c +++ b/src/soc/intel/denverton_ns/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 44ba0335d7..9a42499e9f 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * The sole purpose of this driver is to avoid BAR to be changed during diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index 60ff4d9c7d..ce1a1e26eb 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/denverton_ns/upd_display.c b/src/soc/intel/denverton_ns/upd_display.c index 58e0ad5d68..46a0cf24f5 100644 --- a/src/soc/intel/denverton_ns/upd_display.c +++ b/src/soc/intel/denverton_ns/upd_display.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl index a6aa0abacc..6712fdded1 100644 --- a/src/soc/intel/icelake/acpi/pci_irqs.asl +++ b/src/soc/intel/icelake/acpi/pci_irqs.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index b98f4ef843..a1e8966bc4 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index f8452ea9a1..dd865fb672 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 33e6227f9a..88b5869161 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/icelake/gspi.c b/src/soc/intel/icelake/gspi.c index 43825d8bbb..09adc47e29 100644 --- a/src/soc/intel/icelake/gspi.c +++ b/src/soc/intel/icelake/gspi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/icelake/spi.c b/src/soc/intel/icelake/spi.c index 8a14d244bb..29dcdbec6c 100644 --- a/src/soc/intel/icelake/spi.c +++ b/src/soc/intel/icelake/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl index cc832e41fc..a33804e9de 100644 --- a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define R_ICLK_PCR_CAMERA1 0x8000 #define B_ICLK_PCR_FREQUENCY 0x1 diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl index aa5048ee52..845da7a1b8 100644 --- a/src/soc/intel/jasperlake/acpi/pci_irqs.asl +++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index 549ee96051..339d62ba88 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 7850c64f33..1a6b8ae423 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 33e6227f9a..88b5869161 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c index 43825d8bbb..09adc47e29 100644 --- a/src/soc/intel/jasperlake/gspi.c +++ b/src/soc/intel/jasperlake/gspi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/jasperlake/spi.c b/src/soc/intel/jasperlake/spi.c index 8a14d244bb..29dcdbec6c 100644 --- a/src/soc/intel/jasperlake/spi.c +++ b/src/soc/intel/jasperlake/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c index 13e329dd61..3b945c8246 100644 --- a/src/soc/intel/skylake/gspi.c +++ b/src/soc/intel/skylake/gspi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/skylake/nhlt/da7219.c b/src/soc/intel/skylake/nhlt/da7219.c index 5ce3e357b3..e1673f6606 100644 --- a/src/soc/intel/skylake/nhlt/da7219.c +++ b/src/soc/intel/skylake/nhlt/da7219.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c index bebf6c4186..6283001902 100644 --- a/src/soc/intel/skylake/spi.c +++ b/src/soc/intel/skylake/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index cc832e41fc..a33804e9de 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define R_ICLK_PCR_CAMERA1 0x8000 #define B_ICLK_PCR_FREQUENCY 0x1 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index a021d368a3..c93ef545a8 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 2c99978f33..b5bb504ec4 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c index ca02cd965d..85a25f2283 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index f8d1125d08..f1a490d7d6 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * This file is created based on Intel Tiger Lake Processor SA Datasheet diff --git a/src/soc/intel/tigerlake/gspi.c b/src/soc/intel/tigerlake/gspi.c index 9385ec1043..51bc868f09 100644 --- a/src/soc/intel/tigerlake/gspi.c +++ b/src/soc/intel/tigerlake/gspi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index 765a24d079..16dc996453 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index d89143bf48..1718c85913 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 134d0e6c25..2e90054a70 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_IOMAP_H_ diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index 3f3b3f1538..9869ecdd8e 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _PCR_IDS_H_ #define _PCR_IDS_H_ diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index c4091d1255..27c0067d50 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index bcd476cdf3..bebf2aca58 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_PMC_H_ #define _SOC_PMC_H_ diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 80101f5797..221d6f6ef1 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_ROMSTAGE_H_ diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index e41b771c79..fa368c2e0c 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _XEON_SP_SOC_UTIL_H_ #define _XEON_SP_SOC_UTIL_H_ diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 696734e5ae..f41c288ea7 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/reset.c b/src/soc/intel/xeon_sp/reset.c index 259fbc3089..e4960068ad 100644 --- a/src/soc/intel/xeon_sp/reset.c +++ b/src/soc/intel/xeon_sp/reset.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index c0177bd9bd..947cd01916 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 6d95d51ce8..2f4fb64df1 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl index 3e19165b29..d57c850c5c 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Global Variables */ diff --git a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl index 6347c2ba19..0a067662bc 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define MAKE_IIO_DEV(id,rt) \ Device (PC##id) \ diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl index 4ed1c1dd25..eff5d9b5c3 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index 2bb1e4adaf..095a8788d9 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Uncore devices PCI interrupt routing packages. diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 3f9db8215c..875fe389d2 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index 8b48eb7e80..eb44af9785 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_CHIP_H_ diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index d19921bc2e..431a3bd776 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/skx/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c index 2cc39e6870..97a96cf849 100644 --- a/src/soc/intel/xeon_sp/skx/hob_display.c +++ b/src/soc/intel/xeon_sp/skx/hob_display.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h index e7f176ae7a..7abeeec992 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_ACPI_H_ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index 08ce4edd94..76d5dee182 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_CPU_H_ #define _SOC_CPU_H_ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/irq.h b/src/soc/intel/xeon_sp/skx/include/soc/irq.h index 92bcdc8f0f..726d332e3d 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/irq.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/irq.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h index 31c1c026b4..76b42bcbd9 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/msr.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 07edad25e7..5c20f71424 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h index ffd67b16d9..18373f8884 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 9beddcc4d0..ab1437bec7 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c index fcea838917..d4e04cc787 100644 --- a/src/soc/intel/xeon_sp/skx/upd_display.c +++ b/src/soc/intel/xeon_sp/skx/upd_display.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/soc/intel/xeon_sp/spi.c b/src/soc/intel/xeon_sp/spi.c index fbb60e8b0b..f312a56d7d 100644 --- a/src/soc/intel/xeon_sp/spi.c +++ b/src/soc/intel/xeon_sp/spi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a578efe8e2..836ac55e21 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h index 3d7dbb7199..f60f15ece7 100644 --- a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h +++ b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h @@ -1,14 +1,4 @@ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SOC_MEDIATEK_MD_CTRL_H__ #define __SOC_MEDIATEK_MD_CTRL_H__ diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c index d65b426078..0abd2c9d5d 100644 --- a/src/soc/mediatek/mt8183/md_ctrl.c +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 927533ee94..f0f5b11172 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOC_NVIDIA_TEGRA_DC_H #define __SOC_NVIDIA_TEGRA_DC_H diff --git a/src/soc/nvidia/tegra/pwm.h b/src/soc/nvidia/tegra/pwm.h index 7e9e81aae3..765de08aab 100644 --- a/src/soc/nvidia/tegra/pwm.h +++ b/src/soc/nvidia/tegra/pwm.h @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOC_NVIDIA_TEGRA_PWM_H #define __SOC_NVIDIA_TEGRA_PWM_H diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index 22cb71f9bb..58f92c5823 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_MMU_COMMON_H_ #define _SOC_QUALCOMM_MMU_COMMON_H_ diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index 18a4a32821..16dbdaa64c 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_QCLIB_COMMON_H__ #define _SOC_QUALCOMM_QCLIB_COMMON_H__ diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 68a9b69982..60b3f4eb10 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SYMBOLS_COMMON_H_ #define _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index c9967a79fe..76ce0b6612 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 93472e5014..dc6a842d0d 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/ipq40xx/tz_wrapper.S b/src/soc/qualcomm/ipq40xx/tz_wrapper.S index 1df9801692..fab220417d 100644 --- a/src/soc/qualcomm/ipq40xx/tz_wrapper.S +++ b/src/soc/qualcomm/ipq40xx/tz_wrapper.S @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * TZ expects the ARM core to be in 'ARM' mode. However, coreboot seems diff --git a/src/soc/qualcomm/ipq806x/tz_wrapper.S b/src/soc/qualcomm/ipq806x/tz_wrapper.S index 1df9801692..fab220417d 100644 --- a/src/soc/qualcomm/ipq806x/tz_wrapper.S +++ b/src/soc/qualcomm/ipq806x/tz_wrapper.S @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * TZ expects the ARM core to be in 'ARM' mode. However, coreboot seems diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index dcfc84676b..b7f912a7c4 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 6a0fe9d2db..d7f4500d18 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index cbc16a9614..636b8b9f69 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ - /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ + /* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index 98f4467472..4e283d2438 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ #define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index 1778214d47..0fc27e04e9 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ - /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ + /* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index 9e665edea5..49787b9fd0 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_QCS405_GPIO_H_ #define _SOC_QUALCOMM_QCS405_GPIO_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index f138fb75d1..fb6edb3875 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index a6a9fea26e..b09abe9437 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_QCS405_MMU_H__ #define _SOC_QUALCOMM_QCS405_MMU_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 90f72969cd..d952d722ab 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_ #define _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/usb.h b/src/soc/qualcomm/qcs405/include/soc/usb.h index 04ab3b6cd3..44c0382c0c 100644 --- a/src/soc/qualcomm/qcs405/include/soc/usb.h +++ b/src/soc/qualcomm/qcs405/include/soc/usb.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #ifndef _QCS405_USB_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index e6b70c078e..6517b99459 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index 5f11f73378..3b8a7998f3 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c index 085344c331..7e62c88723 100644 --- a/src/soc/qualcomm/qcs405/timer.c +++ b/src/soc/qualcomm/qcs405/timer.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index 1723fac438..0343b55313 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 784101a3cf..e7c1620390 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 29d5d896a3..f7d5604106 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 3f654fdffb..0065a93a24 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index b7fe201ff2..ab1c20f8f9 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 0b9f4396e1..4f0761f1b4 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ #define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h index 1fd026180e..b702e34123 100644 --- a/src/soc/qualcomm/sc7180/include/soc/aop.h +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SC7180_AOP_H__ #define _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index a2a7a802d4..f7c7f38110 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/include/soc/efuse.h b/src/soc/qualcomm/sc7180/include/soc/efuse.h index fd14d89bc9..1fe7b40db9 100644 --- a/src/soc/qualcomm/sc7180/include/soc/efuse.h +++ b/src/soc/qualcomm/sc7180/include/soc/efuse.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ #define __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index b7f4fdef8d..090fbe444f 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SC7180_GPIO_H_ #define _SOC_QUALCOMM_SC7180_GPIO_H_ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 5c2736ea16..11a1b641d0 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h index 34ff5d72fa..1e5610cb3b 100644 --- a/src/soc/qualcomm/sc7180/include/soc/mmu.h +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SC7180_MMU_H_ #define _SOC_QUALCOMM_SC7180_MMU_H_ diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h index 221e44af33..eaa095c3a6 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SOC_QCOM_QUP_SE_H__ #define __SOC_QCOM_QUP_SE_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/qspi.h b/src/soc/qualcomm/sc7180/include/soc/qspi.h index 0d6fbcb09f..68f155880e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qspi.h +++ b/src/soc/qualcomm/sc7180/include/soc/qspi.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include #include diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h index 3eaf0ce190..eb92496eac 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h @@ -1,14 +1,5 @@ /* This file is part of the depthcharge project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __I2C_QCOM_HEADER___ #define __I2C_QCOM_HEADER___ diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h index 172d937bd1..22be0993f3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_spi.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SPI_QUP_QCOM_HEADER___ #define __SPI_QUP_QCOM_HEADER___ diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 9082f3eea7..ac4593bcc9 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_ #define _SOC_QUALCOMM_SC7180_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h index 846b0d1a70..939b2cf944 100644 --- a/src/soc/qualcomm/sc7180/include/soc/usb.h +++ b/src/soc/qualcomm/sc7180/include/soc/usb.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #ifndef _SC7180_USB_H_ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 5eb9b27cde..6b5c794c61 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 80cc7558b2..c7d50c3115 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index 58a1b36606..b3747a804c 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index f670f6d9b3..cf48603e84 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index 02f92b4aa0..eb6c3dc8da 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -1,14 +1,5 @@ /* This file is part of the depthcharge project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index 4d26a2933b..69255baf02 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index 916d4aa4d4..88e7f13f95 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 775f4e597e..92a9b247ca 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index 5e6292394f..fe2e1edb3d 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c index 085344c331..7e62c88723 100644 --- a/src/soc/qualcomm/sc7180/timer.c +++ b/src/soc/qualcomm/sc7180/timer.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index 645e6a4384..f4ee28f7cf 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index bf3e64a213..4803196d49 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index b984780b1e..d500567808 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c index bdc37c17ae..8065c1d977 100644 --- a/src/soc/qualcomm/sdm845/bootblock.c +++ b/src/soc/qualcomm/sdm845/bootblock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3f654fdffb..0065a93a24 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index 38168602b6..dcc7cd8bd2 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h index e8b00a23f6..d98c6c5ade 100644 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ #define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/aop.h b/src/soc/qualcomm/sdm845/include/soc/aop.h index 72b97b7946..c01e32762b 100644 --- a/src/soc/qualcomm/sdm845/include/soc/aop.h +++ b/src/soc/qualcomm/sdm845/include/soc/aop.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SDM845_AOP_H__ #define _SOC_QUALCOMM_SDM845_AOP_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index a6e451c471..645a78db20 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h index 0b1adf6ddb..43aeb3507d 100644 --- a/src/soc/qualcomm/sdm845/include/soc/efuse.h +++ b/src/soc/qualcomm/sdm845/include/soc/efuse.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ #define __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h index 8cb74763d0..47200c5e11 100644 --- a/src/soc/qualcomm/sdm845/include/soc/gpio.h +++ b/src/soc/qualcomm/sdm845/include/soc/gpio.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SDM845_GPIO_H_ #define _SOC_QUALCOMM_SDM845_GPIO_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index 5c04f49e64..53c7824f5b 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h index 62e9ac2e0b..8258dccdda 100644 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ b/src/soc/qualcomm/sdm845/include/soc/mmu.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SDM845_MMU_H__ #define _SOC_QUALCOMM_SDM845_MMU_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/qspi.h b/src/soc/qualcomm/sdm845/include/soc/qspi.h index 2359c10eab..32d514fa45 100644 --- a/src/soc/qualcomm/sdm845/include/soc/qspi.h +++ b/src/soc/qualcomm/sdm845/include/soc/qspi.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include #include diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index fa5c1a710b..861ff8675e 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h index bb65899ccb..10539bfd46 100644 --- a/src/soc/qualcomm/sdm845/include/soc/usb.h +++ b/src/soc/qualcomm/sdm845/include/soc/usb.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #ifndef _SDM845_USB_H_ diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index 906c0921cf..5aa127b0af 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c index 8be4c9aebb..dafa3ad0c7 100644 --- a/src/soc/qualcomm/sdm845/qclib.c +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c index f0a52f6de0..7337fd94da 100644 --- a/src/soc/qualcomm/sdm845/qspi.c +++ b/src/soc/qualcomm/sdm845/qspi.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index 1f076c903a..468ab5462c 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c index ec068f5ec0..1c9820281c 100644 --- a/src/soc/qualcomm/sdm845/spi.c +++ b/src/soc/qualcomm/sdm845/spi.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c index 085344c331..7e62c88723 100644 --- a/src/soc/qualcomm/sdm845/timer.c +++ b/src/soc/qualcomm/sdm845/timer.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c index 71913d1cbf..7f1720aa5a 100644 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ b/src/soc/qualcomm/sdm845/uart_bitbang.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 6aa0015fd1..65f5ad139b 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 20b8752e82..71bc39de2e 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Designware High-Definition Multimedia Interface (HDMI) driveG diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index eee1743163..76d08a2fd9 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOC_HDMI_H__ #define __SOC_HDMI_H__ diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 90ad93298a..5a7c45dc39 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -1,17 +1,6 @@ /* This file is part of the coreboot project. */ /* DDR3 mem setup file for EXYNOS5 based board */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 101630dab4..7c2fd9f035 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -1,15 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 6bb73512ab..e53adbb8c8 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -1,15 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 20480f4251..53c9fe41bf 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -1,15 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 081728af92..972d06319a 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Utilities for SMM setup diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 4e109e4da7..7670fb7d69 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Utilities for SMI handlers and SMM setup diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c index e53bb70ada..7258fc2335 100644 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SMM utilities used in both SMM and normal mode diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index 478107c5f5..22170aa5d3 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SMI handler for Hudson southbridges diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 081728af92..972d06319a 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Utilities for SMM setup diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index 19358a2bcc..c596fcd892 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Utilities for SMI handlers and SMM setup diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index e53bb70ada..7258fc2335 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SMM utilities used in both SMM and normal mode diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 478107c5f5..22170aa5d3 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * SMI handler for Hudson southbridges diff --git a/src/southbridge/intel/common/finalize.h b/src/southbridge/intel/common/finalize.h index 2e70f849a7..67e039c0ed 100644 --- a/src/southbridge/intel/common/finalize.h +++ b/src/southbridge/intel/common/finalize.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef SOUTHBRIDGE_INTEL_COMMON_FINALIZE_H #define SOUTHBRIDGE_INTEL_COMMON_FINALIZE_H diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 5e967af7cc..380940c739 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -1,15 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3c997f8e60..206a23417a 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -1,15 +1,6 @@ /* This file is part of the coreboot project. */ -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef SOUTHBRIDGE_INTEL_SPI_H #define SOUTHBRIDGE_INTEL_SPI_H diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 6faaa3597f..db9add0c63 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h index 6d42cc1e3f..ab98801f37 100644 --- a/src/southbridge/intel/i82371eb/chip.h +++ b/src/southbridge/intel/i82371eb/chip.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef SOUTHBRIDGE_INTEL_I82371EB_CHIP_H #define SOUTHBRIDGE_INTEL_I82371EB_CHIP_H diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 168d3b2c1d..8da73698c9 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index a7ef1eb9c0..41c324ff50 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index ec8745a286..f33e3cec7b 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */ diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 3433561fef..d6211829b0 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index d2e8614c55..b2d2aca887 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* TODO: Check if this really works for all of the southbridges. */ diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 4e32c1dab7..91405459a3 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 4c1594b4ff..381904ce55 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 80c46b2a23..c9129a319b 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index 9d219b06e3..e1f74562c1 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/intel/i82801gx/sata.h b/src/southbridge/intel/i82801gx/sata.h index a4fc6dc88b..a159f3730a 100644 --- a/src/southbridge/intel/i82801gx/sata.h +++ b/src/southbridge/intel/i82801gx/sata.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef I82801GX_SATA_H #define I82801GX_SATA_H diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index f92269801f..fbbc9dbfcc 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 3ff08b2b95..ca8ced89a5 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 89220eaa6b..3cbc771af0 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* rl5c476 routines and defines*/ diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 8a16653eaf..653eabefc5 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 211b5bc31c..6a769effa6 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/ti/pci7420/chip.h b/src/southbridge/ti/pci7420/chip.h index a5349d055a..114ce8d31f 100644 --- a/src/southbridge/ti/pci7420/chip.h +++ b/src/southbridge/ti/pci7420/chip.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOUTHBRIDGE_TI_PCI7420 #define _SOUTHBRIDGE_TI_PCI7420 diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index 037355e9c3..b5469f20ee 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index 8b02a5079d..fac7d0c081 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ // 0844d060 (old) #define SYSCTL 0x80 // 08405061 diff --git a/util/cbfstool/fdt.h b/util/cbfstool/fdt.h index 126ca95200..0af48abba2 100644 --- a/util/cbfstool/fdt.h +++ b/util/cbfstool/fdt.h @@ -1,15 +1,5 @@ /* Taken from depthcharge: src/base/device_tree.h */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ struct fdt_header { uint32_t magic; diff --git a/util/ectool/ec.c b/util/ectool/ec.c index 17a08dcbf9..e008ac44d0 100644 --- a/util/ectool/ec.c +++ b/util/ectool/ec.c @@ -1,14 +1,5 @@ /* This file is part of the ectool project. */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/ectool/ec.h b/util/ectool/ec.h index b7bc6b938f..004bd7d9bc 100644 --- a/util/ectool/ec.h +++ b/util/ectool/ec.h @@ -1,15 +1,5 @@ /* This file is part of the ectool project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _EC_H #define _EC_H diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index 21e1023b34..a2c3eef465 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -1,15 +1,5 @@ /* This file is part of the ectool project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index e3df257272..b7e2307729 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/intelmetool/me.h b/util/intelmetool/me.h index 4e0036e2d3..57b5475de9 100644 --- a/util/intelmetool/me.h +++ b/util/intelmetool/me.h @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef ME_H #define ME_H diff --git a/util/intelmetool/me_status.c b/util/intelmetool/me_status.c index 77c3ba6644..0970394471 100644 --- a/util/intelmetool/me_status.c +++ b/util/intelmetool/me_status.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include "me.h" diff --git a/util/intelmetool/mmap.c b/util/intelmetool/mmap.c index 70bc42244d..6200dcbc51 100644 --- a/util/intelmetool/mmap.c +++ b/util/intelmetool/mmap.c @@ -1,15 +1,5 @@ /* intelmetool */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include "mmap.h" #include diff --git a/util/intelmetool/mmap.h b/util/intelmetool/mmap.h index ecc327a535..57ecca2460 100644 --- a/util/intelmetool/mmap.h +++ b/util/intelmetool/mmap.h @@ -1,16 +1,5 @@ /* intelmetool */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/util/intelmetool/msr.c b/util/intelmetool/msr.c index d8735a7c0b..263a8202bb 100644 --- a/util/intelmetool/msr.c +++ b/util/intelmetool/msr.c @@ -1,15 +1,5 @@ /* intelmetool */ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/util/intelmetool/msr.h b/util/intelmetool/msr.h index c40700f248..44008d50c6 100644 --- a/util/intelmetool/msr.h +++ b/util/intelmetool/msr.h @@ -1,16 +1,5 @@ /* intelmetool */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/util/intelmetool/rcba.c b/util/intelmetool/rcba.c index d1aaa671a8..3716bcb353 100644 --- a/util/intelmetool/rcba.c +++ b/util/intelmetool/rcba.c @@ -1,15 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/util/intelmetool/rcba.h b/util/intelmetool/rcba.h index a87fe49180..50b16b6331 100644 --- a/util/intelmetool/rcba.h +++ b/util/intelmetool/rcba.h @@ -1,15 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ int write_rcba32(uint32_t addr, uint32_t val); int read_rcba32(uint32_t addr, uint32_t *val); diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 4be40ff38a..2080e3bab5 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -1,16 +1,5 @@ /* ahci.c: dump AHCI registers */ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl b/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl index 3cc78aebd0..9b17d4572e 100644 --- a/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl +++ b/util/mainboard/google/hatch/template/include/variant/acpi/dptf.asl @@ -1,13 +1,4 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/util/mainboard/google/hatch/template/include/variant/ec.h b/util/mainboard/google/hatch/template/include/variant/ec.h index bbcd4a3b99..b9fb4f19cc 100644 --- a/util/mainboard/google/hatch/template/include/variant/ec.h +++ b/util/mainboard/google/hatch/template/include/variant/ec.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/util/mainboard/google/hatch/template/include/variant/gpio.h b/util/mainboard/google/hatch/template/include/variant/gpio.h index 063c0f53a4..f37579e911 100644 --- a/util/mainboard/google/hatch/template/include/variant/gpio.h +++ b/util/mainboard/google/hatch/template/include/variant/gpio.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/util/msrtool/cs5536.c b/util/msrtool/cs5536.c index 3d035000a3..ce28c4d655 100644 --- a/util/msrtool/cs5536.c +++ b/util/msrtool/cs5536.c @@ -1,14 +1,5 @@ /* This file is part of msrtool. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/darwin.c b/util/msrtool/darwin.c index efa37fce79..a362086ffd 100644 --- a/util/msrtool/darwin.c +++ b/util/msrtool/darwin.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/msrtool/freebsd.c b/util/msrtool/freebsd.c index 40cd9a16d7..1ea4eef1ba 100644 --- a/util/msrtool/freebsd.c +++ b/util/msrtool/freebsd.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/msrtool/geodegx2.c b/util/msrtool/geodegx2.c index d6a845fc12..6f6b982430 100644 --- a/util/msrtool/geodegx2.c +++ b/util/msrtool/geodegx2.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/geodelx.c b/util/msrtool/geodelx.c index bac8ec1a82..aa6f8a7efd 100644 --- a/util/msrtool/geodelx.c +++ b/util/msrtool/geodelx.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index ac63a2615f..3e58d949aa 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c index fcb3a91659..7f8717ee5e 100644 --- a/util/msrtool/intel_core1.c +++ b/util/msrtool/intel_core1.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c index ea35ac4b04..4d265311ba 100644 --- a/util/msrtool/intel_core2_early.c +++ b/util/msrtool/intel_core2_early.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 7e1cdfd9c6..ef7cfc5dbf 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 3f472e8f6f..21d8f310e3 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c index aedc4402cf..d51d46c742 100644 --- a/util/msrtool/intel_pentium3.c +++ b/util/msrtool/intel_pentium3.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c index 676f134c41..50cfa24ab7 100644 --- a/util/msrtool/intel_pentium3_early.c +++ b/util/msrtool/intel_pentium3_early.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c index 249cac8136..ac5a1b0bcb 100644 --- a/util/msrtool/intel_pentium4_early.c +++ b/util/msrtool/intel_pentium4_early.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c index 0b51707d19..0795ed2a9e 100644 --- a/util/msrtool/intel_pentium4_later.c +++ b/util/msrtool/intel_pentium4_later.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/intel_pentium_d.c b/util/msrtool/intel_pentium_d.c index 28b544bb01..f58e5d66fd 100644 --- a/util/msrtool/intel_pentium_d.c +++ b/util/msrtool/intel_pentium_d.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/k8.c b/util/msrtool/k8.c index 96aa6c5dfe..405945d963 100644 --- a/util/msrtool/k8.c +++ b/util/msrtool/k8.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/msrtool/linux.c b/util/msrtool/linux.c index ccf8dbd0e0..428f14030c 100644 --- a/util/msrtool/linux.c +++ b/util/msrtool/linux.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 13586d8c78..b4d721a28f 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index f6ba66829b..d1f2eb9a82 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef MSRTOOL_H #define MSRTOOL_H diff --git a/util/msrtool/msrutils.c b/util/msrtool/msrutils.c index 82199a8f80..58330ff98f 100644 --- a/util/msrtool/msrutils.c +++ b/util/msrtool/msrutils.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/msrtool/sys.c b/util/msrtool/sys.c index f79391d434..f32246ed34 100644 --- a/util/msrtool/sys.c +++ b/util/msrtool/sys.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/util/msrtool/via_c7.c b/util/msrtool/via_c7.c index 9939798151..779144ee15 100644 --- a/util/msrtool/via_c7.c +++ b/util/msrtool/via_c7.c @@ -1,15 +1,5 @@ /* This file is part of msrtool. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "msrtool.h" diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index b8bd0ed787..780c91c30f 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -1,15 +1,5 @@ /* This file is part of pgtblgen. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/util/vgabios/include/swab.h b/util/vgabios/include/swab.h index 4b82b6293c..a93e926336 100644 --- a/util/vgabios/include/swab.h +++ b/util/vgabios/include/swab.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SWAB_H #define _SWAB_H From 40454b7b00a59bec178da3527d933d126ca1fbd6 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 4 May 2020 20:52:08 -0700 Subject: [PATCH 1429/1463] soc/amd/common/block/lpc: Use standard pci_dev_ops_pci AMD common block LPC driver does not really need a custom ops_pci structure. This change drops the lops_pci and instead set .ops_pci to the default pci_dev_ops_pci. BUG=b:154445472 Change-Id: Ia06eed04097739c3e21dc13e056a2120ff5eb382 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41068 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/soc/amd/common/block/lpc/lpc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 0c98fcbc6b..54befef7c3 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -306,10 +306,6 @@ static void lpc_enable_resources(struct device *dev) lpc_enable_childrens_resources(dev); } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, @@ -318,7 +314,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { From 4ebe953090df979a76b99a532b2f28e697fbf365 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 2 May 2020 15:34:42 -0700 Subject: [PATCH 1430/1463] util/sconfig: Drop id from struct device maintained by sconfig This change drops the id field from struct device as used by sconfig. It was primarily used for generating unique device names. This was maintained within device structure so that the order in which the device tree entries were parsed is clear. Since the ids are assigned in parsing order, it is problematic when a device is moved from base devicetree to override tree. The entire parsing order changes which makes it really difficult to compare what really changed in static.c file. By moving the dev name assignment to happen later when doing pass0 of static.c generation, the difference in static.c file is minimized when adding support for override trees. BUG=b:155549176 Change-Id: I31870ace5a2fd7d5f95ab5e30d794c3bc959ed46 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41005 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- util/sconfig/main.c | 13 ++++++------- util/sconfig/sconfig.h | 8 +------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index b48f992672..27fca44179 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -98,7 +98,6 @@ static struct bus base_root_bus = { static struct device base_root_dev = { .name = "dev_root", - .id = 0, .chip_instance = &mainboard_instance, .path = " .type = DEVICE_PATH_ROOT ", .parent = &base_root_bus, @@ -113,7 +112,6 @@ static struct bus override_root_bus = { static struct device override_root_dev = { .name = "override_root", - .id = 0, /* * Override tree root device points to the same mainboard chip instance * as the base tree root device. It should not cause any side-effects @@ -429,7 +427,6 @@ static struct device *alloc_dev(struct bus *parent) { struct device *dev = S_ALLOC(sizeof(*dev)); - dev->id = ++count; dev->parent = parent; dev->subsystem_vendor = -1; dev->subsystem_device = -1; @@ -510,10 +507,6 @@ struct device *new_device(struct bus *parent, new_d->path_a = path_a; new_d->path_b = path_b; - char *name = S_ALLOC(10); - sprintf(name, "_dev%d", new_d->id); - new_d->name = name; - new_d->enabled = status & 0x01; new_d->hidden = (status >> 1) & 0x01; new_d->mandatory = (status >> 2) & 0x01; @@ -699,12 +692,18 @@ static int dev_has_children(struct device *dev) static void pass0(FILE *fil, FILE *head, struct device *ptr, struct device *next) { + static int dev_id; + if (ptr == &base_root_dev) { fprintf(fil, "STORAGE struct bus %s_links[];\n", ptr->name); return; } + char *name = S_ALLOC(10); + sprintf(name, "_dev%d", dev_id++); + ptr->name = name; + fprintf(fil, "STORAGE struct device %s;\n", ptr->name); if (ptr->res) fprintf(fil, "STORAGE struct resource %s_res[];\n", diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 60842f12a1..a76506d31d 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -43,10 +43,7 @@ struct pci_irq_info { struct chip; struct chip_instance { - /* - * Monotonically increasing ID for each newly allocated - * node(chip/device). - */ + /* Monotonically increasing ID for each chip instance. */ int id; /* Pointer to registers for this chip. */ @@ -98,9 +95,6 @@ struct bus { }; struct device { - /* Monotonically increasing ID for the device. */ - int id; - /* Indicates device status (enabled / hidden or not). */ int enabled; int hidden; From 9f681d2d7c48431d2d286d5ce7060bba924f4e37 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 2 May 2020 15:51:02 -0700 Subject: [PATCH 1431/1463] util/sconfig: Move chip instance id assignment to emit_chips() This change moves the assignment of id for chip instance from new_chip_instance() to emit_chips(). This is similar to the previous change for moving dev id assignment to happen much later. This ensures that the same ID gets assigned to a chip when adding support for device trees which makes it easier to compare static.c files. BUG=b:155549176 Change-Id: I3efa9af5ed91123675be42bce1cb389bad19cb62 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41006 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- util/sconfig/main.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 27fca44179..951ad6d219 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -30,12 +30,6 @@ extern int linenum; */ static struct chip chip_header; -/* - * This is intentionally shared between chip and device structure ids because it - * is easier to track the order of parsing for chip and device. - */ -static int count = 0; - typedef enum { UNSLASH, SPLIT_1ST, @@ -336,7 +330,6 @@ struct chip_instance *new_chip_instance(char *path) struct chip *chip = get_chip(path); struct chip_instance *instance = S_ALLOC(sizeof(*instance)); - instance->id = ++count; instance->chip = chip; instance->next = chip->instance; chip->instance = instance; @@ -987,6 +980,7 @@ static void emit_chips(FILE *fil) { struct chip *chip = chip_header.next; struct chip_instance *instance; + int chip_id; emit_chip_headers(fil, chip); @@ -996,8 +990,10 @@ static void emit_chips(FILE *fil) if (!chip->chiph_exists) continue; + chip_id = 1; instance = chip->instance; while (instance) { + instance->id = chip_id++; emit_chip_instance(fil, instance); instance = instance->next; } From bbade242416e04ed22f707a30748a1873b2650a8 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 2 May 2020 16:05:29 -0700 Subject: [PATCH 1432/1463] util/sconfig: Drop use of ref_count for chip_instance chip_instance structure currently uses a ref_count to determine how many devices hold reference to that instance. If the count drops to zero, then it is assumed that the chip instance is a duplicate in override tree and has a similar instance that is already overriden in base device tree. ref_count is currently decremented whenever a device in override tree matches the one in base device tree and the registers from the override tree instance are copied over to the base tree instance. On the other hand, if a device in override tree does not match any device in base tree under a given parent, then the device is added to base tree and all the devices in its subtree that hold pointers to its parent chip instance are updated to point to the parent's chip instance in base tree. This is done as part of update_chip_pointers. However, there are a couple of issues that this suffers from: a) If a device is present only in override tree and it does not have its own chip (i.e. pointing to parent's chip instance), then it results in sconfig emiiting parent's chip instance (which can be the SoC chip instance) in static.c even though it is unused. This is because update_chip_pointers() does not call delete_chip_instance() before reassigning the chip instance pointer. b) If a device is added under root device only in the override tree and it does not have its own chip instance (i.e. uses SoC chip instance), then it results in sconfig emitting a copy of the SoC chip instance and setting that as chip_ops for this new device in the override tree. In order to fix the above issues, this change drops the ref_count field from chip_instance structure and instead adds a forwarding pointer `base_chip_instance`. This is setup as per the following rules: 1. If the instance belongs to base devicetree, base_chip_instance is set to NULL. 2. If the instance belongs to override tree, then it is set to its corresponding chip instance in base tree (if present), else set to NULL. State of base_chip_instance is then used when emitting chips and devices using the following rules: 1. If a chip_instance has non-NULL base_chip_instance, then that chip instance is not emitted to static.c 2. When emitting chip_ops for a device, base_chip_instance is used to determine the correct chip instance name to emit. BUG=b:155549176 TEST=Verified that the static.c file generated for base/override tree combination is correct when new devices without chips are added only to override tree. Change-Id: Idbb5b34f49bf874da3f30ebb6a6a0e2d8d091fe5 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41007 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- util/sconfig/main.c | 107 ++++++++--------------------------------- util/sconfig/sconfig.h | 12 +++-- 2 files changed, 30 insertions(+), 89 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 951ad6d219..186eedba43 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -128,7 +128,6 @@ static struct chip mainboard_chip = { static struct chip_instance mainboard_instance = { .id = 0, .chip = &mainboard_chip, - .ref_count = 2, }; /* This is the parent of all devices added by parsing the devicetree file. */ @@ -337,54 +336,6 @@ struct chip_instance *new_chip_instance(char *path) return instance; } -static void delete_chip_instance(struct chip_instance *ins) -{ - - if (ins->ref_count == 0) { - printf("ERROR: ref count for chip instance is zero!!\n"); - exit(1); - } - - if (--ins->ref_count) - return; - - struct chip *c = ins->chip; - - /* Get pointer to first instance of the chip. */ - struct chip_instance *i = c->instance; - - /* - * If chip instance to be deleted is the first instance, then update - * instance pointer of the chip as well. - */ - if (i == ins) { - c->instance = ins->next; - free(ins); - return; - } - - /* - * Loop through the instances list of the chip to find and remove the - * given instance. - */ - while (1) { - if (i == NULL) { - printf("ERROR: chip instance not found!\n"); - exit(1); - } - - if (i->next != ins) { - i = i->next; - continue; - } - - i->next = ins->next; - break; - } - - free(ins); -} - /* * Allocate a new bus for the provided device. * - If this is the first bus being allocated under this device, then its id @@ -504,7 +455,6 @@ struct device *new_device(struct bus *parent, new_d->hidden = (status >> 1) & 0x01; new_d->mandatory = (status >> 2) & 0x01; new_d->chip_instance = chip_instance; - chip_instance->ref_count++; set_new_child(parent, new_d); @@ -780,6 +730,13 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next struct chip_instance *chip_ins = ptr->chip_instance; int has_children = dev_has_children(ptr); + /* + * If the chip instance of device has base_chip_instance pointer set, then follow that + * to update the chip instance for current device. + */ + if (chip_ins->base_chip_instance) + chip_ins = chip_ins->base_chip_instance; + if (ptr == &base_root_dev) fprintf(fil, "DEVTREE_CONST struct device %s = {\n", ptr->name); else @@ -993,8 +950,14 @@ static void emit_chips(FILE *fil) chip_id = 1; instance = chip->instance; while (instance) { - instance->id = chip_id++; - emit_chip_instance(fil, instance); + /* + * Emit this chip instance only if there is no forwarding pointer to the + * base tree chip instance. + */ + if (instance->base_chip_instance == NULL) { + instance->id = chip_id++; + emit_chip_instance(fil, instance); + } instance = instance->next; } } @@ -1081,29 +1044,6 @@ static int res_match(struct resource *a, struct resource *b) (a->index == b->index)); } -/* - * Walk through the override subtree in breadth-first manner starting at node to - * see if chip_instance pointer of the node is same as chip_instance pointer of - * override parent that is passed into the function. If yes, then update the - * chip_instance pointer of the node to chip_instance pointer of the base - * parent. - */ -static void update_chip_pointers(struct device *node, - struct chip_instance *base_parent_ci, - struct chip_instance *override_parent_ci) -{ - struct queue_entry *q_head = NULL; - - enqueue_tail(&q_head, node); - - while ((node = dequeue_head(&q_head))) { - if (node->chip_instance != override_parent_ci) - continue; - node->chip_instance = base_parent_ci; - add_children_to_queue(&q_head, node); - } -} - /* * Add resource to device. If resource is already present, then update its base * and index. If not, then add a new resource to the device. @@ -1286,6 +1226,12 @@ static void update_device(struct device *base_dev, struct device *override_dev) reg = reg->next; } + /* + * Update base_chip_instance member in chip instance of override tree to forward it to + * the chip instance in base tree. + */ + override_dev->chip_instance->base_chip_instance = base_dev->chip_instance; + /* * Now that the device properties are all copied over, look at each bus * of the override device and run override_devicetree in a recursive @@ -1312,9 +1258,6 @@ static void update_device(struct device *base_dev, struct device *override_dev) override_bus = override_bus->next_bus; base_bus = base_bus->next_bus; } - - delete_chip_instance(override_dev->chip_instance); - override_dev->chip_instance = NULL; } /* @@ -1359,14 +1302,6 @@ static void override_devicetree(struct bus *base_parent, * as a new child of base_parent. */ set_new_child(base_parent, override_child); - /* - * Ensure all nodes in override tree pointing to - * override parent chip_instance now point to base - * parent chip_instance. - */ - update_chip_pointers(override_child, - base_parent->dev->chip_instance, - override_parent->dev->chip_instance); } override_child = next_child; diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index a76506d31d..2603904289 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -56,10 +56,16 @@ struct chip_instance { struct chip_instance *next; /* - * Reference count - Indicates how many devices hold pointer to this - * chip instance. + * Pointer to corresponding chip instance in base devicetree. + * a) If the chip instance belongs to the base devicetree, then this pointer is set to + * NULL. + * b) If the chip instance belongs to override tree, then this pointer is set to its + * corresponding chip instance in base devicetree (if it exists), else to NULL. + * + * This is useful when generating chip instances and chip_ops for a device to determine + * if this is the instance to emit or if there is a base chip instance to use instead. */ - int ref_count; + struct chip_instance *base_chip_instance; }; struct chip { From ad2d73b1d9843bc886ea52f84d0e44895af03784 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 5 May 2020 13:08:21 -0700 Subject: [PATCH 1433/1463] soc/intel/tigerlake: Add PMC to platform ACPI name entry PMC device name string "PMC" is added to platform soc_acpi_name() for pmc driver. BUG=b:151646486 TEST=Built and booted to kernel successfully. Signed-off-by: John Zhao Change-Id: Ida7fc7e2340f2a809464ca66fd1922f3229e2e18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41064 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 073c8d2c69..b806dbb004 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -80,6 +80,7 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PMC: return "PMC"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_UART2: return "UAR2"; From 2b75ce2309083fc7e8e473d983aafb47edb88ad3 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 07:41:33 +0200 Subject: [PATCH 1434/1463] mb/x9scl/early_init: Remove unused includes Change-Id: I455a43ab6c4931a4fb1f717a65013b6b7cefb777 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40827 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/mainboard/supermicro/x9scl/early_init.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c index b4a39fe11f..a2f89e7873 100644 --- a/src/mainboard/supermicro/x9scl/early_init.c +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -1,25 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* FIXME: Check if all includes are needed. */ - #include -#include -#include -#include -#include #include #include #include -#include #include #include #include #include -#include #include #include #include + #include "x9scl.h" #define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1) From 6d592c623f0c1b2f1ca6d2676ab63d04d6e3235a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 7 May 2020 15:14:24 +0200 Subject: [PATCH 1435/1463] payloads/external/Makefile.inc: Pass hardware IRQ option to SeaBIOS Makefile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hardware IRQ option was not passed to SeaBIOS Makefile and resulted in HARDWARE_IRQ being permanently disabled regardless of Kconfig selection in coreboot. On platforms that need the hardware IRQ it caused hangs at boot menu or iPXE prompts. TEST=enter SeaBIOS boot menu on Libretrend LT1000 Signed-off-by: Michał Żygowski Change-Id: Iafcfd743177bbcd1ee23e227c74dd8268c4c23c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41147 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Patrick Georgi Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- payloads/external/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 7319a11a6d..5274581256 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -102,7 +102,8 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf: $(DOTCONFIG) CONFIG_SEABIOS_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL) \ CONFIG_DRIVERS_UART_8250MEM_32=$(CONFIG_DRIVERS_UART_8250MEM_32) \ CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \ - CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) + CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) \ + CONFIG_SEABIOS_HARDWARE_IRQ=$(CONFIG_SEABIOS_HARDWARE_IRQ) payloads/external/SeaBIOS/seabios/out/vgabios.bin: payloads/external/SeaBIOS/seabios/out/bios.bin.elf payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf From e8936747eb9b2e9558a297841e6a4612f7988827 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 29 Apr 2020 14:20:05 -0600 Subject: [PATCH 1436/1463] arch/x86: unexpose postcar_frame_common_mtrrs() The only caller is contained within the postcar_loader compilation unit. Therefore, remove postcar_frame_common_mtrrs() from the global symbol namespace. Change-Id: I90d308669d13eb2bebf1eca4d47e3f3b4f178714 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41101 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: HAOUAS Elyes --- src/arch/x86/include/arch/romstage.h | 5 ----- src/arch/x86/postcar_loader.c | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 0f9a3589bd..74ec7f4410 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -41,11 +41,6 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf, */ void postcar_frame_add_romcache(struct postcar_frame *pcf, int type); -/* - * Add a common MTRR setup most platforms will have as a subset. - */ -void postcar_frame_common_mtrrs(struct postcar_frame *pcf); - /* * fill_postcar_frame() is called after raminit completes and right before * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 2efa7ac178..1852eddf23 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -111,7 +111,7 @@ void postcar_frame_add_romcache(struct postcar_frame *pcf, int type) postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type); } -void postcar_frame_common_mtrrs(struct postcar_frame *pcf) +static void postcar_frame_common_mtrrs(struct postcar_frame *pcf) { if (pcf->skip_common_mtrr) return; From d8bd3ff1979ee16b6f7bdaf9f515753ec1e59da6 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 6 May 2020 12:50:51 -0600 Subject: [PATCH 1437/1463] memrange: constify memranges_is_empty() memranges_is_empty() doesn't need to manipulate the object. Mark the parameter as const. Change-Id: I89f4ec404c144eac8d2900945a1ccaf5cc4f88bb Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41102 Reviewed-by: Furquan Shaikh Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/include/memrange.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/memrange.h b/src/include/memrange.h index 2579f20c18..deb8c1e5de 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -69,7 +69,7 @@ static inline void range_entry_update_tag(struct range_entry *r, r->tag = new_tag; } -static inline bool memranges_is_empty(struct memranges *ranges) +static inline bool memranges_is_empty(const struct memranges *ranges) { return ranges->entries == NULL; } From b0800d3e41c54ad813313e572be06a0dcd030921 Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Wed, 6 May 2020 16:01:27 +0200 Subject: [PATCH 1438/1463] tests: Add proper license headers Signed-off-by: Jan Dabros Change-Id: Id8ca7c53122632c674e6bf952046ea22c0408e55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41088 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Julius Werner --- tests/device/Makefile.inc | 14 ++------------ tests/device/i2c-test.c | 14 ++------------ tests/lib/Makefile.inc | 14 ++------------ tests/lib/string-test.c | 3 +++ 4 files changed, 9 insertions(+), 36 deletions(-) diff --git a/tests/device/Makefile.inc b/tests/device/Makefile.inc index f23e72fa32..2bd6bb6a21 100644 --- a/tests/device/Makefile.inc +++ b/tests/device/Makefile.inc @@ -1,15 +1,5 @@ -## -## This file is part of the coreboot project. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. tests-y += i2c-test diff --git a/tests/device/i2c-test.c b/tests/device/i2c-test.c index 16e4d0d1ed..c4fa812d44 100644 --- a/tests/device/i2c-test.c +++ b/tests/device/i2c-test.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 86ac323ab8..fc2f8bc897 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -1,15 +1,5 @@ -## -## This file is part of the coreboot project. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. # object filest should be under build/tests/ build/test/src/ build/test/run/ # two examples - first should be simply string.c, second should use -wrap diff --git a/tests/lib/string-test.c b/tests/lib/string-test.c index 210aabae4a..5d03d51561 100644 --- a/tests/lib/string-test.c +++ b/tests/lib/string-test.c @@ -1,3 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + #include #include #include From bca848c84ec585635aed8badfa0804cc55c7e157 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Wed, 6 May 2020 22:55:58 +0800 Subject: [PATCH 1439/1463] mb/google/reef: add G2 TS support for snappy Add G2 GTCH7503 HID TS support spec from G2: G7500 / Ver.1.2 (3, April, 2018) BUG=b:155827595 BRANCH=master TEST=emerge-snappy coreboot Change-Id: I151bf141148f4f00b3dadd9c44ab3a6b7731cde1 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/41090 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- .../google/reef/variants/snappy/devicetree.cb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 4edf739805..7189508d18 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -244,6 +244,20 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 3 device pci 17.0 on chip drivers/i2c/generic From c409a3e585710ab7e8436e20d68842e210bb8d03 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 7 May 2020 01:18:32 +0200 Subject: [PATCH 1440/1463] soc/intel/skl: Drop `acpi_mainboard_gnvs` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Literally nobody else uses it and it does nothing. Change-Id: I7e6466137b5069a7f785972205bd43f3cb25d378 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41112 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi.c | 5 ----- src/soc/intel/skylake/include/soc/acpi.h | 1 - 2 files changed, 6 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 789af1d9e6..20b60e9a0d 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -654,7 +654,6 @@ void southbridge_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); - acpi_mainboard_gnvs(gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); @@ -707,10 +706,6 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) return GPE0_REG_MAX; } -__weak void acpi_mainboard_gnvs(global_nvs_t *gnvs) -{ -} - const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 9b0369773d..02352f3685 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -15,7 +15,6 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_mainboard_gnvs(global_nvs_t *gnvs); void southbridge_inject_dsdt(const struct device *device); unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); From 8c92bcc966ebdc39cdb813b1432a3e9d821073ff Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 Apr 2020 12:57:45 -0700 Subject: [PATCH 1441/1463] vboot: Provide declaration for verstage_mainboard_early_init() Similar to bootblock, provide declaration for verstage_mainboard_early_init() to support early mainboard initialization if verstage is run before bootblock. BUG=b:155824234 TEST=Verified that trembyle still builds Signed-off-by: Furquan Shaikh Change-Id: I106213ecc1c44100f1f74071189518563ac08121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41137 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/security/vboot/vboot_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index f25ee46b6f..a260475071 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -43,6 +43,7 @@ int vboot_retrieve_hash(void *digest, size_t digest_size); * If the verstage is a separate stage, it should be entered via main(). */ void verstage_main(void); +void verstage_mainboard_early_init(void); void verstage_mainboard_init(void); /* Check boot modes */ From 132384aa4c71b5e8443834d872af89cfbff89376 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 07:19:50 +0200 Subject: [PATCH 1442/1463] sb/intel/i82371eb: Replace GPLv2 long form headers with SPDX header Change-Id: If54234ec2d80d5a6502400eb1c6f02dd9bba73c5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41129 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/southbridge/intel/i82371eb/fadt.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 3240221eff..77801e45b4 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -1,17 +1,8 @@ /* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Based on src/southbridge/via/vt8237r/vt8237_fadt.c - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include From e4fc65bf746fe79babd03ce4d8efc54219b471b4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 07:26:54 +0200 Subject: [PATCH 1443/1463] soc/intel: Replace GPLv2 long form headers with SPDX header Change-Id: I468d2ba85033c41ba53333ebbfd6f4108a36e407 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41130 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/include/soc/gpio_apl.h | 16 +++------------- src/soc/intel/apollolake/include/soc/gpio_glk.h | 17 +++-------------- .../intel/denverton_ns/include/soc/romstage.h | 14 +------------- src/soc/intel/icelake/me.c | 13 +------------ src/soc/intel/tigerlake/me.c | 13 +------------ 5 files changed, 9 insertions(+), 64 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/gpio_apl.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h index 9c02b50fff..56cfadd837 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_apl.h +++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h @@ -1,21 +1,11 @@ +/* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Definitions for the GPIO subsystem on Apollolake * * Placed in a separate file since some of these definitions can be used from * assembly code - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _SOC_APOLLOLAKE_GPIO_H_ diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h index d704757346..9eb3fac415 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_glk.h +++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h @@ -1,20 +1,9 @@ +/* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* - * * Placed in a separate file since some of these definitions can be used from * assembly code - * - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _SOC_GLK_GPIO_H_ diff --git a/src/soc/intel/denverton_ns/include/soc/romstage.h b/src/soc/intel/denverton_ns/include/soc/romstage.h index 66f86ee0cc..4b1a1e5bbb 100644 --- a/src/soc/intel/denverton_ns/include/soc/romstage.h +++ b/src/soc/intel/denverton_ns/include/soc/romstage.h @@ -1,17 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_DENVERTON_NS_ROMSTAGE_H_ #define _SOC_DENVERTON_NS_ROMSTAGE_H_ diff --git a/src/soc/intel/icelake/me.c b/src/soc/intel/icelake/me.c index 05ed199bd7..426015a152 100644 --- a/src/soc/intel/icelake/me.c +++ b/src/soc/intel/icelake/me.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * Copyright (C) 2020 Google LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index a6ebcc317a..357fb92e8d 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -1,16 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * Copyright (C) 2020 Google LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include From 231b251a3e030b6fbd56412a31539821c7505379 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 07:29:44 +0200 Subject: [PATCH 1444/1463] soc/qualcomm: Replace GPLv2 long form headers with SPDX header Change-Id: Ib51e5e9c6159e9b3c2890d0455343bcc0c14b6fe Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41131 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/qualcomm/sc7180/include/soc/qupv3_config.h | 11 +---------- src/soc/qualcomm/sc7180/qupv3_config.c | 11 +---------- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h index 941f6565c3..9c2a4f51f2 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SC7180_QUPV3_CONFIG_H_ #define _SC7180_QUPV3_CONFIG_H_ diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 15b6b4dbe9..90accd5772 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -1,14 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include From 16bc46c7adb23fd0cec8eadc014bb1b0adbd7916 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 07:42:04 +0200 Subject: [PATCH 1445/1463] soc/nvidia: Replace GPLv2 long form headers with SPDX header Change-Id: I7cc9adc95af5a8fc3cd69462d49efb1550e30295 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41133 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/nvidia/tegra124/include/soc/sor.h | 13 ++----------- src/soc/nvidia/tegra210/include/soc/sor.h | 13 ++----------- 2 files changed, 4 insertions(+), 22 deletions(-) diff --git a/src/soc/nvidia/tegra124/include/soc/sor.h b/src/soc/nvidia/tegra124/include/soc/sor.h index d998f8425c..1821ccd3b2 100644 --- a/src/soc/nvidia/tegra124/include/soc/sor.h +++ b/src/soc/nvidia/tegra124/include/soc/sor.h @@ -1,17 +1,8 @@ /* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * drivers/video/tegra/dc/sor_regs.h - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #ifndef __TEGRA124_SOR_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/sor.h b/src/soc/nvidia/tegra210/include/soc/sor.h index bb25c46833..129089ed36 100644 --- a/src/soc/nvidia/tegra210/include/soc/sor.h +++ b/src/soc/nvidia/tegra210/include/soc/sor.h @@ -1,17 +1,8 @@ /* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * drivers/video/tegra/dc/sor_regs.h - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #ifndef __TEGRA210_SOR_H__ From 3a7346c729f3da5ebd58dd55445a7729e891020b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 07:46:17 +0200 Subject: [PATCH 1446/1463] cpu/x86/mtrr: Replace GPLv2 long form headers with SPDX header Change-Id: I9d97cac214f04604f956cd9eee1e281b75c93645 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41134 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/x86/mtrr/mtrr.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 2698708516..53b640088b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -1,15 +1,7 @@ /* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * mtrr.c: setting MTRR to decent values for cache initialization on P6 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel * From d72155d507a9e4f47261e682de50f601c396cd6f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 07:51:34 +0200 Subject: [PATCH 1447/1463] {drivers,ec/kontron}: Replace GPLv2 long form headers with SPDX header Change-Id: Ide6cfd6f79bd54f50d9fde37c55f2b0df702478a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41135 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../intel/fsp2_0/header_util/fspupdvpd.spatch | 12 +----------- src/drivers/usb/ehci.h | 12 +----------- src/ec/kontron/kempld/kempld_i2c.c | 13 +++---------- 3 files changed, 5 insertions(+), 32 deletions(-) diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch index 502db14189..a9a02a254c 100644 --- a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This semantic patch is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Semantic patch for fspupdvpd_sanitize.sh. Please call the script directly. */ diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index d2129016ce..2a83bd8f67 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -1,15 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* This came from the Linux kernel (include/linux/usb/ehci_def.h). */ diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index 56283eacc4..e5f40e7e7f 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -1,18 +1,11 @@ +/* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * I2C bus driver for Kontron COM modules * * Based on the similar driver in Linux. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License 2 as published - * by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ #include #include From 081c4d5e91e1b47e493eb82816f9066e1a9c42dc Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 07:53:59 +0200 Subject: [PATCH 1448/1463] lib/rtc.c: Replace GPLv2 long form headers with SPDX header Change-Id: I812f81307c68a9383619f185633e0a8423319f22 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41136 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/lib/rtc.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/src/lib/rtc.c b/src/lib/rtc.c index 018897b505..96aba243cd 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -1,16 +1,7 @@ /* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * From U-Boot 2016.05 */ From 42eda83cf694d1ca5b1f5a777283ec889a389dbc Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 11:18:05 +0200 Subject: [PATCH 1449/1463] mainboard/*/*.spd.hex: Replace GPLv2 long form headers with SPDX header Change-Id: I3eb39d985f2712ab0a7a5a76b06ed625eb51c9d0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41140 Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks Reviewed-by: Wim Vervoorn Tested-by: build bot (Jenkins) --- src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex | 12 +----------- src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex | 12 +----------- src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex | 12 +----------- src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex | 12 +----------- src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex | 12 +----------- .../fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex | 13 +------------ .../fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex | 13 +------------ .../fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex | 13 +------------ .../gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex | 12 +----------- .../pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex | 11 +---------- .../pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex | 11 +---------- .../m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex | 13 +------------ .../m107/spd/MICRON_MT41K512M16HA-125A.spd.hex | 13 +------------ .../m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex | 13 +------------ 14 files changed, 14 insertions(+), 158 deletions(-) diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex index f214570540..b24869abc4 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex @@ -1,15 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC # BAP ODE E20XX has 2GB RAM soldered down on the Q7 diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex index 5ba55243df..03ad686085 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex @@ -1,15 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC # BAP ODE E20XX has 2GB RAM soldered down on the Q7 diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex index 950ccf4125..83dcd7f498 100644 --- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex @@ -1,15 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC # BAP ODE E21XX has 2GB RAM soldered down on the Q7 diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex index 09444d9359..68e166b4ef 100644 --- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex @@ -1,15 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC # BAP ODE E21XX has 2GB RAM soldered down on the Q7 diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex index 5c98dfe7b9..8aeaf8fa00 100644 --- a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex @@ -1,15 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC # BAP ODE E21XX has 2GB RAM soldered down on the Q7 diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex index fa56b54d96..6d65b294c9 100644 --- a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only # # 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex index 410ca84659..52a8d95387 100644 --- a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only # # 8 Gb DDR3 (1600 MHz 11-11-11) Micron MT41K512M16HA-125:A diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index ef862dab48..6e7beec35d 100644 --- a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only # # 8 Gb DDR3 (1600 MHz 11-11-11) Samsung K4B8G1646D-MYK0 diff --git a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex b/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex index 39a764772a..b95158b8d8 100644 --- a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex +++ b/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex @@ -1,15 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips # The datasheet is available at: diff --git a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex index c9138c05b3..05c5053966 100644 --- a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex +++ b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex @@ -1,14 +1,5 @@ -# # This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # HYNIX-H5TQ2G83CFR diff --git a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex index f091d6b294..3ef574677c 100644 --- a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex +++ b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex @@ -1,14 +1,5 @@ -# # This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only # HYNIX-H5TQ4G83MFR diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex index fa56b54d96..6d65b294c9 100644 --- a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only # # 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex index 410ca84659..52a8d95387 100644 --- a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only # # 8 Gb DDR3 (1600 MHz 11-11-11) Micron MT41K512M16HA-125:A diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index ef862dab48..6e7beec35d 100644 --- a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only # # 8 Gb DDR3 (1600 MHz 11-11-11) Samsung K4B8G1646D-MYK0 From a7e06800d61b9d6e7727be55d4aa2443d851a339 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 11:24:30 +0200 Subject: [PATCH 1450/1463] mainboard/*/*/*.asl: Replace GPLv2 long form headers with SPDX header Change-Id: I5970cd188d06214d410949f4a3f8816c85c39451 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41141 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asrock/b85m_pro4/acpi/superio.asl | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl index 37926305a2..8cb29eacad 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -1,17 +1,5 @@ /* This file is part of the coreboot project. */ -/* - * Copyright (C) 2018 Tristan Corrick - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x2e From 8741510d83401296cfe9cfe5809088c805a9eb09 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 11:49:08 +0200 Subject: [PATCH 1451/1463] southbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX header Change-Id: I339b455683ad481720b67a322bf51c891c2b611d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41142 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/Kconfig | 13 +------------ src/southbridge/amd/agesa/hudson/Kconfig | 15 ++------------- src/southbridge/amd/cimx/Kconfig | 13 +------------ src/southbridge/amd/cimx/sb800/Kconfig | 15 ++------------- src/southbridge/amd/pi/Kconfig | 13 +------------ src/southbridge/amd/pi/hudson/Kconfig | 15 ++------------- src/southbridge/intel/common/firmware/Kconfig | 15 ++------------- src/southbridge/intel/i82801dx/Kconfig | 16 ++-------------- src/southbridge/intel/i82801gx/Kconfig | 15 ++------------- src/southbridge/intel/i82801ix/Kconfig | 15 ++------------- src/southbridge/intel/i82801jx/Kconfig | 15 ++------------- src/southbridge/intel/ibexpeak/Kconfig | 15 ++------------- src/southbridge/ricoh/rl5c476/Kconfig | 15 ++------------- src/southbridge/ti/pci7420/Kconfig | 15 ++------------- src/southbridge/ti/pcixx12/Kconfig | 15 ++------------- 15 files changed, 27 insertions(+), 193 deletions(-) diff --git a/src/southbridge/amd/agesa/Kconfig b/src/southbridge/amd/agesa/Kconfig index 432d90b8cd..03673bcaab 100644 --- a/src/southbridge/amd/agesa/Kconfig +++ b/src/southbridge/amd/agesa/Kconfig @@ -1,15 +1,4 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only source "src/southbridge/amd/agesa/hudson/Kconfig" diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 5e56db434f..5f672bbf07 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_AMD_AGESA_HUDSON bool diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 6fdd86fc58..0a0d402d7b 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only config AMD_SB_CIMX bool diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index e50f7391ac..e9d0709716 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_AMD_CIMX_SB800 bool diff --git a/src/southbridge/amd/pi/Kconfig b/src/southbridge/amd/pi/Kconfig index 0b48d192cb..1ede95c37c 100644 --- a/src/southbridge/amd/pi/Kconfig +++ b/src/southbridge/amd/pi/Kconfig @@ -1,15 +1,4 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only source "src/southbridge/amd/pi/hudson/Kconfig" diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 84031c16ed..cfc9148d54 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_AMD_PI_BOLTON bool diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index d72ff76b18..2af798d9f8 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config HAVE_INTEL_FIRMWARE bool diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 1ed45043f8..007d5431a4 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_INTEL_I82801DX bool diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index e57a3ea2a8..ecdecc1be8 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_INTEL_I82801GX bool diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 7f69845336..8bb7ce30c2 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_INTEL_I82801IX bool diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 1d175ab803..490af23a6e 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_INTEL_I82801JX bool diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 856dc61487..93f489618d 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_INTEL_IBEXPEAK bool diff --git a/src/southbridge/ricoh/rl5c476/Kconfig b/src/southbridge/ricoh/rl5c476/Kconfig index 77d88662c7..8453cfaf14 100644 --- a/src/southbridge/ricoh/rl5c476/Kconfig +++ b/src/southbridge/ricoh/rl5c476/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_RICOH_RL5C476 bool diff --git a/src/southbridge/ti/pci7420/Kconfig b/src/southbridge/ti/pci7420/Kconfig index 3ff9f21c65..15c3ae0adf 100644 --- a/src/southbridge/ti/pci7420/Kconfig +++ b/src/southbridge/ti/pci7420/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_TI_PCI7420 bool diff --git a/src/southbridge/ti/pcixx12/Kconfig b/src/southbridge/ti/pcixx12/Kconfig index 55736fb56c..ff96e4e83c 100644 --- a/src/southbridge/ti/pcixx12/Kconfig +++ b/src/southbridge/ti/pcixx12/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOUTHBRIDGE_TI_PCIXX12 bool From 36787b0e7ba5d902fd5a851e960555c8077abbbb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 12:07:24 +0200 Subject: [PATCH 1452/1463] northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX header Change-Id: Ief2fdedbdba3b7d1708adb2519eb01242e9b52ab Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41144 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/amd/agesa/Kconfig | 13 +------------ src/northbridge/amd/agesa/family14/Kconfig | 16 +++------------- src/northbridge/amd/agesa/family15tn/Kconfig | 16 +++------------- src/northbridge/amd/agesa/family16kb/Kconfig | 16 +++------------- src/northbridge/amd/pi/00630F01/Kconfig | 16 +++------------- src/northbridge/amd/pi/00660F01/Kconfig | 16 +++------------- src/northbridge/amd/pi/00730F01/Kconfig | 16 +++------------- src/northbridge/amd/pi/Kconfig | 13 +------------ src/northbridge/intel/e7505/Kconfig | 15 ++------------- src/northbridge/intel/gm45/Kconfig | 15 ++------------- src/northbridge/intel/haswell/Kconfig | 15 ++------------- src/northbridge/intel/i440bx/Kconfig | 15 ++------------- src/northbridge/intel/i945/Kconfig | 15 ++------------- src/northbridge/intel/ironlake/Kconfig | 15 ++------------- src/northbridge/intel/pineview/Kconfig | 15 ++------------- src/northbridge/intel/x4x/Kconfig | 15 ++------------- 16 files changed, 36 insertions(+), 206 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 1e0153b335..42085c494c 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_AMD_AGESA bool diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 96f75ca8d9..7f10193f7b 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -1,16 +1,6 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 6c24f8774d..ec139b6572 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -1,16 +1,6 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 739668b639..15c1b87ed3 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -1,16 +1,6 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 8eb3205ef3..b78cd78a23 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -1,16 +1,6 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config NORTHBRIDGE_AMD_PI_00630F01 bool diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index 105fbc83db..e47d20d68b 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -1,16 +1,6 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config NORTHBRIDGE_AMD_PI_00660F01 bool diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index cdc974a900..b2a101f3e6 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -1,16 +1,6 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config NORTHBRIDGE_AMD_PI_00730F01 bool diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 74c993b4e7..05f3bece88 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -1,16 +1,5 @@ -# # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_AMD_PI bool diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index b056fa7d4c..0e49a21b4d 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_E7505 bool diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 8857bd4f9b..7edea51dfd 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_GM45 bool diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 06ce371946..972b3c996a 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_HASWELL bool diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 0161eb3020..d8a81934fc 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_I440BX bool diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 4690a54609..2c83be420f 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_I945 bool diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 9d937965dd..30370f89b0 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_IRONLAKE bool diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index f7ffa87ead..181846fdc1 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_PINEVIEW bool diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8c0be74bf2..82fce8f61e 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config NORTHBRIDGE_INTEL_X4X bool From f7b2fe6b6494fd98030bbb08cd57814625ceae3a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 12:38:15 +0200 Subject: [PATCH 1453/1463] {security,soc}/*/Kconfig: Replace GPLv2 long form headers with SPDX header Change-Id: Ie3721f6a93dacb8014f93aa86780d51a659a68df Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/security/Kconfig | 14 ++------------ src/security/intel/Kconfig | 14 ++------------ src/security/intel/txt/Kconfig | 14 ++------------ src/security/memory/Kconfig | 14 ++------------ src/security/tpm/Kconfig | 14 ++------------ src/security/tpm/tss/vendor/cr50/Kconfig | 14 ++------------ src/security/vboot/Kconfig | 14 ++------------ src/soc/intel/denverton_ns/Kconfig | 15 ++------------- src/soc/intel/quark/Kconfig | 15 ++------------- src/soc/intel/xeon_sp/Kconfig | 16 ++-------------- src/soc/rockchip/rk3288/Kconfig | 15 ++------------- src/soc/sifive/fu540/Kconfig | 11 +---------- 12 files changed, 23 insertions(+), 147 deletions(-) diff --git a/src/security/Kconfig b/src/security/Kconfig index 65d2defe7d..e45cc641b7 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -1,15 +1,5 @@ -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig index 01410371ba..4f59772c49 100644 --- a/src/security/intel/Kconfig +++ b/src/security/intel/Kconfig @@ -1,15 +1,5 @@ -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only source "src/security/intel/txt/Kconfig" source "src/security/intel/stm/Kconfig" diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 04c2b6d4cb..095b108bf1 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -1,15 +1,5 @@ -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config INTEL_TXT bool "Intel TXT support" diff --git a/src/security/memory/Kconfig b/src/security/memory/Kconfig index 29ca5c86e7..ede65442c5 100644 --- a/src/security/memory/Kconfig +++ b/src/security/memory/Kconfig @@ -1,15 +1,5 @@ -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only menu "Memory initialization" diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 359b8f11f3..2dc32b0f85 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -1,15 +1,5 @@ -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only source "src/security/tpm/tss/vendor/cr50/Kconfig" diff --git a/src/security/tpm/tss/vendor/cr50/Kconfig b/src/security/tpm/tss/vendor/cr50/Kconfig index 637669d3d2..94b3b83b62 100644 --- a/src/security/tpm/tss/vendor/cr50/Kconfig +++ b/src/security/tpm/tss/vendor/cr50/Kconfig @@ -1,15 +1,5 @@ -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config TPM_CR50 bool diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index f273265054..39b687df92 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -1,15 +1,5 @@ -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only menu "Verified Boot (vboot)" diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 5f2c5aa881..44cc3aedeb 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOC_INTEL_DENVERTON_NS bool diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 3c3dd35393..b6ac3b8ee4 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOC_INTEL_QUARK bool diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index b10c7bee10..ea3f56590b 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-or-later source "src/soc/intel/xeon_sp/skx/Kconfig" source "src/soc/intel/xeon_sp/cpx/Kconfig" diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index d7514f9c31..c404548c78 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -1,16 +1,5 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only config SOC_ROCKCHIP_RK3288 bool diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index b7464ad1fa..d8d48a260e 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -1,14 +1,5 @@ # This file is part of the coreboot project. -# -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0-only config SOC_SIFIVE_FU540 bool From e91af4dc159accb63f341482fbec0728cb20a4ee Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 7 May 2020 00:39:50 +0200 Subject: [PATCH 1454/1463] sb/intel/*/me_status.c: Fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Looks like someone couldn't decide between `enter` and `entry`. According to ME documentation, it should be the latter, so fix it. Change-Id: I971fb667264be97cdffa2b2b0e155f5dcacdaab7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41108 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel --- src/southbridge/intel/bd82x6x/me_status.c | 2 +- src/southbridge/intel/lynxpoint/me_status.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index a19fc01fd9..a429f488cb 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -106,7 +106,7 @@ static const char *me_progress_bup_values[] = { /* Progress Code 3 states */ static const char *me_progress_policy_values[] = { - [0x00] = "Entery into Policy Module", + [0x00] = "Entry into Policy Module", [0x03] = "Received S3 entry", [0x04] = "Received S4 entry", [0x05] = "Received S5 entry", diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 6cb187e1b0..b63de4e6c7 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -107,7 +107,7 @@ static const char *me_progress_bup_values[] = { /* Progress Code 3 states */ static const char *me_progress_policy_values[] = { - [ME_HFS2_STATE_POLICY_ENTRY] = "Entery into Policy Module", + [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module", [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", From d8abb266f45e573967f4375c289998fb844e90a4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 7 May 2020 00:48:35 +0200 Subject: [PATCH 1455/1463] nb/intel/haswell/northbridge.c: Fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `TESGMB` => `TSEGMB` Change-Id: Id48bed068f9d2be7201e7fa120b00608f6fe2f98 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41109 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel --- src/northbridge/intel/haswell/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 552f032de5..099e7f0dc0 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -255,7 +255,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), }; static void mc_read_map_entries(struct device *dev, uint64_t *values) From 6cd6e71b71d4314bfc3dd8aeccc3f5c3c6364c13 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 7 May 2020 00:54:42 +0200 Subject: [PATCH 1456/1463] sb/intel/bd82x6x: Do cosmetic fixes Make the code follow the coding style, and reflow things that fit in 96 characters. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41110 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel --- src/southbridge/intel/bd82x6x/early_pch.c | 20 +++++-------- src/southbridge/intel/bd82x6x/early_rcba.c | 6 ++-- src/southbridge/intel/bd82x6x/early_thermal.c | 29 +++++++++---------- 3 files changed, 22 insertions(+), 33 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 530f11affa..bd507c489b 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -19,15 +19,13 @@ #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) -static void -wait_iobp(void) +static void wait_iobp(void) { while (RCBA8(IOBPS) & 1) ; // implement timeout? } -static u32 -read_iobp(u32 address) +static u32 read_iobp(u32 address) { u32 ret; @@ -40,8 +38,7 @@ read_iobp(u32 address) return ret; } -static void -write_iobp(u32 address, u32 val) +static void write_iobp(u32 address, u32 val) { /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function @@ -137,11 +134,9 @@ void early_pch_init_native_dmi_post(void) ; } -void -early_pch_init_native (void) +void early_pch_init_native(void) { - pci_write_config8 (SOUTHBRIDGE, 0xa6, - pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); + pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2); RCBA32(CIR1) = 0x00109000; RCBA32(REC); // !!! = 0x00000000 @@ -278,9 +273,8 @@ static void pch_enable_lpc_decode(void) * - 0x3f8-0x3ff COMA */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 915a93599c..61877bb93d 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -5,8 +5,7 @@ #include #include "pch.h" -void -southbridge_configure_default_intmap(void) +void southbridge_configure_default_intmap(void) { /* * For the PCH internal PCI functions, provide a reasonable @@ -83,8 +82,7 @@ southbridge_configure_default_intmap(void) (void) RCBA16(OIC); } -void -southbridge_rcba_config(void) +void southbridge_rcba_config(void) { RCBA32(FD) = PCH_DISABLE_ALWAYS; } diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index ac7a3a4c90..e73f3a5908 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -36,34 +36,31 @@ void early_thermal_init(void) pci_write_config32(dev, 0x44, 0x0); /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) | 5); + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); - write16p (0x40000004, 0x3a2b); - write8p (0x4000000c, 0xff); - write8p (0x4000000d, 0x00); - write8p (0x4000000e, 0x40); - write8p (0x40000082, 0x00); - write8p (0x40000001, 0xba); + write16p(0x40000004, 0x3a2b); + write8p(0x4000000c, 0xff); + write8p(0x4000000d, 0x00); + write8p(0x4000000e, 0x40); + write8p(0x40000082, 0x00); + write8p(0x40000001, 0xba); /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); - /* Northbridge temperature slope and offset. */ + /* Northbridge temperature slope and offset */ write16p(0x40000016, 0x808c); - write16p (0x40000014, 0xde87); + write16p(0x40000014, 0xde87); - /* Enable thermal data reporting, processor, PCH and northbridge. */ + /* Enable thermal data reporting, processor, PCH and northbridge */ write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); - /* Disable temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) & ~1); + /* Disable temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_write_config32(dev, 0x40, 0); - write32 (DEFAULT_RCBA + 0x38b0, - (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); + write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); } From 1efa7d90933e64e309c79fe1f9aa3f3033930e0e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 7 May 2020 00:59:32 +0200 Subject: [PATCH 1457/1463] sb/intel/bd82x6x: Put temp BAR in a define We use a temporary BAR value to program the thermal settings. To make this more obvious, factor it out. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: Icda6e4100d954fe28d2624270b5d7ab7ed155e32 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41111 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/bd82x6x/early_thermal.c | 25 +++++++++++-------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index e73f3a5908..60c08d136d 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -22,6 +22,9 @@ static uint16_t read16p (uintptr_t addr) return read16((u16 *)addr); } +/* Temporary address for the thermal BAR */ +#define TBARB_TEMP 0x40000000 + /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) @@ -32,31 +35,31 @@ void early_thermal_init(void) dev = PCI_DEV(0x0, 0x1f, 0x6); /* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); + pci_write_config32(dev, 0x40, TBARB_TEMP); pci_write_config32(dev, 0x44, 0x0); /* Activate temporary BAR. */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); + write16p(TBARB_TEMP + 0x04, 0x3a2b); - write16p(0x40000004, 0x3a2b); - write8p(0x4000000c, 0xff); - write8p(0x4000000d, 0x00); - write8p(0x4000000e, 0x40); - write8p(0x40000082, 0x00); - write8p(0x40000001, 0xba); + write8p(TBARB_TEMP + 0x0c, 0xff); + write8p(TBARB_TEMP + 0x0d, 0x00); + write8p(TBARB_TEMP + 0x0e, 0x40); + write8p(TBARB_TEMP + 0x82, 0x00); + write8p(TBARB_TEMP + 0x01, 0xba); /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset */ - write16p(0x40000016, 0x808c); + write16p(TBARB_TEMP + 0x16, 0x808c); - write16p(0x40000014, 0xde87); + write16p(TBARB_TEMP + 0x14, 0xde87); /* Enable thermal data reporting, processor, PCH and northbridge */ - write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); + write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0); /* Disable temporary BAR */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); From 8211bde9c2a2cf80b82573df6122ca4dd3c764cf Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 6 May 2020 13:20:13 -0700 Subject: [PATCH 1458/1463] memrange: Update comment to indicate limit is inclusive for memranges_next_entry This change updates the comment for memranges_next_entry() to indicate that the limit provided by the caller is inclusive. Change-Id: Id40263efcb9417ed31c130996e56c30dbbc82e02 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41103 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/memrange.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/memrange.h b/src/include/memrange.h index deb8c1e5de..83e3826f2c 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -162,7 +162,7 @@ struct range_entry *memranges_next_entry(struct memranges *ranges, const struct range_entry *r); /* Steals memory from the available list in given ranges as per the constraints: - * limit = Upper bound for the memory range to steal. + * limit = Upper bound for the memory range to steal (Inclusive). * size = Requested size for the stolen memory. * align = Required alignment(log 2) for the starting address of the stolen memory. * tag = Use a range that matches the given tag. From f8f5650873451f64eab84d4b20248419bc19a0f5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 6 May 2020 13:18:05 -0700 Subject: [PATCH 1459/1463] memrange: Break early from memranges_find_entry if limit is crossed This change updates memranges_find_entry() to break and return early if the end address of the hole within the current range entry crosses the requested limit. This is because all range entries and maintained in increasing order and so none of the following range entries can satisfy the given request. Change-Id: I14e03946ddbbb5d254b23e9a9917da42960313a6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/lib/memrange.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 32f053de08..bc827d3635 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -400,8 +400,13 @@ static const struct range_entry *memranges_find_entry(struct memranges *ranges, if (end > r->end) continue; + /* + * If end for the hole in the current range entry goes beyond the requested + * limit, then none of the following ranges can satisfy this request because all + * range entries are maintained in increasing order. + */ if (end > limit) - continue; + break; return r; } From 71a131415e2063d0e8414782b263e04bb5dc818b Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 6 May 2020 11:11:03 -0700 Subject: [PATCH 1460/1463] security: tcg-2.0: Ignore data payload for errors, fix Cr50 boot mode This patch improves the response buffer handling for TPM 2.0. Previously we would allow any command to return no payload, but if there was a payload we would always try to unmarshal it according to the normal success response. This was sort of relying on the fact that the TPM usually returns no additional data after the header for error responses, but in practice that is not always true. It also means that commands without a response payload accidentally work by default even though we did not explicitly add unmarshallig support for them, which seems undesirable. Adding explicit unmarshalling support for TPM2_SelfTest which was only supported through this loophole before. This patch changes the behavior to always accept any amount of payload data for error responses but not unmarshal any of it. None of our use cases actually care about payload data for errors, so it seems safer to not even try to interpret it. For success responses, on the other hand, we always require support for the command to be explicitly added. This fixes a problem with the Cr50 GET_BOOT_MODE command where an error response would only return the subcommand code but no data after that. Also add support for a second, slightly different NO_SUCH_COMMAND error code that was added in Cr50 recently. Signed-off-by: Julius Werner Change-Id: Ib85032d85482d5484180be6fd105f2467f393cd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41100 Reviewed-by: Vadim Bendebury Reviewed-by: Andrey Pronin Tested-by: build bot (Jenkins) --- src/security/tpm/tss/tcg-2.0/tss_marshaling.c | 18 ++++++++++++------ src/security/tpm/tss/vendor/cr50/cr50.c | 6 ++++-- src/security/tpm/tss/vendor/cr50/cr50.h | 1 + 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index a229dd17ef..eff1acd2cd 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -587,17 +587,23 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) if (rc != 0) return NULL; - if (ibuf_remaining(ib) == 0) { - if (tpm2_static_resp.hdr.tpm_size != ibuf_nr_read(ib)) - printk(BIOS_ERR, - "%s: size mismatch in response to command %#x\n", - __func__, command); - return &tpm2_static_resp; + if (ibuf_capacity(ib) != tpm2_static_resp.hdr.tpm_size) { + printk(BIOS_ERR, + "%s: size mismatch in response to command %#x\n", + __func__, command); + return NULL; } + /* On errors, we're not sure what the TPM is returning. None of the + commands we use actually expect useful data payloads for errors, so + just ignore any data after the header. */ + if (tpm2_static_resp.hdr.tpm_code != TPM2_RC_SUCCESS) + return &tpm2_static_resp; + switch (command) { case TPM2_Startup: case TPM2_Shutdown: + case TPM2_SelfTest: break; case TPM2_GetCapability: diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index ae2f7c2516..d7bf48d711 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -89,7 +89,8 @@ uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode) return TPM_E_MUST_REBOOT; } - if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND) { + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND || + response->hdr.tpm_code == VENDOR_RC_NO_SUCH_SUBCOMMAND) { /* * Explicitly inform caller when command is not supported */ @@ -119,7 +120,8 @@ uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode) if (!response) return TPM_E_IOERROR; - if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND) + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND || + response->hdr.tpm_code == VENDOR_RC_NO_SUCH_SUBCOMMAND) /* Explicitly inform caller when command is not supported */ return TPM_E_NO_SUCH_COMMAND; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 0f91732856..e3146a421f 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -21,6 +21,7 @@ #define VENDOR_RC_ERR 0x00000500 enum cr50_vendor_rc { VENDOR_RC_INTERNAL_ERROR = (VENDOR_RC_ERR | 6), + VENDOR_RC_NO_SUCH_SUBCOMMAND = (VENDOR_RC_ERR | 8), VENDOR_RC_NO_SUCH_COMMAND = (VENDOR_RC_ERR | 127), }; From 0cdc97cdd9a767bfe6e43ff4317796298976c457 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Tue, 5 May 2020 20:42:59 -0400 Subject: [PATCH 1461/1463] sb/intel/i82371eb: Fix iasl warning The backslash on the very last line is not needed and causes an iasl warning. Change-Id: I27e78bc34b9386dd014db5880a104693b4f0db5a Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/41094 Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82371eb/acpi/intx.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl index c1dc508a96..fe2c180a26 100644 --- a/src/southbridge/intel/i82371eb/acpi/intx.asl +++ b/src/southbridge/intel/i82371eb/acpi/intx.asl @@ -45,4 +45,4 @@ Device(intx) { \ } \ Store(Local0, pinx) \ } \ -} \ +} From 192a12fb6ab0b4a2033f087cec8a232d42a4c000 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 6 May 2020 10:52:55 +0200 Subject: [PATCH 1462/1463] commonlib/region: Add region_overlap Add inline function to check if two regions overlap. Change-Id: I6f3dfaa9f0805893bd691ba64f112944d89a8e71 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/41083 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Angel Pons --- src/commonlib/include/commonlib/region.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 86b9ee39cc..08b9191a66 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -7,6 +7,7 @@ #include #include #include +#include #include /* @@ -117,6 +118,12 @@ static inline size_t region_end(const struct region *r) return region_offset(r) + region_sz(r); } +static inline bool region_overlap(const struct region *r1, const struct region *r2) +{ + return (region_end(r1) > region_offset(r2)) && + (region_offset(r1) < region_end(r2)); +} + static inline const struct region *region_device_region( const struct region_device *rdev) { From 29fbfcc472462e317e5dcf659523689f28bbfd98 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Mar 2020 15:54:43 -0800 Subject: [PATCH 1463/1463] vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled() vboot_recovery_mode_enabled() was recently changed to assert() when it is called before vboot logic has run, because we cannot determine whether we're going to be in recovery mode at that point and we wanted to flush out existing uses that pretended that we could. Turns out there are a bunch of uses like that, and there is some code that is shared across configurations that can and those that can't. This patch cleans them up to either remove checks that cannot return true, or add explicit Kconfig guards to clarify that the code is shared. This means that using a separate recovery MRC cache is no longer supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already been broken with CB:38780, but with this patch those boards will boot again using their normal MRC caches rather than just die). Skipping the MRC cache and always regenerating from scratch in recovery mode is likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE. For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and that is unlikely to change in the future so we will just hardcode that fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed to work around this issue). Signed-off-by: Julius Werner Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp1_1/Kconfig | 1 + src/drivers/intel/fsp1_1/raminit.c | 6 +-- src/drivers/mrc_cache/Kconfig | 1 + src/drivers/mrc_cache/mrc_cache.c | 2 +- src/northbridge/intel/haswell/raminit.c | 3 +- .../intel/sandybridge/raminit_mrc.c | 3 +- src/soc/intel/baytrail/romstage/raminit.c | 4 +- src/soc/intel/broadwell/romstage/raminit.c | 3 +- src/southbridge/intel/bd82x6x/me_8.x.c | 46 ------------------- 9 files changed, 12 insertions(+), 57 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 7c69888ea1..304cbae31b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -13,6 +13,7 @@ config PLATFORM_USES_FSP1_1 bool + depends on !VBOOT_STARTS_IN_BOOTBLOCK select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MICROCODE_UPDATE_PRE_RAM diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index a090a1fce5..edae755ad3 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -12,7 +12,6 @@ #include /* hexdump */ #include #include -#include void raminit(struct romstage_params *params) { @@ -246,11 +245,10 @@ void raminit(struct romstage_params *params) /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); - if (mrc_hob == NULL) + if (mrc_hob == NULL) { printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); - else if (!vboot_recovery_mode_enabled()) { - /* Do not save MRC data in recovery path */ + } else { params->data_to_save = GET_GUID_HOB_DATA(mrc_hob); params->data_to_save_size = ALIGN_UP( ((u32)GET_HOB_LENGTH(mrc_hob)), 16); diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 543f310e66..79cc205a9d 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -19,6 +19,7 @@ config HAS_RECOVERY_MRC_CACHE config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN bool + depends on VBOOT_STARTS_IN_BOOTBLOCK default n config MRC_SETTINGS_VARIABLE_DATA diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 2b63129435..d7fd32807a 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -95,7 +95,7 @@ static const struct cache_region *lookup_region_type(int type) int i; int flags; - if (vboot_recovery_mode_enabled()) + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) flags = RECOVERY_FLAG; else flags = NORMAL_FLAG; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9fff58eb21..ddb2f83314 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -112,7 +112,8 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); /* Do not pass MRC data in for recovery mode boot, always pass it in for S3 resume */ - if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) + if (!(CONFIG(HASWELL_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) + || pei_data->boot_mode == 2) prepare_mrc_cache(pei_data); /* If MRC data is not found, we cannot continue S3 resume */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index ae95efa81d..2178c9d2ff 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -139,7 +139,8 @@ void sdram_initialize(struct pei_data *pei_data) * Do not pass MRC data in for recovery mode boot, * Always pass it in for S3 resume. */ - if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) + if (!(CONFIG(SANDYBRIDGE_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) || + pei_data->boot_mode == 2) prepare_mrc_cache(pei_data); /* If MRC data is not found we cannot continue S3 resume. */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 68b8c0e0bb..88b61de8cb 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -132,9 +132,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) if (!mp->io_hole_mb) mp->io_hole_mb = 2048; - if (vboot_recovery_mode_enabled()) { - printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { + if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { mp->saved_data_size = region_device_sz(&rdev); mp->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 78081fe54a..c59390857c 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -36,7 +36,8 @@ void raminit(struct pei_data *pei_data) broadwell_fill_pei_data(pei_data); - if (vboot_recovery_mode_enabled()) { + if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) && + vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index d240bf65d5..b529fe295f 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -403,38 +403,6 @@ static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("Wireless LAN (WLAN)", cap->wlan); } -#if CONFIG(CHROMEOS) && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -static int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - struct mei_header mei = { - .is_complete = 1, - .length = sizeof(mkhi) + sizeof(reset), - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - }; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); - if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { @@ -683,20 +651,6 @@ static void intel_me_init(struct device *dev) if (intel_me_read_mbp(&mbp_data)) break; -#if CONFIG(CHROMEOS) && 0 /* DISABLED */ - /* - * Unlock ME in recovery mode. - */ - if (vboot_recovery_mode_enabled()) { - /* Unlock ME flash region */ - mkhi_hmrfpo_enable(); - - /* Issue global reset */ - mkhi_global_reset(); - return; - } -#endif - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { me_print_fw_version(&mbp_data.fw_version_name); me_print_fwcaps(&mbp_data.fw_caps_sku);